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2017-09-26drm/amd/display: dce80, 100, 110 and 112 to dce ipp refactorDmytro Laktyushkin15-848/+171
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/display: dce120 to dce ipp refactorDmytro Laktyushkin14-525/+521
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/display: clarify delay param for REG_WAITTony Cheng1-2/+2
Signed-off-by: Tony Cheng <tony.cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/display: move tg_color to dc_hw_typesTony Cheng2-18/+6
Signed-off-by: Tony Cheng <tony.cheng@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/display: PSR RefactorSylvia Tsai11-150/+93
- Refacotr PSR to follow correct module pattern - fix eDP only working on sink index 0. Signed-off-by: Sylvia Tsai <sylvia.tsai@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/display: Make dc_link param const in set_drive_settingsZeyu Fan2-2/+2
Signed-off-by: Zeyu Fan <Zeyu.Fan@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/display: improve cursor programming reliabilityDmytro Laktyushkin7-41/+32
This change will cache cursor attributes and reprogram them when enabling cursor after power gating if the attributes were not yet reprogrammed Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/display: USB-c DP-HDMI dongle shows garbage on Sony TVCharlene Liu4-4/+47
Signed-off-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/display: Make sure v_total_min and max not less than v_total.Yongqiang Sun3-4/+16
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/display: always retrieve PSR capAmy Zhang1-2/+1
Signed-off-by: Amy Zhang <Amy.Zhang@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/display: fix memory leakDmytro Laktyushkin1-14/+12
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/display: set correct v_total_min and v_total_max for dce.Yongqiang Sun2-4/+4
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/display: remove unnecessary allocation for regamma_params inside oppDmytro Laktyushkin4-17/+5
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/display: Fix memory leak in post_update_surfacesHarry Wentland1-2/+5
Signed-off-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/display: Block YCbCr formats for eDP. Revert previous change.Zeyu Fan1-2/+6
Signed-off-by: Zeyu Fan <Zeyu.Fan@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/display: make dc_commit_surfaces_to_stream() re-entrantShirish S1-27/+44
dc_commit_surfaces_to_stream() function currently is handle's only one plane at a time. This will not work if multiple planes have to be set to a crtc. The functionality of dc_commit_surfaces_to_stream() with this patch is slit into 1. Accumulate and initialise all the surfaces that needs to be set to a crtc. 2. Update the intialised set of surfaces to the steam in one go. Hence dc_commit_surfaces_to_stream() is renamed to init_surfaces(). Once all the planes requested by user space are initialised, dc_commit_surfaces_to_stream() shall sequentially populates *updates, *flip_addr, *plane_info and *scaling_info for all surfaces. BUG: SWDEV-119421 TEST: (On Chromium OS for Stoney Only) * Chromium UI comes up, on both eDP & DP. * 'new_surface_count' now changes as per user input for e.g for all below run tests its 2, without this patch for the below tests it used to be 1 * Executed below tests to see YUV(underlay) & RGB planes on eDP plane_test --format XR24 --size 500x100 -p --format YV12 --size 500x500 plane_test --format AR24 --size 500x50 -p --format YV12 --size 150x150 plane_test --format AR24 --size 500x50 -p --format YV12 --size 1366x768 Signed-off-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Shirish S <shirish.s@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/display: update the YUV plane offsetsShirish S1-7/+7
This patch updates the planes default offsets to the appropriate ones, and aligns the pitch to 64 bits. BUG=SWDEV-119421 TEST=Boots to UI on jadeite TEST= plane_test --format AR24 --size 500x50 -p --format YV12 --size 500x500 plane_test --format AR24 --size 500x50 -p --format YV12 --size 1280x720 plane_test --format AR24 --size 500x50 -p --format YV12 --size 1366x768 Signed-off-by: Shirish S <shirish.s@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/display: initialize YUV plane capabilitiesShirish S1-17/+45
This patch populates the YUV surface configurations. Tests: (On Chromium OS for Stoney Only) builds without any errors. Signed-off-by: Shirish S <shirish.s@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/display: Return context from validate_contextHarry Wentland3-15/+52
This will allow us to carry it from check to commit Signed-off-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/display: Move resource_validate_ctx_destruct to dc.hHarry Wentland4-19/+19
This will be needed to clean up context once we add it to private atomic state. Signed-off-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/display: Copy ctx to current_context instead of assignHarry Wentland1-5/+4
Signed-off-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/display: pull commit_surfaces out of atomic_commit into helper functionHarry Wentland1-51/+62
This should make things simpler when we try to rework this later when we pass validate_context from atomic_check to atomic_commit. Signed-off-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/display: update dce8 & 10 bw programmingDmytro Laktyushkin6-41/+21
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Jordan Lazare <Jordan.Lazare@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/display: Get rid of temp_flip_contextHarry Wentland2-14/+13
If we need to update our context we can allocate memory. No need to keep temporary memory for this. Signed-off-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/display: Remove unused scratch_val_ctxHarry Wentland2-4/+0
Signed-off-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/display: FreeSync LFC MIN/MAX update on current frameEric Cook1-28/+39
- Update BTR/LFC logic so that V_TOTAL_MIN/MAX will take affect on current frame - Add in FreeSync update to MPO code path Signed-off-by: Eric Cook <Eric.Cook@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/display: Add support for programming stereo syncVitaly Prosyak6-5/+49
Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/display: Parse scanline registersSylvia Tsai7-66/+89
They could differ between ASIC generations Signed-off-by: Sylvia Tsai <sylvia.tsai@amd.com> Signed-off-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/display: use full surface update when stream is NULLCharlene Liu2-3/+3
Signed-off-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/display: Fix missing irq refactor causing potential i2c raceJordan Lazare1-5/+10
Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/display: Fix for tile MSTDing Wang4-0/+21
- Set stream signal type to be SST when setting non-tile timing on MST tiled display. - Disable MST on sink after disabling MST link. - Enable MST on sink before enabling MST link. Signed-off-by: Ding Wang <Ding.Wang@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/display: set NULL value during removal for remoteSinkLeon Elazar1-1/+1
In MST case during removal of remote sink its descriptor pointer wasn't freed corectly. Signed-off-by: Leon Elazar <leon.elazar@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/display: change mpo surface update check condition.Yongqiang Sun1-5/+11
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/display: Add same check as reset pipes for programing backend regs.Yongqiang Sun1-0/+4
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/display: Adding dm controlled signal type in dc_streamSylvia Tsai2-15/+16
- Adding dm controlled signal type in dc_stream - Adding fallback to dvi signal when output signal is hdmi and the connector type is not Signed-off-by: Sylvia Tsai <sylvia.tsai@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Sylvia Tsai <Sylvia.Tsai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/display: Memory was freed twice during disableLeon Elazar1-1/+0
1. get_ss_info_from_atombios function was allocating the memory populating the provided pointer but them freeing the memory. Since the pointer was return as a valid value, we are trying to free the same memory during clock resource destruction Signed-off-by: Leon Elazar <leon.elazar@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/display: Fix hotspot programming during set cursor position.Zeyu Fan4-30/+8
- Remove x,y hotspot from dc_cursor_attributes. Only program it through setPosition. Signed-off-by: Zeyu Fan <Zeyu.Fan@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Zeyu Fan <Zeyu.Fan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/display: adding FCLK and DPPCLK clock typesCharlene Liu1-1/+3
Signed-off-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/display: Prevent premature pageflip when comitting in vblank. (v3)Mario Kleiner1-10/+10
Make sure we do not program a hw pageflip inside vblank 'n' iff the atomic flip is comitted while inside the same vblank 'n'. We must defer such a flip by one refresh cycle to vblank 'n+1', unless this is a DRM_MODE_PAGE_FLIP_ASYNC async pageflip, which must always execute as soon as possible. Without this, pageflips programmed via X11 GLX_OML_sync_control extensions glXSwapBuffersMscOML(..., target_msc, ...); call and/or via DRI3/Present PresentPixmap(..., target_msc, ...); request will complete one vblank too early whenever target_msc > current_msc + 1, ie. more than 1 vblank in the future. In such a case, the call of the pageflip ioctl() would be triggered by a queued drmWaitVblank() vblank event, which itself gets dispatched inside the vblank one frame before the target_msc vblank. Testing with this patch does no longer show any problems with OML_sync_control swap scheduling or flip completion timestamps. Tested on R9 380 Tonga. v2: Add acked/r-b by Harry and Michel. v3: Feedback from Andrey: Must not wait an extra frame for DRM_MODE_PAGE_FLIP_ASYNC flips. Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com> Acked-by: Harry Wentland <harry.wentland@amd.com> (v1) Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com> Cc: Harry Wentland <Harry.Wentland@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/display: Fix race between vblank irq and pageflip irq. (v2)Mario Kleiner1-0/+3
Since DC now uses CRTC_VERTICAL_INTERRUPT0 as VBLANK irq trigger and vblank interrupts actually happen earliest at start of vblank, instead of a bit before vblank, we no longer need some of the fudging logic to deal with too early vblank irq handling (grep for lb_vblank_lead_lines). This itself fixes a pageflip scheduling bug in DC, caused by uninitialized use of lb_vblank_lead_lines, with a wrong startup value of 0. Thanks to the new vblank irq trigger this value of zero is now actually correct for DC :). A new problem is that vblank irq's race against pflip irq's, and as both can fire at first line of vblank, it is no longer guaranteed that vblank irq handling (therefore -> drm_handle_vblank() -> drm_update_vblank_count()) executes before pflip irq handling for a given vblank interval when a pageflip completes. Therefore the vblank count and timestamps emitted to user-space as part of the pageflip completion event will be often stale and cause new timestamping and swap scheduling errors in user-space. This was observed with large frequency on R9 380 Tonga Pro. Fix this by enforcing a vblank count+timestamp update right before emitting the pageflip completion event from the pflip irq handler. The logic in core drm_update_vblank_count() makes sure that no redundant or conflicting updates happen, iow. the call turns into a no-op if it wasn't needed for that vblank, burning a few microseconds of cpu time though. Successfully tested on AMD R9 380 "Tonga Pro" (VI/DCE 10) with DC enabled on the current DC staging branch. Independent measurement of pageflip completion timing with special hardware measurement equipment now confirms correct pageflip timestamps and counts in the pageflip completion events. v2: Review comments by Michel, drop outdated paragraph about problem already fixed in 2nd patch of the series. Add acked/r-b by Harry and Michel. Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com> Acked-by: Harry Wentland <harry.wentland@amd.com> (v1) Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Cc: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/display: get_atomic_property missing for drm_connector_funcsPratik Vishwakarma2-38/+49
DRM_IOCTL_MODE_GETCONNECTOR fails with EINVAL on enabling DRIVER_ATOMIC With this DRM_IOCTL_MODE_GETCONNECTOR returns all the connector properties. freesync_property and freesync_capable_property return 0 currently. TESTS(On Chromium OS on Stoney Only) * Builds without compilation errors. * 'atomictest' proceeds after applying patch and fails with vblank event timed out. * Chromium OS ui comes up. Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/display: Fallback on legacy properties in atomic_get_propertiesHarry Wentland1-1/+39
We still rely on legacy properties. Fallback on legacy properties until we get to pull these into some atomic state. Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/display: Allow planes on all crtcsHarry Wentland1-1/+1
4.9 kernel will always add the assigned crtc to possible_crtcs on a plane. This is no longer the case on newer kernels. Make sure we allow any plane on any crtc. Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/display: fix nullptr on vega initializationAlex Deucher1-0/+1
Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/display: Fix s3 hang on resume.Andrey Grodzovsky3-7/+13
Avoid enabling CRTC_VERTICAL_INTERRUPT0 twice on resume. It's enabled once from within manage_dm_interrupts in mode set and another explicitly from amdgpu_dm_irq_resume_late. Seems it lead to CRTC hang. Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/display: Log clock source in error conditionJordan Lazare1-1/+2
Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/display: Ignore visible flag when check surface update type.Yongqiang Sun1-1/+1
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/display: Fill in vrefresh and min_vblank_time for dce8/dce10Jordan Lazare5-4/+40
PPLib is now calling into DC to get vrefresh and min_vblank_time, but since full bandwidth calcs are missing for those generations, the pplib structures were never being filled. This change fills the currently required fields to prevent screen corruption. Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Jordan Lazare <Jordan.Lazare@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/display: PSR Aux Channel and Static Screen Support FixAmy Zhang1-2/+0
- Correct the aux channel selection according to DAL3 Signed-off-by: Amy Zhang <Amy.Zhang@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/display: Refactor edid read.Andrey Grodzovsky15-465/+254
Allow Linux to use DRM provided EDID read functioality by moving DAL edid implementation to module hence removing this code from DC by this cleaning up DC code for upstream. v2: Removing ddc_service. No more need for it. Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-06-14 04:41:28 +0000