diff options
Diffstat (limited to 'drivers/gpu/drm')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c | 5 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c | 6 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c | 6 |
3 files changed, 5 insertions, 12 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c index f2dd98d3f5e6..37098c68a645 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c @@ -654,11 +654,6 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device, else strcpy(fw_name, "amdgpu/vega10_smc.bin"); break; - case CHIP_CARRIZO: - case CHIP_STONEY: - case CHIP_RAVEN: - adev->pm.fw_version = info->version; - return 0; default: DRM_ERROR("SMC firmware not supported\n"); return -EINVAL; diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c index bef0b2dcac9a..bc53f2beda30 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c @@ -247,13 +247,11 @@ static int smu10_smu_fini(struct pp_hwmgr *hwmgr) static int smu10_start_smu(struct pp_hwmgr *hwmgr) { - struct cgs_firmware_info info = {0}; + struct amdgpu_device *adev = hwmgr->adev; smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetSmuVersion); hwmgr->smu_version = smu10_read_arg_from_smc(hwmgr); - info.version = hwmgr->smu_version >> 8; - - cgs_get_firmware_info(hwmgr->device, CGS_UCODE_ID_SMU, &info); + adev->pm.fw_version = hwmgr->smu_version >> 8; if (smu10_verify_smc_interface(hwmgr)) return -EINVAL; diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c index 480deb2ce448..8c49704b81af 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c @@ -698,7 +698,8 @@ static int smu8_start_smu(struct pp_hwmgr *hwmgr) { int ret = 0; uint32_t fw_to_check = 0; - struct cgs_firmware_info info = {0}; + struct amdgpu_device *adev = hwmgr->adev; + uint32_t index = SMN_MP1_SRAM_START_ADDR + SMU8_FIRMWARE_HEADER_LOCATION + offsetof(struct SMU8_Firmware_Header, Version); @@ -709,8 +710,7 @@ static int smu8_start_smu(struct pp_hwmgr *hwmgr) cgs_write_register(hwmgr->device, mmMP0PUB_IND_INDEX, index); hwmgr->smu_version = cgs_read_register(hwmgr->device, mmMP0PUB_IND_DATA); - info.version = hwmgr->smu_version >> 8; - cgs_get_firmware_info(hwmgr->device, CGS_UCODE_ID_SMU, &info); + adev->pm.fw_version = hwmgr->smu_version >> 8; fw_to_check = UCODE_ID_RLC_G_MASK | UCODE_ID_SDMA0_MASK | |