diff options
Diffstat (limited to 'drivers/gpu/drm/amd/powerplay')
34 files changed, 4218 insertions, 118 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/Makefile b/drivers/gpu/drm/amd/powerplay/Makefile index 043e6ebab575..4e132b936e3d 100644 --- a/drivers/gpu/drm/amd/powerplay/Makefile +++ b/drivers/gpu/drm/amd/powerplay/Makefile @@ -1,5 +1,5 @@ -subdir-ccflags-y += -Iinclude/drm \ +subdir-ccflags-y += \ -I$(FULL_AMD_PATH)/powerplay/inc/ \ -I$(FULL_AMD_PATH)/include/asic_reg \ -I$(FULL_AMD_PATH)/include \ diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventmgr.c b/drivers/gpu/drm/amd/powerplay/eventmgr/eventmgr.c index 781e53dcf128..3e3ca03bd344 100644 --- a/drivers/gpu/drm/amd/powerplay/eventmgr/eventmgr.c +++ b/drivers/gpu/drm/amd/powerplay/eventmgr/eventmgr.c @@ -42,8 +42,8 @@ static int pem_init(struct pp_eventmgr *eventmgr) /* Call initialization event */ result = pem_handle_event(eventmgr, AMD_PP_EVENT_INITIALIZE, &event_data); - if (0 != result) - return result; + /* if (0 != result) + return result; */ /* Register interrupt callback functions */ result = pem_register_interrupts(eventmgr); diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile index 27db2b77824f..f0277c16c2bf 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile @@ -9,8 +9,7 @@ HARDWARE_MGR = hwmgr.o processpptables.o functiontables.o \ smu7_hwmgr.o smu7_powertune.o smu7_thermal.o \ smu7_clockpowergating.o \ vega10_processpptables.o vega10_hwmgr.o vega10_powertune.o \ - vega10_thermal.o - + vega10_thermal.o pp_overdriver.o rv_hwmgr.o AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR)) diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c index 7aa5ca815a3a..0b74da3dca8b 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c @@ -1224,6 +1224,12 @@ static int cz_hwmgr_backend_fini(struct pp_hwmgr *hwmgr) phm_destroy_table(hwmgr, &(hwmgr->disable_dynamic_state_management)); phm_destroy_table(hwmgr, &(hwmgr->power_down_asic)); phm_destroy_table(hwmgr, &(hwmgr->setup_asic)); + + if (NULL != hwmgr->dyn_state.vddc_dep_on_dal_pwrl) { + kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl); + hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL; + } + kfree(hwmgr->backend); hwmgr->backend = NULL; } diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c index ff4ae3de6bb6..d025653c7823 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c @@ -22,10 +22,10 @@ */ #include "pp_debug.h" -#include "linux/delay.h" -#include <linux/types.h> +#include <linux/delay.h> #include <linux/kernel.h> #include <linux/slab.h> +#include <linux/types.h> #include <drm/amdgpu_drm.h> #include "cgs_common.h" #include "power_state.h" @@ -115,6 +115,15 @@ int hwmgr_early_init(struct pp_instance *handle) return -EINVAL; } break; + case AMDGPU_FAMILY_RV: + switch (hwmgr->chip_id) { + case CHIP_RAVEN: + rv_init_function_pointers(hwmgr); + break; + default: + return -EINVAL; + } + break; default: return -EINVAL; } diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_acpi.c b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_acpi.c index f5e8fda964f7..f6b4dd96c0ec 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_acpi.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_acpi.c @@ -21,8 +21,8 @@ * */ +#include <linux/delay.h> #include <linux/errno.h> -#include "linux/delay.h" #include "hwmgr.h" #include "amd_acpi.h" #include "pp_acpi.h" diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.c b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.c new file mode 100644 index 000000000000..d09f25485844 --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.c @@ -0,0 +1,1276 @@ +#include "pp_overdriver.h" +#include <linux/errno.h> + +struct phm_fuses_default vega10_fuses_default[] = { + {"0000001000010011111010101001010011011110000011100100100101100100",0x00003C96,0xFFFFE226,0x00000656,0x00002203,0xFFFFF201,0x000003FF,0x00002203,0xFFFFF201,0x000003FF}, + {"0000001000010011111010101001010011011110000010100001100010000100",0x00003CC5,0xFFFFE23A,0x0000064E,0x00002258,0xFFFFF1F7,0x000003FC,0x00002258,0xFFFFF1F7,0x000003FC}, + {"0000001000010011111010101001010011011110000011100011000110100100",0x00003CAF,0xFFFFE36E,0x00000602,0x00001E98,0xFFFFF569,0x00000357,0x00001E98,0xFFFFF569,0x00000357}, + {"0000001000010011111010101001010011011110001011000001000101000100",0x0000391A,0xFFFFE548,0x000005C9,0x00001B98,0xFFFFF707,0x00000324,0x00001B98,0xFFFFF707,0x00000324}, + {"0000001000010011111010101001010011011110001011000001100011000100",0x00003821,0xFFFFE674,0x00000597,0x00002196,0xFFFFF361,0x000003C0,0x00002196,0xFFFFF361,0x000003C0}, + {"0000001000010011111010101001010011011110001001100011100010000100",0x000044A2,0xFFFFDCB7,0x00000738,0x0000325C,0xFFFFE6A7,0x000005E6,0x0000325C,0xFFFFE6A7,0x000005E6}, + {"0000001000010011111010101001010011011110000010000010100100100100",0x00004057,0xFFFFE1CF,0x0000063C,0x00002E2E,0xFFFFEB62,0x000004FD,0x00002E2E,0xFFFFEB62,0x000004FD}, + {"0000001000010011111010101001010011011110001010000100100100100100",0x00003FD0,0xFFFFDF0F,0x000006E5,0x0000267C,0xFFFFEE2D,0x000004AB,0x0000267C,0xFFFFEE2D,0x000004AB}, + {"0000001000010011111010101001010011011110001010000000100100000100",0x00003F13,0xFFFFE010,0x000006AD,0x000020E7,0xFFFFF266,0x000003EC,0x000020E7,0xFFFFF266,0x000003EC}, + {"0000001000010011111010101001010011011110000010000010000001000100",0x00004088,0xFFFFDFAB,0x000006B6,0x0000252B,0xFFFFEFDB,0x00000458,0x0000252B,0xFFFFEFDB,0x00000458}, + {"0000001000010011111010101001010011011110001010000011100010000100",0x00003EF6,0xFFFFE017,0x000006AA,0x00001F67,0xFFFFF369,0x000003BE,0x00001F67,0xFFFFF369,0x000003BE}, + {"0000001000010011111010101001010011011110001011000010000110000100",0x00003CDD,0xFFFFE2A7,0x0000063C,0x000026C6,0xFFFFEF38,0x00000478,0x000026C6,0xFFFFEF38,0x00000478}, + {"0000001000010011111010101001010011011110000100000101000100100100",0x00003FA8,0xFFFFDF02,0x000006F0,0x000027FE,0xFFFFECF6,0x000004EA,0x000027FE,0xFFFFECF6,0x000004EA}, + {"0000001000010011111010101001010011011110001001100011100011000100",0x00004670,0xFFFFDC40,0x00000742,0x00003A7A,0xFFFFE1A7,0x000006B6,0x00003A7A,0xFFFFE1A7,0x000006B6}, + {"0000001000010011111010101001010011011110001011000011000000100100",0x00003CDC,0xFFFFE18C,0x00000683,0x00002A69,0xFFFFEBE7,0x00000515,0x00002A69,0xFFFFEBE7,0x00000515}, + {"0000001000010011111010101001010011011110000011100011100011000100",0x00003CEC,0xFFFFE38E,0x00000601,0x00002752,0xFFFFEFA7,0x00000453,0x00002752,0xFFFFEFA7,0x00000453}, + {"0000001000010011111010101001010011011110001011000001000100100100",0x000037D0,0xFFFFE634,0x000005A7,0x00001CD2,0xFFFFF644,0x00000348,0x00001CD2,0xFFFFF644,0x00000348}, + {"0000001000010011111010101001010011011110001010000011100101100100",0x00003DF5,0xFFFFE0A5,0x00000698,0x00001FD5,0xFFFFF30E,0x000003D1,0x00001FD5,0xFFFFF30E,0x000003D1}, + {"0000001000010011111010101001010011011110000010000010100011000100",0x00004201,0xFFFFE03E,0x00000688,0x00003206,0xFFFFE852,0x0000058A,0x00003206,0xFFFFE852,0x0000058A}, + {"0000001000010011111010101001010011011110001011000001100001100100",0x00003BED,0xFFFFE2F5,0x00000638,0x0000270D,0xFFFFEED0,0x0000048E,0x0000270D,0xFFFFEED0,0x0000048E}, + {"0000001000010011111010101001010011011110000010100001100100000100",0x00003E82,0xFFFFE1BE,0x00000654,0x000025FB,0xFFFFEFFA,0x00000448,0x000025FB,0xFFFFEFFA,0x00000448}, + {"0000001000010011111010101001010011011110001011000100000011000100",0x00003962,0xFFFFE4B9,0x000005EF,0x00002385,0xFFFFF156,0x00000423,0x00002385,0xFFFFF156,0x00000423}, + {"0000001000010011111010101001010011011110001011000000100101000100",0x00003D88,0xFFFFE21A,0x00000655,0x0000295A,0xFFFFED68,0x000004C4,0x0000295A,0xFFFFED68,0x000004C4}, + {"0000001000010011111010101001010011011110001011000001000100000100",0x00003AA4,0xFFFFE4A3,0x000005E0,0x000022EF,0xFFFFF250,0x000003EB,0x000022EF,0xFFFFF250,0x000003EB}, + {"0000001000010011111010101001010011011110000011100010100110100100",0x00003D97,0xFFFFE30D,0x0000060D,0x0000205D,0xFFFFF45D,0x00000380,0x0000205D,0xFFFFF45D,0x00000380}, + {"0000001000010011111010101001010011011110001011000100000010100100",0x000039B6,0xFFFFE446,0x00000605,0x00002325,0xFFFFF16C,0x0000041F,0x00002325,0xFFFFF16C,0x0000041F}, + {"0000001000010011111010101001010011011110001001100011100100000100",0x0000457E,0xFFFFDCF6,0x00000722,0x00003972,0xFFFFE27B,0x0000068E,0x00003972,0xFFFFE27B,0x0000068E}, + {"0000001000010011111010101001010011011110000010100001100100100100",0x00003FB8,0xFFFFE101,0x00000670,0x00002787,0xFFFFEEF5,0x00000471,0x00002787,0xFFFFEEF5,0x00000471}, + {"0000001000010011111010101001010011011110000011100011100010100100",0x00003BB2,0xFFFFE430,0x000005EA,0x000024A5,0xFFFFF162,0x00000409,0x000024A5,0xFFFFF162,0x00000409}, + {"0000001000010011111010101001010011011110000010000010000101000100",0x00003EC5,0xFFFFE1BD,0x0000064F,0x000022F0,0xFFFFF227,0x000003E8,0x000022F0,0xFFFFF227,0x000003E8}, + {"0000001000010011111010101001010011011110001011000011000101100100",0x000038A7,0xFFFFE59F,0x000005C1,0x000021CC,0xFFFFF2DF,0x000003D9,0x000021CC,0xFFFFF2DF,0x000003D9}, + {"0000001000010011111010101001010011011110001100100100000110000100",0x00002995,0xFFFFEF7A,0x0000044C,0x00001552,0xFFFFFB5D,0x00000292,0x00001552,0xFFFFFB5D,0x00000292}, + {"0000001000010011111010101001010011011110001011000100000001100100",0x00003B26,0xFFFFE2D3,0x00000649,0x000023B4,0xFFFFF09B,0x00000449,0x000023B4,0xFFFFF09B,0x00000449}, + {"0000001000010011111010101001010011011110000010000001000100100100",0x000040D2,0xFFFFE00A,0x00000696,0x000022DA,0xFFFFF1E9,0x000003F2,0x000022DA,0xFFFFF1E9,0x000003F2}, + {"0000001000010011111010101001010011011110001011000011100100100100",0x00003C98,0xFFFFE365,0x00000618,0x00002D5D,0xFFFFEB3A,0x0000051D,0x00002D5D,0xFFFFEB3A,0x0000051D}, + {"0000001000010011111010101001010011011110001011000001000010100100",0x00003BBD,0xFFFFE37E,0x00000617,0x0000252E,0xFFFFF06E,0x00000441,0x0000252E,0xFFFFF06E,0x00000441}, + {"0000001000010011111010101001010011011110001001100010100100100100",0x00004363,0xFFFFDF7A,0x000006A0,0x000031F5,0xFFFFE880,0x0000057B,0x000031F5,0xFFFFE880,0x0000057B}, + {"0000001000010011111010101001010011011110000011100011100001000100",0x00003CFC,0xFFFFE2AF,0x0000062E,0x0000212A,0xFFFFF335,0x000003BF,0x0000212A,0xFFFFF335,0x000003BF}, + {"0000001000010011111010101001010011011110000111000100100100100100",0x0000252D,0xFFFFF31B,0x000003C3,0x00001A1A,0xFFFFF882,0x00000325,0x00001A1A,0xFFFFF882,0x00000325}, + {"0000001000010011111010101001010011011110000010100010100110100100",0x00003FE2,0xFFFFDFEF,0x000006AC,0x000025A2,0xFFFFEF84,0x00000462,0x000025A2,0xFFFFEF84,0x00000462}, + {"0000001000010011111010101001010011011110000010000010000011100100",0x000040A5,0xFFFFE13B,0x0000065B,0x00002C13,0xFFFFEC75,0x000004D7,0x00002C13,0xFFFFEC75,0x000004D7}, + {"0000001000010011111010101001010011011110000011100100100010100100",0x00003E42,0xFFFFE1B3,0x00000657,0x0000221D,0xFFFFF273,0x000003DE,0x0000221D,0xFFFFF273,0x000003DE}, + {"0000001000010011111010101001010011011110000010100010000011100100",0x00003E7F,0xFFFFE255,0x00000638,0x00002D30,0xFFFFEB8A,0x00000503,0x00002D30,0xFFFFEB8A,0x00000503}, + {"0000001000010011111010101001010011011110001011000010100111000100",0x00003E56,0xFFFFE16D,0x00000670,0x000028DC,0xFFFFEDA0,0x000004BA,0x000028DC,0xFFFFEDA0,0x000004BA}, + {"0000001000010011111010101001010011011110001001100011000010100100",0x000044AD,0xFFFFDE24,0x000006DD,0x000031AD,0xFFFFE850,0x00000585,0x000031AD,0xFFFFE850,0x00000585}, + {"0000001000010011111010101001010011011110001011000010000011100100",0x00003AF3,0xFFFFE5B0,0x000005A6,0x00002CF6,0xFFFFEC75,0x000004DD,0x00002CF6,0xFFFFEC75,0x000004DD}, + {"0000001000010011111010101001010011011110000010100010000010000100",0x00003E66,0xFFFFE19E,0x0000065B,0x00002332,0xFFFFF1B9,0x000003FD,0x00002332,0xFFFFF1B9,0x000003FD}, + {"0000001000010011111010101001010011011110000010000010100010000100",0x00003FB4,0xFFFFE0A5,0x00000686,0x0000253E,0xFFFFF02E,0x00000444,0x0000253E,0xFFFFF02E,0x00000444}, + {"0000001000010011111010101001010011011110001010000001100010100100",0x00003E28,0xFFFFE14D,0x0000066E,0x00001FE2,0xFFFFF39A,0x000003B1,0x00001FE2,0xFFFFF39A,0x000003B1}, + {"0000001000010011111010101001010011011110001011000000100100000100",0x000039E6,0xFFFFE44B,0x000005FE,0x0000210C,0xFFFFF2F4,0x000003DA,0x0000210C,0xFFFFF2F4,0x000003DA}, + {"0000001000010011111010101001010011011110001011000101000100000100",0x00003A4D,0xFFFFE252,0x0000067A,0x000027E2,0xFFFFECED,0x000004FA,0x000027E2,0xFFFFECED,0x000004FA}, + {"0000001000010011111010101001010011011110000010100010100101100100",0x00004065,0xFFFFE02F,0x0000069B,0x0000299D,0xFFFFED38,0x000004C2,0x0000299D,0xFFFFED38,0x000004C2}, + {"0000001000010011111010101001010011011110000011100010000010100100",0x000039EE,0xFFFFE603,0x00000594,0x0000214F,0xFFFFF429,0x0000038E,0x0000214F,0xFFFFF429,0x0000038E}, + {"0000001000010011111010101001010011011110000011100100100011100100",0x00003BD2,0xFFFFE351,0x00000618,0x000020B8,0xFFFFF377,0x000003B4,0x000020B8,0xFFFFF377,0x000003B4}, + {"0000001000010011111010101001010011011110000010100011000100100100",0x00003FAA,0xFFFFE183,0x0000065E,0x000032AE,0xFFFFE7C2,0x000005A6,0x000032AE,0xFFFFE7C2,0x000005A6}, + {"0000001000010011111010101001010011011110001011000010100110000100",0x00003AFB,0xFFFFE3E4,0x00000608,0x00002293,0xFFFFF21F,0x000003FA,0x00002293,0xFFFFF21F,0x000003FA}, + {"0000001000010011111010101001010011011110001001100010000001100100",0x0000448B,0xFFFFDD5D,0x0000070D,0x00002E4E,0xFFFFE9DF,0x00000551,0x00002E4E,0xFFFFE9DF,0x00000551}, + {"0000001000010011111010101001010011011110000011100010000110000100",0x00003D46,0xFFFFE39B,0x000005F3,0x0000218E,0xFFFFF3CD,0x00000398,0x0000218E,0xFFFFF3CD,0x00000398}, + {"0000001000010011111010101001010011011110000010000100100011100100",0x00003F01,0xFFFFDFD9,0x000006BF,0x000023AF,0xFFFFF04E,0x0000044C,0x000023AF,0xFFFFF04E,0x0000044C}, + {"0000001000010011111010101001010011011110000100000010100110100100",0x0000403D,0xFFFFDF6B,0x000006C9,0x0000270D,0xFFFFEE4B,0x0000049E,0x0000270D,0xFFFFEE4B,0x0000049E}, + {"0000001000010011111010101001010011011110000011100011100101100100",0x00003C11,0xFFFFE35C,0x00000613,0x000020F9,0xFFFFF365,0x000003B9,0x000020F9,0xFFFFF365,0x000003B9}, + {"0000001000010011111010101001010011011110001011000011100010000100",0x00003B58,0xFFFFE37D,0x0000061F,0x00002698,0xFFFFEF46,0x00000478,0x00002698,0xFFFFEF46,0x00000478}, + {"0000001000010011111010101001010011011110001010000100000110100100",0x00003EBC,0xFFFFDF7A,0x000006D6,0x0000212B,0xFFFFF195,0x0000041B,0x0000212B,0xFFFFF195,0x0000041B}, + {"0000001000010011111010101001010011011110000010000100100011000100",0x00004050,0xFFFFDEB3,0x000006FE,0x00002D6C,0xFFFFE961,0x00000582,0x00002D6C,0xFFFFE961,0x00000582}, + {"0000001000010011111010101001010011011110001001100010000001000100",0x000043F0,0xFFFFDD9C,0x00000702,0x00002B31,0xFFFFEBEA,0x000004F7,0x00002B31,0xFFFFEBEA,0x000004F7}, + {"0000001000010011111010101001010011011110000100000000100100100100",0x00003EFA,0xFFFFE093,0x00000696,0x000026DB,0xFFFFEEB3,0x00000489,0x000026DB,0xFFFFEEB3,0x00000489}, + {"0000001000010011111010101001010011011110000010000010000001100100",0x0000425D,0xFFFFDE8D,0x000006E6,0x00002CA4,0xFFFFEAD2,0x00000531,0x00002CA4,0xFFFFEAD2,0x00000531}, + {"0000001000010011111010101001010011011110001001100011100110100100",0x000043B0,0xFFFFDD03,0x00000728,0x00002946,0xFFFFECA6,0x000004DE,0x00002946,0xFFFFECA6,0x000004DE}, + {"0000001000010011111010101001010011011110001010000010100001100100",0x00003F6A,0xFFFFE03A,0x0000069D,0x00002208,0xFFFFF1F8,0x000003F6,0x00002208,0xFFFFF1F8,0x000003F6}, + {"0000001000010011111010101001010011011110001011000010100101100100",0x00003A94,0xFFFFE4A7,0x000005E2,0x000024D0,0xFFFFF100,0x00000426,0x000024D0,0xFFFFF100,0x00000426}, + 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i++) { + temp = list[i].key; + temp_serial_numer = 0; + do { + bit = *temp=='1'? 1 : 0; + temp_serial_numer = (temp_serial_numer <<1 ) | bit; + temp++; + } while (*temp); + + if (key == temp_serial_numer) { + result->key = list[i].key; + result->VFT2_m1 = list[i].VFT2_m1; + result->VFT2_m2 = list[i].VFT2_m2; + result->VFT2_b = list[i].VFT2_b; + result->VFT1_m1 = list[i].VFT1_m1; + result->VFT1_m2 = list[i].VFT1_m2; + result->VFT1_b = list[i].VFT1_b; + result->VFT0_m1 = list[i].VFT0_m1; + result->VFT0_m2 = list[i].VFT0_m2; + result->VFT0_b = list[i].VFT0_b; + return 0; + } + } + + return -EINVAL; +} diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.h b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.h new file mode 100644 index 000000000000..6e8f7a2119c1 --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.h @@ -0,0 +1,48 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef _PP_OVERDRIVER_H_ +#define _PP_OVERDRIVER_H_ + +#include <linux/types.h> +#include <linux/kernel.h> + +struct phm_fuses_default { + const char *key; + uint32_t VFT2_m1; + uint32_t VFT2_m2; + uint32_t VFT2_b; + uint32_t VFT1_m1; + uint32_t VFT1_m2; + uint32_t VFT1_b; + uint32_t VFT0_m1; + uint32_t VFT0_m2; + uint32_t VFT0_b; +}; + +extern struct phm_fuses_default vega10_fuses_default[]; +extern int pp_override_get_default_fuse_value(uint64_t key, + struct phm_fuses_default list[], + struct phm_fuses_default *result); + +#endif
\ No newline at end of file diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c index 56023114ad6f..720d5006ff62 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c @@ -315,13 +315,13 @@ int pp_atomfwctrl_get_avfs_information(struct pp_hwmgr *hwmgr, param->ulGbFuseTableCksoffM1 = le32_to_cpu(profile->avfsgb_fuse_table_cksoff_m1); param->ulGbFuseTableCksoffM2 = - le16_to_cpu(profile->avfsgb_fuse_table_cksoff_m2); + le32_to_cpu(profile->avfsgb_fuse_table_cksoff_m2); param->ulGbFuseTableCksoffB = le32_to_cpu(profile->avfsgb_fuse_table_cksoff_b); param->ulGbFuseTableCksonM1 = le32_to_cpu(profile->avfsgb_fuse_table_ckson_m1); param->ulGbFuseTableCksonM2 = - le16_to_cpu(profile->avfsgb_fuse_table_ckson_m2); + le32_to_cpu(profile->avfsgb_fuse_table_ckson_m2); param->ulGbFuseTableCksonB = le32_to_cpu(profile->avfsgb_fuse_table_ckson_b); @@ -335,25 +335,25 @@ int pp_atomfwctrl_get_avfs_information(struct pp_hwmgr *hwmgr, param->ulDispclk2GfxclkM1 = le32_to_cpu(profile->dispclk2gfxclk_a); param->ulDispclk2GfxclkM2 = - le16_to_cpu(profile->dispclk2gfxclk_b); + le32_to_cpu(profile->dispclk2gfxclk_b); param->ulDispclk2GfxclkB = le32_to_cpu(profile->dispclk2gfxclk_c); param->ulDcefclk2GfxclkM1 = le32_to_cpu(profile->dcefclk2gfxclk_a); param->ulDcefclk2GfxclkM2 = - le16_to_cpu(profile->dcefclk2gfxclk_b); + le32_to_cpu(profile->dcefclk2gfxclk_b); param->ulDcefclk2GfxclkB = le32_to_cpu(profile->dcefclk2gfxclk_c); param->ulPixelclk2GfxclkM1 = le32_to_cpu(profile->pixclk2gfxclk_a); param->ulPixelclk2GfxclkM2 = - le16_to_cpu(profile->pixclk2gfxclk_b); + le32_to_cpu(profile->pixclk2gfxclk_b); param->ulPixelclk2GfxclkB = le32_to_cpu(profile->pixclk2gfxclk_c); param->ulPhyclk2GfxclkM1 = le32_to_cpu(profile->phyclk2gfxclk_a); param->ulPhyclk2GfxclkM2 = - le16_to_cpu(profile->phyclk2gfxclk_b); + le32_to_cpu(profile->phyclk2gfxclk_b); param->ulPhyclk2GfxclkB = le32_to_cpu(profile->phyclk2gfxclk_c); @@ -388,11 +388,33 @@ int pp_atomfwctrl_get_gpio_information(struct pp_hwmgr *hwmgr, return 0; } +int pp_atomfwctrl__get_clk_information_by_clkid(struct pp_hwmgr *hwmgr, BIOS_CLKID id, uint32_t *frequency) +{ + struct atom_get_smu_clock_info_parameters_v3_1 parameters; + struct atom_get_smu_clock_info_output_parameters_v3_1 *output; + uint32_t ix; + + parameters.clk_id = id; + parameters.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ; + + ix = GetIndexIntoMasterCmdTable(getsmuclockinfo); + if (!cgs_atom_exec_cmd_table(hwmgr->device, ix, ¶meters)) { + output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)¶meters; + *frequency = output->atom_smu_outputclkfreq.smu_clock_freq_hz / 10000; + } else { + pr_info("Error execute_table getsmuclockinfo!"); + return -1; + } + + return 0; +} + int pp_atomfwctrl_get_vbios_bootup_values(struct pp_hwmgr *hwmgr, struct pp_atomfwctrl_bios_boot_up_values *boot_values) { struct atom_firmware_info_v3_1 *info = NULL; uint16_t ix; + uint32_t frequency = 0; ix = GetIndexIntoMasterDataTable(firmwareinfo); info = (struct atom_firmware_info_v3_1 *) @@ -407,11 +429,18 @@ int pp_atomfwctrl_get_vbios_bootup_values(struct pp_hwmgr *hwmgr, boot_values->ulRevision = info->firmware_revision; boot_values->ulGfxClk = info->bootup_sclk_in10khz; boot_values->ulUClk = info->bootup_mclk_in10khz; - boot_values->ulSocClk = 0; boot_values->usVddc = info->bootup_vddc_mv; boot_values->usVddci = info->bootup_vddci_mv; boot_values->usMvddc = info->bootup_mvddc_mv; boot_values->usVddGfx = info->bootup_vddgfx_mv; + boot_values->ulSocClk = 0; + boot_values->ulDCEFClk = 0; + + if (!pp_atomfwctrl__get_clk_information_by_clkid(hwmgr, SMU9_SYSPLL0_SOCCLK_ID, &frequency)) + boot_values->ulSocClk = frequency; + + if (!pp_atomfwctrl__get_clk_information_by_clkid(hwmgr, SMU9_SYSPLL0_DCEFCLK_ID, &frequency)) + boot_values->ulDCEFClk = frequency; return 0; }
\ No newline at end of file diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h index 43a6711e3c06..81908b5cfd5f 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h @@ -26,6 +26,8 @@ #include "hwmgr.h" +typedef enum atom_smu9_syspll0_clock_id BIOS_CLKID; + #define GetIndexIntoMasterCmdTable(FieldName) \ (((char*)(&((struct atom_master_list_of_command_functions_v2_1*)0)->FieldName)-(char*)0)/sizeof(uint16_t)) #define GetIndexIntoMasterDataTable(FieldName) \ @@ -125,6 +127,7 @@ struct pp_atomfwctrl_bios_boot_up_values { uint32_t ulGfxClk; uint32_t ulUClk; uint32_t ulSocClk; + uint32_t ulDCEFClk; uint16_t usVddc; uint16_t usVddci; uint16_t usMvddc; diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c index ed6c934927fb..2716721e5453 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c @@ -1015,6 +1015,10 @@ static int init_overdrive_limits(struct pp_hwmgr *hwmgr, hwmgr->platform_descriptor.overdriveLimit.memoryClock = 0; hwmgr->platform_descriptor.minOverdriveVDDC = 0; hwmgr->platform_descriptor.maxOverdriveVDDC = 0; + hwmgr->platform_descriptor.overdriveVDDCStep = 0; + + if (hwmgr->chip_id == CHIP_RAVEN) + return 0; /* We assume here that fw_info is unchanged if this call fails.*/ fw_info = cgs_atom_get_data_table(hwmgr->device, @@ -1559,6 +1563,9 @@ static int pp_tables_initialize(struct pp_hwmgr *hwmgr) int result; const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table; + if (hwmgr->chip_id == CHIP_RAVEN) + return 0; + hwmgr->need_pp_table_upload = true; powerplay_table = get_powerplay_table(hwmgr); @@ -1605,6 +1612,9 @@ static int pp_tables_initialize(struct pp_hwmgr *hwmgr) static int pp_tables_uninitialize(struct pp_hwmgr *hwmgr) { + if (hwmgr->chip_id == CHIP_RAVEN) + return 0; + if (NULL != hwmgr->dyn_state.vddc_dependency_on_sclk) { kfree(hwmgr->dyn_state.vddc_dependency_on_sclk); hwmgr->dyn_state.vddc_dependency_on_sclk = NULL; diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c new file mode 100644 index 000000000000..4c7f430b36eb --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c @@ -0,0 +1,1059 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include "pp_debug.h" +#include <linux/types.h> +#include <linux/kernel.h> +#include <linux/slab.h> +#include "atom-types.h" +#include "atombios.h" +#include "processpptables.h" +#include "cgs_common.h" +#include "smumgr.h" +#include "hwmgr.h" +#include "hardwaremanager.h" +#include "rv_ppsmc.h" +#include "rv_hwmgr.h" +#include "power_state.h" +#include "rv_smumgr.h" +#include "pp_soc15.h" + +#define RAVEN_MAX_DEEPSLEEP_DIVIDER_ID 5 +#define RAVEN_MINIMUM_ENGINE_CLOCK 800 //8Mhz, the low boundary of engine clock allowed on this chip +#define SCLK_MIN_DIV_INTV_SHIFT 12 +#define RAVEN_DISPCLK_BYPASS_THRESHOLD 10000 //100mhz +#define SMC_RAM_END 0x40000 + +static const unsigned long PhwRaven_Magic = (unsigned long) PHM_Rv_Magic; +int rv_display_clock_voltage_request(struct pp_hwmgr *hwmgr, + struct pp_display_clock_request *clock_req); + +struct phm_vq_budgeting_record rv_vqtable[] = { + /* _TBD + * CUs, SSP low, SSP High, Min Sclk Low, Min Sclk, High, AWD/non-AWD, DCLK, ECLK, Sustainable Sclk, Sustainable CUs */ + { 8, 0, 45, 0, 0, VQ_DisplayConfig_NoneAWD, 80000, 120000, 4, 0 }, +}; + +static struct rv_power_state *cast_rv_ps(struct pp_hw_power_state *hw_ps) +{ + if (PhwRaven_Magic != hw_ps->magic) + return NULL; + + return (struct rv_power_state *)hw_ps; +} + +static const struct rv_power_state *cast_const_rv_ps( + const struct pp_hw_power_state *hw_ps) +{ + if (PhwRaven_Magic != hw_ps->magic) + return NULL; + + return (struct rv_power_state *)hw_ps; +} + +static int rv_init_vq_budget_table(struct pp_hwmgr *hwmgr) +{ + uint32_t table_size, i; + struct phm_vq_budgeting_table *ptable; + uint32_t num_entries = ARRAY_SIZE(rv_vqtable); + + if (hwmgr->dyn_state.vq_budgeting_table != NULL) + return 0; + + table_size = sizeof(struct phm_vq_budgeting_table) + + sizeof(struct phm_vq_budgeting_record) * (num_entries - 1); + + ptable = kzalloc(table_size, GFP_KERNEL); + if (NULL == ptable) + return -ENOMEM; + + ptable->numEntries = (uint8_t) num_entries; + + for (i = 0; i < ptable->numEntries; i++) { + ptable->entries[i].ulCUs = rv_vqtable[i].ulCUs; + ptable->entries[i].ulSustainableSOCPowerLimitLow = rv_vqtable[i].ulSustainableSOCPowerLimitLow; + ptable->entries[i].ulSustainableSOCPowerLimitHigh = rv_vqtable[i].ulSustainableSOCPowerLimitHigh; + ptable->entries[i].ulMinSclkLow = rv_vqtable[i].ulMinSclkLow; + ptable->entries[i].ulMinSclkHigh = rv_vqtable[i].ulMinSclkHigh; + ptable->entries[i].ucDispConfig = rv_vqtable[i].ucDispConfig; + ptable->entries[i].ulDClk = rv_vqtable[i].ulDClk; + ptable->entries[i].ulEClk = rv_vqtable[i].ulEClk; + ptable->entries[i].ulSustainableSclk = rv_vqtable[i].ulSustainableSclk; + ptable->entries[i].ulSustainableCUs = rv_vqtable[i].ulSustainableCUs; + } + + hwmgr->dyn_state.vq_budgeting_table = ptable; + + return 0; +} + +static int rv_initialize_dpm_defaults(struct pp_hwmgr *hwmgr) +{ + struct rv_hwmgr *rv_hwmgr = (struct rv_hwmgr *)(hwmgr->backend); + struct cgs_system_info sys_info = {0}; + int result; + + rv_hwmgr->ddi_power_gating_disabled = 0; + rv_hwmgr->bapm_enabled = 1; + rv_hwmgr->dce_slow_sclk_threshold = 30000; + rv_hwmgr->disable_driver_thermal_policy = 1; + rv_hwmgr->thermal_auto_throttling_treshold = 0; + rv_hwmgr->is_nb_dpm_enabled = 1; + rv_hwmgr->dpm_flags = 1; + rv_hwmgr->disable_smu_acp_s3_handshake = 1; + rv_hwmgr->disable_notify_smu_vpu_recovery = 0; + rv_hwmgr->gfx_off_controled_by_driver = false; + + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_DynamicM3Arbiter); + + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_UVDPowerGating); + + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_UVDDynamicPowerGating); + + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_VCEPowerGating); + + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_SamuPowerGating); + + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_ACP); + + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_SclkDeepSleep); + + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_GFXDynamicMGPowerGating); + + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_SclkThrottleLowNotification); + + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_DisableVoltageIsland); + + phm_cap_set(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_DynamicUVDState); + + sys_info.size = sizeof(struct cgs_system_info); + sys_info.info_id = CGS_SYSTEM_INFO_PG_FLAGS; + result = cgs_query_system_info(hwmgr->device, &sys_info); + if (!result) { + if (sys_info.value & AMD_PG_SUPPORT_GFX_DMG) + phm_cap_set(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_GFXDynamicMGPowerGating); + } + + return 0; +} + +static int rv_construct_max_power_limits_table(struct pp_hwmgr *hwmgr, + struct phm_clock_and_voltage_limits *table) +{ + return 0; +} + +static int rv_init_dynamic_state_adjustment_rule_settings( + struct pp_hwmgr *hwmgr) +{ + uint32_t table_size = + sizeof(struct phm_clock_voltage_dependency_table) + + (7 * sizeof(struct phm_clock_voltage_dependency_record)); + + struct phm_clock_voltage_dependency_table *table_clk_vlt = + kzalloc(table_size, GFP_KERNEL); + + if (NULL == table_clk_vlt) { + pr_err("Can not allocate memory!\n"); + return -ENOMEM; + } + + table_clk_vlt->count = 8; + table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_0; + table_clk_vlt->entries[0].v = 0; + table_clk_vlt->entries[1].clk = PP_DAL_POWERLEVEL_1; + table_clk_vlt->entries[1].v = 1; + table_clk_vlt->entries[2].clk = PP_DAL_POWERLEVEL_2; + table_clk_vlt->entries[2].v = 2; + table_clk_vlt->entries[3].clk = PP_DAL_POWERLEVEL_3; + table_clk_vlt->entries[3].v = 3; + table_clk_vlt->entries[4].clk = PP_DAL_POWERLEVEL_4; + table_clk_vlt->entries[4].v = 4; + table_clk_vlt->entries[5].clk = PP_DAL_POWERLEVEL_5; + table_clk_vlt->entries[5].v = 5; + table_clk_vlt->entries[6].clk = PP_DAL_POWERLEVEL_6; + table_clk_vlt->entries[6].v = 6; + table_clk_vlt->entries[7].clk = PP_DAL_POWERLEVEL_7; + table_clk_vlt->entries[7].v = 7; + hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt; + + return 0; +} + +static int rv_get_system_info_data(struct pp_hwmgr *hwmgr) +{ + struct rv_hwmgr *rv_data = (struct rv_hwmgr *)hwmgr->backend; + + rv_data->sys_info.htc_hyst_lmt = 5; + rv_data->sys_info.htc_tmp_lmt = 203; + + if (rv_data->thermal_auto_throttling_treshold == 0) + rv_data->thermal_auto_throttling_treshold = 203; + + rv_construct_max_power_limits_table (hwmgr, + &hwmgr->dyn_state.max_clock_voltage_on_ac); + + rv_init_dynamic_state_adjustment_rule_settings(hwmgr); + + return 0; +} + +static int rv_construct_boot_state(struct pp_hwmgr *hwmgr) +{ + return 0; +} + +static int rv_tf_set_clock_limit(struct pp_hwmgr *hwmgr, void *input, + void *output, void *storage, int result) +{ + struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend); + struct PP_Clocks clocks = {0}; + struct pp_display_clock_request clock_req; + + clocks.dcefClock = hwmgr->display_config.min_dcef_set_clk; + clocks.dcefClockInSR = hwmgr->display_config.min_dcef_deep_sleep_set_clk; + clock_req.clock_type = amd_pp_dcf_clock; + clock_req.clock_freq_in_khz = clocks.dcefClock * 10; + + if (clocks.dcefClock == 0 && clocks.dcefClockInSR == 0) + clock_req.clock_freq_in_khz = rv_data->dcf_actual_hard_min_freq; + + PP_ASSERT_WITH_CODE(!rv_display_clock_voltage_request(hwmgr, &clock_req), + "Attempt to set DCF Clock Failed!", return -EINVAL); + + if(rv_data->need_min_deep_sleep_dcefclk && 0 != clocks.dcefClockInSR) + smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_SetMinDeepSleepDcefclk, + clocks.dcefClockInSR / 100); + /* + if(!rv_data->isp_tileA_power_gated || !rv_data->isp_tileB_power_gated) { + if ((hwmgr->ispArbiter.iclk != 0) && (rv_data->ISPActualHardMinFreq != (hwmgr->ispArbiter.iclk / 100) )) { + smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_SetHardMinIspclkByFreq, hwmgr->ispArbiter.iclk / 100); + rv_read_arg_from_smc(hwmgr->smumgr, &rv_data->ISPActualHardMinFreq), + } + } */ + + if((hwmgr->gfx_arbiter.sclk_hard_min != 0) && + ((hwmgr->gfx_arbiter.sclk_hard_min / 100) != rv_data->soc_actual_hard_min_freq)) { + smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_SetHardMinSocclkByFreq, + hwmgr->gfx_arbiter.sclk_hard_min / 100); + rv_read_arg_from_smc(hwmgr->smumgr, &rv_data->soc_actual_hard_min_freq); + } + + if ((hwmgr->gfx_arbiter.gfxclk != 0) && + (rv_data->gfx_actual_soft_min_freq != (hwmgr->gfx_arbiter.gfxclk))) { + smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_SetMinVideoGfxclkFreq, + hwmgr->gfx_arbiter.gfxclk / 100); + rv_read_arg_from_smc(hwmgr->smumgr, &rv_data->gfx_actual_soft_min_freq); + } + + if ((hwmgr->gfx_arbiter.fclk != 0) && + (rv_data->fabric_actual_soft_min_freq != (hwmgr->gfx_arbiter.fclk / 100))) { + smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_SetMinVideoFclkFreq, + hwmgr->gfx_arbiter.fclk / 100); + rv_read_arg_from_smc(hwmgr->smumgr, &rv_data->fabric_actual_soft_min_freq); + } + + return 0; +} + +static int rv_tf_set_num_active_display(struct pp_hwmgr *hwmgr, void *input, + void *output, void *storage, int result) +{ + uint32_t num_of_active_displays = 0; + struct cgs_display_info info = {0}; + + cgs_get_active_displays_info(hwmgr->device, &info); + num_of_active_displays = info.display_count; + + smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_SetDisplayCount, + num_of_active_displays); + return 0; +} + +static const struct phm_master_table_item rv_set_power_state_list[] = { + { NULL, rv_tf_set_clock_limit }, + { NULL, rv_tf_set_num_active_display }, + { } +}; + +static const struct phm_master_table_header rv_set_power_state_master = { + 0, + PHM_MasterTableFlag_None, + rv_set_power_state_list +}; + +static int rv_tf_init_power_gate_state(struct pp_hwmgr *hwmgr, void *input, + void *output, void *storage, int result) +{ + struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend); + + rv_data->vcn_power_gated = true; + rv_data->isp_tileA_power_gated = true; + rv_data->isp_tileB_power_gated = true; + + return 0; +} + +static const struct phm_master_table_item rv_setup_asic_list[] = { + { .tableFunction = rv_tf_init_power_gate_state }, + { } +}; + +static const struct phm_master_table_header rv_setup_asic_master = { + 0, + PHM_MasterTableFlag_None, + rv_setup_asic_list +}; + +static int rv_tf_reset_cc6_data(struct pp_hwmgr *hwmgr, + void *input, void *output, + void *storage, int result) +{ + struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend); + + rv_data->separation_time = 0; + rv_data->cc6_disable = false; + rv_data->pstate_disable = false; + rv_data->cc6_setting_changed = false; + + return 0; +} + +static const struct phm_master_table_item rv_power_down_asic_list[] = { + { .tableFunction = rv_tf_reset_cc6_data }, + { } +}; + +static const struct phm_master_table_header rv_power_down_asic_master = { + 0, + PHM_MasterTableFlag_None, + rv_power_down_asic_list +}; + + +static int rv_tf_disable_gfx_off(struct pp_hwmgr *hwmgr, + void *input, void *output, + void *storage, int result) +{ + struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend); + + if (rv_data->gfx_off_controled_by_driver) + smum_send_msg_to_smc(hwmgr->smumgr, + PPSMC_MSG_DisableGfxOff); + + return 0; +} + +static const struct phm_master_table_item rv_disable_dpm_list[] = { + {NULL, rv_tf_disable_gfx_off}, + { }, +}; + + +static const struct phm_master_table_header rv_disable_dpm_master = { + 0, + PHM_MasterTableFlag_None, + rv_disable_dpm_list +}; + +static int rv_tf_enable_gfx_off(struct pp_hwmgr *hwmgr, + void *input, void *output, + void *storage, int result) +{ + struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend); + + if (rv_data->gfx_off_controled_by_driver) + smum_send_msg_to_smc(hwmgr->smumgr, + PPSMC_MSG_EnableGfxOff); + + return 0; +} + +static const struct phm_master_table_item rv_enable_dpm_list[] = { + {NULL, rv_tf_enable_gfx_off}, + { }, +}; + +static const struct phm_master_table_header rv_enable_dpm_master = { + 0, + PHM_MasterTableFlag_None, + rv_enable_dpm_list +}; + +static int rv_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, + struct pp_power_state *prequest_ps, + const struct pp_power_state *pcurrent_ps) +{ + return 0; +} + +/* temporary hardcoded clock voltage breakdown tables */ +DpmClock_t VddDcfClk[]= { + { 300, 2600}, + { 600, 3200}, + { 600, 3600}, +}; + +DpmClock_t VddSocClk[]= { + { 478, 2600}, + { 722, 3200}, + { 722, 3600}, +}; + +DpmClock_t VddFClk[]= { + { 400, 2600}, + {1200, 3200}, + {1200, 3600}, +}; + +DpmClock_t VddDispClk[]= { + { 435, 2600}, + { 661, 3200}, + {1086, 3600}, +}; + +DpmClock_t VddDppClk[]= { + { 435, 2600}, + { 661, 3200}, + { 661, 3600}, +}; + +DpmClock_t VddPhyClk[]= { + { 540, 2600}, + { 810, 3200}, + { 810, 3600}, +}; + +static int rv_get_clock_voltage_dependency_table(struct pp_hwmgr *hwmgr, + struct rv_voltage_dependency_table **pptable, + uint32_t num_entry, DpmClock_t *pclk_dependency_table) +{ + uint32_t table_size, i; + struct rv_voltage_dependency_table *ptable; + + table_size = sizeof(uint32_t) + sizeof(struct rv_voltage_dependency_table) * num_entry; + ptable = kzalloc(table_size, GFP_KERNEL); + + if (NULL == ptable) + return -ENOMEM; + + ptable->count = num_entry; + + for (i = 0; i < ptable->count; i++) { + ptable->entries[i].clk = pclk_dependency_table->Freq * 100; + ptable->entries[i].vol = pclk_dependency_table->Vol; + pclk_dependency_table++; + } + + *pptable = ptable; + + return 0; +} + + +static int rv_populate_clock_table(struct pp_hwmgr *hwmgr) +{ + int result; + + struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend); + DpmClocks_t *table = &(rv_data->clock_table); + struct rv_clock_voltage_information *pinfo = &(rv_data->clock_vol_info); + + result = rv_copy_table_from_smc(hwmgr->smumgr, (uint8_t *)table, CLOCKTABLE); + + PP_ASSERT_WITH_CODE((0 == result), + "Attempt to copy clock table from smc failed", + return result); + + if (0 == result && table->DcefClocks[0].Freq != 0) { + rv_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dcefclk, + NUM_DCEFCLK_DPM_LEVELS, + &rv_data->clock_table.DcefClocks[0]); + rv_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_socclk, + NUM_SOCCLK_DPM_LEVELS, + &rv_data->clock_table.SocClocks[0]); + rv_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_fclk, + NUM_FCLK_DPM_LEVELS, + &rv_data->clock_table.FClocks[0]); + rv_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_mclk, + NUM_MEMCLK_DPM_LEVELS, + &rv_data->clock_table.MemClocks[0]); + } else { + rv_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dcefclk, + ARRAY_SIZE(VddDcfClk), + &VddDcfClk[0]); + rv_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_socclk, + ARRAY_SIZE(VddSocClk), + &VddSocClk[0]); + rv_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_fclk, + ARRAY_SIZE(VddFClk), + &VddFClk[0]); + } + rv_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dispclk, + ARRAY_SIZE(VddDispClk), + &VddDispClk[0]); + rv_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dppclk, + ARRAY_SIZE(VddDppClk), &VddDppClk[0]); + rv_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_phyclk, + ARRAY_SIZE(VddPhyClk), &VddPhyClk[0]); + + return 0; +} + +static int rv_hwmgr_backend_init(struct pp_hwmgr *hwmgr) +{ + int result = 0; + struct rv_hwmgr *data; + + data = kzalloc(sizeof(struct rv_hwmgr), GFP_KERNEL); + if (data == NULL) + return -ENOMEM; + + hwmgr->backend = data; + + result = rv_initialize_dpm_defaults(hwmgr); + if (result != 0) { + pr_err("rv_initialize_dpm_defaults failed\n"); + return result; + } + + phm_cap_set(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_PowerPlaySupport); + + rv_populate_clock_table(hwmgr); + + result = rv_get_system_info_data(hwmgr); + if (result != 0) { + pr_err("rv_get_system_info_data failed\n"); + return result; + } + + rv_construct_boot_state(hwmgr); + + result = phm_construct_table(hwmgr, &rv_setup_asic_master, + &(hwmgr->setup_asic)); + if (result != 0) { + pr_err("Fail to construct setup ASIC\n"); + return result; + } + + result = phm_construct_table(hwmgr, &rv_power_down_asic_master, + &(hwmgr->power_down_asic)); + if (result != 0) { + pr_err("Fail to construct power down ASIC\n"); + return result; + } + + result = phm_construct_table(hwmgr, &rv_set_power_state_master, + &(hwmgr->set_power_state)); + if (result != 0) { + pr_err("Fail to construct set_power_state\n"); + return result; + } + + result = phm_construct_table(hwmgr, &rv_disable_dpm_master, + &(hwmgr->disable_dynamic_state_management)); + if (result != 0) { + pr_err("Fail to disable_dynamic_state\n"); + return result; + } + result = phm_construct_table(hwmgr, &rv_enable_dpm_master, + &(hwmgr->enable_dynamic_state_management)); + if (result != 0) { + pr_err("Fail to enable_dynamic_state\n"); + return result; + } + + hwmgr->platform_descriptor.hardwareActivityPerformanceLevels = + RAVEN_MAX_HARDWARE_POWERLEVELS; + + hwmgr->platform_descriptor.hardwarePerformanceLevels = + RAVEN_MAX_HARDWARE_POWERLEVELS; + + hwmgr->platform_descriptor.vbiosInterruptId = 0; + + hwmgr->platform_descriptor.clockStep.engineClock = 500; + + hwmgr->platform_descriptor.clockStep.memoryClock = 500; + + hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50; + + rv_init_vq_budget_table(hwmgr); + + return result; +} + +static int rv_hwmgr_backend_fini(struct pp_hwmgr *hwmgr) +{ + struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend); + struct rv_clock_voltage_information *pinfo = &(rv_data->clock_vol_info); + + phm_destroy_table(hwmgr, &(hwmgr->set_power_state)); + phm_destroy_table(hwmgr, &(hwmgr->enable_dynamic_state_management)); + phm_destroy_table(hwmgr, &(hwmgr->disable_dynamic_state_management)); + phm_destroy_table(hwmgr, &(hwmgr->power_down_asic)); + phm_destroy_table(hwmgr, &(hwmgr->setup_asic)); + + if (pinfo->vdd_dep_on_dcefclk) { + kfree(pinfo->vdd_dep_on_dcefclk); + pinfo->vdd_dep_on_dcefclk = NULL; + } + if (pinfo->vdd_dep_on_socclk) { + kfree(pinfo->vdd_dep_on_socclk); + pinfo->vdd_dep_on_socclk = NULL; + } + if (pinfo->vdd_dep_on_fclk) { + kfree(pinfo->vdd_dep_on_fclk); + pinfo->vdd_dep_on_fclk = NULL; + } + if (pinfo->vdd_dep_on_dispclk) { + kfree(pinfo->vdd_dep_on_dispclk); + pinfo->vdd_dep_on_dispclk = NULL; + } + if (pinfo->vdd_dep_on_dppclk) { + kfree(pinfo->vdd_dep_on_dppclk); + pinfo->vdd_dep_on_dppclk = NULL; + } + if (pinfo->vdd_dep_on_phyclk) { + kfree(pinfo->vdd_dep_on_phyclk); + pinfo->vdd_dep_on_phyclk = NULL; + } + + if (NULL != hwmgr->dyn_state.vddc_dep_on_dal_pwrl) { + kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl); + hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL; + } + + if (NULL != hwmgr->dyn_state.vq_budgeting_table) { + kfree(hwmgr->dyn_state.vq_budgeting_table); + hwmgr->dyn_state.vq_budgeting_table = NULL; + } + + kfree(hwmgr->backend); + hwmgr->backend = NULL; + + return 0; +} + +static int rv_dpm_force_dpm_level(struct pp_hwmgr *hwmgr, + enum amd_dpm_forced_level level) +{ + return 0; +} + +static int rv_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low) +{ + return 0; +} + +static int rv_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low) +{ + return 0; +} + +static int rv_dpm_patch_boot_state(struct pp_hwmgr *hwmgr, + struct pp_hw_power_state *hw_ps) +{ + return 0; +} + +static int rv_dpm_get_pp_table_entry_callback( + struct pp_hwmgr *hwmgr, + struct pp_hw_power_state *hw_ps, + unsigned int index, + const void *clock_info) +{ + struct rv_power_state *rv_ps = cast_rv_ps(hw_ps); + + const ATOM_PPLIB_CZ_CLOCK_INFO *rv_clock_info = clock_info; + + struct phm_clock_voltage_dependency_table *table = + hwmgr->dyn_state.vddc_dependency_on_sclk; + uint8_t clock_info_index = rv_clock_info->index; + + if (clock_info_index > (uint8_t)(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1)) + clock_info_index = (uint8_t)(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1); + + rv_ps->levels[index].engine_clock = table->entries[clock_info_index].clk; + rv_ps->levels[index].vddc_index = (uint8_t)table->entries[clock_info_index].v; + + rv_ps->level = index + 1; + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) { + rv_ps->levels[index].ds_divider_index = 5; + rv_ps->levels[index].ss_divider_index = 5; + } + + return 0; +} + +static int rv_dpm_get_num_of_pp_table_entries(struct pp_hwmgr *hwmgr) +{ + int result; + unsigned long ret = 0; + + result = pp_tables_get_num_of_entries(hwmgr, &ret); + + return result ? 0 : ret; +} + +static int rv_dpm_get_pp_table_entry(struct pp_hwmgr *hwmgr, + unsigned long entry, struct pp_power_state *ps) +{ + int result; + struct rv_power_state *rv_ps; + + ps->hardware.magic = PhwRaven_Magic; + + rv_ps = cast_rv_ps(&(ps->hardware)); + + result = pp_tables_get_entry(hwmgr, entry, ps, + rv_dpm_get_pp_table_entry_callback); + + rv_ps->uvd_clocks.vclk = ps->uvd_clocks.VCLK; + rv_ps->uvd_clocks.dclk = ps->uvd_clocks.DCLK; + + return result; +} + +static int rv_get_power_state_size(struct pp_hwmgr *hwmgr) +{ + return sizeof(struct rv_power_state); +} + +static int rv_set_cpu_power_state(struct pp_hwmgr *hwmgr) +{ + return 0; +} + + +static int rv_store_cc6_data(struct pp_hwmgr *hwmgr, uint32_t separation_time, + bool cc6_disable, bool pstate_disable, bool pstate_switch_disable) +{ + return 0; +} + +static int rv_get_dal_power_level(struct pp_hwmgr *hwmgr, + struct amd_pp_simple_clock_info *info) +{ + return -EINVAL; +} + +static int rv_force_clock_level(struct pp_hwmgr *hwmgr, + enum pp_clock_type type, uint32_t mask) +{ + return 0; +} + +static int rv_print_clock_levels(struct pp_hwmgr *hwmgr, + enum pp_clock_type type, char *buf) +{ + return 0; +} + +static int rv_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, + PHM_PerformanceLevelDesignation designation, uint32_t index, + PHM_PerformanceLevel *level) +{ + const struct rv_power_state *ps; + struct rv_hwmgr *data; + uint32_t level_index; + uint32_t i; + uint32_t vol_dep_record_index = 0; + + if (level == NULL || hwmgr == NULL || state == NULL) + return -EINVAL; + + data = (struct rv_hwmgr *)(hwmgr->backend); + ps = cast_const_rv_ps(state); + + level_index = index > ps->level - 1 ? ps->level - 1 : index; + level->coreClock = ps->levels[level_index].engine_clock; + + if (designation == PHM_PerformanceLevelDesignation_PowerContainment) { + for (i = 1; i < ps->level; i++) { + if (ps->levels[i].engine_clock > data->dce_slow_sclk_threshold) { + level->coreClock = ps->levels[i].engine_clock; + break; + } + } + } + + if (level_index == 0) { + vol_dep_record_index = data->clock_vol_info.vdd_dep_on_fclk->count - 1; + level->memory_clock = + data->clock_vol_info.vdd_dep_on_fclk->entries[vol_dep_record_index].clk; + } else + level->memory_clock = data->clock_vol_info.vdd_dep_on_fclk->entries[0].clk; + + level->nonLocalMemoryFreq = 0; + level->nonLocalMemoryWidth = 0; + + return 0; +} + +static int rv_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr, + const struct pp_hw_power_state *state, struct pp_clock_info *clock_info) +{ + const struct rv_power_state *ps = cast_const_rv_ps(state); + + clock_info->min_eng_clk = ps->levels[0].engine_clock / (1 << (ps->levels[0].ss_divider_index)); + clock_info->max_eng_clk = ps->levels[ps->level - 1].engine_clock / (1 << (ps->levels[ps->level - 1].ss_divider_index)); + + return 0; +} + +#define MEM_FREQ_LOW_LATENCY 25000 +#define MEM_FREQ_HIGH_LATENCY 80000 +#define MEM_LATENCY_HIGH 245 +#define MEM_LATENCY_LOW 35 +#define MEM_LATENCY_ERR 0xFFFF + + +static uint32_t rv_get_mem_latency(struct pp_hwmgr *hwmgr, + uint32_t clock) +{ + if (clock >= MEM_FREQ_LOW_LATENCY && + clock < MEM_FREQ_HIGH_LATENCY) + return MEM_LATENCY_HIGH; + else if (clock >= MEM_FREQ_HIGH_LATENCY) + return MEM_LATENCY_LOW; + else + return MEM_LATENCY_ERR; +} + +static int rv_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr, + enum amd_pp_clock_type type, + struct pp_clock_levels_with_latency *clocks) +{ + uint32_t i; + struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend); + struct rv_clock_voltage_information *pinfo = &(rv_data->clock_vol_info); + struct rv_voltage_dependency_table *pclk_vol_table; + bool latency_required = false; + + if (pinfo == NULL) + return -EINVAL; + + switch (type) { + case amd_pp_mem_clock: + pclk_vol_table = pinfo->vdd_dep_on_mclk; + latency_required = true; + break; + case amd_pp_f_clock: + pclk_vol_table = pinfo->vdd_dep_on_fclk; + latency_required = true; + break; + case amd_pp_dcf_clock: + pclk_vol_table = pinfo->vdd_dep_on_dcefclk; + break; + case amd_pp_disp_clock: + pclk_vol_table = pinfo->vdd_dep_on_dispclk; + break; + case amd_pp_phy_clock: + pclk_vol_table = pinfo->vdd_dep_on_phyclk; + break; + case amd_pp_dpp_clock: + pclk_vol_table = pinfo->vdd_dep_on_dppclk; + default: + return -EINVAL; + } + + if (pclk_vol_table == NULL || pclk_vol_table->count == 0) + return -EINVAL; + + clocks->num_levels = 0; + for (i = 0; i < pclk_vol_table->count; i++) { + clocks->data[i].clocks_in_khz = pclk_vol_table->entries[i].clk; + clocks->data[i].latency_in_us = latency_required ? + rv_get_mem_latency(hwmgr, + pclk_vol_table->entries[i].clk) : + 0; + clocks->num_levels++; + } + + return 0; +} + +static int rv_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr, + enum amd_pp_clock_type type, + struct pp_clock_levels_with_voltage *clocks) +{ + uint32_t i; + struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend); + struct rv_clock_voltage_information *pinfo = &(rv_data->clock_vol_info); + struct rv_voltage_dependency_table *pclk_vol_table = NULL; + + if (pinfo == NULL) + return -EINVAL; + + switch (type) { + case amd_pp_mem_clock: + pclk_vol_table = pinfo->vdd_dep_on_mclk; + break; + case amd_pp_f_clock: + pclk_vol_table = pinfo->vdd_dep_on_fclk; + break; + case amd_pp_dcf_clock: + pclk_vol_table = pinfo->vdd_dep_on_dcefclk; + break; + case amd_pp_soc_clock: + pclk_vol_table = pinfo->vdd_dep_on_socclk; + break; + default: + return -EINVAL; + } + + if (pclk_vol_table == NULL || pclk_vol_table->count == 0) + return -EINVAL; + + clocks->num_levels = 0; + for (i = 0; i < pclk_vol_table->count; i++) { + clocks->data[i].clocks_in_khz = pclk_vol_table->entries[i].clk; + clocks->data[i].voltage_in_mv = pclk_vol_table->entries[i].vol; + clocks->num_levels++; + } + + return 0; +} + +int rv_display_clock_voltage_request(struct pp_hwmgr *hwmgr, + struct pp_display_clock_request *clock_req) +{ + int result = 0; + struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend); + enum amd_pp_clock_type clk_type = clock_req->clock_type; + uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000; + PPSMC_Msg msg; + + switch (clk_type) { + case amd_pp_dcf_clock: + if (clk_freq == rv_data->dcf_actual_hard_min_freq) + return 0; + msg = PPSMC_MSG_SetHardMinDcefclkByFreq; + rv_data->dcf_actual_hard_min_freq = clk_freq; + break; + case amd_pp_soc_clock: + msg = PPSMC_MSG_SetHardMinSocclkByFreq; + break; + case amd_pp_f_clock: + if (clk_freq == rv_data->f_actual_hard_min_freq) + return 0; + rv_data->f_actual_hard_min_freq = clk_freq; + msg = PPSMC_MSG_SetHardMinFclkByFreq; + break; + default: + pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!"); + return -EINVAL; + } + + result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, msg, + clk_freq); + + return result; +} + +static int rv_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks) +{ + return -EINVAL; +} + +static int rv_thermal_get_temperature(struct pp_hwmgr *hwmgr) +{ + uint32_t reg_offset = soc15_get_register_offset(THM_HWID, 0, + mmTHM_TCON_CUR_TMP_BASE_IDX, mmTHM_TCON_CUR_TMP); + uint32_t reg_value = cgs_read_register(hwmgr->device, reg_offset); + int cur_temp = + (reg_value & THM_TCON_CUR_TMP__CUR_TEMP_MASK) >> THM_TCON_CUR_TMP__CUR_TEMP__SHIFT; + + if (cur_temp & THM_TCON_CUR_TMP__CUR_TEMP_RANGE_SEL_MASK) + cur_temp = ((cur_temp / 8) - 49) * PP_TEMPERATURE_UNITS_PER_CENTIGRADES; + else + cur_temp = (cur_temp / 8) * PP_TEMPERATURE_UNITS_PER_CENTIGRADES; + + return cur_temp; +} + +static int rv_read_sensor(struct pp_hwmgr *hwmgr, int idx, + void *value, int *size) +{ + switch (idx) { + case AMDGPU_PP_SENSOR_GPU_TEMP: + *((uint32_t *)value) = rv_thermal_get_temperature(hwmgr); + return 0; + default: + return -EINVAL; + } +} + +static const struct pp_hwmgr_func rv_hwmgr_funcs = { + .backend_init = rv_hwmgr_backend_init, + .backend_fini = rv_hwmgr_backend_fini, + .asic_setup = NULL, + .apply_state_adjust_rules = rv_apply_state_adjust_rules, + .force_dpm_level = rv_dpm_force_dpm_level, + .get_power_state_size = rv_get_power_state_size, + .powerdown_uvd = NULL, + .powergate_uvd = NULL, + .powergate_vce = NULL, + .get_mclk = rv_dpm_get_mclk, + .get_sclk = rv_dpm_get_sclk, + .patch_boot_state = rv_dpm_patch_boot_state, + .get_pp_table_entry = rv_dpm_get_pp_table_entry, + .get_num_of_pp_table_entries = rv_dpm_get_num_of_pp_table_entries, + .set_cpu_power_state = rv_set_cpu_power_state, + .store_cc6_data = rv_store_cc6_data, + .force_clock_level = rv_force_clock_level, + .print_clock_levels = rv_print_clock_levels, + .get_dal_power_level = rv_get_dal_power_level, + .get_performance_level = rv_get_performance_level, + .get_current_shallow_sleep_clocks = rv_get_current_shallow_sleep_clocks, + .get_clock_by_type_with_latency = rv_get_clock_by_type_with_latency, + .get_clock_by_type_with_voltage = rv_get_clock_by_type_with_voltage, + .get_max_high_clocks = rv_get_max_high_clocks, + .read_sensor = rv_read_sensor, +}; + +int rv_init_function_pointers(struct pp_hwmgr *hwmgr) +{ + hwmgr->hwmgr_func = &rv_hwmgr_funcs; + hwmgr->pptable_func = &pptable_funcs; + return 0; +} diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h new file mode 100644 index 000000000000..afb852295a15 --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h @@ -0,0 +1,301 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef RAVEN_HWMGR_H +#define RAVEN_HWMGR_H + +#include "hwmgr.h" +#include "rv_inc.h" +#include "smu10_driver_if.h" +#include "rv_ppsmc.h" + + +#define RAVEN_MAX_HARDWARE_POWERLEVELS 8 +#define PHMRAVEN_DYNCLK_NUMBER_OF_TREND_COEFFICIENTS 15 + +#define DPMFlags_SCLK_Enabled 0x00000001 +#define DPMFlags_UVD_Enabled 0x00000002 +#define DPMFlags_VCE_Enabled 0x00000004 +#define DPMFlags_ACP_Enabled 0x00000008 +#define DPMFlags_ForceHighestValid 0x40000000 + +/* Do not change the following, it is also defined in SMU8.h */ +#define SMU_EnabledFeatureScoreboard_AcpDpmOn 0x00000001 +#define SMU_EnabledFeatureScoreboard_SclkDpmOn 0x00200000 +#define SMU_EnabledFeatureScoreboard_UvdDpmOn 0x01000000 +#define SMU_EnabledFeatureScoreboard_VceDpmOn 0x02000000 + +#define SMU_PHYID_SHIFT 8 + +#define RAVEN_PCIE_POWERGATING_TARGET_GFX 0 +#define RAVEN_PCIE_POWERGATING_TARGET_DDI 1 +#define RAVEN_PCIE_POWERGATING_TARGET_PLLCASCADE 2 +#define RAVEN_PCIE_POWERGATING_TARGET_PHY 3 + +enum VQ_TYPE { + CLOCK_TYPE_DCLK = 0L, + CLOCK_TYPE_ECLK, + CLOCK_TYPE_SCLK, + CLOCK_TYPE_CCLK, + VQ_GFX_CU +}; + +#define SUSTAINABLE_SCLK_MASK 0x00ffffff +#define SUSTAINABLE_SCLK_SHIFT 0 +#define SUSTAINABLE_CU_MASK 0xff000000 +#define SUSTAINABLE_CU_SHIFT 24 + +struct rv_dpm_entry { + uint32_t soft_min_clk; + uint32_t hard_min_clk; + uint32_t soft_max_clk; + uint32_t hard_max_clk; +}; + +struct rv_power_level { + uint32_t engine_clock; + uint8_t vddc_index; + uint8_t ds_divider_index; + uint8_t ss_divider_index; + uint8_t allow_gnb_slow; + uint8_t force_nbp_state; + uint8_t display_wm; + uint8_t vce_wm; + uint8_t num_simd_to_powerdown; + uint8_t hysteresis_up; + uint8_t rsv[3]; +}; + +/*used for the nbpsFlags field in rv_power state*/ +#define RAVEN_POWERSTATE_FLAGS_NBPS_FORCEHIGH (1<<0) +#define RAVEN_POWERSTATE_FLAGS_NBPS_LOCKTOHIGH (1<<1) +#define RAVEN_POWERSTATE_FLAGS_NBPS_LOCKTOLOW (1<<2) + +#define RAVEN_POWERSTATE_FLAGS_BAPM_DISABLE (1<<0) + +struct rv_uvd_clocks { + uint32_t vclk; + uint32_t dclk; + uint32_t vclk_low_divider; + uint32_t vclk_high_divider; + uint32_t dclk_low_divider; + uint32_t dclk_high_divider; +}; + +struct pp_disable_nbpslo_flags { + union { + struct { + uint32_t entry : 1; + uint32_t display : 1; + uint32_t driver: 1; + uint32_t vce : 1; + uint32_t uvd : 1; + uint32_t acp : 1; + uint32_t reserved: 26; + } bits; + uint32_t u32All; + }; +}; + + +enum rv_pstate_previous_action { + DO_NOTHING = 1, + FORCE_HIGH, + CANCEL_FORCE_HIGH +}; + +struct rv_power_state { + unsigned int magic; + uint32_t level; + struct rv_uvd_clocks uvd_clocks; + uint32_t evclk; + uint32_t ecclk; + uint32_t samclk; + uint32_t acpclk; + bool need_dfs_bypass; + + uint32_t nbps_flags; + uint32_t bapm_flags; + uint8_t dpm0_pg_nbps_low; + uint8_t dpm0_pg_nbps_high; + uint8_t dpm_x_nbps_low; + uint8_t dpm_x_nbps_high; + + enum rv_pstate_previous_action action; + + struct rv_power_level levels[RAVEN_MAX_HARDWARE_POWERLEVELS]; + struct pp_disable_nbpslo_flags nbpslo_flags; +}; + +#define RAVEN_NUM_NBPSTATES 4 +#define RAVEN_NUM_NBPMEMORYCLOCK 2 + + +struct rv_display_phy_info_entry { + uint8_t phy_present; + uint8_t active_lane_mapping; + uint8_t display_config_type; + uint8_t active_num_of_lanes; +}; + +#define RAVEN_MAX_DISPLAYPHY_IDS 10 + +struct rv_display_phy_info { + bool display_phy_access_initialized; + struct rv_display_phy_info_entry entries[RAVEN_MAX_DISPLAYPHY_IDS]; +}; + +#define MAX_DISPLAY_CLOCK_LEVEL 8 + +struct rv_system_info{ + uint8_t htc_tmp_lmt; + uint8_t htc_hyst_lmt; +}; + +#define MAX_REGULAR_DPM_NUMBER 8 + +struct rv_mclk_latency_entries { + uint32_t frequency; + uint32_t latency; +}; + +struct rv_mclk_latency_table { + uint32_t count; + struct rv_mclk_latency_entries entries[MAX_REGULAR_DPM_NUMBER]; +}; + +struct rv_clock_voltage_dependency_record { + uint32_t clk; + uint32_t vol; +}; + + +struct rv_voltage_dependency_table { + uint32_t count; + struct rv_clock_voltage_dependency_record entries[1]; +}; + +struct rv_clock_voltage_information { + struct rv_voltage_dependency_table *vdd_dep_on_dcefclk; + struct rv_voltage_dependency_table *vdd_dep_on_socclk; + struct rv_voltage_dependency_table *vdd_dep_on_fclk; + struct rv_voltage_dependency_table *vdd_dep_on_mclk; + struct rv_voltage_dependency_table *vdd_dep_on_dispclk; + struct rv_voltage_dependency_table *vdd_dep_on_dppclk; + struct rv_voltage_dependency_table *vdd_dep_on_phyclk; +}; + +struct rv_hwmgr { + uint32_t disable_driver_thermal_policy; + uint32_t thermal_auto_throttling_treshold; + struct rv_system_info sys_info; + struct rv_mclk_latency_table mclk_latency_table; + + uint32_t ddi_power_gating_disabled; + + struct rv_display_phy_info_entry display_phy_info; + uint32_t dce_slow_sclk_threshold; + + bool disp_clk_bypass; + bool disp_clk_bypass_pending; + uint32_t bapm_enabled; + + bool video_start; + bool battery_state; + + uint32_t is_nb_dpm_enabled; + uint32_t is_voltage_island_enabled; + uint32_t disable_smu_acp_s3_handshake; + uint32_t disable_notify_smu_vpu_recovery; + bool in_vpu_recovery; + bool pg_acp_init; + uint8_t disp_config; + + /* PowerTune */ + uint32_t power_containment_features; + bool cac_enabled; + bool disable_uvd_power_tune_feature; + bool enable_bapm_feature; + bool enable_tdc_limit_feature; + + + /* SMC SRAM Address of firmware header tables */ + uint32_t sram_end; + uint32_t dpm_table_start; + uint32_t soft_regs_start; + + /* start of SMU7_Fusion_DpmTable */ + + uint8_t uvd_level_count; + uint8_t vce_level_count; + uint8_t acp_level_count; + uint8_t samu_level_count; + + uint32_t fps_high_threshold; + uint32_t fps_low_threshold; + + uint32_t dpm_flags; + struct rv_dpm_entry sclk_dpm; + struct rv_dpm_entry uvd_dpm; + struct rv_dpm_entry vce_dpm; + struct rv_dpm_entry acp_dpm; + bool acp_power_up_no_dsp; + + uint32_t max_sclk_level; + uint32_t num_of_clk_entries; + + /* CPU Power State */ + uint32_t separation_time; + bool cc6_disable; + bool pstate_disable; + bool cc6_setting_changed; + + uint32_t ulTotalActiveCUs; + + bool isp_tileA_power_gated; + bool isp_tileB_power_gated; + uint32_t isp_actual_hard_min_freq; + uint32_t soc_actual_hard_min_freq; + uint32_t dcf_actual_hard_min_freq; + + uint32_t f_actual_hard_min_freq; + uint32_t fabric_actual_soft_min_freq; + uint32_t gfx_actual_soft_min_freq; + + bool vcn_power_gated; + bool vcn_dpg_mode; + + bool gfx_off_controled_by_driver; + Watermarks_t water_marks_table; + struct rv_clock_voltage_information clock_vol_info; + DpmClocks_t clock_table; + + uint32_t active_process_mask; + bool need_min_deep_sleep_dcefclk; /* disabled by default */ +}; + +struct pp_hwmgr; + +int rv_init_function_pointers(struct pp_hwmgr *hwmgr); + +#endif diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h new file mode 100644 index 000000000000..9a0149370d26 --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h @@ -0,0 +1,43 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef RAVEN_INC_H +#define RAVEN_INC_H + + +#include "asic_reg/raven1/MP/mp_10_0_default.h" +#include "asic_reg/raven1/MP/mp_10_0_offset.h" +#include "asic_reg/raven1/MP/mp_10_0_sh_mask.h" + +#include "asic_reg/raven1/NBIO/nbio_7_0_default.h" +#include "asic_reg/raven1/NBIO/nbio_7_0_offset.h" +#include "asic_reg/raven1/NBIO/nbio_7_0_sh_mask.h" + +#include "asic_reg/raven1/THM/thm_10_0_default.h" +#include "asic_reg/raven1/THM/thm_10_0_offset.h" +#include "asic_reg/raven1/THM/thm_10_0_sh_mask.h" + + +#define ixDDI_PHY_GEN_STATUS 0x3FCE8 + +#endif diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c index 102eb6d029fa..1f01020ce3a9 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c @@ -21,11 +21,11 @@ * */ #include "pp_debug.h" +#include <linux/delay.h> +#include <linux/fb.h> #include <linux/module.h> #include <linux/slab.h> -#include <linux/fb.h> #include <asm/div64.h> -#include "linux/delay.h" #include "pp_acpi.h" #include "ppatomctrl.h" #include "atombios.h" diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c index 2614af2f553f..f988ed204d9a 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c @@ -20,10 +20,11 @@ * OTHER DEALINGS IN THE SOFTWARE. * */ + +#include <linux/delay.h> +#include <linux/fb.h> #include <linux/module.h> #include <linux/slab.h> -#include <linux/fb.h> -#include "linux/delay.h" #include "hwmgr.h" #include "amd_powerplay.h" @@ -47,7 +48,7 @@ #include "amd_pcie_helpers.h" #include "cgs_linux.h" #include "ppinterrupt.h" - +#include "pp_overdriver.h" #define VOLTAGE_SCALE 4 #define VOLTAGE_VID_OFFSET_SCALE1 625 @@ -124,7 +125,13 @@ static void vega10_set_default_registry_data(struct pp_hwmgr *hwmgr) } data->registry_data.clock_stretcher_support = - hwmgr->feature_mask & PP_CLOCK_STRETCH_MASK ? false : true; + hwmgr->feature_mask & PP_CLOCK_STRETCH_MASK ? true : false; + + data->registry_data.ulv_support = + hwmgr->feature_mask & PP_ULV_MASK ? true : false; + + data->registry_data.sclk_deep_sleep_support = + hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK ? true : false; data->registry_data.disable_water_mark = 0; @@ -349,6 +356,7 @@ static void vega10_init_dpm_defaults(struct pp_hwmgr *hwmgr) data->smu_features[GNLD_DS_GFXCLK].supported = true; data->smu_features[GNLD_DS_SOCCLK].supported = true; data->smu_features[GNLD_DS_LCLK].supported = true; + data->smu_features[GNLD_DS_DCEFCLK].supported = true; } if (data->registry_data.enable_pkg_pwr_tracking_feature) @@ -1161,7 +1169,7 @@ static int vega10_setup_default_pcie_table(struct pp_hwmgr *hwmgr) "Incorrect number of PCIE States from VBIOS!", return -1); - for (i = 0; i < NUM_LINK_LEVELS - 1; i++) { + for (i = 0; i < NUM_LINK_LEVELS; i++) { if (data->registry_data.pcieSpeedOverride) pcie_table->pcie_gen[i] = data->registry_data.pcieSpeedOverride; @@ -1170,12 +1178,11 @@ static int vega10_setup_default_pcie_table(struct pp_hwmgr *hwmgr) bios_pcie_table->entries[i].gen_speed; if (data->registry_data.pcieLaneOverride) - pcie_table->pcie_lane[i] = - data->registry_data.pcieLaneOverride; + pcie_table->pcie_lane[i] = (uint8_t)encode_pcie_lane_width( + data->registry_data.pcieLaneOverride); else - pcie_table->pcie_lane[i] = - bios_pcie_table->entries[i].lane_width; - + pcie_table->pcie_lane[i] = (uint8_t)encode_pcie_lane_width( + bios_pcie_table->entries[i].lane_width); if (data->registry_data.pcieClockOverride) pcie_table->lclk[i] = data->registry_data.pcieClockOverride; @@ -1506,7 +1513,9 @@ static int vega10_populate_single_gfx_level(struct pp_hwmgr *hwmgr, struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend); struct pp_atomfwctrl_clock_dividers_soc15 dividers; - uint32_t i; + uint32_t gfx_max_clock = + hwmgr->platform_descriptor.overdriveLimit.engineClock; + uint32_t i = 0; if (data->apply_overdrive_next_settings_mask & DPMTABLE_OD_UPDATE_VDDC) @@ -1517,14 +1526,18 @@ static int vega10_populate_single_gfx_level(struct pp_hwmgr *hwmgr, "Invalid SOC_VDD-GFX_CLK Dependency Table!", return -EINVAL); - for (i = 0; i < dep_on_sclk->count; i++) { - if (dep_on_sclk->entries[i].clk == gfx_clock) - break; + if (data->need_update_dpm_table & DPMTABLE_OD_UPDATE_SCLK) + gfx_clock = gfx_clock > gfx_max_clock ? gfx_max_clock : gfx_clock; + else { + for (i = 0; i < dep_on_sclk->count; i++) { + if (dep_on_sclk->entries[i].clk == gfx_clock) + break; + } + PP_ASSERT_WITH_CODE(dep_on_sclk->count > i, + "Cannot find gfx_clk in SOC_VDD-GFX_CLK!", + return -EINVAL); } - PP_ASSERT_WITH_CODE(dep_on_sclk->count > i, - "Cannot find gfx_clk in SOC_VDD-GFX_CLK!", - return -EINVAL); PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr, COMPUTE_GPUCLK_INPUT_FLAG_GFXCLK, gfx_clock, ÷rs), @@ -1535,11 +1548,7 @@ static int vega10_populate_single_gfx_level(struct pp_hwmgr *hwmgr, current_gfxclk_level->FbMult = cpu_to_le32(dividers.ulPll_fb_mult); /* Spread FB Multiplier bit: bit 0:8 int, bit 31:16 frac */ - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_EngineSpreadSpectrumSupport)) - current_gfxclk_level->SsOn = dividers.ucPll_ss_enable; - else - current_gfxclk_level->SsOn = 0; + current_gfxclk_level->SsOn = dividers.ucPll_ss_enable; current_gfxclk_level->SsFbMult = cpu_to_le32(dividers.ulPll_ss_fbsmult); current_gfxclk_level->SsSlewFrac = @@ -1692,7 +1701,9 @@ static int vega10_populate_single_memory_level(struct pp_hwmgr *hwmgr, struct phm_ppt_v1_clock_voltage_dependency_table *dep_on_mclk = table_info->vdd_dep_on_mclk; struct pp_atomfwctrl_clock_dividers_soc15 dividers; - uint32_t i; + uint32_t mem_max_clock = + hwmgr->platform_descriptor.overdriveLimit.memoryClock; + uint32_t i = 0; if (data->apply_overdrive_next_settings_mask & DPMTABLE_OD_UPDATE_VDDC) @@ -1703,15 +1714,18 @@ static int vega10_populate_single_memory_level(struct pp_hwmgr *hwmgr, "Invalid SOC_VDD-UCLK Dependency Table!", return -EINVAL); - for (i = 0; i < dep_on_mclk->count; i++) { - if (dep_on_mclk->entries[i].clk == mem_clock) - break; + if (data->need_update_dpm_table & DPMTABLE_OD_UPDATE_MCLK) + mem_clock = mem_clock > mem_max_clock ? mem_max_clock : mem_clock; + else { + for (i = 0; i < dep_on_mclk->count; i++) { + if (dep_on_mclk->entries[i].clk == mem_clock) + break; + } + PP_ASSERT_WITH_CODE(dep_on_mclk->count > i, + "Cannot find UCLK in SOC_VDD-UCLK Dependency Table!", + return -EINVAL); } - PP_ASSERT_WITH_CODE(dep_on_mclk->count > i, - "Cannot find UCLK in SOC_VDD-UCLK Dependency Table!", - return -EINVAL); - PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10( hwmgr, COMPUTE_GPUCLK_INPUT_FLAG_UCLK, mem_clock, ÷rs), "Failed to get UCLK settings from VBIOS!", @@ -2095,7 +2109,7 @@ static int vega10_populate_avfs_parameters(struct pp_hwmgr *hwmgr) pp_table->AvfsGbCksOn.m1 = cpu_to_le32(avfs_params.ulGbFuseTableCksonM1); pp_table->AvfsGbCksOn.m2 = - cpu_to_le16(avfs_params.ulGbFuseTableCksonM2); + cpu_to_le32(avfs_params.ulGbFuseTableCksonM2); pp_table->AvfsGbCksOn.b = cpu_to_le32(avfs_params.ulGbFuseTableCksonB); pp_table->AvfsGbCksOn.m1_shift = 24; @@ -2107,7 +2121,7 @@ static int vega10_populate_avfs_parameters(struct pp_hwmgr *hwmgr) pp_table->AvfsGbCksOff.m1 = cpu_to_le32(avfs_params.ulGbFuseTableCksoffM1); pp_table->AvfsGbCksOff.m2 = - cpu_to_le16(avfs_params.ulGbFuseTableCksoffM2); + cpu_to_le32(avfs_params.ulGbFuseTableCksoffM2); pp_table->AvfsGbCksOff.b = cpu_to_le32(avfs_params.ulGbFuseTableCksoffB); pp_table->AvfsGbCksOff.m1_shift = 24; @@ -2286,6 +2300,73 @@ static int vega10_avfs_enable(struct pp_hwmgr *hwmgr, bool enable) return 0; } +static int vega10_populate_and_upload_avfs_fuse_override(struct pp_hwmgr *hwmgr) +{ + int result = 0; + + uint64_t serial_number = 0; + uint32_t top32, bottom32; + struct phm_fuses_default fuse; + + struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend); + AvfsFuseOverride_t *avfs_fuse_table = &(data->smc_state_table.avfs_fuse_override_table); + + smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_ReadSerialNumTop32); + vega10_read_arg_from_smc(hwmgr->smumgr, &top32); + + smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_ReadSerialNumBottom32); + vega10_read_arg_from_smc(hwmgr->smumgr, &bottom32); + + serial_number = ((uint64_t)bottom32 << 32) | top32; + + if (pp_override_get_default_fuse_value(serial_number, vega10_fuses_default, &fuse) == 0) { + avfs_fuse_table->VFT0_b = fuse.VFT0_b; + avfs_fuse_table->VFT0_m1 = fuse.VFT0_m1; + avfs_fuse_table->VFT0_m2 = fuse.VFT0_m2; + avfs_fuse_table->VFT1_b = fuse.VFT1_b; + avfs_fuse_table->VFT1_m1 = fuse.VFT1_m1; + avfs_fuse_table->VFT1_m2 = fuse.VFT1_m2; + avfs_fuse_table->VFT2_b = fuse.VFT2_b; + avfs_fuse_table->VFT2_m1 = fuse.VFT2_m1; + avfs_fuse_table->VFT2_m2 = fuse.VFT2_m2; + result = vega10_copy_table_to_smc(hwmgr->smumgr, + (uint8_t *)avfs_fuse_table, AVFSFUSETABLE); + PP_ASSERT_WITH_CODE(!result, + "Failed to upload FuseOVerride!", + ); + } + + return result; +} + +static int vega10_save_default_power_profile(struct pp_hwmgr *hwmgr) +{ + struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend); + struct vega10_single_dpm_table *dpm_table = &(data->dpm_table.gfx_table); + uint32_t min_level; + + hwmgr->default_gfx_power_profile.type = AMD_PP_GFX_PROFILE; + hwmgr->default_compute_power_profile.type = AMD_PP_COMPUTE_PROFILE; + + /* Optimize compute power profile: Use only highest + * 2 power levels (if more than 2 are available) + */ + if (dpm_table->count > 2) + min_level = dpm_table->count - 2; + else if (dpm_table->count == 2) + min_level = 1; + else + min_level = 0; + + hwmgr->default_compute_power_profile.min_sclk = + dpm_table->dpm_levels[min_level].value; + + hwmgr->gfx_power_profile = hwmgr->default_gfx_power_profile; + hwmgr->compute_power_profile = hwmgr->default_compute_power_profile; + + return 0; +} + /** * Initializes the SMC table and uploads it * @@ -2382,6 +2463,7 @@ static int vega10_init_smc_table(struct pp_hwmgr *hwmgr) data->vbios_boot_state.gfx_clock = boot_up_values.ulGfxClk; data->vbios_boot_state.mem_clock = boot_up_values.ulUClk; data->vbios_boot_state.soc_clock = boot_up_values.ulSocClk; + data->vbios_boot_state.dcef_clock = boot_up_values.ulDCEFClk; if (0 != boot_up_values.usVddc) { smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_SetFloorSocVoltage, @@ -2390,6 +2472,9 @@ static int vega10_init_smc_table(struct pp_hwmgr *hwmgr) } else { data->vbios_boot_state.bsoc_vddc_lock = false; } + smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_SetMinDeepSleepDcefclk, + (uint32_t)(data->vbios_boot_state.dcef_clock / 100)); } result = vega10_populate_avfs_parameters(hwmgr); @@ -2411,6 +2496,8 @@ static int vega10_init_smc_table(struct pp_hwmgr *hwmgr) pp_table->GfxActivityAverageAlpha = (uint8_t) (data->gfx_activity_average_alpha); + vega10_populate_and_upload_avfs_fuse_override(hwmgr); + result = vega10_copy_table_to_smc(hwmgr->smumgr, (uint8_t *)pp_table, PPTABLE); PP_ASSERT_WITH_CODE(!result, @@ -2420,6 +2507,8 @@ static int vega10_init_smc_table(struct pp_hwmgr *hwmgr) PP_ASSERT_WITH_CODE(!result, "Attempt to enable AVFS feature Failed!", return result); + vega10_save_default_power_profile(hwmgr); + return 0; } @@ -2509,6 +2598,22 @@ static int vega10_enable_ulv(struct pp_hwmgr *hwmgr) return 0; } +static int vega10_disable_ulv(struct pp_hwmgr *hwmgr) +{ + struct vega10_hwmgr *data = + (struct vega10_hwmgr *)(hwmgr->backend); + + if (data->registry_data.ulv_support) { + PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, + false, data->smu_features[GNLD_ULV].smu_feature_bitmap), + "disable ULV Feature Failed!", + return -EINVAL); + data->smu_features[GNLD_ULV].enabled = false; + } + + return 0; +} + static int vega10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) { struct vega10_hwmgr *data = @@ -2518,26 +2623,74 @@ static int vega10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, true, data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap), "Attempt to Enable DS_GFXCLK Feature Failed!", - return -1); + return -EINVAL); data->smu_features[GNLD_DS_GFXCLK].enabled = true; } if (data->smu_features[GNLD_DS_SOCCLK].supported) { PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, true, data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap), - "Attempt to Enable DS_GFXCLK Feature Failed!", - return -1); + "Attempt to Enable DS_SOCCLK Feature Failed!", + return -EINVAL); data->smu_features[GNLD_DS_SOCCLK].enabled = true; } if (data->smu_features[GNLD_DS_LCLK].supported) { PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, true, data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap), - "Attempt to Enable DS_GFXCLK Feature Failed!", - return -1); + "Attempt to Enable DS_LCLK Feature Failed!", + return -EINVAL); data->smu_features[GNLD_DS_LCLK].enabled = true; } + if (data->smu_features[GNLD_DS_DCEFCLK].supported) { + PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, + true, data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap), + "Attempt to Enable DS_DCEFCLK Feature Failed!", + return -EINVAL); + data->smu_features[GNLD_DS_DCEFCLK].enabled = true; + } + + return 0; +} + +static int vega10_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) +{ + struct vega10_hwmgr *data = + (struct vega10_hwmgr *)(hwmgr->backend); + + if (data->smu_features[GNLD_DS_GFXCLK].supported) { + PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, + false, data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap), + "Attempt to disable DS_GFXCLK Feature Failed!", + return -EINVAL); + data->smu_features[GNLD_DS_GFXCLK].enabled = false; + } + + if (data->smu_features[GNLD_DS_SOCCLK].supported) { + PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, + false, data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap), + "Attempt to disable DS_ Feature Failed!", + return -EINVAL); + data->smu_features[GNLD_DS_SOCCLK].enabled = false; + } + + if (data->smu_features[GNLD_DS_LCLK].supported) { + PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, + false, data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap), + "Attempt to disable DS_LCLK Feature Failed!", + return -EINVAL); + data->smu_features[GNLD_DS_LCLK].enabled = false; + } + + if (data->smu_features[GNLD_DS_DCEFCLK].supported) { + PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, + false, data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap), + "Attempt to disable DS_DCEFCLK Feature Failed!", + return -EINVAL); + data->smu_features[GNLD_DS_DCEFCLK].enabled = false; + } + return 0; } @@ -2550,9 +2703,9 @@ static int vega10_stop_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap) if(data->smu_features[GNLD_LED_DISPLAY].supported == true){ PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, - true, data->smu_features[GNLD_LED_DISPLAY].smu_feature_bitmap), - "Attempt to Enable LED DPM feature Failed!", return -EINVAL); - data->smu_features[GNLD_LED_DISPLAY].enabled = true; + false, data->smu_features[GNLD_LED_DISPLAY].smu_feature_bitmap), + "Attempt to disable LED DPM feature failed!", return -EINVAL); + data->smu_features[GNLD_LED_DISPLAY].enabled = false; } for (i = 0; i < GNLD_DPM_MAX; i++) { @@ -2676,11 +2829,6 @@ static int vega10_enable_dpm_tasks(struct pp_hwmgr *hwmgr) "Failed to enable VR hot feature!", result = tmp_result); - tmp_result = vega10_enable_ulv(hwmgr); - PP_ASSERT_WITH_CODE(!tmp_result, - "Failed to enable ULV!", - result = tmp_result); - tmp_result = vega10_enable_deep_sleep_master_switch(hwmgr); PP_ASSERT_WITH_CODE(!tmp_result, "Failed to enable deep sleep master switch!", @@ -2700,6 +2848,11 @@ static int vega10_enable_dpm_tasks(struct pp_hwmgr *hwmgr) "Failed to power control set level!", result = tmp_result); + tmp_result = vega10_enable_ulv(hwmgr); + PP_ASSERT_WITH_CODE(!tmp_result, + "Failed to enable ULV!", + result = tmp_result); + return result; } @@ -2886,7 +3039,7 @@ static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, /* result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/ minimum_clocks.engineClock = hwmgr->display_config.min_core_set_clock; - /* minimum_clocks.memoryClock = hwmgr->display_config.min_mem_set_clock; */ + minimum_clocks.memoryClock = hwmgr->display_config.min_mem_set_clock; if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) { @@ -2978,11 +3131,10 @@ static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, vega10_ps->performance_levels[0].gfx_clock = sclk; vega10_ps->performance_levels[0].mem_clock = mclk; - vega10_ps->performance_levels[1].gfx_clock = - (vega10_ps->performance_levels[1].gfx_clock >= - vega10_ps->performance_levels[0].gfx_clock) ? - vega10_ps->performance_levels[1].gfx_clock : - vega10_ps->performance_levels[0].gfx_clock; + if (vega10_ps->performance_levels[1].gfx_clock < + vega10_ps->performance_levels[0].gfx_clock) + vega10_ps->performance_levels[0].gfx_clock = + vega10_ps->performance_levels[1].gfx_clock; if (disable_mclk_switching) { /* Set Mclk the max of level 0 and level 1 */ @@ -3005,8 +3157,8 @@ static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, } else { if (vega10_ps->performance_levels[1].mem_clock < vega10_ps->performance_levels[0].mem_clock) - vega10_ps->performance_levels[1].mem_clock = - vega10_ps->performance_levels[0].mem_clock; + vega10_ps->performance_levels[0].mem_clock = + vega10_ps->performance_levels[1].mem_clock; } if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, @@ -3673,6 +3825,18 @@ static int vega10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low) [vega10_ps->performance_level_count-1].mem_clock; } +static int vega10_get_gpu_power(struct pp_hwmgr *hwmgr, + struct pp_gpu_power *query) +{ + PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr->smumgr, + PPSMC_MSG_GetCurrPkgPwr), + "Failed to get current package power!", + return -EINVAL); + + return vega10_read_arg_from_smc(hwmgr->smumgr, + &query->average_gpu_power); +} + static int vega10_read_sensor(struct pp_hwmgr *hwmgr, int idx, void *value, int *size) { @@ -3718,6 +3882,14 @@ static int vega10_read_sensor(struct pp_hwmgr *hwmgr, int idx, *((uint32_t *)value) = data->vce_power_gated ? 0 : 1; *size = 4; break; + case AMDGPU_PP_SENSOR_GPU_POWER: + if (*size < sizeof(struct pp_gpu_power)) + ret = -EINVAL; + else { + *size = sizeof(struct pp_gpu_power); + ret = vega10_get_gpu_power(hwmgr, (struct pp_gpu_power *)value); + } + break; default: ret = -EINVAL; break; @@ -3738,7 +3910,7 @@ int vega10_display_clock_voltage_request(struct pp_hwmgr *hwmgr, { int result = 0; enum amd_pp_clock_type clk_type = clock_req->clock_type; - uint32_t clk_freq = clock_req->clock_freq_in_khz / 100; + uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000; DSPCLK_e clk_select = 0; uint32_t clk_request = 0; @@ -3771,6 +3943,26 @@ int vega10_display_clock_voltage_request(struct pp_hwmgr *hwmgr, return result; } +static uint8_t vega10_get_uclk_index(struct pp_hwmgr *hwmgr, + struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table, + uint32_t frequency) +{ + uint8_t count; + uint8_t i; + + if (mclk_table == NULL || mclk_table->count == 0) + return 0; + + count = (uint8_t)(mclk_table->count); + + for(i = 0; i < count; i++) { + if(mclk_table->entries[i].clk >= frequency) + return i; + } + + return i-1; +} + static int vega10_notify_smc_display_config_after_ps_adjustment( struct pp_hwmgr *hwmgr) { @@ -3778,6 +3970,10 @@ static int vega10_notify_smc_display_config_after_ps_adjustment( (struct vega10_hwmgr *)(hwmgr->backend); struct vega10_single_dpm_table *dpm_table = &data->dpm_table.dcef_table; + struct phm_ppt_v2_information *table_info = + (struct phm_ppt_v2_information *)hwmgr->pptable; + struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table = table_info->vdd_dep_on_mclk; + uint32_t idx; uint32_t num_active_disps = 0; struct cgs_display_info info = {0}; struct PP_Clocks min_clocks = {0}; @@ -3797,6 +3993,7 @@ static int vega10_notify_smc_display_config_after_ps_adjustment( min_clocks.dcefClock = hwmgr->display_config.min_dcef_set_clk; min_clocks.dcefClockInSR = hwmgr->display_config.min_dcef_deep_sleep_set_clk; + min_clocks.memoryClock = hwmgr->display_config.min_mem_set_clock; for (i = 0; i < dpm_table->count; i++) { if (dpm_table->dpm_levels[i].value == min_clocks.dcefClock) @@ -3809,12 +4006,20 @@ static int vega10_notify_smc_display_config_after_ps_adjustment( if (!vega10_display_clock_voltage_request(hwmgr, &clock_req)) { PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter( hwmgr->smumgr, PPSMC_MSG_SetMinDeepSleepDcefclk, - min_clocks.dcefClockInSR), + min_clocks.dcefClockInSR /100), "Attempt to set divider for DCEFCLK Failed!",); - } else + } else { pr_info("Attempt to set Hard Min for DCEFCLK Failed!"); - } else + } + } else { pr_info("Cannot find requested DCEFCLK!"); + } + + if (min_clocks.memoryClock != 0) { + idx = vega10_get_uclk_index(hwmgr, mclk_table, min_clocks.memoryClock); + smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_SetSoftMinUclkByIndex, idx); + data->dpm_table.mem_table.dpm_state.soft_min_level= idx; + } return 0; } @@ -4219,11 +4424,6 @@ static int vega10_force_clock_level(struct pp_hwmgr *hwmgr, if (mask & (1 << i)) break; } - - for (i = 0; i < 32; i++) { - if (mask & (1 << i)) - break; - } data->smc_state_table.mem_boot_level = i; for (i = 31; i >= 0; i--) { @@ -4466,6 +4666,14 @@ static int vega10_disable_dpm_tasks(struct pp_hwmgr *hwmgr) PP_ASSERT_WITH_CODE((tmp_result == 0), "Failed to stop DPM!", result = tmp_result); + tmp_result = vega10_disable_deep_sleep_master_switch(hwmgr); + PP_ASSERT_WITH_CODE((tmp_result == 0), + "Failed to disable deep sleep!", result = tmp_result); + + tmp_result = vega10_disable_ulv(hwmgr); + PP_ASSERT_WITH_CODE((tmp_result == 0), + "Failed to disable ulv!", result = tmp_result); + return result; } @@ -4483,6 +4691,170 @@ static int vega10_power_off_asic(struct pp_hwmgr *hwmgr) return result; } +static void vega10_find_min_clock_index(struct pp_hwmgr *hwmgr, + uint32_t *sclk_idx, uint32_t *mclk_idx, + uint32_t min_sclk, uint32_t min_mclk) +{ + struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend); + struct vega10_dpm_table *dpm_table = &(data->dpm_table); + uint32_t i; + + for (i = 0; i < dpm_table->gfx_table.count; i++) { + if (dpm_table->gfx_table.dpm_levels[i].enabled && + dpm_table->gfx_table.dpm_levels[i].value >= min_sclk) { + *sclk_idx = i; + break; + } + } + + for (i = 0; i < dpm_table->mem_table.count; i++) { + if (dpm_table->mem_table.dpm_levels[i].enabled && + dpm_table->mem_table.dpm_levels[i].value >= min_mclk) { + *mclk_idx = i; + break; + } + } +} + +static int vega10_set_power_profile_state(struct pp_hwmgr *hwmgr, + struct amd_pp_profile *request) +{ + struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend); + uint32_t sclk_idx = ~0, mclk_idx = ~0; + + if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_AUTO) + return -EINVAL; + + vega10_find_min_clock_index(hwmgr, &sclk_idx, &mclk_idx, + request->min_sclk, request->min_mclk); + + if (sclk_idx != ~0) { + if (!data->registry_data.sclk_dpm_key_disabled) + PP_ASSERT_WITH_CODE( + !smum_send_msg_to_smc_with_parameter( + hwmgr->smumgr, + PPSMC_MSG_SetSoftMinGfxclkByIndex, + sclk_idx), + "Failed to set soft min sclk index!", + return -EINVAL); + } + + if (mclk_idx != ~0) { + if (!data->registry_data.mclk_dpm_key_disabled) + PP_ASSERT_WITH_CODE( + !smum_send_msg_to_smc_with_parameter( + hwmgr->smumgr, + PPSMC_MSG_SetSoftMinUclkByIndex, + mclk_idx), + "Failed to set soft min mclk index!", + return -EINVAL); + } + + return 0; +} + +static int vega10_get_sclk_od(struct pp_hwmgr *hwmgr) +{ + struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend); + struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table); + struct vega10_single_dpm_table *golden_sclk_table = + &(data->golden_dpm_table.gfx_table); + int value; + + value = (sclk_table->dpm_levels[sclk_table->count - 1].value - + golden_sclk_table->dpm_levels + [golden_sclk_table->count - 1].value) * + 100 / + golden_sclk_table->dpm_levels + [golden_sclk_table->count - 1].value; + + return value; +} + +static int vega10_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value) +{ + struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend); + struct vega10_single_dpm_table *golden_sclk_table = + &(data->golden_dpm_table.gfx_table); + struct pp_power_state *ps; + struct vega10_power_state *vega10_ps; + + ps = hwmgr->request_ps; + + if (ps == NULL) + return -EINVAL; + + vega10_ps = cast_phw_vega10_power_state(&ps->hardware); + + vega10_ps->performance_levels + [vega10_ps->performance_level_count - 1].gfx_clock = + golden_sclk_table->dpm_levels + [golden_sclk_table->count - 1].value * + value / 100 + + golden_sclk_table->dpm_levels + [golden_sclk_table->count - 1].value; + + if (vega10_ps->performance_levels + [vega10_ps->performance_level_count - 1].gfx_clock > + hwmgr->platform_descriptor.overdriveLimit.engineClock) + vega10_ps->performance_levels + [vega10_ps->performance_level_count - 1].gfx_clock = + hwmgr->platform_descriptor.overdriveLimit.engineClock; + + return 0; +} + +static int vega10_get_mclk_od(struct pp_hwmgr *hwmgr) +{ + struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend); + struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table); + struct vega10_single_dpm_table *golden_mclk_table = + &(data->golden_dpm_table.mem_table); + int value; + + value = (mclk_table->dpm_levels + [mclk_table->count - 1].value - + golden_mclk_table->dpm_levels + [golden_mclk_table->count - 1].value) * + 100 / + golden_mclk_table->dpm_levels + [golden_mclk_table->count - 1].value; + + return value; +} + +static int vega10_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value) +{ + struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend); + struct vega10_single_dpm_table *golden_mclk_table = + &(data->golden_dpm_table.mem_table); + struct pp_power_state *ps; + struct vega10_power_state *vega10_ps; + + ps = hwmgr->request_ps; + + if (ps == NULL) + return -EINVAL; + + vega10_ps = cast_phw_vega10_power_state(&ps->hardware); + + vega10_ps->performance_levels + [vega10_ps->performance_level_count - 1].mem_clock = + golden_mclk_table->dpm_levels + [golden_mclk_table->count - 1].value * + value / 100 + + golden_mclk_table->dpm_levels + [golden_mclk_table->count - 1].value; + + if (vega10_ps->performance_levels + [vega10_ps->performance_level_count - 1].mem_clock > + hwmgr->platform_descriptor.overdriveLimit.memoryClock) + vega10_ps->performance_levels + [vega10_ps->performance_level_count - 1].mem_clock = + hwmgr->platform_descriptor.overdriveLimit.memoryClock; + + return 0; +} static const struct pp_hwmgr_func vega10_hwmgr_funcs = { .backend_init = vega10_hwmgr_backend_init, @@ -4531,6 +4903,12 @@ static const struct pp_hwmgr_func vega10_hwmgr_funcs = { vega10_check_smc_update_required_for_display_configuration, .power_off_asic = vega10_power_off_asic, .disable_smc_firmware_ctf = vega10_thermal_disable_alert, + .set_power_profile_state = vega10_set_power_profile_state, + .get_sclk_od = vega10_get_sclk_od, + .set_sclk_od = vega10_set_sclk_od, + .get_mclk_od = vega10_get_mclk_od, + .set_mclk_od = vega10_set_mclk_od, + .avfs_control = vega10_avfs_enable, }; int vega10_hwmgr_init(struct pp_hwmgr *hwmgr) diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h index 1912e086c0cf..6e5c5b99593b 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h @@ -185,6 +185,7 @@ struct vega10_vbios_boot_state { uint32_t gfx_clock; uint32_t mem_clock; uint32_t soc_clock; + uint32_t dcef_clock; }; #define DPMTABLE_OD_UPDATE_SCLK 0x00000001 @@ -210,6 +211,7 @@ struct vega10_smc_state_table { PPTable_t pp_table; Watermarks_t water_marks_table; AvfsTable_t avfs_table; + AvfsFuseOverride_t avfs_fuse_override_table; }; struct vega10_mclk_latency_entries { diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_pptable.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_pptable.h index 6a907c93fd9c..52beea3bf6b7 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_pptable.h +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_pptable.h @@ -355,6 +355,37 @@ typedef struct _ATOM_Vega10_PowerTune_Table_V2 USHORT usTemperatureLimitTedge; } ATOM_Vega10_PowerTune_Table_V2; +typedef struct _ATOM_Vega10_PowerTune_Table_V3 +{ + UCHAR ucRevId; + USHORT usSocketPowerLimit; + USHORT usBatteryPowerLimit; + USHORT usSmallPowerLimit; + USHORT usTdcLimit; + USHORT usEdcLimit; + USHORT usSoftwareShutdownTemp; + USHORT usTemperatureLimitHotSpot; + USHORT usTemperatureLimitLiquid1; + USHORT usTemperatureLimitLiquid2; + USHORT usTemperatureLimitHBM; + USHORT usTemperatureLimitVrSoc; + USHORT usTemperatureLimitVrMem; + USHORT usTemperatureLimitPlx; + USHORT usLoadLineResistance; + UCHAR ucLiquid1_I2C_address; + UCHAR ucLiquid2_I2C_address; + UCHAR ucLiquid_I2C_Line; + UCHAR ucVr_I2C_address; + UCHAR ucVr_I2C_Line; + UCHAR ucPlx_I2C_address; + UCHAR ucPlx_I2C_Line; + USHORT usTemperatureLimitTedge; + USHORT usBoostStartTemperature; + USHORT usBoostStopTemperature; + ULONG ulBoostClock; + ULONG Reserved[2]; +} ATOM_Vega10_PowerTune_Table_V3; + typedef struct _ATOM_Vega10_Hard_Limit_Record { ULONG ulSOCCLKLimit; ULONG ulGFXCLKLimit; diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c index 00e95511e19a..2b892e47d8dc 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c @@ -54,6 +54,7 @@ static const void *get_powerplay_table(struct pp_hwmgr *hwmgr) &size, &frev, &crev); hwmgr->soft_pp_table = table_address; /*Cache the result in RAM.*/ + hwmgr->soft_pp_table_size = size; } return table_address; @@ -210,10 +211,8 @@ static int init_thermal_controller( fan_table_v2->ucFanParameters & ATOM_VEGA10_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK; hwmgr->thermal_controller.fanInfo.ulMinRPM = fan_table_v2->ucFanMinRPM * 100UL; hwmgr->thermal_controller.fanInfo.ulMaxRPM = fan_table_v2->ucFanMaxRPM * 100UL; - phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl); - hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity = le16_to_cpu(fan_table_v2->usFanOutputSensitivity); hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM = @@ -366,6 +365,7 @@ static int get_tdp_table( uint8_t sda; const ATOM_Vega10_PowerTune_Table *power_tune_table; const ATOM_Vega10_PowerTune_Table_V2 *power_tune_table_v2; + const ATOM_Vega10_PowerTune_Table_V3 *power_tune_table_v3; table_size = sizeof(uint32_t) + sizeof(struct phm_tdp_table); @@ -408,7 +408,7 @@ static int get_tdp_table( tdp_table->ucPlx_I2C_Line = power_tune_table->ucPlx_I2C_LineSCL; tdp_table->ucPlx_I2C_LineSDA = power_tune_table->ucPlx_I2C_LineSDA; hwmgr->platform_descriptor.LoadLineSlope = le16_to_cpu(power_tune_table->usLoadLineResistance); - } else { + } else if (table->ucRevId == 6) { power_tune_table_v2 = (ATOM_Vega10_PowerTune_Table_V2 *)table; tdp_table->usMaximumPowerDeliveryLimit = le16_to_cpu(power_tune_table_v2->usSocketPowerLimit); tdp_table->usTDC = le16_to_cpu(power_tune_table_v2->usTdcLimit); @@ -454,6 +454,47 @@ static int get_tdp_table( hwmgr->platform_descriptor.LoadLineSlope = le16_to_cpu(power_tune_table_v2->usLoadLineResistance); + } else { + power_tune_table_v3 = (ATOM_Vega10_PowerTune_Table_V3 *)table; + tdp_table->usMaximumPowerDeliveryLimit = power_tune_table_v3->usSocketPowerLimit; + tdp_table->usTDC = power_tune_table_v3->usTdcLimit; + tdp_table->usEDCLimit = power_tune_table_v3->usEdcLimit; + tdp_table->usSoftwareShutdownTemp = power_tune_table_v3->usSoftwareShutdownTemp; + tdp_table->usTemperatureLimitTedge = power_tune_table_v3->usTemperatureLimitTedge; + tdp_table->usTemperatureLimitHotspot = power_tune_table_v3->usTemperatureLimitHotSpot; + tdp_table->usTemperatureLimitLiquid1 = power_tune_table_v3->usTemperatureLimitLiquid1; + tdp_table->usTemperatureLimitLiquid2 = power_tune_table_v3->usTemperatureLimitLiquid2; + tdp_table->usTemperatureLimitHBM = power_tune_table_v3->usTemperatureLimitHBM; + tdp_table->usTemperatureLimitVrVddc = power_tune_table_v3->usTemperatureLimitVrSoc; + tdp_table->usTemperatureLimitVrMvdd = power_tune_table_v3->usTemperatureLimitVrMem; + tdp_table->usTemperatureLimitPlx = power_tune_table_v3->usTemperatureLimitPlx; + tdp_table->ucLiquid1_I2C_address = power_tune_table_v3->ucLiquid1_I2C_address; + tdp_table->ucLiquid2_I2C_address = power_tune_table_v3->ucLiquid2_I2C_address; + tdp_table->usBoostStartTemperature = power_tune_table_v3->usBoostStartTemperature; + tdp_table->usBoostStopTemperature = power_tune_table_v3->usBoostStopTemperature; + tdp_table->ulBoostClock = power_tune_table_v3->ulBoostClock; + + get_scl_sda_value(power_tune_table_v3->ucLiquid_I2C_Line, &scl, &sda); + + tdp_table->ucLiquid_I2C_Line = scl; + tdp_table->ucLiquid_I2C_LineSDA = sda; + + tdp_table->ucVr_I2C_address = power_tune_table_v3->ucVr_I2C_address; + + get_scl_sda_value(power_tune_table_v3->ucVr_I2C_Line, &scl, &sda); + + tdp_table->ucVr_I2C_Line = scl; + tdp_table->ucVr_I2C_LineSDA = sda; + + tdp_table->ucPlx_I2C_address = power_tune_table_v3->ucPlx_I2C_address; + + get_scl_sda_value(power_tune_table_v3->ucPlx_I2C_Line, &scl, &sda); + + tdp_table->ucPlx_I2C_Line = scl; + tdp_table->ucPlx_I2C_LineSDA = sda; + + hwmgr->platform_descriptor.LoadLineSlope = + le16_to_cpu(power_tune_table_v3->usLoadLineResistance); } *info_tdp_table = tdp_table; @@ -566,7 +607,7 @@ static int get_gfxclk_voltage_dependency_table( clk_table->entries[i].clk = le32_to_cpu(clk_dep_table->entries[i].ulClk); clk_table->entries[i].cks_enable = - (((clk_dep_table->entries[i].usCKSVOffsetandDisable & 0x80) + (((clk_dep_table->entries[i].usCKSVOffsetandDisable & 0x8000) >> 15) == 0) ? 1 : 0; clk_table->entries[i].cks_voffset = (clk_dep_table->entries[i].usCKSVOffsetandDisable & 0x7F); diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c index 83e40fe51b62..e7ab8eb8a0cf 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c @@ -439,9 +439,6 @@ static int vega10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr, cgs_write_register(hwmgr->device, reg, val); - reg = soc15_get_register_offset(THM_HWID, 0, - mmTHM_TCON_HTC_BASE_IDX, mmTHM_TCON_HTC); - return 0; } diff --git a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h index 4e39f35bb745..07e9c0b5915d 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h +++ b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h @@ -273,7 +273,10 @@ enum amd_pp_clock_type { amd_pp_dcef_clock, amd_pp_soc_clock, amd_pp_pixel_clock, - amd_pp_phy_clock + amd_pp_phy_clock, + amd_pp_dcf_clock, + amd_pp_dpp_clock, + amd_pp_f_clock = amd_pp_dcef_clock, }; #define MAX_NUM_CLOCKS 16 diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h index 805b9df452a3..47e57bd2c36f 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h +++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h @@ -99,7 +99,8 @@ enum PHM_BackEnd_Magic { PHM_CIslands_Magic = 0x38AC78B0, PHM_Kv_Magic = 0xDCBBABC0, PHM_VIslands_Magic = 0x20130307, - PHM_Cz_Magic = 0x67DCBA25 + PHM_Cz_Magic = 0x67DCBA25, + PHM_Rv_Magic = 0x20161121 }; @@ -136,11 +137,14 @@ struct phm_vce_arbiter { struct phm_gfx_arbiter { uint32_t sclk; + uint32_t sclk_hard_min; uint32_t mclk; uint32_t sclk_over_drive; uint32_t mclk_over_drive; uint32_t sclk_threshold; uint32_t num_cus; + uint32_t gfxclk; + uint32_t fclk; }; /* Entries in the master tables */ @@ -488,6 +492,9 @@ struct phm_tdp_table { uint8_t ucVr_I2C_LineSDA; uint8_t ucPlx_I2C_LineSDA; uint32_t usBoostPowerLimit; + uint16_t usBoostStartTemperature; + uint16_t usBoostStopTemperature; + uint32_t ulBoostClock; }; struct phm_ppm_table { @@ -624,7 +631,7 @@ struct phm_dynamic_state_info { uint32_t vddc_vddci_delta; uint32_t min_vddc_for_pcie_gen2; struct phm_cac_leakage_table *cac_leakage_table; - struct phm_phase_shedding_limits_table *vddc_phase_shed_limits_table; + struct phm_phase_shedding_limits_table *vddc_phase_shed_limits_table; struct phm_vce_clock_voltage_dependency_table *vce_clock_voltage_dependency_table; @@ -637,8 +644,8 @@ struct phm_dynamic_state_info { struct phm_ppm_table *ppm_parameter_table; struct phm_cac_tdp_table *cac_dtp_table; - struct phm_clock_voltage_dependency_table *vdd_gfx_dependency_on_sclk; - struct phm_vq_budgeting_table *vq_budgeting_table; + struct phm_clock_voltage_dependency_table *vdd_gfx_dependency_on_sclk; + struct phm_vq_budgeting_table *vq_budgeting_table; }; struct pp_fan_info { @@ -822,6 +829,7 @@ extern void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr); extern int smu7_init_function_pointers(struct pp_hwmgr *hwmgr); extern int vega10_hwmgr_init(struct pp_hwmgr *hwmgr); +extern int rv_init_function_pointers(struct pp_hwmgr *hwmgr); extern int phm_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint32_t sclk, uint16_t id, uint16_t *voltage); diff --git a/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h new file mode 100644 index 000000000000..e0e106f1b23a --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h @@ -0,0 +1,77 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef RAVEN_PP_SMC_H +#define RAVEN_PP_SMC_H + +#pragma pack(push, 1) + +#define PPSMC_Result_OK 0x1 +#define PPSMC_Result_Failed 0xFF +#define PPSMC_Result_UnknownCmd 0xFE +#define PPSMC_Result_CmdRejectedPrereq 0xFD +#define PPSMC_Result_CmdRejectedBusy 0xFC + +#define PPSMC_MSG_TestMessage 0x1 +#define PPSMC_MSG_GetSmuVersion 0x2 +#define PPSMC_MSG_GetDriverIfVersion 0x3 +#define PPSMC_MSG_PowerUpGfx 0x6 +#define PPSMC_MSG_EnableGfxOff 0x7 +#define PPSMC_MSG_DisableGfxOff 0x8 +#define PPSMC_MSG_PowerDownIspByTile 0x9 +#define PPSMC_MSG_PowerUpIspByTile 0xA +#define PPSMC_MSG_PowerDownVcn 0xB +#define PPSMC_MSG_PowerUpVcn 0xC +#define PPSMC_MSG_PowerDownSdma 0xD +#define PPSMC_MSG_PowerUpSdma 0xE +#define PPSMC_MSG_SetHardMinIspclkByFreq 0xF +#define PPSMC_MSG_SetHardMinVcn 0x10 +#define PPSMC_MSG_SetMinDisplayClock 0x11 +#define PPSMC_MSG_SetHardMinFclkByFreq 0x12 +#define PPSMC_MSG_SetAllowFclkSwitch 0x13 +#define PPSMC_MSG_SetMinVideoGfxclkFreq 0x14 +#define PPSMC_MSG_ActiveProcessNotify 0x15 +#define PPSMC_MSG_SetCustomPolicy 0x16 +#define PPSMC_MSG_SetVideoFps 0x17 +#define PPSMC_MSG_SetDisplayCount 0x18 +#define PPSMC_MSG_QueryPowerLimit 0x19 +#define PPSMC_MSG_SetDriverDramAddrHigh 0x1A +#define PPSMC_MSG_SetDriverDramAddrLow 0x1B +#define PPSMC_MSG_TransferTableSmu2Dram 0x1C +#define PPSMC_MSG_TransferTableDram2Smu 0x1D +#define PPSMC_MSG_ControlGfxRM 0x1E +#define PPSMC_MSG_SetGfxclkOverdriveByFreqVid 0x1F +#define PPSMC_MSG_SetHardMinDcefclkByFreq 0x20 +#define PPSMC_MSG_SetHardMinSocclkByFreq 0x21 +#define PPSMC_MSG_SetMinVddcrSocVoltage 0x22 +#define PPSMC_MSG_SetMinVideoFclkFreq 0x23 +#define PPSMC_MSG_SetMinDeepSleepDcefclk 0x24 +#define PPSMC_Message_Count 0x25 + +typedef uint16_t PPSMC_Result; +typedef int PPSMC_Msg; + + +#pragma pack(pop) + +#endif diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu10.h b/drivers/gpu/drm/amd/powerplay/inc/smu10.h new file mode 100644 index 000000000000..9e837a5014c5 --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/inc/smu10.h @@ -0,0 +1,188 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef SMU10_H +#define SMU10_H + +#pragma pack(push, 1) + +#define ENABLE_DEBUG_FEATURES + +/* Feature Control Defines */ +#define FEATURE_CCLK_CONTROLLER_BIT 0 +#define FEATURE_FAN_CONTROLLER_BIT 1 +#define FEATURE_DATA_CALCULATION_BIT 2 +#define FEATURE_PPT_BIT 3 +#define FEATURE_TDC_BIT 4 +#define FEATURE_THERMAL_BIT 5 +#define FEATURE_FIT_BIT 6 +#define FEATURE_EDC_BIT 7 +#define FEATURE_PLL_POWER_DOWN_BIT 8 +#define FEATURE_ULV_BIT 9 +#define FEATURE_VDDOFF_BIT 10 +#define FEATURE_VCN_DPM_BIT 11 +#define FEATURE_ACP_DPM_BIT 12 +#define FEATURE_ISP_DPM_BIT 13 +#define FEATURE_FCLK_DPM_BIT 14 +#define FEATURE_SOCCLK_DPM_BIT 15 +#define FEATURE_MP0CLK_DPM_BIT 16 +#define FEATURE_LCLK_DPM_BIT 17 +#define FEATURE_SHUBCLK_DPM_BIT 18 +#define FEATURE_DCEFCLK_DPM_BIT 19 +#define FEATURE_GFX_DPM_BIT 20 +#define FEATURE_DS_GFXCLK_BIT 21 +#define FEATURE_DS_SOCCLK_BIT 22 +#define FEATURE_DS_LCLK_BIT 23 +#define FEATURE_DS_DCEFCLK_BIT 24 +#define FEATURE_DS_SHUBCLK_BIT 25 +#define FEATURE_RM_BIT 26 +#define FEATURE_S0i2_BIT 27 +#define FEATURE_WHISPER_MODE_BIT 28 +#define FEATURE_DS_FCLK_BIT 29 +#define FEATURE_DS_SMNCLK_BIT 30 +#define FEATURE_DS_MP1CLK_BIT 31 +#define FEATURE_DS_MP0CLK_BIT 32 +#define FEATURE_MGCG_BIT 33 +#define FEATURE_DS_FUSE_SRAM_BIT 34 +#define FEATURE_GFX_CKS 35 +#define FEATURE_PSI0_BIT 36 +#define FEATURE_PROCHOT_BIT 37 +#define FEATURE_CPUOFF_BIT 38 +#define FEATURE_STAPM_BIT 39 +#define FEATURE_CORE_CSTATES_BIT 40 +#define FEATURE_SPARE_41_BIT 41 +#define FEATURE_SPARE_42_BIT 42 +#define FEATURE_SPARE_43_BIT 43 +#define FEATURE_SPARE_44_BIT 44 +#define FEATURE_SPARE_45_BIT 45 +#define FEATURE_SPARE_46_BIT 46 +#define FEATURE_SPARE_47_BIT 47 +#define FEATURE_SPARE_48_BIT 48 +#define FEATURE_SPARE_49_BIT 49 +#define FEATURE_SPARE_50_BIT 50 +#define FEATURE_SPARE_51_BIT 51 +#define FEATURE_SPARE_52_BIT 52 +#define FEATURE_SPARE_53_BIT 53 +#define FEATURE_SPARE_54_BIT 54 +#define FEATURE_SPARE_55_BIT 55 +#define FEATURE_SPARE_56_BIT 56 +#define FEATURE_SPARE_57_BIT 57 +#define FEATURE_SPARE_58_BIT 58 +#define FEATURE_SPARE_59_BIT 59 +#define FEATURE_SPARE_60_BIT 60 +#define FEATURE_SPARE_61_BIT 61 +#define FEATURE_SPARE_62_BIT 62 +#define FEATURE_SPARE_63_BIT 63 + +#define NUM_FEATURES 64 + +#define FEATURE_CCLK_CONTROLLER_MASK (1 << FEATURE_CCLK_CONTROLLER_BIT) +#define FEATURE_FAN_CONTROLLER_MASK (1 << FEATURE_FAN_CONTROLLER_BIT) +#define FEATURE_DATA_CALCULATION_MASK (1 << FEATURE_DATA_CALCULATION_BIT) +#define FEATURE_PPT_MASK (1 << FEATURE_PPT_BIT) +#define FEATURE_TDC_MASK (1 << FEATURE_TDC_BIT) +#define FEATURE_THERMAL_MASK (1 << FEATURE_THERMAL_BIT) +#define FEATURE_FIT_MASK (1 << FEATURE_FIT_BIT) +#define FEATURE_EDC_MASK (1 << FEATURE_EDC_BIT) +#define FEATURE_PLL_POWER_DOWN_MASK (1 << FEATURE_PLL_POWER_DOWN_BIT) +#define FEATURE_ULV_MASK (1 << FEATURE_ULV_BIT) +#define FEATURE_VDDOFF_MASK (1 << FEATURE_VDDOFF_BIT) +#define FEATURE_VCN_DPM_MASK (1 << FEATURE_VCN_DPM_BIT) +#define FEATURE_ACP_DPM_MASK (1 << FEATURE_ACP_DPM_BIT) +#define FEATURE_ISP_DPM_MASK (1 << FEATURE_ISP_DPM_BIT) +#define FEATURE_FCLK_DPM_MASK (1 << FEATURE_FCLK_DPM_BIT) +#define FEATURE_SOCCLK_DPM_MASK (1 << FEATURE_SOCCLK_DPM_BIT) +#define FEATURE_MP0CLK_DPM_MASK (1 << FEATURE_MP0CLK_DPM_BIT) +#define FEATURE_LCLK_DPM_MASK (1 << FEATURE_LCLK_DPM_BIT) +#define FEATURE_SHUBCLK_DPM_MASK (1 << FEATURE_SHUBCLK_DPM_BIT) +#define FEATURE_DCEFCLK_DPM_MASK (1 << FEATURE_DCEFCLK_DPM_BIT) +#define FEATURE_GFX_DPM_MASK (1 << FEATURE_GFX_DPM_BIT) +#define FEATURE_DS_GFXCLK_MASK (1 << FEATURE_DS_GFXCLK_BIT) +#define FEATURE_DS_SOCCLK_MASK (1 << FEATURE_DS_SOCCLK_BIT) +#define FEATURE_DS_LCLK_MASK (1 << FEATURE_DS_LCLK_BIT) +#define FEATURE_DS_DCEFCLK_MASK (1 << FEATURE_DS_DCEFCLK_BIT) +#define FEATURE_DS_SHUBCLK_MASK (1 << FEATURE_DS_SHUBCLK_BIT) +#define FEATURE_RM_MASK (1 << FEATURE_RM_BIT) +#define FEATURE_DS_FCLK_MASK (1 << FEATURE_DS_FCLK_BIT) +#define FEATURE_DS_SMNCLK_MASK (1 << FEATURE_DS_SMNCLK_BIT) +#define FEATURE_DS_MP1CLK_MASK (1 << FEATURE_DS_MP1CLK_BIT) +#define FEATURE_DS_MP0CLK_MASK (1 << FEATURE_DS_MP0CLK_BIT) +#define FEATURE_MGCG_MASK (1 << FEATURE_MGCG_BIT) +#define FEATURE_DS_FUSE_SRAM_MASK (1 << FEATURE_DS_FUSE_SRAM_BIT) +#define FEATURE_PSI0_MASK (1 << FEATURE_PSI0_BIT) +#define FEATURE_STAPM_MASK (1 << FEATURE_STAPM_BIT) +#define FEATURE_PROCHOT_MASK (1 << FEATURE_PROCHOT_BIT) +#define FEATURE_CPUOFF_MASK (1 << FEATURE_CPUOFF_BIT) +#define FEATURE_CORE_CSTATES_MASK (1 << FEATURE_CORE_CSTATES_BIT) + +/* Workload bits */ +#define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 0 +#define WORKLOAD_PPLIB_VIDEO_BIT 2 +#define WORKLOAD_PPLIB_VR_BIT 3 +#define WORKLOAD_PPLIB_COMPUTE_BIT 4 +#define WORKLOAD_PPLIB_CUSTOM_BIT 5 +#define WORKLOAD_PPLIB_COUNT 6 + +typedef struct { + /* MP1_EXT_SCRATCH0 */ + uint32_t CurrLevel_ACP : 4; + uint32_t CurrLevel_ISP : 4; + uint32_t CurrLevel_VCN : 4; + uint32_t CurrLevel_LCLK : 4; + uint32_t CurrLevel_MP0CLK : 4; + uint32_t CurrLevel_FCLK : 4; + uint32_t CurrLevel_SOCCLK : 4; + uint32_t CurrLevel_DCEFCLK : 4; + /* MP1_EXT_SCRATCH1 */ + uint32_t TargLevel_ACP : 4; + uint32_t TargLevel_ISP : 4; + uint32_t TargLevel_VCN : 4; + uint32_t TargLevel_LCLK : 4; + uint32_t TargLevel_MP0CLK : 4; + uint32_t TargLevel_FCLK : 4; + uint32_t TargLevel_SOCCLK : 4; + uint32_t TargLevel_DCEFCLK : 4; + /* MP1_EXT_SCRATCH2 */ + uint32_t CurrLevel_SHUBCLK : 4; + uint32_t TargLevel_SHUBCLK : 4; + uint32_t InUlv : 1; + uint32_t InS0i2 : 1; + uint32_t InWhisperMode : 1; + uint32_t Reserved : 21; + /* MP1_EXT_SCRATCH3-4 */ + uint32_t Reserved2[2]; + /* MP1_EXT_SCRATCH5 */ + uint32_t FeatureStatus[NUM_FEATURES / 32]; +} FwStatus_t; + +#define TABLE_BIOS_IF 0 /* Called by BIOS */ +#define TABLE_WATERMARKS 1 /* Called by Driver */ +#define TABLE_CUSTOM_DPM 2 /* Called by Driver */ +#define TABLE_PMSTATUSLOG 3 /* Called by Tools for Agm logging */ +#define TABLE_DPMCLOCKS 4 /* Called by Driver */ +#define TABLE_MOMENTARY_PM 5 /* Called by Tools */ +#define TABLE_COUNT 6 + +#pragma pack(pop) + +#endif diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu10_driver_if.h b/drivers/gpu/drm/amd/powerplay/inc/smu10_driver_if.h new file mode 100644 index 000000000000..dea8fe93da63 --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/inc/smu10_driver_if.h @@ -0,0 +1,116 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef SMU10_DRIVER_IF_H +#define SMU10_DRIVER_IF_H + +#define SMU10_DRIVER_IF_VERSION 0x6 + +#define NUM_DSPCLK_LEVELS 8 + +typedef struct { + int32_t value; + uint32_t numFractionalBits; +} FloatInIntFormat_t; + +typedef enum { + DSPCLK_DCEFCLK = 0, + DSPCLK_DISPCLK, + DSPCLK_PIXCLK, + DSPCLK_PHYCLK, + DSPCLK_COUNT, +} DSPCLK_e; + +typedef struct { + uint16_t Freq; + uint16_t Vid; +} DisplayClockTable_t; + + +typedef struct { + uint16_t MinClock; /* This is either DCFCLK or SOCCLK (in MHz) */ + uint16_t MaxClock; /* This is either DCFCLK or SOCCLK (in MHz) */ + uint16_t MinMclk; + uint16_t MaxMclk; + + uint8_t WmSetting; + uint8_t Padding[3]; +} WatermarkRowGeneric_t; + +#define NUM_WM_RANGES 4 + +typedef enum { + WM_SOCCLK = 0, + WM_DCFCLK, + WM_COUNT, +} WM_CLOCK_e; + +typedef struct { + WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; + uint32_t MmHubPadding[7]; +} Watermarks_t; + +typedef enum { + CUSTOM_DPM_SETTING_GFXCLK, + CUSTOM_DPM_SETTING_CCLK, + CUSTOM_DPM_SETTING_FCLK_CCX, + CUSTOM_DPM_SETTING_FCLK_GFX, + CUSTOM_DPM_SETTING_FCLK_STALLS, + CUSTOM_DPM_SETTING_LCLK, + CUSTOM_DPM_SETTING_COUNT, +} CUSTOM_DPM_SETTING_e; + +typedef struct { + uint8_t ActiveHystLimit; + uint8_t IdleHystLimit; + uint8_t FPS; + uint8_t MinActiveFreqType; + FloatInIntFormat_t MinActiveFreq; + FloatInIntFormat_t PD_Data_limit; + FloatInIntFormat_t PD_Data_time_constant; + FloatInIntFormat_t PD_Data_error_coeff; + FloatInIntFormat_t PD_Data_error_rate_coeff; +} DpmActivityMonitorCoeffExt_t; + +typedef struct { + DpmActivityMonitorCoeffExt_t DpmActivityMonitorCoeff[CUSTOM_DPM_SETTING_COUNT]; +} CustomDpmSettings_t; + +#define NUM_SOCCLK_DPM_LEVELS 8 +#define NUM_DCEFCLK_DPM_LEVELS 4 +#define NUM_FCLK_DPM_LEVELS 4 +#define NUM_MEMCLK_DPM_LEVELS 4 + +typedef struct { + uint32_t Freq; /* In MHz */ + uint32_t Vol; /* Millivolts with 2 fractional bits */ +} DpmClock_t; + +typedef struct { + DpmClock_t DcefClocks[NUM_DCEFCLK_DPM_LEVELS]; + DpmClock_t SocClocks[NUM_SOCCLK_DPM_LEVELS]; + DpmClock_t FClocks[NUM_FCLK_DPM_LEVELS]; + DpmClock_t MemClocks[NUM_MEMCLK_DPM_LEVELS]; +} DpmClocks_t; + +#endif diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h b/drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h index d43f98a910b0..532186b6f941 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h +++ b/drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h @@ -30,7 +30,7 @@ * SMU TEAM: Always increment the interface version if * any structure is changed in this file */ -#define SMU9_DRIVER_IF_VERSION 0xD +#define SMU9_DRIVER_IF_VERSION 0xE #define PPTABLE_V10_SMU_VERSION 1 @@ -380,25 +380,25 @@ typedef struct { uint8_t AvfsVersion; uint8_t Padding[2]; - uint32_t VFT0_m1; /* Q16.16 */ - uint32_t VFT0_m2; /* Q16.16 */ - uint32_t VFT0_b; /* Q16.16 */ + int32_t VFT0_m1; /* Q8.24 */ + int32_t VFT0_m2; /* Q12.12 */ + int32_t VFT0_b; /* Q32 */ - uint32_t VFT1_m1; /* Q16.16 */ - uint32_t VFT1_m2; /* Q16.16 */ - uint32_t VFT1_b; /* Q16.16 */ + int32_t VFT1_m1; /* Q8.16 */ + int32_t VFT1_m2; /* Q12.12 */ + int32_t VFT1_b; /* Q32 */ - uint32_t VFT2_m1; /* Q16.16 */ - uint32_t VFT2_m2; /* Q16.16 */ - uint32_t VFT2_b; /* Q16.16 */ + int32_t VFT2_m1; /* Q8.16 */ + int32_t VFT2_m2; /* Q12.12 */ + int32_t VFT2_b; /* Q32 */ - uint32_t AvfsGb0_m1; /* Q16.16 */ - uint32_t AvfsGb0_m2; /* Q16.16 */ - uint32_t AvfsGb0_b; /* Q16.16 */ + int32_t AvfsGb0_m1; /* Q8.16 */ + int32_t AvfsGb0_m2; /* Q12.12 */ + int32_t AvfsGb0_b; /* Q32 */ - uint32_t AcBtcGb_m1; /* Q16.16 */ - uint32_t AcBtcGb_m2; /* Q16.16 */ - uint32_t AcBtcGb_b; /* Q16.16 */ + int32_t AcBtcGb_m1; /* Q8.24 */ + int32_t AcBtcGb_m2; /* Q12.12 */ + int32_t AcBtcGb_b; /* Q32 */ uint32_t AvfsTempCold; uint32_t AvfsTempMid; @@ -406,9 +406,9 @@ typedef struct { uint32_t InversionVoltage; /* in mV with 2 fractional bits */ - uint32_t P2V_m1; /* Q16.16 */ - uint32_t P2V_m2; /* Q16.16 */ - uint32_t P2V_b; /* Q16.16 */ + int32_t P2V_m1; /* Q8.24 */ + int32_t P2V_m2; /* Q12.12 */ + int32_t P2V_b; /* Q32 */ uint32_t P2VCharzFreq; /* in 10KHz units */ diff --git a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h index 37f41217b8a0..976e942ec694 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h +++ b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h @@ -39,6 +39,7 @@ extern const struct pp_smumgr_func tonga_smu_funcs; extern const struct pp_smumgr_func fiji_smu_funcs; extern const struct pp_smumgr_func polaris10_smu_funcs; extern const struct pp_smumgr_func vega10_smu_funcs; +extern const struct pp_smumgr_func rv_smu_funcs; enum AVFS_BTC_STATUS { AVFS_BTC_BOOT = 0, diff --git a/drivers/gpu/drm/amd/powerplay/inc/vega10_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/vega10_ppsmc.h index 254974d3d371..e07cab311c7a 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/vega10_ppsmc.h +++ b/drivers/gpu/drm/amd/powerplay/inc/vega10_ppsmc.h @@ -124,7 +124,8 @@ typedef uint16_t PPSMC_Result; #define PPSMC_MSG_NumOfDisplays 0x56 #define PPSMC_MSG_ReadSerialNumTop32 0x58 #define PPSMC_MSG_ReadSerialNumBottom32 0x59 -#define PPSMC_Message_Count 0x5A +#define PPSMC_MSG_GetCurrPkgPwr 0x5C +#define PPSMC_Message_Count 0x5D typedef int PPSMC_Msg; diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/Makefile b/drivers/gpu/drm/amd/powerplay/smumgr/Makefile index 68b01b594e11..1703bbefbfd5 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/Makefile +++ b/drivers/gpu/drm/amd/powerplay/smumgr/Makefile @@ -4,7 +4,7 @@ SMU_MGR = smumgr.o cz_smumgr.o tonga_smumgr.o fiji_smumgr.o fiji_smc.o \ polaris10_smumgr.o iceland_smumgr.o polaris10_smc.o tonga_smc.o \ - smu7_smumgr.o iceland_smc.o vega10_smumgr.o + smu7_smumgr.o iceland_smc.o vega10_smumgr.o rv_smumgr.o AMD_PP_SMUMGR = $(addprefix $(AMD_PP_PATH)/smumgr/,$(SMU_MGR)) diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c index 1f6744a443d4..39c7091866e8 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c @@ -20,11 +20,13 @@ * OTHER DEALINGS IN THE SOFTWARE. * */ -#include <linux/types.h> + +#include <linux/delay.h> +#include <linux/gfp.h> #include <linux/kernel.h> #include <linux/slab.h> -#include <linux/gfp.h> -#include "linux/delay.h" +#include <linux/types.h> + #include "cgs_common.h" #include "smu/smu_8_0_d.h" #include "smu/smu_8_0_sh_mask.h" diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c new file mode 100644 index 000000000000..ce0a30388ea1 --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c @@ -0,0 +1,398 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include "smumgr.h" +#include "rv_inc.h" +#include "pp_soc15.h" +#include "rv_smumgr.h" +#include "ppatomctrl.h" +#include "rv_ppsmc.h" +#include "smu10_driver_if.h" +#include "smu10.h" +#include "ppatomctrl.h" +#include "pp_debug.h" +#include "smu_ucode_xfer_vi.h" +#include "smu7_smumgr.h" + +#define VOLTAGE_SCALE 4 + +#define BUFFER_SIZE 80000 +#define MAX_STRING_SIZE 15 +#define BUFFER_SIZETWO 131072 + +#define MP0_Public 0x03800000 +#define MP0_SRAM 0x03900000 +#define MP1_Public 0x03b00000 +#define MP1_SRAM 0x03c00004 + +#define smnMP1_FIRMWARE_FLAGS 0x3010028 + + +bool rv_is_smc_ram_running(struct pp_smumgr *smumgr) +{ + uint32_t mp1_fw_flags, reg; + + reg = soc15_get_register_offset(NBIF_HWID, 0, + mmPCIE_INDEX2_BASE_IDX, mmPCIE_INDEX2); + + cgs_write_register(smumgr->device, reg, + (MP1_Public | (smnMP1_FIRMWARE_FLAGS & 0xffffffff))); + + reg = soc15_get_register_offset(NBIF_HWID, 0, + mmPCIE_DATA2_BASE_IDX, mmPCIE_DATA2); + + mp1_fw_flags = cgs_read_register(smumgr->device, reg); + + if (mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) + return true; + + return false; +} + +static uint32_t rv_wait_for_response(struct pp_smumgr *smumgr) +{ + uint32_t reg; + + if (!rv_is_smc_ram_running(smumgr)) + return -EINVAL; + + reg = soc15_get_register_offset(MP1_HWID, 0, + mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90); + + smum_wait_for_register_unequal(smumgr, reg, + 0, MP1_C2PMSG_90__CONTENT_MASK); + + return cgs_read_register(smumgr->device, reg); +} + +int rv_send_msg_to_smc_without_waiting(struct pp_smumgr *smumgr, + uint16_t msg) +{ + uint32_t reg; + + if (!rv_is_smc_ram_running(smumgr)) + return -EINVAL; + + reg = soc15_get_register_offset(MP1_HWID, 0, + mmMP1_SMN_C2PMSG_66_BASE_IDX, mmMP1_SMN_C2PMSG_66); + cgs_write_register(smumgr->device, reg, msg); + + return 0; +} + +int rv_read_arg_from_smc(struct pp_smumgr *smumgr, uint32_t *arg) +{ + uint32_t reg; + + reg = soc15_get_register_offset(MP1_HWID, 0, + mmMP1_SMN_C2PMSG_82_BASE_IDX, mmMP1_SMN_C2PMSG_82); + + *arg = cgs_read_register(smumgr->device, reg); + + return 0; +} + +int rv_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg) +{ + uint32_t reg; + + rv_wait_for_response(smumgr); + + reg = soc15_get_register_offset(MP1_HWID, 0, + mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90); + cgs_write_register(smumgr->device, reg, 0); + + rv_send_msg_to_smc_without_waiting(smumgr, msg); + + if (rv_wait_for_response(smumgr) == 0) + printk("Failed to send Message %x.\n", msg); + + return 0; +} + + +int rv_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr, + uint16_t msg, uint32_t parameter) +{ + uint32_t reg; + + rv_wait_for_response(smumgr); + + reg = soc15_get_register_offset(MP1_HWID, 0, + mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90); + cgs_write_register(smumgr->device, reg, 0); + + reg = soc15_get_register_offset(MP1_HWID, 0, + mmMP1_SMN_C2PMSG_82_BASE_IDX, mmMP1_SMN_C2PMSG_82); + cgs_write_register(smumgr->device, reg, parameter); + + rv_send_msg_to_smc_without_waiting(smumgr, msg); + + + if (rv_wait_for_response(smumgr) == 0) + printk("Failed to send Message %x.\n", msg); + + return 0; +} + +int rv_copy_table_from_smc(struct pp_smumgr *smumgr, + uint8_t *table, int16_t table_id) +{ + struct rv_smumgr *priv = + (struct rv_smumgr *)(smumgr->backend); + + PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE, + "Invalid SMU Table ID!", return -EINVAL;); + PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0, + "Invalid SMU Table version!", return -EINVAL;); + PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0, + "Invalid SMU Table Length!", return -EINVAL;); + PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(smumgr, + PPSMC_MSG_SetDriverDramAddrHigh, + priv->smu_tables.entry[table_id].table_addr_high) == 0, + "[CopyTableFromSMC] Attempt to Set Dram Addr High Failed!", return -EINVAL;); + PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(smumgr, + PPSMC_MSG_SetDriverDramAddrLow, + priv->smu_tables.entry[table_id].table_addr_low) == 0, + "[CopyTableFromSMC] Attempt to Set Dram Addr Low Failed!", + return -EINVAL;); + PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(smumgr, + PPSMC_MSG_TransferTableSmu2Dram, + priv->smu_tables.entry[table_id].table_id) == 0, + "[CopyTableFromSMC] Attempt to Transfer Table From SMU Failed!", + return -EINVAL;); + + memcpy(table, priv->smu_tables.entry[table_id].table, + priv->smu_tables.entry[table_id].size); + + return 0; +} + +int rv_copy_table_to_smc(struct pp_smumgr *smumgr, + uint8_t *table, int16_t table_id) +{ + struct rv_smumgr *priv = + (struct rv_smumgr *)(smumgr->backend); + + PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE, + "Invalid SMU Table ID!", return -EINVAL;); + PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0, + "Invalid SMU Table version!", return -EINVAL;); + PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0, + "Invalid SMU Table Length!", return -EINVAL;); + + memcpy(priv->smu_tables.entry[table_id].table, table, + priv->smu_tables.entry[table_id].size); + + PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(smumgr, + PPSMC_MSG_SetDriverDramAddrHigh, + priv->smu_tables.entry[table_id].table_addr_high) == 0, + "[CopyTableToSMC] Attempt to Set Dram Addr High Failed!", + return -EINVAL;); + PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(smumgr, + PPSMC_MSG_SetDriverDramAddrLow, + priv->smu_tables.entry[table_id].table_addr_low) == 0, + "[CopyTableToSMC] Attempt to Set Dram Addr Low Failed!", + return -EINVAL;); + PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(smumgr, + PPSMC_MSG_TransferTableDram2Smu, + priv->smu_tables.entry[table_id].table_id) == 0, + "[CopyTableToSMC] Attempt to Transfer Table To SMU Failed!", + return -EINVAL;); + + return 0; +} + +static int rv_verify_smc_interface(struct pp_smumgr *smumgr) +{ + uint32_t smc_driver_if_version; + + PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc(smumgr, + PPSMC_MSG_GetDriverIfVersion), + "Attempt to get SMC IF Version Number Failed!", + return -EINVAL); + PP_ASSERT_WITH_CODE(!rv_read_arg_from_smc(smumgr, + &smc_driver_if_version), + "Attempt to read SMC IF Version Number Failed!", + return -EINVAL); + + if (smc_driver_if_version != SMU10_DRIVER_IF_VERSION) + return -EINVAL; + + return 0; +} + +/* sdma is disabled by default in vbios, need to re-enable in driver */ +static int rv_smc_enable_sdma(struct pp_smumgr *smumgr) +{ + PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc(smumgr, + PPSMC_MSG_PowerUpSdma), + "Attempt to power up sdma Failed!", + return -EINVAL); + + return 0; +} + +static int rv_smc_disable_sdma(struct pp_smumgr *smumgr) +{ + PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc(smumgr, + PPSMC_MSG_PowerDownSdma), + "Attempt to power down sdma Failed!", + return -EINVAL); + + return 0; +} + +/* vcn is disabled by default in vbios, need to re-enable in driver */ +static int rv_smc_enable_vcn(struct pp_smumgr *smumgr) +{ + PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc_with_parameter(smumgr, + PPSMC_MSG_PowerUpVcn, 0), + "Attempt to power up vcn Failed!", + return -EINVAL); + + return 0; +} + +static int rv_smc_disable_vcn(struct pp_smumgr *smumgr) +{ + PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc_with_parameter(smumgr, + PPSMC_MSG_PowerDownVcn, 0), + "Attempt to power down vcn Failed!", + return -EINVAL); + + return 0; +} + +static int rv_smu_fini(struct pp_smumgr *smumgr) +{ + struct rv_smumgr *priv = + (struct rv_smumgr *)(smumgr->backend); + + if (priv) { + rv_smc_disable_sdma(smumgr); + rv_smc_disable_vcn(smumgr); + cgs_free_gpu_mem(smumgr->device, + priv->smu_tables.entry[WMTABLE].handle); + cgs_free_gpu_mem(smumgr->device, + priv->smu_tables.entry[CLOCKTABLE].handle); + kfree(smumgr->backend); + smumgr->backend = NULL; + } + + return 0; +} + +static int rv_start_smu(struct pp_smumgr *smumgr) +{ + if (rv_verify_smc_interface(smumgr)) + return -EINVAL; + if (rv_smc_enable_sdma(smumgr)) + return -EINVAL; + if (rv_smc_enable_vcn(smumgr)) + return -EINVAL; + + return 0; +} + +static int rv_smu_init(struct pp_smumgr *smumgr) +{ + struct rv_smumgr *priv; + uint64_t mc_addr; + void *kaddr = NULL; + unsigned long handle; + + priv = kzalloc(sizeof(struct rv_smumgr), GFP_KERNEL); + + if (!priv) + return -ENOMEM; + + smumgr->backend = priv; + + /* allocate space for watermarks table */ + smu_allocate_memory(smumgr->device, + sizeof(Watermarks_t), + CGS_GPU_MEM_TYPE__GART_CACHEABLE, + PAGE_SIZE, + &mc_addr, + &kaddr, + &handle); + + PP_ASSERT_WITH_CODE(kaddr, + "[rv_smu_init] Out of memory for wmtable.", + kfree(smumgr->backend); + smumgr->backend = NULL; + return -EINVAL); + + priv->smu_tables.entry[WMTABLE].version = 0x01; + priv->smu_tables.entry[WMTABLE].size = sizeof(Watermarks_t); + priv->smu_tables.entry[WMTABLE].table_id = TABLE_WATERMARKS; + priv->smu_tables.entry[WMTABLE].table_addr_high = + smu_upper_32_bits(mc_addr); + priv->smu_tables.entry[WMTABLE].table_addr_low = + smu_lower_32_bits(mc_addr); + priv->smu_tables.entry[WMTABLE].table = kaddr; + priv->smu_tables.entry[WMTABLE].handle = handle; + + /* allocate space for watermarks table */ + smu_allocate_memory(smumgr->device, + sizeof(DpmClocks_t), + CGS_GPU_MEM_TYPE__GART_CACHEABLE, + PAGE_SIZE, + &mc_addr, + &kaddr, + &handle); + + PP_ASSERT_WITH_CODE(kaddr, + "[rv_smu_init] Out of memory for CLOCKTABLE.", + cgs_free_gpu_mem(smumgr->device, + (cgs_handle_t)priv->smu_tables.entry[WMTABLE].handle); + kfree(smumgr->backend); + smumgr->backend = NULL; + return -EINVAL); + + priv->smu_tables.entry[CLOCKTABLE].version = 0x01; + priv->smu_tables.entry[CLOCKTABLE].size = sizeof(DpmClocks_t); + priv->smu_tables.entry[CLOCKTABLE].table_id = TABLE_DPMCLOCKS; + priv->smu_tables.entry[CLOCKTABLE].table_addr_high = + smu_upper_32_bits(mc_addr); + priv->smu_tables.entry[CLOCKTABLE].table_addr_low = + smu_lower_32_bits(mc_addr); + priv->smu_tables.entry[CLOCKTABLE].table = kaddr; + priv->smu_tables.entry[CLOCKTABLE].handle = handle; + + return 0; +} + +const struct pp_smumgr_func rv_smu_funcs = { + .smu_init = &rv_smu_init, + .smu_fini = &rv_smu_fini, + .start_smu = &rv_start_smu, + .request_smu_load_specific_fw = NULL, + .send_msg_to_smc = &rv_send_msg_to_smc, + .send_msg_to_smc_with_parameter = &rv_send_msg_to_smc_with_parameter, + .download_pptable_settings = NULL, + .upload_pptable_settings = NULL, +}; + + diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.h b/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.h new file mode 100644 index 000000000000..262c8ded87c0 --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.h @@ -0,0 +1,62 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef PP_RAVEN_SMUMANAGER_H +#define PP_RAVEN_SMUMANAGER_H + +#include "rv_ppsmc.h" +#include "smu10_driver_if.h" + +enum SMU_TABLE_ID { + WMTABLE = 0, + CLOCKTABLE, + MAX_SMU_TABLE, +}; + +struct smu_table_entry { + uint32_t version; + uint32_t size; + uint32_t table_id; + uint32_t table_addr_high; + uint32_t table_addr_low; + uint8_t *table; + uint32_t handle; +}; + +struct smu_table_array { + struct smu_table_entry entry[MAX_SMU_TABLE]; +}; + +struct rv_smumgr { + struct smu_table_array smu_tables; +}; + +int rv_read_arg_from_smc(struct pp_smumgr *smumgr, uint32_t *arg); +bool rv_is_smc_ram_running(struct pp_smumgr *smumgr); +int rv_copy_table_from_smc(struct pp_smumgr *smumgr, + uint8_t *table, int16_t table_id); +int rv_copy_table_to_smc(struct pp_smumgr *smumgr, + uint8_t *table, int16_t table_id); + + +#endif diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c index c0d75766bbc8..bcc61ffd13cb 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c @@ -20,15 +20,16 @@ * OTHER DEALINGS IN THE SOFTWARE. * */ -#include <linux/types.h> + +#include <linux/delay.h> #include <linux/kernel.h> #include <linux/module.h> #include <linux/slab.h> +#include <linux/types.h> #include <drm/amdgpu_drm.h> #include "pp_instance.h" #include "smumgr.h" #include "cgs_common.h" -#include "linux/delay.h" MODULE_FIRMWARE("amdgpu/topaz_smc.bin"); MODULE_FIRMWARE("amdgpu/topaz_k_smc.bin"); @@ -95,6 +96,15 @@ int smum_early_init(struct pp_instance *handle) return -EINVAL; } break; + case AMDGPU_FAMILY_RV: + switch (smumgr->chip_id) { + case CHIP_RAVEN: + smumgr->smumgr_funcs = &rv_smu_funcs; + break; + default: + return -EINVAL; + } + break; default: kfree(smumgr); return -EINVAL; diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c index 115f0e4b1603..269678443862 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c @@ -500,7 +500,6 @@ static int vega10_smu_init(struct pp_smumgr *smumgr) smu_lower_32_bits(mc_addr); priv->smu_tables.entry[TOOLSTABLE].table = kaddr; priv->smu_tables.entry[TOOLSTABLE].handle = handle; - vega10_set_tools_address(smumgr); } } @@ -569,6 +568,9 @@ static int vega10_start_smu(struct pp_smumgr *smumgr) PP_ASSERT_WITH_CODE(!vega10_verify_smc_interface(smumgr), "Failed to verify SMC interface!", return -EINVAL); + + vega10_set_tools_address(smumgr); + return 0; } |