summaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/amd/powerplay/inc
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/gpu/drm/amd/powerplay/inc')
-rw-r--r--drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h2
-rw-r--r--drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h20
-rw-r--r--drivers/gpu/drm/amd/powerplay/inc/hwmgr.h210
-rw-r--r--drivers/gpu/drm/amd/powerplay/inc/polaris10_ppsmc.h412
-rw-r--r--drivers/gpu/drm/amd/powerplay/inc/power_state.h4
-rw-r--r--drivers/gpu/drm/amd/powerplay/inc/pp_acpi.h26
-rw-r--r--drivers/gpu/drm/amd/powerplay/inc/pp_asicblocks.h47
-rw-r--r--drivers/gpu/drm/amd/powerplay/inc/pp_feature.h67
-rw-r--r--drivers/gpu/drm/amd/powerplay/inc/pp_soc15.h6
-rw-r--r--drivers/gpu/drm/amd/powerplay/inc/pp_thermal.h (renamed from drivers/gpu/drm/amd/powerplay/inc/pp_instance.h)26
-rw-r--r--drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h3
-rw-r--r--drivers/gpu/drm/amd/powerplay/inc/smu7.h19
-rw-r--r--drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h3
-rw-r--r--drivers/gpu/drm/amd/powerplay/inc/smu9.h4
-rw-r--r--drivers/gpu/drm/amd/powerplay/inc/smumgr.h44
-rw-r--r--drivers/gpu/drm/amd/powerplay/inc/vega10_ppsmc.h1
16 files changed, 108 insertions, 786 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
index 152e70db4a81..fe3665965416 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
@@ -30,6 +30,6 @@
#include "cgs_common.h"
#include "dm_pp_interface.h"
#include "kgd_pp_interface.h"
-
+#include "amdgpu.h"
#endif /* _AMD_POWERPLAY_H_ */
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
index 5716b937a6ad..b366a5bd2d81 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
@@ -358,6 +358,17 @@ struct phm_clocks {
uint32_t clock[MAX_NUM_CLOCKS];
};
+#define DPMTABLE_OD_UPDATE_SCLK 0x00000001
+#define DPMTABLE_OD_UPDATE_MCLK 0x00000002
+#define DPMTABLE_UPDATE_SCLK 0x00000004
+#define DPMTABLE_UPDATE_MCLK 0x00000008
+#define DPMTABLE_OD_UPDATE_VDDC 0x00000010
+
+/* To determine if sclk and mclk are in overdrive state */
+#define SCLK_OVERDRIVE_ENABLED 0x00000001
+#define MCLK_OVERDRIVE_ENABLED 0x00000002
+#define VDDC_OVERDRIVE_ENABLED 0x00000010
+
struct phm_odn_performance_level {
uint32_t clock;
uint32_t vddc;
@@ -368,9 +379,9 @@ struct phm_odn_clock_levels {
uint32_t size;
uint32_t options;
uint32_t flags;
- uint32_t number_of_performance_levels;
- /* variable-sized array, specify by ulNumberOfPerformanceLevels. */
- struct phm_odn_performance_level performance_level_entries[8];
+ uint32_t num_of_pl;
+ /* variable-sized array, specify by num_of_pl. */
+ struct phm_odn_performance_level entries[8];
};
extern int phm_disable_clock_power_gatings(struct pp_hwmgr *hwmgr);
@@ -393,7 +404,7 @@ extern int phm_force_dpm_levels(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_leve
extern int phm_display_configuration_changed(struct pp_hwmgr *hwmgr);
extern int phm_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr);
extern int phm_register_thermal_interrupt(struct pp_hwmgr *hwmgr, const void *info);
-extern int phm_start_thermal_controller(struct pp_hwmgr *hwmgr, struct PP_TemperatureRange *temperature_range);
+extern int phm_start_thermal_controller(struct pp_hwmgr *hwmgr);
extern int phm_stop_thermal_controller(struct pp_hwmgr *hwmgr);
extern bool phm_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr);
@@ -437,6 +448,5 @@ extern int phm_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
extern int phm_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks);
extern int phm_disable_smc_firmware_ctf(struct pp_hwmgr *hwmgr);
-extern int phm_reset_power_profile_state(struct pp_hwmgr *hwmgr);
#endif /* _HARDWARE_MANAGER_H_ */
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 565fe0832f41..85b46ad68546 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -25,16 +25,14 @@
#include <linux/seq_file.h>
#include "amd_powerplay.h"
-#include "pp_instance.h"
#include "hardwaremanager.h"
#include "pp_power_source.h"
#include "hwmgr_ppt.h"
#include "ppatomctrl.h"
#include "hwmgr_ppt.h"
#include "power_state.h"
-#include "cgs_linux.h"
+#include "smu_helper.h"
-struct pp_instance;
struct pp_hwmgr;
struct phm_fan_speed_info;
struct pp_atomctrl_voltage_table;
@@ -42,6 +40,7 @@ struct pp_atomctrl_voltage_table;
#define VOLTAGE_SCALE 4
uint8_t convert_to_vid(uint16_t vddc);
+uint16_t convert_to_vddc(uint8_t vid);
enum DISPLAY_GAP {
DISPLAY_GAP_VBLANK_OR_WM = 0, /* Wait for vblank or MCHG watermark. */
@@ -83,6 +82,7 @@ enum PP_FEATURE_MASK {
PP_OD_FUZZY_FAN_CONTROL_MASK = 0x800,
PP_SOCCLK_DPM_MASK = 0x1000,
PP_DCEFCLK_DPM_MASK = 0x2000,
+ PP_OVERDRIVE_MASK = 0x4000,
};
enum PHM_BackEnd_Magic {
@@ -233,9 +233,9 @@ struct pp_smumgr_func {
uint32_t (*get_offsetof)(uint32_t type, uint32_t member);
uint32_t (*get_mac_definition)(uint32_t value);
bool (*is_dpm_running)(struct pp_hwmgr *hwmgr);
- int (*populate_requested_graphic_levels)(struct pp_hwmgr *hwmgr,
- struct amd_pp_profile *request);
bool (*is_hw_avfs_present)(struct pp_hwmgr *hwmgr);
+ int (*update_dpm_settings)(struct pp_hwmgr *hwmgr, void *profile_setting);
+ int (*smc_table_manager)(struct pp_hwmgr *hwmgr, uint8_t *table, uint16_t table_id, bool rw); /*rw: true for read, false for write */
};
struct pp_hwmgr_func {
@@ -277,7 +277,6 @@ struct pp_hwmgr_func {
const uint32_t *msg_id);
int (*set_max_fan_rpm_output)(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm);
int (*set_max_fan_pwm_output)(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm);
- int (*get_temperature)(struct pp_hwmgr *hwmgr);
int (*stop_thermal_controller)(struct pp_hwmgr *hwmgr);
int (*get_fan_speed_info)(struct pp_hwmgr *hwmgr, struct phm_fan_speed_info *fan_speed_info);
void (*set_fan_control_mode)(struct pp_hwmgr *hwmgr, uint32_t mode);
@@ -326,8 +325,6 @@ struct pp_hwmgr_func {
int (*get_mclk_od)(struct pp_hwmgr *hwmgr);
int (*set_mclk_od)(struct pp_hwmgr *hwmgr, uint32_t value);
int (*read_sensor)(struct pp_hwmgr *hwmgr, int idx, void *value, int *size);
- int (*set_power_profile_state)(struct pp_hwmgr *hwmgr,
- struct amd_pp_profile *request);
int (*avfs_control)(struct pp_hwmgr *hwmgr, bool enable);
int (*disable_smc_firmware_ctf)(struct pp_hwmgr *hwmgr);
int (*set_active_display_count)(struct pp_hwmgr *hwmgr, uint32_t count);
@@ -339,6 +336,15 @@ struct pp_hwmgr_func {
uint32_t mc_addr_low,
uint32_t mc_addr_hi,
uint32_t size);
+ int (*get_thermal_temperature_range)(struct pp_hwmgr *hwmgr,
+ struct PP_TemperatureRange *range);
+ int (*get_power_profile_mode)(struct pp_hwmgr *hwmgr, char *buf);
+ int (*set_power_profile_mode)(struct pp_hwmgr *hwmgr, long *input, uint32_t size);
+ int (*odn_edit_dpm_table)(struct pp_hwmgr *hwmgr,
+ enum PP_OD_DPM_TABLE_COMMAND type,
+ long *input, uint32_t size);
+ int (*set_power_limit)(struct pp_hwmgr *hwmgr, uint32_t n);
+ int (*set_mmhub_powergating_by_smu)(struct pp_hwmgr *hwmgr);
};
struct pp_table_func {
@@ -608,7 +614,6 @@ struct phm_dynamic_state_info {
struct phm_ppm_table *ppm_parameter_table;
struct phm_cac_tdp_table *cac_dtp_table;
struct phm_clock_voltage_dependency_table *vdd_gfx_dependency_on_sclk;
- struct phm_vq_budgeting_table *vq_budgeting_table;
};
struct pp_fan_info {
@@ -689,10 +694,15 @@ enum PP_TABLE_VERSION {
/**
* The main hardware manager structure.
*/
+#define Workload_Policy_Max 5
+
struct pp_hwmgr {
+ void *adev;
uint32_t chip_family;
uint32_t chip_id;
uint32_t smu_version;
+ bool pm_en;
+ struct mutex smu_lock;
uint32_t pp_table_version;
void *device;
@@ -739,14 +749,19 @@ struct pp_hwmgr {
struct pp_power_state *uvd_ps;
struct amd_pp_display_configuration display_config;
uint32_t feature_mask;
-
+ bool avfs_supported;
/* UMD Pstate */
- struct amd_pp_profile gfx_power_profile;
- struct amd_pp_profile compute_power_profile;
- struct amd_pp_profile default_gfx_power_profile;
- struct amd_pp_profile default_compute_power_profile;
- enum amd_pp_profile_type current_power_profile;
bool en_umd_pstate;
+ uint32_t power_profile_mode;
+ uint32_t default_power_profile_mode;
+ uint32_t pstate_sclk;
+ uint32_t pstate_mclk;
+ bool od_enabled;
+ uint32_t power_limit;
+ uint32_t default_power_limit;
+ uint32_t workload_mask;
+ uint32_t workload_prority[Workload_Policy_Max];
+ uint32_t workload_setting[Workload_Policy_Max];
};
struct cgs_irq_src_funcs {
@@ -754,166 +769,17 @@ struct cgs_irq_src_funcs {
cgs_irq_handler_func_t handler;
};
-extern int hwmgr_early_init(struct pp_instance *handle);
-extern int hwmgr_hw_init(struct pp_instance *handle);
-extern int hwmgr_hw_fini(struct pp_instance *handle);
-extern int hwmgr_hw_suspend(struct pp_instance *handle);
-extern int hwmgr_hw_resume(struct pp_instance *handle);
-extern int hwmgr_handle_task(struct pp_instance *handle,
+extern int hwmgr_early_init(struct pp_hwmgr *hwmgr);
+extern int hwmgr_hw_init(struct pp_hwmgr *hwmgr);
+extern int hwmgr_hw_fini(struct pp_hwmgr *hwmgr);
+extern int hwmgr_hw_suspend(struct pp_hwmgr *hwmgr);
+extern int hwmgr_hw_resume(struct pp_hwmgr *hwmgr);
+extern int hwmgr_handle_task(struct pp_hwmgr *hwmgr,
enum amd_pp_task task_id,
- void *input, void *output);
-extern int phm_wait_on_register(struct pp_hwmgr *hwmgr, uint32_t index,
- uint32_t value, uint32_t mask);
-
-extern int phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr,
- uint32_t indirect_port,
- uint32_t index,
- uint32_t value,
- uint32_t mask);
-
-extern int phm_wait_for_register_unequal(struct pp_hwmgr *hwmgr,
- uint32_t index,
- uint32_t value, uint32_t mask);
-extern int phm_wait_for_indirect_register_unequal(
- struct pp_hwmgr *hwmgr,
- uint32_t indirect_port, uint32_t index,
- uint32_t value, uint32_t mask);
-
-
-extern bool phm_cf_want_uvd_power_gating(struct pp_hwmgr *hwmgr);
-extern bool phm_cf_want_vce_power_gating(struct pp_hwmgr *hwmgr);
-extern bool phm_cf_want_microcode_fan_ctrl(struct pp_hwmgr *hwmgr);
-
-extern int phm_trim_voltage_table(struct pp_atomctrl_voltage_table *vol_table);
-extern int phm_get_svi2_mvdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_clock_voltage_dependency_table *dep_table);
-extern int phm_get_svi2_vddci_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_clock_voltage_dependency_table *dep_table);
-extern int phm_get_svi2_vdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_voltage_lookup_table *lookup_table);
-extern void phm_trim_voltage_table_to_fit_state_table(uint32_t max_vol_steps, struct pp_atomctrl_voltage_table *vol_table);
-extern int phm_reset_single_dpm_table(void *table, uint32_t count, int max);
-extern void phm_setup_pcie_table_entry(void *table, uint32_t index, uint32_t pcie_gen, uint32_t pcie_lanes);
-extern int32_t phm_get_dpm_level_enable_mask_value(void *table);
-extern uint8_t phm_get_voltage_id(struct pp_atomctrl_voltage_table *voltage_table,
- uint32_t voltage);
-extern uint8_t phm_get_voltage_index(struct phm_ppt_v1_voltage_lookup_table *lookup_table, uint16_t voltage);
-extern uint16_t phm_find_closest_vddci(struct pp_atomctrl_voltage_table *vddci_table, uint16_t vddci);
-extern int phm_find_boot_level(void *table, uint32_t value, uint32_t *boot_level);
-extern int phm_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr, phm_ppt_v1_voltage_lookup_table *lookup_table,
- uint16_t virtual_voltage_id, int32_t *sclk);
-extern int phm_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr);
-extern uint32_t phm_get_lowest_enabled_level(struct pp_hwmgr *hwmgr, uint32_t mask);
-extern void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr);
-
-extern int smu7_init_function_pointers(struct pp_hwmgr *hwmgr);
-extern int vega10_hwmgr_init(struct pp_hwmgr *hwmgr);
-extern int rv_init_function_pointers(struct pp_hwmgr *hwmgr);
-
-extern int phm_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
- uint32_t sclk, uint16_t id, uint16_t *voltage);
-
-#define PHM_ENTIRE_REGISTER_MASK 0xFFFFFFFFU
-
-#define PHM_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
-#define PHM_FIELD_MASK(reg, field) reg##__##field##_MASK
-
-#define PHM_SET_FIELD(origval, reg, field, fieldval) \
- (((origval) & ~PHM_FIELD_MASK(reg, field)) | \
- (PHM_FIELD_MASK(reg, field) & ((fieldval) << PHM_FIELD_SHIFT(reg, field))))
-
-#define PHM_GET_FIELD(value, reg, field) \
- (((value) & PHM_FIELD_MASK(reg, field)) >> \
- PHM_FIELD_SHIFT(reg, field))
-
-
-/* Operations on named fields. */
-
-#define PHM_READ_FIELD(device, reg, field) \
- PHM_GET_FIELD(cgs_read_register(device, mm##reg), reg, field)
-
-#define PHM_READ_INDIRECT_FIELD(device, port, reg, field) \
- PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
- reg, field)
-
-#define PHM_READ_VFPF_INDIRECT_FIELD(device, port, reg, field) \
- PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
- reg, field)
-
-#define PHM_WRITE_FIELD(device, reg, field, fieldval) \
- cgs_write_register(device, mm##reg, PHM_SET_FIELD( \
- cgs_read_register(device, mm##reg), reg, field, fieldval))
-
-#define PHM_WRITE_INDIRECT_FIELD(device, port, reg, field, fieldval) \
- cgs_write_ind_register(device, port, ix##reg, \
- PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
- reg, field, fieldval))
-
-#define PHM_WRITE_VFPF_INDIRECT_FIELD(device, port, reg, field, fieldval) \
- cgs_write_ind_register(device, port, ix##reg, \
- PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
- reg, field, fieldval))
-
-#define PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, index, value, mask) \
- phm_wait_on_indirect_register(hwmgr, mm##port##_INDEX, index, value, mask)
+ enum amd_pm_state_type *user_state);
-#define PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, value, mask) \
- PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
-
-#define PHM_WAIT_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval) \
- PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, (fieldval) \
- << PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
-
-#define PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, index, value, mask) \
- phm_wait_for_indirect_register_unequal(hwmgr, \
- mm##port##_INDEX, index, value, mask)
-
-#define PHM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask) \
- PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
-
-#define PHM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval) \
- PHM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, \
- (fieldval) << PHM_FIELD_SHIFT(reg, field), \
- PHM_FIELD_MASK(reg, field) )
-
-
-#define PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, \
- port, index, value, mask) \
- phm_wait_for_indirect_register_unequal(hwmgr, \
- mm##port##_INDEX_11, index, value, mask)
-
-#define PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask) \
- PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
-
-#define PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval) \
- PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, \
- (fieldval) << PHM_FIELD_SHIFT(reg, field), \
- PHM_FIELD_MASK(reg, field))
-
-
-#define PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, \
- port, index, value, mask) \
- phm_wait_on_indirect_register(hwmgr, \
- mm##port##_INDEX_11, index, value, mask)
-
-#define PHM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, value, mask) \
- PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
-
-#define PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval) \
- PHM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, \
- (fieldval) << PHM_FIELD_SHIFT(reg, field), \
- PHM_FIELD_MASK(reg, field))
-
-#define PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, \
- index, value, mask) \
- phm_wait_for_register_unequal(hwmgr, \
- index, value, mask)
-
-#define PHM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, value, mask) \
- PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, \
- mm##reg, value, mask)
+#define PHM_ENTIRE_REGISTER_MASK 0xFFFFFFFFU
-#define PHM_WAIT_FIELD_UNEQUAL(hwmgr, reg, field, fieldval) \
- PHM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, \
- (fieldval) << PHM_FIELD_SHIFT(reg, field), \
- PHM_FIELD_MASK(reg, field))
#endif /* _HWMGR_H_ */
diff --git a/drivers/gpu/drm/amd/powerplay/inc/polaris10_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/polaris10_ppsmc.h
deleted file mode 100644
index b8f4b73c322e..000000000000
--- a/drivers/gpu/drm/amd/powerplay/inc/polaris10_ppsmc.h
+++ /dev/null
@@ -1,412 +0,0 @@
-/*
- * Copyright 2015 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#ifndef POLARIS10_PP_SMC_H
-#define POLARIS10_PP_SMC_H
-
-
-#pragma pack(push, 1)
-
-#define PPSMC_MSG_SetGBDroopSettings ((uint16_t) 0x305)
-
-#define PPSMC_SWSTATE_FLAG_DC 0x01
-#define PPSMC_SWSTATE_FLAG_UVD 0x02
-#define PPSMC_SWSTATE_FLAG_VCE 0x04
-
-#define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00
-#define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01
-#define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff
-
-#define PPSMC_SYSTEMFLAG_GPIO_DC 0x01
-#define PPSMC_SYSTEMFLAG_STEPVDDC 0x02
-#define PPSMC_SYSTEMFLAG_GDDR5 0x04
-
-#define PPSMC_SYSTEMFLAG_DISABLE_BABYSTEP 0x08
-
-#define PPSMC_SYSTEMFLAG_REGULATOR_HOT 0x10
-#define PPSMC_SYSTEMFLAG_REGULATOR_HOT_ANALOG 0x20
-
-#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_MASK 0x07
-#define PPSMC_EXTRAFLAGS_AC2DC_DONT_WAIT_FOR_VBLANK 0x08
-
-#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTODPMLOWSTATE 0x00
-#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTOINITIALSTATE 0x01
-
-
-#define PPSMC_DPM2FLAGS_TDPCLMP 0x01
-#define PPSMC_DPM2FLAGS_PWRSHFT 0x02
-#define PPSMC_DPM2FLAGS_OCP 0x04
-
-
-#define PPSMC_DISPLAY_WATERMARK_LOW 0
-#define PPSMC_DISPLAY_WATERMARK_HIGH 1
-
-
-#define PPSMC_STATEFLAG_AUTO_PULSE_SKIP 0x01
-#define PPSMC_STATEFLAG_POWERBOOST 0x02
-#define PPSMC_STATEFLAG_PSKIP_ON_TDP_FAULT 0x04
-#define PPSMC_STATEFLAG_POWERSHIFT 0x08
-#define PPSMC_STATEFLAG_SLOW_READ_MARGIN 0x10
-#define PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE 0x20
-#define PPSMC_STATEFLAG_DEEPSLEEP_BYPASS 0x40
-
-
-#define FDO_MODE_HARDWARE 0
-#define FDO_MODE_PIECE_WISE_LINEAR 1
-
-enum FAN_CONTROL {
- FAN_CONTROL_FUZZY,
- FAN_CONTROL_TABLE
-};
-
-
-#define PPSMC_Result_OK ((uint16_t)0x01)
-#define PPSMC_Result_NoMore ((uint16_t)0x02)
-
-#define PPSMC_Result_NotNow ((uint16_t)0x03)
-#define PPSMC_Result_Failed ((uint16_t)0xFF)
-#define PPSMC_Result_UnknownCmd ((uint16_t)0xFE)
-#define PPSMC_Result_UnknownVT ((uint16_t)0xFD)
-
-typedef uint16_t PPSMC_Result;
-
-#define PPSMC_isERROR(x) ((uint16_t)0x80 & (x))
-
-
-#define PPSMC_MSG_Halt ((uint16_t)0x10)
-#define PPSMC_MSG_Resume ((uint16_t)0x11)
-#define PPSMC_MSG_EnableDPMLevel ((uint16_t)0x12)
-#define PPSMC_MSG_ZeroLevelsDisabled ((uint16_t)0x13)
-#define PPSMC_MSG_OneLevelsDisabled ((uint16_t)0x14)
-#define PPSMC_MSG_TwoLevelsDisabled ((uint16_t)0x15)
-#define PPSMC_MSG_EnableThermalInterrupt ((uint16_t)0x16)
-#define PPSMC_MSG_RunningOnAC ((uint16_t)0x17)
-#define PPSMC_MSG_LevelUp ((uint16_t)0x18)
-#define PPSMC_MSG_LevelDown ((uint16_t)0x19)
-#define PPSMC_MSG_ResetDPMCounters ((uint16_t)0x1a)
-#define PPSMC_MSG_SwitchToSwState ((uint16_t)0x20)
-#define PPSMC_MSG_SwitchToSwStateLast ((uint16_t)0x3f)
-#define PPSMC_MSG_SwitchToInitialState ((uint16_t)0x40)
-#define PPSMC_MSG_NoForcedLevel ((uint16_t)0x41)
-#define PPSMC_MSG_ForceHigh ((uint16_t)0x42)
-#define PPSMC_MSG_ForceMediumOrHigh ((uint16_t)0x43)
-#define PPSMC_MSG_SwitchToMinimumPower ((uint16_t)0x51)
-#define PPSMC_MSG_ResumeFromMinimumPower ((uint16_t)0x52)
-#define PPSMC_MSG_EnableCac ((uint16_t)0x53)
-#define PPSMC_MSG_DisableCac ((uint16_t)0x54)
-#define PPSMC_DPMStateHistoryStart ((uint16_t)0x55)
-#define PPSMC_DPMStateHistoryStop ((uint16_t)0x56)
-#define PPSMC_CACHistoryStart ((uint16_t)0x57)
-#define PPSMC_CACHistoryStop ((uint16_t)0x58)
-#define PPSMC_TDPClampingActive ((uint16_t)0x59)
-#define PPSMC_TDPClampingInactive ((uint16_t)0x5A)
-#define PPSMC_StartFanControl ((uint16_t)0x5B)
-#define PPSMC_StopFanControl ((uint16_t)0x5C)
-#define PPSMC_NoDisplay ((uint16_t)0x5D)
-#define PPSMC_HasDisplay ((uint16_t)0x5E)
-#define PPSMC_MSG_UVDPowerOFF ((uint16_t)0x60)
-#define PPSMC_MSG_UVDPowerON ((uint16_t)0x61)
-#define PPSMC_MSG_EnableULV ((uint16_t)0x62)
-#define PPSMC_MSG_DisableULV ((uint16_t)0x63)
-#define PPSMC_MSG_EnterULV ((uint16_t)0x64)
-#define PPSMC_MSG_ExitULV ((uint16_t)0x65)
-#define PPSMC_PowerShiftActive ((uint16_t)0x6A)
-#define PPSMC_PowerShiftInactive ((uint16_t)0x6B)
-#define PPSMC_OCPActive ((uint16_t)0x6C)
-#define PPSMC_OCPInactive ((uint16_t)0x6D)
-#define PPSMC_CACLongTermAvgEnable ((uint16_t)0x6E)
-#define PPSMC_CACLongTermAvgDisable ((uint16_t)0x6F)
-#define PPSMC_MSG_InferredStateSweep_Start ((uint16_t)0x70)
-#define PPSMC_MSG_InferredStateSweep_Stop ((uint16_t)0x71)
-#define PPSMC_MSG_SwitchToLowestInfState ((uint16_t)0x72)
-#define PPSMC_MSG_SwitchToNonInfState ((uint16_t)0x73)
-#define PPSMC_MSG_AllStateSweep_Start ((uint16_t)0x74)
-#define PPSMC_MSG_AllStateSweep_Stop ((uint16_t)0x75)
-#define PPSMC_MSG_SwitchNextLowerInfState ((uint16_t)0x76)
-#define PPSMC_MSG_SwitchNextHigherInfState ((uint16_t)0x77)
-#define PPSMC_MSG_MclkRetrainingTest ((uint16_t)0x78)
-#define PPSMC_MSG_ForceTDPClamping ((uint16_t)0x79)
-#define PPSMC_MSG_CollectCAC_PowerCorreln ((uint16_t)0x7A)
-#define PPSMC_MSG_CollectCAC_WeightCalib ((uint16_t)0x7B)
-#define PPSMC_MSG_CollectCAC_SQonly ((uint16_t)0x7C)
-#define PPSMC_MSG_CollectCAC_TemperaturePwr ((uint16_t)0x7D)
-
-#define PPSMC_MSG_ExtremitiesTest_Start ((uint16_t)0x7E)
-#define PPSMC_MSG_ExtremitiesTest_Stop ((uint16_t)0x7F)
-#define PPSMC_FlushDataCache ((uint16_t)0x80)
-#define PPSMC_FlushInstrCache ((uint16_t)0x81)
-
-#define PPSMC_MSG_SetEnabledLevels ((uint16_t)0x82)
-#define PPSMC_MSG_SetForcedLevels ((uint16_t)0x83)
-
-#define PPSMC_MSG_ResetToDefaults ((uint16_t)0x84)
-
-#define PPSMC_MSG_SetForcedLevelsAndJump ((uint16_t)0x85)
-#define PPSMC_MSG_SetCACHistoryMode ((uint16_t)0x86)
-#define PPSMC_MSG_EnableDTE ((uint16_t)0x87)
-#define PPSMC_MSG_DisableDTE ((uint16_t)0x88)
-
-#define PPSMC_MSG_SmcSpaceSetAddress ((uint16_t)0x89)
-#define PPSM_MSG_SmcSpaceWriteDWordInc ((uint16_t)0x8A)
-#define PPSM_MSG_SmcSpaceWriteWordInc ((uint16_t)0x8B)
-#define PPSM_MSG_SmcSpaceWriteByteInc ((uint16_t)0x8C)
-
-#define PPSMC_MSG_BREAK ((uint16_t)0xF8)
-
-#define PPSMC_MSG_Test ((uint16_t) 0x100)
-#define PPSMC_MSG_DPM_Voltage_Pwrmgt ((uint16_t) 0x101)
-#define PPSMC_MSG_DPM_Config ((uint16_t) 0x102)
-#define PPSMC_MSG_PM_Controller_Start ((uint16_t) 0x103)
-#define PPSMC_MSG_DPM_ForceState ((uint16_t) 0x104)
-#define PPSMC_MSG_PG_PowerDownSIMD ((uint16_t) 0x105)
-#define PPSMC_MSG_PG_PowerUpSIMD ((uint16_t) 0x106)
-#define PPSMC_MSG_PM_Controller_Stop ((uint16_t) 0x107)
-#define PPSMC_MSG_PG_SIMD_Config ((uint16_t) 0x108)
-#define PPSMC_MSG_Voltage_Cntl_Enable ((uint16_t) 0x109)
-#define PPSMC_MSG_Thermal_Cntl_Enable ((uint16_t) 0x10a)
-#define PPSMC_MSG_Reset_Service ((uint16_t) 0x10b)
-#define PPSMC_MSG_VCEPowerOFF ((uint16_t) 0x10e)
-#define PPSMC_MSG_VCEPowerON ((uint16_t) 0x10f)
-#define PPSMC_MSG_DPM_Disable_VCE_HS ((uint16_t) 0x110)
-#define PPSMC_MSG_DPM_Enable_VCE_HS ((uint16_t) 0x111)
-#define PPSMC_MSG_DPM_N_LevelsDisabled ((uint16_t) 0x112)
-#define PPSMC_MSG_DCEPowerOFF ((uint16_t) 0x113)
-#define PPSMC_MSG_DCEPowerON ((uint16_t) 0x114)
-#define PPSMC_MSG_PCIE_DDIPowerDown ((uint16_t) 0x117)
-#define PPSMC_MSG_PCIE_DDIPowerUp ((uint16_t) 0x118)
-#define PPSMC_MSG_PCIE_CascadePLLPowerDown ((uint16_t) 0x119)
-#define PPSMC_MSG_PCIE_CascadePLLPowerUp ((uint16_t) 0x11a)
-#define PPSMC_MSG_SYSPLLPowerOff ((uint16_t) 0x11b)
-#define PPSMC_MSG_SYSPLLPowerOn ((uint16_t) 0x11c)
-#define PPSMC_MSG_DCE_RemoveVoltageAdjustment ((uint16_t) 0x11d)
-#define PPSMC_MSG_DCE_AllowVoltageAdjustment ((uint16_t) 0x11e)
-#define PPSMC_MSG_DISPLAYPHYStatusNotify ((uint16_t) 0x11f)
-#define PPSMC_MSG_EnableBAPM ((uint16_t) 0x120)
-#define PPSMC_MSG_DisableBAPM ((uint16_t) 0x121)
-#define PPSMC_MSG_Spmi_Enable ((uint16_t) 0x122)
-#define PPSMC_MSG_Spmi_Timer ((uint16_t) 0x123)
-#define PPSMC_MSG_LCLK_DPM_Config ((uint16_t) 0x124)
-#define PPSMC_MSG_VddNB_Request ((uint16_t) 0x125)
-#define PPSMC_MSG_PCIE_DDIPhyPowerDown ((uint32_t) 0x126)
-#define PPSMC_MSG_PCIE_DDIPhyPowerUp ((uint32_t) 0x127)
-#define PPSMC_MSG_MCLKDPM_Config ((uint16_t) 0x128)
-
-#define PPSMC_MSG_UVDDPM_Config ((uint16_t) 0x129)
-#define PPSMC_MSG_VCEDPM_Config ((uint16_t) 0x12A)
-#define PPSMC_MSG_ACPDPM_Config ((uint16_t) 0x12B)
-#define PPSMC_MSG_SAMUDPM_Config ((uint16_t) 0x12C)
-#define PPSMC_MSG_UVDDPM_SetEnabledMask ((uint16_t) 0x12D)
-#define PPSMC_MSG_VCEDPM_SetEnabledMask ((uint16_t) 0x12E)
-#define PPSMC_MSG_ACPDPM_SetEnabledMask ((uint16_t) 0x12F)
-#define PPSMC_MSG_SAMUDPM_SetEnabledMask ((uint16_t) 0x130)
-#define PPSMC_MSG_MCLKDPM_ForceState ((uint16_t) 0x131)
-#define PPSMC_MSG_MCLKDPM_NoForcedLevel ((uint16_t) 0x132)
-#define PPSMC_MSG_Thermal_Cntl_Disable ((uint16_t) 0x133)
-#define PPSMC_MSG_SetTDPLimit ((uint16_t) 0x134)
-#define PPSMC_MSG_Voltage_Cntl_Disable ((uint16_t) 0x135)
-#define PPSMC_MSG_PCIeDPM_Enable ((uint16_t) 0x136)
-#define PPSMC_MSG_ACPPowerOFF ((uint16_t) 0x137)
-#define PPSMC_MSG_ACPPowerON ((uint16_t) 0x138)
-#define PPSMC_MSG_SAMPowerOFF ((uint16_t) 0x139)
-#define PPSMC_MSG_SAMPowerON ((uint16_t) 0x13a)
-#define PPSMC_MSG_SDMAPowerOFF ((uint16_t) 0x13b)
-#define PPSMC_MSG_SDMAPowerON ((uint16_t) 0x13c)
-#define PPSMC_MSG_PCIeDPM_Disable ((uint16_t) 0x13d)
-#define PPSMC_MSG_IOMMUPowerOFF ((uint16_t) 0x13e)
-#define PPSMC_MSG_IOMMUPowerON ((uint16_t) 0x13f)
-#define PPSMC_MSG_NBDPM_Enable ((uint16_t) 0x140)
-#define PPSMC_MSG_NBDPM_Disable ((uint16_t) 0x141)
-#define PPSMC_MSG_NBDPM_ForceNominal ((uint16_t) 0x142)
-#define PPSMC_MSG_NBDPM_ForcePerformance ((uint16_t) 0x143)
-#define PPSMC_MSG_NBDPM_UnForce ((uint16_t) 0x144)
-#define PPSMC_MSG_SCLKDPM_SetEnabledMask ((uint16_t) 0x145)
-#define PPSMC_MSG_MCLKDPM_SetEnabledMask ((uint16_t) 0x146)
-#define PPSMC_MSG_PCIeDPM_ForceLevel ((uint16_t) 0x147)
-#define PPSMC_MSG_PCIeDPM_UnForceLevel ((uint16_t) 0x148)
-#define PPSMC_MSG_EnableACDCGPIOInterrupt ((uint16_t) 0x149)
-#define PPSMC_MSG_EnableVRHotGPIOInterrupt ((uint16_t) 0x14a)
-#define PPSMC_MSG_SwitchToAC ((uint16_t) 0x14b)
-#define PPSMC_MSG_XDMAPowerOFF ((uint16_t) 0x14c)
-#define PPSMC_MSG_XDMAPowerON ((uint16_t) 0x14d)
-
-#define PPSMC_MSG_DPM_Enable ((uint16_t) 0x14e)
-#define PPSMC_MSG_DPM_Disable ((uint16_t) 0x14f)
-#define PPSMC_MSG_MCLKDPM_Enable ((uint16_t) 0x150)
-#define PPSMC_MSG_MCLKDPM_Disable ((uint16_t) 0x151)
-#define PPSMC_MSG_LCLKDPM_Enable ((uint16_t) 0x152)
-#define PPSMC_MSG_LCLKDPM_Disable ((uint16_t) 0x153)
-#define PPSMC_MSG_UVDDPM_Enable ((uint16_t) 0x154)
-#define PPSMC_MSG_UVDDPM_Disable ((uint16_t) 0x155)
-#define PPSMC_MSG_SAMUDPM_Enable ((uint16_t) 0x156)
-#define PPSMC_MSG_SAMUDPM_Disable ((uint16_t) 0x157)
-#define PPSMC_MSG_ACPDPM_Enable ((uint16_t) 0x158)
-#define PPSMC_MSG_ACPDPM_Disable ((uint16_t) 0x159)
-#define PPSMC_MSG_VCEDPM_Enable ((uint16_t) 0x15a)
-#define PPSMC_MSG_VCEDPM_Disable ((uint16_t) 0x15b)
-#define PPSMC_MSG_LCLKDPM_SetEnabledMask ((uint16_t) 0x15c)
-#define PPSMC_MSG_DPM_FPS_Mode ((uint16_t) 0x15d)
-#define PPSMC_MSG_DPM_Activity_Mode ((uint16_t) 0x15e)
-#define PPSMC_MSG_VddC_Request ((uint16_t) 0x15f)
-#define PPSMC_MSG_MCLKDPM_GetEnabledMask ((uint16_t) 0x160)
-#define PPSMC_MSG_LCLKDPM_GetEnabledMask ((uint16_t) 0x161)
-#define PPSMC_MSG_SCLKDPM_GetEnabledMask ((uint16_t) 0x162)
-#define PPSMC_MSG_UVDDPM_GetEnabledMask ((uint16_t) 0x163)
-#define PPSMC_MSG_SAMUDPM_GetEnabledMask ((uint16_t) 0x164)
-#define PPSMC_MSG_ACPDPM_GetEnabledMask ((uint16_t) 0x165)
-#define PPSMC_MSG_VCEDPM_GetEnabledMask ((uint16_t) 0x166)
-#define PPSMC_MSG_PCIeDPM_SetEnabledMask ((uint16_t) 0x167)
-#define PPSMC_MSG_PCIeDPM_GetEnabledMask ((uint16_t) 0x168)
-#define PPSMC_MSG_TDCLimitEnable ((uint16_t) 0x169)
-#define PPSMC_MSG_TDCLimitDisable ((uint16_t) 0x16a)
-#define PPSMC_MSG_DPM_AutoRotate_Mode ((uint16_t) 0x16b)
-#define PPSMC_MSG_DISPCLK_FROM_FCH ((uint16_t) 0x16c)
-#define PPSMC_MSG_DISPCLK_FROM_DFS ((uint16_t) 0x16d)
-#define PPSMC_MSG_DPREFCLK_FROM_FCH ((uint16_t) 0x16e)
-#define PPSMC_MSG_DPREFCLK_FROM_DFS ((uint16_t) 0x16f)
-#define PPSMC_MSG_PmStatusLogStart ((uint16_t) 0x170)
-#define PPSMC_MSG_PmStatusLogSample ((uint16_t) 0x171)
-#define PPSMC_MSG_SCLK_AutoDPM_ON ((uint16_t) 0x172)
-#define PPSMC_MSG_MCLK_AutoDPM_ON ((uint16_t) 0x173)
-#define PPSMC_MSG_LCLK_AutoDPM_ON ((uint16_t) 0x174)
-#define PPSMC_MSG_UVD_AutoDPM_ON ((uint16_t) 0x175)
-#define PPSMC_MSG_SAMU_AutoDPM_ON ((uint16_t) 0x176)
-#define PPSMC_MSG_ACP_AutoDPM_ON ((uint16_t) 0x177)
-#define PPSMC_MSG_VCE_AutoDPM_ON ((uint16_t) 0x178)
-#define PPSMC_MSG_PCIe_AutoDPM_ON ((uint16_t) 0x179)
-#define PPSMC_MSG_MASTER_AutoDPM_ON ((uint16_t) 0x17a)
-#define PPSMC_MSG_MASTER_AutoDPM_OFF ((uint16_t) 0x17b)
-#define PPSMC_MSG_DYNAMICDISPPHYPOWER ((uint16_t) 0x17c)
-#define PPSMC_MSG_CAC_COLLECTION_ON ((uint16_t) 0x17d)
-#define PPSMC_MSG_CAC_COLLECTION_OFF ((uint16_t) 0x17e)
-#define PPSMC_MSG_CAC_CORRELATION_ON ((uint16_t) 0x17f)
-#define PPSMC_MSG_CAC_CORRELATION_OFF ((uint16_t) 0x180)
-#define PPSMC_MSG_PM_STATUS_TO_DRAM_ON ((uint16_t) 0x181)
-#define PPSMC_MSG_PM_STATUS_TO_DRAM_OFF ((uint16_t) 0x182)
-#define PPSMC_MSG_ALLOW_LOWSCLK_INTERRUPT ((uint16_t) 0x184)
-#define PPSMC_MSG_PkgPwrLimitEnable ((uint16_t) 0x185)
-#define PPSMC_MSG_PkgPwrLimitDisable ((uint16_t) 0x186)
-#define PPSMC_MSG_PkgPwrSetLimit ((uint16_t) 0x187)
-#define PPSMC_MSG_OverDriveSetTargetTdp ((uint16_t) 0x188)
-#define PPSMC_MSG_SCLKDPM_FreezeLevel ((uint16_t) 0x189)
-#define PPSMC_MSG_SCLKDPM_UnfreezeLevel ((uint16_t) 0x18A)
-#define PPSMC_MSG_MCLKDPM_FreezeLevel ((uint16_t) 0x18B)
-#define PPSMC_MSG_MCLKDPM_UnfreezeLevel ((uint16_t) 0x18C)
-#define PPSMC_MSG_START_DRAM_LOGGING ((uint16_t) 0x18D)
-#define PPSMC_MSG_STOP_DRAM_LOGGING ((uint16_t) 0x18E)
-#define PPSMC_MSG_MASTER_DeepSleep_ON ((uint16_t) 0x18F)
-#define PPSMC_MSG_MASTER_DeepSleep_OFF ((uint16_t) 0x190)
-#define PPSMC_MSG_Remove_DC_Clamp ((uint16_t) 0x191)
-#define PPSMC_MSG_DisableACDCGPIOInterrupt ((uint16_t) 0x192)
-#define PPSMC_MSG_OverrideVoltageControl_SetVddc ((uint16_t) 0x193)
-#define PPSMC_MSG_OverrideVoltageControl_SetVddci ((uint16_t) 0x194)
-#define PPSMC_MSG_SetVidOffset_1 ((uint16_t) 0x195)
-#define PPSMC_MSG_SetVidOffset_2 ((uint16_t) 0x207)
-#define PPSMC_MSG_GetVidOffset_1 ((uint16_t) 0x196)
-#define PPSMC_MSG_GetVidOffset_2 ((uint16_t) 0x208)
-#define PPSMC_MSG_THERMAL_OVERDRIVE_Enable ((uint16_t) 0x197)
-#define PPSMC_MSG_THERMAL_OVERDRIVE_Disable ((uint16_t) 0x198)
-#define PPSMC_MSG_SetTjMax ((uint16_t) 0x199)
-#define PPSMC_MSG_SetFanPwmMax ((uint16_t) 0x19A)
-#define PPSMC_MSG_WaitForMclkSwitchFinish ((uint16_t) 0x19B)
-#define PPSMC_MSG_ENABLE_THERMAL_DPM ((uint16_t) 0x19C)
-#define PPSMC_MSG_DISABLE_THERMAL_DPM ((uint16_t) 0x19D)
-
-#define PPSMC_MSG_API_GetSclkFrequency ((uint16_t) 0x200)
-#define PPSMC_MSG_API_GetMclkFrequency ((uint16_t) 0x201)
-#define PPSMC_MSG_API_GetSclkBusy ((uint16_t) 0x202)
-#define PPSMC_MSG_API_GetMclkBusy ((uint16_t) 0x203)
-#define PPSMC_MSG_API_GetAsicPower ((uint16_t) 0x204)
-#define PPSMC_MSG_SetFanRpmMax ((uint16_t) 0x205)
-#define PPSMC_MSG_SetFanSclkTarget ((uint16_t) 0x206)
-#define PPSMC_MSG_SetFanMinPwm ((uint16_t) 0x209)
-#define PPSMC_MSG_SetFanTemperatureTarget ((uint16_t) 0x20A)
-
-#define PPSMC_MSG_BACO_StartMonitor ((uint16_t) 0x240)
-#define PPSMC_MSG_BACO_Cancel ((uint16_t) 0x241)
-#define PPSMC_MSG_EnableVddGfx ((uint16_t) 0x242)
-#define PPSMC_MSG_DisableVddGfx ((uint16_t) 0x243)
-#define PPSMC_MSG_UcodeAddressLow ((uint16_t) 0x244)
-#define PPSMC_MSG_UcodeAddressHigh ((uint16_t) 0x245)
-#define PPSMC_MSG_UcodeLoadStatus ((uint16_t) 0x246)
-
-#define PPSMC_MSG_DRV_DRAM_ADDR_HI ((uint16_t) 0x250)
-#define PPSMC_MSG_DRV_DRAM_ADDR_LO ((uint16_t) 0x251)
-#define PPSMC_MSG_SMU_DRAM_ADDR_HI ((uint16_t) 0x252)
-#define PPSMC_MSG_SMU_DRAM_ADDR_LO ((uint16_t) 0x253)
-#define PPSMC_MSG_LoadUcodes ((uint16_t) 0x254)
-#define PPSMC_MSG_PowerStateNotify ((uint16_t) 0x255)
-#define PPSMC_MSG_COND_EXEC_DRAM_ADDR_HI ((uint16_t) 0x256)
-#define PPSMC_MSG_COND_EXEC_DRAM_ADDR_LO ((uint16_t) 0x257)
-#define PPSMC_MSG_VBIOS_DRAM_ADDR_HI ((uint16_t) 0x258)
-#define PPSMC_MSG_VBIOS_DRAM_ADDR_LO ((uint16_t) 0x259)
-#define PPSMC_MSG_LoadVBios ((uint16_t) 0x25A)
-#define PPSMC_MSG_GetUcodeVersion ((uint16_t) 0x25B)
-#define DMCUSMC_MSG_PSREntry ((uint16_t) 0x25C)
-#define DMCUSMC_MSG_PSRExit ((uint16_t) 0x25D)
-#define PPSMC_MSG_EnableClockGatingFeature ((uint16_t) 0x260)
-#define PPSMC_MSG_DisableClockGatingFeature ((uint16_t) 0x261)
-#define PPSMC_MSG_IsDeviceRunning ((uint16_t) 0x262)
-#define PPSMC_MSG_LoadMetaData ((uint16_t) 0x263)
-#define PPSMC_MSG_TMON_AutoCaliberate_Enable ((uint16_t) 0x264)
-#define PPSMC_MSG_TMON_AutoCaliberate_Disable ((uint16_t) 0x265)
-#define PPSMC_MSG_GetTelemetry1Slope ((uint16_t) 0x266)
-#define PPSMC_MSG_GetTelemetry1Offset ((uint16_t) 0x267)
-#define PPSMC_MSG_GetTelemetry2Slope ((uint16_t) 0x268)
-#define PPSMC_MSG_GetTelemetry2Offset ((uint16_t) 0x269)
-#define PPSMC_MSG_EnableAvfs ((uint16_t) 0x26A)
-#define PPSMC_MSG_DisableAvfs ((uint16_t) 0x26B)
-
-#define PPSMC_MSG_PerformBtc ((uint16_t) 0x26C)
-#define PPSMC_MSG_VftTableIsValid ((uint16_t) 0x275)
-#define PPSMC_MSG_UseNewGPIOScheme ((uint16_t) 0x277)
-#define PPSMC_MSG_GetEnabledPsm ((uint16_t) 0x400)
-#define PPSMC_MSG_AgmStartPsm ((uint16_t) 0x401)
-#define PPSMC_MSG_AgmReadPsm ((uint16_t) 0x402)
-#define PPSMC_MSG_AgmResetPsm ((uint16_t) 0x403)
-#define PPSMC_MSG_ReadVftCell ((uint16_t) 0x404)
-
-#define PPSMC_MSG_GFX_CU_PG_ENABLE ((uint16_t) 0x280)
-#define PPSMC_MSG_GFX_CU_PG_DISABLE ((uint16_t) 0x281)
-#define PPSMC_MSG_GetCurrPkgPwr ((uint16_t) 0x282)
-
-#define PPSMC_MSG_SetGpuPllDfsForSclk ((uint16_t) 0x300)
-#define PPSMC_MSG_Didt_Block_Function ((uint16_t) 0x301)
-
-#define PPSMC_MSG_SetVBITimeout ((uint16_t) 0x306)
-
-#define PPSMC_MSG_SecureSRBMWrite ((uint16_t) 0x600)
-#define PPSMC_MSG_SecureSRBMRead ((uint16_t) 0x601)
-#define PPSMC_MSG_SetAddress ((uint16_t) 0x800)
-#define PPSMC_MSG_GetData ((uint16_t) 0x801)
-#define PPSMC_MSG_SetData ((uint16_t) 0x802)
-
-typedef uint16_t PPSMC_Msg;
-
-#define PPSMC_EVENT_STATUS_THERMAL 0x00000001
-#define PPSMC_EVENT_STATUS_REGULATORHOT 0x00000002
-#define PPSMC_EVENT_STATUS_DC 0x00000004
-
-#pragma pack(pop)
-
-#endif
-
diff --git a/drivers/gpu/drm/amd/powerplay/inc/power_state.h b/drivers/gpu/drm/amd/powerplay/inc/power_state.h
index 827860fffe78..a99b5cbb113e 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/power_state.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/power_state.h
@@ -122,8 +122,8 @@ struct PP_StateSoftwareAlgorithmBlock {
* Type to hold a temperature range.
*/
struct PP_TemperatureRange {
- uint32_t min;
- uint32_t max;
+ int min;
+ int max;
};
struct PP_StateValidationBlock {
diff --git a/drivers/gpu/drm/amd/powerplay/inc/pp_acpi.h b/drivers/gpu/drm/amd/powerplay/inc/pp_acpi.h
deleted file mode 100644
index 8fe8ba9434ff..000000000000
--- a/drivers/gpu/drm/amd/powerplay/inc/pp_acpi.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * Copyright 2015 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-bool acpi_atcs_functions_supported(void *device, uint32_t index);
-int acpi_pcie_perf_request(void *device, uint8_t perf_req, bool advertise);
-bool acpi_atcs_notify_pcie_device_ready(void *device);
diff --git a/drivers/gpu/drm/amd/powerplay/inc/pp_asicblocks.h b/drivers/gpu/drm/amd/powerplay/inc/pp_asicblocks.h
deleted file mode 100644
index 0c1593e53654..000000000000
--- a/drivers/gpu/drm/amd/powerplay/inc/pp_asicblocks.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Copyright 2015 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-#ifndef PP_ASICBLOCKS_H
-#define PP_ASICBLOCKS_H
-
-
-enum PHM_AsicBlock {
- PHM_AsicBlock_GFX,
- PHM_AsicBlock_UVD_MVC,
- PHM_AsicBlock_UVD,
- PHM_AsicBlock_UVD_HD,
- PHM_AsicBlock_UVD_SD,
- PHM_AsicBlock_Count
-};
-
-enum PHM_ClockGateSetting {
- PHM_ClockGateSetting_StaticOn,
- PHM_ClockGateSetting_StaticOff,
- PHM_ClockGateSetting_Dynamic
-};
-
-struct phm_asic_blocks {
- bool gfx : 1;
- bool uvd : 1;
-};
-
-#endif
diff --git a/drivers/gpu/drm/amd/powerplay/inc/pp_feature.h b/drivers/gpu/drm/amd/powerplay/inc/pp_feature.h
deleted file mode 100644
index 0faf6a25c18b..000000000000
--- a/drivers/gpu/drm/amd/powerplay/inc/pp_feature.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * Copyright 2015 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#ifndef _PP_FEATURE_H_
-#define _PP_FEATURE_H_
-
-/**
- * PowerPlay feature ids.
- */
-enum pp_feature {
- PP_Feature_PowerPlay = 0,
- PP_Feature_User2DPerformance,
- PP_Feature_User3DPerformance,
- PP_Feature_VariBright,
- PP_Feature_VariBrightOnPowerXpress,
- PP_Feature_ReducedRefreshRate,
- PP_Feature_GFXClockGating,
- PP_Feature_OverdriveTest,
- PP_Feature_OverDrive,
- PP_Feature_PowerBudgetWaiver,
- PP_Feature_PowerControl,
- PP_Feature_PowerControl_2,
- PP_Feature_MultiUVDState,
- PP_Feature_Force3DClock,
- PP_Feature_BACO,
- PP_Feature_PowerDown,
- PP_Feature_DynamicUVDState,
- PP_Feature_VCEDPM,
- PP_Feature_PPM,
- PP_Feature_ACP_POWERGATING,
- PP_Feature_FFC,
- PP_Feature_FPS,
- PP_Feature_ViPG,
- PP_Feature_Max
-};
-
-/**
- * Struct for PowerPlay feature info.
- */
-struct pp_feature_info {
- bool supported; /* feature supported by PowerPlay */
- bool enabled; /* feature enabled in PowerPlay */
- bool enabled_default; /* default enable status of the feature */
- uint32_t version; /* feature version */
-};
-
-#endif /* _PP_FEATURE_H_ */
diff --git a/drivers/gpu/drm/amd/powerplay/inc/pp_soc15.h b/drivers/gpu/drm/amd/powerplay/inc/pp_soc15.h
index b7ab69e4c254..214f370c5efd 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/pp_soc15.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/pp_soc15.h
@@ -23,7 +23,8 @@
#ifndef PP_SOC15_H
#define PP_SOC15_H
-#include "soc15ip.h"
+#include "soc15_hw_ip.h"
+#include "vega10_ip_offset.h"
inline static uint32_t soc15_get_register_offset(
uint32_t hw_id,
@@ -43,7 +44,8 @@ inline static uint32_t soc15_get_register_offset(
reg = DF_BASE.instance[inst].segment[segment] + offset;
else if (hw_id == GC_HWID)
reg = GC_BASE.instance[inst].segment[segment] + offset;
-
+ else if (hw_id == SMUIO_HWID)
+ reg = SMUIO_BASE.instance[inst].segment[segment] + offset;
return reg;
}
diff --git a/drivers/gpu/drm/amd/powerplay/inc/pp_instance.h b/drivers/gpu/drm/amd/powerplay/inc/pp_thermal.h
index 7d1eec5d2e7a..201d2b6329ab 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/pp_instance.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/pp_thermal.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2015 Advanced Micro Devices, Inc.
+ * Copyright 2018 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -20,19 +20,21 @@
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
-#ifndef _PP_INSTANCE_H_
-#define _PP_INSTANCE_H_
+#ifndef PP_THERMAL_H
+#define PP_THERMAL_H
-#include "hwmgr.h"
+#include "power_state.h"
-struct pp_instance {
- uint32_t chip_family;
- uint32_t chip_id;
- bool pm_en;
- uint32_t feature_mask;
- void *device;
- struct pp_hwmgr *hwmgr;
- struct mutex pp_lock;
+static const struct PP_TemperatureRange SMU7ThermalWithDelayPolicy[] =
+{
+ {-273150, 99000},
+ { 120000, 120000},
+};
+
+static const struct PP_TemperatureRange SMU7ThermalPolicy[] =
+{
+ {-273150, 99000},
+ { 120000, 120000},
};
#endif
diff --git a/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
index f15f4df9d0a9..426bff2aad2b 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
@@ -80,7 +80,8 @@
#define PPSMC_MSG_SetSoftMaxSocclkByFreq 0x32
#define PPSMC_MSG_SetSoftMaxFclkByFreq 0x33
#define PPSMC_MSG_SetSoftMaxVcn 0x34
-#define PPSMC_Message_Count 0x35
+#define PPSMC_MSG_PowerGateMmHub 0x35
+#define PPSMC_Message_Count 0x36
typedef uint16_t PPSMC_Result;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu7.h b/drivers/gpu/drm/amd/powerplay/inc/smu7.h
index 75a380a15292..e14072d45918 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu7.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu7.h
@@ -82,6 +82,25 @@
#define SCRATCH_B_CURR_SAMU_INDEX_MASK (0x7<<SCRATCH_B_CURR_SAMU_INDEX_SHIFT)
+/* Voltage Regulator Configuration */
+/* VR Config info is contained in dpmTable */
+
+#define VRCONF_VDDC_MASK 0x000000FF
+#define VRCONF_VDDC_SHIFT 0
+#define VRCONF_VDDGFX_MASK 0x0000FF00
+#define VRCONF_VDDGFX_SHIFT 8
+#define VRCONF_VDDCI_MASK 0x00FF0000
+#define VRCONF_VDDCI_SHIFT 16
+#define VRCONF_MVDD_MASK 0xFF000000
+#define VRCONF_MVDD_SHIFT 24
+
+#define VR_MERGED_WITH_VDDC 0
+#define VR_SVI2_PLANE_1 1
+#define VR_SVI2_PLANE_2 2
+#define VR_SMIO_PATTERN_1 3
+#define VR_SMIO_PATTERN_2 4
+#define VR_STATIC_VOLTAGE 5
+
struct SMU7_PIDController
{
uint32_t Ki;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h b/drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h
index 0b0b404ff091..ee876745dd12 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h
@@ -316,7 +316,8 @@ struct SMU7_Discrete_DpmTable
uint8_t AcpLevelCount;
uint8_t SamuLevelCount;
uint8_t MasterDeepSleepControl;
- uint32_t Reserved[5];
+ uint32_t VRConfig;
+ uint32_t Reserved[4];
// uint32_t SamuDefaultLevel;
SMU7_Discrete_GraphicsLevel GraphicsLevel [SMU7_MAX_LEVELS_GRAPHICS];
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu9.h b/drivers/gpu/drm/amd/powerplay/inc/smu9.h
index 550ed675027a..70ac4d477be2 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu9.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu9.h
@@ -58,7 +58,7 @@
#define FEATURE_FAST_PPT_BIT 26
#define FEATURE_GFX_EDC_BIT 27
#define FEATURE_ACG_BIT 28
-#define FEATURE_SPARE_29_BIT 29
+#define FEATURE_PCC_LIMIT_CONTROL_BIT 29
#define FEATURE_SPARE_30_BIT 30
#define FEATURE_SPARE_31_BIT 31
@@ -94,7 +94,7 @@
#define FEATURE_FAST_PPT_MASK (1 << FAST_PPT_BIT )
#define FEATURE_GFX_EDC_MASK (1 << FEATURE_GFX_EDC_BIT )
#define FEATURE_ACG_MASK (1 << FEATURE_ACG_BIT )
-#define FFEATURE_SPARE_29_MASK (1 << FEATURE_SPARE_29_BIT )
+#define FEATURE_PCC_LIMIT_CONTROL_MASK (1 << FEATURE_PCC_LIMIT_CONTROL_BIT )
#define FFEATURE_SPARE_30_MASK (1 << FEATURE_SPARE_30_BIT )
#define FFEATURE_SPARE_31_MASK (1 << FEATURE_SPARE_31_BIT )
/* Workload types */
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
index b1b27b2128f6..fc3a2a533586 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
@@ -26,32 +26,6 @@
#include "amd_powerplay.h"
#include "hwmgr.h"
-#define smu_lower_32_bits(n) ((uint32_t)(n))
-#define smu_upper_32_bits(n) ((uint32_t)(((n)>>16)>>16))
-
-
-
-enum AVFS_BTC_STATUS {
- AVFS_BTC_BOOT = 0,
- AVFS_BTC_BOOT_STARTEDSMU,
- AVFS_LOAD_VIRUS,
- AVFS_BTC_VIRUS_LOADED,
- AVFS_BTC_VIRUS_FAIL,
- AVFS_BTC_COMPLETED_PREVIOUSLY,
- AVFS_BTC_ENABLEAVFS,
- AVFS_BTC_STARTED,
- AVFS_BTC_FAILED,
- AVFS_BTC_RESTOREVFT_FAILED,
- AVFS_BTC_SAVEVFT_FAILED,
- AVFS_BTC_DPMTABLESETUP_FAILED,
- AVFS_BTC_COMPLETED_UNSAVED,
- AVFS_BTC_COMPLETED_SAVED,
- AVFS_BTC_COMPLETED_RESTORED,
- AVFS_BTC_DISABLED,
- AVFS_BTC_NOTSUPPORTED,
- AVFS_BTC_SMUMSG_ERROR
-};
-
enum SMU_TABLE {
SMU_UVD_TABLE = 0,
SMU_VCE_TABLE,
@@ -95,6 +69,11 @@ enum SMU_MAC_DEFINITION {
SMU_UVD_MCLK_HANDSHAKE_DISABLE,
};
+enum SMU10_TABLE_ID {
+ SMU10_WMTABLE = 0,
+ SMU10_CLOCKTABLE,
+};
+
extern int smum_get_argument(struct pp_hwmgr *hwmgr);
extern int smum_download_powerplay_table(struct pp_hwmgr *hwmgr, void **table);
@@ -106,13 +85,6 @@ extern int smum_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg);
extern int smum_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
uint16_t msg, uint32_t parameter);
-extern int smu_allocate_memory(void *device, uint32_t size,
- enum cgs_gpu_mem_type type,
- uint32_t byte_align, uint64_t *mc_addr,
- void **kptr, void *handle);
-
-extern int smu_free_memory(void *device, void *handle);
-
extern int smum_update_sclk_threshold(struct pp_hwmgr *hwmgr);
extern int smum_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type);
@@ -129,10 +101,10 @@ extern uint32_t smum_get_mac_definition(struct pp_hwmgr *hwmgr, uint32_t value);
extern bool smum_is_dpm_running(struct pp_hwmgr *hwmgr);
-extern int smum_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr,
- struct amd_pp_profile *request);
-
extern bool smum_is_hw_avfs_present(struct pp_hwmgr *hwmgr);
+extern int smum_update_dpm_settings(struct pp_hwmgr *hwmgr, void *profile_setting);
+
+extern int smum_smc_table_manager(struct pp_hwmgr *hwmgr, uint8_t *table, uint16_t table_id, bool rw);
#endif
diff --git a/drivers/gpu/drm/amd/powerplay/inc/vega10_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/vega10_ppsmc.h
index 247c97397a27..c3ed737ab951 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/vega10_ppsmc.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/vega10_ppsmc.h
@@ -131,6 +131,7 @@ typedef uint16_t PPSMC_Result;
#define PPSMC_MSG_RunAcgInOpenLoop 0x5E
#define PPSMC_MSG_InitializeAcg 0x5F
#define PPSMC_MSG_GetCurrPkgPwr 0x61
+#define PPSMC_MSG_SetPccThrottleLevel 0x67
#define PPSMC_MSG_UpdatePkgPwrPidAlpha 0x68
#define PPSMC_Message_Count 0x69