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-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/Makefile8
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c209
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.h36
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c54
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c646
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/pp_acpi.c114
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c11
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c8
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c14
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c (renamed from drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c)548
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h (renamed from drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h)130
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/smu10_inc.h (renamed from drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h)4
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c19
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h1
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/smu7_dyn_defaults.h2
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c874
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h34
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c17
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c4
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c (renamed from drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c)1071
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h (renamed from drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.h)82
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c536
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h180
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c520
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h11
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c57
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c21
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c18
28 files changed, 2679 insertions, 2550 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
index a212c27f2e17..f868b955da92 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
@@ -24,14 +24,14 @@
# It provides the hardware management services for the driver.
HARDWARE_MGR = hwmgr.o processpptables.o \
- hardwaremanager.o pp_acpi.o cz_hwmgr.o \
- cz_clockpowergating.o pppcielanes.o\
+ hardwaremanager.o smu8_hwmgr.o \
+ pppcielanes.o\
process_pptables_v1_0.o ppatomctrl.o ppatomfwctrl.o \
smu7_hwmgr.o smu7_powertune.o smu7_thermal.o \
smu7_clockpowergating.o \
vega10_processpptables.o vega10_hwmgr.o vega10_powertune.o \
- vega10_thermal.o rv_hwmgr.o pp_psm.o\
- pp_overdriver.o
+ vega10_thermal.o smu10_hwmgr.o pp_psm.o\
+ pp_overdriver.o smu_helper.o
AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR))
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c
deleted file mode 100644
index 44de0874629f..000000000000
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c
+++ /dev/null
@@ -1,209 +0,0 @@
-/*
- * Copyright 2015 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#include "hwmgr.h"
-#include "cz_clockpowergating.h"
-#include "cz_ppsmc.h"
-
-/* PhyID -> Status Mapping in DDI_PHY_GEN_STATUS
- 0 GFX0L (3:0), (27:24),
- 1 GFX0H (7:4), (31:28),
- 2 GFX1L (3:0), (19:16),
- 3 GFX1H (7:4), (23:20),
- 4 DDIL (3:0), (11: 8),
- 5 DDIH (7:4), (15:12),
- 6 DDI2L (3:0), ( 3: 0),
- 7 DDI2H (7:4), ( 7: 4),
-*/
-#define DDI_PHY_GEN_STATUS_VAL(phyID) (1 << ((3 - ((phyID & 0x07)/2))*8 + (phyID & 0x01)*4))
-#define IS_PHY_ID_USED_BY_PLL(PhyID) (((0xF3 & (1 << PhyID)) & 0xFF) ? true : false)
-
-
-int cz_phm_set_asic_block_gating(struct pp_hwmgr *hwmgr, enum PHM_AsicBlock block, enum PHM_ClockGateSetting gating)
-{
- int ret = 0;
-
- switch (block) {
- case PHM_AsicBlock_UVD_MVC:
- case PHM_AsicBlock_UVD:
- case PHM_AsicBlock_UVD_HD:
- case PHM_AsicBlock_UVD_SD:
- if (gating == PHM_ClockGateSetting_StaticOff)
- ret = cz_dpm_powerdown_uvd(hwmgr);
- else
- ret = cz_dpm_powerup_uvd(hwmgr);
- break;
- case PHM_AsicBlock_GFX:
- default:
- break;
- }
-
- return ret;
-}
-
-
-bool cz_phm_is_safe_for_asic_block(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, enum PHM_AsicBlock block)
-{
- return true;
-}
-
-
-int cz_phm_enable_disable_gfx_power_gating(struct pp_hwmgr *hwmgr, bool enable)
-{
- return 0;
-}
-
-int cz_phm_smu_power_up_down_pcie(struct pp_hwmgr *hwmgr, uint32_t target, bool up, uint32_t args)
-{
- /* TODO */
- return 0;
-}
-
-int cz_phm_initialize_display_phy_access(struct pp_hwmgr *hwmgr, bool initialize, bool accesshw)
-{
- /* TODO */
- return 0;
-}
-
-int cz_phm_get_display_phy_access_info(struct pp_hwmgr *hwmgr)
-{
- /* TODO */
- return 0;
-}
-
-int cz_phm_gate_unused_display_phys(struct pp_hwmgr *hwmgr)
-{
- /* TODO */
- return 0;
-}
-
-int cz_phm_ungate_all_display_phys(struct pp_hwmgr *hwmgr)
-{
- /* TODO */
- return 0;
-}
-
-int cz_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
-{
- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
- uint32_t dpm_features = 0;
-
- if (enable &&
- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_UVDDPM)) {
- cz_hwmgr->dpm_flags |= DPMFlags_UVD_Enabled;
- dpm_features |= UVD_DPM_MASK;
- smum_send_msg_to_smc_with_parameter(hwmgr,
- PPSMC_MSG_EnableAllSmuFeatures, dpm_features);
- } else {
- dpm_features |= UVD_DPM_MASK;
- cz_hwmgr->dpm_flags &= ~DPMFlags_UVD_Enabled;
- smum_send_msg_to_smc_with_parameter(hwmgr,
- PPSMC_MSG_DisableAllSmuFeatures, dpm_features);
- }
- return 0;
-}
-
-int cz_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
-{
- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
- uint32_t dpm_features = 0;
-
- if (enable && phm_cap_enabled(
- hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_VCEDPM)) {
- cz_hwmgr->dpm_flags |= DPMFlags_VCE_Enabled;
- dpm_features |= VCE_DPM_MASK;
- smum_send_msg_to_smc_with_parameter(hwmgr,
- PPSMC_MSG_EnableAllSmuFeatures, dpm_features);
- } else {
- dpm_features |= VCE_DPM_MASK;
- cz_hwmgr->dpm_flags &= ~DPMFlags_VCE_Enabled;
- smum_send_msg_to_smc_with_parameter(hwmgr,
- PPSMC_MSG_DisableAllSmuFeatures, dpm_features);
- }
-
- return 0;
-}
-
-
-void cz_dpm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
-{
- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
-
- cz_hwmgr->uvd_power_gated = bgate;
-
- if (bgate) {
- cgs_set_powergating_state(hwmgr->device,
- AMD_IP_BLOCK_TYPE_UVD,
- AMD_PG_STATE_GATE);
- cgs_set_clockgating_state(hwmgr->device,
- AMD_IP_BLOCK_TYPE_UVD,
- AMD_CG_STATE_GATE);
- cz_dpm_update_uvd_dpm(hwmgr, true);
- cz_dpm_powerdown_uvd(hwmgr);
- } else {
- cz_dpm_powerup_uvd(hwmgr);
- cgs_set_clockgating_state(hwmgr->device,
- AMD_IP_BLOCK_TYPE_UVD,
- AMD_PG_STATE_UNGATE);
- cgs_set_powergating_state(hwmgr->device,
- AMD_IP_BLOCK_TYPE_UVD,
- AMD_CG_STATE_UNGATE);
- cz_dpm_update_uvd_dpm(hwmgr, false);
- }
-
-}
-
-void cz_dpm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
-{
- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
-
- if (bgate) {
- cgs_set_powergating_state(
- hwmgr->device,
- AMD_IP_BLOCK_TYPE_VCE,
- AMD_PG_STATE_GATE);
- cgs_set_clockgating_state(
- hwmgr->device,
- AMD_IP_BLOCK_TYPE_VCE,
- AMD_CG_STATE_GATE);
- cz_enable_disable_vce_dpm(hwmgr, false);
- cz_dpm_powerdown_vce(hwmgr);
- cz_hwmgr->vce_power_gated = true;
- } else {
- cz_dpm_powerup_vce(hwmgr);
- cz_hwmgr->vce_power_gated = false;
- cgs_set_clockgating_state(
- hwmgr->device,
- AMD_IP_BLOCK_TYPE_VCE,
- AMD_PG_STATE_UNGATE);
- cgs_set_powergating_state(
- hwmgr->device,
- AMD_IP_BLOCK_TYPE_VCE,
- AMD_CG_STATE_UNGATE);
- cz_dpm_update_vce_dpm(hwmgr);
- cz_enable_disable_vce_dpm(hwmgr, true);
- }
-}
-
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.h b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.h
deleted file mode 100644
index 92f707bc46e7..000000000000
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * Copyright 2015 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#ifndef _CZ_CLOCK_POWER_GATING_H_
-#define _CZ_CLOCK_POWER_GATING_H_
-
-#include "cz_hwmgr.h"
-#include "pp_asicblocks.h"
-
-extern int cz_phm_set_asic_block_gating(struct pp_hwmgr *hwmgr, enum PHM_AsicBlock block, enum PHM_ClockGateSetting gating);
-extern const struct phm_master_table_header cz_phm_enable_clock_power_gatings_master;
-extern void cz_dpm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate);
-extern void cz_dpm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate);
-extern int cz_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable);
-extern int cz_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable);
-#endif /* _CZ_CLOCK_POWER_GATING_H_ */
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
index 2b0c53fe4c8d..b784131d0f87 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
@@ -79,6 +79,11 @@ int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr)
bool enabled;
PHM_FUNC_CHECK(hwmgr);
+ if (smum_is_dpm_running(hwmgr)) {
+ pr_info("dpm has been enabled\n");
+ return 0;
+ }
+
if (NULL != hwmgr->hwmgr_func->dynamic_state_management_enable)
ret = hwmgr->hwmgr_func->dynamic_state_management_enable(hwmgr);
@@ -96,6 +101,11 @@ int phm_disable_dynamic_state_management(struct pp_hwmgr *hwmgr)
PHM_FUNC_CHECK(hwmgr);
+ if (!smum_is_dpm_running(hwmgr)) {
+ pr_info("dpm has been disabled\n");
+ return 0;
+ }
+
if (hwmgr->hwmgr_func->dynamic_state_management_disable)
ret = hwmgr->hwmgr_func->dynamic_state_management_disable(hwmgr);
@@ -118,23 +128,6 @@ int phm_force_dpm_levels(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level
return ret;
}
-int phm_reset_power_profile_state(struct pp_hwmgr *hwmgr)
-{
- int ret = 0;
-
- if (hwmgr->hwmgr_func->set_power_profile_state) {
- if (hwmgr->current_power_profile == AMD_PP_GFX_PROFILE)
- ret = hwmgr->hwmgr_func->set_power_profile_state(
- hwmgr,
- &hwmgr->gfx_power_profile);
- else if (hwmgr->current_power_profile == AMD_PP_COMPUTE_PROFILE)
- ret = hwmgr->hwmgr_func->set_power_profile_state(
- hwmgr,
- &hwmgr->compute_power_profile);
- }
- return ret;
-}
-
int phm_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
struct pp_power_state *adjusted_ps,
const struct pp_power_state *current_ps)
@@ -223,26 +216,27 @@ int phm_register_thermal_interrupt(struct pp_hwmgr *hwmgr, const void *info)
* Initializes the thermal controller subsystem.
*
* @param pHwMgr the address of the powerplay hardware manager.
-* @param pTemperatureRange the address of the structure holding the temperature range.
* @exception PP_Result_Failed if any of the paramters is NULL, otherwise the return value from the dispatcher.
*/
-int phm_start_thermal_controller(struct pp_hwmgr *hwmgr, struct PP_TemperatureRange *temperature_range)
+int phm_start_thermal_controller(struct pp_hwmgr *hwmgr)
{
- struct PP_TemperatureRange range;
-
- if (temperature_range == NULL) {
- range.max = TEMP_RANGE_MAX;
- range.min = TEMP_RANGE_MIN;
- } else {
- range.max = temperature_range->max;
- range.min = temperature_range->min;
- }
+ int ret = 0;
+ struct PP_TemperatureRange range = {TEMP_RANGE_MIN, TEMP_RANGE_MAX};
+ struct amdgpu_device *adev = hwmgr->adev;
+
+ if (hwmgr->hwmgr_func->get_thermal_temperature_range)
+ hwmgr->hwmgr_func->get_thermal_temperature_range(
+ hwmgr, &range);
+
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_ThermalController)
&& hwmgr->hwmgr_func->start_thermal_controller != NULL)
- return hwmgr->hwmgr_func->start_thermal_controller(hwmgr, &range);
+ ret = hwmgr->hwmgr_func->start_thermal_controller(hwmgr, &range);
- return 0;
+ adev->pm.dpm.thermal.min_temp = range.min;
+ adev->pm.dpm.thermal.max_temp = range.max;
+
+ return ret;
}
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
index 0229f774f7a9..229030027f3e 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
@@ -30,23 +30,24 @@
#include <drm/amdgpu_drm.h>
#include "power_state.h"
#include "hwmgr.h"
-#include "pppcielanes.h"
-#include "ppatomctrl.h"
#include "ppsmc.h"
-#include "pp_acpi.h"
#include "amd_acpi.h"
#include "pp_psm.h"
extern const struct pp_smumgr_func ci_smu_funcs;
-extern const struct pp_smumgr_func cz_smu_funcs;
+extern const struct pp_smumgr_func smu8_smu_funcs;
extern const struct pp_smumgr_func iceland_smu_funcs;
extern const struct pp_smumgr_func tonga_smu_funcs;
extern const struct pp_smumgr_func fiji_smu_funcs;
extern const struct pp_smumgr_func polaris10_smu_funcs;
extern const struct pp_smumgr_func vega10_smu_funcs;
-extern const struct pp_smumgr_func rv_smu_funcs;
+extern const struct pp_smumgr_func smu10_smu_funcs;
+
+extern int smu7_init_function_pointers(struct pp_hwmgr *hwmgr);
+extern int smu8_init_function_pointers(struct pp_hwmgr *hwmgr);
+extern int vega10_hwmgr_init(struct pp_hwmgr *hwmgr);
+extern int smu10_init_function_pointers(struct pp_hwmgr *hwmgr);
-extern int cz_init_function_pointers(struct pp_hwmgr *hwmgr);
static int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr);
static void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr);
static int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr);
@@ -55,35 +56,16 @@ static int tonga_set_asic_special_caps(struct pp_hwmgr *hwmgr);
static int topaz_set_asic_special_caps(struct pp_hwmgr *hwmgr);
static int ci_set_asic_special_caps(struct pp_hwmgr *hwmgr);
-uint8_t convert_to_vid(uint16_t vddc)
-{
- return (uint8_t) ((6200 - (vddc * VOLTAGE_SCALE)) / 25);
-}
-
-static int phm_get_pci_bus_devfn(struct pp_hwmgr *hwmgr,
- struct cgs_system_info *sys_info)
-{
- sys_info->size = sizeof(struct cgs_system_info);
- sys_info->info_id = CGS_SYSTEM_INFO_PCIE_BUS_DEVFN;
-
- return cgs_query_system_info(hwmgr->device, sys_info);
-}
-
static int phm_thermal_l2h_irq(void *private_data,
unsigned src_id, const uint32_t *iv_entry)
{
struct pp_hwmgr *hwmgr = (struct pp_hwmgr *)private_data;
- struct cgs_system_info sys_info = {0};
- int result;
-
- result = phm_get_pci_bus_devfn(hwmgr, &sys_info);
- if (result)
- return -EINVAL;
+ struct amdgpu_device *adev = hwmgr->adev;
- pr_warn("GPU over temperature range detected on PCIe %lld:%lld.%lld!\n",
- PCI_BUS_NUM(sys_info.value),
- PCI_SLOT(sys_info.value),
- PCI_FUNC(sys_info.value));
+ pr_warn("GPU over temperature range detected on PCIe %d:%d.%d!\n",
+ PCI_BUS_NUM(adev->pdev->devfn),
+ PCI_SLOT(adev->pdev->devfn),
+ PCI_FUNC(adev->pdev->devfn));
return 0;
}
@@ -91,17 +73,12 @@ static int phm_thermal_h2l_irq(void *private_data,
unsigned src_id, const uint32_t *iv_entry)
{
struct pp_hwmgr *hwmgr = (struct pp_hwmgr *)private_data;
- struct cgs_system_info sys_info = {0};
- int result;
+ struct amdgpu_device *adev = hwmgr->adev;
- result = phm_get_pci_bus_devfn(hwmgr, &sys_info);
- if (result)
- return -EINVAL;
-
- pr_warn("GPU under temperature range detected on PCIe %lld:%lld.%lld!\n",
- PCI_BUS_NUM(sys_info.value),
- PCI_SLOT(sys_info.value),
- PCI_FUNC(sys_info.value));
+ pr_warn("GPU under temperature range detected on PCIe %d:%d.%d!\n",
+ PCI_BUS_NUM(adev->pdev->devfn),
+ PCI_SLOT(adev->pdev->devfn),
+ PCI_FUNC(adev->pdev->devfn));
return 0;
}
@@ -109,17 +86,12 @@ static int phm_ctf_irq(void *private_data,
unsigned src_id, const uint32_t *iv_entry)
{
struct pp_hwmgr *hwmgr = (struct pp_hwmgr *)private_data;
- struct cgs_system_info sys_info = {0};
- int result;
-
- result = phm_get_pci_bus_devfn(hwmgr, &sys_info);
- if (result)
- return -EINVAL;
+ struct amdgpu_device *adev = hwmgr->adev;
- pr_warn("GPU Critical Temperature Fault detected on PCIe %lld:%lld.%lld!\n",
- PCI_BUS_NUM(sys_info.value),
- PCI_SLOT(sys_info.value),
- PCI_FUNC(sys_info.value));
+ pr_warn("GPU Critical Temperature Fault detected on PCIe %d:%d.%d!\n",
+ PCI_BUS_NUM(adev->pdev->devfn),
+ PCI_SLOT(adev->pdev->devfn),
+ PCI_FUNC(adev->pdev->devfn));
return 0;
}
@@ -129,22 +101,26 @@ static const struct cgs_irq_src_funcs thermal_irq_src[3] = {
{ .handler = phm_ctf_irq }
};
-int hwmgr_early_init(struct pp_instance *handle)
+static void hwmgr_init_workload_prority(struct pp_hwmgr *hwmgr)
{
- struct pp_hwmgr *hwmgr;
+ hwmgr->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 2;
+ hwmgr->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 0;
+ hwmgr->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 1;
+ hwmgr->workload_prority[PP_SMC_POWER_PROFILE_VR] = 3;
+ hwmgr->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 4;
- if (handle == NULL)
- return -EINVAL;
+ hwmgr->workload_setting[0] = PP_SMC_POWER_PROFILE_POWERSAVING;
+ hwmgr->workload_setting[1] = PP_SMC_POWER_PROFILE_VIDEO;
+ hwmgr->workload_setting[2] = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
+ hwmgr->workload_setting[3] = PP_SMC_POWER_PROFILE_VR;
+ hwmgr->workload_setting[4] = PP_SMC_POWER_PROFILE_COMPUTE;
+}
- hwmgr = kzalloc(sizeof(struct pp_hwmgr), GFP_KERNEL);
+int hwmgr_early_init(struct pp_hwmgr *hwmgr)
+{
if (hwmgr == NULL)
- return -ENOMEM;
+ return -EINVAL;
- handle->hwmgr = hwmgr;
- hwmgr->device = handle->device;
- hwmgr->chip_family = handle->chip_family;
- hwmgr->chip_id = handle->chip_id;
- hwmgr->feature_mask = handle->feature_mask;
hwmgr->usec_timeout = AMD_MAX_USEC_TIMEOUT;
hwmgr->power_source = PP_PowerSource_AC;
hwmgr->pp_table_version = PP_TABLE_V1;
@@ -154,6 +130,7 @@ int hwmgr_early_init(struct pp_instance *handle)
hwmgr_set_user_specify_caps(hwmgr);
hwmgr->fan_ctrl_is_in_default_mode = true;
hwmgr->reload_fw = 1;
+ hwmgr_init_workload_prority(hwmgr);
switch (hwmgr->chip_family) {
case AMDGPU_FAMILY_CI:
@@ -162,11 +139,13 @@ int hwmgr_early_init(struct pp_instance *handle)
hwmgr->feature_mask &= ~(PP_VBI_TIME_SUPPORT_MASK |
PP_ENABLE_GFX_CG_THRU_SMU);
hwmgr->pp_table_version = PP_TABLE_V0;
+ hwmgr->od_enabled = false;
smu7_init_function_pointers(hwmgr);
break;
case AMDGPU_FAMILY_CZ:
- hwmgr->smumgr_funcs = &cz_smu_funcs;
- cz_init_function_pointers(hwmgr);
+ hwmgr->od_enabled = false;
+ hwmgr->smumgr_funcs = &smu8_smu_funcs;
+ smu8_init_function_pointers(hwmgr);
break;
case AMDGPU_FAMILY_VI:
switch (hwmgr->chip_id) {
@@ -176,6 +155,7 @@ int hwmgr_early_init(struct pp_instance *handle)
hwmgr->feature_mask &= ~ (PP_VBI_TIME_SUPPORT_MASK |
PP_ENABLE_GFX_CG_THRU_SMU);
hwmgr->pp_table_version = PP_TABLE_V0;
+ hwmgr->od_enabled = false;
break;
case CHIP_TONGA:
hwmgr->smumgr_funcs = &tonga_smu_funcs;
@@ -213,8 +193,9 @@ int hwmgr_early_init(struct pp_instance *handle)
case AMDGPU_FAMILY_RV:
switch (hwmgr->chip_id) {
case CHIP_RAVEN:
- hwmgr->smumgr_funcs = &rv_smu_funcs;
- rv_init_function_pointers(hwmgr);
+ hwmgr->od_enabled = false;
+ hwmgr->smumgr_funcs = &smu10_smu_funcs;
+ smu10_init_function_pointers(hwmgr);
break;
default:
return -EINVAL;
@@ -227,16 +208,13 @@ int hwmgr_early_init(struct pp_instance *handle)
return 0;
}
-int hwmgr_hw_init(struct pp_instance *handle)
+int hwmgr_hw_init(struct pp_hwmgr *hwmgr)
{
- struct pp_hwmgr *hwmgr;
int ret = 0;
- if (handle == NULL)
+ if (hwmgr == NULL)
return -EINVAL;
- hwmgr = handle->hwmgr;
-
if (hwmgr->pptable_func == NULL ||
hwmgr->pptable_func->pptable_init == NULL ||
hwmgr->hwmgr_func->backend_init == NULL)
@@ -261,7 +239,7 @@ int hwmgr_hw_init(struct pp_instance *handle)
ret = phm_enable_dynamic_state_management(hwmgr);
if (ret)
goto err2;
- ret = phm_start_thermal_controller(hwmgr, NULL);
+ ret = phm_start_thermal_controller(hwmgr);
ret |= psm_set_performance_states(hwmgr);
if (ret)
goto err2;
@@ -282,15 +260,11 @@ err:
return ret;
}
-int hwmgr_hw_fini(struct pp_instance *handle)
+int hwmgr_hw_fini(struct pp_hwmgr *hwmgr)
{
- struct pp_hwmgr *hwmgr;
-
- if (handle == NULL || handle->hwmgr == NULL)
+ if (hwmgr == NULL)
return -EINVAL;
- hwmgr = handle->hwmgr;
-
phm_stop_thermal_controller(hwmgr);
psm_set_boot_states(hwmgr);
psm_adjust_power_state_dynamic(hwmgr, false, NULL);
@@ -304,15 +278,13 @@ int hwmgr_hw_fini(struct pp_instance *handle)
return psm_fini_power_state_table(hwmgr);
}
-int hwmgr_hw_suspend(struct pp_instance *handle)
+int hwmgr_hw_suspend(struct pp_hwmgr *hwmgr)
{
- struct pp_hwmgr *hwmgr;
int ret = 0;
- if (handle == NULL || handle->hwmgr == NULL)
+ if (hwmgr == NULL)
return -EINVAL;
- hwmgr = handle->hwmgr;
phm_disable_smc_firmware_ctf(hwmgr);
ret = psm_set_boot_states(hwmgr);
if (ret)
@@ -325,15 +297,13 @@ int hwmgr_hw_suspend(struct pp_instance *handle)
return ret;
}
-int hwmgr_hw_resume(struct pp_instance *handle)
+int hwmgr_hw_resume(struct pp_hwmgr *hwmgr)
{
- struct pp_hwmgr *hwmgr;
int ret = 0;
- if (handle == NULL || handle->hwmgr == NULL)
+ if (hwmgr == NULL)
return -EINVAL;
- hwmgr = handle->hwmgr;
ret = phm_setup_asic(hwmgr);
if (ret)
return ret;
@@ -341,7 +311,7 @@ int hwmgr_hw_resume(struct pp_instance *handle)
ret = phm_enable_dynamic_state_management(hwmgr);
if (ret)
return ret;
- ret = phm_start_thermal_controller(hwmgr, NULL);
+ ret = phm_start_thermal_controller(hwmgr);
if (ret)
return ret;
@@ -368,17 +338,14 @@ static enum PP_StateUILabel power_state_convert(enum amd_pm_state_type state)
}
}
-int hwmgr_handle_task(struct pp_instance *handle, enum amd_pp_task task_id,
- void *input, void *output)
+int hwmgr_handle_task(struct pp_hwmgr *hwmgr, enum amd_pp_task task_id,
+ enum amd_pm_state_type *user_state)
{
int ret = 0;
- struct pp_hwmgr *hwmgr;
- if (handle == NULL || handle->hwmgr == NULL)
+ if (hwmgr == NULL)
return -EINVAL;
- hwmgr = handle->hwmgr;
-
switch (task_id) {
case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE:
ret = phm_set_cpu_power_state(hwmgr);
@@ -391,17 +358,15 @@ int hwmgr_handle_task(struct pp_instance *handle, enum amd_pp_task task_id,
break;
case AMD_PP_TASK_ENABLE_USER_STATE:
{
- enum amd_pm_state_type ps;
enum PP_StateUILabel requested_ui_label;
struct pp_power_state *requested_ps = NULL;
- if (input == NULL) {
+ if (user_state == NULL) {
ret = -EINVAL;
break;
}
- ps = *(unsigned long *)input;
- requested_ui_label = power_state_convert(ps);
+ requested_ui_label = power_state_convert(*user_state);
ret = psm_set_user_performance_state(hwmgr, requested_ui_label, &requested_ps);
if (ret)
return ret;
@@ -417,468 +382,6 @@ int hwmgr_handle_task(struct pp_instance *handle, enum amd_pp_task task_id,
}
return ret;
}
-/**
- * Returns once the part of the register indicated by the mask has
- * reached the given value.
- */
-int phm_wait_on_register(struct pp_hwmgr *hwmgr, uint32_t index,
- uint32_t value, uint32_t mask)
-{
- uint32_t i;
- uint32_t cur_value;
-
- if (hwmgr == NULL || hwmgr->device == NULL) {
- pr_err("Invalid Hardware Manager!");
- return -EINVAL;
- }
-
- for (i = 0; i < hwmgr->usec_timeout; i++) {
- cur_value = cgs_read_register(hwmgr->device, index);
- if ((cur_value & mask) == (value & mask))
- break;
- udelay(1);
- }
-
- /* timeout means wrong logic*/
- if (i == hwmgr->usec_timeout)
- return -1;
- return 0;
-}
-
-
-/**
- * Returns once the part of the register indicated by the mask has
- * reached the given value.The indirect space is described by giving
- * the memory-mapped index of the indirect index register.
- */
-int phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr,
- uint32_t indirect_port,
- uint32_t index,
- uint32_t value,
- uint32_t mask)
-{
- if (hwmgr == NULL || hwmgr->device == NULL) {
- pr_err("Invalid Hardware Manager!");
- return -EINVAL;
- }
-
- cgs_write_register(hwmgr->device, indirect_port, index);
- return phm_wait_on_register(hwmgr, indirect_port + 1, mask, value);
-}
-
-int phm_wait_for_register_unequal(struct pp_hwmgr *hwmgr,
- uint32_t index,
- uint32_t value, uint32_t mask)
-{
- uint32_t i;
- uint32_t cur_value;
-
- if (hwmgr == NULL || hwmgr->device == NULL)
- return -EINVAL;
-
- for (i = 0; i < hwmgr->usec_timeout; i++) {
- cur_value = cgs_read_register(hwmgr->device,
- index);
- if ((cur_value & mask) != (value & mask))
- break;
- udelay(1);
- }
-
- /* timeout means wrong logic */
- if (i == hwmgr->usec_timeout)
- return -ETIME;
- return 0;
-}
-
-int phm_wait_for_indirect_register_unequal(struct pp_hwmgr *hwmgr,
- uint32_t indirect_port,
- uint32_t index,
- uint32_t value,
- uint32_t mask)
-{
- if (hwmgr == NULL || hwmgr->device == NULL)
- return -EINVAL;
-
- cgs_write_register(hwmgr->device, indirect_port, index);
- return phm_wait_for_register_unequal(hwmgr, indirect_port + 1,
- value, mask);
-}
-
-bool phm_cf_want_uvd_power_gating(struct pp_hwmgr *hwmgr)
-{
- return phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UVDPowerGating);
-}
-
-bool phm_cf_want_vce_power_gating(struct pp_hwmgr *hwmgr)
-{
- return phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VCEPowerGating);
-}
-
-
-int phm_trim_voltage_table(struct pp_atomctrl_voltage_table *vol_table)
-{
- uint32_t i, j;
- uint16_t vvalue;
- bool found = false;
- struct pp_atomctrl_voltage_table *table;
-
- PP_ASSERT_WITH_CODE((NULL != vol_table),
- "Voltage Table empty.", return -EINVAL);
-
- table = kzalloc(sizeof(struct pp_atomctrl_voltage_table),
- GFP_KERNEL);
-
- if (NULL == table)
- return -EINVAL;
-
- table->mask_low = vol_table->mask_low;
- table->phase_delay = vol_table->phase_delay;
-
- for (i = 0; i < vol_table->count; i++) {
- vvalue = vol_table->entries[i].value;
- found = false;
-
- for (j = 0; j < table->count; j++) {
- if (vvalue == table->entries[j].value) {
- found = true;
- break;
- }
- }
-
- if (!found) {
- table->entries[table->count].value = vvalue;
- table->entries[table->count].smio_low =
- vol_table->entries[i].smio_low;
- table->count++;
- }
- }
-
- memcpy(vol_table, table, sizeof(struct pp_atomctrl_voltage_table));
- kfree(table);
- table = NULL;
- return 0;
-}
-
-int phm_get_svi2_mvdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table,
- phm_ppt_v1_clock_voltage_dependency_table *dep_table)
-{
- uint32_t i;
- int result;
-
- PP_ASSERT_WITH_CODE((0 != dep_table->count),
- "Voltage Dependency Table empty.", return -EINVAL);
-
- PP_ASSERT_WITH_CODE((NULL != vol_table),
- "vol_table empty.", return -EINVAL);
-
- vol_table->mask_low = 0;
- vol_table->phase_delay = 0;
- vol_table->count = dep_table->count;
-
- for (i = 0; i < dep_table->count; i++) {
- vol_table->entries[i].value = dep_table->entries[i].mvdd;
- vol_table->entries[i].smio_low = 0;
- }
-
- result = phm_trim_voltage_table(vol_table);
- PP_ASSERT_WITH_CODE((0 == result),
- "Failed to trim MVDD table.", return result);
-
- return 0;
-}
-
-int phm_get_svi2_vddci_voltage_table(struct pp_atomctrl_voltage_table *vol_table,
- phm_ppt_v1_clock_voltage_dependency_table *dep_table)
-{
- uint32_t i;
- int result;
-
- PP_ASSERT_WITH_CODE((0 != dep_table->count),
- "Voltage Dependency Table empty.", return -EINVAL);
-
- PP_ASSERT_WITH_CODE((NULL != vol_table),
- "vol_table empty.", return -EINVAL);
-
- vol_table->mask_low = 0;
- vol_table->phase_delay = 0;
- vol_table->count = dep_table->count;
-
- for (i = 0; i < dep_table->count; i++) {
- vol_table->entries[i].value = dep_table->entries[i].vddci;
- vol_table->entries[i].smio_low = 0;
- }
-
- result = phm_trim_voltage_table(vol_table);
- PP_ASSERT_WITH_CODE((0 == result),
- "Failed to trim VDDCI table.", return result);
-
- return 0;
-}
-
-int phm_get_svi2_vdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table,
- phm_ppt_v1_voltage_lookup_table *lookup_table)
-{
- int i = 0;
-
- PP_ASSERT_WITH_CODE((0 != lookup_table->count),
- "Voltage Lookup Table empty.", return -EINVAL);
-
- PP_ASSERT_WITH_CODE((NULL != vol_table),
- "vol_table empty.", return -EINVAL);
-
- vol_table->mask_low = 0;
- vol_table->phase_delay = 0;
-
- vol_table->count = lookup_table->count;
-
- for (i = 0; i < vol_table->count; i++) {
- vol_table->entries[i].value = lookup_table->entries[i].us_vdd;
- vol_table->entries[i].smio_low = 0;
- }
-
- return 0;
-}
-
-void phm_trim_voltage_table_to_fit_state_table(uint32_t max_vol_steps,
- struct pp_atomctrl_voltage_table *vol_table)
-{
- unsigned int i, diff;
-
- if (vol_table->count <= max_vol_steps)
- return;
-
- diff = vol_table->count - max_vol_steps;
-
- for (i = 0; i < max_vol_steps; i++)
- vol_table->entries[i] = vol_table->entries[i + diff];
-
- vol_table->count = max_vol_steps;
-
- return;
-}
-
-int phm_reset_single_dpm_table(void *table,
- uint32_t count, int max)
-{
- int i;
-
- struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table;
-
- dpm_table->count = count > max ? max : count;
-
- for (i = 0; i < dpm_table->count; i++)
- dpm_table->dpm_level[i].enabled = false;
-
- return 0;
-}
-
-void phm_setup_pcie_table_entry(
- void *table,
- uint32_t index, uint32_t pcie_gen,
- uint32_t pcie_lanes)
-{
- struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table;
- dpm_table->dpm_level[index].value = pcie_gen;
- dpm_table->dpm_level[index].param1 = pcie_lanes;
- dpm_table->dpm_level[index].enabled = 1;
-}
-
-int32_t phm_get_dpm_level_enable_mask_value(void *table)
-{
- int32_t i;
- int32_t mask = 0;
- struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table;
-
- for (i = dpm_table->count; i > 0; i--) {
- mask = mask << 1;
- if (dpm_table->dpm_level[i - 1].enabled)
- mask |= 0x1;
- else
- mask &= 0xFFFFFFFE;
- }
-
- return mask;
-}
-
-uint8_t phm_get_voltage_index(
- struct phm_ppt_v1_voltage_lookup_table *lookup_table, uint16_t voltage)
-{
- uint8_t count = (uint8_t) (lookup_table->count);
- uint8_t i;
-
- PP_ASSERT_WITH_CODE((NULL != lookup_table),
- "Lookup Table empty.", return 0);
- PP_ASSERT_WITH_CODE((0 != count),
- "Lookup Table empty.", return 0);
-
- for (i = 0; i < lookup_table->count; i++) {
- /* find first voltage equal or bigger than requested */
- if (lookup_table->entries[i].us_vdd >= voltage)
- return i;
- }
- /* voltage is bigger than max voltage in the table */
- return i - 1;
-}
-
-uint8_t phm_get_voltage_id(pp_atomctrl_voltage_table *voltage_table,
- uint32_t voltage)
-{
- uint8_t count = (uint8_t) (voltage_table->count);
- uint8_t i = 0;
-
- PP_ASSERT_WITH_CODE((NULL != voltage_table),
- "Voltage Table empty.", return 0;);
- PP_ASSERT_WITH_CODE((0 != count),
- "Voltage Table empty.", return 0;);
-
- for (i = 0; i < count; i++) {
- /* find first voltage bigger than requested */
- if (voltage_table->entries[i].value >= voltage)
- return i;
- }
-
- /* voltage is bigger than max voltage in the table */
- return i - 1;
-}
-
-uint16_t phm_find_closest_vddci(struct pp_atomctrl_voltage_table *vddci_table, uint16_t vddci)
-{
- uint32_t i;
-
- for (i = 0; i < vddci_table->count; i++) {
- if (vddci_table->entries[i].value >= vddci)
- return vddci_table->entries[i].value;
- }
-
- pr_debug("vddci is larger than max value in vddci_table\n");
- return vddci_table->entries[i-1].value;
-}
-
-int phm_find_boot_level(void *table,
- uint32_t value, uint32_t *boot_level)
-{
- int result = -EINVAL;
- uint32_t i;
- struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table;
-
- for (i = 0; i < dpm_table->count; i++) {
- if (value == dpm_table->dpm_level[i].value) {
- *boot_level = i;
- result = 0;
- }
- }
-
- return result;
-}
-
-int phm_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr,
- phm_ppt_v1_voltage_lookup_table *lookup_table,
- uint16_t virtual_voltage_id, int32_t *sclk)
-{
- uint8_t entry_id;
- uint8_t voltage_id;
- struct phm_ppt_v1_information *table_info =
- (struct phm_ppt_v1_information *)(hwmgr->pptable);
-
- PP_ASSERT_WITH_CODE(lookup_table->count != 0, "Lookup table is empty", return -EINVAL);
-
- /* search for leakage voltage ID 0xff01 ~ 0xff08 and sckl */
- for (entry_id = 0; entry_id < table_info->vdd_dep_on_sclk->count; entry_id++) {
- voltage_id = table_info->vdd_dep_on_sclk->entries[entry_id].vddInd;
- if (lookup_table->entries[voltage_id].us_vdd == virtual_voltage_id)
- break;
- }
-
- if (entry_id >= table_info->vdd_dep_on_sclk->count) {
- pr_debug("Can't find requested voltage id in vdd_dep_on_sclk table\n");
- return -EINVAL;
- }
-
- *sclk = table_info->vdd_dep_on_sclk->entries[entry_id].clk;
-
- return 0;
-}
-
-/**
- * Initialize Dynamic State Adjustment Rule Settings
- *
- * @param hwmgr the address of the powerplay hardware manager.
- */
-int phm_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr)
-{
- uint32_t table_size;
- struct phm_clock_voltage_dependency_table *table_clk_vlt;
- struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
-
- /* initialize vddc_dep_on_dal_pwrl table */
- table_size = sizeof(uint32_t) + 4 * sizeof(struct phm_clock_voltage_dependency_record);
- table_clk_vlt = kzalloc(table_size, GFP_KERNEL);
-
- if (NULL == table_clk_vlt) {
- pr_err("Can not allocate space for vddc_dep_on_dal_pwrl! \n");
- return -ENOMEM;
- } else {
- table_clk_vlt->count = 4;
- table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_ULTRALOW;
- table_clk_vlt->entries[0].v = 0;
- table_clk_vlt->entries[1].clk = PP_DAL_POWERLEVEL_LOW;
- table_clk_vlt->entries[1].v = 720;
- table_clk_vlt->entries[2].clk = PP_DAL_POWERLEVEL_NOMINAL;
- table_clk_vlt->entries[2].v = 810;
- table_clk_vlt->entries[3].clk = PP_DAL_POWERLEVEL_PERFORMANCE;
- table_clk_vlt->entries[3].v = 900;
- if (pptable_info != NULL)
- pptable_info->vddc_dep_on_dal_pwrl = table_clk_vlt;
- hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt;
- }
-
- return 0;
-}
-
-uint32_t phm_get_lowest_enabled_level(struct pp_hwmgr *hwmgr, uint32_t mask)
-{
- uint32_t level = 0;
-
- while (0 == (mask & (1 << level)))
- level++;
-
- return level;
-}
-
-void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr)
-{
- struct phm_ppt_v1_information *table_info =
- (struct phm_ppt_v1_information *)hwmgr->pptable;
- struct phm_clock_voltage_dependency_table *table =
- table_info->vddc_dep_on_dal_pwrl;
- struct phm_ppt_v1_clock_voltage_dependency_table *vddc_table;
- enum PP_DAL_POWERLEVEL dal_power_level = hwmgr->dal_power_level;
- uint32_t req_vddc = 0, req_volt, i;
-
- if (!table || table->count <= 0
- || dal_power_level < PP_DAL_POWERLEVEL_ULTRALOW
- || dal_power_level > PP_DAL_POWERLEVEL_PERFORMANCE)
- return;
-
- for (i = 0; i < table->count; i++) {
- if (dal_power_level == table->entries[i].clk) {
- req_vddc = table->entries[i].v;
- break;
- }
- }
-
- vddc_table = table_info->vdd_dep_on_sclk;
- for (i = 0; i < vddc_table->count; i++) {
- if (req_vddc <= vddc_table->entries[i].vddc) {
- req_volt = (((uint32_t)vddc_table->entries[i].vddc) * VOLTAGE_SCALE);
- smum_send_msg_to_smc_with_parameter(hwmgr,
- PPSMC_MSG_VddC_Request, req_volt);
- return;
- }
- }
- pr_err("DAL requested level can not"
- " found a available voltage in VDDC DPM Table \n");
-}
void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr)
{
@@ -887,9 +390,10 @@ void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr)
phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UVDDPM);
phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VCEDPM);
- if (acpi_atcs_functions_supported(hwmgr->device, ATCS_FUNCTION_PCIE_PERFORMANCE_REQUEST) &&
- acpi_atcs_functions_supported(hwmgr->device, ATCS_FUNCTION_PCIE_DEVICE_READY_NOTIFICATION))
+#if defined(CONFIG_ACPI)
+ if (amdgpu_acpi_is_pcie_performance_request_supported(hwmgr->adev))
phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);
+#endif
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_DynamicPatchPowerState);
@@ -932,26 +436,10 @@ int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr)
PHM_PlatformCaps_CAC);
}
- return 0;
-}
+ if (hwmgr->feature_mask & PP_OVERDRIVE_MASK)
+ hwmgr->od_enabled = true;
-int phm_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
- uint32_t sclk, uint16_t id, uint16_t *voltage)
-{
- uint32_t vol;
- int ret = 0;
-
- if (hwmgr->chip_id < CHIP_TONGA) {
- ret = atomctrl_get_voltage_evv(hwmgr, id, voltage);
- } else if (hwmgr->chip_id < CHIP_POLARIS10) {
- ret = atomctrl_get_voltage_evv_on_sclk(hwmgr, voltage_type, sclk, id, voltage);
- if (*voltage >= 2000 || *voltage == 0)
- *voltage = 1150;
- } else {
- ret = atomctrl_get_voltage_evv_on_sclk_ai(hwmgr, voltage_type, sclk, id, &vol);
- *voltage = (uint16_t)(vol/100);
- }
- return ret;
+ return 0;
}
int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_acpi.c b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_acpi.c
deleted file mode 100644
index f6b4dd96c0ec..000000000000
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_acpi.c
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * Copyright 2016 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#include <linux/delay.h>
-#include <linux/errno.h>
-#include "hwmgr.h"
-#include "amd_acpi.h"
-#include "pp_acpi.h"
-
-bool acpi_atcs_functions_supported(void *device, uint32_t index)
-{
- int32_t result;
- struct atcs_verify_interface output_buf = {0};
-
- int32_t temp_buffer = 1;
-
- result = cgs_call_acpi_method(device, CGS_ACPI_METHOD_ATCS,
- ATCS_FUNCTION_VERIFY_INTERFACE,
- &temp_buffer,
- &output_buf,
- 1,
- sizeof(temp_buffer),
- sizeof(output_buf));
-
- return result == 0 ? (output_buf.function_bits & (1 << (index - 1))) != 0 : false;
-}
-
-bool acpi_atcs_notify_pcie_device_ready(void *device)
-{
- int32_t temp_buffer = 1;
-
- return cgs_call_acpi_method(device, CGS_ACPI_METHOD_ATCS,
- ATCS_FUNCTION_PCIE_DEVICE_READY_NOTIFICATION,
- &temp_buffer,
- NULL,
- 0,
- sizeof(temp_buffer),
- 0);
-}
-
-
-int acpi_pcie_perf_request(void *device, uint8_t perf_req, bool advertise)
-{
- struct atcs_pref_req_input atcs_input;
- struct atcs_pref_req_output atcs_output;
- u32 retry = 3;
- int result;
- struct cgs_system_info info = {0};
-
- if (acpi_atcs_notify_pcie_device_ready(device))
- return -EINVAL;
-
- info.size = sizeof(struct cgs_system_info);
- info.info_id = CGS_SYSTEM_INFO_ADAPTER_BDF_ID;
- result = cgs_query_system_info(device, &info);
- if (result != 0)
- return -EINVAL;
- atcs_input.client_id = (uint16_t)info.value;
- atcs_input.size = sizeof(struct atcs_pref_req_input);
- atcs_input.valid_flags_mask = ATCS_VALID_FLAGS_MASK;
- atcs_input.flags = ATCS_WAIT_FOR_COMPLETION;
- if (advertise)
- atcs_input.flags |= ATCS_ADVERTISE_CAPS;
- atcs_input.req_type = ATCS_PCIE_LINK_SPEED;
- atcs_input.perf_req = perf_req;
-
- atcs_output.size = sizeof(struct atcs_pref_req_input);
-
- while (retry--) {
- result = cgs_call_acpi_method(device,
- CGS_ACPI_METHOD_ATCS,
- ATCS_FUNCTION_PCIE_PERFORMANCE_REQUEST,
- &atcs_input,
- &atcs_output,
- 1,
- sizeof(atcs_input),
- sizeof(atcs_output));
- if (result != 0)
- return -EIO;
-
- switch (atcs_output.ret_val) {
- case ATCS_REQUEST_REFUSED:
- default:
- return -EINVAL;
- case ATCS_REQUEST_COMPLETE:
- return 0;
- case ATCS_REQUEST_IN_PROGRESS:
- udelay(10);
- break;
- }
- }
-
- return 0;
-}
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c
index 95ab772e0c3e..d0ef8f9c1361 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c
@@ -220,6 +220,8 @@ int psm_adjust_power_state_dynamic(struct pp_hwmgr *hwmgr, bool skip,
struct pp_power_state *pcurrent;
struct pp_power_state *requested;
bool equal;
+ uint32_t index;
+ long workload;
if (skip)
return 0;
@@ -247,7 +249,14 @@ int psm_adjust_power_state_dynamic(struct pp_hwmgr *hwmgr, bool skip,
if (!phm_force_dpm_levels(hwmgr, hwmgr->request_dpm_level))
hwmgr->dpm_level = hwmgr->request_dpm_level;
- phm_reset_power_profile_state(hwmgr);
+ if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
+ index = fls(hwmgr->workload_mask);
+ index = index > 0 && index <= Workload_Policy_Max ? index - 1 : 0;
+ workload = hwmgr->workload_setting[index];
+
+ if (hwmgr->power_profile_mode != workload && hwmgr->hwmgr_func->set_power_profile_mode)
+ hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, &workload, 0);
+ }
return 0;
}
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c b/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
index b49d65c3e984..c9eecce5683f 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
@@ -836,10 +836,10 @@ static int init_over_drive_limits(
hwmgr->platform_descriptor.maxOverdriveVDDC = 0;
hwmgr->platform_descriptor.overdriveVDDCStep = 0;
- if (hwmgr->platform_descriptor.overdriveLimit.engineClock > 0 \
- && hwmgr->platform_descriptor.overdriveLimit.memoryClock > 0) {
- phm_cap_set(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_ACOverdriveSupport);
+ if (hwmgr->platform_descriptor.overdriveLimit.engineClock == 0 \
+ || hwmgr->platform_descriptor.overdriveLimit.memoryClock == 0) {
+ hwmgr->od_enabled = false;
+ pr_debug("OverDrive feature not support by VBIOS\n");
}
return 0;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
index c3e7e34535e8..36ca7c419c90 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
@@ -1074,12 +1074,11 @@ static int init_overdrive_limits(struct pp_hwmgr *hwmgr,
powerplay_table,
(const ATOM_FIRMWARE_INFO_V2_1 *)fw_info);
- if (hwmgr->platform_descriptor.overdriveLimit.engineClock > 0
- && hwmgr->platform_descriptor.overdriveLimit.memoryClock > 0
- && !phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_OverdriveDisabledByPowerBudget))
- phm_cap_set(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_ACOverdriveSupport);
+ if (hwmgr->platform_descriptor.overdriveLimit.engineClock == 0
+ && hwmgr->platform_descriptor.overdriveLimit.memoryClock == 0) {
+ hwmgr->od_enabled = false;
+ pr_debug("OverDrive feature not support by VBIOS\n");
+ }
return result;
}
@@ -1697,9 +1696,6 @@ static int pp_tables_uninitialize(struct pp_hwmgr *hwmgr)
kfree(hwmgr->dyn_state.vdd_gfx_dependency_on_sclk);
hwmgr->dyn_state.vdd_gfx_dependency_on_sclk = NULL;
- kfree(hwmgr->dyn_state.vq_budgeting_table);
- hwmgr->dyn_state.vq_budgeting_table = NULL;
-
return 0;
}
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
index 569073e3a5a1..10253b89b3d8 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
@@ -32,53 +32,52 @@
#include "hwmgr.h"
#include "hardwaremanager.h"
#include "rv_ppsmc.h"
-#include "rv_hwmgr.h"
+#include "smu10_hwmgr.h"
#include "power_state.h"
-#include "rv_smumgr.h"
#include "pp_soc15.h"
-#define RAVEN_MAX_DEEPSLEEP_DIVIDER_ID 5
-#define RAVEN_MINIMUM_ENGINE_CLOCK 800 /* 8Mhz, the low boundary of engine clock allowed on this chip */
+#define SMU10_MAX_DEEPSLEEP_DIVIDER_ID 5
+#define SMU10_MINIMUM_ENGINE_CLOCK 800 /* 8Mhz, the low boundary of engine clock allowed on this chip */
#define SCLK_MIN_DIV_INTV_SHIFT 12
-#define RAVEN_DISPCLK_BYPASS_THRESHOLD 10000 /* 100Mhz */
+#define SMU10_DISPCLK_BYPASS_THRESHOLD 10000 /* 100Mhz */
#define SMC_RAM_END 0x40000
-static const unsigned long PhwRaven_Magic = (unsigned long) PHM_Rv_Magic;
+static const unsigned long SMU10_Magic = (unsigned long) PHM_Rv_Magic;
-int rv_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
+static int smu10_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
struct pp_display_clock_request *clock_req);
-static struct rv_power_state *cast_rv_ps(struct pp_hw_power_state *hw_ps)
+static struct smu10_power_state *cast_smu10_ps(struct pp_hw_power_state *hw_ps)
{
- if (PhwRaven_Magic != hw_ps->magic)
+ if (SMU10_Magic != hw_ps->magic)
return NULL;
- return (struct rv_power_state *)hw_ps;
+ return (struct smu10_power_state *)hw_ps;
}
-static const struct rv_power_state *cast_const_rv_ps(
+static const struct smu10_power_state *cast_const_smu10_ps(
const struct pp_hw_power_state *hw_ps)
{
- if (PhwRaven_Magic != hw_ps->magic)
+ if (SMU10_Magic != hw_ps->magic)
return NULL;
- return (struct rv_power_state *)hw_ps;
+ return (struct smu10_power_state *)hw_ps;
}
-static int rv_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
+static int smu10_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
{
- struct rv_hwmgr *rv_hwmgr = (struct rv_hwmgr *)(hwmgr->backend);
+ struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
- rv_hwmgr->dce_slow_sclk_threshold = 30000;
- rv_hwmgr->thermal_auto_throttling_treshold = 0;
- rv_hwmgr->is_nb_dpm_enabled = 1;
- rv_hwmgr->dpm_flags = 1;
- rv_hwmgr->gfx_off_controled_by_driver = false;
- rv_hwmgr->need_min_deep_sleep_dcefclk = true;
- rv_hwmgr->num_active_display = 0;
- rv_hwmgr->deep_sleep_dcefclk = 0;
+ smu10_data->dce_slow_sclk_threshold = 30000;
+ smu10_data->thermal_auto_throttling_treshold = 0;
+ smu10_data->is_nb_dpm_enabled = 1;
+ smu10_data->dpm_flags = 1;
+ smu10_data->gfx_off_controled_by_driver = false;
+ smu10_data->need_min_deep_sleep_dcefclk = true;
+ smu10_data->num_active_display = 0;
+ smu10_data->deep_sleep_dcefclk = 0;
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SclkDeepSleep);
@@ -91,13 +90,13 @@ static int rv_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
return 0;
}
-static int rv_construct_max_power_limits_table(struct pp_hwmgr *hwmgr,
+static int smu10_construct_max_power_limits_table(struct pp_hwmgr *hwmgr,
struct phm_clock_and_voltage_limits *table)
{
return 0;
}
-static int rv_init_dynamic_state_adjustment_rule_settings(
+static int smu10_init_dynamic_state_adjustment_rule_settings(
struct pp_hwmgr *hwmgr)
{
uint32_t table_size =
@@ -134,30 +133,30 @@ static int rv_init_dynamic_state_adjustment_rule_settings(
return 0;
}
-static int rv_get_system_info_data(struct pp_hwmgr *hwmgr)
+static int smu10_get_system_info_data(struct pp_hwmgr *hwmgr)
{
- struct rv_hwmgr *rv_data = (struct rv_hwmgr *)hwmgr->backend;
+ struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)hwmgr->backend;
- rv_data->sys_info.htc_hyst_lmt = 5;
- rv_data->sys_info.htc_tmp_lmt = 203;
+ smu10_data->sys_info.htc_hyst_lmt = 5;
+ smu10_data->sys_info.htc_tmp_lmt = 203;
- if (rv_data->thermal_auto_throttling_treshold == 0)
- rv_data->thermal_auto_throttling_treshold = 203;
+ if (smu10_data->thermal_auto_throttling_treshold == 0)
+ smu10_data->thermal_auto_throttling_treshold = 203;
- rv_construct_max_power_limits_table (hwmgr,
+ smu10_construct_max_power_limits_table (hwmgr,
&hwmgr->dyn_state.max_clock_voltage_on_ac);
- rv_init_dynamic_state_adjustment_rule_settings(hwmgr);
+ smu10_init_dynamic_state_adjustment_rule_settings(hwmgr);
return 0;
}
-static int rv_construct_boot_state(struct pp_hwmgr *hwmgr)
+static int smu10_construct_boot_state(struct pp_hwmgr *hwmgr)
{
return 0;
}
-static int rv_set_clock_limit(struct pp_hwmgr *hwmgr, const void *input)
+static int smu10_set_clock_limit(struct pp_hwmgr *hwmgr, const void *input)
{
struct PP_Clocks clocks = {0};
struct pp_display_clock_request clock_req;
@@ -166,111 +165,109 @@ static int rv_set_clock_limit(struct pp_hwmgr *hwmgr, const void *input)
clock_req.clock_type = amd_pp_dcf_clock;
clock_req.clock_freq_in_khz = clocks.dcefClock * 10;
- PP_ASSERT_WITH_CODE(!rv_display_clock_voltage_request(hwmgr, &clock_req),
+ PP_ASSERT_WITH_CODE(!smu10_display_clock_voltage_request(hwmgr, &clock_req),
"Attempt to set DCF Clock Failed!", return -EINVAL);
return 0;
}
-static int rv_set_deep_sleep_dcefclk(struct pp_hwmgr *hwmgr, uint32_t clock)
+static int smu10_set_deep_sleep_dcefclk(struct pp_hwmgr *hwmgr, uint32_t clock)
{
- struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
+ struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
- if (rv_data->need_min_deep_sleep_dcefclk && rv_data->deep_sleep_dcefclk != clock/100) {
- rv_data->deep_sleep_dcefclk = clock/100;
+ if (smu10_data->need_min_deep_sleep_dcefclk && smu10_data->deep_sleep_dcefclk != clock/100) {
+ smu10_data->deep_sleep_dcefclk = clock/100;
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetMinDeepSleepDcefclk,
- rv_data->deep_sleep_dcefclk);
+ smu10_data->deep_sleep_dcefclk);
}
return 0;
}
-static int rv_set_active_display_count(struct pp_hwmgr *hwmgr, uint32_t count)
+static int smu10_set_active_display_count(struct pp_hwmgr *hwmgr, uint32_t count)
{
- struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
+ struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
- if (rv_data->num_active_display != count) {
- rv_data->num_active_display = count;
+ if (smu10_data->num_active_display != count) {
+ smu10_data->num_active_display = count;
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetDisplayCount,
- rv_data->num_active_display);
+ smu10_data->num_active_display);
}
return 0;
}
-static int rv_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
+static int smu10_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
{
- return rv_set_clock_limit(hwmgr, input);
+ return smu10_set_clock_limit(hwmgr, input);
}
-static int rv_init_power_gate_state(struct pp_hwmgr *hwmgr)
+static int smu10_init_power_gate_state(struct pp_hwmgr *hwmgr)
{
- struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
+ struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
- rv_data->vcn_power_gated = true;
- rv_data->isp_tileA_power_gated = true;
- rv_data->isp_tileB_power_gated = true;
+ smu10_data->vcn_power_gated = true;
+ smu10_data->isp_tileA_power_gated = true;
+ smu10_data->isp_tileB_power_gated = true;
return 0;
}
-static int rv_setup_asic_task(struct pp_hwmgr *hwmgr)
+static int smu10_setup_asic_task(struct pp_hwmgr *hwmgr)
{
- return rv_init_power_gate_state(hwmgr);
+ return smu10_init_power_gate_state(hwmgr);
}
-static int rv_reset_cc6_data(struct pp_hwmgr *hwmgr)
+static int smu10_reset_cc6_data(struct pp_hwmgr *hwmgr)
{
- struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
+ struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
- rv_data->separation_time = 0;
- rv_data->cc6_disable = false;
- rv_data->pstate_disable = false;
- rv_data->cc6_setting_changed = false;
+ smu10_data->separation_time = 0;
+ smu10_data->cc6_disable = false;
+ smu10_data->pstate_disable = false;
+ smu10_data->cc6_setting_changed = false;
return 0;
}
-static int rv_power_off_asic(struct pp_hwmgr *hwmgr)
+static int smu10_power_off_asic(struct pp_hwmgr *hwmgr)
{
- return rv_reset_cc6_data(hwmgr);
+ return smu10_reset_cc6_data(hwmgr);
}
-static int rv_disable_gfx_off(struct pp_hwmgr *hwmgr)
+static int smu10_disable_gfx_off(struct pp_hwmgr *hwmgr)
{
- struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
+ struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
- if (rv_data->gfx_off_controled_by_driver)
- smum_send_msg_to_smc(hwmgr,
- PPSMC_MSG_DisableGfxOff);
+ if (smu10_data->gfx_off_controled_by_driver)
+ smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableGfxOff);
return 0;
}
-static int rv_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
+static int smu10_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
{
- return rv_disable_gfx_off(hwmgr);
+ return smu10_disable_gfx_off(hwmgr);
}
-static int rv_enable_gfx_off(struct pp_hwmgr *hwmgr)
+static int smu10_enable_gfx_off(struct pp_hwmgr *hwmgr)
{
- struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
+ struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
- if (rv_data->gfx_off_controled_by_driver)
- smum_send_msg_to_smc(hwmgr,
- PPSMC_MSG_EnableGfxOff);
+ if (smu10_data->gfx_off_controled_by_driver)
+ smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableGfxOff);
return 0;
}
-static int rv_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
+static int smu10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
{
- return rv_enable_gfx_off(hwmgr);
+ return smu10_enable_gfx_off(hwmgr);
}
-static int rv_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
+static int smu10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
struct pp_power_state *prequest_ps,
const struct pp_power_state *pcurrent_ps)
{
@@ -314,14 +311,14 @@ static const DpmClock_t VddPhyClk[]= {
{ 810, 3600},
};
-static int rv_get_clock_voltage_dependency_table(struct pp_hwmgr *hwmgr,
- struct rv_voltage_dependency_table **pptable,
+static int smu10_get_clock_voltage_dependency_table(struct pp_hwmgr *hwmgr,
+ struct smu10_voltage_dependency_table **pptable,
uint32_t num_entry, const DpmClock_t *pclk_dependency_table)
{
uint32_t table_size, i;
- struct rv_voltage_dependency_table *ptable;
+ struct smu10_voltage_dependency_table *ptable;
- table_size = sizeof(uint32_t) + sizeof(struct rv_voltage_dependency_table) * num_entry;
+ table_size = sizeof(uint32_t) + sizeof(struct smu10_voltage_dependency_table) * num_entry;
ptable = kzalloc(table_size, GFP_KERNEL);
if (NULL == ptable)
@@ -341,107 +338,95 @@ static int rv_get_clock_voltage_dependency_table(struct pp_hwmgr *hwmgr,
}
-static int rv_populate_clock_table(struct pp_hwmgr *hwmgr)
+static int smu10_populate_clock_table(struct pp_hwmgr *hwmgr)
{
int result;
- struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
- DpmClocks_t *table = &(rv_data->clock_table);
- struct rv_clock_voltage_information *pinfo = &(rv_data->clock_vol_info);
+ struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
+ DpmClocks_t *table = &(smu10_data->clock_table);
+ struct smu10_clock_voltage_information *pinfo = &(smu10_data->clock_vol_info);
- result = rv_copy_table_from_smc(hwmgr, (uint8_t *)table, CLOCKTABLE);
+ result = smum_smc_table_manager(hwmgr, (uint8_t *)table, SMU10_CLOCKTABLE, true);
PP_ASSERT_WITH_CODE((0 == result),
"Attempt to copy clock table from smc failed",
return result);
if (0 == result && table->DcefClocks[0].Freq != 0) {
- rv_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dcefclk,
+ smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dcefclk,
NUM_DCEFCLK_DPM_LEVELS,
- &rv_data->clock_table.DcefClocks[0]);
- rv_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_socclk,
+ &smu10_data->clock_table.DcefClocks[0]);
+ smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_socclk,
NUM_SOCCLK_DPM_LEVELS,
- &rv_data->clock_table.SocClocks[0]);
- rv_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_fclk,
+ &smu10_data->clock_table.SocClocks[0]);
+ smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_fclk,
NUM_FCLK_DPM_LEVELS,
- &rv_data->clock_table.FClocks[0]);
- rv_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_mclk,
+ &smu10_data->clock_table.FClocks[0]);
+ smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_mclk,
NUM_MEMCLK_DPM_LEVELS,
- &rv_data->clock_table.MemClocks[0]);
+ &smu10_data->clock_table.MemClocks[0]);
} else {
- rv_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dcefclk,
+ smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dcefclk,
ARRAY_SIZE(VddDcfClk),
&VddDcfClk[0]);
- rv_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_socclk,
+ smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_socclk,
ARRAY_SIZE(VddSocClk),
&VddSocClk[0]);
- rv_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_fclk,
+ smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_fclk,
ARRAY_SIZE(VddFClk),
&VddFClk[0]);
}
- rv_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dispclk,
+ smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dispclk,
ARRAY_SIZE(VddDispClk),
&VddDispClk[0]);
- rv_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dppclk,
+ smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dppclk,
ARRAY_SIZE(VddDppClk), &VddDppClk[0]);
- rv_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_phyclk,
+ smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_phyclk,
ARRAY_SIZE(VddPhyClk), &VddPhyClk[0]);
- PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
- PPSMC_MSG_GetMinGfxclkFrequency),
- "Attempt to get min GFXCLK Failed!",
- return -1);
- PP_ASSERT_WITH_CODE(!rv_read_arg_from_smc(hwmgr,
- &result),
- "Attempt to get min GFXCLK Failed!",
- return -1);
- rv_data->gfx_min_freq_limit = result * 100;
-
- PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
- PPSMC_MSG_GetMaxGfxclkFrequency),
- "Attempt to get max GFXCLK Failed!",
- return -1);
- PP_ASSERT_WITH_CODE(!rv_read_arg_from_smc(hwmgr,
- &result),
- "Attempt to get max GFXCLK Failed!",
- return -1);
- rv_data->gfx_max_freq_limit = result * 100;
+ smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency);
+ result = smum_get_argument(hwmgr);
+ smu10_data->gfx_min_freq_limit = result * 100;
+
+ smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency);
+ result = smum_get_argument(hwmgr);
+ smu10_data->gfx_max_freq_limit = result * 100;
return 0;
}
-static int rv_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
+static int smu10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
{
int result = 0;
- struct rv_hwmgr *data;
+ struct smu10_hwmgr *data;
- data = kzalloc(sizeof(struct rv_hwmgr), GFP_KERNEL);
+ data = kzalloc(sizeof(struct smu10_hwmgr), GFP_KERNEL);
if (data == NULL)
return -ENOMEM;
hwmgr->backend = data;
- result = rv_initialize_dpm_defaults(hwmgr);
+ result = smu10_initialize_dpm_defaults(hwmgr);
if (result != 0) {
- pr_err("rv_initialize_dpm_defaults failed\n");
+ pr_err("smu10_initialize_dpm_defaults failed\n");
return result;
}
- rv_populate_clock_table(hwmgr);
+ smu10_populate_clock_table(hwmgr);
- result = rv_get_system_info_data(hwmgr);
+ result = smu10_get_system_info_data(hwmgr);
if (result != 0) {
- pr_err("rv_get_system_info_data failed\n");
+ pr_err("smu10_get_system_info_data failed\n");
return result;
}
- rv_construct_boot_state(hwmgr);
+ smu10_construct_boot_state(hwmgr);
hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
- RAVEN_MAX_HARDWARE_POWERLEVELS;
+ SMU10_MAX_HARDWARE_POWERLEVELS;
hwmgr->platform_descriptor.hardwarePerformanceLevels =
- RAVEN_MAX_HARDWARE_POWERLEVELS;
+ SMU10_MAX_HARDWARE_POWERLEVELS;
hwmgr->platform_descriptor.vbiosInterruptId = 0;
@@ -451,13 +436,16 @@ static int rv_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
+ hwmgr->pstate_sclk = SMU10_UMD_PSTATE_GFXCLK;
+ hwmgr->pstate_mclk = SMU10_UMD_PSTATE_FCLK;
+
return result;
}
-static int rv_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
+static int smu10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
{
- struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
- struct rv_clock_voltage_information *pinfo = &(rv_data->clock_vol_info);
+ struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
+ struct smu10_clock_voltage_information *pinfo = &(smu10_data->clock_vol_info);
kfree(pinfo->vdd_dep_on_dcefclk);
pinfo->vdd_dep_on_dcefclk = NULL;
@@ -481,7 +469,7 @@ static int rv_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
return 0;
}
-static int rv_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
+static int smu10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
enum amd_dpm_forced_level level)
{
if (hwmgr->smu_version < 0x1E3700) {
@@ -494,113 +482,113 @@ static int rv_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetHardMinGfxClk,
- RAVEN_UMD_PSTATE_PEAK_GFXCLK);
+ SMU10_UMD_PSTATE_PEAK_GFXCLK);
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetHardMinFclkByFreq,
- RAVEN_UMD_PSTATE_PEAK_FCLK);
+ SMU10_UMD_PSTATE_PEAK_FCLK);
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetHardMinSocclkByFreq,
- RAVEN_UMD_PSTATE_PEAK_SOCCLK);
+ SMU10_UMD_PSTATE_PEAK_SOCCLK);
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetHardMinVcn,
- RAVEN_UMD_PSTATE_VCE);
+ SMU10_UMD_PSTATE_VCE);
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSoftMaxGfxClk,
- RAVEN_UMD_PSTATE_PEAK_GFXCLK);
+ SMU10_UMD_PSTATE_PEAK_GFXCLK);
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSoftMaxFclkByFreq,
- RAVEN_UMD_PSTATE_PEAK_FCLK);
+ SMU10_UMD_PSTATE_PEAK_FCLK);
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSoftMaxSocclkByFreq,
- RAVEN_UMD_PSTATE_PEAK_SOCCLK);
+ SMU10_UMD_PSTATE_PEAK_SOCCLK);
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSoftMaxVcn,
- RAVEN_UMD_PSTATE_VCE);
+ SMU10_UMD_PSTATE_VCE);
break;
case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetHardMinGfxClk,
- RAVEN_UMD_PSTATE_MIN_GFXCLK);
+ SMU10_UMD_PSTATE_MIN_GFXCLK);
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSoftMaxGfxClk,
- RAVEN_UMD_PSTATE_MIN_GFXCLK);
+ SMU10_UMD_PSTATE_MIN_GFXCLK);
break;
case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetHardMinFclkByFreq,
- RAVEN_UMD_PSTATE_MIN_FCLK);
+ SMU10_UMD_PSTATE_MIN_FCLK);
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSoftMaxFclkByFreq,
- RAVEN_UMD_PSTATE_MIN_FCLK);
+ SMU10_UMD_PSTATE_MIN_FCLK);
break;
case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetHardMinGfxClk,
- RAVEN_UMD_PSTATE_GFXCLK);
+ SMU10_UMD_PSTATE_GFXCLK);
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetHardMinFclkByFreq,
- RAVEN_UMD_PSTATE_FCLK);
+ SMU10_UMD_PSTATE_FCLK);
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetHardMinSocclkByFreq,
- RAVEN_UMD_PSTATE_SOCCLK);
+ SMU10_UMD_PSTATE_SOCCLK);
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetHardMinVcn,
- RAVEN_UMD_PSTATE_VCE);
+ SMU10_UMD_PSTATE_VCE);
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSoftMaxGfxClk,
- RAVEN_UMD_PSTATE_GFXCLK);
+ SMU10_UMD_PSTATE_GFXCLK);
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSoftMaxFclkByFreq,
- RAVEN_UMD_PSTATE_FCLK);
+ SMU10_UMD_PSTATE_FCLK);
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSoftMaxSocclkByFreq,
- RAVEN_UMD_PSTATE_SOCCLK);
+ SMU10_UMD_PSTATE_SOCCLK);
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSoftMaxVcn,
- RAVEN_UMD_PSTATE_VCE);
+ SMU10_UMD_PSTATE_VCE);
break;
case AMD_DPM_FORCED_LEVEL_AUTO:
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetHardMinGfxClk,
- RAVEN_UMD_PSTATE_MIN_GFXCLK);
+ SMU10_UMD_PSTATE_MIN_GFXCLK);
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetHardMinFclkByFreq,
- RAVEN_UMD_PSTATE_MIN_FCLK);
+ SMU10_UMD_PSTATE_MIN_FCLK);
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetHardMinSocclkByFreq,
- RAVEN_UMD_PSTATE_MIN_SOCCLK);
+ SMU10_UMD_PSTATE_MIN_SOCCLK);
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetHardMinVcn,
- RAVEN_UMD_PSTATE_MIN_VCE);
+ SMU10_UMD_PSTATE_MIN_VCE);
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSoftMaxGfxClk,
- RAVEN_UMD_PSTATE_PEAK_GFXCLK);
+ SMU10_UMD_PSTATE_PEAK_GFXCLK);
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSoftMaxFclkByFreq,
- RAVEN_UMD_PSTATE_PEAK_FCLK);
+ SMU10_UMD_PSTATE_PEAK_FCLK);
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSoftMaxSocclkByFreq,
- RAVEN_UMD_PSTATE_PEAK_SOCCLK);
+ SMU10_UMD_PSTATE_PEAK_SOCCLK);
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSoftMaxVcn,
- RAVEN_UMD_PSTATE_VCE);
+ SMU10_UMD_PSTATE_VCE);
break;
case AMD_DPM_FORCED_LEVEL_LOW:
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetHardMinGfxClk,
- RAVEN_UMD_PSTATE_MIN_GFXCLK);
+ SMU10_UMD_PSTATE_MIN_GFXCLK);
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSoftMaxGfxClk,
- RAVEN_UMD_PSTATE_MIN_GFXCLK);
+ SMU10_UMD_PSTATE_MIN_GFXCLK);
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetHardMinFclkByFreq,
- RAVEN_UMD_PSTATE_MIN_FCLK);
+ SMU10_UMD_PSTATE_MIN_FCLK);
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSoftMaxFclkByFreq,
- RAVEN_UMD_PSTATE_MIN_FCLK);
+ SMU10_UMD_PSTATE_MIN_FCLK);
break;
case AMD_DPM_FORCED_LEVEL_MANUAL:
case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
@@ -610,14 +598,14 @@ static int rv_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
return 0;
}
-static uint32_t rv_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
+static uint32_t smu10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
{
- struct rv_hwmgr *data;
+ struct smu10_hwmgr *data;
if (hwmgr == NULL)
return -EINVAL;
- data = (struct rv_hwmgr *)(hwmgr->backend);
+ data = (struct smu10_hwmgr *)(hwmgr->backend);
if (low)
return data->clock_vol_info.vdd_dep_on_fclk->entries[0].clk;
@@ -626,14 +614,14 @@ static uint32_t rv_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
data->clock_vol_info.vdd_dep_on_fclk->count - 1].clk;
}
-static uint32_t rv_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
+static uint32_t smu10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
{
- struct rv_hwmgr *data;
+ struct smu10_hwmgr *data;
if (hwmgr == NULL)
return -EINVAL;
- data = (struct rv_hwmgr *)(hwmgr->backend);
+ data = (struct smu10_hwmgr *)(hwmgr->backend);
if (low)
return data->gfx_min_freq_limit;
@@ -641,34 +629,34 @@ static uint32_t rv_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
return data->gfx_max_freq_limit;
}
-static int rv_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
+static int smu10_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
struct pp_hw_power_state *hw_ps)
{
return 0;
}
-static int rv_dpm_get_pp_table_entry_callback(
+static int smu10_dpm_get_pp_table_entry_callback(
struct pp_hwmgr *hwmgr,
struct pp_hw_power_state *hw_ps,
unsigned int index,
const void *clock_info)
{
- struct rv_power_state *rv_ps = cast_rv_ps(hw_ps);
+ struct smu10_power_state *smu10_ps = cast_smu10_ps(hw_ps);
- rv_ps->levels[index].engine_clock = 0;
+ smu10_ps->levels[index].engine_clock = 0;
- rv_ps->levels[index].vddc_index = 0;
- rv_ps->level = index + 1;
+ smu10_ps->levels[index].vddc_index = 0;
+ smu10_ps->level = index + 1;
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
- rv_ps->levels[index].ds_divider_index = 5;
- rv_ps->levels[index].ss_divider_index = 5;
+ smu10_ps->levels[index].ds_divider_index = 5;
+ smu10_ps->levels[index].ss_divider_index = 5;
}
return 0;
}
-static int rv_dpm_get_num_of_pp_table_entries(struct pp_hwmgr *hwmgr)
+static int smu10_dpm_get_num_of_pp_table_entries(struct pp_hwmgr *hwmgr)
{
int result;
unsigned long ret = 0;
@@ -678,72 +666,66 @@ static int rv_dpm_get_num_of_pp_table_entries(struct pp_hwmgr *hwmgr)
return result ? 0 : ret;
}
-static int rv_dpm_get_pp_table_entry(struct pp_hwmgr *hwmgr,
+static int smu10_dpm_get_pp_table_entry(struct pp_hwmgr *hwmgr,
unsigned long entry, struct pp_power_state *ps)
{
int result;
- struct rv_power_state *rv_ps;
+ struct smu10_power_state *smu10_ps;
- ps->hardware.magic = PhwRaven_Magic;
+ ps->hardware.magic = SMU10_Magic;
- rv_ps = cast_rv_ps(&(ps->hardware));
+ smu10_ps = cast_smu10_ps(&(ps->hardware));
result = pp_tables_get_entry(hwmgr, entry, ps,
- rv_dpm_get_pp_table_entry_callback);
+ smu10_dpm_get_pp_table_entry_callback);
- rv_ps->uvd_clocks.vclk = ps->uvd_clocks.VCLK;
- rv_ps->uvd_clocks.dclk = ps->uvd_clocks.DCLK;
+ smu10_ps->uvd_clocks.vclk = ps->uvd_clocks.VCLK;
+ smu10_ps->uvd_clocks.dclk = ps->uvd_clocks.DCLK;
return result;
}
-static int rv_get_power_state_size(struct pp_hwmgr *hwmgr)
+static int smu10_get_power_state_size(struct pp_hwmgr *hwmgr)
{
- return sizeof(struct rv_power_state);
+ return sizeof(struct smu10_power_state);
}
-static int rv_set_cpu_power_state(struct pp_hwmgr *hwmgr)
+static int smu10_set_cpu_power_state(struct pp_hwmgr *hwmgr)
{
return 0;
}
-static int rv_store_cc6_data(struct pp_hwmgr *hwmgr, uint32_t separation_time,
+static int smu10_store_cc6_data(struct pp_hwmgr *hwmgr, uint32_t separation_time,
bool cc6_disable, bool pstate_disable, bool pstate_switch_disable)
{
return 0;
}
-static int rv_get_dal_power_level(struct pp_hwmgr *hwmgr,
+static int smu10_get_dal_power_level(struct pp_hwmgr *hwmgr,
struct amd_pp_simple_clock_info *info)
{
return -EINVAL;
}
-static int rv_force_clock_level(struct pp_hwmgr *hwmgr,
+static int smu10_force_clock_level(struct pp_hwmgr *hwmgr,
enum pp_clock_type type, uint32_t mask)
{
return 0;
}
-static int rv_print_clock_levels(struct pp_hwmgr *hwmgr,
+static int smu10_print_clock_levels(struct pp_hwmgr *hwmgr,
enum pp_clock_type type, char *buf)
{
- struct rv_hwmgr *data = (struct rv_hwmgr *)(hwmgr->backend);
- struct rv_voltage_dependency_table *mclk_table =
+ struct smu10_hwmgr *data = (struct smu10_hwmgr *)(hwmgr->backend);
+ struct smu10_voltage_dependency_table *mclk_table =
data->clock_vol_info.vdd_dep_on_fclk;
int i, now, size = 0;
switch (type) {
case PP_SCLK:
- PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
- PPSMC_MSG_GetGfxclkFrequency),
- "Attempt to get current GFXCLK Failed!",
- return -1);
- PP_ASSERT_WITH_CODE(!rv_read_arg_from_smc(hwmgr,
- &now),
- "Attempt to get current GFXCLK Failed!",
- return -1);
+ smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetGfxclkFrequency);
+ now = smum_get_argument(hwmgr);
size += sprintf(buf + size, "0: %uMhz %s\n",
data->gfx_min_freq_limit / 100,
@@ -755,14 +737,8 @@ static int rv_print_clock_levels(struct pp_hwmgr *hwmgr,
== now) ? "*" : "");
break;
case PP_MCLK:
- PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
- PPSMC_MSG_GetFclkFrequency),
- "Attempt to get current MEMCLK Failed!",
- return -1);
- PP_ASSERT_WITH_CODE(!rv_read_arg_from_smc(hwmgr,
- &now),
- "Attempt to get current MEMCLK Failed!",
- return -1);
+ smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetFclkFrequency);
+ now = smum_get_argument(hwmgr);
for (i = 0; i < mclk_table->count; i++)
size += sprintf(buf + size, "%d: %uMhz %s\n",
@@ -778,16 +754,16 @@ static int rv_print_clock_levels(struct pp_hwmgr *hwmgr,
return size;
}
-static int rv_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
+static int smu10_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
PHM_PerformanceLevelDesignation designation, uint32_t index,
PHM_PerformanceLevel *level)
{
- struct rv_hwmgr *data;
+ struct smu10_hwmgr *data;
if (level == NULL || hwmgr == NULL || state == NULL)
return -EINVAL;
- data = (struct rv_hwmgr *)(hwmgr->backend);
+ data = (struct smu10_hwmgr *)(hwmgr->backend);
if (index == 0) {
level->memory_clock = data->clock_vol_info.vdd_dep_on_fclk->entries[0].clk;
@@ -804,10 +780,10 @@ static int rv_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_p
return 0;
}
-static int rv_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr,
+static int smu10_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr,
const struct pp_hw_power_state *state, struct pp_clock_info *clock_info)
{
- const struct rv_power_state *ps = cast_const_rv_ps(state);
+ const struct smu10_power_state *ps = cast_const_smu10_ps(state);
clock_info->min_eng_clk = ps->levels[0].engine_clock / (1 << (ps->levels[0].ss_divider_index));
clock_info->max_eng_clk = ps->levels[ps->level - 1].engine_clock / (1 << (ps->levels[ps->level - 1].ss_divider_index));
@@ -822,7 +798,7 @@ static int rv_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr,
#define MEM_LATENCY_ERR 0xFFFF
-static uint32_t rv_get_mem_latency(struct pp_hwmgr *hwmgr,
+static uint32_t smu10_get_mem_latency(struct pp_hwmgr *hwmgr,
uint32_t clock)
{
if (clock >= MEM_FREQ_LOW_LATENCY &&
@@ -834,14 +810,14 @@ static uint32_t rv_get_mem_latency(struct pp_hwmgr *hwmgr,
return MEM_LATENCY_ERR;
}
-static int rv_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
+static int smu10_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
enum amd_pp_clock_type type,
struct pp_clock_levels_with_latency *clocks)
{
uint32_t i;
- struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
- struct rv_clock_voltage_information *pinfo = &(rv_data->clock_vol_info);
- struct rv_voltage_dependency_table *pclk_vol_table;
+ struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
+ struct smu10_clock_voltage_information *pinfo = &(smu10_data->clock_vol_info);
+ struct smu10_voltage_dependency_table *pclk_vol_table;
bool latency_required = false;
if (pinfo == NULL)
@@ -878,7 +854,7 @@ static int rv_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
for (i = 0; i < pclk_vol_table->count; i++) {
clocks->data[i].clocks_in_khz = pclk_vol_table->entries[i].clk;
clocks->data[i].latency_in_us = latency_required ?
- rv_get_mem_latency(hwmgr,
+ smu10_get_mem_latency(hwmgr,
pclk_vol_table->entries[i].clk) :
0;
clocks->num_levels++;
@@ -887,14 +863,14 @@ static int rv_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
return 0;
}
-static int rv_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
+static int smu10_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
enum amd_pp_clock_type type,
struct pp_clock_levels_with_voltage *clocks)
{
uint32_t i;
- struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
- struct rv_clock_voltage_information *pinfo = &(rv_data->clock_vol_info);
- struct rv_voltage_dependency_table *pclk_vol_table = NULL;
+ struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
+ struct smu10_clock_voltage_information *pinfo = &(smu10_data->clock_vol_info);
+ struct smu10_voltage_dependency_table *pclk_vol_table = NULL;
if (pinfo == NULL)
return -EINVAL;
@@ -929,29 +905,28 @@ static int rv_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
return 0;
}
-int rv_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
+static int smu10_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
struct pp_display_clock_request *clock_req)
{
- int result = 0;
- struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
+ struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
enum amd_pp_clock_type clk_type = clock_req->clock_type;
uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
PPSMC_Msg msg;
switch (clk_type) {
case amd_pp_dcf_clock:
- if (clk_freq == rv_data->dcf_actual_hard_min_freq)
+ if (clk_freq == smu10_data->dcf_actual_hard_min_freq)
return 0;
msg = PPSMC_MSG_SetHardMinDcefclkByFreq;
- rv_data->dcf_actual_hard_min_freq = clk_freq;
+ smu10_data->dcf_actual_hard_min_freq = clk_freq;
break;
case amd_pp_soc_clock:
msg = PPSMC_MSG_SetHardMinSocclkByFreq;
break;
case amd_pp_f_clock:
- if (clk_freq == rv_data->f_actual_hard_min_freq)
+ if (clk_freq == smu10_data->f_actual_hard_min_freq)
return 0;
- rv_data->f_actual_hard_min_freq = clk_freq;
+ smu10_data->f_actual_hard_min_freq = clk_freq;
msg = PPSMC_MSG_SetHardMinFclkByFreq;
break;
default:
@@ -959,19 +934,18 @@ int rv_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
return -EINVAL;
}
- result = smum_send_msg_to_smc_with_parameter(hwmgr, msg,
- clk_freq);
+ smum_send_msg_to_smc_with_parameter(hwmgr, msg, clk_freq);
- return result;
+ return 0;
}
-static int rv_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks)
+static int smu10_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks)
{
clocks->engine_max_clock = 80000; /* driver can't get engine clock, temp hard code to 800MHz */
return 0;
}
-static int rv_thermal_get_temperature(struct pp_hwmgr *hwmgr)
+static int smu10_thermal_get_temperature(struct pp_hwmgr *hwmgr)
{
uint32_t reg_offset = soc15_get_register_offset(THM_HWID, 0,
mmTHM_TCON_CUR_TMP_BASE_IDX, mmTHM_TCON_CUR_TMP);
@@ -987,7 +961,7 @@ static int rv_thermal_get_temperature(struct pp_hwmgr *hwmgr)
return cur_temp;
}
-static int rv_read_sensor(struct pp_hwmgr *hwmgr, int idx,
+static int smu10_read_sensor(struct pp_hwmgr *hwmgr, int idx,
void *value, int *size)
{
uint32_t sclk, mclk;
@@ -995,25 +969,21 @@ static int rv_read_sensor(struct pp_hwmgr *hwmgr, int idx,
switch (idx) {
case AMDGPU_PP_SENSOR_GFX_SCLK:
- ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetGfxclkFrequency);
- if (!ret) {
- rv_read_arg_from_smc(hwmgr, &sclk);
+ smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetGfxclkFrequency);
+ sclk = smum_get_argument(hwmgr);
/* in units of 10KHZ */
- *((uint32_t *)value) = sclk * 100;
- *size = 4;
- }
+ *((uint32_t *)value) = sclk * 100;
+ *size = 4;
break;
case AMDGPU_PP_SENSOR_GFX_MCLK:
- ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetFclkFrequency);
- if (!ret) {
- rv_read_arg_from_smc(hwmgr, &mclk);
+ smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetFclkFrequency);
+ mclk = smum_get_argument(hwmgr);
/* in units of 10KHZ */
- *((uint32_t *)value) = mclk * 100;
- *size = 4;
- }
+ *((uint32_t *)value) = mclk * 100;
+ *size = 4;
break;
case AMDGPU_PP_SENSOR_GPU_TEMP:
- *((uint32_t *)value) = rv_thermal_get_temperature(hwmgr);
+ *((uint32_t *)value) = smu10_thermal_get_temperature(hwmgr);
break;
default:
ret = -EINVAL;
@@ -1023,44 +993,50 @@ static int rv_read_sensor(struct pp_hwmgr *hwmgr, int idx,
return ret;
}
-static const struct pp_hwmgr_func rv_hwmgr_funcs = {
- .backend_init = rv_hwmgr_backend_init,
- .backend_fini = rv_hwmgr_backend_fini,
+static int smu10_set_mmhub_powergating_by_smu(struct pp_hwmgr *hwmgr)
+{
+ return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerGateMmHub);
+}
+
+static const struct pp_hwmgr_func smu10_hwmgr_funcs = {
+ .backend_init = smu10_hwmgr_backend_init,
+ .backend_fini = smu10_hwmgr_backend_fini,
.asic_setup = NULL,
- .apply_state_adjust_rules = rv_apply_state_adjust_rules,
- .force_dpm_level = rv_dpm_force_dpm_level,
- .get_power_state_size = rv_get_power_state_size,
+ .apply_state_adjust_rules = smu10_apply_state_adjust_rules,
+ .force_dpm_level = smu10_dpm_force_dpm_level,
+ .get_power_state_size = smu10_get_power_state_size,
.powerdown_uvd = NULL,
.powergate_uvd = NULL,
.powergate_vce = NULL,
- .get_mclk = rv_dpm_get_mclk,
- .get_sclk = rv_dpm_get_sclk,
- .patch_boot_state = rv_dpm_patch_boot_state,
- .get_pp_table_entry = rv_dpm_get_pp_table_entry,
- .get_num_of_pp_table_entries = rv_dpm_get_num_of_pp_table_entries,
- .set_cpu_power_state = rv_set_cpu_power_state,
- .store_cc6_data = rv_store_cc6_data,
- .force_clock_level = rv_force_clock_level,
- .print_clock_levels = rv_print_clock_levels,
- .get_dal_power_level = rv_get_dal_power_level,
- .get_performance_level = rv_get_performance_level,
- .get_current_shallow_sleep_clocks = rv_get_current_shallow_sleep_clocks,
- .get_clock_by_type_with_latency = rv_get_clock_by_type_with_latency,
- .get_clock_by_type_with_voltage = rv_get_clock_by_type_with_voltage,
- .get_max_high_clocks = rv_get_max_high_clocks,
- .read_sensor = rv_read_sensor,
- .set_active_display_count = rv_set_active_display_count,
- .set_deep_sleep_dcefclk = rv_set_deep_sleep_dcefclk,
- .dynamic_state_management_enable = rv_enable_dpm_tasks,
- .power_off_asic = rv_power_off_asic,
- .asic_setup = rv_setup_asic_task,
- .power_state_set = rv_set_power_state_tasks,
- .dynamic_state_management_disable = rv_disable_dpm_tasks,
+ .get_mclk = smu10_dpm_get_mclk,
+ .get_sclk = smu10_dpm_get_sclk,
+ .patch_boot_state = smu10_dpm_patch_boot_state,
+ .get_pp_table_entry = smu10_dpm_get_pp_table_entry,
+ .get_num_of_pp_table_entries = smu10_dpm_get_num_of_pp_table_entries,
+ .set_cpu_power_state = smu10_set_cpu_power_state,
+ .store_cc6_data = smu10_store_cc6_data,
+ .force_clock_level = smu10_force_clock_level,
+ .print_clock_levels = smu10_print_clock_levels,
+ .get_dal_power_level = smu10_get_dal_power_level,
+ .get_performance_level = smu10_get_performance_level,
+ .get_current_shallow_sleep_clocks = smu10_get_current_shallow_sleep_clocks,
+ .get_clock_by_type_with_latency = smu10_get_clock_by_type_with_latency,
+ .get_clock_by_type_with_voltage = smu10_get_clock_by_type_with_voltage,
+ .get_max_high_clocks = smu10_get_max_high_clocks,
+ .read_sensor = smu10_read_sensor,
+ .set_active_display_count = smu10_set_active_display_count,
+ .set_deep_sleep_dcefclk = smu10_set_deep_sleep_dcefclk,
+ .dynamic_state_management_enable = smu10_enable_dpm_tasks,
+ .power_off_asic = smu10_power_off_asic,
+ .asic_setup = smu10_setup_asic_task,
+ .power_state_set = smu10_set_power_state_tasks,
+ .dynamic_state_management_disable = smu10_disable_dpm_tasks,
+ .set_mmhub_powergating_by_smu = smu10_set_mmhub_powergating_by_smu,
};
-int rv_init_function_pointers(struct pp_hwmgr *hwmgr)
+int smu10_init_function_pointers(struct pp_hwmgr *hwmgr)
{
- hwmgr->hwmgr_func = &rv_hwmgr_funcs;
+ hwmgr->hwmgr_func = &smu10_hwmgr_funcs;
hwmgr->pptable_func = &pptable_funcs;
return 0;
}
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h
index c3bc311dc59f..175c3a592b6c 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h
@@ -21,17 +21,17 @@
*
*/
-#ifndef RAVEN_HWMGR_H
-#define RAVEN_HWMGR_H
+#ifndef SMU10_HWMGR_H
+#define SMU10_HWMGR_H
#include "hwmgr.h"
-#include "rv_inc.h"
+#include "smu10_inc.h"
#include "smu10_driver_if.h"
#include "rv_ppsmc.h"
-#define RAVEN_MAX_HARDWARE_POWERLEVELS 8
-#define PHMRAVEN_DYNCLK_NUMBER_OF_TREND_COEFFICIENTS 15
+#define SMU10_MAX_HARDWARE_POWERLEVELS 8
+#define SMU10_DYNCLK_NUMBER_OF_TREND_COEFFICIENTS 15
#define DPMFlags_SCLK_Enabled 0x00000001
#define DPMFlags_UVD_Enabled 0x00000002
@@ -47,10 +47,10 @@
#define SMU_PHYID_SHIFT 8
-#define RAVEN_PCIE_POWERGATING_TARGET_GFX 0
-#define RAVEN_PCIE_POWERGATING_TARGET_DDI 1
-#define RAVEN_PCIE_POWERGATING_TARGET_PLLCASCADE 2
-#define RAVEN_PCIE_POWERGATING_TARGET_PHY 3
+#define SMU10_PCIE_POWERGATING_TARGET_GFX 0
+#define SMU10_PCIE_POWERGATING_TARGET_DDI 1
+#define SMU10_PCIE_POWERGATING_TARGET_PLLCASCADE 2
+#define SMU10_PCIE_POWERGATING_TARGET_PHY 3
enum VQ_TYPE {
CLOCK_TYPE_DCLK = 0L,
@@ -65,14 +65,14 @@ enum VQ_TYPE {
#define SUSTAINABLE_CU_MASK 0xff000000
#define SUSTAINABLE_CU_SHIFT 24
-struct rv_dpm_entry {
+struct smu10_dpm_entry {
uint32_t soft_min_clk;
uint32_t hard_min_clk;
uint32_t soft_max_clk;
uint32_t hard_max_clk;
};
-struct rv_power_level {
+struct smu10_power_level {
uint32_t engine_clock;
uint8_t vddc_index;
uint8_t ds_divider_index;
@@ -86,14 +86,14 @@ struct rv_power_level {
uint8_t rsv[3];
};
-/*used for the nbpsFlags field in rv_power state*/
-#define RAVEN_POWERSTATE_FLAGS_NBPS_FORCEHIGH (1<<0)
-#define RAVEN_POWERSTATE_FLAGS_NBPS_LOCKTOHIGH (1<<1)
-#define RAVEN_POWERSTATE_FLAGS_NBPS_LOCKTOLOW (1<<2)
+/*used for the nbpsFlags field in smu10_power state*/
+#define SMU10_POWERSTATE_FLAGS_NBPS_FORCEHIGH (1<<0)
+#define SMU10_POWERSTATE_FLAGS_NBPS_LOCKTOHIGH (1<<1)
+#define SMU10_POWERSTATE_FLAGS_NBPS_LOCKTOLOW (1<<2)
-#define RAVEN_POWERSTATE_FLAGS_BAPM_DISABLE (1<<0)
+#define SMU10_POWERSTATE_FLAGS_BAPM_DISABLE (1<<0)
-struct rv_uvd_clocks {
+struct smu10_uvd_clocks {
uint32_t vclk;
uint32_t dclk;
uint32_t vclk_low_divider;
@@ -118,16 +118,16 @@ struct pp_disable_nbpslo_flags {
};
-enum rv_pstate_previous_action {
+enum smu10_pstate_previous_action {
DO_NOTHING = 1,
FORCE_HIGH,
CANCEL_FORCE_HIGH
};
-struct rv_power_state {
+struct smu10_power_state {
unsigned int magic;
uint32_t level;
- struct rv_uvd_clocks uvd_clocks;
+ struct smu10_uvd_clocks uvd_clocks;
uint32_t evclk;
uint32_t ecclk;
uint32_t samclk;
@@ -141,79 +141,79 @@ struct rv_power_state {
uint8_t dpm_x_nbps_low;
uint8_t dpm_x_nbps_high;
- enum rv_pstate_previous_action action;
+ enum smu10_pstate_previous_action action;
- struct rv_power_level levels[RAVEN_MAX_HARDWARE_POWERLEVELS];
+ struct smu10_power_level levels[SMU10_MAX_HARDWARE_POWERLEVELS];
struct pp_disable_nbpslo_flags nbpslo_flags;
};
-#define RAVEN_NUM_NBPSTATES 4
-#define RAVEN_NUM_NBPMEMORYCLOCK 2
+#define SMU10_NUM_NBPSTATES 4
+#define SMU10_NUM_NBPMEMORYCLOCK 2
-struct rv_display_phy_info_entry {
+struct smu10_display_phy_info_entry {
uint8_t phy_present;
uint8_t active_lane_mapping;
uint8_t display_config_type;
uint8_t active_num_of_lanes;
};
-#define RAVEN_MAX_DISPLAYPHY_IDS 10
+#define SMU10_MAX_DISPLAYPHY_IDS 10
-struct rv_display_phy_info {
+struct smu10_display_phy_info {
bool display_phy_access_initialized;
- struct rv_display_phy_info_entry entries[RAVEN_MAX_DISPLAYPHY_IDS];
+ struct smu10_display_phy_info_entry entries[SMU10_MAX_DISPLAYPHY_IDS];
};
#define MAX_DISPLAY_CLOCK_LEVEL 8
-struct rv_system_info{
+struct smu10_system_info{
uint8_t htc_tmp_lmt;
uint8_t htc_hyst_lmt;
};
#define MAX_REGULAR_DPM_NUMBER 8
-struct rv_mclk_latency_entries {
+struct smu10_mclk_latency_entries {
uint32_t frequency;
uint32_t latency;
};
-struct rv_mclk_latency_table {
+struct smu10_mclk_latency_table {
uint32_t count;
- struct rv_mclk_latency_entries entries[MAX_REGULAR_DPM_NUMBER];
+ struct smu10_mclk_latency_entries entries[MAX_REGULAR_DPM_NUMBER];
};
-struct rv_clock_voltage_dependency_record {
+struct smu10_clock_voltage_dependency_record {
uint32_t clk;
uint32_t vol;
};
-struct rv_voltage_dependency_table {
+struct smu10_voltage_dependency_table {
uint32_t count;
- struct rv_clock_voltage_dependency_record entries[1];
+ struct smu10_clock_voltage_dependency_record entries[1];
};
-struct rv_clock_voltage_information {
- struct rv_voltage_dependency_table *vdd_dep_on_dcefclk;
- struct rv_voltage_dependency_table *vdd_dep_on_socclk;
- struct rv_voltage_dependency_table *vdd_dep_on_fclk;
- struct rv_voltage_dependency_table *vdd_dep_on_mclk;
- struct rv_voltage_dependency_table *vdd_dep_on_dispclk;
- struct rv_voltage_dependency_table *vdd_dep_on_dppclk;
- struct rv_voltage_dependency_table *vdd_dep_on_phyclk;
+struct smu10_clock_voltage_information {
+ struct smu10_voltage_dependency_table *vdd_dep_on_dcefclk;
+ struct smu10_voltage_dependency_table *vdd_dep_on_socclk;
+ struct smu10_voltage_dependency_table *vdd_dep_on_fclk;
+ struct smu10_voltage_dependency_table *vdd_dep_on_mclk;
+ struct smu10_voltage_dependency_table *vdd_dep_on_dispclk;
+ struct smu10_voltage_dependency_table *vdd_dep_on_dppclk;
+ struct smu10_voltage_dependency_table *vdd_dep_on_phyclk;
};
-struct rv_hwmgr {
+struct smu10_hwmgr {
uint32_t disable_driver_thermal_policy;
uint32_t thermal_auto_throttling_treshold;
- struct rv_system_info sys_info;
- struct rv_mclk_latency_table mclk_latency_table;
+ struct smu10_system_info sys_info;
+ struct smu10_mclk_latency_table mclk_latency_table;
uint32_t ddi_power_gating_disabled;
- struct rv_display_phy_info_entry display_phy_info;
+ struct smu10_display_phy_info_entry display_phy_info;
uint32_t dce_slow_sclk_threshold;
bool disp_clk_bypass;
@@ -255,10 +255,10 @@ struct rv_hwmgr {
uint32_t fps_low_threshold;
uint32_t dpm_flags;
- struct rv_dpm_entry sclk_dpm;
- struct rv_dpm_entry uvd_dpm;
- struct rv_dpm_entry vce_dpm;
- struct rv_dpm_entry acp_dpm;
+ struct smu10_dpm_entry sclk_dpm;
+ struct smu10_dpm_entry uvd_dpm;
+ struct smu10_dpm_entry vce_dpm;
+ struct smu10_dpm_entry acp_dpm;
bool acp_power_up_no_dsp;
uint32_t max_sclk_level;
@@ -291,7 +291,7 @@ struct rv_hwmgr {
bool gfx_off_controled_by_driver;
Watermarks_t water_marks_table;
- struct rv_clock_voltage_information clock_vol_info;
+ struct smu10_clock_voltage_information clock_vol_info;
DpmClocks_t clock_table;
uint32_t active_process_mask;
@@ -302,21 +302,21 @@ struct rv_hwmgr {
struct pp_hwmgr;
-int rv_init_function_pointers(struct pp_hwmgr *hwmgr);
+int smu10_init_function_pointers(struct pp_hwmgr *hwmgr);
-/* UMD PState Raven Msg Parameters in MHz */
-#define RAVEN_UMD_PSTATE_GFXCLK 700
-#define RAVEN_UMD_PSTATE_SOCCLK 626
-#define RAVEN_UMD_PSTATE_FCLK 933
-#define RAVEN_UMD_PSTATE_VCE 0x03C00320
+/* UMD PState SMU10 Msg Parameters in MHz */
+#define SMU10_UMD_PSTATE_GFXCLK 700
+#define SMU10_UMD_PSTATE_SOCCLK 626
+#define SMU10_UMD_PSTATE_FCLK 933
+#define SMU10_UMD_PSTATE_VCE 0x03C00320
-#define RAVEN_UMD_PSTATE_PEAK_GFXCLK 1100
-#define RAVEN_UMD_PSTATE_PEAK_SOCCLK 757
-#define RAVEN_UMD_PSTATE_PEAK_FCLK 1200
+#define SMU10_UMD_PSTATE_PEAK_GFXCLK 1100
+#define SMU10_UMD_PSTATE_PEAK_SOCCLK 757
+#define SMU10_UMD_PSTATE_PEAK_FCLK 1200
-#define RAVEN_UMD_PSTATE_MIN_GFXCLK 200
-#define RAVEN_UMD_PSTATE_MIN_FCLK 400
-#define RAVEN_UMD_PSTATE_MIN_SOCCLK 200
-#define RAVEN_UMD_PSTATE_MIN_VCE 0x0190012C
+#define SMU10_UMD_PSTATE_MIN_GFXCLK 200
+#define SMU10_UMD_PSTATE_MIN_FCLK 400
+#define SMU10_UMD_PSTATE_MIN_SOCCLK 200
+#define SMU10_UMD_PSTATE_MIN_VCE 0x0190012C
#endif
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_inc.h
index ae59a3fdea8a..edb68e302f6f 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_inc.h
@@ -21,8 +21,8 @@
*
*/
-#ifndef RAVEN_INC_H
-#define RAVEN_INC_H
+#ifndef SMU10_INC_H
+#define SMU10_INC_H
#include "asic_reg/mp/mp_10_0_default.h"
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
index 69a0678ace98..f4cbaee4e2ca 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
@@ -162,7 +162,7 @@ void smu7_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
AMD_CG_STATE_UNGATE);
cgs_set_powergating_state(hwmgr->device,
AMD_IP_BLOCK_TYPE_UVD,
- AMD_CG_STATE_UNGATE);
+ AMD_PG_STATE_UNGATE);
smu7_update_uvd_dpm(hwmgr, false);
}
@@ -472,23 +472,12 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
*/
int smu7_enable_per_cu_power_gating(struct pp_hwmgr *hwmgr, bool enable)
{
- struct cgs_system_info sys_info = {0};
- uint32_t active_cus;
- int result;
-
- sys_info.size = sizeof(struct cgs_system_info);
- sys_info.info_id = CGS_SYSTEM_INFO_GFX_CU_INFO;
-
- result = cgs_query_system_info(hwmgr->device, &sys_info);
-
- if (result)
- return -EINVAL;
-
- active_cus = sys_info.value;
+ struct amdgpu_device *adev = hwmgr->adev;
if (enable)
return smum_send_msg_to_smc_with_parameter(hwmgr,
- PPSMC_MSG_GFX_CU_PG_ENABLE, active_cus);
+ PPSMC_MSG_GFX_CU_PG_ENABLE,
+ adev->gfx.cu_info.number);
else
return smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_GFX_CU_PG_DISABLE);
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h
index 7b54d48b2ce2..1ddce023218a 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h
@@ -25,7 +25,6 @@
#define _SMU7_CLOCK_POWER_GATING_H_
#include "smu7_hwmgr.h"
-#include "pp_asicblocks.h"
void smu7_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate);
void smu7_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate);
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_dyn_defaults.h b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_dyn_defaults.h
index f967613191cf..3477d4dfff70 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_dyn_defaults.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_dyn_defaults.h
@@ -50,6 +50,6 @@
#define SMU7_CGULVCONTROL_DFLT 0x00007450
#define SMU7_TARGETACTIVITY_DFLT 50
#define SMU7_MCLK_TARGETACTIVITY_DFLT 10
-
+#define SMU7_SCLK_TARGETACTIVITY_DFLT 30
#endif
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 41e42beff213..7a87209f7258 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -27,7 +27,6 @@
#include <linux/slab.h>
#include <asm/div64.h>
#include <drm/amdgpu_drm.h>
-#include "pp_acpi.h"
#include "ppatomctrl.h"
#include "atombios.h"
#include "pptable_v1_0.h"
@@ -41,13 +40,13 @@
#include "hwmgr.h"
#include "smu7_hwmgr.h"
-#include "smu7_smumgr.h"
#include "smu_ucode_xfer_vi.h"
#include "smu7_powertune.h"
#include "smu7_dyn_defaults.h"
#include "smu7_thermal.h"
#include "smu7_clockpowergating.h"
#include "processpptables.h"
+#include "pp_thermal.h"
#define MC_CG_ARB_FREQ_F0 0x0a
#define MC_CG_ARB_FREQ_F1 0x0b
@@ -80,6 +79,13 @@
#define PCIE_BUS_CLK 10000
#define TCLK (PCIE_BUS_CLK / 10)
+static const struct profile_mode_setting smu7_profiling[5] =
+ {{1, 0, 100, 30, 1, 0, 100, 10},
+ {1, 10, 0, 30, 0, 0, 0, 0},
+ {0, 0, 0, 0, 1, 10, 16, 31},
+ {1, 0, 11, 50, 1, 0, 100, 10},
+ {1, 0, 5, 30, 0, 0, 0, 0},
+ };
/** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
enum DPM_EVENT_SRC {
@@ -90,7 +96,6 @@ enum DPM_EVENT_SRC {
DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4
};
-static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable);
static const unsigned long PhwVIslands_Magic = (unsigned long)(PHM_VIslands_Magic);
static int smu7_force_clock_level(struct pp_hwmgr *hwmgr,
enum pp_clock_type type, uint32_t mask);
@@ -792,6 +797,76 @@ static int smu7_setup_dpm_tables_v1(struct pp_hwmgr *hwmgr)
return 0;
}
+static int smu7_get_voltage_dependency_table(
+ const struct phm_ppt_v1_clock_voltage_dependency_table *allowed_dep_table,
+ struct phm_ppt_v1_clock_voltage_dependency_table *dep_table)
+{
+ uint8_t i = 0;
+ PP_ASSERT_WITH_CODE((0 != allowed_dep_table->count),
+ "Voltage Lookup Table empty",
+ return -EINVAL);
+
+ dep_table->count = allowed_dep_table->count;
+ for (i=0; i<dep_table->count; i++) {
+ dep_table->entries[i].clk = allowed_dep_table->entries[i].clk;
+ dep_table->entries[i].vddInd = allowed_dep_table->entries[i].vddInd;
+ dep_table->entries[i].vdd_offset = allowed_dep_table->entries[i].vdd_offset;
+ dep_table->entries[i].vddc = allowed_dep_table->entries[i].vddc;
+ dep_table->entries[i].vddgfx = allowed_dep_table->entries[i].vddgfx;
+ dep_table->entries[i].vddci = allowed_dep_table->entries[i].vddci;
+ dep_table->entries[i].mvdd = allowed_dep_table->entries[i].mvdd;
+ dep_table->entries[i].phases = allowed_dep_table->entries[i].phases;
+ dep_table->entries[i].cks_enable = allowed_dep_table->entries[i].cks_enable;
+ dep_table->entries[i].cks_voffset = allowed_dep_table->entries[i].cks_voffset;
+ }
+
+ return 0;
+}
+
+static int smu7_odn_initial_default_setting(struct pp_hwmgr *hwmgr)
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table);
+ struct phm_ppt_v1_information *table_info =
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
+ uint32_t i;
+
+ struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table;
+ struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table;
+
+ if (table_info == NULL)
+ return -EINVAL;
+
+ dep_sclk_table = table_info->vdd_dep_on_sclk;
+ dep_mclk_table = table_info->vdd_dep_on_mclk;
+
+ odn_table->odn_core_clock_dpm_levels.num_of_pl =
+ data->golden_dpm_table.sclk_table.count;
+ for (i=0; i<data->golden_dpm_table.sclk_table.count; i++) {
+ odn_table->odn_core_clock_dpm_levels.entries[i].clock =
+ data->golden_dpm_table.sclk_table.dpm_levels[i].value;
+ odn_table->odn_core_clock_dpm_levels.entries[i].enabled = true;
+ odn_table->odn_core_clock_dpm_levels.entries[i].vddc = dep_sclk_table->entries[i].vddc;
+ }
+
+ smu7_get_voltage_dependency_table(dep_sclk_table,
+ (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_sclk));
+
+ odn_table->odn_memory_clock_dpm_levels.num_of_pl =
+ data->golden_dpm_table.mclk_table.count;
+ for (i=0; i<data->golden_dpm_table.sclk_table.count; i++) {
+ odn_table->odn_memory_clock_dpm_levels.entries[i].clock =
+ data->golden_dpm_table.mclk_table.dpm_levels[i].value;
+ odn_table->odn_memory_clock_dpm_levels.entries[i].enabled = true;
+ odn_table->odn_memory_clock_dpm_levels.entries[i].vddc = dep_mclk_table->entries[i].vddc;
+ }
+
+ smu7_get_voltage_dependency_table(dep_mclk_table,
+ (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_mclk));
+
+ return 0;
+}
+
static int smu7_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
{
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
@@ -808,6 +883,11 @@ static int smu7_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
/* save a copy of the default DPM table */
memcpy(&(data->golden_dpm_table), &(data->dpm_table),
sizeof(struct smu7_dpm_table));
+
+ /* initialize ODN table */
+ if (hwmgr->od_enabled)
+ smu7_odn_initial_default_setting(hwmgr);
+
return 0;
}
@@ -1164,11 +1244,6 @@ static int smu7_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
int tmp_result = 0;
int result = 0;
- tmp_result = (!smum_is_dpm_running(hwmgr)) ? 0 : -1;
- PP_ASSERT_WITH_CODE(tmp_result == 0,
- "DPM is already running",
- );
-
if (smu7_voltage_control(hwmgr)) {
tmp_result = smu7_enable_voltage_control(hwmgr);
PP_ASSERT_WITH_CODE(tmp_result == 0,
@@ -1275,15 +1350,53 @@ static int smu7_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
return 0;
}
+static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable)
+{
+ if (!hwmgr->avfs_supported)
+ return 0;
+
+ if (enable) {
+ if (!PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
+ CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON)) {
+ PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
+ hwmgr, PPSMC_MSG_EnableAvfs),
+ "Failed to enable AVFS!",
+ return -EINVAL);
+ }
+ } else if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
+ CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON)) {
+ PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
+ hwmgr, PPSMC_MSG_DisableAvfs),
+ "Failed to disable AVFS!",
+ return -EINVAL);
+ }
+
+ return 0;
+}
+
+static int smu7_update_avfs(struct pp_hwmgr *hwmgr)
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+
+ if (!hwmgr->avfs_supported)
+ return 0;
+
+ if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_VDDC) {
+ smu7_avfs_control(hwmgr, false);
+ } else if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
+ smu7_avfs_control(hwmgr, false);
+ smu7_avfs_control(hwmgr, true);
+ } else {
+ smu7_avfs_control(hwmgr, true);
+ }
+
+ return 0;
+}
+
int smu7_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
{
int tmp_result, result = 0;
- tmp_result = (smum_is_dpm_running(hwmgr)) ? 0 : -1;
- PP_ASSERT_WITH_CODE(tmp_result == 0,
- "DPM is not running right now, no need to disable DPM!",
- return 0);
-
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_ThermalController))
PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
@@ -1352,12 +1465,10 @@ static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr)
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
struct phm_ppt_v1_information *table_info =
(struct phm_ppt_v1_information *)(hwmgr->pptable);
- struct cgs_system_info sys_info = {0};
- int result;
+ struct amdgpu_device *adev = hwmgr->adev;
data->dll_default_on = false;
data->mclk_dpm0_activity_target = 0xa;
- data->mclk_activity_target = SMU7_MCLK_TARGETACTIVITY_DFLT;
data->vddc_vddgfx_delta = 300;
data->static_screen_threshold = SMU7_STATICSCREENTHRESHOLD_DFLT;
data->static_screen_threshold_unit = SMU7_STATICSCREENTHRESHOLDUNIT_DFLT;
@@ -1381,6 +1492,17 @@ static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr)
data->enable_pkg_pwr_tracking_feature = true;
data->force_pcie_gen = PP_PCIEGenInvalid;
data->ulv_supported = hwmgr->feature_mask & PP_ULV_MASK ? true : false;
+ data->current_profile_setting.bupdate_sclk = 1;
+ data->current_profile_setting.sclk_up_hyst = 0;
+ data->current_profile_setting.sclk_down_hyst = 100;
+ data->current_profile_setting.sclk_activity = SMU7_SCLK_TARGETACTIVITY_DFLT;
+ data->current_profile_setting.bupdate_sclk = 1;
+ data->current_profile_setting.mclk_up_hyst = 0;
+ data->current_profile_setting.mclk_down_hyst = 100;
+ data->current_profile_setting.mclk_activity = SMU7_MCLK_TARGETACTIVITY_DFLT;
+ hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D];
+ hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
+ hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
if (hwmgr->chip_id == CHIP_POLARIS12 || hwmgr->is_kicker) {
uint8_t tmp1, tmp2;
@@ -1467,17 +1589,13 @@ static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr)
data->pcie_lane_power_saving.max = 0;
data->pcie_lane_power_saving.min = 16;
- sys_info.size = sizeof(struct cgs_system_info);
- sys_info.info_id = CGS_SYSTEM_INFO_PG_FLAGS;
- result = cgs_query_system_info(hwmgr->device, &sys_info);
- if (!result) {
- if (sys_info.value & AMD_PG_SUPPORT_UVD)
- phm_cap_set(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_UVDPowerGating);
- if (sys_info.value & AMD_PG_SUPPORT_VCE)
- phm_cap_set(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_VCEPowerGating);
- }
+
+ if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
+ phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_UVDPowerGating);
+ if (adev->pg_flags & AMD_PG_SUPPORT_VCE)
+ phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_VCEPowerGating);
}
/**
@@ -1912,7 +2030,7 @@ static int smu7_patch_voltage_workaround(struct pp_hwmgr *hwmgr)
struct phm_ppt_v1_voltage_lookup_table *lookup_table;
uint32_t i;
uint32_t hw_revision, sub_vendor_id, sub_sys_id;
- struct cgs_system_info sys_info = {0};
+ struct amdgpu_device *adev = hwmgr->adev;
if (table_info != NULL) {
dep_mclk_table = table_info->vdd_dep_on_mclk;
@@ -1920,19 +2038,9 @@ static int smu7_patch_voltage_workaround(struct pp_hwmgr *hwmgr)
} else
return 0;
- sys_info.size = sizeof(struct cgs_system_info);
-
- sys_info.info_id = CGS_SYSTEM_INFO_PCIE_REV;
- cgs_query_system_info(hwmgr->device, &sys_info);
- hw_revision = (uint32_t)sys_info.value;
-
- sys_info.info_id = CGS_SYSTEM_INFO_PCIE_SUB_SYS_ID;
- cgs_query_system_info(hwmgr->device, &sys_info);
- sub_sys_id = (uint32_t)sys_info.value;
-
- sys_info.info_id = CGS_SYSTEM_INFO_PCIE_SUB_SYS_VENDOR_ID;
- cgs_query_system_info(hwmgr->device, &sys_info);
- sub_vendor_id = (uint32_t)sys_info.value;
+ hw_revision = adev->pdev->revision;
+ sub_sys_id = adev->pdev->subsystem_device;
+ sub_vendor_id = adev->pdev->subsystem_vendor;
if (hwmgr->chip_id == CHIP_POLARIS10 && hw_revision == 0xC7 &&
((sub_sys_id == 0xb37 && sub_vendor_id == 0x1002) ||
@@ -2266,14 +2374,18 @@ static int smu7_set_private_data_based_on_pptable_v0(struct pp_hwmgr *hwmgr)
struct phm_clock_voltage_dependency_table *allowed_mclk_vddci_table = hwmgr->dyn_state.vddci_dependency_on_mclk;
PP_ASSERT_WITH_CODE(allowed_sclk_vddc_table != NULL,
- "VDDC dependency on SCLK table is missing. This table is mandatory\n", return -EINVAL);
+ "VDDC dependency on SCLK table is missing. This table is mandatory",
+ return -EINVAL);
PP_ASSERT_WITH_CODE(allowed_sclk_vddc_table->count >= 1,
- "VDDC dependency on SCLK table has to have is missing. This table is mandatory\n", return -EINVAL);
+ "VDDC dependency on SCLK table has to have is missing. This table is mandatory",
+ return -EINVAL);
PP_ASSERT_WITH_CODE(allowed_mclk_vddc_table != NULL,
- "VDDC dependency on MCLK table is missing. This table is mandatory\n", return -EINVAL);
+ "VDDC dependency on MCLK table is missing. This table is mandatory",
+ return -EINVAL);
PP_ASSERT_WITH_CODE(allowed_mclk_vddc_table->count >= 1,
- "VDD dependency on MCLK table has to have is missing. This table is mandatory\n", return -EINVAL);
+ "VDD dependency on MCLK table has to have is missing. This table is mandatory",
+ return -EINVAL);
data->min_vddc_in_pptable = (uint16_t)allowed_sclk_vddc_table->entries[0].v;
data->max_vddc_in_pptable = (uint16_t)allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
@@ -2371,7 +2483,7 @@ static int smu7_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
result = phm_initializa_dynamic_state_adjustment_rule_settings(hwmgr);
if (0 == result) {
- struct cgs_system_info sys_info = {0};
+ struct amdgpu_device *adev = hwmgr->adev;
data->is_tlu_enabled = false;
@@ -2380,22 +2492,10 @@ static int smu7_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
- sys_info.size = sizeof(struct cgs_system_info);
- sys_info.info_id = CGS_SYSTEM_INFO_PCIE_GEN_INFO;
- result = cgs_query_system_info(hwmgr->device, &sys_info);
- if (result)
- data->pcie_gen_cap = AMDGPU_DEFAULT_PCIE_GEN_MASK;
- else
- data->pcie_gen_cap = (uint32_t)sys_info.value;
+ data->pcie_gen_cap = adev->pm.pcie_gen_mask;
if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
data->pcie_spc_cap = 20;
- sys_info.size = sizeof(struct cgs_system_info);
- sys_info.info_id = CGS_SYSTEM_INFO_PCIE_MLW;
- result = cgs_query_system_info(hwmgr->device, &sys_info);
- if (result)
- data->pcie_lane_cap = AMDGPU_DEFAULT_PCIE_MLW_MASK;
- else
- data->pcie_lane_cap = (uint32_t)sys_info.value;
+ data->pcie_lane_cap = adev->pm.pcie_mlw_mask;
hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
/* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
@@ -2574,8 +2674,10 @@ static int smu7_get_profiling_clk(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_le
break;
}
}
- if (count < 0 || level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK)
+ if (count < 0 || level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
*sclk_mask = 0;
+ tmp_sclk = hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].clk;
+ }
if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
*sclk_mask = hwmgr->dyn_state.vddc_dependency_on_sclk->count-1;
@@ -2590,8 +2692,10 @@ static int smu7_get_profiling_clk(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_le
break;
}
}
- if (count < 0 || level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK)
+ if (count < 0 || level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
*sclk_mask = 0;
+ tmp_sclk = table_info->vdd_dep_on_sclk->entries[0].clk;
+ }
if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
*sclk_mask = table_info->vdd_dep_on_sclk->count - 1;
@@ -2603,6 +2707,9 @@ static int smu7_get_profiling_clk(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_le
*mclk_mask = golden_dpm_table->mclk_table.count - 1;
*pcie_mask = data->dpm_table.pcie_speed_table.count - 1;
+ hwmgr->pstate_sclk = tmp_sclk;
+ hwmgr->pstate_mclk = tmp_mclk;
+
return 0;
}
@@ -2614,6 +2721,9 @@ static int smu7_force_dpm_level(struct pp_hwmgr *hwmgr,
uint32_t mclk_mask = 0;
uint32_t pcie_mask = 0;
+ if (hwmgr->pstate_sclk == 0)
+ smu7_get_profiling_clk(hwmgr, level, &sclk_mask, &mclk_mask, &pcie_mask);
+
switch (level) {
case AMD_DPM_FORCED_LEVEL_HIGH:
ret = smu7_force_dpm_highest(hwmgr);
@@ -2756,10 +2866,12 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
- disable_mclk_switching = ((1 < info.display_count) ||
- disable_mclk_switching_for_frame_lock ||
- smu7_vblank_too_short(hwmgr, mode_info.vblank_time_us) ||
- (mode_info.refresh_rate > 120));
+ if (info.display_count == 0)
+ disable_mclk_switching = false;
+ else
+ disable_mclk_switching = ((1 < info.display_count) ||
+ disable_mclk_switching_for_frame_lock ||
+ smu7_vblank_too_short(hwmgr, mode_info.vblank_time_us));
sclk = smu7_ps->performance_levels[0].engine_clock;
mclk = smu7_ps->performance_levels[0].memory_clock;
@@ -3312,7 +3424,7 @@ static int smu7_read_sensor(struct pp_hwmgr *hwmgr, int idx,
void *value, int *size)
{
uint32_t sclk, mclk, activity_percent;
- uint32_t offset;
+ uint32_t offset, val_vid;
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
/* size must be at least 4 bytes for all sensors */
@@ -3360,6 +3472,16 @@ static int smu7_read_sensor(struct pp_hwmgr *hwmgr, int idx,
return -EINVAL;
*size = sizeof(struct pp_gpu_power);
return smu7_get_gpu_power(hwmgr, (struct pp_gpu_power *)value);
+ case AMDGPU_PP_SENSOR_VDDGFX:
+ if ((data->vr_config & 0xff) == 0x2)
+ val_vid = PHM_READ_INDIRECT_FIELD(hwmgr->device,
+ CGS_IND_REG__SMC, PWR_SVI2_STATUS, PLANE2_VID);
+ else
+ val_vid = PHM_READ_INDIRECT_FIELD(hwmgr->device,
+ CGS_IND_REG__SMC, PWR_SVI2_STATUS, PLANE1_VID);
+
+ *((uint32_t *)value) = (uint32_t)convert_to_vddc(val_vid);
+ return 0;
default:
return -EINVAL;
}
@@ -3382,8 +3504,6 @@ static int smu7_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, cons
uint32_t i;
struct cgs_display_info info = {0};
- data->need_update_smu7_dpm_table = 0;
-
for (i = 0; i < sclk_table->count; i++) {
if (sclk == sclk_table->dpm_levels[i].value)
break;
@@ -3466,15 +3586,17 @@ static int smu7_request_link_speed_change_before_state_change(
if (target_link_speed > current_link_speed) {
switch (target_link_speed) {
+#ifdef CONFIG_ACPI
case PP_PCIEGen3:
- if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN3, false))
+ if (0 == amdgpu_acpi_pcie_performance_request(hwmgr->adev, PCIE_PERF_REQ_GEN3, false))
break;
data->force_pcie_gen = PP_PCIEGen2;
if (current_link_speed == PP_PCIEGen2)
break;
case PP_PCIEGen2:
- if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN2, false))
+ if (0 == amdgpu_acpi_pcie_performance_request(hwmgr->adev, PCIE_PERF_REQ_GEN2, false))
break;
+#endif
default:
data->force_pcie_gen = smu7_get_current_pcie_speed(hwmgr);
break;
@@ -3525,108 +3647,27 @@ static int smu7_populate_and_upload_sclk_mclk_dpm_levels(
struct pp_hwmgr *hwmgr, const void *input)
{
int result = 0;
- const struct phm_set_power_state_input *states =
- (const struct phm_set_power_state_input *)input;
- const struct smu7_power_state *smu7_ps =
- cast_const_phw_smu7_power_state(states->pnew_state);
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- uint32_t sclk = smu7_ps->performance_levels
- [smu7_ps->performance_level_count - 1].engine_clock;
- uint32_t mclk = smu7_ps->performance_levels
- [smu7_ps->performance_level_count - 1].memory_clock;
struct smu7_dpm_table *dpm_table = &data->dpm_table;
-
- struct smu7_dpm_table *golden_dpm_table = &data->golden_dpm_table;
- uint32_t dpm_count, clock_percent;
- uint32_t i;
+ uint32_t count;
+ struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table);
+ struct phm_odn_clock_levels *odn_sclk_table = &(odn_table->odn_core_clock_dpm_levels);
+ struct phm_odn_clock_levels *odn_mclk_table = &(odn_table->odn_memory_clock_dpm_levels);
if (0 == data->need_update_smu7_dpm_table)
return 0;
- if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
- dpm_table->sclk_table.dpm_levels
- [dpm_table->sclk_table.count - 1].value = sclk;
-
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
- /* Need to do calculation based on the golden DPM table
- * as the Heatmap GPU Clock axis is also based on the default values
- */
- PP_ASSERT_WITH_CODE(
- (golden_dpm_table->sclk_table.dpm_levels
- [golden_dpm_table->sclk_table.count - 1].value != 0),
- "Divide by 0!",
- return -EINVAL);
- dpm_count = dpm_table->sclk_table.count < 2 ? 0 : dpm_table->sclk_table.count - 2;
-
- for (i = dpm_count; i > 1; i--) {
- if (sclk > golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value) {
- clock_percent =
- ((sclk
- - golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value
- ) * 100)
- / golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value;
-
- dpm_table->sclk_table.dpm_levels[i].value =
- golden_dpm_table->sclk_table.dpm_levels[i].value +
- (golden_dpm_table->sclk_table.dpm_levels[i].value *
- clock_percent)/100;
-
- } else if (golden_dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value > sclk) {
- clock_percent =
- ((golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count - 1].value
- - sclk) * 100)
- / golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value;
-
- dpm_table->sclk_table.dpm_levels[i].value =
- golden_dpm_table->sclk_table.dpm_levels[i].value -
- (golden_dpm_table->sclk_table.dpm_levels[i].value *
- clock_percent) / 100;
- } else
- dpm_table->sclk_table.dpm_levels[i].value =
- golden_dpm_table->sclk_table.dpm_levels[i].value;
- }
+ if (hwmgr->od_enabled && data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
+ for (count = 0; count < dpm_table->sclk_table.count; count++) {
+ dpm_table->sclk_table.dpm_levels[count].enabled = odn_sclk_table->entries[count].enabled;
+ dpm_table->sclk_table.dpm_levels[count].value = odn_sclk_table->entries[count].clock;
}
}
- if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
- dpm_table->mclk_table.dpm_levels
- [dpm_table->mclk_table.count - 1].value = mclk;
-
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
-
- PP_ASSERT_WITH_CODE(
- (golden_dpm_table->mclk_table.dpm_levels
- [golden_dpm_table->mclk_table.count-1].value != 0),
- "Divide by 0!",
- return -EINVAL);
- dpm_count = dpm_table->mclk_table.count < 2 ? 0 : dpm_table->mclk_table.count - 2;
- for (i = dpm_count; i > 1; i--) {
- if (golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value < mclk) {
- clock_percent = ((mclk -
- golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value) * 100)
- / golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value;
-
- dpm_table->mclk_table.dpm_levels[i].value =
- golden_dpm_table->mclk_table.dpm_levels[i].value +
- (golden_dpm_table->mclk_table.dpm_levels[i].value *
- clock_percent) / 100;
-
- } else if (golden_dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value > mclk) {
- clock_percent = (
- (golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value - mclk)
- * 100)
- / golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value;
-
- dpm_table->mclk_table.dpm_levels[i].value =
- golden_dpm_table->mclk_table.dpm_levels[i].value -
- (golden_dpm_table->mclk_table.dpm_levels[i].value *
- clock_percent) / 100;
- } else
- dpm_table->mclk_table.dpm_levels[i].value =
- golden_dpm_table->mclk_table.dpm_levels[i].value;
- }
+ if (hwmgr->od_enabled && data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
+ for (count = 0; count < dpm_table->mclk_table.count; count++) {
+ dpm_table->mclk_table.dpm_levels[count].enabled = odn_mclk_table->entries[count].enabled;
+ dpm_table->mclk_table.dpm_levels[count].value = odn_mclk_table->entries[count].clock;
}
}
@@ -3748,7 +3789,7 @@ static int smu7_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
return -EINVAL);
}
- data->need_update_smu7_dpm_table = 0;
+ data->need_update_smu7_dpm_table &= DPMTABLE_OD_UPDATE_VDDC;
return 0;
}
@@ -3776,12 +3817,14 @@ static int smu7_notify_link_speed_change_after_state_change(
smu7_get_current_pcie_speed(hwmgr) > 0)
return 0;
- if (acpi_pcie_perf_request(hwmgr->device, request, false)) {
+#ifdef CONFIG_ACPI
+ if (amdgpu_acpi_pcie_performance_request(hwmgr->adev, request, false)) {
if (PP_PCIEGen2 == target_link_speed)
pr_info("PSPP request to switch to Gen2 from Gen3 Failed!");
else
pr_info("PSPP request to switch to Gen1 from Gen2 Failed!");
}
+#endif
}
return 0;
@@ -3825,6 +3868,11 @@ static int smu7_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
"Failed to populate and upload SCLK MCLK DPM levels!",
result = tmp_result);
+ tmp_result = smu7_update_avfs(hwmgr);
+ PP_ASSERT_WITH_CODE((0 == tmp_result),
+ "Failed to update avfs voltages!",
+ result = tmp_result);
+
tmp_result = smu7_generate_dpm_level_enable_mask(hwmgr, input);
PP_ASSERT_WITH_CODE((0 == tmp_result),
"Failed to generate DPM level enabled mask!",
@@ -4016,6 +4064,7 @@ static int smu7_check_states_equal(struct pp_hwmgr *hwmgr,
const struct smu7_power_state *psa;
const struct smu7_power_state *psb;
int i;
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
if (pstate1 == NULL || pstate2 == NULL || equal == NULL)
return -EINVAL;
@@ -4040,6 +4089,10 @@ static int smu7_check_states_equal(struct pp_hwmgr *hwmgr,
*equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk));
*equal &= ((psa->vce_clks.evclk == psb->vce_clks.evclk) && (psa->vce_clks.ecclk == psb->vce_clks.ecclk));
*equal &= (psa->sclk_threshold == psb->sclk_threshold);
+ /* For OD call, set value based on flag */
+ *equal &= !(data->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK |
+ DPMTABLE_OD_UPDATE_MCLK |
+ DPMTABLE_OD_UPDATE_VDDC));
return 0;
}
@@ -4211,9 +4264,7 @@ static int smu7_force_clock_level(struct pp_hwmgr *hwmgr,
{
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- if (hwmgr->request_dpm_level & (AMD_DPM_FORCED_LEVEL_AUTO |
- AMD_DPM_FORCED_LEVEL_LOW |
- AMD_DPM_FORCED_LEVEL_HIGH))
+ if (mask == 0)
return -EINVAL;
switch (type) {
@@ -4232,15 +4283,15 @@ static int smu7_force_clock_level(struct pp_hwmgr *hwmgr,
case PP_PCIE:
{
uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask;
- uint32_t level = 0;
- while (tmp >>= 1)
- level++;
-
- if (!data->pcie_dpm_key_disabled)
- smum_send_msg_to_smc_with_parameter(hwmgr,
+ if (!data->pcie_dpm_key_disabled) {
+ if (fls(tmp) != ffs(tmp))
+ smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PCIeDPM_UnForceLevel);
+ else
+ smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_PCIeDPM_ForceLevel,
- level);
+ fls(tmp) - 1);
+ }
break;
}
default:
@@ -4257,6 +4308,9 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr,
struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
struct smu7_single_dpm_table *pcie_table = &(data->dpm_table.pcie_speed_table);
+ struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table);
+ struct phm_odn_clock_levels *odn_sclk_table = &(odn_table->odn_core_clock_dpm_levels);
+ struct phm_odn_clock_levels *odn_mclk_table = &(odn_table->odn_memory_clock_dpm_levels);
int i, now, size = 0;
uint32_t clock, pcie_speed;
@@ -4309,6 +4363,24 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr,
(pcie_table->dpm_levels[i].value == 2) ? "8.0GT/s, x16" : "",
(i == now) ? "*" : "");
break;
+ case OD_SCLK:
+ if (hwmgr->od_enabled) {
+ size = sprintf(buf, "%s: \n", "OD_SCLK");
+ for (i = 0; i < odn_sclk_table->num_of_pl; i++)
+ size += sprintf(buf + size, "%d: %10uMhz %10u mV\n",
+ i, odn_sclk_table->entries[i].clock / 100,
+ odn_sclk_table->entries[i].vddc);
+ }
+ break;
+ case OD_MCLK:
+ if (hwmgr->od_enabled) {
+ size = sprintf(buf, "%s: \n", "OD_MCLK");
+ for (i = 0; i < odn_mclk_table->num_of_pl; i++)
+ size += sprintf(buf + size, "%d: %10uMhz %10u mV\n",
+ i, odn_mclk_table->entries[i].clock / 100,
+ odn_mclk_table->entries[i].vddc);
+ }
+ break;
default:
break;
}
@@ -4506,110 +4578,6 @@ static int smu7_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type
return 0;
}
-static void smu7_find_min_clock_masks(struct pp_hwmgr *hwmgr,
- uint32_t *sclk_mask, uint32_t *mclk_mask,
- uint32_t min_sclk, uint32_t min_mclk)
-{
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- struct smu7_dpm_table *dpm_table = &(data->dpm_table);
- uint32_t i;
-
- for (i = 0; i < dpm_table->sclk_table.count; i++) {
- if (dpm_table->sclk_table.dpm_levels[i].enabled &&
- dpm_table->sclk_table.dpm_levels[i].value >= min_sclk)
- *sclk_mask |= 1 << i;
- }
-
- for (i = 0; i < dpm_table->mclk_table.count; i++) {
- if (dpm_table->mclk_table.dpm_levels[i].enabled &&
- dpm_table->mclk_table.dpm_levels[i].value >= min_mclk)
- *mclk_mask |= 1 << i;
- }
-}
-
-static int smu7_set_power_profile_state(struct pp_hwmgr *hwmgr,
- struct amd_pp_profile *request)
-{
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- int tmp_result, result = 0;
- uint32_t sclk_mask = 0, mclk_mask = 0;
-
- if (hwmgr->chip_id == CHIP_FIJI) {
- if (request->type == AMD_PP_GFX_PROFILE)
- smu7_enable_power_containment(hwmgr);
- else if (request->type == AMD_PP_COMPUTE_PROFILE)
- smu7_disable_power_containment(hwmgr);
- }
-
- if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_AUTO)
- return -EINVAL;
-
- tmp_result = smu7_freeze_sclk_mclk_dpm(hwmgr);
- PP_ASSERT_WITH_CODE(!tmp_result,
- "Failed to freeze SCLK MCLK DPM!",
- result = tmp_result);
-
- tmp_result = smum_populate_requested_graphic_levels(hwmgr, request);
- PP_ASSERT_WITH_CODE(!tmp_result,
- "Failed to populate requested graphic levels!",
- result = tmp_result);
-
- tmp_result = smu7_unfreeze_sclk_mclk_dpm(hwmgr);
- PP_ASSERT_WITH_CODE(!tmp_result,
- "Failed to unfreeze SCLK MCLK DPM!",
- result = tmp_result);
-
- smu7_find_min_clock_masks(hwmgr, &sclk_mask, &mclk_mask,
- request->min_sclk, request->min_mclk);
-
- if (sclk_mask) {
- if (!data->sclk_dpm_key_disabled)
- smum_send_msg_to_smc_with_parameter(hwmgr,
- PPSMC_MSG_SCLKDPM_SetEnabledMask,
- data->dpm_level_enable_mask.
- sclk_dpm_enable_mask &
- sclk_mask);
- }
-
- if (mclk_mask) {
- if (!data->mclk_dpm_key_disabled)
- smum_send_msg_to_smc_with_parameter(hwmgr,
- PPSMC_MSG_MCLKDPM_SetEnabledMask,
- data->dpm_level_enable_mask.
- mclk_dpm_enable_mask &
- mclk_mask);
- }
-
- return result;
-}
-
-static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable)
-{
- struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
-
- if (smu_data == NULL)
- return -EINVAL;
-
- if (smu_data->avfs.avfs_btc_status == AVFS_BTC_NOTSUPPORTED)
- return 0;
-
- if (enable) {
- if (!PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
- CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON))
- PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
- hwmgr, PPSMC_MSG_EnableAvfs),
- "Failed to enable AVFS!",
- return -EINVAL);
- } else if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
- CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON))
- PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
- hwmgr, PPSMC_MSG_DisableAvfs),
- "Failed to disable AVFS!",
- return -EINVAL);
-
- return 0;
-}
-
static int smu7_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
uint32_t virtual_addr_low,
uint32_t virtual_addr_hi,
@@ -4670,6 +4638,344 @@ static int smu7_get_max_high_clocks(struct pp_hwmgr *hwmgr,
return 0;
}
+static int smu7_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
+ struct PP_TemperatureRange *thermal_data)
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct phm_ppt_v1_information *table_info =
+ (struct phm_ppt_v1_information *)hwmgr->pptable;
+
+ memcpy(thermal_data, &SMU7ThermalPolicy[0], sizeof(struct PP_TemperatureRange));
+
+ if (hwmgr->pp_table_version == PP_TABLE_V1)
+ thermal_data->max = table_info->cac_dtp_table->usSoftwareShutdownTemp *
+ PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
+ else if (hwmgr->pp_table_version == PP_TABLE_V0)
+ thermal_data->max = data->thermal_temp_setting.temperature_shutdown *
+ PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
+
+ return 0;
+}
+
+static bool smu7_check_clk_voltage_valid(struct pp_hwmgr *hwmgr,
+ enum PP_OD_DPM_TABLE_COMMAND type,
+ uint32_t clk,
+ uint32_t voltage)
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+
+ struct phm_ppt_v1_information *table_info =
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
+ uint32_t min_vddc;
+ struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table;
+
+ if (table_info == NULL)
+ return false;
+
+ dep_sclk_table = table_info->vdd_dep_on_sclk;
+ min_vddc = dep_sclk_table->entries[0].vddc;
+
+ if (voltage < min_vddc || voltage > 2000) {
+ pr_info("OD voltage is out of range [%d - 2000] mV\n", min_vddc);
+ return false;
+ }
+
+ if (type == PP_OD_EDIT_SCLK_VDDC_TABLE) {
+ if (data->vbios_boot_state.sclk_bootup_value > clk ||
+ hwmgr->platform_descriptor.overdriveLimit.engineClock < clk) {
+ pr_info("OD engine clock is out of range [%d - %d] MHz\n",
+ data->vbios_boot_state.sclk_bootup_value,
+ hwmgr->platform_descriptor.overdriveLimit.engineClock / 100);
+ return false;
+ }
+ } else if (type == PP_OD_EDIT_MCLK_VDDC_TABLE) {
+ if (data->vbios_boot_state.mclk_bootup_value > clk ||
+ hwmgr->platform_descriptor.overdriveLimit.memoryClock < clk) {
+ pr_info("OD memory clock is out of range [%d - %d] MHz\n",
+ data->vbios_boot_state.mclk_bootup_value/100,
+ hwmgr->platform_descriptor.overdriveLimit.memoryClock / 100);
+ return false;
+ }
+ } else {
+ return false;
+ }
+
+ return true;
+}
+
+static void smu7_check_dpm_table_updated(struct pp_hwmgr *hwmgr)
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table);
+ struct phm_ppt_v1_information *table_info =
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
+ uint32_t i;
+
+ struct phm_ppt_v1_clock_voltage_dependency_table *dep_table;
+ struct phm_ppt_v1_clock_voltage_dependency_table *odn_dep_table;
+
+ if (table_info == NULL)
+ return;
+
+ for (i=0; i<data->dpm_table.sclk_table.count; i++) {
+ if (odn_table->odn_core_clock_dpm_levels.entries[i].clock !=
+ data->dpm_table.sclk_table.dpm_levels[i].value) {
+ data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
+ break;
+ }
+ }
+
+ for (i=0; i<data->dpm_table.sclk_table.count; i++) {
+ if (odn_table->odn_memory_clock_dpm_levels.entries[i].clock !=
+ data->dpm_table.mclk_table.dpm_levels[i].value) {
+ data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
+ break;
+ }
+ }
+
+ dep_table = table_info->vdd_dep_on_mclk;
+ odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_mclk);
+
+ for (i=0; i < dep_table->count; i++) {
+ if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) {
+ data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC;
+ break;
+ }
+ }
+ if (i == dep_table->count)
+ data->need_update_smu7_dpm_table &= ~DPMTABLE_OD_UPDATE_VDDC;
+
+ dep_table = table_info->vdd_dep_on_sclk;
+ odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_sclk);
+ for (i=0; i < dep_table->count; i++) {
+ if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) {
+ data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC;
+ break;
+ }
+ }
+ if (i == dep_table->count)
+ data->need_update_smu7_dpm_table &= ~DPMTABLE_OD_UPDATE_VDDC;
+}
+
+static int smu7_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
+ enum PP_OD_DPM_TABLE_COMMAND type,
+ long *input, uint32_t size)
+{
+ uint32_t i;
+ struct phm_odn_clock_levels *podn_dpm_table_in_backend = NULL;
+ struct smu7_odn_clock_voltage_dependency_table *podn_vdd_dep_in_backend = NULL;
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+
+ uint32_t input_clk;
+ uint32_t input_vol;
+ uint32_t input_level;
+
+ PP_ASSERT_WITH_CODE(input, "NULL user input for clock and voltage",
+ return -EINVAL);
+
+ if (!hwmgr->od_enabled) {
+ pr_info("OverDrive feature not enabled\n");
+ return -EINVAL;
+ }
+
+ if (PP_OD_EDIT_SCLK_VDDC_TABLE == type) {
+ podn_dpm_table_in_backend = &data->odn_dpm_table.odn_core_clock_dpm_levels;
+ podn_vdd_dep_in_backend = &data->odn_dpm_table.vdd_dependency_on_sclk;
+ PP_ASSERT_WITH_CODE((podn_dpm_table_in_backend && podn_vdd_dep_in_backend),
+ "Failed to get ODN SCLK and Voltage tables",
+ return -EINVAL);
+ } else if (PP_OD_EDIT_MCLK_VDDC_TABLE == type) {
+ podn_dpm_table_in_backend = &data->odn_dpm_table.odn_memory_clock_dpm_levels;
+ podn_vdd_dep_in_backend = &data->odn_dpm_table.vdd_dependency_on_mclk;
+
+ PP_ASSERT_WITH_CODE((podn_dpm_table_in_backend && podn_vdd_dep_in_backend),
+ "Failed to get ODN MCLK and Voltage tables",
+ return -EINVAL);
+ } else if (PP_OD_RESTORE_DEFAULT_TABLE == type) {
+ smu7_odn_initial_default_setting(hwmgr);
+ return 0;
+ } else if (PP_OD_COMMIT_DPM_TABLE == type) {
+ smu7_check_dpm_table_updated(hwmgr);
+ return 0;
+ } else {
+ return -EINVAL;
+ }
+
+ for (i = 0; i < size; i += 3) {
+ if (i + 3 > size || input[i] >= podn_dpm_table_in_backend->num_of_pl) {
+ pr_info("invalid clock voltage input \n");
+ return 0;
+ }
+ input_level = input[i];
+ input_clk = input[i+1] * 100;
+ input_vol = input[i+2];
+
+ if (smu7_check_clk_voltage_valid(hwmgr, type, input_clk, input_vol)) {
+ podn_dpm_table_in_backend->entries[input_level].clock = input_clk;
+ podn_vdd_dep_in_backend->entries[input_level].clk = input_clk;
+ podn_dpm_table_in_backend->entries[input_level].vddc = input_vol;
+ podn_vdd_dep_in_backend->entries[input_level].vddc = input_vol;
+ } else {
+ return -EINVAL;
+ }
+ }
+
+ return 0;
+}
+
+static int smu7_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ uint32_t i, size = 0;
+ uint32_t len;
+
+ static const char *profile_name[6] = {"3D_FULL_SCREEN",
+ "POWER_SAVING",
+ "VIDEO",
+ "VR",
+ "COMPUTE",
+ "CUSTOM"};
+
+ static const char *title[8] = {"NUM",
+ "MODE_NAME",
+ "SCLK_UP_HYST",
+ "SCLK_DOWN_HYST",
+ "SCLK_ACTIVE_LEVEL",
+ "MCLK_UP_HYST",
+ "MCLK_DOWN_HYST",
+ "MCLK_ACTIVE_LEVEL"};
+
+ if (!buf)
+ return -EINVAL;
+
+ size += sprintf(buf + size, "%s %16s %16s %16s %16s %16s %16s %16s\n",
+ title[0], title[1], title[2], title[3],
+ title[4], title[5], title[6], title[7]);
+
+ len = sizeof(smu7_profiling) / sizeof(struct profile_mode_setting);
+
+ for (i = 0; i < len; i++) {
+ if (smu7_profiling[i].bupdate_sclk)
+ size += sprintf(buf + size, "%3d %16s: %8d %16d %16d ",
+ i, profile_name[i], smu7_profiling[i].sclk_up_hyst,
+ smu7_profiling[i].sclk_down_hyst,
+ smu7_profiling[i].sclk_activity);
+ else
+ size += sprintf(buf + size, "%3d %16s: %8s %16s %16s ",
+ i, profile_name[i], "-", "-", "-");
+
+ if (smu7_profiling[i].bupdate_mclk)
+ size += sprintf(buf + size, "%16d %16d %16d\n",
+ smu7_profiling[i].mclk_up_hyst,
+ smu7_profiling[i].mclk_down_hyst,
+ smu7_profiling[i].mclk_activity);
+ else
+ size += sprintf(buf + size, "%16s %16s %16s\n",
+ "-", "-", "-");
+ }
+
+ size += sprintf(buf + size, "%3d %16s: %8d %16d %16d %16d %16d %16d\n",
+ i, profile_name[i],
+ data->custom_profile_setting.sclk_up_hyst,
+ data->custom_profile_setting.sclk_down_hyst,
+ data->custom_profile_setting.sclk_activity,
+ data->custom_profile_setting.mclk_up_hyst,
+ data->custom_profile_setting.mclk_down_hyst,
+ data->custom_profile_setting.mclk_activity);
+
+ size += sprintf(buf + size, "%3s %16s: %8d %16d %16d %16d %16d %16d\n",
+ "*", "CURRENT",
+ data->current_profile_setting.sclk_up_hyst,
+ data->current_profile_setting.sclk_down_hyst,
+ data->current_profile_setting.sclk_activity,
+ data->current_profile_setting.mclk_up_hyst,
+ data->current_profile_setting.mclk_down_hyst,
+ data->current_profile_setting.mclk_activity);
+
+ return size;
+}
+
+static void smu7_patch_compute_profile_mode(struct pp_hwmgr *hwmgr,
+ enum PP_SMC_POWER_PROFILE requst)
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ uint32_t tmp, level;
+
+ if (requst == PP_SMC_POWER_PROFILE_COMPUTE) {
+ if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
+ level = 0;
+ tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
+ while (tmp >>= 1)
+ level++;
+ if (level > 0)
+ smu7_force_clock_level(hwmgr, PP_SCLK, 3 << (level-1));
+ }
+ } else if (hwmgr->power_profile_mode == PP_SMC_POWER_PROFILE_COMPUTE) {
+ smu7_force_clock_level(hwmgr, PP_SCLK, data->dpm_level_enable_mask.sclk_dpm_enable_mask);
+ }
+}
+
+static int smu7_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size)
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct profile_mode_setting tmp;
+ enum PP_SMC_POWER_PROFILE mode;
+
+ if (input == NULL)
+ return -EINVAL;
+
+ mode = input[size];
+ switch (mode) {
+ case PP_SMC_POWER_PROFILE_CUSTOM:
+ if (size < 8)
+ return -EINVAL;
+
+ data->custom_profile_setting.bupdate_sclk = input[0];
+ data->custom_profile_setting.sclk_up_hyst = input[1];
+ data->custom_profile_setting.sclk_down_hyst = input[2];
+ data->custom_profile_setting.sclk_activity = input[3];
+ data->custom_profile_setting.bupdate_mclk = input[4];
+ data->custom_profile_setting.mclk_up_hyst = input[5];
+ data->custom_profile_setting.mclk_down_hyst = input[6];
+ data->custom_profile_setting.mclk_activity = input[7];
+ if (!smum_update_dpm_settings(hwmgr, &data->custom_profile_setting)) {
+ memcpy(&data->current_profile_setting, &data->custom_profile_setting, sizeof(struct profile_mode_setting));
+ hwmgr->power_profile_mode = mode;
+ }
+ break;
+ case PP_SMC_POWER_PROFILE_FULLSCREEN3D:
+ case PP_SMC_POWER_PROFILE_POWERSAVING:
+ case PP_SMC_POWER_PROFILE_VIDEO:
+ case PP_SMC_POWER_PROFILE_VR:
+ case PP_SMC_POWER_PROFILE_COMPUTE:
+ if (mode == hwmgr->power_profile_mode)
+ return 0;
+
+ memcpy(&tmp, &smu7_profiling[mode], sizeof(struct profile_mode_setting));
+ if (!smum_update_dpm_settings(hwmgr, &tmp)) {
+ if (tmp.bupdate_sclk) {
+ data->current_profile_setting.bupdate_sclk = tmp.bupdate_sclk;
+ data->current_profile_setting.sclk_up_hyst = tmp.sclk_up_hyst;
+ data->current_profile_setting.sclk_down_hyst = tmp.sclk_down_hyst;
+ data->current_profile_setting.sclk_activity = tmp.sclk_activity;
+ }
+ if (tmp.bupdate_mclk) {
+ data->current_profile_setting.bupdate_mclk = tmp.bupdate_mclk;
+ data->current_profile_setting.mclk_up_hyst = tmp.mclk_up_hyst;
+ data->current_profile_setting.mclk_down_hyst = tmp.mclk_down_hyst;
+ data->current_profile_setting.mclk_activity = tmp.mclk_activity;
+ }
+ smu7_patch_compute_profile_mode(hwmgr, mode);
+ hwmgr->power_profile_mode = mode;
+ }
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
static const struct pp_hwmgr_func smu7_hwmgr_funcs = {
.backend_init = &smu7_hwmgr_backend_init,
.backend_fini = &smu7_hwmgr_backend_fini,
@@ -4693,7 +4999,6 @@ static const struct pp_hwmgr_func smu7_hwmgr_funcs = {
.display_config_changed = smu7_display_configuration_changed_task,
.set_max_fan_pwm_output = smu7_set_max_fan_pwm_output,
.set_max_fan_rpm_output = smu7_set_max_fan_rpm_output,
- .get_temperature = smu7_thermal_get_temperature,
.stop_thermal_controller = smu7_thermal_stop_thermal_controller,
.get_fan_speed_info = smu7_fan_ctrl_get_fan_speed_info,
.get_fan_speed_percent = smu7_fan_ctrl_get_fan_speed_percent,
@@ -4717,12 +5022,16 @@ static const struct pp_hwmgr_func smu7_hwmgr_funcs = {
.get_clock_by_type = smu7_get_clock_by_type,
.read_sensor = smu7_read_sensor,
.dynamic_state_management_disable = smu7_disable_dpm_tasks,
- .set_power_profile_state = smu7_set_power_profile_state,
.avfs_control = smu7_avfs_control,
.disable_smc_firmware_ctf = smu7_thermal_disable_alert,
.start_thermal_controller = smu7_start_thermal_controller,
.notify_cac_buffer_info = smu7_notify_cac_buffer_info,
.get_max_high_clocks = smu7_get_max_high_clocks,
+ .get_thermal_temperature_range = smu7_get_thermal_temperature_range,
+ .odn_edit_dpm_table = smu7_odn_edit_dpm_table,
+ .set_power_limit = smu7_set_power_limit,
+ .get_power_profile_mode = smu7_get_power_profile_mode,
+ .set_power_profile_mode = smu7_set_power_profile_mode,
};
uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock,
@@ -4754,4 +5063,3 @@ int smu7_init_function_pointers(struct pp_hwmgr *hwmgr)
return ret;
}
-
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h
index e021154aedbd..3bcfc61cd5a2 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h
@@ -34,11 +34,6 @@
#define SMU7_VOLTAGE_CONTROL_BY_SVID2 0x2
#define SMU7_VOLTAGE_CONTROL_MERGED 0x3
-#define DPMTABLE_OD_UPDATE_SCLK 0x00000001
-#define DPMTABLE_OD_UPDATE_MCLK 0x00000002
-#define DPMTABLE_UPDATE_SCLK 0x00000004
-#define DPMTABLE_UPDATE_MCLK 0x00000008
-
enum gpu_pt_config_reg_type {
GPU_CONFIGREG_MMR = 0,
GPU_CONFIGREG_SMC_IND,
@@ -178,9 +173,34 @@ struct smu7_pcie_perf_range {
uint16_t min;
};
+struct smu7_odn_clock_voltage_dependency_table {
+ uint32_t count;
+ phm_ppt_v1_clock_voltage_dependency_record entries[MAX_REGULAR_DPM_NUMBER];
+};
+
+struct smu7_odn_dpm_table {
+ struct phm_odn_clock_levels odn_core_clock_dpm_levels;
+ struct phm_odn_clock_levels odn_memory_clock_dpm_levels;
+ struct smu7_odn_clock_voltage_dependency_table vdd_dependency_on_sclk;
+ struct smu7_odn_clock_voltage_dependency_table vdd_dependency_on_mclk;
+ uint32_t odn_mclk_min_limit;
+};
+
+struct profile_mode_setting {
+ uint8_t bupdate_sclk;
+ uint8_t sclk_up_hyst;
+ uint8_t sclk_down_hyst;
+ uint16_t sclk_activity;
+ uint8_t bupdate_mclk;
+ uint8_t mclk_up_hyst;
+ uint8_t mclk_down_hyst;
+ uint16_t mclk_activity;
+};
+
struct smu7_hwmgr {
struct smu7_dpm_table dpm_table;
struct smu7_dpm_table golden_dpm_table;
+ struct smu7_odn_dpm_table odn_dpm_table;
uint32_t voting_rights_clients[8];
uint32_t static_screen_threshold_unit;
@@ -280,7 +300,6 @@ struct smu7_hwmgr {
struct smu7_pcie_perf_range pcie_lane_power_saving;
bool use_pcie_performance_levels;
bool use_pcie_power_saving_levels;
- uint32_t mclk_activity_target;
uint32_t mclk_dpm0_activity_target;
uint32_t low_sclk_interrupt_threshold;
uint32_t last_mclk_dpm_enable_mask;
@@ -305,6 +324,9 @@ struct smu7_hwmgr {
uint32_t frame_time_x2;
uint16_t mem_latency_high;
uint16_t mem_latency_low;
+ uint32_t vr_config;
+ struct profile_mode_setting custom_profile_setting;
+ struct profile_mode_setting current_profile_setting;
};
/* To convert to Q8.8 format for firmware */
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
index 85ca16abb626..03bc7453f3b1 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
@@ -731,14 +731,9 @@ int smu7_enable_didt_config(struct pp_hwmgr *hwmgr)
int result;
uint32_t num_se = 0;
uint32_t count, value, value2;
- struct cgs_system_info sys_info = {0};
+ struct amdgpu_device *adev = hwmgr->adev;
- sys_info.size = sizeof(struct cgs_system_info);
- sys_info.info_id = CGS_SYSTEM_INFO_GFX_SE_INFO;
- result = cgs_query_system_info(hwmgr->device, &sys_info);
-
- if (result == 0)
- num_se = sys_info.value;
+ num_se = adev->gfx.config.max_shader_engines;
if (PP_CAP(PHM_PlatformCaps_SQRamping) ||
PP_CAP(PHM_PlatformCaps_DBRamping) ||
@@ -857,6 +852,8 @@ int smu7_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n)
{
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ n = (n & 0xff) << 8;
+
if (data->power_containment_features &
POWERCONTAINMENT_FEATURE_PkgPwrLimit)
return smum_send_msg_to_smc_with_parameter(hwmgr,
@@ -903,12 +900,12 @@ int smu7_enable_power_containment(struct pp_hwmgr *hwmgr)
PP_ASSERT_WITH_CODE((0 == smc_result),
"Failed to enable PkgPwrTracking in SMC.", result = -1;);
if (0 == smc_result) {
- uint32_t default_limit =
- (uint32_t)(cac_table->usMaximumPowerDeliveryLimit * 256);
+ hwmgr->default_power_limit = hwmgr->power_limit =
+ cac_table->usMaximumPowerDeliveryLimit;
data->power_containment_features |=
POWERCONTAINMENT_FEATURE_PkgPwrLimit;
- if (smu7_set_power_limit(hwmgr, default_limit))
+ if (smu7_set_power_limit(hwmgr, hwmgr->power_limit))
pr_err("Failed to set Default Power Limit in SMC!");
}
}
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c
index d7aa643cdb51..f6573ed0357d 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c
@@ -310,9 +310,9 @@ int smu7_thermal_get_temperature(struct pp_hwmgr *hwmgr)
static int smu7_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
uint32_t low_temp, uint32_t high_temp)
{
- uint32_t low = SMU7_THERMAL_MINIMUM_ALERT_TEMP *
+ int low = SMU7_THERMAL_MINIMUM_ALERT_TEMP *
PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
- uint32_t high = SMU7_THERMAL_MAXIMUM_ALERT_TEMP *
+ int high = SMU7_THERMAL_MAXIMUM_ALERT_TEMP *
PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
if (low < low_temp)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
index b314d09d41af..75a465f771f0 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
@@ -35,9 +35,9 @@
#include "hwmgr.h"
#include "hardwaremanager.h"
#include "cz_ppsmc.h"
-#include "cz_hwmgr.h"
+#include "smu8_hwmgr.h"
#include "power_state.h"
-#include "cz_clockpowergating.h"
+#include "pp_thermal.h"
#define ixSMUSVI_NB_CURRENTVID 0xD8230044
#define CURRENT_NB_VID_MASK 0xff000000
@@ -46,26 +46,26 @@
#define CURRENT_GFX_VID_MASK 0xff000000
#define CURRENT_GFX_VID__SHIFT 24
-static const unsigned long PhwCz_Magic = (unsigned long) PHM_Cz_Magic;
+static const unsigned long smu8_magic = (unsigned long) PHM_Cz_Magic;
-static struct cz_power_state *cast_PhwCzPowerState(struct pp_hw_power_state *hw_ps)
+static struct smu8_power_state *cast_smu8_power_state(struct pp_hw_power_state *hw_ps)
{
- if (PhwCz_Magic != hw_ps->magic)
+ if (smu8_magic != hw_ps->magic)
return NULL;
- return (struct cz_power_state *)hw_ps;
+ return (struct smu8_power_state *)hw_ps;
}
-static const struct cz_power_state *cast_const_PhwCzPowerState(
+static const struct smu8_power_state *cast_const_smu8_power_state(
const struct pp_hw_power_state *hw_ps)
{
- if (PhwCz_Magic != hw_ps->magic)
+ if (smu8_magic != hw_ps->magic)
return NULL;
- return (struct cz_power_state *)hw_ps;
+ return (struct smu8_power_state *)hw_ps;
}
-static uint32_t cz_get_eclk_level(struct pp_hwmgr *hwmgr,
+static uint32_t smu8_get_eclk_level(struct pp_hwmgr *hwmgr,
uint32_t clock, uint32_t msg)
{
int i = 0;
@@ -96,7 +96,7 @@ static uint32_t cz_get_eclk_level(struct pp_hwmgr *hwmgr,
return i;
}
-static uint32_t cz_get_sclk_level(struct pp_hwmgr *hwmgr,
+static uint32_t smu8_get_sclk_level(struct pp_hwmgr *hwmgr,
uint32_t clock, uint32_t msg)
{
int i = 0;
@@ -126,7 +126,7 @@ static uint32_t cz_get_sclk_level(struct pp_hwmgr *hwmgr,
return i;
}
-static uint32_t cz_get_uvd_level(struct pp_hwmgr *hwmgr,
+static uint32_t smu8_get_uvd_level(struct pp_hwmgr *hwmgr,
uint32_t clock, uint32_t msg)
{
int i = 0;
@@ -157,47 +157,42 @@ static uint32_t cz_get_uvd_level(struct pp_hwmgr *hwmgr,
return i;
}
-static uint32_t cz_get_max_sclk_level(struct pp_hwmgr *hwmgr)
+static uint32_t smu8_get_max_sclk_level(struct pp_hwmgr *hwmgr)
{
- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
+ struct smu8_hwmgr *data = hwmgr->backend;
- if (cz_hwmgr->max_sclk_level == 0) {
+ if (data->max_sclk_level == 0) {
smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxSclkLevel);
- cz_hwmgr->max_sclk_level = smum_get_argument(hwmgr) + 1;
+ data->max_sclk_level = smum_get_argument(hwmgr) + 1;
}
- return cz_hwmgr->max_sclk_level;
+ return data->max_sclk_level;
}
-static int cz_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
+static int smu8_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
{
- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
- uint32_t i;
- struct cgs_system_info sys_info = {0};
- int result;
+ struct smu8_hwmgr *data = hwmgr->backend;
+ struct amdgpu_device *adev = hwmgr->adev;
- cz_hwmgr->gfx_ramp_step = 256*25/100;
- cz_hwmgr->gfx_ramp_delay = 1; /* by default, we delay 1us */
-
- for (i = 0; i < CZ_MAX_HARDWARE_POWERLEVELS; i++)
- cz_hwmgr->activity_target[i] = CZ_AT_DFLT;
-
- cz_hwmgr->mgcg_cgtt_local0 = 0x00000000;
- cz_hwmgr->mgcg_cgtt_local1 = 0x00000000;
- cz_hwmgr->clock_slow_down_freq = 25000;
- cz_hwmgr->skip_clock_slow_down = 1;
- cz_hwmgr->enable_nb_ps_policy = 1; /* disable until UNB is ready, Enabled */
- cz_hwmgr->voltage_drop_in_dce_power_gating = 0; /* disable until fully verified */
- cz_hwmgr->voting_rights_clients = 0x00C00033;
- cz_hwmgr->static_screen_threshold = 8;
- cz_hwmgr->ddi_power_gating_disabled = 0;
- cz_hwmgr->bapm_enabled = 1;
- cz_hwmgr->voltage_drop_threshold = 0;
- cz_hwmgr->gfx_power_gating_threshold = 500;
- cz_hwmgr->vce_slow_sclk_threshold = 20000;
- cz_hwmgr->dce_slow_sclk_threshold = 30000;
- cz_hwmgr->disable_driver_thermal_policy = 1;
- cz_hwmgr->disable_nb_ps3_in_battery = 0;
+ data->gfx_ramp_step = 256*25/100;
+ data->gfx_ramp_delay = 1; /* by default, we delay 1us */
+
+ data->mgcg_cgtt_local0 = 0x00000000;
+ data->mgcg_cgtt_local1 = 0x00000000;
+ data->clock_slow_down_freq = 25000;
+ data->skip_clock_slow_down = 1;
+ data->enable_nb_ps_policy = 1; /* disable until UNB is ready, Enabled */
+ data->voltage_drop_in_dce_power_gating = 0; /* disable until fully verified */
+ data->voting_rights_clients = 0x00C00033;
+ data->static_screen_threshold = 8;
+ data->ddi_power_gating_disabled = 0;
+ data->bapm_enabled = 1;
+ data->voltage_drop_threshold = 0;
+ data->gfx_power_gating_threshold = 500;
+ data->vce_slow_sclk_threshold = 20000;
+ data->dce_slow_sclk_threshold = 30000;
+ data->disable_driver_thermal_policy = 1;
+ data->disable_nb_ps3_in_battery = 0;
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_ABM);
@@ -208,14 +203,14 @@ static int cz_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_DynamicM3Arbiter);
- cz_hwmgr->override_dynamic_mgpg = 1;
+ data->override_dynamic_mgpg = 1;
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_DynamicPatchPowerState);
- cz_hwmgr->thermal_auto_throttling_treshold = 0;
- cz_hwmgr->tdr_clock = 0;
- cz_hwmgr->disable_gfx_power_gating_in_uvd = 0;
+ data->thermal_auto_throttling_treshold = 0;
+ data->tdr_clock = 0;
+ data->disable_gfx_power_gating_in_uvd = 0;
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_DynamicUVDState);
@@ -225,10 +220,10 @@ static int cz_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_VCEDPM);
- cz_hwmgr->cc6_settings.cpu_cc6_disable = false;
- cz_hwmgr->cc6_settings.cpu_pstate_disable = false;
- cz_hwmgr->cc6_settings.nb_pstate_switch_disable = false;
- cz_hwmgr->cc6_settings.cpu_pstate_separation_time = 0;
+ data->cc6_settings.cpu_cc6_disable = false;
+ data->cc6_settings.cpu_pstate_disable = false;
+ data->cc6_settings.nb_pstate_switch_disable = false;
+ data->cc6_settings.cpu_pstate_separation_time = 0;
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_DisableVoltageIsland);
@@ -237,45 +232,42 @@ static int cz_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
PHM_PlatformCaps_UVDPowerGating);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_VCEPowerGating);
- sys_info.size = sizeof(struct cgs_system_info);
- sys_info.info_id = CGS_SYSTEM_INFO_PG_FLAGS;
- result = cgs_query_system_info(hwmgr->device, &sys_info);
- if (!result) {
- if (sys_info.value & AMD_PG_SUPPORT_UVD)
- phm_cap_set(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_UVDPowerGating);
- if (sys_info.value & AMD_PG_SUPPORT_VCE)
- phm_cap_set(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_VCEPowerGating);
- }
+
+ if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
+ phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_UVDPowerGating);
+ if (adev->pg_flags & AMD_PG_SUPPORT_VCE)
+ phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_VCEPowerGating);
+
return 0;
}
-static uint32_t cz_convert_8Bit_index_to_voltage(
+static uint32_t smu8_convert_8Bit_index_to_voltage(
struct pp_hwmgr *hwmgr, uint16_t voltage)
{
return 6200 - (voltage * 25);
}
-static int cz_construct_max_power_limits_table(struct pp_hwmgr *hwmgr,
+static int smu8_construct_max_power_limits_table(struct pp_hwmgr *hwmgr,
struct phm_clock_and_voltage_limits *table)
{
- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)hwmgr->backend;
- struct cz_sys_info *sys_info = &cz_hwmgr->sys_info;
+ struct smu8_hwmgr *data = hwmgr->backend;
+ struct smu8_sys_info *sys_info = &data->sys_info;
struct phm_clock_voltage_dependency_table *dep_table =
hwmgr->dyn_state.vddc_dependency_on_sclk;
if (dep_table->count > 0) {
table->sclk = dep_table->entries[dep_table->count-1].clk;
- table->vddc = cz_convert_8Bit_index_to_voltage(hwmgr,
+ table->vddc = smu8_convert_8Bit_index_to_voltage(hwmgr,
(uint16_t)dep_table->entries[dep_table->count-1].v);
}
table->mclk = sys_info->nbp_memory_clock[0];
return 0;
}
-static int cz_init_dynamic_state_adjustment_rule_settings(
+static int smu8_init_dynamic_state_adjustment_rule_settings(
struct pp_hwmgr *hwmgr,
ATOM_CLK_VOLT_CAPABILITY *disp_voltage_table)
{
@@ -313,9 +305,9 @@ static int cz_init_dynamic_state_adjustment_rule_settings(
return 0;
}
-static int cz_get_system_info_data(struct pp_hwmgr *hwmgr)
+static int smu8_get_system_info_data(struct pp_hwmgr *hwmgr)
{
- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)hwmgr->backend;
+ struct smu8_hwmgr *data = hwmgr->backend;
ATOM_INTEGRATED_SYSTEM_INFO_V1_9 *info = NULL;
uint32_t i;
int result = 0;
@@ -337,67 +329,67 @@ static int cz_get_system_info_data(struct pp_hwmgr *hwmgr)
return -EINVAL;
}
- cz_hwmgr->sys_info.bootup_uma_clock =
+ data->sys_info.bootup_uma_clock =
le32_to_cpu(info->ulBootUpUMAClock);
- cz_hwmgr->sys_info.bootup_engine_clock =
+ data->sys_info.bootup_engine_clock =
le32_to_cpu(info->ulBootUpEngineClock);
- cz_hwmgr->sys_info.dentist_vco_freq =
+ data->sys_info.dentist_vco_freq =
le32_to_cpu(info->ulDentistVCOFreq);
- cz_hwmgr->sys_info.system_config =
+ data->sys_info.system_config =
le32_to_cpu(info->ulSystemConfig);
- cz_hwmgr->sys_info.bootup_nb_voltage_index =
+ data->sys_info.bootup_nb_voltage_index =
le16_to_cpu(info->usBootUpNBVoltage);
- cz_hwmgr->sys_info.htc_hyst_lmt =
+ data->sys_info.htc_hyst_lmt =
(info->ucHtcHystLmt == 0) ? 5 : info->ucHtcHystLmt;
- cz_hwmgr->sys_info.htc_tmp_lmt =
+ data->sys_info.htc_tmp_lmt =
(info->ucHtcTmpLmt == 0) ? 203 : info->ucHtcTmpLmt;
- if (cz_hwmgr->sys_info.htc_tmp_lmt <=
- cz_hwmgr->sys_info.htc_hyst_lmt) {
+ if (data->sys_info.htc_tmp_lmt <=
+ data->sys_info.htc_hyst_lmt) {
pr_err("The htcTmpLmt should be larger than htcHystLmt.\n");
return -EINVAL;
}
- cz_hwmgr->sys_info.nb_dpm_enable =
- cz_hwmgr->enable_nb_ps_policy &&
+ data->sys_info.nb_dpm_enable =
+ data->enable_nb_ps_policy &&
(le32_to_cpu(info->ulSystemConfig) >> 3 & 0x1);
- for (i = 0; i < CZ_NUM_NBPSTATES; i++) {
- if (i < CZ_NUM_NBPMEMORYCLOCK) {
- cz_hwmgr->sys_info.nbp_memory_clock[i] =
+ for (i = 0; i < SMU8_NUM_NBPSTATES; i++) {
+ if (i < SMU8_NUM_NBPMEMORYCLOCK) {
+ data->sys_info.nbp_memory_clock[i] =
le32_to_cpu(info->ulNbpStateMemclkFreq[i]);
}
- cz_hwmgr->sys_info.nbp_n_clock[i] =
+ data->sys_info.nbp_n_clock[i] =
le32_to_cpu(info->ulNbpStateNClkFreq[i]);
}
for (i = 0; i < MAX_DISPLAY_CLOCK_LEVEL; i++) {
- cz_hwmgr->sys_info.display_clock[i] =
+ data->sys_info.display_clock[i] =
le32_to_cpu(info->sDispClkVoltageMapping[i].ulMaximumSupportedCLK);
}
/* Here use 4 levels, make sure not exceed */
- for (i = 0; i < CZ_NUM_NBPSTATES; i++) {
- cz_hwmgr->sys_info.nbp_voltage_index[i] =
+ for (i = 0; i < SMU8_NUM_NBPSTATES; i++) {
+ data->sys_info.nbp_voltage_index[i] =
le16_to_cpu(info->usNBPStateVoltage[i]);
}
- if (!cz_hwmgr->sys_info.nb_dpm_enable) {
- for (i = 1; i < CZ_NUM_NBPSTATES; i++) {
- if (i < CZ_NUM_NBPMEMORYCLOCK) {
- cz_hwmgr->sys_info.nbp_memory_clock[i] =
- cz_hwmgr->sys_info.nbp_memory_clock[0];
+ if (!data->sys_info.nb_dpm_enable) {
+ for (i = 1; i < SMU8_NUM_NBPSTATES; i++) {
+ if (i < SMU8_NUM_NBPMEMORYCLOCK) {
+ data->sys_info.nbp_memory_clock[i] =
+ data->sys_info.nbp_memory_clock[0];
}
- cz_hwmgr->sys_info.nbp_n_clock[i] =
- cz_hwmgr->sys_info.nbp_n_clock[0];
- cz_hwmgr->sys_info.nbp_voltage_index[i] =
- cz_hwmgr->sys_info.nbp_voltage_index[0];
+ data->sys_info.nbp_n_clock[i] =
+ data->sys_info.nbp_n_clock[0];
+ data->sys_info.nbp_voltage_index[i] =
+ data->sys_info.nbp_voltage_index[0];
}
}
@@ -407,40 +399,40 @@ static int cz_get_system_info_data(struct pp_hwmgr *hwmgr)
PHM_PlatformCaps_EnableDFSBypass);
}
- cz_hwmgr->sys_info.uma_channel_number = info->ucUMAChannelNumber;
+ data->sys_info.uma_channel_number = info->ucUMAChannelNumber;
- cz_construct_max_power_limits_table (hwmgr,
+ smu8_construct_max_power_limits_table (hwmgr,
&hwmgr->dyn_state.max_clock_voltage_on_ac);
- cz_init_dynamic_state_adjustment_rule_settings(hwmgr,
+ smu8_init_dynamic_state_adjustment_rule_settings(hwmgr,
&info->sDISPCLK_Voltage[0]);
return result;
}
-static int cz_construct_boot_state(struct pp_hwmgr *hwmgr)
+static int smu8_construct_boot_state(struct pp_hwmgr *hwmgr)
{
- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
+ struct smu8_hwmgr *data = hwmgr->backend;
- cz_hwmgr->boot_power_level.engineClock =
- cz_hwmgr->sys_info.bootup_engine_clock;
+ data->boot_power_level.engineClock =
+ data->sys_info.bootup_engine_clock;
- cz_hwmgr->boot_power_level.vddcIndex =
- (uint8_t)cz_hwmgr->sys_info.bootup_nb_voltage_index;
+ data->boot_power_level.vddcIndex =
+ (uint8_t)data->sys_info.bootup_nb_voltage_index;
- cz_hwmgr->boot_power_level.dsDividerIndex = 0;
- cz_hwmgr->boot_power_level.ssDividerIndex = 0;
- cz_hwmgr->boot_power_level.allowGnbSlow = 1;
- cz_hwmgr->boot_power_level.forceNBPstate = 0;
- cz_hwmgr->boot_power_level.hysteresis_up = 0;
- cz_hwmgr->boot_power_level.numSIMDToPowerDown = 0;
- cz_hwmgr->boot_power_level.display_wm = 0;
- cz_hwmgr->boot_power_level.vce_wm = 0;
+ data->boot_power_level.dsDividerIndex = 0;
+ data->boot_power_level.ssDividerIndex = 0;
+ data->boot_power_level.allowGnbSlow = 1;
+ data->boot_power_level.forceNBPstate = 0;
+ data->boot_power_level.hysteresis_up = 0;
+ data->boot_power_level.numSIMDToPowerDown = 0;
+ data->boot_power_level.display_wm = 0;
+ data->boot_power_level.vce_wm = 0;
return 0;
}
-static int cz_upload_pptable_to_smu(struct pp_hwmgr *hwmgr)
+static int smu8_upload_pptable_to_smu(struct pp_hwmgr *hwmgr)
{
struct SMU8_Fusion_ClkTable *clock_table;
int ret;
@@ -470,18 +462,18 @@ static int cz_upload_pptable_to_smu(struct pp_hwmgr *hwmgr)
clock_table = (struct SMU8_Fusion_ClkTable *)table;
/* patch clock table */
- PP_ASSERT_WITH_CODE((vddc_table->count <= CZ_MAX_HARDWARE_POWERLEVELS),
+ PP_ASSERT_WITH_CODE((vddc_table->count <= SMU8_MAX_HARDWARE_POWERLEVELS),
"Dependency table entry exceeds max limit!", return -EINVAL;);
- PP_ASSERT_WITH_CODE((vdd_gfx_table->count <= CZ_MAX_HARDWARE_POWERLEVELS),
+ PP_ASSERT_WITH_CODE((vdd_gfx_table->count <= SMU8_MAX_HARDWARE_POWERLEVELS),
"Dependency table entry exceeds max limit!", return -EINVAL;);
- PP_ASSERT_WITH_CODE((acp_table->count <= CZ_MAX_HARDWARE_POWERLEVELS),
+ PP_ASSERT_WITH_CODE((acp_table->count <= SMU8_MAX_HARDWARE_POWERLEVELS),
"Dependency table entry exceeds max limit!", return -EINVAL;);
- PP_ASSERT_WITH_CODE((uvd_table->count <= CZ_MAX_HARDWARE_POWERLEVELS),
+ PP_ASSERT_WITH_CODE((uvd_table->count <= SMU8_MAX_HARDWARE_POWERLEVELS),
"Dependency table entry exceeds max limit!", return -EINVAL;);
- PP_ASSERT_WITH_CODE((vce_table->count <= CZ_MAX_HARDWARE_POWERLEVELS),
+ PP_ASSERT_WITH_CODE((vce_table->count <= SMU8_MAX_HARDWARE_POWERLEVELS),
"Dependency table entry exceeds max limit!", return -EINVAL;);
- for (i = 0; i < CZ_MAX_HARDWARE_POWERLEVELS; i++) {
+ for (i = 0; i < SMU8_MAX_HARDWARE_POWERLEVELS; i++) {
/* vddc_sclk */
clock_table->SclkBreakdownTable.ClkLevel[i].GnbVid =
@@ -559,9 +551,9 @@ static int cz_upload_pptable_to_smu(struct pp_hwmgr *hwmgr)
return ret;
}
-static int cz_init_sclk_limit(struct pp_hwmgr *hwmgr)
+static int smu8_init_sclk_limit(struct pp_hwmgr *hwmgr)
{
- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
+ struct smu8_hwmgr *data = hwmgr->backend;
struct phm_clock_voltage_dependency_table *table =
hwmgr->dyn_state.vddc_dependency_on_sclk;
unsigned long clock = 0, level;
@@ -569,25 +561,25 @@ static int cz_init_sclk_limit(struct pp_hwmgr *hwmgr)
if (NULL == table || table->count <= 0)
return -EINVAL;
- cz_hwmgr->sclk_dpm.soft_min_clk = table->entries[0].clk;
- cz_hwmgr->sclk_dpm.hard_min_clk = table->entries[0].clk;
+ data->sclk_dpm.soft_min_clk = table->entries[0].clk;
+ data->sclk_dpm.hard_min_clk = table->entries[0].clk;
- level = cz_get_max_sclk_level(hwmgr) - 1;
+ level = smu8_get_max_sclk_level(hwmgr) - 1;
if (level < table->count)
clock = table->entries[level].clk;
else
clock = table->entries[table->count - 1].clk;
- cz_hwmgr->sclk_dpm.soft_max_clk = clock;
- cz_hwmgr->sclk_dpm.hard_max_clk = clock;
+ data->sclk_dpm.soft_max_clk = clock;
+ data->sclk_dpm.hard_max_clk = clock;
return 0;
}
-static int cz_init_uvd_limit(struct pp_hwmgr *hwmgr)
+static int smu8_init_uvd_limit(struct pp_hwmgr *hwmgr)
{
- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
+ struct smu8_hwmgr *data = hwmgr->backend;
struct phm_uvd_clock_voltage_dependency_table *table =
hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
unsigned long clock = 0, level;
@@ -595,8 +587,8 @@ static int cz_init_uvd_limit(struct pp_hwmgr *hwmgr)
if (NULL == table || table->count <= 0)
return -EINVAL;
- cz_hwmgr->uvd_dpm.soft_min_clk = 0;
- cz_hwmgr->uvd_dpm.hard_min_clk = 0;
+ data->uvd_dpm.soft_min_clk = 0;
+ data->uvd_dpm.hard_min_clk = 0;
smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxUvdLevel);
level = smum_get_argument(hwmgr);
@@ -606,15 +598,15 @@ static int cz_init_uvd_limit(struct pp_hwmgr *hwmgr)
else
clock = table->entries[table->count - 1].vclk;
- cz_hwmgr->uvd_dpm.soft_max_clk = clock;
- cz_hwmgr->uvd_dpm.hard_max_clk = clock;
+ data->uvd_dpm.soft_max_clk = clock;
+ data->uvd_dpm.hard_max_clk = clock;
return 0;
}
-static int cz_init_vce_limit(struct pp_hwmgr *hwmgr)
+static int smu8_init_vce_limit(struct pp_hwmgr *hwmgr)
{
- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
+ struct smu8_hwmgr *data = hwmgr->backend;
struct phm_vce_clock_voltage_dependency_table *table =
hwmgr->dyn_state.vce_clock_voltage_dependency_table;
unsigned long clock = 0, level;
@@ -622,8 +614,8 @@ static int cz_init_vce_limit(struct pp_hwmgr *hwmgr)
if (NULL == table || table->count <= 0)
return -EINVAL;
- cz_hwmgr->vce_dpm.soft_min_clk = 0;
- cz_hwmgr->vce_dpm.hard_min_clk = 0;
+ data->vce_dpm.soft_min_clk = 0;
+ data->vce_dpm.hard_min_clk = 0;
smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxEclkLevel);
level = smum_get_argument(hwmgr);
@@ -633,15 +625,15 @@ static int cz_init_vce_limit(struct pp_hwmgr *hwmgr)
else
clock = table->entries[table->count - 1].ecclk;
- cz_hwmgr->vce_dpm.soft_max_clk = clock;
- cz_hwmgr->vce_dpm.hard_max_clk = clock;
+ data->vce_dpm.soft_max_clk = clock;
+ data->vce_dpm.hard_max_clk = clock;
return 0;
}
-static int cz_init_acp_limit(struct pp_hwmgr *hwmgr)
+static int smu8_init_acp_limit(struct pp_hwmgr *hwmgr)
{
- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
+ struct smu8_hwmgr *data = hwmgr->backend;
struct phm_acp_clock_voltage_dependency_table *table =
hwmgr->dyn_state.acp_clock_voltage_dependency_table;
unsigned long clock = 0, level;
@@ -649,8 +641,8 @@ static int cz_init_acp_limit(struct pp_hwmgr *hwmgr)
if (NULL == table || table->count <= 0)
return -EINVAL;
- cz_hwmgr->acp_dpm.soft_min_clk = 0;
- cz_hwmgr->acp_dpm.hard_min_clk = 0;
+ data->acp_dpm.soft_min_clk = 0;
+ data->acp_dpm.hard_min_clk = 0;
smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxAclkLevel);
level = smum_get_argument(hwmgr);
@@ -660,32 +652,32 @@ static int cz_init_acp_limit(struct pp_hwmgr *hwmgr)
else
clock = table->entries[table->count - 1].acpclk;
- cz_hwmgr->acp_dpm.soft_max_clk = clock;
- cz_hwmgr->acp_dpm.hard_max_clk = clock;
+ data->acp_dpm.soft_max_clk = clock;
+ data->acp_dpm.hard_max_clk = clock;
return 0;
}
-static void cz_init_power_gate_state(struct pp_hwmgr *hwmgr)
+static void smu8_init_power_gate_state(struct pp_hwmgr *hwmgr)
{
- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
+ struct smu8_hwmgr *data = hwmgr->backend;
- cz_hwmgr->uvd_power_gated = false;
- cz_hwmgr->vce_power_gated = false;
- cz_hwmgr->samu_power_gated = false;
- cz_hwmgr->acp_power_gated = false;
- cz_hwmgr->pgacpinit = true;
+ data->uvd_power_gated = false;
+ data->vce_power_gated = false;
+ data->samu_power_gated = false;
+ data->acp_power_gated = false;
+ data->pgacpinit = true;
}
-static void cz_init_sclk_threshold(struct pp_hwmgr *hwmgr)
+static void smu8_init_sclk_threshold(struct pp_hwmgr *hwmgr)
{
- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
+ struct smu8_hwmgr *data = hwmgr->backend;
- cz_hwmgr->low_sclk_interrupt_threshold = 0;
+ data->low_sclk_interrupt_threshold = 0;
}
-static int cz_update_sclk_limit(struct pp_hwmgr *hwmgr)
+static int smu8_update_sclk_limit(struct pp_hwmgr *hwmgr)
{
- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
+ struct smu8_hwmgr *data = hwmgr->backend;
struct phm_clock_voltage_dependency_table *table =
hwmgr->dyn_state.vddc_dependency_on_sclk;
@@ -694,29 +686,29 @@ static int cz_update_sclk_limit(struct pp_hwmgr *hwmgr)
unsigned long stable_pstate_sclk;
unsigned long percentage;
- cz_hwmgr->sclk_dpm.soft_min_clk = table->entries[0].clk;
- level = cz_get_max_sclk_level(hwmgr) - 1;
+ data->sclk_dpm.soft_min_clk = table->entries[0].clk;
+ level = smu8_get_max_sclk_level(hwmgr) - 1;
if (level < table->count)
- cz_hwmgr->sclk_dpm.soft_max_clk = table->entries[level].clk;
+ data->sclk_dpm.soft_max_clk = table->entries[level].clk;
else
- cz_hwmgr->sclk_dpm.soft_max_clk = table->entries[table->count - 1].clk;
+ data->sclk_dpm.soft_max_clk = table->entries[table->count - 1].clk;
clock = hwmgr->display_config.min_core_set_clock;
if (clock == 0)
pr_debug("min_core_set_clock not set\n");
- if (cz_hwmgr->sclk_dpm.hard_min_clk != clock) {
- cz_hwmgr->sclk_dpm.hard_min_clk = clock;
+ if (data->sclk_dpm.hard_min_clk != clock) {
+ data->sclk_dpm.hard_min_clk = clock;
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSclkHardMin,
- cz_get_sclk_level(hwmgr,
- cz_hwmgr->sclk_dpm.hard_min_clk,
+ smu8_get_sclk_level(hwmgr,
+ data->sclk_dpm.hard_min_clk,
PPSMC_MSG_SetSclkHardMin));
}
- clock = cz_hwmgr->sclk_dpm.soft_min_clk;
+ clock = data->sclk_dpm.soft_min_clk;
/* update minimum clocks for Stable P-State feature */
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
@@ -730,36 +722,36 @@ static int cz_update_sclk_limit(struct pp_hwmgr *hwmgr)
clock = stable_pstate_sclk;
}
- if (cz_hwmgr->sclk_dpm.soft_min_clk != clock) {
- cz_hwmgr->sclk_dpm.soft_min_clk = clock;
+ if (data->sclk_dpm.soft_min_clk != clock) {
+ data->sclk_dpm.soft_min_clk = clock;
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSclkSoftMin,
- cz_get_sclk_level(hwmgr,
- cz_hwmgr->sclk_dpm.soft_min_clk,
+ smu8_get_sclk_level(hwmgr,
+ data->sclk_dpm.soft_min_clk,
PPSMC_MSG_SetSclkSoftMin));
}
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_StablePState) &&
- cz_hwmgr->sclk_dpm.soft_max_clk != clock) {
- cz_hwmgr->sclk_dpm.soft_max_clk = clock;
+ data->sclk_dpm.soft_max_clk != clock) {
+ data->sclk_dpm.soft_max_clk = clock;
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSclkSoftMax,
- cz_get_sclk_level(hwmgr,
- cz_hwmgr->sclk_dpm.soft_max_clk,
+ smu8_get_sclk_level(hwmgr,
+ data->sclk_dpm.soft_max_clk,
PPSMC_MSG_SetSclkSoftMax));
}
return 0;
}
-static int cz_set_deep_sleep_sclk_threshold(struct pp_hwmgr *hwmgr)
+static int smu8_set_deep_sleep_sclk_threshold(struct pp_hwmgr *hwmgr)
{
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SclkDeepSleep)) {
uint32_t clks = hwmgr->display_config.min_core_set_clock_in_sr;
if (clks == 0)
- clks = CZ_MIN_DEEP_SLEEP_SCLK;
+ clks = SMU8_MIN_DEEP_SLEEP_SCLK;
PP_DBG_LOG("Setting Deep Sleep Clock: %d\n", clks);
@@ -771,21 +763,21 @@ static int cz_set_deep_sleep_sclk_threshold(struct pp_hwmgr *hwmgr)
return 0;
}
-static int cz_set_watermark_threshold(struct pp_hwmgr *hwmgr)
+static int smu8_set_watermark_threshold(struct pp_hwmgr *hwmgr)
{
- struct cz_hwmgr *cz_hwmgr =
- (struct cz_hwmgr *)(hwmgr->backend);
+ struct smu8_hwmgr *data =
+ hwmgr->backend;
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetWatermarkFrequency,
- cz_hwmgr->sclk_dpm.soft_max_clk);
+ data->sclk_dpm.soft_max_clk);
return 0;
}
-static int cz_nbdpm_pstate_enable_disable(struct pp_hwmgr *hwmgr, bool enable, bool lock)
+static int smu8_nbdpm_pstate_enable_disable(struct pp_hwmgr *hwmgr, bool enable, bool lock)
{
- struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
+ struct smu8_hwmgr *hw_data = hwmgr->backend;
if (hw_data->is_nb_dpm_enabled) {
if (enable) {
@@ -806,35 +798,35 @@ static int cz_nbdpm_pstate_enable_disable(struct pp_hwmgr *hwmgr, bool enable, b
return 0;
}
-static int cz_disable_nb_dpm(struct pp_hwmgr *hwmgr)
+static int smu8_disable_nb_dpm(struct pp_hwmgr *hwmgr)
{
int ret = 0;
- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
+ struct smu8_hwmgr *data = hwmgr->backend;
unsigned long dpm_features = 0;
- if (cz_hwmgr->is_nb_dpm_enabled) {
- cz_nbdpm_pstate_enable_disable(hwmgr, true, true);
+ if (data->is_nb_dpm_enabled) {
+ smu8_nbdpm_pstate_enable_disable(hwmgr, true, true);
dpm_features |= NB_DPM_MASK;
ret = smum_send_msg_to_smc_with_parameter(
hwmgr,
PPSMC_MSG_DisableAllSmuFeatures,
dpm_features);
if (ret == 0)
- cz_hwmgr->is_nb_dpm_enabled = false;
+ data->is_nb_dpm_enabled = false;
}
return ret;
}
-static int cz_enable_nb_dpm(struct pp_hwmgr *hwmgr)
+static int smu8_enable_nb_dpm(struct pp_hwmgr *hwmgr)
{
int ret = 0;
- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
+ struct smu8_hwmgr *data = hwmgr->backend;
unsigned long dpm_features = 0;
- if (!cz_hwmgr->is_nb_dpm_enabled) {
+ if (!data->is_nb_dpm_enabled) {
PP_DBG_LOG("enabling ALL SMU features.\n");
dpm_features |= NB_DPM_MASK;
ret = smum_send_msg_to_smc_with_parameter(
@@ -842,94 +834,94 @@ static int cz_enable_nb_dpm(struct pp_hwmgr *hwmgr)
PPSMC_MSG_EnableAllSmuFeatures,
dpm_features);
if (ret == 0)
- cz_hwmgr->is_nb_dpm_enabled = true;
+ data->is_nb_dpm_enabled = true;
}
return ret;
}
-static int cz_update_low_mem_pstate(struct pp_hwmgr *hwmgr, const void *input)
+static int smu8_update_low_mem_pstate(struct pp_hwmgr *hwmgr, const void *input)
{
bool disable_switch;
bool enable_low_mem_state;
- struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
+ struct smu8_hwmgr *hw_data = hwmgr->backend;
const struct phm_set_power_state_input *states = (struct phm_set_power_state_input *)input;
- const struct cz_power_state *pnew_state = cast_const_PhwCzPowerState(states->pnew_state);
+ const struct smu8_power_state *pnew_state = cast_const_smu8_power_state(states->pnew_state);
if (hw_data->sys_info.nb_dpm_enable) {
disable_switch = hw_data->cc6_settings.nb_pstate_switch_disable ? true : false;
enable_low_mem_state = hw_data->cc6_settings.nb_pstate_switch_disable ? false : true;
if (pnew_state->action == FORCE_HIGH)
- cz_nbdpm_pstate_enable_disable(hwmgr, false, disable_switch);
+ smu8_nbdpm_pstate_enable_disable(hwmgr, false, disable_switch);
else if (pnew_state->action == CANCEL_FORCE_HIGH)
- cz_nbdpm_pstate_enable_disable(hwmgr, true, disable_switch);
+ smu8_nbdpm_pstate_enable_disable(hwmgr, true, disable_switch);
else
- cz_nbdpm_pstate_enable_disable(hwmgr, enable_low_mem_state, disable_switch);
+ smu8_nbdpm_pstate_enable_disable(hwmgr, enable_low_mem_state, disable_switch);
}
return 0;
}
-static int cz_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
+static int smu8_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
{
int ret = 0;
- cz_update_sclk_limit(hwmgr);
- cz_set_deep_sleep_sclk_threshold(hwmgr);
- cz_set_watermark_threshold(hwmgr);
- ret = cz_enable_nb_dpm(hwmgr);
+ smu8_update_sclk_limit(hwmgr);
+ smu8_set_deep_sleep_sclk_threshold(hwmgr);
+ smu8_set_watermark_threshold(hwmgr);
+ ret = smu8_enable_nb_dpm(hwmgr);
if (ret)
return ret;
- cz_update_low_mem_pstate(hwmgr, input);
+ smu8_update_low_mem_pstate(hwmgr, input);
return 0;
};
-static int cz_setup_asic_task(struct pp_hwmgr *hwmgr)
+static int smu8_setup_asic_task(struct pp_hwmgr *hwmgr)
{
int ret;
- ret = cz_upload_pptable_to_smu(hwmgr);
+ ret = smu8_upload_pptable_to_smu(hwmgr);
if (ret)
return ret;
- ret = cz_init_sclk_limit(hwmgr);
+ ret = smu8_init_sclk_limit(hwmgr);
if (ret)
return ret;
- ret = cz_init_uvd_limit(hwmgr);
+ ret = smu8_init_uvd_limit(hwmgr);
if (ret)
return ret;
- ret = cz_init_vce_limit(hwmgr);
+ ret = smu8_init_vce_limit(hwmgr);
if (ret)
return ret;
- ret = cz_init_acp_limit(hwmgr);
+ ret = smu8_init_acp_limit(hwmgr);
if (ret)
return ret;
- cz_init_power_gate_state(hwmgr);
- cz_init_sclk_threshold(hwmgr);
+ smu8_init_power_gate_state(hwmgr);
+ smu8_init_sclk_threshold(hwmgr);
return 0;
}
-static void cz_power_up_display_clock_sys_pll(struct pp_hwmgr *hwmgr)
+static void smu8_power_up_display_clock_sys_pll(struct pp_hwmgr *hwmgr)
{
- struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
+ struct smu8_hwmgr *hw_data = hwmgr->backend;
hw_data->disp_clk_bypass_pending = false;
hw_data->disp_clk_bypass = false;
}
-static void cz_clear_nb_dpm_flag(struct pp_hwmgr *hwmgr)
+static void smu8_clear_nb_dpm_flag(struct pp_hwmgr *hwmgr)
{
- struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
+ struct smu8_hwmgr *hw_data = hwmgr->backend;
hw_data->is_nb_dpm_enabled = false;
}
-static void cz_reset_cc6_data(struct pp_hwmgr *hwmgr)
+static void smu8_reset_cc6_data(struct pp_hwmgr *hwmgr)
{
- struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
+ struct smu8_hwmgr *hw_data = hwmgr->backend;
hw_data->cc6_settings.cc6_setting_changed = false;
hw_data->cc6_settings.cpu_pstate_separation_time = 0;
@@ -937,45 +929,47 @@ static void cz_reset_cc6_data(struct pp_hwmgr *hwmgr)
hw_data->cc6_settings.cpu_pstate_disable = false;
}
-static int cz_power_off_asic(struct pp_hwmgr *hwmgr)
+static int smu8_power_off_asic(struct pp_hwmgr *hwmgr)
{
- cz_power_up_display_clock_sys_pll(hwmgr);
- cz_clear_nb_dpm_flag(hwmgr);
- cz_reset_cc6_data(hwmgr);
+ smu8_power_up_display_clock_sys_pll(hwmgr);
+ smu8_clear_nb_dpm_flag(hwmgr);
+ smu8_reset_cc6_data(hwmgr);
return 0;
};
-static void cz_program_voting_clients(struct pp_hwmgr *hwmgr)
+static void smu8_program_voting_clients(struct pp_hwmgr *hwmgr)
{
- PHMCZ_WRITE_SMC_REGISTER(hwmgr->device, CG_FREQ_TRAN_VOTING_0,
- PPCZ_VOTINGRIGHTSCLIENTS_DFLT0);
+ cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
+ ixCG_FREQ_TRAN_VOTING_0,
+ SMU8_VOTINGRIGHTSCLIENTS_DFLT0);
}
-static void cz_clear_voting_clients(struct pp_hwmgr *hwmgr)
+static void smu8_clear_voting_clients(struct pp_hwmgr *hwmgr)
{
- PHMCZ_WRITE_SMC_REGISTER(hwmgr->device, CG_FREQ_TRAN_VOTING_0, 0);
+ cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
+ ixCG_FREQ_TRAN_VOTING_0, 0);
}
-static int cz_start_dpm(struct pp_hwmgr *hwmgr)
+static int smu8_start_dpm(struct pp_hwmgr *hwmgr)
{
- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
+ struct smu8_hwmgr *data = hwmgr->backend;
- cz_hwmgr->dpm_flags |= DPMFlags_SCLK_Enabled;
+ data->dpm_flags |= DPMFlags_SCLK_Enabled;
return smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_EnableAllSmuFeatures,
SCLK_DPM_MASK);
}
-static int cz_stop_dpm(struct pp_hwmgr *hwmgr)
+static int smu8_stop_dpm(struct pp_hwmgr *hwmgr)
{
int ret = 0;
- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
+ struct smu8_hwmgr *data = hwmgr->backend;
unsigned long dpm_features = 0;
- if (cz_hwmgr->dpm_flags & DPMFlags_SCLK_Enabled) {
+ if (data->dpm_flags & DPMFlags_SCLK_Enabled) {
dpm_features |= SCLK_DPM_MASK;
- cz_hwmgr->dpm_flags &= ~DPMFlags_SCLK_Enabled;
+ data->dpm_flags &= ~DPMFlags_SCLK_Enabled;
ret = smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_DisableAllSmuFeatures,
dpm_features);
@@ -983,112 +977,80 @@ static int cz_stop_dpm(struct pp_hwmgr *hwmgr)
return ret;
}
-static int cz_program_bootup_state(struct pp_hwmgr *hwmgr)
+static int smu8_program_bootup_state(struct pp_hwmgr *hwmgr)
{
- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
+ struct smu8_hwmgr *data = hwmgr->backend;
- cz_hwmgr->sclk_dpm.soft_min_clk = cz_hwmgr->sys_info.bootup_engine_clock;
- cz_hwmgr->sclk_dpm.soft_max_clk = cz_hwmgr->sys_info.bootup_engine_clock;
+ data->sclk_dpm.soft_min_clk = data->sys_info.bootup_engine_clock;
+ data->sclk_dpm.soft_max_clk = data->sys_info.bootup_engine_clock;
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSclkSoftMin,
- cz_get_sclk_level(hwmgr,
- cz_hwmgr->sclk_dpm.soft_min_clk,
+ smu8_get_sclk_level(hwmgr,
+ data->sclk_dpm.soft_min_clk,
PPSMC_MSG_SetSclkSoftMin));
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSclkSoftMax,
- cz_get_sclk_level(hwmgr,
- cz_hwmgr->sclk_dpm.soft_max_clk,
+ smu8_get_sclk_level(hwmgr,
+ data->sclk_dpm.soft_max_clk,
PPSMC_MSG_SetSclkSoftMax));
return 0;
}
-static void cz_reset_acp_boot_level(struct pp_hwmgr *hwmgr)
+static void smu8_reset_acp_boot_level(struct pp_hwmgr *hwmgr)
{
- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
+ struct smu8_hwmgr *data = hwmgr->backend;
- cz_hwmgr->acp_boot_level = 0xff;
+ data->acp_boot_level = 0xff;
}
-static bool cz_dpm_check_smu_features(struct pp_hwmgr *hwmgr,
- unsigned long check_feature)
+static int smu8_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
{
- int result;
- unsigned long features;
-
- result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetFeatureStatus, 0);
- if (result == 0) {
- features = smum_get_argument(hwmgr);
- if (features & check_feature)
- return true;
- }
+ smu8_disable_nb_dpm(hwmgr);
- return false;
-}
-
-static bool cz_check_for_dpm_enabled(struct pp_hwmgr *hwmgr)
-{
- if (cz_dpm_check_smu_features(hwmgr, SMU_EnabledFeatureScoreboard_SclkDpmOn))
- return true;
- return false;
-}
-
-static int cz_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
-{
- if (!cz_check_for_dpm_enabled(hwmgr)) {
- pr_info("dpm has been disabled\n");
- return 0;
- }
- cz_disable_nb_dpm(hwmgr);
-
- cz_clear_voting_clients(hwmgr);
- if (cz_stop_dpm(hwmgr))
+ smu8_clear_voting_clients(hwmgr);
+ if (smu8_stop_dpm(hwmgr))
return -EINVAL;
return 0;
};
-static int cz_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
+static int smu8_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
{
- if (cz_check_for_dpm_enabled(hwmgr)) {
- pr_info("dpm has been enabled\n");
- return 0;
- }
-
- cz_program_voting_clients(hwmgr);
- if (cz_start_dpm(hwmgr))
+ smu8_program_voting_clients(hwmgr);
+ if (smu8_start_dpm(hwmgr))
return -EINVAL;
- cz_program_bootup_state(hwmgr);
- cz_reset_acp_boot_level(hwmgr);
+ smu8_program_bootup_state(hwmgr);
+ smu8_reset_acp_boot_level(hwmgr);
return 0;
};
-static int cz_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
+static int smu8_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
struct pp_power_state *prequest_ps,
const struct pp_power_state *pcurrent_ps)
{
- struct cz_power_state *cz_ps =
- cast_PhwCzPowerState(&prequest_ps->hardware);
+ struct smu8_power_state *smu8_ps =
+ cast_smu8_power_state(&prequest_ps->hardware);
- const struct cz_power_state *cz_current_ps =
- cast_const_PhwCzPowerState(&pcurrent_ps->hardware);
+ const struct smu8_power_state *smu8_current_ps =
+ cast_const_smu8_power_state(&pcurrent_ps->hardware);
- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
+ struct smu8_hwmgr *data = hwmgr->backend;
struct PP_Clocks clocks = {0, 0, 0, 0};
bool force_high;
uint32_t num_of_active_displays = 0;
struct cgs_display_info info = {0};
- cz_ps->need_dfs_bypass = true;
+ smu8_ps->need_dfs_bypass = true;
- cz_hwmgr->battery_state = (PP_StateUILabel_Battery == prequest_ps->classification.ui_label);
+ data->battery_state = (PP_StateUILabel_Battery == prequest_ps->classification.ui_label);
clocks.memoryClock = hwmgr->display_config.min_mem_set_clock != 0 ?
hwmgr->display_config.min_mem_set_clock :
- cz_hwmgr->sys_info.nbp_memory_clock[1];
+ data->sys_info.nbp_memory_clock[1];
cgs_get_active_displays_info(hwmgr->device, &info);
num_of_active_displays = info.display_count;
@@ -1096,56 +1058,56 @@ static int cz_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
clocks.memoryClock = hwmgr->dyn_state.max_clock_voltage_on_ac.mclk;
- force_high = (clocks.memoryClock > cz_hwmgr->sys_info.nbp_memory_clock[CZ_NUM_NBPMEMORYCLOCK - 1])
+ force_high = (clocks.memoryClock > data->sys_info.nbp_memory_clock[SMU8_NUM_NBPMEMORYCLOCK - 1])
|| (num_of_active_displays >= 3);
- cz_ps->action = cz_current_ps->action;
+ smu8_ps->action = smu8_current_ps->action;
if (hwmgr->request_dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
- cz_nbdpm_pstate_enable_disable(hwmgr, false, false);
+ smu8_nbdpm_pstate_enable_disable(hwmgr, false, false);
else if (hwmgr->request_dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD)
- cz_nbdpm_pstate_enable_disable(hwmgr, false, true);
- else if (!force_high && (cz_ps->action == FORCE_HIGH))
- cz_ps->action = CANCEL_FORCE_HIGH;
- else if (force_high && (cz_ps->action != FORCE_HIGH))
- cz_ps->action = FORCE_HIGH;
+ smu8_nbdpm_pstate_enable_disable(hwmgr, false, true);
+ else if (!force_high && (smu8_ps->action == FORCE_HIGH))
+ smu8_ps->action = CANCEL_FORCE_HIGH;
+ else if (force_high && (smu8_ps->action != FORCE_HIGH))
+ smu8_ps->action = FORCE_HIGH;
else
- cz_ps->action = DO_NOTHING;
+ smu8_ps->action = DO_NOTHING;
return 0;
}
-static int cz_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
+static int smu8_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
{
int result = 0;
- struct cz_hwmgr *data;
+ struct smu8_hwmgr *data;
- data = kzalloc(sizeof(struct cz_hwmgr), GFP_KERNEL);
+ data = kzalloc(sizeof(struct smu8_hwmgr), GFP_KERNEL);
if (data == NULL)
return -ENOMEM;
hwmgr->backend = data;
- result = cz_initialize_dpm_defaults(hwmgr);
+ result = smu8_initialize_dpm_defaults(hwmgr);
if (result != 0) {
- pr_err("cz_initialize_dpm_defaults failed\n");
+ pr_err("smu8_initialize_dpm_defaults failed\n");
return result;
}
- result = cz_get_system_info_data(hwmgr);
+ result = smu8_get_system_info_data(hwmgr);
if (result != 0) {
- pr_err("cz_get_system_info_data failed\n");
+ pr_err("smu8_get_system_info_data failed\n");
return result;
}
- cz_construct_boot_state(hwmgr);
+ smu8_construct_boot_state(hwmgr);
- hwmgr->platform_descriptor.hardwareActivityPerformanceLevels = CZ_MAX_HARDWARE_POWERLEVELS;
+ hwmgr->platform_descriptor.hardwareActivityPerformanceLevels = SMU8_MAX_HARDWARE_POWERLEVELS;
return result;
}
-static int cz_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
+static int smu8_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
{
if (hwmgr != NULL) {
kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
@@ -1157,28 +1119,28 @@ static int cz_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
return 0;
}
-static int cz_phm_force_dpm_highest(struct pp_hwmgr *hwmgr)
+static int smu8_phm_force_dpm_highest(struct pp_hwmgr *hwmgr)
{
- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
+ struct smu8_hwmgr *data = hwmgr->backend;
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSclkSoftMin,
- cz_get_sclk_level(hwmgr,
- cz_hwmgr->sclk_dpm.soft_max_clk,
+ smu8_get_sclk_level(hwmgr,
+ data->sclk_dpm.soft_max_clk,
PPSMC_MSG_SetSclkSoftMin));
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSclkSoftMax,
- cz_get_sclk_level(hwmgr,
- cz_hwmgr->sclk_dpm.soft_max_clk,
+ smu8_get_sclk_level(hwmgr,
+ data->sclk_dpm.soft_max_clk,
PPSMC_MSG_SetSclkSoftMax));
return 0;
}
-static int cz_phm_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
+static int smu8_phm_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
{
- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
+ struct smu8_hwmgr *data = hwmgr->backend;
struct phm_clock_voltage_dependency_table *table =
hwmgr->dyn_state.vddc_dependency_on_sclk;
unsigned long clock = 0, level;
@@ -1186,54 +1148,56 @@ static int cz_phm_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
if (NULL == table || table->count <= 0)
return -EINVAL;
- cz_hwmgr->sclk_dpm.soft_min_clk = table->entries[0].clk;
- cz_hwmgr->sclk_dpm.hard_min_clk = table->entries[0].clk;
+ data->sclk_dpm.soft_min_clk = table->entries[0].clk;
+ data->sclk_dpm.hard_min_clk = table->entries[0].clk;
+ hwmgr->pstate_sclk = table->entries[0].clk;
+ hwmgr->pstate_mclk = 0;
- level = cz_get_max_sclk_level(hwmgr) - 1;
+ level = smu8_get_max_sclk_level(hwmgr) - 1;
if (level < table->count)
clock = table->entries[level].clk;
else
clock = table->entries[table->count - 1].clk;
- cz_hwmgr->sclk_dpm.soft_max_clk = clock;
- cz_hwmgr->sclk_dpm.hard_max_clk = clock;
+ data->sclk_dpm.soft_max_clk = clock;
+ data->sclk_dpm.hard_max_clk = clock;
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSclkSoftMin,
- cz_get_sclk_level(hwmgr,
- cz_hwmgr->sclk_dpm.soft_min_clk,
+ smu8_get_sclk_level(hwmgr,
+ data->sclk_dpm.soft_min_clk,
PPSMC_MSG_SetSclkSoftMin));
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSclkSoftMax,
- cz_get_sclk_level(hwmgr,
- cz_hwmgr->sclk_dpm.soft_max_clk,
+ smu8_get_sclk_level(hwmgr,
+ data->sclk_dpm.soft_max_clk,
PPSMC_MSG_SetSclkSoftMax));
return 0;
}
-static int cz_phm_force_dpm_lowest(struct pp_hwmgr *hwmgr)
+static int smu8_phm_force_dpm_lowest(struct pp_hwmgr *hwmgr)
{
- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
+ struct smu8_hwmgr *data = hwmgr->backend;
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSclkSoftMax,
- cz_get_sclk_level(hwmgr,
- cz_hwmgr->sclk_dpm.soft_min_clk,
+ smu8_get_sclk_level(hwmgr,
+ data->sclk_dpm.soft_min_clk,
PPSMC_MSG_SetSclkSoftMax));
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSclkSoftMin,
- cz_get_sclk_level(hwmgr,
- cz_hwmgr->sclk_dpm.soft_min_clk,
+ smu8_get_sclk_level(hwmgr,
+ data->sclk_dpm.soft_min_clk,
PPSMC_MSG_SetSclkSoftMin));
return 0;
}
-static int cz_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
+static int smu8_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
enum amd_dpm_forced_level level)
{
int ret = 0;
@@ -1241,15 +1205,15 @@ static int cz_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
switch (level) {
case AMD_DPM_FORCED_LEVEL_HIGH:
case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
- ret = cz_phm_force_dpm_highest(hwmgr);
+ ret = smu8_phm_force_dpm_highest(hwmgr);
break;
case AMD_DPM_FORCED_LEVEL_LOW:
case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
- ret = cz_phm_force_dpm_lowest(hwmgr);
+ ret = smu8_phm_force_dpm_lowest(hwmgr);
break;
case AMD_DPM_FORCED_LEVEL_AUTO:
- ret = cz_phm_unforce_dpm_levels(hwmgr);
+ ret = smu8_phm_unforce_dpm_levels(hwmgr);
break;
case AMD_DPM_FORCED_LEVEL_MANUAL:
case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
@@ -1260,14 +1224,14 @@ static int cz_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
return ret;
}
-int cz_dpm_powerdown_uvd(struct pp_hwmgr *hwmgr)
+static int smu8_dpm_powerdown_uvd(struct pp_hwmgr *hwmgr)
{
if (PP_CAP(PHM_PlatformCaps_UVDPowerGating))
return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_UVDPowerOFF);
return 0;
}
-int cz_dpm_powerup_uvd(struct pp_hwmgr *hwmgr)
+static int smu8_dpm_powerup_uvd(struct pp_hwmgr *hwmgr)
{
if (PP_CAP(PHM_PlatformCaps_UVDPowerGating)) {
return smum_send_msg_to_smc_with_parameter(
@@ -1279,52 +1243,22 @@ int cz_dpm_powerup_uvd(struct pp_hwmgr *hwmgr)
return 0;
}
-int cz_dpm_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
-{
- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
- struct phm_uvd_clock_voltage_dependency_table *ptable =
- hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
-
- if (!bgate) {
- /* Stable Pstate is enabled and we need to set the UVD DPM to highest level */
- if (PP_CAP(PHM_PlatformCaps_StablePState) ||
- hwmgr->en_umd_pstate) {
- cz_hwmgr->uvd_dpm.hard_min_clk =
- ptable->entries[ptable->count - 1].vclk;
-
- smum_send_msg_to_smc_with_parameter(hwmgr,
- PPSMC_MSG_SetUvdHardMin,
- cz_get_uvd_level(hwmgr,
- cz_hwmgr->uvd_dpm.hard_min_clk,
- PPSMC_MSG_SetUvdHardMin));
-
- cz_enable_disable_uvd_dpm(hwmgr, true);
- } else {
- cz_enable_disable_uvd_dpm(hwmgr, true);
- }
- } else {
- cz_enable_disable_uvd_dpm(hwmgr, false);
- }
-
- return 0;
-}
-
-int cz_dpm_update_vce_dpm(struct pp_hwmgr *hwmgr)
+static int smu8_dpm_update_vce_dpm(struct pp_hwmgr *hwmgr)
{
- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
+ struct smu8_hwmgr *data = hwmgr->backend;
struct phm_vce_clock_voltage_dependency_table *ptable =
hwmgr->dyn_state.vce_clock_voltage_dependency_table;
/* Stable Pstate is enabled and we need to set the VCE DPM to highest level */
if (PP_CAP(PHM_PlatformCaps_StablePState) ||
hwmgr->en_umd_pstate) {
- cz_hwmgr->vce_dpm.hard_min_clk =
+ data->vce_dpm.hard_min_clk =
ptable->entries[ptable->count - 1].ecclk;
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetEclkHardMin,
- cz_get_eclk_level(hwmgr,
- cz_hwmgr->vce_dpm.hard_min_clk,
+ smu8_get_eclk_level(hwmgr,
+ data->vce_dpm.hard_min_clk,
PPSMC_MSG_SetEclkHardMin));
} else {
@@ -1338,7 +1272,7 @@ int cz_dpm_update_vce_dpm(struct pp_hwmgr *hwmgr)
return 0;
}
-int cz_dpm_powerdown_vce(struct pp_hwmgr *hwmgr)
+static int smu8_dpm_powerdown_vce(struct pp_hwmgr *hwmgr)
{
if (PP_CAP(PHM_PlatformCaps_VCEPowerGating))
return smum_send_msg_to_smc(hwmgr,
@@ -1346,7 +1280,7 @@ int cz_dpm_powerdown_vce(struct pp_hwmgr *hwmgr)
return 0;
}
-int cz_dpm_powerup_vce(struct pp_hwmgr *hwmgr)
+static int smu8_dpm_powerup_vce(struct pp_hwmgr *hwmgr)
{
if (PP_CAP(PHM_PlatformCaps_VCEPowerGating))
return smum_send_msg_to_smc(hwmgr,
@@ -1354,17 +1288,17 @@ int cz_dpm_powerup_vce(struct pp_hwmgr *hwmgr)
return 0;
}
-static uint32_t cz_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
+static uint32_t smu8_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
{
- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
+ struct smu8_hwmgr *data = hwmgr->backend;
- return cz_hwmgr->sys_info.bootup_uma_clock;
+ return data->sys_info.bootup_uma_clock;
}
-static uint32_t cz_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
+static uint32_t smu8_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
{
struct pp_power_state *ps;
- struct cz_power_state *cz_ps;
+ struct smu8_power_state *smu8_ps;
if (hwmgr == NULL)
return -EINVAL;
@@ -1374,59 +1308,59 @@ static uint32_t cz_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
if (ps == NULL)
return -EINVAL;
- cz_ps = cast_PhwCzPowerState(&ps->hardware);
+ smu8_ps = cast_smu8_power_state(&ps->hardware);
if (low)
- return cz_ps->levels[0].engineClock;
+ return smu8_ps->levels[0].engineClock;
else
- return cz_ps->levels[cz_ps->level-1].engineClock;
+ return smu8_ps->levels[smu8_ps->level-1].engineClock;
}
-static int cz_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
+static int smu8_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
struct pp_hw_power_state *hw_ps)
{
- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
- struct cz_power_state *cz_ps = cast_PhwCzPowerState(hw_ps);
+ struct smu8_hwmgr *data = hwmgr->backend;
+ struct smu8_power_state *smu8_ps = cast_smu8_power_state(hw_ps);
- cz_ps->level = 1;
- cz_ps->nbps_flags = 0;
- cz_ps->bapm_flags = 0;
- cz_ps->levels[0] = cz_hwmgr->boot_power_level;
+ smu8_ps->level = 1;
+ smu8_ps->nbps_flags = 0;
+ smu8_ps->bapm_flags = 0;
+ smu8_ps->levels[0] = data->boot_power_level;
return 0;
}
-static int cz_dpm_get_pp_table_entry_callback(
+static int smu8_dpm_get_pp_table_entry_callback(
struct pp_hwmgr *hwmgr,
struct pp_hw_power_state *hw_ps,
unsigned int index,
const void *clock_info)
{
- struct cz_power_state *cz_ps = cast_PhwCzPowerState(hw_ps);
+ struct smu8_power_state *smu8_ps = cast_smu8_power_state(hw_ps);
- const ATOM_PPLIB_CZ_CLOCK_INFO *cz_clock_info = clock_info;
+ const ATOM_PPLIB_CZ_CLOCK_INFO *smu8_clock_info = clock_info;
struct phm_clock_voltage_dependency_table *table =
hwmgr->dyn_state.vddc_dependency_on_sclk;
- uint8_t clock_info_index = cz_clock_info->index;
+ uint8_t clock_info_index = smu8_clock_info->index;
if (clock_info_index > (uint8_t)(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1))
clock_info_index = (uint8_t)(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1);
- cz_ps->levels[index].engineClock = table->entries[clock_info_index].clk;
- cz_ps->levels[index].vddcIndex = (uint8_t)table->entries[clock_info_index].v;
+ smu8_ps->levels[index].engineClock = table->entries[clock_info_index].clk;
+ smu8_ps->levels[index].vddcIndex = (uint8_t)table->entries[clock_info_index].v;
- cz_ps->level = index + 1;
+ smu8_ps->level = index + 1;
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
- cz_ps->levels[index].dsDividerIndex = 5;
- cz_ps->levels[index].ssDividerIndex = 5;
+ smu8_ps->levels[index].dsDividerIndex = 5;
+ smu8_ps->levels[index].ssDividerIndex = 5;
}
return 0;
}
-static int cz_dpm_get_num_of_pp_table_entries(struct pp_hwmgr *hwmgr)
+static int smu8_dpm_get_num_of_pp_table_entries(struct pp_hwmgr *hwmgr)
{
int result;
unsigned long ret = 0;
@@ -1436,31 +1370,31 @@ static int cz_dpm_get_num_of_pp_table_entries(struct pp_hwmgr *hwmgr)
return result ? 0 : ret;
}
-static int cz_dpm_get_pp_table_entry(struct pp_hwmgr *hwmgr,
+static int smu8_dpm_get_pp_table_entry(struct pp_hwmgr *hwmgr,
unsigned long entry, struct pp_power_state *ps)
{
int result;
- struct cz_power_state *cz_ps;
+ struct smu8_power_state *smu8_ps;
- ps->hardware.magic = PhwCz_Magic;
+ ps->hardware.magic = smu8_magic;
- cz_ps = cast_PhwCzPowerState(&(ps->hardware));
+ smu8_ps = cast_smu8_power_state(&(ps->hardware));
result = pp_tables_get_entry(hwmgr, entry, ps,
- cz_dpm_get_pp_table_entry_callback);
+ smu8_dpm_get_pp_table_entry_callback);
- cz_ps->uvd_clocks.vclk = ps->uvd_clocks.VCLK;
- cz_ps->uvd_clocks.dclk = ps->uvd_clocks.DCLK;
+ smu8_ps->uvd_clocks.vclk = ps->uvd_clocks.VCLK;
+ smu8_ps->uvd_clocks.dclk = ps->uvd_clocks.DCLK;
return result;
}
-static int cz_get_power_state_size(struct pp_hwmgr *hwmgr)
+static int smu8_get_power_state_size(struct pp_hwmgr *hwmgr)
{
- return sizeof(struct cz_power_state);
+ return sizeof(struct smu8_power_state);
}
-static void cz_hw_print_display_cfg(
+static void smu8_hw_print_display_cfg(
const struct cc6_settings *cc6_settings)
{
PP_DBG_LOG("New Display Configuration:\n");
@@ -1475,16 +1409,16 @@ static void cz_hw_print_display_cfg(
cc6_settings->cpu_pstate_separation_time);
}
- static int cz_set_cpu_power_state(struct pp_hwmgr *hwmgr)
+ static int smu8_set_cpu_power_state(struct pp_hwmgr *hwmgr)
{
- struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
+ struct smu8_hwmgr *hw_data = hwmgr->backend;
uint32_t data = 0;
if (hw_data->cc6_settings.cc6_setting_changed) {
hw_data->cc6_settings.cc6_setting_changed = false;
- cz_hw_print_display_cfg(&hw_data->cc6_settings);
+ smu8_hw_print_display_cfg(&hw_data->cc6_settings);
data |= (hw_data->cc6_settings.cpu_pstate_separation_time
& PWRMGT_SEPARATION_TIME_MASK)
@@ -1508,10 +1442,10 @@ static void cz_hw_print_display_cfg(
}
-static int cz_store_cc6_data(struct pp_hwmgr *hwmgr, uint32_t separation_time,
+static int smu8_store_cc6_data(struct pp_hwmgr *hwmgr, uint32_t separation_time,
bool cc6_disable, bool pstate_disable, bool pstate_switch_disable)
{
- struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
+ struct smu8_hwmgr *hw_data = hwmgr->backend;
if (separation_time !=
hw_data->cc6_settings.cpu_pstate_separation_time ||
@@ -1535,7 +1469,7 @@ static int cz_store_cc6_data(struct pp_hwmgr *hwmgr, uint32_t separation_time,
return 0;
}
-static int cz_get_dal_power_level(struct pp_hwmgr *hwmgr,
+static int smu8_get_dal_power_level(struct pp_hwmgr *hwmgr,
struct amd_pp_simple_clock_info *info)
{
uint32_t i;
@@ -1556,12 +1490,9 @@ static int cz_get_dal_power_level(struct pp_hwmgr *hwmgr,
return -EINVAL;
}
-static int cz_force_clock_level(struct pp_hwmgr *hwmgr,
+static int smu8_force_clock_level(struct pp_hwmgr *hwmgr,
enum pp_clock_type type, uint32_t mask)
{
- if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
- return -EINVAL;
-
switch (type) {
case PP_SCLK:
smum_send_msg_to_smc_with_parameter(hwmgr,
@@ -1578,9 +1509,10 @@ static int cz_force_clock_level(struct pp_hwmgr *hwmgr,
return 0;
}
-static int cz_print_clock_levels(struct pp_hwmgr *hwmgr,
+static int smu8_print_clock_levels(struct pp_hwmgr *hwmgr,
enum pp_clock_type type, char *buf)
{
+ struct smu8_hwmgr *data = hwmgr->backend;
struct phm_clock_voltage_dependency_table *sclk_table =
hwmgr->dyn_state.vddc_dependency_on_sclk;
int i, now, size = 0;
@@ -1598,26 +1530,38 @@ static int cz_print_clock_levels(struct pp_hwmgr *hwmgr,
i, sclk_table->entries[i].clk / 100,
(i == now) ? "*" : "");
break;
+ case PP_MCLK:
+ now = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device,
+ CGS_IND_REG__SMC,
+ ixTARGET_AND_CURRENT_PROFILE_INDEX),
+ TARGET_AND_CURRENT_PROFILE_INDEX,
+ CURR_MCLK_INDEX);
+
+ for (i = SMU8_NUM_NBPMEMORYCLOCK; i > 0; i--)
+ size += sprintf(buf + size, "%d: %uMhz %s\n",
+ SMU8_NUM_NBPMEMORYCLOCK-i, data->sys_info.nbp_memory_clock[i-1] / 100,
+ (SMU8_NUM_NBPMEMORYCLOCK-i == now) ? "*" : "");
+ break;
default:
break;
}
return size;
}
-static int cz_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
+static int smu8_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
PHM_PerformanceLevelDesignation designation, uint32_t index,
PHM_PerformanceLevel *level)
{
- const struct cz_power_state *ps;
- struct cz_hwmgr *data;
+ const struct smu8_power_state *ps;
+ struct smu8_hwmgr *data;
uint32_t level_index;
uint32_t i;
if (level == NULL || hwmgr == NULL || state == NULL)
return -EINVAL;
- data = (struct cz_hwmgr *)(hwmgr->backend);
- ps = cast_const_PhwCzPowerState(state);
+ data = hwmgr->backend;
+ ps = cast_const_smu8_power_state(state);
level_index = index > ps->level - 1 ? ps->level - 1 : index;
level->coreClock = ps->levels[level_index].engineClock;
@@ -1632,21 +1576,21 @@ static int cz_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_p
}
if (level_index == 0)
- level->memory_clock = data->sys_info.nbp_memory_clock[CZ_NUM_NBPMEMORYCLOCK - 1];
+ level->memory_clock = data->sys_info.nbp_memory_clock[SMU8_NUM_NBPMEMORYCLOCK - 1];
else
level->memory_clock = data->sys_info.nbp_memory_clock[0];
- level->vddc = (cz_convert_8Bit_index_to_voltage(hwmgr, ps->levels[level_index].vddcIndex) + 2) / 4;
+ level->vddc = (smu8_convert_8Bit_index_to_voltage(hwmgr, ps->levels[level_index].vddcIndex) + 2) / 4;
level->nonLocalMemoryFreq = 0;
level->nonLocalMemoryWidth = 0;
return 0;
}
-static int cz_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr,
+static int smu8_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr,
const struct pp_hw_power_state *state, struct pp_clock_info *clock_info)
{
- const struct cz_power_state *ps = cast_const_PhwCzPowerState(state);
+ const struct smu8_power_state *ps = cast_const_smu8_power_state(state);
clock_info->min_eng_clk = ps->levels[0].engineClock / (1 << (ps->levels[0].ssDividerIndex));
clock_info->max_eng_clk = ps->levels[ps->level - 1].engineClock / (1 << (ps->levels[ps->level - 1].ssDividerIndex));
@@ -1654,14 +1598,14 @@ static int cz_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr,
return 0;
}
-static int cz_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type,
+static int smu8_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type,
struct amd_pp_clocks *clocks)
{
- struct cz_hwmgr *data = (struct cz_hwmgr *)(hwmgr->backend);
+ struct smu8_hwmgr *data = hwmgr->backend;
int i;
struct phm_clock_voltage_dependency_table *table;
- clocks->count = cz_get_max_sclk_level(hwmgr);
+ clocks->count = smu8_get_max_sclk_level(hwmgr);
switch (type) {
case amd_pp_disp_clock:
for (i = 0; i < clocks->count; i++)
@@ -1673,7 +1617,7 @@ static int cz_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type t
clocks->clock[i] = table->entries[i].clk;
break;
case amd_pp_mem_clock:
- clocks->count = CZ_NUM_NBPMEMORYCLOCK;
+ clocks->count = SMU8_NUM_NBPMEMORYCLOCK;
for (i = 0; i < clocks->count; i++)
clocks->clock[i] = data->sys_info.nbp_memory_clock[clocks->count - 1 - i];
break;
@@ -1684,7 +1628,7 @@ static int cz_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type t
return 0;
}
-static int cz_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks)
+static int smu8_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks)
{
struct phm_clock_voltage_dependency_table *table =
hwmgr->dyn_state.vddc_dependency_on_sclk;
@@ -1695,7 +1639,7 @@ static int cz_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_c
if ((NULL == table) || (table->count <= 0) || (clocks == NULL))
return -EINVAL;
- level = cz_get_max_sclk_level(hwmgr) - 1;
+ level = smu8_get_max_sclk_level(hwmgr) - 1;
if (level < table->count)
clocks->engine_max_clock = table->entries[level].clk;
@@ -1707,7 +1651,7 @@ static int cz_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_c
return 0;
}
-static int cz_thermal_get_temperature(struct pp_hwmgr *hwmgr)
+static int smu8_thermal_get_temperature(struct pp_hwmgr *hwmgr)
{
int actual_temp = 0;
uint32_t val = cgs_read_ind_register(hwmgr->device,
@@ -1722,10 +1666,10 @@ static int cz_thermal_get_temperature(struct pp_hwmgr *hwmgr)
return actual_temp;
}
-static int cz_read_sensor(struct pp_hwmgr *hwmgr, int idx,
+static int smu8_read_sensor(struct pp_hwmgr *hwmgr, int idx,
void *value, int *size)
{
- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
+ struct smu8_hwmgr *data = hwmgr->backend;
struct phm_clock_voltage_dependency_table *table =
hwmgr->dyn_state.vddc_dependency_on_sclk;
@@ -1763,18 +1707,18 @@ static int cz_read_sensor(struct pp_hwmgr *hwmgr, int idx,
case AMDGPU_PP_SENSOR_VDDNB:
tmp = (cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMUSVI_NB_CURRENTVID) &
CURRENT_NB_VID_MASK) >> CURRENT_NB_VID__SHIFT;
- vddnb = cz_convert_8Bit_index_to_voltage(hwmgr, tmp);
+ vddnb = smu8_convert_8Bit_index_to_voltage(hwmgr, tmp);
*((uint32_t *)value) = vddnb;
return 0;
case AMDGPU_PP_SENSOR_VDDGFX:
tmp = (cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMUSVI_GFX_CURRENTVID) &
CURRENT_GFX_VID_MASK) >> CURRENT_GFX_VID__SHIFT;
- vddgfx = cz_convert_8Bit_index_to_voltage(hwmgr, (u16)tmp);
+ vddgfx = smu8_convert_8Bit_index_to_voltage(hwmgr, (u16)tmp);
*((uint32_t *)value) = vddgfx;
return 0;
case AMDGPU_PP_SENSOR_UVD_VCLK:
- if (!cz_hwmgr->uvd_power_gated) {
- if (uvd_index >= CZ_MAX_HARDWARE_POWERLEVELS) {
+ if (!data->uvd_power_gated) {
+ if (uvd_index >= SMU8_MAX_HARDWARE_POWERLEVELS) {
return -EINVAL;
} else {
vclk = uvd_table->entries[uvd_index].vclk;
@@ -1785,8 +1729,8 @@ static int cz_read_sensor(struct pp_hwmgr *hwmgr, int idx,
*((uint32_t *)value) = 0;
return 0;
case AMDGPU_PP_SENSOR_UVD_DCLK:
- if (!cz_hwmgr->uvd_power_gated) {
- if (uvd_index >= CZ_MAX_HARDWARE_POWERLEVELS) {
+ if (!data->uvd_power_gated) {
+ if (uvd_index >= SMU8_MAX_HARDWARE_POWERLEVELS) {
return -EINVAL;
} else {
dclk = uvd_table->entries[uvd_index].dclk;
@@ -1797,8 +1741,8 @@ static int cz_read_sensor(struct pp_hwmgr *hwmgr, int idx,
*((uint32_t *)value) = 0;
return 0;
case AMDGPU_PP_SENSOR_VCE_ECCLK:
- if (!cz_hwmgr->vce_power_gated) {
- if (vce_index >= CZ_MAX_HARDWARE_POWERLEVELS) {
+ if (!data->vce_power_gated) {
+ if (vce_index >= SMU8_MAX_HARDWARE_POWERLEVELS) {
return -EINVAL;
} else {
ecclk = vce_table->entries[vce_index].ecclk;
@@ -1819,20 +1763,20 @@ static int cz_read_sensor(struct pp_hwmgr *hwmgr, int idx,
*((uint32_t *)value) = activity_percent;
return 0;
case AMDGPU_PP_SENSOR_UVD_POWER:
- *((uint32_t *)value) = cz_hwmgr->uvd_power_gated ? 0 : 1;
+ *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1;
return 0;
case AMDGPU_PP_SENSOR_VCE_POWER:
- *((uint32_t *)value) = cz_hwmgr->vce_power_gated ? 0 : 1;
+ *((uint32_t *)value) = data->vce_power_gated ? 0 : 1;
return 0;
case AMDGPU_PP_SENSOR_GPU_TEMP:
- *((uint32_t *)value) = cz_thermal_get_temperature(hwmgr);
+ *((uint32_t *)value) = smu8_thermal_get_temperature(hwmgr);
return 0;
default:
return -EINVAL;
}
}
-static int cz_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
+static int smu8_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
uint32_t virtual_addr_low,
uint32_t virtual_addr_hi,
uint32_t mc_addr_low,
@@ -1858,43 +1802,190 @@ static int cz_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
return 0;
}
+static int smu8_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
+ struct PP_TemperatureRange *thermal_data)
+{
+ struct smu8_hwmgr *data = hwmgr->backend;
+
+ memcpy(thermal_data, &SMU7ThermalPolicy[0], sizeof(struct PP_TemperatureRange));
+
+ thermal_data->max = (data->thermal_auto_throttling_treshold +
+ data->sys_info.htc_hyst_lmt) *
+ PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
+
+ return 0;
+}
+
+static int smu8_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
+{
+ struct smu8_hwmgr *data = hwmgr->backend;
+ uint32_t dpm_features = 0;
+
+ if (enable &&
+ phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_UVDDPM)) {
+ data->dpm_flags |= DPMFlags_UVD_Enabled;
+ dpm_features |= UVD_DPM_MASK;
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_EnableAllSmuFeatures, dpm_features);
+ } else {
+ dpm_features |= UVD_DPM_MASK;
+ data->dpm_flags &= ~DPMFlags_UVD_Enabled;
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_DisableAllSmuFeatures, dpm_features);
+ }
+ return 0;
+}
+
+int smu8_dpm_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
+{
+ struct smu8_hwmgr *data = hwmgr->backend;
+ struct phm_uvd_clock_voltage_dependency_table *ptable =
+ hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
+
+ if (!bgate) {
+ /* Stable Pstate is enabled and we need to set the UVD DPM to highest level */
+ if (PP_CAP(PHM_PlatformCaps_StablePState) ||
+ hwmgr->en_umd_pstate) {
+ data->uvd_dpm.hard_min_clk =
+ ptable->entries[ptable->count - 1].vclk;
+
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetUvdHardMin,
+ smu8_get_uvd_level(hwmgr,
+ data->uvd_dpm.hard_min_clk,
+ PPSMC_MSG_SetUvdHardMin));
+
+ smu8_enable_disable_uvd_dpm(hwmgr, true);
+ } else {
+ smu8_enable_disable_uvd_dpm(hwmgr, true);
+ }
+ } else {
+ smu8_enable_disable_uvd_dpm(hwmgr, false);
+ }
+
+ return 0;
+}
+
+static int smu8_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
+{
+ struct smu8_hwmgr *data = hwmgr->backend;
+ uint32_t dpm_features = 0;
+
+ if (enable && phm_cap_enabled(
+ hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_VCEDPM)) {
+ data->dpm_flags |= DPMFlags_VCE_Enabled;
+ dpm_features |= VCE_DPM_MASK;
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_EnableAllSmuFeatures, dpm_features);
+ } else {
+ dpm_features |= VCE_DPM_MASK;
+ data->dpm_flags &= ~DPMFlags_VCE_Enabled;
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_DisableAllSmuFeatures, dpm_features);
+ }
+
+ return 0;
+}
+
+
+static void smu8_dpm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
+{
+ struct smu8_hwmgr *data = hwmgr->backend;
+
+ data->uvd_power_gated = bgate;
+
+ if (bgate) {
+ cgs_set_powergating_state(hwmgr->device,
+ AMD_IP_BLOCK_TYPE_UVD,
+ AMD_PG_STATE_GATE);
+ cgs_set_clockgating_state(hwmgr->device,
+ AMD_IP_BLOCK_TYPE_UVD,
+ AMD_CG_STATE_GATE);
+ smu8_dpm_update_uvd_dpm(hwmgr, true);
+ smu8_dpm_powerdown_uvd(hwmgr);
+ } else {
+ smu8_dpm_powerup_uvd(hwmgr);
+ cgs_set_clockgating_state(hwmgr->device,
+ AMD_IP_BLOCK_TYPE_UVD,
+ AMD_CG_STATE_UNGATE);
+ cgs_set_powergating_state(hwmgr->device,
+ AMD_IP_BLOCK_TYPE_UVD,
+ AMD_PG_STATE_UNGATE);
+ smu8_dpm_update_uvd_dpm(hwmgr, false);
+ }
+
+}
+
+static void smu8_dpm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
+{
+ struct smu8_hwmgr *data = hwmgr->backend;
+
+ if (bgate) {
+ cgs_set_powergating_state(
+ hwmgr->device,
+ AMD_IP_BLOCK_TYPE_VCE,
+ AMD_PG_STATE_GATE);
+ cgs_set_clockgating_state(
+ hwmgr->device,
+ AMD_IP_BLOCK_TYPE_VCE,
+ AMD_CG_STATE_GATE);
+ smu8_enable_disable_vce_dpm(hwmgr, false);
+ smu8_dpm_powerdown_vce(hwmgr);
+ data->vce_power_gated = true;
+ } else {
+ smu8_dpm_powerup_vce(hwmgr);
+ data->vce_power_gated = false;
+ cgs_set_clockgating_state(
+ hwmgr->device,
+ AMD_IP_BLOCK_TYPE_VCE,
+ AMD_CG_STATE_UNGATE);
+ cgs_set_powergating_state(
+ hwmgr->device,
+ AMD_IP_BLOCK_TYPE_VCE,
+ AMD_PG_STATE_UNGATE);
+ smu8_dpm_update_vce_dpm(hwmgr);
+ smu8_enable_disable_vce_dpm(hwmgr, true);
+ }
+}
-static const struct pp_hwmgr_func cz_hwmgr_funcs = {
- .backend_init = cz_hwmgr_backend_init,
- .backend_fini = cz_hwmgr_backend_fini,
- .apply_state_adjust_rules = cz_apply_state_adjust_rules,
- .force_dpm_level = cz_dpm_force_dpm_level,
- .get_power_state_size = cz_get_power_state_size,
- .powerdown_uvd = cz_dpm_powerdown_uvd,
- .powergate_uvd = cz_dpm_powergate_uvd,
- .powergate_vce = cz_dpm_powergate_vce,
- .get_mclk = cz_dpm_get_mclk,
- .get_sclk = cz_dpm_get_sclk,
- .patch_boot_state = cz_dpm_patch_boot_state,
- .get_pp_table_entry = cz_dpm_get_pp_table_entry,
- .get_num_of_pp_table_entries = cz_dpm_get_num_of_pp_table_entries,
- .set_cpu_power_state = cz_set_cpu_power_state,
- .store_cc6_data = cz_store_cc6_data,
- .force_clock_level = cz_force_clock_level,
- .print_clock_levels = cz_print_clock_levels,
- .get_dal_power_level = cz_get_dal_power_level,
- .get_performance_level = cz_get_performance_level,
- .get_current_shallow_sleep_clocks = cz_get_current_shallow_sleep_clocks,
- .get_clock_by_type = cz_get_clock_by_type,
- .get_max_high_clocks = cz_get_max_high_clocks,
- .get_temperature = cz_thermal_get_temperature,
- .read_sensor = cz_read_sensor,
- .power_off_asic = cz_power_off_asic,
- .asic_setup = cz_setup_asic_task,
- .dynamic_state_management_enable = cz_enable_dpm_tasks,
- .power_state_set = cz_set_power_state_tasks,
- .dynamic_state_management_disable = cz_disable_dpm_tasks,
- .notify_cac_buffer_info = cz_notify_cac_buffer_info,
+static const struct pp_hwmgr_func smu8_hwmgr_funcs = {
+ .backend_init = smu8_hwmgr_backend_init,
+ .backend_fini = smu8_hwmgr_backend_fini,
+ .apply_state_adjust_rules = smu8_apply_state_adjust_rules,
+ .force_dpm_level = smu8_dpm_force_dpm_level,
+ .get_power_state_size = smu8_get_power_state_size,
+ .powerdown_uvd = smu8_dpm_powerdown_uvd,
+ .powergate_uvd = smu8_dpm_powergate_uvd,
+ .powergate_vce = smu8_dpm_powergate_vce,
+ .get_mclk = smu8_dpm_get_mclk,
+ .get_sclk = smu8_dpm_get_sclk,
+ .patch_boot_state = smu8_dpm_patch_boot_state,
+ .get_pp_table_entry = smu8_dpm_get_pp_table_entry,
+ .get_num_of_pp_table_entries = smu8_dpm_get_num_of_pp_table_entries,
+ .set_cpu_power_state = smu8_set_cpu_power_state,
+ .store_cc6_data = smu8_store_cc6_data,
+ .force_clock_level = smu8_force_clock_level,
+ .print_clock_levels = smu8_print_clock_levels,
+ .get_dal_power_level = smu8_get_dal_power_level,
+ .get_performance_level = smu8_get_performance_level,
+ .get_current_shallow_sleep_clocks = smu8_get_current_shallow_sleep_clocks,
+ .get_clock_by_type = smu8_get_clock_by_type,
+ .get_max_high_clocks = smu8_get_max_high_clocks,
+ .read_sensor = smu8_read_sensor,
+ .power_off_asic = smu8_power_off_asic,
+ .asic_setup = smu8_setup_asic_task,
+ .dynamic_state_management_enable = smu8_enable_dpm_tasks,
+ .power_state_set = smu8_set_power_state_tasks,
+ .dynamic_state_management_disable = smu8_disable_dpm_tasks,
+ .notify_cac_buffer_info = smu8_notify_cac_buffer_info,
+ .get_thermal_temperature_range = smu8_get_thermal_temperature_range,
};
-int cz_init_function_pointers(struct pp_hwmgr *hwmgr)
+int smu8_init_function_pointers(struct pp_hwmgr *hwmgr)
{
- hwmgr->hwmgr_func = &cz_hwmgr_funcs;
+ hwmgr->hwmgr_func = &smu8_hwmgr_funcs;
hwmgr->pptable_func = &pptable_funcs;
return 0;
}
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h
index 508b422d6159..05a06083e1b8 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h
@@ -21,19 +21,18 @@
*
*/
-#ifndef _CZ_HWMGR_H_
-#define _CZ_HWMGR_H_
+#ifndef _SMU8_HWMGR_H_
+#define _SMU8_HWMGR_H_
#include "cgs_common.h"
#include "ppatomctrl.h"
-#define CZ_NUM_NBPSTATES 4
-#define CZ_NUM_NBPMEMORYCLOCK 2
+#define SMU8_NUM_NBPSTATES 4
+#define SMU8_NUM_NBPMEMORYCLOCK 2
#define MAX_DISPLAY_CLOCK_LEVEL 8
-#define CZ_AT_DFLT 30
-#define CZ_MAX_HARDWARE_POWERLEVELS 8
-#define PPCZ_VOTINGRIGHTSCLIENTS_DFLT0 0x3FFFC102
-#define CZ_MIN_DEEP_SLEEP_SCLK 800
+#define SMU8_MAX_HARDWARE_POWERLEVELS 8
+#define SMU8_VOTINGRIGHTSCLIENTS_DFLT0 0x3FFFC102
+#define SMU8_MIN_DEEP_SLEEP_SCLK 800
/* Carrizo device IDs */
#define DEVICE_ID_CZ_9870 0x9870
@@ -42,24 +41,21 @@
#define DEVICE_ID_CZ_9876 0x9876
#define DEVICE_ID_CZ_9877 0x9877
-#define PHMCZ_WRITE_SMC_REGISTER(device, reg, value) \
- cgs_write_ind_register(device, CGS_IND_REG__SMC, ix##reg, value)
-
-struct cz_dpm_entry {
+struct smu8_dpm_entry {
uint32_t soft_min_clk;
uint32_t hard_min_clk;
uint32_t soft_max_clk;
uint32_t hard_max_clk;
};
-struct cz_sys_info {
+struct smu8_sys_info {
uint32_t bootup_uma_clock;
uint32_t bootup_engine_clock;
uint32_t dentist_vco_freq;
uint32_t nb_dpm_enable;
- uint32_t nbp_memory_clock[CZ_NUM_NBPMEMORYCLOCK];
- uint32_t nbp_n_clock[CZ_NUM_NBPSTATES];
- uint16_t nbp_voltage_index[CZ_NUM_NBPSTATES];
+ uint32_t nbp_memory_clock[SMU8_NUM_NBPMEMORYCLOCK];
+ uint32_t nbp_n_clock[SMU8_NUM_NBPSTATES];
+ uint16_t nbp_voltage_index[SMU8_NUM_NBPSTATES];
uint32_t display_clock[MAX_DISPLAY_CLOCK_LEVEL];
uint16_t bootup_nb_voltage_index;
uint8_t htc_tmp_lmt;
@@ -86,21 +82,21 @@ struct cz_sys_info {
((tx) ? DISPLAYPHY_TX_SELECT : 0) | \
((core) ? DISPLAYPHY_CORE_SELECT : 0))
-struct cz_display_phy_info_entry {
+struct smu8_display_phy_info_entry {
uint8_t phy_present;
uint8_t active_lane_mapping;
uint8_t display_config_type;
uint8_t active_number_of_lanes;
};
-#define CZ_MAX_DISPLAYPHY_IDS 10
+#define SMU8_MAX_DISPLAYPHY_IDS 10
-struct cz_display_phy_info {
+struct smu8_display_phy_info {
bool display_phy_access_initialized;
- struct cz_display_phy_info_entry entries[CZ_MAX_DISPLAYPHY_IDS];
+ struct smu8_display_phy_info_entry entries[SMU8_MAX_DISPLAYPHY_IDS];
};
-struct cz_power_level {
+struct smu8_power_level {
uint32_t engineClock;
uint8_t vddcIndex;
uint8_t dsDividerIndex;
@@ -114,7 +110,7 @@ struct cz_power_level {
uint8_t rsv[3];
};
-struct cz_uvd_clocks {
+struct smu8_uvd_clocks {
uint32_t vclk;
uint32_t dclk;
uint32_t vclk_low_divider;
@@ -123,7 +119,7 @@ struct cz_uvd_clocks {
uint32_t dclk_high_divider;
};
-enum cz_pstate_previous_action {
+enum smu8_pstate_previous_action {
DO_NOTHING = 1,
FORCE_HIGH,
CANCEL_FORCE_HIGH
@@ -144,10 +140,10 @@ struct pp_disable_nb_ps_flags {
};
};
-struct cz_power_state {
+struct smu8_power_state {
unsigned int magic;
uint32_t level;
- struct cz_uvd_clocks uvd_clocks;
+ struct smu8_uvd_clocks uvd_clocks;
uint32_t evclk;
uint32_t ecclk;
uint32_t samclk;
@@ -159,8 +155,8 @@ struct cz_power_state {
uint8_t dpm_0_pg_nb_ps_high;
uint8_t dpm_x_nb_ps_low;
uint8_t dpm_x_nb_ps_high;
- enum cz_pstate_previous_action action;
- struct cz_power_level levels[CZ_MAX_HARDWARE_POWERLEVELS];
+ enum smu8_pstate_previous_action action;
+ struct smu8_power_level levels[SMU8_MAX_HARDWARE_POWERLEVELS];
struct pp_disable_nb_ps_flags disable_nb_ps_flag;
};
@@ -172,7 +168,6 @@ struct cz_power_state {
#define DPMFlags_Debug 0x80000000
#define SMU_EnabledFeatureScoreboard_AcpDpmOn 0x00000001 /* bit 0 */
-#define SMU_EnabledFeatureScoreboard_SclkDpmOn 0x00200000
#define SMU_EnabledFeatureScoreboard_UvdDpmOn 0x00800000 /* bit 23 */
#define SMU_EnabledFeatureScoreboard_VceDpmOn 0x01000000 /* bit 24 */
@@ -184,8 +179,7 @@ struct cc6_settings {
uint32_t cpu_pstate_separation_time;
};
-struct cz_hwmgr {
- uint32_t activity_target[CZ_MAX_HARDWARE_POWERLEVELS];
+struct smu8_hwmgr {
uint32_t dpm_interval;
uint32_t voltage_drop_threshold;
@@ -205,11 +199,11 @@ struct cz_hwmgr {
uint32_t thermal_auto_throttling_treshold;
- struct cz_sys_info sys_info;
+ struct smu8_sys_info sys_info;
- struct cz_power_level boot_power_level;
- struct cz_power_state *cz_current_ps;
- struct cz_power_state *cz_requested_ps;
+ struct smu8_power_level boot_power_level;
+ struct smu8_power_state *smu8_current_ps;
+ struct smu8_power_state *smu8_requested_ps;
uint32_t mgcg_cgtt_local0;
uint32_t mgcg_cgtt_local1;
@@ -222,7 +216,7 @@ struct cz_hwmgr {
uint32_t lock_nb_ps_in_uvd_play_back;
- struct cz_display_phy_info display_phy_info;
+ struct smu8_display_phy_info display_phy_info;
uint32_t vce_slow_sclk_threshold; /* default 200mhz */
uint32_t dce_slow_sclk_threshold; /* default 300mhz */
uint32_t min_sclk_did; /* minimum sclk divider */
@@ -273,10 +267,10 @@ struct cz_hwmgr {
uint32_t fps_low_threshold;
uint32_t dpm_flags;
- struct cz_dpm_entry sclk_dpm;
- struct cz_dpm_entry uvd_dpm;
- struct cz_dpm_entry vce_dpm;
- struct cz_dpm_entry acp_dpm;
+ struct smu8_dpm_entry sclk_dpm;
+ struct smu8_dpm_entry uvd_dpm;
+ struct smu8_dpm_entry vce_dpm;
+ struct smu8_dpm_entry acp_dpm;
uint8_t uvd_boot_level;
uint8_t vce_boot_level;
@@ -314,12 +308,4 @@ struct cz_hwmgr {
uint32_t num_of_clk_entries;
};
-struct pp_hwmgr;
-
-int cz_dpm_powerdown_uvd(struct pp_hwmgr *hwmgr);
-int cz_dpm_powerup_uvd(struct pp_hwmgr *hwmgr);
-int cz_dpm_powerdown_vce(struct pp_hwmgr *hwmgr);
-int cz_dpm_powerup_vce(struct pp_hwmgr *hwmgr);
-int cz_dpm_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate);
-int cz_dpm_update_vce_dpm(struct pp_hwmgr *hwmgr);
-#endif /* _CZ_HWMGR_H_ */
+#endif /* _SMU8_HWMGR_H_ */
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c
new file mode 100644
index 000000000000..e11daf5cbf80
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c
@@ -0,0 +1,536 @@
+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#include "hwmgr.h"
+#include "pp_debug.h"
+#include "ppatomctrl.h"
+#include "ppsmc.h"
+
+uint8_t convert_to_vid(uint16_t vddc)
+{
+ return (uint8_t) ((6200 - (vddc * VOLTAGE_SCALE)) / 25);
+}
+
+uint16_t convert_to_vddc(uint8_t vid)
+{
+ return (uint16_t) ((6200 - (vid * 25)) / VOLTAGE_SCALE);
+}
+
+uint32_t phm_set_field_to_u32(u32 offset, u32 original_data, u32 field, u32 size)
+{
+ u32 mask = 0;
+ u32 shift = 0;
+
+ shift = (offset % 4) << 3;
+ if (size == sizeof(uint8_t))
+ mask = 0xFF << shift;
+ else if (size == sizeof(uint16_t))
+ mask = 0xFFFF << shift;
+
+ original_data &= ~mask;
+ original_data |= (field << shift);
+ return original_data;
+}
+
+/**
+ * Returns once the part of the register indicated by the mask has
+ * reached the given value.
+ */
+int phm_wait_on_register(struct pp_hwmgr *hwmgr, uint32_t index,
+ uint32_t value, uint32_t mask)
+{
+ uint32_t i;
+ uint32_t cur_value;
+
+ if (hwmgr == NULL || hwmgr->device == NULL) {
+ pr_err("Invalid Hardware Manager!");
+ return -EINVAL;
+ }
+
+ for (i = 0; i < hwmgr->usec_timeout; i++) {
+ cur_value = cgs_read_register(hwmgr->device, index);
+ if ((cur_value & mask) == (value & mask))
+ break;
+ udelay(1);
+ }
+
+ /* timeout means wrong logic*/
+ if (i == hwmgr->usec_timeout)
+ return -1;
+ return 0;
+}
+
+
+/**
+ * Returns once the part of the register indicated by the mask has
+ * reached the given value.The indirect space is described by giving
+ * the memory-mapped index of the indirect index register.
+ */
+int phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr,
+ uint32_t indirect_port,
+ uint32_t index,
+ uint32_t value,
+ uint32_t mask)
+{
+ if (hwmgr == NULL || hwmgr->device == NULL) {
+ pr_err("Invalid Hardware Manager!");
+ return -EINVAL;
+ }
+
+ cgs_write_register(hwmgr->device, indirect_port, index);
+ return phm_wait_on_register(hwmgr, indirect_port + 1, mask, value);
+}
+
+int phm_wait_for_register_unequal(struct pp_hwmgr *hwmgr,
+ uint32_t index,
+ uint32_t value, uint32_t mask)
+{
+ uint32_t i;
+ uint32_t cur_value;
+
+ if (hwmgr == NULL || hwmgr->device == NULL)
+ return -EINVAL;
+
+ for (i = 0; i < hwmgr->usec_timeout; i++) {
+ cur_value = cgs_read_register(hwmgr->device,
+ index);
+ if ((cur_value & mask) != (value & mask))
+ break;
+ udelay(1);
+ }
+
+ /* timeout means wrong logic */
+ if (i == hwmgr->usec_timeout)
+ return -ETIME;
+ return 0;
+}
+
+int phm_wait_for_indirect_register_unequal(struct pp_hwmgr *hwmgr,
+ uint32_t indirect_port,
+ uint32_t index,
+ uint32_t value,
+ uint32_t mask)
+{
+ if (hwmgr == NULL || hwmgr->device == NULL)
+ return -EINVAL;
+
+ cgs_write_register(hwmgr->device, indirect_port, index);
+ return phm_wait_for_register_unequal(hwmgr, indirect_port + 1,
+ value, mask);
+}
+
+bool phm_cf_want_uvd_power_gating(struct pp_hwmgr *hwmgr)
+{
+ return phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UVDPowerGating);
+}
+
+bool phm_cf_want_vce_power_gating(struct pp_hwmgr *hwmgr)
+{
+ return phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VCEPowerGating);
+}
+
+
+int phm_trim_voltage_table(struct pp_atomctrl_voltage_table *vol_table)
+{
+ uint32_t i, j;
+ uint16_t vvalue;
+ bool found = false;
+ struct pp_atomctrl_voltage_table *table;
+
+ PP_ASSERT_WITH_CODE((NULL != vol_table),
+ "Voltage Table empty.", return -EINVAL);
+
+ table = kzalloc(sizeof(struct pp_atomctrl_voltage_table),
+ GFP_KERNEL);
+
+ if (NULL == table)
+ return -EINVAL;
+
+ table->mask_low = vol_table->mask_low;
+ table->phase_delay = vol_table->phase_delay;
+
+ for (i = 0; i < vol_table->count; i++) {
+ vvalue = vol_table->entries[i].value;
+ found = false;
+
+ for (j = 0; j < table->count; j++) {
+ if (vvalue == table->entries[j].value) {
+ found = true;
+ break;
+ }
+ }
+
+ if (!found) {
+ table->entries[table->count].value = vvalue;
+ table->entries[table->count].smio_low =
+ vol_table->entries[i].smio_low;
+ table->count++;
+ }
+ }
+
+ memcpy(vol_table, table, sizeof(struct pp_atomctrl_voltage_table));
+ kfree(table);
+ table = NULL;
+ return 0;
+}
+
+int phm_get_svi2_mvdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table,
+ phm_ppt_v1_clock_voltage_dependency_table *dep_table)
+{
+ uint32_t i;
+ int result;
+
+ PP_ASSERT_WITH_CODE((0 != dep_table->count),
+ "Voltage Dependency Table empty.", return -EINVAL);
+
+ PP_ASSERT_WITH_CODE((NULL != vol_table),
+ "vol_table empty.", return -EINVAL);
+
+ vol_table->mask_low = 0;
+ vol_table->phase_delay = 0;
+ vol_table->count = dep_table->count;
+
+ for (i = 0; i < dep_table->count; i++) {
+ vol_table->entries[i].value = dep_table->entries[i].mvdd;
+ vol_table->entries[i].smio_low = 0;
+ }
+
+ result = phm_trim_voltage_table(vol_table);
+ PP_ASSERT_WITH_CODE((0 == result),
+ "Failed to trim MVDD table.", return result);
+
+ return 0;
+}
+
+int phm_get_svi2_vddci_voltage_table(struct pp_atomctrl_voltage_table *vol_table,
+ phm_ppt_v1_clock_voltage_dependency_table *dep_table)
+{
+ uint32_t i;
+ int result;
+
+ PP_ASSERT_WITH_CODE((0 != dep_table->count),
+ "Voltage Dependency Table empty.", return -EINVAL);
+
+ PP_ASSERT_WITH_CODE((NULL != vol_table),
+ "vol_table empty.", return -EINVAL);
+
+ vol_table->mask_low = 0;
+ vol_table->phase_delay = 0;
+ vol_table->count = dep_table->count;
+
+ for (i = 0; i < dep_table->count; i++) {
+ vol_table->entries[i].value = dep_table->entries[i].vddci;
+ vol_table->entries[i].smio_low = 0;
+ }
+
+ result = phm_trim_voltage_table(vol_table);
+ PP_ASSERT_WITH_CODE((0 == result),
+ "Failed to trim VDDCI table.", return result);
+
+ return 0;
+}
+
+int phm_get_svi2_vdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table,
+ phm_ppt_v1_voltage_lookup_table *lookup_table)
+{
+ int i = 0;
+
+ PP_ASSERT_WITH_CODE((0 != lookup_table->count),
+ "Voltage Lookup Table empty.", return -EINVAL);
+
+ PP_ASSERT_WITH_CODE((NULL != vol_table),
+ "vol_table empty.", return -EINVAL);
+
+ vol_table->mask_low = 0;
+ vol_table->phase_delay = 0;
+
+ vol_table->count = lookup_table->count;
+
+ for (i = 0; i < vol_table->count; i++) {
+ vol_table->entries[i].value = lookup_table->entries[i].us_vdd;
+ vol_table->entries[i].smio_low = 0;
+ }
+
+ return 0;
+}
+
+void phm_trim_voltage_table_to_fit_state_table(uint32_t max_vol_steps,
+ struct pp_atomctrl_voltage_table *vol_table)
+{
+ unsigned int i, diff;
+
+ if (vol_table->count <= max_vol_steps)
+ return;
+
+ diff = vol_table->count - max_vol_steps;
+
+ for (i = 0; i < max_vol_steps; i++)
+ vol_table->entries[i] = vol_table->entries[i + diff];
+
+ vol_table->count = max_vol_steps;
+
+ return;
+}
+
+int phm_reset_single_dpm_table(void *table,
+ uint32_t count, int max)
+{
+ int i;
+
+ struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table;
+
+ dpm_table->count = count > max ? max : count;
+
+ for (i = 0; i < dpm_table->count; i++)
+ dpm_table->dpm_level[i].enabled = false;
+
+ return 0;
+}
+
+void phm_setup_pcie_table_entry(
+ void *table,
+ uint32_t index, uint32_t pcie_gen,
+ uint32_t pcie_lanes)
+{
+ struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table;
+ dpm_table->dpm_level[index].value = pcie_gen;
+ dpm_table->dpm_level[index].param1 = pcie_lanes;
+ dpm_table->dpm_level[index].enabled = 1;
+}
+
+int32_t phm_get_dpm_level_enable_mask_value(void *table)
+{
+ int32_t i;
+ int32_t mask = 0;
+ struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table;
+
+ for (i = dpm_table->count; i > 0; i--) {
+ mask = mask << 1;
+ if (dpm_table->dpm_level[i - 1].enabled)
+ mask |= 0x1;
+ else
+ mask &= 0xFFFFFFFE;
+ }
+
+ return mask;
+}
+
+uint8_t phm_get_voltage_index(
+ struct phm_ppt_v1_voltage_lookup_table *lookup_table, uint16_t voltage)
+{
+ uint8_t count = (uint8_t) (lookup_table->count);
+ uint8_t i;
+
+ PP_ASSERT_WITH_CODE((NULL != lookup_table),
+ "Lookup Table empty.", return 0);
+ PP_ASSERT_WITH_CODE((0 != count),
+ "Lookup Table empty.", return 0);
+
+ for (i = 0; i < lookup_table->count; i++) {
+ /* find first voltage equal or bigger than requested */
+ if (lookup_table->entries[i].us_vdd >= voltage)
+ return i;
+ }
+ /* voltage is bigger than max voltage in the table */
+ return i - 1;
+}
+
+uint8_t phm_get_voltage_id(pp_atomctrl_voltage_table *voltage_table,
+ uint32_t voltage)
+{
+ uint8_t count = (uint8_t) (voltage_table->count);
+ uint8_t i = 0;
+
+ PP_ASSERT_WITH_CODE((NULL != voltage_table),
+ "Voltage Table empty.", return 0;);
+ PP_ASSERT_WITH_CODE((0 != count),
+ "Voltage Table empty.", return 0;);
+
+ for (i = 0; i < count; i++) {
+ /* find first voltage bigger than requested */
+ if (voltage_table->entries[i].value >= voltage)
+ return i;
+ }
+
+ /* voltage is bigger than max voltage in the table */
+ return i - 1;
+}
+
+uint16_t phm_find_closest_vddci(struct pp_atomctrl_voltage_table *vddci_table, uint16_t vddci)
+{
+ uint32_t i;
+
+ for (i = 0; i < vddci_table->count; i++) {
+ if (vddci_table->entries[i].value >= vddci)
+ return vddci_table->entries[i].value;
+ }
+
+ pr_debug("vddci is larger than max value in vddci_table\n");
+ return vddci_table->entries[i-1].value;
+}
+
+int phm_find_boot_level(void *table,
+ uint32_t value, uint32_t *boot_level)
+{
+ int result = -EINVAL;
+ uint32_t i;
+ struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table;
+
+ for (i = 0; i < dpm_table->count; i++) {
+ if (value == dpm_table->dpm_level[i].value) {
+ *boot_level = i;
+ result = 0;
+ }
+ }
+
+ return result;
+}
+
+int phm_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr,
+ phm_ppt_v1_voltage_lookup_table *lookup_table,
+ uint16_t virtual_voltage_id, int32_t *sclk)
+{
+ uint8_t entry_id;
+ uint8_t voltage_id;
+ struct phm_ppt_v1_information *table_info =
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
+
+ PP_ASSERT_WITH_CODE(lookup_table->count != 0, "Lookup table is empty", return -EINVAL);
+
+ /* search for leakage voltage ID 0xff01 ~ 0xff08 and sckl */
+ for (entry_id = 0; entry_id < table_info->vdd_dep_on_sclk->count; entry_id++) {
+ voltage_id = table_info->vdd_dep_on_sclk->entries[entry_id].vddInd;
+ if (lookup_table->entries[voltage_id].us_vdd == virtual_voltage_id)
+ break;
+ }
+
+ if (entry_id >= table_info->vdd_dep_on_sclk->count) {
+ pr_debug("Can't find requested voltage id in vdd_dep_on_sclk table\n");
+ return -EINVAL;
+ }
+
+ *sclk = table_info->vdd_dep_on_sclk->entries[entry_id].clk;
+
+ return 0;
+}
+
+/**
+ * Initialize Dynamic State Adjustment Rule Settings
+ *
+ * @param hwmgr the address of the powerplay hardware manager.
+ */
+int phm_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr)
+{
+ uint32_t table_size;
+ struct phm_clock_voltage_dependency_table *table_clk_vlt;
+ struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
+
+ /* initialize vddc_dep_on_dal_pwrl table */
+ table_size = sizeof(uint32_t) + 4 * sizeof(struct phm_clock_voltage_dependency_record);
+ table_clk_vlt = kzalloc(table_size, GFP_KERNEL);
+
+ if (NULL == table_clk_vlt) {
+ pr_err("Can not allocate space for vddc_dep_on_dal_pwrl! \n");
+ return -ENOMEM;
+ } else {
+ table_clk_vlt->count = 4;
+ table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_ULTRALOW;
+ table_clk_vlt->entries[0].v = 0;
+ table_clk_vlt->entries[1].clk = PP_DAL_POWERLEVEL_LOW;
+ table_clk_vlt->entries[1].v = 720;
+ table_clk_vlt->entries[2].clk = PP_DAL_POWERLEVEL_NOMINAL;
+ table_clk_vlt->entries[2].v = 810;
+ table_clk_vlt->entries[3].clk = PP_DAL_POWERLEVEL_PERFORMANCE;
+ table_clk_vlt->entries[3].v = 900;
+ if (pptable_info != NULL)
+ pptable_info->vddc_dep_on_dal_pwrl = table_clk_vlt;
+ hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt;
+ }
+
+ return 0;
+}
+
+uint32_t phm_get_lowest_enabled_level(struct pp_hwmgr *hwmgr, uint32_t mask)
+{
+ uint32_t level = 0;
+
+ while (0 == (mask & (1 << level)))
+ level++;
+
+ return level;
+}
+
+void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr)
+{
+ struct phm_ppt_v1_information *table_info =
+ (struct phm_ppt_v1_information *)hwmgr->pptable;
+ struct phm_clock_voltage_dependency_table *table =
+ table_info->vddc_dep_on_dal_pwrl;
+ struct phm_ppt_v1_clock_voltage_dependency_table *vddc_table;
+ enum PP_DAL_POWERLEVEL dal_power_level = hwmgr->dal_power_level;
+ uint32_t req_vddc = 0, req_volt, i;
+
+ if (!table || table->count <= 0
+ || dal_power_level < PP_DAL_POWERLEVEL_ULTRALOW
+ || dal_power_level > PP_DAL_POWERLEVEL_PERFORMANCE)
+ return;
+
+ for (i = 0; i < table->count; i++) {
+ if (dal_power_level == table->entries[i].clk) {
+ req_vddc = table->entries[i].v;
+ break;
+ }
+ }
+
+ vddc_table = table_info->vdd_dep_on_sclk;
+ for (i = 0; i < vddc_table->count; i++) {
+ if (req_vddc <= vddc_table->entries[i].vddc) {
+ req_volt = (((uint32_t)vddc_table->entries[i].vddc) * VOLTAGE_SCALE);
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_VddC_Request, req_volt);
+ return;
+ }
+ }
+ pr_err("DAL requested level can not"
+ " found a available voltage in VDDC DPM Table \n");
+}
+
+int phm_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
+ uint32_t sclk, uint16_t id, uint16_t *voltage)
+{
+ uint32_t vol;
+ int ret = 0;
+
+ if (hwmgr->chip_id < CHIP_TONGA) {
+ ret = atomctrl_get_voltage_evv(hwmgr, id, voltage);
+ } else if (hwmgr->chip_id < CHIP_POLARIS10) {
+ ret = atomctrl_get_voltage_evv_on_sclk(hwmgr, voltage_type, sclk, id, voltage);
+ if (*voltage >= 2000 || *voltage == 0)
+ *voltage = 1150;
+ } else {
+ ret = atomctrl_get_voltage_evv_on_sclk_ai(hwmgr, voltage_type, sclk, id, &vol);
+ *voltage = (uint16_t)(vol/100);
+ }
+ return ret;
+}
+
+
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h b/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h
new file mode 100644
index 000000000000..a1a491300348
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h
@@ -0,0 +1,180 @@
+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#ifndef _SMU_HELPER_H_
+#define _SMU_HELPER_H_
+
+struct pp_atomctrl_voltage_table;
+struct pp_hwmgr;
+struct phm_ppt_v1_voltage_lookup_table;
+
+extern int phm_wait_for_register_unequal(struct pp_hwmgr *hwmgr,
+ uint32_t index,
+ uint32_t value, uint32_t mask);
+extern int phm_wait_for_indirect_register_unequal(
+ struct pp_hwmgr *hwmgr,
+ uint32_t indirect_port, uint32_t index,
+ uint32_t value, uint32_t mask);
+
+
+extern bool phm_cf_want_uvd_power_gating(struct pp_hwmgr *hwmgr);
+extern bool phm_cf_want_vce_power_gating(struct pp_hwmgr *hwmgr);
+extern bool phm_cf_want_microcode_fan_ctrl(struct pp_hwmgr *hwmgr);
+
+extern int phm_trim_voltage_table(struct pp_atomctrl_voltage_table *vol_table);
+extern int phm_get_svi2_mvdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_clock_voltage_dependency_table *dep_table);
+extern int phm_get_svi2_vddci_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_clock_voltage_dependency_table *dep_table);
+extern int phm_get_svi2_vdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_voltage_lookup_table *lookup_table);
+extern void phm_trim_voltage_table_to_fit_state_table(uint32_t max_vol_steps, struct pp_atomctrl_voltage_table *vol_table);
+extern int phm_reset_single_dpm_table(void *table, uint32_t count, int max);
+extern void phm_setup_pcie_table_entry(void *table, uint32_t index, uint32_t pcie_gen, uint32_t pcie_lanes);
+extern int32_t phm_get_dpm_level_enable_mask_value(void *table);
+extern uint8_t phm_get_voltage_id(struct pp_atomctrl_voltage_table *voltage_table,
+ uint32_t voltage);
+extern uint8_t phm_get_voltage_index(struct phm_ppt_v1_voltage_lookup_table *lookup_table, uint16_t voltage);
+extern uint16_t phm_find_closest_vddci(struct pp_atomctrl_voltage_table *vddci_table, uint16_t vddci);
+extern int phm_find_boot_level(void *table, uint32_t value, uint32_t *boot_level);
+extern int phm_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr, phm_ppt_v1_voltage_lookup_table *lookup_table,
+ uint16_t virtual_voltage_id, int32_t *sclk);
+extern int phm_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr);
+extern uint32_t phm_get_lowest_enabled_level(struct pp_hwmgr *hwmgr, uint32_t mask);
+extern void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr);
+
+extern int phm_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
+ uint32_t sclk, uint16_t id, uint16_t *voltage);
+
+extern uint32_t phm_set_field_to_u32(u32 offset, u32 original_data, u32 field, u32 size);
+
+extern int phm_wait_on_register(struct pp_hwmgr *hwmgr, uint32_t index,
+ uint32_t value, uint32_t mask);
+
+extern int phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr,
+ uint32_t indirect_port,
+ uint32_t index,
+ uint32_t value,
+ uint32_t mask);
+
+#define PHM_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
+#define PHM_FIELD_MASK(reg, field) reg##__##field##_MASK
+
+#define PHM_SET_FIELD(origval, reg, field, fieldval) \
+ (((origval) & ~PHM_FIELD_MASK(reg, field)) | \
+ (PHM_FIELD_MASK(reg, field) & ((fieldval) << PHM_FIELD_SHIFT(reg, field))))
+
+#define PHM_GET_FIELD(value, reg, field) \
+ (((value) & PHM_FIELD_MASK(reg, field)) >> \
+ PHM_FIELD_SHIFT(reg, field))
+
+
+/* Operations on named fields. */
+
+#define PHM_READ_FIELD(device, reg, field) \
+ PHM_GET_FIELD(cgs_read_register(device, mm##reg), reg, field)
+
+#define PHM_READ_INDIRECT_FIELD(device, port, reg, field) \
+ PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
+ reg, field)
+
+#define PHM_READ_VFPF_INDIRECT_FIELD(device, port, reg, field) \
+ PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
+ reg, field)
+
+#define PHM_WRITE_FIELD(device, reg, field, fieldval) \
+ cgs_write_register(device, mm##reg, PHM_SET_FIELD( \
+ cgs_read_register(device, mm##reg), reg, field, fieldval))
+
+#define PHM_WRITE_INDIRECT_FIELD(device, port, reg, field, fieldval) \
+ cgs_write_ind_register(device, port, ix##reg, \
+ PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
+ reg, field, fieldval))
+
+#define PHM_WRITE_VFPF_INDIRECT_FIELD(device, port, reg, field, fieldval) \
+ cgs_write_ind_register(device, port, ix##reg, \
+ PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
+ reg, field, fieldval))
+
+#define PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, index, value, mask) \
+ phm_wait_on_indirect_register(hwmgr, mm##port##_INDEX, index, value, mask)
+
+
+#define PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, value, mask) \
+ PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
+
+#define PHM_WAIT_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval) \
+ PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, (fieldval) \
+ << PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
+
+#define PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, index, value, mask) \
+ phm_wait_for_indirect_register_unequal(hwmgr, \
+ mm##port##_INDEX, index, value, mask)
+
+#define PHM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask) \
+ PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
+
+#define PHM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval) \
+ PHM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, \
+ (fieldval) << PHM_FIELD_SHIFT(reg, field), \
+ PHM_FIELD_MASK(reg, field) )
+
+
+#define PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, \
+ port, index, value, mask) \
+ phm_wait_for_indirect_register_unequal(hwmgr, \
+ mm##port##_INDEX_11, index, value, mask)
+
+#define PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask) \
+ PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
+
+#define PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval) \
+ PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, \
+ (fieldval) << PHM_FIELD_SHIFT(reg, field), \
+ PHM_FIELD_MASK(reg, field))
+
+
+#define PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, \
+ port, index, value, mask) \
+ phm_wait_on_indirect_register(hwmgr, \
+ mm##port##_INDEX_11, index, value, mask)
+
+#define PHM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, value, mask) \
+ PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
+
+#define PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval) \
+ PHM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, \
+ (fieldval) << PHM_FIELD_SHIFT(reg, field), \
+ PHM_FIELD_MASK(reg, field))
+
+#define PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, \
+ index, value, mask) \
+ phm_wait_for_register_unequal(hwmgr, \
+ index, value, mask)
+
+#define PHM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, value, mask) \
+ PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, \
+ mm##reg, value, mask)
+
+#define PHM_WAIT_FIELD_UNEQUAL(hwmgr, reg, field, fieldval) \
+ PHM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, \
+ (fieldval) << PHM_FIELD_SHIFT(reg, field), \
+ PHM_FIELD_MASK(reg, field))
+
+#endif /* _SMU_HELPER_H_ */
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index 2d55dabc77d4..2fcbb17b794d 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -44,11 +44,14 @@
#include "vega10_pptable.h"
#include "vega10_thermal.h"
#include "pp_debug.h"
-#include "pp_acpi.h"
#include "amd_pcie_helpers.h"
#include "cgs_linux.h"
#include "ppinterrupt.h"
#include "pp_overdriver.h"
+#include "pp_thermal.h"
+
+#include "smuio/smuio_9_0_offset.h"
+#include "smuio/smuio_9_0_sh_mask.h"
#define VOLTAGE_SCALE 4
#define VOLTAGE_VID_OFFSET_SCALE1 625
@@ -187,8 +190,7 @@ static int vega10_set_features_platform_caps(struct pp_hwmgr *hwmgr)
(struct vega10_hwmgr *)(hwmgr->backend);
struct phm_ppt_v2_information *table_info =
(struct phm_ppt_v2_information *)hwmgr->pptable;
- struct cgs_system_info sys_info = {0};
- int result;
+ struct amdgpu_device *adev = hwmgr->adev;
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SclkDeepSleep);
@@ -203,15 +205,11 @@ static int vega10_set_features_platform_caps(struct pp_hwmgr *hwmgr)
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_EnableSMU7ThermalManagement);
- sys_info.size = sizeof(struct cgs_system_info);
- sys_info.info_id = CGS_SYSTEM_INFO_PG_FLAGS;
- result = cgs_query_system_info(hwmgr->device, &sys_info);
-
- if (!result && (sys_info.value & AMD_PG_SUPPORT_UVD))
+ if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_UVDPowerGating);
- if (!result && (sys_info.value & AMD_PG_SUPPORT_VCE))
+ if (adev->pg_flags & AMD_PG_SUPPORT_VCE)
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_VCEPowerGating);
@@ -301,6 +299,8 @@ static void vega10_init_dpm_defaults(struct pp_hwmgr *hwmgr)
{
struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
int i;
+ uint32_t sub_vendor_id, hw_revision;
+ struct amdgpu_device *adev = hwmgr->adev;
vega10_initialize_power_tune_defaults(hwmgr);
@@ -365,6 +365,7 @@ static void vega10_init_dpm_defaults(struct pp_hwmgr *hwmgr)
FEATURE_FAN_CONTROL_BIT;
data->smu_features[GNLD_ACG].smu_feature_id = FEATURE_ACG_BIT;
data->smu_features[GNLD_DIDT].smu_feature_id = FEATURE_GFX_EDC_BIT;
+ data->smu_features[GNLD_PCC_LIMIT].smu_feature_id = FEATURE_PCC_LIMIT_CONTROL_BIT;
if (!data->registry_data.prefetcher_dpm_key_disabled)
data->smu_features[GNLD_DPM_PREFETCHER].supported = true;
@@ -434,6 +435,15 @@ static void vega10_init_dpm_defaults(struct pp_hwmgr *hwmgr)
if (data->registry_data.didt_support)
data->smu_features[GNLD_DIDT].supported = true;
+ hw_revision = adev->pdev->revision;
+ sub_vendor_id = adev->pdev->subsystem_vendor;
+
+ if ((hwmgr->chip_id == 0x6862 ||
+ hwmgr->chip_id == 0x6861 ||
+ hwmgr->chip_id == 0x6868) &&
+ (hw_revision == 0) &&
+ (sub_vendor_id != 0x1002))
+ data->smu_features[GNLD_PCC_LIMIT].supported = true;
}
#ifdef PPLIB_VEGA10_EVV_SUPPORT
@@ -747,7 +757,7 @@ static int vega10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
struct vega10_hwmgr *data;
uint32_t config_telemetry = 0;
struct pp_atomfwctrl_voltage_table vol_table;
- struct cgs_system_info sys_info = {0};
+ struct amdgpu_device *adev = hwmgr->adev;
uint32_t reg;
data = kzalloc(sizeof(struct vega10_hwmgr), GFP_KERNEL);
@@ -756,10 +766,12 @@ static int vega10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
hwmgr->backend = data;
- vega10_set_default_registry_data(hwmgr);
+ hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_VIDEO];
+ hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_VIDEO;
+ hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_VIDEO;
+ vega10_set_default_registry_data(hwmgr);
data->disable_dpm_mask = 0xff;
- data->workload_mask = 0xff;
/* need to set voltage control types before EVV patching */
data->vddc_control = VEGA10_VOLTAGE_CONTROL_NONE;
@@ -837,10 +849,7 @@ static int vega10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
hwmgr->platform_descriptor.clockStep.engineClock = 500;
hwmgr->platform_descriptor.clockStep.memoryClock = 500;
- sys_info.size = sizeof(struct cgs_system_info);
- sys_info.info_id = CGS_SYSTEM_INFO_GFX_CU_INFO;
- result = cgs_query_system_info(hwmgr->device, &sys_info);
- data->total_active_cus = sys_info.value;
+ data->total_active_cus = adev->gfx.cu_info.number;
/* Setup default Overdrive Fan control settings */
data->odn_fan_table.target_fan_speed =
hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM;
@@ -921,18 +930,9 @@ static int vega10_setup_asic_task(struct pp_hwmgr *hwmgr)
"Failed to set up led dpm config!",
return -EINVAL);
- return 0;
-}
-
-static bool vega10_is_dpm_running(struct pp_hwmgr *hwmgr)
-{
- uint32_t features_enabled;
+ smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_NumOfDisplays, 0);
- if (!vega10_get_smc_features(hwmgr, &features_enabled)) {
- if (features_enabled & SMC_DPM_FEATURES)
- return true;
- }
- return false;
+ return 0;
}
/**
@@ -1380,14 +1380,12 @@ static int vega10_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
if (PP_CAP(PHM_PlatformCaps_ODNinACSupport) ||
PP_CAP(PHM_PlatformCaps_ODNinDCSupport)) {
- data->odn_dpm_table.odn_core_clock_dpm_levels.
- number_of_performance_levels = data->dpm_table.gfx_table.count;
+ data->odn_dpm_table.odn_core_clock_dpm_levels.num_of_pl =
+ data->dpm_table.gfx_table.count;
for (i = 0; i < data->dpm_table.gfx_table.count; i++) {
- data->odn_dpm_table.odn_core_clock_dpm_levels.
- performance_level_entries[i].clock =
+ data->odn_dpm_table.odn_core_clock_dpm_levels.entries[i].clock =
data->dpm_table.gfx_table.dpm_levels[i].value;
- data->odn_dpm_table.odn_core_clock_dpm_levels.
- performance_level_entries[i].enabled = true;
+ data->odn_dpm_table.odn_core_clock_dpm_levels.entries[i].enabled = true;
}
data->odn_dpm_table.vdd_dependency_on_sclk.count =
@@ -1403,14 +1401,12 @@ static int vega10_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
dep_gfx_table->entries[i].cks_voffset;
}
- data->odn_dpm_table.odn_memory_clock_dpm_levels.
- number_of_performance_levels = data->dpm_table.mem_table.count;
+ data->odn_dpm_table.odn_memory_clock_dpm_levels.num_of_pl =
+ data->dpm_table.mem_table.count;
for (i = 0; i < data->dpm_table.mem_table.count; i++) {
- data->odn_dpm_table.odn_memory_clock_dpm_levels.
- performance_level_entries[i].clock =
+ data->odn_dpm_table.odn_memory_clock_dpm_levels.entries[i].clock =
data->dpm_table.mem_table.dpm_levels[i].value;
- data->odn_dpm_table.odn_memory_clock_dpm_levels.
- performance_level_entries[i].enabled = true;
+ data->odn_dpm_table.odn_memory_clock_dpm_levels.entries[i].enabled = true;
}
data->odn_dpm_table.vdd_dependency_on_mclk.count = dep_mclk_table->count;
@@ -2411,34 +2407,6 @@ static int vega10_populate_and_upload_avfs_fuse_override(struct pp_hwmgr *hwmgr)
return result;
}
-static int vega10_save_default_power_profile(struct pp_hwmgr *hwmgr)
-{
- struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
- struct vega10_single_dpm_table *dpm_table = &(data->dpm_table.gfx_table);
- uint32_t min_level;
-
- hwmgr->default_gfx_power_profile.type = AMD_PP_GFX_PROFILE;
- hwmgr->default_compute_power_profile.type = AMD_PP_COMPUTE_PROFILE;
-
- /* Optimize compute power profile: Use only highest
- * 2 power levels (if more than 2 are available)
- */
- if (dpm_table->count > 2)
- min_level = dpm_table->count - 2;
- else if (dpm_table->count == 2)
- min_level = 1;
- else
- min_level = 0;
-
- hwmgr->default_compute_power_profile.min_sclk =
- dpm_table->dpm_levels[min_level].value;
-
- hwmgr->gfx_power_profile = hwmgr->default_gfx_power_profile;
- hwmgr->compute_power_profile = hwmgr->default_compute_power_profile;
-
- return 0;
-}
-
/**
* Initializes the SMC table and uploads it
*
@@ -2582,7 +2550,6 @@ static int vega10_init_smc_table(struct pp_hwmgr *hwmgr)
PP_ASSERT_WITH_CODE(!result, "Attempt to enable AVFS feature Failed!",
return result);
vega10_acg_enable(hwmgr);
- vega10_save_default_power_profile(hwmgr);
return 0;
}
@@ -2859,34 +2826,39 @@ static int vega10_start_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap)
return 0;
}
-static int vega10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
+static int vega10_enable_disable_PCC_limit_feature(struct pp_hwmgr *hwmgr, bool enable)
{
struct vega10_hwmgr *data =
(struct vega10_hwmgr *)(hwmgr->backend);
- int tmp_result, result = 0;
- tmp_result = smum_send_msg_to_smc_with_parameter(hwmgr,
- PPSMC_MSG_ConfigureTelemetry, data->config_telemetry);
- PP_ASSERT_WITH_CODE(!tmp_result,
- "Failed to configure telemetry!",
- return tmp_result);
+ if (data->smu_features[GNLD_PCC_LIMIT].supported) {
+ if (enable == data->smu_features[GNLD_PCC_LIMIT].enabled)
+ pr_info("GNLD_PCC_LIMIT has been %s \n", enable ? "enabled" : "disabled");
+ PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
+ enable, data->smu_features[GNLD_PCC_LIMIT].smu_feature_bitmap),
+ "Attempt to Enable PCC Limit feature Failed!",
+ return -EINVAL);
+ data->smu_features[GNLD_PCC_LIMIT].enabled = enable;
+ }
- smum_send_msg_to_smc_with_parameter(hwmgr,
- PPSMC_MSG_NumOfDisplays, 0);
+ return 0;
+}
- tmp_result = (!vega10_is_dpm_running(hwmgr)) ? 0 : -1;
- PP_ASSERT_WITH_CODE(!tmp_result,
- "DPM is already running right , skipping re-enablement!",
- return 0);
+static int vega10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
+{
+ struct vega10_hwmgr *data =
+ (struct vega10_hwmgr *)(hwmgr->backend);
+ int tmp_result, result = 0;
+
+ vega10_enable_disable_PCC_limit_feature(hwmgr, true);
if ((hwmgr->smu_version == 0x001c2c00) ||
- (hwmgr->smu_version == 0x001c2d00)) {
- tmp_result = smum_send_msg_to_smc_with_parameter(hwmgr,
+ (hwmgr->smu_version == 0x001c2d00))
+ smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_UpdatePkgPwrPidAlpha, 1);
- PP_ASSERT_WITH_CODE(!tmp_result,
- "Failed to set package power PID!",
- return tmp_result);
- }
+
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_ConfigureTelemetry, data->config_telemetry);
tmp_result = vega10_construct_voltage_tables(hwmgr);
PP_ASSERT_WITH_CODE(!tmp_result,
@@ -3162,16 +3134,19 @@ static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
minimum_clocks.memoryClock = stable_pstate_mclk;
}
- disable_mclk_switching_for_frame_lock = phm_cap_enabled(
- hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
- disable_mclk_switching_for_vr = PP_CAP(PHM_PlatformCaps_DisableMclkSwitchForVR);
+ disable_mclk_switching_for_frame_lock =
+ PP_CAP(PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
+ disable_mclk_switching_for_vr =
+ PP_CAP(PHM_PlatformCaps_DisableMclkSwitchForVR);
force_mclk_high = PP_CAP(PHM_PlatformCaps_ForceMclkHigh);
- disable_mclk_switching = (info.display_count > 1) ||
- disable_mclk_switching_for_frame_lock ||
- disable_mclk_switching_for_vr ||
- force_mclk_high;
+ if (info.display_count == 0)
+ disable_mclk_switching = false;
+ else
+ disable_mclk_switching = (info.display_count > 1) ||
+ disable_mclk_switching_for_frame_lock ||
+ disable_mclk_switching_for_vr ||
+ force_mclk_high;
sclk = vega10_ps->performance_levels[0].gfx_clock;
mclk = vega10_ps->performance_levels[0].mem_clock;
@@ -3348,11 +3323,9 @@ static int vega10_populate_and_upload_sclk_mclk_dpm_levels(
dpm_count < dpm_table->gfx_table.count;
dpm_count++) {
dpm_table->gfx_table.dpm_levels[dpm_count].enabled =
- data->odn_dpm_table.odn_core_clock_dpm_levels.
- performance_level_entries[dpm_count].enabled;
+ data->odn_dpm_table.odn_core_clock_dpm_levels.entries[dpm_count].enabled;
dpm_table->gfx_table.dpm_levels[dpm_count].value =
- data->odn_dpm_table.odn_core_clock_dpm_levels.
- performance_level_entries[dpm_count].clock;
+ data->odn_dpm_table.odn_core_clock_dpm_levels.entries[dpm_count].clock;
}
}
@@ -3362,11 +3335,9 @@ static int vega10_populate_and_upload_sclk_mclk_dpm_levels(
dpm_count < dpm_table->mem_table.count;
dpm_count++) {
dpm_table->mem_table.dpm_levels[dpm_count].enabled =
- data->odn_dpm_table.odn_memory_clock_dpm_levels.
- performance_level_entries[dpm_count].enabled;
+ data->odn_dpm_table.odn_memory_clock_dpm_levels.entries[dpm_count].enabled;
dpm_table->mem_table.dpm_levels[dpm_count].value =
- data->odn_dpm_table.odn_memory_clock_dpm_levels.
- performance_level_entries[dpm_count].clock;
+ data->odn_dpm_table.odn_memory_clock_dpm_levels.entries[dpm_count].clock;
}
}
@@ -3398,8 +3369,7 @@ static int vega10_populate_and_upload_sclk_mclk_dpm_levels(
dpm_table->
gfx_table.dpm_levels[dpm_table->gfx_table.count - 1].
value = sclk;
- if (PP_CAP(PHM_PlatformCaps_OD6PlusinACSupport) ||
- PP_CAP(PHM_PlatformCaps_OD6PlusinDCSupport)) {
+ if (hwmgr->od_enabled) {
/* Need to do calculation based on the golden DPM table
* as the Heatmap GPU Clock axis is also based on
* the default values
@@ -3453,9 +3423,7 @@ static int vega10_populate_and_upload_sclk_mclk_dpm_levels(
mem_table.dpm_levels[dpm_table->mem_table.count - 1].
value = mclk;
- if (PP_CAP(PHM_PlatformCaps_OD6PlusinACSupport) ||
- PP_CAP(PHM_PlatformCaps_OD6PlusinDCSupport)) {
-
+ if (hwmgr->od_enabled) {
PP_ASSERT_WITH_CODE(
golden_dpm_table->mem_table.dpm_levels
[golden_dpm_table->mem_table.count - 1].value,
@@ -3643,12 +3611,9 @@ static int vega10_upload_dpm_bootup_level(struct pp_hwmgr *hwmgr)
if (!data->registry_data.sclk_dpm_key_disabled) {
if (data->smc_state_table.gfx_boot_level !=
data->dpm_table.gfx_table.dpm_state.soft_min_level) {
- PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter(
- hwmgr,
+ smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSoftMinGfxclkByIndex,
- data->smc_state_table.gfx_boot_level),
- "Failed to set soft min sclk index!",
- return -EINVAL);
+ data->smc_state_table.gfx_boot_level);
data->dpm_table.gfx_table.dpm_state.soft_min_level =
data->smc_state_table.gfx_boot_level;
}
@@ -3659,19 +3624,13 @@ static int vega10_upload_dpm_bootup_level(struct pp_hwmgr *hwmgr)
data->dpm_table.mem_table.dpm_state.soft_min_level) {
if (data->smc_state_table.mem_boot_level == NUM_UCLK_DPM_LEVELS - 1) {
socclk_idx = vega10_get_soc_index_for_max_uclk(hwmgr);
- PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter(
- hwmgr,
+ smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSoftMinSocclkByIndex,
- socclk_idx),
- "Failed to set soft min uclk index!",
- return -EINVAL);
+ socclk_idx);
} else {
- PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter(
- hwmgr,
+ smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSoftMinUclkByIndex,
- data->smc_state_table.mem_boot_level),
- "Failed to set soft min uclk index!",
- return -EINVAL);
+ data->smc_state_table.mem_boot_level);
}
data->dpm_table.mem_table.dpm_state.soft_min_level =
data->smc_state_table.mem_boot_level;
@@ -3690,13 +3649,10 @@ static int vega10_upload_dpm_max_level(struct pp_hwmgr *hwmgr)
if (!data->registry_data.sclk_dpm_key_disabled) {
if (data->smc_state_table.gfx_max_level !=
- data->dpm_table.gfx_table.dpm_state.soft_max_level) {
- PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter(
- hwmgr,
+ data->dpm_table.gfx_table.dpm_state.soft_max_level) {
+ smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSoftMaxGfxclkByIndex,
- data->smc_state_table.gfx_max_level),
- "Failed to set soft max sclk index!",
- return -EINVAL);
+ data->smc_state_table.gfx_max_level);
data->dpm_table.gfx_table.dpm_state.soft_max_level =
data->smc_state_table.gfx_max_level;
}
@@ -3704,13 +3660,10 @@ static int vega10_upload_dpm_max_level(struct pp_hwmgr *hwmgr)
if (!data->registry_data.mclk_dpm_key_disabled) {
if (data->smc_state_table.mem_max_level !=
- data->dpm_table.mem_table.dpm_state.soft_max_level) {
- PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter(
- hwmgr,
- PPSMC_MSG_SetSoftMaxUclkByIndex,
- data->smc_state_table.mem_max_level),
- "Failed to set soft max mclk index!",
- return -EINVAL);
+ data->dpm_table.mem_table.dpm_state.soft_max_level) {
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetSoftMaxUclkByIndex,
+ data->smc_state_table.mem_max_level);
data->dpm_table.mem_table.dpm_state.soft_max_level =
data->smc_state_table.mem_max_level;
}
@@ -3780,7 +3733,6 @@ static int vega10_update_sclk_threshold(struct pp_hwmgr *hwmgr)
{
struct vega10_hwmgr *data =
(struct vega10_hwmgr *)(hwmgr->backend);
- int result = 0;
uint32_t low_sclk_interrupt_threshold = 0;
if (PP_CAP(PHM_PlatformCaps_SclkThrottleLowNotification) &&
@@ -3792,12 +3744,12 @@ static int vega10_update_sclk_threshold(struct pp_hwmgr *hwmgr)
cpu_to_le32(low_sclk_interrupt_threshold);
/* This message will also enable SmcToHost Interrupt */
- result = smum_send_msg_to_smc_with_parameter(hwmgr,
+ smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetLowGfxclkInterruptThreshold,
(uint32_t)low_sclk_interrupt_threshold);
}
- return result;
+ return 0;
}
static int vega10_set_power_state_tasks(struct pp_hwmgr *hwmgr,
@@ -3888,13 +3840,11 @@ static int vega10_get_gpu_power(struct pp_hwmgr *hwmgr,
{
uint32_t value;
- PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
- PPSMC_MSG_GetCurrPkgPwr),
- "Failed to get current package power!",
- return -EINVAL);
-
+ smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrPkgPwr);
vega10_read_arg_from_smc(hwmgr, &value);
+
/* power value is an integer */
+ memset(query, 0, sizeof *query);
query->average_gpu_power = value << 8;
return 0;
@@ -3907,31 +3857,34 @@ static int vega10_read_sensor(struct pp_hwmgr *hwmgr, int idx,
struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
struct vega10_dpm_table *dpm_table = &data->dpm_table;
int ret = 0;
+ uint32_t reg, val_vid;
switch (idx) {
case AMDGPU_PP_SENSOR_GFX_SCLK:
- ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentGfxclkIndex);
- if (!ret) {
- vega10_read_arg_from_smc(hwmgr, &sclk_idx);
+ smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentGfxclkIndex);
+ vega10_read_arg_from_smc(hwmgr, &sclk_idx);
+ if (sclk_idx < dpm_table->gfx_table.count) {
*((uint32_t *)value) = dpm_table->gfx_table.dpm_levels[sclk_idx].value;
*size = 4;
+ } else {
+ ret = -EINVAL;
}
break;
case AMDGPU_PP_SENSOR_GFX_MCLK:
- ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentUclkIndex);
- if (!ret) {
- vega10_read_arg_from_smc(hwmgr, &mclk_idx);
+ smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentUclkIndex);
+ vega10_read_arg_from_smc(hwmgr, &mclk_idx);
+ if (mclk_idx < dpm_table->mem_table.count) {
*((uint32_t *)value) = dpm_table->mem_table.dpm_levels[mclk_idx].value;
*size = 4;
+ } else {
+ ret = -EINVAL;
}
break;
case AMDGPU_PP_SENSOR_GPU_LOAD:
- ret = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetAverageGfxActivity, 0);
- if (!ret) {
- vega10_read_arg_from_smc(hwmgr, &activity_percent);
- *((uint32_t *)value) = activity_percent > 100 ? 100 : activity_percent;
- *size = 4;
- }
+ smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetAverageGfxActivity, 0);
+ vega10_read_arg_from_smc(hwmgr, &activity_percent);
+ *((uint32_t *)value) = activity_percent > 100 ? 100 : activity_percent;
+ *size = 4;
break;
case AMDGPU_PP_SENSOR_GPU_TEMP:
*((uint32_t *)value) = vega10_thermal_get_temperature(hwmgr);
@@ -3953,17 +3906,27 @@ static int vega10_read_sensor(struct pp_hwmgr *hwmgr, int idx,
ret = vega10_get_gpu_power(hwmgr, (struct pp_gpu_power *)value);
}
break;
+ case AMDGPU_PP_SENSOR_VDDGFX:
+ reg = soc15_get_register_offset(SMUIO_HWID, 0,
+ mmSMUSVI0_PLANE0_CURRENTVID_BASE_IDX,
+ mmSMUSVI0_PLANE0_CURRENTVID);
+ val_vid = (cgs_read_register(hwmgr->device, reg) &
+ SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID_MASK) >>
+ SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID__SHIFT;
+ *((uint32_t *)value) = (uint32_t)convert_to_vddc((uint8_t)val_vid);
+ return 0;
default:
ret = -EINVAL;
break;
}
+
return ret;
}
-static int vega10_notify_smc_display_change(struct pp_hwmgr *hwmgr,
+static void vega10_notify_smc_display_change(struct pp_hwmgr *hwmgr,
bool has_disp)
{
- return smum_send_msg_to_smc_with_parameter(hwmgr,
+ smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetUclkFastSwitch,
has_disp ? 0 : 1);
}
@@ -3998,7 +3961,7 @@ int vega10_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
if (!result) {
clk_request = (clk_freq << 16) | clk_select;
- result = smum_send_msg_to_smc_with_parameter(hwmgr,
+ smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_RequestDisplayClockByFreq,
clk_request);
}
@@ -4067,10 +4030,9 @@ static int vega10_notify_smc_display_config_after_ps_adjustment(
clock_req.clock_type = amd_pp_dcef_clock;
clock_req.clock_freq_in_khz = dpm_table->dpm_levels[i].value;
if (!vega10_display_clock_voltage_request(hwmgr, &clock_req)) {
- PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter(
+ smum_send_msg_to_smc_with_parameter(
hwmgr, PPSMC_MSG_SetMinDeepSleepDcefclk,
- min_clocks.dcefClockInSR /100),
- "Attempt to set divider for DCEFCLK Failed!",);
+ min_clocks.dcefClockInSR / 100);
} else {
pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
}
@@ -4169,6 +4131,8 @@ static int vega10_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_fo
*sclk_mask = VEGA10_UMD_PSTATE_GFXCLK_LEVEL;
*soc_mask = VEGA10_UMD_PSTATE_SOCCLK_LEVEL;
*mclk_mask = VEGA10_UMD_PSTATE_MCLK_LEVEL;
+ hwmgr->pstate_sclk = table_info->vdd_dep_on_sclk->entries[VEGA10_UMD_PSTATE_GFXCLK_LEVEL].clk;
+ hwmgr->pstate_mclk = table_info->vdd_dep_on_mclk->entries[VEGA10_UMD_PSTATE_MCLK_LEVEL].clk;
}
if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
@@ -4210,6 +4174,9 @@ static int vega10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
uint32_t mclk_mask = 0;
uint32_t soc_mask = 0;
+ if (hwmgr->pstate_sclk == 0)
+ vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
+
switch (level) {
case AMD_DPM_FORCED_LEVEL_HIGH:
ret = vega10_force_dpm_highest(hwmgr);
@@ -4242,6 +4209,7 @@ static int vega10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
else if (level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
vega10_set_fan_control_mode(hwmgr, AMD_FAN_CTRL_AUTO);
}
+
return ret;
}
@@ -4488,26 +4456,11 @@ static int vega10_force_clock_level(struct pp_hwmgr *hwmgr,
enum pp_clock_type type, uint32_t mask)
{
struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
- int i;
-
- if (hwmgr->request_dpm_level & (AMD_DPM_FORCED_LEVEL_AUTO |
- AMD_DPM_FORCED_LEVEL_LOW |
- AMD_DPM_FORCED_LEVEL_HIGH))
- return -EINVAL;
switch (type) {
case PP_SCLK:
- for (i = 0; i < 32; i++) {
- if (mask & (1 << i))
- break;
- }
- data->smc_state_table.gfx_boot_level = i;
-
- for (i = 31; i >= 0; i--) {
- if (mask & (1 << i))
- break;
- }
- data->smc_state_table.gfx_max_level = i;
+ data->smc_state_table.gfx_boot_level = mask ? (ffs(mask) - 1) : 0;
+ data->smc_state_table.gfx_max_level = mask ? (fls(mask) - 1) : 0;
PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
"Failed to upload boot level to lowest!",
@@ -4519,17 +4472,8 @@ static int vega10_force_clock_level(struct pp_hwmgr *hwmgr,
break;
case PP_MCLK:
- for (i = 0; i < 32; i++) {
- if (mask & (1 << i))
- break;
- }
- data->smc_state_table.mem_boot_level = i;
-
- for (i = 31; i >= 0; i--) {
- if (mask & (1 << i))
- break;
- }
- data->smc_state_table.mem_max_level = i;
+ data->smc_state_table.mem_boot_level = mask ? (ffs(mask) - 1) : 0;
+ data->smc_state_table.mem_max_level = mask ? (fls(mask) - 1) : 0;
PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
"Failed to upload boot level to lowest!",
@@ -4563,14 +4507,8 @@ static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,
if (data->registry_data.sclk_dpm_key_disabled)
break;
- PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
- PPSMC_MSG_GetCurrentGfxclkIndex),
- "Attempt to get current sclk index Failed!",
- return -1);
- PP_ASSERT_WITH_CODE(!vega10_read_arg_from_smc(hwmgr,
- &now),
- "Attempt to read sclk index Failed!",
- return -1);
+ smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentGfxclkIndex);
+ vega10_read_arg_from_smc(hwmgr, &now);
for (i = 0; i < sclk_table->count; i++)
size += sprintf(buf + size, "%d: %uMhz %s\n",
@@ -4581,14 +4519,8 @@ static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,
if (data->registry_data.mclk_dpm_key_disabled)
break;
- PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
- PPSMC_MSG_GetCurrentUclkIndex),
- "Attempt to get current mclk index Failed!",
- return -1);
- PP_ASSERT_WITH_CODE(!vega10_read_arg_from_smc(hwmgr,
- &now),
- "Attempt to read mclk index Failed!",
- return -1);
+ smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentUclkIndex);
+ vega10_read_arg_from_smc(hwmgr, &now);
for (i = 0; i < mclk_table->count; i++)
size += sprintf(buf + size, "%d: %uMhz %s\n",
@@ -4596,14 +4528,8 @@ static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,
(i == now) ? "*" : "");
break;
case PP_PCIE:
- PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
- PPSMC_MSG_GetCurrentLinkIndex),
- "Attempt to get current mclk index Failed!",
- return -1);
- PP_ASSERT_WITH_CODE(!vega10_read_arg_from_smc(hwmgr,
- &now),
- "Attempt to read mclk index Failed!",
- return -1);
+ smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentLinkIndex);
+ vega10_read_arg_from_smc(hwmgr, &now);
for (i = 0; i < pcie_table->count; i++)
size += sprintf(buf + size, "%d: %s %s\n", i,
@@ -4744,11 +4670,6 @@ static int vega10_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
{
int tmp_result, result = 0;
- tmp_result = (vega10_is_dpm_running(hwmgr)) ? 0 : -1;
- PP_ASSERT_WITH_CODE(tmp_result == 0,
- "DPM is not running right now, no need to disable DPM!",
- return 0);
-
if (PP_CAP(PHM_PlatformCaps_ThermalController))
vega10_disable_thermal_protection(hwmgr);
@@ -4779,6 +4700,8 @@ static int vega10_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
tmp_result = vega10_acg_disable(hwmgr);
PP_ASSERT_WITH_CODE((tmp_result == 0),
"Failed to disable acg!", result = tmp_result);
+
+ vega10_enable_disable_PCC_limit_feature(hwmgr, false);
return result;
}
@@ -4796,68 +4719,6 @@ static int vega10_power_off_asic(struct pp_hwmgr *hwmgr)
return result;
}
-static void vega10_find_min_clock_index(struct pp_hwmgr *hwmgr,
- uint32_t *sclk_idx, uint32_t *mclk_idx,
- uint32_t min_sclk, uint32_t min_mclk)
-{
- struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
- struct vega10_dpm_table *dpm_table = &(data->dpm_table);
- uint32_t i;
-
- for (i = 0; i < dpm_table->gfx_table.count; i++) {
- if (dpm_table->gfx_table.dpm_levels[i].enabled &&
- dpm_table->gfx_table.dpm_levels[i].value >= min_sclk) {
- *sclk_idx = i;
- break;
- }
- }
-
- for (i = 0; i < dpm_table->mem_table.count; i++) {
- if (dpm_table->mem_table.dpm_levels[i].enabled &&
- dpm_table->mem_table.dpm_levels[i].value >= min_mclk) {
- *mclk_idx = i;
- break;
- }
- }
-}
-
-static int vega10_set_power_profile_state(struct pp_hwmgr *hwmgr,
- struct amd_pp_profile *request)
-{
- struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
- uint32_t sclk_idx = ~0, mclk_idx = ~0;
-
- if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_AUTO)
- return -EINVAL;
-
- vega10_find_min_clock_index(hwmgr, &sclk_idx, &mclk_idx,
- request->min_sclk, request->min_mclk);
-
- if (sclk_idx != ~0) {
- if (!data->registry_data.sclk_dpm_key_disabled)
- PP_ASSERT_WITH_CODE(
- !smum_send_msg_to_smc_with_parameter(
- hwmgr,
- PPSMC_MSG_SetSoftMinGfxclkByIndex,
- sclk_idx),
- "Failed to set soft min sclk index!",
- return -EINVAL);
- }
-
- if (mclk_idx != ~0) {
- if (!data->registry_data.mclk_dpm_key_disabled)
- PP_ASSERT_WITH_CODE(
- !smum_send_msg_to_smc_with_parameter(
- hwmgr,
- PPSMC_MSG_SetSoftMinUclkByIndex,
- mclk_idx),
- "Failed to set soft min mclk index!",
- return -EINVAL);
- }
-
- return 0;
-}
-
static int vega10_get_sclk_od(struct pp_hwmgr *hwmgr)
{
struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
@@ -4988,6 +4849,20 @@ static int vega10_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
return 0;
}
+static int vega10_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
+ struct PP_TemperatureRange *thermal_data)
+{
+ struct phm_ppt_v2_information *table_info =
+ (struct phm_ppt_v2_information *)hwmgr->pptable;
+
+ memcpy(thermal_data, &SMU7ThermalWithDelayPolicy[0], sizeof(struct PP_TemperatureRange));
+
+ thermal_data->max = table_info->tdp_table->usSoftwareShutdownTemp *
+ PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
+
+ return 0;
+}
+
static int vega10_register_thermal_interrupt(struct pp_hwmgr *hwmgr,
const void *info)
{
@@ -4999,12 +4874,12 @@ static int vega10_register_thermal_interrupt(struct pp_hwmgr *hwmgr,
hwmgr->thermal_controller.ucType ==
ATOM_VEGA10_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL) {
PP_ASSERT_WITH_CODE(!cgs_add_irq_source(hwmgr->device,
- 0xf, /* AMDGPU_IH_CLIENTID_THM */
+ SOC15_IH_CLIENTID_THM,
0, 0, irq_src[0].set, irq_src[0].handler, hwmgr),
"Failed to register high thermal interrupt!",
return -EINVAL);
PP_ASSERT_WITH_CODE(!cgs_add_irq_source(hwmgr->device,
- 0xf, /* AMDGPU_IH_CLIENTID_THM */
+ SOC15_IH_CLIENTID_THM,
1, 0, irq_src[1].set, irq_src[1].handler, hwmgr),
"Failed to register low thermal interrupt!",
return -EINVAL);
@@ -5012,7 +4887,7 @@ static int vega10_register_thermal_interrupt(struct pp_hwmgr *hwmgr,
/* Register CTF(GPIO_19) interrupt */
PP_ASSERT_WITH_CODE(!cgs_add_irq_source(hwmgr->device,
- 0x16, /* AMDGPU_IH_CLIENTID_ROM_SMUIO, */
+ SOC15_IH_CLIENTID_ROM_SMUIO,
83, 0, irq_src[2].set, irq_src[2].handler, hwmgr),
"Failed to register CTF thermal interrupt!",
return -EINVAL);
@@ -5020,6 +4895,77 @@ static int vega10_register_thermal_interrupt(struct pp_hwmgr *hwmgr,
return 0;
}
+static int vega10_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
+{
+ struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
+ uint32_t i, size = 0;
+ static const uint8_t profile_mode_setting[5][4] = {{70, 60, 1, 3,},
+ {90, 60, 0, 0,},
+ {70, 60, 0, 0,},
+ {70, 90, 0, 0,},
+ {30, 60, 0, 6,},
+ };
+ static const char *profile_name[6] = {"3D_FULL_SCREEN",
+ "POWER_SAVING",
+ "VIDEO",
+ "VR",
+ "COMPUTE",
+ "CUSTOM"};
+ static const char *title[6] = {"NUM",
+ "MODE_NAME",
+ "BUSY_SET_POINT",
+ "FPS",
+ "USE_RLC_BUSY",
+ "MIN_ACTIVE_LEVEL"};
+
+ if (!buf)
+ return -EINVAL;
+
+ size += sprintf(buf + size, "%s %16s %s %s %s %s\n",title[0],
+ title[1], title[2], title[3], title[4], title[5]);
+
+ for (i = 0; i < PP_SMC_POWER_PROFILE_CUSTOM; i++)
+ size += sprintf(buf + size, "%3d %14s%s: %14d %3d %10d %14d\n",
+ i, profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " ",
+ profile_mode_setting[i][0], profile_mode_setting[i][1],
+ profile_mode_setting[i][2], profile_mode_setting[i][3]);
+ size += sprintf(buf + size, "%3d %14s%s: %14d %3d %10d %14d\n", i,
+ profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " ",
+ data->custom_profile_mode[0], data->custom_profile_mode[1],
+ data->custom_profile_mode[2], data->custom_profile_mode[3]);
+ return size;
+}
+
+static int vega10_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size)
+{
+ struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
+ uint8_t busy_set_point;
+ uint8_t FPS;
+ uint8_t use_rlc_busy;
+ uint8_t min_active_level;
+
+ hwmgr->power_profile_mode = input[size];
+
+ smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetWorkloadMask,
+ 1<<hwmgr->power_profile_mode);
+
+ if (hwmgr->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
+ if (size == 0 || size > 4)
+ return -EINVAL;
+
+ data->custom_profile_mode[0] = busy_set_point = input[0];
+ data->custom_profile_mode[1] = FPS = input[1];
+ data->custom_profile_mode[2] = use_rlc_busy = input[2];
+ data->custom_profile_mode[3] = min_active_level = input[3];
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetCustomGfxDpmParameters,
+ busy_set_point | FPS<<8 |
+ use_rlc_busy << 16 | min_active_level<<24);
+ }
+
+ return 0;
+}
+
static const struct pp_hwmgr_func vega10_hwmgr_funcs = {
.backend_init = vega10_hwmgr_backend_init,
.backend_fini = vega10_hwmgr_backend_fini,
@@ -5038,7 +4984,6 @@ static const struct pp_hwmgr_func vega10_hwmgr_funcs = {
.notify_smc_display_config_after_ps_adjustment =
vega10_notify_smc_display_config_after_ps_adjustment,
.force_dpm_level = vega10_dpm_force_dpm_level,
- .get_temperature = vega10_thermal_get_temperature,
.stop_thermal_controller = vega10_thermal_stop_thermal_controller,
.get_fan_speed_info = vega10_fan_ctrl_get_fan_speed_info,
.get_fan_speed_percent = vega10_fan_ctrl_get_fan_speed_percent,
@@ -5067,15 +5012,18 @@ static const struct pp_hwmgr_func vega10_hwmgr_funcs = {
vega10_check_smc_update_required_for_display_configuration,
.power_off_asic = vega10_power_off_asic,
.disable_smc_firmware_ctf = vega10_thermal_disable_alert,
- .set_power_profile_state = vega10_set_power_profile_state,
.get_sclk_od = vega10_get_sclk_od,
.set_sclk_od = vega10_set_sclk_od,
.get_mclk_od = vega10_get_mclk_od,
.set_mclk_od = vega10_set_mclk_od,
.avfs_control = vega10_avfs_enable,
.notify_cac_buffer_info = vega10_notify_cac_buffer_info,
+ .get_thermal_temperature_range = vega10_get_thermal_temperature_range,
.register_internal_thermal_interrupt = vega10_register_thermal_interrupt,
.start_thermal_controller = vega10_start_thermal_controller,
+ .get_power_profile_mode = vega10_get_power_profile_mode,
+ .set_power_profile_mode = vega10_set_power_profile_mode,
+ .set_power_limit = vega10_set_power_limit,
};
int vega10_hwmgr_init(struct pp_hwmgr *hwmgr)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
index e8507ff8dbb3..8f6c2cb962da 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
@@ -66,6 +66,7 @@ enum {
GNLD_FEATURE_FAST_PPT_BIT,
GNLD_DIDT,
GNLD_ACG,
+ GNLD_PCC_LIMIT,
GNLD_FEATURES_MAX
};
@@ -189,12 +190,6 @@ struct vega10_vbios_boot_state {
uint32_t dcef_clock;
};
-#define DPMTABLE_OD_UPDATE_SCLK 0x00000001
-#define DPMTABLE_OD_UPDATE_MCLK 0x00000002
-#define DPMTABLE_UPDATE_SCLK 0x00000004
-#define DPMTABLE_UPDATE_MCLK 0x00000008
-#define DPMTABLE_OD_UPDATE_VDDC 0x00000010
-
struct vega10_smc_state_table {
uint32_t soc_boot_level;
uint32_t gfx_boot_level;
@@ -379,9 +374,6 @@ struct vega10_hwmgr {
/* ---- Overdrive next setting ---- */
uint32_t apply_overdrive_next_settings_mask;
- /* ---- Workload Mask ---- */
- uint32_t workload_mask;
-
/* ---- SMU9 ---- */
struct smu_features smu_features[GNLD_FEATURES_MAX];
struct vega10_smc_state_table smc_state_table;
@@ -389,6 +381,7 @@ struct vega10_hwmgr {
uint32_t config_telemetry;
uint32_t acg_loop_state;
uint32_t mem_channels;
+ uint8_t custom_profile_mode[4];
};
#define VEGA10_DPM2_NEAR_TDP_DEC 10
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c
index 598a194737a9..b1f74c7f0943 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c
@@ -850,7 +850,6 @@ static int vega10_program_gc_didt_config_registers(struct pp_hwmgr *hwmgr, const
static void vega10_didt_set_mask(struct pp_hwmgr *hwmgr, const bool enable)
{
uint32_t data;
- int result;
uint32_t en = (enable ? 1 : 0);
uint32_t didt_block_info = SQ_IR_MASK | TCP_IR_MASK | TD_PCC_MASK;
@@ -924,24 +923,20 @@ static void vega10_didt_set_mask(struct pp_hwmgr *hwmgr, const bool enable)
}
}
- if (enable) {
- /* For Vega10, SMC does not support any mask yet. */
- result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ConfigureGfxDidt, didt_block_info);
- PP_ASSERT((0 == result), "[EnableDiDtConfig] SMC Configure Gfx Didt Failed!");
- }
+ /* For Vega10, SMC does not support any mask yet. */
+ if (enable)
+ smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ConfigureGfxDidt, didt_block_info);
+
}
static int vega10_enable_cac_driving_se_didt_config(struct pp_hwmgr *hwmgr)
{
int result;
uint32_t num_se = 0, count, data;
- struct cgs_system_info sys_info = {0};
+ struct amdgpu_device *adev = hwmgr->adev;
uint32_t reg;
- sys_info.size = sizeof(struct cgs_system_info);
- sys_info.info_id = CGS_SYSTEM_INFO_GFX_SE_INFO;
- if (cgs_query_system_info(hwmgr->device, &sys_info) == 0)
- num_se = sys_info.value;
+ num_se = adev->gfx.config.max_shader_engines;
cgs_enter_safe_mode(hwmgr->device, true);
@@ -989,13 +984,10 @@ static int vega10_enable_psm_gc_didt_config(struct pp_hwmgr *hwmgr)
{
int result;
uint32_t num_se = 0, count, data;
- struct cgs_system_info sys_info = {0};
+ struct amdgpu_device *adev = hwmgr->adev;
uint32_t reg;
- sys_info.size = sizeof(struct cgs_system_info);
- sys_info.info_id = CGS_SYSTEM_INFO_GFX_SE_INFO;
- if (cgs_query_system_info(hwmgr->device, &sys_info) == 0)
- num_se = sys_info.value;
+ num_se = adev->gfx.config.max_shader_engines;
cgs_enter_safe_mode(hwmgr->device, true);
@@ -1054,13 +1046,10 @@ static int vega10_enable_se_edc_config(struct pp_hwmgr *hwmgr)
{
int result;
uint32_t num_se = 0, count, data;
- struct cgs_system_info sys_info = {0};
+ struct amdgpu_device *adev = hwmgr->adev;
uint32_t reg;
- sys_info.size = sizeof(struct cgs_system_info);
- sys_info.info_id = CGS_SYSTEM_INFO_GFX_SE_INFO;
- if (cgs_query_system_info(hwmgr->device, &sys_info) == 0)
- num_se = sys_info.value;
+ num_se = adev->gfx.config.max_shader_engines;
cgs_enter_safe_mode(hwmgr->device, true);
@@ -1105,13 +1094,10 @@ static int vega10_enable_psm_gc_edc_config(struct pp_hwmgr *hwmgr)
int result;
uint32_t num_se = 0;
uint32_t count, data;
- struct cgs_system_info sys_info = {0};
+ struct amdgpu_device *adev = hwmgr->adev;
uint32_t reg;
- sys_info.size = sizeof(struct cgs_system_info);
- sys_info.info_id = CGS_SYSTEM_INFO_GFX_SE_INFO;
- if (cgs_query_system_info(hwmgr->device, &sys_info) == 0)
- num_se = sys_info.value;
+ num_se = adev->gfx.config.max_shader_engines;
cgs_enter_safe_mode(hwmgr->device, true);
@@ -1344,7 +1330,7 @@ int vega10_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n)
(struct vega10_hwmgr *)(hwmgr->backend);
if (data->registry_data.enable_pkg_pwr_tracking_feature)
- return smum_send_msg_to_smc_with_parameter(hwmgr,
+ smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetPptLimit, n);
return 0;
@@ -1357,10 +1343,11 @@ int vega10_enable_power_containment(struct pp_hwmgr *hwmgr)
struct phm_ppt_v2_information *table_info =
(struct phm_ppt_v2_information *)(hwmgr->pptable);
struct phm_tdp_table *tdp_table = table_info->tdp_table;
- uint32_t default_pwr_limit =
- (uint32_t)(tdp_table->usMaximumPowerDeliveryLimit);
int result = 0;
+ hwmgr->default_power_limit = hwmgr->power_limit =
+ (uint32_t)(tdp_table->usMaximumPowerDeliveryLimit);
+
if (PP_CAP(PHM_PlatformCaps_PowerContainment)) {
if (data->smu_features[GNLD_PPT].supported)
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
@@ -1374,7 +1361,7 @@ int vega10_enable_power_containment(struct pp_hwmgr *hwmgr)
"Attempt to enable PPT feature Failed!",
data->smu_features[GNLD_TDC].supported = false);
- result = vega10_set_power_limit(hwmgr, default_pwr_limit);
+ result = vega10_set_power_limit(hwmgr, hwmgr->power_limit);
PP_ASSERT_WITH_CODE(!result,
"Failed to set Default Power Limit in SMC!",
return result);
@@ -1405,24 +1392,24 @@ int vega10_disable_power_containment(struct pp_hwmgr *hwmgr)
return 0;
}
-static int vega10_set_overdrive_target_percentage(struct pp_hwmgr *hwmgr,
+static void vega10_set_overdrive_target_percentage(struct pp_hwmgr *hwmgr,
uint32_t adjust_percent)
{
- return smum_send_msg_to_smc_with_parameter(hwmgr,
+ smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_OverDriveSetPercentage, adjust_percent);
}
int vega10_power_control_set_level(struct pp_hwmgr *hwmgr)
{
- int adjust_percent, result = 0;
+ int adjust_percent;
if (PP_CAP(PHM_PlatformCaps_PowerContainment)) {
adjust_percent =
hwmgr->platform_descriptor.TDPAdjustmentPolarity ?
hwmgr->platform_descriptor.TDPAdjustment :
(-1 * hwmgr->platform_descriptor.TDPAdjustment);
- result = vega10_set_overdrive_target_percentage(hwmgr,
+ vega10_set_overdrive_target_percentage(hwmgr,
(uint32_t)adjust_percent);
}
- return result;
+ return 0;
}
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c
index f14c7611fad3..c61d0744860d 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c
@@ -267,10 +267,10 @@ static int init_over_drive_limits(
hwmgr->platform_descriptor.maxOverdriveVDDC = 0;
hwmgr->platform_descriptor.overdriveVDDCStep = 0;
- if (hwmgr->platform_descriptor.overdriveLimit.engineClock > 0 &&
- hwmgr->platform_descriptor.overdriveLimit.memoryClock > 0) {
- phm_cap_set(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_ACOverdriveSupport);
+ if (hwmgr->platform_descriptor.overdriveLimit.engineClock == 0 ||
+ hwmgr->platform_descriptor.overdriveLimit.memoryClock == 0) {
+ hwmgr->od_enabled = false;
+ pr_debug("OverDrive feature not support by VBIOS\n");
}
return 0;
@@ -688,9 +688,9 @@ static int get_dcefclk_voltage_dependency_table(
uint8_t num_entries;
struct phm_ppt_v1_clock_voltage_dependency_table
*clk_table;
- struct cgs_system_info sys_info = {0};
uint32_t dev_id;
uint32_t rev_id;
+ struct amdgpu_device *adev = hwmgr->adev;
PP_ASSERT_WITH_CODE((clk_dep_table->ucNumEntries != 0),
"Invalid PowerPlay Table!", return -1);
@@ -701,15 +701,8 @@ static int get_dcefclk_voltage_dependency_table(
* This DPM level was added to support 3DPM monitors @ 4K120Hz
*
*/
- sys_info.size = sizeof(struct cgs_system_info);
- sys_info.info_id = CGS_SYSTEM_INFO_PCIE_DEV;
- cgs_query_system_info(hwmgr->device, &sys_info);
- dev_id = (uint32_t)sys_info.value;
-
- sys_info.size = sizeof(struct cgs_system_info);
- sys_info.info_id = CGS_SYSTEM_INFO_PCIE_REV;
- cgs_query_system_info(hwmgr->device, &sys_info);
- rev_id = (uint32_t)sys_info.value;
+ dev_id = adev->pdev->device;
+ rev_id = adev->pdev->revision;
if (dev_id == 0x6863 && rev_id == 0 &&
clk_dep_table->entries[clk_dep_table->ucNumEntries - 1].ulClk < 90000)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
index dc3761bcb9b6..fc2325e7f387 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
@@ -31,14 +31,8 @@
static int vega10_get_current_rpm(struct pp_hwmgr *hwmgr, uint32_t *current_rpm)
{
- PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
- PPSMC_MSG_GetCurrentRpm),
- "Attempt to get current RPM from SMC Failed!",
- return -1);
- PP_ASSERT_WITH_CODE(!vega10_read_arg_from_smc(hwmgr,
- current_rpm),
- "Attempt to read current RPM from SMC Failed!",
- return -1);
+ smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentRpm);
+ vega10_read_arg_from_smc(hwmgr, current_rpm);
return 0;
}
@@ -386,9 +380,9 @@ int vega10_thermal_get_temperature(struct pp_hwmgr *hwmgr)
static int vega10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
struct PP_TemperatureRange *range)
{
- uint32_t low = VEGA10_THERMAL_MINIMUM_ALERT_TEMP *
+ int low = VEGA10_THERMAL_MINIMUM_ALERT_TEMP *
PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
- uint32_t high = VEGA10_THERMAL_MAXIMUM_ALERT_TEMP *
+ int high = VEGA10_THERMAL_MAXIMUM_ALERT_TEMP *
PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
uint32_t val, reg;
@@ -409,7 +403,9 @@ static int vega10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
- val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
+ val &= (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK) &
+ (~THM_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK) &
+ (~THM_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK);
cgs_write_register(hwmgr->device, reg, val);