diff options
Diffstat (limited to 'drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c')
-rw-r--r-- | drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c | 57 |
1 files changed, 22 insertions, 35 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c index 598a194737a9..b1f74c7f0943 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c @@ -850,7 +850,6 @@ static int vega10_program_gc_didt_config_registers(struct pp_hwmgr *hwmgr, const static void vega10_didt_set_mask(struct pp_hwmgr *hwmgr, const bool enable) { uint32_t data; - int result; uint32_t en = (enable ? 1 : 0); uint32_t didt_block_info = SQ_IR_MASK | TCP_IR_MASK | TD_PCC_MASK; @@ -924,24 +923,20 @@ static void vega10_didt_set_mask(struct pp_hwmgr *hwmgr, const bool enable) } } - if (enable) { - /* For Vega10, SMC does not support any mask yet. */ - result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ConfigureGfxDidt, didt_block_info); - PP_ASSERT((0 == result), "[EnableDiDtConfig] SMC Configure Gfx Didt Failed!"); - } + /* For Vega10, SMC does not support any mask yet. */ + if (enable) + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ConfigureGfxDidt, didt_block_info); + } static int vega10_enable_cac_driving_se_didt_config(struct pp_hwmgr *hwmgr) { int result; uint32_t num_se = 0, count, data; - struct cgs_system_info sys_info = {0}; + struct amdgpu_device *adev = hwmgr->adev; uint32_t reg; - sys_info.size = sizeof(struct cgs_system_info); - sys_info.info_id = CGS_SYSTEM_INFO_GFX_SE_INFO; - if (cgs_query_system_info(hwmgr->device, &sys_info) == 0) - num_se = sys_info.value; + num_se = adev->gfx.config.max_shader_engines; cgs_enter_safe_mode(hwmgr->device, true); @@ -989,13 +984,10 @@ static int vega10_enable_psm_gc_didt_config(struct pp_hwmgr *hwmgr) { int result; uint32_t num_se = 0, count, data; - struct cgs_system_info sys_info = {0}; + struct amdgpu_device *adev = hwmgr->adev; uint32_t reg; - sys_info.size = sizeof(struct cgs_system_info); - sys_info.info_id = CGS_SYSTEM_INFO_GFX_SE_INFO; - if (cgs_query_system_info(hwmgr->device, &sys_info) == 0) - num_se = sys_info.value; + num_se = adev->gfx.config.max_shader_engines; cgs_enter_safe_mode(hwmgr->device, true); @@ -1054,13 +1046,10 @@ static int vega10_enable_se_edc_config(struct pp_hwmgr *hwmgr) { int result; uint32_t num_se = 0, count, data; - struct cgs_system_info sys_info = {0}; + struct amdgpu_device *adev = hwmgr->adev; uint32_t reg; - sys_info.size = sizeof(struct cgs_system_info); - sys_info.info_id = CGS_SYSTEM_INFO_GFX_SE_INFO; - if (cgs_query_system_info(hwmgr->device, &sys_info) == 0) - num_se = sys_info.value; + num_se = adev->gfx.config.max_shader_engines; cgs_enter_safe_mode(hwmgr->device, true); @@ -1105,13 +1094,10 @@ static int vega10_enable_psm_gc_edc_config(struct pp_hwmgr *hwmgr) int result; uint32_t num_se = 0; uint32_t count, data; - struct cgs_system_info sys_info = {0}; + struct amdgpu_device *adev = hwmgr->adev; uint32_t reg; - sys_info.size = sizeof(struct cgs_system_info); - sys_info.info_id = CGS_SYSTEM_INFO_GFX_SE_INFO; - if (cgs_query_system_info(hwmgr->device, &sys_info) == 0) - num_se = sys_info.value; + num_se = adev->gfx.config.max_shader_engines; cgs_enter_safe_mode(hwmgr->device, true); @@ -1344,7 +1330,7 @@ int vega10_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n) (struct vega10_hwmgr *)(hwmgr->backend); if (data->registry_data.enable_pkg_pwr_tracking_feature) - return smum_send_msg_to_smc_with_parameter(hwmgr, + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetPptLimit, n); return 0; @@ -1357,10 +1343,11 @@ int vega10_enable_power_containment(struct pp_hwmgr *hwmgr) struct phm_ppt_v2_information *table_info = (struct phm_ppt_v2_information *)(hwmgr->pptable); struct phm_tdp_table *tdp_table = table_info->tdp_table; - uint32_t default_pwr_limit = - (uint32_t)(tdp_table->usMaximumPowerDeliveryLimit); int result = 0; + hwmgr->default_power_limit = hwmgr->power_limit = + (uint32_t)(tdp_table->usMaximumPowerDeliveryLimit); + if (PP_CAP(PHM_PlatformCaps_PowerContainment)) { if (data->smu_features[GNLD_PPT].supported) PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, @@ -1374,7 +1361,7 @@ int vega10_enable_power_containment(struct pp_hwmgr *hwmgr) "Attempt to enable PPT feature Failed!", data->smu_features[GNLD_TDC].supported = false); - result = vega10_set_power_limit(hwmgr, default_pwr_limit); + result = vega10_set_power_limit(hwmgr, hwmgr->power_limit); PP_ASSERT_WITH_CODE(!result, "Failed to set Default Power Limit in SMC!", return result); @@ -1405,24 +1392,24 @@ int vega10_disable_power_containment(struct pp_hwmgr *hwmgr) return 0; } -static int vega10_set_overdrive_target_percentage(struct pp_hwmgr *hwmgr, +static void vega10_set_overdrive_target_percentage(struct pp_hwmgr *hwmgr, uint32_t adjust_percent) { - return smum_send_msg_to_smc_with_parameter(hwmgr, + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_OverDriveSetPercentage, adjust_percent); } int vega10_power_control_set_level(struct pp_hwmgr *hwmgr) { - int adjust_percent, result = 0; + int adjust_percent; if (PP_CAP(PHM_PlatformCaps_PowerContainment)) { adjust_percent = hwmgr->platform_descriptor.TDPAdjustmentPolarity ? hwmgr->platform_descriptor.TDPAdjustment : (-1 * hwmgr->platform_descriptor.TDPAdjustment); - result = vega10_set_overdrive_target_percentage(hwmgr, + vega10_set_overdrive_target_percentage(hwmgr, (uint32_t)adjust_percent); } - return result; + return 0; } |