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path: root/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
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Diffstat (limited to 'drivers/gpu/drm/amd/powerplay/amd_powerplay.c')
-rw-r--r--drivers/gpu/drm/amd/powerplay/amd_powerplay.c845
1 files changed, 385 insertions, 460 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index 4c3223a4d62b..3da3dccd13e2 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -27,79 +27,76 @@
#include <linux/slab.h>
#include "amd_shared.h"
#include "amd_powerplay.h"
-#include "pp_instance.h"
#include "power_state.h"
+#include "amdgpu.h"
+#include "hwmgr.h"
#define PP_DPM_DISABLED 0xCCCC
static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_task task_id,
- void *input, void *output);
+ enum amd_pm_state_type *user_state);
-static inline int pp_check(struct pp_instance *handle)
-{
- if (handle == NULL)
- return -EINVAL;
+static const struct amd_pm_funcs pp_dpm_funcs;
- if (handle->hwmgr == NULL || handle->hwmgr->smumgr_funcs == NULL)
+static inline int pp_check(struct pp_hwmgr *hwmgr)
+{
+ if (hwmgr == NULL || hwmgr->smumgr_funcs == NULL)
return -EINVAL;
- if (handle->pm_en == 0)
- return PP_DPM_DISABLED;
-
- if (handle->hwmgr->hwmgr_func == NULL)
+ if (hwmgr->pm_en == 0 || hwmgr->hwmgr_func == NULL)
return PP_DPM_DISABLED;
return 0;
}
-static int amd_powerplay_create(struct amd_pp_init *pp_init,
- void **handle)
+static int amd_powerplay_create(struct amdgpu_device *adev)
{
- struct pp_instance *instance;
+ struct pp_hwmgr *hwmgr;
- if (pp_init == NULL || handle == NULL)
+ if (adev == NULL)
return -EINVAL;
- instance = kzalloc(sizeof(struct pp_instance), GFP_KERNEL);
- if (instance == NULL)
+ hwmgr = kzalloc(sizeof(struct pp_hwmgr), GFP_KERNEL);
+ if (hwmgr == NULL)
return -ENOMEM;
- instance->chip_family = pp_init->chip_family;
- instance->chip_id = pp_init->chip_id;
- instance->pm_en = pp_init->pm_en;
- instance->feature_mask = pp_init->feature_mask;
- instance->device = pp_init->device;
- mutex_init(&instance->pp_lock);
- *handle = instance;
+ hwmgr->adev = adev;
+ hwmgr->pm_en = (amdgpu_dpm != 0 && !amdgpu_sriov_vf(adev)) ? true : false;
+ hwmgr->device = amdgpu_cgs_create_device(adev);
+ mutex_init(&hwmgr->smu_lock);
+ hwmgr->chip_family = adev->family;
+ hwmgr->chip_id = adev->asic_type;
+ hwmgr->feature_mask = amdgpu_pp_feature_mask;
+ adev->powerplay.pp_handle = hwmgr;
+ adev->powerplay.pp_funcs = &pp_dpm_funcs;
return 0;
}
-static int amd_powerplay_destroy(void *handle)
+
+static int amd_powerplay_destroy(struct amdgpu_device *adev)
{
- struct pp_instance *instance = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
- kfree(instance->hwmgr->hardcode_pp_table);
- instance->hwmgr->hardcode_pp_table = NULL;
+ kfree(hwmgr->hardcode_pp_table);
+ hwmgr->hardcode_pp_table = NULL;
- kfree(instance->hwmgr);
- instance->hwmgr = NULL;
+ kfree(hwmgr);
+ hwmgr = NULL;
- kfree(instance);
- instance = NULL;
return 0;
}
static int pp_early_init(void *handle)
{
int ret;
- struct pp_instance *pp_handle = NULL;
+ struct amdgpu_device *adev = handle;
- pp_handle = cgs_register_pp_handle(handle, amd_powerplay_create);
+ ret = amd_powerplay_create(adev);
- if (!pp_handle)
- return -EINVAL;
+ if (ret != 0)
+ return ret;
- ret = hwmgr_early_init(pp_handle);
+ ret = hwmgr_early_init(adev->powerplay.pp_handle);
if (ret)
return -EINVAL;
@@ -108,15 +105,13 @@ static int pp_early_init(void *handle)
static int pp_sw_init(void *handle)
{
- struct pp_hwmgr *hwmgr;
+ struct amdgpu_device *adev = handle;
+ struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
int ret = 0;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret >= 0) {
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->smumgr_funcs->smu_init == NULL)
return -EINVAL;
@@ -124,55 +119,57 @@ static int pp_sw_init(void *handle)
pr_debug("amdgpu: powerplay sw initialized\n");
}
+
return ret;
}
static int pp_sw_fini(void *handle)
{
- struct pp_hwmgr *hwmgr;
+ struct amdgpu_device *adev = handle;
+ struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
int ret = 0;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret >= 0) {
- hwmgr = pp_handle->hwmgr;
+ if (hwmgr->smumgr_funcs->smu_fini != NULL)
+ hwmgr->smumgr_funcs->smu_fini(hwmgr);
+ }
- if (hwmgr->smumgr_funcs->smu_fini == NULL)
- return -EINVAL;
+ if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
+ amdgpu_ucode_fini_bo(adev);
- ret = hwmgr->smumgr_funcs->smu_fini(pp_handle->hwmgr);
- }
- return ret;
+ return 0;
}
static int pp_hw_init(void *handle)
{
int ret = 0;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
- struct pp_hwmgr *hwmgr;
+ struct amdgpu_device *adev = handle;
+ struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
- ret = pp_check(pp_handle);
+ if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
+ amdgpu_ucode_init_bo(adev);
- if (ret >= 0) {
- hwmgr = pp_handle->hwmgr;
+ ret = pp_check(hwmgr);
+ if (ret >= 0) {
if (hwmgr->smumgr_funcs->start_smu == NULL)
return -EINVAL;
- if(hwmgr->smumgr_funcs->start_smu(pp_handle->hwmgr)) {
+ if (hwmgr->smumgr_funcs->start_smu(hwmgr)) {
pr_err("smc start failed\n");
- hwmgr->smumgr_funcs->smu_fini(pp_handle->hwmgr);
- return -EINVAL;;
+ hwmgr->smumgr_funcs->smu_fini(hwmgr);
+ return -EINVAL;
}
if (ret == PP_DPM_DISABLED)
goto exit;
- ret = hwmgr_hw_init(pp_handle);
+ ret = hwmgr_hw_init(hwmgr);
if (ret)
goto exit;
}
return ret;
exit:
- pp_handle->pm_en = 0;
+ hwmgr->pm_en = 0;
cgs_notify_dpm_enabled(hwmgr->device, false);
return 0;
@@ -180,32 +177,37 @@ exit:
static int pp_hw_fini(void *handle)
{
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct amdgpu_device *adev = handle;
+ struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret == 0)
- hwmgr_hw_fini(pp_handle);
+ hwmgr_hw_fini(hwmgr);
return 0;
}
static int pp_late_init(void *handle)
{
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct amdgpu_device *adev = handle;
+ struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
+
if (ret == 0)
- pp_dpm_dispatch_tasks(pp_handle,
- AMD_PP_TASK_COMPLETE_INIT, NULL, NULL);
+ pp_dpm_dispatch_tasks(hwmgr,
+ AMD_PP_TASK_COMPLETE_INIT, NULL);
return 0;
}
static void pp_late_fini(void *handle)
{
- amd_powerplay_destroy(handle);
+ struct amdgpu_device *adev = handle;
+
+ amd_powerplay_destroy(adev);
}
@@ -227,17 +229,15 @@ static int pp_sw_reset(void *handle)
static int pp_set_powergating_state(void *handle,
enum amd_powergating_state state)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct amdgpu_device *adev = handle;
+ struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->hwmgr_func->enable_per_cu_power_gating == NULL) {
pr_info("%s was not implemented.\n", __func__);
return 0;
@@ -250,44 +250,43 @@ static int pp_set_powergating_state(void *handle,
static int pp_suspend(void *handle)
{
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct amdgpu_device *adev = handle;
+ struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret == 0)
- hwmgr_hw_suspend(pp_handle);
+ hwmgr_hw_suspend(hwmgr);
return 0;
}
static int pp_resume(void *handle)
{
- struct pp_hwmgr *hwmgr;
+ struct amdgpu_device *adev = handle;
+ struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
int ret;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret < 0)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->smumgr_funcs->start_smu == NULL)
return -EINVAL;
- if (hwmgr->smumgr_funcs->start_smu(pp_handle->hwmgr)) {
+ if (hwmgr->smumgr_funcs->start_smu(hwmgr)) {
pr_err("smc start failed\n");
- hwmgr->smumgr_funcs->smu_fini(pp_handle->hwmgr);
+ hwmgr->smumgr_funcs->smu_fini(hwmgr);
return -EINVAL;
}
if (ret == PP_DPM_DISABLED)
return 0;
- return hwmgr_hw_resume(pp_handle);
+ return hwmgr_hw_resume(hwmgr);
}
-const struct amd_ip_funcs pp_ip_funcs = {
+static const struct amd_ip_funcs pp_ip_funcs = {
.name = "powerplay",
.early_init = pp_early_init,
.late_init = pp_late_init,
@@ -305,6 +304,15 @@ const struct amd_ip_funcs pp_ip_funcs = {
.set_powergating_state = pp_set_powergating_state,
};
+const struct amdgpu_ip_block_version pp_smu_ip_block =
+{
+ .type = AMD_IP_BLOCK_TYPE_SMC,
+ .major = 1,
+ .minor = 0,
+ .rev = 0,
+ .funcs = &pp_ip_funcs,
+};
+
static int pp_dpm_load_fw(void *handle)
{
return 0;
@@ -317,17 +325,14 @@ static int pp_dpm_fw_loading_complete(void *handle)
static int pp_set_clockgating_by_smu(void *handle, uint32_t msg_id)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->hwmgr_func->update_clock_gatings == NULL) {
pr_info("%s was not implemented.\n", __func__);
return 0;
@@ -375,25 +380,22 @@ static void pp_dpm_en_umd_pstate(struct pp_hwmgr *hwmgr,
static int pp_dpm_force_performance_level(void *handle,
enum amd_dpm_forced_level level)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (level == hwmgr->dpm_level)
return 0;
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
pp_dpm_en_umd_pstate(hwmgr, &level);
hwmgr->request_dpm_level = level;
- hwmgr_handle_task(pp_handle, AMD_PP_TASK_READJUST_POWER_STATE, NULL, NULL);
- mutex_unlock(&pp_handle->pp_lock);
+ hwmgr_handle_task(hwmgr, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
+ mutex_unlock(&hwmgr->smu_lock);
return 0;
}
@@ -401,152 +403,135 @@ static int pp_dpm_force_performance_level(void *handle,
static enum amd_dpm_forced_level pp_dpm_get_performance_level(
void *handle)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
enum amd_dpm_forced_level level;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
level = hwmgr->dpm_level;
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return level;
}
static uint32_t pp_dpm_get_sclk(void *handle, bool low)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
uint32_t clk = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->hwmgr_func->get_sclk == NULL) {
pr_info("%s was not implemented.\n", __func__);
return 0;
}
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
clk = hwmgr->hwmgr_func->get_sclk(hwmgr, low);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return clk;
}
static uint32_t pp_dpm_get_mclk(void *handle, bool low)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
uint32_t clk = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->hwmgr_func->get_mclk == NULL) {
pr_info("%s was not implemented.\n", __func__);
return 0;
}
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
clk = hwmgr->hwmgr_func->get_mclk(hwmgr, low);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return clk;
}
static void pp_dpm_powergate_vce(void *handle, bool gate)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->hwmgr_func->powergate_vce == NULL) {
pr_info("%s was not implemented.\n", __func__);
return;
}
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
hwmgr->hwmgr_func->powergate_vce(hwmgr, gate);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
}
static void pp_dpm_powergate_uvd(void *handle, bool gate)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->hwmgr_func->powergate_uvd == NULL) {
pr_info("%s was not implemented.\n", __func__);
return;
}
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
}
static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_task task_id,
- void *input, void *output)
+ enum amd_pm_state_type *user_state)
{
int ret = 0;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- mutex_lock(&pp_handle->pp_lock);
- ret = hwmgr_handle_task(pp_handle, task_id, input, output);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
+ ret = hwmgr_handle_task(hwmgr, task_id, user_state);
+ mutex_unlock(&hwmgr->smu_lock);
return ret;
}
static enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle)
{
- struct pp_hwmgr *hwmgr;
+ struct pp_hwmgr *hwmgr = handle;
struct pp_power_state *state;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
int ret = 0;
enum amd_pm_state_type pm_type;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->current_ps == NULL)
return -EINVAL;
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
state = hwmgr->current_ps;
@@ -567,170 +552,129 @@ static enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle)
pm_type = POWER_STATE_TYPE_DEFAULT;
break;
}
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return pm_type;
}
static void pp_dpm_set_fan_control_mode(void *handle, uint32_t mode)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->hwmgr_func->set_fan_control_mode == NULL) {
pr_info("%s was not implemented.\n", __func__);
return;
}
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
hwmgr->hwmgr_func->set_fan_control_mode(hwmgr, mode);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
}
static uint32_t pp_dpm_get_fan_control_mode(void *handle)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
uint32_t mode = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->hwmgr_func->get_fan_control_mode == NULL) {
pr_info("%s was not implemented.\n", __func__);
return 0;
}
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
mode = hwmgr->hwmgr_func->get_fan_control_mode(hwmgr);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return mode;
}
static int pp_dpm_set_fan_speed_percent(void *handle, uint32_t percent)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->hwmgr_func->set_fan_speed_percent == NULL) {
pr_info("%s was not implemented.\n", __func__);
return 0;
}
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
ret = hwmgr->hwmgr_func->set_fan_speed_percent(hwmgr, percent);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return ret;
}
static int pp_dpm_get_fan_speed_percent(void *handle, uint32_t *speed)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->hwmgr_func->get_fan_speed_percent == NULL) {
pr_info("%s was not implemented.\n", __func__);
return 0;
}
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
ret = hwmgr->hwmgr_func->get_fan_speed_percent(hwmgr, speed);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return ret;
}
static int pp_dpm_get_fan_speed_rpm(void *handle, uint32_t *rpm)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->hwmgr_func->get_fan_speed_rpm == NULL)
return -EINVAL;
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
ret = hwmgr->hwmgr_func->get_fan_speed_rpm(hwmgr, rpm);
- mutex_unlock(&pp_handle->pp_lock);
- return ret;
-}
-
-static int pp_dpm_get_temperature(void *handle)
-{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
- int ret = 0;
-
- ret = pp_check(pp_handle);
-
- if (ret)
- return ret;
-
- hwmgr = pp_handle->hwmgr;
-
- if (hwmgr->hwmgr_func->get_temperature == NULL) {
- pr_info("%s was not implemented.\n", __func__);
- return 0;
- }
- mutex_lock(&pp_handle->pp_lock);
- ret = hwmgr->hwmgr_func->get_temperature(hwmgr);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return ret;
}
static int pp_dpm_get_pp_num_states(void *handle,
struct pp_states_info *data)
{
- struct pp_hwmgr *hwmgr;
+ struct pp_hwmgr *hwmgr = handle;
int i;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
int ret = 0;
memset(data, 0, sizeof(*data));
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->ps == NULL)
return -EINVAL;
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
data->nums = hwmgr->num_ps;
@@ -754,73 +698,68 @@ static int pp_dpm_get_pp_num_states(void *handle,
data->states[i] = POWER_STATE_TYPE_DEFAULT;
}
}
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return 0;
}
static int pp_dpm_get_pp_table(void *handle, char **table)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
int size = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (!hwmgr->soft_pp_table)
return -EINVAL;
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
*table = (char *)hwmgr->soft_pp_table;
size = hwmgr->soft_pp_table_size;
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return size;
}
static int amd_powerplay_reset(void *handle)
{
- struct pp_instance *instance = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret;
- ret = pp_check(instance);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- ret = pp_hw_fini(instance);
+ ret = pp_hw_fini(hwmgr);
if (ret)
return ret;
- ret = hwmgr_hw_init(instance);
+ ret = hwmgr_hw_init(hwmgr);
if (ret)
return ret;
- return hwmgr_handle_task(instance, AMD_PP_TASK_COMPLETE_INIT, NULL, NULL);
+ return hwmgr_handle_task(hwmgr, AMD_PP_TASK_COMPLETE_INIT, NULL);
}
static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t size)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
if (!hwmgr->hardcode_pp_table) {
hwmgr->hardcode_pp_table = kmemdup(hwmgr->soft_pp_table,
hwmgr->soft_pp_table_size,
GFP_KERNEL);
if (!hwmgr->hardcode_pp_table) {
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return -ENOMEM;
}
}
@@ -828,7 +767,7 @@ static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t size)
memcpy(hwmgr->hardcode_pp_table, buf, size);
hwmgr->soft_pp_table = hwmgr->hardcode_pp_table;
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
ret = amd_powerplay_reset(handle);
if (ret)
@@ -846,317 +785,258 @@ static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t size)
static int pp_dpm_force_clock_level(void *handle,
enum pp_clock_type type, uint32_t mask)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->hwmgr_func->force_clock_level == NULL) {
pr_info("%s was not implemented.\n", __func__);
return 0;
}
- mutex_lock(&pp_handle->pp_lock);
- hwmgr->hwmgr_func->force_clock_level(hwmgr, type, mask);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
+ if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)
+ ret = hwmgr->hwmgr_func->force_clock_level(hwmgr, type, mask);
+ else
+ ret = -EINVAL;
+ mutex_unlock(&hwmgr->smu_lock);
return ret;
}
static int pp_dpm_print_clock_levels(void *handle,
enum pp_clock_type type, char *buf)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->hwmgr_func->print_clock_levels == NULL) {
pr_info("%s was not implemented.\n", __func__);
return 0;
}
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
ret = hwmgr->hwmgr_func->print_clock_levels(hwmgr, type, buf);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return ret;
}
static int pp_dpm_get_sclk_od(void *handle)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->hwmgr_func->get_sclk_od == NULL) {
pr_info("%s was not implemented.\n", __func__);
return 0;
}
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
ret = hwmgr->hwmgr_func->get_sclk_od(hwmgr);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return ret;
}
static int pp_dpm_set_sclk_od(void *handle, uint32_t value)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->hwmgr_func->set_sclk_od == NULL) {
pr_info("%s was not implemented.\n", __func__);
return 0;
}
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
ret = hwmgr->hwmgr_func->set_sclk_od(hwmgr, value);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return ret;
}
static int pp_dpm_get_mclk_od(void *handle)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->hwmgr_func->get_mclk_od == NULL) {
pr_info("%s was not implemented.\n", __func__);
return 0;
}
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
ret = hwmgr->hwmgr_func->get_mclk_od(hwmgr);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return ret;
}
static int pp_dpm_set_mclk_od(void *handle, uint32_t value)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->hwmgr_func->set_mclk_od == NULL) {
pr_info("%s was not implemented.\n", __func__);
return 0;
}
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
ret = hwmgr->hwmgr_func->set_mclk_od(hwmgr, value);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return ret;
}
static int pp_dpm_read_sensor(void *handle, int idx,
void *value, int *size)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
-
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
+ if (value == NULL)
+ return -EINVAL;
- if (hwmgr->hwmgr_func->read_sensor == NULL) {
- pr_info("%s was not implemented.\n", __func__);
+ switch (idx) {
+ case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
+ *((uint32_t *)value) = hwmgr->pstate_sclk;
+ return 0;
+ case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK:
+ *((uint32_t *)value) = hwmgr->pstate_mclk;
return 0;
+ default:
+ mutex_lock(&hwmgr->smu_lock);
+ ret = hwmgr->hwmgr_func->read_sensor(hwmgr, idx, value, size);
+ mutex_unlock(&hwmgr->smu_lock);
+ return ret;
}
-
- mutex_lock(&pp_handle->pp_lock);
- ret = hwmgr->hwmgr_func->read_sensor(hwmgr, idx, value, size);
- mutex_unlock(&pp_handle->pp_lock);
-
- return ret;
}
static struct amd_vce_state*
pp_dpm_get_vce_clock_state(void *handle, unsigned idx)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return NULL;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr && idx < hwmgr->num_vce_state_tables)
return &hwmgr->vce_states[idx];
return NULL;
}
-static int pp_dpm_reset_power_profile_state(void *handle,
- struct amd_pp_profile *request)
+static int pp_get_power_profile_mode(void *handle, char *buf)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
- if (!request || pp_check(pp_handle))
+ if (!buf || pp_check(hwmgr))
return -EINVAL;
- hwmgr = pp_handle->hwmgr;
-
- if (hwmgr->hwmgr_func->set_power_profile_state == NULL) {
+ if (hwmgr->hwmgr_func->get_power_profile_mode == NULL) {
pr_info("%s was not implemented.\n", __func__);
- return 0;
+ return snprintf(buf, PAGE_SIZE, "\n");
}
- if (request->type == AMD_PP_GFX_PROFILE) {
- hwmgr->gfx_power_profile = hwmgr->default_gfx_power_profile;
- return hwmgr->hwmgr_func->set_power_profile_state(hwmgr,
- &hwmgr->gfx_power_profile);
- } else if (request->type == AMD_PP_COMPUTE_PROFILE) {
- hwmgr->compute_power_profile =
- hwmgr->default_compute_power_profile;
- return hwmgr->hwmgr_func->set_power_profile_state(hwmgr,
- &hwmgr->compute_power_profile);
- } else
- return -EINVAL;
+ return hwmgr->hwmgr_func->get_power_profile_mode(hwmgr, buf);
}
-static int pp_dpm_get_power_profile_state(void *handle,
- struct amd_pp_profile *query)
+static int pp_set_power_profile_mode(void *handle, long *input, uint32_t size)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
+ int ret = -EINVAL;
- if (!query || pp_check(pp_handle))
+ if (pp_check(hwmgr))
return -EINVAL;
- hwmgr = pp_handle->hwmgr;
-
- if (query->type == AMD_PP_GFX_PROFILE)
- memcpy(query, &hwmgr->gfx_power_profile,
- sizeof(struct amd_pp_profile));
- else if (query->type == AMD_PP_COMPUTE_PROFILE)
- memcpy(query, &hwmgr->compute_power_profile,
- sizeof(struct amd_pp_profile));
- else
+ if (hwmgr->hwmgr_func->set_power_profile_mode == NULL) {
+ pr_info("%s was not implemented.\n", __func__);
return -EINVAL;
-
- return 0;
+ }
+ mutex_lock(&hwmgr->smu_lock);
+ if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)
+ ret = hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, input, size);
+ mutex_unlock(&hwmgr->smu_lock);
+ return ret;
}
-static int pp_dpm_set_power_profile_state(void *handle,
- struct amd_pp_profile *request)
+static int pp_odn_edit_dpm_table(void *handle, uint32_t type, long *input, uint32_t size)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
- int ret = -1;
+ struct pp_hwmgr *hwmgr = handle;
- if (!request || pp_check(pp_handle))
+ if (pp_check(hwmgr))
return -EINVAL;
- hwmgr = pp_handle->hwmgr;
-
- if (hwmgr->hwmgr_func->set_power_profile_state == NULL) {
+ if (hwmgr->hwmgr_func->odn_edit_dpm_table == NULL) {
pr_info("%s was not implemented.\n", __func__);
- return 0;
- }
-
- if (request->min_sclk ||
- request->min_mclk ||
- request->activity_threshold ||
- request->up_hyst ||
- request->down_hyst) {
- if (request->type == AMD_PP_GFX_PROFILE)
- memcpy(&hwmgr->gfx_power_profile, request,
- sizeof(struct amd_pp_profile));
- else if (request->type == AMD_PP_COMPUTE_PROFILE)
- memcpy(&hwmgr->compute_power_profile, request,
- sizeof(struct amd_pp_profile));
- else
- return -EINVAL;
-
- if (request->type == hwmgr->current_power_profile)
- ret = hwmgr->hwmgr_func->set_power_profile_state(
- hwmgr,
- request);
- } else {
- /* set power profile if it exists */
- switch (request->type) {
- case AMD_PP_GFX_PROFILE:
- ret = hwmgr->hwmgr_func->set_power_profile_state(
- hwmgr,
- &hwmgr->gfx_power_profile);
- break;
- case AMD_PP_COMPUTE_PROFILE:
- ret = hwmgr->hwmgr_func->set_power_profile_state(
- hwmgr,
- &hwmgr->compute_power_profile);
- break;
- default:
- return -EINVAL;
- }
+ return -EINVAL;
}
- if (!ret)
- hwmgr->current_power_profile = request->type;
-
- return 0;
+ return hwmgr->hwmgr_func->odn_edit_dpm_table(hwmgr, type, input, size);
}
static int pp_dpm_switch_power_profile(void *handle,
- enum amd_pp_profile_type type)
+ enum PP_SMC_POWER_PROFILE type, bool en)
{
- struct pp_hwmgr *hwmgr;
- struct amd_pp_profile request = {0};
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
+ long workload;
+ uint32_t index;
+
+ if (pp_check(hwmgr))
+ return -EINVAL;
+
+ if (hwmgr->hwmgr_func->set_power_profile_mode == NULL) {
+ pr_info("%s was not implemented.\n", __func__);
+ return -EINVAL;
+ }
- if (pp_check(pp_handle))
+ if (!(type < PP_SMC_POWER_PROFILE_CUSTOM))
return -EINVAL;
- hwmgr = pp_handle->hwmgr;
+ mutex_lock(&hwmgr->smu_lock);
- if (hwmgr->current_power_profile != type) {
- request.type = type;
- pp_dpm_set_power_profile_state(handle, &request);
+ if (!en) {
+ hwmgr->workload_mask &= ~(1 << hwmgr->workload_prority[type]);
+ index = fls(hwmgr->workload_mask);
+ index = index > 0 && index <= Workload_Policy_Max ? index - 1 : 0;
+ workload = hwmgr->workload_setting[index];
+ } else {
+ hwmgr->workload_mask |= (1 << hwmgr->workload_prority[type]);
+ index = fls(hwmgr->workload_mask);
+ index = index <= Workload_Policy_Max ? index - 1 : 0;
+ workload = hwmgr->workload_setting[index];
}
+ if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
+ hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, &workload, 0);
+ mutex_unlock(&hwmgr->smu_lock);
+
return 0;
}
@@ -1167,29 +1047,79 @@ static int pp_dpm_notify_smu_memory_info(void *handle,
uint32_t mc_addr_hi,
uint32_t size)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->hwmgr_func->notify_cac_buffer_info == NULL) {
pr_info("%s was not implemented.\n", __func__);
return -EINVAL;
}
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
ret = hwmgr->hwmgr_func->notify_cac_buffer_info(hwmgr, virtual_addr_low,
virtual_addr_hi, mc_addr_low, mc_addr_hi,
size);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
+
+ return ret;
+}
+
+static int pp_set_power_limit(void *handle, uint32_t limit)
+{
+ struct pp_hwmgr *hwmgr = handle;
+ int ret = 0;
+
+ ret = pp_check(hwmgr);
+
+ if (ret)
+ return ret;
+
+ if (hwmgr->hwmgr_func->set_power_limit == NULL) {
+ pr_info("%s was not implemented.\n", __func__);
+ return -EINVAL;
+ }
+
+ if (limit == 0)
+ limit = hwmgr->default_power_limit;
+
+ if (limit > hwmgr->default_power_limit)
+ return -EINVAL;
+
+ mutex_lock(&hwmgr->smu_lock);
+ hwmgr->hwmgr_func->set_power_limit(hwmgr, limit);
+ hwmgr->power_limit = limit;
+ mutex_unlock(&hwmgr->smu_lock);
+ return ret;
+}
+
+static int pp_get_power_limit(void *handle, uint32_t *limit, bool default_limit)
+{
+ struct pp_hwmgr *hwmgr = handle;
+ int ret = 0;
+
+ ret = pp_check(hwmgr);
+
+ if (ret)
+ return ret;
+
+ if (limit == NULL)
+ return -EINVAL;
+
+ mutex_lock(&hwmgr->smu_lock);
+
+ if (default_limit)
+ *limit = hwmgr->default_power_limit;
+ else
+ *limit = hwmgr->power_limit;
+
+ mutex_unlock(&hwmgr->smu_lock);
return ret;
}
@@ -1197,42 +1127,37 @@ static int pp_dpm_notify_smu_memory_info(void *handle,
static int pp_display_configuration_change(void *handle,
const struct amd_pp_display_configuration *display_config)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
phm_store_dal_configuration_data(hwmgr, display_config);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return 0;
}
static int pp_get_display_power_level(void *handle,
struct amd_pp_simple_clock_info *output)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (output == NULL)
return -EINVAL;
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
ret = phm_get_dal_power_level(hwmgr, output);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return ret;
}
@@ -1241,18 +1166,15 @@ static int pp_get_current_clocks(void *handle,
{
struct amd_pp_simple_clock_info simple_clocks;
struct pp_clock_info hw_clocks;
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
phm_get_dal_power_level(hwmgr, &simple_clocks);
@@ -1266,7 +1188,7 @@ static int pp_get_current_clocks(void *handle,
if (ret) {
pr_info("Error in phm_get_clock_info \n");
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return -EINVAL;
}
@@ -1286,29 +1208,26 @@ static int pp_get_current_clocks(void *handle,
clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
}
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return 0;
}
static int pp_get_clock_by_type(void *handle, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (clocks == NULL)
return -EINVAL;
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
ret = phm_get_clock_by_type(hwmgr, type, clocks);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return ret;
}
@@ -1316,21 +1235,19 @@ static int pp_get_clock_by_type_with_latency(void *handle,
enum amd_pp_clock_type type,
struct pp_clock_levels_with_latency *clocks)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
if (!clocks)
return -EINVAL;
- mutex_lock(&pp_handle->pp_lock);
- hwmgr = ((struct pp_instance *)handle)->hwmgr;
+ mutex_lock(&hwmgr->smu_lock);
ret = phm_get_clock_by_type_with_latency(hwmgr, type, clocks);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return ret;
}
@@ -1338,47 +1255,41 @@ static int pp_get_clock_by_type_with_voltage(void *handle,
enum amd_pp_clock_type type,
struct pp_clock_levels_with_voltage *clocks)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
if (!clocks)
return -EINVAL;
- hwmgr = ((struct pp_instance *)handle)->hwmgr;
-
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
ret = phm_get_clock_by_type_with_voltage(hwmgr, type, clocks);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return ret;
}
static int pp_set_watermarks_for_clocks_ranges(void *handle,
struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
if (!wm_with_clock_ranges)
return -EINVAL;
- hwmgr = ((struct pp_instance *)handle)->hwmgr;
-
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
ret = phm_set_watermarks_for_clocks_ranges(hwmgr,
wm_with_clock_ranges);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return ret;
}
@@ -1386,22 +1297,19 @@ static int pp_set_watermarks_for_clocks_ranges(void *handle,
static int pp_display_clock_voltage_request(void *handle,
struct pp_display_clock_request *clock)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
if (!clock)
return -EINVAL;
- hwmgr = ((struct pp_instance *)handle)->hwmgr;
-
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
ret = phm_display_clock_voltage_request(hwmgr, clock);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return ret;
}
@@ -1409,31 +1317,45 @@ static int pp_display_clock_voltage_request(void *handle,
static int pp_get_display_mode_validation_clocks(void *handle,
struct amd_pp_simple_clock_info *clocks)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (clocks == NULL)
return -EINVAL;
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DynamicPatchPowerState))
ret = phm_get_max_high_clocks(hwmgr, clocks);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return ret;
}
-const struct amd_pm_funcs pp_dpm_funcs = {
- .get_temperature = pp_dpm_get_temperature,
+static int pp_set_mmhub_powergating_by_smu(void *handle)
+{
+ struct pp_hwmgr *hwmgr = handle;
+ int ret = 0;
+
+ ret = pp_check(hwmgr);
+
+ if (ret)
+ return ret;
+
+ if (hwmgr->hwmgr_func->set_mmhub_powergating_by_smu == NULL) {
+ pr_info("%s was not implemented.\n", __func__);
+ return 0;
+ }
+
+ return hwmgr->hwmgr_func->set_mmhub_powergating_by_smu(hwmgr);
+}
+
+static const struct amd_pm_funcs pp_dpm_funcs = {
.load_firmware = pp_dpm_load_fw,
.wait_for_fw_loading_complete = pp_dpm_fw_loading_complete,
.force_performance_level = pp_dpm_force_performance_level,
@@ -1458,12 +1380,14 @@ const struct amd_pm_funcs pp_dpm_funcs = {
.set_mclk_od = pp_dpm_set_mclk_od,
.read_sensor = pp_dpm_read_sensor,
.get_vce_clock_state = pp_dpm_get_vce_clock_state,
- .reset_power_profile_state = pp_dpm_reset_power_profile_state,
- .get_power_profile_state = pp_dpm_get_power_profile_state,
- .set_power_profile_state = pp_dpm_set_power_profile_state,
.switch_power_profile = pp_dpm_switch_power_profile,
.set_clockgating_by_smu = pp_set_clockgating_by_smu,
.notify_smu_memory_info = pp_dpm_notify_smu_memory_info,
+ .get_power_profile_mode = pp_get_power_profile_mode,
+ .set_power_profile_mode = pp_set_power_profile_mode,
+ .odn_edit_dpm_table = pp_odn_edit_dpm_table,
+ .set_power_limit = pp_set_power_limit,
+ .get_power_limit = pp_get_power_limit,
/* export to DC */
.get_sclk = pp_dpm_get_sclk,
.get_mclk = pp_dpm_get_mclk,
@@ -1476,4 +1400,5 @@ const struct amd_pm_funcs pp_dpm_funcs = {
.set_watermarks_for_clocks_ranges = pp_set_watermarks_for_clocks_ranges,
.display_clock_voltage_request = pp_display_clock_voltage_request,
.get_display_mode_validation_clocks = pp_get_display_mode_validation_clocks,
+ .set_mmhub_powergating_by_smu = pp_set_mmhub_powergating_by_smu,
};