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path: root/drivers/gpu/drm/amd/display/dc/dce80
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Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dce80')
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce80/dce80_compressor.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_compressor.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_compressor.c
index eeedb7c4fe53..77626d7624c6 100644
--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_compressor.c
+++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_compressor.c
@@ -407,7 +407,7 @@ void dce80_compressor_enable_fbc(
/* Keep track of enum controller_id FBC is attached to */
compressor->is_enabled = true;
compressor->attached_inst = params->inst;
- cp80->offsets = reg_offsets[params->inst - 1];
+ cp80->offsets = reg_offsets[params->inst];
/*Toggle it as there is bug in HW */
set_reg_field_value(value, 0, FBC_CNTL, FBC_GRPH_COMP_EN);
@@ -777,6 +777,7 @@ bool dce80_compressor_construct(struct dce80_compressor *compressor,
struct dc_bios *bp = ctx->dc_bios;
struct embedded_panel_info panel_info;
+ compressor->base.options.raw = 0;
compressor->base.options.bits.FBC_SUPPORT = true;
compressor->base.options.bits.LPT_SUPPORT = true;
/* For DCE 11 always use one DRAM channel for LPT */
@@ -797,7 +798,6 @@ bool dce80_compressor_construct(struct dce80_compressor *compressor,
compressor->base.allocated_size = 0;
compressor->base.preferred_requested_size = 0;
compressor->base.min_compress_ratio = FBC_COMPRESS_RATIO_INVALID;
- compressor->base.options.raw = 0;
compressor->base.banks_num = 0;
compressor->base.raw_size = 0;
compressor->base.channel_interleave_size = 0;