diff options
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dce120')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c index d4e962756fbb..562ae2205a90 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c @@ -729,21 +729,21 @@ static void bw_calcs_data_update_from_pplib(struct core_dc *dc) } /* convert all the clock fro kHz to fix point mHz TODO: wloop data */ - dc->bw_vbios.high_sclk = bw_frc_to_fixed( + dc->bw_vbios->high_sclk = bw_frc_to_fixed( eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000); - dc->bw_vbios.mid1_sclk = bw_frc_to_fixed( + dc->bw_vbios->mid1_sclk = bw_frc_to_fixed( eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000); - dc->bw_vbios.mid2_sclk = bw_frc_to_fixed( + dc->bw_vbios->mid2_sclk = bw_frc_to_fixed( eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000); - dc->bw_vbios.mid3_sclk = bw_frc_to_fixed( + dc->bw_vbios->mid3_sclk = bw_frc_to_fixed( eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000); - dc->bw_vbios.mid4_sclk = bw_frc_to_fixed( + dc->bw_vbios->mid4_sclk = bw_frc_to_fixed( eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000); - dc->bw_vbios.mid5_sclk = bw_frc_to_fixed( + dc->bw_vbios->mid5_sclk = bw_frc_to_fixed( eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000); - dc->bw_vbios.mid6_sclk = bw_frc_to_fixed( + dc->bw_vbios->mid6_sclk = bw_frc_to_fixed( eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000); - dc->bw_vbios.low_sclk = bw_frc_to_fixed( + dc->bw_vbios->low_sclk = bw_frc_to_fixed( eng_clks.data[0].clocks_in_khz, 1000); /*do memory clock*/ @@ -770,12 +770,12 @@ static void bw_calcs_data_update_from_pplib(struct core_dc *dc) * ALSO always convert UMA clock (from PPLIB) to YCLK (HW formula): * YCLK = UMACLK*m_memoryTypeMultiplier */ - dc->bw_vbios.low_yclk = bw_frc_to_fixed( + dc->bw_vbios->low_yclk = bw_frc_to_fixed( mem_clks.data[0].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, 1000); - dc->bw_vbios.mid_yclk = bw_frc_to_fixed( + dc->bw_vbios->mid_yclk = bw_frc_to_fixed( mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, 1000); - dc->bw_vbios.high_yclk = bw_frc_to_fixed( + dc->bw_vbios->high_yclk = bw_frc_to_fixed( mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, 1000); @@ -984,7 +984,7 @@ static bool construct( dc->public.caps.max_planes = pool->base.pipe_count; - bw_calcs_init(&dc->bw_dceip, &dc->bw_vbios, dc->ctx->asic_id); + bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id); bw_calcs_data_update_from_pplib(dc); |