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path: root/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h
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Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h')
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h18
1 files changed, 7 insertions, 11 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h
index f6a1006a6472..25ba583dbb8f 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h
@@ -31,12 +31,10 @@
#define TO_DCE110_LINK_ENC(link_encoder)\
container_of(link_encoder, struct dce110_link_encoder, base)
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
/* Not found regs in dce120 spec
* BIOS_SCRATCH_2
* DP_DPHY_INTERNAL_CTRL
*/
-#endif
#define AUX_REG_LIST(id)\
SRI(AUX_CONTROL, DP_AUX, id), \
@@ -86,16 +84,14 @@
SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
SR(DCI_MEM_PWR_STATUS)
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
- #define LE_DCE120_REG_LIST(id)\
- LE_COMMON_REG_LIST_BASE(id), \
- SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
- SR(DCI_MEM_PWR_STATUS)
-#endif
+#define LE_DCE120_REG_LIST(id)\
+ LE_COMMON_REG_LIST_BASE(id), \
+ SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
+ SR(DCI_MEM_PWR_STATUS)
- #define LE_DCE80_REG_LIST(id)\
- SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
- LE_COMMON_REG_LIST_BASE(id)
+#define LE_DCE80_REG_LIST(id)\
+ SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
+ LE_COMMON_REG_LIST_BASE(id)
struct dce110_link_enc_aux_registers {