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path: root/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h
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Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h')
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h6
1 files changed, 0 insertions, 6 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h
index 18787f6d4e2a..2fd00e45395c 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h
@@ -45,13 +45,11 @@
CLK_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, mask_sh), \
CLK_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh)
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
#define CLK_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh) \
CLK_SF(DCCG_DFS_DPREFCLK_CNTL, DPREFCLK_SRC_SEL, mask_sh), \
CLK_SF(DCCG_DFS_DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, mask_sh), \
CLK_SF(DCCG_DFS_MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, mask_sh), \
CLK_SF(DCCG_DFS_MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh)
-#endif
#define CLK_REG_FIELD_LIST(type) \
type DPREFCLK_SRC_SEL; \
@@ -126,10 +124,8 @@ struct dce_disp_clk {
int gpu_pll_ss_divider;
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
/* max disp_clk from PPLIB for max validation display clock*/
int max_displ_clk_in_khz;
-#endif
};
@@ -151,13 +147,11 @@ struct display_clock *dce112_disp_clk_create(
const struct dce_disp_clk_shift *clk_shift,
const struct dce_disp_clk_mask *clk_mask);
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
struct display_clock *dce120_disp_clk_create(
struct dc_context *ctx,
const struct dce_disp_clk_registers *regs,
const struct dce_disp_clk_shift *clk_shift,
const struct dce_disp_clk_mask *clk_mask);
-#endif
void dce_disp_clk_destroy(struct display_clock **disp_clk);