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path: root/drivers/gpu/drm/amd/display/amdgpu_dm
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Diffstat (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm')
-rw-r--r--drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c4
-rw-r--r--drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c2
-rw-r--r--drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c2
3 files changed, 0 insertions, 8 deletions
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 9157772a0af3..97d949affcfb 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1123,9 +1123,7 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
case CHIP_POLARIS11:
case CHIP_POLARIS10:
case CHIP_POLARIS12:
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
case CHIP_VEGA10:
-#endif
if (dce110_register_irq_handlers(dm->adev)) {
DRM_ERROR("DM: Failed to initialize IRQ\n");
return -1;
@@ -1392,13 +1390,11 @@ static int dm_early_init(void *handle)
adev->mode_info.num_hpd = 6;
adev->mode_info.num_dig = 6;
break;
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
case CHIP_VEGA10:
adev->mode_info.num_crtc = 6;
adev->mode_info.num_hpd = 6;
adev->mode_info.num_dig = 6;
break;
-#endif
default:
DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type);
return -EINVAL;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
index df53092abc39..a8a53b85905a 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
@@ -402,7 +402,6 @@ bool dm_pp_notify_wm_clock_changes(
return false;
}
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
bool dm_pp_notify_wm_clock_changes_soc15(
const struct dc_context *ctx,
struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges)
@@ -410,7 +409,6 @@ bool dm_pp_notify_wm_clock_changes_soc15(
/* TODO: to be implemented */
return false;
}
-#endif
bool dm_pp_apply_power_level_change_request(
const struct dc_context *ctx,
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index 01aaf968854d..1c1c643439b8 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -523,7 +523,6 @@ static void fill_plane_attributes_from_fb(
surface->tiling_info.gfx8.pipe_config =
AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
-#if defined (CONFIG_DRM_AMD_DC_DCE12_0)
if (adev->asic_type == CHIP_VEGA10) {
/* Fill GFX9 params */
surface->tiling_info.gfx9.num_pipes =
@@ -540,7 +539,6 @@ static void fill_plane_attributes_from_fb(
AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
surface->tiling_info.gfx9.shaderEnable = 1;
}
-#endif
surface->plane_size.grph.surface_size.x = 0;