diff options
| -rw-r--r-- | drivers/gpu/drm/i915/i915_pmu.c | 31 | ||||
| -rw-r--r-- | include/uapi/drm/i915_drm.h | 6 |
2 files changed, 36 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c index fef389ebf92c..1071935bfa67 100644 --- a/drivers/gpu/drm/i915/i915_pmu.c +++ b/drivers/gpu/drm/i915/i915_pmu.c @@ -361,6 +361,15 @@ static int i915_pmu_event_init(struct perf_event *event) break; case I915_PMU_INTERRUPTS: break; + case I915_PMU_RC6_RESIDENCY: + if (!HAS_RC6(i915)) + ret = -ENODEV; + break; + case I915_PMU_RC6p_RESIDENCY: + case I915_PMU_RC6pp_RESIDENCY: + if (!HAS_RC6p(i915)) + ret = -ENODEV; + break; default: ret = -ENOENT; break; @@ -413,6 +422,24 @@ static u64 __i915_pmu_event_read(struct perf_event *event) case I915_PMU_INTERRUPTS: val = count_interrupts(i915); break; + case I915_PMU_RC6_RESIDENCY: + intel_runtime_pm_get(i915); + val = intel_rc6_residency_ns(i915, + IS_VALLEYVIEW(i915) ? + VLV_GT_RENDER_RC6 : + GEN6_GT_GFX_RC6); + intel_runtime_pm_put(i915); + break; + case I915_PMU_RC6p_RESIDENCY: + intel_runtime_pm_get(i915); + val = intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6p); + intel_runtime_pm_put(i915); + break; + case I915_PMU_RC6pp_RESIDENCY: + intel_runtime_pm_get(i915); + val = intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6pp); + intel_runtime_pm_put(i915); + break; } } @@ -677,6 +704,10 @@ static struct attribute *i915_pmu_events_attrs[] = { I915_EVENT_ATTR(interrupts, I915_PMU_INTERRUPTS), + I915_EVENT(rc6-residency, I915_PMU_RC6_RESIDENCY, "ns"), + I915_EVENT(rc6p-residency, I915_PMU_RC6p_RESIDENCY, "ns"), + I915_EVENT(rc6pp-residency, I915_PMU_RC6pp_RESIDENCY, "ns"), + NULL, }; diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index d840ff083520..915a6e85a855 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -141,7 +141,11 @@ enum drm_i915_pmu_engine_sample { #define I915_PMU_INTERRUPTS __I915_PMU_OTHER(2) -#define I915_PMU_LAST I915_PMU_INTERRUPTS +#define I915_PMU_RC6_RESIDENCY __I915_PMU_OTHER(3) +#define I915_PMU_RC6p_RESIDENCY __I915_PMU_OTHER(4) +#define I915_PMU_RC6pp_RESIDENCY __I915_PMU_OTHER(5) + +#define I915_PMU_LAST I915_PMU_RC6pp_RESIDENCY /* Each region is a minimum of 16k, and there are at most 255 of them. */ |