path: root/include/uapi/drm/i915_drm.h
diff options
authorChris Wilson <>2016-08-05 10:14:22 +0100
committerChris Wilson <>2016-08-05 10:54:42 +0100
commitdeeb1519b65a92ca06c8e8554a92df0fdb4d5dea (patch)
tree8a8a464b76cc6000dbfb79cdf5fe3b3e53e0c401 /include/uapi/drm/i915_drm.h
parent9ad3676148511d6af72be6f3638e361fd86e1f7b (diff)
drm/i915: Document and reject invalid tiling modes
Through the GTT interface to the fence registers, we can only handle linear, X and Y tiling. The more esoteric tiling patterns are ignored. Document that the tiling ABI only supports upto Y tiling, and reject any attempts to set a tiling mode other than NONE, X or Y. Signed-off-by: Chris Wilson <> Cc: Joonas Lahtinen <> Reviewed-by: Joonas Lahtinen <> Link:
Diffstat (limited to 'include/uapi/drm/i915_drm.h')
1 files changed, 1 insertions, 0 deletions
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 0f292733cffc..452629de7a57 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -926,6 +926,7 @@ struct drm_i915_gem_caching {
#define I915_TILING_NONE 0
#define I915_TILING_X 1
#define I915_TILING_Y 2
+#define I915_TILING_LAST I915_TILING_Y
#define I915_BIT_6_SWIZZLE_NONE 0
#define I915_BIT_6_SWIZZLE_9 1