diff options
| author | Logatharshan Thothiralingam <logatharshan.thothiralingam@amd.com> | 2017-08-18 19:09:57 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2017-09-26 18:17:25 -0400 |
| commit | 6f54d0b1d82194116fcb8a3683827c9d8eb8cb9b (patch) | |
| tree | bc09e762989eb0fbbb4e22b6c48f5617f5b335e3 /drivers/gpu/drm | |
| parent | b46c085c238fdfea9b1cc49326dae92a47b34832 (diff) | |
drm/amd/display: Get OTG info if OTG master enabled
Signed-off-by: Logatharshan Thothiralingam <logatharshan.thothiralingam@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm')
3 files changed, 9 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 7ea274475598..4fa856e9a872 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -203,10 +203,14 @@ static void dcn10_log_hw_state(struct dc *dc) for (i = 0; i < pool->pipe_count; i++) { struct timing_generator *tg = pool->timing_generators[i]; - struct dcn_otg_state s; + struct dcn_otg_state s = {0}; tgn10_read_otg_state(DCN10TG_FROM_TG(tg), &s); + //only print if OTG master is enabled + if ((s.otg_enabled & 1) == 0) + continue; + DTN_INFO("[%d]:\t %d \t %d \t %d \t %d \t " "%d \t %d \t %d \t %d \t %d \t %d \t " "%d \t %d \t %d \t %d \t %d \t ", diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c index 15f1f44e102a..405f595f219a 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c @@ -1100,6 +1100,9 @@ static bool tgn10_is_stereo_left_eye(struct timing_generator *tg) void tgn10_read_otg_state(struct dcn10_timing_generator *tgn10, struct dcn_otg_state *s) { + REG_GET(OTG_CONTROL, + OTG_MASTER_EN, &s->otg_enabled); + REG_GET_2(OTG_V_BLANK_START_END, OTG_V_BLANK_START, &s->v_blank_start, OTG_V_BLANK_END, &s->v_blank_end); diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h index 38d3dcf89d60..69da293e9b4a 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h @@ -370,6 +370,7 @@ struct dcn_otg_state { uint32_t h_sync_a_pol; uint32_t h_total; uint32_t underflow_occurred_status; + uint32_t otg_enabled; }; void tgn10_read_otg_state(struct dcn10_timing_generator *tgn10, |