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authorThierry Reding <treding@nvidia.com>2015-07-21 16:46:52 +0200
committerThierry Reding <treding@nvidia.com>2016-07-01 14:42:06 +0200
commita198359e39c0e47a995d8e88638d5738ae4cfbe2 (patch)
treea52043f84f72d20696be424b19025bfa11c7b0e9 /drivers/gpu/drm/tegra
parent25bb2cec88401a512c01adc8b815f8a579da2558 (diff)
drm/tegra: sor: Rename tegra_sor_calc_config()
Use a slightly more sensible name, tegra_sor_compute_config(). Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/gpu/drm/tegra')
-rw-r--r--drivers/gpu/drm/tegra/sor.c13
1 files changed, 6 insertions, 7 deletions
diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c
index ed03a1f5b692..fb536c1f5111 100644
--- a/drivers/gpu/drm/tegra/sor.c
+++ b/drivers/gpu/drm/tegra/sor.c
@@ -586,10 +586,10 @@ static int tegra_sor_compute_params(struct tegra_sor *sor,
return false;
}
-static int tegra_sor_calc_config(struct tegra_sor *sor,
- const struct drm_display_mode *mode,
- struct tegra_sor_config *config,
- struct drm_dp_link *link)
+static int tegra_sor_compute_config(struct tegra_sor *sor,
+ const struct drm_display_mode *mode,
+ struct tegra_sor_config *config,
+ struct drm_dp_link *link)
{
const u64 f = 100000, link_rate = link->rate * 1000;
const u64 pclk = mode->clock * 1000;
@@ -1245,10 +1245,9 @@ static void tegra_sor_edp_enable(struct drm_encoder *encoder)
memset(&config, 0, sizeof(config));
config.bits_per_pixel = output->connector.display_info.bpc * 3;
- err = tegra_sor_calc_config(sor, mode, &config, &link);
+ err = tegra_sor_compute_config(sor, mode, &config, &link);
if (err < 0)
- dev_err(sor->dev, "failed to compute link configuration: %d\n",
- err);
+ dev_err(sor->dev, "failed to compute configuration: %d\n", err);
value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;