path: root/drivers/gpu/drm/msm/dsi/dsi.h
diff options
authorHai Li <>2015-07-03 10:09:46 -0400
committerRob Clark <>2015-08-15 18:27:18 -0400
commit328e1a633c9bc26c36ecd320246e4a9b2726e81a (patch)
tree662e05c96fd1cf2bf0d6e059a32479d374616ac3 /drivers/gpu/drm/msm/dsi/dsi.h
parentda882cd1ee132ecbb4a4848a6b0797ea2ed4bee7 (diff)
drm/msm/dsi: Save/Restore PLL status across PHY reset
Reset DSI PHY silently changes its PLL registers to reset status, which will make cached status in clock driver invalid and result in wrong output rate of link clocks. The current restore mechanism in DSI PLL does not cover all the cases. This change is to recover PLL status after PHY reset to match HW status with cached status in clock driver. Signed-off-by: Hai Li <> Signed-off-by: Rob Clark <>
Diffstat (limited to 'drivers/gpu/drm/msm/dsi/dsi.h')
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h
index e18872a62806..912057df5c02 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.h
@@ -95,6 +95,8 @@ struct msm_dsi_pll *msm_dsi_pll_init(struct platform_device *pdev,
void msm_dsi_pll_destroy(struct msm_dsi_pll *pll);
int msm_dsi_pll_get_clk_provider(struct msm_dsi_pll *pll,
struct clk **byte_clk_provider, struct clk **pixel_clk_provider);
+void msm_dsi_pll_save_state(struct msm_dsi_pll *pll);
+int msm_dsi_pll_restore_state(struct msm_dsi_pll *pll);
static inline struct msm_dsi_pll *msm_dsi_pll_init(struct platform_device *pdev,
enum msm_dsi_phy_type type, int id) {
@@ -108,6 +110,13 @@ static inline int msm_dsi_pll_get_clk_provider(struct msm_dsi_pll *pll,
return -ENODEV;
+static inline void msm_dsi_pll_save_state(struct msm_dsi_pll *pll)
+static inline int msm_dsi_pll_restore_state(struct msm_dsi_pll *pll)
+ return 0;
/* dsi host */