|author||Archit Taneja <email@example.com>||2017-01-03 19:45:43 +0530|
|committer||Rob Clark <firstname.lastname@example.org>||2017-02-06 11:28:45 -0500|
drm/msm/dsi: Add PHY/PLL for 8x96
Extend the DSI PHY/PLL drivers to support the DSI 14nm PHY/PLL found on 8x96. These are picked up from the downstream driver. The PHY part is similar to the other DSI PHYs. The PLL driver requires some trickery so that one DSI PLL can drive both the DSIs (i.e, dual DSI mode). In the case of dual DSI mode. One DSI instance becomes the clock master, and other the clock slave. The master PLL's output (Byte and Pixel clock) is fed to both the DSI hosts/PHYs. When the DSIs are configured in dual DSI mode, the PHY driver communicates to the PLL driver using msm_dsi_pll_set_usecase() which instance is the master and which one is the slave. When setting rate, the master PLL also configures some of the slave PLL/PHY registers which need to be identical to the master's for correct dual DSI behaviour. There are 2 PLL post dividers that should have ideally been modelled as generic clk_divider clocks, but require some customization for dual DSI. In particular, when the master PLL's post-diviers are set, the slave PLL's post-dividers need to be set too. The clk_ops for these use clk_divider's helper ops and flags internally to prevent redundant code. Cc: Stephen Boyd <email@example.com> Signed-off-by: Archit Taneja <firstname.lastname@example.org> Signed-off-by: Rob Clark <email@example.com>
Diffstat (limited to 'drivers/gpu/drm/msm/Kconfig')
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig
index 7f78da695dff..5b8e23d051f2 100644
@@ -72,3 +72,10 @@ config DRM_MSM_DSI_28NM_8960_PHY
Choose this option if the 28nm DSI PHY 8960 variant is used on the
+ bool "Enable DSI 14nm PHY driver in MSM DRM (used by MSM8996/APQ8096)"
+ depends on DRM_MSM_DSI
+ default y
+ Choose this option if DSI PHY on 8996 is used on the platform.