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authorUma Shankar <uma.shankar@intel.com>2017-02-08 16:20:54 +0530
committerJani Nikula <jani.nikula@intel.com>2017-02-16 17:21:05 +0200
commiteba4daf0dc5861703000f58b1d51110ced2b2fb5 (patch)
tree87cd57f2687c6c658fec361d0588e95478a35911 /drivers/gpu/drm/i915/intel_dsi.c
parent6043801f937ada9c9ed9dfa3c6ce542a79643401 (diff)
drm/i915/bxt: Fix BXT DSI ULPS sequence
Fix the Sequence to program BXT DSI Latch and ULPS. Signed-off-by: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com> Reviewed-by: Bob Paauwe <bob.j.paauwe@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1486551058-22596-6-git-send-email-vidya.srinivas@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_dsi.c')
-rw-r--r--drivers/gpu/drm/i915/intel_dsi.c23
1 files changed, 5 insertions, 18 deletions
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 99dd7e12abc0..e7e823d00444 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -366,32 +366,19 @@ static void bxt_dsi_device_ready(struct intel_encoder *encoder)
DRM_DEBUG_KMS("\n");
- /* Exit Low power state in 4 steps*/
+ /* Enable MIPI PHY transparent latch */
for_each_dsi_port(port, intel_dsi->ports) {
-
- /* 1. Enable MIPI PHY transparent latch */
val = I915_READ(BXT_MIPI_PORT_CTRL(port));
I915_WRITE(BXT_MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD);
usleep_range(2000, 2500);
+ }
- /* 2. Enter ULPS */
- val = I915_READ(MIPI_DEVICE_READY(port));
- val &= ~ULPS_STATE_MASK;
- val |= (ULPS_STATE_ENTER | DEVICE_READY);
- I915_WRITE(MIPI_DEVICE_READY(port), val);
- /* at least 2us - relaxed for hrtimer subsystem optimization */
- usleep_range(10, 50);
-
- /* 3. Exit ULPS */
+ /* Clear ULPS and set device ready */
+ for_each_dsi_port(port, intel_dsi->ports) {
val = I915_READ(MIPI_DEVICE_READY(port));
val &= ~ULPS_STATE_MASK;
- val |= (ULPS_STATE_EXIT | DEVICE_READY);
I915_WRITE(MIPI_DEVICE_READY(port), val);
- usleep_range(1000, 1500);
-
- /* Clear ULPS and set device ready */
- val = I915_READ(MIPI_DEVICE_READY(port));
- val &= ~ULPS_STATE_MASK;
+ usleep_range(2000, 2500);
val |= DEVICE_READY;
I915_WRITE(MIPI_DEVICE_READY(port), val);
}