diff options
author | Sean Paul <seanpaul@chromium.org> | 2018-03-21 09:40:55 -0400 |
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committer | Sean Paul <seanpaul@chromium.org> | 2018-03-21 09:40:55 -0400 |
commit | 1c7095d2836baafd84e596dd34ba1a1293a4faa9 (patch) | |
tree | 498f529809b9c0a3c75c8b8bb1098ed4f71233db /drivers/gpu/drm/arm/malidp_hw.h | |
parent | 2793c1d77aa8876e5674e901d051c79570e99db2 (diff) | |
parent | 78230c46ec0a91dd4256c9e54934b3c7095a7ee3 (diff) |
Merge airlied/drm-next into drm-misc-nextdrm-misc-next-2018-03-21
Refresh -misc-next
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Diffstat (limited to 'drivers/gpu/drm/arm/malidp_hw.h')
-rw-r--r-- | drivers/gpu/drm/arm/malidp_hw.h | 15 |
1 files changed, 11 insertions, 4 deletions
diff --git a/drivers/gpu/drm/arm/malidp_hw.h b/drivers/gpu/drm/arm/malidp_hw.h index b0690ebb3565..b5dd6c73ec9f 100644 --- a/drivers/gpu/drm/arm/malidp_hw.h +++ b/drivers/gpu/drm/arm/malidp_hw.h @@ -58,7 +58,8 @@ struct malidp_layer { u16 id; /* layer ID */ u16 base; /* address offset for the register bank */ u16 ptr; /* address offset for the pointer register */ - u16 stride_offset; /* Offset to the first stride register. */ + u16 stride_offset; /* offset to the first stride register. */ + s16 yuv2rgb_offset; /* offset to the YUV->RGB matrix entries */ }; enum malidp_scaling_coeff_set { @@ -285,10 +286,16 @@ void malidp_se_irq_fini(struct drm_device *drm); u8 malidp_hw_get_format_id(const struct malidp_hw_regmap *map, u8 layer_id, u32 format); -static inline bool malidp_hw_pitch_valid(struct malidp_hw_device *hwdev, - unsigned int pitch) +static inline u8 malidp_hw_get_pitch_align(struct malidp_hw_device *hwdev, bool rotated) { - return !(pitch & (hwdev->hw->map.bus_align_bytes - 1)); + /* + * only hardware that cannot do 8 bytes bus alignments have further + * constraints on rotated planes + */ + if (hwdev->hw->map.bus_align_bytes == 8) + return 8; + else + return hwdev->hw->map.bus_align_bytes << (rotated ? 2 : 0); } /* U16.16 */ |