path: root/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
diff options
authorRex Zhu <>2017-05-02 16:51:49 +0800
committerAlex Deucher <>2017-05-05 18:11:44 -0400
commit05ee3215110303b3ffacfb44fdae59a151799e89 (patch)
treed532aa73263f3336379cf15fc125e0977d5e6543 /drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
parentef181f268e0e8d868f353b764799d96d6a8a2d86 (diff)
drm/amd/powerplay: set soc floor voltage on boot on vega10.
Send the VBIOS bootup VDDC as a SOC floor voltage to SMU before populating the PPTABLE. After DPM is enabled, This floor voltage will be removed. This will prevent SMC from going to Vmin upon receiving PPTable causing a violation. Signed-off-by: Rex Zhu <> Reviewed-by: Alex Deucher <> Signed-off-by: Alex Deucher <>
Diffstat (limited to 'drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h')
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
index 83c67b9262ff..1912e086c0cf 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
@@ -177,8 +177,11 @@ struct vega10_dpmlevel_enable_mask {
struct vega10_vbios_boot_state {
+ bool bsoc_vddc_lock;
uint16_t vddc;
uint16_t vddci;
+ uint16_t mvddc;
+ uint16_t vdd_gfx;
uint32_t gfx_clock;
uint32_t mem_clock;
uint32_t soc_clock;