summaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/amd/include
diff options
context:
space:
mode:
authorRex Zhu <Rex.Zhu@amd.com>2018-01-02 14:06:05 +0800
committerAlex Deucher <alexander.deucher@amd.com>2018-02-19 14:17:49 -0500
commit680731ade574e770e16f4488eb4217e8b8b13ffe (patch)
tree48f67805b550dbc1056bf6ebb49ec6a079119fc5 /drivers/gpu/drm/amd/include
parent039fdc94c15a5244410449dce59ff6df73ba39d7 (diff)
drm/amd/pp: Export registers for read vddc on VI/Vega10
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/include')
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_d.h1
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h6
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_9_0_offset.h3
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_9_0_sh_mask.h3
4 files changed, 11 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_d.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_d.h
index b89347ed1a40..f35aba72e640 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_d.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_d.h
@@ -1246,5 +1246,6 @@
#define ixGC_CAC_OVRD_CU 0xe7
#define ixCURRENT_PG_STATUS 0xc020029c
#define ixCURRENT_PG_STATUS_APU 0xd020029c
+#define ixPWR_SVI2_STATUS 0xC0200294
#endif /* SMU_7_1_3_D_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h
index 654c1093d362..481ee6560aa9 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h
@@ -6078,6 +6078,8 @@
#define GC_CAC_OVRD_CU__OVRRD_VALUE__SHIFT 0x10
#define CURRENT_PG_STATUS__VCE_PG_STATUS_MASK 0x00000002
#define CURRENT_PG_STATUS__UVD_PG_STATUS_MASK 0x00000004
-
-
+#define PWR_SVI2_STATUS__PLANE1_VID_MASK 0x000000ff
+#define PWR_SVI2_STATUS__PLANE1_VID__SHIFT 0x00000000
+#define PWR_SVI2_STATUS__PLANE2_VID_MASK 0x0000ff00
+#define PWR_SVI2_STATUS__PLANE2_VID__SHIFT 0x00000008
#endif /* SMU_7_1_3_SH_MASK_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_9_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_9_0_offset.h
index c1006fe58daa..efd2704d0f8f 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_9_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_9_0_offset.h
@@ -172,4 +172,7 @@
#define mmROM_SW_DATA_64 0x006d
#define mmROM_SW_DATA_64_BASE_IDX 0
+#define mmSMUSVI0_PLANE0_CURRENTVID_BASE_IDX 0
+#define mmSMUSVI0_PLANE0_CURRENTVID 0x0013
+
#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_9_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_9_0_sh_mask.h
index a0be5c9bfc10..2487ab9621e9 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_9_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_9_0_sh_mask.h
@@ -254,5 +254,8 @@
//ROM_SW_DATA_64
#define ROM_SW_DATA_64__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_64__ROM_SW_DATA_MASK 0xFFFFFFFFL
+/* SMUSVI0_PLANE0_CURRENTVID */
+#define SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID__SHIFT 0x18
+#define SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID_MASK 0xFF000000L
#endif