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authorFeifei Xu <Feifei.Xu@amd.com>2017-11-27 17:00:12 +0800
committerAlex Deucher <alexander.deucher@amd.com>2017-12-06 12:48:24 -0500
commit5a18155d991e808562dab8cd1f67ab637c0970c9 (patch)
tree30f6a17d4683883b1917a5ef0bc56eaae4d4dec6 /drivers/gpu/drm/amd/include
parentad941f7a8bf58b07c6fe5b4731541965cc3d652b (diff)
drm/amd/include:cleanup raven1 gc header files.
Cleanup asic_reg/raven1/GC folder. Remove unused files: gc_9_1_default.h gc_9_1_sh_mask.h Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Acked-by: Christian K├Ânig <christian.koenig@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/include')
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h (renamed from drivers/gpu/drm/amd/include/asic_reg/raven1/GC/gc_9_1_offset.h)0
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/raven1/GC/gc_9_1_default.h4005
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/raven1/GC/gc_9_1_sh_mask.h31191
3 files changed, 0 insertions, 35196 deletions
diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/GC/gc_9_1_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h
index db7ef5ede0e5..db7ef5ede0e5 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/raven1/GC/gc_9_1_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h
diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/GC/gc_9_1_default.h b/drivers/gpu/drm/amd/include/asic_reg/raven1/GC/gc_9_1_default.h
deleted file mode 100644
index 582f1a66e354..000000000000
--- a/drivers/gpu/drm/amd/include/asic_reg/raven1/GC/gc_9_1_default.h
+++ /dev/null
@@ -1,4005 +0,0 @@
-/*
- * Copyright (C) 2017 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-#ifndef _gc_9_1_DEFAULT_HEADER
-#define _gc_9_1_DEFAULT_HEADER
-
-
-// addressBlock: gc_grbmdec
-#define mmGRBM_CNTL_DEFAULT 0x00000018
-#define mmGRBM_SKEW_CNTL_DEFAULT 0x00000020
-#define mmGRBM_STATUS2_DEFAULT 0x00000000
-#define mmGRBM_PWR_CNTL_DEFAULT 0x00000000
-#define mmGRBM_STATUS_DEFAULT 0x00000000
-#define mmGRBM_STATUS_SE0_DEFAULT 0x00000000
-#define mmGRBM_STATUS_SE1_DEFAULT 0x00000000
-#define mmGRBM_SOFT_RESET_DEFAULT 0x00000000
-#define mmGRBM_CGTT_CLK_CNTL_DEFAULT 0x00000100
-#define mmGRBM_GFX_CLKEN_CNTL_DEFAULT 0x00001008
-#define mmGRBM_WAIT_IDLE_CLOCKS_DEFAULT 0x00000030
-#define mmGRBM_STATUS_SE2_DEFAULT 0x00000000
-#define mmGRBM_STATUS_SE3_DEFAULT 0x00000000
-#define mmGRBM_READ_ERROR_DEFAULT 0x00000000
-#define mmGRBM_READ_ERROR2_DEFAULT 0x00000000
-#define mmGRBM_INT_CNTL_DEFAULT 0x00000000
-#define mmGRBM_TRAP_OP_DEFAULT 0x00000000
-#define mmGRBM_TRAP_ADDR_DEFAULT 0x00000000
-#define mmGRBM_TRAP_ADDR_MSK_DEFAULT 0x0003ffff
-#define mmGRBM_TRAP_WD_DEFAULT 0x00000000
-#define mmGRBM_TRAP_WD_MSK_DEFAULT 0xffffffff
-#define mmGRBM_DSM_BYPASS_DEFAULT 0x00000000
-#define mmGRBM_WRITE_ERROR_DEFAULT 0x00000000
-#define mmGRBM_IOV_ERROR_DEFAULT 0x00000000
-#define mmGRBM_CHIP_REVISION_DEFAULT 0x00000000
-#define mmGRBM_GFX_CNTL_DEFAULT 0x00000000
-#define mmGRBM_RSMU_CFG_DEFAULT 0x00011000
-#define mmGRBM_IH_CREDIT_DEFAULT 0x00010000
-#define mmGRBM_PWR_CNTL2_DEFAULT 0x00010000
-#define mmGRBM_UTCL2_INVAL_RANGE_START_DEFAULT 0x00002891
-#define mmGRBM_UTCL2_INVAL_RANGE_END_DEFAULT 0x000028ea
-#define mmGRBM_RSMU_READ_ERROR_DEFAULT 0x00000000
-#define mmGRBM_CHICKEN_BITS_DEFAULT 0x00000000
-#define mmGRBM_NOWHERE_DEFAULT 0x00000000
-#define mmGRBM_SCRATCH_REG0_DEFAULT 0x00000000
-#define mmGRBM_SCRATCH_REG1_DEFAULT 0x00000000
-#define mmGRBM_SCRATCH_REG2_DEFAULT 0x00000000
-#define mmGRBM_SCRATCH_REG3_DEFAULT 0x00000000
-#define mmGRBM_SCRATCH_REG4_DEFAULT 0x00000000
-#define mmGRBM_SCRATCH_REG5_DEFAULT 0x00000000
-#define mmGRBM_SCRATCH_REG6_DEFAULT 0x00000000
-#define mmGRBM_SCRATCH_REG7_DEFAULT 0x00000000
-
-
-// addressBlock: gc_cpdec
-#define mmCP_CPC_STATUS_DEFAULT 0x00000000
-#define mmCP_CPC_BUSY_STAT_DEFAULT 0x00000000
-#define mmCP_CPC_STALLED_STAT1_DEFAULT 0x00000000
-#define mmCP_CPF_STATUS_DEFAULT 0x00000000
-#define mmCP_CPF_BUSY_STAT_DEFAULT 0x00000000
-#define mmCP_CPF_STALLED_STAT1_DEFAULT 0x00000000
-#define mmCP_CPC_GRBM_FREE_COUNT_DEFAULT 0x00000008
-#define mmCP_MEC_CNTL_DEFAULT 0x50000000
-#define mmCP_MEC_ME1_HEADER_DUMP_DEFAULT 0x00000000
-#define mmCP_MEC_ME2_HEADER_DUMP_DEFAULT 0x00000000
-#define mmCP_CPC_SCRATCH_INDEX_DEFAULT 0x00000000
-#define mmCP_CPC_SCRATCH_DATA_DEFAULT 0x00000000
-#define mmCP_CPF_GRBM_FREE_COUNT_DEFAULT 0x00000004
-#define mmCP_CPC_HALT_HYST_COUNT_DEFAULT 0x00000002
-#define mmCP_PRT_LOD_STATS_CNTL0_DEFAULT 0x00000000
-#define mmCP_PRT_LOD_STATS_CNTL1_DEFAULT 0x00000000
-#define mmCP_PRT_LOD_STATS_CNTL2_DEFAULT 0x00000000
-#define mmCP_PRT_LOD_STATS_CNTL3_DEFAULT 0x00000000
-#define mmCP_CE_COMPARE_COUNT_DEFAULT 0x00000000
-#define mmCP_CE_DE_COUNT_DEFAULT 0x00000000
-#define mmCP_DE_CE_COUNT_DEFAULT 0x00000000
-#define mmCP_DE_LAST_INVAL_COUNT_DEFAULT 0x00000000
-#define mmCP_DE_DE_COUNT_DEFAULT 0x00000000
-#define mmCP_STALLED_STAT3_DEFAULT 0x00000000
-#define mmCP_STALLED_STAT1_DEFAULT 0x00000000
-#define mmCP_STALLED_STAT2_DEFAULT 0x00000000
-#define mmCP_BUSY_STAT_DEFAULT 0x00000000
-#define mmCP_STAT_DEFAULT 0x00000000
-#define mmCP_ME_HEADER_DUMP_DEFAULT 0x00000000
-#define mmCP_PFP_HEADER_DUMP_DEFAULT 0x00000000
-#define mmCP_GRBM_FREE_COUNT_DEFAULT 0x00080808
-#define mmCP_CE_HEADER_DUMP_DEFAULT 0x00000000
-#define mmCP_PFP_INSTR_PNTR_DEFAULT 0x00000000
-#define mmCP_ME_INSTR_PNTR_DEFAULT 0x00000000
-#define mmCP_CE_INSTR_PNTR_DEFAULT 0x00000000
-#define mmCP_MEC1_INSTR_PNTR_DEFAULT 0x00000000
-#define mmCP_MEC2_INSTR_PNTR_DEFAULT 0x00000000
-#define mmCP_CSF_STAT_DEFAULT 0x00000000
-#define mmCP_ME_CNTL_DEFAULT 0x15000000
-#define mmCP_CNTX_STAT_DEFAULT 0x00000000
-#define mmCP_ME_PREEMPTION_DEFAULT 0x00000000
-#define mmCP_ROQ_THRESHOLDS_DEFAULT 0x00003010
-#define mmCP_MEQ_STQ_THRESHOLD_DEFAULT 0x00000010
-#define mmCP_RB2_RPTR_DEFAULT 0x00000000
-#define mmCP_RB1_RPTR_DEFAULT 0x00000000
-#define mmCP_RB0_RPTR_DEFAULT 0x00000000
-#define mmCP_RB_RPTR_DEFAULT 0x00000000
-#define mmCP_RB_WPTR_DELAY_DEFAULT 0x00000000
-#define mmCP_RB_WPTR_POLL_CNTL_DEFAULT 0x00400100
-#define mmCP_ROQ1_THRESHOLDS_DEFAULT 0x30101010
-#define mmCP_ROQ2_THRESHOLDS_DEFAULT 0x40403030
-#define mmCP_STQ_THRESHOLDS_DEFAULT 0x00804000
-#define mmCP_QUEUE_THRESHOLDS_DEFAULT 0x00002b16
-#define mmCP_MEQ_THRESHOLDS_DEFAULT 0x00008040
-#define mmCP_ROQ_AVAIL_DEFAULT 0x00000000
-#define mmCP_STQ_AVAIL_DEFAULT 0x00000000
-#define mmCP_ROQ2_AVAIL_DEFAULT 0x00000000
-#define mmCP_MEQ_AVAIL_DEFAULT 0x00000000
-#define mmCP_CMD_INDEX_DEFAULT 0x00000000
-#define mmCP_CMD_DATA_DEFAULT 0x00000000
-#define mmCP_ROQ_RB_STAT_DEFAULT 0x00000000
-#define mmCP_ROQ_IB1_STAT_DEFAULT 0x00000000
-#define mmCP_ROQ_IB2_STAT_DEFAULT 0x00000000
-#define mmCP_STQ_STAT_DEFAULT 0x00000000
-#define mmCP_STQ_WR_STAT_DEFAULT 0x00000000
-#define mmCP_MEQ_STAT_DEFAULT 0x00000000
-#define mmCP_CEQ1_AVAIL_DEFAULT 0x00000000
-#define mmCP_CEQ2_AVAIL_DEFAULT 0x00000000
-#define mmCP_CE_ROQ_RB_STAT_DEFAULT 0x00000000
-#define mmCP_CE_ROQ_IB1_STAT_DEFAULT 0x00000000
-#define mmCP_CE_ROQ_IB2_STAT_DEFAULT 0x00000000
-
-
-// addressBlock: gc_padec
-#define mmVGT_VTX_VECT_EJECT_REG_DEFAULT 0x0000007d
-#define mmVGT_DMA_DATA_FIFO_DEPTH_DEFAULT 0x00040180
-#define mmVGT_DMA_REQ_FIFO_DEPTH_DEFAULT 0x00000020
-#define mmVGT_DRAW_INIT_FIFO_DEPTH_DEFAULT 0x00000020
-#define mmVGT_LAST_COPY_STATE_DEFAULT 0x00000000
-#define mmVGT_CACHE_INVALIDATION_DEFAULT 0x09000000
-#define mmVGT_STRMOUT_DELAY_DEFAULT 0x00092410
-#define mmVGT_FIFO_DEPTHS_DEFAULT 0x08000040
-#define mmVGT_GS_VERTEX_REUSE_DEFAULT 0x00000010
-#define mmVGT_MC_LAT_CNTL_DEFAULT 0x000000fe
-#define mmIA_CNTL_STATUS_DEFAULT 0x00000000
-#define mmVGT_CNTL_STATUS_DEFAULT 0x00000000
-#define mmWD_CNTL_STATUS_DEFAULT 0x00000000
-#define mmCC_GC_PRIM_CONFIG_DEFAULT 0x0e020000
-#define mmGC_USER_PRIM_CONFIG_DEFAULT 0x00000000
-#define mmWD_QOS_DEFAULT 0x00000000
-#define mmWD_UTCL1_CNTL_DEFAULT 0x00000080
-#define mmWD_UTCL1_STATUS_DEFAULT 0x00000000
-#define mmIA_UTCL1_CNTL_DEFAULT 0x00000080
-#define mmIA_UTCL1_STATUS_DEFAULT 0x00000000
-#define mmVGT_SYS_CONFIG_DEFAULT 0x00000011
-#define mmVGT_VS_MAX_WAVE_ID_DEFAULT 0x0000007f
-#define mmVGT_GS_MAX_WAVE_ID_DEFAULT 0x000000ff
-#define mmGFX_PIPE_CONTROL_DEFAULT 0x00000000
-#define mmCC_GC_SHADER_ARRAY_CONFIG_DEFAULT 0xf8000000
-#define mmGC_USER_SHADER_ARRAY_CONFIG_DEFAULT 0x00000000
-#define mmVGT_DMA_PRIMITIVE_TYPE_DEFAULT 0x00000000
-#define mmVGT_DMA_CONTROL_DEFAULT 0x000000ff
-#define mmVGT_DMA_LS_HS_CONFIG_DEFAULT 0x00000000
-#define mmWD_BUF_RESOURCE_1_DEFAULT 0x00000000
-#define mmWD_BUF_RESOURCE_2_DEFAULT 0x00000000
-#define mmPA_CL_CNTL_STATUS_DEFAULT 0x00000000
-#define mmPA_CL_ENHANCE_DEFAULT 0x00000007
-#define mmPA_SU_CNTL_STATUS_DEFAULT 0x00000000
-#define mmPA_SC_FIFO_DEPTH_CNTL_DEFAULT 0x00000018
-#define mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK_DEFAULT 0x00000000
-#define mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK_DEFAULT 0x00000000
-#define mmPA_SC_TRAP_SCREEN_HV_LOCK_DEFAULT 0x00000000
-#define mmPA_SC_FORCE_EOV_MAX_CNTS_DEFAULT 0x00ffffff
-#define mmPA_SC_BINNER_EVENT_CNTL_0_DEFAULT 0x842a4402
-#define mmPA_SC_BINNER_EVENT_CNTL_1_DEFAULT 0x8a000008
-#define mmPA_SC_BINNER_EVENT_CNTL_2_DEFAULT 0x9118aaa8
-#define mmPA_SC_BINNER_EVENT_CNTL_3_DEFAULT 0x82400025
-#define mmPA_SC_BINNER_TIMEOUT_COUNTER_DEFAULT 0x00000000
-#define mmPA_SC_BINNER_PERF_CNTL_0_DEFAULT 0x00000000
-#define mmPA_SC_BINNER_PERF_CNTL_1_DEFAULT 0x00000000
-#define mmPA_SC_BINNER_PERF_CNTL_2_DEFAULT 0x00000000
-#define mmPA_SC_BINNER_PERF_CNTL_3_DEFAULT 0x00000000
-#define mmPA_SC_FIFO_SIZE_DEFAULT 0x00000000
-#define mmPA_SC_IF_FIFO_SIZE_DEFAULT 0x00000000
-#define mmPA_SC_PKR_WAVE_TABLE_CNTL_DEFAULT 0x00000000
-#define mmPA_UTCL1_CNTL1_DEFAULT 0x00000600
-#define mmPA_UTCL1_CNTL2_DEFAULT 0x00000000
-#define mmPA_SIDEBAND_REQUEST_DELAYS_DEFAULT 0x08000020
-#define mmPA_SC_ENHANCE_DEFAULT 0x00000001
-#define mmPA_SC_ENHANCE_1_DEFAULT 0x00040000
-#define mmPA_SC_DSM_CNTL_DEFAULT 0x00000000
-#define mmPA_SC_TILE_STEERING_CREST_OVERRIDE_DEFAULT 0x00000000
-
-
-// addressBlock: gc_sqdec
-#define mmSQ_CONFIG_DEFAULT 0x01180000
-#define mmSQC_CONFIG_DEFAULT 0x010a2000
-#define mmLDS_CONFIG_DEFAULT 0x00000000
-#define mmSQ_RANDOM_WAVE_PRI_DEFAULT 0x0000007f
-#define mmSQ_REG_CREDITS_DEFAULT 0x00000820
-#define mmSQ_FIFO_SIZES_DEFAULT 0x00000f01
-#define mmSQ_DSM_CNTL_DEFAULT 0x00000000
-#define mmSQ_DSM_CNTL2_DEFAULT 0x00000000
-#define mmSQ_RUNTIME_CONFIG_DEFAULT 0x00000000
-#define mmSH_MEM_BASES_DEFAULT 0x00000000
-#define mmSH_MEM_CONFIG_DEFAULT 0x00000000
-#define mmCC_GC_SHADER_RATE_CONFIG_DEFAULT 0x00000000
-#define mmGC_USER_SHADER_RATE_CONFIG_DEFAULT 0x00000000
-#define mmSQ_INTERRUPT_AUTO_MASK_DEFAULT 0x00ffffff
-#define mmSQ_INTERRUPT_MSG_CTRL_DEFAULT 0x00000000
-#define mmSQ_UTCL1_CNTL1_DEFAULT 0x00000580
-#define mmSQ_UTCL1_CNTL2_DEFAULT 0x00000000
-#define mmSQ_UTCL1_STATUS_DEFAULT 0x00000000
-#define mmSQ_SHADER_TBA_LO_DEFAULT 0x00000000
-#define mmSQ_SHADER_TBA_HI_DEFAULT 0x00000000
-#define mmSQ_SHADER_TMA_LO_DEFAULT 0x00000000
-#define mmSQ_SHADER_TMA_HI_DEFAULT 0x00000000
-#define mmSQC_DSM_CNTL_DEFAULT 0x00000000
-#define mmSQC_DSM_CNTLA_DEFAULT 0x00000000
-#define mmSQC_DSM_CNTLB_DEFAULT 0x00000000
-#define mmSQC_DSM_CNTL2_DEFAULT 0x00000000
-#define mmSQC_DSM_CNTL2A_DEFAULT 0x00000000
-#define mmSQC_DSM_CNTL2B_DEFAULT 0x00000000
-#define mmSQC_EDC_FUE_CNTL_DEFAULT 0x00000000
-#define mmSQC_EDC_CNT2_DEFAULT 0x00000000
-#define mmSQC_EDC_CNT3_DEFAULT 0x00000000
-#define mmSQ_REG_TIMESTAMP_DEFAULT 0x00000000
-#define mmSQ_CMD_TIMESTAMP_DEFAULT 0x00000000
-#define mmSQ_IND_INDEX_DEFAULT 0x00000000
-#define mmSQ_IND_DATA_DEFAULT 0x00000000
-#define mmSQ_CMD_DEFAULT 0x00000000
-#define mmSQ_TIME_HI_DEFAULT 0x00000000
-#define mmSQ_TIME_LO_DEFAULT 0x00000000
-#define mmSQ_DS_0_DEFAULT 0x00000000
-#define mmSQ_DS_1_DEFAULT 0x00000000
-#define mmSQ_EXP_0_DEFAULT 0x00000000
-#define mmSQ_EXP_1_DEFAULT 0x00000000
-#define mmSQ_FLAT_0_DEFAULT 0x00000000
-#define mmSQ_FLAT_1_DEFAULT 0x00000000
-#define mmSQ_GLBL_0_DEFAULT 0x00000000
-#define mmSQ_GLBL_1_DEFAULT 0x00000000
-#define mmSQ_INST_DEFAULT 0x00000000
-#define mmSQ_MIMG_0_DEFAULT 0x00000000
-#define mmSQ_MIMG_1_DEFAULT 0x00000000
-#define mmSQ_MTBUF_0_DEFAULT 0x00000000
-#define mmSQ_MTBUF_1_DEFAULT 0x00000000
-#define mmSQ_MUBUF_0_DEFAULT 0x00000000
-#define mmSQ_MUBUF_1_DEFAULT 0x00000000
-#define mmSQ_SCRATCH_0_DEFAULT 0x00000000
-#define mmSQ_SCRATCH_1_DEFAULT 0x00000000
-#define mmSQ_SMEM_0_DEFAULT 0x00000000
-#define mmSQ_SMEM_1_DEFAULT 0x00000000
-#define mmSQ_SOP1_DEFAULT 0x00000000
-#define mmSQ_SOP2_DEFAULT 0x00000000
-#define mmSQ_SOPC_DEFAULT 0x00000000
-#define mmSQ_SOPK_DEFAULT 0x00000000
-#define mmSQ_SOPP_DEFAULT 0x00000000
-#define mmSQ_VINTRP_DEFAULT 0x00000000
-#define mmSQ_VOP1_DEFAULT 0x00000000
-#define mmSQ_VOP2_DEFAULT 0x00000000
-#define mmSQ_VOP3P_0_DEFAULT 0x00000000
-#define mmSQ_VOP3P_1_DEFAULT 0x00000000
-#define mmSQ_VOP3_0_DEFAULT 0x00000000
-#define mmSQ_VOP3_0_SDST_ENC_DEFAULT 0x00000000
-#define mmSQ_VOP3_1_DEFAULT 0x00000000
-#define mmSQ_VOPC_DEFAULT 0x00000000
-#define mmSQ_VOP_DPP_DEFAULT 0x00000000
-#define mmSQ_VOP_SDWA_DEFAULT 0x00000000
-#define mmSQ_VOP_SDWA_SDST_ENC_DEFAULT 0x00000000
-#define mmSQ_LB_CTR_CTRL_DEFAULT 0x00000000
-#define mmSQ_LB_DATA0_DEFAULT 0x00000000
-#define mmSQ_LB_DATA1_DEFAULT 0x00000000
-#define mmSQ_LB_DATA2_DEFAULT 0x00000000
-#define mmSQ_LB_DATA3_DEFAULT 0x00000000
-#define mmSQ_LB_CTR_SEL_DEFAULT 0x00000000
-#define mmSQ_LB_CTR0_CU_DEFAULT 0xffffffff
-#define mmSQ_LB_CTR1_CU_DEFAULT 0xffffffff
-#define mmSQ_LB_CTR2_CU_DEFAULT 0xffffffff
-#define mmSQ_LB_CTR3_CU_DEFAULT 0xffffffff
-#define mmSQC_EDC_CNT_DEFAULT 0x00000000
-#define mmSQ_EDC_SEC_CNT_DEFAULT 0x00000000
-#define mmSQ_EDC_DED_CNT_DEFAULT 0x00000000
-#define mmSQ_EDC_INFO_DEFAULT 0x00000000
-#define mmSQ_EDC_CNT_DEFAULT 0x00000000
-#define mmSQ_EDC_FUE_CNTL_DEFAULT 0x00000000
-#define mmSQ_THREAD_TRACE_WORD_CMN_DEFAULT 0x00000000
-#define mmSQ_THREAD_TRACE_WORD_EVENT_DEFAULT 0x00000000
-#define mmSQ_THREAD_TRACE_WORD_INST_DEFAULT 0x00000000
-#define mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_DEFAULT 0x00000000
-#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_DEFAULT 0x00000000
-#define mmSQ_THREAD_TRACE_WORD_ISSUE_DEFAULT 0x00000000
-#define mmSQ_THREAD_TRACE_WORD_MISC_DEFAULT 0x00000000
-#define mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2_DEFAULT 0x00000000
-#define mmSQ_THREAD_TRACE_WORD_REG_1_OF_2_DEFAULT 0x00000000
-#define mmSQ_THREAD_TRACE_WORD_REG_2_OF_2_DEFAULT 0x00000000
-#define mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_DEFAULT 0x00000000
-#define mmSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2_DEFAULT 0x00000000
-#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2_DEFAULT 0x00000000
-#define mmSQ_THREAD_TRACE_WORD_WAVE_DEFAULT 0x00000000
-#define mmSQ_THREAD_TRACE_WORD_WAVE_START_DEFAULT 0x00000000
-#define mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2_DEFAULT 0x00000000
-#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2_DEFAULT 0x00000000
-#define mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2_DEFAULT 0x00000000
-#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2_DEFAULT 0x00000000
-#define mmSQ_WREXEC_EXEC_HI_DEFAULT 0x00000000
-#define mmSQ_WREXEC_EXEC_LO_DEFAULT 0x00000000
-#define mmSQ_BUF_RSRC_WORD0_DEFAULT 0x00000000
-#define mmSQ_BUF_RSRC_WORD1_DEFAULT 0x00000000
-#define mmSQ_BUF_RSRC_WORD2_DEFAULT 0x00000000
-#define mmSQ_BUF_RSRC_WORD3_DEFAULT 0x00000000
-#define mmSQ_IMG_RSRC_WORD0_DEFAULT 0x00000000
-#define mmSQ_IMG_RSRC_WORD1_DEFAULT 0x00000000
-#define mmSQ_IMG_RSRC_WORD2_DEFAULT 0x00000000
-#define mmSQ_IMG_RSRC_WORD3_DEFAULT 0x00000000
-#define mmSQ_IMG_RSRC_WORD4_DEFAULT 0x00000000
-#define mmSQ_IMG_RSRC_WORD5_DEFAULT 0x00000000
-#define mmSQ_IMG_RSRC_WORD6_DEFAULT 0x00000000
-#define mmSQ_IMG_RSRC_WORD7_DEFAULT 0x00000000
-#define mmSQ_IMG_SAMP_WORD0_DEFAULT 0x00000000
-#define mmSQ_IMG_SAMP_WORD1_DEFAULT 0x00000000
-#define mmSQ_IMG_SAMP_WORD2_DEFAULT 0x00000000
-#define mmSQ_IMG_SAMP_WORD3_DEFAULT 0x00000000
-#define mmSQ_FLAT_SCRATCH_WORD0_DEFAULT 0x00000000
-#define mmSQ_FLAT_SCRATCH_WORD1_DEFAULT 0x00000000
-#define mmSQ_M0_GPR_IDX_WORD_DEFAULT 0x00000000
-#define mmSQC_ICACHE_UTCL1_CNTL1_DEFAULT 0x00000480
-#define mmSQC_ICACHE_UTCL1_CNTL2_DEFAULT 0x00000000
-#define mmSQC_DCACHE_UTCL1_CNTL1_DEFAULT 0x00000500
-#define mmSQC_DCACHE_UTCL1_CNTL2_DEFAULT 0x00000000
-#define mmSQC_ICACHE_UTCL1_STATUS_DEFAULT 0x00000000
-#define mmSQC_DCACHE_UTCL1_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: gc_shsdec
-#define mmSX_DEBUG_1_DEFAULT 0x00000020
-#define mmSPI_PS_MAX_WAVE_ID_DEFAULT 0x020000ff
-#define mmSPI_START_PHASE_DEFAULT 0x00000000
-#define mmSPI_GFX_CNTL_DEFAULT 0x00000000
-#define mmSPI_DSM_CNTL_DEFAULT 0x00000000
-#define mmSPI_DSM_CNTL2_DEFAULT 0x00000000
-#define mmSPI_EDC_CNT_DEFAULT 0x00000000
-#define mmSPI_CONFIG_PS_CU_EN_DEFAULT 0x00000000
-#define mmSPI_WF_LIFETIME_CNTL_DEFAULT 0x00000000
-#define mmSPI_WF_LIFETIME_LIMIT_0_DEFAULT 0x00000100
-#define mmSPI_WF_LIFETIME_LIMIT_1_DEFAULT 0x00000100
-#define mmSPI_WF_LIFETIME_LIMIT_2_DEFAULT 0x00000100
-#define mmSPI_WF_LIFETIME_LIMIT_3_DEFAULT 0x00000100
-#define mmSPI_WF_LIFETIME_LIMIT_4_DEFAULT 0x00000100
-#define mmSPI_WF_LIFETIME_LIMIT_5_DEFAULT 0x00000100
-#define mmSPI_WF_LIFETIME_LIMIT_6_DEFAULT 0x00000100
-#define mmSPI_WF_LIFETIME_LIMIT_7_DEFAULT 0x00000100
-#define mmSPI_WF_LIFETIME_LIMIT_8_DEFAULT 0x00000100
-#define mmSPI_WF_LIFETIME_LIMIT_9_DEFAULT 0x00000100
-#define mmSPI_WF_LIFETIME_STATUS_0_DEFAULT 0x00000000
-#define mmSPI_WF_LIFETIME_STATUS_1_DEFAULT 0x00000000
-#define mmSPI_WF_LIFETIME_STATUS_2_DEFAULT 0x00000000
-#define mmSPI_WF_LIFETIME_STATUS_3_DEFAULT 0x00000000
-#define mmSPI_WF_LIFETIME_STATUS_4_DEFAULT 0x00000000
-#define mmSPI_WF_LIFETIME_STATUS_5_DEFAULT 0x00000000
-#define mmSPI_WF_LIFETIME_STATUS_6_DEFAULT 0x00000000
-#define mmSPI_WF_LIFETIME_STATUS_7_DEFAULT 0x00000000
-#define mmSPI_WF_LIFETIME_STATUS_8_DEFAULT 0x00000000
-#define mmSPI_WF_LIFETIME_STATUS_9_DEFAULT 0x00000000
-#define mmSPI_WF_LIFETIME_STATUS_10_DEFAULT 0x00000000
-#define mmSPI_WF_LIFETIME_STATUS_11_DEFAULT 0x00000000
-#define mmSPI_WF_LIFETIME_STATUS_12_DEFAULT 0x00000000
-#define mmSPI_WF_LIFETIME_STATUS_13_DEFAULT 0x00000000
-#define mmSPI_WF_LIFETIME_STATUS_14_DEFAULT 0x00000000
-#define mmSPI_WF_LIFETIME_STATUS_15_DEFAULT 0x00000000
-#define mmSPI_WF_LIFETIME_STATUS_16_DEFAULT 0x00000000
-#define mmSPI_WF_LIFETIME_STATUS_17_DEFAULT 0x00000000
-#define mmSPI_WF_LIFETIME_STATUS_18_DEFAULT 0x00000000
-#define mmSPI_WF_LIFETIME_STATUS_19_DEFAULT 0x00000000
-#define mmSPI_WF_LIFETIME_STATUS_20_DEFAULT 0x00000000
-#define mmSPI_LB_CTR_CTRL_DEFAULT 0x00000000
-#define mmSPI_LB_CU_MASK_DEFAULT 0x0000ffff
-#define mmSPI_LB_DATA_REG_DEFAULT 0x00000000
-#define mmSPI_PG_ENABLE_STATIC_CU_MASK_DEFAULT 0x0000ffff
-#define mmSPI_GDS_CREDITS_DEFAULT 0x00001080
-#define mmSPI_SX_EXPORT_BUFFER_SIZES_DEFAULT 0x08000800
-#define mmSPI_SX_SCOREBOARD_BUFFER_SIZES_DEFAULT 0x00200040
-#define mmSPI_CSQ_WF_ACTIVE_STATUS_DEFAULT 0x00000000
-#define mmSPI_CSQ_WF_ACTIVE_COUNT_0_DEFAULT 0x00000000
-#define mmSPI_CSQ_WF_ACTIVE_COUNT_1_DEFAULT 0x00000000
-#define mmSPI_CSQ_WF_ACTIVE_COUNT_2_DEFAULT 0x00000000
-#define mmSPI_CSQ_WF_ACTIVE_COUNT_3_DEFAULT 0x00000000
-#define mmSPI_CSQ_WF_ACTIVE_COUNT_4_DEFAULT 0x00000000
-#define mmSPI_CSQ_WF_ACTIVE_COUNT_5_DEFAULT 0x00000000
-#define mmSPI_CSQ_WF_ACTIVE_COUNT_6_DEFAULT 0x00000000
-#define mmSPI_CSQ_WF_ACTIVE_COUNT_7_DEFAULT 0x00000000
-#define mmSPI_LB_DATA_WAVES_DEFAULT 0x00000000
-#define mmSPI_LB_DATA_PERCU_WAVE_HSGS_DEFAULT 0x00000000
-#define mmSPI_LB_DATA_PERCU_WAVE_VSPS_DEFAULT 0x00000000
-#define mmSPI_LB_DATA_PERCU_WAVE_CS_DEFAULT 0x00000000
-#define mmSPI_P0_TRAP_SCREEN_PSBA_LO_DEFAULT 0x00000000
-#define mmSPI_P0_TRAP_SCREEN_PSBA_HI_DEFAULT 0x00000000
-#define mmSPI_P0_TRAP_SCREEN_PSMA_LO_DEFAULT 0x00000000
-#define mmSPI_P0_TRAP_SCREEN_PSMA_HI_DEFAULT 0x00000000
-#define mmSPI_P0_TRAP_SCREEN_GPR_MIN_DEFAULT 0x00000000
-#define mmSPI_P1_TRAP_SCREEN_PSBA_LO_DEFAULT 0x00000000
-#define mmSPI_P1_TRAP_SCREEN_PSBA_HI_DEFAULT 0x00000000
-#define mmSPI_P1_TRAP_SCREEN_PSMA_LO_DEFAULT 0x00000000
-#define mmSPI_P1_TRAP_SCREEN_PSMA_HI_DEFAULT 0x00000000
-#define mmSPI_P1_TRAP_SCREEN_GPR_MIN_DEFAULT 0x00000000
-
-
-// addressBlock: gc_tpdec
-#define mmTD_CNTL_DEFAULT 0x00000000
-#define mmTD_STATUS_DEFAULT 0x00000000
-#define mmTD_DSM_CNTL_DEFAULT 0x00000000
-#define mmTD_DSM_CNTL2_DEFAULT 0x00000000
-#define mmTD_SCRATCH_DEFAULT 0x00000000
-#define mmTA_CNTL_DEFAULT 0x8004d850
-#define mmTA_CNTL_AUX_DEFAULT 0x00000000
-#define mmTA_RESERVED_010C_DEFAULT 0x00000000
-#define mmTA_GRAD_ADJ_DEFAULT 0x40000040
-#define mmTA_STATUS_DEFAULT 0x00000000
-#define mmTA_SCRATCH_DEFAULT 0x00000000
-
-
-// addressBlock: gc_gdsdec
-#define mmGDS_CONFIG_DEFAULT 0x00000000
-#define mmGDS_CNTL_STATUS_DEFAULT 0x00000000
-#define mmGDS_ENHANCE2_DEFAULT 0x00000000
-#define mmGDS_PROTECTION_FAULT_DEFAULT 0x00000000
-#define mmGDS_VM_PROTECTION_FAULT_DEFAULT 0x00000000
-#define mmGDS_EDC_CNT_DEFAULT 0x00000000
-#define mmGDS_EDC_GRBM_CNT_DEFAULT 0x00000000
-#define mmGDS_EDC_OA_DED_DEFAULT 0x00000000
-#define mmGDS_DSM_CNTL_DEFAULT 0x00000000
-#define mmGDS_EDC_OA_PHY_CNT_DEFAULT 0x00000000
-#define mmGDS_EDC_OA_PIPE_CNT_DEFAULT 0x00000000
-#define mmGDS_DSM_CNTL2_DEFAULT 0x00000000
-#define mmGDS_WD_GDS_CSB_DEFAULT 0x00000000
-
-
-// addressBlock: gc_rbdec
-#define mmDB_DEBUG_DEFAULT 0x00000000
-#define mmDB_DEBUG2_DEFAULT 0x00000000
-#define mmDB_DEBUG3_DEFAULT 0x00000000
-#define mmDB_DEBUG4_DEFAULT 0x00000000
-#define mmDB_CREDIT_LIMIT_DEFAULT 0x00000000
-#define mmDB_WATERMARKS_DEFAULT 0x01020204
-#define mmDB_SUBTILE_CONTROL_DEFAULT 0x00000000
-#define mmDB_FREE_CACHELINES_DEFAULT 0x00000000
-#define mmDB_FIFO_DEPTH1_DEFAULT 0x00000000
-#define mmDB_FIFO_DEPTH2_DEFAULT 0x00000000
-#define mmDB_EXCEPTION_CONTROL_DEFAULT 0x00000000
-#define mmDB_RING_CONTROL_DEFAULT 0x00000001
-#define mmDB_MEM_ARB_WATERMARKS_DEFAULT 0x04040404
-#define mmDB_RMI_CACHE_POLICY_DEFAULT 0x0f0f0f07
-#define mmDB_DFSM_CONFIG_DEFAULT 0x00007f00
-#define mmDB_DFSM_WATERMARK_DEFAULT 0x00640064
-#define mmDB_DFSM_TILES_IN_FLIGHT_DEFAULT 0x05dc03e8
-#define mmDB_DFSM_PRIMS_IN_FLIGHT_DEFAULT 0x00fa00c8
-#define mmDB_DFSM_WATCHDOG_DEFAULT 0x000f4240
-#define mmDB_DFSM_FLUSH_ENABLE_DEFAULT 0x000003ff
-#define mmDB_DFSM_FLUSH_AUX_EVENT_DEFAULT 0x00000000
-#define mmCC_RB_REDUNDANCY_DEFAULT 0x00000000
-#define mmCC_RB_BACKEND_DISABLE_DEFAULT 0x00000000
-#define mmGB_ADDR_CONFIG_DEFAULT 0x26010011
-#define mmGB_BACKEND_MAP_DEFAULT 0x33221100
-#define mmGB_GPU_ID_DEFAULT 0x00000000
-#define mmCC_RB_DAISY_CHAIN_DEFAULT 0x76543210
-#define mmGB_ADDR_CONFIG_READ_DEFAULT 0x26010011
-#define mmGB_TILE_MODE0_DEFAULT 0x00000000
-#define mmGB_TILE_MODE1_DEFAULT 0x00000000
-#define mmGB_TILE_MODE2_DEFAULT 0x00000000
-#define mmGB_TILE_MODE3_DEFAULT 0x00000000
-#define mmGB_TILE_MODE4_DEFAULT 0x00000000
-#define mmGB_TILE_MODE5_DEFAULT 0x00000000
-#define mmGB_TILE_MODE6_DEFAULT 0x00000000
-#define mmGB_TILE_MODE7_DEFAULT 0x00000000
-#define mmGB_TILE_MODE8_DEFAULT 0x00000000
-#define mmGB_TILE_MODE9_DEFAULT 0x00000000
-#define mmGB_TILE_MODE10_DEFAULT 0x00000000
-#define mmGB_TILE_MODE11_DEFAULT 0x00000000
-#define mmGB_TILE_MODE12_DEFAULT 0x00000000
-#define mmGB_TILE_MODE13_DEFAULT 0x00000000
-#define mmGB_TILE_MODE14_DEFAULT 0x00000000
-#define mmGB_TILE_MODE15_DEFAULT 0x00000000
-#define mmGB_TILE_MODE16_DEFAULT 0x00000000
-#define mmGB_TILE_MODE17_DEFAULT 0x00000000
-#define mmGB_TILE_MODE18_DEFAULT 0x00000000
-#define mmGB_TILE_MODE19_DEFAULT 0x00000000
-#define mmGB_TILE_MODE20_DEFAULT 0x00000000
-#define mmGB_TILE_MODE21_DEFAULT 0x00000000
-#define mmGB_TILE_MODE22_DEFAULT 0x00000000
-#define mmGB_TILE_MODE23_DEFAULT 0x00000000
-#define mmGB_TILE_MODE24_DEFAULT 0x00000000
-#define mmGB_TILE_MODE25_DEFAULT 0x00000000
-#define mmGB_TILE_MODE26_DEFAULT 0x00000000
-#define mmGB_TILE_MODE27_DEFAULT 0x00000000
-#define mmGB_TILE_MODE28_DEFAULT 0x00000000
-#define mmGB_TILE_MODE29_DEFAULT 0x00000000
-#define mmGB_TILE_MODE30_DEFAULT 0x00000000
-#define mmGB_TILE_MODE31_DEFAULT 0x00000000
-#define mmGB_MACROTILE_MODE0_DEFAULT 0x00000000
-#define mmGB_MACROTILE_MODE1_DEFAULT 0x00000000
-#define mmGB_MACROTILE_MODE2_DEFAULT 0x00000000
-#define mmGB_MACROTILE_MODE3_DEFAULT 0x00000000
-#define mmGB_MACROTILE_MODE4_DEFAULT 0x00000000
-#define mmGB_MACROTILE_MODE5_DEFAULT 0x00000000
-#define mmGB_MACROTILE_MODE6_DEFAULT 0x00000000
-#define mmGB_MACROTILE_MODE7_DEFAULT 0x00000000
-#define mmGB_MACROTILE_MODE8_DEFAULT 0x00000000
-#define mmGB_MACROTILE_MODE9_DEFAULT 0x00000000
-#define mmGB_MACROTILE_MODE10_DEFAULT 0x00000000
-#define mmGB_MACROTILE_MODE11_DEFAULT 0x00000000
-#define mmGB_MACROTILE_MODE12_DEFAULT 0x00000000
-#define mmGB_MACROTILE_MODE13_DEFAULT 0x00000000
-#define mmGB_MACROTILE_MODE14_DEFAULT 0x00000000
-#define mmGB_MACROTILE_MODE15_DEFAULT 0x00000000
-#define mmCB_HW_CONTROL_DEFAULT 0x00014107
-#define mmCB_HW_CONTROL_1_DEFAULT 0x10000000
-#define mmCB_HW_CONTROL_2_DEFAULT 0x00000000
-#define mmCB_HW_CONTROL_3_DEFAULT 0x00000000
-#define mmCB_HW_MEM_ARBITER_RD_DEFAULT 0x00029000
-#define mmCB_HW_MEM_ARBITER_WR_DEFAULT 0x00029000
-#define mmCB_DCC_CONFIG_DEFAULT 0x04000000
-#define mmGC_USER_RB_REDUNDANCY_DEFAULT 0x00000000
-#define mmGC_USER_RB_BACKEND_DISABLE_DEFAULT 0x00000000
-
-
-// addressBlock: gc_ea_gceadec2
-#define mmGCEA_EDC_CNT_DEFAULT 0x00000000
-#define mmGCEA_EDC_CNT2_DEFAULT 0x00000000
-#define mmGCEA_DSM_CNTL_DEFAULT 0x00000000
-#define mmGCEA_DSM_CNTLA_DEFAULT 0x00000000
-#define mmGCEA_DSM_CNTLB_DEFAULT 0x00000000
-#define mmGCEA_DSM_CNTL2_DEFAULT 0x00000000
-#define mmGCEA_DSM_CNTL2A_DEFAULT 0x00000000
-#define mmGCEA_DSM_CNTL2B_DEFAULT 0x00000000
-#define mmGCEA_TCC_XBR_CREDITS_DEFAULT 0x637f637f
-#define mmGCEA_TCC_XBR_MAXBURST_DEFAULT 0x00003333
-#define mmGCEA_PROBE_CNTL_DEFAULT 0x00000000
-#define mmGCEA_PROBE_MAP_DEFAULT 0x0000aaaa
-#define mmGCEA_ERR_STATUS_DEFAULT 0x00000000
-#define mmGCEA_MISC2_DEFAULT 0x00000000
-#define mmGCEA_SDP_BACKDOOR_CMDCREDITS0_DEFAULT 0x00000000
-#define mmGCEA_SDP_BACKDOOR_CMDCREDITS1_DEFAULT 0x00000000
-#define mmGCEA_SDP_BACKDOOR_DATACREDITS0_DEFAULT 0x00000000
-#define mmGCEA_SDP_BACKDOOR_DATACREDITS1_DEFAULT 0x00000000
-#define mmGCEA_SDP_BACKDOOR_MISCCREDITS_DEFAULT 0x00000000
-#define mmGCEA_SDP_ENABLE_DEFAULT 0x00000000
-
-
-// addressBlock: gc_rmi_rmidec
-#define mmRMI_GENERAL_CNTL_DEFAULT 0x00000000
-#define mmRMI_GENERAL_CNTL1_DEFAULT 0x00001a03
-#define mmRMI_GENERAL_STATUS_DEFAULT 0x00000000
-#define mmRMI_SUBBLOCK_STATUS0_DEFAULT 0x00000000
-#define mmRMI_SUBBLOCK_STATUS1_DEFAULT 0x00000000
-#define mmRMI_SUBBLOCK_STATUS2_DEFAULT 0x00000000
-#define mmRMI_SUBBLOCK_STATUS3_DEFAULT 0x00000000
-#define mmRMI_XBAR_CONFIG_DEFAULT 0x00000f00
-#define mmRMI_PROBE_POP_LOGIC_CNTL_DEFAULT 0x000300c0
-#define mmRMI_UTC_XNACK_N_MISC_CNTL_DEFAULT 0x00000564
-#define mmRMI_DEMUX_CNTL_DEFAULT 0x02000200
-#define mmRMI_UTCL1_CNTL1_DEFAULT 0x00020000
-#define mmRMI_UTCL1_CNTL2_DEFAULT 0x00010000
-#define mmRMI_UTC_UNIT_CONFIG_DEFAULT 0x00000000
-#define mmRMI_TCIW_FORMATTER0_CNTL_DEFAULT 0x4404001e
-#define mmRMI_TCIW_FORMATTER1_CNTL_DEFAULT 0x4404001e
-#define mmRMI_SCOREBOARD_CNTL_DEFAULT 0x001ffe00
-#define mmRMI_SCOREBOARD_STATUS0_DEFAULT 0x00000000
-#define mmRMI_SCOREBOARD_STATUS1_DEFAULT 0x00000000
-#define mmRMI_SCOREBOARD_STATUS2_DEFAULT 0x00000000
-#define mmRMI_XBAR_ARBITER_CONFIG_DEFAULT 0x08000800
-#define mmRMI_XBAR_ARBITER_CONFIG_1_DEFAULT 0xffffffff
-#define mmRMI_CLOCK_CNTRL_DEFAULT 0x04208822
-#define mmRMI_UTCL1_STATUS_DEFAULT 0x00000000
-#define mmRMI_SPARE_DEFAULT 0x00000001
-#define mmRMI_SPARE_1_DEFAULT 0x00000000
-#define mmRMI_SPARE_2_DEFAULT 0x00000000
-
-
-// addressBlock: gc_dbgu_gfx_dbgudec
-#define mmport_a_addr_DEFAULT 0x00000000
-#define mmport_a_data_lo_DEFAULT 0x00000000
-#define mmport_a_data_hi_DEFAULT 0x00000000
-#define mmport_b_addr_DEFAULT 0x00000000
-#define mmport_b_data_lo_DEFAULT 0x00000000
-#define mmport_b_data_hi_DEFAULT 0x00000000
-#define mmport_c_addr_DEFAULT 0x00000000
-#define mmport_c_data_lo_DEFAULT 0x00000000
-#define mmport_c_data_hi_DEFAULT 0x00000000
-#define mmport_d_addr_DEFAULT 0x00000000
-#define mmport_d_data_lo_DEFAULT 0x00000000
-#define mmport_d_data_hi_DEFAULT 0x00000000
-
-
-// addressBlock: gc_utcl2_atcl2dec
-#define mmATC_L2_CNTL_DEFAULT 0x000001c9
-#define mmATC_L2_CNTL2_DEFAULT 0x00000100
-#define mmATC_L2_CACHE_DATA0_DEFAULT 0x00000000
-#define mmATC_L2_CACHE_DATA1_DEFAULT 0x00000000
-#define mmATC_L2_CACHE_DATA2_DEFAULT 0x00000000
-#define mmATC_L2_CNTL3_DEFAULT 0x000001f8
-#define mmATC_L2_STATUS_DEFAULT 0x00000000
-#define mmATC_L2_STATUS2_DEFAULT 0x00000000
-#define mmATC_L2_MISC_CG_DEFAULT 0x00000200
-#define mmATC_L2_MEM_POWER_LS_DEFAULT 0x00000208
-#define mmATC_L2_CGTT_CLK_CTRL_DEFAULT 0x00000080
-
-
-// addressBlock: gc_utcl2_vml2pfdec
-#define mmVM_L2_CNTL_DEFAULT 0x00080602
-#define mmVM_L2_CNTL2_DEFAULT 0x00000000
-#define mmVM_L2_CNTL3_DEFAULT 0x80100007
-#define mmVM_L2_STATUS_DEFAULT 0x00000000
-#define mmVM_DUMMY_PAGE_FAULT_CNTL_DEFAULT 0x00000090
-#define mmVM_DUMMY_PAGE_FAULT_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_DUMMY_PAGE_FAULT_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_L2_PROTECTION_FAULT_CNTL_DEFAULT 0x3ffffffc
-#define mmVM_L2_PROTECTION_FAULT_CNTL2_DEFAULT 0x000a0000
-#define mmVM_L2_PROTECTION_FAULT_MM_CNTL3_DEFAULT 0xffffffff
-#define mmVM_L2_PROTECTION_FAULT_MM_CNTL4_DEFAULT 0xffffffff
-#define mmVM_L2_PROTECTION_FAULT_STATUS_DEFAULT 0x00000000
-#define mmVM_L2_PROTECTION_FAULT_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_L2_PROTECTION_FAULT_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_DEFAULT 0x00000000
-#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_DEFAULT 0x00000000
-#define mmVM_L2_CNTL4_DEFAULT 0x000000c1
-#define mmVM_L2_MM_GROUP_RT_CLASSES_DEFAULT 0x00000000
-#define mmVM_L2_BANK_SELECT_RESERVED_CID_DEFAULT 0x00000000
-#define mmVM_L2_BANK_SELECT_RESERVED_CID2_DEFAULT 0x00000000
-#define mmVM_L2_CACHE_PARITY_CNTL_DEFAULT 0x00000000
-#define mmVM_L2_CGTT_CLK_CTRL_DEFAULT 0x00000080
-
-
-// addressBlock: gc_utcl2_vml2vcdec
-#define mmVM_CONTEXT0_CNTL_DEFAULT 0x007ffe80
-#define mmVM_CONTEXT1_CNTL_DEFAULT 0x007ffe80
-#define mmVM_CONTEXT2_CNTL_DEFAULT 0x007ffe80
-#define mmVM_CONTEXT3_CNTL_DEFAULT 0x007ffe80
-#define mmVM_CONTEXT4_CNTL_DEFAULT 0x007ffe80
-#define mmVM_CONTEXT5_CNTL_DEFAULT 0x007ffe80
-#define mmVM_CONTEXT6_CNTL_DEFAULT 0x007ffe80
-#define mmVM_CONTEXT7_CNTL_DEFAULT 0x007ffe80
-#define mmVM_CONTEXT8_CNTL_DEFAULT 0x007ffe80
-#define mmVM_CONTEXT9_CNTL_DEFAULT 0x007ffe80
-#define mmVM_CONTEXT10_CNTL_DEFAULT 0x007ffe80
-#define mmVM_CONTEXT11_CNTL_DEFAULT 0x007ffe80
-#define mmVM_CONTEXT12_CNTL_DEFAULT 0x007ffe80
-#define mmVM_CONTEXT13_CNTL_DEFAULT 0x007ffe80
-#define mmVM_CONTEXT14_CNTL_DEFAULT 0x007ffe80
-#define mmVM_CONTEXT15_CNTL_DEFAULT 0x007ffe80
-#define mmVM_CONTEXTS_DISABLE_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG0_SEM_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG1_SEM_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG2_SEM_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG3_SEM_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG4_SEM_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG5_SEM_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG6_SEM_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG7_SEM_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG8_SEM_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG9_SEM_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG10_SEM_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG11_SEM_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG12_SEM_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG13_SEM_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG14_SEM_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG15_SEM_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG16_SEM_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG17_SEM_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG0_REQ_DEFAULT 0x017c0000
-#define mmVM_INVALIDATE_ENG1_REQ_DEFAULT 0x017c0000
-#define mmVM_INVALIDATE_ENG2_REQ_DEFAULT 0x017c0000
-#define mmVM_INVALIDATE_ENG3_REQ_DEFAULT 0x017c0000
-#define mmVM_INVALIDATE_ENG4_REQ_DEFAULT 0x017c0000
-#define mmVM_INVALIDATE_ENG5_REQ_DEFAULT 0x017c0000
-#define mmVM_INVALIDATE_ENG6_REQ_DEFAULT 0x017c0000
-#define mmVM_INVALIDATE_ENG7_REQ_DEFAULT 0x017c0000
-#define mmVM_INVALIDATE_ENG8_REQ_DEFAULT 0x017c0000
-#define mmVM_INVALIDATE_ENG9_REQ_DEFAULT 0x017c0000
-#define mmVM_INVALIDATE_ENG10_REQ_DEFAULT 0x017c0000
-#define mmVM_INVALIDATE_ENG11_REQ_DEFAULT 0x017c0000
-#define mmVM_INVALIDATE_ENG12_REQ_DEFAULT 0x017c0000
-#define mmVM_INVALIDATE_ENG13_REQ_DEFAULT 0x017c0000
-#define mmVM_INVALIDATE_ENG14_REQ_DEFAULT 0x017c0000
-#define mmVM_INVALIDATE_ENG15_REQ_DEFAULT 0x017c0000
-#define mmVM_INVALIDATE_ENG16_REQ_DEFAULT 0x017c0000
-#define mmVM_INVALIDATE_ENG17_REQ_DEFAULT 0x017c0000
-#define mmVM_INVALIDATE_ENG0_ACK_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG1_ACK_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG2_ACK_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG3_ACK_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG4_ACK_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG5_ACK_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG6_ACK_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG7_ACK_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG8_ACK_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG9_ACK_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG10_ACK_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG11_ACK_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG12_ACK_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG13_ACK_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG14_ACK_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG15_ACK_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG16_ACK_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG17_ACK_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_DEFAULT 0x00000000
-#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
-#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
-#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
-
-
-// addressBlock: gc_utcl2_vmsharedpfdec
-#define mmMC_VM_NB_MMIOBASE_DEFAULT 0x00000000
-#define mmMC_VM_NB_MMIOLIMIT_DEFAULT 0x00000000
-#define mmMC_VM_NB_PCI_CTRL_DEFAULT 0x00000000
-#define mmMC_VM_NB_PCI_ARB_DEFAULT 0x00000008
-#define mmMC_VM_NB_TOP_OF_DRAM_SLOT1_DEFAULT 0x00000000
-#define mmMC_VM_NB_LOWER_TOP_OF_DRAM2_DEFAULT 0x00000000
-#define mmMC_VM_NB_UPPER_TOP_OF_DRAM2_DEFAULT 0x00000000
-#define mmMC_VM_FB_OFFSET_DEFAULT 0x00000000
-#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_DEFAULT 0x00000000
-#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_DEFAULT 0x00000000
-#define mmMC_VM_STEERING_DEFAULT 0x00000001
-#define mmMC_SHARED_VIRT_RESET_REQ_DEFAULT 0x00000000
-#define mmMC_MEM_POWER_LS_DEFAULT 0x00000208
-#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_START_DEFAULT 0x00000000
-#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_END_DEFAULT 0x00000000
-#define mmMC_VM_APT_CNTL_DEFAULT 0x00000000
-#define mmMC_VM_LOCAL_HBM_ADDRESS_START_DEFAULT 0x00000000
-#define mmMC_VM_LOCAL_HBM_ADDRESS_END_DEFAULT 0x000fffff
-#define mmMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_DEFAULT 0x00000000
-
-
-// addressBlock: gc_utcl2_vmsharedvcdec
-#define mmMC_VM_FB_LOCATION_BASE_DEFAULT 0x00000000
-#define mmMC_VM_FB_LOCATION_TOP_DEFAULT 0x00000000
-#define mmMC_VM_AGP_TOP_DEFAULT 0x00000000
-#define mmMC_VM_AGP_BOT_DEFAULT 0x00000000
-#define mmMC_VM_AGP_BASE_DEFAULT 0x00000000
-#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR_DEFAULT 0x00000000
-#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR_DEFAULT 0x00000000
-#define mmMC_VM_MX_L1_TLB_CNTL_DEFAULT 0x00002501
-
-
-// addressBlock: gc_ea_gceadec
-#define mmGCEA_DRAM_RD_CLI2GRP_MAP0_DEFAULT 0xeaaa9580
-#define mmGCEA_DRAM_RD_CLI2GRP_MAP1_DEFAULT 0xeaaa9580
-#define mmGCEA_DRAM_WR_CLI2GRP_MAP0_DEFAULT 0xeaaa9580
-#define mmGCEA_DRAM_WR_CLI2GRP_MAP1_DEFAULT 0xeaaa9580
-#define mmGCEA_DRAM_RD_GRP2VC_MAP_DEFAULT 0x00000924
-#define mmGCEA_DRAM_WR_GRP2VC_MAP_DEFAULT 0x00000324
-#define mmGCEA_DRAM_RD_LAZY_DEFAULT 0x00000924
-#define mmGCEA_DRAM_WR_LAZY_DEFAULT 0x00000924
-#define mmGCEA_DRAM_RD_CAM_CNTL_DEFAULT 0x06db3333
-#define mmGCEA_DRAM_WR_CAM_CNTL_DEFAULT 0x06db3333
-#define mmGCEA_DRAM_PAGE_BURST_DEFAULT 0x20082008
-#define mmGCEA_DRAM_RD_PRI_AGE_DEFAULT 0x00db6249
-#define mmGCEA_DRAM_WR_PRI_AGE_DEFAULT 0x00db6249
-#define mmGCEA_DRAM_RD_PRI_QUEUING_DEFAULT 0x00000db6
-#define mmGCEA_DRAM_WR_PRI_QUEUING_DEFAULT 0x00000db6
-#define mmGCEA_DRAM_RD_PRI_FIXED_DEFAULT 0x00000924
-#define mmGCEA_DRAM_WR_PRI_FIXED_DEFAULT 0x00000924
-#define mmGCEA_DRAM_RD_PRI_URGENCY_DEFAULT 0x0000fdb6
-#define mmGCEA_DRAM_WR_PRI_URGENCY_DEFAULT 0x0000fdb6
-#define mmGCEA_DRAM_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f
-#define mmGCEA_DRAM_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f
-#define mmGCEA_DRAM_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff
-#define mmGCEA_DRAM_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f
-#define mmGCEA_DRAM_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f
-#define mmGCEA_DRAM_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff
-#define mmGCEA_ADDRNORM_BASE_ADDR0_DEFAULT 0x00000000
-#define mmGCEA_ADDRNORM_LIMIT_ADDR0_DEFAULT 0x00000000
-#define mmGCEA_ADDRNORM_BASE_ADDR1_DEFAULT 0x00000000
-#define mmGCEA_ADDRNORM_LIMIT_ADDR1_DEFAULT 0x00000000
-#define mmGCEA_ADDRNORM_OFFSET_ADDR1_DEFAULT 0x00000000
-#define mmGCEA_ADDRNORM_HOLE_CNTL_DEFAULT 0x00000000
-#define mmGCEA_ADDRDEC_BANK_CFG_DEFAULT 0x000001ef
-#define mmGCEA_ADDRDEC_MISC_CFG_DEFAULT 0x3ffff000
-#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK0_DEFAULT 0x00000000
-#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK1_DEFAULT 0x00000000
-#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK2_DEFAULT 0x00000000
-#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK3_DEFAULT 0x00000000
-#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK4_DEFAULT 0x00000000
-#define mmGCEA_ADDRDECDRAM_ADDR_HASH_PC_DEFAULT 0x00000000
-#define mmGCEA_ADDRDECDRAM_ADDR_HASH_PC2_DEFAULT 0x00000000
-#define mmGCEA_ADDRDECDRAM_ADDR_HASH_CS0_DEFAULT 0x00000000
-#define mmGCEA_ADDRDECDRAM_ADDR_HASH_CS1_DEFAULT 0x00000000
-#define mmGCEA_ADDRDECDRAM_HARVEST_ENABLE_DEFAULT 0x00000000
-#define mmGCEA_ADDRDEC0_BASE_ADDR_CS0_DEFAULT 0x00000000
-#define mmGCEA_ADDRDEC0_BASE_ADDR_CS1_DEFAULT 0x00000000
-#define mmGCEA_ADDRDEC0_BASE_ADDR_CS2_DEFAULT 0x00000000
-#define mmGCEA_ADDRDEC0_BASE_ADDR_CS3_DEFAULT 0x00000000
-#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS0_DEFAULT 0x00000000
-#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS1_DEFAULT 0x00000000
-#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS2_DEFAULT 0x00000000
-#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS3_DEFAULT 0x00000000
-#define mmGCEA_ADDRDEC0_ADDR_MASK_CS01_DEFAULT 0xfffffffe
-#define mmGCEA_ADDRDEC0_ADDR_MASK_CS23_DEFAULT 0xfffffffe
-#define mmGCEA_ADDRDEC0_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe
-#define mmGCEA_ADDRDEC0_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe
-#define mmGCEA_ADDRDEC0_ADDR_CFG_CS01_DEFAULT 0x00050408
-#define mmGCEA_ADDRDEC0_ADDR_CFG_CS23_DEFAULT 0x00050408
-#define mmGCEA_ADDRDEC0_ADDR_SEL_CS01_DEFAULT 0x04076543
-#define mmGCEA_ADDRDEC0_ADDR_SEL_CS23_DEFAULT 0x04076543
-#define mmGCEA_ADDRDEC0_COL_SEL_LO_CS01_DEFAULT 0x87654321
-#define mmGCEA_ADDRDEC0_COL_SEL_LO_CS23_DEFAULT 0x87654321
-#define mmGCEA_ADDRDEC0_COL_SEL_HI_CS01_DEFAULT 0xa9876543
-#define mmGCEA_ADDRDEC0_COL_SEL_HI_CS23_DEFAULT 0xa9876543
-#define mmGCEA_ADDRDEC0_RM_SEL_CS01_DEFAULT 0x00000000
-#define mmGCEA_ADDRDEC0_RM_SEL_CS23_DEFAULT 0x00000000
-#define mmGCEA_ADDRDEC0_RM_SEL_SECCS01_DEFAULT 0x00000000
-#define mmGCEA_ADDRDEC0_RM_SEL_SECCS23_DEFAULT 0x00000000
-#define mmGCEA_ADDRDEC1_BASE_ADDR_CS0_DEFAULT 0x00000000
-#define mmGCEA_ADDRDEC1_BASE_ADDR_CS1_DEFAULT 0x00000000
-#define mmGCEA_ADDRDEC1_BASE_ADDR_CS2_DEFAULT 0x00000000
-#define mmGCEA_ADDRDEC1_BASE_ADDR_CS3_DEFAULT 0x00000000
-#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS0_DEFAULT 0x00000000
-#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS1_DEFAULT 0x00000000
-#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS2_DEFAULT 0x00000000
-#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS3_DEFAULT 0x00000000
-#define mmGCEA_ADDRDEC1_ADDR_MASK_CS01_DEFAULT 0xfffffffe
-#define mmGCEA_ADDRDEC1_ADDR_MASK_CS23_DEFAULT 0xfffffffe
-#define mmGCEA_ADDRDEC1_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe
-#define mmGCEA_ADDRDEC1_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe
-#define mmGCEA_ADDRDEC1_ADDR_CFG_CS01_DEFAULT 0x00050408
-#define mmGCEA_ADDRDEC1_ADDR_CFG_CS23_DEFAULT 0x00050408
-#define mmGCEA_ADDRDEC1_ADDR_SEL_CS01_DEFAULT 0x04076543
-#define mmGCEA_ADDRDEC1_ADDR_SEL_CS23_DEFAULT 0x04076543
-#define mmGCEA_ADDRDEC1_COL_SEL_LO_CS01_DEFAULT 0x87654321
-#define mmGCEA_ADDRDEC1_COL_SEL_LO_CS23_DEFAULT 0x87654321
-#define mmGCEA_ADDRDEC1_COL_SEL_HI_CS01_DEFAULT 0xa9876543
-#define mmGCEA_ADDRDEC1_COL_SEL_HI_CS23_DEFAULT 0xa9876543
-#define mmGCEA_ADDRDEC1_RM_SEL_CS01_DEFAULT 0x00000000
-#define mmGCEA_ADDRDEC1_RM_SEL_CS23_DEFAULT 0x00000000
-#define mmGCEA_ADDRDEC1_RM_SEL_SECCS01_DEFAULT 0x00000000
-#define mmGCEA_ADDRDEC1_RM_SEL_SECCS23_DEFAULT 0x00000000
-#define mmGCEA_IO_RD_CLI2GRP_MAP0_DEFAULT 0xeaaa9580
-#define mmGCEA_IO_RD_CLI2GRP_MAP1_DEFAULT 0xeaaa9580
-#define mmGCEA_IO_WR_CLI2GRP_MAP0_DEFAULT 0xeaaa9580
-#define mmGCEA_IO_WR_CLI2GRP_MAP1_DEFAULT 0xeaaa9580
-#define mmGCEA_IO_RD_COMBINE_FLUSH_DEFAULT 0x00007777
-#define mmGCEA_IO_WR_COMBINE_FLUSH_DEFAULT 0x00007777
-#define mmGCEA_IO_GROUP_BURST_DEFAULT 0x1f031f03
-#define mmGCEA_IO_RD_PRI_AGE_DEFAULT 0x00db6249
-#define mmGCEA_IO_WR_PRI_AGE_DEFAULT 0x00db6249
-#define mmGCEA_IO_RD_PRI_QUEUING_DEFAULT 0x00000db6
-#define mmGCEA_IO_WR_PRI_QUEUING_DEFAULT 0x00000db6
-#define mmGCEA_IO_RD_PRI_FIXED_DEFAULT 0x00000924
-#define mmGCEA_IO_WR_PRI_FIXED_DEFAULT 0x00000924
-#define mmGCEA_IO_RD_PRI_URGENCY_DEFAULT 0x00000492
-#define mmGCEA_IO_WR_PRI_URGENCY_DEFAULT 0x00000492
-#define mmGCEA_IO_RD_PRI_URGENCY_MASK_DEFAULT 0xffffffff
-#define mmGCEA_IO_WR_PRI_URGENCY_MASK_DEFAULT 0xffffffff
-#define mmGCEA_IO_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f
-#define mmGCEA_IO_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f
-#define mmGCEA_IO_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff
-#define mmGCEA_IO_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f
-#define mmGCEA_IO_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f
-#define mmGCEA_IO_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff
-#define mmGCEA_SDP_ARB_DRAM_DEFAULT 0x00102040
-#define mmGCEA_SDP_ARB_FINAL_DEFAULT 0x00007fff
-#define mmGCEA_SDP_DRAM_PRIORITY_DEFAULT 0x00000000
-#define mmGCEA_SDP_IO_PRIORITY_DEFAULT 0x00000000
-#define mmGCEA_SDP_CREDITS_DEFAULT 0x000100bf
-#define mmGCEA_SDP_TAG_RESERVE0_DEFAULT 0x00000000
-#define mmGCEA_SDP_TAG_RESERVE1_DEFAULT 0x00000000
-#define mmGCEA_SDP_VCC_RESERVE0_DEFAULT 0x00000000
-#define mmGCEA_SDP_VCC_RESERVE1_DEFAULT 0x00000000
-#define mmGCEA_SDP_VCD_RESERVE0_DEFAULT 0x00000000
-#define mmGCEA_SDP_VCD_RESERVE1_DEFAULT 0x00000000
-#define mmGCEA_SDP_REQ_CNTL_DEFAULT 0x0000000f
-#define mmGCEA_MISC_DEFAULT 0x0de03ff0
-#define mmGCEA_LATENCY_SAMPLING_DEFAULT 0x00000000
-#define mmGCEA_PERFCOUNTER_LO_DEFAULT 0x00000000
-#define mmGCEA_PERFCOUNTER_HI_DEFAULT 0x00000000
-#define mmGCEA_PERFCOUNTER0_CFG_DEFAULT 0x00000000
-#define mmGCEA_PERFCOUNTER1_CFG_DEFAULT 0x00000000
-#define mmGCEA_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000
-
-
-// addressBlock: gc_tcdec
-#define mmTCP_INVALIDATE_DEFAULT 0x00000000
-#define mmTCP_STATUS_DEFAULT 0x00000000
-#define mmTCP_CNTL_DEFAULT 0x2f9c0000
-#define mmTCP_CHAN_STEER_LO_DEFAULT 0x76543210
-#define mmTCP_CHAN_STEER_HI_DEFAULT 0xfedcba98
-#define mmTCP_ADDR_CONFIG_DEFAULT 0x000000f3
-#define mmTCP_CREDIT_DEFAULT 0x804001c0
-#define mmTCP_BUFFER_ADDR_HASH_CNTL_DEFAULT 0x00000000
-#define mmTCP_EDC_CNT_DEFAULT 0x00000000
-#define mmTC_CFG_L1_LOAD_POLICY0_DEFAULT 0x00000000
-#define mmTC_CFG_L1_LOAD_POLICY1_DEFAULT 0x00000000
-#define mmTC_CFG_L1_STORE_POLICY_DEFAULT 0x00000000
-#define mmTC_CFG_L2_LOAD_POLICY0_DEFAULT 0x00000000
-#define mmTC_CFG_L2_LOAD_POLICY1_DEFAULT 0x00000000
-#define mmTC_CFG_L2_STORE_POLICY0_DEFAULT 0x00000000
-#define mmTC_CFG_L2_STORE_POLICY1_DEFAULT 0x00000000
-#define mmTC_CFG_L2_ATOMIC_POLICY_DEFAULT 0x00000000
-#define mmTC_CFG_L1_VOLATILE_DEFAULT 0x00000000
-#define mmTC_CFG_L2_VOLATILE_DEFAULT 0x00000000
-#define mmTCI_STATUS_DEFAULT 0x00000000
-#define mmTCI_CNTL_1_DEFAULT 0x40080022
-#define mmTCI_CNTL_2_DEFAULT 0x00000041
-#define mmTCC_CTRL_DEFAULT 0xf30fff7f
-#define mmTCC_CTRL2_DEFAULT 0x0000000f
-#define mmTCC_EDC_CNT_DEFAULT 0x00000000
-#define mmTCC_EDC_CNT2_DEFAULT 0x00000000
-#define mmTCC_REDUNDANCY_DEFAULT 0x00000000
-#define mmTCC_EXE_DISABLE_DEFAULT 0x00000000
-#define mmTCC_DSM_CNTL_DEFAULT 0x00000000
-#define mmTCC_DSM_CNTLA_DEFAULT 0x00000000
-#define mmTCC_DSM_CNTL2_DEFAULT 0x00000000
-#define mmTCC_DSM_CNTL2A_DEFAULT 0x00000000
-#define mmTCC_DSM_CNTL2B_DEFAULT 0x00000000
-#define mmTCC_WBINVL2_DEFAULT 0x00000010
-#define mmTCC_SOFT_RESET_DEFAULT 0x00000000
-#define mmTCA_CTRL_DEFAULT 0x00000088
-#define mmTCA_BURST_MASK_DEFAULT 0xffffffff
-#define mmTCA_BURST_CTRL_DEFAULT 0x00000007
-#define mmTCA_DSM_CNTL_DEFAULT 0x00000000
-#define mmTCA_DSM_CNTL2_DEFAULT 0x00000000
-#define mmTCA_EDC_CNT_DEFAULT 0x00000000
-
-
-// addressBlock: gc_shdec
-#define mmSPI_SHADER_PGM_RSRC3_PS_DEFAULT 0x0000ffff
-#define mmSPI_SHADER_PGM_LO_PS_DEFAULT 0x00000000
-#define mmSPI_SHADER_PGM_HI_PS_DEFAULT 0x00000000
-#define mmSPI_SHADER_PGM_RSRC1_PS_DEFAULT 0x00000000
-#define mmSPI_SHADER_PGM_RSRC2_PS_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_PS_0_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_PS_1_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_PS_2_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_PS_3_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_PS_4_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_PS_5_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_PS_6_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_PS_7_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_PS_8_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_PS_9_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_PS_10_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_PS_11_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_PS_12_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_PS_13_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_PS_14_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_PS_15_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_PS_16_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_PS_17_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_PS_18_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_PS_19_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_PS_20_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_PS_21_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_PS_22_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_PS_23_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_PS_24_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_PS_25_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_PS_26_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_PS_27_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_PS_28_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_PS_29_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_PS_30_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_PS_31_DEFAULT 0x00000000
-#define mmSPI_SHADER_PGM_RSRC3_VS_DEFAULT 0x0000ffff
-#define mmSPI_SHADER_LATE_ALLOC_VS_DEFAULT 0x00000000
-#define mmSPI_SHADER_PGM_LO_VS_DEFAULT 0x00000000
-#define mmSPI_SHADER_PGM_HI_VS_DEFAULT 0x00000000
-#define mmSPI_SHADER_PGM_RSRC1_VS_DEFAULT 0x00000000
-#define mmSPI_SHADER_PGM_RSRC2_VS_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_VS_0_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_VS_1_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_VS_2_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_VS_3_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_VS_4_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_VS_5_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_VS_6_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_VS_7_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_VS_8_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_VS_9_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_VS_10_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_VS_11_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_VS_12_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_VS_13_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_VS_14_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_VS_15_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_VS_16_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_VS_17_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_VS_18_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_VS_19_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_VS_20_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_VS_21_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_VS_22_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_VS_23_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_VS_24_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_VS_25_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_VS_26_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_VS_27_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_VS_28_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_VS_29_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_VS_30_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_VS_31_DEFAULT 0x00000000
-#define mmSPI_SHADER_PGM_RSRC2_GS_VS_DEFAULT 0x00000000
-#define mmSPI_SHADER_PGM_RSRC4_GS_DEFAULT 0x00000800
-#define mmSPI_SHADER_USER_DATA_ADDR_LO_GS_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ADDR_HI_GS_DEFAULT 0x00000000
-#define mmSPI_SHADER_PGM_LO_ES_DEFAULT 0x00000000
-#define mmSPI_SHADER_PGM_HI_ES_DEFAULT 0x00000000
-#define mmSPI_SHADER_PGM_RSRC3_GS_DEFAULT 0x0000fffe
-#define mmSPI_SHADER_PGM_LO_GS_DEFAULT 0x00000000
-#define mmSPI_SHADER_PGM_HI_GS_DEFAULT 0x00000000
-#define mmSPI_SHADER_PGM_RSRC1_GS_DEFAULT 0x00000000
-#define mmSPI_SHADER_PGM_RSRC2_GS_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ES_0_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ES_1_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ES_2_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ES_3_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ES_4_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ES_5_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ES_6_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ES_7_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ES_8_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ES_9_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ES_10_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ES_11_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ES_12_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ES_13_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ES_14_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ES_15_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ES_16_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ES_17_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ES_18_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ES_19_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ES_20_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ES_21_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ES_22_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ES_23_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ES_24_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ES_25_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ES_26_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ES_27_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ES_28_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ES_29_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ES_30_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ES_31_DEFAULT 0x00000000
-#define mmSPI_SHADER_PGM_RSRC4_HS_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ADDR_LO_HS_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_ADDR_HI_HS_DEFAULT 0x00000000
-#define mmSPI_SHADER_PGM_LO_LS_DEFAULT 0x00000000
-#define mmSPI_SHADER_PGM_HI_LS_DEFAULT 0x00000000
-#define mmSPI_SHADER_PGM_RSRC3_HS_DEFAULT 0xffff0000
-#define mmSPI_SHADER_PGM_LO_HS_DEFAULT 0x00000000
-#define mmSPI_SHADER_PGM_HI_HS_DEFAULT 0x00000000
-#define mmSPI_SHADER_PGM_RSRC1_HS_DEFAULT 0x00000000
-#define mmSPI_SHADER_PGM_RSRC2_HS_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_LS_0_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_LS_1_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_LS_2_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_LS_3_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_LS_4_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_LS_5_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_LS_6_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_LS_7_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_LS_8_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_LS_9_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_LS_10_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_LS_11_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_LS_12_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_LS_13_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_LS_14_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_LS_15_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_LS_16_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_LS_17_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_LS_18_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_LS_19_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_LS_20_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_LS_21_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_LS_22_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_LS_23_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_LS_24_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_LS_25_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_LS_26_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_LS_27_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_LS_28_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_LS_29_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_LS_30_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_LS_31_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_COMMON_0_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_COMMON_1_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_COMMON_2_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_COMMON_3_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_COMMON_4_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_COMMON_5_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_COMMON_6_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_COMMON_7_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_COMMON_8_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_COMMON_9_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_COMMON_10_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_COMMON_11_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_COMMON_12_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_COMMON_13_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_COMMON_14_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_COMMON_15_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_COMMON_16_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_COMMON_17_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_COMMON_18_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_COMMON_19_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_COMMON_20_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_COMMON_21_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_COMMON_22_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_COMMON_23_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_COMMON_24_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_COMMON_25_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_COMMON_26_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_COMMON_27_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_COMMON_28_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_COMMON_29_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_COMMON_30_DEFAULT 0x00000000
-#define mmSPI_SHADER_USER_DATA_COMMON_31_DEFAULT 0x00000000
-#define mmCOMPUTE_DISPATCH_INITIATOR_DEFAULT 0x00000000
-#define mmCOMPUTE_DIM_X_DEFAULT 0x00000000
-#define mmCOMPUTE_DIM_Y_DEFAULT 0x00000000
-#define mmCOMPUTE_DIM_Z_DEFAULT 0x00000000
-#define mmCOMPUTE_START_X_DEFAULT 0x00000000
-#define mmCOMPUTE_START_Y_DEFAULT 0x00000000
-#define mmCOMPUTE_START_Z_DEFAULT 0x00000000
-#define mmCOMPUTE_NUM_THREAD_X_DEFAULT 0x00000000
-#define mmCOMPUTE_NUM_THREAD_Y_DEFAULT 0x00000000
-#define mmCOMPUTE_NUM_THREAD_Z_DEFAULT 0x00000000
-#define mmCOMPUTE_PIPELINESTAT_ENABLE_DEFAULT 0x00000001
-#define mmCOMPUTE_PERFCOUNT_ENABLE_DEFAULT 0x00000000
-#define mmCOMPUTE_PGM_LO_DEFAULT 0x00000000
-#define mmCOMPUTE_PGM_HI_DEFAULT 0x00000000
-#define mmCOMPUTE_DISPATCH_PKT_ADDR_LO_DEFAULT 0x00000000
-#define mmCOMPUTE_DISPATCH_PKT_ADDR_HI_DEFAULT 0x00000000
-#define mmCOMPUTE_DISPATCH_SCRATCH_BASE_LO_DEFAULT 0x00000000
-#define mmCOMPUTE_DISPATCH_SCRATCH_BASE_HI_DEFAULT 0x00000000
-#define mmCOMPUTE_PGM_RSRC1_DEFAULT 0x00000000
-#define mmCOMPUTE_PGM_RSRC2_DEFAULT 0x00000000
-#define mmCOMPUTE_VMID_DEFAULT 0x00000000
-#define mmCOMPUTE_RESOURCE_LIMITS_DEFAULT 0x00000000
-#define mmCOMPUTE_STATIC_THREAD_MGMT_SE0_DEFAULT 0xffffffff
-#define mmCOMPUTE_STATIC_THREAD_MGMT_SE1_DEFAULT 0xffffffff
-#define mmCOMPUTE_TMPRING_SIZE_DEFAULT 0x00000000
-#define mmCOMPUTE_STATIC_THREAD_MGMT_SE2_DEFAULT 0xffffffff
-#define mmCOMPUTE_STATIC_THREAD_MGMT_SE3_DEFAULT 0xffffffff
-#define mmCOMPUTE_RESTART_X_DEFAULT 0x00000000
-#define mmCOMPUTE_RESTART_Y_DEFAULT 0x00000000
-#define mmCOMPUTE_RESTART_Z_DEFAULT 0x00000000
-#define mmCOMPUTE_THREAD_TRACE_ENABLE_DEFAULT 0x00000000
-#define mmCOMPUTE_MISC_RESERVED_DEFAULT 0x00000002
-#define mmCOMPUTE_DISPATCH_ID_DEFAULT 0x00000000
-#define mmCOMPUTE_THREADGROUP_ID_DEFAULT 0x00000000
-#define mmCOMPUTE_RELAUNCH_DEFAULT 0x00000000
-#define mmCOMPUTE_WAVE_RESTORE_ADDR_LO_DEFAULT 0x00000000
-#define mmCOMPUTE_WAVE_RESTORE_ADDR_HI_DEFAULT 0x00000000
-#define mmCOMPUTE_USER_DATA_0_DEFAULT 0x00000000
-#define mmCOMPUTE_USER_DATA_1_DEFAULT 0x00000000
-#define mmCOMPUTE_USER_DATA_2_DEFAULT 0x00000000
-#define mmCOMPUTE_USER_DATA_3_DEFAULT 0x00000000
-#define mmCOMPUTE_USER_DATA_4_DEFAULT 0x00000000
-#define mmCOMPUTE_USER_DATA_5_DEFAULT 0x00000000
-#define mmCOMPUTE_USER_DATA_6_DEFAULT 0x00000000
-#define mmCOMPUTE_USER_DATA_7_DEFAULT 0x00000000
-#define mmCOMPUTE_USER_DATA_8_DEFAULT 0x00000000
-#define mmCOMPUTE_USER_DATA_9_DEFAULT 0x00000000
-#define mmCOMPUTE_USER_DATA_10_DEFAULT 0x00000000
-#define mmCOMPUTE_USER_DATA_11_DEFAULT 0x00000000
-#define mmCOMPUTE_USER_DATA_12_DEFAULT 0x00000000
-#define mmCOMPUTE_USER_DATA_13_DEFAULT 0x00000000
-#define mmCOMPUTE_USER_DATA_14_DEFAULT 0x00000000
-#define mmCOMPUTE_USER_DATA_15_DEFAULT 0x00000000
-#define mmCOMPUTE_NOWHERE_DEFAULT 0x00000000
-
-
-// addressBlock: gc_cppdec
-#define mmCP_DFY_CNTL_DEFAULT 0x00000000
-#define mmCP_DFY_STAT_DEFAULT 0x00000000
-#define mmCP_DFY_ADDR_HI_DEFAULT 0x00000000
-#define mmCP_DFY_ADDR_LO_DEFAULT 0x00000000
-#define mmCP_DFY_DATA_0_DEFAULT 0x00000000
-#define mmCP_DFY_DATA_1_DEFAULT 0x00000000
-#define mmCP_DFY_DATA_2_DEFAULT 0x00000000
-#define mmCP_DFY_DATA_3_DEFAULT 0x00000000
-#define mmCP_DFY_DATA_4_DEFAULT 0x00000000
-#define mmCP_DFY_DATA_5_DEFAULT 0x00000000
-#define mmCP_DFY_DATA_6_DEFAULT 0x00000000
-#define mmCP_DFY_DATA_7_DEFAULT 0x00000000
-#define mmCP_DFY_DATA_8_DEFAULT 0x00000000
-#define mmCP_DFY_DATA_9_DEFAULT 0x00000000
-#define mmCP_DFY_DATA_10_DEFAULT 0x00000000
-#define mmCP_DFY_DATA_11_DEFAULT 0x00000000
-#define mmCP_DFY_DATA_12_DEFAULT 0x00000000
-#define mmCP_DFY_DATA_13_DEFAULT 0x00000000
-#define mmCP_DFY_DATA_14_DEFAULT 0x00000000
-#define mmCP_DFY_DATA_15_DEFAULT 0x00000000
-#define mmCP_DFY_CMD_DEFAULT 0x00000000
-#define mmCP_EOPQ_WAIT_TIME_DEFAULT 0x0000052c
-#define mmCP_CPC_MGCG_SYNC_CNTL_DEFAULT 0x00001020
-#define mmCPC_INT_INFO_DEFAULT 0x00000000
-#define mmCP_VIRT_STATUS_DEFAULT 0x00000000
-#define mmCPC_INT_ADDR_DEFAULT 0x00000000
-#define mmCPC_INT_PASID_DEFAULT 0x00000000
-#define mmCP_GFX_ERROR_DEFAULT 0x00000000
-#define mmCPG_UTCL1_CNTL_DEFAULT 0x00000080
-#define mmCPC_UTCL1_CNTL_DEFAULT 0x00000080
-#define mmCPF_UTCL1_CNTL_DEFAULT 0x00000080
-#define mmCP_AQL_SMM_STATUS_DEFAULT 0x00000000
-#define mmCP_RB0_BASE_DEFAULT 0x00000000
-#define mmCP_RB_BASE_DEFAULT 0x00000000
-#define mmCP_RB0_CNTL_DEFAULT 0x00400000
-#define mmCP_RB_CNTL_DEFAULT 0x00400000
-#define mmCP_RB_RPTR_WR_DEFAULT 0x00000000
-#define mmCP_RB0_RPTR_ADDR_DEFAULT 0x00000000
-#define mmCP_RB_RPTR_ADDR_DEFAULT 0x00000000
-#define mmCP_RB0_RPTR_ADDR_HI_DEFAULT 0x00000000
-#define mmCP_RB_RPTR_ADDR_HI_DEFAULT 0x00000000
-#define mmCP_RB0_BUFSZ_MASK_DEFAULT 0x00000000
-#define mmCP_RB_BUFSZ_MASK_DEFAULT 0x00000000
-#define mmCP_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000
-#define mmCP_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000
-#define mmGC_PRIV_MODE_DEFAULT 0x00000000
-#define mmCP_INT_CNTL_DEFAULT 0x00000000
-#define mmCP_INT_STATUS_DEFAULT 0x00000000
-#define mmCP_DEVICE_ID_DEFAULT 0x00000000
-#define mmCP_ME0_PIPE_PRIORITY_CNTS_DEFAULT 0x08081020
-#define mmCP_RING_PRIORITY_CNTS_DEFAULT 0x08081020
-#define mmCP_ME0_PIPE0_PRIORITY_DEFAULT 0x00000002
-#define mmCP_RING0_PRIORITY_DEFAULT 0x00000002
-#define mmCP_ME0_PIPE1_PRIORITY_DEFAULT 0x00000002
-#define mmCP_RING1_PRIORITY_DEFAULT 0x00000002
-#define mmCP_ME0_PIPE2_PRIORITY_DEFAULT 0x00000002
-#define mmCP_RING2_PRIORITY_DEFAULT 0x00000002
-#define mmCP_FATAL_ERROR_DEFAULT 0x00000000
-#define mmCP_RB_VMID_DEFAULT 0x00000000
-#define mmCP_ME0_PIPE0_VMID_DEFAULT 0x00000000
-#define mmCP_ME0_PIPE1_VMID_DEFAULT 0x00000000
-#define mmCP_RB0_WPTR_DEFAULT 0x00000000
-#define mmCP_RB_WPTR_DEFAULT 0x00000000
-#define mmCP_RB0_WPTR_HI_DEFAULT 0x00000000
-#define mmCP_RB_WPTR_HI_DEFAULT 0x00000000
-#define mmCP_RB1_WPTR_DEFAULT 0x00000000
-#define mmCP_RB1_WPTR_HI_DEFAULT 0x00000000
-#define mmCP_RB2_WPTR_DEFAULT 0x00000000
-#define mmCP_RB_DOORBELL_CONTROL_DEFAULT 0x00000000
-#define mmCP_RB_DOORBELL_RANGE_LOWER_DEFAULT 0x00000000
-#define mmCP_RB_DOORBELL_RANGE_UPPER_DEFAULT 0x00000044
-#define mmCP_MEC_DOORBELL_RANGE_LOWER_DEFAULT 0x00000048
-#define mmCP_MEC_DOORBELL_RANGE_UPPER_DEFAULT 0x0ffffffc
-#define mmCPG_UTCL1_ERROR_DEFAULT 0x00000000
-#define mmCPC_UTCL1_ERROR_DEFAULT 0x00000000
-#define mmCP_RB1_BASE_DEFAULT 0x00000000
-#define mmCP_RB1_CNTL_DEFAULT 0x00400000
-#define mmCP_RB1_RPTR_ADDR_DEFAULT 0x00000000
-#define mmCP_RB1_RPTR_ADDR_HI_DEFAULT 0x00000000
-#define mmCP_RB2_BASE_DEFAULT 0x00000000
-#define mmCP_RB2_CNTL_DEFAULT 0x00400000
-#define mmCP_RB2_RPTR_ADDR_DEFAULT 0x00000000
-#define mmCP_RB2_RPTR_ADDR_HI_DEFAULT 0x00000000
-#define mmCP_RB0_ACTIVE_DEFAULT 0x00000001
-#define mmCP_RB_ACTIVE_DEFAULT 0x00000001
-#define mmCP_INT_CNTL_RING0_DEFAULT 0x00000000
-#define mmCP_INT_CNTL_RING1_DEFAULT 0x00000000
-#define mmCP_INT_CNTL_RING2_DEFAULT 0x00000000
-#define mmCP_INT_STATUS_RING0_DEFAULT 0x00000000
-#define mmCP_INT_STATUS_RING1_DEFAULT 0x00000000
-#define mmCP_INT_STATUS_RING2_DEFAULT 0x00000000
-#define mmCP_PWR_CNTL_DEFAULT 0x00000000
-#define mmCP_MEM_SLP_CNTL_DEFAULT 0x00020200
-#define mmCP_ECC_FIRSTOCCURRENCE_DEFAULT 0x00000000
-#define mmCP_ECC_FIRSTOCCURRENCE_RING0_DEFAULT 0x00000000
-#define mmCP_ECC_FIRSTOCCURRENCE_RING1_DEFAULT 0x00000000
-#define mmCP_ECC_FIRSTOCCURRENCE_RING2_DEFAULT 0x00000000
-#define mmGB_EDC_MODE_DEFAULT 0x00000000
-#define mmCP_PQ_WPTR_POLL_CNTL_DEFAULT 0x00000001
-#define mmCP_PQ_WPTR_POLL_CNTL1_DEFAULT 0x00000000
-#define mmCP_ME1_PIPE0_INT_CNTL_DEFAULT 0x00000000
-#define mmCP_ME1_PIPE1_INT_CNTL_DEFAULT 0x00000000
-#define mmCP_ME1_PIPE2_INT_CNTL_DEFAULT 0x00000000
-#define mmCP_ME1_PIPE3_INT_CNTL_DEFAULT 0x00000000
-#define mmCP_ME2_PIPE0_INT_CNTL_DEFAULT 0x00000000
-#define mmCP_ME2_PIPE1_INT_CNTL_DEFAULT 0x00000000
-#define mmCP_ME2_PIPE2_INT_CNTL_DEFAULT 0x00000000
-#define mmCP_ME2_PIPE3_INT_CNTL_DEFAULT 0x00000000
-#define mmCP_ME1_PIPE0_INT_STATUS_DEFAULT 0x00000000
-#define mmCP_ME1_PIPE1_INT_STATUS_DEFAULT 0x00000000
-#define mmCP_ME1_PIPE2_INT_STATUS_DEFAULT 0x00000000
-#define mmCP_ME1_PIPE3_INT_STATUS_DEFAULT 0x00000000
-#define mmCP_ME2_PIPE0_INT_STATUS_DEFAULT 0x00000000
-#define mmCP_ME2_PIPE1_INT_STATUS_DEFAULT 0x00000000
-#define mmCP_ME2_PIPE2_INT_STATUS_DEFAULT 0x00000000
-#define mmCP_ME2_PIPE3_INT_STATUS_DEFAULT 0x00000000
-#define mmCC_GC_EDC_CONFIG_DEFAULT 0x00000000
-#define mmCP_ME1_PIPE_PRIORITY_CNTS_DEFAULT 0x08081020
-#define mmCP_ME1_PIPE0_PRIORITY_DEFAULT 0x00000002
-#define mmCP_ME1_PIPE1_PRIORITY_DEFAULT 0x00000002
-#define mmCP_ME1_PIPE2_PRIORITY_DEFAULT 0x00000002
-#define mmCP_ME1_PIPE3_PRIORITY_DEFAULT 0x00000002
-#define mmCP_ME2_PIPE_PRIORITY_CNTS_DEFAULT 0x08081020
-#define mmCP_ME2_PIPE0_PRIORITY_DEFAULT 0x00000002
-#define mmCP_ME2_PIPE1_PRIORITY_DEFAULT 0x00000002
-#define mmCP_ME2_PIPE2_PRIORITY_DEFAULT 0x00000002
-#define mmCP_ME2_PIPE3_PRIORITY_DEFAULT 0x00000002
-#define mmCP_CE_PRGRM_CNTR_START_DEFAULT 0x00000000
-#define mmCP_PFP_PRGRM_CNTR_START_DEFAULT 0x00000000
-#define mmCP_ME_PRGRM_CNTR_START_DEFAULT 0x00000000
-#define mmCP_MEC1_PRGRM_CNTR_START_DEFAULT 0x00000000
-#define mmCP_MEC2_PRGRM_CNTR_START_DEFAULT 0x00000000
-#define mmCP_CE_INTR_ROUTINE_START_DEFAULT 0x00000002
-#define mmCP_PFP_INTR_ROUTINE_START_DEFAULT 0x00000002
-#define mmCP_ME_INTR_ROUTINE_START_DEFAULT 0x00000002
-#define mmCP_MEC1_INTR_ROUTINE_START_DEFAULT 0x00000002
-#define mmCP_MEC2_INTR_ROUTINE_START_DEFAULT 0x00000002
-#define mmCP_CONTEXT_CNTL_DEFAULT 0x00750075
-#define mmCP_MAX_CONTEXT_DEFAULT 0x00000007
-#define mmCP_IQ_WAIT_TIME1_DEFAULT 0x40404040
-#define mmCP_IQ_WAIT_TIME2_DEFAULT 0x40404040
-#define mmCP_RB0_BASE_HI_DEFAULT 0x00000000
-#define mmCP_RB1_BASE_HI_DEFAULT 0x00000000
-#define mmCP_VMID_RESET_DEFAULT 0x00000000
-#define mmCPC_INT_CNTL_DEFAULT 0x00000000
-#define mmCPC_INT_STATUS_DEFAULT 0x00000000
-#define mmCP_VMID_PREEMPT_DEFAULT 0x00000000
-#define mmCPC_INT_CNTX_ID_DEFAULT 0x00000000
-#define mmCP_PQ_STATUS_DEFAULT 0x00000000
-#define mmCP_CPC_IC_BASE_LO_DEFAULT 0x00000000
-#define mmCP_CPC_IC_BASE_HI_DEFAULT 0x00000000
-#define mmCP_CPC_IC_BASE_CNTL_DEFAULT 0x00000000
-#define mmCP_CPC_IC_OP_CNTL_DEFAULT 0x00000000
-#define mmCP_MEC1_F32_INT_DIS_DEFAULT 0x00000000
-#define mmCP_MEC2_F32_INT_DIS_DEFAULT 0x00000000
-#define mmCP_VMID_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: gc_cppdec2
-#define mmCP_RB_DOORBELL_CONTROL_SCH_0_DEFAULT 0x00000000
-#define mmCP_RB_DOORBELL_CONTROL_SCH_1_DEFAULT 0x00000000
-#define mmCP_RB_DOORBELL_CONTROL_SCH_2_DEFAULT 0x00000000
-#define mmCP_RB_DOORBELL_CONTROL_SCH_3_DEFAULT 0x00000000
-#define mmCP_RB_DOORBELL_CONTROL_SCH_4_DEFAULT 0x00000000
-#define mmCP_RB_DOORBELL_CONTROL_SCH_5_DEFAULT 0x00000000
-#define mmCP_RB_DOORBELL_CONTROL_SCH_6_DEFAULT 0x00000000
-#define mmCP_RB_DOORBELL_CONTROL_SCH_7_DEFAULT 0x00000000
-#define mmCP_RB_DOORBELL_CLEAR_DEFAULT 0x00000000
-#define mmCP_GFX_MQD_CONTROL_DEFAULT 0x00000100
-#define mmCP_GFX_MQD_BASE_ADDR_DEFAULT 0x00000000
-#define mmCP_GFX_MQD_BASE_ADDR_HI_DEFAULT 0x00000000
-#define mmCP_RB_STATUS_DEFAULT 0x00000000
-#define mmCPG_UTCL1_STATUS_DEFAULT 0x00000000
-#define mmCPC_UTCL1_STATUS_DEFAULT 0x00000000
-#define mmCPF_UTCL1_STATUS_DEFAULT 0x00000000
-#define mmCP_SD_CNTL_DEFAULT 0x0000001f
-#define mmCP_SOFT_RESET_CNTL_DEFAULT 0x00000000
-#define mmCP_CPC_GFX_CNTL_DEFAULT 0x00000000
-
-
-// addressBlock: gc_spipdec
-#define mmSPI_ARB_PRIORITY_DEFAULT 0x00000000
-#define mmSPI_ARB_CYCLES_0_DEFAULT 0x00000000
-#define mmSPI_ARB_CYCLES_1_DEFAULT 0x00000000
-#define mmSPI_WCL_PIPE_PERCENT_GFX_DEFAULT 0x07ffffff
-#define mmSPI_WCL_PIPE_PERCENT_HP3D_DEFAULT 0x07c1f07f
-#define mmSPI_WCL_PIPE_PERCENT_CS0_DEFAULT 0x0000007f
-#define mmSPI_WCL_PIPE_PERCENT_CS1_DEFAULT 0x0000007f
-#define mmSPI_WCL_PIPE_PERCENT_CS2_DEFAULT 0x0000007f
-#define mmSPI_WCL_PIPE_PERCENT_CS3_DEFAULT 0x0000007f
-#define mmSPI_WCL_PIPE_PERCENT_CS4_DEFAULT 0x0000007f
-#define mmSPI_WCL_PIPE_PERCENT_CS5_DEFAULT 0x0000007f
-#define mmSPI_WCL_PIPE_PERCENT_CS6_DEFAULT 0x0000007f
-#define mmSPI_WCL_PIPE_PERCENT_CS7_DEFAULT 0x0000007f
-#define mmSPI_COMPUTE_QUEUE_RESET_DEFAULT 0x00000000
-#define mmSPI_RESOURCE_RESERVE_CU_0_DEFAULT 0x00000000
-#define mmSPI_RESOURCE_RESERVE_CU_1_DEFAULT 0x00000000
-#define mmSPI_RESOURCE_RESERVE_CU_2_DEFAULT 0x00000000
-#define mmSPI_RESOURCE_RESERVE_CU_3_DEFAULT 0x00000000
-#define mmSPI_RESOURCE_RESERVE_CU_4_DEFAULT 0x00000000
-#define mmSPI_RESOURCE_RESERVE_CU_5_DEFAULT 0x00000000
-#define mmSPI_RESOURCE_RESERVE_CU_6_DEFAULT 0x00000000
-#define mmSPI_RESOURCE_RESERVE_CU_7_DEFAULT 0x00000000
-#define mmSPI_RESOURCE_RESERVE_CU_8_DEFAULT 0x00000000
-#define mmSPI_RESOURCE_RESERVE_CU_9_DEFAULT 0x00000000
-#define mmSPI_RESOURCE_RESERVE_EN_CU_0_DEFAULT 0x00000000
-#define mmSPI_RESOURCE_RESERVE_EN_CU_1_DEFAULT 0x00000000
-#define mmSPI_RESOURCE_RESERVE_EN_CU_2_DEFAULT 0x00000000
-#define mmSPI_RESOURCE_RESERVE_EN_CU_3_DEFAULT 0x00000000
-#define mmSPI_RESOURCE_RESERVE_EN_CU_4_DEFAULT 0x00000000
-#define mmSPI_RESOURCE_RESERVE_EN_CU_5_DEFAULT 0x00000000
-#define mmSPI_RESOURCE_RESERVE_EN_CU_6_DEFAULT 0x00000000
-#define mmSPI_RESOURCE_RESERVE_EN_CU_7_DEFAULT 0x00000000
-#define mmSPI_RESOURCE_RESERVE_EN_CU_8_DEFAULT 0x00000000
-#define mmSPI_RESOURCE_RESERVE_EN_CU_9_DEFAULT 0x00000000
-#define mmSPI_RESOURCE_RESERVE_CU_10_DEFAULT 0x00000000
-#define mmSPI_RESOURCE_RESERVE_CU_11_DEFAULT 0x00000000
-#define mmSPI_RESOURCE_RESERVE_EN_CU_10_DEFAULT 0x00000000
-#define mmSPI_RESOURCE_RESERVE_EN_CU_11_DEFAULT 0x00000000
-#define mmSPI_RESOURCE_RESERVE_CU_12_DEFAULT 0x00000000
-#define mmSPI_RESOURCE_RESERVE_CU_13_DEFAULT 0x00000000
-#define mmSPI_RESOURCE_RESERVE_CU_14_DEFAULT 0x00000000
-#define mmSPI_RESOURCE_RESERVE_CU_15_DEFAULT 0x00000000
-#define mmSPI_RESOURCE_RESERVE_EN_CU_12_DEFAULT 0x00000000
-#define mmSPI_RESOURCE_RESERVE_EN_CU_13_DEFAULT 0x00000000
-#define mmSPI_RESOURCE_RESERVE_EN_CU_14_DEFAULT 0x00000000
-#define mmSPI_RESOURCE_RESERVE_EN_CU_15_DEFAULT 0x00000000
-#define mmSPI_COMPUTE_WF_CTX_SAVE_DEFAULT 0x00000000
-#define mmSPI_ARB_CNTL_0_DEFAULT 0x00000000
-
-
-// addressBlock: gc_cpphqddec
-#define mmCP_HQD_GFX_CONTROL_DEFAULT 0x00000000
-#define mmCP_HQD_GFX_STATUS_DEFAULT 0x00000000
-#define mmCP_HPD_ROQ_OFFSETS_DEFAULT 0x00200604
-#define mmCP_HPD_STATUS0_DEFAULT 0x01000000
-#define mmCP_HPD_UTCL1_CNTL_DEFAULT 0x00000000
-#define mmCP_HPD_UTCL1_ERROR_DEFAULT 0x00000000
-#define mmCP_HPD_UTCL1_ERROR_ADDR_DEFAULT 0x00000000
-#define mmCP_MQD_BASE_ADDR_DEFAULT 0x00000000
-#define mmCP_MQD_BASE_ADDR_HI_DEFAULT 0x00000000
-#define mmCP_HQD_ACTIVE_DEFAULT 0x00000000
-#define mmCP_HQD_VMID_DEFAULT 0x00000000
-#define mmCP_HQD_PERSISTENT_STATE_DEFAULT 0x0be05301
-#define mmCP_HQD_PIPE_PRIORITY_DEFAULT 0x00000000
-#define mmCP_HQD_QUEUE_PRIORITY_DEFAULT 0x00000000
-#define mmCP_HQD_QUANTUM_DEFAULT 0x00000000
-#define mmCP_HQD_PQ_BASE_DEFAULT 0x00000000
-#define mmCP_HQD_PQ_BASE_HI_DEFAULT 0x00000000
-#define mmCP_HQD_PQ_RPTR_DEFAULT 0x00000000
-#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_DEFAULT 0x00000000
-#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI_DEFAULT 0x00000000
-#define mmCP_HQD_PQ_WPTR_POLL_ADDR_DEFAULT 0x00000000
-#define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000
-#define mmCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000
-#define mmCP_HQD_PQ_CONTROL_DEFAULT 0x00308509
-#define mmCP_HQD_IB_BASE_ADDR_DEFAULT 0x00000000
-#define mmCP_HQD_IB_BASE_ADDR_HI_DEFAULT 0x00000000
-#define mmCP_HQD_IB_RPTR_DEFAULT 0x00000000
-#define mmCP_HQD_IB_CONTROL_DEFAULT 0x00300000
-#define mmCP_HQD_IQ_TIMER_DEFAULT 0x00000000
-#define mmCP_HQD_IQ_RPTR_DEFAULT 0x00000000
-#define mmCP_HQD_DEQUEUE_REQUEST_DEFAULT 0x00000000
-#define mmCP_HQD_DMA_OFFLOAD_DEFAULT 0x00000000
-#define mmCP_HQD_OFFLOAD_DEFAULT 0x00000000
-#define mmCP_HQD_SEMA_CMD_DEFAULT 0x00000000
-#define mmCP_HQD_MSG_TYPE_DEFAULT 0x00000000
-#define mmCP_HQD_ATOMIC0_PREOP_LO_DEFAULT 0x00000000
-#define mmCP_HQD_ATOMIC0_PREOP_HI_DEFAULT 0x00000000
-#define mmCP_HQD_ATOMIC1_PREOP_LO_DEFAULT 0x00000000
-#define mmCP_HQD_ATOMIC1_PREOP_HI_DEFAULT 0x00000000
-#define mmCP_HQD_HQ_SCHEDULER0_DEFAULT 0x00000000
-#define mmCP_HQD_HQ_STATUS0_DEFAULT 0x40000000
-#define mmCP_HQD_HQ_CONTROL0_DEFAULT 0x00000000
-#define mmCP_HQD_HQ_SCHEDULER1_DEFAULT 0x00000000
-#define mmCP_MQD_CONTROL_DEFAULT 0x00000100
-#define mmCP_HQD_HQ_STATUS1_DEFAULT 0x00000000
-#define mmCP_HQD_HQ_CONTROL1_DEFAULT 0x00000000
-#define mmCP_HQD_EOP_BASE_ADDR_DEFAULT 0x00000000
-#define mmCP_HQD_EOP_BASE_ADDR_HI_DEFAULT 0x00000000
-#define mmCP_HQD_EOP_CONTROL_DEFAULT 0x00000006
-#define mmCP_HQD_EOP_RPTR_DEFAULT 0x40000000
-#define mmCP_HQD_EOP_WPTR_DEFAULT 0x007f8000
-#define mmCP_HQD_EOP_EVENTS_DEFAULT 0x00000000
-#define mmCP_HQD_CTX_SAVE_BASE_ADDR_LO_DEFAULT 0x00000000
-#define mmCP_HQD_CTX_SAVE_BASE_ADDR_HI_DEFAULT 0x00000000
-#define mmCP_HQD_CTX_SAVE_CONTROL_DEFAULT 0x00000000
-#define mmCP_HQD_CNTL_STACK_OFFSET_DEFAULT 0x00000000
-#define mmCP_HQD_CNTL_STACK_SIZE_DEFAULT 0x00000000
-#define mmCP_HQD_WG_STATE_OFFSET_DEFAULT 0x00000000
-#define mmCP_HQD_CTX_SAVE_SIZE_DEFAULT 0x00000000
-#define mmCP_HQD_GDS_RESOURCE_STATE_DEFAULT 0x00000000
-#define mmCP_HQD_ERROR_DEFAULT 0x00000000
-#define mmCP_HQD_EOP_WPTR_MEM_DEFAULT 0x00000000
-#define mmCP_HQD_AQL_CONTROL_DEFAULT 0x00000000
-#define mmCP_HQD_PQ_WPTR_LO_DEFAULT 0x00000000
-#define mmCP_HQD_PQ_WPTR_HI_DEFAULT 0x00000000
-
-
-// addressBlock: gc_didtdec
-#define mmDIDT_IND_INDEX_DEFAULT 0x00000000
-#define mmDIDT_IND_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: gc_gccacdec
-#define mmGC_CAC_CTRL_1_DEFAULT 0x01000000
-#define mmGC_CAC_CTRL_2_DEFAULT 0x00000000
-#define mmGC_CAC_CGTT_CLK_CTRL_DEFAULT 0x00000100
-#define mmGC_CAC_AGGR_LOWER_DEFAULT 0x00000000
-#define mmGC_CAC_AGGR_UPPER_DEFAULT 0x00000000
-#define mmGC_CAC_PG_AGGR_LOWER_DEFAULT 0x00000000
-#define mmGC_CAC_PG_AGGR_UPPER_DEFAULT 0x00000000
-#define mmGC_CAC_SOFT_CTRL_DEFAULT 0x00000000
-#define mmGC_DIDT_CTRL0_DEFAULT 0x00000000
-#define mmGC_DIDT_CTRL1_DEFAULT 0xffff0000
-#define mmGC_DIDT_CTRL2_DEFAULT 0x1880000f
-#define mmGC_DIDT_WEIGHT_DEFAULT 0x00000000
-#define mmGC_EDC_CTRL_DEFAULT 0x00000000
-#define mmGC_EDC_THRESHOLD_DEFAULT 0x00000000
-#define mmGC_EDC_STATUS_DEFAULT 0x00000000
-#define mmGC_EDC_OVERFLOW_DEFAULT 0x00000000
-#define mmGC_EDC_ROLLING_POWER_DELTA_DEFAULT 0x00000000
-#define mmGC_DIDT_DROOP_CTRL_DEFAULT 0x00000000
-#define mmGC_EDC_DROOP_CTRL_DEFAULT 0x00100000
-#define mmGC_CAC_IND_INDEX_DEFAULT 0x00000000
-#define mmGC_CAC_IND_DATA_DEFAULT 0x00000000
-#define mmSE_CAC_CGTT_CLK_CTRL_DEFAULT 0x00000100
-#define mmSE_CAC_IND_INDEX_DEFAULT 0x00000000
-#define mmSE_CAC_IND_DATA_DEFAULT 0x00000000
-
-
-// addressBlock: gc_tcpdec
-#define mmTCP_WATCH0_ADDR_H_DEFAULT 0x00000000
-#define mmTCP_WATCH0_ADDR_L_DEFAULT 0x00000000
-#define mmTCP_WATCH0_CNTL_DEFAULT 0x00000000
-#define mmTCP_WATCH1_ADDR_H_DEFAULT 0x00000000
-#define mmTCP_WATCH1_ADDR_L_DEFAULT 0x00000000
-#define mmTCP_WATCH1_CNTL_DEFAULT 0x00000000
-#define mmTCP_WATCH2_ADDR_H_DEFAULT 0x00000000
-#define mmTCP_WATCH2_ADDR_L_DEFAULT 0x00000000
-#define mmTCP_WATCH2_CNTL_DEFAULT 0x00000000
-#define mmTCP_WATCH3_ADDR_H_DEFAULT 0x00000000
-#define mmTCP_WATCH3_ADDR_L_DEFAULT 0x00000000
-#define mmTCP_WATCH3_CNTL_DEFAULT 0x00000000
-#define mmTCP_GATCL1_CNTL_DEFAULT 0x00000000
-#define mmTCP_ATC_EDC_GATCL1_CNT_DEFAULT 0x00000000
-#define mmTCP_GATCL1_DSM_CNTL_DEFAULT 0x00000000
-#define mmTCP_CNTL2_DEFAULT 0x0000000a
-#define mmTCP_UTCL1_CNTL1_DEFAULT 0x00800400
-#define mmTCP_UTCL1_CNTL2_DEFAULT 0x00000000
-#define mmTCP_UTCL1_STATUS_DEFAULT 0x00000000
-#define mmTCP_PERFCOUNTER_FILTER_DEFAULT 0x00000000
-#define mmTCP_PERFCOUNTER_FILTER_EN_DEFAULT 0x00000000
-
-
-// addressBlock: gc_gdspdec
-#define mmGDS_VMID0_BASE_DEFAULT 0x00000000
-#define mmGDS_VMID0_SIZE_DEFAULT 0x00010000
-#define mmGDS_VMID1_BASE_DEFAULT 0x00000000
-#define mmGDS_VMID1_SIZE_DEFAULT 0x00010000
-#define mmGDS_VMID2_BASE_DEFAULT 0x00000000
-#define mmGDS_VMID2_SIZE_DEFAULT 0x00010000
-#define mmGDS_VMID3_BASE_DEFAULT 0x00000000
-#define mmGDS_VMID3_SIZE_DEFAULT 0x00010000
-#define mmGDS_VMID4_BASE_DEFAULT 0x00000000
-#define mmGDS_VMID4_SIZE_DEFAULT 0x00010000
-#define mmGDS_VMID5_BASE_DEFAULT 0x00000000
-#define mmGDS_VMID5_SIZE_DEFAULT 0x00010000
-#define mmGDS_VMID6_BASE_DEFAULT 0x00000000
-#define mmGDS_VMID6_SIZE_DEFAULT 0x00010000
-#define mmGDS_VMID7_BASE_DEFAULT 0x00000000
-#define mmGDS_VMID7_SIZE_DEFAULT 0x00010000
-#define mmGDS_VMID8_BASE_DEFAULT 0x00000000
-#define mmGDS_VMID8_SIZE_DEFAULT 0x00010000
-#define mmGDS_VMID9_BASE_DEFAULT 0x00000000
-#define mmGDS_VMID9_SIZE_DEFAULT 0x00010000
-#define mmGDS_VMID10_BASE_DEFAULT 0x00000000
-#define mmGDS_VMID10_SIZE_DEFAULT 0x00010000
-#define mmGDS_VMID11_BASE_DEFAULT 0x00000000
-#define mmGDS_VMID11_SIZE_DEFAULT 0x00010000
-#define mmGDS_VMID12_BASE_DEFAULT 0x00000000
-#define mmGDS_VMID12_SIZE_DEFAULT 0x00010000
-#define mmGDS_VMID13_BASE_DEFAULT 0x00000000
-#define mmGDS_VMID13_SIZE_DEFAULT 0x00010000
-#define mmGDS_VMID14_BASE_DEFAULT 0x00000000
-#define mmGDS_VMID14_SIZE_DEFAULT 0x00010000
-#define mmGDS_VMID15_BASE_DEFAULT 0x00000000
-#define mmGDS_VMID15_SIZE_DEFAULT 0x00010000
-#define mmGDS_GWS_VMID0_DEFAULT 0x00400000
-#define mmGDS_GWS_VMID1_DEFAULT 0x00400000
-#define mmGDS_GWS_VMID2_DEFAULT 0x00400000
-#define mmGDS_GWS_VMID3_DEFAULT 0x00400000
-#define mmGDS_GWS_VMID4_DEFAULT 0x00400000
-#define mmGDS_GWS_VMID5_DEFAULT 0x00400000
-#define mmGDS_GWS_VMID6_DEFAULT 0x00400000
-#define mmGDS_GWS_VMID7_DEFAULT 0x00400000
-#define mmGDS_GWS_VMID8_DEFAULT 0x00400000
-#define mmGDS_GWS_VMID9_DEFAULT 0x00400000
-#define mmGDS_GWS_VMID10_DEFAULT 0x00400000
-#define mmGDS_GWS_VMID11_DEFAULT 0x00400000
-#define mmGDS_GWS_VMID12_DEFAULT 0x00400000
-#define mmGDS_GWS_VMID13_DEFAULT 0x00400000
-#define mmGDS_GWS_VMID14_DEFAULT 0x00400000
-#define mmGDS_GWS_VMID15_DEFAULT 0x00400000
-#define mmGDS_OA_VMID0_DEFAULT 0x00000000
-#define mmGDS_OA_VMID1_DEFAULT 0x00000000
-#define mmGDS_OA_VMID2_DEFAULT 0x00000000
-#define mmGDS_OA_VMID3_DEFAULT 0x00000000
-#define mmGDS_OA_VMID4_DEFAULT 0x00000000
-#define mmGDS_OA_VMID5_DEFAULT 0x00000000
-#define mmGDS_OA_VMID6_DEFAULT 0x00000000
-#define mmGDS_OA_VMID7_DEFAULT 0x00000000
-#define mmGDS_OA_VMID8_DEFAULT 0x00000000
-#define mmGDS_OA_VMID9_DEFAULT 0x00000000
-#define mmGDS_OA_VMID10_DEFAULT 0x00000000
-#define mmGDS_OA_VMID11_DEFAULT 0x00000000
-#define mmGDS_OA_VMID12_DEFAULT 0x00000000
-#define mmGDS_OA_VMID13_DEFAULT 0x00000000
-#define mmGDS_OA_VMID14_DEFAULT 0x00000000
-#define mmGDS_OA_VMID15_DEFAULT 0x00000000
-#define mmGDS_GWS_RESET0_DEFAULT 0x00000000
-#define mmGDS_GWS_RESET1_DEFAULT 0x00000000
-#define mmGDS_GWS_RESOURCE_RESET_DEFAULT 0x00000000
-#define mmGDS_COMPUTE_MAX_WAVE_ID_DEFAULT 0x0000015f
-#define mmGDS_OA_RESET_MASK_DEFAULT 0x00000000
-#define mmGDS_OA_RESET_DEFAULT 0x00000000
-#define mmGDS_ENHANCE_DEFAULT 0x00000000
-#define mmGDS_OA_CGPG_RESTORE_DEFAULT 0x00000000
-#define mmGDS_CS_CTXSW_STATUS_DEFAULT 0x00000000
-#define mmGDS_CS_CTXSW_CNT0_DEFAULT 0x00000000
-#define mmGDS_CS_CTXSW_CNT1_DEFAULT 0x00000000
-#define mmGDS_CS_CTXSW_CNT2_DEFAULT 0x00000000
-#define mmGDS_CS_CTXSW_CNT3_DEFAULT 0x00000000
-#define mmGDS_GFX_CTXSW_STATUS_DEFAULT 0x00000000
-#define mmGDS_VS_CTXSW_CNT0_DEFAULT 0x00000000
-#define mmGDS_VS_CTXSW_CNT1_DEFAULT 0x00000000
-#define mmGDS_VS_CTXSW_CNT2_DEFAULT 0x00000000
-#define mmGDS_VS_CTXSW_CNT3_DEFAULT 0x00000000
-#define mmGDS_PS0_CTXSW_CNT0_DEFAULT 0x00000000
-#define mmGDS_PS0_CTXSW_CNT1_DEFAULT 0x00000000
-#define mmGDS_PS0_CTXSW_CNT2_DEFAULT 0x00000000
-#define mmGDS_PS0_CTXSW_CNT3_DEFAULT 0x00000000
-#define mmGDS_PS1_CTXSW_CNT0_DEFAULT 0x00000000
-#define mmGDS_PS1_CTXSW_CNT1_DEFAULT 0x00000000
-#define mmGDS_PS1_CTXSW_CNT2_DEFAULT 0x00000000
-#define mmGDS_PS1_CTXSW_CNT3_DEFAULT 0x00000000
-#define mmGDS_PS2_CTXSW_CNT0_DEFAULT 0x00000000
-#define mmGDS_PS2_CTXSW_CNT1_DEFAULT 0x00000000
-#define mmGDS_PS2_CTXSW_CNT2_DEFAULT 0x00000000
-#define mmGDS_PS2_CTXSW_CNT3_DEFAULT 0x00000000
-#define mmGDS_PS3_CTXSW_CNT0_DEFAULT 0x00000000
-#define mmGDS_PS3_CTXSW_CNT1_DEFAULT 0x00000000
-#define mmGDS_PS3_CTXSW_CNT2_DEFAULT 0x00000000
-#define mmGDS_PS3_CTXSW_CNT3_DEFAULT 0x00000000
-#define mmGDS_PS4_CTXSW_CNT0_DEFAULT 0x00000000
-#define mmGDS_PS4_CTXSW_CNT1_DEFAULT 0x00000000
-#define mmGDS_PS4_CTXSW_CNT2_DEFAULT 0x00000000
-#define mmGDS_PS4_CTXSW_CNT3_DEFAULT 0x00000000
-#define mmGDS_PS5_CTXSW_CNT0_DEFAULT 0x00000000
-#define mmGDS_PS5_CTXSW_CNT1_DEFAULT 0x00000000
-#define mmGDS_PS5_CTXSW_CNT2_DEFAULT 0x00000000
-#define mmGDS_PS5_CTXSW_CNT3_DEFAULT 0x00000000
-#define mmGDS_PS6_CTXSW_CNT0_DEFAULT 0x00000000
-#define mmGDS_PS6_CTXSW_CNT1_DEFAULT 0x00000000
-#define mmGDS_PS6_CTXSW_CNT2_DEFAULT 0x00000000
-#define mmGDS_PS6_CTXSW_CNT3_DEFAULT 0x00000000
-#define mmGDS_PS7_CTXSW_CNT0_DEFAULT 0x00000000
-#define mmGDS_PS7_CTXSW_CNT1_DEFAULT 0x00000000
-#define mmGDS_PS7_CTXSW_CNT2_DEFAULT 0x00000000
-#define mmGDS_PS7_CTXSW_CNT3_DEFAULT 0x00000000
-#define mmGDS_GS_CTXSW_CNT0_DEFAULT 0x00000000
-#define mmGDS_GS_CTXSW_CNT1_DEFAULT 0x00000000
-#define mmGDS_GS_CTXSW_CNT2_DEFAULT 0x00000000
-#define mmGDS_GS_CTXSW_CNT3_DEFAULT 0x00000000
-
-
-// addressBlock: gc_rasdec
-#define mmRAS_SIGNATURE_CONTROL_DEFAULT 0x00000000
-#define mmRAS_SIGNATURE_MASK_DEFAULT 0x00000000
-#define mmRAS_SX_SIGNATURE0_DEFAULT 0x00000000
-#define mmRAS_SX_SIGNATURE1_DEFAULT 0x00000000
-#define mmRAS_SX_SIGNATURE2_DEFAULT 0x00000000
-#define mmRAS_SX_SIGNATURE3_DEFAULT 0x00000000
-#define mmRAS_DB_SIGNATURE0_DEFAULT 0x00000000
-#define mmRAS_PA_SIGNATURE0_DEFAULT 0x00000000
-#define mmRAS_VGT_SIGNATURE0_DEFAULT 0x00000000
-#define mmRAS_SQ_SIGNATURE0_DEFAULT 0x00000000
-#define mmRAS_SC_SIGNATURE0_DEFAULT 0x00000000
-#define mmRAS_SC_SIGNATURE1_DEFAULT 0x00000000
-#define mmRAS_SC_SIGNATURE2_DEFAULT 0x00000000
-#define mmRAS_SC_SIGNATURE3_DEFAULT 0x00000000
-#define mmRAS_SC_SIGNATURE4_DEFAULT 0x00000000
-#define mmRAS_SC_SIGNATURE5_DEFAULT 0x00000000
-#define mmRAS_SC_SIGNATURE6_DEFAULT 0x00000000
-#define mmRAS_SC_SIGNATURE7_DEFAULT 0x00000000
-#define mmRAS_IA_SIGNATURE0_DEFAULT 0x00000000
-#define mmRAS_IA_SIGNATURE1_DEFAULT 0x00000000
-#define mmRAS_SPI_SIGNATURE0_DEFAULT 0x00000000
-#define mmRAS_SPI_SIGNATURE1_DEFAULT 0x00000000
-#define mmRAS_TA_SIGNATURE0_DEFAULT 0x00000000
-#define mmRAS_TD_SIGNATURE0_DEFAULT 0x00000000
-#define mmRAS_CB_SIGNATURE0_DEFAULT 0x00000000
-#define mmRAS_BCI_SIGNATURE0_DEFAULT 0x00000000
-#define mmRAS_BCI_SIGNATURE1_DEFAULT 0x00000000
-#define mmRAS_TA_SIGNATURE1_DEFAULT 0x00000000
-
-
-// addressBlock: gc_gfxdec0
-#define mmDB_RENDER_CONTROL_DEFAULT 0x00000000
-#define mmDB_COUNT_CONTROL_DEFAULT 0x00000000
-#define mmDB_DEPTH_VIEW_DEFAULT 0x00000000
-#define mmDB_RENDER_OVERRIDE_DEFAULT 0x00000000
-#define mmDB_RENDER_OVERRIDE2_DEFAULT 0x00000000
-#define mmDB_HTILE_DATA_BASE_DEFAULT 0x00000000
-#define mmDB_HTILE_DATA_BASE_HI_DEFAULT 0x00000000
-#define mmDB_DEPTH_SIZE_DEFAULT 0x00000000
-#define mmDB_DEPTH_BOUNDS_MIN_DEFAULT 0x00000000
-#define mmDB_DEPTH_BOUNDS_MAX_DEFAULT 0x00000000
-#define mmDB_STENCIL_CLEAR_DEFAULT 0x00000000
-#define mmDB_DEPTH_CLEAR_DEFAULT 0x00000000
-#define mmPA_SC_SCREEN_SCISSOR_TL_DEFAULT 0x00000000
-#define mmPA_SC_SCREEN_SCISSOR_BR_DEFAULT 0x00000000
-#define mmDB_Z_INFO_DEFAULT 0x00000000
-#define mmDB_STENCIL_INFO_DEFAULT 0x00000000
-#define mmDB_Z_READ_BASE_DEFAULT 0x00000000
-#define mmDB_Z_READ_BASE_HI_DEFAULT 0x00000000
-#define mmDB_STENCIL_READ_BASE_DEFAULT 0x00000000
-#define mmDB_STENCIL_READ_BASE_HI_DEFAULT 0x00000000
-#define mmDB_Z_WRITE_BASE_DEFAULT 0x00000000
-#define mmDB_Z_WRITE_BASE_HI_DEFAULT 0x00000000
-#define mmDB_STENCIL_WRITE_BASE_DEFAULT 0x00000000
-#define mmDB_STENCIL_WRITE_BASE_HI_DEFAULT 0x00000000
-#define mmDB_DFSM_CONTROL_DEFAULT 0x00000000
-#define mmDB_RENDER_FILTER_DEFAULT 0x00000000
-#define mmDB_Z_INFO2_DEFAULT 0x00000000
-#define mmDB_STENCIL_INFO2_DEFAULT 0x00000000
-#define mmTA_BC_BASE_ADDR_DEFAULT 0x00000000
-#define mmTA_BC_BASE_ADDR_HI_DEFAULT 0x00000000
-#define mmCOHER_DEST_BASE_HI_0_DEFAULT 0x00000000
-#define mmCOHER_DEST_BASE_HI_1_DEFAULT 0x00000000
-#define mmCOHER_DEST_BASE_HI_2_DEFAULT 0x00000000
-#define mmCOHER_DEST_BASE_HI_3_DEFAULT 0x00000000
-#define mmCOHER_DEST_BASE_2_DEFAULT 0x00000000
-#define mmCOHER_DEST_BASE_3_DEFAULT 0x00000000
-#define mmPA_SC_WINDOW_OFFSET_DEFAULT 0x00000000
-#define mmPA_SC_WINDOW_SCISSOR_TL_DEFAULT 0x00000000
-#define mmPA_SC_WINDOW_SCISSOR_BR_DEFAULT 0x00000000
-#define mmPA_SC_CLIPRECT_RULE_DEFAULT 0x00000000
-#define mmPA_SC_CLIPRECT_0_TL_DEFAULT 0x00000000
-#define mmPA_SC_CLIPRECT_0_BR_DEFAULT 0x00000000
-#define mmPA_SC_CLIPRECT_1_TL_DEFAULT 0x00000000
-#define mmPA_SC_CLIPRECT_1_BR_DEFAULT 0x00000000
-#define mmPA_SC_CLIPRECT_2_TL_DEFAULT 0x00000000
-#define mmPA_SC_CLIPRECT_2_BR_DEFAULT 0x00000000
-#define mmPA_SC_CLIPRECT_3_TL_DEFAULT 0x00000000
-#define mmPA_SC_CLIPRECT_3_BR_DEFAULT 0x00000000
-#define mmPA_SC_EDGERULE_DEFAULT 0x00000000
-#define mmPA_SU_HARDWARE_SCREEN_OFFSET_DEFAULT 0x00000000
-#define mmCB_TARGET_MASK_DEFAULT 0x00000000
-#define mmCB_SHADER_MASK_DEFAULT 0x00000000
-#define mmPA_SC_GENERIC_SCISSOR_TL_DEFAULT 0x00000000
-#define mmPA_SC_GENERIC_SCISSOR_BR_DEFAULT 0x00000000
-#define mmCOHER_DEST_BASE_0_DEFAULT 0x00000000
-#define mmCOHER_DEST_BASE_1_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_SCISSOR_0_TL_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_SCISSOR_0_BR_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_SCISSOR_1_TL_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_SCISSOR_1_BR_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_SCISSOR_2_TL_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_SCISSOR_2_BR_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_SCISSOR_3_TL_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_SCISSOR_3_BR_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_SCISSOR_4_TL_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_SCISSOR_4_BR_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_SCISSOR_5_TL_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_SCISSOR_5_BR_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_SCISSOR_6_TL_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_SCISSOR_6_BR_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_SCISSOR_7_TL_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_SCISSOR_7_BR_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_SCISSOR_8_TL_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_SCISSOR_8_BR_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_SCISSOR_9_TL_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_SCISSOR_9_BR_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_SCISSOR_10_TL_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_SCISSOR_10_BR_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_SCISSOR_11_TL_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_SCISSOR_11_BR_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_SCISSOR_12_TL_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_SCISSOR_12_BR_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_SCISSOR_13_TL_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_SCISSOR_13_BR_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_SCISSOR_14_TL_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_SCISSOR_14_BR_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_SCISSOR_15_TL_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_SCISSOR_15_BR_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_ZMIN_0_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_ZMAX_0_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_ZMIN_1_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_ZMAX_1_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_ZMIN_2_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_ZMAX_2_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_ZMIN_3_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_ZMAX_3_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_ZMIN_4_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_ZMAX_4_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_ZMIN_5_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_ZMAX_5_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_ZMIN_6_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_ZMAX_6_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_ZMIN_7_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_ZMAX_7_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_ZMIN_8_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_ZMAX_8_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_ZMIN_9_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_ZMAX_9_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_ZMIN_10_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_ZMAX_10_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_ZMIN_11_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_ZMAX_11_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_ZMIN_12_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_ZMAX_12_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_ZMIN_13_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_ZMAX_13_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_ZMIN_14_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_ZMAX_14_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_ZMIN_15_DEFAULT 0x00000000
-#define mmPA_SC_VPORT_ZMAX_15_DEFAULT 0x00000000
-#define mmPA_SC_RASTER_CONFIG_DEFAULT 0x00000000
-#define mmPA_SC_RASTER_CONFIG_1_DEFAULT 0x00000000
-#define mmPA_SC_SCREEN_EXTENT_CONTROL_DEFAULT 0x00000000
-#define mmPA_SC_TILE_STEERING_OVERRIDE_DEFAULT 0x00000000
-#define mmCP_PERFMON_CNTX_CNTL_DEFAULT 0x00000000
-#define mmCP_PIPEID_DEFAULT 0x00000000
-#define mmCP_RINGID_DEFAULT 0x00000000
-#define mmCP_VMID_DEFAULT 0x00000000
-#define mmPA_SC_RIGHT_VERT_GRID_DEFAULT 0x00000000
-#define mmPA_SC_LEFT_VERT_GRID_DEFAULT 0x00000000
-#define mmPA_SC_HORIZ_GRID_DEFAULT 0x00000000
-#define mmPA_SC_FOV_WINDOW_LR_DEFAULT 0x00000000
-#define mmPA_SC_FOV_WINDOW_TB_DEFAULT 0x00000000
-#define mmVGT_MULTI_PRIM_IB_RESET_INDX_DEFAULT 0x00000000
-#define mmCB_BLEND_RED_DEFAULT 0x00000000
-#define mmCB_BLEND_GREEN_DEFAULT 0x00000000
-#define mmCB_BLEND_BLUE_DEFAULT 0x00000000
-#define mmCB_BLEND_ALPHA_DEFAULT 0x00000000
-#define mmCB_DCC_CONTROL_DEFAULT 0x00000000
-#define mmDB_STENCIL_CONTROL_DEFAULT 0x00000000
-#define mmDB_STENCILREFMASK_DEFAULT 0x00000000
-#define mmDB_STENCILREFMASK_BF_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_XSCALE_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_XOFFSET_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_YSCALE_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_YOFFSET_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_ZSCALE_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_ZOFFSET_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_XSCALE_1_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_XOFFSET_1_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_YSCALE_1_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_YOFFSET_1_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_ZSCALE_1_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_ZOFFSET_1_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_XSCALE_2_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_XOFFSET_2_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_YSCALE_2_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_YOFFSET_2_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_ZSCALE_2_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_ZOFFSET_2_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_XSCALE_3_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_XOFFSET_3_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_YSCALE_3_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_YOFFSET_3_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_ZSCALE_3_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_ZOFFSET_3_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_XSCALE_4_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_XOFFSET_4_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_YSCALE_4_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_YOFFSET_4_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_ZSCALE_4_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_ZOFFSET_4_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_XSCALE_5_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_XOFFSET_5_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_YSCALE_5_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_YOFFSET_5_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_ZSCALE_5_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_ZOFFSET_5_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_XSCALE_6_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_XOFFSET_6_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_YSCALE_6_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_YOFFSET_6_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_ZSCALE_6_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_ZOFFSET_6_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_XSCALE_7_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_XOFFSET_7_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_YSCALE_7_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_YOFFSET_7_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_ZSCALE_7_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_ZOFFSET_7_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_XSCALE_8_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_XOFFSET_8_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_YSCALE_8_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_YOFFSET_8_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_ZSCALE_8_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_ZOFFSET_8_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_XSCALE_9_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_XOFFSET_9_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_YSCALE_9_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_YOFFSET_9_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_ZSCALE_9_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_ZOFFSET_9_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_XSCALE_10_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_XOFFSET_10_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_YSCALE_10_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_YOFFSET_10_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_ZSCALE_10_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_ZOFFSET_10_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_XSCALE_11_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_XOFFSET_11_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_YSCALE_11_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_YOFFSET_11_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_ZSCALE_11_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_ZOFFSET_11_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_XSCALE_12_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_XOFFSET_12_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_YSCALE_12_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_YOFFSET_12_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_ZSCALE_12_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_ZOFFSET_12_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_XSCALE_13_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_XOFFSET_13_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_YSCALE_13_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_YOFFSET_13_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_ZSCALE_13_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_ZOFFSET_13_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_XSCALE_14_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_XOFFSET_14_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_YSCALE_14_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_YOFFSET_14_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_ZSCALE_14_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_ZOFFSET_14_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_XSCALE_15_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_XOFFSET_15_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_YSCALE_15_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_YOFFSET_15_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_ZSCALE_15_DEFAULT 0x00000000
-#define mmPA_CL_VPORT_ZOFFSET_15_DEFAULT 0x00000000
-#define mmPA_CL_UCP_0_X_DEFAULT 0x00000000
-#define mmPA_CL_UCP_0_Y_DEFAULT 0x00000000
-#define mmPA_CL_UCP_0_Z_DEFAULT 0x00000000
-#define mmPA_CL_UCP_0_W_DEFAULT 0x00000000
-#define mmPA_CL_UCP_1_X_DEFAULT 0x00000000
-#define mmPA_CL_UCP_1_Y_DEFAULT 0x00000000
-#define mmPA_CL_UCP_1_Z_DEFAULT 0x00000000
-#define mmPA_CL_UCP_1_W_DEFAULT 0x00000000
-#define mmPA_CL_UCP_2_X_DEFAULT 0x00000000
-#define mmPA_CL_UCP_2_Y_DEFAULT 0x00000000
-#define mmPA_CL_UCP_2_Z_DEFAULT 0x00000000
-#define mmPA_CL_UCP_2_W_DEFAULT 0x00000000
-#define mmPA_CL_UCP_3_X_DEFAULT 0x00000000
-#define mmPA_CL_UCP_3_Y_DEFAULT 0x00000000
-#define mmPA_CL_UCP_3_Z_DEFAULT 0x00000000
-#define mmPA_CL_UCP_3_W_DEFAULT 0x00000000
-#define mmPA_CL_UCP_4_X_DEFAULT 0x00000000
-#define mmPA_CL_UCP_4_Y_DEFAULT 0x00000000
-#define mmPA_CL_UCP_4_Z_DEFAULT 0x00000000
-#define mmPA_CL_UCP_4_W_DEFAULT 0x00000000
-#define mmPA_CL_UCP_5_X_DEFAULT 0x00000000
-#define mmPA_CL_UCP_5_Y_DEFAULT 0x00000000
-#define mmPA_CL_UCP_5_Z_DEFAULT 0x00000000
-#define mmPA_CL_UCP_5_W_DEFAULT 0x00000000
-#define mmSPI_PS_INPUT_CNTL_0_DEFAULT 0x00000000
-#define mmSPI_PS_INPUT_CNTL_1_DEFAULT 0x00000000
-#define mmSPI_PS_INPUT_CNTL_2_DEFAULT 0x00000000
-#define mmSPI_PS_INPUT_CNTL_3_DEFAULT 0x00000000
-#define mmSPI_PS_INPUT_CNTL_4_DEFAULT 0x00000000
-#define mmSPI_PS_INPUT_CNTL_5_DEFAULT 0x00000000
-#define mmSPI_PS_INPUT_CNTL_6_DEFAULT 0x00000000
-#define mmSPI_PS_INPUT_CNTL_7_DEFAULT 0x00000000
-#define mmSPI_PS_INPUT_CNTL_8_DEFAULT 0x00000000
-#define mmSPI_PS_INPUT_CNTL_9_DEFAULT 0x00000000
-#define mmSPI_PS_INPUT_CNTL_10_DEFAULT 0x00000000
-#define mmSPI_PS_INPUT_CNTL_11_DEFAULT 0x00000000
-#define mmSPI_PS_INPUT_CNTL_12_DEFAULT 0x00000000
-#define mmSPI_PS_INPUT_CNTL_13_DEFAULT 0x00000000
-#define mmSPI_PS_INPUT_CNTL_14_DEFAULT 0x00000000
-#define mmSPI_PS_INPUT_CNTL_15_DEFAULT 0x00000000
-#define mmSPI_PS_INPUT_CNTL_16_DEFAULT 0x00000000
-#define mmSPI_PS_INPUT_CNTL_17_DEFAULT 0x00000000
-#define mmSPI_PS_INPUT_CNTL_18_DEFAULT 0x00000000
-#define mmSPI_PS_INPUT_CNTL_19_DEFAULT 0x00000000
-#define mmSPI_PS_INPUT_CNTL_20_DEFAULT 0x00000000
-#define mmSPI_PS_INPUT_CNTL_21_DEFAULT 0x00000000
-#define mmSPI_PS_INPUT_CNTL_22_DEFAULT 0x00000000
-#define mmSPI_PS_INPUT_CNTL_23_DEFAULT 0x00000000
-#define mmSPI_PS_INPUT_CNTL_24_DEFAULT 0x00000000
-#define mmSPI_PS_INPUT_CNTL_25_DEFAULT 0x00000000
-#define mmSPI_PS_INPUT_CNTL_26_DEFAULT 0x00000000
-#define mmSPI_PS_INPUT_CNTL_27_DEFAULT 0x00000000
-#define mmSPI_PS_INPUT_CNTL_28_DEFAULT 0x00000000
-#define mmSPI_PS_INPUT_CNTL_29_DEFAULT 0x00000000
-#define mmSPI_PS_INPUT_CNTL_30_DEFAULT 0x00000000
-#define mmSPI_PS_INPUT_CNTL_31_DEFAULT 0x00000000
-#define mmSPI_VS_OUT_CONFIG_DEFAULT 0x00000000
-#define mmSPI_PS_INPUT_ENA_DEFAULT 0x00000000
-#define mmSPI_PS_INPUT_ADDR_DEFAULT 0x00000000
-#define mmSPI_INTERP_CONTROL_0_DEFAULT 0x00000000
-#define mmSPI_PS_IN_CONTROL_DEFAULT 0x00000000
-#define mmSPI_BARYC_CNTL_DEFAULT 0x00000000
-#define mmSPI_TMPRING_SIZE_DEFAULT 0x00000000
-#define mmSPI_SHADER_POS_FORMAT_DEFAULT 0x00000000
-#define mmSPI_SHADER_Z_FORMAT_DEFAULT 0x00000000
-#define mmSPI_SHADER_COL_FORMAT_DEFAULT 0x00000000
-#define mmSX_PS_DOWNCONVERT_DEFAULT 0x00000000
-#define mmSX_BLEND_OPT_EPSILON_DEFAULT 0x00000000
-#define mmSX_BLEND_OPT_CONTROL_DEFAULT 0x00000000
-#define mmSX_MRT0_BLEND_OPT_DEFAULT 0x00000000
-#define mmSX_MRT1_BLEND_OPT_DEFAULT 0x00000000
-#define mmSX_MRT2_BLEND_OPT_DEFAULT 0x00000000
-#define mmSX_MRT3_BLEND_OPT_DEFAULT 0x00000000
-#define mmSX_MRT4_BLEND_OPT_DEFAULT 0x00000000
-#define mmSX_MRT5_BLEND_OPT_DEFAULT 0x00000000
-#define mmSX_MRT6_BLEND_OPT_DEFAULT 0x00000000
-#define mmSX_MRT7_BLEND_OPT_DEFAULT 0x00000000
-#define mmCB_BLEND0_CONTROL_DEFAULT 0x00000000
-#define mmCB_BLEND1_CONTROL_DEFAULT 0x00000000
-#define mmCB_BLEND2_CONTROL_DEFAULT 0x00000000
-#define mmCB_BLEND3_CONTROL_DEFAULT 0x00000000
-#define mmCB_BLEND4_CONTROL_DEFAULT 0x00000000
-#define mmCB_BLEND5_CONTROL_DEFAULT 0x00000000
-#define mmCB_BLEND6_CONTROL_DEFAULT 0x00000000
-#define mmCB_BLEND7_CONTROL_DEFAULT 0x00000000
-#define mmCB_MRT0_EPITCH_DEFAULT 0x00000000
-#define mmCB_MRT1_EPITCH_DEFAULT 0x00000000
-#define mmCB_MRT2_EPITCH_DEFAULT 0x00000000
-#define mmCB_MRT3_EPITCH_DEFAULT 0x00000000
-#define mmCB_MRT4_EPITCH_DEFAULT 0x00000000
-#define mmCB_MRT5_EPITCH_DEFAULT 0x00000000
-#define mmCB_MRT6_EPITCH_DEFAULT 0x00000000
-#define mmCB_MRT7_EPITCH_DEFAULT 0x00000000
-#define mmCS_COPY_STATE_DEFAULT 0x00000000
-#define mmGFX_COPY_STATE_DEFAULT 0x00000000
-#define mmPA_CL_POINT_X_RAD_DEFAULT 0x00000000
-#define mmPA_CL_POINT_Y_RAD_DEFAULT 0x00000000
-#define mmPA_CL_POINT_SIZE_DEFAULT 0x00000000
-#define mmPA_CL_POINT_CULL_RAD_DEFAULT 0x00000000
-#define mmVGT_DMA_BASE_HI_DEFAULT 0x00000000
-#define mmVGT_DMA_BASE_DEFAULT 0x00000000
-#define mmVGT_DRAW_INITIATOR_DEFAULT 0x00000000
-#define mmVGT_IMMED_DATA_DEFAULT 0x00000000
-#define mmVGT_EVENT_ADDRESS_REG_DEFAULT 0x00000000
-#define mmDB_DEPTH_CONTROL_DEFAULT 0x00000000
-#define mmDB_EQAA_DEFAULT 0x00000000
-#define mmCB_COLOR_CONTROL_DEFAULT 0x00000000
-#define mmDB_SHADER_CONTROL_DEFAULT 0x00000000
-#define mmPA_CL_CLIP_CNTL_DEFAULT 0x00000000
-#define mmPA_SU_SC_MODE_CNTL_DEFAULT 0x00000000
-#define mmPA_CL_VTE_CNTL_DEFAULT 0x00000000
-#define mmPA_CL_VS_OUT_CNTL_DEFAULT 0x00000000
-#define mmPA_CL_NANINF_CNTL_DEFAULT 0x00000000
-#define mmPA_SU_LINE_STIPPLE_CNTL_DEFAULT 0x00000000
-#define mmPA_SU_LINE_STIPPLE_SCALE_DEFAULT 0x00000000
-#define mmPA_SU_PRIM_FILTER_CNTL_DEFAULT 0x00000000
-#define mmPA_SU_SMALL_PRIM_FILTER_CNTL_DEFAULT 0x00000000
-#define mmPA_CL_OBJPRIM_ID_CNTL_DEFAULT 0x00000000
-#define mmPA_CL_NGG_CNTL_DEFAULT 0x00000000
-#define mmPA_SU_OVER_RASTERIZATION_CNTL_DEFAULT 0x00000000
-#define mmPA_SU_POINT_SIZE_DEFAULT 0x00000000
-#define mmPA_SU_POINT_MINMAX_DEFAULT 0x00000000
-#define mmPA_SU_LINE_CNTL_DEFAULT 0x00000000
-#define mmPA_SC_LINE_STIPPLE_DEFAULT 0x00000000
-#define mmVGT_OUTPUT_PATH_CNTL_DEFAULT 0x00000000
-#define mmVGT_HOS_CNTL_DEFAULT 0x00000000
-#define mmVGT_HOS_MAX_TESS_LEVEL_DEFAULT 0x00000000
-#define mmVGT_HOS_MIN_TESS_LEVEL_DEFAULT 0x00000000
-#define mmVGT_HOS_REUSE_DEPTH_DEFAULT 0x00000000
-#define mmVGT_GROUP_PRIM_TYPE_DEFAULT 0x00000000
-#define mmVGT_GROUP_FIRST_DECR_DEFAULT 0x00000000
-#define mmVGT_GROUP_DECR_DEFAULT 0x00000000
-#define mmVGT_GROUP_VECT_0_CNTL_DEFAULT 0x00000000
-#define mmVGT_GROUP_VECT_1_CNTL_DEFAULT 0x00000000
-#define mmVGT_GROUP_VECT_0_FMT_CNTL_DEFAULT 0x00000000
-#define mmVGT_GROUP_VECT_1_FMT_CNTL_DEFAULT 0x00000000
-#define mmVGT_GS_MODE_DEFAULT 0x00000000
-#define mmVGT_GS_ONCHIP_CNTL_DEFAULT 0x00000000
-#define mmPA_SC_MODE_CNTL_0_DEFAULT 0x00000000
-#define mmPA_SC_MODE_CNTL_1_DEFAULT 0x06000000
-#define mmVGT_ENHANCE_DEFAULT 0x00000000
-#define mmVGT_GS_PER_ES_DEFAULT 0x00000000
-#define mmVGT_ES_PER_GS_DEFAULT 0x00000000
-#define mmVGT_GS_PER_VS_DEFAULT 0x00000000
-#define mmVGT_GSVS_RING_OFFSET_1_DEFAULT 0x00000000
-#define mmVGT_GSVS_RING_OFFSET_2_DEFAULT 0x00000000
-#define mmVGT_GSVS_RING_OFFSET_3_DEFAULT 0x00000000
-#define mmVGT_GS_OUT_PRIM_TYPE_DEFAULT 0x00000000
-#define mmIA_ENHANCE_DEFAULT 0x00000000
-#define mmVGT_DMA_SIZE_DEFAULT 0x00000000
-#define mmVGT_DMA_MAX_SIZE_DEFAULT 0x00000000
-#define mmVGT_DMA_INDEX_TYPE_DEFAULT 0x00000000
-#define mmWD_ENHANCE_DEFAULT 0x00000000
-#define mmVGT_PRIMITIVEID_EN_DEFAULT 0x00000000
-#define mmVGT_DMA_NUM_INSTANCES_DEFAULT 0x00000000
-#define mmVGT_PRIMITIVEID_RESET_DEFAULT 0x00000000
-#define mmVGT_EVENT_INITIATOR_DEFAULT 0x00000000
-#define mmVGT_GS_MAX_PRIMS_PER_SUBGROUP_DEFAULT 0x00000000
-#define mmVGT_DRAW_PAYLOAD_CNTL_DEFAULT 0x00000000
-#define mmVGT_INDEX_PAYLOAD_CNTL_DEFAULT 0x00000000
-#define mmVGT_INSTANCE_STEP_RATE_0_DEFAULT 0x00000000
-#define mmVGT_INSTANCE_STEP_RATE_1_DEFAULT 0x00000000
-#define mmVGT_ESGS_RING_ITEMSIZE_DEFAULT 0x00000000
-#define mmVGT_GSVS_RING_ITEMSIZE_DEFAULT 0x00000000
-#define mmVGT_REUSE_OFF_DEFAULT 0x00000000
-#define mmVGT_VTX_CNT_EN_DEFAULT 0x00000000
-#define mmDB_HTILE_SURFACE_DEFAULT 0x00000000
-#define mmDB_SRESULTS_COMPARE_STATE0_DEFAULT 0x00000000
-#define mmDB_SRESULTS_COMPARE_STATE1_DEFAULT 0x00000000
-#define mmDB_PRELOAD_CONTROL_DEFAULT 0x00000000
-#define mmVGT_STRMOUT_BUFFER_SIZE_0_DEFAULT 0x00000000
-#define mmVGT_STRMOUT_VTX_STRIDE_0_DEFAULT 0x00000000
-#define mmVGT_STRMOUT_BUFFER_OFFSET_0_DEFAULT 0x00000000
-#define mmVGT_STRMOUT_BUFFER_SIZE_1_DEFAULT 0x00000000
-#define mmVGT_STRMOUT_VTX_STRIDE_1_DEFAULT 0x00000000
-#define mmVGT_STRMOUT_BUFFER_OFFSET_1_DEFAULT 0x00000000
-#define mmVGT_STRMOUT_BUFFER_SIZE_2_DEFAULT 0x00000000
-#define mmVGT_STRMOUT_VTX_STRIDE_2_DEFAULT 0x00000000
-#define mmVGT_STRMOUT_BUFFER_OFFSET_2_DEFAULT 0x00000000
-#define mmVGT_STRMOUT_BUFFER_SIZE_3_DEFAULT 0x00000000
-#define mmVGT_STRMOUT_VTX_STRIDE_3_DEFAULT 0x00000000
-#define mmVGT_STRMOUT_BUFFER_OFFSET_3_DEFAULT 0x00000000
-#define mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET_DEFAULT 0x00000000
-#define mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE_DEFAULT 0x00000000
-#define mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE_DEFAULT 0x00000000
-#define mmVGT_GS_MAX_VERT_OUT_DEFAULT 0x00000000
-#define mmVGT_TESS_DISTRIBUTION_DEFAULT 0x00000000
-#define mmVGT_SHADER_STAGES_EN_DEFAULT 0x00000000
-#define mmVGT_LS_HS_CONFIG_DEFAULT 0x00000000
-#define mmVGT_GS_VERT_ITEMSIZE_DEFAULT 0x00000000
-#define mmVGT_GS_VERT_ITEMSIZE_1_DEFAULT 0x00000000
-#define mmVGT_GS_VERT_ITEMSIZE_2_DEFAULT 0x00000000
-#define mmVGT_GS_VERT_ITEMSIZE_3_DEFAULT 0x00000000
-#define mmVGT_TF_PARAM_DEFAULT 0x00000000
-#define mmDB_ALPHA_TO_MASK_DEFAULT 0x00000000
-#define mmVGT_DISPATCH_DRAW_INDEX_DEFAULT 0x00000000
-#define mmPA_SU_POLY_OFFSET_DB_FMT_CNTL_DEFAULT 0x00000000
-#define mmPA_SU_POLY_OFFSET_CLAMP_DEFAULT 0x00000000
-#define mmPA_SU_POLY_OFFSET_FRONT_SCALE_DEFAULT 0x00000000
-#define mmPA_SU_POLY_OFFSET_FRONT_OFFSET_DEFAULT 0x00000000
-#define mmPA_SU_POLY_OFFSET_BACK_SCALE_DEFAULT 0x00000000
-#define mmPA_SU_POLY_OFFSET_BACK_OFFSET_DEFAULT 0x00000000
-#define mmVGT_GS_INSTANCE_CNT_DEFAULT 0x00000000
-#define mmVGT_STRMOUT_CONFIG_DEFAULT 0x00000000
-#define mmVGT_STRMOUT_BUFFER_CONFIG_DEFAULT 0x00000000
-#define mmVGT_DMA_EVENT_INITIATOR_DEFAULT 0x00000000
-#define mmPA_SC_CENTROID_PRIORITY_0_DEFAULT 0x00000000
-#define mmPA_SC_CENTROID_PRIORITY_1_DEFAULT 0x00000000
-#define mmPA_SC_LINE_CNTL_DEFAULT 0x00000000
-#define mmPA_SC_AA_CONFIG_DEFAULT 0x00000000
-#define mmPA_SU_VTX_CNTL_DEFAULT 0x00000000
-#define mmPA_CL_GB_VERT_CLIP_ADJ_DEFAULT 0x00000000
-#define mmPA_CL_GB_VERT_DISC_ADJ_DEFAULT 0x00000000
-#define mmPA_CL_GB_HORZ_CLIP_ADJ_DEFAULT 0x00000000
-#define mmPA_CL_GB_HORZ_DISC_ADJ_DEFAULT 0x00000000
-#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0_DEFAULT 0x00000000
-#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1_DEFAULT 0x00000000
-#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2_DEFAULT 0x00000000
-#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3_DEFAULT 0x00000000
-#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0_DEFAULT 0x00000000
-#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1_DEFAULT 0x00000000
-#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2_DEFAULT 0x00000000
-#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3_DEFAULT 0x00000000
-#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0_DEFAULT 0x00000000
-#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1_DEFAULT 0x00000000
-#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2_DEFAULT 0x00000000
-#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3_DEFAULT 0x00000000
-#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0_DEFAULT 0x00000000
-#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1_DEFAULT 0x00000000
-#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2_DEFAULT 0x00000000
-#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3_DEFAULT 0x00000000
-#define mmPA_SC_AA_MASK_X0Y0_X1Y0_DEFAULT 0x00000000
-#define mmPA_SC_AA_MASK_X0Y1_X1Y1_DEFAULT 0x00000000
-#define mmPA_SC_SHADER_CONTROL_DEFAULT 0x00000000
-#define mmPA_SC_BINNER_CNTL_0_DEFAULT 0x00000000
-#define mmPA_SC_BINNER_CNTL_1_DEFAULT 0x00000000
-#define mmPA_SC_CONSERVATIVE_RASTERIZATION_CNTL_DEFAULT 0x00000000
-#define mmPA_SC_NGG_MODE_CNTL_DEFAULT 0x00000000
-#define mmVGT_VERTEX_REUSE_BLOCK_CNTL_DEFAULT 0x00000000
-#define mmVGT_OUT_DEALLOC_CNTL_DEFAULT 0x00000000
-#define mmCB_COLOR0_BASE_DEFAULT 0x00000000
-#define mmCB_COLOR0_BASE_EXT_DEFAULT 0x00000000
-#define mmCB_COLOR0_ATTRIB2_DEFAULT 0x00000000
-#define mmCB_COLOR0_VIEW_DEFAULT 0x00000000
-#define mmCB_COLOR0_INFO_DEFAULT 0x00000000
-#define mmCB_COLOR0_ATTRIB_DEFAULT 0x00000000
-#define mmCB_COLOR0_DCC_CONTROL_DEFAULT 0x00000000
-#define mmCB_COLOR0_CMASK_DEFAULT 0x00000000
-#define mmCB_COLOR0_CMASK_BASE_EXT_DEFAULT 0x00000000
-#define mmCB_COLOR0_FMASK_DEFAULT 0x00000000
-#define mmCB_COLOR0_FMASK_BASE_EXT_DEFAULT 0x00000000
-#define mmCB_COLOR0_CLEAR_WORD0_DEFAULT 0x00000000
-#define mmCB_COLOR0_CLEAR_WORD1_DEFAULT 0x00000000
-#define mmCB_COLOR0_DCC_BASE_DEFAULT 0x00000000
-#define mmCB_COLOR0_DCC_BASE_EXT_DEFAULT 0x00000000
-#define mmCB_COLOR1_BASE_DEFAULT 0x00000000
-#define mmCB_COLOR1_BASE_EXT_DEFAULT 0x00000000
-#define mmCB_COLOR1_ATTRIB2_DEFAULT 0x00000000
-#define mmCB_COLOR1_VIEW_DEFAULT 0x00000000
-#define mmCB_COLOR1_INFO_DEFAULT 0x00000000
-#define mmCB_COLOR1_ATTRIB_DEFAULT 0x00000000
-#define mmCB_COLOR1_DCC_CONTROL_DEFAULT 0x00000000
-#define mmCB_COLOR1_CMASK_DEFAULT 0x00000000
-#define mmCB_COLOR1_CMASK_BASE_EXT_DEFAULT 0x00000000
-#define mmCB_COLOR1_FMASK_DEFAULT 0x00000000
-#define mmCB_COLOR1_FMASK_BASE_EXT_DEFAULT 0x00000000
-#define mmCB_COLOR1_CLEAR_WORD0_DEFAULT 0x00000000
-#define mmCB_COLOR1_CLEAR_WORD1_DEFAULT 0x00000000
-#define mmCB_COLOR1_DCC_BASE_DEFAULT 0x00000000
-#define mmCB_COLOR1_DCC_BASE_EXT_DEFAULT 0x00000000
-#define mmCB_COLOR2_BASE_DEFAULT 0x00000000
-#define mmCB_COLOR2_BASE_EXT_DEFAULT 0x00000000
-#define mmCB_COLOR2_ATTRIB2_DEFAULT 0x00000000
-#define mmCB_COLOR2_VIEW_DEFAULT 0x00000000
-#define mmCB_COLOR2_INFO_DEFAULT 0x00000000
-#define mmCB_COLOR2_ATTRIB_DEFAULT 0x00000000
-#define mmCB_COLOR2_DCC_CONTROL_DEFAULT 0x00000000
-#define mmCB_COLOR2_CMASK_DEFAULT 0x00000000
-#define mmCB_COLOR2_CMASK_BASE_EXT_DEFAULT 0x00000000
-#define mmCB_COLOR2_FMASK_DEFAULT 0x00000000
-#define mmCB_COLOR2_FMASK_BASE_EXT_DEFAULT 0x00000000
-#define mmCB_COLOR2_CLEAR_WORD0_DEFAULT 0x00000000
-#define mmCB_COLOR2_CLEAR_WORD1_DEFAULT 0x00000000
-#define mmCB_COLOR2_DCC_BASE_DEFAULT 0x00000000
-#define mmCB_COLOR2_DCC_BASE_EXT_DEFAULT 0x00000000
-#define mmCB_COLOR3_BASE_DEFAULT 0x00000000
-#define mmCB_COLOR3_BASE_EXT_DEFAULT 0x00000000
-#define mmCB_COLOR3_ATTRIB2_DEFAULT 0x00000000
-#define mmCB_COLOR3_VIEW_DEFAULT 0x00000000
-#define mmCB_COLOR3_INFO_DEFAULT 0x00000000
-#define mmCB_COLOR3_ATTRIB_DEFAULT 0x00000000
-#define mmCB_COLOR3_DCC_CONTROL_DEFAULT 0x00000000
-#define mmCB_COLOR3_CMASK_DEFAULT 0x00000000
-#define mmCB_COLOR3_CMASK_BASE_EXT_DEFAULT 0x00000000
-#define mmCB_COLOR3_FMASK_DEFAULT 0x00000000
-#define mmCB_COLOR3_FMASK_BASE_EXT_DEFAULT 0x00000000
-#define mmCB_COLOR3_CLEAR_WORD0_DEFAULT 0x00000000
-#define mmCB_COLOR3_CLEAR_WORD1_DEFAULT 0x00000000
-#define mmCB_COLOR3_DCC_BASE_DEFAULT 0x00000000
-#define mmCB_COLOR3_DCC_BASE_EXT_DEFAULT 0x00000000
-#define mmCB_COLOR4_BASE_DEFAULT 0x00000000
-#define mmCB_COLOR4_BASE_EXT_DEFAULT 0x00000000
-#define mmCB_COLOR4_ATTRIB2_DEFAULT 0x00000000
-#define mmCB_COLOR4_VIEW_DEFAULT 0x00000000
-#define mmCB_COLOR4_INFO_DEFAULT 0x00000000
-#define mmCB_COLOR4_ATTRIB_DEFAULT 0x00000000
-#define mmCB_COLOR4_DCC_CONTROL_DEFAULT 0x00000000
-#define mmCB_COLOR4_CMASK_DEFAULT 0x00000000
-#define mmCB_COLOR4_CMASK_BASE_EXT_DEFAULT 0x00000000
-#define mmCB_COLOR4_FMASK_DEFAULT 0x00000000
-#define mmCB_COLOR4_FMASK_BASE_EXT_DEFAULT 0x00000000
-#define mmCB_COLOR4_CLEAR_WORD0_DEFAULT 0x00000000
-#define mmCB_COLOR4_CLEAR_WORD1_DEFAULT 0x00000000
-#define mmCB_COLOR4_DCC_BASE_DEFAULT 0x00000000
-#define mmCB_COLOR4_DCC_BASE_EXT_DEFAULT 0x00000000
-#define mmCB_COLOR5_BASE_DEFAULT 0x00000000
-#define mmCB_COLOR5_BASE_EXT_DEFAULT 0x00000000
-#define mmCB_COLOR5_ATTRIB2_DEFAULT 0x00000000
-#define mmCB_COLOR5_VIEW_DEFAULT 0x00000000
-#define mmCB_COLOR5_INFO_DEFAULT 0x00000000
-#define mmCB_COLOR5_ATTRIB_DEFAULT 0x00000000
-#define mmCB_COLOR5_DCC_CONTROL_DEFAULT 0x00000000
-#define mmCB_COLOR5_CMASK_DEFAULT 0x00000000
-#define mmCB_COLOR5_CMASK_BASE_EXT_DEFAULT 0x00000000
-#define mmCB_COLOR5_FMASK_DEFAULT 0x00000000
-#define mmCB_COLOR5_FMASK_BASE_EXT_DEFAULT 0x00000000
-#define mmCB_COLOR5_CLEAR_WORD0_DEFAULT 0x00000000
-#define mmCB_COLOR5_CLEAR_WORD1_DEFAULT 0x00000000
-#define mmCB_COLOR5_DCC_BASE_DEFAULT 0x00000000
-#define mmCB_COLOR5_DCC_BASE_EXT_DEFAULT 0x00000000
-#define mmCB_COLOR6_BASE_DEFAULT 0x00000000
-#define mmCB_COLOR6_BASE_EXT_DEFAULT 0x00000000
-#define mmCB_COLOR6_ATTRIB2_DEFAULT 0x00000000
-#define mmCB_COLOR6_VIEW_DEFAULT 0x00000000
-#define mmCB_COLOR6_INFO_DEFAULT 0x00000000
-#define mmCB_COLOR6_ATTRIB_DEFAULT 0x00000000
-#define mmCB_COLOR6_DCC_CONTROL_DEFAULT 0x00000000
-#define mmCB_COLOR6_CMASK_DEFAULT 0x00000000
-#define mmCB_COLOR6_CMASK_BASE_EXT_DEFAULT 0x00000000
-#define mmCB_COLOR6_FMASK_DEFAULT 0x00000000
-#define mmCB_COLOR6_FMASK_BASE_EXT_DEFAULT 0x00000000
-#define mmCB_COLOR6_CLEAR_WORD0_DEFAULT 0x00000000
-#define mmCB_COLOR6_CLEAR_WORD1_DEFAULT 0x00000000
-#define mmCB_COLOR6_DCC_BASE_DEFAULT 0x00000000
-#define mmCB_COLOR6_DCC_BASE_EXT_DEFAULT 0x00000000
-#define mmCB_COLOR7_BASE_DEFAULT 0x00000000
-#define mmCB_COLOR7_BASE_EXT_DEFAULT 0x00000000
-#define mmCB_COLOR7_ATTRIB2_DEFAULT 0x00000000
-#define mmCB_COLOR7_VIEW_DEFAULT 0x00000000
-#define mmCB_COLOR7_INFO_DEFAULT 0x00000000
-#define mmCB_COLOR7_ATTRIB_DEFAULT 0x00000000
-#define mmCB_COLOR7_DCC_CONTROL_DEFAULT 0x00000000
-#define mmCB_COLOR7_CMASK_DEFAULT 0x00000000
-#define mmCB_COLOR7_CMASK_BASE_EXT_DEFAULT 0x00000000
-#define mmCB_COLOR7_FMASK_DEFAULT 0x00000000
-#define mmCB_COLOR7_FMASK_BASE_EXT_DEFAULT 0x00000000
-#define mmCB_COLOR7_CLEAR_WORD0_DEFAULT 0x00000000
-#define mmCB_COLOR7_CLEAR_WORD1_DEFAULT 0x00000000
-#define mmCB_COLOR7_DCC_BASE_DEFAULT 0x00000000
-#define mmCB_COLOR7_DCC_BASE_EXT_DEFAULT 0x00000000
-
-
-// addressBlock: gc_gfxudec
-#define mmCP_EOP_DONE_ADDR_LO_DEFAULT 0x00000000
-#define mmCP_EOP_DONE_ADDR_HI_DEFAULT 0x00000000
-#define mmCP_EOP_DONE_DATA_LO_DEFAULT 0x00000000
-#define mmCP_EOP_DONE_DATA_HI_DEFAULT 0x00000000
-#define mmCP_EOP_LAST_FENCE_LO_DEFAULT 0x00000000
-#define mmCP_EOP_LAST_FENCE_HI_DEFAULT 0x00000000
-#define mmCP_STREAM_OUT_ADDR_LO_DEFAULT 0x00000000
-#define mmCP_STREAM_OUT_ADDR_HI_DEFAULT 0x00000000
-#define mmCP_NUM_PRIM_WRITTEN_COUNT0_LO_DEFAULT 0x00000000
-#define mmCP_NUM_PRIM_WRITTEN_COUNT0_HI_DEFAULT 0x00000000
-#define mmCP_NUM_PRIM_NEEDED_COUNT0_LO_DEFAULT 0x00000000
-#define mmCP_NUM_PRIM_NEEDED_COUNT0_HI_DEFAULT 0x00000000
-#define mmCP_NUM_PRIM_WRITTEN_COUNT1_LO_DEFAULT 0x00000000
-#define mmCP_NUM_PRIM_WRITTEN_COUNT1_HI_DEFAULT 0x00000000
-#define mmCP_NUM_PRIM_NEEDED_COUNT1_LO_DEFAULT 0x00000000
-#define mmCP_NUM_PRIM_NEEDED_COUNT1_HI_DEFAULT 0x00000000
-#define mmCP_NUM_PRIM_WRITTEN_COUNT2_LO_DEFAULT 0x00000000
-#define mmCP_NUM_PRIM_WRITTEN_COUNT2_HI_DEFAULT 0x00000000
-#define mmCP_NUM_PRIM_NEEDED_COUNT2_LO_DEFAULT 0x00000000
-#define mmCP_NUM_PRIM_NEEDED_COUNT2_HI_DEFAULT 0x00000000
-#define mmCP_NUM_PRIM_WRITTEN_COUNT3_LO_DEFAULT 0x00000000
-#define mmCP_NUM_PRIM_WRITTEN_COUNT3_HI_DEFAULT 0x00000000
-#define mmCP_NUM_PRIM_NEEDED_COUNT3_LO_DEFAULT 0x00000000
-#define mmCP_NUM_PRIM_NEEDED_COUNT3_HI_DEFAULT 0x00000000
-#define mmCP_PIPE_STATS_ADDR_LO_DEFAULT 0x00000000
-#define mmCP_PIPE_STATS_ADDR_HI_DEFAULT 0x00000000
-#define mmCP_VGT_IAVERT_COUNT_LO_DEFAULT 0x00000000
-#define mmCP_VGT_IAVERT_COUNT_HI_DEFAULT 0x00000000
-#define mmCP_VGT_IAPRIM_COUNT_LO_DEFAULT 0x00000000
-#define mmCP_VGT_IAPRIM_COUNT_HI_DEFAULT 0x00000000
-#define mmCP_VGT_GSPRIM_COUNT_LO_DEFAULT 0x00000000
-#define mmCP_VGT_GSPRIM_COUNT_HI_DEFAULT 0x00000000
-#define mmCP_VGT_VSINVOC_COUNT_LO_DEFAULT 0x00000000
-#define mmCP_VGT_VSINVOC_COUNT_HI_DEFAULT 0x00000000
-#define mmCP_VGT_GSINVOC_COUNT_LO_DEFAULT 0x00000000
-#define mmCP_VGT_GSINVOC_COUNT_HI_DEFAULT 0x00000000
-#define mmCP_VGT_HSINVOC_COUNT_LO_DEFAULT 0x00000000
-#define mmCP_VGT_HSINVOC_COUNT_HI_DEFAULT 0x00000000
-#define mmCP_VGT_DSINVOC_COUNT_LO_DEFAULT 0x00000000
-#define mmCP_VGT_DSINVOC_COUNT_HI_DEFAULT 0x00000000
-#define mmCP_PA_CINVOC_COUNT_LO_DEFAULT 0x00000000
-#define mmCP_PA_CINVOC_COUNT_HI_DEFAULT 0x00000000
-#define mmCP_PA_CPRIM_COUNT_LO_DEFAULT 0x00000000
-#define mmCP_PA_CPRIM_COUNT_HI_DEFAULT 0x00000000
-#define mmCP_SC_PSINVOC_COUNT0_LO_DEFAULT 0x00000000
-#define mmCP_SC_PSINVOC_COUNT0_HI_DEFAULT 0x00000000
-#define mmCP_SC_PSINVOC_COUNT1_LO_DEFAULT 0x00000000
-#define mmCP_SC_PSINVOC_COUNT1_HI_DEFAULT 0x00000000
-#define mmCP_VGT_CSINVOC_COUNT_LO_DEFAULT 0x00000000
-#define mmCP_VGT_CSINVOC_COUNT_HI_DEFAULT 0x00000000
-#define mmCP_PIPE_STATS_CONTROL_DEFAULT 0x00000000
-#define mmCP_STREAM_OUT_CONTROL_DEFAULT 0x00000000
-#define mmCP_STRMOUT_CNTL_DEFAULT 0x00000000
-#define mmSCRATCH_REG0_DEFAULT 0x00000000
-#define mmSCRATCH_REG1_DEFAULT 0x00000000
-#define mmSCRATCH_REG2_DEFAULT 0x00000000
-#define mmSCRATCH_REG3_DEFAULT 0x00000000
-#define mmSCRATCH_REG4_DEFAULT 0x00000000
-#define mmSCRATCH_REG5_DEFAULT 0x00000000
-#define mmSCRATCH_REG6_DEFAULT 0x00000000
-#define mmSCRATCH_REG7_DEFAULT 0x00000000
-#define mmCP_APPEND_DATA_HI_DEFAULT 0x00000000
-#define mmCP_APPEND_LAST_CS_FENCE_HI_DEFAULT 0x00000000
-#define mmCP_APPEND_LAST_PS_FENCE_HI_DEFAULT 0x00000000
-#define mmSCRATCH_UMSK_DEFAULT 0x00000000
-#define mmSCRATCH_ADDR_DEFAULT 0x00000000
-#define mmCP_PFP_ATOMIC_PREOP_LO_DEFAULT 0x00000000
-#define mmCP_PFP_ATOMIC_PREOP_HI_DEFAULT 0x00000000
-#define mmCP_PFP_GDS_ATOMIC0_PREOP_LO_DEFAULT 0x00000000
-#define mmCP_PFP_GDS_ATOMIC0_PREOP_HI_DEFAULT 0x00000000
-#define mmCP_PFP_GDS_ATOMIC1_PREOP_LO_DEFAULT 0x00000000
-#define mmCP_PFP_GDS_ATOMIC1_PREOP_HI_DEFAULT 0x00000000
-#define mmCP_APPEND_ADDR_LO_DEFAULT 0x00000000
-#define mmCP_APPEND_ADDR_HI_DEFAULT 0x00000000
-#define mmCP_APPEND_DATA_LO_DEFAULT 0x00000000
-#define mmCP_APPEND_LAST_CS_FENCE_LO_DEFAULT 0x00000000
-#define mmCP_APPEND_LAST_PS_FENCE_LO_DEFAULT 0x00000000
-#define mmCP_ATOMIC_PREOP_LO_DEFAULT 0x00000000
-#define mmCP_ME_ATOMIC_PREOP_LO_DEFAULT 0x00000000
-#define mmCP_ATOMIC_PREOP_HI_DEFAULT 0x00000000
-#define mmCP_ME_ATOMIC_PREOP_HI_DEFAULT 0x00000000
-#define mmCP_GDS_ATOMIC0_PREOP_LO_DEFAULT 0x00000000
-#define mmCP_ME_GDS_ATOMIC0_PREOP_LO_DEFAULT 0x00000000
-#define mmCP_GDS_ATOMIC0_PREOP_HI_DEFAULT 0x00000000
-#define mmCP_ME_GDS_ATOMIC0_PREOP_HI_DEFAULT 0x00000000
-#define mmCP_GDS_ATOMIC1_PREOP_LO_DEFAULT 0x00000000
-#define mmCP_ME_GDS_ATOMIC1_PREOP_LO_DEFAULT 0x00000000
-#define mmCP_GDS_ATOMIC1_PREOP_HI_DEFAULT 0x00000000
-#define mmCP_ME_GDS_ATOMIC1_PREOP_HI_DEFAULT 0x00000000
-#define mmCP_ME_MC_WADDR_LO_DEFAULT 0x00000000
-#define mmCP_ME_MC_WADDR_HI_DEFAULT 0x00000000
-#define mmCP_ME_MC_WDATA_LO_DEFAULT 0x00000000
-#define mmCP_ME_MC_WDATA_HI_DEFAULT 0x00000000
-#define mmCP_ME_MC_RADDR_LO_DEFAULT 0x00000000
-#define mmCP_ME_MC_RADDR_HI_DEFAULT 0x00000000
-#define mmCP_SEM_WAIT_TIMER_DEFAULT 0x00000000
-#define mmCP_SIG_SEM_ADDR_LO_DEFAULT 0x00000000
-#define mmCP_SIG_SEM_ADDR_HI_DEFAULT 0x00000000
-#define mmCP_WAIT_REG_MEM_TIMEOUT_DEFAULT 0x00000000
-#define mmCP_WAIT_SEM_ADDR_LO_DEFAULT 0x00000000
-#define mmCP_WAIT_SEM_ADDR_HI_DEFAULT 0x00000000
-#define mmCP_DMA_PFP_CONTROL_DEFAULT 0x00000000
-#define mmCP_DMA_ME_CONTROL_DEFAULT 0x00000000
-#define mmCP_COHER_BASE_HI_DEFAULT 0x00000000
-#define mmCP_COHER_START_DELAY_DEFAULT 0x00000020
-#define mmCP_COHER_CNTL_DEFAULT 0x00000000
-#define mmCP_COHER_SIZE_DEFAULT 0x00000000
-#define mmCP_COHER_BASE_DEFAULT 0x00000000
-#define mmCP_COHER_STATUS_DEFAULT 0x00000000
-#define mmCP_DMA_ME_SRC_ADDR_DEFAULT 0x00000000
-#define mmCP_DMA_ME_SRC_ADDR_HI_DEFAULT 0x00000000
-#define mmCP_DMA_ME_DST_ADDR_DEFAULT 0x00000000
-#define mmCP_DMA_ME_DST_ADDR_HI_DEFAULT 0x00000000
-#define mmCP_DMA_ME_COMMAND_DEFAULT 0x00000000
-#define mmCP_DMA_PFP_SRC_ADDR_DEFAULT 0x00000000
-#define mmCP_DMA_PFP_SRC_ADDR_HI_DEFAULT 0x00000000
-#define mmCP_DMA_PFP_DST_ADDR_DEFAULT 0x00000000
-#define mmCP_DMA_PFP_DST_ADDR_HI_DEFAULT 0x00000000
-#define mmCP_DMA_PFP_COMMAND_DEFAULT 0x00000000
-#define mmCP_DMA_CNTL_DEFAULT 0x00080030
-#define mmCP_DMA_READ_TAGS_DEFAULT 0x00000000
-#define mmCP_COHER_SIZE_HI_DEFAULT 0x00000000
-#define mmCP_PFP_IB_CONTROL_DEFAULT 0x00000000
-#define mmCP_PFP_LOAD_CONTROL_DEFAULT 0x00000000
-#define mmCP_SCRATCH_INDEX_DEFAULT 0x00000000
-#define mmCP_SCRATCH_DATA_DEFAULT 0x00000000
-#define mmCP_RB_OFFSET_DEFAULT 0x00000000
-#define mmCP_IB1_OFFSET_DEFAULT 0x00000000
-#define mmCP_IB2_OFFSET_DEFAULT 0x00000000
-#define mmCP_IB1_PREAMBLE_BEGIN_DEFAULT 0x00000000
-#define mmCP_IB1_PREAMBLE_END_DEFAULT 0x00000000
-#define mmCP_IB2_PREAMBLE_BEGIN_DEFAULT 0x00000000
-#define mmCP_IB2_PREAMBLE_END_DEFAULT 0x00000000
-#define mmCP_CE_IB1_OFFSET_DEFAULT 0x00000000
-#define mmCP_CE_IB2_OFFSET_DEFAULT 0x00000000
-#define mmCP_CE_COUNTER_DEFAULT 0x00000000
-#define mmCP_CE_RB_OFFSET_DEFAULT 0x00000000
-#define mmCP_CE_INIT_CMD_BUFSZ_DEFAULT 0x00000000
-#define mmCP_CE_IB1_CMD_BUFSZ_DEFAULT 0x00000000
-#define mmCP_CE_IB2_CMD_BUFSZ_DEFAULT 0x00000000
-#define mmCP_IB1_CMD_BUFSZ_DEFAULT 0x00000000
-#define mmCP_IB2_CMD_BUFSZ_DEFAULT 0x00000000
-#define mmCP_ST_CMD_BUFSZ_DEFAULT 0x00000000
-#define mmCP_CE_INIT_BASE_LO_DEFAULT 0x00000000
-#define mmCP_CE_INIT_BASE_HI_DEFAULT 0x00000000
-#define mmCP_CE_INIT_BUFSZ_DEFAULT 0x00000000
-#define mmCP_CE_IB1_BASE_LO_DEFAULT 0x00000000
-#define mmCP_CE_IB1_BASE_HI_DEFAULT 0x00000000
-#define mmCP_CE_IB1_BUFSZ_DEFAULT 0x00000000
-#define mmCP_CE_IB2_BASE_LO_DEFAULT 0x00000000
-#define mmCP_CE_IB2_BASE_HI_DEFAULT 0x00000000
-#define mmCP_CE_IB2_BUFSZ_DEFAULT 0x00000000
-#define mmCP_IB1_BASE_LO_DEFAULT 0x00000000
-#define mmCP_IB1_BASE_HI_DEFAULT 0x00000000
-#define mmCP_IB1_BUFSZ_DEFAULT 0x00000000
-#define mmCP_IB2_BASE_LO_DEFAULT 0x00000000
-#define mmCP_IB2_BASE_HI_DEFAULT 0x00000000
-#define mmCP_IB2_BUFSZ_DEFAULT 0x00000000
-#define mmCP_ST_BASE_LO_DEFAULT 0x00000000
-#define mmCP_ST_BASE_HI_DEFAULT 0x00000000
-#define mmCP_ST_BUFSZ_DEFAULT 0x00000000
-#define mmCP_EOP_DONE_EVENT_CNTL_DEFAULT 0x00000000
-#define mmCP_EOP_DONE_DATA_CNTL_DEFAULT 0x00000000
-#define mmCP_EOP_DONE_CNTX_ID_DEFAULT 0x00000000
-#define mmCP_PFP_COMPLETION_STATUS_DEFAULT 0x00000000
-#define mmCP_CE_COMPLETION_STATUS_DEFAULT 0x00000000
-#define mmCP_PRED_NOT_VISIBLE_DEFAULT 0x00000000
-#define mmCP_PFP_METADATA_BASE_ADDR_DEFAULT 0x00000000
-#define mmCP_PFP_METADATA_BASE_ADDR_HI_DEFAULT 0x00000000
-#define mmCP_CE_METADATA_BASE_ADDR_DEFAULT 0x00000000
-#define mmCP_CE_METADATA_BASE_ADDR_HI_DEFAULT 0x00000000
-#define mmCP_DRAW_INDX_INDR_ADDR_DEFAULT 0x00000000
-#define mmCP_DRAW_INDX_INDR_ADDR_HI_DEFAULT 0x00000000
-#define mmCP_DISPATCH_INDR_ADDR_DEFAULT 0x00000000
-#define mmCP_DISPATCH_INDR_ADDR_HI_DEFAULT 0x00000000
-#define mmCP_INDEX_BASE_ADDR_DEFAULT 0x00000000
-#define mmCP_INDEX_BASE_ADDR_HI_DEFAULT 0x00000000
-#define mmCP_INDEX_TYPE_DEFAULT 0x00000000
-#define mmCP_GDS_BKUP_ADDR_DEFAULT 0x00000000
-#define mmCP_GDS_BKUP_ADDR_HI_DEFAULT 0x00000000
-#define mmCP_SAMPLE_STATUS_DEFAULT 0x00000000
-#define mmCP_ME_COHER_CNTL_DEFAULT 0x00000000
-#define mmCP_ME_COHER_SIZE_DEFAULT 0x00000000
-#define mmCP_ME_COHER_SIZE_HI_DEFAULT 0x00000000
-#define mmCP_ME_COHER_BASE_DEFAULT 0x00000000
-#define mmCP_ME_COHER_BASE_HI_DEFAULT 0x00000000
-#define mmCP_ME_COHER_STATUS_DEFAULT 0x00000000
-#define mmRLC_GPM_PERF_COUNT_0_DEFAULT 0x00000000
-#define mmRLC_GPM_PERF_COUNT_1_DEFAULT 0x00000000
-#define mmGRBM_GFX_INDEX_DEFAULT 0xe0000000
-#define mmVGT_GSVS_RING_SIZE_DEFAULT 0x00000000
-#define mmVGT_PRIMITIVE_TYPE_DEFAULT 0x00000000
-#define mmVGT_INDEX_TYPE_DEFAULT 0x00000000
-#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0_DEFAULT 0x00000000
-#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1_DEFAULT 0x00000000
-#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2_DEFAULT 0x00000000
-#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3_DEFAULT 0x00000000
-#define mmVGT_MAX_VTX_INDX_DEFAULT 0x00000000
-#define mmVGT_MIN_VTX_INDX_DEFAULT 0x00000000
-#define mmVGT_INDX_OFFSET_DEFAULT 0x00000000
-#define mmVGT_MULTI_PRIM_IB_RESET_EN_DEFAULT 0x00000000
-#define mmVGT_NUM_INDICES_DEFAULT 0x00000000
-#define mmVGT_NUM_INSTANCES_DEFAULT 0x00000000
-#define mmVGT_TF_RING_SIZE_DEFAULT 0x00002000
-#define mmVGT_HS_OFFCHIP_PARAM_DEFAULT 0x00000000
-#define mmVGT_TF_MEMORY_BASE_DEFAULT 0x00000000
-#define mmVGT_TF_MEMORY_BASE_HI_DEFAULT 0x00000000
-#define mmWD_POS_BUF_BASE_DEFAULT 0x00000000
-#define mmWD_POS_BUF_BASE_HI_DEFAULT 0x00000000
-#define mmWD_CNTL_SB_BUF_BASE_DEFAULT 0x00000000
-#define mmWD_CNTL_SB_BUF_BASE_HI_DEFAULT 0x00000000
-#define mmWD_INDEX_BUF_BASE_DEFAULT 0x00000000
-#define mmWD_INDEX_BUF_BASE_HI_DEFAULT 0x00000000
-#define mmIA_MULTI_VGT_PARAM_DEFAULT 0x006000ff
-#define mmVGT_OBJECT_ID_DEFAULT 0x00000000
-#define mmVGT_INSTANCE_BASE_ID_DEFAULT 0x00000000
-#define mmPA_SU_LINE_STIPPLE_VALUE_DEFAULT 0x00000000
-#define mmPA_SC_LINE_STIPPLE_STATE_DEFAULT 0x00000000
-#define mmPA_SC_SCREEN_EXTENT_MIN_0_DEFAULT 0x7fff7fff
-#define mmPA_SC_SCREEN_EXTENT_MAX_0_DEFAULT 0x80008000
-#define mmPA_SC_SCREEN_EXTENT_MIN_1_DEFAULT 0x7fff7fff
-#define mmPA_SC_SCREEN_EXTENT_MAX_1_DEFAULT 0x80008000
-#define mmPA_SC_P3D_TRAP_SCREEN_HV_EN_DEFAULT 0x00000000
-#define mmPA_SC_P3D_TRAP_SCREEN_H_DEFAULT 0x00000000
-#define mmPA_SC_P3D_TRAP_SCREEN_V_DEFAULT 0x00000000
-#define mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE_DEFAULT 0x00000000
-#define mmPA_SC_P3D_TRAP_SCREEN_COUNT_DEFAULT 0x00000000
-#define mmPA_SC_HP3D_TRAP_SCREEN_HV_EN_DEFAULT 0x00000000
-#define mmPA_SC_HP3D_TRAP_SCREEN_H_DEFAULT 0x00000000
-#define mmPA_SC_HP3D_TRAP_SCREEN_V_DEFAULT 0x00000000
-#define mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE_DEFAULT 0x00000000
-#define mmPA_SC_HP3D_TRAP_SCREEN_COUNT_DEFAULT 0x00000000
-#define mmPA_SC_TRAP_SCREEN_HV_EN_DEFAULT 0x00000000
-#define mmPA_SC_TRAP_SCREEN_H_DEFAULT 0x00000000
-#define mmPA_SC_TRAP_SCREEN_V_DEFAULT 0x00000000
-#define mmPA_SC_TRAP_SCREEN_OCCURRENCE_DEFAULT 0x00000000
-#define mmPA_SC_TRAP_SCREEN_COUNT_DEFAULT 0x00000000
-#define mmSQ_THREAD_TRACE_BASE_DEFAULT 0x00000000
-#define mmSQ_THREAD_TRACE_SIZE_DEFAULT 0x00000000
-#define mmSQ_THREAD_TRACE_MASK_DEFAULT 0x0000cf80
-#define mmSQ_THREAD_TRACE_TOKEN_MASK_DEFAULT 0x00ffffff
-#define mmSQ_THREAD_TRACE_PERF_MASK_DEFAULT 0xffffffff
-#define mmSQ_THREAD_TRACE_CTRL_DEFAULT 0x00000000
-#define mmSQ_THREAD_TRACE_MODE_DEFAULT 0x02049249
-#define mmSQ_THREAD_TRACE_BASE2_DEFAULT 0x00000000
-#define mmSQ_THREAD_TRACE_TOKEN_MASK2_DEFAULT 0xffffffff
-#define mmSQ_THREAD_TRACE_WPTR_DEFAULT 0x00000000
-#define mmSQ_THREAD_TRACE_STATUS_DEFAULT 0x00000000
-#define mmSQ_THREAD_TRACE_HIWATER_DEFAULT 0x00000000
-#define mmSQ_THREAD_TRACE_CNTR_DEFAULT 0x00000000
-#define mmSQ_THREAD_TRACE_USERDATA_0_DEFAULT 0x00000000
-#define mmSQ_THREAD_TRACE_USERDATA_1_DEFAULT 0x00000000
-#define mmSQ_THREAD_TRACE_USERDATA_2_DEFAULT 0x00000000
-#define mmSQ_THREAD_TRACE_USERDATA_3_DEFAULT 0x00000000
-#define mmSQC_CACHES_DEFAULT 0x00000000
-#define mmSQC_WRITEBACK_DEFAULT 0x00000000
-#define mmTA_CS_BC_BASE_ADDR_DEFAULT 0x00000000
-#define mmTA_CS_BC_BASE_ADDR_HI_DEFAULT 0x00000000
-#define mmTA_GRAD_ADJ_UCONFIG_DEFAULT 0x40000040
-#define mmDB_OCCLUSION_COUNT0_LOW_DEFAULT 0x00000000
-#define mmDB_OCCLUSION_COUNT0_HI_DEFAULT 0x00000000
-#define mmDB_OCCLUSION_COUNT1_LOW_DEFAULT 0x00000000
-#define mmDB_OCCLUSION_COUNT1_HI_DEFAULT 0x00000000
-#define mmDB_OCCLUSION_COUNT2_LOW_DEFAULT 0x00000000
-#define mmDB_OCCLUSION_COUNT2_HI_DEFAULT 0x00000000
-#define mmDB_OCCLUSION_COUNT3_LOW_DEFAULT 0x00000000
-#define mmDB_OCCLUSION_COUNT3_HI_DEFAULT 0x00000000
-#define mmDB_ZPASS_COUNT_LOW_DEFAULT 0x00000000
-#define mmDB_ZPASS_COUNT_HI_DEFAULT 0x00000000
-#define mmGDS_RD_ADDR_DEFAULT 0x00000000
-#define mmGDS_RD_DATA_DEFAULT 0x00000000
-#define mmGDS_RD_BURST_ADDR_DEFAULT 0x00000000
-#define mmGDS_RD_BURST_COUNT_DEFAULT 0x00000000
-#define mmGDS_RD_BURST_DATA_DEFAULT 0x00000000
-#define mmGDS_WR_ADDR_DEFAULT 0x00000000
-#define mmGDS_WR_DATA_DEFAULT 0x00000000
-#define mmGDS_WR_BURST_ADDR_DEFAULT 0x00000000
-#define mmGDS_WR_BURST_DATA_DEFAULT 0x00000000
-#define mmGDS_WRITE_COMPLETE_DEFAULT 0x00000000
-#define mmGDS_ATOM_CNTL_DEFAULT 0x00000000
-#define mmGDS_ATOM_COMPLETE_DEFAULT 0x00000001
-#define mmGDS_ATOM_BASE_DEFAULT 0x00000000
-#define mmGDS_ATOM_SIZE_DEFAULT 0x00000000
-#define mmGDS_ATOM_OFFSET0_DEFAULT 0x00000000
-#define mmGDS_ATOM_OFFSET1_DEFAULT 0x00000000
-#define mmGDS_ATOM_DST_DEFAULT 0x00000000
-#define mmGDS_ATOM_OP_DEFAULT 0x00000000
-#define mmGDS_ATOM_SRC0_DEFAULT 0x00000000
-#define mmGDS_ATOM_SRC0_U_DEFAULT 0x00000000
-#define mmGDS_ATOM_SRC1_DEFAULT 0x00000000
-#define mmGDS_ATOM_SRC1_U_DEFAULT 0x00000000
-#define mmGDS_ATOM_READ0_DEFAULT 0x00000000
-#define mmGDS_ATOM_READ0_U_DEFAULT 0x00000000
-#define mmGDS_ATOM_READ1_DEFAULT 0x00000000
-#define mmGDS_ATOM_READ1_U_DEFAULT 0x00000000
-#define mmGDS_GWS_RESOURCE_CNTL_DEFAULT 0x00000000
-#define mmGDS_GWS_RESOURCE_DEFAULT 0x00000000
-#define mmGDS_GWS_RESOURCE_CNT_DEFAULT 0x00000000
-#define mmGDS_OA_CNTL_DEFAULT 0x00000000
-#define mmGDS_OA_COUNTER_DEFAULT 0x00000000
-#define mmGDS_OA_ADDRESS_DEFAULT 0x00000000
-#define mmGDS_OA_INCDEC_DEFAULT 0x00000000
-#define mmGDS_OA_RING_SIZE_DEFAULT 0x00000000
-#define mmSPI_CONFIG_CNTL_DEFAULT 0x0062c688
-#define mmSPI_CONFIG_CNTL_1_DEFAULT 0x01000104
-#define mmSPI_CONFIG_CNTL_2_DEFAULT 0x00000011
-
-
-// addressBlock: gc_perfddec
-#define mmCPG_PERFCOUNTER1_LO_DEFAULT 0x00000000
-#define mmCPG_PERFCOUNTER1_HI_DEFAULT 0x00000000
-#define mmCPG_PERFCOUNTER0_LO_DEFAULT 0x00000000
-#define mmCPG_PERFCOUNTER0_HI_DEFAULT 0x00000000
-#define mmCPC_PERFCOUNTER1_LO_DEFAULT 0x00000000
-#define mmCPC_PERFCOUNTER1_HI_DEFAULT 0x00000000
-#define mmCPC_PERFCOUNTER0_LO_DEFAULT 0x00000000
-#define mmCPC_PERFCOUNTER0_HI_DEFAULT 0x00000000
-#define mmCPF_PERFCOUNTER1_LO_DEFAULT 0x00000000
-#define mmCPF_PERFCOUNTER1_HI_DEFAULT 0x00000000
-#define mmCPF_PERFCOUNTER0_LO_DEFAULT 0x00000000
-#define mmCPF_PERFCOUNTER0_HI_DEFAULT 0x00000000
-#define mmCPF_LATENCY_STATS_DATA_DEFAULT 0x00000000
-#define mmCPG_LATENCY_STATS_DATA_DEFAULT 0x00000000
-#define mmCPC_LATENCY_STATS_DATA_DEFAULT 0x00000000
-#define mmGRBM_PERFCOUNTER0_LO_DEFAULT 0x00000000
-#define mmGRBM_PERFCOUNTER0_HI_DEFAULT 0x00000000
-#define mmGRBM_PERFCOUNTER1_LO_DEFAULT 0x00000000
-#define mmGRBM_PERFCOUNTER1_HI_DEFAULT 0x00000000
-#define mmGRBM_SE0_PERFCOUNTER_LO_DEFAULT 0x00000000
-#define mmGRBM_SE0_PERFCOUNTER_HI_DEFAULT 0x00000000
-#define mmGRBM_SE1_PERFCOUNTER_LO_DEFAULT 0x00000000
-#define mmGRBM_SE1_PERFCOUNTER_HI_DEFAULT 0x00000000
-#define mmGRBM_SE2_PERFCOUNTER_LO_DEFAULT 0x00000000
-#define mmGRBM_SE2_PERFCOUNTER_HI_DEFAULT 0x00000000
-#define mmGRBM_SE3_PERFCOUNTER_LO_DEFAULT 0x00000000
-#define mmGRBM_SE3_PERFCOUNTER_HI_DEFAULT 0x00000000
-#define mmWD_PERFCOUNTER0_LO_DEFAULT 0x00000000
-#define mmWD_PERFCOUNTER0_HI_DEFAULT 0x00000000
-#define mmWD_PERFCOUNTER1_LO_DEFAULT 0x00000000
-#define mmWD_PERFCOUNTER1_HI_DEFAULT 0x00000000
-#define mmWD_PERFCOUNTER2_LO_DEFAULT 0x00000000
-#define mmWD_PERFCOUNTER2_HI_DEFAULT 0x00000000
-#define mmWD_PERFCOUNTER3_LO_DEFAULT 0x00000000
-#define mmWD_PERFCOUNTER3_HI_DEFAULT 0x00000000
-#define mmIA_PERFCOUNTER0_LO_DEFAULT 0x00000000
-#define mmIA_PERFCOUNTER0_HI_DEFAULT 0x00000000
-#define mmIA_PERFCOUNTER1_LO_DEFAULT 0x00000000
-#define mmIA_PERFCOUNTER1_HI_DEFAULT 0x00000000
-#define mmIA_PERFCOUNTER2_LO_DEFAULT 0x00000000
-#define mmIA_PERFCOUNTER2_HI_DEFAULT 0x00000000
-#define mmIA_PERFCOUNTER3_LO_DEFAULT 0x00000000
-#define mmIA_PERFCOUNTER3_HI_DEFAULT 0x00000000
-#define mmVGT_PERFCOUNTER0_LO_DEFAULT 0x00000000
-#define mmVGT_PERFCOUNTER0_HI_DEFAULT 0x00000000
-#define mmVGT_PERFCOUNTER1_LO_DEFAULT 0x00000000
-#define mmVGT_PERFCOUNTER1_HI_DEFAULT 0x00000000
-#define mmVGT_PERFCOUNTER2_LO_DEFAULT 0x00000000
-#define mmVGT_PERFCOUNTER2_HI_DEFAULT 0x00000000
-#define mmVGT_PERFCOUNTER3_LO_DEFAULT 0x00000000
-#define mmVGT_PERFCOUNTER3_HI_DEFAULT 0x00000000
-#define mmPA_SU_PERFCOUNTER0_LO_DEFAULT 0x00000000
-#define mmPA_SU_PERFCOUNTER0_HI_DEFAULT 0x00000000
-#define mmPA_SU_PERFCOUNTER1_LO_DEFAULT 0x00000000
-#define mmPA_SU_PERFCOUNTER1_HI_DEFAULT 0x00000000
-#define mmPA_SU_PERFCOUNTER2_LO_DEFAULT 0x00000000
-#define mmPA_SU_PERFCOUNTER2_HI_DEFAULT 0x00000000
-#define mmPA_SU_PERFCOUNTER3_LO_DEFAULT 0x00000000
-#define mmPA_SU_PERFCOUNTER3_HI_DEFAULT 0x00000000
-#define mmPA_SC_PERFCOUNTER0_LO_DEFAULT 0x00000000
-#define mmPA_SC_PERFCOUNTER0_HI_DEFAULT 0x00000000
-#define mmPA_SC_PERFCOUNTER1_LO_DEFAULT 0x00000000
-#define mmPA_SC_PERFCOUNTER1_HI_DEFAULT 0x00000000
-#define mmPA_SC_PERFCOUNTER2_LO_DEFAULT 0x00000000
-#define mmPA_SC_PERFCOUNTER2_HI_DEFAULT 0x00000000
-#define mmPA_SC_PERFCOUNTER3_LO_DEFAULT 0x00000000
-#define mmPA_SC_PERFCOUNTER3_HI_DEFAULT 0x00000000
-#define mmPA_SC_PERFCOUNTER4_LO_DEFAULT 0x00000000
-#define mmPA_SC_PERFCOUNTER4_HI_DEFAULT 0x00000000
-#define mmPA_SC_PERFCOUNTER5_LO_DEFAULT 0x00000000
-#define mmPA_SC_PERFCOUNTER5_HI_DEFAULT 0x00000000
-#define mmPA_SC_PERFCOUNTER6_LO_DEFAULT 0x00000000
-#define mmPA_SC_PERFCOUNTER6_HI_DEFAULT 0x00000000
-#define mmPA_SC_PERFCOUNTER7_LO_DEFAULT 0x00000000
-#define mmPA_SC_PERFCOUNTER7_HI_DEFAULT 0x00000000
-#define mmSPI_PERFCOUNTER0_HI_DEFAULT 0x00000000
-#define mmSPI_PERFCOUNTER0_LO_DEFAULT 0x00000000
-#define mmSPI_PERFCOUNTER1_HI_DEFAULT 0x00000000
-#define mmSPI_PERFCOUNTER1_LO_DEFAULT 0x00000000
-#define mmSPI_PERFCOUNTER2_HI_DEFAULT 0x00000000
-#define mmSPI_PERFCOUNTER2_LO_DEFAULT 0x00000000
-#define mmSPI_PERFCOUNTER3_HI_DEFAULT 0x00000000
-#define mmSPI_PERFCOUNTER3_LO_DEFAULT 0x00000000
-#define mmSPI_PERFCOUNTER4_HI_DEFAULT 0x00000000
-#define mmSPI_PERFCOUNTER4_LO_DEFAULT 0x00000000
-#define mmSPI_PERFCOUNTER5_HI_DEFAULT 0x00000000
-#define mmSPI_PERFCOUNTER5_LO_DEFAULT 0x00000000
-#define mmSQ_PERFCOUNTER0_LO_DEFAULT 0x00000000
-#define mmSQ_PERFCOUNTER0_HI_DEFAULT 0x00000000
-#define mmSQ_PERFCOUNTER1_LO_DEFAULT 0x00000000
-#define mmSQ_PERFCOUNTER1_HI_DEFAULT 0x00000000
-#define mmSQ_PERFCOUNTER2_LO_DEFAULT 0x00000000
-#define mmSQ_PERFCOUNTER2_HI_DEFAULT 0x00000000
-#define mmSQ_PERFCOUNTER3_LO_DEFAULT 0x00000000
-#define mmSQ_PERFCOUNTER3_HI_DEFAULT 0x00000000
-#define mmSQ_PERFCOUNTER4_LO_DEFAULT 0x00000000
-#define mmSQ_PERFCOUNTER4_HI_DEFAULT 0x00000000
-#define mmSQ_PERFCOUNTER5_LO_DEFAULT 0x00000000
-#define mmSQ_PERFCOUNTER5_HI_DEFAULT 0x00000000
-#define mmSQ_PERFCOUNTER6_LO_DEFAULT 0x00000000
-#define mmSQ_PERFCOUNTER6_HI_DEFAULT 0x00000000
-#define mmSQ_PERFCOUNTER7_LO_DEFAULT 0x00000000
-#define mmSQ_PERFCOUNTER7_HI_DEFAULT 0x00000000
-#define mmSQ_PERFCOUNTER8_LO_DEFAULT 0x00000000
-#define mmSQ_PERFCOUNTER8_HI_DEFAULT 0x00000000
-#define mmSQ_PERFCOUNTER9_LO_DEFAULT 0x00000000
-#define mmSQ_PERFCOUNTER9_HI_DEFAULT 0x00000000
-#define mmSQ_PERFCOUNTER10_LO_DEFAULT 0x00000000
-#define mmSQ_PERFCOUNTER10_HI_DEFAULT 0x00000000
-#define mmSQ_PERFCOUNTER11_LO_DEFAULT 0x00000000
-#define mmSQ_PERFCOUNTER11_HI_DEFAULT 0x00000000
-#define mmSQ_PERFCOUNTER12_LO_DEFAULT 0x00000000
-#define mmSQ_PERFCOUNTER12_HI_DEFAULT 0x00000000
-#define mmSQ_PERFCOUNTER13_LO_DEFAULT 0x00000000
-#define mmSQ_PERFCOUNTER13_HI_DEFAULT 0x00000000
-#define mmSQ_PERFCOUNTER14_LO_DEFAULT 0x00000000
-#define mmSQ_PERFCOUNTER14_HI_DEFAULT 0x00000000
-#define mmSQ_PERFCOUNTER15_LO_DEFAULT 0x00000000
-#define mmSQ_PERFCOUNTER15_HI_DEFAULT 0x00000000
-#define mmSX_PERFCOUNTER0_LO_DEFAULT 0x00000000
-#define mmSX_PERFCOUNTER0_HI_DEFAULT 0x00000000
-#define mmSX_PERFCOUNTER1_LO_DEFAULT 0x00000000
-#define mmSX_PERFCOUNTER1_HI_DEFAULT 0x00000000
-#define mmSX_PERFCOUNTER2_LO_DEFAULT 0x00000000
-#define mmSX_PERFCOUNTER2_HI_DEFAULT 0x00000000
-#define mmSX_PERFCOUNTER3_LO_DEFAULT 0x00000000
-#define mmSX_PERFCOUNTER3_HI_DEFAULT 0x00000000
-#define mmGDS_PERFCOUNTER0_LO_DEFAULT 0x00000000
-#define mmGDS_PERFCOUNTER0_HI_DEFAULT 0x00000000
-#define mmGDS_PERFCOUNTER1_LO_DEFAULT 0x00000000
-#define mmGDS_PERFCOUNTER1_HI_DEFAULT 0x00000000
-#define mmGDS_PERFCOUNTER2_LO_DEFAULT 0x00000000
-#define mmGDS_PERFCOUNTER2_HI_DEFAULT 0x00000000
-#define mmGDS_PERFCOUNTER3_LO_DEFAULT 0x00000000
-#define mmGDS_PERFCOUNTER3_HI_DEFAULT 0x00000000
-#define mmTA_PERFCOUNTER0_LO_DEFAULT 0x00000000
-#define mmTA_PERFCOUNTER0_HI_DEFAULT 0x00000000
-#define mmTA_PERFCOUNTER1_LO_DEFAULT 0x00000000
-#define mmTA_PERFCOUNTER1_HI_DEFAULT 0x00000000
-#define mmTD_PERFCOUNTER0_LO_DEFAULT 0x00000000
-#define mmTD_PERFCOUNTER0_HI_DEFAULT 0x00000000
-#define mmTD_PERFCOUNTER1_LO_DEFAULT 0x00000000
-#define mmTD_PERFCOUNTER1_HI_DEFAULT 0x00000000
-#define mmTCP_PERFCOUNTER0_LO_DEFAULT 0x00000000
-#define mmTCP_PERFCOUNTER0_HI_DEFAULT 0x00000000
-#define mmTCP_PERFCOUNTER1_LO_DEFAULT 0x00000000
-#define mmTCP_PERFCOUNTER1_HI_DEFAULT 0x00000000
-#define mmTCP_PERFCOUNTER2_LO_DEFAULT 0x00000000
-#define mmTCP_PERFCOUNTER2_HI_DEFAULT 0x00000000
-#define mmTCP_PERFCOUNTER3_LO_DEFAULT 0x00000000
-#define mmTCP_PERFCOUNTER3_HI_DEFAULT 0x00000000
-#define mmTCC_PERFCOUNTER0_LO_DEFAULT 0x00000000
-#define mmTCC_PERFCOUNTER0_HI_DEFAULT 0x00000000
-#define mmTCC_PERFCOUNTER1_LO_DEFAULT 0x00000000
-#define mmTCC_PERFCOUNTER1_HI_DEFAULT 0x00000000
-#define mmTCC_PERFCOUNTER2_LO_DEFAULT 0x00000000
-#define mmTCC_PERFCOUNTER2_HI_DEFAULT 0x00000000
-#define mmTCC_PERFCOUNTER3_LO_DEFAULT 0x00000000
-#define mmTCC_PERFCOUNTER3_HI_DEFAULT 0x00000000
-#define mmTCA_PERFCOUNTER0_LO_DEFAULT 0x00000000
-#define mmTCA_PERFCOUNTER0_HI_DEFAULT 0x00000000
-#define mmTCA_PERFCOUNTER1_LO_DEFAULT 0x00000000
-#define mmTCA_PERFCOUNTER1_HI_DEFAULT 0x00000000
-#define mmTCA_PERFCOUNTER2_LO_DEFAULT 0x00000000
-#define mmTCA_PERFCOUNTER2_HI_DEFAULT 0x00000000
-#define mmTCA_PERFCOUNTER3_LO_DEFAULT 0x00000000
-#define mmTCA_PERFCOUNTER3_HI_DEFAULT 0x00000000
-#define mmCB_PERFCOUNTER0_LO_DEFAULT 0x00000000
-#define mmCB_PERFCOUNTER0_HI_DEFAULT 0x00000000
-#define mmCB_PERFCOUNTER1_LO_DEFAULT 0x00000000
-#define mmCB_PERFCOUNTER1_HI_DEFAULT 0x00000000
-#define mmCB_PERFCOUNTER2_LO_DEFAULT 0x00000000
-#define mmCB_PERFCOUNTER2_HI_DEFAULT 0x00000000
-#define mmCB_PERFCOUNTER3_LO_DEFAULT 0x00000000
-#define mmCB_PERFCOUNTER3_HI_DEFAULT 0x00000000
-#define mmDB_PERFCOUNTER0_LO_DEFAULT 0x00000000
-#define mmDB_PERFCOUNTER0_HI_DEFAULT 0x00000000
-#define mmDB_PERFCOUNTER1_LO_DEFAULT 0x00000000
-#define mmDB_PERFCOUNTER1_HI_DEFAULT 0x00000000
-#define mmDB_PERFCOUNTER2_LO_DEFAULT 0x00000000
-#define mmDB_PERFCOUNTER2_HI_DEFAULT 0x00000000
-#define mmDB_PERFCOUNTER3_LO_DEFAULT 0x00000000
-#define mmDB_PERFCOUNTER3_HI_DEFAULT 0x00000000
-#define mmRLC_PERFCOUNTER0_LO_DEFAULT 0x00000000
-#define mmRLC_PERFCOUNTER0_HI_DEFAULT 0x00000000
-#define mmRLC_PERFCOUNTER1_LO_DEFAULT 0x00000000
-#define mmRLC_PERFCOUNTER1_HI_DEFAULT 0x00000000
-#define mmRMI_PERFCOUNTER0_LO_DEFAULT 0x00000000
-#define mmRMI_PERFCOUNTER0_HI_DEFAULT 0x00000000
-#define mmRMI_PERFCOUNTER1_LO_DEFAULT 0x00000000
-#define mmRMI_PERFCOUNTER1_HI_DEFAULT 0x00000000
-#define mmRMI_PERFCOUNTER2_LO_DEFAULT 0x00000000
-#define mmRMI_PERFCOUNTER2_HI_DEFAULT 0x00000000
-#define mmRMI_PERFCOUNTER3_LO_DEFAULT 0x00000000
-#define mmRMI_PERFCOUNTER3_HI_DEFAULT 0x00000000
-
-
-// addressBlock: gc_utcl2_atcl2pfcntrdec
-#define mmATC_L2_PERFCOUNTER_LO_DEFAULT 0x00000000
-#define mmATC_L2_PERFCOUNTER_HI_DEFAULT 0x00000000
-
-
-// addressBlock: gc_utcl2_vml2prdec
-#define mmMC_VM_L2_PERFCOUNTER_LO_DEFAULT 0x00000000
-#define mmMC_VM_L2_PERFCOUNTER_HI_DEFAULT 0x00000000
-
-
-// addressBlock: gc_perfsdec
-#define mmCPG_PERFCOUNTER1_SELECT_DEFAULT 0x11000401
-#define mmCPG_PERFCOUNTER0_SELECT1_DEFAULT 0x11000401
-#define mmCPG_PERFCOUNTER0_SELECT_DEFAULT 0x11000401
-#define mmCPC_PERFCOUNTER1_SELECT_DEFAULT 0x11000401
-#define mmCPC_PERFCOUNTER0_SELECT1_DEFAULT 0x11000401
-#define mmCPF_PERFCOUNTER1_SELECT_DEFAULT 0x11000401
-#define mmCPF_PERFCOUNTER0_SELECT1_DEFAULT 0x11000401
-#define mmCPF_PERFCOUNTER0_SELECT_DEFAULT 0x11000401
-#define mmCP_PERFMON_CNTL_DEFAULT 0x00000000
-#define mmCPC_PERFCOUNTER0_SELECT_DEFAULT 0x11000401
-#define mmCPF_TC_PERF_COUNTER_WINDOW_SELECT_DEFAULT 0x00000000
-#define mmCPG_TC_PERF_COUNTER_WINDOW_SELECT_DEFAULT 0x00000000
-#define mmCPF_LATENCY_STATS_SELECT_DEFAULT 0x00000000
-#define mmCPG_LATENCY_STATS_SELECT_DEFAULT 0x00000000
-#define mmCPC_LATENCY_STATS_SELECT_DEFAULT 0x00000000
-#define mmCP_DRAW_OBJECT_DEFAULT 0x00000000
-#define mmCP_DRAW_OBJECT_COUNTER_DEFAULT 0x00000000
-#define mmCP_DRAW_WINDOW_MASK_HI_DEFAULT 0x00000000
-#define mmCP_DRAW_WINDOW_HI_DEFAULT 0x00000000
-#define mmCP_DRAW_WINDOW_LO_DEFAULT 0x00000000
-#define mmCP_DRAW_WINDOW_CNTL_DEFAULT 0x00000007
-#define mmGRBM_PERFCOUNTER0_SELECT_DEFAULT 0x00000000
-#define mmGRBM_PERFCOUNTER1_SELECT_DEFAULT 0x00000000
-#define mmGRBM_SE0_PERFCOUNTER_SELECT_DEFAULT 0x00000000
-#define mmGRBM_SE1_PERFCOUNTER_SELECT_DEFAULT 0x00000000
-#define mmGRBM_SE2_PERFCOUNTER_SELECT_DEFAULT 0x00000000
-#define mmGRBM_SE3_PERFCOUNTER_SELECT_DEFAULT 0x00000000
-#define mmWD_PERFCOUNTER0_SELECT_DEFAULT 0x00000000
-#define mmWD_PERFCOUNTER1_SELECT_DEFAULT 0x00000000
-#define mmWD_PERFCOUNTER2_SELECT_DEFAULT 0x00000000
-#define mmWD_PERFCOUNTER3_SELECT_DEFAULT 0x00000000
-#define mmIA_PERFCOUNTER0_SELECT_DEFAULT 0x00000000
-#define mmIA_PERFCOUNTER1_SELECT_DEFAULT 0x00000000
-#define mmIA_PERFCOUNTER2_SELECT_DEFAULT 0x00000000
-#define mmIA_PERFCOUNTER3_SELECT_DEFAULT 0x00000000
-#define mmIA_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000
-#define mmVGT_PERFCOUNTER0_SELECT_DEFAULT 0x00000000
-#define mmVGT_PERFCOUNTER1_SELECT_DEFAULT 0x00000000
-#define mmVGT_PERFCOUNTER2_SELECT_DEFAULT 0x00000000
-#define mmVGT_PERFCOUNTER3_SELECT_DEFAULT 0x00000000
-#define mmVGT_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000
-#define mmVGT_PERFCOUNTER1_SELECT1_DEFAULT 0x00000000
-#define mmVGT_PERFCOUNTER_SEID_MASK_DEFAULT 0x00000000
-#define mmPA_SU_PERFCOUNTER0_SELECT_DEFAULT 0x00000000
-#define mmPA_SU_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000
-#define mmPA_SU_PERFCOUNTER1_SELECT_DEFAULT 0x00000000
-#define mmPA_SU_PERFCOUNTER1_SELECT1_DEFAULT 0x00000000
-#define mmPA_SU_PERFCOUNTER2_SELECT_DEFAULT 0x00000000
-#define mmPA_SU_PERFCOUNTER3_SELECT_DEFAULT 0x00000000
-#define mmPA_SC_PERFCOUNTER0_SELECT_DEFAULT 0x00000000
-#define mmPA_SC_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000
-#define mmPA_SC_PERFCOUNTER1_SELECT_DEFAULT 0x00000000
-#define mmPA_SC_PERFCOUNTER2_SELECT_DEFAULT 0x00000000
-#define mmPA_SC_PERFCOUNTER3_SELECT_DEFAULT 0x00000000
-#define mmPA_SC_PERFCOUNTER4_SELECT_DEFAULT 0x00000000
-#define mmPA_SC_PERFCOUNTER5_SELECT_DEFAULT 0x00000000
-#define mmPA_SC_PERFCOUNTER6_SELECT_DEFAULT 0x00000000
-#define mmPA_SC_PERFCOUNTER7_SELECT_DEFAULT 0x00000000
-#define mmSPI_PERFCOUNTER0_SELECT_DEFAULT 0x000fffff
-#define mmSPI_PERFCOUNTER1_SELECT_DEFAULT 0x000fffff
-#define mmSPI_PERFCOUNTER2_SELECT_DEFAULT 0x000fffff
-#define mmSPI_PERFCOUNTER3_SELECT_DEFAULT 0x000fffff
-#define mmSPI_PERFCOUNTER0_SELECT1_DEFAULT 0x000fffff
-#define mmSPI_PERFCOUNTER1_SELECT1_DEFAULT 0x000fffff
-#define mmSPI_PERFCOUNTER2_SELECT1_DEFAULT 0x000fffff
-#define mmSPI_PERFCOUNTER3_SELECT1_DEFAULT 0x000fffff
-#define mmSPI_PERFCOUNTER4_SELECT_DEFAULT 0x000000ff
-#define mmSPI_PERFCOUNTER5_SELECT_DEFAULT 0x000000ff
-#define mmSPI_PERFCOUNTER_BINS_DEFAULT 0xfcb87430
-#define mmSQ_PERFCOUNTER0_SELECT_DEFAULT 0x0f0ff000
-#define mmSQ_PERFCOUNTER1_SELECT_DEFAULT 0x0f0ff000
-#define mmSQ_PERFCOUNTER2_SELECT_DEFAULT 0x0f0ff000
-#define mmSQ_PERFCOUNTER3_SELECT_DEFAULT 0x0f0ff000
-#define mmSQ_PERFCOUNTER4_SELECT_DEFAULT 0x0f0ff000
-#define mmSQ_PERFCOUNTER5_SELECT_DEFAULT 0x0f0ff000
-#define mmSQ_PERFCOUNTER6_SELECT_DEFAULT 0x0f0ff000
-#define mmSQ_PERFCOUNTER7_SELECT_DEFAULT 0x0f0ff000
-#define mmSQ_PERFCOUNTER8_SELECT_DEFAULT 0x0f0ff000
-#define mmSQ_PERFCOUNTER9_SELECT_DEFAULT 0x0f0ff000
-#define mmSQ_PERFCOUNTER10_SELECT_DEFAULT 0x0f0ff000
-#define mmSQ_PERFCOUNTER11_SELECT_DEFAULT 0x0f0ff000
-#define mmSQ_PERFCOUNTER12_SELECT_DEFAULT 0x0f0ff000
-#define mmSQ_PERFCOUNTER13_SELECT_DEFAULT 0x0f0ff000
-#define mmSQ_PERFCOUNTER14_SELECT_DEFAULT 0x0f0ff000
-#define mmSQ_PERFCOUNTER15_SELECT_DEFAULT 0x0f0ff000
-#define mmSQ_PERFCOUNTER_CTRL_DEFAULT 0x00000000
-#define mmSQ_PERFCOUNTER_MASK_DEFAULT 0xffffffff
-#define mmSQ_PERFCOUNTER_CTRL2_DEFAULT 0x00000000
-#define mmSX_PERFCOUNTER0_SELECT_DEFAULT 0x00000000
-#define mmSX_PERFCOUNTER1_SELECT_DEFAULT 0x00000000
-#define mmSX_PERFCOUNTER2_SELECT_DEFAULT 0x00000000
-#define mmSX_PERFCOUNTER3_SELECT_DEFAULT 0x00000000
-#define mmSX_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000
-#define mmSX_PERFCOUNTER1_SELECT1_DEFAULT 0x00000000
-#define mmGDS_PERFCOUNTER0_SELECT_DEFAULT 0x00000000
-#define mmGDS_PERFCOUNTER1_SELECT_DEFAULT 0x00000000
-#define mmGDS_PERFCOUNTER2_SELECT_DEFAULT 0x00000000
-#define mmGDS_PERFCOUNTER3_SELECT_DEFAULT 0x00000000
-#define mmGDS_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000
-#define mmTA_PERFCOUNTER0_SELECT_DEFAULT 0x00000000
-#define mmTA_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000
-#define mmTA_PERFCOUNTER1_SELECT_DEFAULT 0x00000000
-#define mmTD_PERFCOUNTER0_SELECT_DEFAULT 0x00000000
-#define mmTD_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000
-#define mmTD_PERFCOUNTER1_SELECT_DEFAULT 0x00000000
-#define mmTCP_PERFCOUNTER0_SELECT_DEFAULT 0x000fffff
-#define mmTCP_PERFCOUNTER0_SELECT1_DEFAULT 0x000fffff
-#define mmTCP_PERFCOUNTER1_SELECT_DEFAULT 0x000fffff
-#define mmTCP_PERFCOUNTER1_SELECT1_DEFAULT 0x000fffff
-#define mmTCP_PERFCOUNTER2_SELECT_DEFAULT 0x000003ff
-#define mmTCP_PERFCOUNTER3_SELECT_DEFAULT 0x000003ff
-#define mmTCC_PERFCOUNTER0_SELECT_DEFAULT 0x000fffff
-#define mmTCC_PERFCOUNTER0_SELECT1_DEFAULT 0x000fffff
-#define mmTCC_PERFCOUNTER1_SELECT_DEFAULT 0x000fffff
-#define mmTCC_PERFCOUNTER1_SELECT1_DEFAULT 0x000fffff
-#define mmTCC_PERFCOUNTER2_SELECT_DEFAULT 0x000003ff
-#define mmTCC_PERFCOUNTER3_SELECT_DEFAULT 0x000003ff
-#define mmTCA_PERFCOUNTER0_SELECT_DEFAULT 0x000fffff
-#define mmTCA_PERFCOUNTER0_SELECT1_DEFAULT 0x000fffff
-#define mmTCA_PERFCOUNTER1_SELECT_DEFAULT 0x000fffff
-#define mmTCA_PERFCOUNTER1_SELECT1_DEFAULT 0x000fffff
-#define mmTCA_PERFCOUNTER2_SELECT_DEFAULT 0x000003ff
-#define mmTCA_PERFCOUNTER3_SELECT_DEFAULT 0x000003ff
-#define mmCB_PERFCOUNTER_FILTER_DEFAULT 0x00000000
-#define mmCB_PERFCOUNTER0_SELECT_DEFAULT 0x00000000
-#define mmCB_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000
-#define mmCB_PERFCOUNTER1_SELECT_DEFAULT 0x00000000
-#define mmCB_PERFCOUNTER2_SELECT_DEFAULT 0x00000000
-#define mmCB_PERFCOUNTER3_SELECT_DEFAULT 0x00000000
-#define mmDB_PERFCOUNTER0_SELECT_DEFAULT 0x00000000
-#define mmDB_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000
-#define mmDB_PERFCOUNTER1_SELECT_DEFAULT 0x00000000
-#define mmDB_PERFCOUNTER1_SELECT1_DEFAULT 0x00000000
-#define mmDB_PERFCOUNTER2_SELECT_DEFAULT 0x00000000
-#define mmDB_PERFCOUNTER3_SELECT_DEFAULT 0x00000000
-#define mmRLC_SPM_PERFMON_CNTL_DEFAULT 0x00000000
-#define mmRLC_SPM_PERFMON_RING_BASE_LO_DEFAULT 0x00000000
-#define mmRLC_SPM_PERFMON_RING_BASE_HI_DEFAULT 0x00000000
-#define mmRLC_SPM_PERFMON_RING_SIZE_DEFAULT 0x00000000
-#define mmRLC_SPM_PERFMON_SEGMENT_SIZE_DEFAULT 0x00000000
-#define mmRLC_SPM_SE_MUXSEL_ADDR_DEFAULT 0x00000000
-#define mmRLC_SPM_SE_MUXSEL_DATA_DEFAULT 0x00000000
-#define mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000
-#define mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000
-#define mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000
-#define mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000
-#define mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000
-#define mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000
-#define mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000
-#define mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000
-#define mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000
-#define mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000
-#define mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000
-#define mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000
-#define mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000
-#define mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000
-#define mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000
-#define mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000
-#define mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000
-#define mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000
-#define mmRLC_SPM_GLOBAL_MUXSEL_ADDR_DEFAULT 0x00000000
-#define mmRLC_SPM_GLOBAL_MUXSEL_DATA_DEFAULT 0x00000000
-#define mmRLC_SPM_RING_RDPTR_DEFAULT 0x00000000
-#define mmRLC_SPM_SEGMENT_THRESHOLD_DEFAULT 0x00000000
-#define mmRLC_SPM_RMI_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000
-#define mmRLC_PERFMON_CLK_CNTL_DEFAULT 0x00000001
-#define mmRLC_PERFMON_CNTL_DEFAULT 0x00000000
-#define mmRLC_PERFCOUNTER0_SELECT_DEFAULT 0x00000000
-#define mmRLC_PERFCOUNTER1_SELECT_DEFAULT 0x00000000
-#define mmRLC_GPU_IOV_PERF_CNT_CNTL_DEFAULT 0x00000000
-#define mmRLC_GPU_IOV_PERF_CNT_WR_ADDR_DEFAULT 0x00000000
-#define mmRLC_GPU_IOV_PERF_CNT_WR_DATA_DEFAULT 0x00000000
-#define mmRLC_GPU_IOV_PERF_CNT_RD_ADDR_DEFAULT 0x00000000
-#define mmRLC_GPU_IOV_PERF_CNT_RD_DATA_DEFAULT 0x00000000
-#define mmRMI_PERFCOUNTER0_SELECT_DEFAULT 0x00000000
-#define mmRMI_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000
-#define mmRMI_PERFCOUNTER1_SELECT_DEFAULT 0x00000000
-#define mmRMI_PERFCOUNTER2_SELECT_DEFAULT 0x00000000
-#define mmRMI_PERFCOUNTER2_SELECT1_DEFAULT 0x00000000
-#define mmRMI_PERFCOUNTER3_SELECT_DEFAULT 0x00000000
-#define mmRMI_PERF_COUNTER_CNTL_DEFAULT 0x00080240
-
-
-// addressBlock: gc_utcl2_atcl2pfcntldec
-#define mmATC_L2_PERFCOUNTER0_CFG_DEFAULT 0x00000000
-#define mmATC_L2_PERFCOUNTER1_CFG_DEFAULT 0x00000000
-#define mmATC_L2_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000
-
-
-// addressBlock: gc_utcl2_vml2pldec
-#define mmMC_VM_L2_PERFCOUNTER0_CFG_DEFAULT 0x00000000
-#define mmMC_VM_L2_PERFCOUNTER1_CFG_DEFAULT 0x00000000
-#define mmMC_VM_L2_PERFCOUNTER2_CFG_DEFAULT 0x00000000
-#define mmMC_VM_L2_PERFCOUNTER3_CFG_DEFAULT 0x00000000
-#define mmMC_VM_L2_PERFCOUNTER4_CFG_DEFAULT 0x00000000
-#define mmMC_VM_L2_PERFCOUNTER5_CFG_DEFAULT 0x00000000
-#define mmMC_VM_L2_PERFCOUNTER6_CFG_DEFAULT 0x00000000
-#define mmMC_VM_L2_PERFCOUNTER7_CFG_DEFAULT 0x00000000
-#define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000
-
-
-// addressBlock: gc_rlcpdec
-#define mmRLC_CNTL_DEFAULT 0x00000001
-#define mmRLC_STAT_DEFAULT 0x00000000
-#define mmRLC_SAFE_MODE_DEFAULT 0x00000000
-#define mmRLC_MEM_SLP_CNTL_DEFAULT 0x00020200
-#define mmSMU_RLC_RESPONSE_DEFAULT 0x00000000
-#define mmRLC_RLCV_SAFE_MODE_DEFAULT 0x00000000
-#define mmRLC_SMU_SAFE_MODE_DEFAULT 0x00000000
-#define mmRLC_RLCV_COMMAND_DEFAULT 0x00000000
-#define mmRLC_REFCLOCK_TIMESTAMP_LSB_DEFAULT 0x00000000
-#define mmRLC_REFCLOCK_TIMESTAMP_MSB_DEFAULT 0x00000000
-#define mmRLC_GPM_TIMER_INT_0_DEFAULT 0x00000000
-#define mmRLC_GPM_TIMER_INT_1_DEFAULT 0x00000000
-#define mmRLC_GPM_TIMER_INT_2_DEFAULT 0x00000000
-#define mmRLC_GPM_TIMER_CTRL_DEFAULT 0x00000000
-#define mmRLC_LB_CNTR_MAX_DEFAULT 0xffffffff
-#define mmRLC_GPM_TIMER_STAT_DEFAULT 0x00000000
-#define mmRLC_GPM_TIMER_INT_3_DEFAULT 0x00000000
-#define mmRLC_SERDES_WR_NONCU_MASTER_MASK_1_DEFAULT 0x00000000
-#define mmRLC_SERDES_NONCU_MASTER_BUSY_1_DEFAULT 0x00000000
-#define mmRLC_INT_STAT_DEFAULT 0x00000000
-#define mmRLC_LB_CNTL_DEFAULT 0x00000010
-#define mmRLC_MGCG_CTRL_DEFAULT 0x00018800
-#define mmRLC_LB_CNTR_INIT_DEFAULT 0x00000000
-#define mmRLC_LOAD_BALANCE_CNTR_DEFAULT 0x00000000
-#define mmRLC_JUMP_TABLE_RESTORE_DEFAULT 0x00000000
-#define mmRLC_PG_DELAY_2_DEFAULT 0x00000004
-#define mmRLC_GPU_CLOCK_COUNT_LSB_DEFAULT 0x00000000
-#define mmRLC_GPU_CLOCK_COUNT_MSB_DEFAULT 0x00000000
-#define mmRLC_CAPTURE_GPU_CLOCK_COUNT_DEFAULT 0x00000000
-#define mmRLC_UCODE_CNTL_DEFAULT 0x00000000
-#define mmRLC_GPM_THREAD_RESET_DEFAULT 0x0000000f
-#define mmRLC_GPM_CP_DMA_COMPLETE_T0_DEFAULT 0x00000000
-#define mmRLC_GPM_CP_DMA_COMPLETE_T1_DEFAULT 0x00000000
-#define mmRLC_FIREWALL_VIOLATION_DEFAULT 0x00000000
-#define mmRLC_GPM_STAT_DEFAULT 0x00100016
-#define mmRLC_GPU_CLOCK_32_RES_SEL_DEFAULT 0x00000000
-#define mmRLC_GPU_CLOCK_32_DEFAULT 0x00000000
-#define mmRLC_PG_CNTL_DEFAULT 0x00000000
-#define mmRLC_GPM_THREAD_PRIORITY_DEFAULT 0x08080808
-#define mmRLC_GPM_THREAD_ENABLE_DEFAULT 0x00000001
-#define mmRLC_CGTT_MGCG_OVERRIDE_DEFAULT 0xffffffff
-#define mmRLC_CGCG_CGLS_CTRL_DEFAULT 0x0001003c
-#define mmRLC_CGCG_RAMP_CTRL_DEFAULT 0x00021711
-#define mmRLC_DYN_PG_STATUS_DEFAULT 0xffffffff
-#define mmRLC_DYN_PG_REQUEST_DEFAULT 0xffffffff
-#define mmRLC_PG_DELAY_DEFAULT 0x00101010
-#define mmRLC_CU_STATUS_DEFAULT 0x00000000
-#define mmRLC_LB_INIT_CU_MASK_DEFAULT 0xffffffff
-#define mmRLC_LB_ALWAYS_ACTIVE_CU_MASK_DEFAULT 0x00000001
-#define mmRLC_LB_PARAMS_DEFAULT 0x00601008
-#define mmRLC_THREAD1_DELAY_DEFAULT 0x00400401
-#define mmRLC_PG_ALWAYS_ON_CU_MASK_DEFAULT 0x00000003
-#define mmRLC_MAX_PG_CU_DEFAULT 0x0000000b
-#define mmRLC_AUTO_PG_CTRL_DEFAULT 0x00000000
-#define mmRLC_SMU_GRBM_REG_SAVE_CTRL_DEFAULT 0x00000000
-#define mmRLC_SERDES_RD_MASTER_INDEX_DEFAULT 0x00000000
-#define mmRLC_SERDES_RD_DATA_0_DEFAULT 0x00000000
-#define mmRLC_SERDES_RD_DATA_1_DEFAULT 0x00000000
-#define mmRLC_SERDES_RD_DATA_2_DEFAULT 0x00000000
-#define mmRLC_SERDES_WR_CU_MASTER_MASK_DEFAULT 0x00000000
-#define mmRLC_SERDES_WR_NONCU_MASTER_MASK_DEFAULT 0x00000000
-#define mmRLC_SERDES_WR_CTRL_DEFAULT 0x00000000
-#define mmRLC_SERDES_WR_DATA_DEFAULT 0x00000000
-#define mmRLC_SERDES_CU_MASTER_BUSY_DEFAULT 0x00000000
-#define mmRLC_SERDES_NONCU_MASTER_BUSY_DEFAULT 0x00000000
-#define mmRLC_GPM_GENERAL_0_DEFAULT 0x00000000
-#define mmRLC_GPM_GENERAL_1_DEFAULT 0x00000000
-#define mmRLC_GPM_GENERAL_2_DEFAULT 0x00000000
-#define mmRLC_GPM_GENERAL_3_DEFAULT 0x00000000
-#define mmRLC_GPM_GENERAL_4_DEFAULT 0x00000000
-#define mmRLC_GPM_GENERAL_5_DEFAULT 0x00000000
-#define mmRLC_GPM_GENERAL_6_DEFAULT 0x00000000
-#define mmRLC_GPM_GENERAL_7_DEFAULT 0x00000000
-#define mmRLC_GPM_SCRATCH_ADDR_DEFAULT 0x00000000
-#define mmRLC_GPM_SCRATCH_DATA_DEFAULT 0x00000000
-#define mmRLC_STATIC_PG_STATUS_DEFAULT 0xffffffff
-#define mmRLC_SPM_MC_CNTL_DEFAULT 0x00000000
-#define mmRLC_SPM_INT_CNTL_DEFAULT 0x00000000
-#define mmRLC_SPM_INT_STATUS_DEFAULT 0x00000000
-#define mmRLC_SMU_MESSAGE_DEFAULT 0x00000000
-#define mmRLC_GPM_LOG_SIZE_DEFAULT 0x00000000
-#define mmRLC_PG_DELAY_3_DEFAULT 0x00000000
-#define mmRLC_GPR_REG1_DEFAULT 0x00000000
-#define mmRLC_GPR_REG2_DEFAULT 0x00000000
-#define mmRLC_GPM_LOG_CONT_DEFAULT 0x00000000
-#define mmRLC_GPM_INT_DISABLE_TH0_DEFAULT 0x00000000
-#define mmRLC_GPM_INT_DISABLE_TH1_DEFAULT 0x00000000
-#define mmRLC_GPM_INT_FORCE_TH0_DEFAULT 0x00000000
-#define mmRLC_GPM_INT_FORCE_TH1_DEFAULT 0x00000000
-#define mmRLC_SRM_CNTL_DEFAULT 0x00000002
-#define mmRLC_SRM_ARAM_ADDR_DEFAULT 0x00000000
-#define mmRLC_SRM_ARAM_DATA_DEFAULT 0x00000000
-#define mmRLC_SRM_DRAM_ADDR_DEFAULT 0x00000000
-#define mmRLC_SRM_DRAM_DATA_DEFAULT 0x00000000
-#define mmRLC_SRM_GPM_COMMAND_DEFAULT 0x00000000
-#define mmRLC_SRM_GPM_COMMAND_STATUS_DEFAULT 0x00000000
-#define mmRLC_SRM_RLCV_COMMAND_DEFAULT 0x00000000
-#define mmRLC_SRM_RLCV_COMMAND_STATUS_DEFAULT 0x00000000
-#define mmRLC_SRM_INDEX_CNTL_ADDR_0_DEFAULT 0x00000000
-#define mmRLC_SRM_INDEX_CNTL_ADDR_1_DEFAULT 0x00000000
-#define mmRLC_SRM_INDEX_CNTL_ADDR_2_DEFAULT 0x00000000
-#define mmRLC_SRM_INDEX_CNTL_ADDR_3_DEFAULT 0x00000000
-#define mmRLC_SRM_INDEX_CNTL_ADDR_4_DEFAULT 0x00000000
-#define mmRLC_SRM_INDEX_CNTL_ADDR_5_DEFAULT 0x00000000
-#define mmRLC_SRM_INDEX_CNTL_ADDR_6_DEFAULT 0x00000000
-#define mmRLC_SRM_INDEX_CNTL_ADDR_7_DEFAULT 0x00000000
-#define mmRLC_SRM_INDEX_CNTL_DATA_0_DEFAULT 0x00000000
-#define mmRLC_SRM_INDEX_CNTL_DATA_1_DEFAULT 0x00000000
-#define mmRLC_SRM_INDEX_CNTL_DATA_2_DEFAULT 0x00000000
-#define mmRLC_SRM_INDEX_CNTL_DATA_3_DEFAULT 0x00000000
-#define mmRLC_SRM_INDEX_CNTL_DATA_4_DEFAULT 0x00000000
-#define mmRLC_SRM_INDEX_CNTL_DATA_5_DEFAULT 0x00000000
-#define mmRLC_SRM_INDEX_CNTL_DATA_6_DEFAULT 0x00000000
-#define mmRLC_SRM_INDEX_CNTL_DATA_7_DEFAULT 0x00000000
-#define mmRLC_SRM_STAT_DEFAULT 0x00000000
-#define mmRLC_SRM_GPM_ABORT_DEFAULT 0x00000000
-#define mmRLC_CSIB_ADDR_LO_DEFAULT 0x00000000
-#define mmRLC_CSIB_ADDR_HI_DEFAULT 0x00000000
-#define mmRLC_CSIB_LENGTH_DEFAULT 0x00000000
-#define mmRLC_SMU_COMMAND_DEFAULT 0x00000000
-#define mmRLC_CP_SCHEDULERS_DEFAULT 0x58504840
-#define mmRLC_SMU_ARGUMENT_1_DEFAULT 0x00000000
-#define mmRLC_SMU_ARGUMENT_2_DEFAULT 0x00000000
-#define mmRLC_GPM_GENERAL_8_DEFAULT 0x00000000
-#define mmRLC_GPM_GENERAL_9_DEFAULT 0x00000000
-#define mmRLC_GPM_GENERAL_10_DEFAULT 0x00000000
-#define mmRLC_GPM_GENERAL_11_DEFAULT 0x00000000
-#define mmRLC_GPM_GENERAL_12_DEFAULT 0x00000000
-#define mmRLC_GPM_UTCL1_CNTL_0_DEFAULT 0x00000080
-#define mmRLC_GPM_UTCL1_CNTL_1_DEFAULT 0x00000080
-#define mmRLC_GPM_UTCL1_CNTL_2_DEFAULT 0x00000080
-#define mmRLC_SPM_UTCL1_CNTL_DEFAULT 0x00000080
-#define mmRLC_UTCL1_STATUS_2_DEFAULT 0x00000000
-#define mmRLC_LB_THR_CONFIG_2_DEFAULT 0x00000000
-#define mmRLC_LB_THR_CONFIG_3_DEFAULT 0x00000000
-#define mmRLC_LB_THR_CONFIG_4_DEFAULT 0x00000000
-#define mmRLC_SPM_UTCL1_ERROR_1_DEFAULT 0x00000000
-#define mmRLC_SPM_UTCL1_ERROR_2_DEFAULT 0x00000000
-#define mmRLC_GPM_UTCL1_TH0_ERROR_1_DEFAULT 0x00000000
-#define mmRLC_LB_THR_CONFIG_1_DEFAULT 0x00000000
-#define mmRLC_GPM_UTCL1_TH0_ERROR_2_DEFAULT 0x00000000
-#define mmRLC_GPM_UTCL1_TH1_ERROR_1_DEFAULT 0x00000000
-#define mmRLC_GPM_UTCL1_TH1_ERROR_2_DEFAULT 0x00000000
-#define mmRLC_GPM_UTCL1_TH2_ERROR_1_DEFAULT 0x00000000
-#define mmRLC_GPM_UTCL1_TH2_ERROR_2_DEFAULT 0x00000000
-#define mmRLC_CGCG_CGLS_CTRL_3D_DEFAULT 0x0001003c
-#define mmRLC_CGCG_RAMP_CTRL_3D_DEFAULT 0x00021711
-#define mmRLC_SEMAPHORE_0_DEFAULT 0x00000000
-#define mmRLC_SEMAPHORE_1_DEFAULT 0x00000000
-#define mmRLC_CP_EOF_INT_DEFAULT 0x00000000
-#define mmRLC_CP_EOF_INT_CNT_DEFAULT 0x00000000
-#define mmRLC_SPARE_INT_DEFAULT 0x00000000
-#define mmRLC_PREWALKER_UTCL1_CNTL_DEFAULT 0x00000080
-#define mmRLC_PREWALKER_UTCL1_TRIG_DEFAULT 0x00000000
-#define mmRLC_PREWALKER_UTCL1_ADDR_LSB_DEFAULT 0x00000000
-#define mmRLC_PREWALKER_UTCL1_ADDR_MSB_DEFAULT 0x00000000
-#define mmRLC_PREWALKER_UTCL1_SIZE_LSB_DEFAULT 0x00000000
-#define mmRLC_PREWALKER_UTCL1_SIZE_MSB_DEFAULT 0x00000000
-#define mmRLC_DSM_TRIG_DEFAULT 0x00000000
-#define mmRLC_UTCL1_STATUS_DEFAULT 0x00000000
-#define mmRLC_R2I_CNTL_0_DEFAULT 0x00000000
-#define mmRLC_R2I_CNTL_1_DEFAULT 0x00000000
-#define mmRLC_R2I_CNTL_2_DEFAULT 0x00000000
-#define mmRLC_R2I_CNTL_3_DEFAULT 0x00000000
-#define mmRLC_UTCL2_CNTL_DEFAULT 0x00000000
-#define mmRLC_LBPW_CU_STAT_DEFAULT 0x00000000
-#define mmRLC_DS_CNTL_DEFAULT 0x00030003
-#define mmRLC_RLCV_SPARE_INT_DEFAULT 0x00000000
-
-
-// addressBlock: gc_pwrdec
-#define mmCGTS_SM_CTRL_REG_DEFAULT 0x00600200
-#define mmCGTS_RD_CTRL_REG_DEFAULT 0x00000000
-#define mmCGTS_RD_REG_DEFAULT 0x00000000
-#define mmCGTS_TCC_DISABLE_DEFAULT 0x00000000
-#define mmCGTS_USER_TCC_DISABLE_DEFAULT 0x00000000
-#define mmCGTS_CU0_SP0_CTRL_REG_DEFAULT 0x00010000
-#define mmCGTS_CU0_LDS_SQ_CTRL_REG_DEFAULT 0x00030002
-#define mmCGTS_CU0_TA_SQC_CTRL_REG_DEFAULT 0x00040007
-#define mmCGTS_CU0_SP1_CTRL_REG_DEFAULT 0x00060005
-#define mmCGTS_CU0_TD_TCP_CTRL_REG_DEFAULT 0x00090008
-#define mmCGTS_CU1_SP0_CTRL_REG_DEFAULT 0x00010000
-#define mmCGTS_CU1_LDS_SQ_CTRL_REG_DEFAULT 0x00030002
-#define mmCGTS_CU1_TA_SQC_CTRL_REG_DEFAULT 0x00000007
-#define mmCGTS_CU1_SP1_CTRL_REG_DEFAULT 0x00060005
-#define mmCGTS_CU1_TD_TCP_CTRL_REG_DEFAULT 0x00090008
-#define mmCGTS_CU2_SP0_CTRL_REG_DEFAULT 0x00010000
-#define mmCGTS_CU2_LDS_SQ_CTRL_REG_DEFAULT 0x00030002
-#define mmCGTS_CU2_TA_SQC_CTRL_REG_DEFAULT 0x00000007
-#define mmCGTS_CU2_SP1_CTRL_REG_DEFAULT 0x00060005
-#define mmCGTS_CU2_TD_TCP_CTRL_REG_DEFAULT 0x00090008
-#define mmCGTS_CU3_SP0_CTRL_REG_DEFAULT 0x00010000
-#define mmCGTS_CU3_LDS_SQ_CTRL_REG_DEFAULT 0x00030002
-#define mmCGTS_CU3_TA_SQC_CTRL_REG_DEFAULT 0x00040007
-#define mmCGTS_CU3_SP1_CTRL_REG_DEFAULT 0x00060005
-#define mmCGTS_CU3_TD_TCP_CTRL_REG_DEFAULT 0x00090008
-#define mmCGTS_CU4_SP0_CTRL_REG_DEFAULT 0x00010000
-#define mmCGTS_CU4_LDS_SQ_CTRL_REG_DEFAULT 0x00030002
-#define mmCGTS_CU4_TA_SQC_CTRL_REG_DEFAULT 0x00000007
-#define mmCGTS_CU4_SP1_CTRL_REG_DEFAULT 0x00060005
-#define mmCGTS_CU4_TD_TCP_CTRL_REG_DEFAULT 0x00090008
-#define mmCGTS_CU5_SP0_CTRL_REG_DEFAULT 0x00010000
-#define mmCGTS_CU5_LDS_SQ_CTRL_REG_DEFAULT 0x00030002
-#define mmCGTS_CU5_TA_SQC_CTRL_REG_DEFAULT 0x00000007
-#define mmCGTS_CU5_SP1_CTRL_REG_DEFAULT 0x00060005
-#define mmCGTS_CU5_TD_TCP_CTRL_REG_DEFAULT 0x00090008
-#define mmCGTS_CU6_SP0_CTRL_REG_DEFAULT 0x00010000
-#define mmCGTS_CU6_LDS_SQ_CTRL_REG_DEFAULT 0x00030002
-#define mmCGTS_CU6_TA_SQC_CTRL_REG_DEFAULT 0x00040007
-#define mmCGTS_CU6_SP1_CTRL_REG_DEFAULT 0x00060005
-#define mmCGTS_CU6_TD_TCP_CTRL_REG_DEFAULT 0x00090008
-#define mmCGTS_CU7_SP0_CTRL_REG_DEFAULT 0x00010000
-#define mmCGTS_CU7_LDS_SQ_CTRL_REG_DEFAULT 0x00030002
-#define mmCGTS_CU7_TA_SQC_CTRL_REG_DEFAULT 0x00000007
-#define mmCGTS_CU7_SP1_CTRL_REG_DEFAULT 0x00060005
-#define mmCGTS_CU7_TD_TCP_CTRL_REG_DEFAULT 0x00090008
-#define mmCGTS_CU8_SP0_CTRL_REG_DEFAULT 0x00010000
-#define mmCGTS_CU8_LDS_SQ_CTRL_REG_DEFAULT 0x00030002
-#define mmCGTS_CU8_TA_SQC_CTRL_REG_DEFAULT 0x00000007
-#define mmCGTS_CU8_SP1_CTRL_REG_DEFAULT 0x00060005
-#define mmCGTS_CU8_TD_TCP_CTRL_REG_DEFAULT 0x00090008
-#define mmCGTS_CU9_SP0_CTRL_REG_DEFAULT 0x00010000
-#define mmCGTS_CU9_LDS_SQ_CTRL_REG_DEFAULT 0x00030002
-#define mmCGTS_CU9_TA_SQC_CTRL_REG_DEFAULT 0x00040007
-#define mmCGTS_CU9_SP1_CTRL_REG_DEFAULT 0x00060005
-#define mmCGTS_CU9_TD_TCP_CTRL_REG_DEFAULT 0x00090008
-#define mmCGTS_CU10_SP0_CTRL_REG_DEFAULT 0x00010000
-#define mmCGTS_CU10_LDS_SQ_CTRL_REG_DEFAULT 0x00030002
-#define mmCGTS_CU10_TA_SQC_CTRL_REG_DEFAULT 0x00000007
-#define mmCGTS_CU10_SP1_CTRL_REG_DEFAULT 0x00060005
-#define mmCGTS_CU10_TD_TCP_CTRL_REG_DEFAULT 0x00090008
-#define mmCGTS_CU11_SP0_CTRL_REG_DEFAULT 0x00010000
-#define mmCGTS_CU11_LDS_SQ_CTRL_REG_DEFAULT 0x00030002
-#define mmCGTS_CU11_TA_SQC_CTRL_REG_DEFAULT 0x00000007
-#define mmCGTS_CU11_SP1_CTRL_REG_DEFAULT 0x00060005
-#define mmCGTS_CU11_TD_TCP_CTRL_REG_DEFAULT 0x00090008
-#define mmCGTS_CU12_SP0_CTRL_REG_DEFAULT 0x00010000
-#define mmCGTS_CU12_LDS_SQ_CTRL_REG_DEFAULT 0x00030002
-#define mmCGTS_CU12_TA_SQC_CTRL_REG_DEFAULT 0x00040007
-#define mmCGTS_CU12_SP1_CTRL_REG_DEFAULT 0x00060005
-#define mmCGTS_CU12_TD_TCP_CTRL_REG_DEFAULT 0x00090008
-#define mmCGTS_CU13_SP0_CTRL_REG_DEFAULT 0x00010000
-#define mmCGTS_CU13_LDS_SQ_CTRL_REG_DEFAULT 0x00030002
-#define mmCGTS_CU13_TA_SQC_CTRL_REG_DEFAULT 0x00000007
-#define mmCGTS_CU13_SP1_CTRL_REG_DEFAULT 0x00060005
-#define mmCGTS_CU13_TD_TCP_CTRL_REG_DEFAULT 0x00090008
-#define mmCGTS_CU14_SP0_CTRL_REG_DEFAULT 0x00010000
-#define mmCGTS_CU14_LDS_SQ_CTRL_REG_DEFAULT 0x00030002
-#define mmCGTS_CU14_TA_SQC_CTRL_REG_DEFAULT 0x00000007
-#define mmCGTS_CU14_SP1_CTRL_REG_DEFAULT 0x00060005
-#define mmCGTS_CU14_TD_TCP_CTRL_REG_DEFAULT 0x00090008
-#define mmCGTS_CU15_SP0_CTRL_REG_DEFAULT 0x00010000
-#define mmCGTS_CU15_LDS_SQ_CTRL_REG_DEFAULT 0x00030002
-#define mmCGTS_CU15_TA_SQC_CTRL_REG_DEFAULT 0x00040007
-#define mmCGTS_CU15_SP1_CTRL_REG_DEFAULT 0x00060005
-#define mmCGTS_CU15_TD_TCP_CTRL_REG_DEFAULT 0x00090008
-#define mmCGTS_CU0_TCPI_CTRL_REG_DEFAULT 0x0000000a
-#define mmCGTS_CU1_TCPI_CTRL_REG_DEFAULT 0x00000001
-#define mmCGTS_CU2_TCPI_CTRL_REG_DEFAULT 0x0000000a
-#define mmCGTS_CU3_TCPI_CTRL_REG_DEFAULT 0x0000000a
-#define mmCGTS_CU4_TCPI_CTRL_REG_DEFAULT 0x0000000a
-#define mmCGTS_CU5_TCPI_CTRL_REG_DEFAULT 0x0000000a
-#define mmCGTS_CU6_TCPI_CTRL_REG_DEFAULT 0x0000000a
-#define mmCGTS_CU7_TCPI_CTRL_REG_DEFAULT 0x0000000a
-#define mmCGTS_CU8_TCPI_CTRL_REG_DEFAULT 0x0000000a
-#define mmCGTS_CU9_TCPI_CTRL_REG_DEFAULT 0x0000000a
-#define mmCGTS_CU10_TCPI_CTRL_REG_DEFAULT 0x0000000a
-#define mmCGTS_CU11_TCPI_CTRL_REG_DEFAULT 0x0000000a
-#define mmCGTS_CU12_TCPI_CTRL_REG_DEFAULT 0x0000000a
-#define mmCGTS_CU13_TCPI_CTRL_REG_DEFAULT 0x0000000a
-#define mmCGTS_CU14_TCPI_CTRL_REG_DEFAULT 0x0000000a
-#define mmCGTS_CU15_TCPI_CTRL_REG_DEFAULT 0x0000000a
-#define mmCGTT_SPI_CLK_CTRL_DEFAULT 0x00000100
-#define mmCGTT_PC_CLK_CTRL_DEFAULT 0x00000100
-#define mmCGTT_BCI_CLK_CTRL_DEFAULT 0x00000100
-#define mmCGTT_VGT_CLK_CTRL_DEFAULT 0x00018100
-#define mmCGTT_IA_CLK_CTRL_DEFAULT 0x06000100
-#define mmCGTT_WD_CLK_CTRL_DEFAULT 0x00018100
-#define mmCGTT_PA_CLK_CTRL_DEFAULT 0x00000100
-#define mmCGTT_SC_CLK_CTRL0_DEFAULT 0x00000100
-#define mmCGTT_SC_CLK_CTRL1_DEFAULT 0x00000100
-#define mmCGTT_SQ_CLK_CTRL_DEFAULT 0x00000100
-#define mmCGTT_SQG_CLK_CTRL_DEFAULT 0x00000100
-#define mmSQ_ALU_CLK_CTRL_DEFAULT 0x00000000
-#define mmSQ_TEX_CLK_CTRL_DEFAULT 0x00000000
-#define mmSQ_LDS_CLK_CTRL_DEFAULT 0x00000000
-#define mmSQ_POWER_THROTTLE_DEFAULT 0x3fff3fff
-#define mmSQ_POWER_THROTTLE2_DEFAULT 0x18800004
-#define mmCGTT_SX_CLK_CTRL0_DEFAULT 0x00000100
-#define mmCGTT_SX_CLK_CTRL1_DEFAULT 0x00000100
-#define mmCGTT_SX_CLK_CTRL2_DEFAULT 0x00000100
-#define mmCGTT_SX_CLK_CTRL3_DEFAULT 0x00000100
-#define mmCGTT_SX_CLK_CTRL4_DEFAULT 0x00000100
-#define mmTD_CGTT_CTRL_DEFAULT 0x00000100
-#define mmTA_CGTT_CTRL_DEFAULT 0x00000100
-#define mmCGTT_TCPI_CLK_CTRL_DEFAULT 0x00000100
-#define mmCGTT_TCI_CLK_CTRL_DEFAULT 0x00000100
-#define mmCGTT_GDS_CLK_CTRL_DEFAULT 0x00000100
-#define mmDB_CGTT_CLK_CTRL_0_DEFAULT 0x00000100
-#define mmCB_CGTT_SCLK_CTRL_DEFAULT 0x00000100
-#define mmTCC_CGTT_SCLK_CTRL_DEFAULT 0x00000100
-#define mmTCA_CGTT_SCLK_CTRL_DEFAULT 0x00000100
-#define mmCGTT_CP_CLK_CTRL_DEFAULT 0x00000100
-#define mmCGTT_CPF_CLK_CTRL_DEFAULT 0x00000100
-#define mmCGTT_CPC_CLK_CTRL_DEFAULT 0x00000100
-#define mmRLC_PWR_CTRL_DEFAULT 0x00000000
-#define mmCGTT_RLC_CLK_CTRL_DEFAULT 0x00000100
-#define mmRLC_GFX_RM_CNTL_DEFAULT 0x00000000
-#define mmRMI_CGTT_SCLK_CTRL_DEFAULT 0x00000100
-#define mmCGTT_TCPF_CLK_CTRL_DEFAULT 0x00000100
-
-
-// addressBlock: gc_ea_pwrdec
-#define mmGCEA_CGTT_CLK_CTRL_DEFAULT 0x00000100
-
-
-// addressBlock: gc_utcl2_vmsharedhvdec
-#define mmMC_VM_FB_SIZE_OFFSET_VF0_DEFAULT 0x00000000
-#define mmMC_VM_FB_SIZE_OFFSET_VF1_DEFAULT 0x00000000
-#define mmMC_VM_FB_SIZE_OFFSET_VF2_DEFAULT 0x00000000
-#define mmMC_VM_FB_SIZE_OFFSET_VF3_DEFAULT 0x00000000
-#define mmMC_VM_FB_SIZE_OFFSET_VF4_DEFAULT 0x00000000
-#define mmMC_VM_FB_SIZE_OFFSET_VF5_DEFAULT 0x00000000
-#define mmMC_VM_FB_SIZE_OFFSET_VF6_DEFAULT 0x00000000
-#define mmMC_VM_FB_SIZE_OFFSET_VF7_DEFAULT 0x00000000
-#define mmMC_VM_FB_SIZE_OFFSET_VF8_DEFAULT 0x00000000
-#define mmMC_VM_FB_SIZE_OFFSET_VF9_DEFAULT 0x00000000
-#define mmMC_VM_FB_SIZE_OFFSET_VF10_DEFAULT 0x00000000
-#define mmMC_VM_FB_SIZE_OFFSET_VF11_DEFAULT 0x00000000
-#define mmMC_VM_FB_SIZE_OFFSET_VF12_DEFAULT 0x00000000
-#define mmMC_VM_FB_SIZE_OFFSET_VF13_DEFAULT 0x00000000
-#define mmMC_VM_FB_SIZE_OFFSET_VF14_DEFAULT 0x00000000
-#define mmMC_VM_FB_SIZE_OFFSET_VF15_DEFAULT 0x00000000
-#define mmVM_IOMMU_MMIO_CNTRL_1_DEFAULT 0x00000100
-#define mmMC_VM_MARC_BASE_LO_0_DEFAULT 0x00000000
-#define mmMC_VM_MARC_BASE_LO_1_DEFAULT 0x00000000
-#define mmMC_VM_MARC_BASE_LO_2_DEFAULT 0x00000000
-#define mmMC_VM_MARC_BASE_LO_3_DEFAULT 0x00000000
-#define mmMC_VM_MARC_BASE_HI_0_DEFAULT 0x00000000
-#define mmMC_VM_MARC_BASE_HI_1_DEFAULT 0x00000000
-#define mmMC_VM_MARC_BASE_HI_2_DEFAULT 0x00000000
-#define mmMC_VM_MARC_BASE_HI_3_DEFAULT 0x00000000
-#define mmMC_VM_MARC_RELOC_LO_0_DEFAULT 0x00000000
-#define mmMC_VM_MARC_RELOC_LO_1_DEFAULT 0x00000000
-#define mmMC_VM_MARC_RELOC_LO_2_DEFAULT 0x00000000
-#define mmMC_VM_MARC_RELOC_LO_3_DEFAULT 0x00000000
-#define mmMC_VM_MARC_RELOC_HI_0_DEFAULT 0x00000000
-#define mmMC_VM_MARC_RELOC_HI_1_DEFAULT 0x00000000
-#define mmMC_VM_MARC_RELOC_HI_2_DEFAULT 0x00000000
-#define mmMC_VM_MARC_RELOC_HI_3_DEFAULT 0x00000000
-#define mmMC_VM_MARC_LEN_LO_0_DEFAULT 0x00000000
-#define mmMC_VM_MARC_LEN_LO_1_DEFAULT 0x00000000
-#define mmMC_VM_MARC_LEN_LO_2_DEFAULT 0x00000000
-#define mmMC_VM_MARC_LEN_LO_3_DEFAULT 0x00000000
-#define mmMC_VM_MARC_LEN_HI_0_DEFAULT 0x00000000
-#define mmMC_VM_MARC_LEN_HI_1_DEFAULT 0x00000000
-#define mmMC_VM_MARC_LEN_HI_2_DEFAULT 0x00000000
-#define mmMC_VM_MARC_LEN_HI_3_DEFAULT 0x00000000
-#define mmVM_IOMMU_CONTROL_REGISTER_DEFAULT 0x00000000
-#define mmVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_DEFAULT 0x00000000
-#define mmVM_PCIE_ATS_CNTL_DEFAULT 0x00000000
-#define mmVM_PCIE_ATS_CNTL_VF_0_DEFAULT 0x00000000
-#define mmVM_PCIE_ATS_CNTL_VF_1_DEFAULT 0x00000000
-#define mmVM_PCIE_ATS_CNTL_VF_2_DEFAULT 0x00000000
-#define mmVM_PCIE_ATS_CNTL_VF_3_DEFAULT 0x00000000
-#define mmVM_PCIE_ATS_CNTL_VF_4_DEFAULT 0x00000000
-#define mmVM_PCIE_ATS_CNTL_VF_5_DEFAULT 0x00000000
-#define mmVM_PCIE_ATS_CNTL_VF_6_DEFAULT 0x00000000
-#define mmVM_PCIE_ATS_CNTL_VF_7_DEFAULT 0x00000000
-#define mmVM_PCIE_ATS_CNTL_VF_8_DEFAULT 0x00000000
-#define mmVM_PCIE_ATS_CNTL_VF_9_DEFAULT 0x00000000
-#define mmVM_PCIE_ATS_CNTL_VF_10_DEFAULT 0x00000000
-#define mmVM_PCIE_ATS_CNTL_VF_11_DEFAULT 0x00000000
-#define mmVM_PCIE_ATS_CNTL_VF_12_DEFAULT 0x00000000
-#define mmVM_PCIE_ATS_CNTL_VF_13_DEFAULT 0x00000000
-#define mmVM_PCIE_ATS_CNTL_VF_14_DEFAULT 0x00000000
-#define mmVM_PCIE_ATS_CNTL_VF_15_DEFAULT 0x00000000
-#define mmUTCL2_CGTT_CLK_CTRL_DEFAULT 0x00000080
-
-
-// addressBlock: gc_hypdec
-#define mmCP_HYP_PFP_UCODE_ADDR_DEFAULT 0x00000000
-#define mmCP_PFP_UCODE_ADDR_DEFAULT 0x00000000
-#define mmCP_HYP_PFP_UCODE_DATA_DEFAULT 0x00000000
-#define mmCP_PFP_UCODE_DATA_DEFAULT 0x00000000
-#define mmCP_HYP_ME_UCODE_ADDR_DEFAULT 0x00000000
-#define mmCP_ME_RAM_RADDR_DEFAULT 0x00000000
-#define mmCP_ME_RAM_WADDR_DEFAULT 0x00000000
-#define mmCP_HYP_ME_UCODE_DATA_DEFAULT 0x00000000
-#define mmCP_ME_RAM_DATA_DEFAULT 0x00000000
-#define mmCP_CE_UCODE_ADDR_DEFAULT 0x00000000
-#define mmCP_HYP_CE_UCODE_ADDR_DEFAULT 0x00000000
-#define mmCP_CE_UCODE_DATA_DEFAULT 0x00000000
-#define mmCP_HYP_CE_UCODE_DATA_DEFAULT 0x00000000
-#define mmCP_HYP_MEC1_UCODE_ADDR_DEFAULT 0x00000000
-#define mmCP_MEC_ME1_UCODE_ADDR_DEFAULT 0x00000000
-#define mmCP_HYP_MEC1_UCODE_DATA_DEFAULT 0x00000000
-#define mmCP_MEC_ME1_UCODE_DATA_DEFAULT 0x00000000
-#define mmCP_HYP_MEC2_UCODE_ADDR_DEFAULT 0x00000000
-#define mmCP_MEC_ME2_UCODE_ADDR_DEFAULT 0x00000000
-#define mmCP_HYP_MEC2_UCODE_DATA_DEFAULT 0x00000000
-#define mmCP_MEC_ME2_UCODE_DATA_DEFAULT 0x00000000
-#define mmRLC_GPM_UCODE_ADDR_DEFAULT 0x00000000
-#define mmRLC_GPM_UCODE_DATA_DEFAULT 0x00000000
-#define mmGRBM_GFX_INDEX_SR_SELECT_DEFAULT 0x00000000
-#define mmGRBM_GFX_INDEX_SR_DATA_DEFAULT 0xe0000000
-#define mmGRBM_GFX_CNTL_SR_SELECT_DEFAULT 0x00000000
-#define mmGRBM_GFX_CNTL_SR_DATA_DEFAULT 0x00000000
-#define mmGRBM_CAM_INDEX_DEFAULT 0x00000000
-#define mmGRBM_HYP_CAM_INDEX_DEFAULT 0x00000000
-#define mmGRBM_CAM_DATA_DEFAULT 0x00000000
-#define mmGRBM_HYP_CAM_DATA_DEFAULT 0x00000000
-#define mmRLC_GPU_IOV_VF_ENABLE_DEFAULT 0x00000000
-#define mmRLC_GFX_RM_CNTL_ADJ_DEFAULT 0x00000000
-#define mmRLC_GPU_IOV_CFG_REG6_DEFAULT 0x00000000
-#define mmRLC_GPU_IOV_CFG_REG8_DEFAULT 0x00000000
-#define mmRLC_RLCV_TIMER_INT_0_DEFAULT 0x00000000
-#define mmRLC_RLCV_TIMER_CTRL_DEFAULT 0x00000000
-#define mmRLC_RLCV_TIMER_STAT_DEFAULT 0x00000000
-#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_DEFAULT 0x0000ffff
-#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_SET_DEFAULT 0x00000000
-#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR_DEFAULT 0x00000000
-#define mmRLC_GPU_IOV_VF_MASK_DEFAULT 0x00010001
-#define mmRLC_HYP_SEMAPHORE_2_DEFAULT 0x00000000
-#define mmRLC_HYP_SEMAPHORE_3_DEFAULT 0x00000000
-#define mmRLC_CLK_CNTL_DEFAULT 0x00000003
-#define mmRLC_GPU_IOV_SCH_BLOCK_DEFAULT 0x00000000
-#define mmRLC_GPU_IOV_CFG_REG1_DEFAULT 0x00000000
-#define mmRLC_GPU_IOV_CFG_REG2_DEFAULT 0x00000000
-#define mmRLC_GPU_IOV_VM_BUSY_STATUS_DEFAULT 0x00000000
-#define mmRLC_GPU_IOV_SCH_0_DEFAULT 0x00000000
-#define mmRLC_GPU_IOV_ACTIVE_FCN_ID_DEFAULT 0x00000000
-#define mmRLC_GPU_IOV_SCH_3_DEFAULT 0x00000000
-#define mmRLC_GPU_IOV_SCH_1_DEFAULT 0x00000000
-#define mmRLC_GPU_IOV_SCH_2_DEFAULT 0x00000000
-#define mmRLC_GPU_IOV_UCODE_ADDR_DEFAULT 0x00000000
-#define mmRLC_GPU_IOV_UCODE_DATA_DEFAULT 0x00000000
-#define mmRLC_GPU_IOV_SCRATCH_ADDR_DEFAULT 0x00000000
-#define mmRLC_GPU_IOV_SCRATCH_DATA_DEFAULT 0x00000000
-#define mmRLC_GPU_IOV_F32_CNTL_DEFAULT 0x00000000
-#define mmRLC_GPU_IOV_F32_RESET_DEFAULT 0x00000000
-#define mmRLC_GPU_IOV_SDMA0_STATUS_DEFAULT 0x00000000
-#define mmRLC_GPU_IOV_SDMA1_STATUS_DEFAULT 0x00000000
-#define mmRLC_GPU_IOV_SMU_RESPONSE_DEFAULT 0x00000000
-#define mmRLC_GPU_IOV_VIRT_RESET_REQ_DEFAULT 0x00000000
-#define mmRLC_GPU_IOV_RLC_RESPONSE_DEFAULT 0x00000000
-#define mmRLC_GPU_IOV_INT_DISABLE_DEFAULT 0x00000000
-#define mmRLC_GPU_IOV_INT_FORCE_DEFAULT 0x00000000
-#define mmRLC_GPU_IOV_SDMA0_BUSY_STATUS_DEFAULT 0x00000000
-#define mmRLC_GPU_IOV_SDMA1_BUSY_STATUS_DEFAULT 0x00000000
-
-
-// addressBlock: gccacind
-#define ixGC_CAC_CNTL_DEFAULT 0x000001fe
-#define ixGC_CAC_OVR_SEL_DEFAULT 0x00000000
-#define ixGC_CAC_OVR_VAL_DEFAULT 0x00000000
-#define ixGC_CAC_WEIGHT_BCI_0_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_CB_0_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_CB_1_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_CP_0_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_CP_1_DEFAULT 0x00000001
-#define ixGC_CAC_WEIGHT_DB_0_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_DB_1_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_GDS_0_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_GDS_1_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_IA_0_DEFAULT 0x00000001
-#define ixGC_CAC_WEIGHT_LDS_0_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_LDS_1_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_PA_0_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_PC_0_DEFAULT 0x00000001
-#define ixGC_CAC_WEIGHT_SC_0_DEFAULT 0x00000001
-#define ixGC_CAC_WEIGHT_SPI_0_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_SPI_1_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_SPI_2_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_SQ_0_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_SQ_1_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_SQ_2_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_SQ_3_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_SQ_4_DEFAULT 0x00000001
-#define ixGC_CAC_WEIGHT_SX_0_DEFAULT 0x00000001
-#define ixGC_CAC_WEIGHT_SXRB_0_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_TA_0_DEFAULT 0x00000001
-#define ixGC_CAC_WEIGHT_TCC_0_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_TCC_1_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_TCC_2_DEFAULT 0x00000001
-#define ixGC_CAC_WEIGHT_TCP_0_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_TCP_1_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_TCP_2_DEFAULT 0x00000001
-#define ixGC_CAC_WEIGHT_TD_0_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_TD_1_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_TD_2_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_VGT_0_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_VGT_1_DEFAULT 0x00000001
-#define ixGC_CAC_WEIGHT_WD_0_DEFAULT 0x00000001
-#define ixGC_CAC_WEIGHT_CU_0_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_CU_1_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_CU_2_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_CU_3_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_CU_4_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_CU_5_DEFAULT 0x00010001
-#define ixGC_CAC_ACC_BCI0_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_CB0_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_CB1_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_CB2_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_CB3_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_CP0_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_CP1_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_CP2_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_DB0_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_DB1_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_DB2_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_DB3_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_GDS0_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_GDS1_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_GDS2_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_GDS3_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_IA0_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_LDS0_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_LDS1_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_LDS2_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_LDS3_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_PA0_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_PA1_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_PC0_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_SC0_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_SPI0_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_SPI1_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_SPI2_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_SPI3_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_SPI4_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_SPI5_DEFAULT 0x00000000
-#define ixGC_CAC_WEIGHT_PG_0_DEFAULT 0x00000001
-#define ixGC_CAC_ACC_PG0_DEFAULT 0x00000000
-#define ixGC_CAC_OVRD_PG_DEFAULT 0x00000000
-#define ixGC_CAC_WEIGHT_UTCL2_ATCL2_0_DEFAULT 0x00010001
-#define ixGC_CAC_ACC_EA0_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_EA1_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_EA2_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_EA3_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_UTCL2_ATCL20_DEFAULT 0x00000000
-#define ixGC_CAC_OVRD_EA_DEFAULT 0x00000000
-#define ixGC_CAC_OVRD_UTCL2_ATCL2_DEFAULT 0x00000000
-#define ixGC_CAC_WEIGHT_EA_0_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_EA_1_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_RMI_0_DEFAULT 0x00000001
-#define ixGC_CAC_ACC_RMI0_DEFAULT 0x00000000
-#define ixGC_CAC_OVRD_RMI_DEFAULT 0x00000000
-#define ixGC_CAC_WEIGHT_UTCL2_ATCL2_1_DEFAULT 0x00010001
-#define ixGC_CAC_ACC_UTCL2_ATCL21_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_UTCL2_ATCL22_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_UTCL2_ATCL23_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_EA4_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_EA5_DEFAULT 0x00000000
-#define ixGC_CAC_WEIGHT_EA_2_DEFAULT 0x00010001
-#define ixGC_CAC_ACC_SQ0_LOWER_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_SQ0_UPPER_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_SQ1_LOWER_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_SQ1_UPPER_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_SQ2_LOWER_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_SQ2_UPPER_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_SQ3_LOWER_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_SQ3_UPPER_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_SQ4_LOWER_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_SQ4_UPPER_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_SQ5_LOWER_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_SQ5_UPPER_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_SQ6_LOWER_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_SQ6_UPPER_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_SQ7_LOWER_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_SQ7_UPPER_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_SQ8_LOWER_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_SQ8_UPPER_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_SX0_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_SXRB0_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_SXRB1_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_TA0_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_TCC0_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_TCC1_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_TCC2_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_TCC3_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_TCC4_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_TCP0_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_TCP1_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_TCP2_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_TCP3_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_TCP4_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_TD0_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_TD1_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_TD2_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_TD3_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_TD4_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_TD5_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_VGT0_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_VGT1_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_VGT2_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_WD0_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_CU0_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_CU1_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_CU2_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_CU3_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_CU4_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_CU5_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_CU6_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_CU7_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_CU8_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_CU9_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_CU10_DEFAULT 0x00000000
-#define ixGC_CAC_OVRD_BCI_DEFAULT 0x00000000
-#define ixGC_CAC_OVRD_CB_DEFAULT 0x00000000
-#define ixGC_CAC_OVRD_CP_DEFAULT 0x00000000
-#define ixGC_CAC_OVRD_DB_DEFAULT 0x00000000
-#define ixGC_CAC_OVRD_GDS_DEFAULT 0x00000000
-#define ixGC_CAC_OVRD_IA_DEFAULT 0x00000000
-#define ixGC_CAC_OVRD_LDS_DEFAULT 0x00000000
-#define ixGC_CAC_OVRD_PA_DEFAULT 0x00000000
-#define ixGC_CAC_OVRD_PC_DEFAULT 0x00000000
-#define ixGC_CAC_OVRD_SC_DEFAULT 0x00000000
-#define ixGC_CAC_OVRD_SPI_DEFAULT 0x00000000
-#define ixGC_CAC_OVRD_CU_DEFAULT 0x00000000
-#define ixGC_CAC_OVRD_SQ_DEFAULT 0x00000000
-#define ixGC_CAC_OVRD_SX_DEFAULT 0x00000000
-#define ixGC_CAC_OVRD_SXRB_DEFAULT 0x00000000
-#define ixGC_CAC_OVRD_TA_DEFAULT 0x00000000
-#define ixGC_CAC_OVRD_TCC_DEFAULT 0x00000000
-#define ixGC_CAC_OVRD_TCP_DEFAULT 0x00000000
-#define ixGC_CAC_OVRD_TD_DEFAULT 0x00000000
-#define ixGC_CAC_OVRD_VGT_DEFAULT 0x00000000
-#define ixGC_CAC_OVRD_WD_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_BCI1_DEFAULT 0x00000000
-#define ixGC_CAC_WEIGHT_UTCL2_ATCL2_2_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_0_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_1_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_2_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_3_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_4_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_UTCL2_VML2_0_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_UTCL2_VML2_1_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_UTCL2_VML2_2_DEFAULT 0x00010001
-#define ixGC_CAC_ACC_UTCL2_ATCL24_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_UTCL2_ROUTER0_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_UTCL2_ROUTER1_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_UTCL2_ROUTER2_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_UTCL2_ROUTER3_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_UTCL2_ROUTER4_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_UTCL2_ROUTER5_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_UTCL2_ROUTER6_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_UTCL2_ROUTER7_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_UTCL2_ROUTER8_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_UTCL2_ROUTER9_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_UTCL2_VML20_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_UTCL2_VML21_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_UTCL2_VML22_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_UTCL2_VML23_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_UTCL2_VML24_DEFAULT 0x00000000
-#define ixGC_CAC_OVRD_UTCL2_ROUTER_DEFAULT 0x00000000
-#define ixGC_CAC_OVRD_UTCL2_VML2_DEFAULT 0x00000000
-#define ixGC_CAC_WEIGHT_UTCL2_WALKER_0_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_UTCL2_WALKER_1_DEFAULT 0x00010001
-#define ixGC_CAC_WEIGHT_UTCL2_WALKER_2_DEFAULT 0x00010001
-#define ixGC_CAC_ACC_UTCL2_WALKER0_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_UTCL2_WALKER1_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_UTCL2_WALKER2_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_UTCL2_WALKER3_DEFAULT 0x00000000
-#define ixGC_CAC_ACC_UTCL2_WALKER4_DEFAULT 0x00000000
-#define ixGC_CAC_OVRD_UTCL2_WALKER_DEFAULT 0x00000000
-
-
-// addressBlock: secacind
-#define ixSE_CAC_CNTL_DEFAULT 0x000001fe
-#define ixSE_CAC_OVR_SEL_DEFAULT 0x00000000
-#define ixSE_CAC_OVR_VAL_DEFAULT 0x00000000
-
-
-// addressBlock: sqind
-#define ixSQ_WAVE_MODE_DEFAULT 0x00000000
-#define ixSQ_WAVE_STATUS_DEFAULT 0x00000000
-#define ixSQ_WAVE_TRAPSTS_DEFAULT 0x00000000
-#define ixSQ_WAVE_HW_ID_DEFAULT 0x00000000
-#define ixSQ_WAVE_GPR_ALLOC_DEFAULT 0x00000000
-#define ixSQ_WAVE_LDS_ALLOC_DEFAULT 0x00000000
-#define ixSQ_WAVE_IB_STS_DEFAULT 0x00000000
-#define ixSQ_WAVE_PC_LO_DEFAULT 0x00000000
-#define ixSQ_WAVE_PC_HI_DEFAULT 0x00000000
-#define ixSQ_WAVE_INST_DW0_DEFAULT 0x00000000
-#define ixSQ_WAVE_INST_DW1_DEFAULT 0x00000000
-#define ixSQ_WAVE_IB_DBG0_DEFAULT 0x00000000
-#define ixSQ_WAVE_IB_DBG1_DEFAULT 0x00000000
-#define ixSQ_WAVE_FLUSH_IB_DEFAULT 0x00000000
-#define ixSQ_WAVE_TTMP0_DEFAULT 0x00000000
-#define ixSQ_WAVE_TTMP1_DEFAULT 0x00000000
-#define ixSQ_WAVE_TTMP2_DEFAULT 0x00000000
-#define ixSQ_WAVE_TTMP3_DEFAULT 0x00000000
-#define ixSQ_WAVE_TTMP4_DEFAULT 0x00000000
-#define ixSQ_WAVE_TTMP5_DEFAULT 0x00000000
-#define ixSQ_WAVE_TTMP6_DEFAULT 0x00000000
-#define ixSQ_WAVE_TTMP7_DEFAULT 0x00000000
-#define ixSQ_WAVE_TTMP8_DEFAULT 0x00000000
-#define ixSQ_WAVE_TTMP9_DEFAULT 0x00000000
-#define ixSQ_WAVE_TTMP10_DEFAULT 0x00000000
-#define ixSQ_WAVE_TTMP11_DEFAULT 0x00000000
-#define ixSQ_WAVE_TTMP12_DEFAULT 0x00000000
-#define ixSQ_WAVE_TTMP13_DEFAULT 0x00000000
-#define ixSQ_WAVE_TTMP14_DEFAULT 0x00000000
-#define ixSQ_WAVE_TTMP15_DEFAULT 0x00000000
-#define ixSQ_WAVE_M0_DEFAULT 0x00000000
-#define ixSQ_WAVE_EXEC_LO_DEFAULT 0x00000000
-#define ixSQ_WAVE_EXEC_HI_DEFAULT 0x00000000
-#define ixSQ_INTERRUPT_WORD_AUTO_CTXID_DEFAULT 0x00000000
-#define ixSQ_INTERRUPT_WORD_AUTO_HI_DEFAULT 0x00000000
-#define ixSQ_INTERRUPT_WORD_AUTO_LO_DEFAULT 0x00000000
-#define ixSQ_INTERRUPT_WORD_CMN_CTXID_DEFAULT 0x00000000
-#define ixSQ_INTERRUPT_WORD_CMN_HI_DEFAULT 0x00000000
-#define ixSQ_INTERRUPT_WORD_WAVE_CTXID_DEFAULT 0x00000000
-#define ixSQ_INTERRUPT_WORD_WAVE_HI_DEFAULT 0x00000000
-#define ixSQ_INTERRUPT_WORD_WAVE_LO_DEFAULT 0x00000000
-
-
-
-
-
-
-
-
-// addressBlock: didtind
-#define ixDIDT_SQ_CTRL0_DEFAULT 0x0000ff00
-#define ixDIDT_SQ_CTRL1_DEFAULT 0x00ff00ff
-#define ixDIDT_SQ_CTRL2_DEFAULT 0x18800004
-#define ixDIDT_SQ_STALL_CTRL_DEFAULT 0x00fff000
-#define ixDIDT_SQ_TUNING_CTRL_DEFAULT 0x00010004
-#define ixDIDT_SQ_STALL_AUTO_RELEASE_CTRL_DEFAULT 0x00ffffff
-#define ixDIDT_SQ_CTRL3_DEFAULT 0x00038000
-#define ixDIDT_SQ_STALL_PATTERN_1_2_DEFAULT 0x01010001
-#define ixDIDT_SQ_STALL_PATTERN_3_4_DEFAULT 0x11110421
-#define ixDIDT_SQ_STALL_PATTERN_5_6_DEFAULT 0x25291249
-#define ixDIDT_SQ_STALL_PATTERN_7_DEFAULT 0x00002aaa
-#define ixDIDT_SQ_WEIGHT0_3_DEFAULT 0x00000000
-#define ixDIDT_SQ_WEIGHT4_7_DEFAULT 0x00000000
-#define ixDIDT_SQ_WEIGHT8_11_DEFAULT 0x00000000
-#define ixDIDT_SQ_EDC_CTRL_DEFAULT 0x00001c00
-#define ixDIDT_SQ_EDC_THRESHOLD_DEFAULT 0x00000000
-#define ixDIDT_SQ_EDC_STALL_PATTERN_1_2_DEFAULT 0x01010001
-#define ixDIDT_SQ_EDC_STALL_PATTERN_3_4_DEFAULT 0x11110421
-#define ixDIDT_SQ_EDC_STALL_PATTERN_5_6_DEFAULT 0x25291249
-#define ixDIDT_SQ_EDC_STALL_PATTERN_7_DEFAULT 0x00002aaa
-#define ixDIDT_SQ_EDC_STATUS_DEFAULT 0x00000000
-#define ixDIDT_SQ_EDC_STALL_DELAY_1_DEFAULT 0x00000000
-#define ixDIDT_SQ_EDC_STALL_DELAY_2_DEFAULT 0x00000000
-#define ixDIDT_SQ_EDC_STALL_DELAY_3_DEFAULT 0x00000000
-#define ixDIDT_SQ_EDC_OVERFLOW_DEFAULT 0x00000000
-#define ixDIDT_SQ_EDC_ROLLING_POWER_DELTA_DEFAULT 0x00000000
-#define ixDIDT_DB_CTRL0_DEFAULT 0x0000ff00
-#define ixDIDT_DB_CTRL1_DEFAULT 0x00ff00ff
-#define ixDIDT_DB_CTRL2_DEFAULT 0x18800004
-#define ixDIDT_DB_STALL_CTRL_DEFAULT 0x00fff000
-#define ixDIDT_DB_TUNING_CTRL_DEFAULT 0x00010004
-#define ixDIDT_DB_STALL_AUTO_RELEASE_CTRL_DEFAULT 0x00ffffff
-#define ixDIDT_DB_CTRL3_DEFAULT 0x00038000
-#define ixDIDT_DB_STALL_PATTERN_1_2_DEFAULT 0x01010001
-#define ixDIDT_DB_STALL_PATTERN_3_4_DEFAULT 0x11110421
-#define ixDIDT_DB_STALL_PATTERN_5_6_DEFAULT 0x25291249
-#define ixDIDT_DB_STALL_PATTERN_7_DEFAULT 0x00002aaa
-#define ixDIDT_DB_WEIGHT0_3_DEFAULT 0x00000000
-#define ixDIDT_DB_WEIGHT4_7_DEFAULT 0x00000000
-#define ixDIDT_DB_WEIGHT8_11_DEFAULT 0x00000000
-#define ixDIDT_DB_EDC_CTRL_DEFAULT 0x00001c00
-#define ixDIDT_DB_EDC_THRESHOLD_DEFAULT 0x00000000
-#define ixDIDT_DB_EDC_STALL_PATTERN_1_2_DEFAULT 0x01010001
-#define ixDIDT_DB_EDC_STALL_PATTERN_3_4_DEFAULT 0x11110421
-#define ixDIDT_DB_EDC_STALL_PATTERN_5_6_DEFAULT 0x25291249
-#define ixDIDT_DB_EDC_STALL_PATTERN_7_DEFAULT 0x00002aaa
-#define ixDIDT_DB_EDC_STATUS_DEFAULT 0x00000000
-#define ixDIDT_DB_EDC_STALL_DELAY_1_DEFAULT 0x00000000
-#define ixDIDT_DB_EDC_OVERFLOW_DEFAULT 0x00000000
-#define ixDIDT_DB_EDC_ROLLING_POWER_DELTA_DEFAULT 0x00000000
-#define ixDIDT_TD_CTRL0_DEFAULT 0x0000ff00
-#define ixDIDT_TD_CTRL1_DEFAULT 0x00ff00ff
-#define ixDIDT_TD_CTRL2_DEFAULT 0x18800004
-#define ixDIDT_TD_STALL_CTRL_DEFAULT 0x00fff000
-#define ixDIDT_TD_TUNING_CTRL_DEFAULT 0x00010004
-#define ixDIDT_TD_STALL_AUTO_RELEASE_CTRL_DEFAULT 0x00ffffff
-#define ixDIDT_TD_CTRL3_DEFAULT 0x00038000
-#define ixDIDT_TD_STALL_PATTERN_1_2_DEFAULT 0x01010001
-#define ixDIDT_TD_STALL_PATTERN_3_4_DEFAULT 0x11110421
-#define ixDIDT_TD_STALL_PATTERN_5_6_DEFAULT 0x25291249
-#define ixDIDT_TD_STALL_PATTERN_7_DEFAULT 0x00002aaa
-#define ixDIDT_TD_WEIGHT0_3_DEFAULT 0x00000000
-#define ixDIDT_TD_WEIGHT4_7_DEFAULT 0x00000000
-#define ixDIDT_TD_WEIGHT8_11_DEFAULT 0x00000000
-#define ixDIDT_TD_EDC_CTRL_DEFAULT 0x00001c00
-#define ixDIDT_TD_EDC_THRESHOLD_DEFAULT 0x00000000
-#define ixDIDT_TD_EDC_STALL_PATTERN_1_2_DEFAULT 0x01010001
-#define ixDIDT_TD_EDC_STALL_PATTERN_3_4_DEFAULT 0x11110421
-#define ixDIDT_TD_EDC_STALL_PATTERN_5_6_DEFAULT 0x25291249
-#define ixDIDT_TD_EDC_STALL_PATTERN_7_DEFAULT 0x00002aaa
-#define ixDIDT_TD_EDC_STATUS_DEFAULT 0x00000000
-#define ixDIDT_TD_EDC_STALL_DELAY_1_DEFAULT 0x00000000
-#define ixDIDT_TD_EDC_STALL_DELAY_2_DEFAULT 0x00000000
-#define ixDIDT_TD_EDC_STALL_DELAY_3_DEFAULT 0x00000000
-#define ixDIDT_TD_EDC_OVERFLOW_DEFAULT 0x00000000
-#define ixDIDT_TD_EDC_ROLLING_POWER_DELTA_DEFAULT 0x00000000
-#define ixDIDT_TCP_CTRL0_DEFAULT 0x0000ff00
-#define ixDIDT_TCP_CTRL1_DEFAULT 0x00ff00ff
-#define ixDIDT_TCP_CTRL2_DEFAULT 0x18800004
-#define ixDIDT_TCP_STALL_CTRL_DEFAULT 0x00fff000
-#define ixDIDT_TCP_TUNING_CTRL_DEFAULT 0x00010004
-#define ixDIDT_TCP_STALL_AUTO_RELEASE_CTRL_DEFAULT 0x00ffffff
-#define ixDIDT_TCP_CTRL3_DEFAULT 0x00038000
-#define ixDIDT_TCP_STALL_PATTERN_1_2_DEFAULT 0x01010001
-#define ixDIDT_TCP_STALL_PATTERN_3_4_DEFAULT 0x11110421
-#define ixDIDT_TCP_STALL_PATTERN_5_6_DEFAULT 0x25291249
-#define ixDIDT_TCP_STALL_PATTERN_7_DEFAULT 0x00002aaa
-#define ixDIDT_TCP_WEIGHT0_3_DEFAULT 0x00000000
-#define ixDIDT_TCP_WEIGHT4_7_DEFAULT 0x00000000
-#define ixDIDT_TCP_WEIGHT8_11_DEFAULT 0x00000000
-#define ixDIDT_TCP_EDC_CTRL_DEFAULT 0x00001c00
-#define ixDIDT_TCP_EDC_THRESHOLD_DEFAULT 0x00000000
-#define ixDIDT_TCP_EDC_STALL_PATTERN_1_2_DEFAULT 0x01010001
-#define ixDIDT_TCP_EDC_STALL_PATTERN_3_4_DEFAULT 0x11110421
-#define ixDIDT_TCP_EDC_STALL_PATTERN_5_6_DEFAULT 0x25291249
-#define ixDIDT_TCP_EDC_STALL_PATTERN_7_DEFAULT 0x00002aaa
-#define ixDIDT_TCP_EDC_STATUS_DEFAULT 0x00000000
-#define ixDIDT_TCP_EDC_STALL_DELAY_1_DEFAULT 0x00000000
-#define ixDIDT_TCP_EDC_STALL_DELAY_2_DEFAULT 0x00000000
-#define ixDIDT_TCP_EDC_STALL_DELAY_3_DEFAULT 0x00000000
-#define ixDIDT_TCP_EDC_OVERFLOW_DEFAULT 0x00000000
-#define ixDIDT_TCP_EDC_ROLLING_POWER_DELTA_DEFAULT 0x00000000
-#define ixDIDT_DBR_CTRL0_DEFAULT 0x0000ff00
-#define ixDIDT_DBR_CTRL1_DEFAULT 0x00ff00ff
-#define ixDIDT_DBR_CTRL2_DEFAULT 0x18800004
-#define ixDIDT_DBR_STALL_CTRL_DEFAULT 0x00fff000
-#define ixDIDT_DBR_TUNING_CTRL_DEFAULT 0x00010004
-#define ixDIDT_DBR_STALL_AUTO_RELEASE_CTRL_DEFAULT 0x00ffffff
-#define ixDIDT_DBR_CTRL3_DEFAULT 0x00038000
-#define ixDIDT_DBR_STALL_PATTERN_1_2_DEFAULT 0x01010001
-#define ixDIDT_DBR_STALL_PATTERN_3_4_DEFAULT 0x11110421
-#define ixDIDT_DBR_STALL_PATTERN_5_6_DEFAULT 0x25291249
-#define ixDIDT_DBR_STALL_PATTERN_7_DEFAULT 0x00002aaa
-#define ixDIDT_DBR_WEIGHT0_3_DEFAULT 0x00000000
-#define ixDIDT_DBR_WEIGHT4_7_DEFAULT 0x00000000
-#define ixDIDT_DBR_WEIGHT8_11_DEFAULT 0x00000000
-#define ixDIDT_DBR_EDC_CTRL_DEFAULT 0x00001c00
-#define ixDIDT_DBR_EDC_THRESHOLD_DEFAULT 0x00000000
-#define ixDIDT_DBR_EDC_STALL_PATTERN_1_2_DEFAULT 0x01010001
-#define ixDIDT_DBR_EDC_STALL_PATTERN_3_4_DEFAULT 0x11110421
-#define ixDIDT_DBR_EDC_STALL_PATTERN_5_6_DEFAULT 0x25291249
-#define ixDIDT_DBR_EDC_STALL_PATTERN_7_DEFAULT 0x00002aaa
-#define ixDIDT_DBR_EDC_STATUS_DEFAULT 0x00000000
-#define ixDIDT_DBR_EDC_STALL_DELAY_1_DEFAULT 0x00000000
-#define ixDIDT_DBR_EDC_OVERFLOW_DEFAULT 0x00000000
-#define ixDIDT_DBR_EDC_ROLLING_POWER_DELTA_DEFAULT 0x00000000
-#define ixDIDT_SQ_STALL_EVENT_COUNTER_DEFAULT 0x00000000
-#define ixDIDT_DB_STALL_EVENT_COUNTER_DEFAULT 0x00000000
-#define ixDIDT_TD_STALL_EVENT_COUNTER_DEFAULT 0x00000000
-#define ixDIDT_TCP_STALL_EVENT_COUNTER_DEFAULT 0x00000000
-#define ixDIDT_DBR_STALL_EVENT_COUNTER_DEFAULT 0x00000000
-
-
-
-
-
-#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/GC/gc_9_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/raven1/GC/gc_9_1_sh_mask.h
deleted file mode 100644
index ab0a25eba483..000000000000
--- a/drivers/gpu/drm/amd/include/asic_reg/raven1/GC/gc_9_1_sh_mask.h
+++ /dev/null
@@ -1,31191 +0,0 @@
-/*
- * Copyright (C) 2017 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-#ifndef _gc_9_1_SH_MASK_HEADER
-#define _gc_9_1_SH_MASK_HEADER
-
-
-// addressBlock: gc_grbmdec
-//GRBM_CNTL
-#define GRBM_CNTL__READ_TIMEOUT__SHIFT 0x0
-#define GRBM_CNTL__REPORT_LAST_RDERR__SHIFT 0x1f
-#define GRBM_CNTL__READ_TIMEOUT_MASK 0x000000FFL
-#define GRBM_CNTL__REPORT_LAST_RDERR_MASK 0x80000000L
-//GRBM_SKEW_CNTL
-#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT 0x0
-#define GRBM_SKEW_CNTL__SKEW_COUNT__SHIFT 0x6
-#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK 0x0000003FL
-#define GRBM_SKEW_CNTL__SKEW_COUNT_MASK 0x00000FC0L
-//GRBM_STATUS2
-#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL__SHIFT 0x0
-#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING__SHIFT 0x4
-#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING__SHIFT 0x5
-#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING__SHIFT 0x6
-#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING__SHIFT 0x7
-#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING__SHIFT 0x8
-#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING__SHIFT 0x9
-#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING__SHIFT 0xa
-#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING__SHIFT 0xb
-#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING__SHIFT 0xc
-#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING__SHIFT 0xd
-#define GRBM_STATUS2__RLC_RQ_PENDING__SHIFT 0xe
-#define GRBM_STATUS2__UTCL2_BUSY__SHIFT 0xf
-#define GRBM_STATUS2__EA_BUSY__SHIFT 0x10
-#define GRBM_STATUS2__RMI_BUSY__SHIFT 0x11
-#define GRBM_STATUS2__UTCL2_RQ_PENDING__SHIFT 0x12
-#define GRBM_STATUS2__CPF_RQ_PENDING__SHIFT 0x13
-#define GRBM_STATUS2__EA_LINK_BUSY__SHIFT 0x14
-#define GRBM_STATUS2__RLC_BUSY__SHIFT 0x18
-#define GRBM_STATUS2__TC_BUSY__SHIFT 0x19
-#define GRBM_STATUS2__TCC_CC_RESIDENT__SHIFT 0x1a
-#define GRBM_STATUS2__CPF_BUSY__SHIFT 0x1c
-#define GRBM_STATUS2__CPC_BUSY__SHIFT 0x1d
-#define GRBM_STATUS2__CPG_BUSY__SHIFT 0x1e
-#define GRBM_STATUS2__CPAXI_BUSY__SHIFT 0x1f
-#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL_MASK 0x0000000FL
-#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING_MASK 0x00000010L
-#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING_MASK 0x00000020L
-#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING_MASK 0x00000040L
-#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING_MASK 0x00000080L
-#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING_MASK 0x00000100L
-#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING_MASK 0x00000200L
-#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING_MASK 0x00000400L
-#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING_MASK 0x00000800L
-#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING_MASK 0x00001000L
-#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING_MASK 0x00002000L
-#define GRBM_STATUS2__RLC_RQ_PENDING_MASK 0x00004000L
-#define GRBM_STATUS2__UTCL2_BUSY_MASK 0x00008000L
-#define GRBM_STATUS2__EA_BUSY_MASK 0x00010000L
-#define GRBM_STATUS2__RMI_BUSY_MASK 0x00020000L
-#define GRBM_STATUS2__UTCL2_RQ_PENDING_MASK 0x00040000L
-#define GRBM_STATUS2__CPF_RQ_PENDING_MASK 0x00080000L
-#define GRBM_STATUS2__EA_LINK_BUSY_MASK 0x00100000L
-#define GRBM_STATUS2__RLC_BUSY_MASK 0x01000000L
-#define GRBM_STATUS2__TC_BUSY_MASK 0x02000000L
-#define GRBM_STATUS2__TCC_CC_RESIDENT_MASK 0x04000000L
-#define GRBM_STATUS2__CPF_BUSY_MASK 0x10000000L
-#define GRBM_STATUS2__CPC_BUSY_MASK 0x20000000L
-#define GRBM_STATUS2__CPG_BUSY_MASK 0x40000000L
-#define GRBM_STATUS2__CPAXI_BUSY_MASK 0x80000000L
-//GRBM_PWR_CNTL
-#define GRBM_PWR_CNTL__ALL_REQ_TYPE__SHIFT 0x0
-#define GRBM_PWR_CNTL__GFX_REQ_TYPE__SHIFT 0x2
-#define GRBM_PWR_CNTL__ALL_RSP_TYPE__SHIFT 0x4
-#define GRBM_PWR_CNTL__GFX_RSP_TYPE__SHIFT 0x6
-#define GRBM_PWR_CNTL__GFX_REQ_EN__SHIFT 0xe
-#define GRBM_PWR_CNTL__ALL_REQ_EN__SHIFT 0xf
-#define GRBM_PWR_CNTL__ALL_REQ_TYPE_MASK 0x00000003L
-#define GRBM_PWR_CNTL__GFX_REQ_TYPE_MASK 0x0000000CL
-#define GRBM_PWR_CNTL__ALL_RSP_TYPE_MASK 0x00000030L
-#define GRBM_PWR_CNTL__GFX_RSP_TYPE_MASK 0x000000C0L
-#define GRBM_PWR_CNTL__GFX_REQ_EN_MASK 0x00004000L
-#define GRBM_PWR_CNTL__ALL_REQ_EN_MASK 0x00008000L
-//GRBM_STATUS
-#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL__SHIFT 0x0
-#define GRBM_STATUS__RSMU_RQ_PENDING__SHIFT 0x5
-#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING__SHIFT 0x7
-#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING__SHIFT 0x8
-#define GRBM_STATUS__GDS_DMA_RQ_PENDING__SHIFT 0x9
-#define GRBM_STATUS__DB_CLEAN__SHIFT 0xc
-#define GRBM_STATUS__CB_CLEAN__SHIFT 0xd
-#define GRBM_STATUS__TA_BUSY__SHIFT 0xe
-#define GRBM_STATUS__GDS_BUSY__SHIFT 0xf
-#define GRBM_STATUS__WD_BUSY_NO_DMA__SHIFT 0x10
-#define GRBM_STATUS__VGT_BUSY__SHIFT 0x11
-#define GRBM_STATUS__IA_BUSY_NO_DMA__SHIFT 0x12
-#define GRBM_STATUS__IA_BUSY__SHIFT 0x13
-#define GRBM_STATUS__SX_BUSY__SHIFT 0x14
-#define GRBM_STATUS__WD_BUSY__SHIFT 0x15
-#define GRBM_STATUS__SPI_BUSY__SHIFT 0x16
-#define GRBM_STATUS__BCI_BUSY__SHIFT 0x17
-#define GRBM_STATUS__SC_BUSY__SHIFT 0x18
-#define GRBM_STATUS__PA_BUSY__SHIFT 0x19
-#define GRBM_STATUS__DB_BUSY__SHIFT 0x1a
-#define GRBM_STATUS__CP_COHERENCY_BUSY__SHIFT 0x1c
-#define GRBM_STATUS__CP_BUSY__SHIFT 0x1d
-#define GRBM_STATUS__CB_BUSY__SHIFT 0x1e
-#define GRBM_STATUS__GUI_ACTIVE__SHIFT 0x1f
-#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL_MASK 0x0000000FL
-#define GRBM_STATUS__RSMU_RQ_PENDING_MASK 0x00000020L
-#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING_MASK 0x00000080L
-#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING_MASK 0x00000100L
-#define GRBM_STATUS__GDS_DMA_RQ_PENDING_MASK 0x00000200L
-#define GRBM_STATUS__DB_CLEAN_MASK 0x00001000L
-#define GRBM_STATUS__CB_CLEAN_MASK 0x00002000L
-#define GRBM_STATUS__TA_BUSY_MASK 0x00004000L
-#define GRBM_STATUS__GDS_BUSY_MASK 0x00008000L
-#define GRBM_STATUS__WD_BUSY_NO_DMA_MASK 0x00010000L
-#define GRBM_STATUS__VGT_BUSY_MASK 0x00020000L
-#define GRBM_STATUS__IA_BUSY_NO_DMA_MASK 0x00040000L
-#define GRBM_STATUS__IA_BUSY_MASK 0x00080000L
-#define GRBM_STATUS__SX_BUSY_MASK 0x00100000L
-#define GRBM_STATUS__WD_BUSY_MASK 0x00200000L
-#define GRBM_STATUS__SPI_BUSY_MASK 0x00400000L
-#define GRBM_STATUS__BCI_BUSY_MASK 0x00800000L
-#define GRBM_STATUS__SC_BUSY_MASK 0x01000000L
-#define GRBM_STATUS__PA_BUSY_MASK 0x02000000L
-#define GRBM_STATUS__DB_BUSY_MASK 0x04000000L
-#define GRBM_STATUS__CP_COHERENCY_BUSY_MASK 0x10000000L
-#define GRBM_STATUS__CP_BUSY_MASK 0x20000000L
-#define GRBM_STATUS__CB_BUSY_MASK 0x40000000L
-#define GRBM_STATUS__GUI_ACTIVE_MASK 0x80000000L
-//GRBM_STATUS_SE0
-#define GRBM_STATUS_SE0__DB_CLEAN__SHIFT 0x1
-#define GRBM_STATUS_SE0__CB_CLEAN__SHIFT 0x2
-#define GRBM_STATUS_SE0__RMI_BUSY__SHIFT 0x15
-#define GRBM_STATUS_SE0__BCI_BUSY__SHIFT 0x16
-#define GRBM_STATUS_SE0__VGT_BUSY__SHIFT 0x17
-#define GRBM_STATUS_SE0__PA_BUSY__SHIFT 0x18
-#define GRBM_STATUS_SE0__TA_BUSY__SHIFT 0x19
-#define GRBM_STATUS_SE0__SX_BUSY__SHIFT 0x1a
-#define GRBM_STATUS_SE0__SPI_BUSY__SHIFT 0x1b
-#define GRBM_STATUS_SE0__SC_BUSY__SHIFT 0x1d
-#define GRBM_STATUS_SE0__DB_BUSY__SHIFT 0x1e
-#define GRBM_STATUS_SE0__CB_BUSY__SHIFT 0x1f
-#define GRBM_STATUS_SE0__DB_CLEAN_MASK 0x00000002L
-#define GRBM_STATUS_SE0__CB_CLEAN_MASK 0x00000004L
-#define GRBM_STATUS_SE0__RMI_BUSY_MASK 0x00200000L
-#define GRBM_STATUS_SE0__BCI_BUSY_MASK 0x00400000L
-#define GRBM_STATUS_SE0__VGT_BUSY_MASK 0x00800000L
-#define GRBM_STATUS_SE0__PA_BUSY_MASK 0x01000000L
-#define GRBM_STATUS_SE0__TA_BUSY_MASK 0x02000000L
-#define GRBM_STATUS_SE0__SX_BUSY_MASK 0x04000000L
-#define GRBM_STATUS_SE0__SPI_BUSY_MASK 0x08000000L
-#define GRBM_STATUS_SE0__SC_BUSY_MASK 0x20000000L
-#define GRBM_STATUS_SE0__DB_BUSY_MASK 0x40000000L
-#define GRBM_STATUS_SE0__CB_BUSY_MASK 0x80000000L
-//GRBM_STATUS_SE1
-#define GRBM_STATUS_SE1__DB_CLEAN__SHIFT 0x1
-#define GRBM_STATUS_SE1__CB_CLEAN__SHIFT 0x2
-#define GRBM_STATUS_SE1__RMI_BUSY__SHIFT 0x15
-#define GRBM_STATUS_SE1__BCI_BUSY__SHIFT 0x16
-#define GRBM_STATUS_SE1__VGT_BUSY__SHIFT 0x17
-#define GRBM_STATUS_SE1__PA_BUSY__SHIFT 0x18
-#define GRBM_STATUS_SE1__TA_BUSY__SHIFT 0x19
-#define GRBM_STATUS_SE1__SX_BUSY__SHIFT 0x1a
-#define GRBM_STATUS_SE1__SPI_BUSY__SHIFT 0x1b
-#define GRBM_STATUS_SE1__SC_BUSY__SHIFT 0x1d
-#define GRBM_STATUS_SE1__DB_BUSY__SHIFT 0x1e
-#define GRBM_STATUS_SE1__CB_BUSY__SHIFT 0x1f
-#define GRBM_STATUS_SE1__DB_CLEAN_MASK 0x00000002L
-#define GRBM_STATUS_SE1__CB_CLEAN_MASK 0x00000004L
-#define GRBM_STATUS_SE1__RMI_BUSY_MASK 0x00200000L
-#define GRBM_STATUS_SE1__BCI_BUSY_MASK 0x00400000L
-#define GRBM_STATUS_SE1__VGT_BUSY_MASK 0x00800000L
-#define GRBM_STATUS_SE1__PA_BUSY_MASK 0x01000000L
-#define GRBM_STATUS_SE1__TA_BUSY_MASK 0x02000000L
-#define GRBM_STATUS_SE1__SX_BUSY_MASK 0x04000000L
-#define GRBM_STATUS_SE1__SPI_BUSY_MASK 0x08000000L
-#define GRBM_STATUS_SE1__SC_BUSY_MASK 0x20000000L
-#define GRBM_STATUS_SE1__DB_BUSY_MASK 0x40000000L
-#define GRBM_STATUS_SE1__CB_BUSY_MASK 0x80000000L
-//GRBM_SOFT_RESET
-#define GRBM_SOFT_RESET__SOFT_RESET_CP__SHIFT 0x0
-#define GRBM_SOFT_RESET__SOFT_RESET_RLC__SHIFT 0x2
-#define GRBM_SOFT_RESET__SOFT_RESET_GFX__SHIFT 0x10
-#define GRBM_SOFT_RESET__SOFT_RESET_CPF__SHIFT 0x11
-#define GRBM_SOFT_RESET__SOFT_RESET_CPC__SHIFT 0x12
-#define GRBM_SOFT_RESET__SOFT_RESET_CPG__SHIFT 0x13
-#define GRBM_SOFT_RESET__SOFT_RESET_CAC__SHIFT 0x14
-#define GRBM_SOFT_RESET__SOFT_RESET_CPAXI__SHIFT 0x15
-#define GRBM_SOFT_RESET__SOFT_RESET_EA__SHIFT 0x16
-#define GRBM_SOFT_RESET__SOFT_RESET_CP_MASK 0x00000001L
-#define GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK 0x00000004L
-#define GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK 0x00010000L
-#define GRBM_SOFT_RESET__SOFT_RESET_CPF_MASK 0x00020000L
-#define GRBM_SOFT_RESET__SOFT_RESET_CPC_MASK 0x00040000L
-#define GRBM_SOFT_RESET__SOFT_RESET_CPG_MASK 0x00080000L
-#define GRBM_SOFT_RESET__SOFT_RESET_CAC_MASK 0x00100000L
-#define GRBM_SOFT_RESET__SOFT_RESET_CPAXI_MASK 0x00200000L
-#define GRBM_SOFT_RESET__SOFT_RESET_EA_MASK 0x00400000L
-//GRBM_CGTT_CLK_CNTL
-#define GRBM_CGTT_CLK_CNTL__ON_DELAY__SHIFT 0x0
-#define GRBM_CGTT_CLK_CNTL__OFF_HYSTERESIS__SHIFT 0x4
-#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
-#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
-#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
-#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
-#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
-#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
-#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
-#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
-#define GRBM_CGTT_CLK_CNTL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
-#define GRBM_CGTT_CLK_CNTL__ON_DELAY_MASK 0x0000000FL
-#define GRBM_CGTT_CLK_CNTL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
-#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
-#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
-#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
-#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
-#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
-#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
-#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
-#define GRBM_CGTT_CLK_CNTL__SOFT_OVERRIDE_DYN_MASK 0x40000000L
-//GRBM_GFX_CLKEN_CNTL
-#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
-#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
-#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0x0000000FL
-#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x00001F00L
-//GRBM_WAIT_IDLE_CLOCKS
-#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS__SHIFT 0x0
-#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_MASK 0x000000FFL
-//GRBM_STATUS_SE2
-#define GRBM_STATUS_SE2__DB_CLEAN__SHIFT 0x1
-#define GRBM_STATUS_SE2__CB_CLEAN__SHIFT 0x2
-#define GRBM_STATUS_SE2__RMI_BUSY__SHIFT 0x15
-#define GRBM_STATUS_SE2__BCI_BUSY__SHIFT 0x16
-#define GRBM_STATUS_SE2__VGT_BUSY__SHIFT 0x17
-#define GRBM_STATUS_SE2__PA_BUSY__SHIFT 0x18
-#define GRBM_STATUS_SE2__TA_BUSY__SHIFT 0x19
-#define GRBM_STATUS_SE2__SX_BUSY__SHIFT 0x1a
-#define GRBM_STATUS_SE2__SPI_BUSY__SHIFT 0x1b
-#define GRBM_STATUS_SE2__SC_BUSY__SHIFT 0x1d
-#define GRBM_STATUS_SE2__DB_BUSY__SHIFT 0x1e
-#define GRBM_STATUS_SE2__CB_BUSY__SHIFT 0x1f
-#define GRBM_STATUS_SE2__DB_CLEAN_MASK 0x00000002L
-#define GRBM_STATUS_SE2__CB_CLEAN_MASK 0x00000004L
-#define GRBM_STATUS_SE2__RMI_BUSY_MASK 0x00200000L
-#define GRBM_STATUS_SE2__BCI_BUSY_MASK 0x00400000L
-#define GRBM_STATUS_SE2__VGT_BUSY_MASK 0x00800000L
-#define GRBM_STATUS_SE2__PA_BUSY_MASK 0x01000000L
-#define GRBM_STATUS_SE2__TA_BUSY_MASK 0x02000000L
-#define GRBM_STATUS_SE2__SX_BUSY_MASK 0x04000000L
-#define GRBM_STATUS_SE2__SPI_BUSY_MASK 0x08000000L
-#define GRBM_STATUS_SE2__SC_BUSY_MASK 0x20000000L
-#define GRBM_STATUS_SE2__DB_BUSY_MASK 0x40000000L
-#define GRBM_STATUS_SE2__CB_BUSY_MASK 0x80000000L
-//GRBM_STATUS_SE3
-#define GRBM_STATUS_SE3__DB_CLEAN__SHIFT 0x1
-#define GRBM_STATUS_SE3__CB_CLEAN__SHIFT 0x2
-#define GRBM_STATUS_SE3__RMI_BUSY__SHIFT 0x15
-#define GRBM_STATUS_SE3__BCI_BUSY__SHIFT 0x16
-#define GRBM_STATUS_SE3__VGT_BUSY__SHIFT 0x17
-#define GRBM_STATUS_SE3__PA_BUSY__SHIFT 0x18
-#define GRBM_STATUS_SE3__TA_BUSY__SHIFT 0x19
-#define GRBM_STATUS_SE3__SX_BUSY__SHIFT 0x1a
-#define GRBM_STATUS_SE3__SPI_BUSY__SHIFT 0x1b
-#define GRBM_STATUS_SE3__SC_BUSY__SHIFT 0x1d
-#define GRBM_STATUS_SE3__DB_BUSY__SHIFT 0x1e
-#define GRBM_STATUS_SE3__CB_BUSY__SHIFT 0x1f
-#define GRBM_STATUS_SE3__DB_CLEAN_MASK 0x00000002L
-#define GRBM_STATUS_SE3__CB_CLEAN_MASK 0x00000004L
-#define GRBM_STATUS_SE3__RMI_BUSY_MASK 0x00200000L
-#define GRBM_STATUS_SE3__BCI_BUSY_MASK 0x00400000L
-#define GRBM_STATUS_SE3__VGT_BUSY_MASK 0x00800000L
-#define GRBM_STATUS_SE3__PA_BUSY_MASK 0x01000000L
-#define GRBM_STATUS_SE3__TA_BUSY_MASK 0x02000000L
-#define GRBM_STATUS_SE3__SX_BUSY_MASK 0x04000000L
-#define GRBM_STATUS_SE3__SPI_BUSY_MASK 0x08000000L
-#define GRBM_STATUS_SE3__SC_BUSY_MASK 0x20000000L
-#define GRBM_STATUS_SE3__DB_BUSY_MASK 0x40000000L
-#define GRBM_STATUS_SE3__CB_BUSY_MASK 0x80000000L
-//GRBM_READ_ERROR
-#define GRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x2
-#define GRBM_READ_ERROR__READ_PIPEID__SHIFT 0x14
-#define GRBM_READ_ERROR__READ_MEID__SHIFT 0x16
-#define GRBM_READ_ERROR__READ_ERROR__SHIFT 0x1f
-#define GRBM_READ_ERROR__READ_ADDRESS_MASK 0x0003FFFCL
-#define GRBM_READ_ERROR__READ_PIPEID_MASK 0x00300000L
-#define GRBM_READ_ERROR__READ_MEID_MASK 0x00C00000L
-#define GRBM_READ_ERROR__READ_ERROR_MASK 0x80000000L
-//GRBM_READ_ERROR2
-#define GRBM_READ_ERROR2__READ_REQUESTER_CPF__SHIFT 0x10
-#define GRBM_READ_ERROR2__READ_REQUESTER_RSMU__SHIFT 0x11
-#define GRBM_READ_ERROR2__READ_REQUESTER_RLC__SHIFT 0x12
-#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA__SHIFT 0x13
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF__SHIFT 0x14
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF__SHIFT 0x15
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF__SHIFT 0x16
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF__SHIFT 0x17
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0__SHIFT 0x18
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1__SHIFT 0x19
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2__SHIFT 0x1a
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3__SHIFT 0x1b
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0__SHIFT 0x1c
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1__SHIFT 0x1d
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2__SHIFT 0x1e
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3__SHIFT 0x1f
-#define GRBM_READ_ERROR2__READ_REQUESTER_CPF_MASK 0x00010000L
-#define GRBM_READ_ERROR2__READ_REQUESTER_RSMU_MASK 0x00020000L
-#define GRBM_READ_ERROR2__READ_REQUESTER_RLC_MASK 0x00040000L
-#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA_MASK 0x00080000L
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF_MASK 0x00100000L
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF_MASK 0x00200000L
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF_MASK 0x00400000L
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF_MASK 0x00800000L
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0_MASK 0x01000000L
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1_MASK 0x02000000L
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2_MASK 0x04000000L
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3_MASK 0x08000000L
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0_MASK 0x10000000L
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1_MASK 0x20000000L
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2_MASK 0x40000000L
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3_MASK 0x80000000L
-//GRBM_INT_CNTL
-#define GRBM_INT_CNTL__RDERR_INT_ENABLE__SHIFT 0x0
-#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE__SHIFT 0x13
-#define GRBM_INT_CNTL__RDERR_INT_ENABLE_MASK 0x00000001L
-#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE_MASK 0x00080000L
-//GRBM_TRAP_OP
-#define GRBM_TRAP_OP__RW__SHIFT 0x0
-#define GRBM_TRAP_OP__RW_MASK 0x00000001L
-//GRBM_TRAP_ADDR
-#define GRBM_TRAP_ADDR__DATA__SHIFT 0x0
-#define GRBM_TRAP_ADDR__DATA_MASK 0x0003FFFFL
-//GRBM_TRAP_ADDR_MSK
-#define GRBM_TRAP_ADDR_MSK__DATA__SHIFT 0x0
-#define GRBM_TRAP_ADDR_MSK__DATA_MASK 0x0003FFFFL
-//GRBM_TRAP_WD
-#define GRBM_TRAP_WD__DATA__SHIFT 0x0
-#define GRBM_TRAP_WD__DATA_MASK 0xFFFFFFFFL
-//GRBM_TRAP_WD_MSK
-#define GRBM_TRAP_WD_MSK__DATA__SHIFT 0x0
-#define GRBM_TRAP_WD_MSK__DATA_MASK 0xFFFFFFFFL
-//GRBM_DSM_BYPASS
-#define GRBM_DSM_BYPASS__BYPASS_BITS__SHIFT 0x0
-#define GRBM_DSM_BYPASS__BYPASS_EN__SHIFT 0x2
-#define GRBM_DSM_BYPASS__BYPASS_BITS_MASK 0x00000003L
-#define GRBM_DSM_BYPASS__BYPASS_EN_MASK 0x00000004L
-//GRBM_WRITE_ERROR
-#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC__SHIFT 0x0
-#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RSMU__SHIFT 0x1
-#define GRBM_WRITE_ERROR__WRITE_SSRCID__SHIFT 0x2
-#define GRBM_WRITE_ERROR__WRITE_VFID__SHIFT 0x5
-#define GRBM_WRITE_ERROR__WRITE_VF__SHIFT 0xc
-#define GRBM_WRITE_ERROR__WRITE_VMID__SHIFT 0xd
-#define GRBM_WRITE_ERROR__WRITE_PIPEID__SHIFT 0x14
-#define GRBM_WRITE_ERROR__WRITE_MEID__SHIFT 0x16
-#define GRBM_WRITE_ERROR__WRITE_ERROR__SHIFT 0x1f
-#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC_MASK 0x00000001L
-#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RSMU_MASK 0x00000002L
-#define GRBM_WRITE_ERROR__WRITE_SSRCID_MASK 0x0000001CL
-#define GRBM_WRITE_ERROR__WRITE_VFID_MASK 0x000001E0L
-#define GRBM_WRITE_ERROR__WRITE_VF_MASK 0x00001000L
-#define GRBM_WRITE_ERROR__WRITE_VMID_MASK 0x0001E000L
-#define GRBM_WRITE_ERROR__WRITE_PIPEID_MASK 0x00300000L
-#define GRBM_WRITE_ERROR__WRITE_MEID_MASK 0x00C00000L
-#define GRBM_WRITE_ERROR__WRITE_ERROR_MASK 0x80000000L
-//GRBM_IOV_ERROR
-#define GRBM_IOV_ERROR__IOV_ADDR__SHIFT 0x2
-#define GRBM_IOV_ERROR__IOV_VFID__SHIFT 0x14
-#define GRBM_IOV_ERROR__IOV_VF__SHIFT 0x1a
-#define GRBM_IOV_ERROR__IOV_OP__SHIFT 0x1b
-#define GRBM_IOV_ERROR__IOV_ERROR__SHIFT 0x1f
-#define GRBM_IOV_ERROR__IOV_ADDR_MASK 0x000FFFFCL
-#define GRBM_IOV_ERROR__IOV_VFID_MASK 0x03F00000L
-#define GRBM_IOV_ERROR__IOV_VF_MASK 0x04000000L
-#define GRBM_IOV_ERROR__IOV_OP_MASK 0x08000000L
-#define GRBM_IOV_ERROR__IOV_ERROR_MASK 0x80000000L
-//GRBM_CHIP_REVISION
-#define GRBM_CHIP_REVISION__CHIP_REVISION__SHIFT 0x0
-#define GRBM_CHIP_REVISION__CHIP_REVISION_MASK 0x000000FFL
-//GRBM_GFX_CNTL
-#define GRBM_GFX_CNTL__PIPEID__SHIFT 0x0
-#define GRBM_GFX_CNTL__MEID__SHIFT 0x2
-#define GRBM_GFX_CNTL__VMID__SHIFT 0x4
-#define GRBM_GFX_CNTL__QUEUEID__SHIFT 0x8
-#define GRBM_GFX_CNTL__PIPEID_MASK 0x00000003L
-#define GRBM_GFX_CNTL__MEID_MASK 0x0000000CL
-#define GRBM_GFX_CNTL__VMID_MASK 0x000000F0L
-#define GRBM_GFX_CNTL__QUEUEID_MASK 0x00000700L
-//GRBM_RSMU_CFG
-#define GRBM_RSMU_CFG__APERTURE_ID__SHIFT 0x0
-#define GRBM_RSMU_CFG__QOS__SHIFT 0xc
-#define GRBM_RSMU_CFG__POSTED_WR__SHIFT 0x10
-#define GRBM_RSMU_CFG__APERTURE_ID_MASK 0x00000FFFL
-#define GRBM_RSMU_CFG__QOS_MASK 0x0000F000L
-#define GRBM_RSMU_CFG__POSTED_WR_MASK 0x00010000L
-//GRBM_IH_CREDIT
-#define GRBM_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0
-#define GRBM_IH_CREDIT__IH_CLIENT_ID__SHIFT 0x10
-#define GRBM_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L
-#define GRBM_IH_CREDIT__IH_CLIENT_ID_MASK 0x00FF0000L
-//GRBM_PWR_CNTL2
-#define GRBM_PWR_CNTL2__PWR_REQUEST_HALT__SHIFT 0x10
-#define GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT__SHIFT 0x14
-#define GRBM_PWR_CNTL2__PWR_REQUEST_HALT_MASK 0x00010000L
-#define GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT_MASK 0x00100000L
-//GRBM_UTCL2_INVAL_RANGE_START
-#define GRBM_UTCL2_INVAL_RANGE_START__DATA__SHIFT 0x0
-#define GRBM_UTCL2_INVAL_RANGE_START__DATA_MASK 0x0003FFFFL
-//GRBM_UTCL2_INVAL_RANGE_END
-#define GRBM_UTCL2_INVAL_RANGE_END__DATA__SHIFT 0x0
-#define GRBM_UTCL2_INVAL_RANGE_END__DATA_MASK 0x0003FFFFL
-//GRBM_RSMU_READ_ERROR
-#define GRBM_RSMU_READ_ERROR__RSMU_READ_ADDRESS__SHIFT 0x2
-#define GRBM_RSMU_READ_ERROR__RSMU_READ_VF__SHIFT 0x14
-#define GRBM_RSMU_READ_ERROR__RSMU_READ_VFID__SHIFT 0x15
-#define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_TYPE__SHIFT 0x1b
-#define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR__SHIFT 0x1f
-#define GRBM_RSMU_READ_ERROR__RSMU_READ_ADDRESS_MASK 0x000FFFFCL
-#define GRBM_RSMU_READ_ERROR__RSMU_READ_VF_MASK 0x00100000L
-#define GRBM_RSMU_READ_ERROR__RSMU_READ_VFID_MASK 0x07E00000L
-#define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_TYPE_MASK 0x08000000L
-#define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_MASK 0x80000000L
-//GRBM_CHICKEN_BITS
-#define GRBM_CHICKEN_BITS__DISABLE_CP_VMID_RESET_REQ__SHIFT 0x0
-#define GRBM_CHICKEN_BITS__DISABLE_CP_VMID_RESET_REQ_MASK 0x00000001L
-//GRBM_NOWHERE
-#define GRBM_NOWHERE__DATA__SHIFT 0x0
-#define GRBM_NOWHERE__DATA_MASK 0xFFFFFFFFL
-//GRBM_SCRATCH_REG0
-#define GRBM_SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0
-#define GRBM_SCRATCH_REG0__SCRATCH_REG0_MASK 0xFFFFFFFFL
-//GRBM_SCRATCH_REG1
-#define GRBM_SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0
-#define GRBM_SCRATCH_REG1__SCRATCH_REG1_MASK 0xFFFFFFFFL
-//GRBM_SCRATCH_REG2
-#define GRBM_SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0
-#define GRBM_SCRATCH_REG2__SCRATCH_REG2_MASK 0xFFFFFFFFL
-//GRBM_SCRATCH_REG3
-#define GRBM_SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0
-#define GRBM_SCRATCH_REG3__SCRATCH_REG3_MASK 0xFFFFFFFFL
-//GRBM_SCRATCH_REG4
-#define GRBM_SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0
-#define GRBM_SCRATCH_REG4__SCRATCH_REG4_MASK 0xFFFFFFFFL
-//GRBM_SCRATCH_REG5
-#define GRBM_SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0
-#define GRBM_SCRATCH_REG5__SCRATCH_REG5_MASK 0xFFFFFFFFL
-//GRBM_SCRATCH_REG6
-#define GRBM_SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0
-#define GRBM_SCRATCH_REG6__SCRATCH_REG6_MASK 0xFFFFFFFFL
-//GRBM_SCRATCH_REG7
-#define GRBM_SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0
-#define GRBM_SCRATCH_REG7__SCRATCH_REG7_MASK 0xFFFFFFFFL
-
-
-// addressBlock: gc_cpdec
-//CP_CPC_STATUS
-#define CP_CPC_STATUS__MEC1_BUSY__SHIFT 0x0
-#define CP_CPC_STATUS__MEC2_BUSY__SHIFT 0x1
-#define CP_CPC_STATUS__DC0_BUSY__SHIFT 0x2
-#define CP_CPC_STATUS__DC1_BUSY__SHIFT 0x3
-#define CP_CPC_STATUS__RCIU1_BUSY__SHIFT 0x4
-#define CP_CPC_STATUS__RCIU2_BUSY__SHIFT 0x5
-#define CP_CPC_STATUS__ROQ1_BUSY__SHIFT 0x6
-#define CP_CPC_STATUS__ROQ2_BUSY__SHIFT 0x7
-#define CP_CPC_STATUS__TCIU_BUSY__SHIFT 0xa
-#define CP_CPC_STATUS__SCRATCH_RAM_BUSY__SHIFT 0xb
-#define CP_CPC_STATUS__QU_BUSY__SHIFT 0xc
-#define CP_CPC_STATUS__UTCL2IU_BUSY__SHIFT 0xd
-#define CP_CPC_STATUS__SAVE_RESTORE_BUSY__SHIFT 0xe
-#define CP_CPC_STATUS__CPG_CPC_BUSY__SHIFT 0x1d
-#define CP_CPC_STATUS__CPF_CPC_BUSY__SHIFT 0x1e
-#define CP_CPC_STATUS__CPC_BUSY__SHIFT 0x1f
-#define CP_CPC_STATUS__MEC1_BUSY_MASK 0x00000001L
-#define CP_CPC_STATUS__MEC2_BUSY_MASK 0x00000002L
-#define CP_CPC_STATUS__DC0_BUSY_MASK 0x00000004L
-#define CP_CPC_STATUS__DC1_BUSY_MASK 0x00000008L
-#define CP_CPC_STATUS__RCIU1_BUSY_MASK 0x00000010L
-#define CP_CPC_STATUS__RCIU2_BUSY_MASK 0x00000020L
-#define CP_CPC_STATUS__ROQ1_BUSY_MASK 0x00000040L
-#define CP_CPC_STATUS__ROQ2_BUSY_MASK 0x00000080L
-#define CP_CPC_STATUS__TCIU_BUSY_MASK 0x00000400L
-#define CP_CPC_STATUS__SCRATCH_RAM_BUSY_MASK 0x00000800L
-#define CP_CPC_STATUS__QU_BUSY_MASK 0x00001000L
-#define CP_CPC_STATUS__UTCL2IU_BUSY_MASK 0x00002000L
-#define CP_CPC_STATUS__SAVE_RESTORE_BUSY_MASK 0x00004000L
-#define CP_CPC_STATUS__CPG_CPC_BUSY_MASK 0x20000000L
-#define CP_CPC_STATUS__CPF_CPC_BUSY_MASK 0x40000000L
-#define CP_CPC_STATUS__CPC_BUSY_MASK 0x80000000L
-//CP_CPC_BUSY_STAT
-#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY__SHIFT 0x0
-#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY__SHIFT 0x1
-#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY__SHIFT 0x2
-#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY__SHIFT 0x3
-#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY__SHIFT 0x4
-#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT 0x5
-#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY__SHIFT 0x6
-#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY__SHIFT 0x7
-#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY__SHIFT 0x8
-#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY__SHIFT 0x9
-#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT 0xa
-#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY__SHIFT 0xb
-#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY__SHIFT 0xc
-#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY__SHIFT 0xd
-#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY__SHIFT 0x10
-#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY__SHIFT 0x11
-#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY__SHIFT 0x12
-#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY__SHIFT 0x13
-#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY__SHIFT 0x14
-#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT 0x15
-#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY__SHIFT 0x16
-#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY__SHIFT 0x17
-#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY__SHIFT 0x18
-#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY__SHIFT 0x19
-#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY__SHIFT 0x1a
-#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY__SHIFT 0x1b
-#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY__SHIFT 0x1c
-#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY__SHIFT 0x1d
-#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY_MASK 0x00000001L
-#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY_MASK 0x00000002L
-#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY_MASK 0x00000004L
-#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY_MASK 0x00000008L
-#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY_MASK 0x00000010L
-#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK 0x00000020L
-#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY_MASK 0x00000040L
-#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY_MASK 0x00000080L
-#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY_MASK 0x00000100L
-#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY_MASK 0x00000200L
-#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY_MASK 0x00000400L
-#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY_MASK 0x00000800L
-#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY_MASK 0x00001000L
-#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY_MASK 0x00002000L
-#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY_MASK 0x00010000L
-#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY_MASK 0x00020000L
-#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY_MASK 0x00040000L
-#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY_MASK 0x00080000L
-#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY_MASK 0x00100000L
-#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY_MASK 0x00200000L
-#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY_MASK 0x00400000L
-#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY_MASK 0x00800000L
-#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY_MASK 0x01000000L
-#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY_MASK 0x02000000L
-#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY_MASK 0x04000000L
-#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY_MASK 0x08000000L
-#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY_MASK 0x10000000L
-#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY_MASK 0x20000000L
-//CP_CPC_STALLED_STAT1
-#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL__SHIFT 0x3
-#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION__SHIFT 0x4
-#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL__SHIFT 0x6
-#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET__SHIFT 0x8
-#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU__SHIFT 0x9
-#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT 0xa
-#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA__SHIFT 0xd
-#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET__SHIFT 0x10
-#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU__SHIFT 0x11
-#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ__SHIFT 0x12
-#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA__SHIFT 0x15
-#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT 0x16
-#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x17
-#define CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS__SHIFT 0x18
-#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL_MASK 0x00000008L
-#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION_MASK 0x00000010L
-#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL_MASK 0x00000040L
-#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET_MASK 0x00000100L
-#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_MASK 0x00000200L
-#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ_MASK 0x00000400L
-#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA_MASK 0x00002000L
-#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET_MASK 0x00010000L
-#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_MASK 0x00020000L
-#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ_MASK 0x00040000L
-#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK 0x00200000L
-#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK 0x00400000L
-#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK 0x00800000L
-#define CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS_MASK 0x01000000L
-//CP_CPF_STATUS
-#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY__SHIFT 0x0
-#define CP_CPF_STATUS__CSF_BUSY__SHIFT 0x1
-#define CP_CPF_STATUS__ROQ_ALIGN_BUSY__SHIFT 0x4
-#define CP_CPF_STATUS__ROQ_RING_BUSY__SHIFT 0x5
-#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY__SHIFT 0x6
-#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY__SHIFT 0x7
-#define CP_CPF_STATUS__ROQ_STATE_BUSY__SHIFT 0x8
-#define CP_CPF_STATUS__ROQ_CE_RING_BUSY__SHIFT 0x9
-#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY__SHIFT 0xa
-#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY__SHIFT 0xb
-#define CP_CPF_STATUS__SEMAPHORE_BUSY__SHIFT 0xc
-#define CP_CPF_STATUS__INTERRUPT_BUSY__SHIFT 0xd
-#define CP_CPF_STATUS__TCIU_BUSY__SHIFT 0xe
-#define CP_CPF_STATUS__HQD_BUSY__SHIFT 0xf
-#define CP_CPF_STATUS__PRT_BUSY__SHIFT 0x10
-#define CP_CPF_STATUS__UTCL2IU_BUSY__SHIFT 0x11
-#define CP_CPF_STATUS__CPF_GFX_BUSY__SHIFT 0x1a
-#define CP_CPF_STATUS__CPF_CMP_BUSY__SHIFT 0x1b
-#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY__SHIFT 0x1c
-#define CP_CPF_STATUS__CPC_CPF_BUSY__SHIFT 0x1e
-#define CP_CPF_STATUS__CPF_BUSY__SHIFT 0x1f
-#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY_MASK 0x00000001L
-#define CP_CPF_STATUS__CSF_BUSY_MASK 0x00000002L
-#define CP_CPF_STATUS__ROQ_ALIGN_BUSY_MASK 0x00000010L
-#define CP_CPF_STATUS__ROQ_RING_BUSY_MASK 0x00000020L
-#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY_MASK 0x00000040L
-#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY_MASK 0x00000080L
-#define CP_CPF_STATUS__ROQ_STATE_BUSY_MASK 0x00000100L
-#define CP_CPF_STATUS__ROQ_CE_RING_BUSY_MASK 0x00000200L
-#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY_MASK 0x00000400L
-#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY_MASK 0x00000800L
-#define CP_CPF_STATUS__SEMAPHORE_BUSY_MASK 0x00001000L
-#define CP_CPF_STATUS__INTERRUPT_BUSY_MASK 0x00002000L
-#define CP_CPF_STATUS__TCIU_BUSY_MASK 0x00004000L
-#define CP_CPF_STATUS__HQD_BUSY_MASK 0x00008000L
-#define CP_CPF_STATUS__PRT_BUSY_MASK 0x00010000L
-#define CP_CPF_STATUS__UTCL2IU_BUSY_MASK 0x00020000L
-#define CP_CPF_STATUS__CPF_GFX_BUSY_MASK 0x04000000L
-#define CP_CPF_STATUS__CPF_CMP_BUSY_MASK 0x08000000L
-#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY_MASK 0x30000000L
-#define CP_CPF_STATUS__CPC_CPF_BUSY_MASK 0x40000000L
-#define CP_CPF_STATUS__CPF_BUSY_MASK 0x80000000L
-//CP_CPF_BUSY_STAT
-#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0
-#define CP_CPF_BUSY_STAT__CSF_RING_BUSY__SHIFT 0x1
-#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY__SHIFT 0x2
-#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY__SHIFT 0x3
-#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY__SHIFT 0x4
-#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY__SHIFT 0x5
-#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY__SHIFT 0x6
-#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY__SHIFT 0x7
-#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY__SHIFT 0x8
-#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS__SHIFT 0x9
-#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY__SHIFT 0xb
-#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY__SHIFT 0xc
-#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY__SHIFT 0xd
-#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY__SHIFT 0xe
-#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY__SHIFT 0xf
-#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY__SHIFT 0x10
-#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY__SHIFT 0x11
-#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY__SHIFT 0x12
-#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY__SHIFT 0x13
-#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY__SHIFT 0x14
-#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY__SHIFT 0x15
-#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY__SHIFT 0x16
-#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY__SHIFT 0x17
-#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY__SHIFT 0x18
-#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY__SHIFT 0x19
-#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY__SHIFT 0x1a
-#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY__SHIFT 0x1b
-#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY__SHIFT 0x1c
-#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY__SHIFT 0x1d
-#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY__SHIFT 0x1e
-#define CP_CPF_BUSY_STAT__HQD_IB_BUSY__SHIFT 0x1f
-#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x00000001L
-#define CP_CPF_BUSY_STAT__CSF_RING_BUSY_MASK 0x00000002L
-#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY_MASK 0x00000004L
-#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY_MASK 0x00000008L
-#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY_MASK 0x00000010L
-#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY_MASK 0x00000020L
-#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY_MASK 0x00000040L
-#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY_MASK 0x00000080L
-#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY_MASK 0x00000100L
-#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS_MASK 0x00000200L
-#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY_MASK 0x00000800L
-#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY_MASK 0x00001000L
-#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY_MASK 0x00002000L
-#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY_MASK 0x00004000L
-#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY_MASK 0x00008000L
-#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY_MASK 0x00010000L
-#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY_MASK 0x00020000L
-#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY_MASK 0x00040000L
-#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY_MASK 0x00080000L
-#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY_MASK 0x00100000L
-#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY_MASK 0x00200000L
-#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY_MASK 0x00400000L
-#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY_MASK 0x00800000L
-#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY_MASK 0x01000000L
-#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY_MASK 0x02000000L
-#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY_MASK 0x04000000L
-#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY_MASK 0x08000000L
-#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY_MASK 0x10000000L
-#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY_MASK 0x20000000L
-#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY_MASK 0x40000000L
-#define CP_CPF_BUSY_STAT__HQD_IB_BUSY_MASK 0x80000000L
-//CP_CPF_STALLED_STAT1
-#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA__SHIFT 0x0
-#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA__SHIFT 0x1
-#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA__SHIFT 0x2
-#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA__SHIFT 0x3
-#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE__SHIFT 0x5
-#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS__SHIFT 0x6
-#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT 0x7
-#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x8
-#define CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS__SHIFT 0x9
-#define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS__SHIFT 0xa
-#define CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE__SHIFT 0xb
-#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA_MASK 0x00000001L
-#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA_MASK 0x00000002L
-#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA_MASK 0x00000004L
-#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA_MASK 0x00000008L
-#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE_MASK 0x00000020L
-#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS_MASK 0x00000040L
-#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK 0x00000080L
-#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK 0x00000100L
-#define CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS_MASK 0x00000200L
-#define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS_MASK 0x00000400L
-#define CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE_MASK 0x00000800L
-//CP_CPC_GRBM_FREE_COUNT
-#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0
-#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x0000003FL
-//CP_MEC_CNTL
-#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE__SHIFT 0x4
-#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET__SHIFT 0x10
-#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET__SHIFT 0x11
-#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET__SHIFT 0x12
-#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET__SHIFT 0x13
-#define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET__SHIFT 0x14
-#define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET__SHIFT 0x15
-#define CP_MEC_CNTL__MEC_ME2_HALT__SHIFT 0x1c
-#define CP_MEC_CNTL__MEC_ME2_STEP__SHIFT 0x1d
-#define CP_MEC_CNTL__MEC_ME1_HALT__SHIFT 0x1e
-#define CP_MEC_CNTL__MEC_ME1_STEP__SHIFT 0x1f
-#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK 0x00000010L
-#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK 0x00010000L
-#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK 0x00020000L
-#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK 0x00040000L
-#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK 0x00080000L
-#define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK 0x00100000L
-#define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK 0x00200000L
-#define CP_MEC_CNTL__MEC_ME2_HALT_MASK 0x10000000L
-#define CP_MEC_CNTL__MEC_ME2_STEP_MASK 0x20000000L
-#define CP_MEC_CNTL__MEC_ME1_HALT_MASK 0x40000000L
-#define CP_MEC_CNTL__MEC_ME1_STEP_MASK 0x80000000L
-//CP_MEC_ME1_HEADER_DUMP
-#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0
-#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP_MASK 0xFFFFFFFFL
-//CP_MEC_ME2_HEADER_DUMP
-#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0
-#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP_MASK 0xFFFFFFFFL
-//CP_CPC_SCRATCH_INDEX
-#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0
-#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000001FFL
-//CP_CPC_SCRATCH_DATA
-#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0
-#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA_MASK 0xFFFFFFFFL
-//CP_CPF_GRBM_FREE_COUNT
-#define CP_CPF_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0
-#define CP_CPF_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x00000007L
-//CP_CPC_HALT_HYST_COUNT
-#define CP_CPC_HALT_HYST_COUNT__COUNT__SHIFT 0x0
-#define CP_CPC_HALT_HYST_COUNT__COUNT_MASK 0x0000000FL
-//CP_PRT_LOD_STATS_CNTL0
-#define CP_PRT_LOD_STATS_CNTL0__BU_SIZE__SHIFT 0x0
-#define CP_PRT_LOD_STATS_CNTL0__BU_SIZE_MASK 0xFFFFFFFFL
-//CP_PRT_LOD_STATS_CNTL1
-#define CP_PRT_LOD_STATS_CNTL1__BASE_LO__SHIFT 0x0
-#define CP_PRT_LOD_STATS_CNTL1__BASE_LO_MASK 0xFFFFFFFFL
-//CP_PRT_LOD_STATS_CNTL2
-#define CP_PRT_LOD_STATS_CNTL2__BASE_HI__SHIFT 0x0
-#define CP_PRT_LOD_STATS_CNTL2__BASE_HI_MASK 0x000003FFL
-//CP_PRT_LOD_STATS_CNTL3
-#define CP_PRT_LOD_STATS_CNTL3__INTERVAL__SHIFT 0x2
-#define CP_PRT_LOD_STATS_CNTL3__RESET_CNT__SHIFT 0xa
-#define CP_PRT_LOD_STATS_CNTL3__RESET_FORCE__SHIFT 0x12
-#define CP_PRT_LOD_STATS_CNTL3__REPORT_AND_RESET__SHIFT 0x13
-#define CP_PRT_LOD_STATS_CNTL3__MC_VMID__SHIFT 0x17
-#define CP_PRT_LOD_STATS_CNTL3__CACHE_POLICY__SHIFT 0x1c
-#define CP_PRT_LOD_STATS_CNTL3__INTERVAL_MASK 0x000003FCL
-#define CP_PRT_LOD_STATS_CNTL3__RESET_CNT_MASK 0x0003FC00L
-#define CP_PRT_LOD_STATS_CNTL3__RESET_FORCE_MASK 0x00040000L
-#define CP_PRT_LOD_STATS_CNTL3__REPORT_AND_RESET_MASK 0x00080000L
-#define CP_PRT_LOD_STATS_CNTL3__MC_VMID_MASK 0x07800000L
-#define CP_PRT_LOD_STATS_CNTL3__CACHE_POLICY_MASK 0x10000000L
-//CP_CE_COMPARE_COUNT
-#define CP_CE_COMPARE_COUNT__COMPARE_COUNT__SHIFT 0x0
-#define CP_CE_COMPARE_COUNT__COMPARE_COUNT_MASK 0xFFFFFFFFL
-//CP_CE_DE_COUNT
-#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0
-#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xFFFFFFFFL
-//CP_DE_CE_COUNT
-#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT__SHIFT 0x0
-#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT_MASK 0xFFFFFFFFL
-//CP_DE_LAST_INVAL_COUNT
-#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT__SHIFT 0x0
-#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT_MASK 0xFFFFFFFFL
-//CP_DE_DE_COUNT
-#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0
-#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xFFFFFFFFL
-//CP_STALLED_STAT3
-#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0
-#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT 0x1
-#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER__SHIFT 0x2
-#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY__SHIFT 0x3
-#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY__SHIFT 0x4
-#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY__SHIFT 0x5
-#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV__SHIFT 0x6
-#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV__SHIFT 0x7
-#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT 0xa
-#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG__SHIFT 0xb
-#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER__SHIFT 0xc
-#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW__SHIFT 0xd
-#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE__SHIFT 0xe
-#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS__SHIFT 0xf
-#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x10
-#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x11
-#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE__SHIFT 0x12
-#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x13
-#define CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS__SHIFT 0x14
-#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV_MASK 0x00000001L
-#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV_MASK 0x00000002L
-#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER_MASK 0x00000004L
-#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY_MASK 0x00000008L
-#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY_MASK 0x00000010L
-#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY_MASK 0x00000020L
-#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV_MASK 0x00000040L
-#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV_MASK 0x00000080L
-#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA_MASK 0x00000400L
-#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG_MASK 0x00000800L
-#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_MASK 0x00001000L
-#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW_MASK 0x00002000L
-#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE_MASK 0x00004000L
-#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS_MASK 0x00008000L
-#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM_MASK 0x00010000L
-#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00020000L
-#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE_MASK 0x00040000L
-#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS_MASK 0x00080000L
-#define CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS_MASK 0x00100000L
-//CP_STALLED_STAT1
-#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV__SHIFT 0x0
-#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV__SHIFT 0x2
-#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV__SHIFT 0x4
-#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT 0xa
-#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG__SHIFT 0xb
-#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM__SHIFT 0xc
-#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0xd
-#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA__SHIFT 0xe
-#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA__SHIFT 0xf
-#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE__SHIFT 0x17
-#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE__SHIFT 0x18
-#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE__SHIFT 0x19
-#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ__SHIFT 0x1a
-#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ__SHIFT 0x1b
-#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ__SHIFT 0x1c
-#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION__SHIFT 0x1d
-#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV_MASK 0x00000001L
-#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_MASK 0x00000004L
-#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_MASK 0x00000010L
-#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG_MASK 0x00000400L
-#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG_MASK 0x00000800L
-#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM_MASK 0x00001000L
-#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00002000L
-#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA_MASK 0x00004000L
-#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA_MASK 0x00008000L
-#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE_MASK 0x00800000L
-#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE_MASK 0x01000000L
-#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE_MASK 0x02000000L
-#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ_MASK 0x04000000L
-#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ_MASK 0x08000000L
-#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ_MASK 0x10000000L
-#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION_MASK 0x20000000L
-//CP_STALLED_STAT2
-#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0
-#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV__SHIFT 0x1
-#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV__SHIFT 0x2
-#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING__SHIFT 0x4
-#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING__SHIFT 0x5
-#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA__SHIFT 0x8
-#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER__SHIFT 0x9
-#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT 0xa
-#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME__SHIFT 0xb
-#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV__SHIFT 0xc
-#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV__SHIFT 0xd
-#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP__SHIFT 0xe
-#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH__SHIFT 0xf
-#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x10
-#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x11
-#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ__SHIFT 0x12
-#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x13
-#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x14
-#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE__SHIFT 0x15
-#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM__SHIFT 0x16
-#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING__SHIFT 0x17
-#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING__SHIFT 0x18
-#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE__SHIFT 0x19
-#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE__SHIFT 0x1a
-#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM__SHIFT 0x1b
-#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION__SHIFT 0x1c
-#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE__SHIFT 0x1d
-#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS__SHIFT 0x1e
-#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN__SHIFT 0x1f
-#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV_MASK 0x00000001L
-#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV_MASK 0x00000002L
-#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV_MASK 0x00000004L
-#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING_MASK 0x00000010L
-#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING_MASK 0x00000020L
-#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA_MASK 0x00000100L
-#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER_MASK 0x00000200L
-#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER_MASK 0x00000400L
-#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME_MASK 0x00000800L
-#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV_MASK 0x00001000L
-#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV_MASK 0x00002000L
-#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP_MASK 0x00004000L
-#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH_MASK 0x00008000L
-#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x00010000L
-#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x00020000L
-#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ_MASK 0x00040000L
-#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM_MASK 0x00080000L
-#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00100000L
-#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE_MASK 0x00200000L
-#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM_MASK 0x00400000L
-#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING_MASK 0x00800000L
-#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING_MASK 0x01000000L
-#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE_MASK 0x02000000L
-#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE_MASK 0x04000000L
-#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM_MASK 0x08000000L
-#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION_MASK 0x10000000L
-#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE_MASK 0x20000000L
-#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS_MASK 0x40000000L
-#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN_MASK 0x80000000L
-//CP_BUSY_STAT
-#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0
-#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO__SHIFT 0x6
-#define CP_BUSY_STAT__PFP_PARSING_PACKETS__SHIFT 0x7
-#define CP_BUSY_STAT__ME_PARSING_PACKETS__SHIFT 0x8
-#define CP_BUSY_STAT__RCIU_PFP_BUSY__SHIFT 0x9
-#define CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT 0xa
-#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY__SHIFT 0xc
-#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING__SHIFT 0xd
-#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS__SHIFT 0xe
-#define CP_BUSY_STAT__GFX_CONTEXT_BUSY__SHIFT 0xf
-#define CP_BUSY_STAT__ME_PARSER_BUSY__SHIFT 0x11
-#define CP_BUSY_STAT__EOP_DONE_BUSY__SHIFT 0x12
-#define CP_BUSY_STAT__STRM_OUT_BUSY__SHIFT 0x13
-#define CP_BUSY_STAT__PIPE_STATS_BUSY__SHIFT 0x14
-#define CP_BUSY_STAT__RCIU_CE_BUSY__SHIFT 0x15
-#define CP_BUSY_STAT__CE_PARSING_PACKETS__SHIFT 0x16
-#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x00000001L
-#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO_MASK 0x00000040L
-#define CP_BUSY_STAT__PFP_PARSING_PACKETS_MASK 0x00000080L
-#define CP_BUSY_STAT__ME_PARSING_PACKETS_MASK 0x00000100L
-#define CP_BUSY_STAT__RCIU_PFP_BUSY_MASK 0x00000200L
-#define CP_BUSY_STAT__RCIU_ME_BUSY_MASK 0x00000400L
-#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY_MASK 0x00001000L
-#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING_MASK 0x00002000L
-#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS_MASK 0x00004000L
-#define CP_BUSY_STAT__GFX_CONTEXT_BUSY_MASK 0x00008000L
-#define CP_BUSY_STAT__ME_PARSER_BUSY_MASK 0x00020000L
-#define CP_BUSY_STAT__EOP_DONE_BUSY_MASK 0x00040000L
-#define CP_BUSY_STAT__STRM_OUT_BUSY_MASK 0x00080000L
-#define CP_BUSY_STAT__PIPE_STATS_BUSY_MASK 0x00100000L
-#define CP_BUSY_STAT__RCIU_CE_BUSY_MASK 0x00200000L
-#define CP_BUSY_STAT__CE_PARSING_PACKETS_MASK 0x00400000L
-//CP_STAT
-#define CP_STAT__ROQ_RING_BUSY__SHIFT 0x9
-#define CP_STAT__ROQ_INDIRECT1_BUSY__SHIFT 0xa
-#define CP_STAT__ROQ_INDIRECT2_BUSY__SHIFT 0xb
-#define CP_STAT__ROQ_STATE_BUSY__SHIFT 0xc
-#define CP_STAT__DC_BUSY__SHIFT 0xd
-#define CP_STAT__UTCL2IU_BUSY__SHIFT 0xe
-#define CP_STAT__PFP_BUSY__SHIFT 0xf
-#define CP_STAT__MEQ_BUSY__SHIFT 0x10
-#define CP_STAT__ME_BUSY__SHIFT 0x11
-#define CP_STAT__QUERY_BUSY__SHIFT 0x12
-#define CP_STAT__SEMAPHORE_BUSY__SHIFT 0x13
-#define CP_STAT__INTERRUPT_BUSY__SHIFT 0x14
-#define CP_STAT__SURFACE_SYNC_BUSY__SHIFT 0x15
-#define CP_STAT__DMA_BUSY__SHIFT 0x16
-#define CP_STAT__RCIU_BUSY__SHIFT 0x17
-#define CP_STAT__SCRATCH_RAM_BUSY__SHIFT 0x18
-#define CP_STAT__CE_BUSY__SHIFT 0x1a
-#define CP_STAT__TCIU_BUSY__SHIFT 0x1b
-#define CP_STAT__ROQ_CE_RING_BUSY__SHIFT 0x1c
-#define CP_STAT__ROQ_CE_INDIRECT1_BUSY__SHIFT 0x1d
-#define CP_STAT__ROQ_CE_INDIRECT2_BUSY__SHIFT 0x1e
-#define CP_STAT__CP_BUSY__SHIFT 0x1f
-#define CP_STAT__ROQ_RING_BUSY_MASK 0x00000200L
-#define CP_STAT__ROQ_INDIRECT1_BUSY_MASK 0x00000400L
-#define CP_STAT__ROQ_INDIRECT2_BUSY_MASK 0x00000800L
-#define CP_STAT__ROQ_STATE_BUSY_MASK 0x00001000L
-#define CP_STAT__DC_BUSY_MASK 0x00002000L
-#define CP_STAT__UTCL2IU_BUSY_MASK 0x00004000L
-#define CP_STAT__PFP_BUSY_MASK 0x00008000L
-#define CP_STAT__MEQ_BUSY_MASK 0x00010000L
-#define CP_STAT__ME_BUSY_MASK 0x00020000L
-#define CP_STAT__QUERY_BUSY_MASK 0x00040000L
-#define CP_STAT__SEMAPHORE_BUSY_MASK 0x00080000L
-#define CP_STAT__INTERRUPT_BUSY_MASK 0x00100000L
-#define CP_STAT__SURFACE_SYNC_BUSY_MASK 0x00200000L
-#define CP_STAT__DMA_BUSY_MASK 0x00400000L
-#define CP_STAT__RCIU_BUSY_MASK 0x00800000L
-#define CP_STAT__SCRATCH_RAM_BUSY_MASK 0x01000000L
-#define CP_STAT__CE_BUSY_MASK 0x04000000L
-#define CP_STAT__TCIU_BUSY_MASK 0x08000000L
-#define CP_STAT__ROQ_CE_RING_BUSY_MASK 0x10000000L
-#define CP_STAT__ROQ_CE_INDIRECT1_BUSY_MASK 0x20000000L
-#define CP_STAT__ROQ_CE_INDIRECT2_BUSY_MASK 0x40000000L
-#define CP_STAT__CP_BUSY_MASK 0x80000000L
-//CP_ME_HEADER_DUMP
-#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP__SHIFT 0x0
-#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP_MASK 0xFFFFFFFFL
-//CP_PFP_HEADER_DUMP
-#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP__SHIFT 0x0
-#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP_MASK 0xFFFFFFFFL
-//CP_GRBM_FREE_COUNT
-#define CP_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0
-#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS__SHIFT 0x8
-#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP__SHIFT 0x10
-#define CP_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x0000003FL
-#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS_MASK 0x00003F00L
-#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP_MASK 0x003F0000L
-//CP_CE_HEADER_DUMP
-#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP__SHIFT 0x0
-#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP_MASK 0xFFFFFFFFL
-//CP_PFP_INSTR_PNTR
-#define CP_PFP_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0
-#define CP_PFP_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL
-//CP_ME_INSTR_PNTR
-#define CP_ME_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0
-#define CP_ME_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL
-//CP_CE_INSTR_PNTR
-#define CP_CE_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0
-#define CP_CE_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL
-//CP_MEC1_INSTR_PNTR
-#define CP_MEC1_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0
-#define CP_MEC1_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL
-//CP_MEC2_INSTR_PNTR
-#define CP_MEC2_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0
-#define CP_MEC2_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL
-//CP_CSF_STAT
-#define CP_CSF_STAT__BUFFER_REQUEST_COUNT__SHIFT 0x8
-#define CP_CSF_STAT__BUFFER_REQUEST_COUNT_MASK 0x0001FF00L
-//CP_ME_CNTL
-#define CP_ME_CNTL__CE_INVALIDATE_ICACHE__SHIFT 0x4
-#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE__SHIFT 0x6
-#define CP_ME_CNTL__ME_INVALIDATE_ICACHE__SHIFT 0x8
-#define CP_ME_CNTL__CE_PIPE0_RESET__SHIFT 0x10
-#define CP_ME_CNTL__CE_PIPE1_RESET__SHIFT 0x11
-#define CP_ME_CNTL__PFP_PIPE0_RESET__SHIFT 0x12
-#define CP_ME_CNTL__PFP_PIPE1_RESET__SHIFT 0x13
-#define CP_ME_CNTL__ME_PIPE0_RESET__SHIFT 0x14
-#define CP_ME_CNTL__ME_PIPE1_RESET__SHIFT 0x15
-#define CP_ME_CNTL__CE_HALT__SHIFT 0x18
-#define CP_ME_CNTL__CE_STEP__SHIFT 0x19
-#define CP_ME_CNTL__PFP_HALT__SHIFT 0x1a
-#define CP_ME_CNTL__PFP_STEP__SHIFT 0x1b
-#define CP_ME_CNTL__ME_HALT__SHIFT 0x1c
-#define CP_ME_CNTL__ME_STEP__SHIFT 0x1d
-#define CP_ME_CNTL__CE_INVALIDATE_ICACHE_MASK 0x00000010L
-#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE_MASK 0x00000040L
-#define CP_ME_CNTL__ME_INVALIDATE_ICACHE_MASK 0x00000100L
-#define CP_ME_CNTL__CE_PIPE0_RESET_MASK 0x00010000L
-#define CP_ME_CNTL__CE_PIPE1_RESET_MASK 0x00020000L
-#define CP_ME_CNTL__PFP_PIPE0_RESET_MASK 0x00040000L
-#define CP_ME_CNTL__PFP_PIPE1_RESET_MASK 0x00080000L
-#define CP_ME_CNTL__ME_PIPE0_RESET_MASK 0x00100000L
-#define CP_ME_CNTL__ME_PIPE1_RESET_MASK 0x00200000L
-#define CP_ME_CNTL__CE_HALT_MASK 0x01000000L
-#define CP_ME_CNTL__CE_STEP_MASK 0x02000000L
-#define CP_ME_CNTL__PFP_HALT_MASK 0x04000000L
-#define CP_ME_CNTL__PFP_STEP_MASK 0x08000000L
-#define CP_ME_CNTL__ME_HALT_MASK 0x10000000L
-#define CP_ME_CNTL__ME_STEP_MASK 0x20000000L
-//CP_CNTX_STAT
-#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS__SHIFT 0x0
-#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT__SHIFT 0x8
-#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS__SHIFT 0x14
-#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT__SHIFT 0x1c
-#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS_MASK 0x000000FFL
-#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT_MASK 0x00000700L
-#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS_MASK 0x0FF00000L
-#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT_MASK 0x70000000L
-//CP_ME_PREEMPTION
-#define CP_ME_PREEMPTION__OBSOLETE__SHIFT 0x0
-#define CP_ME_PREEMPTION__OBSOLETE_MASK 0x00000001L
-//CP_ROQ_THRESHOLDS
-#define CP_ROQ_THRESHOLDS__IB1_START__SHIFT 0x0
-#define CP_ROQ_THRESHOLDS__IB2_START__SHIFT 0x8
-#define CP_ROQ_THRESHOLDS__IB1_START_MASK 0x000000FFL
-#define CP_ROQ_THRESHOLDS__IB2_START_MASK 0x0000FF00L
-//CP_MEQ_STQ_THRESHOLD
-#define CP_MEQ_STQ_THRESHOLD__STQ_START__SHIFT 0x0
-#define CP_MEQ_STQ_THRESHOLD__STQ_START_MASK 0x000000FFL
-//CP_RB2_RPTR
-#define CP_RB2_RPTR__RB_RPTR__SHIFT 0x0
-#define CP_RB2_RPTR__RB_RPTR_MASK 0x000FFFFFL
-//CP_RB1_RPTR
-#define CP_RB1_RPTR__RB_RPTR__SHIFT 0x0
-#define CP_RB1_RPTR__RB_RPTR_MASK 0x000FFFFFL
-//CP_RB0_RPTR
-#define CP_RB0_RPTR__RB_RPTR__SHIFT 0x0
-#define CP_RB0_RPTR__RB_RPTR_MASK 0x000FFFFFL
-//CP_RB_RPTR
-#define CP_RB_RPTR__RB_RPTR__SHIFT 0x0
-#define CP_RB_RPTR__RB_RPTR_MASK 0x000FFFFFL
-//CP_RB_WPTR_DELAY
-#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT 0x0
-#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT 0x1c
-#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK 0x0FFFFFFFL
-#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK 0xF0000000L
-//CP_RB_WPTR_POLL_CNTL
-#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT 0x0
-#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
-#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK 0x0000FFFFL
-#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
-//CP_ROQ1_THRESHOLDS
-#define CP_ROQ1_THRESHOLDS__RB1_START__SHIFT 0x0
-#define CP_ROQ1_THRESHOLDS__RB2_START__SHIFT 0x8
-#define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT 0x10
-#define CP_ROQ1_THRESHOLDS__R1_IB1_START__SHIFT 0x18
-#define CP_ROQ1_THRESHOLDS__RB1_START_MASK 0x000000FFL
-#define CP_ROQ1_THRESHOLDS__RB2_START_MASK 0x0000FF00L
-#define CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK 0x00FF0000L
-#define CP_ROQ1_THRESHOLDS__R1_IB1_START_MASK 0xFF000000L
-//CP_ROQ2_THRESHOLDS
-#define CP_ROQ2_THRESHOLDS__R2_IB1_START__SHIFT 0x0
-#define CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT 0x8
-#define CP_ROQ2_THRESHOLDS__R1_IB2_START__SHIFT 0x10
-#define CP_ROQ2_THRESHOLDS__R2_IB2_START__SHIFT 0x18
-#define CP_ROQ2_THRESHOLDS__R2_IB1_START_MASK 0x000000FFL
-#define CP_ROQ2_THRESHOLDS__R0_IB2_START_MASK 0x0000FF00L
-#define CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK 0x00FF0000L
-#define CP_ROQ2_THRESHOLDS__R2_IB2_START_MASK 0xFF000000L
-//CP_STQ_THRESHOLDS
-#define CP_STQ_THRESHOLDS__STQ0_START__SHIFT 0x0
-#define CP_STQ_THRESHOLDS__STQ1_START__SHIFT 0x8
-#define CP_STQ_THRESHOLDS__STQ2_START__SHIFT 0x10
-#define CP_STQ_THRESHOLDS__STQ0_START_MASK 0x000000FFL
-#define CP_STQ_THRESHOLDS__STQ1_START_MASK 0x0000FF00L
-#define CP_STQ_THRESHOLDS__STQ2_START_MASK 0x00FF0000L
-//CP_QUEUE_THRESHOLDS
-#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT 0x0
-#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT 0x8
-#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START_MASK 0x0000003FL
-#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START_MASK 0x00003F00L
-//CP_MEQ_THRESHOLDS
-#define CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT 0x0
-#define CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT 0x8
-#define CP_MEQ_THRESHOLDS__MEQ1_START_MASK 0x000000FFL
-#define CP_MEQ_THRESHOLDS__MEQ2_START_MASK 0x0000FF00L
-//CP_ROQ_AVAIL
-#define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT 0x0
-#define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 0x10
-#define CP_ROQ_AVAIL__ROQ_CNT_RING_MASK 0x000007FFL
-#define CP_ROQ_AVAIL__ROQ_CNT_IB1_MASK 0x07FF0000L
-//CP_STQ_AVAIL
-#define CP_STQ_AVAIL__STQ_CNT__SHIFT 0x0
-#define CP_STQ_AVAIL__STQ_CNT_MASK 0x000001FFL
-//CP_ROQ2_AVAIL
-#define CP_ROQ2_AVAIL__ROQ_CNT_IB2__SHIFT 0x0
-#define CP_ROQ2_AVAIL__ROQ_CNT_IB2_MASK 0x000007FFL
-//CP_MEQ_AVAIL
-#define CP_MEQ_AVAIL__MEQ_CNT__SHIFT 0x0
-#define CP_MEQ_AVAIL__MEQ_CNT_MASK 0x000003FFL
-//CP_CMD_INDEX
-#define CP_CMD_INDEX__CMD_INDEX__SHIFT 0x0
-#define CP_CMD_INDEX__CMD_ME_SEL__SHIFT 0xc
-#define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT 0x10
-#define CP_CMD_INDEX__CMD_INDEX_MASK 0x000007FFL
-#define CP_CMD_INDEX__CMD_ME_SEL_MASK 0x00003000L
-#define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK 0x00070000L
-//CP_CMD_DATA
-#define CP_CMD_DATA__CMD_DATA__SHIFT 0x0
-#define CP_CMD_DATA__CMD_DATA_MASK 0xFFFFFFFFL
-//CP_ROQ_RB_STAT
-#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY__SHIFT 0x0
-#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY__SHIFT 0x10
-#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY_MASK 0x000003FFL
-#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY_MASK 0x03FF0000L
-//CP_ROQ_IB1_STAT
-#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1__SHIFT 0x0
-#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1__SHIFT 0x10
-#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK 0x000003FFL
-#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1_MASK 0x03FF0000L
-//CP_ROQ_IB2_STAT
-#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2__SHIFT 0x0
-#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2__SHIFT 0x10
-#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2_MASK 0x000003FFL
-#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2_MASK 0x03FF0000L
-//CP_STQ_STAT
-#define CP_STQ_STAT__STQ_RPTR__SHIFT 0x0
-#define CP_STQ_STAT__STQ_RPTR_MASK 0x000003FFL
-//CP_STQ_WR_STAT
-#define CP_STQ_WR_STAT__STQ_WPTR__SHIFT 0x0
-#define CP_STQ_WR_STAT__STQ_WPTR_MASK 0x000003FFL
-//CP_MEQ_STAT
-#define CP_MEQ_STAT__MEQ_RPTR__SHIFT 0x0
-#define CP_MEQ_STAT__MEQ_WPTR__SHIFT 0x10
-#define CP_MEQ_STAT__MEQ_RPTR_MASK 0x000003FFL
-#define CP_MEQ_STAT__MEQ_WPTR_MASK 0x03FF0000L
-//CP_CEQ1_AVAIL
-#define CP_CEQ1_AVAIL__CEQ_CNT_RING__SHIFT 0x0
-#define CP_CEQ1_AVAIL__CEQ_CNT_IB1__SHIFT 0x10
-#define CP_CEQ1_AVAIL__CEQ_CNT_RING_MASK 0x000007FFL
-#define CP_CEQ1_AVAIL__CEQ_CNT_IB1_MASK 0x07FF0000L
-//CP_CEQ2_AVAIL
-#define CP_CEQ2_AVAIL__CEQ_CNT_IB2__SHIFT 0x0
-#define CP_CEQ2_AVAIL__CEQ_CNT_IB2_MASK 0x000007FFL
-//CP_CE_ROQ_RB_STAT
-#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT 0x0
-#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT 0x10
-#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY_MASK 0x000003FFL
-#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK 0x03FF0000L
-//CP_CE_ROQ_IB1_STAT
-#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1__SHIFT 0x0
-#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT 0x10
-#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1_MASK 0x000003FFL
-#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1_MASK 0x03FF0000L
-//CP_CE_ROQ_IB2_STAT
-#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2__SHIFT 0x0
-#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2__SHIFT 0x10
-#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2_MASK 0x000003FFL
-#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2_MASK 0x03FF0000L
-#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED__SHIFT 0x16
-#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17
-#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED_MASK 0x00400000L
-#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L
-
-
-// addressBlock: gc_padec
-//VGT_VTX_VECT_EJECT_REG
-#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT 0x0
-#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK 0x0000007FL
-//VGT_DMA_DATA_FIFO_DEPTH
-#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH__SHIFT 0x0
-#define VGT_DMA_DATA_FIFO_DEPTH__DMA2DRAW_FIFO_DEPTH__SHIFT 0x9
-#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH_MASK 0x000001FFL
-#define VGT_DMA_DATA_FIFO_DEPTH__DMA2DRAW_FIFO_DEPTH_MASK 0x0007FE00L
-//VGT_DMA_REQ_FIFO_DEPTH
-#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH__SHIFT 0x0
-#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH_MASK 0x0000003FL
-//VGT_DRAW_INIT_FIFO_DEPTH
-#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH__SHIFT 0x0
-#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH_MASK 0x0000003FL
-//VGT_LAST_COPY_STATE
-#define VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT 0x0
-#define VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT 0x10
-#define VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L
-#define VGT_LAST_COPY_STATE__DST_STATE_ID_MASK 0x00070000L
-//VGT_CACHE_INVALIDATION
-#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT 0x0
-#define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT__SHIFT 0x4
-#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER__SHIFT 0x5
-#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT 0x6
-#define VGT_CACHE_INVALIDATION__USE_GS_DONE__SHIFT 0x9
-#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD__SHIFT 0xb
-#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN__SHIFT 0xc
-#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH__SHIFT 0xd
-#define VGT_CACHE_INVALIDATION__ES_LIMIT__SHIFT 0x10
-#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG__SHIFT 0x15
-#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_1__SHIFT 0x16
-#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_2__SHIFT 0x19
-#define VGT_CACHE_INVALIDATION__EN_WAVE_MERGE__SHIFT 0x1c
-#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_EOI__SHIFT 0x1d
-#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION_MASK 0x00000003L
-#define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT_MASK 0x00000010L
-#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER_MASK 0x00000020L
-#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN_MASK 0x000000C0L
-#define VGT_CACHE_INVALIDATION__USE_GS_DONE_MASK 0x00000200L
-#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD_MASK 0x00000800L
-#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN_MASK 0x00001000L
-#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH_MASK 0x00002000L
-#define VGT_CACHE_INVALIDATION__ES_LIMIT_MASK 0x001F0000L
-#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_MASK 0x00200000L
-#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_1_MASK 0x01C00000L
-#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_2_MASK 0x0E000000L
-#define VGT_CACHE_INVALIDATION__EN_WAVE_MERGE_MASK 0x10000000L
-#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_EOI_MASK 0x20000000L
-//VGT_STRMOUT_DELAY
-#define VGT_STRMOUT_DELAY__SKIP_DELAY__SHIFT 0x0
-#define VGT_STRMOUT_DELAY__SE0_WD_DELAY__SHIFT 0x8
-#define VGT_STRMOUT_DELAY__SE1_WD_DELAY__SHIFT 0xb
-#define VGT_STRMOUT_DELAY__SE2_WD_DELAY__SHIFT 0xe
-#define VGT_STRMOUT_DELAY__SE3_WD_DELAY__SHIFT 0x11
-#define VGT_STRMOUT_DELAY__SKIP_DELAY_MASK 0x000000FFL
-#define VGT_STRMOUT_DELAY__SE0_WD_DELAY_MASK 0x00000700L
-#define VGT_STRMOUT_DELAY__SE1_WD_DELAY_MASK 0x00003800L
-#define VGT_STRMOUT_DELAY__SE2_WD_DELAY_MASK 0x0001C000L
-#define VGT_STRMOUT_DELAY__SE3_WD_DELAY_MASK 0x000E0000L
-//VGT_FIFO_DEPTHS
-#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH__SHIFT 0x0
-#define VGT_FIFO_DEPTHS__RESERVED_0__SHIFT 0x7
-#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH__SHIFT 0x8
-#define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH__SHIFT 0x16
-#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH_MASK 0x0000007FL
-#define VGT_FIFO_DEPTHS__RESERVED_0_MASK 0x00000080L
-#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH_MASK 0x003FFF00L
-#define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH_MASK 0x0FC00000L
-//VGT_GS_VERTEX_REUSE
-#define VGT_GS_VERTEX_REUSE__VERT_REUSE__SHIFT 0x0
-#define VGT_GS_VERTEX_REUSE__VERT_REUSE_MASK 0x0000001FL
-//VGT_MC_LAT_CNTL
-#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES__SHIFT 0x0
-#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES_MASK 0x0000000FL
-//IA_CNTL_STATUS
-#define IA_CNTL_STATUS__IA_BUSY__SHIFT 0x0
-#define IA_CNTL_STATUS__IA_DMA_BUSY__SHIFT 0x1
-#define IA_CNTL_STATUS__IA_DMA_REQ_BUSY__SHIFT 0x2
-#define IA_CNTL_STATUS__IA_GRP_BUSY__SHIFT 0x3
-#define IA_CNTL_STATUS__IA_ADC_BUSY__SHIFT 0x4
-#define IA_CNTL_STATUS__IA_BUSY_MASK 0x00000001L
-#define IA_CNTL_STATUS__IA_DMA_BUSY_MASK 0x00000002L
-#define IA_CNTL_STATUS__IA_DMA_REQ_BUSY_MASK 0x00000004L
-#define IA_CNTL_STATUS__IA_GRP_BUSY_MASK 0x00000008L
-#define IA_CNTL_STATUS__IA_ADC_BUSY_MASK 0x00000010L
-//VGT_CNTL_STATUS
-#define VGT_CNTL_STATUS__VGT_BUSY__SHIFT 0x0
-#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY__SHIFT 0x1
-#define VGT_CNTL_STATUS__VGT_OUT_BUSY__SHIFT 0x2
-#define VGT_CNTL_STATUS__VGT_PT_BUSY__SHIFT 0x3
-#define VGT_CNTL_STATUS__VGT_TE_BUSY__SHIFT 0x4
-#define VGT_CNTL_STATUS__VGT_VR_BUSY__SHIFT 0x5
-#define VGT_CNTL_STATUS__VGT_PI_BUSY__SHIFT 0x6
-#define VGT_CNTL_STATUS__VGT_GS_BUSY__SHIFT 0x7
-#define VGT_CNTL_STATUS__VGT_HS_BUSY__SHIFT 0x8
-#define VGT_CNTL_STATUS__VGT_TE11_BUSY__SHIFT 0x9
-#define VGT_CNTL_STATUS__VGT_PRIMGEN_BUSY__SHIFT 0xa
-#define VGT_CNTL_STATUS__VGT_BUSY_MASK 0x00000001L
-#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY_MASK 0x00000002L
-#define VGT_CNTL_STATUS__VGT_OUT_BUSY_MASK 0x00000004L
-#define VGT_CNTL_STATUS__VGT_PT_BUSY_MASK 0x00000008L
-#define VGT_CNTL_STATUS__VGT_TE_BUSY_MASK 0x00000010L
-#define VGT_CNTL_STATUS__VGT_VR_BUSY_MASK 0x00000020L
-#define VGT_CNTL_STATUS__VGT_PI_BUSY_MASK 0x00000040L
-#define VGT_CNTL_STATUS__VGT_GS_BUSY_MASK 0x00000080L
-#define VGT_CNTL_STATUS__VGT_HS_BUSY_MASK 0x00000100L
-#define VGT_CNTL_STATUS__VGT_TE11_BUSY_MASK 0x00000200L
-#define VGT_CNTL_STATUS__VGT_PRIMGEN_BUSY_MASK 0x00000400L
-//WD_CNTL_STATUS
-#define WD_CNTL_STATUS__WD_BUSY__SHIFT 0x0
-#define WD_CNTL_STATUS__WD_SPL_DMA_BUSY__SHIFT 0x1
-#define WD_CNTL_STATUS__WD_SPL_DI_BUSY__SHIFT 0x2
-#define WD_CNTL_STATUS__WD_ADC_BUSY__SHIFT 0x3
-#define WD_CNTL_STATUS__WD_BUSY_MASK 0x00000001L
-#define WD_CNTL_STATUS__WD_SPL_DMA_BUSY_MASK 0x00000002L
-#define WD_CNTL_STATUS__WD_SPL_DI_BUSY_MASK 0x00000004L
-#define WD_CNTL_STATUS__WD_ADC_BUSY_MASK 0x00000008L
-//CC_GC_PRIM_CONFIG
-#define CC_GC_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10
-#define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18
-#define CC_GC_PRIM_CONFIG__INACTIVE_IA_MASK 0x00030000L
-#define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0x0F000000L
-//GC_USER_PRIM_CONFIG
-#define GC_USER_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10
-#define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18
-#define GC_USER_PRIM_CONFIG__INACTIVE_IA_MASK 0x00030000L
-#define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0x0F000000L
-//WD_QOS
-#define WD_QOS__DRAW_STALL__SHIFT 0x0
-#define WD_QOS__DRAW_STALL_MASK 0x00000001L
-//WD_UTCL1_CNTL
-#define WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0
-#define WD_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17
-#define WD_UTCL1_CNTL__DROP_MODE__SHIFT 0x18
-#define WD_UTCL1_CNTL__BYPASS__SHIFT 0x19
-#define WD_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a
-#define WD_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b
-#define WD_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c
-#define WD_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d
-#define WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
-#define WD_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L
-#define WD_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L
-#define WD_UTCL1_CNTL__BYPASS_MASK 0x02000000L
-#define WD_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L
-#define WD_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L
-#define WD_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L
-#define WD_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L
-//WD_UTCL1_STATUS
-#define WD_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
-#define WD_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
-#define WD_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
-#define WD_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8
-#define WD_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10
-#define WD_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18
-#define WD_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
-#define WD_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
-#define WD_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
-#define WD_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L
-#define WD_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L
-#define WD_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L
-//IA_UTCL1_CNTL
-#define IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0
-#define IA_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17
-#define IA_UTCL1_CNTL__DROP_MODE__SHIFT 0x18
-#define IA_UTCL1_CNTL__BYPASS__SHIFT 0x19
-#define IA_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a
-#define IA_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b
-#define IA_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c
-#define IA_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d
-#define IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
-#define IA_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L
-#define IA_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L
-#define IA_UTCL1_CNTL__BYPASS_MASK 0x02000000L
-#define IA_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L
-#define IA_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L
-#define IA_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L
-#define IA_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L
-//IA_UTCL1_STATUS
-#define IA_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
-#define IA_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
-#define IA_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
-#define IA_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8
-#define IA_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10
-#define IA_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18
-#define IA_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
-#define IA_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
-#define IA_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
-#define IA_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L
-#define IA_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L
-#define IA_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L
-//VGT_SYS_CONFIG
-#define VGT_SYS_CONFIG__DUAL_CORE_EN__SHIFT 0x0
-#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP__SHIFT 0x1
-#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE__SHIFT 0x7
-#define VGT_SYS_CONFIG__DUAL_CORE_EN_MASK 0x00000001L
-#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP_MASK 0x0000007EL
-#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE_MASK 0x00000080L
-//VGT_VS_MAX_WAVE_ID
-#define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0
-#define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL
-//VGT_GS_MAX_WAVE_ID
-#define VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0
-#define VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL
-//GFX_PIPE_CONTROL
-#define GFX_PIPE_CONTROL__HYSTERESIS_CNT__SHIFT 0x0
-#define GFX_PIPE_CONTROL__RESERVED__SHIFT 0xd
-#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN__SHIFT 0x10
-#define GFX_PIPE_CONTROL__HYSTERESIS_CNT_MASK 0x00001FFFL
-#define GFX_PIPE_CONTROL__RESERVED_MASK 0x0000E000L
-#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN_MASK 0x00010000L
-//CC_GC_SHADER_ARRAY_CONFIG
-#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x10
-#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xFFFF0000L
-//GC_USER_SHADER_ARRAY_CONFIG
-#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x10
-#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xFFFF0000L
-//VGT_DMA_PRIMITIVE_TYPE
-#define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0
-#define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x0000003FL
-//VGT_DMA_CONTROL
-#define VGT_DMA_CONTROL__PRIMGROUP_SIZE__SHIFT 0x0
-#define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP__SHIFT 0x11
-#define VGT_DMA_CONTROL__SWITCH_ON_EOI__SHIFT 0x13
-#define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP__SHIFT 0x14
-#define VGT_DMA_CONTROL__EN_INST_OPT_BASIC__SHIFT 0x15
-#define VGT_DMA_CONTROL__EN_INST_OPT_ADV__SHIFT 0x16
-#define VGT_DMA_CONTROL__HW_USE_ONLY__SHIFT 0x17
-#define VGT_DMA_CONTROL__PRIMGROUP_SIZE_MASK 0x0000FFFFL
-#define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP_MASK 0x00020000L
-#define VGT_DMA_CONTROL__SWITCH_ON_EOI_MASK 0x00080000L
-#define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP_MASK 0x00100000L
-#define VGT_DMA_CONTROL__EN_INST_OPT_BASIC_MASK 0x00200000L
-#define VGT_DMA_CONTROL__EN_INST_OPT_ADV_MASK 0x00400000L
-#define VGT_DMA_CONTROL__HW_USE_ONLY_MASK 0x00800000L
-//VGT_DMA_LS_HS_CONFIG
-#define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8
-#define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x00003F00L
-//WD_BUF_RESOURCE_1
-#define WD_BUF_RESOURCE_1__POS_BUF_SIZE__SHIFT 0x0
-#define WD_BUF_RESOURCE_1__INDEX_BUF_SIZE__SHIFT 0x10
-#define WD_BUF_RESOURCE_1__POS_BUF_SIZE_MASK 0x0000FFFFL
-#define WD_BUF_RESOURCE_1__INDEX_BUF_SIZE_MASK 0xFFFF0000L
-//WD_BUF_RESOURCE_2
-#define WD_BUF_RESOURCE_2__PARAM_BUF_SIZE__SHIFT 0x0
-#define WD_BUF_RESOURCE_2__ADDR_MODE__SHIFT 0xf
-#define WD_BUF_RESOURCE_2__CNTL_SB_BUF_SIZE__SHIFT 0x10
-#define WD_BUF_RESOURCE_2__PARAM_BUF_SIZE_MASK 0x00001FFFL
-#define WD_BUF_RESOURCE_2__ADDR_MODE_MASK 0x00008000L
-#define WD_BUF_RESOURCE_2__CNTL_SB_BUF_SIZE_MASK 0xFFFF0000L
-//PA_CL_CNTL_STATUS
-#define PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED__SHIFT 0x0
-#define PA_CL_CNTL_STATUS__UTC_RETRY_DETECTED__SHIFT 0x1
-#define PA_CL_CNTL_STATUS__UTC_PRT_DETECTED__SHIFT 0x2
-#define PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED_MASK 0x00000001L
-#define PA_CL_CNTL_STATUS__UTC_RETRY_DETECTED_MASK 0x00000002L
-#define PA_CL_CNTL_STATUS__UTC_PRT_DETECTED_MASK 0x00000004L
-//PA_CL_ENHANCE
-#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT 0x0
-#define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT 0x1
-#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL__SHIFT 0x3
-#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE__SHIFT 0x4
-#define PA_CL_ENHANCE__IGNORE_PIPELINE_RESET__SHIFT 0x6
-#define PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS__SHIFT 0x7
-#define PA_CL_ENHANCE__NGG_PA_TO_ALL_SC__SHIFT 0x8
-#define PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION__SHIFT 0x9
-#define PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER__SHIFT 0xb
-#define PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH__SHIFT 0xc
-#define PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH__SHIFT 0xe
-#define PA_CL_ENHANCE__ECO_SPARE3__SHIFT 0x1c
-#define PA_CL_ENHANCE__ECO_SPARE2__SHIFT 0x1d
-#define PA_CL_ENHANCE__ECO_SPARE1__SHIFT 0x1e
-#define PA_CL_ENHANCE__ECO_SPARE0__SHIFT 0x1f
-#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK 0x00000001L
-#define PA_CL_ENHANCE__NUM_CLIP_SEQ_MASK 0x00000006L
-#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL_MASK 0x00000008L
-#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE_MASK 0x00000010L
-#define PA_CL_ENHANCE__IGNORE_PIPELINE_RESET_MASK 0x00000040L
-#define PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS_MASK 0x00000080L
-#define PA_CL_ENHANCE__NGG_PA_TO_ALL_SC_MASK 0x00000100L
-#define PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION_MASK 0x00000600L
-#define PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER_MASK 0x00000800L
-#define PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH_MASK 0x00003000L
-#define PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH_MASK 0x0001C000L
-#define PA_CL_ENHANCE__ECO_SPARE3_MASK 0x10000000L
-#define PA_CL_ENHANCE__ECO_SPARE2_MASK 0x20000000L
-#define PA_CL_ENHANCE__ECO_SPARE1_MASK 0x40000000L
-#define PA_CL_ENHANCE__ECO_SPARE0_MASK 0x80000000L
-//PA_SU_CNTL_STATUS
-#define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT 0x1f
-#define PA_SU_CNTL_STATUS__SU_BUSY_MASK 0x80000000L
-//PA_SC_FIFO_DEPTH_CNTL
-#define PA_SC_FIFO_DEPTH_CNTL__DEPTH__SHIFT 0x0
-#define PA_SC_FIFO_DEPTH_CNTL__DEPTH_MASK 0x000003FFL
-//PA_SC_P3D_TRAP_SCREEN_HV_LOCK
-#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0
-#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L
-//PA_SC_HP3D_TRAP_SCREEN_HV_LOCK
-#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0
-#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L
-//PA_SC_TRAP_SCREEN_HV_LOCK
-#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0
-#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L
-//PA_SC_FORCE_EOV_MAX_CNTS
-#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT 0x0
-#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT 0x10
-#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_MASK 0x0000FFFFL
-#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_MASK 0xFFFF0000L
-//PA_SC_BINNER_EVENT_CNTL_0
-#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0__SHIFT 0x0
-#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1__SHIFT 0x2
-#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2__SHIFT 0x4
-#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3__SHIFT 0x6
-#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS__SHIFT 0x8
-#define PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE__SHIFT 0xa
-#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH__SHIFT 0xc
-#define PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH__SHIFT 0xe
-#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC__SHIFT 0x10
-#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9__SHIFT 0x12
-#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET__SHIFT 0x14
-#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE__SHIFT 0x16
-#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END__SHIFT 0x18
-#define PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT__SHIFT 0x1a
-#define PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH__SHIFT 0x1c
-#define PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH__SHIFT 0x1e
-#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0_MASK 0x00000003L
-#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1_MASK 0x0000000CL
-#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2_MASK 0x00000030L
-#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3_MASK 0x000000C0L
-#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS_MASK 0x00000300L
-#define PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE_MASK 0x00000C00L
-#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_MASK 0x00003000L
-#define PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH_MASK 0x0000C000L
-#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC_MASK 0x00030000L
-#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9_MASK 0x000C0000L
-#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET_MASK 0x00300000L
-#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE_MASK 0x00C00000L
-#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END_MASK 0x03000000L
-#define PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT_MASK 0x0C000000L
-#define PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH_MASK 0x30000000L
-#define PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH_MASK 0xC0000000L
-//PA_SC_BINNER_EVENT_CNTL_1
-#define PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH__SHIFT 0x0
-#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT__SHIFT 0x2
-#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM__SHIFT 0x4
-#define PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT__SHIFT 0x6
-#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT__SHIFT 0x8
-#define PA_SC_BINNER_EVENT_CNTL_1__ZPASS_DONE__SHIFT 0xa
-#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT__SHIFT 0xc
-#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START__SHIFT 0xe
-#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP__SHIFT 0x10
-#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START__SHIFT 0x12
-#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP__SHIFT 0x14
-#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE__SHIFT 0x16
-#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT__SHIFT 0x18
-#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_GS_OUTPUT__SHIFT 0x1a
-#define PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT__SHIFT 0x1c
-#define PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH__SHIFT 0x1e
-#define PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH_MASK 0x00000003L
-#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT_MASK 0x0000000CL
-#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM_MASK 0x00000030L
-#define PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT_MASK 0x000000C0L
-#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT_MASK 0x00000300L
-#define PA_SC_BINNER_EVENT_CNTL_1__ZPASS_DONE_MASK 0x00000C00L
-#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT_MASK 0x00003000L
-#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START_MASK 0x0000C000L
-#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP_MASK 0x00030000L
-#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START_MASK 0x000C0000L
-#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP_MASK 0x00300000L
-#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE_MASK 0x00C00000L
-#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT_MASK 0x03000000L
-#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_GS_OUTPUT_MASK 0x0C000000L
-#define PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT_MASK 0x30000000L
-#define PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH_MASK 0xC0000000L
-//PA_SC_BINNER_EVENT_CNTL_2
-#define PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS__SHIFT 0x0
-#define PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT__SHIFT 0x2
-#define PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE__SHIFT 0x4
-#define PA_SC_BINNER_EVENT_CNTL_2__CS_CONTEXT_DONE__SHIFT 0x6
-#define PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH__SHIFT 0x8
-#define PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER__SHIFT 0xa
-#define PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT__SHIFT 0xc
-#define PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ__SHIFT 0xe
-#define PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS__SHIFT 0x10
-#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_SX_TS__SHIFT 0x12
-#define PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV__SHIFT 0x14
-#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS__SHIFT 0x16
-#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META__SHIFT 0x18
-#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS__SHIFT 0x1a
-#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META__SHIFT 0x1c
-#define PA_SC_BINNER_EVENT_CNTL_2__CS_DONE__SHIFT 0x1e
-#define PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS_MASK 0x00000003L
-#define PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT_MASK 0x0000000CL
-#define PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE_MASK 0x00000030L
-#define PA_SC_BINNER_EVENT_CNTL_2__CS_CONTEXT_DONE_MASK 0x000000C0L
-#define PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH_MASK 0x00000300L
-#define PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER_MASK 0x00000C00L
-#define PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT_MASK 0x00003000L
-#define PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ_MASK 0x0000C000L
-#define PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS_MASK 0x00030000L
-#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_SX_TS_MASK 0x000C0000L
-#define PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV_MASK 0x00300000L
-#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS_MASK 0x00C00000L
-#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META_MASK 0x03000000L
-#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS_MASK 0x0C000000L
-#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META_MASK 0x30000000L
-#define PA_SC_BINNER_EVENT_CNTL_2__CS_DONE_MASK 0xC0000000L
-//PA_SC_BINNER_EVENT_CNTL_3
-#define PA_SC_BINNER_EVENT_CNTL_3__PS_DONE__SHIFT 0x0
-#define PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA__SHIFT 0x2
-#define PA_SC_BINNER_EVENT_CNTL_3__SX_CB_RAT_ACK_REQUEST__SHIFT 0x4
-#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START__SHIFT 0x6
-#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP__SHIFT 0x8
-#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER__SHIFT 0xa
-#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FLUSH__SHIFT 0xc
-#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH__SHIFT 0xe
-#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL__SHIFT 0x10
-#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP__SHIFT 0x12
-#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET__SHIFT 0x14
-#define PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND__SHIFT 0x16
-#define PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC__SHIFT 0x18
-#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE__SHIFT 0x1a
-#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_LEGACY_PIPELINE__SHIFT 0x1c
-#define PA_SC_BINNER_EVENT_CNTL_3__RESERVED_63__SHIFT 0x1e
-#define PA_SC_BINNER_EVENT_CNTL_3__PS_DONE_MASK 0x00000003L
-#define PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA_MASK 0x0000000CL
-#define PA_SC_BINNER_EVENT_CNTL_3__SX_CB_RAT_ACK_REQUEST_MASK 0x00000030L
-#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START_MASK 0x000000C0L
-#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP_MASK 0x00000300L
-#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER_MASK 0x00000C00L
-#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FLUSH_MASK 0x00003000L
-#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH_MASK 0x0000C000L
-#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL_MASK 0x00030000L
-#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP_MASK 0x000C0000L
-#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET_MASK 0x00300000L
-#define PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND_MASK 0x00C00000L
-#define PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC_MASK 0x03000000L
-#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE_MASK 0x0C000000L
-#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_LEGACY_PIPELINE_MASK 0x30000000L
-#define PA_SC_BINNER_EVENT_CNTL_3__RESERVED_63_MASK 0xC0000000L
-//PA_SC_BINNER_TIMEOUT_COUNTER
-#define PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD__SHIFT 0x0
-#define PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD_MASK 0xFFFFFFFFL
-//PA_SC_BINNER_PERF_CNTL_0
-#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD__SHIFT 0x0
-#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD__SHIFT 0xa
-#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD__SHIFT 0x14
-#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD__SHIFT 0x17
-#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD_MASK 0x000003FFL
-#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD_MASK 0x000FFC00L
-#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD_MASK 0x00700000L
-#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD_MASK 0x03800000L
-//PA_SC_BINNER_PERF_CNTL_1
-#define PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT 0x0
-#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT 0x5
-#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD__SHIFT 0xa
-#define PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK 0x0000001FL
-#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK 0x000003E0L
-#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD_MASK 0x03FFFC00L
-//PA_SC_BINNER_PERF_CNTL_2
-#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD__SHIFT 0x0
-#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD__SHIFT 0xb
-#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD_MASK 0x000007FFL
-#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD_MASK 0x003FF800L
-//PA_SC_BINNER_PERF_CNTL_3
-#define PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD__SHIFT 0x0
-#define PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD_MASK 0xFFFFFFFFL
-//PA_SC_FIFO_SIZE
-#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT 0x0
-#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT 0x6
-#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT 0xf
-#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT 0x15
-#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE_MASK 0x0000003FL
-#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE_MASK 0x00007FC0L
-#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE_MASK 0x001F8000L
-#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE_MASK 0xFFE00000L
-//PA_SC_IF_FIFO_SIZE
-#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE__SHIFT 0x0
-#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE__SHIFT 0x6
-#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE__SHIFT 0xc
-#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE__SHIFT 0x12
-#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE_MASK 0x0000003FL
-#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE_MASK 0x00000FC0L
-#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE_MASK 0x0003F000L
-#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE_MASK 0x00FC0000L
-//PA_SC_PKR_WAVE_TABLE_CNTL
-#define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE__SHIFT 0x0
-#define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE_MASK 0x0000003FL
-//PA_UTCL1_CNTL1
-#define PA_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0
-#define PA_UTCL1_CNTL1__GPUVM_64K_DEFAULT__SHIFT 0x1
-#define PA_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2
-#define PA_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3
-#define PA_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5
-#define PA_UTCL1_CNTL1__CLIENTID__SHIFT 0x7
-#define PA_UTCL1_CNTL1__SPARE__SHIFT 0x10
-#define PA_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11
-#define PA_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12
-#define PA_UTCL1_CNTL1__REG_INV_VMID__SHIFT 0x13
-#define PA_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17
-#define PA_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT 0x18
-#define PA_UTCL1_CNTL1__INVALIDATE_ALL_VMID__SHIFT 0x19
-#define PA_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a
-#define PA_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b
-#define PA_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
-#define PA_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
-#define PA_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L
-#define PA_UTCL1_CNTL1__GPUVM_64K_DEFAULT_MASK 0x00000002L
-#define PA_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L
-#define PA_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L
-#define PA_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L
-#define PA_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L
-#define PA_UTCL1_CNTL1__SPARE_MASK 0x00010000L
-#define PA_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L
-#define PA_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L
-#define PA_UTCL1_CNTL1__REG_INV_VMID_MASK 0x00780000L
-#define PA_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L
-#define PA_UTCL1_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L
-#define PA_UTCL1_CNTL1__INVALIDATE_ALL_VMID_MASK 0x02000000L
-#define PA_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L
-#define PA_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L
-#define PA_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L
-#define PA_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L
-//PA_UTCL1_CNTL2
-#define PA_UTCL1_CNTL2__SPARE1__SHIFT 0x0
-#define PA_UTCL1_CNTL2__SPARE2__SHIFT 0x8
-#define PA_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9
-#define PA_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa
-#define PA_UTCL1_CNTL2__SPARE3__SHIFT 0xb
-#define PA_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc
-#define PA_UTCL1_CNTL2__ENABLE_SHOOTDOWN_OPT__SHIFT 0xd
-#define PA_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe
-#define PA_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf
-#define PA_UTCL1_CNTL2__SPARE4__SHIFT 0x10
-#define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12
-#define PA_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13
-#define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14
-#define PA_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT 0x15
-#define PA_UTCL1_CNTL2__SPARE5__SHIFT 0x19
-#define PA_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a
-#define PA_UTCL1_CNTL2__RESERVED__SHIFT 0x1b
-#define PA_UTCL1_CNTL2__SPARE1_MASK 0x000000FFL
-#define PA_UTCL1_CNTL2__SPARE2_MASK 0x00000100L
-#define PA_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L
-#define PA_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L
-#define PA_UTCL1_CNTL2__SPARE3_MASK 0x00000800L
-#define PA_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L
-#define PA_UTCL1_CNTL2__ENABLE_SHOOTDOWN_OPT_MASK 0x00002000L
-#define PA_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L
-#define PA_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L
-#define PA_UTCL1_CNTL2__SPARE4_MASK 0x00030000L
-#define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L
-#define PA_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L
-#define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L
-#define PA_UTCL1_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L
-#define PA_UTCL1_CNTL2__SPARE5_MASK 0x02000000L
-#define PA_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L
-#define PA_UTCL1_CNTL2__RESERVED_MASK 0xF8000000L
-//PA_SIDEBAND_REQUEST_DELAYS
-#define PA_SIDEBAND_REQUEST_DELAYS__RETRY_DELAY__SHIFT 0x0
-#define PA_SIDEBAND_REQUEST_DELAYS__INITIAL_DELAY__SHIFT 0x10
-#define PA_SIDEBAND_REQUEST_DELAYS__RETRY_DELAY_MASK 0x0000FFFFL
-#define PA_SIDEBAND_REQUEST_DELAYS__INITIAL_DELAY_MASK 0xFFFF0000L
-//PA_SC_ENHANCE
-#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER__SHIFT 0x0
-#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX__SHIFT 0x1
-#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX__SHIFT 0x2
-#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS__SHIFT 0x3
-#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID__SHIFT 0x4
-#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX__SHIFT 0x5
-#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER__SHIFT 0x6
-#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION__SHIFT 0x7
-#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT 0x8
-#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE__SHIFT 0x9
-#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE__SHIFT 0xa
-#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE__SHIFT 0xb
-#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS__SHIFT 0xc
-#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE__SHIFT 0xd
-#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE__SHIFT 0xe
-#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE__SHIFT 0xf
-#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST__SHIFT 0x10
-#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING__SHIFT 0x11
-#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY__SHIFT 0x12
-#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING__SHIFT 0x13
-#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING__SHIFT 0x14
-#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS__SHIFT 0x15
-#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID__SHIFT 0x16
-#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO__SHIFT 0x17
-#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT 0x18
-#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING__SHIFT 0x19
-#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET__SHIFT 0x1a
-#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET__SHIFT 0x1b
-#define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE__SHIFT 0x1c
-#define PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING__SHIFT 0x1d
-#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK 0x00000001L
-#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX_MASK 0x00000002L
-#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX_MASK 0x00000004L
-#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS_MASK 0x00000008L
-#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID_MASK 0x00000010L
-#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX_MASK 0x00000020L
-#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER_MASK 0x00000040L
-#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION_MASK 0x00000080L
-#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK 0x00000100L
-#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE_MASK 0x00000200L
-#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK 0x00000400L
-#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE_MASK 0x00000800L
-#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS_MASK 0x00001000L
-#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE_MASK 0x00002000L
-#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE_MASK 0x00004000L
-#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE_MASK 0x00008000L
-#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST_MASK 0x00010000L
-#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING_MASK 0x00020000L
-#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY_MASK 0x00040000L
-#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING_MASK 0x00080000L
-#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING_MASK 0x00100000L
-#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS_MASK 0x00200000L
-#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID_MASK 0x00400000L
-#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO_MASK 0x00800000L
-#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK 0x01000000L
-#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING_MASK 0x02000000L
-#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET_MASK 0x04000000L
-#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET_MASK 0x08000000L
-#define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE_MASK 0x10000000L
-#define PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING_MASK 0x20000000L
-//PA_SC_ENHANCE_1
-#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE__SHIFT 0x0
-#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE__SHIFT 0x1
-#define PA_SC_ENHANCE_1__DISABLE_SC_BINNING__SHIFT 0x3
-#define PA_SC_ENHANCE_1__BYPASS_PBB__SHIFT 0x4
-#define PA_SC_ENHANCE_1__ECO_SPARE0__SHIFT 0x5
-#define PA_SC_ENHANCE_1__ECO_SPARE1__SHIFT 0x6
-#define PA_SC_ENHANCE_1__ECO_SPARE2__SHIFT 0x7
-#define PA_SC_ENHANCE_1__ECO_SPARE3__SHIFT 0x8
-#define PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB__SHIFT 0x9
-#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT__SHIFT 0xa
-#define PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM__SHIFT 0xb
-#define PA_SC_ENHANCE_1__DISABLE_PACKER_GRAD_FDCE_ENHANCE__SHIFT 0xd
-#define PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE__SHIFT 0xe
-#define PA_SC_ENHANCE_1__DISABLE_SC_PIPELINE_RESET_LEGACY_MODE_TRANSITION__SHIFT 0xf
-#define PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE__SHIFT 0x10
-#define PA_SC_ENHANCE_1__ALLOW_SCALE_LINE_WIDTH_PAD_WITH_BINNING__SHIFT 0x11
-#define PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION__SHIFT 0x12
-#define PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS__SHIFT 0x13
-#define PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION__SHIFT 0x14
-#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION__SHIFT 0x15
-#define PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION__SHIFT 0x16
-#define PA_SC_ENHANCE_1__RSVD__SHIFT 0x17
-#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE_MASK 0x00000001L
-#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_MASK 0x00000006L
-#define PA_SC_ENHANCE_1__DISABLE_SC_BINNING_MASK 0x00000008L
-#define PA_SC_ENHANCE_1__BYPASS_PBB_MASK 0x00000010L
-#define PA_SC_ENHANCE_1__ECO_SPARE0_MASK 0x00000020L
-#define PA_SC_ENHANCE_1__ECO_SPARE1_MASK 0x00000040L
-#define PA_SC_ENHANCE_1__ECO_SPARE2_MASK 0x00000080L
-#define PA_SC_ENHANCE_1__ECO_SPARE3_MASK 0x00000100L
-#define PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB_MASK 0x00000200L
-#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT_MASK 0x00000400L
-#define PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM_MASK 0x00000800L
-#define PA_SC_ENHANCE_1__DISABLE_PACKER_GRAD_FDCE_ENHANCE_MASK 0x00002000L
-#define PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE_MASK 0x00004000L
-#define PA_SC_ENHANCE_1__DISABLE_SC_PIPELINE_RESET_LEGACY_MODE_TRANSITION_MASK 0x00008000L
-#define PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE_MASK 0x00010000L
-#define PA_SC_ENHANCE_1__ALLOW_SCALE_LINE_WIDTH_PAD_WITH_BINNING_MASK 0x00020000L
-#define PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION_MASK 0x00040000L
-#define PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS_MASK 0x00080000L
-#define PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION_MASK 0x00100000L
-#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION_MASK 0x00200000L
-#define PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION_MASK 0x00400000L
-#define PA_SC_ENHANCE_1__RSVD_MASK 0xFF800000L
-//PA_SC_DSM_CNTL
-#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0__SHIFT 0x0
-#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1__SHIFT 0x1
-#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0_MASK 0x00000001L
-#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1_MASK 0x00000002L
-//PA_SC_TILE_STEERING_CREST_OVERRIDE
-#define PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE__SHIFT 0x0
-#define PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT__SHIFT 0x1
-#define PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT__SHIFT 0x5
-#define PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE_MASK 0x00000001L
-#define PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT_MASK 0x00000006L
-#define PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT_MASK 0x00000060L
-
-
-// addressBlock: gc_sqdec
-//SQ_CONFIG
-#define SQ_CONFIG__UNUSED__SHIFT 0x0
-#define SQ_CONFIG__OVERRIDE_ALU_BUSY__SHIFT 0x7
-#define SQ_CONFIG__OVERRIDE_LDS_IDX_BUSY__SHIFT 0xb
-#define SQ_CONFIG__EARLY_TA_DONE_DISABLE__SHIFT 0xc
-#define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE__SHIFT 0xd
-#define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE__SHIFT 0xe
-#define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE__SHIFT 0xf
-#define SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE__SHIFT 0x10
-#define SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE__SHIFT 0x11
-#define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS__SHIFT 0x12
-#define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS__SHIFT 0x13
-#define SQ_CONFIG__REPLAY_SLEEP_CNT__SHIFT 0x15
-#define SQ_CONFIG__DISABLE_SP_VGPR_WRITE_SKIP__SHIFT 0x1c
-#define SQ_CONFIG__DISABLE_SP_REDUNDANT_THREAD_GATING__SHIFT 0x1d
-#define SQ_CONFIG__DISABLE_FLAT_SOFT_CLAUSE__SHIFT 0x1e
-#define SQ_CONFIG__DISABLE_MIMG_SOFT_CLAUSE__SHIFT 0x1f
-#define SQ_CONFIG__UNUSED_MASK 0x0000007FL
-#define SQ_CONFIG__OVERRIDE_ALU_BUSY_MASK 0x00000080L
-#define SQ_CONFIG__OVERRIDE_LDS_IDX_BUSY_MASK 0x00000800L
-#define SQ_CONFIG__EARLY_TA_DONE_DISABLE_MASK 0x00001000L
-#define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE_MASK 0x00002000L
-#define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE_MASK 0x00004000L
-#define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE_MASK 0x00008000L
-#define SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE_MASK 0x00010000L
-#define SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE_MASK 0x00020000L
-#define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS_MASK 0x00040000L
-#define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS_MASK 0x00180000L
-#define SQ_CONFIG__REPLAY_SLEEP_CNT_MASK 0x0FE00000L
-#define SQ_CONFIG__DISABLE_SP_VGPR_WRITE_SKIP_MASK 0x10000000L
-#define SQ_CONFIG__DISABLE_SP_REDUNDANT_THREAD_GATING_MASK 0x20000000L
-#define SQ_CONFIG__DISABLE_FLAT_SOFT_CLAUSE_MASK 0x40000000L
-#define SQ_CONFIG__DISABLE_MIMG_SOFT_CLAUSE_MASK 0x80000000L
-//SQC_CONFIG
-#define SQC_CONFIG__INST_CACHE_SIZE__SHIFT 0x0
-#define SQC_CONFIG__DATA_CACHE_SIZE__SHIFT 0x2
-#define SQC_CONFIG__MISS_FIFO_DEPTH__SHIFT 0x4
-#define SQC_CONFIG__HIT_FIFO_DEPTH__SHIFT 0x6
-#define SQC_CONFIG__FORCE_ALWAYS_MISS__SHIFT 0x7
-#define SQC_CONFIG__FORCE_IN_ORDER__SHIFT 0x8
-#define SQC_CONFIG__IDENTITY_HASH_BANK__SHIFT 0x9
-#define SQC_CONFIG__IDENTITY_HASH_SET__SHIFT 0xa
-#define SQC_CONFIG__PER_VMID_INV_DISABLE__SHIFT 0xb
-#define SQC_CONFIG__EVICT_LRU__SHIFT 0xc
-#define SQC_CONFIG__FORCE_2_BANK__SHIFT 0xe
-#define SQC_CONFIG__FORCE_1_BANK__SHIFT 0xf
-#define SQC_CONFIG__LS_DISABLE_CLOCKS__SHIFT 0x10
-#define SQC_CONFIG__INST_PRF_COUNT__SHIFT 0x18
-#define SQC_CONFIG__INST_PRF_FILTER_DIS__SHIFT 0x1a
-#define SQC_CONFIG__INST_CACHE_SIZE_MASK 0x00000003L
-#define SQC_CONFIG__DATA_CACHE_SIZE_MASK 0x0000000CL
-#define SQC_CONFIG__MISS_FIFO_DEPTH_MASK 0x00000030L
-#define SQC_CONFIG__HIT_FIFO_DEPTH_MASK 0x00000040L
-#define SQC_CONFIG__FORCE_ALWAYS_MISS_MASK 0x00000080L
-#define SQC_CONFIG__FORCE_IN_ORDER_MASK 0x00000100L
-#define SQC_CONFIG__IDENTITY_HASH_BANK_MASK 0x00000200L
-#define SQC_CONFIG__IDENTITY_HASH_SET_MASK 0x00000400L
-#define SQC_CONFIG__PER_VMID_INV_DISABLE_MASK 0x00000800L
-#define SQC_CONFIG__EVICT_LRU_MASK 0x00003000L
-#define SQC_CONFIG__FORCE_2_BANK_MASK 0x00004000L
-#define SQC_CONFIG__FORCE_1_BANK_MASK 0x00008000L
-#define SQC_CONFIG__LS_DISABLE_CLOCKS_MASK 0x00FF0000L
-#define SQC_CONFIG__INST_PRF_COUNT_MASK 0x03000000L
-#define SQC_CONFIG__INST_PRF_FILTER_DIS_MASK 0x04000000L
-//LDS_CONFIG
-#define LDS_CONFIG__ADDR_OUT_OF_RANGE_REPORTING__SHIFT 0x0
-#define LDS_CONFIG__ADDR_OUT_OF_RANGE_REPORTING_MASK 0x00000001L
-//SQ_RANDOM_WAVE_PRI
-#define SQ_RANDOM_WAVE_PRI__RET__SHIFT 0x0
-#define SQ_RANDOM_WAVE_PRI__RUI__SHIFT 0x7
-#define SQ_RANDOM_WAVE_PRI__RNG__SHIFT 0xa
-#define SQ_RANDOM_WAVE_PRI__RET_MASK 0x0000007FL
-#define SQ_RANDOM_WAVE_PRI__RUI_MASK 0x00000380L
-#define SQ_RANDOM_WAVE_PRI__RNG_MASK 0x007FFC00L
-//SQ_REG_CREDITS
-#define SQ_REG_CREDITS__SRBM_CREDITS__SHIFT 0x0
-#define SQ_REG_CREDITS__CMD_CREDITS__SHIFT 0x8
-#define SQ_REG_CREDITS__REG_BUSY__SHIFT 0x1c
-#define SQ_REG_CREDITS__SRBM_OVERFLOW__SHIFT 0x1d
-#define SQ_REG_CREDITS__IMMED_OVERFLOW__SHIFT 0x1e
-#define SQ_REG_CREDITS__CMD_OVERFLOW__SHIFT 0x1f
-#define SQ_REG_CREDITS__SRBM_CREDITS_MASK 0x0000003FL
-#define SQ_REG_CREDITS__CMD_CREDITS_MASK 0x00000F00L
-#define SQ_REG_CREDITS__REG_BUSY_MASK 0x10000000L
-#define SQ_REG_CREDITS__SRBM_OVERFLOW_MASK 0x20000000L
-#define SQ_REG_CREDITS__IMMED_OVERFLOW_MASK 0x40000000L
-#define SQ_REG_CREDITS__CMD_OVERFLOW_MASK 0x80000000L
-//SQ_FIFO_SIZES
-#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE__SHIFT 0x0
-#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE__SHIFT 0x8
-#define SQ_FIFO_SIZES__EXPORT_BUF_SIZE__SHIFT 0x10
-#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE__SHIFT 0x12
-#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE_MASK 0x0000000FL
-#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE_MASK 0x00000F00L
-#define SQ_FIFO_SIZES__EXPORT_BUF_SIZE_MASK 0x00030000L
-#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE_MASK 0x000C0000L
-//SQ_DSM_CNTL
-#define SQ_DSM_CNTL__WAVEFRONT_STALL_0__SHIFT 0x0
-#define SQ_DSM_CNTL__WAVEFRONT_STALL_1__SHIFT 0x1
-#define SQ_DSM_CNTL__SPI_BACKPRESSURE_0__SHIFT 0x2
-#define SQ_DSM_CNTL__SPI_BACKPRESSURE_1__SHIFT 0x3
-#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0__SHIFT 0x8
-#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1__SHIFT 0x9
-#define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE__SHIFT 0xa
-#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0__SHIFT 0x10
-#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1__SHIFT 0x11
-#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01__SHIFT 0x12
-#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2__SHIFT 0x13
-#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3__SHIFT 0x14
-#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23__SHIFT 0x15
-#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0__SHIFT 0x18
-#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1__SHIFT 0x19
-#define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE__SHIFT 0x1a
-#define SQ_DSM_CNTL__WAVEFRONT_STALL_0_MASK 0x00000001L
-#define SQ_DSM_CNTL__WAVEFRONT_STALL_1_MASK 0x00000002L
-#define SQ_DSM_CNTL__SPI_BACKPRESSURE_0_MASK 0x00000004L
-#define SQ_DSM_CNTL__SPI_BACKPRESSURE_1_MASK 0x00000008L
-#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0_MASK 0x00000100L
-#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1_MASK 0x00000200L
-#define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE_MASK 0x00000400L
-#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0_MASK 0x00010000L
-#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1_MASK 0x00020000L
-#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01_MASK 0x00040000L
-#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2_MASK 0x00080000L
-#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3_MASK 0x00100000L
-#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23_MASK 0x00200000L
-#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0_MASK 0x01000000L
-#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1_MASK 0x02000000L
-#define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE_MASK 0x04000000L
-//SQ_DSM_CNTL2
-#define SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT__SHIFT 0x0
-#define SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY__SHIFT 0x2
-#define SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT__SHIFT 0x3
-#define SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY__SHIFT 0x5
-#define SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT__SHIFT 0x6
-#define SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY__SHIFT 0x8
-#define SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT__SHIFT 0x9
-#define SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY__SHIFT 0xb
-#define SQ_DSM_CNTL2__LDS_INJECT_DELAY__SHIFT 0xe
-#define SQ_DSM_CNTL2__SP_INJECT_DELAY__SHIFT 0x14
-#define SQ_DSM_CNTL2__SQ_INJECT_DELAY__SHIFT 0x1a
-#define SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT_MASK 0x00000003L
-#define SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY_MASK 0x00000004L
-#define SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT_MASK 0x00000018L
-#define SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY_MASK 0x00000020L
-#define SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT_MASK 0x000000C0L
-#define SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY_MASK 0x00000100L
-#define SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT_MASK 0x00000600L
-#define SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY_MASK 0x00000800L
-#define SQ_DSM_CNTL2__LDS_INJECT_DELAY_MASK 0x000FC000L
-#define SQ_DSM_CNTL2__SP_INJECT_DELAY_MASK 0x03F00000L
-#define SQ_DSM_CNTL2__SQ_INJECT_DELAY_MASK 0xFC000000L
-//SQ_RUNTIME_CONFIG
-#define SQ_RUNTIME_CONFIG__ENABLE_TEX_ARB_OLDEST__SHIFT 0x0
-#define SQ_RUNTIME_CONFIG__ENABLE_TEX_ARB_OLDEST_MASK 0x00000001L
-//SH_MEM_BASES
-#define SH_MEM_BASES__PRIVATE_BASE__SHIFT 0x0
-#define SH_MEM_BASES__SHARED_BASE__SHIFT 0x10
-#define SH_MEM_BASES__PRIVATE_BASE_MASK 0x0000FFFFL
-#define SH_MEM_BASES__SHARED_BASE_MASK 0xFFFF0000L
-//SH_MEM_CONFIG
-#define SH_MEM_CONFIG__ADDRESS_MODE__SHIFT 0x0
-#define SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT 0x3
-#define SH_MEM_CONFIG__RETRY_DISABLE__SHIFT 0xc
-#define SH_MEM_CONFIG__PRIVATE_NV__SHIFT 0xd
-#define SH_MEM_CONFIG__ADDRESS_MODE_MASK 0x00000001L
-#define SH_MEM_CONFIG__ALIGNMENT_MODE_MASK 0x00000018L
-#define SH_MEM_CONFIG__RETRY_DISABLE_MASK 0x00001000L
-#define SH_MEM_CONFIG__PRIVATE_NV_MASK 0x00002000L
-//CC_GC_SHADER_RATE_CONFIG
-#define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x1
-#define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3
-#define CC_GC_SHADER_RATE_CONFIG__HALF_LDS__SHIFT 0x4
-#define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x00000006L
-#define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK 0x00000008L
-#define CC_GC_SHADER_RATE_CONFIG__HALF_LDS_MASK 0x00000010L
-//GC_USER_SHADER_RATE_CONFIG
-#define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x1
-#define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3
-#define GC_USER_SHADER_RATE_CONFIG__HALF_LDS__SHIFT 0x4
-#define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x00000006L
-#define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK 0x00000008L
-#define GC_USER_SHADER_RATE_CONFIG__HALF_LDS_MASK 0x00000010L
-//SQ_INTERRUPT_AUTO_MASK
-#define SQ_INTERRUPT_AUTO_MASK__MASK__SHIFT 0x0
-#define SQ_INTERRUPT_AUTO_MASK__MASK_MASK 0x00FFFFFFL
-//SQ_INTERRUPT_MSG_CTRL
-#define SQ_INTERRUPT_MSG_CTRL__STALL__SHIFT 0x0
-#define SQ_INTERRUPT_MSG_CTRL__STALL_MASK 0x00000001L
-//SQ_UTCL1_CNTL1
-#define SQ_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0
-#define SQ_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1
-#define SQ_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2
-#define SQ_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3
-#define SQ_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5
-#define SQ_UTCL1_CNTL1__CLIENTID__SHIFT 0x7
-#define SQ_UTCL1_CNTL1__USERVM_DIS__SHIFT 0x10
-#define SQ_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11
-#define SQ_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12
-#define SQ_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT 0x13
-#define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT 0x17
-#define SQ_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT 0x18
-#define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL__SHIFT 0x19
-#define SQ_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a
-#define SQ_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b
-#define SQ_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
-#define SQ_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
-#define SQ_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L
-#define SQ_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L
-#define SQ_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L
-#define SQ_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L
-#define SQ_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L
-#define SQ_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L
-#define SQ_UTCL1_CNTL1__USERVM_DIS_MASK 0x00010000L
-#define SQ_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L
-#define SQ_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L
-#define SQ_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK 0x00780000L
-#define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK 0x00800000L
-#define SQ_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK 0x01000000L
-#define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_MASK 0x02000000L
-#define SQ_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L
-#define SQ_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L
-#define SQ_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L
-#define SQ_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L
-//SQ_UTCL1_CNTL2
-#define SQ_UTCL1_CNTL2__SPARE__SHIFT 0x0
-#define SQ_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x8
-#define SQ_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9
-#define SQ_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa
-#define SQ_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb
-#define SQ_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc
-#define SQ_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd
-#define SQ_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe
-#define SQ_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf
-#define SQ_UTCL1_CNTL2__RETRY_TIMER__SHIFT 0x10
-#define SQ_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a
-#define SQ_UTCL1_CNTL2__PREFETCH_PAGE__SHIFT 0x1c
-#define SQ_UTCL1_CNTL2__SPARE_MASK 0x000000FFL
-#define SQ_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L
-#define SQ_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L
-#define SQ_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L
-#define SQ_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L
-#define SQ_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L
-#define SQ_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L
-#define SQ_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L
-#define SQ_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L
-#define SQ_UTCL1_CNTL2__RETRY_TIMER_MASK 0x007F0000L
-#define SQ_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L
-#define SQ_UTCL1_CNTL2__PREFETCH_PAGE_MASK 0xF0000000L
-//SQ_UTCL1_STATUS
-#define SQ_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
-#define SQ_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
-#define SQ_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
-#define SQ_UTCL1_STATUS__RESERVED__SHIFT 0x3
-#define SQ_UTCL1_STATUS__UNUSED__SHIFT 0x10
-#define SQ_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
-#define SQ_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
-#define SQ_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
-#define SQ_UTCL1_STATUS__RESERVED_MASK 0x0000FFF8L
-#define SQ_UTCL1_STATUS__UNUSED_MASK 0xFFFF0000L
-//SQ_SHADER_TBA_LO
-#define SQ_SHADER_TBA_LO__ADDR_LO__SHIFT 0x0
-#define SQ_SHADER_TBA_LO__ADDR_LO_MASK 0xFFFFFFFFL
-//SQ_SHADER_TBA_HI
-#define SQ_SHADER_TBA_HI__ADDR_HI__SHIFT 0x0
-#define SQ_SHADER_TBA_HI__ADDR_HI_MASK 0x000000FFL
-//SQ_SHADER_TMA_LO
-#define SQ_SHADER_TMA_LO__ADDR_LO__SHIFT 0x0
-#define SQ_SHADER_TMA_LO__ADDR_LO_MASK 0xFFFFFFFFL
-//SQ_SHADER_TMA_HI
-#define SQ_SHADER_TMA_HI__ADDR_HI__SHIFT 0x0
-#define SQ_SHADER_TMA_HI__ADDR_HI_MASK 0x000000FFL
-//SQC_DSM_CNTL
-#define SQC_DSM_CNTL__INST_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x0
-#define SQC_DSM_CNTL__INST_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x2
-#define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT 0x3
-#define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT 0x5
-#define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x6
-#define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8
-#define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT 0x9
-#define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT 0xb
-#define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0xc
-#define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0xe
-#define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT 0xf
-#define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT 0x11
-#define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x12
-#define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x14
-#define SQC_DSM_CNTL__INST_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x00000003L
-#define SQC_DSM_CNTL__INST_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00000004L
-#define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK 0x00000018L
-#define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK 0x00000020L
-#define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L
-#define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L
-#define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK 0x00000600L
-#define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK 0x00000800L
-#define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x00003000L
-#define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00004000L
-#define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK 0x00018000L
-#define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK 0x00020000L
-#define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x000C0000L
-#define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00100000L
-//SQC_DSM_CNTLA
-#define SQC_DSM_CNTLA__INST_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0x0
-#define SQC_DSM_CNTLA__INST_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x2
-#define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x3
-#define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x5
-#define SQC_DSM_CNTLA__INST_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x6
-#define SQC_DSM_CNTLA__INST_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8
-#define SQC_DSM_CNTLA__INST_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x9
-#define SQC_DSM_CNTLA__INST_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xb
-#define SQC_DSM_CNTLA__DATA_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0xc
-#define SQC_DSM_CNTLA__DATA_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xe
-#define SQC_DSM_CNTLA__DATA_HIT_FIFO_DSM_IRRITATOR_DATA__SHIFT 0xf
-#define SQC_DSM_CNTLA__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x11
-#define SQC_DSM_CNTLA__DATA_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x12
-#define SQC_DSM_CNTLA__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x14
-#define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA__SHIFT 0x15
-#define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x17
-#define SQC_DSM_CNTLA__DATA_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x18
-#define SQC_DSM_CNTLA__DATA_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x1a
-#define SQC_DSM_CNTLA__INST_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00000003L
-#define SQC_DSM_CNTLA__INST_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
-#define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x00000018L
-#define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000020L
-#define SQC_DSM_CNTLA__INST_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L
-#define SQC_DSM_CNTLA__INST_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L
-#define SQC_DSM_CNTLA__INST_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x00000600L
-#define SQC_DSM_CNTLA__INST_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000800L
-#define SQC_DSM_CNTLA__DATA_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00003000L
-#define SQC_DSM_CNTLA__DATA_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00004000L
-#define SQC_DSM_CNTLA__DATA_HIT_FIFO_DSM_IRRITATOR_DATA_MASK 0x00018000L
-#define SQC_DSM_CNTLA__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00020000L
-#define SQC_DSM_CNTLA__DATA_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000C0000L
-#define SQC_DSM_CNTLA__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00100000L
-#define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA_MASK 0x00600000L
-#define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE_MASK 0x00800000L
-#define SQC_DSM_CNTLA__DATA_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x03000000L
-#define SQC_DSM_CNTLA__DATA_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x04000000L
-//SQC_DSM_CNTLB
-#define SQC_DSM_CNTLB__INST_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0x0
-#define SQC_DSM_CNTLB__INST_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x2
-#define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x3
-#define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x5
-#define SQC_DSM_CNTLB__INST_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x6
-#define SQC_DSM_CNTLB__INST_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8
-#define SQC_DSM_CNTLB__INST_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x9
-#define SQC_DSM_CNTLB__INST_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xb
-#define SQC_DSM_CNTLB__DATA_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0xc
-#define SQC_DSM_CNTLB__DATA_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xe
-#define SQC_DSM_CNTLB__DATA_HIT_FIFO_DSM_IRRITATOR_DATA__SHIFT 0xf
-#define SQC_DSM_CNTLB__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x11
-#define SQC_DSM_CNTLB__DATA_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x12
-#define SQC_DSM_CNTLB__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x14
-#define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA__SHIFT 0x15
-#define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x17
-#define SQC_DSM_CNTLB__DATA_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x18
-#define SQC_DSM_CNTLB__DATA_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x1a
-#define SQC_DSM_CNTLB__INST_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00000003L
-#define SQC_DSM_CNTLB__INST_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
-#define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x00000018L
-#define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000020L
-#define SQC_DSM_CNTLB__INST_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L
-#define SQC_DSM_CNTLB__INST_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L
-#define SQC_DSM_CNTLB__INST_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x00000600L
-#define SQC_DSM_CNTLB__INST_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000800L
-#define SQC_DSM_CNTLB__DATA_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00003000L
-#define SQC_DSM_CNTLB__DATA_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00004000L
-#define SQC_DSM_CNTLB__DATA_HIT_FIFO_DSM_IRRITATOR_DATA_MASK 0x00018000L
-#define SQC_DSM_CNTLB__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00020000L
-#define SQC_DSM_CNTLB__DATA_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000C0000L
-#define SQC_DSM_CNTLB__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00100000L
-#define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA_MASK 0x00600000L
-#define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE_MASK 0x00800000L
-#define SQC_DSM_CNTLB__DATA_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x03000000L
-#define SQC_DSM_CNTLB__DATA_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x04000000L
-//SQC_DSM_CNTL2
-#define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x0
-#define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0x2
-#define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT 0x3
-#define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT 0x5
-#define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x6
-#define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0x8
-#define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT 0x9
-#define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT 0xb
-#define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0xc
-#define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0xe
-#define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT 0xf
-#define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT 0x11
-#define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x12
-#define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0x14
-#define SQC_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a
-#define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x00000003L
-#define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00000004L
-#define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK 0x00000018L
-#define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK 0x00000020L
-#define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L
-#define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00000100L
-#define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK 0x00000600L
-#define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK 0x00000800L
-#define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x00003000L
-#define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00004000L
-#define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK 0x00018000L
-#define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK 0x00020000L
-#define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x000C0000L
-#define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00100000L
-#define SQC_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L
-//SQC_DSM_CNTL2A
-#define SQC_DSM_CNTL2A__INST_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0x0
-#define SQC_DSM_CNTL2A__INST_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0x2
-#define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x3
-#define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x5
-#define SQC_DSM_CNTL2A__INST_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x6
-#define SQC_DSM_CNTL2A__INST_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x8
-#define SQC_DSM_CNTL2A__INST_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x9
-#define SQC_DSM_CNTL2A__INST_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0xb
-#define SQC_DSM_CNTL2A__DATA_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0xc
-#define SQC_DSM_CNTL2A__DATA_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0xe
-#define SQC_DSM_CNTL2A__DATA_HIT_FIFO_ENABLE_ERROR_INJECT__SHIFT 0xf
-#define SQC_DSM_CNTL2A__DATA_HIT_FIFO_SELECT_INJECT_DELAY__SHIFT 0x11
-#define SQC_DSM_CNTL2A__DATA_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x12
-#define SQC_DSM_CNTL2A__DATA_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x14
-#define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT__SHIFT 0x15
-#define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY__SHIFT 0x17
-#define SQC_DSM_CNTL2A__DATA_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x18
-#define SQC_DSM_CNTL2A__DATA_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0x1a
-#define SQC_DSM_CNTL2A__INST_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00000003L
-#define SQC_DSM_CNTL2A__INST_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00000004L
-#define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x00000018L
-#define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000020L
-#define SQC_DSM_CNTL2A__INST_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L
-#define SQC_DSM_CNTL2A__INST_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000100L
-#define SQC_DSM_CNTL2A__INST_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L
-#define SQC_DSM_CNTL2A__INST_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L
-#define SQC_DSM_CNTL2A__DATA_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00003000L
-#define SQC_DSM_CNTL2A__DATA_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00004000L
-#define SQC_DSM_CNTL2A__DATA_HIT_FIFO_ENABLE_ERROR_INJECT_MASK 0x00018000L
-#define SQC_DSM_CNTL2A__DATA_HIT_FIFO_SELECT_INJECT_DELAY_MASK 0x00020000L
-#define SQC_DSM_CNTL2A__DATA_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000C0000L
-#define SQC_DSM_CNTL2A__DATA_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00100000L
-#define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT_MASK 0x00600000L
-#define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY_MASK 0x00800000L
-#define SQC_DSM_CNTL2A__DATA_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x03000000L
-#define SQC_DSM_CNTL2A__DATA_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x04000000L
-//SQC_DSM_CNTL2B
-#define SQC_DSM_CNTL2B__INST_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0x0
-#define SQC_DSM_CNTL2B__INST_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0x2
-#define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x3
-#define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x5
-#define SQC_DSM_CNTL2B__INST_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x6
-#define SQC_DSM_CNTL2B__INST_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x8
-#define SQC_DSM_CNTL2B__INST_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x9
-#define SQC_DSM_CNTL2B__INST_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0xb
-#define SQC_DSM_CNTL2B__DATA_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0xc
-#define SQC_DSM_CNTL2B__DATA_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0xe
-#define SQC_DSM_CNTL2B__DATA_HIT_FIFO_ENABLE_ERROR_INJECT__SHIFT 0xf
-#define SQC_DSM_CNTL2B__DATA_HIT_FIFO_SELECT_INJECT_DELAY__SHIFT 0x11
-#define SQC_DSM_CNTL2B__DATA_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x12
-#define SQC_DSM_CNTL2B__DATA_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x14
-#define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT__SHIFT 0x15
-#define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY__SHIFT 0x17
-#define SQC_DSM_CNTL2B__DATA_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x18
-#define SQC_DSM_CNTL2B__DATA_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0x1a
-#define SQC_DSM_CNTL2B__INST_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00000003L
-#define SQC_DSM_CNTL2B__INST_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00000004L
-#define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x00000018L
-#define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000020L
-#define SQC_DSM_CNTL2B__INST_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L
-#define SQC_DSM_CNTL2B__INST_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000100L
-#define SQC_DSM_CNTL2B__INST_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L
-#define SQC_DSM_CNTL2B__INST_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L
-#define SQC_DSM_CNTL2B__DATA_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00003000L
-#define SQC_DSM_CNTL2B__DATA_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00004000L
-#define SQC_DSM_CNTL2B__DATA_HIT_FIFO_ENABLE_ERROR_INJECT_MASK 0x00018000L
-#define SQC_DSM_CNTL2B__DATA_HIT_FIFO_SELECT_INJECT_DELAY_MASK 0x00020000L
-#define SQC_DSM_CNTL2B__DATA_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000C0000L
-#define SQC_DSM_CNTL2B__DATA_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00100000L
-#define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT_MASK 0x00600000L
-#define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY_MASK 0x00800000L
-#define SQC_DSM_CNTL2B__DATA_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x03000000L
-#define SQC_DSM_CNTL2B__DATA_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x04000000L
-//SQC_EDC_FUE_CNTL
-#define SQC_EDC_FUE_CNTL__BLOCK_FUE_FLAGS__SHIFT 0x0
-#define SQC_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES__SHIFT 0x10
-#define SQC_EDC_FUE_CNTL__BLOCK_FUE_FLAGS_MASK 0x0000FFFFL
-#define SQC_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES_MASK 0xFFFF0000L
-//SQC_EDC_CNT2
-#define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_SEC_COUNT__SHIFT 0x0
-#define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_DED_COUNT__SHIFT 0x2
-#define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_SEC_COUNT__SHIFT 0x4
-#define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_DED_COUNT__SHIFT 0x6
-#define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_SEC_COUNT__SHIFT 0x8
-#define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_DED_COUNT__SHIFT 0xa
-#define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_SEC_COUNT__SHIFT 0xc
-#define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_DED_COUNT__SHIFT 0xe
-#define SQC_EDC_CNT2__INST_BANKA_UTCL1_MISS_FIFO_SED_COUNT__SHIFT 0x10
-#define SQC_EDC_CNT2__INST_BANKA_MISS_FIFO_SED_COUNT__SHIFT 0x12
-#define SQC_EDC_CNT2__DATA_BANKA_HIT_FIFO_SED_COUNT__SHIFT 0x14
-#define SQC_EDC_CNT2__DATA_BANKA_MISS_FIFO_SED_COUNT__SHIFT 0x16
-#define SQC_EDC_CNT2__DATA_BANKA_DIRTY_BIT_RAM_SED_COUNT__SHIFT 0x18
-#define SQC_EDC_CNT2__INST_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x1a
-#define SQC_EDC_CNT2__INST_UTCL1_LFIFO_DED_COUNT__SHIFT 0x1c
-#define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_SEC_COUNT_MASK 0x00000003L
-#define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_DED_COUNT_MASK 0x0000000CL
-#define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_SEC_COUNT_MASK 0x00000030L
-#define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_DED_COUNT_MASK 0x000000C0L
-#define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_SEC_COUNT_MASK 0x00000300L
-#define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_DED_COUNT_MASK 0x00000C00L
-#define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_SEC_COUNT_MASK 0x00003000L
-#define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_DED_COUNT_MASK 0x0000C000L
-#define SQC_EDC_CNT2__INST_BANKA_UTCL1_MISS_FIFO_SED_COUNT_MASK 0x00030000L
-#define SQC_EDC_CNT2__INST_BANKA_MISS_FIFO_SED_COUNT_MASK 0x000C0000L
-#define SQC_EDC_CNT2__DATA_BANKA_HIT_FIFO_SED_COUNT_MASK 0x00300000L
-#define SQC_EDC_CNT2__DATA_BANKA_MISS_FIFO_SED_COUNT_MASK 0x00C00000L
-#define SQC_EDC_CNT2__DATA_BANKA_DIRTY_BIT_RAM_SED_COUNT_MASK 0x03000000L
-#define SQC_EDC_CNT2__INST_UTCL1_LFIFO_SEC_COUNT_MASK 0x0C000000L
-#define SQC_EDC_CNT2__INST_UTCL1_LFIFO_DED_COUNT_MASK 0x30000000L
-//SQC_EDC_CNT3
-#define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_SEC_COUNT__SHIFT 0x0
-#define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_DED_COUNT__SHIFT 0x2
-#define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_SEC_COUNT__SHIFT 0x4
-#define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_DED_COUNT__SHIFT 0x6
-#define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_SEC_COUNT__SHIFT 0x8
-#define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_DED_COUNT__SHIFT 0xa
-#define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_SEC_COUNT__SHIFT 0xc
-#define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_DED_COUNT__SHIFT 0xe
-#define SQC_EDC_CNT3__INST_BANKB_UTCL1_MISS_FIFO_SED_COUNT__SHIFT 0x10
-#define SQC_EDC_CNT3__INST_BANKB_MISS_FIFO_SED_COUNT__SHIFT 0x12
-#define SQC_EDC_CNT3__DATA_BANKB_HIT_FIFO_SED_COUNT__SHIFT 0x14
-#define SQC_EDC_CNT3__DATA_BANKB_MISS_FIFO_SED_COUNT__SHIFT 0x16
-#define SQC_EDC_CNT3__DATA_BANKB_DIRTY_BIT_RAM_SED_COUNT__SHIFT 0x18
-#define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_SEC_COUNT_MASK 0x00000003L
-#define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_DED_COUNT_MASK 0x0000000CL
-#define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_SEC_COUNT_MASK 0x00000030L
-#define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_DED_COUNT_MASK 0x000000C0L
-#define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_SEC_COUNT_MASK 0x00000300L
-#define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_DED_COUNT_MASK 0x00000C00L
-#define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_SEC_COUNT_MASK 0x00003000L
-#define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_DED_COUNT_MASK 0x0000C000L
-#define SQC_EDC_CNT3__INST_BANKB_UTCL1_MISS_FIFO_SED_COUNT_MASK 0x00030000L
-#define SQC_EDC_CNT3__INST_BANKB_MISS_FIFO_SED_COUNT_MASK 0x000C0000L
-#define SQC_EDC_CNT3__DATA_BANKB_HIT_FIFO_SED_COUNT_MASK 0x00300000L
-#define SQC_EDC_CNT3__DATA_BANKB_MISS_FIFO_SED_COUNT_MASK 0x00C00000L
-#define SQC_EDC_CNT3__DATA_BANKB_DIRTY_BIT_RAM_SED_COUNT_MASK 0x03000000L
-//SQ_REG_TIMESTAMP
-#define SQ_REG_TIMESTAMP__TIMESTAMP__SHIFT 0x0
-#define SQ_REG_TIMESTAMP__TIMESTAMP_MASK 0x000000FFL
-//SQ_CMD_TIMESTAMP
-#define SQ_CMD_TIMESTAMP__TIMESTAMP__SHIFT 0x0
-#define SQ_CMD_TIMESTAMP__TIMESTAMP_MASK 0x000000FFL
-//SQ_IND_INDEX
-#define SQ_IND_INDEX__WAVE_ID__SHIFT 0x0
-#define SQ_IND_INDEX__SIMD_ID__SHIFT 0x4
-#define SQ_IND_INDEX__THREAD_ID__SHIFT 0x6
-#define SQ_IND_INDEX__AUTO_INCR__SHIFT 0xc
-#define SQ_IND_INDEX__FORCE_READ__SHIFT 0xd
-#define SQ_IND_INDEX__READ_TIMEOUT__SHIFT 0xe
-#define SQ_IND_INDEX__UNINDEXED__SHIFT 0xf
-#define SQ_IND_INDEX__INDEX__SHIFT 0x10
-#define SQ_IND_INDEX__WAVE_ID_MASK 0x0000000FL
-#define SQ_IND_INDEX__SIMD_ID_MASK 0x00000030L
-#define SQ_IND_INDEX__THREAD_ID_MASK 0x00000FC0L
-#define SQ_IND_INDEX__AUTO_INCR_MASK 0x00001000L
-#define SQ_IND_INDEX__FORCE_READ_MASK 0x00002000L
-#define SQ_IND_INDEX__READ_TIMEOUT_MASK 0x00004000L
-#define SQ_IND_INDEX__UNINDEXED_MASK 0x00008000L
-#define SQ_IND_INDEX__INDEX_MASK 0xFFFF0000L
-//SQ_IND_DATA
-#define SQ_IND_DATA__DATA__SHIFT 0x0
-#define SQ_IND_DATA__DATA_MASK 0xFFFFFFFFL
-//SQ_CMD
-#define SQ_CMD__CMD__SHIFT 0x0
-#define SQ_CMD__MODE__SHIFT 0x4
-#define SQ_CMD__CHECK_VMID__SHIFT 0x7
-#define SQ_CMD__DATA__SHIFT 0x8
-#define SQ_CMD__WAVE_ID__SHIFT 0x10
-#define SQ_CMD__SIMD_ID__SHIFT 0x14
-#define SQ_CMD__QUEUE_ID__SHIFT 0x18
-#define SQ_CMD__VM_ID__SHIFT 0x1c
-#define SQ_CMD__CMD_MASK 0x00000007L
-#define SQ_CMD__MODE_MASK 0x00000070L
-#define SQ_CMD__CHECK_VMID_MASK 0x00000080L
-#define SQ_CMD__DATA_MASK 0x00000F00L
-#define SQ_CMD__WAVE_ID_MASK 0x000F0000L
-#define SQ_CMD__SIMD_ID_MASK 0x00300000L
-#define SQ_CMD__QUEUE_ID_MASK 0x07000000L
-#define SQ_CMD__VM_ID_MASK 0xF0000000L
-//SQ_TIME_HI
-#define SQ_TIME_HI__TIME__SHIFT 0x0
-#define SQ_TIME_HI__TIME_MASK 0xFFFFFFFFL
-//SQ_TIME_LO
-#define SQ_TIME_LO__TIME__SHIFT 0x0
-#define SQ_TIME_LO__TIME_MASK 0xFFFFFFFFL
-//SQ_DS_0
-#define SQ_DS_0__OFFSET0__SHIFT 0x0
-#define SQ_DS_0__OFFSET1__SHIFT 0x8
-#define SQ_DS_0__GDS__SHIFT 0x10
-#define SQ_DS_0__OP__SHIFT 0x11
-#define SQ_DS_0__ENCODING__SHIFT 0x1a
-#define SQ_DS_0__OFFSET0_MASK 0x000000FFL
-#define SQ_DS_0__OFFSET1_MASK 0x0000FF00L
-#define SQ_DS_0__GDS_MASK 0x00010000L
-#define SQ_DS_0__OP_MASK 0x01FE0000L
-#define SQ_DS_0__ENCODING_MASK 0xFC000000L
-//SQ_DS_1
-#define SQ_DS_1__ADDR__SHIFT 0x0
-#define SQ_DS_1__DATA0__SHIFT 0x8
-#define SQ_DS_1__DATA1__SHIFT 0x10
-#define SQ_DS_1__VDST__SHIFT 0x18
-#define SQ_DS_1__ADDR_MASK 0x000000FFL
-#define SQ_DS_1__DATA0_MASK 0x0000FF00L
-#define SQ_DS_1__DATA1_MASK 0x00FF0000L
-#define SQ_DS_1__VDST_MASK 0xFF000000L
-//SQ_EXP_0
-#define SQ_EXP_0__EN__SHIFT 0x0
-#define SQ_EXP_0__TGT__SHIFT 0x4
-#define SQ_EXP_0__COMPR__SHIFT 0xa
-#define SQ_EXP_0__DONE__SHIFT 0xb
-#define SQ_EXP_0__VM__SHIFT 0xc
-#define SQ_EXP_0__ENCODING__SHIFT 0x1a
-#define SQ_EXP_0__EN_MASK 0x0000000FL
-#define SQ_EXP_0__TGT_MASK 0x000003F0L
-#define SQ_EXP_0__COMPR_MASK 0x00000400L
-#define SQ_EXP_0__DONE_MASK 0x00000800L
-#define SQ_EXP_0__VM_MASK 0x00001000L
-#define SQ_EXP_0__ENCODING_MASK 0xFC000000L
-//SQ_EXP_1
-#define SQ_EXP_1__VSRC0__SHIFT 0x0
-#define SQ_EXP_1__VSRC1__SHIFT 0x8
-#define SQ_EXP_1__VSRC2__SHIFT 0x10
-#define SQ_EXP_1__VSRC3__SHIFT 0x18
-#define SQ_EXP_1__VSRC0_MASK 0x000000FFL
-#define SQ_EXP_1__VSRC1_MASK 0x0000FF00L
-#define SQ_EXP_1__VSRC2_MASK 0x00FF0000L
-#define SQ_EXP_1__VSRC3_MASK 0xFF000000L
-//SQ_FLAT_0
-#define SQ_FLAT_0__OFFSET__SHIFT 0x0
-#define SQ_FLAT_0__LDS__SHIFT 0xd
-#define SQ_FLAT_0__SEG__SHIFT 0xe
-#define SQ_FLAT_0__GLC__SHIFT 0x10
-#define SQ_FLAT_0__SLC__SHIFT 0x11
-#define SQ_FLAT_0__OP__SHIFT 0x12
-#define SQ_FLAT_0__ENCODING__SHIFT 0x1a
-#define SQ_FLAT_0__OFFSET_MASK 0x00000FFFL
-#define SQ_FLAT_0__LDS_MASK 0x00002000L
-#define SQ_FLAT_0__SEG_MASK 0x0000C000L
-#define SQ_FLAT_0__GLC_MASK 0x00010000L
-#define SQ_FLAT_0__SLC_MASK 0x00020000L
-#define SQ_FLAT_0__OP_MASK 0x01FC0000L
-#define SQ_FLAT_0__ENCODING_MASK 0xFC000000L
-//SQ_FLAT_1
-#define SQ_FLAT_1__ADDR__SHIFT 0x0
-#define SQ_FLAT_1__DATA__SHIFT 0x8
-#define SQ_FLAT_1__SADDR__SHIFT 0x10
-#define SQ_FLAT_1__NV__SHIFT 0x17
-#define SQ_FLAT_1__VDST__SHIFT 0x18
-#define SQ_FLAT_1__ADDR_MASK 0x000000FFL
-#define SQ_FLAT_1__DATA_MASK 0x0000FF00L
-#define SQ_FLAT_1__SADDR_MASK 0x007F0000L
-#define SQ_FLAT_1__NV_MASK 0x00800000L
-#define SQ_FLAT_1__VDST_MASK 0xFF000000L
-//SQ_GLBL_0
-#define SQ_GLBL_0__OFFSET__SHIFT 0x0
-#define SQ_GLBL_0__LDS__SHIFT 0xd
-#define SQ_GLBL_0__SEG__SHIFT 0xe
-#define SQ_GLBL_0__GLC__SHIFT 0x10
-#define SQ_GLBL_0__SLC__SHIFT 0x11
-#define SQ_GLBL_0__OP__SHIFT 0x12
-#define SQ_GLBL_0__ENCODING__SHIFT 0x1a
-#define SQ_GLBL_0__OFFSET_MASK 0x00001FFFL
-#define SQ_GLBL_0__LDS_MASK 0x00002000L
-#define SQ_GLBL_0__SEG_MASK 0x0000C000L
-#define SQ_GLBL_0__GLC_MASK 0x00010000L
-#define SQ_GLBL_0__SLC_MASK 0x00020000L
-#define SQ_GLBL_0__OP_MASK 0x01FC0000L
-#define SQ_GLBL_0__ENCODING_MASK 0xFC000000L
-//SQ_GLBL_1
-#define SQ_GLBL_1__ADDR__SHIFT 0x0
-#define SQ_GLBL_1__DATA__SHIFT 0x8
-#define SQ_GLBL_1__SADDR__SHIFT 0x10
-#define SQ_GLBL_1__NV__SHIFT 0x17
-#define SQ_GLBL_1__VDST__SHIFT 0x18
-#define SQ_GLBL_1__ADDR_MASK 0x000000FFL
-#define SQ_GLBL_1__DATA_MASK 0x0000FF00L
-#define SQ_GLBL_1__SADDR_MASK 0x007F0000L
-#define SQ_GLBL_1__NV_MASK 0x00800000L
-#define SQ_GLBL_1__VDST_MASK 0xFF000000L
-//SQ_INST
-#define SQ_INST__ENCODING__SHIFT 0x0
-#define SQ_INST__ENCODING_MASK 0xFFFFFFFFL
-//SQ_MIMG_0
-#define SQ_MIMG_0__OPM__SHIFT 0x0
-#define SQ_MIMG_0__DMASK__SHIFT 0x8
-#define SQ_MIMG_0__UNORM__SHIFT 0xc
-#define SQ_MIMG_0__GLC__SHIFT 0xd
-#define SQ_MIMG_0__DA__SHIFT 0xe
-#define SQ_MIMG_0__A16__SHIFT 0xf
-#define SQ_MIMG_0__TFE__SHIFT 0x10
-#define SQ_MIMG_0__LWE__SHIFT 0x11
-#define SQ_MIMG_0__OP__SHIFT 0x12
-#define SQ_MIMG_0__SLC__SHIFT 0x19
-#define SQ_MIMG_0__ENCODING__SHIFT 0x1a
-#define SQ_MIMG_0__OPM_MASK 0x00000001L
-#define SQ_MIMG_0__DMASK_MASK 0x00000F00L
-#define SQ_MIMG_0__UNORM_MASK 0x00001000L
-#define SQ_MIMG_0__GLC_MASK 0x00002000L
-#define SQ_MIMG_0__DA_MASK 0x00004000L
-#define SQ_MIMG_0__A16_MASK 0x00008000L
-#define SQ_MIMG_0__TFE_MASK 0x00010000L
-#define SQ_MIMG_0__LWE_MASK 0x00020000L
-#define SQ_MIMG_0__OP_MASK 0x01FC0000L
-#define SQ_MIMG_0__SLC_MASK 0x02000000L
-#define SQ_MIMG_0__ENCODING_MASK 0xFC000000L
-//SQ_MIMG_1
-#define SQ_MIMG_1__VADDR__SHIFT 0x0
-#define SQ_MIMG_1__VDATA__SHIFT 0x8
-#define SQ_MIMG_1__SRSRC__SHIFT 0x10
-#define SQ_MIMG_1__SSAMP__SHIFT 0x15
-#define SQ_MIMG_1__D16__SHIFT 0x1f
-#define SQ_MIMG_1__VADDR_MASK 0x000000FFL
-#define SQ_MIMG_1__VDATA_MASK 0x0000FF00L
-#define SQ_MIMG_1__SRSRC_MASK 0x001F0000L
-#define SQ_MIMG_1__SSAMP_MASK 0x03E00000L
-#define SQ_MIMG_1__D16_MASK 0x80000000L
-//SQ_MTBUF_0
-#define SQ_MTBUF_0__OFFSET__SHIFT 0x0
-#define SQ_MTBUF_0__OFFEN__SHIFT 0xc
-#define SQ_MTBUF_0__IDXEN__SHIFT 0xd
-#define SQ_MTBUF_0__GLC__SHIFT 0xe
-#define SQ_MTBUF_0__OP__SHIFT 0xf
-#define SQ_MTBUF_0__DFMT__SHIFT 0x13
-#define SQ_MTBUF_0__NFMT__SHIFT 0x17
-#define SQ_MTBUF_0__ENCODING__SHIFT 0x1a
-#define SQ_MTBUF_0__OFFSET_MASK 0x00000FFFL
-#define SQ_MTBUF_0__OFFEN_MASK 0x00001000L
-#define SQ_MTBUF_0__IDXEN_MASK 0x00002000L
-#define SQ_MTBUF_0__GLC_MASK 0x00004000L
-#define SQ_MTBUF_0__OP_MASK 0x00078000L
-#define SQ_MTBUF_0__DFMT_MASK 0x00780000L
-#define SQ_MTBUF_0__NFMT_MASK 0x03800000L
-#define SQ_MTBUF_0__ENCODING_MASK 0xFC000000L
-//SQ_MTBUF_1
-#define SQ_MTBUF_1__VADDR__SHIFT 0x0
-#define SQ_MTBUF_1__VDATA__SHIFT 0x8
-#define SQ_MTBUF_1__SRSRC__SHIFT 0x10
-#define SQ_MTBUF_1__SLC__SHIFT 0x16
-#define SQ_MTBUF_1__TFE__SHIFT 0x17
-#define SQ_MTBUF_1__SOFFSET__SHIFT 0x18
-#define SQ_MTBUF_1__VADDR_MASK 0x000000FFL
-#define SQ_MTBUF_1__VDATA_MASK 0x0000FF00L
-#define SQ_MTBUF_1__SRSRC_MASK 0x001F0000L
-#define SQ_MTBUF_1__SLC_MASK 0x00400000L
-#define SQ_MTBUF_1__TFE_MASK 0x00800000L
-#define SQ_MTBUF_1__SOFFSET_MASK 0xFF000000L
-//SQ_MUBUF_0
-#define SQ_MUBUF_0__OFFSET__SHIFT 0x0
-#define SQ_MUBUF_0__OFFEN__SHIFT 0xc
-#define SQ_MUBUF_0__IDXEN__SHIFT 0xd
-#define SQ_MUBUF_0__GLC__SHIFT 0xe
-#define SQ_MUBUF_0__LDS__SHIFT 0x10
-#define SQ_MUBUF_0__SLC__SHIFT 0x11
-#define SQ_MUBUF_0__OP__SHIFT 0x12
-#define SQ_MUBUF_0__ENCODING__SHIFT 0x1a
-#define SQ_MUBUF_0__OFFSET_MASK 0x00000FFFL
-#define SQ_MUBUF_0__OFFEN_MASK 0x00001000L
-#define SQ_MUBUF_0__IDXEN_MASK 0x00002000L
-#define SQ_MUBUF_0__GLC_MASK 0x00004000L
-#define SQ_MUBUF_0__LDS_MASK 0x00010000L
-#define SQ_MUBUF_0__SLC_MASK 0x00020000L
-#define SQ_MUBUF_0__OP_MASK 0x01FC0000L
-#define SQ_MUBUF_0__ENCODING_MASK 0xFC000000L
-//SQ_MUBUF_1
-#define SQ_MUBUF_1__VADDR__SHIFT 0x0
-#define SQ_MUBUF_1__VDATA__SHIFT 0x8
-#define SQ_MUBUF_1__SRSRC__SHIFT 0x10
-#define SQ_MUBUF_1__TFE__SHIFT 0x17
-#define SQ_MUBUF_1__SOFFSET__SHIFT 0x18
-#define SQ_MUBUF_1__VADDR_MASK 0x000000FFL
-#define SQ_MUBUF_1__VDATA_MASK 0x0000FF00L
-#define SQ_MUBUF_1__SRSRC_MASK 0x001F0000L
-#define SQ_MUBUF_1__TFE_MASK 0x00800000L
-#define SQ_MUBUF_1__SOFFSET_MASK 0xFF000000L
-//SQ_SCRATCH_0
-#define SQ_SCRATCH_0__OFFSET__SHIFT 0x0
-#define SQ_SCRATCH_0__LDS__SHIFT 0xd
-#define SQ_SCRATCH_0__SEG__SHIFT 0xe
-#define SQ_SCRATCH_0__GLC__SHIFT 0x10
-#define SQ_SCRATCH_0__SLC__SHIFT 0x11
-#define SQ_SCRATCH_0__OP__SHIFT 0x12
-#define SQ_SCRATCH_0__ENCODING__SHIFT 0x1a
-#define SQ_SCRATCH_0__OFFSET_MASK 0x00001FFFL
-#define SQ_SCRATCH_0__LDS_MASK 0x00002000L
-#define SQ_SCRATCH_0__SEG_MASK 0x0000C000L
-#define SQ_SCRATCH_0__GLC_MASK 0x00010000L
-#define SQ_SCRATCH_0__SLC_MASK 0x00020000L
-#define SQ_SCRATCH_0__OP_MASK 0x01FC0000L
-#define SQ_SCRATCH_0__ENCODING_MASK 0xFC000000L
-//SQ_SCRATCH_1
-#define SQ_SCRATCH_1__ADDR__SHIFT 0x0
-#define SQ_SCRATCH_1__DATA__SHIFT 0x8
-#define SQ_SCRATCH_1__SADDR__SHIFT 0x10
-#define SQ_SCRATCH_1__NV__SHIFT 0x17
-#define SQ_SCRATCH_1__VDST__SHIFT 0x18
-#define SQ_SCRATCH_1__ADDR_MASK 0x000000FFL
-#define SQ_SCRATCH_1__DATA_MASK 0x0000FF00L
-#define SQ_SCRATCH_1__SADDR_MASK 0x007F0000L
-#define SQ_SCRATCH_1__NV_MASK 0x00800000L
-#define SQ_SCRATCH_1__VDST_MASK 0xFF000000L
-//SQ_SMEM_0
-#define SQ_SMEM_0__SBASE__SHIFT 0x0
-#define SQ_SMEM_0__SDATA__SHIFT 0x6
-#define SQ_SMEM_0__SOFFSET_EN__SHIFT 0xe
-#define SQ_SMEM_0__NV__SHIFT 0xf
-#define SQ_SMEM_0__GLC__SHIFT 0x10
-#define SQ_SMEM_0__IMM__SHIFT 0x11
-#define SQ_SMEM_0__OP__SHIFT 0x12
-#define SQ_SMEM_0__ENCODING__SHIFT 0x1a
-#define SQ_SMEM_0__SBASE_MASK 0x0000003FL
-#define SQ_SMEM_0__SDATA_MASK 0x00001FC0L
-#define SQ_SMEM_0__SOFFSET_EN_MASK 0x00004000L
-#define SQ_SMEM_0__NV_MASK 0x00008000L
-#define SQ_SMEM_0__GLC_MASK 0x00010000L
-#define SQ_SMEM_0__IMM_MASK 0x00020000L
-#define SQ_SMEM_0__OP_MASK 0x03FC0000L
-#define SQ_SMEM_0__ENCODING_MASK 0xFC000000L
-//SQ_SMEM_1
-#define SQ_SMEM_1__OFFSET__SHIFT 0x0
-#define SQ_SMEM_1__SOFFSET__SHIFT 0x19
-#define SQ_SMEM_1__OFFSET_MASK 0x001FFFFFL
-#define SQ_SMEM_1__SOFFSET_MASK 0xFE000000L
-//SQ_SOP1
-#define SQ_SOP1__SSRC0__SHIFT 0x0
-#define SQ_SOP1__OP__SHIFT 0x8
-#define SQ_SOP1__SDST__SHIFT 0x10
-#define SQ_SOP1__ENCODING__SHIFT 0x17
-#define SQ_SOP1__SSRC0_MASK 0x000000FFL
-#define SQ_SOP1__OP_MASK 0x0000FF00L
-#define SQ_SOP1__SDST_MASK 0x007F0000L
-#define SQ_SOP1__ENCODING_MASK 0xFF800000L
-//SQ_SOP2
-#define SQ_SOP2__SSRC0__SHIFT 0x0
-#define SQ_SOP2__SSRC1__SHIFT 0x8
-#define SQ_SOP2__SDST__SHIFT 0x10
-#define SQ_SOP2__OP__SHIFT 0x17
-#define SQ_SOP2__ENCODING__SHIFT 0x1e
-#define SQ_SOP2__SSRC0_MASK 0x000000FFL
-#define SQ_SOP2__SSRC1_MASK 0x0000FF00L
-#define SQ_SOP2__SDST_MASK 0x007F0000L
-#define SQ_SOP2__OP_MASK 0x3F800000L
-#define SQ_SOP2__ENCODING_MASK 0xC0000000L
-//SQ_SOPC
-#define SQ_SOPC__SSRC0__SHIFT 0x0
-#define SQ_SOPC__SSRC1__SHIFT 0x8
-#define SQ_SOPC__OP__SHIFT 0x10
-#define SQ_SOPC__ENCODING__SHIFT 0x17
-#define SQ_SOPC__SSRC0_MASK 0x000000FFL
-#define SQ_SOPC__SSRC1_MASK 0x0000FF00L
-#define SQ_SOPC__OP_MASK 0x007F0000L
-#define SQ_SOPC__ENCODING_MASK 0xFF800000L
-//SQ_SOPK
-#define SQ_SOPK__SIMM16__SHIFT 0x0
-#define SQ_SOPK__SDST__SHIFT 0x10
-#define SQ_SOPK__OP__SHIFT 0x17
-#define SQ_SOPK__ENCODING__SHIFT 0x1c
-#define SQ_SOPK__SIMM16_MASK 0x0000FFFFL
-#define SQ_SOPK__SDST_MASK 0x007F0000L
-#define SQ_SOPK__OP_MASK 0x0F800000L
-#define SQ_SOPK__ENCODING_MASK 0xF0000000L
-//SQ_SOPP
-#define SQ_SOPP__SIMM16__SHIFT 0x0
-#define SQ_SOPP__OP__SHIFT 0x10
-#define SQ_SOPP__ENCODING__SHIFT 0x17
-#define SQ_SOPP__SIMM16_MASK 0x0000FFFFL
-#define SQ_SOPP__OP_MASK 0x007F0000L
-#define SQ_SOPP__ENCODING_MASK 0xFF800000L
-//SQ_VINTRP
-#define SQ_VINTRP__VSRC__SHIFT 0x0
-#define SQ_VINTRP__ATTRCHAN__SHIFT 0x8
-#define SQ_VINTRP__ATTR__SHIFT 0xa
-#define SQ_VINTRP__OP__SHIFT 0x10
-#define SQ_VINTRP__VDST__SHIFT 0x12
-#define SQ_VINTRP__ENCODING__SHIFT 0x1a
-#define SQ_VINTRP__VSRC_MASK 0x000000FFL
-#define SQ_VINTRP__ATTRCHAN_MASK 0x00000300L
-#define SQ_VINTRP__ATTR_MASK 0x0000FC00L
-#define SQ_VINTRP__OP_MASK 0x00030000L
-#define SQ_VINTRP__VDST_MASK 0x03FC0000L
-#define SQ_VINTRP__ENCODING_MASK 0xFC000000L
-//SQ_VOP1
-#define SQ_VOP1__SRC0__SHIFT 0x0
-#define SQ_VOP1__OP__SHIFT 0x9
-#define SQ_VOP1__VDST__SHIFT 0x11
-#define SQ_VOP1__ENCODING__SHIFT 0x19
-#define SQ_VOP1__SRC0_MASK 0x000001FFL
-#define SQ_VOP1__OP_MASK 0x0001FE00L
-#define SQ_VOP1__VDST_MASK 0x01FE0000L
-#define SQ_VOP1__ENCODING_MASK 0xFE000000L
-//SQ_VOP2
-#define SQ_VOP2__SRC0__SHIFT 0x0
-#define SQ_VOP2__VSRC1__SHIFT 0x9
-#define SQ_VOP2__VDST__SHIFT 0x11
-#define SQ_VOP2__OP__SHIFT 0x19
-#define SQ_VOP2__ENCODING__SHIFT 0x1f
-#define SQ_VOP2__SRC0_MASK 0x000001FFL
-#define SQ_VOP2__VSRC1_MASK 0x0001FE00L
-#define SQ_VOP2__VDST_MASK 0x01FE0000L
-#define SQ_VOP2__OP_MASK 0x7E000000L
-#define SQ_VOP2__ENCODING_MASK 0x80000000L
-//SQ_VOP3P_0
-#define SQ_VOP3P_0__VDST__SHIFT 0x0
-#define SQ_VOP3P_0__NEG_HI__SHIFT 0x8
-#define SQ_VOP3P_0__OP_SEL__SHIFT 0xb
-#define SQ_VOP3P_0__OP_SEL_HI_2__SHIFT 0xe
-#define SQ_VOP3P_0__CLAMP__SHIFT 0xf
-#define SQ_VOP3P_0__OP__SHIFT 0x10
-#define SQ_VOP3P_0__ENCODING__SHIFT 0x17
-#define SQ_VOP3P_0__VDST_MASK 0x000000FFL
-#define SQ_VOP3P_0__NEG_HI_MASK 0x00000700L
-#define SQ_VOP3P_0__OP_SEL_MASK 0x00003800L
-#define SQ_VOP3P_0__OP_SEL_HI_2_MASK 0x00004000L
-#define SQ_VOP3P_0__CLAMP_MASK 0x00008000L
-#define SQ_VOP3P_0__OP_MASK 0x007F0000L
-#define SQ_VOP3P_0__ENCODING_MASK 0xFF800000L
-//SQ_VOP3P_1
-#define SQ_VOP3P_1__SRC0__SHIFT 0x0
-#define SQ_VOP3P_1__SRC1__SHIFT 0x9
-#define SQ_VOP3P_1__SRC2__SHIFT 0x12
-#define SQ_VOP3P_1__OP_SEL_HI__SHIFT 0x1b
-#define SQ_VOP3P_1__NEG__SHIFT 0x1d
-#define SQ_VOP3P_1__SRC0_MASK 0x000001FFL
-#define SQ_VOP3P_1__SRC1_MASK 0x0003FE00L
-#define SQ_VOP3P_1__SRC2_MASK 0x07FC0000L
-#define SQ_VOP3P_1__OP_SEL_HI_MASK 0x18000000L
-#define SQ_VOP3P_1__NEG_MASK 0xE0000000L
-//SQ_VOP3_0
-#define SQ_VOP3_0__VDST__SHIFT 0x0
-#define SQ_VOP3_0__ABS__SHIFT 0x8
-#define SQ_VOP3_0__OP_SEL__SHIFT 0xb
-#define SQ_VOP3_0__CLAMP__SHIFT 0xf
-#define SQ_VOP3_0__OP__SHIFT 0x10
-#define SQ_VOP3_0__ENCODING__SHIFT 0x1a
-#define SQ_VOP3_0__VDST_MASK 0x000000FFL
-#define SQ_VOP3_0__ABS_MASK 0x00000700L
-#define SQ_VOP3_0__OP_SEL_MASK 0x00007800L
-#define SQ_VOP3_0__CLAMP_MASK 0x00008000L
-#define SQ_VOP3_0__OP_MASK 0x03FF0000L
-#define SQ_VOP3_0__ENCODING_MASK 0xFC000000L
-//SQ_VOP3_0_SDST_ENC
-#define SQ_VOP3_0_SDST_ENC__VDST__SHIFT 0x0
-#define SQ_VOP3_0_SDST_ENC__SDST__SHIFT 0x8
-#define SQ_VOP3_0_SDST_ENC__CLAMP__SHIFT 0xf
-#define SQ_VOP3_0_SDST_ENC__OP__SHIFT 0x10
-#define SQ_VOP3_0_SDST_ENC__ENCODING__SHIFT 0x1a
-#define SQ_VOP3_0_SDST_ENC__VDST_MASK 0x000000FFL
-#define SQ_VOP3_0_SDST_ENC__SDST_MASK 0x00007F00L
-#define SQ_VOP3_0_SDST_ENC__CLAMP_MASK 0x00008000L
-#define SQ_VOP3_0_SDST_ENC__OP_MASK 0x03FF0000L
-#define SQ_VOP3_0_SDST_ENC__ENCODING_MASK 0xFC000000L
-//SQ_VOP3_1
-#define SQ_VOP3_1__SRC0__SHIFT 0x0
-#define SQ_VOP3_1__SRC1__SHIFT 0x9
-#define SQ_VOP3_1__SRC2__SHIFT 0x12
-#define SQ_VOP3_1__OMOD__SHIFT 0x1b
-#define SQ_VOP3_1__NEG__SHIFT 0x1d
-#define SQ_VOP3_1__SRC0_MASK 0x000001FFL
-#define SQ_VOP3_1__SRC1_MASK 0x0003FE00L
-#define SQ_VOP3_1__SRC2_MASK 0x07FC0000L
-#define SQ_VOP3_1__OMOD_MASK 0x18000000L
-#define SQ_VOP3_1__NEG_MASK 0xE0000000L
-//SQ_VOPC
-#define SQ_VOPC__SRC0__SHIFT 0x0
-#define SQ_VOPC__VSRC1__SHIFT 0x9
-#define SQ_VOPC__OP__SHIFT 0x11
-#define SQ_VOPC__ENCODING__SHIFT 0x19
-#define SQ_VOPC__SRC0_MASK 0x000001FFL
-#define SQ_VOPC__VSRC1_MASK 0x0001FE00L
-#define SQ_VOPC__OP_MASK 0x01FE0000L
-#define SQ_VOPC__ENCODING_MASK 0xFE000000L
-//SQ_VOP_DPP
-#define SQ_VOP_DPP__SRC0__SHIFT 0x0
-#define SQ_VOP_DPP__DPP_CTRL__SHIFT 0x8
-#define SQ_VOP_DPP__BOUND_CTRL__SHIFT 0x13
-#define SQ_VOP_DPP__SRC0_NEG__SHIFT 0x14
-#define SQ_VOP_DPP__SRC0_ABS__SHIFT 0x15
-#define SQ_VOP_DPP__SRC1_NEG__SHIFT 0x16
-#define SQ_VOP_DPP__SRC1_ABS__SHIFT 0x17
-#define SQ_VOP_DPP__BANK_MASK__SHIFT 0x18
-#define SQ_VOP_DPP__ROW_MASK__SHIFT 0x1c
-#define SQ_VOP_DPP__SRC0_MASK 0x000000FFL
-#define SQ_VOP_DPP__DPP_CTRL_MASK 0x0001FF00L
-#define SQ_VOP_DPP__BOUND_CTRL_MASK 0x00080000L
-#define SQ_VOP_DPP__SRC0_NEG_MASK 0x00100000L
-#define SQ_VOP_DPP__SRC0_ABS_MASK 0x00200000L
-#define SQ_VOP_DPP__SRC1_NEG_MASK 0x00400000L
-#define SQ_VOP_DPP__SRC1_ABS_MASK 0x00800000L
-#define SQ_VOP_DPP__BANK_MASK_MASK 0x0F000000L
-#define SQ_VOP_DPP__ROW_MASK_MASK 0xF0000000L
-//SQ_VOP_SDWA
-#define SQ_VOP_SDWA__SRC0__SHIFT 0x0
-#define SQ_VOP_SDWA__DST_SEL__SHIFT 0x8
-#define SQ_VOP_SDWA__DST_UNUSED__SHIFT 0xb
-#define SQ_VOP_SDWA__CLAMP__SHIFT 0xd
-#define SQ_VOP_SDWA__OMOD__SHIFT 0xe
-#define SQ_VOP_SDWA__SRC0_SEL__SHIFT 0x10
-#define SQ_VOP_SDWA__SRC0_SEXT__SHIFT 0x13
-#define SQ_VOP_SDWA__SRC0_NEG__SHIFT 0x14
-#define SQ_VOP_SDWA__SRC0_ABS__SHIFT 0x15
-#define SQ_VOP_SDWA__S0__SHIFT 0x17
-#define SQ_VOP_SDWA__SRC1_SEL__SHIFT 0x18
-#define SQ_VOP_SDWA__SRC1_SEXT__SHIFT 0x1b
-#define SQ_VOP_SDWA__SRC1_NEG__SHIFT 0x1c
-#define SQ_VOP_SDWA__SRC1_ABS__SHIFT 0x1d
-#define SQ_VOP_SDWA__S1__SHIFT 0x1f
-#define SQ_VOP_SDWA__SRC0_MASK 0x000000FFL
-#define SQ_VOP_SDWA__DST_SEL_MASK 0x00000700L
-#define SQ_VOP_SDWA__DST_UNUSED_MASK 0x00001800L
-#define SQ_VOP_SDWA__CLAMP_MASK 0x00002000L
-#define SQ_VOP_SDWA__OMOD_MASK 0x0000C000L
-#define SQ_VOP_SDWA__SRC0_SEL_MASK 0x00070000L
-#define SQ_VOP_SDWA__SRC0_SEXT_MASK 0x00080000L
-#define SQ_VOP_SDWA__SRC0_NEG_MASK 0x00100000L
-#define SQ_VOP_SDWA__SRC0_ABS_MASK 0x00200000L
-#define SQ_VOP_SDWA__S0_MASK 0x00800000L
-#define SQ_VOP_SDWA__SRC1_SEL_MASK 0x07000000L
-#define SQ_VOP_SDWA__SRC1_SEXT_MASK 0x08000000L
-#define SQ_VOP_SDWA__SRC1_NEG_MASK 0x10000000L
-#define SQ_VOP_SDWA__SRC1_ABS_MASK 0x20000000L
-#define SQ_VOP_SDWA__S1_MASK 0x80000000L
-//SQ_VOP_SDWA_SDST_ENC
-#define SQ_VOP_SDWA_SDST_ENC__SRC0__SHIFT 0x0
-#define SQ_VOP_SDWA_SDST_ENC__SDST__SHIFT 0x8
-#define SQ_VOP_SDWA_SDST_ENC__SD__SHIFT 0xf
-#define SQ_VOP_SDWA_SDST_ENC__SRC0_SEL__SHIFT 0x10
-#define SQ_VOP_SDWA_SDST_ENC__SRC0_SEXT__SHIFT 0x13
-#define SQ_VOP_SDWA_SDST_ENC__SRC0_NEG__SHIFT 0x14
-#define SQ_VOP_SDWA_SDST_ENC__SRC0_ABS__SHIFT 0x15
-#define SQ_VOP_SDWA_SDST_ENC__S0__SHIFT 0x17
-#define SQ_VOP_SDWA_SDST_ENC__SRC1_SEL__SHIFT 0x18
-#define SQ_VOP_SDWA_SDST_ENC__SRC1_SEXT__SHIFT 0x1b
-#define SQ_VOP_SDWA_SDST_ENC__SRC1_NEG__SHIFT 0x1c
-#define SQ_VOP_SDWA_SDST_ENC__SRC1_ABS__SHIFT 0x1d
-#define SQ_VOP_SDWA_SDST_ENC__S1__SHIFT 0x1f
-#define SQ_VOP_SDWA_SDST_ENC__SRC0_MASK 0x000000FFL
-#define SQ_VOP_SDWA_SDST_ENC__SDST_MASK 0x00007F00L
-#define SQ_VOP_SDWA_SDST_ENC__SD_MASK 0x00008000L
-#define SQ_VOP_SDWA_SDST_ENC__SRC0_SEL_MASK 0x00070000L
-#define SQ_VOP_SDWA_SDST_ENC__SRC0_SEXT_MASK 0x00080000L
-#define SQ_VOP_SDWA_SDST_ENC__SRC0_NEG_MASK 0x00100000L
-#define SQ_VOP_SDWA_SDST_ENC__SRC0_ABS_MASK 0x00200000L
-#define SQ_VOP_SDWA_SDST_ENC__S0_MASK 0x00800000L
-#define SQ_VOP_SDWA_SDST_ENC__SRC1_SEL_MASK 0x07000000L
-#define SQ_VOP_SDWA_SDST_ENC__SRC1_SEXT_MASK 0x08000000L
-#define SQ_VOP_SDWA_SDST_ENC__SRC1_NEG_MASK 0x10000000L
-#define SQ_VOP_SDWA_SDST_ENC__SRC1_ABS_MASK 0x20000000L
-#define SQ_VOP_SDWA_SDST_ENC__S1_MASK 0x80000000L
-//SQ_LB_CTR_CTRL
-#define SQ_LB_CTR_CTRL__START__SHIFT 0x0
-#define SQ_LB_CTR_CTRL__LOAD__SHIFT 0x1
-#define SQ_LB_CTR_CTRL__CLEAR__SHIFT 0x2
-#define SQ_LB_CTR_CTRL__START_MASK 0x00000001L
-#define SQ_LB_CTR_CTRL__LOAD_MASK 0x00000002L
-#define SQ_LB_CTR_CTRL__CLEAR_MASK 0x00000004L
-//SQ_LB_DATA0
-#define SQ_LB_DATA0__DATA__SHIFT 0x0
-#define SQ_LB_DATA0__DATA_MASK 0xFFFFFFFFL
-//SQ_LB_DATA1
-#define SQ_LB_DATA1__DATA__SHIFT 0x0
-#define SQ_LB_DATA1__DATA_MASK 0xFFFFFFFFL
-//SQ_LB_DATA2
-#define SQ_LB_DATA2__DATA__SHIFT 0x0
-#define SQ_LB_DATA2__DATA_MASK 0xFFFFFFFFL
-//SQ_LB_DATA3
-#define SQ_LB_DATA3__DATA__SHIFT 0x0
-#define SQ_LB_DATA3__DATA_MASK 0xFFFFFFFFL
-//SQ_LB_CTR_SEL
-#define SQ_LB_CTR_SEL__SEL0__SHIFT 0x0
-#define SQ_LB_CTR_SEL__SEL1__SHIFT 0x4
-#define SQ_LB_CTR_SEL__SEL2__SHIFT 0x8
-#define SQ_LB_CTR_SEL__SEL3__SHIFT 0xc
-#define SQ_LB_CTR_SEL__SEL0_MASK 0x0000000FL
-#define SQ_LB_CTR_SEL__SEL1_MASK 0x000000F0L
-#define SQ_LB_CTR_SEL__SEL2_MASK 0x00000F00L
-#define SQ_LB_CTR_SEL__SEL3_MASK 0x0000F000L
-//SQ_LB_CTR0_CU
-#define SQ_LB_CTR0_CU__SH0_MASK__SHIFT 0x0
-#define SQ_LB_CTR0_CU__SH1_MASK__SHIFT 0x10
-#define SQ_LB_CTR0_CU__SH0_MASK_MASK 0x0000FFFFL
-#define SQ_LB_CTR0_CU__SH1_MASK_MASK 0xFFFF0000L
-//SQ_LB_CTR1_CU
-#define SQ_LB_CTR1_CU__SH0_MASK__SHIFT 0x0
-#define SQ_LB_CTR1_CU__SH1_MASK__SHIFT 0x10
-#define SQ_LB_CTR1_CU__SH0_MASK_MASK 0x0000FFFFL
-#define SQ_LB_CTR1_CU__SH1_MASK_MASK 0xFFFF0000L
-//SQ_LB_CTR2_CU
-#define SQ_LB_CTR2_CU__SH0_MASK__SHIFT 0x0
-#define SQ_LB_CTR2_CU__SH1_MASK__SHIFT 0x10
-#define SQ_LB_CTR2_CU__SH0_MASK_MASK 0x0000FFFFL
-#define SQ_LB_CTR2_CU__SH1_MASK_MASK 0xFFFF0000L
-//SQ_LB_CTR3_CU
-#define SQ_LB_CTR3_CU__SH0_MASK__SHIFT 0x0
-#define SQ_LB_CTR3_CU__SH1_MASK__SHIFT 0x10
-#define SQ_LB_CTR3_CU__SH0_MASK_MASK 0x0000FFFFL
-#define SQ_LB_CTR3_CU__SH1_MASK_MASK 0xFFFF0000L
-//SQC_EDC_CNT
-#define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x0
-#define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_DED_COUNT__SHIFT 0x2
-#define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x4
-#define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_DED_COUNT__SHIFT 0x6
-#define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x8
-#define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_DED_COUNT__SHIFT 0xa
-#define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_SEC_COUNT__SHIFT 0xc
-#define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_DED_COUNT__SHIFT 0xe
-#define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x10
-#define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_DED_COUNT__SHIFT 0x12
-#define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x14
-#define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_DED_COUNT__SHIFT 0x16
-#define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x18
-#define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_DED_COUNT__SHIFT 0x1a
-#define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x1c
-#define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_DED_COUNT__SHIFT 0x1e
-#define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_SEC_COUNT_MASK 0x00000003L
-#define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_DED_COUNT_MASK 0x0000000CL
-#define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_SEC_COUNT_MASK 0x00000030L
-#define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_DED_COUNT_MASK 0x000000C0L
-#define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_SEC_COUNT_MASK 0x00000300L
-#define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_DED_COUNT_MASK 0x00000C00L
-#define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_SEC_COUNT_MASK 0x00003000L
-#define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_DED_COUNT_MASK 0x0000C000L
-#define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_SEC_COUNT_MASK 0x00030000L
-#define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_DED_COUNT_MASK 0x000C0000L
-#define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_SEC_COUNT_MASK 0x00300000L
-#define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_DED_COUNT_MASK 0x00C00000L
-#define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_SEC_COUNT_MASK 0x03000000L
-#define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_DED_COUNT_MASK 0x0C000000L
-#define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_SEC_COUNT_MASK 0x30000000L
-#define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_DED_COUNT_MASK 0xC0000000L
-//SQ_EDC_SEC_CNT
-#define SQ_EDC_SEC_CNT__LDS_SEC__SHIFT 0x0
-#define SQ_EDC_SEC_CNT__SGPR_SEC__SHIFT 0x8
-#define SQ_EDC_SEC_CNT__VGPR_SEC__SHIFT 0x10
-#define SQ_EDC_SEC_CNT__LDS_SEC_MASK 0x000000FFL
-#define SQ_EDC_SEC_CNT__SGPR_SEC_MASK 0x0000FF00L
-#define SQ_EDC_SEC_CNT__VGPR_SEC_MASK 0x00FF0000L
-//SQ_EDC_DED_CNT
-#define SQ_EDC_DED_CNT__LDS_DED__SHIFT 0x0
-#define SQ_EDC_DED_CNT__SGPR_DED__SHIFT 0x8
-#define SQ_EDC_DED_CNT__VGPR_DED__SHIFT 0x10
-#define SQ_EDC_DED_CNT__LDS_DED_MASK 0x000000FFL
-#define SQ_EDC_DED_CNT__SGPR_DED_MASK 0x0000FF00L
-#define SQ_EDC_DED_CNT__VGPR_DED_MASK 0x00FF0000L
-//SQ_EDC_INFO
-#define SQ_EDC_INFO__WAVE_ID__SHIFT 0x0
-#define SQ_EDC_INFO__SIMD_ID__SHIFT 0x4
-#define SQ_EDC_INFO__SOURCE__SHIFT 0x6
-#define SQ_EDC_INFO__VM_ID__SHIFT 0x9
-#define SQ_EDC_INFO__WAVE_ID_MASK 0x0000000FL
-#define SQ_EDC_INFO__SIMD_ID_MASK 0x00000030L
-#define SQ_EDC_INFO__SOURCE_MASK 0x000001C0L
-#define SQ_EDC_INFO__VM_ID_MASK 0x00001E00L
-//SQ_EDC_CNT
-#define SQ_EDC_CNT__LDS_D_SEC_COUNT__SHIFT 0x0
-#define SQ_EDC_CNT__LDS_D_DED_COUNT__SHIFT 0x2
-#define SQ_EDC_CNT__LDS_I_SEC_COUNT__SHIFT 0x4
-#define SQ_EDC_CNT__LDS_I_DED_COUNT__SHIFT 0x6
-#define SQ_EDC_CNT__SGPR_SEC_COUNT__SHIFT 0x8
-#define SQ_EDC_CNT__SGPR_DED_COUNT__SHIFT 0xa
-#define SQ_EDC_CNT__VGPR0_SEC_COUNT__SHIFT 0xc
-#define SQ_EDC_CNT__VGPR0_DED_COUNT__SHIFT 0xe
-#define SQ_EDC_CNT__VGPR1_SEC_COUNT__SHIFT 0x10
-#define SQ_EDC_CNT__VGPR1_DED_COUNT__SHIFT 0x12
-#define SQ_EDC_CNT__VGPR2_SEC_COUNT__SHIFT 0x14
-#define SQ_EDC_CNT__VGPR2_DED_COUNT__SHIFT 0x16
-#define SQ_EDC_CNT__VGPR3_SEC_COUNT__SHIFT 0x18
-#define SQ_EDC_CNT__VGPR3_DED_COUNT__SHIFT 0x1a
-#define SQ_EDC_CNT__LDS_D_SEC_COUNT_MASK 0x00000003L
-#define SQ_EDC_CNT__LDS_D_DED_COUNT_MASK 0x0000000CL
-#define SQ_EDC_CNT__LDS_I_SEC_COUNT_MASK 0x00000030L
-#define SQ_EDC_CNT__LDS_I_DED_COUNT_MASK 0x000000C0L
-#define SQ_EDC_CNT__SGPR_SEC_COUNT_MASK 0x00000300L
-#define SQ_EDC_CNT__SGPR_DED_COUNT_MASK 0x00000C00L
-#define SQ_EDC_CNT__VGPR0_SEC_COUNT_MASK 0x00003000L
-#define SQ_EDC_CNT__VGPR0_DED_COUNT_MASK 0x0000C000L
-#define SQ_EDC_CNT__VGPR1_SEC_COUNT_MASK 0x00030000L
-#define SQ_EDC_CNT__VGPR1_DED_COUNT_MASK 0x000C0000L
-#define SQ_EDC_CNT__VGPR2_SEC_COUNT_MASK 0x00300000L
-#define SQ_EDC_CNT__VGPR2_DED_COUNT_MASK 0x00C00000L
-#define SQ_EDC_CNT__VGPR3_SEC_COUNT_MASK 0x03000000L
-#define SQ_EDC_CNT__VGPR3_DED_COUNT_MASK 0x0C000000L
-//SQ_EDC_FUE_CNTL
-#define SQ_EDC_FUE_CNTL__BLOCK_FUE_FLAGS__SHIFT 0x0
-#define SQ_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES__SHIFT 0x10
-#define SQ_EDC_FUE_CNTL__BLOCK_FUE_FLAGS_MASK 0x0000FFFFL
-#define SQ_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES_MASK 0xFFFF0000L
-//SQ_THREAD_TRACE_WORD_CMN
-#define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA__SHIFT 0x4
-#define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE_MASK 0x000FL
-#define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA_MASK 0x0010L
-//SQ_THREAD_TRACE_WORD_EVENT
-#define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA__SHIFT 0x4
-#define SQ_THREAD_TRACE_WORD_EVENT__SH_ID__SHIFT 0x5
-#define SQ_THREAD_TRACE_WORD_EVENT__STAGE__SHIFT 0x6
-#define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE__SHIFT 0xa
-#define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE_MASK 0x000FL
-#define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA_MASK 0x0010L
-#define SQ_THREAD_TRACE_WORD_EVENT__SH_ID_MASK 0x0020L
-#define SQ_THREAD_TRACE_WORD_EVENT__STAGE_MASK 0x01C0L
-#define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE_MASK 0xFC00L
-//SQ_THREAD_TRACE_WORD_INST
-#define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA__SHIFT 0x4
-#define SQ_THREAD_TRACE_WORD_INST__WAVE_ID__SHIFT 0x5
-#define SQ_THREAD_TRACE_WORD_INST__SIMD_ID__SHIFT 0x9
-#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE__SHIFT 0xb
-#define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE_MASK 0x000FL
-#define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA_MASK 0x0010L
-#define SQ_THREAD_TRACE_WORD_INST__WAVE_ID_MASK 0x01E0L
-#define SQ_THREAD_TRACE_WORD_INST__SIMD_ID_MASK 0x0600L
-#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE_MASK 0xF800L
-//SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2
-#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA__SHIFT 0x4
-#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID__SHIFT 0x5
-#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID__SHIFT 0x9
-#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TRAP_ERROR__SHIFT 0xf
-#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO__SHIFT 0x10
-#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL
-#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA_MASK 0x00000010L
-#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID_MASK 0x000001E0L
-#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID_MASK 0x00000600L
-#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TRAP_ERROR_MASK 0x00008000L
-#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO_MASK 0xFFFF0000L
-//SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2
-#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA__SHIFT 0x4
-#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID__SHIFT 0x5
-#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID__SHIFT 0x6
-#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID__SHIFT 0xa
-#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID__SHIFT 0xe
-#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO__SHIFT 0x10
-#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL
-#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA_MASK 0x00000010L
-#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID_MASK 0x00000020L
-#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID_MASK 0x000003C0L
-#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID_MASK 0x00003C00L
-#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID_MASK 0x0000C000L
-#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO_MASK 0xFFFF0000L
-//SQ_THREAD_TRACE_WORD_ISSUE
-#define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA__SHIFT 0x4
-#define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID__SHIFT 0x5
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST0__SHIFT 0x8
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST1__SHIFT 0xa
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST2__SHIFT 0xc
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST3__SHIFT 0xe
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST4__SHIFT 0x10
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST5__SHIFT 0x12
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST6__SHIFT 0x14
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST7__SHIFT 0x16
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST8__SHIFT 0x18
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST9__SHIFT 0x1a
-#define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE_MASK 0x0000000FL
-#define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA_MASK 0x00000010L
-#define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID_MASK 0x00000060L
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST0_MASK 0x00000300L
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST1_MASK 0x00000C00L
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST2_MASK 0x00003000L
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST3_MASK 0x0000C000L
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST4_MASK 0x00030000L
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST5_MASK 0x000C0000L
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST6_MASK 0x00300000L
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST7_MASK 0x00C00000L
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST8_MASK 0x03000000L
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST9_MASK 0x0C000000L
-//SQ_THREAD_TRACE_WORD_MISC
-#define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA__SHIFT 0x4
-#define SQ_THREAD_TRACE_WORD_MISC__SH_ID__SHIFT 0xc
-#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE__SHIFT 0xd
-#define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE_MASK 0x000FL
-#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA_MASK 0x0FF0L
-#define SQ_THREAD_TRACE_WORD_MISC__SH_ID_MASK 0x1000L
-#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE_MASK 0xE000L
-//SQ_THREAD_TRACE_WORD_PERF_1_OF_2
-#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA__SHIFT 0x4
-#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID__SHIFT 0x5
-#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID__SHIFT 0x6
-#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK__SHIFT 0xa
-#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0__SHIFT 0xc
-#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO__SHIFT 0x19
-#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL
-#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA_MASK 0x00000010L
-#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID_MASK 0x00000020L
-#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID_MASK 0x000003C0L
-#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK_MASK 0x00000C00L
-#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0_MASK 0x01FFF000L
-#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO_MASK 0xFE000000L
-//SQ_THREAD_TRACE_WORD_REG_1_OF_2
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA__SHIFT 0x4
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID__SHIFT 0x5
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID__SHIFT 0x7
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV__SHIFT 0x9
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE__SHIFT 0xa
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV__SHIFT 0xe
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP__SHIFT 0xf
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR__SHIFT 0x10
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA_MASK 0x00000010L
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID_MASK 0x00000060L
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID_MASK 0x00000180L
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV_MASK 0x00000200L
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE_MASK 0x00001C00L
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV_MASK 0x00004000L
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP_MASK 0x00008000L
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR_MASK 0xFFFF0000L
-//SQ_THREAD_TRACE_WORD_REG_2_OF_2
-#define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA_MASK 0xFFFFFFFFL
-//SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2
-#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA__SHIFT 0x4
-#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID__SHIFT 0x5
-#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID__SHIFT 0x7
-#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR__SHIFT 0x9
-#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO__SHIFT 0x10
-#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL
-#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA_MASK 0x00000010L
-#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID_MASK 0x00000060L
-#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID_MASK 0x00000180L
-#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR_MASK 0x0000FE00L
-#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO_MASK 0xFFFF0000L
-//SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2
-#define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI_MASK 0x0000FFFFL
-//SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2
-#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO__SHIFT 0x10
-#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL
-#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO_MASK 0xFFFF0000L
-//SQ_THREAD_TRACE_WORD_WAVE
-#define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA__SHIFT 0x4
-#define SQ_THREAD_TRACE_WORD_WAVE__SH_ID__SHIFT 0x5
-#define SQ_THREAD_TRACE_WORD_WAVE__CU_ID__SHIFT 0x6
-#define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID__SHIFT 0xa
-#define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID__SHIFT 0xe
-#define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE_MASK 0x000FL
-#define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA_MASK 0x0010L
-#define SQ_THREAD_TRACE_WORD_WAVE__SH_ID_MASK 0x0020L
-#define SQ_THREAD_TRACE_WORD_WAVE__CU_ID_MASK 0x03C0L
-#define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID_MASK 0x3C00L
-#define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID_MASK 0xC000L
-//SQ_THREAD_TRACE_WORD_WAVE_START
-#define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA__SHIFT 0x4
-#define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID__SHIFT 0x5
-#define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID__SHIFT 0x6
-#define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID__SHIFT 0xa
-#define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID__SHIFT 0xe
-#define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER__SHIFT 0x10
-#define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED__SHIFT 0x15
-#define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT__SHIFT 0x16
-#define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID__SHIFT 0x1d
-#define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE_MASK 0x0000000FL
-#define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA_MASK 0x00000010L
-#define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID_MASK 0x00000020L
-#define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID_MASK 0x000003C0L
-#define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID_MASK 0x00003C00L
-#define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID_MASK 0x0000C000L
-#define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER_MASK 0x001F0000L
-#define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED_MASK 0x00200000L
-#define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT_MASK 0x1FC00000L
-#define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID_MASK 0xE0000000L
-//SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2
-#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI_MASK 0x00FFFFFFL
-//SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2
-#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI_MASK 0xFFFFL
-//SQ_THREAD_TRACE_WORD_PERF_2_OF_2
-#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2__SHIFT 0x6
-#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3__SHIFT 0x13
-#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI_MASK 0x0000003FL
-#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2_MASK 0x0007FFC0L
-#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3_MASK 0xFFF80000L
-//SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2
-#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI_MASK 0xFFFFFFFFL
-//SQ_WREXEC_EXEC_HI
-#define SQ_WREXEC_EXEC_HI__ADDR_HI__SHIFT 0x0
-#define SQ_WREXEC_EXEC_HI__FIRST_WAVE__SHIFT 0x1a
-#define SQ_WREXEC_EXEC_HI__ATC__SHIFT 0x1b
-#define SQ_WREXEC_EXEC_HI__MTYPE__SHIFT 0x1c
-#define SQ_WREXEC_EXEC_HI__MSB__SHIFT 0x1f
-#define SQ_WREXEC_EXEC_HI__ADDR_HI_MASK 0x0000FFFFL
-#define SQ_WREXEC_EXEC_HI__FIRST_WAVE_MASK 0x04000000L
-#define SQ_WREXEC_EXEC_HI__ATC_MASK 0x08000000L
-#define SQ_WREXEC_EXEC_HI__MTYPE_MASK 0x70000000L
-#define SQ_WREXEC_EXEC_HI__MSB_MASK 0x80000000L
-//SQ_WREXEC_EXEC_LO
-#define SQ_WREXEC_EXEC_LO__ADDR_LO__SHIFT 0x0
-#define SQ_WREXEC_EXEC_LO__ADDR_LO_MASK 0xFFFFFFFFL
-//SQ_BUF_RSRC_WORD0
-#define SQ_BUF_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x0
-#define SQ_BUF_RSRC_WORD0__BASE_ADDRESS_MASK 0xFFFFFFFFL
-//SQ_BUF_RSRC_WORD1
-#define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0
-#define SQ_BUF_RSRC_WORD1__STRIDE__SHIFT 0x10
-#define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE__SHIFT 0x1e
-#define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE__SHIFT 0x1f
-#define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0x0000FFFFL
-#define SQ_BUF_RSRC_WORD1__STRIDE_MASK 0x3FFF0000L
-#define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE_MASK 0x40000000L
-#define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE_MASK 0x80000000L
-//SQ_BUF_RSRC_WORD2
-#define SQ_BUF_RSRC_WORD2__NUM_RECORDS__SHIFT 0x0
-#define SQ_BUF_RSRC_WORD2__NUM_RECORDS_MASK 0xFFFFFFFFL
-//SQ_BUF_RSRC_WORD3
-#define SQ_BUF_RSRC_WORD3__DST_SEL_X__SHIFT 0x0
-#define SQ_BUF_RSRC_WORD3__DST_SEL_Y__SHIFT 0x3
-#define SQ_BUF_RSRC_WORD3__DST_SEL_Z__SHIFT 0x6
-#define SQ_BUF_RSRC_WORD3__DST_SEL_W__SHIFT 0x9
-#define SQ_BUF_RSRC_WORD3__NUM_FORMAT__SHIFT 0xc
-#define SQ_BUF_RSRC_WORD3__DATA_FORMAT__SHIFT 0xf
-#define SQ_BUF_RSRC_WORD3__USER_VM_ENABLE__SHIFT 0x13
-#define SQ_BUF_RSRC_WORD3__USER_VM_MODE__SHIFT 0x14
-#define SQ_BUF_RSRC_WORD3__INDEX_STRIDE__SHIFT 0x15
-#define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE__SHIFT 0x17
-#define SQ_BUF_RSRC_WORD3__NV__SHIFT 0x1b
-#define SQ_BUF_RSRC_WORD3__TYPE__SHIFT 0x1e
-#define SQ_BUF_RSRC_WORD3__DST_SEL_X_MASK 0x00000007L
-#define SQ_BUF_RSRC_WORD3__DST_SEL_Y_MASK 0x00000038L
-#define SQ_BUF_RSRC_WORD3__DST_SEL_Z_MASK 0x000001C0L
-#define SQ_BUF_RSRC_WORD3__DST_SEL_W_MASK 0x00000E00L
-#define SQ_BUF_RSRC_WORD3__NUM_FORMAT_MASK 0x00007000L
-#define SQ_BUF_RSRC_WORD3__DATA_FORMAT_MASK 0x00078000L
-#define SQ_BUF_RSRC_WORD3__USER_VM_ENABLE_MASK 0x00080000L
-#define SQ_BUF_RSRC_WORD3__USER_VM_MODE_MASK 0x00100000L
-#define SQ_BUF_RSRC_WORD3__INDEX_STRIDE_MASK 0x00600000L
-#define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE_MASK 0x00800000L
-#define SQ_BUF_RSRC_WORD3__NV_MASK 0x08000000L
-#define SQ_BUF_RSRC_WORD3__TYPE_MASK 0xC0000000L
-//SQ_IMG_RSRC_WORD0
-#define SQ_IMG_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x0
-#define SQ_IMG_RSRC_WORD0__BASE_ADDRESS_MASK 0xFFFFFFFFL
-//SQ_IMG_RSRC_WORD1
-#define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0
-#define SQ_IMG_RSRC_WORD1__MIN_LOD__SHIFT 0x8
-#define SQ_IMG_RSRC_WORD1__DATA_FORMAT__SHIFT 0x14
-#define SQ_IMG_RSRC_WORD1__NUM_FORMAT__SHIFT 0x1a
-#define SQ_IMG_RSRC_WORD1__NV__SHIFT 0x1e
-#define SQ_IMG_RSRC_WORD1__META_DIRECT__SHIFT 0x1f
-#define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0x000000FFL
-#define SQ_IMG_RSRC_WORD1__MIN_LOD_MASK 0x000FFF00L
-#define SQ_IMG_RSRC_WORD1__DATA_FORMAT_MASK 0x03F00000L
-#define SQ_IMG_RSRC_WORD1__NUM_FORMAT_MASK 0x3C000000L
-#define SQ_IMG_RSRC_WORD1__NV_MASK 0x40000000L
-#define SQ_IMG_RSRC_WORD1__META_DIRECT_MASK 0x80000000L
-//SQ_IMG_RSRC_WORD2
-#define SQ_IMG_RSRC_WORD2__WIDTH__SHIFT 0x0
-#define SQ_IMG_RSRC_WORD2__HEIGHT__SHIFT 0xe
-#define SQ_IMG_RSRC_WORD2__PERF_MOD__SHIFT 0x1c
-#define SQ_IMG_RSRC_WORD2__WIDTH_MASK 0x00003FFFL
-#define SQ_IMG_RSRC_WORD2__HEIGHT_MASK 0x0FFFC000L
-#define SQ_IMG_RSRC_WORD2__PERF_MOD_MASK 0x70000000L
-//SQ_IMG_RSRC_WORD3
-#define SQ_IMG_RSRC_WORD3__DST_SEL_X__SHIFT 0x0
-#define SQ_IMG_RSRC_WORD3__DST_SEL_Y__SHIFT 0x3
-#define SQ_IMG_RSRC_WORD3__DST_SEL_Z__SHIFT 0x6
-#define SQ_IMG_RSRC_WORD3__DST_SEL_W__SHIFT 0x9
-#define SQ_IMG_RSRC_WORD3__BASE_LEVEL__SHIFT 0xc
-#define SQ_IMG_RSRC_WORD3__LAST_LEVEL__SHIFT 0x10
-#define SQ_IMG_RSRC_WORD3__SW_MODE__SHIFT 0x14
-#define SQ_IMG_RSRC_WORD3__TYPE__SHIFT 0x1c
-#define SQ_IMG_RSRC_WORD3__DST_SEL_X_MASK 0x00000007L
-#define SQ_IMG_RSRC_WORD3__DST_SEL_Y_MASK 0x00000038L
-#define SQ_IMG_RSRC_WORD3__DST_SEL_Z_MASK 0x000001C0L
-#define SQ_IMG_RSRC_WORD3__DST_SEL_W_MASK 0x00000E00L
-#define SQ_IMG_RSRC_WORD3__BASE_LEVEL_MASK 0x0000F000L
-#define SQ_IMG_RSRC_WORD3__LAST_LEVEL_MASK 0x000F0000L
-#define SQ_IMG_RSRC_WORD3__SW_MODE_MASK 0x01F00000L
-#define SQ_IMG_RSRC_WORD3__TYPE_MASK 0xF0000000L
-//SQ_IMG_RSRC_WORD4
-#define SQ_IMG_RSRC_WORD4__DEPTH__SHIFT 0x0
-#define SQ_IMG_RSRC_WORD4__PITCH__SHIFT 0xd
-#define SQ_IMG_RSRC_WORD4__BC_SWIZZLE__SHIFT 0x1d
-#define SQ_IMG_RSRC_WORD4__DEPTH_MASK 0x00001FFFL
-#define SQ_IMG_RSRC_WORD4__PITCH_MASK 0x1FFFE000L
-#define SQ_IMG_RSRC_WORD4__BC_SWIZZLE_MASK 0xE0000000L
-//SQ_IMG_RSRC_WORD5
-#define SQ_IMG_RSRC_WORD5__BASE_ARRAY__SHIFT 0x0
-#define SQ_IMG_RSRC_WORD5__ARRAY_PITCH__SHIFT 0xd
-#define SQ_IMG_RSRC_WORD5__META_DATA_ADDRESS__SHIFT 0x11
-#define SQ_IMG_RSRC_WORD5__META_LINEAR__SHIFT 0x19
-#define SQ_IMG_RSRC_WORD5__META_PIPE_ALIGNED__SHIFT 0x1a
-#define SQ_IMG_RSRC_WORD5__META_RB_ALIGNED__SHIFT 0x1b
-#define SQ_IMG_RSRC_WORD5__MAX_MIP__SHIFT 0x1c
-#define SQ_IMG_RSRC_WORD5__BASE_ARRAY_MASK 0x00001FFFL
-#define SQ_IMG_RSRC_WORD5__ARRAY_PITCH_MASK 0x0001E000L
-#define SQ_IMG_RSRC_WORD5__META_DATA_ADDRESS_MASK 0x01FE0000L
-#define SQ_IMG_RSRC_WORD5__META_LINEAR_MASK 0x02000000L
-#define SQ_IMG_RSRC_WORD5__META_PIPE_ALIGNED_MASK 0x04000000L
-#define SQ_IMG_RSRC_WORD5__META_RB_ALIGNED_MASK 0x08000000L
-#define SQ_IMG_RSRC_WORD5__MAX_MIP_MASK 0xF0000000L
-//SQ_IMG_RSRC_WORD6
-#define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN__SHIFT 0x0
-#define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID__SHIFT 0xc
-#define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN__SHIFT 0x14
-#define SQ_IMG_RSRC_WORD6__COMPRESSION_EN__SHIFT 0x15
-#define SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB__SHIFT 0x16
-#define SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM__SHIFT 0x17
-#define SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS__SHIFT 0x18
-#define SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS__SHIFT 0x1c
-#define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN_MASK 0x00000FFFL
-#define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID_MASK 0x000FF000L
-#define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN_MASK 0x00100000L
-#define SQ_IMG_RSRC_WORD6__COMPRESSION_EN_MASK 0x00200000L
-#define SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB_MASK 0x00400000L
-#define SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM_MASK 0x00800000L
-#define SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS_MASK 0x0F000000L
-#define SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS_MASK 0xF0000000L
-//SQ_IMG_RSRC_WORD7
-#define SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS__SHIFT 0x0
-#define SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS_MASK 0xFFFFFFFFL
-//SQ_IMG_SAMP_WORD0
-#define SQ_IMG_SAMP_WORD0__CLAMP_X__SHIFT 0x0
-#define SQ_IMG_SAMP_WORD0__CLAMP_Y__SHIFT 0x3
-#define SQ_IMG_SAMP_WORD0__CLAMP_Z__SHIFT 0x6
-#define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO__SHIFT 0x9
-#define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC__SHIFT 0xc
-#define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED__SHIFT 0xf
-#define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD__SHIFT 0x10
-#define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC__SHIFT 0x13
-#define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA__SHIFT 0x14
-#define SQ_IMG_SAMP_WORD0__ANISO_BIAS__SHIFT 0x15
-#define SQ_IMG_SAMP_WORD0__TRUNC_COORD__SHIFT 0x1b
-#define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP__SHIFT 0x1c
-#define SQ_IMG_SAMP_WORD0__FILTER_MODE__SHIFT 0x1d
-#define SQ_IMG_SAMP_WORD0__COMPAT_MODE__SHIFT 0x1f
-#define SQ_IMG_SAMP_WORD0__CLAMP_X_MASK 0x00000007L
-#define SQ_IMG_SAMP_WORD0__CLAMP_Y_MASK 0x00000038L
-#define SQ_IMG_SAMP_WORD0__CLAMP_Z_MASK 0x000001C0L
-#define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO_MASK 0x00000E00L
-#define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC_MASK 0x00007000L
-#define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED_MASK 0x00008000L
-#define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD_MASK 0x00070000L
-#define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC_MASK 0x00080000L
-#define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA_MASK 0x00100000L
-#define SQ_IMG_SAMP_WORD0__ANISO_BIAS_MASK 0x07E00000L
-#define SQ_IMG_SAMP_WORD0__TRUNC_COORD_MASK 0x08000000L
-#define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP_MASK 0x10000000L
-#define SQ_IMG_SAMP_WORD0__FILTER_MODE_MASK 0x60000000L
-#define SQ_IMG_SAMP_WORD0__COMPAT_MODE_MASK 0x80000000L
-//SQ_IMG_SAMP_WORD1
-#define SQ_IMG_SAMP_WORD1__MIN_LOD__SHIFT 0x0
-#define SQ_IMG_SAMP_WORD1__MAX_LOD__SHIFT 0xc
-#define SQ_IMG_SAMP_WORD1__PERF_MIP__SHIFT 0x18
-#define SQ_IMG_SAMP_WORD1__PERF_Z__SHIFT 0x1c
-#define SQ_IMG_SAMP_WORD1__MIN_LOD_MASK 0x00000FFFL
-#define SQ_IMG_SAMP_WORD1__MAX_LOD_MASK 0x00FFF000L
-#define SQ_IMG_SAMP_WORD1__PERF_MIP_MASK 0x0F000000L
-#define SQ_IMG_SAMP_WORD1__PERF_Z_MASK 0xF0000000L
-//SQ_IMG_SAMP_WORD2
-#define SQ_IMG_SAMP_WORD2__LOD_BIAS__SHIFT 0x0
-#define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC__SHIFT 0xe
-#define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER__SHIFT 0x14
-#define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER__SHIFT 0x16
-#define SQ_IMG_SAMP_WORD2__Z_FILTER__SHIFT 0x18
-#define SQ_IMG_SAMP_WORD2__MIP_FILTER__SHIFT 0x1a
-#define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP__SHIFT 0x1c
-#define SQ_IMG_SAMP_WORD2__BLEND_ZERO_PRT__SHIFT 0x1d
-#define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX__SHIFT 0x1e
-#define SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE__SHIFT 0x1f
-#define SQ_IMG_SAMP_WORD2__LOD_BIAS_MASK 0x00003FFFL
-#define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC_MASK 0x000FC000L
-#define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER_MASK 0x00300000L
-#define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER_MASK 0x00C00000L
-#define SQ_IMG_SAMP_WORD2__Z_FILTER_MASK 0x03000000L
-#define SQ_IMG_SAMP_WORD2__MIP_FILTER_MASK 0x0C000000L
-#define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP_MASK 0x10000000L
-#define SQ_IMG_SAMP_WORD2__BLEND_ZERO_PRT_MASK 0x20000000L
-#define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX_MASK 0x40000000L
-#define SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE_MASK 0x80000000L
-//SQ_IMG_SAMP_WORD3
-#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR__SHIFT 0x0
-#define SQ_IMG_SAMP_WORD3__SKIP_DEGAMMA__SHIFT 0xc
-#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE__SHIFT 0x1e
-#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR_MASK 0x00000FFFL
-#define SQ_IMG_SAMP_WORD3__SKIP_DEGAMMA_MASK 0x00001000L
-#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE_MASK 0xC0000000L
-//SQ_FLAT_SCRATCH_WORD0
-#define SQ_FLAT_SCRATCH_WORD0__SIZE__SHIFT 0x0
-#define SQ_FLAT_SCRATCH_WORD0__SIZE_MASK 0x0007FFFFL
-//SQ_FLAT_SCRATCH_WORD1
-#define SQ_FLAT_SCRATCH_WORD1__OFFSET__SHIFT 0x0
-#define SQ_FLAT_SCRATCH_WORD1__OFFSET_MASK 0x00FFFFFFL
-//SQ_M0_GPR_IDX_WORD
-#define SQ_M0_GPR_IDX_WORD__INDEX__SHIFT 0x0
-#define SQ_M0_GPR_IDX_WORD__VSRC0_REL__SHIFT 0xc
-#define SQ_M0_GPR_IDX_WORD__VSRC1_REL__SHIFT 0xd
-#define SQ_M0_GPR_IDX_WORD__VSRC2_REL__SHIFT 0xe
-#define SQ_M0_GPR_IDX_WORD__VDST_REL__SHIFT 0xf
-#define SQ_M0_GPR_IDX_WORD__INDEX_MASK 0x000000FFL
-#define SQ_M0_GPR_IDX_WORD__VSRC0_REL_MASK 0x00001000L
-#define SQ_M0_GPR_IDX_WORD__VSRC1_REL_MASK 0x00002000L
-#define SQ_M0_GPR_IDX_WORD__VSRC2_REL_MASK 0x00004000L
-#define SQ_M0_GPR_IDX_WORD__VDST_REL_MASK 0x00008000L
-//SQC_ICACHE_UTCL1_CNTL1
-#define SQC_ICACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0
-#define SQC_ICACHE_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1
-#define SQC_ICACHE_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2
-#define SQC_ICACHE_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3
-#define SQC_ICACHE_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5
-#define SQC_ICACHE_UTCL1_CNTL1__CLIENTID__SHIFT 0x7
-#define SQC_ICACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11
-#define SQC_ICACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12
-#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT 0x13
-#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT 0x17
-#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT 0x18
-#define SQC_ICACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19
-#define SQC_ICACHE_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a
-#define SQC_ICACHE_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b
-#define SQC_ICACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
-#define SQC_ICACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
-#define SQC_ICACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L
-#define SQC_ICACHE_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L
-#define SQC_ICACHE_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L
-#define SQC_ICACHE_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L
-#define SQC_ICACHE_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L
-#define SQC_ICACHE_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L
-#define SQC_ICACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L
-#define SQC_ICACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L
-#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK 0x00780000L
-#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK 0x00800000L
-#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK 0x01000000L
-#define SQC_ICACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L
-#define SQC_ICACHE_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L
-#define SQC_ICACHE_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L
-#define SQC_ICACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L
-#define SQC_ICACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L
-//SQC_ICACHE_UTCL1_CNTL2
-#define SQC_ICACHE_UTCL1_CNTL2__SPARE__SHIFT 0x0
-#define SQC_ICACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x8
-#define SQC_ICACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9
-#define SQC_ICACHE_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa
-#define SQC_ICACHE_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb
-#define SQC_ICACHE_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc
-#define SQC_ICACHE_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd
-#define SQC_ICACHE_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe
-#define SQC_ICACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf
-#define SQC_ICACHE_UTCL1_CNTL2__ARB_BURST_MODE__SHIFT 0x10
-#define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12
-#define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13
-#define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14
-#define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT 0x15
-#define SQC_ICACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a
-#define SQC_ICACHE_UTCL1_CNTL2__SPARE_MASK 0x000000FFL
-#define SQC_ICACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L
-#define SQC_ICACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L
-#define SQC_ICACHE_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L
-#define SQC_ICACHE_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L
-#define SQC_ICACHE_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L
-#define SQC_ICACHE_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L
-#define SQC_ICACHE_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L
-#define SQC_ICACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L
-#define SQC_ICACHE_UTCL1_CNTL2__ARB_BURST_MODE_MASK 0x00030000L
-#define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L
-#define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L
-#define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L
-#define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L
-#define SQC_ICACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L
-//SQC_DCACHE_UTCL1_CNTL1
-#define SQC_DCACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0
-#define SQC_DCACHE_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1
-#define SQC_DCACHE_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2
-#define SQC_DCACHE_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3
-#define SQC_DCACHE_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5
-#define SQC_DCACHE_UTCL1_CNTL1__CLIENTID__SHIFT 0x7
-#define SQC_DCACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11
-#define SQC_DCACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12
-#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT 0x13
-#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT 0x17
-#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT 0x18
-#define SQC_DCACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19
-#define SQC_DCACHE_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a
-#define SQC_DCACHE_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b
-#define SQC_DCACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
-#define SQC_DCACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
-#define SQC_DCACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L
-#define SQC_DCACHE_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L
-#define SQC_DCACHE_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L
-#define SQC_DCACHE_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L
-#define SQC_DCACHE_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L
-#define SQC_DCACHE_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L
-#define SQC_DCACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L
-#define SQC_DCACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L
-#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK 0x00780000L
-#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK 0x00800000L
-#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK 0x01000000L
-#define SQC_DCACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L
-#define SQC_DCACHE_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L
-#define SQC_DCACHE_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L
-#define SQC_DCACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L
-#define SQC_DCACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L
-//SQC_DCACHE_UTCL1_CNTL2
-#define SQC_DCACHE_UTCL1_CNTL2__SPARE__SHIFT 0x0
-#define SQC_DCACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x8
-#define SQC_DCACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9
-#define SQC_DCACHE_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa
-#define SQC_DCACHE_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb
-#define SQC_DCACHE_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc
-#define SQC_DCACHE_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd
-#define SQC_DCACHE_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe
-#define SQC_DCACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf
-#define SQC_DCACHE_UTCL1_CNTL2__ARB_BURST_MODE__SHIFT 0x10
-#define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12
-#define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13
-#define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14
-#define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT 0x15
-#define SQC_DCACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a
-#define SQC_DCACHE_UTCL1_CNTL2__SPARE_MASK 0x000000FFL
-#define SQC_DCACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L
-#define SQC_DCACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L
-#define SQC_DCACHE_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L
-#define SQC_DCACHE_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L
-#define SQC_DCACHE_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L
-#define SQC_DCACHE_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L
-#define SQC_DCACHE_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L
-#define SQC_DCACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L
-#define SQC_DCACHE_UTCL1_CNTL2__ARB_BURST_MODE_MASK 0x00030000L
-#define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L
-#define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L
-#define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L
-#define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L
-#define SQC_DCACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L
-//SQC_ICACHE_UTCL1_STATUS
-#define SQC_ICACHE_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
-#define SQC_ICACHE_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
-#define SQC_ICACHE_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
-#define SQC_ICACHE_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
-#define SQC_ICACHE_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
-#define SQC_ICACHE_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
-//SQC_DCACHE_UTCL1_STATUS
-#define SQC_DCACHE_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
-#define SQC_DCACHE_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
-#define SQC_DCACHE_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
-#define SQC_DCACHE_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
-#define SQC_DCACHE_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
-#define SQC_DCACHE_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
-
-
-// addressBlock: gc_shsdec
-//SX_DEBUG_1
-#define SX_DEBUG_1__SX_DB_QUAD_CREDIT__SHIFT 0x0
-#define SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x8
-#define SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x9
-#define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0xa
-#define SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT__SHIFT 0xb
-#define SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT__SHIFT 0xc
-#define SX_DEBUG_1__PC_CFG__SHIFT 0xd
-#define SX_DEBUG_1__DEBUG_DATA__SHIFT 0xe
-#define SX_DEBUG_1__SX_DB_QUAD_CREDIT_MASK 0x0000007FL
-#define SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x00000100L
-#define SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS_MASK 0x00000200L
-#define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x00000400L
-#define SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT_MASK 0x00000800L
-#define SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT_MASK 0x00001000L
-#define SX_DEBUG_1__PC_CFG_MASK 0x00002000L
-#define SX_DEBUG_1__DEBUG_DATA_MASK 0xFFFFC000L
-//SPI_PS_MAX_WAVE_ID
-#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0
-#define SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID__SHIFT 0x10
-#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL
-#define SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID_MASK 0x03FF0000L
-//SPI_START_PHASE
-#define SPI_START_PHASE__VGPR_START_PHASE__SHIFT 0x0
-#define SPI_START_PHASE__SGPR_START_PHASE__SHIFT 0x2
-#define SPI_START_PHASE__WAVE_START_PHASE__SHIFT 0x4
-#define SPI_START_PHASE__VGPR_START_PHASE_MASK 0x00000003L
-#define SPI_START_PHASE__SGPR_START_PHASE_MASK 0x0000000CL
-#define SPI_START_PHASE__WAVE_START_PHASE_MASK 0x00000030L
-//SPI_GFX_CNTL
-#define SPI_GFX_CNTL__RESET_COUNTS__SHIFT 0x0
-#define SPI_GFX_CNTL__RESET_COUNTS_MASK 0x00000001L
-//SPI_DSM_CNTL
-#define SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA__SHIFT 0x0
-#define SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE__SHIFT 0x2
-#define SPI_DSM_CNTL__UNUSED__SHIFT 0x3
-#define SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA_MASK 0x00000003L
-#define SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
-#define SPI_DSM_CNTL__UNUSED_MASK 0xFFFFFFF8L
-//SPI_DSM_CNTL2
-#define SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT__SHIFT 0x0
-#define SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY__SHIFT 0x2
-#define SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY__SHIFT 0x4
-#define SPI_DSM_CNTL2__UNUSED__SHIFT 0xa
-#define SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT_MASK 0x00000003L
-#define SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY_MASK 0x00000004L
-#define SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY_MASK 0x000003F0L
-#define SPI_DSM_CNTL2__UNUSED_MASK 0xFFFFFC00L
-//SPI_EDC_CNT
-#define SPI_EDC_CNT__SPI_SR_MEM_SED_COUNT__SHIFT 0x0
-#define SPI_EDC_CNT__SPI_SR_MEM_SED_COUNT_MASK 0x00000003L
-//SPI_CONFIG_PS_CU_EN
-#define SPI_CONFIG_PS_CU_EN__ENABLE__SHIFT 0x0
-#define SPI_CONFIG_PS_CU_EN__PKR0_CU_EN__SHIFT 0x1
-#define SPI_CONFIG_PS_CU_EN__PKR1_CU_EN__SHIFT 0x10
-#define SPI_CONFIG_PS_CU_EN__ENABLE_MASK 0x00000001L
-#define SPI_CONFIG_PS_CU_EN__PKR0_CU_EN_MASK 0x0000FFFEL
-#define SPI_CONFIG_PS_CU_EN__PKR1_CU_EN_MASK 0xFFFF0000L
-//SPI_WF_LIFETIME_CNTL
-#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD__SHIFT 0x0
-#define SPI_WF_LIFETIME_CNTL__EN__SHIFT 0x4
-#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD_MASK 0x0000000FL
-#define SPI_WF_LIFETIME_CNTL__EN_MASK 0x00000010L
-//SPI_WF_LIFETIME_LIMIT_0
-#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN__SHIFT 0x1f
-#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN_MASK 0x80000000L
-//SPI_WF_LIFETIME_LIMIT_1
-#define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_LIMIT_1__EN_WARN__SHIFT 0x1f
-#define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_LIMIT_1__EN_WARN_MASK 0x80000000L
-//SPI_WF_LIFETIME_LIMIT_2
-#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN__SHIFT 0x1f
-#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN_MASK 0x80000000L
-//SPI_WF_LIFETIME_LIMIT_3
-#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN__SHIFT 0x1f
-#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN_MASK 0x80000000L
-//SPI_WF_LIFETIME_LIMIT_4
-#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN__SHIFT 0x1f
-#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN_MASK 0x80000000L
-//SPI_WF_LIFETIME_LIMIT_5
-#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN__SHIFT 0x1f
-#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN_MASK 0x80000000L
-//SPI_WF_LIFETIME_LIMIT_6
-#define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_LIMIT_6__EN_WARN__SHIFT 0x1f
-#define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_LIMIT_6__EN_WARN_MASK 0x80000000L
-//SPI_WF_LIFETIME_LIMIT_7
-#define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_LIMIT_7__EN_WARN__SHIFT 0x1f
-#define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_LIMIT_7__EN_WARN_MASK 0x80000000L
-//SPI_WF_LIFETIME_LIMIT_8
-#define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_LIMIT_8__EN_WARN__SHIFT 0x1f
-#define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_LIMIT_8__EN_WARN_MASK 0x80000000L
-//SPI_WF_LIFETIME_LIMIT_9
-#define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_LIMIT_9__EN_WARN__SHIFT 0x1f
-#define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_LIMIT_9__EN_WARN_MASK 0x80000000L
-//SPI_WF_LIFETIME_STATUS_0
-#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_0__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_STATUS_0__INT_SENT_MASK 0x80000000L
-//SPI_WF_LIFETIME_STATUS_1
-#define SPI_WF_LIFETIME_STATUS_1__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_1__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_1__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_STATUS_1__INT_SENT_MASK 0x80000000L
-//SPI_WF_LIFETIME_STATUS_2
-#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_2__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_STATUS_2__INT_SENT_MASK 0x80000000L
-//SPI_WF_LIFETIME_STATUS_3
-#define SPI_WF_LIFETIME_STATUS_3__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_3__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_3__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_STATUS_3__INT_SENT_MASK 0x80000000L
-//SPI_WF_LIFETIME_STATUS_4
-#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_4__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_STATUS_4__INT_SENT_MASK 0x80000000L
-//SPI_WF_LIFETIME_STATUS_5
-#define SPI_WF_LIFETIME_STATUS_5__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_5__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_5__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_STATUS_5__INT_SENT_MASK 0x80000000L
-//SPI_WF_LIFETIME_STATUS_6
-#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_6__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_STATUS_6__INT_SENT_MASK 0x80000000L
-//SPI_WF_LIFETIME_STATUS_7
-#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_7__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_STATUS_7__INT_SENT_MASK 0x80000000L
-//SPI_WF_LIFETIME_STATUS_8
-#define SPI_WF_LIFETIME_STATUS_8__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_8__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_8__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_STATUS_8__INT_SENT_MASK 0x80000000L
-//SPI_WF_LIFETIME_STATUS_9
-#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_9__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_STATUS_9__INT_SENT_MASK 0x80000000L
-//SPI_WF_LIFETIME_STATUS_10
-#define SPI_WF_LIFETIME_STATUS_10__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_10__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_10__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_STATUS_10__INT_SENT_MASK 0x80000000L
-//SPI_WF_LIFETIME_STATUS_11
-#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_11__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_STATUS_11__INT_SENT_MASK 0x80000000L
-//SPI_WF_LIFETIME_STATUS_12
-#define SPI_WF_LIFETIME_STATUS_12__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_12__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_12__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_STATUS_12__INT_SENT_MASK 0x80000000L
-//SPI_WF_LIFETIME_STATUS_13
-#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_13__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_STATUS_13__INT_SENT_MASK 0x80000000L
-//SPI_WF_LIFETIME_STATUS_14
-#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_14__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_STATUS_14__INT_SENT_MASK 0x80000000L
-//SPI_WF_LIFETIME_STATUS_15
-#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_15__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_STATUS_15__INT_SENT_MASK 0x80000000L
-//SPI_WF_LIFETIME_STATUS_16
-#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_16__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_STATUS_16__INT_SENT_MASK 0x80000000L
-//SPI_WF_LIFETIME_STATUS_17
-#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_17__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_STATUS_17__INT_SENT_MASK 0x80000000L
-//SPI_WF_LIFETIME_STATUS_18
-#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_18__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_STATUS_18__INT_SENT_MASK 0x80000000L
-//SPI_WF_LIFETIME_STATUS_19
-#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_19__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_STATUS_19__INT_SENT_MASK 0x80000000L
-//SPI_WF_LIFETIME_STATUS_20
-#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_20__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_STATUS_20__INT_SENT_MASK 0x80000000L
-//SPI_LB_CTR_CTRL
-#define SPI_LB_CTR_CTRL__LOAD__SHIFT 0x0
-#define SPI_LB_CTR_CTRL__WAVES_SELECT__SHIFT 0x1
-#define SPI_LB_CTR_CTRL__CLEAR_ON_READ__SHIFT 0x3
-#define SPI_LB_CTR_CTRL__RESET_COUNTS__SHIFT 0x4
-#define SPI_LB_CTR_CTRL__LOAD_MASK 0x00000001L
-#define SPI_LB_CTR_CTRL__WAVES_SELECT_MASK 0x00000006L
-#define SPI_LB_CTR_CTRL__CLEAR_ON_READ_MASK 0x00000008L
-#define SPI_LB_CTR_CTRL__RESET_COUNTS_MASK 0x00000010L
-//SPI_LB_CU_MASK
-#define SPI_LB_CU_MASK__CU_MASK__SHIFT 0x0
-#define SPI_LB_CU_MASK__CU_MASK_MASK 0xFFFFL
-//SPI_LB_DATA_REG
-#define SPI_LB_DATA_REG__CNT_DATA__SHIFT 0x0
-#define SPI_LB_DATA_REG__CNT_DATA_MASK 0xFFFFFFFFL
-//SPI_PG_ENABLE_STATIC_CU_MASK
-#define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK__SHIFT 0x0
-#define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK_MASK 0xFFFFL
-//SPI_GDS_CREDITS
-#define SPI_GDS_CREDITS__DS_DATA_CREDITS__SHIFT 0x0
-#define SPI_GDS_CREDITS__DS_CMD_CREDITS__SHIFT 0x8
-#define SPI_GDS_CREDITS__UNUSED__SHIFT 0x10
-#define SPI_GDS_CREDITS__DS_DATA_CREDITS_MASK 0x000000FFL
-#define SPI_GDS_CREDITS__DS_CMD_CREDITS_MASK 0x0000FF00L
-#define SPI_GDS_CREDITS__UNUSED_MASK 0xFFFF0000L
-//SPI_SX_EXPORT_BUFFER_SIZES
-#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE__SHIFT 0x0
-#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE__SHIFT 0x10
-#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE_MASK 0x0000FFFFL
-#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE_MASK 0xFFFF0000L
-//SPI_SX_SCOREBOARD_BUFFER_SIZES
-#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE__SHIFT 0x0
-#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE__SHIFT 0x10
-#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE_MASK 0x0000FFFFL
-#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE_MASK 0xFFFF0000L
-//SPI_CSQ_WF_ACTIVE_STATUS
-#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE__SHIFT 0x0
-#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE_MASK 0xFFFFFFFFL
-//SPI_CSQ_WF_ACTIVE_COUNT_0
-#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT__SHIFT 0x0
-#define SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS__SHIFT 0x10
-#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK 0x000007FFL
-#define SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS_MASK 0x07FF0000L
-//SPI_CSQ_WF_ACTIVE_COUNT_1
-#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT__SHIFT 0x0
-#define SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS__SHIFT 0x10
-#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT_MASK 0x000007FFL
-#define SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS_MASK 0x07FF0000L
-//SPI_CSQ_WF_ACTIVE_COUNT_2
-#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT__SHIFT 0x0
-#define SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS__SHIFT 0x10
-#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT_MASK 0x000007FFL
-#define SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS_MASK 0x07FF0000L
-//SPI_CSQ_WF_ACTIVE_COUNT_3
-#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT__SHIFT 0x0
-#define SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS__SHIFT 0x10
-#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT_MASK 0x000007FFL
-#define SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS_MASK 0x07FF0000L
-//SPI_CSQ_WF_ACTIVE_COUNT_4
-#define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT__SHIFT 0x0
-#define SPI_CSQ_WF_ACTIVE_COUNT_4__EVENTS__SHIFT 0x10
-#define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT_MASK 0x000007FFL
-#define SPI_CSQ_WF_ACTIVE_COUNT_4__EVENTS_MASK 0x07FF0000L
-//SPI_CSQ_WF_ACTIVE_COUNT_5
-#define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT__SHIFT 0x0
-#define SPI_CSQ_WF_ACTIVE_COUNT_5__EVENTS__SHIFT 0x10
-#define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT_MASK 0x000007FFL
-#define SPI_CSQ_WF_ACTIVE_COUNT_5__EVENTS_MASK 0x07FF0000L
-//SPI_CSQ_WF_ACTIVE_COUNT_6
-#define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT__SHIFT 0x0
-#define SPI_CSQ_WF_ACTIVE_COUNT_6__EVENTS__SHIFT 0x10
-#define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT_MASK 0x000007FFL
-#define SPI_CSQ_WF_ACTIVE_COUNT_6__EVENTS_MASK 0x07FF0000L
-//SPI_CSQ_WF_ACTIVE_COUNT_7
-#define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT__SHIFT 0x0
-#define SPI_CSQ_WF_ACTIVE_COUNT_7__EVENTS__SHIFT 0x10
-#define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT_MASK 0x000007FFL
-#define SPI_CSQ_WF_ACTIVE_COUNT_7__EVENTS_MASK 0x07FF0000L
-//SPI_LB_DATA_WAVES
-#define SPI_LB_DATA_WAVES__COUNT0__SHIFT 0x0
-#define SPI_LB_DATA_WAVES__COUNT1__SHIFT 0x10
-#define SPI_LB_DATA_WAVES__COUNT0_MASK 0x0000FFFFL
-#define SPI_LB_DATA_WAVES__COUNT1_MASK 0xFFFF0000L
-//SPI_LB_DATA_PERCU_WAVE_HSGS
-#define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_HS__SHIFT 0x0
-#define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_GS__SHIFT 0x10
-#define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_HS_MASK 0x0000FFFFL
-#define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_GS_MASK 0xFFFF0000L
-//SPI_LB_DATA_PERCU_WAVE_VSPS
-#define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_VS__SHIFT 0x0
-#define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_PS__SHIFT 0x10
-#define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_VS_MASK 0x0000FFFFL
-#define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_PS_MASK 0xFFFF0000L
-//SPI_LB_DATA_PERCU_WAVE_CS
-#define SPI_LB_DATA_PERCU_WAVE_CS__ACTIVE__SHIFT 0x0
-#define SPI_LB_DATA_PERCU_WAVE_CS__ACTIVE_MASK 0xFFFFL
-//SPI_P0_TRAP_SCREEN_PSBA_LO
-#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0
-#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xFFFFFFFFL
-//SPI_P0_TRAP_SCREEN_PSBA_HI
-#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0
-#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xFFL
-//SPI_P0_TRAP_SCREEN_PSMA_LO
-#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0
-#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xFFFFFFFFL
-//SPI_P0_TRAP_SCREEN_PSMA_HI
-#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0
-#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xFFL
-//SPI_P0_TRAP_SCREEN_GPR_MIN
-#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0
-#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6
-#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x003FL
-#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x03C0L
-//SPI_P1_TRAP_SCREEN_PSBA_LO
-#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0
-#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xFFFFFFFFL
-//SPI_P1_TRAP_SCREEN_PSBA_HI
-#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0
-#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xFFL
-//SPI_P1_TRAP_SCREEN_PSMA_LO
-#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0
-#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xFFFFFFFFL
-//SPI_P1_TRAP_SCREEN_PSMA_HI
-#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0
-#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xFFL
-//SPI_P1_TRAP_SCREEN_GPR_MIN
-#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0
-#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6
-#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x003FL
-#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x03C0L
-
-
-// addressBlock: gc_tpdec
-//TD_CNTL
-#define TD_CNTL__SYNC_PHASE_SH__SHIFT 0x0
-#define TD_CNTL__SYNC_PHASE_VC_SMX__SHIFT 0x4
-#define TD_CNTL__PAD_STALL_EN__SHIFT 0x8
-#define TD_CNTL__EXTEND_LDS_STALL__SHIFT 0x9
-#define TD_CNTL__LDS_STALL_PHASE_ADJUST__SHIFT 0xb
-#define TD_CNTL__PRECISION_COMPATIBILITY__SHIFT 0xf
-#define TD_CNTL__GATHER4_FLOAT_MODE__SHIFT 0x10
-#define TD_CNTL__LD_FLOAT_MODE__SHIFT 0x12
-#define TD_CNTL__GATHER4_DX9_MODE__SHIFT 0x13
-#define TD_CNTL__DISABLE_POWER_THROTTLE__SHIFT 0x14
-#define TD_CNTL__ENABLE_ROUND_TO_ZERO__SHIFT 0x15
-#define TD_CNTL__DISABLE_2BIT_SIGNED_FORMAT__SHIFT 0x17
-#define TD_CNTL__DISABLE_MM_QNAN_COMPARE_RESULT__SHIFT 0x18
-#define TD_CNTL__SYNC_PHASE_SH_MASK 0x00000003L
-#define TD_CNTL__SYNC_PHASE_VC_SMX_MASK 0x00000030L
-#define TD_CNTL__PAD_STALL_EN_MASK 0x00000100L
-#define TD_CNTL__EXTEND_LDS_STALL_MASK 0x00000600L
-#define TD_CNTL__LDS_STALL_PHASE_ADJUST_MASK 0x00001800L
-#define TD_CNTL__PRECISION_COMPATIBILITY_MASK 0x00008000L
-#define TD_CNTL__GATHER4_FLOAT_MODE_MASK 0x00010000L
-#define TD_CNTL__LD_FLOAT_MODE_MASK 0x00040000L
-#define TD_CNTL__GATHER4_DX9_MODE_MASK 0x00080000L
-#define TD_CNTL__DISABLE_POWER_THROTTLE_MASK 0x00100000L
-#define TD_CNTL__ENABLE_ROUND_TO_ZERO_MASK 0x00200000L
-#define TD_CNTL__DISABLE_2BIT_SIGNED_FORMAT_MASK 0x00800000L
-#define TD_CNTL__DISABLE_MM_QNAN_COMPARE_RESULT_MASK 0x01000000L
-//TD_STATUS
-#define TD_STATUS__BUSY__SHIFT 0x1f
-#define TD_STATUS__BUSY_MASK 0x80000000L
-//TD_DSM_CNTL
-#define TD_DSM_CNTL__TD_SS_FIFO_LO_DSM_IRRITATOR_DATA__SHIFT 0x0
-#define TD_DSM_CNTL__TD_SS_FIFO_LO_ENABLE_SINGLE_WRITE__SHIFT 0x2
-#define TD_DSM_CNTL__TD_SS_FIFO_HI_DSM_IRRITATOR_DATA__SHIFT 0x3
-#define TD_DSM_CNTL__TD_SS_FIFO_HI_ENABLE_SINGLE_WRITE__SHIFT 0x5
-#define TD_DSM_CNTL__TD_CS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x6
-#define TD_DSM_CNTL__TD_CS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8
-#define TD_DSM_CNTL__TD_SS_FIFO_LO_DSM_IRRITATOR_DATA_MASK 0x00000003L
-#define TD_DSM_CNTL__TD_SS_FIFO_LO_ENABLE_SINGLE_WRITE_MASK 0x00000004L
-#define TD_DSM_CNTL__TD_SS_FIFO_HI_DSM_IRRITATOR_DATA_MASK 0x00000018L
-#define TD_DSM_CNTL__TD_SS_FIFO_HI_ENABLE_SINGLE_WRITE_MASK 0x00000020L
-#define TD_DSM_CNTL__TD_CS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L
-#define TD_DSM_CNTL__TD_CS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L
-//TD_DSM_CNTL2
-#define TD_DSM_CNTL2__TD_SS_FIFO_LO_ENABLE_ERROR_INJECT__SHIFT 0x0
-#define TD_DSM_CNTL2__TD_SS_FIFO_LO_SELECT_INJECT_DELAY__SHIFT 0x2
-#define TD_DSM_CNTL2__TD_SS_FIFO_HI_ENABLE_ERROR_INJECT__SHIFT 0x3
-#define TD_DSM_CNTL2__TD_SS_FIFO_HI_SELECT_INJECT_DELAY__SHIFT 0x5
-#define TD_DSM_CNTL2__TD_CS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x6
-#define TD_DSM_CNTL2__TD_CS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x8
-#define TD_DSM_CNTL2__TD_INJECT_DELAY__SHIFT 0x1a
-#define TD_DSM_CNTL2__TD_SS_FIFO_LO_ENABLE_ERROR_INJECT_MASK 0x00000003L
-#define TD_DSM_CNTL2__TD_SS_FIFO_LO_SELECT_INJECT_DELAY_MASK 0x00000004L
-#define TD_DSM_CNTL2__TD_SS_FIFO_HI_ENABLE_ERROR_INJECT_MASK 0x00000018L
-#define TD_DSM_CNTL2__TD_SS_FIFO_HI_SELECT_INJECT_DELAY_MASK 0x00000020L
-#define TD_DSM_CNTL2__TD_CS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L
-#define TD_DSM_CNTL2__TD_CS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000100L
-#define TD_DSM_CNTL2__TD_INJECT_DELAY_MASK 0xFC000000L
-//TD_SCRATCH
-#define TD_SCRATCH__SCRATCH__SHIFT 0x0
-#define TD_SCRATCH__SCRATCH_MASK 0xFFFFFFFFL
-//TA_CNTL
-#define TA_CNTL__FX_XNACK_CREDIT__SHIFT 0x0
-#define TA_CNTL__SQ_XNACK_CREDIT__SHIFT 0x9
-#define TA_CNTL__TC_DATA_CREDIT__SHIFT 0xd
-#define TA_CNTL__ALIGNER_CREDIT__SHIFT 0x10
-#define TA_CNTL__TD_FIFO_CREDIT__SHIFT 0x16
-#define TA_CNTL__FX_XNACK_CREDIT_MASK 0x0000007FL
-#define TA_CNTL__SQ_XNACK_CREDIT_MASK 0x00001E00L
-#define TA_CNTL__TC_DATA_CREDIT_MASK 0x0000E000L
-#define TA_CNTL__ALIGNER_CREDIT_MASK 0x001F0000L
-#define TA_CNTL__TD_FIFO_CREDIT_MASK 0xFFC00000L
-//TA_CNTL_AUX
-#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N__SHIFT 0x0
-#define TA_CNTL_AUX__RESERVED__SHIFT 0x1
-#define TA_CNTL_AUX__TFAULT_EN_OVERRIDE__SHIFT 0x5
-#define TA_CNTL_AUX__GATHERH_DST_SEL__SHIFT 0x6
-#define TA_CNTL_AUX__DISABLE_GATHER4_BC_SWIZZLE__SHIFT 0x7
-#define TA_CNTL_AUX__NONIMG_ANISO_BYPASS__SHIFT 0x9
-#define TA_CNTL_AUX__ANISO_HALF_THRESH__SHIFT 0xa
-#define TA_CNTL_AUX__ANISO_ERROR_FP_VBIAS__SHIFT 0xc
-#define TA_CNTL_AUX__ANISO_STEP_ORDER__SHIFT 0xd
-#define TA_CNTL_AUX__ANISO_STEP__SHIFT 0xe
-#define TA_CNTL_AUX__MINMAG_UNNORM__SHIFT 0xf
-#define TA_CNTL_AUX__ANISO_WEIGHT_MODE__SHIFT 0x10
-#define TA_CNTL_AUX__ANISO_RATIO_LUT__SHIFT 0x11
-#define TA_CNTL_AUX__ANISO_TAP__SHIFT 0x12
-#define TA_CNTL_AUX__ANISO_MIP_ADJ_MODE__SHIFT 0x13
-#define TA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE__SHIFT 0x14
-#define TA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE__SHIFT 0x15
-#define TA_CNTL_AUX__DETERMINISM_MISC_DISABLE__SHIFT 0x16
-#define TA_CNTL_AUX__DETERMINISM_SAMPLE_C_DFMT_DISABLE__SHIFT 0x17
-#define TA_CNTL_AUX__DETERMINISM_SAMPLER_MSAA_DISABLE__SHIFT 0x18
-#define TA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE__SHIFT 0x19
-#define TA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE__SHIFT 0x1a
-#define TA_CNTL_AUX__DISABLE_DWORD_X2_COALESCE__SHIFT 0x1b
-#define TA_CNTL_AUX__CUBEMAP_SLICE_CLAMP__SHIFT 0x1c
-#define TA_CNTL_AUX__TRUNC_SMALL_NEG__SHIFT 0x1d
-#define TA_CNTL_AUX__ARRAY_ROUND_MODE__SHIFT 0x1e
-#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N_MASK 0x00000001L
-#define TA_CNTL_AUX__RESERVED_MASK 0x0000000EL
-#define TA_CNTL_AUX__TFAULT_EN_OVERRIDE_MASK 0x00000020L
-#define TA_CNTL_AUX__GATHERH_DST_SEL_MASK 0x00000040L
-#define TA_CNTL_AUX__DISABLE_GATHER4_BC_SWIZZLE_MASK 0x00000080L
-#define TA_CNTL_AUX__NONIMG_ANISO_BYPASS_MASK 0x00000200L
-#define TA_CNTL_AUX__ANISO_HALF_THRESH_MASK 0x00000C00L
-#define TA_CNTL_AUX__ANISO_ERROR_FP_VBIAS_MASK 0x00001000L
-#define TA_CNTL_AUX__ANISO_STEP_ORDER_MASK 0x00002000L
-#define TA_CNTL_AUX__ANISO_STEP_MASK 0x00004000L
-#define TA_CNTL_AUX__MINMAG_UNNORM_MASK 0x00008000L
-#define TA_CNTL_AUX__ANISO_WEIGHT_MODE_MASK 0x00010000L
-#define TA_CNTL_AUX__ANISO_RATIO_LUT_MASK 0x00020000L
-#define TA_CNTL_AUX__ANISO_TAP_MASK 0x00040000L
-#define TA_CNTL_AUX__ANISO_MIP_ADJ_MODE_MASK 0x00080000L
-#define TA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE_MASK 0x00100000L
-#define TA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE_MASK 0x00200000L
-#define TA_CNTL_AUX__DETERMINISM_MISC_DISABLE_MASK 0x00400000L
-#define TA_CNTL_AUX__DETERMINISM_SAMPLE_C_DFMT_DISABLE_MASK 0x00800000L
-#define TA_CNTL_AUX__DETERMINISM_SAMPLER_MSAA_DISABLE_MASK 0x01000000L
-#define TA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE_MASK 0x02000000L
-#define TA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE_MASK 0x04000000L
-#define TA_CNTL_AUX__DISABLE_DWORD_X2_COALESCE_MASK 0x08000000L
-#define TA_CNTL_AUX__CUBEMAP_SLICE_CLAMP_MASK 0x10000000L
-#define TA_CNTL_AUX__TRUNC_SMALL_NEG_MASK 0x20000000L
-#define TA_CNTL_AUX__ARRAY_ROUND_MODE_MASK 0xC0000000L
-//TA_RESERVED_010C
-#define TA_RESERVED_010C__Unused__SHIFT 0x0
-#define TA_RESERVED_010C__Unused_MASK 0xFFFFFFFFL
-//TA_GRAD_ADJ
-#define TA_GRAD_ADJ__GRAD_ADJ_0__SHIFT 0x0
-#define TA_GRAD_ADJ__GRAD_ADJ_1__SHIFT 0x8
-#define TA_GRAD_ADJ__GRAD_ADJ_2__SHIFT 0x10
-#define TA_GRAD_ADJ__GRAD_ADJ_3__SHIFT 0x18
-#define TA_GRAD_ADJ__GRAD_ADJ_0_MASK 0x000000FFL
-#define TA_GRAD_ADJ__GRAD_ADJ_1_MASK 0x0000FF00L
-#define TA_GRAD_ADJ__GRAD_ADJ_2_MASK 0x00FF0000L
-#define TA_GRAD_ADJ__GRAD_ADJ_3_MASK 0xFF000000L
-//TA_STATUS
-#define TA_STATUS__FG_PFIFO_EMPTYB__SHIFT 0xc
-#define TA_STATUS__FG_LFIFO_EMPTYB__SHIFT 0xd
-#define TA_STATUS__FG_SFIFO_EMPTYB__SHIFT 0xe
-#define TA_STATUS__FL_PFIFO_EMPTYB__SHIFT 0x10
-#define TA_STATUS__FL_LFIFO_EMPTYB__SHIFT 0x11
-#define TA_STATUS__FL_SFIFO_EMPTYB__SHIFT 0x12
-#define TA_STATUS__FA_PFIFO_EMPTYB__SHIFT 0x14
-#define TA_STATUS__FA_LFIFO_EMPTYB__SHIFT 0x15
-#define TA_STATUS__FA_SFIFO_EMPTYB__SHIFT 0x16
-#define TA_STATUS__IN_BUSY__SHIFT 0x18
-#define TA_STATUS__FG_BUSY__SHIFT 0x19
-#define TA_STATUS__LA_BUSY__SHIFT 0x1a
-#define TA_STATUS__FL_BUSY__SHIFT 0x1b
-#define TA_STATUS__TA_BUSY__SHIFT 0x1c
-#define TA_STATUS__FA_BUSY__SHIFT 0x1d
-#define TA_STATUS__AL_BUSY__SHIFT 0x1e
-#define TA_STATUS__BUSY__SHIFT 0x1f
-#define TA_STATUS__FG_PFIFO_EMPTYB_MASK 0x00001000L
-#define TA_STATUS__FG_LFIFO_EMPTYB_MASK 0x00002000L
-#define TA_STATUS__FG_SFIFO_EMPTYB_MASK 0x00004000L
-#define TA_STATUS__FL_PFIFO_EMPTYB_MASK 0x00010000L
-#define TA_STATUS__FL_LFIFO_EMPTYB_MASK 0x00020000L
-#define TA_STATUS__FL_SFIFO_EMPTYB_MASK 0x00040000L
-#define TA_STATUS__FA_PFIFO_EMPTYB_MASK 0x00100000L
-#define TA_STATUS__FA_LFIFO_EMPTYB_MASK 0x00200000L
-#define TA_STATUS__FA_SFIFO_EMPTYB_MASK 0x00400000L
-#define TA_STATUS__IN_BUSY_MASK 0x01000000L
-#define TA_STATUS__FG_BUSY_MASK 0x02000000L
-#define TA_STATUS__LA_BUSY_MASK 0x04000000L
-#define TA_STATUS__FL_BUSY_MASK 0x08000000L
-#define TA_STATUS__TA_BUSY_MASK 0x10000000L
-#define TA_STATUS__FA_BUSY_MASK 0x20000000L
-#define TA_STATUS__AL_BUSY_MASK 0x40000000L
-#define TA_STATUS__BUSY_MASK 0x80000000L
-//TA_SCRATCH
-#define TA_SCRATCH__SCRATCH__SHIFT 0x0
-#define TA_SCRATCH__SCRATCH_MASK 0xFFFFFFFFL
-
-
-// addressBlock: gc_gdsdec
-//GDS_CONFIG
-#define GDS_CONFIG__SH0_GPR_PHASE_SEL__SHIFT 0x1
-#define GDS_CONFIG__SH1_GPR_PHASE_SEL__SHIFT 0x3
-#define GDS_CONFIG__SH2_GPR_PHASE_SEL__SHIFT 0x5
-#define GDS_CONFIG__SH3_GPR_PHASE_SEL__SHIFT 0x7
-#define GDS_CONFIG__SH0_GPR_PHASE_SEL_MASK 0x00000006L
-#define GDS_CONFIG__SH1_GPR_PHASE_SEL_MASK 0x00000018L
-#define GDS_CONFIG__SH2_GPR_PHASE_SEL_MASK 0x00000060L
-#define GDS_CONFIG__SH3_GPR_PHASE_SEL_MASK 0x00000180L
-//GDS_CNTL_STATUS
-#define GDS_CNTL_STATUS__GDS_BUSY__SHIFT 0x0
-#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY__SHIFT 0x1
-#define GDS_CNTL_STATUS__ORD_APP_BUSY__SHIFT 0x2
-#define GDS_CNTL_STATUS__DS_BANK_CONFLICT__SHIFT 0x3
-#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT__SHIFT 0x4
-#define GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT 0x5
-#define GDS_CNTL_STATUS__DS_RD_CLAMP__SHIFT 0x6
-#define GDS_CNTL_STATUS__GRBM_RBUF_BUSY__SHIFT 0x7
-#define GDS_CNTL_STATUS__DS_BUSY__SHIFT 0x8
-#define GDS_CNTL_STATUS__GWS_BUSY__SHIFT 0x9
-#define GDS_CNTL_STATUS__ORD_FIFO_BUSY__SHIFT 0xa
-#define GDS_CNTL_STATUS__CREDIT_BUSY0__SHIFT 0xb
-#define GDS_CNTL_STATUS__CREDIT_BUSY1__SHIFT 0xc
-#define GDS_CNTL_STATUS__CREDIT_BUSY2__SHIFT 0xd
-#define GDS_CNTL_STATUS__CREDIT_BUSY3__SHIFT 0xe
-#define GDS_CNTL_STATUS__GDS_BUSY_MASK 0x00000001L
-#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY_MASK 0x00000002L
-#define GDS_CNTL_STATUS__ORD_APP_BUSY_MASK 0x00000004L
-#define GDS_CNTL_STATUS__DS_BANK_CONFLICT_MASK 0x00000008L
-#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT_MASK 0x00000010L
-#define GDS_CNTL_STATUS__DS_WR_CLAMP_MASK 0x00000020L
-#define GDS_CNTL_STATUS__DS_RD_CLAMP_MASK 0x00000040L
-#define GDS_CNTL_STATUS__GRBM_RBUF_BUSY_MASK 0x00000080L
-#define GDS_CNTL_STATUS__DS_BUSY_MASK 0x00000100L
-#define GDS_CNTL_STATUS__GWS_BUSY_MASK 0x00000200L
-#define GDS_CNTL_STATUS__ORD_FIFO_BUSY_MASK 0x00000400L
-#define GDS_CNTL_STATUS__CREDIT_BUSY0_MASK 0x00000800L
-#define GDS_CNTL_STATUS__CREDIT_BUSY1_MASK 0x00001000L
-#define GDS_CNTL_STATUS__CREDIT_BUSY2_MASK 0x00002000L
-#define GDS_CNTL_STATUS__CREDIT_BUSY3_MASK 0x00004000L
-//GDS_ENHANCE2
-#define GDS_ENHANCE2__MISC__SHIFT 0x0
-#define GDS_ENHANCE2__UNUSED__SHIFT 0x10
-#define GDS_ENHANCE2__MISC_MASK 0x0000FFFFL
-#define GDS_ENHANCE2__UNUSED_MASK 0xFFFF0000L
-//GDS_PROTECTION_FAULT
-#define GDS_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0
-#define GDS_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1
-#define GDS_PROTECTION_FAULT__GRBM__SHIFT 0x2
-#define GDS_PROTECTION_FAULT__SH_ID__SHIFT 0x3
-#define GDS_PROTECTION_FAULT__CU_ID__SHIFT 0x6
-#define GDS_PROTECTION_FAULT__SIMD_ID__SHIFT 0xa
-#define GDS_PROTECTION_FAULT__WAVE_ID__SHIFT 0xc
-#define GDS_PROTECTION_FAULT__ADDRESS__SHIFT 0x10
-#define GDS_PROTECTION_FAULT__WRITE_DIS_MASK 0x00000001L
-#define GDS_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x00000002L
-#define GDS_PROTECTION_FAULT__GRBM_MASK 0x00000004L
-#define GDS_PROTECTION_FAULT__SH_ID_MASK 0x00000038L
-#define GDS_PROTECTION_FAULT__CU_ID_MASK 0x000003C0L
-#define GDS_PROTECTION_FAULT__SIMD_ID_MASK 0x00000C00L
-#define GDS_PROTECTION_FAULT__WAVE_ID_MASK 0x0000F000L
-#define GDS_PROTECTION_FAULT__ADDRESS_MASK 0xFFFF0000L
-//GDS_VM_PROTECTION_FAULT
-#define GDS_VM_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0
-#define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1
-#define GDS_VM_PROTECTION_FAULT__GWS__SHIFT 0x2
-#define GDS_VM_PROTECTION_FAULT__OA__SHIFT 0x3
-#define GDS_VM_PROTECTION_FAULT__GRBM__SHIFT 0x4
-#define GDS_VM_PROTECTION_FAULT__TMZ__SHIFT 0x5
-#define GDS_VM_PROTECTION_FAULT__VMID__SHIFT 0x8
-#define GDS_VM_PROTECTION_FAULT__ADDRESS__SHIFT 0x10
-#define GDS_VM_PROTECTION_FAULT__WRITE_DIS_MASK 0x00000001L
-#define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x00000002L
-#define GDS_VM_PROTECTION_FAULT__GWS_MASK 0x00000004L
-#define GDS_VM_PROTECTION_FAULT__OA_MASK 0x00000008L
-#define GDS_VM_PROTECTION_FAULT__GRBM_MASK 0x00000010L
-#define GDS_VM_PROTECTION_FAULT__TMZ_MASK 0x00000020L
-#define GDS_VM_PROTECTION_FAULT__VMID_MASK 0x00000F00L
-#define GDS_VM_PROTECTION_FAULT__ADDRESS_MASK 0xFFFF0000L
-//GDS_EDC_CNT
-#define GDS_EDC_CNT__GDS_MEM_DED__SHIFT 0x0
-#define GDS_EDC_CNT__GDS_INPUT_QUEUE_SED__SHIFT 0x2
-#define GDS_EDC_CNT__GDS_MEM_SEC__SHIFT 0x4
-#define GDS_EDC_CNT__UNUSED__SHIFT 0x6
-#define GDS_EDC_CNT__GDS_MEM_DED_MASK 0x00000003L
-#define GDS_EDC_CNT__GDS_INPUT_QUEUE_SED_MASK 0x0000000CL
-#define GDS_EDC_CNT__GDS_MEM_SEC_MASK 0x00000030L
-#define GDS_EDC_CNT__UNUSED_MASK 0xFFFFFFC0L
-//GDS_EDC_GRBM_CNT
-#define GDS_EDC_GRBM_CNT__DED__SHIFT 0x0
-#define GDS_EDC_GRBM_CNT__SEC__SHIFT 0x2
-#define GDS_EDC_GRBM_CNT__UNUSED__SHIFT 0x4
-#define GDS_EDC_GRBM_CNT__DED_MASK 0x00000003L
-#define GDS_EDC_GRBM_CNT__SEC_MASK 0x0000000CL
-#define GDS_EDC_GRBM_CNT__UNUSED_MASK 0xFFFFFFF0L
-//GDS_EDC_OA_DED
-#define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED__SHIFT 0x0
-#define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED__SHIFT 0x1
-#define GDS_EDC_OA_DED__ME0_CS_DED__SHIFT 0x2
-#define GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED__SHIFT 0x3
-#define GDS_EDC_OA_DED__ME1_PIPE0_DED__SHIFT 0x4
-#define GDS_EDC_OA_DED__ME1_PIPE1_DED__SHIFT 0x5
-#define GDS_EDC_OA_DED__ME1_PIPE2_DED__SHIFT 0x6
-#define GDS_EDC_OA_DED__ME1_PIPE3_DED__SHIFT 0x7
-#define GDS_EDC_OA_DED__ME2_PIPE0_DED__SHIFT 0x8
-#define GDS_EDC_OA_DED__ME2_PIPE1_DED__SHIFT 0x9
-#define GDS_EDC_OA_DED__ME2_PIPE2_DED__SHIFT 0xa
-#define GDS_EDC_OA_DED__ME2_PIPE3_DED__SHIFT 0xb
-#define GDS_EDC_OA_DED__UNUSED1__SHIFT 0xc
-#define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED_MASK 0x00000001L
-#define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED_MASK 0x00000002L
-#define GDS_EDC_OA_DED__ME0_CS_DED_MASK 0x00000004L
-#define GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED_MASK 0x00000008L
-#define GDS_EDC_OA_DED__ME1_PIPE0_DED_MASK 0x00000010L
-#define GDS_EDC_OA_DED__ME1_PIPE1_DED_MASK 0x00000020L
-#define GDS_EDC_OA_DED__ME1_PIPE2_DED_MASK 0x00000040L
-#define GDS_EDC_OA_DED__ME1_PIPE3_DED_MASK 0x00000080L
-#define GDS_EDC_OA_DED__ME2_PIPE0_DED_MASK 0x00000100L
-#define GDS_EDC_OA_DED__ME2_PIPE1_DED_MASK 0x00000200L
-#define GDS_EDC_OA_DED__ME2_PIPE2_DED_MASK 0x00000400L
-#define GDS_EDC_OA_DED__ME2_PIPE3_DED_MASK 0x00000800L
-#define GDS_EDC_OA_DED__UNUSED1_MASK 0xFFFFF000L
-//GDS_DSM_CNTL
-#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_0__SHIFT 0x0
-#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_1__SHIFT 0x1
-#define GDS_DSM_CNTL__GDS_MEM_ENABLE_SINGLE_WRITE__SHIFT 0x2
-#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0__SHIFT 0x3
-#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1__SHIFT 0x4
-#define GDS_DSM_CNTL__GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE__SHIFT 0x5
-#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0__SHIFT 0x6
-#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1__SHIFT 0x7
-#define GDS_DSM_CNTL__GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x8
-#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0__SHIFT 0x9
-#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1__SHIFT 0xa
-#define GDS_DSM_CNTL__GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xb
-#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0__SHIFT 0xc
-#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1__SHIFT 0xd
-#define GDS_DSM_CNTL__GDS_PIPE_MEM_ENABLE_SINGLE_WRITE__SHIFT 0xe
-#define GDS_DSM_CNTL__UNUSED__SHIFT 0xf
-#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_0_MASK 0x00000001L
-#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_1_MASK 0x00000002L
-#define GDS_DSM_CNTL__GDS_MEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
-#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0_MASK 0x00000008L
-#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1_MASK 0x00000010L
-#define GDS_DSM_CNTL__GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE_MASK 0x00000020L
-#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0_MASK 0x00000040L
-#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1_MASK 0x00000080L
-#define GDS_DSM_CNTL__GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000100L
-#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0_MASK 0x00000200L
-#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1_MASK 0x00000400L
-#define GDS_DSM_CNTL__GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000800L
-#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0_MASK 0x00001000L
-#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1_MASK 0x00002000L
-#define GDS_DSM_CNTL__GDS_PIPE_MEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L
-#define GDS_DSM_CNTL__UNUSED_MASK 0xFFFF8000L
-//GDS_EDC_OA_PHY_CNT
-#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_SEC__SHIFT 0x0
-#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_DED__SHIFT 0x2
-#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_SEC__SHIFT 0x4
-#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_DED__SHIFT 0x6
-#define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_SED__SHIFT 0x8
-#define GDS_EDC_OA_PHY_CNT__UNUSED1__SHIFT 0xa
-#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_SEC_MASK 0x00000003L
-#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_DED_MASK 0x0000000CL
-#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_SEC_MASK 0x00000030L
-#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_DED_MASK 0x000000C0L
-#define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_SED_MASK 0x00000300L
-#define GDS_EDC_OA_PHY_CNT__UNUSED1_MASK 0xFFFFFC00L
-//GDS_EDC_OA_PIPE_CNT
-#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_SEC__SHIFT 0x0
-#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_DED__SHIFT 0x2
-#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_SEC__SHIFT 0x4
-#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_DED__SHIFT 0x6
-#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_SEC__SHIFT 0x8
-#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED__SHIFT 0xa
-#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_SEC__SHIFT 0xc
-#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_DED__SHIFT 0xe
-#define GDS_EDC_OA_PIPE_CNT__UNUSED__SHIFT 0x10
-#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_SEC_MASK 0x00000003L
-#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_DED_MASK 0x0000000CL
-#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_SEC_MASK 0x00000030L
-#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_DED_MASK 0x000000C0L
-#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_SEC_MASK 0x00000300L
-#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED_MASK 0x00000C00L
-#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_SEC_MASK 0x00003000L
-#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_DED_MASK 0x0000C000L
-#define GDS_EDC_OA_PIPE_CNT__UNUSED_MASK 0xFFFF0000L
-//GDS_DSM_CNTL2
-#define GDS_DSM_CNTL2__GDS_MEM_ENABLE_ERROR_INJECT__SHIFT 0x0
-#define GDS_DSM_CNTL2__GDS_MEM_SELECT_INJECT_DELAY__SHIFT 0x2
-#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT__SHIFT 0x3
-#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_SELECT_INJECT_DELAY__SHIFT 0x5
-#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT__SHIFT 0x6
-#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY__SHIFT 0x8
-#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT__SHIFT 0x9
-#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY__SHIFT 0xb
-#define GDS_DSM_CNTL2__GDS_PIPE_MEM_ENABLE_ERROR_INJECT__SHIFT 0xc
-#define GDS_DSM_CNTL2__GDS_PIPE_MEM_SELECT_INJECT_DELAY__SHIFT 0xe
-#define GDS_DSM_CNTL2__UNUSED__SHIFT 0xf
-#define GDS_DSM_CNTL2__GDS_INJECT_DELAY__SHIFT 0x1a
-#define GDS_DSM_CNTL2__GDS_MEM_ENABLE_ERROR_INJECT_MASK 0x00000003L
-#define GDS_DSM_CNTL2__GDS_MEM_SELECT_INJECT_DELAY_MASK 0x00000004L
-#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT_MASK 0x00000018L
-#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_SELECT_INJECT_DELAY_MASK 0x00000020L
-#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT_MASK 0x000000C0L
-#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY_MASK 0x00000100L
-#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L
-#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L
-#define GDS_DSM_CNTL2__GDS_PIPE_MEM_ENABLE_ERROR_INJECT_MASK 0x00003000L
-#define GDS_DSM_CNTL2__GDS_PIPE_MEM_SELECT_INJECT_DELAY_MASK 0x00004000L
-#define GDS_DSM_CNTL2__UNUSED_MASK 0x03FF8000L
-#define GDS_DSM_CNTL2__GDS_INJECT_DELAY_MASK 0xFC000000L
-//GDS_WD_GDS_CSB
-#define GDS_WD_GDS_CSB__COUNTER__SHIFT 0x0
-#define GDS_WD_GDS_CSB__UNUSED__SHIFT 0xd
-#define GDS_WD_GDS_CSB__COUNTER_MASK 0x00001FFFL
-#define GDS_WD_GDS_CSB__UNUSED_MASK 0xFFFFE000L
-
-
-// addressBlock: gc_rbdec
-//DB_DEBUG
-#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE__SHIFT 0x0
-#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE__SHIFT 0x1
-#define DB_DEBUG__FETCH_FULL_Z_TILE__SHIFT 0x2
-#define DB_DEBUG__FETCH_FULL_STENCIL_TILE__SHIFT 0x3
-#define DB_DEBUG__FORCE_Z_MODE__SHIFT 0x4
-#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ__SHIFT 0x6
-#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ__SHIFT 0x7
-#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE__SHIFT 0x8
-#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0__SHIFT 0xa
-#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1__SHIFT 0xc
-#define DB_DEBUG__DEBUG_FAST_Z_DISABLE__SHIFT 0xe
-#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE__SHIFT 0xf
-#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE__SHIFT 0x10
-#define DB_DEBUG__DISABLE_SUMM_SQUADS__SHIFT 0x11
-#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS__SHIFT 0x12
-#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE__SHIFT 0x13
-#define DB_DEBUG__NEVER_FREE_Z_ONLY__SHIFT 0x15
-#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS__SHIFT 0x16
-#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION__SHIFT 0x17
-#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES__SHIFT 0x18
-#define DB_DEBUG__ONE_FREE_IN_FLIGHT__SHIFT 0x1c
-#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT__SHIFT 0x1d
-#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC__SHIFT 0x1e
-#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC__SHIFT 0x1f
-#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE_MASK 0x00000001L
-#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE_MASK 0x00000002L
-#define DB_DEBUG__FETCH_FULL_Z_TILE_MASK 0x00000004L
-#define DB_DEBUG__FETCH_FULL_STENCIL_TILE_MASK 0x00000008L
-#define DB_DEBUG__FORCE_Z_MODE_MASK 0x00000030L
-#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ_MASK 0x00000040L
-#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ_MASK 0x00000080L
-#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE_MASK 0x00000300L
-#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0_MASK 0x00000C00L
-#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1_MASK 0x00003000L
-#define DB_DEBUG__DEBUG_FAST_Z_DISABLE_MASK 0x00004000L
-#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE_MASK 0x00008000L
-#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE_MASK 0x00010000L
-#define DB_DEBUG__DISABLE_SUMM_SQUADS_MASK 0x00020000L
-#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS_MASK 0x00040000L
-#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE_MASK 0x00180000L
-#define DB_DEBUG__NEVER_FREE_Z_ONLY_MASK 0x00200000L
-#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS_MASK 0x00400000L
-#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION_MASK 0x00800000L
-#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES_MASK 0x0F000000L
-#define DB_DEBUG__ONE_FREE_IN_FLIGHT_MASK 0x10000000L
-#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT_MASK 0x20000000L
-#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC_MASK 0x40000000L
-#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC_MASK 0x80000000L
-//DB_DEBUG2
-#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING__SHIFT 0x0
-#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE__SHIFT 0x1
-#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE__SHIFT 0x2
-#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB__SHIFT 0x3
-#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT 0x4
-#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL__SHIFT 0x5
-#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ__SHIFT 0x6
-#define DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL__SHIFT 0x7
-#define DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE__SHIFT 0x8
-#define DB_DEBUG2__CLK_OFF_DELAY__SHIFT 0x9
-#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER__SHIFT 0xe
-#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING__SHIFT 0xf
-#define DB_DEBUG2__RESERVED__SHIFT 0x10
-#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING__SHIFT 0x11
-#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING__SHIFT 0x12
-#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL__SHIFT 0x13
-#def