diff options
| author | Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> | 2018-02-21 15:10:02 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2018-03-05 15:35:20 -0500 |
| commit | 28d4175413efe4ec4e6db1a197ab66d4b89c0a93 (patch) | |
| tree | d4c2ba1914641f678592a5b7caa1b532ce13d1e9 /drivers/gpu/drm/amd/display | |
| parent | 1296423bf23c7a58133970e223b1f47ec6570308 (diff) | |
drm/amd/display: fix dcn1 dppclk when min dispclk patch applies
Applying min dispclk patch would result in incorrect dppclk divider
without this change
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c index f1d8db56f406..8020bc7742c1 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c @@ -998,7 +998,7 @@ bool dcn_validate_bandwidth( dc->debug.min_disp_clk_khz; } - context->bw.dcn.calc_clk.max_dppclk_khz = (int)(v->dppclk * 1000); + context->bw.dcn.calc_clk.max_dppclk_khz = context->bw.dcn.calc_clk.dispclk_khz / v->dispclk_dppclk_ratio; for (i = 0, input_idx = 0; i < pool->pipe_count; i++) { struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; |