drm/amd/display: Remove DCE12 guards

Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

10 files changed, 9 insertions, 49 deletions

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
index f53dc157db97..bd4524ef3a37 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
@@ -585,9 +585,7 @@ static uint32_t dce110_get_pix_clk_dividers(
 			pll_settings, pix_clk_params);
 		break;
 	case DCE_VERSION_11_2:
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 	case DCE_VERSION_12_0:
-#endif
 		dce112_get_pix_clk_dividers_helper(clk_src,
 				pll_settings, pix_clk_params);
 		break;
@@ -871,9 +869,7 @@ static bool dce110_program_pix_clk(
 
 		break;
 	case DCE_VERSION_11_2:
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 	case DCE_VERSION_12_0:
-#endif
 		if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO) {
 			bp_pc_params.flags.SET_GENLOCK_REF_DIV_SRC =
 							pll_settings->use_external_clk;
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
index 9c743e51c091..263f8900e39c 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
@@ -80,7 +80,6 @@ static struct state_dependent_clocks dce112_max_clks_by_state[] = {
 /*ClocksStatePerformance*/
 { .display_clk_khz = 1132000, .pixel_clk_khz = 600000 } };
 
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 static struct state_dependent_clocks dce120_max_clks_by_state[] = {
 /*ClocksStateInvalid - should not be used*/
 { .display_clk_khz = 0, .pixel_clk_khz = 0 },
@@ -92,7 +91,6 @@ static struct state_dependent_clocks dce120_max_clks_by_state[] = {
 { .display_clk_khz = 670000, .pixel_clk_khz = 600000 },
 /*ClocksStatePerformance*/
 { .display_clk_khz = 1133000, .pixel_clk_khz = 600000 } };
-#endif
 
 /* Starting point for each divider range.*/
 enum dce_divider_range_start {
@@ -497,7 +495,6 @@ static void dce_clock_read_ss_info(struct dce_disp_clk *clk_dce)
 	}
 }
 
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 static bool dce_apply_clock_voltage_request(
 	struct display_clock *clk,
 	enum dm_pp_clock_type clocks_type,
@@ -592,7 +589,6 @@ static const struct display_clock_funcs dce120_funcs = {
 	.apply_clock_voltage_request = dce_apply_clock_voltage_request,
 	.set_clock = dce112_set_clock
 };
-#endif
 
 static const struct display_clock_funcs dce112_funcs = {
 	.get_dp_ref_clk_frequency = dce_clocks_get_dp_ref_freq,
@@ -734,7 +730,6 @@ struct display_clock *dce112_disp_clk_create(
 	return &clk_dce->base;
 }
 
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 struct display_clock *dce120_disp_clk_create(
 		struct dc_context *ctx,
 		const struct dce_disp_clk_registers *regs,
@@ -770,7 +765,6 @@ struct display_clock *dce120_disp_clk_create(
 
 	return &clk_dce->base;
 }
-#endif
 
 void dce_disp_clk_destroy(struct display_clock **disp_clk)
 {
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h
index 18787f6d4e2a..2fd00e45395c 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h
@@ -45,13 +45,11 @@
 	CLK_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, mask_sh), \
 	CLK_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh)
 
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 #define CLK_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh) \
 	CLK_SF(DCCG_DFS_DPREFCLK_CNTL, DPREFCLK_SRC_SEL, mask_sh), \
 	CLK_SF(DCCG_DFS_DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, mask_sh), \
 	CLK_SF(DCCG_DFS_MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, mask_sh), \
 	CLK_SF(DCCG_DFS_MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh)
-#endif
 
 #define CLK_REG_FIELD_LIST(type) \
 	type DPREFCLK_SRC_SEL; \
@@ -126,10 +124,8 @@ struct dce_disp_clk {
 	int gpu_pll_ss_divider;
 
 
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 	/* max disp_clk from PPLIB for max validation display clock*/
 	int max_displ_clk_in_khz;
-#endif
 };
 
 
@@ -151,13 +147,11 @@ struct display_clock *dce112_disp_clk_create(
 	const struct dce_disp_clk_shift *clk_shift,
 	const struct dce_disp_clk_mask *clk_mask);
 
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 struct display_clock *dce120_disp_clk_create(
 	struct dc_context *ctx,
 	const struct dce_disp_clk_registers *regs,
 	const struct dce_disp_clk_shift *clk_shift,
 	const struct dce_disp_clk_mask *clk_mask);
-#endif
 
 void dce_disp_clk_destroy(struct display_clock **disp_clk);
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
index ff7984b08095..c66585188ecd 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
@@ -186,13 +186,11 @@ struct dce_hwseq_registers {
 	HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\
 	HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_)
 
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 #define HWSEQ_DCE12_MASK_SH_LIST(mask_sh)\
 	HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE0_DCFE_),\
 	HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND0_BLND_),\
 	HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_),\
 	HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_)
-#endif
 
 #define HWSEQ_REG_FIED_LIST(type) \
 	type DCFE_CLOCK_ENABLE; \
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h
index f6a1006a6472..25ba583dbb8f 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h
@@ -31,12 +31,10 @@
 #define TO_DCE110_LINK_ENC(link_encoder)\
 	container_of(link_encoder, struct dce110_link_encoder, base)
 
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 /* Not found regs in dce120 spec
  * BIOS_SCRATCH_2
  * DP_DPHY_INTERNAL_CTRL
  */
-#endif
 
 #define AUX_REG_LIST(id)\
 	SRI(AUX_CONTROL, DP_AUX, id), \
@@ -86,16 +84,14 @@
 	SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
 	SR(DCI_MEM_PWR_STATUS)
 
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
-	#define LE_DCE120_REG_LIST(id)\
-		LE_COMMON_REG_LIST_BASE(id), \
-		SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
-		SR(DCI_MEM_PWR_STATUS)
-#endif
+#define LE_DCE120_REG_LIST(id)\
+	LE_COMMON_REG_LIST_BASE(id), \
+	SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
+	SR(DCI_MEM_PWR_STATUS)
 
-	#define LE_DCE80_REG_LIST(id)\
-		SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
-		LE_COMMON_REG_LIST_BASE(id)
+#define LE_DCE80_REG_LIST(id)\
+	SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
+	LE_COMMON_REG_LIST_BASE(id)
 
 
 struct dce110_link_enc_aux_registers {
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
index c494f712b5b5..7acd87152811 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
@@ -187,7 +187,7 @@ static void program_nbp_watermark(struct mem_input *mi,
 		REG_UPDATE(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL,
 				NB_PSTATE_CHANGE_WATERMARK, nbp_wm);
 	}
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
+
 	if (REG(DPG_PIPE_LOW_POWER_CONTROL)) {
 		REG_UPDATE(DPG_WATERMARK_MASK_CONTROL,
 				PSTATE_CHANGE_WATERMARK_MASK, wm_select);
@@ -200,7 +200,6 @@ static void program_nbp_watermark(struct mem_input *mi,
 		REG_UPDATE(DPG_PIPE_LOW_POWER_CONTROL,
 				PSTATE_CHANGE_WATERMARK, nbp_wm);
 	}
-#endif
 }
 
 static void program_stutter_watermark(struct mem_input *mi,
@@ -210,12 +209,10 @@ static void program_stutter_watermark(struct mem_input *mi,
 	REG_UPDATE(DPG_WATERMARK_MASK_CONTROL,
 		STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK, wm_select);
 
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 	if (REG(DPG_PIPE_STUTTER_CONTROL2))
 		REG_UPDATE(DPG_PIPE_STUTTER_CONTROL2,
 				STUTTER_EXIT_SELF_REFRESH_WATERMARK, stutter_mark);
 	else
-#endif
 		REG_UPDATE(DPG_PIPE_STUTTER_CONTROL,
 				STUTTER_EXIT_SELF_REFRESH_WATERMARK, stutter_mark);
 }
@@ -254,7 +251,6 @@ void dce_mem_input_program_display_marks(struct mem_input *mi,
 static void program_tiling(struct mem_input *mi,
 	const union dc_tiling_info *info)
 {
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 	if (mi->masks->GRPH_SW_MODE) { /* GFX9 */
 		REG_UPDATE_6(GRPH_CONTROL,
 				GRPH_SW_MODE, info->gfx9.swizzle,
@@ -268,7 +264,7 @@ static void program_tiling(struct mem_input *mi,
 		GRPH_Z, 0);
 		 */
 	}
-#endif
+
 	if (mi->masks->GRPH_ARRAY_MODE) { /* GFX8 */
 		REG_UPDATE_9(GRPH_CONTROL,
 				GRPH_NUM_BANKS, info->gfx8.num_banks,
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
index 9e18c2a34e85..6af533bdf98c 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
@@ -58,14 +58,12 @@
 	MI_DCE11_2_REG_LIST(id),\
 	MI_DCE_PTE_REG_LIST(id)
 
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 #define MI_DCE12_REG_LIST(id)\
 	MI_DCE_BASE_REG_LIST(id),\
 	MI_DCE_PTE_REG_LIST(id),\
 	SRI(GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, DCP, id),\
 	SRI(DPG_PIPE_STUTTER_CONTROL2, DMIF_PG, id),\
 	SRI(DPG_PIPE_LOW_POWER_CONTROL, DMIF_PG, id)
-#endif
 
 struct dce_mem_input_registers {
 	/* DCP */
@@ -172,7 +170,6 @@ struct dce_mem_input_registers {
 	MI_DCE11_2_MASK_SH_LIST(mask_sh),\
 	MI_DCP_PTE_MASK_SH_LIST(mask_sh, )
 
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 #define MI_GFX9_TILE_MASK_SH_LIST(mask_sh, blk)\
 	SFB(blk, GRPH_CONTROL, GRPH_SW_MODE, mask_sh),\
 	SFB(blk, GRPH_CONTROL, GRPH_SE_ENABLE, mask_sh),\
@@ -195,7 +192,6 @@ struct dce_mem_input_registers {
 	MI_DMIF_PG_MASK_SH_LIST(mask_sh, DMIF_PG0_),\
 	MI_DCE12_DMIF_PG_MASK_SH_LIST(mask_sh, DMIF_PG0_),\
 	MI_GFX9_TILE_MASK_SH_LIST(mask_sh, DCP0_)
-#endif
 
 #define MI_REG_FIELD_LIST(type) \
 	type GRPH_ENABLE; \
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h
index 4784ced6fc80..03ce9ba50b64 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h
@@ -107,13 +107,11 @@ enum dce110_opp_reg_type {
 	SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, FMT, id), \
 	SRI(CONTROL, FMT_MEMORY, id)
 
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 #define OPP_DCE_120_REG_LIST(id) \
 	OPP_COMMON_REG_LIST_BASE(id), \
 	SRI(DCFE_MEM_PWR_CTRL, DCFE, id), \
 	SRI(DCFE_MEM_PWR_STATUS, DCFE, id), \
 	SRI(CONTROL, FMT_MEMORY, id)
-#endif
 
 #define OPP_SF(reg_name, field_name, post_fix)\
 	.field_name = reg_name ## __ ## field_name ## post_fix
@@ -205,7 +203,6 @@ enum dce110_opp_reg_type {
 	OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, DCP_LUT_LIGHT_SLEEP_DIS, mask_sh),\
 	OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, REGAMMA_LUT_MEM_PWR_STATE, mask_sh)
 
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 #define OPP_COMMON_MASK_SH_LIST_DCE_120(mask_sh)\
 	OPP_SF(DCFE0_DCFE_MEM_PWR_CTRL, DCP_REGAMMA_MEM_PWR_DIS, mask_sh),\
 	OPP_SF(DCFE0_DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh),\
@@ -267,7 +264,6 @@ enum dce110_opp_reg_type {
 	OPP_SF(FMT0_FMT_CONTROL, FMT_SUBSAMPLING_MODE, mask_sh),\
 	OPP_SF(FMT0_FMT_CONTROL, FMT_SUBSAMPLING_ORDER, mask_sh),\
 	OPP_SF(FMT0_FMT_CONTROL, FMT_CBCR_BIT_REDUCTION_BYPASS, mask_sh)
-#endif
 
 #define OPP_REG_FIELD_LIST(type) \
 	type DCP_REGAMMA_MEM_PWR_DIS; \
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h
index c784c1b961c6..c2f4050fc6dc 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h
@@ -187,7 +187,6 @@
 #define SE_COMMON_MASK_SH_LIST_DCE_COMMON(mask_sh)\
 	SE_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh)
 
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 #define SE_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh)\
 	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_INDEX, mask_sh),\
 	SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB0, mask_sh),\
@@ -267,7 +266,6 @@
 	SE_SF(DIG0_HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE, mask_sh),\
 	SE_SF(DIG0_DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\
 	SE_SF(DIG0_DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh)
-#endif
 
 #define SE_COMMON_MASK_SH_LIST_SOC(mask_sh)\
 	SE_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh)
@@ -294,7 +292,6 @@
 	SE_SF(DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh),\
 	SE_SF(DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, mask_sh)
 
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 #define SE_COMMON_MASK_SH_LIST_DCE120(mask_sh)\
 	SE_COMMON_MASK_SH_LIST_SOC(mask_sh),\
 	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC0_UPDATE, mask_sh),\
@@ -307,7 +304,6 @@
 	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_AVI_ENABLE, mask_sh),\
 	SE_SF(DIG0_AFMT_AVI_INFO3, AFMT_AVI_INFO_VERSION, mask_sh),\
 	SE_SF(DP0_DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, mask_sh)
-#endif
 
 struct dce_stream_encoder_shift {
 	uint8_t AFMT_GENERIC_INDEX;
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h
index aa6bc4fc80c5..da2a02434665 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h
@@ -153,7 +153,6 @@
 	XFM_SF(DCFE_MEM_PWR_STATUS, SCL_COEFF_MEM_PWR_STATE, mask_sh), \
 	XFM_SF(SCL_MODE, SCL_PSCL_EN, mask_sh)
 
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 #define XFM_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh) \
 	XFM_SF(DCP0_OUT_CLAMP_CONTROL_B_CB, OUT_CLAMP_MIN_B_CB, mask_sh), \
 	XFM_SF(DCP0_OUT_CLAMP_CONTROL_B_CB, OUT_CLAMP_MAX_B_CB, mask_sh), \
@@ -219,7 +218,6 @@
 	XFM_SF(DCFE0_DCFE_MEM_PWR_CTRL, SCL_COEFF_MEM_PWR_DIS, mask_sh), \
 	XFM_SF(DCFE0_DCFE_MEM_PWR_STATUS, SCL_COEFF_MEM_PWR_STATE, mask_sh), \
 	XFM_SF(SCL0_SCL_MODE, SCL_PSCL_EN, mask_sh)
-#endif
 
 #define XFM_REG_FIELD_LIST(type) \
 	type OUT_CLAMP_MIN_B_CB; \