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authorAlex Deucher <alexander.deucher@amd.com>2017-06-15 16:24:01 -0400
committerAlex Deucher <alexander.deucher@amd.com>2017-09-26 17:21:35 -0400
commitd4e13b0db124345be93bc2ff39ecb48409da2c9b (patch)
tree7069fa7fb33b075b02df025e2d7e1dcd208926d7 /drivers/gpu/drm/amd/display/dc/dce120
parent4e3133c79dc4b7dc0ff81eb884d6cfe736fc49b1 (diff)
drm/amd/display: decouple per-crtc-plane model
Current design has per-crtc-plane model. As a result, for asic's that support underlay, are unable to expose it to user space for modesetting. To enable this, the drm driver intialisation now runs for number of surfaces instead of stream/crtc. This patch plumbs surface capabilities to drm framework so that it can be effectively used by user space. Tests: (On Chromium OS for Stoney Only) * 'modetest -p' now shows additional plane with YUV capabilities in case of CZ and ST. * 'plane_test' fails with below error: [drm:amdgpu_dm_connector_atomic_set_property [amdgpu]] *ERROR* Unsupported screen depth 0 as ther is no support for YUYV * Checked multimonitor display works fine Signed-off-by: Shirish S <shirish.s@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dce120')
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
index efa58889058b..f677a77ca6e0 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
@@ -1060,6 +1060,8 @@ static bool construct(
if (!dce120_hw_sequencer_create(dc))
goto controller_create_fail;
+ dc->public.caps.max_surfaces = pool->base.pipe_count;
+
bw_calcs_init(&dc->bw_dceip, &dc->bw_vbios, dc->ctx->asic_id);
bw_calcs_data_update_from_pplib(dc);