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authorBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>2017-08-02 16:56:03 -0400
committerAlex Deucher <alexander.deucher@amd.com>2017-09-26 18:16:37 -0400
commit77a4ea53fd89ccf823e77cc31cea808a3589f732 (patch)
treec5622c8866b1be8159f41496644d80b58fc11209 /drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
parent391e20d84104a6b7b9d4a66fec6a7eb0a93f6ef4 (diff)
drm/amd/display: change bw_dceip and bw_vbios into pointers
-Change bw_calcs_dceip into pointer -Change bw_calcs_vbios into pointer This is needed for flattening of core_dc into dc, as without this the diags build fails Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c')
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c24
1 files changed, 12 insertions, 12 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
index d4e962756fbb..562ae2205a90 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
@@ -729,21 +729,21 @@ static void bw_calcs_data_update_from_pplib(struct core_dc *dc)
}
/* convert all the clock fro kHz to fix point mHz TODO: wloop data */
- dc->bw_vbios.high_sclk = bw_frc_to_fixed(
+ dc->bw_vbios->high_sclk = bw_frc_to_fixed(
eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000);
- dc->bw_vbios.mid1_sclk = bw_frc_to_fixed(
+ dc->bw_vbios->mid1_sclk = bw_frc_to_fixed(
eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000);
- dc->bw_vbios.mid2_sclk = bw_frc_to_fixed(
+ dc->bw_vbios->mid2_sclk = bw_frc_to_fixed(
eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000);
- dc->bw_vbios.mid3_sclk = bw_frc_to_fixed(
+ dc->bw_vbios->mid3_sclk = bw_frc_to_fixed(
eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000);
- dc->bw_vbios.mid4_sclk = bw_frc_to_fixed(
+ dc->bw_vbios->mid4_sclk = bw_frc_to_fixed(
eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000);
- dc->bw_vbios.mid5_sclk = bw_frc_to_fixed(
+ dc->bw_vbios->mid5_sclk = bw_frc_to_fixed(
eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000);
- dc->bw_vbios.mid6_sclk = bw_frc_to_fixed(
+ dc->bw_vbios->mid6_sclk = bw_frc_to_fixed(
eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000);
- dc->bw_vbios.low_sclk = bw_frc_to_fixed(
+ dc->bw_vbios->low_sclk = bw_frc_to_fixed(
eng_clks.data[0].clocks_in_khz, 1000);
/*do memory clock*/
@@ -770,12 +770,12 @@ static void bw_calcs_data_update_from_pplib(struct core_dc *dc)
* ALSO always convert UMA clock (from PPLIB) to YCLK (HW formula):
* YCLK = UMACLK*m_memoryTypeMultiplier
*/
- dc->bw_vbios.low_yclk = bw_frc_to_fixed(
+ dc->bw_vbios->low_yclk = bw_frc_to_fixed(
mem_clks.data[0].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, 1000);
- dc->bw_vbios.mid_yclk = bw_frc_to_fixed(
+ dc->bw_vbios->mid_yclk = bw_frc_to_fixed(
mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER,
1000);
- dc->bw_vbios.high_yclk = bw_frc_to_fixed(
+ dc->bw_vbios->high_yclk = bw_frc_to_fixed(
mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER,
1000);
@@ -984,7 +984,7 @@ static bool construct(
dc->public.caps.max_planes = pool->base.pipe_count;
- bw_calcs_init(&dc->bw_dceip, &dc->bw_vbios, dc->ctx->asic_id);
+ bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id);
bw_calcs_data_update_from_pplib(dc);