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authorMikita Lipski <mikita.lipski@amd.com>2018-02-27 16:22:29 -0500
committerAlex Deucher <alexander.deucher@amd.com>2018-03-14 15:08:46 -0500
commitd54ee946032be661b7645f30f7fa6ae10caa9bc3 (patch)
tree425b48e1edc4d60f1ecc36c5db5ae3c243127e31 /drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
parenta4056c2a6344c64bd62234458a314e6aecce226f (diff)
drm/amd/display: Enable backlight support for pre-DCE11 ASICs
Initializing ABM and DMCU modules for dce 80/81/83/100 as in DCE110 Adding constructors and destructors for each module. Adding register list for DMCU in dce80 as some registers are missing in dce80 from the basic list. DMCU is never used, so it would not have any functional impact. Signed-off-by: Mikita Lipski <mikita.lipski@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c')
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c50
1 files changed, 50 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
index 3bdbed80f7f8..3092f76bdb75 100644
--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
@@ -51,6 +51,9 @@
#include "dce/dce_10_0_d.h"
#include "dce/dce_10_0_sh_mask.h"
+#include "dce/dce_dmcu.h"
+#include "dce/dce_abm.h"
+
#ifndef mmMC_HUB_RDREQ_DMIF_LIMIT
#include "gmc/gmc_8_2_d.h"
#include "gmc/gmc_8_2_sh_mask.h"
@@ -320,7 +323,29 @@ static const struct dce110_clk_src_mask cs_mask = {
CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
};
+static const struct dce_dmcu_registers dmcu_regs = {
+ DMCU_DCE110_COMMON_REG_LIST()
+};
+
+static const struct dce_dmcu_shift dmcu_shift = {
+ DMCU_MASK_SH_LIST_DCE110(__SHIFT)
+};
+
+static const struct dce_dmcu_mask dmcu_mask = {
+ DMCU_MASK_SH_LIST_DCE110(_MASK)
+};
+
+static const struct dce_abm_registers abm_regs = {
+ ABM_DCE110_COMMON_REG_LIST()
+};
+
+static const struct dce_abm_shift abm_shift = {
+ ABM_MASK_SH_LIST_DCE110(__SHIFT)
+};
+static const struct dce_abm_mask abm_mask = {
+ ABM_MASK_SH_LIST_DCE110(_MASK)
+};
#define DCFE_MEM_PWR_CTRL_REG_BASE 0x1b03
@@ -622,6 +647,12 @@ static void destruct(struct dce110_resource_pool *pool)
if (pool->base.display_clock != NULL)
dce_disp_clk_destroy(&pool->base.display_clock);
+ if (pool->base.abm != NULL)
+ dce_abm_destroy(&pool->base.abm);
+
+ if (pool->base.dmcu != NULL)
+ dce_dmcu_destroy(&pool->base.dmcu);
+
if (pool->base.irqs != NULL)
dal_irq_service_destroy(&pool->base.irqs);
}
@@ -829,6 +860,25 @@ static bool construct(
goto res_create_fail;
}
+ pool->base.dmcu = dce_dmcu_create(ctx,
+ &dmcu_regs,
+ &dmcu_shift,
+ &dmcu_mask);
+ if (pool->base.dmcu == NULL) {
+ dm_error("DC: failed to create dmcu!\n");
+ BREAK_TO_DEBUGGER();
+ goto res_create_fail;
+ }
+
+ pool->base.abm = dce_abm_create(ctx,
+ &abm_regs,
+ &abm_shift,
+ &abm_mask);
+ if (pool->base.abm == NULL) {
+ dm_error("DC: failed to create abm!\n");
+ BREAK_TO_DEBUGGER();
+ goto res_create_fail;
+ }
/* get static clock information for PPLIB or firmware, save
* max_clock_state