diff options
| author | Sean Paul <seanpaul@chromium.org> | 2017-08-18 10:52:44 -0400 |
|---|---|---|
| committer | Sean Paul <seanpaul@chromium.org> | 2017-08-18 10:52:44 -0400 |
| commit | 0e8841ec7ee5b1ffe416c3be7743985b1896ec00 (patch) | |
| tree | 9e502f1f39c740ff7417e5078cbda6eedac1c572 /arch/mips/pci/pci.c | |
| parent | 36436f4e933b42616c8e9ba4907dccf1329cb318 (diff) | |
| parent | 8824c751eb61ebffb053c291199932845bac88b4 (diff) | |
Merge airlied/drm-next into drm-misc-nextdrm-misc-next-2017-08-18
Archit requested this backmerge to facilitate merging some patches
depending on changes between -rc2 & -rc5
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Diffstat (limited to 'arch/mips/pci/pci.c')
| -rw-r--r-- | arch/mips/pci/pci.c | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c index bd67ac74fe2d..9632436d74d7 100644 --- a/arch/mips/pci/pci.c +++ b/arch/mips/pci/pci.c @@ -28,16 +28,15 @@ EXPORT_SYMBOL(PCIBIOS_MIN_MEM); static int __init pcibios_set_cache_line_size(void) { - struct cpuinfo_mips *c = ¤t_cpu_data; unsigned int lsize; /* * Set PCI cacheline size to that of the highest level in the * cache hierarchy. */ - lsize = c->dcache.linesz; - lsize = c->scache.linesz ? : lsize; - lsize = c->tcache.linesz ? : lsize; + lsize = cpu_dcache_line_size(); + lsize = cpu_scache_line_size() ? : lsize; + lsize = cpu_tcache_line_size() ? : lsize; BUG_ON(!lsize); |