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6 hoursdrm/i915/display: Rename pipe_timings to transcoder_timingsHEADdrm-intel-next-queuedManasi Navare1-11/+11
12 hoursdrm/i915: Sort ICL PCI IDsVille Syrjälä1-8/+8
12 hoursdrm/i915: Sort CNL PCI IDsVille Syrjälä1-9/+9
12 hoursdrm/i915: Sort CFL PCI IDsVille Syrjälä1-2/+2
12 hoursdrm/i915: Sort CML PCI IDsVille Syrjälä1-6/+6
12 hoursdrm/i915: Sort KBL PCI IDsVille Syrjälä1-4/+4
12 hoursdrm/i915: Sort SKL PCI IDsVille Syrjälä1-4/+4
12 hoursdrm/i915: Sort HSW PCI IDsVille Syrjälä1-17/+17
12 hoursdrm/i915: Ocd the HSW PCI ID hex numbersVille Syrjälä1-3/+3
12 hoursdrm/i915: Try to fix the SKL GT3/4 vs. GT3e/4e commentsVille Syrjälä1-6/+6
12 hoursdrm/i915: Add SKL GT1.5 PCI IDsAlexei Podtelezhnikov1-3/+6
12 hoursdrm/i915: Reclassify SKL 0x1923 and 0x1927 as ULTAlexei Podtelezhnikov1-3/+3
12 hoursdrm/i915: Reclassify SKL 0x192a as GT3Alexei Podtelezhnikov1-1/+1
12 hoursdrm/i915: Update Haswell PCI IDsAlexei Podtelezhnikov1-1/+1
12 hoursdrm/i915: Sort the mess around ICP TC hotplugs regsVille Syrjälä1-107/+106
13 hoursdrm/i915: Refactor .hpd_irq_setup() calls a bitVille Syrjälä1-10/+12
13 hoursdrm/i915: Reorder hpd init vs. display resumeVille Syrjälä5-34/+46
13 hoursdrm/i915: s/intel_dp_sink_dpms/intel_dp_set_power/Ville Syrjälä4-17/+17
13 hoursdrm/i915: Move the lspcon resume from .reset() to intel_dp_sink_dpms()Ville Syrjälä1-3/+2
19 hoursdrm/i915: Drop runtime-pm assert from vgpu io accessorsChris Wilson1-1/+26
19 hoursdrm/i915: Force VT'd workarounds when running as a guest OSChris Wilson1-1/+5
29 hoursdrm/i915/display/fbc: Implement WA 22010751166José Roberto de Souza1-0/+7
30 hoursdrm/i915/display: Program DBUF_CTL tracker state serviceJosé Roberto de Souza2-5/+23
5 daysdrm/i915: Inline intel_dp_ycbcr420_config()Ville Syrjälä1-24/+9
5 daysdrm/i915: Nuke lspcon_ycbcr420_config()Ville Syrjälä3-21/+3
5 daysdrm/i915: Nuke lspcon_downsamplingVille Syrjälä3-23/+12
5 daysdrm/i915: Mark initial fb obj as WT on eLLC machines to avoid rcu lockup duri...Ville Syrjälä1-0/+8
5 daysdrm/i915: Apply WAC6entrylatency to kbl/cflVille Syrjälä1-0/+8
5 daysdrm/i915/rkl: Add new cdclk tableMatt Roper1-1/+31
5 daysdrm/i915/dgfx: define llc and snooping behaviourMichel Thierry1-0/+2
5 daysdrm/i915/dg1: Update DMC_DEBUG registerAnshuman Gupta2-2/+8
5 daysdrm/i915/dg1: DG1 does not support DC6Anshuman Gupta1-1/+4
5 daysdrm/i915/dg1: Add initial DG1 workaroundsStuart Summers6-44/+131
5 daysdrm/i915/dg1: Load DMCMatt Atwood1-3/+9
5 daysdrm/i915/dg1: Enable DPLL for DG1Lucas De Marchi2-4/+8
5 daysdrm/i915/dg1: Add and setup DPLLs for DG1Aditya Swarup1-4/+38
5 daysdrm/i915/dg1: Add DPLL macros for DG1Aditya Swarup2-1/+33
5 daysdrm/i915/dg1: Add DG1 power wellsLucas De Marchi2-2/+6
5 daysdrm/i915/cnl: skip PW_DDI_F on certain skusLucas De Marchi2-12/+9
5 daysdrm/i915/display: allow to skip certain power wellsAditya Swarup1-6/+18
7 daysdrm/i915/jsl: Split EHL/JSL platform info and PCI idsTejas Upadhyay16-38/+54
8 daysdrm/i915: Force DPCD backlight mode for BOE 2270 panelAaron Ma1-0/+1
8 daysdrm/i915/dpcd_bl: uncheck PWM_PIN_CAP when detect eDP backlight capabilitiesAaron Ma1-2/+1
8 daysdrm/i915/dp: Tweak initial dpcd backlight.enabled valueSean Paul1-11/+20
9 daysdrm/i915: Switch to LTTPR non-transparent mode link trainingImre Deak5-73/+321
9 daysdrm/i915: Switch to LTTPR transparent mode link trainingImre Deak4-0/+60
9 daysdrm/dp: Add LTTPR helpersImre Deak2-4/+290
9 daysdrm/i915: Factor out a helper to disable the DPCD training patternImre Deak1-16/+17
9 daysdrm/i915: Simplify the link training functionsImre Deak3-30/+79
9 daysdrm/i915: Fix DP link training pattern maskImre Deak4-8/+13