diff options
| author | Hoath, Nicholas <nicholas.hoath@intel.com> | 2015-02-05 10:47:24 +0000 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2015-02-06 10:24:37 +0100 |
| commit | c157e8637b6c032cc474f0ac1039d3371777c804 (patch) | |
| tree | 60cb83fbd044b8ca78a2d39b36a0e8788a74499d | |
| parent | 6ffba6db701dbbb11c871b1937acc460b8ef07ac (diff) | |
drm/i915/gen9: Implement WaForceEnableNonCoherentdrm-intel-testing-2015-02-06-skl
v2: Don't add WaHdcDisableFetchWhenMasked. Add stepping check for
WaForceEnableNonCoherent
Signed-off-by: Nick Hoath <nicholas.hoath@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| -rw-r--r-- | drivers/gpu/drm/i915/intel_ringbuffer.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index e35b341c3cef..573b80f0c153 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -902,6 +902,17 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring) GEN9_ENABLE_YV12_BUGFIX); } + if (INTEL_REVID(dev) <= SKL_REVID_D0) { + /* + *Use Force Non-Coherent whenever executing a 3D context. This + * is a workaround for a possible hang in the unlikely event + * a TLB invalidation occurs during a PSD flush. + */ + /* WaForceEnableNonCoherent:skl */ + WA_SET_BIT_MASKED(HDC_CHICKEN0, + HDC_FORCE_NON_COHERENT); + } + /* Wa4x4STCOptimizationDisable:skl */ WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE); |