diff options
| author | Luo Xionghu <xionghu.luo@intel.com> | 2016-03-01 19:35:07 +0800 |
|---|---|---|
| committer | Yang Rong <rong.r.yang@intel.com> | 2016-11-08 20:38:21 +0800 |
| commit | d6f43f57179bb36909b986e3593be75a66829dce (patch) | |
| tree | b0b62d118117cef71e48940983b4fa1138696e29 | |
| parent | 9c994cc75cb86e06bce428e1eef142cedb07de35 (diff) | |
support generic atomic.
Signed-off-by: Luo Xionghu <xionghu.luo@intel.com>
Reviewed-by: Ruiling Song <ruiling.song@intel.com>
| -rw-r--r-- | backend/src/backend/gen_insn_selection.cpp | 15 |
1 files changed, 13 insertions, 2 deletions
diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp index 14175412..a80a6a88 100644 --- a/backend/src/backend/gen_insn_selection.cpp +++ b/backend/src/backend/gen_insn_selection.cpp @@ -6334,8 +6334,19 @@ extern bool OCL_DEBUGINFO; // first defined by calling BVAR in program.cpp if (addrBytes == 8) addrDW = convertU64ToU32(sel, address); sel.ATOMIC(dst, genAtomicOp, msgPayload, addrDW, src1, src2, GenRegister::immud(0xfe), sel.getBTITemps(AM)); - } - else + } else if (addrSpace == ir::MEM_GENERIC) { + Register localMask = generateLocalMask(sel, address); + sel.push(); + sel.curr.useVirtualFlag(localMask, GEN_PREDICATE_NORMAL); + GenRegister addrDW = address; + if (addrBytes == 8) + addrDW = convertU64ToU32(sel, address); + sel.ATOMIC(dst, genAtomicOp, msgPayload, addrDW, src1, src2, GenRegister::immud(0xfe), sel.getBTITemps(AM)); + + sel.curr.inversePredicate = 1; + untypedAtomicA64Stateless(sel, insn, msgPayload, dst, address, src1, src2, GenRegister::immud(0xff)); + sel.pop(); + } else untypedAtomicA64Stateless(sel, insn, msgPayload, dst, address, src1, src2, GenRegister::immud(0xff)); markAllChildren(dag); |