diff options
| author | Tom St Denis <tom.stdenis@amd.com> | 2017-05-11 11:02:07 -0400 |
|---|---|---|
| committer | Tom St Denis <tom.stdenis@amd.com> | 2017-05-11 13:05:32 -0400 |
| commit | 6acc89e4ec159de470af1ec1b9f53d4e97c562bb (patch) | |
| tree | 9194b99cddef28b06e998ea82365e8e061f10f2a | |
| parent | ab18f531f2b918b1e9e134cd8c6ccc0b40799597 (diff) | |
Introduction of Raven1 APU asic
Dropped nbif61 as well since not needed.
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
35 files changed, 82565 insertions, 5795 deletions
diff --git a/scripts/soc15_parse.sh b/scripts/soc15_parse.sh index 04b7f79..92c616c 100644 --- a/scripts/soc15_parse.sh +++ b/scripts/soc15_parse.sh @@ -80,8 +80,16 @@ parse_bits ${pk}/vega10/SDMA0/sdma0_4_0 src/lib/ip/sdma040 parse_bits ${pk}/vega10/THM/thm_9_0 src/lib/ip/thm90 parse_bits ${pk}/vega10/OSSSYS/osssys_4_0 src/lib/ip/oss40 parse_bits ${pk}/vega10/GC/gc_9_0 src/lib/ip/gfx90 -parse_bits ${pk}/vega10/NBIF/nbif_6_1 src/lib/ip/nbif61 parse_bits ${pk}/vega10/NBIO/nbio_6_1 src/lib/ip/nbio61 parse_bits ${pk}/vega10/HDP/hdp_4_0 src/lib/ip/hdp40 parse_bits ${pk}/vega10/MMHUB/mmhub_1_0 src/lib/ip/mmhub10 parse_bits ${pk}/vega10/MP/mp_9_0 src/lib/ip/mp90 + +parse_bits ${pk}/raven1/VCN/vcn_1_0 src/lib/ip/vcn10 +parse_bits ${pk}/raven1/DCN/dcn_1_0 src/lib/ip/dcn10 +parse_bits ${pk}/raven1/MMHUB/mmhub_9_1 src/lib/ip/mmhub91 +parse_bits ${pk}/raven1/MP/mp_10_0 src/lib/ip/mp100 +parse_bits ${pk}/raven1/NBIO/nbio_7_0 src/lib/ip/nbio70 +parse_bits ${pk}/raven1/SDMA0/sdma0_4_1 src/lib/ip/sdma041 +parse_bits ${pk}/raven1/MP/mp_10_0 src/lib/ip/mp100 +parse_bits ${pk}/raven1/GC/gc_9_1 src/lib/ip/gfx91 diff --git a/src/app/print_config.c b/src/app/print_config.c index e295302..3ad95c0 100644 --- a/src/app/print_config.c +++ b/src/app/print_config.c @@ -92,6 +92,7 @@ static const struct { { "Volcanic Islands", 130 }, { "Carrizo", 135 }, { "Arctic Islands", 141 }, + { "Raven", 142 }, { NULL, 0 }, }; diff --git a/src/lib/asic/CMakeLists.txt b/src/lib/asic/CMakeLists.txt index b4846d7..fe9148e 100644 --- a/src/lib/asic/CMakeLists.txt +++ b/src/lib/asic/CMakeLists.txt @@ -15,6 +15,7 @@ add_library(asic OBJECT polaris10.c polaris11.c polaris12.c + raven1.c stoney.c tahiti.c tonga.c diff --git a/src/lib/asic/raven1.c b/src/lib/asic/raven1.c new file mode 100644 index 0000000..2d8aff9 --- /dev/null +++ b/src/lib/asic/raven1.c @@ -0,0 +1,47 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Tom St Denis <tom.stdenis@amd.com> + * + */ +#include "umr.h" + +static struct umr_ip_offsets_soc15 vega10_offs[] = { +#include "vega10.i" + { NULL }, +}; + +struct umr_asic *umr_create_raven1(struct umr_options *options) +{ + return + umr_create_asic_helper("raven1", FAMILY_RV, + umr_create_gfx91(vega10_offs, options), + umr_create_vcn10(vega10_offs, options), + umr_create_dcn10(vega10_offs, options), + umr_create_nbio70(vega10_offs, options), + umr_create_sdma041(vega10_offs, options), + umr_create_hdp40(vega10_offs, options), + umr_create_oss40(vega10_offs, options), + umr_create_mmhub91(vega10_offs, options), + umr_create_mp100(vega10_offs, options), + NULL); +} + diff --git a/src/lib/asic/vega10.c b/src/lib/asic/vega10.c index e00751a..933d37f 100644 --- a/src/lib/asic/vega10.c +++ b/src/lib/asic/vega10.c @@ -38,7 +38,6 @@ struct umr_asic *umr_create_vega10(struct umr_options *options) umr_create_vce40(vega10_offs, options), umr_create_dce120(vega10_offs, options), umr_create_hdp40(vega10_offs, options), - umr_create_nbif61(vega10_offs, options), umr_create_nbio61(vega10_offs, options), umr_create_oss40(vega10_offs, options), umr_create_sdma040(vega10_offs, options), diff --git a/src/lib/discover.c b/src/lib/discover.c index 5a6d7e4..67285e4 100644 --- a/src/lib/discover.c +++ b/src/lib/discover.c @@ -189,7 +189,7 @@ struct umr_asic *umr_discover_asic(struct umr_options *options) if (use_region == 6) { for (use_region = 0; use_region < 6; use_region++) if ((asic->family < FAMILY_AI && asic->pci.pdevice->regions[use_region].size == (256UL * 1024)) || - (asic->family == FAMILY_AI && asic->pci.pdevice->regions[use_region].size == (512UL * 1024))) + (asic->family >= FAMILY_AI && asic->pci.pdevice->regions[use_region].size == (512UL * 1024))) break; } diff --git a/src/lib/discover_by_did.c b/src/lib/discover_by_did.c index 7ecd7f3..c55b140 100644 --- a/src/lib/discover_by_did.c +++ b/src/lib/discover_by_did.c @@ -50,6 +50,7 @@ static const struct { { 0x131B, &umr_create_kaveri }, { 0x131C, &umr_create_kaveri }, { 0x131D, &umr_create_kaveri }, + { 0x15DD, &umr_create_raven1 }, { 0x6600, &umr_create_oland }, { 0x6601, &umr_create_oland }, { 0x6602, &umr_create_oland }, diff --git a/src/lib/discover_by_name.c b/src/lib/discover_by_name.c index 6f37bed..ffeffcc 100644 --- a/src/lib/discover_by_name.c +++ b/src/lib/discover_by_name.c @@ -47,6 +47,7 @@ static const struct { { "carrizo", &umr_create_carrizo }, { "stoney", &umr_create_stoney }, { "vega10", &umr_create_vega10 }, + { "raven1", &umr_create_raven1 }, }; struct umr_asic *umr_discover_asic_by_name(struct umr_options *options, char *name) diff --git a/src/lib/ip/CMakeLists.txt b/src/lib/ip/CMakeLists.txt index 1307453..a311b14 100644 --- a/src/lib/ip/CMakeLists.txt +++ b/src/lib/ip/CMakeLists.txt @@ -11,12 +11,14 @@ add_library(ip OBJECT dce120.c dce60.c dce80.c + dcn10.c gfx60.c gfx70.c gfx72.c gfx80.c gfx81.c gfx90.c + gfx91.c gmc60.c gmc70.c gmc71.c @@ -24,14 +26,17 @@ add_library(ip OBJECT gmc82.c hdp40.c mmhub10.c + mmhub91.c mp90.c - nbif61.c + mp100.c nbio61.c + nbio70.c oss10.c oss20.c oss30.c oss40.c sdma040.c + sdma041.c sdma140.c smu60.c smu700.c @@ -51,4 +56,5 @@ add_library(ip OBJECT vce2.c vce3.c vce40.c + vcn10.c ) diff --git a/src/lib/ip/dcn10.c b/src/lib/ip/dcn10.c new file mode 100644 index 0000000..a2223a8 --- /dev/null +++ b/src/lib/ip/dcn10.c @@ -0,0 +1,55 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Tom St Denis <tom.stdenis@amd.com> + * + */ +#include "umr.h" + +#include "dcn10_bits.i" + +static const struct umr_reg_soc15 dcn10_registers[] = { +#include "dcn10_regs.i" +}; + +struct umr_ip_block *umr_create_dcn10(struct umr_ip_offsets_soc15 *soc15_offsets, struct umr_options *options) +{ + struct umr_ip_block *ip; + + ip = calloc(1, sizeof *ip); + if (!ip) + return NULL; + + ip->ipname = "dcn10"; + ip->no_regs = sizeof(dcn10_registers)/sizeof(dcn10_registers[0]); + ip->regs = calloc(ip->no_regs, sizeof(ip->regs[0])); + if (!ip->regs) { + free(ip); + return NULL; + } + + if (umr_transfer_soc15_to_reg(options, soc15_offsets, "DCN", dcn10_registers, ip)) { + free(ip); + return NULL; + } + + return ip; +} diff --git a/src/lib/ip/dcn10_bits.i b/src/lib/ip/dcn10_bits.i new file mode 100644 index 0000000..3df6171 --- /dev/null +++ b/src/lib/ip/dcn10_bits.i @@ -0,0 +1,36714 @@ +static struct umr_bitfield mmVGA_MEM_WRITE_PAGE_ADDR[] = { + { "VGA_MEM_WRITE_PAGE0_ADDR", 0, 9, &umr_bitfield_default }, + { "VGA_MEM_WRITE_PAGE1_ADDR", 16, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGA_MEM_READ_PAGE_ADDR[] = { + { "VGA_MEM_READ_PAGE0_ADDR", 0, 9, &umr_bitfield_default }, + { "VGA_MEM_READ_PAGE1_ADDR", 16, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCRTC8_IDX[] = { + { "VCRTC_IDX", 0, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCRTC8_DATA[] = { + { "VCRTC_DATA", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGENFC_WT[] = { + { "VSYNC_SEL_W", 3, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGENS1[] = { + { "NO_DISPLAY", 0, 0, &umr_bitfield_default }, + { "VGA_VSTATUS", 3, 3, &umr_bitfield_default }, + { "PIXEL_READ_BACK", 4, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield mmATTRDW[] = { + { "ATTR_DATA", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmATTRX[] = { + { "ATTR_IDX", 0, 4, &umr_bitfield_default }, + { "ATTR_PAL_RW_ENB", 5, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield mmATTRDR[] = { + { "ATTR_DATA", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGENMO_WT[] = { + { "GENMO_MONO_ADDRESS_B", 0, 0, &umr_bitfield_default }, + { "VGA_RAM_EN", 1, 1, &umr_bitfield_default }, + { "VGA_CKSEL", 2, 3, &umr_bitfield_default }, + { "ODD_EVEN_MD_PGSEL", 5, 5, &umr_bitfield_default }, + { "VGA_HSYNC_POL", 6, 6, &umr_bitfield_default }, + { "VGA_VSYNC_POL", 7, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGENS0[] = { + { "SENSE_SWITCH", 4, 4, &umr_bitfield_default }, + { "CRT_INTR", 7, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGENENB[] = { + { "BLK_IO_BASE", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSEQ8_IDX[] = { + { "SEQ_IDX", 0, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSEQ8_DATA[] = { + { "SEQ_DATA", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAC_MASK[] = { + { "DAC_MASK", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAC_R_INDEX[] = { + { "DAC_R_INDEX", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAC_W_INDEX[] = { + { "DAC_W_INDEX", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAC_DATA[] = { + { "DAC_DATA", 0, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGENFC_RD[] = { + { "VSYNC_SEL_R", 3, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGENMO_RD[] = { + { "GENMO_MONO_ADDRESS_B", 0, 0, &umr_bitfield_default }, + { "VGA_RAM_EN", 1, 1, &umr_bitfield_default }, + { "VGA_CKSEL", 2, 3, &umr_bitfield_default }, + { "ODD_EVEN_MD_PGSEL", 5, 5, &umr_bitfield_default }, + { "VGA_HSYNC_POL", 6, 6, &umr_bitfield_default }, + { "VGA_VSYNC_POL", 7, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRPH8_IDX[] = { + { "GRPH_IDX", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRPH8_DATA[] = { + { "GRPH_DATA", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCRTC8_IDX_1[] = { + { "VCRTC_IDX", 0, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCRTC8_DATA_1[] = { + { "VCRTC_DATA", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGENFC_WT_1[] = { + { "VSYNC_SEL_W", 3, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGENS1_1[] = { + { "NO_DISPLAY", 0, 0, &umr_bitfield_default }, + { "VGA_VSTATUS", 3, 3, &umr_bitfield_default }, + { "PIXEL_READ_BACK", 4, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCORB_WRITE_POINTER[] = { + { "CORB_WRITE_POINTER", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCORB_READ_POINTER[] = { + { "CORB_READ_POINTER", 0, 7, &umr_bitfield_default }, + { "CORB_READ_POINTER_RESET", 15, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCORB_CONTROL[] = { + { "CORB_MEMORY_ERROR_INTERRUPT_ENABLE", 0, 0, &umr_bitfield_default }, + { "ENABLE_CORB_DMA_ENGINE", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCORB_STATUS[] = { + { "CORB_MEMORY_ERROR_INDICATION", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCORB_SIZE[] = { + { "CORB_SIZE", 0, 1, &umr_bitfield_default }, + { "CORB_SIZE_CAPABILITY", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRIRB_LOWER_BASE_ADDRESS[] = { + { "RIRB_LOWER_BASE_UNIMPLEMENTED_BITS", 0, 6, &umr_bitfield_default }, + { "RIRB_LOWER_BASE_ADDRESS", 7, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRIRB_UPPER_BASE_ADDRESS[] = { + { "RIRB_UPPER_BASE_ADDRESS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRIRB_WRITE_POINTER[] = { + { "RIRB_WRITE_POINTER", 0, 7, &umr_bitfield_default }, + { "RIRB_WRITE_POINTER_RESET", 15, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRESPONSE_INTERRUPT_COUNT[] = { + { "N_RESPONSE_INTERRUPT_COUNT", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRIRB_CONTROL[] = { + { "RESPONSE_INTERRUPT_CONTROL", 0, 0, &umr_bitfield_default }, + { "RIRB_DMA_ENABLE", 1, 1, &umr_bitfield_default }, + { "RESPONSE_OVERRUN_INTERRUPT_CONTROL", 2, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRIRB_STATUS[] = { + { "RESPONSE_INTERRUPT", 0, 0, &umr_bitfield_default }, + { "RESPONSE_OVERRUN_INTERRUPT_STATUS", 2, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRIRB_SIZE[] = { + { "RIRB_SIZE", 0, 1, &umr_bitfield_default }, + { "RIRB_SIZE_CAPABILITY", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE[] = { + { "IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD", 0, 27, &umr_bitfield_default }, + { "IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA[] = { + { "IMMEDIATE_COMMAND_WRITE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX[] = { + { "IMMEDIATE_COMMAND_WRITE", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIMMEDIATE_RESPONSE_INPUT_INTERFACE[] = { + { "IMMEDIATE_RESPONSE_READ", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIMMEDIATE_COMMAND_STATUS[] = { + { "IMMEDIATE_COMMAND_BUSY", 0, 0, &umr_bitfield_default }, + { "IMMEDIATE_RESULT_VALID", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDMA_POSITION_LOWER_BASE_ADDRESS[] = { + { "DMA_POSITION_BUFFER_ENABLE", 0, 0, &umr_bitfield_default }, + { "DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS", 1, 6, &umr_bitfield_default }, + { "DMA_POSITION_LOWER_BASE_ADDRESS", 7, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDMA_POSITION_UPPER_BASE_ADDRESS[] = { + { "DMA_POSITION_UPPER_BASE_ADDRESS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWALL_CLOCK_COUNTER_ALIAS[] = { + { "WALL_CLOCK_COUNTER_ALIAS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA[] = { + { "IMMEDIATE_COMMAND_WRITE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX[] = { + { "IMMEDIATE_COMMAND_WRITE", 0, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA[] = { + { "IMMEDIATE_COMMAND_WRITE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX[] = { + { "IMMEDIATE_COMMAND_WRITE", 0, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA[] = { + { "IMMEDIATE_COMMAND_WRITE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX[] = { + { "IMMEDIATE_COMMAND_WRITE", 0, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS[] = { + { "STREAM_RESET", 0, 0, &umr_bitfield_default }, + { "STREAM_RUN", 1, 1, &umr_bitfield_default }, + { "INTERRUPT_ON_COMPLETION_ENABLE", 2, 2, &umr_bitfield_default }, + { "FIFO_ERROR_INTERRUPT_ENABLE", 3, 3, &umr_bitfield_default }, + { "DESCRIPTOR_ERROR_INTERRUPT_ENABLE", 4, 4, &umr_bitfield_default }, + { "STRIPE_CONTROL", 16, 17, &umr_bitfield_default }, + { "TRAFFIC_PRIORITY", 18, 18, &umr_bitfield_default }, + { "STREAM_NUMBER", 20, 23, &umr_bitfield_default }, + { "BUFFER_COMPLETION_INTERRUPT_STATUS", 26, 26, &umr_bitfield_default }, + { "FIFO_ERROR", 27, 27, &umr_bitfield_default }, + { "DESCRIPTOR_ERROR", 28, 28, &umr_bitfield_default }, + { "FIFO_READY", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER[] = { + { "LINK_POSITION_IN_BUFFER", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH[] = { + { "CYCLIC_BUFFER_LENGTH", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX[] = { + { "LAST_VALID_INDEX", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE[] = { + { "FIFO_SIZE", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT[] = { + { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default }, + { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default }, + { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default }, + { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default }, + { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS[] = { + { "BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS", 0, 6, &umr_bitfield_default }, + { "BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS", 7, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS[] = { + { "BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS[] = { + { "LINK_POSITION_IN_BUFFER_ALIAS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS[] = { + { "STREAM_RESET", 0, 0, &umr_bitfield_default }, + { "STREAM_RUN", 1, 1, &umr_bitfield_default }, + { "INTERRUPT_ON_COMPLETION_ENABLE", 2, 2, &umr_bitfield_default }, + { "FIFO_ERROR_INTERRUPT_ENABLE", 3, 3, &umr_bitfield_default }, + { "DESCRIPTOR_ERROR_INTERRUPT_ENABLE", 4, 4, &umr_bitfield_default }, + { "STRIPE_CONTROL", 16, 17, &umr_bitfield_default }, + { "TRAFFIC_PRIORITY", 18, 18, &umr_bitfield_default }, + { "STREAM_NUMBER", 20, 23, &umr_bitfield_default }, + { "BUFFER_COMPLETION_INTERRUPT_STATUS", 26, 26, &umr_bitfield_default }, + { "FIFO_ERROR", 27, 27, &umr_bitfield_default }, + { "DESCRIPTOR_ERROR", 28, 28, &umr_bitfield_default }, + { "FIFO_READY", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER[] = { + { "LINK_POSITION_IN_BUFFER", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH[] = { + { "CYCLIC_BUFFER_LENGTH", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX[] = { + { "LAST_VALID_INDEX", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE[] = { + { "FIFO_SIZE", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT[] = { + { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default }, + { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default }, + { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default }, + { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default }, + { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS[] = { + { "BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS", 0, 6, &umr_bitfield_default }, + { "BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS", 7, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS[] = { + { "BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS[] = { + { "LINK_POSITION_IN_BUFFER_ALIAS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS[] = { + { "STREAM_RESET", 0, 0, &umr_bitfield_default }, + { "STREAM_RUN", 1, 1, &umr_bitfield_default }, + { "INTERRUPT_ON_COMPLETION_ENABLE", 2, 2, &umr_bitfield_default }, + { "FIFO_ERROR_INTERRUPT_ENABLE", 3, 3, &umr_bitfield_default }, + { "DESCRIPTOR_ERROR_INTERRUPT_ENABLE", 4, 4, &umr_bitfield_default }, + { "STRIPE_CONTROL", 16, 17, &umr_bitfield_default }, + { "TRAFFIC_PRIORITY", 18, 18, &umr_bitfield_default }, + { "STREAM_NUMBER", 20, 23, &umr_bitfield_default }, + { "BUFFER_COMPLETION_INTERRUPT_STATUS", 26, 26, &umr_bitfield_default }, + { "FIFO_ERROR", 27, 27, &umr_bitfield_default }, + { "DESCRIPTOR_ERROR", 28, 28, &umr_bitfield_default }, + { "FIFO_READY", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER[] = { + { "LINK_POSITION_IN_BUFFER", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH[] = { + { "CYCLIC_BUFFER_LENGTH", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX[] = { + { "LAST_VALID_INDEX", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE[] = { + { "FIFO_SIZE", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT[] = { + { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default }, + { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default }, + { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default }, + { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default }, + { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS[] = { + { "BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS", 0, 6, &umr_bitfield_default }, + { "BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS", 7, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS[] = { + { "BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS[] = { + { "LINK_POSITION_IN_BUFFER_ALIAS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS[] = { + { "STREAM_RESET", 0, 0, &umr_bitfield_default }, + { "STREAM_RUN", 1, 1, &umr_bitfield_default }, + { "INTERRUPT_ON_COMPLETION_ENABLE", 2, 2, &umr_bitfield_default }, + { "FIFO_ERROR_INTERRUPT_ENABLE", 3, 3, &umr_bitfield_default }, + { "DESCRIPTOR_ERROR_INTERRUPT_ENABLE", 4, 4, &umr_bitfield_default }, + { "STRIPE_CONTROL", 16, 17, &umr_bitfield_default }, + { "TRAFFIC_PRIORITY", 18, 18, &umr_bitfield_default }, + { "STREAM_NUMBER", 20, 23, &umr_bitfield_default }, + { "BUFFER_COMPLETION_INTERRUPT_STATUS", 26, 26, &umr_bitfield_default }, + { "FIFO_ERROR", 27, 27, &umr_bitfield_default }, + { "DESCRIPTOR_ERROR", 28, 28, &umr_bitfield_default }, + { "FIFO_READY", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER[] = { + { "LINK_POSITION_IN_BUFFER", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH[] = { + { "CYCLIC_BUFFER_LENGTH", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX[] = { + { "LAST_VALID_INDEX", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE[] = { + { "FIFO_SIZE", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT[] = { + { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default }, + { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default }, + { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default }, + { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default }, + { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS[] = { + { "BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS", 0, 6, &umr_bitfield_default }, + { "BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS", 7, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS[] = { + { "BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS[] = { + { "LINK_POSITION_IN_BUFFER_ALIAS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS[] = { + { "STREAM_RESET", 0, 0, &umr_bitfield_default }, + { "STREAM_RUN", 1, 1, &umr_bitfield_default }, + { "INTERRUPT_ON_COMPLETION_ENABLE", 2, 2, &umr_bitfield_default }, + { "FIFO_ERROR_INTERRUPT_ENABLE", 3, 3, &umr_bitfield_default }, + { "DESCRIPTOR_ERROR_INTERRUPT_ENABLE", 4, 4, &umr_bitfield_default }, + { "STRIPE_CONTROL", 16, 17, &umr_bitfield_default }, + { "TRAFFIC_PRIORITY", 18, 18, &umr_bitfield_default }, + { "STREAM_NUMBER", 20, 23, &umr_bitfield_default }, + { "BUFFER_COMPLETION_INTERRUPT_STATUS", 26, 26, &umr_bitfield_default }, + { "FIFO_ERROR", 27, 27, &umr_bitfield_default }, + { "DESCRIPTOR_ERROR", 28, 28, &umr_bitfield_default }, + { "FIFO_READY", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER[] = { + { "LINK_POSITION_IN_BUFFER", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH[] = { + { "CYCLIC_BUFFER_LENGTH", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX[] = { + { "LAST_VALID_INDEX", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE[] = { + { "FIFO_SIZE", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT[] = { + { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default }, + { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default }, + { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default }, + { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default }, + { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS[] = { + { "BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS", 0, 6, &umr_bitfield_default }, + { "BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS", 7, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS[] = { + { "BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS[] = { + { "LINK_POSITION_IN_BUFFER_ALIAS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS[] = { + { "STREAM_RESET", 0, 0, &umr_bitfield_default }, + { "STREAM_RUN", 1, 1, &umr_bitfield_default }, + { "INTERRUPT_ON_COMPLETION_ENABLE", 2, 2, &umr_bitfield_default }, + { "FIFO_ERROR_INTERRUPT_ENABLE", 3, 3, &umr_bitfield_default }, + { "DESCRIPTOR_ERROR_INTERRUPT_ENABLE", 4, 4, &umr_bitfield_default }, + { "STRIPE_CONTROL", 16, 17, &umr_bitfield_default }, + { "TRAFFIC_PRIORITY", 18, 18, &umr_bitfield_default }, + { "STREAM_NUMBER", 20, 23, &umr_bitfield_default }, + { "BUFFER_COMPLETION_INTERRUPT_STATUS", 26, 26, &umr_bitfield_default }, + { "FIFO_ERROR", 27, 27, &umr_bitfield_default }, + { "DESCRIPTOR_ERROR", 28, 28, &umr_bitfield_default }, + { "FIFO_READY", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER[] = { + { "LINK_POSITION_IN_BUFFER", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH[] = { + { "CYCLIC_BUFFER_LENGTH", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX[] = { + { "LAST_VALID_INDEX", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE[] = { + { "FIFO_SIZE", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT[] = { + { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default }, + { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default }, + { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default }, + { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default }, + { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS[] = { + { "BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS", 0, 6, &umr_bitfield_default }, + { "BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS", 7, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS[] = { + { "BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS[] = { + { "LINK_POSITION_IN_BUFFER_ALIAS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS[] = { + { "STREAM_RESET", 0, 0, &umr_bitfield_default }, + { "STREAM_RUN", 1, 1, &umr_bitfield_default }, + { "INTERRUPT_ON_COMPLETION_ENABLE", 2, 2, &umr_bitfield_default }, + { "FIFO_ERROR_INTERRUPT_ENABLE", 3, 3, &umr_bitfield_default }, + { "DESCRIPTOR_ERROR_INTERRUPT_ENABLE", 4, 4, &umr_bitfield_default }, + { "STRIPE_CONTROL", 16, 17, &umr_bitfield_default }, + { "TRAFFIC_PRIORITY", 18, 18, &umr_bitfield_default }, + { "STREAM_NUMBER", 20, 23, &umr_bitfield_default }, + { "BUFFER_COMPLETION_INTERRUPT_STATUS", 26, 26, &umr_bitfield_default }, + { "FIFO_ERROR", 27, 27, &umr_bitfield_default }, + { "DESCRIPTOR_ERROR", 28, 28, &umr_bitfield_default }, + { "FIFO_READY", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER[] = { + { "LINK_POSITION_IN_BUFFER", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH[] = { + { "CYCLIC_BUFFER_LENGTH", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX[] = { + { "LAST_VALID_INDEX", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE[] = { + { "FIFO_SIZE", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT[] = { + { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default }, + { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default }, + { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default }, + { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default }, + { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS[] = { + { "BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS", 0, 6, &umr_bitfield_default }, + { "BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS", 7, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS[] = { + { "BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS[] = { + { "LINK_POSITION_IN_BUFFER_ALIAS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS[] = { + { "STREAM_RESET", 0, 0, &umr_bitfield_default }, + { "STREAM_RUN", 1, 1, &umr_bitfield_default }, + { "INTERRUPT_ON_COMPLETION_ENABLE", 2, 2, &umr_bitfield_default }, + { "FIFO_ERROR_INTERRUPT_ENABLE", 3, 3, &umr_bitfield_default }, + { "DESCRIPTOR_ERROR_INTERRUPT_ENABLE", 4, 4, &umr_bitfield_default }, + { "STRIPE_CONTROL", 16, 17, &umr_bitfield_default }, + { "TRAFFIC_PRIORITY", 18, 18, &umr_bitfield_default }, + { "STREAM_NUMBER", 20, 23, &umr_bitfield_default }, + { "BUFFER_COMPLETION_INTERRUPT_STATUS", 26, 26, &umr_bitfield_default }, + { "FIFO_ERROR", 27, 27, &umr_bitfield_default }, + { "DESCRIPTOR_ERROR", 28, 28, &umr_bitfield_default }, + { "FIFO_READY", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER[] = { + { "LINK_POSITION_IN_BUFFER", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH[] = { + { "CYCLIC_BUFFER_LENGTH", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX[] = { + { "LAST_VALID_INDEX", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE[] = { + { "FIFO_SIZE", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT[] = { + { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default }, + { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default }, + { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default }, + { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default }, + { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS[] = { + { "BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS", 0, 6, &umr_bitfield_default }, + { "BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS", 7, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS[] = { + { "BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS[] = { + { "LINK_POSITION_IN_BUFFER_ALIAS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGA_RENDER_CONTROL[] = { + { "VGA_BLINK_RATE", 0, 4, &umr_bitfield_default }, + { "VGA_BLINK_MODE", 5, 6, &umr_bitfield_default }, + { "VGA_CURSOR_BLINK_INVERT", 7, 7, &umr_bitfield_default }, + { "VGA_EXTD_ADDR_COUNT_ENABLE", 8, 8, &umr_bitfield_default }, + { "VGA_VSTATUS_CNTL", 16, 17, &umr_bitfield_default }, + { "VGA_LOCK_8DOT", 24, 24, &umr_bitfield_default }, + { "VGAREG_LINECMP_COMPATIBILITY_SEL", 25, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGA_SEQUENCER_RESET_CONTROL[] = { + { "D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET", 0, 0, &umr_bitfield_default }, + { "D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET", 1, 1, &umr_bitfield_default }, + { "D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET", 2, 2, &umr_bitfield_default }, + { "D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET", 3, 3, &umr_bitfield_default }, + { "D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET", 4, 4, &umr_bitfield_default }, + { "D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET", 5, 5, &umr_bitfield_default }, + { "D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET", 8, 8, &umr_bitfield_default }, + { "D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET", 9, 9, &umr_bitfield_default }, + { "D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET", 10, 10, &umr_bitfield_default }, + { "D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET", 11, 11, &umr_bitfield_default }, + { "D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET", 12, 12, &umr_bitfield_default }, + { "D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET", 13, 13, &umr_bitfield_default }, + { "VGA_MODE_AUTO_TRIGGER_ENABLE", 16, 16, &umr_bitfield_default }, + { "VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT", 17, 17, &umr_bitfield_default }, + { "VGA_MODE_AUTO_TRIGGER_INDEX_SELECT", 18, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGA_MODE_CONTROL[] = { + { "VGA_ATI_LINEAR", 0, 0, &umr_bitfield_default }, + { "VGA_LUT_PALETTE_UPDATE_MODE", 4, 5, &umr_bitfield_default }, + { "VGA_128K_APERTURE_PAGING", 8, 8, &umr_bitfield_default }, + { "VGA_TEXT_132_COLUMNS_EN", 16, 16, &umr_bitfield_default }, + { "VGA_DEEP_SLEEP_FORCE_EXIT", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGA_SURFACE_PITCH_SELECT[] = { + { "VGA_SURFACE_PITCH_SELECT", 0, 1, &umr_bitfield_default }, + { "VGA_SURFACE_HEIGHT_SELECT", 8, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGA_MEMORY_BASE_ADDRESS[] = { + { "VGA_MEMORY_BASE_ADDRESS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGA_DISPBUF1_SURFACE_ADDR[] = { + { "VGA_DISPBUF1_SURFACE_ADDR", 0, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGA_DISPBUF2_SURFACE_ADDR[] = { + { "VGA_DISPBUF2_SURFACE_ADDR", 0, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGA_MEMORY_BASE_ADDRESS_HIGH[] = { + { "VGA_MEMORY_BASE_ADDRESS_HIGH", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGA_HDP_CONTROL[] = { + { "VGA_MEM_PAGE_SELECT_EN", 0, 0, &umr_bitfield_default }, + { "VGA_MEMORY_DISABLE", 4, 4, &umr_bitfield_default }, + { "VGA_RBBM_LOCK_DISABLE", 8, 8, &umr_bitfield_default }, + { "VGA_SOFT_RESET", 16, 16, &umr_bitfield_default }, + { "VGA_TEST_RESET_CONTROL", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGA_CACHE_CONTROL[] = { + { "VGA_WRITE_THROUGH_CACHE_DIS", 0, 0, &umr_bitfield_default }, + { "VGA_READ_CACHE_DISABLE", 8, 8, &umr_bitfield_default }, + { "VGA_READ_BUFFER_INVALIDATE", 16, 16, &umr_bitfield_default }, + { "VGA_DCCIF_W256ONLY", 20, 20, &umr_bitfield_default }, + { "VGA_DCCIF_WC_TIMEOUT", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmD1VGA_CONTROL[] = { + { "D1VGA_MODE_ENABLE", 0, 0, &umr_bitfield_default }, + { "D1VGA_TIMING_SELECT", 8, 8, &umr_bitfield_default }, + { "D1VGA_SYNC_POLARITY_SELECT", 9, 9, &umr_bitfield_default }, + { "D1VGA_OVERSCAN_COLOR_EN", 16, 16, &umr_bitfield_default }, + { "D1VGA_ROTATE", 24, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmD2VGA_CONTROL[] = { + { "D2VGA_MODE_ENABLE", 0, 0, &umr_bitfield_default }, + { "D2VGA_TIMING_SELECT", 8, 8, &umr_bitfield_default }, + { "D2VGA_SYNC_POLARITY_SELECT", 9, 9, &umr_bitfield_default }, + { "D2VGA_OVERSCAN_COLOR_EN", 16, 16, &umr_bitfield_default }, + { "D2VGA_ROTATE", 24, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGA_STATUS[] = { + { "VGA_MEM_ACCESS_STATUS", 0, 0, &umr_bitfield_default }, + { "VGA_REG_ACCESS_STATUS", 1, 1, &umr_bitfield_default }, + { "VGA_DISPLAY_SWITCH_STATUS", 2, 2, &umr_bitfield_default }, + { "VGA_MODE_AUTO_TRIGGER_STATUS", 3, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGA_INTERRUPT_CONTROL[] = { + { "VGA_MEM_ACCESS_INT_MASK", 0, 0, &umr_bitfield_default }, + { "VGA_REG_ACCESS_INT_MASK", 8, 8, &umr_bitfield_default }, + { "VGA_DISPLAY_SWITCH_INT_MASK", 16, 16, &umr_bitfield_default }, + { "VGA_MODE_AUTO_TRIGGER_INT_MASK", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGA_STATUS_CLEAR[] = { + { "VGA_MEM_ACCESS_INT_CLEAR", 0, 0, &umr_bitfield_default }, + { "VGA_REG_ACCESS_INT_CLEAR", 8, 8, &umr_bitfield_default }, + { "VGA_DISPLAY_SWITCH_INT_CLEAR", 16, 16, &umr_bitfield_default }, + { "VGA_MODE_AUTO_TRIGGER_INT_CLEAR", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGA_INTERRUPT_STATUS[] = { + { "VGA_MEM_ACCESS_INT_STATUS", 0, 0, &umr_bitfield_default }, + { "VGA_REG_ACCESS_INT_STATUS", 1, 1, &umr_bitfield_default }, + { "VGA_DISPLAY_SWITCH_INT_STATUS", 2, 2, &umr_bitfield_default }, + { "VGA_MODE_AUTO_TRIGGER_INT_STATUS", 3, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGA_MAIN_CONTROL[] = { + { "VGA_CRTC_TIMEOUT", 0, 1, &umr_bitfield_default }, + { "VGA_RENDER_TIMEOUT_COUNT", 3, 4, &umr_bitfield_default }, + { "VGA_VIRTUAL_VERTICAL_RETRACE_DURATION", 5, 7, &umr_bitfield_default }, + { "VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT", 8, 9, &umr_bitfield_default }, + { "VGA_MC_WRITE_CLEAN_WAIT_DELAY", 12, 15, &umr_bitfield_default }, + { "VGA_READBACK_NO_DISPLAY_SOURCE_SELECT", 16, 17, &umr_bitfield_default }, + { "VGA_READBACK_CRT_INTR_SOURCE_SELECT", 24, 25, &umr_bitfield_default }, + { "VGA_READBACK_SENSE_SWITCH_SELECT", 26, 26, &umr_bitfield_default }, + { "VGA_EXTERNAL_DAC_SENSE", 29, 29, &umr_bitfield_default }, + { "VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGA_TEST_CONTROL[] = { + { "VGA_TEST_ENABLE", 0, 0, &umr_bitfield_default }, + { "VGA_TEST_RENDER_START", 8, 8, &umr_bitfield_default }, + { "VGA_TEST_RENDER_DONE", 16, 16, &umr_bitfield_default }, + { "VGA_TEST_RENDER_DISPBUF_SELECT", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGA_QOS_CTRL[] = { + { "VGA_READ_QOS", 0, 3, &umr_bitfield_default }, + { "VGA_WRITE_QOS", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmD3VGA_CONTROL[] = { + { "D3VGA_MODE_ENABLE", 0, 0, &umr_bitfield_default }, + { "D3VGA_TIMING_SELECT", 8, 8, &umr_bitfield_default }, + { "D3VGA_SYNC_POLARITY_SELECT", 9, 9, &umr_bitfield_default }, + { "D3VGA_OVERSCAN_COLOR_EN", 16, 16, &umr_bitfield_default }, + { "D3VGA_ROTATE", 24, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmD4VGA_CONTROL[] = { + { "D4VGA_MODE_ENABLE", 0, 0, &umr_bitfield_default }, + { "D4VGA_TIMING_SELECT", 8, 8, &umr_bitfield_default }, + { "D4VGA_SYNC_POLARITY_SELECT", 9, 9, &umr_bitfield_default }, + { "D4VGA_OVERSCAN_COLOR_EN", 16, 16, &umr_bitfield_default }, + { "D4VGA_ROTATE", 24, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmD5VGA_CONTROL[] = { + { "D5VGA_MODE_ENABLE", 0, 0, &umr_bitfield_default }, + { "D5VGA_TIMING_SELECT", 8, 8, &umr_bitfield_default }, + { "D5VGA_SYNC_POLARITY_SELECT", 9, 9, &umr_bitfield_default }, + { "D5VGA_OVERSCAN_COLOR_EN", 16, 16, &umr_bitfield_default }, + { "D5VGA_ROTATE", 24, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmD6VGA_CONTROL[] = { + { "D6VGA_MODE_ENABLE", 0, 0, &umr_bitfield_default }, + { "D6VGA_TIMING_SELECT", 8, 8, &umr_bitfield_default }, + { "D6VGA_SYNC_POLARITY_SELECT", 9, 9, &umr_bitfield_default }, + { "D6VGA_OVERSCAN_COLOR_EN", 16, 16, &umr_bitfield_default }, + { "D6VGA_ROTATE", 24, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGA_SOURCE_SELECT[] = { + { "VGA_SOURCE_SEL_A", 0, 2, &umr_bitfield_default }, + { "VGA_SOURCE_SEL_B", 8, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPHYPLLA_PIXCLK_RESYNC_CNTL[] = { + { "PHYPLLA_PIXCLK_RESYNC_ENABLE", 0, 0, &umr_bitfield_default }, + { "PHYPLLA_DCCG_DEEP_COLOR_CNTL", 4, 5, &umr_bitfield_default }, + { "PHYPLLA_PIXCLK_ENABLE", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPHYPLLB_PIXCLK_RESYNC_CNTL[] = { + { "PHYPLLB_PIXCLK_RESYNC_ENABLE", 0, 0, &umr_bitfield_default }, + { "PHYPLLB_DCCG_DEEP_COLOR_CNTL", 4, 5, &umr_bitfield_default }, + { "PHYPLLB_PIXCLK_ENABLE", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPHYPLLC_PIXCLK_RESYNC_CNTL[] = { + { "PHYPLLC_PIXCLK_RESYNC_ENABLE", 0, 0, &umr_bitfield_default }, + { "PHYPLLC_DCCG_DEEP_COLOR_CNTL", 4, 5, &umr_bitfield_default }, + { "PHYPLLC_PIXCLK_ENABLE", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPHYPLLD_PIXCLK_RESYNC_CNTL[] = { + { "PHYPLLD_PIXCLK_RESYNC_ENABLE", 0, 0, &umr_bitfield_default }, + { "PHYPLLD_DCCG_DEEP_COLOR_CNTL", 4, 5, &umr_bitfield_default }, + { "PHYPLLD_PIXCLK_ENABLE", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_DTO_DBUF_EN[] = { + { "DP_DTO0_DBUF_EN", 0, 0, &umr_bitfield_default }, + { "DP_DTO1_DBUF_EN", 1, 1, &umr_bitfield_default }, + { "DP_DTO2_DBUF_EN", 2, 2, &umr_bitfield_default }, + { "DP_DTO3_DBUF_EN", 3, 3, &umr_bitfield_default }, + { "DP_DTO4_DBUF_EN", 4, 4, &umr_bitfield_default }, + { "DP_DTO5_DBUF_EN", 5, 5, &umr_bitfield_default }, + { "DP_DTO6_DBUF_EN", 6, 6, &umr_bitfield_default }, + { "DP_DTO7_DBUF_EN", 7, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDPREFCLK_CGTT_BLK_CTRL_REG[] = { + { "DPREFCLK_TURN_ON_DELAY", 0, 3, &umr_bitfield_default }, + { "DPREFCLK_TURN_OFF_DELAY", 4, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmREFCLK_CNTL[] = { + { "REFCLK_CLOCK_EN", 0, 0, &umr_bitfield_default }, + { "REFCLK_SRC_SEL", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMIPI_CLK_CNTL[] = { + { "DSICLK_CLOCK_ENABLE", 0, 0, &umr_bitfield_default }, + { "BYTECLK_CLOCK_ENABLE", 1, 1, &umr_bitfield_default }, + { "ESCCLK_CLOCK_ENABLE", 2, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmREFCLK_CGTT_BLK_CTRL_REG[] = { + { "REFCLK_TURN_ON_DELAY", 0, 3, &umr_bitfield_default }, + { "REFCLK_TURN_OFF_DELAY", 4, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPHYPLLE_PIXCLK_RESYNC_CNTL[] = { + { "PHYPLLE_PIXCLK_RESYNC_ENABLE", 0, 0, &umr_bitfield_default }, + { "PHYPLLE_DCCG_DEEP_COLOR_CNTL", 4, 5, &umr_bitfield_default }, + { "PHYPLLE_PIXCLK_ENABLE", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCCG_PERFMON_CNTL2[] = { + { "DCCG_PERF_DSICLK_ENABLE", 0, 0, &umr_bitfield_default }, + { "DCCG_PERF_REFCLK_ENABLE", 1, 1, &umr_bitfield_default }, + { "DCCG_PERF_PIXCLK1_ENABLE", 2, 2, &umr_bitfield_default }, + { "DCCG_PERF_PIXCLK2_ENABLE", 3, 3, &umr_bitfield_default }, + { "DCCG_PERF_UNIPHYC_PIXCLK_ENABLE", 4, 4, &umr_bitfield_default }, + { "DCCG_PERF_UNIPHYD_PIXCLK_ENABLE", 5, 5, &umr_bitfield_default }, + { "DCCG_PERF_UNIPHYE_PIXCLK_ENABLE", 6, 6, &umr_bitfield_default }, + { "DCCG_PERF_UNIPHYF_PIXCLK_ENABLE", 7, 7, &umr_bitfield_default }, + { "DCCG_PERF_UNIPHYG_PIXCLK_ENABLE", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSICLK_CGTT_BLK_CTRL_REG[] = { + { "DSICLK_TURN_ON_DELAY", 0, 3, &umr_bitfield_default }, + { "DSICLK_TURN_OFF_DELAY", 4, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCCG_CBUS_WRCMD_DELAY[] = { + { "CBUS_PLL_WRCMD_DELAY", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCCG_DS_DTO_INCR[] = { + { "DCCG_DS_DTO_INCR", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCCG_DS_DTO_MODULO[] = { + { "DCCG_DS_DTO_MODULO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCCG_DS_CNTL[] = { + { "DCCG_DS_ENABLE", 0, 0, &umr_bitfield_default }, + { "DCCG_DS_REF_SRC", 4, 5, &umr_bitfield_default }, + { "DCCG_DS_HW_CAL_ENABLE", 8, 8, &umr_bitfield_default }, + { "DCCG_DS_ENABLED_STATUS", 9, 9, &umr_bitfield_default }, + { "DCCG_DS_XTALIN_RATE_DIV", 16, 17, &umr_bitfield_default }, + { "DCCG_DS_JITTER_REMOVE_DIS", 24, 24, &umr_bitfield_default }, + { "DCCG_DS_DELAY_XTAL_SEL", 25, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCCG_DS_HW_CAL_INTERVAL[] = { + { "DCCG_DS_HW_CAL_INTERVAL", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSYMCLKG_CLOCK_ENABLE[] = { + { "SYMCLKG_CLOCK_ENABLE", 0, 0, &umr_bitfield_default }, + { "SYMCLKG_FE_FORCE_EN", 4, 4, &umr_bitfield_default }, + { "SYMCLKG_FE_FORCE_SRC", 8, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDPREFCLK_CNTL[] = { + { "DPREFCLK_SRC_SEL", 0, 2, &umr_bitfield_default }, + { "UNB_DB_CLK_ENABLE", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAOMCLK0_CNTL[] = { + { "AOMCLK0_CLOCK_EN", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAOMCLK1_CNTL[] = { + { "AOMCLK1_CLOCK_EN", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAOMCLK2_CNTL[] = { + { "AOMCLK2_CLOCK_EN", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCCG_AUDIO_DTO2_PHASE[] = { + { "DCCG_AUDIO_DTO2_PHASE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCCG_AUDIO_DTO2_MODULO[] = { + { "DCCG_AUDIO_DTO2_MODULO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCE_VERSION[] = { + { "MAJOR_VERSION", 0, 7, &umr_bitfield_default }, + { "MINOR_VERSION", 8, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPHYPLLG_PIXCLK_RESYNC_CNTL[] = { + { "PHYPLLG_PIXCLK_RESYNC_ENABLE", 0, 0, &umr_bitfield_default }, + { "PHYPLLG_DCCG_DEEP_COLOR_CNTL", 4, 5, &umr_bitfield_default }, + { "PHYPLLG_PIXCLK_ENABLE", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCCG_GTC_CNTL[] = { + { "DCCG_GTC_ENABLE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCCG_GTC_DTO_INCR[] = { + { "DCCG_GTC_DTO_INCR", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCCG_GTC_DTO_MODULO[] = { + { "DCCG_GTC_DTO_MODULO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCCG_GTC_CURRENT[] = { + { "DCCG_GTC_CURRENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMIPI_DTO_CNTL[] = { + { "MIPI_DTO_ENABLE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMIPI_DTO_PHASE[] = { + { "MIPI_DTO_PHASE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMIPI_DTO_MODULO[] = { + { "MIPI_DTO_MODULO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAC_CLK_ENABLE[] = { + { "DACA_CLK_ENABLE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDVO_CLK_ENABLE[] = { + { "DVO_CLK_ENABLE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAVSYNC_COUNTER_WRITE[] = { + { "AVSYNC_COUNTER_WRVALUE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAVSYNC_COUNTER_CONTROL[] = { + { "AVSYNC_COUNTER_ENABLE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAVSYNC_COUNTER_READ[] = { + { "AVSYNC_COUNTER_RDVALUE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMILLISECOND_TIME_BASE_DIV[] = { + { "MILLISECOND_TIME_BASE_DIV", 0, 16, &umr_bitfield_default }, + { "MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL", 20, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDISPCLK_FREQ_CHANGE_CNTL[] = { + { "DISPCLK_STEP_DELAY", 0, 13, &umr_bitfield_default }, + { "DISPCLK_STEP_SIZE", 16, 19, &umr_bitfield_default }, + { "DISPCLK_FREQ_RAMP_DONE", 20, 20, &umr_bitfield_default }, + { "DISPCLK_MAX_ERRDET_CYCLES", 25, 27, &umr_bitfield_default }, + { "DCCG_FIFO_ERRDET_RESET", 28, 28, &umr_bitfield_default }, + { "DCCG_FIFO_ERRDET_STATE", 29, 29, &umr_bitfield_default }, + { "DCCG_FIFO_ERRDET_OVR_EN", 30, 30, &umr_bitfield_default }, + { "DISPCLK_CHG_FWD_CORR_DISABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_MEM_GLOBAL_PWR_REQ_CNTL[] = { + { "DC_MEM_GLOBAL_PWR_REQ_DIS", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCCG_PERFMON_CNTL[] = { + { "DCCG_PERF_DISPCLK_ENABLE", 0, 0, &umr_bitfield_default }, + { "DCCG_PERF_DPREFCLK_ENABLE", 1, 1, &umr_bitfield_default }, + { "DCCG_PERF_UNIPHYA_PIXCLK_ENABLE", 2, 2, &umr_bitfield_default }, + { "DCCG_PERF_UNIPHYB_PIXCLK_ENABLE", 3, 3, &umr_bitfield_default }, + { "DCCG_PERF_PIXCLK0_ENABLE", 4, 4, &umr_bitfield_default }, + { "DCCG_PERF_RUN", 5, 5, &umr_bitfield_default }, + { "DCCG_PERF_MODE_VSYNC", 6, 6, &umr_bitfield_default }, + { "DCCG_PERF_MODE_HSYNC", 7, 7, &umr_bitfield_default }, + { "DCCG_PERF_OTG_SEL", 8, 10, &umr_bitfield_default }, + { "DCCG_PERF_XTALIN_PULSE_DIV", 11, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCCG_GATE_DISABLE_CNTL[] = { + { "DISPCLK_DCCG_GATE_DISABLE", 0, 0, &umr_bitfield_default }, + { "DISPCLK_R_DCCG_GATE_DISABLE", 1, 1, &umr_bitfield_default }, + { "SOCCLK_GATE_DISABLE", 2, 2, &umr_bitfield_default }, + { "DPREFCLK_GATE_DISABLE", 3, 3, &umr_bitfield_default }, + { "DACACLK_GATE_DISABLE", 4, 4, &umr_bitfield_default }, + { "DVOACLK_GATE_DISABLE", 6, 6, &umr_bitfield_default }, + { "DPREFCLK_R_DCCG_GATE_DISABLE", 8, 8, &umr_bitfield_default }, + { "DPPCLK_GATE_DISABLE", 9, 9, &umr_bitfield_default }, + { "AOMCLK0_GATE_DISABLE", 17, 17, &umr_bitfield_default }, + { "AOMCLK1_GATE_DISABLE", 18, 18, &umr_bitfield_default }, + { "AOMCLK2_GATE_DISABLE", 19, 19, &umr_bitfield_default }, + { "AUDIO_DTO2_CLK_GATE_DISABLE", 21, 21, &umr_bitfield_default }, + { "DPREFCLK_GTC_GATE_DISABLE", 22, 22, &umr_bitfield_default }, + { "UNB_DB_CLK_GATE_DISABLE", 23, 23, &umr_bitfield_default }, + { "REFCLK_GATE_DISABLE", 26, 26, &umr_bitfield_default }, + { "REFCLK_R_DIG_GATE_DISABLE", 27, 27, &umr_bitfield_default }, + { "DSICLK_GATE_DISABLE", 28, 28, &umr_bitfield_default }, + { "BYTECLK_GATE_DISABLE", 29, 29, &umr_bitfield_default }, + { "ESCCLK_GATE_DISABLE", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDISPCLK_CGTT_BLK_CTRL_REG[] = { + { "DISPCLK_TURN_ON_DELAY", 0, 3, &umr_bitfield_default }, + { "DISPCLK_TURN_OFF_DELAY", 4, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSOCCLK_CGTT_BLK_CTRL_REG[] = { + { "SOCCLK_TURN_ON_DELAY", 0, 3, &umr_bitfield_default }, + { "SOCCLK_TURN_OFF_DELAY", 4, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCCG_CAC_STATUS[] = { + { "CAC_STATUS_RDDATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPIXCLK1_RESYNC_CNTL[] = { + { "PIXCLK1_RESYNC_ENABLE", 0, 0, &umr_bitfield_default }, + { "DCCG_DEEP_COLOR_CNTL1", 4, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPIXCLK2_RESYNC_CNTL[] = { + { "PIXCLK2_RESYNC_ENABLE", 0, 0, &umr_bitfield_default }, + { "DCCG_DEEP_COLOR_CNTL2", 4, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPIXCLK0_RESYNC_CNTL[] = { + { "PIXCLK0_RESYNC_ENABLE", 0, 0, &umr_bitfield_default }, + { "DCCG_DEEP_COLOR_CNTL0", 4, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMICROSECOND_TIME_BASE_DIV[] = { + { "MICROSECOND_TIME_BASE_DIV", 0, 6, &umr_bitfield_default }, + { "XTAL_REF_DIV", 8, 14, &umr_bitfield_default }, + { "XTAL_REF_SEL", 16, 16, &umr_bitfield_default }, + { "XTAL_REF_CLOCK_SOURCE_SEL", 17, 17, &umr_bitfield_default }, + { "MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL", 20, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCCG_GATE_DISABLE_CNTL2[] = { + { "SYMCLKA_FE_GATE_DISABLE", 0, 0, &umr_bitfield_default }, + { "SYMCLKB_FE_GATE_DISABLE", 1, 1, &umr_bitfield_default }, + { "SYMCLKC_FE_GATE_DISABLE", 2, 2, &umr_bitfield_default }, + { "SYMCLKD_FE_GATE_DISABLE", 3, 3, &umr_bitfield_default }, + { "SYMCLKE_FE_GATE_DISABLE", 4, 4, &umr_bitfield_default }, + { "SYMCLKF_FE_GATE_DISABLE", 5, 5, &umr_bitfield_default }, + { "SYMCLKG_FE_GATE_DISABLE", 6, 6, &umr_bitfield_default }, + { "SYMCLKA_GATE_DISABLE", 16, 16, &umr_bitfield_default }, + { "SYMCLKB_GATE_DISABLE", 17, 17, &umr_bitfield_default }, + { "SYMCLKC_GATE_DISABLE", 18, 18, &umr_bitfield_default }, + { "SYMCLKD_GATE_DISABLE", 19, 19, &umr_bitfield_default }, + { "SYMCLKE_GATE_DISABLE", 20, 20, &umr_bitfield_default }, + { "SYMCLKF_GATE_DISABLE", 21, 21, &umr_bitfield_default }, + { "SYMCLKG_GATE_DISABLE", 22, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSYMCLK_CGTT_BLK_CTRL_REG[] = { + { "SYMCLK_TURN_ON_DELAY", 0, 3, &umr_bitfield_default }, + { "SYMCLK_TURN_OFF_DELAY", 4, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPHYPLLF_PIXCLK_RESYNC_CNTL[] = { + { "PHYPLLF_PIXCLK_RESYNC_ENABLE", 0, 0, &umr_bitfield_default }, + { "PHYPLLF_DCCG_DEEP_COLOR_CNTL", 4, 5, &umr_bitfield_default }, + { "PHYPLLF_PIXCLK_ENABLE", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCCG_DISP_CNTL_REG[] = { + { "ALLOW_SR_ON_TRANS_REQ", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_PIXEL_RATE_CNTL[] = { + { "OTG0_PIXEL_RATE_SOURCE", 0, 1, &umr_bitfield_default }, + { "DP_DTO0_ENABLE", 4, 4, &umr_bitfield_default }, + { "DP_DTO0_DS_DISABLE", 5, 5, &umr_bitfield_default }, + { "OTG0_ADD_PIXEL", 8, 8, &umr_bitfield_default }, + { "OTG0_DROP_PIXEL", 9, 9, &umr_bitfield_default }, + { "OTG0_DISPOUT_FIFO_ERROR", 14, 15, &umr_bitfield_default }, + { "OTG0_DISPOUT_ERROR_COUNT", 16, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_DTO0_PHASE[] = { + { "DP_DTO0_PHASE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_DTO0_MODULO[] = { + { "DP_DTO0_MODULO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_PHYPLL_PIXEL_RATE_CNTL[] = { + { "OTG0_PHYPLL_PIXEL_RATE_SOURCE", 0, 2, &umr_bitfield_default }, + { "OTG0_PIXEL_RATE_PLL_SOURCE", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_PIXEL_RATE_CNTL[] = { + { "OTG1_PIXEL_RATE_SOURCE", 0, 1, &umr_bitfield_default }, + { "DP_DTO1_ENABLE", 4, 4, &umr_bitfield_default }, + { "DP_DTO1_DS_DISABLE", 5, 5, &umr_bitfield_default }, + { "OTG1_ADD_PIXEL", 8, 8, &umr_bitfield_default }, + { "OTG1_DROP_PIXEL", 9, 9, &umr_bitfield_default }, + { "OTG1_DISPOUT_FIFO_ERROR", 14, 15, &umr_bitfield_default }, + { "OTG1_DISPOUT_ERROR_COUNT", 16, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_DTO1_PHASE[] = { + { "DP_DTO1_PHASE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_DTO1_MODULO[] = { + { "DP_DTO1_MODULO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_PHYPLL_PIXEL_RATE_CNTL[] = { + { "OTG1_PHYPLL_PIXEL_RATE_SOURCE", 0, 2, &umr_bitfield_default }, + { "OTG1_PIXEL_RATE_PLL_SOURCE", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_PIXEL_RATE_CNTL[] = { + { "OTG2_PIXEL_RATE_SOURCE", 0, 1, &umr_bitfield_default }, + { "DP_DTO2_ENABLE", 4, 4, &umr_bitfield_default }, + { "DP_DTO2_DS_DISABLE", 5, 5, &umr_bitfield_default }, + { "OTG2_ADD_PIXEL", 8, 8, &umr_bitfield_default }, + { "OTG2_DROP_PIXEL", 9, 9, &umr_bitfield_default }, + { "OTG2_DISPOUT_FIFO_ERROR", 14, 15, &umr_bitfield_default }, + { "OTG2_DISPOUT_ERROR_COUNT", 16, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_DTO2_PHASE[] = { + { "DP_DTO2_PHASE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_DTO2_MODULO[] = { + { "DP_DTO2_MODULO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_PHYPLL_PIXEL_RATE_CNTL[] = { + { "OTG2_PHYPLL_PIXEL_RATE_SOURCE", 0, 2, &umr_bitfield_default }, + { "OTG2_PIXEL_RATE_PLL_SOURCE", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_PIXEL_RATE_CNTL[] = { + { "OTG3_PIXEL_RATE_SOURCE", 0, 1, &umr_bitfield_default }, + { "DP_DTO3_ENABLE", 4, 4, &umr_bitfield_default }, + { "DP_DTO3_DS_DISABLE", 5, 5, &umr_bitfield_default }, + { "OTG3_ADD_PIXEL", 8, 8, &umr_bitfield_default }, + { "OTG3_DROP_PIXEL", 9, 9, &umr_bitfield_default }, + { "OTG3_DISPOUT_FIFO_ERROR", 14, 15, &umr_bitfield_default }, + { "OTG3_DISPOUT_ERROR_COUNT", 16, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_DTO3_PHASE[] = { + { "DP_DTO3_PHASE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_DTO3_MODULO[] = { + { "DP_DTO3_MODULO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_PHYPLL_PIXEL_RATE_CNTL[] = { + { "OTG3_PHYPLL_PIXEL_RATE_SOURCE", 0, 2, &umr_bitfield_default }, + { "OTG3_PIXEL_RATE_PLL_SOURCE", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_PIXEL_RATE_CNTL[] = { + { "OTG4_PIXEL_RATE_SOURCE", 0, 1, &umr_bitfield_default }, + { "DP_DTO4_ENABLE", 4, 4, &umr_bitfield_default }, + { "DP_DTO4_DS_DISABLE", 5, 5, &umr_bitfield_default }, + { "OTG4_ADD_PIXEL", 8, 8, &umr_bitfield_default }, + { "OTG4_DROP_PIXEL", 9, 9, &umr_bitfield_default }, + { "OTG4_DISPOUT_FIFO_ERROR", 14, 15, &umr_bitfield_default }, + { "OTG4_DISPOUT_ERROR_COUNT", 16, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_DTO4_PHASE[] = { + { "DP_DTO4_PHASE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_DTO4_MODULO[] = { + { "DP_DTO4_MODULO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_PHYPLL_PIXEL_RATE_CNTL[] = { + { "OTG4_PHYPLL_PIXEL_RATE_SOURCE", 0, 2, &umr_bitfield_default }, + { "OTG4_PIXEL_RATE_PLL_SOURCE", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_PIXEL_RATE_CNTL[] = { + { "OTG5_PIXEL_RATE_SOURCE", 0, 1, &umr_bitfield_default }, + { "DP_DTO5_ENABLE", 4, 4, &umr_bitfield_default }, + { "DP_DTO5_DS_DISABLE", 5, 5, &umr_bitfield_default }, + { "OTG5_ADD_PIXEL", 8, 8, &umr_bitfield_default }, + { "OTG5_DROP_PIXEL", 9, 9, &umr_bitfield_default }, + { "OTG5_DISPOUT_FIFO_ERROR", 14, 15, &umr_bitfield_default }, + { "OTG5_DISPOUT_ERROR_COUNT", 16, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_DTO5_PHASE[] = { + { "DP_DTO5_PHASE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_DTO5_MODULO[] = { + { "DP_DTO5_MODULO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_PHYPLL_PIXEL_RATE_CNTL[] = { + { "OTG5_PHYPLL_PIXEL_RATE_SOURCE", 0, 2, &umr_bitfield_default }, + { "OTG5_PIXEL_RATE_PLL_SOURCE", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDPPCLK_CGTT_BLK_CTRL_REG[] = { + { "DPPCLK_TURN_ON_DELAY", 0, 3, &umr_bitfield_default }, + { "DPPCLK_TURN_OFF_DELAY", 4, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSYMCLKA_CLOCK_ENABLE[] = { + { "SYMCLKA_CLOCK_ENABLE", 0, 0, &umr_bitfield_default }, + { "SYMCLKA_FE_FORCE_EN", 4, 4, &umr_bitfield_default }, + { "SYMCLKA_FE_FORCE_SRC", 8, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSYMCLKB_CLOCK_ENABLE[] = { + { "SYMCLKB_CLOCK_ENABLE", 0, 0, &umr_bitfield_default }, + { "SYMCLKB_FE_FORCE_EN", 4, 4, &umr_bitfield_default }, + { "SYMCLKB_FE_FORCE_SRC", 8, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSYMCLKC_CLOCK_ENABLE[] = { + { "SYMCLKC_CLOCK_ENABLE", 0, 0, &umr_bitfield_default }, + { "SYMCLKC_FE_FORCE_EN", 4, 4, &umr_bitfield_default }, + { "SYMCLKC_FE_FORCE_SRC", 8, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSYMCLKD_CLOCK_ENABLE[] = { + { "SYMCLKD_CLOCK_ENABLE", 0, 0, &umr_bitfield_default }, + { "SYMCLKD_FE_FORCE_EN", 4, 4, &umr_bitfield_default }, + { "SYMCLKD_FE_FORCE_SRC", 8, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSYMCLKE_CLOCK_ENABLE[] = { + { "SYMCLKE_CLOCK_ENABLE", 0, 0, &umr_bitfield_default }, + { "SYMCLKE_FE_FORCE_EN", 4, 4, &umr_bitfield_default }, + { "SYMCLKE_FE_FORCE_SRC", 8, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSYMCLKF_CLOCK_ENABLE[] = { + { "SYMCLKF_CLOCK_ENABLE", 0, 0, &umr_bitfield_default }, + { "SYMCLKF_FE_FORCE_EN", 4, 4, &umr_bitfield_default }, + { "SYMCLKF_FE_FORCE_SRC", 8, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCCG_SOFT_RESET[] = { + { "REFCLK_SOFT_RESET", 0, 0, &umr_bitfield_default }, + { "PCIE_REFCLK_SOFT_RESET", 1, 1, &umr_bitfield_default }, + { "SOFT_RESET_DVO", 2, 2, &umr_bitfield_default }, + { "DVO_ENABLE_RST", 3, 3, &umr_bitfield_default }, + { "AUDIO_DTO2_CLK_SOFT_RESET", 4, 4, &umr_bitfield_default }, + { "DPREFCLK_SOFT_RESET", 8, 8, &umr_bitfield_default }, + { "AMCLK0_SOFT_RESET", 12, 12, &umr_bitfield_default }, + { "AMCLK1_SOFT_RESET", 13, 13, &umr_bitfield_default }, + { "P0PLL_CFG_IF_SOFT_RESET", 14, 14, &umr_bitfield_default }, + { "P1PLL_CFG_IF_SOFT_RESET", 15, 15, &umr_bitfield_default }, + { "P2PLL_CFG_IF_SOFT_RESET", 16, 16, &umr_bitfield_default }, + { "A0PLL_CFG_IF_SOFT_RESET", 17, 17, &umr_bitfield_default }, + { "A1PLL_CFG_IF_SOFT_RESET", 18, 18, &umr_bitfield_default }, + { "C0PLL_CFG_IF_SOFT_RESET", 19, 19, &umr_bitfield_default }, + { "C1PLL_CFG_IF_SOFT_RESET", 20, 20, &umr_bitfield_default }, + { "C2PLL_CFG_IF_SOFT_RESET", 21, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDVOACLKD_CNTL[] = { + { "DVOACLKD_FINE_SKEW_CNTL", 0, 2, &umr_bitfield_default }, + { "DVOACLKD_COARSE_SKEW_CNTL", 8, 12, &umr_bitfield_default }, + { "DVOACLKD_FINE_ADJUST_EN", 16, 16, &umr_bitfield_default }, + { "DVOACLKD_COARSE_ADJUST_EN", 17, 17, &umr_bitfield_default }, + { "DVOACLKD_IN_PHASE", 18, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDVOACLKC_MVP_CNTL[] = { + { "DVOACLKC_MVP_FINE_SKEW_CNTL", 0, 2, &umr_bitfield_default }, + { "DVOACLKC_MVP_COARSE_SKEW_CNTL", 8, 12, &umr_bitfield_default }, + { "DVOACLKC_MVP_FINE_ADJUST_EN", 16, 16, &umr_bitfield_default }, + { "DVOACLKC_MVP_COARSE_ADJUST_EN", 17, 17, &umr_bitfield_default }, + { "DVOACLKC_MVP_IN_PHASE", 18, 18, &umr_bitfield_default }, + { "DVOACLKC_MVP_SKEW_PHASE_OVERRIDE", 20, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDVOACLKC_CNTL[] = { + { "DVOACLKC_FINE_SKEW_CNTL", 0, 2, &umr_bitfield_default }, + { "DVOACLKC_COARSE_SKEW_CNTL", 8, 12, &umr_bitfield_default }, + { "DVOACLKC_FINE_ADJUST_EN", 16, 16, &umr_bitfield_default }, + { "DVOACLKC_COARSE_ADJUST_EN", 17, 17, &umr_bitfield_default }, + { "DVOACLKC_IN_PHASE", 18, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCCG_AUDIO_DTO_SOURCE[] = { + { "DCCG_AUDIO_DTO0_SOURCE_SEL", 0, 2, &umr_bitfield_default }, + { "DCCG_AUDIO_DTO_SEL", 4, 5, &umr_bitfield_default }, + { "DCCG_AUDIO_DTO2_SOURCE_SEL", 12, 13, &umr_bitfield_default }, + { "DCCG_AUDIO_DTO2_CLOCK_EN", 16, 16, &umr_bitfield_default }, + { "DCCG_AUDIO_DTO2_USE_512FBR_DTO", 20, 20, &umr_bitfield_default }, + { "DCCG_AUDIO_DTO0_USE_512FBR_DTO", 24, 24, &umr_bitfield_default }, + { "DCCG_AUDIO_DTO1_USE_512FBR_DTO", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCCG_AUDIO_DTO0_PHASE[] = { + { "DCCG_AUDIO_DTO0_PHASE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCCG_AUDIO_DTO0_MODULE[] = { + { "DCCG_AUDIO_DTO0_MODULE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCCG_AUDIO_DTO1_PHASE[] = { + { "DCCG_AUDIO_DTO1_PHASE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCCG_AUDIO_DTO1_MODULE[] = { + { "DCCG_AUDIO_DTO1_MODULE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCCG_VSYNC_OTG0_LATCH_VALUE[] = { + { "DCCG_VSYNC_CNT_OTG0_LATCH_VALUE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCCG_VSYNC_OTG1_LATCH_VALUE[] = { + { "DCCG_VSYNC_CNT_OTG1_LATCH_VALUE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCCG_VSYNC_OTG2_LATCH_VALUE[] = { + { "DCCG_VSYNC_CNT_OTG2_LATCH_VALUE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCCG_VSYNC_OTG3_LATCH_VALUE[] = { + { "DCCG_VSYNC_CNT_OTG3_LATCH_VALUE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCCG_VSYNC_OTG4_LATCH_VALUE[] = { + { "DCCG_VSYNC_CNT_OTG4_LATCH_VALUE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCCG_VSYNC_OTG5_LATCH_VALUE[] = { + { "DCCG_VSYNC_CNT_OTG5_LATCH_VALUE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCCG_VSYNC_CNT_CTRL[] = { + { "DCCG_VSYNC_CNT_ENABLE", 0, 0, &umr_bitfield_default }, + { "DCCG_VSYNC_CNT_REFCLK_SEL", 1, 1, &umr_bitfield_default }, + { "DCCG_VSYNC_CNT_SW_RESET", 2, 2, &umr_bitfield_default }, + { "DCCG_VSYNC_CNT_RESET_SEL", 3, 3, &umr_bitfield_default }, + { "DCCG_VSYNC_CNT_EXT_TRIG_SEL", 4, 7, &umr_bitfield_default }, + { "DCCG_VSYNC_CNT_FRAME_CNT", 8, 11, &umr_bitfield_default }, + { "DCCG_VSYNC_OTG0_LATCH_EN", 16, 16, &umr_bitfield_default }, + { "DCCG_VSYNC_OTG1_LATCH_EN", 17, 17, &umr_bitfield_default }, + { "DCCG_VSYNC_OTG2_LATCH_EN", 18, 18, &umr_bitfield_default }, + { "DCCG_VSYNC_OTG3_LATCH_EN", 19, 19, &umr_bitfield_default }, + { "DCCG_VSYNC_OTG4_LATCH_EN", 20, 20, &umr_bitfield_default }, + { "DCCG_VSYNC_OTG5_LATCH_EN", 21, 21, &umr_bitfield_default }, + { "DCCG_VSYNC_OTG0_VSYNC_TRIG_SEL", 24, 24, &umr_bitfield_default }, + { "DCCG_VSYNC_OTG1_VSYNC_TRIG_SEL", 25, 25, &umr_bitfield_default }, + { "DCCG_VSYNC_OTG2_VSYNC_TRIG_SEL", 26, 26, &umr_bitfield_default }, + { "DCCG_VSYNC_OTG3_VSYNC_TRIG_SEL", 27, 27, &umr_bitfield_default }, + { "DCCG_VSYNC_OTG4_VSYNC_TRIG_SEL", 28, 28, &umr_bitfield_default }, + { "DCCG_VSYNC_OTG5_VSYNC_TRIG_SEL", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCCG_VSYNC_CNT_INT_CTRL[] = { + { "DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT", 0, 0, &umr_bitfield_default }, + { "DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_CLEAR", 0, 0, &umr_bitfield_default }, + { "DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT", 1, 1, &umr_bitfield_default }, + { "DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_CLEAR", 1, 1, &umr_bitfield_default }, + { "DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT", 2, 2, &umr_bitfield_default }, + { "DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_CLEAR", 2, 2, &umr_bitfield_default }, + { "DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT", 3, 3, &umr_bitfield_default }, + { "DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_CLEAR", 3, 3, &umr_bitfield_default }, + { "DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT", 4, 4, &umr_bitfield_default }, + { "DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_CLEAR", 4, 4, &umr_bitfield_default }, + { "DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT", 5, 5, &umr_bitfield_default }, + { "DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_CLEAR", 5, 5, &umr_bitfield_default }, + { "DCCG_VSYNC_CNT_OTG0_LATCH_MASK", 8, 8, &umr_bitfield_default }, + { "DCCG_VSYNC_CNT_OTG1_LATCH_MASK", 9, 9, &umr_bitfield_default }, + { "DCCG_VSYNC_CNT_OTG2_LATCH_MASK", 10, 10, &umr_bitfield_default }, + { "DCCG_VSYNC_CNT_OTG3_LATCH_MASK", 11, 11, &umr_bitfield_default }, + { "DCCG_VSYNC_CNT_OTG4_LATCH_MASK", 12, 12, &umr_bitfield_default }, + { "DCCG_VSYNC_CNT_OTG5_LATCH_MASK", 13, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCCG_TEST_CLK_SEL[] = { + { "DCCG_TEST_CLK_GENERICA_SEL", 0, 8, &umr_bitfield_default }, + { "DCCG_TEST_CLK_GENERICA_INV", 12, 12, &umr_bitfield_default }, + { "DCCG_TEST_CLK_GENERICB_SEL", 16, 24, &umr_bitfield_default }, + { "DCCG_TEST_CLK_GENERICB_INV", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDENTIST_DISPCLK_CNTL[] = { + { "DENTIST_DISPCLK_WDIVIDER", 0, 6, &umr_bitfield_default }, + { "DENTIST_DISPCLK_RDIVIDER", 8, 14, &umr_bitfield_default }, + { "DENTIST_DISPCLK_CHG_MODE", 15, 16, &umr_bitfield_default }, + { "DENTIST_DISPCLK_CHGTOG", 17, 17, &umr_bitfield_default }, + { "DENTIST_DISPCLK_DONETOG", 18, 18, &umr_bitfield_default }, + { "DENTIST_DISPCLK_CHG_DONE", 19, 19, &umr_bitfield_default }, + { "DENTIST_DPREFCLK_CHG_DONE", 20, 20, &umr_bitfield_default }, + { "DENTIST_DPREFCLK_CHGTOG", 21, 21, &umr_bitfield_default }, + { "DENTIST_DPREFCLK_DONETOG", 22, 22, &umr_bitfield_default }, + { "DENTIST_DPREFCLK_WDIVIDER", 24, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON0_PERFCOUNTER_CNTL[] = { + { "PERFCOUNTER_EVENT_SEL", 0, 8, &umr_bitfield_default }, + { "PERFCOUNTER_CVALUE_SEL", 9, 11, &umr_bitfield_default }, + { "PERFCOUNTER_INC_MODE", 12, 14, &umr_bitfield_default }, + { "PERFCOUNTER_HW_CNTL_SEL", 15, 15, &umr_bitfield_default }, + { "PERFCOUNTER_RUNEN_MODE", 16, 16, &umr_bitfield_default }, + { "PERFCOUNTER_CNTOFF_START_DIS", 22, 22, &umr_bitfield_default }, + { "PERFCOUNTER_RESTART_EN", 23, 23, &umr_bitfield_default }, + { "PERFCOUNTER_INT_EN", 24, 24, &umr_bitfield_default }, + { "PERFCOUNTER_OFF_MASK", 25, 25, &umr_bitfield_default }, + { "PERFCOUNTER_ACTIVE", 26, 26, &umr_bitfield_default }, + { "PERFCOUNTER_CNTL_SEL", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON0_PERFCOUNTER_CNTL2[] = { + { "PERFCOUNTER_COUNTED_VALUE_TYPE", 0, 1, &umr_bitfield_default }, + { "PERFCOUNTER_HW_STOP1_SEL", 2, 2, &umr_bitfield_default }, + { "PERFCOUNTER_HW_STOP2_SEL", 3, 3, &umr_bitfield_default }, + { "PERFCOUNTER_CNTOFF_SEL", 8, 13, &umr_bitfield_default }, + { "PERFCOUNTER_CNTL2_SEL", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON0_PERFCOUNTER_STATE[] = { + { "PERFCOUNTER_CNT0_STATE", 0, 1, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL0", 2, 2, &umr_bitfield_default }, + { "PERFCOUNTER_CNT1_STATE", 4, 5, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL1", 6, 6, &umr_bitfield_default }, + { "PERFCOUNTER_CNT2_STATE", 8, 9, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL2", 10, 10, &umr_bitfield_default }, + { "PERFCOUNTER_CNT3_STATE", 12, 13, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL3", 14, 14, &umr_bitfield_default }, + { "PERFCOUNTER_CNT4_STATE", 16, 17, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL4", 18, 18, &umr_bitfield_default }, + { "PERFCOUNTER_CNT5_STATE", 20, 21, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL5", 22, 22, &umr_bitfield_default }, + { "PERFCOUNTER_CNT6_STATE", 24, 25, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL6", 26, 26, &umr_bitfield_default }, + { "PERFCOUNTER_CNT7_STATE", 28, 29, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL7", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON0_PERFMON_CNTL[] = { + { "PERFMON_STATE", 0, 1, &umr_bitfield_default }, + { "PERFMON_RPT_COUNT", 8, 27, &umr_bitfield_default }, + { "PERFMON_CNTOFF_AND_OR", 28, 28, &umr_bitfield_default }, + { "PERFMON_CNTOFF_INT_EN", 29, 29, &umr_bitfield_default }, + { "PERFMON_CNTOFF_INT_STATUS", 30, 30, &umr_bitfield_default }, + { "PERFMON_CNTOFF_INT_ACK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON0_PERFMON_CNTL2[] = { + { "PERFMON_CNTOFF_INT_TYPE", 0, 0, &umr_bitfield_default }, + { "PERFMON_CLK_ENABLE", 1, 1, &umr_bitfield_default }, + { "PERFMON_RUN_ENABLE_START_SEL", 2, 9, &umr_bitfield_default }, + { "PERFMON_RUN_ENABLE_STOP_SEL", 10, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC[] = { + { "PERFCOUNTER_INT0_STATUS", 0, 0, &umr_bitfield_default }, + { "PERFCOUNTER_INT1_STATUS", 1, 1, &umr_bitfield_default }, + { "PERFCOUNTER_INT2_STATUS", 2, 2, &umr_bitfield_default }, + { "PERFCOUNTER_INT3_STATUS", 3, 3, &umr_bitfield_default }, + { "PERFCOUNTER_INT4_STATUS", 4, 4, &umr_bitfield_default }, + { "PERFCOUNTER_INT5_STATUS", 5, 5, &umr_bitfield_default }, + { "PERFCOUNTER_INT6_STATUS", 6, 6, &umr_bitfield_default }, + { "PERFCOUNTER_INT7_STATUS", 7, 7, &umr_bitfield_default }, + { "PERFCOUNTER_INT0_ACK", 8, 8, &umr_bitfield_default }, + { "PERFCOUNTER_INT1_ACK", 9, 9, &umr_bitfield_default }, + { "PERFCOUNTER_INT2_ACK", 10, 10, &umr_bitfield_default }, + { "PERFCOUNTER_INT3_ACK", 11, 11, &umr_bitfield_default }, + { "PERFCOUNTER_INT4_ACK", 12, 12, &umr_bitfield_default }, + { "PERFCOUNTER_INT5_ACK", 13, 13, &umr_bitfield_default }, + { "PERFCOUNTER_INT6_ACK", 14, 14, &umr_bitfield_default }, + { "PERFCOUNTER_INT7_ACK", 15, 15, &umr_bitfield_default }, + { "PERFMON_CVALUE_HI", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON0_PERFMON_CVALUE_LOW[] = { + { "PERFMON_CVALUE_LOW", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON0_PERFMON_HI[] = { + { "PERFMON_HI", 0, 15, &umr_bitfield_default }, + { "PERFMON_READ_SEL", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON0_PERFMON_LOW[] = { + { "PERFMON_LOW", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON1_PERFCOUNTER_CNTL[] = { + { "PERFCOUNTER_EVENT_SEL", 0, 8, &umr_bitfield_default }, + { "PERFCOUNTER_CVALUE_SEL", 9, 11, &umr_bitfield_default }, + { "PERFCOUNTER_INC_MODE", 12, 14, &umr_bitfield_default }, + { "PERFCOUNTER_HW_CNTL_SEL", 15, 15, &umr_bitfield_default }, + { "PERFCOUNTER_RUNEN_MODE", 16, 16, &umr_bitfield_default }, + { "PERFCOUNTER_CNTOFF_START_DIS", 22, 22, &umr_bitfield_default }, + { "PERFCOUNTER_RESTART_EN", 23, 23, &umr_bitfield_default }, + { "PERFCOUNTER_INT_EN", 24, 24, &umr_bitfield_default }, + { "PERFCOUNTER_OFF_MASK", 25, 25, &umr_bitfield_default }, + { "PERFCOUNTER_ACTIVE", 26, 26, &umr_bitfield_default }, + { "PERFCOUNTER_CNTL_SEL", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON1_PERFCOUNTER_CNTL2[] = { + { "PERFCOUNTER_COUNTED_VALUE_TYPE", 0, 1, &umr_bitfield_default }, + { "PERFCOUNTER_HW_STOP1_SEL", 2, 2, &umr_bitfield_default }, + { "PERFCOUNTER_HW_STOP2_SEL", 3, 3, &umr_bitfield_default }, + { "PERFCOUNTER_CNTOFF_SEL", 8, 13, &umr_bitfield_default }, + { "PERFCOUNTER_CNTL2_SEL", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON1_PERFCOUNTER_STATE[] = { + { "PERFCOUNTER_CNT0_STATE", 0, 1, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL0", 2, 2, &umr_bitfield_default }, + { "PERFCOUNTER_CNT1_STATE", 4, 5, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL1", 6, 6, &umr_bitfield_default }, + { "PERFCOUNTER_CNT2_STATE", 8, 9, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL2", 10, 10, &umr_bitfield_default }, + { "PERFCOUNTER_CNT3_STATE", 12, 13, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL3", 14, 14, &umr_bitfield_default }, + { "PERFCOUNTER_CNT4_STATE", 16, 17, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL4", 18, 18, &umr_bitfield_default }, + { "PERFCOUNTER_CNT5_STATE", 20, 21, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL5", 22, 22, &umr_bitfield_default }, + { "PERFCOUNTER_CNT6_STATE", 24, 25, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL6", 26, 26, &umr_bitfield_default }, + { "PERFCOUNTER_CNT7_STATE", 28, 29, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL7", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON1_PERFMON_CNTL[] = { + { "PERFMON_STATE", 0, 1, &umr_bitfield_default }, + { "PERFMON_RPT_COUNT", 8, 27, &umr_bitfield_default }, + { "PERFMON_CNTOFF_AND_OR", 28, 28, &umr_bitfield_default }, + { "PERFMON_CNTOFF_INT_EN", 29, 29, &umr_bitfield_default }, + { "PERFMON_CNTOFF_INT_STATUS", 30, 30, &umr_bitfield_default }, + { "PERFMON_CNTOFF_INT_ACK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON1_PERFMON_CNTL2[] = { + { "PERFMON_CNTOFF_INT_TYPE", 0, 0, &umr_bitfield_default }, + { "PERFMON_CLK_ENABLE", 1, 1, &umr_bitfield_default }, + { "PERFMON_RUN_ENABLE_START_SEL", 2, 9, &umr_bitfield_default }, + { "PERFMON_RUN_ENABLE_STOP_SEL", 10, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC[] = { + { "PERFCOUNTER_INT0_STATUS", 0, 0, &umr_bitfield_default }, + { "PERFCOUNTER_INT1_STATUS", 1, 1, &umr_bitfield_default }, + { "PERFCOUNTER_INT2_STATUS", 2, 2, &umr_bitfield_default }, + { "PERFCOUNTER_INT3_STATUS", 3, 3, &umr_bitfield_default }, + { "PERFCOUNTER_INT4_STATUS", 4, 4, &umr_bitfield_default }, + { "PERFCOUNTER_INT5_STATUS", 5, 5, &umr_bitfield_default }, + { "PERFCOUNTER_INT6_STATUS", 6, 6, &umr_bitfield_default }, + { "PERFCOUNTER_INT7_STATUS", 7, 7, &umr_bitfield_default }, + { "PERFCOUNTER_INT0_ACK", 8, 8, &umr_bitfield_default }, + { "PERFCOUNTER_INT1_ACK", 9, 9, &umr_bitfield_default }, + { "PERFCOUNTER_INT2_ACK", 10, 10, &umr_bitfield_default }, + { "PERFCOUNTER_INT3_ACK", 11, 11, &umr_bitfield_default }, + { "PERFCOUNTER_INT4_ACK", 12, 12, &umr_bitfield_default }, + { "PERFCOUNTER_INT5_ACK", 13, 13, &umr_bitfield_default }, + { "PERFCOUNTER_INT6_ACK", 14, 14, &umr_bitfield_default }, + { "PERFCOUNTER_INT7_ACK", 15, 15, &umr_bitfield_default }, + { "PERFMON_CVALUE_HI", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON1_PERFMON_CVALUE_LOW[] = { + { "PERFMON_CVALUE_LOW", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON1_PERFMON_HI[] = { + { "PERFMON_HI", 0, 15, &umr_bitfield_default }, + { "PERFMON_READ_SEL", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON1_PERFMON_LOW[] = { + { "PERFMON_LOW", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED0[] = { + { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED1[] = { + { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED2[] = { + { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED3[] = { + { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED4[] = { + { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED5[] = { + { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED6[] = { + { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED7[] = { + { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED8[] = { + { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED9[] = { + { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED10[] = { + { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED11[] = { + { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED12[] = { + { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED13[] = { + { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED14[] = { + { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED15[] = { + { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED16[] = { + { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED17[] = { + { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED18[] = { + { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED19[] = { + { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED20[] = { + { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED21[] = { + { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED22[] = { + { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED23[] = { + { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED24[] = { + { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED25[] = { + { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED26[] = { + { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED27[] = { + { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED28[] = { + { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED29[] = { + { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED30[] = { + { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED31[] = { + { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED32[] = { + { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED33[] = { + { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED34[] = { + { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED35[] = { + { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED36[] = { + { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED37[] = { + { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED38[] = { + { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED39[] = { + { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED40[] = { + { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED41[] = { + { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRBBMIF_TIMEOUT[] = { + { "RBBMIF_TIMEOUT_DELAY", 0, 19, &umr_bitfield_default }, + { "RBBMIF_TIMEOUT_TO_REQ_HOLD", 20, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRBBMIF_STATUS[] = { + { "RBBMIF_TIMEOUT_CLIENTS_DEC", 0, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRBBMIF_INT_STATUS[] = { + { "RBBMIF_TIMEOUT_OP", 28, 28, &umr_bitfield_default }, + { "RBBMIF_TIMEOUT_RDWR_STATUS", 29, 29, &umr_bitfield_default }, + { "RBBMIF_TIMEOUT_ACK", 30, 30, &umr_bitfield_default }, + { "RBBMIF_TIMEOUT_MASK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRBBMIF_TIMEOUT_DIS[] = { + { "CLIENT0_TIMEOUT_DIS", 0, 0, &umr_bitfield_default }, + { "CLIENT1_TIMEOUT_DIS", 1, 1, &umr_bitfield_default }, + { "CLIENT2_TIMEOUT_DIS", 2, 2, &umr_bitfield_default }, + { "CLIENT3_TIMEOUT_DIS", 3, 3, &umr_bitfield_default }, + { "CLIENT4_TIMEOUT_DIS", 4, 4, &umr_bitfield_default }, + { "CLIENT5_TIMEOUT_DIS", 5, 5, &umr_bitfield_default }, + { "CLIENT6_TIMEOUT_DIS", 6, 6, &umr_bitfield_default }, + { "CLIENT7_TIMEOUT_DIS", 7, 7, &umr_bitfield_default }, + { "CLIENT8_TIMEOUT_DIS", 8, 8, &umr_bitfield_default }, + { "CLIENT9_TIMEOUT_DIS", 9, 9, &umr_bitfield_default }, + { "CLIENT10_TIMEOUT_DIS", 10, 10, &umr_bitfield_default }, + { "CLIENT11_TIMEOUT_DIS", 11, 11, &umr_bitfield_default }, + { "CLIENT12_TIMEOUT_DIS", 12, 12, &umr_bitfield_default }, + { "CLIENT13_TIMEOUT_DIS", 13, 13, &umr_bitfield_default }, + { "CLIENT14_TIMEOUT_DIS", 14, 14, &umr_bitfield_default }, + { "CLIENT15_TIMEOUT_DIS", 15, 15, &umr_bitfield_default }, + { "CLIENT16_TIMEOUT_DIS", 16, 16, &umr_bitfield_default }, + { "CLIENT17_TIMEOUT_DIS", 17, 17, &umr_bitfield_default }, + { "CLIENT18_TIMEOUT_DIS", 18, 18, &umr_bitfield_default }, + { "CLIENT19_TIMEOUT_DIS", 19, 19, &umr_bitfield_default }, + { "CLIENT20_TIMEOUT_DIS", 20, 20, &umr_bitfield_default }, + { "CLIENT21_TIMEOUT_DIS", 21, 21, &umr_bitfield_default }, + { "CLIENT22_TIMEOUT_DIS", 22, 22, &umr_bitfield_default }, + { "CLIENT23_TIMEOUT_DIS", 23, 23, &umr_bitfield_default }, + { "CLIENT24_TIMEOUT_DIS", 24, 24, &umr_bitfield_default }, + { "CLIENT25_TIMEOUT_DIS", 25, 25, &umr_bitfield_default }, + { "CLIENT26_TIMEOUT_DIS", 26, 26, &umr_bitfield_default }, + { "CLIENT27_TIMEOUT_DIS", 27, 27, &umr_bitfield_default }, + { "CLIENT28_TIMEOUT_DIS", 28, 28, &umr_bitfield_default }, + { "CLIENT29_TIMEOUT_DIS", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRBBMIF_STATUS_FLAG[] = { + { "RBBMIF_STATE", 0, 1, &umr_bitfield_default }, + { "RBBMIF_READ_TIMEOUT", 4, 4, &umr_bitfield_default }, + { "RBBMIF_FIFO_EMPTY", 5, 5, &umr_bitfield_default }, + { "RBBMIF_FIFO_FULL", 6, 6, &umr_bitfield_default }, + { "RBBMIF_INVALID_ACCESS_FLAG", 8, 8, &umr_bitfield_default }, + { "RBBMIF_INVALID_ACCESS_TYPE", 9, 11, &umr_bitfield_default }, + { "RBBMIF_INVALID_ACCESS_ADDR", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDOMAIN0_PG_CONFIG[] = { + { "DOMAIN0_POWER_FORCEON", 0, 0, &umr_bitfield_default }, + { "DOMAIN0_POWER_GATE", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDOMAIN0_PG_STATUS[] = { + { "DOMAIN0_DESIRED_PWR_STATE", 28, 28, &umr_bitfield_default }, + { "DOMAIN0_PGFSM_PWR_STATUS", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDOMAIN1_PG_CONFIG[] = { + { "DOMAIN1_POWER_FORCEON", 0, 0, &umr_bitfield_default }, + { "DOMAIN1_POWER_GATE", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDOMAIN1_PG_STATUS[] = { + { "DOMAIN1_DESIRED_PWR_STATE", 28, 28, &umr_bitfield_default }, + { "DOMAIN1_PGFSM_PWR_STATUS", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDOMAIN2_PG_CONFIG[] = { + { "DOMAIN2_POWER_FORCEON", 0, 0, &umr_bitfield_default }, + { "DOMAIN2_POWER_GATE", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDOMAIN2_PG_STATUS[] = { + { "DOMAIN2_DESIRED_PWR_STATE", 28, 28, &umr_bitfield_default }, + { "DOMAIN2_PGFSM_PWR_STATUS", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDOMAIN3_PG_CONFIG[] = { + { "DOMAIN3_POWER_FORCEON", 0, 0, &umr_bitfield_default }, + { "DOMAIN3_POWER_GATE", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDOMAIN3_PG_STATUS[] = { + { "DOMAIN3_DESIRED_PWR_STATE", 28, 28, &umr_bitfield_default }, + { "DOMAIN3_PGFSM_PWR_STATUS", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDOMAIN4_PG_CONFIG[] = { + { "DOMAIN4_POWER_FORCEON", 0, 0, &umr_bitfield_default }, + { "DOMAIN4_POWER_GATE", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDOMAIN4_PG_STATUS[] = { + { "DOMAIN4_DESIRED_PWR_STATE", 28, 28, &umr_bitfield_default }, + { "DOMAIN4_PGFSM_PWR_STATUS", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDOMAIN5_PG_CONFIG[] = { + { "DOMAIN5_POWER_FORCEON", 0, 0, &umr_bitfield_default }, + { "DOMAIN5_POWER_GATE", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDOMAIN5_PG_STATUS[] = { + { "DOMAIN5_DESIRED_PWR_STATE", 28, 28, &umr_bitfield_default }, + { "DOMAIN5_PGFSM_PWR_STATUS", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDOMAIN6_PG_CONFIG[] = { + { "DOMAIN6_POWER_FORCEON", 0, 0, &umr_bitfield_default }, + { "DOMAIN6_POWER_GATE", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDOMAIN6_PG_STATUS[] = { + { "DOMAIN6_DESIRED_PWR_STATE", 28, 28, &umr_bitfield_default }, + { "DOMAIN6_PGFSM_PWR_STATUS", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDOMAIN7_PG_CONFIG[] = { + { "DOMAIN7_POWER_FORCEON", 0, 0, &umr_bitfield_default }, + { "DOMAIN7_POWER_GATE", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDOMAIN7_PG_STATUS[] = { + { "DOMAIN7_DESIRED_PWR_STATE", 28, 28, &umr_bitfield_default }, + { "DOMAIN7_PGFSM_PWR_STATUS", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDOMAIN8_PG_CONFIG[] = { + { "DOMAIN8_POWER_FORCEON", 0, 0, &umr_bitfield_default }, + { "DOMAIN8_POWER_GATE", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDOMAIN8_PG_STATUS[] = { + { "DOMAIN8_DESIRED_PWR_STATE", 28, 28, &umr_bitfield_default }, + { "DOMAIN8_PGFSM_PWR_STATUS", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDOMAIN9_PG_CONFIG[] = { + { "DOMAIN9_POWER_FORCEON", 0, 0, &umr_bitfield_default }, + { "DOMAIN9_POWER_GATE", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDOMAIN9_PG_STATUS[] = { + { "DOMAIN9_DESIRED_PWR_STATE", 28, 28, &umr_bitfield_default }, + { "DOMAIN9_PGFSM_PWR_STATUS", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDOMAIN10_PG_CONFIG[] = { + { "DOMAIN10_POWER_FORCEON", 0, 0, &umr_bitfield_default }, + { "DOMAIN10_POWER_GATE", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDOMAIN10_PG_STATUS[] = { + { "DOMAIN10_DESIRED_PWR_STATE", 28, 28, &umr_bitfield_default }, + { "DOMAIN10_PGFSM_PWR_STATUS", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDOMAIN11_PG_CONFIG[] = { + { "DOMAIN11_POWER_FORCEON", 0, 0, &umr_bitfield_default }, + { "DOMAIN11_POWER_GATE", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDOMAIN11_PG_STATUS[] = { + { "DOMAIN11_DESIRED_PWR_STATE", 28, 28, &umr_bitfield_default }, + { "DOMAIN11_PGFSM_PWR_STATUS", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDOMAIN12_PG_CONFIG[] = { + { "DOMAIN12_POWER_FORCEON", 0, 0, &umr_bitfield_default }, + { "DOMAIN12_POWER_GATE", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDOMAIN12_PG_STATUS[] = { + { "DOMAIN12_DESIRED_PWR_STATE", 28, 28, &umr_bitfield_default }, + { "DOMAIN12_PGFSM_PWR_STATUS", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDOMAIN13_PG_CONFIG[] = { + { "DOMAIN13_POWER_FORCEON", 0, 0, &umr_bitfield_default }, + { "DOMAIN13_POWER_GATE", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDOMAIN13_PG_STATUS[] = { + { "DOMAIN13_DESIRED_PWR_STATE", 28, 28, &umr_bitfield_default }, + { "DOMAIN13_PGFSM_PWR_STATUS", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDOMAIN14_PG_CONFIG[] = { + { "DOMAIN14_POWER_FORCEON", 0, 0, &umr_bitfield_default }, + { "DOMAIN14_POWER_GATE", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDOMAIN14_PG_STATUS[] = { + { "DOMAIN14_DESIRED_PWR_STATE", 28, 28, &umr_bitfield_default }, + { "DOMAIN14_PGFSM_PWR_STATUS", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDOMAIN15_PG_CONFIG[] = { + { "DOMAIN15_POWER_FORCEON", 0, 0, &umr_bitfield_default }, + { "DOMAIN15_POWER_GATE", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDOMAIN15_PG_STATUS[] = { + { "DOMAIN15_DESIRED_PWR_STATE", 28, 28, &umr_bitfield_default }, + { "DOMAIN15_PGFSM_PWR_STATUS", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCPG_INTERRUPT_STATUS[] = { + { "DOMAIN0_POWER_UP_INT_OCCURRED", 0, 0, &umr_bitfield_default }, + { "DOMAIN0_POWER_DOWN_INT_OCCURRED", 1, 1, &umr_bitfield_default }, + { "DOMAIN1_POWER_UP_INT_OCCURRED", 2, 2, &umr_bitfield_default }, + { "DOMAIN1_POWER_DOWN_INT_OCCURRED", 3, 3, &umr_bitfield_default }, + { "DOMAIN2_POWER_UP_INT_OCCURRED", 4, 4, &umr_bitfield_default }, + { "DOMAIN2_POWER_DOWN_INT_OCCURRED", 5, 5, &umr_bitfield_default }, + { "DOMAIN3_POWER_UP_INT_OCCURRED", 6, 6, &umr_bitfield_default }, + { "DOMAIN3_POWER_DOWN_INT_OCCURRED", 7, 7, &umr_bitfield_default }, + { "DOMAIN4_POWER_UP_INT_OCCURRED", 8, 8, &umr_bitfield_default }, + { "DOMAIN4_POWER_DOWN_INT_OCCURRED", 9, 9, &umr_bitfield_default }, + { "DOMAIN5_POWER_UP_INT_OCCURRED", 10, 10, &umr_bitfield_default }, + { "DOMAIN5_POWER_DOWN_INT_OCCURRED", 11, 11, &umr_bitfield_default }, + { "DOMAIN6_POWER_UP_INT_OCCURRED", 12, 12, &umr_bitfield_default }, + { "DOMAIN6_POWER_DOWN_INT_OCCURRED", 13, 13, &umr_bitfield_default }, + { "DOMAIN7_POWER_UP_INT_OCCURRED", 14, 14, &umr_bitfield_default }, + { "DOMAIN7_POWER_DOWN_INT_OCCURRED", 15, 15, &umr_bitfield_default }, + { "DOMAIN8_POWER_UP_INT_OCCURRED", 16, 16, &umr_bitfield_default }, + { "DOMAIN8_POWER_DOWN_INT_OCCURRED", 17, 17, &umr_bitfield_default }, + { "DOMAIN9_POWER_UP_INT_OCCURRED", 18, 18, &umr_bitfield_default }, + { "DOMAIN9_POWER_DOWN_INT_OCCURRED", 19, 19, &umr_bitfield_default }, + { "DOMAIN10_POWER_UP_INT_OCCURRED", 20, 20, &umr_bitfield_default }, + { "DOMAIN10_POWER_DOWN_INT_OCCURRED", 21, 21, &umr_bitfield_default }, + { "DOMAIN11_POWER_UP_INT_OCCURRED", 22, 22, &umr_bitfield_default }, + { "DOMAIN11_POWER_DOWN_INT_OCCURRED", 23, 23, &umr_bitfield_default }, + { "DOMAIN12_POWER_UP_INT_OCCURRED", 24, 24, &umr_bitfield_default }, + { "DOMAIN12_POWER_DOWN_INT_OCCURRED", 25, 25, &umr_bitfield_default }, + { "DOMAIN13_POWER_UP_INT_OCCURRED", 26, 26, &umr_bitfield_default }, + { "DOMAIN13_POWER_DOWN_INT_OCCURRED", 27, 27, &umr_bitfield_default }, + { "DOMAIN14_POWER_UP_INT_OCCURRED", 28, 28, &umr_bitfield_default }, + { "DOMAIN14_POWER_DOWN_INT_OCCURRED", 29, 29, &umr_bitfield_default }, + { "DOMAIN15_POWER_UP_INT_OCCURRED", 30, 30, &umr_bitfield_default }, + { "DOMAIN15_POWER_DOWN_INT_OCCURRED", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCPG_INTERRUPT_CONTROL_1[] = { + { "DOMAIN0_POWER_UP_INT_MASK", 0, 0, &umr_bitfield_default }, + { "DOMAIN0_POWER_UP_INT_CLEAR", 1, 1, &umr_bitfield_default }, + { "DOMAIN0_POWER_DOWN_INT_MASK", 2, 2, &umr_bitfield_default }, + { "DOMAIN0_POWER_DOWN_INT_CLEAR", 3, 3, &umr_bitfield_default }, + { "DOMAIN1_POWER_UP_INT_MASK", 4, 4, &umr_bitfield_default }, + { "DOMAIN1_POWER_UP_INT_CLEAR", 5, 5, &umr_bitfield_default }, + { "DOMAIN1_POWER_DOWN_INT_MASK", 6, 6, &umr_bitfield_default }, + { "DOMAIN1_POWER_DOWN_INT_CLEAR", 7, 7, &umr_bitfield_default }, + { "DOMAIN2_POWER_UP_INT_MASK", 8, 8, &umr_bitfield_default }, + { "DOMAIN2_POWER_UP_INT_CLEAR", 9, 9, &umr_bitfield_default }, + { "DOMAIN2_POWER_DOWN_INT_MASK", 10, 10, &umr_bitfield_default }, + { "DOMAIN2_POWER_DOWN_INT_CLEAR", 11, 11, &umr_bitfield_default }, + { "DOMAIN3_POWER_UP_INT_MASK", 12, 12, &umr_bitfield_default }, + { "DOMAIN3_POWER_UP_INT_CLEAR", 13, 13, &umr_bitfield_default }, + { "DOMAIN3_POWER_DOWN_INT_MASK", 14, 14, &umr_bitfield_default }, + { "DOMAIN3_POWER_DOWN_INT_CLEAR", 15, 15, &umr_bitfield_default }, + { "DOMAIN4_POWER_UP_INT_MASK", 16, 16, &umr_bitfield_default }, + { "DOMAIN4_POWER_UP_INT_CLEAR", 17, 17, &umr_bitfield_default }, + { "DOMAIN4_POWER_DOWN_INT_MASK", 18, 18, &umr_bitfield_default }, + { "DOMAIN4_POWER_DOWN_INT_CLEAR", 19, 19, &umr_bitfield_default }, + { "DOMAIN5_POWER_UP_INT_MASK", 20, 20, &umr_bitfield_default }, + { "DOMAIN5_POWER_UP_INT_CLEAR", 21, 21, &umr_bitfield_default }, + { "DOMAIN5_POWER_DOWN_INT_MASK", 22, 22, &umr_bitfield_default }, + { "DOMAIN5_POWER_DOWN_INT_CLEAR", 23, 23, &umr_bitfield_default }, + { "DOMAIN6_POWER_UP_INT_MASK", 24, 24, &umr_bitfield_default }, + { "DOMAIN6_POWER_UP_INT_CLEAR", 25, 25, &umr_bitfield_default }, + { "DOMAIN6_POWER_DOWN_INT_MASK", 26, 26, &umr_bitfield_default }, + { "DOMAIN6_POWER_DOWN_INT_CLEAR", 27, 27, &umr_bitfield_default }, + { "DOMAIN7_POWER_UP_INT_MASK", 28, 28, &umr_bitfield_default }, + { "DOMAIN7_POWER_UP_INT_CLEAR", 29, 29, &umr_bitfield_default }, + { "DOMAIN7_POWER_DOWN_INT_MASK", 30, 30, &umr_bitfield_default }, + { "DOMAIN7_POWER_DOWN_INT_CLEAR", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCPG_INTERRUPT_CONTROL_2[] = { + { "DOMAIN8_POWER_UP_INT_MASK", 0, 0, &umr_bitfield_default }, + { "DOMAIN8_POWER_UP_INT_CLEAR", 1, 1, &umr_bitfield_default }, + { "DOMAIN8_POWER_DOWN_INT_MASK", 2, 2, &umr_bitfield_default }, + { "DOMAIN8_POWER_DOWN_INT_CLEAR", 3, 3, &umr_bitfield_default }, + { "DOMAIN9_POWER_UP_INT_MASK", 4, 4, &umr_bitfield_default }, + { "DOMAIN9_POWER_UP_INT_CLEAR", 5, 5, &umr_bitfield_default }, + { "DOMAIN9_POWER_DOWN_INT_MASK", 6, 6, &umr_bitfield_default }, + { "DOMAIN9_POWER_DOWN_INT_CLEAR", 7, 7, &umr_bitfield_default }, + { "DOMAIN10_POWER_UP_INT_MASK", 8, 8, &umr_bitfield_default }, + { "DOMAIN10_POWER_UP_INT_CLEAR", 9, 9, &umr_bitfield_default }, + { "DOMAIN10_POWER_DOWN_INT_MASK", 10, 10, &umr_bitfield_default }, + { "DOMAIN10_POWER_DOWN_INT_CLEAR", 11, 11, &umr_bitfield_default }, + { "DOMAIN11_POWER_UP_INT_MASK", 12, 12, &umr_bitfield_default }, + { "DOMAIN11_POWER_UP_INT_CLEAR", 13, 13, &umr_bitfield_default }, + { "DOMAIN11_POWER_DOWN_INT_MASK", 14, 14, &umr_bitfield_default }, + { "DOMAIN11_POWER_DOWN_INT_CLEAR", 15, 15, &umr_bitfield_default }, + { "DOMAIN12_POWER_UP_INT_MASK", 16, 16, &umr_bitfield_default }, + { "DOMAIN12_POWER_UP_INT_CLEAR", 17, 17, &umr_bitfield_default }, + { "DOMAIN12_POWER_DOWN_INT_MASK", 18, 18, &umr_bitfield_default }, + { "DOMAIN12_POWER_DOWN_INT_CLEAR", 19, 19, &umr_bitfield_default }, + { "DOMAIN13_POWER_UP_INT_MASK", 20, 20, &umr_bitfield_default }, + { "DOMAIN13_POWER_UP_INT_CLEAR", 21, 21, &umr_bitfield_default }, + { "DOMAIN13_POWER_DOWN_INT_MASK", 22, 22, &umr_bitfield_default }, + { "DOMAIN13_POWER_DOWN_INT_CLEAR", 23, 23, &umr_bitfield_default }, + { "DOMAIN14_POWER_UP_INT_MASK", 24, 24, &umr_bitfield_default }, + { "DOMAIN14_POWER_UP_INT_CLEAR", 25, 25, &umr_bitfield_default }, + { "DOMAIN14_POWER_DOWN_INT_MASK", 26, 26, &umr_bitfield_default }, + { "DOMAIN14_POWER_DOWN_INT_CLEAR", 27, 27, &umr_bitfield_default }, + { "DOMAIN15_POWER_UP_INT_MASK", 28, 28, &umr_bitfield_default }, + { "DOMAIN15_POWER_UP_INT_CLEAR", 29, 29, &umr_bitfield_default }, + { "DOMAIN15_POWER_DOWN_INT_MASK", 30, 30, &umr_bitfield_default }, + { "DOMAIN15_POWER_DOWN_INT_CLEAR", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_IP_REQUEST_CNTL[] = { + { "IP_REQUEST_EN", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON2_PERFCOUNTER_CNTL[] = { + { "PERFCOUNTER_EVENT_SEL", 0, 8, &umr_bitfield_default }, + { "PERFCOUNTER_CVALUE_SEL", 9, 11, &umr_bitfield_default }, + { "PERFCOUNTER_INC_MODE", 12, 14, &umr_bitfield_default }, + { "PERFCOUNTER_HW_CNTL_SEL", 15, 15, &umr_bitfield_default }, + { "PERFCOUNTER_RUNEN_MODE", 16, 16, &umr_bitfield_default }, + { "PERFCOUNTER_CNTOFF_START_DIS", 22, 22, &umr_bitfield_default }, + { "PERFCOUNTER_RESTART_EN", 23, 23, &umr_bitfield_default }, + { "PERFCOUNTER_INT_EN", 24, 24, &umr_bitfield_default }, + { "PERFCOUNTER_OFF_MASK", 25, 25, &umr_bitfield_default }, + { "PERFCOUNTER_ACTIVE", 26, 26, &umr_bitfield_default }, + { "PERFCOUNTER_CNTL_SEL", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON2_PERFCOUNTER_CNTL2[] = { + { "PERFCOUNTER_COUNTED_VALUE_TYPE", 0, 1, &umr_bitfield_default }, + { "PERFCOUNTER_HW_STOP1_SEL", 2, 2, &umr_bitfield_default }, + { "PERFCOUNTER_HW_STOP2_SEL", 3, 3, &umr_bitfield_default }, + { "PERFCOUNTER_CNTOFF_SEL", 8, 13, &umr_bitfield_default }, + { "PERFCOUNTER_CNTL2_SEL", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON2_PERFCOUNTER_STATE[] = { + { "PERFCOUNTER_CNT0_STATE", 0, 1, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL0", 2, 2, &umr_bitfield_default }, + { "PERFCOUNTER_CNT1_STATE", 4, 5, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL1", 6, 6, &umr_bitfield_default }, + { "PERFCOUNTER_CNT2_STATE", 8, 9, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL2", 10, 10, &umr_bitfield_default }, + { "PERFCOUNTER_CNT3_STATE", 12, 13, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL3", 14, 14, &umr_bitfield_default }, + { "PERFCOUNTER_CNT4_STATE", 16, 17, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL4", 18, 18, &umr_bitfield_default }, + { "PERFCOUNTER_CNT5_STATE", 20, 21, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL5", 22, 22, &umr_bitfield_default }, + { "PERFCOUNTER_CNT6_STATE", 24, 25, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL6", 26, 26, &umr_bitfield_default }, + { "PERFCOUNTER_CNT7_STATE", 28, 29, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL7", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON2_PERFMON_CNTL[] = { + { "PERFMON_STATE", 0, 1, &umr_bitfield_default }, + { "PERFMON_RPT_COUNT", 8, 27, &umr_bitfield_default }, + { "PERFMON_CNTOFF_AND_OR", 28, 28, &umr_bitfield_default }, + { "PERFMON_CNTOFF_INT_EN", 29, 29, &umr_bitfield_default }, + { "PERFMON_CNTOFF_INT_STATUS", 30, 30, &umr_bitfield_default }, + { "PERFMON_CNTOFF_INT_ACK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON2_PERFMON_CNTL2[] = { + { "PERFMON_CNTOFF_INT_TYPE", 0, 0, &umr_bitfield_default }, + { "PERFMON_CLK_ENABLE", 1, 1, &umr_bitfield_default }, + { "PERFMON_RUN_ENABLE_START_SEL", 2, 9, &umr_bitfield_default }, + { "PERFMON_RUN_ENABLE_STOP_SEL", 10, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC[] = { + { "PERFCOUNTER_INT0_STATUS", 0, 0, &umr_bitfield_default }, + { "PERFCOUNTER_INT1_STATUS", 1, 1, &umr_bitfield_default }, + { "PERFCOUNTER_INT2_STATUS", 2, 2, &umr_bitfield_default }, + { "PERFCOUNTER_INT3_STATUS", 3, 3, &umr_bitfield_default }, + { "PERFCOUNTER_INT4_STATUS", 4, 4, &umr_bitfield_default }, + { "PERFCOUNTER_INT5_STATUS", 5, 5, &umr_bitfield_default }, + { "PERFCOUNTER_INT6_STATUS", 6, 6, &umr_bitfield_default }, + { "PERFCOUNTER_INT7_STATUS", 7, 7, &umr_bitfield_default }, + { "PERFCOUNTER_INT0_ACK", 8, 8, &umr_bitfield_default }, + { "PERFCOUNTER_INT1_ACK", 9, 9, &umr_bitfield_default }, + { "PERFCOUNTER_INT2_ACK", 10, 10, &umr_bitfield_default }, + { "PERFCOUNTER_INT3_ACK", 11, 11, &umr_bitfield_default }, + { "PERFCOUNTER_INT4_ACK", 12, 12, &umr_bitfield_default }, + { "PERFCOUNTER_INT5_ACK", 13, 13, &umr_bitfield_default }, + { "PERFCOUNTER_INT6_ACK", 14, 14, &umr_bitfield_default }, + { "PERFCOUNTER_INT7_ACK", 15, 15, &umr_bitfield_default }, + { "PERFMON_CVALUE_HI", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON2_PERFMON_CVALUE_LOW[] = { + { "PERFMON_CVALUE_LOW", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON2_PERFMON_HI[] = { + { "PERFMON_HI", 0, 15, &umr_bitfield_default }, + { "PERFMON_READ_SEL", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON2_PERFMON_LOW[] = { + { "PERFMON_LOW", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCC_DC_PIPE_DIS[] = { + { "DC_PIPE_DIS", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDMU_CLK_CNTL[] = { + { "DMU_TEST_CLK_SEL", 0, 1, &umr_bitfield_default }, + { "DISPCLK_R_DMU_GATE_DIS", 2, 2, &umr_bitfield_default }, + { "DISPCLK_G_DMCU_GATE_DIS", 3, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDMU_MEM_PWR_CNTL[] = { + { "DMCU_ERAM_MEM_PWR_MODE_SEL", 0, 0, &umr_bitfield_default }, + { "DMCU_ERAM_MEM_PWR_FORCE", 1, 2, &umr_bitfield_default }, + { "DMCU_ERAM_MEM_PWR_DIS", 3, 3, &umr_bitfield_default }, + { "DMCU_ERAM_MEM_PWR_STATE", 4, 5, &umr_bitfield_default }, + { "DMCU_IRAM_MEM_PWR_FORCE", 8, 8, &umr_bitfield_default }, + { "DMCU_IRAM_MEM_PWR_DIS", 9, 9, &umr_bitfield_default }, + { "DMCU_IRAM_MEM_PWR_STATE", 10, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDMCU_SMU_INTERRUPT_CNTL[] = { + { "DMCU_SMU_STATIC_SCREEN_INT", 0, 0, &umr_bitfield_default }, + { "DMCU_SMU_STATIC_SCREEN_STATUS", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSMU_INTERRUPT_CONTROL[] = { + { "DC_SMU_INT_ENABLE", 0, 0, &umr_bitfield_default }, + { "DC_SMU_INT_STATUS", 4, 4, &umr_bitfield_default }, + { "DC_SMU_INT_EVENT", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDMCU_CTRL[] = { + { "RESET_UC", 0, 0, &umr_bitfield_default }, + { "IGNORE_PWRMGT", 1, 1, &umr_bitfield_default }, + { "DISABLE_IRQ_TO_UC", 2, 2, &umr_bitfield_default }, + { "DISABLE_XIRQ_TO_UC", 3, 3, &umr_bitfield_default }, + { "DMCU_ENABLE", 4, 4, &umr_bitfield_default }, + { "DMCU_DYN_CLK_GATING_EN", 8, 8, &umr_bitfield_default }, + { "UC_REG_RD_TIMEOUT", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDMCU_STATUS[] = { + { "UC_IN_RESET", 0, 0, &umr_bitfield_default }, + { "UC_IN_WAIT_MODE", 1, 1, &umr_bitfield_default }, + { "UC_IN_STOP_MODE", 2, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDMCU_PC_START_ADDR[] = { + { "PC_START_ADDR_LSB", 0, 7, &umr_bitfield_default }, + { "PC_START_ADDR_MSB", 8, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDMCU_FW_START_ADDR[] = { + { "FW_START_ADDR_LSB", 0, 7, &umr_bitfield_default }, + { "FW_START_ADDR_MSB", 8, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDMCU_FW_END_ADDR[] = { + { "FW_END_ADDR_LSB", 0, 7, &umr_bitfield_default }, + { "FW_END_ADDR_MSB", 8, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDMCU_FW_ISR_START_ADDR[] = { + { "FW_ISR_START_ADDR_LSB", 0, 7, &umr_bitfield_default }, + { "FW_ISR_START_ADDR_MSB", 8, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDMCU_FW_CS_HI[] = { + { "FW_CHECKSUM_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDMCU_FW_CS_LO[] = { + { "FW_CHECKSUM_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDMCU_RAM_ACCESS_CTRL[] = { + { "ERAM_WR_ADDR_AUTO_INC", 0, 0, &umr_bitfield_default }, + { "ERAM_RD_ADDR_AUTO_INC", 1, 1, &umr_bitfield_default }, + { "IRAM_WR_ADDR_AUTO_INC", 2, 2, &umr_bitfield_default }, + { "IRAM_RD_ADDR_AUTO_INC", 3, 3, &umr_bitfield_default }, + { "ERAM_HOST_ACCESS_EN", 4, 4, &umr_bitfield_default }, + { "IRAM_HOST_ACCESS_EN", 5, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDMCU_ERAM_WR_CTRL[] = { + { "ERAM_WR_ADDR", 0, 15, &umr_bitfield_default }, + { "ERAM_WR_BE", 16, 19, &umr_bitfield_default }, + { "ERAM_WR_BYTE_MODE", 20, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDMCU_ERAM_WR_DATA[] = { + { "ERAM_WR_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDMCU_ERAM_RD_CTRL[] = { + { "ERAM_RD_ADDR", 0, 15, &umr_bitfield_default }, + { "ERAM_RD_BE", 16, 19, &umr_bitfield_default }, + { "ERAM_RD_BYTE_MODE", 20, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDMCU_ERAM_RD_DATA[] = { + { "ERAM_RD_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDMCU_IRAM_WR_CTRL[] = { + { "IRAM_WR_ADDR", 0, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDMCU_IRAM_WR_DATA[] = { + { "IRAM_WR_DATA", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDMCU_IRAM_RD_CTRL[] = { + { "IRAM_RD_ADDR", 0, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDMCU_IRAM_RD_DATA[] = { + { "IRAM_RD_DATA", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDMCU_EVENT_TRIGGER[] = { + { "GEN_SW_INT_TO_UC", 0, 0, &umr_bitfield_default }, + { "UC_INTERNAL_INT_CODE", 16, 22, &umr_bitfield_default }, + { "GEN_UC_INTERNAL_INT_TO_HOST", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDMCU_UC_INTERNAL_INT_STATUS[] = { + { "UC_INT_IRQ_N_PIN", 0, 0, &umr_bitfield_default }, + { "UC_INT_XIRQ_N_PIN", 1, 1, &umr_bitfield_default }, + { "UC_INT_SOFTWARE_INTERRUPT", 2, 2, &umr_bitfield_default }, + { "UC_INT_ILLEGAL_OPCODE_TRAP", 3, 3, &umr_bitfield_default }, + { "UC_INT_TIMER_OUTPUT_COMPARE_4", 4, 4, &umr_bitfield_default }, + { "UC_INT_TIMER_OUTPUT_COMPARE_3", 5, 5, &umr_bitfield_default }, + { "UC_INT_TIMER_OUTPUT_COMPARE_2", 6, 6, &umr_bitfield_default }, + { "UC_INT_TIMER_OUTPUT_COMPARE_1", 7, 7, &umr_bitfield_default }, + { "UC_INT_TIMER_OVERFLOW", 8, 8, &umr_bitfield_default }, + { "UC_INT_REAL_TIME_INTERRUPT", 9, 9, &umr_bitfield_default }, + { "UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5", 10, 10, &umr_bitfield_default }, + { "UC_INT_TIMER_INPUT_CAPTURE_3", 11, 11, &umr_bitfield_default }, + { "UC_INT_TIMER_INPUT_CAPTURE_2", 12, 12, &umr_bitfield_default }, + { "UC_INT_TIMER_INPUT_CAPTURE_1", 13, 13, &umr_bitfield_default }, + { "UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE", 14, 14, &umr_bitfield_default }, + { "UC_INT_PULSE_ACCUMULATOR_OVERFLOW", 15, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDMCU_SS_INTERRUPT_CNTL_STATUS[] = { + { "STATIC_SCREEN1_INT_STATUS", 13, 13, &umr_bitfield_default }, + { "STATIC_SCREEN1_INT_OCCURRED", 14, 14, &umr_bitfield_default }, + { "STATIC_SCREEN1_INT_CLEAR", 14, 14, &umr_bitfield_default }, + { "STATIC_SCREEN2_INT_STATUS", 15, 15, &umr_bitfield_default }, + { "STATIC_SCREEN2_INT_OCCURRED", 16, 16, &umr_bitfield_default }, + { "STATIC_SCREEN2_INT_CLEAR", 16, 16, &umr_bitfield_default }, + { "STATIC_SCREEN3_INT_STATUS", 17, 17, &umr_bitfield_default }, + { "STATIC_SCREEN3_INT_OCCURRED", 18, 18, &umr_bitfield_default }, + { "STATIC_SCREEN3_INT_CLEAR", 18, 18, &umr_bitfield_default }, + { "STATIC_SCREEN4_INT_STATUS", 19, 19, &umr_bitfield_default }, + { "STATIC_SCREEN4_INT_OCCURRED", 20, 20, &umr_bitfield_default }, + { "STATIC_SCREEN4_INT_CLEAR", 20, 20, &umr_bitfield_default }, + { "STATIC_SCREEN5_INT_STATUS", 21, 21, &umr_bitfield_default }, + { "STATIC_SCREEN5_INT_OCCURRED", 22, 22, &umr_bitfield_default }, + { "STATIC_SCREEN5_INT_CLEAR", 22, 22, &umr_bitfield_default }, + { "STATIC_SCREEN6_INT_STATUS", 23, 23, &umr_bitfield_default }, + { "STATIC_SCREEN6_INT_OCCURRED", 24, 24, &umr_bitfield_default }, + { "STATIC_SCREEN6_INT_CLEAR", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDMCU_INTERRUPT_STATUS[] = { + { "ABM1_HG_READY_INT_OCCURRED", 0, 0, &umr_bitfield_default }, + { "ABM1_HG_READY_INT_CLEAR", 0, 0, &umr_bitfield_default }, + { "ABM1_LS_READY_INT_OCCURRED", 1, 1, &umr_bitfield_default }, + { "ABM1_LS_READY_INT_CLEAR", 1, 1, &umr_bitfield_default }, + { "ABM1_BL_UPDATE_INT_OCCURRED", 2, 2, &umr_bitfield_default }, + { "ABM1_BL_UPDATE_INT_CLEAR", 2, 2, &umr_bitfield_default }, + { "MCP_INT_OCCURRED", 3, 3, &umr_bitfield_default }, + { "EXTERNAL_SW_INT_OCCURRED", 8, 8, &umr_bitfield_default }, + { "EXTERNAL_SW_INT_CLEAR", 8, 8, &umr_bitfield_default }, + { "SCP_INT_OCCURRED", 9, 9, &umr_bitfield_default }, + { "UC_INTERNAL_INT_OCCURRED", 10, 10, &umr_bitfield_default }, + { "UC_INTERNAL_INT_CLEAR", 10, 10, &umr_bitfield_default }, + { "UC_REG_RD_TIMEOUT_INT_OCCURRED", 11, 11, &umr_bitfield_default }, + { "UC_REG_RD_TIMEOUT_INT_CLEAR", 11, 11, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN0_POWER_UP_INT_OCCURRED", 12, 12, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN0_POWER_UP_INT_CLEAR", 12, 12, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN1_POWER_UP_INT_OCCURRED", 13, 13, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN1_POWER_UP_INT_CLEAR", 13, 13, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN2_POWER_UP_INT_OCCURRED", 14, 14, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN2_POWER_UP_INT_CLEAR", 14, 14, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN3_POWER_UP_INT_OCCURRED", 15, 15, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN3_POWER_UP_INT_CLEAR", 15, 15, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN4_POWER_UP_INT_OCCURRED", 16, 16, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN4_POWER_UP_INT_CLEAR", 16, 16, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN5_POWER_UP_INT_OCCURRED", 17, 17, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN5_POWER_UP_INT_CLEAR", 17, 17, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN0_POWER_DOWN_INT_OCCURRED", 18, 18, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN0_POWER_DOWN_INT_CLEAR", 18, 18, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN1_POWER_DOWN_INT_OCCURRED", 19, 19, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN1_POWER_DOWN_INT_CLEAR", 19, 19, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN2_POWER_DOWN_INT_OCCURRED", 20, 20, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN2_POWER_DOWN_INT_CLEAR", 20, 20, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN3_POWER_DOWN_INT_OCCURRED", 21, 21, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN3_POWER_DOWN_INT_CLEAR", 21, 21, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN4_POWER_DOWN_INT_OCCURRED", 22, 22, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN4_POWER_DOWN_INT_CLEAR", 22, 22, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN5_POWER_DOWN_INT_OCCURRED", 23, 23, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN5_POWER_DOWN_INT_CLEAR", 23, 23, &umr_bitfield_default }, + { "VBLANK1_INT_OCCURRED", 24, 24, &umr_bitfield_default }, + { "VBLANK1_INT_CLEAR", 24, 24, &umr_bitfield_default }, + { "VBLANK2_INT_OCCURRED", 25, 25, &umr_bitfield_default }, + { "VBLANK2_INT_CLEAR", 25, 25, &umr_bitfield_default }, + { "VBLANK3_INT_OCCURRED", 26, 26, &umr_bitfield_default }, + { "VBLANK3_INT_CLEAR", 26, 26, &umr_bitfield_default }, + { "VBLANK4_INT_OCCURRED", 27, 27, &umr_bitfield_default }, + { "VBLANK4_INT_CLEAR", 27, 27, &umr_bitfield_default }, + { "VBLANK5_INT_OCCURRED", 28, 28, &umr_bitfield_default }, + { "VBLANK5_INT_CLEAR", 28, 28, &umr_bitfield_default }, + { "VBLANK6_INT_OCCURRED", 29, 29, &umr_bitfield_default }, + { "VBLANK6_INT_CLEAR", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDMCU_INTERRUPT_STATUS_1[] = { + { "OTG0_RANGE_TIMING_UPDATE_OCCURRED", 6, 6, &umr_bitfield_default }, + { "OTG0_RANGE_TIMING_UPDATE_CLEAR", 6, 6, &umr_bitfield_default }, + { "OTG1_RANGE_TIMING_UPDATE_OCCURRED", 7, 7, &umr_bitfield_default }, + { "OTG1_RANGE_TIMING_UPDATE_CLEAR", 7, 7, &umr_bitfield_default }, + { "OTG2_RANGE_TIMING_UPDATE_OCCURRED", 8, 8, &umr_bitfield_default }, + { "OTG2_RANGE_TIMING_UPDATE_CLEAR", 8, 8, &umr_bitfield_default }, + { "OTG3_RANGE_TIMING_UPDATE_OCCURRED", 9, 9, &umr_bitfield_default }, + { "OTG3_RANGE_TIMING_UPDATE_CLEAR", 9, 9, &umr_bitfield_default }, + { "OTG4_RANGE_TIMING_UPDATE_OCCURRED", 10, 10, &umr_bitfield_default }, + { "OTG4_RANGE_TIMING_UPDATE_CLEAR", 10, 10, &umr_bitfield_default }, + { "OTG5_RANGE_TIMING_UPDATE_OCCURRED", 11, 11, &umr_bitfield_default }, + { "OTG5_RANGE_TIMING_UPDATE_CLEAR", 11, 11, &umr_bitfield_default }, + { "DMCU_GENERIC_INTERRUPT_OCCURRED", 13, 13, &umr_bitfield_default }, + { "DMCU_GENERIC_INTERRUPT_CLEAR", 13, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDMCU_INTERRUPT_TO_HOST_EN_MASK[] = { + { "ABM0_HG_READY_INT_MASK", 0, 0, &umr_bitfield_default }, + { "ABM0_LS_READY_INT_MASK", 1, 1, &umr_bitfield_default }, + { "ABM0_BL_UPDATE_INT_MASK", 2, 2, &umr_bitfield_default }, + { "ABM1_HG_READY_INT_MASK", 3, 3, &umr_bitfield_default }, + { "ABM1_LS_READY_INT_MASK", 4, 4, &umr_bitfield_default }, + { "ABM1_BL_UPDATE_INT_MASK", 5, 5, &umr_bitfield_default }, + { "SCP_INT_MASK", 9, 9, &umr_bitfield_default }, + { "UC_INTERNAL_INT_MASK", 10, 10, &umr_bitfield_default }, + { "UC_REG_RD_TIMEOUT_INT_MASK", 11, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDMCU_INTERRUPT_TO_UC_EN_MASK[] = { + { "ABM1_HG_READY_INT_TO_UC_EN", 0, 0, &umr_bitfield_default }, + { "ABM1_LS_READY_INT_TO_UC_EN", 1, 1, &umr_bitfield_default }, + { "ABM1_BL_UPDATE_INT_TO_UC_EN", 2, 2, &umr_bitfield_default }, + { "MCP_INT_TO_UC_EN", 3, 3, &umr_bitfield_default }, + { "STATIC_SCREEN1_INT_TO_UC_EN", 6, 6, &umr_bitfield_default }, + { "STATIC_SCREEN2_INT_TO_UC_EN", 7, 7, &umr_bitfield_default }, + { "EXTERNAL_SW_INT_TO_UC_EN", 8, 8, &umr_bitfield_default }, + { "STATIC_SCREEN3_INT_TO_UC_EN", 9, 9, &umr_bitfield_default }, + { "STATIC_SCREEN4_INT_TO_UC_EN", 10, 10, &umr_bitfield_default }, + { "STATIC_SCREEN5_INT_TO_UC_EN", 11, 11, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN0_POWER_UP_INT_TO_UC_EN", 12, 12, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN1_POWER_UP_INT_TO_UC_EN", 13, 13, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN2_POWER_UP_INT_TO_UC_EN", 14, 14, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN3_POWER_UP_INT_TO_UC_EN", 15, 15, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN4_POWER_UP_INT_TO_UC_EN", 16, 16, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN5_POWER_UP_INT_TO_UC_EN", 17, 17, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN0_POWER_DOWN_INT_TO_UC_EN", 18, 18, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN1_POWER_DOWN_INT_TO_UC_EN", 19, 19, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN2_POWER_DOWN_INT_TO_UC_EN", 20, 20, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN3_POWER_DOWN_INT_TO_UC_EN", 21, 21, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN4_POWER_DOWN_INT_TO_UC_EN", 22, 22, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN5_POWER_DOWN_INT_TO_UC_EN", 23, 23, &umr_bitfield_default }, + { "VBLANK1_INT_TO_UC_EN", 24, 24, &umr_bitfield_default }, + { "VBLANK2_INT_TO_UC_EN", 25, 25, &umr_bitfield_default }, + { "VBLANK3_INT_TO_UC_EN", 26, 26, &umr_bitfield_default }, + { "VBLANK4_INT_TO_UC_EN", 27, 27, &umr_bitfield_default }, + { "VBLANK5_INT_TO_UC_EN", 28, 28, &umr_bitfield_default }, + { "VBLANK6_INT_TO_UC_EN", 29, 29, &umr_bitfield_default }, + { "STATIC_SCREEN6_INT_TO_UC_EN", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDMCU_INTERRUPT_TO_UC_EN_MASK_1[] = { + { "OTG0_RANGE_TIMING_UPDATE_INT_TO_UC_EN", 6, 6, &umr_bitfield_default }, + { "OTG1_RANGE_TIMING_UPDATE_INT_TO_UC_EN", 7, 7, &umr_bitfield_default }, + { "OTG2_RANGE_TIMING_UPDATE_INT_TO_UC_EN", 8, 8, &umr_bitfield_default }, + { "OTG3_RANGE_TIMING_UPDATE_INT_TO_UC_EN", 9, 9, &umr_bitfield_default }, + { "OTG4_RANGE_TIMING_UPDATE_INT_TO_UC_EN", 10, 10, &umr_bitfield_default }, + { "OTG5_RANGE_TIMING_UPDATE_INT_TO_UC_EN", 11, 11, &umr_bitfield_default }, + { "DMCU_GENERIC_INT_TO_UC_EN", 13, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL[] = { + { "ABM1_HG_READY_INT_XIRQ_IRQ_SEL", 0, 0, &umr_bitfield_default }, + { "ABM1_LS_READY_INT_XIRQ_IRQ_SEL", 1, 1, &umr_bitfield_default }, + { "ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL", 2, 2, &umr_bitfield_default }, + { "MCP_INT_XIRQ_IRQ_SEL", 3, 3, &umr_bitfield_default }, + { "STATIC_SCREEN1_INT_XIRQ_IRQ_SEL", 6, 6, &umr_bitfield_default }, + { "STATIC_SCREEN2_INT_XIRQ_IRQ_SEL", 7, 7, &umr_bitfield_default }, + { "EXTERNAL_SW_INT_XIRQ_IRQ_SEL", 8, 8, &umr_bitfield_default }, + { "STATIC_SCREEN3_INT_XIRQ_IRQ_SEL", 9, 9, &umr_bitfield_default }, + { "STATIC_SCREEN4_INT_XIRQ_IRQ_SEL", 10, 10, &umr_bitfield_default }, + { "STATIC_SCREEN5_INT_XIRQ_IRQ_SEL", 11, 11, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN0_POWER_UP_INT_XIRQ_IRQ_SEL", 12, 12, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN1_POWER_UP_INT_XIRQ_IRQ_SEL", 13, 13, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN2_POWER_UP_INT_XIRQ_IRQ_SEL", 14, 14, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN3_POWER_UP_INT_XIRQ_IRQ_SEL", 15, 15, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN4_POWER_UP_INT_XIRQ_IRQ_SEL", 16, 16, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN5_POWER_UP_INT_XIRQ_IRQ_SEL", 17, 17, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN0_POWER_DOWN_INT_XIRQ_IRQ_SEL", 18, 18, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN1_POWER_DOWN_INT_XIRQ_IRQ_SEL", 19, 19, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN2_POWER_DOWN_INT_XIRQ_IRQ_SEL", 20, 20, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN3_POWER_DOWN_INT_XIRQ_IRQ_SEL", 21, 21, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN4_POWER_DOWN_INT_XIRQ_IRQ_SEL", 22, 22, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN5_POWER_DOWN_INT_XIRQ_IRQ_SEL", 23, 23, &umr_bitfield_default }, + { "VBLANK1_INT_XIRQ_IRQ_SEL", 24, 24, &umr_bitfield_default }, + { "VBLANK2_INT_XIRQ_IRQ_SEL", 25, 25, &umr_bitfield_default }, + { "VBLANK3_INT_XIRQ_IRQ_SEL", 26, 26, &umr_bitfield_default }, + { "VBLANK4_INT_XIRQ_IRQ_SEL", 27, 27, &umr_bitfield_default }, + { "VBLANK5_INT_XIRQ_IRQ_SEL", 28, 28, &umr_bitfield_default }, + { "VBLANK6_INT_XIRQ_IRQ_SEL", 29, 29, &umr_bitfield_default }, + { "STATIC_SCREEN6_INT_XIRQ_IRQ_SEL", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1[] = { + { "OTG0_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL", 6, 6, &umr_bitfield_default }, + { "OTG1_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL", 7, 7, &umr_bitfield_default }, + { "OTG2_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL", 8, 8, &umr_bitfield_default }, + { "OTG3_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL", 9, 9, &umr_bitfield_default }, + { "OTG4_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL", 10, 10, &umr_bitfield_default }, + { "OTG5_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL", 11, 11, &umr_bitfield_default }, + { "DMCU_GENERIC_INT_XIRQ_IRQ_SEL", 13, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_DMCU_SCRATCH[] = { + { "DMCU_SCRATCH", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDMCU_INT_CNT[] = { + { "DMCU_ABM1_HG_READY_INT_CNT", 0, 7, &umr_bitfield_default }, + { "DMCU_ABM1_LS_READY_INT_CNT", 8, 15, &umr_bitfield_default }, + { "DMCU_ABM1_BL_UPDATE_INT_CNT", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS[] = { + { "DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS", 0, 1, &umr_bitfield_default }, + { "DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS", 2, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDMCU_UC_CLK_GATING_CNTL[] = { + { "UC_IRAM_RD_DELAY", 0, 2, &umr_bitfield_default }, + { "UC_ERAM_RD_DELAY", 8, 10, &umr_bitfield_default }, + { "UC_RBBM_RD_CLK_GATING_EN", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMASTER_COMM_DATA_REG1[] = { + { "MASTER_COMM_DATA_REG1_BYTE0", 0, 7, &umr_bitfield_default }, + { "MASTER_COMM_DATA_REG1_BYTE1", 8, 15, &umr_bitfield_default }, + { "MASTER_COMM_DATA_REG1_BYTE2", 16, 23, &umr_bitfield_default }, + { "MASTER_COMM_DATA_REG1_BYTE3", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMASTER_COMM_DATA_REG2[] = { + { "MASTER_COMM_DATA_REG2_BYTE0", 0, 7, &umr_bitfield_default }, + { "MASTER_COMM_DATA_REG2_BYTE1", 8, 15, &umr_bitfield_default }, + { "MASTER_COMM_DATA_REG2_BYTE2", 16, 23, &umr_bitfield_default }, + { "MASTER_COMM_DATA_REG2_BYTE3", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMASTER_COMM_DATA_REG3[] = { + { "MASTER_COMM_DATA_REG3_BYTE0", 0, 7, &umr_bitfield_default }, + { "MASTER_COMM_DATA_REG3_BYTE1", 8, 15, &umr_bitfield_default }, + { "MASTER_COMM_DATA_REG3_BYTE2", 16, 23, &umr_bitfield_default }, + { "MASTER_COMM_DATA_REG3_BYTE3", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMASTER_COMM_CMD_REG[] = { + { "MASTER_COMM_CMD_REG_BYTE0", 0, 7, &umr_bitfield_default }, + { "MASTER_COMM_CMD_REG_BYTE1", 8, 15, &umr_bitfield_default }, + { "MASTER_COMM_CMD_REG_BYTE2", 16, 23, &umr_bitfield_default }, + { "MASTER_COMM_CMD_REG_BYTE3", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMASTER_COMM_CNTL_REG[] = { + { "MASTER_COMM_INTERRUPT", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSLAVE_COMM_DATA_REG1[] = { + { "SLAVE_COMM_DATA_REG1_BYTE0", 0, 7, &umr_bitfield_default }, + { "SLAVE_COMM_DATA_REG1_BYTE1", 8, 15, &umr_bitfield_default }, + { "SLAVE_COMM_DATA_REG1_BYTE2", 16, 23, &umr_bitfield_default }, + { "SLAVE_COMM_DATA_REG1_BYTE3", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSLAVE_COMM_DATA_REG2[] = { + { "SLAVE_COMM_DATA_REG2_BYTE0", 0, 7, &umr_bitfield_default }, + { "SLAVE_COMM_DATA_REG2_BYTE1", 8, 15, &umr_bitfield_default }, + { "SLAVE_COMM_DATA_REG2_BYTE2", 16, 23, &umr_bitfield_default }, + { "SLAVE_COMM_DATA_REG2_BYTE3", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSLAVE_COMM_DATA_REG3[] = { + { "SLAVE_COMM_DATA_REG3_BYTE0", 0, 7, &umr_bitfield_default }, + { "SLAVE_COMM_DATA_REG3_BYTE1", 8, 15, &umr_bitfield_default }, + { "SLAVE_COMM_DATA_REG3_BYTE2", 16, 23, &umr_bitfield_default }, + { "SLAVE_COMM_DATA_REG3_BYTE3", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSLAVE_COMM_CMD_REG[] = { + { "SLAVE_COMM_CMD_REG_BYTE0", 0, 7, &umr_bitfield_default }, + { "SLAVE_COMM_CMD_REG_BYTE1", 8, 15, &umr_bitfield_default }, + { "SLAVE_COMM_CMD_REG_BYTE2", 16, 23, &umr_bitfield_default }, + { "SLAVE_COMM_CMD_REG_BYTE3", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSLAVE_COMM_CNTL_REG[] = { + { "SLAVE_COMM_INTERRUPT", 0, 0, &umr_bitfield_default }, + { "COMM_PORT_MSG_TO_HOST_IN_PROGRESS", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_STATUS1[] = { + { "DMU_PERFMON_COUNTER_INT_OCCURRED", 0, 0, &umr_bitfield_default }, + { "DMU_PERFMON_COUNTER_INT_CLEAR", 0, 0, &umr_bitfield_default }, + { "DIO_PERFMON_COUNTER_INT_OCCURRED", 1, 1, &umr_bitfield_default }, + { "DIO_PERFMON_COUNTER_INT_CLEAR", 1, 1, &umr_bitfield_default }, + { "DCCG_PERFMON_COUNTER_INT_OCCURRED", 2, 2, &umr_bitfield_default }, + { "DCCG_PERFMON_COUNTER_INT_CLEAR", 2, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_STATUS2[] = { + { "HUBP0_PERFMON_COUNTER_INT_OCCURRED", 0, 0, &umr_bitfield_default }, + { "HUBP0_PERFMON_COUNTER_INT_CLEAR", 0, 0, &umr_bitfield_default }, + { "HUBP1_PERFMON_COUNTER_INT_OCCURRED", 1, 1, &umr_bitfield_default }, + { "HUBP1_PERFMON_COUNTER_INT_CLEAR", 1, 1, &umr_bitfield_default }, + { "HUBP2_PERFMON_COUNTER_INT_OCCURRED", 2, 2, &umr_bitfield_default }, + { "HUBP2_PERFMON_COUNTER_INT_CLEAR", 2, 2, &umr_bitfield_default }, + { "HUBP3_PERFMON_COUNTER_INT_OCCURRED", 3, 3, &umr_bitfield_default }, + { "HUBP3_PERFMON_COUNTER_INT_CLEAR", 3, 3, &umr_bitfield_default }, + { "HUBP4_PERFMON_COUNTER_INT_OCCURRED", 4, 4, &umr_bitfield_default }, + { "HUBP4_PERFMON_COUNTER_INT_CLEAR", 4, 4, &umr_bitfield_default }, + { "HUBP5_PERFMON_COUNTER_INT_OCCURRED", 5, 5, &umr_bitfield_default }, + { "HUBP5_PERFMON_COUNTER_INT_CLEAR", 5, 5, &umr_bitfield_default }, + { "HUBP6_PERFMON_COUNTER_INT_OCCURRED", 6, 6, &umr_bitfield_default }, + { "HUBP6_PERFMON_COUNTER_INT_CLEAR", 6, 6, &umr_bitfield_default }, + { "HUBP7_PERFMON_COUNTER_INT_OCCURRED", 7, 7, &umr_bitfield_default }, + { "HUBP7_PERFMON_COUNTER_INT_CLEAR", 7, 7, &umr_bitfield_default }, + { "HUBBUB_PERFMON_COUNTER_INT_OCCURRED", 8, 8, &umr_bitfield_default }, + { "HUBBUB_PERFMON_COUNTER_INT_CLEAR", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_STATUS3[] = { + { "DPP0_PERFMON_COUNTER_INT_OCCURRED", 0, 0, &umr_bitfield_default }, + { "DPP0_PERFMON_COUNTER_INT_CLEAR", 0, 0, &umr_bitfield_default }, + { "DPP1_PERFMON_COUNTER_INT_OCCURRED", 1, 1, &umr_bitfield_default }, + { "DPP1_PERFMON_COUNTER_INT_CLEAR", 1, 1, &umr_bitfield_default }, + { "DPP2_PERFMON_COUNTER_INT_OCCURRED", 2, 2, &umr_bitfield_default }, + { "DPP2_PERFMON_COUNTER_INT_CLEAR", 2, 2, &umr_bitfield_default }, + { "DPP3_PERFMON_COUNTER_INT_OCCURRED", 3, 3, &umr_bitfield_default }, + { "DPP3_PERFMON_COUNTER_INT_CLEAR", 3, 3, &umr_bitfield_default }, + { "DPP4_PERFMON_COUNTER_INT_OCCURRED", 4, 4, &umr_bitfield_default }, + { "DPP4_PERFMON_COUNTER_INT_CLEAR", 4, 4, &umr_bitfield_default }, + { "DPP5_PERFMON_COUNTER_INT_OCCURRED", 5, 5, &umr_bitfield_default }, + { "DPP5_PERFMON_COUNTER_INT_CLEAR", 5, 5, &umr_bitfield_default }, + { "DPP6_PERFMON_COUNTER_INT_OCCURRED", 6, 6, &umr_bitfield_default }, + { "DPP6_PERFMON_COUNTER_INT_CLEAR", 6, 6, &umr_bitfield_default }, + { "DPP7_PERFMON_COUNTER_INT_OCCURRED", 7, 7, &umr_bitfield_default }, + { "DPP7_PERFMON_COUNTER_INT_CLEAR", 7, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_STATUS4[] = { + { "WB0_PERFMON_COUNTER_INT_OCCURRED", 0, 0, &umr_bitfield_default }, + { "WB0_PERFMON_COUNTER_INT_CLEAR", 0, 0, &umr_bitfield_default }, + { "WB1_PERFMON_COUNTER_INT_OCCURRED", 1, 1, &umr_bitfield_default }, + { "WB1_PERFMON_COUNTER_INT_CLEAR", 1, 1, &umr_bitfield_default }, + { "DCCG_PERFMON2_COUNTER_INT_OCCURRED", 2, 2, &umr_bitfield_default }, + { "DCCG_PERFMON2_COUNTER_INT_CLEAR", 2, 2, &umr_bitfield_default }, + { "MMHUBBUB_PERFMON_COUNTER_INT_OCCURRED", 3, 3, &umr_bitfield_default }, + { "MMHUBBUB_PERFMON_COUNTER_INT_CLEAR", 3, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_STATUS5[] = { + { "MPC_PERFMON_COUNTER_INT_OCCURRED", 0, 0, &umr_bitfield_default }, + { "MPC_PERFMON_COUNTER_INT_CLEAR", 0, 0, &umr_bitfield_default }, + { "OPP_PERFMON_COUNTER_INT_OCCURRED", 1, 1, &umr_bitfield_default }, + { "OPP_PERFMON_COUNTER_INT_CLEAR", 1, 1, &umr_bitfield_default }, + { "OPTC_PERFMON_COUNTER_INT_OCCURRED", 2, 2, &umr_bitfield_default }, + { "OPTC_PERFMON_COUNTER_INT_CLEAR", 2, 2, &umr_bitfield_default }, + { "HDA_PERFMON_COUNTER_INT_OCCURRED", 3, 3, &umr_bitfield_default }, + { "HDA_PERFMON_COUNTER_INT_CLEAR", 3, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1[] = { + { "DMU_PERFMON_COUNTER_INT_TO_UC_EN", 0, 0, &umr_bitfield_default }, + { "DIO_PERFMON_COUNTER_INT_TO_UC_EN", 1, 1, &umr_bitfield_default }, + { "DCCG_PERFMON_COUNTER_INT_TO_UC_EN", 2, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2[] = { + { "HUBP0_PERFMON_COUNTER_INT_TO_UC_EN", 0, 0, &umr_bitfield_default }, + { "HUBP1_PERFMON_COUNTER_INT_TO_UC_EN", 1, 1, &umr_bitfield_default }, + { "HUBP2_PERFMON_COUNTER_INT_TO_UC_EN", 2, 2, &umr_bitfield_default }, + { "HUBP3_PERFMON_COUNTER_INT_TO_UC_EN", 3, 3, &umr_bitfield_default }, + { "HUBP4_PERFMON_COUNTER_INT_TO_UC_EN", 4, 4, &umr_bitfield_default }, + { "HUBP5_PERFMON_COUNTER_INT_TO_UC_EN", 5, 5, &umr_bitfield_default }, + { "HUBP6_PERFMON_COUNTER_INT_TO_UC_EN", 6, 6, &umr_bitfield_default }, + { "HUBP7_PERFMON_COUNTER_INT_TO_UC_EN", 7, 7, &umr_bitfield_default }, + { "HUBBUB_PERFMON_COUNTER_INT_TO_UC_EN", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3[] = { + { "DPP0_PERFMON_COUNTER_INT_TO_UC_EN", 0, 0, &umr_bitfield_default }, + { "DPP1_PERFMON_COUNTER_INT_TO_UC_EN", 1, 1, &umr_bitfield_default }, + { "DPP2_PERFMON_COUNTER_INT_TO_UC_EN", 2, 2, &umr_bitfield_default }, + { "DPP3_PERFMON_COUNTER_INT_TO_UC_EN", 3, 3, &umr_bitfield_default }, + { "DPP4_PERFMON_COUNTER_INT_TO_UC_EN", 4, 4, &umr_bitfield_default }, + { "DPP5_PERFMON_COUNTER_INT_TO_UC_EN", 5, 5, &umr_bitfield_default }, + { "DPP6_PERFMON_COUNTER_INT_TO_UC_EN", 6, 6, &umr_bitfield_default }, + { "DPP7_PERFMON_COUNTER_INT_TO_UC_EN", 7, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4[] = { + { "WB0_PERFMON_COUNTER_INT_TO_UC_EN", 0, 0, &umr_bitfield_default }, + { "WB1_PERFMON_COUNTER_INT_TO_UC_EN", 1, 1, &umr_bitfield_default }, + { "DCCG_PERFMON2_COUNTER_INT_TO_UC_EN", 2, 2, &umr_bitfield_default }, + { "MMHUBBUB_PERFMON_COUNTER_INT_TO_UC_EN", 3, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5[] = { + { "MPC_PERFMON_COUNTER_INT_TO_UC_EN", 0, 0, &umr_bitfield_default }, + { "OPP_PERFMON_COUNTER_INT_TO_UC_EN", 1, 1, &umr_bitfield_default }, + { "OPTC_PERFMON_COUNTER_INT_TO_UC_EN", 2, 2, &umr_bitfield_default }, + { "HDA_PERFMON_COUNTER_INT_TO_UC_EN", 3, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1[] = { + { "DMU_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL", 0, 0, &umr_bitfield_default }, + { "DIO_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL", 1, 1, &umr_bitfield_default }, + { "DCCG_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL", 2, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2[] = { + { "HUBP0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL", 0, 0, &umr_bitfield_default }, + { "HUBP1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL", 1, 1, &umr_bitfield_default }, + { "HUBP2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL", 2, 2, &umr_bitfield_default }, + { "HUBP3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL", 3, 3, &umr_bitfield_default }, + { "HUBP4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL", 4, 4, &umr_bitfield_default }, + { "HUBP5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL", 5, 5, &umr_bitfield_default }, + { "HUBP6_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL", 6, 6, &umr_bitfield_default }, + { "HUBP7_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL", 7, 7, &umr_bitfield_default }, + { "HUBBUB_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3[] = { + { "DPP0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL", 0, 0, &umr_bitfield_default }, + { "DPP1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL", 1, 1, &umr_bitfield_default }, + { "DPP2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL", 2, 2, &umr_bitfield_default }, + { "DPP3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL", 3, 3, &umr_bitfield_default }, + { "DPP4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL", 4, 4, &umr_bitfield_default }, + { "DPP5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL", 5, 5, &umr_bitfield_default }, + { "DPP6_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL", 6, 6, &umr_bitfield_default }, + { "DPP7_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL", 7, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4[] = { + { "WB0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL", 0, 0, &umr_bitfield_default }, + { "WB1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL", 1, 1, &umr_bitfield_default }, + { "DCCG_PERFMON2_COUNTER_INT_XIRQ_IRQ_SEL", 2, 2, &umr_bitfield_default }, + { "MMHUBBUB_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL", 3, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5[] = { + { "MPC_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL", 0, 0, &umr_bitfield_default }, + { "OPTC_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL", 1, 1, &umr_bitfield_default }, + { "OPP_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL", 2, 2, &umr_bitfield_default }, + { "HDA_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL", 3, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDMCU_DPRX_INTERRUPT_STATUS1[] = { + { "DPRX_SD0P0_MSA_RECEIVED_INT_OCCURRED", 0, 0, &umr_bitfield_default }, + { "DPRX_SD0P0_MSA_RECEIVED_INT_CLEAR", 0, 0, &umr_bitfield_default }, + { "DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED", 1, 1, &umr_bitfield_default }, + { "DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR", 1, 1, &umr_bitfield_default }, + { "DPRX_SD0P0_VERTICAL_INT0_OCCURRED", 2, 2, &umr_bitfield_default }, + { "DPRX_SD0P0_VERTICAL_INT0_CLEAR", 2, 2, &umr_bitfield_default }, + { "DPRX_SD0P0_VERTICAL_INT1_OCCURRED", 3, 3, &umr_bitfield_default }, + { "DPRX_SD0P0_VERTICAL_INT1_CLEAR", 3, 3, &umr_bitfield_default }, + { "DPRX_SD0P0_SDP_RECEIVED_INT_OCCURRED", 4, 4, &umr_bitfield_default }, + { "DPRX_SD0P0_SDP_RECEIVED_INT_CLEAR", 4, 4, &umr_bitfield_default }, + { "DPRX_SD1P0_MSA_RECEIVED_INT_OCCURRED", 5, 5, &umr_bitfield_default }, + { "DPRX_SD1P0_MSA_RECEIVED_INT_CLEAR", 5, 5, &umr_bitfield_default }, + { "DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED", 6, 6, &umr_bitfield_default }, + { "DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR", 6, 6, &umr_bitfield_default }, + { "DPRX_SD1P0_VERTICAL_INT0_OCCURRED", 7, 7, &umr_bitfield_default }, + { "DPRX_SD1P0_VERTICAL_INT0_CLEAR", 7, 7, &umr_bitfield_default }, + { "DPRX_SD1P0_VERTICAL_INT1_OCCURRED", 8, 8, &umr_bitfield_default }, + { "DPRX_SD1P0_VERTICAL_INT1_CLEAR", 8, 8, &umr_bitfield_default }, + { "DPRX_SD1P0_SDP_RECEIVED_INT_OCCURRED", 9, 9, &umr_bitfield_default }, + { "DPRX_SD1P0_SDP_RECEIVED_INT_CLEAR", 9, 9, &umr_bitfield_default }, + { "DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED", 10, 10, &umr_bitfield_default }, + { "DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR", 10, 10, &umr_bitfield_default }, + { "DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED", 11, 11, &umr_bitfield_default }, + { "DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR", 11, 11, &umr_bitfield_default }, + { "DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_OCCURRED", 12, 12, &umr_bitfield_default }, + { "DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_CLEAR", 12, 12, &umr_bitfield_default }, + { "DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_OCCURRED", 13, 13, &umr_bitfield_default }, + { "DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_CLEAR", 13, 13, &umr_bitfield_default }, + { "DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_OCCURRED", 14, 14, &umr_bitfield_default }, + { "DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_CLEAR", 14, 14, &umr_bitfield_default }, + { "DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_OCCURRED", 15, 15, &umr_bitfield_default }, + { "DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_CLEAR", 15, 15, &umr_bitfield_default }, + { "DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_OCCURRED", 16, 16, &umr_bitfield_default }, + { "DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_CLEAR", 16, 16, &umr_bitfield_default }, + { "DPRX_DPHY_P0_DETECT_SR_LOCK_INT_OCCURRED", 17, 17, &umr_bitfield_default }, + { "DPRX_DPHY_P0_DETECT_SR_LOCK_INT_CLEAR", 17, 17, &umr_bitfield_default }, + { "DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_OCCURRED", 18, 18, &umr_bitfield_default }, + { "DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_CLEAR", 18, 18, &umr_bitfield_default }, + { "DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_OCCURRED", 19, 19, &umr_bitfield_default }, + { "DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_CLEAR", 19, 19, &umr_bitfield_default }, + { "DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_OCCURRED", 20, 20, &umr_bitfield_default }, + { "DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_CLEAR", 20, 20, &umr_bitfield_default }, + { "DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_OCCURRED", 21, 21, &umr_bitfield_default }, + { "DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_CLEAR", 21, 21, &umr_bitfield_default }, + { "DPRX_AUX_P0_AUX_INT_OCCURRED", 22, 22, &umr_bitfield_default }, + { "DPRX_AUX_P0_AUX_INT_CLEAR", 22, 22, &umr_bitfield_default }, + { "DPRX_AUX_P0_I2C_INT_OCCURRED", 23, 23, &umr_bitfield_default }, + { "DPRX_AUX_P0_I2C_INT_CLEAR", 23, 23, &umr_bitfield_default }, + { "DPRX_AUX_P0_CPU_INT_OCCURRED", 24, 24, &umr_bitfield_default }, + { "DPRX_AUX_P0_CPU_INT_CLEAR", 24, 24, &umr_bitfield_default }, + { "DPRX_AUX_P0_MSG1_TIMEOUT_INT_OCCURRED", 25, 25, &umr_bitfield_default }, + { "DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR", 25, 25, &umr_bitfield_default }, + { "DPRX_AUX_P0_MSG2_TIMEOUT_INT_OCCURRED", 26, 26, &umr_bitfield_default }, + { "DPRX_AUX_P0_MSG2_TIMEOUT_INT_CLEAR", 26, 26, &umr_bitfield_default }, + { "DPRX_AUX_P0_MSG3_TIMEOUT_INT_OCCURRED", 27, 27, &umr_bitfield_default }, + { "DPRX_AUX_P0_MSG3_TIMEOUT_INT_CLEAR", 27, 27, &umr_bitfield_default }, + { "DPRX_AUX_P0_MSG4_TIMEOUT_INT_OCCURRED", 28, 28, &umr_bitfield_default }, + { "DPRX_AUX_P0_MSG4_TIMEOUT_INT_CLEAR", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1[] = { + { "DPRX_SD0P0_MSA_RECEIVED_INT_TO_UC_EN", 0, 0, &umr_bitfield_default }, + { "DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN", 1, 1, &umr_bitfield_default }, + { "DPRX_SD0P0_VERTICAL_INT0_TO_UC_EN", 2, 2, &umr_bitfield_default }, + { "DPRX_SD0P0_VERTICAL_INT1_TO_UC_EN", 3, 3, &umr_bitfield_default }, + { "DPRX_SD0P0_SDP_RECEIVED_INT_TO_UC_EN", 4, 4, &umr_bitfield_default }, + { "DPRX_SD1P0_MSA_RECEIVED_INT_TO_UC_EN", 5, 5, &umr_bitfield_default }, + { "DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN", 6, 6, &umr_bitfield_default }, + { "DPRX_SD1P0_VERTICAL_INT0_TO_UC_EN", 7, 7, &umr_bitfield_default }, + { "DPRX_SD1P0_VERTICAL_INT1_TO_UC_EN", 8, 8, &umr_bitfield_default }, + { "DPRX_SD1P0_SDP_RECEIVED_INT_TO_UC_EN", 9, 9, &umr_bitfield_default }, + { "DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN", 10, 10, &umr_bitfield_default }, + { "DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN", 11, 11, &umr_bitfield_default }, + { "DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN", 12, 12, &umr_bitfield_default }, + { "DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN", 13, 13, &umr_bitfield_default }, + { "DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN", 14, 14, &umr_bitfield_default }, + { "DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN", 15, 15, &umr_bitfield_default }, + { "DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN", 16, 16, &umr_bitfield_default }, + { "DPRX_DPHY_P0_DETECT_SR_LOCK_INT_TO_UC_EN", 17, 17, &umr_bitfield_default }, + { "DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_TO_UC_EN", 18, 18, &umr_bitfield_default }, + { "DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_TO_UC_EN", 19, 19, &umr_bitfield_default }, + { "DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_TO_UC_EN", 20, 20, &umr_bitfield_default }, + { "DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_TO_UC_EN", 21, 21, &umr_bitfield_default }, + { "DPRX_AUX_P0_AUX_INT_TO_UC_EN", 22, 22, &umr_bitfield_default }, + { "DPRX_AUX_P0_I2C_INT_TO_UC_EN", 23, 23, &umr_bitfield_default }, + { "DPRX_AUX_P0_CPU_INT_TO_UC_EN", 24, 24, &umr_bitfield_default }, + { "DPRX_AUX_P0_MSG1_TIMEOUT_INT_TO_UC_EN", 25, 25, &umr_bitfield_default }, + { "DPRX_AUX_P0_MSG2_TIMEOUT_INT_TO_UC_EN", 26, 26, &umr_bitfield_default }, + { "DPRX_AUX_P0_MSG3_TIMEOUT_INT_TO_UC_EN", 27, 27, &umr_bitfield_default }, + { "DPRX_AUX_P0_MSG4_TIMEOUT_INT_TO_UC_EN", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1[] = { + { "DPRX_SD0P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL", 0, 0, &umr_bitfield_default }, + { "DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL", 1, 1, &umr_bitfield_default }, + { "DPRX_SD0P0_VERTICAL_INT0_XIRQ_IRQ_SEL", 2, 2, &umr_bitfield_default }, + { "DPRX_SD0P0_VERTICAL_INT1_XIRQ_IRQ_SEL", 3, 3, &umr_bitfield_default }, + { "DPRX_SD0P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL", 4, 4, &umr_bitfield_default }, + { "DPRX_SD1P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL", 5, 5, &umr_bitfield_default }, + { "DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL", 6, 6, &umr_bitfield_default }, + { "DPRX_SD1P0_VERTICAL_INT0_XIRQ_IRQ_SEL", 7, 7, &umr_bitfield_default }, + { "DPRX_SD1P0_VERTICAL_INT1_XIRQ_IRQ_SEL", 8, 8, &umr_bitfield_default }, + { "DPRX_SD1P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL", 9, 9, &umr_bitfield_default }, + { "DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL", 10, 10, &umr_bitfield_default }, + { "DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL", 11, 11, &umr_bitfield_default }, + { "DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL", 12, 12, &umr_bitfield_default }, + { "DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL", 13, 13, &umr_bitfield_default }, + { "DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL", 14, 14, &umr_bitfield_default }, + { "DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL", 15, 15, &umr_bitfield_default }, + { "DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL", 16, 16, &umr_bitfield_default }, + { "DPRX_DPHY_P0_DETECT_SR_LOCK_INT_XIRQ_IRQ_SEL", 17, 17, &umr_bitfield_default }, + { "DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_XIRQ_IRQ_SEL", 18, 18, &umr_bitfield_default }, + { "DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_XIRQ_IRQ_SEL", 19, 19, &umr_bitfield_default }, + { "DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_XIRQ_IRQ_SEL", 20, 20, &umr_bitfield_default }, + { "DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_XIRQ_IRQ_SEL", 21, 21, &umr_bitfield_default }, + { "DPRX_AUX_P0_AUX_INT_XIRQ_IRQ_SEL", 22, 22, &umr_bitfield_default }, + { "DPRX_AUX_P0_I2C_INT_XIRQ_IRQ_SEL", 23, 23, &umr_bitfield_default }, + { "DPRX_AUX_P0_CPU_INT_XIRQ_IRQ_SEL", 24, 24, &umr_bitfield_default }, + { "DPRX_AUX_P0_MSG1_TIMEOUT_INT_XIRQ_IRQ_SEL", 25, 25, &umr_bitfield_default }, + { "DPRX_AUX_P0_MSG2_TIMEOUT_INT_XIRQ_IRQ_SEL", 26, 26, &umr_bitfield_default }, + { "DPRX_AUX_P0_MSG3_TIMEOUT_INT_XIRQ_IRQ_SEL", 27, 27, &umr_bitfield_default }, + { "DPRX_AUX_P0_MSG4_TIMEOUT_INT_XIRQ_IRQ_SEL", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDMCU_INTERRUPT_STATUS_CONTINUE[] = { + { "DCPG_IHC_DOMAIN6_POWER_UP_INT_OCCURRED", 0, 0, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN6_POWER_UP_INT_CLEAR", 0, 0, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN7_POWER_UP_INT_OCCURRED", 1, 1, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN7_POWER_UP_INT_CLEAR", 1, 1, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN8_POWER_UP_INT_OCCURRED", 2, 2, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN8_POWER_UP_INT_CLEAR", 2, 2, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN9_POWER_UP_INT_OCCURRED", 3, 3, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN9_POWER_UP_INT_CLEAR", 3, 3, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN10_POWER_UP_INT_OCCURRED", 4, 4, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN10_POWER_UP_INT_CLEAR", 4, 4, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN11_POWER_UP_INT_OCCURRED", 5, 5, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN11_POWER_UP_INT_CLEAR", 5, 5, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN12_POWER_UP_INT_OCCURRED", 6, 6, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN12_POWER_UP_INT_CLEAR", 6, 6, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN13_POWER_UP_INT_OCCURRED", 7, 7, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN13_POWER_UP_INT_CLEAR", 7, 7, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN14_POWER_UP_INT_OCCURRED", 8, 8, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN14_POWER_UP_INT_CLEAR", 8, 8, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN15_POWER_UP_INT_OCCURRED", 9, 9, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN15_POWER_UP_INT_CLEAR", 9, 9, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN6_POWER_DOWN_INT_OCCURRED", 10, 10, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN6_POWER_DOWN_INT_CLEAR", 10, 10, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN7_POWER_DOWN_INT_OCCURRED", 11, 11, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN7_POWER_DOWN_INT_CLEAR", 11, 11, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN8_POWER_DOWN_INT_OCCURRED", 12, 12, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN8_POWER_DOWN_INT_CLEAR", 12, 12, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN9_POWER_DOWN_INT_OCCURRED", 13, 13, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN9_POWER_DOWN_INT_CLEAR", 13, 13, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN10_POWER_DOWN_INT_OCCURRED", 14, 14, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN10_POWER_DOWN_INT_CLEAR", 14, 14, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN11_POWER_DOWN_INT_OCCURRED", 15, 15, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN11_POWER_DOWN_INT_CLEAR", 15, 15, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN12_POWER_DOWN_INT_OCCURRED", 16, 16, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN12_POWER_DOWN_INT_CLEAR", 16, 16, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN13_POWER_DOWN_INT_OCCURRED", 17, 17, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN13_POWER_DOWN_INT_CLEAR", 17, 17, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN14_POWER_DOWN_INT_OCCURRED", 18, 18, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN14_POWER_DOWN_INT_CLEAR", 18, 18, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN15_POWER_DOWN_INT_OCCURRED", 19, 19, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN15_POWER_DOWN_INT_CLEAR", 19, 19, &umr_bitfield_default }, + { "DCCG_DMCU_INT_VSYNC_CNT_OTG0_OCCURRED", 20, 20, &umr_bitfield_default }, + { "DCCG_DMCU_INT_VSYNC_CNT_OTG0_CLEAR", 20, 20, &umr_bitfield_default }, + { "DCCG_DMCU_INT_VSYNC_CNT_OTG1_OCCURRED", 21, 21, &umr_bitfield_default }, + { "DCCG_DMCU_INT_VSYNC_CNT_OTG1_CLEAR", 21, 21, &umr_bitfield_default }, + { "DCCG_DMCU_INT_VSYNC_CNT_OTG2_OCCURRED", 22, 22, &umr_bitfield_default }, + { "DCCG_DMCU_INT_VSYNC_CNT_OTG2_CLEAR", 22, 22, &umr_bitfield_default }, + { "DCCG_DMCU_INT_VSYNC_CNT_OTG3_OCCURRED", 23, 23, &umr_bitfield_default }, + { "DCCG_DMCU_INT_VSYNC_CNT_OTG3_CLEAR", 23, 23, &umr_bitfield_default }, + { "DCCG_DMCU_INT_VSYNC_CNT_OTG4_OCCURRED", 24, 24, &umr_bitfield_default }, + { "DCCG_DMCU_INT_VSYNC_CNT_OTG4_CLEAR", 24, 24, &umr_bitfield_default }, + { "DCCG_DMCU_INT_VSYNC_CNT_OTG5_OCCURRED", 25, 25, &umr_bitfield_default }, + { "DCCG_DMCU_INT_VSYNC_CNT_OTG5_CLEAR", 25, 25, &umr_bitfield_default }, + { "ABM0_HG_READY_INT_OCCURRED", 26, 26, &umr_bitfield_default }, + { "ABM0_HG_READY_INT_CLEAR", 26, 26, &umr_bitfield_default }, + { "ABM0_LS_READY_INT_OCCURRED", 27, 27, &umr_bitfield_default }, + { "ABM0_LS_READY_INT_CLEAR", 27, 27, &umr_bitfield_default }, + { "ABM0_BL_UPDATE_INT_OCCURRED", 28, 28, &umr_bitfield_default }, + { "ABM0_BL_UPDATE_INT_CLEAR", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE[] = { + { "DCPG_IHC_DOMAIN6_POWER_UP_INT_TO_UC_EN", 0, 0, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN7_POWER_UP_INT_TO_UC_EN", 1, 1, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN8_POWER_UP_INT_TO_UC_EN", 2, 2, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN9_POWER_UP_INT_TO_UC_EN", 3, 3, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN10_POWER_UP_INT_TO_UC_EN", 4, 4, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN11_POWER_UP_INT_TO_UC_EN", 5, 5, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN12_POWER_UP_INT_TO_UC_EN", 6, 6, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN13_POWER_UP_INT_TO_UC_EN", 7, 7, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN14_POWER_UP_INT_TO_UC_EN", 8, 8, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN15_POWER_UP_INT_TO_UC_EN", 9, 9, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN6_POWER_DOWN_INT_TO_UC_EN", 10, 10, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN7_POWER_DOWN_INT_TO_UC_EN", 11, 11, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN8_POWER_DOWN_INT_TO_UC_EN", 12, 12, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN9_POWER_DOWN_INT_TO_UC_EN", 13, 13, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN10_POWER_DOWN_INT_TO_UC_EN", 14, 14, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN11_POWER_DOWN_INT_TO_UC_EN", 15, 15, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN12_POWER_DOWN_INT_TO_UC_EN", 16, 16, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN13_POWER_DOWN_INT_TO_UC_EN", 17, 17, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN14_POWER_DOWN_INT_TO_UC_EN", 18, 18, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN15_POWER_DOWN_INT_TO_UC_EN", 19, 19, &umr_bitfield_default }, + { "DCCG_DMCU_INT_VSYNC_CNT_OTG0_TO_UC_EN", 20, 20, &umr_bitfield_default }, + { "DCCG_DMCU_INT_VSYNC_CNT_OTG1_TO_UC_EN", 21, 21, &umr_bitfield_default }, + { "DCCG_DMCU_INT_VSYNC_CNT_OTG2_TO_UC_EN", 22, 22, &umr_bitfield_default }, + { "DCCG_DMCU_INT_VSYNC_CNT_OTG3_TO_UC_EN", 23, 23, &umr_bitfield_default }, + { "DCCG_DMCU_INT_VSYNC_CNT_OTG4_TO_UC_EN", 24, 24, &umr_bitfield_default }, + { "DCCG_DMCU_INT_VSYNC_CNT_OTG5_TO_UC_EN", 25, 25, &umr_bitfield_default }, + { "ABM0_HG_READY_INT_TO_UC_EN", 26, 26, &umr_bitfield_default }, + { "ABM0_LS_READY_INT_TO_UC_EN", 27, 27, &umr_bitfield_default }, + { "ABM0_BL_UPDATE_INT_TO_UC_EN", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE[] = { + { "DCPG_IHC_DOMAIN6_POWER_UP_INT_XIRQ_IRQ_SEL", 0, 0, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN7_POWER_UP_INT_XIRQ_IRQ_SEL", 1, 1, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN8_POWER_UP_INT_XIRQ_IRQ_SEL", 2, 2, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN9_POWER_UP_INT_XIRQ_IRQ_SEL", 3, 3, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN10_POWER_UP_INT_XIRQ_IRQ_SEL", 4, 4, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN11_POWER_UP_INT_XIRQ_IRQ_SEL", 5, 5, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN12_POWER_UP_INT_XIRQ_IRQ_SEL", 6, 6, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN13_POWER_UP_INT_XIRQ_IRQ_SEL", 7, 7, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN14_POWER_UP_INT_XIRQ_IRQ_SEL", 8, 8, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN15_POWER_UP_INT_XIRQ_IRQ_SEL", 9, 9, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN6_POWER_DOWN_INT_XIRQ_IRQ_SEL", 10, 10, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN7_POWER_DOWN_INT_XIRQ_IRQ_SEL", 11, 11, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN8_POWER_DOWN_INT_XIRQ_IRQ_SEL", 12, 12, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN9_POWER_DOWN_INT_XIRQ_IRQ_SEL", 13, 13, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN10_POWER_DOWN_INT_XIRQ_IRQ_SEL", 14, 14, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN11_POWER_DOWN_INT_XIRQ_IRQ_SEL", 15, 15, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN12_POWER_DOWN_INT_XIRQ_IRQ_SEL", 16, 16, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN13_POWER_DOWN_INT_XIRQ_IRQ_SEL", 17, 17, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN14_POWER_DOWN_INT_XIRQ_IRQ_SEL", 18, 18, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN15_POWER_DOWN_INT_XIRQ_IRQ_SEL", 19, 19, &umr_bitfield_default }, + { "DCCG_DMCU_INT_VSYNC_CNT_OTG0_XIRQ_IRQ_SEL", 20, 20, &umr_bitfield_default }, + { "DCCG_DMCU_INT_VSYNC_CNT_OTG1_XIRQ_IRQ_SEL", 21, 21, &umr_bitfield_default }, + { "DCCG_DMCU_INT_VSYNC_CNT_OTG2_XIRQ_IRQ_SEL", 22, 22, &umr_bitfield_default }, + { "DCCG_DMCU_INT_VSYNC_CNT_OTG3_XIRQ_IRQ_SEL", 23, 23, &umr_bitfield_default }, + { "DCCG_DMCU_INT_VSYNC_CNT_OTG4_XIRQ_IRQ_SEL", 24, 24, &umr_bitfield_default }, + { "DCCG_DMCU_INT_VSYNC_CNT_OTG5_XIRQ_IRQ_SEL", 25, 25, &umr_bitfield_default }, + { "ABM0_HG_READY_INT_XIRQ_IRQ_SEL", 26, 26, &umr_bitfield_default }, + { "ABM0_LS_READY_INT_XIRQ_IRQ_SEL", 27, 27, &umr_bitfield_default }, + { "ABM0_BL_UPDATE_INT_XIRQ_IRQ_SEL", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDMCU_INT_CNT_CONTINUE[] = { + { "DMCU_ABM0_HG_READY_INT_CNT", 0, 7, &umr_bitfield_default }, + { "DMCU_ABM0_LS_READY_INT_CNT", 8, 15, &umr_bitfield_default }, + { "DMCU_ABM0_BL_UPDATE_INT_CNT", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPU_TIMER_START_POSITION_V_UPDATE[] = { + { "DC_GPU_TIMER_START_POSITION_D1_V_UPDATE", 0, 2, &umr_bitfield_default }, + { "DC_GPU_TIMER_START_POSITION_D2_V_UPDATE", 4, 6, &umr_bitfield_default }, + { "DC_GPU_TIMER_START_POSITION_D3_V_UPDATE", 8, 10, &umr_bitfield_default }, + { "DC_GPU_TIMER_START_POSITION_D4_V_UPDATE", 12, 14, &umr_bitfield_default }, + { "DC_GPU_TIMER_START_POSITION_D5_V_UPDATE", 16, 18, &umr_bitfield_default }, + { "DC_GPU_TIMER_START_POSITION_D6_V_UPDATE", 20, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPU_TIMER_START_POSITION_VSTARTUP[] = { + { "DC_GPU_TIMER_START_POSITION_D1_VSTARTUP", 0, 2, &umr_bitfield_default }, + { "DC_GPU_TIMER_START_POSITION_D2_VSTARTUP", 4, 6, &umr_bitfield_default }, + { "DC_GPU_TIMER_START_POSITION_D3_VSTARTUP", 8, 10, &umr_bitfield_default }, + { "DC_GPU_TIMER_START_POSITION_D4_VSTARTUP", 12, 14, &umr_bitfield_default }, + { "DC_GPU_TIMER_START_POSITION_D5_VSTARTUP", 16, 18, &umr_bitfield_default }, + { "DC_GPU_TIMER_START_POSITION_D6_VSTARTUP", 20, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPU_TIMER_READ[] = { + { "DC_GPU_TIMER_READ", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPU_TIMER_READ_CNTL[] = { + { "DC_GPU_TIMER_READ_SELECT", 0, 6, &umr_bitfield_default }, + { "DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM", 8, 10, &umr_bitfield_default }, + { "DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM", 11, 13, &umr_bitfield_default }, + { "DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM", 14, 16, &umr_bitfield_default }, + { "DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM", 17, 19, &umr_bitfield_default }, + { "DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM", 20, 22, &umr_bitfield_default }, + { "DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM", 23, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDISP_INTERRUPT_STATUS[] = { + { "OPTC1_DATA_UNDERFLOW_INTERRUPT", 1, 1, &umr_bitfield_default }, + { "OTG1_IHC_SNAPSHOT_INTERRUPT", 4, 4, &umr_bitfield_default }, + { "OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT", 5, 5, &umr_bitfield_default }, + { "OTG1_IHC_FORCE_COUNT_NOW_INTERRUPT", 6, 6, &umr_bitfield_default }, + { "OTG1_IHC_TRIGA_INTERRUPT", 7, 7, &umr_bitfield_default }, + { "OTG1_IHC_TRIGB_INTERRUPT", 8, 8, &umr_bitfield_default }, + { "OTG1_IHC_VSYNC_NOM_INTERRUPT", 9, 9, &umr_bitfield_default }, + { "OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT", 10, 10, &umr_bitfield_default }, + { "DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT", 15, 15, &umr_bitfield_default }, + { "DIGA_DP_VID_STREAM_DISABLE_INTERRUPT", 16, 16, &umr_bitfield_default }, + { "DC_HPD1_INTERRUPT", 17, 17, &umr_bitfield_default }, + { "DC_HPD1_RX_INTERRUPT", 18, 18, &umr_bitfield_default }, + { "AUX1_SW_DONE_INTERRUPT", 19, 19, &umr_bitfield_default }, + { "AUX1_LS_DONE_INTERRUPT", 20, 20, &umr_bitfield_default }, + { "DACA_AUTODETECT_GENERITE_INTERRUPT", 22, 22, &umr_bitfield_default }, + { "RBBMIF_IHC_TIMEOUT_INTERRUPT", 23, 23, &umr_bitfield_default }, + { "DC_I2C_SW_DONE_INTERRUPT", 24, 24, &umr_bitfield_default }, + { "DMCU_UC_INTERNAL_INT", 26, 26, &umr_bitfield_default }, + { "ABM1_HG_READY_INT", 28, 28, &umr_bitfield_default }, + { "ABM1_LS_READY_INT", 29, 29, &umr_bitfield_default }, + { "ABM1_BL_UPDATE_INT", 30, 30, &umr_bitfield_default }, + { "DISP_INTERRUPT_STATUS_CONTINUE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE[] = { + { "OPTC2_DATA_UNDERFLOW_INTERRUPT", 1, 1, &umr_bitfield_default }, + { "OTG2_IHC_SNAPSHOT_INTERRUPT", 4, 4, &umr_bitfield_default }, + { "OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT", 5, 5, &umr_bitfield_default }, + { "OTG2_IHC_FORCE_COUNT_NOW_INTERRUPT", 6, 6, &umr_bitfield_default }, + { "OTG2_IHC_TRIGA_INTERRUPT", 7, 7, &umr_bitfield_default }, + { "OTG2_IHC_TRIGB_INTERRUPT", 8, 8, &umr_bitfield_default }, + { "OTG2_IHC_VSYNC_NOM_INTERRUPT", 9, 9, &umr_bitfield_default }, + { "OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT", 10, 10, &umr_bitfield_default }, + { "DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT", 15, 15, &umr_bitfield_default }, + { "DIGB_DP_VID_STREAM_DISABLE_INTERRUPT", 16, 16, &umr_bitfield_default }, + { "DC_HPD2_INTERRUPT", 17, 17, &umr_bitfield_default }, + { "DC_HPD2_RX_INTERRUPT", 18, 18, &umr_bitfield_default }, + { "AUX2_SW_DONE_INTERRUPT", 19, 19, &umr_bitfield_default }, + { "AUX2_LS_DONE_INTERRUPT", 20, 20, &umr_bitfield_default }, + { "OTG1_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT", 25, 25, &umr_bitfield_default }, + { "OTG1_IHC_EXT_TIMING_SYNC_INTERRUPT", 26, 26, &umr_bitfield_default }, + { "OTG1_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT", 27, 27, &umr_bitfield_default }, + { "OTG1_IHC_VERTICAL_INTERRUPT0", 28, 28, &umr_bitfield_default }, + { "OTG1_IHC_VERTICAL_INTERRUPT1", 29, 29, &umr_bitfield_default }, + { "OTG1_IHC_VERTICAL_INTERRUPT2", 30, 30, &umr_bitfield_default }, + { "DISP_INTERRUPT_STATUS_CONTINUE2", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE2[] = { + { "OPTC3_DATA_UNDERFLOW_INTERRUPT", 1, 1, &umr_bitfield_default }, + { "OTG3_IHC_SNAPSHOT_INTERRUPT", 4, 4, &umr_bitfield_default }, + { "OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT", 5, 5, &umr_bitfield_default }, + { "OTG3_IHC_FORCE_COUNT_NOW_INTERRUPT", 6, 6, &umr_bitfield_default }, + { "OTG3_IHC_TRIGA_INTERRUPT", 7, 7, &umr_bitfield_default }, + { "OTG3_IHC_TRIGB_INTERRUPT", 8, 8, &umr_bitfield_default }, + { "OTG3_IHC_VSYNC_NOM_INTERRUPT", 9, 9, &umr_bitfield_default }, + { "OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT", 10, 10, &umr_bitfield_default }, + { "DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT", 15, 15, &umr_bitfield_default }, + { "DIGC_DP_VID_STREAM_DISABLE_INTERRUPT", 16, 16, &umr_bitfield_default }, + { "DC_HPD3_INTERRUPT", 17, 17, &umr_bitfield_default }, + { "DC_HPD3_RX_INTERRUPT", 18, 18, &umr_bitfield_default }, + { "AUX3_SW_DONE_INTERRUPT", 19, 19, &umr_bitfield_default }, + { "AUX3_LS_DONE_INTERRUPT", 20, 20, &umr_bitfield_default }, + { "OTG2_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT", 25, 25, &umr_bitfield_default }, + { "OTG2_IHC_EXT_TIMING_SYNC_INTERRUPT", 26, 26, &umr_bitfield_default }, + { "OTG2_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT", 27, 27, &umr_bitfield_default }, + { "OTG2_IHC_VERTICAL_INTERRUPT0", 28, 28, &umr_bitfield_default }, + { "OTG2_IHC_VERTICAL_INTERRUPT1", 29, 29, &umr_bitfield_default }, + { "OTG2_IHC_VERTICAL_INTERRUPT2", 30, 30, &umr_bitfield_default }, + { "DISP_INTERRUPT_STATUS_CONTINUE3", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE3[] = { + { "OPTC4_DATA_UNDERFLOW_INTERRUPT", 1, 1, &umr_bitfield_default }, + { "OTG4_IHC_SNAPSHOT_INTERRUPT", 4, 4, &umr_bitfield_default }, + { "OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT", 5, 5, &umr_bitfield_default }, + { "OTG4_IHC_FORCE_COUNT_NOW_INTERRUPT", 6, 6, &umr_bitfield_default }, + { "OTG4_IHC_TRIGA_INTERRUPT", 7, 7, &umr_bitfield_default }, + { "OTG4_IHC_TRIGB_INTERRUPT", 8, 8, &umr_bitfield_default }, + { "OTG4_IHC_VSYNC_NOM_INTERRUPT", 9, 9, &umr_bitfield_default }, + { "OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT", 10, 10, &umr_bitfield_default }, + { "DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT", 15, 15, &umr_bitfield_default }, + { "DIGD_DP_VID_STREAM_DISABLE_INTERRUPT", 16, 16, &umr_bitfield_default }, + { "DC_HPD4_INTERRUPT", 17, 17, &umr_bitfield_default }, + { "DC_HPD4_RX_INTERRUPT", 18, 18, &umr_bitfield_default }, + { "AUX4_SW_DONE_INTERRUPT", 19, 19, &umr_bitfield_default }, + { "AUX4_LS_DONE_INTERRUPT", 20, 20, &umr_bitfield_default }, + { "WBSCL0_HOST_CONFLICT_INTERRUPT", 23, 23, &umr_bitfield_default }, + { "WBSCL0_DATA_OVERFLOW_INTERRUPT", 24, 24, &umr_bitfield_default }, + { "OTG3_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT", 25, 25, &umr_bitfield_default }, + { "OTG3_IHC_EXT_TIMING_SYNC_INTERRUPT", 26, 26, &umr_bitfield_default }, + { "OTG3_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT", 27, 27, &umr_bitfield_default }, + { "OTG3_IHC_VERTICAL_INTERRUPT0", 28, 28, &umr_bitfield_default }, + { "OTG3_IHC_VERTICAL_INTERRUPT1", 29, 29, &umr_bitfield_default }, + { "OTG3_IHC_VERTICAL_INTERRUPT2", 30, 30, &umr_bitfield_default }, + { "DISP_INTERRUPT_STATUS_CONTINUE4", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE4[] = { + { "OPTC5_DATA_UNDERFLOW_INTERRUPT", 0, 0, &umr_bitfield_default }, + { "OPTC6_DATA_UNDERFLOW_INTERRUPT", 1, 1, &umr_bitfield_default }, + { "OTG5_IHC_SNAPSHOT_INTERRUPT", 4, 4, &umr_bitfield_default }, + { "OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT", 5, 5, &umr_bitfield_default }, + { "OTG5_IHC_FORCE_COUNT_NOW_INTERRUPT", 6, 6, &umr_bitfield_default }, + { "OTG5_IHC_TRIGA_INTERRUPT", 7, 7, &umr_bitfield_default }, + { "OTG5_IHC_TRIGB_INTERRUPT", 8, 8, &umr_bitfield_default }, + { "OTG5_IHC_VSYNC_NOM_INTERRUPT", 9, 9, &umr_bitfield_default }, + { "OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT", 10, 10, &umr_bitfield_default }, + { "DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT", 15, 15, &umr_bitfield_default }, + { "DIGE_DP_VID_STREAM_DISABLE_INTERRUPT", 16, 16, &umr_bitfield_default }, + { "DC_HPD5_INTERRUPT", 17, 17, &umr_bitfield_default }, + { "DC_HPD5_RX_INTERRUPT", 18, 18, &umr_bitfield_default }, + { "AUX5_SW_DONE_INTERRUPT", 19, 19, &umr_bitfield_default }, + { "AUX5_LS_DONE_INTERRUPT", 20, 20, &umr_bitfield_default }, + { "OTG4_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT", 22, 22, &umr_bitfield_default }, + { "OTG4_IHC_EXT_TIMING_SYNC_INTERRUPT", 23, 23, &umr_bitfield_default }, + { "OTG4_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT", 24, 24, &umr_bitfield_default }, + { "OTG5_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT", 25, 25, &umr_bitfield_default }, + { "OTG5_IHC_EXT_TIMING_SYNC_INTERRUPT", 26, 26, &umr_bitfield_default }, + { "OTG5_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT", 27, 27, &umr_bitfield_default }, + { "OTG4_IHC_VERTICAL_INTERRUPT0", 28, 28, &umr_bitfield_default }, + { "OTG4_IHC_VERTICAL_INTERRUPT1", 29, 29, &umr_bitfield_default }, + { "OTG4_IHC_VERTICAL_INTERRUPT2", 30, 30, &umr_bitfield_default }, + { "DISP_INTERRUPT_STATUS_CONTINUE5", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE5[] = { + { "OTG6_IHC_SNAPSHOT_INTERRUPT", 4, 4, &umr_bitfield_default }, + { "OTG6_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT", 5, 5, &umr_bitfield_default }, + { "OTG6_IHC_FORCE_COUNT_NOW_INTERRUPT", 6, 6, &umr_bitfield_default }, + { "OTG6_IHC_TRIGA_INTERRUPT", 7, 7, &umr_bitfield_default }, + { "OTG6_IHC_TRIGB_INTERRUPT", 8, 8, &umr_bitfield_default }, + { "OTG6_IHC_VSYNC_NOM_INTERRUPT", 9, 9, &umr_bitfield_default }, + { "OTG6_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT", 10, 10, &umr_bitfield_default }, + { "DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT", 15, 15, &umr_bitfield_default }, + { "DIGF_DP_VID_STREAM_DISABLE_INTERRUPT", 16, 16, &umr_bitfield_default }, + { "DC_HPD6_INTERRUPT", 17, 17, &umr_bitfield_default }, + { "DC_HPD6_RX_INTERRUPT", 18, 18, &umr_bitfield_default }, + { "AUX6_SW_DONE_INTERRUPT", 19, 19, &umr_bitfield_default }, + { "AUX6_LS_DONE_INTERRUPT", 20, 20, &umr_bitfield_default }, + { "OTG6_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT", 22, 22, &umr_bitfield_default }, + { "OTG6_IHC_EXT_TIMING_SYNC_INTERRUPT", 23, 23, &umr_bitfield_default }, + { "OTG6_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT", 24, 24, &umr_bitfield_default }, + { "OTG5_IHC_VERTICAL_INTERRUPT0", 25, 25, &umr_bitfield_default }, + { "OTG5_IHC_VERTICAL_INTERRUPT1", 26, 26, &umr_bitfield_default }, + { "OTG5_IHC_VERTICAL_INTERRUPT2", 27, 27, &umr_bitfield_default }, + { "OTG6_IHC_VERTICAL_INTERRUPT0", 28, 28, &umr_bitfield_default }, + { "OTG6_IHC_VERTICAL_INTERRUPT1", 29, 29, &umr_bitfield_default }, + { "OTG6_IHC_VERTICAL_INTERRUPT2", 30, 30, &umr_bitfield_default }, + { "DISP_INTERRUPT_STATUS_CONTINUE6", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE6[] = { + { "MCIF_CWB0_IHIF_INTERRUPT", 9, 9, &umr_bitfield_default }, + { "MCIF_CWB1_IHIF_INTERRUPT", 10, 10, &umr_bitfield_default }, + { "AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT", 17, 17, &umr_bitfield_default }, + { "AUX1_GTC_SYNC_ERROR_INTERRUPT", 18, 18, &umr_bitfield_default }, + { "AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT", 19, 19, &umr_bitfield_default }, + { "AUX2_GTC_SYNC_ERROR_INTERRUPT", 20, 20, &umr_bitfield_default }, + { "AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT", 21, 21, &umr_bitfield_default }, + { "AUX3_GTC_SYNC_ERROR_INTERRUPT", 22, 22, &umr_bitfield_default }, + { "AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT", 23, 23, &umr_bitfield_default }, + { "AUX4_GTC_SYNC_ERROR_INTERRUPT", 24, 24, &umr_bitfield_default }, + { "AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT", 25, 25, &umr_bitfield_default }, + { "AUX5_GTC_SYNC_ERROR_INTERRUPT", 26, 26, &umr_bitfield_default }, + { "AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT", 27, 27, &umr_bitfield_default }, + { "AUX6_GTC_SYNC_ERROR_INTERRUPT", 28, 28, &umr_bitfield_default }, + { "MCIF_DWB0_IHIF_INTERRUPT", 29, 29, &umr_bitfield_default }, + { "MCIF_DWB1_IHIF_INTERRUPT", 30, 30, &umr_bitfield_default }, + { "DISP_INTERRUPT_STATUS_CONTINUE7", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE7[] = { + { "DCCG_PERFMON_COUNTER0_INTERRUPT", 0, 0, &umr_bitfield_default }, + { "DCCG_PERFMON_COUNTER1_INTERRUPT", 1, 1, &umr_bitfield_default }, + { "DMU_PERFMON_COUNTER0_INTERRUPT", 9, 9, &umr_bitfield_default }, + { "DMU_PERFMON_COUNTER1_INTERRUPT", 10, 10, &umr_bitfield_default }, + { "DIO_PERFMON_COUNTER0_INTERRUPT", 18, 18, &umr_bitfield_default }, + { "DIO_PERFMON_COUNTER1_INTERRUPT", 19, 19, &umr_bitfield_default }, + { "WB0_PERFMON_COUNTER0_INTERRUPT", 27, 27, &umr_bitfield_default }, + { "WB0_PERFMON_COUNTER1_INTERRUPT", 28, 28, &umr_bitfield_default }, + { "DISP_INTERRUPT_STATUS_CONTINUE8", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE8[] = { + { "DPP0_PERFMON_COUNTER0_INTERRUPT", 0, 0, &umr_bitfield_default }, + { "DPP0_PERFMON_COUNTER1_INTERRUPT", 1, 1, &umr_bitfield_default }, + { "DPP1_PERFMON_COUNTER0_INTERRUPT", 9, 9, &umr_bitfield_default }, + { "DPP1_PERFMON_COUNTER1_INTERRUPT", 10, 10, &umr_bitfield_default }, + { "DPP2_PERFMON_COUNTER0_INTERRUPT", 18, 18, &umr_bitfield_default }, + { "DPP2_PERFMON_COUNTER1_INTERRUPT", 19, 19, &umr_bitfield_default }, + { "DISP_INTERRUPT_STATUS_CONTINUE9", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE9[] = { + { "DPP3_PERFMON_COUNTER0_INTERRUPT", 0, 0, &umr_bitfield_default }, + { "DPP3_PERFMON_COUNTER1_INTERRUPT", 1, 1, &umr_bitfield_default }, + { "DPP4_PERFMON_COUNTER0_INTERRUPT", 9, 9, &umr_bitfield_default }, + { "DPP4_PERFMON_COUNTER1_INTERRUPT", 10, 10, &umr_bitfield_default }, + { "DPP5_PERFMON_COUNTER0_INTERRUPT", 18, 18, &umr_bitfield_default }, + { "DPP5_PERFMON_COUNTER1_INTERRUPT", 19, 19, &umr_bitfield_default }, + { "WBSCL1_HOST_CONFLICT_INTERRUPT", 28, 28, &umr_bitfield_default }, + { "WBSCL1_DATA_OVERFLOW_INTERRUPT", 29, 29, &umr_bitfield_default }, + { "DISP_INTERRUPT_STATUS_CONTINUE10", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE10[] = { + { "DCCG_IHC_VSYNC_OTG0_LATCH_INT", 0, 0, &umr_bitfield_default }, + { "DCCG_IHC_VSYNC_OTG1_LATCH_INT", 1, 1, &umr_bitfield_default }, + { "DCCG_IHC_VSYNC_OTG2_LATCH_INT", 2, 2, &umr_bitfield_default }, + { "DCCG_IHC_VSYNC_OTG3_LATCH_INT", 3, 3, &umr_bitfield_default }, + { "DCCG_IHC_VSYNC_OTG4_LATCH_INT", 4, 4, &umr_bitfield_default }, + { "DCCG_IHC_VSYNC_OTG5_LATCH_INT", 5, 5, &umr_bitfield_default }, + { "DCCG_PERFMON2_COUNTER0_INTERRUPT", 12, 12, &umr_bitfield_default }, + { "DCCG_PERFMON2_COUNTER1_INTERRUPT", 13, 13, &umr_bitfield_default }, + { "OTG1_IHC_RANGE_TIMING_UPDATE", 22, 22, &umr_bitfield_default }, + { "OTG2_IHC_RANGE_TIMING_UPDATE", 23, 23, &umr_bitfield_default }, + { "OTG3_IHC_RANGE_TIMING_UPDATE", 24, 24, &umr_bitfield_default }, + { "OTG4_IHC_RANGE_TIMING_UPDATE", 25, 25, &umr_bitfield_default }, + { "OTG5_IHC_RANGE_TIMING_UPDATE", 26, 26, &umr_bitfield_default }, + { "OTG6_IHC_RANGE_TIMING_UPDATE", 27, 27, &umr_bitfield_default }, + { "DISP_INTERRUPT_STATUS_CONTINUE11", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE11[] = { + { "WB1_PERFMON_COUNTER0_INTERRUPT", 6, 6, &umr_bitfield_default }, + { "WB1_PERFMON_COUNTER1_INTERRUPT", 7, 7, &umr_bitfield_default }, + { "MPCC0_STALL_INTERRUPT", 15, 15, &umr_bitfield_default }, + { "MPCC1_STALL_INTERRUPT", 16, 16, &umr_bitfield_default }, + { "MPCC2_STALL_INTERRUPT", 17, 17, &umr_bitfield_default }, + { "MPCC3_STALL_INTERRUPT", 18, 18, &umr_bitfield_default }, + { "MPCC4_STALL_INTERRUPT", 19, 19, &umr_bitfield_default }, + { "MPCC5_STALL_INTERRUPT", 20, 20, &umr_bitfield_default }, + { "MPCC6_STALL_INTERRUPT", 21, 21, &umr_bitfield_default }, + { "MPCC7_STALL_INTERRUPT", 22, 22, &umr_bitfield_default }, + { "VGA_IHC_VGA_CRT_INTERRUPT", 23, 23, &umr_bitfield_default }, + { "DISP_INTERRUPT_STATUS_CONTINUE12", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE12[] = { + { "MPC_PERFMON_COUNTER0_INTERRUPT", 0, 0, &umr_bitfield_default }, + { "MPC_PERFMON_COUNTER1_INTERRUPT", 1, 1, &umr_bitfield_default }, + { "DPP6_PERFMON_COUNTER0_INTERRUPT", 9, 9, &umr_bitfield_default }, + { "DPP6_PERFMON_COUNTER1_INTERRUPT", 10, 10, &umr_bitfield_default }, + { "DPP7_PERFMON_COUNTER0_INTERRUPT", 18, 18, &umr_bitfield_default }, + { "DPP7_PERFMON_COUNTER1_INTERRUPT", 19, 19, &umr_bitfield_default }, + { "DISP_INTERRUPT_STATUS_CONTINUE13", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE13[] = { + { "HUBBUB_PERFMON_COUNTER0_INTERRUPT", 0, 0, &umr_bitfield_default }, + { "HUBBUB_PERFMON_COUNTER1_INTERRUPT", 1, 1, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT", 9, 9, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT", 10, 10, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT", 11, 11, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT", 12, 12, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT", 13, 13, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT", 14, 14, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT", 15, 15, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT", 16, 16, &umr_bitfield_default }, + { "HUBP0_PERFMON_COUNTER0_INTERRUPT", 18, 18, &umr_bitfield_default }, + { "HUBP0_PERFMON_COUNTER1_INTERRUPT", 19, 19, &umr_bitfield_default }, + { "HUBP0_IHC_VBLANK_INTERRUPT", 27, 27, &umr_bitfield_default }, + { "HUBP0_IHC_VLINE_INTERRUPT", 28, 28, &umr_bitfield_default }, + { "HUBP0_IHC_VLINE2_INTERRUPT", 29, 29, &umr_bitfield_default }, + { "HUBP0_IHC_VM_CONTEXT_ERROR_INTERRUPT", 30, 30, &umr_bitfield_default }, + { "DISP_INTERRUPT_STATUS_CONTINUE14", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE14[] = { + { "HUBP1_PERFMON_COUNTER0_INTERRUPT", 0, 0, &umr_bitfield_default }, + { "HUBP1_PERFMON_COUNTER1_INTERRUPT", 1, 1, &umr_bitfield_default }, + { "HUBP2_PERFMON_COUNTER0_INTERRUPT", 9, 9, &umr_bitfield_default }, + { "HUBP2_PERFMON_COUNTER1_INTERRUPT", 10, 10, &umr_bitfield_default }, + { "HUBP3_PERFMON_COUNTER0_INTERRUPT", 18, 18, &umr_bitfield_default }, + { "HUBP3_PERFMON_COUNTER1_INTERRUPT", 19, 19, &umr_bitfield_default }, + { "HUBP1_IHC_VBLANK_INTERRUPT", 27, 27, &umr_bitfield_default }, + { "HUBP1_IHC_VLINE_INTERRUPT", 28, 28, &umr_bitfield_default }, + { "HUBP1_IHC_VLINE2_INTERRUPT", 29, 29, &umr_bitfield_default }, + { "HUBP1_IHC_VM_CONTEXT_ERROR_INTERRUPT", 30, 30, &umr_bitfield_default }, + { "DISP_INTERRUPT_STATUS_CONTINUE15", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE15[] = { + { "HUBP4_PERFMON_COUNTER0_INTERRUPT", 0, 0, &umr_bitfield_default }, + { "HUBP4_PERFMON_COUNTER1_INTERRUPT", 1, 1, &umr_bitfield_default }, + { "HUBP5_PERFMON_COUNTER0_INTERRUPT", 9, 9, &umr_bitfield_default }, + { "HUBP5_PERFMON_COUNTER1_INTERRUPT", 10, 10, &umr_bitfield_default }, + { "HUBP6_PERFMON_COUNTER0_INTERRUPT", 18, 18, &umr_bitfield_default }, + { "HUBP6_PERFMON_COUNTER1_INTERRUPT", 19, 19, &umr_bitfield_default }, + { "HUBP2_IHC_VBLANK_INTERRUPT", 27, 27, &umr_bitfield_default }, + { "HUBP2_IHC_VLINE_INTERRUPT", 28, 28, &umr_bitfield_default }, + { "HUBP2_IHC_VLINE2_INTERRUPT", 29, 29, &umr_bitfield_default }, + { "HUBP2_IHC_VM_CONTEXT_ERROR_INTERRUPT", 30, 30, &umr_bitfield_default }, + { "DISP_INTERRUPT_STATUS_CONTINUE16", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE16[] = { + { "HUBP7_PERFMON_COUNTER0_INTERRUPT", 0, 0, &umr_bitfield_default }, + { "HUBP7_PERFMON_COUNTER1_INTERRUPT", 1, 1, &umr_bitfield_default }, + { "HUBP3_IHC_VBLANK_INTERRUPT", 9, 9, &umr_bitfield_default }, + { "HUBP3_IHC_VLINE_INTERRUPT", 10, 10, &umr_bitfield_default }, + { "HUBP3_IHC_VLINE2_INTERRUPT", 11, 11, &umr_bitfield_default }, + { "HUBP4_IHC_VBLANK_INTERRUPT", 12, 12, &umr_bitfield_default }, + { "HUBP4_IHC_VLINE_INTERRUPT", 13, 13, &umr_bitfield_default }, + { "HUBP4_IHC_VLINE2_INTERRUPT", 14, 14, &umr_bitfield_default }, + { "HUBP5_IHC_VBLANK_INTERRUPT", 15, 15, &umr_bitfield_default }, + { "HUBP5_IHC_VLINE_INTERRUPT", 16, 16, &umr_bitfield_default }, + { "HUBP5_IHC_VLINE2_INTERRUPT", 17, 17, &umr_bitfield_default }, + { "HUBP6_IHC_VBLANK_INTERRUPT", 18, 18, &umr_bitfield_default }, + { "HUBP6_IHC_VLINE_INTERRUPT", 19, 19, &umr_bitfield_default }, + { "HUBP6_IHC_VLINE2_INTERRUPT", 20, 20, &umr_bitfield_default }, + { "HUBP7_IHC_VBLANK_INTERRUPT", 21, 21, &umr_bitfield_default }, + { "HUBP7_IHC_VLINE_INTERRUPT", 22, 22, &umr_bitfield_default }, + { "HUBP7_IHC_VLINE2_INTERRUPT", 23, 23, &umr_bitfield_default }, + { "HUBP3_IHC_VM_CONTEXT_ERROR_INTERRUPT", 24, 24, &umr_bitfield_default }, + { "HUBP4_IHC_VM_CONTEXT_ERROR_INTERRUPT", 25, 25, &umr_bitfield_default }, + { "HUBP5_IHC_VM_CONTEXT_ERROR_INTERRUPT", 26, 26, &umr_bitfield_default }, + { "HUBP6_IHC_VM_CONTEXT_ERROR_INTERRUPT", 27, 27, &umr_bitfield_default }, + { "HUBP7_IHC_VM_CONTEXT_ERROR_INTERRUPT", 28, 28, &umr_bitfield_default }, + { "DISP_INTERRUPT_STATUS_CONTINUE17", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE17[] = { + { "OPP_PERFMON_COUNTER0_INTERRUPT", 0, 0, &umr_bitfield_default }, + { "OPP_PERFMON_COUNTER1_INTERRUPT", 1, 1, &umr_bitfield_default }, + { "HUBP0_IHC_FLIP_INTERRUPT", 2, 2, &umr_bitfield_default }, + { "HUBP1_IHC_FLIP_INTERRUPT", 3, 3, &umr_bitfield_default }, + { "HUBP2_IHC_FLIP_INTERRUPT", 4, 4, &umr_bitfield_default }, + { "HUBP3_IHC_FLIP_INTERRUPT", 5, 5, &umr_bitfield_default }, + { "HUBP4_IHC_FLIP_INTERRUPT", 6, 6, &umr_bitfield_default }, + { "HUBP5_IHC_FLIP_INTERRUPT", 7, 7, &umr_bitfield_default }, + { "HUBP6_IHC_FLIP_INTERRUPT", 8, 8, &umr_bitfield_default }, + { "HUBP7_IHC_FLIP_INTERRUPT", 9, 9, &umr_bitfield_default }, + { "OPTC_PERFMON_COUNTER0_INTERRUPT", 10, 10, &umr_bitfield_default }, + { "OPTC_PERFMON_COUNTER1_INTERRUPT", 11, 11, &umr_bitfield_default }, + { "MMHUBBUB_PERFMON_COUNTER0_INTERRUPT", 18, 18, &umr_bitfield_default }, + { "MMHUBBUB_PERFMON_COUNTER1_INTERRUPT", 19, 19, &umr_bitfield_default }, + { "HUBP0_IHC_FLIP_AWAY_INTERRUPT", 20, 20, &umr_bitfield_default }, + { "HUBP1_IHC_FLIP_AWAY_INTERRUPT", 21, 21, &umr_bitfield_default }, + { "HUBP2_IHC_FLIP_AWAY_INTERRUPT", 22, 22, &umr_bitfield_default }, + { "HUBP3_IHC_FLIP_AWAY_INTERRUPT", 23, 23, &umr_bitfield_default }, + { "HUBP4_IHC_FLIP_AWAY_INTERRUPT", 24, 24, &umr_bitfield_default }, + { "HUBP5_IHC_FLIP_AWAY_INTERRUPT", 25, 25, &umr_bitfield_default }, + { "HUBP6_IHC_FLIP_AWAY_INTERRUPT", 26, 26, &umr_bitfield_default }, + { "HUBP7_IHC_FLIP_AWAY_INTERRUPT", 27, 27, &umr_bitfield_default }, + { "DISP_INTERRUPT_STATUS_CONTINUE18", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE18[] = { + { "AZ_PERFMON_COUNTER0_INTERRUPT", 0, 0, &umr_bitfield_default }, + { "AZ_PERFMON_COUNTER1_INTERRUPT", 1, 1, &umr_bitfield_default }, + { "DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT", 9, 9, &umr_bitfield_default }, + { "DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT", 10, 10, &umr_bitfield_default }, + { "DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT", 11, 11, &umr_bitfield_default }, + { "DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT", 12, 12, &umr_bitfield_default }, + { "DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT", 13, 13, &umr_bitfield_default }, + { "DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT", 14, 14, &umr_bitfield_default }, + { "DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT", 15, 15, &umr_bitfield_default }, + { "DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT", 16, 16, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT", 17, 17, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT", 18, 18, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT", 19, 19, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT", 20, 20, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT", 21, 21, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT", 22, 22, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT", 23, 23, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT", 24, 24, &umr_bitfield_default }, + { "DISP_INTERRUPT_STATUS_CONTINUE19", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE19[] = { + { "AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT", 0, 0, &umr_bitfield_default }, + { "AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT", 1, 1, &umr_bitfield_default }, + { "AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT", 2, 2, &umr_bitfield_default }, + { "AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT", 3, 3, &umr_bitfield_default }, + { "AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT", 4, 4, &umr_bitfield_default }, + { "AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT", 5, 5, &umr_bitfield_default }, + { "AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT", 6, 6, &umr_bitfield_default }, + { "AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT", 7, 7, &umr_bitfield_default }, + { "AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT", 8, 8, &umr_bitfield_default }, + { "AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT", 9, 9, &umr_bitfield_default }, + { "AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT", 10, 10, &umr_bitfield_default }, + { "AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT", 11, 11, &umr_bitfield_default }, + { "AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT", 12, 12, &umr_bitfield_default }, + { "AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT", 13, 13, &umr_bitfield_default }, + { "AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT", 14, 14, &umr_bitfield_default }, + { "AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT", 15, 15, &umr_bitfield_default }, + { "AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT", 16, 16, &umr_bitfield_default }, + { "AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT", 17, 17, &umr_bitfield_default }, + { "AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT", 18, 18, &umr_bitfield_default }, + { "AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT", 19, 19, &umr_bitfield_default }, + { "AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT", 20, 20, &umr_bitfield_default }, + { "AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT", 21, 21, &umr_bitfield_default }, + { "AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT", 22, 22, &umr_bitfield_default }, + { "AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT", 23, 23, &umr_bitfield_default }, + { "DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT", 28, 28, &umr_bitfield_default }, + { "DIGG_DP_VID_STREAM_DISABLE_INTERRUPT", 29, 29, &umr_bitfield_default }, + { "DISP_INTERRUPT_STATUS_CONTINUE20", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE20[] = { + { "OTG1_IHC_CPU_SS_INTERRUPT", 0, 0, &umr_bitfield_default }, + { "OTG2_IHC_CPU_SS_INTERRUPT", 1, 1, &umr_bitfield_default }, + { "OTG3_IHC_CPU_SS_INTERRUPT", 2, 2, &umr_bitfield_default }, + { "OTG4_IHC_CPU_SS_INTERRUPT", 3, 3, &umr_bitfield_default }, + { "OTG5_IHC_CPU_SS_INTERRUPT", 4, 4, &umr_bitfield_default }, + { "OTG6_IHC_CPU_SS_INTERRUPT", 5, 5, &umr_bitfield_default }, + { "OTG1_IHC_V_UPDATE_INTERRUPT", 6, 6, &umr_bitfield_default }, + { "OTG2_IHC_V_UPDATE_INTERRUPT", 7, 7, &umr_bitfield_default }, + { "OTG3_IHC_V_UPDATE_INTERRUPT", 8, 8, &umr_bitfield_default }, + { "OTG4_IHC_V_UPDATE_INTERRUPT", 9, 9, &umr_bitfield_default }, + { "OTG5_IHC_V_UPDATE_INTERRUPT", 10, 10, &umr_bitfield_default }, + { "OTG6_IHC_V_UPDATE_INTERRUPT", 11, 11, &umr_bitfield_default }, + { "OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT", 12, 12, &umr_bitfield_default }, + { "OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT", 13, 13, &umr_bitfield_default }, + { "OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT", 14, 14, &umr_bitfield_default }, + { "OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT", 15, 15, &umr_bitfield_default }, + { "OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT", 16, 16, &umr_bitfield_default }, + { "OTG6_IHC_GSL_VSYNC_GAP_INTERRUPT", 17, 17, &umr_bitfield_default }, + { "OTG1_IHC_VSTARTUP_INTERRUPT", 18, 18, &umr_bitfield_default }, + { "OTG2_IHC_VSTARTUP_INTERRUPT", 19, 19, &umr_bitfield_default }, + { "OTG3_IHC_VSTARTUP_INTERRUPT", 20, 20, &umr_bitfield_default }, + { "OTG4_IHC_VSTARTUP_INTERRUPT", 21, 21, &umr_bitfield_default }, + { "OTG5_IHC_VSTARTUP_INTERRUPT", 22, 22, &umr_bitfield_default }, + { "OTG6_IHC_VSTARTUP_INTERRUPT", 23, 23, &umr_bitfield_default }, + { "OTG1_IHC_VREADY_INTERRUPT", 24, 24, &umr_bitfield_default }, + { "OTG2_IHC_VREADY_INTERRUPT", 25, 25, &umr_bitfield_default }, + { "OTG3_IHC_VREADY_INTERRUPT", 26, 26, &umr_bitfield_default }, + { "OTG4_IHC_VREADY_INTERRUPT", 27, 27, &umr_bitfield_default }, + { "OTG5_IHC_VREADY_INTERRUPT", 28, 28, &umr_bitfield_default }, + { "OTG6_IHC_VREADY_INTERRUPT", 29, 29, &umr_bitfield_default }, + { "DISP_INTERRUPT_STATUS_CONTINUE21", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE21[] = { + { "DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT", 0, 0, &umr_bitfield_default }, + { "DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT", 1, 1, &umr_bitfield_default }, + { "DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT", 2, 2, &umr_bitfield_default }, + { "DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT", 3, 3, &umr_bitfield_default }, + { "DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT", 4, 4, &umr_bitfield_default }, + { "DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT", 5, 5, &umr_bitfield_default }, + { "DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT", 6, 6, &umr_bitfield_default }, + { "DC_I2C_DDC1_READ_REQUEST_INTERRUPT", 7, 7, &umr_bitfield_default }, + { "DC_I2C_DDC2_READ_REQUEST_INTERRUPT", 8, 8, &umr_bitfield_default }, + { "DC_I2C_DDC3_READ_REQUEST_INTERRUPT", 9, 9, &umr_bitfield_default }, + { "DC_I2C_DDC4_READ_REQUEST_INTERRUPT", 10, 10, &umr_bitfield_default }, + { "DC_I2C_DDC5_READ_REQUEST_INTERRUPT", 11, 11, &umr_bitfield_default }, + { "DC_I2C_DDC6_READ_REQUEST_INTERRUPT", 12, 12, &umr_bitfield_default }, + { "DC_I2C_VGA_READ_REQUEST_INTERRUPT", 13, 13, &umr_bitfield_default }, + { "GENERIC_I2C_DDC_READ_REUEST_INTERRUPT", 14, 14, &umr_bitfield_default }, + { "DIGH_DP_FAST_TRAINING_COMPLETE_INTERRUPT", 28, 28, &umr_bitfield_default }, + { "DIGH_DP_VID_STREAM_DISABLE_INTERRUPT", 29, 29, &umr_bitfield_default }, + { "DISP_INTERRUPT_STATUS_CONTINUE22", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE22[] = { + { "DCPG_IHC_DOMAIN8_POWER_UP_INTERRUPT", 0, 0, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN9_POWER_UP_INTERRUPT", 1, 1, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN10_POWER_UP_INTERRUPT", 2, 2, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN11_POWER_UP_INTERRUPT", 3, 3, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN12_POWER_UP_INTERRUPT", 4, 4, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN13_POWER_UP_INTERRUPT", 5, 5, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN14_POWER_UP_INTERRUPT", 6, 6, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN15_POWER_UP_INTERRUPT", 7, 7, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN8_POWER_DOWN_INTERRUPT", 8, 8, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN9_POWER_DOWN_INTERRUPT", 9, 9, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN10_POWER_DOWN_INTERRUPT", 10, 10, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN11_POWER_DOWN_INTERRUPT", 11, 11, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN12_POWER_DOWN_INTERRUPT", 12, 12, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN13_POWER_DOWN_INTERRUPT", 13, 13, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN14_POWER_DOWN_INTERRUPT", 14, 14, &umr_bitfield_default }, + { "DCPG_IHC_DOMAIN15_POWER_DOWN_INTERRUPT", 15, 15, &umr_bitfield_default }, + { "ABM0_HG_READY_INT", 16, 16, &umr_bitfield_default }, + { "ABM0_LS_READY_INT", 17, 17, &umr_bitfield_default }, + { "ABM0_BL_UPDATE_INT", 18, 18, &umr_bitfield_default }, + { "OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT", 19, 19, &umr_bitfield_default }, + { "OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT", 20, 20, &umr_bitfield_default }, + { "OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT", 21, 21, &umr_bitfield_default }, + { "OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT", 22, 22, &umr_bitfield_default }, + { "OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT", 23, 23, &umr_bitfield_default }, + { "OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPU_TIMER_START_POSITION_VREADY[] = { + { "DC_GPU_TIMER_START_POSITION_D1_VREADY", 0, 2, &umr_bitfield_default }, + { "DC_GPU_TIMER_START_POSITION_D2_VREADY", 4, 6, &umr_bitfield_default }, + { "DC_GPU_TIMER_START_POSITION_D3_VREADY", 8, 10, &umr_bitfield_default }, + { "DC_GPU_TIMER_START_POSITION_D4_VREADY", 12, 14, &umr_bitfield_default }, + { "DC_GPU_TIMER_START_POSITION_D5_VREADY", 16, 18, &umr_bitfield_default }, + { "DC_GPU_TIMER_START_POSITION_D6_VREADY", 20, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPU_TIMER_START_POSITION_FLIP[] = { + { "DC_GPU_TIMER_START_POSITION_D1_FLIP", 0, 2, &umr_bitfield_default }, + { "DC_GPU_TIMER_START_POSITION_D2_FLIP", 4, 6, &umr_bitfield_default }, + { "DC_GPU_TIMER_START_POSITION_D3_FLIP", 8, 10, &umr_bitfield_default }, + { "DC_GPU_TIMER_START_POSITION_D4_FLIP", 12, 14, &umr_bitfield_default }, + { "DC_GPU_TIMER_START_POSITION_D5_FLIP", 16, 18, &umr_bitfield_default }, + { "DC_GPU_TIMER_START_POSITION_D6_FLIP", 20, 22, &umr_bitfield_default }, + { "DC_GPU_TIMER_START_POSITION_D7_FLIP", 24, 26, &umr_bitfield_default }, + { "DC_GPU_TIMER_START_POSITION_D8_FLIP", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK[] = { + { "DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_NO_LOCK", 0, 2, &umr_bitfield_default }, + { "DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_NO_LOCK", 4, 6, &umr_bitfield_default }, + { "DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_NO_LOCK", 8, 10, &umr_bitfield_default }, + { "DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_NO_LOCK", 12, 14, &umr_bitfield_default }, + { "DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_NO_LOCK", 16, 18, &umr_bitfield_default }, + { "DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_NO_LOCK", 20, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPU_TIMER_START_POSITION_FLIP_AWAY[] = { + { "DC_GPU_TIMER_START_POSITION_D1_FLIP_AWAY", 0, 2, &umr_bitfield_default }, + { "DC_GPU_TIMER_START_POSITION_D2_FLIP_AWAY", 4, 6, &umr_bitfield_default }, + { "DC_GPU_TIMER_START_POSITION_D3_FLIP_AWAY", 8, 10, &umr_bitfield_default }, + { "DC_GPU_TIMER_START_POSITION_D4_FLIP_AWAY", 12, 14, &umr_bitfield_default }, + { "DC_GPU_TIMER_START_POSITION_D5_FLIP_AWAY", 16, 18, &umr_bitfield_default }, + { "DC_GPU_TIMER_START_POSITION_D6_FLIP_AWAY", 20, 22, &umr_bitfield_default }, + { "DC_GPU_TIMER_START_POSITION_D7_FLIP_AWAY", 24, 26, &umr_bitfield_default }, + { "DC_GPU_TIMER_START_POSITION_D8_FLIP_AWAY", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNV0_WB_ENABLE[] = { + { "WB_ENABLE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNV0_WB_EC_CONFIG[] = { + { "DISPCLK_R_WB_GATE_DIS", 0, 0, &umr_bitfield_default }, + { "DISPCLK_G_WB_GATE_DIS", 1, 1, &umr_bitfield_default }, + { "DISPCLK_G_WBSCL_GATE_DIS", 2, 2, &umr_bitfield_default }, + { "WB_TEST_CLK_SEL", 3, 6, &umr_bitfield_default }, + { "WB_LB_LS_DIS", 7, 7, &umr_bitfield_default }, + { "WB_LB_SD_DIS", 8, 8, &umr_bitfield_default }, + { "WB_LUT_LS_DIS", 9, 9, &umr_bitfield_default }, + { "WBSCL_LB_MEM_PWR_MODE_SEL", 12, 13, &umr_bitfield_default }, + { "WBSCL_LB_MEM_PWR_DIS", 14, 14, &umr_bitfield_default }, + { "WBSCL_LB_MEM_PWR_FORCE", 15, 16, &umr_bitfield_default }, + { "WBSCL_LB_MEM_PWR_STATE_SM", 17, 18, &umr_bitfield_default }, + { "WBSCL_LB_MEM_PWR_STATE_BG", 19, 20, &umr_bitfield_default }, + { "WBSCL_LB_MEM_PWR_STATE", 21, 22, &umr_bitfield_default }, + { "WB_RAM_PW_SAVE_MODE", 23, 23, &umr_bitfield_default }, + { "LB_MEM_PWR_STATE_SM", 24, 25, &umr_bitfield_default }, + { "LB_MEM_PWR_STATE_BG", 26, 27, &umr_bitfield_default }, + { "LB_MEM_PWR_STATE", 28, 29, &umr_bitfield_default }, + { "LUT_MEM_PWR_STATE", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNV0_CNV_MODE[] = { + { "CNV_FRAME_CAPTURE_RATE", 8, 9, &umr_bitfield_default }, + { "CNV_WINDOW_CROP_EN", 12, 12, &umr_bitfield_default }, + { "CNV_STEREO_TYPE", 13, 14, &umr_bitfield_default }, + { "CNV_INTERLACED_MODE", 15, 15, &umr_bitfield_default }, + { "CNV_EYE_SELECTION", 16, 17, &umr_bitfield_default }, + { "CNV_STEREO_POLARITY", 18, 18, &umr_bitfield_default }, + { "CNV_INTERLACED_FIELD_ORDER", 19, 19, &umr_bitfield_default }, + { "CNV_STEREO_SPLIT", 20, 20, &umr_bitfield_default }, + { "CNV_NEW_CONTENT", 24, 24, &umr_bitfield_default }, + { "CNV_FRAME_CAPTURE_EN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNV0_CNV_WINDOW_START[] = { + { "CNV_WINDOW_START_X", 0, 11, &umr_bitfield_default }, + { "CNV_WINDOW_START_Y", 16, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNV0_CNV_WINDOW_SIZE[] = { + { "CNV_WINDOW_WIDTH", 0, 11, &umr_bitfield_default }, + { "CNV_WINDOW_HEIGHT", 16, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNV0_CNV_UPDATE[] = { + { "CNV_UPDATE_PENDING", 0, 0, &umr_bitfield_default }, + { "CNV_UPDATE_TAKEN", 8, 8, &umr_bitfield_default }, + { "CNV_UPDATE_LOCK", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNV0_CNV_SOURCE_SIZE[] = { + { "CNV_SOURCE_WIDTH", 0, 14, &umr_bitfield_default }, + { "CNV_SOURCE_HEIGHT", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNV0_CNV_CSC_CONTROL[] = { + { "CNV_CSC_BYPASS", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNV0_CNV_CSC_C11_C12[] = { + { "CNV_CSC_C11", 0, 12, &umr_bitfield_default }, + { "CNV_CSC_C12", 16, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNV0_CNV_CSC_C13_C14[] = { + { "CNV_CSC_C13", 0, 12, &umr_bitfield_default }, + { "CNV_CSC_C14", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNV0_CNV_CSC_C21_C22[] = { + { "CNV_CSC_C21", 0, 12, &umr_bitfield_default }, + { "CNV_CSC_C22", 16, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNV0_CNV_CSC_C23_C24[] = { + { "CNV_CSC_C23", 0, 12, &umr_bitfield_default }, + { "CNV_CSC_C24", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNV0_CNV_CSC_C31_C32[] = { + { "CNV_CSC_C31", 0, 12, &umr_bitfield_default }, + { "CNV_CSC_C32", 16, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNV0_CNV_CSC_C33_C34[] = { + { "CNV_CSC_C33", 0, 12, &umr_bitfield_default }, + { "CNV_CSC_C34", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNV0_CNV_CSC_ROUND_OFFSET_R[] = { + { "CNV_CSC_ROUND_OFFSET_R", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNV0_CNV_CSC_ROUND_OFFSET_G[] = { + { "CNV_CSC_ROUND_OFFSET_G", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNV0_CNV_CSC_ROUND_OFFSET_B[] = { + { "CNV_CSC_ROUND_OFFSET_B", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNV0_CNV_CSC_CLAMP_R[] = { + { "CNV_CSC_CLAMP_UPPER_R", 0, 15, &umr_bitfield_default }, + { "CNV_CSC_CLAMP_LOWER_R", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNV0_CNV_CSC_CLAMP_G[] = { + { "CNV_CSC_CLAMP_UPPER_G", 0, 15, &umr_bitfield_default }, + { "CNV_CSC_CLAMP_LOWER_G", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNV0_CNV_CSC_CLAMP_B[] = { + { "CNV_CSC_CLAMP_UPPER_B", 0, 15, &umr_bitfield_default }, + { "CNV_CSC_CLAMP_LOWER_B", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNV0_CNV_TEST_CNTL[] = { + { "CNV_TEST_CRC_EN", 4, 4, &umr_bitfield_default }, + { "CNV_TEST_CRC_CONT_EN", 8, 8, &umr_bitfield_default }, + { "CNV_TEST_CRC_DE_ONLY", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNV0_CNV_TEST_CRC_RED[] = { + { "CNV_TEST_CRC_RED_MASK", 4, 15, &umr_bitfield_default }, + { "CNV_TEST_CRC_SIG_RED", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNV0_CNV_TEST_CRC_GREEN[] = { + { "CNV_TEST_CRC_GREEN_MASK", 4, 15, &umr_bitfield_default }, + { "CNV_TEST_CRC_SIG_GREEN", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNV0_CNV_TEST_CRC_BLUE[] = { + { "CNV_TEST_CRC_BLUE_MASK", 4, 15, &umr_bitfield_default }, + { "CNV_TEST_CRC_SIG_BLUE", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNV0_CNV_INPUT_SELECT[] = { + { "CNV_INPUT_SRC_SELECT", 0, 1, &umr_bitfield_default }, + { "CNV_INPUT_PIPE_SELECT", 2, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNV0_WB_SOFT_RESET[] = { + { "WB_SOFT_RESET", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNV0_WB_WARM_UP_MODE_CTL1[] = { + { "WIDTH_WARMUP", 0, 14, &umr_bitfield_default }, + { "HEIGHT_WARMUP", 16, 30, &umr_bitfield_default }, + { "GMC_WARM_UP_ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNV0_WB_WARM_UP_MODE_CTL2[] = { + { "DATA_VALUE_WARMUP", 0, 7, &umr_bitfield_default }, + { "MODE_WARMUP", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWBSCL0_WBSCL_COEF_RAM_SELECT[] = { + { "WBSCL_COEF_RAM_TAP_PAIR_IDX", 0, 2, &umr_bitfield_default }, + { "WBSCL_COEF_RAM_PHASE", 8, 11, &umr_bitfield_default }, + { "WBSCL_COEF_RAM_FILTER_TYPE", 16, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWBSCL0_WBSCL_COEF_RAM_TAP_DATA[] = { + { "WBSCL_COEF_RAM_EVEN_TAP_COEF", 0, 13, &umr_bitfield_default }, + { "WBSCL_COEF_RAM_EVEN_TAP_COEF_EN", 15, 15, &umr_bitfield_default }, + { "WBSCL_COEF_RAM_ODD_TAP_COEF", 16, 29, &umr_bitfield_default }, + { "WBSCL_COEF_RAM_ODD_TAP_COEF_EN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWBSCL0_WBSCL_MODE[] = { + { "WBSCL_MODE", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWBSCL0_WBSCL_TAP_CONTROL[] = { + { "WBSCL_V_NUM_OF_TAPS_Y_RGB", 0, 3, &umr_bitfield_default }, + { "WBSCL_V_NUM_OF_TAPS_CBCR", 4, 7, &umr_bitfield_default }, + { "WBSCL_H_NUM_OF_TAPS_Y_RGB", 8, 11, &umr_bitfield_default }, + { "WBSCL_H_NUM_OF_TAPS_CBCR", 12, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWBSCL0_WBSCL_DEST_SIZE[] = { + { "WBSCL_DEST_HEIGHT", 0, 14, &umr_bitfield_default }, + { "WBSCL_DEST_WIDTH", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWBSCL0_WBSCL_HORZ_FILTER_SCALE_RATIO[] = { + { "WBSCL_H_SCALE_RATIO", 0, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWBSCL0_WBSCL_HORZ_FILTER_INIT_Y_RGB[] = { + { "WBSCL_H_INIT_FRAC_Y_RGB", 0, 23, &umr_bitfield_default }, + { "WBSCL_H_INIT_INT_Y_RGB", 24, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWBSCL0_WBSCL_HORZ_FILTER_INIT_CBCR[] = { + { "WBSCL_H_INIT_FRAC_CBCR", 0, 23, &umr_bitfield_default }, + { "WBSCL_H_INIT_INT_CBCR", 24, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWBSCL0_WBSCL_VERT_FILTER_SCALE_RATIO[] = { + { "WBSCL_V_SCALE_RATIO", 0, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWBSCL0_WBSCL_VERT_FILTER_INIT_Y_RGB[] = { + { "WBSCL_V_INIT_FRAC_Y_RGB", 0, 23, &umr_bitfield_default }, + { "WBSCL_V_INIT_INT_Y_RGB", 24, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWBSCL0_WBSCL_VERT_FILTER_INIT_CBCR[] = { + { "WBSCL_V_INIT_FRAC_CBCR", 0, 23, &umr_bitfield_default }, + { "WBSCL_V_INIT_INT_CBCR", 24, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWBSCL0_WBSCL_ROUND_OFFSET[] = { + { "WBSCL_ROUND_OFFSET_Y_RGB", 0, 15, &umr_bitfield_default }, + { "WBSCL_ROUND_OFFSET_CBCR", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWBSCL0_WBSCL_CLAMP[] = { + { "WBSCL_CLAMP_UPPER_Y_RGB", 0, 7, &umr_bitfield_default }, + { "WBSCL_CLAMP_LOWER_Y_RGB", 8, 15, &umr_bitfield_default }, + { "WBSCL_CLAMP_UPPER_CBCR", 16, 23, &umr_bitfield_default }, + { "WBSCL_CLAMP_LOWER_CBCR", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWBSCL0_WBSCL_OVERFLOW_STATUS[] = { + { "WBSCL_DATA_OVERFLOW_FLAG", 0, 0, &umr_bitfield_default }, + { "WBSCL_DATA_OVERFLOW_ACK", 8, 8, &umr_bitfield_default }, + { "WBSCL_DATA_OVERFLOW_MASK", 12, 12, &umr_bitfield_default }, + { "WBSCL_DATA_OVERFLOW_INT_STATUS", 16, 16, &umr_bitfield_default }, + { "WBSCL_DATA_OVERFLOW_INT_TYPE", 20, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWBSCL0_WBSCL_COEF_RAM_CONFLICT_STATUS[] = { + { "WBSCL_HOST_CONFLICT_FLAG", 0, 0, &umr_bitfield_default }, + { "WBSCL_HOST_CONFLICT_ACK", 8, 8, &umr_bitfield_default }, + { "WBSCL_HOST_CONFLICT_MASK", 12, 12, &umr_bitfield_default }, + { "WBSCL_HOST_CONFLICT_INT_STATUS", 16, 16, &umr_bitfield_default }, + { "WBSCL_HOST_CONFLICT_INT_TYPE", 20, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWBSCL0_WBSCL_OUTSIDE_PIX_STRATEGY[] = { + { "WBSCL_OUTSIDE_PIX_STRATEGY", 0, 0, &umr_bitfield_default }, + { "WBSCL_BLACK_COLOR_B_CB", 8, 15, &umr_bitfield_default }, + { "WBSCL_BLACK_COLOR_G_Y", 16, 23, &umr_bitfield_default }, + { "WBSCL_BLACK_COLOR_R_CR", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWBSCL0_WBSCL_TEST_CNTL[] = { + { "WBSCL_TEST_CRC_EN", 4, 4, &umr_bitfield_default }, + { "WBSCL_TEST_CRC_CONT_EN", 8, 8, &umr_bitfield_default }, + { "WBSCL_TEST_CRC_DE_ONLY", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWBSCL0_WBSCL_TEST_CRC_RED[] = { + { "WBSCL_TEST_CRC_RED_MASK", 8, 15, &umr_bitfield_default }, + { "WBSCL_TEST_CRC_SIG_RED", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWBSCL0_WBSCL_TEST_CRC_GREEN[] = { + { "WBSCL_TEST_CRC_GREEN_MASK", 0, 15, &umr_bitfield_default }, + { "WBSCL_TEST_CRC_SIG_GREEN", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWBSCL0_WBSCL_TEST_CRC_BLUE[] = { + { "WBSCL_TEST_CRC_BLUE_MASK", 8, 15, &umr_bitfield_default }, + { "WBSCL_TEST_CRC_SIG_BLUE", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWBSCL0_WBSCL_BACKPRESSURE_CNT_EN[] = { + { "WBSCL_BACKPRESSURE_CNT_EN", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWBSCL0_WB_MCIF_BACKPRESSURE_CNT[] = { + { "WB_MCIF_Y_MAX_BACKPRESSURE", 0, 15, &umr_bitfield_default }, + { "WB_MCIF_C_MAX_BACKPRESSURE", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWBSCL0_WBSCL_RAM_SHUTDOWN[] = { + { "WBSCL_RAM_SHUTDOWN_SEL", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON3_PERFCOUNTER_CNTL[] = { + { "PERFCOUNTER_EVENT_SEL", 0, 8, &umr_bitfield_default }, + { "PERFCOUNTER_CVALUE_SEL", 9, 11, &umr_bitfield_default }, + { "PERFCOUNTER_INC_MODE", 12, 14, &umr_bitfield_default }, + { "PERFCOUNTER_HW_CNTL_SEL", 15, 15, &umr_bitfield_default }, + { "PERFCOUNTER_RUNEN_MODE", 16, 16, &umr_bitfield_default }, + { "PERFCOUNTER_CNTOFF_START_DIS", 22, 22, &umr_bitfield_default }, + { "PERFCOUNTER_RESTART_EN", 23, 23, &umr_bitfield_default }, + { "PERFCOUNTER_INT_EN", 24, 24, &umr_bitfield_default }, + { "PERFCOUNTER_OFF_MASK", 25, 25, &umr_bitfield_default }, + { "PERFCOUNTER_ACTIVE", 26, 26, &umr_bitfield_default }, + { "PERFCOUNTER_CNTL_SEL", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON3_PERFCOUNTER_CNTL2[] = { + { "PERFCOUNTER_COUNTED_VALUE_TYPE", 0, 1, &umr_bitfield_default }, + { "PERFCOUNTER_HW_STOP1_SEL", 2, 2, &umr_bitfield_default }, + { "PERFCOUNTER_HW_STOP2_SEL", 3, 3, &umr_bitfield_default }, + { "PERFCOUNTER_CNTOFF_SEL", 8, 13, &umr_bitfield_default }, + { "PERFCOUNTER_CNTL2_SEL", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON3_PERFCOUNTER_STATE[] = { + { "PERFCOUNTER_CNT0_STATE", 0, 1, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL0", 2, 2, &umr_bitfield_default }, + { "PERFCOUNTER_CNT1_STATE", 4, 5, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL1", 6, 6, &umr_bitfield_default }, + { "PERFCOUNTER_CNT2_STATE", 8, 9, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL2", 10, 10, &umr_bitfield_default }, + { "PERFCOUNTER_CNT3_STATE", 12, 13, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL3", 14, 14, &umr_bitfield_default }, + { "PERFCOUNTER_CNT4_STATE", 16, 17, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL4", 18, 18, &umr_bitfield_default }, + { "PERFCOUNTER_CNT5_STATE", 20, 21, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL5", 22, 22, &umr_bitfield_default }, + { "PERFCOUNTER_CNT6_STATE", 24, 25, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL6", 26, 26, &umr_bitfield_default }, + { "PERFCOUNTER_CNT7_STATE", 28, 29, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL7", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON3_PERFMON_CNTL[] = { + { "PERFMON_STATE", 0, 1, &umr_bitfield_default }, + { "PERFMON_RPT_COUNT", 8, 27, &umr_bitfield_default }, + { "PERFMON_CNTOFF_AND_OR", 28, 28, &umr_bitfield_default }, + { "PERFMON_CNTOFF_INT_EN", 29, 29, &umr_bitfield_default }, + { "PERFMON_CNTOFF_INT_STATUS", 30, 30, &umr_bitfield_default }, + { "PERFMON_CNTOFF_INT_ACK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON3_PERFMON_CNTL2[] = { + { "PERFMON_CNTOFF_INT_TYPE", 0, 0, &umr_bitfield_default }, + { "PERFMON_CLK_ENABLE", 1, 1, &umr_bitfield_default }, + { "PERFMON_RUN_ENABLE_START_SEL", 2, 9, &umr_bitfield_default }, + { "PERFMON_RUN_ENABLE_STOP_SEL", 10, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC[] = { + { "PERFCOUNTER_INT0_STATUS", 0, 0, &umr_bitfield_default }, + { "PERFCOUNTER_INT1_STATUS", 1, 1, &umr_bitfield_default }, + { "PERFCOUNTER_INT2_STATUS", 2, 2, &umr_bitfield_default }, + { "PERFCOUNTER_INT3_STATUS", 3, 3, &umr_bitfield_default }, + { "PERFCOUNTER_INT4_STATUS", 4, 4, &umr_bitfield_default }, + { "PERFCOUNTER_INT5_STATUS", 5, 5, &umr_bitfield_default }, + { "PERFCOUNTER_INT6_STATUS", 6, 6, &umr_bitfield_default }, + { "PERFCOUNTER_INT7_STATUS", 7, 7, &umr_bitfield_default }, + { "PERFCOUNTER_INT0_ACK", 8, 8, &umr_bitfield_default }, + { "PERFCOUNTER_INT1_ACK", 9, 9, &umr_bitfield_default }, + { "PERFCOUNTER_INT2_ACK", 10, 10, &umr_bitfield_default }, + { "PERFCOUNTER_INT3_ACK", 11, 11, &umr_bitfield_default }, + { "PERFCOUNTER_INT4_ACK", 12, 12, &umr_bitfield_default }, + { "PERFCOUNTER_INT5_ACK", 13, 13, &umr_bitfield_default }, + { "PERFCOUNTER_INT6_ACK", 14, 14, &umr_bitfield_default }, + { "PERFCOUNTER_INT7_ACK", 15, 15, &umr_bitfield_default }, + { "PERFMON_CVALUE_HI", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON3_PERFMON_CVALUE_LOW[] = { + { "PERFMON_CVALUE_LOW", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON3_PERFMON_HI[] = { + { "PERFMON_HI", 0, 15, &umr_bitfield_default }, + { "PERFMON_READ_SEL", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON3_PERFMON_LOW[] = { + { "PERFMON_LOW", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNV1_WB_ENABLE[] = { + { "WB_ENABLE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNV1_WB_EC_CONFIG[] = { + { "DISPCLK_R_WB_GATE_DIS", 0, 0, &umr_bitfield_default }, + { "DISPCLK_G_WB_GATE_DIS", 1, 1, &umr_bitfield_default }, + { "DISPCLK_G_WBSCL_GATE_DIS", 2, 2, &umr_bitfield_default }, + { "WB_TEST_CLK_SEL", 3, 6, &umr_bitfield_default }, + { "WB_LB_LS_DIS", 7, 7, &umr_bitfield_default }, + { "WB_LB_SD_DIS", 8, 8, &umr_bitfield_default }, + { "WB_LUT_LS_DIS", 9, 9, &umr_bitfield_default }, + { "WBSCL_LB_MEM_PWR_MODE_SEL", 12, 13, &umr_bitfield_default }, + { "WBSCL_LB_MEM_PWR_DIS", 14, 14, &umr_bitfield_default }, + { "WBSCL_LB_MEM_PWR_FORCE", 15, 16, &umr_bitfield_default }, + { "WBSCL_LB_MEM_PWR_STATE_SM", 17, 18, &umr_bitfield_default }, + { "WBSCL_LB_MEM_PWR_STATE_BG", 19, 20, &umr_bitfield_default }, + { "WBSCL_LB_MEM_PWR_STATE", 21, 22, &umr_bitfield_default }, + { "WB_RAM_PW_SAVE_MODE", 23, 23, &umr_bitfield_default }, + { "LB_MEM_PWR_STATE_SM", 24, 25, &umr_bitfield_default }, + { "LB_MEM_PWR_STATE_BG", 26, 27, &umr_bitfield_default }, + { "LB_MEM_PWR_STATE", 28, 29, &umr_bitfield_default }, + { "LUT_MEM_PWR_STATE", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNV1_CNV_MODE[] = { + { "CNV_FRAME_CAPTURE_RATE", 8, 9, &umr_bitfield_default }, + { "CNV_WINDOW_CROP_EN", 12, 12, &umr_bitfield_default }, + { "CNV_STEREO_TYPE", 13, 14, &umr_bitfield_default }, + { "CNV_INTERLACED_MODE", 15, 15, &umr_bitfield_default }, + { "CNV_EYE_SELECTION", 16, 17, &umr_bitfield_default }, + { "CNV_STEREO_POLARITY", 18, 18, &umr_bitfield_default }, + { "CNV_INTERLACED_FIELD_ORDER", 19, 19, &umr_bitfield_default }, + { "CNV_STEREO_SPLIT", 20, 20, &umr_bitfield_default }, + { "CNV_NEW_CONTENT", 24, 24, &umr_bitfield_default }, + { "CNV_FRAME_CAPTURE_EN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNV1_CNV_WINDOW_START[] = { + { "CNV_WINDOW_START_X", 0, 11, &umr_bitfield_default }, + { "CNV_WINDOW_START_Y", 16, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNV1_CNV_WINDOW_SIZE[] = { + { "CNV_WINDOW_WIDTH", 0, 11, &umr_bitfield_default }, + { "CNV_WINDOW_HEIGHT", 16, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNV1_CNV_UPDATE[] = { + { "CNV_UPDATE_PENDING", 0, 0, &umr_bitfield_default }, + { "CNV_UPDATE_TAKEN", 8, 8, &umr_bitfield_default }, + { "CNV_UPDATE_LOCK", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNV1_CNV_SOURCE_SIZE[] = { + { "CNV_SOURCE_WIDTH", 0, 14, &umr_bitfield_default }, + { "CNV_SOURCE_HEIGHT", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNV1_CNV_CSC_CONTROL[] = { + { "CNV_CSC_BYPASS", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNV1_CNV_CSC_C11_C12[] = { + { "CNV_CSC_C11", 0, 12, &umr_bitfield_default }, + { "CNV_CSC_C12", 16, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNV1_CNV_CSC_C13_C14[] = { + { "CNV_CSC_C13", 0, 12, &umr_bitfield_default }, + { "CNV_CSC_C14", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNV1_CNV_CSC_C21_C22[] = { + { "CNV_CSC_C21", 0, 12, &umr_bitfield_default }, + { "CNV_CSC_C22", 16, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNV1_CNV_CSC_C23_C24[] = { + { "CNV_CSC_C23", 0, 12, &umr_bitfield_default }, + { "CNV_CSC_C24", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNV1_CNV_CSC_C31_C32[] = { + { "CNV_CSC_C31", 0, 12, &umr_bitfield_default }, + { "CNV_CSC_C32", 16, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNV1_CNV_CSC_C33_C34[] = { + { "CNV_CSC_C33", 0, 12, &umr_bitfield_default }, + { "CNV_CSC_C34", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNV1_CNV_CSC_ROUND_OFFSET_R[] = { + { "CNV_CSC_ROUND_OFFSET_R", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNV1_CNV_CSC_ROUND_OFFSET_G[] = { + { "CNV_CSC_ROUND_OFFSET_G", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNV1_CNV_CSC_ROUND_OFFSET_B[] = { + { "CNV_CSC_ROUND_OFFSET_B", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNV1_CNV_CSC_CLAMP_R[] = { + { "CNV_CSC_CLAMP_UPPER_R", 0, 15, &umr_bitfield_default }, + { "CNV_CSC_CLAMP_LOWER_R", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNV1_CNV_CSC_CLAMP_G[] = { + { "CNV_CSC_CLAMP_UPPER_G", 0, 15, &umr_bitfield_default }, + { "CNV_CSC_CLAMP_LOWER_G", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNV1_CNV_CSC_CLAMP_B[] = { + { "CNV_CSC_CLAMP_UPPER_B", 0, 15, &umr_bitfield_default }, + { "CNV_CSC_CLAMP_LOWER_B", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNV1_CNV_TEST_CNTL[] = { + { "CNV_TEST_CRC_EN", 4, 4, &umr_bitfield_default }, + { "CNV_TEST_CRC_CONT_EN", 8, 8, &umr_bitfield_default }, + { "CNV_TEST_CRC_DE_ONLY", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNV1_CNV_TEST_CRC_RED[] = { + { "CNV_TEST_CRC_RED_MASK", 4, 15, &umr_bitfield_default }, + { "CNV_TEST_CRC_SIG_RED", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNV1_CNV_TEST_CRC_GREEN[] = { + { "CNV_TEST_CRC_GREEN_MASK", 4, 15, &umr_bitfield_default }, + { "CNV_TEST_CRC_SIG_GREEN", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNV1_CNV_TEST_CRC_BLUE[] = { + { "CNV_TEST_CRC_BLUE_MASK", 4, 15, &umr_bitfield_default }, + { "CNV_TEST_CRC_SIG_BLUE", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNV1_CNV_INPUT_SELECT[] = { + { "CNV_INPUT_SRC_SELECT", 0, 1, &umr_bitfield_default }, + { "CNV_INPUT_PIPE_SELECT", 2, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNV1_WB_SOFT_RESET[] = { + { "WB_SOFT_RESET", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNV1_WB_WARM_UP_MODE_CTL1[] = { + { "WIDTH_WARMUP", 0, 14, &umr_bitfield_default }, + { "HEIGHT_WARMUP", 16, 30, &umr_bitfield_default }, + { "GMC_WARM_UP_ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNV1_WB_WARM_UP_MODE_CTL2[] = { + { "DATA_VALUE_WARMUP", 0, 7, &umr_bitfield_default }, + { "MODE_WARMUP", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWBSCL1_WBSCL_COEF_RAM_SELECT[] = { + { "WBSCL_COEF_RAM_TAP_PAIR_IDX", 0, 2, &umr_bitfield_default }, + { "WBSCL_COEF_RAM_PHASE", 8, 11, &umr_bitfield_default }, + { "WBSCL_COEF_RAM_FILTER_TYPE", 16, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWBSCL1_WBSCL_COEF_RAM_TAP_DATA[] = { + { "WBSCL_COEF_RAM_EVEN_TAP_COEF", 0, 13, &umr_bitfield_default }, + { "WBSCL_COEF_RAM_EVEN_TAP_COEF_EN", 15, 15, &umr_bitfield_default }, + { "WBSCL_COEF_RAM_ODD_TAP_COEF", 16, 29, &umr_bitfield_default }, + { "WBSCL_COEF_RAM_ODD_TAP_COEF_EN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWBSCL1_WBSCL_MODE[] = { + { "WBSCL_MODE", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWBSCL1_WBSCL_TAP_CONTROL[] = { + { "WBSCL_V_NUM_OF_TAPS_Y_RGB", 0, 3, &umr_bitfield_default }, + { "WBSCL_V_NUM_OF_TAPS_CBCR", 4, 7, &umr_bitfield_default }, + { "WBSCL_H_NUM_OF_TAPS_Y_RGB", 8, 11, &umr_bitfield_default }, + { "WBSCL_H_NUM_OF_TAPS_CBCR", 12, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWBSCL1_WBSCL_DEST_SIZE[] = { + { "WBSCL_DEST_HEIGHT", 0, 14, &umr_bitfield_default }, + { "WBSCL_DEST_WIDTH", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWBSCL1_WBSCL_HORZ_FILTER_SCALE_RATIO[] = { + { "WBSCL_H_SCALE_RATIO", 0, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWBSCL1_WBSCL_HORZ_FILTER_INIT_Y_RGB[] = { + { "WBSCL_H_INIT_FRAC_Y_RGB", 0, 23, &umr_bitfield_default }, + { "WBSCL_H_INIT_INT_Y_RGB", 24, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWBSCL1_WBSCL_HORZ_FILTER_INIT_CBCR[] = { + { "WBSCL_H_INIT_FRAC_CBCR", 0, 23, &umr_bitfield_default }, + { "WBSCL_H_INIT_INT_CBCR", 24, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWBSCL1_WBSCL_VERT_FILTER_SCALE_RATIO[] = { + { "WBSCL_V_SCALE_RATIO", 0, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWBSCL1_WBSCL_VERT_FILTER_INIT_Y_RGB[] = { + { "WBSCL_V_INIT_FRAC_Y_RGB", 0, 23, &umr_bitfield_default }, + { "WBSCL_V_INIT_INT_Y_RGB", 24, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWBSCL1_WBSCL_VERT_FILTER_INIT_CBCR[] = { + { "WBSCL_V_INIT_FRAC_CBCR", 0, 23, &umr_bitfield_default }, + { "WBSCL_V_INIT_INT_CBCR", 24, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWBSCL1_WBSCL_ROUND_OFFSET[] = { + { "WBSCL_ROUND_OFFSET_Y_RGB", 0, 15, &umr_bitfield_default }, + { "WBSCL_ROUND_OFFSET_CBCR", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWBSCL1_WBSCL_CLAMP[] = { + { "WBSCL_CLAMP_UPPER_Y_RGB", 0, 7, &umr_bitfield_default }, + { "WBSCL_CLAMP_LOWER_Y_RGB", 8, 15, &umr_bitfield_default }, + { "WBSCL_CLAMP_UPPER_CBCR", 16, 23, &umr_bitfield_default }, + { "WBSCL_CLAMP_LOWER_CBCR", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWBSCL1_WBSCL_OVERFLOW_STATUS[] = { + { "WBSCL_DATA_OVERFLOW_FLAG", 0, 0, &umr_bitfield_default }, + { "WBSCL_DATA_OVERFLOW_ACK", 8, 8, &umr_bitfield_default }, + { "WBSCL_DATA_OVERFLOW_MASK", 12, 12, &umr_bitfield_default }, + { "WBSCL_DATA_OVERFLOW_INT_STATUS", 16, 16, &umr_bitfield_default }, + { "WBSCL_DATA_OVERFLOW_INT_TYPE", 20, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWBSCL1_WBSCL_COEF_RAM_CONFLICT_STATUS[] = { + { "WBSCL_HOST_CONFLICT_FLAG", 0, 0, &umr_bitfield_default }, + { "WBSCL_HOST_CONFLICT_ACK", 8, 8, &umr_bitfield_default }, + { "WBSCL_HOST_CONFLICT_MASK", 12, 12, &umr_bitfield_default }, + { "WBSCL_HOST_CONFLICT_INT_STATUS", 16, 16, &umr_bitfield_default }, + { "WBSCL_HOST_CONFLICT_INT_TYPE", 20, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWBSCL1_WBSCL_OUTSIDE_PIX_STRATEGY[] = { + { "WBSCL_OUTSIDE_PIX_STRATEGY", 0, 0, &umr_bitfield_default }, + { "WBSCL_BLACK_COLOR_B_CB", 8, 15, &umr_bitfield_default }, + { "WBSCL_BLACK_COLOR_G_Y", 16, 23, &umr_bitfield_default }, + { "WBSCL_BLACK_COLOR_R_CR", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWBSCL1_WBSCL_TEST_CNTL[] = { + { "WBSCL_TEST_CRC_EN", 4, 4, &umr_bitfield_default }, + { "WBSCL_TEST_CRC_CONT_EN", 8, 8, &umr_bitfield_default }, + { "WBSCL_TEST_CRC_DE_ONLY", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWBSCL1_WBSCL_TEST_CRC_RED[] = { + { "WBSCL_TEST_CRC_RED_MASK", 8, 15, &umr_bitfield_default }, + { "WBSCL_TEST_CRC_SIG_RED", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWBSCL1_WBSCL_TEST_CRC_GREEN[] = { + { "WBSCL_TEST_CRC_GREEN_MASK", 0, 15, &umr_bitfield_default }, + { "WBSCL_TEST_CRC_SIG_GREEN", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWBSCL1_WBSCL_TEST_CRC_BLUE[] = { + { "WBSCL_TEST_CRC_BLUE_MASK", 8, 15, &umr_bitfield_default }, + { "WBSCL_TEST_CRC_SIG_BLUE", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWBSCL1_WBSCL_BACKPRESSURE_CNT_EN[] = { + { "WBSCL_BACKPRESSURE_CNT_EN", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWBSCL1_WB_MCIF_BACKPRESSURE_CNT[] = { + { "WB_MCIF_Y_MAX_BACKPRESSURE", 0, 15, &umr_bitfield_default }, + { "WB_MCIF_C_MAX_BACKPRESSURE", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWBSCL1_WBSCL_RAM_SHUTDOWN[] = { + { "WBSCL_RAM_SHUTDOWN_SEL", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON4_PERFCOUNTER_CNTL[] = { + { "PERFCOUNTER_EVENT_SEL", 0, 8, &umr_bitfield_default }, + { "PERFCOUNTER_CVALUE_SEL", 9, 11, &umr_bitfield_default }, + { "PERFCOUNTER_INC_MODE", 12, 14, &umr_bitfield_default }, + { "PERFCOUNTER_HW_CNTL_SEL", 15, 15, &umr_bitfield_default }, + { "PERFCOUNTER_RUNEN_MODE", 16, 16, &umr_bitfield_default }, + { "PERFCOUNTER_CNTOFF_START_DIS", 22, 22, &umr_bitfield_default }, + { "PERFCOUNTER_RESTART_EN", 23, 23, &umr_bitfield_default }, + { "PERFCOUNTER_INT_EN", 24, 24, &umr_bitfield_default }, + { "PERFCOUNTER_OFF_MASK", 25, 25, &umr_bitfield_default }, + { "PERFCOUNTER_ACTIVE", 26, 26, &umr_bitfield_default }, + { "PERFCOUNTER_CNTL_SEL", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON4_PERFCOUNTER_CNTL2[] = { + { "PERFCOUNTER_COUNTED_VALUE_TYPE", 0, 1, &umr_bitfield_default }, + { "PERFCOUNTER_HW_STOP1_SEL", 2, 2, &umr_bitfield_default }, + { "PERFCOUNTER_HW_STOP2_SEL", 3, 3, &umr_bitfield_default }, + { "PERFCOUNTER_CNTOFF_SEL", 8, 13, &umr_bitfield_default }, + { "PERFCOUNTER_CNTL2_SEL", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON4_PERFCOUNTER_STATE[] = { + { "PERFCOUNTER_CNT0_STATE", 0, 1, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL0", 2, 2, &umr_bitfield_default }, + { "PERFCOUNTER_CNT1_STATE", 4, 5, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL1", 6, 6, &umr_bitfield_default }, + { "PERFCOUNTER_CNT2_STATE", 8, 9, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL2", 10, 10, &umr_bitfield_default }, + { "PERFCOUNTER_CNT3_STATE", 12, 13, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL3", 14, 14, &umr_bitfield_default }, + { "PERFCOUNTER_CNT4_STATE", 16, 17, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL4", 18, 18, &umr_bitfield_default }, + { "PERFCOUNTER_CNT5_STATE", 20, 21, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL5", 22, 22, &umr_bitfield_default }, + { "PERFCOUNTER_CNT6_STATE", 24, 25, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL6", 26, 26, &umr_bitfield_default }, + { "PERFCOUNTER_CNT7_STATE", 28, 29, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL7", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON4_PERFMON_CNTL[] = { + { "PERFMON_STATE", 0, 1, &umr_bitfield_default }, + { "PERFMON_RPT_COUNT", 8, 27, &umr_bitfield_default }, + { "PERFMON_CNTOFF_AND_OR", 28, 28, &umr_bitfield_default }, + { "PERFMON_CNTOFF_INT_EN", 29, 29, &umr_bitfield_default }, + { "PERFMON_CNTOFF_INT_STATUS", 30, 30, &umr_bitfield_default }, + { "PERFMON_CNTOFF_INT_ACK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON4_PERFMON_CNTL2[] = { + { "PERFMON_CNTOFF_INT_TYPE", 0, 0, &umr_bitfield_default }, + { "PERFMON_CLK_ENABLE", 1, 1, &umr_bitfield_default }, + { "PERFMON_RUN_ENABLE_START_SEL", 2, 9, &umr_bitfield_default }, + { "PERFMON_RUN_ENABLE_STOP_SEL", 10, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC[] = { + { "PERFCOUNTER_INT0_STATUS", 0, 0, &umr_bitfield_default }, + { "PERFCOUNTER_INT1_STATUS", 1, 1, &umr_bitfield_default }, + { "PERFCOUNTER_INT2_STATUS", 2, 2, &umr_bitfield_default }, + { "PERFCOUNTER_INT3_STATUS", 3, 3, &umr_bitfield_default }, + { "PERFCOUNTER_INT4_STATUS", 4, 4, &umr_bitfield_default }, + { "PERFCOUNTER_INT5_STATUS", 5, 5, &umr_bitfield_default }, + { "PERFCOUNTER_INT6_STATUS", 6, 6, &umr_bitfield_default }, + { "PERFCOUNTER_INT7_STATUS", 7, 7, &umr_bitfield_default }, + { "PERFCOUNTER_INT0_ACK", 8, 8, &umr_bitfield_default }, + { "PERFCOUNTER_INT1_ACK", 9, 9, &umr_bitfield_default }, + { "PERFCOUNTER_INT2_ACK", 10, 10, &umr_bitfield_default }, + { "PERFCOUNTER_INT3_ACK", 11, 11, &umr_bitfield_default }, + { "PERFCOUNTER_INT4_ACK", 12, 12, &umr_bitfield_default }, + { "PERFCOUNTER_INT5_ACK", 13, 13, &umr_bitfield_default }, + { "PERFCOUNTER_INT6_ACK", 14, 14, &umr_bitfield_default }, + { "PERFCOUNTER_INT7_ACK", 15, 15, &umr_bitfield_default }, + { "PERFMON_CVALUE_HI", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON4_PERFMON_CVALUE_LOW[] = { + { "PERFMON_CVALUE_LOW", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON4_PERFMON_HI[] = { + { "PERFMON_HI", 0, 15, &umr_bitfield_default }, + { "PERFMON_READ_SEL", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON4_PERFMON_LOW[] = { + { "PERFMON_LOW", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL[] = { + { "MCIF_WB_BUFMGR_ENABLE", 0, 0, &umr_bitfield_default }, + { "MCIF_WB_BUF_DUALSIZE_REQ", 1, 1, &umr_bitfield_default }, + { "MCIF_WB_BUFMGR_SW_INT_EN", 4, 4, &umr_bitfield_default }, + { "MCIF_WB_BUFMGR_SW_INT_ACK", 5, 5, &umr_bitfield_default }, + { "MCIF_WB_BUFMGR_SW_SLICE_INT_EN", 6, 6, &umr_bitfield_default }, + { "MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN", 7, 7, &umr_bitfield_default }, + { "MCIF_WB_BUFMGR_SW_LOCK", 8, 11, &umr_bitfield_default }, + { "MCIF_WB_P_VMID", 16, 19, &umr_bitfield_default }, + { "MCIF_WB_BUF_ADDR_FENCE_EN", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R[] = { + { "MCIF_WB_BUFMGR_CUR_LINE_R", 0, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS[] = { + { "MCIF_WB_BUFMGR_VCE_INT_STATUS", 0, 0, &umr_bitfield_default }, + { "MCIF_WB_BUFMGR_SW_INT_STATUS", 1, 1, &umr_bitfield_default }, + { "MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS", 2, 2, &umr_bitfield_default }, + { "MCIF_WB_BUFMGR_CUR_BUF", 4, 6, &umr_bitfield_default }, + { "MCIF_WB_BUF_DUALSIZE_STATUS", 7, 7, &umr_bitfield_default }, + { "MCIF_WB_BUFMGR_BUFTAG", 8, 11, &umr_bitfield_default }, + { "MCIF_WB_BUFMGR_CUR_LINE_L", 12, 24, &umr_bitfield_default }, + { "MCIF_WB_BUFMGR_NEXT_BUF", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB0_MCIF_WB_BUF_PITCH[] = { + { "MCIF_WB_BUF_LUMA_PITCH", 8, 15, &umr_bitfield_default }, + { "MCIF_WB_BUF_CHROMA_PITCH", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB0_MCIF_WB_BUF_1_STATUS[] = { + { "MCIF_WB_BUF_1_ACTIVE", 0, 0, &umr_bitfield_default }, + { "MCIF_WB_BUF_1_SW_LOCKED", 1, 1, &umr_bitfield_default }, + { "MCIF_WB_BUF_1_VCE_LOCKED", 2, 2, &umr_bitfield_default }, + { "MCIF_WB_BUF_1_OVERFLOW", 3, 3, &umr_bitfield_default }, + { "MCIF_WB_BUF_1_DISABLE", 4, 4, &umr_bitfield_default }, + { "MCIF_WB_BUF_1_MODE", 5, 7, &umr_bitfield_default }, + { "MCIF_WB_BUF_1_BUFTAG", 8, 11, &umr_bitfield_default }, + { "MCIF_WB_BUF_1_NXT_BUF", 12, 14, &umr_bitfield_default }, + { "MCIF_WB_BUF_1_FIELD", 15, 15, &umr_bitfield_default }, + { "MCIF_WB_BUF_1_CUR_LINE_L", 16, 28, &umr_bitfield_default }, + { "MCIF_WB_BUF_1_LONG_LINE_ERROR", 29, 29, &umr_bitfield_default }, + { "MCIF_WB_BUF_1_SHORT_LINE_ERROR", 30, 30, &umr_bitfield_default }, + { "MCIF_WB_BUF_1_FRAME_LENGTH_ERROR", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2[] = { + { "MCIF_WB_BUF_1_CUR_LINE_R", 0, 12, &umr_bitfield_default }, + { "MCIF_WB_BUF_1_NEW_CONTENT", 13, 13, &umr_bitfield_default }, + { "MCIF_WB_BUF_1_COLOR_DEPTH", 14, 14, &umr_bitfield_default }, + { "MCIF_WB_BUF_1_Y_OVERRUN", 17, 17, &umr_bitfield_default }, + { "MCIF_WB_BUF_1_C_OVERRUN", 18, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB0_MCIF_WB_BUF_2_STATUS[] = { + { "MCIF_WB_BUF_2_ACTIVE", 0, 0, &umr_bitfield_default }, + { "MCIF_WB_BUF_2_SW_LOCKED", 1, 1, &umr_bitfield_default }, + { "MCIF_WB_BUF_2_VCE_LOCKED", 2, 2, &umr_bitfield_default }, + { "MCIF_WB_BUF_2_OVERFLOW", 3, 3, &umr_bitfield_default }, + { "MCIF_WB_BUF_2_DISABLE", 4, 4, &umr_bitfield_default }, + { "MCIF_WB_BUF_2_MODE", 5, 7, &umr_bitfield_default }, + { "MCIF_WB_BUF_2_BUFTAG", 8, 11, &umr_bitfield_default }, + { "MCIF_WB_BUF_2_NXT_BUF", 12, 14, &umr_bitfield_default }, + { "MCIF_WB_BUF_2_FIELD", 15, 15, &umr_bitfield_default }, + { "MCIF_WB_BUF_2_CUR_LINE_L", 16, 28, &umr_bitfield_default }, + { "MCIF_WB_BUF_2_LONG_LINE_ERROR", 29, 29, &umr_bitfield_default }, + { "MCIF_WB_BUF_2_SHORT_LINE_ERROR", 30, 30, &umr_bitfield_default }, + { "MCIF_WB_BUF_2_FRAME_LENGTH_ERROR", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2[] = { + { "MCIF_WB_BUF_2_CUR_LINE_R", 0, 12, &umr_bitfield_default }, + { "MCIF_WB_BUF_2_NEW_CONTENT", 13, 13, &umr_bitfield_default }, + { "MCIF_WB_BUF_2_COLOR_DEPTH", 14, 14, &umr_bitfield_default }, + { "MCIF_WB_BUF_2_Y_OVERRUN", 17, 17, &umr_bitfield_default }, + { "MCIF_WB_BUF_2_C_OVERRUN", 18, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB0_MCIF_WB_BUF_3_STATUS[] = { + { "MCIF_WB_BUF_3_ACTIVE", 0, 0, &umr_bitfield_default }, + { "MCIF_WB_BUF_3_SW_LOCKED", 1, 1, &umr_bitfield_default }, + { "MCIF_WB_BUF_3_VCE_LOCKED", 2, 2, &umr_bitfield_default }, + { "MCIF_WB_BUF_3_OVERFLOW", 3, 3, &umr_bitfield_default }, + { "MCIF_WB_BUF_3_DISABLE", 4, 4, &umr_bitfield_default }, + { "MCIF_WB_BUF_3_MODE", 5, 7, &umr_bitfield_default }, + { "MCIF_WB_BUF_3_BUFTAG", 8, 11, &umr_bitfield_default }, + { "MCIF_WB_BUF_3_NXT_BUF", 12, 14, &umr_bitfield_default }, + { "MCIF_WB_BUF_3_FIELD", 15, 15, &umr_bitfield_default }, + { "MCIF_WB_BUF_3_CUR_LINE_L", 16, 28, &umr_bitfield_default }, + { "MCIF_WB_BUF_3_LONG_LINE_ERROR", 29, 29, &umr_bitfield_default }, + { "MCIF_WB_BUF_3_SHORT_LINE_ERROR", 30, 30, &umr_bitfield_default }, + { "MCIF_WB_BUF_3_FRAME_LENGTH_ERROR", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2[] = { + { "MCIF_WB_BUF_3_CUR_LINE_R", 0, 12, &umr_bitfield_default }, + { "MCIF_WB_BUF_3_NEW_CONTENT", 13, 13, &umr_bitfield_default }, + { "MCIF_WB_BUF_3_COLOR_DEPTH", 14, 14, &umr_bitfield_default }, + { "MCIF_WB_BUF_3_Y_OVERRUN", 17, 17, &umr_bitfield_default }, + { "MCIF_WB_BUF_3_C_OVERRUN", 18, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB0_MCIF_WB_BUF_4_STATUS[] = { + { "MCIF_WB_BUF_4_ACTIVE", 0, 0, &umr_bitfield_default }, + { "MCIF_WB_BUF_4_SW_LOCKED", 1, 1, &umr_bitfield_default }, + { "MCIF_WB_BUF_4_VCE_LOCKED", 2, 2, &umr_bitfield_default }, + { "MCIF_WB_BUF_4_OVERFLOW", 3, 3, &umr_bitfield_default }, + { "MCIF_WB_BUF_4_DISABLE", 4, 4, &umr_bitfield_default }, + { "MCIF_WB_BUF_4_MODE", 5, 7, &umr_bitfield_default }, + { "MCIF_WB_BUF_4_BUFTAG", 8, 11, &umr_bitfield_default }, + { "MCIF_WB_BUF_4_NXT_BUF", 12, 14, &umr_bitfield_default }, + { "MCIF_WB_BUF_4_FIELD", 15, 15, &umr_bitfield_default }, + { "MCIF_WB_BUF_4_CUR_LINE_L", 16, 28, &umr_bitfield_default }, + { "MCIF_WB_BUF_4_LONG_LINE_ERROR", 29, 29, &umr_bitfield_default }, + { "MCIF_WB_BUF_4_SHORT_LINE_ERROR", 30, 30, &umr_bitfield_default }, + { "MCIF_WB_BUF_4_FRAME_LENGTH_ERROR", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2[] = { + { "MCIF_WB_BUF_4_CUR_LINE_R", 0, 12, &umr_bitfield_default }, + { "MCIF_WB_BUF_4_NEW_CONTENT", 13, 13, &umr_bitfield_default }, + { "MCIF_WB_BUF_4_COLOR_DEPTH", 14, 14, &umr_bitfield_default }, + { "MCIF_WB_BUF_4_Y_OVERRUN", 17, 17, &umr_bitfield_default }, + { "MCIF_WB_BUF_4_C_OVERRUN", 18, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL[] = { + { "MCIF_WB_CLIENT_ARBITRATION_SLICE", 0, 1, &umr_bitfield_default }, + { "MCIF_WB_TIME_PER_PIXEL", 22, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB0_MCIF_WB_SCLK_CHANGE[] = { + { "WM_CHANGE_ACK_FORCE_ON", 0, 0, &umr_bitfield_default }, + { "MCIF_WB_CLI_WATERMARK_MASK", 1, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y[] = { + { "MCIF_WB_BUF_1_ADDR_Y", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET[] = { + { "MCIF_WB_BUF_1_ADDR_Y_OFFSET", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C[] = { + { "MCIF_WB_BUF_1_ADDR_C", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET[] = { + { "MCIF_WB_BUF_1_ADDR_C_OFFSET", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y[] = { + { "MCIF_WB_BUF_2_ADDR_Y", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET[] = { + { "MCIF_WB_BUF_2_ADDR_Y_OFFSET", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C[] = { + { "MCIF_WB_BUF_2_ADDR_C", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET[] = { + { "MCIF_WB_BUF_2_ADDR_C_OFFSET", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y[] = { + { "MCIF_WB_BUF_3_ADDR_Y", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET[] = { + { "MCIF_WB_BUF_3_ADDR_Y_OFFSET", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C[] = { + { "MCIF_WB_BUF_3_ADDR_C", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET[] = { + { "MCIF_WB_BUF_3_ADDR_C_OFFSET", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y[] = { + { "MCIF_WB_BUF_4_ADDR_Y", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET[] = { + { "MCIF_WB_BUF_4_ADDR_Y_OFFSET", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C[] = { + { "MCIF_WB_BUF_4_ADDR_C", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET[] = { + { "MCIF_WB_BUF_4_ADDR_C_OFFSET", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL[] = { + { "MCIF_WB_BUFMGR_VCE_LOCK_IGNORE", 0, 0, &umr_bitfield_default }, + { "MCIF_WB_BUFMGR_VCE_INT_EN", 4, 4, &umr_bitfield_default }, + { "MCIF_WB_BUFMGR_VCE_INT_ACK", 5, 5, &umr_bitfield_default }, + { "MCIF_WB_BUFMGR_VCE_SLICE_INT_EN", 6, 6, &umr_bitfield_default }, + { "MCIF_WB_BUFMGR_VCE_LOCK", 8, 11, &umr_bitfield_default }, + { "MCIF_WB_BUFMGR_SLICE_SIZE", 16, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK[] = { + { "NB_PSTATE_CHANGE_REFRESH_WATERMARK", 0, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL[] = { + { "NB_PSTATE_CHANGE_URGENT_DURING_REQUEST", 0, 0, &umr_bitfield_default }, + { "NB_PSTATE_CHANGE_FORCE_ON", 1, 1, &umr_bitfield_default }, + { "NB_PSTATE_ALLOW_FOR_URGENT", 2, 2, &umr_bitfield_default }, + { "NB_PSTATE_CHANGE_WATERMARK_MASK", 4, 6, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB0_MCIF_WB_WATERMARK[] = { + { "MCIF_WB_CLI_WATERMARK", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL[] = { + { "MCIF_WB_CLI_CLOCK_GATER_OVERRIDE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL[] = { + { "MCIF_WB_PITCH_SIZE_WARMUP", 8, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL[] = { + { "DIS_REFRESH_UNDER_NBPREQ", 0, 0, &umr_bitfield_default }, + { "PERFRAME_SELF_REFRESH", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL[] = { + { "MAX_SCALED_TIME_TO_URGENT", 0, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE[] = { + { "MCIF_WB_BUF_LUMA_SIZE", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE[] = { + { "MCIF_WB_BUF_CHROMA_SIZE", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL[] = { + { "MCIF_WB_BUFMGR_ENABLE", 0, 0, &umr_bitfield_default }, + { "MCIF_WB_BUF_DUALSIZE_REQ", 1, 1, &umr_bitfield_default }, + { "MCIF_WB_BUFMGR_SW_INT_EN", 4, 4, &umr_bitfield_default }, + { "MCIF_WB_BUFMGR_SW_INT_ACK", 5, 5, &umr_bitfield_default }, + { "MCIF_WB_BUFMGR_SW_SLICE_INT_EN", 6, 6, &umr_bitfield_default }, + { "MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN", 7, 7, &umr_bitfield_default }, + { "MCIF_WB_BUFMGR_SW_LOCK", 8, 11, &umr_bitfield_default }, + { "MCIF_WB_P_VMID", 16, 19, &umr_bitfield_default }, + { "MCIF_WB_BUF_ADDR_FENCE_EN", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R[] = { + { "MCIF_WB_BUFMGR_CUR_LINE_R", 0, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS[] = { + { "MCIF_WB_BUFMGR_VCE_INT_STATUS", 0, 0, &umr_bitfield_default }, + { "MCIF_WB_BUFMGR_SW_INT_STATUS", 1, 1, &umr_bitfield_default }, + { "MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS", 2, 2, &umr_bitfield_default }, + { "MCIF_WB_BUFMGR_CUR_BUF", 4, 6, &umr_bitfield_default }, + { "MCIF_WB_BUF_DUALSIZE_STATUS", 7, 7, &umr_bitfield_default }, + { "MCIF_WB_BUFMGR_BUFTAG", 8, 11, &umr_bitfield_default }, + { "MCIF_WB_BUFMGR_CUR_LINE_L", 12, 24, &umr_bitfield_default }, + { "MCIF_WB_BUFMGR_NEXT_BUF", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB1_MCIF_WB_BUF_PITCH[] = { + { "MCIF_WB_BUF_LUMA_PITCH", 8, 15, &umr_bitfield_default }, + { "MCIF_WB_BUF_CHROMA_PITCH", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB1_MCIF_WB_BUF_1_STATUS[] = { + { "MCIF_WB_BUF_1_ACTIVE", 0, 0, &umr_bitfield_default }, + { "MCIF_WB_BUF_1_SW_LOCKED", 1, 1, &umr_bitfield_default }, + { "MCIF_WB_BUF_1_VCE_LOCKED", 2, 2, &umr_bitfield_default }, + { "MCIF_WB_BUF_1_OVERFLOW", 3, 3, &umr_bitfield_default }, + { "MCIF_WB_BUF_1_DISABLE", 4, 4, &umr_bitfield_default }, + { "MCIF_WB_BUF_1_MODE", 5, 7, &umr_bitfield_default }, + { "MCIF_WB_BUF_1_BUFTAG", 8, 11, &umr_bitfield_default }, + { "MCIF_WB_BUF_1_NXT_BUF", 12, 14, &umr_bitfield_default }, + { "MCIF_WB_BUF_1_FIELD", 15, 15, &umr_bitfield_default }, + { "MCIF_WB_BUF_1_CUR_LINE_L", 16, 28, &umr_bitfield_default }, + { "MCIF_WB_BUF_1_LONG_LINE_ERROR", 29, 29, &umr_bitfield_default }, + { "MCIF_WB_BUF_1_SHORT_LINE_ERROR", 30, 30, &umr_bitfield_default }, + { "MCIF_WB_BUF_1_FRAME_LENGTH_ERROR", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2[] = { + { "MCIF_WB_BUF_1_CUR_LINE_R", 0, 12, &umr_bitfield_default }, + { "MCIF_WB_BUF_1_NEW_CONTENT", 13, 13, &umr_bitfield_default }, + { "MCIF_WB_BUF_1_COLOR_DEPTH", 14, 14, &umr_bitfield_default }, + { "MCIF_WB_BUF_1_Y_OVERRUN", 17, 17, &umr_bitfield_default }, + { "MCIF_WB_BUF_1_C_OVERRUN", 18, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB1_MCIF_WB_BUF_2_STATUS[] = { + { "MCIF_WB_BUF_2_ACTIVE", 0, 0, &umr_bitfield_default }, + { "MCIF_WB_BUF_2_SW_LOCKED", 1, 1, &umr_bitfield_default }, + { "MCIF_WB_BUF_2_VCE_LOCKED", 2, 2, &umr_bitfield_default }, + { "MCIF_WB_BUF_2_OVERFLOW", 3, 3, &umr_bitfield_default }, + { "MCIF_WB_BUF_2_DISABLE", 4, 4, &umr_bitfield_default }, + { "MCIF_WB_BUF_2_MODE", 5, 7, &umr_bitfield_default }, + { "MCIF_WB_BUF_2_BUFTAG", 8, 11, &umr_bitfield_default }, + { "MCIF_WB_BUF_2_NXT_BUF", 12, 14, &umr_bitfield_default }, + { "MCIF_WB_BUF_2_FIELD", 15, 15, &umr_bitfield_default }, + { "MCIF_WB_BUF_2_CUR_LINE_L", 16, 28, &umr_bitfield_default }, + { "MCIF_WB_BUF_2_LONG_LINE_ERROR", 29, 29, &umr_bitfield_default }, + { "MCIF_WB_BUF_2_SHORT_LINE_ERROR", 30, 30, &umr_bitfield_default }, + { "MCIF_WB_BUF_2_FRAME_LENGTH_ERROR", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2[] = { + { "MCIF_WB_BUF_2_CUR_LINE_R", 0, 12, &umr_bitfield_default }, + { "MCIF_WB_BUF_2_NEW_CONTENT", 13, 13, &umr_bitfield_default }, + { "MCIF_WB_BUF_2_COLOR_DEPTH", 14, 14, &umr_bitfield_default }, + { "MCIF_WB_BUF_2_Y_OVERRUN", 17, 17, &umr_bitfield_default }, + { "MCIF_WB_BUF_2_C_OVERRUN", 18, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB1_MCIF_WB_BUF_3_STATUS[] = { + { "MCIF_WB_BUF_3_ACTIVE", 0, 0, &umr_bitfield_default }, + { "MCIF_WB_BUF_3_SW_LOCKED", 1, 1, &umr_bitfield_default }, + { "MCIF_WB_BUF_3_VCE_LOCKED", 2, 2, &umr_bitfield_default }, + { "MCIF_WB_BUF_3_OVERFLOW", 3, 3, &umr_bitfield_default }, + { "MCIF_WB_BUF_3_DISABLE", 4, 4, &umr_bitfield_default }, + { "MCIF_WB_BUF_3_MODE", 5, 7, &umr_bitfield_default }, + { "MCIF_WB_BUF_3_BUFTAG", 8, 11, &umr_bitfield_default }, + { "MCIF_WB_BUF_3_NXT_BUF", 12, 14, &umr_bitfield_default }, + { "MCIF_WB_BUF_3_FIELD", 15, 15, &umr_bitfield_default }, + { "MCIF_WB_BUF_3_CUR_LINE_L", 16, 28, &umr_bitfield_default }, + { "MCIF_WB_BUF_3_LONG_LINE_ERROR", 29, 29, &umr_bitfield_default }, + { "MCIF_WB_BUF_3_SHORT_LINE_ERROR", 30, 30, &umr_bitfield_default }, + { "MCIF_WB_BUF_3_FRAME_LENGTH_ERROR", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2[] = { + { "MCIF_WB_BUF_3_CUR_LINE_R", 0, 12, &umr_bitfield_default }, + { "MCIF_WB_BUF_3_NEW_CONTENT", 13, 13, &umr_bitfield_default }, + { "MCIF_WB_BUF_3_COLOR_DEPTH", 14, 14, &umr_bitfield_default }, + { "MCIF_WB_BUF_3_Y_OVERRUN", 17, 17, &umr_bitfield_default }, + { "MCIF_WB_BUF_3_C_OVERRUN", 18, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB1_MCIF_WB_BUF_4_STATUS[] = { + { "MCIF_WB_BUF_4_ACTIVE", 0, 0, &umr_bitfield_default }, + { "MCIF_WB_BUF_4_SW_LOCKED", 1, 1, &umr_bitfield_default }, + { "MCIF_WB_BUF_4_VCE_LOCKED", 2, 2, &umr_bitfield_default }, + { "MCIF_WB_BUF_4_OVERFLOW", 3, 3, &umr_bitfield_default }, + { "MCIF_WB_BUF_4_DISABLE", 4, 4, &umr_bitfield_default }, + { "MCIF_WB_BUF_4_MODE", 5, 7, &umr_bitfield_default }, + { "MCIF_WB_BUF_4_BUFTAG", 8, 11, &umr_bitfield_default }, + { "MCIF_WB_BUF_4_NXT_BUF", 12, 14, &umr_bitfield_default }, + { "MCIF_WB_BUF_4_FIELD", 15, 15, &umr_bitfield_default }, + { "MCIF_WB_BUF_4_CUR_LINE_L", 16, 28, &umr_bitfield_default }, + { "MCIF_WB_BUF_4_LONG_LINE_ERROR", 29, 29, &umr_bitfield_default }, + { "MCIF_WB_BUF_4_SHORT_LINE_ERROR", 30, 30, &umr_bitfield_default }, + { "MCIF_WB_BUF_4_FRAME_LENGTH_ERROR", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2[] = { + { "MCIF_WB_BUF_4_CUR_LINE_R", 0, 12, &umr_bitfield_default }, + { "MCIF_WB_BUF_4_NEW_CONTENT", 13, 13, &umr_bitfield_default }, + { "MCIF_WB_BUF_4_COLOR_DEPTH", 14, 14, &umr_bitfield_default }, + { "MCIF_WB_BUF_4_Y_OVERRUN", 17, 17, &umr_bitfield_default }, + { "MCIF_WB_BUF_4_C_OVERRUN", 18, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL[] = { + { "MCIF_WB_CLIENT_ARBITRATION_SLICE", 0, 1, &umr_bitfield_default }, + { "MCIF_WB_TIME_PER_PIXEL", 22, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB1_MCIF_WB_SCLK_CHANGE[] = { + { "WM_CHANGE_ACK_FORCE_ON", 0, 0, &umr_bitfield_default }, + { "MCIF_WB_CLI_WATERMARK_MASK", 1, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y[] = { + { "MCIF_WB_BUF_1_ADDR_Y", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET[] = { + { "MCIF_WB_BUF_1_ADDR_Y_OFFSET", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C[] = { + { "MCIF_WB_BUF_1_ADDR_C", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET[] = { + { "MCIF_WB_BUF_1_ADDR_C_OFFSET", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y[] = { + { "MCIF_WB_BUF_2_ADDR_Y", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET[] = { + { "MCIF_WB_BUF_2_ADDR_Y_OFFSET", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C[] = { + { "MCIF_WB_BUF_2_ADDR_C", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET[] = { + { "MCIF_WB_BUF_2_ADDR_C_OFFSET", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y[] = { + { "MCIF_WB_BUF_3_ADDR_Y", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET[] = { + { "MCIF_WB_BUF_3_ADDR_Y_OFFSET", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C[] = { + { "MCIF_WB_BUF_3_ADDR_C", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET[] = { + { "MCIF_WB_BUF_3_ADDR_C_OFFSET", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y[] = { + { "MCIF_WB_BUF_4_ADDR_Y", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET[] = { + { "MCIF_WB_BUF_4_ADDR_Y_OFFSET", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C[] = { + { "MCIF_WB_BUF_4_ADDR_C", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET[] = { + { "MCIF_WB_BUF_4_ADDR_C_OFFSET", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL[] = { + { "MCIF_WB_BUFMGR_VCE_LOCK_IGNORE", 0, 0, &umr_bitfield_default }, + { "MCIF_WB_BUFMGR_VCE_INT_EN", 4, 4, &umr_bitfield_default }, + { "MCIF_WB_BUFMGR_VCE_INT_ACK", 5, 5, &umr_bitfield_default }, + { "MCIF_WB_BUFMGR_VCE_SLICE_INT_EN", 6, 6, &umr_bitfield_default }, + { "MCIF_WB_BUFMGR_VCE_LOCK", 8, 11, &umr_bitfield_default }, + { "MCIF_WB_BUFMGR_SLICE_SIZE", 16, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK[] = { + { "NB_PSTATE_CHANGE_REFRESH_WATERMARK", 0, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL[] = { + { "NB_PSTATE_CHANGE_URGENT_DURING_REQUEST", 0, 0, &umr_bitfield_default }, + { "NB_PSTATE_CHANGE_FORCE_ON", 1, 1, &umr_bitfield_default }, + { "NB_PSTATE_ALLOW_FOR_URGENT", 2, 2, &umr_bitfield_default }, + { "NB_PSTATE_CHANGE_WATERMARK_MASK", 4, 6, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB1_MCIF_WB_WATERMARK[] = { + { "MCIF_WB_CLI_WATERMARK", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL[] = { + { "MCIF_WB_CLI_CLOCK_GATER_OVERRIDE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL[] = { + { "MCIF_WB_PITCH_SIZE_WARMUP", 8, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL[] = { + { "DIS_REFRESH_UNDER_NBPREQ", 0, 0, &umr_bitfield_default }, + { "PERFRAME_SELF_REFRESH", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL[] = { + { "MAX_SCALED_TIME_TO_URGENT", 0, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE[] = { + { "MCIF_WB_BUF_LUMA_SIZE", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE[] = { + { "MCIF_WB_BUF_CHROMA_SIZE", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWBIF0_MISC_CTRL[] = { + { "MCIFWB0_WR_COMBINE_TIMEOUT_THRESH", 0, 9, &umr_bitfield_default }, + { "MCIF_WB0_SOCCLK_DS_ENABLE", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWBIF0_SMU_WM_CONTROL[] = { + { "MCIF_WB0_WM_CHG_SEL", 20, 21, &umr_bitfield_default }, + { "MCIF_WB0_WM_CHG_REQ", 22, 22, &umr_bitfield_default }, + { "MCIF_WB0_WM_CHG_ACK_INT_DIS", 24, 24, &umr_bitfield_default }, + { "MCIF_WB0_WM_CHG_ACK_INT_STATUS", 25, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWBIF0_PHASE0_OUTSTANDING_COUNTER[] = { + { "MCIF_WB0_PHASE0_OUTSTANDING_COUNTER", 0, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWBIF0_PHASE1_OUTSTANDING_COUNTER[] = { + { "MCIF_WB0_PHASE1_OUTSTANDING_COUNTER", 0, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWBIF1_MISC_CTRL[] = { + { "MCIFWB1_WR_COMBINE_TIMEOUT_THRESH", 0, 9, &umr_bitfield_default }, + { "MCIF_WB1_SOCCLK_DS_ENABLE", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWBIF1_SMU_WM_CONTROL[] = { + { "MCIF_WB1_WM_CHG_SEL", 20, 21, &umr_bitfield_default }, + { "MCIF_WB1_WM_CHG_REQ", 22, 22, &umr_bitfield_default }, + { "MCIF_WB1_WM_CHG_ACK_INT_DIS", 24, 24, &umr_bitfield_default }, + { "MCIF_WB1_WM_CHG_ACK_INT_STATUS", 25, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWBIF1_PHASE0_OUTSTANDING_COUNTER[] = { + { "MCIF_WB1_PHASE0_OUTSTANDING_COUNTER", 0, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWBIF1_PHASE1_OUTSTANDING_COUNTER[] = { + { "MCIF_WB1_PHASE1_OUTSTANDING_COUNTER", 0, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGA_SRC_SPLIT_CNTL[] = { + { "VGA_SPLIT_SEL", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMHUBBUB_MEM_PWR_STATUS[] = { + { "MCIF_DWB0_LUMA_MEM0_PWR_STATE", 0, 1, &umr_bitfield_default }, + { "MCIF_DWB0_LUMA_MEM1_PWR_STATE", 2, 3, &umr_bitfield_default }, + { "MCIF_DWB0_CHROMA_MEM0_PWR_STATE", 4, 5, &umr_bitfield_default }, + { "MCIF_DWB0_CHROMA_MEM1_PWR_STATE", 6, 7, &umr_bitfield_default }, + { "MCIF_DWB1_LUMA_MEM0_PWR_STATE", 8, 9, &umr_bitfield_default }, + { "MCIF_DWB1_LUMA_MEM1_PWR_STATE", 10, 11, &umr_bitfield_default }, + { "MCIF_DWB1_CHROMA_MEM0_PWR_STATE", 12, 13, &umr_bitfield_default }, + { "MCIF_DWB1_CHROMA_MEM1_PWR_STATE", 14, 15, &umr_bitfield_default }, + { "VGA_MEM_PWR_STATE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMHUBBUB_MEM_PWR_CNTL[] = { + { "VGA_MEM_PWR_FORCE", 0, 0, &umr_bitfield_default }, + { "VGA_MEM_PWR_DIS", 1, 1, &umr_bitfield_default }, + { "MCIF_DWB0_MEM_PWR_FORCE", 2, 3, &umr_bitfield_default }, + { "MCIF_DWB0_MEM_PWR_DIS", 4, 4, &umr_bitfield_default }, + { "MCIF_DWB0_MEM_PWR_MODE_SEL", 5, 6, &umr_bitfield_default }, + { "MCIF_DWB0_LUMA_MEM_EN_NUM", 7, 7, &umr_bitfield_default }, + { "MCIF_DWB0_CHROMA_MEM_EN_NUM", 8, 8, &umr_bitfield_default }, + { "MCIF_DWB1_MEM_PWR_FORCE", 9, 10, &umr_bitfield_default }, + { "MCIF_DWB1_MEM_PWR_DIS", 11, 11, &umr_bitfield_default }, + { "MCIF_DWB1_MEM_PWR_MODE_SEL", 12, 13, &umr_bitfield_default }, + { "MCIF_DWB1_LUMA_MEM_EN_NUM", 14, 14, &umr_bitfield_default }, + { "MCIF_DWB1_CHROMA_MEM_EN_NUM", 15, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMHUBBUB_CLOCK_CNTL[] = { + { "MMHUBBUB_TEST_CLK_SEL", 0, 4, &umr_bitfield_default }, + { "DISPCLK_R_MMHUBBUB_GATE_DIS", 5, 5, &umr_bitfield_default }, + { "DISPCLK_G_VGAIF_GATE_DIS", 6, 6, &umr_bitfield_default }, + { "SOCCLK_G_VGAIF_GATE_DIS", 7, 7, &umr_bitfield_default }, + { "DISPCLK_G_VGA_GATE_DIS", 8, 8, &umr_bitfield_default }, + { "DISPCLK_G_WBIF0_GATE_DIS", 9, 9, &umr_bitfield_default }, + { "SOCCLK_G_WBIF0_GATE_DIS", 10, 10, &umr_bitfield_default }, + { "DISPCLK_G_WBIF1_GATE_DIS", 11, 11, &umr_bitfield_default }, + { "SOCCLK_G_WBIF1_GATE_DIS", 12, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMHUBBUB_SOFT_RESET[] = { + { "VGA_SOFT_RESET", 0, 0, &umr_bitfield_default }, + { "VGAIF_SOFT_RESET", 1, 1, &umr_bitfield_default }, + { "WBIF0_SOFT_RESET", 2, 2, &umr_bitfield_default }, + { "WBIF1_SOFT_RESET", 3, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_CONTROL[] = { + { "MCIF_MC_LATENCY_COUNTER_ENABLE", 30, 30, &umr_bitfield_default }, + { "MCIF_MC_LATENCY_COUNTER_URGENT_ONLY", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_WRITE_COMBINE_CONTROL[] = { + { "MCIF_WRITE_COMBINE_TIMEOUT", 0, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_PHASE0_OUTSTANDING_COUNTER[] = { + { "MCIF_PHASE0_OUTSTANDING_COUNTER", 0, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_PHASE1_OUTSTANDING_COUNTER[] = { + { "MCIF_PHASE1_OUTSTANDING_COUNTER", 0, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMCIF_PHASE2_OUTSTANDING_COUNTER[] = { + { "MCIF_PHASE2_OUTSTANDING_COUNTER", 0, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON5_PERFCOUNTER_CNTL[] = { + { "PERFCOUNTER_EVENT_SEL", 0, 8, &umr_bitfield_default }, + { "PERFCOUNTER_CVALUE_SEL", 9, 11, &umr_bitfield_default }, + { "PERFCOUNTER_INC_MODE", 12, 14, &umr_bitfield_default }, + { "PERFCOUNTER_HW_CNTL_SEL", 15, 15, &umr_bitfield_default }, + { "PERFCOUNTER_RUNEN_MODE", 16, 16, &umr_bitfield_default }, + { "PERFCOUNTER_CNTOFF_START_DIS", 22, 22, &umr_bitfield_default }, + { "PERFCOUNTER_RESTART_EN", 23, 23, &umr_bitfield_default }, + { "PERFCOUNTER_INT_EN", 24, 24, &umr_bitfield_default }, + { "PERFCOUNTER_OFF_MASK", 25, 25, &umr_bitfield_default }, + { "PERFCOUNTER_ACTIVE", 26, 26, &umr_bitfield_default }, + { "PERFCOUNTER_CNTL_SEL", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON5_PERFCOUNTER_CNTL2[] = { + { "PERFCOUNTER_COUNTED_VALUE_TYPE", 0, 1, &umr_bitfield_default }, + { "PERFCOUNTER_HW_STOP1_SEL", 2, 2, &umr_bitfield_default }, + { "PERFCOUNTER_HW_STOP2_SEL", 3, 3, &umr_bitfield_default }, + { "PERFCOUNTER_CNTOFF_SEL", 8, 13, &umr_bitfield_default }, + { "PERFCOUNTER_CNTL2_SEL", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON5_PERFCOUNTER_STATE[] = { + { "PERFCOUNTER_CNT0_STATE", 0, 1, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL0", 2, 2, &umr_bitfield_default }, + { "PERFCOUNTER_CNT1_STATE", 4, 5, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL1", 6, 6, &umr_bitfield_default }, + { "PERFCOUNTER_CNT2_STATE", 8, 9, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL2", 10, 10, &umr_bitfield_default }, + { "PERFCOUNTER_CNT3_STATE", 12, 13, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL3", 14, 14, &umr_bitfield_default }, + { "PERFCOUNTER_CNT4_STATE", 16, 17, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL4", 18, 18, &umr_bitfield_default }, + { "PERFCOUNTER_CNT5_STATE", 20, 21, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL5", 22, 22, &umr_bitfield_default }, + { "PERFCOUNTER_CNT6_STATE", 24, 25, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL6", 26, 26, &umr_bitfield_default }, + { "PERFCOUNTER_CNT7_STATE", 28, 29, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL7", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON5_PERFMON_CNTL[] = { + { "PERFMON_STATE", 0, 1, &umr_bitfield_default }, + { "PERFMON_RPT_COUNT", 8, 27, &umr_bitfield_default }, + { "PERFMON_CNTOFF_AND_OR", 28, 28, &umr_bitfield_default }, + { "PERFMON_CNTOFF_INT_EN", 29, 29, &umr_bitfield_default }, + { "PERFMON_CNTOFF_INT_STATUS", 30, 30, &umr_bitfield_default }, + { "PERFMON_CNTOFF_INT_ACK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON5_PERFMON_CNTL2[] = { + { "PERFMON_CNTOFF_INT_TYPE", 0, 0, &umr_bitfield_default }, + { "PERFMON_CLK_ENABLE", 1, 1, &umr_bitfield_default }, + { "PERFMON_RUN_ENABLE_START_SEL", 2, 9, &umr_bitfield_default }, + { "PERFMON_RUN_ENABLE_STOP_SEL", 10, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC[] = { + { "PERFCOUNTER_INT0_STATUS", 0, 0, &umr_bitfield_default }, + { "PERFCOUNTER_INT1_STATUS", 1, 1, &umr_bitfield_default }, + { "PERFCOUNTER_INT2_STATUS", 2, 2, &umr_bitfield_default }, + { "PERFCOUNTER_INT3_STATUS", 3, 3, &umr_bitfield_default }, + { "PERFCOUNTER_INT4_STATUS", 4, 4, &umr_bitfield_default }, + { "PERFCOUNTER_INT5_STATUS", 5, 5, &umr_bitfield_default }, + { "PERFCOUNTER_INT6_STATUS", 6, 6, &umr_bitfield_default }, + { "PERFCOUNTER_INT7_STATUS", 7, 7, &umr_bitfield_default }, + { "PERFCOUNTER_INT0_ACK", 8, 8, &umr_bitfield_default }, + { "PERFCOUNTER_INT1_ACK", 9, 9, &umr_bitfield_default }, + { "PERFCOUNTER_INT2_ACK", 10, 10, &umr_bitfield_default }, + { "PERFCOUNTER_INT3_ACK", 11, 11, &umr_bitfield_default }, + { "PERFCOUNTER_INT4_ACK", 12, 12, &umr_bitfield_default }, + { "PERFCOUNTER_INT5_ACK", 13, 13, &umr_bitfield_default }, + { "PERFCOUNTER_INT6_ACK", 14, 14, &umr_bitfield_default }, + { "PERFCOUNTER_INT7_ACK", 15, 15, &umr_bitfield_default }, + { "PERFMON_CVALUE_HI", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON5_PERFMON_CVALUE_LOW[] = { + { "PERFMON_CVALUE_LOW", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON5_PERFMON_HI[] = { + { "PERFMON_HI", 0, 15, &umr_bitfield_default }, + { "PERFMON_READ_SEL", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON5_PERFMON_LOW[] = { + { "PERFMON_LOW", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZF0STREAM0_AZALIA_STREAM_INDEX[] = { + { "AZALIA_STREAM_REG_INDEX", 0, 7, &umr_bitfield_default }, + { "AZALIA_STREAM_REG_WRITE_EN", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZF0STREAM0_AZALIA_STREAM_DATA[] = { + { "AZALIA_STREAM_REG_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZF0STREAM1_AZALIA_STREAM_INDEX[] = { + { "AZALIA_STREAM_REG_INDEX", 0, 7, &umr_bitfield_default }, + { "AZALIA_STREAM_REG_WRITE_EN", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZF0STREAM1_AZALIA_STREAM_DATA[] = { + { "AZALIA_STREAM_REG_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZF0STREAM2_AZALIA_STREAM_INDEX[] = { + { "AZALIA_STREAM_REG_INDEX", 0, 7, &umr_bitfield_default }, + { "AZALIA_STREAM_REG_WRITE_EN", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZF0STREAM2_AZALIA_STREAM_DATA[] = { + { "AZALIA_STREAM_REG_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZF0STREAM3_AZALIA_STREAM_INDEX[] = { + { "AZALIA_STREAM_REG_INDEX", 0, 7, &umr_bitfield_default }, + { "AZALIA_STREAM_REG_WRITE_EN", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZF0STREAM3_AZALIA_STREAM_DATA[] = { + { "AZALIA_STREAM_REG_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZF0STREAM4_AZALIA_STREAM_INDEX[] = { + { "AZALIA_STREAM_REG_INDEX", 0, 7, &umr_bitfield_default }, + { "AZALIA_STREAM_REG_WRITE_EN", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZF0STREAM4_AZALIA_STREAM_DATA[] = { + { "AZALIA_STREAM_REG_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZF0STREAM5_AZALIA_STREAM_INDEX[] = { + { "AZALIA_STREAM_REG_INDEX", 0, 7, &umr_bitfield_default }, + { "AZALIA_STREAM_REG_WRITE_EN", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZF0STREAM5_AZALIA_STREAM_DATA[] = { + { "AZALIA_STREAM_REG_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZF0STREAM6_AZALIA_STREAM_INDEX[] = { + { "AZALIA_STREAM_REG_INDEX", 0, 7, &umr_bitfield_default }, + { "AZALIA_STREAM_REG_WRITE_EN", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZF0STREAM6_AZALIA_STREAM_DATA[] = { + { "AZALIA_STREAM_REG_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZF0STREAM7_AZALIA_STREAM_INDEX[] = { + { "AZALIA_STREAM_REG_INDEX", 0, 7, &umr_bitfield_default }, + { "AZALIA_STREAM_REG_WRITE_EN", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZF0STREAM7_AZALIA_STREAM_DATA[] = { + { "AZALIA_STREAM_REG_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZ_CLOCK_CNTL[] = { + { "SCLK_G_STREAM_AZ_GATE_DIS", 0, 0, &umr_bitfield_default }, + { "SCLK_R_AZ_GATE_DIS", 8, 8, &umr_bitfield_default }, + { "SCLK_G_CNTL_AZ_GATE_DIS", 16, 16, &umr_bitfield_default }, + { "DCIPG_TEST_CLK_SEL", 24, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON6_PERFCOUNTER_CNTL[] = { + { "PERFCOUNTER_EVENT_SEL", 0, 8, &umr_bitfield_default }, + { "PERFCOUNTER_CVALUE_SEL", 9, 11, &umr_bitfield_default }, + { "PERFCOUNTER_INC_MODE", 12, 14, &umr_bitfield_default }, + { "PERFCOUNTER_HW_CNTL_SEL", 15, 15, &umr_bitfield_default }, + { "PERFCOUNTER_RUNEN_MODE", 16, 16, &umr_bitfield_default }, + { "PERFCOUNTER_CNTOFF_START_DIS", 22, 22, &umr_bitfield_default }, + { "PERFCOUNTER_RESTART_EN", 23, 23, &umr_bitfield_default }, + { "PERFCOUNTER_INT_EN", 24, 24, &umr_bitfield_default }, + { "PERFCOUNTER_OFF_MASK", 25, 25, &umr_bitfield_default }, + { "PERFCOUNTER_ACTIVE", 26, 26, &umr_bitfield_default }, + { "PERFCOUNTER_CNTL_SEL", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON6_PERFCOUNTER_CNTL2[] = { + { "PERFCOUNTER_COUNTED_VALUE_TYPE", 0, 1, &umr_bitfield_default }, + { "PERFCOUNTER_HW_STOP1_SEL", 2, 2, &umr_bitfield_default }, + { "PERFCOUNTER_HW_STOP2_SEL", 3, 3, &umr_bitfield_default }, + { "PERFCOUNTER_CNTOFF_SEL", 8, 13, &umr_bitfield_default }, + { "PERFCOUNTER_CNTL2_SEL", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON6_PERFCOUNTER_STATE[] = { + { "PERFCOUNTER_CNT0_STATE", 0, 1, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL0", 2, 2, &umr_bitfield_default }, + { "PERFCOUNTER_CNT1_STATE", 4, 5, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL1", 6, 6, &umr_bitfield_default }, + { "PERFCOUNTER_CNT2_STATE", 8, 9, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL2", 10, 10, &umr_bitfield_default }, + { "PERFCOUNTER_CNT3_STATE", 12, 13, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL3", 14, 14, &umr_bitfield_default }, + { "PERFCOUNTER_CNT4_STATE", 16, 17, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL4", 18, 18, &umr_bitfield_default }, + { "PERFCOUNTER_CNT5_STATE", 20, 21, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL5", 22, 22, &umr_bitfield_default }, + { "PERFCOUNTER_CNT6_STATE", 24, 25, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL6", 26, 26, &umr_bitfield_default }, + { "PERFCOUNTER_CNT7_STATE", 28, 29, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL7", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON6_PERFMON_CNTL[] = { + { "PERFMON_STATE", 0, 1, &umr_bitfield_default }, + { "PERFMON_RPT_COUNT", 8, 27, &umr_bitfield_default }, + { "PERFMON_CNTOFF_AND_OR", 28, 28, &umr_bitfield_default }, + { "PERFMON_CNTOFF_INT_EN", 29, 29, &umr_bitfield_default }, + { "PERFMON_CNTOFF_INT_STATUS", 30, 30, &umr_bitfield_default }, + { "PERFMON_CNTOFF_INT_ACK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON6_PERFMON_CNTL2[] = { + { "PERFMON_CNTOFF_INT_TYPE", 0, 0, &umr_bitfield_default }, + { "PERFMON_CLK_ENABLE", 1, 1, &umr_bitfield_default }, + { "PERFMON_RUN_ENABLE_START_SEL", 2, 9, &umr_bitfield_default }, + { "PERFMON_RUN_ENABLE_STOP_SEL", 10, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC[] = { + { "PERFCOUNTER_INT0_STATUS", 0, 0, &umr_bitfield_default }, + { "PERFCOUNTER_INT1_STATUS", 1, 1, &umr_bitfield_default }, + { "PERFCOUNTER_INT2_STATUS", 2, 2, &umr_bitfield_default }, + { "PERFCOUNTER_INT3_STATUS", 3, 3, &umr_bitfield_default }, + { "PERFCOUNTER_INT4_STATUS", 4, 4, &umr_bitfield_default }, + { "PERFCOUNTER_INT5_STATUS", 5, 5, &umr_bitfield_default }, + { "PERFCOUNTER_INT6_STATUS", 6, 6, &umr_bitfield_default }, + { "PERFCOUNTER_INT7_STATUS", 7, 7, &umr_bitfield_default }, + { "PERFCOUNTER_INT0_ACK", 8, 8, &umr_bitfield_default }, + { "PERFCOUNTER_INT1_ACK", 9, 9, &umr_bitfield_default }, + { "PERFCOUNTER_INT2_ACK", 10, 10, &umr_bitfield_default }, + { "PERFCOUNTER_INT3_ACK", 11, 11, &umr_bitfield_default }, + { "PERFCOUNTER_INT4_ACK", 12, 12, &umr_bitfield_default }, + { "PERFCOUNTER_INT5_ACK", 13, 13, &umr_bitfield_default }, + { "PERFCOUNTER_INT6_ACK", 14, 14, &umr_bitfield_default }, + { "PERFCOUNTER_INT7_ACK", 15, 15, &umr_bitfield_default }, + { "PERFMON_CVALUE_HI", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON6_PERFMON_CVALUE_LOW[] = { + { "PERFMON_CVALUE_LOW", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON6_PERFMON_HI[] = { + { "PERFMON_HI", 0, 15, &umr_bitfield_default }, + { "PERFMON_READ_SEL", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON6_PERFMON_LOW[] = { + { "PERFMON_LOW", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX[] = { + { "AZALIA_ENDPOINT_REG_INDEX", 0, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA[] = { + { "AZALIA_ENDPOINT_REG_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX[] = { + { "AZALIA_ENDPOINT_REG_INDEX", 0, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA[] = { + { "AZALIA_ENDPOINT_REG_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX[] = { + { "AZALIA_ENDPOINT_REG_INDEX", 0, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA[] = { + { "AZALIA_ENDPOINT_REG_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX[] = { + { "AZALIA_ENDPOINT_REG_INDEX", 0, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA[] = { + { "AZALIA_ENDPOINT_REG_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX[] = { + { "AZALIA_ENDPOINT_REG_INDEX", 0, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA[] = { + { "AZALIA_ENDPOINT_REG_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX[] = { + { "AZALIA_ENDPOINT_REG_INDEX", 0, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA[] = { + { "AZALIA_ENDPOINT_REG_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX[] = { + { "AZALIA_ENDPOINT_REG_INDEX", 0, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA[] = { + { "AZALIA_ENDPOINT_REG_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX[] = { + { "AZALIA_ENDPOINT_REG_INDEX", 0, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA[] = { + { "AZALIA_ENDPOINT_REG_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZALIA_CONTROLLER_CLOCK_GATING[] = { + { "ENABLE_CLOCK_GATING", 0, 0, &umr_bitfield_default }, + { "CLOCK_ON_STATE", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZALIA_AUDIO_DTO[] = { + { "AZALIA_AUDIO_DTO_PHASE", 0, 15, &umr_bitfield_default }, + { "AZALIA_AUDIO_DTO_MODULE", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZALIA_AUDIO_DTO_CONTROL[] = { + { "AZALIA_AUDIO_FORCE_DTO", 8, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZALIA_SOCCLK_CONTROL[] = { + { "AUDIO_STREAM_SOCCLK_DEEP_SLEEP_EXIT_EN", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZALIA_UNDERFLOW_FILLER_SAMPLE[] = { + { "AZALIA_UNDERFLOW_FILLER_SAMPLE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZALIA_DATA_DMA_CONTROL[] = { + { "DATA_DMA_NON_SNOOP", 0, 1, &umr_bitfield_default }, + { "INPUT_DATA_DMA_NON_SNOOP", 2, 3, &umr_bitfield_default }, + { "DATA_DMA_ISOCHRONOUS", 4, 5, &umr_bitfield_default }, + { "INPUT_DATA_DMA_ISOCHRONOUS", 6, 7, &umr_bitfield_default }, + { "AZALIA_IOC_GENERATION_METHOD", 16, 16, &umr_bitfield_default }, + { "AZALIA_UNDERFLOW_CONTROL", 17, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZALIA_BDL_DMA_CONTROL[] = { + { "BDL_DMA_NON_SNOOP", 0, 1, &umr_bitfield_default }, + { "INPUT_BDL_DMA_NON_SNOOP", 2, 3, &umr_bitfield_default }, + { "BDL_DMA_ISOCHRONOUS", 4, 5, &umr_bitfield_default }, + { "INPUT_BDL_DMA_ISOCHRONOUS", 6, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZALIA_RIRB_AND_DP_CONTROL[] = { + { "RIRB_NON_SNOOP", 0, 0, &umr_bitfield_default }, + { "DP_DMA_NON_SNOOP", 4, 4, &umr_bitfield_default }, + { "DP_UPDATE_FREQ_DIVIDER", 5, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZALIA_CORB_DMA_CONTROL[] = { + { "CORB_DMA_NON_SNOOP", 0, 0, &umr_bitfield_default }, + { "CORB_DMA_ISOCHRONOUS", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER[] = { + { "APPLICATION_POSITION_IN_CYCLIC_BUFFER", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZALIA_CYCLIC_BUFFER_SYNC[] = { + { "CYCLIC_BUFFER_SYNC_ENABLE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZALIA_GLOBAL_CAPABILITIES[] = { + { "NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS", 1, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY[] = { + { "OUTPUT_PAYLOAD_CAPABILITY", 0, 15, &umr_bitfield_default }, + { "OUTSTRMPAY", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL[] = { + { "LATENCY_HIDING_LEVEL", 0, 7, &umr_bitfield_default }, + { "SYS_MEM_ACTIVE_ENABLE", 8, 8, &umr_bitfield_default }, + { "INPUT_LATENCY_HIDING_LEVEL", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZALIA_INPUT_PAYLOAD_CAPABILITY[] = { + { "INPUT_PAYLOAD_CAPABILITY", 0, 15, &umr_bitfield_default }, + { "INSTRMPAY", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZALIA_INPUT_CRC0_CONTROL0[] = { + { "INPUT_CRC_EN", 0, 0, &umr_bitfield_default }, + { "INPUT_CRC_BLOCK_MODE", 4, 4, &umr_bitfield_default }, + { "INPUT_CRC_INSTANCE_SEL", 8, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZALIA_INPUT_CRC0_CONTROL1[] = { + { "INPUT_CRC_BLOCK_SIZE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZALIA_INPUT_CRC0_CONTROL2[] = { + { "INPUT_CRC_BLOCK_ITERATION", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZALIA_INPUT_CRC0_CONTROL3[] = { + { "INPUT_CRC_COMPLETE", 0, 0, &umr_bitfield_default }, + { "INPUT_CRC_BLOCK_COMPLETE_PHASE", 4, 4, &umr_bitfield_default }, + { "INPUT_CRC_CHANNEL_RESULT_SEL", 8, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZALIA_INPUT_CRC0_RESULT[] = { + { "INPUT_CRC_RESULT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZALIA_INPUT_CRC1_CONTROL0[] = { + { "INPUT_CRC_EN", 0, 0, &umr_bitfield_default }, + { "INPUT_CRC_BLOCK_MODE", 4, 4, &umr_bitfield_default }, + { "INPUT_CRC_INSTANCE_SEL", 8, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZALIA_INPUT_CRC1_CONTROL1[] = { + { "INPUT_CRC_BLOCK_SIZE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZALIA_INPUT_CRC1_CONTROL2[] = { + { "INPUT_CRC_BLOCK_ITERATION", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZALIA_INPUT_CRC1_CONTROL3[] = { + { "INPUT_CRC_COMPLETE", 0, 0, &umr_bitfield_default }, + { "INPUT_CRC_BLOCK_COMPLETE_PHASE", 4, 4, &umr_bitfield_default }, + { "INPUT_CRC_CHANNEL_RESULT_SEL", 8, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZALIA_INPUT_CRC1_RESULT[] = { + { "INPUT_CRC_RESULT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZALIA_CRC0_CONTROL0[] = { + { "CRC_EN", 0, 0, &umr_bitfield_default }, + { "CRC_BLOCK_MODE", 4, 4, &umr_bitfield_default }, + { "CRC_INSTANCE_SEL", 8, 10, &umr_bitfield_default }, + { "CRC_SOURCE_SEL", 12, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZALIA_CRC0_CONTROL1[] = { + { "CRC_BLOCK_SIZE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZALIA_CRC0_CONTROL2[] = { + { "CRC_BLOCK_ITERATION", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZALIA_CRC0_CONTROL3[] = { + { "CRC_COMPLETE", 0, 0, &umr_bitfield_default }, + { "CRC_BLOCK_COMPLETE_PHASE", 4, 4, &umr_bitfield_default }, + { "CRC_CHANNEL_RESULT_SEL", 8, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZALIA_CRC0_RESULT[] = { + { "CRC_RESULT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZALIA_CRC1_CONTROL0[] = { + { "CRC_EN", 0, 0, &umr_bitfield_default }, + { "CRC_BLOCK_MODE", 4, 4, &umr_bitfield_default }, + { "CRC_INSTANCE_SEL", 8, 10, &umr_bitfield_default }, + { "CRC_SOURCE_SEL", 12, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZALIA_CRC1_CONTROL1[] = { + { "CRC_BLOCK_SIZE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZALIA_CRC1_CONTROL2[] = { + { "CRC_BLOCK_ITERATION", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZALIA_CRC1_CONTROL3[] = { + { "CRC_COMPLETE", 0, 0, &umr_bitfield_default }, + { "CRC_BLOCK_COMPLETE_PHASE", 4, 4, &umr_bitfield_default }, + { "CRC_CHANNEL_RESULT_SEL", 8, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZALIA_CRC1_RESULT[] = { + { "CRC_RESULT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZALIA_MEM_PWR_CTRL[] = { + { "AZ_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default }, + { "AZ_MEM_PWR_DIS", 2, 2, &umr_bitfield_default }, + { "AZ_INPUT_STREAM0_MEM_PWR_FORCE", 3, 4, &umr_bitfield_default }, + { "AZ_INPUT_STREAM0_MEM_PWR_DIS", 5, 5, &umr_bitfield_default }, + { "AZ_INPUT_STREAM1_MEM_PWR_FORCE", 6, 7, &umr_bitfield_default }, + { "AZ_INPUT_STREAM1_MEM_PWR_DIS", 8, 8, &umr_bitfield_default }, + { "AZ_INPUT_STREAM2_MEM_PWR_FORCE", 9, 10, &umr_bitfield_default }, + { "AZ_INPUT_STREAM2_MEM_PWR_DIS", 11, 11, &umr_bitfield_default }, + { "AZ_INPUT_STREAM3_MEM_PWR_FORCE", 12, 13, &umr_bitfield_default }, + { "AZ_INPUT_STREAM3_MEM_PWR_DIS", 14, 14, &umr_bitfield_default }, + { "AZ_INPUT_STREAM4_MEM_PWR_FORCE", 15, 16, &umr_bitfield_default }, + { "AZ_INPUT_STREAM4_MEM_PWR_DIS", 17, 17, &umr_bitfield_default }, + { "AZ_INPUT_STREAM5_MEM_PWR_FORCE", 18, 19, &umr_bitfield_default }, + { "AZ_INPUT_STREAM5_MEM_PWR_DIS", 20, 20, &umr_bitfield_default }, + { "AZ_MEM_PWR_MODE_SEL", 28, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZALIA_MEM_PWR_STATUS[] = { + { "AZ_MEM_PWR_STATE", 0, 1, &umr_bitfield_default }, + { "AZ_INPUT_STREAM0_MEM_PWR_STATE", 2, 3, &umr_bitfield_default }, + { "AZ_INPUT_STREAM1_MEM_PWR_STATE", 4, 5, &umr_bitfield_default }, + { "AZ_INPUT_STREAM2_MEM_PWR_STATE", 6, 7, &umr_bitfield_default }, + { "AZ_INPUT_STREAM3_MEM_PWR_STATE", 8, 9, &umr_bitfield_default }, + { "AZ_INPUT_STREAM4_MEM_PWR_STATE", 10, 11, &umr_bitfield_default }, + { "AZ_INPUT_STREAM5_MEM_PWR_STATE", 12, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID[] = { + { "AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID[] = { + { "AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL[] = { + { "HBR_CHANNEL_COUNT", 0, 2, &umr_bitfield_default }, + { "COMPRESSED_CHANNEL_COUNT", 4, 6, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL[] = { + { "RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW", 0, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE[] = { + { "AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES[] = { + { "AUDIO_RATE_CAPABILITIES", 0, 11, &umr_bitfield_default }, + { "AUDIO_BIT_CAPABILITIES", 16, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS[] = { + { "AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES[] = { + { "AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES", 0, 29, &umr_bitfield_default }, + { "CLKSTOP", 30, 30, &umr_bitfield_default }, + { "EPSS", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE[] = { + { "POWER_STATE_SET", 0, 3, &umr_bitfield_default }, + { "POWER_STATE_ACT", 4, 7, &umr_bitfield_default }, + { "CLKSTOPOK", 9, 9, &umr_bitfield_default }, + { "POWER_STATE_SETTINGS_RESET", 10, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET[] = { + { "CODEC_RESET", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID[] = { + { "SUBSYSTEM_ID_BYTE0", 0, 7, &umr_bitfield_default }, + { "SUBSYSTEM_ID_BYTE1", 8, 15, &umr_bitfield_default }, + { "SUBSYSTEM_ID_BYTE2", 16, 23, &umr_bitfield_default }, + { "SUBSYSTEM_ID_BYTE3", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION[] = { + { "CONVERTER_SYNCHRONIZATION", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY[] = { + { "PORT_CONNECTIVITY", 0, 2, &umr_bitfield_default }, + { "PORT_CONNECTIVITY_OVERRIDE_ENABLE", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY[] = { + { "INPUT_PORT_CONNECTIVITY", 0, 2, &umr_bitfield_default }, + { "INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZALIA_F0_GTC_GROUP_OFFSET0[] = { + { "GTC_GROUP_OFFSET0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZALIA_F0_GTC_GROUP_OFFSET1[] = { + { "GTC_GROUP_OFFSET1", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZALIA_F0_GTC_GROUP_OFFSET2[] = { + { "GTC_GROUP_OFFSET2", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZALIA_F0_GTC_GROUP_OFFSET3[] = { + { "GTC_GROUP_OFFSET3", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZALIA_F0_GTC_GROUP_OFFSET4[] = { + { "GTC_GROUP_OFFSET4", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZALIA_F0_GTC_GROUP_OFFSET5[] = { + { "GTC_GROUP_OFFSET5", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZALIA_F0_GTC_GROUP_OFFSET6[] = { + { "GTC_GROUP_OFFSET6", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmREG_DC_AUDIO_PORT_CONNECTIVITY[] = { + { "REG_PORT_CONNECTIVITY", 0, 2, &umr_bitfield_default }, + { "REG_PORT_CONNECTIVITY_OVERRIDE_ENABLE", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY[] = { + { "REG_INPUT_PORT_CONNECTIVITY", 0, 2, &umr_bitfield_default }, + { "REG_INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZF0STREAM8_AZALIA_STREAM_INDEX[] = { + { "AZALIA_STREAM_REG_INDEX", 0, 7, &umr_bitfield_default }, + { "AZALIA_STREAM_REG_WRITE_EN", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZF0STREAM8_AZALIA_STREAM_DATA[] = { + { "AZALIA_STREAM_REG_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZF0STREAM9_AZALIA_STREAM_INDEX[] = { + { "AZALIA_STREAM_REG_INDEX", 0, 7, &umr_bitfield_default }, + { "AZALIA_STREAM_REG_WRITE_EN", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZF0STREAM9_AZALIA_STREAM_DATA[] = { + { "AZALIA_STREAM_REG_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZF0STREAM10_AZALIA_STREAM_INDEX[] = { + { "AZALIA_STREAM_REG_INDEX", 0, 7, &umr_bitfield_default }, + { "AZALIA_STREAM_REG_WRITE_EN", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZF0STREAM10_AZALIA_STREAM_DATA[] = { + { "AZALIA_STREAM_REG_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZF0STREAM11_AZALIA_STREAM_INDEX[] = { + { "AZALIA_STREAM_REG_INDEX", 0, 7, &umr_bitfield_default }, + { "AZALIA_STREAM_REG_WRITE_EN", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZF0STREAM11_AZALIA_STREAM_DATA[] = { + { "AZALIA_STREAM_REG_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZF0STREAM12_AZALIA_STREAM_INDEX[] = { + { "AZALIA_STREAM_REG_INDEX", 0, 7, &umr_bitfield_default }, + { "AZALIA_STREAM_REG_WRITE_EN", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZF0STREAM12_AZALIA_STREAM_DATA[] = { + { "AZALIA_STREAM_REG_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZF0STREAM13_AZALIA_STREAM_INDEX[] = { + { "AZALIA_STREAM_REG_INDEX", 0, 7, &umr_bitfield_default }, + { "AZALIA_STREAM_REG_WRITE_EN", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZF0STREAM13_AZALIA_STREAM_DATA[] = { + { "AZALIA_STREAM_REG_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZF0STREAM14_AZALIA_STREAM_INDEX[] = { + { "AZALIA_STREAM_REG_INDEX", 0, 7, &umr_bitfield_default }, + { "AZALIA_STREAM_REG_WRITE_EN", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZF0STREAM14_AZALIA_STREAM_DATA[] = { + { "AZALIA_STREAM_REG_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZF0STREAM15_AZALIA_STREAM_INDEX[] = { + { "AZALIA_STREAM_REG_INDEX", 0, 7, &umr_bitfield_default }, + { "AZALIA_STREAM_REG_WRITE_EN", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZF0STREAM15_AZALIA_STREAM_DATA[] = { + { "AZALIA_STREAM_REG_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX[] = { + { "AZALIA_INPUT_ENDPOINT_REG_INDEX", 0, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA[] = { + { "AZALIA_INPUT_ENDPOINT_REG_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX[] = { + { "AZALIA_INPUT_ENDPOINT_REG_INDEX", 0, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA[] = { + { "AZALIA_INPUT_ENDPOINT_REG_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX[] = { + { "AZALIA_INPUT_ENDPOINT_REG_INDEX", 0, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA[] = { + { "AZALIA_INPUT_ENDPOINT_REG_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX[] = { + { "AZALIA_INPUT_ENDPOINT_REG_INDEX", 0, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA[] = { + { "AZALIA_INPUT_ENDPOINT_REG_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX[] = { + { "AZALIA_INPUT_ENDPOINT_REG_INDEX", 0, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA[] = { + { "AZALIA_INPUT_ENDPOINT_REG_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX[] = { + { "AZALIA_INPUT_ENDPOINT_REG_INDEX", 0, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA[] = { + { "AZALIA_INPUT_ENDPOINT_REG_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX[] = { + { "AZALIA_INPUT_ENDPOINT_REG_INDEX", 0, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA[] = { + { "AZALIA_INPUT_ENDPOINT_REG_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX[] = { + { "AZALIA_INPUT_ENDPOINT_REG_INDEX", 0, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA[] = { + { "AZALIA_INPUT_ENDPOINT_REG_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_SDPIF_CFG0[] = { + { "SDPIF_NO_OUTSTANDING_REQ", 0, 0, &umr_bitfield_default }, + { "SDPIF_PORT_STATUS", 1, 2, &umr_bitfield_default }, + { "SDPIF_DATA_RESPONSE_STATUS", 3, 5, &umr_bitfield_default }, + { "SDPIF_REQ_CREDIT_ERROR", 6, 6, &umr_bitfield_default }, + { "SDPIF_DATA_RESPONSE_STATUS_CLEAR", 7, 7, &umr_bitfield_default }, + { "SDPIF_REQ_CREDIT_ERROR_CLEAR", 8, 8, &umr_bitfield_default }, + { "SDPIF_FLUSH_REQ_CREDIT_EN", 9, 9, &umr_bitfield_default }, + { "SDPIF_REQ_CREDIT_EN", 10, 10, &umr_bitfield_default }, + { "SDPIF_PORT_CONTROL", 11, 11, &umr_bitfield_default }, + { "SDPIF_UNIT_ID_BITMASK", 12, 19, &umr_bitfield_default }, + { "SDPIF_CREDIT_DISCONNECT_DELAY", 20, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_SDPIF_CFG1[] = { + { "SDPIF_INSIDE_FB_IO", 0, 0, &umr_bitfield_default }, + { "SDPIF_INSIDE_FB_VC", 1, 3, &umr_bitfield_default }, + { "SDPIF_OUTSIDE_FB_IO", 4, 4, &umr_bitfield_default }, + { "SDPIF_OUTSIDE_FB_VC", 5, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_FORCE_IO_STATUS_0[] = { + { "SDPIF_FORCE_IO_STATUS", 0, 0, &umr_bitfield_default }, + { "SDPIF_FORCE_IO_STATUS_STICKY", 1, 1, &umr_bitfield_default }, + { "SDPIF_FORCE_IO_STATUS_CLEAR", 2, 2, &umr_bitfield_default }, + { "SDPIF_FORCE_IO_STATUS_PIPE_ID", 3, 6, &umr_bitfield_default }, + { "SDPIF_FORCE_IO_STATUS_REQUEST_TYPE", 7, 9, &umr_bitfield_default }, + { "SDPIF_FORCE_IO_STATUS_ADDR_LO", 10, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_FORCE_IO_STATUS_1[] = { + { "SDPIF_FORCE_IO_STATUS_ADDR_HI", 0, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_SDPIF_FB_BASE[] = { + { "SDPIF_FB_BASE", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_SDPIF_FB_TOP[] = { + { "SDPIF_FB_TOP", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_SDPIF_FB_OFFSET[] = { + { "SDPIF_FB_OFFSET", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_SDPIF_AGP_BOT[] = { + { "SDPIF_AGP_BOT", 0, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_SDPIF_AGP_TOP[] = { + { "SDPIF_AGP_TOP", 0, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_SDPIF_AGP_BASE[] = { + { "SDPIF_AGP_BASE", 0, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_SDPIF_APER_BASE[] = { + { "SDPIF_APER_BASE", 0, 27, &umr_bitfield_default }, + { "SDPIF_LOCK_DRAM_REGS", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_SDPIF_APER_TOP[] = { + { "SDPIF_APER_TOP", 0, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_SDPIF_APER_DEF_0[] = { + { "SDPIF_APER_DEF_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_SDPIF_APER_DEF_1[] = { + { "SDPIF_APER_DEF_1", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_SDPIF_MMIO_CNTRL_0[] = { + { "SDPIF_IOMMU_EN", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_SDPIF_MMIO_CNTRL_1[] = { + { "SDPIF_MARC_EN", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_SDPIF_MMIO_CNTRL_W[] = { + { "SDPIF_GMC_IOMMU_BYPASS", 13, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_SDPIF_MARC_BASE_LO_0[] = { + { "SDPIF_MARC_BASE_LO_0", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_SDPIF_MARC_BASE_HI_0[] = { + { "SDPIF_MARC_BASE_HI_0", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_SDPIF_MARC_RELOC_LO_0[] = { + { "SDPIF_MARC_EN_0", 0, 0, &umr_bitfield_default }, + { "SDPIF_MARC_RELOC_LO_0", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_SDPIF_MARC_RELOC_HI_0[] = { + { "SDPIF_MARC_RELOC_HI_0", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_0[] = { + { "SDPIF_MARC_LENGTH_LO_0", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_0[] = { + { "SDPIF_MARC_LENGTH_HI_0", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_SDPIF_MARC_BASE_LO_1[] = { + { "SDPIF_MARC_BASE_LO_1", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_SDPIF_MARC_BASE_HI_1[] = { + { "SDPIF_MARC_BASE_HI_1", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_SDPIF_MARC_RELOC_LO_1[] = { + { "SDPIF_MARC_EN_1", 0, 0, &umr_bitfield_default }, + { "SDPIF_MARC_RELOC_LO_1", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_SDPIF_MARC_RELOC_HI_1[] = { + { "SDPIF_MARC_RELOC_HI_1", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_1[] = { + { "SDPIF_MARC_LENGTH_LO_1", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_1[] = { + { "SDPIF_MARC_LENGTH_HI_1", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_SDPIF_MARC_BASE_LO_2[] = { + { "SDPIF_MARC_BASE_LO_2", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_SDPIF_MARC_BASE_HI_2[] = { + { "SDPIF_MARC_BASE_HI_2", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_SDPIF_MARC_RELOC_LO_2[] = { + { "SDPIF_MARC_EN_2", 0, 0, &umr_bitfield_default }, + { "SDPIF_MARC_RELOC_LO_2", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_SDPIF_MARC_RELOC_HI_2[] = { + { "SDPIF_MARC_RELOC_HI_2", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_2[] = { + { "SDPIF_MARC_LENGTH_LO_2", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_2[] = { + { "SDPIF_MARC_LENGTH_HI_2", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_SDPIF_MARC_BASE_LO_3[] = { + { "SDPIF_MARC_BASE_LO_3", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_SDPIF_MARC_BASE_HI_3[] = { + { "SDPIF_MARC_BASE_HI_3", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_SDPIF_MARC_RELOC_LO_3[] = { + { "SDPIF_MARC_EN_3", 0, 0, &umr_bitfield_default }, + { "SDPIF_MARC_RELOC_LO_3", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_SDPIF_MARC_RELOC_HI_3[] = { + { "SDPIF_MARC_RELOC_HI_3", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_3[] = { + { "SDPIF_MARC_LENGTH_LO_3", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_3[] = { + { "SDPIF_MARC_LENGTH_HI_3", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_SDPIF_PIPE_SEC_LVL[] = { + { "SDPIF_PIPE0_SEC_LVL", 0, 2, &umr_bitfield_default }, + { "SDPIF_PIPE1_SEC_LVL", 3, 5, &umr_bitfield_default }, + { "SDPIF_PIPE2_SEC_LVL", 6, 8, &umr_bitfield_default }, + { "SDPIF_PIPE3_SEC_LVL", 9, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_SDPIF_MEM_PWR_CTRL[] = { + { "DCHUBBUB_SDPIF_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default }, + { "DCHUBBUB_SDPIF_MEM_PWR_DIS", 2, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_SDPIF_MEM_PWR_STATUS[] = { + { "DCHUBBUB_SDPIF_MEM_PWR_STATE", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_RET_PATH_DCC_CFG[] = { + { "DCC_VIDEO_FORMAT_EN", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_RET_PATH_DCC_CFG0_0[] = { + { "DCC_CFG0_CONSTANT_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_RET_PATH_DCC_CFG0_1[] = { + { "DCC_CFG0_CONSTANT_1", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_RET_PATH_DCC_CFG1_0[] = { + { "DCC_CFG1_CONSTANT_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_RET_PATH_DCC_CFG1_1[] = { + { "DCC_CFG1_CONSTANT_1", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_RET_PATH_DCC_CFG2_0[] = { + { "DCC_CFG2_CONSTANT_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_RET_PATH_DCC_CFG2_1[] = { + { "DCC_CFG2_CONSTANT_1", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_RET_PATH_DCC_CFG3_0[] = { + { "DCC_CFG3_CONSTANT_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_RET_PATH_DCC_CFG3_1[] = { + { "DCC_CFG3_CONSTANT_1", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_RET_PATH_DCC_CFG4_0[] = { + { "DCC_CFG4_CONSTANT_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_RET_PATH_DCC_CFG4_1[] = { + { "DCC_CFG4_CONSTANT_1", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_RET_PATH_DCC_CFG5_0[] = { + { "DCC_CFG5_CONSTANT_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_RET_PATH_DCC_CFG5_1[] = { + { "DCC_CFG5_CONSTANT_1", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_RET_PATH_DCC_CFG6_0[] = { + { "DCC_CFG6_CONSTANT_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_RET_PATH_DCC_CFG6_1[] = { + { "DCC_CFG6_CONSTANT_1", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_RET_PATH_DCC_CFG7_0[] = { + { "DCC_CFG7_CONSTANT_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_RET_PATH_DCC_CFG7_1[] = { + { "DCC_CFG7_CONSTANT_1", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL[] = { + { "DCHUBBUB_RET_PATH_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default }, + { "DCHUBBUB_RET_PATH_MEM_PWR_DIS", 2, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS[] = { + { "DCHUBBUB_RET_PATH_MEM_PWR_STATE", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_CRC_CTRL[] = { + { "DCHUBBUB_CRC_EN", 0, 0, &umr_bitfield_default }, + { "DCHUBBUB_CRC_CONT_EN", 1, 1, &umr_bitfield_default }, + { "DCHUBBUB_CRC0_ONE_SHOT_PENDING", 2, 2, &umr_bitfield_default }, + { "DCHUBBUB_CRC1_ONE_SHOT_PENDING", 3, 3, &umr_bitfield_default }, + { "DCHUBBUB_CRC0_SRC_SEL", 4, 5, &umr_bitfield_default }, + { "DCHUBBUB_CRC1_SRC_SEL", 6, 7, &umr_bitfield_default }, + { "DCHUBBUB_CRC_PIPE_SEL", 8, 11, &umr_bitfield_default }, + { "DCHUBBUB_CRC_SURF_SEL", 12, 13, &umr_bitfield_default }, + { "DCHUBBUB_CRC_DATA_SRC_SEL", 14, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_CRC0_VAL_R_G[] = { + { "DCHUBBUB_CRC0_R_CR", 0, 15, &umr_bitfield_default }, + { "DCHUBBUB_CRC0_G_Y", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_CRC0_VAL_B_A[] = { + { "DCHUBBUB_CRC0_B_CB", 0, 15, &umr_bitfield_default }, + { "DCHUBBUB_CRC0_ALPHA", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_CRC1_VAL_R_G[] = { + { "DCHUBBUB_CRC1_R_CR", 0, 15, &umr_bitfield_default }, + { "DCHUBBUB_CRC1_G_Y", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_CRC1_VAL_B_A[] = { + { "DCHUBBUB_CRC1_B_CB", 0, 15, &umr_bitfield_default }, + { "DCHUBBUB_CRC1_ALPHA", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_ARB_DF_REQ_OUTSTAND[] = { + { "DCHUBBUB_ARB_MAX_REQ_OUTSTAND", 0, 8, &umr_bitfield_default }, + { "DCHUBBUB_ARB_MIN_REQ_OUTSTAND", 16, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_ARB_SAT_LEVEL[] = { + { "DCHUBBUB_ARB_SAT_LEVEL", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_ARB_QOS_FORCE[] = { + { "DCHUBBUB_ARB_QOS_FORCE_VALUE", 0, 3, &umr_bitfield_default }, + { "DCHUBBUB_ARB_QOS_FORCE_ENABLE", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_ARB_DRAM_STATE_CNTL[] = { + { "DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE", 0, 0, &umr_bitfield_default }, + { "DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE", 1, 1, &umr_bitfield_default }, + { "DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCED_CLEAR_DISABLE", 2, 2, &umr_bitfield_default }, + { "DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE", 4, 4, &umr_bitfield_default }, + { "DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE", 5, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A[] = { + { "DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A", 0, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A[] = { + { "DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A", 0, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A[] = { + { "DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A", 0, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A[] = { + { "DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A", 0, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A[] = { + { "DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A", 0, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B[] = { + { "DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B", 0, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B[] = { + { "DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B", 0, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B[] = { + { "DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B", 0, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B[] = { + { "DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B", 0, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B[] = { + { "DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B", 0, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C[] = { + { "DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C", 0, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C[] = { + { "DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C", 0, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C[] = { + { "DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C", 0, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C[] = { + { "DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C", 0, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C[] = { + { "DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C", 0, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D[] = { + { "DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D", 0, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D[] = { + { "DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D", 0, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D[] = { + { "DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D", 0, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D[] = { + { "DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D", 0, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D[] = { + { "DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D", 0, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL[] = { + { "DCHUBBUB_ARB_WATERMARK_CHANGE_SELECT", 0, 1, &umr_bitfield_default }, + { "DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE", 4, 4, &umr_bitfield_default }, + { "DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_STATUS", 5, 5, &umr_bitfield_default }, + { "DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_ACK", 6, 6, &umr_bitfield_default }, + { "DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_ARB_TIMEOUT_ENABLE[] = { + { "DCHUBBUB_ARB_TIMEOUT_ENABLE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_GLOBAL_TIMER_CNTL[] = { + { "DCHUBBUB_GLOBAL_TIMER_REFDIV", 0, 3, &umr_bitfield_default }, + { "DCHUBBUB_GLOBAL_TIMER_ENABLE", 12, 12, &umr_bitfield_default }, + { "DCHUBBUB_GLOBAL_TIMER_INIT", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSURFACE_CHECK0_ADDRESS_LSB[] = { + { "SURFACE_CHECK0_ADDRESS_LSB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSURFACE_CHECK0_ADDRESS_MSB[] = { + { "SURFACE_CHECK0_ADDRESS_MSB", 0, 15, &umr_bitfield_default }, + { "CHECKER0_SURFACE_INUSE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSURFACE_CHECK1_ADDRESS_LSB[] = { + { "SURFACE_CHECK1_ADDRESS_LSB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSURFACE_CHECK1_ADDRESS_MSB[] = { + { "SURFACE_CHECK1_ADDRESS_MSB", 0, 15, &umr_bitfield_default }, + { "CHECKER1_SURFACE_INUSE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSURFACE_CHECK2_ADDRESS_LSB[] = { + { "SURFACE_CHECK2_ADDRESS_LSB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSURFACE_CHECK2_ADDRESS_MSB[] = { + { "SURFACE_CHECK2_ADDRESS_MSB", 0, 15, &umr_bitfield_default }, + { "CHECKER2_SURFACE_INUSE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSURFACE_CHECK3_ADDRESS_LSB[] = { + { "SURFACE_CHECK3_ADDRESS_LSB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSURFACE_CHECK3_ADDRESS_MSB[] = { + { "SURFACE_CHECK3_ADDRESS_MSB", 0, 15, &umr_bitfield_default }, + { "CHECKER3_SURFACE_INUSE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVTG0_CONTROL[] = { + { "VTG0_FP2", 0, 14, &umr_bitfield_default }, + { "VTG0_VCOUNT_INIT", 15, 29, &umr_bitfield_default }, + { "VTG0_ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVTG1_CONTROL[] = { + { "VTG1_FP2", 0, 14, &umr_bitfield_default }, + { "VTG1_VCOUNT_INIT", 15, 29, &umr_bitfield_default }, + { "VTG1_ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVTG2_CONTROL[] = { + { "VTG2_FP2", 0, 14, &umr_bitfield_default }, + { "VTG2_VCOUNT_INIT", 15, 29, &umr_bitfield_default }, + { "VTG2_ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVTG3_CONTROL[] = { + { "VTG3_FP2", 0, 14, &umr_bitfield_default }, + { "VTG3_VCOUNT_INIT", 15, 29, &umr_bitfield_default }, + { "VTG3_ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVTG4_CONTROL[] = { + { "VTG4_FP2", 0, 14, &umr_bitfield_default }, + { "VTG4_VCOUNT_INIT", 15, 29, &umr_bitfield_default }, + { "VTG4_ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVTG5_CONTROL[] = { + { "VTG5_FP2", 0, 14, &umr_bitfield_default }, + { "VTG5_VCOUNT_INIT", 15, 29, &umr_bitfield_default }, + { "VTG5_ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_SOFT_RESET[] = { + { "DCHUBBUB_GLOBAL_SOFT_RESET", 0, 0, &umr_bitfield_default }, + { "ALLOW_CSTATE_SOFT_RESET", 1, 1, &umr_bitfield_default }, + { "GLBFLIP_SOFT_RESET", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_CLOCK_CNTL[] = { + { "DCHUBBUB_TEST_CLK_SEL", 0, 4, &umr_bitfield_default }, + { "DISPCLK_R_DCHUBBUB_GATE_DIS", 5, 5, &umr_bitfield_default }, + { "DCFCLK_R_DCHUBBUB_GATE_DIS", 6, 6, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCFCLK_CNTL[] = { + { "DCFCLK_TURN_ON_DELAY", 0, 3, &umr_bitfield_default }, + { "DCFCLK_TURN_OFF_DELAY", 4, 11, &umr_bitfield_default }, + { "DCFCLK_GATE_DIS", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL[] = { + { "DCHUBBUB_LATENCY_CNT_EN", 0, 0, &umr_bitfield_default }, + { "ARB_LATENCY_PIPE_SEL", 3, 6, &umr_bitfield_default }, + { "ARB_LATENCY_REQ_TYPE_SEL", 7, 9, &umr_bitfield_default }, + { "DF_LATENCY_URGENT_ONLY", 10, 10, &umr_bitfield_default }, + { "ROB_FIFO_LEVEL", 11, 20, &umr_bitfield_default }, + { "ROB_MAX_FIFO_LEVEL", 21, 30, &umr_bitfield_default }, + { "ROB_MAX_FIFO_LEVEL_RESET", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2[] = { + { "DCHUBBUB_LATENCY_FRAME_WIN_EN", 0, 0, &umr_bitfield_default }, + { "DCHUBBUB_LATENCY_FRAME_WIN_SRC_SEL", 1, 3, &umr_bitfield_default }, + { "DCHUBBUB_LATENCY_FRAME_WIN_DUR", 4, 11, &umr_bitfield_default }, + { "LATENCY_SOURCE_SEL", 12, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_VLINE_SNAPSHOT[] = { + { "DCHUBBUB_VLINE_SNAPSHOT", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCHUBBUB_SPARE[] = { + { "DCHUBBUB_SPARE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON7_PERFCOUNTER_CNTL[] = { + { "PERFCOUNTER_EVENT_SEL", 0, 8, &umr_bitfield_default }, + { "PERFCOUNTER_CVALUE_SEL", 9, 11, &umr_bitfield_default }, + { "PERFCOUNTER_INC_MODE", 12, 14, &umr_bitfield_default }, + { "PERFCOUNTER_HW_CNTL_SEL", 15, 15, &umr_bitfield_default }, + { "PERFCOUNTER_RUNEN_MODE", 16, 16, &umr_bitfield_default }, + { "PERFCOUNTER_CNTOFF_START_DIS", 22, 22, &umr_bitfield_default }, + { "PERFCOUNTER_RESTART_EN", 23, 23, &umr_bitfield_default }, + { "PERFCOUNTER_INT_EN", 24, 24, &umr_bitfield_default }, + { "PERFCOUNTER_OFF_MASK", 25, 25, &umr_bitfield_default }, + { "PERFCOUNTER_ACTIVE", 26, 26, &umr_bitfield_default }, + { "PERFCOUNTER_CNTL_SEL", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON7_PERFCOUNTER_CNTL2[] = { + { "PERFCOUNTER_COUNTED_VALUE_TYPE", 0, 1, &umr_bitfield_default }, + { "PERFCOUNTER_HW_STOP1_SEL", 2, 2, &umr_bitfield_default }, + { "PERFCOUNTER_HW_STOP2_SEL", 3, 3, &umr_bitfield_default }, + { "PERFCOUNTER_CNTOFF_SEL", 8, 13, &umr_bitfield_default }, + { "PERFCOUNTER_CNTL2_SEL", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON7_PERFCOUNTER_STATE[] = { + { "PERFCOUNTER_CNT0_STATE", 0, 1, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL0", 2, 2, &umr_bitfield_default }, + { "PERFCOUNTER_CNT1_STATE", 4, 5, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL1", 6, 6, &umr_bitfield_default }, + { "PERFCOUNTER_CNT2_STATE", 8, 9, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL2", 10, 10, &umr_bitfield_default }, + { "PERFCOUNTER_CNT3_STATE", 12, 13, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL3", 14, 14, &umr_bitfield_default }, + { "PERFCOUNTER_CNT4_STATE", 16, 17, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL4", 18, 18, &umr_bitfield_default }, + { "PERFCOUNTER_CNT5_STATE", 20, 21, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL5", 22, 22, &umr_bitfield_default }, + { "PERFCOUNTER_CNT6_STATE", 24, 25, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL6", 26, 26, &umr_bitfield_default }, + { "PERFCOUNTER_CNT7_STATE", 28, 29, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL7", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON7_PERFMON_CNTL[] = { + { "PERFMON_STATE", 0, 1, &umr_bitfield_default }, + { "PERFMON_RPT_COUNT", 8, 27, &umr_bitfield_default }, + { "PERFMON_CNTOFF_AND_OR", 28, 28, &umr_bitfield_default }, + { "PERFMON_CNTOFF_INT_EN", 29, 29, &umr_bitfield_default }, + { "PERFMON_CNTOFF_INT_STATUS", 30, 30, &umr_bitfield_default }, + { "PERFMON_CNTOFF_INT_ACK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON7_PERFMON_CNTL2[] = { + { "PERFMON_CNTOFF_INT_TYPE", 0, 0, &umr_bitfield_default }, + { "PERFMON_CLK_ENABLE", 1, 1, &umr_bitfield_default }, + { "PERFMON_RUN_ENABLE_START_SEL", 2, 9, &umr_bitfield_default }, + { "PERFMON_RUN_ENABLE_STOP_SEL", 10, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC[] = { + { "PERFCOUNTER_INT0_STATUS", 0, 0, &umr_bitfield_default }, + { "PERFCOUNTER_INT1_STATUS", 1, 1, &umr_bitfield_default }, + { "PERFCOUNTER_INT2_STATUS", 2, 2, &umr_bitfield_default }, + { "PERFCOUNTER_INT3_STATUS", 3, 3, &umr_bitfield_default }, + { "PERFCOUNTER_INT4_STATUS", 4, 4, &umr_bitfield_default }, + { "PERFCOUNTER_INT5_STATUS", 5, 5, &umr_bitfield_default }, + { "PERFCOUNTER_INT6_STATUS", 6, 6, &umr_bitfield_default }, + { "PERFCOUNTER_INT7_STATUS", 7, 7, &umr_bitfield_default }, + { "PERFCOUNTER_INT0_ACK", 8, 8, &umr_bitfield_default }, + { "PERFCOUNTER_INT1_ACK", 9, 9, &umr_bitfield_default }, + { "PERFCOUNTER_INT2_ACK", 10, 10, &umr_bitfield_default }, + { "PERFCOUNTER_INT3_ACK", 11, 11, &umr_bitfield_default }, + { "PERFCOUNTER_INT4_ACK", 12, 12, &umr_bitfield_default }, + { "PERFCOUNTER_INT5_ACK", 13, 13, &umr_bitfield_default }, + { "PERFCOUNTER_INT6_ACK", 14, 14, &umr_bitfield_default }, + { "PERFCOUNTER_INT7_ACK", 15, 15, &umr_bitfield_default }, + { "PERFMON_CVALUE_HI", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON7_PERFMON_CVALUE_LOW[] = { + { "PERFMON_CVALUE_LOW", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON7_PERFMON_HI[] = { + { "PERFMON_HI", 0, 15, &umr_bitfield_default }, + { "PERFMON_READ_SEL", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON7_PERFMON_LOW[] = { + { "PERFMON_LOW", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP0_DCSURF_SURFACE_CONFIG[] = { + { "SURFACE_PIXEL_FORMAT", 0, 6, &umr_bitfield_default }, + { "ROTATION_ANGLE", 8, 9, &umr_bitfield_default }, + { "H_MIRROR_EN", 10, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP0_DCSURF_ADDR_CONFIG[] = { + { "NUM_PIPES", 0, 2, &umr_bitfield_default }, + { "NUM_BANKS", 3, 5, &umr_bitfield_default }, + { "PIPE_INTERLEAVE", 6, 7, &umr_bitfield_default }, + { "NUM_SE", 8, 9, &umr_bitfield_default }, + { "NUM_RB_PER_SE", 10, 11, &umr_bitfield_default }, + { "MAX_COMPRESSED_FRAGS", 12, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP0_DCSURF_TILING_CONFIG[] = { + { "SW_MODE", 0, 4, &umr_bitfield_default }, + { "DIM_TYPE", 7, 8, &umr_bitfield_default }, + { "META_LINEAR", 9, 9, &umr_bitfield_default }, + { "RB_ALIGNED", 10, 10, &umr_bitfield_default }, + { "PIPE_ALIGNED", 11, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP0_DCSURF_PRI_VIEWPORT_START[] = { + { "PRI_VIEWPORT_X_START", 0, 13, &umr_bitfield_default }, + { "PRI_VIEWPORT_Y_START", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION[] = { + { "PRI_VIEWPORT_WIDTH", 0, 13, &umr_bitfield_default }, + { "PRI_VIEWPORT_HEIGHT", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP0_DCSURF_PRI_VIEWPORT_START_C[] = { + { "PRI_VIEWPORT_X_START_C", 0, 13, &umr_bitfield_default }, + { "PRI_VIEWPORT_Y_START_C", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C[] = { + { "PRI_VIEWPORT_WIDTH_C", 0, 13, &umr_bitfield_default }, + { "PRI_VIEWPORT_HEIGHT_C", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP0_DCSURF_SEC_VIEWPORT_START[] = { + { "SEC_VIEWPORT_X_START", 0, 13, &umr_bitfield_default }, + { "SEC_VIEWPORT_Y_START", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION[] = { + { "SEC_VIEWPORT_WIDTH", 0, 13, &umr_bitfield_default }, + { "SEC_VIEWPORT_HEIGHT", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP0_DCSURF_SEC_VIEWPORT_START_C[] = { + { "SEC_VIEWPORT_X_START_C", 0, 13, &umr_bitfield_default }, + { "SEC_VIEWPORT_Y_START_C", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C[] = { + { "SEC_VIEWPORT_WIDTH_C", 0, 13, &umr_bitfield_default }, + { "SEC_VIEWPORT_HEIGHT_C", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP0_DCHUBP_REQ_SIZE_CONFIG[] = { + { "SWATH_HEIGHT", 0, 2, &umr_bitfield_default }, + { "PTE_ROW_HEIGHT_LINEAR", 4, 6, &umr_bitfield_default }, + { "CHUNK_SIZE", 8, 10, &umr_bitfield_default }, + { "MIN_CHUNK_SIZE", 11, 12, &umr_bitfield_default }, + { "META_CHUNK_SIZE", 16, 17, &umr_bitfield_default }, + { "MIN_META_CHUNK_SIZE", 18, 19, &umr_bitfield_default }, + { "DPTE_GROUP_SIZE", 20, 22, &umr_bitfield_default }, + { "MPTE_GROUP_SIZE", 24, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C[] = { + { "SWATH_HEIGHT_C", 0, 2, &umr_bitfield_default }, + { "PTE_ROW_HEIGHT_LINEAR_C", 4, 6, &umr_bitfield_default }, + { "CHUNK_SIZE_C", 8, 10, &umr_bitfield_default }, + { "MIN_CHUNK_SIZE_C", 11, 12, &umr_bitfield_default }, + { "META_CHUNK_SIZE_C", 16, 17, &umr_bitfield_default }, + { "MIN_META_CHUNK_SIZE_C", 18, 19, &umr_bitfield_default }, + { "DPTE_GROUP_SIZE_C", 20, 22, &umr_bitfield_default }, + { "MPTE_GROUP_SIZE_C", 24, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP0_DCHUBP_CNTL[] = { + { "HUBP_BLANK_EN", 0, 0, &umr_bitfield_default }, + { "HUBP_NO_OUTSTANDING_REQ", 1, 1, &umr_bitfield_default }, + { "HUBP_DISABLE", 2, 2, &umr_bitfield_default }, + { "HUBP_IN_BLANK", 3, 3, &umr_bitfield_default }, + { "HUBP_VTG_SEL", 4, 7, &umr_bitfield_default }, + { "HUBP_TTU_DISABLE", 12, 12, &umr_bitfield_default }, + { "HUBP_TTU_MODE", 13, 15, &umr_bitfield_default }, + { "HUBP_UNDERFLOW_STATUS", 28, 30, &umr_bitfield_default }, + { "HUBP_UNDERFLOW_CLEAR", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP0_HUBP_CLK_CNTL[] = { + { "HUBP_CLOCK_ENABLE", 0, 0, &umr_bitfield_default }, + { "HUBP_DISPCLK_R_GATE_DIS", 4, 4, &umr_bitfield_default }, + { "HUBP_DPPCLK_G_GATE_DIS", 8, 8, &umr_bitfield_default }, + { "HUBP_DCFCLK_R_GATE_DIS", 12, 12, &umr_bitfield_default }, + { "HUBP_DCFCLK_G_GATE_DIS", 16, 16, &umr_bitfield_default }, + { "HUBP_DISPCLK_R_CLOCK_ON", 20, 20, &umr_bitfield_default }, + { "HUBP_DPPCLK_G_CLOCK_ON", 21, 21, &umr_bitfield_default }, + { "HUBP_DCFCLK_R_CLOCK_ON", 22, 22, &umr_bitfield_default }, + { "HUBP_DCFCLK_G_CLOCK_ON", 23, 23, &umr_bitfield_default }, + { "HUBP_TEST_CLK_SEL", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP0_DCHUBP_VMPG_CONFIG[] = { + { "VMPG_SIZE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP0_HUBPREQ_DEBUG_DB[] = { + { "HUBPREQ_DEBUG", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK[] = { + { "HUBP_MEASURE_WIN_EN_DCFCLK", 0, 0, &umr_bitfield_default }, + { "HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK", 4, 11, &umr_bitfield_default }, + { "HUBP_PERFMON_START_SEL_DCFCLK", 12, 16, &umr_bitfield_default }, + { "HUBP_PERFMON_STOP_SEL_DCFCLK", 20, 24, &umr_bitfield_default }, + { "HUBP_MEASURE_WIN_MODE_DCFCLK", 28, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK[] = { + { "HUBP_MEASURE_WIN_EN_DPPCLK", 0, 0, &umr_bitfield_default }, + { "HUBP_MEASURE_WIN_SRC_SEL_DPPCLK", 1, 1, &umr_bitfield_default }, + { "HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK", 4, 11, &umr_bitfield_default }, + { "HUBP_PERFMON_START_SEL_DPPCLK", 12, 16, &umr_bitfield_default }, + { "HUBP_PERFMON_STOP_SEL_DPPCLK", 20, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_DCSURF_SURFACE_PITCH[] = { + { "PITCH", 0, 13, &umr_bitfield_default }, + { "META_PITCH", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_DCSURF_SURFACE_PITCH_C[] = { + { "PITCH_C", 0, 13, &umr_bitfield_default }, + { "META_PITCH_C", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS[] = { + { "PRIMARY_SURFACE_ADDRESS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH[] = { + { "PRIMARY_SURFACE_ADDRESS_HIGH", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C[] = { + { "PRIMARY_SURFACE_ADDRESS_C", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C[] = { + { "PRIMARY_SURFACE_ADDRESS_HIGH_C", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS[] = { + { "SECONDARY_SURFACE_ADDRESS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH[] = { + { "SECONDARY_SURFACE_ADDRESS_HIGH", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C[] = { + { "SECONDARY_SURFACE_ADDRESS_C", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C[] = { + { "SECONDARY_SURFACE_ADDRESS_HIGH_C", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS[] = { + { "PRIMARY_META_SURFACE_ADDRESS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH[] = { + { "PRIMARY_META_SURFACE_ADDRESS_HIGH", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C[] = { + { "PRIMARY_META_SURFACE_ADDRESS_C", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C[] = { + { "PRIMARY_META_SURFACE_ADDRESS_HIGH_C", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS[] = { + { "SECONDARY_META_SURFACE_ADDRESS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH[] = { + { "SECONDARY_META_SURFACE_ADDRESS_HIGH", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C[] = { + { "SECONDARY_META_SURFACE_ADDRESS_C", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C[] = { + { "SECONDARY_META_SURFACE_ADDRESS_HIGH_C", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_DCSURF_SURFACE_CONTROL[] = { + { "PRIMARY_SURFACE_DCC_EN", 1, 1, &umr_bitfield_default }, + { "PRIMARY_SURFACE_DCC_IND_64B_BLK", 2, 2, &umr_bitfield_default }, + { "PRIMARY_SURFACE_DCC_IND_64B_BLK_C", 5, 5, &umr_bitfield_default }, + { "SECONDARY_SURFACE_DCC_EN", 9, 9, &umr_bitfield_default }, + { "SECONDARY_SURFACE_DCC_IND_64B_BLK", 10, 10, &umr_bitfield_default }, + { "SECONDARY_SURFACE_DCC_IND_64B_BLK_C", 13, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_DCSURF_FLIP_CONTROL[] = { + { "SURFACE_UPDATE_LOCK", 0, 0, &umr_bitfield_default }, + { "SURFACE_FLIP_TYPE", 1, 1, &umr_bitfield_default }, + { "SURFACE_FLIP_VUPDATE_SKIP_NUM", 4, 7, &umr_bitfield_default }, + { "SURFACE_FLIP_MODE_FOR_STEREOSYNC", 12, 13, &umr_bitfield_default }, + { "SURFACE_FLIP_IN_STEREOSYNC", 16, 16, &umr_bitfield_default }, + { "SURFACE_FLIP_STEREO_SELECT_DISABLE", 17, 17, &umr_bitfield_default }, + { "SURFACE_FLIP_STEREO_SELECT_POLARITY", 18, 18, &umr_bitfield_default }, + { "SURFACE_FLIP_PENDING_DELAY", 20, 29, &umr_bitfield_default }, + { "SURFACE_UPDATE_PENDING", 30, 30, &umr_bitfield_default }, + { "SURFACE_FLIP_PENDING", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_DCSURF_FLIP_CONTROL2[] = { + { "SURFACE_UPDATE_FLIP_PENDING_MIN_TIME", 0, 7, &umr_bitfield_default }, + { "SURFACE_UPDATE_PENDING_HIGH_EXTEND_ENABLE", 12, 12, &umr_bitfield_default }, + { "SURFACE_FLIP_PENDING_HIGH_EXTEND_ENABLE", 13, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_DCSURF_FRAME_PACING_CONTROL[] = { + { "SURFACE_FRAME_PACING_ENABLE", 0, 0, &umr_bitfield_default }, + { "SURFACE_FRAME_PACING_MODE", 1, 1, &umr_bitfield_default }, + { "SURFACE_FRAME_PACING_QUEUE_RESET", 8, 8, &umr_bitfield_default }, + { "SURFACE_FRAME_PACING_QUEUE_FREE_ENTRY", 24, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_DCSURF_FRAME_PACING_TIME[] = { + { "SURFACE_FRAME_PACING_TIME", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT[] = { + { "SURFACE_FLIP_INT_MASK", 0, 0, &umr_bitfield_default }, + { "SURFACE_FLIP_INT_TYPE", 1, 1, &umr_bitfield_default }, + { "SURFACE_FLIP_AWAY_INT_MASK", 2, 2, &umr_bitfield_default }, + { "SURFACE_FLIP_AWAY_INT_TYPE", 3, 3, &umr_bitfield_default }, + { "SURFACE_FLIP_CLEAR", 8, 8, &umr_bitfield_default }, + { "SURFACE_FLIP_AWAY_CLEAR", 9, 9, &umr_bitfield_default }, + { "SURFACE_FLIP_OCCURRED", 16, 16, &umr_bitfield_default }, + { "SURFACE_FLIP_INT_STATUS", 17, 17, &umr_bitfield_default }, + { "SURFACE_FLIP_AWAY_OCCURRED", 18, 18, &umr_bitfield_default }, + { "SURFACE_FLIP_AWAY_INT_STATUS", 19, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_DCSURF_SURFACE_INUSE[] = { + { "SURFACE_INUSE_ADDRESS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH[] = { + { "SURFACE_INUSE_ADDRESS_HIGH", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_DCSURF_SURFACE_INUSE_C[] = { + { "SURFACE_INUSE_ADDRESS_C", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C[] = { + { "SURFACE_INUSE_ADDRESS_HIGH_C", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE[] = { + { "SURFACE_EARLIEST_INUSE_ADDRESS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH[] = { + { "SURFACE_EARLIEST_INUSE_ADDRESS_HIGH", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C[] = { + { "SURFACE_EARLIEST_INUSE_ADDRESS_C", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C[] = { + { "SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_DCN_EXPANSION_MODE[] = { + { "DRQ_EXPANSION_MODE", 0, 1, &umr_bitfield_default }, + { "CRQ_EXPANSION_MODE", 2, 3, &umr_bitfield_default }, + { "MRQ_EXPANSION_MODE", 4, 5, &umr_bitfield_default }, + { "PRQ_EXPANSION_MODE", 6, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_DCN_TTU_QOS_WM[] = { + { "QoS_LEVEL_LOW_WM", 0, 13, &umr_bitfield_default }, + { "QoS_LEVEL_HIGH_WM", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL[] = { + { "MIN_TTU_VBLANK", 0, 23, &umr_bitfield_default }, + { "QoS_LEVEL_FLIP", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_DCN_SURF0_TTU_CNTL0[] = { + { "REFCYC_PER_REQ_DELIVERY", 0, 22, &umr_bitfield_default }, + { "QoS_LEVEL_FIXED", 24, 27, &umr_bitfield_default }, + { "QoS_RAMP_DISABLE", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_DCN_SURF0_TTU_CNTL1[] = { + { "REFCYC_PER_REQ_DELIVERY_PRE", 0, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_DCN_SURF1_TTU_CNTL0[] = { + { "REFCYC_PER_REQ_DELIVERY", 0, 22, &umr_bitfield_default }, + { "QoS_LEVEL_FIXED", 24, 27, &umr_bitfield_default }, + { "QoS_RAMP_DISABLE", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_DCN_SURF1_TTU_CNTL1[] = { + { "REFCYC_PER_REQ_DELIVERY_PRE", 0, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_DCN_CUR0_TTU_CNTL0[] = { + { "REFCYC_PER_REQ_DELIVERY", 0, 22, &umr_bitfield_default }, + { "QoS_LEVEL_FIXED", 24, 27, &umr_bitfield_default }, + { "QoS_RAMP_DISABLE", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_DCN_CUR0_TTU_CNTL1[] = { + { "REFCYC_PER_REQ_DELIVERY_PRE", 0, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB[] = { + { "MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB[] = { + { "MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB[] = { + { "MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB[] = { + { "MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB[] = { + { "MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB[] = { + { "MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB", 0, 3, &umr_bitfield_default }, + { "MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM", 28, 28, &umr_bitfield_default }, + { "MC_VM_SYSTEM_APERTURE_DEFAULT_SNOOP", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB[] = { + { "VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB[] = { + { "VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB", 0, 3, &umr_bitfield_default }, + { "VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM", 28, 28, &umr_bitfield_default }, + { "VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SNOOP", 29, 29, &umr_bitfield_default }, + { "VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_TMZ", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB[] = { + { "VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB[] = { + { "VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB[] = { + { "VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB[] = { + { "VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB[] = { + { "VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB[] = { + { "VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_DCN_VM_CONTEXT0_STATUS[] = { + { "DCN_VM_CONTEXT0_ERROR_STATUS", 0, 15, &umr_bitfield_default }, + { "DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_MSB", 24, 27, &umr_bitfield_default }, + { "DCN_VM_CONTEXT0_ERROR_STATUS_MODE", 30, 30, &umr_bitfield_default }, + { "DCN_VM_CONTEXT0_ERROR_STATUS_CLEAR", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB[] = { + { "DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_DCN_VM_CONTEXT0_CNTL[] = { + { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 3, 3, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 4, 4, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 12, 12, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 13, 13, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL[] = { + { "ENABLE_L1_TLB", 0, 0, &umr_bitfield_default }, + { "SYSTEM_ACCESS_MODE", 3, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_BLANK_OFFSET_0[] = { + { "REFCYC_H_BLANK_END", 0, 12, &umr_bitfield_default }, + { "DLG_V_BLANK_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_BLANK_OFFSET_1[] = { + { "MIN_DST_Y_NEXT_START", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_DST_DIMENSIONS[] = { + { "REFCYC_PER_HTOTAL", 0, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_DST_AFTER_SCALER[] = { + { "REFCYC_X_AFTER_SCALER", 0, 12, &umr_bitfield_default }, + { "DST_Y_AFTER_SCALER", 16, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_PREFETCH_SETTINS[] = { + { "VRATIO_PREFETCH", 0, 20, &umr_bitfield_default }, + { "DST_Y_PREFETCH", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_PREFETCH_SETTINS_C[] = { + { "VRATIO_PREFETCH_C", 0, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_VBLANK_PARAMETERS_0[] = { + { "DST_Y_PER_VM_VBLANK", 0, 4, &umr_bitfield_default }, + { "DST_Y_PER_ROW_VBLANK", 8, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_VBLANK_PARAMETERS_1[] = { + { "REFCYC_PER_PTE_GROUP_VBLANK_L", 0, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_VBLANK_PARAMETERS_2[] = { + { "REFCYC_PER_PTE_GROUP_VBLANK_C", 0, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_VBLANK_PARAMETERS_3[] = { + { "REFCYC_PER_META_CHUNK_VBLANK_L", 0, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_VBLANK_PARAMETERS_4[] = { + { "REFCYC_PER_META_CHUNK_VBLANK_C", 0, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_NOM_PARAMETERS_0[] = { + { "DST_Y_PER_PTE_ROW_NOM_L", 0, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_NOM_PARAMETERS_1[] = { + { "REFCYC_PER_PTE_GROUP_NOM_L", 0, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_NOM_PARAMETERS_2[] = { + { "DST_Y_PER_PTE_ROW_NOM_C", 0, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_NOM_PARAMETERS_3[] = { + { "REFCYC_PER_PTE_GROUP_NOM_C", 0, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_NOM_PARAMETERS_4[] = { + { "DST_Y_PER_META_ROW_NOM_L", 0, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_NOM_PARAMETERS_5[] = { + { "REFCYC_PER_META_CHUNK_NOM_L", 0, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_NOM_PARAMETERS_6[] = { + { "DST_Y_PER_META_ROW_NOM_C", 0, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_NOM_PARAMETERS_7[] = { + { "REFCYC_PER_META_CHUNK_NOM_C", 0, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_PER_LINE_DELIVERY_PRE[] = { + { "REFCYC_PER_LINE_DELIVERY_PRE_L", 0, 12, &umr_bitfield_default }, + { "REFCYC_PER_LINE_DELIVERY_PRE_C", 16, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_PER_LINE_DELIVERY[] = { + { "REFCYC_PER_LINE_DELIVERY_L", 0, 12, &umr_bitfield_default }, + { "REFCYC_PER_LINE_DELIVERY_C", 16, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_CURSOR_SETTINS[] = { + { "CURSOR0_DST_Y_OFFSET", 0, 7, &umr_bitfield_default }, + { "CURSOR0_CHUNK_HDL_ADJUST", 8, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ[] = { + { "REF_FREQ_TO_PIX_FREQ", 0, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL[] = { + { "REQ_DPTE_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default }, + { "REQ_DPTE_MEM_PWR_DIS", 2, 2, &umr_bitfield_default }, + { "REQ_MPTE_MEM_PWR_FORCE", 4, 5, &umr_bitfield_default }, + { "REQ_MPTE_MEM_PWR_DIS", 6, 6, &umr_bitfield_default }, + { "REQ_META_MEM_PWR_FORCE", 8, 9, &umr_bitfield_default }, + { "REQ_META_MEM_PWR_DIS", 10, 10, &umr_bitfield_default }, + { "REQ_DPTE_FINE_GRAIN_DIS", 16, 16, &umr_bitfield_default }, + { "REQ_DPTE_FINE_GRAIN_DIS_C", 17, 17, &umr_bitfield_default }, + { "REQ_META_FINE_GRAIN_DIS", 20, 20, &umr_bitfield_default }, + { "REQ_META_FINE_GRAIN_DIS_C", 21, 21, &umr_bitfield_default }, + { "REQ_MPTE_FINE_GRAIN_DIS", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS[] = { + { "REQ_DPTE_MEM_PWR_STATE", 0, 1, &umr_bitfield_default }, + { "REQ_MPTE_MEM_PWR_STATE", 2, 3, &umr_bitfield_default }, + { "REQ_META_MEM_PWR_STATE", 4, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPRET0_HUBPRET_CONTROL[] = { + { "DET_BUF_PLANE1_BASE_ADDRESS", 0, 11, &umr_bitfield_default }, + { "PACK_3TO2_ELEMENT_DISABLE", 12, 12, &umr_bitfield_default }, + { "CROSSBAR_SRC_ALPHA", 16, 17, &umr_bitfield_default }, + { "CROSSBAR_SRC_Y_G", 18, 19, &umr_bitfield_default }, + { "CROSSBAR_SRC_CB_B", 20, 21, &umr_bitfield_default }, + { "CROSSBAR_SRC_CR_R", 22, 23, &umr_bitfield_default }, + { "HUBPRET_CONTROL_SPARE", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPRET0_HUBPRET_MEM_PWR_CTRL[] = { + { "DET_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default }, + { "DET_MEM_PWR_DIS", 2, 2, &umr_bitfield_default }, + { "DET_MEM_PWR_LS_MODE", 4, 5, &umr_bitfield_default }, + { "HUBPRET_MEM_PWR_CTRL_SPARE", 8, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPRET0_HUBPRET_MEM_PWR_STATUS[] = { + { "DET_MEM_PWR_STATE", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPRET0_HUBPRET_READ_LINE_CTRL0[] = { + { "PIPE_READ_LINE_INTERVAL_IN_NONACTIVE", 0, 15, &umr_bitfield_default }, + { "PIPE_READ_LINE_VBLANK_MAXIMUM", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPRET0_HUBPRET_READ_LINE_CTRL1[] = { + { "PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED", 0, 13, &umr_bitfield_default }, + { "HUBPRET_READ_LINE_CTRL1_SPARE", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPRET0_HUBPRET_READ_LINE0[] = { + { "PIPE_READ_LINE0_START", 0, 13, &umr_bitfield_default }, + { "PIPE_READ_LINE0_END", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPRET0_HUBPRET_READ_LINE1[] = { + { "PIPE_READ_LINE1_START", 0, 13, &umr_bitfield_default }, + { "PIPE_READ_LINE1_END", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPRET0_HUBPRET_INTERRUPT[] = { + { "PIPE_VBLANK_INT_MASK", 0, 0, &umr_bitfield_default }, + { "PIPE_READ_LINE0_INT_MASK", 1, 1, &umr_bitfield_default }, + { "PIPE_READ_LINE1_INT_MASK", 2, 2, &umr_bitfield_default }, + { "PIPE_VBLANK_INT_TYPE", 4, 4, &umr_bitfield_default }, + { "PIPE_READ_LINE0_INT_TYPE", 5, 5, &umr_bitfield_default }, + { "PIPE_READ_LINE1_INT_TYPE", 6, 6, &umr_bitfield_default }, + { "PIPE_VBLANK_INT_CLEAR", 8, 8, &umr_bitfield_default }, + { "PIPE_READ_LINE0_INT_CLEAR", 9, 9, &umr_bitfield_default }, + { "PIPE_READ_LINE1_INT_CLEAR", 10, 10, &umr_bitfield_default }, + { "PIPE_VBLANK_STATUS", 12, 12, &umr_bitfield_default }, + { "PIPE_READ_LINE0_STATUS", 13, 13, &umr_bitfield_default }, + { "PIPE_READ_LINE1_STATUS", 14, 14, &umr_bitfield_default }, + { "PIPE_VBLANK_INT_STATUS", 16, 16, &umr_bitfield_default }, + { "PIPE_READ_LINE0_INT_STATUS", 17, 17, &umr_bitfield_default }, + { "PIPE_READ_LINE1_INT_STATUS", 18, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPRET0_HUBPRET_READ_LINE_VALUE[] = { + { "PIPE_READ_LINE", 0, 13, &umr_bitfield_default }, + { "PIPE_READ_LINE_SNAPSHOT", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPRET0_HUBPRET_READ_LINE_STATUS[] = { + { "PIPE_READ_VBLANK", 0, 0, &umr_bitfield_default }, + { "PIPE_READ_LINE0_INSIDE", 4, 4, &umr_bitfield_default }, + { "PIPE_READ_LINE0_OUTSIDE", 5, 5, &umr_bitfield_default }, + { "PIPE_READ_LINE1_INSIDE", 8, 8, &umr_bitfield_default }, + { "PIPE_READ_LINE1_OUTSIDE", 10, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCURSOR0_CURSOR_CONTROL[] = { + { "CURSOR_ENABLE", 0, 0, &umr_bitfield_default }, + { "CURSOR_MODE", 8, 9, &umr_bitfield_default }, + { "CURSOR_SNOOP", 13, 13, &umr_bitfield_default }, + { "CURSOR_SYSTEM", 14, 14, &umr_bitfield_default }, + { "CURSOR_PITCH", 16, 17, &umr_bitfield_default }, + { "CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS", 20, 20, &umr_bitfield_default }, + { "CURSOR_LINES_PER_CHUNK", 24, 28, &umr_bitfield_default }, + { "CURSOR_PERFMON_LATENCY_MEASURE_EN", 30, 30, &umr_bitfield_default }, + { "CURSOR_PERFMON_LATENCY_MEASURE_SEL", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCURSOR0_CURSOR_SURFACE_ADDRESS[] = { + { "CURSOR_SURFACE_ADDRESS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCURSOR0_CURSOR_SURFACE_ADDRESS_HIGH[] = { + { "CURSOR_SURFACE_ADDRESS_HIGH", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCURSOR0_CURSOR_SIZE[] = { + { "CURSOR_HEIGHT", 0, 8, &umr_bitfield_default }, + { "CURSOR_WIDTH", 16, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCURSOR0_CURSOR_POSITION[] = { + { "CURSOR_Y_POSITION", 0, 13, &umr_bitfield_default }, + { "CURSOR_X_POSITION", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCURSOR0_CURSOR_HOT_SPOT[] = { + { "CURSOR_HOT_SPOT_Y", 0, 7, &umr_bitfield_default }, + { "CURSOR_HOT_SPOT_X", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCURSOR0_CURSOR_STEREO_CONTROL[] = { + { "CURSOR_STEREO_EN", 0, 0, &umr_bitfield_default }, + { "CURSOR_PRIMARY_OFFSET", 4, 17, &umr_bitfield_default }, + { "CURSOR_SECONDARY_OFFSET", 18, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCURSOR0_CURSOR_DST_OFFSET[] = { + { "CURSOR_DST_X_OFFSET", 0, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCURSOR0_CURSOR_MEM_PWR_CTRL[] = { + { "CROB_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default }, + { "CROB_MEM_PWR_DIS", 2, 2, &umr_bitfield_default }, + { "CROB_MEM_PWR_LS_MODE", 4, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCURSOR0_CURSOR_MEM_PWR_STATUS[] = { + { "CROB_MEM_PWR_STATE", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON8_PERFCOUNTER_CNTL[] = { + { "PERFCOUNTER_EVENT_SEL", 0, 8, &umr_bitfield_default }, + { "PERFCOUNTER_CVALUE_SEL", 9, 11, &umr_bitfield_default }, + { "PERFCOUNTER_INC_MODE", 12, 14, &umr_bitfield_default }, + { "PERFCOUNTER_HW_CNTL_SEL", 15, 15, &umr_bitfield_default }, + { "PERFCOUNTER_RUNEN_MODE", 16, 16, &umr_bitfield_default }, + { "PERFCOUNTER_CNTOFF_START_DIS", 22, 22, &umr_bitfield_default }, + { "PERFCOUNTER_RESTART_EN", 23, 23, &umr_bitfield_default }, + { "PERFCOUNTER_INT_EN", 24, 24, &umr_bitfield_default }, + { "PERFCOUNTER_OFF_MASK", 25, 25, &umr_bitfield_default }, + { "PERFCOUNTER_ACTIVE", 26, 26, &umr_bitfield_default }, + { "PERFCOUNTER_CNTL_SEL", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON8_PERFCOUNTER_CNTL2[] = { + { "PERFCOUNTER_COUNTED_VALUE_TYPE", 0, 1, &umr_bitfield_default }, + { "PERFCOUNTER_HW_STOP1_SEL", 2, 2, &umr_bitfield_default }, + { "PERFCOUNTER_HW_STOP2_SEL", 3, 3, &umr_bitfield_default }, + { "PERFCOUNTER_CNTOFF_SEL", 8, 13, &umr_bitfield_default }, + { "PERFCOUNTER_CNTL2_SEL", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON8_PERFCOUNTER_STATE[] = { + { "PERFCOUNTER_CNT0_STATE", 0, 1, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL0", 2, 2, &umr_bitfield_default }, + { "PERFCOUNTER_CNT1_STATE", 4, 5, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL1", 6, 6, &umr_bitfield_default }, + { "PERFCOUNTER_CNT2_STATE", 8, 9, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL2", 10, 10, &umr_bitfield_default }, + { "PERFCOUNTER_CNT3_STATE", 12, 13, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL3", 14, 14, &umr_bitfield_default }, + { "PERFCOUNTER_CNT4_STATE", 16, 17, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL4", 18, 18, &umr_bitfield_default }, + { "PERFCOUNTER_CNT5_STATE", 20, 21, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL5", 22, 22, &umr_bitfield_default }, + { "PERFCOUNTER_CNT6_STATE", 24, 25, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL6", 26, 26, &umr_bitfield_default }, + { "PERFCOUNTER_CNT7_STATE", 28, 29, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL7", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON8_PERFMON_CNTL[] = { + { "PERFMON_STATE", 0, 1, &umr_bitfield_default }, + { "PERFMON_RPT_COUNT", 8, 27, &umr_bitfield_default }, + { "PERFMON_CNTOFF_AND_OR", 28, 28, &umr_bitfield_default }, + { "PERFMON_CNTOFF_INT_EN", 29, 29, &umr_bitfield_default }, + { "PERFMON_CNTOFF_INT_STATUS", 30, 30, &umr_bitfield_default }, + { "PERFMON_CNTOFF_INT_ACK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON8_PERFMON_CNTL2[] = { + { "PERFMON_CNTOFF_INT_TYPE", 0, 0, &umr_bitfield_default }, + { "PERFMON_CLK_ENABLE", 1, 1, &umr_bitfield_default }, + { "PERFMON_RUN_ENABLE_START_SEL", 2, 9, &umr_bitfield_default }, + { "PERFMON_RUN_ENABLE_STOP_SEL", 10, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC[] = { + { "PERFCOUNTER_INT0_STATUS", 0, 0, &umr_bitfield_default }, + { "PERFCOUNTER_INT1_STATUS", 1, 1, &umr_bitfield_default }, + { "PERFCOUNTER_INT2_STATUS", 2, 2, &umr_bitfield_default }, + { "PERFCOUNTER_INT3_STATUS", 3, 3, &umr_bitfield_default }, + { "PERFCOUNTER_INT4_STATUS", 4, 4, &umr_bitfield_default }, + { "PERFCOUNTER_INT5_STATUS", 5, 5, &umr_bitfield_default }, + { "PERFCOUNTER_INT6_STATUS", 6, 6, &umr_bitfield_default }, + { "PERFCOUNTER_INT7_STATUS", 7, 7, &umr_bitfield_default }, + { "PERFCOUNTER_INT0_ACK", 8, 8, &umr_bitfield_default }, + { "PERFCOUNTER_INT1_ACK", 9, 9, &umr_bitfield_default }, + { "PERFCOUNTER_INT2_ACK", 10, 10, &umr_bitfield_default }, + { "PERFCOUNTER_INT3_ACK", 11, 11, &umr_bitfield_default }, + { "PERFCOUNTER_INT4_ACK", 12, 12, &umr_bitfield_default }, + { "PERFCOUNTER_INT5_ACK", 13, 13, &umr_bitfield_default }, + { "PERFCOUNTER_INT6_ACK", 14, 14, &umr_bitfield_default }, + { "PERFCOUNTER_INT7_ACK", 15, 15, &umr_bitfield_default }, + { "PERFMON_CVALUE_HI", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON8_PERFMON_CVALUE_LOW[] = { + { "PERFMON_CVALUE_LOW", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON8_PERFMON_HI[] = { + { "PERFMON_HI", 0, 15, &umr_bitfield_default }, + { "PERFMON_READ_SEL", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON8_PERFMON_LOW[] = { + { "PERFMON_LOW", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP1_DCSURF_SURFACE_CONFIG[] = { + { "SURFACE_PIXEL_FORMAT", 0, 6, &umr_bitfield_default }, + { "ROTATION_ANGLE", 8, 9, &umr_bitfield_default }, + { "H_MIRROR_EN", 10, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP1_DCSURF_ADDR_CONFIG[] = { + { "NUM_PIPES", 0, 2, &umr_bitfield_default }, + { "NUM_BANKS", 3, 5, &umr_bitfield_default }, + { "PIPE_INTERLEAVE", 6, 7, &umr_bitfield_default }, + { "NUM_SE", 8, 9, &umr_bitfield_default }, + { "NUM_RB_PER_SE", 10, 11, &umr_bitfield_default }, + { "MAX_COMPRESSED_FRAGS", 12, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP1_DCSURF_TILING_CONFIG[] = { + { "SW_MODE", 0, 4, &umr_bitfield_default }, + { "DIM_TYPE", 7, 8, &umr_bitfield_default }, + { "META_LINEAR", 9, 9, &umr_bitfield_default }, + { "RB_ALIGNED", 10, 10, &umr_bitfield_default }, + { "PIPE_ALIGNED", 11, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP1_DCSURF_PRI_VIEWPORT_START[] = { + { "PRI_VIEWPORT_X_START", 0, 13, &umr_bitfield_default }, + { "PRI_VIEWPORT_Y_START", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION[] = { + { "PRI_VIEWPORT_WIDTH", 0, 13, &umr_bitfield_default }, + { "PRI_VIEWPORT_HEIGHT", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP1_DCSURF_PRI_VIEWPORT_START_C[] = { + { "PRI_VIEWPORT_X_START_C", 0, 13, &umr_bitfield_default }, + { "PRI_VIEWPORT_Y_START_C", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C[] = { + { "PRI_VIEWPORT_WIDTH_C", 0, 13, &umr_bitfield_default }, + { "PRI_VIEWPORT_HEIGHT_C", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP1_DCSURF_SEC_VIEWPORT_START[] = { + { "SEC_VIEWPORT_X_START", 0, 13, &umr_bitfield_default }, + { "SEC_VIEWPORT_Y_START", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION[] = { + { "SEC_VIEWPORT_WIDTH", 0, 13, &umr_bitfield_default }, + { "SEC_VIEWPORT_HEIGHT", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP1_DCSURF_SEC_VIEWPORT_START_C[] = { + { "SEC_VIEWPORT_X_START_C", 0, 13, &umr_bitfield_default }, + { "SEC_VIEWPORT_Y_START_C", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C[] = { + { "SEC_VIEWPORT_WIDTH_C", 0, 13, &umr_bitfield_default }, + { "SEC_VIEWPORT_HEIGHT_C", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP1_DCHUBP_REQ_SIZE_CONFIG[] = { + { "SWATH_HEIGHT", 0, 2, &umr_bitfield_default }, + { "PTE_ROW_HEIGHT_LINEAR", 4, 6, &umr_bitfield_default }, + { "CHUNK_SIZE", 8, 10, &umr_bitfield_default }, + { "MIN_CHUNK_SIZE", 11, 12, &umr_bitfield_default }, + { "META_CHUNK_SIZE", 16, 17, &umr_bitfield_default }, + { "MIN_META_CHUNK_SIZE", 18, 19, &umr_bitfield_default }, + { "DPTE_GROUP_SIZE", 20, 22, &umr_bitfield_default }, + { "MPTE_GROUP_SIZE", 24, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C[] = { + { "SWATH_HEIGHT_C", 0, 2, &umr_bitfield_default }, + { "PTE_ROW_HEIGHT_LINEAR_C", 4, 6, &umr_bitfield_default }, + { "CHUNK_SIZE_C", 8, 10, &umr_bitfield_default }, + { "MIN_CHUNK_SIZE_C", 11, 12, &umr_bitfield_default }, + { "META_CHUNK_SIZE_C", 16, 17, &umr_bitfield_default }, + { "MIN_META_CHUNK_SIZE_C", 18, 19, &umr_bitfield_default }, + { "DPTE_GROUP_SIZE_C", 20, 22, &umr_bitfield_default }, + { "MPTE_GROUP_SIZE_C", 24, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP1_DCHUBP_CNTL[] = { + { "HUBP_BLANK_EN", 0, 0, &umr_bitfield_default }, + { "HUBP_NO_OUTSTANDING_REQ", 1, 1, &umr_bitfield_default }, + { "HUBP_DISABLE", 2, 2, &umr_bitfield_default }, + { "HUBP_IN_BLANK", 3, 3, &umr_bitfield_default }, + { "HUBP_VTG_SEL", 4, 7, &umr_bitfield_default }, + { "HUBP_TTU_DISABLE", 12, 12, &umr_bitfield_default }, + { "HUBP_TTU_MODE", 13, 15, &umr_bitfield_default }, + { "HUBP_UNDERFLOW_STATUS", 28, 30, &umr_bitfield_default }, + { "HUBP_UNDERFLOW_CLEAR", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP1_HUBP_CLK_CNTL[] = { + { "HUBP_CLOCK_ENABLE", 0, 0, &umr_bitfield_default }, + { "HUBP_DISPCLK_R_GATE_DIS", 4, 4, &umr_bitfield_default }, + { "HUBP_DPPCLK_G_GATE_DIS", 8, 8, &umr_bitfield_default }, + { "HUBP_DCFCLK_R_GATE_DIS", 12, 12, &umr_bitfield_default }, + { "HUBP_DCFCLK_G_GATE_DIS", 16, 16, &umr_bitfield_default }, + { "HUBP_DISPCLK_R_CLOCK_ON", 20, 20, &umr_bitfield_default }, + { "HUBP_DPPCLK_G_CLOCK_ON", 21, 21, &umr_bitfield_default }, + { "HUBP_DCFCLK_R_CLOCK_ON", 22, 22, &umr_bitfield_default }, + { "HUBP_DCFCLK_G_CLOCK_ON", 23, 23, &umr_bitfield_default }, + { "HUBP_TEST_CLK_SEL", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP1_DCHUBP_VMPG_CONFIG[] = { + { "VMPG_SIZE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP1_HUBPREQ_DEBUG_DB[] = { + { "HUBPREQ_DEBUG", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK[] = { + { "HUBP_MEASURE_WIN_EN_DCFCLK", 0, 0, &umr_bitfield_default }, + { "HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK", 4, 11, &umr_bitfield_default }, + { "HUBP_PERFMON_START_SEL_DCFCLK", 12, 16, &umr_bitfield_default }, + { "HUBP_PERFMON_STOP_SEL_DCFCLK", 20, 24, &umr_bitfield_default }, + { "HUBP_MEASURE_WIN_MODE_DCFCLK", 28, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK[] = { + { "HUBP_MEASURE_WIN_EN_DPPCLK", 0, 0, &umr_bitfield_default }, + { "HUBP_MEASURE_WIN_SRC_SEL_DPPCLK", 1, 1, &umr_bitfield_default }, + { "HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK", 4, 11, &umr_bitfield_default }, + { "HUBP_PERFMON_START_SEL_DPPCLK", 12, 16, &umr_bitfield_default }, + { "HUBP_PERFMON_STOP_SEL_DPPCLK", 20, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_DCSURF_SURFACE_PITCH[] = { + { "PITCH", 0, 13, &umr_bitfield_default }, + { "META_PITCH", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_DCSURF_SURFACE_PITCH_C[] = { + { "PITCH_C", 0, 13, &umr_bitfield_default }, + { "META_PITCH_C", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS[] = { + { "PRIMARY_SURFACE_ADDRESS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH[] = { + { "PRIMARY_SURFACE_ADDRESS_HIGH", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C[] = { + { "PRIMARY_SURFACE_ADDRESS_C", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C[] = { + { "PRIMARY_SURFACE_ADDRESS_HIGH_C", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS[] = { + { "SECONDARY_SURFACE_ADDRESS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH[] = { + { "SECONDARY_SURFACE_ADDRESS_HIGH", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C[] = { + { "SECONDARY_SURFACE_ADDRESS_C", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C[] = { + { "SECONDARY_SURFACE_ADDRESS_HIGH_C", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS[] = { + { "PRIMARY_META_SURFACE_ADDRESS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH[] = { + { "PRIMARY_META_SURFACE_ADDRESS_HIGH", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C[] = { + { "PRIMARY_META_SURFACE_ADDRESS_C", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C[] = { + { "PRIMARY_META_SURFACE_ADDRESS_HIGH_C", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS[] = { + { "SECONDARY_META_SURFACE_ADDRESS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH[] = { + { "SECONDARY_META_SURFACE_ADDRESS_HIGH", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C[] = { + { "SECONDARY_META_SURFACE_ADDRESS_C", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C[] = { + { "SECONDARY_META_SURFACE_ADDRESS_HIGH_C", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_DCSURF_SURFACE_CONTROL[] = { + { "PRIMARY_SURFACE_DCC_EN", 1, 1, &umr_bitfield_default }, + { "PRIMARY_SURFACE_DCC_IND_64B_BLK", 2, 2, &umr_bitfield_default }, + { "PRIMARY_SURFACE_DCC_IND_64B_BLK_C", 5, 5, &umr_bitfield_default }, + { "SECONDARY_SURFACE_DCC_EN", 9, 9, &umr_bitfield_default }, + { "SECONDARY_SURFACE_DCC_IND_64B_BLK", 10, 10, &umr_bitfield_default }, + { "SECONDARY_SURFACE_DCC_IND_64B_BLK_C", 13, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_DCSURF_FLIP_CONTROL[] = { + { "SURFACE_UPDATE_LOCK", 0, 0, &umr_bitfield_default }, + { "SURFACE_FLIP_TYPE", 1, 1, &umr_bitfield_default }, + { "SURFACE_FLIP_VUPDATE_SKIP_NUM", 4, 7, &umr_bitfield_default }, + { "SURFACE_FLIP_MODE_FOR_STEREOSYNC", 12, 13, &umr_bitfield_default }, + { "SURFACE_FLIP_IN_STEREOSYNC", 16, 16, &umr_bitfield_default }, + { "SURFACE_FLIP_STEREO_SELECT_DISABLE", 17, 17, &umr_bitfield_default }, + { "SURFACE_FLIP_STEREO_SELECT_POLARITY", 18, 18, &umr_bitfield_default }, + { "SURFACE_FLIP_PENDING_DELAY", 20, 29, &umr_bitfield_default }, + { "SURFACE_UPDATE_PENDING", 30, 30, &umr_bitfield_default }, + { "SURFACE_FLIP_PENDING", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_DCSURF_FLIP_CONTROL2[] = { + { "SURFACE_UPDATE_FLIP_PENDING_MIN_TIME", 0, 7, &umr_bitfield_default }, + { "SURFACE_UPDATE_PENDING_HIGH_EXTEND_ENABLE", 12, 12, &umr_bitfield_default }, + { "SURFACE_FLIP_PENDING_HIGH_EXTEND_ENABLE", 13, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_DCSURF_FRAME_PACING_CONTROL[] = { + { "SURFACE_FRAME_PACING_ENABLE", 0, 0, &umr_bitfield_default }, + { "SURFACE_FRAME_PACING_MODE", 1, 1, &umr_bitfield_default }, + { "SURFACE_FRAME_PACING_QUEUE_RESET", 8, 8, &umr_bitfield_default }, + { "SURFACE_FRAME_PACING_QUEUE_FREE_ENTRY", 24, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_DCSURF_FRAME_PACING_TIME[] = { + { "SURFACE_FRAME_PACING_TIME", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT[] = { + { "SURFACE_FLIP_INT_MASK", 0, 0, &umr_bitfield_default }, + { "SURFACE_FLIP_INT_TYPE", 1, 1, &umr_bitfield_default }, + { "SURFACE_FLIP_AWAY_INT_MASK", 2, 2, &umr_bitfield_default }, + { "SURFACE_FLIP_AWAY_INT_TYPE", 3, 3, &umr_bitfield_default }, + { "SURFACE_FLIP_CLEAR", 8, 8, &umr_bitfield_default }, + { "SURFACE_FLIP_AWAY_CLEAR", 9, 9, &umr_bitfield_default }, + { "SURFACE_FLIP_OCCURRED", 16, 16, &umr_bitfield_default }, + { "SURFACE_FLIP_INT_STATUS", 17, 17, &umr_bitfield_default }, + { "SURFACE_FLIP_AWAY_OCCURRED", 18, 18, &umr_bitfield_default }, + { "SURFACE_FLIP_AWAY_INT_STATUS", 19, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_DCSURF_SURFACE_INUSE[] = { + { "SURFACE_INUSE_ADDRESS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH[] = { + { "SURFACE_INUSE_ADDRESS_HIGH", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_DCSURF_SURFACE_INUSE_C[] = { + { "SURFACE_INUSE_ADDRESS_C", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C[] = { + { "SURFACE_INUSE_ADDRESS_HIGH_C", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE[] = { + { "SURFACE_EARLIEST_INUSE_ADDRESS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH[] = { + { "SURFACE_EARLIEST_INUSE_ADDRESS_HIGH", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C[] = { + { "SURFACE_EARLIEST_INUSE_ADDRESS_C", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C[] = { + { "SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_DCN_EXPANSION_MODE[] = { + { "DRQ_EXPANSION_MODE", 0, 1, &umr_bitfield_default }, + { "CRQ_EXPANSION_MODE", 2, 3, &umr_bitfield_default }, + { "MRQ_EXPANSION_MODE", 4, 5, &umr_bitfield_default }, + { "PRQ_EXPANSION_MODE", 6, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_DCN_TTU_QOS_WM[] = { + { "QoS_LEVEL_LOW_WM", 0, 13, &umr_bitfield_default }, + { "QoS_LEVEL_HIGH_WM", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL[] = { + { "MIN_TTU_VBLANK", 0, 23, &umr_bitfield_default }, + { "QoS_LEVEL_FLIP", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_DCN_SURF0_TTU_CNTL0[] = { + { "REFCYC_PER_REQ_DELIVERY", 0, 22, &umr_bitfield_default }, + { "QoS_LEVEL_FIXED", 24, 27, &umr_bitfield_default }, + { "QoS_RAMP_DISABLE", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_DCN_SURF0_TTU_CNTL1[] = { + { "REFCYC_PER_REQ_DELIVERY_PRE", 0, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_DCN_SURF1_TTU_CNTL0[] = { + { "REFCYC_PER_REQ_DELIVERY", 0, 22, &umr_bitfield_default }, + { "QoS_LEVEL_FIXED", 24, 27, &umr_bitfield_default }, + { "QoS_RAMP_DISABLE", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_DCN_SURF1_TTU_CNTL1[] = { + { "REFCYC_PER_REQ_DELIVERY_PRE", 0, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_DCN_CUR0_TTU_CNTL0[] = { + { "REFCYC_PER_REQ_DELIVERY", 0, 22, &umr_bitfield_default }, + { "QoS_LEVEL_FIXED", 24, 27, &umr_bitfield_default }, + { "QoS_RAMP_DISABLE", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_DCN_CUR0_TTU_CNTL1[] = { + { "REFCYC_PER_REQ_DELIVERY_PRE", 0, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB[] = { + { "MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB[] = { + { "MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB[] = { + { "MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB[] = { + { "MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB[] = { + { "MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB[] = { + { "MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB", 0, 3, &umr_bitfield_default }, + { "MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM", 28, 28, &umr_bitfield_default }, + { "MC_VM_SYSTEM_APERTURE_DEFAULT_SNOOP", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB[] = { + { "VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB[] = { + { "VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB", 0, 3, &umr_bitfield_default }, + { "VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM", 28, 28, &umr_bitfield_default }, + { "VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SNOOP", 29, 29, &umr_bitfield_default }, + { "VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_TMZ", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB[] = { + { "VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB[] = { + { "VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB[] = { + { "VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB[] = { + { "VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB[] = { + { "VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB[] = { + { "VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_DCN_VM_CONTEXT0_STATUS[] = { + { "DCN_VM_CONTEXT0_ERROR_STATUS", 0, 15, &umr_bitfield_default }, + { "DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_MSB", 24, 27, &umr_bitfield_default }, + { "DCN_VM_CONTEXT0_ERROR_STATUS_MODE", 30, 30, &umr_bitfield_default }, + { "DCN_VM_CONTEXT0_ERROR_STATUS_CLEAR", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB[] = { + { "DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_DCN_VM_CONTEXT0_CNTL[] = { + { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 3, 3, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 4, 4, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 12, 12, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 13, 13, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL[] = { + { "ENABLE_L1_TLB", 0, 0, &umr_bitfield_default }, + { "SYSTEM_ACCESS_MODE", 3, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_BLANK_OFFSET_0[] = { + { "REFCYC_H_BLANK_END", 0, 12, &umr_bitfield_default }, + { "DLG_V_BLANK_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_BLANK_OFFSET_1[] = { + { "MIN_DST_Y_NEXT_START", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_DST_DIMENSIONS[] = { + { "REFCYC_PER_HTOTAL", 0, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_DST_AFTER_SCALER[] = { + { "REFCYC_X_AFTER_SCALER", 0, 12, &umr_bitfield_default }, + { "DST_Y_AFTER_SCALER", 16, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_PREFETCH_SETTINS[] = { + { "VRATIO_PREFETCH", 0, 20, &umr_bitfield_default }, + { "DST_Y_PREFETCH", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_PREFETCH_SETTINS_C[] = { + { "VRATIO_PREFETCH_C", 0, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_VBLANK_PARAMETERS_0[] = { + { "DST_Y_PER_VM_VBLANK", 0, 4, &umr_bitfield_default }, + { "DST_Y_PER_ROW_VBLANK", 8, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_VBLANK_PARAMETERS_1[] = { + { "REFCYC_PER_PTE_GROUP_VBLANK_L", 0, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_VBLANK_PARAMETERS_2[] = { + { "REFCYC_PER_PTE_GROUP_VBLANK_C", 0, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_VBLANK_PARAMETERS_3[] = { + { "REFCYC_PER_META_CHUNK_VBLANK_L", 0, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_VBLANK_PARAMETERS_4[] = { + { "REFCYC_PER_META_CHUNK_VBLANK_C", 0, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_NOM_PARAMETERS_0[] = { + { "DST_Y_PER_PTE_ROW_NOM_L", 0, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_NOM_PARAMETERS_1[] = { + { "REFCYC_PER_PTE_GROUP_NOM_L", 0, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_NOM_PARAMETERS_2[] = { + { "DST_Y_PER_PTE_ROW_NOM_C", 0, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_NOM_PARAMETERS_3[] = { + { "REFCYC_PER_PTE_GROUP_NOM_C", 0, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_NOM_PARAMETERS_4[] = { + { "DST_Y_PER_META_ROW_NOM_L", 0, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_NOM_PARAMETERS_5[] = { + { "REFCYC_PER_META_CHUNK_NOM_L", 0, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_NOM_PARAMETERS_6[] = { + { "DST_Y_PER_META_ROW_NOM_C", 0, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_NOM_PARAMETERS_7[] = { + { "REFCYC_PER_META_CHUNK_NOM_C", 0, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_PER_LINE_DELIVERY_PRE[] = { + { "REFCYC_PER_LINE_DELIVERY_PRE_L", 0, 12, &umr_bitfield_default }, + { "REFCYC_PER_LINE_DELIVERY_PRE_C", 16, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_PER_LINE_DELIVERY[] = { + { "REFCYC_PER_LINE_DELIVERY_L", 0, 12, &umr_bitfield_default }, + { "REFCYC_PER_LINE_DELIVERY_C", 16, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_CURSOR_SETTINS[] = { + { "CURSOR0_DST_Y_OFFSET", 0, 7, &umr_bitfield_default }, + { "CURSOR0_CHUNK_HDL_ADJUST", 8, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ[] = { + { "REF_FREQ_TO_PIX_FREQ", 0, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL[] = { + { "REQ_DPTE_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default }, + { "REQ_DPTE_MEM_PWR_DIS", 2, 2, &umr_bitfield_default }, + { "REQ_MPTE_MEM_PWR_FORCE", 4, 5, &umr_bitfield_default }, + { "REQ_MPTE_MEM_PWR_DIS", 6, 6, &umr_bitfield_default }, + { "REQ_META_MEM_PWR_FORCE", 8, 9, &umr_bitfield_default }, + { "REQ_META_MEM_PWR_DIS", 10, 10, &umr_bitfield_default }, + { "REQ_DPTE_FINE_GRAIN_DIS", 16, 16, &umr_bitfield_default }, + { "REQ_DPTE_FINE_GRAIN_DIS_C", 17, 17, &umr_bitfield_default }, + { "REQ_META_FINE_GRAIN_DIS", 20, 20, &umr_bitfield_default }, + { "REQ_META_FINE_GRAIN_DIS_C", 21, 21, &umr_bitfield_default }, + { "REQ_MPTE_FINE_GRAIN_DIS", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS[] = { + { "REQ_DPTE_MEM_PWR_STATE", 0, 1, &umr_bitfield_default }, + { "REQ_MPTE_MEM_PWR_STATE", 2, 3, &umr_bitfield_default }, + { "REQ_META_MEM_PWR_STATE", 4, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPRET1_HUBPRET_CONTROL[] = { + { "DET_BUF_PLANE1_BASE_ADDRESS", 0, 11, &umr_bitfield_default }, + { "PACK_3TO2_ELEMENT_DISABLE", 12, 12, &umr_bitfield_default }, + { "CROSSBAR_SRC_ALPHA", 16, 17, &umr_bitfield_default }, + { "CROSSBAR_SRC_Y_G", 18, 19, &umr_bitfield_default }, + { "CROSSBAR_SRC_CB_B", 20, 21, &umr_bitfield_default }, + { "CROSSBAR_SRC_CR_R", 22, 23, &umr_bitfield_default }, + { "HUBPRET_CONTROL_SPARE", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPRET1_HUBPRET_MEM_PWR_CTRL[] = { + { "DET_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default }, + { "DET_MEM_PWR_DIS", 2, 2, &umr_bitfield_default }, + { "DET_MEM_PWR_LS_MODE", 4, 5, &umr_bitfield_default }, + { "HUBPRET_MEM_PWR_CTRL_SPARE", 8, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPRET1_HUBPRET_MEM_PWR_STATUS[] = { + { "DET_MEM_PWR_STATE", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPRET1_HUBPRET_READ_LINE_CTRL0[] = { + { "PIPE_READ_LINE_INTERVAL_IN_NONACTIVE", 0, 15, &umr_bitfield_default }, + { "PIPE_READ_LINE_VBLANK_MAXIMUM", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPRET1_HUBPRET_READ_LINE_CTRL1[] = { + { "PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED", 0, 13, &umr_bitfield_default }, + { "HUBPRET_READ_LINE_CTRL1_SPARE", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPRET1_HUBPRET_READ_LINE0[] = { + { "PIPE_READ_LINE0_START", 0, 13, &umr_bitfield_default }, + { "PIPE_READ_LINE0_END", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPRET1_HUBPRET_READ_LINE1[] = { + { "PIPE_READ_LINE1_START", 0, 13, &umr_bitfield_default }, + { "PIPE_READ_LINE1_END", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPRET1_HUBPRET_INTERRUPT[] = { + { "PIPE_VBLANK_INT_MASK", 0, 0, &umr_bitfield_default }, + { "PIPE_READ_LINE0_INT_MASK", 1, 1, &umr_bitfield_default }, + { "PIPE_READ_LINE1_INT_MASK", 2, 2, &umr_bitfield_default }, + { "PIPE_VBLANK_INT_TYPE", 4, 4, &umr_bitfield_default }, + { "PIPE_READ_LINE0_INT_TYPE", 5, 5, &umr_bitfield_default }, + { "PIPE_READ_LINE1_INT_TYPE", 6, 6, &umr_bitfield_default }, + { "PIPE_VBLANK_INT_CLEAR", 8, 8, &umr_bitfield_default }, + { "PIPE_READ_LINE0_INT_CLEAR", 9, 9, &umr_bitfield_default }, + { "PIPE_READ_LINE1_INT_CLEAR", 10, 10, &umr_bitfield_default }, + { "PIPE_VBLANK_STATUS", 12, 12, &umr_bitfield_default }, + { "PIPE_READ_LINE0_STATUS", 13, 13, &umr_bitfield_default }, + { "PIPE_READ_LINE1_STATUS", 14, 14, &umr_bitfield_default }, + { "PIPE_VBLANK_INT_STATUS", 16, 16, &umr_bitfield_default }, + { "PIPE_READ_LINE0_INT_STATUS", 17, 17, &umr_bitfield_default }, + { "PIPE_READ_LINE1_INT_STATUS", 18, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPRET1_HUBPRET_READ_LINE_VALUE[] = { + { "PIPE_READ_LINE", 0, 13, &umr_bitfield_default }, + { "PIPE_READ_LINE_SNAPSHOT", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPRET1_HUBPRET_READ_LINE_STATUS[] = { + { "PIPE_READ_VBLANK", 0, 0, &umr_bitfield_default }, + { "PIPE_READ_LINE0_INSIDE", 4, 4, &umr_bitfield_default }, + { "PIPE_READ_LINE0_OUTSIDE", 5, 5, &umr_bitfield_default }, + { "PIPE_READ_LINE1_INSIDE", 8, 8, &umr_bitfield_default }, + { "PIPE_READ_LINE1_OUTSIDE", 10, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCURSOR1_CURSOR_CONTROL[] = { + { "CURSOR_ENABLE", 0, 0, &umr_bitfield_default }, + { "CURSOR_MODE", 8, 9, &umr_bitfield_default }, + { "CURSOR_SNOOP", 13, 13, &umr_bitfield_default }, + { "CURSOR_SYSTEM", 14, 14, &umr_bitfield_default }, + { "CURSOR_PITCH", 16, 17, &umr_bitfield_default }, + { "CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS", 20, 20, &umr_bitfield_default }, + { "CURSOR_LINES_PER_CHUNK", 24, 28, &umr_bitfield_default }, + { "CURSOR_PERFMON_LATENCY_MEASURE_EN", 30, 30, &umr_bitfield_default }, + { "CURSOR_PERFMON_LATENCY_MEASURE_SEL", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCURSOR1_CURSOR_SURFACE_ADDRESS[] = { + { "CURSOR_SURFACE_ADDRESS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCURSOR1_CURSOR_SURFACE_ADDRESS_HIGH[] = { + { "CURSOR_SURFACE_ADDRESS_HIGH", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCURSOR1_CURSOR_SIZE[] = { + { "CURSOR_HEIGHT", 0, 8, &umr_bitfield_default }, + { "CURSOR_WIDTH", 16, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCURSOR1_CURSOR_POSITION[] = { + { "CURSOR_Y_POSITION", 0, 13, &umr_bitfield_default }, + { "CURSOR_X_POSITION", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCURSOR1_CURSOR_HOT_SPOT[] = { + { "CURSOR_HOT_SPOT_Y", 0, 7, &umr_bitfield_default }, + { "CURSOR_HOT_SPOT_X", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCURSOR1_CURSOR_STEREO_CONTROL[] = { + { "CURSOR_STEREO_EN", 0, 0, &umr_bitfield_default }, + { "CURSOR_PRIMARY_OFFSET", 4, 17, &umr_bitfield_default }, + { "CURSOR_SECONDARY_OFFSET", 18, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCURSOR1_CURSOR_DST_OFFSET[] = { + { "CURSOR_DST_X_OFFSET", 0, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCURSOR1_CURSOR_MEM_PWR_CTRL[] = { + { "CROB_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default }, + { "CROB_MEM_PWR_DIS", 2, 2, &umr_bitfield_default }, + { "CROB_MEM_PWR_LS_MODE", 4, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCURSOR1_CURSOR_MEM_PWR_STATUS[] = { + { "CROB_MEM_PWR_STATE", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON9_PERFCOUNTER_CNTL[] = { + { "PERFCOUNTER_EVENT_SEL", 0, 8, &umr_bitfield_default }, + { "PERFCOUNTER_CVALUE_SEL", 9, 11, &umr_bitfield_default }, + { "PERFCOUNTER_INC_MODE", 12, 14, &umr_bitfield_default }, + { "PERFCOUNTER_HW_CNTL_SEL", 15, 15, &umr_bitfield_default }, + { "PERFCOUNTER_RUNEN_MODE", 16, 16, &umr_bitfield_default }, + { "PERFCOUNTER_CNTOFF_START_DIS", 22, 22, &umr_bitfield_default }, + { "PERFCOUNTER_RESTART_EN", 23, 23, &umr_bitfield_default }, + { "PERFCOUNTER_INT_EN", 24, 24, &umr_bitfield_default }, + { "PERFCOUNTER_OFF_MASK", 25, 25, &umr_bitfield_default }, + { "PERFCOUNTER_ACTIVE", 26, 26, &umr_bitfield_default }, + { "PERFCOUNTER_CNTL_SEL", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON9_PERFCOUNTER_CNTL2[] = { + { "PERFCOUNTER_COUNTED_VALUE_TYPE", 0, 1, &umr_bitfield_default }, + { "PERFCOUNTER_HW_STOP1_SEL", 2, 2, &umr_bitfield_default }, + { "PERFCOUNTER_HW_STOP2_SEL", 3, 3, &umr_bitfield_default }, + { "PERFCOUNTER_CNTOFF_SEL", 8, 13, &umr_bitfield_default }, + { "PERFCOUNTER_CNTL2_SEL", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON9_PERFCOUNTER_STATE[] = { + { "PERFCOUNTER_CNT0_STATE", 0, 1, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL0", 2, 2, &umr_bitfield_default }, + { "PERFCOUNTER_CNT1_STATE", 4, 5, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL1", 6, 6, &umr_bitfield_default }, + { "PERFCOUNTER_CNT2_STATE", 8, 9, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL2", 10, 10, &umr_bitfield_default }, + { "PERFCOUNTER_CNT3_STATE", 12, 13, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL3", 14, 14, &umr_bitfield_default }, + { "PERFCOUNTER_CNT4_STATE", 16, 17, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL4", 18, 18, &umr_bitfield_default }, + { "PERFCOUNTER_CNT5_STATE", 20, 21, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL5", 22, 22, &umr_bitfield_default }, + { "PERFCOUNTER_CNT6_STATE", 24, 25, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL6", 26, 26, &umr_bitfield_default }, + { "PERFCOUNTER_CNT7_STATE", 28, 29, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL7", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON9_PERFMON_CNTL[] = { + { "PERFMON_STATE", 0, 1, &umr_bitfield_default }, + { "PERFMON_RPT_COUNT", 8, 27, &umr_bitfield_default }, + { "PERFMON_CNTOFF_AND_OR", 28, 28, &umr_bitfield_default }, + { "PERFMON_CNTOFF_INT_EN", 29, 29, &umr_bitfield_default }, + { "PERFMON_CNTOFF_INT_STATUS", 30, 30, &umr_bitfield_default }, + { "PERFMON_CNTOFF_INT_ACK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON9_PERFMON_CNTL2[] = { + { "PERFMON_CNTOFF_INT_TYPE", 0, 0, &umr_bitfield_default }, + { "PERFMON_CLK_ENABLE", 1, 1, &umr_bitfield_default }, + { "PERFMON_RUN_ENABLE_START_SEL", 2, 9, &umr_bitfield_default }, + { "PERFMON_RUN_ENABLE_STOP_SEL", 10, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC[] = { + { "PERFCOUNTER_INT0_STATUS", 0, 0, &umr_bitfield_default }, + { "PERFCOUNTER_INT1_STATUS", 1, 1, &umr_bitfield_default }, + { "PERFCOUNTER_INT2_STATUS", 2, 2, &umr_bitfield_default }, + { "PERFCOUNTER_INT3_STATUS", 3, 3, &umr_bitfield_default }, + { "PERFCOUNTER_INT4_STATUS", 4, 4, &umr_bitfield_default }, + { "PERFCOUNTER_INT5_STATUS", 5, 5, &umr_bitfield_default }, + { "PERFCOUNTER_INT6_STATUS", 6, 6, &umr_bitfield_default }, + { "PERFCOUNTER_INT7_STATUS", 7, 7, &umr_bitfield_default }, + { "PERFCOUNTER_INT0_ACK", 8, 8, &umr_bitfield_default }, + { "PERFCOUNTER_INT1_ACK", 9, 9, &umr_bitfield_default }, + { "PERFCOUNTER_INT2_ACK", 10, 10, &umr_bitfield_default }, + { "PERFCOUNTER_INT3_ACK", 11, 11, &umr_bitfield_default }, + { "PERFCOUNTER_INT4_ACK", 12, 12, &umr_bitfield_default }, + { "PERFCOUNTER_INT5_ACK", 13, 13, &umr_bitfield_default }, + { "PERFCOUNTER_INT6_ACK", 14, 14, &umr_bitfield_default }, + { "PERFCOUNTER_INT7_ACK", 15, 15, &umr_bitfield_default }, + { "PERFMON_CVALUE_HI", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON9_PERFMON_CVALUE_LOW[] = { + { "PERFMON_CVALUE_LOW", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON9_PERFMON_HI[] = { + { "PERFMON_HI", 0, 15, &umr_bitfield_default }, + { "PERFMON_READ_SEL", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON9_PERFMON_LOW[] = { + { "PERFMON_LOW", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP2_DCSURF_SURFACE_CONFIG[] = { + { "SURFACE_PIXEL_FORMAT", 0, 6, &umr_bitfield_default }, + { "ROTATION_ANGLE", 8, 9, &umr_bitfield_default }, + { "H_MIRROR_EN", 10, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP2_DCSURF_ADDR_CONFIG[] = { + { "NUM_PIPES", 0, 2, &umr_bitfield_default }, + { "NUM_BANKS", 3, 5, &umr_bitfield_default }, + { "PIPE_INTERLEAVE", 6, 7, &umr_bitfield_default }, + { "NUM_SE", 8, 9, &umr_bitfield_default }, + { "NUM_RB_PER_SE", 10, 11, &umr_bitfield_default }, + { "MAX_COMPRESSED_FRAGS", 12, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP2_DCSURF_TILING_CONFIG[] = { + { "SW_MODE", 0, 4, &umr_bitfield_default }, + { "DIM_TYPE", 7, 8, &umr_bitfield_default }, + { "META_LINEAR", 9, 9, &umr_bitfield_default }, + { "RB_ALIGNED", 10, 10, &umr_bitfield_default }, + { "PIPE_ALIGNED", 11, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP2_DCSURF_PRI_VIEWPORT_START[] = { + { "PRI_VIEWPORT_X_START", 0, 13, &umr_bitfield_default }, + { "PRI_VIEWPORT_Y_START", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION[] = { + { "PRI_VIEWPORT_WIDTH", 0, 13, &umr_bitfield_default }, + { "PRI_VIEWPORT_HEIGHT", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP2_DCSURF_PRI_VIEWPORT_START_C[] = { + { "PRI_VIEWPORT_X_START_C", 0, 13, &umr_bitfield_default }, + { "PRI_VIEWPORT_Y_START_C", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C[] = { + { "PRI_VIEWPORT_WIDTH_C", 0, 13, &umr_bitfield_default }, + { "PRI_VIEWPORT_HEIGHT_C", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP2_DCSURF_SEC_VIEWPORT_START[] = { + { "SEC_VIEWPORT_X_START", 0, 13, &umr_bitfield_default }, + { "SEC_VIEWPORT_Y_START", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION[] = { + { "SEC_VIEWPORT_WIDTH", 0, 13, &umr_bitfield_default }, + { "SEC_VIEWPORT_HEIGHT", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP2_DCSURF_SEC_VIEWPORT_START_C[] = { + { "SEC_VIEWPORT_X_START_C", 0, 13, &umr_bitfield_default }, + { "SEC_VIEWPORT_Y_START_C", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C[] = { + { "SEC_VIEWPORT_WIDTH_C", 0, 13, &umr_bitfield_default }, + { "SEC_VIEWPORT_HEIGHT_C", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP2_DCHUBP_REQ_SIZE_CONFIG[] = { + { "SWATH_HEIGHT", 0, 2, &umr_bitfield_default }, + { "PTE_ROW_HEIGHT_LINEAR", 4, 6, &umr_bitfield_default }, + { "CHUNK_SIZE", 8, 10, &umr_bitfield_default }, + { "MIN_CHUNK_SIZE", 11, 12, &umr_bitfield_default }, + { "META_CHUNK_SIZE", 16, 17, &umr_bitfield_default }, + { "MIN_META_CHUNK_SIZE", 18, 19, &umr_bitfield_default }, + { "DPTE_GROUP_SIZE", 20, 22, &umr_bitfield_default }, + { "MPTE_GROUP_SIZE", 24, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_C[] = { + { "SWATH_HEIGHT_C", 0, 2, &umr_bitfield_default }, + { "PTE_ROW_HEIGHT_LINEAR_C", 4, 6, &umr_bitfield_default }, + { "CHUNK_SIZE_C", 8, 10, &umr_bitfield_default }, + { "MIN_CHUNK_SIZE_C", 11, 12, &umr_bitfield_default }, + { "META_CHUNK_SIZE_C", 16, 17, &umr_bitfield_default }, + { "MIN_META_CHUNK_SIZE_C", 18, 19, &umr_bitfield_default }, + { "DPTE_GROUP_SIZE_C", 20, 22, &umr_bitfield_default }, + { "MPTE_GROUP_SIZE_C", 24, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP2_DCHUBP_CNTL[] = { + { "HUBP_BLANK_EN", 0, 0, &umr_bitfield_default }, + { "HUBP_NO_OUTSTANDING_REQ", 1, 1, &umr_bitfield_default }, + { "HUBP_DISABLE", 2, 2, &umr_bitfield_default }, + { "HUBP_IN_BLANK", 3, 3, &umr_bitfield_default }, + { "HUBP_VTG_SEL", 4, 7, &umr_bitfield_default }, + { "HUBP_TTU_DISABLE", 12, 12, &umr_bitfield_default }, + { "HUBP_TTU_MODE", 13, 15, &umr_bitfield_default }, + { "HUBP_UNDERFLOW_STATUS", 28, 30, &umr_bitfield_default }, + { "HUBP_UNDERFLOW_CLEAR", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP2_HUBP_CLK_CNTL[] = { + { "HUBP_CLOCK_ENABLE", 0, 0, &umr_bitfield_default }, + { "HUBP_DISPCLK_R_GATE_DIS", 4, 4, &umr_bitfield_default }, + { "HUBP_DPPCLK_G_GATE_DIS", 8, 8, &umr_bitfield_default }, + { "HUBP_DCFCLK_R_GATE_DIS", 12, 12, &umr_bitfield_default }, + { "HUBP_DCFCLK_G_GATE_DIS", 16, 16, &umr_bitfield_default }, + { "HUBP_DISPCLK_R_CLOCK_ON", 20, 20, &umr_bitfield_default }, + { "HUBP_DPPCLK_G_CLOCK_ON", 21, 21, &umr_bitfield_default }, + { "HUBP_DCFCLK_R_CLOCK_ON", 22, 22, &umr_bitfield_default }, + { "HUBP_DCFCLK_G_CLOCK_ON", 23, 23, &umr_bitfield_default }, + { "HUBP_TEST_CLK_SEL", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP2_DCHUBP_VMPG_CONFIG[] = { + { "VMPG_SIZE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP2_HUBPREQ_DEBUG_DB[] = { + { "HUBPREQ_DEBUG", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK[] = { + { "HUBP_MEASURE_WIN_EN_DCFCLK", 0, 0, &umr_bitfield_default }, + { "HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK", 4, 11, &umr_bitfield_default }, + { "HUBP_PERFMON_START_SEL_DCFCLK", 12, 16, &umr_bitfield_default }, + { "HUBP_PERFMON_STOP_SEL_DCFCLK", 20, 24, &umr_bitfield_default }, + { "HUBP_MEASURE_WIN_MODE_DCFCLK", 28, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK[] = { + { "HUBP_MEASURE_WIN_EN_DPPCLK", 0, 0, &umr_bitfield_default }, + { "HUBP_MEASURE_WIN_SRC_SEL_DPPCLK", 1, 1, &umr_bitfield_default }, + { "HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK", 4, 11, &umr_bitfield_default }, + { "HUBP_PERFMON_START_SEL_DPPCLK", 12, 16, &umr_bitfield_default }, + { "HUBP_PERFMON_STOP_SEL_DPPCLK", 20, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_DCSURF_SURFACE_PITCH[] = { + { "PITCH", 0, 13, &umr_bitfield_default }, + { "META_PITCH", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_DCSURF_SURFACE_PITCH_C[] = { + { "PITCH_C", 0, 13, &umr_bitfield_default }, + { "META_PITCH_C", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS[] = { + { "PRIMARY_SURFACE_ADDRESS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH[] = { + { "PRIMARY_SURFACE_ADDRESS_HIGH", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C[] = { + { "PRIMARY_SURFACE_ADDRESS_C", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C[] = { + { "PRIMARY_SURFACE_ADDRESS_HIGH_C", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS[] = { + { "SECONDARY_SURFACE_ADDRESS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH[] = { + { "SECONDARY_SURFACE_ADDRESS_HIGH", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C[] = { + { "SECONDARY_SURFACE_ADDRESS_C", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C[] = { + { "SECONDARY_SURFACE_ADDRESS_HIGH_C", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS[] = { + { "PRIMARY_META_SURFACE_ADDRESS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH[] = { + { "PRIMARY_META_SURFACE_ADDRESS_HIGH", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C[] = { + { "PRIMARY_META_SURFACE_ADDRESS_C", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C[] = { + { "PRIMARY_META_SURFACE_ADDRESS_HIGH_C", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS[] = { + { "SECONDARY_META_SURFACE_ADDRESS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH[] = { + { "SECONDARY_META_SURFACE_ADDRESS_HIGH", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C[] = { + { "SECONDARY_META_SURFACE_ADDRESS_C", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C[] = { + { "SECONDARY_META_SURFACE_ADDRESS_HIGH_C", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_DCSURF_SURFACE_CONTROL[] = { + { "PRIMARY_SURFACE_DCC_EN", 1, 1, &umr_bitfield_default }, + { "PRIMARY_SURFACE_DCC_IND_64B_BLK", 2, 2, &umr_bitfield_default }, + { "PRIMARY_SURFACE_DCC_IND_64B_BLK_C", 5, 5, &umr_bitfield_default }, + { "SECONDARY_SURFACE_DCC_EN", 9, 9, &umr_bitfield_default }, + { "SECONDARY_SURFACE_DCC_IND_64B_BLK", 10, 10, &umr_bitfield_default }, + { "SECONDARY_SURFACE_DCC_IND_64B_BLK_C", 13, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_DCSURF_FLIP_CONTROL[] = { + { "SURFACE_UPDATE_LOCK", 0, 0, &umr_bitfield_default }, + { "SURFACE_FLIP_TYPE", 1, 1, &umr_bitfield_default }, + { "SURFACE_FLIP_VUPDATE_SKIP_NUM", 4, 7, &umr_bitfield_default }, + { "SURFACE_FLIP_MODE_FOR_STEREOSYNC", 12, 13, &umr_bitfield_default }, + { "SURFACE_FLIP_IN_STEREOSYNC", 16, 16, &umr_bitfield_default }, + { "SURFACE_FLIP_STEREO_SELECT_DISABLE", 17, 17, &umr_bitfield_default }, + { "SURFACE_FLIP_STEREO_SELECT_POLARITY", 18, 18, &umr_bitfield_default }, + { "SURFACE_FLIP_PENDING_DELAY", 20, 29, &umr_bitfield_default }, + { "SURFACE_UPDATE_PENDING", 30, 30, &umr_bitfield_default }, + { "SURFACE_FLIP_PENDING", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_DCSURF_FLIP_CONTROL2[] = { + { "SURFACE_UPDATE_FLIP_PENDING_MIN_TIME", 0, 7, &umr_bitfield_default }, + { "SURFACE_UPDATE_PENDING_HIGH_EXTEND_ENABLE", 12, 12, &umr_bitfield_default }, + { "SURFACE_FLIP_PENDING_HIGH_EXTEND_ENABLE", 13, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_DCSURF_FRAME_PACING_CONTROL[] = { + { "SURFACE_FRAME_PACING_ENABLE", 0, 0, &umr_bitfield_default }, + { "SURFACE_FRAME_PACING_MODE", 1, 1, &umr_bitfield_default }, + { "SURFACE_FRAME_PACING_QUEUE_RESET", 8, 8, &umr_bitfield_default }, + { "SURFACE_FRAME_PACING_QUEUE_FREE_ENTRY", 24, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_DCSURF_FRAME_PACING_TIME[] = { + { "SURFACE_FRAME_PACING_TIME", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT[] = { + { "SURFACE_FLIP_INT_MASK", 0, 0, &umr_bitfield_default }, + { "SURFACE_FLIP_INT_TYPE", 1, 1, &umr_bitfield_default }, + { "SURFACE_FLIP_AWAY_INT_MASK", 2, 2, &umr_bitfield_default }, + { "SURFACE_FLIP_AWAY_INT_TYPE", 3, 3, &umr_bitfield_default }, + { "SURFACE_FLIP_CLEAR", 8, 8, &umr_bitfield_default }, + { "SURFACE_FLIP_AWAY_CLEAR", 9, 9, &umr_bitfield_default }, + { "SURFACE_FLIP_OCCURRED", 16, 16, &umr_bitfield_default }, + { "SURFACE_FLIP_INT_STATUS", 17, 17, &umr_bitfield_default }, + { "SURFACE_FLIP_AWAY_OCCURRED", 18, 18, &umr_bitfield_default }, + { "SURFACE_FLIP_AWAY_INT_STATUS", 19, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_DCSURF_SURFACE_INUSE[] = { + { "SURFACE_INUSE_ADDRESS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH[] = { + { "SURFACE_INUSE_ADDRESS_HIGH", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_DCSURF_SURFACE_INUSE_C[] = { + { "SURFACE_INUSE_ADDRESS_C", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C[] = { + { "SURFACE_INUSE_ADDRESS_HIGH_C", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE[] = { + { "SURFACE_EARLIEST_INUSE_ADDRESS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH[] = { + { "SURFACE_EARLIEST_INUSE_ADDRESS_HIGH", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C[] = { + { "SURFACE_EARLIEST_INUSE_ADDRESS_C", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C[] = { + { "SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_DCN_EXPANSION_MODE[] = { + { "DRQ_EXPANSION_MODE", 0, 1, &umr_bitfield_default }, + { "CRQ_EXPANSION_MODE", 2, 3, &umr_bitfield_default }, + { "MRQ_EXPANSION_MODE", 4, 5, &umr_bitfield_default }, + { "PRQ_EXPANSION_MODE", 6, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_DCN_TTU_QOS_WM[] = { + { "QoS_LEVEL_LOW_WM", 0, 13, &umr_bitfield_default }, + { "QoS_LEVEL_HIGH_WM", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_DCN_GLOBAL_TTU_CNTL[] = { + { "MIN_TTU_VBLANK", 0, 23, &umr_bitfield_default }, + { "QoS_LEVEL_FLIP", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_DCN_SURF0_TTU_CNTL0[] = { + { "REFCYC_PER_REQ_DELIVERY", 0, 22, &umr_bitfield_default }, + { "QoS_LEVEL_FIXED", 24, 27, &umr_bitfield_default }, + { "QoS_RAMP_DISABLE", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_DCN_SURF0_TTU_CNTL1[] = { + { "REFCYC_PER_REQ_DELIVERY_PRE", 0, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_DCN_SURF1_TTU_CNTL0[] = { + { "REFCYC_PER_REQ_DELIVERY", 0, 22, &umr_bitfield_default }, + { "QoS_LEVEL_FIXED", 24, 27, &umr_bitfield_default }, + { "QoS_RAMP_DISABLE", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_DCN_SURF1_TTU_CNTL1[] = { + { "REFCYC_PER_REQ_DELIVERY_PRE", 0, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_DCN_CUR0_TTU_CNTL0[] = { + { "REFCYC_PER_REQ_DELIVERY", 0, 22, &umr_bitfield_default }, + { "QoS_LEVEL_FIXED", 24, 27, &umr_bitfield_default }, + { "QoS_RAMP_DISABLE", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_DCN_CUR0_TTU_CNTL1[] = { + { "REFCYC_PER_REQ_DELIVERY_PRE", 0, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB[] = { + { "MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB[] = { + { "MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB[] = { + { "MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB[] = { + { "MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB[] = { + { "MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB[] = { + { "MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB", 0, 3, &umr_bitfield_default }, + { "MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM", 28, 28, &umr_bitfield_default }, + { "MC_VM_SYSTEM_APERTURE_DEFAULT_SNOOP", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB[] = { + { "VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB[] = { + { "VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB", 0, 3, &umr_bitfield_default }, + { "VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM", 28, 28, &umr_bitfield_default }, + { "VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SNOOP", 29, 29, &umr_bitfield_default }, + { "VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_TMZ", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB[] = { + { "VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB[] = { + { "VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB[] = { + { "VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB[] = { + { "VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB[] = { + { "VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB[] = { + { "VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_DCN_VM_CONTEXT0_STATUS[] = { + { "DCN_VM_CONTEXT0_ERROR_STATUS", 0, 15, &umr_bitfield_default }, + { "DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_MSB", 24, 27, &umr_bitfield_default }, + { "DCN_VM_CONTEXT0_ERROR_STATUS_MODE", 30, 30, &umr_bitfield_default }, + { "DCN_VM_CONTEXT0_ERROR_STATUS_CLEAR", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB[] = { + { "DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_DCN_VM_CONTEXT0_CNTL[] = { + { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 3, 3, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 4, 4, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 12, 12, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 13, 13, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL[] = { + { "ENABLE_L1_TLB", 0, 0, &umr_bitfield_default }, + { "SYSTEM_ACCESS_MODE", 3, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_BLANK_OFFSET_0[] = { + { "REFCYC_H_BLANK_END", 0, 12, &umr_bitfield_default }, + { "DLG_V_BLANK_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_BLANK_OFFSET_1[] = { + { "MIN_DST_Y_NEXT_START", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_DST_DIMENSIONS[] = { + { "REFCYC_PER_HTOTAL", 0, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_DST_AFTER_SCALER[] = { + { "REFCYC_X_AFTER_SCALER", 0, 12, &umr_bitfield_default }, + { "DST_Y_AFTER_SCALER", 16, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_PREFETCH_SETTINS[] = { + { "VRATIO_PREFETCH", 0, 20, &umr_bitfield_default }, + { "DST_Y_PREFETCH", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_PREFETCH_SETTINS_C[] = { + { "VRATIO_PREFETCH_C", 0, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_VBLANK_PARAMETERS_0[] = { + { "DST_Y_PER_VM_VBLANK", 0, 4, &umr_bitfield_default }, + { "DST_Y_PER_ROW_VBLANK", 8, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_VBLANK_PARAMETERS_1[] = { + { "REFCYC_PER_PTE_GROUP_VBLANK_L", 0, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_VBLANK_PARAMETERS_2[] = { + { "REFCYC_PER_PTE_GROUP_VBLANK_C", 0, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_VBLANK_PARAMETERS_3[] = { + { "REFCYC_PER_META_CHUNK_VBLANK_L", 0, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_VBLANK_PARAMETERS_4[] = { + { "REFCYC_PER_META_CHUNK_VBLANK_C", 0, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_NOM_PARAMETERS_0[] = { + { "DST_Y_PER_PTE_ROW_NOM_L", 0, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_NOM_PARAMETERS_1[] = { + { "REFCYC_PER_PTE_GROUP_NOM_L", 0, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_NOM_PARAMETERS_2[] = { + { "DST_Y_PER_PTE_ROW_NOM_C", 0, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_NOM_PARAMETERS_3[] = { + { "REFCYC_PER_PTE_GROUP_NOM_C", 0, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_NOM_PARAMETERS_4[] = { + { "DST_Y_PER_META_ROW_NOM_L", 0, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_NOM_PARAMETERS_5[] = { + { "REFCYC_PER_META_CHUNK_NOM_L", 0, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_NOM_PARAMETERS_6[] = { + { "DST_Y_PER_META_ROW_NOM_C", 0, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_NOM_PARAMETERS_7[] = { + { "REFCYC_PER_META_CHUNK_NOM_C", 0, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_PER_LINE_DELIVERY_PRE[] = { + { "REFCYC_PER_LINE_DELIVERY_PRE_L", 0, 12, &umr_bitfield_default }, + { "REFCYC_PER_LINE_DELIVERY_PRE_C", 16, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_PER_LINE_DELIVERY[] = { + { "REFCYC_PER_LINE_DELIVERY_L", 0, 12, &umr_bitfield_default }, + { "REFCYC_PER_LINE_DELIVERY_C", 16, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_CURSOR_SETTINS[] = { + { "CURSOR0_DST_Y_OFFSET", 0, 7, &umr_bitfield_default }, + { "CURSOR0_CHUNK_HDL_ADJUST", 8, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_REF_FREQ_TO_PIX_FREQ[] = { + { "REF_FREQ_TO_PIX_FREQ", 0, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_HUBPREQ_MEM_PWR_CTRL[] = { + { "REQ_DPTE_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default }, + { "REQ_DPTE_MEM_PWR_DIS", 2, 2, &umr_bitfield_default }, + { "REQ_MPTE_MEM_PWR_FORCE", 4, 5, &umr_bitfield_default }, + { "REQ_MPTE_MEM_PWR_DIS", 6, 6, &umr_bitfield_default }, + { "REQ_META_MEM_PWR_FORCE", 8, 9, &umr_bitfield_default }, + { "REQ_META_MEM_PWR_DIS", 10, 10, &umr_bitfield_default }, + { "REQ_DPTE_FINE_GRAIN_DIS", 16, 16, &umr_bitfield_default }, + { "REQ_DPTE_FINE_GRAIN_DIS_C", 17, 17, &umr_bitfield_default }, + { "REQ_META_FINE_GRAIN_DIS", 20, 20, &umr_bitfield_default }, + { "REQ_META_FINE_GRAIN_DIS_C", 21, 21, &umr_bitfield_default }, + { "REQ_MPTE_FINE_GRAIN_DIS", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ2_HUBPREQ_MEM_PWR_STATUS[] = { + { "REQ_DPTE_MEM_PWR_STATE", 0, 1, &umr_bitfield_default }, + { "REQ_MPTE_MEM_PWR_STATE", 2, 3, &umr_bitfield_default }, + { "REQ_META_MEM_PWR_STATE", 4, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPRET2_HUBPRET_CONTROL[] = { + { "DET_BUF_PLANE1_BASE_ADDRESS", 0, 11, &umr_bitfield_default }, + { "PACK_3TO2_ELEMENT_DISABLE", 12, 12, &umr_bitfield_default }, + { "CROSSBAR_SRC_ALPHA", 16, 17, &umr_bitfield_default }, + { "CROSSBAR_SRC_Y_G", 18, 19, &umr_bitfield_default }, + { "CROSSBAR_SRC_CB_B", 20, 21, &umr_bitfield_default }, + { "CROSSBAR_SRC_CR_R", 22, 23, &umr_bitfield_default }, + { "HUBPRET_CONTROL_SPARE", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPRET2_HUBPRET_MEM_PWR_CTRL[] = { + { "DET_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default }, + { "DET_MEM_PWR_DIS", 2, 2, &umr_bitfield_default }, + { "DET_MEM_PWR_LS_MODE", 4, 5, &umr_bitfield_default }, + { "HUBPRET_MEM_PWR_CTRL_SPARE", 8, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPRET2_HUBPRET_MEM_PWR_STATUS[] = { + { "DET_MEM_PWR_STATE", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPRET2_HUBPRET_READ_LINE_CTRL0[] = { + { "PIPE_READ_LINE_INTERVAL_IN_NONACTIVE", 0, 15, &umr_bitfield_default }, + { "PIPE_READ_LINE_VBLANK_MAXIMUM", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPRET2_HUBPRET_READ_LINE_CTRL1[] = { + { "PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED", 0, 13, &umr_bitfield_default }, + { "HUBPRET_READ_LINE_CTRL1_SPARE", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPRET2_HUBPRET_READ_LINE0[] = { + { "PIPE_READ_LINE0_START", 0, 13, &umr_bitfield_default }, + { "PIPE_READ_LINE0_END", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPRET2_HUBPRET_READ_LINE1[] = { + { "PIPE_READ_LINE1_START", 0, 13, &umr_bitfield_default }, + { "PIPE_READ_LINE1_END", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPRET2_HUBPRET_INTERRUPT[] = { + { "PIPE_VBLANK_INT_MASK", 0, 0, &umr_bitfield_default }, + { "PIPE_READ_LINE0_INT_MASK", 1, 1, &umr_bitfield_default }, + { "PIPE_READ_LINE1_INT_MASK", 2, 2, &umr_bitfield_default }, + { "PIPE_VBLANK_INT_TYPE", 4, 4, &umr_bitfield_default }, + { "PIPE_READ_LINE0_INT_TYPE", 5, 5, &umr_bitfield_default }, + { "PIPE_READ_LINE1_INT_TYPE", 6, 6, &umr_bitfield_default }, + { "PIPE_VBLANK_INT_CLEAR", 8, 8, &umr_bitfield_default }, + { "PIPE_READ_LINE0_INT_CLEAR", 9, 9, &umr_bitfield_default }, + { "PIPE_READ_LINE1_INT_CLEAR", 10, 10, &umr_bitfield_default }, + { "PIPE_VBLANK_STATUS", 12, 12, &umr_bitfield_default }, + { "PIPE_READ_LINE0_STATUS", 13, 13, &umr_bitfield_default }, + { "PIPE_READ_LINE1_STATUS", 14, 14, &umr_bitfield_default }, + { "PIPE_VBLANK_INT_STATUS", 16, 16, &umr_bitfield_default }, + { "PIPE_READ_LINE0_INT_STATUS", 17, 17, &umr_bitfield_default }, + { "PIPE_READ_LINE1_INT_STATUS", 18, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPRET2_HUBPRET_READ_LINE_VALUE[] = { + { "PIPE_READ_LINE", 0, 13, &umr_bitfield_default }, + { "PIPE_READ_LINE_SNAPSHOT", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPRET2_HUBPRET_READ_LINE_STATUS[] = { + { "PIPE_READ_VBLANK", 0, 0, &umr_bitfield_default }, + { "PIPE_READ_LINE0_INSIDE", 4, 4, &umr_bitfield_default }, + { "PIPE_READ_LINE0_OUTSIDE", 5, 5, &umr_bitfield_default }, + { "PIPE_READ_LINE1_INSIDE", 8, 8, &umr_bitfield_default }, + { "PIPE_READ_LINE1_OUTSIDE", 10, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCURSOR2_CURSOR_CONTROL[] = { + { "CURSOR_ENABLE", 0, 0, &umr_bitfield_default }, + { "CURSOR_MODE", 8, 9, &umr_bitfield_default }, + { "CURSOR_SNOOP", 13, 13, &umr_bitfield_default }, + { "CURSOR_SYSTEM", 14, 14, &umr_bitfield_default }, + { "CURSOR_PITCH", 16, 17, &umr_bitfield_default }, + { "CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS", 20, 20, &umr_bitfield_default }, + { "CURSOR_LINES_PER_CHUNK", 24, 28, &umr_bitfield_default }, + { "CURSOR_PERFMON_LATENCY_MEASURE_EN", 30, 30, &umr_bitfield_default }, + { "CURSOR_PERFMON_LATENCY_MEASURE_SEL", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCURSOR2_CURSOR_SURFACE_ADDRESS[] = { + { "CURSOR_SURFACE_ADDRESS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCURSOR2_CURSOR_SURFACE_ADDRESS_HIGH[] = { + { "CURSOR_SURFACE_ADDRESS_HIGH", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCURSOR2_CURSOR_SIZE[] = { + { "CURSOR_HEIGHT", 0, 8, &umr_bitfield_default }, + { "CURSOR_WIDTH", 16, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCURSOR2_CURSOR_POSITION[] = { + { "CURSOR_Y_POSITION", 0, 13, &umr_bitfield_default }, + { "CURSOR_X_POSITION", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCURSOR2_CURSOR_HOT_SPOT[] = { + { "CURSOR_HOT_SPOT_Y", 0, 7, &umr_bitfield_default }, + { "CURSOR_HOT_SPOT_X", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCURSOR2_CURSOR_STEREO_CONTROL[] = { + { "CURSOR_STEREO_EN", 0, 0, &umr_bitfield_default }, + { "CURSOR_PRIMARY_OFFSET", 4, 17, &umr_bitfield_default }, + { "CURSOR_SECONDARY_OFFSET", 18, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCURSOR2_CURSOR_DST_OFFSET[] = { + { "CURSOR_DST_X_OFFSET", 0, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCURSOR2_CURSOR_MEM_PWR_CTRL[] = { + { "CROB_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default }, + { "CROB_MEM_PWR_DIS", 2, 2, &umr_bitfield_default }, + { "CROB_MEM_PWR_LS_MODE", 4, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCURSOR2_CURSOR_MEM_PWR_STATUS[] = { + { "CROB_MEM_PWR_STATE", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON10_PERFCOUNTER_CNTL[] = { + { "PERFCOUNTER_EVENT_SEL", 0, 8, &umr_bitfield_default }, + { "PERFCOUNTER_CVALUE_SEL", 9, 11, &umr_bitfield_default }, + { "PERFCOUNTER_INC_MODE", 12, 14, &umr_bitfield_default }, + { "PERFCOUNTER_HW_CNTL_SEL", 15, 15, &umr_bitfield_default }, + { "PERFCOUNTER_RUNEN_MODE", 16, 16, &umr_bitfield_default }, + { "PERFCOUNTER_CNTOFF_START_DIS", 22, 22, &umr_bitfield_default }, + { "PERFCOUNTER_RESTART_EN", 23, 23, &umr_bitfield_default }, + { "PERFCOUNTER_INT_EN", 24, 24, &umr_bitfield_default }, + { "PERFCOUNTER_OFF_MASK", 25, 25, &umr_bitfield_default }, + { "PERFCOUNTER_ACTIVE", 26, 26, &umr_bitfield_default }, + { "PERFCOUNTER_CNTL_SEL", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON10_PERFCOUNTER_CNTL2[] = { + { "PERFCOUNTER_COUNTED_VALUE_TYPE", 0, 1, &umr_bitfield_default }, + { "PERFCOUNTER_HW_STOP1_SEL", 2, 2, &umr_bitfield_default }, + { "PERFCOUNTER_HW_STOP2_SEL", 3, 3, &umr_bitfield_default }, + { "PERFCOUNTER_CNTOFF_SEL", 8, 13, &umr_bitfield_default }, + { "PERFCOUNTER_CNTL2_SEL", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON10_PERFCOUNTER_STATE[] = { + { "PERFCOUNTER_CNT0_STATE", 0, 1, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL0", 2, 2, &umr_bitfield_default }, + { "PERFCOUNTER_CNT1_STATE", 4, 5, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL1", 6, 6, &umr_bitfield_default }, + { "PERFCOUNTER_CNT2_STATE", 8, 9, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL2", 10, 10, &umr_bitfield_default }, + { "PERFCOUNTER_CNT3_STATE", 12, 13, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL3", 14, 14, &umr_bitfield_default }, + { "PERFCOUNTER_CNT4_STATE", 16, 17, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL4", 18, 18, &umr_bitfield_default }, + { "PERFCOUNTER_CNT5_STATE", 20, 21, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL5", 22, 22, &umr_bitfield_default }, + { "PERFCOUNTER_CNT6_STATE", 24, 25, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL6", 26, 26, &umr_bitfield_default }, + { "PERFCOUNTER_CNT7_STATE", 28, 29, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL7", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON10_PERFMON_CNTL[] = { + { "PERFMON_STATE", 0, 1, &umr_bitfield_default }, + { "PERFMON_RPT_COUNT", 8, 27, &umr_bitfield_default }, + { "PERFMON_CNTOFF_AND_OR", 28, 28, &umr_bitfield_default }, + { "PERFMON_CNTOFF_INT_EN", 29, 29, &umr_bitfield_default }, + { "PERFMON_CNTOFF_INT_STATUS", 30, 30, &umr_bitfield_default }, + { "PERFMON_CNTOFF_INT_ACK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON10_PERFMON_CNTL2[] = { + { "PERFMON_CNTOFF_INT_TYPE", 0, 0, &umr_bitfield_default }, + { "PERFMON_CLK_ENABLE", 1, 1, &umr_bitfield_default }, + { "PERFMON_RUN_ENABLE_START_SEL", 2, 9, &umr_bitfield_default }, + { "PERFMON_RUN_ENABLE_STOP_SEL", 10, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC[] = { + { "PERFCOUNTER_INT0_STATUS", 0, 0, &umr_bitfield_default }, + { "PERFCOUNTER_INT1_STATUS", 1, 1, &umr_bitfield_default }, + { "PERFCOUNTER_INT2_STATUS", 2, 2, &umr_bitfield_default }, + { "PERFCOUNTER_INT3_STATUS", 3, 3, &umr_bitfield_default }, + { "PERFCOUNTER_INT4_STATUS", 4, 4, &umr_bitfield_default }, + { "PERFCOUNTER_INT5_STATUS", 5, 5, &umr_bitfield_default }, + { "PERFCOUNTER_INT6_STATUS", 6, 6, &umr_bitfield_default }, + { "PERFCOUNTER_INT7_STATUS", 7, 7, &umr_bitfield_default }, + { "PERFCOUNTER_INT0_ACK", 8, 8, &umr_bitfield_default }, + { "PERFCOUNTER_INT1_ACK", 9, 9, &umr_bitfield_default }, + { "PERFCOUNTER_INT2_ACK", 10, 10, &umr_bitfield_default }, + { "PERFCOUNTER_INT3_ACK", 11, 11, &umr_bitfield_default }, + { "PERFCOUNTER_INT4_ACK", 12, 12, &umr_bitfield_default }, + { "PERFCOUNTER_INT5_ACK", 13, 13, &umr_bitfield_default }, + { "PERFCOUNTER_INT6_ACK", 14, 14, &umr_bitfield_default }, + { "PERFCOUNTER_INT7_ACK", 15, 15, &umr_bitfield_default }, + { "PERFMON_CVALUE_HI", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON10_PERFMON_CVALUE_LOW[] = { + { "PERFMON_CVALUE_LOW", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON10_PERFMON_HI[] = { + { "PERFMON_HI", 0, 15, &umr_bitfield_default }, + { "PERFMON_READ_SEL", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON10_PERFMON_LOW[] = { + { "PERFMON_LOW", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP3_DCSURF_SURFACE_CONFIG[] = { + { "SURFACE_PIXEL_FORMAT", 0, 6, &umr_bitfield_default }, + { "ROTATION_ANGLE", 8, 9, &umr_bitfield_default }, + { "H_MIRROR_EN", 10, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP3_DCSURF_ADDR_CONFIG[] = { + { "NUM_PIPES", 0, 2, &umr_bitfield_default }, + { "NUM_BANKS", 3, 5, &umr_bitfield_default }, + { "PIPE_INTERLEAVE", 6, 7, &umr_bitfield_default }, + { "NUM_SE", 8, 9, &umr_bitfield_default }, + { "NUM_RB_PER_SE", 10, 11, &umr_bitfield_default }, + { "MAX_COMPRESSED_FRAGS", 12, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP3_DCSURF_TILING_CONFIG[] = { + { "SW_MODE", 0, 4, &umr_bitfield_default }, + { "DIM_TYPE", 7, 8, &umr_bitfield_default }, + { "META_LINEAR", 9, 9, &umr_bitfield_default }, + { "RB_ALIGNED", 10, 10, &umr_bitfield_default }, + { "PIPE_ALIGNED", 11, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP3_DCSURF_PRI_VIEWPORT_START[] = { + { "PRI_VIEWPORT_X_START", 0, 13, &umr_bitfield_default }, + { "PRI_VIEWPORT_Y_START", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION[] = { + { "PRI_VIEWPORT_WIDTH", 0, 13, &umr_bitfield_default }, + { "PRI_VIEWPORT_HEIGHT", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP3_DCSURF_PRI_VIEWPORT_START_C[] = { + { "PRI_VIEWPORT_X_START_C", 0, 13, &umr_bitfield_default }, + { "PRI_VIEWPORT_Y_START_C", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C[] = { + { "PRI_VIEWPORT_WIDTH_C", 0, 13, &umr_bitfield_default }, + { "PRI_VIEWPORT_HEIGHT_C", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP3_DCSURF_SEC_VIEWPORT_START[] = { + { "SEC_VIEWPORT_X_START", 0, 13, &umr_bitfield_default }, + { "SEC_VIEWPORT_Y_START", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION[] = { + { "SEC_VIEWPORT_WIDTH", 0, 13, &umr_bitfield_default }, + { "SEC_VIEWPORT_HEIGHT", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP3_DCSURF_SEC_VIEWPORT_START_C[] = { + { "SEC_VIEWPORT_X_START_C", 0, 13, &umr_bitfield_default }, + { "SEC_VIEWPORT_Y_START_C", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C[] = { + { "SEC_VIEWPORT_WIDTH_C", 0, 13, &umr_bitfield_default }, + { "SEC_VIEWPORT_HEIGHT_C", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP3_DCHUBP_REQ_SIZE_CONFIG[] = { + { "SWATH_HEIGHT", 0, 2, &umr_bitfield_default }, + { "PTE_ROW_HEIGHT_LINEAR", 4, 6, &umr_bitfield_default }, + { "CHUNK_SIZE", 8, 10, &umr_bitfield_default }, + { "MIN_CHUNK_SIZE", 11, 12, &umr_bitfield_default }, + { "META_CHUNK_SIZE", 16, 17, &umr_bitfield_default }, + { "MIN_META_CHUNK_SIZE", 18, 19, &umr_bitfield_default }, + { "DPTE_GROUP_SIZE", 20, 22, &umr_bitfield_default }, + { "MPTE_GROUP_SIZE", 24, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_C[] = { + { "SWATH_HEIGHT_C", 0, 2, &umr_bitfield_default }, + { "PTE_ROW_HEIGHT_LINEAR_C", 4, 6, &umr_bitfield_default }, + { "CHUNK_SIZE_C", 8, 10, &umr_bitfield_default }, + { "MIN_CHUNK_SIZE_C", 11, 12, &umr_bitfield_default }, + { "META_CHUNK_SIZE_C", 16, 17, &umr_bitfield_default }, + { "MIN_META_CHUNK_SIZE_C", 18, 19, &umr_bitfield_default }, + { "DPTE_GROUP_SIZE_C", 20, 22, &umr_bitfield_default }, + { "MPTE_GROUP_SIZE_C", 24, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP3_DCHUBP_CNTL[] = { + { "HUBP_BLANK_EN", 0, 0, &umr_bitfield_default }, + { "HUBP_NO_OUTSTANDING_REQ", 1, 1, &umr_bitfield_default }, + { "HUBP_DISABLE", 2, 2, &umr_bitfield_default }, + { "HUBP_IN_BLANK", 3, 3, &umr_bitfield_default }, + { "HUBP_VTG_SEL", 4, 7, &umr_bitfield_default }, + { "HUBP_TTU_DISABLE", 12, 12, &umr_bitfield_default }, + { "HUBP_TTU_MODE", 13, 15, &umr_bitfield_default }, + { "HUBP_UNDERFLOW_STATUS", 28, 30, &umr_bitfield_default }, + { "HUBP_UNDERFLOW_CLEAR", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP3_HUBP_CLK_CNTL[] = { + { "HUBP_CLOCK_ENABLE", 0, 0, &umr_bitfield_default }, + { "HUBP_DISPCLK_R_GATE_DIS", 4, 4, &umr_bitfield_default }, + { "HUBP_DPPCLK_G_GATE_DIS", 8, 8, &umr_bitfield_default }, + { "HUBP_DCFCLK_R_GATE_DIS", 12, 12, &umr_bitfield_default }, + { "HUBP_DCFCLK_G_GATE_DIS", 16, 16, &umr_bitfield_default }, + { "HUBP_DISPCLK_R_CLOCK_ON", 20, 20, &umr_bitfield_default }, + { "HUBP_DPPCLK_G_CLOCK_ON", 21, 21, &umr_bitfield_default }, + { "HUBP_DCFCLK_R_CLOCK_ON", 22, 22, &umr_bitfield_default }, + { "HUBP_DCFCLK_G_CLOCK_ON", 23, 23, &umr_bitfield_default }, + { "HUBP_TEST_CLK_SEL", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP3_DCHUBP_VMPG_CONFIG[] = { + { "VMPG_SIZE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP3_HUBPREQ_DEBUG_DB[] = { + { "HUBPREQ_DEBUG", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK[] = { + { "HUBP_MEASURE_WIN_EN_DCFCLK", 0, 0, &umr_bitfield_default }, + { "HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK", 4, 11, &umr_bitfield_default }, + { "HUBP_PERFMON_START_SEL_DCFCLK", 12, 16, &umr_bitfield_default }, + { "HUBP_PERFMON_STOP_SEL_DCFCLK", 20, 24, &umr_bitfield_default }, + { "HUBP_MEASURE_WIN_MODE_DCFCLK", 28, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK[] = { + { "HUBP_MEASURE_WIN_EN_DPPCLK", 0, 0, &umr_bitfield_default }, + { "HUBP_MEASURE_WIN_SRC_SEL_DPPCLK", 1, 1, &umr_bitfield_default }, + { "HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK", 4, 11, &umr_bitfield_default }, + { "HUBP_PERFMON_START_SEL_DPPCLK", 12, 16, &umr_bitfield_default }, + { "HUBP_PERFMON_STOP_SEL_DPPCLK", 20, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_DCSURF_SURFACE_PITCH[] = { + { "PITCH", 0, 13, &umr_bitfield_default }, + { "META_PITCH", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_DCSURF_SURFACE_PITCH_C[] = { + { "PITCH_C", 0, 13, &umr_bitfield_default }, + { "META_PITCH_C", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS[] = { + { "PRIMARY_SURFACE_ADDRESS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH[] = { + { "PRIMARY_SURFACE_ADDRESS_HIGH", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C[] = { + { "PRIMARY_SURFACE_ADDRESS_C", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C[] = { + { "PRIMARY_SURFACE_ADDRESS_HIGH_C", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS[] = { + { "SECONDARY_SURFACE_ADDRESS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH[] = { + { "SECONDARY_SURFACE_ADDRESS_HIGH", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C[] = { + { "SECONDARY_SURFACE_ADDRESS_C", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C[] = { + { "SECONDARY_SURFACE_ADDRESS_HIGH_C", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS[] = { + { "PRIMARY_META_SURFACE_ADDRESS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH[] = { + { "PRIMARY_META_SURFACE_ADDRESS_HIGH", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C[] = { + { "PRIMARY_META_SURFACE_ADDRESS_C", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C[] = { + { "PRIMARY_META_SURFACE_ADDRESS_HIGH_C", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS[] = { + { "SECONDARY_META_SURFACE_ADDRESS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH[] = { + { "SECONDARY_META_SURFACE_ADDRESS_HIGH", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C[] = { + { "SECONDARY_META_SURFACE_ADDRESS_C", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C[] = { + { "SECONDARY_META_SURFACE_ADDRESS_HIGH_C", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_DCSURF_SURFACE_CONTROL[] = { + { "PRIMARY_SURFACE_DCC_EN", 1, 1, &umr_bitfield_default }, + { "PRIMARY_SURFACE_DCC_IND_64B_BLK", 2, 2, &umr_bitfield_default }, + { "PRIMARY_SURFACE_DCC_IND_64B_BLK_C", 5, 5, &umr_bitfield_default }, + { "SECONDARY_SURFACE_DCC_EN", 9, 9, &umr_bitfield_default }, + { "SECONDARY_SURFACE_DCC_IND_64B_BLK", 10, 10, &umr_bitfield_default }, + { "SECONDARY_SURFACE_DCC_IND_64B_BLK_C", 13, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_DCSURF_FLIP_CONTROL[] = { + { "SURFACE_UPDATE_LOCK", 0, 0, &umr_bitfield_default }, + { "SURFACE_FLIP_TYPE", 1, 1, &umr_bitfield_default }, + { "SURFACE_FLIP_VUPDATE_SKIP_NUM", 4, 7, &umr_bitfield_default }, + { "SURFACE_FLIP_MODE_FOR_STEREOSYNC", 12, 13, &umr_bitfield_default }, + { "SURFACE_FLIP_IN_STEREOSYNC", 16, 16, &umr_bitfield_default }, + { "SURFACE_FLIP_STEREO_SELECT_DISABLE", 17, 17, &umr_bitfield_default }, + { "SURFACE_FLIP_STEREO_SELECT_POLARITY", 18, 18, &umr_bitfield_default }, + { "SURFACE_FLIP_PENDING_DELAY", 20, 29, &umr_bitfield_default }, + { "SURFACE_UPDATE_PENDING", 30, 30, &umr_bitfield_default }, + { "SURFACE_FLIP_PENDING", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_DCSURF_FLIP_CONTROL2[] = { + { "SURFACE_UPDATE_FLIP_PENDING_MIN_TIME", 0, 7, &umr_bitfield_default }, + { "SURFACE_UPDATE_PENDING_HIGH_EXTEND_ENABLE", 12, 12, &umr_bitfield_default }, + { "SURFACE_FLIP_PENDING_HIGH_EXTEND_ENABLE", 13, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_DCSURF_FRAME_PACING_CONTROL[] = { + { "SURFACE_FRAME_PACING_ENABLE", 0, 0, &umr_bitfield_default }, + { "SURFACE_FRAME_PACING_MODE", 1, 1, &umr_bitfield_default }, + { "SURFACE_FRAME_PACING_QUEUE_RESET", 8, 8, &umr_bitfield_default }, + { "SURFACE_FRAME_PACING_QUEUE_FREE_ENTRY", 24, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_DCSURF_FRAME_PACING_TIME[] = { + { "SURFACE_FRAME_PACING_TIME", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT[] = { + { "SURFACE_FLIP_INT_MASK", 0, 0, &umr_bitfield_default }, + { "SURFACE_FLIP_INT_TYPE", 1, 1, &umr_bitfield_default }, + { "SURFACE_FLIP_AWAY_INT_MASK", 2, 2, &umr_bitfield_default }, + { "SURFACE_FLIP_AWAY_INT_TYPE", 3, 3, &umr_bitfield_default }, + { "SURFACE_FLIP_CLEAR", 8, 8, &umr_bitfield_default }, + { "SURFACE_FLIP_AWAY_CLEAR", 9, 9, &umr_bitfield_default }, + { "SURFACE_FLIP_OCCURRED", 16, 16, &umr_bitfield_default }, + { "SURFACE_FLIP_INT_STATUS", 17, 17, &umr_bitfield_default }, + { "SURFACE_FLIP_AWAY_OCCURRED", 18, 18, &umr_bitfield_default }, + { "SURFACE_FLIP_AWAY_INT_STATUS", 19, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_DCSURF_SURFACE_INUSE[] = { + { "SURFACE_INUSE_ADDRESS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH[] = { + { "SURFACE_INUSE_ADDRESS_HIGH", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_DCSURF_SURFACE_INUSE_C[] = { + { "SURFACE_INUSE_ADDRESS_C", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C[] = { + { "SURFACE_INUSE_ADDRESS_HIGH_C", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE[] = { + { "SURFACE_EARLIEST_INUSE_ADDRESS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH[] = { + { "SURFACE_EARLIEST_INUSE_ADDRESS_HIGH", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C[] = { + { "SURFACE_EARLIEST_INUSE_ADDRESS_C", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C[] = { + { "SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_DCN_EXPANSION_MODE[] = { + { "DRQ_EXPANSION_MODE", 0, 1, &umr_bitfield_default }, + { "CRQ_EXPANSION_MODE", 2, 3, &umr_bitfield_default }, + { "MRQ_EXPANSION_MODE", 4, 5, &umr_bitfield_default }, + { "PRQ_EXPANSION_MODE", 6, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_DCN_TTU_QOS_WM[] = { + { "QoS_LEVEL_LOW_WM", 0, 13, &umr_bitfield_default }, + { "QoS_LEVEL_HIGH_WM", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_DCN_GLOBAL_TTU_CNTL[] = { + { "MIN_TTU_VBLANK", 0, 23, &umr_bitfield_default }, + { "QoS_LEVEL_FLIP", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_DCN_SURF0_TTU_CNTL0[] = { + { "REFCYC_PER_REQ_DELIVERY", 0, 22, &umr_bitfield_default }, + { "QoS_LEVEL_FIXED", 24, 27, &umr_bitfield_default }, + { "QoS_RAMP_DISABLE", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_DCN_SURF0_TTU_CNTL1[] = { + { "REFCYC_PER_REQ_DELIVERY_PRE", 0, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_DCN_SURF1_TTU_CNTL0[] = { + { "REFCYC_PER_REQ_DELIVERY", 0, 22, &umr_bitfield_default }, + { "QoS_LEVEL_FIXED", 24, 27, &umr_bitfield_default }, + { "QoS_RAMP_DISABLE", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_DCN_SURF1_TTU_CNTL1[] = { + { "REFCYC_PER_REQ_DELIVERY_PRE", 0, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_DCN_CUR0_TTU_CNTL0[] = { + { "REFCYC_PER_REQ_DELIVERY", 0, 22, &umr_bitfield_default }, + { "QoS_LEVEL_FIXED", 24, 27, &umr_bitfield_default }, + { "QoS_RAMP_DISABLE", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_DCN_CUR0_TTU_CNTL1[] = { + { "REFCYC_PER_REQ_DELIVERY_PRE", 0, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB[] = { + { "MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB[] = { + { "MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB[] = { + { "MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB[] = { + { "MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB[] = { + { "MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB[] = { + { "MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB", 0, 3, &umr_bitfield_default }, + { "MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM", 28, 28, &umr_bitfield_default }, + { "MC_VM_SYSTEM_APERTURE_DEFAULT_SNOOP", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB[] = { + { "VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB[] = { + { "VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB", 0, 3, &umr_bitfield_default }, + { "VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM", 28, 28, &umr_bitfield_default }, + { "VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SNOOP", 29, 29, &umr_bitfield_default }, + { "VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_TMZ", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB[] = { + { "VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB[] = { + { "VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB[] = { + { "VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB[] = { + { "VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB[] = { + { "VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB[] = { + { "VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_DCN_VM_CONTEXT0_STATUS[] = { + { "DCN_VM_CONTEXT0_ERROR_STATUS", 0, 15, &umr_bitfield_default }, + { "DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_MSB", 24, 27, &umr_bitfield_default }, + { "DCN_VM_CONTEXT0_ERROR_STATUS_MODE", 30, 30, &umr_bitfield_default }, + { "DCN_VM_CONTEXT0_ERROR_STATUS_CLEAR", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB[] = { + { "DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_DCN_VM_CONTEXT0_CNTL[] = { + { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 3, 3, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 4, 4, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 12, 12, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 13, 13, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL[] = { + { "ENABLE_L1_TLB", 0, 0, &umr_bitfield_default }, + { "SYSTEM_ACCESS_MODE", 3, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_BLANK_OFFSET_0[] = { + { "REFCYC_H_BLANK_END", 0, 12, &umr_bitfield_default }, + { "DLG_V_BLANK_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_BLANK_OFFSET_1[] = { + { "MIN_DST_Y_NEXT_START", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_DST_DIMENSIONS[] = { + { "REFCYC_PER_HTOTAL", 0, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_DST_AFTER_SCALER[] = { + { "REFCYC_X_AFTER_SCALER", 0, 12, &umr_bitfield_default }, + { "DST_Y_AFTER_SCALER", 16, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_PREFETCH_SETTINS[] = { + { "VRATIO_PREFETCH", 0, 20, &umr_bitfield_default }, + { "DST_Y_PREFETCH", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_PREFETCH_SETTINS_C[] = { + { "VRATIO_PREFETCH_C", 0, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_VBLANK_PARAMETERS_0[] = { + { "DST_Y_PER_VM_VBLANK", 0, 4, &umr_bitfield_default }, + { "DST_Y_PER_ROW_VBLANK", 8, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_VBLANK_PARAMETERS_1[] = { + { "REFCYC_PER_PTE_GROUP_VBLANK_L", 0, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_VBLANK_PARAMETERS_2[] = { + { "REFCYC_PER_PTE_GROUP_VBLANK_C", 0, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_VBLANK_PARAMETERS_3[] = { + { "REFCYC_PER_META_CHUNK_VBLANK_L", 0, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_VBLANK_PARAMETERS_4[] = { + { "REFCYC_PER_META_CHUNK_VBLANK_C", 0, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_NOM_PARAMETERS_0[] = { + { "DST_Y_PER_PTE_ROW_NOM_L", 0, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_NOM_PARAMETERS_1[] = { + { "REFCYC_PER_PTE_GROUP_NOM_L", 0, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_NOM_PARAMETERS_2[] = { + { "DST_Y_PER_PTE_ROW_NOM_C", 0, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_NOM_PARAMETERS_3[] = { + { "REFCYC_PER_PTE_GROUP_NOM_C", 0, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_NOM_PARAMETERS_4[] = { + { "DST_Y_PER_META_ROW_NOM_L", 0, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_NOM_PARAMETERS_5[] = { + { "REFCYC_PER_META_CHUNK_NOM_L", 0, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_NOM_PARAMETERS_6[] = { + { "DST_Y_PER_META_ROW_NOM_C", 0, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_NOM_PARAMETERS_7[] = { + { "REFCYC_PER_META_CHUNK_NOM_C", 0, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_PER_LINE_DELIVERY_PRE[] = { + { "REFCYC_PER_LINE_DELIVERY_PRE_L", 0, 12, &umr_bitfield_default }, + { "REFCYC_PER_LINE_DELIVERY_PRE_C", 16, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_PER_LINE_DELIVERY[] = { + { "REFCYC_PER_LINE_DELIVERY_L", 0, 12, &umr_bitfield_default }, + { "REFCYC_PER_LINE_DELIVERY_C", 16, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_CURSOR_SETTINS[] = { + { "CURSOR0_DST_Y_OFFSET", 0, 7, &umr_bitfield_default }, + { "CURSOR0_CHUNK_HDL_ADJUST", 8, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_REF_FREQ_TO_PIX_FREQ[] = { + { "REF_FREQ_TO_PIX_FREQ", 0, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_HUBPREQ_MEM_PWR_CTRL[] = { + { "REQ_DPTE_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default }, + { "REQ_DPTE_MEM_PWR_DIS", 2, 2, &umr_bitfield_default }, + { "REQ_MPTE_MEM_PWR_FORCE", 4, 5, &umr_bitfield_default }, + { "REQ_MPTE_MEM_PWR_DIS", 6, 6, &umr_bitfield_default }, + { "REQ_META_MEM_PWR_FORCE", 8, 9, &umr_bitfield_default }, + { "REQ_META_MEM_PWR_DIS", 10, 10, &umr_bitfield_default }, + { "REQ_DPTE_FINE_GRAIN_DIS", 16, 16, &umr_bitfield_default }, + { "REQ_DPTE_FINE_GRAIN_DIS_C", 17, 17, &umr_bitfield_default }, + { "REQ_META_FINE_GRAIN_DIS", 20, 20, &umr_bitfield_default }, + { "REQ_META_FINE_GRAIN_DIS_C", 21, 21, &umr_bitfield_default }, + { "REQ_MPTE_FINE_GRAIN_DIS", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPREQ3_HUBPREQ_MEM_PWR_STATUS[] = { + { "REQ_DPTE_MEM_PWR_STATE", 0, 1, &umr_bitfield_default }, + { "REQ_MPTE_MEM_PWR_STATE", 2, 3, &umr_bitfield_default }, + { "REQ_META_MEM_PWR_STATE", 4, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPRET3_HUBPRET_CONTROL[] = { + { "DET_BUF_PLANE1_BASE_ADDRESS", 0, 11, &umr_bitfield_default }, + { "PACK_3TO2_ELEMENT_DISABLE", 12, 12, &umr_bitfield_default }, + { "CROSSBAR_SRC_ALPHA", 16, 17, &umr_bitfield_default }, + { "CROSSBAR_SRC_Y_G", 18, 19, &umr_bitfield_default }, + { "CROSSBAR_SRC_CB_B", 20, 21, &umr_bitfield_default }, + { "CROSSBAR_SRC_CR_R", 22, 23, &umr_bitfield_default }, + { "HUBPRET_CONTROL_SPARE", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPRET3_HUBPRET_MEM_PWR_CTRL[] = { + { "DET_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default }, + { "DET_MEM_PWR_DIS", 2, 2, &umr_bitfield_default }, + { "DET_MEM_PWR_LS_MODE", 4, 5, &umr_bitfield_default }, + { "HUBPRET_MEM_PWR_CTRL_SPARE", 8, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPRET3_HUBPRET_MEM_PWR_STATUS[] = { + { "DET_MEM_PWR_STATE", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPRET3_HUBPRET_READ_LINE_CTRL0[] = { + { "PIPE_READ_LINE_INTERVAL_IN_NONACTIVE", 0, 15, &umr_bitfield_default }, + { "PIPE_READ_LINE_VBLANK_MAXIMUM", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPRET3_HUBPRET_READ_LINE_CTRL1[] = { + { "PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED", 0, 13, &umr_bitfield_default }, + { "HUBPRET_READ_LINE_CTRL1_SPARE", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPRET3_HUBPRET_READ_LINE0[] = { + { "PIPE_READ_LINE0_START", 0, 13, &umr_bitfield_default }, + { "PIPE_READ_LINE0_END", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPRET3_HUBPRET_READ_LINE1[] = { + { "PIPE_READ_LINE1_START", 0, 13, &umr_bitfield_default }, + { "PIPE_READ_LINE1_END", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPRET3_HUBPRET_INTERRUPT[] = { + { "PIPE_VBLANK_INT_MASK", 0, 0, &umr_bitfield_default }, + { "PIPE_READ_LINE0_INT_MASK", 1, 1, &umr_bitfield_default }, + { "PIPE_READ_LINE1_INT_MASK", 2, 2, &umr_bitfield_default }, + { "PIPE_VBLANK_INT_TYPE", 4, 4, &umr_bitfield_default }, + { "PIPE_READ_LINE0_INT_TYPE", 5, 5, &umr_bitfield_default }, + { "PIPE_READ_LINE1_INT_TYPE", 6, 6, &umr_bitfield_default }, + { "PIPE_VBLANK_INT_CLEAR", 8, 8, &umr_bitfield_default }, + { "PIPE_READ_LINE0_INT_CLEAR", 9, 9, &umr_bitfield_default }, + { "PIPE_READ_LINE1_INT_CLEAR", 10, 10, &umr_bitfield_default }, + { "PIPE_VBLANK_STATUS", 12, 12, &umr_bitfield_default }, + { "PIPE_READ_LINE0_STATUS", 13, 13, &umr_bitfield_default }, + { "PIPE_READ_LINE1_STATUS", 14, 14, &umr_bitfield_default }, + { "PIPE_VBLANK_INT_STATUS", 16, 16, &umr_bitfield_default }, + { "PIPE_READ_LINE0_INT_STATUS", 17, 17, &umr_bitfield_default }, + { "PIPE_READ_LINE1_INT_STATUS", 18, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPRET3_HUBPRET_READ_LINE_VALUE[] = { + { "PIPE_READ_LINE", 0, 13, &umr_bitfield_default }, + { "PIPE_READ_LINE_SNAPSHOT", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHUBPRET3_HUBPRET_READ_LINE_STATUS[] = { + { "PIPE_READ_VBLANK", 0, 0, &umr_bitfield_default }, + { "PIPE_READ_LINE0_INSIDE", 4, 4, &umr_bitfield_default }, + { "PIPE_READ_LINE0_OUTSIDE", 5, 5, &umr_bitfield_default }, + { "PIPE_READ_LINE1_INSIDE", 8, 8, &umr_bitfield_default }, + { "PIPE_READ_LINE1_OUTSIDE", 10, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCURSOR3_CURSOR_CONTROL[] = { + { "CURSOR_ENABLE", 0, 0, &umr_bitfield_default }, + { "CURSOR_MODE", 8, 9, &umr_bitfield_default }, + { "CURSOR_SNOOP", 13, 13, &umr_bitfield_default }, + { "CURSOR_SYSTEM", 14, 14, &umr_bitfield_default }, + { "CURSOR_PITCH", 16, 17, &umr_bitfield_default }, + { "CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS", 20, 20, &umr_bitfield_default }, + { "CURSOR_LINES_PER_CHUNK", 24, 28, &umr_bitfield_default }, + { "CURSOR_PERFMON_LATENCY_MEASURE_EN", 30, 30, &umr_bitfield_default }, + { "CURSOR_PERFMON_LATENCY_MEASURE_SEL", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCURSOR3_CURSOR_SURFACE_ADDRESS[] = { + { "CURSOR_SURFACE_ADDRESS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCURSOR3_CURSOR_SURFACE_ADDRESS_HIGH[] = { + { "CURSOR_SURFACE_ADDRESS_HIGH", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCURSOR3_CURSOR_SIZE[] = { + { "CURSOR_HEIGHT", 0, 8, &umr_bitfield_default }, + { "CURSOR_WIDTH", 16, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCURSOR3_CURSOR_POSITION[] = { + { "CURSOR_Y_POSITION", 0, 13, &umr_bitfield_default }, + { "CURSOR_X_POSITION", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCURSOR3_CURSOR_HOT_SPOT[] = { + { "CURSOR_HOT_SPOT_Y", 0, 7, &umr_bitfield_default }, + { "CURSOR_HOT_SPOT_X", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCURSOR3_CURSOR_STEREO_CONTROL[] = { + { "CURSOR_STEREO_EN", 0, 0, &umr_bitfield_default }, + { "CURSOR_PRIMARY_OFFSET", 4, 17, &umr_bitfield_default }, + { "CURSOR_SECONDARY_OFFSET", 18, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCURSOR3_CURSOR_DST_OFFSET[] = { + { "CURSOR_DST_X_OFFSET", 0, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCURSOR3_CURSOR_MEM_PWR_CTRL[] = { + { "CROB_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default }, + { "CROB_MEM_PWR_DIS", 2, 2, &umr_bitfield_default }, + { "CROB_MEM_PWR_LS_MODE", 4, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCURSOR3_CURSOR_MEM_PWR_STATUS[] = { + { "CROB_MEM_PWR_STATE", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON11_PERFCOUNTER_CNTL[] = { + { "PERFCOUNTER_EVENT_SEL", 0, 8, &umr_bitfield_default }, + { "PERFCOUNTER_CVALUE_SEL", 9, 11, &umr_bitfield_default }, + { "PERFCOUNTER_INC_MODE", 12, 14, &umr_bitfield_default }, + { "PERFCOUNTER_HW_CNTL_SEL", 15, 15, &umr_bitfield_default }, + { "PERFCOUNTER_RUNEN_MODE", 16, 16, &umr_bitfield_default }, + { "PERFCOUNTER_CNTOFF_START_DIS", 22, 22, &umr_bitfield_default }, + { "PERFCOUNTER_RESTART_EN", 23, 23, &umr_bitfield_default }, + { "PERFCOUNTER_INT_EN", 24, 24, &umr_bitfield_default }, + { "PERFCOUNTER_OFF_MASK", 25, 25, &umr_bitfield_default }, + { "PERFCOUNTER_ACTIVE", 26, 26, &umr_bitfield_default }, + { "PERFCOUNTER_CNTL_SEL", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON11_PERFCOUNTER_CNTL2[] = { + { "PERFCOUNTER_COUNTED_VALUE_TYPE", 0, 1, &umr_bitfield_default }, + { "PERFCOUNTER_HW_STOP1_SEL", 2, 2, &umr_bitfield_default }, + { "PERFCOUNTER_HW_STOP2_SEL", 3, 3, &umr_bitfield_default }, + { "PERFCOUNTER_CNTOFF_SEL", 8, 13, &umr_bitfield_default }, + { "PERFCOUNTER_CNTL2_SEL", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON11_PERFCOUNTER_STATE[] = { + { "PERFCOUNTER_CNT0_STATE", 0, 1, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL0", 2, 2, &umr_bitfield_default }, + { "PERFCOUNTER_CNT1_STATE", 4, 5, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL1", 6, 6, &umr_bitfield_default }, + { "PERFCOUNTER_CNT2_STATE", 8, 9, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL2", 10, 10, &umr_bitfield_default }, + { "PERFCOUNTER_CNT3_STATE", 12, 13, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL3", 14, 14, &umr_bitfield_default }, + { "PERFCOUNTER_CNT4_STATE", 16, 17, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL4", 18, 18, &umr_bitfield_default }, + { "PERFCOUNTER_CNT5_STATE", 20, 21, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL5", 22, 22, &umr_bitfield_default }, + { "PERFCOUNTER_CNT6_STATE", 24, 25, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL6", 26, 26, &umr_bitfield_default }, + { "PERFCOUNTER_CNT7_STATE", 28, 29, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL7", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON11_PERFMON_CNTL[] = { + { "PERFMON_STATE", 0, 1, &umr_bitfield_default }, + { "PERFMON_RPT_COUNT", 8, 27, &umr_bitfield_default }, + { "PERFMON_CNTOFF_AND_OR", 28, 28, &umr_bitfield_default }, + { "PERFMON_CNTOFF_INT_EN", 29, 29, &umr_bitfield_default }, + { "PERFMON_CNTOFF_INT_STATUS", 30, 30, &umr_bitfield_default }, + { "PERFMON_CNTOFF_INT_ACK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON11_PERFMON_CNTL2[] = { + { "PERFMON_CNTOFF_INT_TYPE", 0, 0, &umr_bitfield_default }, + { "PERFMON_CLK_ENABLE", 1, 1, &umr_bitfield_default }, + { "PERFMON_RUN_ENABLE_START_SEL", 2, 9, &umr_bitfield_default }, + { "PERFMON_RUN_ENABLE_STOP_SEL", 10, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC[] = { + { "PERFCOUNTER_INT0_STATUS", 0, 0, &umr_bitfield_default }, + { "PERFCOUNTER_INT1_STATUS", 1, 1, &umr_bitfield_default }, + { "PERFCOUNTER_INT2_STATUS", 2, 2, &umr_bitfield_default }, + { "PERFCOUNTER_INT3_STATUS", 3, 3, &umr_bitfield_default }, + { "PERFCOUNTER_INT4_STATUS", 4, 4, &umr_bitfield_default }, + { "PERFCOUNTER_INT5_STATUS", 5, 5, &umr_bitfield_default }, + { "PERFCOUNTER_INT6_STATUS", 6, 6, &umr_bitfield_default }, + { "PERFCOUNTER_INT7_STATUS", 7, 7, &umr_bitfield_default }, + { "PERFCOUNTER_INT0_ACK", 8, 8, &umr_bitfield_default }, + { "PERFCOUNTER_INT1_ACK", 9, 9, &umr_bitfield_default }, + { "PERFCOUNTER_INT2_ACK", 10, 10, &umr_bitfield_default }, + { "PERFCOUNTER_INT3_ACK", 11, 11, &umr_bitfield_default }, + { "PERFCOUNTER_INT4_ACK", 12, 12, &umr_bitfield_default }, + { "PERFCOUNTER_INT5_ACK", 13, 13, &umr_bitfield_default }, + { "PERFCOUNTER_INT6_ACK", 14, 14, &umr_bitfield_default }, + { "PERFCOUNTER_INT7_ACK", 15, 15, &umr_bitfield_default }, + { "PERFMON_CVALUE_HI", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON11_PERFMON_CVALUE_LOW[] = { + { "PERFMON_CVALUE_LOW", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON11_PERFMON_HI[] = { + { "PERFMON_HI", 0, 15, &umr_bitfield_default }, + { "PERFMON_READ_SEL", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON11_PERFMON_LOW[] = { + { "PERFMON_LOW", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDPP_TOP0_DPP_CONTROL[] = { + { "DPP_CLOCK_ENABLE", 4, 4, &umr_bitfield_default }, + { "DPPCLK_G_GATE_DISABLE", 8, 8, &umr_bitfield_default }, + { "DPPCLK_G_DYN_GATE_DISABLE", 10, 10, &umr_bitfield_default }, + { "DPPCLK_G_DSCL_GATE_DISABLE", 12, 12, &umr_bitfield_default }, + { "DPPCLK_R_GATE_DISABLE", 16, 16, &umr_bitfield_default }, + { "DISPCLK_R_GATE_DISABLE", 18, 18, &umr_bitfield_default }, + { "DISPCLK_G_GATE_DISABLE", 20, 20, &umr_bitfield_default }, + { "DPPCLK_RATE_CONTROL", 24, 24, &umr_bitfield_default }, + { "DPP_TEST_CLK_SEL", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDPP_TOP0_DPP_SOFT_RESET[] = { + { "CNVC_SOFT_RESET", 0, 0, &umr_bitfield_default }, + { "DSCL_SOFT_RESET", 4, 4, &umr_bitfield_default }, + { "CM_SOFT_RESET", 8, 8, &umr_bitfield_default }, + { "OBUF_SOFT_RESET", 12, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDPP_TOP0_DPP_CRC_VAL_R_G[] = { + { "DPP_CRC_R_CR", 0, 15, &umr_bitfield_default }, + { "DPP_CRC_G_Y", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDPP_TOP0_DPP_CRC_VAL_B_A[] = { + { "DPP_CRC_B_CB", 0, 15, &umr_bitfield_default }, + { "DPP_CRC_ALPHA", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDPP_TOP0_DPP_CRC_CTRL[] = { + { "DPP_CRC_EN", 0, 0, &umr_bitfield_default }, + { "DPP_CRC_CONT_EN", 1, 1, &umr_bitfield_default }, + { "DPP_CRC_ONE_SHOT_PENDING", 2, 2, &umr_bitfield_default }, + { "DPP_CRC_420_COMP_SEL", 3, 3, &umr_bitfield_default }, + { "DPP_CRC_SRC_SEL", 4, 5, &umr_bitfield_default }, + { "DPP_CRC_STEREO_EN", 7, 7, &umr_bitfield_default }, + { "DPP_CRC_STEREO_MODE", 8, 9, &umr_bitfield_default }, + { "DPP_CRC_INTERLACE_MODE", 10, 11, &umr_bitfield_default }, + { "DPP_CRC_PIX_FORMAT_SEL", 12, 14, &umr_bitfield_default }, + { "DPP_CRC_CURSOR_FORMAT_SEL", 15, 15, &umr_bitfield_default }, + { "DPP_CRC_MASK", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDPP_TOP0_HOST_READ_CONTROL[] = { + { "HOST_READ_RATE_CONTROL", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT[] = { + { "CNVC_SURFACE_PIXEL_FORMAT", 0, 6, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNVC_CFG0_FORMAT_CONTROL[] = { + { "FORMAT_EXPANSION_MODE", 0, 0, &umr_bitfield_default }, + { "FORMAT_CNV16", 4, 4, &umr_bitfield_default }, + { "ALPHA_EN", 8, 8, &umr_bitfield_default }, + { "CNVC_BYPASS", 12, 12, &umr_bitfield_default }, + { "OUTPUT_FP", 16, 16, &umr_bitfield_default }, + { "CNVC_UPDATE_PENDING", 20, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNVC_CFG0_FCNV_FP_SCALE_BIAS[] = { + { "FCNV_FP_SCALE", 0, 15, &umr_bitfield_default }, + { "FCNV_FP_BIAS", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNVC_CFG0_DENORM_CONTROL[] = { + { "DENORM_SCALE", 0, 14, &umr_bitfield_default }, + { "CLAMP_POSITIVE", 15, 15, &umr_bitfield_default }, + { "DENORM_BIAS", 16, 30, &umr_bitfield_default }, + { "DENORM_TRUNCATE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNVC_CFG0_COLOR_KEYER_CONTROL[] = { + { "COLOR_KEYER_EN", 0, 0, &umr_bitfield_default }, + { "COLOR_KEYER_MODE", 4, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNVC_CFG0_COLOR_KEYER_ALPHA[] = { + { "COLOR_KEYER_ALPHA_LOW", 0, 15, &umr_bitfield_default }, + { "COLOR_KEYER_ALPHA_HIGH", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNVC_CFG0_COLOR_KEYER_RED[] = { + { "COLOR_KEYER_RED_LOW", 0, 15, &umr_bitfield_default }, + { "COLOR_KEYER_RED_HIGH", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNVC_CFG0_COLOR_KEYER_GREEN[] = { + { "COLOR_KEYER_GREEN_LOW", 0, 15, &umr_bitfield_default }, + { "COLOR_KEYER_GREEN_HIGH", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNVC_CFG0_COLOR_KEYER_BLUE[] = { + { "COLOR_KEYER_BLUE_LOW", 0, 15, &umr_bitfield_default }, + { "COLOR_KEYER_BLUE_HIGH", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNVC_CUR0_CURSOR0_CONTROL[] = { + { "CUR0_ENABLE", 0, 0, &umr_bitfield_default }, + { "CUR0_EXPANSION_MODE", 1, 1, &umr_bitfield_default }, + { "CUR0_INVERT_MODE", 2, 2, &umr_bitfield_default }, + { "CUR0_MODE", 4, 5, &umr_bitfield_default }, + { "CUR0_UPDATE_PENDING", 6, 6, &umr_bitfield_default }, + { "CUR0_MAX", 8, 19, &umr_bitfield_default }, + { "CUR0_MIN", 20, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNVC_CUR0_CURSOR0_COLOR0[] = { + { "CUR0_COLOR0", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNVC_CUR0_CURSOR0_COLOR1[] = { + { "CUR0_COLOR1", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS[] = { + { "CUR0_FP_SCALE", 0, 15, &umr_bitfield_default }, + { "CUR0_FP_BIAS", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL0_SCL_COEF_RAM_TAP_SELECT[] = { + { "SCL_COEF_RAM_TAP_PAIR_IDX", 0, 1, &umr_bitfield_default }, + { "SCL_COEF_RAM_PHASE", 8, 13, &umr_bitfield_default }, + { "SCL_COEF_RAM_FILTER_TYPE", 16, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL0_SCL_COEF_RAM_TAP_DATA[] = { + { "SCL_COEF_RAM_EVEN_TAP_COEF", 0, 13, &umr_bitfield_default }, + { "SCL_COEF_RAM_EVEN_TAP_COEF_EN", 15, 15, &umr_bitfield_default }, + { "SCL_COEF_RAM_ODD_TAP_COEF", 16, 29, &umr_bitfield_default }, + { "SCL_COEF_RAM_ODD_TAP_COEF_EN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL0_SCL_MODE[] = { + { "DSCL_MODE", 0, 2, &umr_bitfield_default }, + { "SCL_COEF_RAM_SELECT", 8, 8, &umr_bitfield_default }, + { "SCL_COEF_RAM_SELECT_CURRENT", 12, 12, &umr_bitfield_default }, + { "SCL_CHROMA_COEF_MODE", 16, 16, &umr_bitfield_default }, + { "SCL_ALPHA_COEF_MODE", 20, 20, &umr_bitfield_default }, + { "SCL_COEF_RAM_SELECT_RD", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL0_SCL_TAP_CONTROL[] = { + { "SCL_V_NUM_TAPS", 0, 2, &umr_bitfield_default }, + { "SCL_H_NUM_TAPS", 4, 6, &umr_bitfield_default }, + { "SCL_V_NUM_TAPS_C", 8, 10, &umr_bitfield_default }, + { "SCL_H_NUM_TAPS_C", 12, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL0_DSCL_CONTROL[] = { + { "SCL_BOUNDARY_MODE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL0_DSCL_2TAP_CONTROL[] = { + { "SCL_H_2TAP_HARDCODE_COEF_EN", 0, 0, &umr_bitfield_default }, + { "SCL_H_2TAP_SHARP_EN", 4, 4, &umr_bitfield_default }, + { "SCL_H_2TAP_SHARP_FACTOR", 8, 10, &umr_bitfield_default }, + { "SCL_V_2TAP_HARDCODE_COEF_EN", 16, 16, &umr_bitfield_default }, + { "SCL_V_2TAP_SHARP_EN", 20, 20, &umr_bitfield_default }, + { "SCL_V_2TAP_SHARP_FACTOR", 24, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL[] = { + { "SCL_V_MANUAL_REPLICATE_FACTOR", 0, 3, &umr_bitfield_default }, + { "SCL_H_MANUAL_REPLICATE_FACTOR", 8, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO[] = { + { "SCL_H_SCALE_RATIO", 0, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL0_SCL_HORZ_FILTER_INIT[] = { + { "SCL_H_INIT_FRAC", 0, 23, &umr_bitfield_default }, + { "SCL_H_INIT_INT", 24, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C[] = { + { "SCL_H_SCALE_RATIO_C", 0, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL0_SCL_HORZ_FILTER_INIT_C[] = { + { "SCL_H_INIT_FRAC_C", 0, 23, &umr_bitfield_default }, + { "SCL_H_INIT_INT_C", 24, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO[] = { + { "SCL_V_SCALE_RATIO", 0, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL0_SCL_VERT_FILTER_INIT[] = { + { "SCL_V_INIT_FRAC", 0, 23, &umr_bitfield_default }, + { "SCL_V_INIT_INT", 24, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL0_SCL_VERT_FILTER_INIT_BOT[] = { + { "SCL_V_INIT_FRAC_BOT", 0, 23, &umr_bitfield_default }, + { "SCL_V_INIT_INT_BOT", 24, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C[] = { + { "SCL_V_SCALE_RATIO_C", 0, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL0_SCL_VERT_FILTER_INIT_C[] = { + { "SCL_V_INIT_FRAC_C", 0, 23, &umr_bitfield_default }, + { "SCL_V_INIT_INT_C", 24, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C[] = { + { "SCL_V_INIT_FRAC_BOT_C", 0, 23, &umr_bitfield_default }, + { "SCL_V_INIT_INT_BOT_C", 24, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL0_SCL_BLACK_OFFSET[] = { + { "SCL_BLACK_OFFSET_RGB_Y", 0, 15, &umr_bitfield_default }, + { "SCL_BLACK_OFFSET_CBCR", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL0_DSCL_UPDATE[] = { + { "SCL_UPDATE_PENDING", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL0_DSCL_AUTOCAL[] = { + { "AUTOCAL_MODE", 0, 1, &umr_bitfield_default }, + { "AUTOCAL_NUM_PIPE", 8, 9, &umr_bitfield_default }, + { "AUTOCAL_PIPE_ID", 12, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT[] = { + { "EXT_OVERSCAN_RIGHT", 0, 12, &umr_bitfield_default }, + { "EXT_OVERSCAN_LEFT", 16, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM[] = { + { "EXT_OVERSCAN_BOTTOM", 0, 12, &umr_bitfield_default }, + { "EXT_OVERSCAN_TOP", 16, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL0_OTG_H_BLANK[] = { + { "OTG_H_BLANK_START", 0, 13, &umr_bitfield_default }, + { "OTG_H_BLANK_END", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL0_OTG_V_BLANK[] = { + { "OTG_V_BLANK_START", 0, 13, &umr_bitfield_default }, + { "OTG_V_BLANK_END", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL0_RECOUT_START[] = { + { "RECOUT_START_X", 0, 12, &umr_bitfield_default }, + { "RECOUT_START_Y", 16, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL0_RECOUT_SIZE[] = { + { "RECOUT_WIDTH", 0, 13, &umr_bitfield_default }, + { "RECOUT_HEIGHT", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL0_MPC_SIZE[] = { + { "MPC_WIDTH", 0, 13, &umr_bitfield_default }, + { "MPC_HEIGHT", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL0_LB_DATA_FORMAT[] = { + { "PIXEL_DEPTH", 0, 1, &umr_bitfield_default }, + { "PIXEL_EXPAN_MODE", 8, 8, &umr_bitfield_default }, + { "PIXEL_REDUCE_MODE", 12, 12, &umr_bitfield_default }, + { "DYNAMIC_PIXEL_DEPTH", 16, 16, &umr_bitfield_default }, + { "DITHER_EN", 20, 20, &umr_bitfield_default }, + { "INTERLEAVE_EN", 24, 24, &umr_bitfield_default }, + { "ALPHA_EN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL0_LB_MEMORY_CTRL[] = { + { "MEMORY_CONFIG", 0, 1, &umr_bitfield_default }, + { "LB_MAX_PARTITIONS", 8, 13, &umr_bitfield_default }, + { "LB_NUM_PARTITIONS", 16, 22, &umr_bitfield_default }, + { "LB_NUM_PARTITIONS_C", 24, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL0_LB_V_COUNTER[] = { + { "V_COUNTER", 0, 12, &umr_bitfield_default }, + { "V_COUNTER_C", 16, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL0_DSCL_MEM_PWR_CTRL[] = { + { "LUT_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default }, + { "LUT_MEM_PWR_DIS", 2, 2, &umr_bitfield_default }, + { "LB_G1_MEM_PWR_FORCE", 4, 5, &umr_bitfield_default }, + { "LB_G1_MEM_PWR_DIS", 6, 6, &umr_bitfield_default }, + { "LB_G2_MEM_PWR_FORCE", 8, 9, &umr_bitfield_default }, + { "LB_G2_MEM_PWR_DIS", 10, 10, &umr_bitfield_default }, + { "LB_G3_MEM_PWR_FORCE", 12, 13, &umr_bitfield_default }, + { "LB_G3_MEM_PWR_DIS", 14, 14, &umr_bitfield_default }, + { "LB_G4_MEM_PWR_FORCE", 16, 17, &umr_bitfield_default }, + { "LB_G4_MEM_PWR_DIS", 18, 18, &umr_bitfield_default }, + { "LB_G5_MEM_PWR_FORCE", 20, 21, &umr_bitfield_default }, + { "LB_G5_MEM_PWR_DIS", 22, 22, &umr_bitfield_default }, + { "LB_G6_MEM_PWR_FORCE", 24, 25, &umr_bitfield_default }, + { "LB_G6_MEM_PWR_DIS", 26, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL0_DSCL_MEM_PWR_STATUS[] = { + { "LUT_MEM_PWR_STATE", 0, 1, &umr_bitfield_default }, + { "LB_G1_MEM_PWR_STATE", 2, 3, &umr_bitfield_default }, + { "LB_G2_MEM_PWR_STATE", 4, 5, &umr_bitfield_default }, + { "LB_G3_MEM_PWR_STATE", 6, 7, &umr_bitfield_default }, + { "LB_G4_MEM_PWR_STATE", 8, 9, &umr_bitfield_default }, + { "LB_G5_MEM_PWR_STATE", 10, 11, &umr_bitfield_default }, + { "LB_G6_MEM_PWR_STATE", 12, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL0_OBUF_CONTROL[] = { + { "OBUF_BYPASS", 0, 0, &umr_bitfield_default }, + { "OBUF_USE_FULL_BUFFER", 4, 4, &umr_bitfield_default }, + { "OBUF_H_2X_UPSCALE_EN", 8, 8, &umr_bitfield_default }, + { "OBUF_IS_HALF_RECOUT_WIDTH", 12, 12, &umr_bitfield_default }, + { "OBUF_H_2X_COEF_PHASE0_SEL", 16, 16, &umr_bitfield_default }, + { "OBUF_H_2X_COEF_PHASE1_SEL", 24, 24, &umr_bitfield_default }, + { "OBUF_OUT_HOLD_CNT", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL0_OBUF_MEM_PWR_CTRL[] = { + { "OBUF_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default }, + { "OBUF_MEM_PWR_DIS", 2, 2, &umr_bitfield_default }, + { "OBUF_MEM_PWR_STATE", 16, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_CONTROL[] = { + { "CM_BYPASS_EN", 0, 0, &umr_bitfield_default }, + { "CM_UPDATE_PENDING", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_COMA_C11_C12[] = { + { "CM_COMA_C11", 0, 15, &umr_bitfield_default }, + { "CM_COMA_C12", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_COMA_C13_C14[] = { + { "CM_COMA_C13", 0, 15, &umr_bitfield_default }, + { "CM_COMA_C14", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_COMA_C21_C22[] = { + { "CM_COMA_C21", 0, 15, &umr_bitfield_default }, + { "CM_COMA_C22", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_COMA_C23_C24[] = { + { "CM_COMA_C23", 0, 15, &umr_bitfield_default }, + { "CM_COMA_C24", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_COMA_C31_C32[] = { + { "CM_COMA_C31", 0, 15, &umr_bitfield_default }, + { "CM_COMA_C32", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_COMA_C33_C34[] = { + { "CM_COMA_C33", 0, 15, &umr_bitfield_default }, + { "CM_COMA_C34", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_COMB_C11_C12[] = { + { "CM_COMB_C11", 0, 15, &umr_bitfield_default }, + { "CM_COMB_C12", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_COMB_C13_C14[] = { + { "CM_COMB_C13", 0, 15, &umr_bitfield_default }, + { "CM_COMB_C14", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_COMB_C21_C22[] = { + { "CM_COMB_C21", 0, 15, &umr_bitfield_default }, + { "CM_COMB_C22", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_COMB_C23_C24[] = { + { "CM_COMB_C23", 0, 15, &umr_bitfield_default }, + { "CM_COMB_C24", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_COMB_C31_C32[] = { + { "CM_COMB_C31", 0, 15, &umr_bitfield_default }, + { "CM_COMB_C32", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_COMB_C33_C34[] = { + { "CM_COMB_C33", 0, 15, &umr_bitfield_default }, + { "CM_COMB_C34", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_IGAM_CONTROL[] = { + { "CM_IGAM_LUT_MODE", 0, 1, &umr_bitfield_default }, + { "CM_IGAM_LUT_DATA_SIGNED_EN_B", 2, 2, &umr_bitfield_default }, + { "CM_IGAM_LUT_DATA_SIGNED_EN_G", 3, 3, &umr_bitfield_default }, + { "CM_IGAM_LUT_DATA_SIGNED_EN_R", 4, 4, &umr_bitfield_default }, + { "CM_IGAM_LUT_INC_B", 5, 8, &umr_bitfield_default }, + { "CM_IGAM_LUT_INC_G", 9, 12, &umr_bitfield_default }, + { "CM_IGAM_LUT_INC_R", 13, 16, &umr_bitfield_default }, + { "CM_IGAM_LUT_FORMAT_B", 17, 18, &umr_bitfield_default }, + { "CM_IGAM_LUT_FORMAT_G", 19, 20, &umr_bitfield_default }, + { "CM_IGAM_LUT_FORMAT_R", 21, 22, &umr_bitfield_default }, + { "CM_IGAM_LUT_B_FLOAT_POINT_EN", 23, 23, &umr_bitfield_default }, + { "CM_IGAM_LUT_G_FLOAT_POINT_EN", 24, 24, &umr_bitfield_default }, + { "CM_IGAM_LUT_R_FLOAT_POINT_EN", 25, 25, &umr_bitfield_default }, + { "CM_IGAM_INPUT_FORMAT", 26, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_IGAM_LUT_RW_CONTROL[] = { + { "CM_IGAM_LUT_RW_MODE", 0, 0, &umr_bitfield_default }, + { "CM_IGAM_LUT_WRITE_EN_MASK", 4, 6, &umr_bitfield_default }, + { "CM_IGAM_LUT_SEL", 8, 8, &umr_bitfield_default }, + { "CM_IGAM_LUT_HOST_EN", 12, 12, &umr_bitfield_default }, + { "CM_IGAM_DGAM_CONFIG_STATUS", 16, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_IGAM_LUT_RW_INDEX[] = { + { "CM_IGAM_LUT_RW_INDEX", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_IGAM_LUT_SEQ_COLOR[] = { + { "CM_IGAM_LUT_SEQ_COLOR", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_IGAM_LUT_30_COLOR[] = { + { "CM_IGAM_LUT_10_BLUE", 0, 9, &umr_bitfield_default }, + { "CM_IGAM_LUT_10_GREEN", 10, 19, &umr_bitfield_default }, + { "CM_IGAM_LUT_10_RED", 20, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_IGAM_LUT_PWL_DATA[] = { + { "CM_IGAM_LUT_PWL_BASE", 0, 15, &umr_bitfield_default }, + { "CM_IGAM_LUT_PWL_DELTA", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_IGAM_LUT_AUTOFILL[] = { + { "CM_IGAM_LUT_AUTOFILL", 0, 0, &umr_bitfield_default }, + { "CM_IGAM_LUT_AUTOFILL_DONE", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_IGAM_LUT_BW_OFFSET_BLUE[] = { + { "CM_IGAM_LUT_BLACK_OFFSET_BLUE", 0, 15, &umr_bitfield_default }, + { "CM_IGAM_LUT_WHITE_OFFSET_BLUE", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_IGAM_LUT_BW_OFFSET_GREEN[] = { + { "CM_IGAM_LUT_BLACK_OFFSET_GREEN", 0, 15, &umr_bitfield_default }, + { "CM_IGAM_LUT_WHITE_OFFSET_GREEN", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_IGAM_LUT_BW_OFFSET_RED[] = { + { "CM_IGAM_LUT_BLACK_OFFSET_RED", 0, 15, &umr_bitfield_default }, + { "CM_IGAM_LUT_WHITE_OFFSET_RED", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_ICSC_CONTROL[] = { + { "CM_ICSC_MODE", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_ICSC_C11_C12[] = { + { "CM_ICSC_C11", 0, 15, &umr_bitfield_default }, + { "CM_ICSC_C12", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_ICSC_C13_C14[] = { + { "CM_ICSC_C13", 0, 15, &umr_bitfield_default }, + { "CM_ICSC_C14", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_ICSC_C21_C22[] = { + { "CM_ICSC_C21", 0, 15, &umr_bitfield_default }, + { "CM_ICSC_C22", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_ICSC_C23_C24[] = { + { "CM_ICSC_C23", 0, 15, &umr_bitfield_default }, + { "CM_ICSC_C24", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_ICSC_C31_C32[] = { + { "CM_ICSC_C31", 0, 15, &umr_bitfield_default }, + { "CM_ICSC_C32", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_ICSC_C33_C34[] = { + { "CM_ICSC_C33", 0, 15, &umr_bitfield_default }, + { "CM_ICSC_C34", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_GAMUT_REMAP_CONTROL[] = { + { "CM_GAMUT_REMAP_MODE", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_GAMUT_REMAP_C11_C12[] = { + { "CM_GAMUT_REMAP_C11", 0, 15, &umr_bitfield_default }, + { "CM_GAMUT_REMAP_C12", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_GAMUT_REMAP_C13_C14[] = { + { "CM_GAMUT_REMAP_C13", 0, 15, &umr_bitfield_default }, + { "CM_GAMUT_REMAP_C14", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_GAMUT_REMAP_C21_C22[] = { + { "CM_GAMUT_REMAP_C21", 0, 15, &umr_bitfield_default }, + { "CM_GAMUT_REMAP_C22", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_GAMUT_REMAP_C23_C24[] = { + { "CM_GAMUT_REMAP_C23", 0, 15, &umr_bitfield_default }, + { "CM_GAMUT_REMAP_C24", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_GAMUT_REMAP_C31_C32[] = { + { "CM_GAMUT_REMAP_C31", 0, 15, &umr_bitfield_default }, + { "CM_GAMUT_REMAP_C32", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_GAMUT_REMAP_C33_C34[] = { + { "CM_GAMUT_REMAP_C33", 0, 15, &umr_bitfield_default }, + { "CM_GAMUT_REMAP_C34", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_OCSC_CONTROL[] = { + { "CM_OCSC_MODE", 0, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_OCSC_C11_C12[] = { + { "CM_OCSC_C11", 0, 15, &umr_bitfield_default }, + { "CM_OCSC_C12", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_OCSC_C13_C14[] = { + { "CM_OCSC_C13", 0, 15, &umr_bitfield_default }, + { "CM_OCSC_C14", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_OCSC_C21_C22[] = { + { "CM_OCSC_C21", 0, 15, &umr_bitfield_default }, + { "CM_OCSC_C22", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_OCSC_C23_C24[] = { + { "CM_OCSC_C23", 0, 15, &umr_bitfield_default }, + { "CM_OCSC_C24", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_OCSC_C31_C32[] = { + { "CM_OCSC_C31", 0, 15, &umr_bitfield_default }, + { "CM_OCSC_C32", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_OCSC_C33_C34[] = { + { "CM_OCSC_C33", 0, 15, &umr_bitfield_default }, + { "CM_OCSC_C34", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_BNS_VALUES_R[] = { + { "CM_BNS_BIAS_R", 0, 15, &umr_bitfield_default }, + { "CM_BNS_SCALE_R", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_BNS_VALUES_G[] = { + { "CM_BNS_BIAS_G", 0, 15, &umr_bitfield_default }, + { "CM_BNS_SCALE_G", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_BNS_VALUES_B[] = { + { "CM_BNS_BIAS_B", 0, 15, &umr_bitfield_default }, + { "CM_BNS_SCALE_B", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_DGAM_CONTROL[] = { + { "CM_DGAM_LUT_MODE", 0, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_DGAM_LUT_INDEX[] = { + { "CM_DGAM_LUT_INDEX", 0, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_DGAM_LUT_DATA[] = { + { "CM_DGAM_LUT_DATA", 0, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_DGAM_LUT_WRITE_EN_MASK[] = { + { "CM_DGAM_LUT_WRITE_EN_MASK", 0, 2, &umr_bitfield_default }, + { "CM_DGAM_LUT_WRITE_SEL", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_DGAM_RAMA_START_CNTL_B[] = { + { "CM_DGAM_RAMA_EXP_REGION_START_B", 0, 17, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B", 20, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_DGAM_RAMA_START_CNTL_G[] = { + { "CM_DGAM_RAMA_EXP_REGION_START_G", 0, 17, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G", 20, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_DGAM_RAMA_START_CNTL_R[] = { + { "CM_DGAM_RAMA_EXP_REGION_START_R", 0, 17, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R", 20, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_B[] = { + { "CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_G[] = { + { "CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_R[] = { + { "CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_DGAM_RAMA_END_CNTL1_B[] = { + { "CM_DGAM_RAMA_EXP_REGION_END_B", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_DGAM_RAMA_END_CNTL2_B[] = { + { "CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B", 0, 15, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION_END_BASE_B", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_DGAM_RAMA_END_CNTL1_G[] = { + { "CM_DGAM_RAMA_EXP_REGION_END_G", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_DGAM_RAMA_END_CNTL2_G[] = { + { "CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G", 0, 15, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION_END_BASE_G", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_DGAM_RAMA_END_CNTL1_R[] = { + { "CM_DGAM_RAMA_EXP_REGION_END_R", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_DGAM_RAMA_END_CNTL2_R[] = { + { "CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R", 0, 15, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION_END_BASE_R", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_DGAM_RAMA_REGION_0_1[] = { + { "CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_DGAM_RAMA_REGION_2_3[] = { + { "CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_DGAM_RAMA_REGION_4_5[] = { + { "CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_DGAM_RAMA_REGION_6_7[] = { + { "CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_DGAM_RAMA_REGION_8_9[] = { + { "CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_DGAM_RAMA_REGION_10_11[] = { + { "CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_DGAM_RAMA_REGION_12_13[] = { + { "CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_DGAM_RAMA_REGION_14_15[] = { + { "CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_DGAM_RAMB_START_CNTL_B[] = { + { "CM_DGAM_RAMB_EXP_REGION_START_B", 0, 17, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B", 20, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_DGAM_RAMB_START_CNTL_G[] = { + { "CM_DGAM_RAMB_EXP_REGION_START_G", 0, 17, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G", 20, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_DGAM_RAMB_START_CNTL_R[] = { + { "CM_DGAM_RAMB_EXP_REGION_START_R", 0, 17, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R", 20, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_B[] = { + { "CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_G[] = { + { "CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_R[] = { + { "CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_DGAM_RAMB_END_CNTL1_B[] = { + { "CM_DGAM_RAMB_EXP_REGION_END_B", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_DGAM_RAMB_END_CNTL2_B[] = { + { "CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B", 0, 15, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION_END_BASE_B", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_DGAM_RAMB_END_CNTL1_G[] = { + { "CM_DGAM_RAMB_EXP_REGION_END_G", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_DGAM_RAMB_END_CNTL2_G[] = { + { "CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G", 0, 15, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION_END_BASE_G", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_DGAM_RAMB_END_CNTL1_R[] = { + { "CM_DGAM_RAMB_EXP_REGION_END_R", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_DGAM_RAMB_END_CNTL2_R[] = { + { "CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R", 0, 15, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION_END_BASE_R", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_DGAM_RAMB_REGION_0_1[] = { + { "CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_DGAM_RAMB_REGION_2_3[] = { + { "CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_DGAM_RAMB_REGION_4_5[] = { + { "CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_DGAM_RAMB_REGION_6_7[] = { + { "CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_DGAM_RAMB_REGION_8_9[] = { + { "CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_DGAM_RAMB_REGION_10_11[] = { + { "CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_DGAM_RAMB_REGION_12_13[] = { + { "CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_DGAM_RAMB_REGION_14_15[] = { + { "CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_RGAM_CONTROL[] = { + { "CM_RGAM_LUT_MODE", 0, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_RGAM_LUT_INDEX[] = { + { "CM_RGAM_LUT_INDEX", 0, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_RGAM_LUT_DATA[] = { + { "CM_RGAM_LUT_DATA", 0, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_RGAM_LUT_WRITE_EN_MASK[] = { + { "CM_RGAM_LUT_WRITE_EN_MASK", 0, 2, &umr_bitfield_default }, + { "CM_RGAM_LUT_WRITE_SEL", 4, 4, &umr_bitfield_default }, + { "CM_RGAM_CONFIG_STATUS", 8, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_RGAM_RAMA_START_CNTL_B[] = { + { "CM_RGAM_RAMA_EXP_REGION_START_B", 0, 17, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_B", 20, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_RGAM_RAMA_START_CNTL_G[] = { + { "CM_RGAM_RAMA_EXP_REGION_START_G", 0, 17, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_G", 20, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_RGAM_RAMA_START_CNTL_R[] = { + { "CM_RGAM_RAMA_EXP_REGION_START_R", 0, 17, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_R", 20, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_B[] = { + { "CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_G[] = { + { "CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_R[] = { + { "CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_RGAM_RAMA_END_CNTL1_B[] = { + { "CM_RGAM_RAMA_EXP_REGION_END_B", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_RGAM_RAMA_END_CNTL2_B[] = { + { "CM_RGAM_RAMA_EXP_REGION_END_SLOPE_B", 0, 15, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION_END_BASE_B", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_RGAM_RAMA_END_CNTL1_G[] = { + { "CM_RGAM_RAMA_EXP_REGION_END_G", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_RGAM_RAMA_END_CNTL2_G[] = { + { "CM_RGAM_RAMA_EXP_REGION_END_SLOPE_G", 0, 15, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION_END_BASE_G", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_RGAM_RAMA_END_CNTL1_R[] = { + { "CM_RGAM_RAMA_EXP_REGION_END_R", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_RGAM_RAMA_END_CNTL2_R[] = { + { "CM_RGAM_RAMA_EXP_REGION_END_SLOPE_R", 0, 15, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION_END_BASE_R", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_RGAM_RAMA_REGION_0_1[] = { + { "CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_RGAM_RAMA_REGION_2_3[] = { + { "CM_RGAM_RAMA_EXP_REGION2_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION2_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION3_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION3_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_RGAM_RAMA_REGION_4_5[] = { + { "CM_RGAM_RAMA_EXP_REGION4_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION4_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION5_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION5_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_RGAM_RAMA_REGION_6_7[] = { + { "CM_RGAM_RAMA_EXP_REGION6_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION6_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION7_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION7_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_RGAM_RAMA_REGION_8_9[] = { + { "CM_RGAM_RAMA_EXP_REGION8_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION8_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION9_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION9_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_RGAM_RAMA_REGION_10_11[] = { + { "CM_RGAM_RAMA_EXP_REGION10_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION10_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION11_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION11_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_RGAM_RAMA_REGION_12_13[] = { + { "CM_RGAM_RAMA_EXP_REGION12_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION12_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION13_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION13_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_RGAM_RAMA_REGION_14_15[] = { + { "CM_RGAM_RAMA_EXP_REGION14_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION14_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION15_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION15_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_RGAM_RAMA_REGION_16_17[] = { + { "CM_RGAM_RAMA_EXP_REGION16_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION16_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION17_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION17_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_RGAM_RAMA_REGION_18_19[] = { + { "CM_RGAM_RAMA_EXP_REGION18_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION18_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION19_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION19_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_RGAM_RAMA_REGION_20_21[] = { + { "CM_RGAM_RAMA_EXP_REGION20_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION20_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION21_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION21_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_RGAM_RAMA_REGION_22_23[] = { + { "CM_RGAM_RAMA_EXP_REGION22_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION22_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION23_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION23_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_RGAM_RAMA_REGION_24_25[] = { + { "CM_RGAM_RAMA_EXP_REGION24_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION24_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION25_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION25_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_RGAM_RAMA_REGION_26_27[] = { + { "CM_RGAM_RAMA_EXP_REGION26_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION26_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION27_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION27_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_RGAM_RAMA_REGION_28_29[] = { + { "CM_RGAM_RAMA_EXP_REGION28_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION28_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION29_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION29_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_RGAM_RAMA_REGION_30_31[] = { + { "CM_RGAM_RAMA_EXP_REGION30_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION30_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION31_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION31_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_RGAM_RAMA_REGION_32_33[] = { + { "CM_RGAM_RAMA_EXP_REGION32_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION32_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_RGAM_RAMB_START_CNTL_B[] = { + { "CM_RGAM_RAMB_EXP_REGION_START_B", 0, 17, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B", 20, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_RGAM_RAMB_START_CNTL_G[] = { + { "CM_RGAM_RAMB_EXP_REGION_START_G", 0, 17, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_G", 20, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_RGAM_RAMB_START_CNTL_R[] = { + { "CM_RGAM_RAMB_EXP_REGION_START_R", 0, 17, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_R", 20, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_B[] = { + { "CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_G[] = { + { "CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_R[] = { + { "CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_RGAM_RAMB_END_CNTL1_B[] = { + { "CM_RGAM_RAMB_EXP_REGION_END_B", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_RGAM_RAMB_END_CNTL2_B[] = { + { "CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B", 0, 15, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION_END_BASE_B", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_RGAM_RAMB_END_CNTL1_G[] = { + { "CM_RGAM_RAMB_EXP_REGION_END_G", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_RGAM_RAMB_END_CNTL2_G[] = { + { "CM_RGAM_RAMB_EXP_REGION_END_SLOPE_G", 0, 15, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION_END_BASE_G", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_RGAM_RAMB_END_CNTL1_R[] = { + { "CM_RGAM_RAMB_EXP_REGION_END_R", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_RGAM_RAMB_END_CNTL2_R[] = { + { "CM_RGAM_RAMB_EXP_REGION_END_SLOPE_R", 0, 15, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION_END_BASE_R", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_RGAM_RAMB_REGION_0_1[] = { + { "CM_RGAM_RAMB_EXP_REGION0_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION0_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION1_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION1_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_RGAM_RAMB_REGION_2_3[] = { + { "CM_RGAM_RAMB_EXP_REGION2_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION2_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION3_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION3_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_RGAM_RAMB_REGION_4_5[] = { + { "CM_RGAM_RAMB_EXP_REGION4_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION4_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION5_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION5_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_RGAM_RAMB_REGION_6_7[] = { + { "CM_RGAM_RAMB_EXP_REGION6_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION6_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION7_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION7_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_RGAM_RAMB_REGION_8_9[] = { + { "CM_RGAM_RAMB_EXP_REGION8_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION8_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION9_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION9_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_RGAM_RAMB_REGION_10_11[] = { + { "CM_RGAM_RAMB_EXP_REGION10_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION10_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION11_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION11_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_RGAM_RAMB_REGION_12_13[] = { + { "CM_RGAM_RAMB_EXP_REGION12_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION12_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION13_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION13_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_RGAM_RAMB_REGION_14_15[] = { + { "CM_RGAM_RAMB_EXP_REGION14_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION14_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION15_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION15_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_RGAM_RAMB_REGION_16_17[] = { + { "CM_RGAM_RAMB_EXP_REGION16_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION16_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION17_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION17_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_RGAM_RAMB_REGION_18_19[] = { + { "CM_RGAM_RAMB_EXP_REGION18_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION18_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION19_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION19_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_RGAM_RAMB_REGION_20_21[] = { + { "CM_RGAM_RAMB_EXP_REGION20_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION20_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION21_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION21_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_RGAM_RAMB_REGION_22_23[] = { + { "CM_RGAM_RAMB_EXP_REGION22_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION22_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION23_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION23_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_RGAM_RAMB_REGION_24_25[] = { + { "CM_RGAM_RAMB_EXP_REGION24_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION24_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION25_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION25_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_RGAM_RAMB_REGION_26_27[] = { + { "CM_RGAM_RAMB_EXP_REGION26_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION26_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION27_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION27_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_RGAM_RAMB_REGION_28_29[] = { + { "CM_RGAM_RAMB_EXP_REGION28_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION28_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION29_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION29_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_RGAM_RAMB_REGION_30_31[] = { + { "CM_RGAM_RAMB_EXP_REGION30_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION30_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION31_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION31_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_RGAM_RAMB_REGION_32_33[] = { + { "CM_RGAM_RAMB_EXP_REGION32_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION32_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION33_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION33_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_HDR_MULT_COEF[] = { + { "CM_HDR_MULT_COEF", 0, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_RANGE_CLAMP_CONTROL_R[] = { + { "CM_RANGE_CLAMP_MAX_R", 0, 15, &umr_bitfield_default }, + { "CM_RANGE_CLAMP_MIN_R", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_RANGE_CLAMP_CONTROL_G[] = { + { "CM_RANGE_CLAMP_MAX_G", 0, 15, &umr_bitfield_default }, + { "CM_RANGE_CLAMP_MIN_G", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_RANGE_CLAMP_CONTROL_B[] = { + { "CM_RANGE_CLAMP_MAX_B", 0, 15, &umr_bitfield_default }, + { "CM_RANGE_CLAMP_MIN_B", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_DENORM_CONTROL[] = { + { "CM_DENORM_MODE", 0, 2, &umr_bitfield_default }, + { "CM_DENORM_ROUND_CLAMP", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_CMOUT_CONTROL[] = { + { "CM_CMOUT_ROUND_TRUNC_MODE", 0, 3, &umr_bitfield_default }, + { "CM_CMOUT_SPATIAL_DITHER_EN", 4, 4, &umr_bitfield_default }, + { "CM_CMOUT_SPATIAL_DITHER_MODE", 8, 9, &umr_bitfield_default }, + { "CM_CMOUT_SPATIAL_DITHER_DEPTH", 12, 13, &umr_bitfield_default }, + { "CM_CMOUT_FRAME_RANDOM_ENABLE", 16, 16, &umr_bitfield_default }, + { "CM_CMOUT_RGB_RANDOM_EN", 20, 20, &umr_bitfield_default }, + { "CM_CMOUT_HIGHPASS_RANDOM_ENABLE", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_CMOUT_RANDOM_SEEDS[] = { + { "CM_CMOUT_RAND_R_SEED", 0, 7, &umr_bitfield_default }, + { "CM_CMOUT_RAND_G_SEED", 8, 15, &umr_bitfield_default }, + { "CM_CMOUT_RAND_B_SEED", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_MEM_PWR_CTRL[] = { + { "SHARED_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default }, + { "SHARED_MEM_PWR_DIS", 2, 2, &umr_bitfield_default }, + { "RGAM_MEM_PWR_FORCE", 4, 5, &umr_bitfield_default }, + { "RGAM_MEM_PWR_DIS", 6, 6, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM0_CM_MEM_PWR_STATUS[] = { + { "SHARED_MEM_PWR_STATE", 0, 1, &umr_bitfield_default }, + { "RGAM_MEM_PWR_STATE", 2, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON12_PERFCOUNTER_CNTL[] = { + { "PERFCOUNTER_EVENT_SEL", 0, 8, &umr_bitfield_default }, + { "PERFCOUNTER_CVALUE_SEL", 9, 11, &umr_bitfield_default }, + { "PERFCOUNTER_INC_MODE", 12, 14, &umr_bitfield_default }, + { "PERFCOUNTER_HW_CNTL_SEL", 15, 15, &umr_bitfield_default }, + { "PERFCOUNTER_RUNEN_MODE", 16, 16, &umr_bitfield_default }, + { "PERFCOUNTER_CNTOFF_START_DIS", 22, 22, &umr_bitfield_default }, + { "PERFCOUNTER_RESTART_EN", 23, 23, &umr_bitfield_default }, + { "PERFCOUNTER_INT_EN", 24, 24, &umr_bitfield_default }, + { "PERFCOUNTER_OFF_MASK", 25, 25, &umr_bitfield_default }, + { "PERFCOUNTER_ACTIVE", 26, 26, &umr_bitfield_default }, + { "PERFCOUNTER_CNTL_SEL", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON12_PERFCOUNTER_CNTL2[] = { + { "PERFCOUNTER_COUNTED_VALUE_TYPE", 0, 1, &umr_bitfield_default }, + { "PERFCOUNTER_HW_STOP1_SEL", 2, 2, &umr_bitfield_default }, + { "PERFCOUNTER_HW_STOP2_SEL", 3, 3, &umr_bitfield_default }, + { "PERFCOUNTER_CNTOFF_SEL", 8, 13, &umr_bitfield_default }, + { "PERFCOUNTER_CNTL2_SEL", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON12_PERFCOUNTER_STATE[] = { + { "PERFCOUNTER_CNT0_STATE", 0, 1, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL0", 2, 2, &umr_bitfield_default }, + { "PERFCOUNTER_CNT1_STATE", 4, 5, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL1", 6, 6, &umr_bitfield_default }, + { "PERFCOUNTER_CNT2_STATE", 8, 9, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL2", 10, 10, &umr_bitfield_default }, + { "PERFCOUNTER_CNT3_STATE", 12, 13, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL3", 14, 14, &umr_bitfield_default }, + { "PERFCOUNTER_CNT4_STATE", 16, 17, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL4", 18, 18, &umr_bitfield_default }, + { "PERFCOUNTER_CNT5_STATE", 20, 21, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL5", 22, 22, &umr_bitfield_default }, + { "PERFCOUNTER_CNT6_STATE", 24, 25, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL6", 26, 26, &umr_bitfield_default }, + { "PERFCOUNTER_CNT7_STATE", 28, 29, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL7", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON12_PERFMON_CNTL[] = { + { "PERFMON_STATE", 0, 1, &umr_bitfield_default }, + { "PERFMON_RPT_COUNT", 8, 27, &umr_bitfield_default }, + { "PERFMON_CNTOFF_AND_OR", 28, 28, &umr_bitfield_default }, + { "PERFMON_CNTOFF_INT_EN", 29, 29, &umr_bitfield_default }, + { "PERFMON_CNTOFF_INT_STATUS", 30, 30, &umr_bitfield_default }, + { "PERFMON_CNTOFF_INT_ACK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON12_PERFMON_CNTL2[] = { + { "PERFMON_CNTOFF_INT_TYPE", 0, 0, &umr_bitfield_default }, + { "PERFMON_CLK_ENABLE", 1, 1, &umr_bitfield_default }, + { "PERFMON_RUN_ENABLE_START_SEL", 2, 9, &umr_bitfield_default }, + { "PERFMON_RUN_ENABLE_STOP_SEL", 10, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC[] = { + { "PERFCOUNTER_INT0_STATUS", 0, 0, &umr_bitfield_default }, + { "PERFCOUNTER_INT1_STATUS", 1, 1, &umr_bitfield_default }, + { "PERFCOUNTER_INT2_STATUS", 2, 2, &umr_bitfield_default }, + { "PERFCOUNTER_INT3_STATUS", 3, 3, &umr_bitfield_default }, + { "PERFCOUNTER_INT4_STATUS", 4, 4, &umr_bitfield_default }, + { "PERFCOUNTER_INT5_STATUS", 5, 5, &umr_bitfield_default }, + { "PERFCOUNTER_INT6_STATUS", 6, 6, &umr_bitfield_default }, + { "PERFCOUNTER_INT7_STATUS", 7, 7, &umr_bitfield_default }, + { "PERFCOUNTER_INT0_ACK", 8, 8, &umr_bitfield_default }, + { "PERFCOUNTER_INT1_ACK", 9, 9, &umr_bitfield_default }, + { "PERFCOUNTER_INT2_ACK", 10, 10, &umr_bitfield_default }, + { "PERFCOUNTER_INT3_ACK", 11, 11, &umr_bitfield_default }, + { "PERFCOUNTER_INT4_ACK", 12, 12, &umr_bitfield_default }, + { "PERFCOUNTER_INT5_ACK", 13, 13, &umr_bitfield_default }, + { "PERFCOUNTER_INT6_ACK", 14, 14, &umr_bitfield_default }, + { "PERFCOUNTER_INT7_ACK", 15, 15, &umr_bitfield_default }, + { "PERFMON_CVALUE_HI", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON12_PERFMON_CVALUE_LOW[] = { + { "PERFMON_CVALUE_LOW", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON12_PERFMON_HI[] = { + { "PERFMON_HI", 0, 15, &umr_bitfield_default }, + { "PERFMON_READ_SEL", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON12_PERFMON_LOW[] = { + { "PERFMON_LOW", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDPP_TOP1_DPP_CONTROL[] = { + { "DPP_CLOCK_ENABLE", 4, 4, &umr_bitfield_default }, + { "DPPCLK_G_GATE_DISABLE", 8, 8, &umr_bitfield_default }, + { "DPPCLK_G_DYN_GATE_DISABLE", 10, 10, &umr_bitfield_default }, + { "DPPCLK_G_DSCL_GATE_DISABLE", 12, 12, &umr_bitfield_default }, + { "DPPCLK_R_GATE_DISABLE", 16, 16, &umr_bitfield_default }, + { "DISPCLK_R_GATE_DISABLE", 18, 18, &umr_bitfield_default }, + { "DISPCLK_G_GATE_DISABLE", 20, 20, &umr_bitfield_default }, + { "DPPCLK_RATE_CONTROL", 24, 24, &umr_bitfield_default }, + { "DPP_TEST_CLK_SEL", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDPP_TOP1_DPP_SOFT_RESET[] = { + { "CNVC_SOFT_RESET", 0, 0, &umr_bitfield_default }, + { "DSCL_SOFT_RESET", 4, 4, &umr_bitfield_default }, + { "CM_SOFT_RESET", 8, 8, &umr_bitfield_default }, + { "OBUF_SOFT_RESET", 12, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDPP_TOP1_DPP_CRC_VAL_R_G[] = { + { "DPP_CRC_R_CR", 0, 15, &umr_bitfield_default }, + { "DPP_CRC_G_Y", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDPP_TOP1_DPP_CRC_VAL_B_A[] = { + { "DPP_CRC_B_CB", 0, 15, &umr_bitfield_default }, + { "DPP_CRC_ALPHA", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDPP_TOP1_DPP_CRC_CTRL[] = { + { "DPP_CRC_EN", 0, 0, &umr_bitfield_default }, + { "DPP_CRC_CONT_EN", 1, 1, &umr_bitfield_default }, + { "DPP_CRC_ONE_SHOT_PENDING", 2, 2, &umr_bitfield_default }, + { "DPP_CRC_420_COMP_SEL", 3, 3, &umr_bitfield_default }, + { "DPP_CRC_SRC_SEL", 4, 5, &umr_bitfield_default }, + { "DPP_CRC_STEREO_EN", 7, 7, &umr_bitfield_default }, + { "DPP_CRC_STEREO_MODE", 8, 9, &umr_bitfield_default }, + { "DPP_CRC_INTERLACE_MODE", 10, 11, &umr_bitfield_default }, + { "DPP_CRC_PIX_FORMAT_SEL", 12, 14, &umr_bitfield_default }, + { "DPP_CRC_CURSOR_FORMAT_SEL", 15, 15, &umr_bitfield_default }, + { "DPP_CRC_MASK", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDPP_TOP1_HOST_READ_CONTROL[] = { + { "HOST_READ_RATE_CONTROL", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT[] = { + { "CNVC_SURFACE_PIXEL_FORMAT", 0, 6, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNVC_CFG1_FORMAT_CONTROL[] = { + { "FORMAT_EXPANSION_MODE", 0, 0, &umr_bitfield_default }, + { "FORMAT_CNV16", 4, 4, &umr_bitfield_default }, + { "ALPHA_EN", 8, 8, &umr_bitfield_default }, + { "CNVC_BYPASS", 12, 12, &umr_bitfield_default }, + { "OUTPUT_FP", 16, 16, &umr_bitfield_default }, + { "CNVC_UPDATE_PENDING", 20, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNVC_CFG1_FCNV_FP_SCALE_BIAS[] = { + { "FCNV_FP_SCALE", 0, 15, &umr_bitfield_default }, + { "FCNV_FP_BIAS", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNVC_CFG1_DENORM_CONTROL[] = { + { "DENORM_SCALE", 0, 14, &umr_bitfield_default }, + { "CLAMP_POSITIVE", 15, 15, &umr_bitfield_default }, + { "DENORM_BIAS", 16, 30, &umr_bitfield_default }, + { "DENORM_TRUNCATE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNVC_CFG1_COLOR_KEYER_CONTROL[] = { + { "COLOR_KEYER_EN", 0, 0, &umr_bitfield_default }, + { "COLOR_KEYER_MODE", 4, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNVC_CFG1_COLOR_KEYER_ALPHA[] = { + { "COLOR_KEYER_ALPHA_LOW", 0, 15, &umr_bitfield_default }, + { "COLOR_KEYER_ALPHA_HIGH", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNVC_CFG1_COLOR_KEYER_RED[] = { + { "COLOR_KEYER_RED_LOW", 0, 15, &umr_bitfield_default }, + { "COLOR_KEYER_RED_HIGH", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNVC_CFG1_COLOR_KEYER_GREEN[] = { + { "COLOR_KEYER_GREEN_LOW", 0, 15, &umr_bitfield_default }, + { "COLOR_KEYER_GREEN_HIGH", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNVC_CFG1_COLOR_KEYER_BLUE[] = { + { "COLOR_KEYER_BLUE_LOW", 0, 15, &umr_bitfield_default }, + { "COLOR_KEYER_BLUE_HIGH", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNVC_CUR1_CURSOR0_CONTROL[] = { + { "CUR0_ENABLE", 0, 0, &umr_bitfield_default }, + { "CUR0_EXPANSION_MODE", 1, 1, &umr_bitfield_default }, + { "CUR0_INVERT_MODE", 2, 2, &umr_bitfield_default }, + { "CUR0_MODE", 4, 5, &umr_bitfield_default }, + { "CUR0_UPDATE_PENDING", 6, 6, &umr_bitfield_default }, + { "CUR0_MAX", 8, 19, &umr_bitfield_default }, + { "CUR0_MIN", 20, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNVC_CUR1_CURSOR0_COLOR0[] = { + { "CUR0_COLOR0", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNVC_CUR1_CURSOR0_COLOR1[] = { + { "CUR0_COLOR1", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS[] = { + { "CUR0_FP_SCALE", 0, 15, &umr_bitfield_default }, + { "CUR0_FP_BIAS", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL1_SCL_COEF_RAM_TAP_SELECT[] = { + { "SCL_COEF_RAM_TAP_PAIR_IDX", 0, 1, &umr_bitfield_default }, + { "SCL_COEF_RAM_PHASE", 8, 13, &umr_bitfield_default }, + { "SCL_COEF_RAM_FILTER_TYPE", 16, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL1_SCL_COEF_RAM_TAP_DATA[] = { + { "SCL_COEF_RAM_EVEN_TAP_COEF", 0, 13, &umr_bitfield_default }, + { "SCL_COEF_RAM_EVEN_TAP_COEF_EN", 15, 15, &umr_bitfield_default }, + { "SCL_COEF_RAM_ODD_TAP_COEF", 16, 29, &umr_bitfield_default }, + { "SCL_COEF_RAM_ODD_TAP_COEF_EN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL1_SCL_MODE[] = { + { "DSCL_MODE", 0, 2, &umr_bitfield_default }, + { "SCL_COEF_RAM_SELECT", 8, 8, &umr_bitfield_default }, + { "SCL_COEF_RAM_SELECT_CURRENT", 12, 12, &umr_bitfield_default }, + { "SCL_CHROMA_COEF_MODE", 16, 16, &umr_bitfield_default }, + { "SCL_ALPHA_COEF_MODE", 20, 20, &umr_bitfield_default }, + { "SCL_COEF_RAM_SELECT_RD", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL1_SCL_TAP_CONTROL[] = { + { "SCL_V_NUM_TAPS", 0, 2, &umr_bitfield_default }, + { "SCL_H_NUM_TAPS", 4, 6, &umr_bitfield_default }, + { "SCL_V_NUM_TAPS_C", 8, 10, &umr_bitfield_default }, + { "SCL_H_NUM_TAPS_C", 12, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL1_DSCL_CONTROL[] = { + { "SCL_BOUNDARY_MODE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL1_DSCL_2TAP_CONTROL[] = { + { "SCL_H_2TAP_HARDCODE_COEF_EN", 0, 0, &umr_bitfield_default }, + { "SCL_H_2TAP_SHARP_EN", 4, 4, &umr_bitfield_default }, + { "SCL_H_2TAP_SHARP_FACTOR", 8, 10, &umr_bitfield_default }, + { "SCL_V_2TAP_HARDCODE_COEF_EN", 16, 16, &umr_bitfield_default }, + { "SCL_V_2TAP_SHARP_EN", 20, 20, &umr_bitfield_default }, + { "SCL_V_2TAP_SHARP_FACTOR", 24, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL[] = { + { "SCL_V_MANUAL_REPLICATE_FACTOR", 0, 3, &umr_bitfield_default }, + { "SCL_H_MANUAL_REPLICATE_FACTOR", 8, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO[] = { + { "SCL_H_SCALE_RATIO", 0, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL1_SCL_HORZ_FILTER_INIT[] = { + { "SCL_H_INIT_FRAC", 0, 23, &umr_bitfield_default }, + { "SCL_H_INIT_INT", 24, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C[] = { + { "SCL_H_SCALE_RATIO_C", 0, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL1_SCL_HORZ_FILTER_INIT_C[] = { + { "SCL_H_INIT_FRAC_C", 0, 23, &umr_bitfield_default }, + { "SCL_H_INIT_INT_C", 24, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO[] = { + { "SCL_V_SCALE_RATIO", 0, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL1_SCL_VERT_FILTER_INIT[] = { + { "SCL_V_INIT_FRAC", 0, 23, &umr_bitfield_default }, + { "SCL_V_INIT_INT", 24, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL1_SCL_VERT_FILTER_INIT_BOT[] = { + { "SCL_V_INIT_FRAC_BOT", 0, 23, &umr_bitfield_default }, + { "SCL_V_INIT_INT_BOT", 24, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C[] = { + { "SCL_V_SCALE_RATIO_C", 0, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL1_SCL_VERT_FILTER_INIT_C[] = { + { "SCL_V_INIT_FRAC_C", 0, 23, &umr_bitfield_default }, + { "SCL_V_INIT_INT_C", 24, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C[] = { + { "SCL_V_INIT_FRAC_BOT_C", 0, 23, &umr_bitfield_default }, + { "SCL_V_INIT_INT_BOT_C", 24, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL1_SCL_BLACK_OFFSET[] = { + { "SCL_BLACK_OFFSET_RGB_Y", 0, 15, &umr_bitfield_default }, + { "SCL_BLACK_OFFSET_CBCR", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL1_DSCL_UPDATE[] = { + { "SCL_UPDATE_PENDING", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL1_DSCL_AUTOCAL[] = { + { "AUTOCAL_MODE", 0, 1, &umr_bitfield_default }, + { "AUTOCAL_NUM_PIPE", 8, 9, &umr_bitfield_default }, + { "AUTOCAL_PIPE_ID", 12, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT[] = { + { "EXT_OVERSCAN_RIGHT", 0, 12, &umr_bitfield_default }, + { "EXT_OVERSCAN_LEFT", 16, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM[] = { + { "EXT_OVERSCAN_BOTTOM", 0, 12, &umr_bitfield_default }, + { "EXT_OVERSCAN_TOP", 16, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL1_OTG_H_BLANK[] = { + { "OTG_H_BLANK_START", 0, 13, &umr_bitfield_default }, + { "OTG_H_BLANK_END", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL1_OTG_V_BLANK[] = { + { "OTG_V_BLANK_START", 0, 13, &umr_bitfield_default }, + { "OTG_V_BLANK_END", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL1_RECOUT_START[] = { + { "RECOUT_START_X", 0, 12, &umr_bitfield_default }, + { "RECOUT_START_Y", 16, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL1_RECOUT_SIZE[] = { + { "RECOUT_WIDTH", 0, 13, &umr_bitfield_default }, + { "RECOUT_HEIGHT", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL1_MPC_SIZE[] = { + { "MPC_WIDTH", 0, 13, &umr_bitfield_default }, + { "MPC_HEIGHT", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL1_LB_DATA_FORMAT[] = { + { "PIXEL_DEPTH", 0, 1, &umr_bitfield_default }, + { "PIXEL_EXPAN_MODE", 8, 8, &umr_bitfield_default }, + { "PIXEL_REDUCE_MODE", 12, 12, &umr_bitfield_default }, + { "DYNAMIC_PIXEL_DEPTH", 16, 16, &umr_bitfield_default }, + { "DITHER_EN", 20, 20, &umr_bitfield_default }, + { "INTERLEAVE_EN", 24, 24, &umr_bitfield_default }, + { "ALPHA_EN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL1_LB_MEMORY_CTRL[] = { + { "MEMORY_CONFIG", 0, 1, &umr_bitfield_default }, + { "LB_MAX_PARTITIONS", 8, 13, &umr_bitfield_default }, + { "LB_NUM_PARTITIONS", 16, 22, &umr_bitfield_default }, + { "LB_NUM_PARTITIONS_C", 24, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL1_LB_V_COUNTER[] = { + { "V_COUNTER", 0, 12, &umr_bitfield_default }, + { "V_COUNTER_C", 16, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL1_DSCL_MEM_PWR_CTRL[] = { + { "LUT_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default }, + { "LUT_MEM_PWR_DIS", 2, 2, &umr_bitfield_default }, + { "LB_G1_MEM_PWR_FORCE", 4, 5, &umr_bitfield_default }, + { "LB_G1_MEM_PWR_DIS", 6, 6, &umr_bitfield_default }, + { "LB_G2_MEM_PWR_FORCE", 8, 9, &umr_bitfield_default }, + { "LB_G2_MEM_PWR_DIS", 10, 10, &umr_bitfield_default }, + { "LB_G3_MEM_PWR_FORCE", 12, 13, &umr_bitfield_default }, + { "LB_G3_MEM_PWR_DIS", 14, 14, &umr_bitfield_default }, + { "LB_G4_MEM_PWR_FORCE", 16, 17, &umr_bitfield_default }, + { "LB_G4_MEM_PWR_DIS", 18, 18, &umr_bitfield_default }, + { "LB_G5_MEM_PWR_FORCE", 20, 21, &umr_bitfield_default }, + { "LB_G5_MEM_PWR_DIS", 22, 22, &umr_bitfield_default }, + { "LB_G6_MEM_PWR_FORCE", 24, 25, &umr_bitfield_default }, + { "LB_G6_MEM_PWR_DIS", 26, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL1_DSCL_MEM_PWR_STATUS[] = { + { "LUT_MEM_PWR_STATE", 0, 1, &umr_bitfield_default }, + { "LB_G1_MEM_PWR_STATE", 2, 3, &umr_bitfield_default }, + { "LB_G2_MEM_PWR_STATE", 4, 5, &umr_bitfield_default }, + { "LB_G3_MEM_PWR_STATE", 6, 7, &umr_bitfield_default }, + { "LB_G4_MEM_PWR_STATE", 8, 9, &umr_bitfield_default }, + { "LB_G5_MEM_PWR_STATE", 10, 11, &umr_bitfield_default }, + { "LB_G6_MEM_PWR_STATE", 12, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL1_OBUF_CONTROL[] = { + { "OBUF_BYPASS", 0, 0, &umr_bitfield_default }, + { "OBUF_USE_FULL_BUFFER", 4, 4, &umr_bitfield_default }, + { "OBUF_H_2X_UPSCALE_EN", 8, 8, &umr_bitfield_default }, + { "OBUF_IS_HALF_RECOUT_WIDTH", 12, 12, &umr_bitfield_default }, + { "OBUF_H_2X_COEF_PHASE0_SEL", 16, 16, &umr_bitfield_default }, + { "OBUF_H_2X_COEF_PHASE1_SEL", 24, 24, &umr_bitfield_default }, + { "OBUF_OUT_HOLD_CNT", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL1_OBUF_MEM_PWR_CTRL[] = { + { "OBUF_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default }, + { "OBUF_MEM_PWR_DIS", 2, 2, &umr_bitfield_default }, + { "OBUF_MEM_PWR_STATE", 16, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_CONTROL[] = { + { "CM_BYPASS_EN", 0, 0, &umr_bitfield_default }, + { "CM_UPDATE_PENDING", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_COMA_C11_C12[] = { + { "CM_COMA_C11", 0, 15, &umr_bitfield_default }, + { "CM_COMA_C12", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_COMA_C13_C14[] = { + { "CM_COMA_C13", 0, 15, &umr_bitfield_default }, + { "CM_COMA_C14", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_COMA_C21_C22[] = { + { "CM_COMA_C21", 0, 15, &umr_bitfield_default }, + { "CM_COMA_C22", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_COMA_C23_C24[] = { + { "CM_COMA_C23", 0, 15, &umr_bitfield_default }, + { "CM_COMA_C24", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_COMA_C31_C32[] = { + { "CM_COMA_C31", 0, 15, &umr_bitfield_default }, + { "CM_COMA_C32", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_COMA_C33_C34[] = { + { "CM_COMA_C33", 0, 15, &umr_bitfield_default }, + { "CM_COMA_C34", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_COMB_C11_C12[] = { + { "CM_COMB_C11", 0, 15, &umr_bitfield_default }, + { "CM_COMB_C12", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_COMB_C13_C14[] = { + { "CM_COMB_C13", 0, 15, &umr_bitfield_default }, + { "CM_COMB_C14", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_COMB_C21_C22[] = { + { "CM_COMB_C21", 0, 15, &umr_bitfield_default }, + { "CM_COMB_C22", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_COMB_C23_C24[] = { + { "CM_COMB_C23", 0, 15, &umr_bitfield_default }, + { "CM_COMB_C24", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_COMB_C31_C32[] = { + { "CM_COMB_C31", 0, 15, &umr_bitfield_default }, + { "CM_COMB_C32", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_COMB_C33_C34[] = { + { "CM_COMB_C33", 0, 15, &umr_bitfield_default }, + { "CM_COMB_C34", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_IGAM_CONTROL[] = { + { "CM_IGAM_LUT_MODE", 0, 1, &umr_bitfield_default }, + { "CM_IGAM_LUT_DATA_SIGNED_EN_B", 2, 2, &umr_bitfield_default }, + { "CM_IGAM_LUT_DATA_SIGNED_EN_G", 3, 3, &umr_bitfield_default }, + { "CM_IGAM_LUT_DATA_SIGNED_EN_R", 4, 4, &umr_bitfield_default }, + { "CM_IGAM_LUT_INC_B", 5, 8, &umr_bitfield_default }, + { "CM_IGAM_LUT_INC_G", 9, 12, &umr_bitfield_default }, + { "CM_IGAM_LUT_INC_R", 13, 16, &umr_bitfield_default }, + { "CM_IGAM_LUT_FORMAT_B", 17, 18, &umr_bitfield_default }, + { "CM_IGAM_LUT_FORMAT_G", 19, 20, &umr_bitfield_default }, + { "CM_IGAM_LUT_FORMAT_R", 21, 22, &umr_bitfield_default }, + { "CM_IGAM_LUT_B_FLOAT_POINT_EN", 23, 23, &umr_bitfield_default }, + { "CM_IGAM_LUT_G_FLOAT_POINT_EN", 24, 24, &umr_bitfield_default }, + { "CM_IGAM_LUT_R_FLOAT_POINT_EN", 25, 25, &umr_bitfield_default }, + { "CM_IGAM_INPUT_FORMAT", 26, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_IGAM_LUT_RW_CONTROL[] = { + { "CM_IGAM_LUT_RW_MODE", 0, 0, &umr_bitfield_default }, + { "CM_IGAM_LUT_WRITE_EN_MASK", 4, 6, &umr_bitfield_default }, + { "CM_IGAM_LUT_SEL", 8, 8, &umr_bitfield_default }, + { "CM_IGAM_LUT_HOST_EN", 12, 12, &umr_bitfield_default }, + { "CM_IGAM_DGAM_CONFIG_STATUS", 16, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_IGAM_LUT_RW_INDEX[] = { + { "CM_IGAM_LUT_RW_INDEX", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_IGAM_LUT_SEQ_COLOR[] = { + { "CM_IGAM_LUT_SEQ_COLOR", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_IGAM_LUT_30_COLOR[] = { + { "CM_IGAM_LUT_10_BLUE", 0, 9, &umr_bitfield_default }, + { "CM_IGAM_LUT_10_GREEN", 10, 19, &umr_bitfield_default }, + { "CM_IGAM_LUT_10_RED", 20, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_IGAM_LUT_PWL_DATA[] = { + { "CM_IGAM_LUT_PWL_BASE", 0, 15, &umr_bitfield_default }, + { "CM_IGAM_LUT_PWL_DELTA", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_IGAM_LUT_AUTOFILL[] = { + { "CM_IGAM_LUT_AUTOFILL", 0, 0, &umr_bitfield_default }, + { "CM_IGAM_LUT_AUTOFILL_DONE", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_IGAM_LUT_BW_OFFSET_BLUE[] = { + { "CM_IGAM_LUT_BLACK_OFFSET_BLUE", 0, 15, &umr_bitfield_default }, + { "CM_IGAM_LUT_WHITE_OFFSET_BLUE", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_IGAM_LUT_BW_OFFSET_GREEN[] = { + { "CM_IGAM_LUT_BLACK_OFFSET_GREEN", 0, 15, &umr_bitfield_default }, + { "CM_IGAM_LUT_WHITE_OFFSET_GREEN", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_IGAM_LUT_BW_OFFSET_RED[] = { + { "CM_IGAM_LUT_BLACK_OFFSET_RED", 0, 15, &umr_bitfield_default }, + { "CM_IGAM_LUT_WHITE_OFFSET_RED", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_ICSC_CONTROL[] = { + { "CM_ICSC_MODE", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_ICSC_C11_C12[] = { + { "CM_ICSC_C11", 0, 15, &umr_bitfield_default }, + { "CM_ICSC_C12", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_ICSC_C13_C14[] = { + { "CM_ICSC_C13", 0, 15, &umr_bitfield_default }, + { "CM_ICSC_C14", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_ICSC_C21_C22[] = { + { "CM_ICSC_C21", 0, 15, &umr_bitfield_default }, + { "CM_ICSC_C22", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_ICSC_C23_C24[] = { + { "CM_ICSC_C23", 0, 15, &umr_bitfield_default }, + { "CM_ICSC_C24", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_ICSC_C31_C32[] = { + { "CM_ICSC_C31", 0, 15, &umr_bitfield_default }, + { "CM_ICSC_C32", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_ICSC_C33_C34[] = { + { "CM_ICSC_C33", 0, 15, &umr_bitfield_default }, + { "CM_ICSC_C34", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_GAMUT_REMAP_CONTROL[] = { + { "CM_GAMUT_REMAP_MODE", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_GAMUT_REMAP_C11_C12[] = { + { "CM_GAMUT_REMAP_C11", 0, 15, &umr_bitfield_default }, + { "CM_GAMUT_REMAP_C12", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_GAMUT_REMAP_C13_C14[] = { + { "CM_GAMUT_REMAP_C13", 0, 15, &umr_bitfield_default }, + { "CM_GAMUT_REMAP_C14", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_GAMUT_REMAP_C21_C22[] = { + { "CM_GAMUT_REMAP_C21", 0, 15, &umr_bitfield_default }, + { "CM_GAMUT_REMAP_C22", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_GAMUT_REMAP_C23_C24[] = { + { "CM_GAMUT_REMAP_C23", 0, 15, &umr_bitfield_default }, + { "CM_GAMUT_REMAP_C24", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_GAMUT_REMAP_C31_C32[] = { + { "CM_GAMUT_REMAP_C31", 0, 15, &umr_bitfield_default }, + { "CM_GAMUT_REMAP_C32", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_GAMUT_REMAP_C33_C34[] = { + { "CM_GAMUT_REMAP_C33", 0, 15, &umr_bitfield_default }, + { "CM_GAMUT_REMAP_C34", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_OCSC_CONTROL[] = { + { "CM_OCSC_MODE", 0, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_OCSC_C11_C12[] = { + { "CM_OCSC_C11", 0, 15, &umr_bitfield_default }, + { "CM_OCSC_C12", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_OCSC_C13_C14[] = { + { "CM_OCSC_C13", 0, 15, &umr_bitfield_default }, + { "CM_OCSC_C14", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_OCSC_C21_C22[] = { + { "CM_OCSC_C21", 0, 15, &umr_bitfield_default }, + { "CM_OCSC_C22", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_OCSC_C23_C24[] = { + { "CM_OCSC_C23", 0, 15, &umr_bitfield_default }, + { "CM_OCSC_C24", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_OCSC_C31_C32[] = { + { "CM_OCSC_C31", 0, 15, &umr_bitfield_default }, + { "CM_OCSC_C32", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_OCSC_C33_C34[] = { + { "CM_OCSC_C33", 0, 15, &umr_bitfield_default }, + { "CM_OCSC_C34", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_BNS_VALUES_R[] = { + { "CM_BNS_BIAS_R", 0, 15, &umr_bitfield_default }, + { "CM_BNS_SCALE_R", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_BNS_VALUES_G[] = { + { "CM_BNS_BIAS_G", 0, 15, &umr_bitfield_default }, + { "CM_BNS_SCALE_G", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_BNS_VALUES_B[] = { + { "CM_BNS_BIAS_B", 0, 15, &umr_bitfield_default }, + { "CM_BNS_SCALE_B", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_DGAM_CONTROL[] = { + { "CM_DGAM_LUT_MODE", 0, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_DGAM_LUT_INDEX[] = { + { "CM_DGAM_LUT_INDEX", 0, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_DGAM_LUT_DATA[] = { + { "CM_DGAM_LUT_DATA", 0, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_DGAM_LUT_WRITE_EN_MASK[] = { + { "CM_DGAM_LUT_WRITE_EN_MASK", 0, 2, &umr_bitfield_default }, + { "CM_DGAM_LUT_WRITE_SEL", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_DGAM_RAMA_START_CNTL_B[] = { + { "CM_DGAM_RAMA_EXP_REGION_START_B", 0, 17, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B", 20, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_DGAM_RAMA_START_CNTL_G[] = { + { "CM_DGAM_RAMA_EXP_REGION_START_G", 0, 17, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G", 20, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_DGAM_RAMA_START_CNTL_R[] = { + { "CM_DGAM_RAMA_EXP_REGION_START_R", 0, 17, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R", 20, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_B[] = { + { "CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_G[] = { + { "CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_R[] = { + { "CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_DGAM_RAMA_END_CNTL1_B[] = { + { "CM_DGAM_RAMA_EXP_REGION_END_B", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_DGAM_RAMA_END_CNTL2_B[] = { + { "CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B", 0, 15, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION_END_BASE_B", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_DGAM_RAMA_END_CNTL1_G[] = { + { "CM_DGAM_RAMA_EXP_REGION_END_G", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_DGAM_RAMA_END_CNTL2_G[] = { + { "CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G", 0, 15, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION_END_BASE_G", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_DGAM_RAMA_END_CNTL1_R[] = { + { "CM_DGAM_RAMA_EXP_REGION_END_R", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_DGAM_RAMA_END_CNTL2_R[] = { + { "CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R", 0, 15, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION_END_BASE_R", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_DGAM_RAMA_REGION_0_1[] = { + { "CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_DGAM_RAMA_REGION_2_3[] = { + { "CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_DGAM_RAMA_REGION_4_5[] = { + { "CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_DGAM_RAMA_REGION_6_7[] = { + { "CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_DGAM_RAMA_REGION_8_9[] = { + { "CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_DGAM_RAMA_REGION_10_11[] = { + { "CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_DGAM_RAMA_REGION_12_13[] = { + { "CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_DGAM_RAMA_REGION_14_15[] = { + { "CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_DGAM_RAMB_START_CNTL_B[] = { + { "CM_DGAM_RAMB_EXP_REGION_START_B", 0, 17, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B", 20, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_DGAM_RAMB_START_CNTL_G[] = { + { "CM_DGAM_RAMB_EXP_REGION_START_G", 0, 17, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G", 20, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_DGAM_RAMB_START_CNTL_R[] = { + { "CM_DGAM_RAMB_EXP_REGION_START_R", 0, 17, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R", 20, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_B[] = { + { "CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_G[] = { + { "CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_R[] = { + { "CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_DGAM_RAMB_END_CNTL1_B[] = { + { "CM_DGAM_RAMB_EXP_REGION_END_B", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_DGAM_RAMB_END_CNTL2_B[] = { + { "CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B", 0, 15, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION_END_BASE_B", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_DGAM_RAMB_END_CNTL1_G[] = { + { "CM_DGAM_RAMB_EXP_REGION_END_G", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_DGAM_RAMB_END_CNTL2_G[] = { + { "CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G", 0, 15, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION_END_BASE_G", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_DGAM_RAMB_END_CNTL1_R[] = { + { "CM_DGAM_RAMB_EXP_REGION_END_R", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_DGAM_RAMB_END_CNTL2_R[] = { + { "CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R", 0, 15, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION_END_BASE_R", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_DGAM_RAMB_REGION_0_1[] = { + { "CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_DGAM_RAMB_REGION_2_3[] = { + { "CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_DGAM_RAMB_REGION_4_5[] = { + { "CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_DGAM_RAMB_REGION_6_7[] = { + { "CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_DGAM_RAMB_REGION_8_9[] = { + { "CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_DGAM_RAMB_REGION_10_11[] = { + { "CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_DGAM_RAMB_REGION_12_13[] = { + { "CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_DGAM_RAMB_REGION_14_15[] = { + { "CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_RGAM_CONTROL[] = { + { "CM_RGAM_LUT_MODE", 0, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_RGAM_LUT_INDEX[] = { + { "CM_RGAM_LUT_INDEX", 0, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_RGAM_LUT_DATA[] = { + { "CM_RGAM_LUT_DATA", 0, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_RGAM_LUT_WRITE_EN_MASK[] = { + { "CM_RGAM_LUT_WRITE_EN_MASK", 0, 2, &umr_bitfield_default }, + { "CM_RGAM_LUT_WRITE_SEL", 4, 4, &umr_bitfield_default }, + { "CM_RGAM_CONFIG_STATUS", 8, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_RGAM_RAMA_START_CNTL_B[] = { + { "CM_RGAM_RAMA_EXP_REGION_START_B", 0, 17, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_B", 20, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_RGAM_RAMA_START_CNTL_G[] = { + { "CM_RGAM_RAMA_EXP_REGION_START_G", 0, 17, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_G", 20, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_RGAM_RAMA_START_CNTL_R[] = { + { "CM_RGAM_RAMA_EXP_REGION_START_R", 0, 17, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_R", 20, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_B[] = { + { "CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_G[] = { + { "CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_R[] = { + { "CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_RGAM_RAMA_END_CNTL1_B[] = { + { "CM_RGAM_RAMA_EXP_REGION_END_B", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_RGAM_RAMA_END_CNTL2_B[] = { + { "CM_RGAM_RAMA_EXP_REGION_END_SLOPE_B", 0, 15, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION_END_BASE_B", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_RGAM_RAMA_END_CNTL1_G[] = { + { "CM_RGAM_RAMA_EXP_REGION_END_G", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_RGAM_RAMA_END_CNTL2_G[] = { + { "CM_RGAM_RAMA_EXP_REGION_END_SLOPE_G", 0, 15, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION_END_BASE_G", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_RGAM_RAMA_END_CNTL1_R[] = { + { "CM_RGAM_RAMA_EXP_REGION_END_R", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_RGAM_RAMA_END_CNTL2_R[] = { + { "CM_RGAM_RAMA_EXP_REGION_END_SLOPE_R", 0, 15, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION_END_BASE_R", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_RGAM_RAMA_REGION_0_1[] = { + { "CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_RGAM_RAMA_REGION_2_3[] = { + { "CM_RGAM_RAMA_EXP_REGION2_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION2_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION3_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION3_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_RGAM_RAMA_REGION_4_5[] = { + { "CM_RGAM_RAMA_EXP_REGION4_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION4_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION5_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION5_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_RGAM_RAMA_REGION_6_7[] = { + { "CM_RGAM_RAMA_EXP_REGION6_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION6_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION7_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION7_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_RGAM_RAMA_REGION_8_9[] = { + { "CM_RGAM_RAMA_EXP_REGION8_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION8_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION9_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION9_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_RGAM_RAMA_REGION_10_11[] = { + { "CM_RGAM_RAMA_EXP_REGION10_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION10_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION11_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION11_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_RGAM_RAMA_REGION_12_13[] = { + { "CM_RGAM_RAMA_EXP_REGION12_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION12_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION13_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION13_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_RGAM_RAMA_REGION_14_15[] = { + { "CM_RGAM_RAMA_EXP_REGION14_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION14_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION15_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION15_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_RGAM_RAMA_REGION_16_17[] = { + { "CM_RGAM_RAMA_EXP_REGION16_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION16_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION17_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION17_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_RGAM_RAMA_REGION_18_19[] = { + { "CM_RGAM_RAMA_EXP_REGION18_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION18_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION19_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION19_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_RGAM_RAMA_REGION_20_21[] = { + { "CM_RGAM_RAMA_EXP_REGION20_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION20_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION21_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION21_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_RGAM_RAMA_REGION_22_23[] = { + { "CM_RGAM_RAMA_EXP_REGION22_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION22_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION23_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION23_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_RGAM_RAMA_REGION_24_25[] = { + { "CM_RGAM_RAMA_EXP_REGION24_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION24_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION25_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION25_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_RGAM_RAMA_REGION_26_27[] = { + { "CM_RGAM_RAMA_EXP_REGION26_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION26_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION27_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION27_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_RGAM_RAMA_REGION_28_29[] = { + { "CM_RGAM_RAMA_EXP_REGION28_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION28_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION29_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION29_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_RGAM_RAMA_REGION_30_31[] = { + { "CM_RGAM_RAMA_EXP_REGION30_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION30_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION31_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION31_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_RGAM_RAMA_REGION_32_33[] = { + { "CM_RGAM_RAMA_EXP_REGION32_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION32_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_RGAM_RAMB_START_CNTL_B[] = { + { "CM_RGAM_RAMB_EXP_REGION_START_B", 0, 17, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B", 20, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_RGAM_RAMB_START_CNTL_G[] = { + { "CM_RGAM_RAMB_EXP_REGION_START_G", 0, 17, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_G", 20, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_RGAM_RAMB_START_CNTL_R[] = { + { "CM_RGAM_RAMB_EXP_REGION_START_R", 0, 17, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_R", 20, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_B[] = { + { "CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_G[] = { + { "CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_R[] = { + { "CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_RGAM_RAMB_END_CNTL1_B[] = { + { "CM_RGAM_RAMB_EXP_REGION_END_B", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_RGAM_RAMB_END_CNTL2_B[] = { + { "CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B", 0, 15, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION_END_BASE_B", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_RGAM_RAMB_END_CNTL1_G[] = { + { "CM_RGAM_RAMB_EXP_REGION_END_G", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_RGAM_RAMB_END_CNTL2_G[] = { + { "CM_RGAM_RAMB_EXP_REGION_END_SLOPE_G", 0, 15, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION_END_BASE_G", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_RGAM_RAMB_END_CNTL1_R[] = { + { "CM_RGAM_RAMB_EXP_REGION_END_R", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_RGAM_RAMB_END_CNTL2_R[] = { + { "CM_RGAM_RAMB_EXP_REGION_END_SLOPE_R", 0, 15, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION_END_BASE_R", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_RGAM_RAMB_REGION_0_1[] = { + { "CM_RGAM_RAMB_EXP_REGION0_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION0_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION1_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION1_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_RGAM_RAMB_REGION_2_3[] = { + { "CM_RGAM_RAMB_EXP_REGION2_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION2_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION3_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION3_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_RGAM_RAMB_REGION_4_5[] = { + { "CM_RGAM_RAMB_EXP_REGION4_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION4_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION5_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION5_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_RGAM_RAMB_REGION_6_7[] = { + { "CM_RGAM_RAMB_EXP_REGION6_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION6_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION7_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION7_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_RGAM_RAMB_REGION_8_9[] = { + { "CM_RGAM_RAMB_EXP_REGION8_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION8_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION9_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION9_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_RGAM_RAMB_REGION_10_11[] = { + { "CM_RGAM_RAMB_EXP_REGION10_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION10_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION11_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION11_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_RGAM_RAMB_REGION_12_13[] = { + { "CM_RGAM_RAMB_EXP_REGION12_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION12_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION13_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION13_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_RGAM_RAMB_REGION_14_15[] = { + { "CM_RGAM_RAMB_EXP_REGION14_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION14_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION15_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION15_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_RGAM_RAMB_REGION_16_17[] = { + { "CM_RGAM_RAMB_EXP_REGION16_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION16_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION17_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION17_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_RGAM_RAMB_REGION_18_19[] = { + { "CM_RGAM_RAMB_EXP_REGION18_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION18_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION19_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION19_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_RGAM_RAMB_REGION_20_21[] = { + { "CM_RGAM_RAMB_EXP_REGION20_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION20_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION21_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION21_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_RGAM_RAMB_REGION_22_23[] = { + { "CM_RGAM_RAMB_EXP_REGION22_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION22_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION23_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION23_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_RGAM_RAMB_REGION_24_25[] = { + { "CM_RGAM_RAMB_EXP_REGION24_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION24_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION25_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION25_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_RGAM_RAMB_REGION_26_27[] = { + { "CM_RGAM_RAMB_EXP_REGION26_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION26_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION27_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION27_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_RGAM_RAMB_REGION_28_29[] = { + { "CM_RGAM_RAMB_EXP_REGION28_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION28_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION29_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION29_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_RGAM_RAMB_REGION_30_31[] = { + { "CM_RGAM_RAMB_EXP_REGION30_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION30_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION31_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION31_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_RGAM_RAMB_REGION_32_33[] = { + { "CM_RGAM_RAMB_EXP_REGION32_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION32_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION33_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION33_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_HDR_MULT_COEF[] = { + { "CM_HDR_MULT_COEF", 0, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_RANGE_CLAMP_CONTROL_R[] = { + { "CM_RANGE_CLAMP_MAX_R", 0, 15, &umr_bitfield_default }, + { "CM_RANGE_CLAMP_MIN_R", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_RANGE_CLAMP_CONTROL_G[] = { + { "CM_RANGE_CLAMP_MAX_G", 0, 15, &umr_bitfield_default }, + { "CM_RANGE_CLAMP_MIN_G", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_RANGE_CLAMP_CONTROL_B[] = { + { "CM_RANGE_CLAMP_MAX_B", 0, 15, &umr_bitfield_default }, + { "CM_RANGE_CLAMP_MIN_B", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_DENORM_CONTROL[] = { + { "CM_DENORM_MODE", 0, 2, &umr_bitfield_default }, + { "CM_DENORM_ROUND_CLAMP", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_CMOUT_CONTROL[] = { + { "CM_CMOUT_ROUND_TRUNC_MODE", 0, 3, &umr_bitfield_default }, + { "CM_CMOUT_SPATIAL_DITHER_EN", 4, 4, &umr_bitfield_default }, + { "CM_CMOUT_SPATIAL_DITHER_MODE", 8, 9, &umr_bitfield_default }, + { "CM_CMOUT_SPATIAL_DITHER_DEPTH", 12, 13, &umr_bitfield_default }, + { "CM_CMOUT_FRAME_RANDOM_ENABLE", 16, 16, &umr_bitfield_default }, + { "CM_CMOUT_RGB_RANDOM_EN", 20, 20, &umr_bitfield_default }, + { "CM_CMOUT_HIGHPASS_RANDOM_ENABLE", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_CMOUT_RANDOM_SEEDS[] = { + { "CM_CMOUT_RAND_R_SEED", 0, 7, &umr_bitfield_default }, + { "CM_CMOUT_RAND_G_SEED", 8, 15, &umr_bitfield_default }, + { "CM_CMOUT_RAND_B_SEED", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_MEM_PWR_CTRL[] = { + { "SHARED_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default }, + { "SHARED_MEM_PWR_DIS", 2, 2, &umr_bitfield_default }, + { "RGAM_MEM_PWR_FORCE", 4, 5, &umr_bitfield_default }, + { "RGAM_MEM_PWR_DIS", 6, 6, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM1_CM_MEM_PWR_STATUS[] = { + { "SHARED_MEM_PWR_STATE", 0, 1, &umr_bitfield_default }, + { "RGAM_MEM_PWR_STATE", 2, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON13_PERFCOUNTER_CNTL[] = { + { "PERFCOUNTER_EVENT_SEL", 0, 8, &umr_bitfield_default }, + { "PERFCOUNTER_CVALUE_SEL", 9, 11, &umr_bitfield_default }, + { "PERFCOUNTER_INC_MODE", 12, 14, &umr_bitfield_default }, + { "PERFCOUNTER_HW_CNTL_SEL", 15, 15, &umr_bitfield_default }, + { "PERFCOUNTER_RUNEN_MODE", 16, 16, &umr_bitfield_default }, + { "PERFCOUNTER_CNTOFF_START_DIS", 22, 22, &umr_bitfield_default }, + { "PERFCOUNTER_RESTART_EN", 23, 23, &umr_bitfield_default }, + { "PERFCOUNTER_INT_EN", 24, 24, &umr_bitfield_default }, + { "PERFCOUNTER_OFF_MASK", 25, 25, &umr_bitfield_default }, + { "PERFCOUNTER_ACTIVE", 26, 26, &umr_bitfield_default }, + { "PERFCOUNTER_CNTL_SEL", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON13_PERFCOUNTER_CNTL2[] = { + { "PERFCOUNTER_COUNTED_VALUE_TYPE", 0, 1, &umr_bitfield_default }, + { "PERFCOUNTER_HW_STOP1_SEL", 2, 2, &umr_bitfield_default }, + { "PERFCOUNTER_HW_STOP2_SEL", 3, 3, &umr_bitfield_default }, + { "PERFCOUNTER_CNTOFF_SEL", 8, 13, &umr_bitfield_default }, + { "PERFCOUNTER_CNTL2_SEL", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON13_PERFCOUNTER_STATE[] = { + { "PERFCOUNTER_CNT0_STATE", 0, 1, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL0", 2, 2, &umr_bitfield_default }, + { "PERFCOUNTER_CNT1_STATE", 4, 5, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL1", 6, 6, &umr_bitfield_default }, + { "PERFCOUNTER_CNT2_STATE", 8, 9, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL2", 10, 10, &umr_bitfield_default }, + { "PERFCOUNTER_CNT3_STATE", 12, 13, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL3", 14, 14, &umr_bitfield_default }, + { "PERFCOUNTER_CNT4_STATE", 16, 17, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL4", 18, 18, &umr_bitfield_default }, + { "PERFCOUNTER_CNT5_STATE", 20, 21, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL5", 22, 22, &umr_bitfield_default }, + { "PERFCOUNTER_CNT6_STATE", 24, 25, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL6", 26, 26, &umr_bitfield_default }, + { "PERFCOUNTER_CNT7_STATE", 28, 29, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL7", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON13_PERFMON_CNTL[] = { + { "PERFMON_STATE", 0, 1, &umr_bitfield_default }, + { "PERFMON_RPT_COUNT", 8, 27, &umr_bitfield_default }, + { "PERFMON_CNTOFF_AND_OR", 28, 28, &umr_bitfield_default }, + { "PERFMON_CNTOFF_INT_EN", 29, 29, &umr_bitfield_default }, + { "PERFMON_CNTOFF_INT_STATUS", 30, 30, &umr_bitfield_default }, + { "PERFMON_CNTOFF_INT_ACK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON13_PERFMON_CNTL2[] = { + { "PERFMON_CNTOFF_INT_TYPE", 0, 0, &umr_bitfield_default }, + { "PERFMON_CLK_ENABLE", 1, 1, &umr_bitfield_default }, + { "PERFMON_RUN_ENABLE_START_SEL", 2, 9, &umr_bitfield_default }, + { "PERFMON_RUN_ENABLE_STOP_SEL", 10, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC[] = { + { "PERFCOUNTER_INT0_STATUS", 0, 0, &umr_bitfield_default }, + { "PERFCOUNTER_INT1_STATUS", 1, 1, &umr_bitfield_default }, + { "PERFCOUNTER_INT2_STATUS", 2, 2, &umr_bitfield_default }, + { "PERFCOUNTER_INT3_STATUS", 3, 3, &umr_bitfield_default }, + { "PERFCOUNTER_INT4_STATUS", 4, 4, &umr_bitfield_default }, + { "PERFCOUNTER_INT5_STATUS", 5, 5, &umr_bitfield_default }, + { "PERFCOUNTER_INT6_STATUS", 6, 6, &umr_bitfield_default }, + { "PERFCOUNTER_INT7_STATUS", 7, 7, &umr_bitfield_default }, + { "PERFCOUNTER_INT0_ACK", 8, 8, &umr_bitfield_default }, + { "PERFCOUNTER_INT1_ACK", 9, 9, &umr_bitfield_default }, + { "PERFCOUNTER_INT2_ACK", 10, 10, &umr_bitfield_default }, + { "PERFCOUNTER_INT3_ACK", 11, 11, &umr_bitfield_default }, + { "PERFCOUNTER_INT4_ACK", 12, 12, &umr_bitfield_default }, + { "PERFCOUNTER_INT5_ACK", 13, 13, &umr_bitfield_default }, + { "PERFCOUNTER_INT6_ACK", 14, 14, &umr_bitfield_default }, + { "PERFCOUNTER_INT7_ACK", 15, 15, &umr_bitfield_default }, + { "PERFMON_CVALUE_HI", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON13_PERFMON_CVALUE_LOW[] = { + { "PERFMON_CVALUE_LOW", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON13_PERFMON_HI[] = { + { "PERFMON_HI", 0, 15, &umr_bitfield_default }, + { "PERFMON_READ_SEL", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON13_PERFMON_LOW[] = { + { "PERFMON_LOW", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDPP_TOP2_DPP_CONTROL[] = { + { "DPP_CLOCK_ENABLE", 4, 4, &umr_bitfield_default }, + { "DPPCLK_G_GATE_DISABLE", 8, 8, &umr_bitfield_default }, + { "DPPCLK_G_DYN_GATE_DISABLE", 10, 10, &umr_bitfield_default }, + { "DPPCLK_G_DSCL_GATE_DISABLE", 12, 12, &umr_bitfield_default }, + { "DPPCLK_R_GATE_DISABLE", 16, 16, &umr_bitfield_default }, + { "DISPCLK_R_GATE_DISABLE", 18, 18, &umr_bitfield_default }, + { "DISPCLK_G_GATE_DISABLE", 20, 20, &umr_bitfield_default }, + { "DPPCLK_RATE_CONTROL", 24, 24, &umr_bitfield_default }, + { "DPP_TEST_CLK_SEL", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDPP_TOP2_DPP_SOFT_RESET[] = { + { "CNVC_SOFT_RESET", 0, 0, &umr_bitfield_default }, + { "DSCL_SOFT_RESET", 4, 4, &umr_bitfield_default }, + { "CM_SOFT_RESET", 8, 8, &umr_bitfield_default }, + { "OBUF_SOFT_RESET", 12, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDPP_TOP2_DPP_CRC_VAL_R_G[] = { + { "DPP_CRC_R_CR", 0, 15, &umr_bitfield_default }, + { "DPP_CRC_G_Y", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDPP_TOP2_DPP_CRC_VAL_B_A[] = { + { "DPP_CRC_B_CB", 0, 15, &umr_bitfield_default }, + { "DPP_CRC_ALPHA", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDPP_TOP2_DPP_CRC_CTRL[] = { + { "DPP_CRC_EN", 0, 0, &umr_bitfield_default }, + { "DPP_CRC_CONT_EN", 1, 1, &umr_bitfield_default }, + { "DPP_CRC_ONE_SHOT_PENDING", 2, 2, &umr_bitfield_default }, + { "DPP_CRC_420_COMP_SEL", 3, 3, &umr_bitfield_default }, + { "DPP_CRC_SRC_SEL", 4, 5, &umr_bitfield_default }, + { "DPP_CRC_STEREO_EN", 7, 7, &umr_bitfield_default }, + { "DPP_CRC_STEREO_MODE", 8, 9, &umr_bitfield_default }, + { "DPP_CRC_INTERLACE_MODE", 10, 11, &umr_bitfield_default }, + { "DPP_CRC_PIX_FORMAT_SEL", 12, 14, &umr_bitfield_default }, + { "DPP_CRC_CURSOR_FORMAT_SEL", 15, 15, &umr_bitfield_default }, + { "DPP_CRC_MASK", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDPP_TOP2_HOST_READ_CONTROL[] = { + { "HOST_READ_RATE_CONTROL", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT[] = { + { "CNVC_SURFACE_PIXEL_FORMAT", 0, 6, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNVC_CFG2_FORMAT_CONTROL[] = { + { "FORMAT_EXPANSION_MODE", 0, 0, &umr_bitfield_default }, + { "FORMAT_CNV16", 4, 4, &umr_bitfield_default }, + { "ALPHA_EN", 8, 8, &umr_bitfield_default }, + { "CNVC_BYPASS", 12, 12, &umr_bitfield_default }, + { "OUTPUT_FP", 16, 16, &umr_bitfield_default }, + { "CNVC_UPDATE_PENDING", 20, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNVC_CFG2_FCNV_FP_SCALE_BIAS[] = { + { "FCNV_FP_SCALE", 0, 15, &umr_bitfield_default }, + { "FCNV_FP_BIAS", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNVC_CFG2_DENORM_CONTROL[] = { + { "DENORM_SCALE", 0, 14, &umr_bitfield_default }, + { "CLAMP_POSITIVE", 15, 15, &umr_bitfield_default }, + { "DENORM_BIAS", 16, 30, &umr_bitfield_default }, + { "DENORM_TRUNCATE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNVC_CFG2_COLOR_KEYER_CONTROL[] = { + { "COLOR_KEYER_EN", 0, 0, &umr_bitfield_default }, + { "COLOR_KEYER_MODE", 4, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNVC_CFG2_COLOR_KEYER_ALPHA[] = { + { "COLOR_KEYER_ALPHA_LOW", 0, 15, &umr_bitfield_default }, + { "COLOR_KEYER_ALPHA_HIGH", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNVC_CFG2_COLOR_KEYER_RED[] = { + { "COLOR_KEYER_RED_LOW", 0, 15, &umr_bitfield_default }, + { "COLOR_KEYER_RED_HIGH", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNVC_CFG2_COLOR_KEYER_GREEN[] = { + { "COLOR_KEYER_GREEN_LOW", 0, 15, &umr_bitfield_default }, + { "COLOR_KEYER_GREEN_HIGH", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNVC_CFG2_COLOR_KEYER_BLUE[] = { + { "COLOR_KEYER_BLUE_LOW", 0, 15, &umr_bitfield_default }, + { "COLOR_KEYER_BLUE_HIGH", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNVC_CUR2_CURSOR0_CONTROL[] = { + { "CUR0_ENABLE", 0, 0, &umr_bitfield_default }, + { "CUR0_EXPANSION_MODE", 1, 1, &umr_bitfield_default }, + { "CUR0_INVERT_MODE", 2, 2, &umr_bitfield_default }, + { "CUR0_MODE", 4, 5, &umr_bitfield_default }, + { "CUR0_UPDATE_PENDING", 6, 6, &umr_bitfield_default }, + { "CUR0_MAX", 8, 19, &umr_bitfield_default }, + { "CUR0_MIN", 20, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNVC_CUR2_CURSOR0_COLOR0[] = { + { "CUR0_COLOR0", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNVC_CUR2_CURSOR0_COLOR1[] = { + { "CUR0_COLOR1", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNVC_CUR2_CURSOR0_FP_SCALE_BIAS[] = { + { "CUR0_FP_SCALE", 0, 15, &umr_bitfield_default }, + { "CUR0_FP_BIAS", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL2_SCL_COEF_RAM_TAP_SELECT[] = { + { "SCL_COEF_RAM_TAP_PAIR_IDX", 0, 1, &umr_bitfield_default }, + { "SCL_COEF_RAM_PHASE", 8, 13, &umr_bitfield_default }, + { "SCL_COEF_RAM_FILTER_TYPE", 16, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL2_SCL_COEF_RAM_TAP_DATA[] = { + { "SCL_COEF_RAM_EVEN_TAP_COEF", 0, 13, &umr_bitfield_default }, + { "SCL_COEF_RAM_EVEN_TAP_COEF_EN", 15, 15, &umr_bitfield_default }, + { "SCL_COEF_RAM_ODD_TAP_COEF", 16, 29, &umr_bitfield_default }, + { "SCL_COEF_RAM_ODD_TAP_COEF_EN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL2_SCL_MODE[] = { + { "DSCL_MODE", 0, 2, &umr_bitfield_default }, + { "SCL_COEF_RAM_SELECT", 8, 8, &umr_bitfield_default }, + { "SCL_COEF_RAM_SELECT_CURRENT", 12, 12, &umr_bitfield_default }, + { "SCL_CHROMA_COEF_MODE", 16, 16, &umr_bitfield_default }, + { "SCL_ALPHA_COEF_MODE", 20, 20, &umr_bitfield_default }, + { "SCL_COEF_RAM_SELECT_RD", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL2_SCL_TAP_CONTROL[] = { + { "SCL_V_NUM_TAPS", 0, 2, &umr_bitfield_default }, + { "SCL_H_NUM_TAPS", 4, 6, &umr_bitfield_default }, + { "SCL_V_NUM_TAPS_C", 8, 10, &umr_bitfield_default }, + { "SCL_H_NUM_TAPS_C", 12, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL2_DSCL_CONTROL[] = { + { "SCL_BOUNDARY_MODE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL2_DSCL_2TAP_CONTROL[] = { + { "SCL_H_2TAP_HARDCODE_COEF_EN", 0, 0, &umr_bitfield_default }, + { "SCL_H_2TAP_SHARP_EN", 4, 4, &umr_bitfield_default }, + { "SCL_H_2TAP_SHARP_FACTOR", 8, 10, &umr_bitfield_default }, + { "SCL_V_2TAP_HARDCODE_COEF_EN", 16, 16, &umr_bitfield_default }, + { "SCL_V_2TAP_SHARP_EN", 20, 20, &umr_bitfield_default }, + { "SCL_V_2TAP_SHARP_FACTOR", 24, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL2_SCL_MANUAL_REPLICATE_CONTROL[] = { + { "SCL_V_MANUAL_REPLICATE_FACTOR", 0, 3, &umr_bitfield_default }, + { "SCL_H_MANUAL_REPLICATE_FACTOR", 8, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO[] = { + { "SCL_H_SCALE_RATIO", 0, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL2_SCL_HORZ_FILTER_INIT[] = { + { "SCL_H_INIT_FRAC", 0, 23, &umr_bitfield_default }, + { "SCL_H_INIT_INT", 24, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C[] = { + { "SCL_H_SCALE_RATIO_C", 0, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL2_SCL_HORZ_FILTER_INIT_C[] = { + { "SCL_H_INIT_FRAC_C", 0, 23, &umr_bitfield_default }, + { "SCL_H_INIT_INT_C", 24, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO[] = { + { "SCL_V_SCALE_RATIO", 0, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL2_SCL_VERT_FILTER_INIT[] = { + { "SCL_V_INIT_FRAC", 0, 23, &umr_bitfield_default }, + { "SCL_V_INIT_INT", 24, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL2_SCL_VERT_FILTER_INIT_BOT[] = { + { "SCL_V_INIT_FRAC_BOT", 0, 23, &umr_bitfield_default }, + { "SCL_V_INIT_INT_BOT", 24, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C[] = { + { "SCL_V_SCALE_RATIO_C", 0, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL2_SCL_VERT_FILTER_INIT_C[] = { + { "SCL_V_INIT_FRAC_C", 0, 23, &umr_bitfield_default }, + { "SCL_V_INIT_INT_C", 24, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL2_SCL_VERT_FILTER_INIT_BOT_C[] = { + { "SCL_V_INIT_FRAC_BOT_C", 0, 23, &umr_bitfield_default }, + { "SCL_V_INIT_INT_BOT_C", 24, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL2_SCL_BLACK_OFFSET[] = { + { "SCL_BLACK_OFFSET_RGB_Y", 0, 15, &umr_bitfield_default }, + { "SCL_BLACK_OFFSET_CBCR", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL2_DSCL_UPDATE[] = { + { "SCL_UPDATE_PENDING", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL2_DSCL_AUTOCAL[] = { + { "AUTOCAL_MODE", 0, 1, &umr_bitfield_default }, + { "AUTOCAL_NUM_PIPE", 8, 9, &umr_bitfield_default }, + { "AUTOCAL_PIPE_ID", 12, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT[] = { + { "EXT_OVERSCAN_RIGHT", 0, 12, &umr_bitfield_default }, + { "EXT_OVERSCAN_LEFT", 16, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM[] = { + { "EXT_OVERSCAN_BOTTOM", 0, 12, &umr_bitfield_default }, + { "EXT_OVERSCAN_TOP", 16, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL2_OTG_H_BLANK[] = { + { "OTG_H_BLANK_START", 0, 13, &umr_bitfield_default }, + { "OTG_H_BLANK_END", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL2_OTG_V_BLANK[] = { + { "OTG_V_BLANK_START", 0, 13, &umr_bitfield_default }, + { "OTG_V_BLANK_END", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL2_RECOUT_START[] = { + { "RECOUT_START_X", 0, 12, &umr_bitfield_default }, + { "RECOUT_START_Y", 16, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL2_RECOUT_SIZE[] = { + { "RECOUT_WIDTH", 0, 13, &umr_bitfield_default }, + { "RECOUT_HEIGHT", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL2_MPC_SIZE[] = { + { "MPC_WIDTH", 0, 13, &umr_bitfield_default }, + { "MPC_HEIGHT", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL2_LB_DATA_FORMAT[] = { + { "PIXEL_DEPTH", 0, 1, &umr_bitfield_default }, + { "PIXEL_EXPAN_MODE", 8, 8, &umr_bitfield_default }, + { "PIXEL_REDUCE_MODE", 12, 12, &umr_bitfield_default }, + { "DYNAMIC_PIXEL_DEPTH", 16, 16, &umr_bitfield_default }, + { "DITHER_EN", 20, 20, &umr_bitfield_default }, + { "INTERLEAVE_EN", 24, 24, &umr_bitfield_default }, + { "ALPHA_EN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL2_LB_MEMORY_CTRL[] = { + { "MEMORY_CONFIG", 0, 1, &umr_bitfield_default }, + { "LB_MAX_PARTITIONS", 8, 13, &umr_bitfield_default }, + { "LB_NUM_PARTITIONS", 16, 22, &umr_bitfield_default }, + { "LB_NUM_PARTITIONS_C", 24, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL2_LB_V_COUNTER[] = { + { "V_COUNTER", 0, 12, &umr_bitfield_default }, + { "V_COUNTER_C", 16, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL2_DSCL_MEM_PWR_CTRL[] = { + { "LUT_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default }, + { "LUT_MEM_PWR_DIS", 2, 2, &umr_bitfield_default }, + { "LB_G1_MEM_PWR_FORCE", 4, 5, &umr_bitfield_default }, + { "LB_G1_MEM_PWR_DIS", 6, 6, &umr_bitfield_default }, + { "LB_G2_MEM_PWR_FORCE", 8, 9, &umr_bitfield_default }, + { "LB_G2_MEM_PWR_DIS", 10, 10, &umr_bitfield_default }, + { "LB_G3_MEM_PWR_FORCE", 12, 13, &umr_bitfield_default }, + { "LB_G3_MEM_PWR_DIS", 14, 14, &umr_bitfield_default }, + { "LB_G4_MEM_PWR_FORCE", 16, 17, &umr_bitfield_default }, + { "LB_G4_MEM_PWR_DIS", 18, 18, &umr_bitfield_default }, + { "LB_G5_MEM_PWR_FORCE", 20, 21, &umr_bitfield_default }, + { "LB_G5_MEM_PWR_DIS", 22, 22, &umr_bitfield_default }, + { "LB_G6_MEM_PWR_FORCE", 24, 25, &umr_bitfield_default }, + { "LB_G6_MEM_PWR_DIS", 26, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL2_DSCL_MEM_PWR_STATUS[] = { + { "LUT_MEM_PWR_STATE", 0, 1, &umr_bitfield_default }, + { "LB_G1_MEM_PWR_STATE", 2, 3, &umr_bitfield_default }, + { "LB_G2_MEM_PWR_STATE", 4, 5, &umr_bitfield_default }, + { "LB_G3_MEM_PWR_STATE", 6, 7, &umr_bitfield_default }, + { "LB_G4_MEM_PWR_STATE", 8, 9, &umr_bitfield_default }, + { "LB_G5_MEM_PWR_STATE", 10, 11, &umr_bitfield_default }, + { "LB_G6_MEM_PWR_STATE", 12, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL2_OBUF_CONTROL[] = { + { "OBUF_BYPASS", 0, 0, &umr_bitfield_default }, + { "OBUF_USE_FULL_BUFFER", 4, 4, &umr_bitfield_default }, + { "OBUF_H_2X_UPSCALE_EN", 8, 8, &umr_bitfield_default }, + { "OBUF_IS_HALF_RECOUT_WIDTH", 12, 12, &umr_bitfield_default }, + { "OBUF_H_2X_COEF_PHASE0_SEL", 16, 16, &umr_bitfield_default }, + { "OBUF_H_2X_COEF_PHASE1_SEL", 24, 24, &umr_bitfield_default }, + { "OBUF_OUT_HOLD_CNT", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL2_OBUF_MEM_PWR_CTRL[] = { + { "OBUF_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default }, + { "OBUF_MEM_PWR_DIS", 2, 2, &umr_bitfield_default }, + { "OBUF_MEM_PWR_STATE", 16, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_CONTROL[] = { + { "CM_BYPASS_EN", 0, 0, &umr_bitfield_default }, + { "CM_UPDATE_PENDING", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_COMA_C11_C12[] = { + { "CM_COMA_C11", 0, 15, &umr_bitfield_default }, + { "CM_COMA_C12", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_COMA_C13_C14[] = { + { "CM_COMA_C13", 0, 15, &umr_bitfield_default }, + { "CM_COMA_C14", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_COMA_C21_C22[] = { + { "CM_COMA_C21", 0, 15, &umr_bitfield_default }, + { "CM_COMA_C22", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_COMA_C23_C24[] = { + { "CM_COMA_C23", 0, 15, &umr_bitfield_default }, + { "CM_COMA_C24", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_COMA_C31_C32[] = { + { "CM_COMA_C31", 0, 15, &umr_bitfield_default }, + { "CM_COMA_C32", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_COMA_C33_C34[] = { + { "CM_COMA_C33", 0, 15, &umr_bitfield_default }, + { "CM_COMA_C34", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_COMB_C11_C12[] = { + { "CM_COMB_C11", 0, 15, &umr_bitfield_default }, + { "CM_COMB_C12", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_COMB_C13_C14[] = { + { "CM_COMB_C13", 0, 15, &umr_bitfield_default }, + { "CM_COMB_C14", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_COMB_C21_C22[] = { + { "CM_COMB_C21", 0, 15, &umr_bitfield_default }, + { "CM_COMB_C22", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_COMB_C23_C24[] = { + { "CM_COMB_C23", 0, 15, &umr_bitfield_default }, + { "CM_COMB_C24", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_COMB_C31_C32[] = { + { "CM_COMB_C31", 0, 15, &umr_bitfield_default }, + { "CM_COMB_C32", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_COMB_C33_C34[] = { + { "CM_COMB_C33", 0, 15, &umr_bitfield_default }, + { "CM_COMB_C34", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_IGAM_CONTROL[] = { + { "CM_IGAM_LUT_MODE", 0, 1, &umr_bitfield_default }, + { "CM_IGAM_LUT_DATA_SIGNED_EN_B", 2, 2, &umr_bitfield_default }, + { "CM_IGAM_LUT_DATA_SIGNED_EN_G", 3, 3, &umr_bitfield_default }, + { "CM_IGAM_LUT_DATA_SIGNED_EN_R", 4, 4, &umr_bitfield_default }, + { "CM_IGAM_LUT_INC_B", 5, 8, &umr_bitfield_default }, + { "CM_IGAM_LUT_INC_G", 9, 12, &umr_bitfield_default }, + { "CM_IGAM_LUT_INC_R", 13, 16, &umr_bitfield_default }, + { "CM_IGAM_LUT_FORMAT_B", 17, 18, &umr_bitfield_default }, + { "CM_IGAM_LUT_FORMAT_G", 19, 20, &umr_bitfield_default }, + { "CM_IGAM_LUT_FORMAT_R", 21, 22, &umr_bitfield_default }, + { "CM_IGAM_LUT_B_FLOAT_POINT_EN", 23, 23, &umr_bitfield_default }, + { "CM_IGAM_LUT_G_FLOAT_POINT_EN", 24, 24, &umr_bitfield_default }, + { "CM_IGAM_LUT_R_FLOAT_POINT_EN", 25, 25, &umr_bitfield_default }, + { "CM_IGAM_INPUT_FORMAT", 26, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_IGAM_LUT_RW_CONTROL[] = { + { "CM_IGAM_LUT_RW_MODE", 0, 0, &umr_bitfield_default }, + { "CM_IGAM_LUT_WRITE_EN_MASK", 4, 6, &umr_bitfield_default }, + { "CM_IGAM_LUT_SEL", 8, 8, &umr_bitfield_default }, + { "CM_IGAM_LUT_HOST_EN", 12, 12, &umr_bitfield_default }, + { "CM_IGAM_DGAM_CONFIG_STATUS", 16, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_IGAM_LUT_RW_INDEX[] = { + { "CM_IGAM_LUT_RW_INDEX", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_IGAM_LUT_SEQ_COLOR[] = { + { "CM_IGAM_LUT_SEQ_COLOR", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_IGAM_LUT_30_COLOR[] = { + { "CM_IGAM_LUT_10_BLUE", 0, 9, &umr_bitfield_default }, + { "CM_IGAM_LUT_10_GREEN", 10, 19, &umr_bitfield_default }, + { "CM_IGAM_LUT_10_RED", 20, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_IGAM_LUT_PWL_DATA[] = { + { "CM_IGAM_LUT_PWL_BASE", 0, 15, &umr_bitfield_default }, + { "CM_IGAM_LUT_PWL_DELTA", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_IGAM_LUT_AUTOFILL[] = { + { "CM_IGAM_LUT_AUTOFILL", 0, 0, &umr_bitfield_default }, + { "CM_IGAM_LUT_AUTOFILL_DONE", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_IGAM_LUT_BW_OFFSET_BLUE[] = { + { "CM_IGAM_LUT_BLACK_OFFSET_BLUE", 0, 15, &umr_bitfield_default }, + { "CM_IGAM_LUT_WHITE_OFFSET_BLUE", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_IGAM_LUT_BW_OFFSET_GREEN[] = { + { "CM_IGAM_LUT_BLACK_OFFSET_GREEN", 0, 15, &umr_bitfield_default }, + { "CM_IGAM_LUT_WHITE_OFFSET_GREEN", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_IGAM_LUT_BW_OFFSET_RED[] = { + { "CM_IGAM_LUT_BLACK_OFFSET_RED", 0, 15, &umr_bitfield_default }, + { "CM_IGAM_LUT_WHITE_OFFSET_RED", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_ICSC_CONTROL[] = { + { "CM_ICSC_MODE", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_ICSC_C11_C12[] = { + { "CM_ICSC_C11", 0, 15, &umr_bitfield_default }, + { "CM_ICSC_C12", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_ICSC_C13_C14[] = { + { "CM_ICSC_C13", 0, 15, &umr_bitfield_default }, + { "CM_ICSC_C14", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_ICSC_C21_C22[] = { + { "CM_ICSC_C21", 0, 15, &umr_bitfield_default }, + { "CM_ICSC_C22", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_ICSC_C23_C24[] = { + { "CM_ICSC_C23", 0, 15, &umr_bitfield_default }, + { "CM_ICSC_C24", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_ICSC_C31_C32[] = { + { "CM_ICSC_C31", 0, 15, &umr_bitfield_default }, + { "CM_ICSC_C32", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_ICSC_C33_C34[] = { + { "CM_ICSC_C33", 0, 15, &umr_bitfield_default }, + { "CM_ICSC_C34", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_GAMUT_REMAP_CONTROL[] = { + { "CM_GAMUT_REMAP_MODE", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_GAMUT_REMAP_C11_C12[] = { + { "CM_GAMUT_REMAP_C11", 0, 15, &umr_bitfield_default }, + { "CM_GAMUT_REMAP_C12", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_GAMUT_REMAP_C13_C14[] = { + { "CM_GAMUT_REMAP_C13", 0, 15, &umr_bitfield_default }, + { "CM_GAMUT_REMAP_C14", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_GAMUT_REMAP_C21_C22[] = { + { "CM_GAMUT_REMAP_C21", 0, 15, &umr_bitfield_default }, + { "CM_GAMUT_REMAP_C22", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_GAMUT_REMAP_C23_C24[] = { + { "CM_GAMUT_REMAP_C23", 0, 15, &umr_bitfield_default }, + { "CM_GAMUT_REMAP_C24", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_GAMUT_REMAP_C31_C32[] = { + { "CM_GAMUT_REMAP_C31", 0, 15, &umr_bitfield_default }, + { "CM_GAMUT_REMAP_C32", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_GAMUT_REMAP_C33_C34[] = { + { "CM_GAMUT_REMAP_C33", 0, 15, &umr_bitfield_default }, + { "CM_GAMUT_REMAP_C34", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_OCSC_CONTROL[] = { + { "CM_OCSC_MODE", 0, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_OCSC_C11_C12[] = { + { "CM_OCSC_C11", 0, 15, &umr_bitfield_default }, + { "CM_OCSC_C12", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_OCSC_C13_C14[] = { + { "CM_OCSC_C13", 0, 15, &umr_bitfield_default }, + { "CM_OCSC_C14", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_OCSC_C21_C22[] = { + { "CM_OCSC_C21", 0, 15, &umr_bitfield_default }, + { "CM_OCSC_C22", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_OCSC_C23_C24[] = { + { "CM_OCSC_C23", 0, 15, &umr_bitfield_default }, + { "CM_OCSC_C24", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_OCSC_C31_C32[] = { + { "CM_OCSC_C31", 0, 15, &umr_bitfield_default }, + { "CM_OCSC_C32", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_OCSC_C33_C34[] = { + { "CM_OCSC_C33", 0, 15, &umr_bitfield_default }, + { "CM_OCSC_C34", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_BNS_VALUES_R[] = { + { "CM_BNS_BIAS_R", 0, 15, &umr_bitfield_default }, + { "CM_BNS_SCALE_R", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_BNS_VALUES_G[] = { + { "CM_BNS_BIAS_G", 0, 15, &umr_bitfield_default }, + { "CM_BNS_SCALE_G", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_BNS_VALUES_B[] = { + { "CM_BNS_BIAS_B", 0, 15, &umr_bitfield_default }, + { "CM_BNS_SCALE_B", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_DGAM_CONTROL[] = { + { "CM_DGAM_LUT_MODE", 0, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_DGAM_LUT_INDEX[] = { + { "CM_DGAM_LUT_INDEX", 0, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_DGAM_LUT_DATA[] = { + { "CM_DGAM_LUT_DATA", 0, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_DGAM_LUT_WRITE_EN_MASK[] = { + { "CM_DGAM_LUT_WRITE_EN_MASK", 0, 2, &umr_bitfield_default }, + { "CM_DGAM_LUT_WRITE_SEL", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_DGAM_RAMA_START_CNTL_B[] = { + { "CM_DGAM_RAMA_EXP_REGION_START_B", 0, 17, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B", 20, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_DGAM_RAMA_START_CNTL_G[] = { + { "CM_DGAM_RAMA_EXP_REGION_START_G", 0, 17, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G", 20, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_DGAM_RAMA_START_CNTL_R[] = { + { "CM_DGAM_RAMA_EXP_REGION_START_R", 0, 17, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R", 20, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_B[] = { + { "CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_G[] = { + { "CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_R[] = { + { "CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_DGAM_RAMA_END_CNTL1_B[] = { + { "CM_DGAM_RAMA_EXP_REGION_END_B", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_DGAM_RAMA_END_CNTL2_B[] = { + { "CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B", 0, 15, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION_END_BASE_B", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_DGAM_RAMA_END_CNTL1_G[] = { + { "CM_DGAM_RAMA_EXP_REGION_END_G", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_DGAM_RAMA_END_CNTL2_G[] = { + { "CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G", 0, 15, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION_END_BASE_G", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_DGAM_RAMA_END_CNTL1_R[] = { + { "CM_DGAM_RAMA_EXP_REGION_END_R", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_DGAM_RAMA_END_CNTL2_R[] = { + { "CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R", 0, 15, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION_END_BASE_R", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_DGAM_RAMA_REGION_0_1[] = { + { "CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_DGAM_RAMA_REGION_2_3[] = { + { "CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_DGAM_RAMA_REGION_4_5[] = { + { "CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_DGAM_RAMA_REGION_6_7[] = { + { "CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_DGAM_RAMA_REGION_8_9[] = { + { "CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_DGAM_RAMA_REGION_10_11[] = { + { "CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_DGAM_RAMA_REGION_12_13[] = { + { "CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_DGAM_RAMA_REGION_14_15[] = { + { "CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_DGAM_RAMB_START_CNTL_B[] = { + { "CM_DGAM_RAMB_EXP_REGION_START_B", 0, 17, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B", 20, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_DGAM_RAMB_START_CNTL_G[] = { + { "CM_DGAM_RAMB_EXP_REGION_START_G", 0, 17, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G", 20, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_DGAM_RAMB_START_CNTL_R[] = { + { "CM_DGAM_RAMB_EXP_REGION_START_R", 0, 17, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R", 20, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_B[] = { + { "CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_G[] = { + { "CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_R[] = { + { "CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_DGAM_RAMB_END_CNTL1_B[] = { + { "CM_DGAM_RAMB_EXP_REGION_END_B", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_DGAM_RAMB_END_CNTL2_B[] = { + { "CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B", 0, 15, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION_END_BASE_B", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_DGAM_RAMB_END_CNTL1_G[] = { + { "CM_DGAM_RAMB_EXP_REGION_END_G", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_DGAM_RAMB_END_CNTL2_G[] = { + { "CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G", 0, 15, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION_END_BASE_G", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_DGAM_RAMB_END_CNTL1_R[] = { + { "CM_DGAM_RAMB_EXP_REGION_END_R", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_DGAM_RAMB_END_CNTL2_R[] = { + { "CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R", 0, 15, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION_END_BASE_R", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_DGAM_RAMB_REGION_0_1[] = { + { "CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_DGAM_RAMB_REGION_2_3[] = { + { "CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_DGAM_RAMB_REGION_4_5[] = { + { "CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_DGAM_RAMB_REGION_6_7[] = { + { "CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_DGAM_RAMB_REGION_8_9[] = { + { "CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_DGAM_RAMB_REGION_10_11[] = { + { "CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_DGAM_RAMB_REGION_12_13[] = { + { "CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_DGAM_RAMB_REGION_14_15[] = { + { "CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_RGAM_CONTROL[] = { + { "CM_RGAM_LUT_MODE", 0, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_RGAM_LUT_INDEX[] = { + { "CM_RGAM_LUT_INDEX", 0, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_RGAM_LUT_DATA[] = { + { "CM_RGAM_LUT_DATA", 0, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_RGAM_LUT_WRITE_EN_MASK[] = { + { "CM_RGAM_LUT_WRITE_EN_MASK", 0, 2, &umr_bitfield_default }, + { "CM_RGAM_LUT_WRITE_SEL", 4, 4, &umr_bitfield_default }, + { "CM_RGAM_CONFIG_STATUS", 8, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_RGAM_RAMA_START_CNTL_B[] = { + { "CM_RGAM_RAMA_EXP_REGION_START_B", 0, 17, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_B", 20, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_RGAM_RAMA_START_CNTL_G[] = { + { "CM_RGAM_RAMA_EXP_REGION_START_G", 0, 17, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_G", 20, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_RGAM_RAMA_START_CNTL_R[] = { + { "CM_RGAM_RAMA_EXP_REGION_START_R", 0, 17, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_R", 20, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_B[] = { + { "CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_G[] = { + { "CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_R[] = { + { "CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_RGAM_RAMA_END_CNTL1_B[] = { + { "CM_RGAM_RAMA_EXP_REGION_END_B", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_RGAM_RAMA_END_CNTL2_B[] = { + { "CM_RGAM_RAMA_EXP_REGION_END_SLOPE_B", 0, 15, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION_END_BASE_B", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_RGAM_RAMA_END_CNTL1_G[] = { + { "CM_RGAM_RAMA_EXP_REGION_END_G", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_RGAM_RAMA_END_CNTL2_G[] = { + { "CM_RGAM_RAMA_EXP_REGION_END_SLOPE_G", 0, 15, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION_END_BASE_G", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_RGAM_RAMA_END_CNTL1_R[] = { + { "CM_RGAM_RAMA_EXP_REGION_END_R", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_RGAM_RAMA_END_CNTL2_R[] = { + { "CM_RGAM_RAMA_EXP_REGION_END_SLOPE_R", 0, 15, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION_END_BASE_R", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_RGAM_RAMA_REGION_0_1[] = { + { "CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_RGAM_RAMA_REGION_2_3[] = { + { "CM_RGAM_RAMA_EXP_REGION2_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION2_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION3_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION3_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_RGAM_RAMA_REGION_4_5[] = { + { "CM_RGAM_RAMA_EXP_REGION4_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION4_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION5_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION5_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_RGAM_RAMA_REGION_6_7[] = { + { "CM_RGAM_RAMA_EXP_REGION6_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION6_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION7_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION7_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_RGAM_RAMA_REGION_8_9[] = { + { "CM_RGAM_RAMA_EXP_REGION8_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION8_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION9_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION9_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_RGAM_RAMA_REGION_10_11[] = { + { "CM_RGAM_RAMA_EXP_REGION10_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION10_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION11_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION11_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_RGAM_RAMA_REGION_12_13[] = { + { "CM_RGAM_RAMA_EXP_REGION12_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION12_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION13_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION13_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_RGAM_RAMA_REGION_14_15[] = { + { "CM_RGAM_RAMA_EXP_REGION14_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION14_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION15_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION15_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_RGAM_RAMA_REGION_16_17[] = { + { "CM_RGAM_RAMA_EXP_REGION16_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION16_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION17_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION17_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_RGAM_RAMA_REGION_18_19[] = { + { "CM_RGAM_RAMA_EXP_REGION18_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION18_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION19_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION19_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_RGAM_RAMA_REGION_20_21[] = { + { "CM_RGAM_RAMA_EXP_REGION20_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION20_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION21_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION21_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_RGAM_RAMA_REGION_22_23[] = { + { "CM_RGAM_RAMA_EXP_REGION22_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION22_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION23_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION23_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_RGAM_RAMA_REGION_24_25[] = { + { "CM_RGAM_RAMA_EXP_REGION24_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION24_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION25_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION25_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_RGAM_RAMA_REGION_26_27[] = { + { "CM_RGAM_RAMA_EXP_REGION26_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION26_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION27_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION27_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_RGAM_RAMA_REGION_28_29[] = { + { "CM_RGAM_RAMA_EXP_REGION28_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION28_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION29_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION29_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_RGAM_RAMA_REGION_30_31[] = { + { "CM_RGAM_RAMA_EXP_REGION30_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION30_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION31_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION31_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_RGAM_RAMA_REGION_32_33[] = { + { "CM_RGAM_RAMA_EXP_REGION32_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION32_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_RGAM_RAMB_START_CNTL_B[] = { + { "CM_RGAM_RAMB_EXP_REGION_START_B", 0, 17, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B", 20, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_RGAM_RAMB_START_CNTL_G[] = { + { "CM_RGAM_RAMB_EXP_REGION_START_G", 0, 17, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_G", 20, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_RGAM_RAMB_START_CNTL_R[] = { + { "CM_RGAM_RAMB_EXP_REGION_START_R", 0, 17, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_R", 20, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_B[] = { + { "CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_G[] = { + { "CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_R[] = { + { "CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_RGAM_RAMB_END_CNTL1_B[] = { + { "CM_RGAM_RAMB_EXP_REGION_END_B", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_RGAM_RAMB_END_CNTL2_B[] = { + { "CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B", 0, 15, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION_END_BASE_B", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_RGAM_RAMB_END_CNTL1_G[] = { + { "CM_RGAM_RAMB_EXP_REGION_END_G", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_RGAM_RAMB_END_CNTL2_G[] = { + { "CM_RGAM_RAMB_EXP_REGION_END_SLOPE_G", 0, 15, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION_END_BASE_G", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_RGAM_RAMB_END_CNTL1_R[] = { + { "CM_RGAM_RAMB_EXP_REGION_END_R", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_RGAM_RAMB_END_CNTL2_R[] = { + { "CM_RGAM_RAMB_EXP_REGION_END_SLOPE_R", 0, 15, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION_END_BASE_R", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_RGAM_RAMB_REGION_0_1[] = { + { "CM_RGAM_RAMB_EXP_REGION0_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION0_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION1_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION1_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_RGAM_RAMB_REGION_2_3[] = { + { "CM_RGAM_RAMB_EXP_REGION2_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION2_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION3_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION3_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_RGAM_RAMB_REGION_4_5[] = { + { "CM_RGAM_RAMB_EXP_REGION4_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION4_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION5_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION5_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_RGAM_RAMB_REGION_6_7[] = { + { "CM_RGAM_RAMB_EXP_REGION6_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION6_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION7_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION7_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_RGAM_RAMB_REGION_8_9[] = { + { "CM_RGAM_RAMB_EXP_REGION8_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION8_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION9_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION9_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_RGAM_RAMB_REGION_10_11[] = { + { "CM_RGAM_RAMB_EXP_REGION10_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION10_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION11_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION11_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_RGAM_RAMB_REGION_12_13[] = { + { "CM_RGAM_RAMB_EXP_REGION12_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION12_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION13_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION13_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_RGAM_RAMB_REGION_14_15[] = { + { "CM_RGAM_RAMB_EXP_REGION14_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION14_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION15_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION15_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_RGAM_RAMB_REGION_16_17[] = { + { "CM_RGAM_RAMB_EXP_REGION16_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION16_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION17_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION17_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_RGAM_RAMB_REGION_18_19[] = { + { "CM_RGAM_RAMB_EXP_REGION18_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION18_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION19_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION19_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_RGAM_RAMB_REGION_20_21[] = { + { "CM_RGAM_RAMB_EXP_REGION20_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION20_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION21_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION21_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_RGAM_RAMB_REGION_22_23[] = { + { "CM_RGAM_RAMB_EXP_REGION22_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION22_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION23_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION23_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_RGAM_RAMB_REGION_24_25[] = { + { "CM_RGAM_RAMB_EXP_REGION24_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION24_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION25_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION25_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_RGAM_RAMB_REGION_26_27[] = { + { "CM_RGAM_RAMB_EXP_REGION26_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION26_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION27_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION27_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_RGAM_RAMB_REGION_28_29[] = { + { "CM_RGAM_RAMB_EXP_REGION28_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION28_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION29_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION29_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_RGAM_RAMB_REGION_30_31[] = { + { "CM_RGAM_RAMB_EXP_REGION30_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION30_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION31_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION31_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_RGAM_RAMB_REGION_32_33[] = { + { "CM_RGAM_RAMB_EXP_REGION32_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION32_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION33_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION33_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_HDR_MULT_COEF[] = { + { "CM_HDR_MULT_COEF", 0, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_RANGE_CLAMP_CONTROL_R[] = { + { "CM_RANGE_CLAMP_MAX_R", 0, 15, &umr_bitfield_default }, + { "CM_RANGE_CLAMP_MIN_R", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_RANGE_CLAMP_CONTROL_G[] = { + { "CM_RANGE_CLAMP_MAX_G", 0, 15, &umr_bitfield_default }, + { "CM_RANGE_CLAMP_MIN_G", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_RANGE_CLAMP_CONTROL_B[] = { + { "CM_RANGE_CLAMP_MAX_B", 0, 15, &umr_bitfield_default }, + { "CM_RANGE_CLAMP_MIN_B", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_DENORM_CONTROL[] = { + { "CM_DENORM_MODE", 0, 2, &umr_bitfield_default }, + { "CM_DENORM_ROUND_CLAMP", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_CMOUT_CONTROL[] = { + { "CM_CMOUT_ROUND_TRUNC_MODE", 0, 3, &umr_bitfield_default }, + { "CM_CMOUT_SPATIAL_DITHER_EN", 4, 4, &umr_bitfield_default }, + { "CM_CMOUT_SPATIAL_DITHER_MODE", 8, 9, &umr_bitfield_default }, + { "CM_CMOUT_SPATIAL_DITHER_DEPTH", 12, 13, &umr_bitfield_default }, + { "CM_CMOUT_FRAME_RANDOM_ENABLE", 16, 16, &umr_bitfield_default }, + { "CM_CMOUT_RGB_RANDOM_EN", 20, 20, &umr_bitfield_default }, + { "CM_CMOUT_HIGHPASS_RANDOM_ENABLE", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_CMOUT_RANDOM_SEEDS[] = { + { "CM_CMOUT_RAND_R_SEED", 0, 7, &umr_bitfield_default }, + { "CM_CMOUT_RAND_G_SEED", 8, 15, &umr_bitfield_default }, + { "CM_CMOUT_RAND_B_SEED", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_MEM_PWR_CTRL[] = { + { "SHARED_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default }, + { "SHARED_MEM_PWR_DIS", 2, 2, &umr_bitfield_default }, + { "RGAM_MEM_PWR_FORCE", 4, 5, &umr_bitfield_default }, + { "RGAM_MEM_PWR_DIS", 6, 6, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM2_CM_MEM_PWR_STATUS[] = { + { "SHARED_MEM_PWR_STATE", 0, 1, &umr_bitfield_default }, + { "RGAM_MEM_PWR_STATE", 2, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON14_PERFCOUNTER_CNTL[] = { + { "PERFCOUNTER_EVENT_SEL", 0, 8, &umr_bitfield_default }, + { "PERFCOUNTER_CVALUE_SEL", 9, 11, &umr_bitfield_default }, + { "PERFCOUNTER_INC_MODE", 12, 14, &umr_bitfield_default }, + { "PERFCOUNTER_HW_CNTL_SEL", 15, 15, &umr_bitfield_default }, + { "PERFCOUNTER_RUNEN_MODE", 16, 16, &umr_bitfield_default }, + { "PERFCOUNTER_CNTOFF_START_DIS", 22, 22, &umr_bitfield_default }, + { "PERFCOUNTER_RESTART_EN", 23, 23, &umr_bitfield_default }, + { "PERFCOUNTER_INT_EN", 24, 24, &umr_bitfield_default }, + { "PERFCOUNTER_OFF_MASK", 25, 25, &umr_bitfield_default }, + { "PERFCOUNTER_ACTIVE", 26, 26, &umr_bitfield_default }, + { "PERFCOUNTER_CNTL_SEL", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON14_PERFCOUNTER_CNTL2[] = { + { "PERFCOUNTER_COUNTED_VALUE_TYPE", 0, 1, &umr_bitfield_default }, + { "PERFCOUNTER_HW_STOP1_SEL", 2, 2, &umr_bitfield_default }, + { "PERFCOUNTER_HW_STOP2_SEL", 3, 3, &umr_bitfield_default }, + { "PERFCOUNTER_CNTOFF_SEL", 8, 13, &umr_bitfield_default }, + { "PERFCOUNTER_CNTL2_SEL", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON14_PERFCOUNTER_STATE[] = { + { "PERFCOUNTER_CNT0_STATE", 0, 1, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL0", 2, 2, &umr_bitfield_default }, + { "PERFCOUNTER_CNT1_STATE", 4, 5, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL1", 6, 6, &umr_bitfield_default }, + { "PERFCOUNTER_CNT2_STATE", 8, 9, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL2", 10, 10, &umr_bitfield_default }, + { "PERFCOUNTER_CNT3_STATE", 12, 13, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL3", 14, 14, &umr_bitfield_default }, + { "PERFCOUNTER_CNT4_STATE", 16, 17, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL4", 18, 18, &umr_bitfield_default }, + { "PERFCOUNTER_CNT5_STATE", 20, 21, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL5", 22, 22, &umr_bitfield_default }, + { "PERFCOUNTER_CNT6_STATE", 24, 25, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL6", 26, 26, &umr_bitfield_default }, + { "PERFCOUNTER_CNT7_STATE", 28, 29, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL7", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON14_PERFMON_CNTL[] = { + { "PERFMON_STATE", 0, 1, &umr_bitfield_default }, + { "PERFMON_RPT_COUNT", 8, 27, &umr_bitfield_default }, + { "PERFMON_CNTOFF_AND_OR", 28, 28, &umr_bitfield_default }, + { "PERFMON_CNTOFF_INT_EN", 29, 29, &umr_bitfield_default }, + { "PERFMON_CNTOFF_INT_STATUS", 30, 30, &umr_bitfield_default }, + { "PERFMON_CNTOFF_INT_ACK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON14_PERFMON_CNTL2[] = { + { "PERFMON_CNTOFF_INT_TYPE", 0, 0, &umr_bitfield_default }, + { "PERFMON_CLK_ENABLE", 1, 1, &umr_bitfield_default }, + { "PERFMON_RUN_ENABLE_START_SEL", 2, 9, &umr_bitfield_default }, + { "PERFMON_RUN_ENABLE_STOP_SEL", 10, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON14_PERFMON_CVALUE_INT_MISC[] = { + { "PERFCOUNTER_INT0_STATUS", 0, 0, &umr_bitfield_default }, + { "PERFCOUNTER_INT1_STATUS", 1, 1, &umr_bitfield_default }, + { "PERFCOUNTER_INT2_STATUS", 2, 2, &umr_bitfield_default }, + { "PERFCOUNTER_INT3_STATUS", 3, 3, &umr_bitfield_default }, + { "PERFCOUNTER_INT4_STATUS", 4, 4, &umr_bitfield_default }, + { "PERFCOUNTER_INT5_STATUS", 5, 5, &umr_bitfield_default }, + { "PERFCOUNTER_INT6_STATUS", 6, 6, &umr_bitfield_default }, + { "PERFCOUNTER_INT7_STATUS", 7, 7, &umr_bitfield_default }, + { "PERFCOUNTER_INT0_ACK", 8, 8, &umr_bitfield_default }, + { "PERFCOUNTER_INT1_ACK", 9, 9, &umr_bitfield_default }, + { "PERFCOUNTER_INT2_ACK", 10, 10, &umr_bitfield_default }, + { "PERFCOUNTER_INT3_ACK", 11, 11, &umr_bitfield_default }, + { "PERFCOUNTER_INT4_ACK", 12, 12, &umr_bitfield_default }, + { "PERFCOUNTER_INT5_ACK", 13, 13, &umr_bitfield_default }, + { "PERFCOUNTER_INT6_ACK", 14, 14, &umr_bitfield_default }, + { "PERFCOUNTER_INT7_ACK", 15, 15, &umr_bitfield_default }, + { "PERFMON_CVALUE_HI", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON14_PERFMON_CVALUE_LOW[] = { + { "PERFMON_CVALUE_LOW", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON14_PERFMON_HI[] = { + { "PERFMON_HI", 0, 15, &umr_bitfield_default }, + { "PERFMON_READ_SEL", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON14_PERFMON_LOW[] = { + { "PERFMON_LOW", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDPP_TOP3_DPP_CONTROL[] = { + { "DPP_CLOCK_ENABLE", 4, 4, &umr_bitfield_default }, + { "DPPCLK_G_GATE_DISABLE", 8, 8, &umr_bitfield_default }, + { "DPPCLK_G_DYN_GATE_DISABLE", 10, 10, &umr_bitfield_default }, + { "DPPCLK_G_DSCL_GATE_DISABLE", 12, 12, &umr_bitfield_default }, + { "DPPCLK_R_GATE_DISABLE", 16, 16, &umr_bitfield_default }, + { "DISPCLK_R_GATE_DISABLE", 18, 18, &umr_bitfield_default }, + { "DISPCLK_G_GATE_DISABLE", 20, 20, &umr_bitfield_default }, + { "DPPCLK_RATE_CONTROL", 24, 24, &umr_bitfield_default }, + { "DPP_TEST_CLK_SEL", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDPP_TOP3_DPP_SOFT_RESET[] = { + { "CNVC_SOFT_RESET", 0, 0, &umr_bitfield_default }, + { "DSCL_SOFT_RESET", 4, 4, &umr_bitfield_default }, + { "CM_SOFT_RESET", 8, 8, &umr_bitfield_default }, + { "OBUF_SOFT_RESET", 12, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDPP_TOP3_DPP_CRC_VAL_R_G[] = { + { "DPP_CRC_R_CR", 0, 15, &umr_bitfield_default }, + { "DPP_CRC_G_Y", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDPP_TOP3_DPP_CRC_VAL_B_A[] = { + { "DPP_CRC_B_CB", 0, 15, &umr_bitfield_default }, + { "DPP_CRC_ALPHA", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDPP_TOP3_DPP_CRC_CTRL[] = { + { "DPP_CRC_EN", 0, 0, &umr_bitfield_default }, + { "DPP_CRC_CONT_EN", 1, 1, &umr_bitfield_default }, + { "DPP_CRC_ONE_SHOT_PENDING", 2, 2, &umr_bitfield_default }, + { "DPP_CRC_420_COMP_SEL", 3, 3, &umr_bitfield_default }, + { "DPP_CRC_SRC_SEL", 4, 5, &umr_bitfield_default }, + { "DPP_CRC_STEREO_EN", 7, 7, &umr_bitfield_default }, + { "DPP_CRC_STEREO_MODE", 8, 9, &umr_bitfield_default }, + { "DPP_CRC_INTERLACE_MODE", 10, 11, &umr_bitfield_default }, + { "DPP_CRC_PIX_FORMAT_SEL", 12, 14, &umr_bitfield_default }, + { "DPP_CRC_CURSOR_FORMAT_SEL", 15, 15, &umr_bitfield_default }, + { "DPP_CRC_MASK", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDPP_TOP3_HOST_READ_CONTROL[] = { + { "HOST_READ_RATE_CONTROL", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT[] = { + { "CNVC_SURFACE_PIXEL_FORMAT", 0, 6, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNVC_CFG3_FORMAT_CONTROL[] = { + { "FORMAT_EXPANSION_MODE", 0, 0, &umr_bitfield_default }, + { "FORMAT_CNV16", 4, 4, &umr_bitfield_default }, + { "ALPHA_EN", 8, 8, &umr_bitfield_default }, + { "CNVC_BYPASS", 12, 12, &umr_bitfield_default }, + { "OUTPUT_FP", 16, 16, &umr_bitfield_default }, + { "CNVC_UPDATE_PENDING", 20, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNVC_CFG3_FCNV_FP_SCALE_BIAS[] = { + { "FCNV_FP_SCALE", 0, 15, &umr_bitfield_default }, + { "FCNV_FP_BIAS", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNVC_CFG3_DENORM_CONTROL[] = { + { "DENORM_SCALE", 0, 14, &umr_bitfield_default }, + { "CLAMP_POSITIVE", 15, 15, &umr_bitfield_default }, + { "DENORM_BIAS", 16, 30, &umr_bitfield_default }, + { "DENORM_TRUNCATE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNVC_CFG3_COLOR_KEYER_CONTROL[] = { + { "COLOR_KEYER_EN", 0, 0, &umr_bitfield_default }, + { "COLOR_KEYER_MODE", 4, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNVC_CFG3_COLOR_KEYER_ALPHA[] = { + { "COLOR_KEYER_ALPHA_LOW", 0, 15, &umr_bitfield_default }, + { "COLOR_KEYER_ALPHA_HIGH", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNVC_CFG3_COLOR_KEYER_RED[] = { + { "COLOR_KEYER_RED_LOW", 0, 15, &umr_bitfield_default }, + { "COLOR_KEYER_RED_HIGH", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNVC_CFG3_COLOR_KEYER_GREEN[] = { + { "COLOR_KEYER_GREEN_LOW", 0, 15, &umr_bitfield_default }, + { "COLOR_KEYER_GREEN_HIGH", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNVC_CFG3_COLOR_KEYER_BLUE[] = { + { "COLOR_KEYER_BLUE_LOW", 0, 15, &umr_bitfield_default }, + { "COLOR_KEYER_BLUE_HIGH", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNVC_CUR3_CURSOR0_CONTROL[] = { + { "CUR0_ENABLE", 0, 0, &umr_bitfield_default }, + { "CUR0_EXPANSION_MODE", 1, 1, &umr_bitfield_default }, + { "CUR0_INVERT_MODE", 2, 2, &umr_bitfield_default }, + { "CUR0_MODE", 4, 5, &umr_bitfield_default }, + { "CUR0_UPDATE_PENDING", 6, 6, &umr_bitfield_default }, + { "CUR0_MAX", 8, 19, &umr_bitfield_default }, + { "CUR0_MIN", 20, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNVC_CUR3_CURSOR0_COLOR0[] = { + { "CUR0_COLOR0", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNVC_CUR3_CURSOR0_COLOR1[] = { + { "CUR0_COLOR1", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCNVC_CUR3_CURSOR0_FP_SCALE_BIAS[] = { + { "CUR0_FP_SCALE", 0, 15, &umr_bitfield_default }, + { "CUR0_FP_BIAS", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL3_SCL_COEF_RAM_TAP_SELECT[] = { + { "SCL_COEF_RAM_TAP_PAIR_IDX", 0, 1, &umr_bitfield_default }, + { "SCL_COEF_RAM_PHASE", 8, 13, &umr_bitfield_default }, + { "SCL_COEF_RAM_FILTER_TYPE", 16, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL3_SCL_COEF_RAM_TAP_DATA[] = { + { "SCL_COEF_RAM_EVEN_TAP_COEF", 0, 13, &umr_bitfield_default }, + { "SCL_COEF_RAM_EVEN_TAP_COEF_EN", 15, 15, &umr_bitfield_default }, + { "SCL_COEF_RAM_ODD_TAP_COEF", 16, 29, &umr_bitfield_default }, + { "SCL_COEF_RAM_ODD_TAP_COEF_EN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL3_SCL_MODE[] = { + { "DSCL_MODE", 0, 2, &umr_bitfield_default }, + { "SCL_COEF_RAM_SELECT", 8, 8, &umr_bitfield_default }, + { "SCL_COEF_RAM_SELECT_CURRENT", 12, 12, &umr_bitfield_default }, + { "SCL_CHROMA_COEF_MODE", 16, 16, &umr_bitfield_default }, + { "SCL_ALPHA_COEF_MODE", 20, 20, &umr_bitfield_default }, + { "SCL_COEF_RAM_SELECT_RD", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL3_SCL_TAP_CONTROL[] = { + { "SCL_V_NUM_TAPS", 0, 2, &umr_bitfield_default }, + { "SCL_H_NUM_TAPS", 4, 6, &umr_bitfield_default }, + { "SCL_V_NUM_TAPS_C", 8, 10, &umr_bitfield_default }, + { "SCL_H_NUM_TAPS_C", 12, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL3_DSCL_CONTROL[] = { + { "SCL_BOUNDARY_MODE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL3_DSCL_2TAP_CONTROL[] = { + { "SCL_H_2TAP_HARDCODE_COEF_EN", 0, 0, &umr_bitfield_default }, + { "SCL_H_2TAP_SHARP_EN", 4, 4, &umr_bitfield_default }, + { "SCL_H_2TAP_SHARP_FACTOR", 8, 10, &umr_bitfield_default }, + { "SCL_V_2TAP_HARDCODE_COEF_EN", 16, 16, &umr_bitfield_default }, + { "SCL_V_2TAP_SHARP_EN", 20, 20, &umr_bitfield_default }, + { "SCL_V_2TAP_SHARP_FACTOR", 24, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL3_SCL_MANUAL_REPLICATE_CONTROL[] = { + { "SCL_V_MANUAL_REPLICATE_FACTOR", 0, 3, &umr_bitfield_default }, + { "SCL_H_MANUAL_REPLICATE_FACTOR", 8, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO[] = { + { "SCL_H_SCALE_RATIO", 0, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL3_SCL_HORZ_FILTER_INIT[] = { + { "SCL_H_INIT_FRAC", 0, 23, &umr_bitfield_default }, + { "SCL_H_INIT_INT", 24, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C[] = { + { "SCL_H_SCALE_RATIO_C", 0, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL3_SCL_HORZ_FILTER_INIT_C[] = { + { "SCL_H_INIT_FRAC_C", 0, 23, &umr_bitfield_default }, + { "SCL_H_INIT_INT_C", 24, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO[] = { + { "SCL_V_SCALE_RATIO", 0, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL3_SCL_VERT_FILTER_INIT[] = { + { "SCL_V_INIT_FRAC", 0, 23, &umr_bitfield_default }, + { "SCL_V_INIT_INT", 24, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL3_SCL_VERT_FILTER_INIT_BOT[] = { + { "SCL_V_INIT_FRAC_BOT", 0, 23, &umr_bitfield_default }, + { "SCL_V_INIT_INT_BOT", 24, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C[] = { + { "SCL_V_SCALE_RATIO_C", 0, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL3_SCL_VERT_FILTER_INIT_C[] = { + { "SCL_V_INIT_FRAC_C", 0, 23, &umr_bitfield_default }, + { "SCL_V_INIT_INT_C", 24, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL3_SCL_VERT_FILTER_INIT_BOT_C[] = { + { "SCL_V_INIT_FRAC_BOT_C", 0, 23, &umr_bitfield_default }, + { "SCL_V_INIT_INT_BOT_C", 24, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL3_SCL_BLACK_OFFSET[] = { + { "SCL_BLACK_OFFSET_RGB_Y", 0, 15, &umr_bitfield_default }, + { "SCL_BLACK_OFFSET_CBCR", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL3_DSCL_UPDATE[] = { + { "SCL_UPDATE_PENDING", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL3_DSCL_AUTOCAL[] = { + { "AUTOCAL_MODE", 0, 1, &umr_bitfield_default }, + { "AUTOCAL_NUM_PIPE", 8, 9, &umr_bitfield_default }, + { "AUTOCAL_PIPE_ID", 12, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT[] = { + { "EXT_OVERSCAN_RIGHT", 0, 12, &umr_bitfield_default }, + { "EXT_OVERSCAN_LEFT", 16, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM[] = { + { "EXT_OVERSCAN_BOTTOM", 0, 12, &umr_bitfield_default }, + { "EXT_OVERSCAN_TOP", 16, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL3_OTG_H_BLANK[] = { + { "OTG_H_BLANK_START", 0, 13, &umr_bitfield_default }, + { "OTG_H_BLANK_END", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL3_OTG_V_BLANK[] = { + { "OTG_V_BLANK_START", 0, 13, &umr_bitfield_default }, + { "OTG_V_BLANK_END", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL3_RECOUT_START[] = { + { "RECOUT_START_X", 0, 12, &umr_bitfield_default }, + { "RECOUT_START_Y", 16, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL3_RECOUT_SIZE[] = { + { "RECOUT_WIDTH", 0, 13, &umr_bitfield_default }, + { "RECOUT_HEIGHT", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL3_MPC_SIZE[] = { + { "MPC_WIDTH", 0, 13, &umr_bitfield_default }, + { "MPC_HEIGHT", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL3_LB_DATA_FORMAT[] = { + { "PIXEL_DEPTH", 0, 1, &umr_bitfield_default }, + { "PIXEL_EXPAN_MODE", 8, 8, &umr_bitfield_default }, + { "PIXEL_REDUCE_MODE", 12, 12, &umr_bitfield_default }, + { "DYNAMIC_PIXEL_DEPTH", 16, 16, &umr_bitfield_default }, + { "DITHER_EN", 20, 20, &umr_bitfield_default }, + { "INTERLEAVE_EN", 24, 24, &umr_bitfield_default }, + { "ALPHA_EN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL3_LB_MEMORY_CTRL[] = { + { "MEMORY_CONFIG", 0, 1, &umr_bitfield_default }, + { "LB_MAX_PARTITIONS", 8, 13, &umr_bitfield_default }, + { "LB_NUM_PARTITIONS", 16, 22, &umr_bitfield_default }, + { "LB_NUM_PARTITIONS_C", 24, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL3_LB_V_COUNTER[] = { + { "V_COUNTER", 0, 12, &umr_bitfield_default }, + { "V_COUNTER_C", 16, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL3_DSCL_MEM_PWR_CTRL[] = { + { "LUT_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default }, + { "LUT_MEM_PWR_DIS", 2, 2, &umr_bitfield_default }, + { "LB_G1_MEM_PWR_FORCE", 4, 5, &umr_bitfield_default }, + { "LB_G1_MEM_PWR_DIS", 6, 6, &umr_bitfield_default }, + { "LB_G2_MEM_PWR_FORCE", 8, 9, &umr_bitfield_default }, + { "LB_G2_MEM_PWR_DIS", 10, 10, &umr_bitfield_default }, + { "LB_G3_MEM_PWR_FORCE", 12, 13, &umr_bitfield_default }, + { "LB_G3_MEM_PWR_DIS", 14, 14, &umr_bitfield_default }, + { "LB_G4_MEM_PWR_FORCE", 16, 17, &umr_bitfield_default }, + { "LB_G4_MEM_PWR_DIS", 18, 18, &umr_bitfield_default }, + { "LB_G5_MEM_PWR_FORCE", 20, 21, &umr_bitfield_default }, + { "LB_G5_MEM_PWR_DIS", 22, 22, &umr_bitfield_default }, + { "LB_G6_MEM_PWR_FORCE", 24, 25, &umr_bitfield_default }, + { "LB_G6_MEM_PWR_DIS", 26, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL3_DSCL_MEM_PWR_STATUS[] = { + { "LUT_MEM_PWR_STATE", 0, 1, &umr_bitfield_default }, + { "LB_G1_MEM_PWR_STATE", 2, 3, &umr_bitfield_default }, + { "LB_G2_MEM_PWR_STATE", 4, 5, &umr_bitfield_default }, + { "LB_G3_MEM_PWR_STATE", 6, 7, &umr_bitfield_default }, + { "LB_G4_MEM_PWR_STATE", 8, 9, &umr_bitfield_default }, + { "LB_G5_MEM_PWR_STATE", 10, 11, &umr_bitfield_default }, + { "LB_G6_MEM_PWR_STATE", 12, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL3_OBUF_CONTROL[] = { + { "OBUF_BYPASS", 0, 0, &umr_bitfield_default }, + { "OBUF_USE_FULL_BUFFER", 4, 4, &umr_bitfield_default }, + { "OBUF_H_2X_UPSCALE_EN", 8, 8, &umr_bitfield_default }, + { "OBUF_IS_HALF_RECOUT_WIDTH", 12, 12, &umr_bitfield_default }, + { "OBUF_H_2X_COEF_PHASE0_SEL", 16, 16, &umr_bitfield_default }, + { "OBUF_H_2X_COEF_PHASE1_SEL", 24, 24, &umr_bitfield_default }, + { "OBUF_OUT_HOLD_CNT", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDSCL3_OBUF_MEM_PWR_CTRL[] = { + { "OBUF_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default }, + { "OBUF_MEM_PWR_DIS", 2, 2, &umr_bitfield_default }, + { "OBUF_MEM_PWR_STATE", 16, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_CONTROL[] = { + { "CM_BYPASS_EN", 0, 0, &umr_bitfield_default }, + { "CM_UPDATE_PENDING", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_COMA_C11_C12[] = { + { "CM_COMA_C11", 0, 15, &umr_bitfield_default }, + { "CM_COMA_C12", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_COMA_C13_C14[] = { + { "CM_COMA_C13", 0, 15, &umr_bitfield_default }, + { "CM_COMA_C14", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_COMA_C21_C22[] = { + { "CM_COMA_C21", 0, 15, &umr_bitfield_default }, + { "CM_COMA_C22", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_COMA_C23_C24[] = { + { "CM_COMA_C23", 0, 15, &umr_bitfield_default }, + { "CM_COMA_C24", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_COMA_C31_C32[] = { + { "CM_COMA_C31", 0, 15, &umr_bitfield_default }, + { "CM_COMA_C32", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_COMA_C33_C34[] = { + { "CM_COMA_C33", 0, 15, &umr_bitfield_default }, + { "CM_COMA_C34", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_COMB_C11_C12[] = { + { "CM_COMB_C11", 0, 15, &umr_bitfield_default }, + { "CM_COMB_C12", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_COMB_C13_C14[] = { + { "CM_COMB_C13", 0, 15, &umr_bitfield_default }, + { "CM_COMB_C14", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_COMB_C21_C22[] = { + { "CM_COMB_C21", 0, 15, &umr_bitfield_default }, + { "CM_COMB_C22", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_COMB_C23_C24[] = { + { "CM_COMB_C23", 0, 15, &umr_bitfield_default }, + { "CM_COMB_C24", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_COMB_C31_C32[] = { + { "CM_COMB_C31", 0, 15, &umr_bitfield_default }, + { "CM_COMB_C32", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_COMB_C33_C34[] = { + { "CM_COMB_C33", 0, 15, &umr_bitfield_default }, + { "CM_COMB_C34", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_IGAM_CONTROL[] = { + { "CM_IGAM_LUT_MODE", 0, 1, &umr_bitfield_default }, + { "CM_IGAM_LUT_DATA_SIGNED_EN_B", 2, 2, &umr_bitfield_default }, + { "CM_IGAM_LUT_DATA_SIGNED_EN_G", 3, 3, &umr_bitfield_default }, + { "CM_IGAM_LUT_DATA_SIGNED_EN_R", 4, 4, &umr_bitfield_default }, + { "CM_IGAM_LUT_INC_B", 5, 8, &umr_bitfield_default }, + { "CM_IGAM_LUT_INC_G", 9, 12, &umr_bitfield_default }, + { "CM_IGAM_LUT_INC_R", 13, 16, &umr_bitfield_default }, + { "CM_IGAM_LUT_FORMAT_B", 17, 18, &umr_bitfield_default }, + { "CM_IGAM_LUT_FORMAT_G", 19, 20, &umr_bitfield_default }, + { "CM_IGAM_LUT_FORMAT_R", 21, 22, &umr_bitfield_default }, + { "CM_IGAM_LUT_B_FLOAT_POINT_EN", 23, 23, &umr_bitfield_default }, + { "CM_IGAM_LUT_G_FLOAT_POINT_EN", 24, 24, &umr_bitfield_default }, + { "CM_IGAM_LUT_R_FLOAT_POINT_EN", 25, 25, &umr_bitfield_default }, + { "CM_IGAM_INPUT_FORMAT", 26, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_IGAM_LUT_RW_CONTROL[] = { + { "CM_IGAM_LUT_RW_MODE", 0, 0, &umr_bitfield_default }, + { "CM_IGAM_LUT_WRITE_EN_MASK", 4, 6, &umr_bitfield_default }, + { "CM_IGAM_LUT_SEL", 8, 8, &umr_bitfield_default }, + { "CM_IGAM_LUT_HOST_EN", 12, 12, &umr_bitfield_default }, + { "CM_IGAM_DGAM_CONFIG_STATUS", 16, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_IGAM_LUT_RW_INDEX[] = { + { "CM_IGAM_LUT_RW_INDEX", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_IGAM_LUT_SEQ_COLOR[] = { + { "CM_IGAM_LUT_SEQ_COLOR", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_IGAM_LUT_30_COLOR[] = { + { "CM_IGAM_LUT_10_BLUE", 0, 9, &umr_bitfield_default }, + { "CM_IGAM_LUT_10_GREEN", 10, 19, &umr_bitfield_default }, + { "CM_IGAM_LUT_10_RED", 20, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_IGAM_LUT_PWL_DATA[] = { + { "CM_IGAM_LUT_PWL_BASE", 0, 15, &umr_bitfield_default }, + { "CM_IGAM_LUT_PWL_DELTA", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_IGAM_LUT_AUTOFILL[] = { + { "CM_IGAM_LUT_AUTOFILL", 0, 0, &umr_bitfield_default }, + { "CM_IGAM_LUT_AUTOFILL_DONE", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_IGAM_LUT_BW_OFFSET_BLUE[] = { + { "CM_IGAM_LUT_BLACK_OFFSET_BLUE", 0, 15, &umr_bitfield_default }, + { "CM_IGAM_LUT_WHITE_OFFSET_BLUE", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_IGAM_LUT_BW_OFFSET_GREEN[] = { + { "CM_IGAM_LUT_BLACK_OFFSET_GREEN", 0, 15, &umr_bitfield_default }, + { "CM_IGAM_LUT_WHITE_OFFSET_GREEN", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_IGAM_LUT_BW_OFFSET_RED[] = { + { "CM_IGAM_LUT_BLACK_OFFSET_RED", 0, 15, &umr_bitfield_default }, + { "CM_IGAM_LUT_WHITE_OFFSET_RED", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_ICSC_CONTROL[] = { + { "CM_ICSC_MODE", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_ICSC_C11_C12[] = { + { "CM_ICSC_C11", 0, 15, &umr_bitfield_default }, + { "CM_ICSC_C12", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_ICSC_C13_C14[] = { + { "CM_ICSC_C13", 0, 15, &umr_bitfield_default }, + { "CM_ICSC_C14", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_ICSC_C21_C22[] = { + { "CM_ICSC_C21", 0, 15, &umr_bitfield_default }, + { "CM_ICSC_C22", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_ICSC_C23_C24[] = { + { "CM_ICSC_C23", 0, 15, &umr_bitfield_default }, + { "CM_ICSC_C24", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_ICSC_C31_C32[] = { + { "CM_ICSC_C31", 0, 15, &umr_bitfield_default }, + { "CM_ICSC_C32", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_ICSC_C33_C34[] = { + { "CM_ICSC_C33", 0, 15, &umr_bitfield_default }, + { "CM_ICSC_C34", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_GAMUT_REMAP_CONTROL[] = { + { "CM_GAMUT_REMAP_MODE", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_GAMUT_REMAP_C11_C12[] = { + { "CM_GAMUT_REMAP_C11", 0, 15, &umr_bitfield_default }, + { "CM_GAMUT_REMAP_C12", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_GAMUT_REMAP_C13_C14[] = { + { "CM_GAMUT_REMAP_C13", 0, 15, &umr_bitfield_default }, + { "CM_GAMUT_REMAP_C14", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_GAMUT_REMAP_C21_C22[] = { + { "CM_GAMUT_REMAP_C21", 0, 15, &umr_bitfield_default }, + { "CM_GAMUT_REMAP_C22", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_GAMUT_REMAP_C23_C24[] = { + { "CM_GAMUT_REMAP_C23", 0, 15, &umr_bitfield_default }, + { "CM_GAMUT_REMAP_C24", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_GAMUT_REMAP_C31_C32[] = { + { "CM_GAMUT_REMAP_C31", 0, 15, &umr_bitfield_default }, + { "CM_GAMUT_REMAP_C32", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_GAMUT_REMAP_C33_C34[] = { + { "CM_GAMUT_REMAP_C33", 0, 15, &umr_bitfield_default }, + { "CM_GAMUT_REMAP_C34", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_OCSC_CONTROL[] = { + { "CM_OCSC_MODE", 0, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_OCSC_C11_C12[] = { + { "CM_OCSC_C11", 0, 15, &umr_bitfield_default }, + { "CM_OCSC_C12", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_OCSC_C13_C14[] = { + { "CM_OCSC_C13", 0, 15, &umr_bitfield_default }, + { "CM_OCSC_C14", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_OCSC_C21_C22[] = { + { "CM_OCSC_C21", 0, 15, &umr_bitfield_default }, + { "CM_OCSC_C22", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_OCSC_C23_C24[] = { + { "CM_OCSC_C23", 0, 15, &umr_bitfield_default }, + { "CM_OCSC_C24", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_OCSC_C31_C32[] = { + { "CM_OCSC_C31", 0, 15, &umr_bitfield_default }, + { "CM_OCSC_C32", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_OCSC_C33_C34[] = { + { "CM_OCSC_C33", 0, 15, &umr_bitfield_default }, + { "CM_OCSC_C34", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_BNS_VALUES_R[] = { + { "CM_BNS_BIAS_R", 0, 15, &umr_bitfield_default }, + { "CM_BNS_SCALE_R", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_BNS_VALUES_G[] = { + { "CM_BNS_BIAS_G", 0, 15, &umr_bitfield_default }, + { "CM_BNS_SCALE_G", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_BNS_VALUES_B[] = { + { "CM_BNS_BIAS_B", 0, 15, &umr_bitfield_default }, + { "CM_BNS_SCALE_B", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_DGAM_CONTROL[] = { + { "CM_DGAM_LUT_MODE", 0, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_DGAM_LUT_INDEX[] = { + { "CM_DGAM_LUT_INDEX", 0, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_DGAM_LUT_DATA[] = { + { "CM_DGAM_LUT_DATA", 0, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_DGAM_LUT_WRITE_EN_MASK[] = { + { "CM_DGAM_LUT_WRITE_EN_MASK", 0, 2, &umr_bitfield_default }, + { "CM_DGAM_LUT_WRITE_SEL", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_DGAM_RAMA_START_CNTL_B[] = { + { "CM_DGAM_RAMA_EXP_REGION_START_B", 0, 17, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B", 20, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_DGAM_RAMA_START_CNTL_G[] = { + { "CM_DGAM_RAMA_EXP_REGION_START_G", 0, 17, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G", 20, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_DGAM_RAMA_START_CNTL_R[] = { + { "CM_DGAM_RAMA_EXP_REGION_START_R", 0, 17, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R", 20, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_B[] = { + { "CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_G[] = { + { "CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_R[] = { + { "CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_DGAM_RAMA_END_CNTL1_B[] = { + { "CM_DGAM_RAMA_EXP_REGION_END_B", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_DGAM_RAMA_END_CNTL2_B[] = { + { "CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B", 0, 15, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION_END_BASE_B", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_DGAM_RAMA_END_CNTL1_G[] = { + { "CM_DGAM_RAMA_EXP_REGION_END_G", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_DGAM_RAMA_END_CNTL2_G[] = { + { "CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G", 0, 15, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION_END_BASE_G", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_DGAM_RAMA_END_CNTL1_R[] = { + { "CM_DGAM_RAMA_EXP_REGION_END_R", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_DGAM_RAMA_END_CNTL2_R[] = { + { "CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R", 0, 15, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION_END_BASE_R", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_DGAM_RAMA_REGION_0_1[] = { + { "CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_DGAM_RAMA_REGION_2_3[] = { + { "CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_DGAM_RAMA_REGION_4_5[] = { + { "CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_DGAM_RAMA_REGION_6_7[] = { + { "CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_DGAM_RAMA_REGION_8_9[] = { + { "CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_DGAM_RAMA_REGION_10_11[] = { + { "CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_DGAM_RAMA_REGION_12_13[] = { + { "CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_DGAM_RAMA_REGION_14_15[] = { + { "CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_DGAM_RAMB_START_CNTL_B[] = { + { "CM_DGAM_RAMB_EXP_REGION_START_B", 0, 17, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B", 20, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_DGAM_RAMB_START_CNTL_G[] = { + { "CM_DGAM_RAMB_EXP_REGION_START_G", 0, 17, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G", 20, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_DGAM_RAMB_START_CNTL_R[] = { + { "CM_DGAM_RAMB_EXP_REGION_START_R", 0, 17, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R", 20, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_B[] = { + { "CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_G[] = { + { "CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_R[] = { + { "CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_DGAM_RAMB_END_CNTL1_B[] = { + { "CM_DGAM_RAMB_EXP_REGION_END_B", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_DGAM_RAMB_END_CNTL2_B[] = { + { "CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B", 0, 15, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION_END_BASE_B", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_DGAM_RAMB_END_CNTL1_G[] = { + { "CM_DGAM_RAMB_EXP_REGION_END_G", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_DGAM_RAMB_END_CNTL2_G[] = { + { "CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G", 0, 15, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION_END_BASE_G", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_DGAM_RAMB_END_CNTL1_R[] = { + { "CM_DGAM_RAMB_EXP_REGION_END_R", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_DGAM_RAMB_END_CNTL2_R[] = { + { "CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R", 0, 15, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION_END_BASE_R", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_DGAM_RAMB_REGION_0_1[] = { + { "CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_DGAM_RAMB_REGION_2_3[] = { + { "CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_DGAM_RAMB_REGION_4_5[] = { + { "CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_DGAM_RAMB_REGION_6_7[] = { + { "CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_DGAM_RAMB_REGION_8_9[] = { + { "CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_DGAM_RAMB_REGION_10_11[] = { + { "CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_DGAM_RAMB_REGION_12_13[] = { + { "CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_DGAM_RAMB_REGION_14_15[] = { + { "CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_RGAM_CONTROL[] = { + { "CM_RGAM_LUT_MODE", 0, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_RGAM_LUT_INDEX[] = { + { "CM_RGAM_LUT_INDEX", 0, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_RGAM_LUT_DATA[] = { + { "CM_RGAM_LUT_DATA", 0, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_RGAM_LUT_WRITE_EN_MASK[] = { + { "CM_RGAM_LUT_WRITE_EN_MASK", 0, 2, &umr_bitfield_default }, + { "CM_RGAM_LUT_WRITE_SEL", 4, 4, &umr_bitfield_default }, + { "CM_RGAM_CONFIG_STATUS", 8, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_RGAM_RAMA_START_CNTL_B[] = { + { "CM_RGAM_RAMA_EXP_REGION_START_B", 0, 17, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_B", 20, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_RGAM_RAMA_START_CNTL_G[] = { + { "CM_RGAM_RAMA_EXP_REGION_START_G", 0, 17, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_G", 20, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_RGAM_RAMA_START_CNTL_R[] = { + { "CM_RGAM_RAMA_EXP_REGION_START_R", 0, 17, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_R", 20, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_B[] = { + { "CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_G[] = { + { "CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_R[] = { + { "CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_RGAM_RAMA_END_CNTL1_B[] = { + { "CM_RGAM_RAMA_EXP_REGION_END_B", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_RGAM_RAMA_END_CNTL2_B[] = { + { "CM_RGAM_RAMA_EXP_REGION_END_SLOPE_B", 0, 15, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION_END_BASE_B", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_RGAM_RAMA_END_CNTL1_G[] = { + { "CM_RGAM_RAMA_EXP_REGION_END_G", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_RGAM_RAMA_END_CNTL2_G[] = { + { "CM_RGAM_RAMA_EXP_REGION_END_SLOPE_G", 0, 15, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION_END_BASE_G", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_RGAM_RAMA_END_CNTL1_R[] = { + { "CM_RGAM_RAMA_EXP_REGION_END_R", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_RGAM_RAMA_END_CNTL2_R[] = { + { "CM_RGAM_RAMA_EXP_REGION_END_SLOPE_R", 0, 15, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION_END_BASE_R", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_RGAM_RAMA_REGION_0_1[] = { + { "CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_RGAM_RAMA_REGION_2_3[] = { + { "CM_RGAM_RAMA_EXP_REGION2_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION2_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION3_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION3_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_RGAM_RAMA_REGION_4_5[] = { + { "CM_RGAM_RAMA_EXP_REGION4_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION4_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION5_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION5_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_RGAM_RAMA_REGION_6_7[] = { + { "CM_RGAM_RAMA_EXP_REGION6_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION6_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION7_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION7_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_RGAM_RAMA_REGION_8_9[] = { + { "CM_RGAM_RAMA_EXP_REGION8_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION8_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION9_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION9_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_RGAM_RAMA_REGION_10_11[] = { + { "CM_RGAM_RAMA_EXP_REGION10_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION10_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION11_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION11_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_RGAM_RAMA_REGION_12_13[] = { + { "CM_RGAM_RAMA_EXP_REGION12_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION12_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION13_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION13_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_RGAM_RAMA_REGION_14_15[] = { + { "CM_RGAM_RAMA_EXP_REGION14_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION14_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION15_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION15_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_RGAM_RAMA_REGION_16_17[] = { + { "CM_RGAM_RAMA_EXP_REGION16_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION16_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION17_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION17_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_RGAM_RAMA_REGION_18_19[] = { + { "CM_RGAM_RAMA_EXP_REGION18_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION18_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION19_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION19_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_RGAM_RAMA_REGION_20_21[] = { + { "CM_RGAM_RAMA_EXP_REGION20_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION20_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION21_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION21_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_RGAM_RAMA_REGION_22_23[] = { + { "CM_RGAM_RAMA_EXP_REGION22_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION22_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION23_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION23_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_RGAM_RAMA_REGION_24_25[] = { + { "CM_RGAM_RAMA_EXP_REGION24_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION24_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION25_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION25_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_RGAM_RAMA_REGION_26_27[] = { + { "CM_RGAM_RAMA_EXP_REGION26_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION26_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION27_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION27_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_RGAM_RAMA_REGION_28_29[] = { + { "CM_RGAM_RAMA_EXP_REGION28_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION28_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION29_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION29_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_RGAM_RAMA_REGION_30_31[] = { + { "CM_RGAM_RAMA_EXP_REGION30_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION30_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION31_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION31_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_RGAM_RAMA_REGION_32_33[] = { + { "CM_RGAM_RAMA_EXP_REGION32_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION32_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_RGAM_RAMB_START_CNTL_B[] = { + { "CM_RGAM_RAMB_EXP_REGION_START_B", 0, 17, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B", 20, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_RGAM_RAMB_START_CNTL_G[] = { + { "CM_RGAM_RAMB_EXP_REGION_START_G", 0, 17, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_G", 20, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_RGAM_RAMB_START_CNTL_R[] = { + { "CM_RGAM_RAMB_EXP_REGION_START_R", 0, 17, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_R", 20, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_B[] = { + { "CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_G[] = { + { "CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_R[] = { + { "CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_RGAM_RAMB_END_CNTL1_B[] = { + { "CM_RGAM_RAMB_EXP_REGION_END_B", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_RGAM_RAMB_END_CNTL2_B[] = { + { "CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B", 0, 15, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION_END_BASE_B", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_RGAM_RAMB_END_CNTL1_G[] = { + { "CM_RGAM_RAMB_EXP_REGION_END_G", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_RGAM_RAMB_END_CNTL2_G[] = { + { "CM_RGAM_RAMB_EXP_REGION_END_SLOPE_G", 0, 15, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION_END_BASE_G", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_RGAM_RAMB_END_CNTL1_R[] = { + { "CM_RGAM_RAMB_EXP_REGION_END_R", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_RGAM_RAMB_END_CNTL2_R[] = { + { "CM_RGAM_RAMB_EXP_REGION_END_SLOPE_R", 0, 15, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION_END_BASE_R", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_RGAM_RAMB_REGION_0_1[] = { + { "CM_RGAM_RAMB_EXP_REGION0_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION0_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION1_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION1_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_RGAM_RAMB_REGION_2_3[] = { + { "CM_RGAM_RAMB_EXP_REGION2_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION2_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION3_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION3_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_RGAM_RAMB_REGION_4_5[] = { + { "CM_RGAM_RAMB_EXP_REGION4_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION4_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION5_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION5_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_RGAM_RAMB_REGION_6_7[] = { + { "CM_RGAM_RAMB_EXP_REGION6_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION6_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION7_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION7_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_RGAM_RAMB_REGION_8_9[] = { + { "CM_RGAM_RAMB_EXP_REGION8_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION8_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION9_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION9_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_RGAM_RAMB_REGION_10_11[] = { + { "CM_RGAM_RAMB_EXP_REGION10_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION10_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION11_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION11_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_RGAM_RAMB_REGION_12_13[] = { + { "CM_RGAM_RAMB_EXP_REGION12_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION12_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION13_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION13_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_RGAM_RAMB_REGION_14_15[] = { + { "CM_RGAM_RAMB_EXP_REGION14_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION14_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION15_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION15_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_RGAM_RAMB_REGION_16_17[] = { + { "CM_RGAM_RAMB_EXP_REGION16_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION16_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION17_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION17_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_RGAM_RAMB_REGION_18_19[] = { + { "CM_RGAM_RAMB_EXP_REGION18_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION18_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION19_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION19_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_RGAM_RAMB_REGION_20_21[] = { + { "CM_RGAM_RAMB_EXP_REGION20_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION20_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION21_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION21_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_RGAM_RAMB_REGION_22_23[] = { + { "CM_RGAM_RAMB_EXP_REGION22_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION22_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION23_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION23_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_RGAM_RAMB_REGION_24_25[] = { + { "CM_RGAM_RAMB_EXP_REGION24_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION24_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION25_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION25_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_RGAM_RAMB_REGION_26_27[] = { + { "CM_RGAM_RAMB_EXP_REGION26_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION26_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION27_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION27_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_RGAM_RAMB_REGION_28_29[] = { + { "CM_RGAM_RAMB_EXP_REGION28_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION28_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION29_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION29_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_RGAM_RAMB_REGION_30_31[] = { + { "CM_RGAM_RAMB_EXP_REGION30_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION30_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION31_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION31_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_RGAM_RAMB_REGION_32_33[] = { + { "CM_RGAM_RAMB_EXP_REGION32_LUT_OFFSET", 0, 8, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION32_NUM_SEGMENTS", 12, 14, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION33_LUT_OFFSET", 16, 24, &umr_bitfield_default }, + { "CM_RGAM_RAMB_EXP_REGION33_NUM_SEGMENTS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_HDR_MULT_COEF[] = { + { "CM_HDR_MULT_COEF", 0, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_RANGE_CLAMP_CONTROL_R[] = { + { "CM_RANGE_CLAMP_MAX_R", 0, 15, &umr_bitfield_default }, + { "CM_RANGE_CLAMP_MIN_R", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_RANGE_CLAMP_CONTROL_G[] = { + { "CM_RANGE_CLAMP_MAX_G", 0, 15, &umr_bitfield_default }, + { "CM_RANGE_CLAMP_MIN_G", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_RANGE_CLAMP_CONTROL_B[] = { + { "CM_RANGE_CLAMP_MAX_B", 0, 15, &umr_bitfield_default }, + { "CM_RANGE_CLAMP_MIN_B", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_DENORM_CONTROL[] = { + { "CM_DENORM_MODE", 0, 2, &umr_bitfield_default }, + { "CM_DENORM_ROUND_CLAMP", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_CMOUT_CONTROL[] = { + { "CM_CMOUT_ROUND_TRUNC_MODE", 0, 3, &umr_bitfield_default }, + { "CM_CMOUT_SPATIAL_DITHER_EN", 4, 4, &umr_bitfield_default }, + { "CM_CMOUT_SPATIAL_DITHER_MODE", 8, 9, &umr_bitfield_default }, + { "CM_CMOUT_SPATIAL_DITHER_DEPTH", 12, 13, &umr_bitfield_default }, + { "CM_CMOUT_FRAME_RANDOM_ENABLE", 16, 16, &umr_bitfield_default }, + { "CM_CMOUT_RGB_RANDOM_EN", 20, 20, &umr_bitfield_default }, + { "CM_CMOUT_HIGHPASS_RANDOM_ENABLE", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_CMOUT_RANDOM_SEEDS[] = { + { "CM_CMOUT_RAND_R_SEED", 0, 7, &umr_bitfield_default }, + { "CM_CMOUT_RAND_G_SEED", 8, 15, &umr_bitfield_default }, + { "CM_CMOUT_RAND_B_SEED", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_MEM_PWR_CTRL[] = { + { "SHARED_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default }, + { "SHARED_MEM_PWR_DIS", 2, 2, &umr_bitfield_default }, + { "RGAM_MEM_PWR_FORCE", 4, 5, &umr_bitfield_default }, + { "RGAM_MEM_PWR_DIS", 6, 6, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCM3_CM_MEM_PWR_STATUS[] = { + { "SHARED_MEM_PWR_STATE", 0, 1, &umr_bitfield_default }, + { "RGAM_MEM_PWR_STATE", 2, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON15_PERFCOUNTER_CNTL[] = { + { "PERFCOUNTER_EVENT_SEL", 0, 8, &umr_bitfield_default }, + { "PERFCOUNTER_CVALUE_SEL", 9, 11, &umr_bitfield_default }, + { "PERFCOUNTER_INC_MODE", 12, 14, &umr_bitfield_default }, + { "PERFCOUNTER_HW_CNTL_SEL", 15, 15, &umr_bitfield_default }, + { "PERFCOUNTER_RUNEN_MODE", 16, 16, &umr_bitfield_default }, + { "PERFCOUNTER_CNTOFF_START_DIS", 22, 22, &umr_bitfield_default }, + { "PERFCOUNTER_RESTART_EN", 23, 23, &umr_bitfield_default }, + { "PERFCOUNTER_INT_EN", 24, 24, &umr_bitfield_default }, + { "PERFCOUNTER_OFF_MASK", 25, 25, &umr_bitfield_default }, + { "PERFCOUNTER_ACTIVE", 26, 26, &umr_bitfield_default }, + { "PERFCOUNTER_CNTL_SEL", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON15_PERFCOUNTER_CNTL2[] = { + { "PERFCOUNTER_COUNTED_VALUE_TYPE", 0, 1, &umr_bitfield_default }, + { "PERFCOUNTER_HW_STOP1_SEL", 2, 2, &umr_bitfield_default }, + { "PERFCOUNTER_HW_STOP2_SEL", 3, 3, &umr_bitfield_default }, + { "PERFCOUNTER_CNTOFF_SEL", 8, 13, &umr_bitfield_default }, + { "PERFCOUNTER_CNTL2_SEL", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON15_PERFCOUNTER_STATE[] = { + { "PERFCOUNTER_CNT0_STATE", 0, 1, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL0", 2, 2, &umr_bitfield_default }, + { "PERFCOUNTER_CNT1_STATE", 4, 5, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL1", 6, 6, &umr_bitfield_default }, + { "PERFCOUNTER_CNT2_STATE", 8, 9, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL2", 10, 10, &umr_bitfield_default }, + { "PERFCOUNTER_CNT3_STATE", 12, 13, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL3", 14, 14, &umr_bitfield_default }, + { "PERFCOUNTER_CNT4_STATE", 16, 17, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL4", 18, 18, &umr_bitfield_default }, + { "PERFCOUNTER_CNT5_STATE", 20, 21, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL5", 22, 22, &umr_bitfield_default }, + { "PERFCOUNTER_CNT6_STATE", 24, 25, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL6", 26, 26, &umr_bitfield_default }, + { "PERFCOUNTER_CNT7_STATE", 28, 29, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL7", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON15_PERFMON_CNTL[] = { + { "PERFMON_STATE", 0, 1, &umr_bitfield_default }, + { "PERFMON_RPT_COUNT", 8, 27, &umr_bitfield_default }, + { "PERFMON_CNTOFF_AND_OR", 28, 28, &umr_bitfield_default }, + { "PERFMON_CNTOFF_INT_EN", 29, 29, &umr_bitfield_default }, + { "PERFMON_CNTOFF_INT_STATUS", 30, 30, &umr_bitfield_default }, + { "PERFMON_CNTOFF_INT_ACK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON15_PERFMON_CNTL2[] = { + { "PERFMON_CNTOFF_INT_TYPE", 0, 0, &umr_bitfield_default }, + { "PERFMON_CLK_ENABLE", 1, 1, &umr_bitfield_default }, + { "PERFMON_RUN_ENABLE_START_SEL", 2, 9, &umr_bitfield_default }, + { "PERFMON_RUN_ENABLE_STOP_SEL", 10, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON15_PERFMON_CVALUE_INT_MISC[] = { + { "PERFCOUNTER_INT0_STATUS", 0, 0, &umr_bitfield_default }, + { "PERFCOUNTER_INT1_STATUS", 1, 1, &umr_bitfield_default }, + { "PERFCOUNTER_INT2_STATUS", 2, 2, &umr_bitfield_default }, + { "PERFCOUNTER_INT3_STATUS", 3, 3, &umr_bitfield_default }, + { "PERFCOUNTER_INT4_STATUS", 4, 4, &umr_bitfield_default }, + { "PERFCOUNTER_INT5_STATUS", 5, 5, &umr_bitfield_default }, + { "PERFCOUNTER_INT6_STATUS", 6, 6, &umr_bitfield_default }, + { "PERFCOUNTER_INT7_STATUS", 7, 7, &umr_bitfield_default }, + { "PERFCOUNTER_INT0_ACK", 8, 8, &umr_bitfield_default }, + { "PERFCOUNTER_INT1_ACK", 9, 9, &umr_bitfield_default }, + { "PERFCOUNTER_INT2_ACK", 10, 10, &umr_bitfield_default }, + { "PERFCOUNTER_INT3_ACK", 11, 11, &umr_bitfield_default }, + { "PERFCOUNTER_INT4_ACK", 12, 12, &umr_bitfield_default }, + { "PERFCOUNTER_INT5_ACK", 13, 13, &umr_bitfield_default }, + { "PERFCOUNTER_INT6_ACK", 14, 14, &umr_bitfield_default }, + { "PERFCOUNTER_INT7_ACK", 15, 15, &umr_bitfield_default }, + { "PERFMON_CVALUE_HI", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON15_PERFMON_CVALUE_LOW[] = { + { "PERFMON_CVALUE_LOW", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON15_PERFMON_HI[] = { + { "PERFMON_HI", 0, 15, &umr_bitfield_default }, + { "PERFMON_READ_SEL", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON15_PERFMON_LOW[] = { + { "PERFMON_LOW", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPCC0_MPCC_TOP_SEL[] = { + { "MPCC_TOP_SEL", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPCC0_MPCC_BOT_SEL[] = { + { "MPCC_BOT_SEL", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPCC0_MPCC_OPP_ID[] = { + { "MPCC_OPP_ID", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPCC0_MPCC_CONTROL[] = { + { "MPCC_MODE", 0, 1, &umr_bitfield_default }, + { "MPCC_ALPHA_BLND_MODE", 4, 5, &umr_bitfield_default }, + { "MPCC_ALPHA_MULTIPLIED_MODE", 6, 6, &umr_bitfield_default }, + { "MPCC_BLND_ACTIVE_OVERLAP_ONLY", 7, 7, &umr_bitfield_default }, + { "MPCC_GLOBAL_ALPHA", 16, 23, &umr_bitfield_default }, + { "MPCC_GLOBAL_GAIN", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPCC0_MPCC_SM_CONTROL[] = { + { "MPCC_SM_EN", 0, 0, &umr_bitfield_default }, + { "MPCC_SM_MODE", 1, 3, &umr_bitfield_default }, + { "MPCC_SM_FRAME_ALT", 4, 4, &umr_bitfield_default }, + { "MPCC_SM_FIELD_ALT", 5, 5, &umr_bitfield_default }, + { "MPCC_SM_FORCE_NEXT_FRAME_POL", 8, 9, &umr_bitfield_default }, + { "MPCC_SM_FORCE_NEXT_TOP_POL", 16, 17, &umr_bitfield_default }, + { "MPCC_SM_CURRENT_FRAME_POL", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPCC0_MPCC_UPDATE_LOCK_SEL[] = { + { "MPCC_UPDATE_LOCK_SEL", 0, 3, &umr_bitfield_default }, + { "MPCC_UPDATE_LOCKED_STATUS", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPCC0_MPCC_TOP_OFFSET[] = { + { "MPCC_TOP_OFFSET_L", 0, 11, &umr_bitfield_default }, + { "MPCC_TOP_OFFSET_C", 16, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPCC0_MPCC_BOT_OFFSET[] = { + { "MPCC_BOT_OFFSET_L", 0, 11, &umr_bitfield_default }, + { "MPCC_BOT_OFFSET_C", 16, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPCC0_MPCC_OFFSET[] = { + { "MPCC_OFFSET_L", 0, 11, &umr_bitfield_default }, + { "MPCC_OFFSET_C", 16, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPCC0_MPCC_BG_R_CR[] = { + { "MPCC_BG_R_CR", 0, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPCC0_MPCC_BG_G_Y[] = { + { "MPCC_BG_G_Y", 0, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPCC0_MPCC_BG_B_CB[] = { + { "MPCC_BG_B_CB", 0, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPCC0_MPCC_STALL_STATUS[] = { + { "MPCC_STALL_INT_OCCURED", 0, 0, &umr_bitfield_default }, + { "MPCC_STALL_INT_ACK", 8, 8, &umr_bitfield_default }, + { "MPCC_STALL_INT_MASK", 12, 12, &umr_bitfield_default }, + { "MPCC_STALL_INFO", 16, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPCC0_MPCC_STATUS[] = { + { "MPCC_IDLE", 0, 0, &umr_bitfield_default }, + { "MPCC_BUSY", 1, 1, &umr_bitfield_default }, + { "DPP_MPCC_EOL_MISSED", 16, 16, &umr_bitfield_default }, + { "DPP_MPCC_MULTI_EOL", 17, 17, &umr_bitfield_default }, + { "DPP_MPCC_EOF_MISSED", 18, 18, &umr_bitfield_default }, + { "DPP_MPCC_MULTI_EOF", 19, 19, &umr_bitfield_default }, + { "DPP_MPCC_LESS_PIXEL", 20, 20, &umr_bitfield_default }, + { "DPP_MPCC_MORE_PIXEL", 21, 21, &umr_bitfield_default }, + { "DPP_MPCC_LESS_LINES", 22, 22, &umr_bitfield_default }, + { "DPP_MPCC_MORE_LINES", 23, 23, &umr_bitfield_default }, + { "DPP_MPCC_INPUT_CHECK_ENABLE", 30, 30, &umr_bitfield_default }, + { "DPP_MPCC_EXCEPTION_ACK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPCC1_MPCC_TOP_SEL[] = { + { "MPCC_TOP_SEL", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPCC1_MPCC_BOT_SEL[] = { + { "MPCC_BOT_SEL", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPCC1_MPCC_OPP_ID[] = { + { "MPCC_OPP_ID", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPCC1_MPCC_CONTROL[] = { + { "MPCC_MODE", 0, 1, &umr_bitfield_default }, + { "MPCC_ALPHA_BLND_MODE", 4, 5, &umr_bitfield_default }, + { "MPCC_ALPHA_MULTIPLIED_MODE", 6, 6, &umr_bitfield_default }, + { "MPCC_BLND_ACTIVE_OVERLAP_ONLY", 7, 7, &umr_bitfield_default }, + { "MPCC_GLOBAL_ALPHA", 16, 23, &umr_bitfield_default }, + { "MPCC_GLOBAL_GAIN", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPCC1_MPCC_SM_CONTROL[] = { + { "MPCC_SM_EN", 0, 0, &umr_bitfield_default }, + { "MPCC_SM_MODE", 1, 3, &umr_bitfield_default }, + { "MPCC_SM_FRAME_ALT", 4, 4, &umr_bitfield_default }, + { "MPCC_SM_FIELD_ALT", 5, 5, &umr_bitfield_default }, + { "MPCC_SM_FORCE_NEXT_FRAME_POL", 8, 9, &umr_bitfield_default }, + { "MPCC_SM_FORCE_NEXT_TOP_POL", 16, 17, &umr_bitfield_default }, + { "MPCC_SM_CURRENT_FRAME_POL", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPCC1_MPCC_UPDATE_LOCK_SEL[] = { + { "MPCC_UPDATE_LOCK_SEL", 0, 3, &umr_bitfield_default }, + { "MPCC_UPDATE_LOCKED_STATUS", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPCC1_MPCC_TOP_OFFSET[] = { + { "MPCC_TOP_OFFSET_L", 0, 11, &umr_bitfield_default }, + { "MPCC_TOP_OFFSET_C", 16, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPCC1_MPCC_BOT_OFFSET[] = { + { "MPCC_BOT_OFFSET_L", 0, 11, &umr_bitfield_default }, + { "MPCC_BOT_OFFSET_C", 16, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPCC1_MPCC_OFFSET[] = { + { "MPCC_OFFSET_L", 0, 11, &umr_bitfield_default }, + { "MPCC_OFFSET_C", 16, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPCC1_MPCC_BG_R_CR[] = { + { "MPCC_BG_R_CR", 0, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPCC1_MPCC_BG_G_Y[] = { + { "MPCC_BG_G_Y", 0, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPCC1_MPCC_BG_B_CB[] = { + { "MPCC_BG_B_CB", 0, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPCC1_MPCC_STALL_STATUS[] = { + { "MPCC_STALL_INT_OCCURED", 0, 0, &umr_bitfield_default }, + { "MPCC_STALL_INT_ACK", 8, 8, &umr_bitfield_default }, + { "MPCC_STALL_INT_MASK", 12, 12, &umr_bitfield_default }, + { "MPCC_STALL_INFO", 16, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPCC1_MPCC_STATUS[] = { + { "MPCC_IDLE", 0, 0, &umr_bitfield_default }, + { "MPCC_BUSY", 1, 1, &umr_bitfield_default }, + { "DPP_MPCC_EOL_MISSED", 16, 16, &umr_bitfield_default }, + { "DPP_MPCC_MULTI_EOL", 17, 17, &umr_bitfield_default }, + { "DPP_MPCC_EOF_MISSED", 18, 18, &umr_bitfield_default }, + { "DPP_MPCC_MULTI_EOF", 19, 19, &umr_bitfield_default }, + { "DPP_MPCC_LESS_PIXEL", 20, 20, &umr_bitfield_default }, + { "DPP_MPCC_MORE_PIXEL", 21, 21, &umr_bitfield_default }, + { "DPP_MPCC_LESS_LINES", 22, 22, &umr_bitfield_default }, + { "DPP_MPCC_MORE_LINES", 23, 23, &umr_bitfield_default }, + { "DPP_MPCC_INPUT_CHECK_ENABLE", 30, 30, &umr_bitfield_default }, + { "DPP_MPCC_EXCEPTION_ACK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPCC2_MPCC_TOP_SEL[] = { + { "MPCC_TOP_SEL", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPCC2_MPCC_BOT_SEL[] = { + { "MPCC_BOT_SEL", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPCC2_MPCC_OPP_ID[] = { + { "MPCC_OPP_ID", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPCC2_MPCC_CONTROL[] = { + { "MPCC_MODE", 0, 1, &umr_bitfield_default }, + { "MPCC_ALPHA_BLND_MODE", 4, 5, &umr_bitfield_default }, + { "MPCC_ALPHA_MULTIPLIED_MODE", 6, 6, &umr_bitfield_default }, + { "MPCC_BLND_ACTIVE_OVERLAP_ONLY", 7, 7, &umr_bitfield_default }, + { "MPCC_GLOBAL_ALPHA", 16, 23, &umr_bitfield_default }, + { "MPCC_GLOBAL_GAIN", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPCC2_MPCC_SM_CONTROL[] = { + { "MPCC_SM_EN", 0, 0, &umr_bitfield_default }, + { "MPCC_SM_MODE", 1, 3, &umr_bitfield_default }, + { "MPCC_SM_FRAME_ALT", 4, 4, &umr_bitfield_default }, + { "MPCC_SM_FIELD_ALT", 5, 5, &umr_bitfield_default }, + { "MPCC_SM_FORCE_NEXT_FRAME_POL", 8, 9, &umr_bitfield_default }, + { "MPCC_SM_FORCE_NEXT_TOP_POL", 16, 17, &umr_bitfield_default }, + { "MPCC_SM_CURRENT_FRAME_POL", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPCC2_MPCC_UPDATE_LOCK_SEL[] = { + { "MPCC_UPDATE_LOCK_SEL", 0, 3, &umr_bitfield_default }, + { "MPCC_UPDATE_LOCKED_STATUS", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPCC2_MPCC_TOP_OFFSET[] = { + { "MPCC_TOP_OFFSET_L", 0, 11, &umr_bitfield_default }, + { "MPCC_TOP_OFFSET_C", 16, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPCC2_MPCC_BOT_OFFSET[] = { + { "MPCC_BOT_OFFSET_L", 0, 11, &umr_bitfield_default }, + { "MPCC_BOT_OFFSET_C", 16, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPCC2_MPCC_OFFSET[] = { + { "MPCC_OFFSET_L", 0, 11, &umr_bitfield_default }, + { "MPCC_OFFSET_C", 16, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPCC2_MPCC_BG_R_CR[] = { + { "MPCC_BG_R_CR", 0, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPCC2_MPCC_BG_G_Y[] = { + { "MPCC_BG_G_Y", 0, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPCC2_MPCC_BG_B_CB[] = { + { "MPCC_BG_B_CB", 0, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPCC2_MPCC_STALL_STATUS[] = { + { "MPCC_STALL_INT_OCCURED", 0, 0, &umr_bitfield_default }, + { "MPCC_STALL_INT_ACK", 8, 8, &umr_bitfield_default }, + { "MPCC_STALL_INT_MASK", 12, 12, &umr_bitfield_default }, + { "MPCC_STALL_INFO", 16, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPCC2_MPCC_STATUS[] = { + { "MPCC_IDLE", 0, 0, &umr_bitfield_default }, + { "MPCC_BUSY", 1, 1, &umr_bitfield_default }, + { "DPP_MPCC_EOL_MISSED", 16, 16, &umr_bitfield_default }, + { "DPP_MPCC_MULTI_EOL", 17, 17, &umr_bitfield_default }, + { "DPP_MPCC_EOF_MISSED", 18, 18, &umr_bitfield_default }, + { "DPP_MPCC_MULTI_EOF", 19, 19, &umr_bitfield_default }, + { "DPP_MPCC_LESS_PIXEL", 20, 20, &umr_bitfield_default }, + { "DPP_MPCC_MORE_PIXEL", 21, 21, &umr_bitfield_default }, + { "DPP_MPCC_LESS_LINES", 22, 22, &umr_bitfield_default }, + { "DPP_MPCC_MORE_LINES", 23, 23, &umr_bitfield_default }, + { "DPP_MPCC_INPUT_CHECK_ENABLE", 30, 30, &umr_bitfield_default }, + { "DPP_MPCC_EXCEPTION_ACK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPCC3_MPCC_TOP_SEL[] = { + { "MPCC_TOP_SEL", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPCC3_MPCC_BOT_SEL[] = { + { "MPCC_BOT_SEL", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPCC3_MPCC_OPP_ID[] = { + { "MPCC_OPP_ID", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPCC3_MPCC_CONTROL[] = { + { "MPCC_MODE", 0, 1, &umr_bitfield_default }, + { "MPCC_ALPHA_BLND_MODE", 4, 5, &umr_bitfield_default }, + { "MPCC_ALPHA_MULTIPLIED_MODE", 6, 6, &umr_bitfield_default }, + { "MPCC_BLND_ACTIVE_OVERLAP_ONLY", 7, 7, &umr_bitfield_default }, + { "MPCC_GLOBAL_ALPHA", 16, 23, &umr_bitfield_default }, + { "MPCC_GLOBAL_GAIN", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPCC3_MPCC_SM_CONTROL[] = { + { "MPCC_SM_EN", 0, 0, &umr_bitfield_default }, + { "MPCC_SM_MODE", 1, 3, &umr_bitfield_default }, + { "MPCC_SM_FRAME_ALT", 4, 4, &umr_bitfield_default }, + { "MPCC_SM_FIELD_ALT", 5, 5, &umr_bitfield_default }, + { "MPCC_SM_FORCE_NEXT_FRAME_POL", 8, 9, &umr_bitfield_default }, + { "MPCC_SM_FORCE_NEXT_TOP_POL", 16, 17, &umr_bitfield_default }, + { "MPCC_SM_CURRENT_FRAME_POL", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPCC3_MPCC_UPDATE_LOCK_SEL[] = { + { "MPCC_UPDATE_LOCK_SEL", 0, 3, &umr_bitfield_default }, + { "MPCC_UPDATE_LOCKED_STATUS", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPCC3_MPCC_TOP_OFFSET[] = { + { "MPCC_TOP_OFFSET_L", 0, 11, &umr_bitfield_default }, + { "MPCC_TOP_OFFSET_C", 16, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPCC3_MPCC_BOT_OFFSET[] = { + { "MPCC_BOT_OFFSET_L", 0, 11, &umr_bitfield_default }, + { "MPCC_BOT_OFFSET_C", 16, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPCC3_MPCC_OFFSET[] = { + { "MPCC_OFFSET_L", 0, 11, &umr_bitfield_default }, + { "MPCC_OFFSET_C", 16, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPCC3_MPCC_BG_R_CR[] = { + { "MPCC_BG_R_CR", 0, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPCC3_MPCC_BG_G_Y[] = { + { "MPCC_BG_G_Y", 0, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPCC3_MPCC_BG_B_CB[] = { + { "MPCC_BG_B_CB", 0, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPCC3_MPCC_STALL_STATUS[] = { + { "MPCC_STALL_INT_OCCURED", 0, 0, &umr_bitfield_default }, + { "MPCC_STALL_INT_ACK", 8, 8, &umr_bitfield_default }, + { "MPCC_STALL_INT_MASK", 12, 12, &umr_bitfield_default }, + { "MPCC_STALL_INFO", 16, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPCC3_MPCC_STATUS[] = { + { "MPCC_IDLE", 0, 0, &umr_bitfield_default }, + { "MPCC_BUSY", 1, 1, &umr_bitfield_default }, + { "DPP_MPCC_EOL_MISSED", 16, 16, &umr_bitfield_default }, + { "DPP_MPCC_MULTI_EOL", 17, 17, &umr_bitfield_default }, + { "DPP_MPCC_EOF_MISSED", 18, 18, &umr_bitfield_default }, + { "DPP_MPCC_MULTI_EOF", 19, 19, &umr_bitfield_default }, + { "DPP_MPCC_LESS_PIXEL", 20, 20, &umr_bitfield_default }, + { "DPP_MPCC_MORE_PIXEL", 21, 21, &umr_bitfield_default }, + { "DPP_MPCC_LESS_LINES", 22, 22, &umr_bitfield_default }, + { "DPP_MPCC_MORE_LINES", 23, 23, &umr_bitfield_default }, + { "DPP_MPCC_INPUT_CHECK_ENABLE", 30, 30, &umr_bitfield_default }, + { "DPP_MPCC_EXCEPTION_ACK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPC_CLOCK_CONTROL[] = { + { "DISPCLK_R_GATE_DISABLE", 1, 1, &umr_bitfield_default }, + { "MPC_TEST_CLK_SEL", 4, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPC_SOFT_RESET[] = { + { "MPCC0_SOFT_RESET", 0, 0, &umr_bitfield_default }, + { "MPCC1_SOFT_RESET", 1, 1, &umr_bitfield_default }, + { "MPCC2_SOFT_RESET", 2, 2, &umr_bitfield_default }, + { "MPCC3_SOFT_RESET", 3, 3, &umr_bitfield_default }, + { "MPC_SFR0_SOFT_RESET", 10, 10, &umr_bitfield_default }, + { "MPC_SFR1_SOFT_RESET", 11, 11, &umr_bitfield_default }, + { "MPC_SFR2_SOFT_RESET", 12, 12, &umr_bitfield_default }, + { "MPC_SFR3_SOFT_RESET", 13, 13, &umr_bitfield_default }, + { "MPC_SFT0_SOFT_RESET", 20, 20, &umr_bitfield_default }, + { "MPC_SFT1_SOFT_RESET", 21, 21, &umr_bitfield_default }, + { "MPC_SFT2_SOFT_RESET", 22, 22, &umr_bitfield_default }, + { "MPC_SFT3_SOFT_RESET", 23, 23, &umr_bitfield_default }, + { "MPC_SOFT_RESET", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPC_CRC_CTRL[] = { + { "MPC_CRC_EN", 0, 0, &umr_bitfield_default }, + { "MPC_CRC_CONT_EN", 4, 4, &umr_bitfield_default }, + { "MPC_CRC_STEREO_MODE", 8, 9, &umr_bitfield_default }, + { "MPC_CRC_STEREO_EN", 10, 10, &umr_bitfield_default }, + { "MPC_CRC_INTERLACE_MODE", 12, 13, &umr_bitfield_default }, + { "MPC_CRC_SRC_SEL", 24, 25, &umr_bitfield_default }, + { "MPC_CRC_ONE_SHOT_PENDING", 28, 28, &umr_bitfield_default }, + { "MPC_CRC_UPDATE_LOCK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPC_CRC_SEL_CONTROL[] = { + { "MPC_CRC_DPP_SEL", 0, 3, &umr_bitfield_default }, + { "MPC_CRC_OPP_SEL", 4, 7, &umr_bitfield_default }, + { "MPC_CRC_MASK", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPC_CRC_RESULT_AR[] = { + { "MPC_CRC_RESULT_A", 0, 15, &umr_bitfield_default }, + { "MPC_CRC_RESULT_R", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPC_CRC_RESULT_GB[] = { + { "MPC_CRC_RESULT_G", 0, 15, &umr_bitfield_default }, + { "MPC_CRC_RESULT_B", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPC_CRC_RESULT_C[] = { + { "MPC_CRC_RESULT_C", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPC_PERFMON_EVENT_CTRL[] = { + { "MPC_PERFMON_EVENT_EN", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPC_BYPASS_BG_AR[] = { + { "MPC_BYPASS_BG_ALPHA", 0, 15, &umr_bitfield_default }, + { "MPC_BYPASS_BG_R_CR", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPC_BYPASS_BG_GB[] = { + { "MPC_BYPASS_BG_G_Y", 0, 15, &umr_bitfield_default }, + { "MPC_BYPASS_BG_B_CB", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPC_OUT0_MUX[] = { + { "MPC_OUT_MUX", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPC_OUT1_MUX[] = { + { "MPC_OUT_MUX", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPC_OUT2_MUX[] = { + { "MPC_OUT_MUX", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPC_OUT3_MUX[] = { + { "MPC_OUT_MUX", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMPC_STALL_GRACE_WINDOW[] = { + { "MPC_STALL_GRACE_WINDOW_PERIOD", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmADR_CFG_VUPDATE_LOCK_SET0[] = { + { "ADR_CFG_VUPDATE_LOCK_SET", 0, 0, &umr_bitfield_default }, + { "CFG_VUPDATE_LOCK_SET", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmADR_VUPDATE_LOCK_SET0[] = { + { "ADR_VUPDATE_LOCK_SET", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCUR0_VUPDATE_LOCK_SET0[] = { + { "CUR0_VUPDATE_LOCK_SET", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCUR1_VUPDATE_LOCK_SET0[] = { + { "CUR1_VUPDATE_LOCK_SET", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmADR_CFG_VUPDATE_LOCK_SET1[] = { + { "ADR_CFG_VUPDATE_LOCK_SET", 0, 0, &umr_bitfield_default }, + { "CFG_VUPDATE_LOCK_SET", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmADR_VUPDATE_LOCK_SET1[] = { + { "ADR_VUPDATE_LOCK_SET", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCUR0_VUPDATE_LOCK_SET1[] = { + { "CUR0_VUPDATE_LOCK_SET", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCUR1_VUPDATE_LOCK_SET1[] = { + { "CUR1_VUPDATE_LOCK_SET", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmADR_CFG_VUPDATE_LOCK_SET2[] = { + { "ADR_CFG_VUPDATE_LOCK_SET", 0, 0, &umr_bitfield_default }, + { "CFG_VUPDATE_LOCK_SET", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmADR_VUPDATE_LOCK_SET2[] = { + { "ADR_VUPDATE_LOCK_SET", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCUR0_VUPDATE_LOCK_SET2[] = { + { "CUR0_VUPDATE_LOCK_SET", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCUR1_VUPDATE_LOCK_SET2[] = { + { "CUR1_VUPDATE_LOCK_SET", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmADR_CFG_VUPDATE_LOCK_SET3[] = { + { "ADR_CFG_VUPDATE_LOCK_SET", 0, 0, &umr_bitfield_default }, + { "CFG_VUPDATE_LOCK_SET", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmADR_VUPDATE_LOCK_SET3[] = { + { "ADR_VUPDATE_LOCK_SET", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCUR0_VUPDATE_LOCK_SET3[] = { + { "CUR0_VUPDATE_LOCK_SET", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCUR1_VUPDATE_LOCK_SET3[] = { + { "CUR1_VUPDATE_LOCK_SET", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON16_PERFCOUNTER_CNTL[] = { + { "PERFCOUNTER_EVENT_SEL", 0, 8, &umr_bitfield_default }, + { "PERFCOUNTER_CVALUE_SEL", 9, 11, &umr_bitfield_default }, + { "PERFCOUNTER_INC_MODE", 12, 14, &umr_bitfield_default }, + { "PERFCOUNTER_HW_CNTL_SEL", 15, 15, &umr_bitfield_default }, + { "PERFCOUNTER_RUNEN_MODE", 16, 16, &umr_bitfield_default }, + { "PERFCOUNTER_CNTOFF_START_DIS", 22, 22, &umr_bitfield_default }, + { "PERFCOUNTER_RESTART_EN", 23, 23, &umr_bitfield_default }, + { "PERFCOUNTER_INT_EN", 24, 24, &umr_bitfield_default }, + { "PERFCOUNTER_OFF_MASK", 25, 25, &umr_bitfield_default }, + { "PERFCOUNTER_ACTIVE", 26, 26, &umr_bitfield_default }, + { "PERFCOUNTER_CNTL_SEL", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON16_PERFCOUNTER_CNTL2[] = { + { "PERFCOUNTER_COUNTED_VALUE_TYPE", 0, 1, &umr_bitfield_default }, + { "PERFCOUNTER_HW_STOP1_SEL", 2, 2, &umr_bitfield_default }, + { "PERFCOUNTER_HW_STOP2_SEL", 3, 3, &umr_bitfield_default }, + { "PERFCOUNTER_CNTOFF_SEL", 8, 13, &umr_bitfield_default }, + { "PERFCOUNTER_CNTL2_SEL", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON16_PERFCOUNTER_STATE[] = { + { "PERFCOUNTER_CNT0_STATE", 0, 1, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL0", 2, 2, &umr_bitfield_default }, + { "PERFCOUNTER_CNT1_STATE", 4, 5, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL1", 6, 6, &umr_bitfield_default }, + { "PERFCOUNTER_CNT2_STATE", 8, 9, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL2", 10, 10, &umr_bitfield_default }, + { "PERFCOUNTER_CNT3_STATE", 12, 13, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL3", 14, 14, &umr_bitfield_default }, + { "PERFCOUNTER_CNT4_STATE", 16, 17, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL4", 18, 18, &umr_bitfield_default }, + { "PERFCOUNTER_CNT5_STATE", 20, 21, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL5", 22, 22, &umr_bitfield_default }, + { "PERFCOUNTER_CNT6_STATE", 24, 25, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL6", 26, 26, &umr_bitfield_default }, + { "PERFCOUNTER_CNT7_STATE", 28, 29, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL7", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON16_PERFMON_CNTL[] = { + { "PERFMON_STATE", 0, 1, &umr_bitfield_default }, + { "PERFMON_RPT_COUNT", 8, 27, &umr_bitfield_default }, + { "PERFMON_CNTOFF_AND_OR", 28, 28, &umr_bitfield_default }, + { "PERFMON_CNTOFF_INT_EN", 29, 29, &umr_bitfield_default }, + { "PERFMON_CNTOFF_INT_STATUS", 30, 30, &umr_bitfield_default }, + { "PERFMON_CNTOFF_INT_ACK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON16_PERFMON_CNTL2[] = { + { "PERFMON_CNTOFF_INT_TYPE", 0, 0, &umr_bitfield_default }, + { "PERFMON_CLK_ENABLE", 1, 1, &umr_bitfield_default }, + { "PERFMON_RUN_ENABLE_START_SEL", 2, 9, &umr_bitfield_default }, + { "PERFMON_RUN_ENABLE_STOP_SEL", 10, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON16_PERFMON_CVALUE_INT_MISC[] = { + { "PERFCOUNTER_INT0_STATUS", 0, 0, &umr_bitfield_default }, + { "PERFCOUNTER_INT1_STATUS", 1, 1, &umr_bitfield_default }, + { "PERFCOUNTER_INT2_STATUS", 2, 2, &umr_bitfield_default }, + { "PERFCOUNTER_INT3_STATUS", 3, 3, &umr_bitfield_default }, + { "PERFCOUNTER_INT4_STATUS", 4, 4, &umr_bitfield_default }, + { "PERFCOUNTER_INT5_STATUS", 5, 5, &umr_bitfield_default }, + { "PERFCOUNTER_INT6_STATUS", 6, 6, &umr_bitfield_default }, + { "PERFCOUNTER_INT7_STATUS", 7, 7, &umr_bitfield_default }, + { "PERFCOUNTER_INT0_ACK", 8, 8, &umr_bitfield_default }, + { "PERFCOUNTER_INT1_ACK", 9, 9, &umr_bitfield_default }, + { "PERFCOUNTER_INT2_ACK", 10, 10, &umr_bitfield_default }, + { "PERFCOUNTER_INT3_ACK", 11, 11, &umr_bitfield_default }, + { "PERFCOUNTER_INT4_ACK", 12, 12, &umr_bitfield_default }, + { "PERFCOUNTER_INT5_ACK", 13, 13, &umr_bitfield_default }, + { "PERFCOUNTER_INT6_ACK", 14, 14, &umr_bitfield_default }, + { "PERFCOUNTER_INT7_ACK", 15, 15, &umr_bitfield_default }, + { "PERFMON_CVALUE_HI", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON16_PERFMON_CVALUE_LOW[] = { + { "PERFMON_CVALUE_LOW", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON16_PERFMON_HI[] = { + { "PERFMON_HI", 0, 15, &umr_bitfield_default }, + { "PERFMON_READ_SEL", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON16_PERFMON_LOW[] = { + { "PERFMON_LOW", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL[] = { + { "BL1_PWM_AMBIENT_LIGHT_LEVEL", 0, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM0_BL1_PWM_USER_LEVEL[] = { + { "BL1_PWM_USER_LEVEL", 0, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM0_BL1_PWM_TARGET_ABM_LEVEL[] = { + { "BL1_PWM_TARGET_ABM_LEVEL", 0, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM0_BL1_PWM_CURRENT_ABM_LEVEL[] = { + { "BL1_PWM_CURRENT_ABM_LEVEL", 0, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM0_BL1_PWM_FINAL_DUTY_CYCLE[] = { + { "BL1_PWM_FINAL_DUTY_CYCLE", 0, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM0_BL1_PWM_MINIMUM_DUTY_CYCLE[] = { + { "BL1_PWM_MINIMUM_DUTY_CYCLE", 0, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM0_BL1_PWM_ABM_CNTL[] = { + { "BL1_PWM_USE_ABM_EN", 0, 0, &umr_bitfield_default }, + { "BL1_PWM_USE_AMBIENT_LEVEL_EN", 1, 1, &umr_bitfield_default }, + { "BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN", 2, 2, &umr_bitfield_default }, + { "BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN", 3, 3, &umr_bitfield_default }, + { "BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE[] = { + { "BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN", 0, 0, &umr_bitfield_default }, + { "BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER", 1, 1, &umr_bitfield_default }, + { "BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT", 8, 15, &umr_bitfield_default }, + { "BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET", 16, 23, &umr_bitfield_default }, + { "ABM1_HGLS_REG_LOCK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM0_BL1_PWM_GRP2_REG_LOCK[] = { + { "BL1_PWM_GRP2_REG_LOCK", 0, 0, &umr_bitfield_default }, + { "BL1_PWM_GRP2_REG_UPDATE_PENDING", 8, 8, &umr_bitfield_default }, + { "BL1_PWM_GRP2_UPDATE_AT_FRAME_START", 16, 16, &umr_bitfield_default }, + { "BL1_PWM_GRP2_FRAME_START_DISP_SEL", 17, 19, &umr_bitfield_default }, + { "BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN", 24, 24, &umr_bitfield_default }, + { "BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM0_DC_ABM1_CNTL[] = { + { "ABM1_EN", 0, 0, &umr_bitfield_default }, + { "ABM1_SOURCE_SELECT", 8, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM0_DC_ABM1_IPCSC_COEFF_SEL[] = { + { "ABM1_IPCSC_COEFF_SEL_B", 0, 3, &umr_bitfield_default }, + { "ABM1_IPCSC_COEFF_SEL_G", 8, 11, &umr_bitfield_default }, + { "ABM1_IPCSC_COEFF_SEL_R", 16, 19, &umr_bitfield_default }, + { "ABM1_HGLS_REG_LOCK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_0[] = { + { "ABM1_ACE_SLOPE_0", 0, 14, &umr_bitfield_default }, + { "ABM1_ACE_OFFSET_0", 16, 26, &umr_bitfield_default }, + { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_1[] = { + { "ABM1_ACE_SLOPE_1", 0, 14, &umr_bitfield_default }, + { "ABM1_ACE_OFFSET_1", 16, 26, &umr_bitfield_default }, + { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_2[] = { + { "ABM1_ACE_SLOPE_2", 0, 14, &umr_bitfield_default }, + { "ABM1_ACE_OFFSET_2", 16, 26, &umr_bitfield_default }, + { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_3[] = { + { "ABM1_ACE_SLOPE_3", 0, 14, &umr_bitfield_default }, + { "ABM1_ACE_OFFSET_3", 16, 26, &umr_bitfield_default }, + { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_4[] = { + { "ABM1_ACE_SLOPE_4", 0, 14, &umr_bitfield_default }, + { "ABM1_ACE_OFFSET_4", 16, 26, &umr_bitfield_default }, + { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM0_DC_ABM1_ACE_THRES_12[] = { + { "ABM1_ACE_THRES_1", 0, 9, &umr_bitfield_default }, + { "ABM1_ACE_THRES_2", 16, 25, &umr_bitfield_default }, + { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM0_DC_ABM1_ACE_THRES_34[] = { + { "ABM1_ACE_THRES_3", 0, 9, &umr_bitfield_default }, + { "ABM1_ACE_THRES_4", 16, 25, &umr_bitfield_default }, + { "ABM1_ACE_IGNORE_MASTER_LOCK_EN", 28, 28, &umr_bitfield_default }, + { "ABM1_ACE_READBACK_DB_REG_VALUE_EN", 29, 29, &umr_bitfield_default }, + { "ABM1_ACE_DBUF_REG_UPDATE_PENDING", 30, 30, &umr_bitfield_default }, + { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM0_DC_ABM1_ACE_CNTL_MISC[] = { + { "ABM1_ACE_REG_WR_MISSED_FRAME", 0, 0, &umr_bitfield_default }, + { "ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM0_DC_ABM1_HGLS_REG_READ_PROGRESS[] = { + { "ABM1_HG_REG_READ_IN_PROGRESS", 0, 0, &umr_bitfield_default }, + { "ABM1_LS_REG_READ_IN_PROGRESS", 1, 1, &umr_bitfield_default }, + { "ABM1_BL_REG_READ_IN_PROGRESS", 2, 2, &umr_bitfield_default }, + { "ABM1_HG_REG_READ_MISSED_FRAME", 8, 8, &umr_bitfield_default }, + { "ABM1_LS_REG_READ_MISSED_FRAME", 9, 9, &umr_bitfield_default }, + { "ABM1_BL_REG_READ_MISSED_FRAME", 10, 10, &umr_bitfield_default }, + { "ABM1_HG_REG_READ_MISSED_FRAME_CLEAR", 16, 16, &umr_bitfield_default }, + { "ABM1_LS_REG_READ_MISSED_FRAME_CLEAR", 24, 24, &umr_bitfield_default }, + { "ABM1_BL_REG_READ_MISSED_FRAME_CLEAR", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM0_DC_ABM1_HG_MISC_CTRL[] = { + { "ABM1_HG_NUM_OF_BINS_SEL", 0, 1, &umr_bitfield_default }, + { "ABM1_HG_VMAX_SEL", 8, 8, &umr_bitfield_default }, + { "ABM1_HG_FINE_MODE_BIN_SEL", 12, 12, &umr_bitfield_default }, + { "ABM1_HG_BIN_BITWIDTH_SIZE_SEL", 16, 17, &umr_bitfield_default }, + { "ABM1_OVR_SCAN_PIXEL_PROCESS_EN", 20, 20, &umr_bitfield_default }, + { "ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN", 23, 23, &umr_bitfield_default }, + { "ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL", 24, 26, &umr_bitfield_default }, + { "ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START", 28, 28, &umr_bitfield_default }, + { "ABM1_HGLS_IGNORE_MASTER_LOCK_EN", 29, 29, &umr_bitfield_default }, + { "ABM1_DBUF_HGLS_REG_UPDATE_PENDING", 30, 30, &umr_bitfield_default }, + { "ABM1_HGLS_REG_LOCK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM0_DC_ABM1_LS_SUM_OF_LUMA[] = { + { "ABM1_LS_SUM_OF_LUMA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM0_DC_ABM1_LS_MIN_MAX_LUMA[] = { + { "ABM1_LS_MIN_LUMA", 0, 9, &umr_bitfield_default }, + { "ABM1_LS_MAX_LUMA", 16, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA[] = { + { "ABM1_LS_FILTERED_MIN_LUMA", 0, 9, &umr_bitfield_default }, + { "ABM1_LS_FILTERED_MAX_LUMA", 16, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM0_DC_ABM1_LS_PIXEL_COUNT[] = { + { "ABM1_LS_PIXEL_COUNT", 0, 23, &umr_bitfield_default }, + { "ABM1_LS_SUM_OF_LUMA_MSB", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES[] = { + { "ABM1_LS_MIN_PIXEL_VALUE_THRES", 0, 9, &umr_bitfield_default }, + { "ABM1_LS_MAX_PIXEL_VALUE_THRES", 16, 25, &umr_bitfield_default }, + { "ABM1_HGLS_REG_LOCK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT[] = { + { "ABM1_LS_MIN_PIXEL_VALUE_COUNT", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT[] = { + { "ABM1_LS_MAX_PIXEL_VALUE_COUNT", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM0_DC_ABM1_HG_SAMPLE_RATE[] = { + { "ABM1_HG_SAMPLE_RATE_COUNT_EN", 0, 0, &umr_bitfield_default }, + { "ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER", 1, 1, &umr_bitfield_default }, + { "ABM1_HG_SAMPLE_RATE_FRAME_COUNT", 8, 15, &umr_bitfield_default }, + { "ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET", 16, 23, &umr_bitfield_default }, + { "ABM1_HGLS_REG_LOCK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM0_DC_ABM1_LS_SAMPLE_RATE[] = { + { "ABM1_LS_SAMPLE_RATE_COUNT_EN", 0, 0, &umr_bitfield_default }, + { "ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER", 1, 1, &umr_bitfield_default }, + { "ABM1_LS_SAMPLE_RATE_FRAME_COUNT", 8, 15, &umr_bitfield_default }, + { "ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET", 16, 23, &umr_bitfield_default }, + { "ABM1_HGLS_REG_LOCK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG[] = { + { "ABM1_HG_BIN_1_32_SHIFT_FLAG", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX[] = { + { "ABM1_HG_BIN_1_8_SHIFT_INDEX", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX[] = { + { "ABM1_HG_BIN_9_16_SHIFT_INDEX", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX[] = { + { "ABM1_HG_BIN_17_24_SHIFT_INDEX", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX[] = { + { "ABM1_HG_BIN_25_32_SHIFT_INDEX", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM0_DC_ABM1_HG_RESULT_1[] = { + { "ABM1_HG_RESULT_1", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM0_DC_ABM1_HG_RESULT_2[] = { + { "ABM1_HG_RESULT_2", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM0_DC_ABM1_HG_RESULT_3[] = { + { "ABM1_HG_RESULT_3", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM0_DC_ABM1_HG_RESULT_4[] = { + { "ABM1_HG_RESULT_4", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM0_DC_ABM1_HG_RESULT_5[] = { + { "ABM1_HG_RESULT_5", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM0_DC_ABM1_HG_RESULT_6[] = { + { "ABM1_HG_RESULT_6", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM0_DC_ABM1_HG_RESULT_7[] = { + { "ABM1_HG_RESULT_7", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM0_DC_ABM1_HG_RESULT_8[] = { + { "ABM1_HG_RESULT_8", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM0_DC_ABM1_HG_RESULT_9[] = { + { "ABM1_HG_RESULT_9", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM0_DC_ABM1_HG_RESULT_10[] = { + { "ABM1_HG_RESULT_10", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM0_DC_ABM1_HG_RESULT_11[] = { + { "ABM1_HG_RESULT_11", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM0_DC_ABM1_HG_RESULT_12[] = { + { "ABM1_HG_RESULT_12", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM0_DC_ABM1_HG_RESULT_13[] = { + { "ABM1_HG_RESULT_13", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM0_DC_ABM1_HG_RESULT_14[] = { + { "ABM1_HG_RESULT_14", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM0_DC_ABM1_HG_RESULT_15[] = { + { "ABM1_HG_RESULT_15", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM0_DC_ABM1_HG_RESULT_16[] = { + { "ABM1_HG_RESULT_16", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM0_DC_ABM1_HG_RESULT_17[] = { + { "ABM1_HG_RESULT_17", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM0_DC_ABM1_HG_RESULT_18[] = { + { "ABM1_HG_RESULT_18", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM0_DC_ABM1_HG_RESULT_19[] = { + { "ABM1_HG_RESULT_19", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM0_DC_ABM1_HG_RESULT_20[] = { + { "ABM1_HG_RESULT_20", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM0_DC_ABM1_HG_RESULT_21[] = { + { "ABM1_HG_RESULT_21", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM0_DC_ABM1_HG_RESULT_22[] = { + { "ABM1_HG_RESULT_22", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM0_DC_ABM1_HG_RESULT_23[] = { + { "ABM1_HG_RESULT_23", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM0_DC_ABM1_HG_RESULT_24[] = { + { "ABM1_HG_RESULT_24", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM0_DC_ABM1_BL_MASTER_LOCK[] = { + { "ABM1_BL_MASTER_LOCK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL[] = { + { "BL1_PWM_AMBIENT_LIGHT_LEVEL", 0, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM1_BL1_PWM_USER_LEVEL[] = { + { "BL1_PWM_USER_LEVEL", 0, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM1_BL1_PWM_TARGET_ABM_LEVEL[] = { + { "BL1_PWM_TARGET_ABM_LEVEL", 0, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM1_BL1_PWM_CURRENT_ABM_LEVEL[] = { + { "BL1_PWM_CURRENT_ABM_LEVEL", 0, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM1_BL1_PWM_FINAL_DUTY_CYCLE[] = { + { "BL1_PWM_FINAL_DUTY_CYCLE", 0, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM1_BL1_PWM_MINIMUM_DUTY_CYCLE[] = { + { "BL1_PWM_MINIMUM_DUTY_CYCLE", 0, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM1_BL1_PWM_ABM_CNTL[] = { + { "BL1_PWM_USE_ABM_EN", 0, 0, &umr_bitfield_default }, + { "BL1_PWM_USE_AMBIENT_LEVEL_EN", 1, 1, &umr_bitfield_default }, + { "BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN", 2, 2, &umr_bitfield_default }, + { "BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN", 3, 3, &umr_bitfield_default }, + { "BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE[] = { + { "BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN", 0, 0, &umr_bitfield_default }, + { "BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER", 1, 1, &umr_bitfield_default }, + { "BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT", 8, 15, &umr_bitfield_default }, + { "BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET", 16, 23, &umr_bitfield_default }, + { "ABM1_HGLS_REG_LOCK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM1_BL1_PWM_GRP2_REG_LOCK[] = { + { "BL1_PWM_GRP2_REG_LOCK", 0, 0, &umr_bitfield_default }, + { "BL1_PWM_GRP2_REG_UPDATE_PENDING", 8, 8, &umr_bitfield_default }, + { "BL1_PWM_GRP2_UPDATE_AT_FRAME_START", 16, 16, &umr_bitfield_default }, + { "BL1_PWM_GRP2_FRAME_START_DISP_SEL", 17, 19, &umr_bitfield_default }, + { "BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN", 24, 24, &umr_bitfield_default }, + { "BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM1_DC_ABM1_CNTL[] = { + { "ABM1_EN", 0, 0, &umr_bitfield_default }, + { "ABM1_SOURCE_SELECT", 8, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM1_DC_ABM1_IPCSC_COEFF_SEL[] = { + { "ABM1_IPCSC_COEFF_SEL_B", 0, 3, &umr_bitfield_default }, + { "ABM1_IPCSC_COEFF_SEL_G", 8, 11, &umr_bitfield_default }, + { "ABM1_IPCSC_COEFF_SEL_R", 16, 19, &umr_bitfield_default }, + { "ABM1_HGLS_REG_LOCK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_0[] = { + { "ABM1_ACE_SLOPE_0", 0, 14, &umr_bitfield_default }, + { "ABM1_ACE_OFFSET_0", 16, 26, &umr_bitfield_default }, + { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_1[] = { + { "ABM1_ACE_SLOPE_1", 0, 14, &umr_bitfield_default }, + { "ABM1_ACE_OFFSET_1", 16, 26, &umr_bitfield_default }, + { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_2[] = { + { "ABM1_ACE_SLOPE_2", 0, 14, &umr_bitfield_default }, + { "ABM1_ACE_OFFSET_2", 16, 26, &umr_bitfield_default }, + { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_3[] = { + { "ABM1_ACE_SLOPE_3", 0, 14, &umr_bitfield_default }, + { "ABM1_ACE_OFFSET_3", 16, 26, &umr_bitfield_default }, + { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_4[] = { + { "ABM1_ACE_SLOPE_4", 0, 14, &umr_bitfield_default }, + { "ABM1_ACE_OFFSET_4", 16, 26, &umr_bitfield_default }, + { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM1_DC_ABM1_ACE_THRES_12[] = { + { "ABM1_ACE_THRES_1", 0, 9, &umr_bitfield_default }, + { "ABM1_ACE_THRES_2", 16, 25, &umr_bitfield_default }, + { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM1_DC_ABM1_ACE_THRES_34[] = { + { "ABM1_ACE_THRES_3", 0, 9, &umr_bitfield_default }, + { "ABM1_ACE_THRES_4", 16, 25, &umr_bitfield_default }, + { "ABM1_ACE_IGNORE_MASTER_LOCK_EN", 28, 28, &umr_bitfield_default }, + { "ABM1_ACE_READBACK_DB_REG_VALUE_EN", 29, 29, &umr_bitfield_default }, + { "ABM1_ACE_DBUF_REG_UPDATE_PENDING", 30, 30, &umr_bitfield_default }, + { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM1_DC_ABM1_ACE_CNTL_MISC[] = { + { "ABM1_ACE_REG_WR_MISSED_FRAME", 0, 0, &umr_bitfield_default }, + { "ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM1_DC_ABM1_HGLS_REG_READ_PROGRESS[] = { + { "ABM1_HG_REG_READ_IN_PROGRESS", 0, 0, &umr_bitfield_default }, + { "ABM1_LS_REG_READ_IN_PROGRESS", 1, 1, &umr_bitfield_default }, + { "ABM1_BL_REG_READ_IN_PROGRESS", 2, 2, &umr_bitfield_default }, + { "ABM1_HG_REG_READ_MISSED_FRAME", 8, 8, &umr_bitfield_default }, + { "ABM1_LS_REG_READ_MISSED_FRAME", 9, 9, &umr_bitfield_default }, + { "ABM1_BL_REG_READ_MISSED_FRAME", 10, 10, &umr_bitfield_default }, + { "ABM1_HG_REG_READ_MISSED_FRAME_CLEAR", 16, 16, &umr_bitfield_default }, + { "ABM1_LS_REG_READ_MISSED_FRAME_CLEAR", 24, 24, &umr_bitfield_default }, + { "ABM1_BL_REG_READ_MISSED_FRAME_CLEAR", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM1_DC_ABM1_HG_MISC_CTRL[] = { + { "ABM1_HG_NUM_OF_BINS_SEL", 0, 1, &umr_bitfield_default }, + { "ABM1_HG_VMAX_SEL", 8, 8, &umr_bitfield_default }, + { "ABM1_HG_FINE_MODE_BIN_SEL", 12, 12, &umr_bitfield_default }, + { "ABM1_HG_BIN_BITWIDTH_SIZE_SEL", 16, 17, &umr_bitfield_default }, + { "ABM1_OVR_SCAN_PIXEL_PROCESS_EN", 20, 20, &umr_bitfield_default }, + { "ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN", 23, 23, &umr_bitfield_default }, + { "ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL", 24, 26, &umr_bitfield_default }, + { "ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START", 28, 28, &umr_bitfield_default }, + { "ABM1_HGLS_IGNORE_MASTER_LOCK_EN", 29, 29, &umr_bitfield_default }, + { "ABM1_DBUF_HGLS_REG_UPDATE_PENDING", 30, 30, &umr_bitfield_default }, + { "ABM1_HGLS_REG_LOCK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM1_DC_ABM1_LS_SUM_OF_LUMA[] = { + { "ABM1_LS_SUM_OF_LUMA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM1_DC_ABM1_LS_MIN_MAX_LUMA[] = { + { "ABM1_LS_MIN_LUMA", 0, 9, &umr_bitfield_default }, + { "ABM1_LS_MAX_LUMA", 16, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA[] = { + { "ABM1_LS_FILTERED_MIN_LUMA", 0, 9, &umr_bitfield_default }, + { "ABM1_LS_FILTERED_MAX_LUMA", 16, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM1_DC_ABM1_LS_PIXEL_COUNT[] = { + { "ABM1_LS_PIXEL_COUNT", 0, 23, &umr_bitfield_default }, + { "ABM1_LS_SUM_OF_LUMA_MSB", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES[] = { + { "ABM1_LS_MIN_PIXEL_VALUE_THRES", 0, 9, &umr_bitfield_default }, + { "ABM1_LS_MAX_PIXEL_VALUE_THRES", 16, 25, &umr_bitfield_default }, + { "ABM1_HGLS_REG_LOCK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT[] = { + { "ABM1_LS_MIN_PIXEL_VALUE_COUNT", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT[] = { + { "ABM1_LS_MAX_PIXEL_VALUE_COUNT", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM1_DC_ABM1_HG_SAMPLE_RATE[] = { + { "ABM1_HG_SAMPLE_RATE_COUNT_EN", 0, 0, &umr_bitfield_default }, + { "ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER", 1, 1, &umr_bitfield_default }, + { "ABM1_HG_SAMPLE_RATE_FRAME_COUNT", 8, 15, &umr_bitfield_default }, + { "ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET", 16, 23, &umr_bitfield_default }, + { "ABM1_HGLS_REG_LOCK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM1_DC_ABM1_LS_SAMPLE_RATE[] = { + { "ABM1_LS_SAMPLE_RATE_COUNT_EN", 0, 0, &umr_bitfield_default }, + { "ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER", 1, 1, &umr_bitfield_default }, + { "ABM1_LS_SAMPLE_RATE_FRAME_COUNT", 8, 15, &umr_bitfield_default }, + { "ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET", 16, 23, &umr_bitfield_default }, + { "ABM1_HGLS_REG_LOCK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG[] = { + { "ABM1_HG_BIN_1_32_SHIFT_FLAG", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX[] = { + { "ABM1_HG_BIN_1_8_SHIFT_INDEX", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX[] = { + { "ABM1_HG_BIN_9_16_SHIFT_INDEX", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX[] = { + { "ABM1_HG_BIN_17_24_SHIFT_INDEX", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX[] = { + { "ABM1_HG_BIN_25_32_SHIFT_INDEX", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM1_DC_ABM1_HG_RESULT_1[] = { + { "ABM1_HG_RESULT_1", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM1_DC_ABM1_HG_RESULT_2[] = { + { "ABM1_HG_RESULT_2", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM1_DC_ABM1_HG_RESULT_3[] = { + { "ABM1_HG_RESULT_3", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM1_DC_ABM1_HG_RESULT_4[] = { + { "ABM1_HG_RESULT_4", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM1_DC_ABM1_HG_RESULT_5[] = { + { "ABM1_HG_RESULT_5", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM1_DC_ABM1_HG_RESULT_6[] = { + { "ABM1_HG_RESULT_6", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM1_DC_ABM1_HG_RESULT_7[] = { + { "ABM1_HG_RESULT_7", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM1_DC_ABM1_HG_RESULT_8[] = { + { "ABM1_HG_RESULT_8", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM1_DC_ABM1_HG_RESULT_9[] = { + { "ABM1_HG_RESULT_9", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM1_DC_ABM1_HG_RESULT_10[] = { + { "ABM1_HG_RESULT_10", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM1_DC_ABM1_HG_RESULT_11[] = { + { "ABM1_HG_RESULT_11", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM1_DC_ABM1_HG_RESULT_12[] = { + { "ABM1_HG_RESULT_12", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM1_DC_ABM1_HG_RESULT_13[] = { + { "ABM1_HG_RESULT_13", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM1_DC_ABM1_HG_RESULT_14[] = { + { "ABM1_HG_RESULT_14", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM1_DC_ABM1_HG_RESULT_15[] = { + { "ABM1_HG_RESULT_15", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM1_DC_ABM1_HG_RESULT_16[] = { + { "ABM1_HG_RESULT_16", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM1_DC_ABM1_HG_RESULT_17[] = { + { "ABM1_HG_RESULT_17", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM1_DC_ABM1_HG_RESULT_18[] = { + { "ABM1_HG_RESULT_18", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM1_DC_ABM1_HG_RESULT_19[] = { + { "ABM1_HG_RESULT_19", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM1_DC_ABM1_HG_RESULT_20[] = { + { "ABM1_HG_RESULT_20", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM1_DC_ABM1_HG_RESULT_21[] = { + { "ABM1_HG_RESULT_21", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM1_DC_ABM1_HG_RESULT_22[] = { + { "ABM1_HG_RESULT_22", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM1_DC_ABM1_HG_RESULT_23[] = { + { "ABM1_HG_RESULT_23", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM1_DC_ABM1_HG_RESULT_24[] = { + { "ABM1_HG_RESULT_24", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmABM1_DC_ABM1_BL_MASTER_LOCK[] = { + { "ABM1_BL_MASTER_LOCK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT0_FMT_CLAMP_COMPONENT_R[] = { + { "FMT_CLAMP_LOWER_R", 0, 15, &umr_bitfield_default }, + { "FMT_CLAMP_UPPER_R", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT0_FMT_CLAMP_COMPONENT_G[] = { + { "FMT_CLAMP_LOWER_G", 0, 15, &umr_bitfield_default }, + { "FMT_CLAMP_UPPER_G", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT0_FMT_CLAMP_COMPONENT_B[] = { + { "FMT_CLAMP_LOWER_B", 0, 15, &umr_bitfield_default }, + { "FMT_CLAMP_UPPER_B", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT0_FMT_DYNAMIC_EXP_CNTL[] = { + { "FMT_DYNAMIC_EXP_EN", 0, 0, &umr_bitfield_default }, + { "FMT_DYNAMIC_EXP_MODE", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT0_FMT_CONTROL[] = { + { "FMT_STEREOSYNC_OVERRIDE", 0, 0, &umr_bitfield_default }, + { "FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX", 8, 11, &umr_bitfield_default }, + { "FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP", 12, 13, &umr_bitfield_default }, + { "FMT_PIXEL_ENCODING", 16, 17, &umr_bitfield_default }, + { "FMT_SUBSAMPLING_MODE", 18, 19, &umr_bitfield_default }, + { "FMT_SUBSAMPLING_ORDER", 20, 20, &umr_bitfield_default }, + { "FMT_CBCR_BIT_REDUCTION_BYPASS", 21, 21, &umr_bitfield_default }, + { "FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT0_FMT_BIT_DEPTH_CONTROL[] = { + { "FMT_TRUNCATE_EN", 0, 0, &umr_bitfield_default }, + { "FMT_TRUNCATE_MODE", 1, 1, &umr_bitfield_default }, + { "FMT_TRUNCATE_DEPTH", 4, 5, &umr_bitfield_default }, + { "FMT_SPATIAL_DITHER_EN", 8, 8, &umr_bitfield_default }, + { "FMT_SPATIAL_DITHER_MODE", 9, 10, &umr_bitfield_default }, + { "FMT_SPATIAL_DITHER_DEPTH", 11, 12, &umr_bitfield_default }, + { "FMT_FRAME_RANDOM_ENABLE", 13, 13, &umr_bitfield_default }, + { "FMT_RGB_RANDOM_ENABLE", 14, 14, &umr_bitfield_default }, + { "FMT_HIGHPASS_RANDOM_ENABLE", 15, 15, &umr_bitfield_default }, + { "FMT_TEMPORAL_DITHER_EN", 16, 16, &umr_bitfield_default }, + { "FMT_TEMPORAL_DITHER_DEPTH", 17, 18, &umr_bitfield_default }, + { "FMT_TEMPORAL_DITHER_OFFSET", 21, 22, &umr_bitfield_default }, + { "FMT_TEMPORAL_LEVEL", 24, 24, &umr_bitfield_default }, + { "FMT_TEMPORAL_DITHER_RESET", 25, 25, &umr_bitfield_default }, + { "FMT_25FRC_SEL", 26, 27, &umr_bitfield_default }, + { "FMT_50FRC_SEL", 28, 29, &umr_bitfield_default }, + { "FMT_75FRC_SEL", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT0_FMT_DITHER_RAND_R_SEED[] = { + { "FMT_RAND_R_SEED", 0, 7, &umr_bitfield_default }, + { "FMT_OFFSET_R_CR", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT0_FMT_DITHER_RAND_G_SEED[] = { + { "FMT_RAND_G_SEED", 0, 7, &umr_bitfield_default }, + { "FMT_OFFSET_G_Y", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT0_FMT_DITHER_RAND_B_SEED[] = { + { "FMT_RAND_B_SEED", 0, 7, &umr_bitfield_default }, + { "FMT_OFFSET_B_CB", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT0_FMT_CLAMP_CNTL[] = { + { "FMT_CLAMP_DATA_EN", 0, 0, &umr_bitfield_default }, + { "FMT_CLAMP_COLOR_FORMAT", 16, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL[] = { + { "FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH", 0, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT0_FMT_MAP420_MEMORY_CONTROL[] = { + { "FMT_MAP420MEM_PWR_FORCE", 0, 1, &umr_bitfield_default }, + { "FMT_MAP420MEM_PWR_DIS", 4, 4, &umr_bitfield_default }, + { "FMT_MAP420MEM_PWR_STATE", 8, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOPPBUF0_OPPBUF_CONTROL[] = { + { "OPPBUF_ACTIVE_WIDTH", 0, 13, &umr_bitfield_default }, + { "OPPBUF_DISPLAY_SEGMENTATION", 16, 18, &umr_bitfield_default }, + { "OPPBUF_OVERLAP_PIXEL_NUM", 20, 23, &umr_bitfield_default }, + { "OPPBUF_PIXEL_REPETITION", 24, 27, &umr_bitfield_default }, + { "OPPBUF_DOUBLE_BUFFER_PENDING", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOPPBUF0_OPPBUF_3D_PARAMETERS_0[] = { + { "OPPBUF_3D_VACT_SPACE1_SIZE", 0, 9, &umr_bitfield_default }, + { "OPPBUF_3D_VACT_SPACE2_SIZE", 10, 19, &umr_bitfield_default }, + { "OPPBUF_DUMMY_DATA_R", 20, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOPPBUF0_OPPBUF_3D_PARAMETERS_1[] = { + { "OPPBUF_DUMMY_DATA_G", 0, 11, &umr_bitfield_default }, + { "OPPBUF_DUMMY_DATA_B", 16, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOPP_PIPE0_OPP_PIPE_CONTROL[] = { + { "OPP_PIPE_CLOCK_EN", 0, 0, &umr_bitfield_default }, + { "OPP_PIPE_CLOCK_ON", 1, 1, &umr_bitfield_default }, + { "OPP_PIPE_DIGITAL_BYPASS_EN", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL[] = { + { "OPP_PIPE_CRC_EN", 0, 0, &umr_bitfield_default }, + { "OPP_PIPE_CRC_CONT_EN", 4, 4, &umr_bitfield_default }, + { "OPP_PIPE_CRC_STEREO_MODE", 8, 9, &umr_bitfield_default }, + { "OPP_PIPE_CRC_STEREO_EN", 10, 10, &umr_bitfield_default }, + { "OPP_PIPE_CRC_INTERLACE_MODE", 12, 13, &umr_bitfield_default }, + { "OPP_PIPE_CRC_INTERLACE_EN", 14, 14, &umr_bitfield_default }, + { "OPP_PIPE_CRC_PIXEL_SELECT", 20, 21, &umr_bitfield_default }, + { "OPP_PIPE_CRC_SOURCE_SELECT", 24, 24, &umr_bitfield_default }, + { "OPP_PIPE_CRC_ONE_SHOT_PENDING", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK[] = { + { "OPP_PIPE_CRC_MASK", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0[] = { + { "OPP_PIPE_CRC_RESULT_A", 0, 15, &umr_bitfield_default }, + { "OPP_PIPE_CRC_RESULT_R", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1[] = { + { "OPP_PIPE_CRC_RESULT_G", 0, 15, &umr_bitfield_default }, + { "OPP_PIPE_CRC_RESULT_B", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2[] = { + { "OPP_PIPE_CRC_RESULT_C", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT1_FMT_CLAMP_COMPONENT_R[] = { + { "FMT_CLAMP_LOWER_R", 0, 15, &umr_bitfield_default }, + { "FMT_CLAMP_UPPER_R", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT1_FMT_CLAMP_COMPONENT_G[] = { + { "FMT_CLAMP_LOWER_G", 0, 15, &umr_bitfield_default }, + { "FMT_CLAMP_UPPER_G", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT1_FMT_CLAMP_COMPONENT_B[] = { + { "FMT_CLAMP_LOWER_B", 0, 15, &umr_bitfield_default }, + { "FMT_CLAMP_UPPER_B", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT1_FMT_DYNAMIC_EXP_CNTL[] = { + { "FMT_DYNAMIC_EXP_EN", 0, 0, &umr_bitfield_default }, + { "FMT_DYNAMIC_EXP_MODE", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT1_FMT_CONTROL[] = { + { "FMT_STEREOSYNC_OVERRIDE", 0, 0, &umr_bitfield_default }, + { "FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX", 8, 11, &umr_bitfield_default }, + { "FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP", 12, 13, &umr_bitfield_default }, + { "FMT_PIXEL_ENCODING", 16, 17, &umr_bitfield_default }, + { "FMT_SUBSAMPLING_MODE", 18, 19, &umr_bitfield_default }, + { "FMT_SUBSAMPLING_ORDER", 20, 20, &umr_bitfield_default }, + { "FMT_CBCR_BIT_REDUCTION_BYPASS", 21, 21, &umr_bitfield_default }, + { "FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT1_FMT_BIT_DEPTH_CONTROL[] = { + { "FMT_TRUNCATE_EN", 0, 0, &umr_bitfield_default }, + { "FMT_TRUNCATE_MODE", 1, 1, &umr_bitfield_default }, + { "FMT_TRUNCATE_DEPTH", 4, 5, &umr_bitfield_default }, + { "FMT_SPATIAL_DITHER_EN", 8, 8, &umr_bitfield_default }, + { "FMT_SPATIAL_DITHER_MODE", 9, 10, &umr_bitfield_default }, + { "FMT_SPATIAL_DITHER_DEPTH", 11, 12, &umr_bitfield_default }, + { "FMT_FRAME_RANDOM_ENABLE", 13, 13, &umr_bitfield_default }, + { "FMT_RGB_RANDOM_ENABLE", 14, 14, &umr_bitfield_default }, + { "FMT_HIGHPASS_RANDOM_ENABLE", 15, 15, &umr_bitfield_default }, + { "FMT_TEMPORAL_DITHER_EN", 16, 16, &umr_bitfield_default }, + { "FMT_TEMPORAL_DITHER_DEPTH", 17, 18, &umr_bitfield_default }, + { "FMT_TEMPORAL_DITHER_OFFSET", 21, 22, &umr_bitfield_default }, + { "FMT_TEMPORAL_LEVEL", 24, 24, &umr_bitfield_default }, + { "FMT_TEMPORAL_DITHER_RESET", 25, 25, &umr_bitfield_default }, + { "FMT_25FRC_SEL", 26, 27, &umr_bitfield_default }, + { "FMT_50FRC_SEL", 28, 29, &umr_bitfield_default }, + { "FMT_75FRC_SEL", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT1_FMT_DITHER_RAND_R_SEED[] = { + { "FMT_RAND_R_SEED", 0, 7, &umr_bitfield_default }, + { "FMT_OFFSET_R_CR", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT1_FMT_DITHER_RAND_G_SEED[] = { + { "FMT_RAND_G_SEED", 0, 7, &umr_bitfield_default }, + { "FMT_OFFSET_G_Y", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT1_FMT_DITHER_RAND_B_SEED[] = { + { "FMT_RAND_B_SEED", 0, 7, &umr_bitfield_default }, + { "FMT_OFFSET_B_CB", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT1_FMT_CLAMP_CNTL[] = { + { "FMT_CLAMP_DATA_EN", 0, 0, &umr_bitfield_default }, + { "FMT_CLAMP_COLOR_FORMAT", 16, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL[] = { + { "FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH", 0, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT1_FMT_MAP420_MEMORY_CONTROL[] = { + { "FMT_MAP420MEM_PWR_FORCE", 0, 1, &umr_bitfield_default }, + { "FMT_MAP420MEM_PWR_DIS", 4, 4, &umr_bitfield_default }, + { "FMT_MAP420MEM_PWR_STATE", 8, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOPPBUF1_OPPBUF_CONTROL[] = { + { "OPPBUF_ACTIVE_WIDTH", 0, 13, &umr_bitfield_default }, + { "OPPBUF_DISPLAY_SEGMENTATION", 16, 18, &umr_bitfield_default }, + { "OPPBUF_OVERLAP_PIXEL_NUM", 20, 23, &umr_bitfield_default }, + { "OPPBUF_PIXEL_REPETITION", 24, 27, &umr_bitfield_default }, + { "OPPBUF_DOUBLE_BUFFER_PENDING", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOPPBUF1_OPPBUF_3D_PARAMETERS_0[] = { + { "OPPBUF_3D_VACT_SPACE1_SIZE", 0, 9, &umr_bitfield_default }, + { "OPPBUF_3D_VACT_SPACE2_SIZE", 10, 19, &umr_bitfield_default }, + { "OPPBUF_DUMMY_DATA_R", 20, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOPPBUF1_OPPBUF_3D_PARAMETERS_1[] = { + { "OPPBUF_DUMMY_DATA_G", 0, 11, &umr_bitfield_default }, + { "OPPBUF_DUMMY_DATA_B", 16, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOPP_PIPE1_OPP_PIPE_CONTROL[] = { + { "OPP_PIPE_CLOCK_EN", 0, 0, &umr_bitfield_default }, + { "OPP_PIPE_CLOCK_ON", 1, 1, &umr_bitfield_default }, + { "OPP_PIPE_DIGITAL_BYPASS_EN", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL[] = { + { "OPP_PIPE_CRC_EN", 0, 0, &umr_bitfield_default }, + { "OPP_PIPE_CRC_CONT_EN", 4, 4, &umr_bitfield_default }, + { "OPP_PIPE_CRC_STEREO_MODE", 8, 9, &umr_bitfield_default }, + { "OPP_PIPE_CRC_STEREO_EN", 10, 10, &umr_bitfield_default }, + { "OPP_PIPE_CRC_INTERLACE_MODE", 12, 13, &umr_bitfield_default }, + { "OPP_PIPE_CRC_INTERLACE_EN", 14, 14, &umr_bitfield_default }, + { "OPP_PIPE_CRC_PIXEL_SELECT", 20, 21, &umr_bitfield_default }, + { "OPP_PIPE_CRC_SOURCE_SELECT", 24, 24, &umr_bitfield_default }, + { "OPP_PIPE_CRC_ONE_SHOT_PENDING", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK[] = { + { "OPP_PIPE_CRC_MASK", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0[] = { + { "OPP_PIPE_CRC_RESULT_A", 0, 15, &umr_bitfield_default }, + { "OPP_PIPE_CRC_RESULT_R", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1[] = { + { "OPP_PIPE_CRC_RESULT_G", 0, 15, &umr_bitfield_default }, + { "OPP_PIPE_CRC_RESULT_B", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2[] = { + { "OPP_PIPE_CRC_RESULT_C", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT2_FMT_CLAMP_COMPONENT_R[] = { + { "FMT_CLAMP_LOWER_R", 0, 15, &umr_bitfield_default }, + { "FMT_CLAMP_UPPER_R", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT2_FMT_CLAMP_COMPONENT_G[] = { + { "FMT_CLAMP_LOWER_G", 0, 15, &umr_bitfield_default }, + { "FMT_CLAMP_UPPER_G", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT2_FMT_CLAMP_COMPONENT_B[] = { + { "FMT_CLAMP_LOWER_B", 0, 15, &umr_bitfield_default }, + { "FMT_CLAMP_UPPER_B", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT2_FMT_DYNAMIC_EXP_CNTL[] = { + { "FMT_DYNAMIC_EXP_EN", 0, 0, &umr_bitfield_default }, + { "FMT_DYNAMIC_EXP_MODE", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT2_FMT_CONTROL[] = { + { "FMT_STEREOSYNC_OVERRIDE", 0, 0, &umr_bitfield_default }, + { "FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX", 8, 11, &umr_bitfield_default }, + { "FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP", 12, 13, &umr_bitfield_default }, + { "FMT_PIXEL_ENCODING", 16, 17, &umr_bitfield_default }, + { "FMT_SUBSAMPLING_MODE", 18, 19, &umr_bitfield_default }, + { "FMT_SUBSAMPLING_ORDER", 20, 20, &umr_bitfield_default }, + { "FMT_CBCR_BIT_REDUCTION_BYPASS", 21, 21, &umr_bitfield_default }, + { "FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT2_FMT_BIT_DEPTH_CONTROL[] = { + { "FMT_TRUNCATE_EN", 0, 0, &umr_bitfield_default }, + { "FMT_TRUNCATE_MODE", 1, 1, &umr_bitfield_default }, + { "FMT_TRUNCATE_DEPTH", 4, 5, &umr_bitfield_default }, + { "FMT_SPATIAL_DITHER_EN", 8, 8, &umr_bitfield_default }, + { "FMT_SPATIAL_DITHER_MODE", 9, 10, &umr_bitfield_default }, + { "FMT_SPATIAL_DITHER_DEPTH", 11, 12, &umr_bitfield_default }, + { "FMT_FRAME_RANDOM_ENABLE", 13, 13, &umr_bitfield_default }, + { "FMT_RGB_RANDOM_ENABLE", 14, 14, &umr_bitfield_default }, + { "FMT_HIGHPASS_RANDOM_ENABLE", 15, 15, &umr_bitfield_default }, + { "FMT_TEMPORAL_DITHER_EN", 16, 16, &umr_bitfield_default }, + { "FMT_TEMPORAL_DITHER_DEPTH", 17, 18, &umr_bitfield_default }, + { "FMT_TEMPORAL_DITHER_OFFSET", 21, 22, &umr_bitfield_default }, + { "FMT_TEMPORAL_LEVEL", 24, 24, &umr_bitfield_default }, + { "FMT_TEMPORAL_DITHER_RESET", 25, 25, &umr_bitfield_default }, + { "FMT_25FRC_SEL", 26, 27, &umr_bitfield_default }, + { "FMT_50FRC_SEL", 28, 29, &umr_bitfield_default }, + { "FMT_75FRC_SEL", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT2_FMT_DITHER_RAND_R_SEED[] = { + { "FMT_RAND_R_SEED", 0, 7, &umr_bitfield_default }, + { "FMT_OFFSET_R_CR", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT2_FMT_DITHER_RAND_G_SEED[] = { + { "FMT_RAND_G_SEED", 0, 7, &umr_bitfield_default }, + { "FMT_OFFSET_G_Y", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT2_FMT_DITHER_RAND_B_SEED[] = { + { "FMT_RAND_B_SEED", 0, 7, &umr_bitfield_default }, + { "FMT_OFFSET_B_CB", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT2_FMT_CLAMP_CNTL[] = { + { "FMT_CLAMP_DATA_EN", 0, 0, &umr_bitfield_default }, + { "FMT_CLAMP_COLOR_FORMAT", 16, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL[] = { + { "FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH", 0, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT2_FMT_MAP420_MEMORY_CONTROL[] = { + { "FMT_MAP420MEM_PWR_FORCE", 0, 1, &umr_bitfield_default }, + { "FMT_MAP420MEM_PWR_DIS", 4, 4, &umr_bitfield_default }, + { "FMT_MAP420MEM_PWR_STATE", 8, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOPPBUF2_OPPBUF_CONTROL[] = { + { "OPPBUF_ACTIVE_WIDTH", 0, 13, &umr_bitfield_default }, + { "OPPBUF_DISPLAY_SEGMENTATION", 16, 18, &umr_bitfield_default }, + { "OPPBUF_OVERLAP_PIXEL_NUM", 20, 23, &umr_bitfield_default }, + { "OPPBUF_PIXEL_REPETITION", 24, 27, &umr_bitfield_default }, + { "OPPBUF_DOUBLE_BUFFER_PENDING", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOPPBUF2_OPPBUF_3D_PARAMETERS_0[] = { + { "OPPBUF_3D_VACT_SPACE1_SIZE", 0, 9, &umr_bitfield_default }, + { "OPPBUF_3D_VACT_SPACE2_SIZE", 10, 19, &umr_bitfield_default }, + { "OPPBUF_DUMMY_DATA_R", 20, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOPPBUF2_OPPBUF_3D_PARAMETERS_1[] = { + { "OPPBUF_DUMMY_DATA_G", 0, 11, &umr_bitfield_default }, + { "OPPBUF_DUMMY_DATA_B", 16, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOPP_PIPE2_OPP_PIPE_CONTROL[] = { + { "OPP_PIPE_CLOCK_EN", 0, 0, &umr_bitfield_default }, + { "OPP_PIPE_CLOCK_ON", 1, 1, &umr_bitfield_default }, + { "OPP_PIPE_DIGITAL_BYPASS_EN", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL[] = { + { "OPP_PIPE_CRC_EN", 0, 0, &umr_bitfield_default }, + { "OPP_PIPE_CRC_CONT_EN", 4, 4, &umr_bitfield_default }, + { "OPP_PIPE_CRC_STEREO_MODE", 8, 9, &umr_bitfield_default }, + { "OPP_PIPE_CRC_STEREO_EN", 10, 10, &umr_bitfield_default }, + { "OPP_PIPE_CRC_INTERLACE_MODE", 12, 13, &umr_bitfield_default }, + { "OPP_PIPE_CRC_INTERLACE_EN", 14, 14, &umr_bitfield_default }, + { "OPP_PIPE_CRC_PIXEL_SELECT", 20, 21, &umr_bitfield_default }, + { "OPP_PIPE_CRC_SOURCE_SELECT", 24, 24, &umr_bitfield_default }, + { "OPP_PIPE_CRC_ONE_SHOT_PENDING", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK[] = { + { "OPP_PIPE_CRC_MASK", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0[] = { + { "OPP_PIPE_CRC_RESULT_A", 0, 15, &umr_bitfield_default }, + { "OPP_PIPE_CRC_RESULT_R", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1[] = { + { "OPP_PIPE_CRC_RESULT_G", 0, 15, &umr_bitfield_default }, + { "OPP_PIPE_CRC_RESULT_B", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2[] = { + { "OPP_PIPE_CRC_RESULT_C", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT3_FMT_CLAMP_COMPONENT_R[] = { + { "FMT_CLAMP_LOWER_R", 0, 15, &umr_bitfield_default }, + { "FMT_CLAMP_UPPER_R", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT3_FMT_CLAMP_COMPONENT_G[] = { + { "FMT_CLAMP_LOWER_G", 0, 15, &umr_bitfield_default }, + { "FMT_CLAMP_UPPER_G", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT3_FMT_CLAMP_COMPONENT_B[] = { + { "FMT_CLAMP_LOWER_B", 0, 15, &umr_bitfield_default }, + { "FMT_CLAMP_UPPER_B", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT3_FMT_DYNAMIC_EXP_CNTL[] = { + { "FMT_DYNAMIC_EXP_EN", 0, 0, &umr_bitfield_default }, + { "FMT_DYNAMIC_EXP_MODE", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT3_FMT_CONTROL[] = { + { "FMT_STEREOSYNC_OVERRIDE", 0, 0, &umr_bitfield_default }, + { "FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX", 8, 11, &umr_bitfield_default }, + { "FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP", 12, 13, &umr_bitfield_default }, + { "FMT_PIXEL_ENCODING", 16, 17, &umr_bitfield_default }, + { "FMT_SUBSAMPLING_MODE", 18, 19, &umr_bitfield_default }, + { "FMT_SUBSAMPLING_ORDER", 20, 20, &umr_bitfield_default }, + { "FMT_CBCR_BIT_REDUCTION_BYPASS", 21, 21, &umr_bitfield_default }, + { "FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT3_FMT_BIT_DEPTH_CONTROL[] = { + { "FMT_TRUNCATE_EN", 0, 0, &umr_bitfield_default }, + { "FMT_TRUNCATE_MODE", 1, 1, &umr_bitfield_default }, + { "FMT_TRUNCATE_DEPTH", 4, 5, &umr_bitfield_default }, + { "FMT_SPATIAL_DITHER_EN", 8, 8, &umr_bitfield_default }, + { "FMT_SPATIAL_DITHER_MODE", 9, 10, &umr_bitfield_default }, + { "FMT_SPATIAL_DITHER_DEPTH", 11, 12, &umr_bitfield_default }, + { "FMT_FRAME_RANDOM_ENABLE", 13, 13, &umr_bitfield_default }, + { "FMT_RGB_RANDOM_ENABLE", 14, 14, &umr_bitfield_default }, + { "FMT_HIGHPASS_RANDOM_ENABLE", 15, 15, &umr_bitfield_default }, + { "FMT_TEMPORAL_DITHER_EN", 16, 16, &umr_bitfield_default }, + { "FMT_TEMPORAL_DITHER_DEPTH", 17, 18, &umr_bitfield_default }, + { "FMT_TEMPORAL_DITHER_OFFSET", 21, 22, &umr_bitfield_default }, + { "FMT_TEMPORAL_LEVEL", 24, 24, &umr_bitfield_default }, + { "FMT_TEMPORAL_DITHER_RESET", 25, 25, &umr_bitfield_default }, + { "FMT_25FRC_SEL", 26, 27, &umr_bitfield_default }, + { "FMT_50FRC_SEL", 28, 29, &umr_bitfield_default }, + { "FMT_75FRC_SEL", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT3_FMT_DITHER_RAND_R_SEED[] = { + { "FMT_RAND_R_SEED", 0, 7, &umr_bitfield_default }, + { "FMT_OFFSET_R_CR", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT3_FMT_DITHER_RAND_G_SEED[] = { + { "FMT_RAND_G_SEED", 0, 7, &umr_bitfield_default }, + { "FMT_OFFSET_G_Y", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT3_FMT_DITHER_RAND_B_SEED[] = { + { "FMT_RAND_B_SEED", 0, 7, &umr_bitfield_default }, + { "FMT_OFFSET_B_CB", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT3_FMT_CLAMP_CNTL[] = { + { "FMT_CLAMP_DATA_EN", 0, 0, &umr_bitfield_default }, + { "FMT_CLAMP_COLOR_FORMAT", 16, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL[] = { + { "FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH", 0, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT3_FMT_MAP420_MEMORY_CONTROL[] = { + { "FMT_MAP420MEM_PWR_FORCE", 0, 1, &umr_bitfield_default }, + { "FMT_MAP420MEM_PWR_DIS", 4, 4, &umr_bitfield_default }, + { "FMT_MAP420MEM_PWR_STATE", 8, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOPPBUF3_OPPBUF_CONTROL[] = { + { "OPPBUF_ACTIVE_WIDTH", 0, 13, &umr_bitfield_default }, + { "OPPBUF_DISPLAY_SEGMENTATION", 16, 18, &umr_bitfield_default }, + { "OPPBUF_OVERLAP_PIXEL_NUM", 20, 23, &umr_bitfield_default }, + { "OPPBUF_PIXEL_REPETITION", 24, 27, &umr_bitfield_default }, + { "OPPBUF_DOUBLE_BUFFER_PENDING", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOPPBUF3_OPPBUF_3D_PARAMETERS_0[] = { + { "OPPBUF_3D_VACT_SPACE1_SIZE", 0, 9, &umr_bitfield_default }, + { "OPPBUF_3D_VACT_SPACE2_SIZE", 10, 19, &umr_bitfield_default }, + { "OPPBUF_DUMMY_DATA_R", 20, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOPPBUF3_OPPBUF_3D_PARAMETERS_1[] = { + { "OPPBUF_DUMMY_DATA_G", 0, 11, &umr_bitfield_default }, + { "OPPBUF_DUMMY_DATA_B", 16, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOPP_PIPE3_OPP_PIPE_CONTROL[] = { + { "OPP_PIPE_CLOCK_EN", 0, 0, &umr_bitfield_default }, + { "OPP_PIPE_CLOCK_ON", 1, 1, &umr_bitfield_default }, + { "OPP_PIPE_DIGITAL_BYPASS_EN", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL[] = { + { "OPP_PIPE_CRC_EN", 0, 0, &umr_bitfield_default }, + { "OPP_PIPE_CRC_CONT_EN", 4, 4, &umr_bitfield_default }, + { "OPP_PIPE_CRC_STEREO_MODE", 8, 9, &umr_bitfield_default }, + { "OPP_PIPE_CRC_STEREO_EN", 10, 10, &umr_bitfield_default }, + { "OPP_PIPE_CRC_INTERLACE_MODE", 12, 13, &umr_bitfield_default }, + { "OPP_PIPE_CRC_INTERLACE_EN", 14, 14, &umr_bitfield_default }, + { "OPP_PIPE_CRC_PIXEL_SELECT", 20, 21, &umr_bitfield_default }, + { "OPP_PIPE_CRC_SOURCE_SELECT", 24, 24, &umr_bitfield_default }, + { "OPP_PIPE_CRC_ONE_SHOT_PENDING", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK[] = { + { "OPP_PIPE_CRC_MASK", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0[] = { + { "OPP_PIPE_CRC_RESULT_A", 0, 15, &umr_bitfield_default }, + { "OPP_PIPE_CRC_RESULT_R", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1[] = { + { "OPP_PIPE_CRC_RESULT_G", 0, 15, &umr_bitfield_default }, + { "OPP_PIPE_CRC_RESULT_B", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2[] = { + { "OPP_PIPE_CRC_RESULT_C", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT4_FMT_CLAMP_COMPONENT_R[] = { + { "FMT_CLAMP_LOWER_R", 0, 15, &umr_bitfield_default }, + { "FMT_CLAMP_UPPER_R", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT4_FMT_CLAMP_COMPONENT_G[] = { + { "FMT_CLAMP_LOWER_G", 0, 15, &umr_bitfield_default }, + { "FMT_CLAMP_UPPER_G", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT4_FMT_CLAMP_COMPONENT_B[] = { + { "FMT_CLAMP_LOWER_B", 0, 15, &umr_bitfield_default }, + { "FMT_CLAMP_UPPER_B", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT4_FMT_DYNAMIC_EXP_CNTL[] = { + { "FMT_DYNAMIC_EXP_EN", 0, 0, &umr_bitfield_default }, + { "FMT_DYNAMIC_EXP_MODE", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT4_FMT_CONTROL[] = { + { "FMT_STEREOSYNC_OVERRIDE", 0, 0, &umr_bitfield_default }, + { "FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX", 8, 11, &umr_bitfield_default }, + { "FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP", 12, 13, &umr_bitfield_default }, + { "FMT_PIXEL_ENCODING", 16, 17, &umr_bitfield_default }, + { "FMT_SUBSAMPLING_MODE", 18, 19, &umr_bitfield_default }, + { "FMT_SUBSAMPLING_ORDER", 20, 20, &umr_bitfield_default }, + { "FMT_CBCR_BIT_REDUCTION_BYPASS", 21, 21, &umr_bitfield_default }, + { "FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT4_FMT_BIT_DEPTH_CONTROL[] = { + { "FMT_TRUNCATE_EN", 0, 0, &umr_bitfield_default }, + { "FMT_TRUNCATE_MODE", 1, 1, &umr_bitfield_default }, + { "FMT_TRUNCATE_DEPTH", 4, 5, &umr_bitfield_default }, + { "FMT_SPATIAL_DITHER_EN", 8, 8, &umr_bitfield_default }, + { "FMT_SPATIAL_DITHER_MODE", 9, 10, &umr_bitfield_default }, + { "FMT_SPATIAL_DITHER_DEPTH", 11, 12, &umr_bitfield_default }, + { "FMT_FRAME_RANDOM_ENABLE", 13, 13, &umr_bitfield_default }, + { "FMT_RGB_RANDOM_ENABLE", 14, 14, &umr_bitfield_default }, + { "FMT_HIGHPASS_RANDOM_ENABLE", 15, 15, &umr_bitfield_default }, + { "FMT_TEMPORAL_DITHER_EN", 16, 16, &umr_bitfield_default }, + { "FMT_TEMPORAL_DITHER_DEPTH", 17, 18, &umr_bitfield_default }, + { "FMT_TEMPORAL_DITHER_OFFSET", 21, 22, &umr_bitfield_default }, + { "FMT_TEMPORAL_LEVEL", 24, 24, &umr_bitfield_default }, + { "FMT_TEMPORAL_DITHER_RESET", 25, 25, &umr_bitfield_default }, + { "FMT_25FRC_SEL", 26, 27, &umr_bitfield_default }, + { "FMT_50FRC_SEL", 28, 29, &umr_bitfield_default }, + { "FMT_75FRC_SEL", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT4_FMT_DITHER_RAND_R_SEED[] = { + { "FMT_RAND_R_SEED", 0, 7, &umr_bitfield_default }, + { "FMT_OFFSET_R_CR", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT4_FMT_DITHER_RAND_G_SEED[] = { + { "FMT_RAND_G_SEED", 0, 7, &umr_bitfield_default }, + { "FMT_OFFSET_G_Y", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT4_FMT_DITHER_RAND_B_SEED[] = { + { "FMT_RAND_B_SEED", 0, 7, &umr_bitfield_default }, + { "FMT_OFFSET_B_CB", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT4_FMT_CLAMP_CNTL[] = { + { "FMT_CLAMP_DATA_EN", 0, 0, &umr_bitfield_default }, + { "FMT_CLAMP_COLOR_FORMAT", 16, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL[] = { + { "FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH", 0, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT4_FMT_MAP420_MEMORY_CONTROL[] = { + { "FMT_MAP420MEM_PWR_FORCE", 0, 1, &umr_bitfield_default }, + { "FMT_MAP420MEM_PWR_DIS", 4, 4, &umr_bitfield_default }, + { "FMT_MAP420MEM_PWR_STATE", 8, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOPPBUF4_OPPBUF_CONTROL[] = { + { "OPPBUF_ACTIVE_WIDTH", 0, 13, &umr_bitfield_default }, + { "OPPBUF_DISPLAY_SEGMENTATION", 16, 18, &umr_bitfield_default }, + { "OPPBUF_OVERLAP_PIXEL_NUM", 20, 23, &umr_bitfield_default }, + { "OPPBUF_PIXEL_REPETITION", 24, 27, &umr_bitfield_default }, + { "OPPBUF_DOUBLE_BUFFER_PENDING", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOPPBUF4_OPPBUF_3D_PARAMETERS_0[] = { + { "OPPBUF_3D_VACT_SPACE1_SIZE", 0, 9, &umr_bitfield_default }, + { "OPPBUF_3D_VACT_SPACE2_SIZE", 10, 19, &umr_bitfield_default }, + { "OPPBUF_DUMMY_DATA_R", 20, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOPPBUF4_OPPBUF_3D_PARAMETERS_1[] = { + { "OPPBUF_DUMMY_DATA_G", 0, 11, &umr_bitfield_default }, + { "OPPBUF_DUMMY_DATA_B", 16, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOPP_PIPE4_OPP_PIPE_CONTROL[] = { + { "OPP_PIPE_CLOCK_EN", 0, 0, &umr_bitfield_default }, + { "OPP_PIPE_CLOCK_ON", 1, 1, &umr_bitfield_default }, + { "OPP_PIPE_DIGITAL_BYPASS_EN", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL[] = { + { "OPP_PIPE_CRC_EN", 0, 0, &umr_bitfield_default }, + { "OPP_PIPE_CRC_CONT_EN", 4, 4, &umr_bitfield_default }, + { "OPP_PIPE_CRC_STEREO_MODE", 8, 9, &umr_bitfield_default }, + { "OPP_PIPE_CRC_STEREO_EN", 10, 10, &umr_bitfield_default }, + { "OPP_PIPE_CRC_INTERLACE_MODE", 12, 13, &umr_bitfield_default }, + { "OPP_PIPE_CRC_INTERLACE_EN", 14, 14, &umr_bitfield_default }, + { "OPP_PIPE_CRC_PIXEL_SELECT", 20, 21, &umr_bitfield_default }, + { "OPP_PIPE_CRC_SOURCE_SELECT", 24, 24, &umr_bitfield_default }, + { "OPP_PIPE_CRC_ONE_SHOT_PENDING", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOPP_PIPE_CRC4_OPP_PIPE_CRC_MASK[] = { + { "OPP_PIPE_CRC_MASK", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0[] = { + { "OPP_PIPE_CRC_RESULT_A", 0, 15, &umr_bitfield_default }, + { "OPP_PIPE_CRC_RESULT_R", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1[] = { + { "OPP_PIPE_CRC_RESULT_G", 0, 15, &umr_bitfield_default }, + { "OPP_PIPE_CRC_RESULT_B", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2[] = { + { "OPP_PIPE_CRC_RESULT_C", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT5_FMT_CLAMP_COMPONENT_R[] = { + { "FMT_CLAMP_LOWER_R", 0, 15, &umr_bitfield_default }, + { "FMT_CLAMP_UPPER_R", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT5_FMT_CLAMP_COMPONENT_G[] = { + { "FMT_CLAMP_LOWER_G", 0, 15, &umr_bitfield_default }, + { "FMT_CLAMP_UPPER_G", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT5_FMT_CLAMP_COMPONENT_B[] = { + { "FMT_CLAMP_LOWER_B", 0, 15, &umr_bitfield_default }, + { "FMT_CLAMP_UPPER_B", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT5_FMT_DYNAMIC_EXP_CNTL[] = { + { "FMT_DYNAMIC_EXP_EN", 0, 0, &umr_bitfield_default }, + { "FMT_DYNAMIC_EXP_MODE", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT5_FMT_CONTROL[] = { + { "FMT_STEREOSYNC_OVERRIDE", 0, 0, &umr_bitfield_default }, + { "FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX", 8, 11, &umr_bitfield_default }, + { "FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP", 12, 13, &umr_bitfield_default }, + { "FMT_PIXEL_ENCODING", 16, 17, &umr_bitfield_default }, + { "FMT_SUBSAMPLING_MODE", 18, 19, &umr_bitfield_default }, + { "FMT_SUBSAMPLING_ORDER", 20, 20, &umr_bitfield_default }, + { "FMT_CBCR_BIT_REDUCTION_BYPASS", 21, 21, &umr_bitfield_default }, + { "FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT5_FMT_BIT_DEPTH_CONTROL[] = { + { "FMT_TRUNCATE_EN", 0, 0, &umr_bitfield_default }, + { "FMT_TRUNCATE_MODE", 1, 1, &umr_bitfield_default }, + { "FMT_TRUNCATE_DEPTH", 4, 5, &umr_bitfield_default }, + { "FMT_SPATIAL_DITHER_EN", 8, 8, &umr_bitfield_default }, + { "FMT_SPATIAL_DITHER_MODE", 9, 10, &umr_bitfield_default }, + { "FMT_SPATIAL_DITHER_DEPTH", 11, 12, &umr_bitfield_default }, + { "FMT_FRAME_RANDOM_ENABLE", 13, 13, &umr_bitfield_default }, + { "FMT_RGB_RANDOM_ENABLE", 14, 14, &umr_bitfield_default }, + { "FMT_HIGHPASS_RANDOM_ENABLE", 15, 15, &umr_bitfield_default }, + { "FMT_TEMPORAL_DITHER_EN", 16, 16, &umr_bitfield_default }, + { "FMT_TEMPORAL_DITHER_DEPTH", 17, 18, &umr_bitfield_default }, + { "FMT_TEMPORAL_DITHER_OFFSET", 21, 22, &umr_bitfield_default }, + { "FMT_TEMPORAL_LEVEL", 24, 24, &umr_bitfield_default }, + { "FMT_TEMPORAL_DITHER_RESET", 25, 25, &umr_bitfield_default }, + { "FMT_25FRC_SEL", 26, 27, &umr_bitfield_default }, + { "FMT_50FRC_SEL", 28, 29, &umr_bitfield_default }, + { "FMT_75FRC_SEL", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT5_FMT_DITHER_RAND_R_SEED[] = { + { "FMT_RAND_R_SEED", 0, 7, &umr_bitfield_default }, + { "FMT_OFFSET_R_CR", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT5_FMT_DITHER_RAND_G_SEED[] = { + { "FMT_RAND_G_SEED", 0, 7, &umr_bitfield_default }, + { "FMT_OFFSET_G_Y", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT5_FMT_DITHER_RAND_B_SEED[] = { + { "FMT_RAND_B_SEED", 0, 7, &umr_bitfield_default }, + { "FMT_OFFSET_B_CB", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT5_FMT_CLAMP_CNTL[] = { + { "FMT_CLAMP_DATA_EN", 0, 0, &umr_bitfield_default }, + { "FMT_CLAMP_COLOR_FORMAT", 16, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL[] = { + { "FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH", 0, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmFMT5_FMT_MAP420_MEMORY_CONTROL[] = { + { "FMT_MAP420MEM_PWR_FORCE", 0, 1, &umr_bitfield_default }, + { "FMT_MAP420MEM_PWR_DIS", 4, 4, &umr_bitfield_default }, + { "FMT_MAP420MEM_PWR_STATE", 8, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOPPBUF5_OPPBUF_CONTROL[] = { + { "OPPBUF_ACTIVE_WIDTH", 0, 13, &umr_bitfield_default }, + { "OPPBUF_DISPLAY_SEGMENTATION", 16, 18, &umr_bitfield_default }, + { "OPPBUF_OVERLAP_PIXEL_NUM", 20, 23, &umr_bitfield_default }, + { "OPPBUF_PIXEL_REPETITION", 24, 27, &umr_bitfield_default }, + { "OPPBUF_DOUBLE_BUFFER_PENDING", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOPPBUF5_OPPBUF_3D_PARAMETERS_0[] = { + { "OPPBUF_3D_VACT_SPACE1_SIZE", 0, 9, &umr_bitfield_default }, + { "OPPBUF_3D_VACT_SPACE2_SIZE", 10, 19, &umr_bitfield_default }, + { "OPPBUF_DUMMY_DATA_R", 20, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOPPBUF5_OPPBUF_3D_PARAMETERS_1[] = { + { "OPPBUF_DUMMY_DATA_G", 0, 11, &umr_bitfield_default }, + { "OPPBUF_DUMMY_DATA_B", 16, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOPP_PIPE5_OPP_PIPE_CONTROL[] = { + { "OPP_PIPE_CLOCK_EN", 0, 0, &umr_bitfield_default }, + { "OPP_PIPE_CLOCK_ON", 1, 1, &umr_bitfield_default }, + { "OPP_PIPE_DIGITAL_BYPASS_EN", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL[] = { + { "OPP_PIPE_CRC_EN", 0, 0, &umr_bitfield_default }, + { "OPP_PIPE_CRC_CONT_EN", 4, 4, &umr_bitfield_default }, + { "OPP_PIPE_CRC_STEREO_MODE", 8, 9, &umr_bitfield_default }, + { "OPP_PIPE_CRC_STEREO_EN", 10, 10, &umr_bitfield_default }, + { "OPP_PIPE_CRC_INTERLACE_MODE", 12, 13, &umr_bitfield_default }, + { "OPP_PIPE_CRC_INTERLACE_EN", 14, 14, &umr_bitfield_default }, + { "OPP_PIPE_CRC_PIXEL_SELECT", 20, 21, &umr_bitfield_default }, + { "OPP_PIPE_CRC_SOURCE_SELECT", 24, 24, &umr_bitfield_default }, + { "OPP_PIPE_CRC_ONE_SHOT_PENDING", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOPP_PIPE_CRC5_OPP_PIPE_CRC_MASK[] = { + { "OPP_PIPE_CRC_MASK", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0[] = { + { "OPP_PIPE_CRC_RESULT_A", 0, 15, &umr_bitfield_default }, + { "OPP_PIPE_CRC_RESULT_R", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1[] = { + { "OPP_PIPE_CRC_RESULT_G", 0, 15, &umr_bitfield_default }, + { "OPP_PIPE_CRC_RESULT_B", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT2[] = { + { "OPP_PIPE_CRC_RESULT_C", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOPP_TOP_CLK_CONTROL[] = { + { "OPP_DISPCLK_R_GATE_DIS", 0, 0, &umr_bitfield_default }, + { "OPP_DISPCLK_G_ABM_GATE_DIS", 4, 4, &umr_bitfield_default }, + { "OPP_TEST_CLK_SEL", 8, 11, &umr_bitfield_default }, + { "OPP_ABM0_CLOCK_ON", 12, 12, &umr_bitfield_default }, + { "OPP_ABM1_CLOCK_ON", 13, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON17_PERFCOUNTER_CNTL[] = { + { "PERFCOUNTER_EVENT_SEL", 0, 8, &umr_bitfield_default }, + { "PERFCOUNTER_CVALUE_SEL", 9, 11, &umr_bitfield_default }, + { "PERFCOUNTER_INC_MODE", 12, 14, &umr_bitfield_default }, + { "PERFCOUNTER_HW_CNTL_SEL", 15, 15, &umr_bitfield_default }, + { "PERFCOUNTER_RUNEN_MODE", 16, 16, &umr_bitfield_default }, + { "PERFCOUNTER_CNTOFF_START_DIS", 22, 22, &umr_bitfield_default }, + { "PERFCOUNTER_RESTART_EN", 23, 23, &umr_bitfield_default }, + { "PERFCOUNTER_INT_EN", 24, 24, &umr_bitfield_default }, + { "PERFCOUNTER_OFF_MASK", 25, 25, &umr_bitfield_default }, + { "PERFCOUNTER_ACTIVE", 26, 26, &umr_bitfield_default }, + { "PERFCOUNTER_CNTL_SEL", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON17_PERFCOUNTER_CNTL2[] = { + { "PERFCOUNTER_COUNTED_VALUE_TYPE", 0, 1, &umr_bitfield_default }, + { "PERFCOUNTER_HW_STOP1_SEL", 2, 2, &umr_bitfield_default }, + { "PERFCOUNTER_HW_STOP2_SEL", 3, 3, &umr_bitfield_default }, + { "PERFCOUNTER_CNTOFF_SEL", 8, 13, &umr_bitfield_default }, + { "PERFCOUNTER_CNTL2_SEL", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON17_PERFCOUNTER_STATE[] = { + { "PERFCOUNTER_CNT0_STATE", 0, 1, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL0", 2, 2, &umr_bitfield_default }, + { "PERFCOUNTER_CNT1_STATE", 4, 5, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL1", 6, 6, &umr_bitfield_default }, + { "PERFCOUNTER_CNT2_STATE", 8, 9, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL2", 10, 10, &umr_bitfield_default }, + { "PERFCOUNTER_CNT3_STATE", 12, 13, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL3", 14, 14, &umr_bitfield_default }, + { "PERFCOUNTER_CNT4_STATE", 16, 17, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL4", 18, 18, &umr_bitfield_default }, + { "PERFCOUNTER_CNT5_STATE", 20, 21, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL5", 22, 22, &umr_bitfield_default }, + { "PERFCOUNTER_CNT6_STATE", 24, 25, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL6", 26, 26, &umr_bitfield_default }, + { "PERFCOUNTER_CNT7_STATE", 28, 29, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL7", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON17_PERFMON_CNTL[] = { + { "PERFMON_STATE", 0, 1, &umr_bitfield_default }, + { "PERFMON_RPT_COUNT", 8, 27, &umr_bitfield_default }, + { "PERFMON_CNTOFF_AND_OR", 28, 28, &umr_bitfield_default }, + { "PERFMON_CNTOFF_INT_EN", 29, 29, &umr_bitfield_default }, + { "PERFMON_CNTOFF_INT_STATUS", 30, 30, &umr_bitfield_default }, + { "PERFMON_CNTOFF_INT_ACK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON17_PERFMON_CNTL2[] = { + { "PERFMON_CNTOFF_INT_TYPE", 0, 0, &umr_bitfield_default }, + { "PERFMON_CLK_ENABLE", 1, 1, &umr_bitfield_default }, + { "PERFMON_RUN_ENABLE_START_SEL", 2, 9, &umr_bitfield_default }, + { "PERFMON_RUN_ENABLE_STOP_SEL", 10, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON17_PERFMON_CVALUE_INT_MISC[] = { + { "PERFCOUNTER_INT0_STATUS", 0, 0, &umr_bitfield_default }, + { "PERFCOUNTER_INT1_STATUS", 1, 1, &umr_bitfield_default }, + { "PERFCOUNTER_INT2_STATUS", 2, 2, &umr_bitfield_default }, + { "PERFCOUNTER_INT3_STATUS", 3, 3, &umr_bitfield_default }, + { "PERFCOUNTER_INT4_STATUS", 4, 4, &umr_bitfield_default }, + { "PERFCOUNTER_INT5_STATUS", 5, 5, &umr_bitfield_default }, + { "PERFCOUNTER_INT6_STATUS", 6, 6, &umr_bitfield_default }, + { "PERFCOUNTER_INT7_STATUS", 7, 7, &umr_bitfield_default }, + { "PERFCOUNTER_INT0_ACK", 8, 8, &umr_bitfield_default }, + { "PERFCOUNTER_INT1_ACK", 9, 9, &umr_bitfield_default }, + { "PERFCOUNTER_INT2_ACK", 10, 10, &umr_bitfield_default }, + { "PERFCOUNTER_INT3_ACK", 11, 11, &umr_bitfield_default }, + { "PERFCOUNTER_INT4_ACK", 12, 12, &umr_bitfield_default }, + { "PERFCOUNTER_INT5_ACK", 13, 13, &umr_bitfield_default }, + { "PERFCOUNTER_INT6_ACK", 14, 14, &umr_bitfield_default }, + { "PERFCOUNTER_INT7_ACK", 15, 15, &umr_bitfield_default }, + { "PERFMON_CVALUE_HI", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON17_PERFMON_CVALUE_LOW[] = { + { "PERFMON_CVALUE_LOW", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON17_PERFMON_HI[] = { + { "PERFMON_HI", 0, 15, &umr_bitfield_default }, + { "PERFMON_READ_SEL", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON17_PERFMON_LOW[] = { + { "PERFMON_LOW", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmODM0_OPTC_INPUT_GLOBAL_CONTROL[] = { + { "OPTC_INPUT_SOFT_RESET", 0, 0, &umr_bitfield_default }, + { "OPTC_UNDERFLOW_INT_EN", 8, 8, &umr_bitfield_default }, + { "OPTC_UNDERFLOW_INT_TYPE", 9, 9, &umr_bitfield_default }, + { "OPTC_UNDERFLOW_OCCURRED_STATUS", 10, 10, &umr_bitfield_default }, + { "OPTC_UNDERFLOW_INT_STATUS", 11, 11, &umr_bitfield_default }, + { "OPTC_UNDERFLOW_CLEAR", 12, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmODM0_OPTC_DATA_SOURCE_SELECT[] = { + { "OPTC_SRC_SEL", 8, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmODM0_OPTC_INPUT_CLOCK_CONTROL[] = { + { "OPTC_INPUT_CLK_GATE_DIS", 0, 0, &umr_bitfield_default }, + { "OPTC_INPUT_CLK_EN", 1, 1, &umr_bitfield_default }, + { "OPTC_INPUT_CLK_ON", 2, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmODM0_OPTC_INPUT_SPARE_REGISTER[] = { + { "OPTC_INPUT_SPARE_REG", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmODM1_OPTC_INPUT_GLOBAL_CONTROL[] = { + { "OPTC_INPUT_SOFT_RESET", 0, 0, &umr_bitfield_default }, + { "OPTC_UNDERFLOW_INT_EN", 8, 8, &umr_bitfield_default }, + { "OPTC_UNDERFLOW_INT_TYPE", 9, 9, &umr_bitfield_default }, + { "OPTC_UNDERFLOW_OCCURRED_STATUS", 10, 10, &umr_bitfield_default }, + { "OPTC_UNDERFLOW_INT_STATUS", 11, 11, &umr_bitfield_default }, + { "OPTC_UNDERFLOW_CLEAR", 12, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmODM1_OPTC_DATA_SOURCE_SELECT[] = { + { "OPTC_SRC_SEL", 8, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmODM1_OPTC_INPUT_CLOCK_CONTROL[] = { + { "OPTC_INPUT_CLK_GATE_DIS", 0, 0, &umr_bitfield_default }, + { "OPTC_INPUT_CLK_EN", 1, 1, &umr_bitfield_default }, + { "OPTC_INPUT_CLK_ON", 2, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmODM1_OPTC_INPUT_SPARE_REGISTER[] = { + { "OPTC_INPUT_SPARE_REG", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmODM2_OPTC_INPUT_GLOBAL_CONTROL[] = { + { "OPTC_INPUT_SOFT_RESET", 0, 0, &umr_bitfield_default }, + { "OPTC_UNDERFLOW_INT_EN", 8, 8, &umr_bitfield_default }, + { "OPTC_UNDERFLOW_INT_TYPE", 9, 9, &umr_bitfield_default }, + { "OPTC_UNDERFLOW_OCCURRED_STATUS", 10, 10, &umr_bitfield_default }, + { "OPTC_UNDERFLOW_INT_STATUS", 11, 11, &umr_bitfield_default }, + { "OPTC_UNDERFLOW_CLEAR", 12, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmODM2_OPTC_DATA_SOURCE_SELECT[] = { + { "OPTC_SRC_SEL", 8, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmODM2_OPTC_INPUT_CLOCK_CONTROL[] = { + { "OPTC_INPUT_CLK_GATE_DIS", 0, 0, &umr_bitfield_default }, + { "OPTC_INPUT_CLK_EN", 1, 1, &umr_bitfield_default }, + { "OPTC_INPUT_CLK_ON", 2, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmODM2_OPTC_INPUT_SPARE_REGISTER[] = { + { "OPTC_INPUT_SPARE_REG", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmODM3_OPTC_INPUT_GLOBAL_CONTROL[] = { + { "OPTC_INPUT_SOFT_RESET", 0, 0, &umr_bitfield_default }, + { "OPTC_UNDERFLOW_INT_EN", 8, 8, &umr_bitfield_default }, + { "OPTC_UNDERFLOW_INT_TYPE", 9, 9, &umr_bitfield_default }, + { "OPTC_UNDERFLOW_OCCURRED_STATUS", 10, 10, &umr_bitfield_default }, + { "OPTC_UNDERFLOW_INT_STATUS", 11, 11, &umr_bitfield_default }, + { "OPTC_UNDERFLOW_CLEAR", 12, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmODM3_OPTC_DATA_SOURCE_SELECT[] = { + { "OPTC_SRC_SEL", 8, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmODM3_OPTC_INPUT_CLOCK_CONTROL[] = { + { "OPTC_INPUT_CLK_GATE_DIS", 0, 0, &umr_bitfield_default }, + { "OPTC_INPUT_CLK_EN", 1, 1, &umr_bitfield_default }, + { "OPTC_INPUT_CLK_ON", 2, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmODM3_OPTC_INPUT_SPARE_REGISTER[] = { + { "OPTC_INPUT_SPARE_REG", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmODM4_OPTC_INPUT_GLOBAL_CONTROL[] = { + { "OPTC_INPUT_SOFT_RESET", 0, 0, &umr_bitfield_default }, + { "OPTC_UNDERFLOW_INT_EN", 8, 8, &umr_bitfield_default }, + { "OPTC_UNDERFLOW_INT_TYPE", 9, 9, &umr_bitfield_default }, + { "OPTC_UNDERFLOW_OCCURRED_STATUS", 10, 10, &umr_bitfield_default }, + { "OPTC_UNDERFLOW_INT_STATUS", 11, 11, &umr_bitfield_default }, + { "OPTC_UNDERFLOW_CLEAR", 12, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmODM4_OPTC_DATA_SOURCE_SELECT[] = { + { "OPTC_SRC_SEL", 8, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmODM4_OPTC_INPUT_CLOCK_CONTROL[] = { + { "OPTC_INPUT_CLK_GATE_DIS", 0, 0, &umr_bitfield_default }, + { "OPTC_INPUT_CLK_EN", 1, 1, &umr_bitfield_default }, + { "OPTC_INPUT_CLK_ON", 2, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmODM4_OPTC_INPUT_SPARE_REGISTER[] = { + { "OPTC_INPUT_SPARE_REG", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmODM5_OPTC_INPUT_GLOBAL_CONTROL[] = { + { "OPTC_INPUT_SOFT_RESET", 0, 0, &umr_bitfield_default }, + { "OPTC_UNDERFLOW_INT_EN", 8, 8, &umr_bitfield_default }, + { "OPTC_UNDERFLOW_INT_TYPE", 9, 9, &umr_bitfield_default }, + { "OPTC_UNDERFLOW_OCCURRED_STATUS", 10, 10, &umr_bitfield_default }, + { "OPTC_UNDERFLOW_INT_STATUS", 11, 11, &umr_bitfield_default }, + { "OPTC_UNDERFLOW_CLEAR", 12, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmODM5_OPTC_DATA_SOURCE_SELECT[] = { + { "OPTC_SRC_SEL", 8, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmODM5_OPTC_INPUT_CLOCK_CONTROL[] = { + { "OPTC_INPUT_CLK_GATE_DIS", 0, 0, &umr_bitfield_default }, + { "OPTC_INPUT_CLK_EN", 1, 1, &umr_bitfield_default }, + { "OPTC_INPUT_CLK_ON", 2, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmODM5_OPTC_INPUT_SPARE_REGISTER[] = { + { "OPTC_INPUT_SPARE_REG", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_H_TOTAL[] = { + { "OTG_H_TOTAL", 0, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_H_BLANK_START_END[] = { + { "OTG_H_BLANK_START", 0, 14, &umr_bitfield_default }, + { "OTG_H_BLANK_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_H_SYNC_A[] = { + { "OTG_H_SYNC_A_START", 0, 14, &umr_bitfield_default }, + { "OTG_H_SYNC_A_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_H_SYNC_A_CNTL[] = { + { "OTG_H_SYNC_A_POL", 0, 0, &umr_bitfield_default }, + { "OTG_COMP_SYNC_A_EN", 16, 16, &umr_bitfield_default }, + { "OTG_H_SYNC_A_CUTOFF", 17, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_H_TIMING_CNTL[] = { + { "OTG_H_TIMING_DIV_BY2", 0, 0, &umr_bitfield_default }, + { "OTG_H_TIMING_DIV_BY2_UPDATE_MODE", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_V_TOTAL[] = { + { "OTG_V_TOTAL", 0, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_V_TOTAL_MIN[] = { + { "OTG_V_TOTAL_MIN", 0, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_V_TOTAL_MAX[] = { + { "OTG_V_TOTAL_MAX", 0, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_V_TOTAL_MID[] = { + { "OTG_V_TOTAL_MID", 0, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_V_TOTAL_CONTROL[] = { + { "OTG_V_TOTAL_MIN_SEL", 0, 0, &umr_bitfield_default }, + { "OTG_V_TOTAL_MAX_SEL", 1, 1, &umr_bitfield_default }, + { "OTG_VTOTAL_MID_REPLACING_MAX_EN", 2, 2, &umr_bitfield_default }, + { "OTG_VTOTAL_MID_REPLACING_MIN_EN", 3, 3, &umr_bitfield_default }, + { "OTG_FORCE_LOCK_ON_EVENT", 4, 4, &umr_bitfield_default }, + { "OTG_SET_V_TOTAL_MIN_MASK_EN", 7, 7, &umr_bitfield_default }, + { "OTG_VTOTAL_MID_FRAME_NUM", 8, 15, &umr_bitfield_default }, + { "OTG_SET_V_TOTAL_MIN_MASK", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_V_TOTAL_INT_STATUS[] = { + { "OTG_SET_V_TOTAL_MIN_EVENT_OCCURED", 0, 0, &umr_bitfield_default }, + { "OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_INT", 4, 4, &umr_bitfield_default }, + { "OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK", 8, 8, &umr_bitfield_default }, + { "OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK", 12, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_VSYNC_NOM_INT_STATUS[] = { + { "OTG_VSYNC_NOM", 0, 0, &umr_bitfield_default }, + { "OTG_VSYNC_NOM_INT_CLEAR", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_V_BLANK_START_END[] = { + { "OTG_V_BLANK_START", 0, 14, &umr_bitfield_default }, + { "OTG_V_BLANK_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_V_SYNC_A[] = { + { "OTG_V_SYNC_A_START", 0, 14, &umr_bitfield_default }, + { "OTG_V_SYNC_A_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_V_SYNC_A_CNTL[] = { + { "OTG_V_SYNC_A_POL", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_TRIGA_CNTL[] = { + { "OTG_TRIGA_SOURCE_SELECT", 0, 4, &umr_bitfield_default }, + { "OTG_TRIGA_SOURCE_PIPE_SELECT", 5, 7, &umr_bitfield_default }, + { "OTG_TRIGA_POLARITY_SELECT", 8, 10, &umr_bitfield_default }, + { "OTG_TRIGA_RESYNC_BYPASS_EN", 11, 11, &umr_bitfield_default }, + { "OTG_TRIGA_INPUT_STATUS", 12, 12, &umr_bitfield_default }, + { "OTG_TRIGA_POLARITY_STATUS", 13, 13, &umr_bitfield_default }, + { "OTG_TRIGA_OCCURRED", 14, 14, &umr_bitfield_default }, + { "OTG_TRIGA_RISING_EDGE_DETECT_CNTL", 16, 17, &umr_bitfield_default }, + { "OTG_TRIGA_FALLING_EDGE_DETECT_CNTL", 18, 19, &umr_bitfield_default }, + { "OTG_TRIGA_FREQUENCY_SELECT", 20, 21, &umr_bitfield_default }, + { "OTG_TRIGA_DELAY", 24, 28, &umr_bitfield_default }, + { "OTG_TRIGA_CLEAR", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_TRIGA_MANUAL_TRIG[] = { + { "OTG_TRIGA_MANUAL_TRIG", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_TRIGB_CNTL[] = { + { "OTG_TRIGB_SOURCE_SELECT", 0, 4, &umr_bitfield_default }, + { "OTG_TRIGB_SOURCE_PIPE_SELECT", 5, 7, &umr_bitfield_default }, + { "OTG_TRIGB_POLARITY_SELECT", 8, 10, &umr_bitfield_default }, + { "OTG_TRIGB_RESYNC_BYPASS_EN", 11, 11, &umr_bitfield_default }, + { "OTG_TRIGB_INPUT_STATUS", 12, 12, &umr_bitfield_default }, + { "OTG_TRIGB_POLARITY_STATUS", 13, 13, &umr_bitfield_default }, + { "OTG_TRIGB_OCCURRED", 14, 14, &umr_bitfield_default }, + { "OTG_TRIGB_RISING_EDGE_DETECT_CNTL", 16, 17, &umr_bitfield_default }, + { "OTG_TRIGB_FALLING_EDGE_DETECT_CNTL", 18, 19, &umr_bitfield_default }, + { "OTG_TRIGB_FREQUENCY_SELECT", 20, 21, &umr_bitfield_default }, + { "OTG_TRIGB_DELAY", 24, 28, &umr_bitfield_default }, + { "OTG_TRIGB_CLEAR", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_TRIGB_MANUAL_TRIG[] = { + { "OTG_TRIGB_MANUAL_TRIG", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_FORCE_COUNT_NOW_CNTL[] = { + { "OTG_FORCE_COUNT_NOW_MODE", 0, 1, &umr_bitfield_default }, + { "OTG_FORCE_COUNT_NOW_CHECK", 4, 4, &umr_bitfield_default }, + { "OTG_FORCE_COUNT_NOW_TRIG_SEL", 8, 8, &umr_bitfield_default }, + { "OTG_FORCE_COUNT_NOW_OCCURRED", 16, 16, &umr_bitfield_default }, + { "OTG_FORCE_COUNT_NOW_CLEAR", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_FLOW_CONTROL[] = { + { "OTG_FLOW_CONTROL_SOURCE_SELECT", 0, 4, &umr_bitfield_default }, + { "OTG_FLOW_CONTROL_POLARITY", 8, 8, &umr_bitfield_default }, + { "OTG_FLOW_CONTROL_GRANULARITY", 16, 16, &umr_bitfield_default }, + { "OTG_FLOW_CONTROL_INPUT_STATUS", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_STEREO_FORCE_NEXT_EYE[] = { + { "OTG_STEREO_FORCE_NEXT_EYE", 0, 1, &umr_bitfield_default }, + { "OTG_AVSYNC_FRAME_COUNTER", 8, 15, &umr_bitfield_default }, + { "OTG_AVSYNC_LINE_COUNTER", 16, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_AVSYNC_COUNTER[] = { + { "OTG_AVSYNC_COUNTER", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_CONTROL[] = { + { "OTG_MASTER_EN", 0, 0, &umr_bitfield_default }, + { "OTG_DISABLE_POINT_CNTL", 8, 9, &umr_bitfield_default }, + { "OTG_START_POINT_CNTL", 12, 12, &umr_bitfield_default }, + { "OTG_FIELD_NUMBER_CNTL", 13, 13, &umr_bitfield_default }, + { "OTG_FIELD_NUMBER_POLARITY", 14, 14, &umr_bitfield_default }, + { "OTG_CURRENT_MASTER_EN_STATE", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_BLANK_CONTROL[] = { + { "OTG_CURRENT_BLANK_STATE", 0, 0, &umr_bitfield_default }, + { "OTG_BLANK_DATA_EN", 8, 8, &umr_bitfield_default }, + { "OTG_BLANK_DE_MODE", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_PIPE_ABORT_CONTROL[] = { + { "OTG_PIPE_ABORT", 0, 0, &umr_bitfield_default }, + { "OTG_PIPE_ABORT_DONE", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_INTERLACE_CONTROL[] = { + { "OTG_INTERLACE_ENABLE", 0, 0, &umr_bitfield_default }, + { "OTG_INTERLACE_FORCE_NEXT_FIELD", 16, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_INTERLACE_STATUS[] = { + { "OTG_INTERLACE_CURRENT_FIELD", 0, 0, &umr_bitfield_default }, + { "OTG_INTERLACE_NEXT_FIELD", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_FIELD_INDICATION_CONTROL[] = { + { "OTG_FIELD_INDICATION_OUTPUT_POLARITY", 0, 0, &umr_bitfield_default }, + { "OTG_FIELD_ALIGNMENT", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_PIXEL_DATA_READBACK0[] = { + { "OTG_PIXEL_DATA_BLUE_CB", 0, 15, &umr_bitfield_default }, + { "OTG_PIXEL_DATA_GREEN_Y", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_PIXEL_DATA_READBACK1[] = { + { "OTG_PIXEL_DATA_RED_CR", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_STATUS[] = { + { "OTG_V_BLANK", 0, 0, &umr_bitfield_default }, + { "OTG_V_ACTIVE_DISP", 1, 1, &umr_bitfield_default }, + { "OTG_V_SYNC_A", 2, 2, &umr_bitfield_default }, + { "OTG_V_UPDATE", 3, 3, &umr_bitfield_default }, + { "OTG_V_BLANK_3D_STRUCTURE", 5, 5, &umr_bitfield_default }, + { "OTG_H_BLANK", 16, 16, &umr_bitfield_default }, + { "OTG_H_ACTIVE_DISP", 17, 17, &umr_bitfield_default }, + { "OTG_H_SYNC_A", 18, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_STATUS_POSITION[] = { + { "OTG_VERT_COUNT", 0, 14, &umr_bitfield_default }, + { "OTG_HORZ_COUNT", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_NOM_VERT_POSITION[] = { + { "OTG_VERT_COUNT_NOM", 0, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_STATUS_FRAME_COUNT[] = { + { "OTG_FRAME_COUNT", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_STATUS_VF_COUNT[] = { + { "OTG_VF_COUNT", 0, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_STATUS_HV_COUNT[] = { + { "OTG_HV_COUNT", 0, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_COUNT_CONTROL[] = { + { "OTG_HORZ_COUNT_BY2_EN", 0, 0, &umr_bitfield_default }, + { "OTG_HORZ_REPETITION_COUNT", 1, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_COUNT_RESET[] = { + { "OTG_RESET_FRAME_COUNT", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE[] = { + { "OTG_MANUAL_FORCE_VSYNC_NEXT_LINE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_VERT_SYNC_CONTROL[] = { + { "OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED", 0, 0, &umr_bitfield_default }, + { "OTG_FORCE_VSYNC_NEXT_LINE_CLEAR", 8, 8, &umr_bitfield_default }, + { "OTG_AUTO_FORCE_VSYNC_MODE", 16, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_STEREO_STATUS[] = { + { "OTG_STEREO_CURRENT_EYE", 0, 0, &umr_bitfield_default }, + { "OTG_STEREO_SYNC_OUTPUT", 8, 8, &umr_bitfield_default }, + { "OTG_STEREO_SYNC_SELECT", 16, 16, &umr_bitfield_default }, + { "OTG_STEREO_EYE_FLAG", 20, 20, &umr_bitfield_default }, + { "OTG_STEREO_FORCE_NEXT_EYE_PENDING", 24, 25, &umr_bitfield_default }, + { "OTG_CURRENT_3D_STRUCTURE_STATE", 30, 30, &umr_bitfield_default }, + { "OTG_CURRENT_STEREOSYNC_EN_STATE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_STEREO_CONTROL[] = { + { "OTG_STEREO_SYNC_OUTPUT_LINE_NUM", 0, 14, &umr_bitfield_default }, + { "OTG_STEREO_SYNC_OUTPUT_POLARITY", 15, 15, &umr_bitfield_default }, + { "OTG_STEREO_EYE_FLAG_POLARITY", 17, 17, &umr_bitfield_default }, + { "OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP", 18, 18, &umr_bitfield_default }, + { "OTG_DISABLE_FIELD_NUM", 19, 19, &umr_bitfield_default }, + { "OTG_DISABLE_V_BLANK_FOR_DP_FIX", 20, 20, &umr_bitfield_default }, + { "OTG_STEREO_EN", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_SNAPSHOT_STATUS[] = { + { "OTG_SNAPSHOT_OCCURRED", 0, 0, &umr_bitfield_default }, + { "OTG_SNAPSHOT_CLEAR", 1, 1, &umr_bitfield_default }, + { "OTG_SNAPSHOT_MANUAL_TRIGGER", 2, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_SNAPSHOT_CONTROL[] = { + { "OTG_AUTO_SNAPSHOT_TRIG_SEL", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_SNAPSHOT_POSITION[] = { + { "OTG_SNAPSHOT_VERT_COUNT", 0, 14, &umr_bitfield_default }, + { "OTG_SNAPSHOT_HORZ_COUNT", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_SNAPSHOT_FRAME[] = { + { "OTG_SNAPSHOT_FRAME_COUNT", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_INTERRUPT_CONTROL[] = { + { "OTG_SNAPSHOT_INT_MSK", 0, 0, &umr_bitfield_default }, + { "OTG_SNAPSHOT_INT_TYPE", 1, 1, &umr_bitfield_default }, + { "OTG_FORCE_COUNT_NOW_INT_MSK", 8, 8, &umr_bitfield_default }, + { "OTG_FORCE_COUNT_NOW_INT_TYPE", 9, 9, &umr_bitfield_default }, + { "OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK", 16, 16, &umr_bitfield_default }, + { "OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE", 17, 17, &umr_bitfield_default }, + { "OTG_TRIGA_INT_MSK", 24, 24, &umr_bitfield_default }, + { "OTG_TRIGB_INT_MSK", 25, 25, &umr_bitfield_default }, + { "OTG_TRIGA_INT_TYPE", 26, 26, &umr_bitfield_default }, + { "OTG_TRIGB_INT_TYPE", 27, 27, &umr_bitfield_default }, + { "OTG_VSYNC_NOM_INT_MSK", 28, 28, &umr_bitfield_default }, + { "OTG_VSYNC_NOM_INT_TYPE", 29, 29, &umr_bitfield_default }, + { "OTG_GSL_VSYNC_GAP_INT_MSK", 30, 30, &umr_bitfield_default }, + { "OTG_GSL_VSYNC_GAP_INT_TYPE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_UPDATE_LOCK[] = { + { "OTG_UPDATE_LOCK", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_DOUBLE_BUFFER_CONTROL[] = { + { "OTG_UPDATE_PENDING", 0, 0, &umr_bitfield_default }, + { "OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING", 2, 2, &umr_bitfield_default }, + { "OTG_BLANK_DATA_EN_UPDATE_PENDING", 3, 3, &umr_bitfield_default }, + { "OTG_RANGE_TIMING_DBUF_UPDATE_PENDING", 4, 4, &umr_bitfield_default }, + { "OTG_TIMING_DB_UPDATE_PENDING", 5, 5, &umr_bitfield_default }, + { "OTG_3D_CTRL_DB_UPDATE_PENDING", 6, 6, &umr_bitfield_default }, + { "OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING", 7, 7, &umr_bitfield_default }, + { "OTG_UPDATE_INSTANTLY", 8, 8, &umr_bitfield_default }, + { "OTG_BLANK_DATA_DOUBLE_BUFFER_EN", 16, 16, &umr_bitfield_default }, + { "OTG_RANGE_TIMING_DBUF_UPDATE_MODE", 24, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_TEST_PATTERN_CONTROL[] = { + { "OTG_TEST_PATTERN_EN", 0, 0, &umr_bitfield_default }, + { "OTG_TEST_PATTERN_MODE", 8, 10, &umr_bitfield_default }, + { "OTG_TEST_PATTERN_DYNAMIC_RANGE", 16, 16, &umr_bitfield_default }, + { "OTG_TEST_PATTERN_COLOR_FORMAT", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_TEST_PATTERN_PARAMETERS[] = { + { "OTG_TEST_PATTERN_INC0", 0, 3, &umr_bitfield_default }, + { "OTG_TEST_PATTERN_INC1", 4, 7, &umr_bitfield_default }, + { "OTG_TEST_PATTERN_VRES", 8, 11, &umr_bitfield_default }, + { "OTG_TEST_PATTERN_HRES", 12, 15, &umr_bitfield_default }, + { "OTG_TEST_PATTERN_RAMP0_OFFSET", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_TEST_PATTERN_COLOR[] = { + { "OTG_TEST_PATTERN_DATA", 0, 15, &umr_bitfield_default }, + { "OTG_TEST_PATTERN_MASK", 16, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_MASTER_EN[] = { + { "OTG_MASTER_EN", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_BLANK_DATA_COLOR[] = { + { "OTG_BLANK_DATA_COLOR_BLUE_CB", 0, 9, &umr_bitfield_default }, + { "OTG_BLANK_DATA_COLOR_GREEN_Y", 10, 19, &umr_bitfield_default }, + { "OTG_BLANK_DATA_COLOR_RED_CR", 20, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_BLANK_DATA_COLOR_EXT[] = { + { "OTG_BLANK_DATA_COLOR_BLUE_CB_EXT", 0, 5, &umr_bitfield_default }, + { "OTG_BLANK_DATA_COLOR_GREEN_Y_EXT", 8, 13, &umr_bitfield_default }, + { "OTG_BLANK_DATA_COLOR_RED_CR_EXT", 16, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_BLACK_COLOR[] = { + { "OTG_BLACK_COLOR_B_CB", 0, 9, &umr_bitfield_default }, + { "OTG_BLACK_COLOR_G_Y", 10, 19, &umr_bitfield_default }, + { "OTG_BLACK_COLOR_R_CR", 20, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_BLACK_COLOR_EXT[] = { + { "OTG_BLACK_COLOR_B_CB_EXT", 0, 5, &umr_bitfield_default }, + { "OTG_BLACK_COLOR_G_Y_EXT", 8, 13, &umr_bitfield_default }, + { "OTG_BLACK_COLOR_R_CR_EXT", 16, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_VERTICAL_INTERRUPT0_POSITION[] = { + { "OTG_VERTICAL_INTERRUPT0_LINE_START", 0, 14, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT0_LINE_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL[] = { + { "OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY", 4, 4, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT0_INT_ENABLE", 8, 8, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT0_STATUS", 12, 12, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT0_INT_STATUS", 16, 16, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT0_CLEAR", 20, 20, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT0_INT_TYPE", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_VERTICAL_INTERRUPT1_POSITION[] = { + { "OTG_VERTICAL_INTERRUPT1_LINE_START", 0, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL[] = { + { "OTG_VERTICAL_INTERRUPT1_INT_ENABLE", 8, 8, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT1_STATUS", 12, 12, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT1_INT_STATUS", 16, 16, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT1_CLEAR", 20, 20, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT1_INT_TYPE", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_VERTICAL_INTERRUPT2_POSITION[] = { + { "OTG_VERTICAL_INTERRUPT2_LINE_START", 0, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL[] = { + { "OTG_VERTICAL_INTERRUPT2_INT_ENABLE", 8, 8, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT2_STATUS", 12, 12, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT2_INT_STATUS", 16, 16, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT2_CLEAR", 20, 20, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT2_INT_TYPE", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_CRC_CNTL[] = { + { "OTG_CRC_EN", 0, 0, &umr_bitfield_default }, + { "OTG_CRC_DUAL_LINK_EN", 1, 1, &umr_bitfield_default }, + { "OTG_CRC_DUAL_LINK_MODE", 2, 2, &umr_bitfield_default }, + { "OTG_CRC_BLANK_ONLY", 3, 3, &umr_bitfield_default }, + { "OTG_CRC_CONT_EN", 4, 4, &umr_bitfield_default }, + { "OTG_CRC_CAPTURE_START_SEL", 5, 6, &umr_bitfield_default }, + { "OTG_CRC_STEREO_MODE", 8, 9, &umr_bitfield_default }, + { "OTG_CRC_INTERLACE_MODE", 12, 13, &umr_bitfield_default }, + { "OTG_CRC_MULTI_STREAM_MODE", 16, 18, &umr_bitfield_default }, + { "OTG_CRC_USE_NEW_AND_REPEATED_PIXELS", 19, 19, &umr_bitfield_default }, + { "OTG_CRC0_SELECT", 20, 22, &umr_bitfield_default }, + { "OTG_CRC1_SELECT", 24, 26, &umr_bitfield_default }, + { "OTG_ONE_SHOT_CRC0_PENDING", 28, 28, &umr_bitfield_default }, + { "OTG_ONE_SHOT_CRC1_PENDING", 29, 29, &umr_bitfield_default }, + { "OTG_ONE_SHOT_CRC2_PENDING", 30, 30, &umr_bitfield_default }, + { "OTG_ONE_SHOT_CRC3_PENDING", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_CRC0_WINDOWA_X_CONTROL[] = { + { "OTG_CRC0_WINDOWA_X_START", 0, 14, &umr_bitfield_default }, + { "OTG_CRC0_WINDOWA_X_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_CRC0_WINDOWA_Y_CONTROL[] = { + { "OTG_CRC0_WINDOWA_Y_START", 0, 14, &umr_bitfield_default }, + { "OTG_CRC0_WINDOWA_Y_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_CRC0_WINDOWB_X_CONTROL[] = { + { "OTG_CRC0_WINDOWB_X_START", 0, 14, &umr_bitfield_default }, + { "OTG_CRC0_WINDOWB_X_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_CRC0_WINDOWB_Y_CONTROL[] = { + { "OTG_CRC0_WINDOWB_Y_START", 0, 14, &umr_bitfield_default }, + { "OTG_CRC0_WINDOWB_Y_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_CRC0_DATA_RG[] = { + { "CRC0_R_CR", 0, 15, &umr_bitfield_default }, + { "CRC0_G_Y", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_CRC0_DATA_B[] = { + { "CRC0_B_CB", 0, 15, &umr_bitfield_default }, + { "CRC0_C", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_CRC1_WINDOWA_X_CONTROL[] = { + { "OTG_CRC1_WINDOWA_X_START", 0, 14, &umr_bitfield_default }, + { "OTG_CRC1_WINDOWA_X_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_CRC1_WINDOWA_Y_CONTROL[] = { + { "OTG_CRC1_WINDOWA_Y_START", 0, 14, &umr_bitfield_default }, + { "OTG_CRC1_WINDOWA_Y_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_CRC1_WINDOWB_X_CONTROL[] = { + { "OTG_CRC1_WINDOWB_X_START", 0, 14, &umr_bitfield_default }, + { "OTG_CRC1_WINDOWB_X_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_CRC1_WINDOWB_Y_CONTROL[] = { + { "OTG_CRC1_WINDOWB_Y_START", 0, 14, &umr_bitfield_default }, + { "OTG_CRC1_WINDOWB_Y_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_CRC1_DATA_RG[] = { + { "CRC1_R_CR", 0, 15, &umr_bitfield_default }, + { "CRC1_G_Y", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_CRC1_DATA_B[] = { + { "CRC1_B_CB", 0, 15, &umr_bitfield_default }, + { "CRC1_C", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_CRC2_DATA_RG[] = { + { "CRC2_R_CR", 0, 15, &umr_bitfield_default }, + { "CRC2_G_Y", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_CRC2_DATA_B[] = { + { "CRC2_B_CB", 0, 15, &umr_bitfield_default }, + { "CRC2_C", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_CRC3_DATA_RG[] = { + { "CRC3_R_CR", 0, 15, &umr_bitfield_default }, + { "CRC3_G_Y", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_CRC3_DATA_B[] = { + { "CRC3_B_CB", 0, 15, &umr_bitfield_default }, + { "CRC3_C", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_CRC_SIG_RED_GREEN_MASK[] = { + { "OTG_CRC_SIG_RED_MASK", 0, 15, &umr_bitfield_default }, + { "OTG_CRC_SIG_GREEN_MASK", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK[] = { + { "OTG_CRC_SIG_BLUE_MASK", 0, 15, &umr_bitfield_default }, + { "OTG_CRC_SIG_CONTROL_MASK", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_STATIC_SCREEN_CONTROL[] = { + { "OTG_STATIC_SCREEN_EVENT_MASK", 0, 15, &umr_bitfield_default }, + { "OTG_STATIC_SCREEN_FRAME_COUNT", 16, 23, &umr_bitfield_default }, + { "OTG_CPU_SS_INT_ENABLE", 24, 24, &umr_bitfield_default }, + { "OTG_SS_STATUS", 25, 25, &umr_bitfield_default }, + { "OTG_CPU_SS_INT_STATUS", 26, 26, &umr_bitfield_default }, + { "OTG_CPU_SS_INT_CLEAR", 27, 27, &umr_bitfield_default }, + { "OTG_CPU_SS_INT_TYPE", 28, 28, &umr_bitfield_default }, + { "OTG_STATIC_SCREEN_OVERRIDE", 30, 30, &umr_bitfield_default }, + { "OTG_STATIC_SCREEN_OVERRIDE_VALUE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_3D_STRUCTURE_CONTROL[] = { + { "OTG_3D_STRUCTURE_EN", 0, 0, &umr_bitfield_default }, + { "OTG_3D_STRUCTURE_V_UPDATE_MODE", 8, 9, &umr_bitfield_default }, + { "OTG_3D_STRUCTURE_STEREO_SEL_OVR", 12, 12, &umr_bitfield_default }, + { "OTG_3D_STRUCTURE_F_COUNT_RESET", 16, 16, &umr_bitfield_default }, + { "OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING", 17, 17, &umr_bitfield_default }, + { "OTG_3D_STRUCTURE_F_COUNT", 18, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_GSL_VSYNC_GAP[] = { + { "OTG_GSL_VSYNC_GAP_LIMIT", 0, 7, &umr_bitfield_default }, + { "OTG_GSL_VSYNC_GAP_DELAY", 8, 15, &umr_bitfield_default }, + { "OTG_GSL_VSYNC_GAP_SOURCE_SEL", 16, 16, &umr_bitfield_default }, + { "OTG_GSL_VSYNC_GAP_MODE", 17, 18, &umr_bitfield_default }, + { "OTG_GSL_VSYNC_GAP_CLEAR", 19, 19, &umr_bitfield_default }, + { "OTG_GSL_VSYNC_GAP_OCCURRED", 20, 20, &umr_bitfield_default }, + { "OTG_GSL_VSYNC_GAP_MASTER_FASTER", 23, 23, &umr_bitfield_default }, + { "OTG_GSL_VSYNC_GAP", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_MASTER_UPDATE_MODE[] = { + { "MASTER_UPDATE_INTERLACED_MODE", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_CLOCK_CONTROL[] = { + { "OTG_CLOCK_EN", 0, 0, &umr_bitfield_default }, + { "OTG_CLOCK_GATE_DIS", 1, 1, &umr_bitfield_default }, + { "OTG_SOFT_RESET", 4, 4, &umr_bitfield_default }, + { "OTG_CLOCK_ON", 8, 8, &umr_bitfield_default }, + { "OTG_BUSY", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_VSTARTUP_PARAM[] = { + { "VSTARTUP_START", 0, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_VUPDATE_PARAM[] = { + { "VUPDATE_OFFSET", 0, 15, &umr_bitfield_default }, + { "VUPDATE_WIDTH", 16, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_VREADY_PARAM[] = { + { "VREADY_OFFSET", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_GLOBAL_SYNC_STATUS[] = { + { "VSTARTUP_INT_EN", 0, 0, &umr_bitfield_default }, + { "VSTARTUP_INT_TYPE", 1, 1, &umr_bitfield_default }, + { "VSTARTUP_EVENT_OCCURRED", 2, 2, &umr_bitfield_default }, + { "VSTARTUP_INT_STATUS", 3, 3, &umr_bitfield_default }, + { "VSTARTUP_EVENT_CLEAR", 4, 4, &umr_bitfield_default }, + { "VUPDATE_INT_EN", 5, 5, &umr_bitfield_default }, + { "VUPDATE_INT_TYPE", 6, 6, &umr_bitfield_default }, + { "VUPDATE_INT_POSITION_SEL", 7, 7, &umr_bitfield_default }, + { "VUPDATE_EVENT_OCCURRED", 8, 8, &umr_bitfield_default }, + { "VUPDATE_INT_STATUS", 9, 9, &umr_bitfield_default }, + { "VUPDATE_EVENT_CLEAR", 10, 10, &umr_bitfield_default }, + { "VUPDATE_STATUS", 11, 11, &umr_bitfield_default }, + { "VUPDATE_NO_LOCK_INT_EN", 12, 12, &umr_bitfield_default }, + { "VUPDATE_NO_LOCK_INT_TYPE", 13, 13, &umr_bitfield_default }, + { "VUPDATE_NO_LOCK_EVENT_OCCURRED", 14, 14, &umr_bitfield_default }, + { "VUPDATE_NO_LOCK_INT_STATUS", 15, 15, &umr_bitfield_default }, + { "VUPDATE_NO_LOCK_EVENT_CLEAR", 16, 16, &umr_bitfield_default }, + { "VUPDATE_NO_LOCK_STATUS", 17, 17, &umr_bitfield_default }, + { "VREADY_INT_EN", 18, 18, &umr_bitfield_default }, + { "VREADY_INT_TYPE", 19, 19, &umr_bitfield_default }, + { "VREADY_EVENT_OCCURRED", 20, 20, &umr_bitfield_default }, + { "VREADY_INT_STATUS", 21, 21, &umr_bitfield_default }, + { "VREADY_EVENT_CLEAR", 22, 22, &umr_bitfield_default }, + { "STEREO_SELECT_STATUS", 24, 24, &umr_bitfield_default }, + { "FIELD_NUMBER_STATUS", 25, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_MASTER_UPDATE_LOCK[] = { + { "OTG_MASTER_UPDATE_LOCK", 0, 0, &umr_bitfield_default }, + { "UPDATE_LOCK_STATUS", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_GSL_CONTROL[] = { + { "OTG_GSL0_EN", 0, 0, &umr_bitfield_default }, + { "OTG_GSL1_EN", 1, 1, &umr_bitfield_default }, + { "OTG_GSL2_EN", 2, 2, &umr_bitfield_default }, + { "OTG_GSL_MASTER_EN", 3, 3, &umr_bitfield_default }, + { "OTG_GSL_FORCE_DELAY", 16, 20, &umr_bitfield_default }, + { "OTG_GSL_CHECK_ALL_FIELDS", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_GSL_WINDOW_X[] = { + { "OTG_GSL_WINDOW_START_X", 0, 14, &umr_bitfield_default }, + { "OTG_GSL_WINDOW_END_X", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_GSL_WINDOW_Y[] = { + { "OTG_GSL_WINDOW_START_Y", 0, 14, &umr_bitfield_default }, + { "OTG_GSL_WINDOW_END_Y", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_VUPDATE_KEEPOUT[] = { + { "MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET", 0, 15, &umr_bitfield_default }, + { "MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET", 16, 25, &umr_bitfield_default }, + { "OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_GLOBAL_CONTROL0[] = { + { "OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT", 0, 7, &umr_bitfield_default }, + { "OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN", 8, 8, &umr_bitfield_default }, + { "OTG_MASTER_UPDATE_LOCK_SEL", 25, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_GLOBAL_CONTROL1[] = { + { "MASTER_UPDATE_LOCK_DB_X", 0, 14, &umr_bitfield_default }, + { "MASTER_UPDATE_LOCK_DB_Y", 16, 30, &umr_bitfield_default }, + { "MASTER_UPDATE_LOCK_DB_EN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_GLOBAL_CONTROL2[] = { + { "DIG_UPDATE_LOCATION", 0, 9, &umr_bitfield_default }, + { "GLOBAL_UPDATE_LOCK_EN", 10, 10, &umr_bitfield_default }, + { "MANUAL_FLOW_CONTROL_SEL", 16, 18, &umr_bitfield_default }, + { "DCCG_VUPDATE_MODE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_GLOBAL_CONTROL3[] = { + { "MASTER_UPDATE_LOCK_DB_FIELD", 0, 1, &umr_bitfield_default }, + { "MASTER_UPDATE_LOCK_DB_STEREO_SEL", 4, 5, &umr_bitfield_default }, + { "MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_TRIG_MANUAL_CONTROL[] = { + { "TRIG_MANUAL_CONTROL", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_MANUAL_FLOW_CONTROL[] = { + { "MANUAL_FLOW_CONTROL", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_RANGE_TIMING_INT_STATUS[] = { + { "OTG_RANGE_TIMING_UPDATE_OCCURRED", 0, 0, &umr_bitfield_default }, + { "OTG_RANGE_TIMING_UPDATE_OCCURRED_INT", 4, 4, &umr_bitfield_default }, + { "OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR", 8, 8, &umr_bitfield_default }, + { "OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK", 12, 12, &umr_bitfield_default }, + { "OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_DRR_CONTROL[] = { + { "OTG_DRR_AVERAGE_FRAME", 0, 2, &umr_bitfield_default }, + { "OTG_V_TOTAL_LAST_USED_BY_DRR", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_REQUEST_CONTROL[] = { + { "OTG_REQUEST_MODE_FOR_H_DUPLICATE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG0_OTG_SPARE_REGISTER[] = { + { "OTG_SPARE_REG", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_H_TOTAL[] = { + { "OTG_H_TOTAL", 0, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_H_BLANK_START_END[] = { + { "OTG_H_BLANK_START", 0, 14, &umr_bitfield_default }, + { "OTG_H_BLANK_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_H_SYNC_A[] = { + { "OTG_H_SYNC_A_START", 0, 14, &umr_bitfield_default }, + { "OTG_H_SYNC_A_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_H_SYNC_A_CNTL[] = { + { "OTG_H_SYNC_A_POL", 0, 0, &umr_bitfield_default }, + { "OTG_COMP_SYNC_A_EN", 16, 16, &umr_bitfield_default }, + { "OTG_H_SYNC_A_CUTOFF", 17, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_H_TIMING_CNTL[] = { + { "OTG_H_TIMING_DIV_BY2", 0, 0, &umr_bitfield_default }, + { "OTG_H_TIMING_DIV_BY2_UPDATE_MODE", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_V_TOTAL[] = { + { "OTG_V_TOTAL", 0, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_V_TOTAL_MIN[] = { + { "OTG_V_TOTAL_MIN", 0, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_V_TOTAL_MAX[] = { + { "OTG_V_TOTAL_MAX", 0, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_V_TOTAL_MID[] = { + { "OTG_V_TOTAL_MID", 0, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_V_TOTAL_CONTROL[] = { + { "OTG_V_TOTAL_MIN_SEL", 0, 0, &umr_bitfield_default }, + { "OTG_V_TOTAL_MAX_SEL", 1, 1, &umr_bitfield_default }, + { "OTG_VTOTAL_MID_REPLACING_MAX_EN", 2, 2, &umr_bitfield_default }, + { "OTG_VTOTAL_MID_REPLACING_MIN_EN", 3, 3, &umr_bitfield_default }, + { "OTG_FORCE_LOCK_ON_EVENT", 4, 4, &umr_bitfield_default }, + { "OTG_SET_V_TOTAL_MIN_MASK_EN", 7, 7, &umr_bitfield_default }, + { "OTG_VTOTAL_MID_FRAME_NUM", 8, 15, &umr_bitfield_default }, + { "OTG_SET_V_TOTAL_MIN_MASK", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_V_TOTAL_INT_STATUS[] = { + { "OTG_SET_V_TOTAL_MIN_EVENT_OCCURED", 0, 0, &umr_bitfield_default }, + { "OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_INT", 4, 4, &umr_bitfield_default }, + { "OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK", 8, 8, &umr_bitfield_default }, + { "OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK", 12, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_VSYNC_NOM_INT_STATUS[] = { + { "OTG_VSYNC_NOM", 0, 0, &umr_bitfield_default }, + { "OTG_VSYNC_NOM_INT_CLEAR", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_V_BLANK_START_END[] = { + { "OTG_V_BLANK_START", 0, 14, &umr_bitfield_default }, + { "OTG_V_BLANK_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_V_SYNC_A[] = { + { "OTG_V_SYNC_A_START", 0, 14, &umr_bitfield_default }, + { "OTG_V_SYNC_A_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_V_SYNC_A_CNTL[] = { + { "OTG_V_SYNC_A_POL", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_TRIGA_CNTL[] = { + { "OTG_TRIGA_SOURCE_SELECT", 0, 4, &umr_bitfield_default }, + { "OTG_TRIGA_SOURCE_PIPE_SELECT", 5, 7, &umr_bitfield_default }, + { "OTG_TRIGA_POLARITY_SELECT", 8, 10, &umr_bitfield_default }, + { "OTG_TRIGA_RESYNC_BYPASS_EN", 11, 11, &umr_bitfield_default }, + { "OTG_TRIGA_INPUT_STATUS", 12, 12, &umr_bitfield_default }, + { "OTG_TRIGA_POLARITY_STATUS", 13, 13, &umr_bitfield_default }, + { "OTG_TRIGA_OCCURRED", 14, 14, &umr_bitfield_default }, + { "OTG_TRIGA_RISING_EDGE_DETECT_CNTL", 16, 17, &umr_bitfield_default }, + { "OTG_TRIGA_FALLING_EDGE_DETECT_CNTL", 18, 19, &umr_bitfield_default }, + { "OTG_TRIGA_FREQUENCY_SELECT", 20, 21, &umr_bitfield_default }, + { "OTG_TRIGA_DELAY", 24, 28, &umr_bitfield_default }, + { "OTG_TRIGA_CLEAR", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_TRIGA_MANUAL_TRIG[] = { + { "OTG_TRIGA_MANUAL_TRIG", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_TRIGB_CNTL[] = { + { "OTG_TRIGB_SOURCE_SELECT", 0, 4, &umr_bitfield_default }, + { "OTG_TRIGB_SOURCE_PIPE_SELECT", 5, 7, &umr_bitfield_default }, + { "OTG_TRIGB_POLARITY_SELECT", 8, 10, &umr_bitfield_default }, + { "OTG_TRIGB_RESYNC_BYPASS_EN", 11, 11, &umr_bitfield_default }, + { "OTG_TRIGB_INPUT_STATUS", 12, 12, &umr_bitfield_default }, + { "OTG_TRIGB_POLARITY_STATUS", 13, 13, &umr_bitfield_default }, + { "OTG_TRIGB_OCCURRED", 14, 14, &umr_bitfield_default }, + { "OTG_TRIGB_RISING_EDGE_DETECT_CNTL", 16, 17, &umr_bitfield_default }, + { "OTG_TRIGB_FALLING_EDGE_DETECT_CNTL", 18, 19, &umr_bitfield_default }, + { "OTG_TRIGB_FREQUENCY_SELECT", 20, 21, &umr_bitfield_default }, + { "OTG_TRIGB_DELAY", 24, 28, &umr_bitfield_default }, + { "OTG_TRIGB_CLEAR", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_TRIGB_MANUAL_TRIG[] = { + { "OTG_TRIGB_MANUAL_TRIG", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_FORCE_COUNT_NOW_CNTL[] = { + { "OTG_FORCE_COUNT_NOW_MODE", 0, 1, &umr_bitfield_default }, + { "OTG_FORCE_COUNT_NOW_CHECK", 4, 4, &umr_bitfield_default }, + { "OTG_FORCE_COUNT_NOW_TRIG_SEL", 8, 8, &umr_bitfield_default }, + { "OTG_FORCE_COUNT_NOW_OCCURRED", 16, 16, &umr_bitfield_default }, + { "OTG_FORCE_COUNT_NOW_CLEAR", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_FLOW_CONTROL[] = { + { "OTG_FLOW_CONTROL_SOURCE_SELECT", 0, 4, &umr_bitfield_default }, + { "OTG_FLOW_CONTROL_POLARITY", 8, 8, &umr_bitfield_default }, + { "OTG_FLOW_CONTROL_GRANULARITY", 16, 16, &umr_bitfield_default }, + { "OTG_FLOW_CONTROL_INPUT_STATUS", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_STEREO_FORCE_NEXT_EYE[] = { + { "OTG_STEREO_FORCE_NEXT_EYE", 0, 1, &umr_bitfield_default }, + { "OTG_AVSYNC_FRAME_COUNTER", 8, 15, &umr_bitfield_default }, + { "OTG_AVSYNC_LINE_COUNTER", 16, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_AVSYNC_COUNTER[] = { + { "OTG_AVSYNC_COUNTER", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_CONTROL[] = { + { "OTG_MASTER_EN", 0, 0, &umr_bitfield_default }, + { "OTG_DISABLE_POINT_CNTL", 8, 9, &umr_bitfield_default }, + { "OTG_START_POINT_CNTL", 12, 12, &umr_bitfield_default }, + { "OTG_FIELD_NUMBER_CNTL", 13, 13, &umr_bitfield_default }, + { "OTG_FIELD_NUMBER_POLARITY", 14, 14, &umr_bitfield_default }, + { "OTG_CURRENT_MASTER_EN_STATE", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_BLANK_CONTROL[] = { + { "OTG_CURRENT_BLANK_STATE", 0, 0, &umr_bitfield_default }, + { "OTG_BLANK_DATA_EN", 8, 8, &umr_bitfield_default }, + { "OTG_BLANK_DE_MODE", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_PIPE_ABORT_CONTROL[] = { + { "OTG_PIPE_ABORT", 0, 0, &umr_bitfield_default }, + { "OTG_PIPE_ABORT_DONE", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_INTERLACE_CONTROL[] = { + { "OTG_INTERLACE_ENABLE", 0, 0, &umr_bitfield_default }, + { "OTG_INTERLACE_FORCE_NEXT_FIELD", 16, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_INTERLACE_STATUS[] = { + { "OTG_INTERLACE_CURRENT_FIELD", 0, 0, &umr_bitfield_default }, + { "OTG_INTERLACE_NEXT_FIELD", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_FIELD_INDICATION_CONTROL[] = { + { "OTG_FIELD_INDICATION_OUTPUT_POLARITY", 0, 0, &umr_bitfield_default }, + { "OTG_FIELD_ALIGNMENT", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_PIXEL_DATA_READBACK0[] = { + { "OTG_PIXEL_DATA_BLUE_CB", 0, 15, &umr_bitfield_default }, + { "OTG_PIXEL_DATA_GREEN_Y", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_PIXEL_DATA_READBACK1[] = { + { "OTG_PIXEL_DATA_RED_CR", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_STATUS[] = { + { "OTG_V_BLANK", 0, 0, &umr_bitfield_default }, + { "OTG_V_ACTIVE_DISP", 1, 1, &umr_bitfield_default }, + { "OTG_V_SYNC_A", 2, 2, &umr_bitfield_default }, + { "OTG_V_UPDATE", 3, 3, &umr_bitfield_default }, + { "OTG_V_BLANK_3D_STRUCTURE", 5, 5, &umr_bitfield_default }, + { "OTG_H_BLANK", 16, 16, &umr_bitfield_default }, + { "OTG_H_ACTIVE_DISP", 17, 17, &umr_bitfield_default }, + { "OTG_H_SYNC_A", 18, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_STATUS_POSITION[] = { + { "OTG_VERT_COUNT", 0, 14, &umr_bitfield_default }, + { "OTG_HORZ_COUNT", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_NOM_VERT_POSITION[] = { + { "OTG_VERT_COUNT_NOM", 0, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_STATUS_FRAME_COUNT[] = { + { "OTG_FRAME_COUNT", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_STATUS_VF_COUNT[] = { + { "OTG_VF_COUNT", 0, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_STATUS_HV_COUNT[] = { + { "OTG_HV_COUNT", 0, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_COUNT_CONTROL[] = { + { "OTG_HORZ_COUNT_BY2_EN", 0, 0, &umr_bitfield_default }, + { "OTG_HORZ_REPETITION_COUNT", 1, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_COUNT_RESET[] = { + { "OTG_RESET_FRAME_COUNT", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE[] = { + { "OTG_MANUAL_FORCE_VSYNC_NEXT_LINE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_VERT_SYNC_CONTROL[] = { + { "OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED", 0, 0, &umr_bitfield_default }, + { "OTG_FORCE_VSYNC_NEXT_LINE_CLEAR", 8, 8, &umr_bitfield_default }, + { "OTG_AUTO_FORCE_VSYNC_MODE", 16, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_STEREO_STATUS[] = { + { "OTG_STEREO_CURRENT_EYE", 0, 0, &umr_bitfield_default }, + { "OTG_STEREO_SYNC_OUTPUT", 8, 8, &umr_bitfield_default }, + { "OTG_STEREO_SYNC_SELECT", 16, 16, &umr_bitfield_default }, + { "OTG_STEREO_EYE_FLAG", 20, 20, &umr_bitfield_default }, + { "OTG_STEREO_FORCE_NEXT_EYE_PENDING", 24, 25, &umr_bitfield_default }, + { "OTG_CURRENT_3D_STRUCTURE_STATE", 30, 30, &umr_bitfield_default }, + { "OTG_CURRENT_STEREOSYNC_EN_STATE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_STEREO_CONTROL[] = { + { "OTG_STEREO_SYNC_OUTPUT_LINE_NUM", 0, 14, &umr_bitfield_default }, + { "OTG_STEREO_SYNC_OUTPUT_POLARITY", 15, 15, &umr_bitfield_default }, + { "OTG_STEREO_EYE_FLAG_POLARITY", 17, 17, &umr_bitfield_default }, + { "OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP", 18, 18, &umr_bitfield_default }, + { "OTG_DISABLE_FIELD_NUM", 19, 19, &umr_bitfield_default }, + { "OTG_DISABLE_V_BLANK_FOR_DP_FIX", 20, 20, &umr_bitfield_default }, + { "OTG_STEREO_EN", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_SNAPSHOT_STATUS[] = { + { "OTG_SNAPSHOT_OCCURRED", 0, 0, &umr_bitfield_default }, + { "OTG_SNAPSHOT_CLEAR", 1, 1, &umr_bitfield_default }, + { "OTG_SNAPSHOT_MANUAL_TRIGGER", 2, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_SNAPSHOT_CONTROL[] = { + { "OTG_AUTO_SNAPSHOT_TRIG_SEL", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_SNAPSHOT_POSITION[] = { + { "OTG_SNAPSHOT_VERT_COUNT", 0, 14, &umr_bitfield_default }, + { "OTG_SNAPSHOT_HORZ_COUNT", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_SNAPSHOT_FRAME[] = { + { "OTG_SNAPSHOT_FRAME_COUNT", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_INTERRUPT_CONTROL[] = { + { "OTG_SNAPSHOT_INT_MSK", 0, 0, &umr_bitfield_default }, + { "OTG_SNAPSHOT_INT_TYPE", 1, 1, &umr_bitfield_default }, + { "OTG_FORCE_COUNT_NOW_INT_MSK", 8, 8, &umr_bitfield_default }, + { "OTG_FORCE_COUNT_NOW_INT_TYPE", 9, 9, &umr_bitfield_default }, + { "OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK", 16, 16, &umr_bitfield_default }, + { "OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE", 17, 17, &umr_bitfield_default }, + { "OTG_TRIGA_INT_MSK", 24, 24, &umr_bitfield_default }, + { "OTG_TRIGB_INT_MSK", 25, 25, &umr_bitfield_default }, + { "OTG_TRIGA_INT_TYPE", 26, 26, &umr_bitfield_default }, + { "OTG_TRIGB_INT_TYPE", 27, 27, &umr_bitfield_default }, + { "OTG_VSYNC_NOM_INT_MSK", 28, 28, &umr_bitfield_default }, + { "OTG_VSYNC_NOM_INT_TYPE", 29, 29, &umr_bitfield_default }, + { "OTG_GSL_VSYNC_GAP_INT_MSK", 30, 30, &umr_bitfield_default }, + { "OTG_GSL_VSYNC_GAP_INT_TYPE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_UPDATE_LOCK[] = { + { "OTG_UPDATE_LOCK", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_DOUBLE_BUFFER_CONTROL[] = { + { "OTG_UPDATE_PENDING", 0, 0, &umr_bitfield_default }, + { "OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING", 2, 2, &umr_bitfield_default }, + { "OTG_BLANK_DATA_EN_UPDATE_PENDING", 3, 3, &umr_bitfield_default }, + { "OTG_RANGE_TIMING_DBUF_UPDATE_PENDING", 4, 4, &umr_bitfield_default }, + { "OTG_TIMING_DB_UPDATE_PENDING", 5, 5, &umr_bitfield_default }, + { "OTG_3D_CTRL_DB_UPDATE_PENDING", 6, 6, &umr_bitfield_default }, + { "OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING", 7, 7, &umr_bitfield_default }, + { "OTG_UPDATE_INSTANTLY", 8, 8, &umr_bitfield_default }, + { "OTG_BLANK_DATA_DOUBLE_BUFFER_EN", 16, 16, &umr_bitfield_default }, + { "OTG_RANGE_TIMING_DBUF_UPDATE_MODE", 24, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_TEST_PATTERN_CONTROL[] = { + { "OTG_TEST_PATTERN_EN", 0, 0, &umr_bitfield_default }, + { "OTG_TEST_PATTERN_MODE", 8, 10, &umr_bitfield_default }, + { "OTG_TEST_PATTERN_DYNAMIC_RANGE", 16, 16, &umr_bitfield_default }, + { "OTG_TEST_PATTERN_COLOR_FORMAT", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_TEST_PATTERN_PARAMETERS[] = { + { "OTG_TEST_PATTERN_INC0", 0, 3, &umr_bitfield_default }, + { "OTG_TEST_PATTERN_INC1", 4, 7, &umr_bitfield_default }, + { "OTG_TEST_PATTERN_VRES", 8, 11, &umr_bitfield_default }, + { "OTG_TEST_PATTERN_HRES", 12, 15, &umr_bitfield_default }, + { "OTG_TEST_PATTERN_RAMP0_OFFSET", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_TEST_PATTERN_COLOR[] = { + { "OTG_TEST_PATTERN_DATA", 0, 15, &umr_bitfield_default }, + { "OTG_TEST_PATTERN_MASK", 16, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_MASTER_EN[] = { + { "OTG_MASTER_EN", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_BLANK_DATA_COLOR[] = { + { "OTG_BLANK_DATA_COLOR_BLUE_CB", 0, 9, &umr_bitfield_default }, + { "OTG_BLANK_DATA_COLOR_GREEN_Y", 10, 19, &umr_bitfield_default }, + { "OTG_BLANK_DATA_COLOR_RED_CR", 20, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_BLANK_DATA_COLOR_EXT[] = { + { "OTG_BLANK_DATA_COLOR_BLUE_CB_EXT", 0, 5, &umr_bitfield_default }, + { "OTG_BLANK_DATA_COLOR_GREEN_Y_EXT", 8, 13, &umr_bitfield_default }, + { "OTG_BLANK_DATA_COLOR_RED_CR_EXT", 16, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_BLACK_COLOR[] = { + { "OTG_BLACK_COLOR_B_CB", 0, 9, &umr_bitfield_default }, + { "OTG_BLACK_COLOR_G_Y", 10, 19, &umr_bitfield_default }, + { "OTG_BLACK_COLOR_R_CR", 20, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_BLACK_COLOR_EXT[] = { + { "OTG_BLACK_COLOR_B_CB_EXT", 0, 5, &umr_bitfield_default }, + { "OTG_BLACK_COLOR_G_Y_EXT", 8, 13, &umr_bitfield_default }, + { "OTG_BLACK_COLOR_R_CR_EXT", 16, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_VERTICAL_INTERRUPT0_POSITION[] = { + { "OTG_VERTICAL_INTERRUPT0_LINE_START", 0, 14, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT0_LINE_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL[] = { + { "OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY", 4, 4, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT0_INT_ENABLE", 8, 8, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT0_STATUS", 12, 12, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT0_INT_STATUS", 16, 16, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT0_CLEAR", 20, 20, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT0_INT_TYPE", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_VERTICAL_INTERRUPT1_POSITION[] = { + { "OTG_VERTICAL_INTERRUPT1_LINE_START", 0, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL[] = { + { "OTG_VERTICAL_INTERRUPT1_INT_ENABLE", 8, 8, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT1_STATUS", 12, 12, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT1_INT_STATUS", 16, 16, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT1_CLEAR", 20, 20, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT1_INT_TYPE", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_VERTICAL_INTERRUPT2_POSITION[] = { + { "OTG_VERTICAL_INTERRUPT2_LINE_START", 0, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL[] = { + { "OTG_VERTICAL_INTERRUPT2_INT_ENABLE", 8, 8, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT2_STATUS", 12, 12, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT2_INT_STATUS", 16, 16, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT2_CLEAR", 20, 20, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT2_INT_TYPE", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_CRC_CNTL[] = { + { "OTG_CRC_EN", 0, 0, &umr_bitfield_default }, + { "OTG_CRC_DUAL_LINK_EN", 1, 1, &umr_bitfield_default }, + { "OTG_CRC_DUAL_LINK_MODE", 2, 2, &umr_bitfield_default }, + { "OTG_CRC_BLANK_ONLY", 3, 3, &umr_bitfield_default }, + { "OTG_CRC_CONT_EN", 4, 4, &umr_bitfield_default }, + { "OTG_CRC_CAPTURE_START_SEL", 5, 6, &umr_bitfield_default }, + { "OTG_CRC_STEREO_MODE", 8, 9, &umr_bitfield_default }, + { "OTG_CRC_INTERLACE_MODE", 12, 13, &umr_bitfield_default }, + { "OTG_CRC_MULTI_STREAM_MODE", 16, 18, &umr_bitfield_default }, + { "OTG_CRC_USE_NEW_AND_REPEATED_PIXELS", 19, 19, &umr_bitfield_default }, + { "OTG_CRC0_SELECT", 20, 22, &umr_bitfield_default }, + { "OTG_CRC1_SELECT", 24, 26, &umr_bitfield_default }, + { "OTG_ONE_SHOT_CRC0_PENDING", 28, 28, &umr_bitfield_default }, + { "OTG_ONE_SHOT_CRC1_PENDING", 29, 29, &umr_bitfield_default }, + { "OTG_ONE_SHOT_CRC2_PENDING", 30, 30, &umr_bitfield_default }, + { "OTG_ONE_SHOT_CRC3_PENDING", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_CRC0_WINDOWA_X_CONTROL[] = { + { "OTG_CRC0_WINDOWA_X_START", 0, 14, &umr_bitfield_default }, + { "OTG_CRC0_WINDOWA_X_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_CRC0_WINDOWA_Y_CONTROL[] = { + { "OTG_CRC0_WINDOWA_Y_START", 0, 14, &umr_bitfield_default }, + { "OTG_CRC0_WINDOWA_Y_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_CRC0_WINDOWB_X_CONTROL[] = { + { "OTG_CRC0_WINDOWB_X_START", 0, 14, &umr_bitfield_default }, + { "OTG_CRC0_WINDOWB_X_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_CRC0_WINDOWB_Y_CONTROL[] = { + { "OTG_CRC0_WINDOWB_Y_START", 0, 14, &umr_bitfield_default }, + { "OTG_CRC0_WINDOWB_Y_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_CRC0_DATA_RG[] = { + { "CRC0_R_CR", 0, 15, &umr_bitfield_default }, + { "CRC0_G_Y", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_CRC0_DATA_B[] = { + { "CRC0_B_CB", 0, 15, &umr_bitfield_default }, + { "CRC0_C", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_CRC1_WINDOWA_X_CONTROL[] = { + { "OTG_CRC1_WINDOWA_X_START", 0, 14, &umr_bitfield_default }, + { "OTG_CRC1_WINDOWA_X_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_CRC1_WINDOWA_Y_CONTROL[] = { + { "OTG_CRC1_WINDOWA_Y_START", 0, 14, &umr_bitfield_default }, + { "OTG_CRC1_WINDOWA_Y_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_CRC1_WINDOWB_X_CONTROL[] = { + { "OTG_CRC1_WINDOWB_X_START", 0, 14, &umr_bitfield_default }, + { "OTG_CRC1_WINDOWB_X_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_CRC1_WINDOWB_Y_CONTROL[] = { + { "OTG_CRC1_WINDOWB_Y_START", 0, 14, &umr_bitfield_default }, + { "OTG_CRC1_WINDOWB_Y_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_CRC1_DATA_RG[] = { + { "CRC1_R_CR", 0, 15, &umr_bitfield_default }, + { "CRC1_G_Y", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_CRC1_DATA_B[] = { + { "CRC1_B_CB", 0, 15, &umr_bitfield_default }, + { "CRC1_C", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_CRC2_DATA_RG[] = { + { "CRC2_R_CR", 0, 15, &umr_bitfield_default }, + { "CRC2_G_Y", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_CRC2_DATA_B[] = { + { "CRC2_B_CB", 0, 15, &umr_bitfield_default }, + { "CRC2_C", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_CRC3_DATA_RG[] = { + { "CRC3_R_CR", 0, 15, &umr_bitfield_default }, + { "CRC3_G_Y", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_CRC3_DATA_B[] = { + { "CRC3_B_CB", 0, 15, &umr_bitfield_default }, + { "CRC3_C", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_CRC_SIG_RED_GREEN_MASK[] = { + { "OTG_CRC_SIG_RED_MASK", 0, 15, &umr_bitfield_default }, + { "OTG_CRC_SIG_GREEN_MASK", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK[] = { + { "OTG_CRC_SIG_BLUE_MASK", 0, 15, &umr_bitfield_default }, + { "OTG_CRC_SIG_CONTROL_MASK", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_STATIC_SCREEN_CONTROL[] = { + { "OTG_STATIC_SCREEN_EVENT_MASK", 0, 15, &umr_bitfield_default }, + { "OTG_STATIC_SCREEN_FRAME_COUNT", 16, 23, &umr_bitfield_default }, + { "OTG_CPU_SS_INT_ENABLE", 24, 24, &umr_bitfield_default }, + { "OTG_SS_STATUS", 25, 25, &umr_bitfield_default }, + { "OTG_CPU_SS_INT_STATUS", 26, 26, &umr_bitfield_default }, + { "OTG_CPU_SS_INT_CLEAR", 27, 27, &umr_bitfield_default }, + { "OTG_CPU_SS_INT_TYPE", 28, 28, &umr_bitfield_default }, + { "OTG_STATIC_SCREEN_OVERRIDE", 30, 30, &umr_bitfield_default }, + { "OTG_STATIC_SCREEN_OVERRIDE_VALUE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_3D_STRUCTURE_CONTROL[] = { + { "OTG_3D_STRUCTURE_EN", 0, 0, &umr_bitfield_default }, + { "OTG_3D_STRUCTURE_V_UPDATE_MODE", 8, 9, &umr_bitfield_default }, + { "OTG_3D_STRUCTURE_STEREO_SEL_OVR", 12, 12, &umr_bitfield_default }, + { "OTG_3D_STRUCTURE_F_COUNT_RESET", 16, 16, &umr_bitfield_default }, + { "OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING", 17, 17, &umr_bitfield_default }, + { "OTG_3D_STRUCTURE_F_COUNT", 18, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_GSL_VSYNC_GAP[] = { + { "OTG_GSL_VSYNC_GAP_LIMIT", 0, 7, &umr_bitfield_default }, + { "OTG_GSL_VSYNC_GAP_DELAY", 8, 15, &umr_bitfield_default }, + { "OTG_GSL_VSYNC_GAP_SOURCE_SEL", 16, 16, &umr_bitfield_default }, + { "OTG_GSL_VSYNC_GAP_MODE", 17, 18, &umr_bitfield_default }, + { "OTG_GSL_VSYNC_GAP_CLEAR", 19, 19, &umr_bitfield_default }, + { "OTG_GSL_VSYNC_GAP_OCCURRED", 20, 20, &umr_bitfield_default }, + { "OTG_GSL_VSYNC_GAP_MASTER_FASTER", 23, 23, &umr_bitfield_default }, + { "OTG_GSL_VSYNC_GAP", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_MASTER_UPDATE_MODE[] = { + { "MASTER_UPDATE_INTERLACED_MODE", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_CLOCK_CONTROL[] = { + { "OTG_CLOCK_EN", 0, 0, &umr_bitfield_default }, + { "OTG_CLOCK_GATE_DIS", 1, 1, &umr_bitfield_default }, + { "OTG_SOFT_RESET", 4, 4, &umr_bitfield_default }, + { "OTG_CLOCK_ON", 8, 8, &umr_bitfield_default }, + { "OTG_BUSY", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_VSTARTUP_PARAM[] = { + { "VSTARTUP_START", 0, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_VUPDATE_PARAM[] = { + { "VUPDATE_OFFSET", 0, 15, &umr_bitfield_default }, + { "VUPDATE_WIDTH", 16, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_VREADY_PARAM[] = { + { "VREADY_OFFSET", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_GLOBAL_SYNC_STATUS[] = { + { "VSTARTUP_INT_EN", 0, 0, &umr_bitfield_default }, + { "VSTARTUP_INT_TYPE", 1, 1, &umr_bitfield_default }, + { "VSTARTUP_EVENT_OCCURRED", 2, 2, &umr_bitfield_default }, + { "VSTARTUP_INT_STATUS", 3, 3, &umr_bitfield_default }, + { "VSTARTUP_EVENT_CLEAR", 4, 4, &umr_bitfield_default }, + { "VUPDATE_INT_EN", 5, 5, &umr_bitfield_default }, + { "VUPDATE_INT_TYPE", 6, 6, &umr_bitfield_default }, + { "VUPDATE_INT_POSITION_SEL", 7, 7, &umr_bitfield_default }, + { "VUPDATE_EVENT_OCCURRED", 8, 8, &umr_bitfield_default }, + { "VUPDATE_INT_STATUS", 9, 9, &umr_bitfield_default }, + { "VUPDATE_EVENT_CLEAR", 10, 10, &umr_bitfield_default }, + { "VUPDATE_STATUS", 11, 11, &umr_bitfield_default }, + { "VUPDATE_NO_LOCK_INT_EN", 12, 12, &umr_bitfield_default }, + { "VUPDATE_NO_LOCK_INT_TYPE", 13, 13, &umr_bitfield_default }, + { "VUPDATE_NO_LOCK_EVENT_OCCURRED", 14, 14, &umr_bitfield_default }, + { "VUPDATE_NO_LOCK_INT_STATUS", 15, 15, &umr_bitfield_default }, + { "VUPDATE_NO_LOCK_EVENT_CLEAR", 16, 16, &umr_bitfield_default }, + { "VUPDATE_NO_LOCK_STATUS", 17, 17, &umr_bitfield_default }, + { "VREADY_INT_EN", 18, 18, &umr_bitfield_default }, + { "VREADY_INT_TYPE", 19, 19, &umr_bitfield_default }, + { "VREADY_EVENT_OCCURRED", 20, 20, &umr_bitfield_default }, + { "VREADY_INT_STATUS", 21, 21, &umr_bitfield_default }, + { "VREADY_EVENT_CLEAR", 22, 22, &umr_bitfield_default }, + { "STEREO_SELECT_STATUS", 24, 24, &umr_bitfield_default }, + { "FIELD_NUMBER_STATUS", 25, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_MASTER_UPDATE_LOCK[] = { + { "OTG_MASTER_UPDATE_LOCK", 0, 0, &umr_bitfield_default }, + { "UPDATE_LOCK_STATUS", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_GSL_CONTROL[] = { + { "OTG_GSL0_EN", 0, 0, &umr_bitfield_default }, + { "OTG_GSL1_EN", 1, 1, &umr_bitfield_default }, + { "OTG_GSL2_EN", 2, 2, &umr_bitfield_default }, + { "OTG_GSL_MASTER_EN", 3, 3, &umr_bitfield_default }, + { "OTG_GSL_FORCE_DELAY", 16, 20, &umr_bitfield_default }, + { "OTG_GSL_CHECK_ALL_FIELDS", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_GSL_WINDOW_X[] = { + { "OTG_GSL_WINDOW_START_X", 0, 14, &umr_bitfield_default }, + { "OTG_GSL_WINDOW_END_X", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_GSL_WINDOW_Y[] = { + { "OTG_GSL_WINDOW_START_Y", 0, 14, &umr_bitfield_default }, + { "OTG_GSL_WINDOW_END_Y", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_VUPDATE_KEEPOUT[] = { + { "MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET", 0, 15, &umr_bitfield_default }, + { "MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET", 16, 25, &umr_bitfield_default }, + { "OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_GLOBAL_CONTROL0[] = { + { "OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT", 0, 7, &umr_bitfield_default }, + { "OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN", 8, 8, &umr_bitfield_default }, + { "OTG_MASTER_UPDATE_LOCK_SEL", 25, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_GLOBAL_CONTROL1[] = { + { "MASTER_UPDATE_LOCK_DB_X", 0, 14, &umr_bitfield_default }, + { "MASTER_UPDATE_LOCK_DB_Y", 16, 30, &umr_bitfield_default }, + { "MASTER_UPDATE_LOCK_DB_EN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_GLOBAL_CONTROL2[] = { + { "DIG_UPDATE_LOCATION", 0, 9, &umr_bitfield_default }, + { "GLOBAL_UPDATE_LOCK_EN", 10, 10, &umr_bitfield_default }, + { "MANUAL_FLOW_CONTROL_SEL", 16, 18, &umr_bitfield_default }, + { "DCCG_VUPDATE_MODE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_GLOBAL_CONTROL3[] = { + { "MASTER_UPDATE_LOCK_DB_FIELD", 0, 1, &umr_bitfield_default }, + { "MASTER_UPDATE_LOCK_DB_STEREO_SEL", 4, 5, &umr_bitfield_default }, + { "MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_TRIG_MANUAL_CONTROL[] = { + { "TRIG_MANUAL_CONTROL", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_MANUAL_FLOW_CONTROL[] = { + { "MANUAL_FLOW_CONTROL", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_RANGE_TIMING_INT_STATUS[] = { + { "OTG_RANGE_TIMING_UPDATE_OCCURRED", 0, 0, &umr_bitfield_default }, + { "OTG_RANGE_TIMING_UPDATE_OCCURRED_INT", 4, 4, &umr_bitfield_default }, + { "OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR", 8, 8, &umr_bitfield_default }, + { "OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK", 12, 12, &umr_bitfield_default }, + { "OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_DRR_CONTROL[] = { + { "OTG_DRR_AVERAGE_FRAME", 0, 2, &umr_bitfield_default }, + { "OTG_V_TOTAL_LAST_USED_BY_DRR", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_REQUEST_CONTROL[] = { + { "OTG_REQUEST_MODE_FOR_H_DUPLICATE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG1_OTG_SPARE_REGISTER[] = { + { "OTG_SPARE_REG", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_H_TOTAL[] = { + { "OTG_H_TOTAL", 0, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_H_BLANK_START_END[] = { + { "OTG_H_BLANK_START", 0, 14, &umr_bitfield_default }, + { "OTG_H_BLANK_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_H_SYNC_A[] = { + { "OTG_H_SYNC_A_START", 0, 14, &umr_bitfield_default }, + { "OTG_H_SYNC_A_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_H_SYNC_A_CNTL[] = { + { "OTG_H_SYNC_A_POL", 0, 0, &umr_bitfield_default }, + { "OTG_COMP_SYNC_A_EN", 16, 16, &umr_bitfield_default }, + { "OTG_H_SYNC_A_CUTOFF", 17, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_H_TIMING_CNTL[] = { + { "OTG_H_TIMING_DIV_BY2", 0, 0, &umr_bitfield_default }, + { "OTG_H_TIMING_DIV_BY2_UPDATE_MODE", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_V_TOTAL[] = { + { "OTG_V_TOTAL", 0, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_V_TOTAL_MIN[] = { + { "OTG_V_TOTAL_MIN", 0, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_V_TOTAL_MAX[] = { + { "OTG_V_TOTAL_MAX", 0, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_V_TOTAL_MID[] = { + { "OTG_V_TOTAL_MID", 0, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_V_TOTAL_CONTROL[] = { + { "OTG_V_TOTAL_MIN_SEL", 0, 0, &umr_bitfield_default }, + { "OTG_V_TOTAL_MAX_SEL", 1, 1, &umr_bitfield_default }, + { "OTG_VTOTAL_MID_REPLACING_MAX_EN", 2, 2, &umr_bitfield_default }, + { "OTG_VTOTAL_MID_REPLACING_MIN_EN", 3, 3, &umr_bitfield_default }, + { "OTG_FORCE_LOCK_ON_EVENT", 4, 4, &umr_bitfield_default }, + { "OTG_SET_V_TOTAL_MIN_MASK_EN", 7, 7, &umr_bitfield_default }, + { "OTG_VTOTAL_MID_FRAME_NUM", 8, 15, &umr_bitfield_default }, + { "OTG_SET_V_TOTAL_MIN_MASK", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_V_TOTAL_INT_STATUS[] = { + { "OTG_SET_V_TOTAL_MIN_EVENT_OCCURED", 0, 0, &umr_bitfield_default }, + { "OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_INT", 4, 4, &umr_bitfield_default }, + { "OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK", 8, 8, &umr_bitfield_default }, + { "OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK", 12, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_VSYNC_NOM_INT_STATUS[] = { + { "OTG_VSYNC_NOM", 0, 0, &umr_bitfield_default }, + { "OTG_VSYNC_NOM_INT_CLEAR", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_V_BLANK_START_END[] = { + { "OTG_V_BLANK_START", 0, 14, &umr_bitfield_default }, + { "OTG_V_BLANK_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_V_SYNC_A[] = { + { "OTG_V_SYNC_A_START", 0, 14, &umr_bitfield_default }, + { "OTG_V_SYNC_A_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_V_SYNC_A_CNTL[] = { + { "OTG_V_SYNC_A_POL", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_TRIGA_CNTL[] = { + { "OTG_TRIGA_SOURCE_SELECT", 0, 4, &umr_bitfield_default }, + { "OTG_TRIGA_SOURCE_PIPE_SELECT", 5, 7, &umr_bitfield_default }, + { "OTG_TRIGA_POLARITY_SELECT", 8, 10, &umr_bitfield_default }, + { "OTG_TRIGA_RESYNC_BYPASS_EN", 11, 11, &umr_bitfield_default }, + { "OTG_TRIGA_INPUT_STATUS", 12, 12, &umr_bitfield_default }, + { "OTG_TRIGA_POLARITY_STATUS", 13, 13, &umr_bitfield_default }, + { "OTG_TRIGA_OCCURRED", 14, 14, &umr_bitfield_default }, + { "OTG_TRIGA_RISING_EDGE_DETECT_CNTL", 16, 17, &umr_bitfield_default }, + { "OTG_TRIGA_FALLING_EDGE_DETECT_CNTL", 18, 19, &umr_bitfield_default }, + { "OTG_TRIGA_FREQUENCY_SELECT", 20, 21, &umr_bitfield_default }, + { "OTG_TRIGA_DELAY", 24, 28, &umr_bitfield_default }, + { "OTG_TRIGA_CLEAR", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_TRIGA_MANUAL_TRIG[] = { + { "OTG_TRIGA_MANUAL_TRIG", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_TRIGB_CNTL[] = { + { "OTG_TRIGB_SOURCE_SELECT", 0, 4, &umr_bitfield_default }, + { "OTG_TRIGB_SOURCE_PIPE_SELECT", 5, 7, &umr_bitfield_default }, + { "OTG_TRIGB_POLARITY_SELECT", 8, 10, &umr_bitfield_default }, + { "OTG_TRIGB_RESYNC_BYPASS_EN", 11, 11, &umr_bitfield_default }, + { "OTG_TRIGB_INPUT_STATUS", 12, 12, &umr_bitfield_default }, + { "OTG_TRIGB_POLARITY_STATUS", 13, 13, &umr_bitfield_default }, + { "OTG_TRIGB_OCCURRED", 14, 14, &umr_bitfield_default }, + { "OTG_TRIGB_RISING_EDGE_DETECT_CNTL", 16, 17, &umr_bitfield_default }, + { "OTG_TRIGB_FALLING_EDGE_DETECT_CNTL", 18, 19, &umr_bitfield_default }, + { "OTG_TRIGB_FREQUENCY_SELECT", 20, 21, &umr_bitfield_default }, + { "OTG_TRIGB_DELAY", 24, 28, &umr_bitfield_default }, + { "OTG_TRIGB_CLEAR", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_TRIGB_MANUAL_TRIG[] = { + { "OTG_TRIGB_MANUAL_TRIG", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_FORCE_COUNT_NOW_CNTL[] = { + { "OTG_FORCE_COUNT_NOW_MODE", 0, 1, &umr_bitfield_default }, + { "OTG_FORCE_COUNT_NOW_CHECK", 4, 4, &umr_bitfield_default }, + { "OTG_FORCE_COUNT_NOW_TRIG_SEL", 8, 8, &umr_bitfield_default }, + { "OTG_FORCE_COUNT_NOW_OCCURRED", 16, 16, &umr_bitfield_default }, + { "OTG_FORCE_COUNT_NOW_CLEAR", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_FLOW_CONTROL[] = { + { "OTG_FLOW_CONTROL_SOURCE_SELECT", 0, 4, &umr_bitfield_default }, + { "OTG_FLOW_CONTROL_POLARITY", 8, 8, &umr_bitfield_default }, + { "OTG_FLOW_CONTROL_GRANULARITY", 16, 16, &umr_bitfield_default }, + { "OTG_FLOW_CONTROL_INPUT_STATUS", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_STEREO_FORCE_NEXT_EYE[] = { + { "OTG_STEREO_FORCE_NEXT_EYE", 0, 1, &umr_bitfield_default }, + { "OTG_AVSYNC_FRAME_COUNTER", 8, 15, &umr_bitfield_default }, + { "OTG_AVSYNC_LINE_COUNTER", 16, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_AVSYNC_COUNTER[] = { + { "OTG_AVSYNC_COUNTER", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_CONTROL[] = { + { "OTG_MASTER_EN", 0, 0, &umr_bitfield_default }, + { "OTG_DISABLE_POINT_CNTL", 8, 9, &umr_bitfield_default }, + { "OTG_START_POINT_CNTL", 12, 12, &umr_bitfield_default }, + { "OTG_FIELD_NUMBER_CNTL", 13, 13, &umr_bitfield_default }, + { "OTG_FIELD_NUMBER_POLARITY", 14, 14, &umr_bitfield_default }, + { "OTG_CURRENT_MASTER_EN_STATE", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_BLANK_CONTROL[] = { + { "OTG_CURRENT_BLANK_STATE", 0, 0, &umr_bitfield_default }, + { "OTG_BLANK_DATA_EN", 8, 8, &umr_bitfield_default }, + { "OTG_BLANK_DE_MODE", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_PIPE_ABORT_CONTROL[] = { + { "OTG_PIPE_ABORT", 0, 0, &umr_bitfield_default }, + { "OTG_PIPE_ABORT_DONE", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_INTERLACE_CONTROL[] = { + { "OTG_INTERLACE_ENABLE", 0, 0, &umr_bitfield_default }, + { "OTG_INTERLACE_FORCE_NEXT_FIELD", 16, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_INTERLACE_STATUS[] = { + { "OTG_INTERLACE_CURRENT_FIELD", 0, 0, &umr_bitfield_default }, + { "OTG_INTERLACE_NEXT_FIELD", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_FIELD_INDICATION_CONTROL[] = { + { "OTG_FIELD_INDICATION_OUTPUT_POLARITY", 0, 0, &umr_bitfield_default }, + { "OTG_FIELD_ALIGNMENT", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_PIXEL_DATA_READBACK0[] = { + { "OTG_PIXEL_DATA_BLUE_CB", 0, 15, &umr_bitfield_default }, + { "OTG_PIXEL_DATA_GREEN_Y", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_PIXEL_DATA_READBACK1[] = { + { "OTG_PIXEL_DATA_RED_CR", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_STATUS[] = { + { "OTG_V_BLANK", 0, 0, &umr_bitfield_default }, + { "OTG_V_ACTIVE_DISP", 1, 1, &umr_bitfield_default }, + { "OTG_V_SYNC_A", 2, 2, &umr_bitfield_default }, + { "OTG_V_UPDATE", 3, 3, &umr_bitfield_default }, + { "OTG_V_BLANK_3D_STRUCTURE", 5, 5, &umr_bitfield_default }, + { "OTG_H_BLANK", 16, 16, &umr_bitfield_default }, + { "OTG_H_ACTIVE_DISP", 17, 17, &umr_bitfield_default }, + { "OTG_H_SYNC_A", 18, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_STATUS_POSITION[] = { + { "OTG_VERT_COUNT", 0, 14, &umr_bitfield_default }, + { "OTG_HORZ_COUNT", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_NOM_VERT_POSITION[] = { + { "OTG_VERT_COUNT_NOM", 0, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_STATUS_FRAME_COUNT[] = { + { "OTG_FRAME_COUNT", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_STATUS_VF_COUNT[] = { + { "OTG_VF_COUNT", 0, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_STATUS_HV_COUNT[] = { + { "OTG_HV_COUNT", 0, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_COUNT_CONTROL[] = { + { "OTG_HORZ_COUNT_BY2_EN", 0, 0, &umr_bitfield_default }, + { "OTG_HORZ_REPETITION_COUNT", 1, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_COUNT_RESET[] = { + { "OTG_RESET_FRAME_COUNT", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE[] = { + { "OTG_MANUAL_FORCE_VSYNC_NEXT_LINE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_VERT_SYNC_CONTROL[] = { + { "OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED", 0, 0, &umr_bitfield_default }, + { "OTG_FORCE_VSYNC_NEXT_LINE_CLEAR", 8, 8, &umr_bitfield_default }, + { "OTG_AUTO_FORCE_VSYNC_MODE", 16, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_STEREO_STATUS[] = { + { "OTG_STEREO_CURRENT_EYE", 0, 0, &umr_bitfield_default }, + { "OTG_STEREO_SYNC_OUTPUT", 8, 8, &umr_bitfield_default }, + { "OTG_STEREO_SYNC_SELECT", 16, 16, &umr_bitfield_default }, + { "OTG_STEREO_EYE_FLAG", 20, 20, &umr_bitfield_default }, + { "OTG_STEREO_FORCE_NEXT_EYE_PENDING", 24, 25, &umr_bitfield_default }, + { "OTG_CURRENT_3D_STRUCTURE_STATE", 30, 30, &umr_bitfield_default }, + { "OTG_CURRENT_STEREOSYNC_EN_STATE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_STEREO_CONTROL[] = { + { "OTG_STEREO_SYNC_OUTPUT_LINE_NUM", 0, 14, &umr_bitfield_default }, + { "OTG_STEREO_SYNC_OUTPUT_POLARITY", 15, 15, &umr_bitfield_default }, + { "OTG_STEREO_EYE_FLAG_POLARITY", 17, 17, &umr_bitfield_default }, + { "OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP", 18, 18, &umr_bitfield_default }, + { "OTG_DISABLE_FIELD_NUM", 19, 19, &umr_bitfield_default }, + { "OTG_DISABLE_V_BLANK_FOR_DP_FIX", 20, 20, &umr_bitfield_default }, + { "OTG_STEREO_EN", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_SNAPSHOT_STATUS[] = { + { "OTG_SNAPSHOT_OCCURRED", 0, 0, &umr_bitfield_default }, + { "OTG_SNAPSHOT_CLEAR", 1, 1, &umr_bitfield_default }, + { "OTG_SNAPSHOT_MANUAL_TRIGGER", 2, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_SNAPSHOT_CONTROL[] = { + { "OTG_AUTO_SNAPSHOT_TRIG_SEL", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_SNAPSHOT_POSITION[] = { + { "OTG_SNAPSHOT_VERT_COUNT", 0, 14, &umr_bitfield_default }, + { "OTG_SNAPSHOT_HORZ_COUNT", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_SNAPSHOT_FRAME[] = { + { "OTG_SNAPSHOT_FRAME_COUNT", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_INTERRUPT_CONTROL[] = { + { "OTG_SNAPSHOT_INT_MSK", 0, 0, &umr_bitfield_default }, + { "OTG_SNAPSHOT_INT_TYPE", 1, 1, &umr_bitfield_default }, + { "OTG_FORCE_COUNT_NOW_INT_MSK", 8, 8, &umr_bitfield_default }, + { "OTG_FORCE_COUNT_NOW_INT_TYPE", 9, 9, &umr_bitfield_default }, + { "OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK", 16, 16, &umr_bitfield_default }, + { "OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE", 17, 17, &umr_bitfield_default }, + { "OTG_TRIGA_INT_MSK", 24, 24, &umr_bitfield_default }, + { "OTG_TRIGB_INT_MSK", 25, 25, &umr_bitfield_default }, + { "OTG_TRIGA_INT_TYPE", 26, 26, &umr_bitfield_default }, + { "OTG_TRIGB_INT_TYPE", 27, 27, &umr_bitfield_default }, + { "OTG_VSYNC_NOM_INT_MSK", 28, 28, &umr_bitfield_default }, + { "OTG_VSYNC_NOM_INT_TYPE", 29, 29, &umr_bitfield_default }, + { "OTG_GSL_VSYNC_GAP_INT_MSK", 30, 30, &umr_bitfield_default }, + { "OTG_GSL_VSYNC_GAP_INT_TYPE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_UPDATE_LOCK[] = { + { "OTG_UPDATE_LOCK", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_DOUBLE_BUFFER_CONTROL[] = { + { "OTG_UPDATE_PENDING", 0, 0, &umr_bitfield_default }, + { "OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING", 2, 2, &umr_bitfield_default }, + { "OTG_BLANK_DATA_EN_UPDATE_PENDING", 3, 3, &umr_bitfield_default }, + { "OTG_RANGE_TIMING_DBUF_UPDATE_PENDING", 4, 4, &umr_bitfield_default }, + { "OTG_TIMING_DB_UPDATE_PENDING", 5, 5, &umr_bitfield_default }, + { "OTG_3D_CTRL_DB_UPDATE_PENDING", 6, 6, &umr_bitfield_default }, + { "OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING", 7, 7, &umr_bitfield_default }, + { "OTG_UPDATE_INSTANTLY", 8, 8, &umr_bitfield_default }, + { "OTG_BLANK_DATA_DOUBLE_BUFFER_EN", 16, 16, &umr_bitfield_default }, + { "OTG_RANGE_TIMING_DBUF_UPDATE_MODE", 24, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_TEST_PATTERN_CONTROL[] = { + { "OTG_TEST_PATTERN_EN", 0, 0, &umr_bitfield_default }, + { "OTG_TEST_PATTERN_MODE", 8, 10, &umr_bitfield_default }, + { "OTG_TEST_PATTERN_DYNAMIC_RANGE", 16, 16, &umr_bitfield_default }, + { "OTG_TEST_PATTERN_COLOR_FORMAT", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_TEST_PATTERN_PARAMETERS[] = { + { "OTG_TEST_PATTERN_INC0", 0, 3, &umr_bitfield_default }, + { "OTG_TEST_PATTERN_INC1", 4, 7, &umr_bitfield_default }, + { "OTG_TEST_PATTERN_VRES", 8, 11, &umr_bitfield_default }, + { "OTG_TEST_PATTERN_HRES", 12, 15, &umr_bitfield_default }, + { "OTG_TEST_PATTERN_RAMP0_OFFSET", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_TEST_PATTERN_COLOR[] = { + { "OTG_TEST_PATTERN_DATA", 0, 15, &umr_bitfield_default }, + { "OTG_TEST_PATTERN_MASK", 16, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_MASTER_EN[] = { + { "OTG_MASTER_EN", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_BLANK_DATA_COLOR[] = { + { "OTG_BLANK_DATA_COLOR_BLUE_CB", 0, 9, &umr_bitfield_default }, + { "OTG_BLANK_DATA_COLOR_GREEN_Y", 10, 19, &umr_bitfield_default }, + { "OTG_BLANK_DATA_COLOR_RED_CR", 20, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_BLANK_DATA_COLOR_EXT[] = { + { "OTG_BLANK_DATA_COLOR_BLUE_CB_EXT", 0, 5, &umr_bitfield_default }, + { "OTG_BLANK_DATA_COLOR_GREEN_Y_EXT", 8, 13, &umr_bitfield_default }, + { "OTG_BLANK_DATA_COLOR_RED_CR_EXT", 16, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_BLACK_COLOR[] = { + { "OTG_BLACK_COLOR_B_CB", 0, 9, &umr_bitfield_default }, + { "OTG_BLACK_COLOR_G_Y", 10, 19, &umr_bitfield_default }, + { "OTG_BLACK_COLOR_R_CR", 20, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_BLACK_COLOR_EXT[] = { + { "OTG_BLACK_COLOR_B_CB_EXT", 0, 5, &umr_bitfield_default }, + { "OTG_BLACK_COLOR_G_Y_EXT", 8, 13, &umr_bitfield_default }, + { "OTG_BLACK_COLOR_R_CR_EXT", 16, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_VERTICAL_INTERRUPT0_POSITION[] = { + { "OTG_VERTICAL_INTERRUPT0_LINE_START", 0, 14, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT0_LINE_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL[] = { + { "OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY", 4, 4, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT0_INT_ENABLE", 8, 8, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT0_STATUS", 12, 12, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT0_INT_STATUS", 16, 16, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT0_CLEAR", 20, 20, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT0_INT_TYPE", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_VERTICAL_INTERRUPT1_POSITION[] = { + { "OTG_VERTICAL_INTERRUPT1_LINE_START", 0, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL[] = { + { "OTG_VERTICAL_INTERRUPT1_INT_ENABLE", 8, 8, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT1_STATUS", 12, 12, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT1_INT_STATUS", 16, 16, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT1_CLEAR", 20, 20, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT1_INT_TYPE", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_VERTICAL_INTERRUPT2_POSITION[] = { + { "OTG_VERTICAL_INTERRUPT2_LINE_START", 0, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL[] = { + { "OTG_VERTICAL_INTERRUPT2_INT_ENABLE", 8, 8, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT2_STATUS", 12, 12, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT2_INT_STATUS", 16, 16, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT2_CLEAR", 20, 20, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT2_INT_TYPE", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_CRC_CNTL[] = { + { "OTG_CRC_EN", 0, 0, &umr_bitfield_default }, + { "OTG_CRC_DUAL_LINK_EN", 1, 1, &umr_bitfield_default }, + { "OTG_CRC_DUAL_LINK_MODE", 2, 2, &umr_bitfield_default }, + { "OTG_CRC_BLANK_ONLY", 3, 3, &umr_bitfield_default }, + { "OTG_CRC_CONT_EN", 4, 4, &umr_bitfield_default }, + { "OTG_CRC_CAPTURE_START_SEL", 5, 6, &umr_bitfield_default }, + { "OTG_CRC_STEREO_MODE", 8, 9, &umr_bitfield_default }, + { "OTG_CRC_INTERLACE_MODE", 12, 13, &umr_bitfield_default }, + { "OTG_CRC_MULTI_STREAM_MODE", 16, 18, &umr_bitfield_default }, + { "OTG_CRC_USE_NEW_AND_REPEATED_PIXELS", 19, 19, &umr_bitfield_default }, + { "OTG_CRC0_SELECT", 20, 22, &umr_bitfield_default }, + { "OTG_CRC1_SELECT", 24, 26, &umr_bitfield_default }, + { "OTG_ONE_SHOT_CRC0_PENDING", 28, 28, &umr_bitfield_default }, + { "OTG_ONE_SHOT_CRC1_PENDING", 29, 29, &umr_bitfield_default }, + { "OTG_ONE_SHOT_CRC2_PENDING", 30, 30, &umr_bitfield_default }, + { "OTG_ONE_SHOT_CRC3_PENDING", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_CRC0_WINDOWA_X_CONTROL[] = { + { "OTG_CRC0_WINDOWA_X_START", 0, 14, &umr_bitfield_default }, + { "OTG_CRC0_WINDOWA_X_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_CRC0_WINDOWA_Y_CONTROL[] = { + { "OTG_CRC0_WINDOWA_Y_START", 0, 14, &umr_bitfield_default }, + { "OTG_CRC0_WINDOWA_Y_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_CRC0_WINDOWB_X_CONTROL[] = { + { "OTG_CRC0_WINDOWB_X_START", 0, 14, &umr_bitfield_default }, + { "OTG_CRC0_WINDOWB_X_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_CRC0_WINDOWB_Y_CONTROL[] = { + { "OTG_CRC0_WINDOWB_Y_START", 0, 14, &umr_bitfield_default }, + { "OTG_CRC0_WINDOWB_Y_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_CRC0_DATA_RG[] = { + { "CRC0_R_CR", 0, 15, &umr_bitfield_default }, + { "CRC0_G_Y", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_CRC0_DATA_B[] = { + { "CRC0_B_CB", 0, 15, &umr_bitfield_default }, + { "CRC0_C", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_CRC1_WINDOWA_X_CONTROL[] = { + { "OTG_CRC1_WINDOWA_X_START", 0, 14, &umr_bitfield_default }, + { "OTG_CRC1_WINDOWA_X_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_CRC1_WINDOWA_Y_CONTROL[] = { + { "OTG_CRC1_WINDOWA_Y_START", 0, 14, &umr_bitfield_default }, + { "OTG_CRC1_WINDOWA_Y_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_CRC1_WINDOWB_X_CONTROL[] = { + { "OTG_CRC1_WINDOWB_X_START", 0, 14, &umr_bitfield_default }, + { "OTG_CRC1_WINDOWB_X_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_CRC1_WINDOWB_Y_CONTROL[] = { + { "OTG_CRC1_WINDOWB_Y_START", 0, 14, &umr_bitfield_default }, + { "OTG_CRC1_WINDOWB_Y_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_CRC1_DATA_RG[] = { + { "CRC1_R_CR", 0, 15, &umr_bitfield_default }, + { "CRC1_G_Y", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_CRC1_DATA_B[] = { + { "CRC1_B_CB", 0, 15, &umr_bitfield_default }, + { "CRC1_C", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_CRC2_DATA_RG[] = { + { "CRC2_R_CR", 0, 15, &umr_bitfield_default }, + { "CRC2_G_Y", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_CRC2_DATA_B[] = { + { "CRC2_B_CB", 0, 15, &umr_bitfield_default }, + { "CRC2_C", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_CRC3_DATA_RG[] = { + { "CRC3_R_CR", 0, 15, &umr_bitfield_default }, + { "CRC3_G_Y", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_CRC3_DATA_B[] = { + { "CRC3_B_CB", 0, 15, &umr_bitfield_default }, + { "CRC3_C", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_CRC_SIG_RED_GREEN_MASK[] = { + { "OTG_CRC_SIG_RED_MASK", 0, 15, &umr_bitfield_default }, + { "OTG_CRC_SIG_GREEN_MASK", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK[] = { + { "OTG_CRC_SIG_BLUE_MASK", 0, 15, &umr_bitfield_default }, + { "OTG_CRC_SIG_CONTROL_MASK", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_STATIC_SCREEN_CONTROL[] = { + { "OTG_STATIC_SCREEN_EVENT_MASK", 0, 15, &umr_bitfield_default }, + { "OTG_STATIC_SCREEN_FRAME_COUNT", 16, 23, &umr_bitfield_default }, + { "OTG_CPU_SS_INT_ENABLE", 24, 24, &umr_bitfield_default }, + { "OTG_SS_STATUS", 25, 25, &umr_bitfield_default }, + { "OTG_CPU_SS_INT_STATUS", 26, 26, &umr_bitfield_default }, + { "OTG_CPU_SS_INT_CLEAR", 27, 27, &umr_bitfield_default }, + { "OTG_CPU_SS_INT_TYPE", 28, 28, &umr_bitfield_default }, + { "OTG_STATIC_SCREEN_OVERRIDE", 30, 30, &umr_bitfield_default }, + { "OTG_STATIC_SCREEN_OVERRIDE_VALUE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_3D_STRUCTURE_CONTROL[] = { + { "OTG_3D_STRUCTURE_EN", 0, 0, &umr_bitfield_default }, + { "OTG_3D_STRUCTURE_V_UPDATE_MODE", 8, 9, &umr_bitfield_default }, + { "OTG_3D_STRUCTURE_STEREO_SEL_OVR", 12, 12, &umr_bitfield_default }, + { "OTG_3D_STRUCTURE_F_COUNT_RESET", 16, 16, &umr_bitfield_default }, + { "OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING", 17, 17, &umr_bitfield_default }, + { "OTG_3D_STRUCTURE_F_COUNT", 18, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_GSL_VSYNC_GAP[] = { + { "OTG_GSL_VSYNC_GAP_LIMIT", 0, 7, &umr_bitfield_default }, + { "OTG_GSL_VSYNC_GAP_DELAY", 8, 15, &umr_bitfield_default }, + { "OTG_GSL_VSYNC_GAP_SOURCE_SEL", 16, 16, &umr_bitfield_default }, + { "OTG_GSL_VSYNC_GAP_MODE", 17, 18, &umr_bitfield_default }, + { "OTG_GSL_VSYNC_GAP_CLEAR", 19, 19, &umr_bitfield_default }, + { "OTG_GSL_VSYNC_GAP_OCCURRED", 20, 20, &umr_bitfield_default }, + { "OTG_GSL_VSYNC_GAP_MASTER_FASTER", 23, 23, &umr_bitfield_default }, + { "OTG_GSL_VSYNC_GAP", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_MASTER_UPDATE_MODE[] = { + { "MASTER_UPDATE_INTERLACED_MODE", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_CLOCK_CONTROL[] = { + { "OTG_CLOCK_EN", 0, 0, &umr_bitfield_default }, + { "OTG_CLOCK_GATE_DIS", 1, 1, &umr_bitfield_default }, + { "OTG_SOFT_RESET", 4, 4, &umr_bitfield_default }, + { "OTG_CLOCK_ON", 8, 8, &umr_bitfield_default }, + { "OTG_BUSY", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_VSTARTUP_PARAM[] = { + { "VSTARTUP_START", 0, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_VUPDATE_PARAM[] = { + { "VUPDATE_OFFSET", 0, 15, &umr_bitfield_default }, + { "VUPDATE_WIDTH", 16, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_VREADY_PARAM[] = { + { "VREADY_OFFSET", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_GLOBAL_SYNC_STATUS[] = { + { "VSTARTUP_INT_EN", 0, 0, &umr_bitfield_default }, + { "VSTARTUP_INT_TYPE", 1, 1, &umr_bitfield_default }, + { "VSTARTUP_EVENT_OCCURRED", 2, 2, &umr_bitfield_default }, + { "VSTARTUP_INT_STATUS", 3, 3, &umr_bitfield_default }, + { "VSTARTUP_EVENT_CLEAR", 4, 4, &umr_bitfield_default }, + { "VUPDATE_INT_EN", 5, 5, &umr_bitfield_default }, + { "VUPDATE_INT_TYPE", 6, 6, &umr_bitfield_default }, + { "VUPDATE_INT_POSITION_SEL", 7, 7, &umr_bitfield_default }, + { "VUPDATE_EVENT_OCCURRED", 8, 8, &umr_bitfield_default }, + { "VUPDATE_INT_STATUS", 9, 9, &umr_bitfield_default }, + { "VUPDATE_EVENT_CLEAR", 10, 10, &umr_bitfield_default }, + { "VUPDATE_STATUS", 11, 11, &umr_bitfield_default }, + { "VUPDATE_NO_LOCK_INT_EN", 12, 12, &umr_bitfield_default }, + { "VUPDATE_NO_LOCK_INT_TYPE", 13, 13, &umr_bitfield_default }, + { "VUPDATE_NO_LOCK_EVENT_OCCURRED", 14, 14, &umr_bitfield_default }, + { "VUPDATE_NO_LOCK_INT_STATUS", 15, 15, &umr_bitfield_default }, + { "VUPDATE_NO_LOCK_EVENT_CLEAR", 16, 16, &umr_bitfield_default }, + { "VUPDATE_NO_LOCK_STATUS", 17, 17, &umr_bitfield_default }, + { "VREADY_INT_EN", 18, 18, &umr_bitfield_default }, + { "VREADY_INT_TYPE", 19, 19, &umr_bitfield_default }, + { "VREADY_EVENT_OCCURRED", 20, 20, &umr_bitfield_default }, + { "VREADY_INT_STATUS", 21, 21, &umr_bitfield_default }, + { "VREADY_EVENT_CLEAR", 22, 22, &umr_bitfield_default }, + { "STEREO_SELECT_STATUS", 24, 24, &umr_bitfield_default }, + { "FIELD_NUMBER_STATUS", 25, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_MASTER_UPDATE_LOCK[] = { + { "OTG_MASTER_UPDATE_LOCK", 0, 0, &umr_bitfield_default }, + { "UPDATE_LOCK_STATUS", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_GSL_CONTROL[] = { + { "OTG_GSL0_EN", 0, 0, &umr_bitfield_default }, + { "OTG_GSL1_EN", 1, 1, &umr_bitfield_default }, + { "OTG_GSL2_EN", 2, 2, &umr_bitfield_default }, + { "OTG_GSL_MASTER_EN", 3, 3, &umr_bitfield_default }, + { "OTG_GSL_FORCE_DELAY", 16, 20, &umr_bitfield_default }, + { "OTG_GSL_CHECK_ALL_FIELDS", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_GSL_WINDOW_X[] = { + { "OTG_GSL_WINDOW_START_X", 0, 14, &umr_bitfield_default }, + { "OTG_GSL_WINDOW_END_X", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_GSL_WINDOW_Y[] = { + { "OTG_GSL_WINDOW_START_Y", 0, 14, &umr_bitfield_default }, + { "OTG_GSL_WINDOW_END_Y", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_VUPDATE_KEEPOUT[] = { + { "MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET", 0, 15, &umr_bitfield_default }, + { "MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET", 16, 25, &umr_bitfield_default }, + { "OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_GLOBAL_CONTROL0[] = { + { "OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT", 0, 7, &umr_bitfield_default }, + { "OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN", 8, 8, &umr_bitfield_default }, + { "OTG_MASTER_UPDATE_LOCK_SEL", 25, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_GLOBAL_CONTROL1[] = { + { "MASTER_UPDATE_LOCK_DB_X", 0, 14, &umr_bitfield_default }, + { "MASTER_UPDATE_LOCK_DB_Y", 16, 30, &umr_bitfield_default }, + { "MASTER_UPDATE_LOCK_DB_EN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_GLOBAL_CONTROL2[] = { + { "DIG_UPDATE_LOCATION", 0, 9, &umr_bitfield_default }, + { "GLOBAL_UPDATE_LOCK_EN", 10, 10, &umr_bitfield_default }, + { "MANUAL_FLOW_CONTROL_SEL", 16, 18, &umr_bitfield_default }, + { "DCCG_VUPDATE_MODE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_GLOBAL_CONTROL3[] = { + { "MASTER_UPDATE_LOCK_DB_FIELD", 0, 1, &umr_bitfield_default }, + { "MASTER_UPDATE_LOCK_DB_STEREO_SEL", 4, 5, &umr_bitfield_default }, + { "MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_TRIG_MANUAL_CONTROL[] = { + { "TRIG_MANUAL_CONTROL", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_MANUAL_FLOW_CONTROL[] = { + { "MANUAL_FLOW_CONTROL", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_RANGE_TIMING_INT_STATUS[] = { + { "OTG_RANGE_TIMING_UPDATE_OCCURRED", 0, 0, &umr_bitfield_default }, + { "OTG_RANGE_TIMING_UPDATE_OCCURRED_INT", 4, 4, &umr_bitfield_default }, + { "OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR", 8, 8, &umr_bitfield_default }, + { "OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK", 12, 12, &umr_bitfield_default }, + { "OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_DRR_CONTROL[] = { + { "OTG_DRR_AVERAGE_FRAME", 0, 2, &umr_bitfield_default }, + { "OTG_V_TOTAL_LAST_USED_BY_DRR", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_REQUEST_CONTROL[] = { + { "OTG_REQUEST_MODE_FOR_H_DUPLICATE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG2_OTG_SPARE_REGISTER[] = { + { "OTG_SPARE_REG", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_H_TOTAL[] = { + { "OTG_H_TOTAL", 0, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_H_BLANK_START_END[] = { + { "OTG_H_BLANK_START", 0, 14, &umr_bitfield_default }, + { "OTG_H_BLANK_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_H_SYNC_A[] = { + { "OTG_H_SYNC_A_START", 0, 14, &umr_bitfield_default }, + { "OTG_H_SYNC_A_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_H_SYNC_A_CNTL[] = { + { "OTG_H_SYNC_A_POL", 0, 0, &umr_bitfield_default }, + { "OTG_COMP_SYNC_A_EN", 16, 16, &umr_bitfield_default }, + { "OTG_H_SYNC_A_CUTOFF", 17, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_H_TIMING_CNTL[] = { + { "OTG_H_TIMING_DIV_BY2", 0, 0, &umr_bitfield_default }, + { "OTG_H_TIMING_DIV_BY2_UPDATE_MODE", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_V_TOTAL[] = { + { "OTG_V_TOTAL", 0, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_V_TOTAL_MIN[] = { + { "OTG_V_TOTAL_MIN", 0, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_V_TOTAL_MAX[] = { + { "OTG_V_TOTAL_MAX", 0, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_V_TOTAL_MID[] = { + { "OTG_V_TOTAL_MID", 0, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_V_TOTAL_CONTROL[] = { + { "OTG_V_TOTAL_MIN_SEL", 0, 0, &umr_bitfield_default }, + { "OTG_V_TOTAL_MAX_SEL", 1, 1, &umr_bitfield_default }, + { "OTG_VTOTAL_MID_REPLACING_MAX_EN", 2, 2, &umr_bitfield_default }, + { "OTG_VTOTAL_MID_REPLACING_MIN_EN", 3, 3, &umr_bitfield_default }, + { "OTG_FORCE_LOCK_ON_EVENT", 4, 4, &umr_bitfield_default }, + { "OTG_SET_V_TOTAL_MIN_MASK_EN", 7, 7, &umr_bitfield_default }, + { "OTG_VTOTAL_MID_FRAME_NUM", 8, 15, &umr_bitfield_default }, + { "OTG_SET_V_TOTAL_MIN_MASK", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_V_TOTAL_INT_STATUS[] = { + { "OTG_SET_V_TOTAL_MIN_EVENT_OCCURED", 0, 0, &umr_bitfield_default }, + { "OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_INT", 4, 4, &umr_bitfield_default }, + { "OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK", 8, 8, &umr_bitfield_default }, + { "OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK", 12, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_VSYNC_NOM_INT_STATUS[] = { + { "OTG_VSYNC_NOM", 0, 0, &umr_bitfield_default }, + { "OTG_VSYNC_NOM_INT_CLEAR", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_V_BLANK_START_END[] = { + { "OTG_V_BLANK_START", 0, 14, &umr_bitfield_default }, + { "OTG_V_BLANK_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_V_SYNC_A[] = { + { "OTG_V_SYNC_A_START", 0, 14, &umr_bitfield_default }, + { "OTG_V_SYNC_A_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_V_SYNC_A_CNTL[] = { + { "OTG_V_SYNC_A_POL", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_TRIGA_CNTL[] = { + { "OTG_TRIGA_SOURCE_SELECT", 0, 4, &umr_bitfield_default }, + { "OTG_TRIGA_SOURCE_PIPE_SELECT", 5, 7, &umr_bitfield_default }, + { "OTG_TRIGA_POLARITY_SELECT", 8, 10, &umr_bitfield_default }, + { "OTG_TRIGA_RESYNC_BYPASS_EN", 11, 11, &umr_bitfield_default }, + { "OTG_TRIGA_INPUT_STATUS", 12, 12, &umr_bitfield_default }, + { "OTG_TRIGA_POLARITY_STATUS", 13, 13, &umr_bitfield_default }, + { "OTG_TRIGA_OCCURRED", 14, 14, &umr_bitfield_default }, + { "OTG_TRIGA_RISING_EDGE_DETECT_CNTL", 16, 17, &umr_bitfield_default }, + { "OTG_TRIGA_FALLING_EDGE_DETECT_CNTL", 18, 19, &umr_bitfield_default }, + { "OTG_TRIGA_FREQUENCY_SELECT", 20, 21, &umr_bitfield_default }, + { "OTG_TRIGA_DELAY", 24, 28, &umr_bitfield_default }, + { "OTG_TRIGA_CLEAR", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_TRIGA_MANUAL_TRIG[] = { + { "OTG_TRIGA_MANUAL_TRIG", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_TRIGB_CNTL[] = { + { "OTG_TRIGB_SOURCE_SELECT", 0, 4, &umr_bitfield_default }, + { "OTG_TRIGB_SOURCE_PIPE_SELECT", 5, 7, &umr_bitfield_default }, + { "OTG_TRIGB_POLARITY_SELECT", 8, 10, &umr_bitfield_default }, + { "OTG_TRIGB_RESYNC_BYPASS_EN", 11, 11, &umr_bitfield_default }, + { "OTG_TRIGB_INPUT_STATUS", 12, 12, &umr_bitfield_default }, + { "OTG_TRIGB_POLARITY_STATUS", 13, 13, &umr_bitfield_default }, + { "OTG_TRIGB_OCCURRED", 14, 14, &umr_bitfield_default }, + { "OTG_TRIGB_RISING_EDGE_DETECT_CNTL", 16, 17, &umr_bitfield_default }, + { "OTG_TRIGB_FALLING_EDGE_DETECT_CNTL", 18, 19, &umr_bitfield_default }, + { "OTG_TRIGB_FREQUENCY_SELECT", 20, 21, &umr_bitfield_default }, + { "OTG_TRIGB_DELAY", 24, 28, &umr_bitfield_default }, + { "OTG_TRIGB_CLEAR", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_TRIGB_MANUAL_TRIG[] = { + { "OTG_TRIGB_MANUAL_TRIG", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_FORCE_COUNT_NOW_CNTL[] = { + { "OTG_FORCE_COUNT_NOW_MODE", 0, 1, &umr_bitfield_default }, + { "OTG_FORCE_COUNT_NOW_CHECK", 4, 4, &umr_bitfield_default }, + { "OTG_FORCE_COUNT_NOW_TRIG_SEL", 8, 8, &umr_bitfield_default }, + { "OTG_FORCE_COUNT_NOW_OCCURRED", 16, 16, &umr_bitfield_default }, + { "OTG_FORCE_COUNT_NOW_CLEAR", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_FLOW_CONTROL[] = { + { "OTG_FLOW_CONTROL_SOURCE_SELECT", 0, 4, &umr_bitfield_default }, + { "OTG_FLOW_CONTROL_POLARITY", 8, 8, &umr_bitfield_default }, + { "OTG_FLOW_CONTROL_GRANULARITY", 16, 16, &umr_bitfield_default }, + { "OTG_FLOW_CONTROL_INPUT_STATUS", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_STEREO_FORCE_NEXT_EYE[] = { + { "OTG_STEREO_FORCE_NEXT_EYE", 0, 1, &umr_bitfield_default }, + { "OTG_AVSYNC_FRAME_COUNTER", 8, 15, &umr_bitfield_default }, + { "OTG_AVSYNC_LINE_COUNTER", 16, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_AVSYNC_COUNTER[] = { + { "OTG_AVSYNC_COUNTER", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_CONTROL[] = { + { "OTG_MASTER_EN", 0, 0, &umr_bitfield_default }, + { "OTG_DISABLE_POINT_CNTL", 8, 9, &umr_bitfield_default }, + { "OTG_START_POINT_CNTL", 12, 12, &umr_bitfield_default }, + { "OTG_FIELD_NUMBER_CNTL", 13, 13, &umr_bitfield_default }, + { "OTG_FIELD_NUMBER_POLARITY", 14, 14, &umr_bitfield_default }, + { "OTG_CURRENT_MASTER_EN_STATE", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_BLANK_CONTROL[] = { + { "OTG_CURRENT_BLANK_STATE", 0, 0, &umr_bitfield_default }, + { "OTG_BLANK_DATA_EN", 8, 8, &umr_bitfield_default }, + { "OTG_BLANK_DE_MODE", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_PIPE_ABORT_CONTROL[] = { + { "OTG_PIPE_ABORT", 0, 0, &umr_bitfield_default }, + { "OTG_PIPE_ABORT_DONE", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_INTERLACE_CONTROL[] = { + { "OTG_INTERLACE_ENABLE", 0, 0, &umr_bitfield_default }, + { "OTG_INTERLACE_FORCE_NEXT_FIELD", 16, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_INTERLACE_STATUS[] = { + { "OTG_INTERLACE_CURRENT_FIELD", 0, 0, &umr_bitfield_default }, + { "OTG_INTERLACE_NEXT_FIELD", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_FIELD_INDICATION_CONTROL[] = { + { "OTG_FIELD_INDICATION_OUTPUT_POLARITY", 0, 0, &umr_bitfield_default }, + { "OTG_FIELD_ALIGNMENT", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_PIXEL_DATA_READBACK0[] = { + { "OTG_PIXEL_DATA_BLUE_CB", 0, 15, &umr_bitfield_default }, + { "OTG_PIXEL_DATA_GREEN_Y", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_PIXEL_DATA_READBACK1[] = { + { "OTG_PIXEL_DATA_RED_CR", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_STATUS[] = { + { "OTG_V_BLANK", 0, 0, &umr_bitfield_default }, + { "OTG_V_ACTIVE_DISP", 1, 1, &umr_bitfield_default }, + { "OTG_V_SYNC_A", 2, 2, &umr_bitfield_default }, + { "OTG_V_UPDATE", 3, 3, &umr_bitfield_default }, + { "OTG_V_BLANK_3D_STRUCTURE", 5, 5, &umr_bitfield_default }, + { "OTG_H_BLANK", 16, 16, &umr_bitfield_default }, + { "OTG_H_ACTIVE_DISP", 17, 17, &umr_bitfield_default }, + { "OTG_H_SYNC_A", 18, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_STATUS_POSITION[] = { + { "OTG_VERT_COUNT", 0, 14, &umr_bitfield_default }, + { "OTG_HORZ_COUNT", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_NOM_VERT_POSITION[] = { + { "OTG_VERT_COUNT_NOM", 0, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_STATUS_FRAME_COUNT[] = { + { "OTG_FRAME_COUNT", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_STATUS_VF_COUNT[] = { + { "OTG_VF_COUNT", 0, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_STATUS_HV_COUNT[] = { + { "OTG_HV_COUNT", 0, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_COUNT_CONTROL[] = { + { "OTG_HORZ_COUNT_BY2_EN", 0, 0, &umr_bitfield_default }, + { "OTG_HORZ_REPETITION_COUNT", 1, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_COUNT_RESET[] = { + { "OTG_RESET_FRAME_COUNT", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE[] = { + { "OTG_MANUAL_FORCE_VSYNC_NEXT_LINE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_VERT_SYNC_CONTROL[] = { + { "OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED", 0, 0, &umr_bitfield_default }, + { "OTG_FORCE_VSYNC_NEXT_LINE_CLEAR", 8, 8, &umr_bitfield_default }, + { "OTG_AUTO_FORCE_VSYNC_MODE", 16, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_STEREO_STATUS[] = { + { "OTG_STEREO_CURRENT_EYE", 0, 0, &umr_bitfield_default }, + { "OTG_STEREO_SYNC_OUTPUT", 8, 8, &umr_bitfield_default }, + { "OTG_STEREO_SYNC_SELECT", 16, 16, &umr_bitfield_default }, + { "OTG_STEREO_EYE_FLAG", 20, 20, &umr_bitfield_default }, + { "OTG_STEREO_FORCE_NEXT_EYE_PENDING", 24, 25, &umr_bitfield_default }, + { "OTG_CURRENT_3D_STRUCTURE_STATE", 30, 30, &umr_bitfield_default }, + { "OTG_CURRENT_STEREOSYNC_EN_STATE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_STEREO_CONTROL[] = { + { "OTG_STEREO_SYNC_OUTPUT_LINE_NUM", 0, 14, &umr_bitfield_default }, + { "OTG_STEREO_SYNC_OUTPUT_POLARITY", 15, 15, &umr_bitfield_default }, + { "OTG_STEREO_EYE_FLAG_POLARITY", 17, 17, &umr_bitfield_default }, + { "OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP", 18, 18, &umr_bitfield_default }, + { "OTG_DISABLE_FIELD_NUM", 19, 19, &umr_bitfield_default }, + { "OTG_DISABLE_V_BLANK_FOR_DP_FIX", 20, 20, &umr_bitfield_default }, + { "OTG_STEREO_EN", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_SNAPSHOT_STATUS[] = { + { "OTG_SNAPSHOT_OCCURRED", 0, 0, &umr_bitfield_default }, + { "OTG_SNAPSHOT_CLEAR", 1, 1, &umr_bitfield_default }, + { "OTG_SNAPSHOT_MANUAL_TRIGGER", 2, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_SNAPSHOT_CONTROL[] = { + { "OTG_AUTO_SNAPSHOT_TRIG_SEL", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_SNAPSHOT_POSITION[] = { + { "OTG_SNAPSHOT_VERT_COUNT", 0, 14, &umr_bitfield_default }, + { "OTG_SNAPSHOT_HORZ_COUNT", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_SNAPSHOT_FRAME[] = { + { "OTG_SNAPSHOT_FRAME_COUNT", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_INTERRUPT_CONTROL[] = { + { "OTG_SNAPSHOT_INT_MSK", 0, 0, &umr_bitfield_default }, + { "OTG_SNAPSHOT_INT_TYPE", 1, 1, &umr_bitfield_default }, + { "OTG_FORCE_COUNT_NOW_INT_MSK", 8, 8, &umr_bitfield_default }, + { "OTG_FORCE_COUNT_NOW_INT_TYPE", 9, 9, &umr_bitfield_default }, + { "OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK", 16, 16, &umr_bitfield_default }, + { "OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE", 17, 17, &umr_bitfield_default }, + { "OTG_TRIGA_INT_MSK", 24, 24, &umr_bitfield_default }, + { "OTG_TRIGB_INT_MSK", 25, 25, &umr_bitfield_default }, + { "OTG_TRIGA_INT_TYPE", 26, 26, &umr_bitfield_default }, + { "OTG_TRIGB_INT_TYPE", 27, 27, &umr_bitfield_default }, + { "OTG_VSYNC_NOM_INT_MSK", 28, 28, &umr_bitfield_default }, + { "OTG_VSYNC_NOM_INT_TYPE", 29, 29, &umr_bitfield_default }, + { "OTG_GSL_VSYNC_GAP_INT_MSK", 30, 30, &umr_bitfield_default }, + { "OTG_GSL_VSYNC_GAP_INT_TYPE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_UPDATE_LOCK[] = { + { "OTG_UPDATE_LOCK", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_DOUBLE_BUFFER_CONTROL[] = { + { "OTG_UPDATE_PENDING", 0, 0, &umr_bitfield_default }, + { "OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING", 2, 2, &umr_bitfield_default }, + { "OTG_BLANK_DATA_EN_UPDATE_PENDING", 3, 3, &umr_bitfield_default }, + { "OTG_RANGE_TIMING_DBUF_UPDATE_PENDING", 4, 4, &umr_bitfield_default }, + { "OTG_TIMING_DB_UPDATE_PENDING", 5, 5, &umr_bitfield_default }, + { "OTG_3D_CTRL_DB_UPDATE_PENDING", 6, 6, &umr_bitfield_default }, + { "OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING", 7, 7, &umr_bitfield_default }, + { "OTG_UPDATE_INSTANTLY", 8, 8, &umr_bitfield_default }, + { "OTG_BLANK_DATA_DOUBLE_BUFFER_EN", 16, 16, &umr_bitfield_default }, + { "OTG_RANGE_TIMING_DBUF_UPDATE_MODE", 24, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_TEST_PATTERN_CONTROL[] = { + { "OTG_TEST_PATTERN_EN", 0, 0, &umr_bitfield_default }, + { "OTG_TEST_PATTERN_MODE", 8, 10, &umr_bitfield_default }, + { "OTG_TEST_PATTERN_DYNAMIC_RANGE", 16, 16, &umr_bitfield_default }, + { "OTG_TEST_PATTERN_COLOR_FORMAT", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_TEST_PATTERN_PARAMETERS[] = { + { "OTG_TEST_PATTERN_INC0", 0, 3, &umr_bitfield_default }, + { "OTG_TEST_PATTERN_INC1", 4, 7, &umr_bitfield_default }, + { "OTG_TEST_PATTERN_VRES", 8, 11, &umr_bitfield_default }, + { "OTG_TEST_PATTERN_HRES", 12, 15, &umr_bitfield_default }, + { "OTG_TEST_PATTERN_RAMP0_OFFSET", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_TEST_PATTERN_COLOR[] = { + { "OTG_TEST_PATTERN_DATA", 0, 15, &umr_bitfield_default }, + { "OTG_TEST_PATTERN_MASK", 16, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_MASTER_EN[] = { + { "OTG_MASTER_EN", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_BLANK_DATA_COLOR[] = { + { "OTG_BLANK_DATA_COLOR_BLUE_CB", 0, 9, &umr_bitfield_default }, + { "OTG_BLANK_DATA_COLOR_GREEN_Y", 10, 19, &umr_bitfield_default }, + { "OTG_BLANK_DATA_COLOR_RED_CR", 20, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_BLANK_DATA_COLOR_EXT[] = { + { "OTG_BLANK_DATA_COLOR_BLUE_CB_EXT", 0, 5, &umr_bitfield_default }, + { "OTG_BLANK_DATA_COLOR_GREEN_Y_EXT", 8, 13, &umr_bitfield_default }, + { "OTG_BLANK_DATA_COLOR_RED_CR_EXT", 16, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_BLACK_COLOR[] = { + { "OTG_BLACK_COLOR_B_CB", 0, 9, &umr_bitfield_default }, + { "OTG_BLACK_COLOR_G_Y", 10, 19, &umr_bitfield_default }, + { "OTG_BLACK_COLOR_R_CR", 20, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_BLACK_COLOR_EXT[] = { + { "OTG_BLACK_COLOR_B_CB_EXT", 0, 5, &umr_bitfield_default }, + { "OTG_BLACK_COLOR_G_Y_EXT", 8, 13, &umr_bitfield_default }, + { "OTG_BLACK_COLOR_R_CR_EXT", 16, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_VERTICAL_INTERRUPT0_POSITION[] = { + { "OTG_VERTICAL_INTERRUPT0_LINE_START", 0, 14, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT0_LINE_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL[] = { + { "OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY", 4, 4, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT0_INT_ENABLE", 8, 8, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT0_STATUS", 12, 12, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT0_INT_STATUS", 16, 16, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT0_CLEAR", 20, 20, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT0_INT_TYPE", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_VERTICAL_INTERRUPT1_POSITION[] = { + { "OTG_VERTICAL_INTERRUPT1_LINE_START", 0, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL[] = { + { "OTG_VERTICAL_INTERRUPT1_INT_ENABLE", 8, 8, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT1_STATUS", 12, 12, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT1_INT_STATUS", 16, 16, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT1_CLEAR", 20, 20, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT1_INT_TYPE", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_VERTICAL_INTERRUPT2_POSITION[] = { + { "OTG_VERTICAL_INTERRUPT2_LINE_START", 0, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL[] = { + { "OTG_VERTICAL_INTERRUPT2_INT_ENABLE", 8, 8, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT2_STATUS", 12, 12, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT2_INT_STATUS", 16, 16, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT2_CLEAR", 20, 20, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT2_INT_TYPE", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_CRC_CNTL[] = { + { "OTG_CRC_EN", 0, 0, &umr_bitfield_default }, + { "OTG_CRC_DUAL_LINK_EN", 1, 1, &umr_bitfield_default }, + { "OTG_CRC_DUAL_LINK_MODE", 2, 2, &umr_bitfield_default }, + { "OTG_CRC_BLANK_ONLY", 3, 3, &umr_bitfield_default }, + { "OTG_CRC_CONT_EN", 4, 4, &umr_bitfield_default }, + { "OTG_CRC_CAPTURE_START_SEL", 5, 6, &umr_bitfield_default }, + { "OTG_CRC_STEREO_MODE", 8, 9, &umr_bitfield_default }, + { "OTG_CRC_INTERLACE_MODE", 12, 13, &umr_bitfield_default }, + { "OTG_CRC_MULTI_STREAM_MODE", 16, 18, &umr_bitfield_default }, + { "OTG_CRC_USE_NEW_AND_REPEATED_PIXELS", 19, 19, &umr_bitfield_default }, + { "OTG_CRC0_SELECT", 20, 22, &umr_bitfield_default }, + { "OTG_CRC1_SELECT", 24, 26, &umr_bitfield_default }, + { "OTG_ONE_SHOT_CRC0_PENDING", 28, 28, &umr_bitfield_default }, + { "OTG_ONE_SHOT_CRC1_PENDING", 29, 29, &umr_bitfield_default }, + { "OTG_ONE_SHOT_CRC2_PENDING", 30, 30, &umr_bitfield_default }, + { "OTG_ONE_SHOT_CRC3_PENDING", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_CRC0_WINDOWA_X_CONTROL[] = { + { "OTG_CRC0_WINDOWA_X_START", 0, 14, &umr_bitfield_default }, + { "OTG_CRC0_WINDOWA_X_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_CRC0_WINDOWA_Y_CONTROL[] = { + { "OTG_CRC0_WINDOWA_Y_START", 0, 14, &umr_bitfield_default }, + { "OTG_CRC0_WINDOWA_Y_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_CRC0_WINDOWB_X_CONTROL[] = { + { "OTG_CRC0_WINDOWB_X_START", 0, 14, &umr_bitfield_default }, + { "OTG_CRC0_WINDOWB_X_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_CRC0_WINDOWB_Y_CONTROL[] = { + { "OTG_CRC0_WINDOWB_Y_START", 0, 14, &umr_bitfield_default }, + { "OTG_CRC0_WINDOWB_Y_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_CRC0_DATA_RG[] = { + { "CRC0_R_CR", 0, 15, &umr_bitfield_default }, + { "CRC0_G_Y", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_CRC0_DATA_B[] = { + { "CRC0_B_CB", 0, 15, &umr_bitfield_default }, + { "CRC0_C", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_CRC1_WINDOWA_X_CONTROL[] = { + { "OTG_CRC1_WINDOWA_X_START", 0, 14, &umr_bitfield_default }, + { "OTG_CRC1_WINDOWA_X_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_CRC1_WINDOWA_Y_CONTROL[] = { + { "OTG_CRC1_WINDOWA_Y_START", 0, 14, &umr_bitfield_default }, + { "OTG_CRC1_WINDOWA_Y_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_CRC1_WINDOWB_X_CONTROL[] = { + { "OTG_CRC1_WINDOWB_X_START", 0, 14, &umr_bitfield_default }, + { "OTG_CRC1_WINDOWB_X_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_CRC1_WINDOWB_Y_CONTROL[] = { + { "OTG_CRC1_WINDOWB_Y_START", 0, 14, &umr_bitfield_default }, + { "OTG_CRC1_WINDOWB_Y_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_CRC1_DATA_RG[] = { + { "CRC1_R_CR", 0, 15, &umr_bitfield_default }, + { "CRC1_G_Y", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_CRC1_DATA_B[] = { + { "CRC1_B_CB", 0, 15, &umr_bitfield_default }, + { "CRC1_C", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_CRC2_DATA_RG[] = { + { "CRC2_R_CR", 0, 15, &umr_bitfield_default }, + { "CRC2_G_Y", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_CRC2_DATA_B[] = { + { "CRC2_B_CB", 0, 15, &umr_bitfield_default }, + { "CRC2_C", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_CRC3_DATA_RG[] = { + { "CRC3_R_CR", 0, 15, &umr_bitfield_default }, + { "CRC3_G_Y", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_CRC3_DATA_B[] = { + { "CRC3_B_CB", 0, 15, &umr_bitfield_default }, + { "CRC3_C", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_CRC_SIG_RED_GREEN_MASK[] = { + { "OTG_CRC_SIG_RED_MASK", 0, 15, &umr_bitfield_default }, + { "OTG_CRC_SIG_GREEN_MASK", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK[] = { + { "OTG_CRC_SIG_BLUE_MASK", 0, 15, &umr_bitfield_default }, + { "OTG_CRC_SIG_CONTROL_MASK", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_STATIC_SCREEN_CONTROL[] = { + { "OTG_STATIC_SCREEN_EVENT_MASK", 0, 15, &umr_bitfield_default }, + { "OTG_STATIC_SCREEN_FRAME_COUNT", 16, 23, &umr_bitfield_default }, + { "OTG_CPU_SS_INT_ENABLE", 24, 24, &umr_bitfield_default }, + { "OTG_SS_STATUS", 25, 25, &umr_bitfield_default }, + { "OTG_CPU_SS_INT_STATUS", 26, 26, &umr_bitfield_default }, + { "OTG_CPU_SS_INT_CLEAR", 27, 27, &umr_bitfield_default }, + { "OTG_CPU_SS_INT_TYPE", 28, 28, &umr_bitfield_default }, + { "OTG_STATIC_SCREEN_OVERRIDE", 30, 30, &umr_bitfield_default }, + { "OTG_STATIC_SCREEN_OVERRIDE_VALUE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_3D_STRUCTURE_CONTROL[] = { + { "OTG_3D_STRUCTURE_EN", 0, 0, &umr_bitfield_default }, + { "OTG_3D_STRUCTURE_V_UPDATE_MODE", 8, 9, &umr_bitfield_default }, + { "OTG_3D_STRUCTURE_STEREO_SEL_OVR", 12, 12, &umr_bitfield_default }, + { "OTG_3D_STRUCTURE_F_COUNT_RESET", 16, 16, &umr_bitfield_default }, + { "OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING", 17, 17, &umr_bitfield_default }, + { "OTG_3D_STRUCTURE_F_COUNT", 18, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_GSL_VSYNC_GAP[] = { + { "OTG_GSL_VSYNC_GAP_LIMIT", 0, 7, &umr_bitfield_default }, + { "OTG_GSL_VSYNC_GAP_DELAY", 8, 15, &umr_bitfield_default }, + { "OTG_GSL_VSYNC_GAP_SOURCE_SEL", 16, 16, &umr_bitfield_default }, + { "OTG_GSL_VSYNC_GAP_MODE", 17, 18, &umr_bitfield_default }, + { "OTG_GSL_VSYNC_GAP_CLEAR", 19, 19, &umr_bitfield_default }, + { "OTG_GSL_VSYNC_GAP_OCCURRED", 20, 20, &umr_bitfield_default }, + { "OTG_GSL_VSYNC_GAP_MASTER_FASTER", 23, 23, &umr_bitfield_default }, + { "OTG_GSL_VSYNC_GAP", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_MASTER_UPDATE_MODE[] = { + { "MASTER_UPDATE_INTERLACED_MODE", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_CLOCK_CONTROL[] = { + { "OTG_CLOCK_EN", 0, 0, &umr_bitfield_default }, + { "OTG_CLOCK_GATE_DIS", 1, 1, &umr_bitfield_default }, + { "OTG_SOFT_RESET", 4, 4, &umr_bitfield_default }, + { "OTG_CLOCK_ON", 8, 8, &umr_bitfield_default }, + { "OTG_BUSY", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_VSTARTUP_PARAM[] = { + { "VSTARTUP_START", 0, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_VUPDATE_PARAM[] = { + { "VUPDATE_OFFSET", 0, 15, &umr_bitfield_default }, + { "VUPDATE_WIDTH", 16, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_VREADY_PARAM[] = { + { "VREADY_OFFSET", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_GLOBAL_SYNC_STATUS[] = { + { "VSTARTUP_INT_EN", 0, 0, &umr_bitfield_default }, + { "VSTARTUP_INT_TYPE", 1, 1, &umr_bitfield_default }, + { "VSTARTUP_EVENT_OCCURRED", 2, 2, &umr_bitfield_default }, + { "VSTARTUP_INT_STATUS", 3, 3, &umr_bitfield_default }, + { "VSTARTUP_EVENT_CLEAR", 4, 4, &umr_bitfield_default }, + { "VUPDATE_INT_EN", 5, 5, &umr_bitfield_default }, + { "VUPDATE_INT_TYPE", 6, 6, &umr_bitfield_default }, + { "VUPDATE_INT_POSITION_SEL", 7, 7, &umr_bitfield_default }, + { "VUPDATE_EVENT_OCCURRED", 8, 8, &umr_bitfield_default }, + { "VUPDATE_INT_STATUS", 9, 9, &umr_bitfield_default }, + { "VUPDATE_EVENT_CLEAR", 10, 10, &umr_bitfield_default }, + { "VUPDATE_STATUS", 11, 11, &umr_bitfield_default }, + { "VUPDATE_NO_LOCK_INT_EN", 12, 12, &umr_bitfield_default }, + { "VUPDATE_NO_LOCK_INT_TYPE", 13, 13, &umr_bitfield_default }, + { "VUPDATE_NO_LOCK_EVENT_OCCURRED", 14, 14, &umr_bitfield_default }, + { "VUPDATE_NO_LOCK_INT_STATUS", 15, 15, &umr_bitfield_default }, + { "VUPDATE_NO_LOCK_EVENT_CLEAR", 16, 16, &umr_bitfield_default }, + { "VUPDATE_NO_LOCK_STATUS", 17, 17, &umr_bitfield_default }, + { "VREADY_INT_EN", 18, 18, &umr_bitfield_default }, + { "VREADY_INT_TYPE", 19, 19, &umr_bitfield_default }, + { "VREADY_EVENT_OCCURRED", 20, 20, &umr_bitfield_default }, + { "VREADY_INT_STATUS", 21, 21, &umr_bitfield_default }, + { "VREADY_EVENT_CLEAR", 22, 22, &umr_bitfield_default }, + { "STEREO_SELECT_STATUS", 24, 24, &umr_bitfield_default }, + { "FIELD_NUMBER_STATUS", 25, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_MASTER_UPDATE_LOCK[] = { + { "OTG_MASTER_UPDATE_LOCK", 0, 0, &umr_bitfield_default }, + { "UPDATE_LOCK_STATUS", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_GSL_CONTROL[] = { + { "OTG_GSL0_EN", 0, 0, &umr_bitfield_default }, + { "OTG_GSL1_EN", 1, 1, &umr_bitfield_default }, + { "OTG_GSL2_EN", 2, 2, &umr_bitfield_default }, + { "OTG_GSL_MASTER_EN", 3, 3, &umr_bitfield_default }, + { "OTG_GSL_FORCE_DELAY", 16, 20, &umr_bitfield_default }, + { "OTG_GSL_CHECK_ALL_FIELDS", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_GSL_WINDOW_X[] = { + { "OTG_GSL_WINDOW_START_X", 0, 14, &umr_bitfield_default }, + { "OTG_GSL_WINDOW_END_X", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_GSL_WINDOW_Y[] = { + { "OTG_GSL_WINDOW_START_Y", 0, 14, &umr_bitfield_default }, + { "OTG_GSL_WINDOW_END_Y", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_VUPDATE_KEEPOUT[] = { + { "MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET", 0, 15, &umr_bitfield_default }, + { "MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET", 16, 25, &umr_bitfield_default }, + { "OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_GLOBAL_CONTROL0[] = { + { "OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT", 0, 7, &umr_bitfield_default }, + { "OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN", 8, 8, &umr_bitfield_default }, + { "OTG_MASTER_UPDATE_LOCK_SEL", 25, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_GLOBAL_CONTROL1[] = { + { "MASTER_UPDATE_LOCK_DB_X", 0, 14, &umr_bitfield_default }, + { "MASTER_UPDATE_LOCK_DB_Y", 16, 30, &umr_bitfield_default }, + { "MASTER_UPDATE_LOCK_DB_EN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_GLOBAL_CONTROL2[] = { + { "DIG_UPDATE_LOCATION", 0, 9, &umr_bitfield_default }, + { "GLOBAL_UPDATE_LOCK_EN", 10, 10, &umr_bitfield_default }, + { "MANUAL_FLOW_CONTROL_SEL", 16, 18, &umr_bitfield_default }, + { "DCCG_VUPDATE_MODE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_GLOBAL_CONTROL3[] = { + { "MASTER_UPDATE_LOCK_DB_FIELD", 0, 1, &umr_bitfield_default }, + { "MASTER_UPDATE_LOCK_DB_STEREO_SEL", 4, 5, &umr_bitfield_default }, + { "MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_TRIG_MANUAL_CONTROL[] = { + { "TRIG_MANUAL_CONTROL", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_MANUAL_FLOW_CONTROL[] = { + { "MANUAL_FLOW_CONTROL", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_RANGE_TIMING_INT_STATUS[] = { + { "OTG_RANGE_TIMING_UPDATE_OCCURRED", 0, 0, &umr_bitfield_default }, + { "OTG_RANGE_TIMING_UPDATE_OCCURRED_INT", 4, 4, &umr_bitfield_default }, + { "OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR", 8, 8, &umr_bitfield_default }, + { "OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK", 12, 12, &umr_bitfield_default }, + { "OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_DRR_CONTROL[] = { + { "OTG_DRR_AVERAGE_FRAME", 0, 2, &umr_bitfield_default }, + { "OTG_V_TOTAL_LAST_USED_BY_DRR", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_REQUEST_CONTROL[] = { + { "OTG_REQUEST_MODE_FOR_H_DUPLICATE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG3_OTG_SPARE_REGISTER[] = { + { "OTG_SPARE_REG", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_H_TOTAL[] = { + { "OTG_H_TOTAL", 0, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_H_BLANK_START_END[] = { + { "OTG_H_BLANK_START", 0, 14, &umr_bitfield_default }, + { "OTG_H_BLANK_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_H_SYNC_A[] = { + { "OTG_H_SYNC_A_START", 0, 14, &umr_bitfield_default }, + { "OTG_H_SYNC_A_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_H_SYNC_A_CNTL[] = { + { "OTG_H_SYNC_A_POL", 0, 0, &umr_bitfield_default }, + { "OTG_COMP_SYNC_A_EN", 16, 16, &umr_bitfield_default }, + { "OTG_H_SYNC_A_CUTOFF", 17, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_H_TIMING_CNTL[] = { + { "OTG_H_TIMING_DIV_BY2", 0, 0, &umr_bitfield_default }, + { "OTG_H_TIMING_DIV_BY2_UPDATE_MODE", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_V_TOTAL[] = { + { "OTG_V_TOTAL", 0, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_V_TOTAL_MIN[] = { + { "OTG_V_TOTAL_MIN", 0, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_V_TOTAL_MAX[] = { + { "OTG_V_TOTAL_MAX", 0, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_V_TOTAL_MID[] = { + { "OTG_V_TOTAL_MID", 0, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_V_TOTAL_CONTROL[] = { + { "OTG_V_TOTAL_MIN_SEL", 0, 0, &umr_bitfield_default }, + { "OTG_V_TOTAL_MAX_SEL", 1, 1, &umr_bitfield_default }, + { "OTG_VTOTAL_MID_REPLACING_MAX_EN", 2, 2, &umr_bitfield_default }, + { "OTG_VTOTAL_MID_REPLACING_MIN_EN", 3, 3, &umr_bitfield_default }, + { "OTG_FORCE_LOCK_ON_EVENT", 4, 4, &umr_bitfield_default }, + { "OTG_SET_V_TOTAL_MIN_MASK_EN", 7, 7, &umr_bitfield_default }, + { "OTG_VTOTAL_MID_FRAME_NUM", 8, 15, &umr_bitfield_default }, + { "OTG_SET_V_TOTAL_MIN_MASK", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_V_TOTAL_INT_STATUS[] = { + { "OTG_SET_V_TOTAL_MIN_EVENT_OCCURED", 0, 0, &umr_bitfield_default }, + { "OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_INT", 4, 4, &umr_bitfield_default }, + { "OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK", 8, 8, &umr_bitfield_default }, + { "OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK", 12, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_VSYNC_NOM_INT_STATUS[] = { + { "OTG_VSYNC_NOM", 0, 0, &umr_bitfield_default }, + { "OTG_VSYNC_NOM_INT_CLEAR", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_V_BLANK_START_END[] = { + { "OTG_V_BLANK_START", 0, 14, &umr_bitfield_default }, + { "OTG_V_BLANK_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_V_SYNC_A[] = { + { "OTG_V_SYNC_A_START", 0, 14, &umr_bitfield_default }, + { "OTG_V_SYNC_A_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_V_SYNC_A_CNTL[] = { + { "OTG_V_SYNC_A_POL", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_TRIGA_CNTL[] = { + { "OTG_TRIGA_SOURCE_SELECT", 0, 4, &umr_bitfield_default }, + { "OTG_TRIGA_SOURCE_PIPE_SELECT", 5, 7, &umr_bitfield_default }, + { "OTG_TRIGA_POLARITY_SELECT", 8, 10, &umr_bitfield_default }, + { "OTG_TRIGA_RESYNC_BYPASS_EN", 11, 11, &umr_bitfield_default }, + { "OTG_TRIGA_INPUT_STATUS", 12, 12, &umr_bitfield_default }, + { "OTG_TRIGA_POLARITY_STATUS", 13, 13, &umr_bitfield_default }, + { "OTG_TRIGA_OCCURRED", 14, 14, &umr_bitfield_default }, + { "OTG_TRIGA_RISING_EDGE_DETECT_CNTL", 16, 17, &umr_bitfield_default }, + { "OTG_TRIGA_FALLING_EDGE_DETECT_CNTL", 18, 19, &umr_bitfield_default }, + { "OTG_TRIGA_FREQUENCY_SELECT", 20, 21, &umr_bitfield_default }, + { "OTG_TRIGA_DELAY", 24, 28, &umr_bitfield_default }, + { "OTG_TRIGA_CLEAR", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_TRIGA_MANUAL_TRIG[] = { + { "OTG_TRIGA_MANUAL_TRIG", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_TRIGB_CNTL[] = { + { "OTG_TRIGB_SOURCE_SELECT", 0, 4, &umr_bitfield_default }, + { "OTG_TRIGB_SOURCE_PIPE_SELECT", 5, 7, &umr_bitfield_default }, + { "OTG_TRIGB_POLARITY_SELECT", 8, 10, &umr_bitfield_default }, + { "OTG_TRIGB_RESYNC_BYPASS_EN", 11, 11, &umr_bitfield_default }, + { "OTG_TRIGB_INPUT_STATUS", 12, 12, &umr_bitfield_default }, + { "OTG_TRIGB_POLARITY_STATUS", 13, 13, &umr_bitfield_default }, + { "OTG_TRIGB_OCCURRED", 14, 14, &umr_bitfield_default }, + { "OTG_TRIGB_RISING_EDGE_DETECT_CNTL", 16, 17, &umr_bitfield_default }, + { "OTG_TRIGB_FALLING_EDGE_DETECT_CNTL", 18, 19, &umr_bitfield_default }, + { "OTG_TRIGB_FREQUENCY_SELECT", 20, 21, &umr_bitfield_default }, + { "OTG_TRIGB_DELAY", 24, 28, &umr_bitfield_default }, + { "OTG_TRIGB_CLEAR", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_TRIGB_MANUAL_TRIG[] = { + { "OTG_TRIGB_MANUAL_TRIG", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_FORCE_COUNT_NOW_CNTL[] = { + { "OTG_FORCE_COUNT_NOW_MODE", 0, 1, &umr_bitfield_default }, + { "OTG_FORCE_COUNT_NOW_CHECK", 4, 4, &umr_bitfield_default }, + { "OTG_FORCE_COUNT_NOW_TRIG_SEL", 8, 8, &umr_bitfield_default }, + { "OTG_FORCE_COUNT_NOW_OCCURRED", 16, 16, &umr_bitfield_default }, + { "OTG_FORCE_COUNT_NOW_CLEAR", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_FLOW_CONTROL[] = { + { "OTG_FLOW_CONTROL_SOURCE_SELECT", 0, 4, &umr_bitfield_default }, + { "OTG_FLOW_CONTROL_POLARITY", 8, 8, &umr_bitfield_default }, + { "OTG_FLOW_CONTROL_GRANULARITY", 16, 16, &umr_bitfield_default }, + { "OTG_FLOW_CONTROL_INPUT_STATUS", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_STEREO_FORCE_NEXT_EYE[] = { + { "OTG_STEREO_FORCE_NEXT_EYE", 0, 1, &umr_bitfield_default }, + { "OTG_AVSYNC_FRAME_COUNTER", 8, 15, &umr_bitfield_default }, + { "OTG_AVSYNC_LINE_COUNTER", 16, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_AVSYNC_COUNTER[] = { + { "OTG_AVSYNC_COUNTER", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_CONTROL[] = { + { "OTG_MASTER_EN", 0, 0, &umr_bitfield_default }, + { "OTG_DISABLE_POINT_CNTL", 8, 9, &umr_bitfield_default }, + { "OTG_START_POINT_CNTL", 12, 12, &umr_bitfield_default }, + { "OTG_FIELD_NUMBER_CNTL", 13, 13, &umr_bitfield_default }, + { "OTG_FIELD_NUMBER_POLARITY", 14, 14, &umr_bitfield_default }, + { "OTG_CURRENT_MASTER_EN_STATE", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_BLANK_CONTROL[] = { + { "OTG_CURRENT_BLANK_STATE", 0, 0, &umr_bitfield_default }, + { "OTG_BLANK_DATA_EN", 8, 8, &umr_bitfield_default }, + { "OTG_BLANK_DE_MODE", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_PIPE_ABORT_CONTROL[] = { + { "OTG_PIPE_ABORT", 0, 0, &umr_bitfield_default }, + { "OTG_PIPE_ABORT_DONE", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_INTERLACE_CONTROL[] = { + { "OTG_INTERLACE_ENABLE", 0, 0, &umr_bitfield_default }, + { "OTG_INTERLACE_FORCE_NEXT_FIELD", 16, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_INTERLACE_STATUS[] = { + { "OTG_INTERLACE_CURRENT_FIELD", 0, 0, &umr_bitfield_default }, + { "OTG_INTERLACE_NEXT_FIELD", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_FIELD_INDICATION_CONTROL[] = { + { "OTG_FIELD_INDICATION_OUTPUT_POLARITY", 0, 0, &umr_bitfield_default }, + { "OTG_FIELD_ALIGNMENT", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_PIXEL_DATA_READBACK0[] = { + { "OTG_PIXEL_DATA_BLUE_CB", 0, 15, &umr_bitfield_default }, + { "OTG_PIXEL_DATA_GREEN_Y", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_PIXEL_DATA_READBACK1[] = { + { "OTG_PIXEL_DATA_RED_CR", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_STATUS[] = { + { "OTG_V_BLANK", 0, 0, &umr_bitfield_default }, + { "OTG_V_ACTIVE_DISP", 1, 1, &umr_bitfield_default }, + { "OTG_V_SYNC_A", 2, 2, &umr_bitfield_default }, + { "OTG_V_UPDATE", 3, 3, &umr_bitfield_default }, + { "OTG_V_BLANK_3D_STRUCTURE", 5, 5, &umr_bitfield_default }, + { "OTG_H_BLANK", 16, 16, &umr_bitfield_default }, + { "OTG_H_ACTIVE_DISP", 17, 17, &umr_bitfield_default }, + { "OTG_H_SYNC_A", 18, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_STATUS_POSITION[] = { + { "OTG_VERT_COUNT", 0, 14, &umr_bitfield_default }, + { "OTG_HORZ_COUNT", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_NOM_VERT_POSITION[] = { + { "OTG_VERT_COUNT_NOM", 0, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_STATUS_FRAME_COUNT[] = { + { "OTG_FRAME_COUNT", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_STATUS_VF_COUNT[] = { + { "OTG_VF_COUNT", 0, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_STATUS_HV_COUNT[] = { + { "OTG_HV_COUNT", 0, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_COUNT_CONTROL[] = { + { "OTG_HORZ_COUNT_BY2_EN", 0, 0, &umr_bitfield_default }, + { "OTG_HORZ_REPETITION_COUNT", 1, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_COUNT_RESET[] = { + { "OTG_RESET_FRAME_COUNT", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE[] = { + { "OTG_MANUAL_FORCE_VSYNC_NEXT_LINE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_VERT_SYNC_CONTROL[] = { + { "OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED", 0, 0, &umr_bitfield_default }, + { "OTG_FORCE_VSYNC_NEXT_LINE_CLEAR", 8, 8, &umr_bitfield_default }, + { "OTG_AUTO_FORCE_VSYNC_MODE", 16, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_STEREO_STATUS[] = { + { "OTG_STEREO_CURRENT_EYE", 0, 0, &umr_bitfield_default }, + { "OTG_STEREO_SYNC_OUTPUT", 8, 8, &umr_bitfield_default }, + { "OTG_STEREO_SYNC_SELECT", 16, 16, &umr_bitfield_default }, + { "OTG_STEREO_EYE_FLAG", 20, 20, &umr_bitfield_default }, + { "OTG_STEREO_FORCE_NEXT_EYE_PENDING", 24, 25, &umr_bitfield_default }, + { "OTG_CURRENT_3D_STRUCTURE_STATE", 30, 30, &umr_bitfield_default }, + { "OTG_CURRENT_STEREOSYNC_EN_STATE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_STEREO_CONTROL[] = { + { "OTG_STEREO_SYNC_OUTPUT_LINE_NUM", 0, 14, &umr_bitfield_default }, + { "OTG_STEREO_SYNC_OUTPUT_POLARITY", 15, 15, &umr_bitfield_default }, + { "OTG_STEREO_EYE_FLAG_POLARITY", 17, 17, &umr_bitfield_default }, + { "OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP", 18, 18, &umr_bitfield_default }, + { "OTG_DISABLE_FIELD_NUM", 19, 19, &umr_bitfield_default }, + { "OTG_DISABLE_V_BLANK_FOR_DP_FIX", 20, 20, &umr_bitfield_default }, + { "OTG_STEREO_EN", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_SNAPSHOT_STATUS[] = { + { "OTG_SNAPSHOT_OCCURRED", 0, 0, &umr_bitfield_default }, + { "OTG_SNAPSHOT_CLEAR", 1, 1, &umr_bitfield_default }, + { "OTG_SNAPSHOT_MANUAL_TRIGGER", 2, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_SNAPSHOT_CONTROL[] = { + { "OTG_AUTO_SNAPSHOT_TRIG_SEL", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_SNAPSHOT_POSITION[] = { + { "OTG_SNAPSHOT_VERT_COUNT", 0, 14, &umr_bitfield_default }, + { "OTG_SNAPSHOT_HORZ_COUNT", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_SNAPSHOT_FRAME[] = { + { "OTG_SNAPSHOT_FRAME_COUNT", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_INTERRUPT_CONTROL[] = { + { "OTG_SNAPSHOT_INT_MSK", 0, 0, &umr_bitfield_default }, + { "OTG_SNAPSHOT_INT_TYPE", 1, 1, &umr_bitfield_default }, + { "OTG_FORCE_COUNT_NOW_INT_MSK", 8, 8, &umr_bitfield_default }, + { "OTG_FORCE_COUNT_NOW_INT_TYPE", 9, 9, &umr_bitfield_default }, + { "OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK", 16, 16, &umr_bitfield_default }, + { "OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE", 17, 17, &umr_bitfield_default }, + { "OTG_TRIGA_INT_MSK", 24, 24, &umr_bitfield_default }, + { "OTG_TRIGB_INT_MSK", 25, 25, &umr_bitfield_default }, + { "OTG_TRIGA_INT_TYPE", 26, 26, &umr_bitfield_default }, + { "OTG_TRIGB_INT_TYPE", 27, 27, &umr_bitfield_default }, + { "OTG_VSYNC_NOM_INT_MSK", 28, 28, &umr_bitfield_default }, + { "OTG_VSYNC_NOM_INT_TYPE", 29, 29, &umr_bitfield_default }, + { "OTG_GSL_VSYNC_GAP_INT_MSK", 30, 30, &umr_bitfield_default }, + { "OTG_GSL_VSYNC_GAP_INT_TYPE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_UPDATE_LOCK[] = { + { "OTG_UPDATE_LOCK", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_DOUBLE_BUFFER_CONTROL[] = { + { "OTG_UPDATE_PENDING", 0, 0, &umr_bitfield_default }, + { "OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING", 2, 2, &umr_bitfield_default }, + { "OTG_BLANK_DATA_EN_UPDATE_PENDING", 3, 3, &umr_bitfield_default }, + { "OTG_RANGE_TIMING_DBUF_UPDATE_PENDING", 4, 4, &umr_bitfield_default }, + { "OTG_TIMING_DB_UPDATE_PENDING", 5, 5, &umr_bitfield_default }, + { "OTG_3D_CTRL_DB_UPDATE_PENDING", 6, 6, &umr_bitfield_default }, + { "OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING", 7, 7, &umr_bitfield_default }, + { "OTG_UPDATE_INSTANTLY", 8, 8, &umr_bitfield_default }, + { "OTG_BLANK_DATA_DOUBLE_BUFFER_EN", 16, 16, &umr_bitfield_default }, + { "OTG_RANGE_TIMING_DBUF_UPDATE_MODE", 24, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_TEST_PATTERN_CONTROL[] = { + { "OTG_TEST_PATTERN_EN", 0, 0, &umr_bitfield_default }, + { "OTG_TEST_PATTERN_MODE", 8, 10, &umr_bitfield_default }, + { "OTG_TEST_PATTERN_DYNAMIC_RANGE", 16, 16, &umr_bitfield_default }, + { "OTG_TEST_PATTERN_COLOR_FORMAT", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_TEST_PATTERN_PARAMETERS[] = { + { "OTG_TEST_PATTERN_INC0", 0, 3, &umr_bitfield_default }, + { "OTG_TEST_PATTERN_INC1", 4, 7, &umr_bitfield_default }, + { "OTG_TEST_PATTERN_VRES", 8, 11, &umr_bitfield_default }, + { "OTG_TEST_PATTERN_HRES", 12, 15, &umr_bitfield_default }, + { "OTG_TEST_PATTERN_RAMP0_OFFSET", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_TEST_PATTERN_COLOR[] = { + { "OTG_TEST_PATTERN_DATA", 0, 15, &umr_bitfield_default }, + { "OTG_TEST_PATTERN_MASK", 16, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_MASTER_EN[] = { + { "OTG_MASTER_EN", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_BLANK_DATA_COLOR[] = { + { "OTG_BLANK_DATA_COLOR_BLUE_CB", 0, 9, &umr_bitfield_default }, + { "OTG_BLANK_DATA_COLOR_GREEN_Y", 10, 19, &umr_bitfield_default }, + { "OTG_BLANK_DATA_COLOR_RED_CR", 20, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_BLANK_DATA_COLOR_EXT[] = { + { "OTG_BLANK_DATA_COLOR_BLUE_CB_EXT", 0, 5, &umr_bitfield_default }, + { "OTG_BLANK_DATA_COLOR_GREEN_Y_EXT", 8, 13, &umr_bitfield_default }, + { "OTG_BLANK_DATA_COLOR_RED_CR_EXT", 16, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_BLACK_COLOR[] = { + { "OTG_BLACK_COLOR_B_CB", 0, 9, &umr_bitfield_default }, + { "OTG_BLACK_COLOR_G_Y", 10, 19, &umr_bitfield_default }, + { "OTG_BLACK_COLOR_R_CR", 20, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_BLACK_COLOR_EXT[] = { + { "OTG_BLACK_COLOR_B_CB_EXT", 0, 5, &umr_bitfield_default }, + { "OTG_BLACK_COLOR_G_Y_EXT", 8, 13, &umr_bitfield_default }, + { "OTG_BLACK_COLOR_R_CR_EXT", 16, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_VERTICAL_INTERRUPT0_POSITION[] = { + { "OTG_VERTICAL_INTERRUPT0_LINE_START", 0, 14, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT0_LINE_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_VERTICAL_INTERRUPT0_CONTROL[] = { + { "OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY", 4, 4, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT0_INT_ENABLE", 8, 8, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT0_STATUS", 12, 12, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT0_INT_STATUS", 16, 16, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT0_CLEAR", 20, 20, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT0_INT_TYPE", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_VERTICAL_INTERRUPT1_POSITION[] = { + { "OTG_VERTICAL_INTERRUPT1_LINE_START", 0, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_VERTICAL_INTERRUPT1_CONTROL[] = { + { "OTG_VERTICAL_INTERRUPT1_INT_ENABLE", 8, 8, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT1_STATUS", 12, 12, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT1_INT_STATUS", 16, 16, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT1_CLEAR", 20, 20, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT1_INT_TYPE", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_VERTICAL_INTERRUPT2_POSITION[] = { + { "OTG_VERTICAL_INTERRUPT2_LINE_START", 0, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_VERTICAL_INTERRUPT2_CONTROL[] = { + { "OTG_VERTICAL_INTERRUPT2_INT_ENABLE", 8, 8, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT2_STATUS", 12, 12, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT2_INT_STATUS", 16, 16, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT2_CLEAR", 20, 20, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT2_INT_TYPE", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_CRC_CNTL[] = { + { "OTG_CRC_EN", 0, 0, &umr_bitfield_default }, + { "OTG_CRC_DUAL_LINK_EN", 1, 1, &umr_bitfield_default }, + { "OTG_CRC_DUAL_LINK_MODE", 2, 2, &umr_bitfield_default }, + { "OTG_CRC_BLANK_ONLY", 3, 3, &umr_bitfield_default }, + { "OTG_CRC_CONT_EN", 4, 4, &umr_bitfield_default }, + { "OTG_CRC_CAPTURE_START_SEL", 5, 6, &umr_bitfield_default }, + { "OTG_CRC_STEREO_MODE", 8, 9, &umr_bitfield_default }, + { "OTG_CRC_INTERLACE_MODE", 12, 13, &umr_bitfield_default }, + { "OTG_CRC_MULTI_STREAM_MODE", 16, 18, &umr_bitfield_default }, + { "OTG_CRC_USE_NEW_AND_REPEATED_PIXELS", 19, 19, &umr_bitfield_default }, + { "OTG_CRC0_SELECT", 20, 22, &umr_bitfield_default }, + { "OTG_CRC1_SELECT", 24, 26, &umr_bitfield_default }, + { "OTG_ONE_SHOT_CRC0_PENDING", 28, 28, &umr_bitfield_default }, + { "OTG_ONE_SHOT_CRC1_PENDING", 29, 29, &umr_bitfield_default }, + { "OTG_ONE_SHOT_CRC2_PENDING", 30, 30, &umr_bitfield_default }, + { "OTG_ONE_SHOT_CRC3_PENDING", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_CRC0_WINDOWA_X_CONTROL[] = { + { "OTG_CRC0_WINDOWA_X_START", 0, 14, &umr_bitfield_default }, + { "OTG_CRC0_WINDOWA_X_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_CRC0_WINDOWA_Y_CONTROL[] = { + { "OTG_CRC0_WINDOWA_Y_START", 0, 14, &umr_bitfield_default }, + { "OTG_CRC0_WINDOWA_Y_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_CRC0_WINDOWB_X_CONTROL[] = { + { "OTG_CRC0_WINDOWB_X_START", 0, 14, &umr_bitfield_default }, + { "OTG_CRC0_WINDOWB_X_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_CRC0_WINDOWB_Y_CONTROL[] = { + { "OTG_CRC0_WINDOWB_Y_START", 0, 14, &umr_bitfield_default }, + { "OTG_CRC0_WINDOWB_Y_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_CRC0_DATA_RG[] = { + { "CRC0_R_CR", 0, 15, &umr_bitfield_default }, + { "CRC0_G_Y", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_CRC0_DATA_B[] = { + { "CRC0_B_CB", 0, 15, &umr_bitfield_default }, + { "CRC0_C", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_CRC1_WINDOWA_X_CONTROL[] = { + { "OTG_CRC1_WINDOWA_X_START", 0, 14, &umr_bitfield_default }, + { "OTG_CRC1_WINDOWA_X_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_CRC1_WINDOWA_Y_CONTROL[] = { + { "OTG_CRC1_WINDOWA_Y_START", 0, 14, &umr_bitfield_default }, + { "OTG_CRC1_WINDOWA_Y_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_CRC1_WINDOWB_X_CONTROL[] = { + { "OTG_CRC1_WINDOWB_X_START", 0, 14, &umr_bitfield_default }, + { "OTG_CRC1_WINDOWB_X_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_CRC1_WINDOWB_Y_CONTROL[] = { + { "OTG_CRC1_WINDOWB_Y_START", 0, 14, &umr_bitfield_default }, + { "OTG_CRC1_WINDOWB_Y_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_CRC1_DATA_RG[] = { + { "CRC1_R_CR", 0, 15, &umr_bitfield_default }, + { "CRC1_G_Y", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_CRC1_DATA_B[] = { + { "CRC1_B_CB", 0, 15, &umr_bitfield_default }, + { "CRC1_C", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_CRC2_DATA_RG[] = { + { "CRC2_R_CR", 0, 15, &umr_bitfield_default }, + { "CRC2_G_Y", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_CRC2_DATA_B[] = { + { "CRC2_B_CB", 0, 15, &umr_bitfield_default }, + { "CRC2_C", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_CRC3_DATA_RG[] = { + { "CRC3_R_CR", 0, 15, &umr_bitfield_default }, + { "CRC3_G_Y", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_CRC3_DATA_B[] = { + { "CRC3_B_CB", 0, 15, &umr_bitfield_default }, + { "CRC3_C", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_CRC_SIG_RED_GREEN_MASK[] = { + { "OTG_CRC_SIG_RED_MASK", 0, 15, &umr_bitfield_default }, + { "OTG_CRC_SIG_GREEN_MASK", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK[] = { + { "OTG_CRC_SIG_BLUE_MASK", 0, 15, &umr_bitfield_default }, + { "OTG_CRC_SIG_CONTROL_MASK", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_STATIC_SCREEN_CONTROL[] = { + { "OTG_STATIC_SCREEN_EVENT_MASK", 0, 15, &umr_bitfield_default }, + { "OTG_STATIC_SCREEN_FRAME_COUNT", 16, 23, &umr_bitfield_default }, + { "OTG_CPU_SS_INT_ENABLE", 24, 24, &umr_bitfield_default }, + { "OTG_SS_STATUS", 25, 25, &umr_bitfield_default }, + { "OTG_CPU_SS_INT_STATUS", 26, 26, &umr_bitfield_default }, + { "OTG_CPU_SS_INT_CLEAR", 27, 27, &umr_bitfield_default }, + { "OTG_CPU_SS_INT_TYPE", 28, 28, &umr_bitfield_default }, + { "OTG_STATIC_SCREEN_OVERRIDE", 30, 30, &umr_bitfield_default }, + { "OTG_STATIC_SCREEN_OVERRIDE_VALUE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_3D_STRUCTURE_CONTROL[] = { + { "OTG_3D_STRUCTURE_EN", 0, 0, &umr_bitfield_default }, + { "OTG_3D_STRUCTURE_V_UPDATE_MODE", 8, 9, &umr_bitfield_default }, + { "OTG_3D_STRUCTURE_STEREO_SEL_OVR", 12, 12, &umr_bitfield_default }, + { "OTG_3D_STRUCTURE_F_COUNT_RESET", 16, 16, &umr_bitfield_default }, + { "OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING", 17, 17, &umr_bitfield_default }, + { "OTG_3D_STRUCTURE_F_COUNT", 18, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_GSL_VSYNC_GAP[] = { + { "OTG_GSL_VSYNC_GAP_LIMIT", 0, 7, &umr_bitfield_default }, + { "OTG_GSL_VSYNC_GAP_DELAY", 8, 15, &umr_bitfield_default }, + { "OTG_GSL_VSYNC_GAP_SOURCE_SEL", 16, 16, &umr_bitfield_default }, + { "OTG_GSL_VSYNC_GAP_MODE", 17, 18, &umr_bitfield_default }, + { "OTG_GSL_VSYNC_GAP_CLEAR", 19, 19, &umr_bitfield_default }, + { "OTG_GSL_VSYNC_GAP_OCCURRED", 20, 20, &umr_bitfield_default }, + { "OTG_GSL_VSYNC_GAP_MASTER_FASTER", 23, 23, &umr_bitfield_default }, + { "OTG_GSL_VSYNC_GAP", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_MASTER_UPDATE_MODE[] = { + { "MASTER_UPDATE_INTERLACED_MODE", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_CLOCK_CONTROL[] = { + { "OTG_CLOCK_EN", 0, 0, &umr_bitfield_default }, + { "OTG_CLOCK_GATE_DIS", 1, 1, &umr_bitfield_default }, + { "OTG_SOFT_RESET", 4, 4, &umr_bitfield_default }, + { "OTG_CLOCK_ON", 8, 8, &umr_bitfield_default }, + { "OTG_BUSY", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_VSTARTUP_PARAM[] = { + { "VSTARTUP_START", 0, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_VUPDATE_PARAM[] = { + { "VUPDATE_OFFSET", 0, 15, &umr_bitfield_default }, + { "VUPDATE_WIDTH", 16, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_VREADY_PARAM[] = { + { "VREADY_OFFSET", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_GLOBAL_SYNC_STATUS[] = { + { "VSTARTUP_INT_EN", 0, 0, &umr_bitfield_default }, + { "VSTARTUP_INT_TYPE", 1, 1, &umr_bitfield_default }, + { "VSTARTUP_EVENT_OCCURRED", 2, 2, &umr_bitfield_default }, + { "VSTARTUP_INT_STATUS", 3, 3, &umr_bitfield_default }, + { "VSTARTUP_EVENT_CLEAR", 4, 4, &umr_bitfield_default }, + { "VUPDATE_INT_EN", 5, 5, &umr_bitfield_default }, + { "VUPDATE_INT_TYPE", 6, 6, &umr_bitfield_default }, + { "VUPDATE_INT_POSITION_SEL", 7, 7, &umr_bitfield_default }, + { "VUPDATE_EVENT_OCCURRED", 8, 8, &umr_bitfield_default }, + { "VUPDATE_INT_STATUS", 9, 9, &umr_bitfield_default }, + { "VUPDATE_EVENT_CLEAR", 10, 10, &umr_bitfield_default }, + { "VUPDATE_STATUS", 11, 11, &umr_bitfield_default }, + { "VUPDATE_NO_LOCK_INT_EN", 12, 12, &umr_bitfield_default }, + { "VUPDATE_NO_LOCK_INT_TYPE", 13, 13, &umr_bitfield_default }, + { "VUPDATE_NO_LOCK_EVENT_OCCURRED", 14, 14, &umr_bitfield_default }, + { "VUPDATE_NO_LOCK_INT_STATUS", 15, 15, &umr_bitfield_default }, + { "VUPDATE_NO_LOCK_EVENT_CLEAR", 16, 16, &umr_bitfield_default }, + { "VUPDATE_NO_LOCK_STATUS", 17, 17, &umr_bitfield_default }, + { "VREADY_INT_EN", 18, 18, &umr_bitfield_default }, + { "VREADY_INT_TYPE", 19, 19, &umr_bitfield_default }, + { "VREADY_EVENT_OCCURRED", 20, 20, &umr_bitfield_default }, + { "VREADY_INT_STATUS", 21, 21, &umr_bitfield_default }, + { "VREADY_EVENT_CLEAR", 22, 22, &umr_bitfield_default }, + { "STEREO_SELECT_STATUS", 24, 24, &umr_bitfield_default }, + { "FIELD_NUMBER_STATUS", 25, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_MASTER_UPDATE_LOCK[] = { + { "OTG_MASTER_UPDATE_LOCK", 0, 0, &umr_bitfield_default }, + { "UPDATE_LOCK_STATUS", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_GSL_CONTROL[] = { + { "OTG_GSL0_EN", 0, 0, &umr_bitfield_default }, + { "OTG_GSL1_EN", 1, 1, &umr_bitfield_default }, + { "OTG_GSL2_EN", 2, 2, &umr_bitfield_default }, + { "OTG_GSL_MASTER_EN", 3, 3, &umr_bitfield_default }, + { "OTG_GSL_FORCE_DELAY", 16, 20, &umr_bitfield_default }, + { "OTG_GSL_CHECK_ALL_FIELDS", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_GSL_WINDOW_X[] = { + { "OTG_GSL_WINDOW_START_X", 0, 14, &umr_bitfield_default }, + { "OTG_GSL_WINDOW_END_X", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_GSL_WINDOW_Y[] = { + { "OTG_GSL_WINDOW_START_Y", 0, 14, &umr_bitfield_default }, + { "OTG_GSL_WINDOW_END_Y", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_VUPDATE_KEEPOUT[] = { + { "MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET", 0, 15, &umr_bitfield_default }, + { "MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET", 16, 25, &umr_bitfield_default }, + { "OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_GLOBAL_CONTROL0[] = { + { "OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT", 0, 7, &umr_bitfield_default }, + { "OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN", 8, 8, &umr_bitfield_default }, + { "OTG_MASTER_UPDATE_LOCK_SEL", 25, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_GLOBAL_CONTROL1[] = { + { "MASTER_UPDATE_LOCK_DB_X", 0, 14, &umr_bitfield_default }, + { "MASTER_UPDATE_LOCK_DB_Y", 16, 30, &umr_bitfield_default }, + { "MASTER_UPDATE_LOCK_DB_EN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_GLOBAL_CONTROL2[] = { + { "DIG_UPDATE_LOCATION", 0, 9, &umr_bitfield_default }, + { "GLOBAL_UPDATE_LOCK_EN", 10, 10, &umr_bitfield_default }, + { "MANUAL_FLOW_CONTROL_SEL", 16, 18, &umr_bitfield_default }, + { "DCCG_VUPDATE_MODE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_GLOBAL_CONTROL3[] = { + { "MASTER_UPDATE_LOCK_DB_FIELD", 0, 1, &umr_bitfield_default }, + { "MASTER_UPDATE_LOCK_DB_STEREO_SEL", 4, 5, &umr_bitfield_default }, + { "MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_TRIG_MANUAL_CONTROL[] = { + { "TRIG_MANUAL_CONTROL", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_MANUAL_FLOW_CONTROL[] = { + { "MANUAL_FLOW_CONTROL", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_RANGE_TIMING_INT_STATUS[] = { + { "OTG_RANGE_TIMING_UPDATE_OCCURRED", 0, 0, &umr_bitfield_default }, + { "OTG_RANGE_TIMING_UPDATE_OCCURRED_INT", 4, 4, &umr_bitfield_default }, + { "OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR", 8, 8, &umr_bitfield_default }, + { "OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK", 12, 12, &umr_bitfield_default }, + { "OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_DRR_CONTROL[] = { + { "OTG_DRR_AVERAGE_FRAME", 0, 2, &umr_bitfield_default }, + { "OTG_V_TOTAL_LAST_USED_BY_DRR", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_REQUEST_CONTROL[] = { + { "OTG_REQUEST_MODE_FOR_H_DUPLICATE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG4_OTG_SPARE_REGISTER[] = { + { "OTG_SPARE_REG", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_H_TOTAL[] = { + { "OTG_H_TOTAL", 0, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_H_BLANK_START_END[] = { + { "OTG_H_BLANK_START", 0, 14, &umr_bitfield_default }, + { "OTG_H_BLANK_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_H_SYNC_A[] = { + { "OTG_H_SYNC_A_START", 0, 14, &umr_bitfield_default }, + { "OTG_H_SYNC_A_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_H_SYNC_A_CNTL[] = { + { "OTG_H_SYNC_A_POL", 0, 0, &umr_bitfield_default }, + { "OTG_COMP_SYNC_A_EN", 16, 16, &umr_bitfield_default }, + { "OTG_H_SYNC_A_CUTOFF", 17, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_H_TIMING_CNTL[] = { + { "OTG_H_TIMING_DIV_BY2", 0, 0, &umr_bitfield_default }, + { "OTG_H_TIMING_DIV_BY2_UPDATE_MODE", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_V_TOTAL[] = { + { "OTG_V_TOTAL", 0, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_V_TOTAL_MIN[] = { + { "OTG_V_TOTAL_MIN", 0, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_V_TOTAL_MAX[] = { + { "OTG_V_TOTAL_MAX", 0, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_V_TOTAL_MID[] = { + { "OTG_V_TOTAL_MID", 0, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_V_TOTAL_CONTROL[] = { + { "OTG_V_TOTAL_MIN_SEL", 0, 0, &umr_bitfield_default }, + { "OTG_V_TOTAL_MAX_SEL", 1, 1, &umr_bitfield_default }, + { "OTG_VTOTAL_MID_REPLACING_MAX_EN", 2, 2, &umr_bitfield_default }, + { "OTG_VTOTAL_MID_REPLACING_MIN_EN", 3, 3, &umr_bitfield_default }, + { "OTG_FORCE_LOCK_ON_EVENT", 4, 4, &umr_bitfield_default }, + { "OTG_SET_V_TOTAL_MIN_MASK_EN", 7, 7, &umr_bitfield_default }, + { "OTG_VTOTAL_MID_FRAME_NUM", 8, 15, &umr_bitfield_default }, + { "OTG_SET_V_TOTAL_MIN_MASK", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_V_TOTAL_INT_STATUS[] = { + { "OTG_SET_V_TOTAL_MIN_EVENT_OCCURED", 0, 0, &umr_bitfield_default }, + { "OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_INT", 4, 4, &umr_bitfield_default }, + { "OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK", 8, 8, &umr_bitfield_default }, + { "OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK", 12, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_VSYNC_NOM_INT_STATUS[] = { + { "OTG_VSYNC_NOM", 0, 0, &umr_bitfield_default }, + { "OTG_VSYNC_NOM_INT_CLEAR", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_V_BLANK_START_END[] = { + { "OTG_V_BLANK_START", 0, 14, &umr_bitfield_default }, + { "OTG_V_BLANK_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_V_SYNC_A[] = { + { "OTG_V_SYNC_A_START", 0, 14, &umr_bitfield_default }, + { "OTG_V_SYNC_A_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_V_SYNC_A_CNTL[] = { + { "OTG_V_SYNC_A_POL", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_TRIGA_CNTL[] = { + { "OTG_TRIGA_SOURCE_SELECT", 0, 4, &umr_bitfield_default }, + { "OTG_TRIGA_SOURCE_PIPE_SELECT", 5, 7, &umr_bitfield_default }, + { "OTG_TRIGA_POLARITY_SELECT", 8, 10, &umr_bitfield_default }, + { "OTG_TRIGA_RESYNC_BYPASS_EN", 11, 11, &umr_bitfield_default }, + { "OTG_TRIGA_INPUT_STATUS", 12, 12, &umr_bitfield_default }, + { "OTG_TRIGA_POLARITY_STATUS", 13, 13, &umr_bitfield_default }, + { "OTG_TRIGA_OCCURRED", 14, 14, &umr_bitfield_default }, + { "OTG_TRIGA_RISING_EDGE_DETECT_CNTL", 16, 17, &umr_bitfield_default }, + { "OTG_TRIGA_FALLING_EDGE_DETECT_CNTL", 18, 19, &umr_bitfield_default }, + { "OTG_TRIGA_FREQUENCY_SELECT", 20, 21, &umr_bitfield_default }, + { "OTG_TRIGA_DELAY", 24, 28, &umr_bitfield_default }, + { "OTG_TRIGA_CLEAR", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_TRIGA_MANUAL_TRIG[] = { + { "OTG_TRIGA_MANUAL_TRIG", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_TRIGB_CNTL[] = { + { "OTG_TRIGB_SOURCE_SELECT", 0, 4, &umr_bitfield_default }, + { "OTG_TRIGB_SOURCE_PIPE_SELECT", 5, 7, &umr_bitfield_default }, + { "OTG_TRIGB_POLARITY_SELECT", 8, 10, &umr_bitfield_default }, + { "OTG_TRIGB_RESYNC_BYPASS_EN", 11, 11, &umr_bitfield_default }, + { "OTG_TRIGB_INPUT_STATUS", 12, 12, &umr_bitfield_default }, + { "OTG_TRIGB_POLARITY_STATUS", 13, 13, &umr_bitfield_default }, + { "OTG_TRIGB_OCCURRED", 14, 14, &umr_bitfield_default }, + { "OTG_TRIGB_RISING_EDGE_DETECT_CNTL", 16, 17, &umr_bitfield_default }, + { "OTG_TRIGB_FALLING_EDGE_DETECT_CNTL", 18, 19, &umr_bitfield_default }, + { "OTG_TRIGB_FREQUENCY_SELECT", 20, 21, &umr_bitfield_default }, + { "OTG_TRIGB_DELAY", 24, 28, &umr_bitfield_default }, + { "OTG_TRIGB_CLEAR", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_TRIGB_MANUAL_TRIG[] = { + { "OTG_TRIGB_MANUAL_TRIG", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_FORCE_COUNT_NOW_CNTL[] = { + { "OTG_FORCE_COUNT_NOW_MODE", 0, 1, &umr_bitfield_default }, + { "OTG_FORCE_COUNT_NOW_CHECK", 4, 4, &umr_bitfield_default }, + { "OTG_FORCE_COUNT_NOW_TRIG_SEL", 8, 8, &umr_bitfield_default }, + { "OTG_FORCE_COUNT_NOW_OCCURRED", 16, 16, &umr_bitfield_default }, + { "OTG_FORCE_COUNT_NOW_CLEAR", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_FLOW_CONTROL[] = { + { "OTG_FLOW_CONTROL_SOURCE_SELECT", 0, 4, &umr_bitfield_default }, + { "OTG_FLOW_CONTROL_POLARITY", 8, 8, &umr_bitfield_default }, + { "OTG_FLOW_CONTROL_GRANULARITY", 16, 16, &umr_bitfield_default }, + { "OTG_FLOW_CONTROL_INPUT_STATUS", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_STEREO_FORCE_NEXT_EYE[] = { + { "OTG_STEREO_FORCE_NEXT_EYE", 0, 1, &umr_bitfield_default }, + { "OTG_AVSYNC_FRAME_COUNTER", 8, 15, &umr_bitfield_default }, + { "OTG_AVSYNC_LINE_COUNTER", 16, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_AVSYNC_COUNTER[] = { + { "OTG_AVSYNC_COUNTER", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_CONTROL[] = { + { "OTG_MASTER_EN", 0, 0, &umr_bitfield_default }, + { "OTG_DISABLE_POINT_CNTL", 8, 9, &umr_bitfield_default }, + { "OTG_START_POINT_CNTL", 12, 12, &umr_bitfield_default }, + { "OTG_FIELD_NUMBER_CNTL", 13, 13, &umr_bitfield_default }, + { "OTG_FIELD_NUMBER_POLARITY", 14, 14, &umr_bitfield_default }, + { "OTG_CURRENT_MASTER_EN_STATE", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_BLANK_CONTROL[] = { + { "OTG_CURRENT_BLANK_STATE", 0, 0, &umr_bitfield_default }, + { "OTG_BLANK_DATA_EN", 8, 8, &umr_bitfield_default }, + { "OTG_BLANK_DE_MODE", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_PIPE_ABORT_CONTROL[] = { + { "OTG_PIPE_ABORT", 0, 0, &umr_bitfield_default }, + { "OTG_PIPE_ABORT_DONE", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_INTERLACE_CONTROL[] = { + { "OTG_INTERLACE_ENABLE", 0, 0, &umr_bitfield_default }, + { "OTG_INTERLACE_FORCE_NEXT_FIELD", 16, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_INTERLACE_STATUS[] = { + { "OTG_INTERLACE_CURRENT_FIELD", 0, 0, &umr_bitfield_default }, + { "OTG_INTERLACE_NEXT_FIELD", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_FIELD_INDICATION_CONTROL[] = { + { "OTG_FIELD_INDICATION_OUTPUT_POLARITY", 0, 0, &umr_bitfield_default }, + { "OTG_FIELD_ALIGNMENT", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_PIXEL_DATA_READBACK0[] = { + { "OTG_PIXEL_DATA_BLUE_CB", 0, 15, &umr_bitfield_default }, + { "OTG_PIXEL_DATA_GREEN_Y", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_PIXEL_DATA_READBACK1[] = { + { "OTG_PIXEL_DATA_RED_CR", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_STATUS[] = { + { "OTG_V_BLANK", 0, 0, &umr_bitfield_default }, + { "OTG_V_ACTIVE_DISP", 1, 1, &umr_bitfield_default }, + { "OTG_V_SYNC_A", 2, 2, &umr_bitfield_default }, + { "OTG_V_UPDATE", 3, 3, &umr_bitfield_default }, + { "OTG_V_BLANK_3D_STRUCTURE", 5, 5, &umr_bitfield_default }, + { "OTG_H_BLANK", 16, 16, &umr_bitfield_default }, + { "OTG_H_ACTIVE_DISP", 17, 17, &umr_bitfield_default }, + { "OTG_H_SYNC_A", 18, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_STATUS_POSITION[] = { + { "OTG_VERT_COUNT", 0, 14, &umr_bitfield_default }, + { "OTG_HORZ_COUNT", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_NOM_VERT_POSITION[] = { + { "OTG_VERT_COUNT_NOM", 0, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_STATUS_FRAME_COUNT[] = { + { "OTG_FRAME_COUNT", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_STATUS_VF_COUNT[] = { + { "OTG_VF_COUNT", 0, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_STATUS_HV_COUNT[] = { + { "OTG_HV_COUNT", 0, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_COUNT_CONTROL[] = { + { "OTG_HORZ_COUNT_BY2_EN", 0, 0, &umr_bitfield_default }, + { "OTG_HORZ_REPETITION_COUNT", 1, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_COUNT_RESET[] = { + { "OTG_RESET_FRAME_COUNT", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE[] = { + { "OTG_MANUAL_FORCE_VSYNC_NEXT_LINE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_VERT_SYNC_CONTROL[] = { + { "OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED", 0, 0, &umr_bitfield_default }, + { "OTG_FORCE_VSYNC_NEXT_LINE_CLEAR", 8, 8, &umr_bitfield_default }, + { "OTG_AUTO_FORCE_VSYNC_MODE", 16, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_STEREO_STATUS[] = { + { "OTG_STEREO_CURRENT_EYE", 0, 0, &umr_bitfield_default }, + { "OTG_STEREO_SYNC_OUTPUT", 8, 8, &umr_bitfield_default }, + { "OTG_STEREO_SYNC_SELECT", 16, 16, &umr_bitfield_default }, + { "OTG_STEREO_EYE_FLAG", 20, 20, &umr_bitfield_default }, + { "OTG_STEREO_FORCE_NEXT_EYE_PENDING", 24, 25, &umr_bitfield_default }, + { "OTG_CURRENT_3D_STRUCTURE_STATE", 30, 30, &umr_bitfield_default }, + { "OTG_CURRENT_STEREOSYNC_EN_STATE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_STEREO_CONTROL[] = { + { "OTG_STEREO_SYNC_OUTPUT_LINE_NUM", 0, 14, &umr_bitfield_default }, + { "OTG_STEREO_SYNC_OUTPUT_POLARITY", 15, 15, &umr_bitfield_default }, + { "OTG_STEREO_EYE_FLAG_POLARITY", 17, 17, &umr_bitfield_default }, + { "OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP", 18, 18, &umr_bitfield_default }, + { "OTG_DISABLE_FIELD_NUM", 19, 19, &umr_bitfield_default }, + { "OTG_DISABLE_V_BLANK_FOR_DP_FIX", 20, 20, &umr_bitfield_default }, + { "OTG_STEREO_EN", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_SNAPSHOT_STATUS[] = { + { "OTG_SNAPSHOT_OCCURRED", 0, 0, &umr_bitfield_default }, + { "OTG_SNAPSHOT_CLEAR", 1, 1, &umr_bitfield_default }, + { "OTG_SNAPSHOT_MANUAL_TRIGGER", 2, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_SNAPSHOT_CONTROL[] = { + { "OTG_AUTO_SNAPSHOT_TRIG_SEL", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_SNAPSHOT_POSITION[] = { + { "OTG_SNAPSHOT_VERT_COUNT", 0, 14, &umr_bitfield_default }, + { "OTG_SNAPSHOT_HORZ_COUNT", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_SNAPSHOT_FRAME[] = { + { "OTG_SNAPSHOT_FRAME_COUNT", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_INTERRUPT_CONTROL[] = { + { "OTG_SNAPSHOT_INT_MSK", 0, 0, &umr_bitfield_default }, + { "OTG_SNAPSHOT_INT_TYPE", 1, 1, &umr_bitfield_default }, + { "OTG_FORCE_COUNT_NOW_INT_MSK", 8, 8, &umr_bitfield_default }, + { "OTG_FORCE_COUNT_NOW_INT_TYPE", 9, 9, &umr_bitfield_default }, + { "OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK", 16, 16, &umr_bitfield_default }, + { "OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE", 17, 17, &umr_bitfield_default }, + { "OTG_TRIGA_INT_MSK", 24, 24, &umr_bitfield_default }, + { "OTG_TRIGB_INT_MSK", 25, 25, &umr_bitfield_default }, + { "OTG_TRIGA_INT_TYPE", 26, 26, &umr_bitfield_default }, + { "OTG_TRIGB_INT_TYPE", 27, 27, &umr_bitfield_default }, + { "OTG_VSYNC_NOM_INT_MSK", 28, 28, &umr_bitfield_default }, + { "OTG_VSYNC_NOM_INT_TYPE", 29, 29, &umr_bitfield_default }, + { "OTG_GSL_VSYNC_GAP_INT_MSK", 30, 30, &umr_bitfield_default }, + { "OTG_GSL_VSYNC_GAP_INT_TYPE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_UPDATE_LOCK[] = { + { "OTG_UPDATE_LOCK", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_DOUBLE_BUFFER_CONTROL[] = { + { "OTG_UPDATE_PENDING", 0, 0, &umr_bitfield_default }, + { "OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING", 2, 2, &umr_bitfield_default }, + { "OTG_BLANK_DATA_EN_UPDATE_PENDING", 3, 3, &umr_bitfield_default }, + { "OTG_RANGE_TIMING_DBUF_UPDATE_PENDING", 4, 4, &umr_bitfield_default }, + { "OTG_TIMING_DB_UPDATE_PENDING", 5, 5, &umr_bitfield_default }, + { "OTG_3D_CTRL_DB_UPDATE_PENDING", 6, 6, &umr_bitfield_default }, + { "OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING", 7, 7, &umr_bitfield_default }, + { "OTG_UPDATE_INSTANTLY", 8, 8, &umr_bitfield_default }, + { "OTG_BLANK_DATA_DOUBLE_BUFFER_EN", 16, 16, &umr_bitfield_default }, + { "OTG_RANGE_TIMING_DBUF_UPDATE_MODE", 24, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_TEST_PATTERN_CONTROL[] = { + { "OTG_TEST_PATTERN_EN", 0, 0, &umr_bitfield_default }, + { "OTG_TEST_PATTERN_MODE", 8, 10, &umr_bitfield_default }, + { "OTG_TEST_PATTERN_DYNAMIC_RANGE", 16, 16, &umr_bitfield_default }, + { "OTG_TEST_PATTERN_COLOR_FORMAT", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_TEST_PATTERN_PARAMETERS[] = { + { "OTG_TEST_PATTERN_INC0", 0, 3, &umr_bitfield_default }, + { "OTG_TEST_PATTERN_INC1", 4, 7, &umr_bitfield_default }, + { "OTG_TEST_PATTERN_VRES", 8, 11, &umr_bitfield_default }, + { "OTG_TEST_PATTERN_HRES", 12, 15, &umr_bitfield_default }, + { "OTG_TEST_PATTERN_RAMP0_OFFSET", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_TEST_PATTERN_COLOR[] = { + { "OTG_TEST_PATTERN_DATA", 0, 15, &umr_bitfield_default }, + { "OTG_TEST_PATTERN_MASK", 16, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_MASTER_EN[] = { + { "OTG_MASTER_EN", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_BLANK_DATA_COLOR[] = { + { "OTG_BLANK_DATA_COLOR_BLUE_CB", 0, 9, &umr_bitfield_default }, + { "OTG_BLANK_DATA_COLOR_GREEN_Y", 10, 19, &umr_bitfield_default }, + { "OTG_BLANK_DATA_COLOR_RED_CR", 20, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_BLANK_DATA_COLOR_EXT[] = { + { "OTG_BLANK_DATA_COLOR_BLUE_CB_EXT", 0, 5, &umr_bitfield_default }, + { "OTG_BLANK_DATA_COLOR_GREEN_Y_EXT", 8, 13, &umr_bitfield_default }, + { "OTG_BLANK_DATA_COLOR_RED_CR_EXT", 16, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_BLACK_COLOR[] = { + { "OTG_BLACK_COLOR_B_CB", 0, 9, &umr_bitfield_default }, + { "OTG_BLACK_COLOR_G_Y", 10, 19, &umr_bitfield_default }, + { "OTG_BLACK_COLOR_R_CR", 20, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_BLACK_COLOR_EXT[] = { + { "OTG_BLACK_COLOR_B_CB_EXT", 0, 5, &umr_bitfield_default }, + { "OTG_BLACK_COLOR_G_Y_EXT", 8, 13, &umr_bitfield_default }, + { "OTG_BLACK_COLOR_R_CR_EXT", 16, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_VERTICAL_INTERRUPT0_POSITION[] = { + { "OTG_VERTICAL_INTERRUPT0_LINE_START", 0, 14, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT0_LINE_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_VERTICAL_INTERRUPT0_CONTROL[] = { + { "OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY", 4, 4, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT0_INT_ENABLE", 8, 8, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT0_STATUS", 12, 12, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT0_INT_STATUS", 16, 16, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT0_CLEAR", 20, 20, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT0_INT_TYPE", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_VERTICAL_INTERRUPT1_POSITION[] = { + { "OTG_VERTICAL_INTERRUPT1_LINE_START", 0, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_VERTICAL_INTERRUPT1_CONTROL[] = { + { "OTG_VERTICAL_INTERRUPT1_INT_ENABLE", 8, 8, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT1_STATUS", 12, 12, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT1_INT_STATUS", 16, 16, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT1_CLEAR", 20, 20, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT1_INT_TYPE", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_VERTICAL_INTERRUPT2_POSITION[] = { + { "OTG_VERTICAL_INTERRUPT2_LINE_START", 0, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_VERTICAL_INTERRUPT2_CONTROL[] = { + { "OTG_VERTICAL_INTERRUPT2_INT_ENABLE", 8, 8, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT2_STATUS", 12, 12, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT2_INT_STATUS", 16, 16, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT2_CLEAR", 20, 20, &umr_bitfield_default }, + { "OTG_VERTICAL_INTERRUPT2_INT_TYPE", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_CRC_CNTL[] = { + { "OTG_CRC_EN", 0, 0, &umr_bitfield_default }, + { "OTG_CRC_DUAL_LINK_EN", 1, 1, &umr_bitfield_default }, + { "OTG_CRC_DUAL_LINK_MODE", 2, 2, &umr_bitfield_default }, + { "OTG_CRC_BLANK_ONLY", 3, 3, &umr_bitfield_default }, + { "OTG_CRC_CONT_EN", 4, 4, &umr_bitfield_default }, + { "OTG_CRC_CAPTURE_START_SEL", 5, 6, &umr_bitfield_default }, + { "OTG_CRC_STEREO_MODE", 8, 9, &umr_bitfield_default }, + { "OTG_CRC_INTERLACE_MODE", 12, 13, &umr_bitfield_default }, + { "OTG_CRC_MULTI_STREAM_MODE", 16, 18, &umr_bitfield_default }, + { "OTG_CRC_USE_NEW_AND_REPEATED_PIXELS", 19, 19, &umr_bitfield_default }, + { "OTG_CRC0_SELECT", 20, 22, &umr_bitfield_default }, + { "OTG_CRC1_SELECT", 24, 26, &umr_bitfield_default }, + { "OTG_ONE_SHOT_CRC0_PENDING", 28, 28, &umr_bitfield_default }, + { "OTG_ONE_SHOT_CRC1_PENDING", 29, 29, &umr_bitfield_default }, + { "OTG_ONE_SHOT_CRC2_PENDING", 30, 30, &umr_bitfield_default }, + { "OTG_ONE_SHOT_CRC3_PENDING", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_CRC0_WINDOWA_X_CONTROL[] = { + { "OTG_CRC0_WINDOWA_X_START", 0, 14, &umr_bitfield_default }, + { "OTG_CRC0_WINDOWA_X_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_CRC0_WINDOWA_Y_CONTROL[] = { + { "OTG_CRC0_WINDOWA_Y_START", 0, 14, &umr_bitfield_default }, + { "OTG_CRC0_WINDOWA_Y_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_CRC0_WINDOWB_X_CONTROL[] = { + { "OTG_CRC0_WINDOWB_X_START", 0, 14, &umr_bitfield_default }, + { "OTG_CRC0_WINDOWB_X_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_CRC0_WINDOWB_Y_CONTROL[] = { + { "OTG_CRC0_WINDOWB_Y_START", 0, 14, &umr_bitfield_default }, + { "OTG_CRC0_WINDOWB_Y_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_CRC0_DATA_RG[] = { + { "CRC0_R_CR", 0, 15, &umr_bitfield_default }, + { "CRC0_G_Y", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_CRC0_DATA_B[] = { + { "CRC0_B_CB", 0, 15, &umr_bitfield_default }, + { "CRC0_C", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_CRC1_WINDOWA_X_CONTROL[] = { + { "OTG_CRC1_WINDOWA_X_START", 0, 14, &umr_bitfield_default }, + { "OTG_CRC1_WINDOWA_X_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_CRC1_WINDOWA_Y_CONTROL[] = { + { "OTG_CRC1_WINDOWA_Y_START", 0, 14, &umr_bitfield_default }, + { "OTG_CRC1_WINDOWA_Y_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_CRC1_WINDOWB_X_CONTROL[] = { + { "OTG_CRC1_WINDOWB_X_START", 0, 14, &umr_bitfield_default }, + { "OTG_CRC1_WINDOWB_X_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_CRC1_WINDOWB_Y_CONTROL[] = { + { "OTG_CRC1_WINDOWB_Y_START", 0, 14, &umr_bitfield_default }, + { "OTG_CRC1_WINDOWB_Y_END", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_CRC1_DATA_RG[] = { + { "CRC1_R_CR", 0, 15, &umr_bitfield_default }, + { "CRC1_G_Y", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_CRC1_DATA_B[] = { + { "CRC1_B_CB", 0, 15, &umr_bitfield_default }, + { "CRC1_C", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_CRC2_DATA_RG[] = { + { "CRC2_R_CR", 0, 15, &umr_bitfield_default }, + { "CRC2_G_Y", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_CRC2_DATA_B[] = { + { "CRC2_B_CB", 0, 15, &umr_bitfield_default }, + { "CRC2_C", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_CRC3_DATA_RG[] = { + { "CRC3_R_CR", 0, 15, &umr_bitfield_default }, + { "CRC3_G_Y", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_CRC3_DATA_B[] = { + { "CRC3_B_CB", 0, 15, &umr_bitfield_default }, + { "CRC3_C", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_CRC_SIG_RED_GREEN_MASK[] = { + { "OTG_CRC_SIG_RED_MASK", 0, 15, &umr_bitfield_default }, + { "OTG_CRC_SIG_GREEN_MASK", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK[] = { + { "OTG_CRC_SIG_BLUE_MASK", 0, 15, &umr_bitfield_default }, + { "OTG_CRC_SIG_CONTROL_MASK", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_STATIC_SCREEN_CONTROL[] = { + { "OTG_STATIC_SCREEN_EVENT_MASK", 0, 15, &umr_bitfield_default }, + { "OTG_STATIC_SCREEN_FRAME_COUNT", 16, 23, &umr_bitfield_default }, + { "OTG_CPU_SS_INT_ENABLE", 24, 24, &umr_bitfield_default }, + { "OTG_SS_STATUS", 25, 25, &umr_bitfield_default }, + { "OTG_CPU_SS_INT_STATUS", 26, 26, &umr_bitfield_default }, + { "OTG_CPU_SS_INT_CLEAR", 27, 27, &umr_bitfield_default }, + { "OTG_CPU_SS_INT_TYPE", 28, 28, &umr_bitfield_default }, + { "OTG_STATIC_SCREEN_OVERRIDE", 30, 30, &umr_bitfield_default }, + { "OTG_STATIC_SCREEN_OVERRIDE_VALUE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_3D_STRUCTURE_CONTROL[] = { + { "OTG_3D_STRUCTURE_EN", 0, 0, &umr_bitfield_default }, + { "OTG_3D_STRUCTURE_V_UPDATE_MODE", 8, 9, &umr_bitfield_default }, + { "OTG_3D_STRUCTURE_STEREO_SEL_OVR", 12, 12, &umr_bitfield_default }, + { "OTG_3D_STRUCTURE_F_COUNT_RESET", 16, 16, &umr_bitfield_default }, + { "OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING", 17, 17, &umr_bitfield_default }, + { "OTG_3D_STRUCTURE_F_COUNT", 18, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_GSL_VSYNC_GAP[] = { + { "OTG_GSL_VSYNC_GAP_LIMIT", 0, 7, &umr_bitfield_default }, + { "OTG_GSL_VSYNC_GAP_DELAY", 8, 15, &umr_bitfield_default }, + { "OTG_GSL_VSYNC_GAP_SOURCE_SEL", 16, 16, &umr_bitfield_default }, + { "OTG_GSL_VSYNC_GAP_MODE", 17, 18, &umr_bitfield_default }, + { "OTG_GSL_VSYNC_GAP_CLEAR", 19, 19, &umr_bitfield_default }, + { "OTG_GSL_VSYNC_GAP_OCCURRED", 20, 20, &umr_bitfield_default }, + { "OTG_GSL_VSYNC_GAP_MASTER_FASTER", 23, 23, &umr_bitfield_default }, + { "OTG_GSL_VSYNC_GAP", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_MASTER_UPDATE_MODE[] = { + { "MASTER_UPDATE_INTERLACED_MODE", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_CLOCK_CONTROL[] = { + { "OTG_CLOCK_EN", 0, 0, &umr_bitfield_default }, + { "OTG_CLOCK_GATE_DIS", 1, 1, &umr_bitfield_default }, + { "OTG_SOFT_RESET", 4, 4, &umr_bitfield_default }, + { "OTG_CLOCK_ON", 8, 8, &umr_bitfield_default }, + { "OTG_BUSY", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_VSTARTUP_PARAM[] = { + { "VSTARTUP_START", 0, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_VUPDATE_PARAM[] = { + { "VUPDATE_OFFSET", 0, 15, &umr_bitfield_default }, + { "VUPDATE_WIDTH", 16, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_VREADY_PARAM[] = { + { "VREADY_OFFSET", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_GLOBAL_SYNC_STATUS[] = { + { "VSTARTUP_INT_EN", 0, 0, &umr_bitfield_default }, + { "VSTARTUP_INT_TYPE", 1, 1, &umr_bitfield_default }, + { "VSTARTUP_EVENT_OCCURRED", 2, 2, &umr_bitfield_default }, + { "VSTARTUP_INT_STATUS", 3, 3, &umr_bitfield_default }, + { "VSTARTUP_EVENT_CLEAR", 4, 4, &umr_bitfield_default }, + { "VUPDATE_INT_EN", 5, 5, &umr_bitfield_default }, + { "VUPDATE_INT_TYPE", 6, 6, &umr_bitfield_default }, + { "VUPDATE_INT_POSITION_SEL", 7, 7, &umr_bitfield_default }, + { "VUPDATE_EVENT_OCCURRED", 8, 8, &umr_bitfield_default }, + { "VUPDATE_INT_STATUS", 9, 9, &umr_bitfield_default }, + { "VUPDATE_EVENT_CLEAR", 10, 10, &umr_bitfield_default }, + { "VUPDATE_STATUS", 11, 11, &umr_bitfield_default }, + { "VUPDATE_NO_LOCK_INT_EN", 12, 12, &umr_bitfield_default }, + { "VUPDATE_NO_LOCK_INT_TYPE", 13, 13, &umr_bitfield_default }, + { "VUPDATE_NO_LOCK_EVENT_OCCURRED", 14, 14, &umr_bitfield_default }, + { "VUPDATE_NO_LOCK_INT_STATUS", 15, 15, &umr_bitfield_default }, + { "VUPDATE_NO_LOCK_EVENT_CLEAR", 16, 16, &umr_bitfield_default }, + { "VUPDATE_NO_LOCK_STATUS", 17, 17, &umr_bitfield_default }, + { "VREADY_INT_EN", 18, 18, &umr_bitfield_default }, + { "VREADY_INT_TYPE", 19, 19, &umr_bitfield_default }, + { "VREADY_EVENT_OCCURRED", 20, 20, &umr_bitfield_default }, + { "VREADY_INT_STATUS", 21, 21, &umr_bitfield_default }, + { "VREADY_EVENT_CLEAR", 22, 22, &umr_bitfield_default }, + { "STEREO_SELECT_STATUS", 24, 24, &umr_bitfield_default }, + { "FIELD_NUMBER_STATUS", 25, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_MASTER_UPDATE_LOCK[] = { + { "OTG_MASTER_UPDATE_LOCK", 0, 0, &umr_bitfield_default }, + { "UPDATE_LOCK_STATUS", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_GSL_CONTROL[] = { + { "OTG_GSL0_EN", 0, 0, &umr_bitfield_default }, + { "OTG_GSL1_EN", 1, 1, &umr_bitfield_default }, + { "OTG_GSL2_EN", 2, 2, &umr_bitfield_default }, + { "OTG_GSL_MASTER_EN", 3, 3, &umr_bitfield_default }, + { "OTG_GSL_FORCE_DELAY", 16, 20, &umr_bitfield_default }, + { "OTG_GSL_CHECK_ALL_FIELDS", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_GSL_WINDOW_X[] = { + { "OTG_GSL_WINDOW_START_X", 0, 14, &umr_bitfield_default }, + { "OTG_GSL_WINDOW_END_X", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_GSL_WINDOW_Y[] = { + { "OTG_GSL_WINDOW_START_Y", 0, 14, &umr_bitfield_default }, + { "OTG_GSL_WINDOW_END_Y", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_VUPDATE_KEEPOUT[] = { + { "MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET", 0, 15, &umr_bitfield_default }, + { "MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET", 16, 25, &umr_bitfield_default }, + { "OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_GLOBAL_CONTROL0[] = { + { "OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT", 0, 7, &umr_bitfield_default }, + { "OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN", 8, 8, &umr_bitfield_default }, + { "OTG_MASTER_UPDATE_LOCK_SEL", 25, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_GLOBAL_CONTROL1[] = { + { "MASTER_UPDATE_LOCK_DB_X", 0, 14, &umr_bitfield_default }, + { "MASTER_UPDATE_LOCK_DB_Y", 16, 30, &umr_bitfield_default }, + { "MASTER_UPDATE_LOCK_DB_EN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_GLOBAL_CONTROL2[] = { + { "DIG_UPDATE_LOCATION", 0, 9, &umr_bitfield_default }, + { "GLOBAL_UPDATE_LOCK_EN", 10, 10, &umr_bitfield_default }, + { "MANUAL_FLOW_CONTROL_SEL", 16, 18, &umr_bitfield_default }, + { "DCCG_VUPDATE_MODE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_GLOBAL_CONTROL3[] = { + { "MASTER_UPDATE_LOCK_DB_FIELD", 0, 1, &umr_bitfield_default }, + { "MASTER_UPDATE_LOCK_DB_STEREO_SEL", 4, 5, &umr_bitfield_default }, + { "MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_TRIG_MANUAL_CONTROL[] = { + { "TRIG_MANUAL_CONTROL", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_MANUAL_FLOW_CONTROL[] = { + { "MANUAL_FLOW_CONTROL", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_RANGE_TIMING_INT_STATUS[] = { + { "OTG_RANGE_TIMING_UPDATE_OCCURRED", 0, 0, &umr_bitfield_default }, + { "OTG_RANGE_TIMING_UPDATE_OCCURRED_INT", 4, 4, &umr_bitfield_default }, + { "OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR", 8, 8, &umr_bitfield_default }, + { "OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK", 12, 12, &umr_bitfield_default }, + { "OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_DRR_CONTROL[] = { + { "OTG_DRR_AVERAGE_FRAME", 0, 2, &umr_bitfield_default }, + { "OTG_V_TOTAL_LAST_USED_BY_DRR", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_REQUEST_CONTROL[] = { + { "OTG_REQUEST_MODE_FOR_H_DUPLICATE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOTG5_OTG_SPARE_REGISTER[] = { + { "OTG_SPARE_REG", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDWB_SOURCE_SELECT[] = { + { "OPTC_DWB0_SOURCE_SELECT", 0, 2, &umr_bitfield_default }, + { "OPTC_DWB1_SOURCE_SELECT", 3, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGSL_SOURCE_SELECT[] = { + { "GSL0_READY_SOURCE_SEL", 0, 2, &umr_bitfield_default }, + { "GSL1_READY_SOURCE_SEL", 4, 6, &umr_bitfield_default }, + { "GSL2_READY_SOURCE_SEL", 8, 10, &umr_bitfield_default }, + { "GSL_TIMING_SYNC_SEL", 16, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOPTC_CLOCK_CONTROL[] = { + { "OPTC_DISPCLK_R_GATE_DIS", 0, 0, &umr_bitfield_default }, + { "OPTC_DISPCLK_R_CLOCK_ON", 1, 1, &umr_bitfield_default }, + { "OPTC_TEST_CLK_SEL", 8, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmOPTC_MISC_SPARE_REGISTER[] = { + { "OPTC_MISC_SPARE_REG", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON18_PERFCOUNTER_CNTL[] = { + { "PERFCOUNTER_EVENT_SEL", 0, 8, &umr_bitfield_default }, + { "PERFCOUNTER_CVALUE_SEL", 9, 11, &umr_bitfield_default }, + { "PERFCOUNTER_INC_MODE", 12, 14, &umr_bitfield_default }, + { "PERFCOUNTER_HW_CNTL_SEL", 15, 15, &umr_bitfield_default }, + { "PERFCOUNTER_RUNEN_MODE", 16, 16, &umr_bitfield_default }, + { "PERFCOUNTER_CNTOFF_START_DIS", 22, 22, &umr_bitfield_default }, + { "PERFCOUNTER_RESTART_EN", 23, 23, &umr_bitfield_default }, + { "PERFCOUNTER_INT_EN", 24, 24, &umr_bitfield_default }, + { "PERFCOUNTER_OFF_MASK", 25, 25, &umr_bitfield_default }, + { "PERFCOUNTER_ACTIVE", 26, 26, &umr_bitfield_default }, + { "PERFCOUNTER_CNTL_SEL", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON18_PERFCOUNTER_CNTL2[] = { + { "PERFCOUNTER_COUNTED_VALUE_TYPE", 0, 1, &umr_bitfield_default }, + { "PERFCOUNTER_HW_STOP1_SEL", 2, 2, &umr_bitfield_default }, + { "PERFCOUNTER_HW_STOP2_SEL", 3, 3, &umr_bitfield_default }, + { "PERFCOUNTER_CNTOFF_SEL", 8, 13, &umr_bitfield_default }, + { "PERFCOUNTER_CNTL2_SEL", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON18_PERFCOUNTER_STATE[] = { + { "PERFCOUNTER_CNT0_STATE", 0, 1, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL0", 2, 2, &umr_bitfield_default }, + { "PERFCOUNTER_CNT1_STATE", 4, 5, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL1", 6, 6, &umr_bitfield_default }, + { "PERFCOUNTER_CNT2_STATE", 8, 9, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL2", 10, 10, &umr_bitfield_default }, + { "PERFCOUNTER_CNT3_STATE", 12, 13, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL3", 14, 14, &umr_bitfield_default }, + { "PERFCOUNTER_CNT4_STATE", 16, 17, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL4", 18, 18, &umr_bitfield_default }, + { "PERFCOUNTER_CNT5_STATE", 20, 21, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL5", 22, 22, &umr_bitfield_default }, + { "PERFCOUNTER_CNT6_STATE", 24, 25, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL6", 26, 26, &umr_bitfield_default }, + { "PERFCOUNTER_CNT7_STATE", 28, 29, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL7", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON18_PERFMON_CNTL[] = { + { "PERFMON_STATE", 0, 1, &umr_bitfield_default }, + { "PERFMON_RPT_COUNT", 8, 27, &umr_bitfield_default }, + { "PERFMON_CNTOFF_AND_OR", 28, 28, &umr_bitfield_default }, + { "PERFMON_CNTOFF_INT_EN", 29, 29, &umr_bitfield_default }, + { "PERFMON_CNTOFF_INT_STATUS", 30, 30, &umr_bitfield_default }, + { "PERFMON_CNTOFF_INT_ACK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON18_PERFMON_CNTL2[] = { + { "PERFMON_CNTOFF_INT_TYPE", 0, 0, &umr_bitfield_default }, + { "PERFMON_CLK_ENABLE", 1, 1, &umr_bitfield_default }, + { "PERFMON_RUN_ENABLE_START_SEL", 2, 9, &umr_bitfield_default }, + { "PERFMON_RUN_ENABLE_STOP_SEL", 10, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON18_PERFMON_CVALUE_INT_MISC[] = { + { "PERFCOUNTER_INT0_STATUS", 0, 0, &umr_bitfield_default }, + { "PERFCOUNTER_INT1_STATUS", 1, 1, &umr_bitfield_default }, + { "PERFCOUNTER_INT2_STATUS", 2, 2, &umr_bitfield_default }, + { "PERFCOUNTER_INT3_STATUS", 3, 3, &umr_bitfield_default }, + { "PERFCOUNTER_INT4_STATUS", 4, 4, &umr_bitfield_default }, + { "PERFCOUNTER_INT5_STATUS", 5, 5, &umr_bitfield_default }, + { "PERFCOUNTER_INT6_STATUS", 6, 6, &umr_bitfield_default }, + { "PERFCOUNTER_INT7_STATUS", 7, 7, &umr_bitfield_default }, + { "PERFCOUNTER_INT0_ACK", 8, 8, &umr_bitfield_default }, + { "PERFCOUNTER_INT1_ACK", 9, 9, &umr_bitfield_default }, + { "PERFCOUNTER_INT2_ACK", 10, 10, &umr_bitfield_default }, + { "PERFCOUNTER_INT3_ACK", 11, 11, &umr_bitfield_default }, + { "PERFCOUNTER_INT4_ACK", 12, 12, &umr_bitfield_default }, + { "PERFCOUNTER_INT5_ACK", 13, 13, &umr_bitfield_default }, + { "PERFCOUNTER_INT6_ACK", 14, 14, &umr_bitfield_default }, + { "PERFCOUNTER_INT7_ACK", 15, 15, &umr_bitfield_default }, + { "PERFMON_CVALUE_HI", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON18_PERFMON_CVALUE_LOW[] = { + { "PERFMON_CVALUE_LOW", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON18_PERFMON_HI[] = { + { "PERFMON_HI", 0, 15, &umr_bitfield_default }, + { "PERFMON_READ_SEL", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON18_PERFMON_LOW[] = { + { "PERFMON_LOW", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAC_ENABLE[] = { + { "DAC_ENABLE", 0, 0, &umr_bitfield_default }, + { "DAC_RESYNC_FIFO_ENABLE", 1, 1, &umr_bitfield_default }, + { "DAC_RESYNC_FIFO_POINTER_SKEW", 2, 3, &umr_bitfield_default }, + { "DAC_RESYNC_FIFO_ERROR", 4, 4, &umr_bitfield_default }, + { "DAC_RESYNC_FIFO_ERROR_ACK", 5, 5, &umr_bitfield_default }, + { "DAC_RESYNC_FIFO_TVOUT_SIM", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAC_SOURCE_SELECT[] = { + { "DAC_SOURCE_SELECT", 0, 2, &umr_bitfield_default }, + { "DAC_TV_SELECT", 3, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAC_CRC_EN[] = { + { "DAC_CRC_EN", 0, 0, &umr_bitfield_default }, + { "DAC_CRC_CONT_EN", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAC_CRC_CONTROL[] = { + { "DAC_CRC_FIELD", 0, 0, &umr_bitfield_default }, + { "DAC_CRC_ONLY_BLANKB", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAC_CRC_SIG_RGB_MASK[] = { + { "DAC_CRC_SIG_BLUE_MASK", 0, 9, &umr_bitfield_default }, + { "DAC_CRC_SIG_GREEN_MASK", 10, 19, &umr_bitfield_default }, + { "DAC_CRC_SIG_RED_MASK", 20, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAC_CRC_SIG_CONTROL_MASK[] = { + { "DAC_CRC_SIG_CONTROL_MASK", 0, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAC_CRC_SIG_RGB[] = { + { "DAC_CRC_SIG_BLUE", 0, 9, &umr_bitfield_default }, + { "DAC_CRC_SIG_GREEN", 10, 19, &umr_bitfield_default }, + { "DAC_CRC_SIG_RED", 20, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAC_CRC_SIG_CONTROL[] = { + { "DAC_CRC_SIG_CONTROL", 0, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAC_SYNC_TRISTATE_CONTROL[] = { + { "DAC_HSYNCA_TRISTATE", 0, 0, &umr_bitfield_default }, + { "DAC_VSYNCA_TRISTATE", 8, 8, &umr_bitfield_default }, + { "DAC_SYNCA_TRISTATE", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAC_STEREOSYNC_SELECT[] = { + { "DAC_STEREOSYNC_SELECT", 0, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAC_AUTODETECT_CONTROL[] = { + { "DAC_AUTODETECT_MODE", 0, 1, &umr_bitfield_default }, + { "DAC_AUTODETECT_FRAME_TIME_COUNTER", 8, 15, &umr_bitfield_default }, + { "DAC_AUTODETECT_CHECK_MASK", 16, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAC_AUTODETECT_CONTROL2[] = { + { "DAC_AUTODETECT_POWERUP_COUNTER", 0, 7, &umr_bitfield_default }, + { "DAC_AUTODETECT_TESTMODE", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAC_AUTODETECT_CONTROL3[] = { + { "DAC_AUTODET_COMPARATOR_IN_DELAY", 0, 7, &umr_bitfield_default }, + { "DAC_AUTODET_COMPARATOR_OUT_DELAY", 8, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAC_AUTODETECT_STATUS[] = { + { "DAC_AUTODETECT_STATUS", 0, 0, &umr_bitfield_default }, + { "DAC_AUTODETECT_CONNECT", 4, 4, &umr_bitfield_default }, + { "DAC_AUTODETECT_RED_SENSE", 8, 9, &umr_bitfield_default }, + { "DAC_AUTODETECT_GREEN_SENSE", 16, 17, &umr_bitfield_default }, + { "DAC_AUTODETECT_BLUE_SENSE", 24, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAC_AUTODETECT_INT_CONTROL[] = { + { "DAC_AUTODETECT_ACK", 0, 0, &umr_bitfield_default }, + { "DAC_AUTODETECT_INT_ENABLE", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAC_FORCE_OUTPUT_CNTL[] = { + { "DAC_FORCE_DATA_EN", 0, 0, &umr_bitfield_default }, + { "DAC_FORCE_DATA_SEL", 8, 10, &umr_bitfield_default }, + { "DAC_FORCE_DATA_ON_BLANKB_ONLY", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAC_FORCE_DATA[] = { + { "DAC_FORCE_DATA", 0, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAC_POWERDOWN[] = { + { "DAC_POWERDOWN", 0, 0, &umr_bitfield_default }, + { "DAC_POWERDOWN_BLUE", 8, 8, &umr_bitfield_default }, + { "DAC_POWERDOWN_GREEN", 16, 16, &umr_bitfield_default }, + { "DAC_POWERDOWN_RED", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAC_CONTROL[] = { + { "DAC_DFORCE_EN", 0, 0, &umr_bitfield_default }, + { "DAC_TV_ENABLE", 8, 8, &umr_bitfield_default }, + { "DAC_ZSCALE_SHIFT", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAC_COMPARATOR_ENABLE[] = { + { "DAC_COMP_DDET_REF_EN", 0, 0, &umr_bitfield_default }, + { "DAC_COMP_SDET_REF_EN", 8, 8, &umr_bitfield_default }, + { "DAC_R_ASYNC_ENABLE", 16, 16, &umr_bitfield_default }, + { "DAC_G_ASYNC_ENABLE", 17, 17, &umr_bitfield_default }, + { "DAC_B_ASYNC_ENABLE", 18, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAC_COMPARATOR_OUTPUT[] = { + { "DAC_COMPARATOR_OUTPUT", 0, 0, &umr_bitfield_default }, + { "DAC_COMPARATOR_OUTPUT_BLUE", 1, 1, &umr_bitfield_default }, + { "DAC_COMPARATOR_OUTPUT_GREEN", 2, 2, &umr_bitfield_default }, + { "DAC_COMPARATOR_OUTPUT_RED", 3, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAC_PWR_CNTL[] = { + { "DAC_BG_MODE", 0, 1, &umr_bitfield_default }, + { "DAC_PWRCNTL", 16, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAC_DFT_CONFIG[] = { + { "DAC_DFT_CONFIG", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAC_FIFO_STATUS[] = { + { "DAC_FIFO_USE_OVERWRITE_LEVEL", 1, 1, &umr_bitfield_default }, + { "DAC_FIFO_OVERWRITE_LEVEL", 2, 7, &umr_bitfield_default }, + { "DAC_FIFO_CAL_AVERAGE_LEVEL", 10, 15, &umr_bitfield_default }, + { "DAC_FIFO_MAXIMUM_LEVEL", 16, 19, &umr_bitfield_default }, + { "DAC_FIFO_MINIMUM_LEVEL", 22, 25, &umr_bitfield_default }, + { "DAC_FIFO_CALIBRATED", 29, 29, &umr_bitfield_default }, + { "DAC_FIFO_FORCE_RECAL_AVERAGE", 30, 30, &umr_bitfield_default }, + { "DAC_FIFO_FORCE_RECOMP_MINMAX", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_I2C_CONTROL[] = { + { "DC_I2C_GO", 0, 0, &umr_bitfield_default }, + { "DC_I2C_SOFT_RESET", 1, 1, &umr_bitfield_default }, + { "DC_I2C_SEND_RESET", 2, 2, &umr_bitfield_default }, + { "DC_I2C_SW_STATUS_RESET", 3, 3, &umr_bitfield_default }, + { "DC_I2C_DDC_SELECT", 8, 10, &umr_bitfield_default }, + { "DC_I2C_TRANSACTION_COUNT", 20, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_I2C_ARBITRATION[] = { + { "DC_I2C_SW_PRIORITY", 0, 1, &umr_bitfield_default }, + { "DC_I2C_REG_RW_CNTL_STATUS", 2, 3, &umr_bitfield_default }, + { "DC_I2C_NO_QUEUED_SW_GO", 4, 4, &umr_bitfield_default }, + { "DC_I2C_ABORT_HW_XFER", 8, 8, &umr_bitfield_default }, + { "DC_I2C_ABORT_SW_XFER", 12, 12, &umr_bitfield_default }, + { "DC_I2C_SW_USE_I2C_REG_REQ", 20, 20, &umr_bitfield_default }, + { "DC_I2C_SW_DONE_USING_I2C_REG", 21, 21, &umr_bitfield_default }, + { "DC_I2C_DMCU_USE_I2C_REG_REQ", 24, 24, &umr_bitfield_default }, + { "DC_I2C_DMCU_DONE_USING_I2C_REG", 25, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_I2C_INTERRUPT_CONTROL[] = { + { "DC_I2C_SW_DONE_INT", 0, 0, &umr_bitfield_default }, + { "DC_I2C_SW_DONE_ACK", 1, 1, &umr_bitfield_default }, + { "DC_I2C_SW_DONE_MASK", 2, 2, &umr_bitfield_default }, + { "DC_I2C_DDC1_HW_DONE_INT", 4, 4, &umr_bitfield_default }, + { "DC_I2C_DDC1_HW_DONE_ACK", 5, 5, &umr_bitfield_default }, + { "DC_I2C_DDC1_HW_DONE_MASK", 6, 6, &umr_bitfield_default }, + { "DC_I2C_DDC2_HW_DONE_INT", 8, 8, &umr_bitfield_default }, + { "DC_I2C_DDC2_HW_DONE_ACK", 9, 9, &umr_bitfield_default }, + { "DC_I2C_DDC2_HW_DONE_MASK", 10, 10, &umr_bitfield_default }, + { "DC_I2C_DDC3_HW_DONE_INT", 12, 12, &umr_bitfield_default }, + { "DC_I2C_DDC3_HW_DONE_ACK", 13, 13, &umr_bitfield_default }, + { "DC_I2C_DDC3_HW_DONE_MASK", 14, 14, &umr_bitfield_default }, + { "DC_I2C_DDC4_HW_DONE_INT", 16, 16, &umr_bitfield_default }, + { "DC_I2C_DDC4_HW_DONE_ACK", 17, 17, &umr_bitfield_default }, + { "DC_I2C_DDC4_HW_DONE_MASK", 18, 18, &umr_bitfield_default }, + { "DC_I2C_DDC5_HW_DONE_INT", 20, 20, &umr_bitfield_default }, + { "DC_I2C_DDC5_HW_DONE_ACK", 21, 21, &umr_bitfield_default }, + { "DC_I2C_DDC5_HW_DONE_MASK", 22, 22, &umr_bitfield_default }, + { "DC_I2C_DDC6_HW_DONE_INT", 24, 24, &umr_bitfield_default }, + { "DC_I2C_DDC6_HW_DONE_ACK", 25, 25, &umr_bitfield_default }, + { "DC_I2C_DDC6_HW_DONE_MASK", 26, 26, &umr_bitfield_default }, + { "DC_I2C_DDCVGA_HW_DONE_INT", 27, 27, &umr_bitfield_default }, + { "DC_I2C_DDCVGA_HW_DONE_ACK", 28, 28, &umr_bitfield_default }, + { "DC_I2C_DDCVGA_HW_DONE_MASK", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_I2C_SW_STATUS[] = { + { "DC_I2C_SW_STATUS", 0, 1, &umr_bitfield_default }, + { "DC_I2C_SW_DONE", 2, 2, &umr_bitfield_default }, + { "DC_I2C_SW_ABORTED", 4, 4, &umr_bitfield_default }, + { "DC_I2C_SW_TIMEOUT", 5, 5, &umr_bitfield_default }, + { "DC_I2C_SW_INTERRUPTED", 6, 6, &umr_bitfield_default }, + { "DC_I2C_SW_BUFFER_OVERFLOW", 7, 7, &umr_bitfield_default }, + { "DC_I2C_SW_STOPPED_ON_NACK", 8, 8, &umr_bitfield_default }, + { "DC_I2C_SW_NACK0", 12, 12, &umr_bitfield_default }, + { "DC_I2C_SW_NACK1", 13, 13, &umr_bitfield_default }, + { "DC_I2C_SW_NACK2", 14, 14, &umr_bitfield_default }, + { "DC_I2C_SW_NACK3", 15, 15, &umr_bitfield_default }, + { "DC_I2C_SW_REQ", 18, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_I2C_DDC1_HW_STATUS[] = { + { "DC_I2C_DDC1_HW_STATUS", 0, 1, &umr_bitfield_default }, + { "DC_I2C_DDC1_HW_DONE", 3, 3, &umr_bitfield_default }, + { "DC_I2C_DDC1_HW_REQ", 16, 16, &umr_bitfield_default }, + { "DC_I2C_DDC1_HW_URG", 17, 17, &umr_bitfield_default }, + { "DC_I2C_DDC1_EDID_DETECT_STATUS", 20, 20, &umr_bitfield_default }, + { "DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES", 24, 27, &umr_bitfield_default }, + { "DC_I2C_DDC1_EDID_DETECT_STATE", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_I2C_DDC2_HW_STATUS[] = { + { "DC_I2C_DDC2_HW_STATUS", 0, 1, &umr_bitfield_default }, + { "DC_I2C_DDC2_HW_DONE", 3, 3, &umr_bitfield_default }, + { "DC_I2C_DDC2_HW_REQ", 16, 16, &umr_bitfield_default }, + { "DC_I2C_DDC2_HW_URG", 17, 17, &umr_bitfield_default }, + { "DC_I2C_DDC2_EDID_DETECT_STATUS", 20, 20, &umr_bitfield_default }, + { "DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES", 24, 27, &umr_bitfield_default }, + { "DC_I2C_DDC2_EDID_DETECT_STATE", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_I2C_DDC3_HW_STATUS[] = { + { "DC_I2C_DDC3_HW_STATUS", 0, 1, &umr_bitfield_default }, + { "DC_I2C_DDC3_HW_DONE", 3, 3, &umr_bitfield_default }, + { "DC_I2C_DDC3_HW_REQ", 16, 16, &umr_bitfield_default }, + { "DC_I2C_DDC3_HW_URG", 17, 17, &umr_bitfield_default }, + { "DC_I2C_DDC3_EDID_DETECT_STATUS", 20, 20, &umr_bitfield_default }, + { "DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES", 24, 27, &umr_bitfield_default }, + { "DC_I2C_DDC3_EDID_DETECT_STATE", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_I2C_DDC4_HW_STATUS[] = { + { "DC_I2C_DDC4_HW_STATUS", 0, 1, &umr_bitfield_default }, + { "DC_I2C_DDC4_HW_DONE", 3, 3, &umr_bitfield_default }, + { "DC_I2C_DDC4_HW_REQ", 16, 16, &umr_bitfield_default }, + { "DC_I2C_DDC4_HW_URG", 17, 17, &umr_bitfield_default }, + { "DC_I2C_DDC4_EDID_DETECT_STATUS", 20, 20, &umr_bitfield_default }, + { "DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES", 24, 27, &umr_bitfield_default }, + { "DC_I2C_DDC4_EDID_DETECT_STATE", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_I2C_DDC5_HW_STATUS[] = { + { "DC_I2C_DDC5_HW_STATUS", 0, 1, &umr_bitfield_default }, + { "DC_I2C_DDC5_HW_DONE", 3, 3, &umr_bitfield_default }, + { "DC_I2C_DDC5_HW_REQ", 16, 16, &umr_bitfield_default }, + { "DC_I2C_DDC5_HW_URG", 17, 17, &umr_bitfield_default }, + { "DC_I2C_DDC5_EDID_DETECT_STATUS", 20, 20, &umr_bitfield_default }, + { "DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES", 24, 27, &umr_bitfield_default }, + { "DC_I2C_DDC5_EDID_DETECT_STATE", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_I2C_DDC6_HW_STATUS[] = { + { "DC_I2C_DDC6_HW_STATUS", 0, 1, &umr_bitfield_default }, + { "DC_I2C_DDC6_HW_DONE", 3, 3, &umr_bitfield_default }, + { "DC_I2C_DDC6_HW_REQ", 16, 16, &umr_bitfield_default }, + { "DC_I2C_DDC6_HW_URG", 17, 17, &umr_bitfield_default }, + { "DC_I2C_DDC6_EDID_DETECT_STATUS", 20, 20, &umr_bitfield_default }, + { "DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES", 24, 27, &umr_bitfield_default }, + { "DC_I2C_DDC6_EDID_DETECT_STATE", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_I2C_DDC1_SPEED[] = { + { "DC_I2C_DDC1_THRESHOLD", 0, 1, &umr_bitfield_default }, + { "DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL", 4, 4, &umr_bitfield_default }, + { "DC_I2C_DDC1_START_STOP_TIMING_CNTL", 8, 9, &umr_bitfield_default }, + { "DC_I2C_DDC1_PRESCALE", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_I2C_DDC1_SETUP[] = { + { "DC_I2C_DDC1_DATA_DRIVE_EN", 0, 0, &umr_bitfield_default }, + { "DC_I2C_DDC1_DATA_DRIVE_SEL", 1, 1, &umr_bitfield_default }, + { "DC_I2C_DDC1_EDID_DETECT_ENABLE", 4, 4, &umr_bitfield_default }, + { "DC_I2C_DDC1_EDID_DETECT_MODE", 5, 5, &umr_bitfield_default }, + { "DC_I2C_DDC1_ENABLE", 6, 6, &umr_bitfield_default }, + { "DC_I2C_DDC1_CLK_DRIVE_EN", 7, 7, &umr_bitfield_default }, + { "DC_I2C_DDC1_INTRA_BYTE_DELAY", 8, 15, &umr_bitfield_default }, + { "DC_I2C_DDC1_INTRA_TRANSACTION_DELAY", 16, 23, &umr_bitfield_default }, + { "DC_I2C_DDC1_TIME_LIMIT", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_I2C_DDC2_SPEED[] = { + { "DC_I2C_DDC2_THRESHOLD", 0, 1, &umr_bitfield_default }, + { "DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL", 4, 4, &umr_bitfield_default }, + { "DC_I2C_DDC2_START_STOP_TIMING_CNTL", 8, 9, &umr_bitfield_default }, + { "DC_I2C_DDC2_PRESCALE", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_I2C_DDC2_SETUP[] = { + { "DC_I2C_DDC2_DATA_DRIVE_EN", 0, 0, &umr_bitfield_default }, + { "DC_I2C_DDC2_DATA_DRIVE_SEL", 1, 1, &umr_bitfield_default }, + { "DC_I2C_DDC2_EDID_DETECT_ENABLE", 4, 4, &umr_bitfield_default }, + { "DC_I2C_DDC2_EDID_DETECT_MODE", 5, 5, &umr_bitfield_default }, + { "DC_I2C_DDC2_ENABLE", 6, 6, &umr_bitfield_default }, + { "DC_I2C_DDC2_CLK_DRIVE_EN", 7, 7, &umr_bitfield_default }, + { "DC_I2C_DDC2_INTRA_BYTE_DELAY", 8, 15, &umr_bitfield_default }, + { "DC_I2C_DDC2_INTRA_TRANSACTION_DELAY", 16, 23, &umr_bitfield_default }, + { "DC_I2C_DDC2_TIME_LIMIT", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_I2C_DDC3_SPEED[] = { + { "DC_I2C_DDC3_THRESHOLD", 0, 1, &umr_bitfield_default }, + { "DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL", 4, 4, &umr_bitfield_default }, + { "DC_I2C_DDC3_START_STOP_TIMING_CNTL", 8, 9, &umr_bitfield_default }, + { "DC_I2C_DDC3_PRESCALE", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_I2C_DDC3_SETUP[] = { + { "DC_I2C_DDC3_DATA_DRIVE_EN", 0, 0, &umr_bitfield_default }, + { "DC_I2C_DDC3_DATA_DRIVE_SEL", 1, 1, &umr_bitfield_default }, + { "DC_I2C_DDC3_EDID_DETECT_ENABLE", 4, 4, &umr_bitfield_default }, + { "DC_I2C_DDC3_EDID_DETECT_MODE", 5, 5, &umr_bitfield_default }, + { "DC_I2C_DDC3_ENABLE", 6, 6, &umr_bitfield_default }, + { "DC_I2C_DDC3_CLK_DRIVE_EN", 7, 7, &umr_bitfield_default }, + { "DC_I2C_DDC3_INTRA_BYTE_DELAY", 8, 15, &umr_bitfield_default }, + { "DC_I2C_DDC3_INTRA_TRANSACTION_DELAY", 16, 23, &umr_bitfield_default }, + { "DC_I2C_DDC3_TIME_LIMIT", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_I2C_DDC4_SPEED[] = { + { "DC_I2C_DDC4_THRESHOLD", 0, 1, &umr_bitfield_default }, + { "DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL", 4, 4, &umr_bitfield_default }, + { "DC_I2C_DDC4_START_STOP_TIMING_CNTL", 8, 9, &umr_bitfield_default }, + { "DC_I2C_DDC4_PRESCALE", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_I2C_DDC4_SETUP[] = { + { "DC_I2C_DDC4_DATA_DRIVE_EN", 0, 0, &umr_bitfield_default }, + { "DC_I2C_DDC4_DATA_DRIVE_SEL", 1, 1, &umr_bitfield_default }, + { "DC_I2C_DDC4_EDID_DETECT_ENABLE", 4, 4, &umr_bitfield_default }, + { "DC_I2C_DDC4_EDID_DETECT_MODE", 5, 5, &umr_bitfield_default }, + { "DC_I2C_DDC4_ENABLE", 6, 6, &umr_bitfield_default }, + { "DC_I2C_DDC4_CLK_DRIVE_EN", 7, 7, &umr_bitfield_default }, + { "DC_I2C_DDC4_INTRA_BYTE_DELAY", 8, 15, &umr_bitfield_default }, + { "DC_I2C_DDC4_INTRA_TRANSACTION_DELAY", 16, 23, &umr_bitfield_default }, + { "DC_I2C_DDC4_TIME_LIMIT", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_I2C_DDC5_SPEED[] = { + { "DC_I2C_DDC5_THRESHOLD", 0, 1, &umr_bitfield_default }, + { "DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL", 4, 4, &umr_bitfield_default }, + { "DC_I2C_DDC5_START_STOP_TIMING_CNTL", 8, 9, &umr_bitfield_default }, + { "DC_I2C_DDC5_PRESCALE", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_I2C_DDC5_SETUP[] = { + { "DC_I2C_DDC5_DATA_DRIVE_EN", 0, 0, &umr_bitfield_default }, + { "DC_I2C_DDC5_DATA_DRIVE_SEL", 1, 1, &umr_bitfield_default }, + { "DC_I2C_DDC5_EDID_DETECT_ENABLE", 4, 4, &umr_bitfield_default }, + { "DC_I2C_DDC5_EDID_DETECT_MODE", 5, 5, &umr_bitfield_default }, + { "DC_I2C_DDC5_ENABLE", 6, 6, &umr_bitfield_default }, + { "DC_I2C_DDC5_CLK_DRIVE_EN", 7, 7, &umr_bitfield_default }, + { "DC_I2C_DDC5_INTRA_BYTE_DELAY", 8, 15, &umr_bitfield_default }, + { "DC_I2C_DDC5_INTRA_TRANSACTION_DELAY", 16, 23, &umr_bitfield_default }, + { "DC_I2C_DDC5_TIME_LIMIT", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_I2C_DDC6_SPEED[] = { + { "DC_I2C_DDC6_THRESHOLD", 0, 1, &umr_bitfield_default }, + { "DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL", 4, 4, &umr_bitfield_default }, + { "DC_I2C_DDC6_START_STOP_TIMING_CNTL", 8, 9, &umr_bitfield_default }, + { "DC_I2C_DDC6_PRESCALE", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_I2C_DDC6_SETUP[] = { + { "DC_I2C_DDC6_DATA_DRIVE_EN", 0, 0, &umr_bitfield_default }, + { "DC_I2C_DDC6_DATA_DRIVE_SEL", 1, 1, &umr_bitfield_default }, + { "DC_I2C_DDC6_EDID_DETECT_ENABLE", 4, 4, &umr_bitfield_default }, + { "DC_I2C_DDC6_EDID_DETECT_MODE", 5, 5, &umr_bitfield_default }, + { "DC_I2C_DDC6_ENABLE", 6, 6, &umr_bitfield_default }, + { "DC_I2C_DDC6_CLK_DRIVE_EN", 7, 7, &umr_bitfield_default }, + { "DC_I2C_DDC6_INTRA_BYTE_DELAY", 8, 15, &umr_bitfield_default }, + { "DC_I2C_DDC6_INTRA_TRANSACTION_DELAY", 16, 23, &umr_bitfield_default }, + { "DC_I2C_DDC6_TIME_LIMIT", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_I2C_TRANSACTION0[] = { + { "DC_I2C_RW0", 0, 0, &umr_bitfield_default }, + { "DC_I2C_STOP_ON_NACK0", 8, 8, &umr_bitfield_default }, + { "DC_I2C_START0", 12, 12, &umr_bitfield_default }, + { "DC_I2C_STOP0", 13, 13, &umr_bitfield_default }, + { "DC_I2C_COUNT0", 16, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_I2C_TRANSACTION1[] = { + { "DC_I2C_RW1", 0, 0, &umr_bitfield_default }, + { "DC_I2C_STOP_ON_NACK1", 8, 8, &umr_bitfield_default }, + { "DC_I2C_START1", 12, 12, &umr_bitfield_default }, + { "DC_I2C_STOP1", 13, 13, &umr_bitfield_default }, + { "DC_I2C_COUNT1", 16, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_I2C_TRANSACTION2[] = { + { "DC_I2C_RW2", 0, 0, &umr_bitfield_default }, + { "DC_I2C_STOP_ON_NACK2", 8, 8, &umr_bitfield_default }, + { "DC_I2C_START2", 12, 12, &umr_bitfield_default }, + { "DC_I2C_STOP2", 13, 13, &umr_bitfield_default }, + { "DC_I2C_COUNT2", 16, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_I2C_TRANSACTION3[] = { + { "DC_I2C_RW3", 0, 0, &umr_bitfield_default }, + { "DC_I2C_STOP_ON_NACK3", 8, 8, &umr_bitfield_default }, + { "DC_I2C_START3", 12, 12, &umr_bitfield_default }, + { "DC_I2C_STOP3", 13, 13, &umr_bitfield_default }, + { "DC_I2C_COUNT3", 16, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_I2C_DATA[] = { + { "DC_I2C_DATA_RW", 0, 0, &umr_bitfield_default }, + { "DC_I2C_DATA", 8, 15, &umr_bitfield_default }, + { "DC_I2C_INDEX", 16, 25, &umr_bitfield_default }, + { "DC_I2C_INDEX_WRITE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_I2C_DDCVGA_HW_STATUS[] = { + { "DC_I2C_DDCVGA_HW_STATUS", 0, 1, &umr_bitfield_default }, + { "DC_I2C_DDCVGA_HW_DONE", 3, 3, &umr_bitfield_default }, + { "DC_I2C_DDCVGA_HW_REQ", 16, 16, &umr_bitfield_default }, + { "DC_I2C_DDCVGA_HW_URG", 17, 17, &umr_bitfield_default }, + { "DC_I2C_DDCVGA_EDID_DETECT_STATUS", 20, 20, &umr_bitfield_default }, + { "DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES", 24, 27, &umr_bitfield_default }, + { "DC_I2C_DDCVGA_EDID_DETECT_STATE", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_I2C_DDCVGA_SPEED[] = { + { "DC_I2C_DDCVGA_THRESHOLD", 0, 1, &umr_bitfield_default }, + { "DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL", 4, 4, &umr_bitfield_default }, + { "DC_I2C_DDCVGA_START_STOP_TIMING_CNTL", 8, 9, &umr_bitfield_default }, + { "DC_I2C_DDCVGA_PRESCALE", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_I2C_DDCVGA_SETUP[] = { + { "DC_I2C_DDCVGA_DATA_DRIVE_EN", 0, 0, &umr_bitfield_default }, + { "DC_I2C_DDCVGA_DATA_DRIVE_SEL", 1, 1, &umr_bitfield_default }, + { "DC_I2C_DDCVGA_EDID_DETECT_ENABLE", 4, 4, &umr_bitfield_default }, + { "DC_I2C_DDCVGA_EDID_DETECT_MODE", 5, 5, &umr_bitfield_default }, + { "DC_I2C_DDCVGA_ENABLE", 6, 6, &umr_bitfield_default }, + { "DC_I2C_DDCVGA_CLK_DRIVE_EN", 7, 7, &umr_bitfield_default }, + { "DC_I2C_DDCVGA_INTRA_BYTE_DELAY", 8, 15, &umr_bitfield_default }, + { "DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY", 16, 23, &umr_bitfield_default }, + { "DC_I2C_DDCVGA_TIME_LIMIT", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_I2C_EDID_DETECT_CTRL[] = { + { "DC_I2C_EDID_DETECT_WAIT_TIME", 0, 15, &umr_bitfield_default }, + { "DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID", 20, 23, &umr_bitfield_default }, + { "DC_I2C_EDID_DETECT_SEND_RESET", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_I2C_READ_REQUEST_INTERRUPT[] = { + { "DC_I2C_DDC1_READ_REQUEST_OCCURRED", 0, 0, &umr_bitfield_default }, + { "DC_I2C_DDC1_READ_REQUEST_INT", 1, 1, &umr_bitfield_default }, + { "DC_I2C_DDC1_READ_REQUEST_ACK", 2, 2, &umr_bitfield_default }, + { "DC_I2C_DDC1_READ_REQUEST_MASK", 3, 3, &umr_bitfield_default }, + { "DC_I2C_DDC2_READ_REQUEST_OCCURRED", 4, 4, &umr_bitfield_default }, + { "DC_I2C_DDC2_READ_REQUEST_INT", 5, 5, &umr_bitfield_default }, + { "DC_I2C_DDC2_READ_REQUEST_ACK", 6, 6, &umr_bitfield_default }, + { "DC_I2C_DDC2_READ_REQUEST_MASK", 7, 7, &umr_bitfield_default }, + { "DC_I2C_DDC3_READ_REQUEST_OCCURRED", 8, 8, &umr_bitfield_default }, + { "DC_I2C_DDC3_READ_REQUEST_INT", 9, 9, &umr_bitfield_default }, + { "DC_I2C_DDC3_READ_REQUEST_ACK", 10, 10, &umr_bitfield_default }, + { "DC_I2C_DDC3_READ_REQUEST_MASK", 11, 11, &umr_bitfield_default }, + { "DC_I2C_DDC4_READ_REQUEST_OCCURRED", 12, 12, &umr_bitfield_default }, + { "DC_I2C_DDC4_READ_REQUEST_INT", 13, 13, &umr_bitfield_default }, + { "DC_I2C_DDC4_READ_REQUEST_ACK", 14, 14, &umr_bitfield_default }, + { "DC_I2C_DDC4_READ_REQUEST_MASK", 15, 15, &umr_bitfield_default }, + { "DC_I2C_DDC5_READ_REQUEST_OCCURRED", 16, 16, &umr_bitfield_default }, + { "DC_I2C_DDC5_READ_REQUEST_INT", 17, 17, &umr_bitfield_default }, + { "DC_I2C_DDC5_READ_REQUEST_ACK", 18, 18, &umr_bitfield_default }, + { "DC_I2C_DDC5_READ_REQUEST_MASK", 19, 19, &umr_bitfield_default }, + { "DC_I2C_DDC6_READ_REQUEST_OCCURRED", 20, 20, &umr_bitfield_default }, + { "DC_I2C_DDC6_READ_REQUEST_INT", 21, 21, &umr_bitfield_default }, + { "DC_I2C_DDC6_READ_REQUEST_ACK", 22, 22, &umr_bitfield_default }, + { "DC_I2C_DDC6_READ_REQUEST_MASK", 23, 23, &umr_bitfield_default }, + { "DC_I2C_DDCVGA_READ_REQUEST_OCCURRED", 24, 24, &umr_bitfield_default }, + { "DC_I2C_DDCVGA_READ_REQUEST_INT", 25, 25, &umr_bitfield_default }, + { "DC_I2C_DDCVGA_READ_REQUEST_ACK", 26, 26, &umr_bitfield_default }, + { "DC_I2C_DDCVGA_READ_REQUEST_MASK", 27, 27, &umr_bitfield_default }, + { "DC_I2C_DDC_READ_REQUEST_ACK_ENABLE", 30, 30, &umr_bitfield_default }, + { "DC_I2C_DDC_READ_REQUEST_INT_TYPE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGENERIC_I2C_CONTROL[] = { + { "GENERIC_I2C_GO", 0, 0, &umr_bitfield_default }, + { "GENERIC_I2C_SOFT_RESET", 1, 1, &umr_bitfield_default }, + { "GENERIC_I2C_SEND_RESET", 2, 2, &umr_bitfield_default }, + { "GENERIC_I2C_ENABLE", 3, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGENERIC_I2C_INTERRUPT_CONTROL[] = { + { "GENERIC_I2C_DONE_INT", 0, 0, &umr_bitfield_default }, + { "GENERIC_I2C_DONE_ACK", 1, 1, &umr_bitfield_default }, + { "GENERIC_I2C_DONE_MASK", 2, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGENERIC_I2C_STATUS[] = { + { "GENERIC_I2C_STATUS", 0, 3, &umr_bitfield_default }, + { "GENERIC_I2C_DONE", 4, 4, &umr_bitfield_default }, + { "GENERIC_I2C_ABORTED", 5, 5, &umr_bitfield_default }, + { "GENERIC_I2C_TIMEOUT", 6, 6, &umr_bitfield_default }, + { "GENERIC_I2C_STOPPED_ON_NACK", 9, 9, &umr_bitfield_default }, + { "GENERIC_I2C_NACK", 10, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGENERIC_I2C_SPEED[] = { + { "GENERIC_I2C_THRESHOLD", 0, 1, &umr_bitfield_default }, + { "GENERIC_I2C_DISABLE_FILTER_DURING_STALL", 4, 4, &umr_bitfield_default }, + { "GENERIC_I2C_START_STOP_TIMING_CNTL", 8, 9, &umr_bitfield_default }, + { "GENERIC_I2C_PRESCALE", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGENERIC_I2C_SETUP[] = { + { "GENERIC_I2C_DATA_DRIVE_EN", 0, 0, &umr_bitfield_default }, + { "GENERIC_I2C_DATA_DRIVE_SEL", 1, 1, &umr_bitfield_default }, + { "GENERIC_I2C_CLK_DRIVE_EN", 7, 7, &umr_bitfield_default }, + { "GENERIC_I2C_INTRA_BYTE_DELAY", 8, 15, &umr_bitfield_default }, + { "GENERIC_I2C_TIME_LIMIT", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGENERIC_I2C_TRANSACTION[] = { + { "GENERIC_I2C_RW", 0, 0, &umr_bitfield_default }, + { "GENERIC_I2C_STOP_ON_NACK", 8, 8, &umr_bitfield_default }, + { "GENERIC_I2C_ACK_ON_READ", 9, 9, &umr_bitfield_default }, + { "GENERIC_I2C_START", 12, 12, &umr_bitfield_default }, + { "GENERIC_I2C_STOP", 13, 13, &umr_bitfield_default }, + { "GENERIC_I2C_COUNT", 16, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGENERIC_I2C_DATA[] = { + { "GENERIC_I2C_DATA_RW", 0, 0, &umr_bitfield_default }, + { "GENERIC_I2C_DATA", 8, 15, &umr_bitfield_default }, + { "GENERIC_I2C_INDEX", 16, 19, &umr_bitfield_default }, + { "GENERIC_I2C_INDEX_WRITE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGENERIC_I2C_PIN_SELECTION[] = { + { "GENERIC_I2C_SCL_PIN_SEL", 0, 6, &umr_bitfield_default }, + { "GENERIC_I2C_SDA_PIN_SEL", 8, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIO_SCRATCH0[] = { + { "DIO_SCRATCH0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIO_SCRATCH1[] = { + { "DIO_SCRATCH1", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIO_SCRATCH2[] = { + { "DIO_SCRATCH2", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIO_SCRATCH3[] = { + { "DIO_SCRATCH3", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIO_SCRATCH4[] = { + { "DIO_SCRATCH4", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIO_SCRATCH5[] = { + { "DIO_SCRATCH5", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIO_SCRATCH6[] = { + { "DIO_SCRATCH6", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIO_SCRATCH7[] = { + { "DIO_SCRATCH7", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCE_VCE_CONTROL[] = { + { "DC_VCE_AUDIO_STREAM_SELECT", 4, 6, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIO_MEM_PWR_STATUS[] = { + { "I2C_MEM_PWR_STATE", 0, 0, &umr_bitfield_default }, + { "DPA_MEM_PWR_STATE", 3, 3, &umr_bitfield_default }, + { "DPB_MEM_PWR_STATE", 4, 4, &umr_bitfield_default }, + { "DPC_MEM_PWR_STATE", 5, 5, &umr_bitfield_default }, + { "DPD_MEM_PWR_STATE", 6, 6, &umr_bitfield_default }, + { "DPE_MEM_PWR_STATE", 7, 7, &umr_bitfield_default }, + { "DPF_MEM_PWR_STATE", 8, 8, &umr_bitfield_default }, + { "DPG_MEM_PWR_STATE", 9, 9, &umr_bitfield_default }, + { "HDMI0_MEM_PWR_STATE", 10, 11, &umr_bitfield_default }, + { "HDMI1_MEM_PWR_STATE", 12, 13, &umr_bitfield_default }, + { "HDMI2_MEM_PWR_STATE", 14, 15, &umr_bitfield_default }, + { "HDMI3_MEM_PWR_STATE", 16, 17, &umr_bitfield_default }, + { "HDMI4_MEM_PWR_STATE", 18, 19, &umr_bitfield_default }, + { "HDMI5_MEM_PWR_STATE", 20, 21, &umr_bitfield_default }, + { "HDMI6_MEM_PWR_STATE", 22, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIO_MEM_PWR_CTRL[] = { + { "I2C_LIGHT_SLEEP_FORCE", 0, 0, &umr_bitfield_default }, + { "I2C_LIGHT_SLEEP_DIS", 1, 1, &umr_bitfield_default }, + { "DPA_LIGHT_SLEEP_DIS", 4, 4, &umr_bitfield_default }, + { "DPB_LIGHT_SLEEP_DIS", 5, 5, &umr_bitfield_default }, + { "DPC_LIGHT_SLEEP_DIS", 6, 6, &umr_bitfield_default }, + { "DPD_LIGHT_SLEEP_DIS", 7, 7, &umr_bitfield_default }, + { "DPE_LIGHT_SLEEP_DIS", 8, 8, &umr_bitfield_default }, + { "DPF_LIGHT_SLEEP_DIS", 9, 9, &umr_bitfield_default }, + { "DPG_LIGHT_SLEEP_DIS", 10, 10, &umr_bitfield_default }, + { "HDMI0_MEM_PWR_FORCE", 11, 12, &umr_bitfield_default }, + { "HDMI0_MEM_PWR_DIS", 13, 13, &umr_bitfield_default }, + { "HDMI1_MEM_PWR_FORCE", 14, 15, &umr_bitfield_default }, + { "HDMI1_MEM_PWR_DIS", 16, 16, &umr_bitfield_default }, + { "HDMI2_MEM_PWR_FORCE", 17, 18, &umr_bitfield_default }, + { "HDMI2_MEM_PWR_DIS", 19, 19, &umr_bitfield_default }, + { "HDMI3_MEM_PWR_FORCE", 20, 21, &umr_bitfield_default }, + { "HDMI3_MEM_PWR_DIS", 22, 22, &umr_bitfield_default }, + { "HDMI4_MEM_PWR_FORCE", 23, 24, &umr_bitfield_default }, + { "HDMI4_MEM_PWR_DIS", 25, 25, &umr_bitfield_default }, + { "HDMI5_MEM_PWR_FORCE", 26, 27, &umr_bitfield_default }, + { "HDMI5_MEM_PWR_DIS", 28, 28, &umr_bitfield_default }, + { "HDMI6_MEM_PWR_FORCE", 29, 30, &umr_bitfield_default }, + { "HDMI6_MEM_PWR_DIS", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIO_MEM_PWR_CTRL2[] = { + { "HDMI_MEM_PWR_MODE_SEL", 0, 1, &umr_bitfield_default }, + { "AFMT0_LIGHT_SLEEP_DIS", 4, 4, &umr_bitfield_default }, + { "AFMT0_LIGHT_SLEEP_FORCE", 5, 5, &umr_bitfield_default }, + { "AFMT1_LIGHT_SLEEP_DIS", 6, 6, &umr_bitfield_default }, + { "AFMT1_LIGHT_SLEEP_FORCE", 7, 7, &umr_bitfield_default }, + { "AFMT2_LIGHT_SLEEP_DIS", 8, 8, &umr_bitfield_default }, + { "AFMT2_LIGHT_SLEEP_FORCE", 9, 9, &umr_bitfield_default }, + { "AFMT3_LIGHT_SLEEP_DIS", 10, 10, &umr_bitfield_default }, + { "AFMT3_LIGHT_SLEEP_FORCE", 11, 11, &umr_bitfield_default }, + { "AFMT4_LIGHT_SLEEP_DIS", 12, 12, &umr_bitfield_default }, + { "AFMT4_LIGHT_SLEEP_FORCE", 13, 13, &umr_bitfield_default }, + { "AFMT5_LIGHT_SLEEP_DIS", 14, 14, &umr_bitfield_default }, + { "AFMT5_LIGHT_SLEEP_FORCE", 15, 15, &umr_bitfield_default }, + { "DPA_LIGHT_SLEEP_FORCE", 24, 24, &umr_bitfield_default }, + { "DPB_LIGHT_SLEEP_FORCE", 25, 25, &umr_bitfield_default }, + { "DPC_LIGHT_SLEEP_FORCE", 26, 26, &umr_bitfield_default }, + { "DPD_LIGHT_SLEEP_FORCE", 27, 27, &umr_bitfield_default }, + { "DPE_LIGHT_SLEEP_FORCE", 28, 28, &umr_bitfield_default }, + { "DPF_LIGHT_SLEEP_FORCE", 29, 29, &umr_bitfield_default }, + { "DPG_LIGHT_SLEEP_FORCE", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIO_CLK_CNTL[] = { + { "DISPCLK_R_DIO_GATE_DIS", 5, 5, &umr_bitfield_default }, + { "DISPCLK_G_DVO_GATE_DIS", 7, 7, &umr_bitfield_default }, + { "DISPCLK_G_DACA_GATE_DIS", 8, 8, &umr_bitfield_default }, + { "REFCLK_R_DIO_GATE_DIS", 10, 10, &umr_bitfield_default }, + { "DISPCLK_G_DIGA_GATE_DIS", 24, 24, &umr_bitfield_default }, + { "DISPCLK_G_DIGB_GATE_DIS", 25, 25, &umr_bitfield_default }, + { "DISPCLK_G_DIGC_GATE_DIS", 26, 26, &umr_bitfield_default }, + { "DISPCLK_G_DIGD_GATE_DIS", 27, 27, &umr_bitfield_default }, + { "DISPCLK_G_DIGE_GATE_DIS", 28, 28, &umr_bitfield_default }, + { "DISPCLK_G_DIGF_GATE_DIS", 29, 29, &umr_bitfield_default }, + { "DISPCLK_G_DIGG_GATE_DIS", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIO_POWER_MANAGEMENT_CNTL[] = { + { "PM_ASSERT_RESET", 0, 0, &umr_bitfield_default }, + { "PM_ALL_BUSY_OFF", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIO_STEREOSYNC_SEL[] = { + { "GENERICA_STEREOSYNC_SEL", 0, 2, &umr_bitfield_default }, + { "GENERICB_STEREOSYNC_SEL", 16, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIO_SOFT_RESET[] = { + { "DACA_SOFT_RESET", 0, 0, &umr_bitfield_default }, + { "I2S0_SPDIF0_SOFT_RESET", 4, 4, &umr_bitfield_default }, + { "I2S1_SOFT_RESET", 5, 5, &umr_bitfield_default }, + { "SPDIF1_SOFT_RESET", 6, 6, &umr_bitfield_default }, + { "DB_CLK_SOFT_RESET", 12, 12, &umr_bitfield_default }, + { "DVO_SOFT_RESET", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG_SOFT_RESET[] = { + { "DIGA_FE_SOFT_RESET", 0, 0, &umr_bitfield_default }, + { "DIGA_BE_SOFT_RESET", 1, 1, &umr_bitfield_default }, + { "DIGB_FE_SOFT_RESET", 4, 4, &umr_bitfield_default }, + { "DIGB_BE_SOFT_RESET", 5, 5, &umr_bitfield_default }, + { "DIGC_FE_SOFT_RESET", 8, 8, &umr_bitfield_default }, + { "DIGC_BE_SOFT_RESET", 9, 9, &umr_bitfield_default }, + { "DIGD_FE_SOFT_RESET", 12, 12, &umr_bitfield_default }, + { "DIGD_BE_SOFT_RESET", 13, 13, &umr_bitfield_default }, + { "DIGE_FE_SOFT_RESET", 16, 16, &umr_bitfield_default }, + { "DIGE_BE_SOFT_RESET", 17, 17, &umr_bitfield_default }, + { "DIGF_FE_SOFT_RESET", 20, 20, &umr_bitfield_default }, + { "DIGF_BE_SOFT_RESET", 21, 21, &umr_bitfield_default }, + { "DIGG_FE_SOFT_RESET", 24, 24, &umr_bitfield_default }, + { "DIGG_BE_SOFT_RESET", 25, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIO_MEM_PWR_STATUS1[] = { + { "AFMT0_MEM_PWR_STATE", 0, 0, &umr_bitfield_default }, + { "AFMT1_MEM_PWR_STATE", 2, 2, &umr_bitfield_default }, + { "AFMT2_MEM_PWR_STATE", 4, 4, &umr_bitfield_default }, + { "AFMT3_MEM_PWR_STATE", 6, 6, &umr_bitfield_default }, + { "AFMT4_MEM_PWR_STATE", 8, 8, &umr_bitfield_default }, + { "AFMT5_MEM_PWR_STATE", 10, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIO_CLK_CNTL2[] = { + { "DIO_TEST_CLK_SEL", 0, 6, &umr_bitfield_default }, + { "SOCCLK_G_AFMTA_GATE_DIS", 7, 7, &umr_bitfield_default }, + { "SOCCLK_G_AFMTB_GATE_DIS", 8, 8, &umr_bitfield_default }, + { "SOCCLK_G_AFMTC_GATE_DIS", 9, 9, &umr_bitfield_default }, + { "SOCCLK_G_AFMTD_GATE_DIS", 10, 10, &umr_bitfield_default }, + { "SOCCLK_G_AFMTE_GATE_DIS", 11, 11, &umr_bitfield_default }, + { "SOCCLK_G_AFMTF_GATE_DIS", 12, 12, &umr_bitfield_default }, + { "SOCCLK_G_AFMTG_GATE_DIS", 13, 13, &umr_bitfield_default }, + { "SYMCLKA_FE_G_AFMT_GATE_DIS", 17, 17, &umr_bitfield_default }, + { "SYMCLKB_FE_G_AFMT_GATE_DIS", 18, 18, &umr_bitfield_default }, + { "SYMCLKC_FE_G_AFMT_GATE_DIS", 19, 19, &umr_bitfield_default }, + { "SYMCLKD_FE_G_AFMT_GATE_DIS", 20, 20, &umr_bitfield_default }, + { "SYMCLKE_FE_G_AFMT_GATE_DIS", 21, 21, &umr_bitfield_default }, + { "SYMCLKF_FE_G_AFMT_GATE_DIS", 22, 22, &umr_bitfield_default }, + { "SYMCLKG_FE_G_AFMT_GATE_DIS", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIO_CLK_CNTL3[] = { + { "SYMCLKA_FE_G_TMDS_GATE_DIS", 0, 0, &umr_bitfield_default }, + { "SYMCLKB_FE_G_TMDS_GATE_DIS", 1, 1, &umr_bitfield_default }, + { "SYMCLKC_FE_G_TMDS_GATE_DIS", 2, 2, &umr_bitfield_default }, + { "SYMCLKD_FE_G_TMDS_GATE_DIS", 3, 3, &umr_bitfield_default }, + { "SYMCLKE_FE_G_TMDS_GATE_DIS", 4, 4, &umr_bitfield_default }, + { "SYMCLKF_FE_G_TMDS_GATE_DIS", 5, 5, &umr_bitfield_default }, + { "SYMCLKG_FE_G_TMDS_GATE_DIS", 6, 6, &umr_bitfield_default }, + { "SYMCLKA_G_TMDS_GATE_DIS", 10, 10, &umr_bitfield_default }, + { "SYMCLKB_G_TMDS_GATE_DIS", 11, 11, &umr_bitfield_default }, + { "SYMCLKC_G_TMDS_GATE_DIS", 12, 12, &umr_bitfield_default }, + { "SYMCLKD_G_TMDS_GATE_DIS", 13, 13, &umr_bitfield_default }, + { "SYMCLKE_G_TMDS_GATE_DIS", 14, 14, &umr_bitfield_default }, + { "SYMCLKF_G_TMDS_GATE_DIS", 15, 15, &umr_bitfield_default }, + { "SYMCLKG_G_TMDS_GATE_DIS", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIO_HDMI_RXSTATUS_TIMER_CONTROL[] = { + { "DIO_HDMI_RXSTATUS_TIMER_ENABLE", 0, 0, &umr_bitfield_default }, + { "DIO_HDMI_RXSTATUS_TIMER_TYPE", 4, 4, &umr_bitfield_default }, + { "DIO_HDMI_RXSTATUS_TIMER_STATUS", 8, 8, &umr_bitfield_default }, + { "DIO_HDMI_RXSTATUS_TIMER_MASK", 12, 12, &umr_bitfield_default }, + { "DIO_HDMI_RXSTATUS_TIMER_INTERVAL", 16, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIO_PSP_INTERRUPT_STATUS[] = { + { "DIO_PSP_INTERRUPT_STATUS", 0, 0, &umr_bitfield_default }, + { "DIO_PSP_INTERRUPT_MESSAGE", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIO_PSP_INTERRUPT_CLEAR[] = { + { "DIO_PSP_INTERRUPT_CLEAR", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIO_GENERIC_INTERRUPT_MESSAGE[] = { + { "DIO_GENERIC_INTERRUPT_STATUS", 0, 0, &umr_bitfield_default }, + { "DIO_GENERIC_INTERRUPT_MESSAGE", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIO_GENERIC_INTERRUPT_CLEAR[] = { + { "DIO_GENERIC_INTERRUPT_CLEAR", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHPD0_DC_HPD_INT_STATUS[] = { + { "DC_HPD_INT_STATUS", 0, 0, &umr_bitfield_default }, + { "DC_HPD_SENSE", 1, 1, &umr_bitfield_default }, + { "DC_HPD_SENSE_DELAYED", 4, 4, &umr_bitfield_default }, + { "DC_HPD_RX_INT_STATUS", 8, 8, &umr_bitfield_default }, + { "DC_HPD_TOGGLE_FILT_CON_TIMER_VAL", 12, 19, &umr_bitfield_default }, + { "DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHPD0_DC_HPD_INT_CONTROL[] = { + { "DC_HPD_INT_ACK", 0, 0, &umr_bitfield_default }, + { "DC_HPD_INT_POLARITY", 8, 8, &umr_bitfield_default }, + { "DC_HPD_INT_EN", 16, 16, &umr_bitfield_default }, + { "DC_HPD_RX_INT_ACK", 20, 20, &umr_bitfield_default }, + { "DC_HPD_RX_INT_EN", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHPD0_DC_HPD_CONTROL[] = { + { "DC_HPD_CONNECTION_TIMER", 0, 12, &umr_bitfield_default }, + { "DC_HPD_RX_INT_TIMER", 16, 25, &umr_bitfield_default }, + { "DC_HPD_EN", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHPD0_DC_HPD_FAST_TRAIN_CNTL[] = { + { "DC_HPD_CONNECT_AUX_TX_DELAY", 0, 7, &umr_bitfield_default }, + { "DC_HPD_CONNECT_FAST_TRAIN_DELAY", 12, 19, &umr_bitfield_default }, + { "DC_HPD_CONNECT_AUX_TX_EN", 24, 24, &umr_bitfield_default }, + { "DC_HPD_CONNECT_FAST_TRAIN_EN", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHPD0_DC_HPD_TOGGLE_FILT_CNTL[] = { + { "DC_HPD_CONNECT_INT_DELAY", 0, 7, &umr_bitfield_default }, + { "DC_HPD_DISCONNECT_INT_DELAY", 20, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHPD1_DC_HPD_INT_STATUS[] = { + { "DC_HPD_INT_STATUS", 0, 0, &umr_bitfield_default }, + { "DC_HPD_SENSE", 1, 1, &umr_bitfield_default }, + { "DC_HPD_SENSE_DELAYED", 4, 4, &umr_bitfield_default }, + { "DC_HPD_RX_INT_STATUS", 8, 8, &umr_bitfield_default }, + { "DC_HPD_TOGGLE_FILT_CON_TIMER_VAL", 12, 19, &umr_bitfield_default }, + { "DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHPD1_DC_HPD_INT_CONTROL[] = { + { "DC_HPD_INT_ACK", 0, 0, &umr_bitfield_default }, + { "DC_HPD_INT_POLARITY", 8, 8, &umr_bitfield_default }, + { "DC_HPD_INT_EN", 16, 16, &umr_bitfield_default }, + { "DC_HPD_RX_INT_ACK", 20, 20, &umr_bitfield_default }, + { "DC_HPD_RX_INT_EN", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHPD1_DC_HPD_CONTROL[] = { + { "DC_HPD_CONNECTION_TIMER", 0, 12, &umr_bitfield_default }, + { "DC_HPD_RX_INT_TIMER", 16, 25, &umr_bitfield_default }, + { "DC_HPD_EN", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHPD1_DC_HPD_FAST_TRAIN_CNTL[] = { + { "DC_HPD_CONNECT_AUX_TX_DELAY", 0, 7, &umr_bitfield_default }, + { "DC_HPD_CONNECT_FAST_TRAIN_DELAY", 12, 19, &umr_bitfield_default }, + { "DC_HPD_CONNECT_AUX_TX_EN", 24, 24, &umr_bitfield_default }, + { "DC_HPD_CONNECT_FAST_TRAIN_EN", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHPD1_DC_HPD_TOGGLE_FILT_CNTL[] = { + { "DC_HPD_CONNECT_INT_DELAY", 0, 7, &umr_bitfield_default }, + { "DC_HPD_DISCONNECT_INT_DELAY", 20, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHPD2_DC_HPD_INT_STATUS[] = { + { "DC_HPD_INT_STATUS", 0, 0, &umr_bitfield_default }, + { "DC_HPD_SENSE", 1, 1, &umr_bitfield_default }, + { "DC_HPD_SENSE_DELAYED", 4, 4, &umr_bitfield_default }, + { "DC_HPD_RX_INT_STATUS", 8, 8, &umr_bitfield_default }, + { "DC_HPD_TOGGLE_FILT_CON_TIMER_VAL", 12, 19, &umr_bitfield_default }, + { "DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHPD2_DC_HPD_INT_CONTROL[] = { + { "DC_HPD_INT_ACK", 0, 0, &umr_bitfield_default }, + { "DC_HPD_INT_POLARITY", 8, 8, &umr_bitfield_default }, + { "DC_HPD_INT_EN", 16, 16, &umr_bitfield_default }, + { "DC_HPD_RX_INT_ACK", 20, 20, &umr_bitfield_default }, + { "DC_HPD_RX_INT_EN", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHPD2_DC_HPD_CONTROL[] = { + { "DC_HPD_CONNECTION_TIMER", 0, 12, &umr_bitfield_default }, + { "DC_HPD_RX_INT_TIMER", 16, 25, &umr_bitfield_default }, + { "DC_HPD_EN", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHPD2_DC_HPD_FAST_TRAIN_CNTL[] = { + { "DC_HPD_CONNECT_AUX_TX_DELAY", 0, 7, &umr_bitfield_default }, + { "DC_HPD_CONNECT_FAST_TRAIN_DELAY", 12, 19, &umr_bitfield_default }, + { "DC_HPD_CONNECT_AUX_TX_EN", 24, 24, &umr_bitfield_default }, + { "DC_HPD_CONNECT_FAST_TRAIN_EN", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHPD2_DC_HPD_TOGGLE_FILT_CNTL[] = { + { "DC_HPD_CONNECT_INT_DELAY", 0, 7, &umr_bitfield_default }, + { "DC_HPD_DISCONNECT_INT_DELAY", 20, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHPD3_DC_HPD_INT_STATUS[] = { + { "DC_HPD_INT_STATUS", 0, 0, &umr_bitfield_default }, + { "DC_HPD_SENSE", 1, 1, &umr_bitfield_default }, + { "DC_HPD_SENSE_DELAYED", 4, 4, &umr_bitfield_default }, + { "DC_HPD_RX_INT_STATUS", 8, 8, &umr_bitfield_default }, + { "DC_HPD_TOGGLE_FILT_CON_TIMER_VAL", 12, 19, &umr_bitfield_default }, + { "DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHPD3_DC_HPD_INT_CONTROL[] = { + { "DC_HPD_INT_ACK", 0, 0, &umr_bitfield_default }, + { "DC_HPD_INT_POLARITY", 8, 8, &umr_bitfield_default }, + { "DC_HPD_INT_EN", 16, 16, &umr_bitfield_default }, + { "DC_HPD_RX_INT_ACK", 20, 20, &umr_bitfield_default }, + { "DC_HPD_RX_INT_EN", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHPD3_DC_HPD_CONTROL[] = { + { "DC_HPD_CONNECTION_TIMER", 0, 12, &umr_bitfield_default }, + { "DC_HPD_RX_INT_TIMER", 16, 25, &umr_bitfield_default }, + { "DC_HPD_EN", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHPD3_DC_HPD_FAST_TRAIN_CNTL[] = { + { "DC_HPD_CONNECT_AUX_TX_DELAY", 0, 7, &umr_bitfield_default }, + { "DC_HPD_CONNECT_FAST_TRAIN_DELAY", 12, 19, &umr_bitfield_default }, + { "DC_HPD_CONNECT_AUX_TX_EN", 24, 24, &umr_bitfield_default }, + { "DC_HPD_CONNECT_FAST_TRAIN_EN", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHPD3_DC_HPD_TOGGLE_FILT_CNTL[] = { + { "DC_HPD_CONNECT_INT_DELAY", 0, 7, &umr_bitfield_default }, + { "DC_HPD_DISCONNECT_INT_DELAY", 20, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHPD4_DC_HPD_INT_STATUS[] = { + { "DC_HPD_INT_STATUS", 0, 0, &umr_bitfield_default }, + { "DC_HPD_SENSE", 1, 1, &umr_bitfield_default }, + { "DC_HPD_SENSE_DELAYED", 4, 4, &umr_bitfield_default }, + { "DC_HPD_RX_INT_STATUS", 8, 8, &umr_bitfield_default }, + { "DC_HPD_TOGGLE_FILT_CON_TIMER_VAL", 12, 19, &umr_bitfield_default }, + { "DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHPD4_DC_HPD_INT_CONTROL[] = { + { "DC_HPD_INT_ACK", 0, 0, &umr_bitfield_default }, + { "DC_HPD_INT_POLARITY", 8, 8, &umr_bitfield_default }, + { "DC_HPD_INT_EN", 16, 16, &umr_bitfield_default }, + { "DC_HPD_RX_INT_ACK", 20, 20, &umr_bitfield_default }, + { "DC_HPD_RX_INT_EN", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHPD4_DC_HPD_CONTROL[] = { + { "DC_HPD_CONNECTION_TIMER", 0, 12, &umr_bitfield_default }, + { "DC_HPD_RX_INT_TIMER", 16, 25, &umr_bitfield_default }, + { "DC_HPD_EN", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHPD4_DC_HPD_FAST_TRAIN_CNTL[] = { + { "DC_HPD_CONNECT_AUX_TX_DELAY", 0, 7, &umr_bitfield_default }, + { "DC_HPD_CONNECT_FAST_TRAIN_DELAY", 12, 19, &umr_bitfield_default }, + { "DC_HPD_CONNECT_AUX_TX_EN", 24, 24, &umr_bitfield_default }, + { "DC_HPD_CONNECT_FAST_TRAIN_EN", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHPD4_DC_HPD_TOGGLE_FILT_CNTL[] = { + { "DC_HPD_CONNECT_INT_DELAY", 0, 7, &umr_bitfield_default }, + { "DC_HPD_DISCONNECT_INT_DELAY", 20, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHPD5_DC_HPD_INT_STATUS[] = { + { "DC_HPD_INT_STATUS", 0, 0, &umr_bitfield_default }, + { "DC_HPD_SENSE", 1, 1, &umr_bitfield_default }, + { "DC_HPD_SENSE_DELAYED", 4, 4, &umr_bitfield_default }, + { "DC_HPD_RX_INT_STATUS", 8, 8, &umr_bitfield_default }, + { "DC_HPD_TOGGLE_FILT_CON_TIMER_VAL", 12, 19, &umr_bitfield_default }, + { "DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHPD5_DC_HPD_INT_CONTROL[] = { + { "DC_HPD_INT_ACK", 0, 0, &umr_bitfield_default }, + { "DC_HPD_INT_POLARITY", 8, 8, &umr_bitfield_default }, + { "DC_HPD_INT_EN", 16, 16, &umr_bitfield_default }, + { "DC_HPD_RX_INT_ACK", 20, 20, &umr_bitfield_default }, + { "DC_HPD_RX_INT_EN", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHPD5_DC_HPD_CONTROL[] = { + { "DC_HPD_CONNECTION_TIMER", 0, 12, &umr_bitfield_default }, + { "DC_HPD_RX_INT_TIMER", 16, 25, &umr_bitfield_default }, + { "DC_HPD_EN", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHPD5_DC_HPD_FAST_TRAIN_CNTL[] = { + { "DC_HPD_CONNECT_AUX_TX_DELAY", 0, 7, &umr_bitfield_default }, + { "DC_HPD_CONNECT_FAST_TRAIN_DELAY", 12, 19, &umr_bitfield_default }, + { "DC_HPD_CONNECT_AUX_TX_EN", 24, 24, &umr_bitfield_default }, + { "DC_HPD_CONNECT_FAST_TRAIN_EN", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHPD5_DC_HPD_TOGGLE_FILT_CNTL[] = { + { "DC_HPD_CONNECT_INT_DELAY", 0, 7, &umr_bitfield_default }, + { "DC_HPD_DISCONNECT_INT_DELAY", 20, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON19_PERFCOUNTER_CNTL[] = { + { "PERFCOUNTER_EVENT_SEL", 0, 8, &umr_bitfield_default }, + { "PERFCOUNTER_CVALUE_SEL", 9, 11, &umr_bitfield_default }, + { "PERFCOUNTER_INC_MODE", 12, 14, &umr_bitfield_default }, + { "PERFCOUNTER_HW_CNTL_SEL", 15, 15, &umr_bitfield_default }, + { "PERFCOUNTER_RUNEN_MODE", 16, 16, &umr_bitfield_default }, + { "PERFCOUNTER_CNTOFF_START_DIS", 22, 22, &umr_bitfield_default }, + { "PERFCOUNTER_RESTART_EN", 23, 23, &umr_bitfield_default }, + { "PERFCOUNTER_INT_EN", 24, 24, &umr_bitfield_default }, + { "PERFCOUNTER_OFF_MASK", 25, 25, &umr_bitfield_default }, + { "PERFCOUNTER_ACTIVE", 26, 26, &umr_bitfield_default }, + { "PERFCOUNTER_CNTL_SEL", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON19_PERFCOUNTER_CNTL2[] = { + { "PERFCOUNTER_COUNTED_VALUE_TYPE", 0, 1, &umr_bitfield_default }, + { "PERFCOUNTER_HW_STOP1_SEL", 2, 2, &umr_bitfield_default }, + { "PERFCOUNTER_HW_STOP2_SEL", 3, 3, &umr_bitfield_default }, + { "PERFCOUNTER_CNTOFF_SEL", 8, 13, &umr_bitfield_default }, + { "PERFCOUNTER_CNTL2_SEL", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON19_PERFCOUNTER_STATE[] = { + { "PERFCOUNTER_CNT0_STATE", 0, 1, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL0", 2, 2, &umr_bitfield_default }, + { "PERFCOUNTER_CNT1_STATE", 4, 5, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL1", 6, 6, &umr_bitfield_default }, + { "PERFCOUNTER_CNT2_STATE", 8, 9, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL2", 10, 10, &umr_bitfield_default }, + { "PERFCOUNTER_CNT3_STATE", 12, 13, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL3", 14, 14, &umr_bitfield_default }, + { "PERFCOUNTER_CNT4_STATE", 16, 17, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL4", 18, 18, &umr_bitfield_default }, + { "PERFCOUNTER_CNT5_STATE", 20, 21, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL5", 22, 22, &umr_bitfield_default }, + { "PERFCOUNTER_CNT6_STATE", 24, 25, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL6", 26, 26, &umr_bitfield_default }, + { "PERFCOUNTER_CNT7_STATE", 28, 29, &umr_bitfield_default }, + { "PERFCOUNTER_STATE_SEL7", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON19_PERFMON_CNTL[] = { + { "PERFMON_STATE", 0, 1, &umr_bitfield_default }, + { "PERFMON_RPT_COUNT", 8, 27, &umr_bitfield_default }, + { "PERFMON_CNTOFF_AND_OR", 28, 28, &umr_bitfield_default }, + { "PERFMON_CNTOFF_INT_EN", 29, 29, &umr_bitfield_default }, + { "PERFMON_CNTOFF_INT_STATUS", 30, 30, &umr_bitfield_default }, + { "PERFMON_CNTOFF_INT_ACK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON19_PERFMON_CNTL2[] = { + { "PERFMON_CNTOFF_INT_TYPE", 0, 0, &umr_bitfield_default }, + { "PERFMON_CLK_ENABLE", 1, 1, &umr_bitfield_default }, + { "PERFMON_RUN_ENABLE_START_SEL", 2, 9, &umr_bitfield_default }, + { "PERFMON_RUN_ENABLE_STOP_SEL", 10, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON19_PERFMON_CVALUE_INT_MISC[] = { + { "PERFCOUNTER_INT0_STATUS", 0, 0, &umr_bitfield_default }, + { "PERFCOUNTER_INT1_STATUS", 1, 1, &umr_bitfield_default }, + { "PERFCOUNTER_INT2_STATUS", 2, 2, &umr_bitfield_default }, + { "PERFCOUNTER_INT3_STATUS", 3, 3, &umr_bitfield_default }, + { "PERFCOUNTER_INT4_STATUS", 4, 4, &umr_bitfield_default }, + { "PERFCOUNTER_INT5_STATUS", 5, 5, &umr_bitfield_default }, + { "PERFCOUNTER_INT6_STATUS", 6, 6, &umr_bitfield_default }, + { "PERFCOUNTER_INT7_STATUS", 7, 7, &umr_bitfield_default }, + { "PERFCOUNTER_INT0_ACK", 8, 8, &umr_bitfield_default }, + { "PERFCOUNTER_INT1_ACK", 9, 9, &umr_bitfield_default }, + { "PERFCOUNTER_INT2_ACK", 10, 10, &umr_bitfield_default }, + { "PERFCOUNTER_INT3_ACK", 11, 11, &umr_bitfield_default }, + { "PERFCOUNTER_INT4_ACK", 12, 12, &umr_bitfield_default }, + { "PERFCOUNTER_INT5_ACK", 13, 13, &umr_bitfield_default }, + { "PERFCOUNTER_INT6_ACK", 14, 14, &umr_bitfield_default }, + { "PERFCOUNTER_INT7_ACK", 15, 15, &umr_bitfield_default }, + { "PERFMON_CVALUE_HI", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON19_PERFMON_CVALUE_LOW[] = { + { "PERFMON_CVALUE_LOW", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON19_PERFMON_HI[] = { + { "PERFMON_HI", 0, 15, &umr_bitfield_default }, + { "PERFMON_READ_SEL", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_PERFMON19_PERFMON_LOW[] = { + { "PERFMON_LOW", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX0_AUX_CONTROL[] = { + { "AUX_EN", 0, 0, &umr_bitfield_default }, + { "AUX_RESET", 4, 4, &umr_bitfield_default }, + { "AUX_RESET_DONE", 5, 5, &umr_bitfield_default }, + { "AUX_LS_READ_EN", 8, 8, &umr_bitfield_default }, + { "AUX_LS_UPDATE_DISABLE", 12, 12, &umr_bitfield_default }, + { "AUX_IGNORE_HPD_DISCON", 16, 16, &umr_bitfield_default }, + { "AUX_MODE_DET_EN", 18, 18, &umr_bitfield_default }, + { "AUX_HPD_SEL", 20, 22, &umr_bitfield_default }, + { "AUX_IMPCAL_REQ_EN", 24, 24, &umr_bitfield_default }, + { "AUX_TEST_MODE", 28, 28, &umr_bitfield_default }, + { "AUX_DEGLITCH_EN", 29, 29, &umr_bitfield_default }, + { "SPARE_0", 30, 30, &umr_bitfield_default }, + { "SPARE_1", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX0_AUX_SW_CONTROL[] = { + { "AUX_SW_GO", 0, 0, &umr_bitfield_default }, + { "AUX_LS_READ_TRIG", 2, 2, &umr_bitfield_default }, + { "AUX_SW_START_DELAY", 4, 7, &umr_bitfield_default }, + { "AUX_SW_WR_BYTES", 16, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX0_AUX_ARB_CONTROL[] = { + { "AUX_ARB_PRIORITY", 0, 1, &umr_bitfield_default }, + { "AUX_REG_RW_CNTL_STATUS", 2, 3, &umr_bitfield_default }, + { "AUX_NO_QUEUED_SW_GO", 8, 8, &umr_bitfield_default }, + { "AUX_NO_QUEUED_LS_GO", 10, 10, &umr_bitfield_default }, + { "AUX_SW_USE_AUX_REG_REQ", 16, 16, &umr_bitfield_default }, + { "AUX_SW_PENDING_USE_AUX_REG_REQ", 16, 16, &umr_bitfield_default }, + { "AUX_SW_DONE_USING_AUX_REG", 17, 17, &umr_bitfield_default }, + { "AUX_DMCU_USE_AUX_REG_REQ", 24, 24, &umr_bitfield_default }, + { "AUX_DMCU_PENDING_USE_AUX_REG_REQ", 24, 24, &umr_bitfield_default }, + { "AUX_DMCU_DONE_USING_AUX_REG", 25, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX0_AUX_INTERRUPT_CONTROL[] = { + { "AUX_SW_DONE_INT", 0, 0, &umr_bitfield_default }, + { "AUX_SW_DONE_ACK", 1, 1, &umr_bitfield_default }, + { "AUX_SW_DONE_MASK", 2, 2, &umr_bitfield_default }, + { "AUX_LS_DONE_INT", 4, 4, &umr_bitfield_default }, + { "AUX_LS_DONE_ACK", 5, 5, &umr_bitfield_default }, + { "AUX_LS_DONE_MASK", 6, 6, &umr_bitfield_default }, + { "AUX_GTC_SYNC_LOCK_DONE_INT", 8, 8, &umr_bitfield_default }, + { "AUX_GTC_SYNC_LOCK_DONE_ACK", 9, 9, &umr_bitfield_default }, + { "AUX_GTC_SYNC_LOCK_DONE_INT_MASK", 10, 10, &umr_bitfield_default }, + { "AUX_GTC_SYNC_ERROR_INT", 12, 12, &umr_bitfield_default }, + { "AUX_GTC_SYNC_ERROR_ACK", 13, 13, &umr_bitfield_default }, + { "AUX_GTC_SYNC_ERROR_INT_MASK", 14, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX0_AUX_SW_STATUS[] = { + { "AUX_SW_DONE", 0, 0, &umr_bitfield_default }, + { "AUX_SW_REQ", 1, 1, &umr_bitfield_default }, + { "AUX_SW_RX_TIMEOUT_STATE", 4, 6, &umr_bitfield_default }, + { "AUX_SW_RX_TIMEOUT", 7, 7, &umr_bitfield_default }, + { "AUX_SW_RX_OVERFLOW", 8, 8, &umr_bitfield_default }, + { "AUX_SW_HPD_DISCON", 9, 9, &umr_bitfield_default }, + { "AUX_SW_RX_PARTIAL_BYTE", 10, 10, &umr_bitfield_default }, + { "AUX_SW_NON_AUX_MODE", 11, 11, &umr_bitfield_default }, + { "AUX_SW_RX_MIN_COUNT_VIOL", 12, 12, &umr_bitfield_default }, + { "AUX_SW_RX_INVALID_STOP", 14, 14, &umr_bitfield_default }, + { "AUX_SW_RX_SYNC_INVALID_L", 17, 17, &umr_bitfield_default }, + { "AUX_SW_RX_SYNC_INVALID_H", 18, 18, &umr_bitfield_default }, + { "AUX_SW_RX_INVALID_START", 19, 19, &umr_bitfield_default }, + { "AUX_SW_RX_RECV_NO_DET", 20, 20, &umr_bitfield_default }, + { "AUX_SW_RX_RECV_INVALID_H", 22, 22, &umr_bitfield_default }, + { "AUX_SW_RX_RECV_INVALID_L", 23, 23, &umr_bitfield_default }, + { "AUX_SW_REPLY_BYTE_COUNT", 24, 28, &umr_bitfield_default }, + { "AUX_ARB_STATUS", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX0_AUX_LS_STATUS[] = { + { "AUX_LS_DONE", 0, 0, &umr_bitfield_default }, + { "AUX_LS_REQ", 1, 1, &umr_bitfield_default }, + { "AUX_LS_RX_TIMEOUT_STATE", 4, 6, &umr_bitfield_default }, + { "AUX_LS_RX_TIMEOUT", 7, 7, &umr_bitfield_default }, + { "AUX_LS_RX_OVERFLOW", 8, 8, &umr_bitfield_default }, + { "AUX_LS_HPD_DISCON", 9, 9, &umr_bitfield_default }, + { "AUX_LS_RX_PARTIAL_BYTE", 10, 10, &umr_bitfield_default }, + { "AUX_LS_NON_AUX_MODE", 11, 11, &umr_bitfield_default }, + { "AUX_LS_RX_MIN_COUNT_VIOL", 12, 12, &umr_bitfield_default }, + { "AUX_LS_RX_INVALID_STOP", 14, 14, &umr_bitfield_default }, + { "AUX_LS_RX_SYNC_INVALID_L", 17, 17, &umr_bitfield_default }, + { "AUX_LS_RX_SYNC_INVALID_H", 18, 18, &umr_bitfield_default }, + { "AUX_LS_RX_INVALID_START", 19, 19, &umr_bitfield_default }, + { "AUX_LS_RX_RECV_NO_DET", 20, 20, &umr_bitfield_default }, + { "AUX_LS_RX_RECV_INVALID_H", 22, 22, &umr_bitfield_default }, + { "AUX_LS_RX_RECV_INVALID_L", 23, 23, &umr_bitfield_default }, + { "AUX_LS_REPLY_BYTE_COUNT", 24, 28, &umr_bitfield_default }, + { "AUX_LS_CP_IRQ", 29, 29, &umr_bitfield_default }, + { "AUX_LS_UPDATED", 30, 30, &umr_bitfield_default }, + { "AUX_LS_UPDATED_ACK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX0_AUX_SW_DATA[] = { + { "AUX_SW_DATA_RW", 0, 0, &umr_bitfield_default }, + { "AUX_SW_DATA", 8, 15, &umr_bitfield_default }, + { "AUX_SW_INDEX", 16, 20, &umr_bitfield_default }, + { "AUX_SW_AUTOINCREMENT_DISABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX0_AUX_LS_DATA[] = { + { "AUX_LS_DATA", 8, 15, &umr_bitfield_default }, + { "AUX_LS_INDEX", 16, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL[] = { + { "AUX_TX_REF_SEL", 0, 0, &umr_bitfield_default }, + { "AUX_TX_RATE", 4, 5, &umr_bitfield_default }, + { "AUX_TX_REF_DIV", 16, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX0_AUX_DPHY_TX_CONTROL[] = { + { "AUX_TX_PRECHARGE_LEN", 0, 2, &umr_bitfield_default }, + { "AUX_TX_PRECHARGE_SYMBOLS", 8, 13, &umr_bitfield_default }, + { "AUX_MODE_DET_CHECK_DELAY", 16, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX0_AUX_DPHY_RX_CONTROL0[] = { + { "AUX_RX_START_WINDOW", 4, 6, &umr_bitfield_default }, + { "AUX_RX_RECEIVE_WINDOW", 8, 10, &umr_bitfield_default }, + { "AUX_RX_HALF_SYM_DETECT_LEN", 12, 13, &umr_bitfield_default }, + { "AUX_RX_TRANSITION_FILTER_EN", 16, 16, &umr_bitfield_default }, + { "AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT", 17, 17, &umr_bitfield_default }, + { "AUX_RX_ALLOW_BELOW_THRESHOLD_START", 18, 18, &umr_bitfield_default }, + { "AUX_RX_ALLOW_BELOW_THRESHOLD_STOP", 19, 19, &umr_bitfield_default }, + { "AUX_RX_PHASE_DETECT_LEN", 20, 21, &umr_bitfield_default }, + { "AUX_RX_TIMEOUT_LEN", 24, 26, &umr_bitfield_default }, + { "AUX_RX_DETECTION_THRESHOLD", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX0_AUX_DPHY_RX_CONTROL1[] = { + { "AUX_RX_PRECHARGE_SKIP", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX0_AUX_DPHY_TX_STATUS[] = { + { "AUX_TX_ACTIVE", 0, 0, &umr_bitfield_default }, + { "AUX_TX_STATE", 4, 6, &umr_bitfield_default }, + { "AUX_TX_HALF_SYM_PERIOD", 16, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX0_AUX_DPHY_RX_STATUS[] = { + { "AUX_RX_STATE", 0, 2, &umr_bitfield_default }, + { "AUX_RX_SYNC_VALID_COUNT", 8, 12, &umr_bitfield_default }, + { "AUX_RX_HALF_SYM_PERIOD_FRACT", 16, 20, &umr_bitfield_default }, + { "AUX_RX_HALF_SYM_PERIOD", 21, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL[] = { + { "AUX_GTC_POTENTIAL_ERROR_THRESHOLD", 0, 4, &umr_bitfield_default }, + { "AUX_GTC_DEFINITE_ERROR_THRESHOLD", 8, 12, &umr_bitfield_default }, + { "AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN", 16, 17, &umr_bitfield_default }, + { "AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT", 20, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS[] = { + { "AUX_GTC_SYNC_LOCK_ACQ_COMPLETE", 0, 0, &umr_bitfield_default }, + { "AUX_GTC_SYNC_LOCK_LOST", 4, 4, &umr_bitfield_default }, + { "AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED", 8, 8, &umr_bitfield_default }, + { "AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE", 9, 12, &umr_bitfield_default }, + { "AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL", 16, 16, &umr_bitfield_default }, + { "AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED", 20, 20, &umr_bitfield_default }, + { "AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK", 21, 21, &umr_bitfield_default }, + { "AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED", 22, 22, &umr_bitfield_default }, + { "AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK", 23, 23, &umr_bitfield_default }, + { "AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED", 24, 24, &umr_bitfield_default }, + { "AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK", 25, 25, &umr_bitfield_default }, + { "AUX_GTC_SYNC_CTRL_STATE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX0_AUX_GTC_SYNC_STATUS[] = { + { "AUX_GTC_SYNC_DONE", 0, 0, &umr_bitfield_default }, + { "AUX_GTC_SYNC_REQ", 1, 1, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_TIMEOUT_STATE", 4, 6, &umr_bitfield_default }, + { "AUX_GTC_SYNC_TIMEOUT", 7, 7, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_OVERFLOW", 8, 8, &umr_bitfield_default }, + { "AUX_GTC_SYNC_HPD_DISCON", 9, 9, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_PARTIAL_BYTE", 10, 10, &umr_bitfield_default }, + { "AUX_GTC_SYNC_NON_AUX_MODE", 11, 11, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_MIN_COUNT_VIOL", 12, 12, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_INVALID_STOP", 14, 14, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_SYNC_INVALID_L", 17, 17, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_SYNC_INVALID_H", 18, 18, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_INVALID_START", 19, 19, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_RECV_NO_DET", 20, 20, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_RECV_INVALID_H", 22, 22, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_RECV_INVALID_L", 23, 23, &umr_bitfield_default }, + { "AUX_GTC_SYNC_REPLY_BYTE_COUNT", 24, 28, &umr_bitfield_default }, + { "AUX_GTC_SYNC_NACKED", 29, 29, &umr_bitfield_default }, + { "AUX_GTC_MASTER_REQ_BY_RX", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX1_AUX_CONTROL[] = { + { "AUX_EN", 0, 0, &umr_bitfield_default }, + { "AUX_RESET", 4, 4, &umr_bitfield_default }, + { "AUX_RESET_DONE", 5, 5, &umr_bitfield_default }, + { "AUX_LS_READ_EN", 8, 8, &umr_bitfield_default }, + { "AUX_LS_UPDATE_DISABLE", 12, 12, &umr_bitfield_default }, + { "AUX_IGNORE_HPD_DISCON", 16, 16, &umr_bitfield_default }, + { "AUX_MODE_DET_EN", 18, 18, &umr_bitfield_default }, + { "AUX_HPD_SEL", 20, 22, &umr_bitfield_default }, + { "AUX_IMPCAL_REQ_EN", 24, 24, &umr_bitfield_default }, + { "AUX_TEST_MODE", 28, 28, &umr_bitfield_default }, + { "AUX_DEGLITCH_EN", 29, 29, &umr_bitfield_default }, + { "SPARE_0", 30, 30, &umr_bitfield_default }, + { "SPARE_1", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX1_AUX_SW_CONTROL[] = { + { "AUX_SW_GO", 0, 0, &umr_bitfield_default }, + { "AUX_LS_READ_TRIG", 2, 2, &umr_bitfield_default }, + { "AUX_SW_START_DELAY", 4, 7, &umr_bitfield_default }, + { "AUX_SW_WR_BYTES", 16, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX1_AUX_ARB_CONTROL[] = { + { "AUX_ARB_PRIORITY", 0, 1, &umr_bitfield_default }, + { "AUX_REG_RW_CNTL_STATUS", 2, 3, &umr_bitfield_default }, + { "AUX_NO_QUEUED_SW_GO", 8, 8, &umr_bitfield_default }, + { "AUX_NO_QUEUED_LS_GO", 10, 10, &umr_bitfield_default }, + { "AUX_SW_USE_AUX_REG_REQ", 16, 16, &umr_bitfield_default }, + { "AUX_SW_PENDING_USE_AUX_REG_REQ", 16, 16, &umr_bitfield_default }, + { "AUX_SW_DONE_USING_AUX_REG", 17, 17, &umr_bitfield_default }, + { "AUX_DMCU_USE_AUX_REG_REQ", 24, 24, &umr_bitfield_default }, + { "AUX_DMCU_PENDING_USE_AUX_REG_REQ", 24, 24, &umr_bitfield_default }, + { "AUX_DMCU_DONE_USING_AUX_REG", 25, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX1_AUX_INTERRUPT_CONTROL[] = { + { "AUX_SW_DONE_INT", 0, 0, &umr_bitfield_default }, + { "AUX_SW_DONE_ACK", 1, 1, &umr_bitfield_default }, + { "AUX_SW_DONE_MASK", 2, 2, &umr_bitfield_default }, + { "AUX_LS_DONE_INT", 4, 4, &umr_bitfield_default }, + { "AUX_LS_DONE_ACK", 5, 5, &umr_bitfield_default }, + { "AUX_LS_DONE_MASK", 6, 6, &umr_bitfield_default }, + { "AUX_GTC_SYNC_LOCK_DONE_INT", 8, 8, &umr_bitfield_default }, + { "AUX_GTC_SYNC_LOCK_DONE_ACK", 9, 9, &umr_bitfield_default }, + { "AUX_GTC_SYNC_LOCK_DONE_INT_MASK", 10, 10, &umr_bitfield_default }, + { "AUX_GTC_SYNC_ERROR_INT", 12, 12, &umr_bitfield_default }, + { "AUX_GTC_SYNC_ERROR_ACK", 13, 13, &umr_bitfield_default }, + { "AUX_GTC_SYNC_ERROR_INT_MASK", 14, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX1_AUX_SW_STATUS[] = { + { "AUX_SW_DONE", 0, 0, &umr_bitfield_default }, + { "AUX_SW_REQ", 1, 1, &umr_bitfield_default }, + { "AUX_SW_RX_TIMEOUT_STATE", 4, 6, &umr_bitfield_default }, + { "AUX_SW_RX_TIMEOUT", 7, 7, &umr_bitfield_default }, + { "AUX_SW_RX_OVERFLOW", 8, 8, &umr_bitfield_default }, + { "AUX_SW_HPD_DISCON", 9, 9, &umr_bitfield_default }, + { "AUX_SW_RX_PARTIAL_BYTE", 10, 10, &umr_bitfield_default }, + { "AUX_SW_NON_AUX_MODE", 11, 11, &umr_bitfield_default }, + { "AUX_SW_RX_MIN_COUNT_VIOL", 12, 12, &umr_bitfield_default }, + { "AUX_SW_RX_INVALID_STOP", 14, 14, &umr_bitfield_default }, + { "AUX_SW_RX_SYNC_INVALID_L", 17, 17, &umr_bitfield_default }, + { "AUX_SW_RX_SYNC_INVALID_H", 18, 18, &umr_bitfield_default }, + { "AUX_SW_RX_INVALID_START", 19, 19, &umr_bitfield_default }, + { "AUX_SW_RX_RECV_NO_DET", 20, 20, &umr_bitfield_default }, + { "AUX_SW_RX_RECV_INVALID_H", 22, 22, &umr_bitfield_default }, + { "AUX_SW_RX_RECV_INVALID_L", 23, 23, &umr_bitfield_default }, + { "AUX_SW_REPLY_BYTE_COUNT", 24, 28, &umr_bitfield_default }, + { "AUX_ARB_STATUS", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX1_AUX_LS_STATUS[] = { + { "AUX_LS_DONE", 0, 0, &umr_bitfield_default }, + { "AUX_LS_REQ", 1, 1, &umr_bitfield_default }, + { "AUX_LS_RX_TIMEOUT_STATE", 4, 6, &umr_bitfield_default }, + { "AUX_LS_RX_TIMEOUT", 7, 7, &umr_bitfield_default }, + { "AUX_LS_RX_OVERFLOW", 8, 8, &umr_bitfield_default }, + { "AUX_LS_HPD_DISCON", 9, 9, &umr_bitfield_default }, + { "AUX_LS_RX_PARTIAL_BYTE", 10, 10, &umr_bitfield_default }, + { "AUX_LS_NON_AUX_MODE", 11, 11, &umr_bitfield_default }, + { "AUX_LS_RX_MIN_COUNT_VIOL", 12, 12, &umr_bitfield_default }, + { "AUX_LS_RX_INVALID_STOP", 14, 14, &umr_bitfield_default }, + { "AUX_LS_RX_SYNC_INVALID_L", 17, 17, &umr_bitfield_default }, + { "AUX_LS_RX_SYNC_INVALID_H", 18, 18, &umr_bitfield_default }, + { "AUX_LS_RX_INVALID_START", 19, 19, &umr_bitfield_default }, + { "AUX_LS_RX_RECV_NO_DET", 20, 20, &umr_bitfield_default }, + { "AUX_LS_RX_RECV_INVALID_H", 22, 22, &umr_bitfield_default }, + { "AUX_LS_RX_RECV_INVALID_L", 23, 23, &umr_bitfield_default }, + { "AUX_LS_REPLY_BYTE_COUNT", 24, 28, &umr_bitfield_default }, + { "AUX_LS_CP_IRQ", 29, 29, &umr_bitfield_default }, + { "AUX_LS_UPDATED", 30, 30, &umr_bitfield_default }, + { "AUX_LS_UPDATED_ACK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX1_AUX_SW_DATA[] = { + { "AUX_SW_DATA_RW", 0, 0, &umr_bitfield_default }, + { "AUX_SW_DATA", 8, 15, &umr_bitfield_default }, + { "AUX_SW_INDEX", 16, 20, &umr_bitfield_default }, + { "AUX_SW_AUTOINCREMENT_DISABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX1_AUX_LS_DATA[] = { + { "AUX_LS_DATA", 8, 15, &umr_bitfield_default }, + { "AUX_LS_INDEX", 16, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL[] = { + { "AUX_TX_REF_SEL", 0, 0, &umr_bitfield_default }, + { "AUX_TX_RATE", 4, 5, &umr_bitfield_default }, + { "AUX_TX_REF_DIV", 16, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX1_AUX_DPHY_TX_CONTROL[] = { + { "AUX_TX_PRECHARGE_LEN", 0, 2, &umr_bitfield_default }, + { "AUX_TX_PRECHARGE_SYMBOLS", 8, 13, &umr_bitfield_default }, + { "AUX_MODE_DET_CHECK_DELAY", 16, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX1_AUX_DPHY_RX_CONTROL0[] = { + { "AUX_RX_START_WINDOW", 4, 6, &umr_bitfield_default }, + { "AUX_RX_RECEIVE_WINDOW", 8, 10, &umr_bitfield_default }, + { "AUX_RX_HALF_SYM_DETECT_LEN", 12, 13, &umr_bitfield_default }, + { "AUX_RX_TRANSITION_FILTER_EN", 16, 16, &umr_bitfield_default }, + { "AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT", 17, 17, &umr_bitfield_default }, + { "AUX_RX_ALLOW_BELOW_THRESHOLD_START", 18, 18, &umr_bitfield_default }, + { "AUX_RX_ALLOW_BELOW_THRESHOLD_STOP", 19, 19, &umr_bitfield_default }, + { "AUX_RX_PHASE_DETECT_LEN", 20, 21, &umr_bitfield_default }, + { "AUX_RX_TIMEOUT_LEN", 24, 26, &umr_bitfield_default }, + { "AUX_RX_DETECTION_THRESHOLD", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX1_AUX_DPHY_RX_CONTROL1[] = { + { "AUX_RX_PRECHARGE_SKIP", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX1_AUX_DPHY_TX_STATUS[] = { + { "AUX_TX_ACTIVE", 0, 0, &umr_bitfield_default }, + { "AUX_TX_STATE", 4, 6, &umr_bitfield_default }, + { "AUX_TX_HALF_SYM_PERIOD", 16, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX1_AUX_DPHY_RX_STATUS[] = { + { "AUX_RX_STATE", 0, 2, &umr_bitfield_default }, + { "AUX_RX_SYNC_VALID_COUNT", 8, 12, &umr_bitfield_default }, + { "AUX_RX_HALF_SYM_PERIOD_FRACT", 16, 20, &umr_bitfield_default }, + { "AUX_RX_HALF_SYM_PERIOD", 21, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL[] = { + { "AUX_GTC_POTENTIAL_ERROR_THRESHOLD", 0, 4, &umr_bitfield_default }, + { "AUX_GTC_DEFINITE_ERROR_THRESHOLD", 8, 12, &umr_bitfield_default }, + { "AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN", 16, 17, &umr_bitfield_default }, + { "AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT", 20, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS[] = { + { "AUX_GTC_SYNC_LOCK_ACQ_COMPLETE", 0, 0, &umr_bitfield_default }, + { "AUX_GTC_SYNC_LOCK_LOST", 4, 4, &umr_bitfield_default }, + { "AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED", 8, 8, &umr_bitfield_default }, + { "AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE", 9, 12, &umr_bitfield_default }, + { "AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL", 16, 16, &umr_bitfield_default }, + { "AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED", 20, 20, &umr_bitfield_default }, + { "AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK", 21, 21, &umr_bitfield_default }, + { "AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED", 22, 22, &umr_bitfield_default }, + { "AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK", 23, 23, &umr_bitfield_default }, + { "AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED", 24, 24, &umr_bitfield_default }, + { "AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK", 25, 25, &umr_bitfield_default }, + { "AUX_GTC_SYNC_CTRL_STATE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX1_AUX_GTC_SYNC_STATUS[] = { + { "AUX_GTC_SYNC_DONE", 0, 0, &umr_bitfield_default }, + { "AUX_GTC_SYNC_REQ", 1, 1, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_TIMEOUT_STATE", 4, 6, &umr_bitfield_default }, + { "AUX_GTC_SYNC_TIMEOUT", 7, 7, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_OVERFLOW", 8, 8, &umr_bitfield_default }, + { "AUX_GTC_SYNC_HPD_DISCON", 9, 9, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_PARTIAL_BYTE", 10, 10, &umr_bitfield_default }, + { "AUX_GTC_SYNC_NON_AUX_MODE", 11, 11, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_MIN_COUNT_VIOL", 12, 12, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_INVALID_STOP", 14, 14, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_SYNC_INVALID_L", 17, 17, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_SYNC_INVALID_H", 18, 18, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_INVALID_START", 19, 19, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_RECV_NO_DET", 20, 20, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_RECV_INVALID_H", 22, 22, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_RECV_INVALID_L", 23, 23, &umr_bitfield_default }, + { "AUX_GTC_SYNC_REPLY_BYTE_COUNT", 24, 28, &umr_bitfield_default }, + { "AUX_GTC_SYNC_NACKED", 29, 29, &umr_bitfield_default }, + { "AUX_GTC_MASTER_REQ_BY_RX", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX2_AUX_CONTROL[] = { + { "AUX_EN", 0, 0, &umr_bitfield_default }, + { "AUX_RESET", 4, 4, &umr_bitfield_default }, + { "AUX_RESET_DONE", 5, 5, &umr_bitfield_default }, + { "AUX_LS_READ_EN", 8, 8, &umr_bitfield_default }, + { "AUX_LS_UPDATE_DISABLE", 12, 12, &umr_bitfield_default }, + { "AUX_IGNORE_HPD_DISCON", 16, 16, &umr_bitfield_default }, + { "AUX_MODE_DET_EN", 18, 18, &umr_bitfield_default }, + { "AUX_HPD_SEL", 20, 22, &umr_bitfield_default }, + { "AUX_IMPCAL_REQ_EN", 24, 24, &umr_bitfield_default }, + { "AUX_TEST_MODE", 28, 28, &umr_bitfield_default }, + { "AUX_DEGLITCH_EN", 29, 29, &umr_bitfield_default }, + { "SPARE_0", 30, 30, &umr_bitfield_default }, + { "SPARE_1", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX2_AUX_SW_CONTROL[] = { + { "AUX_SW_GO", 0, 0, &umr_bitfield_default }, + { "AUX_LS_READ_TRIG", 2, 2, &umr_bitfield_default }, + { "AUX_SW_START_DELAY", 4, 7, &umr_bitfield_default }, + { "AUX_SW_WR_BYTES", 16, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX2_AUX_ARB_CONTROL[] = { + { "AUX_ARB_PRIORITY", 0, 1, &umr_bitfield_default }, + { "AUX_REG_RW_CNTL_STATUS", 2, 3, &umr_bitfield_default }, + { "AUX_NO_QUEUED_SW_GO", 8, 8, &umr_bitfield_default }, + { "AUX_NO_QUEUED_LS_GO", 10, 10, &umr_bitfield_default }, + { "AUX_SW_USE_AUX_REG_REQ", 16, 16, &umr_bitfield_default }, + { "AUX_SW_PENDING_USE_AUX_REG_REQ", 16, 16, &umr_bitfield_default }, + { "AUX_SW_DONE_USING_AUX_REG", 17, 17, &umr_bitfield_default }, + { "AUX_DMCU_USE_AUX_REG_REQ", 24, 24, &umr_bitfield_default }, + { "AUX_DMCU_PENDING_USE_AUX_REG_REQ", 24, 24, &umr_bitfield_default }, + { "AUX_DMCU_DONE_USING_AUX_REG", 25, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX2_AUX_INTERRUPT_CONTROL[] = { + { "AUX_SW_DONE_INT", 0, 0, &umr_bitfield_default }, + { "AUX_SW_DONE_ACK", 1, 1, &umr_bitfield_default }, + { "AUX_SW_DONE_MASK", 2, 2, &umr_bitfield_default }, + { "AUX_LS_DONE_INT", 4, 4, &umr_bitfield_default }, + { "AUX_LS_DONE_ACK", 5, 5, &umr_bitfield_default }, + { "AUX_LS_DONE_MASK", 6, 6, &umr_bitfield_default }, + { "AUX_GTC_SYNC_LOCK_DONE_INT", 8, 8, &umr_bitfield_default }, + { "AUX_GTC_SYNC_LOCK_DONE_ACK", 9, 9, &umr_bitfield_default }, + { "AUX_GTC_SYNC_LOCK_DONE_INT_MASK", 10, 10, &umr_bitfield_default }, + { "AUX_GTC_SYNC_ERROR_INT", 12, 12, &umr_bitfield_default }, + { "AUX_GTC_SYNC_ERROR_ACK", 13, 13, &umr_bitfield_default }, + { "AUX_GTC_SYNC_ERROR_INT_MASK", 14, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX2_AUX_SW_STATUS[] = { + { "AUX_SW_DONE", 0, 0, &umr_bitfield_default }, + { "AUX_SW_REQ", 1, 1, &umr_bitfield_default }, + { "AUX_SW_RX_TIMEOUT_STATE", 4, 6, &umr_bitfield_default }, + { "AUX_SW_RX_TIMEOUT", 7, 7, &umr_bitfield_default }, + { "AUX_SW_RX_OVERFLOW", 8, 8, &umr_bitfield_default }, + { "AUX_SW_HPD_DISCON", 9, 9, &umr_bitfield_default }, + { "AUX_SW_RX_PARTIAL_BYTE", 10, 10, &umr_bitfield_default }, + { "AUX_SW_NON_AUX_MODE", 11, 11, &umr_bitfield_default }, + { "AUX_SW_RX_MIN_COUNT_VIOL", 12, 12, &umr_bitfield_default }, + { "AUX_SW_RX_INVALID_STOP", 14, 14, &umr_bitfield_default }, + { "AUX_SW_RX_SYNC_INVALID_L", 17, 17, &umr_bitfield_default }, + { "AUX_SW_RX_SYNC_INVALID_H", 18, 18, &umr_bitfield_default }, + { "AUX_SW_RX_INVALID_START", 19, 19, &umr_bitfield_default }, + { "AUX_SW_RX_RECV_NO_DET", 20, 20, &umr_bitfield_default }, + { "AUX_SW_RX_RECV_INVALID_H", 22, 22, &umr_bitfield_default }, + { "AUX_SW_RX_RECV_INVALID_L", 23, 23, &umr_bitfield_default }, + { "AUX_SW_REPLY_BYTE_COUNT", 24, 28, &umr_bitfield_default }, + { "AUX_ARB_STATUS", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX2_AUX_LS_STATUS[] = { + { "AUX_LS_DONE", 0, 0, &umr_bitfield_default }, + { "AUX_LS_REQ", 1, 1, &umr_bitfield_default }, + { "AUX_LS_RX_TIMEOUT_STATE", 4, 6, &umr_bitfield_default }, + { "AUX_LS_RX_TIMEOUT", 7, 7, &umr_bitfield_default }, + { "AUX_LS_RX_OVERFLOW", 8, 8, &umr_bitfield_default }, + { "AUX_LS_HPD_DISCON", 9, 9, &umr_bitfield_default }, + { "AUX_LS_RX_PARTIAL_BYTE", 10, 10, &umr_bitfield_default }, + { "AUX_LS_NON_AUX_MODE", 11, 11, &umr_bitfield_default }, + { "AUX_LS_RX_MIN_COUNT_VIOL", 12, 12, &umr_bitfield_default }, + { "AUX_LS_RX_INVALID_STOP", 14, 14, &umr_bitfield_default }, + { "AUX_LS_RX_SYNC_INVALID_L", 17, 17, &umr_bitfield_default }, + { "AUX_LS_RX_SYNC_INVALID_H", 18, 18, &umr_bitfield_default }, + { "AUX_LS_RX_INVALID_START", 19, 19, &umr_bitfield_default }, + { "AUX_LS_RX_RECV_NO_DET", 20, 20, &umr_bitfield_default }, + { "AUX_LS_RX_RECV_INVALID_H", 22, 22, &umr_bitfield_default }, + { "AUX_LS_RX_RECV_INVALID_L", 23, 23, &umr_bitfield_default }, + { "AUX_LS_REPLY_BYTE_COUNT", 24, 28, &umr_bitfield_default }, + { "AUX_LS_CP_IRQ", 29, 29, &umr_bitfield_default }, + { "AUX_LS_UPDATED", 30, 30, &umr_bitfield_default }, + { "AUX_LS_UPDATED_ACK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX2_AUX_SW_DATA[] = { + { "AUX_SW_DATA_RW", 0, 0, &umr_bitfield_default }, + { "AUX_SW_DATA", 8, 15, &umr_bitfield_default }, + { "AUX_SW_INDEX", 16, 20, &umr_bitfield_default }, + { "AUX_SW_AUTOINCREMENT_DISABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX2_AUX_LS_DATA[] = { + { "AUX_LS_DATA", 8, 15, &umr_bitfield_default }, + { "AUX_LS_INDEX", 16, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL[] = { + { "AUX_TX_REF_SEL", 0, 0, &umr_bitfield_default }, + { "AUX_TX_RATE", 4, 5, &umr_bitfield_default }, + { "AUX_TX_REF_DIV", 16, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX2_AUX_DPHY_TX_CONTROL[] = { + { "AUX_TX_PRECHARGE_LEN", 0, 2, &umr_bitfield_default }, + { "AUX_TX_PRECHARGE_SYMBOLS", 8, 13, &umr_bitfield_default }, + { "AUX_MODE_DET_CHECK_DELAY", 16, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX2_AUX_DPHY_RX_CONTROL0[] = { + { "AUX_RX_START_WINDOW", 4, 6, &umr_bitfield_default }, + { "AUX_RX_RECEIVE_WINDOW", 8, 10, &umr_bitfield_default }, + { "AUX_RX_HALF_SYM_DETECT_LEN", 12, 13, &umr_bitfield_default }, + { "AUX_RX_TRANSITION_FILTER_EN", 16, 16, &umr_bitfield_default }, + { "AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT", 17, 17, &umr_bitfield_default }, + { "AUX_RX_ALLOW_BELOW_THRESHOLD_START", 18, 18, &umr_bitfield_default }, + { "AUX_RX_ALLOW_BELOW_THRESHOLD_STOP", 19, 19, &umr_bitfield_default }, + { "AUX_RX_PHASE_DETECT_LEN", 20, 21, &umr_bitfield_default }, + { "AUX_RX_TIMEOUT_LEN", 24, 26, &umr_bitfield_default }, + { "AUX_RX_DETECTION_THRESHOLD", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX2_AUX_DPHY_RX_CONTROL1[] = { + { "AUX_RX_PRECHARGE_SKIP", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX2_AUX_DPHY_TX_STATUS[] = { + { "AUX_TX_ACTIVE", 0, 0, &umr_bitfield_default }, + { "AUX_TX_STATE", 4, 6, &umr_bitfield_default }, + { "AUX_TX_HALF_SYM_PERIOD", 16, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX2_AUX_DPHY_RX_STATUS[] = { + { "AUX_RX_STATE", 0, 2, &umr_bitfield_default }, + { "AUX_RX_SYNC_VALID_COUNT", 8, 12, &umr_bitfield_default }, + { "AUX_RX_HALF_SYM_PERIOD_FRACT", 16, 20, &umr_bitfield_default }, + { "AUX_RX_HALF_SYM_PERIOD", 21, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL[] = { + { "AUX_GTC_POTENTIAL_ERROR_THRESHOLD", 0, 4, &umr_bitfield_default }, + { "AUX_GTC_DEFINITE_ERROR_THRESHOLD", 8, 12, &umr_bitfield_default }, + { "AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN", 16, 17, &umr_bitfield_default }, + { "AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT", 20, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS[] = { + { "AUX_GTC_SYNC_LOCK_ACQ_COMPLETE", 0, 0, &umr_bitfield_default }, + { "AUX_GTC_SYNC_LOCK_LOST", 4, 4, &umr_bitfield_default }, + { "AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED", 8, 8, &umr_bitfield_default }, + { "AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE", 9, 12, &umr_bitfield_default }, + { "AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL", 16, 16, &umr_bitfield_default }, + { "AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED", 20, 20, &umr_bitfield_default }, + { "AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK", 21, 21, &umr_bitfield_default }, + { "AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED", 22, 22, &umr_bitfield_default }, + { "AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK", 23, 23, &umr_bitfield_default }, + { "AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED", 24, 24, &umr_bitfield_default }, + { "AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK", 25, 25, &umr_bitfield_default }, + { "AUX_GTC_SYNC_CTRL_STATE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX2_AUX_GTC_SYNC_STATUS[] = { + { "AUX_GTC_SYNC_DONE", 0, 0, &umr_bitfield_default }, + { "AUX_GTC_SYNC_REQ", 1, 1, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_TIMEOUT_STATE", 4, 6, &umr_bitfield_default }, + { "AUX_GTC_SYNC_TIMEOUT", 7, 7, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_OVERFLOW", 8, 8, &umr_bitfield_default }, + { "AUX_GTC_SYNC_HPD_DISCON", 9, 9, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_PARTIAL_BYTE", 10, 10, &umr_bitfield_default }, + { "AUX_GTC_SYNC_NON_AUX_MODE", 11, 11, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_MIN_COUNT_VIOL", 12, 12, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_INVALID_STOP", 14, 14, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_SYNC_INVALID_L", 17, 17, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_SYNC_INVALID_H", 18, 18, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_INVALID_START", 19, 19, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_RECV_NO_DET", 20, 20, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_RECV_INVALID_H", 22, 22, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_RECV_INVALID_L", 23, 23, &umr_bitfield_default }, + { "AUX_GTC_SYNC_REPLY_BYTE_COUNT", 24, 28, &umr_bitfield_default }, + { "AUX_GTC_SYNC_NACKED", 29, 29, &umr_bitfield_default }, + { "AUX_GTC_MASTER_REQ_BY_RX", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX3_AUX_CONTROL[] = { + { "AUX_EN", 0, 0, &umr_bitfield_default }, + { "AUX_RESET", 4, 4, &umr_bitfield_default }, + { "AUX_RESET_DONE", 5, 5, &umr_bitfield_default }, + { "AUX_LS_READ_EN", 8, 8, &umr_bitfield_default }, + { "AUX_LS_UPDATE_DISABLE", 12, 12, &umr_bitfield_default }, + { "AUX_IGNORE_HPD_DISCON", 16, 16, &umr_bitfield_default }, + { "AUX_MODE_DET_EN", 18, 18, &umr_bitfield_default }, + { "AUX_HPD_SEL", 20, 22, &umr_bitfield_default }, + { "AUX_IMPCAL_REQ_EN", 24, 24, &umr_bitfield_default }, + { "AUX_TEST_MODE", 28, 28, &umr_bitfield_default }, + { "AUX_DEGLITCH_EN", 29, 29, &umr_bitfield_default }, + { "SPARE_0", 30, 30, &umr_bitfield_default }, + { "SPARE_1", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX3_AUX_SW_CONTROL[] = { + { "AUX_SW_GO", 0, 0, &umr_bitfield_default }, + { "AUX_LS_READ_TRIG", 2, 2, &umr_bitfield_default }, + { "AUX_SW_START_DELAY", 4, 7, &umr_bitfield_default }, + { "AUX_SW_WR_BYTES", 16, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX3_AUX_ARB_CONTROL[] = { + { "AUX_ARB_PRIORITY", 0, 1, &umr_bitfield_default }, + { "AUX_REG_RW_CNTL_STATUS", 2, 3, &umr_bitfield_default }, + { "AUX_NO_QUEUED_SW_GO", 8, 8, &umr_bitfield_default }, + { "AUX_NO_QUEUED_LS_GO", 10, 10, &umr_bitfield_default }, + { "AUX_SW_USE_AUX_REG_REQ", 16, 16, &umr_bitfield_default }, + { "AUX_SW_PENDING_USE_AUX_REG_REQ", 16, 16, &umr_bitfield_default }, + { "AUX_SW_DONE_USING_AUX_REG", 17, 17, &umr_bitfield_default }, + { "AUX_DMCU_USE_AUX_REG_REQ", 24, 24, &umr_bitfield_default }, + { "AUX_DMCU_PENDING_USE_AUX_REG_REQ", 24, 24, &umr_bitfield_default }, + { "AUX_DMCU_DONE_USING_AUX_REG", 25, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX3_AUX_INTERRUPT_CONTROL[] = { + { "AUX_SW_DONE_INT", 0, 0, &umr_bitfield_default }, + { "AUX_SW_DONE_ACK", 1, 1, &umr_bitfield_default }, + { "AUX_SW_DONE_MASK", 2, 2, &umr_bitfield_default }, + { "AUX_LS_DONE_INT", 4, 4, &umr_bitfield_default }, + { "AUX_LS_DONE_ACK", 5, 5, &umr_bitfield_default }, + { "AUX_LS_DONE_MASK", 6, 6, &umr_bitfield_default }, + { "AUX_GTC_SYNC_LOCK_DONE_INT", 8, 8, &umr_bitfield_default }, + { "AUX_GTC_SYNC_LOCK_DONE_ACK", 9, 9, &umr_bitfield_default }, + { "AUX_GTC_SYNC_LOCK_DONE_INT_MASK", 10, 10, &umr_bitfield_default }, + { "AUX_GTC_SYNC_ERROR_INT", 12, 12, &umr_bitfield_default }, + { "AUX_GTC_SYNC_ERROR_ACK", 13, 13, &umr_bitfield_default }, + { "AUX_GTC_SYNC_ERROR_INT_MASK", 14, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX3_AUX_SW_STATUS[] = { + { "AUX_SW_DONE", 0, 0, &umr_bitfield_default }, + { "AUX_SW_REQ", 1, 1, &umr_bitfield_default }, + { "AUX_SW_RX_TIMEOUT_STATE", 4, 6, &umr_bitfield_default }, + { "AUX_SW_RX_TIMEOUT", 7, 7, &umr_bitfield_default }, + { "AUX_SW_RX_OVERFLOW", 8, 8, &umr_bitfield_default }, + { "AUX_SW_HPD_DISCON", 9, 9, &umr_bitfield_default }, + { "AUX_SW_RX_PARTIAL_BYTE", 10, 10, &umr_bitfield_default }, + { "AUX_SW_NON_AUX_MODE", 11, 11, &umr_bitfield_default }, + { "AUX_SW_RX_MIN_COUNT_VIOL", 12, 12, &umr_bitfield_default }, + { "AUX_SW_RX_INVALID_STOP", 14, 14, &umr_bitfield_default }, + { "AUX_SW_RX_SYNC_INVALID_L", 17, 17, &umr_bitfield_default }, + { "AUX_SW_RX_SYNC_INVALID_H", 18, 18, &umr_bitfield_default }, + { "AUX_SW_RX_INVALID_START", 19, 19, &umr_bitfield_default }, + { "AUX_SW_RX_RECV_NO_DET", 20, 20, &umr_bitfield_default }, + { "AUX_SW_RX_RECV_INVALID_H", 22, 22, &umr_bitfield_default }, + { "AUX_SW_RX_RECV_INVALID_L", 23, 23, &umr_bitfield_default }, + { "AUX_SW_REPLY_BYTE_COUNT", 24, 28, &umr_bitfield_default }, + { "AUX_ARB_STATUS", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX3_AUX_LS_STATUS[] = { + { "AUX_LS_DONE", 0, 0, &umr_bitfield_default }, + { "AUX_LS_REQ", 1, 1, &umr_bitfield_default }, + { "AUX_LS_RX_TIMEOUT_STATE", 4, 6, &umr_bitfield_default }, + { "AUX_LS_RX_TIMEOUT", 7, 7, &umr_bitfield_default }, + { "AUX_LS_RX_OVERFLOW", 8, 8, &umr_bitfield_default }, + { "AUX_LS_HPD_DISCON", 9, 9, &umr_bitfield_default }, + { "AUX_LS_RX_PARTIAL_BYTE", 10, 10, &umr_bitfield_default }, + { "AUX_LS_NON_AUX_MODE", 11, 11, &umr_bitfield_default }, + { "AUX_LS_RX_MIN_COUNT_VIOL", 12, 12, &umr_bitfield_default }, + { "AUX_LS_RX_INVALID_STOP", 14, 14, &umr_bitfield_default }, + { "AUX_LS_RX_SYNC_INVALID_L", 17, 17, &umr_bitfield_default }, + { "AUX_LS_RX_SYNC_INVALID_H", 18, 18, &umr_bitfield_default }, + { "AUX_LS_RX_INVALID_START", 19, 19, &umr_bitfield_default }, + { "AUX_LS_RX_RECV_NO_DET", 20, 20, &umr_bitfield_default }, + { "AUX_LS_RX_RECV_INVALID_H", 22, 22, &umr_bitfield_default }, + { "AUX_LS_RX_RECV_INVALID_L", 23, 23, &umr_bitfield_default }, + { "AUX_LS_REPLY_BYTE_COUNT", 24, 28, &umr_bitfield_default }, + { "AUX_LS_CP_IRQ", 29, 29, &umr_bitfield_default }, + { "AUX_LS_UPDATED", 30, 30, &umr_bitfield_default }, + { "AUX_LS_UPDATED_ACK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX3_AUX_SW_DATA[] = { + { "AUX_SW_DATA_RW", 0, 0, &umr_bitfield_default }, + { "AUX_SW_DATA", 8, 15, &umr_bitfield_default }, + { "AUX_SW_INDEX", 16, 20, &umr_bitfield_default }, + { "AUX_SW_AUTOINCREMENT_DISABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX3_AUX_LS_DATA[] = { + { "AUX_LS_DATA", 8, 15, &umr_bitfield_default }, + { "AUX_LS_INDEX", 16, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL[] = { + { "AUX_TX_REF_SEL", 0, 0, &umr_bitfield_default }, + { "AUX_TX_RATE", 4, 5, &umr_bitfield_default }, + { "AUX_TX_REF_DIV", 16, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX3_AUX_DPHY_TX_CONTROL[] = { + { "AUX_TX_PRECHARGE_LEN", 0, 2, &umr_bitfield_default }, + { "AUX_TX_PRECHARGE_SYMBOLS", 8, 13, &umr_bitfield_default }, + { "AUX_MODE_DET_CHECK_DELAY", 16, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX3_AUX_DPHY_RX_CONTROL0[] = { + { "AUX_RX_START_WINDOW", 4, 6, &umr_bitfield_default }, + { "AUX_RX_RECEIVE_WINDOW", 8, 10, &umr_bitfield_default }, + { "AUX_RX_HALF_SYM_DETECT_LEN", 12, 13, &umr_bitfield_default }, + { "AUX_RX_TRANSITION_FILTER_EN", 16, 16, &umr_bitfield_default }, + { "AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT", 17, 17, &umr_bitfield_default }, + { "AUX_RX_ALLOW_BELOW_THRESHOLD_START", 18, 18, &umr_bitfield_default }, + { "AUX_RX_ALLOW_BELOW_THRESHOLD_STOP", 19, 19, &umr_bitfield_default }, + { "AUX_RX_PHASE_DETECT_LEN", 20, 21, &umr_bitfield_default }, + { "AUX_RX_TIMEOUT_LEN", 24, 26, &umr_bitfield_default }, + { "AUX_RX_DETECTION_THRESHOLD", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX3_AUX_DPHY_RX_CONTROL1[] = { + { "AUX_RX_PRECHARGE_SKIP", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX3_AUX_DPHY_TX_STATUS[] = { + { "AUX_TX_ACTIVE", 0, 0, &umr_bitfield_default }, + { "AUX_TX_STATE", 4, 6, &umr_bitfield_default }, + { "AUX_TX_HALF_SYM_PERIOD", 16, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX3_AUX_DPHY_RX_STATUS[] = { + { "AUX_RX_STATE", 0, 2, &umr_bitfield_default }, + { "AUX_RX_SYNC_VALID_COUNT", 8, 12, &umr_bitfield_default }, + { "AUX_RX_HALF_SYM_PERIOD_FRACT", 16, 20, &umr_bitfield_default }, + { "AUX_RX_HALF_SYM_PERIOD", 21, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL[] = { + { "AUX_GTC_POTENTIAL_ERROR_THRESHOLD", 0, 4, &umr_bitfield_default }, + { "AUX_GTC_DEFINITE_ERROR_THRESHOLD", 8, 12, &umr_bitfield_default }, + { "AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN", 16, 17, &umr_bitfield_default }, + { "AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT", 20, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS[] = { + { "AUX_GTC_SYNC_LOCK_ACQ_COMPLETE", 0, 0, &umr_bitfield_default }, + { "AUX_GTC_SYNC_LOCK_LOST", 4, 4, &umr_bitfield_default }, + { "AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED", 8, 8, &umr_bitfield_default }, + { "AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE", 9, 12, &umr_bitfield_default }, + { "AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL", 16, 16, &umr_bitfield_default }, + { "AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED", 20, 20, &umr_bitfield_default }, + { "AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK", 21, 21, &umr_bitfield_default }, + { "AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED", 22, 22, &umr_bitfield_default }, + { "AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK", 23, 23, &umr_bitfield_default }, + { "AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED", 24, 24, &umr_bitfield_default }, + { "AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK", 25, 25, &umr_bitfield_default }, + { "AUX_GTC_SYNC_CTRL_STATE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX3_AUX_GTC_SYNC_STATUS[] = { + { "AUX_GTC_SYNC_DONE", 0, 0, &umr_bitfield_default }, + { "AUX_GTC_SYNC_REQ", 1, 1, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_TIMEOUT_STATE", 4, 6, &umr_bitfield_default }, + { "AUX_GTC_SYNC_TIMEOUT", 7, 7, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_OVERFLOW", 8, 8, &umr_bitfield_default }, + { "AUX_GTC_SYNC_HPD_DISCON", 9, 9, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_PARTIAL_BYTE", 10, 10, &umr_bitfield_default }, + { "AUX_GTC_SYNC_NON_AUX_MODE", 11, 11, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_MIN_COUNT_VIOL", 12, 12, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_INVALID_STOP", 14, 14, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_SYNC_INVALID_L", 17, 17, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_SYNC_INVALID_H", 18, 18, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_INVALID_START", 19, 19, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_RECV_NO_DET", 20, 20, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_RECV_INVALID_H", 22, 22, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_RECV_INVALID_L", 23, 23, &umr_bitfield_default }, + { "AUX_GTC_SYNC_REPLY_BYTE_COUNT", 24, 28, &umr_bitfield_default }, + { "AUX_GTC_SYNC_NACKED", 29, 29, &umr_bitfield_default }, + { "AUX_GTC_MASTER_REQ_BY_RX", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX4_AUX_CONTROL[] = { + { "AUX_EN", 0, 0, &umr_bitfield_default }, + { "AUX_RESET", 4, 4, &umr_bitfield_default }, + { "AUX_RESET_DONE", 5, 5, &umr_bitfield_default }, + { "AUX_LS_READ_EN", 8, 8, &umr_bitfield_default }, + { "AUX_LS_UPDATE_DISABLE", 12, 12, &umr_bitfield_default }, + { "AUX_IGNORE_HPD_DISCON", 16, 16, &umr_bitfield_default }, + { "AUX_MODE_DET_EN", 18, 18, &umr_bitfield_default }, + { "AUX_HPD_SEL", 20, 22, &umr_bitfield_default }, + { "AUX_IMPCAL_REQ_EN", 24, 24, &umr_bitfield_default }, + { "AUX_TEST_MODE", 28, 28, &umr_bitfield_default }, + { "AUX_DEGLITCH_EN", 29, 29, &umr_bitfield_default }, + { "SPARE_0", 30, 30, &umr_bitfield_default }, + { "SPARE_1", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX4_AUX_SW_CONTROL[] = { + { "AUX_SW_GO", 0, 0, &umr_bitfield_default }, + { "AUX_LS_READ_TRIG", 2, 2, &umr_bitfield_default }, + { "AUX_SW_START_DELAY", 4, 7, &umr_bitfield_default }, + { "AUX_SW_WR_BYTES", 16, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX4_AUX_ARB_CONTROL[] = { + { "AUX_ARB_PRIORITY", 0, 1, &umr_bitfield_default }, + { "AUX_REG_RW_CNTL_STATUS", 2, 3, &umr_bitfield_default }, + { "AUX_NO_QUEUED_SW_GO", 8, 8, &umr_bitfield_default }, + { "AUX_NO_QUEUED_LS_GO", 10, 10, &umr_bitfield_default }, + { "AUX_SW_USE_AUX_REG_REQ", 16, 16, &umr_bitfield_default }, + { "AUX_SW_PENDING_USE_AUX_REG_REQ", 16, 16, &umr_bitfield_default }, + { "AUX_SW_DONE_USING_AUX_REG", 17, 17, &umr_bitfield_default }, + { "AUX_DMCU_USE_AUX_REG_REQ", 24, 24, &umr_bitfield_default }, + { "AUX_DMCU_PENDING_USE_AUX_REG_REQ", 24, 24, &umr_bitfield_default }, + { "AUX_DMCU_DONE_USING_AUX_REG", 25, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX4_AUX_INTERRUPT_CONTROL[] = { + { "AUX_SW_DONE_INT", 0, 0, &umr_bitfield_default }, + { "AUX_SW_DONE_ACK", 1, 1, &umr_bitfield_default }, + { "AUX_SW_DONE_MASK", 2, 2, &umr_bitfield_default }, + { "AUX_LS_DONE_INT", 4, 4, &umr_bitfield_default }, + { "AUX_LS_DONE_ACK", 5, 5, &umr_bitfield_default }, + { "AUX_LS_DONE_MASK", 6, 6, &umr_bitfield_default }, + { "AUX_GTC_SYNC_LOCK_DONE_INT", 8, 8, &umr_bitfield_default }, + { "AUX_GTC_SYNC_LOCK_DONE_ACK", 9, 9, &umr_bitfield_default }, + { "AUX_GTC_SYNC_LOCK_DONE_INT_MASK", 10, 10, &umr_bitfield_default }, + { "AUX_GTC_SYNC_ERROR_INT", 12, 12, &umr_bitfield_default }, + { "AUX_GTC_SYNC_ERROR_ACK", 13, 13, &umr_bitfield_default }, + { "AUX_GTC_SYNC_ERROR_INT_MASK", 14, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX4_AUX_SW_STATUS[] = { + { "AUX_SW_DONE", 0, 0, &umr_bitfield_default }, + { "AUX_SW_REQ", 1, 1, &umr_bitfield_default }, + { "AUX_SW_RX_TIMEOUT_STATE", 4, 6, &umr_bitfield_default }, + { "AUX_SW_RX_TIMEOUT", 7, 7, &umr_bitfield_default }, + { "AUX_SW_RX_OVERFLOW", 8, 8, &umr_bitfield_default }, + { "AUX_SW_HPD_DISCON", 9, 9, &umr_bitfield_default }, + { "AUX_SW_RX_PARTIAL_BYTE", 10, 10, &umr_bitfield_default }, + { "AUX_SW_NON_AUX_MODE", 11, 11, &umr_bitfield_default }, + { "AUX_SW_RX_MIN_COUNT_VIOL", 12, 12, &umr_bitfield_default }, + { "AUX_SW_RX_INVALID_STOP", 14, 14, &umr_bitfield_default }, + { "AUX_SW_RX_SYNC_INVALID_L", 17, 17, &umr_bitfield_default }, + { "AUX_SW_RX_SYNC_INVALID_H", 18, 18, &umr_bitfield_default }, + { "AUX_SW_RX_INVALID_START", 19, 19, &umr_bitfield_default }, + { "AUX_SW_RX_RECV_NO_DET", 20, 20, &umr_bitfield_default }, + { "AUX_SW_RX_RECV_INVALID_H", 22, 22, &umr_bitfield_default }, + { "AUX_SW_RX_RECV_INVALID_L", 23, 23, &umr_bitfield_default }, + { "AUX_SW_REPLY_BYTE_COUNT", 24, 28, &umr_bitfield_default }, + { "AUX_ARB_STATUS", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX4_AUX_LS_STATUS[] = { + { "AUX_LS_DONE", 0, 0, &umr_bitfield_default }, + { "AUX_LS_REQ", 1, 1, &umr_bitfield_default }, + { "AUX_LS_RX_TIMEOUT_STATE", 4, 6, &umr_bitfield_default }, + { "AUX_LS_RX_TIMEOUT", 7, 7, &umr_bitfield_default }, + { "AUX_LS_RX_OVERFLOW", 8, 8, &umr_bitfield_default }, + { "AUX_LS_HPD_DISCON", 9, 9, &umr_bitfield_default }, + { "AUX_LS_RX_PARTIAL_BYTE", 10, 10, &umr_bitfield_default }, + { "AUX_LS_NON_AUX_MODE", 11, 11, &umr_bitfield_default }, + { "AUX_LS_RX_MIN_COUNT_VIOL", 12, 12, &umr_bitfield_default }, + { "AUX_LS_RX_INVALID_STOP", 14, 14, &umr_bitfield_default }, + { "AUX_LS_RX_SYNC_INVALID_L", 17, 17, &umr_bitfield_default }, + { "AUX_LS_RX_SYNC_INVALID_H", 18, 18, &umr_bitfield_default }, + { "AUX_LS_RX_INVALID_START", 19, 19, &umr_bitfield_default }, + { "AUX_LS_RX_RECV_NO_DET", 20, 20, &umr_bitfield_default }, + { "AUX_LS_RX_RECV_INVALID_H", 22, 22, &umr_bitfield_default }, + { "AUX_LS_RX_RECV_INVALID_L", 23, 23, &umr_bitfield_default }, + { "AUX_LS_REPLY_BYTE_COUNT", 24, 28, &umr_bitfield_default }, + { "AUX_LS_CP_IRQ", 29, 29, &umr_bitfield_default }, + { "AUX_LS_UPDATED", 30, 30, &umr_bitfield_default }, + { "AUX_LS_UPDATED_ACK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX4_AUX_SW_DATA[] = { + { "AUX_SW_DATA_RW", 0, 0, &umr_bitfield_default }, + { "AUX_SW_DATA", 8, 15, &umr_bitfield_default }, + { "AUX_SW_INDEX", 16, 20, &umr_bitfield_default }, + { "AUX_SW_AUTOINCREMENT_DISABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX4_AUX_LS_DATA[] = { + { "AUX_LS_DATA", 8, 15, &umr_bitfield_default }, + { "AUX_LS_INDEX", 16, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL[] = { + { "AUX_TX_REF_SEL", 0, 0, &umr_bitfield_default }, + { "AUX_TX_RATE", 4, 5, &umr_bitfield_default }, + { "AUX_TX_REF_DIV", 16, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX4_AUX_DPHY_TX_CONTROL[] = { + { "AUX_TX_PRECHARGE_LEN", 0, 2, &umr_bitfield_default }, + { "AUX_TX_PRECHARGE_SYMBOLS", 8, 13, &umr_bitfield_default }, + { "AUX_MODE_DET_CHECK_DELAY", 16, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX4_AUX_DPHY_RX_CONTROL0[] = { + { "AUX_RX_START_WINDOW", 4, 6, &umr_bitfield_default }, + { "AUX_RX_RECEIVE_WINDOW", 8, 10, &umr_bitfield_default }, + { "AUX_RX_HALF_SYM_DETECT_LEN", 12, 13, &umr_bitfield_default }, + { "AUX_RX_TRANSITION_FILTER_EN", 16, 16, &umr_bitfield_default }, + { "AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT", 17, 17, &umr_bitfield_default }, + { "AUX_RX_ALLOW_BELOW_THRESHOLD_START", 18, 18, &umr_bitfield_default }, + { "AUX_RX_ALLOW_BELOW_THRESHOLD_STOP", 19, 19, &umr_bitfield_default }, + { "AUX_RX_PHASE_DETECT_LEN", 20, 21, &umr_bitfield_default }, + { "AUX_RX_TIMEOUT_LEN", 24, 26, &umr_bitfield_default }, + { "AUX_RX_DETECTION_THRESHOLD", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX4_AUX_DPHY_RX_CONTROL1[] = { + { "AUX_RX_PRECHARGE_SKIP", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX4_AUX_DPHY_TX_STATUS[] = { + { "AUX_TX_ACTIVE", 0, 0, &umr_bitfield_default }, + { "AUX_TX_STATE", 4, 6, &umr_bitfield_default }, + { "AUX_TX_HALF_SYM_PERIOD", 16, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX4_AUX_DPHY_RX_STATUS[] = { + { "AUX_RX_STATE", 0, 2, &umr_bitfield_default }, + { "AUX_RX_SYNC_VALID_COUNT", 8, 12, &umr_bitfield_default }, + { "AUX_RX_HALF_SYM_PERIOD_FRACT", 16, 20, &umr_bitfield_default }, + { "AUX_RX_HALF_SYM_PERIOD", 21, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL[] = { + { "AUX_GTC_POTENTIAL_ERROR_THRESHOLD", 0, 4, &umr_bitfield_default }, + { "AUX_GTC_DEFINITE_ERROR_THRESHOLD", 8, 12, &umr_bitfield_default }, + { "AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN", 16, 17, &umr_bitfield_default }, + { "AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT", 20, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS[] = { + { "AUX_GTC_SYNC_LOCK_ACQ_COMPLETE", 0, 0, &umr_bitfield_default }, + { "AUX_GTC_SYNC_LOCK_LOST", 4, 4, &umr_bitfield_default }, + { "AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED", 8, 8, &umr_bitfield_default }, + { "AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE", 9, 12, &umr_bitfield_default }, + { "AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL", 16, 16, &umr_bitfield_default }, + { "AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED", 20, 20, &umr_bitfield_default }, + { "AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK", 21, 21, &umr_bitfield_default }, + { "AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED", 22, 22, &umr_bitfield_default }, + { "AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK", 23, 23, &umr_bitfield_default }, + { "AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED", 24, 24, &umr_bitfield_default }, + { "AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK", 25, 25, &umr_bitfield_default }, + { "AUX_GTC_SYNC_CTRL_STATE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX4_AUX_GTC_SYNC_STATUS[] = { + { "AUX_GTC_SYNC_DONE", 0, 0, &umr_bitfield_default }, + { "AUX_GTC_SYNC_REQ", 1, 1, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_TIMEOUT_STATE", 4, 6, &umr_bitfield_default }, + { "AUX_GTC_SYNC_TIMEOUT", 7, 7, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_OVERFLOW", 8, 8, &umr_bitfield_default }, + { "AUX_GTC_SYNC_HPD_DISCON", 9, 9, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_PARTIAL_BYTE", 10, 10, &umr_bitfield_default }, + { "AUX_GTC_SYNC_NON_AUX_MODE", 11, 11, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_MIN_COUNT_VIOL", 12, 12, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_INVALID_STOP", 14, 14, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_SYNC_INVALID_L", 17, 17, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_SYNC_INVALID_H", 18, 18, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_INVALID_START", 19, 19, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_RECV_NO_DET", 20, 20, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_RECV_INVALID_H", 22, 22, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_RECV_INVALID_L", 23, 23, &umr_bitfield_default }, + { "AUX_GTC_SYNC_REPLY_BYTE_COUNT", 24, 28, &umr_bitfield_default }, + { "AUX_GTC_SYNC_NACKED", 29, 29, &umr_bitfield_default }, + { "AUX_GTC_MASTER_REQ_BY_RX", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX5_AUX_CONTROL[] = { + { "AUX_EN", 0, 0, &umr_bitfield_default }, + { "AUX_RESET", 4, 4, &umr_bitfield_default }, + { "AUX_RESET_DONE", 5, 5, &umr_bitfield_default }, + { "AUX_LS_READ_EN", 8, 8, &umr_bitfield_default }, + { "AUX_LS_UPDATE_DISABLE", 12, 12, &umr_bitfield_default }, + { "AUX_IGNORE_HPD_DISCON", 16, 16, &umr_bitfield_default }, + { "AUX_MODE_DET_EN", 18, 18, &umr_bitfield_default }, + { "AUX_HPD_SEL", 20, 22, &umr_bitfield_default }, + { "AUX_IMPCAL_REQ_EN", 24, 24, &umr_bitfield_default }, + { "AUX_TEST_MODE", 28, 28, &umr_bitfield_default }, + { "AUX_DEGLITCH_EN", 29, 29, &umr_bitfield_default }, + { "SPARE_0", 30, 30, &umr_bitfield_default }, + { "SPARE_1", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX5_AUX_SW_CONTROL[] = { + { "AUX_SW_GO", 0, 0, &umr_bitfield_default }, + { "AUX_LS_READ_TRIG", 2, 2, &umr_bitfield_default }, + { "AUX_SW_START_DELAY", 4, 7, &umr_bitfield_default }, + { "AUX_SW_WR_BYTES", 16, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX5_AUX_ARB_CONTROL[] = { + { "AUX_ARB_PRIORITY", 0, 1, &umr_bitfield_default }, + { "AUX_REG_RW_CNTL_STATUS", 2, 3, &umr_bitfield_default }, + { "AUX_NO_QUEUED_SW_GO", 8, 8, &umr_bitfield_default }, + { "AUX_NO_QUEUED_LS_GO", 10, 10, &umr_bitfield_default }, + { "AUX_SW_USE_AUX_REG_REQ", 16, 16, &umr_bitfield_default }, + { "AUX_SW_PENDING_USE_AUX_REG_REQ", 16, 16, &umr_bitfield_default }, + { "AUX_SW_DONE_USING_AUX_REG", 17, 17, &umr_bitfield_default }, + { "AUX_DMCU_USE_AUX_REG_REQ", 24, 24, &umr_bitfield_default }, + { "AUX_DMCU_PENDING_USE_AUX_REG_REQ", 24, 24, &umr_bitfield_default }, + { "AUX_DMCU_DONE_USING_AUX_REG", 25, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX5_AUX_INTERRUPT_CONTROL[] = { + { "AUX_SW_DONE_INT", 0, 0, &umr_bitfield_default }, + { "AUX_SW_DONE_ACK", 1, 1, &umr_bitfield_default }, + { "AUX_SW_DONE_MASK", 2, 2, &umr_bitfield_default }, + { "AUX_LS_DONE_INT", 4, 4, &umr_bitfield_default }, + { "AUX_LS_DONE_ACK", 5, 5, &umr_bitfield_default }, + { "AUX_LS_DONE_MASK", 6, 6, &umr_bitfield_default }, + { "AUX_GTC_SYNC_LOCK_DONE_INT", 8, 8, &umr_bitfield_default }, + { "AUX_GTC_SYNC_LOCK_DONE_ACK", 9, 9, &umr_bitfield_default }, + { "AUX_GTC_SYNC_LOCK_DONE_INT_MASK", 10, 10, &umr_bitfield_default }, + { "AUX_GTC_SYNC_ERROR_INT", 12, 12, &umr_bitfield_default }, + { "AUX_GTC_SYNC_ERROR_ACK", 13, 13, &umr_bitfield_default }, + { "AUX_GTC_SYNC_ERROR_INT_MASK", 14, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX5_AUX_SW_STATUS[] = { + { "AUX_SW_DONE", 0, 0, &umr_bitfield_default }, + { "AUX_SW_REQ", 1, 1, &umr_bitfield_default }, + { "AUX_SW_RX_TIMEOUT_STATE", 4, 6, &umr_bitfield_default }, + { "AUX_SW_RX_TIMEOUT", 7, 7, &umr_bitfield_default }, + { "AUX_SW_RX_OVERFLOW", 8, 8, &umr_bitfield_default }, + { "AUX_SW_HPD_DISCON", 9, 9, &umr_bitfield_default }, + { "AUX_SW_RX_PARTIAL_BYTE", 10, 10, &umr_bitfield_default }, + { "AUX_SW_NON_AUX_MODE", 11, 11, &umr_bitfield_default }, + { "AUX_SW_RX_MIN_COUNT_VIOL", 12, 12, &umr_bitfield_default }, + { "AUX_SW_RX_INVALID_STOP", 14, 14, &umr_bitfield_default }, + { "AUX_SW_RX_SYNC_INVALID_L", 17, 17, &umr_bitfield_default }, + { "AUX_SW_RX_SYNC_INVALID_H", 18, 18, &umr_bitfield_default }, + { "AUX_SW_RX_INVALID_START", 19, 19, &umr_bitfield_default }, + { "AUX_SW_RX_RECV_NO_DET", 20, 20, &umr_bitfield_default }, + { "AUX_SW_RX_RECV_INVALID_H", 22, 22, &umr_bitfield_default }, + { "AUX_SW_RX_RECV_INVALID_L", 23, 23, &umr_bitfield_default }, + { "AUX_SW_REPLY_BYTE_COUNT", 24, 28, &umr_bitfield_default }, + { "AUX_ARB_STATUS", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX5_AUX_LS_STATUS[] = { + { "AUX_LS_DONE", 0, 0, &umr_bitfield_default }, + { "AUX_LS_REQ", 1, 1, &umr_bitfield_default }, + { "AUX_LS_RX_TIMEOUT_STATE", 4, 6, &umr_bitfield_default }, + { "AUX_LS_RX_TIMEOUT", 7, 7, &umr_bitfield_default }, + { "AUX_LS_RX_OVERFLOW", 8, 8, &umr_bitfield_default }, + { "AUX_LS_HPD_DISCON", 9, 9, &umr_bitfield_default }, + { "AUX_LS_RX_PARTIAL_BYTE", 10, 10, &umr_bitfield_default }, + { "AUX_LS_NON_AUX_MODE", 11, 11, &umr_bitfield_default }, + { "AUX_LS_RX_MIN_COUNT_VIOL", 12, 12, &umr_bitfield_default }, + { "AUX_LS_RX_INVALID_STOP", 14, 14, &umr_bitfield_default }, + { "AUX_LS_RX_SYNC_INVALID_L", 17, 17, &umr_bitfield_default }, + { "AUX_LS_RX_SYNC_INVALID_H", 18, 18, &umr_bitfield_default }, + { "AUX_LS_RX_INVALID_START", 19, 19, &umr_bitfield_default }, + { "AUX_LS_RX_RECV_NO_DET", 20, 20, &umr_bitfield_default }, + { "AUX_LS_RX_RECV_INVALID_H", 22, 22, &umr_bitfield_default }, + { "AUX_LS_RX_RECV_INVALID_L", 23, 23, &umr_bitfield_default }, + { "AUX_LS_REPLY_BYTE_COUNT", 24, 28, &umr_bitfield_default }, + { "AUX_LS_CP_IRQ", 29, 29, &umr_bitfield_default }, + { "AUX_LS_UPDATED", 30, 30, &umr_bitfield_default }, + { "AUX_LS_UPDATED_ACK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX5_AUX_SW_DATA[] = { + { "AUX_SW_DATA_RW", 0, 0, &umr_bitfield_default }, + { "AUX_SW_DATA", 8, 15, &umr_bitfield_default }, + { "AUX_SW_INDEX", 16, 20, &umr_bitfield_default }, + { "AUX_SW_AUTOINCREMENT_DISABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX5_AUX_LS_DATA[] = { + { "AUX_LS_DATA", 8, 15, &umr_bitfield_default }, + { "AUX_LS_INDEX", 16, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL[] = { + { "AUX_TX_REF_SEL", 0, 0, &umr_bitfield_default }, + { "AUX_TX_RATE", 4, 5, &umr_bitfield_default }, + { "AUX_TX_REF_DIV", 16, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX5_AUX_DPHY_TX_CONTROL[] = { + { "AUX_TX_PRECHARGE_LEN", 0, 2, &umr_bitfield_default }, + { "AUX_TX_PRECHARGE_SYMBOLS", 8, 13, &umr_bitfield_default }, + { "AUX_MODE_DET_CHECK_DELAY", 16, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX5_AUX_DPHY_RX_CONTROL0[] = { + { "AUX_RX_START_WINDOW", 4, 6, &umr_bitfield_default }, + { "AUX_RX_RECEIVE_WINDOW", 8, 10, &umr_bitfield_default }, + { "AUX_RX_HALF_SYM_DETECT_LEN", 12, 13, &umr_bitfield_default }, + { "AUX_RX_TRANSITION_FILTER_EN", 16, 16, &umr_bitfield_default }, + { "AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT", 17, 17, &umr_bitfield_default }, + { "AUX_RX_ALLOW_BELOW_THRESHOLD_START", 18, 18, &umr_bitfield_default }, + { "AUX_RX_ALLOW_BELOW_THRESHOLD_STOP", 19, 19, &umr_bitfield_default }, + { "AUX_RX_PHASE_DETECT_LEN", 20, 21, &umr_bitfield_default }, + { "AUX_RX_TIMEOUT_LEN", 24, 26, &umr_bitfield_default }, + { "AUX_RX_DETECTION_THRESHOLD", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX5_AUX_DPHY_RX_CONTROL1[] = { + { "AUX_RX_PRECHARGE_SKIP", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX5_AUX_DPHY_TX_STATUS[] = { + { "AUX_TX_ACTIVE", 0, 0, &umr_bitfield_default }, + { "AUX_TX_STATE", 4, 6, &umr_bitfield_default }, + { "AUX_TX_HALF_SYM_PERIOD", 16, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX5_AUX_DPHY_RX_STATUS[] = { + { "AUX_RX_STATE", 0, 2, &umr_bitfield_default }, + { "AUX_RX_SYNC_VALID_COUNT", 8, 12, &umr_bitfield_default }, + { "AUX_RX_HALF_SYM_PERIOD_FRACT", 16, 20, &umr_bitfield_default }, + { "AUX_RX_HALF_SYM_PERIOD", 21, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL[] = { + { "AUX_GTC_POTENTIAL_ERROR_THRESHOLD", 0, 4, &umr_bitfield_default }, + { "AUX_GTC_DEFINITE_ERROR_THRESHOLD", 8, 12, &umr_bitfield_default }, + { "AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN", 16, 17, &umr_bitfield_default }, + { "AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT", 20, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS[] = { + { "AUX_GTC_SYNC_LOCK_ACQ_COMPLETE", 0, 0, &umr_bitfield_default }, + { "AUX_GTC_SYNC_LOCK_LOST", 4, 4, &umr_bitfield_default }, + { "AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED", 8, 8, &umr_bitfield_default }, + { "AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE", 9, 12, &umr_bitfield_default }, + { "AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL", 16, 16, &umr_bitfield_default }, + { "AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED", 20, 20, &umr_bitfield_default }, + { "AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK", 21, 21, &umr_bitfield_default }, + { "AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED", 22, 22, &umr_bitfield_default }, + { "AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK", 23, 23, &umr_bitfield_default }, + { "AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED", 24, 24, &umr_bitfield_default }, + { "AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK", 25, 25, &umr_bitfield_default }, + { "AUX_GTC_SYNC_CTRL_STATE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX5_AUX_GTC_SYNC_STATUS[] = { + { "AUX_GTC_SYNC_DONE", 0, 0, &umr_bitfield_default }, + { "AUX_GTC_SYNC_REQ", 1, 1, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_TIMEOUT_STATE", 4, 6, &umr_bitfield_default }, + { "AUX_GTC_SYNC_TIMEOUT", 7, 7, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_OVERFLOW", 8, 8, &umr_bitfield_default }, + { "AUX_GTC_SYNC_HPD_DISCON", 9, 9, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_PARTIAL_BYTE", 10, 10, &umr_bitfield_default }, + { "AUX_GTC_SYNC_NON_AUX_MODE", 11, 11, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_MIN_COUNT_VIOL", 12, 12, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_INVALID_STOP", 14, 14, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_SYNC_INVALID_L", 17, 17, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_SYNC_INVALID_H", 18, 18, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_INVALID_START", 19, 19, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_RECV_NO_DET", 20, 20, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_RECV_INVALID_H", 22, 22, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_RECV_INVALID_L", 23, 23, &umr_bitfield_default }, + { "AUX_GTC_SYNC_REPLY_BYTE_COUNT", 24, 28, &umr_bitfield_default }, + { "AUX_GTC_SYNC_NACKED", 29, 29, &umr_bitfield_default }, + { "AUX_GTC_MASTER_REQ_BY_RX", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX6_AUX_CONTROL[] = { + { "AUX_EN", 0, 0, &umr_bitfield_default }, + { "AUX_RESET", 4, 4, &umr_bitfield_default }, + { "AUX_RESET_DONE", 5, 5, &umr_bitfield_default }, + { "AUX_LS_READ_EN", 8, 8, &umr_bitfield_default }, + { "AUX_LS_UPDATE_DISABLE", 12, 12, &umr_bitfield_default }, + { "AUX_IGNORE_HPD_DISCON", 16, 16, &umr_bitfield_default }, + { "AUX_MODE_DET_EN", 18, 18, &umr_bitfield_default }, + { "AUX_HPD_SEL", 20, 22, &umr_bitfield_default }, + { "AUX_IMPCAL_REQ_EN", 24, 24, &umr_bitfield_default }, + { "AUX_TEST_MODE", 28, 28, &umr_bitfield_default }, + { "AUX_DEGLITCH_EN", 29, 29, &umr_bitfield_default }, + { "SPARE_0", 30, 30, &umr_bitfield_default }, + { "SPARE_1", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX6_AUX_SW_CONTROL[] = { + { "AUX_SW_GO", 0, 0, &umr_bitfield_default }, + { "AUX_LS_READ_TRIG", 2, 2, &umr_bitfield_default }, + { "AUX_SW_START_DELAY", 4, 7, &umr_bitfield_default }, + { "AUX_SW_WR_BYTES", 16, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX6_AUX_ARB_CONTROL[] = { + { "AUX_ARB_PRIORITY", 0, 1, &umr_bitfield_default }, + { "AUX_REG_RW_CNTL_STATUS", 2, 3, &umr_bitfield_default }, + { "AUX_NO_QUEUED_SW_GO", 8, 8, &umr_bitfield_default }, + { "AUX_NO_QUEUED_LS_GO", 10, 10, &umr_bitfield_default }, + { "AUX_SW_USE_AUX_REG_REQ", 16, 16, &umr_bitfield_default }, + { "AUX_SW_PENDING_USE_AUX_REG_REQ", 16, 16, &umr_bitfield_default }, + { "AUX_SW_DONE_USING_AUX_REG", 17, 17, &umr_bitfield_default }, + { "AUX_DMCU_USE_AUX_REG_REQ", 24, 24, &umr_bitfield_default }, + { "AUX_DMCU_PENDING_USE_AUX_REG_REQ", 24, 24, &umr_bitfield_default }, + { "AUX_DMCU_DONE_USING_AUX_REG", 25, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX6_AUX_INTERRUPT_CONTROL[] = { + { "AUX_SW_DONE_INT", 0, 0, &umr_bitfield_default }, + { "AUX_SW_DONE_ACK", 1, 1, &umr_bitfield_default }, + { "AUX_SW_DONE_MASK", 2, 2, &umr_bitfield_default }, + { "AUX_LS_DONE_INT", 4, 4, &umr_bitfield_default }, + { "AUX_LS_DONE_ACK", 5, 5, &umr_bitfield_default }, + { "AUX_LS_DONE_MASK", 6, 6, &umr_bitfield_default }, + { "AUX_GTC_SYNC_LOCK_DONE_INT", 8, 8, &umr_bitfield_default }, + { "AUX_GTC_SYNC_LOCK_DONE_ACK", 9, 9, &umr_bitfield_default }, + { "AUX_GTC_SYNC_LOCK_DONE_INT_MASK", 10, 10, &umr_bitfield_default }, + { "AUX_GTC_SYNC_ERROR_INT", 12, 12, &umr_bitfield_default }, + { "AUX_GTC_SYNC_ERROR_ACK", 13, 13, &umr_bitfield_default }, + { "AUX_GTC_SYNC_ERROR_INT_MASK", 14, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX6_AUX_SW_STATUS[] = { + { "AUX_SW_DONE", 0, 0, &umr_bitfield_default }, + { "AUX_SW_REQ", 1, 1, &umr_bitfield_default }, + { "AUX_SW_RX_TIMEOUT_STATE", 4, 6, &umr_bitfield_default }, + { "AUX_SW_RX_TIMEOUT", 7, 7, &umr_bitfield_default }, + { "AUX_SW_RX_OVERFLOW", 8, 8, &umr_bitfield_default }, + { "AUX_SW_HPD_DISCON", 9, 9, &umr_bitfield_default }, + { "AUX_SW_RX_PARTIAL_BYTE", 10, 10, &umr_bitfield_default }, + { "AUX_SW_NON_AUX_MODE", 11, 11, &umr_bitfield_default }, + { "AUX_SW_RX_MIN_COUNT_VIOL", 12, 12, &umr_bitfield_default }, + { "AUX_SW_RX_INVALID_STOP", 14, 14, &umr_bitfield_default }, + { "AUX_SW_RX_SYNC_INVALID_L", 17, 17, &umr_bitfield_default }, + { "AUX_SW_RX_SYNC_INVALID_H", 18, 18, &umr_bitfield_default }, + { "AUX_SW_RX_INVALID_START", 19, 19, &umr_bitfield_default }, + { "AUX_SW_RX_RECV_NO_DET", 20, 20, &umr_bitfield_default }, + { "AUX_SW_RX_RECV_INVALID_H", 22, 22, &umr_bitfield_default }, + { "AUX_SW_RX_RECV_INVALID_L", 23, 23, &umr_bitfield_default }, + { "AUX_SW_REPLY_BYTE_COUNT", 24, 28, &umr_bitfield_default }, + { "AUX_ARB_STATUS", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX6_AUX_LS_STATUS[] = { + { "AUX_LS_DONE", 0, 0, &umr_bitfield_default }, + { "AUX_LS_REQ", 1, 1, &umr_bitfield_default }, + { "AUX_LS_RX_TIMEOUT_STATE", 4, 6, &umr_bitfield_default }, + { "AUX_LS_RX_TIMEOUT", 7, 7, &umr_bitfield_default }, + { "AUX_LS_RX_OVERFLOW", 8, 8, &umr_bitfield_default }, + { "AUX_LS_HPD_DISCON", 9, 9, &umr_bitfield_default }, + { "AUX_LS_RX_PARTIAL_BYTE", 10, 10, &umr_bitfield_default }, + { "AUX_LS_NON_AUX_MODE", 11, 11, &umr_bitfield_default }, + { "AUX_LS_RX_MIN_COUNT_VIOL", 12, 12, &umr_bitfield_default }, + { "AUX_LS_RX_INVALID_STOP", 14, 14, &umr_bitfield_default }, + { "AUX_LS_RX_SYNC_INVALID_L", 17, 17, &umr_bitfield_default }, + { "AUX_LS_RX_SYNC_INVALID_H", 18, 18, &umr_bitfield_default }, + { "AUX_LS_RX_INVALID_START", 19, 19, &umr_bitfield_default }, + { "AUX_LS_RX_RECV_NO_DET", 20, 20, &umr_bitfield_default }, + { "AUX_LS_RX_RECV_INVALID_H", 22, 22, &umr_bitfield_default }, + { "AUX_LS_RX_RECV_INVALID_L", 23, 23, &umr_bitfield_default }, + { "AUX_LS_REPLY_BYTE_COUNT", 24, 28, &umr_bitfield_default }, + { "AUX_LS_CP_IRQ", 29, 29, &umr_bitfield_default }, + { "AUX_LS_UPDATED", 30, 30, &umr_bitfield_default }, + { "AUX_LS_UPDATED_ACK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX6_AUX_SW_DATA[] = { + { "AUX_SW_DATA_RW", 0, 0, &umr_bitfield_default }, + { "AUX_SW_DATA", 8, 15, &umr_bitfield_default }, + { "AUX_SW_INDEX", 16, 20, &umr_bitfield_default }, + { "AUX_SW_AUTOINCREMENT_DISABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX6_AUX_LS_DATA[] = { + { "AUX_LS_DATA", 8, 15, &umr_bitfield_default }, + { "AUX_LS_INDEX", 16, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX6_AUX_DPHY_TX_REF_CONTROL[] = { + { "AUX_TX_REF_SEL", 0, 0, &umr_bitfield_default }, + { "AUX_TX_RATE", 4, 5, &umr_bitfield_default }, + { "AUX_TX_REF_DIV", 16, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX6_AUX_DPHY_TX_CONTROL[] = { + { "AUX_TX_PRECHARGE_LEN", 0, 2, &umr_bitfield_default }, + { "AUX_TX_PRECHARGE_SYMBOLS", 8, 13, &umr_bitfield_default }, + { "AUX_MODE_DET_CHECK_DELAY", 16, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX6_AUX_DPHY_RX_CONTROL0[] = { + { "AUX_RX_START_WINDOW", 4, 6, &umr_bitfield_default }, + { "AUX_RX_RECEIVE_WINDOW", 8, 10, &umr_bitfield_default }, + { "AUX_RX_HALF_SYM_DETECT_LEN", 12, 13, &umr_bitfield_default }, + { "AUX_RX_TRANSITION_FILTER_EN", 16, 16, &umr_bitfield_default }, + { "AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT", 17, 17, &umr_bitfield_default }, + { "AUX_RX_ALLOW_BELOW_THRESHOLD_START", 18, 18, &umr_bitfield_default }, + { "AUX_RX_ALLOW_BELOW_THRESHOLD_STOP", 19, 19, &umr_bitfield_default }, + { "AUX_RX_PHASE_DETECT_LEN", 20, 21, &umr_bitfield_default }, + { "AUX_RX_TIMEOUT_LEN", 24, 26, &umr_bitfield_default }, + { "AUX_RX_DETECTION_THRESHOLD", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX6_AUX_DPHY_RX_CONTROL1[] = { + { "AUX_RX_PRECHARGE_SKIP", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX6_AUX_DPHY_TX_STATUS[] = { + { "AUX_TX_ACTIVE", 0, 0, &umr_bitfield_default }, + { "AUX_TX_STATE", 4, 6, &umr_bitfield_default }, + { "AUX_TX_HALF_SYM_PERIOD", 16, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX6_AUX_DPHY_RX_STATUS[] = { + { "AUX_RX_STATE", 0, 2, &umr_bitfield_default }, + { "AUX_RX_SYNC_VALID_COUNT", 8, 12, &umr_bitfield_default }, + { "AUX_RX_HALF_SYM_PERIOD_FRACT", 16, 20, &umr_bitfield_default }, + { "AUX_RX_HALF_SYM_PERIOD", 21, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX6_AUX_GTC_SYNC_ERROR_CONTROL[] = { + { "AUX_GTC_POTENTIAL_ERROR_THRESHOLD", 0, 4, &umr_bitfield_default }, + { "AUX_GTC_DEFINITE_ERROR_THRESHOLD", 8, 12, &umr_bitfield_default }, + { "AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN", 16, 17, &umr_bitfield_default }, + { "AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT", 20, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS[] = { + { "AUX_GTC_SYNC_LOCK_ACQ_COMPLETE", 0, 0, &umr_bitfield_default }, + { "AUX_GTC_SYNC_LOCK_LOST", 4, 4, &umr_bitfield_default }, + { "AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED", 8, 8, &umr_bitfield_default }, + { "AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE", 9, 12, &umr_bitfield_default }, + { "AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL", 16, 16, &umr_bitfield_default }, + { "AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED", 20, 20, &umr_bitfield_default }, + { "AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK", 21, 21, &umr_bitfield_default }, + { "AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED", 22, 22, &umr_bitfield_default }, + { "AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK", 23, 23, &umr_bitfield_default }, + { "AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED", 24, 24, &umr_bitfield_default }, + { "AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK", 25, 25, &umr_bitfield_default }, + { "AUX_GTC_SYNC_CTRL_STATE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP_AUX6_AUX_GTC_SYNC_STATUS[] = { + { "AUX_GTC_SYNC_DONE", 0, 0, &umr_bitfield_default }, + { "AUX_GTC_SYNC_REQ", 1, 1, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_TIMEOUT_STATE", 4, 6, &umr_bitfield_default }, + { "AUX_GTC_SYNC_TIMEOUT", 7, 7, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_OVERFLOW", 8, 8, &umr_bitfield_default }, + { "AUX_GTC_SYNC_HPD_DISCON", 9, 9, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_PARTIAL_BYTE", 10, 10, &umr_bitfield_default }, + { "AUX_GTC_SYNC_NON_AUX_MODE", 11, 11, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_MIN_COUNT_VIOL", 12, 12, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_INVALID_STOP", 14, 14, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_SYNC_INVALID_L", 17, 17, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_SYNC_INVALID_H", 18, 18, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_INVALID_START", 19, 19, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_RECV_NO_DET", 20, 20, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_RECV_INVALID_H", 22, 22, &umr_bitfield_default }, + { "AUX_GTC_SYNC_RX_RECV_INVALID_L", 23, 23, &umr_bitfield_default }, + { "AUX_GTC_SYNC_REPLY_BYTE_COUNT", 24, 28, &umr_bitfield_default }, + { "AUX_GTC_SYNC_NACKED", 29, 29, &umr_bitfield_default }, + { "AUX_GTC_MASTER_REQ_BY_RX", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_DIG_FE_CNTL[] = { + { "DIG_SOURCE_SELECT", 0, 2, &umr_bitfield_default }, + { "DIG_STEREOSYNC_SELECT", 4, 6, &umr_bitfield_default }, + { "DIG_STEREOSYNC_GATE_EN", 8, 8, &umr_bitfield_default }, + { "DIG_START", 10, 10, &umr_bitfield_default }, + { "DIG_DIGITAL_BYPASS_SELECT", 12, 14, &umr_bitfield_default }, + { "DIG_SYMCLK_FE_ON", 24, 24, &umr_bitfield_default }, + { "TMDS_PIXEL_ENCODING", 28, 28, &umr_bitfield_default }, + { "TMDS_COLOR_FORMAT", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_DIG_OUTPUT_CRC_CNTL[] = { + { "DIG_OUTPUT_CRC_EN", 0, 0, &umr_bitfield_default }, + { "DIG_OUTPUT_CRC_LINK_SEL", 4, 4, &umr_bitfield_default }, + { "DIG_OUTPUT_CRC_DATA_SEL", 8, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_DIG_OUTPUT_CRC_RESULT[] = { + { "DIG_OUTPUT_CRC_RESULT", 0, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_DIG_CLOCK_PATTERN[] = { + { "DIG_CLOCK_PATTERN", 0, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_DIG_TEST_PATTERN[] = { + { "DIG_TEST_PATTERN_OUT_EN", 0, 0, &umr_bitfield_default }, + { "DIG_HALF_CLOCK_PATTERN_SEL", 1, 1, &umr_bitfield_default }, + { "DIG_RANDOM_PATTERN_OUT_EN", 4, 4, &umr_bitfield_default }, + { "DIG_RANDOM_PATTERN_RESET", 5, 5, &umr_bitfield_default }, + { "DIG_TEST_PATTERN_EXTERNAL_RESET_EN", 6, 6, &umr_bitfield_default }, + { "DIG_STATIC_TEST_PATTERN", 16, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_DIG_RANDOM_PATTERN_SEED[] = { + { "DIG_RANDOM_PATTERN_SEED", 0, 23, &umr_bitfield_default }, + { "DIG_RAN_PAT_DURING_DE_ONLY", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_DIG_FIFO_STATUS[] = { + { "DIG_FIFO_LEVEL_ERROR", 0, 0, &umr_bitfield_default }, + { "DIG_FIFO_USE_OVERWRITE_LEVEL", 1, 1, &umr_bitfield_default }, + { "DIG_FIFO_OVERWRITE_LEVEL", 2, 7, &umr_bitfield_default }, + { "DIG_FIFO_ERROR_ACK", 8, 8, &umr_bitfield_default }, + { "DIG_FIFO_CAL_AVERAGE_LEVEL", 10, 15, &umr_bitfield_default }, + { "DIG_FIFO_MAXIMUM_LEVEL", 16, 20, &umr_bitfield_default }, + { "DIG_FIFO_MINIMUM_LEVEL", 22, 25, &umr_bitfield_default }, + { "DIG_FIFO_READ_CLOCK_SRC", 26, 26, &umr_bitfield_default }, + { "DIG_FIFO_CALIBRATED", 29, 29, &umr_bitfield_default }, + { "DIG_FIFO_FORCE_RECAL_AVERAGE", 30, 30, &umr_bitfield_default }, + { "DIG_FIFO_FORCE_RECOMP_MINMAX", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_HDMI_CONTROL[] = { + { "HDMI_KEEPOUT_MODE", 0, 0, &umr_bitfield_default }, + { "HDMI_DATA_SCRAMBLE_EN", 1, 1, &umr_bitfield_default }, + { "HDMI_CLOCK_CHANNEL_RATE", 2, 2, &umr_bitfield_default }, + { "HDMI_NO_EXTRA_NULL_PACKET_FILLED", 3, 3, &umr_bitfield_default }, + { "HDMI_PACKET_GEN_VERSION", 4, 4, &umr_bitfield_default }, + { "HDMI_ERROR_ACK", 8, 8, &umr_bitfield_default }, + { "HDMI_ERROR_MASK", 9, 9, &umr_bitfield_default }, + { "HDMI_DEEP_COLOR_ENABLE", 24, 24, &umr_bitfield_default }, + { "HDMI_DEEP_COLOR_DEPTH", 28, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_HDMI_STATUS[] = { + { "HDMI_ACTIVE_AVMUTE", 0, 0, &umr_bitfield_default }, + { "HDMI_AUDIO_PACKET_ERROR", 16, 16, &umr_bitfield_default }, + { "HDMI_VBI_PACKET_ERROR", 20, 20, &umr_bitfield_default }, + { "HDMI_ERROR_INT", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_HDMI_AUDIO_PACKET_CONTROL[] = { + { "HDMI_AUDIO_DELAY_EN", 4, 5, &umr_bitfield_default }, + { "HDMI_AUDIO_PACKETS_PER_LINE", 16, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_HDMI_ACR_PACKET_CONTROL[] = { + { "HDMI_ACR_SEND", 0, 0, &umr_bitfield_default }, + { "HDMI_ACR_CONT", 1, 1, &umr_bitfield_default }, + { "HDMI_ACR_SELECT", 4, 5, &umr_bitfield_default }, + { "HDMI_ACR_SOURCE", 8, 8, &umr_bitfield_default }, + { "HDMI_ACR_AUTO_SEND", 12, 12, &umr_bitfield_default }, + { "HDMI_ACR_N_MULTIPLE", 16, 18, &umr_bitfield_default }, + { "HDMI_ACR_AUDIO_PRIORITY", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_HDMI_VBI_PACKET_CONTROL[] = { + { "HDMI_NULL_SEND", 0, 0, &umr_bitfield_default }, + { "HDMI_GC_SEND", 4, 4, &umr_bitfield_default }, + { "HDMI_GC_CONT", 5, 5, &umr_bitfield_default }, + { "HDMI_ISRC_SEND", 8, 8, &umr_bitfield_default }, + { "HDMI_ISRC_CONT", 9, 9, &umr_bitfield_default }, + { "HDMI_ISRC_LINE", 16, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_HDMI_INFOFRAME_CONTROL0[] = { + { "HDMI_AUDIO_INFO_SEND", 4, 4, &umr_bitfield_default }, + { "HDMI_AUDIO_INFO_CONT", 5, 5, &umr_bitfield_default }, + { "HDMI_MPEG_INFO_SEND", 8, 8, &umr_bitfield_default }, + { "HDMI_MPEG_INFO_CONT", 9, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_HDMI_INFOFRAME_CONTROL1[] = { + { "HDMI_AUDIO_INFO_LINE", 8, 13, &umr_bitfield_default }, + { "HDMI_MPEG_INFO_LINE", 16, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_HDMI_GENERIC_PACKET_CONTROL0[] = { + { "HDMI_GENERIC0_SEND", 0, 0, &umr_bitfield_default }, + { "HDMI_GENERIC0_CONT", 1, 1, &umr_bitfield_default }, + { "HDMI_GENERIC1_SEND", 4, 4, &umr_bitfield_default }, + { "HDMI_GENERIC1_CONT", 5, 5, &umr_bitfield_default }, + { "HDMI_GENERIC0_LINE", 16, 21, &umr_bitfield_default }, + { "HDMI_GENERIC1_LINE", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_HDMI_GC[] = { + { "HDMI_GC_AVMUTE", 0, 0, &umr_bitfield_default }, + { "HDMI_GC_AVMUTE_CONT", 2, 2, &umr_bitfield_default }, + { "HDMI_DEFAULT_PHASE", 4, 4, &umr_bitfield_default }, + { "HDMI_PACKING_PHASE", 8, 11, &umr_bitfield_default }, + { "HDMI_PACKING_PHASE_OVERRIDE", 12, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_AFMT_AUDIO_PACKET_CONTROL2[] = { + { "AFMT_AUDIO_LAYOUT_OVRD", 0, 0, &umr_bitfield_default }, + { "AFMT_AUDIO_LAYOUT_SELECT", 1, 1, &umr_bitfield_default }, + { "AFMT_AUDIO_CHANNEL_ENABLE", 8, 15, &umr_bitfield_default }, + { "AFMT_DP_AUDIO_STREAM_ID", 16, 23, &umr_bitfield_default }, + { "AFMT_HBR_ENABLE_OVRD", 24, 24, &umr_bitfield_default }, + { "AFMT_60958_OSF_OVRD", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_AFMT_ISRC1_0[] = { + { "AFMT_ISRC_STATUS", 0, 2, &umr_bitfield_default }, + { "AFMT_ISRC_CONTINUE", 6, 6, &umr_bitfield_default }, + { "AFMT_ISRC_VALID", 7, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_AFMT_ISRC1_1[] = { + { "AFMT_UPC_EAN_ISRC0", 0, 7, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC1", 8, 15, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC2", 16, 23, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC3", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_AFMT_ISRC1_2[] = { + { "AFMT_UPC_EAN_ISRC4", 0, 7, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC5", 8, 15, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC6", 16, 23, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC7", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_AFMT_ISRC1_3[] = { + { "AFMT_UPC_EAN_ISRC8", 0, 7, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC9", 8, 15, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC10", 16, 23, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC11", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_AFMT_ISRC1_4[] = { + { "AFMT_UPC_EAN_ISRC12", 0, 7, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC13", 8, 15, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC14", 16, 23, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC15", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_AFMT_ISRC2_0[] = { + { "AFMT_UPC_EAN_ISRC16", 0, 7, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC17", 8, 15, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC18", 16, 23, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC19", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_AFMT_ISRC2_1[] = { + { "AFMT_UPC_EAN_ISRC20", 0, 7, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC21", 8, 15, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC22", 16, 23, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC23", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_AFMT_ISRC2_2[] = { + { "AFMT_UPC_EAN_ISRC24", 0, 7, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC25", 8, 15, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC26", 16, 23, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC27", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_AFMT_ISRC2_3[] = { + { "AFMT_UPC_EAN_ISRC28", 0, 7, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC29", 8, 15, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC30", 16, 23, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC31", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_HDMI_GENERIC_PACKET_CONTROL2[] = { + { "HDMI_GENERIC4_SEND", 0, 0, &umr_bitfield_default }, + { "HDMI_GENERIC4_CONT", 1, 1, &umr_bitfield_default }, + { "HDMI_GENERIC5_SEND", 4, 4, &umr_bitfield_default }, + { "HDMI_GENERIC5_CONT", 5, 5, &umr_bitfield_default }, + { "HDMI_GENERIC4_LINE", 16, 21, &umr_bitfield_default }, + { "HDMI_GENERIC5_LINE", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_HDMI_GENERIC_PACKET_CONTROL3[] = { + { "HDMI_GENERIC6_SEND", 0, 0, &umr_bitfield_default }, + { "HDMI_GENERIC6_CONT", 1, 1, &umr_bitfield_default }, + { "HDMI_GENERIC7_SEND", 4, 4, &umr_bitfield_default }, + { "HDMI_GENERIC7_CONT", 5, 5, &umr_bitfield_default }, + { "HDMI_GENERIC6_LINE", 16, 21, &umr_bitfield_default }, + { "HDMI_GENERIC7_LINE", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_HDMI_DB_CONTROL[] = { + { "HDMI_DB_PENDING", 0, 0, &umr_bitfield_default }, + { "HDMI_DB_TAKEN", 4, 4, &umr_bitfield_default }, + { "HDMI_DB_TAKEN_CLR", 5, 5, &umr_bitfield_default }, + { "HDMI_DB_LOCK", 8, 8, &umr_bitfield_default }, + { "HDMI_DB_DISABLE", 12, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_AFMT_MPEG_INFO0[] = { + { "AFMT_MPEG_INFO_CHECKSUM", 0, 7, &umr_bitfield_default }, + { "AFMT_MPEG_INFO_MB0", 8, 15, &umr_bitfield_default }, + { "AFMT_MPEG_INFO_MB1", 16, 23, &umr_bitfield_default }, + { "AFMT_MPEG_INFO_MB2", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_AFMT_MPEG_INFO1[] = { + { "AFMT_MPEG_INFO_MB3", 0, 7, &umr_bitfield_default }, + { "AFMT_MPEG_INFO_MF", 8, 9, &umr_bitfield_default }, + { "AFMT_MPEG_INFO_FR", 12, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_AFMT_GENERIC_HDR[] = { + { "AFMT_GENERIC_HB0", 0, 7, &umr_bitfield_default }, + { "AFMT_GENERIC_HB1", 8, 15, &umr_bitfield_default }, + { "AFMT_GENERIC_HB2", 16, 23, &umr_bitfield_default }, + { "AFMT_GENERIC_HB3", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_AFMT_GENERIC_0[] = { + { "AFMT_GENERIC_BYTE0", 0, 7, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE1", 8, 15, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE2", 16, 23, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE3", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_AFMT_GENERIC_1[] = { + { "AFMT_GENERIC_BYTE4", 0, 7, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE5", 8, 15, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE6", 16, 23, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE7", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_AFMT_GENERIC_2[] = { + { "AFMT_GENERIC_BYTE8", 0, 7, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE9", 8, 15, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE10", 16, 23, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE11", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_AFMT_GENERIC_3[] = { + { "AFMT_GENERIC_BYTE12", 0, 7, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE13", 8, 15, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE14", 16, 23, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE15", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_AFMT_GENERIC_4[] = { + { "AFMT_GENERIC_BYTE16", 0, 7, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE17", 8, 15, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE18", 16, 23, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE19", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_AFMT_GENERIC_5[] = { + { "AFMT_GENERIC_BYTE20", 0, 7, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE21", 8, 15, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE22", 16, 23, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE23", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_AFMT_GENERIC_6[] = { + { "AFMT_GENERIC_BYTE24", 0, 7, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE25", 8, 15, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE26", 16, 23, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE27", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_AFMT_GENERIC_7[] = { + { "AFMT_GENERIC_BYTE28", 0, 7, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE29", 8, 15, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE30", 16, 23, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE31", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_HDMI_GENERIC_PACKET_CONTROL1[] = { + { "HDMI_GENERIC2_SEND", 0, 0, &umr_bitfield_default }, + { "HDMI_GENERIC2_CONT", 1, 1, &umr_bitfield_default }, + { "HDMI_GENERIC3_SEND", 4, 4, &umr_bitfield_default }, + { "HDMI_GENERIC3_CONT", 5, 5, &umr_bitfield_default }, + { "HDMI_GENERIC2_LINE", 16, 21, &umr_bitfield_default }, + { "HDMI_GENERIC3_LINE", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_HDMI_ACR_32_0[] = { + { "HDMI_ACR_CTS_32", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_HDMI_ACR_32_1[] = { + { "HDMI_ACR_N_32", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_HDMI_ACR_44_0[] = { + { "HDMI_ACR_CTS_44", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_HDMI_ACR_44_1[] = { + { "HDMI_ACR_N_44", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_HDMI_ACR_48_0[] = { + { "HDMI_ACR_CTS_48", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_HDMI_ACR_48_1[] = { + { "HDMI_ACR_N_48", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_HDMI_ACR_STATUS_0[] = { + { "HDMI_ACR_CTS", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_HDMI_ACR_STATUS_1[] = { + { "HDMI_ACR_N", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_AFMT_AUDIO_INFO0[] = { + { "AFMT_AUDIO_INFO_CHECKSUM", 0, 7, &umr_bitfield_default }, + { "AFMT_AUDIO_INFO_CC", 8, 10, &umr_bitfield_default }, + { "AFMT_AUDIO_INFO_CT", 11, 14, &umr_bitfield_default }, + { "AFMT_AUDIO_INFO_CHECKSUM_OFFSET", 16, 23, &umr_bitfield_default }, + { "AFMT_AUDIO_INFO_CXT", 24, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_AFMT_AUDIO_INFO1[] = { + { "AFMT_AUDIO_INFO_CA", 0, 7, &umr_bitfield_default }, + { "AFMT_AUDIO_INFO_LSV", 11, 14, &umr_bitfield_default }, + { "AFMT_AUDIO_INFO_DM_INH", 15, 15, &umr_bitfield_default }, + { "AFMT_AUDIO_INFO_LFEPBL", 16, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_AFMT_60958_0[] = { + { "AFMT_60958_CS_A", 0, 0, &umr_bitfield_default }, + { "AFMT_60958_CS_B", 1, 1, &umr_bitfield_default }, + { "AFMT_60958_CS_C", 2, 2, &umr_bitfield_default }, + { "AFMT_60958_CS_D", 3, 5, &umr_bitfield_default }, + { "AFMT_60958_CS_MODE", 6, 7, &umr_bitfield_default }, + { "AFMT_60958_CS_CATEGORY_CODE", 8, 15, &umr_bitfield_default }, + { "AFMT_60958_CS_SOURCE_NUMBER", 16, 19, &umr_bitfield_default }, + { "AFMT_60958_CS_CHANNEL_NUMBER_L", 20, 23, &umr_bitfield_default }, + { "AFMT_60958_CS_SAMPLING_FREQUENCY", 24, 27, &umr_bitfield_default }, + { "AFMT_60958_CS_CLOCK_ACCURACY", 28, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_AFMT_60958_1[] = { + { "AFMT_60958_CS_WORD_LENGTH", 0, 3, &umr_bitfield_default }, + { "AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY", 4, 7, &umr_bitfield_default }, + { "AFMT_60958_VALID_L", 16, 16, &umr_bitfield_default }, + { "AFMT_60958_VALID_R", 18, 18, &umr_bitfield_default }, + { "AFMT_60958_CS_CHANNEL_NUMBER_R", 20, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_AFMT_AUDIO_CRC_CONTROL[] = { + { "AFMT_AUDIO_CRC_EN", 0, 0, &umr_bitfield_default }, + { "AFMT_AUDIO_CRC_CONT", 4, 4, &umr_bitfield_default }, + { "AFMT_AUDIO_CRC_SOURCE", 8, 8, &umr_bitfield_default }, + { "AFMT_AUDIO_CRC_CH_SEL", 12, 15, &umr_bitfield_default }, + { "AFMT_AUDIO_CRC_COUNT", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_AFMT_RAMP_CONTROL0[] = { + { "AFMT_RAMP_MAX_COUNT", 0, 23, &umr_bitfield_default }, + { "AFMT_RAMP_DATA_SIGN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_AFMT_RAMP_CONTROL1[] = { + { "AFMT_RAMP_MIN_COUNT", 0, 23, &umr_bitfield_default }, + { "AFMT_AUDIO_TEST_CH_DISABLE", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_AFMT_RAMP_CONTROL2[] = { + { "AFMT_RAMP_INC_COUNT", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_AFMT_RAMP_CONTROL3[] = { + { "AFMT_RAMP_DEC_COUNT", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_AFMT_60958_2[] = { + { "AFMT_60958_CS_CHANNEL_NUMBER_2", 0, 3, &umr_bitfield_default }, + { "AFMT_60958_CS_CHANNEL_NUMBER_3", 4, 7, &umr_bitfield_default }, + { "AFMT_60958_CS_CHANNEL_NUMBER_4", 8, 11, &umr_bitfield_default }, + { "AFMT_60958_CS_CHANNEL_NUMBER_5", 12, 15, &umr_bitfield_default }, + { "AFMT_60958_CS_CHANNEL_NUMBER_6", 16, 19, &umr_bitfield_default }, + { "AFMT_60958_CS_CHANNEL_NUMBER_7", 20, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_AFMT_AUDIO_CRC_RESULT[] = { + { "AFMT_AUDIO_CRC_DONE", 0, 0, &umr_bitfield_default }, + { "AFMT_AUDIO_CRC", 8, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_AFMT_STATUS[] = { + { "AFMT_AUDIO_ENABLE", 4, 4, &umr_bitfield_default }, + { "AFMT_AZ_HBR_ENABLE", 8, 8, &umr_bitfield_default }, + { "AFMT_AUDIO_FIFO_OVERFLOW", 24, 24, &umr_bitfield_default }, + { "AFMT_AZ_AUDIO_ENABLE_CHG", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_AFMT_AUDIO_PACKET_CONTROL[] = { + { "AFMT_AUDIO_SAMPLE_SEND", 0, 0, &umr_bitfield_default }, + { "AFMT_RESET_FIFO_WHEN_AUDIO_DIS", 11, 11, &umr_bitfield_default }, + { "AFMT_AUDIO_TEST_EN", 12, 12, &umr_bitfield_default }, + { "AFMT_AUDIO_TEST_MODE", 14, 14, &umr_bitfield_default }, + { "AFMT_AUDIO_FIFO_OVERFLOW_ACK", 23, 23, &umr_bitfield_default }, + { "AFMT_AUDIO_CHANNEL_SWAP", 24, 24, &umr_bitfield_default }, + { "AFMT_60958_CS_UPDATE", 26, 26, &umr_bitfield_default }, + { "AFMT_AZ_AUDIO_ENABLE_CHG_ACK", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_AFMT_VBI_PACKET_CONTROL[] = { + { "AFMT_GENERIC_LOCK_STATUS", 8, 8, &umr_bitfield_default }, + { "AFMT_GENERIC_CONFLICT", 16, 16, &umr_bitfield_default }, + { "AFMT_GENERIC_CONFLICT_CLR", 17, 17, &umr_bitfield_default }, + { "AFMT_GENERIC_INDEX", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_AFMT_INFOFRAME_CONTROL0[] = { + { "AFMT_AUDIO_INFO_SOURCE", 6, 6, &umr_bitfield_default }, + { "AFMT_AUDIO_INFO_UPDATE", 7, 7, &umr_bitfield_default }, + { "AFMT_MPEG_INFO_UPDATE", 10, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_AFMT_AUDIO_SRC_CONTROL[] = { + { "AFMT_AUDIO_SRC_SELECT", 0, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_DIG_BE_CNTL[] = { + { "DIG_DUAL_LINK_ENABLE", 0, 0, &umr_bitfield_default }, + { "DIG_SWAP", 1, 1, &umr_bitfield_default }, + { "DIG_FE_SOURCE_SELECT", 8, 14, &umr_bitfield_default }, + { "DIG_MODE", 16, 18, &umr_bitfield_default }, + { "DIG_HPD_SELECT", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_DIG_BE_EN_CNTL[] = { + { "DIG_ENABLE", 0, 0, &umr_bitfield_default }, + { "DIG_SYMCLK_BE_ON", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_TMDS_CNTL[] = { + { "TMDS_SYNC_PHASE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_TMDS_CONTROL_CHAR[] = { + { "TMDS_CONTROL_CHAR0_OUT_EN", 0, 0, &umr_bitfield_default }, + { "TMDS_CONTROL_CHAR1_OUT_EN", 1, 1, &umr_bitfield_default }, + { "TMDS_CONTROL_CHAR2_OUT_EN", 2, 2, &umr_bitfield_default }, + { "TMDS_CONTROL_CHAR3_OUT_EN", 3, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_TMDS_CONTROL0_FEEDBACK[] = { + { "TMDS_CONTROL0_FEEDBACK_SELECT", 0, 1, &umr_bitfield_default }, + { "TMDS_CONTROL0_FEEDBACK_DELAY", 8, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_TMDS_STEREOSYNC_CTL_SEL[] = { + { "TMDS_STEREOSYNC_CTL_SEL", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1[] = { + { "TMDS_SYNC_CHAR_PATTERN0", 0, 9, &umr_bitfield_default }, + { "TMDS_SYNC_CHAR_PATTERN1", 16, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3[] = { + { "TMDS_SYNC_CHAR_PATTERN2", 0, 9, &umr_bitfield_default }, + { "TMDS_SYNC_CHAR_PATTERN3", 16, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_TMDS_CTL_BITS[] = { + { "TMDS_CTL0", 0, 0, &umr_bitfield_default }, + { "TMDS_CTL1", 8, 8, &umr_bitfield_default }, + { "TMDS_CTL2", 16, 16, &umr_bitfield_default }, + { "TMDS_CTL3", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_TMDS_DCBALANCER_CONTROL[] = { + { "TMDS_DCBALANCER_EN", 0, 0, &umr_bitfield_default }, + { "TMDS_DCBALANCER_TEST_EN", 8, 8, &umr_bitfield_default }, + { "TMDS_DCBALANCER_TEST_IN", 16, 19, &umr_bitfield_default }, + { "TMDS_DCBALANCER_FORCE", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_TMDS_CTL0_1_GEN_CNTL[] = { + { "TMDS_CTL0_DATA_SEL", 0, 3, &umr_bitfield_default }, + { "TMDS_CTL0_DATA_DELAY", 4, 6, &umr_bitfield_default }, + { "TMDS_CTL0_DATA_INVERT", 7, 7, &umr_bitfield_default }, + { "TMDS_CTL0_DATA_MODULATION", 8, 9, &umr_bitfield_default }, + { "TMDS_CTL0_USE_FEEDBACK_PATH", 10, 10, &umr_bitfield_default }, + { "TMDS_CTL0_FB_SYNC_CONT", 11, 11, &umr_bitfield_default }, + { "TMDS_CTL0_PATTERN_OUT_EN", 12, 12, &umr_bitfield_default }, + { "TMDS_CTL1_DATA_SEL", 16, 19, &umr_bitfield_default }, + { "TMDS_CTL1_DATA_DELAY", 20, 22, &umr_bitfield_default }, + { "TMDS_CTL1_DATA_INVERT", 23, 23, &umr_bitfield_default }, + { "TMDS_CTL1_DATA_MODULATION", 24, 25, &umr_bitfield_default }, + { "TMDS_CTL1_USE_FEEDBACK_PATH", 26, 26, &umr_bitfield_default }, + { "TMDS_CTL1_FB_SYNC_CONT", 27, 27, &umr_bitfield_default }, + { "TMDS_CTL1_PATTERN_OUT_EN", 28, 28, &umr_bitfield_default }, + { "TMDS_2BIT_COUNTER_EN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_TMDS_CTL2_3_GEN_CNTL[] = { + { "TMDS_CTL2_DATA_SEL", 0, 3, &umr_bitfield_default }, + { "TMDS_CTL2_DATA_DELAY", 4, 6, &umr_bitfield_default }, + { "TMDS_CTL2_DATA_INVERT", 7, 7, &umr_bitfield_default }, + { "TMDS_CTL2_DATA_MODULATION", 8, 9, &umr_bitfield_default }, + { "TMDS_CTL2_USE_FEEDBACK_PATH", 10, 10, &umr_bitfield_default }, + { "TMDS_CTL2_FB_SYNC_CONT", 11, 11, &umr_bitfield_default }, + { "TMDS_CTL2_PATTERN_OUT_EN", 12, 12, &umr_bitfield_default }, + { "TMDS_CTL3_DATA_SEL", 16, 19, &umr_bitfield_default }, + { "TMDS_CTL3_DATA_DELAY", 20, 22, &umr_bitfield_default }, + { "TMDS_CTL3_DATA_INVERT", 23, 23, &umr_bitfield_default }, + { "TMDS_CTL3_DATA_MODULATION", 24, 25, &umr_bitfield_default }, + { "TMDS_CTL3_USE_FEEDBACK_PATH", 26, 26, &umr_bitfield_default }, + { "TMDS_CTL3_FB_SYNC_CONT", 27, 27, &umr_bitfield_default }, + { "TMDS_CTL3_PATTERN_OUT_EN", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_DIG_VERSION[] = { + { "DIG_TYPE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_DIG_LANE_ENABLE[] = { + { "DIG_LANE0EN", 0, 0, &umr_bitfield_default }, + { "DIG_LANE1EN", 1, 1, &umr_bitfield_default }, + { "DIG_LANE2EN", 2, 2, &umr_bitfield_default }, + { "DIG_LANE3EN", 3, 3, &umr_bitfield_default }, + { "DIG_CLK_EN", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_AFMT_CNTL[] = { + { "AFMT_AUDIO_CLOCK_EN", 0, 0, &umr_bitfield_default }, + { "AFMT_AUDIO_CLOCK_ON", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG0_AFMT_VBI_PACKET_CONTROL1[] = { + { "AFMT_GENERIC0_FRAME_UPDATE", 0, 0, &umr_bitfield_default }, + { "AFMT_GENERIC0_FRAME_UPDATE_PENDING", 1, 1, &umr_bitfield_default }, + { "AFMT_GENERIC0_IMMEDIATE_UPDATE", 2, 2, &umr_bitfield_default }, + { "AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING", 3, 3, &umr_bitfield_default }, + { "AFMT_GENERIC1_FRAME_UPDATE", 4, 4, &umr_bitfield_default }, + { "AFMT_GENERIC1_FRAME_UPDATE_PENDING", 5, 5, &umr_bitfield_default }, + { "AFMT_GENERIC1_IMMEDIATE_UPDATE", 6, 6, &umr_bitfield_default }, + { "AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING", 7, 7, &umr_bitfield_default }, + { "AFMT_GENERIC2_FRAME_UPDATE", 8, 8, &umr_bitfield_default }, + { "AFMT_GENERIC2_FRAME_UPDATE_PENDING", 9, 9, &umr_bitfield_default }, + { "AFMT_GENERIC2_IMMEDIATE_UPDATE", 10, 10, &umr_bitfield_default }, + { "AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING", 11, 11, &umr_bitfield_default }, + { "AFMT_GENERIC3_FRAME_UPDATE", 12, 12, &umr_bitfield_default }, + { "AFMT_GENERIC3_FRAME_UPDATE_PENDING", 13, 13, &umr_bitfield_default }, + { "AFMT_GENERIC3_IMMEDIATE_UPDATE", 14, 14, &umr_bitfield_default }, + { "AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING", 15, 15, &umr_bitfield_default }, + { "AFMT_GENERIC4_FRAME_UPDATE", 16, 16, &umr_bitfield_default }, + { "AFMT_GENERIC4_FRAME_UPDATE_PENDING", 17, 17, &umr_bitfield_default }, + { "AFMT_GENERIC4_IMMEDIATE_UPDATE", 18, 18, &umr_bitfield_default }, + { "AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING", 19, 19, &umr_bitfield_default }, + { "AFMT_GENERIC5_FRAME_UPDATE", 20, 20, &umr_bitfield_default }, + { "AFMT_GENERIC5_FRAME_UPDATE_PENDING", 21, 21, &umr_bitfield_default }, + { "AFMT_GENERIC5_IMMEDIATE_UPDATE", 22, 22, &umr_bitfield_default }, + { "AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING", 23, 23, &umr_bitfield_default }, + { "AFMT_GENERIC6_FRAME_UPDATE", 24, 24, &umr_bitfield_default }, + { "AFMT_GENERIC6_FRAME_UPDATE_PENDING", 25, 25, &umr_bitfield_default }, + { "AFMT_GENERIC6_IMMEDIATE_UPDATE", 26, 26, &umr_bitfield_default }, + { "AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING", 27, 27, &umr_bitfield_default }, + { "AFMT_GENERIC7_FRAME_UPDATE", 28, 28, &umr_bitfield_default }, + { "AFMT_GENERIC7_FRAME_UPDATE_PENDING", 29, 29, &umr_bitfield_default }, + { "AFMT_GENERIC7_IMMEDIATE_UPDATE", 30, 30, &umr_bitfield_default }, + { "AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_LINK_CNTL[] = { + { "DP_LINK_TRAINING_COMPLETE", 4, 4, &umr_bitfield_default }, + { "DP_LINK_STATUS", 8, 8, &umr_bitfield_default }, + { "DP_EMBEDDED_PANEL_MODE", 17, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_PIXEL_FORMAT[] = { + { "DP_PIXEL_ENCODING", 0, 2, &umr_bitfield_default }, + { "DP_COMPONENT_DEPTH", 24, 26, &umr_bitfield_default }, + { "DP_PIXEL_COMBINE", 28, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_MSA_COLORIMETRY[] = { + { "DP_MSA_MISC0", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_CONFIG[] = { + { "DP_UDI_LANES", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_VID_STREAM_CNTL[] = { + { "DP_VID_STREAM_ENABLE", 0, 0, &umr_bitfield_default }, + { "DP_VID_STREAM_DIS_DEFER", 8, 9, &umr_bitfield_default }, + { "DP_VID_STREAM_STATUS", 16, 16, &umr_bitfield_default }, + { "DP_VID_STREAM_CHANGE_KEEPOUT", 20, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_STEER_FIFO[] = { + { "DP_STEER_FIFO_RESET", 0, 0, &umr_bitfield_default }, + { "DP_STEER_OVERFLOW_FLAG", 4, 4, &umr_bitfield_default }, + { "DP_STEER_OVERFLOW_INT", 5, 5, &umr_bitfield_default }, + { "DP_STEER_OVERFLOW_ACK", 6, 6, &umr_bitfield_default }, + { "DP_STEER_OVERFLOW_MASK", 7, 7, &umr_bitfield_default }, + { "DP_TU_OVERFLOW_FLAG", 8, 8, &umr_bitfield_default }, + { "DP_TU_OVERFLOW_ACK", 12, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_MSA_MISC[] = { + { "DP_MSA_MISC1", 0, 7, &umr_bitfield_default }, + { "DP_MSA_MISC2", 8, 15, &umr_bitfield_default }, + { "DP_MSA_MISC3", 16, 23, &umr_bitfield_default }, + { "DP_MSA_MISC4", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_VID_TIMING[] = { + { "DP_VID_M_N_DOUBLE_BUFFER_MODE", 4, 4, &umr_bitfield_default }, + { "DP_VID_M_N_GEN_EN", 8, 8, &umr_bitfield_default }, + { "DP_VID_N_MUL", 10, 11, &umr_bitfield_default }, + { "DP_VID_M_DIV", 12, 13, &umr_bitfield_default }, + { "DP_VID_N_DIV", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_VID_N[] = { + { "DP_VID_N", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_VID_M[] = { + { "DP_VID_M", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_LINK_FRAMING_CNTL[] = { + { "DP_IDLE_BS_INTERVAL", 0, 17, &umr_bitfield_default }, + { "DP_VBID_DISABLE", 24, 24, &umr_bitfield_default }, + { "DP_VID_ENHANCED_FRAME_MODE", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_HBR2_EYE_PATTERN[] = { + { "DP_HBR2_EYE_PATTERN_ENABLE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_VID_MSA_VBID[] = { + { "DP_VID_MSA_LOCATION", 0, 11, &umr_bitfield_default }, + { "DP_VID_VBID_FIELD_POL", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_VID_INTERRUPT_CNTL[] = { + { "DP_VID_STREAM_DISABLE_INT", 0, 0, &umr_bitfield_default }, + { "DP_VID_STREAM_DISABLE_ACK", 1, 1, &umr_bitfield_default }, + { "DP_VID_STREAM_DISABLE_MASK", 2, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_DPHY_CNTL[] = { + { "DPHY_ATEST_SEL_LANE0", 0, 0, &umr_bitfield_default }, + { "DPHY_ATEST_SEL_LANE1", 1, 1, &umr_bitfield_default }, + { "DPHY_ATEST_SEL_LANE2", 2, 2, &umr_bitfield_default }, + { "DPHY_ATEST_SEL_LANE3", 3, 3, &umr_bitfield_default }, + { "DPHY_BYPASS", 16, 16, &umr_bitfield_default }, + { "DPHY_SKEW_BYPASS", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_DPHY_TRAINING_PATTERN_SEL[] = { + { "DPHY_TRAINING_PATTERN_SEL", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_DPHY_SYM0[] = { + { "DPHY_SYM1", 0, 9, &umr_bitfield_default }, + { "DPHY_SYM2", 10, 19, &umr_bitfield_default }, + { "DPHY_SYM3", 20, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_DPHY_SYM1[] = { + { "DPHY_SYM4", 0, 9, &umr_bitfield_default }, + { "DPHY_SYM5", 10, 19, &umr_bitfield_default }, + { "DPHY_SYM6", 20, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_DPHY_SYM2[] = { + { "DPHY_SYM7", 0, 9, &umr_bitfield_default }, + { "DPHY_SYM8", 10, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_DPHY_8B10B_CNTL[] = { + { "DPHY_8B10B_RESET", 8, 8, &umr_bitfield_default }, + { "DPHY_8B10B_EXT_DISP", 16, 16, &umr_bitfield_default }, + { "DPHY_8B10B_CUR_DISP", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_DPHY_PRBS_CNTL[] = { + { "DPHY_PRBS_EN", 0, 0, &umr_bitfield_default }, + { "DPHY_PRBS_SEL", 4, 5, &umr_bitfield_default }, + { "DPHY_PRBS_SEED", 8, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_DPHY_SCRAM_CNTL[] = { + { "DPHY_SCRAMBLER_DIS", 0, 0, &umr_bitfield_default }, + { "DPHY_SCRAMBLER_ADVANCE", 4, 4, &umr_bitfield_default }, + { "DPHY_SCRAMBLER_BS_COUNT", 8, 17, &umr_bitfield_default }, + { "DPHY_SCRAMBLER_KCODE", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_DPHY_CRC_EN[] = { + { "DPHY_CRC_EN", 0, 0, &umr_bitfield_default }, + { "DPHY_CRC_CONT_EN", 4, 4, &umr_bitfield_default }, + { "DPHY_CRC_RESULT_VALID", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_DPHY_CRC_CNTL[] = { + { "DPHY_CRC_FIELD", 0, 0, &umr_bitfield_default }, + { "DPHY_CRC_SEL", 4, 5, &umr_bitfield_default }, + { "DPHY_CRC_MASK", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_DPHY_CRC_RESULT[] = { + { "DPHY_CRC_RESULT", 0, 7, &umr_bitfield_default }, + { "DPHY_CRC_RESULT1", 8, 15, &umr_bitfield_default }, + { "DPHY_CRC_RESULT2", 16, 23, &umr_bitfield_default }, + { "DPHY_CRC_RESULT3", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_DPHY_CRC_MST_CNTL[] = { + { "DPHY_CRC_MST_FIRST_SLOT", 0, 5, &umr_bitfield_default }, + { "DPHY_CRC_MST_LAST_SLOT", 8, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_DPHY_CRC_MST_STATUS[] = { + { "DPHY_CRC_MST_PHASE_LOCK", 0, 0, &umr_bitfield_default }, + { "DPHY_CRC_MST_PHASE_ERROR", 8, 8, &umr_bitfield_default }, + { "DPHY_CRC_MST_PHASE_ERROR_ACK", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_DPHY_FAST_TRAINING[] = { + { "DPHY_RX_FAST_TRAINING_CAPABLE", 0, 0, &umr_bitfield_default }, + { "DPHY_SW_FAST_TRAINING_START", 1, 1, &umr_bitfield_default }, + { "DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN", 2, 2, &umr_bitfield_default }, + { "DPHY_FAST_TRAINING_TP1_TIME", 8, 19, &umr_bitfield_default }, + { "DPHY_FAST_TRAINING_TP2_TIME", 20, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_DPHY_FAST_TRAINING_STATUS[] = { + { "DPHY_FAST_TRAINING_STATE", 0, 2, &umr_bitfield_default }, + { "DPHY_FAST_TRAINING_COMPLETE_OCCURRED", 4, 4, &umr_bitfield_default }, + { "DPHY_FAST_TRAINING_COMPLETE_MASK", 8, 8, &umr_bitfield_default }, + { "DPHY_FAST_TRAINING_COMPLETE_ACK", 12, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_SEC_CNTL[] = { + { "DP_SEC_STREAM_ENABLE", 0, 0, &umr_bitfield_default }, + { "DP_SEC_ASP_ENABLE", 4, 4, &umr_bitfield_default }, + { "DP_SEC_ATP_ENABLE", 8, 8, &umr_bitfield_default }, + { "DP_SEC_AIP_ENABLE", 12, 12, &umr_bitfield_default }, + { "DP_SEC_ACM_ENABLE", 16, 16, &umr_bitfield_default }, + { "DP_SEC_GSP0_ENABLE", 20, 20, &umr_bitfield_default }, + { "DP_SEC_GSP1_ENABLE", 21, 21, &umr_bitfield_default }, + { "DP_SEC_GSP2_ENABLE", 22, 22, &umr_bitfield_default }, + { "DP_SEC_GSP3_ENABLE", 23, 23, &umr_bitfield_default }, + { "DP_SEC_GSP4_ENABLE", 24, 24, &umr_bitfield_default }, + { "DP_SEC_GSP5_ENABLE", 25, 25, &umr_bitfield_default }, + { "DP_SEC_GSP6_ENABLE", 26, 26, &umr_bitfield_default }, + { "DP_SEC_GSP7_ENABLE", 27, 27, &umr_bitfield_default }, + { "DP_SEC_MPG_ENABLE", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_SEC_CNTL1[] = { + { "DP_SEC_ISRC_ENABLE", 0, 0, &umr_bitfield_default }, + { "DP_SEC_GSP0_PRIORITY", 4, 4, &umr_bitfield_default }, + { "DP_SEC_GSP0_SEND", 5, 5, &umr_bitfield_default }, + { "DP_SEC_GSP0_SEND_PENDING", 6, 6, &umr_bitfield_default }, + { "DP_SEC_GSP0_SEND_DEADLINE_MISSED", 7, 7, &umr_bitfield_default }, + { "DP_SEC_GSP0_SEND_ANY_LINE", 8, 8, &umr_bitfield_default }, + { "DP_SEC_GSP0_LINE_NUM", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_SEC_FRAMING1[] = { + { "DP_SEC_FRAME_START_LOCATION", 0, 11, &umr_bitfield_default }, + { "DP_SEC_VBLANK_TRANSMIT_WIDTH", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_SEC_FRAMING2[] = { + { "DP_SEC_START_POSITION", 0, 15, &umr_bitfield_default }, + { "DP_SEC_HBLANK_TRANSMIT_WIDTH", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_SEC_FRAMING3[] = { + { "DP_SEC_IDLE_FRAME_SIZE", 0, 13, &umr_bitfield_default }, + { "DP_SEC_IDLE_TRANSMIT_WIDTH", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_SEC_FRAMING4[] = { + { "DP_SEC_COLLISION_STATUS", 20, 20, &umr_bitfield_default }, + { "DP_SEC_COLLISION_ACK", 24, 24, &umr_bitfield_default }, + { "DP_SEC_AUDIO_MUTE", 28, 28, &umr_bitfield_default }, + { "DP_SEC_AUDIO_MUTE_STATUS", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_SEC_AUD_N[] = { + { "DP_SEC_AUD_N", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_SEC_AUD_N_READBACK[] = { + { "DP_SEC_AUD_N_READBACK", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_SEC_AUD_M[] = { + { "DP_SEC_AUD_M", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_SEC_AUD_M_READBACK[] = { + { "DP_SEC_AUD_M_READBACK", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_SEC_TIMESTAMP[] = { + { "DP_SEC_TIMESTAMP_MODE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_SEC_PACKET_CNTL[] = { + { "DP_SEC_ASP_CODING_TYPE", 1, 3, &umr_bitfield_default }, + { "DP_SEC_ASP_PRIORITY", 4, 4, &umr_bitfield_default }, + { "DP_SEC_VERSION", 8, 13, &umr_bitfield_default }, + { "DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_MSE_RATE_CNTL[] = { + { "DP_MSE_RATE_Y", 0, 25, &umr_bitfield_default }, + { "DP_MSE_RATE_X", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_MSE_RATE_UPDATE[] = { + { "DP_MSE_RATE_UPDATE_PENDING", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_MSE_SAT0[] = { + { "DP_MSE_SAT_SRC0", 0, 2, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT0", 8, 13, &umr_bitfield_default }, + { "DP_MSE_SAT_SRC1", 16, 18, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT1", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_MSE_SAT1[] = { + { "DP_MSE_SAT_SRC2", 0, 2, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT2", 8, 13, &umr_bitfield_default }, + { "DP_MSE_SAT_SRC3", 16, 18, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT3", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_MSE_SAT2[] = { + { "DP_MSE_SAT_SRC4", 0, 2, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT4", 8, 13, &umr_bitfield_default }, + { "DP_MSE_SAT_SRC5", 16, 18, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT5", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_MSE_SAT_UPDATE[] = { + { "DP_MSE_SAT_UPDATE", 0, 1, &umr_bitfield_default }, + { "DP_MSE_16_MTP_KEEPOUT", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_MSE_LINK_TIMING[] = { + { "DP_MSE_LINK_FRAME", 0, 9, &umr_bitfield_default }, + { "DP_MSE_LINK_LINE", 16, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_MSE_MISC_CNTL[] = { + { "DP_MSE_BLANK_CODE", 0, 0, &umr_bitfield_default }, + { "DP_MSE_TIMESTAMP_MODE", 4, 4, &umr_bitfield_default }, + { "DP_MSE_ZERO_ENCODER", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_DPHY_BS_SR_SWAP_CNTL[] = { + { "DPHY_LOAD_BS_COUNT", 0, 9, &umr_bitfield_default }, + { "DPHY_BS_SR_SWAP_DONE", 15, 15, &umr_bitfield_default }, + { "DPHY_LOAD_BS_COUNT_START", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL[] = { + { "DP_DPHY_HBR2_PATTERN_CONTROL", 0, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_MSE_SAT0_STATUS[] = { + { "DP_MSE_SAT_SRC0_STATUS", 0, 2, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT0_STATUS", 8, 13, &umr_bitfield_default }, + { "DP_MSE_SAT_SRC1_STATUS", 16, 18, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT1_STATUS", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_MSE_SAT1_STATUS[] = { + { "DP_MSE_SAT_SRC2_STATUS", 0, 2, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT2_STATUS", 8, 13, &umr_bitfield_default }, + { "DP_MSE_SAT_SRC3_STATUS", 16, 18, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT3_STATUS", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_MSE_SAT2_STATUS[] = { + { "DP_MSE_SAT_SRC4_STATUS", 0, 2, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT4_STATUS", 8, 13, &umr_bitfield_default }, + { "DP_MSE_SAT_SRC5_STATUS", 16, 18, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT5_STATUS", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_MSA_TIMING_PARAM1[] = { + { "DP_MSA_VTOTAL", 0, 15, &umr_bitfield_default }, + { "DP_MSA_HTOTAL", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_MSA_TIMING_PARAM2[] = { + { "DP_MSA_VSTART", 0, 15, &umr_bitfield_default }, + { "DP_MSA_HSTART", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_MSA_TIMING_PARAM3[] = { + { "DP_MSA_VSYNCWIDTH", 0, 14, &umr_bitfield_default }, + { "DP_MSA_VSYNCPOLARITY", 15, 15, &umr_bitfield_default }, + { "DP_MSA_HSYNCWIDTH", 16, 30, &umr_bitfield_default }, + { "DP_MSA_HSYNCPOLARITY", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_MSA_TIMING_PARAM4[] = { + { "DP_MSA_VHEIGHT", 0, 15, &umr_bitfield_default }, + { "DP_MSA_HWIDTH", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_MSO_CNTL[] = { + { "DP_MSO_NUM_OF_SSTLINK", 0, 1, &umr_bitfield_default }, + { "DP_MSO_SEC_STREAM_ENABLE", 4, 7, &umr_bitfield_default }, + { "DP_MSO_SEC_ASP_ENABLE", 8, 11, &umr_bitfield_default }, + { "DP_MSO_SEC_ATP_ENABLE", 12, 15, &umr_bitfield_default }, + { "DP_MSO_SEC_AIP_ENABLE", 16, 19, &umr_bitfield_default }, + { "DP_MSO_SEC_ACM_ENABLE", 20, 23, &umr_bitfield_default }, + { "DP_MSO_SEC_GSP0_ENABLE", 24, 27, &umr_bitfield_default }, + { "DP_MSO_SEC_GSP1_ENABLE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_MSO_CNTL1[] = { + { "DP_MSO_SEC_GSP2_ENABLE", 0, 3, &umr_bitfield_default }, + { "DP_MSO_SEC_GSP3_ENABLE", 4, 7, &umr_bitfield_default }, + { "DP_MSO_SEC_GSP4_ENABLE", 8, 11, &umr_bitfield_default }, + { "DP_MSO_SEC_GSP5_ENABLE", 12, 15, &umr_bitfield_default }, + { "DP_MSO_SEC_GSP6_ENABLE", 16, 19, &umr_bitfield_default }, + { "DP_MSO_SEC_GSP7_ENABLE", 20, 23, &umr_bitfield_default }, + { "DP_MSO_SEC_MPG_ENABLE", 24, 27, &umr_bitfield_default }, + { "DP_MSO_SEC_ISRC_ENABLE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_DSC_CNTL[] = { + { "DP_DSC_EN", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_SEC_CNTL2[] = { + { "DP_SEC_GSP1_SEND", 0, 0, &umr_bitfield_default }, + { "DP_SEC_GSP1_SEND_PENDING", 1, 1, &umr_bitfield_default }, + { "DP_SEC_GSP1_SEND_DEADLINE_MISSED", 2, 2, &umr_bitfield_default }, + { "DP_SEC_GSP1_SEND_ANY_LINE", 3, 3, &umr_bitfield_default }, + { "DP_SEC_GSP2_SEND", 4, 4, &umr_bitfield_default }, + { "DP_SEC_GSP2_SEND_PENDING", 5, 5, &umr_bitfield_default }, + { "DP_SEC_GSP2_SEND_DEADLINE_MISSED", 6, 6, &umr_bitfield_default }, + { "DP_SEC_GSP2_SEND_ANY_LINE", 7, 7, &umr_bitfield_default }, + { "DP_SEC_GSP3_SEND", 8, 8, &umr_bitfield_default }, + { "DP_SEC_GSP3_SEND_PENDING", 9, 9, &umr_bitfield_default }, + { "DP_SEC_GSP3_SEND_DEADLINE_MISSED", 10, 10, &umr_bitfield_default }, + { "DP_SEC_GSP3_SEND_ANY_LINE", 11, 11, &umr_bitfield_default }, + { "DP_SEC_GSP4_SEND", 12, 12, &umr_bitfield_default }, + { "DP_SEC_GSP4_SEND_PENDING", 13, 13, &umr_bitfield_default }, + { "DP_SEC_GSP4_SEND_DEADLINE_MISSED", 14, 14, &umr_bitfield_default }, + { "DP_SEC_GSP4_SEND_ANY_LINE", 15, 15, &umr_bitfield_default }, + { "DP_SEC_GSP5_SEND", 16, 16, &umr_bitfield_default }, + { "DP_SEC_GSP5_SEND_PENDING", 17, 17, &umr_bitfield_default }, + { "DP_SEC_GSP5_SEND_DEADLINE_MISSED", 18, 18, &umr_bitfield_default }, + { "DP_SEC_GSP5_SEND_ANY_LINE", 19, 19, &umr_bitfield_default }, + { "DP_SEC_GSP6_SEND", 20, 20, &umr_bitfield_default }, + { "DP_SEC_GSP6_SEND_PENDING", 21, 21, &umr_bitfield_default }, + { "DP_SEC_GSP6_SEND_DEADLINE_MISSED", 22, 22, &umr_bitfield_default }, + { "DP_SEC_GSP6_SEND_ANY_LINE", 23, 23, &umr_bitfield_default }, + { "DP_SEC_GSP7_SEND", 24, 24, &umr_bitfield_default }, + { "DP_SEC_GSP7_SEND_PENDING", 25, 25, &umr_bitfield_default }, + { "DP_SEC_GSP7_SEND_DEADLINE_MISSED", 26, 26, &umr_bitfield_default }, + { "DP_SEC_GSP7_SEND_ANY_LINE", 27, 27, &umr_bitfield_default }, + { "DP_SEC_GSP7_PPS", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_SEC_CNTL3[] = { + { "DP_SEC_GSP1_LINE_NUM", 0, 15, &umr_bitfield_default }, + { "DP_SEC_GSP2_LINE_NUM", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_SEC_CNTL4[] = { + { "DP_SEC_GSP3_LINE_NUM", 0, 15, &umr_bitfield_default }, + { "DP_SEC_GSP4_LINE_NUM", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_SEC_CNTL5[] = { + { "DP_SEC_GSP5_LINE_NUM", 0, 15, &umr_bitfield_default }, + { "DP_SEC_GSP6_LINE_NUM", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_SEC_CNTL6[] = { + { "DP_SEC_GSP7_LINE_NUM", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_SEC_CNTL7[] = { + { "DP_SEC_GSP0_SEND_ACTIVE", 0, 0, &umr_bitfield_default }, + { "DP_SEC_GSP1_SEND_ACTIVE", 4, 4, &umr_bitfield_default }, + { "DP_SEC_GSP2_SEND_ACTIVE", 8, 8, &umr_bitfield_default }, + { "DP_SEC_GSP3_SEND_ACTIVE", 12, 12, &umr_bitfield_default }, + { "DP_SEC_GSP4_SEND_ACTIVE", 16, 16, &umr_bitfield_default }, + { "DP_SEC_GSP5_SEND_ACTIVE", 20, 20, &umr_bitfield_default }, + { "DP_SEC_GSP6_SEND_ACTIVE", 24, 24, &umr_bitfield_default }, + { "DP_SEC_GSP7_SEND_ACTIVE", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_DB_CNTL[] = { + { "DP_DB_PENDING", 0, 0, &umr_bitfield_default }, + { "DP_DB_TAKEN", 4, 4, &umr_bitfield_default }, + { "DP_DB_TAKEN_CLR", 5, 5, &umr_bitfield_default }, + { "DP_DB_LOCK", 8, 8, &umr_bitfield_default }, + { "DP_DB_DISABLE", 12, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP0_DP_MSA_VBID_MISC[] = { + { "DP_MSA_MISC1_STEREOSYNC_OVERRIDE", 0, 1, &umr_bitfield_default }, + { "DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN", 4, 4, &umr_bitfield_default }, + { "DP_VBID1_OVERRIDE", 8, 8, &umr_bitfield_default }, + { "DP_VBID2_OVERRIDE", 9, 9, &umr_bitfield_default }, + { "DP_VBID1_OVERRIDE_EN", 12, 12, &umr_bitfield_default }, + { "DP_VBID2_OVERRIDE_EN", 13, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_DIG_FE_CNTL[] = { + { "DIG_SOURCE_SELECT", 0, 2, &umr_bitfield_default }, + { "DIG_STEREOSYNC_SELECT", 4, 6, &umr_bitfield_default }, + { "DIG_STEREOSYNC_GATE_EN", 8, 8, &umr_bitfield_default }, + { "DIG_START", 10, 10, &umr_bitfield_default }, + { "DIG_DIGITAL_BYPASS_SELECT", 12, 14, &umr_bitfield_default }, + { "DIG_SYMCLK_FE_ON", 24, 24, &umr_bitfield_default }, + { "TMDS_PIXEL_ENCODING", 28, 28, &umr_bitfield_default }, + { "TMDS_COLOR_FORMAT", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_DIG_OUTPUT_CRC_CNTL[] = { + { "DIG_OUTPUT_CRC_EN", 0, 0, &umr_bitfield_default }, + { "DIG_OUTPUT_CRC_LINK_SEL", 4, 4, &umr_bitfield_default }, + { "DIG_OUTPUT_CRC_DATA_SEL", 8, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_DIG_OUTPUT_CRC_RESULT[] = { + { "DIG_OUTPUT_CRC_RESULT", 0, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_DIG_CLOCK_PATTERN[] = { + { "DIG_CLOCK_PATTERN", 0, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_DIG_TEST_PATTERN[] = { + { "DIG_TEST_PATTERN_OUT_EN", 0, 0, &umr_bitfield_default }, + { "DIG_HALF_CLOCK_PATTERN_SEL", 1, 1, &umr_bitfield_default }, + { "DIG_RANDOM_PATTERN_OUT_EN", 4, 4, &umr_bitfield_default }, + { "DIG_RANDOM_PATTERN_RESET", 5, 5, &umr_bitfield_default }, + { "DIG_TEST_PATTERN_EXTERNAL_RESET_EN", 6, 6, &umr_bitfield_default }, + { "DIG_STATIC_TEST_PATTERN", 16, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_DIG_RANDOM_PATTERN_SEED[] = { + { "DIG_RANDOM_PATTERN_SEED", 0, 23, &umr_bitfield_default }, + { "DIG_RAN_PAT_DURING_DE_ONLY", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_DIG_FIFO_STATUS[] = { + { "DIG_FIFO_LEVEL_ERROR", 0, 0, &umr_bitfield_default }, + { "DIG_FIFO_USE_OVERWRITE_LEVEL", 1, 1, &umr_bitfield_default }, + { "DIG_FIFO_OVERWRITE_LEVEL", 2, 7, &umr_bitfield_default }, + { "DIG_FIFO_ERROR_ACK", 8, 8, &umr_bitfield_default }, + { "DIG_FIFO_CAL_AVERAGE_LEVEL", 10, 15, &umr_bitfield_default }, + { "DIG_FIFO_MAXIMUM_LEVEL", 16, 20, &umr_bitfield_default }, + { "DIG_FIFO_MINIMUM_LEVEL", 22, 25, &umr_bitfield_default }, + { "DIG_FIFO_READ_CLOCK_SRC", 26, 26, &umr_bitfield_default }, + { "DIG_FIFO_CALIBRATED", 29, 29, &umr_bitfield_default }, + { "DIG_FIFO_FORCE_RECAL_AVERAGE", 30, 30, &umr_bitfield_default }, + { "DIG_FIFO_FORCE_RECOMP_MINMAX", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_HDMI_CONTROL[] = { + { "HDMI_KEEPOUT_MODE", 0, 0, &umr_bitfield_default }, + { "HDMI_DATA_SCRAMBLE_EN", 1, 1, &umr_bitfield_default }, + { "HDMI_CLOCK_CHANNEL_RATE", 2, 2, &umr_bitfield_default }, + { "HDMI_NO_EXTRA_NULL_PACKET_FILLED", 3, 3, &umr_bitfield_default }, + { "HDMI_PACKET_GEN_VERSION", 4, 4, &umr_bitfield_default }, + { "HDMI_ERROR_ACK", 8, 8, &umr_bitfield_default }, + { "HDMI_ERROR_MASK", 9, 9, &umr_bitfield_default }, + { "HDMI_DEEP_COLOR_ENABLE", 24, 24, &umr_bitfield_default }, + { "HDMI_DEEP_COLOR_DEPTH", 28, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_HDMI_STATUS[] = { + { "HDMI_ACTIVE_AVMUTE", 0, 0, &umr_bitfield_default }, + { "HDMI_AUDIO_PACKET_ERROR", 16, 16, &umr_bitfield_default }, + { "HDMI_VBI_PACKET_ERROR", 20, 20, &umr_bitfield_default }, + { "HDMI_ERROR_INT", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_HDMI_AUDIO_PACKET_CONTROL[] = { + { "HDMI_AUDIO_DELAY_EN", 4, 5, &umr_bitfield_default }, + { "HDMI_AUDIO_PACKETS_PER_LINE", 16, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_HDMI_ACR_PACKET_CONTROL[] = { + { "HDMI_ACR_SEND", 0, 0, &umr_bitfield_default }, + { "HDMI_ACR_CONT", 1, 1, &umr_bitfield_default }, + { "HDMI_ACR_SELECT", 4, 5, &umr_bitfield_default }, + { "HDMI_ACR_SOURCE", 8, 8, &umr_bitfield_default }, + { "HDMI_ACR_AUTO_SEND", 12, 12, &umr_bitfield_default }, + { "HDMI_ACR_N_MULTIPLE", 16, 18, &umr_bitfield_default }, + { "HDMI_ACR_AUDIO_PRIORITY", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_HDMI_VBI_PACKET_CONTROL[] = { + { "HDMI_NULL_SEND", 0, 0, &umr_bitfield_default }, + { "HDMI_GC_SEND", 4, 4, &umr_bitfield_default }, + { "HDMI_GC_CONT", 5, 5, &umr_bitfield_default }, + { "HDMI_ISRC_SEND", 8, 8, &umr_bitfield_default }, + { "HDMI_ISRC_CONT", 9, 9, &umr_bitfield_default }, + { "HDMI_ISRC_LINE", 16, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_HDMI_INFOFRAME_CONTROL0[] = { + { "HDMI_AUDIO_INFO_SEND", 4, 4, &umr_bitfield_default }, + { "HDMI_AUDIO_INFO_CONT", 5, 5, &umr_bitfield_default }, + { "HDMI_MPEG_INFO_SEND", 8, 8, &umr_bitfield_default }, + { "HDMI_MPEG_INFO_CONT", 9, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_HDMI_INFOFRAME_CONTROL1[] = { + { "HDMI_AUDIO_INFO_LINE", 8, 13, &umr_bitfield_default }, + { "HDMI_MPEG_INFO_LINE", 16, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_HDMI_GENERIC_PACKET_CONTROL0[] = { + { "HDMI_GENERIC0_SEND", 0, 0, &umr_bitfield_default }, + { "HDMI_GENERIC0_CONT", 1, 1, &umr_bitfield_default }, + { "HDMI_GENERIC1_SEND", 4, 4, &umr_bitfield_default }, + { "HDMI_GENERIC1_CONT", 5, 5, &umr_bitfield_default }, + { "HDMI_GENERIC0_LINE", 16, 21, &umr_bitfield_default }, + { "HDMI_GENERIC1_LINE", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_HDMI_GC[] = { + { "HDMI_GC_AVMUTE", 0, 0, &umr_bitfield_default }, + { "HDMI_GC_AVMUTE_CONT", 2, 2, &umr_bitfield_default }, + { "HDMI_DEFAULT_PHASE", 4, 4, &umr_bitfield_default }, + { "HDMI_PACKING_PHASE", 8, 11, &umr_bitfield_default }, + { "HDMI_PACKING_PHASE_OVERRIDE", 12, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_AFMT_AUDIO_PACKET_CONTROL2[] = { + { "AFMT_AUDIO_LAYOUT_OVRD", 0, 0, &umr_bitfield_default }, + { "AFMT_AUDIO_LAYOUT_SELECT", 1, 1, &umr_bitfield_default }, + { "AFMT_AUDIO_CHANNEL_ENABLE", 8, 15, &umr_bitfield_default }, + { "AFMT_DP_AUDIO_STREAM_ID", 16, 23, &umr_bitfield_default }, + { "AFMT_HBR_ENABLE_OVRD", 24, 24, &umr_bitfield_default }, + { "AFMT_60958_OSF_OVRD", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_AFMT_ISRC1_0[] = { + { "AFMT_ISRC_STATUS", 0, 2, &umr_bitfield_default }, + { "AFMT_ISRC_CONTINUE", 6, 6, &umr_bitfield_default }, + { "AFMT_ISRC_VALID", 7, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_AFMT_ISRC1_1[] = { + { "AFMT_UPC_EAN_ISRC0", 0, 7, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC1", 8, 15, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC2", 16, 23, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC3", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_AFMT_ISRC1_2[] = { + { "AFMT_UPC_EAN_ISRC4", 0, 7, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC5", 8, 15, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC6", 16, 23, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC7", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_AFMT_ISRC1_3[] = { + { "AFMT_UPC_EAN_ISRC8", 0, 7, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC9", 8, 15, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC10", 16, 23, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC11", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_AFMT_ISRC1_4[] = { + { "AFMT_UPC_EAN_ISRC12", 0, 7, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC13", 8, 15, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC14", 16, 23, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC15", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_AFMT_ISRC2_0[] = { + { "AFMT_UPC_EAN_ISRC16", 0, 7, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC17", 8, 15, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC18", 16, 23, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC19", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_AFMT_ISRC2_1[] = { + { "AFMT_UPC_EAN_ISRC20", 0, 7, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC21", 8, 15, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC22", 16, 23, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC23", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_AFMT_ISRC2_2[] = { + { "AFMT_UPC_EAN_ISRC24", 0, 7, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC25", 8, 15, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC26", 16, 23, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC27", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_AFMT_ISRC2_3[] = { + { "AFMT_UPC_EAN_ISRC28", 0, 7, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC29", 8, 15, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC30", 16, 23, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC31", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_HDMI_GENERIC_PACKET_CONTROL2[] = { + { "HDMI_GENERIC4_SEND", 0, 0, &umr_bitfield_default }, + { "HDMI_GENERIC4_CONT", 1, 1, &umr_bitfield_default }, + { "HDMI_GENERIC5_SEND", 4, 4, &umr_bitfield_default }, + { "HDMI_GENERIC5_CONT", 5, 5, &umr_bitfield_default }, + { "HDMI_GENERIC4_LINE", 16, 21, &umr_bitfield_default }, + { "HDMI_GENERIC5_LINE", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_HDMI_GENERIC_PACKET_CONTROL3[] = { + { "HDMI_GENERIC6_SEND", 0, 0, &umr_bitfield_default }, + { "HDMI_GENERIC6_CONT", 1, 1, &umr_bitfield_default }, + { "HDMI_GENERIC7_SEND", 4, 4, &umr_bitfield_default }, + { "HDMI_GENERIC7_CONT", 5, 5, &umr_bitfield_default }, + { "HDMI_GENERIC6_LINE", 16, 21, &umr_bitfield_default }, + { "HDMI_GENERIC7_LINE", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_HDMI_DB_CONTROL[] = { + { "HDMI_DB_PENDING", 0, 0, &umr_bitfield_default }, + { "HDMI_DB_TAKEN", 4, 4, &umr_bitfield_default }, + { "HDMI_DB_TAKEN_CLR", 5, 5, &umr_bitfield_default }, + { "HDMI_DB_LOCK", 8, 8, &umr_bitfield_default }, + { "HDMI_DB_DISABLE", 12, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_AFMT_MPEG_INFO0[] = { + { "AFMT_MPEG_INFO_CHECKSUM", 0, 7, &umr_bitfield_default }, + { "AFMT_MPEG_INFO_MB0", 8, 15, &umr_bitfield_default }, + { "AFMT_MPEG_INFO_MB1", 16, 23, &umr_bitfield_default }, + { "AFMT_MPEG_INFO_MB2", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_AFMT_MPEG_INFO1[] = { + { "AFMT_MPEG_INFO_MB3", 0, 7, &umr_bitfield_default }, + { "AFMT_MPEG_INFO_MF", 8, 9, &umr_bitfield_default }, + { "AFMT_MPEG_INFO_FR", 12, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_AFMT_GENERIC_HDR[] = { + { "AFMT_GENERIC_HB0", 0, 7, &umr_bitfield_default }, + { "AFMT_GENERIC_HB1", 8, 15, &umr_bitfield_default }, + { "AFMT_GENERIC_HB2", 16, 23, &umr_bitfield_default }, + { "AFMT_GENERIC_HB3", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_AFMT_GENERIC_0[] = { + { "AFMT_GENERIC_BYTE0", 0, 7, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE1", 8, 15, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE2", 16, 23, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE3", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_AFMT_GENERIC_1[] = { + { "AFMT_GENERIC_BYTE4", 0, 7, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE5", 8, 15, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE6", 16, 23, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE7", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_AFMT_GENERIC_2[] = { + { "AFMT_GENERIC_BYTE8", 0, 7, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE9", 8, 15, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE10", 16, 23, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE11", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_AFMT_GENERIC_3[] = { + { "AFMT_GENERIC_BYTE12", 0, 7, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE13", 8, 15, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE14", 16, 23, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE15", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_AFMT_GENERIC_4[] = { + { "AFMT_GENERIC_BYTE16", 0, 7, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE17", 8, 15, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE18", 16, 23, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE19", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_AFMT_GENERIC_5[] = { + { "AFMT_GENERIC_BYTE20", 0, 7, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE21", 8, 15, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE22", 16, 23, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE23", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_AFMT_GENERIC_6[] = { + { "AFMT_GENERIC_BYTE24", 0, 7, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE25", 8, 15, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE26", 16, 23, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE27", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_AFMT_GENERIC_7[] = { + { "AFMT_GENERIC_BYTE28", 0, 7, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE29", 8, 15, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE30", 16, 23, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE31", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_HDMI_GENERIC_PACKET_CONTROL1[] = { + { "HDMI_GENERIC2_SEND", 0, 0, &umr_bitfield_default }, + { "HDMI_GENERIC2_CONT", 1, 1, &umr_bitfield_default }, + { "HDMI_GENERIC3_SEND", 4, 4, &umr_bitfield_default }, + { "HDMI_GENERIC3_CONT", 5, 5, &umr_bitfield_default }, + { "HDMI_GENERIC2_LINE", 16, 21, &umr_bitfield_default }, + { "HDMI_GENERIC3_LINE", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_HDMI_ACR_32_0[] = { + { "HDMI_ACR_CTS_32", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_HDMI_ACR_32_1[] = { + { "HDMI_ACR_N_32", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_HDMI_ACR_44_0[] = { + { "HDMI_ACR_CTS_44", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_HDMI_ACR_44_1[] = { + { "HDMI_ACR_N_44", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_HDMI_ACR_48_0[] = { + { "HDMI_ACR_CTS_48", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_HDMI_ACR_48_1[] = { + { "HDMI_ACR_N_48", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_HDMI_ACR_STATUS_0[] = { + { "HDMI_ACR_CTS", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_HDMI_ACR_STATUS_1[] = { + { "HDMI_ACR_N", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_AFMT_AUDIO_INFO0[] = { + { "AFMT_AUDIO_INFO_CHECKSUM", 0, 7, &umr_bitfield_default }, + { "AFMT_AUDIO_INFO_CC", 8, 10, &umr_bitfield_default }, + { "AFMT_AUDIO_INFO_CT", 11, 14, &umr_bitfield_default }, + { "AFMT_AUDIO_INFO_CHECKSUM_OFFSET", 16, 23, &umr_bitfield_default }, + { "AFMT_AUDIO_INFO_CXT", 24, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_AFMT_AUDIO_INFO1[] = { + { "AFMT_AUDIO_INFO_CA", 0, 7, &umr_bitfield_default }, + { "AFMT_AUDIO_INFO_LSV", 11, 14, &umr_bitfield_default }, + { "AFMT_AUDIO_INFO_DM_INH", 15, 15, &umr_bitfield_default }, + { "AFMT_AUDIO_INFO_LFEPBL", 16, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_AFMT_60958_0[] = { + { "AFMT_60958_CS_A", 0, 0, &umr_bitfield_default }, + { "AFMT_60958_CS_B", 1, 1, &umr_bitfield_default }, + { "AFMT_60958_CS_C", 2, 2, &umr_bitfield_default }, + { "AFMT_60958_CS_D", 3, 5, &umr_bitfield_default }, + { "AFMT_60958_CS_MODE", 6, 7, &umr_bitfield_default }, + { "AFMT_60958_CS_CATEGORY_CODE", 8, 15, &umr_bitfield_default }, + { "AFMT_60958_CS_SOURCE_NUMBER", 16, 19, &umr_bitfield_default }, + { "AFMT_60958_CS_CHANNEL_NUMBER_L", 20, 23, &umr_bitfield_default }, + { "AFMT_60958_CS_SAMPLING_FREQUENCY", 24, 27, &umr_bitfield_default }, + { "AFMT_60958_CS_CLOCK_ACCURACY", 28, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_AFMT_60958_1[] = { + { "AFMT_60958_CS_WORD_LENGTH", 0, 3, &umr_bitfield_default }, + { "AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY", 4, 7, &umr_bitfield_default }, + { "AFMT_60958_VALID_L", 16, 16, &umr_bitfield_default }, + { "AFMT_60958_VALID_R", 18, 18, &umr_bitfield_default }, + { "AFMT_60958_CS_CHANNEL_NUMBER_R", 20, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_AFMT_AUDIO_CRC_CONTROL[] = { + { "AFMT_AUDIO_CRC_EN", 0, 0, &umr_bitfield_default }, + { "AFMT_AUDIO_CRC_CONT", 4, 4, &umr_bitfield_default }, + { "AFMT_AUDIO_CRC_SOURCE", 8, 8, &umr_bitfield_default }, + { "AFMT_AUDIO_CRC_CH_SEL", 12, 15, &umr_bitfield_default }, + { "AFMT_AUDIO_CRC_COUNT", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_AFMT_RAMP_CONTROL0[] = { + { "AFMT_RAMP_MAX_COUNT", 0, 23, &umr_bitfield_default }, + { "AFMT_RAMP_DATA_SIGN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_AFMT_RAMP_CONTROL1[] = { + { "AFMT_RAMP_MIN_COUNT", 0, 23, &umr_bitfield_default }, + { "AFMT_AUDIO_TEST_CH_DISABLE", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_AFMT_RAMP_CONTROL2[] = { + { "AFMT_RAMP_INC_COUNT", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_AFMT_RAMP_CONTROL3[] = { + { "AFMT_RAMP_DEC_COUNT", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_AFMT_60958_2[] = { + { "AFMT_60958_CS_CHANNEL_NUMBER_2", 0, 3, &umr_bitfield_default }, + { "AFMT_60958_CS_CHANNEL_NUMBER_3", 4, 7, &umr_bitfield_default }, + { "AFMT_60958_CS_CHANNEL_NUMBER_4", 8, 11, &umr_bitfield_default }, + { "AFMT_60958_CS_CHANNEL_NUMBER_5", 12, 15, &umr_bitfield_default }, + { "AFMT_60958_CS_CHANNEL_NUMBER_6", 16, 19, &umr_bitfield_default }, + { "AFMT_60958_CS_CHANNEL_NUMBER_7", 20, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_AFMT_AUDIO_CRC_RESULT[] = { + { "AFMT_AUDIO_CRC_DONE", 0, 0, &umr_bitfield_default }, + { "AFMT_AUDIO_CRC", 8, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_AFMT_STATUS[] = { + { "AFMT_AUDIO_ENABLE", 4, 4, &umr_bitfield_default }, + { "AFMT_AZ_HBR_ENABLE", 8, 8, &umr_bitfield_default }, + { "AFMT_AUDIO_FIFO_OVERFLOW", 24, 24, &umr_bitfield_default }, + { "AFMT_AZ_AUDIO_ENABLE_CHG", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_AFMT_AUDIO_PACKET_CONTROL[] = { + { "AFMT_AUDIO_SAMPLE_SEND", 0, 0, &umr_bitfield_default }, + { "AFMT_RESET_FIFO_WHEN_AUDIO_DIS", 11, 11, &umr_bitfield_default }, + { "AFMT_AUDIO_TEST_EN", 12, 12, &umr_bitfield_default }, + { "AFMT_AUDIO_TEST_MODE", 14, 14, &umr_bitfield_default }, + { "AFMT_AUDIO_FIFO_OVERFLOW_ACK", 23, 23, &umr_bitfield_default }, + { "AFMT_AUDIO_CHANNEL_SWAP", 24, 24, &umr_bitfield_default }, + { "AFMT_60958_CS_UPDATE", 26, 26, &umr_bitfield_default }, + { "AFMT_AZ_AUDIO_ENABLE_CHG_ACK", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_AFMT_VBI_PACKET_CONTROL[] = { + { "AFMT_GENERIC_LOCK_STATUS", 8, 8, &umr_bitfield_default }, + { "AFMT_GENERIC_CONFLICT", 16, 16, &umr_bitfield_default }, + { "AFMT_GENERIC_CONFLICT_CLR", 17, 17, &umr_bitfield_default }, + { "AFMT_GENERIC_INDEX", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_AFMT_INFOFRAME_CONTROL0[] = { + { "AFMT_AUDIO_INFO_SOURCE", 6, 6, &umr_bitfield_default }, + { "AFMT_AUDIO_INFO_UPDATE", 7, 7, &umr_bitfield_default }, + { "AFMT_MPEG_INFO_UPDATE", 10, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_AFMT_AUDIO_SRC_CONTROL[] = { + { "AFMT_AUDIO_SRC_SELECT", 0, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_DIG_BE_CNTL[] = { + { "DIG_DUAL_LINK_ENABLE", 0, 0, &umr_bitfield_default }, + { "DIG_SWAP", 1, 1, &umr_bitfield_default }, + { "DIG_FE_SOURCE_SELECT", 8, 14, &umr_bitfield_default }, + { "DIG_MODE", 16, 18, &umr_bitfield_default }, + { "DIG_HPD_SELECT", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_DIG_BE_EN_CNTL[] = { + { "DIG_ENABLE", 0, 0, &umr_bitfield_default }, + { "DIG_SYMCLK_BE_ON", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_TMDS_CNTL[] = { + { "TMDS_SYNC_PHASE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_TMDS_CONTROL_CHAR[] = { + { "TMDS_CONTROL_CHAR0_OUT_EN", 0, 0, &umr_bitfield_default }, + { "TMDS_CONTROL_CHAR1_OUT_EN", 1, 1, &umr_bitfield_default }, + { "TMDS_CONTROL_CHAR2_OUT_EN", 2, 2, &umr_bitfield_default }, + { "TMDS_CONTROL_CHAR3_OUT_EN", 3, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_TMDS_CONTROL0_FEEDBACK[] = { + { "TMDS_CONTROL0_FEEDBACK_SELECT", 0, 1, &umr_bitfield_default }, + { "TMDS_CONTROL0_FEEDBACK_DELAY", 8, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_TMDS_STEREOSYNC_CTL_SEL[] = { + { "TMDS_STEREOSYNC_CTL_SEL", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1[] = { + { "TMDS_SYNC_CHAR_PATTERN0", 0, 9, &umr_bitfield_default }, + { "TMDS_SYNC_CHAR_PATTERN1", 16, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3[] = { + { "TMDS_SYNC_CHAR_PATTERN2", 0, 9, &umr_bitfield_default }, + { "TMDS_SYNC_CHAR_PATTERN3", 16, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_TMDS_CTL_BITS[] = { + { "TMDS_CTL0", 0, 0, &umr_bitfield_default }, + { "TMDS_CTL1", 8, 8, &umr_bitfield_default }, + { "TMDS_CTL2", 16, 16, &umr_bitfield_default }, + { "TMDS_CTL3", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_TMDS_DCBALANCER_CONTROL[] = { + { "TMDS_DCBALANCER_EN", 0, 0, &umr_bitfield_default }, + { "TMDS_DCBALANCER_TEST_EN", 8, 8, &umr_bitfield_default }, + { "TMDS_DCBALANCER_TEST_IN", 16, 19, &umr_bitfield_default }, + { "TMDS_DCBALANCER_FORCE", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_TMDS_CTL0_1_GEN_CNTL[] = { + { "TMDS_CTL0_DATA_SEL", 0, 3, &umr_bitfield_default }, + { "TMDS_CTL0_DATA_DELAY", 4, 6, &umr_bitfield_default }, + { "TMDS_CTL0_DATA_INVERT", 7, 7, &umr_bitfield_default }, + { "TMDS_CTL0_DATA_MODULATION", 8, 9, &umr_bitfield_default }, + { "TMDS_CTL0_USE_FEEDBACK_PATH", 10, 10, &umr_bitfield_default }, + { "TMDS_CTL0_FB_SYNC_CONT", 11, 11, &umr_bitfield_default }, + { "TMDS_CTL0_PATTERN_OUT_EN", 12, 12, &umr_bitfield_default }, + { "TMDS_CTL1_DATA_SEL", 16, 19, &umr_bitfield_default }, + { "TMDS_CTL1_DATA_DELAY", 20, 22, &umr_bitfield_default }, + { "TMDS_CTL1_DATA_INVERT", 23, 23, &umr_bitfield_default }, + { "TMDS_CTL1_DATA_MODULATION", 24, 25, &umr_bitfield_default }, + { "TMDS_CTL1_USE_FEEDBACK_PATH", 26, 26, &umr_bitfield_default }, + { "TMDS_CTL1_FB_SYNC_CONT", 27, 27, &umr_bitfield_default }, + { "TMDS_CTL1_PATTERN_OUT_EN", 28, 28, &umr_bitfield_default }, + { "TMDS_2BIT_COUNTER_EN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_TMDS_CTL2_3_GEN_CNTL[] = { + { "TMDS_CTL2_DATA_SEL", 0, 3, &umr_bitfield_default }, + { "TMDS_CTL2_DATA_DELAY", 4, 6, &umr_bitfield_default }, + { "TMDS_CTL2_DATA_INVERT", 7, 7, &umr_bitfield_default }, + { "TMDS_CTL2_DATA_MODULATION", 8, 9, &umr_bitfield_default }, + { "TMDS_CTL2_USE_FEEDBACK_PATH", 10, 10, &umr_bitfield_default }, + { "TMDS_CTL2_FB_SYNC_CONT", 11, 11, &umr_bitfield_default }, + { "TMDS_CTL2_PATTERN_OUT_EN", 12, 12, &umr_bitfield_default }, + { "TMDS_CTL3_DATA_SEL", 16, 19, &umr_bitfield_default }, + { "TMDS_CTL3_DATA_DELAY", 20, 22, &umr_bitfield_default }, + { "TMDS_CTL3_DATA_INVERT", 23, 23, &umr_bitfield_default }, + { "TMDS_CTL3_DATA_MODULATION", 24, 25, &umr_bitfield_default }, + { "TMDS_CTL3_USE_FEEDBACK_PATH", 26, 26, &umr_bitfield_default }, + { "TMDS_CTL3_FB_SYNC_CONT", 27, 27, &umr_bitfield_default }, + { "TMDS_CTL3_PATTERN_OUT_EN", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_DIG_VERSION[] = { + { "DIG_TYPE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_DIG_LANE_ENABLE[] = { + { "DIG_LANE0EN", 0, 0, &umr_bitfield_default }, + { "DIG_LANE1EN", 1, 1, &umr_bitfield_default }, + { "DIG_LANE2EN", 2, 2, &umr_bitfield_default }, + { "DIG_LANE3EN", 3, 3, &umr_bitfield_default }, + { "DIG_CLK_EN", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_AFMT_CNTL[] = { + { "AFMT_AUDIO_CLOCK_EN", 0, 0, &umr_bitfield_default }, + { "AFMT_AUDIO_CLOCK_ON", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG1_AFMT_VBI_PACKET_CONTROL1[] = { + { "AFMT_GENERIC0_FRAME_UPDATE", 0, 0, &umr_bitfield_default }, + { "AFMT_GENERIC0_FRAME_UPDATE_PENDING", 1, 1, &umr_bitfield_default }, + { "AFMT_GENERIC0_IMMEDIATE_UPDATE", 2, 2, &umr_bitfield_default }, + { "AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING", 3, 3, &umr_bitfield_default }, + { "AFMT_GENERIC1_FRAME_UPDATE", 4, 4, &umr_bitfield_default }, + { "AFMT_GENERIC1_FRAME_UPDATE_PENDING", 5, 5, &umr_bitfield_default }, + { "AFMT_GENERIC1_IMMEDIATE_UPDATE", 6, 6, &umr_bitfield_default }, + { "AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING", 7, 7, &umr_bitfield_default }, + { "AFMT_GENERIC2_FRAME_UPDATE", 8, 8, &umr_bitfield_default }, + { "AFMT_GENERIC2_FRAME_UPDATE_PENDING", 9, 9, &umr_bitfield_default }, + { "AFMT_GENERIC2_IMMEDIATE_UPDATE", 10, 10, &umr_bitfield_default }, + { "AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING", 11, 11, &umr_bitfield_default }, + { "AFMT_GENERIC3_FRAME_UPDATE", 12, 12, &umr_bitfield_default }, + { "AFMT_GENERIC3_FRAME_UPDATE_PENDING", 13, 13, &umr_bitfield_default }, + { "AFMT_GENERIC3_IMMEDIATE_UPDATE", 14, 14, &umr_bitfield_default }, + { "AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING", 15, 15, &umr_bitfield_default }, + { "AFMT_GENERIC4_FRAME_UPDATE", 16, 16, &umr_bitfield_default }, + { "AFMT_GENERIC4_FRAME_UPDATE_PENDING", 17, 17, &umr_bitfield_default }, + { "AFMT_GENERIC4_IMMEDIATE_UPDATE", 18, 18, &umr_bitfield_default }, + { "AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING", 19, 19, &umr_bitfield_default }, + { "AFMT_GENERIC5_FRAME_UPDATE", 20, 20, &umr_bitfield_default }, + { "AFMT_GENERIC5_FRAME_UPDATE_PENDING", 21, 21, &umr_bitfield_default }, + { "AFMT_GENERIC5_IMMEDIATE_UPDATE", 22, 22, &umr_bitfield_default }, + { "AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING", 23, 23, &umr_bitfield_default }, + { "AFMT_GENERIC6_FRAME_UPDATE", 24, 24, &umr_bitfield_default }, + { "AFMT_GENERIC6_FRAME_UPDATE_PENDING", 25, 25, &umr_bitfield_default }, + { "AFMT_GENERIC6_IMMEDIATE_UPDATE", 26, 26, &umr_bitfield_default }, + { "AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING", 27, 27, &umr_bitfield_default }, + { "AFMT_GENERIC7_FRAME_UPDATE", 28, 28, &umr_bitfield_default }, + { "AFMT_GENERIC7_FRAME_UPDATE_PENDING", 29, 29, &umr_bitfield_default }, + { "AFMT_GENERIC7_IMMEDIATE_UPDATE", 30, 30, &umr_bitfield_default }, + { "AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_LINK_CNTL[] = { + { "DP_LINK_TRAINING_COMPLETE", 4, 4, &umr_bitfield_default }, + { "DP_LINK_STATUS", 8, 8, &umr_bitfield_default }, + { "DP_EMBEDDED_PANEL_MODE", 17, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_PIXEL_FORMAT[] = { + { "DP_PIXEL_ENCODING", 0, 2, &umr_bitfield_default }, + { "DP_COMPONENT_DEPTH", 24, 26, &umr_bitfield_default }, + { "DP_PIXEL_COMBINE", 28, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_MSA_COLORIMETRY[] = { + { "DP_MSA_MISC0", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_CONFIG[] = { + { "DP_UDI_LANES", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_VID_STREAM_CNTL[] = { + { "DP_VID_STREAM_ENABLE", 0, 0, &umr_bitfield_default }, + { "DP_VID_STREAM_DIS_DEFER", 8, 9, &umr_bitfield_default }, + { "DP_VID_STREAM_STATUS", 16, 16, &umr_bitfield_default }, + { "DP_VID_STREAM_CHANGE_KEEPOUT", 20, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_STEER_FIFO[] = { + { "DP_STEER_FIFO_RESET", 0, 0, &umr_bitfield_default }, + { "DP_STEER_OVERFLOW_FLAG", 4, 4, &umr_bitfield_default }, + { "DP_STEER_OVERFLOW_INT", 5, 5, &umr_bitfield_default }, + { "DP_STEER_OVERFLOW_ACK", 6, 6, &umr_bitfield_default }, + { "DP_STEER_OVERFLOW_MASK", 7, 7, &umr_bitfield_default }, + { "DP_TU_OVERFLOW_FLAG", 8, 8, &umr_bitfield_default }, + { "DP_TU_OVERFLOW_ACK", 12, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_MSA_MISC[] = { + { "DP_MSA_MISC1", 0, 7, &umr_bitfield_default }, + { "DP_MSA_MISC2", 8, 15, &umr_bitfield_default }, + { "DP_MSA_MISC3", 16, 23, &umr_bitfield_default }, + { "DP_MSA_MISC4", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_VID_TIMING[] = { + { "DP_VID_M_N_DOUBLE_BUFFER_MODE", 4, 4, &umr_bitfield_default }, + { "DP_VID_M_N_GEN_EN", 8, 8, &umr_bitfield_default }, + { "DP_VID_N_MUL", 10, 11, &umr_bitfield_default }, + { "DP_VID_M_DIV", 12, 13, &umr_bitfield_default }, + { "DP_VID_N_DIV", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_VID_N[] = { + { "DP_VID_N", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_VID_M[] = { + { "DP_VID_M", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_LINK_FRAMING_CNTL[] = { + { "DP_IDLE_BS_INTERVAL", 0, 17, &umr_bitfield_default }, + { "DP_VBID_DISABLE", 24, 24, &umr_bitfield_default }, + { "DP_VID_ENHANCED_FRAME_MODE", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_HBR2_EYE_PATTERN[] = { + { "DP_HBR2_EYE_PATTERN_ENABLE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_VID_MSA_VBID[] = { + { "DP_VID_MSA_LOCATION", 0, 11, &umr_bitfield_default }, + { "DP_VID_VBID_FIELD_POL", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_VID_INTERRUPT_CNTL[] = { + { "DP_VID_STREAM_DISABLE_INT", 0, 0, &umr_bitfield_default }, + { "DP_VID_STREAM_DISABLE_ACK", 1, 1, &umr_bitfield_default }, + { "DP_VID_STREAM_DISABLE_MASK", 2, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_DPHY_CNTL[] = { + { "DPHY_ATEST_SEL_LANE0", 0, 0, &umr_bitfield_default }, + { "DPHY_ATEST_SEL_LANE1", 1, 1, &umr_bitfield_default }, + { "DPHY_ATEST_SEL_LANE2", 2, 2, &umr_bitfield_default }, + { "DPHY_ATEST_SEL_LANE3", 3, 3, &umr_bitfield_default }, + { "DPHY_BYPASS", 16, 16, &umr_bitfield_default }, + { "DPHY_SKEW_BYPASS", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_DPHY_TRAINING_PATTERN_SEL[] = { + { "DPHY_TRAINING_PATTERN_SEL", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_DPHY_SYM0[] = { + { "DPHY_SYM1", 0, 9, &umr_bitfield_default }, + { "DPHY_SYM2", 10, 19, &umr_bitfield_default }, + { "DPHY_SYM3", 20, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_DPHY_SYM1[] = { + { "DPHY_SYM4", 0, 9, &umr_bitfield_default }, + { "DPHY_SYM5", 10, 19, &umr_bitfield_default }, + { "DPHY_SYM6", 20, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_DPHY_SYM2[] = { + { "DPHY_SYM7", 0, 9, &umr_bitfield_default }, + { "DPHY_SYM8", 10, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_DPHY_8B10B_CNTL[] = { + { "DPHY_8B10B_RESET", 8, 8, &umr_bitfield_default }, + { "DPHY_8B10B_EXT_DISP", 16, 16, &umr_bitfield_default }, + { "DPHY_8B10B_CUR_DISP", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_DPHY_PRBS_CNTL[] = { + { "DPHY_PRBS_EN", 0, 0, &umr_bitfield_default }, + { "DPHY_PRBS_SEL", 4, 5, &umr_bitfield_default }, + { "DPHY_PRBS_SEED", 8, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_DPHY_SCRAM_CNTL[] = { + { "DPHY_SCRAMBLER_DIS", 0, 0, &umr_bitfield_default }, + { "DPHY_SCRAMBLER_ADVANCE", 4, 4, &umr_bitfield_default }, + { "DPHY_SCRAMBLER_BS_COUNT", 8, 17, &umr_bitfield_default }, + { "DPHY_SCRAMBLER_KCODE", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_DPHY_CRC_EN[] = { + { "DPHY_CRC_EN", 0, 0, &umr_bitfield_default }, + { "DPHY_CRC_CONT_EN", 4, 4, &umr_bitfield_default }, + { "DPHY_CRC_RESULT_VALID", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_DPHY_CRC_CNTL[] = { + { "DPHY_CRC_FIELD", 0, 0, &umr_bitfield_default }, + { "DPHY_CRC_SEL", 4, 5, &umr_bitfield_default }, + { "DPHY_CRC_MASK", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_DPHY_CRC_RESULT[] = { + { "DPHY_CRC_RESULT", 0, 7, &umr_bitfield_default }, + { "DPHY_CRC_RESULT1", 8, 15, &umr_bitfield_default }, + { "DPHY_CRC_RESULT2", 16, 23, &umr_bitfield_default }, + { "DPHY_CRC_RESULT3", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_DPHY_CRC_MST_CNTL[] = { + { "DPHY_CRC_MST_FIRST_SLOT", 0, 5, &umr_bitfield_default }, + { "DPHY_CRC_MST_LAST_SLOT", 8, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_DPHY_CRC_MST_STATUS[] = { + { "DPHY_CRC_MST_PHASE_LOCK", 0, 0, &umr_bitfield_default }, + { "DPHY_CRC_MST_PHASE_ERROR", 8, 8, &umr_bitfield_default }, + { "DPHY_CRC_MST_PHASE_ERROR_ACK", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_DPHY_FAST_TRAINING[] = { + { "DPHY_RX_FAST_TRAINING_CAPABLE", 0, 0, &umr_bitfield_default }, + { "DPHY_SW_FAST_TRAINING_START", 1, 1, &umr_bitfield_default }, + { "DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN", 2, 2, &umr_bitfield_default }, + { "DPHY_FAST_TRAINING_TP1_TIME", 8, 19, &umr_bitfield_default }, + { "DPHY_FAST_TRAINING_TP2_TIME", 20, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_DPHY_FAST_TRAINING_STATUS[] = { + { "DPHY_FAST_TRAINING_STATE", 0, 2, &umr_bitfield_default }, + { "DPHY_FAST_TRAINING_COMPLETE_OCCURRED", 4, 4, &umr_bitfield_default }, + { "DPHY_FAST_TRAINING_COMPLETE_MASK", 8, 8, &umr_bitfield_default }, + { "DPHY_FAST_TRAINING_COMPLETE_ACK", 12, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_SEC_CNTL[] = { + { "DP_SEC_STREAM_ENABLE", 0, 0, &umr_bitfield_default }, + { "DP_SEC_ASP_ENABLE", 4, 4, &umr_bitfield_default }, + { "DP_SEC_ATP_ENABLE", 8, 8, &umr_bitfield_default }, + { "DP_SEC_AIP_ENABLE", 12, 12, &umr_bitfield_default }, + { "DP_SEC_ACM_ENABLE", 16, 16, &umr_bitfield_default }, + { "DP_SEC_GSP0_ENABLE", 20, 20, &umr_bitfield_default }, + { "DP_SEC_GSP1_ENABLE", 21, 21, &umr_bitfield_default }, + { "DP_SEC_GSP2_ENABLE", 22, 22, &umr_bitfield_default }, + { "DP_SEC_GSP3_ENABLE", 23, 23, &umr_bitfield_default }, + { "DP_SEC_GSP4_ENABLE", 24, 24, &umr_bitfield_default }, + { "DP_SEC_GSP5_ENABLE", 25, 25, &umr_bitfield_default }, + { "DP_SEC_GSP6_ENABLE", 26, 26, &umr_bitfield_default }, + { "DP_SEC_GSP7_ENABLE", 27, 27, &umr_bitfield_default }, + { "DP_SEC_MPG_ENABLE", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_SEC_CNTL1[] = { + { "DP_SEC_ISRC_ENABLE", 0, 0, &umr_bitfield_default }, + { "DP_SEC_GSP0_PRIORITY", 4, 4, &umr_bitfield_default }, + { "DP_SEC_GSP0_SEND", 5, 5, &umr_bitfield_default }, + { "DP_SEC_GSP0_SEND_PENDING", 6, 6, &umr_bitfield_default }, + { "DP_SEC_GSP0_SEND_DEADLINE_MISSED", 7, 7, &umr_bitfield_default }, + { "DP_SEC_GSP0_SEND_ANY_LINE", 8, 8, &umr_bitfield_default }, + { "DP_SEC_GSP0_LINE_NUM", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_SEC_FRAMING1[] = { + { "DP_SEC_FRAME_START_LOCATION", 0, 11, &umr_bitfield_default }, + { "DP_SEC_VBLANK_TRANSMIT_WIDTH", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_SEC_FRAMING2[] = { + { "DP_SEC_START_POSITION", 0, 15, &umr_bitfield_default }, + { "DP_SEC_HBLANK_TRANSMIT_WIDTH", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_SEC_FRAMING3[] = { + { "DP_SEC_IDLE_FRAME_SIZE", 0, 13, &umr_bitfield_default }, + { "DP_SEC_IDLE_TRANSMIT_WIDTH", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_SEC_FRAMING4[] = { + { "DP_SEC_COLLISION_STATUS", 20, 20, &umr_bitfield_default }, + { "DP_SEC_COLLISION_ACK", 24, 24, &umr_bitfield_default }, + { "DP_SEC_AUDIO_MUTE", 28, 28, &umr_bitfield_default }, + { "DP_SEC_AUDIO_MUTE_STATUS", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_SEC_AUD_N[] = { + { "DP_SEC_AUD_N", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_SEC_AUD_N_READBACK[] = { + { "DP_SEC_AUD_N_READBACK", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_SEC_AUD_M[] = { + { "DP_SEC_AUD_M", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_SEC_AUD_M_READBACK[] = { + { "DP_SEC_AUD_M_READBACK", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_SEC_TIMESTAMP[] = { + { "DP_SEC_TIMESTAMP_MODE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_SEC_PACKET_CNTL[] = { + { "DP_SEC_ASP_CODING_TYPE", 1, 3, &umr_bitfield_default }, + { "DP_SEC_ASP_PRIORITY", 4, 4, &umr_bitfield_default }, + { "DP_SEC_VERSION", 8, 13, &umr_bitfield_default }, + { "DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_MSE_RATE_CNTL[] = { + { "DP_MSE_RATE_Y", 0, 25, &umr_bitfield_default }, + { "DP_MSE_RATE_X", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_MSE_RATE_UPDATE[] = { + { "DP_MSE_RATE_UPDATE_PENDING", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_MSE_SAT0[] = { + { "DP_MSE_SAT_SRC0", 0, 2, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT0", 8, 13, &umr_bitfield_default }, + { "DP_MSE_SAT_SRC1", 16, 18, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT1", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_MSE_SAT1[] = { + { "DP_MSE_SAT_SRC2", 0, 2, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT2", 8, 13, &umr_bitfield_default }, + { "DP_MSE_SAT_SRC3", 16, 18, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT3", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_MSE_SAT2[] = { + { "DP_MSE_SAT_SRC4", 0, 2, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT4", 8, 13, &umr_bitfield_default }, + { "DP_MSE_SAT_SRC5", 16, 18, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT5", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_MSE_SAT_UPDATE[] = { + { "DP_MSE_SAT_UPDATE", 0, 1, &umr_bitfield_default }, + { "DP_MSE_16_MTP_KEEPOUT", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_MSE_LINK_TIMING[] = { + { "DP_MSE_LINK_FRAME", 0, 9, &umr_bitfield_default }, + { "DP_MSE_LINK_LINE", 16, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_MSE_MISC_CNTL[] = { + { "DP_MSE_BLANK_CODE", 0, 0, &umr_bitfield_default }, + { "DP_MSE_TIMESTAMP_MODE", 4, 4, &umr_bitfield_default }, + { "DP_MSE_ZERO_ENCODER", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_DPHY_BS_SR_SWAP_CNTL[] = { + { "DPHY_LOAD_BS_COUNT", 0, 9, &umr_bitfield_default }, + { "DPHY_BS_SR_SWAP_DONE", 15, 15, &umr_bitfield_default }, + { "DPHY_LOAD_BS_COUNT_START", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL[] = { + { "DP_DPHY_HBR2_PATTERN_CONTROL", 0, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_MSE_SAT0_STATUS[] = { + { "DP_MSE_SAT_SRC0_STATUS", 0, 2, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT0_STATUS", 8, 13, &umr_bitfield_default }, + { "DP_MSE_SAT_SRC1_STATUS", 16, 18, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT1_STATUS", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_MSE_SAT1_STATUS[] = { + { "DP_MSE_SAT_SRC2_STATUS", 0, 2, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT2_STATUS", 8, 13, &umr_bitfield_default }, + { "DP_MSE_SAT_SRC3_STATUS", 16, 18, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT3_STATUS", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_MSE_SAT2_STATUS[] = { + { "DP_MSE_SAT_SRC4_STATUS", 0, 2, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT4_STATUS", 8, 13, &umr_bitfield_default }, + { "DP_MSE_SAT_SRC5_STATUS", 16, 18, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT5_STATUS", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_MSA_TIMING_PARAM1[] = { + { "DP_MSA_VTOTAL", 0, 15, &umr_bitfield_default }, + { "DP_MSA_HTOTAL", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_MSA_TIMING_PARAM2[] = { + { "DP_MSA_VSTART", 0, 15, &umr_bitfield_default }, + { "DP_MSA_HSTART", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_MSA_TIMING_PARAM3[] = { + { "DP_MSA_VSYNCWIDTH", 0, 14, &umr_bitfield_default }, + { "DP_MSA_VSYNCPOLARITY", 15, 15, &umr_bitfield_default }, + { "DP_MSA_HSYNCWIDTH", 16, 30, &umr_bitfield_default }, + { "DP_MSA_HSYNCPOLARITY", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_MSA_TIMING_PARAM4[] = { + { "DP_MSA_VHEIGHT", 0, 15, &umr_bitfield_default }, + { "DP_MSA_HWIDTH", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_MSO_CNTL[] = { + { "DP_MSO_NUM_OF_SSTLINK", 0, 1, &umr_bitfield_default }, + { "DP_MSO_SEC_STREAM_ENABLE", 4, 7, &umr_bitfield_default }, + { "DP_MSO_SEC_ASP_ENABLE", 8, 11, &umr_bitfield_default }, + { "DP_MSO_SEC_ATP_ENABLE", 12, 15, &umr_bitfield_default }, + { "DP_MSO_SEC_AIP_ENABLE", 16, 19, &umr_bitfield_default }, + { "DP_MSO_SEC_ACM_ENABLE", 20, 23, &umr_bitfield_default }, + { "DP_MSO_SEC_GSP0_ENABLE", 24, 27, &umr_bitfield_default }, + { "DP_MSO_SEC_GSP1_ENABLE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_MSO_CNTL1[] = { + { "DP_MSO_SEC_GSP2_ENABLE", 0, 3, &umr_bitfield_default }, + { "DP_MSO_SEC_GSP3_ENABLE", 4, 7, &umr_bitfield_default }, + { "DP_MSO_SEC_GSP4_ENABLE", 8, 11, &umr_bitfield_default }, + { "DP_MSO_SEC_GSP5_ENABLE", 12, 15, &umr_bitfield_default }, + { "DP_MSO_SEC_GSP6_ENABLE", 16, 19, &umr_bitfield_default }, + { "DP_MSO_SEC_GSP7_ENABLE", 20, 23, &umr_bitfield_default }, + { "DP_MSO_SEC_MPG_ENABLE", 24, 27, &umr_bitfield_default }, + { "DP_MSO_SEC_ISRC_ENABLE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_DSC_CNTL[] = { + { "DP_DSC_EN", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_SEC_CNTL2[] = { + { "DP_SEC_GSP1_SEND", 0, 0, &umr_bitfield_default }, + { "DP_SEC_GSP1_SEND_PENDING", 1, 1, &umr_bitfield_default }, + { "DP_SEC_GSP1_SEND_DEADLINE_MISSED", 2, 2, &umr_bitfield_default }, + { "DP_SEC_GSP1_SEND_ANY_LINE", 3, 3, &umr_bitfield_default }, + { "DP_SEC_GSP2_SEND", 4, 4, &umr_bitfield_default }, + { "DP_SEC_GSP2_SEND_PENDING", 5, 5, &umr_bitfield_default }, + { "DP_SEC_GSP2_SEND_DEADLINE_MISSED", 6, 6, &umr_bitfield_default }, + { "DP_SEC_GSP2_SEND_ANY_LINE", 7, 7, &umr_bitfield_default }, + { "DP_SEC_GSP3_SEND", 8, 8, &umr_bitfield_default }, + { "DP_SEC_GSP3_SEND_PENDING", 9, 9, &umr_bitfield_default }, + { "DP_SEC_GSP3_SEND_DEADLINE_MISSED", 10, 10, &umr_bitfield_default }, + { "DP_SEC_GSP3_SEND_ANY_LINE", 11, 11, &umr_bitfield_default }, + { "DP_SEC_GSP4_SEND", 12, 12, &umr_bitfield_default }, + { "DP_SEC_GSP4_SEND_PENDING", 13, 13, &umr_bitfield_default }, + { "DP_SEC_GSP4_SEND_DEADLINE_MISSED", 14, 14, &umr_bitfield_default }, + { "DP_SEC_GSP4_SEND_ANY_LINE", 15, 15, &umr_bitfield_default }, + { "DP_SEC_GSP5_SEND", 16, 16, &umr_bitfield_default }, + { "DP_SEC_GSP5_SEND_PENDING", 17, 17, &umr_bitfield_default }, + { "DP_SEC_GSP5_SEND_DEADLINE_MISSED", 18, 18, &umr_bitfield_default }, + { "DP_SEC_GSP5_SEND_ANY_LINE", 19, 19, &umr_bitfield_default }, + { "DP_SEC_GSP6_SEND", 20, 20, &umr_bitfield_default }, + { "DP_SEC_GSP6_SEND_PENDING", 21, 21, &umr_bitfield_default }, + { "DP_SEC_GSP6_SEND_DEADLINE_MISSED", 22, 22, &umr_bitfield_default }, + { "DP_SEC_GSP6_SEND_ANY_LINE", 23, 23, &umr_bitfield_default }, + { "DP_SEC_GSP7_SEND", 24, 24, &umr_bitfield_default }, + { "DP_SEC_GSP7_SEND_PENDING", 25, 25, &umr_bitfield_default }, + { "DP_SEC_GSP7_SEND_DEADLINE_MISSED", 26, 26, &umr_bitfield_default }, + { "DP_SEC_GSP7_SEND_ANY_LINE", 27, 27, &umr_bitfield_default }, + { "DP_SEC_GSP7_PPS", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_SEC_CNTL3[] = { + { "DP_SEC_GSP1_LINE_NUM", 0, 15, &umr_bitfield_default }, + { "DP_SEC_GSP2_LINE_NUM", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_SEC_CNTL4[] = { + { "DP_SEC_GSP3_LINE_NUM", 0, 15, &umr_bitfield_default }, + { "DP_SEC_GSP4_LINE_NUM", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_SEC_CNTL5[] = { + { "DP_SEC_GSP5_LINE_NUM", 0, 15, &umr_bitfield_default }, + { "DP_SEC_GSP6_LINE_NUM", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_SEC_CNTL6[] = { + { "DP_SEC_GSP7_LINE_NUM", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_SEC_CNTL7[] = { + { "DP_SEC_GSP0_SEND_ACTIVE", 0, 0, &umr_bitfield_default }, + { "DP_SEC_GSP1_SEND_ACTIVE", 4, 4, &umr_bitfield_default }, + { "DP_SEC_GSP2_SEND_ACTIVE", 8, 8, &umr_bitfield_default }, + { "DP_SEC_GSP3_SEND_ACTIVE", 12, 12, &umr_bitfield_default }, + { "DP_SEC_GSP4_SEND_ACTIVE", 16, 16, &umr_bitfield_default }, + { "DP_SEC_GSP5_SEND_ACTIVE", 20, 20, &umr_bitfield_default }, + { "DP_SEC_GSP6_SEND_ACTIVE", 24, 24, &umr_bitfield_default }, + { "DP_SEC_GSP7_SEND_ACTIVE", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_DB_CNTL[] = { + { "DP_DB_PENDING", 0, 0, &umr_bitfield_default }, + { "DP_DB_TAKEN", 4, 4, &umr_bitfield_default }, + { "DP_DB_TAKEN_CLR", 5, 5, &umr_bitfield_default }, + { "DP_DB_LOCK", 8, 8, &umr_bitfield_default }, + { "DP_DB_DISABLE", 12, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP1_DP_MSA_VBID_MISC[] = { + { "DP_MSA_MISC1_STEREOSYNC_OVERRIDE", 0, 1, &umr_bitfield_default }, + { "DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN", 4, 4, &umr_bitfield_default }, + { "DP_VBID1_OVERRIDE", 8, 8, &umr_bitfield_default }, + { "DP_VBID2_OVERRIDE", 9, 9, &umr_bitfield_default }, + { "DP_VBID1_OVERRIDE_EN", 12, 12, &umr_bitfield_default }, + { "DP_VBID2_OVERRIDE_EN", 13, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_DIG_FE_CNTL[] = { + { "DIG_SOURCE_SELECT", 0, 2, &umr_bitfield_default }, + { "DIG_STEREOSYNC_SELECT", 4, 6, &umr_bitfield_default }, + { "DIG_STEREOSYNC_GATE_EN", 8, 8, &umr_bitfield_default }, + { "DIG_START", 10, 10, &umr_bitfield_default }, + { "DIG_DIGITAL_BYPASS_SELECT", 12, 14, &umr_bitfield_default }, + { "DIG_SYMCLK_FE_ON", 24, 24, &umr_bitfield_default }, + { "TMDS_PIXEL_ENCODING", 28, 28, &umr_bitfield_default }, + { "TMDS_COLOR_FORMAT", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_DIG_OUTPUT_CRC_CNTL[] = { + { "DIG_OUTPUT_CRC_EN", 0, 0, &umr_bitfield_default }, + { "DIG_OUTPUT_CRC_LINK_SEL", 4, 4, &umr_bitfield_default }, + { "DIG_OUTPUT_CRC_DATA_SEL", 8, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_DIG_OUTPUT_CRC_RESULT[] = { + { "DIG_OUTPUT_CRC_RESULT", 0, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_DIG_CLOCK_PATTERN[] = { + { "DIG_CLOCK_PATTERN", 0, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_DIG_TEST_PATTERN[] = { + { "DIG_TEST_PATTERN_OUT_EN", 0, 0, &umr_bitfield_default }, + { "DIG_HALF_CLOCK_PATTERN_SEL", 1, 1, &umr_bitfield_default }, + { "DIG_RANDOM_PATTERN_OUT_EN", 4, 4, &umr_bitfield_default }, + { "DIG_RANDOM_PATTERN_RESET", 5, 5, &umr_bitfield_default }, + { "DIG_TEST_PATTERN_EXTERNAL_RESET_EN", 6, 6, &umr_bitfield_default }, + { "DIG_STATIC_TEST_PATTERN", 16, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_DIG_RANDOM_PATTERN_SEED[] = { + { "DIG_RANDOM_PATTERN_SEED", 0, 23, &umr_bitfield_default }, + { "DIG_RAN_PAT_DURING_DE_ONLY", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_DIG_FIFO_STATUS[] = { + { "DIG_FIFO_LEVEL_ERROR", 0, 0, &umr_bitfield_default }, + { "DIG_FIFO_USE_OVERWRITE_LEVEL", 1, 1, &umr_bitfield_default }, + { "DIG_FIFO_OVERWRITE_LEVEL", 2, 7, &umr_bitfield_default }, + { "DIG_FIFO_ERROR_ACK", 8, 8, &umr_bitfield_default }, + { "DIG_FIFO_CAL_AVERAGE_LEVEL", 10, 15, &umr_bitfield_default }, + { "DIG_FIFO_MAXIMUM_LEVEL", 16, 20, &umr_bitfield_default }, + { "DIG_FIFO_MINIMUM_LEVEL", 22, 25, &umr_bitfield_default }, + { "DIG_FIFO_READ_CLOCK_SRC", 26, 26, &umr_bitfield_default }, + { "DIG_FIFO_CALIBRATED", 29, 29, &umr_bitfield_default }, + { "DIG_FIFO_FORCE_RECAL_AVERAGE", 30, 30, &umr_bitfield_default }, + { "DIG_FIFO_FORCE_RECOMP_MINMAX", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_HDMI_CONTROL[] = { + { "HDMI_KEEPOUT_MODE", 0, 0, &umr_bitfield_default }, + { "HDMI_DATA_SCRAMBLE_EN", 1, 1, &umr_bitfield_default }, + { "HDMI_CLOCK_CHANNEL_RATE", 2, 2, &umr_bitfield_default }, + { "HDMI_NO_EXTRA_NULL_PACKET_FILLED", 3, 3, &umr_bitfield_default }, + { "HDMI_PACKET_GEN_VERSION", 4, 4, &umr_bitfield_default }, + { "HDMI_ERROR_ACK", 8, 8, &umr_bitfield_default }, + { "HDMI_ERROR_MASK", 9, 9, &umr_bitfield_default }, + { "HDMI_DEEP_COLOR_ENABLE", 24, 24, &umr_bitfield_default }, + { "HDMI_DEEP_COLOR_DEPTH", 28, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_HDMI_STATUS[] = { + { "HDMI_ACTIVE_AVMUTE", 0, 0, &umr_bitfield_default }, + { "HDMI_AUDIO_PACKET_ERROR", 16, 16, &umr_bitfield_default }, + { "HDMI_VBI_PACKET_ERROR", 20, 20, &umr_bitfield_default }, + { "HDMI_ERROR_INT", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_HDMI_AUDIO_PACKET_CONTROL[] = { + { "HDMI_AUDIO_DELAY_EN", 4, 5, &umr_bitfield_default }, + { "HDMI_AUDIO_PACKETS_PER_LINE", 16, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_HDMI_ACR_PACKET_CONTROL[] = { + { "HDMI_ACR_SEND", 0, 0, &umr_bitfield_default }, + { "HDMI_ACR_CONT", 1, 1, &umr_bitfield_default }, + { "HDMI_ACR_SELECT", 4, 5, &umr_bitfield_default }, + { "HDMI_ACR_SOURCE", 8, 8, &umr_bitfield_default }, + { "HDMI_ACR_AUTO_SEND", 12, 12, &umr_bitfield_default }, + { "HDMI_ACR_N_MULTIPLE", 16, 18, &umr_bitfield_default }, + { "HDMI_ACR_AUDIO_PRIORITY", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_HDMI_VBI_PACKET_CONTROL[] = { + { "HDMI_NULL_SEND", 0, 0, &umr_bitfield_default }, + { "HDMI_GC_SEND", 4, 4, &umr_bitfield_default }, + { "HDMI_GC_CONT", 5, 5, &umr_bitfield_default }, + { "HDMI_ISRC_SEND", 8, 8, &umr_bitfield_default }, + { "HDMI_ISRC_CONT", 9, 9, &umr_bitfield_default }, + { "HDMI_ISRC_LINE", 16, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_HDMI_INFOFRAME_CONTROL0[] = { + { "HDMI_AUDIO_INFO_SEND", 4, 4, &umr_bitfield_default }, + { "HDMI_AUDIO_INFO_CONT", 5, 5, &umr_bitfield_default }, + { "HDMI_MPEG_INFO_SEND", 8, 8, &umr_bitfield_default }, + { "HDMI_MPEG_INFO_CONT", 9, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_HDMI_INFOFRAME_CONTROL1[] = { + { "HDMI_AUDIO_INFO_LINE", 8, 13, &umr_bitfield_default }, + { "HDMI_MPEG_INFO_LINE", 16, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_HDMI_GENERIC_PACKET_CONTROL0[] = { + { "HDMI_GENERIC0_SEND", 0, 0, &umr_bitfield_default }, + { "HDMI_GENERIC0_CONT", 1, 1, &umr_bitfield_default }, + { "HDMI_GENERIC1_SEND", 4, 4, &umr_bitfield_default }, + { "HDMI_GENERIC1_CONT", 5, 5, &umr_bitfield_default }, + { "HDMI_GENERIC0_LINE", 16, 21, &umr_bitfield_default }, + { "HDMI_GENERIC1_LINE", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_HDMI_GC[] = { + { "HDMI_GC_AVMUTE", 0, 0, &umr_bitfield_default }, + { "HDMI_GC_AVMUTE_CONT", 2, 2, &umr_bitfield_default }, + { "HDMI_DEFAULT_PHASE", 4, 4, &umr_bitfield_default }, + { "HDMI_PACKING_PHASE", 8, 11, &umr_bitfield_default }, + { "HDMI_PACKING_PHASE_OVERRIDE", 12, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_AFMT_AUDIO_PACKET_CONTROL2[] = { + { "AFMT_AUDIO_LAYOUT_OVRD", 0, 0, &umr_bitfield_default }, + { "AFMT_AUDIO_LAYOUT_SELECT", 1, 1, &umr_bitfield_default }, + { "AFMT_AUDIO_CHANNEL_ENABLE", 8, 15, &umr_bitfield_default }, + { "AFMT_DP_AUDIO_STREAM_ID", 16, 23, &umr_bitfield_default }, + { "AFMT_HBR_ENABLE_OVRD", 24, 24, &umr_bitfield_default }, + { "AFMT_60958_OSF_OVRD", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_AFMT_ISRC1_0[] = { + { "AFMT_ISRC_STATUS", 0, 2, &umr_bitfield_default }, + { "AFMT_ISRC_CONTINUE", 6, 6, &umr_bitfield_default }, + { "AFMT_ISRC_VALID", 7, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_AFMT_ISRC1_1[] = { + { "AFMT_UPC_EAN_ISRC0", 0, 7, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC1", 8, 15, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC2", 16, 23, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC3", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_AFMT_ISRC1_2[] = { + { "AFMT_UPC_EAN_ISRC4", 0, 7, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC5", 8, 15, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC6", 16, 23, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC7", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_AFMT_ISRC1_3[] = { + { "AFMT_UPC_EAN_ISRC8", 0, 7, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC9", 8, 15, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC10", 16, 23, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC11", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_AFMT_ISRC1_4[] = { + { "AFMT_UPC_EAN_ISRC12", 0, 7, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC13", 8, 15, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC14", 16, 23, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC15", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_AFMT_ISRC2_0[] = { + { "AFMT_UPC_EAN_ISRC16", 0, 7, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC17", 8, 15, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC18", 16, 23, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC19", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_AFMT_ISRC2_1[] = { + { "AFMT_UPC_EAN_ISRC20", 0, 7, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC21", 8, 15, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC22", 16, 23, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC23", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_AFMT_ISRC2_2[] = { + { "AFMT_UPC_EAN_ISRC24", 0, 7, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC25", 8, 15, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC26", 16, 23, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC27", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_AFMT_ISRC2_3[] = { + { "AFMT_UPC_EAN_ISRC28", 0, 7, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC29", 8, 15, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC30", 16, 23, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC31", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_HDMI_GENERIC_PACKET_CONTROL2[] = { + { "HDMI_GENERIC4_SEND", 0, 0, &umr_bitfield_default }, + { "HDMI_GENERIC4_CONT", 1, 1, &umr_bitfield_default }, + { "HDMI_GENERIC5_SEND", 4, 4, &umr_bitfield_default }, + { "HDMI_GENERIC5_CONT", 5, 5, &umr_bitfield_default }, + { "HDMI_GENERIC4_LINE", 16, 21, &umr_bitfield_default }, + { "HDMI_GENERIC5_LINE", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_HDMI_GENERIC_PACKET_CONTROL3[] = { + { "HDMI_GENERIC6_SEND", 0, 0, &umr_bitfield_default }, + { "HDMI_GENERIC6_CONT", 1, 1, &umr_bitfield_default }, + { "HDMI_GENERIC7_SEND", 4, 4, &umr_bitfield_default }, + { "HDMI_GENERIC7_CONT", 5, 5, &umr_bitfield_default }, + { "HDMI_GENERIC6_LINE", 16, 21, &umr_bitfield_default }, + { "HDMI_GENERIC7_LINE", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_HDMI_DB_CONTROL[] = { + { "HDMI_DB_PENDING", 0, 0, &umr_bitfield_default }, + { "HDMI_DB_TAKEN", 4, 4, &umr_bitfield_default }, + { "HDMI_DB_TAKEN_CLR", 5, 5, &umr_bitfield_default }, + { "HDMI_DB_LOCK", 8, 8, &umr_bitfield_default }, + { "HDMI_DB_DISABLE", 12, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_AFMT_MPEG_INFO0[] = { + { "AFMT_MPEG_INFO_CHECKSUM", 0, 7, &umr_bitfield_default }, + { "AFMT_MPEG_INFO_MB0", 8, 15, &umr_bitfield_default }, + { "AFMT_MPEG_INFO_MB1", 16, 23, &umr_bitfield_default }, + { "AFMT_MPEG_INFO_MB2", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_AFMT_MPEG_INFO1[] = { + { "AFMT_MPEG_INFO_MB3", 0, 7, &umr_bitfield_default }, + { "AFMT_MPEG_INFO_MF", 8, 9, &umr_bitfield_default }, + { "AFMT_MPEG_INFO_FR", 12, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_AFMT_GENERIC_HDR[] = { + { "AFMT_GENERIC_HB0", 0, 7, &umr_bitfield_default }, + { "AFMT_GENERIC_HB1", 8, 15, &umr_bitfield_default }, + { "AFMT_GENERIC_HB2", 16, 23, &umr_bitfield_default }, + { "AFMT_GENERIC_HB3", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_AFMT_GENERIC_0[] = { + { "AFMT_GENERIC_BYTE0", 0, 7, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE1", 8, 15, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE2", 16, 23, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE3", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_AFMT_GENERIC_1[] = { + { "AFMT_GENERIC_BYTE4", 0, 7, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE5", 8, 15, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE6", 16, 23, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE7", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_AFMT_GENERIC_2[] = { + { "AFMT_GENERIC_BYTE8", 0, 7, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE9", 8, 15, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE10", 16, 23, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE11", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_AFMT_GENERIC_3[] = { + { "AFMT_GENERIC_BYTE12", 0, 7, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE13", 8, 15, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE14", 16, 23, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE15", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_AFMT_GENERIC_4[] = { + { "AFMT_GENERIC_BYTE16", 0, 7, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE17", 8, 15, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE18", 16, 23, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE19", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_AFMT_GENERIC_5[] = { + { "AFMT_GENERIC_BYTE20", 0, 7, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE21", 8, 15, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE22", 16, 23, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE23", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_AFMT_GENERIC_6[] = { + { "AFMT_GENERIC_BYTE24", 0, 7, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE25", 8, 15, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE26", 16, 23, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE27", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_AFMT_GENERIC_7[] = { + { "AFMT_GENERIC_BYTE28", 0, 7, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE29", 8, 15, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE30", 16, 23, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE31", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_HDMI_GENERIC_PACKET_CONTROL1[] = { + { "HDMI_GENERIC2_SEND", 0, 0, &umr_bitfield_default }, + { "HDMI_GENERIC2_CONT", 1, 1, &umr_bitfield_default }, + { "HDMI_GENERIC3_SEND", 4, 4, &umr_bitfield_default }, + { "HDMI_GENERIC3_CONT", 5, 5, &umr_bitfield_default }, + { "HDMI_GENERIC2_LINE", 16, 21, &umr_bitfield_default }, + { "HDMI_GENERIC3_LINE", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_HDMI_ACR_32_0[] = { + { "HDMI_ACR_CTS_32", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_HDMI_ACR_32_1[] = { + { "HDMI_ACR_N_32", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_HDMI_ACR_44_0[] = { + { "HDMI_ACR_CTS_44", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_HDMI_ACR_44_1[] = { + { "HDMI_ACR_N_44", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_HDMI_ACR_48_0[] = { + { "HDMI_ACR_CTS_48", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_HDMI_ACR_48_1[] = { + { "HDMI_ACR_N_48", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_HDMI_ACR_STATUS_0[] = { + { "HDMI_ACR_CTS", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_HDMI_ACR_STATUS_1[] = { + { "HDMI_ACR_N", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_AFMT_AUDIO_INFO0[] = { + { "AFMT_AUDIO_INFO_CHECKSUM", 0, 7, &umr_bitfield_default }, + { "AFMT_AUDIO_INFO_CC", 8, 10, &umr_bitfield_default }, + { "AFMT_AUDIO_INFO_CT", 11, 14, &umr_bitfield_default }, + { "AFMT_AUDIO_INFO_CHECKSUM_OFFSET", 16, 23, &umr_bitfield_default }, + { "AFMT_AUDIO_INFO_CXT", 24, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_AFMT_AUDIO_INFO1[] = { + { "AFMT_AUDIO_INFO_CA", 0, 7, &umr_bitfield_default }, + { "AFMT_AUDIO_INFO_LSV", 11, 14, &umr_bitfield_default }, + { "AFMT_AUDIO_INFO_DM_INH", 15, 15, &umr_bitfield_default }, + { "AFMT_AUDIO_INFO_LFEPBL", 16, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_AFMT_60958_0[] = { + { "AFMT_60958_CS_A", 0, 0, &umr_bitfield_default }, + { "AFMT_60958_CS_B", 1, 1, &umr_bitfield_default }, + { "AFMT_60958_CS_C", 2, 2, &umr_bitfield_default }, + { "AFMT_60958_CS_D", 3, 5, &umr_bitfield_default }, + { "AFMT_60958_CS_MODE", 6, 7, &umr_bitfield_default }, + { "AFMT_60958_CS_CATEGORY_CODE", 8, 15, &umr_bitfield_default }, + { "AFMT_60958_CS_SOURCE_NUMBER", 16, 19, &umr_bitfield_default }, + { "AFMT_60958_CS_CHANNEL_NUMBER_L", 20, 23, &umr_bitfield_default }, + { "AFMT_60958_CS_SAMPLING_FREQUENCY", 24, 27, &umr_bitfield_default }, + { "AFMT_60958_CS_CLOCK_ACCURACY", 28, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_AFMT_60958_1[] = { + { "AFMT_60958_CS_WORD_LENGTH", 0, 3, &umr_bitfield_default }, + { "AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY", 4, 7, &umr_bitfield_default }, + { "AFMT_60958_VALID_L", 16, 16, &umr_bitfield_default }, + { "AFMT_60958_VALID_R", 18, 18, &umr_bitfield_default }, + { "AFMT_60958_CS_CHANNEL_NUMBER_R", 20, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_AFMT_AUDIO_CRC_CONTROL[] = { + { "AFMT_AUDIO_CRC_EN", 0, 0, &umr_bitfield_default }, + { "AFMT_AUDIO_CRC_CONT", 4, 4, &umr_bitfield_default }, + { "AFMT_AUDIO_CRC_SOURCE", 8, 8, &umr_bitfield_default }, + { "AFMT_AUDIO_CRC_CH_SEL", 12, 15, &umr_bitfield_default }, + { "AFMT_AUDIO_CRC_COUNT", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_AFMT_RAMP_CONTROL0[] = { + { "AFMT_RAMP_MAX_COUNT", 0, 23, &umr_bitfield_default }, + { "AFMT_RAMP_DATA_SIGN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_AFMT_RAMP_CONTROL1[] = { + { "AFMT_RAMP_MIN_COUNT", 0, 23, &umr_bitfield_default }, + { "AFMT_AUDIO_TEST_CH_DISABLE", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_AFMT_RAMP_CONTROL2[] = { + { "AFMT_RAMP_INC_COUNT", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_AFMT_RAMP_CONTROL3[] = { + { "AFMT_RAMP_DEC_COUNT", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_AFMT_60958_2[] = { + { "AFMT_60958_CS_CHANNEL_NUMBER_2", 0, 3, &umr_bitfield_default }, + { "AFMT_60958_CS_CHANNEL_NUMBER_3", 4, 7, &umr_bitfield_default }, + { "AFMT_60958_CS_CHANNEL_NUMBER_4", 8, 11, &umr_bitfield_default }, + { "AFMT_60958_CS_CHANNEL_NUMBER_5", 12, 15, &umr_bitfield_default }, + { "AFMT_60958_CS_CHANNEL_NUMBER_6", 16, 19, &umr_bitfield_default }, + { "AFMT_60958_CS_CHANNEL_NUMBER_7", 20, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_AFMT_AUDIO_CRC_RESULT[] = { + { "AFMT_AUDIO_CRC_DONE", 0, 0, &umr_bitfield_default }, + { "AFMT_AUDIO_CRC", 8, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_AFMT_STATUS[] = { + { "AFMT_AUDIO_ENABLE", 4, 4, &umr_bitfield_default }, + { "AFMT_AZ_HBR_ENABLE", 8, 8, &umr_bitfield_default }, + { "AFMT_AUDIO_FIFO_OVERFLOW", 24, 24, &umr_bitfield_default }, + { "AFMT_AZ_AUDIO_ENABLE_CHG", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_AFMT_AUDIO_PACKET_CONTROL[] = { + { "AFMT_AUDIO_SAMPLE_SEND", 0, 0, &umr_bitfield_default }, + { "AFMT_RESET_FIFO_WHEN_AUDIO_DIS", 11, 11, &umr_bitfield_default }, + { "AFMT_AUDIO_TEST_EN", 12, 12, &umr_bitfield_default }, + { "AFMT_AUDIO_TEST_MODE", 14, 14, &umr_bitfield_default }, + { "AFMT_AUDIO_FIFO_OVERFLOW_ACK", 23, 23, &umr_bitfield_default }, + { "AFMT_AUDIO_CHANNEL_SWAP", 24, 24, &umr_bitfield_default }, + { "AFMT_60958_CS_UPDATE", 26, 26, &umr_bitfield_default }, + { "AFMT_AZ_AUDIO_ENABLE_CHG_ACK", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_AFMT_VBI_PACKET_CONTROL[] = { + { "AFMT_GENERIC_LOCK_STATUS", 8, 8, &umr_bitfield_default }, + { "AFMT_GENERIC_CONFLICT", 16, 16, &umr_bitfield_default }, + { "AFMT_GENERIC_CONFLICT_CLR", 17, 17, &umr_bitfield_default }, + { "AFMT_GENERIC_INDEX", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_AFMT_INFOFRAME_CONTROL0[] = { + { "AFMT_AUDIO_INFO_SOURCE", 6, 6, &umr_bitfield_default }, + { "AFMT_AUDIO_INFO_UPDATE", 7, 7, &umr_bitfield_default }, + { "AFMT_MPEG_INFO_UPDATE", 10, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_AFMT_AUDIO_SRC_CONTROL[] = { + { "AFMT_AUDIO_SRC_SELECT", 0, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_DIG_BE_CNTL[] = { + { "DIG_DUAL_LINK_ENABLE", 0, 0, &umr_bitfield_default }, + { "DIG_SWAP", 1, 1, &umr_bitfield_default }, + { "DIG_FE_SOURCE_SELECT", 8, 14, &umr_bitfield_default }, + { "DIG_MODE", 16, 18, &umr_bitfield_default }, + { "DIG_HPD_SELECT", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_DIG_BE_EN_CNTL[] = { + { "DIG_ENABLE", 0, 0, &umr_bitfield_default }, + { "DIG_SYMCLK_BE_ON", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_TMDS_CNTL[] = { + { "TMDS_SYNC_PHASE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_TMDS_CONTROL_CHAR[] = { + { "TMDS_CONTROL_CHAR0_OUT_EN", 0, 0, &umr_bitfield_default }, + { "TMDS_CONTROL_CHAR1_OUT_EN", 1, 1, &umr_bitfield_default }, + { "TMDS_CONTROL_CHAR2_OUT_EN", 2, 2, &umr_bitfield_default }, + { "TMDS_CONTROL_CHAR3_OUT_EN", 3, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_TMDS_CONTROL0_FEEDBACK[] = { + { "TMDS_CONTROL0_FEEDBACK_SELECT", 0, 1, &umr_bitfield_default }, + { "TMDS_CONTROL0_FEEDBACK_DELAY", 8, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_TMDS_STEREOSYNC_CTL_SEL[] = { + { "TMDS_STEREOSYNC_CTL_SEL", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1[] = { + { "TMDS_SYNC_CHAR_PATTERN0", 0, 9, &umr_bitfield_default }, + { "TMDS_SYNC_CHAR_PATTERN1", 16, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3[] = { + { "TMDS_SYNC_CHAR_PATTERN2", 0, 9, &umr_bitfield_default }, + { "TMDS_SYNC_CHAR_PATTERN3", 16, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_TMDS_CTL_BITS[] = { + { "TMDS_CTL0", 0, 0, &umr_bitfield_default }, + { "TMDS_CTL1", 8, 8, &umr_bitfield_default }, + { "TMDS_CTL2", 16, 16, &umr_bitfield_default }, + { "TMDS_CTL3", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_TMDS_DCBALANCER_CONTROL[] = { + { "TMDS_DCBALANCER_EN", 0, 0, &umr_bitfield_default }, + { "TMDS_DCBALANCER_TEST_EN", 8, 8, &umr_bitfield_default }, + { "TMDS_DCBALANCER_TEST_IN", 16, 19, &umr_bitfield_default }, + { "TMDS_DCBALANCER_FORCE", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_TMDS_CTL0_1_GEN_CNTL[] = { + { "TMDS_CTL0_DATA_SEL", 0, 3, &umr_bitfield_default }, + { "TMDS_CTL0_DATA_DELAY", 4, 6, &umr_bitfield_default }, + { "TMDS_CTL0_DATA_INVERT", 7, 7, &umr_bitfield_default }, + { "TMDS_CTL0_DATA_MODULATION", 8, 9, &umr_bitfield_default }, + { "TMDS_CTL0_USE_FEEDBACK_PATH", 10, 10, &umr_bitfield_default }, + { "TMDS_CTL0_FB_SYNC_CONT", 11, 11, &umr_bitfield_default }, + { "TMDS_CTL0_PATTERN_OUT_EN", 12, 12, &umr_bitfield_default }, + { "TMDS_CTL1_DATA_SEL", 16, 19, &umr_bitfield_default }, + { "TMDS_CTL1_DATA_DELAY", 20, 22, &umr_bitfield_default }, + { "TMDS_CTL1_DATA_INVERT", 23, 23, &umr_bitfield_default }, + { "TMDS_CTL1_DATA_MODULATION", 24, 25, &umr_bitfield_default }, + { "TMDS_CTL1_USE_FEEDBACK_PATH", 26, 26, &umr_bitfield_default }, + { "TMDS_CTL1_FB_SYNC_CONT", 27, 27, &umr_bitfield_default }, + { "TMDS_CTL1_PATTERN_OUT_EN", 28, 28, &umr_bitfield_default }, + { "TMDS_2BIT_COUNTER_EN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_TMDS_CTL2_3_GEN_CNTL[] = { + { "TMDS_CTL2_DATA_SEL", 0, 3, &umr_bitfield_default }, + { "TMDS_CTL2_DATA_DELAY", 4, 6, &umr_bitfield_default }, + { "TMDS_CTL2_DATA_INVERT", 7, 7, &umr_bitfield_default }, + { "TMDS_CTL2_DATA_MODULATION", 8, 9, &umr_bitfield_default }, + { "TMDS_CTL2_USE_FEEDBACK_PATH", 10, 10, &umr_bitfield_default }, + { "TMDS_CTL2_FB_SYNC_CONT", 11, 11, &umr_bitfield_default }, + { "TMDS_CTL2_PATTERN_OUT_EN", 12, 12, &umr_bitfield_default }, + { "TMDS_CTL3_DATA_SEL", 16, 19, &umr_bitfield_default }, + { "TMDS_CTL3_DATA_DELAY", 20, 22, &umr_bitfield_default }, + { "TMDS_CTL3_DATA_INVERT", 23, 23, &umr_bitfield_default }, + { "TMDS_CTL3_DATA_MODULATION", 24, 25, &umr_bitfield_default }, + { "TMDS_CTL3_USE_FEEDBACK_PATH", 26, 26, &umr_bitfield_default }, + { "TMDS_CTL3_FB_SYNC_CONT", 27, 27, &umr_bitfield_default }, + { "TMDS_CTL3_PATTERN_OUT_EN", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_DIG_VERSION[] = { + { "DIG_TYPE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_DIG_LANE_ENABLE[] = { + { "DIG_LANE0EN", 0, 0, &umr_bitfield_default }, + { "DIG_LANE1EN", 1, 1, &umr_bitfield_default }, + { "DIG_LANE2EN", 2, 2, &umr_bitfield_default }, + { "DIG_LANE3EN", 3, 3, &umr_bitfield_default }, + { "DIG_CLK_EN", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_AFMT_CNTL[] = { + { "AFMT_AUDIO_CLOCK_EN", 0, 0, &umr_bitfield_default }, + { "AFMT_AUDIO_CLOCK_ON", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG2_AFMT_VBI_PACKET_CONTROL1[] = { + { "AFMT_GENERIC0_FRAME_UPDATE", 0, 0, &umr_bitfield_default }, + { "AFMT_GENERIC0_FRAME_UPDATE_PENDING", 1, 1, &umr_bitfield_default }, + { "AFMT_GENERIC0_IMMEDIATE_UPDATE", 2, 2, &umr_bitfield_default }, + { "AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING", 3, 3, &umr_bitfield_default }, + { "AFMT_GENERIC1_FRAME_UPDATE", 4, 4, &umr_bitfield_default }, + { "AFMT_GENERIC1_FRAME_UPDATE_PENDING", 5, 5, &umr_bitfield_default }, + { "AFMT_GENERIC1_IMMEDIATE_UPDATE", 6, 6, &umr_bitfield_default }, + { "AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING", 7, 7, &umr_bitfield_default }, + { "AFMT_GENERIC2_FRAME_UPDATE", 8, 8, &umr_bitfield_default }, + { "AFMT_GENERIC2_FRAME_UPDATE_PENDING", 9, 9, &umr_bitfield_default }, + { "AFMT_GENERIC2_IMMEDIATE_UPDATE", 10, 10, &umr_bitfield_default }, + { "AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING", 11, 11, &umr_bitfield_default }, + { "AFMT_GENERIC3_FRAME_UPDATE", 12, 12, &umr_bitfield_default }, + { "AFMT_GENERIC3_FRAME_UPDATE_PENDING", 13, 13, &umr_bitfield_default }, + { "AFMT_GENERIC3_IMMEDIATE_UPDATE", 14, 14, &umr_bitfield_default }, + { "AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING", 15, 15, &umr_bitfield_default }, + { "AFMT_GENERIC4_FRAME_UPDATE", 16, 16, &umr_bitfield_default }, + { "AFMT_GENERIC4_FRAME_UPDATE_PENDING", 17, 17, &umr_bitfield_default }, + { "AFMT_GENERIC4_IMMEDIATE_UPDATE", 18, 18, &umr_bitfield_default }, + { "AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING", 19, 19, &umr_bitfield_default }, + { "AFMT_GENERIC5_FRAME_UPDATE", 20, 20, &umr_bitfield_default }, + { "AFMT_GENERIC5_FRAME_UPDATE_PENDING", 21, 21, &umr_bitfield_default }, + { "AFMT_GENERIC5_IMMEDIATE_UPDATE", 22, 22, &umr_bitfield_default }, + { "AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING", 23, 23, &umr_bitfield_default }, + { "AFMT_GENERIC6_FRAME_UPDATE", 24, 24, &umr_bitfield_default }, + { "AFMT_GENERIC6_FRAME_UPDATE_PENDING", 25, 25, &umr_bitfield_default }, + { "AFMT_GENERIC6_IMMEDIATE_UPDATE", 26, 26, &umr_bitfield_default }, + { "AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING", 27, 27, &umr_bitfield_default }, + { "AFMT_GENERIC7_FRAME_UPDATE", 28, 28, &umr_bitfield_default }, + { "AFMT_GENERIC7_FRAME_UPDATE_PENDING", 29, 29, &umr_bitfield_default }, + { "AFMT_GENERIC7_IMMEDIATE_UPDATE", 30, 30, &umr_bitfield_default }, + { "AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_LINK_CNTL[] = { + { "DP_LINK_TRAINING_COMPLETE", 4, 4, &umr_bitfield_default }, + { "DP_LINK_STATUS", 8, 8, &umr_bitfield_default }, + { "DP_EMBEDDED_PANEL_MODE", 17, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_PIXEL_FORMAT[] = { + { "DP_PIXEL_ENCODING", 0, 2, &umr_bitfield_default }, + { "DP_COMPONENT_DEPTH", 24, 26, &umr_bitfield_default }, + { "DP_PIXEL_COMBINE", 28, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_MSA_COLORIMETRY[] = { + { "DP_MSA_MISC0", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_CONFIG[] = { + { "DP_UDI_LANES", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_VID_STREAM_CNTL[] = { + { "DP_VID_STREAM_ENABLE", 0, 0, &umr_bitfield_default }, + { "DP_VID_STREAM_DIS_DEFER", 8, 9, &umr_bitfield_default }, + { "DP_VID_STREAM_STATUS", 16, 16, &umr_bitfield_default }, + { "DP_VID_STREAM_CHANGE_KEEPOUT", 20, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_STEER_FIFO[] = { + { "DP_STEER_FIFO_RESET", 0, 0, &umr_bitfield_default }, + { "DP_STEER_OVERFLOW_FLAG", 4, 4, &umr_bitfield_default }, + { "DP_STEER_OVERFLOW_INT", 5, 5, &umr_bitfield_default }, + { "DP_STEER_OVERFLOW_ACK", 6, 6, &umr_bitfield_default }, + { "DP_STEER_OVERFLOW_MASK", 7, 7, &umr_bitfield_default }, + { "DP_TU_OVERFLOW_FLAG", 8, 8, &umr_bitfield_default }, + { "DP_TU_OVERFLOW_ACK", 12, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_MSA_MISC[] = { + { "DP_MSA_MISC1", 0, 7, &umr_bitfield_default }, + { "DP_MSA_MISC2", 8, 15, &umr_bitfield_default }, + { "DP_MSA_MISC3", 16, 23, &umr_bitfield_default }, + { "DP_MSA_MISC4", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_VID_TIMING[] = { + { "DP_VID_M_N_DOUBLE_BUFFER_MODE", 4, 4, &umr_bitfield_default }, + { "DP_VID_M_N_GEN_EN", 8, 8, &umr_bitfield_default }, + { "DP_VID_N_MUL", 10, 11, &umr_bitfield_default }, + { "DP_VID_M_DIV", 12, 13, &umr_bitfield_default }, + { "DP_VID_N_DIV", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_VID_N[] = { + { "DP_VID_N", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_VID_M[] = { + { "DP_VID_M", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_LINK_FRAMING_CNTL[] = { + { "DP_IDLE_BS_INTERVAL", 0, 17, &umr_bitfield_default }, + { "DP_VBID_DISABLE", 24, 24, &umr_bitfield_default }, + { "DP_VID_ENHANCED_FRAME_MODE", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_HBR2_EYE_PATTERN[] = { + { "DP_HBR2_EYE_PATTERN_ENABLE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_VID_MSA_VBID[] = { + { "DP_VID_MSA_LOCATION", 0, 11, &umr_bitfield_default }, + { "DP_VID_VBID_FIELD_POL", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_VID_INTERRUPT_CNTL[] = { + { "DP_VID_STREAM_DISABLE_INT", 0, 0, &umr_bitfield_default }, + { "DP_VID_STREAM_DISABLE_ACK", 1, 1, &umr_bitfield_default }, + { "DP_VID_STREAM_DISABLE_MASK", 2, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_DPHY_CNTL[] = { + { "DPHY_ATEST_SEL_LANE0", 0, 0, &umr_bitfield_default }, + { "DPHY_ATEST_SEL_LANE1", 1, 1, &umr_bitfield_default }, + { "DPHY_ATEST_SEL_LANE2", 2, 2, &umr_bitfield_default }, + { "DPHY_ATEST_SEL_LANE3", 3, 3, &umr_bitfield_default }, + { "DPHY_BYPASS", 16, 16, &umr_bitfield_default }, + { "DPHY_SKEW_BYPASS", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_DPHY_TRAINING_PATTERN_SEL[] = { + { "DPHY_TRAINING_PATTERN_SEL", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_DPHY_SYM0[] = { + { "DPHY_SYM1", 0, 9, &umr_bitfield_default }, + { "DPHY_SYM2", 10, 19, &umr_bitfield_default }, + { "DPHY_SYM3", 20, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_DPHY_SYM1[] = { + { "DPHY_SYM4", 0, 9, &umr_bitfield_default }, + { "DPHY_SYM5", 10, 19, &umr_bitfield_default }, + { "DPHY_SYM6", 20, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_DPHY_SYM2[] = { + { "DPHY_SYM7", 0, 9, &umr_bitfield_default }, + { "DPHY_SYM8", 10, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_DPHY_8B10B_CNTL[] = { + { "DPHY_8B10B_RESET", 8, 8, &umr_bitfield_default }, + { "DPHY_8B10B_EXT_DISP", 16, 16, &umr_bitfield_default }, + { "DPHY_8B10B_CUR_DISP", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_DPHY_PRBS_CNTL[] = { + { "DPHY_PRBS_EN", 0, 0, &umr_bitfield_default }, + { "DPHY_PRBS_SEL", 4, 5, &umr_bitfield_default }, + { "DPHY_PRBS_SEED", 8, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_DPHY_SCRAM_CNTL[] = { + { "DPHY_SCRAMBLER_DIS", 0, 0, &umr_bitfield_default }, + { "DPHY_SCRAMBLER_ADVANCE", 4, 4, &umr_bitfield_default }, + { "DPHY_SCRAMBLER_BS_COUNT", 8, 17, &umr_bitfield_default }, + { "DPHY_SCRAMBLER_KCODE", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_DPHY_CRC_EN[] = { + { "DPHY_CRC_EN", 0, 0, &umr_bitfield_default }, + { "DPHY_CRC_CONT_EN", 4, 4, &umr_bitfield_default }, + { "DPHY_CRC_RESULT_VALID", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_DPHY_CRC_CNTL[] = { + { "DPHY_CRC_FIELD", 0, 0, &umr_bitfield_default }, + { "DPHY_CRC_SEL", 4, 5, &umr_bitfield_default }, + { "DPHY_CRC_MASK", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_DPHY_CRC_RESULT[] = { + { "DPHY_CRC_RESULT", 0, 7, &umr_bitfield_default }, + { "DPHY_CRC_RESULT1", 8, 15, &umr_bitfield_default }, + { "DPHY_CRC_RESULT2", 16, 23, &umr_bitfield_default }, + { "DPHY_CRC_RESULT3", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_DPHY_CRC_MST_CNTL[] = { + { "DPHY_CRC_MST_FIRST_SLOT", 0, 5, &umr_bitfield_default }, + { "DPHY_CRC_MST_LAST_SLOT", 8, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_DPHY_CRC_MST_STATUS[] = { + { "DPHY_CRC_MST_PHASE_LOCK", 0, 0, &umr_bitfield_default }, + { "DPHY_CRC_MST_PHASE_ERROR", 8, 8, &umr_bitfield_default }, + { "DPHY_CRC_MST_PHASE_ERROR_ACK", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_DPHY_FAST_TRAINING[] = { + { "DPHY_RX_FAST_TRAINING_CAPABLE", 0, 0, &umr_bitfield_default }, + { "DPHY_SW_FAST_TRAINING_START", 1, 1, &umr_bitfield_default }, + { "DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN", 2, 2, &umr_bitfield_default }, + { "DPHY_FAST_TRAINING_TP1_TIME", 8, 19, &umr_bitfield_default }, + { "DPHY_FAST_TRAINING_TP2_TIME", 20, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_DPHY_FAST_TRAINING_STATUS[] = { + { "DPHY_FAST_TRAINING_STATE", 0, 2, &umr_bitfield_default }, + { "DPHY_FAST_TRAINING_COMPLETE_OCCURRED", 4, 4, &umr_bitfield_default }, + { "DPHY_FAST_TRAINING_COMPLETE_MASK", 8, 8, &umr_bitfield_default }, + { "DPHY_FAST_TRAINING_COMPLETE_ACK", 12, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_SEC_CNTL[] = { + { "DP_SEC_STREAM_ENABLE", 0, 0, &umr_bitfield_default }, + { "DP_SEC_ASP_ENABLE", 4, 4, &umr_bitfield_default }, + { "DP_SEC_ATP_ENABLE", 8, 8, &umr_bitfield_default }, + { "DP_SEC_AIP_ENABLE", 12, 12, &umr_bitfield_default }, + { "DP_SEC_ACM_ENABLE", 16, 16, &umr_bitfield_default }, + { "DP_SEC_GSP0_ENABLE", 20, 20, &umr_bitfield_default }, + { "DP_SEC_GSP1_ENABLE", 21, 21, &umr_bitfield_default }, + { "DP_SEC_GSP2_ENABLE", 22, 22, &umr_bitfield_default }, + { "DP_SEC_GSP3_ENABLE", 23, 23, &umr_bitfield_default }, + { "DP_SEC_GSP4_ENABLE", 24, 24, &umr_bitfield_default }, + { "DP_SEC_GSP5_ENABLE", 25, 25, &umr_bitfield_default }, + { "DP_SEC_GSP6_ENABLE", 26, 26, &umr_bitfield_default }, + { "DP_SEC_GSP7_ENABLE", 27, 27, &umr_bitfield_default }, + { "DP_SEC_MPG_ENABLE", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_SEC_CNTL1[] = { + { "DP_SEC_ISRC_ENABLE", 0, 0, &umr_bitfield_default }, + { "DP_SEC_GSP0_PRIORITY", 4, 4, &umr_bitfield_default }, + { "DP_SEC_GSP0_SEND", 5, 5, &umr_bitfield_default }, + { "DP_SEC_GSP0_SEND_PENDING", 6, 6, &umr_bitfield_default }, + { "DP_SEC_GSP0_SEND_DEADLINE_MISSED", 7, 7, &umr_bitfield_default }, + { "DP_SEC_GSP0_SEND_ANY_LINE", 8, 8, &umr_bitfield_default }, + { "DP_SEC_GSP0_LINE_NUM", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_SEC_FRAMING1[] = { + { "DP_SEC_FRAME_START_LOCATION", 0, 11, &umr_bitfield_default }, + { "DP_SEC_VBLANK_TRANSMIT_WIDTH", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_SEC_FRAMING2[] = { + { "DP_SEC_START_POSITION", 0, 15, &umr_bitfield_default }, + { "DP_SEC_HBLANK_TRANSMIT_WIDTH", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_SEC_FRAMING3[] = { + { "DP_SEC_IDLE_FRAME_SIZE", 0, 13, &umr_bitfield_default }, + { "DP_SEC_IDLE_TRANSMIT_WIDTH", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_SEC_FRAMING4[] = { + { "DP_SEC_COLLISION_STATUS", 20, 20, &umr_bitfield_default }, + { "DP_SEC_COLLISION_ACK", 24, 24, &umr_bitfield_default }, + { "DP_SEC_AUDIO_MUTE", 28, 28, &umr_bitfield_default }, + { "DP_SEC_AUDIO_MUTE_STATUS", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_SEC_AUD_N[] = { + { "DP_SEC_AUD_N", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_SEC_AUD_N_READBACK[] = { + { "DP_SEC_AUD_N_READBACK", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_SEC_AUD_M[] = { + { "DP_SEC_AUD_M", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_SEC_AUD_M_READBACK[] = { + { "DP_SEC_AUD_M_READBACK", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_SEC_TIMESTAMP[] = { + { "DP_SEC_TIMESTAMP_MODE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_SEC_PACKET_CNTL[] = { + { "DP_SEC_ASP_CODING_TYPE", 1, 3, &umr_bitfield_default }, + { "DP_SEC_ASP_PRIORITY", 4, 4, &umr_bitfield_default }, + { "DP_SEC_VERSION", 8, 13, &umr_bitfield_default }, + { "DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_MSE_RATE_CNTL[] = { + { "DP_MSE_RATE_Y", 0, 25, &umr_bitfield_default }, + { "DP_MSE_RATE_X", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_MSE_RATE_UPDATE[] = { + { "DP_MSE_RATE_UPDATE_PENDING", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_MSE_SAT0[] = { + { "DP_MSE_SAT_SRC0", 0, 2, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT0", 8, 13, &umr_bitfield_default }, + { "DP_MSE_SAT_SRC1", 16, 18, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT1", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_MSE_SAT1[] = { + { "DP_MSE_SAT_SRC2", 0, 2, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT2", 8, 13, &umr_bitfield_default }, + { "DP_MSE_SAT_SRC3", 16, 18, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT3", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_MSE_SAT2[] = { + { "DP_MSE_SAT_SRC4", 0, 2, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT4", 8, 13, &umr_bitfield_default }, + { "DP_MSE_SAT_SRC5", 16, 18, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT5", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_MSE_SAT_UPDATE[] = { + { "DP_MSE_SAT_UPDATE", 0, 1, &umr_bitfield_default }, + { "DP_MSE_16_MTP_KEEPOUT", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_MSE_LINK_TIMING[] = { + { "DP_MSE_LINK_FRAME", 0, 9, &umr_bitfield_default }, + { "DP_MSE_LINK_LINE", 16, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_MSE_MISC_CNTL[] = { + { "DP_MSE_BLANK_CODE", 0, 0, &umr_bitfield_default }, + { "DP_MSE_TIMESTAMP_MODE", 4, 4, &umr_bitfield_default }, + { "DP_MSE_ZERO_ENCODER", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_DPHY_BS_SR_SWAP_CNTL[] = { + { "DPHY_LOAD_BS_COUNT", 0, 9, &umr_bitfield_default }, + { "DPHY_BS_SR_SWAP_DONE", 15, 15, &umr_bitfield_default }, + { "DPHY_LOAD_BS_COUNT_START", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL[] = { + { "DP_DPHY_HBR2_PATTERN_CONTROL", 0, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_MSE_SAT0_STATUS[] = { + { "DP_MSE_SAT_SRC0_STATUS", 0, 2, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT0_STATUS", 8, 13, &umr_bitfield_default }, + { "DP_MSE_SAT_SRC1_STATUS", 16, 18, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT1_STATUS", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_MSE_SAT1_STATUS[] = { + { "DP_MSE_SAT_SRC2_STATUS", 0, 2, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT2_STATUS", 8, 13, &umr_bitfield_default }, + { "DP_MSE_SAT_SRC3_STATUS", 16, 18, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT3_STATUS", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_MSE_SAT2_STATUS[] = { + { "DP_MSE_SAT_SRC4_STATUS", 0, 2, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT4_STATUS", 8, 13, &umr_bitfield_default }, + { "DP_MSE_SAT_SRC5_STATUS", 16, 18, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT5_STATUS", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_MSA_TIMING_PARAM1[] = { + { "DP_MSA_VTOTAL", 0, 15, &umr_bitfield_default }, + { "DP_MSA_HTOTAL", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_MSA_TIMING_PARAM2[] = { + { "DP_MSA_VSTART", 0, 15, &umr_bitfield_default }, + { "DP_MSA_HSTART", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_MSA_TIMING_PARAM3[] = { + { "DP_MSA_VSYNCWIDTH", 0, 14, &umr_bitfield_default }, + { "DP_MSA_VSYNCPOLARITY", 15, 15, &umr_bitfield_default }, + { "DP_MSA_HSYNCWIDTH", 16, 30, &umr_bitfield_default }, + { "DP_MSA_HSYNCPOLARITY", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_MSA_TIMING_PARAM4[] = { + { "DP_MSA_VHEIGHT", 0, 15, &umr_bitfield_default }, + { "DP_MSA_HWIDTH", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_MSO_CNTL[] = { + { "DP_MSO_NUM_OF_SSTLINK", 0, 1, &umr_bitfield_default }, + { "DP_MSO_SEC_STREAM_ENABLE", 4, 7, &umr_bitfield_default }, + { "DP_MSO_SEC_ASP_ENABLE", 8, 11, &umr_bitfield_default }, + { "DP_MSO_SEC_ATP_ENABLE", 12, 15, &umr_bitfield_default }, + { "DP_MSO_SEC_AIP_ENABLE", 16, 19, &umr_bitfield_default }, + { "DP_MSO_SEC_ACM_ENABLE", 20, 23, &umr_bitfield_default }, + { "DP_MSO_SEC_GSP0_ENABLE", 24, 27, &umr_bitfield_default }, + { "DP_MSO_SEC_GSP1_ENABLE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_MSO_CNTL1[] = { + { "DP_MSO_SEC_GSP2_ENABLE", 0, 3, &umr_bitfield_default }, + { "DP_MSO_SEC_GSP3_ENABLE", 4, 7, &umr_bitfield_default }, + { "DP_MSO_SEC_GSP4_ENABLE", 8, 11, &umr_bitfield_default }, + { "DP_MSO_SEC_GSP5_ENABLE", 12, 15, &umr_bitfield_default }, + { "DP_MSO_SEC_GSP6_ENABLE", 16, 19, &umr_bitfield_default }, + { "DP_MSO_SEC_GSP7_ENABLE", 20, 23, &umr_bitfield_default }, + { "DP_MSO_SEC_MPG_ENABLE", 24, 27, &umr_bitfield_default }, + { "DP_MSO_SEC_ISRC_ENABLE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_DSC_CNTL[] = { + { "DP_DSC_EN", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_SEC_CNTL2[] = { + { "DP_SEC_GSP1_SEND", 0, 0, &umr_bitfield_default }, + { "DP_SEC_GSP1_SEND_PENDING", 1, 1, &umr_bitfield_default }, + { "DP_SEC_GSP1_SEND_DEADLINE_MISSED", 2, 2, &umr_bitfield_default }, + { "DP_SEC_GSP1_SEND_ANY_LINE", 3, 3, &umr_bitfield_default }, + { "DP_SEC_GSP2_SEND", 4, 4, &umr_bitfield_default }, + { "DP_SEC_GSP2_SEND_PENDING", 5, 5, &umr_bitfield_default }, + { "DP_SEC_GSP2_SEND_DEADLINE_MISSED", 6, 6, &umr_bitfield_default }, + { "DP_SEC_GSP2_SEND_ANY_LINE", 7, 7, &umr_bitfield_default }, + { "DP_SEC_GSP3_SEND", 8, 8, &umr_bitfield_default }, + { "DP_SEC_GSP3_SEND_PENDING", 9, 9, &umr_bitfield_default }, + { "DP_SEC_GSP3_SEND_DEADLINE_MISSED", 10, 10, &umr_bitfield_default }, + { "DP_SEC_GSP3_SEND_ANY_LINE", 11, 11, &umr_bitfield_default }, + { "DP_SEC_GSP4_SEND", 12, 12, &umr_bitfield_default }, + { "DP_SEC_GSP4_SEND_PENDING", 13, 13, &umr_bitfield_default }, + { "DP_SEC_GSP4_SEND_DEADLINE_MISSED", 14, 14, &umr_bitfield_default }, + { "DP_SEC_GSP4_SEND_ANY_LINE", 15, 15, &umr_bitfield_default }, + { "DP_SEC_GSP5_SEND", 16, 16, &umr_bitfield_default }, + { "DP_SEC_GSP5_SEND_PENDING", 17, 17, &umr_bitfield_default }, + { "DP_SEC_GSP5_SEND_DEADLINE_MISSED", 18, 18, &umr_bitfield_default }, + { "DP_SEC_GSP5_SEND_ANY_LINE", 19, 19, &umr_bitfield_default }, + { "DP_SEC_GSP6_SEND", 20, 20, &umr_bitfield_default }, + { "DP_SEC_GSP6_SEND_PENDING", 21, 21, &umr_bitfield_default }, + { "DP_SEC_GSP6_SEND_DEADLINE_MISSED", 22, 22, &umr_bitfield_default }, + { "DP_SEC_GSP6_SEND_ANY_LINE", 23, 23, &umr_bitfield_default }, + { "DP_SEC_GSP7_SEND", 24, 24, &umr_bitfield_default }, + { "DP_SEC_GSP7_SEND_PENDING", 25, 25, &umr_bitfield_default }, + { "DP_SEC_GSP7_SEND_DEADLINE_MISSED", 26, 26, &umr_bitfield_default }, + { "DP_SEC_GSP7_SEND_ANY_LINE", 27, 27, &umr_bitfield_default }, + { "DP_SEC_GSP7_PPS", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_SEC_CNTL3[] = { + { "DP_SEC_GSP1_LINE_NUM", 0, 15, &umr_bitfield_default }, + { "DP_SEC_GSP2_LINE_NUM", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_SEC_CNTL4[] = { + { "DP_SEC_GSP3_LINE_NUM", 0, 15, &umr_bitfield_default }, + { "DP_SEC_GSP4_LINE_NUM", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_SEC_CNTL5[] = { + { "DP_SEC_GSP5_LINE_NUM", 0, 15, &umr_bitfield_default }, + { "DP_SEC_GSP6_LINE_NUM", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_SEC_CNTL6[] = { + { "DP_SEC_GSP7_LINE_NUM", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_SEC_CNTL7[] = { + { "DP_SEC_GSP0_SEND_ACTIVE", 0, 0, &umr_bitfield_default }, + { "DP_SEC_GSP1_SEND_ACTIVE", 4, 4, &umr_bitfield_default }, + { "DP_SEC_GSP2_SEND_ACTIVE", 8, 8, &umr_bitfield_default }, + { "DP_SEC_GSP3_SEND_ACTIVE", 12, 12, &umr_bitfield_default }, + { "DP_SEC_GSP4_SEND_ACTIVE", 16, 16, &umr_bitfield_default }, + { "DP_SEC_GSP5_SEND_ACTIVE", 20, 20, &umr_bitfield_default }, + { "DP_SEC_GSP6_SEND_ACTIVE", 24, 24, &umr_bitfield_default }, + { "DP_SEC_GSP7_SEND_ACTIVE", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_DB_CNTL[] = { + { "DP_DB_PENDING", 0, 0, &umr_bitfield_default }, + { "DP_DB_TAKEN", 4, 4, &umr_bitfield_default }, + { "DP_DB_TAKEN_CLR", 5, 5, &umr_bitfield_default }, + { "DP_DB_LOCK", 8, 8, &umr_bitfield_default }, + { "DP_DB_DISABLE", 12, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP2_DP_MSA_VBID_MISC[] = { + { "DP_MSA_MISC1_STEREOSYNC_OVERRIDE", 0, 1, &umr_bitfield_default }, + { "DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN", 4, 4, &umr_bitfield_default }, + { "DP_VBID1_OVERRIDE", 8, 8, &umr_bitfield_default }, + { "DP_VBID2_OVERRIDE", 9, 9, &umr_bitfield_default }, + { "DP_VBID1_OVERRIDE_EN", 12, 12, &umr_bitfield_default }, + { "DP_VBID2_OVERRIDE_EN", 13, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_DIG_FE_CNTL[] = { + { "DIG_SOURCE_SELECT", 0, 2, &umr_bitfield_default }, + { "DIG_STEREOSYNC_SELECT", 4, 6, &umr_bitfield_default }, + { "DIG_STEREOSYNC_GATE_EN", 8, 8, &umr_bitfield_default }, + { "DIG_START", 10, 10, &umr_bitfield_default }, + { "DIG_DIGITAL_BYPASS_SELECT", 12, 14, &umr_bitfield_default }, + { "DIG_SYMCLK_FE_ON", 24, 24, &umr_bitfield_default }, + { "TMDS_PIXEL_ENCODING", 28, 28, &umr_bitfield_default }, + { "TMDS_COLOR_FORMAT", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_DIG_OUTPUT_CRC_CNTL[] = { + { "DIG_OUTPUT_CRC_EN", 0, 0, &umr_bitfield_default }, + { "DIG_OUTPUT_CRC_LINK_SEL", 4, 4, &umr_bitfield_default }, + { "DIG_OUTPUT_CRC_DATA_SEL", 8, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_DIG_OUTPUT_CRC_RESULT[] = { + { "DIG_OUTPUT_CRC_RESULT", 0, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_DIG_CLOCK_PATTERN[] = { + { "DIG_CLOCK_PATTERN", 0, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_DIG_TEST_PATTERN[] = { + { "DIG_TEST_PATTERN_OUT_EN", 0, 0, &umr_bitfield_default }, + { "DIG_HALF_CLOCK_PATTERN_SEL", 1, 1, &umr_bitfield_default }, + { "DIG_RANDOM_PATTERN_OUT_EN", 4, 4, &umr_bitfield_default }, + { "DIG_RANDOM_PATTERN_RESET", 5, 5, &umr_bitfield_default }, + { "DIG_TEST_PATTERN_EXTERNAL_RESET_EN", 6, 6, &umr_bitfield_default }, + { "DIG_STATIC_TEST_PATTERN", 16, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_DIG_RANDOM_PATTERN_SEED[] = { + { "DIG_RANDOM_PATTERN_SEED", 0, 23, &umr_bitfield_default }, + { "DIG_RAN_PAT_DURING_DE_ONLY", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_DIG_FIFO_STATUS[] = { + { "DIG_FIFO_LEVEL_ERROR", 0, 0, &umr_bitfield_default }, + { "DIG_FIFO_USE_OVERWRITE_LEVEL", 1, 1, &umr_bitfield_default }, + { "DIG_FIFO_OVERWRITE_LEVEL", 2, 7, &umr_bitfield_default }, + { "DIG_FIFO_ERROR_ACK", 8, 8, &umr_bitfield_default }, + { "DIG_FIFO_CAL_AVERAGE_LEVEL", 10, 15, &umr_bitfield_default }, + { "DIG_FIFO_MAXIMUM_LEVEL", 16, 20, &umr_bitfield_default }, + { "DIG_FIFO_MINIMUM_LEVEL", 22, 25, &umr_bitfield_default }, + { "DIG_FIFO_READ_CLOCK_SRC", 26, 26, &umr_bitfield_default }, + { "DIG_FIFO_CALIBRATED", 29, 29, &umr_bitfield_default }, + { "DIG_FIFO_FORCE_RECAL_AVERAGE", 30, 30, &umr_bitfield_default }, + { "DIG_FIFO_FORCE_RECOMP_MINMAX", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_HDMI_CONTROL[] = { + { "HDMI_KEEPOUT_MODE", 0, 0, &umr_bitfield_default }, + { "HDMI_DATA_SCRAMBLE_EN", 1, 1, &umr_bitfield_default }, + { "HDMI_CLOCK_CHANNEL_RATE", 2, 2, &umr_bitfield_default }, + { "HDMI_NO_EXTRA_NULL_PACKET_FILLED", 3, 3, &umr_bitfield_default }, + { "HDMI_PACKET_GEN_VERSION", 4, 4, &umr_bitfield_default }, + { "HDMI_ERROR_ACK", 8, 8, &umr_bitfield_default }, + { "HDMI_ERROR_MASK", 9, 9, &umr_bitfield_default }, + { "HDMI_DEEP_COLOR_ENABLE", 24, 24, &umr_bitfield_default }, + { "HDMI_DEEP_COLOR_DEPTH", 28, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_HDMI_STATUS[] = { + { "HDMI_ACTIVE_AVMUTE", 0, 0, &umr_bitfield_default }, + { "HDMI_AUDIO_PACKET_ERROR", 16, 16, &umr_bitfield_default }, + { "HDMI_VBI_PACKET_ERROR", 20, 20, &umr_bitfield_default }, + { "HDMI_ERROR_INT", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_HDMI_AUDIO_PACKET_CONTROL[] = { + { "HDMI_AUDIO_DELAY_EN", 4, 5, &umr_bitfield_default }, + { "HDMI_AUDIO_PACKETS_PER_LINE", 16, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_HDMI_ACR_PACKET_CONTROL[] = { + { "HDMI_ACR_SEND", 0, 0, &umr_bitfield_default }, + { "HDMI_ACR_CONT", 1, 1, &umr_bitfield_default }, + { "HDMI_ACR_SELECT", 4, 5, &umr_bitfield_default }, + { "HDMI_ACR_SOURCE", 8, 8, &umr_bitfield_default }, + { "HDMI_ACR_AUTO_SEND", 12, 12, &umr_bitfield_default }, + { "HDMI_ACR_N_MULTIPLE", 16, 18, &umr_bitfield_default }, + { "HDMI_ACR_AUDIO_PRIORITY", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_HDMI_VBI_PACKET_CONTROL[] = { + { "HDMI_NULL_SEND", 0, 0, &umr_bitfield_default }, + { "HDMI_GC_SEND", 4, 4, &umr_bitfield_default }, + { "HDMI_GC_CONT", 5, 5, &umr_bitfield_default }, + { "HDMI_ISRC_SEND", 8, 8, &umr_bitfield_default }, + { "HDMI_ISRC_CONT", 9, 9, &umr_bitfield_default }, + { "HDMI_ISRC_LINE", 16, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_HDMI_INFOFRAME_CONTROL0[] = { + { "HDMI_AUDIO_INFO_SEND", 4, 4, &umr_bitfield_default }, + { "HDMI_AUDIO_INFO_CONT", 5, 5, &umr_bitfield_default }, + { "HDMI_MPEG_INFO_SEND", 8, 8, &umr_bitfield_default }, + { "HDMI_MPEG_INFO_CONT", 9, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_HDMI_INFOFRAME_CONTROL1[] = { + { "HDMI_AUDIO_INFO_LINE", 8, 13, &umr_bitfield_default }, + { "HDMI_MPEG_INFO_LINE", 16, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_HDMI_GENERIC_PACKET_CONTROL0[] = { + { "HDMI_GENERIC0_SEND", 0, 0, &umr_bitfield_default }, + { "HDMI_GENERIC0_CONT", 1, 1, &umr_bitfield_default }, + { "HDMI_GENERIC1_SEND", 4, 4, &umr_bitfield_default }, + { "HDMI_GENERIC1_CONT", 5, 5, &umr_bitfield_default }, + { "HDMI_GENERIC0_LINE", 16, 21, &umr_bitfield_default }, + { "HDMI_GENERIC1_LINE", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_HDMI_GC[] = { + { "HDMI_GC_AVMUTE", 0, 0, &umr_bitfield_default }, + { "HDMI_GC_AVMUTE_CONT", 2, 2, &umr_bitfield_default }, + { "HDMI_DEFAULT_PHASE", 4, 4, &umr_bitfield_default }, + { "HDMI_PACKING_PHASE", 8, 11, &umr_bitfield_default }, + { "HDMI_PACKING_PHASE_OVERRIDE", 12, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_AFMT_AUDIO_PACKET_CONTROL2[] = { + { "AFMT_AUDIO_LAYOUT_OVRD", 0, 0, &umr_bitfield_default }, + { "AFMT_AUDIO_LAYOUT_SELECT", 1, 1, &umr_bitfield_default }, + { "AFMT_AUDIO_CHANNEL_ENABLE", 8, 15, &umr_bitfield_default }, + { "AFMT_DP_AUDIO_STREAM_ID", 16, 23, &umr_bitfield_default }, + { "AFMT_HBR_ENABLE_OVRD", 24, 24, &umr_bitfield_default }, + { "AFMT_60958_OSF_OVRD", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_AFMT_ISRC1_0[] = { + { "AFMT_ISRC_STATUS", 0, 2, &umr_bitfield_default }, + { "AFMT_ISRC_CONTINUE", 6, 6, &umr_bitfield_default }, + { "AFMT_ISRC_VALID", 7, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_AFMT_ISRC1_1[] = { + { "AFMT_UPC_EAN_ISRC0", 0, 7, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC1", 8, 15, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC2", 16, 23, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC3", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_AFMT_ISRC1_2[] = { + { "AFMT_UPC_EAN_ISRC4", 0, 7, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC5", 8, 15, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC6", 16, 23, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC7", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_AFMT_ISRC1_3[] = { + { "AFMT_UPC_EAN_ISRC8", 0, 7, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC9", 8, 15, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC10", 16, 23, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC11", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_AFMT_ISRC1_4[] = { + { "AFMT_UPC_EAN_ISRC12", 0, 7, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC13", 8, 15, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC14", 16, 23, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC15", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_AFMT_ISRC2_0[] = { + { "AFMT_UPC_EAN_ISRC16", 0, 7, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC17", 8, 15, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC18", 16, 23, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC19", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_AFMT_ISRC2_1[] = { + { "AFMT_UPC_EAN_ISRC20", 0, 7, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC21", 8, 15, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC22", 16, 23, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC23", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_AFMT_ISRC2_2[] = { + { "AFMT_UPC_EAN_ISRC24", 0, 7, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC25", 8, 15, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC26", 16, 23, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC27", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_AFMT_ISRC2_3[] = { + { "AFMT_UPC_EAN_ISRC28", 0, 7, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC29", 8, 15, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC30", 16, 23, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC31", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_HDMI_GENERIC_PACKET_CONTROL2[] = { + { "HDMI_GENERIC4_SEND", 0, 0, &umr_bitfield_default }, + { "HDMI_GENERIC4_CONT", 1, 1, &umr_bitfield_default }, + { "HDMI_GENERIC5_SEND", 4, 4, &umr_bitfield_default }, + { "HDMI_GENERIC5_CONT", 5, 5, &umr_bitfield_default }, + { "HDMI_GENERIC4_LINE", 16, 21, &umr_bitfield_default }, + { "HDMI_GENERIC5_LINE", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_HDMI_GENERIC_PACKET_CONTROL3[] = { + { "HDMI_GENERIC6_SEND", 0, 0, &umr_bitfield_default }, + { "HDMI_GENERIC6_CONT", 1, 1, &umr_bitfield_default }, + { "HDMI_GENERIC7_SEND", 4, 4, &umr_bitfield_default }, + { "HDMI_GENERIC7_CONT", 5, 5, &umr_bitfield_default }, + { "HDMI_GENERIC6_LINE", 16, 21, &umr_bitfield_default }, + { "HDMI_GENERIC7_LINE", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_HDMI_DB_CONTROL[] = { + { "HDMI_DB_PENDING", 0, 0, &umr_bitfield_default }, + { "HDMI_DB_TAKEN", 4, 4, &umr_bitfield_default }, + { "HDMI_DB_TAKEN_CLR", 5, 5, &umr_bitfield_default }, + { "HDMI_DB_LOCK", 8, 8, &umr_bitfield_default }, + { "HDMI_DB_DISABLE", 12, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_AFMT_MPEG_INFO0[] = { + { "AFMT_MPEG_INFO_CHECKSUM", 0, 7, &umr_bitfield_default }, + { "AFMT_MPEG_INFO_MB0", 8, 15, &umr_bitfield_default }, + { "AFMT_MPEG_INFO_MB1", 16, 23, &umr_bitfield_default }, + { "AFMT_MPEG_INFO_MB2", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_AFMT_MPEG_INFO1[] = { + { "AFMT_MPEG_INFO_MB3", 0, 7, &umr_bitfield_default }, + { "AFMT_MPEG_INFO_MF", 8, 9, &umr_bitfield_default }, + { "AFMT_MPEG_INFO_FR", 12, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_AFMT_GENERIC_HDR[] = { + { "AFMT_GENERIC_HB0", 0, 7, &umr_bitfield_default }, + { "AFMT_GENERIC_HB1", 8, 15, &umr_bitfield_default }, + { "AFMT_GENERIC_HB2", 16, 23, &umr_bitfield_default }, + { "AFMT_GENERIC_HB3", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_AFMT_GENERIC_0[] = { + { "AFMT_GENERIC_BYTE0", 0, 7, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE1", 8, 15, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE2", 16, 23, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE3", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_AFMT_GENERIC_1[] = { + { "AFMT_GENERIC_BYTE4", 0, 7, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE5", 8, 15, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE6", 16, 23, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE7", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_AFMT_GENERIC_2[] = { + { "AFMT_GENERIC_BYTE8", 0, 7, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE9", 8, 15, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE10", 16, 23, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE11", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_AFMT_GENERIC_3[] = { + { "AFMT_GENERIC_BYTE12", 0, 7, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE13", 8, 15, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE14", 16, 23, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE15", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_AFMT_GENERIC_4[] = { + { "AFMT_GENERIC_BYTE16", 0, 7, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE17", 8, 15, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE18", 16, 23, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE19", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_AFMT_GENERIC_5[] = { + { "AFMT_GENERIC_BYTE20", 0, 7, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE21", 8, 15, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE22", 16, 23, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE23", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_AFMT_GENERIC_6[] = { + { "AFMT_GENERIC_BYTE24", 0, 7, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE25", 8, 15, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE26", 16, 23, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE27", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_AFMT_GENERIC_7[] = { + { "AFMT_GENERIC_BYTE28", 0, 7, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE29", 8, 15, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE30", 16, 23, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE31", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_HDMI_GENERIC_PACKET_CONTROL1[] = { + { "HDMI_GENERIC2_SEND", 0, 0, &umr_bitfield_default }, + { "HDMI_GENERIC2_CONT", 1, 1, &umr_bitfield_default }, + { "HDMI_GENERIC3_SEND", 4, 4, &umr_bitfield_default }, + { "HDMI_GENERIC3_CONT", 5, 5, &umr_bitfield_default }, + { "HDMI_GENERIC2_LINE", 16, 21, &umr_bitfield_default }, + { "HDMI_GENERIC3_LINE", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_HDMI_ACR_32_0[] = { + { "HDMI_ACR_CTS_32", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_HDMI_ACR_32_1[] = { + { "HDMI_ACR_N_32", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_HDMI_ACR_44_0[] = { + { "HDMI_ACR_CTS_44", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_HDMI_ACR_44_1[] = { + { "HDMI_ACR_N_44", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_HDMI_ACR_48_0[] = { + { "HDMI_ACR_CTS_48", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_HDMI_ACR_48_1[] = { + { "HDMI_ACR_N_48", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_HDMI_ACR_STATUS_0[] = { + { "HDMI_ACR_CTS", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_HDMI_ACR_STATUS_1[] = { + { "HDMI_ACR_N", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_AFMT_AUDIO_INFO0[] = { + { "AFMT_AUDIO_INFO_CHECKSUM", 0, 7, &umr_bitfield_default }, + { "AFMT_AUDIO_INFO_CC", 8, 10, &umr_bitfield_default }, + { "AFMT_AUDIO_INFO_CT", 11, 14, &umr_bitfield_default }, + { "AFMT_AUDIO_INFO_CHECKSUM_OFFSET", 16, 23, &umr_bitfield_default }, + { "AFMT_AUDIO_INFO_CXT", 24, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_AFMT_AUDIO_INFO1[] = { + { "AFMT_AUDIO_INFO_CA", 0, 7, &umr_bitfield_default }, + { "AFMT_AUDIO_INFO_LSV", 11, 14, &umr_bitfield_default }, + { "AFMT_AUDIO_INFO_DM_INH", 15, 15, &umr_bitfield_default }, + { "AFMT_AUDIO_INFO_LFEPBL", 16, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_AFMT_60958_0[] = { + { "AFMT_60958_CS_A", 0, 0, &umr_bitfield_default }, + { "AFMT_60958_CS_B", 1, 1, &umr_bitfield_default }, + { "AFMT_60958_CS_C", 2, 2, &umr_bitfield_default }, + { "AFMT_60958_CS_D", 3, 5, &umr_bitfield_default }, + { "AFMT_60958_CS_MODE", 6, 7, &umr_bitfield_default }, + { "AFMT_60958_CS_CATEGORY_CODE", 8, 15, &umr_bitfield_default }, + { "AFMT_60958_CS_SOURCE_NUMBER", 16, 19, &umr_bitfield_default }, + { "AFMT_60958_CS_CHANNEL_NUMBER_L", 20, 23, &umr_bitfield_default }, + { "AFMT_60958_CS_SAMPLING_FREQUENCY", 24, 27, &umr_bitfield_default }, + { "AFMT_60958_CS_CLOCK_ACCURACY", 28, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_AFMT_60958_1[] = { + { "AFMT_60958_CS_WORD_LENGTH", 0, 3, &umr_bitfield_default }, + { "AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY", 4, 7, &umr_bitfield_default }, + { "AFMT_60958_VALID_L", 16, 16, &umr_bitfield_default }, + { "AFMT_60958_VALID_R", 18, 18, &umr_bitfield_default }, + { "AFMT_60958_CS_CHANNEL_NUMBER_R", 20, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_AFMT_AUDIO_CRC_CONTROL[] = { + { "AFMT_AUDIO_CRC_EN", 0, 0, &umr_bitfield_default }, + { "AFMT_AUDIO_CRC_CONT", 4, 4, &umr_bitfield_default }, + { "AFMT_AUDIO_CRC_SOURCE", 8, 8, &umr_bitfield_default }, + { "AFMT_AUDIO_CRC_CH_SEL", 12, 15, &umr_bitfield_default }, + { "AFMT_AUDIO_CRC_COUNT", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_AFMT_RAMP_CONTROL0[] = { + { "AFMT_RAMP_MAX_COUNT", 0, 23, &umr_bitfield_default }, + { "AFMT_RAMP_DATA_SIGN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_AFMT_RAMP_CONTROL1[] = { + { "AFMT_RAMP_MIN_COUNT", 0, 23, &umr_bitfield_default }, + { "AFMT_AUDIO_TEST_CH_DISABLE", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_AFMT_RAMP_CONTROL2[] = { + { "AFMT_RAMP_INC_COUNT", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_AFMT_RAMP_CONTROL3[] = { + { "AFMT_RAMP_DEC_COUNT", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_AFMT_60958_2[] = { + { "AFMT_60958_CS_CHANNEL_NUMBER_2", 0, 3, &umr_bitfield_default }, + { "AFMT_60958_CS_CHANNEL_NUMBER_3", 4, 7, &umr_bitfield_default }, + { "AFMT_60958_CS_CHANNEL_NUMBER_4", 8, 11, &umr_bitfield_default }, + { "AFMT_60958_CS_CHANNEL_NUMBER_5", 12, 15, &umr_bitfield_default }, + { "AFMT_60958_CS_CHANNEL_NUMBER_6", 16, 19, &umr_bitfield_default }, + { "AFMT_60958_CS_CHANNEL_NUMBER_7", 20, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_AFMT_AUDIO_CRC_RESULT[] = { + { "AFMT_AUDIO_CRC_DONE", 0, 0, &umr_bitfield_default }, + { "AFMT_AUDIO_CRC", 8, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_AFMT_STATUS[] = { + { "AFMT_AUDIO_ENABLE", 4, 4, &umr_bitfield_default }, + { "AFMT_AZ_HBR_ENABLE", 8, 8, &umr_bitfield_default }, + { "AFMT_AUDIO_FIFO_OVERFLOW", 24, 24, &umr_bitfield_default }, + { "AFMT_AZ_AUDIO_ENABLE_CHG", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_AFMT_AUDIO_PACKET_CONTROL[] = { + { "AFMT_AUDIO_SAMPLE_SEND", 0, 0, &umr_bitfield_default }, + { "AFMT_RESET_FIFO_WHEN_AUDIO_DIS", 11, 11, &umr_bitfield_default }, + { "AFMT_AUDIO_TEST_EN", 12, 12, &umr_bitfield_default }, + { "AFMT_AUDIO_TEST_MODE", 14, 14, &umr_bitfield_default }, + { "AFMT_AUDIO_FIFO_OVERFLOW_ACK", 23, 23, &umr_bitfield_default }, + { "AFMT_AUDIO_CHANNEL_SWAP", 24, 24, &umr_bitfield_default }, + { "AFMT_60958_CS_UPDATE", 26, 26, &umr_bitfield_default }, + { "AFMT_AZ_AUDIO_ENABLE_CHG_ACK", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_AFMT_VBI_PACKET_CONTROL[] = { + { "AFMT_GENERIC_LOCK_STATUS", 8, 8, &umr_bitfield_default }, + { "AFMT_GENERIC_CONFLICT", 16, 16, &umr_bitfield_default }, + { "AFMT_GENERIC_CONFLICT_CLR", 17, 17, &umr_bitfield_default }, + { "AFMT_GENERIC_INDEX", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_AFMT_INFOFRAME_CONTROL0[] = { + { "AFMT_AUDIO_INFO_SOURCE", 6, 6, &umr_bitfield_default }, + { "AFMT_AUDIO_INFO_UPDATE", 7, 7, &umr_bitfield_default }, + { "AFMT_MPEG_INFO_UPDATE", 10, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_AFMT_AUDIO_SRC_CONTROL[] = { + { "AFMT_AUDIO_SRC_SELECT", 0, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_DIG_BE_CNTL[] = { + { "DIG_DUAL_LINK_ENABLE", 0, 0, &umr_bitfield_default }, + { "DIG_SWAP", 1, 1, &umr_bitfield_default }, + { "DIG_FE_SOURCE_SELECT", 8, 14, &umr_bitfield_default }, + { "DIG_MODE", 16, 18, &umr_bitfield_default }, + { "DIG_HPD_SELECT", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_DIG_BE_EN_CNTL[] = { + { "DIG_ENABLE", 0, 0, &umr_bitfield_default }, + { "DIG_SYMCLK_BE_ON", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_TMDS_CNTL[] = { + { "TMDS_SYNC_PHASE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_TMDS_CONTROL_CHAR[] = { + { "TMDS_CONTROL_CHAR0_OUT_EN", 0, 0, &umr_bitfield_default }, + { "TMDS_CONTROL_CHAR1_OUT_EN", 1, 1, &umr_bitfield_default }, + { "TMDS_CONTROL_CHAR2_OUT_EN", 2, 2, &umr_bitfield_default }, + { "TMDS_CONTROL_CHAR3_OUT_EN", 3, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_TMDS_CONTROL0_FEEDBACK[] = { + { "TMDS_CONTROL0_FEEDBACK_SELECT", 0, 1, &umr_bitfield_default }, + { "TMDS_CONTROL0_FEEDBACK_DELAY", 8, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_TMDS_STEREOSYNC_CTL_SEL[] = { + { "TMDS_STEREOSYNC_CTL_SEL", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1[] = { + { "TMDS_SYNC_CHAR_PATTERN0", 0, 9, &umr_bitfield_default }, + { "TMDS_SYNC_CHAR_PATTERN1", 16, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3[] = { + { "TMDS_SYNC_CHAR_PATTERN2", 0, 9, &umr_bitfield_default }, + { "TMDS_SYNC_CHAR_PATTERN3", 16, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_TMDS_CTL_BITS[] = { + { "TMDS_CTL0", 0, 0, &umr_bitfield_default }, + { "TMDS_CTL1", 8, 8, &umr_bitfield_default }, + { "TMDS_CTL2", 16, 16, &umr_bitfield_default }, + { "TMDS_CTL3", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_TMDS_DCBALANCER_CONTROL[] = { + { "TMDS_DCBALANCER_EN", 0, 0, &umr_bitfield_default }, + { "TMDS_DCBALANCER_TEST_EN", 8, 8, &umr_bitfield_default }, + { "TMDS_DCBALANCER_TEST_IN", 16, 19, &umr_bitfield_default }, + { "TMDS_DCBALANCER_FORCE", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_TMDS_CTL0_1_GEN_CNTL[] = { + { "TMDS_CTL0_DATA_SEL", 0, 3, &umr_bitfield_default }, + { "TMDS_CTL0_DATA_DELAY", 4, 6, &umr_bitfield_default }, + { "TMDS_CTL0_DATA_INVERT", 7, 7, &umr_bitfield_default }, + { "TMDS_CTL0_DATA_MODULATION", 8, 9, &umr_bitfield_default }, + { "TMDS_CTL0_USE_FEEDBACK_PATH", 10, 10, &umr_bitfield_default }, + { "TMDS_CTL0_FB_SYNC_CONT", 11, 11, &umr_bitfield_default }, + { "TMDS_CTL0_PATTERN_OUT_EN", 12, 12, &umr_bitfield_default }, + { "TMDS_CTL1_DATA_SEL", 16, 19, &umr_bitfield_default }, + { "TMDS_CTL1_DATA_DELAY", 20, 22, &umr_bitfield_default }, + { "TMDS_CTL1_DATA_INVERT", 23, 23, &umr_bitfield_default }, + { "TMDS_CTL1_DATA_MODULATION", 24, 25, &umr_bitfield_default }, + { "TMDS_CTL1_USE_FEEDBACK_PATH", 26, 26, &umr_bitfield_default }, + { "TMDS_CTL1_FB_SYNC_CONT", 27, 27, &umr_bitfield_default }, + { "TMDS_CTL1_PATTERN_OUT_EN", 28, 28, &umr_bitfield_default }, + { "TMDS_2BIT_COUNTER_EN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_TMDS_CTL2_3_GEN_CNTL[] = { + { "TMDS_CTL2_DATA_SEL", 0, 3, &umr_bitfield_default }, + { "TMDS_CTL2_DATA_DELAY", 4, 6, &umr_bitfield_default }, + { "TMDS_CTL2_DATA_INVERT", 7, 7, &umr_bitfield_default }, + { "TMDS_CTL2_DATA_MODULATION", 8, 9, &umr_bitfield_default }, + { "TMDS_CTL2_USE_FEEDBACK_PATH", 10, 10, &umr_bitfield_default }, + { "TMDS_CTL2_FB_SYNC_CONT", 11, 11, &umr_bitfield_default }, + { "TMDS_CTL2_PATTERN_OUT_EN", 12, 12, &umr_bitfield_default }, + { "TMDS_CTL3_DATA_SEL", 16, 19, &umr_bitfield_default }, + { "TMDS_CTL3_DATA_DELAY", 20, 22, &umr_bitfield_default }, + { "TMDS_CTL3_DATA_INVERT", 23, 23, &umr_bitfield_default }, + { "TMDS_CTL3_DATA_MODULATION", 24, 25, &umr_bitfield_default }, + { "TMDS_CTL3_USE_FEEDBACK_PATH", 26, 26, &umr_bitfield_default }, + { "TMDS_CTL3_FB_SYNC_CONT", 27, 27, &umr_bitfield_default }, + { "TMDS_CTL3_PATTERN_OUT_EN", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_DIG_VERSION[] = { + { "DIG_TYPE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_DIG_LANE_ENABLE[] = { + { "DIG_LANE0EN", 0, 0, &umr_bitfield_default }, + { "DIG_LANE1EN", 1, 1, &umr_bitfield_default }, + { "DIG_LANE2EN", 2, 2, &umr_bitfield_default }, + { "DIG_LANE3EN", 3, 3, &umr_bitfield_default }, + { "DIG_CLK_EN", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_AFMT_CNTL[] = { + { "AFMT_AUDIO_CLOCK_EN", 0, 0, &umr_bitfield_default }, + { "AFMT_AUDIO_CLOCK_ON", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG3_AFMT_VBI_PACKET_CONTROL1[] = { + { "AFMT_GENERIC0_FRAME_UPDATE", 0, 0, &umr_bitfield_default }, + { "AFMT_GENERIC0_FRAME_UPDATE_PENDING", 1, 1, &umr_bitfield_default }, + { "AFMT_GENERIC0_IMMEDIATE_UPDATE", 2, 2, &umr_bitfield_default }, + { "AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING", 3, 3, &umr_bitfield_default }, + { "AFMT_GENERIC1_FRAME_UPDATE", 4, 4, &umr_bitfield_default }, + { "AFMT_GENERIC1_FRAME_UPDATE_PENDING", 5, 5, &umr_bitfield_default }, + { "AFMT_GENERIC1_IMMEDIATE_UPDATE", 6, 6, &umr_bitfield_default }, + { "AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING", 7, 7, &umr_bitfield_default }, + { "AFMT_GENERIC2_FRAME_UPDATE", 8, 8, &umr_bitfield_default }, + { "AFMT_GENERIC2_FRAME_UPDATE_PENDING", 9, 9, &umr_bitfield_default }, + { "AFMT_GENERIC2_IMMEDIATE_UPDATE", 10, 10, &umr_bitfield_default }, + { "AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING", 11, 11, &umr_bitfield_default }, + { "AFMT_GENERIC3_FRAME_UPDATE", 12, 12, &umr_bitfield_default }, + { "AFMT_GENERIC3_FRAME_UPDATE_PENDING", 13, 13, &umr_bitfield_default }, + { "AFMT_GENERIC3_IMMEDIATE_UPDATE", 14, 14, &umr_bitfield_default }, + { "AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING", 15, 15, &umr_bitfield_default }, + { "AFMT_GENERIC4_FRAME_UPDATE", 16, 16, &umr_bitfield_default }, + { "AFMT_GENERIC4_FRAME_UPDATE_PENDING", 17, 17, &umr_bitfield_default }, + { "AFMT_GENERIC4_IMMEDIATE_UPDATE", 18, 18, &umr_bitfield_default }, + { "AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING", 19, 19, &umr_bitfield_default }, + { "AFMT_GENERIC5_FRAME_UPDATE", 20, 20, &umr_bitfield_default }, + { "AFMT_GENERIC5_FRAME_UPDATE_PENDING", 21, 21, &umr_bitfield_default }, + { "AFMT_GENERIC5_IMMEDIATE_UPDATE", 22, 22, &umr_bitfield_default }, + { "AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING", 23, 23, &umr_bitfield_default }, + { "AFMT_GENERIC6_FRAME_UPDATE", 24, 24, &umr_bitfield_default }, + { "AFMT_GENERIC6_FRAME_UPDATE_PENDING", 25, 25, &umr_bitfield_default }, + { "AFMT_GENERIC6_IMMEDIATE_UPDATE", 26, 26, &umr_bitfield_default }, + { "AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING", 27, 27, &umr_bitfield_default }, + { "AFMT_GENERIC7_FRAME_UPDATE", 28, 28, &umr_bitfield_default }, + { "AFMT_GENERIC7_FRAME_UPDATE_PENDING", 29, 29, &umr_bitfield_default }, + { "AFMT_GENERIC7_IMMEDIATE_UPDATE", 30, 30, &umr_bitfield_default }, + { "AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_LINK_CNTL[] = { + { "DP_LINK_TRAINING_COMPLETE", 4, 4, &umr_bitfield_default }, + { "DP_LINK_STATUS", 8, 8, &umr_bitfield_default }, + { "DP_EMBEDDED_PANEL_MODE", 17, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_PIXEL_FORMAT[] = { + { "DP_PIXEL_ENCODING", 0, 2, &umr_bitfield_default }, + { "DP_COMPONENT_DEPTH", 24, 26, &umr_bitfield_default }, + { "DP_PIXEL_COMBINE", 28, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_MSA_COLORIMETRY[] = { + { "DP_MSA_MISC0", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_CONFIG[] = { + { "DP_UDI_LANES", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_VID_STREAM_CNTL[] = { + { "DP_VID_STREAM_ENABLE", 0, 0, &umr_bitfield_default }, + { "DP_VID_STREAM_DIS_DEFER", 8, 9, &umr_bitfield_default }, + { "DP_VID_STREAM_STATUS", 16, 16, &umr_bitfield_default }, + { "DP_VID_STREAM_CHANGE_KEEPOUT", 20, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_STEER_FIFO[] = { + { "DP_STEER_FIFO_RESET", 0, 0, &umr_bitfield_default }, + { "DP_STEER_OVERFLOW_FLAG", 4, 4, &umr_bitfield_default }, + { "DP_STEER_OVERFLOW_INT", 5, 5, &umr_bitfield_default }, + { "DP_STEER_OVERFLOW_ACK", 6, 6, &umr_bitfield_default }, + { "DP_STEER_OVERFLOW_MASK", 7, 7, &umr_bitfield_default }, + { "DP_TU_OVERFLOW_FLAG", 8, 8, &umr_bitfield_default }, + { "DP_TU_OVERFLOW_ACK", 12, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_MSA_MISC[] = { + { "DP_MSA_MISC1", 0, 7, &umr_bitfield_default }, + { "DP_MSA_MISC2", 8, 15, &umr_bitfield_default }, + { "DP_MSA_MISC3", 16, 23, &umr_bitfield_default }, + { "DP_MSA_MISC4", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_VID_TIMING[] = { + { "DP_VID_M_N_DOUBLE_BUFFER_MODE", 4, 4, &umr_bitfield_default }, + { "DP_VID_M_N_GEN_EN", 8, 8, &umr_bitfield_default }, + { "DP_VID_N_MUL", 10, 11, &umr_bitfield_default }, + { "DP_VID_M_DIV", 12, 13, &umr_bitfield_default }, + { "DP_VID_N_DIV", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_VID_N[] = { + { "DP_VID_N", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_VID_M[] = { + { "DP_VID_M", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_LINK_FRAMING_CNTL[] = { + { "DP_IDLE_BS_INTERVAL", 0, 17, &umr_bitfield_default }, + { "DP_VBID_DISABLE", 24, 24, &umr_bitfield_default }, + { "DP_VID_ENHANCED_FRAME_MODE", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_HBR2_EYE_PATTERN[] = { + { "DP_HBR2_EYE_PATTERN_ENABLE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_VID_MSA_VBID[] = { + { "DP_VID_MSA_LOCATION", 0, 11, &umr_bitfield_default }, + { "DP_VID_VBID_FIELD_POL", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_VID_INTERRUPT_CNTL[] = { + { "DP_VID_STREAM_DISABLE_INT", 0, 0, &umr_bitfield_default }, + { "DP_VID_STREAM_DISABLE_ACK", 1, 1, &umr_bitfield_default }, + { "DP_VID_STREAM_DISABLE_MASK", 2, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_DPHY_CNTL[] = { + { "DPHY_ATEST_SEL_LANE0", 0, 0, &umr_bitfield_default }, + { "DPHY_ATEST_SEL_LANE1", 1, 1, &umr_bitfield_default }, + { "DPHY_ATEST_SEL_LANE2", 2, 2, &umr_bitfield_default }, + { "DPHY_ATEST_SEL_LANE3", 3, 3, &umr_bitfield_default }, + { "DPHY_BYPASS", 16, 16, &umr_bitfield_default }, + { "DPHY_SKEW_BYPASS", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_DPHY_TRAINING_PATTERN_SEL[] = { + { "DPHY_TRAINING_PATTERN_SEL", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_DPHY_SYM0[] = { + { "DPHY_SYM1", 0, 9, &umr_bitfield_default }, + { "DPHY_SYM2", 10, 19, &umr_bitfield_default }, + { "DPHY_SYM3", 20, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_DPHY_SYM1[] = { + { "DPHY_SYM4", 0, 9, &umr_bitfield_default }, + { "DPHY_SYM5", 10, 19, &umr_bitfield_default }, + { "DPHY_SYM6", 20, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_DPHY_SYM2[] = { + { "DPHY_SYM7", 0, 9, &umr_bitfield_default }, + { "DPHY_SYM8", 10, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_DPHY_8B10B_CNTL[] = { + { "DPHY_8B10B_RESET", 8, 8, &umr_bitfield_default }, + { "DPHY_8B10B_EXT_DISP", 16, 16, &umr_bitfield_default }, + { "DPHY_8B10B_CUR_DISP", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_DPHY_PRBS_CNTL[] = { + { "DPHY_PRBS_EN", 0, 0, &umr_bitfield_default }, + { "DPHY_PRBS_SEL", 4, 5, &umr_bitfield_default }, + { "DPHY_PRBS_SEED", 8, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_DPHY_SCRAM_CNTL[] = { + { "DPHY_SCRAMBLER_DIS", 0, 0, &umr_bitfield_default }, + { "DPHY_SCRAMBLER_ADVANCE", 4, 4, &umr_bitfield_default }, + { "DPHY_SCRAMBLER_BS_COUNT", 8, 17, &umr_bitfield_default }, + { "DPHY_SCRAMBLER_KCODE", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_DPHY_CRC_EN[] = { + { "DPHY_CRC_EN", 0, 0, &umr_bitfield_default }, + { "DPHY_CRC_CONT_EN", 4, 4, &umr_bitfield_default }, + { "DPHY_CRC_RESULT_VALID", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_DPHY_CRC_CNTL[] = { + { "DPHY_CRC_FIELD", 0, 0, &umr_bitfield_default }, + { "DPHY_CRC_SEL", 4, 5, &umr_bitfield_default }, + { "DPHY_CRC_MASK", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_DPHY_CRC_RESULT[] = { + { "DPHY_CRC_RESULT", 0, 7, &umr_bitfield_default }, + { "DPHY_CRC_RESULT1", 8, 15, &umr_bitfield_default }, + { "DPHY_CRC_RESULT2", 16, 23, &umr_bitfield_default }, + { "DPHY_CRC_RESULT3", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_DPHY_CRC_MST_CNTL[] = { + { "DPHY_CRC_MST_FIRST_SLOT", 0, 5, &umr_bitfield_default }, + { "DPHY_CRC_MST_LAST_SLOT", 8, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_DPHY_CRC_MST_STATUS[] = { + { "DPHY_CRC_MST_PHASE_LOCK", 0, 0, &umr_bitfield_default }, + { "DPHY_CRC_MST_PHASE_ERROR", 8, 8, &umr_bitfield_default }, + { "DPHY_CRC_MST_PHASE_ERROR_ACK", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_DPHY_FAST_TRAINING[] = { + { "DPHY_RX_FAST_TRAINING_CAPABLE", 0, 0, &umr_bitfield_default }, + { "DPHY_SW_FAST_TRAINING_START", 1, 1, &umr_bitfield_default }, + { "DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN", 2, 2, &umr_bitfield_default }, + { "DPHY_FAST_TRAINING_TP1_TIME", 8, 19, &umr_bitfield_default }, + { "DPHY_FAST_TRAINING_TP2_TIME", 20, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_DPHY_FAST_TRAINING_STATUS[] = { + { "DPHY_FAST_TRAINING_STATE", 0, 2, &umr_bitfield_default }, + { "DPHY_FAST_TRAINING_COMPLETE_OCCURRED", 4, 4, &umr_bitfield_default }, + { "DPHY_FAST_TRAINING_COMPLETE_MASK", 8, 8, &umr_bitfield_default }, + { "DPHY_FAST_TRAINING_COMPLETE_ACK", 12, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_SEC_CNTL[] = { + { "DP_SEC_STREAM_ENABLE", 0, 0, &umr_bitfield_default }, + { "DP_SEC_ASP_ENABLE", 4, 4, &umr_bitfield_default }, + { "DP_SEC_ATP_ENABLE", 8, 8, &umr_bitfield_default }, + { "DP_SEC_AIP_ENABLE", 12, 12, &umr_bitfield_default }, + { "DP_SEC_ACM_ENABLE", 16, 16, &umr_bitfield_default }, + { "DP_SEC_GSP0_ENABLE", 20, 20, &umr_bitfield_default }, + { "DP_SEC_GSP1_ENABLE", 21, 21, &umr_bitfield_default }, + { "DP_SEC_GSP2_ENABLE", 22, 22, &umr_bitfield_default }, + { "DP_SEC_GSP3_ENABLE", 23, 23, &umr_bitfield_default }, + { "DP_SEC_GSP4_ENABLE", 24, 24, &umr_bitfield_default }, + { "DP_SEC_GSP5_ENABLE", 25, 25, &umr_bitfield_default }, + { "DP_SEC_GSP6_ENABLE", 26, 26, &umr_bitfield_default }, + { "DP_SEC_GSP7_ENABLE", 27, 27, &umr_bitfield_default }, + { "DP_SEC_MPG_ENABLE", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_SEC_CNTL1[] = { + { "DP_SEC_ISRC_ENABLE", 0, 0, &umr_bitfield_default }, + { "DP_SEC_GSP0_PRIORITY", 4, 4, &umr_bitfield_default }, + { "DP_SEC_GSP0_SEND", 5, 5, &umr_bitfield_default }, + { "DP_SEC_GSP0_SEND_PENDING", 6, 6, &umr_bitfield_default }, + { "DP_SEC_GSP0_SEND_DEADLINE_MISSED", 7, 7, &umr_bitfield_default }, + { "DP_SEC_GSP0_SEND_ANY_LINE", 8, 8, &umr_bitfield_default }, + { "DP_SEC_GSP0_LINE_NUM", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_SEC_FRAMING1[] = { + { "DP_SEC_FRAME_START_LOCATION", 0, 11, &umr_bitfield_default }, + { "DP_SEC_VBLANK_TRANSMIT_WIDTH", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_SEC_FRAMING2[] = { + { "DP_SEC_START_POSITION", 0, 15, &umr_bitfield_default }, + { "DP_SEC_HBLANK_TRANSMIT_WIDTH", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_SEC_FRAMING3[] = { + { "DP_SEC_IDLE_FRAME_SIZE", 0, 13, &umr_bitfield_default }, + { "DP_SEC_IDLE_TRANSMIT_WIDTH", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_SEC_FRAMING4[] = { + { "DP_SEC_COLLISION_STATUS", 20, 20, &umr_bitfield_default }, + { "DP_SEC_COLLISION_ACK", 24, 24, &umr_bitfield_default }, + { "DP_SEC_AUDIO_MUTE", 28, 28, &umr_bitfield_default }, + { "DP_SEC_AUDIO_MUTE_STATUS", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_SEC_AUD_N[] = { + { "DP_SEC_AUD_N", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_SEC_AUD_N_READBACK[] = { + { "DP_SEC_AUD_N_READBACK", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_SEC_AUD_M[] = { + { "DP_SEC_AUD_M", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_SEC_AUD_M_READBACK[] = { + { "DP_SEC_AUD_M_READBACK", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_SEC_TIMESTAMP[] = { + { "DP_SEC_TIMESTAMP_MODE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_SEC_PACKET_CNTL[] = { + { "DP_SEC_ASP_CODING_TYPE", 1, 3, &umr_bitfield_default }, + { "DP_SEC_ASP_PRIORITY", 4, 4, &umr_bitfield_default }, + { "DP_SEC_VERSION", 8, 13, &umr_bitfield_default }, + { "DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_MSE_RATE_CNTL[] = { + { "DP_MSE_RATE_Y", 0, 25, &umr_bitfield_default }, + { "DP_MSE_RATE_X", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_MSE_RATE_UPDATE[] = { + { "DP_MSE_RATE_UPDATE_PENDING", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_MSE_SAT0[] = { + { "DP_MSE_SAT_SRC0", 0, 2, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT0", 8, 13, &umr_bitfield_default }, + { "DP_MSE_SAT_SRC1", 16, 18, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT1", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_MSE_SAT1[] = { + { "DP_MSE_SAT_SRC2", 0, 2, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT2", 8, 13, &umr_bitfield_default }, + { "DP_MSE_SAT_SRC3", 16, 18, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT3", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_MSE_SAT2[] = { + { "DP_MSE_SAT_SRC4", 0, 2, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT4", 8, 13, &umr_bitfield_default }, + { "DP_MSE_SAT_SRC5", 16, 18, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT5", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_MSE_SAT_UPDATE[] = { + { "DP_MSE_SAT_UPDATE", 0, 1, &umr_bitfield_default }, + { "DP_MSE_16_MTP_KEEPOUT", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_MSE_LINK_TIMING[] = { + { "DP_MSE_LINK_FRAME", 0, 9, &umr_bitfield_default }, + { "DP_MSE_LINK_LINE", 16, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_MSE_MISC_CNTL[] = { + { "DP_MSE_BLANK_CODE", 0, 0, &umr_bitfield_default }, + { "DP_MSE_TIMESTAMP_MODE", 4, 4, &umr_bitfield_default }, + { "DP_MSE_ZERO_ENCODER", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_DPHY_BS_SR_SWAP_CNTL[] = { + { "DPHY_LOAD_BS_COUNT", 0, 9, &umr_bitfield_default }, + { "DPHY_BS_SR_SWAP_DONE", 15, 15, &umr_bitfield_default }, + { "DPHY_LOAD_BS_COUNT_START", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL[] = { + { "DP_DPHY_HBR2_PATTERN_CONTROL", 0, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_MSE_SAT0_STATUS[] = { + { "DP_MSE_SAT_SRC0_STATUS", 0, 2, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT0_STATUS", 8, 13, &umr_bitfield_default }, + { "DP_MSE_SAT_SRC1_STATUS", 16, 18, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT1_STATUS", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_MSE_SAT1_STATUS[] = { + { "DP_MSE_SAT_SRC2_STATUS", 0, 2, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT2_STATUS", 8, 13, &umr_bitfield_default }, + { "DP_MSE_SAT_SRC3_STATUS", 16, 18, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT3_STATUS", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_MSE_SAT2_STATUS[] = { + { "DP_MSE_SAT_SRC4_STATUS", 0, 2, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT4_STATUS", 8, 13, &umr_bitfield_default }, + { "DP_MSE_SAT_SRC5_STATUS", 16, 18, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT5_STATUS", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_MSA_TIMING_PARAM1[] = { + { "DP_MSA_VTOTAL", 0, 15, &umr_bitfield_default }, + { "DP_MSA_HTOTAL", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_MSA_TIMING_PARAM2[] = { + { "DP_MSA_VSTART", 0, 15, &umr_bitfield_default }, + { "DP_MSA_HSTART", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_MSA_TIMING_PARAM3[] = { + { "DP_MSA_VSYNCWIDTH", 0, 14, &umr_bitfield_default }, + { "DP_MSA_VSYNCPOLARITY", 15, 15, &umr_bitfield_default }, + { "DP_MSA_HSYNCWIDTH", 16, 30, &umr_bitfield_default }, + { "DP_MSA_HSYNCPOLARITY", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_MSA_TIMING_PARAM4[] = { + { "DP_MSA_VHEIGHT", 0, 15, &umr_bitfield_default }, + { "DP_MSA_HWIDTH", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_MSO_CNTL[] = { + { "DP_MSO_NUM_OF_SSTLINK", 0, 1, &umr_bitfield_default }, + { "DP_MSO_SEC_STREAM_ENABLE", 4, 7, &umr_bitfield_default }, + { "DP_MSO_SEC_ASP_ENABLE", 8, 11, &umr_bitfield_default }, + { "DP_MSO_SEC_ATP_ENABLE", 12, 15, &umr_bitfield_default }, + { "DP_MSO_SEC_AIP_ENABLE", 16, 19, &umr_bitfield_default }, + { "DP_MSO_SEC_ACM_ENABLE", 20, 23, &umr_bitfield_default }, + { "DP_MSO_SEC_GSP0_ENABLE", 24, 27, &umr_bitfield_default }, + { "DP_MSO_SEC_GSP1_ENABLE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_MSO_CNTL1[] = { + { "DP_MSO_SEC_GSP2_ENABLE", 0, 3, &umr_bitfield_default }, + { "DP_MSO_SEC_GSP3_ENABLE", 4, 7, &umr_bitfield_default }, + { "DP_MSO_SEC_GSP4_ENABLE", 8, 11, &umr_bitfield_default }, + { "DP_MSO_SEC_GSP5_ENABLE", 12, 15, &umr_bitfield_default }, + { "DP_MSO_SEC_GSP6_ENABLE", 16, 19, &umr_bitfield_default }, + { "DP_MSO_SEC_GSP7_ENABLE", 20, 23, &umr_bitfield_default }, + { "DP_MSO_SEC_MPG_ENABLE", 24, 27, &umr_bitfield_default }, + { "DP_MSO_SEC_ISRC_ENABLE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_DSC_CNTL[] = { + { "DP_DSC_EN", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_SEC_CNTL2[] = { + { "DP_SEC_GSP1_SEND", 0, 0, &umr_bitfield_default }, + { "DP_SEC_GSP1_SEND_PENDING", 1, 1, &umr_bitfield_default }, + { "DP_SEC_GSP1_SEND_DEADLINE_MISSED", 2, 2, &umr_bitfield_default }, + { "DP_SEC_GSP1_SEND_ANY_LINE", 3, 3, &umr_bitfield_default }, + { "DP_SEC_GSP2_SEND", 4, 4, &umr_bitfield_default }, + { "DP_SEC_GSP2_SEND_PENDING", 5, 5, &umr_bitfield_default }, + { "DP_SEC_GSP2_SEND_DEADLINE_MISSED", 6, 6, &umr_bitfield_default }, + { "DP_SEC_GSP2_SEND_ANY_LINE", 7, 7, &umr_bitfield_default }, + { "DP_SEC_GSP3_SEND", 8, 8, &umr_bitfield_default }, + { "DP_SEC_GSP3_SEND_PENDING", 9, 9, &umr_bitfield_default }, + { "DP_SEC_GSP3_SEND_DEADLINE_MISSED", 10, 10, &umr_bitfield_default }, + { "DP_SEC_GSP3_SEND_ANY_LINE", 11, 11, &umr_bitfield_default }, + { "DP_SEC_GSP4_SEND", 12, 12, &umr_bitfield_default }, + { "DP_SEC_GSP4_SEND_PENDING", 13, 13, &umr_bitfield_default }, + { "DP_SEC_GSP4_SEND_DEADLINE_MISSED", 14, 14, &umr_bitfield_default }, + { "DP_SEC_GSP4_SEND_ANY_LINE", 15, 15, &umr_bitfield_default }, + { "DP_SEC_GSP5_SEND", 16, 16, &umr_bitfield_default }, + { "DP_SEC_GSP5_SEND_PENDING", 17, 17, &umr_bitfield_default }, + { "DP_SEC_GSP5_SEND_DEADLINE_MISSED", 18, 18, &umr_bitfield_default }, + { "DP_SEC_GSP5_SEND_ANY_LINE", 19, 19, &umr_bitfield_default }, + { "DP_SEC_GSP6_SEND", 20, 20, &umr_bitfield_default }, + { "DP_SEC_GSP6_SEND_PENDING", 21, 21, &umr_bitfield_default }, + { "DP_SEC_GSP6_SEND_DEADLINE_MISSED", 22, 22, &umr_bitfield_default }, + { "DP_SEC_GSP6_SEND_ANY_LINE", 23, 23, &umr_bitfield_default }, + { "DP_SEC_GSP7_SEND", 24, 24, &umr_bitfield_default }, + { "DP_SEC_GSP7_SEND_PENDING", 25, 25, &umr_bitfield_default }, + { "DP_SEC_GSP7_SEND_DEADLINE_MISSED", 26, 26, &umr_bitfield_default }, + { "DP_SEC_GSP7_SEND_ANY_LINE", 27, 27, &umr_bitfield_default }, + { "DP_SEC_GSP7_PPS", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_SEC_CNTL3[] = { + { "DP_SEC_GSP1_LINE_NUM", 0, 15, &umr_bitfield_default }, + { "DP_SEC_GSP2_LINE_NUM", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_SEC_CNTL4[] = { + { "DP_SEC_GSP3_LINE_NUM", 0, 15, &umr_bitfield_default }, + { "DP_SEC_GSP4_LINE_NUM", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_SEC_CNTL5[] = { + { "DP_SEC_GSP5_LINE_NUM", 0, 15, &umr_bitfield_default }, + { "DP_SEC_GSP6_LINE_NUM", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_SEC_CNTL6[] = { + { "DP_SEC_GSP7_LINE_NUM", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_SEC_CNTL7[] = { + { "DP_SEC_GSP0_SEND_ACTIVE", 0, 0, &umr_bitfield_default }, + { "DP_SEC_GSP1_SEND_ACTIVE", 4, 4, &umr_bitfield_default }, + { "DP_SEC_GSP2_SEND_ACTIVE", 8, 8, &umr_bitfield_default }, + { "DP_SEC_GSP3_SEND_ACTIVE", 12, 12, &umr_bitfield_default }, + { "DP_SEC_GSP4_SEND_ACTIVE", 16, 16, &umr_bitfield_default }, + { "DP_SEC_GSP5_SEND_ACTIVE", 20, 20, &umr_bitfield_default }, + { "DP_SEC_GSP6_SEND_ACTIVE", 24, 24, &umr_bitfield_default }, + { "DP_SEC_GSP7_SEND_ACTIVE", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_DB_CNTL[] = { + { "DP_DB_PENDING", 0, 0, &umr_bitfield_default }, + { "DP_DB_TAKEN", 4, 4, &umr_bitfield_default }, + { "DP_DB_TAKEN_CLR", 5, 5, &umr_bitfield_default }, + { "DP_DB_LOCK", 8, 8, &umr_bitfield_default }, + { "DP_DB_DISABLE", 12, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP3_DP_MSA_VBID_MISC[] = { + { "DP_MSA_MISC1_STEREOSYNC_OVERRIDE", 0, 1, &umr_bitfield_default }, + { "DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN", 4, 4, &umr_bitfield_default }, + { "DP_VBID1_OVERRIDE", 8, 8, &umr_bitfield_default }, + { "DP_VBID2_OVERRIDE", 9, 9, &umr_bitfield_default }, + { "DP_VBID1_OVERRIDE_EN", 12, 12, &umr_bitfield_default }, + { "DP_VBID2_OVERRIDE_EN", 13, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_DIG_FE_CNTL[] = { + { "DIG_SOURCE_SELECT", 0, 2, &umr_bitfield_default }, + { "DIG_STEREOSYNC_SELECT", 4, 6, &umr_bitfield_default }, + { "DIG_STEREOSYNC_GATE_EN", 8, 8, &umr_bitfield_default }, + { "DIG_START", 10, 10, &umr_bitfield_default }, + { "DIG_DIGITAL_BYPASS_SELECT", 12, 14, &umr_bitfield_default }, + { "DIG_SYMCLK_FE_ON", 24, 24, &umr_bitfield_default }, + { "TMDS_PIXEL_ENCODING", 28, 28, &umr_bitfield_default }, + { "TMDS_COLOR_FORMAT", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_DIG_OUTPUT_CRC_CNTL[] = { + { "DIG_OUTPUT_CRC_EN", 0, 0, &umr_bitfield_default }, + { "DIG_OUTPUT_CRC_LINK_SEL", 4, 4, &umr_bitfield_default }, + { "DIG_OUTPUT_CRC_DATA_SEL", 8, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_DIG_OUTPUT_CRC_RESULT[] = { + { "DIG_OUTPUT_CRC_RESULT", 0, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_DIG_CLOCK_PATTERN[] = { + { "DIG_CLOCK_PATTERN", 0, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_DIG_TEST_PATTERN[] = { + { "DIG_TEST_PATTERN_OUT_EN", 0, 0, &umr_bitfield_default }, + { "DIG_HALF_CLOCK_PATTERN_SEL", 1, 1, &umr_bitfield_default }, + { "DIG_RANDOM_PATTERN_OUT_EN", 4, 4, &umr_bitfield_default }, + { "DIG_RANDOM_PATTERN_RESET", 5, 5, &umr_bitfield_default }, + { "DIG_TEST_PATTERN_EXTERNAL_RESET_EN", 6, 6, &umr_bitfield_default }, + { "DIG_STATIC_TEST_PATTERN", 16, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_DIG_RANDOM_PATTERN_SEED[] = { + { "DIG_RANDOM_PATTERN_SEED", 0, 23, &umr_bitfield_default }, + { "DIG_RAN_PAT_DURING_DE_ONLY", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_DIG_FIFO_STATUS[] = { + { "DIG_FIFO_LEVEL_ERROR", 0, 0, &umr_bitfield_default }, + { "DIG_FIFO_USE_OVERWRITE_LEVEL", 1, 1, &umr_bitfield_default }, + { "DIG_FIFO_OVERWRITE_LEVEL", 2, 7, &umr_bitfield_default }, + { "DIG_FIFO_ERROR_ACK", 8, 8, &umr_bitfield_default }, + { "DIG_FIFO_CAL_AVERAGE_LEVEL", 10, 15, &umr_bitfield_default }, + { "DIG_FIFO_MAXIMUM_LEVEL", 16, 20, &umr_bitfield_default }, + { "DIG_FIFO_MINIMUM_LEVEL", 22, 25, &umr_bitfield_default }, + { "DIG_FIFO_READ_CLOCK_SRC", 26, 26, &umr_bitfield_default }, + { "DIG_FIFO_CALIBRATED", 29, 29, &umr_bitfield_default }, + { "DIG_FIFO_FORCE_RECAL_AVERAGE", 30, 30, &umr_bitfield_default }, + { "DIG_FIFO_FORCE_RECOMP_MINMAX", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_HDMI_CONTROL[] = { + { "HDMI_KEEPOUT_MODE", 0, 0, &umr_bitfield_default }, + { "HDMI_DATA_SCRAMBLE_EN", 1, 1, &umr_bitfield_default }, + { "HDMI_CLOCK_CHANNEL_RATE", 2, 2, &umr_bitfield_default }, + { "HDMI_NO_EXTRA_NULL_PACKET_FILLED", 3, 3, &umr_bitfield_default }, + { "HDMI_PACKET_GEN_VERSION", 4, 4, &umr_bitfield_default }, + { "HDMI_ERROR_ACK", 8, 8, &umr_bitfield_default }, + { "HDMI_ERROR_MASK", 9, 9, &umr_bitfield_default }, + { "HDMI_DEEP_COLOR_ENABLE", 24, 24, &umr_bitfield_default }, + { "HDMI_DEEP_COLOR_DEPTH", 28, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_HDMI_STATUS[] = { + { "HDMI_ACTIVE_AVMUTE", 0, 0, &umr_bitfield_default }, + { "HDMI_AUDIO_PACKET_ERROR", 16, 16, &umr_bitfield_default }, + { "HDMI_VBI_PACKET_ERROR", 20, 20, &umr_bitfield_default }, + { "HDMI_ERROR_INT", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_HDMI_AUDIO_PACKET_CONTROL[] = { + { "HDMI_AUDIO_DELAY_EN", 4, 5, &umr_bitfield_default }, + { "HDMI_AUDIO_PACKETS_PER_LINE", 16, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_HDMI_ACR_PACKET_CONTROL[] = { + { "HDMI_ACR_SEND", 0, 0, &umr_bitfield_default }, + { "HDMI_ACR_CONT", 1, 1, &umr_bitfield_default }, + { "HDMI_ACR_SELECT", 4, 5, &umr_bitfield_default }, + { "HDMI_ACR_SOURCE", 8, 8, &umr_bitfield_default }, + { "HDMI_ACR_AUTO_SEND", 12, 12, &umr_bitfield_default }, + { "HDMI_ACR_N_MULTIPLE", 16, 18, &umr_bitfield_default }, + { "HDMI_ACR_AUDIO_PRIORITY", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_HDMI_VBI_PACKET_CONTROL[] = { + { "HDMI_NULL_SEND", 0, 0, &umr_bitfield_default }, + { "HDMI_GC_SEND", 4, 4, &umr_bitfield_default }, + { "HDMI_GC_CONT", 5, 5, &umr_bitfield_default }, + { "HDMI_ISRC_SEND", 8, 8, &umr_bitfield_default }, + { "HDMI_ISRC_CONT", 9, 9, &umr_bitfield_default }, + { "HDMI_ISRC_LINE", 16, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_HDMI_INFOFRAME_CONTROL0[] = { + { "HDMI_AUDIO_INFO_SEND", 4, 4, &umr_bitfield_default }, + { "HDMI_AUDIO_INFO_CONT", 5, 5, &umr_bitfield_default }, + { "HDMI_MPEG_INFO_SEND", 8, 8, &umr_bitfield_default }, + { "HDMI_MPEG_INFO_CONT", 9, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_HDMI_INFOFRAME_CONTROL1[] = { + { "HDMI_AUDIO_INFO_LINE", 8, 13, &umr_bitfield_default }, + { "HDMI_MPEG_INFO_LINE", 16, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_HDMI_GENERIC_PACKET_CONTROL0[] = { + { "HDMI_GENERIC0_SEND", 0, 0, &umr_bitfield_default }, + { "HDMI_GENERIC0_CONT", 1, 1, &umr_bitfield_default }, + { "HDMI_GENERIC1_SEND", 4, 4, &umr_bitfield_default }, + { "HDMI_GENERIC1_CONT", 5, 5, &umr_bitfield_default }, + { "HDMI_GENERIC0_LINE", 16, 21, &umr_bitfield_default }, + { "HDMI_GENERIC1_LINE", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_HDMI_GC[] = { + { "HDMI_GC_AVMUTE", 0, 0, &umr_bitfield_default }, + { "HDMI_GC_AVMUTE_CONT", 2, 2, &umr_bitfield_default }, + { "HDMI_DEFAULT_PHASE", 4, 4, &umr_bitfield_default }, + { "HDMI_PACKING_PHASE", 8, 11, &umr_bitfield_default }, + { "HDMI_PACKING_PHASE_OVERRIDE", 12, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_AFMT_AUDIO_PACKET_CONTROL2[] = { + { "AFMT_AUDIO_LAYOUT_OVRD", 0, 0, &umr_bitfield_default }, + { "AFMT_AUDIO_LAYOUT_SELECT", 1, 1, &umr_bitfield_default }, + { "AFMT_AUDIO_CHANNEL_ENABLE", 8, 15, &umr_bitfield_default }, + { "AFMT_DP_AUDIO_STREAM_ID", 16, 23, &umr_bitfield_default }, + { "AFMT_HBR_ENABLE_OVRD", 24, 24, &umr_bitfield_default }, + { "AFMT_60958_OSF_OVRD", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_AFMT_ISRC1_0[] = { + { "AFMT_ISRC_STATUS", 0, 2, &umr_bitfield_default }, + { "AFMT_ISRC_CONTINUE", 6, 6, &umr_bitfield_default }, + { "AFMT_ISRC_VALID", 7, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_AFMT_ISRC1_1[] = { + { "AFMT_UPC_EAN_ISRC0", 0, 7, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC1", 8, 15, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC2", 16, 23, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC3", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_AFMT_ISRC1_2[] = { + { "AFMT_UPC_EAN_ISRC4", 0, 7, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC5", 8, 15, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC6", 16, 23, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC7", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_AFMT_ISRC1_3[] = { + { "AFMT_UPC_EAN_ISRC8", 0, 7, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC9", 8, 15, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC10", 16, 23, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC11", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_AFMT_ISRC1_4[] = { + { "AFMT_UPC_EAN_ISRC12", 0, 7, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC13", 8, 15, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC14", 16, 23, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC15", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_AFMT_ISRC2_0[] = { + { "AFMT_UPC_EAN_ISRC16", 0, 7, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC17", 8, 15, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC18", 16, 23, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC19", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_AFMT_ISRC2_1[] = { + { "AFMT_UPC_EAN_ISRC20", 0, 7, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC21", 8, 15, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC22", 16, 23, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC23", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_AFMT_ISRC2_2[] = { + { "AFMT_UPC_EAN_ISRC24", 0, 7, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC25", 8, 15, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC26", 16, 23, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC27", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_AFMT_ISRC2_3[] = { + { "AFMT_UPC_EAN_ISRC28", 0, 7, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC29", 8, 15, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC30", 16, 23, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC31", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_HDMI_GENERIC_PACKET_CONTROL2[] = { + { "HDMI_GENERIC4_SEND", 0, 0, &umr_bitfield_default }, + { "HDMI_GENERIC4_CONT", 1, 1, &umr_bitfield_default }, + { "HDMI_GENERIC5_SEND", 4, 4, &umr_bitfield_default }, + { "HDMI_GENERIC5_CONT", 5, 5, &umr_bitfield_default }, + { "HDMI_GENERIC4_LINE", 16, 21, &umr_bitfield_default }, + { "HDMI_GENERIC5_LINE", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_HDMI_GENERIC_PACKET_CONTROL3[] = { + { "HDMI_GENERIC6_SEND", 0, 0, &umr_bitfield_default }, + { "HDMI_GENERIC6_CONT", 1, 1, &umr_bitfield_default }, + { "HDMI_GENERIC7_SEND", 4, 4, &umr_bitfield_default }, + { "HDMI_GENERIC7_CONT", 5, 5, &umr_bitfield_default }, + { "HDMI_GENERIC6_LINE", 16, 21, &umr_bitfield_default }, + { "HDMI_GENERIC7_LINE", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_HDMI_DB_CONTROL[] = { + { "HDMI_DB_PENDING", 0, 0, &umr_bitfield_default }, + { "HDMI_DB_TAKEN", 4, 4, &umr_bitfield_default }, + { "HDMI_DB_TAKEN_CLR", 5, 5, &umr_bitfield_default }, + { "HDMI_DB_LOCK", 8, 8, &umr_bitfield_default }, + { "HDMI_DB_DISABLE", 12, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_AFMT_MPEG_INFO0[] = { + { "AFMT_MPEG_INFO_CHECKSUM", 0, 7, &umr_bitfield_default }, + { "AFMT_MPEG_INFO_MB0", 8, 15, &umr_bitfield_default }, + { "AFMT_MPEG_INFO_MB1", 16, 23, &umr_bitfield_default }, + { "AFMT_MPEG_INFO_MB2", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_AFMT_MPEG_INFO1[] = { + { "AFMT_MPEG_INFO_MB3", 0, 7, &umr_bitfield_default }, + { "AFMT_MPEG_INFO_MF", 8, 9, &umr_bitfield_default }, + { "AFMT_MPEG_INFO_FR", 12, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_AFMT_GENERIC_HDR[] = { + { "AFMT_GENERIC_HB0", 0, 7, &umr_bitfield_default }, + { "AFMT_GENERIC_HB1", 8, 15, &umr_bitfield_default }, + { "AFMT_GENERIC_HB2", 16, 23, &umr_bitfield_default }, + { "AFMT_GENERIC_HB3", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_AFMT_GENERIC_0[] = { + { "AFMT_GENERIC_BYTE0", 0, 7, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE1", 8, 15, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE2", 16, 23, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE3", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_AFMT_GENERIC_1[] = { + { "AFMT_GENERIC_BYTE4", 0, 7, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE5", 8, 15, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE6", 16, 23, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE7", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_AFMT_GENERIC_2[] = { + { "AFMT_GENERIC_BYTE8", 0, 7, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE9", 8, 15, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE10", 16, 23, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE11", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_AFMT_GENERIC_3[] = { + { "AFMT_GENERIC_BYTE12", 0, 7, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE13", 8, 15, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE14", 16, 23, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE15", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_AFMT_GENERIC_4[] = { + { "AFMT_GENERIC_BYTE16", 0, 7, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE17", 8, 15, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE18", 16, 23, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE19", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_AFMT_GENERIC_5[] = { + { "AFMT_GENERIC_BYTE20", 0, 7, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE21", 8, 15, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE22", 16, 23, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE23", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_AFMT_GENERIC_6[] = { + { "AFMT_GENERIC_BYTE24", 0, 7, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE25", 8, 15, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE26", 16, 23, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE27", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_AFMT_GENERIC_7[] = { + { "AFMT_GENERIC_BYTE28", 0, 7, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE29", 8, 15, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE30", 16, 23, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE31", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_HDMI_GENERIC_PACKET_CONTROL1[] = { + { "HDMI_GENERIC2_SEND", 0, 0, &umr_bitfield_default }, + { "HDMI_GENERIC2_CONT", 1, 1, &umr_bitfield_default }, + { "HDMI_GENERIC3_SEND", 4, 4, &umr_bitfield_default }, + { "HDMI_GENERIC3_CONT", 5, 5, &umr_bitfield_default }, + { "HDMI_GENERIC2_LINE", 16, 21, &umr_bitfield_default }, + { "HDMI_GENERIC3_LINE", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_HDMI_ACR_32_0[] = { + { "HDMI_ACR_CTS_32", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_HDMI_ACR_32_1[] = { + { "HDMI_ACR_N_32", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_HDMI_ACR_44_0[] = { + { "HDMI_ACR_CTS_44", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_HDMI_ACR_44_1[] = { + { "HDMI_ACR_N_44", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_HDMI_ACR_48_0[] = { + { "HDMI_ACR_CTS_48", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_HDMI_ACR_48_1[] = { + { "HDMI_ACR_N_48", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_HDMI_ACR_STATUS_0[] = { + { "HDMI_ACR_CTS", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_HDMI_ACR_STATUS_1[] = { + { "HDMI_ACR_N", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_AFMT_AUDIO_INFO0[] = { + { "AFMT_AUDIO_INFO_CHECKSUM", 0, 7, &umr_bitfield_default }, + { "AFMT_AUDIO_INFO_CC", 8, 10, &umr_bitfield_default }, + { "AFMT_AUDIO_INFO_CT", 11, 14, &umr_bitfield_default }, + { "AFMT_AUDIO_INFO_CHECKSUM_OFFSET", 16, 23, &umr_bitfield_default }, + { "AFMT_AUDIO_INFO_CXT", 24, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_AFMT_AUDIO_INFO1[] = { + { "AFMT_AUDIO_INFO_CA", 0, 7, &umr_bitfield_default }, + { "AFMT_AUDIO_INFO_LSV", 11, 14, &umr_bitfield_default }, + { "AFMT_AUDIO_INFO_DM_INH", 15, 15, &umr_bitfield_default }, + { "AFMT_AUDIO_INFO_LFEPBL", 16, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_AFMT_60958_0[] = { + { "AFMT_60958_CS_A", 0, 0, &umr_bitfield_default }, + { "AFMT_60958_CS_B", 1, 1, &umr_bitfield_default }, + { "AFMT_60958_CS_C", 2, 2, &umr_bitfield_default }, + { "AFMT_60958_CS_D", 3, 5, &umr_bitfield_default }, + { "AFMT_60958_CS_MODE", 6, 7, &umr_bitfield_default }, + { "AFMT_60958_CS_CATEGORY_CODE", 8, 15, &umr_bitfield_default }, + { "AFMT_60958_CS_SOURCE_NUMBER", 16, 19, &umr_bitfield_default }, + { "AFMT_60958_CS_CHANNEL_NUMBER_L", 20, 23, &umr_bitfield_default }, + { "AFMT_60958_CS_SAMPLING_FREQUENCY", 24, 27, &umr_bitfield_default }, + { "AFMT_60958_CS_CLOCK_ACCURACY", 28, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_AFMT_60958_1[] = { + { "AFMT_60958_CS_WORD_LENGTH", 0, 3, &umr_bitfield_default }, + { "AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY", 4, 7, &umr_bitfield_default }, + { "AFMT_60958_VALID_L", 16, 16, &umr_bitfield_default }, + { "AFMT_60958_VALID_R", 18, 18, &umr_bitfield_default }, + { "AFMT_60958_CS_CHANNEL_NUMBER_R", 20, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_AFMT_AUDIO_CRC_CONTROL[] = { + { "AFMT_AUDIO_CRC_EN", 0, 0, &umr_bitfield_default }, + { "AFMT_AUDIO_CRC_CONT", 4, 4, &umr_bitfield_default }, + { "AFMT_AUDIO_CRC_SOURCE", 8, 8, &umr_bitfield_default }, + { "AFMT_AUDIO_CRC_CH_SEL", 12, 15, &umr_bitfield_default }, + { "AFMT_AUDIO_CRC_COUNT", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_AFMT_RAMP_CONTROL0[] = { + { "AFMT_RAMP_MAX_COUNT", 0, 23, &umr_bitfield_default }, + { "AFMT_RAMP_DATA_SIGN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_AFMT_RAMP_CONTROL1[] = { + { "AFMT_RAMP_MIN_COUNT", 0, 23, &umr_bitfield_default }, + { "AFMT_AUDIO_TEST_CH_DISABLE", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_AFMT_RAMP_CONTROL2[] = { + { "AFMT_RAMP_INC_COUNT", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_AFMT_RAMP_CONTROL3[] = { + { "AFMT_RAMP_DEC_COUNT", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_AFMT_60958_2[] = { + { "AFMT_60958_CS_CHANNEL_NUMBER_2", 0, 3, &umr_bitfield_default }, + { "AFMT_60958_CS_CHANNEL_NUMBER_3", 4, 7, &umr_bitfield_default }, + { "AFMT_60958_CS_CHANNEL_NUMBER_4", 8, 11, &umr_bitfield_default }, + { "AFMT_60958_CS_CHANNEL_NUMBER_5", 12, 15, &umr_bitfield_default }, + { "AFMT_60958_CS_CHANNEL_NUMBER_6", 16, 19, &umr_bitfield_default }, + { "AFMT_60958_CS_CHANNEL_NUMBER_7", 20, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_AFMT_AUDIO_CRC_RESULT[] = { + { "AFMT_AUDIO_CRC_DONE", 0, 0, &umr_bitfield_default }, + { "AFMT_AUDIO_CRC", 8, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_AFMT_STATUS[] = { + { "AFMT_AUDIO_ENABLE", 4, 4, &umr_bitfield_default }, + { "AFMT_AZ_HBR_ENABLE", 8, 8, &umr_bitfield_default }, + { "AFMT_AUDIO_FIFO_OVERFLOW", 24, 24, &umr_bitfield_default }, + { "AFMT_AZ_AUDIO_ENABLE_CHG", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_AFMT_AUDIO_PACKET_CONTROL[] = { + { "AFMT_AUDIO_SAMPLE_SEND", 0, 0, &umr_bitfield_default }, + { "AFMT_RESET_FIFO_WHEN_AUDIO_DIS", 11, 11, &umr_bitfield_default }, + { "AFMT_AUDIO_TEST_EN", 12, 12, &umr_bitfield_default }, + { "AFMT_AUDIO_TEST_MODE", 14, 14, &umr_bitfield_default }, + { "AFMT_AUDIO_FIFO_OVERFLOW_ACK", 23, 23, &umr_bitfield_default }, + { "AFMT_AUDIO_CHANNEL_SWAP", 24, 24, &umr_bitfield_default }, + { "AFMT_60958_CS_UPDATE", 26, 26, &umr_bitfield_default }, + { "AFMT_AZ_AUDIO_ENABLE_CHG_ACK", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_AFMT_VBI_PACKET_CONTROL[] = { + { "AFMT_GENERIC_LOCK_STATUS", 8, 8, &umr_bitfield_default }, + { "AFMT_GENERIC_CONFLICT", 16, 16, &umr_bitfield_default }, + { "AFMT_GENERIC_CONFLICT_CLR", 17, 17, &umr_bitfield_default }, + { "AFMT_GENERIC_INDEX", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_AFMT_INFOFRAME_CONTROL0[] = { + { "AFMT_AUDIO_INFO_SOURCE", 6, 6, &umr_bitfield_default }, + { "AFMT_AUDIO_INFO_UPDATE", 7, 7, &umr_bitfield_default }, + { "AFMT_MPEG_INFO_UPDATE", 10, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_AFMT_AUDIO_SRC_CONTROL[] = { + { "AFMT_AUDIO_SRC_SELECT", 0, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_DIG_BE_CNTL[] = { + { "DIG_DUAL_LINK_ENABLE", 0, 0, &umr_bitfield_default }, + { "DIG_SWAP", 1, 1, &umr_bitfield_default }, + { "DIG_FE_SOURCE_SELECT", 8, 14, &umr_bitfield_default }, + { "DIG_MODE", 16, 18, &umr_bitfield_default }, + { "DIG_HPD_SELECT", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_DIG_BE_EN_CNTL[] = { + { "DIG_ENABLE", 0, 0, &umr_bitfield_default }, + { "DIG_SYMCLK_BE_ON", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_TMDS_CNTL[] = { + { "TMDS_SYNC_PHASE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_TMDS_CONTROL_CHAR[] = { + { "TMDS_CONTROL_CHAR0_OUT_EN", 0, 0, &umr_bitfield_default }, + { "TMDS_CONTROL_CHAR1_OUT_EN", 1, 1, &umr_bitfield_default }, + { "TMDS_CONTROL_CHAR2_OUT_EN", 2, 2, &umr_bitfield_default }, + { "TMDS_CONTROL_CHAR3_OUT_EN", 3, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_TMDS_CONTROL0_FEEDBACK[] = { + { "TMDS_CONTROL0_FEEDBACK_SELECT", 0, 1, &umr_bitfield_default }, + { "TMDS_CONTROL0_FEEDBACK_DELAY", 8, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_TMDS_STEREOSYNC_CTL_SEL[] = { + { "TMDS_STEREOSYNC_CTL_SEL", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1[] = { + { "TMDS_SYNC_CHAR_PATTERN0", 0, 9, &umr_bitfield_default }, + { "TMDS_SYNC_CHAR_PATTERN1", 16, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3[] = { + { "TMDS_SYNC_CHAR_PATTERN2", 0, 9, &umr_bitfield_default }, + { "TMDS_SYNC_CHAR_PATTERN3", 16, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_TMDS_CTL_BITS[] = { + { "TMDS_CTL0", 0, 0, &umr_bitfield_default }, + { "TMDS_CTL1", 8, 8, &umr_bitfield_default }, + { "TMDS_CTL2", 16, 16, &umr_bitfield_default }, + { "TMDS_CTL3", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_TMDS_DCBALANCER_CONTROL[] = { + { "TMDS_DCBALANCER_EN", 0, 0, &umr_bitfield_default }, + { "TMDS_DCBALANCER_TEST_EN", 8, 8, &umr_bitfield_default }, + { "TMDS_DCBALANCER_TEST_IN", 16, 19, &umr_bitfield_default }, + { "TMDS_DCBALANCER_FORCE", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_TMDS_CTL0_1_GEN_CNTL[] = { + { "TMDS_CTL0_DATA_SEL", 0, 3, &umr_bitfield_default }, + { "TMDS_CTL0_DATA_DELAY", 4, 6, &umr_bitfield_default }, + { "TMDS_CTL0_DATA_INVERT", 7, 7, &umr_bitfield_default }, + { "TMDS_CTL0_DATA_MODULATION", 8, 9, &umr_bitfield_default }, + { "TMDS_CTL0_USE_FEEDBACK_PATH", 10, 10, &umr_bitfield_default }, + { "TMDS_CTL0_FB_SYNC_CONT", 11, 11, &umr_bitfield_default }, + { "TMDS_CTL0_PATTERN_OUT_EN", 12, 12, &umr_bitfield_default }, + { "TMDS_CTL1_DATA_SEL", 16, 19, &umr_bitfield_default }, + { "TMDS_CTL1_DATA_DELAY", 20, 22, &umr_bitfield_default }, + { "TMDS_CTL1_DATA_INVERT", 23, 23, &umr_bitfield_default }, + { "TMDS_CTL1_DATA_MODULATION", 24, 25, &umr_bitfield_default }, + { "TMDS_CTL1_USE_FEEDBACK_PATH", 26, 26, &umr_bitfield_default }, + { "TMDS_CTL1_FB_SYNC_CONT", 27, 27, &umr_bitfield_default }, + { "TMDS_CTL1_PATTERN_OUT_EN", 28, 28, &umr_bitfield_default }, + { "TMDS_2BIT_COUNTER_EN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_TMDS_CTL2_3_GEN_CNTL[] = { + { "TMDS_CTL2_DATA_SEL", 0, 3, &umr_bitfield_default }, + { "TMDS_CTL2_DATA_DELAY", 4, 6, &umr_bitfield_default }, + { "TMDS_CTL2_DATA_INVERT", 7, 7, &umr_bitfield_default }, + { "TMDS_CTL2_DATA_MODULATION", 8, 9, &umr_bitfield_default }, + { "TMDS_CTL2_USE_FEEDBACK_PATH", 10, 10, &umr_bitfield_default }, + { "TMDS_CTL2_FB_SYNC_CONT", 11, 11, &umr_bitfield_default }, + { "TMDS_CTL2_PATTERN_OUT_EN", 12, 12, &umr_bitfield_default }, + { "TMDS_CTL3_DATA_SEL", 16, 19, &umr_bitfield_default }, + { "TMDS_CTL3_DATA_DELAY", 20, 22, &umr_bitfield_default }, + { "TMDS_CTL3_DATA_INVERT", 23, 23, &umr_bitfield_default }, + { "TMDS_CTL3_DATA_MODULATION", 24, 25, &umr_bitfield_default }, + { "TMDS_CTL3_USE_FEEDBACK_PATH", 26, 26, &umr_bitfield_default }, + { "TMDS_CTL3_FB_SYNC_CONT", 27, 27, &umr_bitfield_default }, + { "TMDS_CTL3_PATTERN_OUT_EN", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_DIG_VERSION[] = { + { "DIG_TYPE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_DIG_LANE_ENABLE[] = { + { "DIG_LANE0EN", 0, 0, &umr_bitfield_default }, + { "DIG_LANE1EN", 1, 1, &umr_bitfield_default }, + { "DIG_LANE2EN", 2, 2, &umr_bitfield_default }, + { "DIG_LANE3EN", 3, 3, &umr_bitfield_default }, + { "DIG_CLK_EN", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_AFMT_CNTL[] = { + { "AFMT_AUDIO_CLOCK_EN", 0, 0, &umr_bitfield_default }, + { "AFMT_AUDIO_CLOCK_ON", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG4_AFMT_VBI_PACKET_CONTROL1[] = { + { "AFMT_GENERIC0_FRAME_UPDATE", 0, 0, &umr_bitfield_default }, + { "AFMT_GENERIC0_FRAME_UPDATE_PENDING", 1, 1, &umr_bitfield_default }, + { "AFMT_GENERIC0_IMMEDIATE_UPDATE", 2, 2, &umr_bitfield_default }, + { "AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING", 3, 3, &umr_bitfield_default }, + { "AFMT_GENERIC1_FRAME_UPDATE", 4, 4, &umr_bitfield_default }, + { "AFMT_GENERIC1_FRAME_UPDATE_PENDING", 5, 5, &umr_bitfield_default }, + { "AFMT_GENERIC1_IMMEDIATE_UPDATE", 6, 6, &umr_bitfield_default }, + { "AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING", 7, 7, &umr_bitfield_default }, + { "AFMT_GENERIC2_FRAME_UPDATE", 8, 8, &umr_bitfield_default }, + { "AFMT_GENERIC2_FRAME_UPDATE_PENDING", 9, 9, &umr_bitfield_default }, + { "AFMT_GENERIC2_IMMEDIATE_UPDATE", 10, 10, &umr_bitfield_default }, + { "AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING", 11, 11, &umr_bitfield_default }, + { "AFMT_GENERIC3_FRAME_UPDATE", 12, 12, &umr_bitfield_default }, + { "AFMT_GENERIC3_FRAME_UPDATE_PENDING", 13, 13, &umr_bitfield_default }, + { "AFMT_GENERIC3_IMMEDIATE_UPDATE", 14, 14, &umr_bitfield_default }, + { "AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING", 15, 15, &umr_bitfield_default }, + { "AFMT_GENERIC4_FRAME_UPDATE", 16, 16, &umr_bitfield_default }, + { "AFMT_GENERIC4_FRAME_UPDATE_PENDING", 17, 17, &umr_bitfield_default }, + { "AFMT_GENERIC4_IMMEDIATE_UPDATE", 18, 18, &umr_bitfield_default }, + { "AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING", 19, 19, &umr_bitfield_default }, + { "AFMT_GENERIC5_FRAME_UPDATE", 20, 20, &umr_bitfield_default }, + { "AFMT_GENERIC5_FRAME_UPDATE_PENDING", 21, 21, &umr_bitfield_default }, + { "AFMT_GENERIC5_IMMEDIATE_UPDATE", 22, 22, &umr_bitfield_default }, + { "AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING", 23, 23, &umr_bitfield_default }, + { "AFMT_GENERIC6_FRAME_UPDATE", 24, 24, &umr_bitfield_default }, + { "AFMT_GENERIC6_FRAME_UPDATE_PENDING", 25, 25, &umr_bitfield_default }, + { "AFMT_GENERIC6_IMMEDIATE_UPDATE", 26, 26, &umr_bitfield_default }, + { "AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING", 27, 27, &umr_bitfield_default }, + { "AFMT_GENERIC7_FRAME_UPDATE", 28, 28, &umr_bitfield_default }, + { "AFMT_GENERIC7_FRAME_UPDATE_PENDING", 29, 29, &umr_bitfield_default }, + { "AFMT_GENERIC7_IMMEDIATE_UPDATE", 30, 30, &umr_bitfield_default }, + { "AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_LINK_CNTL[] = { + { "DP_LINK_TRAINING_COMPLETE", 4, 4, &umr_bitfield_default }, + { "DP_LINK_STATUS", 8, 8, &umr_bitfield_default }, + { "DP_EMBEDDED_PANEL_MODE", 17, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_PIXEL_FORMAT[] = { + { "DP_PIXEL_ENCODING", 0, 2, &umr_bitfield_default }, + { "DP_COMPONENT_DEPTH", 24, 26, &umr_bitfield_default }, + { "DP_PIXEL_COMBINE", 28, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_MSA_COLORIMETRY[] = { + { "DP_MSA_MISC0", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_CONFIG[] = { + { "DP_UDI_LANES", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_VID_STREAM_CNTL[] = { + { "DP_VID_STREAM_ENABLE", 0, 0, &umr_bitfield_default }, + { "DP_VID_STREAM_DIS_DEFER", 8, 9, &umr_bitfield_default }, + { "DP_VID_STREAM_STATUS", 16, 16, &umr_bitfield_default }, + { "DP_VID_STREAM_CHANGE_KEEPOUT", 20, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_STEER_FIFO[] = { + { "DP_STEER_FIFO_RESET", 0, 0, &umr_bitfield_default }, + { "DP_STEER_OVERFLOW_FLAG", 4, 4, &umr_bitfield_default }, + { "DP_STEER_OVERFLOW_INT", 5, 5, &umr_bitfield_default }, + { "DP_STEER_OVERFLOW_ACK", 6, 6, &umr_bitfield_default }, + { "DP_STEER_OVERFLOW_MASK", 7, 7, &umr_bitfield_default }, + { "DP_TU_OVERFLOW_FLAG", 8, 8, &umr_bitfield_default }, + { "DP_TU_OVERFLOW_ACK", 12, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_MSA_MISC[] = { + { "DP_MSA_MISC1", 0, 7, &umr_bitfield_default }, + { "DP_MSA_MISC2", 8, 15, &umr_bitfield_default }, + { "DP_MSA_MISC3", 16, 23, &umr_bitfield_default }, + { "DP_MSA_MISC4", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_VID_TIMING[] = { + { "DP_VID_M_N_DOUBLE_BUFFER_MODE", 4, 4, &umr_bitfield_default }, + { "DP_VID_M_N_GEN_EN", 8, 8, &umr_bitfield_default }, + { "DP_VID_N_MUL", 10, 11, &umr_bitfield_default }, + { "DP_VID_M_DIV", 12, 13, &umr_bitfield_default }, + { "DP_VID_N_DIV", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_VID_N[] = { + { "DP_VID_N", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_VID_M[] = { + { "DP_VID_M", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_LINK_FRAMING_CNTL[] = { + { "DP_IDLE_BS_INTERVAL", 0, 17, &umr_bitfield_default }, + { "DP_VBID_DISABLE", 24, 24, &umr_bitfield_default }, + { "DP_VID_ENHANCED_FRAME_MODE", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_HBR2_EYE_PATTERN[] = { + { "DP_HBR2_EYE_PATTERN_ENABLE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_VID_MSA_VBID[] = { + { "DP_VID_MSA_LOCATION", 0, 11, &umr_bitfield_default }, + { "DP_VID_VBID_FIELD_POL", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_VID_INTERRUPT_CNTL[] = { + { "DP_VID_STREAM_DISABLE_INT", 0, 0, &umr_bitfield_default }, + { "DP_VID_STREAM_DISABLE_ACK", 1, 1, &umr_bitfield_default }, + { "DP_VID_STREAM_DISABLE_MASK", 2, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_DPHY_CNTL[] = { + { "DPHY_ATEST_SEL_LANE0", 0, 0, &umr_bitfield_default }, + { "DPHY_ATEST_SEL_LANE1", 1, 1, &umr_bitfield_default }, + { "DPHY_ATEST_SEL_LANE2", 2, 2, &umr_bitfield_default }, + { "DPHY_ATEST_SEL_LANE3", 3, 3, &umr_bitfield_default }, + { "DPHY_BYPASS", 16, 16, &umr_bitfield_default }, + { "DPHY_SKEW_BYPASS", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_DPHY_TRAINING_PATTERN_SEL[] = { + { "DPHY_TRAINING_PATTERN_SEL", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_DPHY_SYM0[] = { + { "DPHY_SYM1", 0, 9, &umr_bitfield_default }, + { "DPHY_SYM2", 10, 19, &umr_bitfield_default }, + { "DPHY_SYM3", 20, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_DPHY_SYM1[] = { + { "DPHY_SYM4", 0, 9, &umr_bitfield_default }, + { "DPHY_SYM5", 10, 19, &umr_bitfield_default }, + { "DPHY_SYM6", 20, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_DPHY_SYM2[] = { + { "DPHY_SYM7", 0, 9, &umr_bitfield_default }, + { "DPHY_SYM8", 10, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_DPHY_8B10B_CNTL[] = { + { "DPHY_8B10B_RESET", 8, 8, &umr_bitfield_default }, + { "DPHY_8B10B_EXT_DISP", 16, 16, &umr_bitfield_default }, + { "DPHY_8B10B_CUR_DISP", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_DPHY_PRBS_CNTL[] = { + { "DPHY_PRBS_EN", 0, 0, &umr_bitfield_default }, + { "DPHY_PRBS_SEL", 4, 5, &umr_bitfield_default }, + { "DPHY_PRBS_SEED", 8, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_DPHY_SCRAM_CNTL[] = { + { "DPHY_SCRAMBLER_DIS", 0, 0, &umr_bitfield_default }, + { "DPHY_SCRAMBLER_ADVANCE", 4, 4, &umr_bitfield_default }, + { "DPHY_SCRAMBLER_BS_COUNT", 8, 17, &umr_bitfield_default }, + { "DPHY_SCRAMBLER_KCODE", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_DPHY_CRC_EN[] = { + { "DPHY_CRC_EN", 0, 0, &umr_bitfield_default }, + { "DPHY_CRC_CONT_EN", 4, 4, &umr_bitfield_default }, + { "DPHY_CRC_RESULT_VALID", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_DPHY_CRC_CNTL[] = { + { "DPHY_CRC_FIELD", 0, 0, &umr_bitfield_default }, + { "DPHY_CRC_SEL", 4, 5, &umr_bitfield_default }, + { "DPHY_CRC_MASK", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_DPHY_CRC_RESULT[] = { + { "DPHY_CRC_RESULT", 0, 7, &umr_bitfield_default }, + { "DPHY_CRC_RESULT1", 8, 15, &umr_bitfield_default }, + { "DPHY_CRC_RESULT2", 16, 23, &umr_bitfield_default }, + { "DPHY_CRC_RESULT3", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_DPHY_CRC_MST_CNTL[] = { + { "DPHY_CRC_MST_FIRST_SLOT", 0, 5, &umr_bitfield_default }, + { "DPHY_CRC_MST_LAST_SLOT", 8, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_DPHY_CRC_MST_STATUS[] = { + { "DPHY_CRC_MST_PHASE_LOCK", 0, 0, &umr_bitfield_default }, + { "DPHY_CRC_MST_PHASE_ERROR", 8, 8, &umr_bitfield_default }, + { "DPHY_CRC_MST_PHASE_ERROR_ACK", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_DPHY_FAST_TRAINING[] = { + { "DPHY_RX_FAST_TRAINING_CAPABLE", 0, 0, &umr_bitfield_default }, + { "DPHY_SW_FAST_TRAINING_START", 1, 1, &umr_bitfield_default }, + { "DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN", 2, 2, &umr_bitfield_default }, + { "DPHY_FAST_TRAINING_TP1_TIME", 8, 19, &umr_bitfield_default }, + { "DPHY_FAST_TRAINING_TP2_TIME", 20, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_DPHY_FAST_TRAINING_STATUS[] = { + { "DPHY_FAST_TRAINING_STATE", 0, 2, &umr_bitfield_default }, + { "DPHY_FAST_TRAINING_COMPLETE_OCCURRED", 4, 4, &umr_bitfield_default }, + { "DPHY_FAST_TRAINING_COMPLETE_MASK", 8, 8, &umr_bitfield_default }, + { "DPHY_FAST_TRAINING_COMPLETE_ACK", 12, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_SEC_CNTL[] = { + { "DP_SEC_STREAM_ENABLE", 0, 0, &umr_bitfield_default }, + { "DP_SEC_ASP_ENABLE", 4, 4, &umr_bitfield_default }, + { "DP_SEC_ATP_ENABLE", 8, 8, &umr_bitfield_default }, + { "DP_SEC_AIP_ENABLE", 12, 12, &umr_bitfield_default }, + { "DP_SEC_ACM_ENABLE", 16, 16, &umr_bitfield_default }, + { "DP_SEC_GSP0_ENABLE", 20, 20, &umr_bitfield_default }, + { "DP_SEC_GSP1_ENABLE", 21, 21, &umr_bitfield_default }, + { "DP_SEC_GSP2_ENABLE", 22, 22, &umr_bitfield_default }, + { "DP_SEC_GSP3_ENABLE", 23, 23, &umr_bitfield_default }, + { "DP_SEC_GSP4_ENABLE", 24, 24, &umr_bitfield_default }, + { "DP_SEC_GSP5_ENABLE", 25, 25, &umr_bitfield_default }, + { "DP_SEC_GSP6_ENABLE", 26, 26, &umr_bitfield_default }, + { "DP_SEC_GSP7_ENABLE", 27, 27, &umr_bitfield_default }, + { "DP_SEC_MPG_ENABLE", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_SEC_CNTL1[] = { + { "DP_SEC_ISRC_ENABLE", 0, 0, &umr_bitfield_default }, + { "DP_SEC_GSP0_PRIORITY", 4, 4, &umr_bitfield_default }, + { "DP_SEC_GSP0_SEND", 5, 5, &umr_bitfield_default }, + { "DP_SEC_GSP0_SEND_PENDING", 6, 6, &umr_bitfield_default }, + { "DP_SEC_GSP0_SEND_DEADLINE_MISSED", 7, 7, &umr_bitfield_default }, + { "DP_SEC_GSP0_SEND_ANY_LINE", 8, 8, &umr_bitfield_default }, + { "DP_SEC_GSP0_LINE_NUM", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_SEC_FRAMING1[] = { + { "DP_SEC_FRAME_START_LOCATION", 0, 11, &umr_bitfield_default }, + { "DP_SEC_VBLANK_TRANSMIT_WIDTH", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_SEC_FRAMING2[] = { + { "DP_SEC_START_POSITION", 0, 15, &umr_bitfield_default }, + { "DP_SEC_HBLANK_TRANSMIT_WIDTH", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_SEC_FRAMING3[] = { + { "DP_SEC_IDLE_FRAME_SIZE", 0, 13, &umr_bitfield_default }, + { "DP_SEC_IDLE_TRANSMIT_WIDTH", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_SEC_FRAMING4[] = { + { "DP_SEC_COLLISION_STATUS", 20, 20, &umr_bitfield_default }, + { "DP_SEC_COLLISION_ACK", 24, 24, &umr_bitfield_default }, + { "DP_SEC_AUDIO_MUTE", 28, 28, &umr_bitfield_default }, + { "DP_SEC_AUDIO_MUTE_STATUS", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_SEC_AUD_N[] = { + { "DP_SEC_AUD_N", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_SEC_AUD_N_READBACK[] = { + { "DP_SEC_AUD_N_READBACK", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_SEC_AUD_M[] = { + { "DP_SEC_AUD_M", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_SEC_AUD_M_READBACK[] = { + { "DP_SEC_AUD_M_READBACK", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_SEC_TIMESTAMP[] = { + { "DP_SEC_TIMESTAMP_MODE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_SEC_PACKET_CNTL[] = { + { "DP_SEC_ASP_CODING_TYPE", 1, 3, &umr_bitfield_default }, + { "DP_SEC_ASP_PRIORITY", 4, 4, &umr_bitfield_default }, + { "DP_SEC_VERSION", 8, 13, &umr_bitfield_default }, + { "DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_MSE_RATE_CNTL[] = { + { "DP_MSE_RATE_Y", 0, 25, &umr_bitfield_default }, + { "DP_MSE_RATE_X", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_MSE_RATE_UPDATE[] = { + { "DP_MSE_RATE_UPDATE_PENDING", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_MSE_SAT0[] = { + { "DP_MSE_SAT_SRC0", 0, 2, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT0", 8, 13, &umr_bitfield_default }, + { "DP_MSE_SAT_SRC1", 16, 18, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT1", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_MSE_SAT1[] = { + { "DP_MSE_SAT_SRC2", 0, 2, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT2", 8, 13, &umr_bitfield_default }, + { "DP_MSE_SAT_SRC3", 16, 18, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT3", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_MSE_SAT2[] = { + { "DP_MSE_SAT_SRC4", 0, 2, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT4", 8, 13, &umr_bitfield_default }, + { "DP_MSE_SAT_SRC5", 16, 18, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT5", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_MSE_SAT_UPDATE[] = { + { "DP_MSE_SAT_UPDATE", 0, 1, &umr_bitfield_default }, + { "DP_MSE_16_MTP_KEEPOUT", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_MSE_LINK_TIMING[] = { + { "DP_MSE_LINK_FRAME", 0, 9, &umr_bitfield_default }, + { "DP_MSE_LINK_LINE", 16, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_MSE_MISC_CNTL[] = { + { "DP_MSE_BLANK_CODE", 0, 0, &umr_bitfield_default }, + { "DP_MSE_TIMESTAMP_MODE", 4, 4, &umr_bitfield_default }, + { "DP_MSE_ZERO_ENCODER", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_DPHY_BS_SR_SWAP_CNTL[] = { + { "DPHY_LOAD_BS_COUNT", 0, 9, &umr_bitfield_default }, + { "DPHY_BS_SR_SWAP_DONE", 15, 15, &umr_bitfield_default }, + { "DPHY_LOAD_BS_COUNT_START", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL[] = { + { "DP_DPHY_HBR2_PATTERN_CONTROL", 0, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_MSE_SAT0_STATUS[] = { + { "DP_MSE_SAT_SRC0_STATUS", 0, 2, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT0_STATUS", 8, 13, &umr_bitfield_default }, + { "DP_MSE_SAT_SRC1_STATUS", 16, 18, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT1_STATUS", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_MSE_SAT1_STATUS[] = { + { "DP_MSE_SAT_SRC2_STATUS", 0, 2, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT2_STATUS", 8, 13, &umr_bitfield_default }, + { "DP_MSE_SAT_SRC3_STATUS", 16, 18, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT3_STATUS", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_MSE_SAT2_STATUS[] = { + { "DP_MSE_SAT_SRC4_STATUS", 0, 2, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT4_STATUS", 8, 13, &umr_bitfield_default }, + { "DP_MSE_SAT_SRC5_STATUS", 16, 18, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT5_STATUS", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_MSA_TIMING_PARAM1[] = { + { "DP_MSA_VTOTAL", 0, 15, &umr_bitfield_default }, + { "DP_MSA_HTOTAL", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_MSA_TIMING_PARAM2[] = { + { "DP_MSA_VSTART", 0, 15, &umr_bitfield_default }, + { "DP_MSA_HSTART", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_MSA_TIMING_PARAM3[] = { + { "DP_MSA_VSYNCWIDTH", 0, 14, &umr_bitfield_default }, + { "DP_MSA_VSYNCPOLARITY", 15, 15, &umr_bitfield_default }, + { "DP_MSA_HSYNCWIDTH", 16, 30, &umr_bitfield_default }, + { "DP_MSA_HSYNCPOLARITY", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_MSA_TIMING_PARAM4[] = { + { "DP_MSA_VHEIGHT", 0, 15, &umr_bitfield_default }, + { "DP_MSA_HWIDTH", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_MSO_CNTL[] = { + { "DP_MSO_NUM_OF_SSTLINK", 0, 1, &umr_bitfield_default }, + { "DP_MSO_SEC_STREAM_ENABLE", 4, 7, &umr_bitfield_default }, + { "DP_MSO_SEC_ASP_ENABLE", 8, 11, &umr_bitfield_default }, + { "DP_MSO_SEC_ATP_ENABLE", 12, 15, &umr_bitfield_default }, + { "DP_MSO_SEC_AIP_ENABLE", 16, 19, &umr_bitfield_default }, + { "DP_MSO_SEC_ACM_ENABLE", 20, 23, &umr_bitfield_default }, + { "DP_MSO_SEC_GSP0_ENABLE", 24, 27, &umr_bitfield_default }, + { "DP_MSO_SEC_GSP1_ENABLE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_MSO_CNTL1[] = { + { "DP_MSO_SEC_GSP2_ENABLE", 0, 3, &umr_bitfield_default }, + { "DP_MSO_SEC_GSP3_ENABLE", 4, 7, &umr_bitfield_default }, + { "DP_MSO_SEC_GSP4_ENABLE", 8, 11, &umr_bitfield_default }, + { "DP_MSO_SEC_GSP5_ENABLE", 12, 15, &umr_bitfield_default }, + { "DP_MSO_SEC_GSP6_ENABLE", 16, 19, &umr_bitfield_default }, + { "DP_MSO_SEC_GSP7_ENABLE", 20, 23, &umr_bitfield_default }, + { "DP_MSO_SEC_MPG_ENABLE", 24, 27, &umr_bitfield_default }, + { "DP_MSO_SEC_ISRC_ENABLE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_DSC_CNTL[] = { + { "DP_DSC_EN", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_SEC_CNTL2[] = { + { "DP_SEC_GSP1_SEND", 0, 0, &umr_bitfield_default }, + { "DP_SEC_GSP1_SEND_PENDING", 1, 1, &umr_bitfield_default }, + { "DP_SEC_GSP1_SEND_DEADLINE_MISSED", 2, 2, &umr_bitfield_default }, + { "DP_SEC_GSP1_SEND_ANY_LINE", 3, 3, &umr_bitfield_default }, + { "DP_SEC_GSP2_SEND", 4, 4, &umr_bitfield_default }, + { "DP_SEC_GSP2_SEND_PENDING", 5, 5, &umr_bitfield_default }, + { "DP_SEC_GSP2_SEND_DEADLINE_MISSED", 6, 6, &umr_bitfield_default }, + { "DP_SEC_GSP2_SEND_ANY_LINE", 7, 7, &umr_bitfield_default }, + { "DP_SEC_GSP3_SEND", 8, 8, &umr_bitfield_default }, + { "DP_SEC_GSP3_SEND_PENDING", 9, 9, &umr_bitfield_default }, + { "DP_SEC_GSP3_SEND_DEADLINE_MISSED", 10, 10, &umr_bitfield_default }, + { "DP_SEC_GSP3_SEND_ANY_LINE", 11, 11, &umr_bitfield_default }, + { "DP_SEC_GSP4_SEND", 12, 12, &umr_bitfield_default }, + { "DP_SEC_GSP4_SEND_PENDING", 13, 13, &umr_bitfield_default }, + { "DP_SEC_GSP4_SEND_DEADLINE_MISSED", 14, 14, &umr_bitfield_default }, + { "DP_SEC_GSP4_SEND_ANY_LINE", 15, 15, &umr_bitfield_default }, + { "DP_SEC_GSP5_SEND", 16, 16, &umr_bitfield_default }, + { "DP_SEC_GSP5_SEND_PENDING", 17, 17, &umr_bitfield_default }, + { "DP_SEC_GSP5_SEND_DEADLINE_MISSED", 18, 18, &umr_bitfield_default }, + { "DP_SEC_GSP5_SEND_ANY_LINE", 19, 19, &umr_bitfield_default }, + { "DP_SEC_GSP6_SEND", 20, 20, &umr_bitfield_default }, + { "DP_SEC_GSP6_SEND_PENDING", 21, 21, &umr_bitfield_default }, + { "DP_SEC_GSP6_SEND_DEADLINE_MISSED", 22, 22, &umr_bitfield_default }, + { "DP_SEC_GSP6_SEND_ANY_LINE", 23, 23, &umr_bitfield_default }, + { "DP_SEC_GSP7_SEND", 24, 24, &umr_bitfield_default }, + { "DP_SEC_GSP7_SEND_PENDING", 25, 25, &umr_bitfield_default }, + { "DP_SEC_GSP7_SEND_DEADLINE_MISSED", 26, 26, &umr_bitfield_default }, + { "DP_SEC_GSP7_SEND_ANY_LINE", 27, 27, &umr_bitfield_default }, + { "DP_SEC_GSP7_PPS", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_SEC_CNTL3[] = { + { "DP_SEC_GSP1_LINE_NUM", 0, 15, &umr_bitfield_default }, + { "DP_SEC_GSP2_LINE_NUM", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_SEC_CNTL4[] = { + { "DP_SEC_GSP3_LINE_NUM", 0, 15, &umr_bitfield_default }, + { "DP_SEC_GSP4_LINE_NUM", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_SEC_CNTL5[] = { + { "DP_SEC_GSP5_LINE_NUM", 0, 15, &umr_bitfield_default }, + { "DP_SEC_GSP6_LINE_NUM", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_SEC_CNTL6[] = { + { "DP_SEC_GSP7_LINE_NUM", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_SEC_CNTL7[] = { + { "DP_SEC_GSP0_SEND_ACTIVE", 0, 0, &umr_bitfield_default }, + { "DP_SEC_GSP1_SEND_ACTIVE", 4, 4, &umr_bitfield_default }, + { "DP_SEC_GSP2_SEND_ACTIVE", 8, 8, &umr_bitfield_default }, + { "DP_SEC_GSP3_SEND_ACTIVE", 12, 12, &umr_bitfield_default }, + { "DP_SEC_GSP4_SEND_ACTIVE", 16, 16, &umr_bitfield_default }, + { "DP_SEC_GSP5_SEND_ACTIVE", 20, 20, &umr_bitfield_default }, + { "DP_SEC_GSP6_SEND_ACTIVE", 24, 24, &umr_bitfield_default }, + { "DP_SEC_GSP7_SEND_ACTIVE", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_DB_CNTL[] = { + { "DP_DB_PENDING", 0, 0, &umr_bitfield_default }, + { "DP_DB_TAKEN", 4, 4, &umr_bitfield_default }, + { "DP_DB_TAKEN_CLR", 5, 5, &umr_bitfield_default }, + { "DP_DB_LOCK", 8, 8, &umr_bitfield_default }, + { "DP_DB_DISABLE", 12, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP4_DP_MSA_VBID_MISC[] = { + { "DP_MSA_MISC1_STEREOSYNC_OVERRIDE", 0, 1, &umr_bitfield_default }, + { "DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN", 4, 4, &umr_bitfield_default }, + { "DP_VBID1_OVERRIDE", 8, 8, &umr_bitfield_default }, + { "DP_VBID2_OVERRIDE", 9, 9, &umr_bitfield_default }, + { "DP_VBID1_OVERRIDE_EN", 12, 12, &umr_bitfield_default }, + { "DP_VBID2_OVERRIDE_EN", 13, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_DIG_FE_CNTL[] = { + { "DIG_SOURCE_SELECT", 0, 2, &umr_bitfield_default }, + { "DIG_STEREOSYNC_SELECT", 4, 6, &umr_bitfield_default }, + { "DIG_STEREOSYNC_GATE_EN", 8, 8, &umr_bitfield_default }, + { "DIG_START", 10, 10, &umr_bitfield_default }, + { "DIG_DIGITAL_BYPASS_SELECT", 12, 14, &umr_bitfield_default }, + { "DIG_SYMCLK_FE_ON", 24, 24, &umr_bitfield_default }, + { "TMDS_PIXEL_ENCODING", 28, 28, &umr_bitfield_default }, + { "TMDS_COLOR_FORMAT", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_DIG_OUTPUT_CRC_CNTL[] = { + { "DIG_OUTPUT_CRC_EN", 0, 0, &umr_bitfield_default }, + { "DIG_OUTPUT_CRC_LINK_SEL", 4, 4, &umr_bitfield_default }, + { "DIG_OUTPUT_CRC_DATA_SEL", 8, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_DIG_OUTPUT_CRC_RESULT[] = { + { "DIG_OUTPUT_CRC_RESULT", 0, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_DIG_CLOCK_PATTERN[] = { + { "DIG_CLOCK_PATTERN", 0, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_DIG_TEST_PATTERN[] = { + { "DIG_TEST_PATTERN_OUT_EN", 0, 0, &umr_bitfield_default }, + { "DIG_HALF_CLOCK_PATTERN_SEL", 1, 1, &umr_bitfield_default }, + { "DIG_RANDOM_PATTERN_OUT_EN", 4, 4, &umr_bitfield_default }, + { "DIG_RANDOM_PATTERN_RESET", 5, 5, &umr_bitfield_default }, + { "DIG_TEST_PATTERN_EXTERNAL_RESET_EN", 6, 6, &umr_bitfield_default }, + { "DIG_STATIC_TEST_PATTERN", 16, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_DIG_RANDOM_PATTERN_SEED[] = { + { "DIG_RANDOM_PATTERN_SEED", 0, 23, &umr_bitfield_default }, + { "DIG_RAN_PAT_DURING_DE_ONLY", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_DIG_FIFO_STATUS[] = { + { "DIG_FIFO_LEVEL_ERROR", 0, 0, &umr_bitfield_default }, + { "DIG_FIFO_USE_OVERWRITE_LEVEL", 1, 1, &umr_bitfield_default }, + { "DIG_FIFO_OVERWRITE_LEVEL", 2, 7, &umr_bitfield_default }, + { "DIG_FIFO_ERROR_ACK", 8, 8, &umr_bitfield_default }, + { "DIG_FIFO_CAL_AVERAGE_LEVEL", 10, 15, &umr_bitfield_default }, + { "DIG_FIFO_MAXIMUM_LEVEL", 16, 20, &umr_bitfield_default }, + { "DIG_FIFO_MINIMUM_LEVEL", 22, 25, &umr_bitfield_default }, + { "DIG_FIFO_READ_CLOCK_SRC", 26, 26, &umr_bitfield_default }, + { "DIG_FIFO_CALIBRATED", 29, 29, &umr_bitfield_default }, + { "DIG_FIFO_FORCE_RECAL_AVERAGE", 30, 30, &umr_bitfield_default }, + { "DIG_FIFO_FORCE_RECOMP_MINMAX", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_HDMI_CONTROL[] = { + { "HDMI_KEEPOUT_MODE", 0, 0, &umr_bitfield_default }, + { "HDMI_DATA_SCRAMBLE_EN", 1, 1, &umr_bitfield_default }, + { "HDMI_CLOCK_CHANNEL_RATE", 2, 2, &umr_bitfield_default }, + { "HDMI_NO_EXTRA_NULL_PACKET_FILLED", 3, 3, &umr_bitfield_default }, + { "HDMI_PACKET_GEN_VERSION", 4, 4, &umr_bitfield_default }, + { "HDMI_ERROR_ACK", 8, 8, &umr_bitfield_default }, + { "HDMI_ERROR_MASK", 9, 9, &umr_bitfield_default }, + { "HDMI_DEEP_COLOR_ENABLE", 24, 24, &umr_bitfield_default }, + { "HDMI_DEEP_COLOR_DEPTH", 28, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_HDMI_STATUS[] = { + { "HDMI_ACTIVE_AVMUTE", 0, 0, &umr_bitfield_default }, + { "HDMI_AUDIO_PACKET_ERROR", 16, 16, &umr_bitfield_default }, + { "HDMI_VBI_PACKET_ERROR", 20, 20, &umr_bitfield_default }, + { "HDMI_ERROR_INT", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_HDMI_AUDIO_PACKET_CONTROL[] = { + { "HDMI_AUDIO_DELAY_EN", 4, 5, &umr_bitfield_default }, + { "HDMI_AUDIO_PACKETS_PER_LINE", 16, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_HDMI_ACR_PACKET_CONTROL[] = { + { "HDMI_ACR_SEND", 0, 0, &umr_bitfield_default }, + { "HDMI_ACR_CONT", 1, 1, &umr_bitfield_default }, + { "HDMI_ACR_SELECT", 4, 5, &umr_bitfield_default }, + { "HDMI_ACR_SOURCE", 8, 8, &umr_bitfield_default }, + { "HDMI_ACR_AUTO_SEND", 12, 12, &umr_bitfield_default }, + { "HDMI_ACR_N_MULTIPLE", 16, 18, &umr_bitfield_default }, + { "HDMI_ACR_AUDIO_PRIORITY", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_HDMI_VBI_PACKET_CONTROL[] = { + { "HDMI_NULL_SEND", 0, 0, &umr_bitfield_default }, + { "HDMI_GC_SEND", 4, 4, &umr_bitfield_default }, + { "HDMI_GC_CONT", 5, 5, &umr_bitfield_default }, + { "HDMI_ISRC_SEND", 8, 8, &umr_bitfield_default }, + { "HDMI_ISRC_CONT", 9, 9, &umr_bitfield_default }, + { "HDMI_ISRC_LINE", 16, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_HDMI_INFOFRAME_CONTROL0[] = { + { "HDMI_AUDIO_INFO_SEND", 4, 4, &umr_bitfield_default }, + { "HDMI_AUDIO_INFO_CONT", 5, 5, &umr_bitfield_default }, + { "HDMI_MPEG_INFO_SEND", 8, 8, &umr_bitfield_default }, + { "HDMI_MPEG_INFO_CONT", 9, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_HDMI_INFOFRAME_CONTROL1[] = { + { "HDMI_AUDIO_INFO_LINE", 8, 13, &umr_bitfield_default }, + { "HDMI_MPEG_INFO_LINE", 16, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_HDMI_GENERIC_PACKET_CONTROL0[] = { + { "HDMI_GENERIC0_SEND", 0, 0, &umr_bitfield_default }, + { "HDMI_GENERIC0_CONT", 1, 1, &umr_bitfield_default }, + { "HDMI_GENERIC1_SEND", 4, 4, &umr_bitfield_default }, + { "HDMI_GENERIC1_CONT", 5, 5, &umr_bitfield_default }, + { "HDMI_GENERIC0_LINE", 16, 21, &umr_bitfield_default }, + { "HDMI_GENERIC1_LINE", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_HDMI_GC[] = { + { "HDMI_GC_AVMUTE", 0, 0, &umr_bitfield_default }, + { "HDMI_GC_AVMUTE_CONT", 2, 2, &umr_bitfield_default }, + { "HDMI_DEFAULT_PHASE", 4, 4, &umr_bitfield_default }, + { "HDMI_PACKING_PHASE", 8, 11, &umr_bitfield_default }, + { "HDMI_PACKING_PHASE_OVERRIDE", 12, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_AFMT_AUDIO_PACKET_CONTROL2[] = { + { "AFMT_AUDIO_LAYOUT_OVRD", 0, 0, &umr_bitfield_default }, + { "AFMT_AUDIO_LAYOUT_SELECT", 1, 1, &umr_bitfield_default }, + { "AFMT_AUDIO_CHANNEL_ENABLE", 8, 15, &umr_bitfield_default }, + { "AFMT_DP_AUDIO_STREAM_ID", 16, 23, &umr_bitfield_default }, + { "AFMT_HBR_ENABLE_OVRD", 24, 24, &umr_bitfield_default }, + { "AFMT_60958_OSF_OVRD", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_AFMT_ISRC1_0[] = { + { "AFMT_ISRC_STATUS", 0, 2, &umr_bitfield_default }, + { "AFMT_ISRC_CONTINUE", 6, 6, &umr_bitfield_default }, + { "AFMT_ISRC_VALID", 7, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_AFMT_ISRC1_1[] = { + { "AFMT_UPC_EAN_ISRC0", 0, 7, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC1", 8, 15, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC2", 16, 23, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC3", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_AFMT_ISRC1_2[] = { + { "AFMT_UPC_EAN_ISRC4", 0, 7, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC5", 8, 15, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC6", 16, 23, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC7", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_AFMT_ISRC1_3[] = { + { "AFMT_UPC_EAN_ISRC8", 0, 7, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC9", 8, 15, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC10", 16, 23, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC11", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_AFMT_ISRC1_4[] = { + { "AFMT_UPC_EAN_ISRC12", 0, 7, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC13", 8, 15, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC14", 16, 23, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC15", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_AFMT_ISRC2_0[] = { + { "AFMT_UPC_EAN_ISRC16", 0, 7, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC17", 8, 15, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC18", 16, 23, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC19", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_AFMT_ISRC2_1[] = { + { "AFMT_UPC_EAN_ISRC20", 0, 7, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC21", 8, 15, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC22", 16, 23, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC23", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_AFMT_ISRC2_2[] = { + { "AFMT_UPC_EAN_ISRC24", 0, 7, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC25", 8, 15, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC26", 16, 23, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC27", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_AFMT_ISRC2_3[] = { + { "AFMT_UPC_EAN_ISRC28", 0, 7, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC29", 8, 15, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC30", 16, 23, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC31", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_HDMI_GENERIC_PACKET_CONTROL2[] = { + { "HDMI_GENERIC4_SEND", 0, 0, &umr_bitfield_default }, + { "HDMI_GENERIC4_CONT", 1, 1, &umr_bitfield_default }, + { "HDMI_GENERIC5_SEND", 4, 4, &umr_bitfield_default }, + { "HDMI_GENERIC5_CONT", 5, 5, &umr_bitfield_default }, + { "HDMI_GENERIC4_LINE", 16, 21, &umr_bitfield_default }, + { "HDMI_GENERIC5_LINE", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_HDMI_GENERIC_PACKET_CONTROL3[] = { + { "HDMI_GENERIC6_SEND", 0, 0, &umr_bitfield_default }, + { "HDMI_GENERIC6_CONT", 1, 1, &umr_bitfield_default }, + { "HDMI_GENERIC7_SEND", 4, 4, &umr_bitfield_default }, + { "HDMI_GENERIC7_CONT", 5, 5, &umr_bitfield_default }, + { "HDMI_GENERIC6_LINE", 16, 21, &umr_bitfield_default }, + { "HDMI_GENERIC7_LINE", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_HDMI_DB_CONTROL[] = { + { "HDMI_DB_PENDING", 0, 0, &umr_bitfield_default }, + { "HDMI_DB_TAKEN", 4, 4, &umr_bitfield_default }, + { "HDMI_DB_TAKEN_CLR", 5, 5, &umr_bitfield_default }, + { "HDMI_DB_LOCK", 8, 8, &umr_bitfield_default }, + { "HDMI_DB_DISABLE", 12, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_AFMT_MPEG_INFO0[] = { + { "AFMT_MPEG_INFO_CHECKSUM", 0, 7, &umr_bitfield_default }, + { "AFMT_MPEG_INFO_MB0", 8, 15, &umr_bitfield_default }, + { "AFMT_MPEG_INFO_MB1", 16, 23, &umr_bitfield_default }, + { "AFMT_MPEG_INFO_MB2", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_AFMT_MPEG_INFO1[] = { + { "AFMT_MPEG_INFO_MB3", 0, 7, &umr_bitfield_default }, + { "AFMT_MPEG_INFO_MF", 8, 9, &umr_bitfield_default }, + { "AFMT_MPEG_INFO_FR", 12, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_AFMT_GENERIC_HDR[] = { + { "AFMT_GENERIC_HB0", 0, 7, &umr_bitfield_default }, + { "AFMT_GENERIC_HB1", 8, 15, &umr_bitfield_default }, + { "AFMT_GENERIC_HB2", 16, 23, &umr_bitfield_default }, + { "AFMT_GENERIC_HB3", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_AFMT_GENERIC_0[] = { + { "AFMT_GENERIC_BYTE0", 0, 7, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE1", 8, 15, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE2", 16, 23, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE3", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_AFMT_GENERIC_1[] = { + { "AFMT_GENERIC_BYTE4", 0, 7, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE5", 8, 15, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE6", 16, 23, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE7", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_AFMT_GENERIC_2[] = { + { "AFMT_GENERIC_BYTE8", 0, 7, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE9", 8, 15, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE10", 16, 23, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE11", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_AFMT_GENERIC_3[] = { + { "AFMT_GENERIC_BYTE12", 0, 7, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE13", 8, 15, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE14", 16, 23, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE15", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_AFMT_GENERIC_4[] = { + { "AFMT_GENERIC_BYTE16", 0, 7, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE17", 8, 15, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE18", 16, 23, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE19", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_AFMT_GENERIC_5[] = { + { "AFMT_GENERIC_BYTE20", 0, 7, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE21", 8, 15, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE22", 16, 23, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE23", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_AFMT_GENERIC_6[] = { + { "AFMT_GENERIC_BYTE24", 0, 7, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE25", 8, 15, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE26", 16, 23, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE27", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_AFMT_GENERIC_7[] = { + { "AFMT_GENERIC_BYTE28", 0, 7, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE29", 8, 15, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE30", 16, 23, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE31", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_HDMI_GENERIC_PACKET_CONTROL1[] = { + { "HDMI_GENERIC2_SEND", 0, 0, &umr_bitfield_default }, + { "HDMI_GENERIC2_CONT", 1, 1, &umr_bitfield_default }, + { "HDMI_GENERIC3_SEND", 4, 4, &umr_bitfield_default }, + { "HDMI_GENERIC3_CONT", 5, 5, &umr_bitfield_default }, + { "HDMI_GENERIC2_LINE", 16, 21, &umr_bitfield_default }, + { "HDMI_GENERIC3_LINE", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_HDMI_ACR_32_0[] = { + { "HDMI_ACR_CTS_32", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_HDMI_ACR_32_1[] = { + { "HDMI_ACR_N_32", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_HDMI_ACR_44_0[] = { + { "HDMI_ACR_CTS_44", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_HDMI_ACR_44_1[] = { + { "HDMI_ACR_N_44", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_HDMI_ACR_48_0[] = { + { "HDMI_ACR_CTS_48", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_HDMI_ACR_48_1[] = { + { "HDMI_ACR_N_48", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_HDMI_ACR_STATUS_0[] = { + { "HDMI_ACR_CTS", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_HDMI_ACR_STATUS_1[] = { + { "HDMI_ACR_N", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_AFMT_AUDIO_INFO0[] = { + { "AFMT_AUDIO_INFO_CHECKSUM", 0, 7, &umr_bitfield_default }, + { "AFMT_AUDIO_INFO_CC", 8, 10, &umr_bitfield_default }, + { "AFMT_AUDIO_INFO_CT", 11, 14, &umr_bitfield_default }, + { "AFMT_AUDIO_INFO_CHECKSUM_OFFSET", 16, 23, &umr_bitfield_default }, + { "AFMT_AUDIO_INFO_CXT", 24, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_AFMT_AUDIO_INFO1[] = { + { "AFMT_AUDIO_INFO_CA", 0, 7, &umr_bitfield_default }, + { "AFMT_AUDIO_INFO_LSV", 11, 14, &umr_bitfield_default }, + { "AFMT_AUDIO_INFO_DM_INH", 15, 15, &umr_bitfield_default }, + { "AFMT_AUDIO_INFO_LFEPBL", 16, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_AFMT_60958_0[] = { + { "AFMT_60958_CS_A", 0, 0, &umr_bitfield_default }, + { "AFMT_60958_CS_B", 1, 1, &umr_bitfield_default }, + { "AFMT_60958_CS_C", 2, 2, &umr_bitfield_default }, + { "AFMT_60958_CS_D", 3, 5, &umr_bitfield_default }, + { "AFMT_60958_CS_MODE", 6, 7, &umr_bitfield_default }, + { "AFMT_60958_CS_CATEGORY_CODE", 8, 15, &umr_bitfield_default }, + { "AFMT_60958_CS_SOURCE_NUMBER", 16, 19, &umr_bitfield_default }, + { "AFMT_60958_CS_CHANNEL_NUMBER_L", 20, 23, &umr_bitfield_default }, + { "AFMT_60958_CS_SAMPLING_FREQUENCY", 24, 27, &umr_bitfield_default }, + { "AFMT_60958_CS_CLOCK_ACCURACY", 28, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_AFMT_60958_1[] = { + { "AFMT_60958_CS_WORD_LENGTH", 0, 3, &umr_bitfield_default }, + { "AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY", 4, 7, &umr_bitfield_default }, + { "AFMT_60958_VALID_L", 16, 16, &umr_bitfield_default }, + { "AFMT_60958_VALID_R", 18, 18, &umr_bitfield_default }, + { "AFMT_60958_CS_CHANNEL_NUMBER_R", 20, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_AFMT_AUDIO_CRC_CONTROL[] = { + { "AFMT_AUDIO_CRC_EN", 0, 0, &umr_bitfield_default }, + { "AFMT_AUDIO_CRC_CONT", 4, 4, &umr_bitfield_default }, + { "AFMT_AUDIO_CRC_SOURCE", 8, 8, &umr_bitfield_default }, + { "AFMT_AUDIO_CRC_CH_SEL", 12, 15, &umr_bitfield_default }, + { "AFMT_AUDIO_CRC_COUNT", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_AFMT_RAMP_CONTROL0[] = { + { "AFMT_RAMP_MAX_COUNT", 0, 23, &umr_bitfield_default }, + { "AFMT_RAMP_DATA_SIGN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_AFMT_RAMP_CONTROL1[] = { + { "AFMT_RAMP_MIN_COUNT", 0, 23, &umr_bitfield_default }, + { "AFMT_AUDIO_TEST_CH_DISABLE", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_AFMT_RAMP_CONTROL2[] = { + { "AFMT_RAMP_INC_COUNT", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_AFMT_RAMP_CONTROL3[] = { + { "AFMT_RAMP_DEC_COUNT", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_AFMT_60958_2[] = { + { "AFMT_60958_CS_CHANNEL_NUMBER_2", 0, 3, &umr_bitfield_default }, + { "AFMT_60958_CS_CHANNEL_NUMBER_3", 4, 7, &umr_bitfield_default }, + { "AFMT_60958_CS_CHANNEL_NUMBER_4", 8, 11, &umr_bitfield_default }, + { "AFMT_60958_CS_CHANNEL_NUMBER_5", 12, 15, &umr_bitfield_default }, + { "AFMT_60958_CS_CHANNEL_NUMBER_6", 16, 19, &umr_bitfield_default }, + { "AFMT_60958_CS_CHANNEL_NUMBER_7", 20, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_AFMT_AUDIO_CRC_RESULT[] = { + { "AFMT_AUDIO_CRC_DONE", 0, 0, &umr_bitfield_default }, + { "AFMT_AUDIO_CRC", 8, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_AFMT_STATUS[] = { + { "AFMT_AUDIO_ENABLE", 4, 4, &umr_bitfield_default }, + { "AFMT_AZ_HBR_ENABLE", 8, 8, &umr_bitfield_default }, + { "AFMT_AUDIO_FIFO_OVERFLOW", 24, 24, &umr_bitfield_default }, + { "AFMT_AZ_AUDIO_ENABLE_CHG", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_AFMT_AUDIO_PACKET_CONTROL[] = { + { "AFMT_AUDIO_SAMPLE_SEND", 0, 0, &umr_bitfield_default }, + { "AFMT_RESET_FIFO_WHEN_AUDIO_DIS", 11, 11, &umr_bitfield_default }, + { "AFMT_AUDIO_TEST_EN", 12, 12, &umr_bitfield_default }, + { "AFMT_AUDIO_TEST_MODE", 14, 14, &umr_bitfield_default }, + { "AFMT_AUDIO_FIFO_OVERFLOW_ACK", 23, 23, &umr_bitfield_default }, + { "AFMT_AUDIO_CHANNEL_SWAP", 24, 24, &umr_bitfield_default }, + { "AFMT_60958_CS_UPDATE", 26, 26, &umr_bitfield_default }, + { "AFMT_AZ_AUDIO_ENABLE_CHG_ACK", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_AFMT_VBI_PACKET_CONTROL[] = { + { "AFMT_GENERIC_LOCK_STATUS", 8, 8, &umr_bitfield_default }, + { "AFMT_GENERIC_CONFLICT", 16, 16, &umr_bitfield_default }, + { "AFMT_GENERIC_CONFLICT_CLR", 17, 17, &umr_bitfield_default }, + { "AFMT_GENERIC_INDEX", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_AFMT_INFOFRAME_CONTROL0[] = { + { "AFMT_AUDIO_INFO_SOURCE", 6, 6, &umr_bitfield_default }, + { "AFMT_AUDIO_INFO_UPDATE", 7, 7, &umr_bitfield_default }, + { "AFMT_MPEG_INFO_UPDATE", 10, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_AFMT_AUDIO_SRC_CONTROL[] = { + { "AFMT_AUDIO_SRC_SELECT", 0, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_DIG_BE_CNTL[] = { + { "DIG_DUAL_LINK_ENABLE", 0, 0, &umr_bitfield_default }, + { "DIG_SWAP", 1, 1, &umr_bitfield_default }, + { "DIG_FE_SOURCE_SELECT", 8, 14, &umr_bitfield_default }, + { "DIG_MODE", 16, 18, &umr_bitfield_default }, + { "DIG_HPD_SELECT", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_DIG_BE_EN_CNTL[] = { + { "DIG_ENABLE", 0, 0, &umr_bitfield_default }, + { "DIG_SYMCLK_BE_ON", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_TMDS_CNTL[] = { + { "TMDS_SYNC_PHASE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_TMDS_CONTROL_CHAR[] = { + { "TMDS_CONTROL_CHAR0_OUT_EN", 0, 0, &umr_bitfield_default }, + { "TMDS_CONTROL_CHAR1_OUT_EN", 1, 1, &umr_bitfield_default }, + { "TMDS_CONTROL_CHAR2_OUT_EN", 2, 2, &umr_bitfield_default }, + { "TMDS_CONTROL_CHAR3_OUT_EN", 3, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_TMDS_CONTROL0_FEEDBACK[] = { + { "TMDS_CONTROL0_FEEDBACK_SELECT", 0, 1, &umr_bitfield_default }, + { "TMDS_CONTROL0_FEEDBACK_DELAY", 8, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_TMDS_STEREOSYNC_CTL_SEL[] = { + { "TMDS_STEREOSYNC_CTL_SEL", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1[] = { + { "TMDS_SYNC_CHAR_PATTERN0", 0, 9, &umr_bitfield_default }, + { "TMDS_SYNC_CHAR_PATTERN1", 16, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3[] = { + { "TMDS_SYNC_CHAR_PATTERN2", 0, 9, &umr_bitfield_default }, + { "TMDS_SYNC_CHAR_PATTERN3", 16, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_TMDS_CTL_BITS[] = { + { "TMDS_CTL0", 0, 0, &umr_bitfield_default }, + { "TMDS_CTL1", 8, 8, &umr_bitfield_default }, + { "TMDS_CTL2", 16, 16, &umr_bitfield_default }, + { "TMDS_CTL3", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_TMDS_DCBALANCER_CONTROL[] = { + { "TMDS_DCBALANCER_EN", 0, 0, &umr_bitfield_default }, + { "TMDS_DCBALANCER_TEST_EN", 8, 8, &umr_bitfield_default }, + { "TMDS_DCBALANCER_TEST_IN", 16, 19, &umr_bitfield_default }, + { "TMDS_DCBALANCER_FORCE", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_TMDS_CTL0_1_GEN_CNTL[] = { + { "TMDS_CTL0_DATA_SEL", 0, 3, &umr_bitfield_default }, + { "TMDS_CTL0_DATA_DELAY", 4, 6, &umr_bitfield_default }, + { "TMDS_CTL0_DATA_INVERT", 7, 7, &umr_bitfield_default }, + { "TMDS_CTL0_DATA_MODULATION", 8, 9, &umr_bitfield_default }, + { "TMDS_CTL0_USE_FEEDBACK_PATH", 10, 10, &umr_bitfield_default }, + { "TMDS_CTL0_FB_SYNC_CONT", 11, 11, &umr_bitfield_default }, + { "TMDS_CTL0_PATTERN_OUT_EN", 12, 12, &umr_bitfield_default }, + { "TMDS_CTL1_DATA_SEL", 16, 19, &umr_bitfield_default }, + { "TMDS_CTL1_DATA_DELAY", 20, 22, &umr_bitfield_default }, + { "TMDS_CTL1_DATA_INVERT", 23, 23, &umr_bitfield_default }, + { "TMDS_CTL1_DATA_MODULATION", 24, 25, &umr_bitfield_default }, + { "TMDS_CTL1_USE_FEEDBACK_PATH", 26, 26, &umr_bitfield_default }, + { "TMDS_CTL1_FB_SYNC_CONT", 27, 27, &umr_bitfield_default }, + { "TMDS_CTL1_PATTERN_OUT_EN", 28, 28, &umr_bitfield_default }, + { "TMDS_2BIT_COUNTER_EN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_TMDS_CTL2_3_GEN_CNTL[] = { + { "TMDS_CTL2_DATA_SEL", 0, 3, &umr_bitfield_default }, + { "TMDS_CTL2_DATA_DELAY", 4, 6, &umr_bitfield_default }, + { "TMDS_CTL2_DATA_INVERT", 7, 7, &umr_bitfield_default }, + { "TMDS_CTL2_DATA_MODULATION", 8, 9, &umr_bitfield_default }, + { "TMDS_CTL2_USE_FEEDBACK_PATH", 10, 10, &umr_bitfield_default }, + { "TMDS_CTL2_FB_SYNC_CONT", 11, 11, &umr_bitfield_default }, + { "TMDS_CTL2_PATTERN_OUT_EN", 12, 12, &umr_bitfield_default }, + { "TMDS_CTL3_DATA_SEL", 16, 19, &umr_bitfield_default }, + { "TMDS_CTL3_DATA_DELAY", 20, 22, &umr_bitfield_default }, + { "TMDS_CTL3_DATA_INVERT", 23, 23, &umr_bitfield_default }, + { "TMDS_CTL3_DATA_MODULATION", 24, 25, &umr_bitfield_default }, + { "TMDS_CTL3_USE_FEEDBACK_PATH", 26, 26, &umr_bitfield_default }, + { "TMDS_CTL3_FB_SYNC_CONT", 27, 27, &umr_bitfield_default }, + { "TMDS_CTL3_PATTERN_OUT_EN", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_DIG_VERSION[] = { + { "DIG_TYPE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_DIG_LANE_ENABLE[] = { + { "DIG_LANE0EN", 0, 0, &umr_bitfield_default }, + { "DIG_LANE1EN", 1, 1, &umr_bitfield_default }, + { "DIG_LANE2EN", 2, 2, &umr_bitfield_default }, + { "DIG_LANE3EN", 3, 3, &umr_bitfield_default }, + { "DIG_CLK_EN", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_AFMT_CNTL[] = { + { "AFMT_AUDIO_CLOCK_EN", 0, 0, &umr_bitfield_default }, + { "AFMT_AUDIO_CLOCK_ON", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG5_AFMT_VBI_PACKET_CONTROL1[] = { + { "AFMT_GENERIC0_FRAME_UPDATE", 0, 0, &umr_bitfield_default }, + { "AFMT_GENERIC0_FRAME_UPDATE_PENDING", 1, 1, &umr_bitfield_default }, + { "AFMT_GENERIC0_IMMEDIATE_UPDATE", 2, 2, &umr_bitfield_default }, + { "AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING", 3, 3, &umr_bitfield_default }, + { "AFMT_GENERIC1_FRAME_UPDATE", 4, 4, &umr_bitfield_default }, + { "AFMT_GENERIC1_FRAME_UPDATE_PENDING", 5, 5, &umr_bitfield_default }, + { "AFMT_GENERIC1_IMMEDIATE_UPDATE", 6, 6, &umr_bitfield_default }, + { "AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING", 7, 7, &umr_bitfield_default }, + { "AFMT_GENERIC2_FRAME_UPDATE", 8, 8, &umr_bitfield_default }, + { "AFMT_GENERIC2_FRAME_UPDATE_PENDING", 9, 9, &umr_bitfield_default }, + { "AFMT_GENERIC2_IMMEDIATE_UPDATE", 10, 10, &umr_bitfield_default }, + { "AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING", 11, 11, &umr_bitfield_default }, + { "AFMT_GENERIC3_FRAME_UPDATE", 12, 12, &umr_bitfield_default }, + { "AFMT_GENERIC3_FRAME_UPDATE_PENDING", 13, 13, &umr_bitfield_default }, + { "AFMT_GENERIC3_IMMEDIATE_UPDATE", 14, 14, &umr_bitfield_default }, + { "AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING", 15, 15, &umr_bitfield_default }, + { "AFMT_GENERIC4_FRAME_UPDATE", 16, 16, &umr_bitfield_default }, + { "AFMT_GENERIC4_FRAME_UPDATE_PENDING", 17, 17, &umr_bitfield_default }, + { "AFMT_GENERIC4_IMMEDIATE_UPDATE", 18, 18, &umr_bitfield_default }, + { "AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING", 19, 19, &umr_bitfield_default }, + { "AFMT_GENERIC5_FRAME_UPDATE", 20, 20, &umr_bitfield_default }, + { "AFMT_GENERIC5_FRAME_UPDATE_PENDING", 21, 21, &umr_bitfield_default }, + { "AFMT_GENERIC5_IMMEDIATE_UPDATE", 22, 22, &umr_bitfield_default }, + { "AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING", 23, 23, &umr_bitfield_default }, + { "AFMT_GENERIC6_FRAME_UPDATE", 24, 24, &umr_bitfield_default }, + { "AFMT_GENERIC6_FRAME_UPDATE_PENDING", 25, 25, &umr_bitfield_default }, + { "AFMT_GENERIC6_IMMEDIATE_UPDATE", 26, 26, &umr_bitfield_default }, + { "AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING", 27, 27, &umr_bitfield_default }, + { "AFMT_GENERIC7_FRAME_UPDATE", 28, 28, &umr_bitfield_default }, + { "AFMT_GENERIC7_FRAME_UPDATE_PENDING", 29, 29, &umr_bitfield_default }, + { "AFMT_GENERIC7_IMMEDIATE_UPDATE", 30, 30, &umr_bitfield_default }, + { "AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_LINK_CNTL[] = { + { "DP_LINK_TRAINING_COMPLETE", 4, 4, &umr_bitfield_default }, + { "DP_LINK_STATUS", 8, 8, &umr_bitfield_default }, + { "DP_EMBEDDED_PANEL_MODE", 17, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_PIXEL_FORMAT[] = { + { "DP_PIXEL_ENCODING", 0, 2, &umr_bitfield_default }, + { "DP_COMPONENT_DEPTH", 24, 26, &umr_bitfield_default }, + { "DP_PIXEL_COMBINE", 28, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_MSA_COLORIMETRY[] = { + { "DP_MSA_MISC0", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_CONFIG[] = { + { "DP_UDI_LANES", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_VID_STREAM_CNTL[] = { + { "DP_VID_STREAM_ENABLE", 0, 0, &umr_bitfield_default }, + { "DP_VID_STREAM_DIS_DEFER", 8, 9, &umr_bitfield_default }, + { "DP_VID_STREAM_STATUS", 16, 16, &umr_bitfield_default }, + { "DP_VID_STREAM_CHANGE_KEEPOUT", 20, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_STEER_FIFO[] = { + { "DP_STEER_FIFO_RESET", 0, 0, &umr_bitfield_default }, + { "DP_STEER_OVERFLOW_FLAG", 4, 4, &umr_bitfield_default }, + { "DP_STEER_OVERFLOW_INT", 5, 5, &umr_bitfield_default }, + { "DP_STEER_OVERFLOW_ACK", 6, 6, &umr_bitfield_default }, + { "DP_STEER_OVERFLOW_MASK", 7, 7, &umr_bitfield_default }, + { "DP_TU_OVERFLOW_FLAG", 8, 8, &umr_bitfield_default }, + { "DP_TU_OVERFLOW_ACK", 12, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_MSA_MISC[] = { + { "DP_MSA_MISC1", 0, 7, &umr_bitfield_default }, + { "DP_MSA_MISC2", 8, 15, &umr_bitfield_default }, + { "DP_MSA_MISC3", 16, 23, &umr_bitfield_default }, + { "DP_MSA_MISC4", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_VID_TIMING[] = { + { "DP_VID_M_N_DOUBLE_BUFFER_MODE", 4, 4, &umr_bitfield_default }, + { "DP_VID_M_N_GEN_EN", 8, 8, &umr_bitfield_default }, + { "DP_VID_N_MUL", 10, 11, &umr_bitfield_default }, + { "DP_VID_M_DIV", 12, 13, &umr_bitfield_default }, + { "DP_VID_N_DIV", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_VID_N[] = { + { "DP_VID_N", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_VID_M[] = { + { "DP_VID_M", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_LINK_FRAMING_CNTL[] = { + { "DP_IDLE_BS_INTERVAL", 0, 17, &umr_bitfield_default }, + { "DP_VBID_DISABLE", 24, 24, &umr_bitfield_default }, + { "DP_VID_ENHANCED_FRAME_MODE", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_HBR2_EYE_PATTERN[] = { + { "DP_HBR2_EYE_PATTERN_ENABLE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_VID_MSA_VBID[] = { + { "DP_VID_MSA_LOCATION", 0, 11, &umr_bitfield_default }, + { "DP_VID_VBID_FIELD_POL", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_VID_INTERRUPT_CNTL[] = { + { "DP_VID_STREAM_DISABLE_INT", 0, 0, &umr_bitfield_default }, + { "DP_VID_STREAM_DISABLE_ACK", 1, 1, &umr_bitfield_default }, + { "DP_VID_STREAM_DISABLE_MASK", 2, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_DPHY_CNTL[] = { + { "DPHY_ATEST_SEL_LANE0", 0, 0, &umr_bitfield_default }, + { "DPHY_ATEST_SEL_LANE1", 1, 1, &umr_bitfield_default }, + { "DPHY_ATEST_SEL_LANE2", 2, 2, &umr_bitfield_default }, + { "DPHY_ATEST_SEL_LANE3", 3, 3, &umr_bitfield_default }, + { "DPHY_BYPASS", 16, 16, &umr_bitfield_default }, + { "DPHY_SKEW_BYPASS", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_DPHY_TRAINING_PATTERN_SEL[] = { + { "DPHY_TRAINING_PATTERN_SEL", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_DPHY_SYM0[] = { + { "DPHY_SYM1", 0, 9, &umr_bitfield_default }, + { "DPHY_SYM2", 10, 19, &umr_bitfield_default }, + { "DPHY_SYM3", 20, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_DPHY_SYM1[] = { + { "DPHY_SYM4", 0, 9, &umr_bitfield_default }, + { "DPHY_SYM5", 10, 19, &umr_bitfield_default }, + { "DPHY_SYM6", 20, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_DPHY_SYM2[] = { + { "DPHY_SYM7", 0, 9, &umr_bitfield_default }, + { "DPHY_SYM8", 10, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_DPHY_8B10B_CNTL[] = { + { "DPHY_8B10B_RESET", 8, 8, &umr_bitfield_default }, + { "DPHY_8B10B_EXT_DISP", 16, 16, &umr_bitfield_default }, + { "DPHY_8B10B_CUR_DISP", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_DPHY_PRBS_CNTL[] = { + { "DPHY_PRBS_EN", 0, 0, &umr_bitfield_default }, + { "DPHY_PRBS_SEL", 4, 5, &umr_bitfield_default }, + { "DPHY_PRBS_SEED", 8, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_DPHY_SCRAM_CNTL[] = { + { "DPHY_SCRAMBLER_DIS", 0, 0, &umr_bitfield_default }, + { "DPHY_SCRAMBLER_ADVANCE", 4, 4, &umr_bitfield_default }, + { "DPHY_SCRAMBLER_BS_COUNT", 8, 17, &umr_bitfield_default }, + { "DPHY_SCRAMBLER_KCODE", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_DPHY_CRC_EN[] = { + { "DPHY_CRC_EN", 0, 0, &umr_bitfield_default }, + { "DPHY_CRC_CONT_EN", 4, 4, &umr_bitfield_default }, + { "DPHY_CRC_RESULT_VALID", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_DPHY_CRC_CNTL[] = { + { "DPHY_CRC_FIELD", 0, 0, &umr_bitfield_default }, + { "DPHY_CRC_SEL", 4, 5, &umr_bitfield_default }, + { "DPHY_CRC_MASK", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_DPHY_CRC_RESULT[] = { + { "DPHY_CRC_RESULT", 0, 7, &umr_bitfield_default }, + { "DPHY_CRC_RESULT1", 8, 15, &umr_bitfield_default }, + { "DPHY_CRC_RESULT2", 16, 23, &umr_bitfield_default }, + { "DPHY_CRC_RESULT3", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_DPHY_CRC_MST_CNTL[] = { + { "DPHY_CRC_MST_FIRST_SLOT", 0, 5, &umr_bitfield_default }, + { "DPHY_CRC_MST_LAST_SLOT", 8, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_DPHY_CRC_MST_STATUS[] = { + { "DPHY_CRC_MST_PHASE_LOCK", 0, 0, &umr_bitfield_default }, + { "DPHY_CRC_MST_PHASE_ERROR", 8, 8, &umr_bitfield_default }, + { "DPHY_CRC_MST_PHASE_ERROR_ACK", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_DPHY_FAST_TRAINING[] = { + { "DPHY_RX_FAST_TRAINING_CAPABLE", 0, 0, &umr_bitfield_default }, + { "DPHY_SW_FAST_TRAINING_START", 1, 1, &umr_bitfield_default }, + { "DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN", 2, 2, &umr_bitfield_default }, + { "DPHY_FAST_TRAINING_TP1_TIME", 8, 19, &umr_bitfield_default }, + { "DPHY_FAST_TRAINING_TP2_TIME", 20, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_DPHY_FAST_TRAINING_STATUS[] = { + { "DPHY_FAST_TRAINING_STATE", 0, 2, &umr_bitfield_default }, + { "DPHY_FAST_TRAINING_COMPLETE_OCCURRED", 4, 4, &umr_bitfield_default }, + { "DPHY_FAST_TRAINING_COMPLETE_MASK", 8, 8, &umr_bitfield_default }, + { "DPHY_FAST_TRAINING_COMPLETE_ACK", 12, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_SEC_CNTL[] = { + { "DP_SEC_STREAM_ENABLE", 0, 0, &umr_bitfield_default }, + { "DP_SEC_ASP_ENABLE", 4, 4, &umr_bitfield_default }, + { "DP_SEC_ATP_ENABLE", 8, 8, &umr_bitfield_default }, + { "DP_SEC_AIP_ENABLE", 12, 12, &umr_bitfield_default }, + { "DP_SEC_ACM_ENABLE", 16, 16, &umr_bitfield_default }, + { "DP_SEC_GSP0_ENABLE", 20, 20, &umr_bitfield_default }, + { "DP_SEC_GSP1_ENABLE", 21, 21, &umr_bitfield_default }, + { "DP_SEC_GSP2_ENABLE", 22, 22, &umr_bitfield_default }, + { "DP_SEC_GSP3_ENABLE", 23, 23, &umr_bitfield_default }, + { "DP_SEC_GSP4_ENABLE", 24, 24, &umr_bitfield_default }, + { "DP_SEC_GSP5_ENABLE", 25, 25, &umr_bitfield_default }, + { "DP_SEC_GSP6_ENABLE", 26, 26, &umr_bitfield_default }, + { "DP_SEC_GSP7_ENABLE", 27, 27, &umr_bitfield_default }, + { "DP_SEC_MPG_ENABLE", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_SEC_CNTL1[] = { + { "DP_SEC_ISRC_ENABLE", 0, 0, &umr_bitfield_default }, + { "DP_SEC_GSP0_PRIORITY", 4, 4, &umr_bitfield_default }, + { "DP_SEC_GSP0_SEND", 5, 5, &umr_bitfield_default }, + { "DP_SEC_GSP0_SEND_PENDING", 6, 6, &umr_bitfield_default }, + { "DP_SEC_GSP0_SEND_DEADLINE_MISSED", 7, 7, &umr_bitfield_default }, + { "DP_SEC_GSP0_SEND_ANY_LINE", 8, 8, &umr_bitfield_default }, + { "DP_SEC_GSP0_LINE_NUM", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_SEC_FRAMING1[] = { + { "DP_SEC_FRAME_START_LOCATION", 0, 11, &umr_bitfield_default }, + { "DP_SEC_VBLANK_TRANSMIT_WIDTH", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_SEC_FRAMING2[] = { + { "DP_SEC_START_POSITION", 0, 15, &umr_bitfield_default }, + { "DP_SEC_HBLANK_TRANSMIT_WIDTH", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_SEC_FRAMING3[] = { + { "DP_SEC_IDLE_FRAME_SIZE", 0, 13, &umr_bitfield_default }, + { "DP_SEC_IDLE_TRANSMIT_WIDTH", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_SEC_FRAMING4[] = { + { "DP_SEC_COLLISION_STATUS", 20, 20, &umr_bitfield_default }, + { "DP_SEC_COLLISION_ACK", 24, 24, &umr_bitfield_default }, + { "DP_SEC_AUDIO_MUTE", 28, 28, &umr_bitfield_default }, + { "DP_SEC_AUDIO_MUTE_STATUS", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_SEC_AUD_N[] = { + { "DP_SEC_AUD_N", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_SEC_AUD_N_READBACK[] = { + { "DP_SEC_AUD_N_READBACK", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_SEC_AUD_M[] = { + { "DP_SEC_AUD_M", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_SEC_AUD_M_READBACK[] = { + { "DP_SEC_AUD_M_READBACK", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_SEC_TIMESTAMP[] = { + { "DP_SEC_TIMESTAMP_MODE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_SEC_PACKET_CNTL[] = { + { "DP_SEC_ASP_CODING_TYPE", 1, 3, &umr_bitfield_default }, + { "DP_SEC_ASP_PRIORITY", 4, 4, &umr_bitfield_default }, + { "DP_SEC_VERSION", 8, 13, &umr_bitfield_default }, + { "DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_MSE_RATE_CNTL[] = { + { "DP_MSE_RATE_Y", 0, 25, &umr_bitfield_default }, + { "DP_MSE_RATE_X", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_MSE_RATE_UPDATE[] = { + { "DP_MSE_RATE_UPDATE_PENDING", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_MSE_SAT0[] = { + { "DP_MSE_SAT_SRC0", 0, 2, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT0", 8, 13, &umr_bitfield_default }, + { "DP_MSE_SAT_SRC1", 16, 18, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT1", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_MSE_SAT1[] = { + { "DP_MSE_SAT_SRC2", 0, 2, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT2", 8, 13, &umr_bitfield_default }, + { "DP_MSE_SAT_SRC3", 16, 18, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT3", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_MSE_SAT2[] = { + { "DP_MSE_SAT_SRC4", 0, 2, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT4", 8, 13, &umr_bitfield_default }, + { "DP_MSE_SAT_SRC5", 16, 18, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT5", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_MSE_SAT_UPDATE[] = { + { "DP_MSE_SAT_UPDATE", 0, 1, &umr_bitfield_default }, + { "DP_MSE_16_MTP_KEEPOUT", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_MSE_LINK_TIMING[] = { + { "DP_MSE_LINK_FRAME", 0, 9, &umr_bitfield_default }, + { "DP_MSE_LINK_LINE", 16, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_MSE_MISC_CNTL[] = { + { "DP_MSE_BLANK_CODE", 0, 0, &umr_bitfield_default }, + { "DP_MSE_TIMESTAMP_MODE", 4, 4, &umr_bitfield_default }, + { "DP_MSE_ZERO_ENCODER", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_DPHY_BS_SR_SWAP_CNTL[] = { + { "DPHY_LOAD_BS_COUNT", 0, 9, &umr_bitfield_default }, + { "DPHY_BS_SR_SWAP_DONE", 15, 15, &umr_bitfield_default }, + { "DPHY_LOAD_BS_COUNT_START", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL[] = { + { "DP_DPHY_HBR2_PATTERN_CONTROL", 0, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_MSE_SAT0_STATUS[] = { + { "DP_MSE_SAT_SRC0_STATUS", 0, 2, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT0_STATUS", 8, 13, &umr_bitfield_default }, + { "DP_MSE_SAT_SRC1_STATUS", 16, 18, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT1_STATUS", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_MSE_SAT1_STATUS[] = { + { "DP_MSE_SAT_SRC2_STATUS", 0, 2, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT2_STATUS", 8, 13, &umr_bitfield_default }, + { "DP_MSE_SAT_SRC3_STATUS", 16, 18, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT3_STATUS", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_MSE_SAT2_STATUS[] = { + { "DP_MSE_SAT_SRC4_STATUS", 0, 2, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT4_STATUS", 8, 13, &umr_bitfield_default }, + { "DP_MSE_SAT_SRC5_STATUS", 16, 18, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT5_STATUS", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_MSA_TIMING_PARAM1[] = { + { "DP_MSA_VTOTAL", 0, 15, &umr_bitfield_default }, + { "DP_MSA_HTOTAL", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_MSA_TIMING_PARAM2[] = { + { "DP_MSA_VSTART", 0, 15, &umr_bitfield_default }, + { "DP_MSA_HSTART", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_MSA_TIMING_PARAM3[] = { + { "DP_MSA_VSYNCWIDTH", 0, 14, &umr_bitfield_default }, + { "DP_MSA_VSYNCPOLARITY", 15, 15, &umr_bitfield_default }, + { "DP_MSA_HSYNCWIDTH", 16, 30, &umr_bitfield_default }, + { "DP_MSA_HSYNCPOLARITY", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_MSA_TIMING_PARAM4[] = { + { "DP_MSA_VHEIGHT", 0, 15, &umr_bitfield_default }, + { "DP_MSA_HWIDTH", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_MSO_CNTL[] = { + { "DP_MSO_NUM_OF_SSTLINK", 0, 1, &umr_bitfield_default }, + { "DP_MSO_SEC_STREAM_ENABLE", 4, 7, &umr_bitfield_default }, + { "DP_MSO_SEC_ASP_ENABLE", 8, 11, &umr_bitfield_default }, + { "DP_MSO_SEC_ATP_ENABLE", 12, 15, &umr_bitfield_default }, + { "DP_MSO_SEC_AIP_ENABLE", 16, 19, &umr_bitfield_default }, + { "DP_MSO_SEC_ACM_ENABLE", 20, 23, &umr_bitfield_default }, + { "DP_MSO_SEC_GSP0_ENABLE", 24, 27, &umr_bitfield_default }, + { "DP_MSO_SEC_GSP1_ENABLE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_MSO_CNTL1[] = { + { "DP_MSO_SEC_GSP2_ENABLE", 0, 3, &umr_bitfield_default }, + { "DP_MSO_SEC_GSP3_ENABLE", 4, 7, &umr_bitfield_default }, + { "DP_MSO_SEC_GSP4_ENABLE", 8, 11, &umr_bitfield_default }, + { "DP_MSO_SEC_GSP5_ENABLE", 12, 15, &umr_bitfield_default }, + { "DP_MSO_SEC_GSP6_ENABLE", 16, 19, &umr_bitfield_default }, + { "DP_MSO_SEC_GSP7_ENABLE", 20, 23, &umr_bitfield_default }, + { "DP_MSO_SEC_MPG_ENABLE", 24, 27, &umr_bitfield_default }, + { "DP_MSO_SEC_ISRC_ENABLE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_DSC_CNTL[] = { + { "DP_DSC_EN", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_SEC_CNTL2[] = { + { "DP_SEC_GSP1_SEND", 0, 0, &umr_bitfield_default }, + { "DP_SEC_GSP1_SEND_PENDING", 1, 1, &umr_bitfield_default }, + { "DP_SEC_GSP1_SEND_DEADLINE_MISSED", 2, 2, &umr_bitfield_default }, + { "DP_SEC_GSP1_SEND_ANY_LINE", 3, 3, &umr_bitfield_default }, + { "DP_SEC_GSP2_SEND", 4, 4, &umr_bitfield_default }, + { "DP_SEC_GSP2_SEND_PENDING", 5, 5, &umr_bitfield_default }, + { "DP_SEC_GSP2_SEND_DEADLINE_MISSED", 6, 6, &umr_bitfield_default }, + { "DP_SEC_GSP2_SEND_ANY_LINE", 7, 7, &umr_bitfield_default }, + { "DP_SEC_GSP3_SEND", 8, 8, &umr_bitfield_default }, + { "DP_SEC_GSP3_SEND_PENDING", 9, 9, &umr_bitfield_default }, + { "DP_SEC_GSP3_SEND_DEADLINE_MISSED", 10, 10, &umr_bitfield_default }, + { "DP_SEC_GSP3_SEND_ANY_LINE", 11, 11, &umr_bitfield_default }, + { "DP_SEC_GSP4_SEND", 12, 12, &umr_bitfield_default }, + { "DP_SEC_GSP4_SEND_PENDING", 13, 13, &umr_bitfield_default }, + { "DP_SEC_GSP4_SEND_DEADLINE_MISSED", 14, 14, &umr_bitfield_default }, + { "DP_SEC_GSP4_SEND_ANY_LINE", 15, 15, &umr_bitfield_default }, + { "DP_SEC_GSP5_SEND", 16, 16, &umr_bitfield_default }, + { "DP_SEC_GSP5_SEND_PENDING", 17, 17, &umr_bitfield_default }, + { "DP_SEC_GSP5_SEND_DEADLINE_MISSED", 18, 18, &umr_bitfield_default }, + { "DP_SEC_GSP5_SEND_ANY_LINE", 19, 19, &umr_bitfield_default }, + { "DP_SEC_GSP6_SEND", 20, 20, &umr_bitfield_default }, + { "DP_SEC_GSP6_SEND_PENDING", 21, 21, &umr_bitfield_default }, + { "DP_SEC_GSP6_SEND_DEADLINE_MISSED", 22, 22, &umr_bitfield_default }, + { "DP_SEC_GSP6_SEND_ANY_LINE", 23, 23, &umr_bitfield_default }, + { "DP_SEC_GSP7_SEND", 24, 24, &umr_bitfield_default }, + { "DP_SEC_GSP7_SEND_PENDING", 25, 25, &umr_bitfield_default }, + { "DP_SEC_GSP7_SEND_DEADLINE_MISSED", 26, 26, &umr_bitfield_default }, + { "DP_SEC_GSP7_SEND_ANY_LINE", 27, 27, &umr_bitfield_default }, + { "DP_SEC_GSP7_PPS", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_SEC_CNTL3[] = { + { "DP_SEC_GSP1_LINE_NUM", 0, 15, &umr_bitfield_default }, + { "DP_SEC_GSP2_LINE_NUM", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_SEC_CNTL4[] = { + { "DP_SEC_GSP3_LINE_NUM", 0, 15, &umr_bitfield_default }, + { "DP_SEC_GSP4_LINE_NUM", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_SEC_CNTL5[] = { + { "DP_SEC_GSP5_LINE_NUM", 0, 15, &umr_bitfield_default }, + { "DP_SEC_GSP6_LINE_NUM", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_SEC_CNTL6[] = { + { "DP_SEC_GSP7_LINE_NUM", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_SEC_CNTL7[] = { + { "DP_SEC_GSP0_SEND_ACTIVE", 0, 0, &umr_bitfield_default }, + { "DP_SEC_GSP1_SEND_ACTIVE", 4, 4, &umr_bitfield_default }, + { "DP_SEC_GSP2_SEND_ACTIVE", 8, 8, &umr_bitfield_default }, + { "DP_SEC_GSP3_SEND_ACTIVE", 12, 12, &umr_bitfield_default }, + { "DP_SEC_GSP4_SEND_ACTIVE", 16, 16, &umr_bitfield_default }, + { "DP_SEC_GSP5_SEND_ACTIVE", 20, 20, &umr_bitfield_default }, + { "DP_SEC_GSP6_SEND_ACTIVE", 24, 24, &umr_bitfield_default }, + { "DP_SEC_GSP7_SEND_ACTIVE", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_DB_CNTL[] = { + { "DP_DB_PENDING", 0, 0, &umr_bitfield_default }, + { "DP_DB_TAKEN", 4, 4, &umr_bitfield_default }, + { "DP_DB_TAKEN_CLR", 5, 5, &umr_bitfield_default }, + { "DP_DB_LOCK", 8, 8, &umr_bitfield_default }, + { "DP_DB_DISABLE", 12, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP5_DP_MSA_VBID_MISC[] = { + { "DP_MSA_MISC1_STEREOSYNC_OVERRIDE", 0, 1, &umr_bitfield_default }, + { "DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN", 4, 4, &umr_bitfield_default }, + { "DP_VBID1_OVERRIDE", 8, 8, &umr_bitfield_default }, + { "DP_VBID2_OVERRIDE", 9, 9, &umr_bitfield_default }, + { "DP_VBID1_OVERRIDE_EN", 12, 12, &umr_bitfield_default }, + { "DP_VBID2_OVERRIDE_EN", 13, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_DIG_FE_CNTL[] = { + { "DIG_SOURCE_SELECT", 0, 2, &umr_bitfield_default }, + { "DIG_STEREOSYNC_SELECT", 4, 6, &umr_bitfield_default }, + { "DIG_STEREOSYNC_GATE_EN", 8, 8, &umr_bitfield_default }, + { "DIG_START", 10, 10, &umr_bitfield_default }, + { "DIG_DIGITAL_BYPASS_SELECT", 12, 14, &umr_bitfield_default }, + { "DIG_SYMCLK_FE_ON", 24, 24, &umr_bitfield_default }, + { "TMDS_PIXEL_ENCODING", 28, 28, &umr_bitfield_default }, + { "TMDS_COLOR_FORMAT", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_DIG_OUTPUT_CRC_CNTL[] = { + { "DIG_OUTPUT_CRC_EN", 0, 0, &umr_bitfield_default }, + { "DIG_OUTPUT_CRC_LINK_SEL", 4, 4, &umr_bitfield_default }, + { "DIG_OUTPUT_CRC_DATA_SEL", 8, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_DIG_OUTPUT_CRC_RESULT[] = { + { "DIG_OUTPUT_CRC_RESULT", 0, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_DIG_CLOCK_PATTERN[] = { + { "DIG_CLOCK_PATTERN", 0, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_DIG_TEST_PATTERN[] = { + { "DIG_TEST_PATTERN_OUT_EN", 0, 0, &umr_bitfield_default }, + { "DIG_HALF_CLOCK_PATTERN_SEL", 1, 1, &umr_bitfield_default }, + { "DIG_RANDOM_PATTERN_OUT_EN", 4, 4, &umr_bitfield_default }, + { "DIG_RANDOM_PATTERN_RESET", 5, 5, &umr_bitfield_default }, + { "DIG_TEST_PATTERN_EXTERNAL_RESET_EN", 6, 6, &umr_bitfield_default }, + { "DIG_STATIC_TEST_PATTERN", 16, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_DIG_RANDOM_PATTERN_SEED[] = { + { "DIG_RANDOM_PATTERN_SEED", 0, 23, &umr_bitfield_default }, + { "DIG_RAN_PAT_DURING_DE_ONLY", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_DIG_FIFO_STATUS[] = { + { "DIG_FIFO_LEVEL_ERROR", 0, 0, &umr_bitfield_default }, + { "DIG_FIFO_USE_OVERWRITE_LEVEL", 1, 1, &umr_bitfield_default }, + { "DIG_FIFO_OVERWRITE_LEVEL", 2, 7, &umr_bitfield_default }, + { "DIG_FIFO_ERROR_ACK", 8, 8, &umr_bitfield_default }, + { "DIG_FIFO_CAL_AVERAGE_LEVEL", 10, 15, &umr_bitfield_default }, + { "DIG_FIFO_MAXIMUM_LEVEL", 16, 20, &umr_bitfield_default }, + { "DIG_FIFO_MINIMUM_LEVEL", 22, 25, &umr_bitfield_default }, + { "DIG_FIFO_READ_CLOCK_SRC", 26, 26, &umr_bitfield_default }, + { "DIG_FIFO_CALIBRATED", 29, 29, &umr_bitfield_default }, + { "DIG_FIFO_FORCE_RECAL_AVERAGE", 30, 30, &umr_bitfield_default }, + { "DIG_FIFO_FORCE_RECOMP_MINMAX", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_HDMI_CONTROL[] = { + { "HDMI_KEEPOUT_MODE", 0, 0, &umr_bitfield_default }, + { "HDMI_DATA_SCRAMBLE_EN", 1, 1, &umr_bitfield_default }, + { "HDMI_CLOCK_CHANNEL_RATE", 2, 2, &umr_bitfield_default }, + { "HDMI_NO_EXTRA_NULL_PACKET_FILLED", 3, 3, &umr_bitfield_default }, + { "HDMI_PACKET_GEN_VERSION", 4, 4, &umr_bitfield_default }, + { "HDMI_ERROR_ACK", 8, 8, &umr_bitfield_default }, + { "HDMI_ERROR_MASK", 9, 9, &umr_bitfield_default }, + { "HDMI_DEEP_COLOR_ENABLE", 24, 24, &umr_bitfield_default }, + { "HDMI_DEEP_COLOR_DEPTH", 28, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_HDMI_STATUS[] = { + { "HDMI_ACTIVE_AVMUTE", 0, 0, &umr_bitfield_default }, + { "HDMI_AUDIO_PACKET_ERROR", 16, 16, &umr_bitfield_default }, + { "HDMI_VBI_PACKET_ERROR", 20, 20, &umr_bitfield_default }, + { "HDMI_ERROR_INT", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_HDMI_AUDIO_PACKET_CONTROL[] = { + { "HDMI_AUDIO_DELAY_EN", 4, 5, &umr_bitfield_default }, + { "HDMI_AUDIO_PACKETS_PER_LINE", 16, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_HDMI_ACR_PACKET_CONTROL[] = { + { "HDMI_ACR_SEND", 0, 0, &umr_bitfield_default }, + { "HDMI_ACR_CONT", 1, 1, &umr_bitfield_default }, + { "HDMI_ACR_SELECT", 4, 5, &umr_bitfield_default }, + { "HDMI_ACR_SOURCE", 8, 8, &umr_bitfield_default }, + { "HDMI_ACR_AUTO_SEND", 12, 12, &umr_bitfield_default }, + { "HDMI_ACR_N_MULTIPLE", 16, 18, &umr_bitfield_default }, + { "HDMI_ACR_AUDIO_PRIORITY", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_HDMI_VBI_PACKET_CONTROL[] = { + { "HDMI_NULL_SEND", 0, 0, &umr_bitfield_default }, + { "HDMI_GC_SEND", 4, 4, &umr_bitfield_default }, + { "HDMI_GC_CONT", 5, 5, &umr_bitfield_default }, + { "HDMI_ISRC_SEND", 8, 8, &umr_bitfield_default }, + { "HDMI_ISRC_CONT", 9, 9, &umr_bitfield_default }, + { "HDMI_ISRC_LINE", 16, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_HDMI_INFOFRAME_CONTROL0[] = { + { "HDMI_AUDIO_INFO_SEND", 4, 4, &umr_bitfield_default }, + { "HDMI_AUDIO_INFO_CONT", 5, 5, &umr_bitfield_default }, + { "HDMI_MPEG_INFO_SEND", 8, 8, &umr_bitfield_default }, + { "HDMI_MPEG_INFO_CONT", 9, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_HDMI_INFOFRAME_CONTROL1[] = { + { "HDMI_AUDIO_INFO_LINE", 8, 13, &umr_bitfield_default }, + { "HDMI_MPEG_INFO_LINE", 16, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_HDMI_GENERIC_PACKET_CONTROL0[] = { + { "HDMI_GENERIC0_SEND", 0, 0, &umr_bitfield_default }, + { "HDMI_GENERIC0_CONT", 1, 1, &umr_bitfield_default }, + { "HDMI_GENERIC1_SEND", 4, 4, &umr_bitfield_default }, + { "HDMI_GENERIC1_CONT", 5, 5, &umr_bitfield_default }, + { "HDMI_GENERIC0_LINE", 16, 21, &umr_bitfield_default }, + { "HDMI_GENERIC1_LINE", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_HDMI_GC[] = { + { "HDMI_GC_AVMUTE", 0, 0, &umr_bitfield_default }, + { "HDMI_GC_AVMUTE_CONT", 2, 2, &umr_bitfield_default }, + { "HDMI_DEFAULT_PHASE", 4, 4, &umr_bitfield_default }, + { "HDMI_PACKING_PHASE", 8, 11, &umr_bitfield_default }, + { "HDMI_PACKING_PHASE_OVERRIDE", 12, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_AFMT_AUDIO_PACKET_CONTROL2[] = { + { "AFMT_AUDIO_LAYOUT_OVRD", 0, 0, &umr_bitfield_default }, + { "AFMT_AUDIO_LAYOUT_SELECT", 1, 1, &umr_bitfield_default }, + { "AFMT_AUDIO_CHANNEL_ENABLE", 8, 15, &umr_bitfield_default }, + { "AFMT_DP_AUDIO_STREAM_ID", 16, 23, &umr_bitfield_default }, + { "AFMT_HBR_ENABLE_OVRD", 24, 24, &umr_bitfield_default }, + { "AFMT_60958_OSF_OVRD", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_AFMT_ISRC1_0[] = { + { "AFMT_ISRC_STATUS", 0, 2, &umr_bitfield_default }, + { "AFMT_ISRC_CONTINUE", 6, 6, &umr_bitfield_default }, + { "AFMT_ISRC_VALID", 7, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_AFMT_ISRC1_1[] = { + { "AFMT_UPC_EAN_ISRC0", 0, 7, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC1", 8, 15, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC2", 16, 23, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC3", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_AFMT_ISRC1_2[] = { + { "AFMT_UPC_EAN_ISRC4", 0, 7, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC5", 8, 15, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC6", 16, 23, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC7", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_AFMT_ISRC1_3[] = { + { "AFMT_UPC_EAN_ISRC8", 0, 7, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC9", 8, 15, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC10", 16, 23, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC11", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_AFMT_ISRC1_4[] = { + { "AFMT_UPC_EAN_ISRC12", 0, 7, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC13", 8, 15, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC14", 16, 23, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC15", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_AFMT_ISRC2_0[] = { + { "AFMT_UPC_EAN_ISRC16", 0, 7, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC17", 8, 15, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC18", 16, 23, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC19", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_AFMT_ISRC2_1[] = { + { "AFMT_UPC_EAN_ISRC20", 0, 7, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC21", 8, 15, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC22", 16, 23, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC23", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_AFMT_ISRC2_2[] = { + { "AFMT_UPC_EAN_ISRC24", 0, 7, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC25", 8, 15, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC26", 16, 23, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC27", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_AFMT_ISRC2_3[] = { + { "AFMT_UPC_EAN_ISRC28", 0, 7, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC29", 8, 15, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC30", 16, 23, &umr_bitfield_default }, + { "AFMT_UPC_EAN_ISRC31", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_HDMI_GENERIC_PACKET_CONTROL2[] = { + { "HDMI_GENERIC4_SEND", 0, 0, &umr_bitfield_default }, + { "HDMI_GENERIC4_CONT", 1, 1, &umr_bitfield_default }, + { "HDMI_GENERIC5_SEND", 4, 4, &umr_bitfield_default }, + { "HDMI_GENERIC5_CONT", 5, 5, &umr_bitfield_default }, + { "HDMI_GENERIC4_LINE", 16, 21, &umr_bitfield_default }, + { "HDMI_GENERIC5_LINE", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_HDMI_GENERIC_PACKET_CONTROL3[] = { + { "HDMI_GENERIC6_SEND", 0, 0, &umr_bitfield_default }, + { "HDMI_GENERIC6_CONT", 1, 1, &umr_bitfield_default }, + { "HDMI_GENERIC7_SEND", 4, 4, &umr_bitfield_default }, + { "HDMI_GENERIC7_CONT", 5, 5, &umr_bitfield_default }, + { "HDMI_GENERIC6_LINE", 16, 21, &umr_bitfield_default }, + { "HDMI_GENERIC7_LINE", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_HDMI_DB_CONTROL[] = { + { "HDMI_DB_PENDING", 0, 0, &umr_bitfield_default }, + { "HDMI_DB_TAKEN", 4, 4, &umr_bitfield_default }, + { "HDMI_DB_TAKEN_CLR", 5, 5, &umr_bitfield_default }, + { "HDMI_DB_LOCK", 8, 8, &umr_bitfield_default }, + { "HDMI_DB_DISABLE", 12, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_AFMT_MPEG_INFO0[] = { + { "AFMT_MPEG_INFO_CHECKSUM", 0, 7, &umr_bitfield_default }, + { "AFMT_MPEG_INFO_MB0", 8, 15, &umr_bitfield_default }, + { "AFMT_MPEG_INFO_MB1", 16, 23, &umr_bitfield_default }, + { "AFMT_MPEG_INFO_MB2", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_AFMT_MPEG_INFO1[] = { + { "AFMT_MPEG_INFO_MB3", 0, 7, &umr_bitfield_default }, + { "AFMT_MPEG_INFO_MF", 8, 9, &umr_bitfield_default }, + { "AFMT_MPEG_INFO_FR", 12, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_AFMT_GENERIC_HDR[] = { + { "AFMT_GENERIC_HB0", 0, 7, &umr_bitfield_default }, + { "AFMT_GENERIC_HB1", 8, 15, &umr_bitfield_default }, + { "AFMT_GENERIC_HB2", 16, 23, &umr_bitfield_default }, + { "AFMT_GENERIC_HB3", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_AFMT_GENERIC_0[] = { + { "AFMT_GENERIC_BYTE0", 0, 7, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE1", 8, 15, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE2", 16, 23, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE3", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_AFMT_GENERIC_1[] = { + { "AFMT_GENERIC_BYTE4", 0, 7, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE5", 8, 15, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE6", 16, 23, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE7", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_AFMT_GENERIC_2[] = { + { "AFMT_GENERIC_BYTE8", 0, 7, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE9", 8, 15, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE10", 16, 23, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE11", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_AFMT_GENERIC_3[] = { + { "AFMT_GENERIC_BYTE12", 0, 7, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE13", 8, 15, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE14", 16, 23, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE15", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_AFMT_GENERIC_4[] = { + { "AFMT_GENERIC_BYTE16", 0, 7, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE17", 8, 15, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE18", 16, 23, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE19", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_AFMT_GENERIC_5[] = { + { "AFMT_GENERIC_BYTE20", 0, 7, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE21", 8, 15, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE22", 16, 23, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE23", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_AFMT_GENERIC_6[] = { + { "AFMT_GENERIC_BYTE24", 0, 7, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE25", 8, 15, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE26", 16, 23, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE27", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_AFMT_GENERIC_7[] = { + { "AFMT_GENERIC_BYTE28", 0, 7, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE29", 8, 15, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE30", 16, 23, &umr_bitfield_default }, + { "AFMT_GENERIC_BYTE31", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_HDMI_GENERIC_PACKET_CONTROL1[] = { + { "HDMI_GENERIC2_SEND", 0, 0, &umr_bitfield_default }, + { "HDMI_GENERIC2_CONT", 1, 1, &umr_bitfield_default }, + { "HDMI_GENERIC3_SEND", 4, 4, &umr_bitfield_default }, + { "HDMI_GENERIC3_CONT", 5, 5, &umr_bitfield_default }, + { "HDMI_GENERIC2_LINE", 16, 21, &umr_bitfield_default }, + { "HDMI_GENERIC3_LINE", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_HDMI_ACR_32_0[] = { + { "HDMI_ACR_CTS_32", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_HDMI_ACR_32_1[] = { + { "HDMI_ACR_N_32", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_HDMI_ACR_44_0[] = { + { "HDMI_ACR_CTS_44", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_HDMI_ACR_44_1[] = { + { "HDMI_ACR_N_44", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_HDMI_ACR_48_0[] = { + { "HDMI_ACR_CTS_48", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_HDMI_ACR_48_1[] = { + { "HDMI_ACR_N_48", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_HDMI_ACR_STATUS_0[] = { + { "HDMI_ACR_CTS", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_HDMI_ACR_STATUS_1[] = { + { "HDMI_ACR_N", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_AFMT_AUDIO_INFO0[] = { + { "AFMT_AUDIO_INFO_CHECKSUM", 0, 7, &umr_bitfield_default }, + { "AFMT_AUDIO_INFO_CC", 8, 10, &umr_bitfield_default }, + { "AFMT_AUDIO_INFO_CT", 11, 14, &umr_bitfield_default }, + { "AFMT_AUDIO_INFO_CHECKSUM_OFFSET", 16, 23, &umr_bitfield_default }, + { "AFMT_AUDIO_INFO_CXT", 24, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_AFMT_AUDIO_INFO1[] = { + { "AFMT_AUDIO_INFO_CA", 0, 7, &umr_bitfield_default }, + { "AFMT_AUDIO_INFO_LSV", 11, 14, &umr_bitfield_default }, + { "AFMT_AUDIO_INFO_DM_INH", 15, 15, &umr_bitfield_default }, + { "AFMT_AUDIO_INFO_LFEPBL", 16, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_AFMT_60958_0[] = { + { "AFMT_60958_CS_A", 0, 0, &umr_bitfield_default }, + { "AFMT_60958_CS_B", 1, 1, &umr_bitfield_default }, + { "AFMT_60958_CS_C", 2, 2, &umr_bitfield_default }, + { "AFMT_60958_CS_D", 3, 5, &umr_bitfield_default }, + { "AFMT_60958_CS_MODE", 6, 7, &umr_bitfield_default }, + { "AFMT_60958_CS_CATEGORY_CODE", 8, 15, &umr_bitfield_default }, + { "AFMT_60958_CS_SOURCE_NUMBER", 16, 19, &umr_bitfield_default }, + { "AFMT_60958_CS_CHANNEL_NUMBER_L", 20, 23, &umr_bitfield_default }, + { "AFMT_60958_CS_SAMPLING_FREQUENCY", 24, 27, &umr_bitfield_default }, + { "AFMT_60958_CS_CLOCK_ACCURACY", 28, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_AFMT_60958_1[] = { + { "AFMT_60958_CS_WORD_LENGTH", 0, 3, &umr_bitfield_default }, + { "AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY", 4, 7, &umr_bitfield_default }, + { "AFMT_60958_VALID_L", 16, 16, &umr_bitfield_default }, + { "AFMT_60958_VALID_R", 18, 18, &umr_bitfield_default }, + { "AFMT_60958_CS_CHANNEL_NUMBER_R", 20, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_AFMT_AUDIO_CRC_CONTROL[] = { + { "AFMT_AUDIO_CRC_EN", 0, 0, &umr_bitfield_default }, + { "AFMT_AUDIO_CRC_CONT", 4, 4, &umr_bitfield_default }, + { "AFMT_AUDIO_CRC_SOURCE", 8, 8, &umr_bitfield_default }, + { "AFMT_AUDIO_CRC_CH_SEL", 12, 15, &umr_bitfield_default }, + { "AFMT_AUDIO_CRC_COUNT", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_AFMT_RAMP_CONTROL0[] = { + { "AFMT_RAMP_MAX_COUNT", 0, 23, &umr_bitfield_default }, + { "AFMT_RAMP_DATA_SIGN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_AFMT_RAMP_CONTROL1[] = { + { "AFMT_RAMP_MIN_COUNT", 0, 23, &umr_bitfield_default }, + { "AFMT_AUDIO_TEST_CH_DISABLE", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_AFMT_RAMP_CONTROL2[] = { + { "AFMT_RAMP_INC_COUNT", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_AFMT_RAMP_CONTROL3[] = { + { "AFMT_RAMP_DEC_COUNT", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_AFMT_60958_2[] = { + { "AFMT_60958_CS_CHANNEL_NUMBER_2", 0, 3, &umr_bitfield_default }, + { "AFMT_60958_CS_CHANNEL_NUMBER_3", 4, 7, &umr_bitfield_default }, + { "AFMT_60958_CS_CHANNEL_NUMBER_4", 8, 11, &umr_bitfield_default }, + { "AFMT_60958_CS_CHANNEL_NUMBER_5", 12, 15, &umr_bitfield_default }, + { "AFMT_60958_CS_CHANNEL_NUMBER_6", 16, 19, &umr_bitfield_default }, + { "AFMT_60958_CS_CHANNEL_NUMBER_7", 20, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_AFMT_AUDIO_CRC_RESULT[] = { + { "AFMT_AUDIO_CRC_DONE", 0, 0, &umr_bitfield_default }, + { "AFMT_AUDIO_CRC", 8, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_AFMT_STATUS[] = { + { "AFMT_AUDIO_ENABLE", 4, 4, &umr_bitfield_default }, + { "AFMT_AZ_HBR_ENABLE", 8, 8, &umr_bitfield_default }, + { "AFMT_AUDIO_FIFO_OVERFLOW", 24, 24, &umr_bitfield_default }, + { "AFMT_AZ_AUDIO_ENABLE_CHG", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_AFMT_AUDIO_PACKET_CONTROL[] = { + { "AFMT_AUDIO_SAMPLE_SEND", 0, 0, &umr_bitfield_default }, + { "AFMT_RESET_FIFO_WHEN_AUDIO_DIS", 11, 11, &umr_bitfield_default }, + { "AFMT_AUDIO_TEST_EN", 12, 12, &umr_bitfield_default }, + { "AFMT_AUDIO_TEST_MODE", 14, 14, &umr_bitfield_default }, + { "AFMT_AUDIO_FIFO_OVERFLOW_ACK", 23, 23, &umr_bitfield_default }, + { "AFMT_AUDIO_CHANNEL_SWAP", 24, 24, &umr_bitfield_default }, + { "AFMT_60958_CS_UPDATE", 26, 26, &umr_bitfield_default }, + { "AFMT_AZ_AUDIO_ENABLE_CHG_ACK", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_AFMT_VBI_PACKET_CONTROL[] = { + { "AFMT_GENERIC_LOCK_STATUS", 8, 8, &umr_bitfield_default }, + { "AFMT_GENERIC_CONFLICT", 16, 16, &umr_bitfield_default }, + { "AFMT_GENERIC_CONFLICT_CLR", 17, 17, &umr_bitfield_default }, + { "AFMT_GENERIC_INDEX", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_AFMT_INFOFRAME_CONTROL0[] = { + { "AFMT_AUDIO_INFO_SOURCE", 6, 6, &umr_bitfield_default }, + { "AFMT_AUDIO_INFO_UPDATE", 7, 7, &umr_bitfield_default }, + { "AFMT_MPEG_INFO_UPDATE", 10, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_AFMT_AUDIO_SRC_CONTROL[] = { + { "AFMT_AUDIO_SRC_SELECT", 0, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_DIG_BE_CNTL[] = { + { "DIG_DUAL_LINK_ENABLE", 0, 0, &umr_bitfield_default }, + { "DIG_SWAP", 1, 1, &umr_bitfield_default }, + { "DIG_FE_SOURCE_SELECT", 8, 14, &umr_bitfield_default }, + { "DIG_MODE", 16, 18, &umr_bitfield_default }, + { "DIG_HPD_SELECT", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_DIG_BE_EN_CNTL[] = { + { "DIG_ENABLE", 0, 0, &umr_bitfield_default }, + { "DIG_SYMCLK_BE_ON", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_TMDS_CNTL[] = { + { "TMDS_SYNC_PHASE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_TMDS_CONTROL_CHAR[] = { + { "TMDS_CONTROL_CHAR0_OUT_EN", 0, 0, &umr_bitfield_default }, + { "TMDS_CONTROL_CHAR1_OUT_EN", 1, 1, &umr_bitfield_default }, + { "TMDS_CONTROL_CHAR2_OUT_EN", 2, 2, &umr_bitfield_default }, + { "TMDS_CONTROL_CHAR3_OUT_EN", 3, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_TMDS_CONTROL0_FEEDBACK[] = { + { "TMDS_CONTROL0_FEEDBACK_SELECT", 0, 1, &umr_bitfield_default }, + { "TMDS_CONTROL0_FEEDBACK_DELAY", 8, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_TMDS_STEREOSYNC_CTL_SEL[] = { + { "TMDS_STEREOSYNC_CTL_SEL", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1[] = { + { "TMDS_SYNC_CHAR_PATTERN0", 0, 9, &umr_bitfield_default }, + { "TMDS_SYNC_CHAR_PATTERN1", 16, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3[] = { + { "TMDS_SYNC_CHAR_PATTERN2", 0, 9, &umr_bitfield_default }, + { "TMDS_SYNC_CHAR_PATTERN3", 16, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_TMDS_CTL_BITS[] = { + { "TMDS_CTL0", 0, 0, &umr_bitfield_default }, + { "TMDS_CTL1", 8, 8, &umr_bitfield_default }, + { "TMDS_CTL2", 16, 16, &umr_bitfield_default }, + { "TMDS_CTL3", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_TMDS_DCBALANCER_CONTROL[] = { + { "TMDS_DCBALANCER_EN", 0, 0, &umr_bitfield_default }, + { "TMDS_DCBALANCER_TEST_EN", 8, 8, &umr_bitfield_default }, + { "TMDS_DCBALANCER_TEST_IN", 16, 19, &umr_bitfield_default }, + { "TMDS_DCBALANCER_FORCE", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_TMDS_CTL0_1_GEN_CNTL[] = { + { "TMDS_CTL0_DATA_SEL", 0, 3, &umr_bitfield_default }, + { "TMDS_CTL0_DATA_DELAY", 4, 6, &umr_bitfield_default }, + { "TMDS_CTL0_DATA_INVERT", 7, 7, &umr_bitfield_default }, + { "TMDS_CTL0_DATA_MODULATION", 8, 9, &umr_bitfield_default }, + { "TMDS_CTL0_USE_FEEDBACK_PATH", 10, 10, &umr_bitfield_default }, + { "TMDS_CTL0_FB_SYNC_CONT", 11, 11, &umr_bitfield_default }, + { "TMDS_CTL0_PATTERN_OUT_EN", 12, 12, &umr_bitfield_default }, + { "TMDS_CTL1_DATA_SEL", 16, 19, &umr_bitfield_default }, + { "TMDS_CTL1_DATA_DELAY", 20, 22, &umr_bitfield_default }, + { "TMDS_CTL1_DATA_INVERT", 23, 23, &umr_bitfield_default }, + { "TMDS_CTL1_DATA_MODULATION", 24, 25, &umr_bitfield_default }, + { "TMDS_CTL1_USE_FEEDBACK_PATH", 26, 26, &umr_bitfield_default }, + { "TMDS_CTL1_FB_SYNC_CONT", 27, 27, &umr_bitfield_default }, + { "TMDS_CTL1_PATTERN_OUT_EN", 28, 28, &umr_bitfield_default }, + { "TMDS_2BIT_COUNTER_EN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_TMDS_CTL2_3_GEN_CNTL[] = { + { "TMDS_CTL2_DATA_SEL", 0, 3, &umr_bitfield_default }, + { "TMDS_CTL2_DATA_DELAY", 4, 6, &umr_bitfield_default }, + { "TMDS_CTL2_DATA_INVERT", 7, 7, &umr_bitfield_default }, + { "TMDS_CTL2_DATA_MODULATION", 8, 9, &umr_bitfield_default }, + { "TMDS_CTL2_USE_FEEDBACK_PATH", 10, 10, &umr_bitfield_default }, + { "TMDS_CTL2_FB_SYNC_CONT", 11, 11, &umr_bitfield_default }, + { "TMDS_CTL2_PATTERN_OUT_EN", 12, 12, &umr_bitfield_default }, + { "TMDS_CTL3_DATA_SEL", 16, 19, &umr_bitfield_default }, + { "TMDS_CTL3_DATA_DELAY", 20, 22, &umr_bitfield_default }, + { "TMDS_CTL3_DATA_INVERT", 23, 23, &umr_bitfield_default }, + { "TMDS_CTL3_DATA_MODULATION", 24, 25, &umr_bitfield_default }, + { "TMDS_CTL3_USE_FEEDBACK_PATH", 26, 26, &umr_bitfield_default }, + { "TMDS_CTL3_FB_SYNC_CONT", 27, 27, &umr_bitfield_default }, + { "TMDS_CTL3_PATTERN_OUT_EN", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_DIG_VERSION[] = { + { "DIG_TYPE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_DIG_LANE_ENABLE[] = { + { "DIG_LANE0EN", 0, 0, &umr_bitfield_default }, + { "DIG_LANE1EN", 1, 1, &umr_bitfield_default }, + { "DIG_LANE2EN", 2, 2, &umr_bitfield_default }, + { "DIG_LANE3EN", 3, 3, &umr_bitfield_default }, + { "DIG_CLK_EN", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_AFMT_CNTL[] = { + { "AFMT_AUDIO_CLOCK_EN", 0, 0, &umr_bitfield_default }, + { "AFMT_AUDIO_CLOCK_ON", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIG6_AFMT_VBI_PACKET_CONTROL1[] = { + { "AFMT_GENERIC0_FRAME_UPDATE", 0, 0, &umr_bitfield_default }, + { "AFMT_GENERIC0_FRAME_UPDATE_PENDING", 1, 1, &umr_bitfield_default }, + { "AFMT_GENERIC0_IMMEDIATE_UPDATE", 2, 2, &umr_bitfield_default }, + { "AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING", 3, 3, &umr_bitfield_default }, + { "AFMT_GENERIC1_FRAME_UPDATE", 4, 4, &umr_bitfield_default }, + { "AFMT_GENERIC1_FRAME_UPDATE_PENDING", 5, 5, &umr_bitfield_default }, + { "AFMT_GENERIC1_IMMEDIATE_UPDATE", 6, 6, &umr_bitfield_default }, + { "AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING", 7, 7, &umr_bitfield_default }, + { "AFMT_GENERIC2_FRAME_UPDATE", 8, 8, &umr_bitfield_default }, + { "AFMT_GENERIC2_FRAME_UPDATE_PENDING", 9, 9, &umr_bitfield_default }, + { "AFMT_GENERIC2_IMMEDIATE_UPDATE", 10, 10, &umr_bitfield_default }, + { "AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING", 11, 11, &umr_bitfield_default }, + { "AFMT_GENERIC3_FRAME_UPDATE", 12, 12, &umr_bitfield_default }, + { "AFMT_GENERIC3_FRAME_UPDATE_PENDING", 13, 13, &umr_bitfield_default }, + { "AFMT_GENERIC3_IMMEDIATE_UPDATE", 14, 14, &umr_bitfield_default }, + { "AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING", 15, 15, &umr_bitfield_default }, + { "AFMT_GENERIC4_FRAME_UPDATE", 16, 16, &umr_bitfield_default }, + { "AFMT_GENERIC4_FRAME_UPDATE_PENDING", 17, 17, &umr_bitfield_default }, + { "AFMT_GENERIC4_IMMEDIATE_UPDATE", 18, 18, &umr_bitfield_default }, + { "AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING", 19, 19, &umr_bitfield_default }, + { "AFMT_GENERIC5_FRAME_UPDATE", 20, 20, &umr_bitfield_default }, + { "AFMT_GENERIC5_FRAME_UPDATE_PENDING", 21, 21, &umr_bitfield_default }, + { "AFMT_GENERIC5_IMMEDIATE_UPDATE", 22, 22, &umr_bitfield_default }, + { "AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING", 23, 23, &umr_bitfield_default }, + { "AFMT_GENERIC6_FRAME_UPDATE", 24, 24, &umr_bitfield_default }, + { "AFMT_GENERIC6_FRAME_UPDATE_PENDING", 25, 25, &umr_bitfield_default }, + { "AFMT_GENERIC6_IMMEDIATE_UPDATE", 26, 26, &umr_bitfield_default }, + { "AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING", 27, 27, &umr_bitfield_default }, + { "AFMT_GENERIC7_FRAME_UPDATE", 28, 28, &umr_bitfield_default }, + { "AFMT_GENERIC7_FRAME_UPDATE_PENDING", 29, 29, &umr_bitfield_default }, + { "AFMT_GENERIC7_IMMEDIATE_UPDATE", 30, 30, &umr_bitfield_default }, + { "AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_LINK_CNTL[] = { + { "DP_LINK_TRAINING_COMPLETE", 4, 4, &umr_bitfield_default }, + { "DP_LINK_STATUS", 8, 8, &umr_bitfield_default }, + { "DP_EMBEDDED_PANEL_MODE", 17, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_PIXEL_FORMAT[] = { + { "DP_PIXEL_ENCODING", 0, 2, &umr_bitfield_default }, + { "DP_COMPONENT_DEPTH", 24, 26, &umr_bitfield_default }, + { "DP_PIXEL_COMBINE", 28, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_MSA_COLORIMETRY[] = { + { "DP_MSA_MISC0", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_CONFIG[] = { + { "DP_UDI_LANES", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_VID_STREAM_CNTL[] = { + { "DP_VID_STREAM_ENABLE", 0, 0, &umr_bitfield_default }, + { "DP_VID_STREAM_DIS_DEFER", 8, 9, &umr_bitfield_default }, + { "DP_VID_STREAM_STATUS", 16, 16, &umr_bitfield_default }, + { "DP_VID_STREAM_CHANGE_KEEPOUT", 20, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_STEER_FIFO[] = { + { "DP_STEER_FIFO_RESET", 0, 0, &umr_bitfield_default }, + { "DP_STEER_OVERFLOW_FLAG", 4, 4, &umr_bitfield_default }, + { "DP_STEER_OVERFLOW_INT", 5, 5, &umr_bitfield_default }, + { "DP_STEER_OVERFLOW_ACK", 6, 6, &umr_bitfield_default }, + { "DP_STEER_OVERFLOW_MASK", 7, 7, &umr_bitfield_default }, + { "DP_TU_OVERFLOW_FLAG", 8, 8, &umr_bitfield_default }, + { "DP_TU_OVERFLOW_ACK", 12, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_MSA_MISC[] = { + { "DP_MSA_MISC1", 0, 7, &umr_bitfield_default }, + { "DP_MSA_MISC2", 8, 15, &umr_bitfield_default }, + { "DP_MSA_MISC3", 16, 23, &umr_bitfield_default }, + { "DP_MSA_MISC4", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_VID_TIMING[] = { + { "DP_VID_M_N_DOUBLE_BUFFER_MODE", 4, 4, &umr_bitfield_default }, + { "DP_VID_M_N_GEN_EN", 8, 8, &umr_bitfield_default }, + { "DP_VID_N_MUL", 10, 11, &umr_bitfield_default }, + { "DP_VID_M_DIV", 12, 13, &umr_bitfield_default }, + { "DP_VID_N_DIV", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_VID_N[] = { + { "DP_VID_N", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_VID_M[] = { + { "DP_VID_M", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_LINK_FRAMING_CNTL[] = { + { "DP_IDLE_BS_INTERVAL", 0, 17, &umr_bitfield_default }, + { "DP_VBID_DISABLE", 24, 24, &umr_bitfield_default }, + { "DP_VID_ENHANCED_FRAME_MODE", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_HBR2_EYE_PATTERN[] = { + { "DP_HBR2_EYE_PATTERN_ENABLE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_VID_MSA_VBID[] = { + { "DP_VID_MSA_LOCATION", 0, 11, &umr_bitfield_default }, + { "DP_VID_VBID_FIELD_POL", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_VID_INTERRUPT_CNTL[] = { + { "DP_VID_STREAM_DISABLE_INT", 0, 0, &umr_bitfield_default }, + { "DP_VID_STREAM_DISABLE_ACK", 1, 1, &umr_bitfield_default }, + { "DP_VID_STREAM_DISABLE_MASK", 2, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_DPHY_CNTL[] = { + { "DPHY_ATEST_SEL_LANE0", 0, 0, &umr_bitfield_default }, + { "DPHY_ATEST_SEL_LANE1", 1, 1, &umr_bitfield_default }, + { "DPHY_ATEST_SEL_LANE2", 2, 2, &umr_bitfield_default }, + { "DPHY_ATEST_SEL_LANE3", 3, 3, &umr_bitfield_default }, + { "DPHY_BYPASS", 16, 16, &umr_bitfield_default }, + { "DPHY_SKEW_BYPASS", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_DPHY_TRAINING_PATTERN_SEL[] = { + { "DPHY_TRAINING_PATTERN_SEL", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_DPHY_SYM0[] = { + { "DPHY_SYM1", 0, 9, &umr_bitfield_default }, + { "DPHY_SYM2", 10, 19, &umr_bitfield_default }, + { "DPHY_SYM3", 20, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_DPHY_SYM1[] = { + { "DPHY_SYM4", 0, 9, &umr_bitfield_default }, + { "DPHY_SYM5", 10, 19, &umr_bitfield_default }, + { "DPHY_SYM6", 20, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_DPHY_SYM2[] = { + { "DPHY_SYM7", 0, 9, &umr_bitfield_default }, + { "DPHY_SYM8", 10, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_DPHY_8B10B_CNTL[] = { + { "DPHY_8B10B_RESET", 8, 8, &umr_bitfield_default }, + { "DPHY_8B10B_EXT_DISP", 16, 16, &umr_bitfield_default }, + { "DPHY_8B10B_CUR_DISP", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_DPHY_PRBS_CNTL[] = { + { "DPHY_PRBS_EN", 0, 0, &umr_bitfield_default }, + { "DPHY_PRBS_SEL", 4, 5, &umr_bitfield_default }, + { "DPHY_PRBS_SEED", 8, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_DPHY_SCRAM_CNTL[] = { + { "DPHY_SCRAMBLER_DIS", 0, 0, &umr_bitfield_default }, + { "DPHY_SCRAMBLER_ADVANCE", 4, 4, &umr_bitfield_default }, + { "DPHY_SCRAMBLER_BS_COUNT", 8, 17, &umr_bitfield_default }, + { "DPHY_SCRAMBLER_KCODE", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_DPHY_CRC_EN[] = { + { "DPHY_CRC_EN", 0, 0, &umr_bitfield_default }, + { "DPHY_CRC_CONT_EN", 4, 4, &umr_bitfield_default }, + { "DPHY_CRC_RESULT_VALID", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_DPHY_CRC_CNTL[] = { + { "DPHY_CRC_FIELD", 0, 0, &umr_bitfield_default }, + { "DPHY_CRC_SEL", 4, 5, &umr_bitfield_default }, + { "DPHY_CRC_MASK", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_DPHY_CRC_RESULT[] = { + { "DPHY_CRC_RESULT", 0, 7, &umr_bitfield_default }, + { "DPHY_CRC_RESULT1", 8, 15, &umr_bitfield_default }, + { "DPHY_CRC_RESULT2", 16, 23, &umr_bitfield_default }, + { "DPHY_CRC_RESULT3", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_DPHY_CRC_MST_CNTL[] = { + { "DPHY_CRC_MST_FIRST_SLOT", 0, 5, &umr_bitfield_default }, + { "DPHY_CRC_MST_LAST_SLOT", 8, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_DPHY_CRC_MST_STATUS[] = { + { "DPHY_CRC_MST_PHASE_LOCK", 0, 0, &umr_bitfield_default }, + { "DPHY_CRC_MST_PHASE_ERROR", 8, 8, &umr_bitfield_default }, + { "DPHY_CRC_MST_PHASE_ERROR_ACK", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_DPHY_FAST_TRAINING[] = { + { "DPHY_RX_FAST_TRAINING_CAPABLE", 0, 0, &umr_bitfield_default }, + { "DPHY_SW_FAST_TRAINING_START", 1, 1, &umr_bitfield_default }, + { "DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN", 2, 2, &umr_bitfield_default }, + { "DPHY_FAST_TRAINING_TP1_TIME", 8, 19, &umr_bitfield_default }, + { "DPHY_FAST_TRAINING_TP2_TIME", 20, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_DPHY_FAST_TRAINING_STATUS[] = { + { "DPHY_FAST_TRAINING_STATE", 0, 2, &umr_bitfield_default }, + { "DPHY_FAST_TRAINING_COMPLETE_OCCURRED", 4, 4, &umr_bitfield_default }, + { "DPHY_FAST_TRAINING_COMPLETE_MASK", 8, 8, &umr_bitfield_default }, + { "DPHY_FAST_TRAINING_COMPLETE_ACK", 12, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_SEC_CNTL[] = { + { "DP_SEC_STREAM_ENABLE", 0, 0, &umr_bitfield_default }, + { "DP_SEC_ASP_ENABLE", 4, 4, &umr_bitfield_default }, + { "DP_SEC_ATP_ENABLE", 8, 8, &umr_bitfield_default }, + { "DP_SEC_AIP_ENABLE", 12, 12, &umr_bitfield_default }, + { "DP_SEC_ACM_ENABLE", 16, 16, &umr_bitfield_default }, + { "DP_SEC_GSP0_ENABLE", 20, 20, &umr_bitfield_default }, + { "DP_SEC_GSP1_ENABLE", 21, 21, &umr_bitfield_default }, + { "DP_SEC_GSP2_ENABLE", 22, 22, &umr_bitfield_default }, + { "DP_SEC_GSP3_ENABLE", 23, 23, &umr_bitfield_default }, + { "DP_SEC_GSP4_ENABLE", 24, 24, &umr_bitfield_default }, + { "DP_SEC_GSP5_ENABLE", 25, 25, &umr_bitfield_default }, + { "DP_SEC_GSP6_ENABLE", 26, 26, &umr_bitfield_default }, + { "DP_SEC_GSP7_ENABLE", 27, 27, &umr_bitfield_default }, + { "DP_SEC_MPG_ENABLE", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_SEC_CNTL1[] = { + { "DP_SEC_ISRC_ENABLE", 0, 0, &umr_bitfield_default }, + { "DP_SEC_GSP0_PRIORITY", 4, 4, &umr_bitfield_default }, + { "DP_SEC_GSP0_SEND", 5, 5, &umr_bitfield_default }, + { "DP_SEC_GSP0_SEND_PENDING", 6, 6, &umr_bitfield_default }, + { "DP_SEC_GSP0_SEND_DEADLINE_MISSED", 7, 7, &umr_bitfield_default }, + { "DP_SEC_GSP0_SEND_ANY_LINE", 8, 8, &umr_bitfield_default }, + { "DP_SEC_GSP0_LINE_NUM", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_SEC_FRAMING1[] = { + { "DP_SEC_FRAME_START_LOCATION", 0, 11, &umr_bitfield_default }, + { "DP_SEC_VBLANK_TRANSMIT_WIDTH", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_SEC_FRAMING2[] = { + { "DP_SEC_START_POSITION", 0, 15, &umr_bitfield_default }, + { "DP_SEC_HBLANK_TRANSMIT_WIDTH", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_SEC_FRAMING3[] = { + { "DP_SEC_IDLE_FRAME_SIZE", 0, 13, &umr_bitfield_default }, + { "DP_SEC_IDLE_TRANSMIT_WIDTH", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_SEC_FRAMING4[] = { + { "DP_SEC_COLLISION_STATUS", 20, 20, &umr_bitfield_default }, + { "DP_SEC_COLLISION_ACK", 24, 24, &umr_bitfield_default }, + { "DP_SEC_AUDIO_MUTE", 28, 28, &umr_bitfield_default }, + { "DP_SEC_AUDIO_MUTE_STATUS", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_SEC_AUD_N[] = { + { "DP_SEC_AUD_N", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_SEC_AUD_N_READBACK[] = { + { "DP_SEC_AUD_N_READBACK", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_SEC_AUD_M[] = { + { "DP_SEC_AUD_M", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_SEC_AUD_M_READBACK[] = { + { "DP_SEC_AUD_M_READBACK", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_SEC_TIMESTAMP[] = { + { "DP_SEC_TIMESTAMP_MODE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_SEC_PACKET_CNTL[] = { + { "DP_SEC_ASP_CODING_TYPE", 1, 3, &umr_bitfield_default }, + { "DP_SEC_ASP_PRIORITY", 4, 4, &umr_bitfield_default }, + { "DP_SEC_VERSION", 8, 13, &umr_bitfield_default }, + { "DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_MSE_RATE_CNTL[] = { + { "DP_MSE_RATE_Y", 0, 25, &umr_bitfield_default }, + { "DP_MSE_RATE_X", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_MSE_RATE_UPDATE[] = { + { "DP_MSE_RATE_UPDATE_PENDING", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_MSE_SAT0[] = { + { "DP_MSE_SAT_SRC0", 0, 2, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT0", 8, 13, &umr_bitfield_default }, + { "DP_MSE_SAT_SRC1", 16, 18, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT1", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_MSE_SAT1[] = { + { "DP_MSE_SAT_SRC2", 0, 2, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT2", 8, 13, &umr_bitfield_default }, + { "DP_MSE_SAT_SRC3", 16, 18, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT3", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_MSE_SAT2[] = { + { "DP_MSE_SAT_SRC4", 0, 2, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT4", 8, 13, &umr_bitfield_default }, + { "DP_MSE_SAT_SRC5", 16, 18, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT5", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_MSE_SAT_UPDATE[] = { + { "DP_MSE_SAT_UPDATE", 0, 1, &umr_bitfield_default }, + { "DP_MSE_16_MTP_KEEPOUT", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_MSE_LINK_TIMING[] = { + { "DP_MSE_LINK_FRAME", 0, 9, &umr_bitfield_default }, + { "DP_MSE_LINK_LINE", 16, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_MSE_MISC_CNTL[] = { + { "DP_MSE_BLANK_CODE", 0, 0, &umr_bitfield_default }, + { "DP_MSE_TIMESTAMP_MODE", 4, 4, &umr_bitfield_default }, + { "DP_MSE_ZERO_ENCODER", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_DPHY_BS_SR_SWAP_CNTL[] = { + { "DPHY_LOAD_BS_COUNT", 0, 9, &umr_bitfield_default }, + { "DPHY_BS_SR_SWAP_DONE", 15, 15, &umr_bitfield_default }, + { "DPHY_LOAD_BS_COUNT_START", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_DPHY_HBR2_PATTERN_CONTROL[] = { + { "DP_DPHY_HBR2_PATTERN_CONTROL", 0, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_MSE_SAT0_STATUS[] = { + { "DP_MSE_SAT_SRC0_STATUS", 0, 2, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT0_STATUS", 8, 13, &umr_bitfield_default }, + { "DP_MSE_SAT_SRC1_STATUS", 16, 18, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT1_STATUS", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_MSE_SAT1_STATUS[] = { + { "DP_MSE_SAT_SRC2_STATUS", 0, 2, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT2_STATUS", 8, 13, &umr_bitfield_default }, + { "DP_MSE_SAT_SRC3_STATUS", 16, 18, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT3_STATUS", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_MSE_SAT2_STATUS[] = { + { "DP_MSE_SAT_SRC4_STATUS", 0, 2, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT4_STATUS", 8, 13, &umr_bitfield_default }, + { "DP_MSE_SAT_SRC5_STATUS", 16, 18, &umr_bitfield_default }, + { "DP_MSE_SAT_SLOT_COUNT5_STATUS", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_MSA_TIMING_PARAM1[] = { + { "DP_MSA_VTOTAL", 0, 15, &umr_bitfield_default }, + { "DP_MSA_HTOTAL", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_MSA_TIMING_PARAM2[] = { + { "DP_MSA_VSTART", 0, 15, &umr_bitfield_default }, + { "DP_MSA_HSTART", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_MSA_TIMING_PARAM3[] = { + { "DP_MSA_VSYNCWIDTH", 0, 14, &umr_bitfield_default }, + { "DP_MSA_VSYNCPOLARITY", 15, 15, &umr_bitfield_default }, + { "DP_MSA_HSYNCWIDTH", 16, 30, &umr_bitfield_default }, + { "DP_MSA_HSYNCPOLARITY", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_MSA_TIMING_PARAM4[] = { + { "DP_MSA_VHEIGHT", 0, 15, &umr_bitfield_default }, + { "DP_MSA_HWIDTH", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_MSO_CNTL[] = { + { "DP_MSO_NUM_OF_SSTLINK", 0, 1, &umr_bitfield_default }, + { "DP_MSO_SEC_STREAM_ENABLE", 4, 7, &umr_bitfield_default }, + { "DP_MSO_SEC_ASP_ENABLE", 8, 11, &umr_bitfield_default }, + { "DP_MSO_SEC_ATP_ENABLE", 12, 15, &umr_bitfield_default }, + { "DP_MSO_SEC_AIP_ENABLE", 16, 19, &umr_bitfield_default }, + { "DP_MSO_SEC_ACM_ENABLE", 20, 23, &umr_bitfield_default }, + { "DP_MSO_SEC_GSP0_ENABLE", 24, 27, &umr_bitfield_default }, + { "DP_MSO_SEC_GSP1_ENABLE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_MSO_CNTL1[] = { + { "DP_MSO_SEC_GSP2_ENABLE", 0, 3, &umr_bitfield_default }, + { "DP_MSO_SEC_GSP3_ENABLE", 4, 7, &umr_bitfield_default }, + { "DP_MSO_SEC_GSP4_ENABLE", 8, 11, &umr_bitfield_default }, + { "DP_MSO_SEC_GSP5_ENABLE", 12, 15, &umr_bitfield_default }, + { "DP_MSO_SEC_GSP6_ENABLE", 16, 19, &umr_bitfield_default }, + { "DP_MSO_SEC_GSP7_ENABLE", 20, 23, &umr_bitfield_default }, + { "DP_MSO_SEC_MPG_ENABLE", 24, 27, &umr_bitfield_default }, + { "DP_MSO_SEC_ISRC_ENABLE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_DSC_CNTL[] = { + { "DP_DSC_EN", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_SEC_CNTL2[] = { + { "DP_SEC_GSP1_SEND", 0, 0, &umr_bitfield_default }, + { "DP_SEC_GSP1_SEND_PENDING", 1, 1, &umr_bitfield_default }, + { "DP_SEC_GSP1_SEND_DEADLINE_MISSED", 2, 2, &umr_bitfield_default }, + { "DP_SEC_GSP1_SEND_ANY_LINE", 3, 3, &umr_bitfield_default }, + { "DP_SEC_GSP2_SEND", 4, 4, &umr_bitfield_default }, + { "DP_SEC_GSP2_SEND_PENDING", 5, 5, &umr_bitfield_default }, + { "DP_SEC_GSP2_SEND_DEADLINE_MISSED", 6, 6, &umr_bitfield_default }, + { "DP_SEC_GSP2_SEND_ANY_LINE", 7, 7, &umr_bitfield_default }, + { "DP_SEC_GSP3_SEND", 8, 8, &umr_bitfield_default }, + { "DP_SEC_GSP3_SEND_PENDING", 9, 9, &umr_bitfield_default }, + { "DP_SEC_GSP3_SEND_DEADLINE_MISSED", 10, 10, &umr_bitfield_default }, + { "DP_SEC_GSP3_SEND_ANY_LINE", 11, 11, &umr_bitfield_default }, + { "DP_SEC_GSP4_SEND", 12, 12, &umr_bitfield_default }, + { "DP_SEC_GSP4_SEND_PENDING", 13, 13, &umr_bitfield_default }, + { "DP_SEC_GSP4_SEND_DEADLINE_MISSED", 14, 14, &umr_bitfield_default }, + { "DP_SEC_GSP4_SEND_ANY_LINE", 15, 15, &umr_bitfield_default }, + { "DP_SEC_GSP5_SEND", 16, 16, &umr_bitfield_default }, + { "DP_SEC_GSP5_SEND_PENDING", 17, 17, &umr_bitfield_default }, + { "DP_SEC_GSP5_SEND_DEADLINE_MISSED", 18, 18, &umr_bitfield_default }, + { "DP_SEC_GSP5_SEND_ANY_LINE", 19, 19, &umr_bitfield_default }, + { "DP_SEC_GSP6_SEND", 20, 20, &umr_bitfield_default }, + { "DP_SEC_GSP6_SEND_PENDING", 21, 21, &umr_bitfield_default }, + { "DP_SEC_GSP6_SEND_DEADLINE_MISSED", 22, 22, &umr_bitfield_default }, + { "DP_SEC_GSP6_SEND_ANY_LINE", 23, 23, &umr_bitfield_default }, + { "DP_SEC_GSP7_SEND", 24, 24, &umr_bitfield_default }, + { "DP_SEC_GSP7_SEND_PENDING", 25, 25, &umr_bitfield_default }, + { "DP_SEC_GSP7_SEND_DEADLINE_MISSED", 26, 26, &umr_bitfield_default }, + { "DP_SEC_GSP7_SEND_ANY_LINE", 27, 27, &umr_bitfield_default }, + { "DP_SEC_GSP7_PPS", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_SEC_CNTL3[] = { + { "DP_SEC_GSP1_LINE_NUM", 0, 15, &umr_bitfield_default }, + { "DP_SEC_GSP2_LINE_NUM", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_SEC_CNTL4[] = { + { "DP_SEC_GSP3_LINE_NUM", 0, 15, &umr_bitfield_default }, + { "DP_SEC_GSP4_LINE_NUM", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_SEC_CNTL5[] = { + { "DP_SEC_GSP5_LINE_NUM", 0, 15, &umr_bitfield_default }, + { "DP_SEC_GSP6_LINE_NUM", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_SEC_CNTL6[] = { + { "DP_SEC_GSP7_LINE_NUM", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_SEC_CNTL7[] = { + { "DP_SEC_GSP0_SEND_ACTIVE", 0, 0, &umr_bitfield_default }, + { "DP_SEC_GSP1_SEND_ACTIVE", 4, 4, &umr_bitfield_default }, + { "DP_SEC_GSP2_SEND_ACTIVE", 8, 8, &umr_bitfield_default }, + { "DP_SEC_GSP3_SEND_ACTIVE", 12, 12, &umr_bitfield_default }, + { "DP_SEC_GSP4_SEND_ACTIVE", 16, 16, &umr_bitfield_default }, + { "DP_SEC_GSP5_SEND_ACTIVE", 20, 20, &umr_bitfield_default }, + { "DP_SEC_GSP6_SEND_ACTIVE", 24, 24, &umr_bitfield_default }, + { "DP_SEC_GSP7_SEND_ACTIVE", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_DB_CNTL[] = { + { "DP_DB_PENDING", 0, 0, &umr_bitfield_default }, + { "DP_DB_TAKEN", 4, 4, &umr_bitfield_default }, + { "DP_DB_TAKEN_CLR", 5, 5, &umr_bitfield_default }, + { "DP_DB_LOCK", 8, 8, &umr_bitfield_default }, + { "DP_DB_DISABLE", 12, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDP6_DP_MSA_VBID_MISC[] = { + { "DP_MSA_MISC1_STEREOSYNC_OVERRIDE", 0, 1, &umr_bitfield_default }, + { "DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN", 4, 4, &umr_bitfield_default }, + { "DP_VBID1_OVERRIDE", 8, 8, &umr_bitfield_default }, + { "DP_VBID2_OVERRIDE", 9, 9, &umr_bitfield_default }, + { "DP_VBID1_OVERRIDE_EN", 12, 12, &umr_bitfield_default }, + { "DP_VBID2_OVERRIDE_EN", 13, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GENERICA[] = { + { "GENERICA_EN", 0, 0, &umr_bitfield_default }, + { "GENERICA_SEL", 7, 11, &umr_bitfield_default }, + { "GENERICA_UNIPHY_REFDIV_CLK_SEL", 12, 15, &umr_bitfield_default }, + { "GENERICA_UNIPHY_FBDIV_CLK_SEL", 16, 19, &umr_bitfield_default }, + { "GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL", 20, 23, &umr_bitfield_default }, + { "GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL", 24, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GENERICB[] = { + { "GENERICB_EN", 0, 0, &umr_bitfield_default }, + { "GENERICB_SEL", 8, 11, &umr_bitfield_default }, + { "GENERICB_UNIPHY_REFDIV_CLK_SEL", 12, 15, &umr_bitfield_default }, + { "GENERICB_UNIPHY_FBDIV_CLK_SEL", 16, 19, &umr_bitfield_default }, + { "GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL", 20, 23, &umr_bitfield_default }, + { "GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL", 24, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_REF_CLK_CNTL[] = { + { "HSYNCA_OUTPUT_SEL", 0, 1, &umr_bitfield_default }, + { "GENLK_CLK_OUTPUT_SEL", 8, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_DEBUG[] = { + { "DC_GPIO_VIP_DEBUG", 0, 0, &umr_bitfield_default }, + { "DC_GPIO_MACRO_DEBUG", 8, 9, &umr_bitfield_default }, + { "DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL", 16, 16, &umr_bitfield_default }, + { "DC_GPIO_DEBUG_BUS_FLOP_EN", 17, 17, &umr_bitfield_default }, + { "DPRX_LOOPBACK_ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUNIPHYA_LINK_CNTL[] = { + { "UNIPHY_PFREQCHG", 0, 0, &umr_bitfield_default }, + { "UNIPHY_PIXVLD_RESET", 4, 4, &umr_bitfield_default }, + { "UNIPHY_MINIMUM_PIXVLD_LOW_DURATION", 8, 10, &umr_bitfield_default }, + { "UNIPHY_CHANNEL0_INVERT", 12, 12, &umr_bitfield_default }, + { "UNIPHY_CHANNEL1_INVERT", 13, 13, &umr_bitfield_default }, + { "UNIPHY_CHANNEL2_INVERT", 14, 14, &umr_bitfield_default }, + { "UNIPHY_CHANNEL3_INVERT", 15, 15, &umr_bitfield_default }, + { "UNIPHY_LANE_STAGGER_DELAY", 20, 22, &umr_bitfield_default }, + { "UNIPHY_LINK_ENABLE_HPD_MASK", 24, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUNIPHYA_CHANNEL_XBAR_CNTL[] = { + { "UNIPHY_CHANNEL0_XBAR_SOURCE", 0, 1, &umr_bitfield_default }, + { "UNIPHY_CHANNEL1_XBAR_SOURCE", 8, 9, &umr_bitfield_default }, + { "UNIPHY_CHANNEL2_XBAR_SOURCE", 16, 17, &umr_bitfield_default }, + { "UNIPHY_CHANNEL3_XBAR_SOURCE", 24, 25, &umr_bitfield_default }, + { "UNIPHY_LINK_ENABLE", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUNIPHYB_LINK_CNTL[] = { + { "UNIPHY_PFREQCHG", 0, 0, &umr_bitfield_default }, + { "UNIPHY_PIXVLD_RESET", 4, 4, &umr_bitfield_default }, + { "UNIPHY_MINIMUM_PIXVLD_LOW_DURATION", 8, 10, &umr_bitfield_default }, + { "UNIPHY_CHANNEL0_INVERT", 12, 12, &umr_bitfield_default }, + { "UNIPHY_CHANNEL1_INVERT", 13, 13, &umr_bitfield_default }, + { "UNIPHY_CHANNEL2_INVERT", 14, 14, &umr_bitfield_default }, + { "UNIPHY_CHANNEL3_INVERT", 15, 15, &umr_bitfield_default }, + { "UNIPHY_LANE_STAGGER_DELAY", 20, 22, &umr_bitfield_default }, + { "UNIPHY_LINK_ENABLE_HPD_MASK", 24, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUNIPHYB_CHANNEL_XBAR_CNTL[] = { + { "UNIPHY_CHANNEL0_XBAR_SOURCE", 0, 1, &umr_bitfield_default }, + { "UNIPHY_CHANNEL1_XBAR_SOURCE", 8, 9, &umr_bitfield_default }, + { "UNIPHY_CHANNEL2_XBAR_SOURCE", 16, 17, &umr_bitfield_default }, + { "UNIPHY_CHANNEL3_XBAR_SOURCE", 24, 25, &umr_bitfield_default }, + { "UNIPHY_LINK_ENABLE", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUNIPHYC_LINK_CNTL[] = { + { "UNIPHY_PFREQCHG", 0, 0, &umr_bitfield_default }, + { "UNIPHY_PIXVLD_RESET", 4, 4, &umr_bitfield_default }, + { "UNIPHY_MINIMUM_PIXVLD_LOW_DURATION", 8, 10, &umr_bitfield_default }, + { "UNIPHY_CHANNEL0_INVERT", 12, 12, &umr_bitfield_default }, + { "UNIPHY_CHANNEL1_INVERT", 13, 13, &umr_bitfield_default }, + { "UNIPHY_CHANNEL2_INVERT", 14, 14, &umr_bitfield_default }, + { "UNIPHY_CHANNEL3_INVERT", 15, 15, &umr_bitfield_default }, + { "UNIPHY_LANE_STAGGER_DELAY", 20, 22, &umr_bitfield_default }, + { "UNIPHY_LINK_ENABLE_HPD_MASK", 24, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUNIPHYC_CHANNEL_XBAR_CNTL[] = { + { "UNIPHY_CHANNEL0_XBAR_SOURCE", 0, 1, &umr_bitfield_default }, + { "UNIPHY_CHANNEL1_XBAR_SOURCE", 8, 9, &umr_bitfield_default }, + { "UNIPHY_CHANNEL2_XBAR_SOURCE", 16, 17, &umr_bitfield_default }, + { "UNIPHY_CHANNEL3_XBAR_SOURCE", 24, 25, &umr_bitfield_default }, + { "UNIPHY_LINK_ENABLE", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUNIPHYD_LINK_CNTL[] = { + { "UNIPHY_PFREQCHG", 0, 0, &umr_bitfield_default }, + { "UNIPHY_PIXVLD_RESET", 4, 4, &umr_bitfield_default }, + { "UNIPHY_MINIMUM_PIXVLD_LOW_DURATION", 8, 10, &umr_bitfield_default }, + { "UNIPHY_CHANNEL0_INVERT", 12, 12, &umr_bitfield_default }, + { "UNIPHY_CHANNEL1_INVERT", 13, 13, &umr_bitfield_default }, + { "UNIPHY_CHANNEL2_INVERT", 14, 14, &umr_bitfield_default }, + { "UNIPHY_CHANNEL3_INVERT", 15, 15, &umr_bitfield_default }, + { "UNIPHY_LANE_STAGGER_DELAY", 20, 22, &umr_bitfield_default }, + { "UNIPHY_LINK_ENABLE_HPD_MASK", 24, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUNIPHYD_CHANNEL_XBAR_CNTL[] = { + { "UNIPHY_CHANNEL0_XBAR_SOURCE", 0, 1, &umr_bitfield_default }, + { "UNIPHY_CHANNEL1_XBAR_SOURCE", 8, 9, &umr_bitfield_default }, + { "UNIPHY_CHANNEL2_XBAR_SOURCE", 16, 17, &umr_bitfield_default }, + { "UNIPHY_CHANNEL3_XBAR_SOURCE", 24, 25, &umr_bitfield_default }, + { "UNIPHY_LINK_ENABLE", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUNIPHYE_LINK_CNTL[] = { + { "UNIPHY_PFREQCHG", 0, 0, &umr_bitfield_default }, + { "UNIPHY_PIXVLD_RESET", 4, 4, &umr_bitfield_default }, + { "UNIPHY_MINIMUM_PIXVLD_LOW_DURATION", 8, 10, &umr_bitfield_default }, + { "UNIPHY_CHANNEL0_INVERT", 12, 12, &umr_bitfield_default }, + { "UNIPHY_CHANNEL1_INVERT", 13, 13, &umr_bitfield_default }, + { "UNIPHY_CHANNEL2_INVERT", 14, 14, &umr_bitfield_default }, + { "UNIPHY_CHANNEL3_INVERT", 15, 15, &umr_bitfield_default }, + { "UNIPHY_LANE_STAGGER_DELAY", 20, 22, &umr_bitfield_default }, + { "UNIPHY_LINK_ENABLE_HPD_MASK", 24, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUNIPHYE_CHANNEL_XBAR_CNTL[] = { + { "UNIPHY_CHANNEL0_XBAR_SOURCE", 0, 1, &umr_bitfield_default }, + { "UNIPHY_CHANNEL1_XBAR_SOURCE", 8, 9, &umr_bitfield_default }, + { "UNIPHY_CHANNEL2_XBAR_SOURCE", 16, 17, &umr_bitfield_default }, + { "UNIPHY_CHANNEL3_XBAR_SOURCE", 24, 25, &umr_bitfield_default }, + { "UNIPHY_LINK_ENABLE", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUNIPHYF_LINK_CNTL[] = { + { "UNIPHY_PFREQCHG", 0, 0, &umr_bitfield_default }, + { "UNIPHY_PIXVLD_RESET", 4, 4, &umr_bitfield_default }, + { "UNIPHY_MINIMUM_PIXVLD_LOW_DURATION", 8, 10, &umr_bitfield_default }, + { "UNIPHY_CHANNEL0_INVERT", 12, 12, &umr_bitfield_default }, + { "UNIPHY_CHANNEL1_INVERT", 13, 13, &umr_bitfield_default }, + { "UNIPHY_CHANNEL2_INVERT", 14, 14, &umr_bitfield_default }, + { "UNIPHY_CHANNEL3_INVERT", 15, 15, &umr_bitfield_default }, + { "UNIPHY_LANE_STAGGER_DELAY", 20, 22, &umr_bitfield_default }, + { "UNIPHY_LINK_ENABLE_HPD_MASK", 24, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUNIPHYF_CHANNEL_XBAR_CNTL[] = { + { "UNIPHY_CHANNEL0_XBAR_SOURCE", 0, 1, &umr_bitfield_default }, + { "UNIPHY_CHANNEL1_XBAR_SOURCE", 8, 9, &umr_bitfield_default }, + { "UNIPHY_CHANNEL2_XBAR_SOURCE", 16, 17, &umr_bitfield_default }, + { "UNIPHY_CHANNEL3_XBAR_SOURCE", 24, 25, &umr_bitfield_default }, + { "UNIPHY_LINK_ENABLE", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUNIPHYG_LINK_CNTL[] = { + { "UNIPHY_PFREQCHG", 0, 0, &umr_bitfield_default }, + { "UNIPHY_PIXVLD_RESET", 4, 4, &umr_bitfield_default }, + { "UNIPHY_MINIMUM_PIXVLD_LOW_DURATION", 8, 10, &umr_bitfield_default }, + { "UNIPHY_CHANNEL0_INVERT", 12, 12, &umr_bitfield_default }, + { "UNIPHY_CHANNEL1_INVERT", 13, 13, &umr_bitfield_default }, + { "UNIPHY_CHANNEL2_INVERT", 14, 14, &umr_bitfield_default }, + { "UNIPHY_CHANNEL3_INVERT", 15, 15, &umr_bitfield_default }, + { "UNIPHY_LANE_STAGGER_DELAY", 20, 22, &umr_bitfield_default }, + { "UNIPHY_LINK_ENABLE_HPD_MASK", 24, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUNIPHYG_CHANNEL_XBAR_CNTL[] = { + { "UNIPHY_CHANNEL0_XBAR_SOURCE", 0, 1, &umr_bitfield_default }, + { "UNIPHY_CHANNEL1_XBAR_SOURCE", 8, 9, &umr_bitfield_default }, + { "UNIPHY_CHANNEL2_XBAR_SOURCE", 16, 17, &umr_bitfield_default }, + { "UNIPHY_CHANNEL3_XBAR_SOURCE", 24, 25, &umr_bitfield_default }, + { "UNIPHY_LINK_ENABLE", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_WRCMD_DELAY[] = { + { "UNIPHY_DELAY", 0, 3, &umr_bitfield_default }, + { "DAC_DELAY", 4, 7, &umr_bitfield_default }, + { "DPHY_DELAY", 8, 11, &umr_bitfield_default }, + { "DCRXPHY_DELAY", 12, 15, &umr_bitfield_default }, + { "ZCAL_DELAY", 16, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_DVODATA_CONFIG[] = { + { "VIP_MUX_EN", 19, 19, &umr_bitfield_default }, + { "VIP_ALTER_MAPPING_EN", 20, 20, &umr_bitfield_default }, + { "DVO_ALTER_MAPPING_EN", 21, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmLVTMA_PWRSEQ_CNTL[] = { + { "LVTMA_PWRSEQ_EN", 0, 0, &umr_bitfield_default }, + { "LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN", 1, 1, &umr_bitfield_default }, + { "LVTMA_PWRSEQ_TARGET_STATE", 4, 4, &umr_bitfield_default }, + { "LVTMA_SYNCEN", 8, 8, &umr_bitfield_default }, + { "LVTMA_SYNCEN_OVRD", 9, 9, &umr_bitfield_default }, + { "LVTMA_SYNCEN_POL", 10, 10, &umr_bitfield_default }, + { "LVTMA_DIGON", 16, 16, &umr_bitfield_default }, + { "LVTMA_DIGON_OVRD", 17, 17, &umr_bitfield_default }, + { "LVTMA_DIGON_POL", 18, 18, &umr_bitfield_default }, + { "LVTMA_BLON", 24, 24, &umr_bitfield_default }, + { "LVTMA_BLON_OVRD", 25, 25, &umr_bitfield_default }, + { "LVTMA_BLON_POL", 26, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmLVTMA_PWRSEQ_STATE[] = { + { "LVTMA_PWRSEQ_TARGET_STATE_R", 0, 0, &umr_bitfield_default }, + { "LVTMA_PWRSEQ_DIGON", 1, 1, &umr_bitfield_default }, + { "LVTMA_PWRSEQ_SYNCEN", 2, 2, &umr_bitfield_default }, + { "LVTMA_PWRSEQ_BLON", 3, 3, &umr_bitfield_default }, + { "LVTMA_PWRSEQ_DONE", 4, 4, &umr_bitfield_default }, + { "LVTMA_PWRSEQ_STATE", 8, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmLVTMA_PWRSEQ_REF_DIV[] = { + { "LVTMA_PWRSEQ_REF_DIV", 0, 11, &umr_bitfield_default }, + { "BL_PWM_REF_DIV", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmLVTMA_PWRSEQ_DELAY1[] = { + { "LVTMA_PWRUP_DELAY1", 0, 7, &umr_bitfield_default }, + { "LVTMA_PWRUP_DELAY2", 8, 15, &umr_bitfield_default }, + { "LVTMA_PWRDN_DELAY1", 16, 23, &umr_bitfield_default }, + { "LVTMA_PWRDN_DELAY2", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmLVTMA_PWRSEQ_DELAY2[] = { + { "LVTMA_PWRDN_MIN_LENGTH", 0, 7, &umr_bitfield_default }, + { "LVTMA_PWRUP_DELAY3", 8, 15, &umr_bitfield_default }, + { "LVTMA_PWRDN_DELAY3", 16, 23, &umr_bitfield_default }, + { "LVTMA_VARY_BL_OVERRIDE_EN", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBL_PWM_CNTL[] = { + { "BL_ACTIVE_INT_FRAC_CNT", 0, 15, &umr_bitfield_default }, + { "BL_PWM_FRACTIONAL_EN", 30, 30, &umr_bitfield_default }, + { "BL_PWM_EN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBL_PWM_CNTL2[] = { + { "BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE", 0, 15, &umr_bitfield_default }, + { "BL_PWM_OVERRIDE_BL_OUT_ENABLE", 30, 30, &umr_bitfield_default }, + { "BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBL_PWM_PERIOD_CNTL[] = { + { "BL_PWM_PERIOD", 0, 15, &umr_bitfield_default }, + { "BL_PWM_PERIOD_BITCNT", 16, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBL_PWM_GRP1_REG_LOCK[] = { + { "BL_PWM_GRP1_REG_LOCK", 0, 0, &umr_bitfield_default }, + { "BL_PWM_GRP1_REG_UPDATE_PENDING", 8, 8, &umr_bitfield_default }, + { "BL_PWM_GRP1_UPDATE_AT_FRAME_START", 16, 16, &umr_bitfield_default }, + { "BL_PWM_GRP1_FRAME_START_DISP_SEL", 17, 19, &umr_bitfield_default }, + { "BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN", 24, 24, &umr_bitfield_default }, + { "BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_GSL_GENLK_PAD_CNTL[] = { + { "DCIO_GENLK_CLK_GSL_FLIP_READY_SEL", 4, 5, &umr_bitfield_default }, + { "DCIO_GENLK_CLK_GSL_MASK", 8, 9, &umr_bitfield_default }, + { "DCIO_GENLK_VSYNC_GSL_FLIP_READY_SEL", 20, 21, &umr_bitfield_default }, + { "DCIO_GENLK_VSYNC_GSL_MASK", 24, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_GSL_SWAPLOCK_PAD_CNTL[] = { + { "DCIO_SWAPLOCK_A_GSL_FLIP_READY_SEL", 4, 5, &umr_bitfield_default }, + { "DCIO_SWAPLOCK_A_GSL_MASK", 8, 9, &umr_bitfield_default }, + { "DCIO_SWAPLOCK_B_GSL_FLIP_READY_SEL", 20, 21, &umr_bitfield_default }, + { "DCIO_SWAPLOCK_B_GSL_MASK", 24, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_CLOCK_CNTL[] = { + { "DCIO_TEST_CLK_SEL", 0, 4, &umr_bitfield_default }, + { "DISPCLK_R_DCIO_GATE_DIS", 5, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIO_OTG_EXT_VSYNC_CNTL[] = { + { "DIO_OTG0_EXT_VSYNC_MUX", 0, 2, &umr_bitfield_default }, + { "DIO_OTG1_EXT_VSYNC_MUX", 4, 6, &umr_bitfield_default }, + { "DIO_OTG2_EXT_VSYNC_MUX", 8, 10, &umr_bitfield_default }, + { "DIO_OTG3_EXT_VSYNC_MUX", 12, 14, &umr_bitfield_default }, + { "DIO_OTG4_EXT_VSYNC_MUX", 16, 18, &umr_bitfield_default }, + { "DIO_OTG5_EXT_VSYNC_MUX", 20, 22, &umr_bitfield_default }, + { "DIO_SWAPLOCKB_EXT_VSYNC_MASK", 24, 26, &umr_bitfield_default }, + { "DIO_GENERICB_EXT_VSYNC_MASK", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_SOFT_RESET[] = { + { "UNIPHYA_SOFT_RESET", 0, 0, &umr_bitfield_default }, + { "DSYNCA_SOFT_RESET", 1, 1, &umr_bitfield_default }, + { "UNIPHYB_SOFT_RESET", 2, 2, &umr_bitfield_default }, + { "DSYNCB_SOFT_RESET", 3, 3, &umr_bitfield_default }, + { "UNIPHYC_SOFT_RESET", 4, 4, &umr_bitfield_default }, + { "DSYNCC_SOFT_RESET", 5, 5, &umr_bitfield_default }, + { "UNIPHYD_SOFT_RESET", 6, 6, &umr_bitfield_default }, + { "DSYNCD_SOFT_RESET", 7, 7, &umr_bitfield_default }, + { "UNIPHYE_SOFT_RESET", 8, 8, &umr_bitfield_default }, + { "DSYNCE_SOFT_RESET", 9, 9, &umr_bitfield_default }, + { "UNIPHYF_SOFT_RESET", 10, 10, &umr_bitfield_default }, + { "DSYNCF_SOFT_RESET", 11, 11, &umr_bitfield_default }, + { "UNIPHYG_SOFT_RESET", 12, 12, &umr_bitfield_default }, + { "DSYNCG_SOFT_RESET", 13, 13, &umr_bitfield_default }, + { "DACA_SOFT_RESET", 16, 16, &umr_bitfield_default }, + { "DCRXPHY_SOFT_RESET", 20, 20, &umr_bitfield_default }, + { "DPHY_SOFT_RESET", 24, 24, &umr_bitfield_default }, + { "ZCAL_SOFT_RESET", 26, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_DPHY_SEL[] = { + { "DPHY_LANE0_SEL", 0, 1, &umr_bitfield_default }, + { "DPHY_LANE1_SEL", 2, 3, &umr_bitfield_default }, + { "DPHY_LANE2_SEL", 4, 5, &umr_bitfield_default }, + { "DPHY_LANE3_SEL", 6, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUNIPHY_IMPCAL_LINKA[] = { + { "UNIPHY_IMPCAL_ENABLE_LINKA", 0, 0, &umr_bitfield_default }, + { "UNIPHY_IMPCAL_CALOUT_LINKA", 8, 8, &umr_bitfield_default }, + { "UNIPHY_CALOUT_ERROR_LINKA", 9, 9, &umr_bitfield_default }, + { "UNIPHY_CALOUT_ERROR_LINKA_AK", 10, 10, &umr_bitfield_default }, + { "UNIPHY_IMPCAL_VALUE_LINKA", 16, 19, &umr_bitfield_default }, + { "UNIPHY_IMPCAL_STEP_DELAY_LINKA", 20, 23, &umr_bitfield_default }, + { "UNIPHY_IMPCAL_OVERRIDE_LINKA", 24, 27, &umr_bitfield_default }, + { "UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA", 28, 28, &umr_bitfield_default }, + { "UNIPHY_IMPCAL_SEL_LINKA", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUNIPHY_IMPCAL_LINKB[] = { + { "UNIPHY_IMPCAL_ENABLE_LINKB", 0, 0, &umr_bitfield_default }, + { "UNIPHY_IMPCAL_CALOUT_LINKB", 8, 8, &umr_bitfield_default }, + { "UNIPHY_CALOUT_ERROR_LINKB", 9, 9, &umr_bitfield_default }, + { "UNIPHY_CALOUT_ERROR_LINKB_AK", 10, 10, &umr_bitfield_default }, + { "UNIPHY_IMPCAL_VALUE_LINKB", 16, 19, &umr_bitfield_default }, + { "UNIPHY_IMPCAL_STEP_DELAY_LINKB", 20, 23, &umr_bitfield_default }, + { "UNIPHY_IMPCAL_OVERRIDE_LINKB", 24, 27, &umr_bitfield_default }, + { "UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB", 28, 28, &umr_bitfield_default }, + { "UNIPHY_IMPCAL_SEL_LINKB", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUNIPHY_IMPCAL_PERIOD[] = { + { "UNIPHY_IMPCAL_PERIOD", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAUXP_IMPCAL[] = { + { "AUXP_IMPCAL_ENABLE", 0, 0, &umr_bitfield_default }, + { "AUXP_IMPCAL_CALOUT", 8, 8, &umr_bitfield_default }, + { "AUXP_CALOUT_ERROR", 9, 9, &umr_bitfield_default }, + { "AUXP_CALOUT_ERROR_AK", 10, 10, &umr_bitfield_default }, + { "AUXP_IMPCAL_VALUE", 16, 19, &umr_bitfield_default }, + { "AUXP_IMPCAL_STEP_DELAY", 20, 23, &umr_bitfield_default }, + { "AUXP_IMPCAL_OVERRIDE", 24, 27, &umr_bitfield_default }, + { "AUXP_IMPCAL_OVERRIDE_ENABLE", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmAUXN_IMPCAL[] = { + { "AUXN_IMPCAL_ENABLE", 0, 0, &umr_bitfield_default }, + { "AUXN_IMPCAL_CALOUT", 8, 8, &umr_bitfield_default }, + { "AUXN_CALOUT_ERROR", 9, 9, &umr_bitfield_default }, + { "AUXN_CALOUT_ERROR_AK", 10, 10, &umr_bitfield_default }, + { "AUXN_IMPCAL_VALUE", 16, 19, &umr_bitfield_default }, + { "AUXN_IMPCAL_STEP_DELAY", 20, 23, &umr_bitfield_default }, + { "AUXN_IMPCAL_OVERRIDE", 24, 27, &umr_bitfield_default }, + { "AUXN_IMPCAL_OVERRIDE_ENABLE", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_IMPCAL_CNTL[] = { + { "CALR_CNTL_OVERRIDE", 0, 3, &umr_bitfield_default }, + { "IMPCAL_SOFT_RESET", 5, 5, &umr_bitfield_default }, + { "IMPCAL_STATUS", 8, 9, &umr_bitfield_default }, + { "IMPCAL_ARB_STATE", 12, 14, &umr_bitfield_default }, + { "AUX_IMPCAL_INTERVAL", 15, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUNIPHY_IMPCAL_PSW_AB[] = { + { "UNIPHY_IMPCAL_PSW_LINKA", 0, 14, &umr_bitfield_default }, + { "UNIPHY_IMPCAL_PSW_LINKB", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUNIPHY_IMPCAL_LINKC[] = { + { "UNIPHY_IMPCAL_ENABLE_LINKC", 0, 0, &umr_bitfield_default }, + { "UNIPHY_IMPCAL_CALOUT_LINKC", 8, 8, &umr_bitfield_default }, + { "UNIPHY_CALOUT_ERROR_LINKC", 9, 9, &umr_bitfield_default }, + { "UNIPHY_CALOUT_ERROR_LINKC_AK", 10, 10, &umr_bitfield_default }, + { "UNIPHY_IMPCAL_VALUE_LINKC", 16, 19, &umr_bitfield_default }, + { "UNIPHY_IMPCAL_STEP_DELAY_LINKC", 20, 23, &umr_bitfield_default }, + { "UNIPHY_IMPCAL_OVERRIDE_LINKC", 24, 27, &umr_bitfield_default }, + { "UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC", 28, 28, &umr_bitfield_default }, + { "UNIPHY_IMPCAL_SEL_LINKC", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUNIPHY_IMPCAL_LINKD[] = { + { "UNIPHY_IMPCAL_ENABLE_LINKD", 0, 0, &umr_bitfield_default }, + { "UNIPHY_IMPCAL_CALOUT_LINKD", 8, 8, &umr_bitfield_default }, + { "UNIPHY_CALOUT_ERROR_LINKD", 9, 9, &umr_bitfield_default }, + { "UNIPHY_CALOUT_ERROR_LINKD_AK", 10, 10, &umr_bitfield_default }, + { "UNIPHY_IMPCAL_VALUE_LINKD", 16, 19, &umr_bitfield_default }, + { "UNIPHY_IMPCAL_STEP_DELAY_LINKD", 20, 23, &umr_bitfield_default }, + { "UNIPHY_IMPCAL_OVERRIDE_LINKD", 24, 27, &umr_bitfield_default }, + { "UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD", 28, 28, &umr_bitfield_default }, + { "UNIPHY_IMPCAL_SEL_LINKD", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_IMPCAL_CNTL_CD[] = { + { "CALR_CNTL_OVERRIDE", 0, 3, &umr_bitfield_default }, + { "IMPCAL_SOFT_RESET", 5, 5, &umr_bitfield_default }, + { "IMPCAL_STATUS", 8, 9, &umr_bitfield_default }, + { "IMPCAL_ARB_STATE", 12, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUNIPHY_IMPCAL_PSW_CD[] = { + { "UNIPHY_IMPCAL_PSW_LINKC", 0, 14, &umr_bitfield_default }, + { "UNIPHY_IMPCAL_PSW_LINKD", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUNIPHY_IMPCAL_LINKE[] = { + { "UNIPHY_IMPCAL_ENABLE_LINKE", 0, 0, &umr_bitfield_default }, + { "UNIPHY_IMPCAL_CALOUT_LINKE", 8, 8, &umr_bitfield_default }, + { "UNIPHY_CALOUT_ERROR_LINKE", 9, 9, &umr_bitfield_default }, + { "UNIPHY_CALOUT_ERROR_LINKE_AK", 10, 10, &umr_bitfield_default }, + { "UNIPHY_IMPCAL_VALUE_LINKE", 16, 19, &umr_bitfield_default }, + { "UNIPHY_IMPCAL_STEP_DELAY_LINKE", 20, 23, &umr_bitfield_default }, + { "UNIPHY_IMPCAL_OVERRIDE_LINKE", 24, 27, &umr_bitfield_default }, + { "UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE", 28, 28, &umr_bitfield_default }, + { "UNIPHY_IMPCAL_SEL_LINKE", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUNIPHY_IMPCAL_LINKF[] = { + { "UNIPHY_IMPCAL_ENABLE_LINKF", 0, 0, &umr_bitfield_default }, + { "UNIPHY_IMPCAL_CALOUT_LINKF", 8, 8, &umr_bitfield_default }, + { "UNIPHY_CALOUT_ERROR_LINKF", 9, 9, &umr_bitfield_default }, + { "UNIPHY_CALOUT_ERROR_LINKF_AK", 10, 10, &umr_bitfield_default }, + { "UNIPHY_IMPCAL_VALUE_LINKF", 16, 19, &umr_bitfield_default }, + { "UNIPHY_IMPCAL_STEP_DELAY_LINKF", 20, 23, &umr_bitfield_default }, + { "UNIPHY_IMPCAL_OVERRIDE_LINKF", 24, 27, &umr_bitfield_default }, + { "UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF", 28, 28, &umr_bitfield_default }, + { "UNIPHY_IMPCAL_SEL_LINKF", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_IMPCAL_CNTL_EF[] = { + { "CALR_CNTL_OVERRIDE", 0, 3, &umr_bitfield_default }, + { "IMPCAL_SOFT_RESET", 5, 5, &umr_bitfield_default }, + { "IMPCAL_STATUS", 8, 9, &umr_bitfield_default }, + { "IMPCAL_ARB_STATE", 12, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUNIPHY_IMPCAL_PSW_EF[] = { + { "UNIPHY_IMPCAL_PSW_LINKE", 0, 14, &umr_bitfield_default }, + { "UNIPHY_IMPCAL_PSW_LINKF", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_DPCS_TX_INTERRUPT[] = { + { "DCIO_DPCS_TXA_INT_TYPE", 0, 0, &umr_bitfield_default }, + { "DCIO_DPCS_TXA_INT_MASK", 1, 1, &umr_bitfield_default }, + { "DCIO_DPCS_TXA_INT_OCCUR", 2, 2, &umr_bitfield_default }, + { "DCIO_DPCS_TXB_INT_TYPE", 3, 3, &umr_bitfield_default }, + { "DCIO_DPCS_TXB_INT_MASK", 4, 4, &umr_bitfield_default }, + { "DCIO_DPCS_TXB_INT_OCCUR", 5, 5, &umr_bitfield_default }, + { "DCIO_DPCS_TXC_INT_TYPE", 6, 6, &umr_bitfield_default }, + { "DCIO_DPCS_TXC_INT_MASK", 7, 7, &umr_bitfield_default }, + { "DCIO_DPCS_TXC_INT_OCCUR", 8, 8, &umr_bitfield_default }, + { "DCIO_DPCS_TXD_INT_TYPE", 9, 9, &umr_bitfield_default }, + { "DCIO_DPCS_TXD_INT_MASK", 10, 10, &umr_bitfield_default }, + { "DCIO_DPCS_TXD_INT_OCCUR", 11, 11, &umr_bitfield_default }, + { "DCIO_DPCS_TXE_INT_TYPE", 12, 12, &umr_bitfield_default }, + { "DCIO_DPCS_TXE_INT_MASK", 13, 13, &umr_bitfield_default }, + { "DCIO_DPCS_TXE_INT_OCCUR", 14, 14, &umr_bitfield_default }, + { "DCIO_DPCS_TXF_INT_TYPE", 15, 15, &umr_bitfield_default }, + { "DCIO_DPCS_TXF_INT_MASK", 16, 16, &umr_bitfield_default }, + { "DCIO_DPCS_TXF_INT_OCCUR", 17, 17, &umr_bitfield_default }, + { "DCIO_DPCS_TXG_INT_TYPE", 18, 18, &umr_bitfield_default }, + { "DCIO_DPCS_TXG_INT_MASK", 19, 19, &umr_bitfield_default }, + { "DCIO_DPCS_TXG_INT_OCCUR", 20, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_DPCS_RX_INTERRUPT[] = { + { "DCIO_DPCS_RXA_INT_TYPE", 0, 0, &umr_bitfield_default }, + { "DCIO_DPCS_RXA_INT_MASK", 1, 1, &umr_bitfield_default }, + { "DCIO_DPCS_RXA_INT_OCCUR", 2, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_SEMAPHORE0[] = { + { "DCIO_SEMAPHORE0_REQ", 0, 15, &umr_bitfield_default }, + { "DCIO_SEMAPHORE0_GNT", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_SEMAPHORE1[] = { + { "DCIO_SEMAPHORE1_REQ", 0, 15, &umr_bitfield_default }, + { "DCIO_SEMAPHORE1_GNT", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_SEMAPHORE2[] = { + { "DCIO_SEMAPHORE2_REQ", 0, 15, &umr_bitfield_default }, + { "DCIO_SEMAPHORE2_GNT", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_SEMAPHORE3[] = { + { "DCIO_SEMAPHORE3_REQ", 0, 15, &umr_bitfield_default }, + { "DCIO_SEMAPHORE3_GNT", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_SEMAPHORE4[] = { + { "DCIO_SEMAPHORE4_REQ", 0, 15, &umr_bitfield_default }, + { "DCIO_SEMAPHORE4_GNT", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_SEMAPHORE5[] = { + { "DCIO_SEMAPHORE5_REQ", 0, 15, &umr_bitfield_default }, + { "DCIO_SEMAPHORE5_GNT", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_SEMAPHORE6[] = { + { "DCIO_SEMAPHORE6_REQ", 0, 15, &umr_bitfield_default }, + { "DCIO_SEMAPHORE6_GNT", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_SEMAPHORE7[] = { + { "DCIO_SEMAPHORE7_REQ", 0, 15, &umr_bitfield_default }, + { "DCIO_SEMAPHORE7_GNT", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_USBC_FLIP_EN_SEL[] = { + { "DCIO_UNIPHYA_USBC_FLIP_EN_SEL", 0, 2, &umr_bitfield_default }, + { "DCIO_UNIPHYB_USBC_FLIP_EN_SEL", 4, 6, &umr_bitfield_default }, + { "DCIO_UNIPHYC_USBC_FLIP_EN_SEL", 8, 10, &umr_bitfield_default }, + { "DCIO_UNIPHYD_USBC_FLIP_EN_SEL", 12, 14, &umr_bitfield_default }, + { "DCIO_UNIPHYE_USBC_FLIP_EN_SEL", 16, 18, &umr_bitfield_default }, + { "DCIO_UNIPHYF_USBC_FLIP_EN_SEL", 20, 22, &umr_bitfield_default }, + { "DCIO_FCH_DC_LINKA_USBC_DP_FLIP_EN", 24, 24, &umr_bitfield_default }, + { "DCIO_FCH_DC_LINKB_USBC_DP_FLIP_EN", 25, 25, &umr_bitfield_default }, + { "DCIO_FCH_DC_LINKC_USBC_DP_FLIP_EN", 26, 26, &umr_bitfield_default }, + { "DCIO_FCH_DC_LINKD_USBC_DP_FLIP_EN", 27, 27, &umr_bitfield_default }, + { "DCIO_FCH_DC_LINKE_USBC_DP_FLIP_EN", 28, 28, &umr_bitfield_default }, + { "DCIO_FCH_DC_LINKF_USBC_DP_FLIP_EN", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_GENERIC_MASK[] = { + { "DC_GPIO_GENERICA_MASK", 0, 0, &umr_bitfield_default }, + { "DC_GPIO_GENERICA_PD_DIS", 1, 1, &umr_bitfield_default }, + { "DC_GPIO_GENERICA_RECV", 2, 3, &umr_bitfield_default }, + { "DC_GPIO_GENERICB_MASK", 4, 4, &umr_bitfield_default }, + { "DC_GPIO_GENERICB_PD_DIS", 5, 5, &umr_bitfield_default }, + { "DC_GPIO_GENERICB_RECV", 6, 7, &umr_bitfield_default }, + { "DC_GPIO_GENERICC_MASK", 8, 8, &umr_bitfield_default }, + { "DC_GPIO_GENERICC_PD_DIS", 9, 9, &umr_bitfield_default }, + { "DC_GPIO_GENERICC_RECV", 10, 11, &umr_bitfield_default }, + { "DC_GPIO_GENERICD_MASK", 12, 12, &umr_bitfield_default }, + { "DC_GPIO_GENERICD_PD_DIS", 13, 13, &umr_bitfield_default }, + { "DC_GPIO_GENERICD_RECV", 14, 15, &umr_bitfield_default }, + { "DC_GPIO_GENERICE_MASK", 16, 16, &umr_bitfield_default }, + { "DC_GPIO_GENERICE_PD_DIS", 17, 17, &umr_bitfield_default }, + { "DC_GPIO_GENERICE_RECV", 18, 19, &umr_bitfield_default }, + { "DC_GPIO_GENERICF_MASK", 20, 20, &umr_bitfield_default }, + { "DC_GPIO_GENERICF_PD_DIS", 21, 21, &umr_bitfield_default }, + { "DC_GPIO_GENERICF_RECV", 22, 23, &umr_bitfield_default }, + { "DC_GPIO_GENERICG_MASK", 24, 24, &umr_bitfield_default }, + { "DC_GPIO_GENERICG_PD_DIS", 25, 25, &umr_bitfield_default }, + { "DC_GPIO_GENERICG_RECV", 26, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_GENERIC_A[] = { + { "DC_GPIO_GENERICA_A", 0, 0, &umr_bitfield_default }, + { "DC_GPIO_GENERICB_A", 8, 8, &umr_bitfield_default }, + { "DC_GPIO_GENERICC_A", 16, 16, &umr_bitfield_default }, + { "DC_GPIO_GENERICD_A", 20, 20, &umr_bitfield_default }, + { "DC_GPIO_GENERICE_A", 21, 21, &umr_bitfield_default }, + { "DC_GPIO_GENERICF_A", 22, 22, &umr_bitfield_default }, + { "DC_GPIO_GENERICG_A", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_GENERIC_EN[] = { + { "DC_GPIO_GENERICA_EN", 0, 0, &umr_bitfield_default }, + { "DC_GPIO_GENERICB_EN", 8, 8, &umr_bitfield_default }, + { "DC_GPIO_GENERICC_EN", 16, 16, &umr_bitfield_default }, + { "DC_GPIO_GENERICD_EN", 20, 20, &umr_bitfield_default }, + { "DC_GPIO_GENERICE_EN", 21, 21, &umr_bitfield_default }, + { "DC_GPIO_GENERICF_EN", 22, 22, &umr_bitfield_default }, + { "DC_GPIO_GENERICG_EN", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_GENERIC_Y[] = { + { "DC_GPIO_GENERICA_Y", 0, 0, &umr_bitfield_default }, + { "DC_GPIO_GENERICB_Y", 8, 8, &umr_bitfield_default }, + { "DC_GPIO_GENERICC_Y", 16, 16, &umr_bitfield_default }, + { "DC_GPIO_GENERICD_Y", 20, 20, &umr_bitfield_default }, + { "DC_GPIO_GENERICE_Y", 21, 21, &umr_bitfield_default }, + { "DC_GPIO_GENERICF_Y", 22, 22, &umr_bitfield_default }, + { "DC_GPIO_GENERICG_Y", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_DVODATA_MASK[] = { + { "DC_GPIO_DVODATA_MASK", 0, 23, &umr_bitfield_default }, + { "DC_GPIO_DVOCNTL_MASK", 24, 28, &umr_bitfield_default }, + { "DC_GPIO_DVOCLK_MASK", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_DVODATA_A[] = { + { "DC_GPIO_DVODATA_A", 0, 23, &umr_bitfield_default }, + { "DC_GPIO_DVOCNTL_A", 24, 28, &umr_bitfield_default }, + { "DC_GPIO_DVOCLK_A", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_DVODATA_EN[] = { + { "DC_GPIO_DVODATA_EN", 0, 23, &umr_bitfield_default }, + { "DC_GPIO_DVOCNTL_EN", 24, 28, &umr_bitfield_default }, + { "DC_GPIO_DVOCLK_EN", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_DVODATA_Y[] = { + { "DC_GPIO_DVODATA_Y", 0, 23, &umr_bitfield_default }, + { "DC_GPIO_DVOCNTL_Y", 24, 28, &umr_bitfield_default }, + { "DC_GPIO_DVOCLK_Y", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_DDC1_MASK[] = { + { "DC_GPIO_DDC1CLK_MASK", 0, 0, &umr_bitfield_default }, + { "DC_GPIO_DDC1CLK_PD_EN", 4, 4, &umr_bitfield_default }, + { "DC_GPIO_DDC1CLK_RECV", 6, 6, &umr_bitfield_default }, + { "DC_GPIO_DDC1DATA_MASK", 8, 8, &umr_bitfield_default }, + { "DC_GPIO_DDC1DATA_PD_EN", 12, 12, &umr_bitfield_default }, + { "DC_GPIO_DDC1DATA_RECV", 14, 14, &umr_bitfield_default }, + { "AUX_PAD1_MODE", 16, 16, &umr_bitfield_default }, + { "AUX1_POL", 20, 20, &umr_bitfield_default }, + { "ALLOW_HW_DDC1_PD_EN", 22, 22, &umr_bitfield_default }, + { "DC_GPIO_DDC1CLK_STR", 24, 27, &umr_bitfield_default }, + { "DC_GPIO_DDC1DATA_STR", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_DDC1_A[] = { + { "DC_GPIO_DDC1CLK_A", 0, 0, &umr_bitfield_default }, + { "DC_GPIO_DDC1DATA_A", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_DDC1_EN[] = { + { "DC_GPIO_DDC1CLK_EN", 0, 0, &umr_bitfield_default }, + { "DC_GPIO_DDC1DATA_EN", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_DDC1_Y[] = { + { "DC_GPIO_DDC1CLK_Y", 0, 0, &umr_bitfield_default }, + { "DC_GPIO_DDC1DATA_Y", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_DDC2_MASK[] = { + { "DC_GPIO_DDC2CLK_MASK", 0, 0, &umr_bitfield_default }, + { "DC_GPIO_DDC2CLK_PD_EN", 4, 4, &umr_bitfield_default }, + { "DC_GPIO_DDC2CLK_RECV", 6, 6, &umr_bitfield_default }, + { "DC_GPIO_DDC2DATA_MASK", 8, 8, &umr_bitfield_default }, + { "DC_GPIO_DDC2DATA_PD_EN", 12, 12, &umr_bitfield_default }, + { "DC_GPIO_DDC2DATA_RECV", 14, 14, &umr_bitfield_default }, + { "AUX_PAD2_MODE", 16, 16, &umr_bitfield_default }, + { "AUX2_POL", 20, 20, &umr_bitfield_default }, + { "ALLOW_HW_DDC2_PD_EN", 22, 22, &umr_bitfield_default }, + { "DC_GPIO_DDC2CLK_STR", 24, 27, &umr_bitfield_default }, + { "DC_GPIO_DDC2DATA_STR", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_DDC2_A[] = { + { "DC_GPIO_DDC2CLK_A", 0, 0, &umr_bitfield_default }, + { "DC_GPIO_DDC2DATA_A", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_DDC2_EN[] = { + { "DC_GPIO_DDC2CLK_EN", 0, 0, &umr_bitfield_default }, + { "DC_GPIO_DDC2DATA_EN", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_DDC2_Y[] = { + { "DC_GPIO_DDC2CLK_Y", 0, 0, &umr_bitfield_default }, + { "DC_GPIO_DDC2DATA_Y", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_DDC3_MASK[] = { + { "DC_GPIO_DDC3CLK_MASK", 0, 0, &umr_bitfield_default }, + { "DC_GPIO_DDC3CLK_PD_EN", 4, 4, &umr_bitfield_default }, + { "DC_GPIO_DDC3CLK_RECV", 6, 6, &umr_bitfield_default }, + { "DC_GPIO_DDC3DATA_MASK", 8, 8, &umr_bitfield_default }, + { "DC_GPIO_DDC3DATA_PD_EN", 12, 12, &umr_bitfield_default }, + { "DC_GPIO_DDC3DATA_RECV", 14, 14, &umr_bitfield_default }, + { "AUX_PAD3_MODE", 16, 16, &umr_bitfield_default }, + { "AUX3_POL", 20, 20, &umr_bitfield_default }, + { "ALLOW_HW_DDC3_PD_EN", 22, 22, &umr_bitfield_default }, + { "DC_GPIO_DDC3CLK_STR", 24, 27, &umr_bitfield_default }, + { "DC_GPIO_DDC3DATA_STR", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_DDC3_A[] = { + { "DC_GPIO_DDC3CLK_A", 0, 0, &umr_bitfield_default }, + { "DC_GPIO_DDC3DATA_A", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_DDC3_EN[] = { + { "DC_GPIO_DDC3CLK_EN", 0, 0, &umr_bitfield_default }, + { "DC_GPIO_DDC3DATA_EN", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_DDC3_Y[] = { + { "DC_GPIO_DDC3CLK_Y", 0, 0, &umr_bitfield_default }, + { "DC_GPIO_DDC3DATA_Y", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_DDC4_MASK[] = { + { "DC_GPIO_DDC4CLK_MASK", 0, 0, &umr_bitfield_default }, + { "DC_GPIO_DDC4CLK_PD_EN", 4, 4, &umr_bitfield_default }, + { "DC_GPIO_DDC4CLK_RECV", 6, 6, &umr_bitfield_default }, + { "DC_GPIO_DDC4DATA_MASK", 8, 8, &umr_bitfield_default }, + { "DC_GPIO_DDC4DATA_PD_EN", 12, 12, &umr_bitfield_default }, + { "DC_GPIO_DDC4DATA_RECV", 14, 14, &umr_bitfield_default }, + { "AUX_PAD4_MODE", 16, 16, &umr_bitfield_default }, + { "AUX4_POL", 20, 20, &umr_bitfield_default }, + { "ALLOW_HW_DDC4_PD_EN", 22, 22, &umr_bitfield_default }, + { "DC_GPIO_DDC4CLK_STR", 24, 27, &umr_bitfield_default }, + { "DC_GPIO_DDC4DATA_STR", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_DDC4_A[] = { + { "DC_GPIO_DDC4CLK_A", 0, 0, &umr_bitfield_default }, + { "DC_GPIO_DDC4DATA_A", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_DDC4_EN[] = { + { "DC_GPIO_DDC4CLK_EN", 0, 0, &umr_bitfield_default }, + { "DC_GPIO_DDC4DATA_EN", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_DDC4_Y[] = { + { "DC_GPIO_DDC4CLK_Y", 0, 0, &umr_bitfield_default }, + { "DC_GPIO_DDC4DATA_Y", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_DDC5_MASK[] = { + { "DC_GPIO_DDC5CLK_MASK", 0, 0, &umr_bitfield_default }, + { "DC_GPIO_DDC5CLK_PD_EN", 4, 4, &umr_bitfield_default }, + { "DC_GPIO_DDC5CLK_RECV", 6, 6, &umr_bitfield_default }, + { "DC_GPIO_DDC5DATA_MASK", 8, 8, &umr_bitfield_default }, + { "DC_GPIO_DDC5DATA_PD_EN", 12, 12, &umr_bitfield_default }, + { "DC_GPIO_DDC5DATA_RECV", 14, 14, &umr_bitfield_default }, + { "AUX_PAD5_MODE", 16, 16, &umr_bitfield_default }, + { "AUX5_POL", 20, 20, &umr_bitfield_default }, + { "ALLOW_HW_DDC5_PD_EN", 22, 22, &umr_bitfield_default }, + { "DC_GPIO_DDC5CLK_STR", 24, 27, &umr_bitfield_default }, + { "DC_GPIO_DDC5DATA_STR", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_DDC5_A[] = { + { "DC_GPIO_DDC5CLK_A", 0, 0, &umr_bitfield_default }, + { "DC_GPIO_DDC5DATA_A", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_DDC5_EN[] = { + { "DC_GPIO_DDC5CLK_EN", 0, 0, &umr_bitfield_default }, + { "DC_GPIO_DDC5DATA_EN", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_DDC5_Y[] = { + { "DC_GPIO_DDC5CLK_Y", 0, 0, &umr_bitfield_default }, + { "DC_GPIO_DDC5DATA_Y", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_DDC6_MASK[] = { + { "DC_GPIO_DDC6CLK_MASK", 0, 0, &umr_bitfield_default }, + { "DC_GPIO_DDC6CLK_PD_EN", 4, 4, &umr_bitfield_default }, + { "DC_GPIO_DDC6CLK_RECV", 6, 6, &umr_bitfield_default }, + { "DC_GPIO_DDC6DATA_MASK", 8, 8, &umr_bitfield_default }, + { "DC_GPIO_DDC6DATA_PD_EN", 12, 12, &umr_bitfield_default }, + { "DC_GPIO_DDC6DATA_RECV", 14, 14, &umr_bitfield_default }, + { "AUX_PAD6_MODE", 16, 16, &umr_bitfield_default }, + { "AUX6_POL", 20, 20, &umr_bitfield_default }, + { "ALLOW_HW_DDC6_PD_EN", 22, 22, &umr_bitfield_default }, + { "DC_GPIO_DDC6CLK_STR", 24, 27, &umr_bitfield_default }, + { "DC_GPIO_DDC6DATA_STR", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_DDC6_A[] = { + { "DC_GPIO_DDC6CLK_A", 0, 0, &umr_bitfield_default }, + { "DC_GPIO_DDC6DATA_A", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_DDC6_EN[] = { + { "DC_GPIO_DDC6CLK_EN", 0, 0, &umr_bitfield_default }, + { "DC_GPIO_DDC6DATA_EN", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_DDC6_Y[] = { + { "DC_GPIO_DDC6CLK_Y", 0, 0, &umr_bitfield_default }, + { "DC_GPIO_DDC6DATA_Y", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_DDCVGA_MASK[] = { + { "DC_GPIO_DDCVGACLK_MASK", 0, 0, &umr_bitfield_default }, + { "DC_GPIO_DDCVGACLK_RECV", 6, 6, &umr_bitfield_default }, + { "DC_GPIO_DDCVGADATA_MASK", 8, 8, &umr_bitfield_default }, + { "DC_GPIO_DDCVGADATA_PD_EN", 12, 12, &umr_bitfield_default }, + { "DC_GPIO_DDCVGADATA_RECV", 14, 14, &umr_bitfield_default }, + { "AUX_PADVGA_MODE", 16, 16, &umr_bitfield_default }, + { "AUXVGA_POL", 20, 20, &umr_bitfield_default }, + { "ALLOW_HW_DDCVGA_PD_EN", 22, 22, &umr_bitfield_default }, + { "DC_GPIO_DDCVGACLK_STR", 24, 27, &umr_bitfield_default }, + { "DC_GPIO_DDCVGADATA_STR", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_DDCVGA_A[] = { + { "DC_GPIO_DDCVGACLK_A", 0, 0, &umr_bitfield_default }, + { "DC_GPIO_DDCVGADATA_A", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_DDCVGA_EN[] = { + { "DC_GPIO_DDCVGACLK_EN", 0, 0, &umr_bitfield_default }, + { "DC_GPIO_DDCVGADATA_EN", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_DDCVGA_Y[] = { + { "DC_GPIO_DDCVGACLK_Y", 0, 0, &umr_bitfield_default }, + { "DC_GPIO_DDCVGADATA_Y", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_SYNCA_MASK[] = { + { "DC_GPIO_HSYNCA_MASK", 0, 0, &umr_bitfield_default }, + { "DC_GPIO_HSYNCA_PD_DIS", 4, 4, &umr_bitfield_default }, + { "DC_GPIO_HSYNCA_RECV", 6, 7, &umr_bitfield_default }, + { "DC_GPIO_VSYNCA_MASK", 8, 8, &umr_bitfield_default }, + { "DC_GPIO_VSYNCA_PD_DIS", 12, 12, &umr_bitfield_default }, + { "DC_GPIO_VSYNCA_RECV", 14, 15, &umr_bitfield_default }, + { "DC_GPIO_HSYNCA_OPTC_HSYNC_MASK", 24, 26, &umr_bitfield_default }, + { "DC_GPIO_VSYNCA_OPTC_VSYNC_MASK", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_SYNCA_A[] = { + { "DC_GPIO_HSYNCA_A", 0, 0, &umr_bitfield_default }, + { "DC_GPIO_VSYNCA_A", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_SYNCA_EN[] = { + { "DC_GPIO_HSYNCA_EN", 0, 0, &umr_bitfield_default }, + { "DC_GPIO_VSYNCA_EN", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_SYNCA_Y[] = { + { "DC_GPIO_HSYNCA_Y", 0, 0, &umr_bitfield_default }, + { "DC_GPIO_VSYNCA_Y", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_GENLK_MASK[] = { + { "DC_GPIO_GENLK_CLK_MASK", 0, 0, &umr_bitfield_default }, + { "DC_GPIO_GENLK_CLK_PD_DIS", 1, 1, &umr_bitfield_default }, + { "DC_GPIO_GENLK_CLK_PU_EN", 3, 3, &umr_bitfield_default }, + { "DC_GPIO_GENLK_CLK_RECV", 4, 5, &umr_bitfield_default }, + { "DC_GPIO_GENLK_VSYNC_MASK", 8, 8, &umr_bitfield_default }, + { "DC_GPIO_GENLK_VSYNC_PD_DIS", 9, 9, &umr_bitfield_default }, + { "DC_GPIO_GENLK_VSYNC_PU_EN", 11, 11, &umr_bitfield_default }, + { "DC_GPIO_GENLK_VSYNC_RECV", 12, 13, &umr_bitfield_default }, + { "DC_GPIO_SWAPLOCK_A_MASK", 16, 16, &umr_bitfield_default }, + { "DC_GPIO_SWAPLOCK_A_PD_DIS", 17, 17, &umr_bitfield_default }, + { "DC_GPIO_SWAPLOCK_A_PU_EN", 19, 19, &umr_bitfield_default }, + { "DC_GPIO_SWAPLOCK_A_RECV", 20, 21, &umr_bitfield_default }, + { "DC_GPIO_SWAPLOCK_B_MASK", 24, 24, &umr_bitfield_default }, + { "DC_GPIO_SWAPLOCK_B_PD_DIS", 25, 25, &umr_bitfield_default }, + { "DC_GPIO_SWAPLOCK_B_PU_EN", 27, 27, &umr_bitfield_default }, + { "DC_GPIO_SWAPLOCK_B_RECV", 28, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_GENLK_A[] = { + { "DC_GPIO_GENLK_CLK_A", 0, 0, &umr_bitfield_default }, + { "DC_GPIO_GENLK_VSYNC_A", 8, 8, &umr_bitfield_default }, + { "DC_GPIO_SWAPLOCK_A_A", 16, 16, &umr_bitfield_default }, + { "DC_GPIO_SWAPLOCK_B_A", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_GENLK_EN[] = { + { "DC_GPIO_GENLK_CLK_EN", 0, 0, &umr_bitfield_default }, + { "DC_GPIO_GENLK_VSYNC_EN", 8, 8, &umr_bitfield_default }, + { "DC_GPIO_SWAPLOCK_A_EN", 16, 16, &umr_bitfield_default }, + { "DC_GPIO_SWAPLOCK_B_EN", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_GENLK_Y[] = { + { "DC_GPIO_GENLK_CLK_Y", 0, 0, &umr_bitfield_default }, + { "DC_GPIO_GENLK_VSYNC_Y", 8, 8, &umr_bitfield_default }, + { "DC_GPIO_SWAPLOCK_A_Y", 16, 16, &umr_bitfield_default }, + { "DC_GPIO_SWAPLOCK_B_Y", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_HPD_MASK[] = { + { "DC_GPIO_HPD1_MASK", 0, 0, &umr_bitfield_default }, + { "DC_GPIO_RX_HPD_MASK", 1, 1, &umr_bitfield_default }, + { "DC_GPIO_RX_HPD_PD_DIS", 2, 2, &umr_bitfield_default }, + { "DC_GPIO_RX_HPD_RX_SEL", 3, 3, &umr_bitfield_default }, + { "DC_GPIO_HPD1_PD_DIS", 4, 4, &umr_bitfield_default }, + { "DC_GPIO_HPD1_RECV", 6, 7, &umr_bitfield_default }, + { "DC_GPIO_HPD2_MASK", 8, 8, &umr_bitfield_default }, + { "DC_GPIO_HPD2_PD_DIS", 9, 9, &umr_bitfield_default }, + { "DC_GPIO_HPD2_RECV", 10, 11, &umr_bitfield_default }, + { "DC_GPIO_HPD3_MASK", 16, 16, &umr_bitfield_default }, + { "DC_GPIO_HPD3_PD_DIS", 17, 17, &umr_bitfield_default }, + { "DC_GPIO_HPD3_RECV", 18, 19, &umr_bitfield_default }, + { "DC_GPIO_HPD4_MASK", 20, 20, &umr_bitfield_default }, + { "DC_GPIO_HPD4_PD_DIS", 21, 21, &umr_bitfield_default }, + { "DC_GPIO_HPD4_RECV", 22, 23, &umr_bitfield_default }, + { "DC_GPIO_HPD5_MASK", 24, 24, &umr_bitfield_default }, + { "DC_GPIO_HPD5_PD_DIS", 25, 25, &umr_bitfield_default }, + { "DC_GPIO_HPD5_RECV", 26, 27, &umr_bitfield_default }, + { "DC_GPIO_HPD6_MASK", 28, 28, &umr_bitfield_default }, + { "DC_GPIO_HPD6_PD_DIS", 29, 29, &umr_bitfield_default }, + { "DC_GPIO_HPD6_RECV", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_HPD_A[] = { + { "DC_GPIO_HPD1_A", 0, 0, &umr_bitfield_default }, + { "DC_GPIO_HPD2_A", 8, 8, &umr_bitfield_default }, + { "DC_GPIO_HPD3_A", 16, 16, &umr_bitfield_default }, + { "DC_GPIO_HPD4_A", 24, 24, &umr_bitfield_default }, + { "DC_GPIO_HPD5_A", 26, 26, &umr_bitfield_default }, + { "DC_GPIO_HPD6_A", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_HPD_EN[] = { + { "DC_GPIO_HPD1_EN", 0, 0, &umr_bitfield_default }, + { "HPD1_SCHMEN_PI", 1, 1, &umr_bitfield_default }, + { "HPD1_SLEWNCORE", 2, 2, &umr_bitfield_default }, + { "RX_HPD_SCHMEN_PI", 3, 3, &umr_bitfield_default }, + { "RX_HPD_SLEWNCORE", 4, 4, &umr_bitfield_default }, + { "HPD12_SPARE0", 5, 5, &umr_bitfield_default }, + { "HPD1_SEL0", 6, 6, &umr_bitfield_default }, + { "RX_HPD_SEL0", 7, 7, &umr_bitfield_default }, + { "DC_GPIO_HPD2_EN", 8, 8, &umr_bitfield_default }, + { "HPD2_SCHMEN_PI", 9, 9, &umr_bitfield_default }, + { "HPD12_SPARE1", 10, 10, &umr_bitfield_default }, + { "DC_GPIO_HPD3_EN", 16, 16, &umr_bitfield_default }, + { "HPD3_SCHMEN_PI", 17, 17, &umr_bitfield_default }, + { "HPD34_SPARE0", 18, 18, &umr_bitfield_default }, + { "DC_GPIO_HPD4_EN", 20, 20, &umr_bitfield_default }, + { "HPD4_SCHMEN_PI", 21, 21, &umr_bitfield_default }, + { "HPD34_SPARE1", 22, 22, &umr_bitfield_default }, + { "DC_GPIO_HPD5_EN", 24, 24, &umr_bitfield_default }, + { "HPD5_SCHMEN_PI", 25, 25, &umr_bitfield_default }, + { "HPD56_SPARE0", 26, 26, &umr_bitfield_default }, + { "DC_GPIO_HPD6_EN", 28, 28, &umr_bitfield_default }, + { "HPD6_SCHMEN_PI", 29, 29, &umr_bitfield_default }, + { "HPD56_SPARE1", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_HPD_Y[] = { + { "DC_GPIO_HPD1_Y", 0, 0, &umr_bitfield_default }, + { "DC_GPIO_HPD2_Y", 8, 8, &umr_bitfield_default }, + { "DC_GPIO_HPD3_Y", 16, 16, &umr_bitfield_default }, + { "DC_GPIO_HPD4_Y", 24, 24, &umr_bitfield_default }, + { "DC_GPIO_HPD5_Y", 26, 26, &umr_bitfield_default }, + { "DC_GPIO_HPD6_Y", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_PWRSEQ_MASK[] = { + { "DC_GPIO_BLON_MASK", 0, 0, &umr_bitfield_default }, + { "DC_GPIO_BLON_PD_DIS", 4, 4, &umr_bitfield_default }, + { "DC_GPIO_BLON_RECV", 6, 7, &umr_bitfield_default }, + { "DC_GPIO_DIGON_MASK", 8, 8, &umr_bitfield_default }, + { "DC_GPIO_DIGON_PD_DIS", 12, 12, &umr_bitfield_default }, + { "DC_GPIO_DIGON_RECV", 14, 15, &umr_bitfield_default }, + { "DC_GPIO_ENA_BL_MASK", 16, 16, &umr_bitfield_default }, + { "DC_GPIO_ENA_BL_PD_DIS", 20, 20, &umr_bitfield_default }, + { "DC_GPIO_ENA_BL_RECV", 22, 23, &umr_bitfield_default }, + { "DC_GPIO_VSYNC_IN_MASK", 24, 24, &umr_bitfield_default }, + { "DC_GPIO_VSYNC_IN_PD_DIS", 25, 25, &umr_bitfield_default }, + { "DC_GPIO_VSYNC_IN_RECV", 26, 26, &umr_bitfield_default }, + { "DC_GPIO_HSYNC_IN_MASK", 28, 28, &umr_bitfield_default }, + { "DC_GPIO_HSYNC_IN_PD_DIS", 29, 29, &umr_bitfield_default }, + { "DC_GPIO_HSYNC_IN_RECV", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_PWRSEQ_A[] = { + { "DC_GPIO_BLON_A", 0, 0, &umr_bitfield_default }, + { "DC_GPIO_DIGON_A", 8, 8, &umr_bitfield_default }, + { "DC_GPIO_ENA_BL_A", 16, 16, &umr_bitfield_default }, + { "DC_GPIO_VSYNC_IN_A", 24, 24, &umr_bitfield_default }, + { "DC_GPIO_HSYNC_IN_A", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_PWRSEQ_EN[] = { + { "DC_GPIO_BLON_EN", 0, 0, &umr_bitfield_default }, + { "DC_GPIO_VARY_BL_GENERICA_EN", 1, 1, &umr_bitfield_default }, + { "DC_GPIO_DIGON_EN", 8, 8, &umr_bitfield_default }, + { "DC_GPIO_ENA_BL_EN", 16, 16, &umr_bitfield_default }, + { "DC_GPIO_VSYNC_IN_EN", 24, 24, &umr_bitfield_default }, + { "DC_GPIO_HSYNC_IN_EN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_PWRSEQ_Y[] = { + { "DC_GPIO_BLON_Y", 0, 0, &umr_bitfield_default }, + { "DC_GPIO_DIGON_Y", 8, 8, &umr_bitfield_default }, + { "DC_GPIO_ENA_BL_Y", 16, 16, &umr_bitfield_default }, + { "DC_GPIO_VSYNC_IN", 24, 24, &umr_bitfield_default }, + { "DC_GPIO_HSYNC_IN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_PAD_STRENGTH_1[] = { + { "GENLK_STRENGTH_SN", 0, 3, &umr_bitfield_default }, + { "GENLK_STRENGTH_SP", 4, 7, &umr_bitfield_default }, + { "RX_HPD_STRENGTH_SN", 8, 11, &umr_bitfield_default }, + { "RX_HPD_STRENGTH_SP", 12, 15, &umr_bitfield_default }, + { "TX_HPD_STRENGTH_SN", 16, 19, &umr_bitfield_default }, + { "TX_HPD_STRENGTH_SP", 20, 23, &umr_bitfield_default }, + { "SYNC_STRENGTH_SN", 24, 27, &umr_bitfield_default }, + { "SYNC_STRENGTH_SP", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_PAD_STRENGTH_2[] = { + { "STRENGTH_SN", 0, 3, &umr_bitfield_default }, + { "STRENGTH_SP", 4, 7, &umr_bitfield_default }, + { "EXT_RESET_DRVSTRENGTH", 8, 10, &umr_bitfield_default }, + { "REF_27_DRVSTRENGTH", 12, 14, &umr_bitfield_default }, + { "PWRSEQ_STRENGTH_SN", 16, 19, &umr_bitfield_default }, + { "PWRSEQ_STRENGTH_SP", 20, 23, &umr_bitfield_default }, + { "REF_27_SRC_SEL", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPHY_AUX_CNTL[] = { + { "AUXSLAVE_PAD_SLEWN", 0, 0, &umr_bitfield_default }, + { "AUXSLAVE_PAD_WAKE", 1, 1, &umr_bitfield_default }, + { "AUXSLAVE_PAD_RXSEL", 2, 2, &umr_bitfield_default }, + { "AUXSLAVE_PAD_MODE", 3, 3, &umr_bitfield_default }, + { "DDCSLAVE_DATA_PD_EN", 4, 4, &umr_bitfield_default }, + { "DDCSLAVE_DATA_EN", 5, 5, &umr_bitfield_default }, + { "DDCSLAVE_CLK_PD_EN", 6, 6, &umr_bitfield_default }, + { "DDCSLAVE_CLK_EN", 7, 7, &umr_bitfield_default }, + { "AUX_PAD_SLEWN", 12, 12, &umr_bitfield_default }, + { "AUXSLAVE_CLK_PD_EN", 13, 13, &umr_bitfield_default }, + { "AUX_PAD_WAKE", 14, 14, &umr_bitfield_default }, + { "AUX_PAD_RXSEL", 16, 17, &umr_bitfield_default }, + { "AUX_CAL_BIASENTST", 20, 22, &umr_bitfield_default }, + { "AUX_CAL_RESBIASEN", 23, 23, &umr_bitfield_default }, + { "AUX_CAL_SPARE", 24, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_I2CPAD_MASK[] = { + { "DC_GPIO_SCL_MASK", 0, 0, &umr_bitfield_default }, + { "DC_GPIO_SCL_PD_DIS", 1, 1, &umr_bitfield_default }, + { "DC_GPIO_SCL_RECV", 2, 2, &umr_bitfield_default }, + { "DC_GPIO_SDA_MASK", 4, 4, &umr_bitfield_default }, + { "DC_GPIO_SDA_PD_DIS", 5, 5, &umr_bitfield_default }, + { "DC_GPIO_SDA_RECV", 6, 6, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_I2CPAD_A[] = { + { "DC_GPIO_SCL_A", 0, 0, &umr_bitfield_default }, + { "DC_GPIO_SDA_A", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_I2CPAD_EN[] = { + { "DC_GPIO_SCL_EN", 0, 0, &umr_bitfield_default }, + { "DC_GPIO_SDA_EN", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_I2CPAD_Y[] = { + { "DC_GPIO_SCL_Y", 0, 0, &umr_bitfield_default }, + { "DC_GPIO_SDA_Y", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_I2CPAD_STRENGTH[] = { + { "I2C_STRENGTH_SN", 0, 3, &umr_bitfield_default }, + { "I2C_STRENGTH_SP", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDVO_STRENGTH_CONTROL[] = { + { "DVO_SP", 0, 3, &umr_bitfield_default }, + { "DVO_SN", 4, 7, &umr_bitfield_default }, + { "DVOCLK_SP", 8, 11, &umr_bitfield_default }, + { "DVOCLK_SN", 12, 15, &umr_bitfield_default }, + { "DVO_DRVSTRENGTH", 16, 18, &umr_bitfield_default }, + { "DVOCLK_DRVSTRENGTH", 20, 22, &umr_bitfield_default }, + { "FLDO_VITNE_DRVSTRENGTH", 24, 26, &umr_bitfield_default }, + { "DVO_LSB_VMODE", 28, 28, &umr_bitfield_default }, + { "DVO_MSB_VMODE", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDVO_VREF_CONTROL[] = { + { "DVO_VREFPON", 0, 0, &umr_bitfield_default }, + { "DVO_VREFSEL", 1, 1, &umr_bitfield_default }, + { "DVO_VREFCAL", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDVO_SKEW_ADJUST[] = { + { "DVO_SKEW_ADJUST", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_I2S_SPDIF_MASK[] = { + { "DC_GPIO_I2SDATA0_MASK", 0, 3, &umr_bitfield_default }, + { "DC_GPIO_MCLK0_MASK", 4, 4, &umr_bitfield_default }, + { "DC_GPIO_BCLK0_MASK", 5, 5, &umr_bitfield_default }, + { "DC_GPIO_LRCK0_MASK", 6, 6, &umr_bitfield_default }, + { "DC_GPIO_SPDIF0_MASK", 7, 7, &umr_bitfield_default }, + { "DC_GPIO_I2SDATA1_MASK", 8, 8, &umr_bitfield_default }, + { "DC_GPIO_MCLK1_MASK", 9, 9, &umr_bitfield_default }, + { "DC_GPIO_BCLK1_MASK", 10, 10, &umr_bitfield_default }, + { "DC_GPIO_LRCK1_MASK", 11, 11, &umr_bitfield_default }, + { "DC_GPIO_SPDIF1_MASK", 12, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_I2S_SPDIF_A[] = { + { "DC_GPIO_I2SDATA0_A", 0, 3, &umr_bitfield_default }, + { "DC_GPIO_MCLK0_A", 4, 4, &umr_bitfield_default }, + { "DC_GPIO_BCLK0_A", 5, 5, &umr_bitfield_default }, + { "DC_GPIO_LRCK0_A", 6, 6, &umr_bitfield_default }, + { "DC_GPIO_SPDIF0_A", 7, 7, &umr_bitfield_default }, + { "DC_GPIO_I2SDATA1_A", 8, 8, &umr_bitfield_default }, + { "DC_GPIO_MCLK1_A", 9, 9, &umr_bitfield_default }, + { "DC_GPIO_BCLK1_A", 10, 10, &umr_bitfield_default }, + { "DC_GPIO_LRCK1_A", 11, 11, &umr_bitfield_default }, + { "DC_GPIO_SPDIF1_A", 12, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_I2S_SPDIF_EN[] = { + { "DC_GPIO_I2SDATA0_EN", 0, 3, &umr_bitfield_default }, + { "DC_GPIO_MCLK0_EN", 4, 4, &umr_bitfield_default }, + { "DC_GPIO_BCLK0_EN", 5, 5, &umr_bitfield_default }, + { "DC_GPIO_LRCK0_EN", 6, 6, &umr_bitfield_default }, + { "DC_GPIO_SPDIF0_EN", 7, 7, &umr_bitfield_default }, + { "DC_GPIO_I2SDATA1_EN", 8, 8, &umr_bitfield_default }, + { "DC_GPIO_MCLK1_EN", 9, 9, &umr_bitfield_default }, + { "DC_GPIO_BCLK1_EN", 10, 10, &umr_bitfield_default }, + { "DC_GPIO_LRCK1_EN", 11, 11, &umr_bitfield_default }, + { "DC_GPIO_SPDIF1_EN", 12, 12, &umr_bitfield_default }, + { "SPDIF1_APORT", 13, 13, &umr_bitfield_default }, + { "SPDIF1_PU", 14, 14, &umr_bitfield_default }, + { "SPDIF1_RXSEL", 15, 15, &umr_bitfield_default }, + { "SPDIF1_SCHMEN", 16, 16, &umr_bitfield_default }, + { "SPDIF1_SMODE_EN", 17, 17, &umr_bitfield_default }, + { "SPDIF1_IMODE", 18, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_I2S_SPDIF_Y[] = { + { "DC_GPIO_I2SDATA0_Y", 0, 3, &umr_bitfield_default }, + { "DC_GPIO_MCLK0_Y", 4, 4, &umr_bitfield_default }, + { "DC_GPIO_BCLK0_Y", 5, 5, &umr_bitfield_default }, + { "DC_GPIO_LRCK0_Y", 6, 6, &umr_bitfield_default }, + { "DC_GPIO_SPDIF0_Y", 7, 7, &umr_bitfield_default }, + { "DC_GPIO_I2SDATA1_Y", 8, 8, &umr_bitfield_default }, + { "DC_GPIO_MCLK1_Y", 9, 9, &umr_bitfield_default }, + { "DC_GPIO_BCLK1_Y", 10, 10, &umr_bitfield_default }, + { "DC_GPIO_LRCK1_Y", 11, 11, &umr_bitfield_default }, + { "DC_GPIO_SPDIF1_Y", 12, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_I2S_SPDIF_STRENGTH[] = { + { "I2S0_DRVSTRENGTH", 0, 2, &umr_bitfield_default }, + { "SPDIF0_DRVSTRENGTH_SN", 8, 10, &umr_bitfield_default }, + { "SPDIF0_DRVSTRENGTH_SP", 11, 13, &umr_bitfield_default }, + { "I2S1_DRVSTRENGTH", 16, 18, &umr_bitfield_default }, + { "SPDIF1_DRVSTRENGTH_SN", 24, 26, &umr_bitfield_default }, + { "SPDIF1_DRVSTRENGTH_SP", 27, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_TX12_EN[] = { + { "DC_GPIO_BLON_TX12_EN", 0, 0, &umr_bitfield_default }, + { "DC_GPIO_DIGON_TX12_EN", 1, 1, &umr_bitfield_default }, + { "DC_GPIO_ENA_BL_TX12_EN", 2, 2, &umr_bitfield_default }, + { "DC_GPIO_GENERICA_TX12_EN", 3, 3, &umr_bitfield_default }, + { "DC_GPIO_GENERICB_TX12_EN", 4, 4, &umr_bitfield_default }, + { "DC_GPIO_GENERICC_TX12_EN", 5, 5, &umr_bitfield_default }, + { "DC_GPIO_GENERICD_TX12_EN", 6, 6, &umr_bitfield_default }, + { "DC_GPIO_GENERICE_TX12_EN", 7, 7, &umr_bitfield_default }, + { "DC_GPIO_GENERICF_TX12_EN", 8, 8, &umr_bitfield_default }, + { "DC_GPIO_GENERICG_TX12_EN", 9, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_AUX_CTRL_0[] = { + { "DC_GPIO_AUX1_FALLSLEWSEL", 0, 1, &umr_bitfield_default }, + { "DC_GPIO_AUX2_FALLSLEWSEL", 2, 3, &umr_bitfield_default }, + { "DC_GPIO_AUX3_FALLSLEWSEL", 4, 5, &umr_bitfield_default }, + { "DC_GPIO_AUX4_FALLSLEWSEL", 6, 7, &umr_bitfield_default }, + { "DC_GPIO_AUX5_FALLSLEWSEL", 8, 9, &umr_bitfield_default }, + { "DC_GPIO_AUX6_FALLSLEWSEL", 10, 11, &umr_bitfield_default }, + { "DC_GPIO_DDCVGA_FALLSLEWSEL", 12, 13, &umr_bitfield_default }, + { "DC_GPIO_GENI2C_FALLSLEWSEL", 14, 15, &umr_bitfield_default }, + { "DC_GPIO_AUX1_SPIKERCEN", 16, 16, &umr_bitfield_default }, + { "DC_GPIO_AUX2_SPIKERCEN", 17, 17, &umr_bitfield_default }, + { "DC_GPIO_AUX3_SPIKERCEN", 18, 18, &umr_bitfield_default }, + { "DC_GPIO_AUX4_SPIKERCEN", 19, 19, &umr_bitfield_default }, + { "DC_GPIO_AUX5_SPIKERCEN", 20, 20, &umr_bitfield_default }, + { "DC_GPIO_AUX6_SPIKERCEN", 21, 21, &umr_bitfield_default }, + { "DC_GPIO_DDCVGA_SPIKERCEN", 22, 22, &umr_bitfield_default }, + { "DC_GPIO_GENI2C_SPIKERCEN", 23, 23, &umr_bitfield_default }, + { "DC_GPIO_AUX1_SPIKERCSEL", 24, 24, &umr_bitfield_default }, + { "DC_GPIO_AUX2_SPIKERCSEL", 25, 25, &umr_bitfield_default }, + { "DC_GPIO_AUX3_SPIKERCSEL", 26, 26, &umr_bitfield_default }, + { "DC_GPIO_AUX4_SPIKERCSEL", 27, 27, &umr_bitfield_default }, + { "DC_GPIO_AUX5_SPIKERCSEL", 28, 28, &umr_bitfield_default }, + { "DC_GPIO_AUX6_SPIKERCSEL", 29, 29, &umr_bitfield_default }, + { "DC_GPIO_DDCVGA_SPIKERCSEL", 30, 30, &umr_bitfield_default }, + { "DC_GPIO_GENI2C_SPIKERCSEL", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_AUX_CTRL_1[] = { + { "DC_GPIO_AUX_CSEL_0P9", 0, 0, &umr_bitfield_default }, + { "DC_GPIO_AUX_CSEL_1P1", 1, 1, &umr_bitfield_default }, + { "DC_GPIO_AUX_RSEL_0P9", 2, 2, &umr_bitfield_default }, + { "DC_GPIO_AUX_RSEL_1P1", 3, 3, &umr_bitfield_default }, + { "DC_GPIO_I2C_CSEL_0P9", 4, 4, &umr_bitfield_default }, + { "DC_GPIO_I2C_CSEL_1P1", 5, 5, &umr_bitfield_default }, + { "DC_GPIO_I2C_RSEL_0P9", 6, 6, &umr_bitfield_default }, + { "DC_GPIO_I2C_RSEL_1P1", 7, 7, &umr_bitfield_default }, + { "DC_GPIO_AUX_BIASCRTEN", 8, 8, &umr_bitfield_default }, + { "DC_GPIO_I2C_BIASCRTEN", 9, 9, &umr_bitfield_default }, + { "DC_GPIO_AUX_RESBIASEN", 10, 10, &umr_bitfield_default }, + { "DC_GPIO_I2C_RESBIASEN", 11, 11, &umr_bitfield_default }, + { "DC_GPIO_AUX1_COMPSEL", 12, 12, &umr_bitfield_default }, + { "DC_GPIO_GENI2C_COMPSEL", 13, 13, &umr_bitfield_default }, + { "DC_GPIO_DDCVGA_SPARE", 14, 15, &umr_bitfield_default }, + { "DC_GPIO_GENI2C_SPARE", 16, 17, &umr_bitfield_default }, + { "DC_GPIO_DDCVGA_SLEWN", 18, 18, &umr_bitfield_default }, + { "DC_GPIO_GENI2C_SLEWN", 19, 19, &umr_bitfield_default }, + { "DC_GPIO_DDCVGA_RXSEL", 20, 21, &umr_bitfield_default }, + { "DC_GPIO_GENI2C_RXSEL", 22, 23, &umr_bitfield_default }, + { "DC_GPIO_GENI2C_PDEN", 24, 24, &umr_bitfield_default }, + { "DC_GPIO_AUX2_COMPSEL", 25, 25, &umr_bitfield_default }, + { "DC_GPIO_AUX3_COMPSEL", 26, 26, &umr_bitfield_default }, + { "DC_GPIO_AUX4_COMPSEL", 27, 27, &umr_bitfield_default }, + { "DC_GPIO_AUX5_COMPSEL", 28, 28, &umr_bitfield_default }, + { "DC_GPIO_AUX6_COMPSEL", 29, 29, &umr_bitfield_default }, + { "DC_GPIO_DDCVGA_COMPSEL", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_AUX_CTRL_2[] = { + { "DC_GPIO_HPD12_FALLSLEWSEL", 0, 1, &umr_bitfield_default }, + { "DC_GPIO_HPD34_FALLSLEWSEL", 2, 3, &umr_bitfield_default }, + { "DC_GPIO_HPD56_FALLSLEWSEL", 4, 5, &umr_bitfield_default }, + { "DC_GPIO_HPD12_SPIKERCEN", 8, 8, &umr_bitfield_default }, + { "DC_GPIO_HPD34_SPIKERCEN", 9, 9, &umr_bitfield_default }, + { "DC_GPIO_HPD56_SPIKERCEN", 10, 10, &umr_bitfield_default }, + { "DC_GPIO_HPD12_SPIKERCSEL", 12, 12, &umr_bitfield_default }, + { "DC_GPIO_HPD34_SPIKERCSEL", 13, 13, &umr_bitfield_default }, + { "DC_GPIO_HPD56_SPIKERCSEL", 14, 14, &umr_bitfield_default }, + { "DC_GPIO_HPD_CSEL_0P9", 16, 16, &umr_bitfield_default }, + { "DC_GPIO_HPD_CSEL_1P1", 17, 17, &umr_bitfield_default }, + { "DC_GPIO_HPD_RSEL_0P9", 18, 18, &umr_bitfield_default }, + { "DC_GPIO_HPD_RSEL_1P1", 19, 19, &umr_bitfield_default }, + { "DC_GPIO_HPD_BIASCRTEN", 20, 20, &umr_bitfield_default }, + { "DC_GPIO_HPD12_SLEWN", 24, 24, &umr_bitfield_default }, + { "DC_GPIO_HPD34_SLEWN", 25, 25, &umr_bitfield_default }, + { "DC_GPIO_HPD56_SLEWN", 26, 26, &umr_bitfield_default }, + { "DC_GPIO_HPD_RESBIASEN", 27, 27, &umr_bitfield_default }, + { "DC_GPIO_HPD12_COMPSEL", 28, 28, &umr_bitfield_default }, + { "DC_GPIO_HPD34_COMPSEL", 29, 29, &umr_bitfield_default }, + { "DC_GPIO_HPD56_COMPSEL", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_RXEN[] = { + { "DC_GPIO_GENERICA_RXEN", 0, 0, &umr_bitfield_default }, + { "DC_GPIO_GENERICB_RXEN", 1, 1, &umr_bitfield_default }, + { "DC_GPIO_GENERICC_RXEN", 2, 2, &umr_bitfield_default }, + { "DC_GPIO_GENERICD_RXEN", 3, 3, &umr_bitfield_default }, + { "DC_GPIO_GENERICE_RXEN", 4, 4, &umr_bitfield_default }, + { "DC_GPIO_GENERICF_RXEN", 5, 5, &umr_bitfield_default }, + { "DC_GPIO_GENERICG_RXEN", 6, 6, &umr_bitfield_default }, + { "DC_GPIO_HSYNCA_RXEN", 8, 8, &umr_bitfield_default }, + { "DC_GPIO_VSYNCA_RXEN", 9, 9, &umr_bitfield_default }, + { "DC_GPIO_GENLK_CLK_RXEN", 10, 10, &umr_bitfield_default }, + { "DC_GPIO_GENLK_VSYNC_RXEN", 11, 11, &umr_bitfield_default }, + { "DC_GPIO_SWAPLOCK_A_RXEN", 12, 12, &umr_bitfield_default }, + { "DC_GPIO_SWAPLOCK_B_RXEN", 13, 13, &umr_bitfield_default }, + { "DC_GPIO_HPD1_RXEN", 14, 14, &umr_bitfield_default }, + { "DC_GPIO_HPD2_RXEN", 15, 15, &umr_bitfield_default }, + { "DC_GPIO_HPD3_RXEN", 16, 16, &umr_bitfield_default }, + { "DC_GPIO_HPD4_RXEN", 17, 17, &umr_bitfield_default }, + { "DC_GPIO_HPD5_RXEN", 18, 18, &umr_bitfield_default }, + { "DC_GPIO_HPD6_RXEN", 19, 19, &umr_bitfield_default }, + { "DC_GPIO_BLON_RXEN", 20, 20, &umr_bitfield_default }, + { "DC_GPIO_DIGON_RXEN", 21, 21, &umr_bitfield_default }, + { "DC_GPIO_ENA_BL_RXEN", 22, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_GPIO_PULLUPEN[] = { + { "DC_GPIO_GENERICA_PU_EN", 0, 0, &umr_bitfield_default }, + { "DC_GPIO_GENERICB_PU_EN", 1, 1, &umr_bitfield_default }, + { "DC_GPIO_GENERICC_PU_EN", 2, 2, &umr_bitfield_default }, + { "DC_GPIO_GENERICD_PU_EN", 3, 3, &umr_bitfield_default }, + { "DC_GPIO_GENERICE_PU_EN", 4, 4, &umr_bitfield_default }, + { "DC_GPIO_GENERICF_PU_EN", 5, 5, &umr_bitfield_default }, + { "DC_GPIO_GENERICG_PU_EN", 6, 6, &umr_bitfield_default }, + { "DC_GPIO_HSYNCA_PU_EN", 8, 8, &umr_bitfield_default }, + { "DC_GPIO_VSYNCA_PU_EN", 9, 9, &umr_bitfield_default }, + { "DC_GPIO_HPD1_PU_EN", 14, 14, &umr_bitfield_default }, + { "DC_GPIO_BLON_PU_EN", 20, 20, &umr_bitfield_default }, + { "DC_GPIO_DIGON_PU_EN", 21, 21, &umr_bitfield_default }, + { "DC_GPIO_ENA_BL_PU_EN", 22, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAC_MACRO_CNTL_RESERVED0[] = { + { "DAC_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAC_MACRO_CNTL_RESERVED1[] = { + { "DAC_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAC_MACRO_CNTL_RESERVED2[] = { + { "DAC_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAC_MACRO_CNTL_RESERVED3[] = { + { "DAC_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYCMREGS0_COMMON_FUSE1[] = { + { "fuse1_valid", 0, 0, &umr_bitfield_default }, + { "fuse1_unpopulated0", 1, 2, &umr_bitfield_default }, + { "fuse1_ron_override_val", 3, 8, &umr_bitfield_default }, + { "fuse1_unpopulated1", 9, 9, &umr_bitfield_default }, + { "fuse1_ron_ctl", 10, 11, &umr_bitfield_default }, + { "fuse1_unpopulated2", 12, 12, &umr_bitfield_default }, + { "fuse1_rtt_override_val", 13, 18, &umr_bitfield_default }, + { "fuse1_unpopulated3", 19, 19, &umr_bitfield_default }, + { "fuse1_rtt_ctl", 20, 21, &umr_bitfield_default }, + { "fuse1_refresh_cal_en", 22, 22, &umr_bitfield_default }, + { "fuse1_spare", 23, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYCMREGS0_COMMON_FUSE2[] = { + { "fuse2_valid", 0, 0, &umr_bitfield_default }, + { "fuse2_unpopulated", 1, 8, &umr_bitfield_default }, + { "fuse2_tx_fifo_ptr", 9, 13, &umr_bitfield_default }, + { "fuse2_spare", 14, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYCMREGS0_COMMON_FUSE3[] = { + { "fuse3_valid", 0, 0, &umr_bitfield_default }, + { "fuse3_unpopulated", 1, 9, &umr_bitfield_default }, + { "fuse3_ei_det_thresh_sel", 10, 12, &umr_bitfield_default }, + { "cdr_dac_safeval_sel", 13, 15, &umr_bitfield_default }, + { "cdr_freq_lock_timer", 16, 17, &umr_bitfield_default }, + { "cdr_cal_dac_stpsz", 18, 19, &umr_bitfield_default }, + { "cdr_byp_init_val", 20, 20, &umr_bitfield_default }, + { "cdr_icostart_sel", 21, 21, &umr_bitfield_default }, + { "cdr_bbweight", 22, 25, &umr_bitfield_default }, + { "cdr_cur_mirr_ratio", 26, 28, &umr_bitfield_default }, + { "fuse3_spare", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM[] = { + { "tx_margin_nom", 0, 7, &umr_bitfield_default }, + { "deemph_gen1_nom", 8, 15, &umr_bitfield_default }, + { "deemph35_gen2_nom", 16, 23, &umr_bitfield_default }, + { "deemph60_gen2_nom", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT[] = { + { "pgdelay", 0, 3, &umr_bitfield_default }, + { "pgmask", 4, 9, &umr_bitfield_default }, + { "vprot_en", 11, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYCMREGS0_COMMON_TXCNTRL[] = { + { "rdptr_rst_val_gen3", 0, 4, &umr_bitfield_default }, + { "clkgate_dis", 5, 5, &umr_bitfield_default }, + { "slew_rate_ctl_gen1", 6, 8, &umr_bitfield_default }, + { "slew_rate_ctl_gen2", 9, 11, &umr_bitfield_default }, + { "slew_rate_ctl_gen3", 12, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYCMREGS0_COMMON_TMDP[] = { + { "tmdp_spare", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYCMREGS0_COMMON_LANE_RESETS[] = { + { "lane_0_reset_l", 0, 0, &umr_bitfield_default }, + { "lane_1_reset_l", 1, 1, &umr_bitfield_default }, + { "lane_2_reset_l", 2, 2, &umr_bitfield_default }, + { "lane_3_reset_l", 3, 3, &umr_bitfield_default }, + { "lane_4_reset_l", 4, 4, &umr_bitfield_default }, + { "lane_5_reset_l", 5, 5, &umr_bitfield_default }, + { "lane_6_reset_l", 6, 6, &umr_bitfield_default }, + { "lane_7_reset_l", 7, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL[] = { + { "zcalcode_override", 0, 0, &umr_bitfield_default }, + { "tx_binary_code_override_val", 1, 5, &umr_bitfield_default }, + { "rx_therm_code_override_val", 6, 20, &umr_bitfield_default }, + { "tx_driver_fifty_ohms", 21, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU1[] = { + { "rfu_value1", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU2[] = { + { "rfu_value2", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU3[] = { + { "rfu_value3", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU4[] = { + { "rfu_value4", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU5[] = { + { "rfu_value5", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU6[] = { + { "rfu_value6", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU7[] = { + { "rfu_value7", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0[] = { + { "tx_pwr", 0, 2, &umr_bitfield_default }, + { "tx_pg_en", 3, 4, &umr_bitfield_default }, + { "tx_rdy", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0[] = { + { "txmarg_sel", 0, 2, &umr_bitfield_default }, + { "deemph_sel", 3, 4, &umr_bitfield_default }, + { "tx_margin_en", 5, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0[] = { + { "twosym_en", 1, 2, &umr_bitfield_default }, + { "link_speed", 3, 4, &umr_bitfield_default }, + { "gang_mode", 5, 7, &umr_bitfield_default }, + { "max_linkrate", 8, 9, &umr_bitfield_default }, + { "pcs_freq", 10, 11, &umr_bitfield_default }, + { "pcs_clken", 12, 12, &umr_bitfield_default }, + { "pcs_clkdone", 13, 13, &umr_bitfield_default }, + { "pll1_always_on", 14, 14, &umr_bitfield_default }, + { "rdclk_div2_en", 15, 15, &umr_bitfield_default }, + { "tx_boost_adj", 16, 19, &umr_bitfield_default }, + { "tx_boost_en", 20, 20, &umr_bitfield_default }, + { "tx_binary_ron_code_offset", 22, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0[] = { + { "rfu_value0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0[] = { + { "rfu_value1", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0[] = { + { "rfu_value2", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0[] = { + { "rfu_value3", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0[] = { + { "rfu_value4", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0[] = { + { "rfu_value5", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0[] = { + { "rfu_value6", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0[] = { + { "rfu_value7", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0[] = { + { "rfu_value8", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0[] = { + { "rfu_value9", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0[] = { + { "rfu_value10", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0[] = { + { "rfu_value11", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0[] = { + { "rfu_value12", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1[] = { + { "tx_pwr", 0, 2, &umr_bitfield_default }, + { "tx_pg_en", 3, 4, &umr_bitfield_default }, + { "tx_rdy", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1[] = { + { "txmarg_sel", 0, 2, &umr_bitfield_default }, + { "deemph_sel", 3, 4, &umr_bitfield_default }, + { "tx_margin_en", 5, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1[] = { + { "twosym_en", 1, 2, &umr_bitfield_default }, + { "link_speed", 3, 4, &umr_bitfield_default }, + { "gang_mode", 5, 7, &umr_bitfield_default }, + { "max_linkrate", 8, 9, &umr_bitfield_default }, + { "pcs_freq", 10, 11, &umr_bitfield_default }, + { "pcs_clken", 12, 12, &umr_bitfield_default }, + { "pcs_clkdone", 13, 13, &umr_bitfield_default }, + { "pll1_always_on", 14, 14, &umr_bitfield_default }, + { "rdclk_div2_en", 15, 15, &umr_bitfield_default }, + { "tx_boost_adj", 16, 19, &umr_bitfield_default }, + { "tx_boost_en", 20, 20, &umr_bitfield_default }, + { "tx_binary_ron_code_offset", 22, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1[] = { + { "rfu_value0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1[] = { + { "rfu_value1", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1[] = { + { "rfu_value2", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1[] = { + { "rfu_value3", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1[] = { + { "rfu_value4", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1[] = { + { "rfu_value5", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1[] = { + { "rfu_value6", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1[] = { + { "rfu_value7", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1[] = { + { "rfu_value8", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1[] = { + { "rfu_value9", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1[] = { + { "rfu_value10", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1[] = { + { "rfu_value11", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1[] = { + { "rfu_value12", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2[] = { + { "tx_pwr", 0, 2, &umr_bitfield_default }, + { "tx_pg_en", 3, 4, &umr_bitfield_default }, + { "tx_rdy", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2[] = { + { "txmarg_sel", 0, 2, &umr_bitfield_default }, + { "deemph_sel", 3, 4, &umr_bitfield_default }, + { "tx_margin_en", 5, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2[] = { + { "twosym_en", 1, 2, &umr_bitfield_default }, + { "link_speed", 3, 4, &umr_bitfield_default }, + { "gang_mode", 5, 7, &umr_bitfield_default }, + { "max_linkrate", 8, 9, &umr_bitfield_default }, + { "pcs_freq", 10, 11, &umr_bitfield_default }, + { "pcs_clken", 12, 12, &umr_bitfield_default }, + { "pcs_clkdone", 13, 13, &umr_bitfield_default }, + { "pll1_always_on", 14, 14, &umr_bitfield_default }, + { "rdclk_div2_en", 15, 15, &umr_bitfield_default }, + { "tx_boost_adj", 16, 19, &umr_bitfield_default }, + { "tx_boost_en", 20, 20, &umr_bitfield_default }, + { "tx_binary_ron_code_offset", 22, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2[] = { + { "rfu_value0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2[] = { + { "rfu_value1", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2[] = { + { "rfu_value2", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2[] = { + { "rfu_value3", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2[] = { + { "rfu_value4", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2[] = { + { "rfu_value5", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2[] = { + { "rfu_value6", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2[] = { + { "rfu_value7", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2[] = { + { "rfu_value8", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2[] = { + { "rfu_value9", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2[] = { + { "rfu_value10", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2[] = { + { "rfu_value11", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2[] = { + { "rfu_value12", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3[] = { + { "tx_pwr", 0, 2, &umr_bitfield_default }, + { "tx_pg_en", 3, 4, &umr_bitfield_default }, + { "tx_rdy", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3[] = { + { "txmarg_sel", 0, 2, &umr_bitfield_default }, + { "deemph_sel", 3, 4, &umr_bitfield_default }, + { "tx_margin_en", 5, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3[] = { + { "twosym_en", 1, 2, &umr_bitfield_default }, + { "link_speed", 3, 4, &umr_bitfield_default }, + { "gang_mode", 5, 7, &umr_bitfield_default }, + { "max_linkrate", 8, 9, &umr_bitfield_default }, + { "pcs_freq", 10, 11, &umr_bitfield_default }, + { "pcs_clken", 12, 12, &umr_bitfield_default }, + { "pcs_clkdone", 13, 13, &umr_bitfield_default }, + { "pll1_always_on", 14, 14, &umr_bitfield_default }, + { "rdclk_div2_en", 15, 15, &umr_bitfield_default }, + { "tx_boost_adj", 16, 19, &umr_bitfield_default }, + { "tx_boost_en", 20, 20, &umr_bitfield_default }, + { "tx_binary_ron_code_offset", 22, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3[] = { + { "rfu_value0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3[] = { + { "rfu_value1", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3[] = { + { "rfu_value2", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3[] = { + { "rfu_value3", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3[] = { + { "rfu_value4", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3[] = { + { "rfu_value5", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3[] = { + { "rfu_value6", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3[] = { + { "rfu_value7", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3[] = { + { "rfu_value8", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3[] = { + { "rfu_value9", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3[] = { + { "rfu_value10", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3[] = { + { "rfu_value11", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3[] = { + { "rfu_value12", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYPLLREGS0_FREQ_CTRL0[] = { + { "fcw0_frac", 0, 15, &umr_bitfield_default }, + { "fcw0_int", 16, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYPLLREGS0_FREQ_CTRL1[] = { + { "fcw1_frac", 0, 15, &umr_bitfield_default }, + { "fcw1_int", 16, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYPLLREGS0_FREQ_CTRL2[] = { + { "fcw_denom", 0, 15, &umr_bitfield_default }, + { "fcw_slew_frac", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYPLLREGS0_FREQ_CTRL3[] = { + { "refclk_div", 0, 1, &umr_bitfield_default }, + { "vco_pre_div", 3, 4, &umr_bitfield_default }, + { "fracn_en", 6, 6, &umr_bitfield_default }, + { "ssc_en", 8, 8, &umr_bitfield_default }, + { "fcw_sel", 10, 10, &umr_bitfield_default }, + { "freq_jump_en", 12, 12, &umr_bitfield_default }, + { "tdc_resolution", 16, 23, &umr_bitfield_default }, + { "dpll_cfg_1", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYPLLREGS0_BW_CTRL_COARSE[] = { + { "gi_coarse_mant", 0, 1, &umr_bitfield_default }, + { "gi_coarse_exp", 2, 5, &umr_bitfield_default }, + { "gp_coarse_mant", 7, 10, &umr_bitfield_default }, + { "gp_coarse_exp", 12, 15, &umr_bitfield_default }, + { "nctl_coarse_res", 17, 22, &umr_bitfield_default }, + { "nctl_coarse_frac_res", 24, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYPLLREGS0_BW_CTRL_FINE[] = { + { "dpll_cfg_3", 0, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYPLLREGS0_CAL_CTRL[] = { + { "bypass_freq_lock", 0, 0, &umr_bitfield_default }, + { "tdc_cal_en", 1, 1, &umr_bitfield_default }, + { "tdc_cal_ctrl", 3, 8, &umr_bitfield_default }, + { "meas_win_sel", 9, 10, &umr_bitfield_default }, + { "kdco_cal_dis", 11, 11, &umr_bitfield_default }, + { "kdco_ratio", 13, 20, &umr_bitfield_default }, + { "kdco_incr_cal_dis", 22, 22, &umr_bitfield_default }, + { "nctl_adj_dis", 23, 23, &umr_bitfield_default }, + { "refclk_rate", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYPLLREGS0_LOOP_CTRL[] = { + { "fbdiv_mask_en", 0, 0, &umr_bitfield_default }, + { "fb_slip_dis", 2, 2, &umr_bitfield_default }, + { "clk_tdc_sel", 4, 5, &umr_bitfield_default }, + { "clk_nctl_sel", 7, 8, &umr_bitfield_default }, + { "sig_del_patt_sel", 10, 10, &umr_bitfield_default }, + { "nctl_sig_del_dis", 12, 12, &umr_bitfield_default }, + { "fbclk_track_refclk", 14, 14, &umr_bitfield_default }, + { "prbs_en", 16, 16, &umr_bitfield_default }, + { "tdc_clk_gate_en", 18, 18, &umr_bitfield_default }, + { "phase_offset", 20, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYPLLREGS0_VREG_CFG[] = { + { "bleeder_ac", 0, 0, &umr_bitfield_default }, + { "bleeder_en", 1, 1, &umr_bitfield_default }, + { "is_1p2", 2, 2, &umr_bitfield_default }, + { "reg_obs_sel", 3, 4, &umr_bitfield_default }, + { "reg_on_mode", 5, 6, &umr_bitfield_default }, + { "rlad_tap_sel", 7, 10, &umr_bitfield_default }, + { "reg_off_hi", 11, 11, &umr_bitfield_default }, + { "reg_off_lo", 12, 12, &umr_bitfield_default }, + { "scale_driver", 13, 14, &umr_bitfield_default }, + { "sel_bump", 15, 15, &umr_bitfield_default }, + { "sel_rladder_x", 16, 16, &umr_bitfield_default }, + { "short_rc_filt_x", 17, 17, &umr_bitfield_default }, + { "vref_pwr_on", 18, 18, &umr_bitfield_default }, + { "dpll_cfg_2", 20, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYPLLREGS0_OBSERVE0[] = { + { "lock_det_tdc_steps", 0, 4, &umr_bitfield_default }, + { "clear_sticky_lock", 6, 6, &umr_bitfield_default }, + { "lock_det_dis", 8, 8, &umr_bitfield_default }, + { "dco_cfg", 10, 17, &umr_bitfield_default }, + { "anaobs_sel", 21, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYPLLREGS0_OBSERVE1[] = { + { "digobs_sel", 0, 3, &umr_bitfield_default }, + { "digobs_trig_sel", 5, 8, &umr_bitfield_default }, + { "digobs_div", 10, 11, &umr_bitfield_default }, + { "digobs_trig_div", 13, 14, &umr_bitfield_default }, + { "lock_timer", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYPLLREGS0_DFT_OUT[] = { + { "dft_data", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL1[] = { + { "wrap_cfg_sel_clk", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL[] = { + { "wrap_cfg_pll_freq_programming_ovveride", 0, 0, &umr_bitfield_default }, + { "wrap_cfg_pll_pwr_state_ovrride", 1, 1, &umr_bitfield_default }, + { "wrap_cfg_pll_pwr_state", 2, 3, &umr_bitfield_default }, + { "wrap_cfg_tx_pdiv_val", 5, 7, &umr_bitfield_default }, + { "wrap_cfg_tx_pixdiv_val", 8, 8, &umr_bitfield_default }, + { "wrap_cfg_cml_cmos_sel", 10, 10, &umr_bitfield_default }, + { "wrap_cfg_pll_rdy", 13, 13, &umr_bitfield_default }, + { "wrap_cfg_pll_update", 14, 14, &umr_bitfield_default }, + { "wrap_cfg_ref_values_chg", 15, 15, &umr_bitfield_default }, + { "wrap_cfg_clk_gate_w_rdy", 16, 16, &umr_bitfield_default }, + { "wrap_cfg_pll_dsm_sel", 17, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYCMREGS1_COMMON_FUSE1[] = { + { "fuse1_valid", 0, 0, &umr_bitfield_default }, + { "fuse1_unpopulated0", 1, 2, &umr_bitfield_default }, + { "fuse1_ron_override_val", 3, 8, &umr_bitfield_default }, + { "fuse1_unpopulated1", 9, 9, &umr_bitfield_default }, + { "fuse1_ron_ctl", 10, 11, &umr_bitfield_default }, + { "fuse1_unpopulated2", 12, 12, &umr_bitfield_default }, + { "fuse1_rtt_override_val", 13, 18, &umr_bitfield_default }, + { "fuse1_unpopulated3", 19, 19, &umr_bitfield_default }, + { "fuse1_rtt_ctl", 20, 21, &umr_bitfield_default }, + { "fuse1_refresh_cal_en", 22, 22, &umr_bitfield_default }, + { "fuse1_spare", 23, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYCMREGS1_COMMON_FUSE2[] = { + { "fuse2_valid", 0, 0, &umr_bitfield_default }, + { "fuse2_unpopulated", 1, 8, &umr_bitfield_default }, + { "fuse2_tx_fifo_ptr", 9, 13, &umr_bitfield_default }, + { "fuse2_spare", 14, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYCMREGS1_COMMON_FUSE3[] = { + { "fuse3_valid", 0, 0, &umr_bitfield_default }, + { "fuse3_unpopulated", 1, 9, &umr_bitfield_default }, + { "fuse3_ei_det_thresh_sel", 10, 12, &umr_bitfield_default }, + { "cdr_dac_safeval_sel", 13, 15, &umr_bitfield_default }, + { "cdr_freq_lock_timer", 16, 17, &umr_bitfield_default }, + { "cdr_cal_dac_stpsz", 18, 19, &umr_bitfield_default }, + { "cdr_byp_init_val", 20, 20, &umr_bitfield_default }, + { "cdr_icostart_sel", 21, 21, &umr_bitfield_default }, + { "cdr_bbweight", 22, 25, &umr_bitfield_default }, + { "cdr_cur_mirr_ratio", 26, 28, &umr_bitfield_default }, + { "fuse3_spare", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM[] = { + { "tx_margin_nom", 0, 7, &umr_bitfield_default }, + { "deemph_gen1_nom", 8, 15, &umr_bitfield_default }, + { "deemph35_gen2_nom", 16, 23, &umr_bitfield_default }, + { "deemph60_gen2_nom", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT[] = { + { "pgdelay", 0, 3, &umr_bitfield_default }, + { "pgmask", 4, 9, &umr_bitfield_default }, + { "vprot_en", 11, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYCMREGS1_COMMON_TXCNTRL[] = { + { "rdptr_rst_val_gen3", 0, 4, &umr_bitfield_default }, + { "clkgate_dis", 5, 5, &umr_bitfield_default }, + { "slew_rate_ctl_gen1", 6, 8, &umr_bitfield_default }, + { "slew_rate_ctl_gen2", 9, 11, &umr_bitfield_default }, + { "slew_rate_ctl_gen3", 12, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYCMREGS1_COMMON_TMDP[] = { + { "tmdp_spare", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYCMREGS1_COMMON_LANE_RESETS[] = { + { "lane_0_reset_l", 0, 0, &umr_bitfield_default }, + { "lane_1_reset_l", 1, 1, &umr_bitfield_default }, + { "lane_2_reset_l", 2, 2, &umr_bitfield_default }, + { "lane_3_reset_l", 3, 3, &umr_bitfield_default }, + { "lane_4_reset_l", 4, 4, &umr_bitfield_default }, + { "lane_5_reset_l", 5, 5, &umr_bitfield_default }, + { "lane_6_reset_l", 6, 6, &umr_bitfield_default }, + { "lane_7_reset_l", 7, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL[] = { + { "zcalcode_override", 0, 0, &umr_bitfield_default }, + { "tx_binary_code_override_val", 1, 5, &umr_bitfield_default }, + { "rx_therm_code_override_val", 6, 20, &umr_bitfield_default }, + { "tx_driver_fifty_ohms", 21, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU1[] = { + { "rfu_value1", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU2[] = { + { "rfu_value2", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU3[] = { + { "rfu_value3", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU4[] = { + { "rfu_value4", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU5[] = { + { "rfu_value5", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU6[] = { + { "rfu_value6", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU7[] = { + { "rfu_value7", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0[] = { + { "tx_pwr", 0, 2, &umr_bitfield_default }, + { "tx_pg_en", 3, 4, &umr_bitfield_default }, + { "tx_rdy", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0[] = { + { "txmarg_sel", 0, 2, &umr_bitfield_default }, + { "deemph_sel", 3, 4, &umr_bitfield_default }, + { "tx_margin_en", 5, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0[] = { + { "twosym_en", 1, 2, &umr_bitfield_default }, + { "link_speed", 3, 4, &umr_bitfield_default }, + { "gang_mode", 5, 7, &umr_bitfield_default }, + { "max_linkrate", 8, 9, &umr_bitfield_default }, + { "pcs_freq", 10, 11, &umr_bitfield_default }, + { "pcs_clken", 12, 12, &umr_bitfield_default }, + { "pcs_clkdone", 13, 13, &umr_bitfield_default }, + { "pll1_always_on", 14, 14, &umr_bitfield_default }, + { "rdclk_div2_en", 15, 15, &umr_bitfield_default }, + { "tx_boost_adj", 16, 19, &umr_bitfield_default }, + { "tx_boost_en", 20, 20, &umr_bitfield_default }, + { "tx_binary_ron_code_offset", 22, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0[] = { + { "rfu_value0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0[] = { + { "rfu_value1", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0[] = { + { "rfu_value2", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0[] = { + { "rfu_value3", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0[] = { + { "rfu_value4", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0[] = { + { "rfu_value5", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0[] = { + { "rfu_value6", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0[] = { + { "rfu_value7", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0[] = { + { "rfu_value8", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0[] = { + { "rfu_value9", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0[] = { + { "rfu_value10", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0[] = { + { "rfu_value11", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0[] = { + { "rfu_value12", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1[] = { + { "tx_pwr", 0, 2, &umr_bitfield_default }, + { "tx_pg_en", 3, 4, &umr_bitfield_default }, + { "tx_rdy", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1[] = { + { "txmarg_sel", 0, 2, &umr_bitfield_default }, + { "deemph_sel", 3, 4, &umr_bitfield_default }, + { "tx_margin_en", 5, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1[] = { + { "twosym_en", 1, 2, &umr_bitfield_default }, + { "link_speed", 3, 4, &umr_bitfield_default }, + { "gang_mode", 5, 7, &umr_bitfield_default }, + { "max_linkrate", 8, 9, &umr_bitfield_default }, + { "pcs_freq", 10, 11, &umr_bitfield_default }, + { "pcs_clken", 12, 12, &umr_bitfield_default }, + { "pcs_clkdone", 13, 13, &umr_bitfield_default }, + { "pll1_always_on", 14, 14, &umr_bitfield_default }, + { "rdclk_div2_en", 15, 15, &umr_bitfield_default }, + { "tx_boost_adj", 16, 19, &umr_bitfield_default }, + { "tx_boost_en", 20, 20, &umr_bitfield_default }, + { "tx_binary_ron_code_offset", 22, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1[] = { + { "rfu_value0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1[] = { + { "rfu_value1", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1[] = { + { "rfu_value2", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1[] = { + { "rfu_value3", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1[] = { + { "rfu_value4", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1[] = { + { "rfu_value5", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1[] = { + { "rfu_value6", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1[] = { + { "rfu_value7", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1[] = { + { "rfu_value8", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1[] = { + { "rfu_value9", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1[] = { + { "rfu_value10", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1[] = { + { "rfu_value11", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1[] = { + { "rfu_value12", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2[] = { + { "tx_pwr", 0, 2, &umr_bitfield_default }, + { "tx_pg_en", 3, 4, &umr_bitfield_default }, + { "tx_rdy", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2[] = { + { "txmarg_sel", 0, 2, &umr_bitfield_default }, + { "deemph_sel", 3, 4, &umr_bitfield_default }, + { "tx_margin_en", 5, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2[] = { + { "twosym_en", 1, 2, &umr_bitfield_default }, + { "link_speed", 3, 4, &umr_bitfield_default }, + { "gang_mode", 5, 7, &umr_bitfield_default }, + { "max_linkrate", 8, 9, &umr_bitfield_default }, + { "pcs_freq", 10, 11, &umr_bitfield_default }, + { "pcs_clken", 12, 12, &umr_bitfield_default }, + { "pcs_clkdone", 13, 13, &umr_bitfield_default }, + { "pll1_always_on", 14, 14, &umr_bitfield_default }, + { "rdclk_div2_en", 15, 15, &umr_bitfield_default }, + { "tx_boost_adj", 16, 19, &umr_bitfield_default }, + { "tx_boost_en", 20, 20, &umr_bitfield_default }, + { "tx_binary_ron_code_offset", 22, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2[] = { + { "rfu_value0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2[] = { + { "rfu_value1", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2[] = { + { "rfu_value2", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2[] = { + { "rfu_value3", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2[] = { + { "rfu_value4", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2[] = { + { "rfu_value5", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2[] = { + { "rfu_value6", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2[] = { + { "rfu_value7", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2[] = { + { "rfu_value8", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2[] = { + { "rfu_value9", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2[] = { + { "rfu_value10", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2[] = { + { "rfu_value11", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2[] = { + { "rfu_value12", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3[] = { + { "tx_pwr", 0, 2, &umr_bitfield_default }, + { "tx_pg_en", 3, 4, &umr_bitfield_default }, + { "tx_rdy", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3[] = { + { "txmarg_sel", 0, 2, &umr_bitfield_default }, + { "deemph_sel", 3, 4, &umr_bitfield_default }, + { "tx_margin_en", 5, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3[] = { + { "twosym_en", 1, 2, &umr_bitfield_default }, + { "link_speed", 3, 4, &umr_bitfield_default }, + { "gang_mode", 5, 7, &umr_bitfield_default }, + { "max_linkrate", 8, 9, &umr_bitfield_default }, + { "pcs_freq", 10, 11, &umr_bitfield_default }, + { "pcs_clken", 12, 12, &umr_bitfield_default }, + { "pcs_clkdone", 13, 13, &umr_bitfield_default }, + { "pll1_always_on", 14, 14, &umr_bitfield_default }, + { "rdclk_div2_en", 15, 15, &umr_bitfield_default }, + { "tx_boost_adj", 16, 19, &umr_bitfield_default }, + { "tx_boost_en", 20, 20, &umr_bitfield_default }, + { "tx_binary_ron_code_offset", 22, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3[] = { + { "rfu_value0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3[] = { + { "rfu_value1", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3[] = { + { "rfu_value2", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3[] = { + { "rfu_value3", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3[] = { + { "rfu_value4", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3[] = { + { "rfu_value5", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3[] = { + { "rfu_value6", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3[] = { + { "rfu_value7", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3[] = { + { "rfu_value8", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3[] = { + { "rfu_value9", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3[] = { + { "rfu_value10", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3[] = { + { "rfu_value11", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3[] = { + { "rfu_value12", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYPLLREGS1_FREQ_CTRL0[] = { + { "fcw0_frac", 0, 15, &umr_bitfield_default }, + { "fcw0_int", 16, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYPLLREGS1_FREQ_CTRL1[] = { + { "fcw1_frac", 0, 15, &umr_bitfield_default }, + { "fcw1_int", 16, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYPLLREGS1_FREQ_CTRL2[] = { + { "fcw_denom", 0, 15, &umr_bitfield_default }, + { "fcw_slew_frac", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYPLLREGS1_FREQ_CTRL3[] = { + { "refclk_div", 0, 1, &umr_bitfield_default }, + { "vco_pre_div", 3, 4, &umr_bitfield_default }, + { "fracn_en", 6, 6, &umr_bitfield_default }, + { "ssc_en", 8, 8, &umr_bitfield_default }, + { "fcw_sel", 10, 10, &umr_bitfield_default }, + { "freq_jump_en", 12, 12, &umr_bitfield_default }, + { "tdc_resolution", 16, 23, &umr_bitfield_default }, + { "dpll_cfg_1", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYPLLREGS1_BW_CTRL_COARSE[] = { + { "gi_coarse_mant", 0, 1, &umr_bitfield_default }, + { "gi_coarse_exp", 2, 5, &umr_bitfield_default }, + { "gp_coarse_mant", 7, 10, &umr_bitfield_default }, + { "gp_coarse_exp", 12, 15, &umr_bitfield_default }, + { "nctl_coarse_res", 17, 22, &umr_bitfield_default }, + { "nctl_coarse_frac_res", 24, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYPLLREGS1_BW_CTRL_FINE[] = { + { "dpll_cfg_3", 0, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYPLLREGS1_CAL_CTRL[] = { + { "bypass_freq_lock", 0, 0, &umr_bitfield_default }, + { "tdc_cal_en", 1, 1, &umr_bitfield_default }, + { "tdc_cal_ctrl", 3, 8, &umr_bitfield_default }, + { "meas_win_sel", 9, 10, &umr_bitfield_default }, + { "kdco_cal_dis", 11, 11, &umr_bitfield_default }, + { "kdco_ratio", 13, 20, &umr_bitfield_default }, + { "kdco_incr_cal_dis", 22, 22, &umr_bitfield_default }, + { "nctl_adj_dis", 23, 23, &umr_bitfield_default }, + { "refclk_rate", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYPLLREGS1_LOOP_CTRL[] = { + { "fbdiv_mask_en", 0, 0, &umr_bitfield_default }, + { "fb_slip_dis", 2, 2, &umr_bitfield_default }, + { "clk_tdc_sel", 4, 5, &umr_bitfield_default }, + { "clk_nctl_sel", 7, 8, &umr_bitfield_default }, + { "sig_del_patt_sel", 10, 10, &umr_bitfield_default }, + { "nctl_sig_del_dis", 12, 12, &umr_bitfield_default }, + { "fbclk_track_refclk", 14, 14, &umr_bitfield_default }, + { "prbs_en", 16, 16, &umr_bitfield_default }, + { "tdc_clk_gate_en", 18, 18, &umr_bitfield_default }, + { "phase_offset", 20, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYPLLREGS1_VREG_CFG[] = { + { "bleeder_ac", 0, 0, &umr_bitfield_default }, + { "bleeder_en", 1, 1, &umr_bitfield_default }, + { "is_1p2", 2, 2, &umr_bitfield_default }, + { "reg_obs_sel", 3, 4, &umr_bitfield_default }, + { "reg_on_mode", 5, 6, &umr_bitfield_default }, + { "rlad_tap_sel", 7, 10, &umr_bitfield_default }, + { "reg_off_hi", 11, 11, &umr_bitfield_default }, + { "reg_off_lo", 12, 12, &umr_bitfield_default }, + { "scale_driver", 13, 14, &umr_bitfield_default }, + { "sel_bump", 15, 15, &umr_bitfield_default }, + { "sel_rladder_x", 16, 16, &umr_bitfield_default }, + { "short_rc_filt_x", 17, 17, &umr_bitfield_default }, + { "vref_pwr_on", 18, 18, &umr_bitfield_default }, + { "dpll_cfg_2", 20, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYPLLREGS1_OBSERVE0[] = { + { "lock_det_tdc_steps", 0, 4, &umr_bitfield_default }, + { "clear_sticky_lock", 6, 6, &umr_bitfield_default }, + { "lock_det_dis", 8, 8, &umr_bitfield_default }, + { "dco_cfg", 10, 17, &umr_bitfield_default }, + { "anaobs_sel", 21, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYPLLREGS1_OBSERVE1[] = { + { "digobs_sel", 0, 3, &umr_bitfield_default }, + { "digobs_trig_sel", 5, 8, &umr_bitfield_default }, + { "digobs_div", 10, 11, &umr_bitfield_default }, + { "digobs_trig_div", 13, 14, &umr_bitfield_default }, + { "lock_timer", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYPLLREGS1_DFT_OUT[] = { + { "dft_data", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL1[] = { + { "wrap_cfg_sel_clk", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL[] = { + { "wrap_cfg_pll_freq_programming_ovveride", 0, 0, &umr_bitfield_default }, + { "wrap_cfg_pll_pwr_state_ovrride", 1, 1, &umr_bitfield_default }, + { "wrap_cfg_pll_pwr_state", 2, 3, &umr_bitfield_default }, + { "wrap_cfg_tx_pdiv_val", 5, 7, &umr_bitfield_default }, + { "wrap_cfg_tx_pixdiv_val", 8, 8, &umr_bitfield_default }, + { "wrap_cfg_cml_cmos_sel", 10, 10, &umr_bitfield_default }, + { "wrap_cfg_pll_rdy", 13, 13, &umr_bitfield_default }, + { "wrap_cfg_pll_update", 14, 14, &umr_bitfield_default }, + { "wrap_cfg_ref_values_chg", 15, 15, &umr_bitfield_default }, + { "wrap_cfg_clk_gate_w_rdy", 16, 16, &umr_bitfield_default }, + { "wrap_cfg_pll_dsm_sel", 17, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYCMREGS2_COMMON_FUSE1[] = { + { "fuse1_valid", 0, 0, &umr_bitfield_default }, + { "fuse1_unpopulated0", 1, 2, &umr_bitfield_default }, + { "fuse1_ron_override_val", 3, 8, &umr_bitfield_default }, + { "fuse1_unpopulated1", 9, 9, &umr_bitfield_default }, + { "fuse1_ron_ctl", 10, 11, &umr_bitfield_default }, + { "fuse1_unpopulated2", 12, 12, &umr_bitfield_default }, + { "fuse1_rtt_override_val", 13, 18, &umr_bitfield_default }, + { "fuse1_unpopulated3", 19, 19, &umr_bitfield_default }, + { "fuse1_rtt_ctl", 20, 21, &umr_bitfield_default }, + { "fuse1_refresh_cal_en", 22, 22, &umr_bitfield_default }, + { "fuse1_spare", 23, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYCMREGS2_COMMON_FUSE2[] = { + { "fuse2_valid", 0, 0, &umr_bitfield_default }, + { "fuse2_unpopulated", 1, 8, &umr_bitfield_default }, + { "fuse2_tx_fifo_ptr", 9, 13, &umr_bitfield_default }, + { "fuse2_spare", 14, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYCMREGS2_COMMON_FUSE3[] = { + { "fuse3_valid", 0, 0, &umr_bitfield_default }, + { "fuse3_unpopulated", 1, 9, &umr_bitfield_default }, + { "fuse3_ei_det_thresh_sel", 10, 12, &umr_bitfield_default }, + { "cdr_dac_safeval_sel", 13, 15, &umr_bitfield_default }, + { "cdr_freq_lock_timer", 16, 17, &umr_bitfield_default }, + { "cdr_cal_dac_stpsz", 18, 19, &umr_bitfield_default }, + { "cdr_byp_init_val", 20, 20, &umr_bitfield_default }, + { "cdr_icostart_sel", 21, 21, &umr_bitfield_default }, + { "cdr_bbweight", 22, 25, &umr_bitfield_default }, + { "cdr_cur_mirr_ratio", 26, 28, &umr_bitfield_default }, + { "fuse3_spare", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM[] = { + { "tx_margin_nom", 0, 7, &umr_bitfield_default }, + { "deemph_gen1_nom", 8, 15, &umr_bitfield_default }, + { "deemph35_gen2_nom", 16, 23, &umr_bitfield_default }, + { "deemph60_gen2_nom", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT[] = { + { "pgdelay", 0, 3, &umr_bitfield_default }, + { "pgmask", 4, 9, &umr_bitfield_default }, + { "vprot_en", 11, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYCMREGS2_COMMON_TXCNTRL[] = { + { "rdptr_rst_val_gen3", 0, 4, &umr_bitfield_default }, + { "clkgate_dis", 5, 5, &umr_bitfield_default }, + { "slew_rate_ctl_gen1", 6, 8, &umr_bitfield_default }, + { "slew_rate_ctl_gen2", 9, 11, &umr_bitfield_default }, + { "slew_rate_ctl_gen3", 12, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYCMREGS2_COMMON_TMDP[] = { + { "tmdp_spare", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYCMREGS2_COMMON_LANE_RESETS[] = { + { "lane_0_reset_l", 0, 0, &umr_bitfield_default }, + { "lane_1_reset_l", 1, 1, &umr_bitfield_default }, + { "lane_2_reset_l", 2, 2, &umr_bitfield_default }, + { "lane_3_reset_l", 3, 3, &umr_bitfield_default }, + { "lane_4_reset_l", 4, 4, &umr_bitfield_default }, + { "lane_5_reset_l", 5, 5, &umr_bitfield_default }, + { "lane_6_reset_l", 6, 6, &umr_bitfield_default }, + { "lane_7_reset_l", 7, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL[] = { + { "zcalcode_override", 0, 0, &umr_bitfield_default }, + { "tx_binary_code_override_val", 1, 5, &umr_bitfield_default }, + { "rx_therm_code_override_val", 6, 20, &umr_bitfield_default }, + { "tx_driver_fifty_ohms", 21, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU1[] = { + { "rfu_value1", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU2[] = { + { "rfu_value2", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU3[] = { + { "rfu_value3", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU4[] = { + { "rfu_value4", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU5[] = { + { "rfu_value5", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU6[] = { + { "rfu_value6", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU7[] = { + { "rfu_value7", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0[] = { + { "tx_pwr", 0, 2, &umr_bitfield_default }, + { "tx_pg_en", 3, 4, &umr_bitfield_default }, + { "tx_rdy", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0[] = { + { "txmarg_sel", 0, 2, &umr_bitfield_default }, + { "deemph_sel", 3, 4, &umr_bitfield_default }, + { "tx_margin_en", 5, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0[] = { + { "twosym_en", 1, 2, &umr_bitfield_default }, + { "link_speed", 3, 4, &umr_bitfield_default }, + { "gang_mode", 5, 7, &umr_bitfield_default }, + { "max_linkrate", 8, 9, &umr_bitfield_default }, + { "pcs_freq", 10, 11, &umr_bitfield_default }, + { "pcs_clken", 12, 12, &umr_bitfield_default }, + { "pcs_clkdone", 13, 13, &umr_bitfield_default }, + { "pll1_always_on", 14, 14, &umr_bitfield_default }, + { "rdclk_div2_en", 15, 15, &umr_bitfield_default }, + { "tx_boost_adj", 16, 19, &umr_bitfield_default }, + { "tx_boost_en", 20, 20, &umr_bitfield_default }, + { "tx_binary_ron_code_offset", 22, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0[] = { + { "rfu_value0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0[] = { + { "rfu_value1", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0[] = { + { "rfu_value2", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0[] = { + { "rfu_value3", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0[] = { + { "rfu_value4", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0[] = { + { "rfu_value5", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0[] = { + { "rfu_value6", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0[] = { + { "rfu_value7", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0[] = { + { "rfu_value8", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0[] = { + { "rfu_value9", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0[] = { + { "rfu_value10", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0[] = { + { "rfu_value11", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0[] = { + { "rfu_value12", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1[] = { + { "tx_pwr", 0, 2, &umr_bitfield_default }, + { "tx_pg_en", 3, 4, &umr_bitfield_default }, + { "tx_rdy", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1[] = { + { "txmarg_sel", 0, 2, &umr_bitfield_default }, + { "deemph_sel", 3, 4, &umr_bitfield_default }, + { "tx_margin_en", 5, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1[] = { + { "twosym_en", 1, 2, &umr_bitfield_default }, + { "link_speed", 3, 4, &umr_bitfield_default }, + { "gang_mode", 5, 7, &umr_bitfield_default }, + { "max_linkrate", 8, 9, &umr_bitfield_default }, + { "pcs_freq", 10, 11, &umr_bitfield_default }, + { "pcs_clken", 12, 12, &umr_bitfield_default }, + { "pcs_clkdone", 13, 13, &umr_bitfield_default }, + { "pll1_always_on", 14, 14, &umr_bitfield_default }, + { "rdclk_div2_en", 15, 15, &umr_bitfield_default }, + { "tx_boost_adj", 16, 19, &umr_bitfield_default }, + { "tx_boost_en", 20, 20, &umr_bitfield_default }, + { "tx_binary_ron_code_offset", 22, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1[] = { + { "rfu_value0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1[] = { + { "rfu_value1", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1[] = { + { "rfu_value2", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1[] = { + { "rfu_value3", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1[] = { + { "rfu_value4", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1[] = { + { "rfu_value5", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1[] = { + { "rfu_value6", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1[] = { + { "rfu_value7", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1[] = { + { "rfu_value8", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1[] = { + { "rfu_value9", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1[] = { + { "rfu_value10", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1[] = { + { "rfu_value11", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1[] = { + { "rfu_value12", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2[] = { + { "tx_pwr", 0, 2, &umr_bitfield_default }, + { "tx_pg_en", 3, 4, &umr_bitfield_default }, + { "tx_rdy", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2[] = { + { "txmarg_sel", 0, 2, &umr_bitfield_default }, + { "deemph_sel", 3, 4, &umr_bitfield_default }, + { "tx_margin_en", 5, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2[] = { + { "twosym_en", 1, 2, &umr_bitfield_default }, + { "link_speed", 3, 4, &umr_bitfield_default }, + { "gang_mode", 5, 7, &umr_bitfield_default }, + { "max_linkrate", 8, 9, &umr_bitfield_default }, + { "pcs_freq", 10, 11, &umr_bitfield_default }, + { "pcs_clken", 12, 12, &umr_bitfield_default }, + { "pcs_clkdone", 13, 13, &umr_bitfield_default }, + { "pll1_always_on", 14, 14, &umr_bitfield_default }, + { "rdclk_div2_en", 15, 15, &umr_bitfield_default }, + { "tx_boost_adj", 16, 19, &umr_bitfield_default }, + { "tx_boost_en", 20, 20, &umr_bitfield_default }, + { "tx_binary_ron_code_offset", 22, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2[] = { + { "rfu_value0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2[] = { + { "rfu_value1", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2[] = { + { "rfu_value2", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2[] = { + { "rfu_value3", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2[] = { + { "rfu_value4", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2[] = { + { "rfu_value5", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2[] = { + { "rfu_value6", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2[] = { + { "rfu_value7", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2[] = { + { "rfu_value8", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2[] = { + { "rfu_value9", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2[] = { + { "rfu_value10", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2[] = { + { "rfu_value11", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2[] = { + { "rfu_value12", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3[] = { + { "tx_pwr", 0, 2, &umr_bitfield_default }, + { "tx_pg_en", 3, 4, &umr_bitfield_default }, + { "tx_rdy", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3[] = { + { "txmarg_sel", 0, 2, &umr_bitfield_default }, + { "deemph_sel", 3, 4, &umr_bitfield_default }, + { "tx_margin_en", 5, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3[] = { + { "twosym_en", 1, 2, &umr_bitfield_default }, + { "link_speed", 3, 4, &umr_bitfield_default }, + { "gang_mode", 5, 7, &umr_bitfield_default }, + { "max_linkrate", 8, 9, &umr_bitfield_default }, + { "pcs_freq", 10, 11, &umr_bitfield_default }, + { "pcs_clken", 12, 12, &umr_bitfield_default }, + { "pcs_clkdone", 13, 13, &umr_bitfield_default }, + { "pll1_always_on", 14, 14, &umr_bitfield_default }, + { "rdclk_div2_en", 15, 15, &umr_bitfield_default }, + { "tx_boost_adj", 16, 19, &umr_bitfield_default }, + { "tx_boost_en", 20, 20, &umr_bitfield_default }, + { "tx_binary_ron_code_offset", 22, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3[] = { + { "rfu_value0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3[] = { + { "rfu_value1", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3[] = { + { "rfu_value2", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3[] = { + { "rfu_value3", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3[] = { + { "rfu_value4", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3[] = { + { "rfu_value5", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3[] = { + { "rfu_value6", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3[] = { + { "rfu_value7", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3[] = { + { "rfu_value8", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3[] = { + { "rfu_value9", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3[] = { + { "rfu_value10", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3[] = { + { "rfu_value11", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3[] = { + { "rfu_value12", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYPLLREGS2_FREQ_CTRL0[] = { + { "fcw0_frac", 0, 15, &umr_bitfield_default }, + { "fcw0_int", 16, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYPLLREGS2_FREQ_CTRL1[] = { + { "fcw1_frac", 0, 15, &umr_bitfield_default }, + { "fcw1_int", 16, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYPLLREGS2_FREQ_CTRL2[] = { + { "fcw_denom", 0, 15, &umr_bitfield_default }, + { "fcw_slew_frac", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYPLLREGS2_FREQ_CTRL3[] = { + { "refclk_div", 0, 1, &umr_bitfield_default }, + { "vco_pre_div", 3, 4, &umr_bitfield_default }, + { "fracn_en", 6, 6, &umr_bitfield_default }, + { "ssc_en", 8, 8, &umr_bitfield_default }, + { "fcw_sel", 10, 10, &umr_bitfield_default }, + { "freq_jump_en", 12, 12, &umr_bitfield_default }, + { "tdc_resolution", 16, 23, &umr_bitfield_default }, + { "dpll_cfg_1", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYPLLREGS2_BW_CTRL_COARSE[] = { + { "gi_coarse_mant", 0, 1, &umr_bitfield_default }, + { "gi_coarse_exp", 2, 5, &umr_bitfield_default }, + { "gp_coarse_mant", 7, 10, &umr_bitfield_default }, + { "gp_coarse_exp", 12, 15, &umr_bitfield_default }, + { "nctl_coarse_res", 17, 22, &umr_bitfield_default }, + { "nctl_coarse_frac_res", 24, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYPLLREGS2_BW_CTRL_FINE[] = { + { "dpll_cfg_3", 0, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYPLLREGS2_CAL_CTRL[] = { + { "bypass_freq_lock", 0, 0, &umr_bitfield_default }, + { "tdc_cal_en", 1, 1, &umr_bitfield_default }, + { "tdc_cal_ctrl", 3, 8, &umr_bitfield_default }, + { "meas_win_sel", 9, 10, &umr_bitfield_default }, + { "kdco_cal_dis", 11, 11, &umr_bitfield_default }, + { "kdco_ratio", 13, 20, &umr_bitfield_default }, + { "kdco_incr_cal_dis", 22, 22, &umr_bitfield_default }, + { "nctl_adj_dis", 23, 23, &umr_bitfield_default }, + { "refclk_rate", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYPLLREGS2_LOOP_CTRL[] = { + { "fbdiv_mask_en", 0, 0, &umr_bitfield_default }, + { "fb_slip_dis", 2, 2, &umr_bitfield_default }, + { "clk_tdc_sel", 4, 5, &umr_bitfield_default }, + { "clk_nctl_sel", 7, 8, &umr_bitfield_default }, + { "sig_del_patt_sel", 10, 10, &umr_bitfield_default }, + { "nctl_sig_del_dis", 12, 12, &umr_bitfield_default }, + { "fbclk_track_refclk", 14, 14, &umr_bitfield_default }, + { "prbs_en", 16, 16, &umr_bitfield_default }, + { "tdc_clk_gate_en", 18, 18, &umr_bitfield_default }, + { "phase_offset", 20, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYPLLREGS2_VREG_CFG[] = { + { "bleeder_ac", 0, 0, &umr_bitfield_default }, + { "bleeder_en", 1, 1, &umr_bitfield_default }, + { "is_1p2", 2, 2, &umr_bitfield_default }, + { "reg_obs_sel", 3, 4, &umr_bitfield_default }, + { "reg_on_mode", 5, 6, &umr_bitfield_default }, + { "rlad_tap_sel", 7, 10, &umr_bitfield_default }, + { "reg_off_hi", 11, 11, &umr_bitfield_default }, + { "reg_off_lo", 12, 12, &umr_bitfield_default }, + { "scale_driver", 13, 14, &umr_bitfield_default }, + { "sel_bump", 15, 15, &umr_bitfield_default }, + { "sel_rladder_x", 16, 16, &umr_bitfield_default }, + { "short_rc_filt_x", 17, 17, &umr_bitfield_default }, + { "vref_pwr_on", 18, 18, &umr_bitfield_default }, + { "dpll_cfg_2", 20, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYPLLREGS2_OBSERVE0[] = { + { "lock_det_tdc_steps", 0, 4, &umr_bitfield_default }, + { "clear_sticky_lock", 6, 6, &umr_bitfield_default }, + { "lock_det_dis", 8, 8, &umr_bitfield_default }, + { "dco_cfg", 10, 17, &umr_bitfield_default }, + { "anaobs_sel", 21, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYPLLREGS2_OBSERVE1[] = { + { "digobs_sel", 0, 3, &umr_bitfield_default }, + { "digobs_trig_sel", 5, 8, &umr_bitfield_default }, + { "digobs_div", 10, 11, &umr_bitfield_default }, + { "digobs_trig_div", 13, 14, &umr_bitfield_default }, + { "lock_timer", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYPLLREGS2_DFT_OUT[] = { + { "dft_data", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL1[] = { + { "wrap_cfg_sel_clk", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL[] = { + { "wrap_cfg_pll_freq_programming_ovveride", 0, 0, &umr_bitfield_default }, + { "wrap_cfg_pll_pwr_state_ovrride", 1, 1, &umr_bitfield_default }, + { "wrap_cfg_pll_pwr_state", 2, 3, &umr_bitfield_default }, + { "wrap_cfg_tx_pdiv_val", 5, 7, &umr_bitfield_default }, + { "wrap_cfg_tx_pixdiv_val", 8, 8, &umr_bitfield_default }, + { "wrap_cfg_cml_cmos_sel", 10, 10, &umr_bitfield_default }, + { "wrap_cfg_pll_rdy", 13, 13, &umr_bitfield_default }, + { "wrap_cfg_pll_update", 14, 14, &umr_bitfield_default }, + { "wrap_cfg_ref_values_chg", 15, 15, &umr_bitfield_default }, + { "wrap_cfg_clk_gate_w_rdy", 16, 16, &umr_bitfield_default }, + { "wrap_cfg_pll_dsm_sel", 17, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159[] = { + { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYCMREGS3_COMMON_FUSE1[] = { + { "fuse1_valid", 0, 0, &umr_bitfield_default }, + { "fuse1_unpopulated0", 1, 2, &umr_bitfield_default }, + { "fuse1_ron_override_val", 3, 8, &umr_bitfield_default }, + { "fuse1_unpopulated1", 9, 9, &umr_bitfield_default }, + { "fuse1_ron_ctl", 10, 11, &umr_bitfield_default }, + { "fuse1_unpopulated2", 12, 12, &umr_bitfield_default }, + { "fuse1_rtt_override_val", 13, 18, &umr_bitfield_default }, + { "fuse1_unpopulated3", 19, 19, &umr_bitfield_default }, + { "fuse1_rtt_ctl", 20, 21, &umr_bitfield_default }, + { "fuse1_refresh_cal_en", 22, 22, &umr_bitfield_default }, + { "fuse1_spare", 23, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYCMREGS3_COMMON_FUSE2[] = { + { "fuse2_valid", 0, 0, &umr_bitfield_default }, + { "fuse2_unpopulated", 1, 8, &umr_bitfield_default }, + { "fuse2_tx_fifo_ptr", 9, 13, &umr_bitfield_default }, + { "fuse2_spare", 14, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYCMREGS3_COMMON_FUSE3[] = { + { "fuse3_valid", 0, 0, &umr_bitfield_default }, + { "fuse3_unpopulated", 1, 9, &umr_bitfield_default }, + { "fuse3_ei_det_thresh_sel", 10, 12, &umr_bitfield_default }, + { "cdr_dac_safeval_sel", 13, 15, &umr_bitfield_default }, + { "cdr_freq_lock_timer", 16, 17, &umr_bitfield_default }, + { "cdr_cal_dac_stpsz", 18, 19, &umr_bitfield_default }, + { "cdr_byp_init_val", 20, 20, &umr_bitfield_default }, + { "cdr_icostart_sel", 21, 21, &umr_bitfield_default }, + { "cdr_bbweight", 22, 25, &umr_bitfield_default }, + { "cdr_cur_mirr_ratio", 26, 28, &umr_bitfield_default }, + { "fuse3_spare", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM[] = { + { "tx_margin_nom", 0, 7, &umr_bitfield_default }, + { "deemph_gen1_nom", 8, 15, &umr_bitfield_default }, + { "deemph35_gen2_nom", 16, 23, &umr_bitfield_default }, + { "deemph60_gen2_nom", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT[] = { + { "pgdelay", 0, 3, &umr_bitfield_default }, + { "pgmask", 4, 9, &umr_bitfield_default }, + { "vprot_en", 11, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYCMREGS3_COMMON_TXCNTRL[] = { + { "rdptr_rst_val_gen3", 0, 4, &umr_bitfield_default }, + { "clkgate_dis", 5, 5, &umr_bitfield_default }, + { "slew_rate_ctl_gen1", 6, 8, &umr_bitfield_default }, + { "slew_rate_ctl_gen2", 9, 11, &umr_bitfield_default }, + { "slew_rate_ctl_gen3", 12, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYCMREGS3_COMMON_TMDP[] = { + { "tmdp_spare", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYCMREGS3_COMMON_LANE_RESETS[] = { + { "lane_0_reset_l", 0, 0, &umr_bitfield_default }, + { "lane_1_reset_l", 1, 1, &umr_bitfield_default }, + { "lane_2_reset_l", 2, 2, &umr_bitfield_default }, + { "lane_3_reset_l", 3, 3, &umr_bitfield_default }, + { "lane_4_reset_l", 4, 4, &umr_bitfield_default }, + { "lane_5_reset_l", 5, 5, &umr_bitfield_default }, + { "lane_6_reset_l", 6, 6, &umr_bitfield_default }, + { "lane_7_reset_l", 7, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL[] = { + { "zcalcode_override", 0, 0, &umr_bitfield_default }, + { "tx_binary_code_override_val", 1, 5, &umr_bitfield_default }, + { "rx_therm_code_override_val", 6, 20, &umr_bitfield_default }, + { "tx_driver_fifty_ohms", 21, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU1[] = { + { "rfu_value1", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU2[] = { + { "rfu_value2", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU3[] = { + { "rfu_value3", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU4[] = { + { "rfu_value4", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU5[] = { + { "rfu_value5", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU6[] = { + { "rfu_value6", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU7[] = { + { "rfu_value7", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0[] = { + { "tx_pwr", 0, 2, &umr_bitfield_default }, + { "tx_pg_en", 3, 4, &umr_bitfield_default }, + { "tx_rdy", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0[] = { + { "txmarg_sel", 0, 2, &umr_bitfield_default }, + { "deemph_sel", 3, 4, &umr_bitfield_default }, + { "tx_margin_en", 5, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0[] = { + { "twosym_en", 1, 2, &umr_bitfield_default }, + { "link_speed", 3, 4, &umr_bitfield_default }, + { "gang_mode", 5, 7, &umr_bitfield_default }, + { "max_linkrate", 8, 9, &umr_bitfield_default }, + { "pcs_freq", 10, 11, &umr_bitfield_default }, + { "pcs_clken", 12, 12, &umr_bitfield_default }, + { "pcs_clkdone", 13, 13, &umr_bitfield_default }, + { "pll1_always_on", 14, 14, &umr_bitfield_default }, + { "rdclk_div2_en", 15, 15, &umr_bitfield_default }, + { "tx_boost_adj", 16, 19, &umr_bitfield_default }, + { "tx_boost_en", 20, 20, &umr_bitfield_default }, + { "tx_binary_ron_code_offset", 22, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0[] = { + { "rfu_value0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0[] = { + { "rfu_value1", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0[] = { + { "rfu_value2", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0[] = { + { "rfu_value3", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0[] = { + { "rfu_value4", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0[] = { + { "rfu_value5", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0[] = { + { "rfu_value6", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0[] = { + { "rfu_value7", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0[] = { + { "rfu_value8", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0[] = { + { "rfu_value9", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0[] = { + { "rfu_value10", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0[] = { + { "rfu_value11", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0[] = { + { "rfu_value12", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1[] = { + { "tx_pwr", 0, 2, &umr_bitfield_default }, + { "tx_pg_en", 3, 4, &umr_bitfield_default }, + { "tx_rdy", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1[] = { + { "txmarg_sel", 0, 2, &umr_bitfield_default }, + { "deemph_sel", 3, 4, &umr_bitfield_default }, + { "tx_margin_en", 5, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1[] = { + { "twosym_en", 1, 2, &umr_bitfield_default }, + { "link_speed", 3, 4, &umr_bitfield_default }, + { "gang_mode", 5, 7, &umr_bitfield_default }, + { "max_linkrate", 8, 9, &umr_bitfield_default }, + { "pcs_freq", 10, 11, &umr_bitfield_default }, + { "pcs_clken", 12, 12, &umr_bitfield_default }, + { "pcs_clkdone", 13, 13, &umr_bitfield_default }, + { "pll1_always_on", 14, 14, &umr_bitfield_default }, + { "rdclk_div2_en", 15, 15, &umr_bitfield_default }, + { "tx_boost_adj", 16, 19, &umr_bitfield_default }, + { "tx_boost_en", 20, 20, &umr_bitfield_default }, + { "tx_binary_ron_code_offset", 22, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1[] = { + { "rfu_value0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1[] = { + { "rfu_value1", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1[] = { + { "rfu_value2", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1[] = { + { "rfu_value3", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1[] = { + { "rfu_value4", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1[] = { + { "rfu_value5", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1[] = { + { "rfu_value6", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1[] = { + { "rfu_value7", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1[] = { + { "rfu_value8", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1[] = { + { "rfu_value9", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1[] = { + { "rfu_value10", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1[] = { + { "rfu_value11", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1[] = { + { "rfu_value12", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2[] = { + { "tx_pwr", 0, 2, &umr_bitfield_default }, + { "tx_pg_en", 3, 4, &umr_bitfield_default }, + { "tx_rdy", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2[] = { + { "txmarg_sel", 0, 2, &umr_bitfield_default }, + { "deemph_sel", 3, 4, &umr_bitfield_default }, + { "tx_margin_en", 5, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2[] = { + { "twosym_en", 1, 2, &umr_bitfield_default }, + { "link_speed", 3, 4, &umr_bitfield_default }, + { "gang_mode", 5, 7, &umr_bitfield_default }, + { "max_linkrate", 8, 9, &umr_bitfield_default }, + { "pcs_freq", 10, 11, &umr_bitfield_default }, + { "pcs_clken", 12, 12, &umr_bitfield_default }, + { "pcs_clkdone", 13, 13, &umr_bitfield_default }, + { "pll1_always_on", 14, 14, &umr_bitfield_default }, + { "rdclk_div2_en", 15, 15, &umr_bitfield_default }, + { "tx_boost_adj", 16, 19, &umr_bitfield_default }, + { "tx_boost_en", 20, 20, &umr_bitfield_default }, + { "tx_binary_ron_code_offset", 22, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2[] = { + { "rfu_value0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2[] = { + { "rfu_value1", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2[] = { + { "rfu_value2", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2[] = { + { "rfu_value3", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2[] = { + { "rfu_value4", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2[] = { + { "rfu_value5", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2[] = { + { "rfu_value6", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2[] = { + { "rfu_value7", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2[] = { + { "rfu_value8", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2[] = { + { "rfu_value9", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2[] = { + { "rfu_value10", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2[] = { + { "rfu_value11", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2[] = { + { "rfu_value12", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3[] = { + { "tx_pwr", 0, 2, &umr_bitfield_default }, + { "tx_pg_en", 3, 4, &umr_bitfield_default }, + { "tx_rdy", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3[] = { + { "txmarg_sel", 0, 2, &umr_bitfield_default }, + { "deemph_sel", 3, 4, &umr_bitfield_default }, + { "tx_margin_en", 5, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3[] = { + { "twosym_en", 1, 2, &umr_bitfield_default }, + { "link_speed", 3, 4, &umr_bitfield_default }, + { "gang_mode", 5, 7, &umr_bitfield_default }, + { "max_linkrate", 8, 9, &umr_bitfield_default }, + { "pcs_freq", 10, 11, &umr_bitfield_default }, + { "pcs_clken", 12, 12, &umr_bitfield_default }, + { "pcs_clkdone", 13, 13, &umr_bitfield_default }, + { "pll1_always_on", 14, 14, &umr_bitfield_default }, + { "rdclk_div2_en", 15, 15, &umr_bitfield_default }, + { "tx_boost_adj", 16, 19, &umr_bitfield_default }, + { "tx_boost_en", 20, 20, &umr_bitfield_default }, + { "tx_binary_ron_code_offset", 22, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3[] = { + { "rfu_value0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3[] = { + { "rfu_value1", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3[] = { + { "rfu_value2", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3[] = { + { "rfu_value3", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3[] = { + { "rfu_value4", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3[] = { + { "rfu_value5", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3[] = { + { "rfu_value6", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3[] = { + { "rfu_value7", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3[] = { + { "rfu_value8", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3[] = { + { "rfu_value9", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3[] = { + { "rfu_value10", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3[] = { + { "rfu_value11", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3[] = { + { "rfu_value12", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYPLLREGS3_FREQ_CTRL0[] = { + { "fcw0_frac", 0, 15, &umr_bitfield_default }, + { "fcw0_int", 16, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYPLLREGS3_FREQ_CTRL1[] = { + { "fcw1_frac", 0, 15, &umr_bitfield_default }, + { "fcw1_int", 16, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYPLLREGS3_FREQ_CTRL2[] = { + { "fcw_denom", 0, 15, &umr_bitfield_default }, + { "fcw_slew_frac", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYPLLREGS3_FREQ_CTRL3[] = { + { "refclk_div", 0, 1, &umr_bitfield_default }, + { "vco_pre_div", 3, 4, &umr_bitfield_default }, + { "fracn_en", 6, 6, &umr_bitfield_default }, + { "ssc_en", 8, 8, &umr_bitfield_default }, + { "fcw_sel", 10, 10, &umr_bitfield_default }, + { "freq_jump_en", 12, 12, &umr_bitfield_default }, + { "tdc_resolution", 16, 23, &umr_bitfield_default }, + { "dpll_cfg_1", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYPLLREGS3_BW_CTRL_COARSE[] = { + { "gi_coarse_mant", 0, 1, &umr_bitfield_default }, + { "gi_coarse_exp", 2, 5, &umr_bitfield_default }, + { "gp_coarse_mant", 7, 10, &umr_bitfield_default }, + { "gp_coarse_exp", 12, 15, &umr_bitfield_default }, + { "nctl_coarse_res", 17, 22, &umr_bitfield_default }, + { "nctl_coarse_frac_res", 24, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYPLLREGS3_BW_CTRL_FINE[] = { + { "dpll_cfg_3", 0, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYPLLREGS3_CAL_CTRL[] = { + { "bypass_freq_lock", 0, 0, &umr_bitfield_default }, + { "tdc_cal_en", 1, 1, &umr_bitfield_default }, + { "tdc_cal_ctrl", 3, 8, &umr_bitfield_default }, + { "meas_win_sel", 9, 10, &umr_bitfield_default }, + { "kdco_cal_dis", 11, 11, &umr_bitfield_default }, + { "kdco_ratio", 13, 20, &umr_bitfield_default }, + { "kdco_incr_cal_dis", 22, 22, &umr_bitfield_default }, + { "nctl_adj_dis", 23, 23, &umr_bitfield_default }, + { "refclk_rate", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYPLLREGS3_LOOP_CTRL[] = { + { "fbdiv_mask_en", 0, 0, &umr_bitfield_default }, + { "fb_slip_dis", 2, 2, &umr_bitfield_default }, + { "clk_tdc_sel", 4, 5, &umr_bitfield_default }, + { "clk_nctl_sel", 7, 8, &umr_bitfield_default }, + { "sig_del_patt_sel", 10, 10, &umr_bitfield_default }, + { "nctl_sig_del_dis", 12, 12, &umr_bitfield_default }, + { "fbclk_track_refclk", 14, 14, &umr_bitfield_default }, + { "prbs_en", 16, 16, &umr_bitfield_default }, + { "tdc_clk_gate_en", 18, 18, &umr_bitfield_default }, + { "phase_offset", 20, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYPLLREGS3_VREG_CFG[] = { + { "bleeder_ac", 0, 0, &umr_bitfield_default }, + { "bleeder_en", 1, 1, &umr_bitfield_default }, + { "is_1p2", 2, 2, &umr_bitfield_default }, + { "reg_obs_sel", 3, 4, &umr_bitfield_default }, + { "reg_on_mode", 5, 6, &umr_bitfield_default }, + { "rlad_tap_sel", 7, 10, &umr_bitfield_default }, + { "reg_off_hi", 11, 11, &umr_bitfield_default }, + { "reg_off_lo", 12, 12, &umr_bitfield_default }, + { "scale_driver", 13, 14, &umr_bitfield_default }, + { "sel_bump", 15, 15, &umr_bitfield_default }, + { "sel_rladder_x", 16, 16, &umr_bitfield_default }, + { "short_rc_filt_x", 17, 17, &umr_bitfield_default }, + { "vref_pwr_on", 18, 18, &umr_bitfield_default }, + { "dpll_cfg_2", 20, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYPLLREGS3_OBSERVE0[] = { + { "lock_det_tdc_steps", 0, 4, &umr_bitfield_default }, + { "clear_sticky_lock", 6, 6, &umr_bitfield_default }, + { "lock_det_dis", 8, 8, &umr_bitfield_default }, + { "dco_cfg", 10, 17, &umr_bitfield_default }, + { "anaobs_sel", 21, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYPLLREGS3_OBSERVE1[] = { + { "digobs_sel", 0, 3, &umr_bitfield_default }, + { "digobs_trig_sel", 5, 8, &umr_bitfield_default }, + { "digobs_div", 10, 11, &umr_bitfield_default }, + { "digobs_trig_div", 13, 14, &umr_bitfield_default }, + { "lock_timer", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYPLLREGS3_DFT_OUT[] = { + { "dft_data", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL1[] = { + { "wrap_cfg_sel_clk", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL[] = { + { "wrap_cfg_pll_freq_programming_ovveride", 0, 0, &umr_bitfield_default }, + { "wrap_cfg_pll_pwr_state_ovrride", 1, 1, &umr_bitfield_default }, + { "wrap_cfg_pll_pwr_state", 2, 3, &umr_bitfield_default }, + { "wrap_cfg_tx_pdiv_val", 5, 7, &umr_bitfield_default }, + { "wrap_cfg_tx_pixdiv_val", 8, 8, &umr_bitfield_default }, + { "wrap_cfg_cml_cmos_sel", 10, 10, &umr_bitfield_default }, + { "wrap_cfg_pll_rdy", 13, 13, &umr_bitfield_default }, + { "wrap_cfg_pll_update", 14, 14, &umr_bitfield_default }, + { "wrap_cfg_ref_values_chg", 15, 15, &umr_bitfield_default }, + { "wrap_cfg_clk_gate_w_rdy", 16, 16, &umr_bitfield_default }, + { "wrap_cfg_pll_dsm_sel", 17, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmZCAL_MACRO_CNTL_RESERVED0[] = { + { "ZCAL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmZCAL_MACRO_CNTL_RESERVED1[] = { + { "ZCAL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmZCAL_MACRO_CNTL_RESERVED2[] = { + { "ZCAL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmZCAL_MACRO_CNTL_RESERVED3[] = { + { "ZCAL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmZCAL_MACRO_CNTL_RESERVED4[] = { + { "ZCAL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCOMP_EN_CTL[] = { + { "comp_en", 0, 0, &umr_bitfield_default }, + { "comp_en_override", 2, 2, &umr_bitfield_default }, + { "comp_done", 4, 4, &umr_bitfield_default }, + { "zcal_code_override", 6, 6, &umr_bitfield_default }, + { "zcal_cal_rtt", 7, 7, &umr_bitfield_default }, + { "zcal_base_en", 8, 8, &umr_bitfield_default }, + { "zcal_ht_rtt_sel", 9, 9, &umr_bitfield_default }, + { "zcal_code", 10, 14, &umr_bitfield_default }, + { "zcal_ron_cal_mode", 16, 16, &umr_bitfield_default }, + { "zcal_ana_dbg_sel", 17, 18, &umr_bitfield_default }, + { "cfg_cml_cmos_sel", 19, 19, &umr_bitfield_default }, + { "dsm_sel", 20, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCOMP_EN_DFX[] = { + { "autocal_ron_code", 0, 4, &umr_bitfield_default }, + { "autocal_rtt_code", 5, 9, &umr_bitfield_default }, + { "pre_fused_ron_code", 11, 15, &umr_bitfield_default }, + { "pre_fused_rtt_code", 16, 20, &umr_bitfield_default }, + { "broadcast_ron_code", 22, 26, &umr_bitfield_default }, + { "broadcast_rtt_code", 27, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmZCAL_FUSES[] = { + { "fuse_valid", 0, 0, &umr_bitfield_default }, + { "fuse_ron_override_val", 3, 8, &umr_bitfield_default }, + { "fuse_ron_ctl", 10, 11, &umr_bitfield_default }, + { "fuse_rtt_override_val", 13, 18, &umr_bitfield_default }, + { "fuse_rtt_ctl", 20, 21, &umr_bitfield_default }, + { "fuse_refresh_cal_en", 22, 22, &umr_bitfield_default }, + { "fuse_spare", 23, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSEQ00[] = { + { "SEQ_RST0B", 0, 0, &umr_bitfield_default }, + { "SEQ_RST1B", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSEQ01[] = { + { "SEQ_DOT8", 0, 0, &umr_bitfield_default }, + { "SEQ_SHIFT2", 2, 2, &umr_bitfield_default }, + { "SEQ_PCLKBY2", 3, 3, &umr_bitfield_default }, + { "SEQ_SHIFT4", 4, 4, &umr_bitfield_default }, + { "SEQ_MAXBW", 5, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSEQ02[] = { + { "SEQ_MAP0_EN", 0, 0, &umr_bitfield_default }, + { "SEQ_MAP1_EN", 1, 1, &umr_bitfield_default }, + { "SEQ_MAP2_EN", 2, 2, &umr_bitfield_default }, + { "SEQ_MAP3_EN", 3, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSEQ03[] = { + { "SEQ_FONT_B1", 0, 0, &umr_bitfield_default }, + { "SEQ_FONT_B2", 1, 1, &umr_bitfield_default }, + { "SEQ_FONT_A1", 2, 2, &umr_bitfield_default }, + { "SEQ_FONT_A2", 3, 3, &umr_bitfield_default }, + { "SEQ_FONT_B0", 4, 4, &umr_bitfield_default }, + { "SEQ_FONT_A0", 5, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSEQ04[] = { + { "SEQ_256K", 1, 1, &umr_bitfield_default }, + { "SEQ_ODDEVEN", 2, 2, &umr_bitfield_default }, + { "SEQ_CHAIN", 3, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield ixCRT00[] = { + { "H_TOTAL", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixCRT01[] = { + { "H_DISP_END", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixCRT02[] = { + { "H_BLANK_START", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixCRT03[] = { + { "H_BLANK_END", 0, 4, &umr_bitfield_default }, + { "H_DE_SKEW", 5, 6, &umr_bitfield_default }, + { "CR10CR11_R_DIS_B", 7, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixCRT04[] = { + { "H_SYNC_START", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixCRT05[] = { + { "H_SYNC_END", 0, 4, &umr_bitfield_default }, + { "H_SYNC_SKEW", 5, 6, &umr_bitfield_default }, + { "H_BLANK_END_B5", 7, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixCRT06[] = { + { "V_TOTAL", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixCRT07[] = { + { "V_TOTAL_B8", 0, 0, &umr_bitfield_default }, + { "V_DISP_END_B8", 1, 1, &umr_bitfield_default }, + { "V_SYNC_START_B8", 2, 2, &umr_bitfield_default }, + { "V_BLANK_START_B8", 3, 3, &umr_bitfield_default }, + { "LINE_CMP_B8", 4, 4, &umr_bitfield_default }, + { "V_TOTAL_B9", 5, 5, &umr_bitfield_default }, + { "V_DISP_END_B9", 6, 6, &umr_bitfield_default }, + { "V_SYNC_START_B9", 7, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixCRT08[] = { + { "ROW_SCAN_START", 0, 4, &umr_bitfield_default }, + { "BYTE_PAN", 5, 6, &umr_bitfield_default }, +}; +static struct umr_bitfield ixCRT09[] = { + { "MAX_ROW_SCAN", 0, 4, &umr_bitfield_default }, + { "V_BLANK_START_B9", 5, 5, &umr_bitfield_default }, + { "LINE_CMP_B9", 6, 6, &umr_bitfield_default }, + { "DOUBLE_CHAR_HEIGHT", 7, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixCRT0A[] = { + { "CURSOR_START", 0, 4, &umr_bitfield_default }, + { "CURSOR_DISABLE", 5, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield ixCRT0B[] = { + { "CURSOR_END", 0, 4, &umr_bitfield_default }, + { "CURSOR_SKEW", 5, 6, &umr_bitfield_default }, +}; +static struct umr_bitfield ixCRT0C[] = { + { "DISP_START", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixCRT0D[] = { + { "DISP_START", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixCRT0E[] = { + { "CURSOR_LOC_HI", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixCRT0F[] = { + { "CURSOR_LOC_LO", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixCRT10[] = { + { "V_SYNC_START", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixCRT11[] = { + { "V_SYNC_END", 0, 3, &umr_bitfield_default }, + { "V_INTR_CLR", 4, 4, &umr_bitfield_default }, + { "V_INTR_EN", 5, 5, &umr_bitfield_default }, + { "SEL5_REFRESH_CYC", 6, 6, &umr_bitfield_default }, + { "C0T7_WR_ONLY", 7, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixCRT12[] = { + { "V_DISP_END", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixCRT13[] = { + { "DISP_PITCH", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixCRT14[] = { + { "UNDRLN_LOC", 0, 4, &umr_bitfield_default }, + { "ADDR_CNT_BY4", 5, 5, &umr_bitfield_default }, + { "DOUBLE_WORD", 6, 6, &umr_bitfield_default }, +}; +static struct umr_bitfield ixCRT15[] = { + { "V_BLANK_START", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixCRT16[] = { + { "V_BLANK_END", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixCRT17[] = { + { "RA0_AS_A13B", 0, 0, &umr_bitfield_default }, + { "RA1_AS_A14B", 1, 1, &umr_bitfield_default }, + { "VCOUNT_BY2", 2, 2, &umr_bitfield_default }, + { "ADDR_CNT_BY2", 3, 3, &umr_bitfield_default }, + { "WRAP_A15TOA0", 5, 5, &umr_bitfield_default }, + { "BYTE_MODE", 6, 6, &umr_bitfield_default }, + { "CRTC_SYNC_EN", 7, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixCRT18[] = { + { "LINE_CMP", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixCRT1E[] = { + { "GRPH_DEC_RD1", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield ixCRT1F[] = { + { "GRPH_DEC_RD0", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixCRT22[] = { + { "GRPH_LATCH_DATA", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGRA00[] = { + { "GRPH_SET_RESET0", 0, 0, &umr_bitfield_default }, + { "GRPH_SET_RESET1", 1, 1, &umr_bitfield_default }, + { "GRPH_SET_RESET2", 2, 2, &umr_bitfield_default }, + { "GRPH_SET_RESET3", 3, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGRA01[] = { + { "GRPH_SET_RESET_ENA0", 0, 0, &umr_bitfield_default }, + { "GRPH_SET_RESET_ENA1", 1, 1, &umr_bitfield_default }, + { "GRPH_SET_RESET_ENA2", 2, 2, &umr_bitfield_default }, + { "GRPH_SET_RESET_ENA3", 3, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGRA02[] = { + { "GRPH_CCOMP", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGRA03[] = { + { "GRPH_ROTATE", 0, 2, &umr_bitfield_default }, + { "GRPH_FN_SEL", 3, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGRA04[] = { + { "GRPH_RMAP", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGRA05[] = { + { "GRPH_WRITE_MODE", 0, 1, &umr_bitfield_default }, + { "GRPH_READ1", 3, 3, &umr_bitfield_default }, + { "CGA_ODDEVEN", 4, 4, &umr_bitfield_default }, + { "GRPH_OES", 5, 5, &umr_bitfield_default }, + { "GRPH_PACK", 6, 6, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGRA06[] = { + { "GRPH_GRAPHICS", 0, 0, &umr_bitfield_default }, + { "GRPH_ODDEVEN", 1, 1, &umr_bitfield_default }, + { "GRPH_ADRSEL", 2, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGRA07[] = { + { "GRPH_XCARE0", 0, 0, &umr_bitfield_default }, + { "GRPH_XCARE1", 1, 1, &umr_bitfield_default }, + { "GRPH_XCARE2", 2, 2, &umr_bitfield_default }, + { "GRPH_XCARE3", 3, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGRA08[] = { + { "GRPH_BMSK", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixATTR00[] = { + { "ATTR_PAL", 0, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield ixATTR01[] = { + { "ATTR_PAL", 0, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield ixATTR02[] = { + { "ATTR_PAL", 0, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield ixATTR03[] = { + { "ATTR_PAL", 0, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield ixATTR04[] = { + { "ATTR_PAL", 0, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield ixATTR05[] = { + { "ATTR_PAL", 0, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield ixATTR06[] = { + { "ATTR_PAL", 0, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield ixATTR07[] = { + { "ATTR_PAL", 0, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield ixATTR08[] = { + { "ATTR_PAL", 0, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield ixATTR09[] = { + { "ATTR_PAL", 0, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield ixATTR0A[] = { + { "ATTR_PAL", 0, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield ixATTR0B[] = { + { "ATTR_PAL", 0, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield ixATTR0C[] = { + { "ATTR_PAL", 0, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield ixATTR0D[] = { + { "ATTR_PAL", 0, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield ixATTR0E[] = { + { "ATTR_PAL", 0, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield ixATTR0F[] = { + { "ATTR_PAL", 0, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield ixATTR10[] = { + { "ATTR_GRPH_MODE", 0, 0, &umr_bitfield_default }, + { "ATTR_MONO_EN", 1, 1, &umr_bitfield_default }, + { "ATTR_LGRPH_EN", 2, 2, &umr_bitfield_default }, + { "ATTR_BLINK_EN", 3, 3, &umr_bitfield_default }, + { "ATTR_PANTOPONLY", 5, 5, &umr_bitfield_default }, + { "ATTR_PCLKBY2", 6, 6, &umr_bitfield_default }, + { "ATTR_CSEL_EN", 7, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixATTR11[] = { + { "ATTR_OVSC", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixATTR12[] = { + { "ATTR_MAP_EN", 0, 3, &umr_bitfield_default }, + { "ATTR_VSMUX", 4, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield ixATTR13[] = { + { "ATTR_PPAN", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield ixATTR14[] = { + { "ATTR_CSEL1", 0, 1, &umr_bitfield_default }, + { "ATTR_CSEL2", 2, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT[] = { + { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default }, + { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default }, + { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default }, + { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default }, + { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default }, + { "STREAM_TYPE", 15, 15, &umr_bitfield_default }, + { "STREAM_TYPE_R", 15, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID[] = { + { "CHANNEL_ID", 0, 3, &umr_bitfield_default }, + { "STREAM_ID", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER[] = { + { "DIGEN", 0, 0, &umr_bitfield_default }, + { "V", 1, 1, &umr_bitfield_default }, + { "VCFG", 2, 2, &umr_bitfield_default }, + { "PRE", 3, 3, &umr_bitfield_default }, + { "COPY", 4, 4, &umr_bitfield_default }, + { "NON_AUDIO", 5, 5, &umr_bitfield_default }, + { "PRO", 6, 6, &umr_bitfield_default }, + { "L", 7, 7, &umr_bitfield_default }, + { "CC", 8, 14, &umr_bitfield_default }, + { "KEEPALIVE", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2[] = { + { "CC", 0, 6, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL[] = { + { "STRIPE_CONTROL", 0, 1, &umr_bitfield_default }, + { "STRIPE_CAPABILITY", 20, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3[] = { + { "KEEPALIVE", 7, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE[] = { + { "RAMP_RATE", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING[] = { + { "PRESENTATION_TIME_EMBEDDING_ENABLE", 0, 0, &umr_bitfield_default }, + { "PRESENTATION_TIME_OFFSET_CHANGED", 1, 1, &umr_bitfield_default }, + { "PRESENTATION_TIME_EMBEDDING_GROUP", 4, 6, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = { + { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default }, + { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default }, + { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default }, + { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default }, + { "FORMAT_OVERRIDE", 4, 4, &umr_bitfield_default }, + { "STRIPE", 5, 5, &umr_bitfield_default }, + { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default }, + { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default }, + { "CONNECTION_LIST", 8, 8, &umr_bitfield_default }, + { "DIGITAL", 9, 9, &umr_bitfield_default }, + { "POWER_CONTROL", 10, 10, &umr_bitfield_default }, + { "LR_SWAP", 11, 11, &umr_bitfield_default }, + { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default }, + { "TYPE", 20, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[] = { + { "AUDIO_RATE_CAPABILITIES", 0, 11, &umr_bitfield_default }, + { "AUDIO_BIT_CAPABILITIES", 16, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS[] = { + { "STREAM_FORMATS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY[] = { + { "CONNECTION_LIST_ENTRY", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL[] = { + { "OUT_ENABLE", 6, 6, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE[] = { + { "TAG", 0, 5, &umr_bitfield_default }, + { "ENABLE", 7, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE[] = { + { "IMPEDANCE_SENSE", 0, 30, &umr_bitfield_default }, + { "PRESENCE_DETECT", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[] = { + { "SEQUENCE", 0, 3, &umr_bitfield_default }, + { "DEFAULT_ASSOCIATION", 4, 7, &umr_bitfield_default }, + { "MISC", 8, 11, &umr_bitfield_default }, + { "COLOR", 12, 15, &umr_bitfield_default }, + { "CONNECTION_TYPE", 16, 19, &umr_bitfield_default }, + { "DEFAULT_DEVICE", 20, 23, &umr_bitfield_default }, + { "LOCATION", 24, 29, &umr_bitfield_default }, + { "PORT_CONNECTIVITY", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2[] = { + { "MISC", 0, 3, &umr_bitfield_default }, + { "COLOR", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3[] = { + { "CONNECTION_TYPE", 0, 3, &umr_bitfield_default }, + { "DEFAULT_DEVICE", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4[] = { + { "LOCATION", 0, 5, &umr_bitfield_default }, + { "PORT_CONNECTIVITY", 6, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION[] = { + { "SPEAKER_ALLOCATION", 0, 6, &umr_bitfield_default }, + { "HDMI_CONNECTION", 8, 8, &umr_bitfield_default }, + { "DP_CONNECTION", 9, 9, &umr_bitfield_default }, + { "EXTRA_CONNECTION_INFO", 10, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION[] = { + { "CHANNEL_ALLOCATION", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO[] = { + { "LFE_PLAYBACK_LEVEL", 0, 1, &umr_bitfield_default }, + { "LEVEL_SHIFT", 3, 6, &umr_bitfield_default }, + { "DOWN_MIX_INHIBIT", 7, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "FORMAT_CODE", 3, 6, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA[] = { + { "DESCRIPTOR", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE[] = { + { "MULTICHANNEL01_ENABLE", 0, 0, &umr_bitfield_default }, + { "MULTICHANNEL01_MUTE", 1, 1, &umr_bitfield_default }, + { "MULTICHANNEL01_CHANNEL_ID", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE[] = { + { "MULTICHANNEL23_ENABLE", 0, 0, &umr_bitfield_default }, + { "MULTICHANNEL23_MUTE", 1, 1, &umr_bitfield_default }, + { "MULTICHANNEL23_CHANNEL_ID", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE[] = { + { "MULTICHANNEL45_ENABLE", 0, 0, &umr_bitfield_default }, + { "MULTICHANNEL45_MUTE", 1, 1, &umr_bitfield_default }, + { "MULTICHANNEL45_CHANNEL_ID", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE[] = { + { "MULTICHANNEL67_ENABLE", 0, 0, &umr_bitfield_default }, + { "MULTICHANNEL67_MUTE", 1, 1, &umr_bitfield_default }, + { "MULTICHANNEL67_CHANNEL_ID", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC[] = { + { "VIDEO_LIPSYNC", 0, 7, &umr_bitfield_default }, + { "AUDIO_LIPSYNC", 8, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_HBR[] = { + { "HBR_CAPABLE", 0, 0, &umr_bitfield_default }, + { "HBR_ENABLE", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX[] = { + { "SINK_INFO_INDEX", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA[] = { + { "SINK_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE[] = { + { "MULTICHANNEL1_ENABLE", 0, 0, &umr_bitfield_default }, + { "MULTICHANNEL1_MUTE", 1, 1, &umr_bitfield_default }, + { "MULTICHANNEL1_CHANNEL_ID", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE[] = { + { "MULTICHANNEL3_ENABLE", 0, 0, &umr_bitfield_default }, + { "MULTICHANNEL3_MUTE", 1, 1, &umr_bitfield_default }, + { "MULTICHANNEL3_CHANNEL_ID", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE[] = { + { "MULTICHANNEL5_ENABLE", 0, 0, &umr_bitfield_default }, + { "MULTICHANNEL5_MUTE", 1, 1, &umr_bitfield_default }, + { "MULTICHANNEL5_CHANNEL_ID", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE[] = { + { "MULTICHANNEL7_ENABLE", 0, 0, &umr_bitfield_default }, + { "MULTICHANNEL7_MUTE", 1, 1, &umr_bitfield_default }, + { "MULTICHANNEL7_CHANNEL_ID", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE[] = { + { "MULTICHANNEL_MODE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0[] = { + { "IEC_60958_CS_MODE", 0, 1, &umr_bitfield_default }, + { "IEC_60958_CS_SOURCE_NUMBER", 2, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1[] = { + { "IEC_60958_CS_CLOCK_ACCURACY", 0, 1, &umr_bitfield_default }, + { "IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN", 2, 2, &umr_bitfield_default }, + { "IEC_60958_CS_WORD_LENGTH", 3, 6, &umr_bitfield_default }, + { "IEC_60958_CS_WORD_LENGTH_OVRRD_EN", 7, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2[] = { + { "IEC_60958_CS_SAMPLING_FREQUENCY", 0, 5, &umr_bitfield_default }, + { "IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN", 6, 6, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3[] = { + { "IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY", 0, 3, &umr_bitfield_default }, + { "IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4[] = { + { "IEC_60958_CS_SAMPLING_FREQUENCY_COEFF", 0, 3, &umr_bitfield_default }, + { "IEC_60958_CS_MPEG_SURROUND_INFO", 4, 4, &umr_bitfield_default }, + { "IEC_60958_CS_CGMS_A", 5, 6, &umr_bitfield_default }, + { "IEC_60958_CS_CGMS_A_VALID", 7, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5[] = { + { "IEC_60958_CS_CHANNEL_NUMBER_L", 0, 3, &umr_bitfield_default }, + { "IEC_60958_CS_CHANNEL_NUMBER_R", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6[] = { + { "IEC_60958_CS_CHANNEL_NUMBER_2", 0, 3, &umr_bitfield_default }, + { "IEC_60958_CS_CHANNEL_NUMBER_3", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7[] = { + { "IEC_60958_CS_CHANNEL_NUMBER_4", 0, 3, &umr_bitfield_default }, + { "IEC_60958_CS_CHANNEL_NUMBER_5", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8[] = { + { "IEC_60958_CS_CHANNEL_NUMBER_6", 0, 3, &umr_bitfield_default }, + { "IEC_60958_CS_CHANNEL_NUMBER_7", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO[] = { + { "ASSOCIATION_INFO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS[] = { + { "OUTPUT_ACTIVE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[] = { + { "LPIB_SNAPSHOT_LOCK", 0, 0, &umr_bitfield_default }, + { "CYCLIC_BUFFER_WRAP_COUNT", 8, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB[] = { + { "LPIB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[] = { + { "LPIB_TIMER_SNAPSHOT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE[] = { + { "CODING_TYPE", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED[] = { + { "FORMAT_CHANGED", 0, 0, &umr_bitfield_default }, + { "FORMAT_CHANGED_ACK_UR_ENABLE", 1, 1, &umr_bitfield_default }, + { "FORMAT_CHANGE_REASON", 8, 15, &umr_bitfield_default }, + { "FORMAT_CHANGE_RESPONSE", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION[] = { + { "WIRELESS_DISPLAY_IDENTIFICATION", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE[] = { + { "REMOTE_KEEP_ALIVE_ENABLE", 0, 0, &umr_bitfield_default }, + { "REMOTE_KEEP_ALIVE_CAPABILITY", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = { + { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default }, + { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default }, + { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default }, + { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default }, + { "STRIPE", 5, 5, &umr_bitfield_default }, + { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default }, + { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default }, + { "CONNECTION_LIST", 8, 8, &umr_bitfield_default }, + { "DIGITAL", 9, 9, &umr_bitfield_default }, + { "POWER_CONTROL", 10, 10, &umr_bitfield_default }, + { "LR_SWAP", 11, 11, &umr_bitfield_default }, + { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default }, + { "TYPE", 20, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES[] = { + { "IMPEDANCE_SENSE_CAPABLE", 0, 0, &umr_bitfield_default }, + { "TRIGGER_REQUIRED", 1, 1, &umr_bitfield_default }, + { "JACK_DETECTION_CAPABILITY", 2, 2, &umr_bitfield_default }, + { "HEADPHONE_DRIVE_CAPABLE", 3, 3, &umr_bitfield_default }, + { "OUTPUT_CAPABLE", 4, 4, &umr_bitfield_default }, + { "INPUT_CAPABLE", 5, 5, &umr_bitfield_default }, + { "BALANCED_I_O_PINS", 6, 6, &umr_bitfield_default }, + { "HDMI", 7, 7, &umr_bitfield_default }, + { "VREF_CONTROL", 8, 15, &umr_bitfield_default }, + { "EAPD_CAPABLE", 16, 16, &umr_bitfield_default }, + { "DP", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH[] = { + { "CONNECTION_LIST_LENGTH", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAUDIO_DESCRIPTOR0[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAUDIO_DESCRIPTOR1[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAUDIO_DESCRIPTOR2[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAUDIO_DESCRIPTOR3[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAUDIO_DESCRIPTOR4[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAUDIO_DESCRIPTOR5[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAUDIO_DESCRIPTOR6[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAUDIO_DESCRIPTOR7[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAUDIO_DESCRIPTOR8[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAUDIO_DESCRIPTOR9[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAUDIO_DESCRIPTOR10[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAUDIO_DESCRIPTOR11[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAUDIO_DESCRIPTOR12[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAUDIO_DESCRIPTOR13[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID[] = { + { "MANUFACTURER_ID", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID[] = { + { "PRODUCT_ID", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN[] = { + { "SINK_DESCRIPTION_LEN", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0[] = { + { "PORTID", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1[] = { + { "PORTID", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSINK_DESCRIPTION0[] = { + { "DESCRIPTION", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSINK_DESCRIPTION1[] = { + { "DESCRIPTION", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSINK_DESCRIPTION2[] = { + { "DESCRIPTION", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSINK_DESCRIPTION3[] = { + { "DESCRIPTION", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSINK_DESCRIPTION4[] = { + { "DESCRIPTION", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSINK_DESCRIPTION5[] = { + { "DESCRIPTION", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSINK_DESCRIPTION6[] = { + { "DESCRIPTION", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSINK_DESCRIPTION7[] = { + { "DESCRIPTION", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSINK_DESCRIPTION8[] = { + { "DESCRIPTION", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSINK_DESCRIPTION9[] = { + { "DESCRIPTION", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSINK_DESCRIPTION10[] = { + { "DESCRIPTION", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSINK_DESCRIPTION11[] = { + { "DESCRIPTION", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSINK_DESCRIPTION12[] = { + { "DESCRIPTION", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSINK_DESCRIPTION13[] = { + { "DESCRIPTION", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSINK_DESCRIPTION14[] = { + { "DESCRIPTION", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSINK_DESCRIPTION15[] = { + { "DESCRIPTION", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSINK_DESCRIPTION16[] = { + { "DESCRIPTION", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSINK_DESCRIPTION17[] = { + { "DESCRIPTION", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_INPUT_CRC0_CHANNEL0[] = { + { "INPUT_CRC_CHANNEL0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_INPUT_CRC0_CHANNEL1[] = { + { "INPUT_CRC_CHANNEL1", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_INPUT_CRC0_CHANNEL2[] = { + { "INPUT_CRC_CHANNEL2", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_INPUT_CRC0_CHANNEL3[] = { + { "INPUT_CRC_CHANNEL3", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_INPUT_CRC0_CHANNEL4[] = { + { "INPUT_CRC_CHANNEL4", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_INPUT_CRC0_CHANNEL5[] = { + { "INPUT_CRC_CHANNEL5", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_INPUT_CRC0_CHANNEL6[] = { + { "INPUT_CRC_CHANNEL6", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_INPUT_CRC0_CHANNEL7[] = { + { "INPUT_CRC_CHANNEL7", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_INPUT_CRC1_CHANNEL0[] = { + { "INPUT_CRC_CHANNEL0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_INPUT_CRC1_CHANNEL1[] = { + { "INPUT_CRC_CHANNEL1", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_INPUT_CRC1_CHANNEL2[] = { + { "INPUT_CRC_CHANNEL2", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_INPUT_CRC1_CHANNEL3[] = { + { "INPUT_CRC_CHANNEL3", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_INPUT_CRC1_CHANNEL4[] = { + { "INPUT_CRC_CHANNEL4", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_INPUT_CRC1_CHANNEL5[] = { + { "INPUT_CRC_CHANNEL5", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_INPUT_CRC1_CHANNEL6[] = { + { "INPUT_CRC_CHANNEL6", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_INPUT_CRC1_CHANNEL7[] = { + { "INPUT_CRC_CHANNEL7", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_CRC0_CHANNEL0[] = { + { "CRC_CHANNEL0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_CRC0_CHANNEL1[] = { + { "CRC_CHANNEL1", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_CRC0_CHANNEL2[] = { + { "CRC_CHANNEL2", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_CRC0_CHANNEL3[] = { + { "CRC_CHANNEL3", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_CRC0_CHANNEL4[] = { + { "CRC_CHANNEL4", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_CRC0_CHANNEL5[] = { + { "CRC_CHANNEL5", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_CRC0_CHANNEL6[] = { + { "CRC_CHANNEL6", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_CRC0_CHANNEL7[] = { + { "CRC_CHANNEL7", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_CRC1_CHANNEL0[] = { + { "CRC_CHANNEL0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_CRC1_CHANNEL1[] = { + { "CRC_CHANNEL1", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_CRC1_CHANNEL2[] = { + { "CRC_CHANNEL2", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_CRC1_CHANNEL3[] = { + { "CRC_CHANNEL3", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_CRC1_CHANNEL4[] = { + { "CRC_CHANNEL4", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_CRC1_CHANNEL5[] = { + { "CRC_CHANNEL5", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_CRC1_CHANNEL6[] = { + { "CRC_CHANNEL6", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_CRC1_CHANNEL7[] = { + { "CRC_CHANNEL7", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT[] = { + { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default }, + { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default }, + { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default }, + { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default }, + { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default }, + { "STREAM_TYPE", 15, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID[] = { + { "CHANNEL_ID", 0, 3, &umr_bitfield_default }, + { "STREAM_ID", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER[] = { + { "DIGEN", 0, 0, &umr_bitfield_default }, + { "V", 1, 1, &umr_bitfield_default }, + { "VCFG", 2, 2, &umr_bitfield_default }, + { "PRE", 3, 3, &umr_bitfield_default }, + { "COPY", 4, 4, &umr_bitfield_default }, + { "NON_AUDIO", 5, 5, &umr_bitfield_default }, + { "PRO", 6, 6, &umr_bitfield_default }, + { "L", 7, 7, &umr_bitfield_default }, + { "CC", 8, 14, &umr_bitfield_default }, + { "KEEPALIVE", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = { + { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default }, + { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default }, + { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default }, + { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default }, + { "FORMAT_OVERRIDE", 4, 4, &umr_bitfield_default }, + { "STRIPE", 5, 5, &umr_bitfield_default }, + { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default }, + { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default }, + { "CONNECTION_LIST", 8, 8, &umr_bitfield_default }, + { "DIGITAL", 9, 9, &umr_bitfield_default }, + { "POWER_CONTROL", 10, 10, &umr_bitfield_default }, + { "LR_SWAP", 11, 11, &umr_bitfield_default }, + { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default }, + { "TYPE", 20, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[] = { + { "AUDIO_RATE_CAPABILITIES", 0, 11, &umr_bitfield_default }, + { "AUDIO_BIT_CAPABILITIES", 16, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS[] = { + { "STREAM_FORMATS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL[] = { + { "IN_ENABLE", 5, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE[] = { + { "TAG", 0, 5, &umr_bitfield_default }, + { "ENABLE", 7, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE[] = { + { "IMPEDANCE_SENSE", 0, 30, &umr_bitfield_default }, + { "PRESENCE_DETECT", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[] = { + { "SEQUENCE", 0, 3, &umr_bitfield_default }, + { "DEFAULT_ASSOCIATION", 4, 7, &umr_bitfield_default }, + { "MISC", 8, 11, &umr_bitfield_default }, + { "COLOR", 12, 15, &umr_bitfield_default }, + { "CONNECTION_TYPE", 16, 19, &umr_bitfield_default }, + { "DEFAULT_DEVICE", 20, 23, &umr_bitfield_default }, + { "LOCATION", 24, 29, &umr_bitfield_default }, + { "PORT_CONNECTIVITY", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2[] = { + { "MISC", 0, 3, &umr_bitfield_default }, + { "COLOR", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3[] = { + { "CONNECTION_TYPE", 0, 3, &umr_bitfield_default }, + { "DEFAULT_DEVICE", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4[] = { + { "LOCATION", 0, 5, &umr_bitfield_default }, + { "PORT_CONNECTIVITY", 6, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION[] = { + { "CHANNEL_ALLOCATION", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE[] = { + { "MULTICHANNEL0_ENABLE", 0, 0, &umr_bitfield_default }, + { "MULTICHANNEL0_MUTE", 1, 1, &umr_bitfield_default }, + { "MULTICHANNEL0_CHANNEL_ID", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE[] = { + { "MULTICHANNEL2_ENABLE", 0, 0, &umr_bitfield_default }, + { "MULTICHANNEL2_MUTE", 1, 1, &umr_bitfield_default }, + { "MULTICHANNEL2_CHANNEL_ID", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE[] = { + { "MULTICHANNEL4_ENABLE", 0, 0, &umr_bitfield_default }, + { "MULTICHANNEL4_MUTE", 1, 1, &umr_bitfield_default }, + { "MULTICHANNEL4_CHANNEL_ID", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE[] = { + { "MULTICHANNEL6_ENABLE", 0, 0, &umr_bitfield_default }, + { "MULTICHANNEL6_MUTE", 1, 1, &umr_bitfield_default }, + { "MULTICHANNEL6_CHANNEL_ID", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR[] = { + { "HBR_CAPABLE", 0, 0, &umr_bitfield_default }, + { "HBR_ENABLE", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE[] = { + { "MULTICHANNEL1_ENABLE", 0, 0, &umr_bitfield_default }, + { "MULTICHANNEL1_MUTE", 1, 1, &umr_bitfield_default }, + { "MULTICHANNEL1_CHANNEL_ID", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE[] = { + { "MULTICHANNEL3_ENABLE", 0, 0, &umr_bitfield_default }, + { "MULTICHANNEL3_MUTE", 1, 1, &umr_bitfield_default }, + { "MULTICHANNEL3_CHANNEL_ID", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE[] = { + { "MULTICHANNEL5_ENABLE", 0, 0, &umr_bitfield_default }, + { "MULTICHANNEL5_MUTE", 1, 1, &umr_bitfield_default }, + { "MULTICHANNEL5_CHANNEL_ID", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE[] = { + { "MULTICHANNEL7_ENABLE", 0, 0, &umr_bitfield_default }, + { "MULTICHANNEL7_MUTE", 1, 1, &umr_bitfield_default }, + { "MULTICHANNEL7_CHANNEL_ID", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[] = { + { "LPIB_SNAPSHOT_LOCK", 0, 0, &umr_bitfield_default }, + { "CYCLIC_BUFFER_WRAP_COUNT", 8, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB[] = { + { "LPIB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[] = { + { "LPIB_TIMER_SNAPSHOT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL[] = { + { "INPUT_ACTIVITY", 0, 0, &umr_bitfield_default }, + { "CHANNEL_LAYOUT", 1, 2, &umr_bitfield_default }, + { "INPUT_ACTIVITY_UR_ENABLE", 4, 4, &umr_bitfield_default }, + { "INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE", 5, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME[] = { + { "CHANNEL_COUNT", 0, 2, &umr_bitfield_default }, + { "CHANNEL_ALLOCATION", 8, 15, &umr_bitfield_default }, + { "INFOFRAME_BYTE_5", 16, 23, &umr_bitfield_default }, + { "INFOFRAME_VALID", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L[] = { + { "CHANNEL_STATUS_L", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H[] = { + { "CHANNEL_STATUS_H", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = { + { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default }, + { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default }, + { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default }, + { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default }, + { "STRIPE", 5, 5, &umr_bitfield_default }, + { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default }, + { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default }, + { "CONNECTION_LIST", 8, 8, &umr_bitfield_default }, + { "DIGITAL", 9, 9, &umr_bitfield_default }, + { "POWER_CONTROL", 10, 10, &umr_bitfield_default }, + { "LR_SWAP", 11, 11, &umr_bitfield_default }, + { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default }, + { "TYPE", 20, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES[] = { + { "IMPEDANCE_SENSE_CAPABLE", 0, 0, &umr_bitfield_default }, + { "TRIGGER_REQUIRED", 1, 1, &umr_bitfield_default }, + { "JACK_DETECTION_CAPABILITY", 2, 2, &umr_bitfield_default }, + { "HEADPHONE_DRIVE_CAPABLE", 3, 3, &umr_bitfield_default }, + { "OUTPUT_CAPABLE", 4, 4, &umr_bitfield_default }, + { "INPUT_CAPABLE", 5, 5, &umr_bitfield_default }, + { "BALANCED_I_O_PINS", 6, 6, &umr_bitfield_default }, + { "HDMI", 7, 7, &umr_bitfield_default }, + { "VREF_CONTROL", 8, 15, &umr_bitfield_default }, + { "EAPD_CAPABLE", 16, 16, &umr_bitfield_default }, + { "DP", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID[] = { + { "AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID[] = { + { "AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT[] = { + { "AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE[] = { + { "POWER_STATE_SET", 0, 3, &umr_bitfield_default }, + { "POWER_STATE_ACT", 4, 7, &umr_bitfield_default }, + { "CLKSTOPOK", 9, 9, &umr_bitfield_default }, + { "POWER_STATE_SETTINGS_RESET", 10, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID[] = { + { "SUBSYSTEM_ID_BYTE0", 0, 7, &umr_bitfield_default }, + { "SUBSYSTEM_ID_BYTE1", 8, 15, &umr_bitfield_default }, + { "SUBSYSTEM_ID_BYTE2", 16, 23, &umr_bitfield_default }, + { "SUBSYSTEM_ID_BYTE3", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2[] = { + { "SUBSYSTEM_ID_BYTE1", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3[] = { + { "SUBSYSTEM_ID_BYTE2", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4[] = { + { "SUBSYSTEM_ID_BYTE3", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION[] = { + { "CONVERTER_SYNCHRONIZATION", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET[] = { + { "CODEC_RESET", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT[] = { + { "AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE[] = { + { "AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES[] = { + { "AUDIO_RATE_CAPABILITIES", 0, 11, &umr_bitfield_default }, + { "AUDIO_BIT_CAPABILITIES", 16, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS[] = { + { "AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES[] = { + { "AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES", 0, 29, &umr_bitfield_default }, + { "CLKSTOP", 30, 30, &umr_bitfield_default }, + { "EPSS", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL[] = { + { "MIN_FIFO_SIZE", 0, 6, &umr_bitfield_default }, + { "MAX_FIFO_SIZE", 8, 14, &umr_bitfield_default }, + { "MAX_LATENCY_SUPPORT", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL[] = { + { "AZALIA_LATENCY_COUNTER_RESET", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT[] = { + { "AZALIA_WORSTCASE_LATENCY_COUNT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT[] = { + { "AZALIA_CUMULATIVE_LATENCY_COUNT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT[] = { + { "AZALIA_CUMULATIVE_REQUEST_COUNT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL[] = { + { "MIN_FIFO_SIZE", 0, 6, &umr_bitfield_default }, + { "MAX_FIFO_SIZE", 8, 14, &umr_bitfield_default }, + { "MAX_LATENCY_SUPPORT", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL[] = { + { "AZALIA_LATENCY_COUNTER_RESET", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT[] = { + { "AZALIA_WORSTCASE_LATENCY_COUNT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT[] = { + { "AZALIA_CUMULATIVE_LATENCY_COUNT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT[] = { + { "AZALIA_CUMULATIVE_REQUEST_COUNT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL[] = { + { "MIN_FIFO_SIZE", 0, 6, &umr_bitfield_default }, + { "MAX_FIFO_SIZE", 8, 14, &umr_bitfield_default }, + { "MAX_LATENCY_SUPPORT", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL[] = { + { "AZALIA_LATENCY_COUNTER_RESET", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT[] = { + { "AZALIA_WORSTCASE_LATENCY_COUNT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT[] = { + { "AZALIA_CUMULATIVE_LATENCY_COUNT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT[] = { + { "AZALIA_CUMULATIVE_REQUEST_COUNT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL[] = { + { "MIN_FIFO_SIZE", 0, 6, &umr_bitfield_default }, + { "MAX_FIFO_SIZE", 8, 14, &umr_bitfield_default }, + { "MAX_LATENCY_SUPPORT", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL[] = { + { "AZALIA_LATENCY_COUNTER_RESET", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT[] = { + { "AZALIA_WORSTCASE_LATENCY_COUNT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT[] = { + { "AZALIA_CUMULATIVE_LATENCY_COUNT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT[] = { + { "AZALIA_CUMULATIVE_REQUEST_COUNT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL[] = { + { "MIN_FIFO_SIZE", 0, 6, &umr_bitfield_default }, + { "MAX_FIFO_SIZE", 8, 14, &umr_bitfield_default }, + { "MAX_LATENCY_SUPPORT", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL[] = { + { "AZALIA_LATENCY_COUNTER_RESET", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT[] = { + { "AZALIA_WORSTCASE_LATENCY_COUNT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT[] = { + { "AZALIA_CUMULATIVE_LATENCY_COUNT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT[] = { + { "AZALIA_CUMULATIVE_REQUEST_COUNT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL[] = { + { "MIN_FIFO_SIZE", 0, 6, &umr_bitfield_default }, + { "MAX_FIFO_SIZE", 8, 14, &umr_bitfield_default }, + { "MAX_LATENCY_SUPPORT", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL[] = { + { "AZALIA_LATENCY_COUNTER_RESET", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT[] = { + { "AZALIA_WORSTCASE_LATENCY_COUNT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT[] = { + { "AZALIA_CUMULATIVE_LATENCY_COUNT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT[] = { + { "AZALIA_CUMULATIVE_REQUEST_COUNT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL[] = { + { "MIN_FIFO_SIZE", 0, 6, &umr_bitfield_default }, + { "MAX_FIFO_SIZE", 8, 14, &umr_bitfield_default }, + { "MAX_LATENCY_SUPPORT", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL[] = { + { "AZALIA_LATENCY_COUNTER_RESET", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT[] = { + { "AZALIA_WORSTCASE_LATENCY_COUNT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT[] = { + { "AZALIA_CUMULATIVE_LATENCY_COUNT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT[] = { + { "AZALIA_CUMULATIVE_REQUEST_COUNT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL[] = { + { "MIN_FIFO_SIZE", 0, 6, &umr_bitfield_default }, + { "MAX_FIFO_SIZE", 8, 14, &umr_bitfield_default }, + { "MAX_LATENCY_SUPPORT", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL[] = { + { "AZALIA_LATENCY_COUNTER_RESET", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT[] = { + { "AZALIA_WORSTCASE_LATENCY_COUNT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT[] = { + { "AZALIA_CUMULATIVE_LATENCY_COUNT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT[] = { + { "AZALIA_CUMULATIVE_REQUEST_COUNT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL[] = { + { "MIN_FIFO_SIZE", 0, 6, &umr_bitfield_default }, + { "MAX_FIFO_SIZE", 8, 14, &umr_bitfield_default }, + { "MAX_LATENCY_SUPPORT", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL[] = { + { "AZALIA_LATENCY_COUNTER_RESET", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT[] = { + { "AZALIA_WORSTCASE_LATENCY_COUNT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT[] = { + { "AZALIA_CUMULATIVE_LATENCY_COUNT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT[] = { + { "AZALIA_CUMULATIVE_REQUEST_COUNT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL[] = { + { "MIN_FIFO_SIZE", 0, 6, &umr_bitfield_default }, + { "MAX_FIFO_SIZE", 8, 14, &umr_bitfield_default }, + { "MAX_LATENCY_SUPPORT", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL[] = { + { "AZALIA_LATENCY_COUNTER_RESET", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT[] = { + { "AZALIA_WORSTCASE_LATENCY_COUNT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT[] = { + { "AZALIA_CUMULATIVE_LATENCY_COUNT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT[] = { + { "AZALIA_CUMULATIVE_REQUEST_COUNT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL[] = { + { "MIN_FIFO_SIZE", 0, 6, &umr_bitfield_default }, + { "MAX_FIFO_SIZE", 8, 14, &umr_bitfield_default }, + { "MAX_LATENCY_SUPPORT", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL[] = { + { "AZALIA_LATENCY_COUNTER_RESET", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT[] = { + { "AZALIA_WORSTCASE_LATENCY_COUNT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT[] = { + { "AZALIA_CUMULATIVE_LATENCY_COUNT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT[] = { + { "AZALIA_CUMULATIVE_REQUEST_COUNT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL[] = { + { "MIN_FIFO_SIZE", 0, 6, &umr_bitfield_default }, + { "MAX_FIFO_SIZE", 8, 14, &umr_bitfield_default }, + { "MAX_LATENCY_SUPPORT", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL[] = { + { "AZALIA_LATENCY_COUNTER_RESET", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT[] = { + { "AZALIA_WORSTCASE_LATENCY_COUNT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT[] = { + { "AZALIA_CUMULATIVE_LATENCY_COUNT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT[] = { + { "AZALIA_CUMULATIVE_REQUEST_COUNT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL[] = { + { "MIN_FIFO_SIZE", 0, 6, &umr_bitfield_default }, + { "MAX_FIFO_SIZE", 8, 14, &umr_bitfield_default }, + { "MAX_LATENCY_SUPPORT", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL[] = { + { "AZALIA_LATENCY_COUNTER_RESET", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT[] = { + { "AZALIA_WORSTCASE_LATENCY_COUNT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT[] = { + { "AZALIA_CUMULATIVE_LATENCY_COUNT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT[] = { + { "AZALIA_CUMULATIVE_REQUEST_COUNT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL[] = { + { "MIN_FIFO_SIZE", 0, 6, &umr_bitfield_default }, + { "MAX_FIFO_SIZE", 8, 14, &umr_bitfield_default }, + { "MAX_LATENCY_SUPPORT", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL[] = { + { "AZALIA_LATENCY_COUNTER_RESET", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT[] = { + { "AZALIA_WORSTCASE_LATENCY_COUNT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT[] = { + { "AZALIA_CUMULATIVE_LATENCY_COUNT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT[] = { + { "AZALIA_CUMULATIVE_REQUEST_COUNT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL[] = { + { "MIN_FIFO_SIZE", 0, 6, &umr_bitfield_default }, + { "MAX_FIFO_SIZE", 8, 14, &umr_bitfield_default }, + { "MAX_LATENCY_SUPPORT", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL[] = { + { "AZALIA_LATENCY_COUNTER_RESET", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT[] = { + { "AZALIA_WORSTCASE_LATENCY_COUNT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT[] = { + { "AZALIA_CUMULATIVE_LATENCY_COUNT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT[] = { + { "AZALIA_CUMULATIVE_REQUEST_COUNT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL[] = { + { "MIN_FIFO_SIZE", 0, 6, &umr_bitfield_default }, + { "MAX_FIFO_SIZE", 8, 14, &umr_bitfield_default }, + { "MAX_LATENCY_SUPPORT", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL[] = { + { "AZALIA_LATENCY_COUNTER_RESET", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT[] = { + { "AZALIA_WORSTCASE_LATENCY_COUNT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT[] = { + { "AZALIA_CUMULATIVE_LATENCY_COUNT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT[] = { + { "AZALIA_CUMULATIVE_REQUEST_COUNT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = { + { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default }, + { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default }, + { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default }, + { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default }, + { "FORMAT_OVERRIDE", 4, 4, &umr_bitfield_default }, + { "STRIPE", 5, 5, &umr_bitfield_default }, + { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default }, + { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default }, + { "CONNECTION_LIST", 8, 8, &umr_bitfield_default }, + { "DIGITAL", 9, 9, &umr_bitfield_default }, + { "POWER_CONTROL", 10, 10, &umr_bitfield_default }, + { "LR_SWAP", 11, 11, &umr_bitfield_default }, + { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default }, + { "TYPE", 20, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT[] = { + { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default }, + { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default }, + { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default }, + { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default }, + { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default }, + { "STREAM_TYPE", 15, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID[] = { + { "CHANNEL_ID", 0, 3, &umr_bitfield_default }, + { "STREAM_ID", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER[] = { + { "DIGEN", 0, 0, &umr_bitfield_default }, + { "V", 1, 1, &umr_bitfield_default }, + { "VCFG", 2, 2, &umr_bitfield_default }, + { "PRE", 3, 3, &umr_bitfield_default }, + { "COPY", 4, 4, &umr_bitfield_default }, + { "NON_AUDIO", 5, 5, &umr_bitfield_default }, + { "PRO", 6, 6, &umr_bitfield_default }, + { "L", 7, 7, &umr_bitfield_default }, + { "CC", 8, 14, &umr_bitfield_default }, + { "KEEPALIVE", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS[] = { + { "STREAM_FORMATS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[] = { + { "AUDIO_RATE_CAPABILITIES", 0, 11, &umr_bitfield_default }, + { "AUDIO_BIT_CAPABILITIES", 16, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL[] = { + { "STRIPE_CONTROL", 0, 1, &umr_bitfield_default }, + { "STRIPE_CAPABILITY", 20, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE[] = { + { "RAMP_RATE", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING[] = { + { "PRESENTATION_TIME_EMBEDDING_ENABLE", 0, 0, &umr_bitfield_default }, + { "PRESENTATION_TIME_OFFSET_CHANGED", 1, 1, &umr_bitfield_default }, + { "CLEAR_GTC_COUNTER_MIN_MAX_DELTA", 2, 2, &umr_bitfield_default }, + { "PRESENTATION_TIME_EMBEDDING_GROUP", 4, 6, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA[] = { + { "GTC_COUNTER_DELTA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN[] = { + { "GTC_COUNTER_DELTA_MIN", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX[] = { + { "GTC_COUNTER_DELTA_MAX", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = { + { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default }, + { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default }, + { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default }, + { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default }, + { "STRIPE", 5, 5, &umr_bitfield_default }, + { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default }, + { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default }, + { "CONNECTION_LIST", 8, 8, &umr_bitfield_default }, + { "DIGITAL", 9, 9, &umr_bitfield_default }, + { "POWER_CONTROL", 10, 10, &umr_bitfield_default }, + { "LR_SWAP", 11, 11, &umr_bitfield_default }, + { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default }, + { "TYPE", 20, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES[] = { + { "IMPEDANCE_SENSE_CAPABLE", 0, 0, &umr_bitfield_default }, + { "TRIGGER_REQUIRED", 1, 1, &umr_bitfield_default }, + { "JACK_DETECTION_CAPABILITY", 2, 2, &umr_bitfield_default }, + { "HEADPHONE_DRIVE_CAPABLE", 3, 3, &umr_bitfield_default }, + { "OUTPUT_CAPABLE", 4, 4, &umr_bitfield_default }, + { "INPUT_CAPABLE", 5, 5, &umr_bitfield_default }, + { "BALANCED_I_O_PINS", 6, 6, &umr_bitfield_default }, + { "HDMI", 7, 7, &umr_bitfield_default }, + { "VREF_CONTROL", 8, 15, &umr_bitfield_default }, + { "EAPD_CAPABLE", 16, 16, &umr_bitfield_default }, + { "DP", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE[] = { + { "TAG", 0, 5, &umr_bitfield_default }, + { "ENABLE", 7, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE[] = { + { "IMPEDANCE_SENSE", 0, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL[] = { + { "OUT_ENABLE", 6, 6, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER[] = { + { "SPEAKER_ALLOCATION", 0, 6, &umr_bitfield_default }, + { "CHANNEL_ALLOCATION", 8, 15, &umr_bitfield_default }, + { "HDMI_CONNECTION", 16, 16, &umr_bitfield_default }, + { "DP_CONNECTION", 17, 17, &umr_bitfield_default }, + { "EXTRA_CONNECTION_INFO", 18, 23, &umr_bitfield_default }, + { "LFE_PLAYBACK_LEVEL", 24, 25, &umr_bitfield_default }, + { "LEVEL_SHIFT", 27, 30, &umr_bitfield_default }, + { "DOWN_MIX_INHIBIT", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE[] = { + { "MULTICHANNEL01_ENABLE", 0, 0, &umr_bitfield_default }, + { "MULTICHANNEL01_MUTE", 1, 1, &umr_bitfield_default }, + { "MULTICHANNEL01_CHANNEL_ID", 4, 7, &umr_bitfield_default }, + { "MULTICHANNEL23_ENABLE", 8, 8, &umr_bitfield_default }, + { "MULTICHANNEL23_MUTE", 9, 9, &umr_bitfield_default }, + { "MULTICHANNEL23_CHANNEL_ID", 12, 15, &umr_bitfield_default }, + { "MULTICHANNEL45_ENABLE", 16, 16, &umr_bitfield_default }, + { "MULTICHANNEL45_MUTE", 17, 17, &umr_bitfield_default }, + { "MULTICHANNEL45_CHANNEL_ID", 20, 23, &umr_bitfield_default }, + { "MULTICHANNEL67_ENABLE", 24, 24, &umr_bitfield_default }, + { "MULTICHANNEL67_MUTE", 25, 25, &umr_bitfield_default }, + { "MULTICHANNEL67_CHANNEL_ID", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC[] = { + { "VIDEO_LIPSYNC", 0, 7, &umr_bitfield_default }, + { "AUDIO_LIPSYNC", 8, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR[] = { + { "HBR_CAPABLE", 0, 0, &umr_bitfield_default }, + { "HBR_ENABLE", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0[] = { + { "MANUFACTURER_ID", 0, 15, &umr_bitfield_default }, + { "PRODUCT_ID", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1[] = { + { "SINK_DESCRIPTION_LEN", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2[] = { + { "PORT_ID0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3[] = { + { "PORT_ID1", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4[] = { + { "DESCRIPTION0", 0, 7, &umr_bitfield_default }, + { "DESCRIPTION1", 8, 15, &umr_bitfield_default }, + { "DESCRIPTION2", 16, 23, &umr_bitfield_default }, + { "DESCRIPTION3", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5[] = { + { "DESCRIPTION4", 0, 7, &umr_bitfield_default }, + { "DESCRIPTION5", 8, 15, &umr_bitfield_default }, + { "DESCRIPTION6", 16, 23, &umr_bitfield_default }, + { "DESCRIPTION7", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6[] = { + { "DESCRIPTION8", 0, 7, &umr_bitfield_default }, + { "DESCRIPTION9", 8, 15, &umr_bitfield_default }, + { "DESCRIPTION10", 16, 23, &umr_bitfield_default }, + { "DESCRIPTION11", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7[] = { + { "DESCRIPTION12", 0, 7, &umr_bitfield_default }, + { "DESCRIPTION13", 8, 15, &umr_bitfield_default }, + { "DESCRIPTION14", 16, 23, &umr_bitfield_default }, + { "DESCRIPTION15", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8[] = { + { "DESCRIPTION16", 0, 7, &umr_bitfield_default }, + { "DESCRIPTION17", 8, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL[] = { + { "CLOCK_GATING_DISABLE", 0, 0, &umr_bitfield_default }, + { "CLOCK_ON_STATE", 4, 4, &umr_bitfield_default }, + { "AUDIO_ENABLED", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[] = { + { "UNSOLICITED_RESPONSE_PAYLOAD", 0, 25, &umr_bitfield_default }, + { "UNSOLICITED_RESPONSE_FORCE", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[] = { + { "SEQUENCE", 0, 3, &umr_bitfield_default }, + { "DEFAULT_ASSOCIATION", 4, 7, &umr_bitfield_default }, + { "MISC", 8, 11, &umr_bitfield_default }, + { "COLOR", 12, 15, &umr_bitfield_default }, + { "CONNECTION_TYPE", 16, 19, &umr_bitfield_default }, + { "DEFAULT_DEVICE", 20, 23, &umr_bitfield_default }, + { "LOCATION", 24, 29, &umr_bitfield_default }, + { "PORT_CONNECTIVITY", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2[] = { + { "MULTICHANNEL1_ENABLE", 0, 0, &umr_bitfield_default }, + { "MULTICHANNEL1_MUTE", 1, 1, &umr_bitfield_default }, + { "MULTICHANNEL1_CHANNEL_ID", 4, 7, &umr_bitfield_default }, + { "MULTICHANNEL3_ENABLE", 8, 8, &umr_bitfield_default }, + { "MULTICHANNEL3_MUTE", 9, 9, &umr_bitfield_default }, + { "MULTICHANNEL3_CHANNEL_ID", 12, 15, &umr_bitfield_default }, + { "MULTICHANNEL5_ENABLE", 16, 16, &umr_bitfield_default }, + { "MULTICHANNEL5_MUTE", 17, 17, &umr_bitfield_default }, + { "MULTICHANNEL5_CHANNEL_ID", 20, 23, &umr_bitfield_default }, + { "MULTICHANNEL7_ENABLE", 24, 24, &umr_bitfield_default }, + { "MULTICHANNEL7_MUTE", 25, 25, &umr_bitfield_default }, + { "MULTICHANNEL7_CHANNEL_ID", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE[] = { + { "MULTICHANNEL_MODE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0[] = { + { "IEC_60958_CS_MODE", 0, 1, &umr_bitfield_default }, + { "IEC_60958_CS_SOURCE_NUMBER", 2, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1[] = { + { "IEC_60958_CS_CLOCK_ACCURACY", 0, 1, &umr_bitfield_default }, + { "IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN", 2, 2, &umr_bitfield_default }, + { "IEC_60958_CS_WORD_LENGTH", 3, 6, &umr_bitfield_default }, + { "IEC_60958_CS_WORD_LENGTH_OVRRD_EN", 7, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2[] = { + { "IEC_60958_CS_SAMPLING_FREQUENCY", 0, 5, &umr_bitfield_default }, + { "IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN", 6, 6, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3[] = { + { "IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY", 0, 3, &umr_bitfield_default }, + { "IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4[] = { + { "IEC_60958_CS_SAMPLING_FREQUENCY_COEFF", 0, 3, &umr_bitfield_default }, + { "IEC_60958_CS_MPEG_SURROUND_INFO", 4, 4, &umr_bitfield_default }, + { "IEC_60958_CS_CGMS_A", 5, 6, &umr_bitfield_default }, + { "IEC_60958_CS_CGMS_A_VALID", 7, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5[] = { + { "IEC_60958_CS_CHANNEL_NUMBER_L", 0, 3, &umr_bitfield_default }, + { "IEC_60958_CS_CHANNEL_NUMBER_R", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6[] = { + { "IEC_60958_CS_CHANNEL_NUMBER_2", 0, 3, &umr_bitfield_default }, + { "IEC_60958_CS_CHANNEL_NUMBER_3", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7[] = { + { "IEC_60958_CS_CHANNEL_NUMBER_4", 0, 3, &umr_bitfield_default }, + { "IEC_60958_CS_CHANNEL_NUMBER_5", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8[] = { + { "IEC_60958_CS_CHANNEL_NUMBER_6", 0, 3, &umr_bitfield_default }, + { "IEC_60958_CS_CHANNEL_NUMBER_7", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO[] = { + { "ASSOCIATION_INFO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS[] = { + { "OUTPUT_ACTIVE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[] = { + { "LPIB_SNAPSHOT_LOCK", 0, 0, &umr_bitfield_default }, + { "CYCLIC_BUFFER_WRAP_COUNT", 8, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB[] = { + { "LPIB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[] = { + { "LPIB_TIMER_SNAPSHOT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE[] = { + { "CODING_TYPE", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED[] = { + { "FORMAT_CHANGED", 0, 0, &umr_bitfield_default }, + { "FORMAT_CHANGED_ACK_UR_ENABLE", 1, 1, &umr_bitfield_default }, + { "FORMAT_CHANGE_REASON", 8, 15, &umr_bitfield_default }, + { "FORMAT_CHANGE_RESPONSE", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION[] = { + { "WIRELESS_DISPLAY_IDENTIFICATION", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE[] = { + { "REMOTE_KEEP_ALIVE_ENABLE", 0, 0, &umr_bitfield_default }, + { "REMOTE_KEEP_ALIVE_CAPABILITY", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS[] = { + { "AUDIO_ENABLE_STATUS", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS[] = { + { "AUDIO_ENABLED_FLAG", 0, 0, &umr_bitfield_default }, + { "AUDIO_ENABLED_MASK", 4, 4, &umr_bitfield_default }, + { "AUDIO_ENABLED_TYPE", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS[] = { + { "AUDIO_DISABLED_FLAG", 0, 0, &umr_bitfield_default }, + { "AUDIO_DISABLED_MASK", 4, 4, &umr_bitfield_default }, + { "AUDIO_DISABLED_TYPE", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS[] = { + { "AUDIO_FORMAT_CHANGED_FLAG", 0, 0, &umr_bitfield_default }, + { "AUDIO_FORMAT_CHANGED_MASK", 4, 4, &umr_bitfield_default }, + { "AUDIO_FORMAT_CHANGED_TYPE", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = { + { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default }, + { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default }, + { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default }, + { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default }, + { "FORMAT_OVERRIDE", 4, 4, &umr_bitfield_default }, + { "STRIPE", 5, 5, &umr_bitfield_default }, + { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default }, + { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default }, + { "CONNECTION_LIST", 8, 8, &umr_bitfield_default }, + { "DIGITAL", 9, 9, &umr_bitfield_default }, + { "POWER_CONTROL", 10, 10, &umr_bitfield_default }, + { "LR_SWAP", 11, 11, &umr_bitfield_default }, + { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default }, + { "TYPE", 20, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT[] = { + { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default }, + { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default }, + { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default }, + { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default }, + { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default }, + { "STREAM_TYPE", 15, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID[] = { + { "CHANNEL_ID", 0, 3, &umr_bitfield_default }, + { "STREAM_ID", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER[] = { + { "DIGEN", 0, 0, &umr_bitfield_default }, + { "V", 1, 1, &umr_bitfield_default }, + { "VCFG", 2, 2, &umr_bitfield_default }, + { "PRE", 3, 3, &umr_bitfield_default }, + { "COPY", 4, 4, &umr_bitfield_default }, + { "NON_AUDIO", 5, 5, &umr_bitfield_default }, + { "PRO", 6, 6, &umr_bitfield_default }, + { "L", 7, 7, &umr_bitfield_default }, + { "CC", 8, 14, &umr_bitfield_default }, + { "KEEPALIVE", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS[] = { + { "STREAM_FORMATS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[] = { + { "AUDIO_RATE_CAPABILITIES", 0, 11, &umr_bitfield_default }, + { "AUDIO_BIT_CAPABILITIES", 16, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL[] = { + { "STRIPE_CONTROL", 0, 1, &umr_bitfield_default }, + { "STRIPE_CAPABILITY", 20, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE[] = { + { "RAMP_RATE", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING[] = { + { "PRESENTATION_TIME_EMBEDDING_ENABLE", 0, 0, &umr_bitfield_default }, + { "PRESENTATION_TIME_OFFSET_CHANGED", 1, 1, &umr_bitfield_default }, + { "CLEAR_GTC_COUNTER_MIN_MAX_DELTA", 2, 2, &umr_bitfield_default }, + { "PRESENTATION_TIME_EMBEDDING_GROUP", 4, 6, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA[] = { + { "GTC_COUNTER_DELTA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN[] = { + { "GTC_COUNTER_DELTA_MIN", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX[] = { + { "GTC_COUNTER_DELTA_MAX", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = { + { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default }, + { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default }, + { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default }, + { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default }, + { "STRIPE", 5, 5, &umr_bitfield_default }, + { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default }, + { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default }, + { "CONNECTION_LIST", 8, 8, &umr_bitfield_default }, + { "DIGITAL", 9, 9, &umr_bitfield_default }, + { "POWER_CONTROL", 10, 10, &umr_bitfield_default }, + { "LR_SWAP", 11, 11, &umr_bitfield_default }, + { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default }, + { "TYPE", 20, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES[] = { + { "IMPEDANCE_SENSE_CAPABLE", 0, 0, &umr_bitfield_default }, + { "TRIGGER_REQUIRED", 1, 1, &umr_bitfield_default }, + { "JACK_DETECTION_CAPABILITY", 2, 2, &umr_bitfield_default }, + { "HEADPHONE_DRIVE_CAPABLE", 3, 3, &umr_bitfield_default }, + { "OUTPUT_CAPABLE", 4, 4, &umr_bitfield_default }, + { "INPUT_CAPABLE", 5, 5, &umr_bitfield_default }, + { "BALANCED_I_O_PINS", 6, 6, &umr_bitfield_default }, + { "HDMI", 7, 7, &umr_bitfield_default }, + { "VREF_CONTROL", 8, 15, &umr_bitfield_default }, + { "EAPD_CAPABLE", 16, 16, &umr_bitfield_default }, + { "DP", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE[] = { + { "TAG", 0, 5, &umr_bitfield_default }, + { "ENABLE", 7, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE[] = { + { "IMPEDANCE_SENSE", 0, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL[] = { + { "OUT_ENABLE", 6, 6, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER[] = { + { "SPEAKER_ALLOCATION", 0, 6, &umr_bitfield_default }, + { "CHANNEL_ALLOCATION", 8, 15, &umr_bitfield_default }, + { "HDMI_CONNECTION", 16, 16, &umr_bitfield_default }, + { "DP_CONNECTION", 17, 17, &umr_bitfield_default }, + { "EXTRA_CONNECTION_INFO", 18, 23, &umr_bitfield_default }, + { "LFE_PLAYBACK_LEVEL", 24, 25, &umr_bitfield_default }, + { "LEVEL_SHIFT", 27, 30, &umr_bitfield_default }, + { "DOWN_MIX_INHIBIT", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE[] = { + { "MULTICHANNEL01_ENABLE", 0, 0, &umr_bitfield_default }, + { "MULTICHANNEL01_MUTE", 1, 1, &umr_bitfield_default }, + { "MULTICHANNEL01_CHANNEL_ID", 4, 7, &umr_bitfield_default }, + { "MULTICHANNEL23_ENABLE", 8, 8, &umr_bitfield_default }, + { "MULTICHANNEL23_MUTE", 9, 9, &umr_bitfield_default }, + { "MULTICHANNEL23_CHANNEL_ID", 12, 15, &umr_bitfield_default }, + { "MULTICHANNEL45_ENABLE", 16, 16, &umr_bitfield_default }, + { "MULTICHANNEL45_MUTE", 17, 17, &umr_bitfield_default }, + { "MULTICHANNEL45_CHANNEL_ID", 20, 23, &umr_bitfield_default }, + { "MULTICHANNEL67_ENABLE", 24, 24, &umr_bitfield_default }, + { "MULTICHANNEL67_MUTE", 25, 25, &umr_bitfield_default }, + { "MULTICHANNEL67_CHANNEL_ID", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC[] = { + { "VIDEO_LIPSYNC", 0, 7, &umr_bitfield_default }, + { "AUDIO_LIPSYNC", 8, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR[] = { + { "HBR_CAPABLE", 0, 0, &umr_bitfield_default }, + { "HBR_ENABLE", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0[] = { + { "MANUFACTURER_ID", 0, 15, &umr_bitfield_default }, + { "PRODUCT_ID", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1[] = { + { "SINK_DESCRIPTION_LEN", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2[] = { + { "PORT_ID0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3[] = { + { "PORT_ID1", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4[] = { + { "DESCRIPTION0", 0, 7, &umr_bitfield_default }, + { "DESCRIPTION1", 8, 15, &umr_bitfield_default }, + { "DESCRIPTION2", 16, 23, &umr_bitfield_default }, + { "DESCRIPTION3", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5[] = { + { "DESCRIPTION4", 0, 7, &umr_bitfield_default }, + { "DESCRIPTION5", 8, 15, &umr_bitfield_default }, + { "DESCRIPTION6", 16, 23, &umr_bitfield_default }, + { "DESCRIPTION7", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6[] = { + { "DESCRIPTION8", 0, 7, &umr_bitfield_default }, + { "DESCRIPTION9", 8, 15, &umr_bitfield_default }, + { "DESCRIPTION10", 16, 23, &umr_bitfield_default }, + { "DESCRIPTION11", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7[] = { + { "DESCRIPTION12", 0, 7, &umr_bitfield_default }, + { "DESCRIPTION13", 8, 15, &umr_bitfield_default }, + { "DESCRIPTION14", 16, 23, &umr_bitfield_default }, + { "DESCRIPTION15", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8[] = { + { "DESCRIPTION16", 0, 7, &umr_bitfield_default }, + { "DESCRIPTION17", 8, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL[] = { + { "CLOCK_GATING_DISABLE", 0, 0, &umr_bitfield_default }, + { "CLOCK_ON_STATE", 4, 4, &umr_bitfield_default }, + { "AUDIO_ENABLED", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[] = { + { "UNSOLICITED_RESPONSE_PAYLOAD", 0, 25, &umr_bitfield_default }, + { "UNSOLICITED_RESPONSE_FORCE", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[] = { + { "SEQUENCE", 0, 3, &umr_bitfield_default }, + { "DEFAULT_ASSOCIATION", 4, 7, &umr_bitfield_default }, + { "MISC", 8, 11, &umr_bitfield_default }, + { "COLOR", 12, 15, &umr_bitfield_default }, + { "CONNECTION_TYPE", 16, 19, &umr_bitfield_default }, + { "DEFAULT_DEVICE", 20, 23, &umr_bitfield_default }, + { "LOCATION", 24, 29, &umr_bitfield_default }, + { "PORT_CONNECTIVITY", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2[] = { + { "MULTICHANNEL1_ENABLE", 0, 0, &umr_bitfield_default }, + { "MULTICHANNEL1_MUTE", 1, 1, &umr_bitfield_default }, + { "MULTICHANNEL1_CHANNEL_ID", 4, 7, &umr_bitfield_default }, + { "MULTICHANNEL3_ENABLE", 8, 8, &umr_bitfield_default }, + { "MULTICHANNEL3_MUTE", 9, 9, &umr_bitfield_default }, + { "MULTICHANNEL3_CHANNEL_ID", 12, 15, &umr_bitfield_default }, + { "MULTICHANNEL5_ENABLE", 16, 16, &umr_bitfield_default }, + { "MULTICHANNEL5_MUTE", 17, 17, &umr_bitfield_default }, + { "MULTICHANNEL5_CHANNEL_ID", 20, 23, &umr_bitfield_default }, + { "MULTICHANNEL7_ENABLE", 24, 24, &umr_bitfield_default }, + { "MULTICHANNEL7_MUTE", 25, 25, &umr_bitfield_default }, + { "MULTICHANNEL7_CHANNEL_ID", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE[] = { + { "MULTICHANNEL_MODE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0[] = { + { "IEC_60958_CS_MODE", 0, 1, &umr_bitfield_default }, + { "IEC_60958_CS_SOURCE_NUMBER", 2, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1[] = { + { "IEC_60958_CS_CLOCK_ACCURACY", 0, 1, &umr_bitfield_default }, + { "IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN", 2, 2, &umr_bitfield_default }, + { "IEC_60958_CS_WORD_LENGTH", 3, 6, &umr_bitfield_default }, + { "IEC_60958_CS_WORD_LENGTH_OVRRD_EN", 7, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2[] = { + { "IEC_60958_CS_SAMPLING_FREQUENCY", 0, 5, &umr_bitfield_default }, + { "IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN", 6, 6, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3[] = { + { "IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY", 0, 3, &umr_bitfield_default }, + { "IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4[] = { + { "IEC_60958_CS_SAMPLING_FREQUENCY_COEFF", 0, 3, &umr_bitfield_default }, + { "IEC_60958_CS_MPEG_SURROUND_INFO", 4, 4, &umr_bitfield_default }, + { "IEC_60958_CS_CGMS_A", 5, 6, &umr_bitfield_default }, + { "IEC_60958_CS_CGMS_A_VALID", 7, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5[] = { + { "IEC_60958_CS_CHANNEL_NUMBER_L", 0, 3, &umr_bitfield_default }, + { "IEC_60958_CS_CHANNEL_NUMBER_R", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6[] = { + { "IEC_60958_CS_CHANNEL_NUMBER_2", 0, 3, &umr_bitfield_default }, + { "IEC_60958_CS_CHANNEL_NUMBER_3", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7[] = { + { "IEC_60958_CS_CHANNEL_NUMBER_4", 0, 3, &umr_bitfield_default }, + { "IEC_60958_CS_CHANNEL_NUMBER_5", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8[] = { + { "IEC_60958_CS_CHANNEL_NUMBER_6", 0, 3, &umr_bitfield_default }, + { "IEC_60958_CS_CHANNEL_NUMBER_7", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO[] = { + { "ASSOCIATION_INFO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS[] = { + { "OUTPUT_ACTIVE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[] = { + { "LPIB_SNAPSHOT_LOCK", 0, 0, &umr_bitfield_default }, + { "CYCLIC_BUFFER_WRAP_COUNT", 8, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB[] = { + { "LPIB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[] = { + { "LPIB_TIMER_SNAPSHOT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE[] = { + { "CODING_TYPE", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED[] = { + { "FORMAT_CHANGED", 0, 0, &umr_bitfield_default }, + { "FORMAT_CHANGED_ACK_UR_ENABLE", 1, 1, &umr_bitfield_default }, + { "FORMAT_CHANGE_REASON", 8, 15, &umr_bitfield_default }, + { "FORMAT_CHANGE_RESPONSE", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION[] = { + { "WIRELESS_DISPLAY_IDENTIFICATION", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE[] = { + { "REMOTE_KEEP_ALIVE_ENABLE", 0, 0, &umr_bitfield_default }, + { "REMOTE_KEEP_ALIVE_CAPABILITY", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS[] = { + { "AUDIO_ENABLE_STATUS", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS[] = { + { "AUDIO_ENABLED_FLAG", 0, 0, &umr_bitfield_default }, + { "AUDIO_ENABLED_MASK", 4, 4, &umr_bitfield_default }, + { "AUDIO_ENABLED_TYPE", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS[] = { + { "AUDIO_DISABLED_FLAG", 0, 0, &umr_bitfield_default }, + { "AUDIO_DISABLED_MASK", 4, 4, &umr_bitfield_default }, + { "AUDIO_DISABLED_TYPE", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS[] = { + { "AUDIO_FORMAT_CHANGED_FLAG", 0, 0, &umr_bitfield_default }, + { "AUDIO_FORMAT_CHANGED_MASK", 4, 4, &umr_bitfield_default }, + { "AUDIO_FORMAT_CHANGED_TYPE", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = { + { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default }, + { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default }, + { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default }, + { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default }, + { "FORMAT_OVERRIDE", 4, 4, &umr_bitfield_default }, + { "STRIPE", 5, 5, &umr_bitfield_default }, + { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default }, + { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default }, + { "CONNECTION_LIST", 8, 8, &umr_bitfield_default }, + { "DIGITAL", 9, 9, &umr_bitfield_default }, + { "POWER_CONTROL", 10, 10, &umr_bitfield_default }, + { "LR_SWAP", 11, 11, &umr_bitfield_default }, + { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default }, + { "TYPE", 20, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT[] = { + { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default }, + { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default }, + { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default }, + { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default }, + { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default }, + { "STREAM_TYPE", 15, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID[] = { + { "CHANNEL_ID", 0, 3, &umr_bitfield_default }, + { "STREAM_ID", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER[] = { + { "DIGEN", 0, 0, &umr_bitfield_default }, + { "V", 1, 1, &umr_bitfield_default }, + { "VCFG", 2, 2, &umr_bitfield_default }, + { "PRE", 3, 3, &umr_bitfield_default }, + { "COPY", 4, 4, &umr_bitfield_default }, + { "NON_AUDIO", 5, 5, &umr_bitfield_default }, + { "PRO", 6, 6, &umr_bitfield_default }, + { "L", 7, 7, &umr_bitfield_default }, + { "CC", 8, 14, &umr_bitfield_default }, + { "KEEPALIVE", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS[] = { + { "STREAM_FORMATS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[] = { + { "AUDIO_RATE_CAPABILITIES", 0, 11, &umr_bitfield_default }, + { "AUDIO_BIT_CAPABILITIES", 16, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL[] = { + { "STRIPE_CONTROL", 0, 1, &umr_bitfield_default }, + { "STRIPE_CAPABILITY", 20, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE[] = { + { "RAMP_RATE", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING[] = { + { "PRESENTATION_TIME_EMBEDDING_ENABLE", 0, 0, &umr_bitfield_default }, + { "PRESENTATION_TIME_OFFSET_CHANGED", 1, 1, &umr_bitfield_default }, + { "CLEAR_GTC_COUNTER_MIN_MAX_DELTA", 2, 2, &umr_bitfield_default }, + { "PRESENTATION_TIME_EMBEDDING_GROUP", 4, 6, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA[] = { + { "GTC_COUNTER_DELTA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN[] = { + { "GTC_COUNTER_DELTA_MIN", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX[] = { + { "GTC_COUNTER_DELTA_MAX", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = { + { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default }, + { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default }, + { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default }, + { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default }, + { "STRIPE", 5, 5, &umr_bitfield_default }, + { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default }, + { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default }, + { "CONNECTION_LIST", 8, 8, &umr_bitfield_default }, + { "DIGITAL", 9, 9, &umr_bitfield_default }, + { "POWER_CONTROL", 10, 10, &umr_bitfield_default }, + { "LR_SWAP", 11, 11, &umr_bitfield_default }, + { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default }, + { "TYPE", 20, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES[] = { + { "IMPEDANCE_SENSE_CAPABLE", 0, 0, &umr_bitfield_default }, + { "TRIGGER_REQUIRED", 1, 1, &umr_bitfield_default }, + { "JACK_DETECTION_CAPABILITY", 2, 2, &umr_bitfield_default }, + { "HEADPHONE_DRIVE_CAPABLE", 3, 3, &umr_bitfield_default }, + { "OUTPUT_CAPABLE", 4, 4, &umr_bitfield_default }, + { "INPUT_CAPABLE", 5, 5, &umr_bitfield_default }, + { "BALANCED_I_O_PINS", 6, 6, &umr_bitfield_default }, + { "HDMI", 7, 7, &umr_bitfield_default }, + { "VREF_CONTROL", 8, 15, &umr_bitfield_default }, + { "EAPD_CAPABLE", 16, 16, &umr_bitfield_default }, + { "DP", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE[] = { + { "TAG", 0, 5, &umr_bitfield_default }, + { "ENABLE", 7, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE[] = { + { "IMPEDANCE_SENSE", 0, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL[] = { + { "OUT_ENABLE", 6, 6, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER[] = { + { "SPEAKER_ALLOCATION", 0, 6, &umr_bitfield_default }, + { "CHANNEL_ALLOCATION", 8, 15, &umr_bitfield_default }, + { "HDMI_CONNECTION", 16, 16, &umr_bitfield_default }, + { "DP_CONNECTION", 17, 17, &umr_bitfield_default }, + { "EXTRA_CONNECTION_INFO", 18, 23, &umr_bitfield_default }, + { "LFE_PLAYBACK_LEVEL", 24, 25, &umr_bitfield_default }, + { "LEVEL_SHIFT", 27, 30, &umr_bitfield_default }, + { "DOWN_MIX_INHIBIT", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE[] = { + { "MULTICHANNEL01_ENABLE", 0, 0, &umr_bitfield_default }, + { "MULTICHANNEL01_MUTE", 1, 1, &umr_bitfield_default }, + { "MULTICHANNEL01_CHANNEL_ID", 4, 7, &umr_bitfield_default }, + { "MULTICHANNEL23_ENABLE", 8, 8, &umr_bitfield_default }, + { "MULTICHANNEL23_MUTE", 9, 9, &umr_bitfield_default }, + { "MULTICHANNEL23_CHANNEL_ID", 12, 15, &umr_bitfield_default }, + { "MULTICHANNEL45_ENABLE", 16, 16, &umr_bitfield_default }, + { "MULTICHANNEL45_MUTE", 17, 17, &umr_bitfield_default }, + { "MULTICHANNEL45_CHANNEL_ID", 20, 23, &umr_bitfield_default }, + { "MULTICHANNEL67_ENABLE", 24, 24, &umr_bitfield_default }, + { "MULTICHANNEL67_MUTE", 25, 25, &umr_bitfield_default }, + { "MULTICHANNEL67_CHANNEL_ID", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC[] = { + { "VIDEO_LIPSYNC", 0, 7, &umr_bitfield_default }, + { "AUDIO_LIPSYNC", 8, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR[] = { + { "HBR_CAPABLE", 0, 0, &umr_bitfield_default }, + { "HBR_ENABLE", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0[] = { + { "MANUFACTURER_ID", 0, 15, &umr_bitfield_default }, + { "PRODUCT_ID", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1[] = { + { "SINK_DESCRIPTION_LEN", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2[] = { + { "PORT_ID0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3[] = { + { "PORT_ID1", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4[] = { + { "DESCRIPTION0", 0, 7, &umr_bitfield_default }, + { "DESCRIPTION1", 8, 15, &umr_bitfield_default }, + { "DESCRIPTION2", 16, 23, &umr_bitfield_default }, + { "DESCRIPTION3", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5[] = { + { "DESCRIPTION4", 0, 7, &umr_bitfield_default }, + { "DESCRIPTION5", 8, 15, &umr_bitfield_default }, + { "DESCRIPTION6", 16, 23, &umr_bitfield_default }, + { "DESCRIPTION7", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6[] = { + { "DESCRIPTION8", 0, 7, &umr_bitfield_default }, + { "DESCRIPTION9", 8, 15, &umr_bitfield_default }, + { "DESCRIPTION10", 16, 23, &umr_bitfield_default }, + { "DESCRIPTION11", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7[] = { + { "DESCRIPTION12", 0, 7, &umr_bitfield_default }, + { "DESCRIPTION13", 8, 15, &umr_bitfield_default }, + { "DESCRIPTION14", 16, 23, &umr_bitfield_default }, + { "DESCRIPTION15", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8[] = { + { "DESCRIPTION16", 0, 7, &umr_bitfield_default }, + { "DESCRIPTION17", 8, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL[] = { + { "CLOCK_GATING_DISABLE", 0, 0, &umr_bitfield_default }, + { "CLOCK_ON_STATE", 4, 4, &umr_bitfield_default }, + { "AUDIO_ENABLED", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[] = { + { "UNSOLICITED_RESPONSE_PAYLOAD", 0, 25, &umr_bitfield_default }, + { "UNSOLICITED_RESPONSE_FORCE", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[] = { + { "SEQUENCE", 0, 3, &umr_bitfield_default }, + { "DEFAULT_ASSOCIATION", 4, 7, &umr_bitfield_default }, + { "MISC", 8, 11, &umr_bitfield_default }, + { "COLOR", 12, 15, &umr_bitfield_default }, + { "CONNECTION_TYPE", 16, 19, &umr_bitfield_default }, + { "DEFAULT_DEVICE", 20, 23, &umr_bitfield_default }, + { "LOCATION", 24, 29, &umr_bitfield_default }, + { "PORT_CONNECTIVITY", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2[] = { + { "MULTICHANNEL1_ENABLE", 0, 0, &umr_bitfield_default }, + { "MULTICHANNEL1_MUTE", 1, 1, &umr_bitfield_default }, + { "MULTICHANNEL1_CHANNEL_ID", 4, 7, &umr_bitfield_default }, + { "MULTICHANNEL3_ENABLE", 8, 8, &umr_bitfield_default }, + { "MULTICHANNEL3_MUTE", 9, 9, &umr_bitfield_default }, + { "MULTICHANNEL3_CHANNEL_ID", 12, 15, &umr_bitfield_default }, + { "MULTICHANNEL5_ENABLE", 16, 16, &umr_bitfield_default }, + { "MULTICHANNEL5_MUTE", 17, 17, &umr_bitfield_default }, + { "MULTICHANNEL5_CHANNEL_ID", 20, 23, &umr_bitfield_default }, + { "MULTICHANNEL7_ENABLE", 24, 24, &umr_bitfield_default }, + { "MULTICHANNEL7_MUTE", 25, 25, &umr_bitfield_default }, + { "MULTICHANNEL7_CHANNEL_ID", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE[] = { + { "MULTICHANNEL_MODE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0[] = { + { "IEC_60958_CS_MODE", 0, 1, &umr_bitfield_default }, + { "IEC_60958_CS_SOURCE_NUMBER", 2, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1[] = { + { "IEC_60958_CS_CLOCK_ACCURACY", 0, 1, &umr_bitfield_default }, + { "IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN", 2, 2, &umr_bitfield_default }, + { "IEC_60958_CS_WORD_LENGTH", 3, 6, &umr_bitfield_default }, + { "IEC_60958_CS_WORD_LENGTH_OVRRD_EN", 7, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2[] = { + { "IEC_60958_CS_SAMPLING_FREQUENCY", 0, 5, &umr_bitfield_default }, + { "IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN", 6, 6, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3[] = { + { "IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY", 0, 3, &umr_bitfield_default }, + { "IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4[] = { + { "IEC_60958_CS_SAMPLING_FREQUENCY_COEFF", 0, 3, &umr_bitfield_default }, + { "IEC_60958_CS_MPEG_SURROUND_INFO", 4, 4, &umr_bitfield_default }, + { "IEC_60958_CS_CGMS_A", 5, 6, &umr_bitfield_default }, + { "IEC_60958_CS_CGMS_A_VALID", 7, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5[] = { + { "IEC_60958_CS_CHANNEL_NUMBER_L", 0, 3, &umr_bitfield_default }, + { "IEC_60958_CS_CHANNEL_NUMBER_R", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6[] = { + { "IEC_60958_CS_CHANNEL_NUMBER_2", 0, 3, &umr_bitfield_default }, + { "IEC_60958_CS_CHANNEL_NUMBER_3", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7[] = { + { "IEC_60958_CS_CHANNEL_NUMBER_4", 0, 3, &umr_bitfield_default }, + { "IEC_60958_CS_CHANNEL_NUMBER_5", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8[] = { + { "IEC_60958_CS_CHANNEL_NUMBER_6", 0, 3, &umr_bitfield_default }, + { "IEC_60958_CS_CHANNEL_NUMBER_7", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO[] = { + { "ASSOCIATION_INFO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS[] = { + { "OUTPUT_ACTIVE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[] = { + { "LPIB_SNAPSHOT_LOCK", 0, 0, &umr_bitfield_default }, + { "CYCLIC_BUFFER_WRAP_COUNT", 8, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB[] = { + { "LPIB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[] = { + { "LPIB_TIMER_SNAPSHOT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE[] = { + { "CODING_TYPE", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED[] = { + { "FORMAT_CHANGED", 0, 0, &umr_bitfield_default }, + { "FORMAT_CHANGED_ACK_UR_ENABLE", 1, 1, &umr_bitfield_default }, + { "FORMAT_CHANGE_REASON", 8, 15, &umr_bitfield_default }, + { "FORMAT_CHANGE_RESPONSE", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION[] = { + { "WIRELESS_DISPLAY_IDENTIFICATION", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE[] = { + { "REMOTE_KEEP_ALIVE_ENABLE", 0, 0, &umr_bitfield_default }, + { "REMOTE_KEEP_ALIVE_CAPABILITY", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS[] = { + { "AUDIO_ENABLE_STATUS", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS[] = { + { "AUDIO_ENABLED_FLAG", 0, 0, &umr_bitfield_default }, + { "AUDIO_ENABLED_MASK", 4, 4, &umr_bitfield_default }, + { "AUDIO_ENABLED_TYPE", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS[] = { + { "AUDIO_DISABLED_FLAG", 0, 0, &umr_bitfield_default }, + { "AUDIO_DISABLED_MASK", 4, 4, &umr_bitfield_default }, + { "AUDIO_DISABLED_TYPE", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS[] = { + { "AUDIO_FORMAT_CHANGED_FLAG", 0, 0, &umr_bitfield_default }, + { "AUDIO_FORMAT_CHANGED_MASK", 4, 4, &umr_bitfield_default }, + { "AUDIO_FORMAT_CHANGED_TYPE", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = { + { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default }, + { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default }, + { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default }, + { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default }, + { "FORMAT_OVERRIDE", 4, 4, &umr_bitfield_default }, + { "STRIPE", 5, 5, &umr_bitfield_default }, + { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default }, + { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default }, + { "CONNECTION_LIST", 8, 8, &umr_bitfield_default }, + { "DIGITAL", 9, 9, &umr_bitfield_default }, + { "POWER_CONTROL", 10, 10, &umr_bitfield_default }, + { "LR_SWAP", 11, 11, &umr_bitfield_default }, + { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default }, + { "TYPE", 20, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT[] = { + { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default }, + { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default }, + { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default }, + { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default }, + { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default }, + { "STREAM_TYPE", 15, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID[] = { + { "CHANNEL_ID", 0, 3, &umr_bitfield_default }, + { "STREAM_ID", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER[] = { + { "DIGEN", 0, 0, &umr_bitfield_default }, + { "V", 1, 1, &umr_bitfield_default }, + { "VCFG", 2, 2, &umr_bitfield_default }, + { "PRE", 3, 3, &umr_bitfield_default }, + { "COPY", 4, 4, &umr_bitfield_default }, + { "NON_AUDIO", 5, 5, &umr_bitfield_default }, + { "PRO", 6, 6, &umr_bitfield_default }, + { "L", 7, 7, &umr_bitfield_default }, + { "CC", 8, 14, &umr_bitfield_default }, + { "KEEPALIVE", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS[] = { + { "STREAM_FORMATS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[] = { + { "AUDIO_RATE_CAPABILITIES", 0, 11, &umr_bitfield_default }, + { "AUDIO_BIT_CAPABILITIES", 16, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL[] = { + { "STRIPE_CONTROL", 0, 1, &umr_bitfield_default }, + { "STRIPE_CAPABILITY", 20, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE[] = { + { "RAMP_RATE", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING[] = { + { "PRESENTATION_TIME_EMBEDDING_ENABLE", 0, 0, &umr_bitfield_default }, + { "PRESENTATION_TIME_OFFSET_CHANGED", 1, 1, &umr_bitfield_default }, + { "CLEAR_GTC_COUNTER_MIN_MAX_DELTA", 2, 2, &umr_bitfield_default }, + { "PRESENTATION_TIME_EMBEDDING_GROUP", 4, 6, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA[] = { + { "GTC_COUNTER_DELTA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN[] = { + { "GTC_COUNTER_DELTA_MIN", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX[] = { + { "GTC_COUNTER_DELTA_MAX", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = { + { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default }, + { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default }, + { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default }, + { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default }, + { "STRIPE", 5, 5, &umr_bitfield_default }, + { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default }, + { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default }, + { "CONNECTION_LIST", 8, 8, &umr_bitfield_default }, + { "DIGITAL", 9, 9, &umr_bitfield_default }, + { "POWER_CONTROL", 10, 10, &umr_bitfield_default }, + { "LR_SWAP", 11, 11, &umr_bitfield_default }, + { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default }, + { "TYPE", 20, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES[] = { + { "IMPEDANCE_SENSE_CAPABLE", 0, 0, &umr_bitfield_default }, + { "TRIGGER_REQUIRED", 1, 1, &umr_bitfield_default }, + { "JACK_DETECTION_CAPABILITY", 2, 2, &umr_bitfield_default }, + { "HEADPHONE_DRIVE_CAPABLE", 3, 3, &umr_bitfield_default }, + { "OUTPUT_CAPABLE", 4, 4, &umr_bitfield_default }, + { "INPUT_CAPABLE", 5, 5, &umr_bitfield_default }, + { "BALANCED_I_O_PINS", 6, 6, &umr_bitfield_default }, + { "HDMI", 7, 7, &umr_bitfield_default }, + { "VREF_CONTROL", 8, 15, &umr_bitfield_default }, + { "EAPD_CAPABLE", 16, 16, &umr_bitfield_default }, + { "DP", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE[] = { + { "TAG", 0, 5, &umr_bitfield_default }, + { "ENABLE", 7, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE[] = { + { "IMPEDANCE_SENSE", 0, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL[] = { + { "OUT_ENABLE", 6, 6, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER[] = { + { "SPEAKER_ALLOCATION", 0, 6, &umr_bitfield_default }, + { "CHANNEL_ALLOCATION", 8, 15, &umr_bitfield_default }, + { "HDMI_CONNECTION", 16, 16, &umr_bitfield_default }, + { "DP_CONNECTION", 17, 17, &umr_bitfield_default }, + { "EXTRA_CONNECTION_INFO", 18, 23, &umr_bitfield_default }, + { "LFE_PLAYBACK_LEVEL", 24, 25, &umr_bitfield_default }, + { "LEVEL_SHIFT", 27, 30, &umr_bitfield_default }, + { "DOWN_MIX_INHIBIT", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE[] = { + { "MULTICHANNEL01_ENABLE", 0, 0, &umr_bitfield_default }, + { "MULTICHANNEL01_MUTE", 1, 1, &umr_bitfield_default }, + { "MULTICHANNEL01_CHANNEL_ID", 4, 7, &umr_bitfield_default }, + { "MULTICHANNEL23_ENABLE", 8, 8, &umr_bitfield_default }, + { "MULTICHANNEL23_MUTE", 9, 9, &umr_bitfield_default }, + { "MULTICHANNEL23_CHANNEL_ID", 12, 15, &umr_bitfield_default }, + { "MULTICHANNEL45_ENABLE", 16, 16, &umr_bitfield_default }, + { "MULTICHANNEL45_MUTE", 17, 17, &umr_bitfield_default }, + { "MULTICHANNEL45_CHANNEL_ID", 20, 23, &umr_bitfield_default }, + { "MULTICHANNEL67_ENABLE", 24, 24, &umr_bitfield_default }, + { "MULTICHANNEL67_MUTE", 25, 25, &umr_bitfield_default }, + { "MULTICHANNEL67_CHANNEL_ID", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC[] = { + { "VIDEO_LIPSYNC", 0, 7, &umr_bitfield_default }, + { "AUDIO_LIPSYNC", 8, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR[] = { + { "HBR_CAPABLE", 0, 0, &umr_bitfield_default }, + { "HBR_ENABLE", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0[] = { + { "MANUFACTURER_ID", 0, 15, &umr_bitfield_default }, + { "PRODUCT_ID", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1[] = { + { "SINK_DESCRIPTION_LEN", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2[] = { + { "PORT_ID0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3[] = { + { "PORT_ID1", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4[] = { + { "DESCRIPTION0", 0, 7, &umr_bitfield_default }, + { "DESCRIPTION1", 8, 15, &umr_bitfield_default }, + { "DESCRIPTION2", 16, 23, &umr_bitfield_default }, + { "DESCRIPTION3", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5[] = { + { "DESCRIPTION4", 0, 7, &umr_bitfield_default }, + { "DESCRIPTION5", 8, 15, &umr_bitfield_default }, + { "DESCRIPTION6", 16, 23, &umr_bitfield_default }, + { "DESCRIPTION7", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6[] = { + { "DESCRIPTION8", 0, 7, &umr_bitfield_default }, + { "DESCRIPTION9", 8, 15, &umr_bitfield_default }, + { "DESCRIPTION10", 16, 23, &umr_bitfield_default }, + { "DESCRIPTION11", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7[] = { + { "DESCRIPTION12", 0, 7, &umr_bitfield_default }, + { "DESCRIPTION13", 8, 15, &umr_bitfield_default }, + { "DESCRIPTION14", 16, 23, &umr_bitfield_default }, + { "DESCRIPTION15", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8[] = { + { "DESCRIPTION16", 0, 7, &umr_bitfield_default }, + { "DESCRIPTION17", 8, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL[] = { + { "CLOCK_GATING_DISABLE", 0, 0, &umr_bitfield_default }, + { "CLOCK_ON_STATE", 4, 4, &umr_bitfield_default }, + { "AUDIO_ENABLED", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[] = { + { "UNSOLICITED_RESPONSE_PAYLOAD", 0, 25, &umr_bitfield_default }, + { "UNSOLICITED_RESPONSE_FORCE", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[] = { + { "SEQUENCE", 0, 3, &umr_bitfield_default }, + { "DEFAULT_ASSOCIATION", 4, 7, &umr_bitfield_default }, + { "MISC", 8, 11, &umr_bitfield_default }, + { "COLOR", 12, 15, &umr_bitfield_default }, + { "CONNECTION_TYPE", 16, 19, &umr_bitfield_default }, + { "DEFAULT_DEVICE", 20, 23, &umr_bitfield_default }, + { "LOCATION", 24, 29, &umr_bitfield_default }, + { "PORT_CONNECTIVITY", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2[] = { + { "MULTICHANNEL1_ENABLE", 0, 0, &umr_bitfield_default }, + { "MULTICHANNEL1_MUTE", 1, 1, &umr_bitfield_default }, + { "MULTICHANNEL1_CHANNEL_ID", 4, 7, &umr_bitfield_default }, + { "MULTICHANNEL3_ENABLE", 8, 8, &umr_bitfield_default }, + { "MULTICHANNEL3_MUTE", 9, 9, &umr_bitfield_default }, + { "MULTICHANNEL3_CHANNEL_ID", 12, 15, &umr_bitfield_default }, + { "MULTICHANNEL5_ENABLE", 16, 16, &umr_bitfield_default }, + { "MULTICHANNEL5_MUTE", 17, 17, &umr_bitfield_default }, + { "MULTICHANNEL5_CHANNEL_ID", 20, 23, &umr_bitfield_default }, + { "MULTICHANNEL7_ENABLE", 24, 24, &umr_bitfield_default }, + { "MULTICHANNEL7_MUTE", 25, 25, &umr_bitfield_default }, + { "MULTICHANNEL7_CHANNEL_ID", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE[] = { + { "MULTICHANNEL_MODE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0[] = { + { "IEC_60958_CS_MODE", 0, 1, &umr_bitfield_default }, + { "IEC_60958_CS_SOURCE_NUMBER", 2, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1[] = { + { "IEC_60958_CS_CLOCK_ACCURACY", 0, 1, &umr_bitfield_default }, + { "IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN", 2, 2, &umr_bitfield_default }, + { "IEC_60958_CS_WORD_LENGTH", 3, 6, &umr_bitfield_default }, + { "IEC_60958_CS_WORD_LENGTH_OVRRD_EN", 7, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2[] = { + { "IEC_60958_CS_SAMPLING_FREQUENCY", 0, 5, &umr_bitfield_default }, + { "IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN", 6, 6, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3[] = { + { "IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY", 0, 3, &umr_bitfield_default }, + { "IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4[] = { + { "IEC_60958_CS_SAMPLING_FREQUENCY_COEFF", 0, 3, &umr_bitfield_default }, + { "IEC_60958_CS_MPEG_SURROUND_INFO", 4, 4, &umr_bitfield_default }, + { "IEC_60958_CS_CGMS_A", 5, 6, &umr_bitfield_default }, + { "IEC_60958_CS_CGMS_A_VALID", 7, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5[] = { + { "IEC_60958_CS_CHANNEL_NUMBER_L", 0, 3, &umr_bitfield_default }, + { "IEC_60958_CS_CHANNEL_NUMBER_R", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6[] = { + { "IEC_60958_CS_CHANNEL_NUMBER_2", 0, 3, &umr_bitfield_default }, + { "IEC_60958_CS_CHANNEL_NUMBER_3", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7[] = { + { "IEC_60958_CS_CHANNEL_NUMBER_4", 0, 3, &umr_bitfield_default }, + { "IEC_60958_CS_CHANNEL_NUMBER_5", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8[] = { + { "IEC_60958_CS_CHANNEL_NUMBER_6", 0, 3, &umr_bitfield_default }, + { "IEC_60958_CS_CHANNEL_NUMBER_7", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO[] = { + { "ASSOCIATION_INFO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS[] = { + { "OUTPUT_ACTIVE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[] = { + { "LPIB_SNAPSHOT_LOCK", 0, 0, &umr_bitfield_default }, + { "CYCLIC_BUFFER_WRAP_COUNT", 8, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB[] = { + { "LPIB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[] = { + { "LPIB_TIMER_SNAPSHOT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE[] = { + { "CODING_TYPE", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED[] = { + { "FORMAT_CHANGED", 0, 0, &umr_bitfield_default }, + { "FORMAT_CHANGED_ACK_UR_ENABLE", 1, 1, &umr_bitfield_default }, + { "FORMAT_CHANGE_REASON", 8, 15, &umr_bitfield_default }, + { "FORMAT_CHANGE_RESPONSE", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION[] = { + { "WIRELESS_DISPLAY_IDENTIFICATION", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE[] = { + { "REMOTE_KEEP_ALIVE_ENABLE", 0, 0, &umr_bitfield_default }, + { "REMOTE_KEEP_ALIVE_CAPABILITY", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS[] = { + { "AUDIO_ENABLE_STATUS", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS[] = { + { "AUDIO_ENABLED_FLAG", 0, 0, &umr_bitfield_default }, + { "AUDIO_ENABLED_MASK", 4, 4, &umr_bitfield_default }, + { "AUDIO_ENABLED_TYPE", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS[] = { + { "AUDIO_DISABLED_FLAG", 0, 0, &umr_bitfield_default }, + { "AUDIO_DISABLED_MASK", 4, 4, &umr_bitfield_default }, + { "AUDIO_DISABLED_TYPE", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS[] = { + { "AUDIO_FORMAT_CHANGED_FLAG", 0, 0, &umr_bitfield_default }, + { "AUDIO_FORMAT_CHANGED_MASK", 4, 4, &umr_bitfield_default }, + { "AUDIO_FORMAT_CHANGED_TYPE", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = { + { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default }, + { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default }, + { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default }, + { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default }, + { "FORMAT_OVERRIDE", 4, 4, &umr_bitfield_default }, + { "STRIPE", 5, 5, &umr_bitfield_default }, + { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default }, + { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default }, + { "CONNECTION_LIST", 8, 8, &umr_bitfield_default }, + { "DIGITAL", 9, 9, &umr_bitfield_default }, + { "POWER_CONTROL", 10, 10, &umr_bitfield_default }, + { "LR_SWAP", 11, 11, &umr_bitfield_default }, + { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default }, + { "TYPE", 20, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT[] = { + { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default }, + { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default }, + { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default }, + { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default }, + { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default }, + { "STREAM_TYPE", 15, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID[] = { + { "CHANNEL_ID", 0, 3, &umr_bitfield_default }, + { "STREAM_ID", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER[] = { + { "DIGEN", 0, 0, &umr_bitfield_default }, + { "V", 1, 1, &umr_bitfield_default }, + { "VCFG", 2, 2, &umr_bitfield_default }, + { "PRE", 3, 3, &umr_bitfield_default }, + { "COPY", 4, 4, &umr_bitfield_default }, + { "NON_AUDIO", 5, 5, &umr_bitfield_default }, + { "PRO", 6, 6, &umr_bitfield_default }, + { "L", 7, 7, &umr_bitfield_default }, + { "CC", 8, 14, &umr_bitfield_default }, + { "KEEPALIVE", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS[] = { + { "STREAM_FORMATS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[] = { + { "AUDIO_RATE_CAPABILITIES", 0, 11, &umr_bitfield_default }, + { "AUDIO_BIT_CAPABILITIES", 16, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL[] = { + { "STRIPE_CONTROL", 0, 1, &umr_bitfield_default }, + { "STRIPE_CAPABILITY", 20, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE[] = { + { "RAMP_RATE", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING[] = { + { "PRESENTATION_TIME_EMBEDDING_ENABLE", 0, 0, &umr_bitfield_default }, + { "PRESENTATION_TIME_OFFSET_CHANGED", 1, 1, &umr_bitfield_default }, + { "CLEAR_GTC_COUNTER_MIN_MAX_DELTA", 2, 2, &umr_bitfield_default }, + { "PRESENTATION_TIME_EMBEDDING_GROUP", 4, 6, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA[] = { + { "GTC_COUNTER_DELTA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN[] = { + { "GTC_COUNTER_DELTA_MIN", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX[] = { + { "GTC_COUNTER_DELTA_MAX", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = { + { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default }, + { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default }, + { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default }, + { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default }, + { "STRIPE", 5, 5, &umr_bitfield_default }, + { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default }, + { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default }, + { "CONNECTION_LIST", 8, 8, &umr_bitfield_default }, + { "DIGITAL", 9, 9, &umr_bitfield_default }, + { "POWER_CONTROL", 10, 10, &umr_bitfield_default }, + { "LR_SWAP", 11, 11, &umr_bitfield_default }, + { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default }, + { "TYPE", 20, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES[] = { + { "IMPEDANCE_SENSE_CAPABLE", 0, 0, &umr_bitfield_default }, + { "TRIGGER_REQUIRED", 1, 1, &umr_bitfield_default }, + { "JACK_DETECTION_CAPABILITY", 2, 2, &umr_bitfield_default }, + { "HEADPHONE_DRIVE_CAPABLE", 3, 3, &umr_bitfield_default }, + { "OUTPUT_CAPABLE", 4, 4, &umr_bitfield_default }, + { "INPUT_CAPABLE", 5, 5, &umr_bitfield_default }, + { "BALANCED_I_O_PINS", 6, 6, &umr_bitfield_default }, + { "HDMI", 7, 7, &umr_bitfield_default }, + { "VREF_CONTROL", 8, 15, &umr_bitfield_default }, + { "EAPD_CAPABLE", 16, 16, &umr_bitfield_default }, + { "DP", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE[] = { + { "TAG", 0, 5, &umr_bitfield_default }, + { "ENABLE", 7, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE[] = { + { "IMPEDANCE_SENSE", 0, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL[] = { + { "OUT_ENABLE", 6, 6, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER[] = { + { "SPEAKER_ALLOCATION", 0, 6, &umr_bitfield_default }, + { "CHANNEL_ALLOCATION", 8, 15, &umr_bitfield_default }, + { "HDMI_CONNECTION", 16, 16, &umr_bitfield_default }, + { "DP_CONNECTION", 17, 17, &umr_bitfield_default }, + { "EXTRA_CONNECTION_INFO", 18, 23, &umr_bitfield_default }, + { "LFE_PLAYBACK_LEVEL", 24, 25, &umr_bitfield_default }, + { "LEVEL_SHIFT", 27, 30, &umr_bitfield_default }, + { "DOWN_MIX_INHIBIT", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE[] = { + { "MULTICHANNEL01_ENABLE", 0, 0, &umr_bitfield_default }, + { "MULTICHANNEL01_MUTE", 1, 1, &umr_bitfield_default }, + { "MULTICHANNEL01_CHANNEL_ID", 4, 7, &umr_bitfield_default }, + { "MULTICHANNEL23_ENABLE", 8, 8, &umr_bitfield_default }, + { "MULTICHANNEL23_MUTE", 9, 9, &umr_bitfield_default }, + { "MULTICHANNEL23_CHANNEL_ID", 12, 15, &umr_bitfield_default }, + { "MULTICHANNEL45_ENABLE", 16, 16, &umr_bitfield_default }, + { "MULTICHANNEL45_MUTE", 17, 17, &umr_bitfield_default }, + { "MULTICHANNEL45_CHANNEL_ID", 20, 23, &umr_bitfield_default }, + { "MULTICHANNEL67_ENABLE", 24, 24, &umr_bitfield_default }, + { "MULTICHANNEL67_MUTE", 25, 25, &umr_bitfield_default }, + { "MULTICHANNEL67_CHANNEL_ID", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC[] = { + { "VIDEO_LIPSYNC", 0, 7, &umr_bitfield_default }, + { "AUDIO_LIPSYNC", 8, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR[] = { + { "HBR_CAPABLE", 0, 0, &umr_bitfield_default }, + { "HBR_ENABLE", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0[] = { + { "MANUFACTURER_ID", 0, 15, &umr_bitfield_default }, + { "PRODUCT_ID", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1[] = { + { "SINK_DESCRIPTION_LEN", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2[] = { + { "PORT_ID0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3[] = { + { "PORT_ID1", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4[] = { + { "DESCRIPTION0", 0, 7, &umr_bitfield_default }, + { "DESCRIPTION1", 8, 15, &umr_bitfield_default }, + { "DESCRIPTION2", 16, 23, &umr_bitfield_default }, + { "DESCRIPTION3", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5[] = { + { "DESCRIPTION4", 0, 7, &umr_bitfield_default }, + { "DESCRIPTION5", 8, 15, &umr_bitfield_default }, + { "DESCRIPTION6", 16, 23, &umr_bitfield_default }, + { "DESCRIPTION7", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6[] = { + { "DESCRIPTION8", 0, 7, &umr_bitfield_default }, + { "DESCRIPTION9", 8, 15, &umr_bitfield_default }, + { "DESCRIPTION10", 16, 23, &umr_bitfield_default }, + { "DESCRIPTION11", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7[] = { + { "DESCRIPTION12", 0, 7, &umr_bitfield_default }, + { "DESCRIPTION13", 8, 15, &umr_bitfield_default }, + { "DESCRIPTION14", 16, 23, &umr_bitfield_default }, + { "DESCRIPTION15", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8[] = { + { "DESCRIPTION16", 0, 7, &umr_bitfield_default }, + { "DESCRIPTION17", 8, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL[] = { + { "CLOCK_GATING_DISABLE", 0, 0, &umr_bitfield_default }, + { "CLOCK_ON_STATE", 4, 4, &umr_bitfield_default }, + { "AUDIO_ENABLED", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[] = { + { "UNSOLICITED_RESPONSE_PAYLOAD", 0, 25, &umr_bitfield_default }, + { "UNSOLICITED_RESPONSE_FORCE", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[] = { + { "SEQUENCE", 0, 3, &umr_bitfield_default }, + { "DEFAULT_ASSOCIATION", 4, 7, &umr_bitfield_default }, + { "MISC", 8, 11, &umr_bitfield_default }, + { "COLOR", 12, 15, &umr_bitfield_default }, + { "CONNECTION_TYPE", 16, 19, &umr_bitfield_default }, + { "DEFAULT_DEVICE", 20, 23, &umr_bitfield_default }, + { "LOCATION", 24, 29, &umr_bitfield_default }, + { "PORT_CONNECTIVITY", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2[] = { + { "MULTICHANNEL1_ENABLE", 0, 0, &umr_bitfield_default }, + { "MULTICHANNEL1_MUTE", 1, 1, &umr_bitfield_default }, + { "MULTICHANNEL1_CHANNEL_ID", 4, 7, &umr_bitfield_default }, + { "MULTICHANNEL3_ENABLE", 8, 8, &umr_bitfield_default }, + { "MULTICHANNEL3_MUTE", 9, 9, &umr_bitfield_default }, + { "MULTICHANNEL3_CHANNEL_ID", 12, 15, &umr_bitfield_default }, + { "MULTICHANNEL5_ENABLE", 16, 16, &umr_bitfield_default }, + { "MULTICHANNEL5_MUTE", 17, 17, &umr_bitfield_default }, + { "MULTICHANNEL5_CHANNEL_ID", 20, 23, &umr_bitfield_default }, + { "MULTICHANNEL7_ENABLE", 24, 24, &umr_bitfield_default }, + { "MULTICHANNEL7_MUTE", 25, 25, &umr_bitfield_default }, + { "MULTICHANNEL7_CHANNEL_ID", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE[] = { + { "MULTICHANNEL_MODE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0[] = { + { "IEC_60958_CS_MODE", 0, 1, &umr_bitfield_default }, + { "IEC_60958_CS_SOURCE_NUMBER", 2, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1[] = { + { "IEC_60958_CS_CLOCK_ACCURACY", 0, 1, &umr_bitfield_default }, + { "IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN", 2, 2, &umr_bitfield_default }, + { "IEC_60958_CS_WORD_LENGTH", 3, 6, &umr_bitfield_default }, + { "IEC_60958_CS_WORD_LENGTH_OVRRD_EN", 7, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2[] = { + { "IEC_60958_CS_SAMPLING_FREQUENCY", 0, 5, &umr_bitfield_default }, + { "IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN", 6, 6, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3[] = { + { "IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY", 0, 3, &umr_bitfield_default }, + { "IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4[] = { + { "IEC_60958_CS_SAMPLING_FREQUENCY_COEFF", 0, 3, &umr_bitfield_default }, + { "IEC_60958_CS_MPEG_SURROUND_INFO", 4, 4, &umr_bitfield_default }, + { "IEC_60958_CS_CGMS_A", 5, 6, &umr_bitfield_default }, + { "IEC_60958_CS_CGMS_A_VALID", 7, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5[] = { + { "IEC_60958_CS_CHANNEL_NUMBER_L", 0, 3, &umr_bitfield_default }, + { "IEC_60958_CS_CHANNEL_NUMBER_R", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6[] = { + { "IEC_60958_CS_CHANNEL_NUMBER_2", 0, 3, &umr_bitfield_default }, + { "IEC_60958_CS_CHANNEL_NUMBER_3", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7[] = { + { "IEC_60958_CS_CHANNEL_NUMBER_4", 0, 3, &umr_bitfield_default }, + { "IEC_60958_CS_CHANNEL_NUMBER_5", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8[] = { + { "IEC_60958_CS_CHANNEL_NUMBER_6", 0, 3, &umr_bitfield_default }, + { "IEC_60958_CS_CHANNEL_NUMBER_7", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO[] = { + { "ASSOCIATION_INFO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS[] = { + { "OUTPUT_ACTIVE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[] = { + { "LPIB_SNAPSHOT_LOCK", 0, 0, &umr_bitfield_default }, + { "CYCLIC_BUFFER_WRAP_COUNT", 8, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB[] = { + { "LPIB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[] = { + { "LPIB_TIMER_SNAPSHOT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE[] = { + { "CODING_TYPE", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED[] = { + { "FORMAT_CHANGED", 0, 0, &umr_bitfield_default }, + { "FORMAT_CHANGED_ACK_UR_ENABLE", 1, 1, &umr_bitfield_default }, + { "FORMAT_CHANGE_REASON", 8, 15, &umr_bitfield_default }, + { "FORMAT_CHANGE_RESPONSE", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION[] = { + { "WIRELESS_DISPLAY_IDENTIFICATION", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE[] = { + { "REMOTE_KEEP_ALIVE_ENABLE", 0, 0, &umr_bitfield_default }, + { "REMOTE_KEEP_ALIVE_CAPABILITY", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS[] = { + { "AUDIO_ENABLE_STATUS", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS[] = { + { "AUDIO_ENABLED_FLAG", 0, 0, &umr_bitfield_default }, + { "AUDIO_ENABLED_MASK", 4, 4, &umr_bitfield_default }, + { "AUDIO_ENABLED_TYPE", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS[] = { + { "AUDIO_DISABLED_FLAG", 0, 0, &umr_bitfield_default }, + { "AUDIO_DISABLED_MASK", 4, 4, &umr_bitfield_default }, + { "AUDIO_DISABLED_TYPE", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS[] = { + { "AUDIO_FORMAT_CHANGED_FLAG", 0, 0, &umr_bitfield_default }, + { "AUDIO_FORMAT_CHANGED_MASK", 4, 4, &umr_bitfield_default }, + { "AUDIO_FORMAT_CHANGED_TYPE", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = { + { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default }, + { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default }, + { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default }, + { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default }, + { "FORMAT_OVERRIDE", 4, 4, &umr_bitfield_default }, + { "STRIPE", 5, 5, &umr_bitfield_default }, + { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default }, + { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default }, + { "CONNECTION_LIST", 8, 8, &umr_bitfield_default }, + { "DIGITAL", 9, 9, &umr_bitfield_default }, + { "POWER_CONTROL", 10, 10, &umr_bitfield_default }, + { "LR_SWAP", 11, 11, &umr_bitfield_default }, + { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default }, + { "TYPE", 20, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT[] = { + { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default }, + { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default }, + { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default }, + { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default }, + { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default }, + { "STREAM_TYPE", 15, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID[] = { + { "CHANNEL_ID", 0, 3, &umr_bitfield_default }, + { "STREAM_ID", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER[] = { + { "DIGEN", 0, 0, &umr_bitfield_default }, + { "V", 1, 1, &umr_bitfield_default }, + { "VCFG", 2, 2, &umr_bitfield_default }, + { "PRE", 3, 3, &umr_bitfield_default }, + { "COPY", 4, 4, &umr_bitfield_default }, + { "NON_AUDIO", 5, 5, &umr_bitfield_default }, + { "PRO", 6, 6, &umr_bitfield_default }, + { "L", 7, 7, &umr_bitfield_default }, + { "CC", 8, 14, &umr_bitfield_default }, + { "KEEPALIVE", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS[] = { + { "STREAM_FORMATS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[] = { + { "AUDIO_RATE_CAPABILITIES", 0, 11, &umr_bitfield_default }, + { "AUDIO_BIT_CAPABILITIES", 16, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL[] = { + { "STRIPE_CONTROL", 0, 1, &umr_bitfield_default }, + { "STRIPE_CAPABILITY", 20, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE[] = { + { "RAMP_RATE", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING[] = { + { "PRESENTATION_TIME_EMBEDDING_ENABLE", 0, 0, &umr_bitfield_default }, + { "PRESENTATION_TIME_OFFSET_CHANGED", 1, 1, &umr_bitfield_default }, + { "CLEAR_GTC_COUNTER_MIN_MAX_DELTA", 2, 2, &umr_bitfield_default }, + { "PRESENTATION_TIME_EMBEDDING_GROUP", 4, 6, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA[] = { + { "GTC_COUNTER_DELTA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN[] = { + { "GTC_COUNTER_DELTA_MIN", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX[] = { + { "GTC_COUNTER_DELTA_MAX", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = { + { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default }, + { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default }, + { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default }, + { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default }, + { "STRIPE", 5, 5, &umr_bitfield_default }, + { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default }, + { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default }, + { "CONNECTION_LIST", 8, 8, &umr_bitfield_default }, + { "DIGITAL", 9, 9, &umr_bitfield_default }, + { "POWER_CONTROL", 10, 10, &umr_bitfield_default }, + { "LR_SWAP", 11, 11, &umr_bitfield_default }, + { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default }, + { "TYPE", 20, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES[] = { + { "IMPEDANCE_SENSE_CAPABLE", 0, 0, &umr_bitfield_default }, + { "TRIGGER_REQUIRED", 1, 1, &umr_bitfield_default }, + { "JACK_DETECTION_CAPABILITY", 2, 2, &umr_bitfield_default }, + { "HEADPHONE_DRIVE_CAPABLE", 3, 3, &umr_bitfield_default }, + { "OUTPUT_CAPABLE", 4, 4, &umr_bitfield_default }, + { "INPUT_CAPABLE", 5, 5, &umr_bitfield_default }, + { "BALANCED_I_O_PINS", 6, 6, &umr_bitfield_default }, + { "HDMI", 7, 7, &umr_bitfield_default }, + { "VREF_CONTROL", 8, 15, &umr_bitfield_default }, + { "EAPD_CAPABLE", 16, 16, &umr_bitfield_default }, + { "DP", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE[] = { + { "TAG", 0, 5, &umr_bitfield_default }, + { "ENABLE", 7, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE[] = { + { "IMPEDANCE_SENSE", 0, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL[] = { + { "OUT_ENABLE", 6, 6, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER[] = { + { "SPEAKER_ALLOCATION", 0, 6, &umr_bitfield_default }, + { "CHANNEL_ALLOCATION", 8, 15, &umr_bitfield_default }, + { "HDMI_CONNECTION", 16, 16, &umr_bitfield_default }, + { "DP_CONNECTION", 17, 17, &umr_bitfield_default }, + { "EXTRA_CONNECTION_INFO", 18, 23, &umr_bitfield_default }, + { "LFE_PLAYBACK_LEVEL", 24, 25, &umr_bitfield_default }, + { "LEVEL_SHIFT", 27, 30, &umr_bitfield_default }, + { "DOWN_MIX_INHIBIT", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE[] = { + { "MULTICHANNEL01_ENABLE", 0, 0, &umr_bitfield_default }, + { "MULTICHANNEL01_MUTE", 1, 1, &umr_bitfield_default }, + { "MULTICHANNEL01_CHANNEL_ID", 4, 7, &umr_bitfield_default }, + { "MULTICHANNEL23_ENABLE", 8, 8, &umr_bitfield_default }, + { "MULTICHANNEL23_MUTE", 9, 9, &umr_bitfield_default }, + { "MULTICHANNEL23_CHANNEL_ID", 12, 15, &umr_bitfield_default }, + { "MULTICHANNEL45_ENABLE", 16, 16, &umr_bitfield_default }, + { "MULTICHANNEL45_MUTE", 17, 17, &umr_bitfield_default }, + { "MULTICHANNEL45_CHANNEL_ID", 20, 23, &umr_bitfield_default }, + { "MULTICHANNEL67_ENABLE", 24, 24, &umr_bitfield_default }, + { "MULTICHANNEL67_MUTE", 25, 25, &umr_bitfield_default }, + { "MULTICHANNEL67_CHANNEL_ID", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC[] = { + { "VIDEO_LIPSYNC", 0, 7, &umr_bitfield_default }, + { "AUDIO_LIPSYNC", 8, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR[] = { + { "HBR_CAPABLE", 0, 0, &umr_bitfield_default }, + { "HBR_ENABLE", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0[] = { + { "MANUFACTURER_ID", 0, 15, &umr_bitfield_default }, + { "PRODUCT_ID", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1[] = { + { "SINK_DESCRIPTION_LEN", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2[] = { + { "PORT_ID0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3[] = { + { "PORT_ID1", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4[] = { + { "DESCRIPTION0", 0, 7, &umr_bitfield_default }, + { "DESCRIPTION1", 8, 15, &umr_bitfield_default }, + { "DESCRIPTION2", 16, 23, &umr_bitfield_default }, + { "DESCRIPTION3", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5[] = { + { "DESCRIPTION4", 0, 7, &umr_bitfield_default }, + { "DESCRIPTION5", 8, 15, &umr_bitfield_default }, + { "DESCRIPTION6", 16, 23, &umr_bitfield_default }, + { "DESCRIPTION7", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6[] = { + { "DESCRIPTION8", 0, 7, &umr_bitfield_default }, + { "DESCRIPTION9", 8, 15, &umr_bitfield_default }, + { "DESCRIPTION10", 16, 23, &umr_bitfield_default }, + { "DESCRIPTION11", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7[] = { + { "DESCRIPTION12", 0, 7, &umr_bitfield_default }, + { "DESCRIPTION13", 8, 15, &umr_bitfield_default }, + { "DESCRIPTION14", 16, 23, &umr_bitfield_default }, + { "DESCRIPTION15", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8[] = { + { "DESCRIPTION16", 0, 7, &umr_bitfield_default }, + { "DESCRIPTION17", 8, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL[] = { + { "CLOCK_GATING_DISABLE", 0, 0, &umr_bitfield_default }, + { "CLOCK_ON_STATE", 4, 4, &umr_bitfield_default }, + { "AUDIO_ENABLED", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[] = { + { "UNSOLICITED_RESPONSE_PAYLOAD", 0, 25, &umr_bitfield_default }, + { "UNSOLICITED_RESPONSE_FORCE", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[] = { + { "SEQUENCE", 0, 3, &umr_bitfield_default }, + { "DEFAULT_ASSOCIATION", 4, 7, &umr_bitfield_default }, + { "MISC", 8, 11, &umr_bitfield_default }, + { "COLOR", 12, 15, &umr_bitfield_default }, + { "CONNECTION_TYPE", 16, 19, &umr_bitfield_default }, + { "DEFAULT_DEVICE", 20, 23, &umr_bitfield_default }, + { "LOCATION", 24, 29, &umr_bitfield_default }, + { "PORT_CONNECTIVITY", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2[] = { + { "MULTICHANNEL1_ENABLE", 0, 0, &umr_bitfield_default }, + { "MULTICHANNEL1_MUTE", 1, 1, &umr_bitfield_default }, + { "MULTICHANNEL1_CHANNEL_ID", 4, 7, &umr_bitfield_default }, + { "MULTICHANNEL3_ENABLE", 8, 8, &umr_bitfield_default }, + { "MULTICHANNEL3_MUTE", 9, 9, &umr_bitfield_default }, + { "MULTICHANNEL3_CHANNEL_ID", 12, 15, &umr_bitfield_default }, + { "MULTICHANNEL5_ENABLE", 16, 16, &umr_bitfield_default }, + { "MULTICHANNEL5_MUTE", 17, 17, &umr_bitfield_default }, + { "MULTICHANNEL5_CHANNEL_ID", 20, 23, &umr_bitfield_default }, + { "MULTICHANNEL7_ENABLE", 24, 24, &umr_bitfield_default }, + { "MULTICHANNEL7_MUTE", 25, 25, &umr_bitfield_default }, + { "MULTICHANNEL7_CHANNEL_ID", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE[] = { + { "MULTICHANNEL_MODE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0[] = { + { "IEC_60958_CS_MODE", 0, 1, &umr_bitfield_default }, + { "IEC_60958_CS_SOURCE_NUMBER", 2, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1[] = { + { "IEC_60958_CS_CLOCK_ACCURACY", 0, 1, &umr_bitfield_default }, + { "IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN", 2, 2, &umr_bitfield_default }, + { "IEC_60958_CS_WORD_LENGTH", 3, 6, &umr_bitfield_default }, + { "IEC_60958_CS_WORD_LENGTH_OVRRD_EN", 7, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2[] = { + { "IEC_60958_CS_SAMPLING_FREQUENCY", 0, 5, &umr_bitfield_default }, + { "IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN", 6, 6, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3[] = { + { "IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY", 0, 3, &umr_bitfield_default }, + { "IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4[] = { + { "IEC_60958_CS_SAMPLING_FREQUENCY_COEFF", 0, 3, &umr_bitfield_default }, + { "IEC_60958_CS_MPEG_SURROUND_INFO", 4, 4, &umr_bitfield_default }, + { "IEC_60958_CS_CGMS_A", 5, 6, &umr_bitfield_default }, + { "IEC_60958_CS_CGMS_A_VALID", 7, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5[] = { + { "IEC_60958_CS_CHANNEL_NUMBER_L", 0, 3, &umr_bitfield_default }, + { "IEC_60958_CS_CHANNEL_NUMBER_R", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6[] = { + { "IEC_60958_CS_CHANNEL_NUMBER_2", 0, 3, &umr_bitfield_default }, + { "IEC_60958_CS_CHANNEL_NUMBER_3", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7[] = { + { "IEC_60958_CS_CHANNEL_NUMBER_4", 0, 3, &umr_bitfield_default }, + { "IEC_60958_CS_CHANNEL_NUMBER_5", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8[] = { + { "IEC_60958_CS_CHANNEL_NUMBER_6", 0, 3, &umr_bitfield_default }, + { "IEC_60958_CS_CHANNEL_NUMBER_7", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO[] = { + { "ASSOCIATION_INFO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS[] = { + { "OUTPUT_ACTIVE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[] = { + { "LPIB_SNAPSHOT_LOCK", 0, 0, &umr_bitfield_default }, + { "CYCLIC_BUFFER_WRAP_COUNT", 8, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB[] = { + { "LPIB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[] = { + { "LPIB_TIMER_SNAPSHOT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE[] = { + { "CODING_TYPE", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED[] = { + { "FORMAT_CHANGED", 0, 0, &umr_bitfield_default }, + { "FORMAT_CHANGED_ACK_UR_ENABLE", 1, 1, &umr_bitfield_default }, + { "FORMAT_CHANGE_REASON", 8, 15, &umr_bitfield_default }, + { "FORMAT_CHANGE_RESPONSE", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION[] = { + { "WIRELESS_DISPLAY_IDENTIFICATION", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE[] = { + { "REMOTE_KEEP_ALIVE_ENABLE", 0, 0, &umr_bitfield_default }, + { "REMOTE_KEEP_ALIVE_CAPABILITY", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS[] = { + { "AUDIO_ENABLE_STATUS", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS[] = { + { "AUDIO_ENABLED_FLAG", 0, 0, &umr_bitfield_default }, + { "AUDIO_ENABLED_MASK", 4, 4, &umr_bitfield_default }, + { "AUDIO_ENABLED_TYPE", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS[] = { + { "AUDIO_DISABLED_FLAG", 0, 0, &umr_bitfield_default }, + { "AUDIO_DISABLED_MASK", 4, 4, &umr_bitfield_default }, + { "AUDIO_DISABLED_TYPE", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS[] = { + { "AUDIO_FORMAT_CHANGED_FLAG", 0, 0, &umr_bitfield_default }, + { "AUDIO_FORMAT_CHANGED_MASK", 4, 4, &umr_bitfield_default }, + { "AUDIO_FORMAT_CHANGED_TYPE", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = { + { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default }, + { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default }, + { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default }, + { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default }, + { "FORMAT_OVERRIDE", 4, 4, &umr_bitfield_default }, + { "STRIPE", 5, 5, &umr_bitfield_default }, + { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default }, + { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default }, + { "CONNECTION_LIST", 8, 8, &umr_bitfield_default }, + { "DIGITAL", 9, 9, &umr_bitfield_default }, + { "POWER_CONTROL", 10, 10, &umr_bitfield_default }, + { "LR_SWAP", 11, 11, &umr_bitfield_default }, + { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default }, + { "TYPE", 20, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT[] = { + { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default }, + { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default }, + { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default }, + { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default }, + { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default }, + { "STREAM_TYPE", 15, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID[] = { + { "CHANNEL_ID", 0, 3, &umr_bitfield_default }, + { "STREAM_ID", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER[] = { + { "DIGEN", 0, 0, &umr_bitfield_default }, + { "V", 1, 1, &umr_bitfield_default }, + { "VCFG", 2, 2, &umr_bitfield_default }, + { "PRE", 3, 3, &umr_bitfield_default }, + { "COPY", 4, 4, &umr_bitfield_default }, + { "NON_AUDIO", 5, 5, &umr_bitfield_default }, + { "PRO", 6, 6, &umr_bitfield_default }, + { "L", 7, 7, &umr_bitfield_default }, + { "CC", 8, 14, &umr_bitfield_default }, + { "KEEPALIVE", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS[] = { + { "STREAM_FORMATS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[] = { + { "AUDIO_RATE_CAPABILITIES", 0, 11, &umr_bitfield_default }, + { "AUDIO_BIT_CAPABILITIES", 16, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL[] = { + { "STRIPE_CONTROL", 0, 1, &umr_bitfield_default }, + { "STRIPE_CAPABILITY", 20, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE[] = { + { "RAMP_RATE", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING[] = { + { "PRESENTATION_TIME_EMBEDDING_ENABLE", 0, 0, &umr_bitfield_default }, + { "PRESENTATION_TIME_OFFSET_CHANGED", 1, 1, &umr_bitfield_default }, + { "CLEAR_GTC_COUNTER_MIN_MAX_DELTA", 2, 2, &umr_bitfield_default }, + { "PRESENTATION_TIME_EMBEDDING_GROUP", 4, 6, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA[] = { + { "GTC_COUNTER_DELTA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN[] = { + { "GTC_COUNTER_DELTA_MIN", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX[] = { + { "GTC_COUNTER_DELTA_MAX", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = { + { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default }, + { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default }, + { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default }, + { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default }, + { "STRIPE", 5, 5, &umr_bitfield_default }, + { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default }, + { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default }, + { "CONNECTION_LIST", 8, 8, &umr_bitfield_default }, + { "DIGITAL", 9, 9, &umr_bitfield_default }, + { "POWER_CONTROL", 10, 10, &umr_bitfield_default }, + { "LR_SWAP", 11, 11, &umr_bitfield_default }, + { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default }, + { "TYPE", 20, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES[] = { + { "IMPEDANCE_SENSE_CAPABLE", 0, 0, &umr_bitfield_default }, + { "TRIGGER_REQUIRED", 1, 1, &umr_bitfield_default }, + { "JACK_DETECTION_CAPABILITY", 2, 2, &umr_bitfield_default }, + { "HEADPHONE_DRIVE_CAPABLE", 3, 3, &umr_bitfield_default }, + { "OUTPUT_CAPABLE", 4, 4, &umr_bitfield_default }, + { "INPUT_CAPABLE", 5, 5, &umr_bitfield_default }, + { "BALANCED_I_O_PINS", 6, 6, &umr_bitfield_default }, + { "HDMI", 7, 7, &umr_bitfield_default }, + { "VREF_CONTROL", 8, 15, &umr_bitfield_default }, + { "EAPD_CAPABLE", 16, 16, &umr_bitfield_default }, + { "DP", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE[] = { + { "TAG", 0, 5, &umr_bitfield_default }, + { "ENABLE", 7, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE[] = { + { "IMPEDANCE_SENSE", 0, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL[] = { + { "OUT_ENABLE", 6, 6, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER[] = { + { "SPEAKER_ALLOCATION", 0, 6, &umr_bitfield_default }, + { "CHANNEL_ALLOCATION", 8, 15, &umr_bitfield_default }, + { "HDMI_CONNECTION", 16, 16, &umr_bitfield_default }, + { "DP_CONNECTION", 17, 17, &umr_bitfield_default }, + { "EXTRA_CONNECTION_INFO", 18, 23, &umr_bitfield_default }, + { "LFE_PLAYBACK_LEVEL", 24, 25, &umr_bitfield_default }, + { "LEVEL_SHIFT", 27, 30, &umr_bitfield_default }, + { "DOWN_MIX_INHIBIT", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE[] = { + { "MULTICHANNEL01_ENABLE", 0, 0, &umr_bitfield_default }, + { "MULTICHANNEL01_MUTE", 1, 1, &umr_bitfield_default }, + { "MULTICHANNEL01_CHANNEL_ID", 4, 7, &umr_bitfield_default }, + { "MULTICHANNEL23_ENABLE", 8, 8, &umr_bitfield_default }, + { "MULTICHANNEL23_MUTE", 9, 9, &umr_bitfield_default }, + { "MULTICHANNEL23_CHANNEL_ID", 12, 15, &umr_bitfield_default }, + { "MULTICHANNEL45_ENABLE", 16, 16, &umr_bitfield_default }, + { "MULTICHANNEL45_MUTE", 17, 17, &umr_bitfield_default }, + { "MULTICHANNEL45_CHANNEL_ID", 20, 23, &umr_bitfield_default }, + { "MULTICHANNEL67_ENABLE", 24, 24, &umr_bitfield_default }, + { "MULTICHANNEL67_MUTE", 25, 25, &umr_bitfield_default }, + { "MULTICHANNEL67_CHANNEL_ID", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC[] = { + { "VIDEO_LIPSYNC", 0, 7, &umr_bitfield_default }, + { "AUDIO_LIPSYNC", 8, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR[] = { + { "HBR_CAPABLE", 0, 0, &umr_bitfield_default }, + { "HBR_ENABLE", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0[] = { + { "MANUFACTURER_ID", 0, 15, &umr_bitfield_default }, + { "PRODUCT_ID", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1[] = { + { "SINK_DESCRIPTION_LEN", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2[] = { + { "PORT_ID0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3[] = { + { "PORT_ID1", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4[] = { + { "DESCRIPTION0", 0, 7, &umr_bitfield_default }, + { "DESCRIPTION1", 8, 15, &umr_bitfield_default }, + { "DESCRIPTION2", 16, 23, &umr_bitfield_default }, + { "DESCRIPTION3", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5[] = { + { "DESCRIPTION4", 0, 7, &umr_bitfield_default }, + { "DESCRIPTION5", 8, 15, &umr_bitfield_default }, + { "DESCRIPTION6", 16, 23, &umr_bitfield_default }, + { "DESCRIPTION7", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6[] = { + { "DESCRIPTION8", 0, 7, &umr_bitfield_default }, + { "DESCRIPTION9", 8, 15, &umr_bitfield_default }, + { "DESCRIPTION10", 16, 23, &umr_bitfield_default }, + { "DESCRIPTION11", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7[] = { + { "DESCRIPTION12", 0, 7, &umr_bitfield_default }, + { "DESCRIPTION13", 8, 15, &umr_bitfield_default }, + { "DESCRIPTION14", 16, 23, &umr_bitfield_default }, + { "DESCRIPTION15", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8[] = { + { "DESCRIPTION16", 0, 7, &umr_bitfield_default }, + { "DESCRIPTION17", 8, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL[] = { + { "CLOCK_GATING_DISABLE", 0, 0, &umr_bitfield_default }, + { "CLOCK_ON_STATE", 4, 4, &umr_bitfield_default }, + { "AUDIO_ENABLED", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[] = { + { "UNSOLICITED_RESPONSE_PAYLOAD", 0, 25, &umr_bitfield_default }, + { "UNSOLICITED_RESPONSE_FORCE", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[] = { + { "SEQUENCE", 0, 3, &umr_bitfield_default }, + { "DEFAULT_ASSOCIATION", 4, 7, &umr_bitfield_default }, + { "MISC", 8, 11, &umr_bitfield_default }, + { "COLOR", 12, 15, &umr_bitfield_default }, + { "CONNECTION_TYPE", 16, 19, &umr_bitfield_default }, + { "DEFAULT_DEVICE", 20, 23, &umr_bitfield_default }, + { "LOCATION", 24, 29, &umr_bitfield_default }, + { "PORT_CONNECTIVITY", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2[] = { + { "MULTICHANNEL1_ENABLE", 0, 0, &umr_bitfield_default }, + { "MULTICHANNEL1_MUTE", 1, 1, &umr_bitfield_default }, + { "MULTICHANNEL1_CHANNEL_ID", 4, 7, &umr_bitfield_default }, + { "MULTICHANNEL3_ENABLE", 8, 8, &umr_bitfield_default }, + { "MULTICHANNEL3_MUTE", 9, 9, &umr_bitfield_default }, + { "MULTICHANNEL3_CHANNEL_ID", 12, 15, &umr_bitfield_default }, + { "MULTICHANNEL5_ENABLE", 16, 16, &umr_bitfield_default }, + { "MULTICHANNEL5_MUTE", 17, 17, &umr_bitfield_default }, + { "MULTICHANNEL5_CHANNEL_ID", 20, 23, &umr_bitfield_default }, + { "MULTICHANNEL7_ENABLE", 24, 24, &umr_bitfield_default }, + { "MULTICHANNEL7_MUTE", 25, 25, &umr_bitfield_default }, + { "MULTICHANNEL7_CHANNEL_ID", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE[] = { + { "MULTICHANNEL_MODE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0[] = { + { "IEC_60958_CS_MODE", 0, 1, &umr_bitfield_default }, + { "IEC_60958_CS_SOURCE_NUMBER", 2, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1[] = { + { "IEC_60958_CS_CLOCK_ACCURACY", 0, 1, &umr_bitfield_default }, + { "IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN", 2, 2, &umr_bitfield_default }, + { "IEC_60958_CS_WORD_LENGTH", 3, 6, &umr_bitfield_default }, + { "IEC_60958_CS_WORD_LENGTH_OVRRD_EN", 7, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2[] = { + { "IEC_60958_CS_SAMPLING_FREQUENCY", 0, 5, &umr_bitfield_default }, + { "IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN", 6, 6, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3[] = { + { "IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY", 0, 3, &umr_bitfield_default }, + { "IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4[] = { + { "IEC_60958_CS_SAMPLING_FREQUENCY_COEFF", 0, 3, &umr_bitfield_default }, + { "IEC_60958_CS_MPEG_SURROUND_INFO", 4, 4, &umr_bitfield_default }, + { "IEC_60958_CS_CGMS_A", 5, 6, &umr_bitfield_default }, + { "IEC_60958_CS_CGMS_A_VALID", 7, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5[] = { + { "IEC_60958_CS_CHANNEL_NUMBER_L", 0, 3, &umr_bitfield_default }, + { "IEC_60958_CS_CHANNEL_NUMBER_R", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6[] = { + { "IEC_60958_CS_CHANNEL_NUMBER_2", 0, 3, &umr_bitfield_default }, + { "IEC_60958_CS_CHANNEL_NUMBER_3", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7[] = { + { "IEC_60958_CS_CHANNEL_NUMBER_4", 0, 3, &umr_bitfield_default }, + { "IEC_60958_CS_CHANNEL_NUMBER_5", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8[] = { + { "IEC_60958_CS_CHANNEL_NUMBER_6", 0, 3, &umr_bitfield_default }, + { "IEC_60958_CS_CHANNEL_NUMBER_7", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO[] = { + { "ASSOCIATION_INFO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS[] = { + { "OUTPUT_ACTIVE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[] = { + { "LPIB_SNAPSHOT_LOCK", 0, 0, &umr_bitfield_default }, + { "CYCLIC_BUFFER_WRAP_COUNT", 8, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB[] = { + { "LPIB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[] = { + { "LPIB_TIMER_SNAPSHOT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE[] = { + { "CODING_TYPE", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED[] = { + { "FORMAT_CHANGED", 0, 0, &umr_bitfield_default }, + { "FORMAT_CHANGED_ACK_UR_ENABLE", 1, 1, &umr_bitfield_default }, + { "FORMAT_CHANGE_REASON", 8, 15, &umr_bitfield_default }, + { "FORMAT_CHANGE_RESPONSE", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION[] = { + { "WIRELESS_DISPLAY_IDENTIFICATION", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE[] = { + { "REMOTE_KEEP_ALIVE_ENABLE", 0, 0, &umr_bitfield_default }, + { "REMOTE_KEEP_ALIVE_CAPABILITY", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS[] = { + { "AUDIO_ENABLE_STATUS", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS[] = { + { "AUDIO_ENABLED_FLAG", 0, 0, &umr_bitfield_default }, + { "AUDIO_ENABLED_MASK", 4, 4, &umr_bitfield_default }, + { "AUDIO_ENABLED_TYPE", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS[] = { + { "AUDIO_DISABLED_FLAG", 0, 0, &umr_bitfield_default }, + { "AUDIO_DISABLED_MASK", 4, 4, &umr_bitfield_default }, + { "AUDIO_DISABLED_TYPE", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS[] = { + { "AUDIO_FORMAT_CHANGED_FLAG", 0, 0, &umr_bitfield_default }, + { "AUDIO_FORMAT_CHANGED_MASK", 4, 4, &umr_bitfield_default }, + { "AUDIO_FORMAT_CHANGED_TYPE", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = { + { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default }, + { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default }, + { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default }, + { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default }, + { "FORMAT_OVERRIDE", 4, 4, &umr_bitfield_default }, + { "STRIPE", 5, 5, &umr_bitfield_default }, + { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default }, + { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default }, + { "CONNECTION_LIST", 8, 8, &umr_bitfield_default }, + { "DIGITAL", 9, 9, &umr_bitfield_default }, + { "POWER_CONTROL", 10, 10, &umr_bitfield_default }, + { "LR_SWAP", 11, 11, &umr_bitfield_default }, + { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default }, + { "TYPE", 20, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT[] = { + { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default }, + { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default }, + { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default }, + { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default }, + { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default }, + { "STREAM_TYPE", 15, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID[] = { + { "CHANNEL_ID", 0, 3, &umr_bitfield_default }, + { "STREAM_ID", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER[] = { + { "DIGEN", 0, 0, &umr_bitfield_default }, + { "V", 1, 1, &umr_bitfield_default }, + { "VCFG", 2, 2, &umr_bitfield_default }, + { "PRE", 3, 3, &umr_bitfield_default }, + { "COPY", 4, 4, &umr_bitfield_default }, + { "NON_AUDIO", 5, 5, &umr_bitfield_default }, + { "PRO", 6, 6, &umr_bitfield_default }, + { "L", 7, 7, &umr_bitfield_default }, + { "CC", 8, 14, &umr_bitfield_default }, + { "KEEPALIVE", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS[] = { + { "STREAM_FORMATS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[] = { + { "AUDIO_RATE_CAPABILITIES", 0, 11, &umr_bitfield_default }, + { "AUDIO_BIT_CAPABILITIES", 16, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL[] = { + { "STRIPE_CONTROL", 0, 1, &umr_bitfield_default }, + { "STRIPE_CAPABILITY", 20, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE[] = { + { "RAMP_RATE", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING[] = { + { "PRESENTATION_TIME_EMBEDDING_ENABLE", 0, 0, &umr_bitfield_default }, + { "PRESENTATION_TIME_OFFSET_CHANGED", 1, 1, &umr_bitfield_default }, + { "CLEAR_GTC_COUNTER_MIN_MAX_DELTA", 2, 2, &umr_bitfield_default }, + { "PRESENTATION_TIME_EMBEDDING_GROUP", 4, 6, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA[] = { + { "GTC_COUNTER_DELTA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN[] = { + { "GTC_COUNTER_DELTA_MIN", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX[] = { + { "GTC_COUNTER_DELTA_MAX", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = { + { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default }, + { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default }, + { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default }, + { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default }, + { "STRIPE", 5, 5, &umr_bitfield_default }, + { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default }, + { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default }, + { "CONNECTION_LIST", 8, 8, &umr_bitfield_default }, + { "DIGITAL", 9, 9, &umr_bitfield_default }, + { "POWER_CONTROL", 10, 10, &umr_bitfield_default }, + { "LR_SWAP", 11, 11, &umr_bitfield_default }, + { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default }, + { "TYPE", 20, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES[] = { + { "IMPEDANCE_SENSE_CAPABLE", 0, 0, &umr_bitfield_default }, + { "TRIGGER_REQUIRED", 1, 1, &umr_bitfield_default }, + { "JACK_DETECTION_CAPABILITY", 2, 2, &umr_bitfield_default }, + { "HEADPHONE_DRIVE_CAPABLE", 3, 3, &umr_bitfield_default }, + { "OUTPUT_CAPABLE", 4, 4, &umr_bitfield_default }, + { "INPUT_CAPABLE", 5, 5, &umr_bitfield_default }, + { "BALANCED_I_O_PINS", 6, 6, &umr_bitfield_default }, + { "HDMI", 7, 7, &umr_bitfield_default }, + { "VREF_CONTROL", 8, 15, &umr_bitfield_default }, + { "EAPD_CAPABLE", 16, 16, &umr_bitfield_default }, + { "DP", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE[] = { + { "TAG", 0, 5, &umr_bitfield_default }, + { "ENABLE", 7, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE[] = { + { "IMPEDANCE_SENSE", 0, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL[] = { + { "OUT_ENABLE", 6, 6, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER[] = { + { "SPEAKER_ALLOCATION", 0, 6, &umr_bitfield_default }, + { "CHANNEL_ALLOCATION", 8, 15, &umr_bitfield_default }, + { "HDMI_CONNECTION", 16, 16, &umr_bitfield_default }, + { "DP_CONNECTION", 17, 17, &umr_bitfield_default }, + { "EXTRA_CONNECTION_INFO", 18, 23, &umr_bitfield_default }, + { "LFE_PLAYBACK_LEVEL", 24, 25, &umr_bitfield_default }, + { "LEVEL_SHIFT", 27, 30, &umr_bitfield_default }, + { "DOWN_MIX_INHIBIT", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13[] = { + { "MAX_CHANNELS", 0, 2, &umr_bitfield_default }, + { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default }, + { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE[] = { + { "MULTICHANNEL01_ENABLE", 0, 0, &umr_bitfield_default }, + { "MULTICHANNEL01_MUTE", 1, 1, &umr_bitfield_default }, + { "MULTICHANNEL01_CHANNEL_ID", 4, 7, &umr_bitfield_default }, + { "MULTICHANNEL23_ENABLE", 8, 8, &umr_bitfield_default }, + { "MULTICHANNEL23_MUTE", 9, 9, &umr_bitfield_default }, + { "MULTICHANNEL23_CHANNEL_ID", 12, 15, &umr_bitfield_default }, + { "MULTICHANNEL45_ENABLE", 16, 16, &umr_bitfield_default }, + { "MULTICHANNEL45_MUTE", 17, 17, &umr_bitfield_default }, + { "MULTICHANNEL45_CHANNEL_ID", 20, 23, &umr_bitfield_default }, + { "MULTICHANNEL67_ENABLE", 24, 24, &umr_bitfield_default }, + { "MULTICHANNEL67_MUTE", 25, 25, &umr_bitfield_default }, + { "MULTICHANNEL67_CHANNEL_ID", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC[] = { + { "VIDEO_LIPSYNC", 0, 7, &umr_bitfield_default }, + { "AUDIO_LIPSYNC", 8, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR[] = { + { "HBR_CAPABLE", 0, 0, &umr_bitfield_default }, + { "HBR_ENABLE", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0[] = { + { "MANUFACTURER_ID", 0, 15, &umr_bitfield_default }, + { "PRODUCT_ID", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1[] = { + { "SINK_DESCRIPTION_LEN", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2[] = { + { "PORT_ID0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3[] = { + { "PORT_ID1", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4[] = { + { "DESCRIPTION0", 0, 7, &umr_bitfield_default }, + { "DESCRIPTION1", 8, 15, &umr_bitfield_default }, + { "DESCRIPTION2", 16, 23, &umr_bitfield_default }, + { "DESCRIPTION3", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5[] = { + { "DESCRIPTION4", 0, 7, &umr_bitfield_default }, + { "DESCRIPTION5", 8, 15, &umr_bitfield_default }, + { "DESCRIPTION6", 16, 23, &umr_bitfield_default }, + { "DESCRIPTION7", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6[] = { + { "DESCRIPTION8", 0, 7, &umr_bitfield_default }, + { "DESCRIPTION9", 8, 15, &umr_bitfield_default }, + { "DESCRIPTION10", 16, 23, &umr_bitfield_default }, + { "DESCRIPTION11", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7[] = { + { "DESCRIPTION12", 0, 7, &umr_bitfield_default }, + { "DESCRIPTION13", 8, 15, &umr_bitfield_default }, + { "DESCRIPTION14", 16, 23, &umr_bitfield_default }, + { "DESCRIPTION15", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8[] = { + { "DESCRIPTION16", 0, 7, &umr_bitfield_default }, + { "DESCRIPTION17", 8, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL[] = { + { "CLOCK_GATING_DISABLE", 0, 0, &umr_bitfield_default }, + { "CLOCK_ON_STATE", 4, 4, &umr_bitfield_default }, + { "AUDIO_ENABLED", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[] = { + { "UNSOLICITED_RESPONSE_PAYLOAD", 0, 25, &umr_bitfield_default }, + { "UNSOLICITED_RESPONSE_FORCE", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[] = { + { "SEQUENCE", 0, 3, &umr_bitfield_default }, + { "DEFAULT_ASSOCIATION", 4, 7, &umr_bitfield_default }, + { "MISC", 8, 11, &umr_bitfield_default }, + { "COLOR", 12, 15, &umr_bitfield_default }, + { "CONNECTION_TYPE", 16, 19, &umr_bitfield_default }, + { "DEFAULT_DEVICE", 20, 23, &umr_bitfield_default }, + { "LOCATION", 24, 29, &umr_bitfield_default }, + { "PORT_CONNECTIVITY", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2[] = { + { "MULTICHANNEL1_ENABLE", 0, 0, &umr_bitfield_default }, + { "MULTICHANNEL1_MUTE", 1, 1, &umr_bitfield_default }, + { "MULTICHANNEL1_CHANNEL_ID", 4, 7, &umr_bitfield_default }, + { "MULTICHANNEL3_ENABLE", 8, 8, &umr_bitfield_default }, + { "MULTICHANNEL3_MUTE", 9, 9, &umr_bitfield_default }, + { "MULTICHANNEL3_CHANNEL_ID", 12, 15, &umr_bitfield_default }, + { "MULTICHANNEL5_ENABLE", 16, 16, &umr_bitfield_default }, + { "MULTICHANNEL5_MUTE", 17, 17, &umr_bitfield_default }, + { "MULTICHANNEL5_CHANNEL_ID", 20, 23, &umr_bitfield_default }, + { "MULTICHANNEL7_ENABLE", 24, 24, &umr_bitfield_default }, + { "MULTICHANNEL7_MUTE", 25, 25, &umr_bitfield_default }, + { "MULTICHANNEL7_CHANNEL_ID", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE[] = { + { "MULTICHANNEL_MODE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0[] = { + { "IEC_60958_CS_MODE", 0, 1, &umr_bitfield_default }, + { "IEC_60958_CS_SOURCE_NUMBER", 2, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1[] = { + { "IEC_60958_CS_CLOCK_ACCURACY", 0, 1, &umr_bitfield_default }, + { "IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN", 2, 2, &umr_bitfield_default }, + { "IEC_60958_CS_WORD_LENGTH", 3, 6, &umr_bitfield_default }, + { "IEC_60958_CS_WORD_LENGTH_OVRRD_EN", 7, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2[] = { + { "IEC_60958_CS_SAMPLING_FREQUENCY", 0, 5, &umr_bitfield_default }, + { "IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN", 6, 6, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3[] = { + { "IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY", 0, 3, &umr_bitfield_default }, + { "IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4[] = { + { "IEC_60958_CS_SAMPLING_FREQUENCY_COEFF", 0, 3, &umr_bitfield_default }, + { "IEC_60958_CS_MPEG_SURROUND_INFO", 4, 4, &umr_bitfield_default }, + { "IEC_60958_CS_CGMS_A", 5, 6, &umr_bitfield_default }, + { "IEC_60958_CS_CGMS_A_VALID", 7, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5[] = { + { "IEC_60958_CS_CHANNEL_NUMBER_L", 0, 3, &umr_bitfield_default }, + { "IEC_60958_CS_CHANNEL_NUMBER_R", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6[] = { + { "IEC_60958_CS_CHANNEL_NUMBER_2", 0, 3, &umr_bitfield_default }, + { "IEC_60958_CS_CHANNEL_NUMBER_3", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7[] = { + { "IEC_60958_CS_CHANNEL_NUMBER_4", 0, 3, &umr_bitfield_default }, + { "IEC_60958_CS_CHANNEL_NUMBER_5", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8[] = { + { "IEC_60958_CS_CHANNEL_NUMBER_6", 0, 3, &umr_bitfield_default }, + { "IEC_60958_CS_CHANNEL_NUMBER_7", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO[] = { + { "ASSOCIATION_INFO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS[] = { + { "OUTPUT_ACTIVE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[] = { + { "LPIB_SNAPSHOT_LOCK", 0, 0, &umr_bitfield_default }, + { "CYCLIC_BUFFER_WRAP_COUNT", 8, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB[] = { + { "LPIB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[] = { + { "LPIB_TIMER_SNAPSHOT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE[] = { + { "CODING_TYPE", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED[] = { + { "FORMAT_CHANGED", 0, 0, &umr_bitfield_default }, + { "FORMAT_CHANGED_ACK_UR_ENABLE", 1, 1, &umr_bitfield_default }, + { "FORMAT_CHANGE_REASON", 8, 15, &umr_bitfield_default }, + { "FORMAT_CHANGE_RESPONSE", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION[] = { + { "WIRELESS_DISPLAY_IDENTIFICATION", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE[] = { + { "REMOTE_KEEP_ALIVE_ENABLE", 0, 0, &umr_bitfield_default }, + { "REMOTE_KEEP_ALIVE_CAPABILITY", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS[] = { + { "AUDIO_ENABLE_STATUS", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS[] = { + { "AUDIO_ENABLED_FLAG", 0, 0, &umr_bitfield_default }, + { "AUDIO_ENABLED_MASK", 4, 4, &umr_bitfield_default }, + { "AUDIO_ENABLED_TYPE", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS[] = { + { "AUDIO_DISABLED_FLAG", 0, 0, &umr_bitfield_default }, + { "AUDIO_DISABLED_MASK", 4, 4, &umr_bitfield_default }, + { "AUDIO_DISABLED_TYPE", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS[] = { + { "AUDIO_FORMAT_CHANGED_FLAG", 0, 0, &umr_bitfield_default }, + { "AUDIO_FORMAT_CHANGED_MASK", 4, 4, &umr_bitfield_default }, + { "AUDIO_FORMAT_CHANGED_TYPE", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = { + { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default }, + { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default }, + { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default }, + { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default }, + { "FORMAT_OVERRIDE", 4, 4, &umr_bitfield_default }, + { "STRIPE", 5, 5, &umr_bitfield_default }, + { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default }, + { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default }, + { "CONNECTION_LIST", 8, 8, &umr_bitfield_default }, + { "DIGITAL", 9, 9, &umr_bitfield_default }, + { "POWER_CONTROL", 10, 10, &umr_bitfield_default }, + { "LR_SWAP", 11, 11, &umr_bitfield_default }, + { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default }, + { "TYPE", 20, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT[] = { + { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default }, + { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default }, + { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default }, + { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default }, + { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default }, + { "STREAM_TYPE", 15, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID[] = { + { "CHANNEL_ID", 0, 3, &umr_bitfield_default }, + { "STREAM_ID", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER[] = { + { "DIGEN", 0, 0, &umr_bitfield_default }, + { "V", 1, 1, &umr_bitfield_default }, + { "VCFG", 2, 2, &umr_bitfield_default }, + { "PRE", 3, 3, &umr_bitfield_default }, + { "COPY", 4, 4, &umr_bitfield_default }, + { "NON_AUDIO", 5, 5, &umr_bitfield_default }, + { "PRO", 6, 6, &umr_bitfield_default }, + { "L", 7, 7, &umr_bitfield_default }, + { "CC", 8, 14, &umr_bitfield_default }, + { "KEEPALIVE", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS[] = { + { "STREAM_FORMATS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[] = { + { "AUDIO_RATE_CAPABILITIES", 0, 11, &umr_bitfield_default }, + { "AUDIO_BIT_CAPABILITIES", 16, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = { + { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default }, + { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default }, + { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default }, + { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default }, + { "STRIPE", 5, 5, &umr_bitfield_default }, + { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default }, + { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default }, + { "CONNECTION_LIST", 8, 8, &umr_bitfield_default }, + { "DIGITAL", 9, 9, &umr_bitfield_default }, + { "POWER_CONTROL", 10, 10, &umr_bitfield_default }, + { "LR_SWAP", 11, 11, &umr_bitfield_default }, + { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default }, + { "TYPE", 20, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES[] = { + { "IMPEDANCE_SENSE_CAPABLE", 0, 0, &umr_bitfield_default }, + { "TRIGGER_REQUIRED", 1, 1, &umr_bitfield_default }, + { "JACK_DETECTION_CAPABILITY", 2, 2, &umr_bitfield_default }, + { "HEADPHONE_DRIVE_CAPABLE", 3, 3, &umr_bitfield_default }, + { "OUTPUT_CAPABLE", 4, 4, &umr_bitfield_default }, + { "INPUT_CAPABLE", 5, 5, &umr_bitfield_default }, + { "BALANCED_I_O_PINS", 6, 6, &umr_bitfield_default }, + { "HDMI", 7, 7, &umr_bitfield_default }, + { "VREF_CONTROL", 8, 15, &umr_bitfield_default }, + { "EAPD_CAPABLE", 16, 16, &umr_bitfield_default }, + { "DP", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE[] = { + { "TAG", 0, 5, &umr_bitfield_default }, + { "ENABLE", 7, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE[] = { + { "IMPEDANCE_SENSE", 0, 30, &umr_bitfield_default }, + { "PRESENCE_DETECT", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL[] = { + { "IN_ENABLE", 5, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE[] = { + { "MULTICHANNEL0_ENABLE", 0, 0, &umr_bitfield_default }, + { "MULTICHANNEL0_MUTE", 1, 1, &umr_bitfield_default }, + { "MULTICHANNEL0_CHANNEL_ID", 4, 7, &umr_bitfield_default }, + { "MULTICHANNEL1_ENABLE", 8, 8, &umr_bitfield_default }, + { "MULTICHANNEL1_MUTE", 9, 9, &umr_bitfield_default }, + { "MULTICHANNEL1_CHANNEL_ID", 12, 15, &umr_bitfield_default }, + { "MULTICHANNEL2_ENABLE", 16, 16, &umr_bitfield_default }, + { "MULTICHANNEL2_MUTE", 17, 17, &umr_bitfield_default }, + { "MULTICHANNEL2_CHANNEL_ID", 20, 23, &umr_bitfield_default }, + { "MULTICHANNEL3_ENABLE", 24, 24, &umr_bitfield_default }, + { "MULTICHANNEL3_MUTE", 25, 25, &umr_bitfield_default }, + { "MULTICHANNEL3_CHANNEL_ID", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2[] = { + { "MULTICHANNEL4_ENABLE", 0, 0, &umr_bitfield_default }, + { "MULTICHANNEL4_MUTE", 1, 1, &umr_bitfield_default }, + { "MULTICHANNEL4_CHANNEL_ID", 4, 7, &umr_bitfield_default }, + { "MULTICHANNEL5_ENABLE", 8, 8, &umr_bitfield_default }, + { "MULTICHANNEL5_MUTE", 9, 9, &umr_bitfield_default }, + { "MULTICHANNEL5_CHANNEL_ID", 12, 15, &umr_bitfield_default }, + { "MULTICHANNEL6_ENABLE", 16, 16, &umr_bitfield_default }, + { "MULTICHANNEL6_MUTE", 17, 17, &umr_bitfield_default }, + { "MULTICHANNEL6_CHANNEL_ID", 20, 23, &umr_bitfield_default }, + { "MULTICHANNEL7_ENABLE", 24, 24, &umr_bitfield_default }, + { "MULTICHANNEL7_MUTE", 25, 25, &umr_bitfield_default }, + { "MULTICHANNEL7_CHANNEL_ID", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR[] = { + { "HBR_CAPABLE", 0, 0, &umr_bitfield_default }, + { "HBR_ENABLE", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION[] = { + { "CHANNEL_ALLOCATION", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL[] = { + { "CLOCK_GATING_DISABLE", 0, 0, &umr_bitfield_default }, + { "CLOCK_ON_STATE", 4, 4, &umr_bitfield_default }, + { "AUDIO_ENABLED", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[] = { + { "UNSOLICITED_RESPONSE_PAYLOAD", 0, 25, &umr_bitfield_default }, + { "UNSOLICITED_RESPONSE_FORCE", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[] = { + { "SEQUENCE", 0, 3, &umr_bitfield_default }, + { "DEFAULT_ASSOCIATION", 4, 7, &umr_bitfield_default }, + { "MISC", 8, 11, &umr_bitfield_default }, + { "COLOR", 12, 15, &umr_bitfield_default }, + { "CONNECTION_TYPE", 16, 19, &umr_bitfield_default }, + { "DEFAULT_DEVICE", 20, 23, &umr_bitfield_default }, + { "LOCATION", 24, 29, &umr_bitfield_default }, + { "PORT_CONNECTIVITY", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[] = { + { "LPIB_SNAPSHOT_LOCK", 0, 0, &umr_bitfield_default }, + { "CYCLIC_BUFFER_WRAP_COUNT", 8, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB[] = { + { "LPIB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[] = { + { "LPIB_TIMER_SNAPSHOT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL[] = { + { "INPUT_ACTIVITY", 0, 0, &umr_bitfield_default }, + { "CHANNEL_LAYOUT", 1, 2, &umr_bitfield_default }, + { "INPUT_ACTIVITY_UR_ENABLE", 4, 4, &umr_bitfield_default }, + { "INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE", 5, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME[] = { + { "CHANNEL_COUNT", 0, 2, &umr_bitfield_default }, + { "CHANNEL_ALLOCATION", 8, 15, &umr_bitfield_default }, + { "INFOFRAME_BYTE_5", 16, 23, &umr_bitfield_default }, + { "INFOFRAME_VALID", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = { + { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default }, + { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default }, + { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default }, + { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default }, + { "FORMAT_OVERRIDE", 4, 4, &umr_bitfield_default }, + { "STRIPE", 5, 5, &umr_bitfield_default }, + { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default }, + { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default }, + { "CONNECTION_LIST", 8, 8, &umr_bitfield_default }, + { "DIGITAL", 9, 9, &umr_bitfield_default }, + { "POWER_CONTROL", 10, 10, &umr_bitfield_default }, + { "LR_SWAP", 11, 11, &umr_bitfield_default }, + { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default }, + { "TYPE", 20, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT[] = { + { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default }, + { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default }, + { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default }, + { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default }, + { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default }, + { "STREAM_TYPE", 15, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID[] = { + { "CHANNEL_ID", 0, 3, &umr_bitfield_default }, + { "STREAM_ID", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER[] = { + { "DIGEN", 0, 0, &umr_bitfield_default }, + { "V", 1, 1, &umr_bitfield_default }, + { "VCFG", 2, 2, &umr_bitfield_default }, + { "PRE", 3, 3, &umr_bitfield_default }, + { "COPY", 4, 4, &umr_bitfield_default }, + { "NON_AUDIO", 5, 5, &umr_bitfield_default }, + { "PRO", 6, 6, &umr_bitfield_default }, + { "L", 7, 7, &umr_bitfield_default }, + { "CC", 8, 14, &umr_bitfield_default }, + { "KEEPALIVE", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS[] = { + { "STREAM_FORMATS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[] = { + { "AUDIO_RATE_CAPABILITIES", 0, 11, &umr_bitfield_default }, + { "AUDIO_BIT_CAPABILITIES", 16, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = { + { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default }, + { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default }, + { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default }, + { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default }, + { "STRIPE", 5, 5, &umr_bitfield_default }, + { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default }, + { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default }, + { "CONNECTION_LIST", 8, 8, &umr_bitfield_default }, + { "DIGITAL", 9, 9, &umr_bitfield_default }, + { "POWER_CONTROL", 10, 10, &umr_bitfield_default }, + { "LR_SWAP", 11, 11, &umr_bitfield_default }, + { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default }, + { "TYPE", 20, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES[] = { + { "IMPEDANCE_SENSE_CAPABLE", 0, 0, &umr_bitfield_default }, + { "TRIGGER_REQUIRED", 1, 1, &umr_bitfield_default }, + { "JACK_DETECTION_CAPABILITY", 2, 2, &umr_bitfield_default }, + { "HEADPHONE_DRIVE_CAPABLE", 3, 3, &umr_bitfield_default }, + { "OUTPUT_CAPABLE", 4, 4, &umr_bitfield_default }, + { "INPUT_CAPABLE", 5, 5, &umr_bitfield_default }, + { "BALANCED_I_O_PINS", 6, 6, &umr_bitfield_default }, + { "HDMI", 7, 7, &umr_bitfield_default }, + { "VREF_CONTROL", 8, 15, &umr_bitfield_default }, + { "EAPD_CAPABLE", 16, 16, &umr_bitfield_default }, + { "DP", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE[] = { + { "TAG", 0, 5, &umr_bitfield_default }, + { "ENABLE", 7, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE[] = { + { "IMPEDANCE_SENSE", 0, 30, &umr_bitfield_default }, + { "PRESENCE_DETECT", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL[] = { + { "IN_ENABLE", 5, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE[] = { + { "MULTICHANNEL0_ENABLE", 0, 0, &umr_bitfield_default }, + { "MULTICHANNEL0_MUTE", 1, 1, &umr_bitfield_default }, + { "MULTICHANNEL0_CHANNEL_ID", 4, 7, &umr_bitfield_default }, + { "MULTICHANNEL1_ENABLE", 8, 8, &umr_bitfield_default }, + { "MULTICHANNEL1_MUTE", 9, 9, &umr_bitfield_default }, + { "MULTICHANNEL1_CHANNEL_ID", 12, 15, &umr_bitfield_default }, + { "MULTICHANNEL2_ENABLE", 16, 16, &umr_bitfield_default }, + { "MULTICHANNEL2_MUTE", 17, 17, &umr_bitfield_default }, + { "MULTICHANNEL2_CHANNEL_ID", 20, 23, &umr_bitfield_default }, + { "MULTICHANNEL3_ENABLE", 24, 24, &umr_bitfield_default }, + { "MULTICHANNEL3_MUTE", 25, 25, &umr_bitfield_default }, + { "MULTICHANNEL3_CHANNEL_ID", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2[] = { + { "MULTICHANNEL4_ENABLE", 0, 0, &umr_bitfield_default }, + { "MULTICHANNEL4_MUTE", 1, 1, &umr_bitfield_default }, + { "MULTICHANNEL4_CHANNEL_ID", 4, 7, &umr_bitfield_default }, + { "MULTICHANNEL5_ENABLE", 8, 8, &umr_bitfield_default }, + { "MULTICHANNEL5_MUTE", 9, 9, &umr_bitfield_default }, + { "MULTICHANNEL5_CHANNEL_ID", 12, 15, &umr_bitfield_default }, + { "MULTICHANNEL6_ENABLE", 16, 16, &umr_bitfield_default }, + { "MULTICHANNEL6_MUTE", 17, 17, &umr_bitfield_default }, + { "MULTICHANNEL6_CHANNEL_ID", 20, 23, &umr_bitfield_default }, + { "MULTICHANNEL7_ENABLE", 24, 24, &umr_bitfield_default }, + { "MULTICHANNEL7_MUTE", 25, 25, &umr_bitfield_default }, + { "MULTICHANNEL7_CHANNEL_ID", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR[] = { + { "HBR_CAPABLE", 0, 0, &umr_bitfield_default }, + { "HBR_ENABLE", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION[] = { + { "CHANNEL_ALLOCATION", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL[] = { + { "CLOCK_GATING_DISABLE", 0, 0, &umr_bitfield_default }, + { "CLOCK_ON_STATE", 4, 4, &umr_bitfield_default }, + { "AUDIO_ENABLED", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[] = { + { "UNSOLICITED_RESPONSE_PAYLOAD", 0, 25, &umr_bitfield_default }, + { "UNSOLICITED_RESPONSE_FORCE", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[] = { + { "SEQUENCE", 0, 3, &umr_bitfield_default }, + { "DEFAULT_ASSOCIATION", 4, 7, &umr_bitfield_default }, + { "MISC", 8, 11, &umr_bitfield_default }, + { "COLOR", 12, 15, &umr_bitfield_default }, + { "CONNECTION_TYPE", 16, 19, &umr_bitfield_default }, + { "DEFAULT_DEVICE", 20, 23, &umr_bitfield_default }, + { "LOCATION", 24, 29, &umr_bitfield_default }, + { "PORT_CONNECTIVITY", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[] = { + { "LPIB_SNAPSHOT_LOCK", 0, 0, &umr_bitfield_default }, + { "CYCLIC_BUFFER_WRAP_COUNT", 8, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB[] = { + { "LPIB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[] = { + { "LPIB_TIMER_SNAPSHOT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL[] = { + { "INPUT_ACTIVITY", 0, 0, &umr_bitfield_default }, + { "CHANNEL_LAYOUT", 1, 2, &umr_bitfield_default }, + { "INPUT_ACTIVITY_UR_ENABLE", 4, 4, &umr_bitfield_default }, + { "INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE", 5, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME[] = { + { "CHANNEL_COUNT", 0, 2, &umr_bitfield_default }, + { "CHANNEL_ALLOCATION", 8, 15, &umr_bitfield_default }, + { "INFOFRAME_BYTE_5", 16, 23, &umr_bitfield_default }, + { "INFOFRAME_VALID", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = { + { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default }, + { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default }, + { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default }, + { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default }, + { "FORMAT_OVERRIDE", 4, 4, &umr_bitfield_default }, + { "STRIPE", 5, 5, &umr_bitfield_default }, + { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default }, + { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default }, + { "CONNECTION_LIST", 8, 8, &umr_bitfield_default }, + { "DIGITAL", 9, 9, &umr_bitfield_default }, + { "POWER_CONTROL", 10, 10, &umr_bitfield_default }, + { "LR_SWAP", 11, 11, &umr_bitfield_default }, + { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default }, + { "TYPE", 20, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT[] = { + { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default }, + { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default }, + { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default }, + { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default }, + { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default }, + { "STREAM_TYPE", 15, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID[] = { + { "CHANNEL_ID", 0, 3, &umr_bitfield_default }, + { "STREAM_ID", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER[] = { + { "DIGEN", 0, 0, &umr_bitfield_default }, + { "V", 1, 1, &umr_bitfield_default }, + { "VCFG", 2, 2, &umr_bitfield_default }, + { "PRE", 3, 3, &umr_bitfield_default }, + { "COPY", 4, 4, &umr_bitfield_default }, + { "NON_AUDIO", 5, 5, &umr_bitfield_default }, + { "PRO", 6, 6, &umr_bitfield_default }, + { "L", 7, 7, &umr_bitfield_default }, + { "CC", 8, 14, &umr_bitfield_default }, + { "KEEPALIVE", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS[] = { + { "STREAM_FORMATS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[] = { + { "AUDIO_RATE_CAPABILITIES", 0, 11, &umr_bitfield_default }, + { "AUDIO_BIT_CAPABILITIES", 16, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = { + { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default }, + { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default }, + { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default }, + { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default }, + { "STRIPE", 5, 5, &umr_bitfield_default }, + { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default }, + { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default }, + { "CONNECTION_LIST", 8, 8, &umr_bitfield_default }, + { "DIGITAL", 9, 9, &umr_bitfield_default }, + { "POWER_CONTROL", 10, 10, &umr_bitfield_default }, + { "LR_SWAP", 11, 11, &umr_bitfield_default }, + { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default }, + { "TYPE", 20, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES[] = { + { "IMPEDANCE_SENSE_CAPABLE", 0, 0, &umr_bitfield_default }, + { "TRIGGER_REQUIRED", 1, 1, &umr_bitfield_default }, + { "JACK_DETECTION_CAPABILITY", 2, 2, &umr_bitfield_default }, + { "HEADPHONE_DRIVE_CAPABLE", 3, 3, &umr_bitfield_default }, + { "OUTPUT_CAPABLE", 4, 4, &umr_bitfield_default }, + { "INPUT_CAPABLE", 5, 5, &umr_bitfield_default }, + { "BALANCED_I_O_PINS", 6, 6, &umr_bitfield_default }, + { "HDMI", 7, 7, &umr_bitfield_default }, + { "VREF_CONTROL", 8, 15, &umr_bitfield_default }, + { "EAPD_CAPABLE", 16, 16, &umr_bitfield_default }, + { "DP", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE[] = { + { "TAG", 0, 5, &umr_bitfield_default }, + { "ENABLE", 7, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE[] = { + { "IMPEDANCE_SENSE", 0, 30, &umr_bitfield_default }, + { "PRESENCE_DETECT", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL[] = { + { "IN_ENABLE", 5, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE[] = { + { "MULTICHANNEL0_ENABLE", 0, 0, &umr_bitfield_default }, + { "MULTICHANNEL0_MUTE", 1, 1, &umr_bitfield_default }, + { "MULTICHANNEL0_CHANNEL_ID", 4, 7, &umr_bitfield_default }, + { "MULTICHANNEL1_ENABLE", 8, 8, &umr_bitfield_default }, + { "MULTICHANNEL1_MUTE", 9, 9, &umr_bitfield_default }, + { "MULTICHANNEL1_CHANNEL_ID", 12, 15, &umr_bitfield_default }, + { "MULTICHANNEL2_ENABLE", 16, 16, &umr_bitfield_default }, + { "MULTICHANNEL2_MUTE", 17, 17, &umr_bitfield_default }, + { "MULTICHANNEL2_CHANNEL_ID", 20, 23, &umr_bitfield_default }, + { "MULTICHANNEL3_ENABLE", 24, 24, &umr_bitfield_default }, + { "MULTICHANNEL3_MUTE", 25, 25, &umr_bitfield_default }, + { "MULTICHANNEL3_CHANNEL_ID", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2[] = { + { "MULTICHANNEL4_ENABLE", 0, 0, &umr_bitfield_default }, + { "MULTICHANNEL4_MUTE", 1, 1, &umr_bitfield_default }, + { "MULTICHANNEL4_CHANNEL_ID", 4, 7, &umr_bitfield_default }, + { "MULTICHANNEL5_ENABLE", 8, 8, &umr_bitfield_default }, + { "MULTICHANNEL5_MUTE", 9, 9, &umr_bitfield_default }, + { "MULTICHANNEL5_CHANNEL_ID", 12, 15, &umr_bitfield_default }, + { "MULTICHANNEL6_ENABLE", 16, 16, &umr_bitfield_default }, + { "MULTICHANNEL6_MUTE", 17, 17, &umr_bitfield_default }, + { "MULTICHANNEL6_CHANNEL_ID", 20, 23, &umr_bitfield_default }, + { "MULTICHANNEL7_ENABLE", 24, 24, &umr_bitfield_default }, + { "MULTICHANNEL7_MUTE", 25, 25, &umr_bitfield_default }, + { "MULTICHANNEL7_CHANNEL_ID", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR[] = { + { "HBR_CAPABLE", 0, 0, &umr_bitfield_default }, + { "HBR_ENABLE", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION[] = { + { "CHANNEL_ALLOCATION", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL[] = { + { "CLOCK_GATING_DISABLE", 0, 0, &umr_bitfield_default }, + { "CLOCK_ON_STATE", 4, 4, &umr_bitfield_default }, + { "AUDIO_ENABLED", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[] = { + { "UNSOLICITED_RESPONSE_PAYLOAD", 0, 25, &umr_bitfield_default }, + { "UNSOLICITED_RESPONSE_FORCE", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[] = { + { "SEQUENCE", 0, 3, &umr_bitfield_default }, + { "DEFAULT_ASSOCIATION", 4, 7, &umr_bitfield_default }, + { "MISC", 8, 11, &umr_bitfield_default }, + { "COLOR", 12, 15, &umr_bitfield_default }, + { "CONNECTION_TYPE", 16, 19, &umr_bitfield_default }, + { "DEFAULT_DEVICE", 20, 23, &umr_bitfield_default }, + { "LOCATION", 24, 29, &umr_bitfield_default }, + { "PORT_CONNECTIVITY", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[] = { + { "LPIB_SNAPSHOT_LOCK", 0, 0, &umr_bitfield_default }, + { "CYCLIC_BUFFER_WRAP_COUNT", 8, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB[] = { + { "LPIB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[] = { + { "LPIB_TIMER_SNAPSHOT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL[] = { + { "INPUT_ACTIVITY", 0, 0, &umr_bitfield_default }, + { "CHANNEL_LAYOUT", 1, 2, &umr_bitfield_default }, + { "INPUT_ACTIVITY_UR_ENABLE", 4, 4, &umr_bitfield_default }, + { "INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE", 5, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME[] = { + { "CHANNEL_COUNT", 0, 2, &umr_bitfield_default }, + { "CHANNEL_ALLOCATION", 8, 15, &umr_bitfield_default }, + { "INFOFRAME_BYTE_5", 16, 23, &umr_bitfield_default }, + { "INFOFRAME_VALID", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = { + { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default }, + { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default }, + { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default }, + { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default }, + { "FORMAT_OVERRIDE", 4, 4, &umr_bitfield_default }, + { "STRIPE", 5, 5, &umr_bitfield_default }, + { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default }, + { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default }, + { "CONNECTION_LIST", 8, 8, &umr_bitfield_default }, + { "DIGITAL", 9, 9, &umr_bitfield_default }, + { "POWER_CONTROL", 10, 10, &umr_bitfield_default }, + { "LR_SWAP", 11, 11, &umr_bitfield_default }, + { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default }, + { "TYPE", 20, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT[] = { + { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default }, + { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default }, + { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default }, + { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default }, + { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default }, + { "STREAM_TYPE", 15, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID[] = { + { "CHANNEL_ID", 0, 3, &umr_bitfield_default }, + { "STREAM_ID", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER[] = { + { "DIGEN", 0, 0, &umr_bitfield_default }, + { "V", 1, 1, &umr_bitfield_default }, + { "VCFG", 2, 2, &umr_bitfield_default }, + { "PRE", 3, 3, &umr_bitfield_default }, + { "COPY", 4, 4, &umr_bitfield_default }, + { "NON_AUDIO", 5, 5, &umr_bitfield_default }, + { "PRO", 6, 6, &umr_bitfield_default }, + { "L", 7, 7, &umr_bitfield_default }, + { "CC", 8, 14, &umr_bitfield_default }, + { "KEEPALIVE", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS[] = { + { "STREAM_FORMATS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[] = { + { "AUDIO_RATE_CAPABILITIES", 0, 11, &umr_bitfield_default }, + { "AUDIO_BIT_CAPABILITIES", 16, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = { + { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default }, + { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default }, + { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default }, + { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default }, + { "STRIPE", 5, 5, &umr_bitfield_default }, + { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default }, + { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default }, + { "CONNECTION_LIST", 8, 8, &umr_bitfield_default }, + { "DIGITAL", 9, 9, &umr_bitfield_default }, + { "POWER_CONTROL", 10, 10, &umr_bitfield_default }, + { "LR_SWAP", 11, 11, &umr_bitfield_default }, + { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default }, + { "TYPE", 20, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES[] = { + { "IMPEDANCE_SENSE_CAPABLE", 0, 0, &umr_bitfield_default }, + { "TRIGGER_REQUIRED", 1, 1, &umr_bitfield_default }, + { "JACK_DETECTION_CAPABILITY", 2, 2, &umr_bitfield_default }, + { "HEADPHONE_DRIVE_CAPABLE", 3, 3, &umr_bitfield_default }, + { "OUTPUT_CAPABLE", 4, 4, &umr_bitfield_default }, + { "INPUT_CAPABLE", 5, 5, &umr_bitfield_default }, + { "BALANCED_I_O_PINS", 6, 6, &umr_bitfield_default }, + { "HDMI", 7, 7, &umr_bitfield_default }, + { "VREF_CONTROL", 8, 15, &umr_bitfield_default }, + { "EAPD_CAPABLE", 16, 16, &umr_bitfield_default }, + { "DP", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE[] = { + { "TAG", 0, 5, &umr_bitfield_default }, + { "ENABLE", 7, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE[] = { + { "IMPEDANCE_SENSE", 0, 30, &umr_bitfield_default }, + { "PRESENCE_DETECT", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL[] = { + { "IN_ENABLE", 5, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE[] = { + { "MULTICHANNEL0_ENABLE", 0, 0, &umr_bitfield_default }, + { "MULTICHANNEL0_MUTE", 1, 1, &umr_bitfield_default }, + { "MULTICHANNEL0_CHANNEL_ID", 4, 7, &umr_bitfield_default }, + { "MULTICHANNEL1_ENABLE", 8, 8, &umr_bitfield_default }, + { "MULTICHANNEL1_MUTE", 9, 9, &umr_bitfield_default }, + { "MULTICHANNEL1_CHANNEL_ID", 12, 15, &umr_bitfield_default }, + { "MULTICHANNEL2_ENABLE", 16, 16, &umr_bitfield_default }, + { "MULTICHANNEL2_MUTE", 17, 17, &umr_bitfield_default }, + { "MULTICHANNEL2_CHANNEL_ID", 20, 23, &umr_bitfield_default }, + { "MULTICHANNEL3_ENABLE", 24, 24, &umr_bitfield_default }, + { "MULTICHANNEL3_MUTE", 25, 25, &umr_bitfield_default }, + { "MULTICHANNEL3_CHANNEL_ID", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2[] = { + { "MULTICHANNEL4_ENABLE", 0, 0, &umr_bitfield_default }, + { "MULTICHANNEL4_MUTE", 1, 1, &umr_bitfield_default }, + { "MULTICHANNEL4_CHANNEL_ID", 4, 7, &umr_bitfield_default }, + { "MULTICHANNEL5_ENABLE", 8, 8, &umr_bitfield_default }, + { "MULTICHANNEL5_MUTE", 9, 9, &umr_bitfield_default }, + { "MULTICHANNEL5_CHANNEL_ID", 12, 15, &umr_bitfield_default }, + { "MULTICHANNEL6_ENABLE", 16, 16, &umr_bitfield_default }, + { "MULTICHANNEL6_MUTE", 17, 17, &umr_bitfield_default }, + { "MULTICHANNEL6_CHANNEL_ID", 20, 23, &umr_bitfield_default }, + { "MULTICHANNEL7_ENABLE", 24, 24, &umr_bitfield_default }, + { "MULTICHANNEL7_MUTE", 25, 25, &umr_bitfield_default }, + { "MULTICHANNEL7_CHANNEL_ID", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR[] = { + { "HBR_CAPABLE", 0, 0, &umr_bitfield_default }, + { "HBR_ENABLE", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION[] = { + { "CHANNEL_ALLOCATION", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL[] = { + { "CLOCK_GATING_DISABLE", 0, 0, &umr_bitfield_default }, + { "CLOCK_ON_STATE", 4, 4, &umr_bitfield_default }, + { "AUDIO_ENABLED", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[] = { + { "UNSOLICITED_RESPONSE_PAYLOAD", 0, 25, &umr_bitfield_default }, + { "UNSOLICITED_RESPONSE_FORCE", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[] = { + { "SEQUENCE", 0, 3, &umr_bitfield_default }, + { "DEFAULT_ASSOCIATION", 4, 7, &umr_bitfield_default }, + { "MISC", 8, 11, &umr_bitfield_default }, + { "COLOR", 12, 15, &umr_bitfield_default }, + { "CONNECTION_TYPE", 16, 19, &umr_bitfield_default }, + { "DEFAULT_DEVICE", 20, 23, &umr_bitfield_default }, + { "LOCATION", 24, 29, &umr_bitfield_default }, + { "PORT_CONNECTIVITY", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[] = { + { "LPIB_SNAPSHOT_LOCK", 0, 0, &umr_bitfield_default }, + { "CYCLIC_BUFFER_WRAP_COUNT", 8, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB[] = { + { "LPIB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[] = { + { "LPIB_TIMER_SNAPSHOT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL[] = { + { "INPUT_ACTIVITY", 0, 0, &umr_bitfield_default }, + { "CHANNEL_LAYOUT", 1, 2, &umr_bitfield_default }, + { "INPUT_ACTIVITY_UR_ENABLE", 4, 4, &umr_bitfield_default }, + { "INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE", 5, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME[] = { + { "CHANNEL_COUNT", 0, 2, &umr_bitfield_default }, + { "CHANNEL_ALLOCATION", 8, 15, &umr_bitfield_default }, + { "INFOFRAME_BYTE_5", 16, 23, &umr_bitfield_default }, + { "INFOFRAME_VALID", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = { + { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default }, + { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default }, + { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default }, + { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default }, + { "FORMAT_OVERRIDE", 4, 4, &umr_bitfield_default }, + { "STRIPE", 5, 5, &umr_bitfield_default }, + { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default }, + { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default }, + { "CONNECTION_LIST", 8, 8, &umr_bitfield_default }, + { "DIGITAL", 9, 9, &umr_bitfield_default }, + { "POWER_CONTROL", 10, 10, &umr_bitfield_default }, + { "LR_SWAP", 11, 11, &umr_bitfield_default }, + { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default }, + { "TYPE", 20, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT[] = { + { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default }, + { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default }, + { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default }, + { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default }, + { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default }, + { "STREAM_TYPE", 15, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID[] = { + { "CHANNEL_ID", 0, 3, &umr_bitfield_default }, + { "STREAM_ID", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER[] = { + { "DIGEN", 0, 0, &umr_bitfield_default }, + { "V", 1, 1, &umr_bitfield_default }, + { "VCFG", 2, 2, &umr_bitfield_default }, + { "PRE", 3, 3, &umr_bitfield_default }, + { "COPY", 4, 4, &umr_bitfield_default }, + { "NON_AUDIO", 5, 5, &umr_bitfield_default }, + { "PRO", 6, 6, &umr_bitfield_default }, + { "L", 7, 7, &umr_bitfield_default }, + { "CC", 8, 14, &umr_bitfield_default }, + { "KEEPALIVE", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS[] = { + { "STREAM_FORMATS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[] = { + { "AUDIO_RATE_CAPABILITIES", 0, 11, &umr_bitfield_default }, + { "AUDIO_BIT_CAPABILITIES", 16, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = { + { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default }, + { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default }, + { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default }, + { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default }, + { "STRIPE", 5, 5, &umr_bitfield_default }, + { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default }, + { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default }, + { "CONNECTION_LIST", 8, 8, &umr_bitfield_default }, + { "DIGITAL", 9, 9, &umr_bitfield_default }, + { "POWER_CONTROL", 10, 10, &umr_bitfield_default }, + { "LR_SWAP", 11, 11, &umr_bitfield_default }, + { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default }, + { "TYPE", 20, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES[] = { + { "IMPEDANCE_SENSE_CAPABLE", 0, 0, &umr_bitfield_default }, + { "TRIGGER_REQUIRED", 1, 1, &umr_bitfield_default }, + { "JACK_DETECTION_CAPABILITY", 2, 2, &umr_bitfield_default }, + { "HEADPHONE_DRIVE_CAPABLE", 3, 3, &umr_bitfield_default }, + { "OUTPUT_CAPABLE", 4, 4, &umr_bitfield_default }, + { "INPUT_CAPABLE", 5, 5, &umr_bitfield_default }, + { "BALANCED_I_O_PINS", 6, 6, &umr_bitfield_default }, + { "HDMI", 7, 7, &umr_bitfield_default }, + { "VREF_CONTROL", 8, 15, &umr_bitfield_default }, + { "EAPD_CAPABLE", 16, 16, &umr_bitfield_default }, + { "DP", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE[] = { + { "TAG", 0, 5, &umr_bitfield_default }, + { "ENABLE", 7, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE[] = { + { "IMPEDANCE_SENSE", 0, 30, &umr_bitfield_default }, + { "PRESENCE_DETECT", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL[] = { + { "IN_ENABLE", 5, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE[] = { + { "MULTICHANNEL0_ENABLE", 0, 0, &umr_bitfield_default }, + { "MULTICHANNEL0_MUTE", 1, 1, &umr_bitfield_default }, + { "MULTICHANNEL0_CHANNEL_ID", 4, 7, &umr_bitfield_default }, + { "MULTICHANNEL1_ENABLE", 8, 8, &umr_bitfield_default }, + { "MULTICHANNEL1_MUTE", 9, 9, &umr_bitfield_default }, + { "MULTICHANNEL1_CHANNEL_ID", 12, 15, &umr_bitfield_default }, + { "MULTICHANNEL2_ENABLE", 16, 16, &umr_bitfield_default }, + { "MULTICHANNEL2_MUTE", 17, 17, &umr_bitfield_default }, + { "MULTICHANNEL2_CHANNEL_ID", 20, 23, &umr_bitfield_default }, + { "MULTICHANNEL3_ENABLE", 24, 24, &umr_bitfield_default }, + { "MULTICHANNEL3_MUTE", 25, 25, &umr_bitfield_default }, + { "MULTICHANNEL3_CHANNEL_ID", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2[] = { + { "MULTICHANNEL4_ENABLE", 0, 0, &umr_bitfield_default }, + { "MULTICHANNEL4_MUTE", 1, 1, &umr_bitfield_default }, + { "MULTICHANNEL4_CHANNEL_ID", 4, 7, &umr_bitfield_default }, + { "MULTICHANNEL5_ENABLE", 8, 8, &umr_bitfield_default }, + { "MULTICHANNEL5_MUTE", 9, 9, &umr_bitfield_default }, + { "MULTICHANNEL5_CHANNEL_ID", 12, 15, &umr_bitfield_default }, + { "MULTICHANNEL6_ENABLE", 16, 16, &umr_bitfield_default }, + { "MULTICHANNEL6_MUTE", 17, 17, &umr_bitfield_default }, + { "MULTICHANNEL6_CHANNEL_ID", 20, 23, &umr_bitfield_default }, + { "MULTICHANNEL7_ENABLE", 24, 24, &umr_bitfield_default }, + { "MULTICHANNEL7_MUTE", 25, 25, &umr_bitfield_default }, + { "MULTICHANNEL7_CHANNEL_ID", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR[] = { + { "HBR_CAPABLE", 0, 0, &umr_bitfield_default }, + { "HBR_ENABLE", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION[] = { + { "CHANNEL_ALLOCATION", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL[] = { + { "CLOCK_GATING_DISABLE", 0, 0, &umr_bitfield_default }, + { "CLOCK_ON_STATE", 4, 4, &umr_bitfield_default }, + { "AUDIO_ENABLED", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[] = { + { "UNSOLICITED_RESPONSE_PAYLOAD", 0, 25, &umr_bitfield_default }, + { "UNSOLICITED_RESPONSE_FORCE", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[] = { + { "SEQUENCE", 0, 3, &umr_bitfield_default }, + { "DEFAULT_ASSOCIATION", 4, 7, &umr_bitfield_default }, + { "MISC", 8, 11, &umr_bitfield_default }, + { "COLOR", 12, 15, &umr_bitfield_default }, + { "CONNECTION_TYPE", 16, 19, &umr_bitfield_default }, + { "DEFAULT_DEVICE", 20, 23, &umr_bitfield_default }, + { "LOCATION", 24, 29, &umr_bitfield_default }, + { "PORT_CONNECTIVITY", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[] = { + { "LPIB_SNAPSHOT_LOCK", 0, 0, &umr_bitfield_default }, + { "CYCLIC_BUFFER_WRAP_COUNT", 8, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB[] = { + { "LPIB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[] = { + { "LPIB_TIMER_SNAPSHOT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL[] = { + { "INPUT_ACTIVITY", 0, 0, &umr_bitfield_default }, + { "CHANNEL_LAYOUT", 1, 2, &umr_bitfield_default }, + { "INPUT_ACTIVITY_UR_ENABLE", 4, 4, &umr_bitfield_default }, + { "INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE", 5, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME[] = { + { "CHANNEL_COUNT", 0, 2, &umr_bitfield_default }, + { "CHANNEL_ALLOCATION", 8, 15, &umr_bitfield_default }, + { "INFOFRAME_BYTE_5", 16, 23, &umr_bitfield_default }, + { "INFOFRAME_VALID", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = { + { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default }, + { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default }, + { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default }, + { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default }, + { "FORMAT_OVERRIDE", 4, 4, &umr_bitfield_default }, + { "STRIPE", 5, 5, &umr_bitfield_default }, + { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default }, + { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default }, + { "CONNECTION_LIST", 8, 8, &umr_bitfield_default }, + { "DIGITAL", 9, 9, &umr_bitfield_default }, + { "POWER_CONTROL", 10, 10, &umr_bitfield_default }, + { "LR_SWAP", 11, 11, &umr_bitfield_default }, + { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default }, + { "TYPE", 20, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT[] = { + { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default }, + { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default }, + { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default }, + { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default }, + { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default }, + { "STREAM_TYPE", 15, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID[] = { + { "CHANNEL_ID", 0, 3, &umr_bitfield_default }, + { "STREAM_ID", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER[] = { + { "DIGEN", 0, 0, &umr_bitfield_default }, + { "V", 1, 1, &umr_bitfield_default }, + { "VCFG", 2, 2, &umr_bitfield_default }, + { "PRE", 3, 3, &umr_bitfield_default }, + { "COPY", 4, 4, &umr_bitfield_default }, + { "NON_AUDIO", 5, 5, &umr_bitfield_default }, + { "PRO", 6, 6, &umr_bitfield_default }, + { "L", 7, 7, &umr_bitfield_default }, + { "CC", 8, 14, &umr_bitfield_default }, + { "KEEPALIVE", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS[] = { + { "STREAM_FORMATS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[] = { + { "AUDIO_RATE_CAPABILITIES", 0, 11, &umr_bitfield_default }, + { "AUDIO_BIT_CAPABILITIES", 16, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = { + { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default }, + { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default }, + { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default }, + { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default }, + { "STRIPE", 5, 5, &umr_bitfield_default }, + { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default }, + { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default }, + { "CONNECTION_LIST", 8, 8, &umr_bitfield_default }, + { "DIGITAL", 9, 9, &umr_bitfield_default }, + { "POWER_CONTROL", 10, 10, &umr_bitfield_default }, + { "LR_SWAP", 11, 11, &umr_bitfield_default }, + { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default }, + { "TYPE", 20, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES[] = { + { "IMPEDANCE_SENSE_CAPABLE", 0, 0, &umr_bitfield_default }, + { "TRIGGER_REQUIRED", 1, 1, &umr_bitfield_default }, + { "JACK_DETECTION_CAPABILITY", 2, 2, &umr_bitfield_default }, + { "HEADPHONE_DRIVE_CAPABLE", 3, 3, &umr_bitfield_default }, + { "OUTPUT_CAPABLE", 4, 4, &umr_bitfield_default }, + { "INPUT_CAPABLE", 5, 5, &umr_bitfield_default }, + { "BALANCED_I_O_PINS", 6, 6, &umr_bitfield_default }, + { "HDMI", 7, 7, &umr_bitfield_default }, + { "VREF_CONTROL", 8, 15, &umr_bitfield_default }, + { "EAPD_CAPABLE", 16, 16, &umr_bitfield_default }, + { "DP", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE[] = { + { "TAG", 0, 5, &umr_bitfield_default }, + { "ENABLE", 7, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE[] = { + { "IMPEDANCE_SENSE", 0, 30, &umr_bitfield_default }, + { "PRESENCE_DETECT", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL[] = { + { "IN_ENABLE", 5, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE[] = { + { "MULTICHANNEL0_ENABLE", 0, 0, &umr_bitfield_default }, + { "MULTICHANNEL0_MUTE", 1, 1, &umr_bitfield_default }, + { "MULTICHANNEL0_CHANNEL_ID", 4, 7, &umr_bitfield_default }, + { "MULTICHANNEL1_ENABLE", 8, 8, &umr_bitfield_default }, + { "MULTICHANNEL1_MUTE", 9, 9, &umr_bitfield_default }, + { "MULTICHANNEL1_CHANNEL_ID", 12, 15, &umr_bitfield_default }, + { "MULTICHANNEL2_ENABLE", 16, 16, &umr_bitfield_default }, + { "MULTICHANNEL2_MUTE", 17, 17, &umr_bitfield_default }, + { "MULTICHANNEL2_CHANNEL_ID", 20, 23, &umr_bitfield_default }, + { "MULTICHANNEL3_ENABLE", 24, 24, &umr_bitfield_default }, + { "MULTICHANNEL3_MUTE", 25, 25, &umr_bitfield_default }, + { "MULTICHANNEL3_CHANNEL_ID", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2[] = { + { "MULTICHANNEL4_ENABLE", 0, 0, &umr_bitfield_default }, + { "MULTICHANNEL4_MUTE", 1, 1, &umr_bitfield_default }, + { "MULTICHANNEL4_CHANNEL_ID", 4, 7, &umr_bitfield_default }, + { "MULTICHANNEL5_ENABLE", 8, 8, &umr_bitfield_default }, + { "MULTICHANNEL5_MUTE", 9, 9, &umr_bitfield_default }, + { "MULTICHANNEL5_CHANNEL_ID", 12, 15, &umr_bitfield_default }, + { "MULTICHANNEL6_ENABLE", 16, 16, &umr_bitfield_default }, + { "MULTICHANNEL6_MUTE", 17, 17, &umr_bitfield_default }, + { "MULTICHANNEL6_CHANNEL_ID", 20, 23, &umr_bitfield_default }, + { "MULTICHANNEL7_ENABLE", 24, 24, &umr_bitfield_default }, + { "MULTICHANNEL7_MUTE", 25, 25, &umr_bitfield_default }, + { "MULTICHANNEL7_CHANNEL_ID", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR[] = { + { "HBR_CAPABLE", 0, 0, &umr_bitfield_default }, + { "HBR_ENABLE", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION[] = { + { "CHANNEL_ALLOCATION", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL[] = { + { "CLOCK_GATING_DISABLE", 0, 0, &umr_bitfield_default }, + { "CLOCK_ON_STATE", 4, 4, &umr_bitfield_default }, + { "AUDIO_ENABLED", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[] = { + { "UNSOLICITED_RESPONSE_PAYLOAD", 0, 25, &umr_bitfield_default }, + { "UNSOLICITED_RESPONSE_FORCE", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[] = { + { "SEQUENCE", 0, 3, &umr_bitfield_default }, + { "DEFAULT_ASSOCIATION", 4, 7, &umr_bitfield_default }, + { "MISC", 8, 11, &umr_bitfield_default }, + { "COLOR", 12, 15, &umr_bitfield_default }, + { "CONNECTION_TYPE", 16, 19, &umr_bitfield_default }, + { "DEFAULT_DEVICE", 20, 23, &umr_bitfield_default }, + { "LOCATION", 24, 29, &umr_bitfield_default }, + { "PORT_CONNECTIVITY", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[] = { + { "LPIB_SNAPSHOT_LOCK", 0, 0, &umr_bitfield_default }, + { "CYCLIC_BUFFER_WRAP_COUNT", 8, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB[] = { + { "LPIB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[] = { + { "LPIB_TIMER_SNAPSHOT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL[] = { + { "INPUT_ACTIVITY", 0, 0, &umr_bitfield_default }, + { "CHANNEL_LAYOUT", 1, 2, &umr_bitfield_default }, + { "INPUT_ACTIVITY_UR_ENABLE", 4, 4, &umr_bitfield_default }, + { "INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE", 5, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME[] = { + { "CHANNEL_COUNT", 0, 2, &umr_bitfield_default }, + { "CHANNEL_ALLOCATION", 8, 15, &umr_bitfield_default }, + { "INFOFRAME_BYTE_5", 16, 23, &umr_bitfield_default }, + { "INFOFRAME_VALID", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = { + { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default }, + { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default }, + { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default }, + { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default }, + { "FORMAT_OVERRIDE", 4, 4, &umr_bitfield_default }, + { "STRIPE", 5, 5, &umr_bitfield_default }, + { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default }, + { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default }, + { "CONNECTION_LIST", 8, 8, &umr_bitfield_default }, + { "DIGITAL", 9, 9, &umr_bitfield_default }, + { "POWER_CONTROL", 10, 10, &umr_bitfield_default }, + { "LR_SWAP", 11, 11, &umr_bitfield_default }, + { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default }, + { "TYPE", 20, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT[] = { + { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default }, + { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default }, + { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default }, + { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default }, + { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default }, + { "STREAM_TYPE", 15, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID[] = { + { "CHANNEL_ID", 0, 3, &umr_bitfield_default }, + { "STREAM_ID", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER[] = { + { "DIGEN", 0, 0, &umr_bitfield_default }, + { "V", 1, 1, &umr_bitfield_default }, + { "VCFG", 2, 2, &umr_bitfield_default }, + { "PRE", 3, 3, &umr_bitfield_default }, + { "COPY", 4, 4, &umr_bitfield_default }, + { "NON_AUDIO", 5, 5, &umr_bitfield_default }, + { "PRO", 6, 6, &umr_bitfield_default }, + { "L", 7, 7, &umr_bitfield_default }, + { "CC", 8, 14, &umr_bitfield_default }, + { "KEEPALIVE", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS[] = { + { "STREAM_FORMATS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[] = { + { "AUDIO_RATE_CAPABILITIES", 0, 11, &umr_bitfield_default }, + { "AUDIO_BIT_CAPABILITIES", 16, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = { + { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default }, + { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default }, + { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default }, + { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default }, + { "STRIPE", 5, 5, &umr_bitfield_default }, + { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default }, + { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default }, + { "CONNECTION_LIST", 8, 8, &umr_bitfield_default }, + { "DIGITAL", 9, 9, &umr_bitfield_default }, + { "POWER_CONTROL", 10, 10, &umr_bitfield_default }, + { "LR_SWAP", 11, 11, &umr_bitfield_default }, + { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default }, + { "TYPE", 20, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES[] = { + { "IMPEDANCE_SENSE_CAPABLE", 0, 0, &umr_bitfield_default }, + { "TRIGGER_REQUIRED", 1, 1, &umr_bitfield_default }, + { "JACK_DETECTION_CAPABILITY", 2, 2, &umr_bitfield_default }, + { "HEADPHONE_DRIVE_CAPABLE", 3, 3, &umr_bitfield_default }, + { "OUTPUT_CAPABLE", 4, 4, &umr_bitfield_default }, + { "INPUT_CAPABLE", 5, 5, &umr_bitfield_default }, + { "BALANCED_I_O_PINS", 6, 6, &umr_bitfield_default }, + { "HDMI", 7, 7, &umr_bitfield_default }, + { "VREF_CONTROL", 8, 15, &umr_bitfield_default }, + { "EAPD_CAPABLE", 16, 16, &umr_bitfield_default }, + { "DP", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE[] = { + { "TAG", 0, 5, &umr_bitfield_default }, + { "ENABLE", 7, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE[] = { + { "IMPEDANCE_SENSE", 0, 30, &umr_bitfield_default }, + { "PRESENCE_DETECT", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL[] = { + { "IN_ENABLE", 5, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE[] = { + { "MULTICHANNEL0_ENABLE", 0, 0, &umr_bitfield_default }, + { "MULTICHANNEL0_MUTE", 1, 1, &umr_bitfield_default }, + { "MULTICHANNEL0_CHANNEL_ID", 4, 7, &umr_bitfield_default }, + { "MULTICHANNEL1_ENABLE", 8, 8, &umr_bitfield_default }, + { "MULTICHANNEL1_MUTE", 9, 9, &umr_bitfield_default }, + { "MULTICHANNEL1_CHANNEL_ID", 12, 15, &umr_bitfield_default }, + { "MULTICHANNEL2_ENABLE", 16, 16, &umr_bitfield_default }, + { "MULTICHANNEL2_MUTE", 17, 17, &umr_bitfield_default }, + { "MULTICHANNEL2_CHANNEL_ID", 20, 23, &umr_bitfield_default }, + { "MULTICHANNEL3_ENABLE", 24, 24, &umr_bitfield_default }, + { "MULTICHANNEL3_MUTE", 25, 25, &umr_bitfield_default }, + { "MULTICHANNEL3_CHANNEL_ID", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2[] = { + { "MULTICHANNEL4_ENABLE", 0, 0, &umr_bitfield_default }, + { "MULTICHANNEL4_MUTE", 1, 1, &umr_bitfield_default }, + { "MULTICHANNEL4_CHANNEL_ID", 4, 7, &umr_bitfield_default }, + { "MULTICHANNEL5_ENABLE", 8, 8, &umr_bitfield_default }, + { "MULTICHANNEL5_MUTE", 9, 9, &umr_bitfield_default }, + { "MULTICHANNEL5_CHANNEL_ID", 12, 15, &umr_bitfield_default }, + { "MULTICHANNEL6_ENABLE", 16, 16, &umr_bitfield_default }, + { "MULTICHANNEL6_MUTE", 17, 17, &umr_bitfield_default }, + { "MULTICHANNEL6_CHANNEL_ID", 20, 23, &umr_bitfield_default }, + { "MULTICHANNEL7_ENABLE", 24, 24, &umr_bitfield_default }, + { "MULTICHANNEL7_MUTE", 25, 25, &umr_bitfield_default }, + { "MULTICHANNEL7_CHANNEL_ID", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR[] = { + { "HBR_CAPABLE", 0, 0, &umr_bitfield_default }, + { "HBR_ENABLE", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION[] = { + { "CHANNEL_ALLOCATION", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL[] = { + { "CLOCK_GATING_DISABLE", 0, 0, &umr_bitfield_default }, + { "CLOCK_ON_STATE", 4, 4, &umr_bitfield_default }, + { "AUDIO_ENABLED", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[] = { + { "UNSOLICITED_RESPONSE_PAYLOAD", 0, 25, &umr_bitfield_default }, + { "UNSOLICITED_RESPONSE_FORCE", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[] = { + { "SEQUENCE", 0, 3, &umr_bitfield_default }, + { "DEFAULT_ASSOCIATION", 4, 7, &umr_bitfield_default }, + { "MISC", 8, 11, &umr_bitfield_default }, + { "COLOR", 12, 15, &umr_bitfield_default }, + { "CONNECTION_TYPE", 16, 19, &umr_bitfield_default }, + { "DEFAULT_DEVICE", 20, 23, &umr_bitfield_default }, + { "LOCATION", 24, 29, &umr_bitfield_default }, + { "PORT_CONNECTIVITY", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[] = { + { "LPIB_SNAPSHOT_LOCK", 0, 0, &umr_bitfield_default }, + { "CYCLIC_BUFFER_WRAP_COUNT", 8, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB[] = { + { "LPIB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[] = { + { "LPIB_TIMER_SNAPSHOT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL[] = { + { "INPUT_ACTIVITY", 0, 0, &umr_bitfield_default }, + { "CHANNEL_LAYOUT", 1, 2, &umr_bitfield_default }, + { "INPUT_ACTIVITY_UR_ENABLE", 4, 4, &umr_bitfield_default }, + { "INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE", 5, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME[] = { + { "CHANNEL_COUNT", 0, 2, &umr_bitfield_default }, + { "CHANNEL_ALLOCATION", 8, 15, &umr_bitfield_default }, + { "INFOFRAME_BYTE_5", 16, 23, &umr_bitfield_default }, + { "INFOFRAME_VALID", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = { + { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default }, + { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default }, + { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default }, + { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default }, + { "FORMAT_OVERRIDE", 4, 4, &umr_bitfield_default }, + { "STRIPE", 5, 5, &umr_bitfield_default }, + { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default }, + { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default }, + { "CONNECTION_LIST", 8, 8, &umr_bitfield_default }, + { "DIGITAL", 9, 9, &umr_bitfield_default }, + { "POWER_CONTROL", 10, 10, &umr_bitfield_default }, + { "LR_SWAP", 11, 11, &umr_bitfield_default }, + { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default }, + { "TYPE", 20, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT[] = { + { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default }, + { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default }, + { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default }, + { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default }, + { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default }, + { "STREAM_TYPE", 15, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID[] = { + { "CHANNEL_ID", 0, 3, &umr_bitfield_default }, + { "STREAM_ID", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER[] = { + { "DIGEN", 0, 0, &umr_bitfield_default }, + { "V", 1, 1, &umr_bitfield_default }, + { "VCFG", 2, 2, &umr_bitfield_default }, + { "PRE", 3, 3, &umr_bitfield_default }, + { "COPY", 4, 4, &umr_bitfield_default }, + { "NON_AUDIO", 5, 5, &umr_bitfield_default }, + { "PRO", 6, 6, &umr_bitfield_default }, + { "L", 7, 7, &umr_bitfield_default }, + { "CC", 8, 14, &umr_bitfield_default }, + { "KEEPALIVE", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS[] = { + { "STREAM_FORMATS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[] = { + { "AUDIO_RATE_CAPABILITIES", 0, 11, &umr_bitfield_default }, + { "AUDIO_BIT_CAPABILITIES", 16, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = { + { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default }, + { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default }, + { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default }, + { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default }, + { "STRIPE", 5, 5, &umr_bitfield_default }, + { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default }, + { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default }, + { "CONNECTION_LIST", 8, 8, &umr_bitfield_default }, + { "DIGITAL", 9, 9, &umr_bitfield_default }, + { "POWER_CONTROL", 10, 10, &umr_bitfield_default }, + { "LR_SWAP", 11, 11, &umr_bitfield_default }, + { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default }, + { "TYPE", 20, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES[] = { + { "IMPEDANCE_SENSE_CAPABLE", 0, 0, &umr_bitfield_default }, + { "TRIGGER_REQUIRED", 1, 1, &umr_bitfield_default }, + { "JACK_DETECTION_CAPABILITY", 2, 2, &umr_bitfield_default }, + { "HEADPHONE_DRIVE_CAPABLE", 3, 3, &umr_bitfield_default }, + { "OUTPUT_CAPABLE", 4, 4, &umr_bitfield_default }, + { "INPUT_CAPABLE", 5, 5, &umr_bitfield_default }, + { "BALANCED_I_O_PINS", 6, 6, &umr_bitfield_default }, + { "HDMI", 7, 7, &umr_bitfield_default }, + { "VREF_CONTROL", 8, 15, &umr_bitfield_default }, + { "EAPD_CAPABLE", 16, 16, &umr_bitfield_default }, + { "DP", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE[] = { + { "TAG", 0, 5, &umr_bitfield_default }, + { "ENABLE", 7, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE[] = { + { "IMPEDANCE_SENSE", 0, 30, &umr_bitfield_default }, + { "PRESENCE_DETECT", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL[] = { + { "IN_ENABLE", 5, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE[] = { + { "MULTICHANNEL0_ENABLE", 0, 0, &umr_bitfield_default }, + { "MULTICHANNEL0_MUTE", 1, 1, &umr_bitfield_default }, + { "MULTICHANNEL0_CHANNEL_ID", 4, 7, &umr_bitfield_default }, + { "MULTICHANNEL1_ENABLE", 8, 8, &umr_bitfield_default }, + { "MULTICHANNEL1_MUTE", 9, 9, &umr_bitfield_default }, + { "MULTICHANNEL1_CHANNEL_ID", 12, 15, &umr_bitfield_default }, + { "MULTICHANNEL2_ENABLE", 16, 16, &umr_bitfield_default }, + { "MULTICHANNEL2_MUTE", 17, 17, &umr_bitfield_default }, + { "MULTICHANNEL2_CHANNEL_ID", 20, 23, &umr_bitfield_default }, + { "MULTICHANNEL3_ENABLE", 24, 24, &umr_bitfield_default }, + { "MULTICHANNEL3_MUTE", 25, 25, &umr_bitfield_default }, + { "MULTICHANNEL3_CHANNEL_ID", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2[] = { + { "MULTICHANNEL4_ENABLE", 0, 0, &umr_bitfield_default }, + { "MULTICHANNEL4_MUTE", 1, 1, &umr_bitfield_default }, + { "MULTICHANNEL4_CHANNEL_ID", 4, 7, &umr_bitfield_default }, + { "MULTICHANNEL5_ENABLE", 8, 8, &umr_bitfield_default }, + { "MULTICHANNEL5_MUTE", 9, 9, &umr_bitfield_default }, + { "MULTICHANNEL5_CHANNEL_ID", 12, 15, &umr_bitfield_default }, + { "MULTICHANNEL6_ENABLE", 16, 16, &umr_bitfield_default }, + { "MULTICHANNEL6_MUTE", 17, 17, &umr_bitfield_default }, + { "MULTICHANNEL6_CHANNEL_ID", 20, 23, &umr_bitfield_default }, + { "MULTICHANNEL7_ENABLE", 24, 24, &umr_bitfield_default }, + { "MULTICHANNEL7_MUTE", 25, 25, &umr_bitfield_default }, + { "MULTICHANNEL7_CHANNEL_ID", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR[] = { + { "HBR_CAPABLE", 0, 0, &umr_bitfield_default }, + { "HBR_ENABLE", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION[] = { + { "CHANNEL_ALLOCATION", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL[] = { + { "CLOCK_GATING_DISABLE", 0, 0, &umr_bitfield_default }, + { "CLOCK_ON_STATE", 4, 4, &umr_bitfield_default }, + { "AUDIO_ENABLED", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[] = { + { "UNSOLICITED_RESPONSE_PAYLOAD", 0, 25, &umr_bitfield_default }, + { "UNSOLICITED_RESPONSE_FORCE", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[] = { + { "SEQUENCE", 0, 3, &umr_bitfield_default }, + { "DEFAULT_ASSOCIATION", 4, 7, &umr_bitfield_default }, + { "MISC", 8, 11, &umr_bitfield_default }, + { "COLOR", 12, 15, &umr_bitfield_default }, + { "CONNECTION_TYPE", 16, 19, &umr_bitfield_default }, + { "DEFAULT_DEVICE", 20, 23, &umr_bitfield_default }, + { "LOCATION", 24, 29, &umr_bitfield_default }, + { "PORT_CONNECTIVITY", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[] = { + { "LPIB_SNAPSHOT_LOCK", 0, 0, &umr_bitfield_default }, + { "CYCLIC_BUFFER_WRAP_COUNT", 8, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB[] = { + { "LPIB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[] = { + { "LPIB_TIMER_SNAPSHOT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL[] = { + { "INPUT_ACTIVITY", 0, 0, &umr_bitfield_default }, + { "CHANNEL_LAYOUT", 1, 2, &umr_bitfield_default }, + { "INPUT_ACTIVITY_UR_ENABLE", 4, 4, &umr_bitfield_default }, + { "INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE", 5, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME[] = { + { "CHANNEL_COUNT", 0, 2, &umr_bitfield_default }, + { "CHANNEL_ALLOCATION", 8, 15, &umr_bitfield_default }, + { "INFOFRAME_BYTE_5", 16, 23, &umr_bitfield_default }, + { "INFOFRAME_VALID", 31, 31, &umr_bitfield_default }, +}; diff --git a/src/lib/ip/dcn10_regs.i b/src/lib/ip/dcn10_regs.i new file mode 100644 index 0000000..ccbece4 --- /dev/null +++ b/src/lib/ip/dcn10_regs.i @@ -0,0 +1,6967 @@ + { "mmVGA_MEM_WRITE_PAGE_ADDR", REG_MMIO, 0x0000, 0, &mmVGA_MEM_WRITE_PAGE_ADDR[0], sizeof(mmVGA_MEM_WRITE_PAGE_ADDR)/sizeof(mmVGA_MEM_WRITE_PAGE_ADDR[0]), 0, 0 }, + { "mmVGA_MEM_READ_PAGE_ADDR", REG_MMIO, 0x0001, 0, &mmVGA_MEM_READ_PAGE_ADDR[0], sizeof(mmVGA_MEM_READ_PAGE_ADDR)/sizeof(mmVGA_MEM_READ_PAGE_ADDR[0]), 0, 0 }, + { "mmCRTC8_IDX", REG_MMIO, 0x002d, 1, &mmCRTC8_IDX[0], sizeof(mmCRTC8_IDX)/sizeof(mmCRTC8_IDX[0]), 0, 0 }, + { "mmCRTC8_DATA", REG_MMIO, 0x002d, 1, &mmCRTC8_DATA[0], sizeof(mmCRTC8_DATA)/sizeof(mmCRTC8_DATA[0]), 0, 0 }, + { "mmGENFC_WT", REG_MMIO, 0x002e, 1, &mmGENFC_WT[0], sizeof(mmGENFC_WT)/sizeof(mmGENFC_WT[0]), 0, 0 }, + { "mmGENS1", REG_MMIO, 0x002e, 1, &mmGENS1[0], sizeof(mmGENS1)/sizeof(mmGENS1[0]), 0, 0 }, + { "mmATTRDW", REG_MMIO, 0x0030, 1, &mmATTRDW[0], sizeof(mmATTRDW)/sizeof(mmATTRDW[0]), 0, 0 }, + { "mmATTRX", REG_MMIO, 0x0030, 1, &mmATTRX[0], sizeof(mmATTRX)/sizeof(mmATTRX[0]), 0, 0 }, + { "mmATTRDR", REG_MMIO, 0x0030, 1, &mmATTRDR[0], sizeof(mmATTRDR)/sizeof(mmATTRDR[0]), 0, 0 }, + { "mmGENMO_WT", REG_MMIO, 0x0030, 1, &mmGENMO_WT[0], sizeof(mmGENMO_WT)/sizeof(mmGENMO_WT[0]), 0, 0 }, + { "mmGENS0", REG_MMIO, 0x0030, 1, &mmGENS0[0], sizeof(mmGENS0)/sizeof(mmGENS0[0]), 0, 0 }, + { "mmGENENB", REG_MMIO, 0x0030, 1, &mmGENENB[0], sizeof(mmGENENB)/sizeof(mmGENENB[0]), 0, 0 }, + { "mmSEQ8_IDX", REG_MMIO, 0x0031, 1, &mmSEQ8_IDX[0], sizeof(mmSEQ8_IDX)/sizeof(mmSEQ8_IDX[0]), 0, 0 }, + { "mmSEQ8_DATA", REG_MMIO, 0x0031, 1, &mmSEQ8_DATA[0], sizeof(mmSEQ8_DATA)/sizeof(mmSEQ8_DATA[0]), 0, 0 }, + { "mmDAC_MASK", REG_MMIO, 0x0031, 1, &mmDAC_MASK[0], sizeof(mmDAC_MASK)/sizeof(mmDAC_MASK[0]), 0, 0 }, + { "mmDAC_R_INDEX", REG_MMIO, 0x0031, 1, &mmDAC_R_INDEX[0], sizeof(mmDAC_R_INDEX)/sizeof(mmDAC_R_INDEX[0]), 0, 0 }, + { "mmDAC_W_INDEX", REG_MMIO, 0x0032, 1, &mmDAC_W_INDEX[0], sizeof(mmDAC_W_INDEX)/sizeof(mmDAC_W_INDEX[0]), 0, 0 }, + { "mmDAC_DATA", REG_MMIO, 0x0032, 1, &mmDAC_DATA[0], sizeof(mmDAC_DATA)/sizeof(mmDAC_DATA[0]), 0, 0 }, + { "mmGENFC_RD", REG_MMIO, 0x0032, 1, &mmGENFC_RD[0], sizeof(mmGENFC_RD)/sizeof(mmGENFC_RD[0]), 0, 0 }, + { "mmGENMO_RD", REG_MMIO, 0x0033, 1, &mmGENMO_RD[0], sizeof(mmGENMO_RD)/sizeof(mmGENMO_RD[0]), 0, 0 }, + { "mmGRPH8_IDX", REG_MMIO, 0x0033, 1, &mmGRPH8_IDX[0], sizeof(mmGRPH8_IDX)/sizeof(mmGRPH8_IDX[0]), 0, 0 }, + { "mmGRPH8_DATA", REG_MMIO, 0x0033, 1, &mmGRPH8_DATA[0], sizeof(mmGRPH8_DATA)/sizeof(mmGRPH8_DATA[0]), 0, 0 }, + { "mmCRTC8_IDX_1", REG_MMIO, 0x0035, 1, &mmCRTC8_IDX_1[0], sizeof(mmCRTC8_IDX_1)/sizeof(mmCRTC8_IDX_1[0]), 0, 0 }, + { "mmCRTC8_DATA_1", REG_MMIO, 0x0035, 1, &mmCRTC8_DATA_1[0], sizeof(mmCRTC8_DATA_1)/sizeof(mmCRTC8_DATA_1[0]), 0, 0 }, + { "mmGENFC_WT_1", REG_MMIO, 0x0036, 1, &mmGENFC_WT_1[0], sizeof(mmGENFC_WT_1)/sizeof(mmGENFC_WT_1[0]), 0, 0 }, + { "mmGENS1_1", REG_MMIO, 0x0036, 1, &mmGENS1_1[0], sizeof(mmGENS1_1)/sizeof(mmGENS1_1[0]), 0, 0 }, + { "mmCORB_WRITE_POINTER", REG_MMIO, 0x0000, 0, &mmCORB_WRITE_POINTER[0], sizeof(mmCORB_WRITE_POINTER)/sizeof(mmCORB_WRITE_POINTER[0]), 0, 0 }, + { "mmCORB_READ_POINTER", REG_MMIO, 0x0000, 0, &mmCORB_READ_POINTER[0], sizeof(mmCORB_READ_POINTER)/sizeof(mmCORB_READ_POINTER[0]), 0, 0 }, + { "mmCORB_CONTROL", REG_MMIO, 0x0001, 0, &mmCORB_CONTROL[0], sizeof(mmCORB_CONTROL)/sizeof(mmCORB_CONTROL[0]), 0, 0 }, + { "mmCORB_STATUS", REG_MMIO, 0x0001, 0, &mmCORB_STATUS[0], sizeof(mmCORB_STATUS)/sizeof(mmCORB_STATUS[0]), 0, 0 }, + { "mmCORB_SIZE", REG_MMIO, 0x0001, 0, &mmCORB_SIZE[0], sizeof(mmCORB_SIZE)/sizeof(mmCORB_SIZE[0]), 0, 0 }, + { "mmRIRB_LOWER_BASE_ADDRESS", REG_MMIO, 0x0002, 0, &mmRIRB_LOWER_BASE_ADDRESS[0], sizeof(mmRIRB_LOWER_BASE_ADDRESS)/sizeof(mmRIRB_LOWER_BASE_ADDRESS[0]), 0, 0 }, + { "mmRIRB_UPPER_BASE_ADDRESS", REG_MMIO, 0x0003, 0, &mmRIRB_UPPER_BASE_ADDRESS[0], sizeof(mmRIRB_UPPER_BASE_ADDRESS)/sizeof(mmRIRB_UPPER_BASE_ADDRESS[0]), 0, 0 }, + { "mmRIRB_WRITE_POINTER", REG_MMIO, 0x0004, 0, &mmRIRB_WRITE_POINTER[0], sizeof(mmRIRB_WRITE_POINTER)/sizeof(mmRIRB_WRITE_POINTER[0]), 0, 0 }, + { "mmRESPONSE_INTERRUPT_COUNT", REG_MMIO, 0x0004, 0, &mmRESPONSE_INTERRUPT_COUNT[0], sizeof(mmRESPONSE_INTERRUPT_COUNT)/sizeof(mmRESPONSE_INTERRUPT_COUNT[0]), 0, 0 }, + { "mmRIRB_CONTROL", REG_MMIO, 0x0005, 0, &mmRIRB_CONTROL[0], sizeof(mmRIRB_CONTROL)/sizeof(mmRIRB_CONTROL[0]), 0, 0 }, + { "mmRIRB_STATUS", REG_MMIO, 0x0005, 0, &mmRIRB_STATUS[0], sizeof(mmRIRB_STATUS)/sizeof(mmRIRB_STATUS[0]), 0, 0 }, + { "mmRIRB_SIZE", REG_MMIO, 0x0005, 0, &mmRIRB_SIZE[0], sizeof(mmRIRB_SIZE)/sizeof(mmRIRB_SIZE[0]), 0, 0 }, + { "mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE", REG_MMIO, 0x0006, 0, &mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE[0], sizeof(mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE)/sizeof(mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE[0]), 0, 0 }, + { "mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA", REG_MMIO, 0x0006, 0, &mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA[0], sizeof(mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA)/sizeof(mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA[0]), 0, 0 }, + { "mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX", REG_MMIO, 0x0006, 0, &mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX[0], sizeof(mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX)/sizeof(mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX[0]), 0, 0 }, + { "mmIMMEDIATE_RESPONSE_INPUT_INTERFACE", REG_MMIO, 0x0007, 0, &mmIMMEDIATE_RESPONSE_INPUT_INTERFACE[0], sizeof(mmIMMEDIATE_RESPONSE_INPUT_INTERFACE)/sizeof(mmIMMEDIATE_RESPONSE_INPUT_INTERFACE[0]), 0, 0 }, + { "mmIMMEDIATE_COMMAND_STATUS", REG_MMIO, 0x0008, 0, &mmIMMEDIATE_COMMAND_STATUS[0], sizeof(mmIMMEDIATE_COMMAND_STATUS)/sizeof(mmIMMEDIATE_COMMAND_STATUS[0]), 0, 0 }, + { "mmDMA_POSITION_LOWER_BASE_ADDRESS", REG_MMIO, 0x000a, 0, &mmDMA_POSITION_LOWER_BASE_ADDRESS[0], sizeof(mmDMA_POSITION_LOWER_BASE_ADDRESS)/sizeof(mmDMA_POSITION_LOWER_BASE_ADDRESS[0]), 0, 0 }, + { "mmDMA_POSITION_UPPER_BASE_ADDRESS", REG_MMIO, 0x000b, 0, &mmDMA_POSITION_UPPER_BASE_ADDRESS[0], sizeof(mmDMA_POSITION_UPPER_BASE_ADDRESS)/sizeof(mmDMA_POSITION_UPPER_BASE_ADDRESS[0]), 0, 0 }, + { "mmWALL_CLOCK_COUNTER_ALIAS", REG_MMIO, 0x074c, 1, &mmWALL_CLOCK_COUNTER_ALIAS[0], sizeof(mmWALL_CLOCK_COUNTER_ALIAS)/sizeof(mmWALL_CLOCK_COUNTER_ALIAS[0]), 0, 0 }, + { "mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA", REG_MMIO, 0x0006, 0, &mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA[0], sizeof(mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA)/sizeof(mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA[0]), 0, 0 }, + { "mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX", REG_MMIO, 0x0006, 0, &mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX[0], sizeof(mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX)/sizeof(mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX[0]), 0, 0 }, + { "mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA", REG_MMIO, 0x0006, 0, &mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA[0], sizeof(mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA)/sizeof(mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA[0]), 0, 0 }, + { "mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX", REG_MMIO, 0x0006, 0, &mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX[0], sizeof(mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX)/sizeof(mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX[0]), 0, 0 }, + { "mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA", REG_MMIO, 0x0006, 0, &mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA[0], sizeof(mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA)/sizeof(mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA[0]), 0, 0 }, + { "mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX", REG_MMIO, 0x0006, 0, &mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX[0], sizeof(mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX)/sizeof(mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX[0]), 0, 0 }, + { "mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS", REG_MMIO, 0x000e, 0, &mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS[0], sizeof(mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS)/sizeof(mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS[0]), 0, 0 }, + { "mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER", REG_MMIO, 0x000f, 0, &mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER[0], sizeof(mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER)/sizeof(mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER[0]), 0, 0 }, + { "mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH", REG_MMIO, 0x0010, 0, &mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH[0], sizeof(mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH)/sizeof(mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH[0]), 0, 0 }, + { "mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX", REG_MMIO, 0x0011, 0, &mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX[0], sizeof(mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX)/sizeof(mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX[0]), 0, 0 }, + { "mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE", REG_MMIO, 0x0012, 0, &mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE[0], sizeof(mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE)/sizeof(mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE[0]), 0, 0 }, + { "mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT", REG_MMIO, 0x0012, 0, &mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT[0], sizeof(mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT)/sizeof(mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT[0]), 0, 0 }, + { "mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS", REG_MMIO, 0x0014, 0, &mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS[0], sizeof(mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS)/sizeof(mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS[0]), 0, 0 }, + { "mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS", REG_MMIO, 0x0015, 0, &mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS[0], sizeof(mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS)/sizeof(mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS[0]), 0, 0 }, + { "mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS", REG_MMIO, 0x0761, 1, &mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS[0], sizeof(mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS)/sizeof(mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS[0]), 0, 0 }, + { "mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS", REG_MMIO, 0x0016, 0, &mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS[0], sizeof(mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS)/sizeof(mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS[0]), 0, 0 }, + { "mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER", REG_MMIO, 0x0017, 0, &mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER[0], sizeof(mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER)/sizeof(mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER[0]), 0, 0 }, + { "mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH", REG_MMIO, 0x0018, 0, &mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH[0], sizeof(mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH)/sizeof(mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH[0]), 0, 0 }, + { "mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX", REG_MMIO, 0x0019, 0, &mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX[0], sizeof(mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX)/sizeof(mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX[0]), 0, 0 }, + { "mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE", REG_MMIO, 0x001a, 0, &mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE[0], sizeof(mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE)/sizeof(mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE[0]), 0, 0 }, + { "mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT", REG_MMIO, 0x001a, 0, &mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT[0], sizeof(mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT)/sizeof(mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT[0]), 0, 0 }, + { "mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS", REG_MMIO, 0x001c, 0, &mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS[0], sizeof(mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS)/sizeof(mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS[0]), 0, 0 }, + { "mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS", REG_MMIO, 0x001d, 0, &mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS[0], sizeof(mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS)/sizeof(mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS[0]), 0, 0 }, + { "mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS", REG_MMIO, 0x0769, 1, &mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS[0], sizeof(mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS)/sizeof(mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS[0]), 0, 0 }, + { "mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS", REG_MMIO, 0x001e, 0, &mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS[0], sizeof(mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS)/sizeof(mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS[0]), 0, 0 }, + { "mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER", REG_MMIO, 0x001f, 0, &mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER[0], sizeof(mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER)/sizeof(mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER[0]), 0, 0 }, + { "mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH", REG_MMIO, 0x0020, 0, &mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH[0], sizeof(mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH)/sizeof(mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH[0]), 0, 0 }, + { "mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX", REG_MMIO, 0x0021, 0, &mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX[0], sizeof(mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX)/sizeof(mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX[0]), 0, 0 }, + { "mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE", REG_MMIO, 0x0022, 0, &mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE[0], sizeof(mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE)/sizeof(mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE[0]), 0, 0 }, + { "mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT", REG_MMIO, 0x0022, 0, &mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT[0], sizeof(mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT)/sizeof(mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT[0]), 0, 0 }, + { "mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS", REG_MMIO, 0x0024, 0, &mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS[0], sizeof(mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS)/sizeof(mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS[0]), 0, 0 }, + { "mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS", REG_MMIO, 0x0025, 0, &mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS[0], sizeof(mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS)/sizeof(mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS[0]), 0, 0 }, + { "mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS", REG_MMIO, 0x0771, 1, &mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS[0], sizeof(mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS)/sizeof(mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS[0]), 0, 0 }, + { "mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS", REG_MMIO, 0x0026, 0, &mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS[0], sizeof(mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS)/sizeof(mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS[0]), 0, 0 }, + { "mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER", REG_MMIO, 0x0027, 0, &mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER[0], sizeof(mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER)/sizeof(mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER[0]), 0, 0 }, + { "mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH", REG_MMIO, 0x0028, 0, &mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH[0], sizeof(mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH)/sizeof(mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH[0]), 0, 0 }, + { "mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX", REG_MMIO, 0x0029, 0, &mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX[0], sizeof(mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX)/sizeof(mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX[0]), 0, 0 }, + { "mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE", REG_MMIO, 0x002a, 0, &mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE[0], sizeof(mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE)/sizeof(mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE[0]), 0, 0 }, + { "mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT", REG_MMIO, 0x002a, 0, &mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT[0], sizeof(mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT)/sizeof(mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT[0]), 0, 0 }, + { "mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS", REG_MMIO, 0x002c, 0, &mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS[0], sizeof(mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS)/sizeof(mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS[0]), 0, 0 }, + { "mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS", REG_MMIO, 0x002d, 0, &mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS[0], sizeof(mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS)/sizeof(mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS[0]), 0, 0 }, + { "mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS", REG_MMIO, 0x0779, 1, &mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS[0], sizeof(mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS)/sizeof(mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS[0]), 0, 0 }, + { "mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS", REG_MMIO, 0x002e, 0, &mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS[0], sizeof(mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS)/sizeof(mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS[0]), 0, 0 }, + { "mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER", REG_MMIO, 0x002f, 0, &mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER[0], sizeof(mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER)/sizeof(mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER[0]), 0, 0 }, + { "mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH", REG_MMIO, 0x0030, 0, &mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH[0], sizeof(mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH)/sizeof(mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH[0]), 0, 0 }, + { "mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX", REG_MMIO, 0x0031, 0, &mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX[0], sizeof(mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX)/sizeof(mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX[0]), 0, 0 }, + { "mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE", REG_MMIO, 0x0032, 0, &mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE[0], sizeof(mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE)/sizeof(mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE[0]), 0, 0 }, + { "mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT", REG_MMIO, 0x0032, 0, &mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT[0], sizeof(mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT)/sizeof(mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT[0]), 0, 0 }, + { "mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS", REG_MMIO, 0x0034, 0, &mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS[0], sizeof(mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS)/sizeof(mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS[0]), 0, 0 }, + { "mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS", REG_MMIO, 0x0035, 0, &mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS[0], sizeof(mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS)/sizeof(mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS[0]), 0, 0 }, + { "mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS", REG_MMIO, 0x0781, 1, &mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS[0], sizeof(mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS)/sizeof(mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS[0]), 0, 0 }, + { "mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS", REG_MMIO, 0x0036, 0, &mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS[0], sizeof(mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS)/sizeof(mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS[0]), 0, 0 }, + { "mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER", REG_MMIO, 0x0037, 0, &mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER[0], sizeof(mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER)/sizeof(mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER[0]), 0, 0 }, + { "mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH", REG_MMIO, 0x0038, 0, &mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH[0], sizeof(mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH)/sizeof(mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH[0]), 0, 0 }, + { "mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX", REG_MMIO, 0x0039, 0, &mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX[0], sizeof(mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX)/sizeof(mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX[0]), 0, 0 }, + { "mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE", REG_MMIO, 0x003a, 0, &mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE[0], sizeof(mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE)/sizeof(mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE[0]), 0, 0 }, + { "mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT", REG_MMIO, 0x003a, 0, &mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT[0], sizeof(mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT)/sizeof(mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT[0]), 0, 0 }, + { "mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS", REG_MMIO, 0x003c, 0, &mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS[0], sizeof(mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS)/sizeof(mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS[0]), 0, 0 }, + { "mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS", REG_MMIO, 0x003d, 0, &mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS[0], sizeof(mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS)/sizeof(mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS[0]), 0, 0 }, + { "mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS", REG_MMIO, 0x0789, 1, &mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS[0], sizeof(mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS)/sizeof(mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS[0]), 0, 0 }, + { "mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS", REG_MMIO, 0x003e, 0, &mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS[0], sizeof(mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS)/sizeof(mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS[0]), 0, 0 }, + { "mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER", REG_MMIO, 0x003f, 0, &mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER[0], sizeof(mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER)/sizeof(mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER[0]), 0, 0 }, + { "mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH", REG_MMIO, 0x0040, 0, &mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH[0], sizeof(mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH)/sizeof(mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH[0]), 0, 0 }, + { "mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX", REG_MMIO, 0x0041, 0, &mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX[0], sizeof(mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX)/sizeof(mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX[0]), 0, 0 }, + { "mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE", REG_MMIO, 0x0042, 0, &mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE[0], sizeof(mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE)/sizeof(mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE[0]), 0, 0 }, + { "mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT", REG_MMIO, 0x0042, 0, &mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT[0], sizeof(mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT)/sizeof(mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT[0]), 0, 0 }, + { "mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS", REG_MMIO, 0x0044, 0, &mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS[0], sizeof(mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS)/sizeof(mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS[0]), 0, 0 }, + { "mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS", REG_MMIO, 0x0045, 0, &mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS[0], sizeof(mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS)/sizeof(mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS[0]), 0, 0 }, + { "mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS", REG_MMIO, 0x0791, 1, &mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS[0], sizeof(mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS)/sizeof(mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS[0]), 0, 0 }, + { "mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS", REG_MMIO, 0x0046, 0, &mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS[0], sizeof(mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS)/sizeof(mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS[0]), 0, 0 }, + { "mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER", REG_MMIO, 0x0047, 0, &mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER[0], sizeof(mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER)/sizeof(mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER[0]), 0, 0 }, + { "mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH", REG_MMIO, 0x0048, 0, &mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH[0], sizeof(mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH)/sizeof(mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH[0]), 0, 0 }, + { "mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX", REG_MMIO, 0x0049, 0, &mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX[0], sizeof(mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX)/sizeof(mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX[0]), 0, 0 }, + { "mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE", REG_MMIO, 0x004a, 0, &mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE[0], sizeof(mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE)/sizeof(mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE[0]), 0, 0 }, + { "mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT", REG_MMIO, 0x004a, 0, &mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT[0], sizeof(mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT)/sizeof(mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT[0]), 0, 0 }, + { "mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS", REG_MMIO, 0x004c, 0, &mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS[0], sizeof(mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS)/sizeof(mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS[0]), 0, 0 }, + { "mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS", REG_MMIO, 0x004d, 0, &mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS[0], sizeof(mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS)/sizeof(mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS[0]), 0, 0 }, + { "mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS", REG_MMIO, 0x0799, 1, &mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS[0], sizeof(mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS)/sizeof(mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS[0]), 0, 0 }, + { "mmVGA_VGA_MEM_WRITE_PAGE_ADDR", REG_MMIO, 0x0000, 0, NULL, 0, 0, 0 }, + { "mmVGA_VGA_MEM_READ_PAGE_ADDR", REG_MMIO, 0x0001, 0, NULL, 0, 0, 0 }, + { "mmVGA_VGA_MEM_WRITE_PAGE_ADDR", REG_MMIO, 0x0000, 0, NULL, 0, 0, 0 }, + { "mmVGA_VGA_MEM_READ_PAGE_ADDR", REG_MMIO, 0x0001, 0, NULL, 0, 0, 0 }, + { "mmVGA_RENDER_CONTROL", REG_MMIO, 0x0000, 1, &mmVGA_RENDER_CONTROL[0], sizeof(mmVGA_RENDER_CONTROL)/sizeof(mmVGA_RENDER_CONTROL[0]), 0, 0 }, + { "mmVGA_SEQUENCER_RESET_CONTROL", REG_MMIO, 0x0001, 1, &mmVGA_SEQUENCER_RESET_CONTROL[0], sizeof(mmVGA_SEQUENCER_RESET_CONTROL)/sizeof(mmVGA_SEQUENCER_RESET_CONTROL[0]), 0, 0 }, + { "mmVGA_MODE_CONTROL", REG_MMIO, 0x0002, 1, &mmVGA_MODE_CONTROL[0], sizeof(mmVGA_MODE_CONTROL)/sizeof(mmVGA_MODE_CONTROL[0]), 0, 0 }, + { "mmVGA_SURFACE_PITCH_SELECT", REG_MMIO, 0x0003, 1, &mmVGA_SURFACE_PITCH_SELECT[0], sizeof(mmVGA_SURFACE_PITCH_SELECT)/sizeof(mmVGA_SURFACE_PITCH_SELECT[0]), 0, 0 }, + { "mmVGA_MEMORY_BASE_ADDRESS", REG_MMIO, 0x0004, 1, &mmVGA_MEMORY_BASE_ADDRESS[0], sizeof(mmVGA_MEMORY_BASE_ADDRESS)/sizeof(mmVGA_MEMORY_BASE_ADDRESS[0]), 0, 0 }, + { "mmVGA_DISPBUF1_SURFACE_ADDR", REG_MMIO, 0x0006, 1, &mmVGA_DISPBUF1_SURFACE_ADDR[0], sizeof(mmVGA_DISPBUF1_SURFACE_ADDR)/sizeof(mmVGA_DISPBUF1_SURFACE_ADDR[0]), 0, 0 }, + { "mmVGA_DISPBUF2_SURFACE_ADDR", REG_MMIO, 0x0008, 1, &mmVGA_DISPBUF2_SURFACE_ADDR[0], sizeof(mmVGA_DISPBUF2_SURFACE_ADDR)/sizeof(mmVGA_DISPBUF2_SURFACE_ADDR[0]), 0, 0 }, + { "mmVGA_MEMORY_BASE_ADDRESS_HIGH", REG_MMIO, 0x0009, 1, &mmVGA_MEMORY_BASE_ADDRESS_HIGH[0], sizeof(mmVGA_MEMORY_BASE_ADDRESS_HIGH)/sizeof(mmVGA_MEMORY_BASE_ADDRESS_HIGH[0]), 0, 0 }, + { "mmVGA_HDP_CONTROL", REG_MMIO, 0x000a, 1, &mmVGA_HDP_CONTROL[0], sizeof(mmVGA_HDP_CONTROL)/sizeof(mmVGA_HDP_CONTROL[0]), 0, 0 }, + { "mmVGA_CACHE_CONTROL", REG_MMIO, 0x000b, 1, &mmVGA_CACHE_CONTROL[0], sizeof(mmVGA_CACHE_CONTROL)/sizeof(mmVGA_CACHE_CONTROL[0]), 0, 0 }, + { "mmD1VGA_CONTROL", REG_MMIO, 0x000c, 1, &mmD1VGA_CONTROL[0], sizeof(mmD1VGA_CONTROL)/sizeof(mmD1VGA_CONTROL[0]), 0, 0 }, + { "mmD2VGA_CONTROL", REG_MMIO, 0x000e, 1, &mmD2VGA_CONTROL[0], sizeof(mmD2VGA_CONTROL)/sizeof(mmD2VGA_CONTROL[0]), 0, 0 }, + { "mmVGA_STATUS", REG_MMIO, 0x0010, 1, &mmVGA_STATUS[0], sizeof(mmVGA_STATUS)/sizeof(mmVGA_STATUS[0]), 0, 0 }, + { "mmVGA_INTERRUPT_CONTROL", REG_MMIO, 0x0011, 1, &mmVGA_INTERRUPT_CONTROL[0], sizeof(mmVGA_INTERRUPT_CONTROL)/sizeof(mmVGA_INTERRUPT_CONTROL[0]), 0, 0 }, + { "mmVGA_STATUS_CLEAR", REG_MMIO, 0x0012, 1, &mmVGA_STATUS_CLEAR[0], sizeof(mmVGA_STATUS_CLEAR)/sizeof(mmVGA_STATUS_CLEAR[0]), 0, 0 }, + { "mmVGA_INTERRUPT_STATUS", REG_MMIO, 0x0013, 1, &mmVGA_INTERRUPT_STATUS[0], sizeof(mmVGA_INTERRUPT_STATUS)/sizeof(mmVGA_INTERRUPT_STATUS[0]), 0, 0 }, + { "mmVGA_MAIN_CONTROL", REG_MMIO, 0x0014, 1, &mmVGA_MAIN_CONTROL[0], sizeof(mmVGA_MAIN_CONTROL)/sizeof(mmVGA_MAIN_CONTROL[0]), 0, 0 }, + { "mmVGA_TEST_CONTROL", REG_MMIO, 0x0015, 1, &mmVGA_TEST_CONTROL[0], sizeof(mmVGA_TEST_CONTROL)/sizeof(mmVGA_TEST_CONTROL[0]), 0, 0 }, + { "mmVGA_QOS_CTRL", REG_MMIO, 0x0018, 1, &mmVGA_QOS_CTRL[0], sizeof(mmVGA_QOS_CTRL)/sizeof(mmVGA_QOS_CTRL[0]), 0, 0 }, + { "mmVGA_CRTC8_IDX", REG_MMIO, 0x002d, 0, NULL, 0, 0, 0 }, + { "mmVGA_CRTC8_DATA", REG_MMIO, 0x002d, 0, NULL, 0, 0, 0 }, + { "mmVGA_GENFC_WT", REG_MMIO, 0x002e, 0, NULL, 0, 0, 0 }, + { "mmVGA_GENS1", REG_MMIO, 0x002e, 0, NULL, 0, 0, 0 }, + { "mmVGA_ATTRDW", REG_MMIO, 0x0030, 0, NULL, 0, 0, 0 }, + { "mmVGA_ATTRX", REG_MMIO, 0x0030, 0, NULL, 0, 0, 0 }, + { "mmVGA_ATTRDR", REG_MMIO, 0x0030, 0, NULL, 0, 0, 0 }, + { "mmVGA_GENMO_WT", REG_MMIO, 0x0030, 0, NULL, 0, 0, 0 }, + { "mmVGA_GENS0", REG_MMIO, 0x0030, 0, NULL, 0, 0, 0 }, + { "mmVGA_GENENB", REG_MMIO, 0x0030, 0, NULL, 0, 0, 0 }, + { "mmVGA_SEQ8_IDX", REG_MMIO, 0x0031, 0, NULL, 0, 0, 0 }, + { "mmVGA_SEQ8_DATA", REG_MMIO, 0x0031, 0, NULL, 0, 0, 0 }, + { "mmVGA_DAC_MASK", REG_MMIO, 0x0031, 0, NULL, 0, 0, 0 }, + { "mmVGA_DAC_R_INDEX", REG_MMIO, 0x0031, 0, NULL, 0, 0, 0 }, + { "mmVGA_DAC_W_INDEX", REG_MMIO, 0x0032, 0, NULL, 0, 0, 0 }, + { "mmVGA_DAC_DATA", REG_MMIO, 0x0032, 0, NULL, 0, 0, 0 }, + { "mmVGA_GENFC_RD", REG_MMIO, 0x0032, 0, NULL, 0, 0, 0 }, + { "mmVGA_GENMO_RD", REG_MMIO, 0x0033, 0, NULL, 0, 0, 0 }, + { "mmVGA_GRPH8_IDX", REG_MMIO, 0x0033, 0, NULL, 0, 0, 0 }, + { "mmVGA_GRPH8_DATA", REG_MMIO, 0x0033, 0, NULL, 0, 0, 0 }, + { "mmVGA_CRTC8_IDX_1", REG_MMIO, 0x0035, 0, NULL, 0, 0, 0 }, + { "mmVGA_CRTC8_DATA_1", REG_MMIO, 0x0035, 0, NULL, 0, 0, 0 }, + { "mmVGA_GENFC_WT_1", REG_MMIO, 0x0036, 0, NULL, 0, 0, 0 }, + { "mmVGA_GENS1_1", REG_MMIO, 0x0036, 0, NULL, 0, 0, 0 }, + { "mmD3VGA_CONTROL", REG_MMIO, 0x0038, 1, &mmD3VGA_CONTROL[0], sizeof(mmD3VGA_CONTROL)/sizeof(mmD3VGA_CONTROL[0]), 0, 0 }, + { "mmD4VGA_CONTROL", REG_MMIO, 0x0039, 1, &mmD4VGA_CONTROL[0], sizeof(mmD4VGA_CONTROL)/sizeof(mmD4VGA_CONTROL[0]), 0, 0 }, + { "mmD5VGA_CONTROL", REG_MMIO, 0x003a, 1, &mmD5VGA_CONTROL[0], sizeof(mmD5VGA_CONTROL)/sizeof(mmD5VGA_CONTROL[0]), 0, 0 }, + { "mmD6VGA_CONTROL", REG_MMIO, 0x003b, 1, &mmD6VGA_CONTROL[0], sizeof(mmD6VGA_CONTROL)/sizeof(mmD6VGA_CONTROL[0]), 0, 0 }, + { "mmVGA_SOURCE_SELECT", REG_MMIO, 0x003c, 1, &mmVGA_SOURCE_SELECT[0], sizeof(mmVGA_SOURCE_SELECT)/sizeof(mmVGA_SOURCE_SELECT[0]), 0, 0 }, + { "mmPHYPLLA_PIXCLK_RESYNC_CNTL", REG_MMIO, 0x0040, 1, &mmPHYPLLA_PIXCLK_RESYNC_CNTL[0], sizeof(mmPHYPLLA_PIXCLK_RESYNC_CNTL)/sizeof(mmPHYPLLA_PIXCLK_RESYNC_CNTL[0]), 0, 0 }, + { "mmPHYPLLB_PIXCLK_RESYNC_CNTL", REG_MMIO, 0x0041, 1, &mmPHYPLLB_PIXCLK_RESYNC_CNTL[0], sizeof(mmPHYPLLB_PIXCLK_RESYNC_CNTL)/sizeof(mmPHYPLLB_PIXCLK_RESYNC_CNTL[0]), 0, 0 }, + { "mmPHYPLLC_PIXCLK_RESYNC_CNTL", REG_MMIO, 0x0042, 1, &mmPHYPLLC_PIXCLK_RESYNC_CNTL[0], sizeof(mmPHYPLLC_PIXCLK_RESYNC_CNTL)/sizeof(mmPHYPLLC_PIXCLK_RESYNC_CNTL[0]), 0, 0 }, + { "mmPHYPLLD_PIXCLK_RESYNC_CNTL", REG_MMIO, 0x0043, 1, &mmPHYPLLD_PIXCLK_RESYNC_CNTL[0], sizeof(mmPHYPLLD_PIXCLK_RESYNC_CNTL)/sizeof(mmPHYPLLD_PIXCLK_RESYNC_CNTL[0]), 0, 0 }, + { "mmDP_DTO_DBUF_EN", REG_MMIO, 0x0044, 1, &mmDP_DTO_DBUF_EN[0], sizeof(mmDP_DTO_DBUF_EN)/sizeof(mmDP_DTO_DBUF_EN[0]), 0, 0 }, + { "mmDPREFCLK_CGTT_BLK_CTRL_REG", REG_MMIO, 0x0048, 1, &mmDPREFCLK_CGTT_BLK_CTRL_REG[0], sizeof(mmDPREFCLK_CGTT_BLK_CTRL_REG)/sizeof(mmDPREFCLK_CGTT_BLK_CTRL_REG[0]), 0, 0 }, + { "mmREFCLK_CNTL", REG_MMIO, 0x0049, 1, &mmREFCLK_CNTL[0], sizeof(mmREFCLK_CNTL)/sizeof(mmREFCLK_CNTL[0]), 0, 0 }, + { "mmMIPI_CLK_CNTL", REG_MMIO, 0x004a, 1, &mmMIPI_CLK_CNTL[0], sizeof(mmMIPI_CLK_CNTL)/sizeof(mmMIPI_CLK_CNTL[0]), 0, 0 }, + { "mmREFCLK_CGTT_BLK_CTRL_REG", REG_MMIO, 0x004b, 1, &mmREFCLK_CGTT_BLK_CTRL_REG[0], sizeof(mmREFCLK_CGTT_BLK_CTRL_REG)/sizeof(mmREFCLK_CGTT_BLK_CTRL_REG[0]), 0, 0 }, + { "mmPHYPLLE_PIXCLK_RESYNC_CNTL", REG_MMIO, 0x004c, 1, &mmPHYPLLE_PIXCLK_RESYNC_CNTL[0], sizeof(mmPHYPLLE_PIXCLK_RESYNC_CNTL)/sizeof(mmPHYPLLE_PIXCLK_RESYNC_CNTL[0]), 0, 0 }, + { "mmDCCG_PERFMON_CNTL2", REG_MMIO, 0x004e, 1, &mmDCCG_PERFMON_CNTL2[0], sizeof(mmDCCG_PERFMON_CNTL2)/sizeof(mmDCCG_PERFMON_CNTL2[0]), 0, 0 }, + { "mmDSICLK_CGTT_BLK_CTRL_REG", REG_MMIO, 0x004f, 1, &mmDSICLK_CGTT_BLK_CTRL_REG[0], sizeof(mmDSICLK_CGTT_BLK_CTRL_REG)/sizeof(mmDSICLK_CGTT_BLK_CTRL_REG[0]), 0, 0 }, + { "mmDCCG_CBUS_WRCMD_DELAY", REG_MMIO, 0x0050, 1, &mmDCCG_CBUS_WRCMD_DELAY[0], sizeof(mmDCCG_CBUS_WRCMD_DELAY)/sizeof(mmDCCG_CBUS_WRCMD_DELAY[0]), 0, 0 }, + { "mmDCCG_DS_DTO_INCR", REG_MMIO, 0x0053, 1, &mmDCCG_DS_DTO_INCR[0], sizeof(mmDCCG_DS_DTO_INCR)/sizeof(mmDCCG_DS_DTO_INCR[0]), 0, 0 }, + { "mmDCCG_DS_DTO_MODULO", REG_MMIO, 0x0054, 1, &mmDCCG_DS_DTO_MODULO[0], sizeof(mmDCCG_DS_DTO_MODULO)/sizeof(mmDCCG_DS_DTO_MODULO[0]), 0, 0 }, + { "mmDCCG_DS_CNTL", REG_MMIO, 0x0055, 1, &mmDCCG_DS_CNTL[0], sizeof(mmDCCG_DS_CNTL)/sizeof(mmDCCG_DS_CNTL[0]), 0, 0 }, + { "mmDCCG_DS_HW_CAL_INTERVAL", REG_MMIO, 0x0056, 1, &mmDCCG_DS_HW_CAL_INTERVAL[0], sizeof(mmDCCG_DS_HW_CAL_INTERVAL)/sizeof(mmDCCG_DS_HW_CAL_INTERVAL[0]), 0, 0 }, + { "mmSYMCLKG_CLOCK_ENABLE", REG_MMIO, 0x0057, 1, &mmSYMCLKG_CLOCK_ENABLE[0], sizeof(mmSYMCLKG_CLOCK_ENABLE)/sizeof(mmSYMCLKG_CLOCK_ENABLE[0]), 0, 0 }, + { "mmDPREFCLK_CNTL", REG_MMIO, 0x0058, 1, &mmDPREFCLK_CNTL[0], sizeof(mmDPREFCLK_CNTL)/sizeof(mmDPREFCLK_CNTL[0]), 0, 0 }, + { "mmAOMCLK0_CNTL", REG_MMIO, 0x0059, 1, &mmAOMCLK0_CNTL[0], sizeof(mmAOMCLK0_CNTL)/sizeof(mmAOMCLK0_CNTL[0]), 0, 0 }, + { "mmAOMCLK1_CNTL", REG_MMIO, 0x005a, 1, &mmAOMCLK1_CNTL[0], sizeof(mmAOMCLK1_CNTL)/sizeof(mmAOMCLK1_CNTL[0]), 0, 0 }, + { "mmAOMCLK2_CNTL", REG_MMIO, 0x005b, 1, &mmAOMCLK2_CNTL[0], sizeof(mmAOMCLK2_CNTL)/sizeof(mmAOMCLK2_CNTL[0]), 0, 0 }, + { "mmDCCG_AUDIO_DTO2_PHASE", REG_MMIO, 0x005c, 1, &mmDCCG_AUDIO_DTO2_PHASE[0], sizeof(mmDCCG_AUDIO_DTO2_PHASE)/sizeof(mmDCCG_AUDIO_DTO2_PHASE[0]), 0, 0 }, + { "mmDCCG_AUDIO_DTO2_MODULO", REG_MMIO, 0x005d, 1, &mmDCCG_AUDIO_DTO2_MODULO[0], sizeof(mmDCCG_AUDIO_DTO2_MODULO)/sizeof(mmDCCG_AUDIO_DTO2_MODULO[0]), 0, 0 }, + { "mmDCE_VERSION", REG_MMIO, 0x005e, 1, &mmDCE_VERSION[0], sizeof(mmDCE_VERSION)/sizeof(mmDCE_VERSION[0]), 0, 0 }, + { "mmPHYPLLG_PIXCLK_RESYNC_CNTL", REG_MMIO, 0x005f, 1, &mmPHYPLLG_PIXCLK_RESYNC_CNTL[0], sizeof(mmPHYPLLG_PIXCLK_RESYNC_CNTL)/sizeof(mmPHYPLLG_PIXCLK_RESYNC_CNTL[0]), 0, 0 }, + { "mmDCCG_GTC_CNTL", REG_MMIO, 0x0060, 1, &mmDCCG_GTC_CNTL[0], sizeof(mmDCCG_GTC_CNTL)/sizeof(mmDCCG_GTC_CNTL[0]), 0, 0 }, + { "mmDCCG_GTC_DTO_INCR", REG_MMIO, 0x0061, 1, &mmDCCG_GTC_DTO_INCR[0], sizeof(mmDCCG_GTC_DTO_INCR)/sizeof(mmDCCG_GTC_DTO_INCR[0]), 0, 0 }, + { "mmDCCG_GTC_DTO_MODULO", REG_MMIO, 0x0062, 1, &mmDCCG_GTC_DTO_MODULO[0], sizeof(mmDCCG_GTC_DTO_MODULO)/sizeof(mmDCCG_GTC_DTO_MODULO[0]), 0, 0 }, + { "mmDCCG_GTC_CURRENT", REG_MMIO, 0x0063, 1, &mmDCCG_GTC_CURRENT[0], sizeof(mmDCCG_GTC_CURRENT)/sizeof(mmDCCG_GTC_CURRENT[0]), 0, 0 }, + { "mmMIPI_DTO_CNTL", REG_MMIO, 0x0065, 1, &mmMIPI_DTO_CNTL[0], sizeof(mmMIPI_DTO_CNTL)/sizeof(mmMIPI_DTO_CNTL[0]), 0, 0 }, + { "mmMIPI_DTO_PHASE", REG_MMIO, 0x0066, 1, &mmMIPI_DTO_PHASE[0], sizeof(mmMIPI_DTO_PHASE)/sizeof(mmMIPI_DTO_PHASE[0]), 0, 0 }, + { "mmMIPI_DTO_MODULO", REG_MMIO, 0x0067, 1, &mmMIPI_DTO_MODULO[0], sizeof(mmMIPI_DTO_MODULO)/sizeof(mmMIPI_DTO_MODULO[0]), 0, 0 }, + { "mmDAC_CLK_ENABLE", REG_MMIO, 0x0068, 1, &mmDAC_CLK_ENABLE[0], sizeof(mmDAC_CLK_ENABLE)/sizeof(mmDAC_CLK_ENABLE[0]), 0, 0 }, + { "mmDVO_CLK_ENABLE", REG_MMIO, 0x0069, 1, &mmDVO_CLK_ENABLE[0], sizeof(mmDVO_CLK_ENABLE)/sizeof(mmDVO_CLK_ENABLE[0]), 0, 0 }, + { "mmAVSYNC_COUNTER_WRITE", REG_MMIO, 0x006a, 1, &mmAVSYNC_COUNTER_WRITE[0], sizeof(mmAVSYNC_COUNTER_WRITE)/sizeof(mmAVSYNC_COUNTER_WRITE[0]), 0, 0 }, + { "mmAVSYNC_COUNTER_CONTROL", REG_MMIO, 0x006b, 1, &mmAVSYNC_COUNTER_CONTROL[0], sizeof(mmAVSYNC_COUNTER_CONTROL)/sizeof(mmAVSYNC_COUNTER_CONTROL[0]), 0, 0 }, + { "mmAVSYNC_COUNTER_READ", REG_MMIO, 0x006f, 1, &mmAVSYNC_COUNTER_READ[0], sizeof(mmAVSYNC_COUNTER_READ)/sizeof(mmAVSYNC_COUNTER_READ[0]), 0, 0 }, + { "mmMILLISECOND_TIME_BASE_DIV", REG_MMIO, 0x0070, 1, &mmMILLISECOND_TIME_BASE_DIV[0], sizeof(mmMILLISECOND_TIME_BASE_DIV)/sizeof(mmMILLISECOND_TIME_BASE_DIV[0]), 0, 0 }, + { "mmDISPCLK_FREQ_CHANGE_CNTL", REG_MMIO, 0x0071, 1, &mmDISPCLK_FREQ_CHANGE_CNTL[0], sizeof(mmDISPCLK_FREQ_CHANGE_CNTL)/sizeof(mmDISPCLK_FREQ_CHANGE_CNTL[0]), 0, 0 }, + { "mmDC_MEM_GLOBAL_PWR_REQ_CNTL", REG_MMIO, 0x0072, 1, &mmDC_MEM_GLOBAL_PWR_REQ_CNTL[0], sizeof(mmDC_MEM_GLOBAL_PWR_REQ_CNTL)/sizeof(mmDC_MEM_GLOBAL_PWR_REQ_CNTL[0]), 0, 0 }, + { "mmDCCG_PERFMON_CNTL", REG_MMIO, 0x0073, 1, &mmDCCG_PERFMON_CNTL[0], sizeof(mmDCCG_PERFMON_CNTL)/sizeof(mmDCCG_PERFMON_CNTL[0]), 0, 0 }, + { "mmDCCG_GATE_DISABLE_CNTL", REG_MMIO, 0x0074, 1, &mmDCCG_GATE_DISABLE_CNTL[0], sizeof(mmDCCG_GATE_DISABLE_CNTL)/sizeof(mmDCCG_GATE_DISABLE_CNTL[0]), 0, 0 }, + { "mmDISPCLK_CGTT_BLK_CTRL_REG", REG_MMIO, 0x0075, 1, &mmDISPCLK_CGTT_BLK_CTRL_REG[0], sizeof(mmDISPCLK_CGTT_BLK_CTRL_REG)/sizeof(mmDISPCLK_CGTT_BLK_CTRL_REG[0]), 0, 0 }, + { "mmSOCCLK_CGTT_BLK_CTRL_REG", REG_MMIO, 0x0076, 1, &mmSOCCLK_CGTT_BLK_CTRL_REG[0], sizeof(mmSOCCLK_CGTT_BLK_CTRL_REG)/sizeof(mmSOCCLK_CGTT_BLK_CTRL_REG[0]), 0, 0 }, + { "mmDCCG_CAC_STATUS", REG_MMIO, 0x0077, 1, &mmDCCG_CAC_STATUS[0], sizeof(mmDCCG_CAC_STATUS)/sizeof(mmDCCG_CAC_STATUS[0]), 0, 0 }, + { "mmPIXCLK1_RESYNC_CNTL", REG_MMIO, 0x0078, 1, &mmPIXCLK1_RESYNC_CNTL[0], sizeof(mmPIXCLK1_RESYNC_CNTL)/sizeof(mmPIXCLK1_RESYNC_CNTL[0]), 0, 0 }, + { "mmPIXCLK2_RESYNC_CNTL", REG_MMIO, 0x0079, 1, &mmPIXCLK2_RESYNC_CNTL[0], sizeof(mmPIXCLK2_RESYNC_CNTL)/sizeof(mmPIXCLK2_RESYNC_CNTL[0]), 0, 0 }, + { "mmPIXCLK0_RESYNC_CNTL", REG_MMIO, 0x007a, 1, &mmPIXCLK0_RESYNC_CNTL[0], sizeof(mmPIXCLK0_RESYNC_CNTL)/sizeof(mmPIXCLK0_RESYNC_CNTL[0]), 0, 0 }, + { "mmMICROSECOND_TIME_BASE_DIV", REG_MMIO, 0x007b, 1, &mmMICROSECOND_TIME_BASE_DIV[0], sizeof(mmMICROSECOND_TIME_BASE_DIV)/sizeof(mmMICROSECOND_TIME_BASE_DIV[0]), 0, 0 }, + { "mmDCCG_GATE_DISABLE_CNTL2", REG_MMIO, 0x007c, 1, &mmDCCG_GATE_DISABLE_CNTL2[0], sizeof(mmDCCG_GATE_DISABLE_CNTL2)/sizeof(mmDCCG_GATE_DISABLE_CNTL2[0]), 0, 0 }, + { "mmSYMCLK_CGTT_BLK_CTRL_REG", REG_MMIO, 0x007d, 1, &mmSYMCLK_CGTT_BLK_CTRL_REG[0], sizeof(mmSYMCLK_CGTT_BLK_CTRL_REG)/sizeof(mmSYMCLK_CGTT_BLK_CTRL_REG[0]), 0, 0 }, + { "mmPHYPLLF_PIXCLK_RESYNC_CNTL", REG_MMIO, 0x007e, 1, &mmPHYPLLF_PIXCLK_RESYNC_CNTL[0], sizeof(mmPHYPLLF_PIXCLK_RESYNC_CNTL)/sizeof(mmPHYPLLF_PIXCLK_RESYNC_CNTL[0]), 0, 0 }, + { "mmDCCG_DISP_CNTL_REG", REG_MMIO, 0x007f, 1, &mmDCCG_DISP_CNTL_REG[0], sizeof(mmDCCG_DISP_CNTL_REG)/sizeof(mmDCCG_DISP_CNTL_REG[0]), 0, 0 }, + { "mmOTG0_PIXEL_RATE_CNTL", REG_MMIO, 0x0080, 1, &mmOTG0_PIXEL_RATE_CNTL[0], sizeof(mmOTG0_PIXEL_RATE_CNTL)/sizeof(mmOTG0_PIXEL_RATE_CNTL[0]), 0, 0 }, + { "mmDP_DTO0_PHASE", REG_MMIO, 0x0081, 1, &mmDP_DTO0_PHASE[0], sizeof(mmDP_DTO0_PHASE)/sizeof(mmDP_DTO0_PHASE[0]), 0, 0 }, + { "mmDP_DTO0_MODULO", REG_MMIO, 0x0082, 1, &mmDP_DTO0_MODULO[0], sizeof(mmDP_DTO0_MODULO)/sizeof(mmDP_DTO0_MODULO[0]), 0, 0 }, + { "mmOTG0_PHYPLL_PIXEL_RATE_CNTL", REG_MMIO, 0x0083, 1, &mmOTG0_PHYPLL_PIXEL_RATE_CNTL[0], sizeof(mmOTG0_PHYPLL_PIXEL_RATE_CNTL)/sizeof(mmOTG0_PHYPLL_PIXEL_RATE_CNTL[0]), 0, 0 }, + { "mmOTG1_PIXEL_RATE_CNTL", REG_MMIO, 0x0084, 1, &mmOTG1_PIXEL_RATE_CNTL[0], sizeof(mmOTG1_PIXEL_RATE_CNTL)/sizeof(mmOTG1_PIXEL_RATE_CNTL[0]), 0, 0 }, + { "mmDP_DTO1_PHASE", REG_MMIO, 0x0085, 1, &mmDP_DTO1_PHASE[0], sizeof(mmDP_DTO1_PHASE)/sizeof(mmDP_DTO1_PHASE[0]), 0, 0 }, + { "mmDP_DTO1_MODULO", REG_MMIO, 0x0086, 1, &mmDP_DTO1_MODULO[0], sizeof(mmDP_DTO1_MODULO)/sizeof(mmDP_DTO1_MODULO[0]), 0, 0 }, + { "mmOTG1_PHYPLL_PIXEL_RATE_CNTL", REG_MMIO, 0x0087, 1, &mmOTG1_PHYPLL_PIXEL_RATE_CNTL[0], sizeof(mmOTG1_PHYPLL_PIXEL_RATE_CNTL)/sizeof(mmOTG1_PHYPLL_PIXEL_RATE_CNTL[0]), 0, 0 }, + { "mmOTG2_PIXEL_RATE_CNTL", REG_MMIO, 0x0088, 1, &mmOTG2_PIXEL_RATE_CNTL[0], sizeof(mmOTG2_PIXEL_RATE_CNTL)/sizeof(mmOTG2_PIXEL_RATE_CNTL[0]), 0, 0 }, + { "mmDP_DTO2_PHASE", REG_MMIO, 0x0089, 1, &mmDP_DTO2_PHASE[0], sizeof(mmDP_DTO2_PHASE)/sizeof(mmDP_DTO2_PHASE[0]), 0, 0 }, + { "mmDP_DTO2_MODULO", REG_MMIO, 0x008a, 1, &mmDP_DTO2_MODULO[0], sizeof(mmDP_DTO2_MODULO)/sizeof(mmDP_DTO2_MODULO[0]), 0, 0 }, + { "mmOTG2_PHYPLL_PIXEL_RATE_CNTL", REG_MMIO, 0x008b, 1, &mmOTG2_PHYPLL_PIXEL_RATE_CNTL[0], sizeof(mmOTG2_PHYPLL_PIXEL_RATE_CNTL)/sizeof(mmOTG2_PHYPLL_PIXEL_RATE_CNTL[0]), 0, 0 }, + { "mmOTG3_PIXEL_RATE_CNTL", REG_MMIO, 0x008c, 1, &mmOTG3_PIXEL_RATE_CNTL[0], sizeof(mmOTG3_PIXEL_RATE_CNTL)/sizeof(mmOTG3_PIXEL_RATE_CNTL[0]), 0, 0 }, + { "mmDP_DTO3_PHASE", REG_MMIO, 0x008d, 1, &mmDP_DTO3_PHASE[0], sizeof(mmDP_DTO3_PHASE)/sizeof(mmDP_DTO3_PHASE[0]), 0, 0 }, + { "mmDP_DTO3_MODULO", REG_MMIO, 0x008e, 1, &mmDP_DTO3_MODULO[0], sizeof(mmDP_DTO3_MODULO)/sizeof(mmDP_DTO3_MODULO[0]), 0, 0 }, + { "mmOTG3_PHYPLL_PIXEL_RATE_CNTL", REG_MMIO, 0x008f, 1, &mmOTG3_PHYPLL_PIXEL_RATE_CNTL[0], sizeof(mmOTG3_PHYPLL_PIXEL_RATE_CNTL)/sizeof(mmOTG3_PHYPLL_PIXEL_RATE_CNTL[0]), 0, 0 }, + { "mmOTG4_PIXEL_RATE_CNTL", REG_MMIO, 0x0090, 1, &mmOTG4_PIXEL_RATE_CNTL[0], sizeof(mmOTG4_PIXEL_RATE_CNTL)/sizeof(mmOTG4_PIXEL_RATE_CNTL[0]), 0, 0 }, + { "mmDP_DTO4_PHASE", REG_MMIO, 0x0091, 1, &mmDP_DTO4_PHASE[0], sizeof(mmDP_DTO4_PHASE)/sizeof(mmDP_DTO4_PHASE[0]), 0, 0 }, + { "mmDP_DTO4_MODULO", REG_MMIO, 0x0092, 1, &mmDP_DTO4_MODULO[0], sizeof(mmDP_DTO4_MODULO)/sizeof(mmDP_DTO4_MODULO[0]), 0, 0 }, + { "mmOTG4_PHYPLL_PIXEL_RATE_CNTL", REG_MMIO, 0x0093, 1, &mmOTG4_PHYPLL_PIXEL_RATE_CNTL[0], sizeof(mmOTG4_PHYPLL_PIXEL_RATE_CNTL)/sizeof(mmOTG4_PHYPLL_PIXEL_RATE_CNTL[0]), 0, 0 }, + { "mmOTG5_PIXEL_RATE_CNTL", REG_MMIO, 0x0094, 1, &mmOTG5_PIXEL_RATE_CNTL[0], sizeof(mmOTG5_PIXEL_RATE_CNTL)/sizeof(mmOTG5_PIXEL_RATE_CNTL[0]), 0, 0 }, + { "mmDP_DTO5_PHASE", REG_MMIO, 0x0095, 1, &mmDP_DTO5_PHASE[0], sizeof(mmDP_DTO5_PHASE)/sizeof(mmDP_DTO5_PHASE[0]), 0, 0 }, + { "mmDP_DTO5_MODULO", REG_MMIO, 0x0096, 1, &mmDP_DTO5_MODULO[0], sizeof(mmDP_DTO5_MODULO)/sizeof(mmDP_DTO5_MODULO[0]), 0, 0 }, + { "mmOTG5_PHYPLL_PIXEL_RATE_CNTL", REG_MMIO, 0x0097, 1, &mmOTG5_PHYPLL_PIXEL_RATE_CNTL[0], sizeof(mmOTG5_PHYPLL_PIXEL_RATE_CNTL)/sizeof(mmOTG5_PHYPLL_PIXEL_RATE_CNTL[0]), 0, 0 }, + { "mmDPPCLK_CGTT_BLK_CTRL_REG", REG_MMIO, 0x0098, 1, &mmDPPCLK_CGTT_BLK_CTRL_REG[0], sizeof(mmDPPCLK_CGTT_BLK_CTRL_REG)/sizeof(mmDPPCLK_CGTT_BLK_CTRL_REG[0]), 0, 0 }, + { "mmSYMCLKA_CLOCK_ENABLE", REG_MMIO, 0x00a0, 1, &mmSYMCLKA_CLOCK_ENABLE[0], sizeof(mmSYMCLKA_CLOCK_ENABLE)/sizeof(mmSYMCLKA_CLOCK_ENABLE[0]), 0, 0 }, + { "mmSYMCLKB_CLOCK_ENABLE", REG_MMIO, 0x00a1, 1, &mmSYMCLKB_CLOCK_ENABLE[0], sizeof(mmSYMCLKB_CLOCK_ENABLE)/sizeof(mmSYMCLKB_CLOCK_ENABLE[0]), 0, 0 }, + { "mmSYMCLKC_CLOCK_ENABLE", REG_MMIO, 0x00a2, 1, &mmSYMCLKC_CLOCK_ENABLE[0], sizeof(mmSYMCLKC_CLOCK_ENABLE)/sizeof(mmSYMCLKC_CLOCK_ENABLE[0]), 0, 0 }, + { "mmSYMCLKD_CLOCK_ENABLE", REG_MMIO, 0x00a3, 1, &mmSYMCLKD_CLOCK_ENABLE[0], sizeof(mmSYMCLKD_CLOCK_ENABLE)/sizeof(mmSYMCLKD_CLOCK_ENABLE[0]), 0, 0 }, + { "mmSYMCLKE_CLOCK_ENABLE", REG_MMIO, 0x00a4, 1, &mmSYMCLKE_CLOCK_ENABLE[0], sizeof(mmSYMCLKE_CLOCK_ENABLE)/sizeof(mmSYMCLKE_CLOCK_ENABLE[0]), 0, 0 }, + { "mmSYMCLKF_CLOCK_ENABLE", REG_MMIO, 0x00a5, 1, &mmSYMCLKF_CLOCK_ENABLE[0], sizeof(mmSYMCLKF_CLOCK_ENABLE)/sizeof(mmSYMCLKF_CLOCK_ENABLE[0]), 0, 0 }, + { "mmDCCG_SOFT_RESET", REG_MMIO, 0x00a6, 1, &mmDCCG_SOFT_RESET[0], sizeof(mmDCCG_SOFT_RESET)/sizeof(mmDCCG_SOFT_RESET[0]), 0, 0 }, + { "mmDVOACLKD_CNTL", REG_MMIO, 0x00a8, 1, &mmDVOACLKD_CNTL[0], sizeof(mmDVOACLKD_CNTL)/sizeof(mmDVOACLKD_CNTL[0]), 0, 0 }, + { "mmDVOACLKC_MVP_CNTL", REG_MMIO, 0x00a9, 1, &mmDVOACLKC_MVP_CNTL[0], sizeof(mmDVOACLKC_MVP_CNTL)/sizeof(mmDVOACLKC_MVP_CNTL[0]), 0, 0 }, + { "mmDVOACLKC_CNTL", REG_MMIO, 0x00aa, 1, &mmDVOACLKC_CNTL[0], sizeof(mmDVOACLKC_CNTL)/sizeof(mmDVOACLKC_CNTL[0]), 0, 0 }, + { "mmDCCG_AUDIO_DTO_SOURCE", REG_MMIO, 0x00ab, 1, &mmDCCG_AUDIO_DTO_SOURCE[0], sizeof(mmDCCG_AUDIO_DTO_SOURCE)/sizeof(mmDCCG_AUDIO_DTO_SOURCE[0]), 0, 0 }, + { "mmDCCG_AUDIO_DTO0_PHASE", REG_MMIO, 0x00ac, 1, &mmDCCG_AUDIO_DTO0_PHASE[0], sizeof(mmDCCG_AUDIO_DTO0_PHASE)/sizeof(mmDCCG_AUDIO_DTO0_PHASE[0]), 0, 0 }, + { "mmDCCG_AUDIO_DTO0_MODULE", REG_MMIO, 0x00ad, 1, &mmDCCG_AUDIO_DTO0_MODULE[0], sizeof(mmDCCG_AUDIO_DTO0_MODULE)/sizeof(mmDCCG_AUDIO_DTO0_MODULE[0]), 0, 0 }, + { "mmDCCG_AUDIO_DTO1_PHASE", REG_MMIO, 0x00ae, 1, &mmDCCG_AUDIO_DTO1_PHASE[0], sizeof(mmDCCG_AUDIO_DTO1_PHASE)/sizeof(mmDCCG_AUDIO_DTO1_PHASE[0]), 0, 0 }, + { "mmDCCG_AUDIO_DTO1_MODULE", REG_MMIO, 0x00af, 1, &mmDCCG_AUDIO_DTO1_MODULE[0], sizeof(mmDCCG_AUDIO_DTO1_MODULE)/sizeof(mmDCCG_AUDIO_DTO1_MODULE[0]), 0, 0 }, + { "mmDCCG_VSYNC_OTG0_LATCH_VALUE", REG_MMIO, 0x00b0, 1, &mmDCCG_VSYNC_OTG0_LATCH_VALUE[0], sizeof(mmDCCG_VSYNC_OTG0_LATCH_VALUE)/sizeof(mmDCCG_VSYNC_OTG0_LATCH_VALUE[0]), 0, 0 }, + { "mmDCCG_VSYNC_OTG1_LATCH_VALUE", REG_MMIO, 0x00b1, 1, &mmDCCG_VSYNC_OTG1_LATCH_VALUE[0], sizeof(mmDCCG_VSYNC_OTG1_LATCH_VALUE)/sizeof(mmDCCG_VSYNC_OTG1_LATCH_VALUE[0]), 0, 0 }, + { "mmDCCG_VSYNC_OTG2_LATCH_VALUE", REG_MMIO, 0x00b2, 1, &mmDCCG_VSYNC_OTG2_LATCH_VALUE[0], sizeof(mmDCCG_VSYNC_OTG2_LATCH_VALUE)/sizeof(mmDCCG_VSYNC_OTG2_LATCH_VALUE[0]), 0, 0 }, + { "mmDCCG_VSYNC_OTG3_LATCH_VALUE", REG_MMIO, 0x00b3, 1, &mmDCCG_VSYNC_OTG3_LATCH_VALUE[0], sizeof(mmDCCG_VSYNC_OTG3_LATCH_VALUE)/sizeof(mmDCCG_VSYNC_OTG3_LATCH_VALUE[0]), 0, 0 }, + { "mmDCCG_VSYNC_OTG4_LATCH_VALUE", REG_MMIO, 0x00b4, 1, &mmDCCG_VSYNC_OTG4_LATCH_VALUE[0], sizeof(mmDCCG_VSYNC_OTG4_LATCH_VALUE)/sizeof(mmDCCG_VSYNC_OTG4_LATCH_VALUE[0]), 0, 0 }, + { "mmDCCG_VSYNC_OTG5_LATCH_VALUE", REG_MMIO, 0x00b5, 1, &mmDCCG_VSYNC_OTG5_LATCH_VALUE[0], sizeof(mmDCCG_VSYNC_OTG5_LATCH_VALUE)/sizeof(mmDCCG_VSYNC_OTG5_LATCH_VALUE[0]), 0, 0 }, + { "mmDCCG_VSYNC_CNT_CTRL", REG_MMIO, 0x00b8, 1, &mmDCCG_VSYNC_CNT_CTRL[0], sizeof(mmDCCG_VSYNC_CNT_CTRL)/sizeof(mmDCCG_VSYNC_CNT_CTRL[0]), 0, 0 }, + { "mmDCCG_VSYNC_CNT_INT_CTRL", REG_MMIO, 0x00b9, 1, &mmDCCG_VSYNC_CNT_INT_CTRL[0], sizeof(mmDCCG_VSYNC_CNT_INT_CTRL)/sizeof(mmDCCG_VSYNC_CNT_INT_CTRL[0]), 0, 0 }, + { "mmDCCG_TEST_CLK_SEL", REG_MMIO, 0x00be, 1, &mmDCCG_TEST_CLK_SEL[0], sizeof(mmDCCG_TEST_CLK_SEL)/sizeof(mmDCCG_TEST_CLK_SEL[0]), 0, 0 }, + { "mmDENTIST_DISPCLK_CNTL", REG_MMIO, 0x0064, 1, &mmDENTIST_DISPCLK_CNTL[0], sizeof(mmDENTIST_DISPCLK_CNTL)/sizeof(mmDENTIST_DISPCLK_CNTL[0]), 0, 0 }, + { "mmDC_PERFMON0_PERFCOUNTER_CNTL", REG_MMIO, 0x0000, 2, &mmDC_PERFMON0_PERFCOUNTER_CNTL[0], sizeof(mmDC_PERFMON0_PERFCOUNTER_CNTL)/sizeof(mmDC_PERFMON0_PERFCOUNTER_CNTL[0]), 0, 0 }, + { "mmDC_PERFMON0_PERFCOUNTER_CNTL2", REG_MMIO, 0x0001, 2, &mmDC_PERFMON0_PERFCOUNTER_CNTL2[0], sizeof(mmDC_PERFMON0_PERFCOUNTER_CNTL2)/sizeof(mmDC_PERFMON0_PERFCOUNTER_CNTL2[0]), 0, 0 }, + { "mmDC_PERFMON0_PERFCOUNTER_STATE", REG_MMIO, 0x0002, 2, &mmDC_PERFMON0_PERFCOUNTER_STATE[0], sizeof(mmDC_PERFMON0_PERFCOUNTER_STATE)/sizeof(mmDC_PERFMON0_PERFCOUNTER_STATE[0]), 0, 0 }, + { "mmDC_PERFMON0_PERFMON_CNTL", REG_MMIO, 0x0003, 2, &mmDC_PERFMON0_PERFMON_CNTL[0], sizeof(mmDC_PERFMON0_PERFMON_CNTL)/sizeof(mmDC_PERFMON0_PERFMON_CNTL[0]), 0, 0 }, + { "mmDC_PERFMON0_PERFMON_CNTL2", REG_MMIO, 0x0004, 2, &mmDC_PERFMON0_PERFMON_CNTL2[0], sizeof(mmDC_PERFMON0_PERFMON_CNTL2)/sizeof(mmDC_PERFMON0_PERFMON_CNTL2[0]), 0, 0 }, + { "mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC", REG_MMIO, 0x0005, 2, &mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC[0], sizeof(mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC)/sizeof(mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC[0]), 0, 0 }, + { "mmDC_PERFMON0_PERFMON_CVALUE_LOW", REG_MMIO, 0x0006, 2, &mmDC_PERFMON0_PERFMON_CVALUE_LOW[0], sizeof(mmDC_PERFMON0_PERFMON_CVALUE_LOW)/sizeof(mmDC_PERFMON0_PERFMON_CVALUE_LOW[0]), 0, 0 }, + { "mmDC_PERFMON0_PERFMON_HI", REG_MMIO, 0x0007, 2, &mmDC_PERFMON0_PERFMON_HI[0], sizeof(mmDC_PERFMON0_PERFMON_HI)/sizeof(mmDC_PERFMON0_PERFMON_HI[0]), 0, 0 }, + { "mmDC_PERFMON0_PERFMON_LOW", REG_MMIO, 0x0008, 2, &mmDC_PERFMON0_PERFMON_LOW[0], sizeof(mmDC_PERFMON0_PERFMON_LOW)/sizeof(mmDC_PERFMON0_PERFMON_LOW[0]), 0, 0 }, + { "mmDC_PERFMON1_PERFCOUNTER_CNTL", REG_MMIO, 0x000c, 2, &mmDC_PERFMON1_PERFCOUNTER_CNTL[0], sizeof(mmDC_PERFMON1_PERFCOUNTER_CNTL)/sizeof(mmDC_PERFMON1_PERFCOUNTER_CNTL[0]), 0, 0 }, + { "mmDC_PERFMON1_PERFCOUNTER_CNTL2", REG_MMIO, 0x000d, 2, &mmDC_PERFMON1_PERFCOUNTER_CNTL2[0], sizeof(mmDC_PERFMON1_PERFCOUNTER_CNTL2)/sizeof(mmDC_PERFMON1_PERFCOUNTER_CNTL2[0]), 0, 0 }, + { "mmDC_PERFMON1_PERFCOUNTER_STATE", REG_MMIO, 0x000e, 2, &mmDC_PERFMON1_PERFCOUNTER_STATE[0], sizeof(mmDC_PERFMON1_PERFCOUNTER_STATE)/sizeof(mmDC_PERFMON1_PERFCOUNTER_STATE[0]), 0, 0 }, + { "mmDC_PERFMON1_PERFMON_CNTL", REG_MMIO, 0x000f, 2, &mmDC_PERFMON1_PERFMON_CNTL[0], sizeof(mmDC_PERFMON1_PERFMON_CNTL)/sizeof(mmDC_PERFMON1_PERFMON_CNTL[0]), 0, 0 }, + { "mmDC_PERFMON1_PERFMON_CNTL2", REG_MMIO, 0x0010, 2, &mmDC_PERFMON1_PERFMON_CNTL2[0], sizeof(mmDC_PERFMON1_PERFMON_CNTL2)/sizeof(mmDC_PERFMON1_PERFMON_CNTL2[0]), 0, 0 }, + { "mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC", REG_MMIO, 0x0011, 2, &mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC[0], sizeof(mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC)/sizeof(mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC[0]), 0, 0 }, + { "mmDC_PERFMON1_PERFMON_CVALUE_LOW", REG_MMIO, 0x0012, 2, &mmDC_PERFMON1_PERFMON_CVALUE_LOW[0], sizeof(mmDC_PERFMON1_PERFMON_CVALUE_LOW)/sizeof(mmDC_PERFMON1_PERFMON_CVALUE_LOW[0]), 0, 0 }, + { "mmDC_PERFMON1_PERFMON_HI", REG_MMIO, 0x0013, 2, &mmDC_PERFMON1_PERFMON_HI[0], sizeof(mmDC_PERFMON1_PERFMON_HI)/sizeof(mmDC_PERFMON1_PERFMON_HI[0]), 0, 0 }, + { "mmDC_PERFMON1_PERFMON_LOW", REG_MMIO, 0x0014, 2, &mmDC_PERFMON1_PERFMON_LOW[0], sizeof(mmDC_PERFMON1_PERFMON_LOW)/sizeof(mmDC_PERFMON1_PERFMON_LOW[0]), 0, 0 }, + { "mmPLL_MACRO_CNTL_RESERVED0", REG_MMIO, 0x0018, 2, &mmPLL_MACRO_CNTL_RESERVED0[0], sizeof(mmPLL_MACRO_CNTL_RESERVED0)/sizeof(mmPLL_MACRO_CNTL_RESERVED0[0]), 0, 0 }, + { "mmPLL_MACRO_CNTL_RESERVED1", REG_MMIO, 0x0019, 2, &mmPLL_MACRO_CNTL_RESERVED1[0], sizeof(mmPLL_MACRO_CNTL_RESERVED1)/sizeof(mmPLL_MACRO_CNTL_RESERVED1[0]), 0, 0 }, + { "mmPLL_MACRO_CNTL_RESERVED2", REG_MMIO, 0x001a, 2, &mmPLL_MACRO_CNTL_RESERVED2[0], sizeof(mmPLL_MACRO_CNTL_RESERVED2)/sizeof(mmPLL_MACRO_CNTL_RESERVED2[0]), 0, 0 }, + { "mmPLL_MACRO_CNTL_RESERVED3", REG_MMIO, 0x001b, 2, &mmPLL_MACRO_CNTL_RESERVED3[0], sizeof(mmPLL_MACRO_CNTL_RESERVED3)/sizeof(mmPLL_MACRO_CNTL_RESERVED3[0]), 0, 0 }, + { "mmPLL_MACRO_CNTL_RESERVED4", REG_MMIO, 0x001c, 2, &mmPLL_MACRO_CNTL_RESERVED4[0], sizeof(mmPLL_MACRO_CNTL_RESERVED4)/sizeof(mmPLL_MACRO_CNTL_RESERVED4[0]), 0, 0 }, + { "mmPLL_MACRO_CNTL_RESERVED5", REG_MMIO, 0x001d, 2, &mmPLL_MACRO_CNTL_RESERVED5[0], sizeof(mmPLL_MACRO_CNTL_RESERVED5)/sizeof(mmPLL_MACRO_CNTL_RESERVED5[0]), 0, 0 }, + { "mmPLL_MACRO_CNTL_RESERVED6", REG_MMIO, 0x001e, 2, &mmPLL_MACRO_CNTL_RESERVED6[0], sizeof(mmPLL_MACRO_CNTL_RESERVED6)/sizeof(mmPLL_MACRO_CNTL_RESERVED6[0]), 0, 0 }, + { "mmPLL_MACRO_CNTL_RESERVED7", REG_MMIO, 0x001f, 2, &mmPLL_MACRO_CNTL_RESERVED7[0], sizeof(mmPLL_MACRO_CNTL_RESERVED7)/sizeof(mmPLL_MACRO_CNTL_RESERVED7[0]), 0, 0 }, + { "mmPLL_MACRO_CNTL_RESERVED8", REG_MMIO, 0x0020, 2, &mmPLL_MACRO_CNTL_RESERVED8[0], sizeof(mmPLL_MACRO_CNTL_RESERVED8)/sizeof(mmPLL_MACRO_CNTL_RESERVED8[0]), 0, 0 }, + { "mmPLL_MACRO_CNTL_RESERVED9", REG_MMIO, 0x0021, 2, &mmPLL_MACRO_CNTL_RESERVED9[0], sizeof(mmPLL_MACRO_CNTL_RESERVED9)/sizeof(mmPLL_MACRO_CNTL_RESERVED9[0]), 0, 0 }, + { "mmPLL_MACRO_CNTL_RESERVED10", REG_MMIO, 0x0022, 2, &mmPLL_MACRO_CNTL_RESERVED10[0], sizeof(mmPLL_MACRO_CNTL_RESERVED10)/sizeof(mmPLL_MACRO_CNTL_RESERVED10[0]), 0, 0 }, + { "mmPLL_MACRO_CNTL_RESERVED11", REG_MMIO, 0x0023, 2, &mmPLL_MACRO_CNTL_RESERVED11[0], sizeof(mmPLL_MACRO_CNTL_RESERVED11)/sizeof(mmPLL_MACRO_CNTL_RESERVED11[0]), 0, 0 }, + { "mmPLL_MACRO_CNTL_RESERVED12", REG_MMIO, 0x0024, 2, &mmPLL_MACRO_CNTL_RESERVED12[0], sizeof(mmPLL_MACRO_CNTL_RESERVED12)/sizeof(mmPLL_MACRO_CNTL_RESERVED12[0]), 0, 0 }, + { "mmPLL_MACRO_CNTL_RESERVED13", REG_MMIO, 0x0025, 2, &mmPLL_MACRO_CNTL_RESERVED13[0], sizeof(mmPLL_MACRO_CNTL_RESERVED13)/sizeof(mmPLL_MACRO_CNTL_RESERVED13[0]), 0, 0 }, + { "mmPLL_MACRO_CNTL_RESERVED14", REG_MMIO, 0x0026, 2, &mmPLL_MACRO_CNTL_RESERVED14[0], sizeof(mmPLL_MACRO_CNTL_RESERVED14)/sizeof(mmPLL_MACRO_CNTL_RESERVED14[0]), 0, 0 }, + { "mmPLL_MACRO_CNTL_RESERVED15", REG_MMIO, 0x0027, 2, &mmPLL_MACRO_CNTL_RESERVED15[0], sizeof(mmPLL_MACRO_CNTL_RESERVED15)/sizeof(mmPLL_MACRO_CNTL_RESERVED15[0]), 0, 0 }, + { "mmPLL_MACRO_CNTL_RESERVED16", REG_MMIO, 0x0028, 2, &mmPLL_MACRO_CNTL_RESERVED16[0], sizeof(mmPLL_MACRO_CNTL_RESERVED16)/sizeof(mmPLL_MACRO_CNTL_RESERVED16[0]), 0, 0 }, + { "mmPLL_MACRO_CNTL_RESERVED17", REG_MMIO, 0x0029, 2, &mmPLL_MACRO_CNTL_RESERVED17[0], sizeof(mmPLL_MACRO_CNTL_RESERVED17)/sizeof(mmPLL_MACRO_CNTL_RESERVED17[0]), 0, 0 }, + { "mmPLL_MACRO_CNTL_RESERVED18", REG_MMIO, 0x002a, 2, &mmPLL_MACRO_CNTL_RESERVED18[0], sizeof(mmPLL_MACRO_CNTL_RESERVED18)/sizeof(mmPLL_MACRO_CNTL_RESERVED18[0]), 0, 0 }, + { "mmPLL_MACRO_CNTL_RESERVED19", REG_MMIO, 0x002b, 2, &mmPLL_MACRO_CNTL_RESERVED19[0], sizeof(mmPLL_MACRO_CNTL_RESERVED19)/sizeof(mmPLL_MACRO_CNTL_RESERVED19[0]), 0, 0 }, + { "mmPLL_MACRO_CNTL_RESERVED20", REG_MMIO, 0x002c, 2, &mmPLL_MACRO_CNTL_RESERVED20[0], sizeof(mmPLL_MACRO_CNTL_RESERVED20)/sizeof(mmPLL_MACRO_CNTL_RESERVED20[0]), 0, 0 }, + { "mmPLL_MACRO_CNTL_RESERVED21", REG_MMIO, 0x002d, 2, &mmPLL_MACRO_CNTL_RESERVED21[0], sizeof(mmPLL_MACRO_CNTL_RESERVED21)/sizeof(mmPLL_MACRO_CNTL_RESERVED21[0]), 0, 0 }, + { "mmPLL_MACRO_CNTL_RESERVED22", REG_MMIO, 0x002e, 2, &mmPLL_MACRO_CNTL_RESERVED22[0], sizeof(mmPLL_MACRO_CNTL_RESERVED22)/sizeof(mmPLL_MACRO_CNTL_RESERVED22[0]), 0, 0 }, + { "mmPLL_MACRO_CNTL_RESERVED23", REG_MMIO, 0x002f, 2, &mmPLL_MACRO_CNTL_RESERVED23[0], sizeof(mmPLL_MACRO_CNTL_RESERVED23)/sizeof(mmPLL_MACRO_CNTL_RESERVED23[0]), 0, 0 }, + { "mmPLL_MACRO_CNTL_RESERVED24", REG_MMIO, 0x0030, 2, &mmPLL_MACRO_CNTL_RESERVED24[0], sizeof(mmPLL_MACRO_CNTL_RESERVED24)/sizeof(mmPLL_MACRO_CNTL_RESERVED24[0]), 0, 0 }, + { "mmPLL_MACRO_CNTL_RESERVED25", REG_MMIO, 0x0031, 2, &mmPLL_MACRO_CNTL_RESERVED25[0], sizeof(mmPLL_MACRO_CNTL_RESERVED25)/sizeof(mmPLL_MACRO_CNTL_RESERVED25[0]), 0, 0 }, + { "mmPLL_MACRO_CNTL_RESERVED26", REG_MMIO, 0x0032, 2, &mmPLL_MACRO_CNTL_RESERVED26[0], sizeof(mmPLL_MACRO_CNTL_RESERVED26)/sizeof(mmPLL_MACRO_CNTL_RESERVED26[0]), 0, 0 }, + { "mmPLL_MACRO_CNTL_RESERVED27", REG_MMIO, 0x0033, 2, &mmPLL_MACRO_CNTL_RESERVED27[0], sizeof(mmPLL_MACRO_CNTL_RESERVED27)/sizeof(mmPLL_MACRO_CNTL_RESERVED27[0]), 0, 0 }, + { "mmPLL_MACRO_CNTL_RESERVED28", REG_MMIO, 0x0034, 2, &mmPLL_MACRO_CNTL_RESERVED28[0], sizeof(mmPLL_MACRO_CNTL_RESERVED28)/sizeof(mmPLL_MACRO_CNTL_RESERVED28[0]), 0, 0 }, + { "mmPLL_MACRO_CNTL_RESERVED29", REG_MMIO, 0x0035, 2, &mmPLL_MACRO_CNTL_RESERVED29[0], sizeof(mmPLL_MACRO_CNTL_RESERVED29)/sizeof(mmPLL_MACRO_CNTL_RESERVED29[0]), 0, 0 }, + { "mmPLL_MACRO_CNTL_RESERVED30", REG_MMIO, 0x0036, 2, &mmPLL_MACRO_CNTL_RESERVED30[0], sizeof(mmPLL_MACRO_CNTL_RESERVED30)/sizeof(mmPLL_MACRO_CNTL_RESERVED30[0]), 0, 0 }, + { "mmPLL_MACRO_CNTL_RESERVED31", REG_MMIO, 0x0037, 2, &mmPLL_MACRO_CNTL_RESERVED31[0], sizeof(mmPLL_MACRO_CNTL_RESERVED31)/sizeof(mmPLL_MACRO_CNTL_RESERVED31[0]), 0, 0 }, + { "mmPLL_MACRO_CNTL_RESERVED32", REG_MMIO, 0x0038, 2, &mmPLL_MACRO_CNTL_RESERVED32[0], sizeof(mmPLL_MACRO_CNTL_RESERVED32)/sizeof(mmPLL_MACRO_CNTL_RESERVED32[0]), 0, 0 }, + { "mmPLL_MACRO_CNTL_RESERVED33", REG_MMIO, 0x0039, 2, &mmPLL_MACRO_CNTL_RESERVED33[0], sizeof(mmPLL_MACRO_CNTL_RESERVED33)/sizeof(mmPLL_MACRO_CNTL_RESERVED33[0]), 0, 0 }, + { "mmPLL_MACRO_CNTL_RESERVED34", REG_MMIO, 0x003a, 2, &mmPLL_MACRO_CNTL_RESERVED34[0], sizeof(mmPLL_MACRO_CNTL_RESERVED34)/sizeof(mmPLL_MACRO_CNTL_RESERVED34[0]), 0, 0 }, + { "mmPLL_MACRO_CNTL_RESERVED35", REG_MMIO, 0x003b, 2, &mmPLL_MACRO_CNTL_RESERVED35[0], sizeof(mmPLL_MACRO_CNTL_RESERVED35)/sizeof(mmPLL_MACRO_CNTL_RESERVED35[0]), 0, 0 }, + { "mmPLL_MACRO_CNTL_RESERVED36", REG_MMIO, 0x003c, 2, &mmPLL_MACRO_CNTL_RESERVED36[0], sizeof(mmPLL_MACRO_CNTL_RESERVED36)/sizeof(mmPLL_MACRO_CNTL_RESERVED36[0]), 0, 0 }, + { "mmPLL_MACRO_CNTL_RESERVED37", REG_MMIO, 0x003d, 2, &mmPLL_MACRO_CNTL_RESERVED37[0], sizeof(mmPLL_MACRO_CNTL_RESERVED37)/sizeof(mmPLL_MACRO_CNTL_RESERVED37[0]), 0, 0 }, + { "mmPLL_MACRO_CNTL_RESERVED38", REG_MMIO, 0x003e, 2, &mmPLL_MACRO_CNTL_RESERVED38[0], sizeof(mmPLL_MACRO_CNTL_RESERVED38)/sizeof(mmPLL_MACRO_CNTL_RESERVED38[0]), 0, 0 }, + { "mmPLL_MACRO_CNTL_RESERVED39", REG_MMIO, 0x003f, 2, &mmPLL_MACRO_CNTL_RESERVED39[0], sizeof(mmPLL_MACRO_CNTL_RESERVED39)/sizeof(mmPLL_MACRO_CNTL_RESERVED39[0]), 0, 0 }, + { "mmPLL_MACRO_CNTL_RESERVED40", REG_MMIO, 0x0040, 2, &mmPLL_MACRO_CNTL_RESERVED40[0], sizeof(mmPLL_MACRO_CNTL_RESERVED40)/sizeof(mmPLL_MACRO_CNTL_RESERVED40[0]), 0, 0 }, + { "mmPLL_MACRO_CNTL_RESERVED41", REG_MMIO, 0x0041, 2, &mmPLL_MACRO_CNTL_RESERVED41[0], sizeof(mmPLL_MACRO_CNTL_RESERVED41)/sizeof(mmPLL_MACRO_CNTL_RESERVED41[0]), 0, 0 }, + { "mmRBBMIF_TIMEOUT", REG_MMIO, 0x0055, 2, &mmRBBMIF_TIMEOUT[0], sizeof(mmRBBMIF_TIMEOUT)/sizeof(mmRBBMIF_TIMEOUT[0]), 0, 0 }, + { "mmRBBMIF_STATUS", REG_MMIO, 0x0056, 2, &mmRBBMIF_STATUS[0], sizeof(mmRBBMIF_STATUS)/sizeof(mmRBBMIF_STATUS[0]), 0, 0 }, + { "mmRBBMIF_INT_STATUS", REG_MMIO, 0x0057, 2, &mmRBBMIF_INT_STATUS[0], sizeof(mmRBBMIF_INT_STATUS)/sizeof(mmRBBMIF_INT_STATUS[0]), 0, 0 }, + { "mmRBBMIF_TIMEOUT_DIS", REG_MMIO, 0x0058, 2, &mmRBBMIF_TIMEOUT_DIS[0], sizeof(mmRBBMIF_TIMEOUT_DIS)/sizeof(mmRBBMIF_TIMEOUT_DIS[0]), 0, 0 }, + { "mmRBBMIF_STATUS_FLAG", REG_MMIO, 0x0059, 2, &mmRBBMIF_STATUS_FLAG[0], sizeof(mmRBBMIF_STATUS_FLAG)/sizeof(mmRBBMIF_STATUS_FLAG[0]), 0, 0 }, + { "mmDOMAIN0_PG_CONFIG", REG_MMIO, 0x008a, 2, &mmDOMAIN0_PG_CONFIG[0], sizeof(mmDOMAIN0_PG_CONFIG)/sizeof(mmDOMAIN0_PG_CONFIG[0]), 0, 0 }, + { "mmDOMAIN0_PG_STATUS", REG_MMIO, 0x008b, 2, &mmDOMAIN0_PG_STATUS[0], sizeof(mmDOMAIN0_PG_STATUS)/sizeof(mmDOMAIN0_PG_STATUS[0]), 0, 0 }, + { "mmDOMAIN1_PG_CONFIG", REG_MMIO, 0x008c, 2, &mmDOMAIN1_PG_CONFIG[0], sizeof(mmDOMAIN1_PG_CONFIG)/sizeof(mmDOMAIN1_PG_CONFIG[0]), 0, 0 }, + { "mmDOMAIN1_PG_STATUS", REG_MMIO, 0x008d, 2, &mmDOMAIN1_PG_STATUS[0], sizeof(mmDOMAIN1_PG_STATUS)/sizeof(mmDOMAIN1_PG_STATUS[0]), 0, 0 }, + { "mmDOMAIN2_PG_CONFIG", REG_MMIO, 0x008e, 2, &mmDOMAIN2_PG_CONFIG[0], sizeof(mmDOMAIN2_PG_CONFIG)/sizeof(mmDOMAIN2_PG_CONFIG[0]), 0, 0 }, + { "mmDOMAIN2_PG_STATUS", REG_MMIO, 0x008f, 2, &mmDOMAIN2_PG_STATUS[0], sizeof(mmDOMAIN2_PG_STATUS)/sizeof(mmDOMAIN2_PG_STATUS[0]), 0, 0 }, + { "mmDOMAIN3_PG_CONFIG", REG_MMIO, 0x0090, 2, &mmDOMAIN3_PG_CONFIG[0], sizeof(mmDOMAIN3_PG_CONFIG)/sizeof(mmDOMAIN3_PG_CONFIG[0]), 0, 0 }, + { "mmDOMAIN3_PG_STATUS", REG_MMIO, 0x0091, 2, &mmDOMAIN3_PG_STATUS[0], sizeof(mmDOMAIN3_PG_STATUS)/sizeof(mmDOMAIN3_PG_STATUS[0]), 0, 0 }, + { "mmDOMAIN4_PG_CONFIG", REG_MMIO, 0x0092, 2, &mmDOMAIN4_PG_CONFIG[0], sizeof(mmDOMAIN4_PG_CONFIG)/sizeof(mmDOMAIN4_PG_CONFIG[0]), 0, 0 }, + { "mmDOMAIN4_PG_STATUS", REG_MMIO, 0x0093, 2, &mmDOMAIN4_PG_STATUS[0], sizeof(mmDOMAIN4_PG_STATUS)/sizeof(mmDOMAIN4_PG_STATUS[0]), 0, 0 }, + { "mmDOMAIN5_PG_CONFIG", REG_MMIO, 0x0094, 2, &mmDOMAIN5_PG_CONFIG[0], sizeof(mmDOMAIN5_PG_CONFIG)/sizeof(mmDOMAIN5_PG_CONFIG[0]), 0, 0 }, + { "mmDOMAIN5_PG_STATUS", REG_MMIO, 0x0095, 2, &mmDOMAIN5_PG_STATUS[0], sizeof(mmDOMAIN5_PG_STATUS)/sizeof(mmDOMAIN5_PG_STATUS[0]), 0, 0 }, + { "mmDOMAIN6_PG_CONFIG", REG_MMIO, 0x0096, 2, &mmDOMAIN6_PG_CONFIG[0], sizeof(mmDOMAIN6_PG_CONFIG)/sizeof(mmDOMAIN6_PG_CONFIG[0]), 0, 0 }, + { "mmDOMAIN6_PG_STATUS", REG_MMIO, 0x0097, 2, &mmDOMAIN6_PG_STATUS[0], sizeof(mmDOMAIN6_PG_STATUS)/sizeof(mmDOMAIN6_PG_STATUS[0]), 0, 0 }, + { "mmDOMAIN7_PG_CONFIG", REG_MMIO, 0x0098, 2, &mmDOMAIN7_PG_CONFIG[0], sizeof(mmDOMAIN7_PG_CONFIG)/sizeof(mmDOMAIN7_PG_CONFIG[0]), 0, 0 }, + { "mmDOMAIN7_PG_STATUS", REG_MMIO, 0x0099, 2, &mmDOMAIN7_PG_STATUS[0], sizeof(mmDOMAIN7_PG_STATUS)/sizeof(mmDOMAIN7_PG_STATUS[0]), 0, 0 }, + { "mmDOMAIN8_PG_CONFIG", REG_MMIO, 0x009a, 2, &mmDOMAIN8_PG_CONFIG[0], sizeof(mmDOMAIN8_PG_CONFIG)/sizeof(mmDOMAIN8_PG_CONFIG[0]), 0, 0 }, + { "mmDOMAIN8_PG_STATUS", REG_MMIO, 0x009b, 2, &mmDOMAIN8_PG_STATUS[0], sizeof(mmDOMAIN8_PG_STATUS)/sizeof(mmDOMAIN8_PG_STATUS[0]), 0, 0 }, + { "mmDOMAIN9_PG_CONFIG", REG_MMIO, 0x009c, 2, &mmDOMAIN9_PG_CONFIG[0], sizeof(mmDOMAIN9_PG_CONFIG)/sizeof(mmDOMAIN9_PG_CONFIG[0]), 0, 0 }, + { "mmDOMAIN9_PG_STATUS", REG_MMIO, 0x009d, 2, &mmDOMAIN9_PG_STATUS[0], sizeof(mmDOMAIN9_PG_STATUS)/sizeof(mmDOMAIN9_PG_STATUS[0]), 0, 0 }, + { "mmDOMAIN10_PG_CONFIG", REG_MMIO, 0x009e, 2, &mmDOMAIN10_PG_CONFIG[0], sizeof(mmDOMAIN10_PG_CONFIG)/sizeof(mmDOMAIN10_PG_CONFIG[0]), 0, 0 }, + { "mmDOMAIN10_PG_STATUS", REG_MMIO, 0x009f, 2, &mmDOMAIN10_PG_STATUS[0], sizeof(mmDOMAIN10_PG_STATUS)/sizeof(mmDOMAIN10_PG_STATUS[0]), 0, 0 }, + { "mmDOMAIN11_PG_CONFIG", REG_MMIO, 0x00a0, 2, &mmDOMAIN11_PG_CONFIG[0], sizeof(mmDOMAIN11_PG_CONFIG)/sizeof(mmDOMAIN11_PG_CONFIG[0]), 0, 0 }, + { "mmDOMAIN11_PG_STATUS", REG_MMIO, 0x00a1, 2, &mmDOMAIN11_PG_STATUS[0], sizeof(mmDOMAIN11_PG_STATUS)/sizeof(mmDOMAIN11_PG_STATUS[0]), 0, 0 }, + { "mmDOMAIN12_PG_CONFIG", REG_MMIO, 0x00a2, 2, &mmDOMAIN12_PG_CONFIG[0], sizeof(mmDOMAIN12_PG_CONFIG)/sizeof(mmDOMAIN12_PG_CONFIG[0]), 0, 0 }, + { "mmDOMAIN12_PG_STATUS", REG_MMIO, 0x00a3, 2, &mmDOMAIN12_PG_STATUS[0], sizeof(mmDOMAIN12_PG_STATUS)/sizeof(mmDOMAIN12_PG_STATUS[0]), 0, 0 }, + { "mmDOMAIN13_PG_CONFIG", REG_MMIO, 0x00a4, 2, &mmDOMAIN13_PG_CONFIG[0], sizeof(mmDOMAIN13_PG_CONFIG)/sizeof(mmDOMAIN13_PG_CONFIG[0]), 0, 0 }, + { "mmDOMAIN13_PG_STATUS", REG_MMIO, 0x00a5, 2, &mmDOMAIN13_PG_STATUS[0], sizeof(mmDOMAIN13_PG_STATUS)/sizeof(mmDOMAIN13_PG_STATUS[0]), 0, 0 }, + { "mmDOMAIN14_PG_CONFIG", REG_MMIO, 0x00a6, 2, &mmDOMAIN14_PG_CONFIG[0], sizeof(mmDOMAIN14_PG_CONFIG)/sizeof(mmDOMAIN14_PG_CONFIG[0]), 0, 0 }, + { "mmDOMAIN14_PG_STATUS", REG_MMIO, 0x00a7, 2, &mmDOMAIN14_PG_STATUS[0], sizeof(mmDOMAIN14_PG_STATUS)/sizeof(mmDOMAIN14_PG_STATUS[0]), 0, 0 }, + { "mmDOMAIN15_PG_CONFIG", REG_MMIO, 0x00a8, 2, &mmDOMAIN15_PG_CONFIG[0], sizeof(mmDOMAIN15_PG_CONFIG)/sizeof(mmDOMAIN15_PG_CONFIG[0]), 0, 0 }, + { "mmDOMAIN15_PG_STATUS", REG_MMIO, 0x00a9, 2, &mmDOMAIN15_PG_STATUS[0], sizeof(mmDOMAIN15_PG_STATUS)/sizeof(mmDOMAIN15_PG_STATUS[0]), 0, 0 }, + { "mmDCPG_INTERRUPT_STATUS", REG_MMIO, 0x00aa, 2, &mmDCPG_INTERRUPT_STATUS[0], sizeof(mmDCPG_INTERRUPT_STATUS)/sizeof(mmDCPG_INTERRUPT_STATUS[0]), 0, 0 }, + { "mmDCPG_INTERRUPT_CONTROL_1", REG_MMIO, 0x00ab, 2, &mmDCPG_INTERRUPT_CONTROL_1[0], sizeof(mmDCPG_INTERRUPT_CONTROL_1)/sizeof(mmDCPG_INTERRUPT_CONTROL_1[0]), 0, 0 }, + { "mmDCPG_INTERRUPT_CONTROL_2", REG_MMIO, 0x00ac, 2, &mmDCPG_INTERRUPT_CONTROL_2[0], sizeof(mmDCPG_INTERRUPT_CONTROL_2)/sizeof(mmDCPG_INTERRUPT_CONTROL_2[0]), 0, 0 }, + { "mmDC_IP_REQUEST_CNTL", REG_MMIO, 0x00ad, 2, &mmDC_IP_REQUEST_CNTL[0], sizeof(mmDC_IP_REQUEST_CNTL)/sizeof(mmDC_IP_REQUEST_CNTL[0]), 0, 0 }, + { "mmDC_PGCNTL_STATUS_REG", REG_MMIO, 0x00ae, 2, NULL, 0, 0, 0 }, + { "mmDC_PERFMON2_PERFCOUNTER_CNTL", REG_MMIO, 0x00be, 2, &mmDC_PERFMON2_PERFCOUNTER_CNTL[0], sizeof(mmDC_PERFMON2_PERFCOUNTER_CNTL)/sizeof(mmDC_PERFMON2_PERFCOUNTER_CNTL[0]), 0, 0 }, + { "mmDC_PERFMON2_PERFCOUNTER_CNTL2", REG_MMIO, 0x00bf, 2, &mmDC_PERFMON2_PERFCOUNTER_CNTL2[0], sizeof(mmDC_PERFMON2_PERFCOUNTER_CNTL2)/sizeof(mmDC_PERFMON2_PERFCOUNTER_CNTL2[0]), 0, 0 }, + { "mmDC_PERFMON2_PERFCOUNTER_STATE", REG_MMIO, 0x00c0, 2, &mmDC_PERFMON2_PERFCOUNTER_STATE[0], sizeof(mmDC_PERFMON2_PERFCOUNTER_STATE)/sizeof(mmDC_PERFMON2_PERFCOUNTER_STATE[0]), 0, 0 }, + { "mmDC_PERFMON2_PERFMON_CNTL", REG_MMIO, 0x00c1, 2, &mmDC_PERFMON2_PERFMON_CNTL[0], sizeof(mmDC_PERFMON2_PERFMON_CNTL)/sizeof(mmDC_PERFMON2_PERFMON_CNTL[0]), 0, 0 }, + { "mmDC_PERFMON2_PERFMON_CNTL2", REG_MMIO, 0x00c2, 2, &mmDC_PERFMON2_PERFMON_CNTL2[0], sizeof(mmDC_PERFMON2_PERFMON_CNTL2)/sizeof(mmDC_PERFMON2_PERFMON_CNTL2[0]), 0, 0 }, + { "mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC", REG_MMIO, 0x00c3, 2, &mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC[0], sizeof(mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC)/sizeof(mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC[0]), 0, 0 }, + { "mmDC_PERFMON2_PERFMON_CVALUE_LOW", REG_MMIO, 0x00c4, 2, &mmDC_PERFMON2_PERFMON_CVALUE_LOW[0], sizeof(mmDC_PERFMON2_PERFMON_CVALUE_LOW)/sizeof(mmDC_PERFMON2_PERFMON_CVALUE_LOW[0]), 0, 0 }, + { "mmDC_PERFMON2_PERFMON_HI", REG_MMIO, 0x00c5, 2, &mmDC_PERFMON2_PERFMON_HI[0], sizeof(mmDC_PERFMON2_PERFMON_HI)/sizeof(mmDC_PERFMON2_PERFMON_HI[0]), 0, 0 }, + { "mmDC_PERFMON2_PERFMON_LOW", REG_MMIO, 0x00c6, 2, &mmDC_PERFMON2_PERFMON_LOW[0], sizeof(mmDC_PERFMON2_PERFMON_LOW)/sizeof(mmDC_PERFMON2_PERFMON_LOW[0]), 0, 0 }, + { "mmCC_DC_PIPE_DIS", REG_MMIO, 0x00ca, 2, &mmCC_DC_PIPE_DIS[0], sizeof(mmCC_DC_PIPE_DIS)/sizeof(mmCC_DC_PIPE_DIS[0]), 0, 0 }, + { "mmDMU_CLK_CNTL", REG_MMIO, 0x00cb, 2, &mmDMU_CLK_CNTL[0], sizeof(mmDMU_CLK_CNTL)/sizeof(mmDMU_CLK_CNTL[0]), 0, 0 }, + { "mmDMU_MEM_PWR_CNTL", REG_MMIO, 0x00cc, 2, &mmDMU_MEM_PWR_CNTL[0], sizeof(mmDMU_MEM_PWR_CNTL)/sizeof(mmDMU_MEM_PWR_CNTL[0]), 0, 0 }, + { "mmDMCU_SMU_INTERRUPT_CNTL", REG_MMIO, 0x00cd, 2, &mmDMCU_SMU_INTERRUPT_CNTL[0], sizeof(mmDMCU_SMU_INTERRUPT_CNTL)/sizeof(mmDMCU_SMU_INTERRUPT_CNTL[0]), 0, 0 }, + { "mmSMU_INTERRUPT_CONTROL", REG_MMIO, 0x00ce, 2, &mmSMU_INTERRUPT_CONTROL[0], sizeof(mmSMU_INTERRUPT_CONTROL)/sizeof(mmSMU_INTERRUPT_CONTROL[0]), 0, 0 }, + { "mmDMCU_CTRL", REG_MMIO, 0x00da, 2, &mmDMCU_CTRL[0], sizeof(mmDMCU_CTRL)/sizeof(mmDMCU_CTRL[0]), 0, 0 }, + { "mmDMCU_STATUS", REG_MMIO, 0x00db, 2, &mmDMCU_STATUS[0], sizeof(mmDMCU_STATUS)/sizeof(mmDMCU_STATUS[0]), 0, 0 }, + { "mmDMCU_PC_START_ADDR", REG_MMIO, 0x00dc, 2, &mmDMCU_PC_START_ADDR[0], sizeof(mmDMCU_PC_START_ADDR)/sizeof(mmDMCU_PC_START_ADDR[0]), 0, 0 }, + { "mmDMCU_FW_START_ADDR", REG_MMIO, 0x00dd, 2, &mmDMCU_FW_START_ADDR[0], sizeof(mmDMCU_FW_START_ADDR)/sizeof(mmDMCU_FW_START_ADDR[0]), 0, 0 }, + { "mmDMCU_FW_END_ADDR", REG_MMIO, 0x00de, 2, &mmDMCU_FW_END_ADDR[0], sizeof(mmDMCU_FW_END_ADDR)/sizeof(mmDMCU_FW_END_ADDR[0]), 0, 0 }, + { "mmDMCU_FW_ISR_START_ADDR", REG_MMIO, 0x00df, 2, &mmDMCU_FW_ISR_START_ADDR[0], sizeof(mmDMCU_FW_ISR_START_ADDR)/sizeof(mmDMCU_FW_ISR_START_ADDR[0]), 0, 0 }, + { "mmDMCU_FW_CS_HI", REG_MMIO, 0x00e0, 2, &mmDMCU_FW_CS_HI[0], sizeof(mmDMCU_FW_CS_HI)/sizeof(mmDMCU_FW_CS_HI[0]), 0, 0 }, + { "mmDMCU_FW_CS_LO", REG_MMIO, 0x00e1, 2, &mmDMCU_FW_CS_LO[0], sizeof(mmDMCU_FW_CS_LO)/sizeof(mmDMCU_FW_CS_LO[0]), 0, 0 }, + { "mmDMCU_RAM_ACCESS_CTRL", REG_MMIO, 0x00e2, 2, &mmDMCU_RAM_ACCESS_CTRL[0], sizeof(mmDMCU_RAM_ACCESS_CTRL)/sizeof(mmDMCU_RAM_ACCESS_CTRL[0]), 0, 0 }, + { "mmDMCU_ERAM_WR_CTRL", REG_MMIO, 0x00e3, 2, &mmDMCU_ERAM_WR_CTRL[0], sizeof(mmDMCU_ERAM_WR_CTRL)/sizeof(mmDMCU_ERAM_WR_CTRL[0]), 0, 0 }, + { "mmDMCU_ERAM_WR_DATA", REG_MMIO, 0x00e4, 2, &mmDMCU_ERAM_WR_DATA[0], sizeof(mmDMCU_ERAM_WR_DATA)/sizeof(mmDMCU_ERAM_WR_DATA[0]), 0, 0 }, + { "mmDMCU_ERAM_RD_CTRL", REG_MMIO, 0x00e5, 2, &mmDMCU_ERAM_RD_CTRL[0], sizeof(mmDMCU_ERAM_RD_CTRL)/sizeof(mmDMCU_ERAM_RD_CTRL[0]), 0, 0 }, + { "mmDMCU_ERAM_RD_DATA", REG_MMIO, 0x00e6, 2, &mmDMCU_ERAM_RD_DATA[0], sizeof(mmDMCU_ERAM_RD_DATA)/sizeof(mmDMCU_ERAM_RD_DATA[0]), 0, 0 }, + { "mmDMCU_IRAM_WR_CTRL", REG_MMIO, 0x00e7, 2, &mmDMCU_IRAM_WR_CTRL[0], sizeof(mmDMCU_IRAM_WR_CTRL)/sizeof(mmDMCU_IRAM_WR_CTRL[0]), 0, 0 }, + { "mmDMCU_IRAM_WR_DATA", REG_MMIO, 0x00e8, 2, &mmDMCU_IRAM_WR_DATA[0], sizeof(mmDMCU_IRAM_WR_DATA)/sizeof(mmDMCU_IRAM_WR_DATA[0]), 0, 0 }, + { "mmDMCU_IRAM_RD_CTRL", REG_MMIO, 0x00e9, 2, &mmDMCU_IRAM_RD_CTRL[0], sizeof(mmDMCU_IRAM_RD_CTRL)/sizeof(mmDMCU_IRAM_RD_CTRL[0]), 0, 0 }, + { "mmDMCU_IRAM_RD_DATA", REG_MMIO, 0x00ea, 2, &mmDMCU_IRAM_RD_DATA[0], sizeof(mmDMCU_IRAM_RD_DATA)/sizeof(mmDMCU_IRAM_RD_DATA[0]), 0, 0 }, + { "mmDMCU_EVENT_TRIGGER", REG_MMIO, 0x00eb, 2, &mmDMCU_EVENT_TRIGGER[0], sizeof(mmDMCU_EVENT_TRIGGER)/sizeof(mmDMCU_EVENT_TRIGGER[0]), 0, 0 }, + { "mmDMCU_UC_INTERNAL_INT_STATUS", REG_MMIO, 0x00ec, 2, &mmDMCU_UC_INTERNAL_INT_STATUS[0], sizeof(mmDMCU_UC_INTERNAL_INT_STATUS)/sizeof(mmDMCU_UC_INTERNAL_INT_STATUS[0]), 0, 0 }, + { "mmDMCU_SS_INTERRUPT_CNTL_STATUS", REG_MMIO, 0x00ed, 2, &mmDMCU_SS_INTERRUPT_CNTL_STATUS[0], sizeof(mmDMCU_SS_INTERRUPT_CNTL_STATUS)/sizeof(mmDMCU_SS_INTERRUPT_CNTL_STATUS[0]), 0, 0 }, + { "mmDMCU_INTERRUPT_STATUS", REG_MMIO, 0x00ee, 2, &mmDMCU_INTERRUPT_STATUS[0], sizeof(mmDMCU_INTERRUPT_STATUS)/sizeof(mmDMCU_INTERRUPT_STATUS[0]), 0, 0 }, + { "mmDMCU_INTERRUPT_STATUS_1", REG_MMIO, 0x00ef, 2, &mmDMCU_INTERRUPT_STATUS_1[0], sizeof(mmDMCU_INTERRUPT_STATUS_1)/sizeof(mmDMCU_INTERRUPT_STATUS_1[0]), 0, 0 }, + { "mmDMCU_INTERRUPT_TO_HOST_EN_MASK", REG_MMIO, 0x00f0, 2, &mmDMCU_INTERRUPT_TO_HOST_EN_MASK[0], sizeof(mmDMCU_INTERRUPT_TO_HOST_EN_MASK)/sizeof(mmDMCU_INTERRUPT_TO_HOST_EN_MASK[0]), 0, 0 }, + { "mmDMCU_INTERRUPT_TO_UC_EN_MASK", REG_MMIO, 0x00f1, 2, &mmDMCU_INTERRUPT_TO_UC_EN_MASK[0], sizeof(mmDMCU_INTERRUPT_TO_UC_EN_MASK)/sizeof(mmDMCU_INTERRUPT_TO_UC_EN_MASK[0]), 0, 0 }, + { "mmDMCU_INTERRUPT_TO_UC_EN_MASK_1", REG_MMIO, 0x00f2, 2, &mmDMCU_INTERRUPT_TO_UC_EN_MASK_1[0], sizeof(mmDMCU_INTERRUPT_TO_UC_EN_MASK_1)/sizeof(mmDMCU_INTERRUPT_TO_UC_EN_MASK_1[0]), 0, 0 }, + { "mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL", REG_MMIO, 0x00f3, 2, &mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL[0], sizeof(mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL)/sizeof(mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL[0]), 0, 0 }, + { "mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1", REG_MMIO, 0x00f4, 2, &mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1[0], sizeof(mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1)/sizeof(mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1[0]), 0, 0 }, + { "mmDC_DMCU_SCRATCH", REG_MMIO, 0x00f5, 2, &mmDC_DMCU_SCRATCH[0], sizeof(mmDC_DMCU_SCRATCH)/sizeof(mmDC_DMCU_SCRATCH[0]), 0, 0 }, + { "mmDMCU_INT_CNT", REG_MMIO, 0x00f6, 2, &mmDMCU_INT_CNT[0], sizeof(mmDMCU_INT_CNT)/sizeof(mmDMCU_INT_CNT[0]), 0, 0 }, + { "mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS", REG_MMIO, 0x00f7, 2, &mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS[0], sizeof(mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS)/sizeof(mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS[0]), 0, 0 }, + { "mmDMCU_UC_CLK_GATING_CNTL", REG_MMIO, 0x00f8, 2, &mmDMCU_UC_CLK_GATING_CNTL[0], sizeof(mmDMCU_UC_CLK_GATING_CNTL)/sizeof(mmDMCU_UC_CLK_GATING_CNTL[0]), 0, 0 }, + { "mmMASTER_COMM_DATA_REG1", REG_MMIO, 0x00f9, 2, &mmMASTER_COMM_DATA_REG1[0], sizeof(mmMASTER_COMM_DATA_REG1)/sizeof(mmMASTER_COMM_DATA_REG1[0]), 0, 0 }, + { "mmMASTER_COMM_DATA_REG2", REG_MMIO, 0x00fa, 2, &mmMASTER_COMM_DATA_REG2[0], sizeof(mmMASTER_COMM_DATA_REG2)/sizeof(mmMASTER_COMM_DATA_REG2[0]), 0, 0 }, + { "mmMASTER_COMM_DATA_REG3", REG_MMIO, 0x00fb, 2, &mmMASTER_COMM_DATA_REG3[0], sizeof(mmMASTER_COMM_DATA_REG3)/sizeof(mmMASTER_COMM_DATA_REG3[0]), 0, 0 }, + { "mmMASTER_COMM_CMD_REG", REG_MMIO, 0x00fc, 2, &mmMASTER_COMM_CMD_REG[0], sizeof(mmMASTER_COMM_CMD_REG)/sizeof(mmMASTER_COMM_CMD_REG[0]), 0, 0 }, + { "mmMASTER_COMM_CNTL_REG", REG_MMIO, 0x00fd, 2, &mmMASTER_COMM_CNTL_REG[0], sizeof(mmMASTER_COMM_CNTL_REG)/sizeof(mmMASTER_COMM_CNTL_REG[0]), 0, 0 }, + { "mmSLAVE_COMM_DATA_REG1", REG_MMIO, 0x00fe, 2, &mmSLAVE_COMM_DATA_REG1[0], sizeof(mmSLAVE_COMM_DATA_REG1)/sizeof(mmSLAVE_COMM_DATA_REG1[0]), 0, 0 }, + { "mmSLAVE_COMM_DATA_REG2", REG_MMIO, 0x00ff, 2, &mmSLAVE_COMM_DATA_REG2[0], sizeof(mmSLAVE_COMM_DATA_REG2)/sizeof(mmSLAVE_COMM_DATA_REG2[0]), 0, 0 }, + { "mmSLAVE_COMM_DATA_REG3", REG_MMIO, 0x0100, 2, &mmSLAVE_COMM_DATA_REG3[0], sizeof(mmSLAVE_COMM_DATA_REG3)/sizeof(mmSLAVE_COMM_DATA_REG3[0]), 0, 0 }, + { "mmSLAVE_COMM_CMD_REG", REG_MMIO, 0x0101, 2, &mmSLAVE_COMM_CMD_REG[0], sizeof(mmSLAVE_COMM_CMD_REG)/sizeof(mmSLAVE_COMM_CMD_REG[0]), 0, 0 }, + { "mmSLAVE_COMM_CNTL_REG", REG_MMIO, 0x0102, 2, &mmSLAVE_COMM_CNTL_REG[0], sizeof(mmSLAVE_COMM_CNTL_REG)/sizeof(mmSLAVE_COMM_CNTL_REG[0]), 0, 0 }, + { "mmDMCU_PERFMON_INTERRUPT_STATUS1", REG_MMIO, 0x0105, 2, &mmDMCU_PERFMON_INTERRUPT_STATUS1[0], sizeof(mmDMCU_PERFMON_INTERRUPT_STATUS1)/sizeof(mmDMCU_PERFMON_INTERRUPT_STATUS1[0]), 0, 0 }, + { "mmDMCU_PERFMON_INTERRUPT_STATUS2", REG_MMIO, 0x0106, 2, &mmDMCU_PERFMON_INTERRUPT_STATUS2[0], sizeof(mmDMCU_PERFMON_INTERRUPT_STATUS2)/sizeof(mmDMCU_PERFMON_INTERRUPT_STATUS2[0]), 0, 0 }, + { "mmDMCU_PERFMON_INTERRUPT_STATUS3", REG_MMIO, 0x0107, 2, &mmDMCU_PERFMON_INTERRUPT_STATUS3[0], sizeof(mmDMCU_PERFMON_INTERRUPT_STATUS3)/sizeof(mmDMCU_PERFMON_INTERRUPT_STATUS3[0]), 0, 0 }, + { "mmDMCU_PERFMON_INTERRUPT_STATUS4", REG_MMIO, 0x0108, 2, &mmDMCU_PERFMON_INTERRUPT_STATUS4[0], sizeof(mmDMCU_PERFMON_INTERRUPT_STATUS4)/sizeof(mmDMCU_PERFMON_INTERRUPT_STATUS4[0]), 0, 0 }, + { "mmDMCU_PERFMON_INTERRUPT_STATUS5", REG_MMIO, 0x0109, 2, &mmDMCU_PERFMON_INTERRUPT_STATUS5[0], sizeof(mmDMCU_PERFMON_INTERRUPT_STATUS5)/sizeof(mmDMCU_PERFMON_INTERRUPT_STATUS5[0]), 0, 0 }, + { "mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1", REG_MMIO, 0x010a, 2, &mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1[0], sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1)/sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1[0]), 0, 0 }, + { "mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2", REG_MMIO, 0x010b, 2, &mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2[0], sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2)/sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2[0]), 0, 0 }, + { "mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3", REG_MMIO, 0x010c, 2, &mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3[0], sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3)/sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3[0]), 0, 0 }, + { "mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4", REG_MMIO, 0x010d, 2, &mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4[0], sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4)/sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4[0]), 0, 0 }, + { "mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5", REG_MMIO, 0x010e, 2, &mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5[0], sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5)/sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5[0]), 0, 0 }, + { "mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1", REG_MMIO, 0x010f, 2, &mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1[0], sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1)/sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1[0]), 0, 0 }, + { "mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2", REG_MMIO, 0x0110, 2, &mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2[0], sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2)/sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2[0]), 0, 0 }, + { "mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3", REG_MMIO, 0x0111, 2, &mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3[0], sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3)/sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3[0]), 0, 0 }, + { "mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4", REG_MMIO, 0x0112, 2, &mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4[0], sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4)/sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4[0]), 0, 0 }, + { "mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5", REG_MMIO, 0x0113, 2, &mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5[0], sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5)/sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5[0]), 0, 0 }, + { "mmDMCU_DPRX_INTERRUPT_STATUS1", REG_MMIO, 0x0114, 2, &mmDMCU_DPRX_INTERRUPT_STATUS1[0], sizeof(mmDMCU_DPRX_INTERRUPT_STATUS1)/sizeof(mmDMCU_DPRX_INTERRUPT_STATUS1[0]), 0, 0 }, + { "mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1", REG_MMIO, 0x0115, 2, &mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1[0], sizeof(mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1)/sizeof(mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1[0]), 0, 0 }, + { "mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1", REG_MMIO, 0x0116, 2, &mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1[0], sizeof(mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1)/sizeof(mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1[0]), 0, 0 }, + { "mmDMCU_INTERRUPT_STATUS_CONTINUE", REG_MMIO, 0x0119, 2, &mmDMCU_INTERRUPT_STATUS_CONTINUE[0], sizeof(mmDMCU_INTERRUPT_STATUS_CONTINUE)/sizeof(mmDMCU_INTERRUPT_STATUS_CONTINUE[0]), 0, 0 }, + { "mmDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE", REG_MMIO, 0x011a, 2, &mmDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE[0], sizeof(mmDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE)/sizeof(mmDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE[0]), 0, 0 }, + { "mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE", REG_MMIO, 0x011b, 2, &mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE[0], sizeof(mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE)/sizeof(mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE[0]), 0, 0 }, + { "mmDMCU_INT_CNT_CONTINUE", REG_MMIO, 0x011c, 2, &mmDMCU_INT_CNT_CONTINUE[0], sizeof(mmDMCU_INT_CNT_CONTINUE)/sizeof(mmDMCU_INT_CNT_CONTINUE[0]), 0, 0 }, + { "mmDC_GPU_TIMER_START_POSITION_V_UPDATE", REG_MMIO, 0x0126, 2, &mmDC_GPU_TIMER_START_POSITION_V_UPDATE[0], sizeof(mmDC_GPU_TIMER_START_POSITION_V_UPDATE)/sizeof(mmDC_GPU_TIMER_START_POSITION_V_UPDATE[0]), 0, 0 }, + { "mmDC_GPU_TIMER_START_POSITION_VSTARTUP", REG_MMIO, 0x0127, 2, &mmDC_GPU_TIMER_START_POSITION_VSTARTUP[0], sizeof(mmDC_GPU_TIMER_START_POSITION_VSTARTUP)/sizeof(mmDC_GPU_TIMER_START_POSITION_VSTARTUP[0]), 0, 0 }, + { "mmDC_GPU_TIMER_READ", REG_MMIO, 0x0128, 2, &mmDC_GPU_TIMER_READ[0], sizeof(mmDC_GPU_TIMER_READ)/sizeof(mmDC_GPU_TIMER_READ[0]), 0, 0 }, + { "mmDC_GPU_TIMER_READ_CNTL", REG_MMIO, 0x0129, 2, &mmDC_GPU_TIMER_READ_CNTL[0], sizeof(mmDC_GPU_TIMER_READ_CNTL)/sizeof(mmDC_GPU_TIMER_READ_CNTL[0]), 0, 0 }, + { "mmDISP_INTERRUPT_STATUS", REG_MMIO, 0x012a, 2, &mmDISP_INTERRUPT_STATUS[0], sizeof(mmDISP_INTERRUPT_STATUS)/sizeof(mmDISP_INTERRUPT_STATUS[0]), 0, 0 }, + { "mmDISP_INTERRUPT_STATUS_CONTINUE", REG_MMIO, 0x012b, 2, &mmDISP_INTERRUPT_STATUS_CONTINUE[0], sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE)/sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE[0]), 0, 0 }, + { "mmDISP_INTERRUPT_STATUS_CONTINUE2", REG_MMIO, 0x012c, 2, &mmDISP_INTERRUPT_STATUS_CONTINUE2[0], sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE2)/sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE2[0]), 0, 0 }, + { "mmDISP_INTERRUPT_STATUS_CONTINUE3", REG_MMIO, 0x012d, 2, &mmDISP_INTERRUPT_STATUS_CONTINUE3[0], sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE3)/sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE3[0]), 0, 0 }, + { "mmDISP_INTERRUPT_STATUS_CONTINUE4", REG_MMIO, 0x012e, 2, &mmDISP_INTERRUPT_STATUS_CONTINUE4[0], sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE4)/sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE4[0]), 0, 0 }, + { "mmDISP_INTERRUPT_STATUS_CONTINUE5", REG_MMIO, 0x012f, 2, &mmDISP_INTERRUPT_STATUS_CONTINUE5[0], sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE5)/sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE5[0]), 0, 0 }, + { "mmDISP_INTERRUPT_STATUS_CONTINUE6", REG_MMIO, 0x0130, 2, &mmDISP_INTERRUPT_STATUS_CONTINUE6[0], sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE6)/sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE6[0]), 0, 0 }, + { "mmDISP_INTERRUPT_STATUS_CONTINUE7", REG_MMIO, 0x0131, 2, &mmDISP_INTERRUPT_STATUS_CONTINUE7[0], sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE7)/sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE7[0]), 0, 0 }, + { "mmDISP_INTERRUPT_STATUS_CONTINUE8", REG_MMIO, 0x0132, 2, &mmDISP_INTERRUPT_STATUS_CONTINUE8[0], sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE8)/sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE8[0]), 0, 0 }, + { "mmDISP_INTERRUPT_STATUS_CONTINUE9", REG_MMIO, 0x0133, 2, &mmDISP_INTERRUPT_STATUS_CONTINUE9[0], sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE9)/sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE9[0]), 0, 0 }, + { "mmDISP_INTERRUPT_STATUS_CONTINUE10", REG_MMIO, 0x0134, 2, &mmDISP_INTERRUPT_STATUS_CONTINUE10[0], sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE10)/sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE10[0]), 0, 0 }, + { "mmDISP_INTERRUPT_STATUS_CONTINUE11", REG_MMIO, 0x0135, 2, &mmDISP_INTERRUPT_STATUS_CONTINUE11[0], sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE11)/sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE11[0]), 0, 0 }, + { "mmDISP_INTERRUPT_STATUS_CONTINUE12", REG_MMIO, 0x0136, 2, &mmDISP_INTERRUPT_STATUS_CONTINUE12[0], sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE12)/sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE12[0]), 0, 0 }, + { "mmDISP_INTERRUPT_STATUS_CONTINUE13", REG_MMIO, 0x0137, 2, &mmDISP_INTERRUPT_STATUS_CONTINUE13[0], sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE13)/sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE13[0]), 0, 0 }, + { "mmDISP_INTERRUPT_STATUS_CONTINUE14", REG_MMIO, 0x0138, 2, &mmDISP_INTERRUPT_STATUS_CONTINUE14[0], sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE14)/sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE14[0]), 0, 0 }, + { "mmDISP_INTERRUPT_STATUS_CONTINUE15", REG_MMIO, 0x0139, 2, &mmDISP_INTERRUPT_STATUS_CONTINUE15[0], sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE15)/sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE15[0]), 0, 0 }, + { "mmDISP_INTERRUPT_STATUS_CONTINUE16", REG_MMIO, 0x013a, 2, &mmDISP_INTERRUPT_STATUS_CONTINUE16[0], sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE16)/sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE16[0]), 0, 0 }, + { "mmDISP_INTERRUPT_STATUS_CONTINUE17", REG_MMIO, 0x013b, 2, &mmDISP_INTERRUPT_STATUS_CONTINUE17[0], sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE17)/sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE17[0]), 0, 0 }, + { "mmDISP_INTERRUPT_STATUS_CONTINUE18", REG_MMIO, 0x013c, 2, &mmDISP_INTERRUPT_STATUS_CONTINUE18[0], sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE18)/sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE18[0]), 0, 0 }, + { "mmDISP_INTERRUPT_STATUS_CONTINUE19", REG_MMIO, 0x013d, 2, &mmDISP_INTERRUPT_STATUS_CONTINUE19[0], sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE19)/sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE19[0]), 0, 0 }, + { "mmDISP_INTERRUPT_STATUS_CONTINUE20", REG_MMIO, 0x013e, 2, &mmDISP_INTERRUPT_STATUS_CONTINUE20[0], sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE20)/sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE20[0]), 0, 0 }, + { "mmDISP_INTERRUPT_STATUS_CONTINUE21", REG_MMIO, 0x013f, 2, &mmDISP_INTERRUPT_STATUS_CONTINUE21[0], sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE21)/sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE21[0]), 0, 0 }, + { "mmDISP_INTERRUPT_STATUS_CONTINUE22", REG_MMIO, 0x0140, 2, &mmDISP_INTERRUPT_STATUS_CONTINUE22[0], sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE22)/sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE22[0]), 0, 0 }, + { "mmDC_GPU_TIMER_START_POSITION_VREADY", REG_MMIO, 0x0141, 2, &mmDC_GPU_TIMER_START_POSITION_VREADY[0], sizeof(mmDC_GPU_TIMER_START_POSITION_VREADY)/sizeof(mmDC_GPU_TIMER_START_POSITION_VREADY[0]), 0, 0 }, + { "mmDC_GPU_TIMER_START_POSITION_FLIP", REG_MMIO, 0x0142, 2, &mmDC_GPU_TIMER_START_POSITION_FLIP[0], sizeof(mmDC_GPU_TIMER_START_POSITION_FLIP)/sizeof(mmDC_GPU_TIMER_START_POSITION_FLIP[0]), 0, 0 }, + { "mmDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK", REG_MMIO, 0x0143, 2, &mmDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK[0], sizeof(mmDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK)/sizeof(mmDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK[0]), 0, 0 }, + { "mmDC_GPU_TIMER_START_POSITION_FLIP_AWAY", REG_MMIO, 0x0144, 2, &mmDC_GPU_TIMER_START_POSITION_FLIP_AWAY[0], sizeof(mmDC_GPU_TIMER_START_POSITION_FLIP_AWAY)/sizeof(mmDC_GPU_TIMER_START_POSITION_FLIP_AWAY[0]), 0, 0 }, + { "mmCNV0_WB_ENABLE", REG_MMIO, 0x01da, 2, &mmCNV0_WB_ENABLE[0], sizeof(mmCNV0_WB_ENABLE)/sizeof(mmCNV0_WB_ENABLE[0]), 0, 0 }, + { "mmCNV0_WB_EC_CONFIG", REG_MMIO, 0x01db, 2, &mmCNV0_WB_EC_CONFIG[0], sizeof(mmCNV0_WB_EC_CONFIG)/sizeof(mmCNV0_WB_EC_CONFIG[0]), 0, 0 }, + { "mmCNV0_CNV_MODE", REG_MMIO, 0x01dc, 2, &mmCNV0_CNV_MODE[0], sizeof(mmCNV0_CNV_MODE)/sizeof(mmCNV0_CNV_MODE[0]), 0, 0 }, + { "mmCNV0_CNV_WINDOW_START", REG_MMIO, 0x01dd, 2, &mmCNV0_CNV_WINDOW_START[0], sizeof(mmCNV0_CNV_WINDOW_START)/sizeof(mmCNV0_CNV_WINDOW_START[0]), 0, 0 }, + { "mmCNV0_CNV_WINDOW_SIZE", REG_MMIO, 0x01de, 2, &mmCNV0_CNV_WINDOW_SIZE[0], sizeof(mmCNV0_CNV_WINDOW_SIZE)/sizeof(mmCNV0_CNV_WINDOW_SIZE[0]), 0, 0 }, + { "mmCNV0_CNV_UPDATE", REG_MMIO, 0x01df, 2, &mmCNV0_CNV_UPDATE[0], sizeof(mmCNV0_CNV_UPDATE)/sizeof(mmCNV0_CNV_UPDATE[0]), 0, 0 }, + { "mmCNV0_CNV_SOURCE_SIZE", REG_MMIO, 0x01e0, 2, &mmCNV0_CNV_SOURCE_SIZE[0], sizeof(mmCNV0_CNV_SOURCE_SIZE)/sizeof(mmCNV0_CNV_SOURCE_SIZE[0]), 0, 0 }, + { "mmCNV0_CNV_CSC_CONTROL", REG_MMIO, 0x01e1, 2, &mmCNV0_CNV_CSC_CONTROL[0], sizeof(mmCNV0_CNV_CSC_CONTROL)/sizeof(mmCNV0_CNV_CSC_CONTROL[0]), 0, 0 }, + { "mmCNV0_CNV_CSC_C11_C12", REG_MMIO, 0x01e2, 2, &mmCNV0_CNV_CSC_C11_C12[0], sizeof(mmCNV0_CNV_CSC_C11_C12)/sizeof(mmCNV0_CNV_CSC_C11_C12[0]), 0, 0 }, + { "mmCNV0_CNV_CSC_C13_C14", REG_MMIO, 0x01e3, 2, &mmCNV0_CNV_CSC_C13_C14[0], sizeof(mmCNV0_CNV_CSC_C13_C14)/sizeof(mmCNV0_CNV_CSC_C13_C14[0]), 0, 0 }, + { "mmCNV0_CNV_CSC_C21_C22", REG_MMIO, 0x01e4, 2, &mmCNV0_CNV_CSC_C21_C22[0], sizeof(mmCNV0_CNV_CSC_C21_C22)/sizeof(mmCNV0_CNV_CSC_C21_C22[0]), 0, 0 }, + { "mmCNV0_CNV_CSC_C23_C24", REG_MMIO, 0x01e5, 2, &mmCNV0_CNV_CSC_C23_C24[0], sizeof(mmCNV0_CNV_CSC_C23_C24)/sizeof(mmCNV0_CNV_CSC_C23_C24[0]), 0, 0 }, + { "mmCNV0_CNV_CSC_C31_C32", REG_MMIO, 0x01e6, 2, &mmCNV0_CNV_CSC_C31_C32[0], sizeof(mmCNV0_CNV_CSC_C31_C32)/sizeof(mmCNV0_CNV_CSC_C31_C32[0]), 0, 0 }, + { "mmCNV0_CNV_CSC_C33_C34", REG_MMIO, 0x01e7, 2, &mmCNV0_CNV_CSC_C33_C34[0], sizeof(mmCNV0_CNV_CSC_C33_C34)/sizeof(mmCNV0_CNV_CSC_C33_C34[0]), 0, 0 }, + { "mmCNV0_CNV_CSC_ROUND_OFFSET_R", REG_MMIO, 0x01e8, 2, &mmCNV0_CNV_CSC_ROUND_OFFSET_R[0], sizeof(mmCNV0_CNV_CSC_ROUND_OFFSET_R)/sizeof(mmCNV0_CNV_CSC_ROUND_OFFSET_R[0]), 0, 0 }, + { "mmCNV0_CNV_CSC_ROUND_OFFSET_G", REG_MMIO, 0x01e9, 2, &mmCNV0_CNV_CSC_ROUND_OFFSET_G[0], sizeof(mmCNV0_CNV_CSC_ROUND_OFFSET_G)/sizeof(mmCNV0_CNV_CSC_ROUND_OFFSET_G[0]), 0, 0 }, + { "mmCNV0_CNV_CSC_ROUND_OFFSET_B", REG_MMIO, 0x01ea, 2, &mmCNV0_CNV_CSC_ROUND_OFFSET_B[0], sizeof(mmCNV0_CNV_CSC_ROUND_OFFSET_B)/sizeof(mmCNV0_CNV_CSC_ROUND_OFFSET_B[0]), 0, 0 }, + { "mmCNV0_CNV_CSC_CLAMP_R", REG_MMIO, 0x01eb, 2, &mmCNV0_CNV_CSC_CLAMP_R[0], sizeof(mmCNV0_CNV_CSC_CLAMP_R)/sizeof(mmCNV0_CNV_CSC_CLAMP_R[0]), 0, 0 }, + { "mmCNV0_CNV_CSC_CLAMP_G", REG_MMIO, 0x01ec, 2, &mmCNV0_CNV_CSC_CLAMP_G[0], sizeof(mmCNV0_CNV_CSC_CLAMP_G)/sizeof(mmCNV0_CNV_CSC_CLAMP_G[0]), 0, 0 }, + { "mmCNV0_CNV_CSC_CLAMP_B", REG_MMIO, 0x01ed, 2, &mmCNV0_CNV_CSC_CLAMP_B[0], sizeof(mmCNV0_CNV_CSC_CLAMP_B)/sizeof(mmCNV0_CNV_CSC_CLAMP_B[0]), 0, 0 }, + { "mmCNV0_CNV_TEST_CNTL", REG_MMIO, 0x01ee, 2, &mmCNV0_CNV_TEST_CNTL[0], sizeof(mmCNV0_CNV_TEST_CNTL)/sizeof(mmCNV0_CNV_TEST_CNTL[0]), 0, 0 }, + { "mmCNV0_CNV_TEST_CRC_RED", REG_MMIO, 0x01ef, 2, &mmCNV0_CNV_TEST_CRC_RED[0], sizeof(mmCNV0_CNV_TEST_CRC_RED)/sizeof(mmCNV0_CNV_TEST_CRC_RED[0]), 0, 0 }, + { "mmCNV0_CNV_TEST_CRC_GREEN", REG_MMIO, 0x01f0, 2, &mmCNV0_CNV_TEST_CRC_GREEN[0], sizeof(mmCNV0_CNV_TEST_CRC_GREEN)/sizeof(mmCNV0_CNV_TEST_CRC_GREEN[0]), 0, 0 }, + { "mmCNV0_CNV_TEST_CRC_BLUE", REG_MMIO, 0x01f1, 2, &mmCNV0_CNV_TEST_CRC_BLUE[0], sizeof(mmCNV0_CNV_TEST_CRC_BLUE)/sizeof(mmCNV0_CNV_TEST_CRC_BLUE[0]), 0, 0 }, + { "mmCNV0_CNV_INPUT_SELECT", REG_MMIO, 0x01f5, 2, &mmCNV0_CNV_INPUT_SELECT[0], sizeof(mmCNV0_CNV_INPUT_SELECT)/sizeof(mmCNV0_CNV_INPUT_SELECT[0]), 0, 0 }, + { "mmCNV0_WB_SOFT_RESET", REG_MMIO, 0x01f8, 2, &mmCNV0_WB_SOFT_RESET[0], sizeof(mmCNV0_WB_SOFT_RESET)/sizeof(mmCNV0_WB_SOFT_RESET[0]), 0, 0 }, + { "mmCNV0_WB_WARM_UP_MODE_CTL1", REG_MMIO, 0x01f9, 2, &mmCNV0_WB_WARM_UP_MODE_CTL1[0], sizeof(mmCNV0_WB_WARM_UP_MODE_CTL1)/sizeof(mmCNV0_WB_WARM_UP_MODE_CTL1[0]), 0, 0 }, + { "mmCNV0_WB_WARM_UP_MODE_CTL2", REG_MMIO, 0x01fa, 2, &mmCNV0_WB_WARM_UP_MODE_CTL2[0], sizeof(mmCNV0_WB_WARM_UP_MODE_CTL2)/sizeof(mmCNV0_WB_WARM_UP_MODE_CTL2[0]), 0, 0 }, + { "mmWBSCL0_WBSCL_COEF_RAM_SELECT", REG_MMIO, 0x020a, 2, &mmWBSCL0_WBSCL_COEF_RAM_SELECT[0], sizeof(mmWBSCL0_WBSCL_COEF_RAM_SELECT)/sizeof(mmWBSCL0_WBSCL_COEF_RAM_SELECT[0]), 0, 0 }, + { "mmWBSCL0_WBSCL_COEF_RAM_TAP_DATA", REG_MMIO, 0x020b, 2, &mmWBSCL0_WBSCL_COEF_RAM_TAP_DATA[0], sizeof(mmWBSCL0_WBSCL_COEF_RAM_TAP_DATA)/sizeof(mmWBSCL0_WBSCL_COEF_RAM_TAP_DATA[0]), 0, 0 }, + { "mmWBSCL0_WBSCL_MODE", REG_MMIO, 0x020c, 2, &mmWBSCL0_WBSCL_MODE[0], sizeof(mmWBSCL0_WBSCL_MODE)/sizeof(mmWBSCL0_WBSCL_MODE[0]), 0, 0 }, + { "mmWBSCL0_WBSCL_TAP_CONTROL", REG_MMIO, 0x020d, 2, &mmWBSCL0_WBSCL_TAP_CONTROL[0], sizeof(mmWBSCL0_WBSCL_TAP_CONTROL)/sizeof(mmWBSCL0_WBSCL_TAP_CONTROL[0]), 0, 0 }, + { "mmWBSCL0_WBSCL_DEST_SIZE", REG_MMIO, 0x020e, 2, &mmWBSCL0_WBSCL_DEST_SIZE[0], sizeof(mmWBSCL0_WBSCL_DEST_SIZE)/sizeof(mmWBSCL0_WBSCL_DEST_SIZE[0]), 0, 0 }, + { "mmWBSCL0_WBSCL_HORZ_FILTER_SCALE_RATIO", REG_MMIO, 0x020f, 2, &mmWBSCL0_WBSCL_HORZ_FILTER_SCALE_RATIO[0], sizeof(mmWBSCL0_WBSCL_HORZ_FILTER_SCALE_RATIO)/sizeof(mmWBSCL0_WBSCL_HORZ_FILTER_SCALE_RATIO[0]), 0, 0 }, + { "mmWBSCL0_WBSCL_HORZ_FILTER_INIT_Y_RGB", REG_MMIO, 0x0210, 2, &mmWBSCL0_WBSCL_HORZ_FILTER_INIT_Y_RGB[0], sizeof(mmWBSCL0_WBSCL_HORZ_FILTER_INIT_Y_RGB)/sizeof(mmWBSCL0_WBSCL_HORZ_FILTER_INIT_Y_RGB[0]), 0, 0 }, + { "mmWBSCL0_WBSCL_HORZ_FILTER_INIT_CBCR", REG_MMIO, 0x0211, 2, &mmWBSCL0_WBSCL_HORZ_FILTER_INIT_CBCR[0], sizeof(mmWBSCL0_WBSCL_HORZ_FILTER_INIT_CBCR)/sizeof(mmWBSCL0_WBSCL_HORZ_FILTER_INIT_CBCR[0]), 0, 0 }, + { "mmWBSCL0_WBSCL_VERT_FILTER_SCALE_RATIO", REG_MMIO, 0x0212, 2, &mmWBSCL0_WBSCL_VERT_FILTER_SCALE_RATIO[0], sizeof(mmWBSCL0_WBSCL_VERT_FILTER_SCALE_RATIO)/sizeof(mmWBSCL0_WBSCL_VERT_FILTER_SCALE_RATIO[0]), 0, 0 }, + { "mmWBSCL0_WBSCL_VERT_FILTER_INIT_Y_RGB", REG_MMIO, 0x0213, 2, &mmWBSCL0_WBSCL_VERT_FILTER_INIT_Y_RGB[0], sizeof(mmWBSCL0_WBSCL_VERT_FILTER_INIT_Y_RGB)/sizeof(mmWBSCL0_WBSCL_VERT_FILTER_INIT_Y_RGB[0]), 0, 0 }, + { "mmWBSCL0_WBSCL_VERT_FILTER_INIT_CBCR", REG_MMIO, 0x0214, 2, &mmWBSCL0_WBSCL_VERT_FILTER_INIT_CBCR[0], sizeof(mmWBSCL0_WBSCL_VERT_FILTER_INIT_CBCR)/sizeof(mmWBSCL0_WBSCL_VERT_FILTER_INIT_CBCR[0]), 0, 0 }, + { "mmWBSCL0_WBSCL_ROUND_OFFSET", REG_MMIO, 0x0215, 2, &mmWBSCL0_WBSCL_ROUND_OFFSET[0], sizeof(mmWBSCL0_WBSCL_ROUND_OFFSET)/sizeof(mmWBSCL0_WBSCL_ROUND_OFFSET[0]), 0, 0 }, + { "mmWBSCL0_WBSCL_CLAMP", REG_MMIO, 0x0216, 2, &mmWBSCL0_WBSCL_CLAMP[0], sizeof(mmWBSCL0_WBSCL_CLAMP)/sizeof(mmWBSCL0_WBSCL_CLAMP[0]), 0, 0 }, + { "mmWBSCL0_WBSCL_OVERFLOW_STATUS", REG_MMIO, 0x0217, 2, &mmWBSCL0_WBSCL_OVERFLOW_STATUS[0], sizeof(mmWBSCL0_WBSCL_OVERFLOW_STATUS)/sizeof(mmWBSCL0_WBSCL_OVERFLOW_STATUS[0]), 0, 0 }, + { "mmWBSCL0_WBSCL_COEF_RAM_CONFLICT_STATUS", REG_MMIO, 0x0218, 2, &mmWBSCL0_WBSCL_COEF_RAM_CONFLICT_STATUS[0], sizeof(mmWBSCL0_WBSCL_COEF_RAM_CONFLICT_STATUS)/sizeof(mmWBSCL0_WBSCL_COEF_RAM_CONFLICT_STATUS[0]), 0, 0 }, + { "mmWBSCL0_WBSCL_OUTSIDE_PIX_STRATEGY", REG_MMIO, 0x0219, 2, &mmWBSCL0_WBSCL_OUTSIDE_PIX_STRATEGY[0], sizeof(mmWBSCL0_WBSCL_OUTSIDE_PIX_STRATEGY)/sizeof(mmWBSCL0_WBSCL_OUTSIDE_PIX_STRATEGY[0]), 0, 0 }, + { "mmWBSCL0_WBSCL_TEST_CNTL", REG_MMIO, 0x021a, 2, &mmWBSCL0_WBSCL_TEST_CNTL[0], sizeof(mmWBSCL0_WBSCL_TEST_CNTL)/sizeof(mmWBSCL0_WBSCL_TEST_CNTL[0]), 0, 0 }, + { "mmWBSCL0_WBSCL_TEST_CRC_RED", REG_MMIO, 0x021b, 2, &mmWBSCL0_WBSCL_TEST_CRC_RED[0], sizeof(mmWBSCL0_WBSCL_TEST_CRC_RED)/sizeof(mmWBSCL0_WBSCL_TEST_CRC_RED[0]), 0, 0 }, + { "mmWBSCL0_WBSCL_TEST_CRC_GREEN", REG_MMIO, 0x021c, 2, &mmWBSCL0_WBSCL_TEST_CRC_GREEN[0], sizeof(mmWBSCL0_WBSCL_TEST_CRC_GREEN)/sizeof(mmWBSCL0_WBSCL_TEST_CRC_GREEN[0]), 0, 0 }, + { "mmWBSCL0_WBSCL_TEST_CRC_BLUE", REG_MMIO, 0x021d, 2, &mmWBSCL0_WBSCL_TEST_CRC_BLUE[0], sizeof(mmWBSCL0_WBSCL_TEST_CRC_BLUE)/sizeof(mmWBSCL0_WBSCL_TEST_CRC_BLUE[0]), 0, 0 }, + { "mmWBSCL0_WBSCL_BACKPRESSURE_CNT_EN", REG_MMIO, 0x021e, 2, &mmWBSCL0_WBSCL_BACKPRESSURE_CNT_EN[0], sizeof(mmWBSCL0_WBSCL_BACKPRESSURE_CNT_EN)/sizeof(mmWBSCL0_WBSCL_BACKPRESSURE_CNT_EN[0]), 0, 0 }, + { "mmWBSCL0_WB_MCIF_BACKPRESSURE_CNT", REG_MMIO, 0x021f, 2, &mmWBSCL0_WB_MCIF_BACKPRESSURE_CNT[0], sizeof(mmWBSCL0_WB_MCIF_BACKPRESSURE_CNT)/sizeof(mmWBSCL0_WB_MCIF_BACKPRESSURE_CNT[0]), 0, 0 }, + { "mmWBSCL0_WBSCL_RAM_SHUTDOWN", REG_MMIO, 0x0222, 2, &mmWBSCL0_WBSCL_RAM_SHUTDOWN[0], sizeof(mmWBSCL0_WBSCL_RAM_SHUTDOWN)/sizeof(mmWBSCL0_WBSCL_RAM_SHUTDOWN[0]), 0, 0 }, + { "mmDC_PERFMON3_PERFCOUNTER_CNTL", REG_MMIO, 0x023a, 2, &mmDC_PERFMON3_PERFCOUNTER_CNTL[0], sizeof(mmDC_PERFMON3_PERFCOUNTER_CNTL)/sizeof(mmDC_PERFMON3_PERFCOUNTER_CNTL[0]), 0, 0 }, + { "mmDC_PERFMON3_PERFCOUNTER_CNTL2", REG_MMIO, 0x023b, 2, &mmDC_PERFMON3_PERFCOUNTER_CNTL2[0], sizeof(mmDC_PERFMON3_PERFCOUNTER_CNTL2)/sizeof(mmDC_PERFMON3_PERFCOUNTER_CNTL2[0]), 0, 0 }, + { "mmDC_PERFMON3_PERFCOUNTER_STATE", REG_MMIO, 0x023c, 2, &mmDC_PERFMON3_PERFCOUNTER_STATE[0], sizeof(mmDC_PERFMON3_PERFCOUNTER_STATE)/sizeof(mmDC_PERFMON3_PERFCOUNTER_STATE[0]), 0, 0 }, + { "mmDC_PERFMON3_PERFMON_CNTL", REG_MMIO, 0x023d, 2, &mmDC_PERFMON3_PERFMON_CNTL[0], sizeof(mmDC_PERFMON3_PERFMON_CNTL)/sizeof(mmDC_PERFMON3_PERFMON_CNTL[0]), 0, 0 }, + { "mmDC_PERFMON3_PERFMON_CNTL2", REG_MMIO, 0x023e, 2, &mmDC_PERFMON3_PERFMON_CNTL2[0], sizeof(mmDC_PERFMON3_PERFMON_CNTL2)/sizeof(mmDC_PERFMON3_PERFMON_CNTL2[0]), 0, 0 }, + { "mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC", REG_MMIO, 0x023f, 2, &mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC[0], sizeof(mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC)/sizeof(mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC[0]), 0, 0 }, + { "mmDC_PERFMON3_PERFMON_CVALUE_LOW", REG_MMIO, 0x0240, 2, &mmDC_PERFMON3_PERFMON_CVALUE_LOW[0], sizeof(mmDC_PERFMON3_PERFMON_CVALUE_LOW)/sizeof(mmDC_PERFMON3_PERFMON_CVALUE_LOW[0]), 0, 0 }, + { "mmDC_PERFMON3_PERFMON_HI", REG_MMIO, 0x0241, 2, &mmDC_PERFMON3_PERFMON_HI[0], sizeof(mmDC_PERFMON3_PERFMON_HI)/sizeof(mmDC_PERFMON3_PERFMON_HI[0]), 0, 0 }, + { "mmDC_PERFMON3_PERFMON_LOW", REG_MMIO, 0x0242, 2, &mmDC_PERFMON3_PERFMON_LOW[0], sizeof(mmDC_PERFMON3_PERFMON_LOW)/sizeof(mmDC_PERFMON3_PERFMON_LOW[0]), 0, 0 }, + { "mmCNV1_WB_ENABLE", REG_MMIO, 0x0246, 2, &mmCNV1_WB_ENABLE[0], sizeof(mmCNV1_WB_ENABLE)/sizeof(mmCNV1_WB_ENABLE[0]), 0, 0 }, + { "mmCNV1_WB_EC_CONFIG", REG_MMIO, 0x0247, 2, &mmCNV1_WB_EC_CONFIG[0], sizeof(mmCNV1_WB_EC_CONFIG)/sizeof(mmCNV1_WB_EC_CONFIG[0]), 0, 0 }, + { "mmCNV1_CNV_MODE", REG_MMIO, 0x0248, 2, &mmCNV1_CNV_MODE[0], sizeof(mmCNV1_CNV_MODE)/sizeof(mmCNV1_CNV_MODE[0]), 0, 0 }, + { "mmCNV1_CNV_WINDOW_START", REG_MMIO, 0x0249, 2, &mmCNV1_CNV_WINDOW_START[0], sizeof(mmCNV1_CNV_WINDOW_START)/sizeof(mmCNV1_CNV_WINDOW_START[0]), 0, 0 }, + { "mmCNV1_CNV_WINDOW_SIZE", REG_MMIO, 0x024a, 2, &mmCNV1_CNV_WINDOW_SIZE[0], sizeof(mmCNV1_CNV_WINDOW_SIZE)/sizeof(mmCNV1_CNV_WINDOW_SIZE[0]), 0, 0 }, + { "mmCNV1_CNV_UPDATE", REG_MMIO, 0x024b, 2, &mmCNV1_CNV_UPDATE[0], sizeof(mmCNV1_CNV_UPDATE)/sizeof(mmCNV1_CNV_UPDATE[0]), 0, 0 }, + { "mmCNV1_CNV_SOURCE_SIZE", REG_MMIO, 0x024c, 2, &mmCNV1_CNV_SOURCE_SIZE[0], sizeof(mmCNV1_CNV_SOURCE_SIZE)/sizeof(mmCNV1_CNV_SOURCE_SIZE[0]), 0, 0 }, + { "mmCNV1_CNV_CSC_CONTROL", REG_MMIO, 0x024d, 2, &mmCNV1_CNV_CSC_CONTROL[0], sizeof(mmCNV1_CNV_CSC_CONTROL)/sizeof(mmCNV1_CNV_CSC_CONTROL[0]), 0, 0 }, + { "mmCNV1_CNV_CSC_C11_C12", REG_MMIO, 0x024e, 2, &mmCNV1_CNV_CSC_C11_C12[0], sizeof(mmCNV1_CNV_CSC_C11_C12)/sizeof(mmCNV1_CNV_CSC_C11_C12[0]), 0, 0 }, + { "mmCNV1_CNV_CSC_C13_C14", REG_MMIO, 0x024f, 2, &mmCNV1_CNV_CSC_C13_C14[0], sizeof(mmCNV1_CNV_CSC_C13_C14)/sizeof(mmCNV1_CNV_CSC_C13_C14[0]), 0, 0 }, + { "mmCNV1_CNV_CSC_C21_C22", REG_MMIO, 0x0250, 2, &mmCNV1_CNV_CSC_C21_C22[0], sizeof(mmCNV1_CNV_CSC_C21_C22)/sizeof(mmCNV1_CNV_CSC_C21_C22[0]), 0, 0 }, + { "mmCNV1_CNV_CSC_C23_C24", REG_MMIO, 0x0251, 2, &mmCNV1_CNV_CSC_C23_C24[0], sizeof(mmCNV1_CNV_CSC_C23_C24)/sizeof(mmCNV1_CNV_CSC_C23_C24[0]), 0, 0 }, + { "mmCNV1_CNV_CSC_C31_C32", REG_MMIO, 0x0252, 2, &mmCNV1_CNV_CSC_C31_C32[0], sizeof(mmCNV1_CNV_CSC_C31_C32)/sizeof(mmCNV1_CNV_CSC_C31_C32[0]), 0, 0 }, + { "mmCNV1_CNV_CSC_C33_C34", REG_MMIO, 0x0253, 2, &mmCNV1_CNV_CSC_C33_C34[0], sizeof(mmCNV1_CNV_CSC_C33_C34)/sizeof(mmCNV1_CNV_CSC_C33_C34[0]), 0, 0 }, + { "mmCNV1_CNV_CSC_ROUND_OFFSET_R", REG_MMIO, 0x0254, 2, &mmCNV1_CNV_CSC_ROUND_OFFSET_R[0], sizeof(mmCNV1_CNV_CSC_ROUND_OFFSET_R)/sizeof(mmCNV1_CNV_CSC_ROUND_OFFSET_R[0]), 0, 0 }, + { "mmCNV1_CNV_CSC_ROUND_OFFSET_G", REG_MMIO, 0x0255, 2, &mmCNV1_CNV_CSC_ROUND_OFFSET_G[0], sizeof(mmCNV1_CNV_CSC_ROUND_OFFSET_G)/sizeof(mmCNV1_CNV_CSC_ROUND_OFFSET_G[0]), 0, 0 }, + { "mmCNV1_CNV_CSC_ROUND_OFFSET_B", REG_MMIO, 0x0256, 2, &mmCNV1_CNV_CSC_ROUND_OFFSET_B[0], sizeof(mmCNV1_CNV_CSC_ROUND_OFFSET_B)/sizeof(mmCNV1_CNV_CSC_ROUND_OFFSET_B[0]), 0, 0 }, + { "mmCNV1_CNV_CSC_CLAMP_R", REG_MMIO, 0x0257, 2, &mmCNV1_CNV_CSC_CLAMP_R[0], sizeof(mmCNV1_CNV_CSC_CLAMP_R)/sizeof(mmCNV1_CNV_CSC_CLAMP_R[0]), 0, 0 }, + { "mmCNV1_CNV_CSC_CLAMP_G", REG_MMIO, 0x0258, 2, &mmCNV1_CNV_CSC_CLAMP_G[0], sizeof(mmCNV1_CNV_CSC_CLAMP_G)/sizeof(mmCNV1_CNV_CSC_CLAMP_G[0]), 0, 0 }, + { "mmCNV1_CNV_CSC_CLAMP_B", REG_MMIO, 0x0259, 2, &mmCNV1_CNV_CSC_CLAMP_B[0], sizeof(mmCNV1_CNV_CSC_CLAMP_B)/sizeof(mmCNV1_CNV_CSC_CLAMP_B[0]), 0, 0 }, + { "mmCNV1_CNV_TEST_CNTL", REG_MMIO, 0x025a, 2, &mmCNV1_CNV_TEST_CNTL[0], sizeof(mmCNV1_CNV_TEST_CNTL)/sizeof(mmCNV1_CNV_TEST_CNTL[0]), 0, 0 }, + { "mmCNV1_CNV_TEST_CRC_RED", REG_MMIO, 0x025b, 2, &mmCNV1_CNV_TEST_CRC_RED[0], sizeof(mmCNV1_CNV_TEST_CRC_RED)/sizeof(mmCNV1_CNV_TEST_CRC_RED[0]), 0, 0 }, + { "mmCNV1_CNV_TEST_CRC_GREEN", REG_MMIO, 0x025c, 2, &mmCNV1_CNV_TEST_CRC_GREEN[0], sizeof(mmCNV1_CNV_TEST_CRC_GREEN)/sizeof(mmCNV1_CNV_TEST_CRC_GREEN[0]), 0, 0 }, + { "mmCNV1_CNV_TEST_CRC_BLUE", REG_MMIO, 0x025d, 2, &mmCNV1_CNV_TEST_CRC_BLUE[0], sizeof(mmCNV1_CNV_TEST_CRC_BLUE)/sizeof(mmCNV1_CNV_TEST_CRC_BLUE[0]), 0, 0 }, + { "mmCNV1_CNV_INPUT_SELECT", REG_MMIO, 0x0261, 2, &mmCNV1_CNV_INPUT_SELECT[0], sizeof(mmCNV1_CNV_INPUT_SELECT)/sizeof(mmCNV1_CNV_INPUT_SELECT[0]), 0, 0 }, + { "mmCNV1_WB_SOFT_RESET", REG_MMIO, 0x0264, 2, &mmCNV1_WB_SOFT_RESET[0], sizeof(mmCNV1_WB_SOFT_RESET)/sizeof(mmCNV1_WB_SOFT_RESET[0]), 0, 0 }, + { "mmCNV1_WB_WARM_UP_MODE_CTL1", REG_MMIO, 0x0265, 2, &mmCNV1_WB_WARM_UP_MODE_CTL1[0], sizeof(mmCNV1_WB_WARM_UP_MODE_CTL1)/sizeof(mmCNV1_WB_WARM_UP_MODE_CTL1[0]), 0, 0 }, + { "mmCNV1_WB_WARM_UP_MODE_CTL2", REG_MMIO, 0x0266, 2, &mmCNV1_WB_WARM_UP_MODE_CTL2[0], sizeof(mmCNV1_WB_WARM_UP_MODE_CTL2)/sizeof(mmCNV1_WB_WARM_UP_MODE_CTL2[0]), 0, 0 }, + { "mmWBSCL1_WBSCL_COEF_RAM_SELECT", REG_MMIO, 0x0276, 2, &mmWBSCL1_WBSCL_COEF_RAM_SELECT[0], sizeof(mmWBSCL1_WBSCL_COEF_RAM_SELECT)/sizeof(mmWBSCL1_WBSCL_COEF_RAM_SELECT[0]), 0, 0 }, + { "mmWBSCL1_WBSCL_COEF_RAM_TAP_DATA", REG_MMIO, 0x0277, 2, &mmWBSCL1_WBSCL_COEF_RAM_TAP_DATA[0], sizeof(mmWBSCL1_WBSCL_COEF_RAM_TAP_DATA)/sizeof(mmWBSCL1_WBSCL_COEF_RAM_TAP_DATA[0]), 0, 0 }, + { "mmWBSCL1_WBSCL_MODE", REG_MMIO, 0x0278, 2, &mmWBSCL1_WBSCL_MODE[0], sizeof(mmWBSCL1_WBSCL_MODE)/sizeof(mmWBSCL1_WBSCL_MODE[0]), 0, 0 }, + { "mmWBSCL1_WBSCL_TAP_CONTROL", REG_MMIO, 0x0279, 2, &mmWBSCL1_WBSCL_TAP_CONTROL[0], sizeof(mmWBSCL1_WBSCL_TAP_CONTROL)/sizeof(mmWBSCL1_WBSCL_TAP_CONTROL[0]), 0, 0 }, + { "mmWBSCL1_WBSCL_DEST_SIZE", REG_MMIO, 0x027a, 2, &mmWBSCL1_WBSCL_DEST_SIZE[0], sizeof(mmWBSCL1_WBSCL_DEST_SIZE)/sizeof(mmWBSCL1_WBSCL_DEST_SIZE[0]), 0, 0 }, + { "mmWBSCL1_WBSCL_HORZ_FILTER_SCALE_RATIO", REG_MMIO, 0x027b, 2, &mmWBSCL1_WBSCL_HORZ_FILTER_SCALE_RATIO[0], sizeof(mmWBSCL1_WBSCL_HORZ_FILTER_SCALE_RATIO)/sizeof(mmWBSCL1_WBSCL_HORZ_FILTER_SCALE_RATIO[0]), 0, 0 }, + { "mmWBSCL1_WBSCL_HORZ_FILTER_INIT_Y_RGB", REG_MMIO, 0x027c, 2, &mmWBSCL1_WBSCL_HORZ_FILTER_INIT_Y_RGB[0], sizeof(mmWBSCL1_WBSCL_HORZ_FILTER_INIT_Y_RGB)/sizeof(mmWBSCL1_WBSCL_HORZ_FILTER_INIT_Y_RGB[0]), 0, 0 }, + { "mmWBSCL1_WBSCL_HORZ_FILTER_INIT_CBCR", REG_MMIO, 0x027d, 2, &mmWBSCL1_WBSCL_HORZ_FILTER_INIT_CBCR[0], sizeof(mmWBSCL1_WBSCL_HORZ_FILTER_INIT_CBCR)/sizeof(mmWBSCL1_WBSCL_HORZ_FILTER_INIT_CBCR[0]), 0, 0 }, + { "mmWBSCL1_WBSCL_VERT_FILTER_SCALE_RATIO", REG_MMIO, 0x027e, 2, &mmWBSCL1_WBSCL_VERT_FILTER_SCALE_RATIO[0], sizeof(mmWBSCL1_WBSCL_VERT_FILTER_SCALE_RATIO)/sizeof(mmWBSCL1_WBSCL_VERT_FILTER_SCALE_RATIO[0]), 0, 0 }, + { "mmWBSCL1_WBSCL_VERT_FILTER_INIT_Y_RGB", REG_MMIO, 0x027f, 2, &mmWBSCL1_WBSCL_VERT_FILTER_INIT_Y_RGB[0], sizeof(mmWBSCL1_WBSCL_VERT_FILTER_INIT_Y_RGB)/sizeof(mmWBSCL1_WBSCL_VERT_FILTER_INIT_Y_RGB[0]), 0, 0 }, + { "mmWBSCL1_WBSCL_VERT_FILTER_INIT_CBCR", REG_MMIO, 0x0280, 2, &mmWBSCL1_WBSCL_VERT_FILTER_INIT_CBCR[0], sizeof(mmWBSCL1_WBSCL_VERT_FILTER_INIT_CBCR)/sizeof(mmWBSCL1_WBSCL_VERT_FILTER_INIT_CBCR[0]), 0, 0 }, + { "mmWBSCL1_WBSCL_ROUND_OFFSET", REG_MMIO, 0x0281, 2, &mmWBSCL1_WBSCL_ROUND_OFFSET[0], sizeof(mmWBSCL1_WBSCL_ROUND_OFFSET)/sizeof(mmWBSCL1_WBSCL_ROUND_OFFSET[0]), 0, 0 }, + { "mmWBSCL1_WBSCL_CLAMP", REG_MMIO, 0x0282, 2, &mmWBSCL1_WBSCL_CLAMP[0], sizeof(mmWBSCL1_WBSCL_CLAMP)/sizeof(mmWBSCL1_WBSCL_CLAMP[0]), 0, 0 }, + { "mmWBSCL1_WBSCL_OVERFLOW_STATUS", REG_MMIO, 0x0283, 2, &mmWBSCL1_WBSCL_OVERFLOW_STATUS[0], sizeof(mmWBSCL1_WBSCL_OVERFLOW_STATUS)/sizeof(mmWBSCL1_WBSCL_OVERFLOW_STATUS[0]), 0, 0 }, + { "mmWBSCL1_WBSCL_COEF_RAM_CONFLICT_STATUS", REG_MMIO, 0x0284, 2, &mmWBSCL1_WBSCL_COEF_RAM_CONFLICT_STATUS[0], sizeof(mmWBSCL1_WBSCL_COEF_RAM_CONFLICT_STATUS)/sizeof(mmWBSCL1_WBSCL_COEF_RAM_CONFLICT_STATUS[0]), 0, 0 }, + { "mmWBSCL1_WBSCL_OUTSIDE_PIX_STRATEGY", REG_MMIO, 0x0285, 2, &mmWBSCL1_WBSCL_OUTSIDE_PIX_STRATEGY[0], sizeof(mmWBSCL1_WBSCL_OUTSIDE_PIX_STRATEGY)/sizeof(mmWBSCL1_WBSCL_OUTSIDE_PIX_STRATEGY[0]), 0, 0 }, + { "mmWBSCL1_WBSCL_TEST_CNTL", REG_MMIO, 0x0286, 2, &mmWBSCL1_WBSCL_TEST_CNTL[0], sizeof(mmWBSCL1_WBSCL_TEST_CNTL)/sizeof(mmWBSCL1_WBSCL_TEST_CNTL[0]), 0, 0 }, + { "mmWBSCL1_WBSCL_TEST_CRC_RED", REG_MMIO, 0x0287, 2, &mmWBSCL1_WBSCL_TEST_CRC_RED[0], sizeof(mmWBSCL1_WBSCL_TEST_CRC_RED)/sizeof(mmWBSCL1_WBSCL_TEST_CRC_RED[0]), 0, 0 }, + { "mmWBSCL1_WBSCL_TEST_CRC_GREEN", REG_MMIO, 0x0288, 2, &mmWBSCL1_WBSCL_TEST_CRC_GREEN[0], sizeof(mmWBSCL1_WBSCL_TEST_CRC_GREEN)/sizeof(mmWBSCL1_WBSCL_TEST_CRC_GREEN[0]), 0, 0 }, + { "mmWBSCL1_WBSCL_TEST_CRC_BLUE", REG_MMIO, 0x0289, 2, &mmWBSCL1_WBSCL_TEST_CRC_BLUE[0], sizeof(mmWBSCL1_WBSCL_TEST_CRC_BLUE)/sizeof(mmWBSCL1_WBSCL_TEST_CRC_BLUE[0]), 0, 0 }, + { "mmWBSCL1_WBSCL_BACKPRESSURE_CNT_EN", REG_MMIO, 0x028a, 2, &mmWBSCL1_WBSCL_BACKPRESSURE_CNT_EN[0], sizeof(mmWBSCL1_WBSCL_BACKPRESSURE_CNT_EN)/sizeof(mmWBSCL1_WBSCL_BACKPRESSURE_CNT_EN[0]), 0, 0 }, + { "mmWBSCL1_WB_MCIF_BACKPRESSURE_CNT", REG_MMIO, 0x028b, 2, &mmWBSCL1_WB_MCIF_BACKPRESSURE_CNT[0], sizeof(mmWBSCL1_WB_MCIF_BACKPRESSURE_CNT)/sizeof(mmWBSCL1_WB_MCIF_BACKPRESSURE_CNT[0]), 0, 0 }, + { "mmWBSCL1_WBSCL_RAM_SHUTDOWN", REG_MMIO, 0x028e, 2, &mmWBSCL1_WBSCL_RAM_SHUTDOWN[0], sizeof(mmWBSCL1_WBSCL_RAM_SHUTDOWN)/sizeof(mmWBSCL1_WBSCL_RAM_SHUTDOWN[0]), 0, 0 }, + { "mmDC_PERFMON4_PERFCOUNTER_CNTL", REG_MMIO, 0x02a6, 2, &mmDC_PERFMON4_PERFCOUNTER_CNTL[0], sizeof(mmDC_PERFMON4_PERFCOUNTER_CNTL)/sizeof(mmDC_PERFMON4_PERFCOUNTER_CNTL[0]), 0, 0 }, + { "mmDC_PERFMON4_PERFCOUNTER_CNTL2", REG_MMIO, 0x02a7, 2, &mmDC_PERFMON4_PERFCOUNTER_CNTL2[0], sizeof(mmDC_PERFMON4_PERFCOUNTER_CNTL2)/sizeof(mmDC_PERFMON4_PERFCOUNTER_CNTL2[0]), 0, 0 }, + { "mmDC_PERFMON4_PERFCOUNTER_STATE", REG_MMIO, 0x02a8, 2, &mmDC_PERFMON4_PERFCOUNTER_STATE[0], sizeof(mmDC_PERFMON4_PERFCOUNTER_STATE)/sizeof(mmDC_PERFMON4_PERFCOUNTER_STATE[0]), 0, 0 }, + { "mmDC_PERFMON4_PERFMON_CNTL", REG_MMIO, 0x02a9, 2, &mmDC_PERFMON4_PERFMON_CNTL[0], sizeof(mmDC_PERFMON4_PERFMON_CNTL)/sizeof(mmDC_PERFMON4_PERFMON_CNTL[0]), 0, 0 }, + { "mmDC_PERFMON4_PERFMON_CNTL2", REG_MMIO, 0x02aa, 2, &mmDC_PERFMON4_PERFMON_CNTL2[0], sizeof(mmDC_PERFMON4_PERFMON_CNTL2)/sizeof(mmDC_PERFMON4_PERFMON_CNTL2[0]), 0, 0 }, + { "mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC", REG_MMIO, 0x02ab, 2, &mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC[0], sizeof(mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC)/sizeof(mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC[0]), 0, 0 }, + { "mmDC_PERFMON4_PERFMON_CVALUE_LOW", REG_MMIO, 0x02ac, 2, &mmDC_PERFMON4_PERFMON_CVALUE_LOW[0], sizeof(mmDC_PERFMON4_PERFMON_CVALUE_LOW)/sizeof(mmDC_PERFMON4_PERFMON_CVALUE_LOW[0]), 0, 0 }, + { "mmDC_PERFMON4_PERFMON_HI", REG_MMIO, 0x02ad, 2, &mmDC_PERFMON4_PERFMON_HI[0], sizeof(mmDC_PERFMON4_PERFMON_HI)/sizeof(mmDC_PERFMON4_PERFMON_HI[0]), 0, 0 }, + { "mmDC_PERFMON4_PERFMON_LOW", REG_MMIO, 0x02ae, 2, &mmDC_PERFMON4_PERFMON_LOW[0], sizeof(mmDC_PERFMON4_PERFMON_LOW)/sizeof(mmDC_PERFMON4_PERFMON_LOW[0]), 0, 0 }, + { "mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL", REG_MMIO, 0x02b2, 2, &mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL[0], sizeof(mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL)/sizeof(mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL[0]), 0, 0 }, + { "mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R", REG_MMIO, 0x02b3, 2, &mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R[0], sizeof(mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R)/sizeof(mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R[0]), 0, 0 }, + { "mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS", REG_MMIO, 0x02b4, 2, &mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS[0], sizeof(mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS)/sizeof(mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS[0]), 0, 0 }, + { "mmMCIF_WB0_MCIF_WB_BUF_PITCH", REG_MMIO, 0x02b5, 2, &mmMCIF_WB0_MCIF_WB_BUF_PITCH[0], sizeof(mmMCIF_WB0_MCIF_WB_BUF_PITCH)/sizeof(mmMCIF_WB0_MCIF_WB_BUF_PITCH[0]), 0, 0 }, + { "mmMCIF_WB0_MCIF_WB_BUF_1_STATUS", REG_MMIO, 0x02b6, 2, &mmMCIF_WB0_MCIF_WB_BUF_1_STATUS[0], sizeof(mmMCIF_WB0_MCIF_WB_BUF_1_STATUS)/sizeof(mmMCIF_WB0_MCIF_WB_BUF_1_STATUS[0]), 0, 0 }, + { "mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2", REG_MMIO, 0x02b7, 2, &mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2[0], sizeof(mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2)/sizeof(mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2[0]), 0, 0 }, + { "mmMCIF_WB0_MCIF_WB_BUF_2_STATUS", REG_MMIO, 0x02b8, 2, &mmMCIF_WB0_MCIF_WB_BUF_2_STATUS[0], sizeof(mmMCIF_WB0_MCIF_WB_BUF_2_STATUS)/sizeof(mmMCIF_WB0_MCIF_WB_BUF_2_STATUS[0]), 0, 0 }, + { "mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2", REG_MMIO, 0x02b9, 2, &mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2[0], sizeof(mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2)/sizeof(mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2[0]), 0, 0 }, + { "mmMCIF_WB0_MCIF_WB_BUF_3_STATUS", REG_MMIO, 0x02ba, 2, &mmMCIF_WB0_MCIF_WB_BUF_3_STATUS[0], sizeof(mmMCIF_WB0_MCIF_WB_BUF_3_STATUS)/sizeof(mmMCIF_WB0_MCIF_WB_BUF_3_STATUS[0]), 0, 0 }, + { "mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2", REG_MMIO, 0x02bb, 2, &mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2[0], sizeof(mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2)/sizeof(mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2[0]), 0, 0 }, + { "mmMCIF_WB0_MCIF_WB_BUF_4_STATUS", REG_MMIO, 0x02bc, 2, &mmMCIF_WB0_MCIF_WB_BUF_4_STATUS[0], sizeof(mmMCIF_WB0_MCIF_WB_BUF_4_STATUS)/sizeof(mmMCIF_WB0_MCIF_WB_BUF_4_STATUS[0]), 0, 0 }, + { "mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2", REG_MMIO, 0x02bd, 2, &mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2[0], sizeof(mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2)/sizeof(mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2[0]), 0, 0 }, + { "mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL", REG_MMIO, 0x02be, 2, &mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL[0], sizeof(mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL)/sizeof(mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL[0]), 0, 0 }, + { "mmMCIF_WB0_MCIF_WB_SCLK_CHANGE", REG_MMIO, 0x02bf, 2, &mmMCIF_WB0_MCIF_WB_SCLK_CHANGE[0], sizeof(mmMCIF_WB0_MCIF_WB_SCLK_CHANGE)/sizeof(mmMCIF_WB0_MCIF_WB_SCLK_CHANGE[0]), 0, 0 }, + { "mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y", REG_MMIO, 0x02c2, 2, &mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y[0], sizeof(mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y)/sizeof(mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y[0]), 0, 0 }, + { "mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET", REG_MMIO, 0x02c3, 2, &mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET[0], sizeof(mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET)/sizeof(mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET[0]), 0, 0 }, + { "mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C", REG_MMIO, 0x02c4, 2, &mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C[0], sizeof(mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C)/sizeof(mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C[0]), 0, 0 }, + { "mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET", REG_MMIO, 0x02c5, 2, &mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET[0], sizeof(mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET)/sizeof(mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET[0]), 0, 0 }, + { "mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y", REG_MMIO, 0x02c6, 2, &mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y[0], sizeof(mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y)/sizeof(mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y[0]), 0, 0 }, + { "mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET", REG_MMIO, 0x02c7, 2, &mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET[0], sizeof(mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET)/sizeof(mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET[0]), 0, 0 }, + { "mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C", REG_MMIO, 0x02c8, 2, &mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C[0], sizeof(mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C)/sizeof(mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C[0]), 0, 0 }, + { "mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET", REG_MMIO, 0x02c9, 2, &mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET[0], sizeof(mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET)/sizeof(mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET[0]), 0, 0 }, + { "mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y", REG_MMIO, 0x02ca, 2, &mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y[0], sizeof(mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y)/sizeof(mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y[0]), 0, 0 }, + { "mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET", REG_MMIO, 0x02cb, 2, &mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET[0], sizeof(mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET)/sizeof(mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET[0]), 0, 0 }, + { "mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C", REG_MMIO, 0x02cc, 2, &mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C[0], sizeof(mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C)/sizeof(mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C[0]), 0, 0 }, + { "mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET", REG_MMIO, 0x02cd, 2, &mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET[0], sizeof(mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET)/sizeof(mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET[0]), 0, 0 }, + { "mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y", REG_MMIO, 0x02ce, 2, &mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y[0], sizeof(mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y)/sizeof(mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y[0]), 0, 0 }, + { "mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET", REG_MMIO, 0x02cf, 2, &mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET[0], sizeof(mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET)/sizeof(mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET[0]), 0, 0 }, + { "mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C", REG_MMIO, 0x02d0, 2, &mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C[0], sizeof(mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C)/sizeof(mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C[0]), 0, 0 }, + { "mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET", REG_MMIO, 0x02d1, 2, &mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET[0], sizeof(mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET)/sizeof(mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET[0]), 0, 0 }, + { "mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL", REG_MMIO, 0x02d2, 2, &mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL[0], sizeof(mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL)/sizeof(mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL[0]), 0, 0 }, + { "mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK", REG_MMIO, 0x02d3, 2, &mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK[0], sizeof(mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK)/sizeof(mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK[0]), 0, 0 }, + { "mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL", REG_MMIO, 0x02d4, 2, &mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL[0], sizeof(mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL)/sizeof(mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL[0]), 0, 0 }, + { "mmMCIF_WB0_MCIF_WB_WATERMARK", REG_MMIO, 0x02d5, 2, &mmMCIF_WB0_MCIF_WB_WATERMARK[0], sizeof(mmMCIF_WB0_MCIF_WB_WATERMARK)/sizeof(mmMCIF_WB0_MCIF_WB_WATERMARK[0]), 0, 0 }, + { "mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL", REG_MMIO, 0x02d6, 2, &mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL[0], sizeof(mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL)/sizeof(mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL[0]), 0, 0 }, + { "mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL", REG_MMIO, 0x02d7, 2, &mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL[0], sizeof(mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL)/sizeof(mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL[0]), 0, 0 }, + { "mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL", REG_MMIO, 0x02d8, 2, &mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL[0], sizeof(mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL)/sizeof(mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL[0]), 0, 0 }, + { "mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL", REG_MMIO, 0x02d9, 2, &mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL[0], sizeof(mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL)/sizeof(mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL[0]), 0, 0 }, + { "mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE", REG_MMIO, 0x02db, 2, &mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE[0], sizeof(mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE)/sizeof(mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE[0]), 0, 0 }, + { "mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE", REG_MMIO, 0x02dc, 2, &mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE[0], sizeof(mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE)/sizeof(mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE[0]), 0, 0 }, + { "mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL", REG_MMIO, 0x02f2, 2, &mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL[0], sizeof(mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL)/sizeof(mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL[0]), 0, 0 }, + { "mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R", REG_MMIO, 0x02f3, 2, &mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R[0], sizeof(mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R)/sizeof(mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R[0]), 0, 0 }, + { "mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS", REG_MMIO, 0x02f4, 2, &mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS[0], sizeof(mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS)/sizeof(mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS[0]), 0, 0 }, + { "mmMCIF_WB1_MCIF_WB_BUF_PITCH", REG_MMIO, 0x02f5, 2, &mmMCIF_WB1_MCIF_WB_BUF_PITCH[0], sizeof(mmMCIF_WB1_MCIF_WB_BUF_PITCH)/sizeof(mmMCIF_WB1_MCIF_WB_BUF_PITCH[0]), 0, 0 }, + { "mmMCIF_WB1_MCIF_WB_BUF_1_STATUS", REG_MMIO, 0x02f6, 2, &mmMCIF_WB1_MCIF_WB_BUF_1_STATUS[0], sizeof(mmMCIF_WB1_MCIF_WB_BUF_1_STATUS)/sizeof(mmMCIF_WB1_MCIF_WB_BUF_1_STATUS[0]), 0, 0 }, + { "mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2", REG_MMIO, 0x02f7, 2, &mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2[0], sizeof(mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2)/sizeof(mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2[0]), 0, 0 }, + { "mmMCIF_WB1_MCIF_WB_BUF_2_STATUS", REG_MMIO, 0x02f8, 2, &mmMCIF_WB1_MCIF_WB_BUF_2_STATUS[0], sizeof(mmMCIF_WB1_MCIF_WB_BUF_2_STATUS)/sizeof(mmMCIF_WB1_MCIF_WB_BUF_2_STATUS[0]), 0, 0 }, + { "mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2", REG_MMIO, 0x02f9, 2, &mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2[0], sizeof(mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2)/sizeof(mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2[0]), 0, 0 }, + { "mmMCIF_WB1_MCIF_WB_BUF_3_STATUS", REG_MMIO, 0x02fa, 2, &mmMCIF_WB1_MCIF_WB_BUF_3_STATUS[0], sizeof(mmMCIF_WB1_MCIF_WB_BUF_3_STATUS)/sizeof(mmMCIF_WB1_MCIF_WB_BUF_3_STATUS[0]), 0, 0 }, + { "mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2", REG_MMIO, 0x02fb, 2, &mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2[0], sizeof(mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2)/sizeof(mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2[0]), 0, 0 }, + { "mmMCIF_WB1_MCIF_WB_BUF_4_STATUS", REG_MMIO, 0x02fc, 2, &mmMCIF_WB1_MCIF_WB_BUF_4_STATUS[0], sizeof(mmMCIF_WB1_MCIF_WB_BUF_4_STATUS)/sizeof(mmMCIF_WB1_MCIF_WB_BUF_4_STATUS[0]), 0, 0 }, + { "mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2", REG_MMIO, 0x02fd, 2, &mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2[0], sizeof(mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2)/sizeof(mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2[0]), 0, 0 }, + { "mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL", REG_MMIO, 0x02fe, 2, &mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL[0], sizeof(mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL)/sizeof(mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL[0]), 0, 0 }, + { "mmMCIF_WB1_MCIF_WB_SCLK_CHANGE", REG_MMIO, 0x02ff, 2, &mmMCIF_WB1_MCIF_WB_SCLK_CHANGE[0], sizeof(mmMCIF_WB1_MCIF_WB_SCLK_CHANGE)/sizeof(mmMCIF_WB1_MCIF_WB_SCLK_CHANGE[0]), 0, 0 }, + { "mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y", REG_MMIO, 0x0302, 2, &mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y[0], sizeof(mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y)/sizeof(mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y[0]), 0, 0 }, + { "mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET", REG_MMIO, 0x0303, 2, &mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET[0], sizeof(mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET)/sizeof(mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET[0]), 0, 0 }, + { "mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C", REG_MMIO, 0x0304, 2, &mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C[0], sizeof(mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C)/sizeof(mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C[0]), 0, 0 }, + { "mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET", REG_MMIO, 0x0305, 2, &mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET[0], sizeof(mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET)/sizeof(mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET[0]), 0, 0 }, + { "mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y", REG_MMIO, 0x0306, 2, &mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y[0], sizeof(mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y)/sizeof(mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y[0]), 0, 0 }, + { "mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET", REG_MMIO, 0x0307, 2, &mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET[0], sizeof(mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET)/sizeof(mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET[0]), 0, 0 }, + { "mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C", REG_MMIO, 0x0308, 2, &mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C[0], sizeof(mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C)/sizeof(mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C[0]), 0, 0 }, + { "mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET", REG_MMIO, 0x0309, 2, &mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET[0], sizeof(mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET)/sizeof(mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET[0]), 0, 0 }, + { "mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y", REG_MMIO, 0x030a, 2, &mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y[0], sizeof(mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y)/sizeof(mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y[0]), 0, 0 }, + { "mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET", REG_MMIO, 0x030b, 2, &mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET[0], sizeof(mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET)/sizeof(mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET[0]), 0, 0 }, + { "mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C", REG_MMIO, 0x030c, 2, &mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C[0], sizeof(mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C)/sizeof(mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C[0]), 0, 0 }, + { "mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET", REG_MMIO, 0x030d, 2, &mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET[0], sizeof(mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET)/sizeof(mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET[0]), 0, 0 }, + { "mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y", REG_MMIO, 0x030e, 2, &mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y[0], sizeof(mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y)/sizeof(mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y[0]), 0, 0 }, + { "mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET", REG_MMIO, 0x030f, 2, &mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET[0], sizeof(mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET)/sizeof(mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET[0]), 0, 0 }, + { "mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C", REG_MMIO, 0x0310, 2, &mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C[0], sizeof(mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C)/sizeof(mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C[0]), 0, 0 }, + { "mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET", REG_MMIO, 0x0311, 2, &mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET[0], sizeof(mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET)/sizeof(mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET[0]), 0, 0 }, + { "mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL", REG_MMIO, 0x0312, 2, &mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL[0], sizeof(mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL)/sizeof(mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL[0]), 0, 0 }, + { "mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK", REG_MMIO, 0x0313, 2, &mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK[0], sizeof(mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK)/sizeof(mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK[0]), 0, 0 }, + { "mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL", REG_MMIO, 0x0314, 2, &mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL[0], sizeof(mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL)/sizeof(mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL[0]), 0, 0 }, + { "mmMCIF_WB1_MCIF_WB_WATERMARK", REG_MMIO, 0x0315, 2, &mmMCIF_WB1_MCIF_WB_WATERMARK[0], sizeof(mmMCIF_WB1_MCIF_WB_WATERMARK)/sizeof(mmMCIF_WB1_MCIF_WB_WATERMARK[0]), 0, 0 }, + { "mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL", REG_MMIO, 0x0316, 2, &mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL[0], sizeof(mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL)/sizeof(mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL[0]), 0, 0 }, + { "mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL", REG_MMIO, 0x0317, 2, &mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL[0], sizeof(mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL)/sizeof(mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL[0]), 0, 0 }, + { "mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL", REG_MMIO, 0x0318, 2, &mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL[0], sizeof(mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL)/sizeof(mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL[0]), 0, 0 }, + { "mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL", REG_MMIO, 0x0319, 2, &mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL[0], sizeof(mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL)/sizeof(mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL[0]), 0, 0 }, + { "mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE", REG_MMIO, 0x031b, 2, &mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE[0], sizeof(mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE)/sizeof(mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE[0]), 0, 0 }, + { "mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE", REG_MMIO, 0x031c, 2, &mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE[0], sizeof(mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE)/sizeof(mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE[0]), 0, 0 }, + { "mmWBIF0_MISC_CTRL", REG_MMIO, 0x0333, 2, &mmWBIF0_MISC_CTRL[0], sizeof(mmWBIF0_MISC_CTRL)/sizeof(mmWBIF0_MISC_CTRL[0]), 0, 0 }, + { "mmWBIF0_SMU_WM_CONTROL", REG_MMIO, 0x0334, 2, &mmWBIF0_SMU_WM_CONTROL[0], sizeof(mmWBIF0_SMU_WM_CONTROL)/sizeof(mmWBIF0_SMU_WM_CONTROL[0]), 0, 0 }, + { "mmWBIF0_PHASE0_OUTSTANDING_COUNTER", REG_MMIO, 0x0335, 2, &mmWBIF0_PHASE0_OUTSTANDING_COUNTER[0], sizeof(mmWBIF0_PHASE0_OUTSTANDING_COUNTER)/sizeof(mmWBIF0_PHASE0_OUTSTANDING_COUNTER[0]), 0, 0 }, + { "mmWBIF0_PHASE1_OUTSTANDING_COUNTER", REG_MMIO, 0x0336, 2, &mmWBIF0_PHASE1_OUTSTANDING_COUNTER[0], sizeof(mmWBIF0_PHASE1_OUTSTANDING_COUNTER)/sizeof(mmWBIF0_PHASE1_OUTSTANDING_COUNTER[0]), 0, 0 }, + { "mmWBIF1_MISC_CTRL", REG_MMIO, 0x0337, 2, &mmWBIF1_MISC_CTRL[0], sizeof(mmWBIF1_MISC_CTRL)/sizeof(mmWBIF1_MISC_CTRL[0]), 0, 0 }, + { "mmWBIF1_SMU_WM_CONTROL", REG_MMIO, 0x0338, 2, &mmWBIF1_SMU_WM_CONTROL[0], sizeof(mmWBIF1_SMU_WM_CONTROL)/sizeof(mmWBIF1_SMU_WM_CONTROL[0]), 0, 0 }, + { "mmWBIF1_PHASE0_OUTSTANDING_COUNTER", REG_MMIO, 0x0339, 2, &mmWBIF1_PHASE0_OUTSTANDING_COUNTER[0], sizeof(mmWBIF1_PHASE0_OUTSTANDING_COUNTER)/sizeof(mmWBIF1_PHASE0_OUTSTANDING_COUNTER[0]), 0, 0 }, + { "mmWBIF1_PHASE1_OUTSTANDING_COUNTER", REG_MMIO, 0x033a, 2, &mmWBIF1_PHASE1_OUTSTANDING_COUNTER[0], sizeof(mmWBIF1_PHASE1_OUTSTANDING_COUNTER)/sizeof(mmWBIF1_PHASE1_OUTSTANDING_COUNTER[0]), 0, 0 }, + { "mmVGA_SRC_SPLIT_CNTL", REG_MMIO, 0x033b, 2, &mmVGA_SRC_SPLIT_CNTL[0], sizeof(mmVGA_SRC_SPLIT_CNTL)/sizeof(mmVGA_SRC_SPLIT_CNTL[0]), 0, 0 }, + { "mmMMHUBBUB_MEM_PWR_STATUS", REG_MMIO, 0x033c, 2, &mmMMHUBBUB_MEM_PWR_STATUS[0], sizeof(mmMMHUBBUB_MEM_PWR_STATUS)/sizeof(mmMMHUBBUB_MEM_PWR_STATUS[0]), 0, 0 }, + { "mmMMHUBBUB_MEM_PWR_CNTL", REG_MMIO, 0x033d, 2, &mmMMHUBBUB_MEM_PWR_CNTL[0], sizeof(mmMMHUBBUB_MEM_PWR_CNTL)/sizeof(mmMMHUBBUB_MEM_PWR_CNTL[0]), 0, 0 }, + { "mmMMHUBBUB_CLOCK_CNTL", REG_MMIO, 0x033e, 2, &mmMMHUBBUB_CLOCK_CNTL[0], sizeof(mmMMHUBBUB_CLOCK_CNTL)/sizeof(mmMMHUBBUB_CLOCK_CNTL[0]), 0, 0 }, + { "mmMMHUBBUB_SOFT_RESET", REG_MMIO, 0x033f, 2, &mmMMHUBBUB_SOFT_RESET[0], sizeof(mmMMHUBBUB_SOFT_RESET)/sizeof(mmMMHUBBUB_SOFT_RESET[0]), 0, 0 }, + { "mmMCIF_CONTROL", REG_MMIO, 0x034a, 2, &mmMCIF_CONTROL[0], sizeof(mmMCIF_CONTROL)/sizeof(mmMCIF_CONTROL[0]), 0, 0 }, + { "mmMCIF_WRITE_COMBINE_CONTROL", REG_MMIO, 0x034b, 2, &mmMCIF_WRITE_COMBINE_CONTROL[0], sizeof(mmMCIF_WRITE_COMBINE_CONTROL)/sizeof(mmMCIF_WRITE_COMBINE_CONTROL[0]), 0, 0 }, + { "mmMCIF_PHASE0_OUTSTANDING_COUNTER", REG_MMIO, 0x034e, 2, &mmMCIF_PHASE0_OUTSTANDING_COUNTER[0], sizeof(mmMCIF_PHASE0_OUTSTANDING_COUNTER)/sizeof(mmMCIF_PHASE0_OUTSTANDING_COUNTER[0]), 0, 0 }, + { "mmMCIF_PHASE1_OUTSTANDING_COUNTER", REG_MMIO, 0x034f, 2, &mmMCIF_PHASE1_OUTSTANDING_COUNTER[0], sizeof(mmMCIF_PHASE1_OUTSTANDING_COUNTER)/sizeof(mmMCIF_PHASE1_OUTSTANDING_COUNTER[0]), 0, 0 }, + { "mmMCIF_PHASE2_OUTSTANDING_COUNTER", REG_MMIO, 0x0350, 2, &mmMCIF_PHASE2_OUTSTANDING_COUNTER[0], sizeof(mmMCIF_PHASE2_OUTSTANDING_COUNTER)/sizeof(mmMCIF_PHASE2_OUTSTANDING_COUNTER[0]), 0, 0 }, + { "mmDC_PERFMON5_PERFCOUNTER_CNTL", REG_MMIO, 0x0352, 2, &mmDC_PERFMON5_PERFCOUNTER_CNTL[0], sizeof(mmDC_PERFMON5_PERFCOUNTER_CNTL)/sizeof(mmDC_PERFMON5_PERFCOUNTER_CNTL[0]), 0, 0 }, + { "mmDC_PERFMON5_PERFCOUNTER_CNTL2", REG_MMIO, 0x0353, 2, &mmDC_PERFMON5_PERFCOUNTER_CNTL2[0], sizeof(mmDC_PERFMON5_PERFCOUNTER_CNTL2)/sizeof(mmDC_PERFMON5_PERFCOUNTER_CNTL2[0]), 0, 0 }, + { "mmDC_PERFMON5_PERFCOUNTER_STATE", REG_MMIO, 0x0354, 2, &mmDC_PERFMON5_PERFCOUNTER_STATE[0], sizeof(mmDC_PERFMON5_PERFCOUNTER_STATE)/sizeof(mmDC_PERFMON5_PERFCOUNTER_STATE[0]), 0, 0 }, + { "mmDC_PERFMON5_PERFMON_CNTL", REG_MMIO, 0x0355, 2, &mmDC_PERFMON5_PERFMON_CNTL[0], sizeof(mmDC_PERFMON5_PERFMON_CNTL)/sizeof(mmDC_PERFMON5_PERFMON_CNTL[0]), 0, 0 }, + { "mmDC_PERFMON5_PERFMON_CNTL2", REG_MMIO, 0x0356, 2, &mmDC_PERFMON5_PERFMON_CNTL2[0], sizeof(mmDC_PERFMON5_PERFMON_CNTL2)/sizeof(mmDC_PERFMON5_PERFMON_CNTL2[0]), 0, 0 }, + { "mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC", REG_MMIO, 0x0357, 2, &mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC[0], sizeof(mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC)/sizeof(mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC[0]), 0, 0 }, + { "mmDC_PERFMON5_PERFMON_CVALUE_LOW", REG_MMIO, 0x0358, 2, &mmDC_PERFMON5_PERFMON_CVALUE_LOW[0], sizeof(mmDC_PERFMON5_PERFMON_CVALUE_LOW)/sizeof(mmDC_PERFMON5_PERFMON_CVALUE_LOW[0]), 0, 0 }, + { "mmDC_PERFMON5_PERFMON_HI", REG_MMIO, 0x0359, 2, &mmDC_PERFMON5_PERFMON_HI[0], sizeof(mmDC_PERFMON5_PERFMON_HI)/sizeof(mmDC_PERFMON5_PERFMON_HI[0]), 0, 0 }, + { "mmDC_PERFMON5_PERFMON_LOW", REG_MMIO, 0x035a, 2, &mmDC_PERFMON5_PERFMON_LOW[0], sizeof(mmDC_PERFMON5_PERFMON_LOW)/sizeof(mmDC_PERFMON5_PERFMON_LOW[0]), 0, 0 }, + { "mmAZF0STREAM0_AZALIA_STREAM_INDEX", REG_MMIO, 0x035e, 2, &mmAZF0STREAM0_AZALIA_STREAM_INDEX[0], sizeof(mmAZF0STREAM0_AZALIA_STREAM_INDEX)/sizeof(mmAZF0STREAM0_AZALIA_STREAM_INDEX[0]), 0, 0 }, + { "mmAZF0STREAM0_AZALIA_STREAM_DATA", REG_MMIO, 0x035f, 2, &mmAZF0STREAM0_AZALIA_STREAM_DATA[0], sizeof(mmAZF0STREAM0_AZALIA_STREAM_DATA)/sizeof(mmAZF0STREAM0_AZALIA_STREAM_DATA[0]), 0, 0 }, + { "mmAZF0STREAM1_AZALIA_STREAM_INDEX", REG_MMIO, 0x0360, 2, &mmAZF0STREAM1_AZALIA_STREAM_INDEX[0], sizeof(mmAZF0STREAM1_AZALIA_STREAM_INDEX)/sizeof(mmAZF0STREAM1_AZALIA_STREAM_INDEX[0]), 0, 0 }, + { "mmAZF0STREAM1_AZALIA_STREAM_DATA", REG_MMIO, 0x0361, 2, &mmAZF0STREAM1_AZALIA_STREAM_DATA[0], sizeof(mmAZF0STREAM1_AZALIA_STREAM_DATA)/sizeof(mmAZF0STREAM1_AZALIA_STREAM_DATA[0]), 0, 0 }, + { "mmAZF0STREAM2_AZALIA_STREAM_INDEX", REG_MMIO, 0x0362, 2, &mmAZF0STREAM2_AZALIA_STREAM_INDEX[0], sizeof(mmAZF0STREAM2_AZALIA_STREAM_INDEX)/sizeof(mmAZF0STREAM2_AZALIA_STREAM_INDEX[0]), 0, 0 }, + { "mmAZF0STREAM2_AZALIA_STREAM_DATA", REG_MMIO, 0x0363, 2, &mmAZF0STREAM2_AZALIA_STREAM_DATA[0], sizeof(mmAZF0STREAM2_AZALIA_STREAM_DATA)/sizeof(mmAZF0STREAM2_AZALIA_STREAM_DATA[0]), 0, 0 }, + { "mmAZF0STREAM3_AZALIA_STREAM_INDEX", REG_MMIO, 0x0364, 2, &mmAZF0STREAM3_AZALIA_STREAM_INDEX[0], sizeof(mmAZF0STREAM3_AZALIA_STREAM_INDEX)/sizeof(mmAZF0STREAM3_AZALIA_STREAM_INDEX[0]), 0, 0 }, + { "mmAZF0STREAM3_AZALIA_STREAM_DATA", REG_MMIO, 0x0365, 2, &mmAZF0STREAM3_AZALIA_STREAM_DATA[0], sizeof(mmAZF0STREAM3_AZALIA_STREAM_DATA)/sizeof(mmAZF0STREAM3_AZALIA_STREAM_DATA[0]), 0, 0 }, + { "mmAZF0STREAM4_AZALIA_STREAM_INDEX", REG_MMIO, 0x0366, 2, &mmAZF0STREAM4_AZALIA_STREAM_INDEX[0], sizeof(mmAZF0STREAM4_AZALIA_STREAM_INDEX)/sizeof(mmAZF0STREAM4_AZALIA_STREAM_INDEX[0]), 0, 0 }, + { "mmAZF0STREAM4_AZALIA_STREAM_DATA", REG_MMIO, 0x0367, 2, &mmAZF0STREAM4_AZALIA_STREAM_DATA[0], sizeof(mmAZF0STREAM4_AZALIA_STREAM_DATA)/sizeof(mmAZF0STREAM4_AZALIA_STREAM_DATA[0]), 0, 0 }, + { "mmAZF0STREAM5_AZALIA_STREAM_INDEX", REG_MMIO, 0x0368, 2, &mmAZF0STREAM5_AZALIA_STREAM_INDEX[0], sizeof(mmAZF0STREAM5_AZALIA_STREAM_INDEX)/sizeof(mmAZF0STREAM5_AZALIA_STREAM_INDEX[0]), 0, 0 }, + { "mmAZF0STREAM5_AZALIA_STREAM_DATA", REG_MMIO, 0x0369, 2, &mmAZF0STREAM5_AZALIA_STREAM_DATA[0], sizeof(mmAZF0STREAM5_AZALIA_STREAM_DATA)/sizeof(mmAZF0STREAM5_AZALIA_STREAM_DATA[0]), 0, 0 }, + { "mmAZF0STREAM6_AZALIA_STREAM_INDEX", REG_MMIO, 0x036a, 2, &mmAZF0STREAM6_AZALIA_STREAM_INDEX[0], sizeof(mmAZF0STREAM6_AZALIA_STREAM_INDEX)/sizeof(mmAZF0STREAM6_AZALIA_STREAM_INDEX[0]), 0, 0 }, + { "mmAZF0STREAM6_AZALIA_STREAM_DATA", REG_MMIO, 0x036b, 2, &mmAZF0STREAM6_AZALIA_STREAM_DATA[0], sizeof(mmAZF0STREAM6_AZALIA_STREAM_DATA)/sizeof(mmAZF0STREAM6_AZALIA_STREAM_DATA[0]), 0, 0 }, + { "mmAZF0STREAM7_AZALIA_STREAM_INDEX", REG_MMIO, 0x036c, 2, &mmAZF0STREAM7_AZALIA_STREAM_INDEX[0], sizeof(mmAZF0STREAM7_AZALIA_STREAM_INDEX)/sizeof(mmAZF0STREAM7_AZALIA_STREAM_INDEX[0]), 0, 0 }, + { "mmAZF0STREAM7_AZALIA_STREAM_DATA", REG_MMIO, 0x036d, 2, &mmAZF0STREAM7_AZALIA_STREAM_DATA[0], sizeof(mmAZF0STREAM7_AZALIA_STREAM_DATA)/sizeof(mmAZF0STREAM7_AZALIA_STREAM_DATA[0]), 0, 0 }, + { "mmAZ_CLOCK_CNTL", REG_MMIO, 0x0372, 2, &mmAZ_CLOCK_CNTL[0], sizeof(mmAZ_CLOCK_CNTL)/sizeof(mmAZ_CLOCK_CNTL[0]), 0, 0 }, + { "mmDC_PERFMON6_PERFCOUNTER_CNTL", REG_MMIO, 0x037a, 2, &mmDC_PERFMON6_PERFCOUNTER_CNTL[0], sizeof(mmDC_PERFMON6_PERFCOUNTER_CNTL)/sizeof(mmDC_PERFMON6_PERFCOUNTER_CNTL[0]), 0, 0 }, + { "mmDC_PERFMON6_PERFCOUNTER_CNTL2", REG_MMIO, 0x037b, 2, &mmDC_PERFMON6_PERFCOUNTER_CNTL2[0], sizeof(mmDC_PERFMON6_PERFCOUNTER_CNTL2)/sizeof(mmDC_PERFMON6_PERFCOUNTER_CNTL2[0]), 0, 0 }, + { "mmDC_PERFMON6_PERFCOUNTER_STATE", REG_MMIO, 0x037c, 2, &mmDC_PERFMON6_PERFCOUNTER_STATE[0], sizeof(mmDC_PERFMON6_PERFCOUNTER_STATE)/sizeof(mmDC_PERFMON6_PERFCOUNTER_STATE[0]), 0, 0 }, + { "mmDC_PERFMON6_PERFMON_CNTL", REG_MMIO, 0x037d, 2, &mmDC_PERFMON6_PERFMON_CNTL[0], sizeof(mmDC_PERFMON6_PERFMON_CNTL)/sizeof(mmDC_PERFMON6_PERFMON_CNTL[0]), 0, 0 }, + { "mmDC_PERFMON6_PERFMON_CNTL2", REG_MMIO, 0x037e, 2, &mmDC_PERFMON6_PERFMON_CNTL2[0], sizeof(mmDC_PERFMON6_PERFMON_CNTL2)/sizeof(mmDC_PERFMON6_PERFMON_CNTL2[0]), 0, 0 }, + { "mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC", REG_MMIO, 0x037f, 2, &mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC[0], sizeof(mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC)/sizeof(mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC[0]), 0, 0 }, + { "mmDC_PERFMON6_PERFMON_CVALUE_LOW", REG_MMIO, 0x0380, 2, &mmDC_PERFMON6_PERFMON_CVALUE_LOW[0], sizeof(mmDC_PERFMON6_PERFMON_CVALUE_LOW)/sizeof(mmDC_PERFMON6_PERFMON_CVALUE_LOW[0]), 0, 0 }, + { "mmDC_PERFMON6_PERFMON_HI", REG_MMIO, 0x0381, 2, &mmDC_PERFMON6_PERFMON_HI[0], sizeof(mmDC_PERFMON6_PERFMON_HI)/sizeof(mmDC_PERFMON6_PERFMON_HI[0]), 0, 0 }, + { "mmDC_PERFMON6_PERFMON_LOW", REG_MMIO, 0x0382, 2, &mmDC_PERFMON6_PERFMON_LOW[0], sizeof(mmDC_PERFMON6_PERFMON_LOW)/sizeof(mmDC_PERFMON6_PERFMON_LOW[0]), 0, 0 }, + { "mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX", REG_MMIO, 0x0386, 2, &mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX[0], sizeof(mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX)/sizeof(mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX[0]), 0, 0 }, + { "mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA", REG_MMIO, 0x0387, 2, &mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA[0], sizeof(mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA)/sizeof(mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA[0]), 0, 0 }, + { "mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX", REG_MMIO, 0x038c, 2, &mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX[0], sizeof(mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX)/sizeof(mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX[0]), 0, 0 }, + { "mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA", REG_MMIO, 0x038d, 2, &mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA[0], sizeof(mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA)/sizeof(mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA[0]), 0, 0 }, + { "mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX", REG_MMIO, 0x0392, 2, &mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX[0], sizeof(mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX)/sizeof(mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX[0]), 0, 0 }, + { "mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA", REG_MMIO, 0x0393, 2, &mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA[0], sizeof(mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA)/sizeof(mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA[0]), 0, 0 }, + { "mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX", REG_MMIO, 0x0398, 2, &mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX[0], sizeof(mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX)/sizeof(mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX[0]), 0, 0 }, + { "mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA", REG_MMIO, 0x0399, 2, &mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA[0], sizeof(mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA)/sizeof(mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA[0]), 0, 0 }, + { "mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX", REG_MMIO, 0x039e, 2, &mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX[0], sizeof(mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX)/sizeof(mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX[0]), 0, 0 }, + { "mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA", REG_MMIO, 0x039f, 2, &mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA[0], sizeof(mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA)/sizeof(mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA[0]), 0, 0 }, + { "mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX", REG_MMIO, 0x03a4, 2, &mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX[0], sizeof(mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX)/sizeof(mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX[0]), 0, 0 }, + { "mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA", REG_MMIO, 0x03a5, 2, &mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA[0], sizeof(mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA)/sizeof(mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA[0]), 0, 0 }, + { "mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX", REG_MMIO, 0x03aa, 2, &mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX[0], sizeof(mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX)/sizeof(mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX[0]), 0, 0 }, + { "mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA", REG_MMIO, 0x03ab, 2, &mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA[0], sizeof(mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA)/sizeof(mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA[0]), 0, 0 }, + { "mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX", REG_MMIO, 0x03b0, 2, &mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX[0], sizeof(mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX)/sizeof(mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX[0]), 0, 0 }, + { "mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA", REG_MMIO, 0x03b1, 2, &mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA[0], sizeof(mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA)/sizeof(mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA[0]), 0, 0 }, + { "mmAZALIA_CONTROLLER_CLOCK_GATING", REG_MMIO, 0x03c2, 2, &mmAZALIA_CONTROLLER_CLOCK_GATING[0], sizeof(mmAZALIA_CONTROLLER_CLOCK_GATING)/sizeof(mmAZALIA_CONTROLLER_CLOCK_GATING[0]), 0, 0 }, + { "mmAZALIA_AUDIO_DTO", REG_MMIO, 0x03c3, 2, &mmAZALIA_AUDIO_DTO[0], sizeof(mmAZALIA_AUDIO_DTO)/sizeof(mmAZALIA_AUDIO_DTO[0]), 0, 0 }, + { "mmAZALIA_AUDIO_DTO_CONTROL", REG_MMIO, 0x03c4, 2, &mmAZALIA_AUDIO_DTO_CONTROL[0], sizeof(mmAZALIA_AUDIO_DTO_CONTROL)/sizeof(mmAZALIA_AUDIO_DTO_CONTROL[0]), 0, 0 }, + { "mmAZALIA_SOCCLK_CONTROL", REG_MMIO, 0x03c5, 2, &mmAZALIA_SOCCLK_CONTROL[0], sizeof(mmAZALIA_SOCCLK_CONTROL)/sizeof(mmAZALIA_SOCCLK_CONTROL[0]), 0, 0 }, + { "mmAZALIA_UNDERFLOW_FILLER_SAMPLE", REG_MMIO, 0x03c6, 2, &mmAZALIA_UNDERFLOW_FILLER_SAMPLE[0], sizeof(mmAZALIA_UNDERFLOW_FILLER_SAMPLE)/sizeof(mmAZALIA_UNDERFLOW_FILLER_SAMPLE[0]), 0, 0 }, + { "mmAZALIA_DATA_DMA_CONTROL", REG_MMIO, 0x03c7, 2, &mmAZALIA_DATA_DMA_CONTROL[0], sizeof(mmAZALIA_DATA_DMA_CONTROL)/sizeof(mmAZALIA_DATA_DMA_CONTROL[0]), 0, 0 }, + { "mmAZALIA_BDL_DMA_CONTROL", REG_MMIO, 0x03c8, 2, &mmAZALIA_BDL_DMA_CONTROL[0], sizeof(mmAZALIA_BDL_DMA_CONTROL)/sizeof(mmAZALIA_BDL_DMA_CONTROL[0]), 0, 0 }, + { "mmAZALIA_RIRB_AND_DP_CONTROL", REG_MMIO, 0x03c9, 2, &mmAZALIA_RIRB_AND_DP_CONTROL[0], sizeof(mmAZALIA_RIRB_AND_DP_CONTROL)/sizeof(mmAZALIA_RIRB_AND_DP_CONTROL[0]), 0, 0 }, + { "mmAZALIA_CORB_DMA_CONTROL", REG_MMIO, 0x03ca, 2, &mmAZALIA_CORB_DMA_CONTROL[0], sizeof(mmAZALIA_CORB_DMA_CONTROL)/sizeof(mmAZALIA_CORB_DMA_CONTROL[0]), 0, 0 }, + { "mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER", REG_MMIO, 0x03d1, 2, &mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER[0], sizeof(mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER)/sizeof(mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER[0]), 0, 0 }, + { "mmAZALIA_CYCLIC_BUFFER_SYNC", REG_MMIO, 0x03d2, 2, &mmAZALIA_CYCLIC_BUFFER_SYNC[0], sizeof(mmAZALIA_CYCLIC_BUFFER_SYNC)/sizeof(mmAZALIA_CYCLIC_BUFFER_SYNC[0]), 0, 0 }, + { "mmAZALIA_GLOBAL_CAPABILITIES", REG_MMIO, 0x03d3, 2, &mmAZALIA_GLOBAL_CAPABILITIES[0], sizeof(mmAZALIA_GLOBAL_CAPABILITIES)/sizeof(mmAZALIA_GLOBAL_CAPABILITIES[0]), 0, 0 }, + { "mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY", REG_MMIO, 0x03d4, 2, &mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY[0], sizeof(mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY)/sizeof(mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY[0]), 0, 0 }, + { "mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL", REG_MMIO, 0x03d5, 2, &mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL[0], sizeof(mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL)/sizeof(mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL[0]), 0, 0 }, + { "mmAZALIA_INPUT_PAYLOAD_CAPABILITY", REG_MMIO, 0x03d6, 2, &mmAZALIA_INPUT_PAYLOAD_CAPABILITY[0], sizeof(mmAZALIA_INPUT_PAYLOAD_CAPABILITY)/sizeof(mmAZALIA_INPUT_PAYLOAD_CAPABILITY[0]), 0, 0 }, + { "mmAZALIA_INPUT_CRC0_CONTROL0", REG_MMIO, 0x03d9, 2, &mmAZALIA_INPUT_CRC0_CONTROL0[0], sizeof(mmAZALIA_INPUT_CRC0_CONTROL0)/sizeof(mmAZALIA_INPUT_CRC0_CONTROL0[0]), 0, 0 }, + { "mmAZALIA_INPUT_CRC0_CONTROL1", REG_MMIO, 0x03da, 2, &mmAZALIA_INPUT_CRC0_CONTROL1[0], sizeof(mmAZALIA_INPUT_CRC0_CONTROL1)/sizeof(mmAZALIA_INPUT_CRC0_CONTROL1[0]), 0, 0 }, + { "mmAZALIA_INPUT_CRC0_CONTROL2", REG_MMIO, 0x03db, 2, &mmAZALIA_INPUT_CRC0_CONTROL2[0], sizeof(mmAZALIA_INPUT_CRC0_CONTROL2)/sizeof(mmAZALIA_INPUT_CRC0_CONTROL2[0]), 0, 0 }, + { "mmAZALIA_INPUT_CRC0_CONTROL3", REG_MMIO, 0x03dc, 2, &mmAZALIA_INPUT_CRC0_CONTROL3[0], sizeof(mmAZALIA_INPUT_CRC0_CONTROL3)/sizeof(mmAZALIA_INPUT_CRC0_CONTROL3[0]), 0, 0 }, + { "mmAZALIA_INPUT_CRC0_RESULT", REG_MMIO, 0x03dd, 2, &mmAZALIA_INPUT_CRC0_RESULT[0], sizeof(mmAZALIA_INPUT_CRC0_RESULT)/sizeof(mmAZALIA_INPUT_CRC0_RESULT[0]), 0, 0 }, + { "mmAZALIA_INPUT_CRC1_CONTROL0", REG_MMIO, 0x03de, 2, &mmAZALIA_INPUT_CRC1_CONTROL0[0], sizeof(mmAZALIA_INPUT_CRC1_CONTROL0)/sizeof(mmAZALIA_INPUT_CRC1_CONTROL0[0]), 0, 0 }, + { "mmAZALIA_INPUT_CRC1_CONTROL1", REG_MMIO, 0x03df, 2, &mmAZALIA_INPUT_CRC1_CONTROL1[0], sizeof(mmAZALIA_INPUT_CRC1_CONTROL1)/sizeof(mmAZALIA_INPUT_CRC1_CONTROL1[0]), 0, 0 }, + { "mmAZALIA_INPUT_CRC1_CONTROL2", REG_MMIO, 0x03e0, 2, &mmAZALIA_INPUT_CRC1_CONTROL2[0], sizeof(mmAZALIA_INPUT_CRC1_CONTROL2)/sizeof(mmAZALIA_INPUT_CRC1_CONTROL2[0]), 0, 0 }, + { "mmAZALIA_INPUT_CRC1_CONTROL3", REG_MMIO, 0x03e1, 2, &mmAZALIA_INPUT_CRC1_CONTROL3[0], sizeof(mmAZALIA_INPUT_CRC1_CONTROL3)/sizeof(mmAZALIA_INPUT_CRC1_CONTROL3[0]), 0, 0 }, + { "mmAZALIA_INPUT_CRC1_RESULT", REG_MMIO, 0x03e2, 2, &mmAZALIA_INPUT_CRC1_RESULT[0], sizeof(mmAZALIA_INPUT_CRC1_RESULT)/sizeof(mmAZALIA_INPUT_CRC1_RESULT[0]), 0, 0 }, + { "mmAZALIA_CRC0_CONTROL0", REG_MMIO, 0x03e3, 2, &mmAZALIA_CRC0_CONTROL0[0], sizeof(mmAZALIA_CRC0_CONTROL0)/sizeof(mmAZALIA_CRC0_CONTROL0[0]), 0, 0 }, + { "mmAZALIA_CRC0_CONTROL1", REG_MMIO, 0x03e4, 2, &mmAZALIA_CRC0_CONTROL1[0], sizeof(mmAZALIA_CRC0_CONTROL1)/sizeof(mmAZALIA_CRC0_CONTROL1[0]), 0, 0 }, + { "mmAZALIA_CRC0_CONTROL2", REG_MMIO, 0x03e5, 2, &mmAZALIA_CRC0_CONTROL2[0], sizeof(mmAZALIA_CRC0_CONTROL2)/sizeof(mmAZALIA_CRC0_CONTROL2[0]), 0, 0 }, + { "mmAZALIA_CRC0_CONTROL3", REG_MMIO, 0x03e6, 2, &mmAZALIA_CRC0_CONTROL3[0], sizeof(mmAZALIA_CRC0_CONTROL3)/sizeof(mmAZALIA_CRC0_CONTROL3[0]), 0, 0 }, + { "mmAZALIA_CRC0_RESULT", REG_MMIO, 0x03e7, 2, &mmAZALIA_CRC0_RESULT[0], sizeof(mmAZALIA_CRC0_RESULT)/sizeof(mmAZALIA_CRC0_RESULT[0]), 0, 0 }, + { "mmAZALIA_CRC1_CONTROL0", REG_MMIO, 0x03e8, 2, &mmAZALIA_CRC1_CONTROL0[0], sizeof(mmAZALIA_CRC1_CONTROL0)/sizeof(mmAZALIA_CRC1_CONTROL0[0]), 0, 0 }, + { "mmAZALIA_CRC1_CONTROL1", REG_MMIO, 0x03e9, 2, &mmAZALIA_CRC1_CONTROL1[0], sizeof(mmAZALIA_CRC1_CONTROL1)/sizeof(mmAZALIA_CRC1_CONTROL1[0]), 0, 0 }, + { "mmAZALIA_CRC1_CONTROL2", REG_MMIO, 0x03ea, 2, &mmAZALIA_CRC1_CONTROL2[0], sizeof(mmAZALIA_CRC1_CONTROL2)/sizeof(mmAZALIA_CRC1_CONTROL2[0]), 0, 0 }, + { "mmAZALIA_CRC1_CONTROL3", REG_MMIO, 0x03eb, 2, &mmAZALIA_CRC1_CONTROL3[0], sizeof(mmAZALIA_CRC1_CONTROL3)/sizeof(mmAZALIA_CRC1_CONTROL3[0]), 0, 0 }, + { "mmAZALIA_CRC1_RESULT", REG_MMIO, 0x03ec, 2, &mmAZALIA_CRC1_RESULT[0], sizeof(mmAZALIA_CRC1_RESULT)/sizeof(mmAZALIA_CRC1_RESULT[0]), 0, 0 }, + { "mmAZALIA_MEM_PWR_CTRL", REG_MMIO, 0x03ee, 2, &mmAZALIA_MEM_PWR_CTRL[0], sizeof(mmAZALIA_MEM_PWR_CTRL)/sizeof(mmAZALIA_MEM_PWR_CTRL[0]), 0, 0 }, + { "mmAZALIA_MEM_PWR_STATUS", REG_MMIO, 0x03ef, 2, &mmAZALIA_MEM_PWR_STATUS[0], sizeof(mmAZALIA_MEM_PWR_STATUS)/sizeof(mmAZALIA_MEM_PWR_STATUS[0]), 0, 0 }, + { "mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID", REG_MMIO, 0x0406, 2, &mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID[0], sizeof(mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID)/sizeof(mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID[0]), 0, 0 }, + { "mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID", REG_MMIO, 0x0407, 2, &mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID[0], sizeof(mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID)/sizeof(mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID[0]), 0, 0 }, + { "mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL", REG_MMIO, 0x0408, 2, &mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL[0], sizeof(mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL)/sizeof(mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL[0]), 0, 0 }, + { "mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL", REG_MMIO, 0x0409, 2, &mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL[0], sizeof(mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL)/sizeof(mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL[0]), 0, 0 }, + { "mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE", REG_MMIO, 0x040a, 2, &mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE[0], sizeof(mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE)/sizeof(mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE[0]), 0, 0 }, + { "mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES", REG_MMIO, 0x040b, 2, &mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES[0], sizeof(mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES)/sizeof(mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES[0]), 0, 0 }, + { "mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS", REG_MMIO, 0x040c, 2, &mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS[0], sizeof(mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS)/sizeof(mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS[0]), 0, 0 }, + { "mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES", REG_MMIO, 0x040d, 2, &mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES[0], sizeof(mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES)/sizeof(mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES[0]), 0, 0 }, + { "mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE", REG_MMIO, 0x040e, 2, &mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE[0], sizeof(mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE)/sizeof(mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE[0]), 0, 0 }, + { "mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET", REG_MMIO, 0x040f, 2, &mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET[0], sizeof(mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET)/sizeof(mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET[0]), 0, 0 }, + { "mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID", REG_MMIO, 0x0410, 2, &mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID[0], sizeof(mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID)/sizeof(mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID[0]), 0, 0 }, + { "mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION", REG_MMIO, 0x0411, 2, &mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION[0], sizeof(mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION)/sizeof(mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION[0]), 0, 0 }, + { "mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY", REG_MMIO, 0x0412, 2, &mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY[0], sizeof(mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY)/sizeof(mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY[0]), 0, 0 }, + { "mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY", REG_MMIO, 0x0413, 2, &mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY[0], sizeof(mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY)/sizeof(mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY[0]), 0, 0 }, + { "mmAZALIA_F0_GTC_GROUP_OFFSET0", REG_MMIO, 0x0415, 2, &mmAZALIA_F0_GTC_GROUP_OFFSET0[0], sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET0)/sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET0[0]), 0, 0 }, + { "mmAZALIA_F0_GTC_GROUP_OFFSET1", REG_MMIO, 0x0416, 2, &mmAZALIA_F0_GTC_GROUP_OFFSET1[0], sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET1)/sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET1[0]), 0, 0 }, + { "mmAZALIA_F0_GTC_GROUP_OFFSET2", REG_MMIO, 0x0417, 2, &mmAZALIA_F0_GTC_GROUP_OFFSET2[0], sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET2)/sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET2[0]), 0, 0 }, + { "mmAZALIA_F0_GTC_GROUP_OFFSET3", REG_MMIO, 0x0418, 2, &mmAZALIA_F0_GTC_GROUP_OFFSET3[0], sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET3)/sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET3[0]), 0, 0 }, + { "mmAZALIA_F0_GTC_GROUP_OFFSET4", REG_MMIO, 0x0419, 2, &mmAZALIA_F0_GTC_GROUP_OFFSET4[0], sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET4)/sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET4[0]), 0, 0 }, + { "mmAZALIA_F0_GTC_GROUP_OFFSET5", REG_MMIO, 0x041a, 2, &mmAZALIA_F0_GTC_GROUP_OFFSET5[0], sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET5)/sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET5[0]), 0, 0 }, + { "mmAZALIA_F0_GTC_GROUP_OFFSET6", REG_MMIO, 0x041b, 2, &mmAZALIA_F0_GTC_GROUP_OFFSET6[0], sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET6)/sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET6[0]), 0, 0 }, + { "mmREG_DC_AUDIO_PORT_CONNECTIVITY", REG_MMIO, 0x041c, 2, &mmREG_DC_AUDIO_PORT_CONNECTIVITY[0], sizeof(mmREG_DC_AUDIO_PORT_CONNECTIVITY)/sizeof(mmREG_DC_AUDIO_PORT_CONNECTIVITY[0]), 0, 0 }, + { "mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY", REG_MMIO, 0x041d, 2, &mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY[0], sizeof(mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY)/sizeof(mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY[0]), 0, 0 }, + { "mmAZF0STREAM8_AZALIA_STREAM_INDEX", REG_MMIO, 0x0426, 2, &mmAZF0STREAM8_AZALIA_STREAM_INDEX[0], sizeof(mmAZF0STREAM8_AZALIA_STREAM_INDEX)/sizeof(mmAZF0STREAM8_AZALIA_STREAM_INDEX[0]), 0, 0 }, + { "mmAZF0STREAM8_AZALIA_STREAM_DATA", REG_MMIO, 0x0427, 2, &mmAZF0STREAM8_AZALIA_STREAM_DATA[0], sizeof(mmAZF0STREAM8_AZALIA_STREAM_DATA)/sizeof(mmAZF0STREAM8_AZALIA_STREAM_DATA[0]), 0, 0 }, + { "mmAZF0STREAM9_AZALIA_STREAM_INDEX", REG_MMIO, 0x0428, 2, &mmAZF0STREAM9_AZALIA_STREAM_INDEX[0], sizeof(mmAZF0STREAM9_AZALIA_STREAM_INDEX)/sizeof(mmAZF0STREAM9_AZALIA_STREAM_INDEX[0]), 0, 0 }, + { "mmAZF0STREAM9_AZALIA_STREAM_DATA", REG_MMIO, 0x0429, 2, &mmAZF0STREAM9_AZALIA_STREAM_DATA[0], sizeof(mmAZF0STREAM9_AZALIA_STREAM_DATA)/sizeof(mmAZF0STREAM9_AZALIA_STREAM_DATA[0]), 0, 0 }, + { "mmAZF0STREAM10_AZALIA_STREAM_INDEX", REG_MMIO, 0x042a, 2, &mmAZF0STREAM10_AZALIA_STREAM_INDEX[0], sizeof(mmAZF0STREAM10_AZALIA_STREAM_INDEX)/sizeof(mmAZF0STREAM10_AZALIA_STREAM_INDEX[0]), 0, 0 }, + { "mmAZF0STREAM10_AZALIA_STREAM_DATA", REG_MMIO, 0x042b, 2, &mmAZF0STREAM10_AZALIA_STREAM_DATA[0], sizeof(mmAZF0STREAM10_AZALIA_STREAM_DATA)/sizeof(mmAZF0STREAM10_AZALIA_STREAM_DATA[0]), 0, 0 }, + { "mmAZF0STREAM11_AZALIA_STREAM_INDEX", REG_MMIO, 0x042c, 2, &mmAZF0STREAM11_AZALIA_STREAM_INDEX[0], sizeof(mmAZF0STREAM11_AZALIA_STREAM_INDEX)/sizeof(mmAZF0STREAM11_AZALIA_STREAM_INDEX[0]), 0, 0 }, + { "mmAZF0STREAM11_AZALIA_STREAM_DATA", REG_MMIO, 0x042d, 2, &mmAZF0STREAM11_AZALIA_STREAM_DATA[0], sizeof(mmAZF0STREAM11_AZALIA_STREAM_DATA)/sizeof(mmAZF0STREAM11_AZALIA_STREAM_DATA[0]), 0, 0 }, + { "mmAZF0STREAM12_AZALIA_STREAM_INDEX", REG_MMIO, 0x042e, 2, &mmAZF0STREAM12_AZALIA_STREAM_INDEX[0], sizeof(mmAZF0STREAM12_AZALIA_STREAM_INDEX)/sizeof(mmAZF0STREAM12_AZALIA_STREAM_INDEX[0]), 0, 0 }, + { "mmAZF0STREAM12_AZALIA_STREAM_DATA", REG_MMIO, 0x042f, 2, &mmAZF0STREAM12_AZALIA_STREAM_DATA[0], sizeof(mmAZF0STREAM12_AZALIA_STREAM_DATA)/sizeof(mmAZF0STREAM12_AZALIA_STREAM_DATA[0]), 0, 0 }, + { "mmAZF0STREAM13_AZALIA_STREAM_INDEX", REG_MMIO, 0x0430, 2, &mmAZF0STREAM13_AZALIA_STREAM_INDEX[0], sizeof(mmAZF0STREAM13_AZALIA_STREAM_INDEX)/sizeof(mmAZF0STREAM13_AZALIA_STREAM_INDEX[0]), 0, 0 }, + { "mmAZF0STREAM13_AZALIA_STREAM_DATA", REG_MMIO, 0x0431, 2, &mmAZF0STREAM13_AZALIA_STREAM_DATA[0], sizeof(mmAZF0STREAM13_AZALIA_STREAM_DATA)/sizeof(mmAZF0STREAM13_AZALIA_STREAM_DATA[0]), 0, 0 }, + { "mmAZF0STREAM14_AZALIA_STREAM_INDEX", REG_MMIO, 0x0432, 2, &mmAZF0STREAM14_AZALIA_STREAM_INDEX[0], sizeof(mmAZF0STREAM14_AZALIA_STREAM_INDEX)/sizeof(mmAZF0STREAM14_AZALIA_STREAM_INDEX[0]), 0, 0 }, + { "mmAZF0STREAM14_AZALIA_STREAM_DATA", REG_MMIO, 0x0433, 2, &mmAZF0STREAM14_AZALIA_STREAM_DATA[0], sizeof(mmAZF0STREAM14_AZALIA_STREAM_DATA)/sizeof(mmAZF0STREAM14_AZALIA_STREAM_DATA[0]), 0, 0 }, + { "mmAZF0STREAM15_AZALIA_STREAM_INDEX", REG_MMIO, 0x0434, 2, &mmAZF0STREAM15_AZALIA_STREAM_INDEX[0], sizeof(mmAZF0STREAM15_AZALIA_STREAM_INDEX)/sizeof(mmAZF0STREAM15_AZALIA_STREAM_INDEX[0]), 0, 0 }, + { "mmAZF0STREAM15_AZALIA_STREAM_DATA", REG_MMIO, 0x0435, 2, &mmAZF0STREAM15_AZALIA_STREAM_DATA[0], sizeof(mmAZF0STREAM15_AZALIA_STREAM_DATA)/sizeof(mmAZF0STREAM15_AZALIA_STREAM_DATA[0]), 0, 0 }, + { "mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX", REG_MMIO, 0x043a, 2, &mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX[0], sizeof(mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX)/sizeof(mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX[0]), 0, 0 }, + { "mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA", REG_MMIO, 0x043b, 2, &mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA[0], sizeof(mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA)/sizeof(mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA[0]), 0, 0 }, + { "mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX", REG_MMIO, 0x043e, 2, &mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX[0], sizeof(mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX)/sizeof(mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX[0]), 0, 0 }, + { "mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA", REG_MMIO, 0x043f, 2, &mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA[0], sizeof(mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA)/sizeof(mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA[0]), 0, 0 }, + { "mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX", REG_MMIO, 0x0442, 2, &mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX[0], sizeof(mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX)/sizeof(mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX[0]), 0, 0 }, + { "mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA", REG_MMIO, 0x0443, 2, &mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA[0], sizeof(mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA)/sizeof(mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA[0]), 0, 0 }, + { "mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX", REG_MMIO, 0x0446, 2, &mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX[0], sizeof(mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX)/sizeof(mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX[0]), 0, 0 }, + { "mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA", REG_MMIO, 0x0447, 2, &mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA[0], sizeof(mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA)/sizeof(mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA[0]), 0, 0 }, + { "mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX", REG_MMIO, 0x044a, 2, &mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX[0], sizeof(mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX)/sizeof(mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX[0]), 0, 0 }, + { "mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA", REG_MMIO, 0x044b, 2, &mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA[0], sizeof(mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA)/sizeof(mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA[0]), 0, 0 }, + { "mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX", REG_MMIO, 0x044e, 2, &mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX[0], sizeof(mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX)/sizeof(mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX[0]), 0, 0 }, + { "mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA", REG_MMIO, 0x044f, 2, &mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA[0], sizeof(mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA)/sizeof(mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA[0]), 0, 0 }, + { "mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX", REG_MMIO, 0x0452, 2, &mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX[0], sizeof(mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX)/sizeof(mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX[0]), 0, 0 }, + { "mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA", REG_MMIO, 0x0453, 2, &mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA[0], sizeof(mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA)/sizeof(mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA[0]), 0, 0 }, + { "mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX", REG_MMIO, 0x0456, 2, &mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX[0], sizeof(mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX)/sizeof(mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX[0]), 0, 0 }, + { "mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA", REG_MMIO, 0x0457, 2, &mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA[0], sizeof(mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA)/sizeof(mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA[0]), 0, 0 }, + { "mmDCHUBBUB_SDPIF_CFG0", REG_MMIO, 0x048f, 2, &mmDCHUBBUB_SDPIF_CFG0[0], sizeof(mmDCHUBBUB_SDPIF_CFG0)/sizeof(mmDCHUBBUB_SDPIF_CFG0[0]), 0, 0 }, + { "mmDCHUBBUB_SDPIF_CFG1", REG_MMIO, 0x0490, 2, &mmDCHUBBUB_SDPIF_CFG1[0], sizeof(mmDCHUBBUB_SDPIF_CFG1)/sizeof(mmDCHUBBUB_SDPIF_CFG1[0]), 0, 0 }, + { "mmDCHUBBUB_FORCE_IO_STATUS_0", REG_MMIO, 0x0491, 2, &mmDCHUBBUB_FORCE_IO_STATUS_0[0], sizeof(mmDCHUBBUB_FORCE_IO_STATUS_0)/sizeof(mmDCHUBBUB_FORCE_IO_STATUS_0[0]), 0, 0 }, + { "mmDCHUBBUB_FORCE_IO_STATUS_1", REG_MMIO, 0x0492, 2, &mmDCHUBBUB_FORCE_IO_STATUS_1[0], sizeof(mmDCHUBBUB_FORCE_IO_STATUS_1)/sizeof(mmDCHUBBUB_FORCE_IO_STATUS_1[0]), 0, 0 }, + { "mmDCHUBBUB_SDPIF_FB_BASE", REG_MMIO, 0x0493, 2, &mmDCHUBBUB_SDPIF_FB_BASE[0], sizeof(mmDCHUBBUB_SDPIF_FB_BASE)/sizeof(mmDCHUBBUB_SDPIF_FB_BASE[0]), 0, 0 }, + { "mmDCHUBBUB_SDPIF_FB_TOP", REG_MMIO, 0x0494, 2, &mmDCHUBBUB_SDPIF_FB_TOP[0], sizeof(mmDCHUBBUB_SDPIF_FB_TOP)/sizeof(mmDCHUBBUB_SDPIF_FB_TOP[0]), 0, 0 }, + { "mmDCHUBBUB_SDPIF_FB_OFFSET", REG_MMIO, 0x0495, 2, &mmDCHUBBUB_SDPIF_FB_OFFSET[0], sizeof(mmDCHUBBUB_SDPIF_FB_OFFSET)/sizeof(mmDCHUBBUB_SDPIF_FB_OFFSET[0]), 0, 0 }, + { "mmDCHUBBUB_SDPIF_AGP_BOT", REG_MMIO, 0x0496, 2, &mmDCHUBBUB_SDPIF_AGP_BOT[0], sizeof(mmDCHUBBUB_SDPIF_AGP_BOT)/sizeof(mmDCHUBBUB_SDPIF_AGP_BOT[0]), 0, 0 }, + { "mmDCHUBBUB_SDPIF_AGP_TOP", REG_MMIO, 0x0497, 2, &mmDCHUBBUB_SDPIF_AGP_TOP[0], sizeof(mmDCHUBBUB_SDPIF_AGP_TOP)/sizeof(mmDCHUBBUB_SDPIF_AGP_TOP[0]), 0, 0 }, + { "mmDCHUBBUB_SDPIF_AGP_BASE", REG_MMIO, 0x0498, 2, &mmDCHUBBUB_SDPIF_AGP_BASE[0], sizeof(mmDCHUBBUB_SDPIF_AGP_BASE)/sizeof(mmDCHUBBUB_SDPIF_AGP_BASE[0]), 0, 0 }, + { "mmDCHUBBUB_SDPIF_APER_BASE", REG_MMIO, 0x0499, 2, &mmDCHUBBUB_SDPIF_APER_BASE[0], sizeof(mmDCHUBBUB_SDPIF_APER_BASE)/sizeof(mmDCHUBBUB_SDPIF_APER_BASE[0]), 0, 0 }, + { "mmDCHUBBUB_SDPIF_APER_TOP", REG_MMIO, 0x049a, 2, &mmDCHUBBUB_SDPIF_APER_TOP[0], sizeof(mmDCHUBBUB_SDPIF_APER_TOP)/sizeof(mmDCHUBBUB_SDPIF_APER_TOP[0]), 0, 0 }, + { "mmDCHUBBUB_SDPIF_APER_DEF_0", REG_MMIO, 0x049b, 2, &mmDCHUBBUB_SDPIF_APER_DEF_0[0], sizeof(mmDCHUBBUB_SDPIF_APER_DEF_0)/sizeof(mmDCHUBBUB_SDPIF_APER_DEF_0[0]), 0, 0 }, + { "mmDCHUBBUB_SDPIF_APER_DEF_1", REG_MMIO, 0x049c, 2, &mmDCHUBBUB_SDPIF_APER_DEF_1[0], sizeof(mmDCHUBBUB_SDPIF_APER_DEF_1)/sizeof(mmDCHUBBUB_SDPIF_APER_DEF_1[0]), 0, 0 }, + { "mmDCHUBBUB_SDPIF_MMIO_CNTRL_0", REG_MMIO, 0x049d, 2, &mmDCHUBBUB_SDPIF_MMIO_CNTRL_0[0], sizeof(mmDCHUBBUB_SDPIF_MMIO_CNTRL_0)/sizeof(mmDCHUBBUB_SDPIF_MMIO_CNTRL_0[0]), 0, 0 }, + { "mmDCHUBBUB_SDPIF_MMIO_CNTRL_1", REG_MMIO, 0x049e, 2, &mmDCHUBBUB_SDPIF_MMIO_CNTRL_1[0], sizeof(mmDCHUBBUB_SDPIF_MMIO_CNTRL_1)/sizeof(mmDCHUBBUB_SDPIF_MMIO_CNTRL_1[0]), 0, 0 }, + { "mmDCHUBBUB_SDPIF_MMIO_CNTRL_W", REG_MMIO, 0x049f, 2, &mmDCHUBBUB_SDPIF_MMIO_CNTRL_W[0], sizeof(mmDCHUBBUB_SDPIF_MMIO_CNTRL_W)/sizeof(mmDCHUBBUB_SDPIF_MMIO_CNTRL_W[0]), 0, 0 }, + { "mmDCHUBBUB_SDPIF_MARC_BASE_LO_0", REG_MMIO, 0x04a0, 2, &mmDCHUBBUB_SDPIF_MARC_BASE_LO_0[0], sizeof(mmDCHUBBUB_SDPIF_MARC_BASE_LO_0)/sizeof(mmDCHUBBUB_SDPIF_MARC_BASE_LO_0[0]), 0, 0 }, + { "mmDCHUBBUB_SDPIF_MARC_BASE_HI_0", REG_MMIO, 0x04a1, 2, &mmDCHUBBUB_SDPIF_MARC_BASE_HI_0[0], sizeof(mmDCHUBBUB_SDPIF_MARC_BASE_HI_0)/sizeof(mmDCHUBBUB_SDPIF_MARC_BASE_HI_0[0]), 0, 0 }, + { "mmDCHUBBUB_SDPIF_MARC_RELOC_LO_0", REG_MMIO, 0x04a2, 2, &mmDCHUBBUB_SDPIF_MARC_RELOC_LO_0[0], sizeof(mmDCHUBBUB_SDPIF_MARC_RELOC_LO_0)/sizeof(mmDCHUBBUB_SDPIF_MARC_RELOC_LO_0[0]), 0, 0 }, + { "mmDCHUBBUB_SDPIF_MARC_RELOC_HI_0", REG_MMIO, 0x04a3, 2, &mmDCHUBBUB_SDPIF_MARC_RELOC_HI_0[0], sizeof(mmDCHUBBUB_SDPIF_MARC_RELOC_HI_0)/sizeof(mmDCHUBBUB_SDPIF_MARC_RELOC_HI_0[0]), 0, 0 }, + { "mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_0", REG_MMIO, 0x04a4, 2, &mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_0[0], sizeof(mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_0)/sizeof(mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_0[0]), 0, 0 }, + { "mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_0", REG_MMIO, 0x04a5, 2, &mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_0[0], sizeof(mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_0)/sizeof(mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_0[0]), 0, 0 }, + { "mmDCHUBBUB_SDPIF_MARC_BASE_LO_1", REG_MMIO, 0x04a6, 2, &mmDCHUBBUB_SDPIF_MARC_BASE_LO_1[0], sizeof(mmDCHUBBUB_SDPIF_MARC_BASE_LO_1)/sizeof(mmDCHUBBUB_SDPIF_MARC_BASE_LO_1[0]), 0, 0 }, + { "mmDCHUBBUB_SDPIF_MARC_BASE_HI_1", REG_MMIO, 0x04a7, 2, &mmDCHUBBUB_SDPIF_MARC_BASE_HI_1[0], sizeof(mmDCHUBBUB_SDPIF_MARC_BASE_HI_1)/sizeof(mmDCHUBBUB_SDPIF_MARC_BASE_HI_1[0]), 0, 0 }, + { "mmDCHUBBUB_SDPIF_MARC_RELOC_LO_1", REG_MMIO, 0x04a8, 2, &mmDCHUBBUB_SDPIF_MARC_RELOC_LO_1[0], sizeof(mmDCHUBBUB_SDPIF_MARC_RELOC_LO_1)/sizeof(mmDCHUBBUB_SDPIF_MARC_RELOC_LO_1[0]), 0, 0 }, + { "mmDCHUBBUB_SDPIF_MARC_RELOC_HI_1", REG_MMIO, 0x04a9, 2, &mmDCHUBBUB_SDPIF_MARC_RELOC_HI_1[0], sizeof(mmDCHUBBUB_SDPIF_MARC_RELOC_HI_1)/sizeof(mmDCHUBBUB_SDPIF_MARC_RELOC_HI_1[0]), 0, 0 }, + { "mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_1", REG_MMIO, 0x04aa, 2, &mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_1[0], sizeof(mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_1)/sizeof(mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_1[0]), 0, 0 }, + { "mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_1", REG_MMIO, 0x04ab, 2, &mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_1[0], sizeof(mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_1)/sizeof(mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_1[0]), 0, 0 }, + { "mmDCHUBBUB_SDPIF_MARC_BASE_LO_2", REG_MMIO, 0x04ac, 2, &mmDCHUBBUB_SDPIF_MARC_BASE_LO_2[0], sizeof(mmDCHUBBUB_SDPIF_MARC_BASE_LO_2)/sizeof(mmDCHUBBUB_SDPIF_MARC_BASE_LO_2[0]), 0, 0 }, + { "mmDCHUBBUB_SDPIF_MARC_BASE_HI_2", REG_MMIO, 0x04ad, 2, &mmDCHUBBUB_SDPIF_MARC_BASE_HI_2[0], sizeof(mmDCHUBBUB_SDPIF_MARC_BASE_HI_2)/sizeof(mmDCHUBBUB_SDPIF_MARC_BASE_HI_2[0]), 0, 0 }, + { "mmDCHUBBUB_SDPIF_MARC_RELOC_LO_2", REG_MMIO, 0x04ae, 2, &mmDCHUBBUB_SDPIF_MARC_RELOC_LO_2[0], sizeof(mmDCHUBBUB_SDPIF_MARC_RELOC_LO_2)/sizeof(mmDCHUBBUB_SDPIF_MARC_RELOC_LO_2[0]), 0, 0 }, + { "mmDCHUBBUB_SDPIF_MARC_RELOC_HI_2", REG_MMIO, 0x04af, 2, &mmDCHUBBUB_SDPIF_MARC_RELOC_HI_2[0], sizeof(mmDCHUBBUB_SDPIF_MARC_RELOC_HI_2)/sizeof(mmDCHUBBUB_SDPIF_MARC_RELOC_HI_2[0]), 0, 0 }, + { "mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_2", REG_MMIO, 0x04b0, 2, &mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_2[0], sizeof(mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_2)/sizeof(mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_2[0]), 0, 0 }, + { "mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_2", REG_MMIO, 0x04b1, 2, &mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_2[0], sizeof(mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_2)/sizeof(mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_2[0]), 0, 0 }, + { "mmDCHUBBUB_SDPIF_MARC_BASE_LO_3", REG_MMIO, 0x04b2, 2, &mmDCHUBBUB_SDPIF_MARC_BASE_LO_3[0], sizeof(mmDCHUBBUB_SDPIF_MARC_BASE_LO_3)/sizeof(mmDCHUBBUB_SDPIF_MARC_BASE_LO_3[0]), 0, 0 }, + { "mmDCHUBBUB_SDPIF_MARC_BASE_HI_3", REG_MMIO, 0x04b3, 2, &mmDCHUBBUB_SDPIF_MARC_BASE_HI_3[0], sizeof(mmDCHUBBUB_SDPIF_MARC_BASE_HI_3)/sizeof(mmDCHUBBUB_SDPIF_MARC_BASE_HI_3[0]), 0, 0 }, + { "mmDCHUBBUB_SDPIF_MARC_RELOC_LO_3", REG_MMIO, 0x04b4, 2, &mmDCHUBBUB_SDPIF_MARC_RELOC_LO_3[0], sizeof(mmDCHUBBUB_SDPIF_MARC_RELOC_LO_3)/sizeof(mmDCHUBBUB_SDPIF_MARC_RELOC_LO_3[0]), 0, 0 }, + { "mmDCHUBBUB_SDPIF_MARC_RELOC_HI_3", REG_MMIO, 0x04b5, 2, &mmDCHUBBUB_SDPIF_MARC_RELOC_HI_3[0], sizeof(mmDCHUBBUB_SDPIF_MARC_RELOC_HI_3)/sizeof(mmDCHUBBUB_SDPIF_MARC_RELOC_HI_3[0]), 0, 0 }, + { "mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_3", REG_MMIO, 0x04b6, 2, &mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_3[0], sizeof(mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_3)/sizeof(mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_3[0]), 0, 0 }, + { "mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_3", REG_MMIO, 0x04b7, 2, &mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_3[0], sizeof(mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_3)/sizeof(mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_3[0]), 0, 0 }, + { "mmDCHUBBUB_SDPIF_PIPE_SEC_LVL", REG_MMIO, 0x04b8, 2, &mmDCHUBBUB_SDPIF_PIPE_SEC_LVL[0], sizeof(mmDCHUBBUB_SDPIF_PIPE_SEC_LVL)/sizeof(mmDCHUBBUB_SDPIF_PIPE_SEC_LVL[0]), 0, 0 }, + { "mmDCHUBBUB_SDPIF_MEM_PWR_CTRL", REG_MMIO, 0x04b9, 2, &mmDCHUBBUB_SDPIF_MEM_PWR_CTRL[0], sizeof(mmDCHUBBUB_SDPIF_MEM_PWR_CTRL)/sizeof(mmDCHUBBUB_SDPIF_MEM_PWR_CTRL[0]), 0, 0 }, + { "mmDCHUBBUB_SDPIF_MEM_PWR_STATUS", REG_MMIO, 0x04ba, 2, &mmDCHUBBUB_SDPIF_MEM_PWR_STATUS[0], sizeof(mmDCHUBBUB_SDPIF_MEM_PWR_STATUS)/sizeof(mmDCHUBBUB_SDPIF_MEM_PWR_STATUS[0]), 0, 0 }, + { "mmDCHUBBUB_RET_PATH_DCC_CFG", REG_MMIO, 0x04cf, 2, &mmDCHUBBUB_RET_PATH_DCC_CFG[0], sizeof(mmDCHUBBUB_RET_PATH_DCC_CFG)/sizeof(mmDCHUBBUB_RET_PATH_DCC_CFG[0]), 0, 0 }, + { "mmDCHUBBUB_RET_PATH_DCC_CFG0_0", REG_MMIO, 0x04d0, 2, &mmDCHUBBUB_RET_PATH_DCC_CFG0_0[0], sizeof(mmDCHUBBUB_RET_PATH_DCC_CFG0_0)/sizeof(mmDCHUBBUB_RET_PATH_DCC_CFG0_0[0]), 0, 0 }, + { "mmDCHUBBUB_RET_PATH_DCC_CFG0_1", REG_MMIO, 0x04d1, 2, &mmDCHUBBUB_RET_PATH_DCC_CFG0_1[0], sizeof(mmDCHUBBUB_RET_PATH_DCC_CFG0_1)/sizeof(mmDCHUBBUB_RET_PATH_DCC_CFG0_1[0]), 0, 0 }, + { "mmDCHUBBUB_RET_PATH_DCC_CFG1_0", REG_MMIO, 0x04d2, 2, &mmDCHUBBUB_RET_PATH_DCC_CFG1_0[0], sizeof(mmDCHUBBUB_RET_PATH_DCC_CFG1_0)/sizeof(mmDCHUBBUB_RET_PATH_DCC_CFG1_0[0]), 0, 0 }, + { "mmDCHUBBUB_RET_PATH_DCC_CFG1_1", REG_MMIO, 0x04d3, 2, &mmDCHUBBUB_RET_PATH_DCC_CFG1_1[0], sizeof(mmDCHUBBUB_RET_PATH_DCC_CFG1_1)/sizeof(mmDCHUBBUB_RET_PATH_DCC_CFG1_1[0]), 0, 0 }, + { "mmDCHUBBUB_RET_PATH_DCC_CFG2_0", REG_MMIO, 0x04d4, 2, &mmDCHUBBUB_RET_PATH_DCC_CFG2_0[0], sizeof(mmDCHUBBUB_RET_PATH_DCC_CFG2_0)/sizeof(mmDCHUBBUB_RET_PATH_DCC_CFG2_0[0]), 0, 0 }, + { "mmDCHUBBUB_RET_PATH_DCC_CFG2_1", REG_MMIO, 0x04d5, 2, &mmDCHUBBUB_RET_PATH_DCC_CFG2_1[0], sizeof(mmDCHUBBUB_RET_PATH_DCC_CFG2_1)/sizeof(mmDCHUBBUB_RET_PATH_DCC_CFG2_1[0]), 0, 0 }, + { "mmDCHUBBUB_RET_PATH_DCC_CFG3_0", REG_MMIO, 0x04d6, 2, &mmDCHUBBUB_RET_PATH_DCC_CFG3_0[0], sizeof(mmDCHUBBUB_RET_PATH_DCC_CFG3_0)/sizeof(mmDCHUBBUB_RET_PATH_DCC_CFG3_0[0]), 0, 0 }, + { "mmDCHUBBUB_RET_PATH_DCC_CFG3_1", REG_MMIO, 0x04d7, 2, &mmDCHUBBUB_RET_PATH_DCC_CFG3_1[0], sizeof(mmDCHUBBUB_RET_PATH_DCC_CFG3_1)/sizeof(mmDCHUBBUB_RET_PATH_DCC_CFG3_1[0]), 0, 0 }, + { "mmDCHUBBUB_RET_PATH_DCC_CFG4_0", REG_MMIO, 0x04d8, 2, &mmDCHUBBUB_RET_PATH_DCC_CFG4_0[0], sizeof(mmDCHUBBUB_RET_PATH_DCC_CFG4_0)/sizeof(mmDCHUBBUB_RET_PATH_DCC_CFG4_0[0]), 0, 0 }, + { "mmDCHUBBUB_RET_PATH_DCC_CFG4_1", REG_MMIO, 0x04d9, 2, &mmDCHUBBUB_RET_PATH_DCC_CFG4_1[0], sizeof(mmDCHUBBUB_RET_PATH_DCC_CFG4_1)/sizeof(mmDCHUBBUB_RET_PATH_DCC_CFG4_1[0]), 0, 0 }, + { "mmDCHUBBUB_RET_PATH_DCC_CFG5_0", REG_MMIO, 0x04da, 2, &mmDCHUBBUB_RET_PATH_DCC_CFG5_0[0], sizeof(mmDCHUBBUB_RET_PATH_DCC_CFG5_0)/sizeof(mmDCHUBBUB_RET_PATH_DCC_CFG5_0[0]), 0, 0 }, + { "mmDCHUBBUB_RET_PATH_DCC_CFG5_1", REG_MMIO, 0x04db, 2, &mmDCHUBBUB_RET_PATH_DCC_CFG5_1[0], sizeof(mmDCHUBBUB_RET_PATH_DCC_CFG5_1)/sizeof(mmDCHUBBUB_RET_PATH_DCC_CFG5_1[0]), 0, 0 }, + { "mmDCHUBBUB_RET_PATH_DCC_CFG6_0", REG_MMIO, 0x04dc, 2, &mmDCHUBBUB_RET_PATH_DCC_CFG6_0[0], sizeof(mmDCHUBBUB_RET_PATH_DCC_CFG6_0)/sizeof(mmDCHUBBUB_RET_PATH_DCC_CFG6_0[0]), 0, 0 }, + { "mmDCHUBBUB_RET_PATH_DCC_CFG6_1", REG_MMIO, 0x04dd, 2, &mmDCHUBBUB_RET_PATH_DCC_CFG6_1[0], sizeof(mmDCHUBBUB_RET_PATH_DCC_CFG6_1)/sizeof(mmDCHUBBUB_RET_PATH_DCC_CFG6_1[0]), 0, 0 }, + { "mmDCHUBBUB_RET_PATH_DCC_CFG7_0", REG_MMIO, 0x04de, 2, &mmDCHUBBUB_RET_PATH_DCC_CFG7_0[0], sizeof(mmDCHUBBUB_RET_PATH_DCC_CFG7_0)/sizeof(mmDCHUBBUB_RET_PATH_DCC_CFG7_0[0]), 0, 0 }, + { "mmDCHUBBUB_RET_PATH_DCC_CFG7_1", REG_MMIO, 0x04df, 2, &mmDCHUBBUB_RET_PATH_DCC_CFG7_1[0], sizeof(mmDCHUBBUB_RET_PATH_DCC_CFG7_1)/sizeof(mmDCHUBBUB_RET_PATH_DCC_CFG7_1[0]), 0, 0 }, + { "mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL", REG_MMIO, 0x04e0, 2, &mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL[0], sizeof(mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL)/sizeof(mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL[0]), 0, 0 }, + { "mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS", REG_MMIO, 0x04e1, 2, &mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS[0], sizeof(mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS)/sizeof(mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS[0]), 0, 0 }, + { "mmDCHUBBUB_CRC_CTRL", REG_MMIO, 0x04e2, 2, &mmDCHUBBUB_CRC_CTRL[0], sizeof(mmDCHUBBUB_CRC_CTRL)/sizeof(mmDCHUBBUB_CRC_CTRL[0]), 0, 0 }, + { "mmDCHUBBUB_CRC0_VAL_R_G", REG_MMIO, 0x04e3, 2, &mmDCHUBBUB_CRC0_VAL_R_G[0], sizeof(mmDCHUBBUB_CRC0_VAL_R_G)/sizeof(mmDCHUBBUB_CRC0_VAL_R_G[0]), 0, 0 }, + { "mmDCHUBBUB_CRC0_VAL_B_A", REG_MMIO, 0x04e4, 2, &mmDCHUBBUB_CRC0_VAL_B_A[0], sizeof(mmDCHUBBUB_CRC0_VAL_B_A)/sizeof(mmDCHUBBUB_CRC0_VAL_B_A[0]), 0, 0 }, + { "mmDCHUBBUB_CRC1_VAL_R_G", REG_MMIO, 0x04e5, 2, &mmDCHUBBUB_CRC1_VAL_R_G[0], sizeof(mmDCHUBBUB_CRC1_VAL_R_G)/sizeof(mmDCHUBBUB_CRC1_VAL_R_G[0]), 0, 0 }, + { "mmDCHUBBUB_CRC1_VAL_B_A", REG_MMIO, 0x04e6, 2, &mmDCHUBBUB_CRC1_VAL_B_A[0], sizeof(mmDCHUBBUB_CRC1_VAL_B_A)/sizeof(mmDCHUBBUB_CRC1_VAL_B_A[0]), 0, 0 }, + { "mmDCHUBBUB_ARB_DF_REQ_OUTSTAND", REG_MMIO, 0x0505, 2, &mmDCHUBBUB_ARB_DF_REQ_OUTSTAND[0], sizeof(mmDCHUBBUB_ARB_DF_REQ_OUTSTAND)/sizeof(mmDCHUBBUB_ARB_DF_REQ_OUTSTAND[0]), 0, 0 }, + { "mmDCHUBBUB_ARB_SAT_LEVEL", REG_MMIO, 0x0506, 2, &mmDCHUBBUB_ARB_SAT_LEVEL[0], sizeof(mmDCHUBBUB_ARB_SAT_LEVEL)/sizeof(mmDCHUBBUB_ARB_SAT_LEVEL[0]), 0, 0 }, + { "mmDCHUBBUB_ARB_QOS_FORCE", REG_MMIO, 0x0507, 2, &mmDCHUBBUB_ARB_QOS_FORCE[0], sizeof(mmDCHUBBUB_ARB_QOS_FORCE)/sizeof(mmDCHUBBUB_ARB_QOS_FORCE[0]), 0, 0 }, + { "mmDCHUBBUB_ARB_DRAM_STATE_CNTL", REG_MMIO, 0x0508, 2, &mmDCHUBBUB_ARB_DRAM_STATE_CNTL[0], sizeof(mmDCHUBBUB_ARB_DRAM_STATE_CNTL)/sizeof(mmDCHUBBUB_ARB_DRAM_STATE_CNTL[0]), 0, 0 }, + { "mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A", REG_MMIO, 0x0509, 2, &mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A[0], sizeof(mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A)/sizeof(mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A[0]), 0, 0 }, + { "mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A", REG_MMIO, 0x050a, 2, &mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A[0], sizeof(mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A)/sizeof(mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A[0]), 0, 0 }, + { "mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A", REG_MMIO, 0x050b, 2, &mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A[0], sizeof(mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A)/sizeof(mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A[0]), 0, 0 }, + { "mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A", REG_MMIO, 0x050c, 2, &mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A[0], sizeof(mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A)/sizeof(mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A[0]), 0, 0 }, + { "mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A", REG_MMIO, 0x050d, 2, &mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A[0], sizeof(mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A)/sizeof(mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A[0]), 0, 0 }, + { "mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B", REG_MMIO, 0x050e, 2, &mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B[0], sizeof(mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B)/sizeof(mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B[0]), 0, 0 }, + { "mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B", REG_MMIO, 0x050f, 2, &mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B[0], sizeof(mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B)/sizeof(mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B[0]), 0, 0 }, + { "mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B", REG_MMIO, 0x0510, 2, &mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B[0], sizeof(mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B)/sizeof(mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B[0]), 0, 0 }, + { "mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B", REG_MMIO, 0x0511, 2, &mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B[0], sizeof(mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B)/sizeof(mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B[0]), 0, 0 }, + { "mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B", REG_MMIO, 0x0512, 2, &mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B[0], sizeof(mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B)/sizeof(mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B[0]), 0, 0 }, + { "mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C", REG_MMIO, 0x0513, 2, &mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C[0], sizeof(mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C)/sizeof(mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C[0]), 0, 0 }, + { "mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C", REG_MMIO, 0x0514, 2, &mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C[0], sizeof(mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C)/sizeof(mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C[0]), 0, 0 }, + { "mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C", REG_MMIO, 0x0515, 2, &mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C[0], sizeof(mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C)/sizeof(mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C[0]), 0, 0 }, + { "mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C", REG_MMIO, 0x0516, 2, &mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C[0], sizeof(mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C)/sizeof(mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C[0]), 0, 0 }, + { "mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C", REG_MMIO, 0x0517, 2, &mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C[0], sizeof(mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C)/sizeof(mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C[0]), 0, 0 }, + { "mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D", REG_MMIO, 0x0518, 2, &mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D[0], sizeof(mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D)/sizeof(mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D[0]), 0, 0 }, + { "mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D", REG_MMIO, 0x0519, 2, &mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D[0], sizeof(mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D)/sizeof(mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D[0]), 0, 0 }, + { "mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D", REG_MMIO, 0x051a, 2, &mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D[0], sizeof(mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D)/sizeof(mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D[0]), 0, 0 }, + { "mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D", REG_MMIO, 0x051b, 2, &mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D[0], sizeof(mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D)/sizeof(mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D[0]), 0, 0 }, + { "mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D", REG_MMIO, 0x051c, 2, &mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D[0], sizeof(mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D)/sizeof(mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D[0]), 0, 0 }, + { "mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL", REG_MMIO, 0x051d, 2, &mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL[0], sizeof(mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL)/sizeof(mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL[0]), 0, 0 }, + { "mmDCHUBBUB_ARB_TIMEOUT_ENABLE", REG_MMIO, 0x051e, 2, &mmDCHUBBUB_ARB_TIMEOUT_ENABLE[0], sizeof(mmDCHUBBUB_ARB_TIMEOUT_ENABLE)/sizeof(mmDCHUBBUB_ARB_TIMEOUT_ENABLE[0]), 0, 0 }, + { "mmDCHUBBUB_GLOBAL_TIMER_CNTL", REG_MMIO, 0x051f, 2, &mmDCHUBBUB_GLOBAL_TIMER_CNTL[0], sizeof(mmDCHUBBUB_GLOBAL_TIMER_CNTL)/sizeof(mmDCHUBBUB_GLOBAL_TIMER_CNTL[0]), 0, 0 }, + { "mmSURFACE_CHECK0_ADDRESS_LSB", REG_MMIO, 0x0520, 2, &mmSURFACE_CHECK0_ADDRESS_LSB[0], sizeof(mmSURFACE_CHECK0_ADDRESS_LSB)/sizeof(mmSURFACE_CHECK0_ADDRESS_LSB[0]), 0, 0 }, + { "mmSURFACE_CHECK0_ADDRESS_MSB", REG_MMIO, 0x0521, 2, &mmSURFACE_CHECK0_ADDRESS_MSB[0], sizeof(mmSURFACE_CHECK0_ADDRESS_MSB)/sizeof(mmSURFACE_CHECK0_ADDRESS_MSB[0]), 0, 0 }, + { "mmSURFACE_CHECK1_ADDRESS_LSB", REG_MMIO, 0x0522, 2, &mmSURFACE_CHECK1_ADDRESS_LSB[0], sizeof(mmSURFACE_CHECK1_ADDRESS_LSB)/sizeof(mmSURFACE_CHECK1_ADDRESS_LSB[0]), 0, 0 }, + { "mmSURFACE_CHECK1_ADDRESS_MSB", REG_MMIO, 0x0523, 2, &mmSURFACE_CHECK1_ADDRESS_MSB[0], sizeof(mmSURFACE_CHECK1_ADDRESS_MSB)/sizeof(mmSURFACE_CHECK1_ADDRESS_MSB[0]), 0, 0 }, + { "mmSURFACE_CHECK2_ADDRESS_LSB", REG_MMIO, 0x0524, 2, &mmSURFACE_CHECK2_ADDRESS_LSB[0], sizeof(mmSURFACE_CHECK2_ADDRESS_LSB)/sizeof(mmSURFACE_CHECK2_ADDRESS_LSB[0]), 0, 0 }, + { "mmSURFACE_CHECK2_ADDRESS_MSB", REG_MMIO, 0x0525, 2, &mmSURFACE_CHECK2_ADDRESS_MSB[0], sizeof(mmSURFACE_CHECK2_ADDRESS_MSB)/sizeof(mmSURFACE_CHECK2_ADDRESS_MSB[0]), 0, 0 }, + { "mmSURFACE_CHECK3_ADDRESS_LSB", REG_MMIO, 0x0526, 2, &mmSURFACE_CHECK3_ADDRESS_LSB[0], sizeof(mmSURFACE_CHECK3_ADDRESS_LSB)/sizeof(mmSURFACE_CHECK3_ADDRESS_LSB[0]), 0, 0 }, + { "mmSURFACE_CHECK3_ADDRESS_MSB", REG_MMIO, 0x0527, 2, &mmSURFACE_CHECK3_ADDRESS_MSB[0], sizeof(mmSURFACE_CHECK3_ADDRESS_MSB)/sizeof(mmSURFACE_CHECK3_ADDRESS_MSB[0]), 0, 0 }, + { "mmVTG0_CONTROL", REG_MMIO, 0x0528, 2, &mmVTG0_CONTROL[0], sizeof(mmVTG0_CONTROL)/sizeof(mmVTG0_CONTROL[0]), 0, 0 }, + { "mmVTG1_CONTROL", REG_MMIO, 0x0529, 2, &mmVTG1_CONTROL[0], sizeof(mmVTG1_CONTROL)/sizeof(mmVTG1_CONTROL[0]), 0, 0 }, + { "mmVTG2_CONTROL", REG_MMIO, 0x052a, 2, &mmVTG2_CONTROL[0], sizeof(mmVTG2_CONTROL)/sizeof(mmVTG2_CONTROL[0]), 0, 0 }, + { "mmVTG3_CONTROL", REG_MMIO, 0x052b, 2, &mmVTG3_CONTROL[0], sizeof(mmVTG3_CONTROL)/sizeof(mmVTG3_CONTROL[0]), 0, 0 }, + { "mmVTG4_CONTROL", REG_MMIO, 0x052c, 2, &mmVTG4_CONTROL[0], sizeof(mmVTG4_CONTROL)/sizeof(mmVTG4_CONTROL[0]), 0, 0 }, + { "mmVTG5_CONTROL", REG_MMIO, 0x052d, 2, &mmVTG5_CONTROL[0], sizeof(mmVTG5_CONTROL)/sizeof(mmVTG5_CONTROL[0]), 0, 0 }, + { "mmDCHUBBUB_SOFT_RESET", REG_MMIO, 0x052e, 2, &mmDCHUBBUB_SOFT_RESET[0], sizeof(mmDCHUBBUB_SOFT_RESET)/sizeof(mmDCHUBBUB_SOFT_RESET[0]), 0, 0 }, + { "mmDCHUBBUB_CLOCK_CNTL", REG_MMIO, 0x052f, 2, &mmDCHUBBUB_CLOCK_CNTL[0], sizeof(mmDCHUBBUB_CLOCK_CNTL)/sizeof(mmDCHUBBUB_CLOCK_CNTL[0]), 0, 0 }, + { "mmDCFCLK_CNTL", REG_MMIO, 0x0530, 2, &mmDCFCLK_CNTL[0], sizeof(mmDCFCLK_CNTL)/sizeof(mmDCFCLK_CNTL[0]), 0, 0 }, + { "mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL", REG_MMIO, 0x0531, 2, &mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL[0], sizeof(mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL)/sizeof(mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL[0]), 0, 0 }, + { "mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2", REG_MMIO, 0x0532, 2, &mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2[0], sizeof(mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2)/sizeof(mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2[0]), 0, 0 }, + { "mmDCHUBBUB_VLINE_SNAPSHOT", REG_MMIO, 0x0533, 2, &mmDCHUBBUB_VLINE_SNAPSHOT[0], sizeof(mmDCHUBBUB_VLINE_SNAPSHOT)/sizeof(mmDCHUBBUB_VLINE_SNAPSHOT[0]), 0, 0 }, + { "mmDCHUBBUB_SPARE", REG_MMIO, 0x0534, 2, &mmDCHUBBUB_SPARE[0], sizeof(mmDCHUBBUB_SPARE)/sizeof(mmDCHUBBUB_SPARE[0]), 0, 0 }, + { "mmDC_PERFMON7_PERFCOUNTER_CNTL", REG_MMIO, 0x054d, 2, &mmDC_PERFMON7_PERFCOUNTER_CNTL[0], sizeof(mmDC_PERFMON7_PERFCOUNTER_CNTL)/sizeof(mmDC_PERFMON7_PERFCOUNTER_CNTL[0]), 0, 0 }, + { "mmDC_PERFMON7_PERFCOUNTER_CNTL2", REG_MMIO, 0x054e, 2, &mmDC_PERFMON7_PERFCOUNTER_CNTL2[0], sizeof(mmDC_PERFMON7_PERFCOUNTER_CNTL2)/sizeof(mmDC_PERFMON7_PERFCOUNTER_CNTL2[0]), 0, 0 }, + { "mmDC_PERFMON7_PERFCOUNTER_STATE", REG_MMIO, 0x054f, 2, &mmDC_PERFMON7_PERFCOUNTER_STATE[0], sizeof(mmDC_PERFMON7_PERFCOUNTER_STATE)/sizeof(mmDC_PERFMON7_PERFCOUNTER_STATE[0]), 0, 0 }, + { "mmDC_PERFMON7_PERFMON_CNTL", REG_MMIO, 0x0550, 2, &mmDC_PERFMON7_PERFMON_CNTL[0], sizeof(mmDC_PERFMON7_PERFMON_CNTL)/sizeof(mmDC_PERFMON7_PERFMON_CNTL[0]), 0, 0 }, + { "mmDC_PERFMON7_PERFMON_CNTL2", REG_MMIO, 0x0551, 2, &mmDC_PERFMON7_PERFMON_CNTL2[0], sizeof(mmDC_PERFMON7_PERFMON_CNTL2)/sizeof(mmDC_PERFMON7_PERFMON_CNTL2[0]), 0, 0 }, + { "mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC", REG_MMIO, 0x0552, 2, &mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC[0], sizeof(mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC)/sizeof(mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC[0]), 0, 0 }, + { "mmDC_PERFMON7_PERFMON_CVALUE_LOW", REG_MMIO, 0x0553, 2, &mmDC_PERFMON7_PERFMON_CVALUE_LOW[0], sizeof(mmDC_PERFMON7_PERFMON_CVALUE_LOW)/sizeof(mmDC_PERFMON7_PERFMON_CVALUE_LOW[0]), 0, 0 }, + { "mmDC_PERFMON7_PERFMON_HI", REG_MMIO, 0x0554, 2, &mmDC_PERFMON7_PERFMON_HI[0], sizeof(mmDC_PERFMON7_PERFMON_HI)/sizeof(mmDC_PERFMON7_PERFMON_HI[0]), 0, 0 }, + { "mmDC_PERFMON7_PERFMON_LOW", REG_MMIO, 0x0555, 2, &mmDC_PERFMON7_PERFMON_LOW[0], sizeof(mmDC_PERFMON7_PERFMON_LOW)/sizeof(mmDC_PERFMON7_PERFMON_LOW[0]), 0, 0 }, + { "mmHUBP0_DCSURF_SURFACE_CONFIG", REG_MMIO, 0x0559, 2, &mmHUBP0_DCSURF_SURFACE_CONFIG[0], sizeof(mmHUBP0_DCSURF_SURFACE_CONFIG)/sizeof(mmHUBP0_DCSURF_SURFACE_CONFIG[0]), 0, 0 }, + { "mmHUBP0_DCSURF_ADDR_CONFIG", REG_MMIO, 0x055a, 2, &mmHUBP0_DCSURF_ADDR_CONFIG[0], sizeof(mmHUBP0_DCSURF_ADDR_CONFIG)/sizeof(mmHUBP0_DCSURF_ADDR_CONFIG[0]), 0, 0 }, + { "mmHUBP0_DCSURF_TILING_CONFIG", REG_MMIO, 0x055b, 2, &mmHUBP0_DCSURF_TILING_CONFIG[0], sizeof(mmHUBP0_DCSURF_TILING_CONFIG)/sizeof(mmHUBP0_DCSURF_TILING_CONFIG[0]), 0, 0 }, + { "mmHUBP0_DCSURF_PRI_VIEWPORT_START", REG_MMIO, 0x055c, 2, &mmHUBP0_DCSURF_PRI_VIEWPORT_START[0], sizeof(mmHUBP0_DCSURF_PRI_VIEWPORT_START)/sizeof(mmHUBP0_DCSURF_PRI_VIEWPORT_START[0]), 0, 0 }, + { "mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION", REG_MMIO, 0x055d, 2, &mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION[0], sizeof(mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION)/sizeof(mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION[0]), 0, 0 }, + { "mmHUBP0_DCSURF_PRI_VIEWPORT_START_C", REG_MMIO, 0x055e, 2, &mmHUBP0_DCSURF_PRI_VIEWPORT_START_C[0], sizeof(mmHUBP0_DCSURF_PRI_VIEWPORT_START_C)/sizeof(mmHUBP0_DCSURF_PRI_VIEWPORT_START_C[0]), 0, 0 }, + { "mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C", REG_MMIO, 0x055f, 2, &mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C[0], sizeof(mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C)/sizeof(mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C[0]), 0, 0 }, + { "mmHUBP0_DCSURF_SEC_VIEWPORT_START", REG_MMIO, 0x0560, 2, &mmHUBP0_DCSURF_SEC_VIEWPORT_START[0], sizeof(mmHUBP0_DCSURF_SEC_VIEWPORT_START)/sizeof(mmHUBP0_DCSURF_SEC_VIEWPORT_START[0]), 0, 0 }, + { "mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION", REG_MMIO, 0x0561, 2, &mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION[0], sizeof(mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION)/sizeof(mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION[0]), 0, 0 }, + { "mmHUBP0_DCSURF_SEC_VIEWPORT_START_C", REG_MMIO, 0x0562, 2, &mmHUBP0_DCSURF_SEC_VIEWPORT_START_C[0], sizeof(mmHUBP0_DCSURF_SEC_VIEWPORT_START_C)/sizeof(mmHUBP0_DCSURF_SEC_VIEWPORT_START_C[0]), 0, 0 }, + { "mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C", REG_MMIO, 0x0563, 2, &mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C[0], sizeof(mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C)/sizeof(mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C[0]), 0, 0 }, + { "mmHUBP0_DCHUBP_REQ_SIZE_CONFIG", REG_MMIO, 0x0564, 2, &mmHUBP0_DCHUBP_REQ_SIZE_CONFIG[0], sizeof(mmHUBP0_DCHUBP_REQ_SIZE_CONFIG)/sizeof(mmHUBP0_DCHUBP_REQ_SIZE_CONFIG[0]), 0, 0 }, + { "mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C", REG_MMIO, 0x0565, 2, &mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C[0], sizeof(mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C)/sizeof(mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C[0]), 0, 0 }, + { "mmHUBP0_DCHUBP_CNTL", REG_MMIO, 0x0566, 2, &mmHUBP0_DCHUBP_CNTL[0], sizeof(mmHUBP0_DCHUBP_CNTL)/sizeof(mmHUBP0_DCHUBP_CNTL[0]), 0, 0 }, + { "mmHUBP0_HUBP_CLK_CNTL", REG_MMIO, 0x0567, 2, &mmHUBP0_HUBP_CLK_CNTL[0], sizeof(mmHUBP0_HUBP_CLK_CNTL)/sizeof(mmHUBP0_HUBP_CLK_CNTL[0]), 0, 0 }, + { "mmHUBP0_DCHUBP_VMPG_CONFIG", REG_MMIO, 0x0568, 2, &mmHUBP0_DCHUBP_VMPG_CONFIG[0], sizeof(mmHUBP0_DCHUBP_VMPG_CONFIG)/sizeof(mmHUBP0_DCHUBP_VMPG_CONFIG[0]), 0, 0 }, + { "mmHUBP0_HUBPREQ_DEBUG_DB", REG_MMIO, 0x0569, 2, &mmHUBP0_HUBPREQ_DEBUG_DB[0], sizeof(mmHUBP0_HUBPREQ_DEBUG_DB)/sizeof(mmHUBP0_HUBPREQ_DEBUG_DB[0]), 0, 0 }, + { "mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK", REG_MMIO, 0x056e, 2, &mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK[0], sizeof(mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK)/sizeof(mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK[0]), 0, 0 }, + { "mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK", REG_MMIO, 0x056f, 2, &mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK[0], sizeof(mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK)/sizeof(mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK[0]), 0, 0 }, + { "mmHUBPREQ0_DCSURF_SURFACE_PITCH", REG_MMIO, 0x057b, 2, &mmHUBPREQ0_DCSURF_SURFACE_PITCH[0], sizeof(mmHUBPREQ0_DCSURF_SURFACE_PITCH)/sizeof(mmHUBPREQ0_DCSURF_SURFACE_PITCH[0]), 0, 0 }, + { "mmHUBPREQ0_DCSURF_SURFACE_PITCH_C", REG_MMIO, 0x057c, 2, &mmHUBPREQ0_DCSURF_SURFACE_PITCH_C[0], sizeof(mmHUBPREQ0_DCSURF_SURFACE_PITCH_C)/sizeof(mmHUBPREQ0_DCSURF_SURFACE_PITCH_C[0]), 0, 0 }, + { "mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS", REG_MMIO, 0x057d, 2, &mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS[0], sizeof(mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS)/sizeof(mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS[0]), 0, 0 }, + { "mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x057e, 2, &mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH[0], sizeof(mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH)/sizeof(mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH[0]), 0, 0 }, + { "mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C", REG_MMIO, 0x057f, 2, &mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C[0], sizeof(mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C)/sizeof(mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C[0]), 0, 0 }, + { "mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C", REG_MMIO, 0x0580, 2, &mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C[0], sizeof(mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C)/sizeof(mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C[0]), 0, 0 }, + { "mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS", REG_MMIO, 0x0581, 2, &mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS[0], sizeof(mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS)/sizeof(mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS[0]), 0, 0 }, + { "mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x0582, 2, &mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH[0], sizeof(mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH)/sizeof(mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH[0]), 0, 0 }, + { "mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C", REG_MMIO, 0x0583, 2, &mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C[0], sizeof(mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C)/sizeof(mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C[0]), 0, 0 }, + { "mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C", REG_MMIO, 0x0584, 2, &mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C[0], sizeof(mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C)/sizeof(mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C[0]), 0, 0 }, + { "mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS", REG_MMIO, 0x0585, 2, &mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS[0], sizeof(mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS)/sizeof(mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS[0]), 0, 0 }, + { "mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x0586, 2, &mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH[0], sizeof(mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH)/sizeof(mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH[0]), 0, 0 }, + { "mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C", REG_MMIO, 0x0587, 2, &mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C[0], sizeof(mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C)/sizeof(mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C[0]), 0, 0 }, + { "mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C", REG_MMIO, 0x0588, 2, &mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C[0], sizeof(mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C)/sizeof(mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C[0]), 0, 0 }, + { "mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS", REG_MMIO, 0x0589, 2, &mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS[0], sizeof(mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS)/sizeof(mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS[0]), 0, 0 }, + { "mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x058a, 2, &mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH[0], sizeof(mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH)/sizeof(mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH[0]), 0, 0 }, + { "mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C", REG_MMIO, 0x058b, 2, &mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C[0], sizeof(mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C)/sizeof(mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C[0]), 0, 0 }, + { "mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C", REG_MMIO, 0x058c, 2, &mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C[0], sizeof(mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C)/sizeof(mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C[0]), 0, 0 }, + { "mmHUBPREQ0_DCSURF_SURFACE_CONTROL", REG_MMIO, 0x058d, 2, &mmHUBPREQ0_DCSURF_SURFACE_CONTROL[0], sizeof(mmHUBPREQ0_DCSURF_SURFACE_CONTROL)/sizeof(mmHUBPREQ0_DCSURF_SURFACE_CONTROL[0]), 0, 0 }, + { "mmHUBPREQ0_DCSURF_FLIP_CONTROL", REG_MMIO, 0x058e, 2, &mmHUBPREQ0_DCSURF_FLIP_CONTROL[0], sizeof(mmHUBPREQ0_DCSURF_FLIP_CONTROL)/sizeof(mmHUBPREQ0_DCSURF_FLIP_CONTROL[0]), 0, 0 }, + { "mmHUBPREQ0_DCSURF_FLIP_CONTROL2", REG_MMIO, 0x058f, 2, &mmHUBPREQ0_DCSURF_FLIP_CONTROL2[0], sizeof(mmHUBPREQ0_DCSURF_FLIP_CONTROL2)/sizeof(mmHUBPREQ0_DCSURF_FLIP_CONTROL2[0]), 0, 0 }, + { "mmHUBPREQ0_DCSURF_FRAME_PACING_CONTROL", REG_MMIO, 0x0590, 2, &mmHUBPREQ0_DCSURF_FRAME_PACING_CONTROL[0], sizeof(mmHUBPREQ0_DCSURF_FRAME_PACING_CONTROL)/sizeof(mmHUBPREQ0_DCSURF_FRAME_PACING_CONTROL[0]), 0, 0 }, + { "mmHUBPREQ0_DCSURF_FRAME_PACING_TIME", REG_MMIO, 0x0591, 2, &mmHUBPREQ0_DCSURF_FRAME_PACING_TIME[0], sizeof(mmHUBPREQ0_DCSURF_FRAME_PACING_TIME)/sizeof(mmHUBPREQ0_DCSURF_FRAME_PACING_TIME[0]), 0, 0 }, + { "mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT", REG_MMIO, 0x0592, 2, &mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT[0], sizeof(mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT)/sizeof(mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT[0]), 0, 0 }, + { "mmHUBPREQ0_DCSURF_SURFACE_INUSE", REG_MMIO, 0x0593, 2, &mmHUBPREQ0_DCSURF_SURFACE_INUSE[0], sizeof(mmHUBPREQ0_DCSURF_SURFACE_INUSE)/sizeof(mmHUBPREQ0_DCSURF_SURFACE_INUSE[0]), 0, 0 }, + { "mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH", REG_MMIO, 0x0594, 2, &mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH[0], sizeof(mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH)/sizeof(mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH[0]), 0, 0 }, + { "mmHUBPREQ0_DCSURF_SURFACE_INUSE_C", REG_MMIO, 0x0595, 2, &mmHUBPREQ0_DCSURF_SURFACE_INUSE_C[0], sizeof(mmHUBPREQ0_DCSURF_SURFACE_INUSE_C)/sizeof(mmHUBPREQ0_DCSURF_SURFACE_INUSE_C[0]), 0, 0 }, + { "mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C", REG_MMIO, 0x0596, 2, &mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C[0], sizeof(mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C)/sizeof(mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C[0]), 0, 0 }, + { "mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE", REG_MMIO, 0x0597, 2, &mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE[0], sizeof(mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE)/sizeof(mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE[0]), 0, 0 }, + { "mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH", REG_MMIO, 0x0598, 2, &mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH[0], sizeof(mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH)/sizeof(mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH[0]), 0, 0 }, + { "mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C", REG_MMIO, 0x0599, 2, &mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C[0], sizeof(mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C)/sizeof(mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C[0]), 0, 0 }, + { "mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C", REG_MMIO, 0x059a, 2, &mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C[0], sizeof(mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C)/sizeof(mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C[0]), 0, 0 }, + { "mmHUBPREQ0_DCN_EXPANSION_MODE", REG_MMIO, 0x059b, 2, &mmHUBPREQ0_DCN_EXPANSION_MODE[0], sizeof(mmHUBPREQ0_DCN_EXPANSION_MODE)/sizeof(mmHUBPREQ0_DCN_EXPANSION_MODE[0]), 0, 0 }, + { "mmHUBPREQ0_DCN_TTU_QOS_WM", REG_MMIO, 0x059c, 2, &mmHUBPREQ0_DCN_TTU_QOS_WM[0], sizeof(mmHUBPREQ0_DCN_TTU_QOS_WM)/sizeof(mmHUBPREQ0_DCN_TTU_QOS_WM[0]), 0, 0 }, + { "mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL", REG_MMIO, 0x059d, 2, &mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL[0], sizeof(mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL)/sizeof(mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL[0]), 0, 0 }, + { "mmHUBPREQ0_DCN_SURF0_TTU_CNTL0", REG_MMIO, 0x059e, 2, &mmHUBPREQ0_DCN_SURF0_TTU_CNTL0[0], sizeof(mmHUBPREQ0_DCN_SURF0_TTU_CNTL0)/sizeof(mmHUBPREQ0_DCN_SURF0_TTU_CNTL0[0]), 0, 0 }, + { "mmHUBPREQ0_DCN_SURF0_TTU_CNTL1", REG_MMIO, 0x059f, 2, &mmHUBPREQ0_DCN_SURF0_TTU_CNTL1[0], sizeof(mmHUBPREQ0_DCN_SURF0_TTU_CNTL1)/sizeof(mmHUBPREQ0_DCN_SURF0_TTU_CNTL1[0]), 0, 0 }, + { "mmHUBPREQ0_DCN_SURF1_TTU_CNTL0", REG_MMIO, 0x05a0, 2, &mmHUBPREQ0_DCN_SURF1_TTU_CNTL0[0], sizeof(mmHUBPREQ0_DCN_SURF1_TTU_CNTL0)/sizeof(mmHUBPREQ0_DCN_SURF1_TTU_CNTL0[0]), 0, 0 }, + { "mmHUBPREQ0_DCN_SURF1_TTU_CNTL1", REG_MMIO, 0x05a1, 2, &mmHUBPREQ0_DCN_SURF1_TTU_CNTL1[0], sizeof(mmHUBPREQ0_DCN_SURF1_TTU_CNTL1)/sizeof(mmHUBPREQ0_DCN_SURF1_TTU_CNTL1[0]), 0, 0 }, + { "mmHUBPREQ0_DCN_CUR0_TTU_CNTL0", REG_MMIO, 0x05a2, 2, &mmHUBPREQ0_DCN_CUR0_TTU_CNTL0[0], sizeof(mmHUBPREQ0_DCN_CUR0_TTU_CNTL0)/sizeof(mmHUBPREQ0_DCN_CUR0_TTU_CNTL0[0]), 0, 0 }, + { "mmHUBPREQ0_DCN_CUR0_TTU_CNTL1", REG_MMIO, 0x05a3, 2, &mmHUBPREQ0_DCN_CUR0_TTU_CNTL1[0], sizeof(mmHUBPREQ0_DCN_CUR0_TTU_CNTL1)/sizeof(mmHUBPREQ0_DCN_CUR0_TTU_CNTL1[0]), 0, 0 }, + { "mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB", REG_MMIO, 0x05a4, 2, &mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB[0], sizeof(mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB)/sizeof(mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB[0]), 0, 0 }, + { "mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB", REG_MMIO, 0x05a5, 2, &mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB[0], sizeof(mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB)/sizeof(mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB[0]), 0, 0 }, + { "mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB", REG_MMIO, 0x05a6, 2, &mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB[0], sizeof(mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB)/sizeof(mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB[0]), 0, 0 }, + { "mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB", REG_MMIO, 0x05a7, 2, &mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB[0], sizeof(mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB)/sizeof(mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB[0]), 0, 0 }, + { "mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB", REG_MMIO, 0x05a8, 2, &mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB[0], sizeof(mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB)/sizeof(mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB[0]), 0, 0 }, + { "mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB", REG_MMIO, 0x05a9, 2, &mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB[0], sizeof(mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB)/sizeof(mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB[0]), 0, 0 }, + { "mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB", REG_MMIO, 0x05aa, 2, &mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB[0], sizeof(mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB)/sizeof(mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB[0]), 0, 0 }, + { "mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB", REG_MMIO, 0x05ab, 2, &mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB[0], sizeof(mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB)/sizeof(mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB[0]), 0, 0 }, + { "mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB", REG_MMIO, 0x05ac, 2, &mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB[0], sizeof(mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB)/sizeof(mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB[0]), 0, 0 }, + { "mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB", REG_MMIO, 0x05ad, 2, &mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB[0], sizeof(mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB)/sizeof(mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB[0]), 0, 0 }, + { "mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB", REG_MMIO, 0x05ae, 2, &mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB[0], sizeof(mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB)/sizeof(mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB[0]), 0, 0 }, + { "mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB", REG_MMIO, 0x05af, 2, &mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB[0], sizeof(mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB)/sizeof(mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB[0]), 0, 0 }, + { "mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB", REG_MMIO, 0x05b0, 2, &mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB[0], sizeof(mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB)/sizeof(mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB[0]), 0, 0 }, + { "mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB", REG_MMIO, 0x05b1, 2, &mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB[0], sizeof(mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB)/sizeof(mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB[0]), 0, 0 }, + { "mmHUBPREQ0_DCN_VM_CONTEXT0_STATUS", REG_MMIO, 0x05b2, 2, &mmHUBPREQ0_DCN_VM_CONTEXT0_STATUS[0], sizeof(mmHUBPREQ0_DCN_VM_CONTEXT0_STATUS)/sizeof(mmHUBPREQ0_DCN_VM_CONTEXT0_STATUS[0]), 0, 0 }, + { "mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB", REG_MMIO, 0x05b3, 2, &mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB[0], sizeof(mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB)/sizeof(mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB[0]), 0, 0 }, + { "mmHUBPREQ0_DCN_VM_CONTEXT0_CNTL", REG_MMIO, 0x05b4, 2, &mmHUBPREQ0_DCN_VM_CONTEXT0_CNTL[0], sizeof(mmHUBPREQ0_DCN_VM_CONTEXT0_CNTL)/sizeof(mmHUBPREQ0_DCN_VM_CONTEXT0_CNTL[0]), 0, 0 }, + { "mmHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL", REG_MMIO, 0x05b5, 2, &mmHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL[0], sizeof(mmHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL)/sizeof(mmHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL[0]), 0, 0 }, + { "mmHUBPREQ0_BLANK_OFFSET_0", REG_MMIO, 0x05b6, 2, &mmHUBPREQ0_BLANK_OFFSET_0[0], sizeof(mmHUBPREQ0_BLANK_OFFSET_0)/sizeof(mmHUBPREQ0_BLANK_OFFSET_0[0]), 0, 0 }, + { "mmHUBPREQ0_BLANK_OFFSET_1", REG_MMIO, 0x05b7, 2, &mmHUBPREQ0_BLANK_OFFSET_1[0], sizeof(mmHUBPREQ0_BLANK_OFFSET_1)/sizeof(mmHUBPREQ0_BLANK_OFFSET_1[0]), 0, 0 }, + { "mmHUBPREQ0_DST_DIMENSIONS", REG_MMIO, 0x05b8, 2, &mmHUBPREQ0_DST_DIMENSIONS[0], sizeof(mmHUBPREQ0_DST_DIMENSIONS)/sizeof(mmHUBPREQ0_DST_DIMENSIONS[0]), 0, 0 }, + { "mmHUBPREQ0_DST_AFTER_SCALER", REG_MMIO, 0x05b9, 2, &mmHUBPREQ0_DST_AFTER_SCALER[0], sizeof(mmHUBPREQ0_DST_AFTER_SCALER)/sizeof(mmHUBPREQ0_DST_AFTER_SCALER[0]), 0, 0 }, + { "mmHUBPREQ0_PREFETCH_SETTINS", REG_MMIO, 0x05ba, 2, &mmHUBPREQ0_PREFETCH_SETTINS[0], sizeof(mmHUBPREQ0_PREFETCH_SETTINS)/sizeof(mmHUBPREQ0_PREFETCH_SETTINS[0]), 0, 0 }, + { "mmHUBPREQ0_PREFETCH_SETTINS_C", REG_MMIO, 0x05bb, 2, &mmHUBPREQ0_PREFETCH_SETTINS_C[0], sizeof(mmHUBPREQ0_PREFETCH_SETTINS_C)/sizeof(mmHUBPREQ0_PREFETCH_SETTINS_C[0]), 0, 0 }, + { "mmHUBPREQ0_VBLANK_PARAMETERS_0", REG_MMIO, 0x05bc, 2, &mmHUBPREQ0_VBLANK_PARAMETERS_0[0], sizeof(mmHUBPREQ0_VBLANK_PARAMETERS_0)/sizeof(mmHUBPREQ0_VBLANK_PARAMETERS_0[0]), 0, 0 }, + { "mmHUBPREQ0_VBLANK_PARAMETERS_1", REG_MMIO, 0x05bd, 2, &mmHUBPREQ0_VBLANK_PARAMETERS_1[0], sizeof(mmHUBPREQ0_VBLANK_PARAMETERS_1)/sizeof(mmHUBPREQ0_VBLANK_PARAMETERS_1[0]), 0, 0 }, + { "mmHUBPREQ0_VBLANK_PARAMETERS_2", REG_MMIO, 0x05be, 2, &mmHUBPREQ0_VBLANK_PARAMETERS_2[0], sizeof(mmHUBPREQ0_VBLANK_PARAMETERS_2)/sizeof(mmHUBPREQ0_VBLANK_PARAMETERS_2[0]), 0, 0 }, + { "mmHUBPREQ0_VBLANK_PARAMETERS_3", REG_MMIO, 0x05bf, 2, &mmHUBPREQ0_VBLANK_PARAMETERS_3[0], sizeof(mmHUBPREQ0_VBLANK_PARAMETERS_3)/sizeof(mmHUBPREQ0_VBLANK_PARAMETERS_3[0]), 0, 0 }, + { "mmHUBPREQ0_VBLANK_PARAMETERS_4", REG_MMIO, 0x05c0, 2, &mmHUBPREQ0_VBLANK_PARAMETERS_4[0], sizeof(mmHUBPREQ0_VBLANK_PARAMETERS_4)/sizeof(mmHUBPREQ0_VBLANK_PARAMETERS_4[0]), 0, 0 }, + { "mmHUBPREQ0_NOM_PARAMETERS_0", REG_MMIO, 0x05c1, 2, &mmHUBPREQ0_NOM_PARAMETERS_0[0], sizeof(mmHUBPREQ0_NOM_PARAMETERS_0)/sizeof(mmHUBPREQ0_NOM_PARAMETERS_0[0]), 0, 0 }, + { "mmHUBPREQ0_NOM_PARAMETERS_1", REG_MMIO, 0x05c2, 2, &mmHUBPREQ0_NOM_PARAMETERS_1[0], sizeof(mmHUBPREQ0_NOM_PARAMETERS_1)/sizeof(mmHUBPREQ0_NOM_PARAMETERS_1[0]), 0, 0 }, + { "mmHUBPREQ0_NOM_PARAMETERS_2", REG_MMIO, 0x05c3, 2, &mmHUBPREQ0_NOM_PARAMETERS_2[0], sizeof(mmHUBPREQ0_NOM_PARAMETERS_2)/sizeof(mmHUBPREQ0_NOM_PARAMETERS_2[0]), 0, 0 }, + { "mmHUBPREQ0_NOM_PARAMETERS_3", REG_MMIO, 0x05c4, 2, &mmHUBPREQ0_NOM_PARAMETERS_3[0], sizeof(mmHUBPREQ0_NOM_PARAMETERS_3)/sizeof(mmHUBPREQ0_NOM_PARAMETERS_3[0]), 0, 0 }, + { "mmHUBPREQ0_NOM_PARAMETERS_4", REG_MMIO, 0x05c5, 2, &mmHUBPREQ0_NOM_PARAMETERS_4[0], sizeof(mmHUBPREQ0_NOM_PARAMETERS_4)/sizeof(mmHUBPREQ0_NOM_PARAMETERS_4[0]), 0, 0 }, + { "mmHUBPREQ0_NOM_PARAMETERS_5", REG_MMIO, 0x05c6, 2, &mmHUBPREQ0_NOM_PARAMETERS_5[0], sizeof(mmHUBPREQ0_NOM_PARAMETERS_5)/sizeof(mmHUBPREQ0_NOM_PARAMETERS_5[0]), 0, 0 }, + { "mmHUBPREQ0_NOM_PARAMETERS_6", REG_MMIO, 0x05c7, 2, &mmHUBPREQ0_NOM_PARAMETERS_6[0], sizeof(mmHUBPREQ0_NOM_PARAMETERS_6)/sizeof(mmHUBPREQ0_NOM_PARAMETERS_6[0]), 0, 0 }, + { "mmHUBPREQ0_NOM_PARAMETERS_7", REG_MMIO, 0x05c8, 2, &mmHUBPREQ0_NOM_PARAMETERS_7[0], sizeof(mmHUBPREQ0_NOM_PARAMETERS_7)/sizeof(mmHUBPREQ0_NOM_PARAMETERS_7[0]), 0, 0 }, + { "mmHUBPREQ0_PER_LINE_DELIVERY_PRE", REG_MMIO, 0x05c9, 2, &mmHUBPREQ0_PER_LINE_DELIVERY_PRE[0], sizeof(mmHUBPREQ0_PER_LINE_DELIVERY_PRE)/sizeof(mmHUBPREQ0_PER_LINE_DELIVERY_PRE[0]), 0, 0 }, + { "mmHUBPREQ0_PER_LINE_DELIVERY", REG_MMIO, 0x05ca, 2, &mmHUBPREQ0_PER_LINE_DELIVERY[0], sizeof(mmHUBPREQ0_PER_LINE_DELIVERY)/sizeof(mmHUBPREQ0_PER_LINE_DELIVERY[0]), 0, 0 }, + { "mmHUBPREQ0_CURSOR_SETTINS", REG_MMIO, 0x05cb, 2, &mmHUBPREQ0_CURSOR_SETTINS[0], sizeof(mmHUBPREQ0_CURSOR_SETTINS)/sizeof(mmHUBPREQ0_CURSOR_SETTINS[0]), 0, 0 }, + { "mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ", REG_MMIO, 0x05cc, 2, &mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ[0], sizeof(mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ)/sizeof(mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ[0]), 0, 0 }, + { "mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL", REG_MMIO, 0x05cd, 2, &mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL[0], sizeof(mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL)/sizeof(mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL[0]), 0, 0 }, + { "mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS", REG_MMIO, 0x05ce, 2, &mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS[0], sizeof(mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS)/sizeof(mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS[0]), 0, 0 }, + { "mmHUBPRET0_HUBPRET_CONTROL", REG_MMIO, 0x05e0, 2, &mmHUBPRET0_HUBPRET_CONTROL[0], sizeof(mmHUBPRET0_HUBPRET_CONTROL)/sizeof(mmHUBPRET0_HUBPRET_CONTROL[0]), 0, 0 }, + { "mmHUBPRET0_HUBPRET_MEM_PWR_CTRL", REG_MMIO, 0x05e1, 2, &mmHUBPRET0_HUBPRET_MEM_PWR_CTRL[0], sizeof(mmHUBPRET0_HUBPRET_MEM_PWR_CTRL)/sizeof(mmHUBPRET0_HUBPRET_MEM_PWR_CTRL[0]), 0, 0 }, + { "mmHUBPRET0_HUBPRET_MEM_PWR_STATUS", REG_MMIO, 0x05e2, 2, &mmHUBPRET0_HUBPRET_MEM_PWR_STATUS[0], sizeof(mmHUBPRET0_HUBPRET_MEM_PWR_STATUS)/sizeof(mmHUBPRET0_HUBPRET_MEM_PWR_STATUS[0]), 0, 0 }, + { "mmHUBPRET0_HUBPRET_READ_LINE_CTRL0", REG_MMIO, 0x05e3, 2, &mmHUBPRET0_HUBPRET_READ_LINE_CTRL0[0], sizeof(mmHUBPRET0_HUBPRET_READ_LINE_CTRL0)/sizeof(mmHUBPRET0_HUBPRET_READ_LINE_CTRL0[0]), 0, 0 }, + { "mmHUBPRET0_HUBPRET_READ_LINE_CTRL1", REG_MMIO, 0x05e4, 2, &mmHUBPRET0_HUBPRET_READ_LINE_CTRL1[0], sizeof(mmHUBPRET0_HUBPRET_READ_LINE_CTRL1)/sizeof(mmHUBPRET0_HUBPRET_READ_LINE_CTRL1[0]), 0, 0 }, + { "mmHUBPRET0_HUBPRET_READ_LINE0", REG_MMIO, 0x05e5, 2, &mmHUBPRET0_HUBPRET_READ_LINE0[0], sizeof(mmHUBPRET0_HUBPRET_READ_LINE0)/sizeof(mmHUBPRET0_HUBPRET_READ_LINE0[0]), 0, 0 }, + { "mmHUBPRET0_HUBPRET_READ_LINE1", REG_MMIO, 0x05e6, 2, &mmHUBPRET0_HUBPRET_READ_LINE1[0], sizeof(mmHUBPRET0_HUBPRET_READ_LINE1)/sizeof(mmHUBPRET0_HUBPRET_READ_LINE1[0]), 0, 0 }, + { "mmHUBPRET0_HUBPRET_INTERRUPT", REG_MMIO, 0x05e7, 2, &mmHUBPRET0_HUBPRET_INTERRUPT[0], sizeof(mmHUBPRET0_HUBPRET_INTERRUPT)/sizeof(mmHUBPRET0_HUBPRET_INTERRUPT[0]), 0, 0 }, + { "mmHUBPRET0_HUBPRET_READ_LINE_VALUE", REG_MMIO, 0x05e8, 2, &mmHUBPRET0_HUBPRET_READ_LINE_VALUE[0], sizeof(mmHUBPRET0_HUBPRET_READ_LINE_VALUE)/sizeof(mmHUBPRET0_HUBPRET_READ_LINE_VALUE[0]), 0, 0 }, + { "mmHUBPRET0_HUBPRET_READ_LINE_STATUS", REG_MMIO, 0x05e9, 2, &mmHUBPRET0_HUBPRET_READ_LINE_STATUS[0], sizeof(mmHUBPRET0_HUBPRET_READ_LINE_STATUS)/sizeof(mmHUBPRET0_HUBPRET_READ_LINE_STATUS[0]), 0, 0 }, + { "mmCURSOR0_CURSOR_CONTROL", REG_MMIO, 0x05ec, 2, &mmCURSOR0_CURSOR_CONTROL[0], sizeof(mmCURSOR0_CURSOR_CONTROL)/sizeof(mmCURSOR0_CURSOR_CONTROL[0]), 0, 0 }, + { "mmCURSOR0_CURSOR_SURFACE_ADDRESS", REG_MMIO, 0x05ed, 2, &mmCURSOR0_CURSOR_SURFACE_ADDRESS[0], sizeof(mmCURSOR0_CURSOR_SURFACE_ADDRESS)/sizeof(mmCURSOR0_CURSOR_SURFACE_ADDRESS[0]), 0, 0 }, + { "mmCURSOR0_CURSOR_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x05ee, 2, &mmCURSOR0_CURSOR_SURFACE_ADDRESS_HIGH[0], sizeof(mmCURSOR0_CURSOR_SURFACE_ADDRESS_HIGH)/sizeof(mmCURSOR0_CURSOR_SURFACE_ADDRESS_HIGH[0]), 0, 0 }, + { "mmCURSOR0_CURSOR_SIZE", REG_MMIO, 0x05ef, 2, &mmCURSOR0_CURSOR_SIZE[0], sizeof(mmCURSOR0_CURSOR_SIZE)/sizeof(mmCURSOR0_CURSOR_SIZE[0]), 0, 0 }, + { "mmCURSOR0_CURSOR_POSITION", REG_MMIO, 0x05f0, 2, &mmCURSOR0_CURSOR_POSITION[0], sizeof(mmCURSOR0_CURSOR_POSITION)/sizeof(mmCURSOR0_CURSOR_POSITION[0]), 0, 0 }, + { "mmCURSOR0_CURSOR_HOT_SPOT", REG_MMIO, 0x05f1, 2, &mmCURSOR0_CURSOR_HOT_SPOT[0], sizeof(mmCURSOR0_CURSOR_HOT_SPOT)/sizeof(mmCURSOR0_CURSOR_HOT_SPOT[0]), 0, 0 }, + { "mmCURSOR0_CURSOR_STEREO_CONTROL", REG_MMIO, 0x05f2, 2, &mmCURSOR0_CURSOR_STEREO_CONTROL[0], sizeof(mmCURSOR0_CURSOR_STEREO_CONTROL)/sizeof(mmCURSOR0_CURSOR_STEREO_CONTROL[0]), 0, 0 }, + { "mmCURSOR0_CURSOR_DST_OFFSET", REG_MMIO, 0x05f3, 2, &mmCURSOR0_CURSOR_DST_OFFSET[0], sizeof(mmCURSOR0_CURSOR_DST_OFFSET)/sizeof(mmCURSOR0_CURSOR_DST_OFFSET[0]), 0, 0 }, + { "mmCURSOR0_CURSOR_MEM_PWR_CTRL", REG_MMIO, 0x05f4, 2, &mmCURSOR0_CURSOR_MEM_PWR_CTRL[0], sizeof(mmCURSOR0_CURSOR_MEM_PWR_CTRL)/sizeof(mmCURSOR0_CURSOR_MEM_PWR_CTRL[0]), 0, 0 }, + { "mmCURSOR0_CURSOR_MEM_PWR_STATUS", REG_MMIO, 0x05f5, 2, &mmCURSOR0_CURSOR_MEM_PWR_STATUS[0], sizeof(mmCURSOR0_CURSOR_MEM_PWR_STATUS)/sizeof(mmCURSOR0_CURSOR_MEM_PWR_STATUS[0]), 0, 0 }, + { "mmDC_PERFMON8_PERFCOUNTER_CNTL", REG_MMIO, 0x0611, 2, &mmDC_PERFMON8_PERFCOUNTER_CNTL[0], sizeof(mmDC_PERFMON8_PERFCOUNTER_CNTL)/sizeof(mmDC_PERFMON8_PERFCOUNTER_CNTL[0]), 0, 0 }, + { "mmDC_PERFMON8_PERFCOUNTER_CNTL2", REG_MMIO, 0x0612, 2, &mmDC_PERFMON8_PERFCOUNTER_CNTL2[0], sizeof(mmDC_PERFMON8_PERFCOUNTER_CNTL2)/sizeof(mmDC_PERFMON8_PERFCOUNTER_CNTL2[0]), 0, 0 }, + { "mmDC_PERFMON8_PERFCOUNTER_STATE", REG_MMIO, 0x0613, 2, &mmDC_PERFMON8_PERFCOUNTER_STATE[0], sizeof(mmDC_PERFMON8_PERFCOUNTER_STATE)/sizeof(mmDC_PERFMON8_PERFCOUNTER_STATE[0]), 0, 0 }, + { "mmDC_PERFMON8_PERFMON_CNTL", REG_MMIO, 0x0614, 2, &mmDC_PERFMON8_PERFMON_CNTL[0], sizeof(mmDC_PERFMON8_PERFMON_CNTL)/sizeof(mmDC_PERFMON8_PERFMON_CNTL[0]), 0, 0 }, + { "mmDC_PERFMON8_PERFMON_CNTL2", REG_MMIO, 0x0615, 2, &mmDC_PERFMON8_PERFMON_CNTL2[0], sizeof(mmDC_PERFMON8_PERFMON_CNTL2)/sizeof(mmDC_PERFMON8_PERFMON_CNTL2[0]), 0, 0 }, + { "mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC", REG_MMIO, 0x0616, 2, &mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC[0], sizeof(mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC)/sizeof(mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC[0]), 0, 0 }, + { "mmDC_PERFMON8_PERFMON_CVALUE_LOW", REG_MMIO, 0x0617, 2, &mmDC_PERFMON8_PERFMON_CVALUE_LOW[0], sizeof(mmDC_PERFMON8_PERFMON_CVALUE_LOW)/sizeof(mmDC_PERFMON8_PERFMON_CVALUE_LOW[0]), 0, 0 }, + { "mmDC_PERFMON8_PERFMON_HI", REG_MMIO, 0x0618, 2, &mmDC_PERFMON8_PERFMON_HI[0], sizeof(mmDC_PERFMON8_PERFMON_HI)/sizeof(mmDC_PERFMON8_PERFMON_HI[0]), 0, 0 }, + { "mmDC_PERFMON8_PERFMON_LOW", REG_MMIO, 0x0619, 2, &mmDC_PERFMON8_PERFMON_LOW[0], sizeof(mmDC_PERFMON8_PERFMON_LOW)/sizeof(mmDC_PERFMON8_PERFMON_LOW[0]), 0, 0 }, + { "mmHUBP1_DCSURF_SURFACE_CONFIG", REG_MMIO, 0x061d, 2, &mmHUBP1_DCSURF_SURFACE_CONFIG[0], sizeof(mmHUBP1_DCSURF_SURFACE_CONFIG)/sizeof(mmHUBP1_DCSURF_SURFACE_CONFIG[0]), 0, 0 }, + { "mmHUBP1_DCSURF_ADDR_CONFIG", REG_MMIO, 0x061e, 2, &mmHUBP1_DCSURF_ADDR_CONFIG[0], sizeof(mmHUBP1_DCSURF_ADDR_CONFIG)/sizeof(mmHUBP1_DCSURF_ADDR_CONFIG[0]), 0, 0 }, + { "mmHUBP1_DCSURF_TILING_CONFIG", REG_MMIO, 0x061f, 2, &mmHUBP1_DCSURF_TILING_CONFIG[0], sizeof(mmHUBP1_DCSURF_TILING_CONFIG)/sizeof(mmHUBP1_DCSURF_TILING_CONFIG[0]), 0, 0 }, + { "mmHUBP1_DCSURF_PRI_VIEWPORT_START", REG_MMIO, 0x0620, 2, &mmHUBP1_DCSURF_PRI_VIEWPORT_START[0], sizeof(mmHUBP1_DCSURF_PRI_VIEWPORT_START)/sizeof(mmHUBP1_DCSURF_PRI_VIEWPORT_START[0]), 0, 0 }, + { "mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION", REG_MMIO, 0x0621, 2, &mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION[0], sizeof(mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION)/sizeof(mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION[0]), 0, 0 }, + { "mmHUBP1_DCSURF_PRI_VIEWPORT_START_C", REG_MMIO, 0x0622, 2, &mmHUBP1_DCSURF_PRI_VIEWPORT_START_C[0], sizeof(mmHUBP1_DCSURF_PRI_VIEWPORT_START_C)/sizeof(mmHUBP1_DCSURF_PRI_VIEWPORT_START_C[0]), 0, 0 }, + { "mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C", REG_MMIO, 0x0623, 2, &mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C[0], sizeof(mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C)/sizeof(mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C[0]), 0, 0 }, + { "mmHUBP1_DCSURF_SEC_VIEWPORT_START", REG_MMIO, 0x0624, 2, &mmHUBP1_DCSURF_SEC_VIEWPORT_START[0], sizeof(mmHUBP1_DCSURF_SEC_VIEWPORT_START)/sizeof(mmHUBP1_DCSURF_SEC_VIEWPORT_START[0]), 0, 0 }, + { "mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION", REG_MMIO, 0x0625, 2, &mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION[0], sizeof(mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION)/sizeof(mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION[0]), 0, 0 }, + { "mmHUBP1_DCSURF_SEC_VIEWPORT_START_C", REG_MMIO, 0x0626, 2, &mmHUBP1_DCSURF_SEC_VIEWPORT_START_C[0], sizeof(mmHUBP1_DCSURF_SEC_VIEWPORT_START_C)/sizeof(mmHUBP1_DCSURF_SEC_VIEWPORT_START_C[0]), 0, 0 }, + { "mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C", REG_MMIO, 0x0627, 2, &mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C[0], sizeof(mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C)/sizeof(mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C[0]), 0, 0 }, + { "mmHUBP1_DCHUBP_REQ_SIZE_CONFIG", REG_MMIO, 0x0628, 2, &mmHUBP1_DCHUBP_REQ_SIZE_CONFIG[0], sizeof(mmHUBP1_DCHUBP_REQ_SIZE_CONFIG)/sizeof(mmHUBP1_DCHUBP_REQ_SIZE_CONFIG[0]), 0, 0 }, + { "mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C", REG_MMIO, 0x0629, 2, &mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C[0], sizeof(mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C)/sizeof(mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C[0]), 0, 0 }, + { "mmHUBP1_DCHUBP_CNTL", REG_MMIO, 0x062a, 2, &mmHUBP1_DCHUBP_CNTL[0], sizeof(mmHUBP1_DCHUBP_CNTL)/sizeof(mmHUBP1_DCHUBP_CNTL[0]), 0, 0 }, + { "mmHUBP1_HUBP_CLK_CNTL", REG_MMIO, 0x062b, 2, &mmHUBP1_HUBP_CLK_CNTL[0], sizeof(mmHUBP1_HUBP_CLK_CNTL)/sizeof(mmHUBP1_HUBP_CLK_CNTL[0]), 0, 0 }, + { "mmHUBP1_DCHUBP_VMPG_CONFIG", REG_MMIO, 0x062c, 2, &mmHUBP1_DCHUBP_VMPG_CONFIG[0], sizeof(mmHUBP1_DCHUBP_VMPG_CONFIG)/sizeof(mmHUBP1_DCHUBP_VMPG_CONFIG[0]), 0, 0 }, + { "mmHUBP1_HUBPREQ_DEBUG_DB", REG_MMIO, 0x062d, 2, &mmHUBP1_HUBPREQ_DEBUG_DB[0], sizeof(mmHUBP1_HUBPREQ_DEBUG_DB)/sizeof(mmHUBP1_HUBPREQ_DEBUG_DB[0]), 0, 0 }, + { "mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK", REG_MMIO, 0x0632, 2, &mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK[0], sizeof(mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK)/sizeof(mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK[0]), 0, 0 }, + { "mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK", REG_MMIO, 0x0633, 2, &mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK[0], sizeof(mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK)/sizeof(mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK[0]), 0, 0 }, + { "mmHUBPREQ1_DCSURF_SURFACE_PITCH", REG_MMIO, 0x063f, 2, &mmHUBPREQ1_DCSURF_SURFACE_PITCH[0], sizeof(mmHUBPREQ1_DCSURF_SURFACE_PITCH)/sizeof(mmHUBPREQ1_DCSURF_SURFACE_PITCH[0]), 0, 0 }, + { "mmHUBPREQ1_DCSURF_SURFACE_PITCH_C", REG_MMIO, 0x0640, 2, &mmHUBPREQ1_DCSURF_SURFACE_PITCH_C[0], sizeof(mmHUBPREQ1_DCSURF_SURFACE_PITCH_C)/sizeof(mmHUBPREQ1_DCSURF_SURFACE_PITCH_C[0]), 0, 0 }, + { "mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS", REG_MMIO, 0x0641, 2, &mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS[0], sizeof(mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS)/sizeof(mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS[0]), 0, 0 }, + { "mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x0642, 2, &mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH[0], sizeof(mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH)/sizeof(mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH[0]), 0, 0 }, + { "mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C", REG_MMIO, 0x0643, 2, &mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C[0], sizeof(mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C)/sizeof(mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C[0]), 0, 0 }, + { "mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C", REG_MMIO, 0x0644, 2, &mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C[0], sizeof(mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C)/sizeof(mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C[0]), 0, 0 }, + { "mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS", REG_MMIO, 0x0645, 2, &mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS[0], sizeof(mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS)/sizeof(mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS[0]), 0, 0 }, + { "mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x0646, 2, &mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH[0], sizeof(mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH)/sizeof(mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH[0]), 0, 0 }, + { "mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C", REG_MMIO, 0x0647, 2, &mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C[0], sizeof(mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C)/sizeof(mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C[0]), 0, 0 }, + { "mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C", REG_MMIO, 0x0648, 2, &mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C[0], sizeof(mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C)/sizeof(mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C[0]), 0, 0 }, + { "mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS", REG_MMIO, 0x0649, 2, &mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS[0], sizeof(mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS)/sizeof(mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS[0]), 0, 0 }, + { "mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x064a, 2, &mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH[0], sizeof(mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH)/sizeof(mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH[0]), 0, 0 }, + { "mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C", REG_MMIO, 0x064b, 2, &mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C[0], sizeof(mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C)/sizeof(mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C[0]), 0, 0 }, + { "mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C", REG_MMIO, 0x064c, 2, &mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C[0], sizeof(mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C)/sizeof(mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C[0]), 0, 0 }, + { "mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS", REG_MMIO, 0x064d, 2, &mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS[0], sizeof(mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS)/sizeof(mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS[0]), 0, 0 }, + { "mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x064e, 2, &mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH[0], sizeof(mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH)/sizeof(mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH[0]), 0, 0 }, + { "mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C", REG_MMIO, 0x064f, 2, &mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C[0], sizeof(mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C)/sizeof(mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C[0]), 0, 0 }, + { "mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C", REG_MMIO, 0x0650, 2, &mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C[0], sizeof(mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C)/sizeof(mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C[0]), 0, 0 }, + { "mmHUBPREQ1_DCSURF_SURFACE_CONTROL", REG_MMIO, 0x0651, 2, &mmHUBPREQ1_DCSURF_SURFACE_CONTROL[0], sizeof(mmHUBPREQ1_DCSURF_SURFACE_CONTROL)/sizeof(mmHUBPREQ1_DCSURF_SURFACE_CONTROL[0]), 0, 0 }, + { "mmHUBPREQ1_DCSURF_FLIP_CONTROL", REG_MMIO, 0x0652, 2, &mmHUBPREQ1_DCSURF_FLIP_CONTROL[0], sizeof(mmHUBPREQ1_DCSURF_FLIP_CONTROL)/sizeof(mmHUBPREQ1_DCSURF_FLIP_CONTROL[0]), 0, 0 }, + { "mmHUBPREQ1_DCSURF_FLIP_CONTROL2", REG_MMIO, 0x0653, 2, &mmHUBPREQ1_DCSURF_FLIP_CONTROL2[0], sizeof(mmHUBPREQ1_DCSURF_FLIP_CONTROL2)/sizeof(mmHUBPREQ1_DCSURF_FLIP_CONTROL2[0]), 0, 0 }, + { "mmHUBPREQ1_DCSURF_FRAME_PACING_CONTROL", REG_MMIO, 0x0654, 2, &mmHUBPREQ1_DCSURF_FRAME_PACING_CONTROL[0], sizeof(mmHUBPREQ1_DCSURF_FRAME_PACING_CONTROL)/sizeof(mmHUBPREQ1_DCSURF_FRAME_PACING_CONTROL[0]), 0, 0 }, + { "mmHUBPREQ1_DCSURF_FRAME_PACING_TIME", REG_MMIO, 0x0655, 2, &mmHUBPREQ1_DCSURF_FRAME_PACING_TIME[0], sizeof(mmHUBPREQ1_DCSURF_FRAME_PACING_TIME)/sizeof(mmHUBPREQ1_DCSURF_FRAME_PACING_TIME[0]), 0, 0 }, + { "mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT", REG_MMIO, 0x0656, 2, &mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT[0], sizeof(mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT)/sizeof(mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT[0]), 0, 0 }, + { "mmHUBPREQ1_DCSURF_SURFACE_INUSE", REG_MMIO, 0x0657, 2, &mmHUBPREQ1_DCSURF_SURFACE_INUSE[0], sizeof(mmHUBPREQ1_DCSURF_SURFACE_INUSE)/sizeof(mmHUBPREQ1_DCSURF_SURFACE_INUSE[0]), 0, 0 }, + { "mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH", REG_MMIO, 0x0658, 2, &mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH[0], sizeof(mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH)/sizeof(mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH[0]), 0, 0 }, + { "mmHUBPREQ1_DCSURF_SURFACE_INUSE_C", REG_MMIO, 0x0659, 2, &mmHUBPREQ1_DCSURF_SURFACE_INUSE_C[0], sizeof(mmHUBPREQ1_DCSURF_SURFACE_INUSE_C)/sizeof(mmHUBPREQ1_DCSURF_SURFACE_INUSE_C[0]), 0, 0 }, + { "mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C", REG_MMIO, 0x065a, 2, &mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C[0], sizeof(mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C)/sizeof(mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C[0]), 0, 0 }, + { "mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE", REG_MMIO, 0x065b, 2, &mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE[0], sizeof(mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE)/sizeof(mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE[0]), 0, 0 }, + { "mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH", REG_MMIO, 0x065c, 2, &mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH[0], sizeof(mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH)/sizeof(mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH[0]), 0, 0 }, + { "mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C", REG_MMIO, 0x065d, 2, &mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C[0], sizeof(mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C)/sizeof(mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C[0]), 0, 0 }, + { "mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C", REG_MMIO, 0x065e, 2, &mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C[0], sizeof(mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C)/sizeof(mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C[0]), 0, 0 }, + { "mmHUBPREQ1_DCN_EXPANSION_MODE", REG_MMIO, 0x065f, 2, &mmHUBPREQ1_DCN_EXPANSION_MODE[0], sizeof(mmHUBPREQ1_DCN_EXPANSION_MODE)/sizeof(mmHUBPREQ1_DCN_EXPANSION_MODE[0]), 0, 0 }, + { "mmHUBPREQ1_DCN_TTU_QOS_WM", REG_MMIO, 0x0660, 2, &mmHUBPREQ1_DCN_TTU_QOS_WM[0], sizeof(mmHUBPREQ1_DCN_TTU_QOS_WM)/sizeof(mmHUBPREQ1_DCN_TTU_QOS_WM[0]), 0, 0 }, + { "mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL", REG_MMIO, 0x0661, 2, &mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL[0], sizeof(mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL)/sizeof(mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL[0]), 0, 0 }, + { "mmHUBPREQ1_DCN_SURF0_TTU_CNTL0", REG_MMIO, 0x0662, 2, &mmHUBPREQ1_DCN_SURF0_TTU_CNTL0[0], sizeof(mmHUBPREQ1_DCN_SURF0_TTU_CNTL0)/sizeof(mmHUBPREQ1_DCN_SURF0_TTU_CNTL0[0]), 0, 0 }, + { "mmHUBPREQ1_DCN_SURF0_TTU_CNTL1", REG_MMIO, 0x0663, 2, &mmHUBPREQ1_DCN_SURF0_TTU_CNTL1[0], sizeof(mmHUBPREQ1_DCN_SURF0_TTU_CNTL1)/sizeof(mmHUBPREQ1_DCN_SURF0_TTU_CNTL1[0]), 0, 0 }, + { "mmHUBPREQ1_DCN_SURF1_TTU_CNTL0", REG_MMIO, 0x0664, 2, &mmHUBPREQ1_DCN_SURF1_TTU_CNTL0[0], sizeof(mmHUBPREQ1_DCN_SURF1_TTU_CNTL0)/sizeof(mmHUBPREQ1_DCN_SURF1_TTU_CNTL0[0]), 0, 0 }, + { "mmHUBPREQ1_DCN_SURF1_TTU_CNTL1", REG_MMIO, 0x0665, 2, &mmHUBPREQ1_DCN_SURF1_TTU_CNTL1[0], sizeof(mmHUBPREQ1_DCN_SURF1_TTU_CNTL1)/sizeof(mmHUBPREQ1_DCN_SURF1_TTU_CNTL1[0]), 0, 0 }, + { "mmHUBPREQ1_DCN_CUR0_TTU_CNTL0", REG_MMIO, 0x0666, 2, &mmHUBPREQ1_DCN_CUR0_TTU_CNTL0[0], sizeof(mmHUBPREQ1_DCN_CUR0_TTU_CNTL0)/sizeof(mmHUBPREQ1_DCN_CUR0_TTU_CNTL0[0]), 0, 0 }, + { "mmHUBPREQ1_DCN_CUR0_TTU_CNTL1", REG_MMIO, 0x0667, 2, &mmHUBPREQ1_DCN_CUR0_TTU_CNTL1[0], sizeof(mmHUBPREQ1_DCN_CUR0_TTU_CNTL1)/sizeof(mmHUBPREQ1_DCN_CUR0_TTU_CNTL1[0]), 0, 0 }, + { "mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB", REG_MMIO, 0x0668, 2, &mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB[0], sizeof(mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB)/sizeof(mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB[0]), 0, 0 }, + { "mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB", REG_MMIO, 0x0669, 2, &mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB[0], sizeof(mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB)/sizeof(mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB[0]), 0, 0 }, + { "mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB", REG_MMIO, 0x066a, 2, &mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB[0], sizeof(mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB)/sizeof(mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB[0]), 0, 0 }, + { "mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB", REG_MMIO, 0x066b, 2, &mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB[0], sizeof(mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB)/sizeof(mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB[0]), 0, 0 }, + { "mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB", REG_MMIO, 0x066c, 2, &mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB[0], sizeof(mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB)/sizeof(mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB[0]), 0, 0 }, + { "mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB", REG_MMIO, 0x066d, 2, &mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB[0], sizeof(mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB)/sizeof(mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB[0]), 0, 0 }, + { "mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB", REG_MMIO, 0x066e, 2, &mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB[0], sizeof(mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB)/sizeof(mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB[0]), 0, 0 }, + { "mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB", REG_MMIO, 0x066f, 2, &mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB[0], sizeof(mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB)/sizeof(mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB[0]), 0, 0 }, + { "mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB", REG_MMIO, 0x0670, 2, &mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB[0], sizeof(mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB)/sizeof(mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB[0]), 0, 0 }, + { "mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB", REG_MMIO, 0x0671, 2, &mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB[0], sizeof(mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB)/sizeof(mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB[0]), 0, 0 }, + { "mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB", REG_MMIO, 0x0672, 2, &mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB[0], sizeof(mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB)/sizeof(mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB[0]), 0, 0 }, + { "mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB", REG_MMIO, 0x0673, 2, &mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB[0], sizeof(mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB)/sizeof(mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB[0]), 0, 0 }, + { "mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB", REG_MMIO, 0x0674, 2, &mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB[0], sizeof(mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB)/sizeof(mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB[0]), 0, 0 }, + { "mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB", REG_MMIO, 0x0675, 2, &mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB[0], sizeof(mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB)/sizeof(mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB[0]), 0, 0 }, + { "mmHUBPREQ1_DCN_VM_CONTEXT0_STATUS", REG_MMIO, 0x0676, 2, &mmHUBPREQ1_DCN_VM_CONTEXT0_STATUS[0], sizeof(mmHUBPREQ1_DCN_VM_CONTEXT0_STATUS)/sizeof(mmHUBPREQ1_DCN_VM_CONTEXT0_STATUS[0]), 0, 0 }, + { "mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB", REG_MMIO, 0x0677, 2, &mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB[0], sizeof(mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB)/sizeof(mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB[0]), 0, 0 }, + { "mmHUBPREQ1_DCN_VM_CONTEXT0_CNTL", REG_MMIO, 0x0678, 2, &mmHUBPREQ1_DCN_VM_CONTEXT0_CNTL[0], sizeof(mmHUBPREQ1_DCN_VM_CONTEXT0_CNTL)/sizeof(mmHUBPREQ1_DCN_VM_CONTEXT0_CNTL[0]), 0, 0 }, + { "mmHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL", REG_MMIO, 0x0679, 2, &mmHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL[0], sizeof(mmHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL)/sizeof(mmHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL[0]), 0, 0 }, + { "mmHUBPREQ1_BLANK_OFFSET_0", REG_MMIO, 0x067a, 2, &mmHUBPREQ1_BLANK_OFFSET_0[0], sizeof(mmHUBPREQ1_BLANK_OFFSET_0)/sizeof(mmHUBPREQ1_BLANK_OFFSET_0[0]), 0, 0 }, + { "mmHUBPREQ1_BLANK_OFFSET_1", REG_MMIO, 0x067b, 2, &mmHUBPREQ1_BLANK_OFFSET_1[0], sizeof(mmHUBPREQ1_BLANK_OFFSET_1)/sizeof(mmHUBPREQ1_BLANK_OFFSET_1[0]), 0, 0 }, + { "mmHUBPREQ1_DST_DIMENSIONS", REG_MMIO, 0x067c, 2, &mmHUBPREQ1_DST_DIMENSIONS[0], sizeof(mmHUBPREQ1_DST_DIMENSIONS)/sizeof(mmHUBPREQ1_DST_DIMENSIONS[0]), 0, 0 }, + { "mmHUBPREQ1_DST_AFTER_SCALER", REG_MMIO, 0x067d, 2, &mmHUBPREQ1_DST_AFTER_SCALER[0], sizeof(mmHUBPREQ1_DST_AFTER_SCALER)/sizeof(mmHUBPREQ1_DST_AFTER_SCALER[0]), 0, 0 }, + { "mmHUBPREQ1_PREFETCH_SETTINS", REG_MMIO, 0x067e, 2, &mmHUBPREQ1_PREFETCH_SETTINS[0], sizeof(mmHUBPREQ1_PREFETCH_SETTINS)/sizeof(mmHUBPREQ1_PREFETCH_SETTINS[0]), 0, 0 }, + { "mmHUBPREQ1_PREFETCH_SETTINS_C", REG_MMIO, 0x067f, 2, &mmHUBPREQ1_PREFETCH_SETTINS_C[0], sizeof(mmHUBPREQ1_PREFETCH_SETTINS_C)/sizeof(mmHUBPREQ1_PREFETCH_SETTINS_C[0]), 0, 0 }, + { "mmHUBPREQ1_VBLANK_PARAMETERS_0", REG_MMIO, 0x0680, 2, &mmHUBPREQ1_VBLANK_PARAMETERS_0[0], sizeof(mmHUBPREQ1_VBLANK_PARAMETERS_0)/sizeof(mmHUBPREQ1_VBLANK_PARAMETERS_0[0]), 0, 0 }, + { "mmHUBPREQ1_VBLANK_PARAMETERS_1", REG_MMIO, 0x0681, 2, &mmHUBPREQ1_VBLANK_PARAMETERS_1[0], sizeof(mmHUBPREQ1_VBLANK_PARAMETERS_1)/sizeof(mmHUBPREQ1_VBLANK_PARAMETERS_1[0]), 0, 0 }, + { "mmHUBPREQ1_VBLANK_PARAMETERS_2", REG_MMIO, 0x0682, 2, &mmHUBPREQ1_VBLANK_PARAMETERS_2[0], sizeof(mmHUBPREQ1_VBLANK_PARAMETERS_2)/sizeof(mmHUBPREQ1_VBLANK_PARAMETERS_2[0]), 0, 0 }, + { "mmHUBPREQ1_VBLANK_PARAMETERS_3", REG_MMIO, 0x0683, 2, &mmHUBPREQ1_VBLANK_PARAMETERS_3[0], sizeof(mmHUBPREQ1_VBLANK_PARAMETERS_3)/sizeof(mmHUBPREQ1_VBLANK_PARAMETERS_3[0]), 0, 0 }, + { "mmHUBPREQ1_VBLANK_PARAMETERS_4", REG_MMIO, 0x0684, 2, &mmHUBPREQ1_VBLANK_PARAMETERS_4[0], sizeof(mmHUBPREQ1_VBLANK_PARAMETERS_4)/sizeof(mmHUBPREQ1_VBLANK_PARAMETERS_4[0]), 0, 0 }, + { "mmHUBPREQ1_NOM_PARAMETERS_0", REG_MMIO, 0x0685, 2, &mmHUBPREQ1_NOM_PARAMETERS_0[0], sizeof(mmHUBPREQ1_NOM_PARAMETERS_0)/sizeof(mmHUBPREQ1_NOM_PARAMETERS_0[0]), 0, 0 }, + { "mmHUBPREQ1_NOM_PARAMETERS_1", REG_MMIO, 0x0686, 2, &mmHUBPREQ1_NOM_PARAMETERS_1[0], sizeof(mmHUBPREQ1_NOM_PARAMETERS_1)/sizeof(mmHUBPREQ1_NOM_PARAMETERS_1[0]), 0, 0 }, + { "mmHUBPREQ1_NOM_PARAMETERS_2", REG_MMIO, 0x0687, 2, &mmHUBPREQ1_NOM_PARAMETERS_2[0], sizeof(mmHUBPREQ1_NOM_PARAMETERS_2)/sizeof(mmHUBPREQ1_NOM_PARAMETERS_2[0]), 0, 0 }, + { "mmHUBPREQ1_NOM_PARAMETERS_3", REG_MMIO, 0x0688, 2, &mmHUBPREQ1_NOM_PARAMETERS_3[0], sizeof(mmHUBPREQ1_NOM_PARAMETERS_3)/sizeof(mmHUBPREQ1_NOM_PARAMETERS_3[0]), 0, 0 }, + { "mmHUBPREQ1_NOM_PARAMETERS_4", REG_MMIO, 0x0689, 2, &mmHUBPREQ1_NOM_PARAMETERS_4[0], sizeof(mmHUBPREQ1_NOM_PARAMETERS_4)/sizeof(mmHUBPREQ1_NOM_PARAMETERS_4[0]), 0, 0 }, + { "mmHUBPREQ1_NOM_PARAMETERS_5", REG_MMIO, 0x068a, 2, &mmHUBPREQ1_NOM_PARAMETERS_5[0], sizeof(mmHUBPREQ1_NOM_PARAMETERS_5)/sizeof(mmHUBPREQ1_NOM_PARAMETERS_5[0]), 0, 0 }, + { "mmHUBPREQ1_NOM_PARAMETERS_6", REG_MMIO, 0x068b, 2, &mmHUBPREQ1_NOM_PARAMETERS_6[0], sizeof(mmHUBPREQ1_NOM_PARAMETERS_6)/sizeof(mmHUBPREQ1_NOM_PARAMETERS_6[0]), 0, 0 }, + { "mmHUBPREQ1_NOM_PARAMETERS_7", REG_MMIO, 0x068c, 2, &mmHUBPREQ1_NOM_PARAMETERS_7[0], sizeof(mmHUBPREQ1_NOM_PARAMETERS_7)/sizeof(mmHUBPREQ1_NOM_PARAMETERS_7[0]), 0, 0 }, + { "mmHUBPREQ1_PER_LINE_DELIVERY_PRE", REG_MMIO, 0x068d, 2, &mmHUBPREQ1_PER_LINE_DELIVERY_PRE[0], sizeof(mmHUBPREQ1_PER_LINE_DELIVERY_PRE)/sizeof(mmHUBPREQ1_PER_LINE_DELIVERY_PRE[0]), 0, 0 }, + { "mmHUBPREQ1_PER_LINE_DELIVERY", REG_MMIO, 0x068e, 2, &mmHUBPREQ1_PER_LINE_DELIVERY[0], sizeof(mmHUBPREQ1_PER_LINE_DELIVERY)/sizeof(mmHUBPREQ1_PER_LINE_DELIVERY[0]), 0, 0 }, + { "mmHUBPREQ1_CURSOR_SETTINS", REG_MMIO, 0x068f, 2, &mmHUBPREQ1_CURSOR_SETTINS[0], sizeof(mmHUBPREQ1_CURSOR_SETTINS)/sizeof(mmHUBPREQ1_CURSOR_SETTINS[0]), 0, 0 }, + { "mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ", REG_MMIO, 0x0690, 2, &mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ[0], sizeof(mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ)/sizeof(mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ[0]), 0, 0 }, + { "mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL", REG_MMIO, 0x0691, 2, &mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL[0], sizeof(mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL)/sizeof(mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL[0]), 0, 0 }, + { "mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS", REG_MMIO, 0x0692, 2, &mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS[0], sizeof(mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS)/sizeof(mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS[0]), 0, 0 }, + { "mmHUBPRET1_HUBPRET_CONTROL", REG_MMIO, 0x06a4, 2, &mmHUBPRET1_HUBPRET_CONTROL[0], sizeof(mmHUBPRET1_HUBPRET_CONTROL)/sizeof(mmHUBPRET1_HUBPRET_CONTROL[0]), 0, 0 }, + { "mmHUBPRET1_HUBPRET_MEM_PWR_CTRL", REG_MMIO, 0x06a5, 2, &mmHUBPRET1_HUBPRET_MEM_PWR_CTRL[0], sizeof(mmHUBPRET1_HUBPRET_MEM_PWR_CTRL)/sizeof(mmHUBPRET1_HUBPRET_MEM_PWR_CTRL[0]), 0, 0 }, + { "mmHUBPRET1_HUBPRET_MEM_PWR_STATUS", REG_MMIO, 0x06a6, 2, &mmHUBPRET1_HUBPRET_MEM_PWR_STATUS[0], sizeof(mmHUBPRET1_HUBPRET_MEM_PWR_STATUS)/sizeof(mmHUBPRET1_HUBPRET_MEM_PWR_STATUS[0]), 0, 0 }, + { "mmHUBPRET1_HUBPRET_READ_LINE_CTRL0", REG_MMIO, 0x06a7, 2, &mmHUBPRET1_HUBPRET_READ_LINE_CTRL0[0], sizeof(mmHUBPRET1_HUBPRET_READ_LINE_CTRL0)/sizeof(mmHUBPRET1_HUBPRET_READ_LINE_CTRL0[0]), 0, 0 }, + { "mmHUBPRET1_HUBPRET_READ_LINE_CTRL1", REG_MMIO, 0x06a8, 2, &mmHUBPRET1_HUBPRET_READ_LINE_CTRL1[0], sizeof(mmHUBPRET1_HUBPRET_READ_LINE_CTRL1)/sizeof(mmHUBPRET1_HUBPRET_READ_LINE_CTRL1[0]), 0, 0 }, + { "mmHUBPRET1_HUBPRET_READ_LINE0", REG_MMIO, 0x06a9, 2, &mmHUBPRET1_HUBPRET_READ_LINE0[0], sizeof(mmHUBPRET1_HUBPRET_READ_LINE0)/sizeof(mmHUBPRET1_HUBPRET_READ_LINE0[0]), 0, 0 }, + { "mmHUBPRET1_HUBPRET_READ_LINE1", REG_MMIO, 0x06aa, 2, &mmHUBPRET1_HUBPRET_READ_LINE1[0], sizeof(mmHUBPRET1_HUBPRET_READ_LINE1)/sizeof(mmHUBPRET1_HUBPRET_READ_LINE1[0]), 0, 0 }, + { "mmHUBPRET1_HUBPRET_INTERRUPT", REG_MMIO, 0x06ab, 2, &mmHUBPRET1_HUBPRET_INTERRUPT[0], sizeof(mmHUBPRET1_HUBPRET_INTERRUPT)/sizeof(mmHUBPRET1_HUBPRET_INTERRUPT[0]), 0, 0 }, + { "mmHUBPRET1_HUBPRET_READ_LINE_VALUE", REG_MMIO, 0x06ac, 2, &mmHUBPRET1_HUBPRET_READ_LINE_VALUE[0], sizeof(mmHUBPRET1_HUBPRET_READ_LINE_VALUE)/sizeof(mmHUBPRET1_HUBPRET_READ_LINE_VALUE[0]), 0, 0 }, + { "mmHUBPRET1_HUBPRET_READ_LINE_STATUS", REG_MMIO, 0x06ad, 2, &mmHUBPRET1_HUBPRET_READ_LINE_STATUS[0], sizeof(mmHUBPRET1_HUBPRET_READ_LINE_STATUS)/sizeof(mmHUBPRET1_HUBPRET_READ_LINE_STATUS[0]), 0, 0 }, + { "mmCURSOR1_CURSOR_CONTROL", REG_MMIO, 0x06b0, 2, &mmCURSOR1_CURSOR_CONTROL[0], sizeof(mmCURSOR1_CURSOR_CONTROL)/sizeof(mmCURSOR1_CURSOR_CONTROL[0]), 0, 0 }, + { "mmCURSOR1_CURSOR_SURFACE_ADDRESS", REG_MMIO, 0x06b1, 2, &mmCURSOR1_CURSOR_SURFACE_ADDRESS[0], sizeof(mmCURSOR1_CURSOR_SURFACE_ADDRESS)/sizeof(mmCURSOR1_CURSOR_SURFACE_ADDRESS[0]), 0, 0 }, + { "mmCURSOR1_CURSOR_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x06b2, 2, &mmCURSOR1_CURSOR_SURFACE_ADDRESS_HIGH[0], sizeof(mmCURSOR1_CURSOR_SURFACE_ADDRESS_HIGH)/sizeof(mmCURSOR1_CURSOR_SURFACE_ADDRESS_HIGH[0]), 0, 0 }, + { "mmCURSOR1_CURSOR_SIZE", REG_MMIO, 0x06b3, 2, &mmCURSOR1_CURSOR_SIZE[0], sizeof(mmCURSOR1_CURSOR_SIZE)/sizeof(mmCURSOR1_CURSOR_SIZE[0]), 0, 0 }, + { "mmCURSOR1_CURSOR_POSITION", REG_MMIO, 0x06b4, 2, &mmCURSOR1_CURSOR_POSITION[0], sizeof(mmCURSOR1_CURSOR_POSITION)/sizeof(mmCURSOR1_CURSOR_POSITION[0]), 0, 0 }, + { "mmCURSOR1_CURSOR_HOT_SPOT", REG_MMIO, 0x06b5, 2, &mmCURSOR1_CURSOR_HOT_SPOT[0], sizeof(mmCURSOR1_CURSOR_HOT_SPOT)/sizeof(mmCURSOR1_CURSOR_HOT_SPOT[0]), 0, 0 }, + { "mmCURSOR1_CURSOR_STEREO_CONTROL", REG_MMIO, 0x06b6, 2, &mmCURSOR1_CURSOR_STEREO_CONTROL[0], sizeof(mmCURSOR1_CURSOR_STEREO_CONTROL)/sizeof(mmCURSOR1_CURSOR_STEREO_CONTROL[0]), 0, 0 }, + { "mmCURSOR1_CURSOR_DST_OFFSET", REG_MMIO, 0x06b7, 2, &mmCURSOR1_CURSOR_DST_OFFSET[0], sizeof(mmCURSOR1_CURSOR_DST_OFFSET)/sizeof(mmCURSOR1_CURSOR_DST_OFFSET[0]), 0, 0 }, + { "mmCURSOR1_CURSOR_MEM_PWR_CTRL", REG_MMIO, 0x06b8, 2, &mmCURSOR1_CURSOR_MEM_PWR_CTRL[0], sizeof(mmCURSOR1_CURSOR_MEM_PWR_CTRL)/sizeof(mmCURSOR1_CURSOR_MEM_PWR_CTRL[0]), 0, 0 }, + { "mmCURSOR1_CURSOR_MEM_PWR_STATUS", REG_MMIO, 0x06b9, 2, &mmCURSOR1_CURSOR_MEM_PWR_STATUS[0], sizeof(mmCURSOR1_CURSOR_MEM_PWR_STATUS)/sizeof(mmCURSOR1_CURSOR_MEM_PWR_STATUS[0]), 0, 0 }, + { "mmDC_PERFMON9_PERFCOUNTER_CNTL", REG_MMIO, 0x06d5, 2, &mmDC_PERFMON9_PERFCOUNTER_CNTL[0], sizeof(mmDC_PERFMON9_PERFCOUNTER_CNTL)/sizeof(mmDC_PERFMON9_PERFCOUNTER_CNTL[0]), 0, 0 }, + { "mmDC_PERFMON9_PERFCOUNTER_CNTL2", REG_MMIO, 0x06d6, 2, &mmDC_PERFMON9_PERFCOUNTER_CNTL2[0], sizeof(mmDC_PERFMON9_PERFCOUNTER_CNTL2)/sizeof(mmDC_PERFMON9_PERFCOUNTER_CNTL2[0]), 0, 0 }, + { "mmDC_PERFMON9_PERFCOUNTER_STATE", REG_MMIO, 0x06d7, 2, &mmDC_PERFMON9_PERFCOUNTER_STATE[0], sizeof(mmDC_PERFMON9_PERFCOUNTER_STATE)/sizeof(mmDC_PERFMON9_PERFCOUNTER_STATE[0]), 0, 0 }, + { "mmDC_PERFMON9_PERFMON_CNTL", REG_MMIO, 0x06d8, 2, &mmDC_PERFMON9_PERFMON_CNTL[0], sizeof(mmDC_PERFMON9_PERFMON_CNTL)/sizeof(mmDC_PERFMON9_PERFMON_CNTL[0]), 0, 0 }, + { "mmDC_PERFMON9_PERFMON_CNTL2", REG_MMIO, 0x06d9, 2, &mmDC_PERFMON9_PERFMON_CNTL2[0], sizeof(mmDC_PERFMON9_PERFMON_CNTL2)/sizeof(mmDC_PERFMON9_PERFMON_CNTL2[0]), 0, 0 }, + { "mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC", REG_MMIO, 0x06da, 2, &mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC[0], sizeof(mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC)/sizeof(mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC[0]), 0, 0 }, + { "mmDC_PERFMON9_PERFMON_CVALUE_LOW", REG_MMIO, 0x06db, 2, &mmDC_PERFMON9_PERFMON_CVALUE_LOW[0], sizeof(mmDC_PERFMON9_PERFMON_CVALUE_LOW)/sizeof(mmDC_PERFMON9_PERFMON_CVALUE_LOW[0]), 0, 0 }, + { "mmDC_PERFMON9_PERFMON_HI", REG_MMIO, 0x06dc, 2, &mmDC_PERFMON9_PERFMON_HI[0], sizeof(mmDC_PERFMON9_PERFMON_HI)/sizeof(mmDC_PERFMON9_PERFMON_HI[0]), 0, 0 }, + { "mmDC_PERFMON9_PERFMON_LOW", REG_MMIO, 0x06dd, 2, &mmDC_PERFMON9_PERFMON_LOW[0], sizeof(mmDC_PERFMON9_PERFMON_LOW)/sizeof(mmDC_PERFMON9_PERFMON_LOW[0]), 0, 0 }, + { "mmHUBP2_DCSURF_SURFACE_CONFIG", REG_MMIO, 0x06e1, 2, &mmHUBP2_DCSURF_SURFACE_CONFIG[0], sizeof(mmHUBP2_DCSURF_SURFACE_CONFIG)/sizeof(mmHUBP2_DCSURF_SURFACE_CONFIG[0]), 0, 0 }, + { "mmHUBP2_DCSURF_ADDR_CONFIG", REG_MMIO, 0x06e2, 2, &mmHUBP2_DCSURF_ADDR_CONFIG[0], sizeof(mmHUBP2_DCSURF_ADDR_CONFIG)/sizeof(mmHUBP2_DCSURF_ADDR_CONFIG[0]), 0, 0 }, + { "mmHUBP2_DCSURF_TILING_CONFIG", REG_MMIO, 0x06e3, 2, &mmHUBP2_DCSURF_TILING_CONFIG[0], sizeof(mmHUBP2_DCSURF_TILING_CONFIG)/sizeof(mmHUBP2_DCSURF_TILING_CONFIG[0]), 0, 0 }, + { "mmHUBP2_DCSURF_PRI_VIEWPORT_START", REG_MMIO, 0x06e4, 2, &mmHUBP2_DCSURF_PRI_VIEWPORT_START[0], sizeof(mmHUBP2_DCSURF_PRI_VIEWPORT_START)/sizeof(mmHUBP2_DCSURF_PRI_VIEWPORT_START[0]), 0, 0 }, + { "mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION", REG_MMIO, 0x06e5, 2, &mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION[0], sizeof(mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION)/sizeof(mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION[0]), 0, 0 }, + { "mmHUBP2_DCSURF_PRI_VIEWPORT_START_C", REG_MMIO, 0x06e6, 2, &mmHUBP2_DCSURF_PRI_VIEWPORT_START_C[0], sizeof(mmHUBP2_DCSURF_PRI_VIEWPORT_START_C)/sizeof(mmHUBP2_DCSURF_PRI_VIEWPORT_START_C[0]), 0, 0 }, + { "mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C", REG_MMIO, 0x06e7, 2, &mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C[0], sizeof(mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C)/sizeof(mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C[0]), 0, 0 }, + { "mmHUBP2_DCSURF_SEC_VIEWPORT_START", REG_MMIO, 0x06e8, 2, &mmHUBP2_DCSURF_SEC_VIEWPORT_START[0], sizeof(mmHUBP2_DCSURF_SEC_VIEWPORT_START)/sizeof(mmHUBP2_DCSURF_SEC_VIEWPORT_START[0]), 0, 0 }, + { "mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION", REG_MMIO, 0x06e9, 2, &mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION[0], sizeof(mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION)/sizeof(mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION[0]), 0, 0 }, + { "mmHUBP2_DCSURF_SEC_VIEWPORT_START_C", REG_MMIO, 0x06ea, 2, &mmHUBP2_DCSURF_SEC_VIEWPORT_START_C[0], sizeof(mmHUBP2_DCSURF_SEC_VIEWPORT_START_C)/sizeof(mmHUBP2_DCSURF_SEC_VIEWPORT_START_C[0]), 0, 0 }, + { "mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C", REG_MMIO, 0x06eb, 2, &mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C[0], sizeof(mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C)/sizeof(mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C[0]), 0, 0 }, + { "mmHUBP2_DCHUBP_REQ_SIZE_CONFIG", REG_MMIO, 0x06ec, 2, &mmHUBP2_DCHUBP_REQ_SIZE_CONFIG[0], sizeof(mmHUBP2_DCHUBP_REQ_SIZE_CONFIG)/sizeof(mmHUBP2_DCHUBP_REQ_SIZE_CONFIG[0]), 0, 0 }, + { "mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_C", REG_MMIO, 0x06ed, 2, &mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_C[0], sizeof(mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_C)/sizeof(mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_C[0]), 0, 0 }, + { "mmHUBP2_DCHUBP_CNTL", REG_MMIO, 0x06ee, 2, &mmHUBP2_DCHUBP_CNTL[0], sizeof(mmHUBP2_DCHUBP_CNTL)/sizeof(mmHUBP2_DCHUBP_CNTL[0]), 0, 0 }, + { "mmHUBP2_HUBP_CLK_CNTL", REG_MMIO, 0x06ef, 2, &mmHUBP2_HUBP_CLK_CNTL[0], sizeof(mmHUBP2_HUBP_CLK_CNTL)/sizeof(mmHUBP2_HUBP_CLK_CNTL[0]), 0, 0 }, + { "mmHUBP2_DCHUBP_VMPG_CONFIG", REG_MMIO, 0x06f0, 2, &mmHUBP2_DCHUBP_VMPG_CONFIG[0], sizeof(mmHUBP2_DCHUBP_VMPG_CONFIG)/sizeof(mmHUBP2_DCHUBP_VMPG_CONFIG[0]), 0, 0 }, + { "mmHUBP2_HUBPREQ_DEBUG_DB", REG_MMIO, 0x06f1, 2, &mmHUBP2_HUBPREQ_DEBUG_DB[0], sizeof(mmHUBP2_HUBPREQ_DEBUG_DB)/sizeof(mmHUBP2_HUBPREQ_DEBUG_DB[0]), 0, 0 }, + { "mmHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK", REG_MMIO, 0x06f6, 2, &mmHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK[0], sizeof(mmHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK)/sizeof(mmHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK[0]), 0, 0 }, + { "mmHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK", REG_MMIO, 0x06f7, 2, &mmHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK[0], sizeof(mmHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK)/sizeof(mmHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK[0]), 0, 0 }, + { "mmHUBPREQ2_DCSURF_SURFACE_PITCH", REG_MMIO, 0x0703, 2, &mmHUBPREQ2_DCSURF_SURFACE_PITCH[0], sizeof(mmHUBPREQ2_DCSURF_SURFACE_PITCH)/sizeof(mmHUBPREQ2_DCSURF_SURFACE_PITCH[0]), 0, 0 }, + { "mmHUBPREQ2_DCSURF_SURFACE_PITCH_C", REG_MMIO, 0x0704, 2, &mmHUBPREQ2_DCSURF_SURFACE_PITCH_C[0], sizeof(mmHUBPREQ2_DCSURF_SURFACE_PITCH_C)/sizeof(mmHUBPREQ2_DCSURF_SURFACE_PITCH_C[0]), 0, 0 }, + { "mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS", REG_MMIO, 0x0705, 2, &mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS[0], sizeof(mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS)/sizeof(mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS[0]), 0, 0 }, + { "mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x0706, 2, &mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH[0], sizeof(mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH)/sizeof(mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH[0]), 0, 0 }, + { "mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C", REG_MMIO, 0x0707, 2, &mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C[0], sizeof(mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C)/sizeof(mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C[0]), 0, 0 }, + { "mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C", REG_MMIO, 0x0708, 2, &mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C[0], sizeof(mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C)/sizeof(mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C[0]), 0, 0 }, + { "mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS", REG_MMIO, 0x0709, 2, &mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS[0], sizeof(mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS)/sizeof(mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS[0]), 0, 0 }, + { "mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x070a, 2, &mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH[0], sizeof(mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH)/sizeof(mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH[0]), 0, 0 }, + { "mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C", REG_MMIO, 0x070b, 2, &mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C[0], sizeof(mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C)/sizeof(mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C[0]), 0, 0 }, + { "mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C", REG_MMIO, 0x070c, 2, &mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C[0], sizeof(mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C)/sizeof(mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C[0]), 0, 0 }, + { "mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS", REG_MMIO, 0x070d, 2, &mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS[0], sizeof(mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS)/sizeof(mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS[0]), 0, 0 }, + { "mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x070e, 2, &mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH[0], sizeof(mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH)/sizeof(mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH[0]), 0, 0 }, + { "mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C", REG_MMIO, 0x070f, 2, &mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C[0], sizeof(mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C)/sizeof(mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C[0]), 0, 0 }, + { "mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C", REG_MMIO, 0x0710, 2, &mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C[0], sizeof(mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C)/sizeof(mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C[0]), 0, 0 }, + { "mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS", REG_MMIO, 0x0711, 2, &mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS[0], sizeof(mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS)/sizeof(mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS[0]), 0, 0 }, + { "mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x0712, 2, &mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH[0], sizeof(mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH)/sizeof(mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH[0]), 0, 0 }, + { "mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C", REG_MMIO, 0x0713, 2, &mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C[0], sizeof(mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C)/sizeof(mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C[0]), 0, 0 }, + { "mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C", REG_MMIO, 0x0714, 2, &mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C[0], sizeof(mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C)/sizeof(mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C[0]), 0, 0 }, + { "mmHUBPREQ2_DCSURF_SURFACE_CONTROL", REG_MMIO, 0x0715, 2, &mmHUBPREQ2_DCSURF_SURFACE_CONTROL[0], sizeof(mmHUBPREQ2_DCSURF_SURFACE_CONTROL)/sizeof(mmHUBPREQ2_DCSURF_SURFACE_CONTROL[0]), 0, 0 }, + { "mmHUBPREQ2_DCSURF_FLIP_CONTROL", REG_MMIO, 0x0716, 2, &mmHUBPREQ2_DCSURF_FLIP_CONTROL[0], sizeof(mmHUBPREQ2_DCSURF_FLIP_CONTROL)/sizeof(mmHUBPREQ2_DCSURF_FLIP_CONTROL[0]), 0, 0 }, + { "mmHUBPREQ2_DCSURF_FLIP_CONTROL2", REG_MMIO, 0x0717, 2, &mmHUBPREQ2_DCSURF_FLIP_CONTROL2[0], sizeof(mmHUBPREQ2_DCSURF_FLIP_CONTROL2)/sizeof(mmHUBPREQ2_DCSURF_FLIP_CONTROL2[0]), 0, 0 }, + { "mmHUBPREQ2_DCSURF_FRAME_PACING_CONTROL", REG_MMIO, 0x0718, 2, &mmHUBPREQ2_DCSURF_FRAME_PACING_CONTROL[0], sizeof(mmHUBPREQ2_DCSURF_FRAME_PACING_CONTROL)/sizeof(mmHUBPREQ2_DCSURF_FRAME_PACING_CONTROL[0]), 0, 0 }, + { "mmHUBPREQ2_DCSURF_FRAME_PACING_TIME", REG_MMIO, 0x0719, 2, &mmHUBPREQ2_DCSURF_FRAME_PACING_TIME[0], sizeof(mmHUBPREQ2_DCSURF_FRAME_PACING_TIME)/sizeof(mmHUBPREQ2_DCSURF_FRAME_PACING_TIME[0]), 0, 0 }, + { "mmHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT", REG_MMIO, 0x071a, 2, &mmHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT[0], sizeof(mmHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT)/sizeof(mmHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT[0]), 0, 0 }, + { "mmHUBPREQ2_DCSURF_SURFACE_INUSE", REG_MMIO, 0x071b, 2, &mmHUBPREQ2_DCSURF_SURFACE_INUSE[0], sizeof(mmHUBPREQ2_DCSURF_SURFACE_INUSE)/sizeof(mmHUBPREQ2_DCSURF_SURFACE_INUSE[0]), 0, 0 }, + { "mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH", REG_MMIO, 0x071c, 2, &mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH[0], sizeof(mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH)/sizeof(mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH[0]), 0, 0 }, + { "mmHUBPREQ2_DCSURF_SURFACE_INUSE_C", REG_MMIO, 0x071d, 2, &mmHUBPREQ2_DCSURF_SURFACE_INUSE_C[0], sizeof(mmHUBPREQ2_DCSURF_SURFACE_INUSE_C)/sizeof(mmHUBPREQ2_DCSURF_SURFACE_INUSE_C[0]), 0, 0 }, + { "mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C", REG_MMIO, 0x071e, 2, &mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C[0], sizeof(mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C)/sizeof(mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C[0]), 0, 0 }, + { "mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE", REG_MMIO, 0x071f, 2, &mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE[0], sizeof(mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE)/sizeof(mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE[0]), 0, 0 }, + { "mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH", REG_MMIO, 0x0720, 2, &mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH[0], sizeof(mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH)/sizeof(mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH[0]), 0, 0 }, + { "mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C", REG_MMIO, 0x0721, 2, &mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C[0], sizeof(mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C)/sizeof(mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C[0]), 0, 0 }, + { "mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C", REG_MMIO, 0x0722, 2, &mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C[0], sizeof(mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C)/sizeof(mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C[0]), 0, 0 }, + { "mmHUBPREQ2_DCN_EXPANSION_MODE", REG_MMIO, 0x0723, 2, &mmHUBPREQ2_DCN_EXPANSION_MODE[0], sizeof(mmHUBPREQ2_DCN_EXPANSION_MODE)/sizeof(mmHUBPREQ2_DCN_EXPANSION_MODE[0]), 0, 0 }, + { "mmHUBPREQ2_DCN_TTU_QOS_WM", REG_MMIO, 0x0724, 2, &mmHUBPREQ2_DCN_TTU_QOS_WM[0], sizeof(mmHUBPREQ2_DCN_TTU_QOS_WM)/sizeof(mmHUBPREQ2_DCN_TTU_QOS_WM[0]), 0, 0 }, + { "mmHUBPREQ2_DCN_GLOBAL_TTU_CNTL", REG_MMIO, 0x0725, 2, &mmHUBPREQ2_DCN_GLOBAL_TTU_CNTL[0], sizeof(mmHUBPREQ2_DCN_GLOBAL_TTU_CNTL)/sizeof(mmHUBPREQ2_DCN_GLOBAL_TTU_CNTL[0]), 0, 0 }, + { "mmHUBPREQ2_DCN_SURF0_TTU_CNTL0", REG_MMIO, 0x0726, 2, &mmHUBPREQ2_DCN_SURF0_TTU_CNTL0[0], sizeof(mmHUBPREQ2_DCN_SURF0_TTU_CNTL0)/sizeof(mmHUBPREQ2_DCN_SURF0_TTU_CNTL0[0]), 0, 0 }, + { "mmHUBPREQ2_DCN_SURF0_TTU_CNTL1", REG_MMIO, 0x0727, 2, &mmHUBPREQ2_DCN_SURF0_TTU_CNTL1[0], sizeof(mmHUBPREQ2_DCN_SURF0_TTU_CNTL1)/sizeof(mmHUBPREQ2_DCN_SURF0_TTU_CNTL1[0]), 0, 0 }, + { "mmHUBPREQ2_DCN_SURF1_TTU_CNTL0", REG_MMIO, 0x0728, 2, &mmHUBPREQ2_DCN_SURF1_TTU_CNTL0[0], sizeof(mmHUBPREQ2_DCN_SURF1_TTU_CNTL0)/sizeof(mmHUBPREQ2_DCN_SURF1_TTU_CNTL0[0]), 0, 0 }, + { "mmHUBPREQ2_DCN_SURF1_TTU_CNTL1", REG_MMIO, 0x0729, 2, &mmHUBPREQ2_DCN_SURF1_TTU_CNTL1[0], sizeof(mmHUBPREQ2_DCN_SURF1_TTU_CNTL1)/sizeof(mmHUBPREQ2_DCN_SURF1_TTU_CNTL1[0]), 0, 0 }, + { "mmHUBPREQ2_DCN_CUR0_TTU_CNTL0", REG_MMIO, 0x072a, 2, &mmHUBPREQ2_DCN_CUR0_TTU_CNTL0[0], sizeof(mmHUBPREQ2_DCN_CUR0_TTU_CNTL0)/sizeof(mmHUBPREQ2_DCN_CUR0_TTU_CNTL0[0]), 0, 0 }, + { "mmHUBPREQ2_DCN_CUR0_TTU_CNTL1", REG_MMIO, 0x072b, 2, &mmHUBPREQ2_DCN_CUR0_TTU_CNTL1[0], sizeof(mmHUBPREQ2_DCN_CUR0_TTU_CNTL1)/sizeof(mmHUBPREQ2_DCN_CUR0_TTU_CNTL1[0]), 0, 0 }, + { "mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB", REG_MMIO, 0x072c, 2, &mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB[0], sizeof(mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB)/sizeof(mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB[0]), 0, 0 }, + { "mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB", REG_MMIO, 0x072d, 2, &mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB[0], sizeof(mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB)/sizeof(mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB[0]), 0, 0 }, + { "mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB", REG_MMIO, 0x072e, 2, &mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB[0], sizeof(mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB)/sizeof(mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB[0]), 0, 0 }, + { "mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB", REG_MMIO, 0x072f, 2, &mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB[0], sizeof(mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB)/sizeof(mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB[0]), 0, 0 }, + { "mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB", REG_MMIO, 0x0730, 2, &mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB[0], sizeof(mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB)/sizeof(mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB[0]), 0, 0 }, + { "mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB", REG_MMIO, 0x0731, 2, &mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB[0], sizeof(mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB)/sizeof(mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB[0]), 0, 0 }, + { "mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB", REG_MMIO, 0x0732, 2, &mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB[0], sizeof(mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB)/sizeof(mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB[0]), 0, 0 }, + { "mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB", REG_MMIO, 0x0733, 2, &mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB[0], sizeof(mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB)/sizeof(mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB[0]), 0, 0 }, + { "mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB", REG_MMIO, 0x0734, 2, &mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB[0], sizeof(mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB)/sizeof(mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB[0]), 0, 0 }, + { "mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB", REG_MMIO, 0x0735, 2, &mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB[0], sizeof(mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB)/sizeof(mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB[0]), 0, 0 }, + { "mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB", REG_MMIO, 0x0736, 2, &mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB[0], sizeof(mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB)/sizeof(mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB[0]), 0, 0 }, + { "mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB", REG_MMIO, 0x0737, 2, &mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB[0], sizeof(mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB)/sizeof(mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB[0]), 0, 0 }, + { "mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB", REG_MMIO, 0x0738, 2, &mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB[0], sizeof(mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB)/sizeof(mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB[0]), 0, 0 }, + { "mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB", REG_MMIO, 0x0739, 2, &mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB[0], sizeof(mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB)/sizeof(mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB[0]), 0, 0 }, + { "mmHUBPREQ2_DCN_VM_CONTEXT0_STATUS", REG_MMIO, 0x073a, 2, &mmHUBPREQ2_DCN_VM_CONTEXT0_STATUS[0], sizeof(mmHUBPREQ2_DCN_VM_CONTEXT0_STATUS)/sizeof(mmHUBPREQ2_DCN_VM_CONTEXT0_STATUS[0]), 0, 0 }, + { "mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB", REG_MMIO, 0x073b, 2, &mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB[0], sizeof(mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB)/sizeof(mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB[0]), 0, 0 }, + { "mmHUBPREQ2_DCN_VM_CONTEXT0_CNTL", REG_MMIO, 0x073c, 2, &mmHUBPREQ2_DCN_VM_CONTEXT0_CNTL[0], sizeof(mmHUBPREQ2_DCN_VM_CONTEXT0_CNTL)/sizeof(mmHUBPREQ2_DCN_VM_CONTEXT0_CNTL[0]), 0, 0 }, + { "mmHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL", REG_MMIO, 0x073d, 2, &mmHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL[0], sizeof(mmHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL)/sizeof(mmHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL[0]), 0, 0 }, + { "mmHUBPREQ2_BLANK_OFFSET_0", REG_MMIO, 0x073e, 2, &mmHUBPREQ2_BLANK_OFFSET_0[0], sizeof(mmHUBPREQ2_BLANK_OFFSET_0)/sizeof(mmHUBPREQ2_BLANK_OFFSET_0[0]), 0, 0 }, + { "mmHUBPREQ2_BLANK_OFFSET_1", REG_MMIO, 0x073f, 2, &mmHUBPREQ2_BLANK_OFFSET_1[0], sizeof(mmHUBPREQ2_BLANK_OFFSET_1)/sizeof(mmHUBPREQ2_BLANK_OFFSET_1[0]), 0, 0 }, + { "mmHUBPREQ2_DST_DIMENSIONS", REG_MMIO, 0x0740, 2, &mmHUBPREQ2_DST_DIMENSIONS[0], sizeof(mmHUBPREQ2_DST_DIMENSIONS)/sizeof(mmHUBPREQ2_DST_DIMENSIONS[0]), 0, 0 }, + { "mmHUBPREQ2_DST_AFTER_SCALER", REG_MMIO, 0x0741, 2, &mmHUBPREQ2_DST_AFTER_SCALER[0], sizeof(mmHUBPREQ2_DST_AFTER_SCALER)/sizeof(mmHUBPREQ2_DST_AFTER_SCALER[0]), 0, 0 }, + { "mmHUBPREQ2_PREFETCH_SETTINS", REG_MMIO, 0x0742, 2, &mmHUBPREQ2_PREFETCH_SETTINS[0], sizeof(mmHUBPREQ2_PREFETCH_SETTINS)/sizeof(mmHUBPREQ2_PREFETCH_SETTINS[0]), 0, 0 }, + { "mmHUBPREQ2_PREFETCH_SETTINS_C", REG_MMIO, 0x0743, 2, &mmHUBPREQ2_PREFETCH_SETTINS_C[0], sizeof(mmHUBPREQ2_PREFETCH_SETTINS_C)/sizeof(mmHUBPREQ2_PREFETCH_SETTINS_C[0]), 0, 0 }, + { "mmHUBPREQ2_VBLANK_PARAMETERS_0", REG_MMIO, 0x0744, 2, &mmHUBPREQ2_VBLANK_PARAMETERS_0[0], sizeof(mmHUBPREQ2_VBLANK_PARAMETERS_0)/sizeof(mmHUBPREQ2_VBLANK_PARAMETERS_0[0]), 0, 0 }, + { "mmHUBPREQ2_VBLANK_PARAMETERS_1", REG_MMIO, 0x0745, 2, &mmHUBPREQ2_VBLANK_PARAMETERS_1[0], sizeof(mmHUBPREQ2_VBLANK_PARAMETERS_1)/sizeof(mmHUBPREQ2_VBLANK_PARAMETERS_1[0]), 0, 0 }, + { "mmHUBPREQ2_VBLANK_PARAMETERS_2", REG_MMIO, 0x0746, 2, &mmHUBPREQ2_VBLANK_PARAMETERS_2[0], sizeof(mmHUBPREQ2_VBLANK_PARAMETERS_2)/sizeof(mmHUBPREQ2_VBLANK_PARAMETERS_2[0]), 0, 0 }, + { "mmHUBPREQ2_VBLANK_PARAMETERS_3", REG_MMIO, 0x0747, 2, &mmHUBPREQ2_VBLANK_PARAMETERS_3[0], sizeof(mmHUBPREQ2_VBLANK_PARAMETERS_3)/sizeof(mmHUBPREQ2_VBLANK_PARAMETERS_3[0]), 0, 0 }, + { "mmHUBPREQ2_VBLANK_PARAMETERS_4", REG_MMIO, 0x0748, 2, &mmHUBPREQ2_VBLANK_PARAMETERS_4[0], sizeof(mmHUBPREQ2_VBLANK_PARAMETERS_4)/sizeof(mmHUBPREQ2_VBLANK_PARAMETERS_4[0]), 0, 0 }, + { "mmHUBPREQ2_NOM_PARAMETERS_0", REG_MMIO, 0x0749, 2, &mmHUBPREQ2_NOM_PARAMETERS_0[0], sizeof(mmHUBPREQ2_NOM_PARAMETERS_0)/sizeof(mmHUBPREQ2_NOM_PARAMETERS_0[0]), 0, 0 }, + { "mmHUBPREQ2_NOM_PARAMETERS_1", REG_MMIO, 0x074a, 2, &mmHUBPREQ2_NOM_PARAMETERS_1[0], sizeof(mmHUBPREQ2_NOM_PARAMETERS_1)/sizeof(mmHUBPREQ2_NOM_PARAMETERS_1[0]), 0, 0 }, + { "mmHUBPREQ2_NOM_PARAMETERS_2", REG_MMIO, 0x074b, 2, &mmHUBPREQ2_NOM_PARAMETERS_2[0], sizeof(mmHUBPREQ2_NOM_PARAMETERS_2)/sizeof(mmHUBPREQ2_NOM_PARAMETERS_2[0]), 0, 0 }, + { "mmHUBPREQ2_NOM_PARAMETERS_3", REG_MMIO, 0x074c, 2, &mmHUBPREQ2_NOM_PARAMETERS_3[0], sizeof(mmHUBPREQ2_NOM_PARAMETERS_3)/sizeof(mmHUBPREQ2_NOM_PARAMETERS_3[0]), 0, 0 }, + { "mmHUBPREQ2_NOM_PARAMETERS_4", REG_MMIO, 0x074d, 2, &mmHUBPREQ2_NOM_PARAMETERS_4[0], sizeof(mmHUBPREQ2_NOM_PARAMETERS_4)/sizeof(mmHUBPREQ2_NOM_PARAMETERS_4[0]), 0, 0 }, + { "mmHUBPREQ2_NOM_PARAMETERS_5", REG_MMIO, 0x074e, 2, &mmHUBPREQ2_NOM_PARAMETERS_5[0], sizeof(mmHUBPREQ2_NOM_PARAMETERS_5)/sizeof(mmHUBPREQ2_NOM_PARAMETERS_5[0]), 0, 0 }, + { "mmHUBPREQ2_NOM_PARAMETERS_6", REG_MMIO, 0x074f, 2, &mmHUBPREQ2_NOM_PARAMETERS_6[0], sizeof(mmHUBPREQ2_NOM_PARAMETERS_6)/sizeof(mmHUBPREQ2_NOM_PARAMETERS_6[0]), 0, 0 }, + { "mmHUBPREQ2_NOM_PARAMETERS_7", REG_MMIO, 0x0750, 2, &mmHUBPREQ2_NOM_PARAMETERS_7[0], sizeof(mmHUBPREQ2_NOM_PARAMETERS_7)/sizeof(mmHUBPREQ2_NOM_PARAMETERS_7[0]), 0, 0 }, + { "mmHUBPREQ2_PER_LINE_DELIVERY_PRE", REG_MMIO, 0x0751, 2, &mmHUBPREQ2_PER_LINE_DELIVERY_PRE[0], sizeof(mmHUBPREQ2_PER_LINE_DELIVERY_PRE)/sizeof(mmHUBPREQ2_PER_LINE_DELIVERY_PRE[0]), 0, 0 }, + { "mmHUBPREQ2_PER_LINE_DELIVERY", REG_MMIO, 0x0752, 2, &mmHUBPREQ2_PER_LINE_DELIVERY[0], sizeof(mmHUBPREQ2_PER_LINE_DELIVERY)/sizeof(mmHUBPREQ2_PER_LINE_DELIVERY[0]), 0, 0 }, + { "mmHUBPREQ2_CURSOR_SETTINS", REG_MMIO, 0x0753, 2, &mmHUBPREQ2_CURSOR_SETTINS[0], sizeof(mmHUBPREQ2_CURSOR_SETTINS)/sizeof(mmHUBPREQ2_CURSOR_SETTINS[0]), 0, 0 }, + { "mmHUBPREQ2_REF_FREQ_TO_PIX_FREQ", REG_MMIO, 0x0754, 2, &mmHUBPREQ2_REF_FREQ_TO_PIX_FREQ[0], sizeof(mmHUBPREQ2_REF_FREQ_TO_PIX_FREQ)/sizeof(mmHUBPREQ2_REF_FREQ_TO_PIX_FREQ[0]), 0, 0 }, + { "mmHUBPREQ2_HUBPREQ_MEM_PWR_CTRL", REG_MMIO, 0x0755, 2, &mmHUBPREQ2_HUBPREQ_MEM_PWR_CTRL[0], sizeof(mmHUBPREQ2_HUBPREQ_MEM_PWR_CTRL)/sizeof(mmHUBPREQ2_HUBPREQ_MEM_PWR_CTRL[0]), 0, 0 }, + { "mmHUBPREQ2_HUBPREQ_MEM_PWR_STATUS", REG_MMIO, 0x0756, 2, &mmHUBPREQ2_HUBPREQ_MEM_PWR_STATUS[0], sizeof(mmHUBPREQ2_HUBPREQ_MEM_PWR_STATUS)/sizeof(mmHUBPREQ2_HUBPREQ_MEM_PWR_STATUS[0]), 0, 0 }, + { "mmHUBPRET2_HUBPRET_CONTROL", REG_MMIO, 0x0768, 2, &mmHUBPRET2_HUBPRET_CONTROL[0], sizeof(mmHUBPRET2_HUBPRET_CONTROL)/sizeof(mmHUBPRET2_HUBPRET_CONTROL[0]), 0, 0 }, + { "mmHUBPRET2_HUBPRET_MEM_PWR_CTRL", REG_MMIO, 0x0769, 2, &mmHUBPRET2_HUBPRET_MEM_PWR_CTRL[0], sizeof(mmHUBPRET2_HUBPRET_MEM_PWR_CTRL)/sizeof(mmHUBPRET2_HUBPRET_MEM_PWR_CTRL[0]), 0, 0 }, + { "mmHUBPRET2_HUBPRET_MEM_PWR_STATUS", REG_MMIO, 0x076a, 2, &mmHUBPRET2_HUBPRET_MEM_PWR_STATUS[0], sizeof(mmHUBPRET2_HUBPRET_MEM_PWR_STATUS)/sizeof(mmHUBPRET2_HUBPRET_MEM_PWR_STATUS[0]), 0, 0 }, + { "mmHUBPRET2_HUBPRET_READ_LINE_CTRL0", REG_MMIO, 0x076b, 2, &mmHUBPRET2_HUBPRET_READ_LINE_CTRL0[0], sizeof(mmHUBPRET2_HUBPRET_READ_LINE_CTRL0)/sizeof(mmHUBPRET2_HUBPRET_READ_LINE_CTRL0[0]), 0, 0 }, + { "mmHUBPRET2_HUBPRET_READ_LINE_CTRL1", REG_MMIO, 0x076c, 2, &mmHUBPRET2_HUBPRET_READ_LINE_CTRL1[0], sizeof(mmHUBPRET2_HUBPRET_READ_LINE_CTRL1)/sizeof(mmHUBPRET2_HUBPRET_READ_LINE_CTRL1[0]), 0, 0 }, + { "mmHUBPRET2_HUBPRET_READ_LINE0", REG_MMIO, 0x076d, 2, &mmHUBPRET2_HUBPRET_READ_LINE0[0], sizeof(mmHUBPRET2_HUBPRET_READ_LINE0)/sizeof(mmHUBPRET2_HUBPRET_READ_LINE0[0]), 0, 0 }, + { "mmHUBPRET2_HUBPRET_READ_LINE1", REG_MMIO, 0x076e, 2, &mmHUBPRET2_HUBPRET_READ_LINE1[0], sizeof(mmHUBPRET2_HUBPRET_READ_LINE1)/sizeof(mmHUBPRET2_HUBPRET_READ_LINE1[0]), 0, 0 }, + { "mmHUBPRET2_HUBPRET_INTERRUPT", REG_MMIO, 0x076f, 2, &mmHUBPRET2_HUBPRET_INTERRUPT[0], sizeof(mmHUBPRET2_HUBPRET_INTERRUPT)/sizeof(mmHUBPRET2_HUBPRET_INTERRUPT[0]), 0, 0 }, + { "mmHUBPRET2_HUBPRET_READ_LINE_VALUE", REG_MMIO, 0x0770, 2, &mmHUBPRET2_HUBPRET_READ_LINE_VALUE[0], sizeof(mmHUBPRET2_HUBPRET_READ_LINE_VALUE)/sizeof(mmHUBPRET2_HUBPRET_READ_LINE_VALUE[0]), 0, 0 }, + { "mmHUBPRET2_HUBPRET_READ_LINE_STATUS", REG_MMIO, 0x0771, 2, &mmHUBPRET2_HUBPRET_READ_LINE_STATUS[0], sizeof(mmHUBPRET2_HUBPRET_READ_LINE_STATUS)/sizeof(mmHUBPRET2_HUBPRET_READ_LINE_STATUS[0]), 0, 0 }, + { "mmCURSOR2_CURSOR_CONTROL", REG_MMIO, 0x0774, 2, &mmCURSOR2_CURSOR_CONTROL[0], sizeof(mmCURSOR2_CURSOR_CONTROL)/sizeof(mmCURSOR2_CURSOR_CONTROL[0]), 0, 0 }, + { "mmCURSOR2_CURSOR_SURFACE_ADDRESS", REG_MMIO, 0x0775, 2, &mmCURSOR2_CURSOR_SURFACE_ADDRESS[0], sizeof(mmCURSOR2_CURSOR_SURFACE_ADDRESS)/sizeof(mmCURSOR2_CURSOR_SURFACE_ADDRESS[0]), 0, 0 }, + { "mmCURSOR2_CURSOR_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x0776, 2, &mmCURSOR2_CURSOR_SURFACE_ADDRESS_HIGH[0], sizeof(mmCURSOR2_CURSOR_SURFACE_ADDRESS_HIGH)/sizeof(mmCURSOR2_CURSOR_SURFACE_ADDRESS_HIGH[0]), 0, 0 }, + { "mmCURSOR2_CURSOR_SIZE", REG_MMIO, 0x0777, 2, &mmCURSOR2_CURSOR_SIZE[0], sizeof(mmCURSOR2_CURSOR_SIZE)/sizeof(mmCURSOR2_CURSOR_SIZE[0]), 0, 0 }, + { "mmCURSOR2_CURSOR_POSITION", REG_MMIO, 0x0778, 2, &mmCURSOR2_CURSOR_POSITION[0], sizeof(mmCURSOR2_CURSOR_POSITION)/sizeof(mmCURSOR2_CURSOR_POSITION[0]), 0, 0 }, + { "mmCURSOR2_CURSOR_HOT_SPOT", REG_MMIO, 0x0779, 2, &mmCURSOR2_CURSOR_HOT_SPOT[0], sizeof(mmCURSOR2_CURSOR_HOT_SPOT)/sizeof(mmCURSOR2_CURSOR_HOT_SPOT[0]), 0, 0 }, + { "mmCURSOR2_CURSOR_STEREO_CONTROL", REG_MMIO, 0x077a, 2, &mmCURSOR2_CURSOR_STEREO_CONTROL[0], sizeof(mmCURSOR2_CURSOR_STEREO_CONTROL)/sizeof(mmCURSOR2_CURSOR_STEREO_CONTROL[0]), 0, 0 }, + { "mmCURSOR2_CURSOR_DST_OFFSET", REG_MMIO, 0x077b, 2, &mmCURSOR2_CURSOR_DST_OFFSET[0], sizeof(mmCURSOR2_CURSOR_DST_OFFSET)/sizeof(mmCURSOR2_CURSOR_DST_OFFSET[0]), 0, 0 }, + { "mmCURSOR2_CURSOR_MEM_PWR_CTRL", REG_MMIO, 0x077c, 2, &mmCURSOR2_CURSOR_MEM_PWR_CTRL[0], sizeof(mmCURSOR2_CURSOR_MEM_PWR_CTRL)/sizeof(mmCURSOR2_CURSOR_MEM_PWR_CTRL[0]), 0, 0 }, + { "mmCURSOR2_CURSOR_MEM_PWR_STATUS", REG_MMIO, 0x077d, 2, &mmCURSOR2_CURSOR_MEM_PWR_STATUS[0], sizeof(mmCURSOR2_CURSOR_MEM_PWR_STATUS)/sizeof(mmCURSOR2_CURSOR_MEM_PWR_STATUS[0]), 0, 0 }, + { "mmDC_PERFMON10_PERFCOUNTER_CNTL", REG_MMIO, 0x0799, 2, &mmDC_PERFMON10_PERFCOUNTER_CNTL[0], sizeof(mmDC_PERFMON10_PERFCOUNTER_CNTL)/sizeof(mmDC_PERFMON10_PERFCOUNTER_CNTL[0]), 0, 0 }, + { "mmDC_PERFMON10_PERFCOUNTER_CNTL2", REG_MMIO, 0x079a, 2, &mmDC_PERFMON10_PERFCOUNTER_CNTL2[0], sizeof(mmDC_PERFMON10_PERFCOUNTER_CNTL2)/sizeof(mmDC_PERFMON10_PERFCOUNTER_CNTL2[0]), 0, 0 }, + { "mmDC_PERFMON10_PERFCOUNTER_STATE", REG_MMIO, 0x079b, 2, &mmDC_PERFMON10_PERFCOUNTER_STATE[0], sizeof(mmDC_PERFMON10_PERFCOUNTER_STATE)/sizeof(mmDC_PERFMON10_PERFCOUNTER_STATE[0]), 0, 0 }, + { "mmDC_PERFMON10_PERFMON_CNTL", REG_MMIO, 0x079c, 2, &mmDC_PERFMON10_PERFMON_CNTL[0], sizeof(mmDC_PERFMON10_PERFMON_CNTL)/sizeof(mmDC_PERFMON10_PERFMON_CNTL[0]), 0, 0 }, + { "mmDC_PERFMON10_PERFMON_CNTL2", REG_MMIO, 0x079d, 2, &mmDC_PERFMON10_PERFMON_CNTL2[0], sizeof(mmDC_PERFMON10_PERFMON_CNTL2)/sizeof(mmDC_PERFMON10_PERFMON_CNTL2[0]), 0, 0 }, + { "mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC", REG_MMIO, 0x079e, 2, &mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC[0], sizeof(mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC)/sizeof(mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC[0]), 0, 0 }, + { "mmDC_PERFMON10_PERFMON_CVALUE_LOW", REG_MMIO, 0x079f, 2, &mmDC_PERFMON10_PERFMON_CVALUE_LOW[0], sizeof(mmDC_PERFMON10_PERFMON_CVALUE_LOW)/sizeof(mmDC_PERFMON10_PERFMON_CVALUE_LOW[0]), 0, 0 }, + { "mmDC_PERFMON10_PERFMON_HI", REG_MMIO, 0x07a0, 2, &mmDC_PERFMON10_PERFMON_HI[0], sizeof(mmDC_PERFMON10_PERFMON_HI)/sizeof(mmDC_PERFMON10_PERFMON_HI[0]), 0, 0 }, + { "mmDC_PERFMON10_PERFMON_LOW", REG_MMIO, 0x07a1, 2, &mmDC_PERFMON10_PERFMON_LOW[0], sizeof(mmDC_PERFMON10_PERFMON_LOW)/sizeof(mmDC_PERFMON10_PERFMON_LOW[0]), 0, 0 }, + { "mmHUBP3_DCSURF_SURFACE_CONFIG", REG_MMIO, 0x07a5, 2, &mmHUBP3_DCSURF_SURFACE_CONFIG[0], sizeof(mmHUBP3_DCSURF_SURFACE_CONFIG)/sizeof(mmHUBP3_DCSURF_SURFACE_CONFIG[0]), 0, 0 }, + { "mmHUBP3_DCSURF_ADDR_CONFIG", REG_MMIO, 0x07a6, 2, &mmHUBP3_DCSURF_ADDR_CONFIG[0], sizeof(mmHUBP3_DCSURF_ADDR_CONFIG)/sizeof(mmHUBP3_DCSURF_ADDR_CONFIG[0]), 0, 0 }, + { "mmHUBP3_DCSURF_TILING_CONFIG", REG_MMIO, 0x07a7, 2, &mmHUBP3_DCSURF_TILING_CONFIG[0], sizeof(mmHUBP3_DCSURF_TILING_CONFIG)/sizeof(mmHUBP3_DCSURF_TILING_CONFIG[0]), 0, 0 }, + { "mmHUBP3_DCSURF_PRI_VIEWPORT_START", REG_MMIO, 0x07a8, 2, &mmHUBP3_DCSURF_PRI_VIEWPORT_START[0], sizeof(mmHUBP3_DCSURF_PRI_VIEWPORT_START)/sizeof(mmHUBP3_DCSURF_PRI_VIEWPORT_START[0]), 0, 0 }, + { "mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION", REG_MMIO, 0x07a9, 2, &mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION[0], sizeof(mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION)/sizeof(mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION[0]), 0, 0 }, + { "mmHUBP3_DCSURF_PRI_VIEWPORT_START_C", REG_MMIO, 0x07aa, 2, &mmHUBP3_DCSURF_PRI_VIEWPORT_START_C[0], sizeof(mmHUBP3_DCSURF_PRI_VIEWPORT_START_C)/sizeof(mmHUBP3_DCSURF_PRI_VIEWPORT_START_C[0]), 0, 0 }, + { "mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C", REG_MMIO, 0x07ab, 2, &mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C[0], sizeof(mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C)/sizeof(mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C[0]), 0, 0 }, + { "mmHUBP3_DCSURF_SEC_VIEWPORT_START", REG_MMIO, 0x07ac, 2, &mmHUBP3_DCSURF_SEC_VIEWPORT_START[0], sizeof(mmHUBP3_DCSURF_SEC_VIEWPORT_START)/sizeof(mmHUBP3_DCSURF_SEC_VIEWPORT_START[0]), 0, 0 }, + { "mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION", REG_MMIO, 0x07ad, 2, &mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION[0], sizeof(mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION)/sizeof(mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION[0]), 0, 0 }, + { "mmHUBP3_DCSURF_SEC_VIEWPORT_START_C", REG_MMIO, 0x07ae, 2, &mmHUBP3_DCSURF_SEC_VIEWPORT_START_C[0], sizeof(mmHUBP3_DCSURF_SEC_VIEWPORT_START_C)/sizeof(mmHUBP3_DCSURF_SEC_VIEWPORT_START_C[0]), 0, 0 }, + { "mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C", REG_MMIO, 0x07af, 2, &mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C[0], sizeof(mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C)/sizeof(mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C[0]), 0, 0 }, + { "mmHUBP3_DCHUBP_REQ_SIZE_CONFIG", REG_MMIO, 0x07b0, 2, &mmHUBP3_DCHUBP_REQ_SIZE_CONFIG[0], sizeof(mmHUBP3_DCHUBP_REQ_SIZE_CONFIG)/sizeof(mmHUBP3_DCHUBP_REQ_SIZE_CONFIG[0]), 0, 0 }, + { "mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_C", REG_MMIO, 0x07b1, 2, &mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_C[0], sizeof(mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_C)/sizeof(mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_C[0]), 0, 0 }, + { "mmHUBP3_DCHUBP_CNTL", REG_MMIO, 0x07b2, 2, &mmHUBP3_DCHUBP_CNTL[0], sizeof(mmHUBP3_DCHUBP_CNTL)/sizeof(mmHUBP3_DCHUBP_CNTL[0]), 0, 0 }, + { "mmHUBP3_HUBP_CLK_CNTL", REG_MMIO, 0x07b3, 2, &mmHUBP3_HUBP_CLK_CNTL[0], sizeof(mmHUBP3_HUBP_CLK_CNTL)/sizeof(mmHUBP3_HUBP_CLK_CNTL[0]), 0, 0 }, + { "mmHUBP3_DCHUBP_VMPG_CONFIG", REG_MMIO, 0x07b4, 2, &mmHUBP3_DCHUBP_VMPG_CONFIG[0], sizeof(mmHUBP3_DCHUBP_VMPG_CONFIG)/sizeof(mmHUBP3_DCHUBP_VMPG_CONFIG[0]), 0, 0 }, + { "mmHUBP3_HUBPREQ_DEBUG_DB", REG_MMIO, 0x07b5, 2, &mmHUBP3_HUBPREQ_DEBUG_DB[0], sizeof(mmHUBP3_HUBPREQ_DEBUG_DB)/sizeof(mmHUBP3_HUBPREQ_DEBUG_DB[0]), 0, 0 }, + { "mmHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK", REG_MMIO, 0x07ba, 2, &mmHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK[0], sizeof(mmHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK)/sizeof(mmHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK[0]), 0, 0 }, + { "mmHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK", REG_MMIO, 0x07bb, 2, &mmHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK[0], sizeof(mmHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK)/sizeof(mmHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK[0]), 0, 0 }, + { "mmHUBPREQ3_DCSURF_SURFACE_PITCH", REG_MMIO, 0x07c7, 2, &mmHUBPREQ3_DCSURF_SURFACE_PITCH[0], sizeof(mmHUBPREQ3_DCSURF_SURFACE_PITCH)/sizeof(mmHUBPREQ3_DCSURF_SURFACE_PITCH[0]), 0, 0 }, + { "mmHUBPREQ3_DCSURF_SURFACE_PITCH_C", REG_MMIO, 0x07c8, 2, &mmHUBPREQ3_DCSURF_SURFACE_PITCH_C[0], sizeof(mmHUBPREQ3_DCSURF_SURFACE_PITCH_C)/sizeof(mmHUBPREQ3_DCSURF_SURFACE_PITCH_C[0]), 0, 0 }, + { "mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS", REG_MMIO, 0x07c9, 2, &mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS[0], sizeof(mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS)/sizeof(mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS[0]), 0, 0 }, + { "mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x07ca, 2, &mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH[0], sizeof(mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH)/sizeof(mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH[0]), 0, 0 }, + { "mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C", REG_MMIO, 0x07cb, 2, &mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C[0], sizeof(mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C)/sizeof(mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C[0]), 0, 0 }, + { "mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C", REG_MMIO, 0x07cc, 2, &mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C[0], sizeof(mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C)/sizeof(mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C[0]), 0, 0 }, + { "mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS", REG_MMIO, 0x07cd, 2, &mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS[0], sizeof(mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS)/sizeof(mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS[0]), 0, 0 }, + { "mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x07ce, 2, &mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH[0], sizeof(mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH)/sizeof(mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH[0]), 0, 0 }, + { "mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C", REG_MMIO, 0x07cf, 2, &mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C[0], sizeof(mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C)/sizeof(mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C[0]), 0, 0 }, + { "mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C", REG_MMIO, 0x07d0, 2, &mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C[0], sizeof(mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C)/sizeof(mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C[0]), 0, 0 }, + { "mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS", REG_MMIO, 0x07d1, 2, &mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS[0], sizeof(mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS)/sizeof(mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS[0]), 0, 0 }, + { "mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x07d2, 2, &mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH[0], sizeof(mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH)/sizeof(mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH[0]), 0, 0 }, + { "mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C", REG_MMIO, 0x07d3, 2, &mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C[0], sizeof(mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C)/sizeof(mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C[0]), 0, 0 }, + { "mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C", REG_MMIO, 0x07d4, 2, &mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C[0], sizeof(mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C)/sizeof(mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C[0]), 0, 0 }, + { "mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS", REG_MMIO, 0x07d5, 2, &mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS[0], sizeof(mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS)/sizeof(mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS[0]), 0, 0 }, + { "mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x07d6, 2, &mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH[0], sizeof(mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH)/sizeof(mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH[0]), 0, 0 }, + { "mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C", REG_MMIO, 0x07d7, 2, &mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C[0], sizeof(mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C)/sizeof(mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C[0]), 0, 0 }, + { "mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C", REG_MMIO, 0x07d8, 2, &mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C[0], sizeof(mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C)/sizeof(mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C[0]), 0, 0 }, + { "mmHUBPREQ3_DCSURF_SURFACE_CONTROL", REG_MMIO, 0x07d9, 2, &mmHUBPREQ3_DCSURF_SURFACE_CONTROL[0], sizeof(mmHUBPREQ3_DCSURF_SURFACE_CONTROL)/sizeof(mmHUBPREQ3_DCSURF_SURFACE_CONTROL[0]), 0, 0 }, + { "mmHUBPREQ3_DCSURF_FLIP_CONTROL", REG_MMIO, 0x07da, 2, &mmHUBPREQ3_DCSURF_FLIP_CONTROL[0], sizeof(mmHUBPREQ3_DCSURF_FLIP_CONTROL)/sizeof(mmHUBPREQ3_DCSURF_FLIP_CONTROL[0]), 0, 0 }, + { "mmHUBPREQ3_DCSURF_FLIP_CONTROL2", REG_MMIO, 0x07db, 2, &mmHUBPREQ3_DCSURF_FLIP_CONTROL2[0], sizeof(mmHUBPREQ3_DCSURF_FLIP_CONTROL2)/sizeof(mmHUBPREQ3_DCSURF_FLIP_CONTROL2[0]), 0, 0 }, + { "mmHUBPREQ3_DCSURF_FRAME_PACING_CONTROL", REG_MMIO, 0x07dc, 2, &mmHUBPREQ3_DCSURF_FRAME_PACING_CONTROL[0], sizeof(mmHUBPREQ3_DCSURF_FRAME_PACING_CONTROL)/sizeof(mmHUBPREQ3_DCSURF_FRAME_PACING_CONTROL[0]), 0, 0 }, + { "mmHUBPREQ3_DCSURF_FRAME_PACING_TIME", REG_MMIO, 0x07dd, 2, &mmHUBPREQ3_DCSURF_FRAME_PACING_TIME[0], sizeof(mmHUBPREQ3_DCSURF_FRAME_PACING_TIME)/sizeof(mmHUBPREQ3_DCSURF_FRAME_PACING_TIME[0]), 0, 0 }, + { "mmHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT", REG_MMIO, 0x07de, 2, &mmHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT[0], sizeof(mmHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT)/sizeof(mmHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT[0]), 0, 0 }, + { "mmHUBPREQ3_DCSURF_SURFACE_INUSE", REG_MMIO, 0x07df, 2, &mmHUBPREQ3_DCSURF_SURFACE_INUSE[0], sizeof(mmHUBPREQ3_DCSURF_SURFACE_INUSE)/sizeof(mmHUBPREQ3_DCSURF_SURFACE_INUSE[0]), 0, 0 }, + { "mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH", REG_MMIO, 0x07e0, 2, &mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH[0], sizeof(mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH)/sizeof(mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH[0]), 0, 0 }, + { "mmHUBPREQ3_DCSURF_SURFACE_INUSE_C", REG_MMIO, 0x07e1, 2, &mmHUBPREQ3_DCSURF_SURFACE_INUSE_C[0], sizeof(mmHUBPREQ3_DCSURF_SURFACE_INUSE_C)/sizeof(mmHUBPREQ3_DCSURF_SURFACE_INUSE_C[0]), 0, 0 }, + { "mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C", REG_MMIO, 0x07e2, 2, &mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C[0], sizeof(mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C)/sizeof(mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C[0]), 0, 0 }, + { "mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE", REG_MMIO, 0x07e3, 2, &mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE[0], sizeof(mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE)/sizeof(mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE[0]), 0, 0 }, + { "mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH", REG_MMIO, 0x07e4, 2, &mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH[0], sizeof(mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH)/sizeof(mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH[0]), 0, 0 }, + { "mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C", REG_MMIO, 0x07e5, 2, &mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C[0], sizeof(mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C)/sizeof(mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C[0]), 0, 0 }, + { "mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C", REG_MMIO, 0x07e6, 2, &mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C[0], sizeof(mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C)/sizeof(mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C[0]), 0, 0 }, + { "mmHUBPREQ3_DCN_EXPANSION_MODE", REG_MMIO, 0x07e7, 2, &mmHUBPREQ3_DCN_EXPANSION_MODE[0], sizeof(mmHUBPREQ3_DCN_EXPANSION_MODE)/sizeof(mmHUBPREQ3_DCN_EXPANSION_MODE[0]), 0, 0 }, + { "mmHUBPREQ3_DCN_TTU_QOS_WM", REG_MMIO, 0x07e8, 2, &mmHUBPREQ3_DCN_TTU_QOS_WM[0], sizeof(mmHUBPREQ3_DCN_TTU_QOS_WM)/sizeof(mmHUBPREQ3_DCN_TTU_QOS_WM[0]), 0, 0 }, + { "mmHUBPREQ3_DCN_GLOBAL_TTU_CNTL", REG_MMIO, 0x07e9, 2, &mmHUBPREQ3_DCN_GLOBAL_TTU_CNTL[0], sizeof(mmHUBPREQ3_DCN_GLOBAL_TTU_CNTL)/sizeof(mmHUBPREQ3_DCN_GLOBAL_TTU_CNTL[0]), 0, 0 }, + { "mmHUBPREQ3_DCN_SURF0_TTU_CNTL0", REG_MMIO, 0x07ea, 2, &mmHUBPREQ3_DCN_SURF0_TTU_CNTL0[0], sizeof(mmHUBPREQ3_DCN_SURF0_TTU_CNTL0)/sizeof(mmHUBPREQ3_DCN_SURF0_TTU_CNTL0[0]), 0, 0 }, + { "mmHUBPREQ3_DCN_SURF0_TTU_CNTL1", REG_MMIO, 0x07eb, 2, &mmHUBPREQ3_DCN_SURF0_TTU_CNTL1[0], sizeof(mmHUBPREQ3_DCN_SURF0_TTU_CNTL1)/sizeof(mmHUBPREQ3_DCN_SURF0_TTU_CNTL1[0]), 0, 0 }, + { "mmHUBPREQ3_DCN_SURF1_TTU_CNTL0", REG_MMIO, 0x07ec, 2, &mmHUBPREQ3_DCN_SURF1_TTU_CNTL0[0], sizeof(mmHUBPREQ3_DCN_SURF1_TTU_CNTL0)/sizeof(mmHUBPREQ3_DCN_SURF1_TTU_CNTL0[0]), 0, 0 }, + { "mmHUBPREQ3_DCN_SURF1_TTU_CNTL1", REG_MMIO, 0x07ed, 2, &mmHUBPREQ3_DCN_SURF1_TTU_CNTL1[0], sizeof(mmHUBPREQ3_DCN_SURF1_TTU_CNTL1)/sizeof(mmHUBPREQ3_DCN_SURF1_TTU_CNTL1[0]), 0, 0 }, + { "mmHUBPREQ3_DCN_CUR0_TTU_CNTL0", REG_MMIO, 0x07ee, 2, &mmHUBPREQ3_DCN_CUR0_TTU_CNTL0[0], sizeof(mmHUBPREQ3_DCN_CUR0_TTU_CNTL0)/sizeof(mmHUBPREQ3_DCN_CUR0_TTU_CNTL0[0]), 0, 0 }, + { "mmHUBPREQ3_DCN_CUR0_TTU_CNTL1", REG_MMIO, 0x07ef, 2, &mmHUBPREQ3_DCN_CUR0_TTU_CNTL1[0], sizeof(mmHUBPREQ3_DCN_CUR0_TTU_CNTL1)/sizeof(mmHUBPREQ3_DCN_CUR0_TTU_CNTL1[0]), 0, 0 }, + { "mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB", REG_MMIO, 0x07f0, 2, &mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB[0], sizeof(mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB)/sizeof(mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB[0]), 0, 0 }, + { "mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB", REG_MMIO, 0x07f1, 2, &mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB[0], sizeof(mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB)/sizeof(mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB[0]), 0, 0 }, + { "mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB", REG_MMIO, 0x07f2, 2, &mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB[0], sizeof(mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB)/sizeof(mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB[0]), 0, 0 }, + { "mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB", REG_MMIO, 0x07f3, 2, &mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB[0], sizeof(mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB)/sizeof(mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB[0]), 0, 0 }, + { "mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB", REG_MMIO, 0x07f4, 2, &mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB[0], sizeof(mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB)/sizeof(mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB[0]), 0, 0 }, + { "mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB", REG_MMIO, 0x07f5, 2, &mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB[0], sizeof(mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB)/sizeof(mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB[0]), 0, 0 }, + { "mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB", REG_MMIO, 0x07f6, 2, &mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB[0], sizeof(mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB)/sizeof(mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB[0]), 0, 0 }, + { "mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB", REG_MMIO, 0x07f7, 2, &mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB[0], sizeof(mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB)/sizeof(mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB[0]), 0, 0 }, + { "mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB", REG_MMIO, 0x07f8, 2, &mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB[0], sizeof(mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB)/sizeof(mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB[0]), 0, 0 }, + { "mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB", REG_MMIO, 0x07f9, 2, &mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB[0], sizeof(mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB)/sizeof(mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB[0]), 0, 0 }, + { "mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB", REG_MMIO, 0x07fa, 2, &mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB[0], sizeof(mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB)/sizeof(mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB[0]), 0, 0 }, + { "mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB", REG_MMIO, 0x07fb, 2, &mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB[0], sizeof(mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB)/sizeof(mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB[0]), 0, 0 }, + { "mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB", REG_MMIO, 0x07fc, 2, &mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB[0], sizeof(mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB)/sizeof(mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB[0]), 0, 0 }, + { "mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB", REG_MMIO, 0x07fd, 2, &mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB[0], sizeof(mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB)/sizeof(mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB[0]), 0, 0 }, + { "mmHUBPREQ3_DCN_VM_CONTEXT0_STATUS", REG_MMIO, 0x07fe, 2, &mmHUBPREQ3_DCN_VM_CONTEXT0_STATUS[0], sizeof(mmHUBPREQ3_DCN_VM_CONTEXT0_STATUS)/sizeof(mmHUBPREQ3_DCN_VM_CONTEXT0_STATUS[0]), 0, 0 }, + { "mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB", REG_MMIO, 0x07ff, 2, &mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB[0], sizeof(mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB)/sizeof(mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB[0]), 0, 0 }, + { "mmHUBPREQ3_DCN_VM_CONTEXT0_CNTL", REG_MMIO, 0x0800, 2, &mmHUBPREQ3_DCN_VM_CONTEXT0_CNTL[0], sizeof(mmHUBPREQ3_DCN_VM_CONTEXT0_CNTL)/sizeof(mmHUBPREQ3_DCN_VM_CONTEXT0_CNTL[0]), 0, 0 }, + { "mmHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL", REG_MMIO, 0x0801, 2, &mmHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL[0], sizeof(mmHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL)/sizeof(mmHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL[0]), 0, 0 }, + { "mmHUBPREQ3_BLANK_OFFSET_0", REG_MMIO, 0x0802, 2, &mmHUBPREQ3_BLANK_OFFSET_0[0], sizeof(mmHUBPREQ3_BLANK_OFFSET_0)/sizeof(mmHUBPREQ3_BLANK_OFFSET_0[0]), 0, 0 }, + { "mmHUBPREQ3_BLANK_OFFSET_1", REG_MMIO, 0x0803, 2, &mmHUBPREQ3_BLANK_OFFSET_1[0], sizeof(mmHUBPREQ3_BLANK_OFFSET_1)/sizeof(mmHUBPREQ3_BLANK_OFFSET_1[0]), 0, 0 }, + { "mmHUBPREQ3_DST_DIMENSIONS", REG_MMIO, 0x0804, 2, &mmHUBPREQ3_DST_DIMENSIONS[0], sizeof(mmHUBPREQ3_DST_DIMENSIONS)/sizeof(mmHUBPREQ3_DST_DIMENSIONS[0]), 0, 0 }, + { "mmHUBPREQ3_DST_AFTER_SCALER", REG_MMIO, 0x0805, 2, &mmHUBPREQ3_DST_AFTER_SCALER[0], sizeof(mmHUBPREQ3_DST_AFTER_SCALER)/sizeof(mmHUBPREQ3_DST_AFTER_SCALER[0]), 0, 0 }, + { "mmHUBPREQ3_PREFETCH_SETTINS", REG_MMIO, 0x0806, 2, &mmHUBPREQ3_PREFETCH_SETTINS[0], sizeof(mmHUBPREQ3_PREFETCH_SETTINS)/sizeof(mmHUBPREQ3_PREFETCH_SETTINS[0]), 0, 0 }, + { "mmHUBPREQ3_PREFETCH_SETTINS_C", REG_MMIO, 0x0807, 2, &mmHUBPREQ3_PREFETCH_SETTINS_C[0], sizeof(mmHUBPREQ3_PREFETCH_SETTINS_C)/sizeof(mmHUBPREQ3_PREFETCH_SETTINS_C[0]), 0, 0 }, + { "mmHUBPREQ3_VBLANK_PARAMETERS_0", REG_MMIO, 0x0808, 2, &mmHUBPREQ3_VBLANK_PARAMETERS_0[0], sizeof(mmHUBPREQ3_VBLANK_PARAMETERS_0)/sizeof(mmHUBPREQ3_VBLANK_PARAMETERS_0[0]), 0, 0 }, + { "mmHUBPREQ3_VBLANK_PARAMETERS_1", REG_MMIO, 0x0809, 2, &mmHUBPREQ3_VBLANK_PARAMETERS_1[0], sizeof(mmHUBPREQ3_VBLANK_PARAMETERS_1)/sizeof(mmHUBPREQ3_VBLANK_PARAMETERS_1[0]), 0, 0 }, + { "mmHUBPREQ3_VBLANK_PARAMETERS_2", REG_MMIO, 0x080a, 2, &mmHUBPREQ3_VBLANK_PARAMETERS_2[0], sizeof(mmHUBPREQ3_VBLANK_PARAMETERS_2)/sizeof(mmHUBPREQ3_VBLANK_PARAMETERS_2[0]), 0, 0 }, + { "mmHUBPREQ3_VBLANK_PARAMETERS_3", REG_MMIO, 0x080b, 2, &mmHUBPREQ3_VBLANK_PARAMETERS_3[0], sizeof(mmHUBPREQ3_VBLANK_PARAMETERS_3)/sizeof(mmHUBPREQ3_VBLANK_PARAMETERS_3[0]), 0, 0 }, + { "mmHUBPREQ3_VBLANK_PARAMETERS_4", REG_MMIO, 0x080c, 2, &mmHUBPREQ3_VBLANK_PARAMETERS_4[0], sizeof(mmHUBPREQ3_VBLANK_PARAMETERS_4)/sizeof(mmHUBPREQ3_VBLANK_PARAMETERS_4[0]), 0, 0 }, + { "mmHUBPREQ3_NOM_PARAMETERS_0", REG_MMIO, 0x080d, 2, &mmHUBPREQ3_NOM_PARAMETERS_0[0], sizeof(mmHUBPREQ3_NOM_PARAMETERS_0)/sizeof(mmHUBPREQ3_NOM_PARAMETERS_0[0]), 0, 0 }, + { "mmHUBPREQ3_NOM_PARAMETERS_1", REG_MMIO, 0x080e, 2, &mmHUBPREQ3_NOM_PARAMETERS_1[0], sizeof(mmHUBPREQ3_NOM_PARAMETERS_1)/sizeof(mmHUBPREQ3_NOM_PARAMETERS_1[0]), 0, 0 }, + { "mmHUBPREQ3_NOM_PARAMETERS_2", REG_MMIO, 0x080f, 2, &mmHUBPREQ3_NOM_PARAMETERS_2[0], sizeof(mmHUBPREQ3_NOM_PARAMETERS_2)/sizeof(mmHUBPREQ3_NOM_PARAMETERS_2[0]), 0, 0 }, + { "mmHUBPREQ3_NOM_PARAMETERS_3", REG_MMIO, 0x0810, 2, &mmHUBPREQ3_NOM_PARAMETERS_3[0], sizeof(mmHUBPREQ3_NOM_PARAMETERS_3)/sizeof(mmHUBPREQ3_NOM_PARAMETERS_3[0]), 0, 0 }, + { "mmHUBPREQ3_NOM_PARAMETERS_4", REG_MMIO, 0x0811, 2, &mmHUBPREQ3_NOM_PARAMETERS_4[0], sizeof(mmHUBPREQ3_NOM_PARAMETERS_4)/sizeof(mmHUBPREQ3_NOM_PARAMETERS_4[0]), 0, 0 }, + { "mmHUBPREQ3_NOM_PARAMETERS_5", REG_MMIO, 0x0812, 2, &mmHUBPREQ3_NOM_PARAMETERS_5[0], sizeof(mmHUBPREQ3_NOM_PARAMETERS_5)/sizeof(mmHUBPREQ3_NOM_PARAMETERS_5[0]), 0, 0 }, + { "mmHUBPREQ3_NOM_PARAMETERS_6", REG_MMIO, 0x0813, 2, &mmHUBPREQ3_NOM_PARAMETERS_6[0], sizeof(mmHUBPREQ3_NOM_PARAMETERS_6)/sizeof(mmHUBPREQ3_NOM_PARAMETERS_6[0]), 0, 0 }, + { "mmHUBPREQ3_NOM_PARAMETERS_7", REG_MMIO, 0x0814, 2, &mmHUBPREQ3_NOM_PARAMETERS_7[0], sizeof(mmHUBPREQ3_NOM_PARAMETERS_7)/sizeof(mmHUBPREQ3_NOM_PARAMETERS_7[0]), 0, 0 }, + { "mmHUBPREQ3_PER_LINE_DELIVERY_PRE", REG_MMIO, 0x0815, 2, &mmHUBPREQ3_PER_LINE_DELIVERY_PRE[0], sizeof(mmHUBPREQ3_PER_LINE_DELIVERY_PRE)/sizeof(mmHUBPREQ3_PER_LINE_DELIVERY_PRE[0]), 0, 0 }, + { "mmHUBPREQ3_PER_LINE_DELIVERY", REG_MMIO, 0x0816, 2, &mmHUBPREQ3_PER_LINE_DELIVERY[0], sizeof(mmHUBPREQ3_PER_LINE_DELIVERY)/sizeof(mmHUBPREQ3_PER_LINE_DELIVERY[0]), 0, 0 }, + { "mmHUBPREQ3_CURSOR_SETTINS", REG_MMIO, 0x0817, 2, &mmHUBPREQ3_CURSOR_SETTINS[0], sizeof(mmHUBPREQ3_CURSOR_SETTINS)/sizeof(mmHUBPREQ3_CURSOR_SETTINS[0]), 0, 0 }, + { "mmHUBPREQ3_REF_FREQ_TO_PIX_FREQ", REG_MMIO, 0x0818, 2, &mmHUBPREQ3_REF_FREQ_TO_PIX_FREQ[0], sizeof(mmHUBPREQ3_REF_FREQ_TO_PIX_FREQ)/sizeof(mmHUBPREQ3_REF_FREQ_TO_PIX_FREQ[0]), 0, 0 }, + { "mmHUBPREQ3_HUBPREQ_MEM_PWR_CTRL", REG_MMIO, 0x0819, 2, &mmHUBPREQ3_HUBPREQ_MEM_PWR_CTRL[0], sizeof(mmHUBPREQ3_HUBPREQ_MEM_PWR_CTRL)/sizeof(mmHUBPREQ3_HUBPREQ_MEM_PWR_CTRL[0]), 0, 0 }, + { "mmHUBPREQ3_HUBPREQ_MEM_PWR_STATUS", REG_MMIO, 0x081a, 2, &mmHUBPREQ3_HUBPREQ_MEM_PWR_STATUS[0], sizeof(mmHUBPREQ3_HUBPREQ_MEM_PWR_STATUS)/sizeof(mmHUBPREQ3_HUBPREQ_MEM_PWR_STATUS[0]), 0, 0 }, + { "mmHUBPRET3_HUBPRET_CONTROL", REG_MMIO, 0x082c, 2, &mmHUBPRET3_HUBPRET_CONTROL[0], sizeof(mmHUBPRET3_HUBPRET_CONTROL)/sizeof(mmHUBPRET3_HUBPRET_CONTROL[0]), 0, 0 }, + { "mmHUBPRET3_HUBPRET_MEM_PWR_CTRL", REG_MMIO, 0x082d, 2, &mmHUBPRET3_HUBPRET_MEM_PWR_CTRL[0], sizeof(mmHUBPRET3_HUBPRET_MEM_PWR_CTRL)/sizeof(mmHUBPRET3_HUBPRET_MEM_PWR_CTRL[0]), 0, 0 }, + { "mmHUBPRET3_HUBPRET_MEM_PWR_STATUS", REG_MMIO, 0x082e, 2, &mmHUBPRET3_HUBPRET_MEM_PWR_STATUS[0], sizeof(mmHUBPRET3_HUBPRET_MEM_PWR_STATUS)/sizeof(mmHUBPRET3_HUBPRET_MEM_PWR_STATUS[0]), 0, 0 }, + { "mmHUBPRET3_HUBPRET_READ_LINE_CTRL0", REG_MMIO, 0x082f, 2, &mmHUBPRET3_HUBPRET_READ_LINE_CTRL0[0], sizeof(mmHUBPRET3_HUBPRET_READ_LINE_CTRL0)/sizeof(mmHUBPRET3_HUBPRET_READ_LINE_CTRL0[0]), 0, 0 }, + { "mmHUBPRET3_HUBPRET_READ_LINE_CTRL1", REG_MMIO, 0x0830, 2, &mmHUBPRET3_HUBPRET_READ_LINE_CTRL1[0], sizeof(mmHUBPRET3_HUBPRET_READ_LINE_CTRL1)/sizeof(mmHUBPRET3_HUBPRET_READ_LINE_CTRL1[0]), 0, 0 }, + { "mmHUBPRET3_HUBPRET_READ_LINE0", REG_MMIO, 0x0831, 2, &mmHUBPRET3_HUBPRET_READ_LINE0[0], sizeof(mmHUBPRET3_HUBPRET_READ_LINE0)/sizeof(mmHUBPRET3_HUBPRET_READ_LINE0[0]), 0, 0 }, + { "mmHUBPRET3_HUBPRET_READ_LINE1", REG_MMIO, 0x0832, 2, &mmHUBPRET3_HUBPRET_READ_LINE1[0], sizeof(mmHUBPRET3_HUBPRET_READ_LINE1)/sizeof(mmHUBPRET3_HUBPRET_READ_LINE1[0]), 0, 0 }, + { "mmHUBPRET3_HUBPRET_INTERRUPT", REG_MMIO, 0x0833, 2, &mmHUBPRET3_HUBPRET_INTERRUPT[0], sizeof(mmHUBPRET3_HUBPRET_INTERRUPT)/sizeof(mmHUBPRET3_HUBPRET_INTERRUPT[0]), 0, 0 }, + { "mmHUBPRET3_HUBPRET_READ_LINE_VALUE", REG_MMIO, 0x0834, 2, &mmHUBPRET3_HUBPRET_READ_LINE_VALUE[0], sizeof(mmHUBPRET3_HUBPRET_READ_LINE_VALUE)/sizeof(mmHUBPRET3_HUBPRET_READ_LINE_VALUE[0]), 0, 0 }, + { "mmHUBPRET3_HUBPRET_READ_LINE_STATUS", REG_MMIO, 0x0835, 2, &mmHUBPRET3_HUBPRET_READ_LINE_STATUS[0], sizeof(mmHUBPRET3_HUBPRET_READ_LINE_STATUS)/sizeof(mmHUBPRET3_HUBPRET_READ_LINE_STATUS[0]), 0, 0 }, + { "mmCURSOR3_CURSOR_CONTROL", REG_MMIO, 0x0838, 2, &mmCURSOR3_CURSOR_CONTROL[0], sizeof(mmCURSOR3_CURSOR_CONTROL)/sizeof(mmCURSOR3_CURSOR_CONTROL[0]), 0, 0 }, + { "mmCURSOR3_CURSOR_SURFACE_ADDRESS", REG_MMIO, 0x0839, 2, &mmCURSOR3_CURSOR_SURFACE_ADDRESS[0], sizeof(mmCURSOR3_CURSOR_SURFACE_ADDRESS)/sizeof(mmCURSOR3_CURSOR_SURFACE_ADDRESS[0]), 0, 0 }, + { "mmCURSOR3_CURSOR_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x083a, 2, &mmCURSOR3_CURSOR_SURFACE_ADDRESS_HIGH[0], sizeof(mmCURSOR3_CURSOR_SURFACE_ADDRESS_HIGH)/sizeof(mmCURSOR3_CURSOR_SURFACE_ADDRESS_HIGH[0]), 0, 0 }, + { "mmCURSOR3_CURSOR_SIZE", REG_MMIO, 0x083b, 2, &mmCURSOR3_CURSOR_SIZE[0], sizeof(mmCURSOR3_CURSOR_SIZE)/sizeof(mmCURSOR3_CURSOR_SIZE[0]), 0, 0 }, + { "mmCURSOR3_CURSOR_POSITION", REG_MMIO, 0x083c, 2, &mmCURSOR3_CURSOR_POSITION[0], sizeof(mmCURSOR3_CURSOR_POSITION)/sizeof(mmCURSOR3_CURSOR_POSITION[0]), 0, 0 }, + { "mmCURSOR3_CURSOR_HOT_SPOT", REG_MMIO, 0x083d, 2, &mmCURSOR3_CURSOR_HOT_SPOT[0], sizeof(mmCURSOR3_CURSOR_HOT_SPOT)/sizeof(mmCURSOR3_CURSOR_HOT_SPOT[0]), 0, 0 }, + { "mmCURSOR3_CURSOR_STEREO_CONTROL", REG_MMIO, 0x083e, 2, &mmCURSOR3_CURSOR_STEREO_CONTROL[0], sizeof(mmCURSOR3_CURSOR_STEREO_CONTROL)/sizeof(mmCURSOR3_CURSOR_STEREO_CONTROL[0]), 0, 0 }, + { "mmCURSOR3_CURSOR_DST_OFFSET", REG_MMIO, 0x083f, 2, &mmCURSOR3_CURSOR_DST_OFFSET[0], sizeof(mmCURSOR3_CURSOR_DST_OFFSET)/sizeof(mmCURSOR3_CURSOR_DST_OFFSET[0]), 0, 0 }, + { "mmCURSOR3_CURSOR_MEM_PWR_CTRL", REG_MMIO, 0x0840, 2, &mmCURSOR3_CURSOR_MEM_PWR_CTRL[0], sizeof(mmCURSOR3_CURSOR_MEM_PWR_CTRL)/sizeof(mmCURSOR3_CURSOR_MEM_PWR_CTRL[0]), 0, 0 }, + { "mmCURSOR3_CURSOR_MEM_PWR_STATUS", REG_MMIO, 0x0841, 2, &mmCURSOR3_CURSOR_MEM_PWR_STATUS[0], sizeof(mmCURSOR3_CURSOR_MEM_PWR_STATUS)/sizeof(mmCURSOR3_CURSOR_MEM_PWR_STATUS[0]), 0, 0 }, + { "mmDC_PERFMON11_PERFCOUNTER_CNTL", REG_MMIO, 0x085d, 2, &mmDC_PERFMON11_PERFCOUNTER_CNTL[0], sizeof(mmDC_PERFMON11_PERFCOUNTER_CNTL)/sizeof(mmDC_PERFMON11_PERFCOUNTER_CNTL[0]), 0, 0 }, + { "mmDC_PERFMON11_PERFCOUNTER_CNTL2", REG_MMIO, 0x085e, 2, &mmDC_PERFMON11_PERFCOUNTER_CNTL2[0], sizeof(mmDC_PERFMON11_PERFCOUNTER_CNTL2)/sizeof(mmDC_PERFMON11_PERFCOUNTER_CNTL2[0]), 0, 0 }, + { "mmDC_PERFMON11_PERFCOUNTER_STATE", REG_MMIO, 0x085f, 2, &mmDC_PERFMON11_PERFCOUNTER_STATE[0], sizeof(mmDC_PERFMON11_PERFCOUNTER_STATE)/sizeof(mmDC_PERFMON11_PERFCOUNTER_STATE[0]), 0, 0 }, + { "mmDC_PERFMON11_PERFMON_CNTL", REG_MMIO, 0x0860, 2, &mmDC_PERFMON11_PERFMON_CNTL[0], sizeof(mmDC_PERFMON11_PERFMON_CNTL)/sizeof(mmDC_PERFMON11_PERFMON_CNTL[0]), 0, 0 }, + { "mmDC_PERFMON11_PERFMON_CNTL2", REG_MMIO, 0x0861, 2, &mmDC_PERFMON11_PERFMON_CNTL2[0], sizeof(mmDC_PERFMON11_PERFMON_CNTL2)/sizeof(mmDC_PERFMON11_PERFMON_CNTL2[0]), 0, 0 }, + { "mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC", REG_MMIO, 0x0862, 2, &mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC[0], sizeof(mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC)/sizeof(mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC[0]), 0, 0 }, + { "mmDC_PERFMON11_PERFMON_CVALUE_LOW", REG_MMIO, 0x0863, 2, &mmDC_PERFMON11_PERFMON_CVALUE_LOW[0], sizeof(mmDC_PERFMON11_PERFMON_CVALUE_LOW)/sizeof(mmDC_PERFMON11_PERFMON_CVALUE_LOW[0]), 0, 0 }, + { "mmDC_PERFMON11_PERFMON_HI", REG_MMIO, 0x0864, 2, &mmDC_PERFMON11_PERFMON_HI[0], sizeof(mmDC_PERFMON11_PERFMON_HI)/sizeof(mmDC_PERFMON11_PERFMON_HI[0]), 0, 0 }, + { "mmDC_PERFMON11_PERFMON_LOW", REG_MMIO, 0x0865, 2, &mmDC_PERFMON11_PERFMON_LOW[0], sizeof(mmDC_PERFMON11_PERFMON_LOW)/sizeof(mmDC_PERFMON11_PERFMON_LOW[0]), 0, 0 }, + { "mmDPP_TOP0_DPP_CONTROL", REG_MMIO, 0x0c3d, 2, &mmDPP_TOP0_DPP_CONTROL[0], sizeof(mmDPP_TOP0_DPP_CONTROL)/sizeof(mmDPP_TOP0_DPP_CONTROL[0]), 0, 0 }, + { "mmDPP_TOP0_DPP_SOFT_RESET", REG_MMIO, 0x0c3e, 2, &mmDPP_TOP0_DPP_SOFT_RESET[0], sizeof(mmDPP_TOP0_DPP_SOFT_RESET)/sizeof(mmDPP_TOP0_DPP_SOFT_RESET[0]), 0, 0 }, + { "mmDPP_TOP0_DPP_CRC_VAL_R_G", REG_MMIO, 0x0c3f, 2, &mmDPP_TOP0_DPP_CRC_VAL_R_G[0], sizeof(mmDPP_TOP0_DPP_CRC_VAL_R_G)/sizeof(mmDPP_TOP0_DPP_CRC_VAL_R_G[0]), 0, 0 }, + { "mmDPP_TOP0_DPP_CRC_VAL_B_A", REG_MMIO, 0x0c40, 2, &mmDPP_TOP0_DPP_CRC_VAL_B_A[0], sizeof(mmDPP_TOP0_DPP_CRC_VAL_B_A)/sizeof(mmDPP_TOP0_DPP_CRC_VAL_B_A[0]), 0, 0 }, + { "mmDPP_TOP0_DPP_CRC_CTRL", REG_MMIO, 0x0c41, 2, &mmDPP_TOP0_DPP_CRC_CTRL[0], sizeof(mmDPP_TOP0_DPP_CRC_CTRL)/sizeof(mmDPP_TOP0_DPP_CRC_CTRL[0]), 0, 0 }, + { "mmDPP_TOP0_HOST_READ_CONTROL", REG_MMIO, 0x0c42, 2, &mmDPP_TOP0_HOST_READ_CONTROL[0], sizeof(mmDPP_TOP0_HOST_READ_CONTROL)/sizeof(mmDPP_TOP0_HOST_READ_CONTROL[0]), 0, 0 }, + { "mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT", REG_MMIO, 0x0c47, 2, &mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT[0], sizeof(mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT)/sizeof(mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT[0]), 0, 0 }, + { "mmCNVC_CFG0_FORMAT_CONTROL", REG_MMIO, 0x0c48, 2, &mmCNVC_CFG0_FORMAT_CONTROL[0], sizeof(mmCNVC_CFG0_FORMAT_CONTROL)/sizeof(mmCNVC_CFG0_FORMAT_CONTROL[0]), 0, 0 }, + { "mmCNVC_CFG0_FCNV_FP_SCALE_BIAS", REG_MMIO, 0x0c49, 2, &mmCNVC_CFG0_FCNV_FP_SCALE_BIAS[0], sizeof(mmCNVC_CFG0_FCNV_FP_SCALE_BIAS)/sizeof(mmCNVC_CFG0_FCNV_FP_SCALE_BIAS[0]), 0, 0 }, + { "mmCNVC_CFG0_DENORM_CONTROL", REG_MMIO, 0x0c4a, 2, &mmCNVC_CFG0_DENORM_CONTROL[0], sizeof(mmCNVC_CFG0_DENORM_CONTROL)/sizeof(mmCNVC_CFG0_DENORM_CONTROL[0]), 0, 0 }, + { "mmCNVC_CFG0_COLOR_KEYER_CONTROL", REG_MMIO, 0x0c4c, 2, &mmCNVC_CFG0_COLOR_KEYER_CONTROL[0], sizeof(mmCNVC_CFG0_COLOR_KEYER_CONTROL)/sizeof(mmCNVC_CFG0_COLOR_KEYER_CONTROL[0]), 0, 0 }, + { "mmCNVC_CFG0_COLOR_KEYER_ALPHA", REG_MMIO, 0x0c4d, 2, &mmCNVC_CFG0_COLOR_KEYER_ALPHA[0], sizeof(mmCNVC_CFG0_COLOR_KEYER_ALPHA)/sizeof(mmCNVC_CFG0_COLOR_KEYER_ALPHA[0]), 0, 0 }, + { "mmCNVC_CFG0_COLOR_KEYER_RED", REG_MMIO, 0x0c4e, 2, &mmCNVC_CFG0_COLOR_KEYER_RED[0], sizeof(mmCNVC_CFG0_COLOR_KEYER_RED)/sizeof(mmCNVC_CFG0_COLOR_KEYER_RED[0]), 0, 0 }, + { "mmCNVC_CFG0_COLOR_KEYER_GREEN", REG_MMIO, 0x0c4f, 2, &mmCNVC_CFG0_COLOR_KEYER_GREEN[0], sizeof(mmCNVC_CFG0_COLOR_KEYER_GREEN)/sizeof(mmCNVC_CFG0_COLOR_KEYER_GREEN[0]), 0, 0 }, + { "mmCNVC_CFG0_COLOR_KEYER_BLUE", REG_MMIO, 0x0c50, 2, &mmCNVC_CFG0_COLOR_KEYER_BLUE[0], sizeof(mmCNVC_CFG0_COLOR_KEYER_BLUE)/sizeof(mmCNVC_CFG0_COLOR_KEYER_BLUE[0]), 0, 0 }, + { "mmCNVC_CUR0_CURSOR0_CONTROL", REG_MMIO, 0x0c58, 2, &mmCNVC_CUR0_CURSOR0_CONTROL[0], sizeof(mmCNVC_CUR0_CURSOR0_CONTROL)/sizeof(mmCNVC_CUR0_CURSOR0_CONTROL[0]), 0, 0 }, + { "mmCNVC_CUR0_CURSOR0_COLOR0", REG_MMIO, 0x0c59, 2, &mmCNVC_CUR0_CURSOR0_COLOR0[0], sizeof(mmCNVC_CUR0_CURSOR0_COLOR0)/sizeof(mmCNVC_CUR0_CURSOR0_COLOR0[0]), 0, 0 }, + { "mmCNVC_CUR0_CURSOR0_COLOR1", REG_MMIO, 0x0c5a, 2, &mmCNVC_CUR0_CURSOR0_COLOR1[0], sizeof(mmCNVC_CUR0_CURSOR0_COLOR1)/sizeof(mmCNVC_CUR0_CURSOR0_COLOR1[0]), 0, 0 }, + { "mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS", REG_MMIO, 0x0c5b, 2, &mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS[0], sizeof(mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS)/sizeof(mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS[0]), 0, 0 }, + { "mmDSCL0_SCL_COEF_RAM_TAP_SELECT", REG_MMIO, 0x0c62, 2, &mmDSCL0_SCL_COEF_RAM_TAP_SELECT[0], sizeof(mmDSCL0_SCL_COEF_RAM_TAP_SELECT)/sizeof(mmDSCL0_SCL_COEF_RAM_TAP_SELECT[0]), 0, 0 }, + { "mmDSCL0_SCL_COEF_RAM_TAP_DATA", REG_MMIO, 0x0c63, 2, &mmDSCL0_SCL_COEF_RAM_TAP_DATA[0], sizeof(mmDSCL0_SCL_COEF_RAM_TAP_DATA)/sizeof(mmDSCL0_SCL_COEF_RAM_TAP_DATA[0]), 0, 0 }, + { "mmDSCL0_SCL_MODE", REG_MMIO, 0x0c64, 2, &mmDSCL0_SCL_MODE[0], sizeof(mmDSCL0_SCL_MODE)/sizeof(mmDSCL0_SCL_MODE[0]), 0, 0 }, + { "mmDSCL0_SCL_TAP_CONTROL", REG_MMIO, 0x0c65, 2, &mmDSCL0_SCL_TAP_CONTROL[0], sizeof(mmDSCL0_SCL_TAP_CONTROL)/sizeof(mmDSCL0_SCL_TAP_CONTROL[0]), 0, 0 }, + { "mmDSCL0_DSCL_CONTROL", REG_MMIO, 0x0c66, 2, &mmDSCL0_DSCL_CONTROL[0], sizeof(mmDSCL0_DSCL_CONTROL)/sizeof(mmDSCL0_DSCL_CONTROL[0]), 0, 0 }, + { "mmDSCL0_DSCL_2TAP_CONTROL", REG_MMIO, 0x0c67, 2, &mmDSCL0_DSCL_2TAP_CONTROL[0], sizeof(mmDSCL0_DSCL_2TAP_CONTROL)/sizeof(mmDSCL0_DSCL_2TAP_CONTROL[0]), 0, 0 }, + { "mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL", REG_MMIO, 0x0c68, 2, &mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL[0], sizeof(mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL)/sizeof(mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL[0]), 0, 0 }, + { "mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO", REG_MMIO, 0x0c69, 2, &mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO[0], sizeof(mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO)/sizeof(mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO[0]), 0, 0 }, + { "mmDSCL0_SCL_HORZ_FILTER_INIT", REG_MMIO, 0x0c6a, 2, &mmDSCL0_SCL_HORZ_FILTER_INIT[0], sizeof(mmDSCL0_SCL_HORZ_FILTER_INIT)/sizeof(mmDSCL0_SCL_HORZ_FILTER_INIT[0]), 0, 0 }, + { "mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C", REG_MMIO, 0x0c6b, 2, &mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C[0], sizeof(mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C)/sizeof(mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C[0]), 0, 0 }, + { "mmDSCL0_SCL_HORZ_FILTER_INIT_C", REG_MMIO, 0x0c6c, 2, &mmDSCL0_SCL_HORZ_FILTER_INIT_C[0], sizeof(mmDSCL0_SCL_HORZ_FILTER_INIT_C)/sizeof(mmDSCL0_SCL_HORZ_FILTER_INIT_C[0]), 0, 0 }, + { "mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO", REG_MMIO, 0x0c6d, 2, &mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO[0], sizeof(mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO)/sizeof(mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO[0]), 0, 0 }, + { "mmDSCL0_SCL_VERT_FILTER_INIT", REG_MMIO, 0x0c6e, 2, &mmDSCL0_SCL_VERT_FILTER_INIT[0], sizeof(mmDSCL0_SCL_VERT_FILTER_INIT)/sizeof(mmDSCL0_SCL_VERT_FILTER_INIT[0]), 0, 0 }, + { "mmDSCL0_SCL_VERT_FILTER_INIT_BOT", REG_MMIO, 0x0c6f, 2, &mmDSCL0_SCL_VERT_FILTER_INIT_BOT[0], sizeof(mmDSCL0_SCL_VERT_FILTER_INIT_BOT)/sizeof(mmDSCL0_SCL_VERT_FILTER_INIT_BOT[0]), 0, 0 }, + { "mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C", REG_MMIO, 0x0c70, 2, &mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C[0], sizeof(mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C)/sizeof(mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C[0]), 0, 0 }, + { "mmDSCL0_SCL_VERT_FILTER_INIT_C", REG_MMIO, 0x0c71, 2, &mmDSCL0_SCL_VERT_FILTER_INIT_C[0], sizeof(mmDSCL0_SCL_VERT_FILTER_INIT_C)/sizeof(mmDSCL0_SCL_VERT_FILTER_INIT_C[0]), 0, 0 }, + { "mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C", REG_MMIO, 0x0c72, 2, &mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C[0], sizeof(mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C)/sizeof(mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C[0]), 0, 0 }, + { "mmDSCL0_SCL_BLACK_OFFSET", REG_MMIO, 0x0c73, 2, &mmDSCL0_SCL_BLACK_OFFSET[0], sizeof(mmDSCL0_SCL_BLACK_OFFSET)/sizeof(mmDSCL0_SCL_BLACK_OFFSET[0]), 0, 0 }, + { "mmDSCL0_DSCL_UPDATE", REG_MMIO, 0x0c74, 2, &mmDSCL0_DSCL_UPDATE[0], sizeof(mmDSCL0_DSCL_UPDATE)/sizeof(mmDSCL0_DSCL_UPDATE[0]), 0, 0 }, + { "mmDSCL0_DSCL_AUTOCAL", REG_MMIO, 0x0c75, 2, &mmDSCL0_DSCL_AUTOCAL[0], sizeof(mmDSCL0_DSCL_AUTOCAL)/sizeof(mmDSCL0_DSCL_AUTOCAL[0]), 0, 0 }, + { "mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT", REG_MMIO, 0x0c76, 2, &mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT[0], sizeof(mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT)/sizeof(mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT[0]), 0, 0 }, + { "mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM", REG_MMIO, 0x0c77, 2, &mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM[0], sizeof(mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM)/sizeof(mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM[0]), 0, 0 }, + { "mmDSCL0_OTG_H_BLANK", REG_MMIO, 0x0c78, 2, &mmDSCL0_OTG_H_BLANK[0], sizeof(mmDSCL0_OTG_H_BLANK)/sizeof(mmDSCL0_OTG_H_BLANK[0]), 0, 0 }, + { "mmDSCL0_OTG_V_BLANK", REG_MMIO, 0x0c79, 2, &mmDSCL0_OTG_V_BLANK[0], sizeof(mmDSCL0_OTG_V_BLANK)/sizeof(mmDSCL0_OTG_V_BLANK[0]), 0, 0 }, + { "mmDSCL0_RECOUT_START", REG_MMIO, 0x0c7a, 2, &mmDSCL0_RECOUT_START[0], sizeof(mmDSCL0_RECOUT_START)/sizeof(mmDSCL0_RECOUT_START[0]), 0, 0 }, + { "mmDSCL0_RECOUT_SIZE", REG_MMIO, 0x0c7b, 2, &mmDSCL0_RECOUT_SIZE[0], sizeof(mmDSCL0_RECOUT_SIZE)/sizeof(mmDSCL0_RECOUT_SIZE[0]), 0, 0 }, + { "mmDSCL0_MPC_SIZE", REG_MMIO, 0x0c7c, 2, &mmDSCL0_MPC_SIZE[0], sizeof(mmDSCL0_MPC_SIZE)/sizeof(mmDSCL0_MPC_SIZE[0]), 0, 0 }, + { "mmDSCL0_LB_DATA_FORMAT", REG_MMIO, 0x0c7d, 2, &mmDSCL0_LB_DATA_FORMAT[0], sizeof(mmDSCL0_LB_DATA_FORMAT)/sizeof(mmDSCL0_LB_DATA_FORMAT[0]), 0, 0 }, + { "mmDSCL0_LB_MEMORY_CTRL", REG_MMIO, 0x0c7e, 2, &mmDSCL0_LB_MEMORY_CTRL[0], sizeof(mmDSCL0_LB_MEMORY_CTRL)/sizeof(mmDSCL0_LB_MEMORY_CTRL[0]), 0, 0 }, + { "mmDSCL0_LB_V_COUNTER", REG_MMIO, 0x0c7f, 2, &mmDSCL0_LB_V_COUNTER[0], sizeof(mmDSCL0_LB_V_COUNTER)/sizeof(mmDSCL0_LB_V_COUNTER[0]), 0, 0 }, + { "mmDSCL0_DSCL_MEM_PWR_CTRL", REG_MMIO, 0x0c80, 2, &mmDSCL0_DSCL_MEM_PWR_CTRL[0], sizeof(mmDSCL0_DSCL_MEM_PWR_CTRL)/sizeof(mmDSCL0_DSCL_MEM_PWR_CTRL[0]), 0, 0 }, + { "mmDSCL0_DSCL_MEM_PWR_STATUS", REG_MMIO, 0x0c81, 2, &mmDSCL0_DSCL_MEM_PWR_STATUS[0], sizeof(mmDSCL0_DSCL_MEM_PWR_STATUS)/sizeof(mmDSCL0_DSCL_MEM_PWR_STATUS[0]), 0, 0 }, + { "mmDSCL0_OBUF_CONTROL", REG_MMIO, 0x0c82, 2, &mmDSCL0_OBUF_CONTROL[0], sizeof(mmDSCL0_OBUF_CONTROL)/sizeof(mmDSCL0_OBUF_CONTROL[0]), 0, 0 }, + { "mmDSCL0_OBUF_MEM_PWR_CTRL", REG_MMIO, 0x0c83, 2, &mmDSCL0_OBUF_MEM_PWR_CTRL[0], sizeof(mmDSCL0_OBUF_MEM_PWR_CTRL)/sizeof(mmDSCL0_OBUF_MEM_PWR_CTRL[0]), 0, 0 }, + { "mmCM0_CM_CONTROL", REG_MMIO, 0x0c92, 2, &mmCM0_CM_CONTROL[0], sizeof(mmCM0_CM_CONTROL)/sizeof(mmCM0_CM_CONTROL[0]), 0, 0 }, + { "mmCM0_CM_COMA_C11_C12", REG_MMIO, 0x0c93, 2, &mmCM0_CM_COMA_C11_C12[0], sizeof(mmCM0_CM_COMA_C11_C12)/sizeof(mmCM0_CM_COMA_C11_C12[0]), 0, 0 }, + { "mmCM0_CM_COMA_C13_C14", REG_MMIO, 0x0c94, 2, &mmCM0_CM_COMA_C13_C14[0], sizeof(mmCM0_CM_COMA_C13_C14)/sizeof(mmCM0_CM_COMA_C13_C14[0]), 0, 0 }, + { "mmCM0_CM_COMA_C21_C22", REG_MMIO, 0x0c95, 2, &mmCM0_CM_COMA_C21_C22[0], sizeof(mmCM0_CM_COMA_C21_C22)/sizeof(mmCM0_CM_COMA_C21_C22[0]), 0, 0 }, + { "mmCM0_CM_COMA_C23_C24", REG_MMIO, 0x0c96, 2, &mmCM0_CM_COMA_C23_C24[0], sizeof(mmCM0_CM_COMA_C23_C24)/sizeof(mmCM0_CM_COMA_C23_C24[0]), 0, 0 }, + { "mmCM0_CM_COMA_C31_C32", REG_MMIO, 0x0c97, 2, &mmCM0_CM_COMA_C31_C32[0], sizeof(mmCM0_CM_COMA_C31_C32)/sizeof(mmCM0_CM_COMA_C31_C32[0]), 0, 0 }, + { "mmCM0_CM_COMA_C33_C34", REG_MMIO, 0x0c98, 2, &mmCM0_CM_COMA_C33_C34[0], sizeof(mmCM0_CM_COMA_C33_C34)/sizeof(mmCM0_CM_COMA_C33_C34[0]), 0, 0 }, + { "mmCM0_CM_COMB_C11_C12", REG_MMIO, 0x0c99, 2, &mmCM0_CM_COMB_C11_C12[0], sizeof(mmCM0_CM_COMB_C11_C12)/sizeof(mmCM0_CM_COMB_C11_C12[0]), 0, 0 }, + { "mmCM0_CM_COMB_C13_C14", REG_MMIO, 0x0c9a, 2, &mmCM0_CM_COMB_C13_C14[0], sizeof(mmCM0_CM_COMB_C13_C14)/sizeof(mmCM0_CM_COMB_C13_C14[0]), 0, 0 }, + { "mmCM0_CM_COMB_C21_C22", REG_MMIO, 0x0c9b, 2, &mmCM0_CM_COMB_C21_C22[0], sizeof(mmCM0_CM_COMB_C21_C22)/sizeof(mmCM0_CM_COMB_C21_C22[0]), 0, 0 }, + { "mmCM0_CM_COMB_C23_C24", REG_MMIO, 0x0c9c, 2, &mmCM0_CM_COMB_C23_C24[0], sizeof(mmCM0_CM_COMB_C23_C24)/sizeof(mmCM0_CM_COMB_C23_C24[0]), 0, 0 }, + { "mmCM0_CM_COMB_C31_C32", REG_MMIO, 0x0c9d, 2, &mmCM0_CM_COMB_C31_C32[0], sizeof(mmCM0_CM_COMB_C31_C32)/sizeof(mmCM0_CM_COMB_C31_C32[0]), 0, 0 }, + { "mmCM0_CM_COMB_C33_C34", REG_MMIO, 0x0c9e, 2, &mmCM0_CM_COMB_C33_C34[0], sizeof(mmCM0_CM_COMB_C33_C34)/sizeof(mmCM0_CM_COMB_C33_C34[0]), 0, 0 }, + { "mmCM0_CM_IGAM_CONTROL", REG_MMIO, 0x0c9f, 2, &mmCM0_CM_IGAM_CONTROL[0], sizeof(mmCM0_CM_IGAM_CONTROL)/sizeof(mmCM0_CM_IGAM_CONTROL[0]), 0, 0 }, + { "mmCM0_CM_IGAM_LUT_RW_CONTROL", REG_MMIO, 0x0ca0, 2, &mmCM0_CM_IGAM_LUT_RW_CONTROL[0], sizeof(mmCM0_CM_IGAM_LUT_RW_CONTROL)/sizeof(mmCM0_CM_IGAM_LUT_RW_CONTROL[0]), 0, 0 }, + { "mmCM0_CM_IGAM_LUT_RW_INDEX", REG_MMIO, 0x0ca1, 2, &mmCM0_CM_IGAM_LUT_RW_INDEX[0], sizeof(mmCM0_CM_IGAM_LUT_RW_INDEX)/sizeof(mmCM0_CM_IGAM_LUT_RW_INDEX[0]), 0, 0 }, + { "mmCM0_CM_IGAM_LUT_SEQ_COLOR", REG_MMIO, 0x0ca2, 2, &mmCM0_CM_IGAM_LUT_SEQ_COLOR[0], sizeof(mmCM0_CM_IGAM_LUT_SEQ_COLOR)/sizeof(mmCM0_CM_IGAM_LUT_SEQ_COLOR[0]), 0, 0 }, + { "mmCM0_CM_IGAM_LUT_30_COLOR", REG_MMIO, 0x0ca3, 2, &mmCM0_CM_IGAM_LUT_30_COLOR[0], sizeof(mmCM0_CM_IGAM_LUT_30_COLOR)/sizeof(mmCM0_CM_IGAM_LUT_30_COLOR[0]), 0, 0 }, + { "mmCM0_CM_IGAM_LUT_PWL_DATA", REG_MMIO, 0x0ca4, 2, &mmCM0_CM_IGAM_LUT_PWL_DATA[0], sizeof(mmCM0_CM_IGAM_LUT_PWL_DATA)/sizeof(mmCM0_CM_IGAM_LUT_PWL_DATA[0]), 0, 0 }, + { "mmCM0_CM_IGAM_LUT_AUTOFILL", REG_MMIO, 0x0ca5, 2, &mmCM0_CM_IGAM_LUT_AUTOFILL[0], sizeof(mmCM0_CM_IGAM_LUT_AUTOFILL)/sizeof(mmCM0_CM_IGAM_LUT_AUTOFILL[0]), 0, 0 }, + { "mmCM0_CM_IGAM_LUT_BW_OFFSET_BLUE", REG_MMIO, 0x0ca6, 2, &mmCM0_CM_IGAM_LUT_BW_OFFSET_BLUE[0], sizeof(mmCM0_CM_IGAM_LUT_BW_OFFSET_BLUE)/sizeof(mmCM0_CM_IGAM_LUT_BW_OFFSET_BLUE[0]), 0, 0 }, + { "mmCM0_CM_IGAM_LUT_BW_OFFSET_GREEN", REG_MMIO, 0x0ca7, 2, &mmCM0_CM_IGAM_LUT_BW_OFFSET_GREEN[0], sizeof(mmCM0_CM_IGAM_LUT_BW_OFFSET_GREEN)/sizeof(mmCM0_CM_IGAM_LUT_BW_OFFSET_GREEN[0]), 0, 0 }, + { "mmCM0_CM_IGAM_LUT_BW_OFFSET_RED", REG_MMIO, 0x0ca8, 2, &mmCM0_CM_IGAM_LUT_BW_OFFSET_RED[0], sizeof(mmCM0_CM_IGAM_LUT_BW_OFFSET_RED)/sizeof(mmCM0_CM_IGAM_LUT_BW_OFFSET_RED[0]), 0, 0 }, + { "mmCM0_CM_ICSC_CONTROL", REG_MMIO, 0x0ca9, 2, &mmCM0_CM_ICSC_CONTROL[0], sizeof(mmCM0_CM_ICSC_CONTROL)/sizeof(mmCM0_CM_ICSC_CONTROL[0]), 0, 0 }, + { "mmCM0_CM_ICSC_C11_C12", REG_MMIO, 0x0caa, 2, &mmCM0_CM_ICSC_C11_C12[0], sizeof(mmCM0_CM_ICSC_C11_C12)/sizeof(mmCM0_CM_ICSC_C11_C12[0]), 0, 0 }, + { "mmCM0_CM_ICSC_C13_C14", REG_MMIO, 0x0cab, 2, &mmCM0_CM_ICSC_C13_C14[0], sizeof(mmCM0_CM_ICSC_C13_C14)/sizeof(mmCM0_CM_ICSC_C13_C14[0]), 0, 0 }, + { "mmCM0_CM_ICSC_C21_C22", REG_MMIO, 0x0cac, 2, &mmCM0_CM_ICSC_C21_C22[0], sizeof(mmCM0_CM_ICSC_C21_C22)/sizeof(mmCM0_CM_ICSC_C21_C22[0]), 0, 0 }, + { "mmCM0_CM_ICSC_C23_C24", REG_MMIO, 0x0cad, 2, &mmCM0_CM_ICSC_C23_C24[0], sizeof(mmCM0_CM_ICSC_C23_C24)/sizeof(mmCM0_CM_ICSC_C23_C24[0]), 0, 0 }, + { "mmCM0_CM_ICSC_C31_C32", REG_MMIO, 0x0cae, 2, &mmCM0_CM_ICSC_C31_C32[0], sizeof(mmCM0_CM_ICSC_C31_C32)/sizeof(mmCM0_CM_ICSC_C31_C32[0]), 0, 0 }, + { "mmCM0_CM_ICSC_C33_C34", REG_MMIO, 0x0caf, 2, &mmCM0_CM_ICSC_C33_C34[0], sizeof(mmCM0_CM_ICSC_C33_C34)/sizeof(mmCM0_CM_ICSC_C33_C34[0]), 0, 0 }, + { "mmCM0_CM_GAMUT_REMAP_CONTROL", REG_MMIO, 0x0cb0, 2, &mmCM0_CM_GAMUT_REMAP_CONTROL[0], sizeof(mmCM0_CM_GAMUT_REMAP_CONTROL)/sizeof(mmCM0_CM_GAMUT_REMAP_CONTROL[0]), 0, 0 }, + { "mmCM0_CM_GAMUT_REMAP_C11_C12", REG_MMIO, 0x0cb1, 2, &mmCM0_CM_GAMUT_REMAP_C11_C12[0], sizeof(mmCM0_CM_GAMUT_REMAP_C11_C12)/sizeof(mmCM0_CM_GAMUT_REMAP_C11_C12[0]), 0, 0 }, + { "mmCM0_CM_GAMUT_REMAP_C13_C14", REG_MMIO, 0x0cb2, 2, &mmCM0_CM_GAMUT_REMAP_C13_C14[0], sizeof(mmCM0_CM_GAMUT_REMAP_C13_C14)/sizeof(mmCM0_CM_GAMUT_REMAP_C13_C14[0]), 0, 0 }, + { "mmCM0_CM_GAMUT_REMAP_C21_C22", REG_MMIO, 0x0cb3, 2, &mmCM0_CM_GAMUT_REMAP_C21_C22[0], sizeof(mmCM0_CM_GAMUT_REMAP_C21_C22)/sizeof(mmCM0_CM_GAMUT_REMAP_C21_C22[0]), 0, 0 }, + { "mmCM0_CM_GAMUT_REMAP_C23_C24", REG_MMIO, 0x0cb4, 2, &mmCM0_CM_GAMUT_REMAP_C23_C24[0], sizeof(mmCM0_CM_GAMUT_REMAP_C23_C24)/sizeof(mmCM0_CM_GAMUT_REMAP_C23_C24[0]), 0, 0 }, + { "mmCM0_CM_GAMUT_REMAP_C31_C32", REG_MMIO, 0x0cb5, 2, &mmCM0_CM_GAMUT_REMAP_C31_C32[0], sizeof(mmCM0_CM_GAMUT_REMAP_C31_C32)/sizeof(mmCM0_CM_GAMUT_REMAP_C31_C32[0]), 0, 0 }, + { "mmCM0_CM_GAMUT_REMAP_C33_C34", REG_MMIO, 0x0cb6, 2, &mmCM0_CM_GAMUT_REMAP_C33_C34[0], sizeof(mmCM0_CM_GAMUT_REMAP_C33_C34)/sizeof(mmCM0_CM_GAMUT_REMAP_C33_C34[0]), 0, 0 }, + { "mmCM0_CM_OCSC_CONTROL", REG_MMIO, 0x0cb7, 2, &mmCM0_CM_OCSC_CONTROL[0], sizeof(mmCM0_CM_OCSC_CONTROL)/sizeof(mmCM0_CM_OCSC_CONTROL[0]), 0, 0 }, + { "mmCM0_CM_OCSC_C11_C12", REG_MMIO, 0x0cb8, 2, &mmCM0_CM_OCSC_C11_C12[0], sizeof(mmCM0_CM_OCSC_C11_C12)/sizeof(mmCM0_CM_OCSC_C11_C12[0]), 0, 0 }, + { "mmCM0_CM_OCSC_C13_C14", REG_MMIO, 0x0cb9, 2, &mmCM0_CM_OCSC_C13_C14[0], sizeof(mmCM0_CM_OCSC_C13_C14)/sizeof(mmCM0_CM_OCSC_C13_C14[0]), 0, 0 }, + { "mmCM0_CM_OCSC_C21_C22", REG_MMIO, 0x0cba, 2, &mmCM0_CM_OCSC_C21_C22[0], sizeof(mmCM0_CM_OCSC_C21_C22)/sizeof(mmCM0_CM_OCSC_C21_C22[0]), 0, 0 }, + { "mmCM0_CM_OCSC_C23_C24", REG_MMIO, 0x0cbb, 2, &mmCM0_CM_OCSC_C23_C24[0], sizeof(mmCM0_CM_OCSC_C23_C24)/sizeof(mmCM0_CM_OCSC_C23_C24[0]), 0, 0 }, + { "mmCM0_CM_OCSC_C31_C32", REG_MMIO, 0x0cbc, 2, &mmCM0_CM_OCSC_C31_C32[0], sizeof(mmCM0_CM_OCSC_C31_C32)/sizeof(mmCM0_CM_OCSC_C31_C32[0]), 0, 0 }, + { "mmCM0_CM_OCSC_C33_C34", REG_MMIO, 0x0cbd, 2, &mmCM0_CM_OCSC_C33_C34[0], sizeof(mmCM0_CM_OCSC_C33_C34)/sizeof(mmCM0_CM_OCSC_C33_C34[0]), 0, 0 }, + { "mmCM0_CM_BNS_VALUES_R", REG_MMIO, 0x0cbe, 2, &mmCM0_CM_BNS_VALUES_R[0], sizeof(mmCM0_CM_BNS_VALUES_R)/sizeof(mmCM0_CM_BNS_VALUES_R[0]), 0, 0 }, + { "mmCM0_CM_BNS_VALUES_G", REG_MMIO, 0x0cbf, 2, &mmCM0_CM_BNS_VALUES_G[0], sizeof(mmCM0_CM_BNS_VALUES_G)/sizeof(mmCM0_CM_BNS_VALUES_G[0]), 0, 0 }, + { "mmCM0_CM_BNS_VALUES_B", REG_MMIO, 0x0cc0, 2, &mmCM0_CM_BNS_VALUES_B[0], sizeof(mmCM0_CM_BNS_VALUES_B)/sizeof(mmCM0_CM_BNS_VALUES_B[0]), 0, 0 }, + { "mmCM0_CM_DGAM_CONTROL", REG_MMIO, 0x0cc1, 2, &mmCM0_CM_DGAM_CONTROL[0], sizeof(mmCM0_CM_DGAM_CONTROL)/sizeof(mmCM0_CM_DGAM_CONTROL[0]), 0, 0 }, + { "mmCM0_CM_DGAM_LUT_INDEX", REG_MMIO, 0x0cc2, 2, &mmCM0_CM_DGAM_LUT_INDEX[0], sizeof(mmCM0_CM_DGAM_LUT_INDEX)/sizeof(mmCM0_CM_DGAM_LUT_INDEX[0]), 0, 0 }, + { "mmCM0_CM_DGAM_LUT_DATA", REG_MMIO, 0x0cc3, 2, &mmCM0_CM_DGAM_LUT_DATA[0], sizeof(mmCM0_CM_DGAM_LUT_DATA)/sizeof(mmCM0_CM_DGAM_LUT_DATA[0]), 0, 0 }, + { "mmCM0_CM_DGAM_LUT_WRITE_EN_MASK", REG_MMIO, 0x0cc4, 2, &mmCM0_CM_DGAM_LUT_WRITE_EN_MASK[0], sizeof(mmCM0_CM_DGAM_LUT_WRITE_EN_MASK)/sizeof(mmCM0_CM_DGAM_LUT_WRITE_EN_MASK[0]), 0, 0 }, + { "mmCM0_CM_DGAM_RAMA_START_CNTL_B", REG_MMIO, 0x0cc5, 2, &mmCM0_CM_DGAM_RAMA_START_CNTL_B[0], sizeof(mmCM0_CM_DGAM_RAMA_START_CNTL_B)/sizeof(mmCM0_CM_DGAM_RAMA_START_CNTL_B[0]), 0, 0 }, + { "mmCM0_CM_DGAM_RAMA_START_CNTL_G", REG_MMIO, 0x0cc6, 2, &mmCM0_CM_DGAM_RAMA_START_CNTL_G[0], sizeof(mmCM0_CM_DGAM_RAMA_START_CNTL_G)/sizeof(mmCM0_CM_DGAM_RAMA_START_CNTL_G[0]), 0, 0 }, + { "mmCM0_CM_DGAM_RAMA_START_CNTL_R", REG_MMIO, 0x0cc7, 2, &mmCM0_CM_DGAM_RAMA_START_CNTL_R[0], sizeof(mmCM0_CM_DGAM_RAMA_START_CNTL_R)/sizeof(mmCM0_CM_DGAM_RAMA_START_CNTL_R[0]), 0, 0 }, + { "mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_B", REG_MMIO, 0x0cc8, 2, &mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_B[0], sizeof(mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_B)/sizeof(mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_B[0]), 0, 0 }, + { "mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_G", REG_MMIO, 0x0cc9, 2, &mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_G[0], sizeof(mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_G)/sizeof(mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_G[0]), 0, 0 }, + { "mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_R", REG_MMIO, 0x0cca, 2, &mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_R[0], sizeof(mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_R)/sizeof(mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_R[0]), 0, 0 }, + { "mmCM0_CM_DGAM_RAMA_END_CNTL1_B", REG_MMIO, 0x0ccb, 2, &mmCM0_CM_DGAM_RAMA_END_CNTL1_B[0], sizeof(mmCM0_CM_DGAM_RAMA_END_CNTL1_B)/sizeof(mmCM0_CM_DGAM_RAMA_END_CNTL1_B[0]), 0, 0 }, + { "mmCM0_CM_DGAM_RAMA_END_CNTL2_B", REG_MMIO, 0x0ccc, 2, &mmCM0_CM_DGAM_RAMA_END_CNTL2_B[0], sizeof(mmCM0_CM_DGAM_RAMA_END_CNTL2_B)/sizeof(mmCM0_CM_DGAM_RAMA_END_CNTL2_B[0]), 0, 0 }, + { "mmCM0_CM_DGAM_RAMA_END_CNTL1_G", REG_MMIO, 0x0ccd, 2, &mmCM0_CM_DGAM_RAMA_END_CNTL1_G[0], sizeof(mmCM0_CM_DGAM_RAMA_END_CNTL1_G)/sizeof(mmCM0_CM_DGAM_RAMA_END_CNTL1_G[0]), 0, 0 }, + { "mmCM0_CM_DGAM_RAMA_END_CNTL2_G", REG_MMIO, 0x0cce, 2, &mmCM0_CM_DGAM_RAMA_END_CNTL2_G[0], sizeof(mmCM0_CM_DGAM_RAMA_END_CNTL2_G)/sizeof(mmCM0_CM_DGAM_RAMA_END_CNTL2_G[0]), 0, 0 }, + { "mmCM0_CM_DGAM_RAMA_END_CNTL1_R", REG_MMIO, 0x0ccf, 2, &mmCM0_CM_DGAM_RAMA_END_CNTL1_R[0], sizeof(mmCM0_CM_DGAM_RAMA_END_CNTL1_R)/sizeof(mmCM0_CM_DGAM_RAMA_END_CNTL1_R[0]), 0, 0 }, + { "mmCM0_CM_DGAM_RAMA_END_CNTL2_R", REG_MMIO, 0x0cd0, 2, &mmCM0_CM_DGAM_RAMA_END_CNTL2_R[0], sizeof(mmCM0_CM_DGAM_RAMA_END_CNTL2_R)/sizeof(mmCM0_CM_DGAM_RAMA_END_CNTL2_R[0]), 0, 0 }, + { "mmCM0_CM_DGAM_RAMA_REGION_0_1", REG_MMIO, 0x0cd1, 2, &mmCM0_CM_DGAM_RAMA_REGION_0_1[0], sizeof(mmCM0_CM_DGAM_RAMA_REGION_0_1)/sizeof(mmCM0_CM_DGAM_RAMA_REGION_0_1[0]), 0, 0 }, + { "mmCM0_CM_DGAM_RAMA_REGION_2_3", REG_MMIO, 0x0cd2, 2, &mmCM0_CM_DGAM_RAMA_REGION_2_3[0], sizeof(mmCM0_CM_DGAM_RAMA_REGION_2_3)/sizeof(mmCM0_CM_DGAM_RAMA_REGION_2_3[0]), 0, 0 }, + { "mmCM0_CM_DGAM_RAMA_REGION_4_5", REG_MMIO, 0x0cd3, 2, &mmCM0_CM_DGAM_RAMA_REGION_4_5[0], sizeof(mmCM0_CM_DGAM_RAMA_REGION_4_5)/sizeof(mmCM0_CM_DGAM_RAMA_REGION_4_5[0]), 0, 0 }, + { "mmCM0_CM_DGAM_RAMA_REGION_6_7", REG_MMIO, 0x0cd4, 2, &mmCM0_CM_DGAM_RAMA_REGION_6_7[0], sizeof(mmCM0_CM_DGAM_RAMA_REGION_6_7)/sizeof(mmCM0_CM_DGAM_RAMA_REGION_6_7[0]), 0, 0 }, + { "mmCM0_CM_DGAM_RAMA_REGION_8_9", REG_MMIO, 0x0cd5, 2, &mmCM0_CM_DGAM_RAMA_REGION_8_9[0], sizeof(mmCM0_CM_DGAM_RAMA_REGION_8_9)/sizeof(mmCM0_CM_DGAM_RAMA_REGION_8_9[0]), 0, 0 }, + { "mmCM0_CM_DGAM_RAMA_REGION_10_11", REG_MMIO, 0x0cd6, 2, &mmCM0_CM_DGAM_RAMA_REGION_10_11[0], sizeof(mmCM0_CM_DGAM_RAMA_REGION_10_11)/sizeof(mmCM0_CM_DGAM_RAMA_REGION_10_11[0]), 0, 0 }, + { "mmCM0_CM_DGAM_RAMA_REGION_12_13", REG_MMIO, 0x0cd7, 2, &mmCM0_CM_DGAM_RAMA_REGION_12_13[0], sizeof(mmCM0_CM_DGAM_RAMA_REGION_12_13)/sizeof(mmCM0_CM_DGAM_RAMA_REGION_12_13[0]), 0, 0 }, + { "mmCM0_CM_DGAM_RAMA_REGION_14_15", REG_MMIO, 0x0cd8, 2, &mmCM0_CM_DGAM_RAMA_REGION_14_15[0], sizeof(mmCM0_CM_DGAM_RAMA_REGION_14_15)/sizeof(mmCM0_CM_DGAM_RAMA_REGION_14_15[0]), 0, 0 }, + { "mmCM0_CM_DGAM_RAMB_START_CNTL_B", REG_MMIO, 0x0cd9, 2, &mmCM0_CM_DGAM_RAMB_START_CNTL_B[0], sizeof(mmCM0_CM_DGAM_RAMB_START_CNTL_B)/sizeof(mmCM0_CM_DGAM_RAMB_START_CNTL_B[0]), 0, 0 }, + { "mmCM0_CM_DGAM_RAMB_START_CNTL_G", REG_MMIO, 0x0cda, 2, &mmCM0_CM_DGAM_RAMB_START_CNTL_G[0], sizeof(mmCM0_CM_DGAM_RAMB_START_CNTL_G)/sizeof(mmCM0_CM_DGAM_RAMB_START_CNTL_G[0]), 0, 0 }, + { "mmCM0_CM_DGAM_RAMB_START_CNTL_R", REG_MMIO, 0x0cdb, 2, &mmCM0_CM_DGAM_RAMB_START_CNTL_R[0], sizeof(mmCM0_CM_DGAM_RAMB_START_CNTL_R)/sizeof(mmCM0_CM_DGAM_RAMB_START_CNTL_R[0]), 0, 0 }, + { "mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_B", REG_MMIO, 0x0cdc, 2, &mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_B[0], sizeof(mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_B)/sizeof(mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_B[0]), 0, 0 }, + { "mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_G", REG_MMIO, 0x0cdd, 2, &mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_G[0], sizeof(mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_G)/sizeof(mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_G[0]), 0, 0 }, + { "mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_R", REG_MMIO, 0x0cde, 2, &mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_R[0], sizeof(mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_R)/sizeof(mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_R[0]), 0, 0 }, + { "mmCM0_CM_DGAM_RAMB_END_CNTL1_B", REG_MMIO, 0x0cdf, 2, &mmCM0_CM_DGAM_RAMB_END_CNTL1_B[0], sizeof(mmCM0_CM_DGAM_RAMB_END_CNTL1_B)/sizeof(mmCM0_CM_DGAM_RAMB_END_CNTL1_B[0]), 0, 0 }, + { "mmCM0_CM_DGAM_RAMB_END_CNTL2_B", REG_MMIO, 0x0ce0, 2, &mmCM0_CM_DGAM_RAMB_END_CNTL2_B[0], sizeof(mmCM0_CM_DGAM_RAMB_END_CNTL2_B)/sizeof(mmCM0_CM_DGAM_RAMB_END_CNTL2_B[0]), 0, 0 }, + { "mmCM0_CM_DGAM_RAMB_END_CNTL1_G", REG_MMIO, 0x0ce1, 2, &mmCM0_CM_DGAM_RAMB_END_CNTL1_G[0], sizeof(mmCM0_CM_DGAM_RAMB_END_CNTL1_G)/sizeof(mmCM0_CM_DGAM_RAMB_END_CNTL1_G[0]), 0, 0 }, + { "mmCM0_CM_DGAM_RAMB_END_CNTL2_G", REG_MMIO, 0x0ce2, 2, &mmCM0_CM_DGAM_RAMB_END_CNTL2_G[0], sizeof(mmCM0_CM_DGAM_RAMB_END_CNTL2_G)/sizeof(mmCM0_CM_DGAM_RAMB_END_CNTL2_G[0]), 0, 0 }, + { "mmCM0_CM_DGAM_RAMB_END_CNTL1_R", REG_MMIO, 0x0ce3, 2, &mmCM0_CM_DGAM_RAMB_END_CNTL1_R[0], sizeof(mmCM0_CM_DGAM_RAMB_END_CNTL1_R)/sizeof(mmCM0_CM_DGAM_RAMB_END_CNTL1_R[0]), 0, 0 }, + { "mmCM0_CM_DGAM_RAMB_END_CNTL2_R", REG_MMIO, 0x0ce4, 2, &mmCM0_CM_DGAM_RAMB_END_CNTL2_R[0], sizeof(mmCM0_CM_DGAM_RAMB_END_CNTL2_R)/sizeof(mmCM0_CM_DGAM_RAMB_END_CNTL2_R[0]), 0, 0 }, + { "mmCM0_CM_DGAM_RAMB_REGION_0_1", REG_MMIO, 0x0ce5, 2, &mmCM0_CM_DGAM_RAMB_REGION_0_1[0], sizeof(mmCM0_CM_DGAM_RAMB_REGION_0_1)/sizeof(mmCM0_CM_DGAM_RAMB_REGION_0_1[0]), 0, 0 }, + { "mmCM0_CM_DGAM_RAMB_REGION_2_3", REG_MMIO, 0x0ce6, 2, &mmCM0_CM_DGAM_RAMB_REGION_2_3[0], sizeof(mmCM0_CM_DGAM_RAMB_REGION_2_3)/sizeof(mmCM0_CM_DGAM_RAMB_REGION_2_3[0]), 0, 0 }, + { "mmCM0_CM_DGAM_RAMB_REGION_4_5", REG_MMIO, 0x0ce7, 2, &mmCM0_CM_DGAM_RAMB_REGION_4_5[0], sizeof(mmCM0_CM_DGAM_RAMB_REGION_4_5)/sizeof(mmCM0_CM_DGAM_RAMB_REGION_4_5[0]), 0, 0 }, + { "mmCM0_CM_DGAM_RAMB_REGION_6_7", REG_MMIO, 0x0ce8, 2, &mmCM0_CM_DGAM_RAMB_REGION_6_7[0], sizeof(mmCM0_CM_DGAM_RAMB_REGION_6_7)/sizeof(mmCM0_CM_DGAM_RAMB_REGION_6_7[0]), 0, 0 }, + { "mmCM0_CM_DGAM_RAMB_REGION_8_9", REG_MMIO, 0x0ce9, 2, &mmCM0_CM_DGAM_RAMB_REGION_8_9[0], sizeof(mmCM0_CM_DGAM_RAMB_REGION_8_9)/sizeof(mmCM0_CM_DGAM_RAMB_REGION_8_9[0]), 0, 0 }, + { "mmCM0_CM_DGAM_RAMB_REGION_10_11", REG_MMIO, 0x0cea, 2, &mmCM0_CM_DGAM_RAMB_REGION_10_11[0], sizeof(mmCM0_CM_DGAM_RAMB_REGION_10_11)/sizeof(mmCM0_CM_DGAM_RAMB_REGION_10_11[0]), 0, 0 }, + { "mmCM0_CM_DGAM_RAMB_REGION_12_13", REG_MMIO, 0x0ceb, 2, &mmCM0_CM_DGAM_RAMB_REGION_12_13[0], sizeof(mmCM0_CM_DGAM_RAMB_REGION_12_13)/sizeof(mmCM0_CM_DGAM_RAMB_REGION_12_13[0]), 0, 0 }, + { "mmCM0_CM_DGAM_RAMB_REGION_14_15", REG_MMIO, 0x0cec, 2, &mmCM0_CM_DGAM_RAMB_REGION_14_15[0], sizeof(mmCM0_CM_DGAM_RAMB_REGION_14_15)/sizeof(mmCM0_CM_DGAM_RAMB_REGION_14_15[0]), 0, 0 }, + { "mmCM0_CM_RGAM_CONTROL", REG_MMIO, 0x0ced, 2, &mmCM0_CM_RGAM_CONTROL[0], sizeof(mmCM0_CM_RGAM_CONTROL)/sizeof(mmCM0_CM_RGAM_CONTROL[0]), 0, 0 }, + { "mmCM0_CM_RGAM_LUT_INDEX", REG_MMIO, 0x0cee, 2, &mmCM0_CM_RGAM_LUT_INDEX[0], sizeof(mmCM0_CM_RGAM_LUT_INDEX)/sizeof(mmCM0_CM_RGAM_LUT_INDEX[0]), 0, 0 }, + { "mmCM0_CM_RGAM_LUT_DATA", REG_MMIO, 0x0cef, 2, &mmCM0_CM_RGAM_LUT_DATA[0], sizeof(mmCM0_CM_RGAM_LUT_DATA)/sizeof(mmCM0_CM_RGAM_LUT_DATA[0]), 0, 0 }, + { "mmCM0_CM_RGAM_LUT_WRITE_EN_MASK", REG_MMIO, 0x0cf0, 2, &mmCM0_CM_RGAM_LUT_WRITE_EN_MASK[0], sizeof(mmCM0_CM_RGAM_LUT_WRITE_EN_MASK)/sizeof(mmCM0_CM_RGAM_LUT_WRITE_EN_MASK[0]), 0, 0 }, + { "mmCM0_CM_RGAM_RAMA_START_CNTL_B", REG_MMIO, 0x0cf1, 2, &mmCM0_CM_RGAM_RAMA_START_CNTL_B[0], sizeof(mmCM0_CM_RGAM_RAMA_START_CNTL_B)/sizeof(mmCM0_CM_RGAM_RAMA_START_CNTL_B[0]), 0, 0 }, + { "mmCM0_CM_RGAM_RAMA_START_CNTL_G", REG_MMIO, 0x0cf2, 2, &mmCM0_CM_RGAM_RAMA_START_CNTL_G[0], sizeof(mmCM0_CM_RGAM_RAMA_START_CNTL_G)/sizeof(mmCM0_CM_RGAM_RAMA_START_CNTL_G[0]), 0, 0 }, + { "mmCM0_CM_RGAM_RAMA_START_CNTL_R", REG_MMIO, 0x0cf3, 2, &mmCM0_CM_RGAM_RAMA_START_CNTL_R[0], sizeof(mmCM0_CM_RGAM_RAMA_START_CNTL_R)/sizeof(mmCM0_CM_RGAM_RAMA_START_CNTL_R[0]), 0, 0 }, + { "mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_B", REG_MMIO, 0x0cf4, 2, &mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_B[0], sizeof(mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_B)/sizeof(mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_B[0]), 0, 0 }, + { "mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_G", REG_MMIO, 0x0cf5, 2, &mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_G[0], sizeof(mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_G)/sizeof(mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_G[0]), 0, 0 }, + { "mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_R", REG_MMIO, 0x0cf6, 2, &mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_R[0], sizeof(mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_R)/sizeof(mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_R[0]), 0, 0 }, + { "mmCM0_CM_RGAM_RAMA_END_CNTL1_B", REG_MMIO, 0x0cf7, 2, &mmCM0_CM_RGAM_RAMA_END_CNTL1_B[0], sizeof(mmCM0_CM_RGAM_RAMA_END_CNTL1_B)/sizeof(mmCM0_CM_RGAM_RAMA_END_CNTL1_B[0]), 0, 0 }, + { "mmCM0_CM_RGAM_RAMA_END_CNTL2_B", REG_MMIO, 0x0cf8, 2, &mmCM0_CM_RGAM_RAMA_END_CNTL2_B[0], sizeof(mmCM0_CM_RGAM_RAMA_END_CNTL2_B)/sizeof(mmCM0_CM_RGAM_RAMA_END_CNTL2_B[0]), 0, 0 }, + { "mmCM0_CM_RGAM_RAMA_END_CNTL1_G", REG_MMIO, 0x0cf9, 2, &mmCM0_CM_RGAM_RAMA_END_CNTL1_G[0], sizeof(mmCM0_CM_RGAM_RAMA_END_CNTL1_G)/sizeof(mmCM0_CM_RGAM_RAMA_END_CNTL1_G[0]), 0, 0 }, + { "mmCM0_CM_RGAM_RAMA_END_CNTL2_G", REG_MMIO, 0x0cfa, 2, &mmCM0_CM_RGAM_RAMA_END_CNTL2_G[0], sizeof(mmCM0_CM_RGAM_RAMA_END_CNTL2_G)/sizeof(mmCM0_CM_RGAM_RAMA_END_CNTL2_G[0]), 0, 0 }, + { "mmCM0_CM_RGAM_RAMA_END_CNTL1_R", REG_MMIO, 0x0cfb, 2, &mmCM0_CM_RGAM_RAMA_END_CNTL1_R[0], sizeof(mmCM0_CM_RGAM_RAMA_END_CNTL1_R)/sizeof(mmCM0_CM_RGAM_RAMA_END_CNTL1_R[0]), 0, 0 }, + { "mmCM0_CM_RGAM_RAMA_END_CNTL2_R", REG_MMIO, 0x0cfc, 2, &mmCM0_CM_RGAM_RAMA_END_CNTL2_R[0], sizeof(mmCM0_CM_RGAM_RAMA_END_CNTL2_R)/sizeof(mmCM0_CM_RGAM_RAMA_END_CNTL2_R[0]), 0, 0 }, + { "mmCM0_CM_RGAM_RAMA_REGION_0_1", REG_MMIO, 0x0cfd, 2, &mmCM0_CM_RGAM_RAMA_REGION_0_1[0], sizeof(mmCM0_CM_RGAM_RAMA_REGION_0_1)/sizeof(mmCM0_CM_RGAM_RAMA_REGION_0_1[0]), 0, 0 }, + { "mmCM0_CM_RGAM_RAMA_REGION_2_3", REG_MMIO, 0x0cfe, 2, &mmCM0_CM_RGAM_RAMA_REGION_2_3[0], sizeof(mmCM0_CM_RGAM_RAMA_REGION_2_3)/sizeof(mmCM0_CM_RGAM_RAMA_REGION_2_3[0]), 0, 0 }, + { "mmCM0_CM_RGAM_RAMA_REGION_4_5", REG_MMIO, 0x0cff, 2, &mmCM0_CM_RGAM_RAMA_REGION_4_5[0], sizeof(mmCM0_CM_RGAM_RAMA_REGION_4_5)/sizeof(mmCM0_CM_RGAM_RAMA_REGION_4_5[0]), 0, 0 }, + { "mmCM0_CM_RGAM_RAMA_REGION_6_7", REG_MMIO, 0x0d00, 2, &mmCM0_CM_RGAM_RAMA_REGION_6_7[0], sizeof(mmCM0_CM_RGAM_RAMA_REGION_6_7)/sizeof(mmCM0_CM_RGAM_RAMA_REGION_6_7[0]), 0, 0 }, + { "mmCM0_CM_RGAM_RAMA_REGION_8_9", REG_MMIO, 0x0d01, 2, &mmCM0_CM_RGAM_RAMA_REGION_8_9[0], sizeof(mmCM0_CM_RGAM_RAMA_REGION_8_9)/sizeof(mmCM0_CM_RGAM_RAMA_REGION_8_9[0]), 0, 0 }, + { "mmCM0_CM_RGAM_RAMA_REGION_10_11", REG_MMIO, 0x0d02, 2, &mmCM0_CM_RGAM_RAMA_REGION_10_11[0], sizeof(mmCM0_CM_RGAM_RAMA_REGION_10_11)/sizeof(mmCM0_CM_RGAM_RAMA_REGION_10_11[0]), 0, 0 }, + { "mmCM0_CM_RGAM_RAMA_REGION_12_13", REG_MMIO, 0x0d03, 2, &mmCM0_CM_RGAM_RAMA_REGION_12_13[0], sizeof(mmCM0_CM_RGAM_RAMA_REGION_12_13)/sizeof(mmCM0_CM_RGAM_RAMA_REGION_12_13[0]), 0, 0 }, + { "mmCM0_CM_RGAM_RAMA_REGION_14_15", REG_MMIO, 0x0d04, 2, &mmCM0_CM_RGAM_RAMA_REGION_14_15[0], sizeof(mmCM0_CM_RGAM_RAMA_REGION_14_15)/sizeof(mmCM0_CM_RGAM_RAMA_REGION_14_15[0]), 0, 0 }, + { "mmCM0_CM_RGAM_RAMA_REGION_16_17", REG_MMIO, 0x0d05, 2, &mmCM0_CM_RGAM_RAMA_REGION_16_17[0], sizeof(mmCM0_CM_RGAM_RAMA_REGION_16_17)/sizeof(mmCM0_CM_RGAM_RAMA_REGION_16_17[0]), 0, 0 }, + { "mmCM0_CM_RGAM_RAMA_REGION_18_19", REG_MMIO, 0x0d06, 2, &mmCM0_CM_RGAM_RAMA_REGION_18_19[0], sizeof(mmCM0_CM_RGAM_RAMA_REGION_18_19)/sizeof(mmCM0_CM_RGAM_RAMA_REGION_18_19[0]), 0, 0 }, + { "mmCM0_CM_RGAM_RAMA_REGION_20_21", REG_MMIO, 0x0d07, 2, &mmCM0_CM_RGAM_RAMA_REGION_20_21[0], sizeof(mmCM0_CM_RGAM_RAMA_REGION_20_21)/sizeof(mmCM0_CM_RGAM_RAMA_REGION_20_21[0]), 0, 0 }, + { "mmCM0_CM_RGAM_RAMA_REGION_22_23", REG_MMIO, 0x0d08, 2, &mmCM0_CM_RGAM_RAMA_REGION_22_23[0], sizeof(mmCM0_CM_RGAM_RAMA_REGION_22_23)/sizeof(mmCM0_CM_RGAM_RAMA_REGION_22_23[0]), 0, 0 }, + { "mmCM0_CM_RGAM_RAMA_REGION_24_25", REG_MMIO, 0x0d09, 2, &mmCM0_CM_RGAM_RAMA_REGION_24_25[0], sizeof(mmCM0_CM_RGAM_RAMA_REGION_24_25)/sizeof(mmCM0_CM_RGAM_RAMA_REGION_24_25[0]), 0, 0 }, + { "mmCM0_CM_RGAM_RAMA_REGION_26_27", REG_MMIO, 0x0d0a, 2, &mmCM0_CM_RGAM_RAMA_REGION_26_27[0], sizeof(mmCM0_CM_RGAM_RAMA_REGION_26_27)/sizeof(mmCM0_CM_RGAM_RAMA_REGION_26_27[0]), 0, 0 }, + { "mmCM0_CM_RGAM_RAMA_REGION_28_29", REG_MMIO, 0x0d0b, 2, &mmCM0_CM_RGAM_RAMA_REGION_28_29[0], sizeof(mmCM0_CM_RGAM_RAMA_REGION_28_29)/sizeof(mmCM0_CM_RGAM_RAMA_REGION_28_29[0]), 0, 0 }, + { "mmCM0_CM_RGAM_RAMA_REGION_30_31", REG_MMIO, 0x0d0c, 2, &mmCM0_CM_RGAM_RAMA_REGION_30_31[0], sizeof(mmCM0_CM_RGAM_RAMA_REGION_30_31)/sizeof(mmCM0_CM_RGAM_RAMA_REGION_30_31[0]), 0, 0 }, + { "mmCM0_CM_RGAM_RAMA_REGION_32_33", REG_MMIO, 0x0d0d, 2, &mmCM0_CM_RGAM_RAMA_REGION_32_33[0], sizeof(mmCM0_CM_RGAM_RAMA_REGION_32_33)/sizeof(mmCM0_CM_RGAM_RAMA_REGION_32_33[0]), 0, 0 }, + { "mmCM0_CM_RGAM_RAMB_START_CNTL_B", REG_MMIO, 0x0d0e, 2, &mmCM0_CM_RGAM_RAMB_START_CNTL_B[0], sizeof(mmCM0_CM_RGAM_RAMB_START_CNTL_B)/sizeof(mmCM0_CM_RGAM_RAMB_START_CNTL_B[0]), 0, 0 }, + { "mmCM0_CM_RGAM_RAMB_START_CNTL_G", REG_MMIO, 0x0d0f, 2, &mmCM0_CM_RGAM_RAMB_START_CNTL_G[0], sizeof(mmCM0_CM_RGAM_RAMB_START_CNTL_G)/sizeof(mmCM0_CM_RGAM_RAMB_START_CNTL_G[0]), 0, 0 }, + { "mmCM0_CM_RGAM_RAMB_START_CNTL_R", REG_MMIO, 0x0d10, 2, &mmCM0_CM_RGAM_RAMB_START_CNTL_R[0], sizeof(mmCM0_CM_RGAM_RAMB_START_CNTL_R)/sizeof(mmCM0_CM_RGAM_RAMB_START_CNTL_R[0]), 0, 0 }, + { "mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_B", REG_MMIO, 0x0d11, 2, &mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_B[0], sizeof(mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_B)/sizeof(mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_B[0]), 0, 0 }, + { "mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_G", REG_MMIO, 0x0d12, 2, &mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_G[0], sizeof(mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_G)/sizeof(mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_G[0]), 0, 0 }, + { "mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_R", REG_MMIO, 0x0d13, 2, &mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_R[0], sizeof(mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_R)/sizeof(mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_R[0]), 0, 0 }, + { "mmCM0_CM_RGAM_RAMB_END_CNTL1_B", REG_MMIO, 0x0d14, 2, &mmCM0_CM_RGAM_RAMB_END_CNTL1_B[0], sizeof(mmCM0_CM_RGAM_RAMB_END_CNTL1_B)/sizeof(mmCM0_CM_RGAM_RAMB_END_CNTL1_B[0]), 0, 0 }, + { "mmCM0_CM_RGAM_RAMB_END_CNTL2_B", REG_MMIO, 0x0d15, 2, &mmCM0_CM_RGAM_RAMB_END_CNTL2_B[0], sizeof(mmCM0_CM_RGAM_RAMB_END_CNTL2_B)/sizeof(mmCM0_CM_RGAM_RAMB_END_CNTL2_B[0]), 0, 0 }, + { "mmCM0_CM_RGAM_RAMB_END_CNTL1_G", REG_MMIO, 0x0d16, 2, &mmCM0_CM_RGAM_RAMB_END_CNTL1_G[0], sizeof(mmCM0_CM_RGAM_RAMB_END_CNTL1_G)/sizeof(mmCM0_CM_RGAM_RAMB_END_CNTL1_G[0]), 0, 0 }, + { "mmCM0_CM_RGAM_RAMB_END_CNTL2_G", REG_MMIO, 0x0d17, 2, &mmCM0_CM_RGAM_RAMB_END_CNTL2_G[0], sizeof(mmCM0_CM_RGAM_RAMB_END_CNTL2_G)/sizeof(mmCM0_CM_RGAM_RAMB_END_CNTL2_G[0]), 0, 0 }, + { "mmCM0_CM_RGAM_RAMB_END_CNTL1_R", REG_MMIO, 0x0d18, 2, &mmCM0_CM_RGAM_RAMB_END_CNTL1_R[0], sizeof(mmCM0_CM_RGAM_RAMB_END_CNTL1_R)/sizeof(mmCM0_CM_RGAM_RAMB_END_CNTL1_R[0]), 0, 0 }, + { "mmCM0_CM_RGAM_RAMB_END_CNTL2_R", REG_MMIO, 0x0d19, 2, &mmCM0_CM_RGAM_RAMB_END_CNTL2_R[0], sizeof(mmCM0_CM_RGAM_RAMB_END_CNTL2_R)/sizeof(mmCM0_CM_RGAM_RAMB_END_CNTL2_R[0]), 0, 0 }, + { "mmCM0_CM_RGAM_RAMB_REGION_0_1", REG_MMIO, 0x0d1a, 2, &mmCM0_CM_RGAM_RAMB_REGION_0_1[0], sizeof(mmCM0_CM_RGAM_RAMB_REGION_0_1)/sizeof(mmCM0_CM_RGAM_RAMB_REGION_0_1[0]), 0, 0 }, + { "mmCM0_CM_RGAM_RAMB_REGION_2_3", REG_MMIO, 0x0d1b, 2, &mmCM0_CM_RGAM_RAMB_REGION_2_3[0], sizeof(mmCM0_CM_RGAM_RAMB_REGION_2_3)/sizeof(mmCM0_CM_RGAM_RAMB_REGION_2_3[0]), 0, 0 }, + { "mmCM0_CM_RGAM_RAMB_REGION_4_5", REG_MMIO, 0x0d1c, 2, &mmCM0_CM_RGAM_RAMB_REGION_4_5[0], sizeof(mmCM0_CM_RGAM_RAMB_REGION_4_5)/sizeof(mmCM0_CM_RGAM_RAMB_REGION_4_5[0]), 0, 0 }, + { "mmCM0_CM_RGAM_RAMB_REGION_6_7", REG_MMIO, 0x0d1d, 2, &mmCM0_CM_RGAM_RAMB_REGION_6_7[0], sizeof(mmCM0_CM_RGAM_RAMB_REGION_6_7)/sizeof(mmCM0_CM_RGAM_RAMB_REGION_6_7[0]), 0, 0 }, + { "mmCM0_CM_RGAM_RAMB_REGION_8_9", REG_MMIO, 0x0d1e, 2, &mmCM0_CM_RGAM_RAMB_REGION_8_9[0], sizeof(mmCM0_CM_RGAM_RAMB_REGION_8_9)/sizeof(mmCM0_CM_RGAM_RAMB_REGION_8_9[0]), 0, 0 }, + { "mmCM0_CM_RGAM_RAMB_REGION_10_11", REG_MMIO, 0x0d1f, 2, &mmCM0_CM_RGAM_RAMB_REGION_10_11[0], sizeof(mmCM0_CM_RGAM_RAMB_REGION_10_11)/sizeof(mmCM0_CM_RGAM_RAMB_REGION_10_11[0]), 0, 0 }, + { "mmCM0_CM_RGAM_RAMB_REGION_12_13", REG_MMIO, 0x0d20, 2, &mmCM0_CM_RGAM_RAMB_REGION_12_13[0], sizeof(mmCM0_CM_RGAM_RAMB_REGION_12_13)/sizeof(mmCM0_CM_RGAM_RAMB_REGION_12_13[0]), 0, 0 }, + { "mmCM0_CM_RGAM_RAMB_REGION_14_15", REG_MMIO, 0x0d21, 2, &mmCM0_CM_RGAM_RAMB_REGION_14_15[0], sizeof(mmCM0_CM_RGAM_RAMB_REGION_14_15)/sizeof(mmCM0_CM_RGAM_RAMB_REGION_14_15[0]), 0, 0 }, + { "mmCM0_CM_RGAM_RAMB_REGION_16_17", REG_MMIO, 0x0d22, 2, &mmCM0_CM_RGAM_RAMB_REGION_16_17[0], sizeof(mmCM0_CM_RGAM_RAMB_REGION_16_17)/sizeof(mmCM0_CM_RGAM_RAMB_REGION_16_17[0]), 0, 0 }, + { "mmCM0_CM_RGAM_RAMB_REGION_18_19", REG_MMIO, 0x0d23, 2, &mmCM0_CM_RGAM_RAMB_REGION_18_19[0], sizeof(mmCM0_CM_RGAM_RAMB_REGION_18_19)/sizeof(mmCM0_CM_RGAM_RAMB_REGION_18_19[0]), 0, 0 }, + { "mmCM0_CM_RGAM_RAMB_REGION_20_21", REG_MMIO, 0x0d24, 2, &mmCM0_CM_RGAM_RAMB_REGION_20_21[0], sizeof(mmCM0_CM_RGAM_RAMB_REGION_20_21)/sizeof(mmCM0_CM_RGAM_RAMB_REGION_20_21[0]), 0, 0 }, + { "mmCM0_CM_RGAM_RAMB_REGION_22_23", REG_MMIO, 0x0d25, 2, &mmCM0_CM_RGAM_RAMB_REGION_22_23[0], sizeof(mmCM0_CM_RGAM_RAMB_REGION_22_23)/sizeof(mmCM0_CM_RGAM_RAMB_REGION_22_23[0]), 0, 0 }, + { "mmCM0_CM_RGAM_RAMB_REGION_24_25", REG_MMIO, 0x0d26, 2, &mmCM0_CM_RGAM_RAMB_REGION_24_25[0], sizeof(mmCM0_CM_RGAM_RAMB_REGION_24_25)/sizeof(mmCM0_CM_RGAM_RAMB_REGION_24_25[0]), 0, 0 }, + { "mmCM0_CM_RGAM_RAMB_REGION_26_27", REG_MMIO, 0x0d27, 2, &mmCM0_CM_RGAM_RAMB_REGION_26_27[0], sizeof(mmCM0_CM_RGAM_RAMB_REGION_26_27)/sizeof(mmCM0_CM_RGAM_RAMB_REGION_26_27[0]), 0, 0 }, + { "mmCM0_CM_RGAM_RAMB_REGION_28_29", REG_MMIO, 0x0d28, 2, &mmCM0_CM_RGAM_RAMB_REGION_28_29[0], sizeof(mmCM0_CM_RGAM_RAMB_REGION_28_29)/sizeof(mmCM0_CM_RGAM_RAMB_REGION_28_29[0]), 0, 0 }, + { "mmCM0_CM_RGAM_RAMB_REGION_30_31", REG_MMIO, 0x0d29, 2, &mmCM0_CM_RGAM_RAMB_REGION_30_31[0], sizeof(mmCM0_CM_RGAM_RAMB_REGION_30_31)/sizeof(mmCM0_CM_RGAM_RAMB_REGION_30_31[0]), 0, 0 }, + { "mmCM0_CM_RGAM_RAMB_REGION_32_33", REG_MMIO, 0x0d2a, 2, &mmCM0_CM_RGAM_RAMB_REGION_32_33[0], sizeof(mmCM0_CM_RGAM_RAMB_REGION_32_33)/sizeof(mmCM0_CM_RGAM_RAMB_REGION_32_33[0]), 0, 0 }, + { "mmCM0_CM_HDR_MULT_COEF", REG_MMIO, 0x0d2b, 2, &mmCM0_CM_HDR_MULT_COEF[0], sizeof(mmCM0_CM_HDR_MULT_COEF)/sizeof(mmCM0_CM_HDR_MULT_COEF[0]), 0, 0 }, + { "mmCM0_CM_RANGE_CLAMP_CONTROL_R", REG_MMIO, 0x0d2c, 2, &mmCM0_CM_RANGE_CLAMP_CONTROL_R[0], sizeof(mmCM0_CM_RANGE_CLAMP_CONTROL_R)/sizeof(mmCM0_CM_RANGE_CLAMP_CONTROL_R[0]), 0, 0 }, + { "mmCM0_CM_RANGE_CLAMP_CONTROL_G", REG_MMIO, 0x0d2d, 2, &mmCM0_CM_RANGE_CLAMP_CONTROL_G[0], sizeof(mmCM0_CM_RANGE_CLAMP_CONTROL_G)/sizeof(mmCM0_CM_RANGE_CLAMP_CONTROL_G[0]), 0, 0 }, + { "mmCM0_CM_RANGE_CLAMP_CONTROL_B", REG_MMIO, 0x0d2e, 2, &mmCM0_CM_RANGE_CLAMP_CONTROL_B[0], sizeof(mmCM0_CM_RANGE_CLAMP_CONTROL_B)/sizeof(mmCM0_CM_RANGE_CLAMP_CONTROL_B[0]), 0, 0 }, + { "mmCM0_CM_DENORM_CONTROL", REG_MMIO, 0x0d2f, 2, &mmCM0_CM_DENORM_CONTROL[0], sizeof(mmCM0_CM_DENORM_CONTROL)/sizeof(mmCM0_CM_DENORM_CONTROL[0]), 0, 0 }, + { "mmCM0_CM_CMOUT_CONTROL", REG_MMIO, 0x0d30, 2, &mmCM0_CM_CMOUT_CONTROL[0], sizeof(mmCM0_CM_CMOUT_CONTROL)/sizeof(mmCM0_CM_CMOUT_CONTROL[0]), 0, 0 }, + { "mmCM0_CM_CMOUT_RANDOM_SEEDS", REG_MMIO, 0x0d31, 2, &mmCM0_CM_CMOUT_RANDOM_SEEDS[0], sizeof(mmCM0_CM_CMOUT_RANDOM_SEEDS)/sizeof(mmCM0_CM_CMOUT_RANDOM_SEEDS[0]), 0, 0 }, + { "mmCM0_CM_MEM_PWR_CTRL", REG_MMIO, 0x0d32, 2, &mmCM0_CM_MEM_PWR_CTRL[0], sizeof(mmCM0_CM_MEM_PWR_CTRL)/sizeof(mmCM0_CM_MEM_PWR_CTRL[0]), 0, 0 }, + { "mmCM0_CM_MEM_PWR_STATUS", REG_MMIO, 0x0d33, 2, &mmCM0_CM_MEM_PWR_STATUS[0], sizeof(mmCM0_CM_MEM_PWR_STATUS)/sizeof(mmCM0_CM_MEM_PWR_STATUS[0]), 0, 0 }, + { "mmDC_PERFMON12_PERFCOUNTER_CNTL", REG_MMIO, 0x0d4c, 2, &mmDC_PERFMON12_PERFCOUNTER_CNTL[0], sizeof(mmDC_PERFMON12_PERFCOUNTER_CNTL)/sizeof(mmDC_PERFMON12_PERFCOUNTER_CNTL[0]), 0, 0 }, + { "mmDC_PERFMON12_PERFCOUNTER_CNTL2", REG_MMIO, 0x0d4d, 2, &mmDC_PERFMON12_PERFCOUNTER_CNTL2[0], sizeof(mmDC_PERFMON12_PERFCOUNTER_CNTL2)/sizeof(mmDC_PERFMON12_PERFCOUNTER_CNTL2[0]), 0, 0 }, + { "mmDC_PERFMON12_PERFCOUNTER_STATE", REG_MMIO, 0x0d4e, 2, &mmDC_PERFMON12_PERFCOUNTER_STATE[0], sizeof(mmDC_PERFMON12_PERFCOUNTER_STATE)/sizeof(mmDC_PERFMON12_PERFCOUNTER_STATE[0]), 0, 0 }, + { "mmDC_PERFMON12_PERFMON_CNTL", REG_MMIO, 0x0d4f, 2, &mmDC_PERFMON12_PERFMON_CNTL[0], sizeof(mmDC_PERFMON12_PERFMON_CNTL)/sizeof(mmDC_PERFMON12_PERFMON_CNTL[0]), 0, 0 }, + { "mmDC_PERFMON12_PERFMON_CNTL2", REG_MMIO, 0x0d50, 2, &mmDC_PERFMON12_PERFMON_CNTL2[0], sizeof(mmDC_PERFMON12_PERFMON_CNTL2)/sizeof(mmDC_PERFMON12_PERFMON_CNTL2[0]), 0, 0 }, + { "mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC", REG_MMIO, 0x0d51, 2, &mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC[0], sizeof(mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC)/sizeof(mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC[0]), 0, 0 }, + { "mmDC_PERFMON12_PERFMON_CVALUE_LOW", REG_MMIO, 0x0d52, 2, &mmDC_PERFMON12_PERFMON_CVALUE_LOW[0], sizeof(mmDC_PERFMON12_PERFMON_CVALUE_LOW)/sizeof(mmDC_PERFMON12_PERFMON_CVALUE_LOW[0]), 0, 0 }, + { "mmDC_PERFMON12_PERFMON_HI", REG_MMIO, 0x0d53, 2, &mmDC_PERFMON12_PERFMON_HI[0], sizeof(mmDC_PERFMON12_PERFMON_HI)/sizeof(mmDC_PERFMON12_PERFMON_HI[0]), 0, 0 }, + { "mmDC_PERFMON12_PERFMON_LOW", REG_MMIO, 0x0d54, 2, &mmDC_PERFMON12_PERFMON_LOW[0], sizeof(mmDC_PERFMON12_PERFMON_LOW)/sizeof(mmDC_PERFMON12_PERFMON_LOW[0]), 0, 0 }, + { "mmDPP_TOP1_DPP_CONTROL", REG_MMIO, 0x0d58, 2, &mmDPP_TOP1_DPP_CONTROL[0], sizeof(mmDPP_TOP1_DPP_CONTROL)/sizeof(mmDPP_TOP1_DPP_CONTROL[0]), 0, 0 }, + { "mmDPP_TOP1_DPP_SOFT_RESET", REG_MMIO, 0x0d59, 2, &mmDPP_TOP1_DPP_SOFT_RESET[0], sizeof(mmDPP_TOP1_DPP_SOFT_RESET)/sizeof(mmDPP_TOP1_DPP_SOFT_RESET[0]), 0, 0 }, + { "mmDPP_TOP1_DPP_CRC_VAL_R_G", REG_MMIO, 0x0d5a, 2, &mmDPP_TOP1_DPP_CRC_VAL_R_G[0], sizeof(mmDPP_TOP1_DPP_CRC_VAL_R_G)/sizeof(mmDPP_TOP1_DPP_CRC_VAL_R_G[0]), 0, 0 }, + { "mmDPP_TOP1_DPP_CRC_VAL_B_A", REG_MMIO, 0x0d5b, 2, &mmDPP_TOP1_DPP_CRC_VAL_B_A[0], sizeof(mmDPP_TOP1_DPP_CRC_VAL_B_A)/sizeof(mmDPP_TOP1_DPP_CRC_VAL_B_A[0]), 0, 0 }, + { "mmDPP_TOP1_DPP_CRC_CTRL", REG_MMIO, 0x0d5c, 2, &mmDPP_TOP1_DPP_CRC_CTRL[0], sizeof(mmDPP_TOP1_DPP_CRC_CTRL)/sizeof(mmDPP_TOP1_DPP_CRC_CTRL[0]), 0, 0 }, + { "mmDPP_TOP1_HOST_READ_CONTROL", REG_MMIO, 0x0d5d, 2, &mmDPP_TOP1_HOST_READ_CONTROL[0], sizeof(mmDPP_TOP1_HOST_READ_CONTROL)/sizeof(mmDPP_TOP1_HOST_READ_CONTROL[0]), 0, 0 }, + { "mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT", REG_MMIO, 0x0d62, 2, &mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT[0], sizeof(mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT)/sizeof(mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT[0]), 0, 0 }, + { "mmCNVC_CFG1_FORMAT_CONTROL", REG_MMIO, 0x0d63, 2, &mmCNVC_CFG1_FORMAT_CONTROL[0], sizeof(mmCNVC_CFG1_FORMAT_CONTROL)/sizeof(mmCNVC_CFG1_FORMAT_CONTROL[0]), 0, 0 }, + { "mmCNVC_CFG1_FCNV_FP_SCALE_BIAS", REG_MMIO, 0x0d64, 2, &mmCNVC_CFG1_FCNV_FP_SCALE_BIAS[0], sizeof(mmCNVC_CFG1_FCNV_FP_SCALE_BIAS)/sizeof(mmCNVC_CFG1_FCNV_FP_SCALE_BIAS[0]), 0, 0 }, + { "mmCNVC_CFG1_DENORM_CONTROL", REG_MMIO, 0x0d65, 2, &mmCNVC_CFG1_DENORM_CONTROL[0], sizeof(mmCNVC_CFG1_DENORM_CONTROL)/sizeof(mmCNVC_CFG1_DENORM_CONTROL[0]), 0, 0 }, + { "mmCNVC_CFG1_COLOR_KEYER_CONTROL", REG_MMIO, 0x0d67, 2, &mmCNVC_CFG1_COLOR_KEYER_CONTROL[0], sizeof(mmCNVC_CFG1_COLOR_KEYER_CONTROL)/sizeof(mmCNVC_CFG1_COLOR_KEYER_CONTROL[0]), 0, 0 }, + { "mmCNVC_CFG1_COLOR_KEYER_ALPHA", REG_MMIO, 0x0d68, 2, &mmCNVC_CFG1_COLOR_KEYER_ALPHA[0], sizeof(mmCNVC_CFG1_COLOR_KEYER_ALPHA)/sizeof(mmCNVC_CFG1_COLOR_KEYER_ALPHA[0]), 0, 0 }, + { "mmCNVC_CFG1_COLOR_KEYER_RED", REG_MMIO, 0x0d69, 2, &mmCNVC_CFG1_COLOR_KEYER_RED[0], sizeof(mmCNVC_CFG1_COLOR_KEYER_RED)/sizeof(mmCNVC_CFG1_COLOR_KEYER_RED[0]), 0, 0 }, + { "mmCNVC_CFG1_COLOR_KEYER_GREEN", REG_MMIO, 0x0d6a, 2, &mmCNVC_CFG1_COLOR_KEYER_GREEN[0], sizeof(mmCNVC_CFG1_COLOR_KEYER_GREEN)/sizeof(mmCNVC_CFG1_COLOR_KEYER_GREEN[0]), 0, 0 }, + { "mmCNVC_CFG1_COLOR_KEYER_BLUE", REG_MMIO, 0x0d6b, 2, &mmCNVC_CFG1_COLOR_KEYER_BLUE[0], sizeof(mmCNVC_CFG1_COLOR_KEYER_BLUE)/sizeof(mmCNVC_CFG1_COLOR_KEYER_BLUE[0]), 0, 0 }, + { "mmCNVC_CUR1_CURSOR0_CONTROL", REG_MMIO, 0x0d73, 2, &mmCNVC_CUR1_CURSOR0_CONTROL[0], sizeof(mmCNVC_CUR1_CURSOR0_CONTROL)/sizeof(mmCNVC_CUR1_CURSOR0_CONTROL[0]), 0, 0 }, + { "mmCNVC_CUR1_CURSOR0_COLOR0", REG_MMIO, 0x0d74, 2, &mmCNVC_CUR1_CURSOR0_COLOR0[0], sizeof(mmCNVC_CUR1_CURSOR0_COLOR0)/sizeof(mmCNVC_CUR1_CURSOR0_COLOR0[0]), 0, 0 }, + { "mmCNVC_CUR1_CURSOR0_COLOR1", REG_MMIO, 0x0d75, 2, &mmCNVC_CUR1_CURSOR0_COLOR1[0], sizeof(mmCNVC_CUR1_CURSOR0_COLOR1)/sizeof(mmCNVC_CUR1_CURSOR0_COLOR1[0]), 0, 0 }, + { "mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS", REG_MMIO, 0x0d76, 2, &mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS[0], sizeof(mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS)/sizeof(mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS[0]), 0, 0 }, + { "mmDSCL1_SCL_COEF_RAM_TAP_SELECT", REG_MMIO, 0x0d7d, 2, &mmDSCL1_SCL_COEF_RAM_TAP_SELECT[0], sizeof(mmDSCL1_SCL_COEF_RAM_TAP_SELECT)/sizeof(mmDSCL1_SCL_COEF_RAM_TAP_SELECT[0]), 0, 0 }, + { "mmDSCL1_SCL_COEF_RAM_TAP_DATA", REG_MMIO, 0x0d7e, 2, &mmDSCL1_SCL_COEF_RAM_TAP_DATA[0], sizeof(mmDSCL1_SCL_COEF_RAM_TAP_DATA)/sizeof(mmDSCL1_SCL_COEF_RAM_TAP_DATA[0]), 0, 0 }, + { "mmDSCL1_SCL_MODE", REG_MMIO, 0x0d7f, 2, &mmDSCL1_SCL_MODE[0], sizeof(mmDSCL1_SCL_MODE)/sizeof(mmDSCL1_SCL_MODE[0]), 0, 0 }, + { "mmDSCL1_SCL_TAP_CONTROL", REG_MMIO, 0x0d80, 2, &mmDSCL1_SCL_TAP_CONTROL[0], sizeof(mmDSCL1_SCL_TAP_CONTROL)/sizeof(mmDSCL1_SCL_TAP_CONTROL[0]), 0, 0 }, + { "mmDSCL1_DSCL_CONTROL", REG_MMIO, 0x0d81, 2, &mmDSCL1_DSCL_CONTROL[0], sizeof(mmDSCL1_DSCL_CONTROL)/sizeof(mmDSCL1_DSCL_CONTROL[0]), 0, 0 }, + { "mmDSCL1_DSCL_2TAP_CONTROL", REG_MMIO, 0x0d82, 2, &mmDSCL1_DSCL_2TAP_CONTROL[0], sizeof(mmDSCL1_DSCL_2TAP_CONTROL)/sizeof(mmDSCL1_DSCL_2TAP_CONTROL[0]), 0, 0 }, + { "mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL", REG_MMIO, 0x0d83, 2, &mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL[0], sizeof(mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL)/sizeof(mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL[0]), 0, 0 }, + { "mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO", REG_MMIO, 0x0d84, 2, &mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO[0], sizeof(mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO)/sizeof(mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO[0]), 0, 0 }, + { "mmDSCL1_SCL_HORZ_FILTER_INIT", REG_MMIO, 0x0d85, 2, &mmDSCL1_SCL_HORZ_FILTER_INIT[0], sizeof(mmDSCL1_SCL_HORZ_FILTER_INIT)/sizeof(mmDSCL1_SCL_HORZ_FILTER_INIT[0]), 0, 0 }, + { "mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C", REG_MMIO, 0x0d86, 2, &mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C[0], sizeof(mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C)/sizeof(mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C[0]), 0, 0 }, + { "mmDSCL1_SCL_HORZ_FILTER_INIT_C", REG_MMIO, 0x0d87, 2, &mmDSCL1_SCL_HORZ_FILTER_INIT_C[0], sizeof(mmDSCL1_SCL_HORZ_FILTER_INIT_C)/sizeof(mmDSCL1_SCL_HORZ_FILTER_INIT_C[0]), 0, 0 }, + { "mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO", REG_MMIO, 0x0d88, 2, &mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO[0], sizeof(mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO)/sizeof(mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO[0]), 0, 0 }, + { "mmDSCL1_SCL_VERT_FILTER_INIT", REG_MMIO, 0x0d89, 2, &mmDSCL1_SCL_VERT_FILTER_INIT[0], sizeof(mmDSCL1_SCL_VERT_FILTER_INIT)/sizeof(mmDSCL1_SCL_VERT_FILTER_INIT[0]), 0, 0 }, + { "mmDSCL1_SCL_VERT_FILTER_INIT_BOT", REG_MMIO, 0x0d8a, 2, &mmDSCL1_SCL_VERT_FILTER_INIT_BOT[0], sizeof(mmDSCL1_SCL_VERT_FILTER_INIT_BOT)/sizeof(mmDSCL1_SCL_VERT_FILTER_INIT_BOT[0]), 0, 0 }, + { "mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C", REG_MMIO, 0x0d8b, 2, &mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C[0], sizeof(mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C)/sizeof(mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C[0]), 0, 0 }, + { "mmDSCL1_SCL_VERT_FILTER_INIT_C", REG_MMIO, 0x0d8c, 2, &mmDSCL1_SCL_VERT_FILTER_INIT_C[0], sizeof(mmDSCL1_SCL_VERT_FILTER_INIT_C)/sizeof(mmDSCL1_SCL_VERT_FILTER_INIT_C[0]), 0, 0 }, + { "mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C", REG_MMIO, 0x0d8d, 2, &mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C[0], sizeof(mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C)/sizeof(mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C[0]), 0, 0 }, + { "mmDSCL1_SCL_BLACK_OFFSET", REG_MMIO, 0x0d8e, 2, &mmDSCL1_SCL_BLACK_OFFSET[0], sizeof(mmDSCL1_SCL_BLACK_OFFSET)/sizeof(mmDSCL1_SCL_BLACK_OFFSET[0]), 0, 0 }, + { "mmDSCL1_DSCL_UPDATE", REG_MMIO, 0x0d8f, 2, &mmDSCL1_DSCL_UPDATE[0], sizeof(mmDSCL1_DSCL_UPDATE)/sizeof(mmDSCL1_DSCL_UPDATE[0]), 0, 0 }, + { "mmDSCL1_DSCL_AUTOCAL", REG_MMIO, 0x0d90, 2, &mmDSCL1_DSCL_AUTOCAL[0], sizeof(mmDSCL1_DSCL_AUTOCAL)/sizeof(mmDSCL1_DSCL_AUTOCAL[0]), 0, 0 }, + { "mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT", REG_MMIO, 0x0d91, 2, &mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT[0], sizeof(mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT)/sizeof(mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT[0]), 0, 0 }, + { "mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM", REG_MMIO, 0x0d92, 2, &mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM[0], sizeof(mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM)/sizeof(mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM[0]), 0, 0 }, + { "mmDSCL1_OTG_H_BLANK", REG_MMIO, 0x0d93, 2, &mmDSCL1_OTG_H_BLANK[0], sizeof(mmDSCL1_OTG_H_BLANK)/sizeof(mmDSCL1_OTG_H_BLANK[0]), 0, 0 }, + { "mmDSCL1_OTG_V_BLANK", REG_MMIO, 0x0d94, 2, &mmDSCL1_OTG_V_BLANK[0], sizeof(mmDSCL1_OTG_V_BLANK)/sizeof(mmDSCL1_OTG_V_BLANK[0]), 0, 0 }, + { "mmDSCL1_RECOUT_START", REG_MMIO, 0x0d95, 2, &mmDSCL1_RECOUT_START[0], sizeof(mmDSCL1_RECOUT_START)/sizeof(mmDSCL1_RECOUT_START[0]), 0, 0 }, + { "mmDSCL1_RECOUT_SIZE", REG_MMIO, 0x0d96, 2, &mmDSCL1_RECOUT_SIZE[0], sizeof(mmDSCL1_RECOUT_SIZE)/sizeof(mmDSCL1_RECOUT_SIZE[0]), 0, 0 }, + { "mmDSCL1_MPC_SIZE", REG_MMIO, 0x0d97, 2, &mmDSCL1_MPC_SIZE[0], sizeof(mmDSCL1_MPC_SIZE)/sizeof(mmDSCL1_MPC_SIZE[0]), 0, 0 }, + { "mmDSCL1_LB_DATA_FORMAT", REG_MMIO, 0x0d98, 2, &mmDSCL1_LB_DATA_FORMAT[0], sizeof(mmDSCL1_LB_DATA_FORMAT)/sizeof(mmDSCL1_LB_DATA_FORMAT[0]), 0, 0 }, + { "mmDSCL1_LB_MEMORY_CTRL", REG_MMIO, 0x0d99, 2, &mmDSCL1_LB_MEMORY_CTRL[0], sizeof(mmDSCL1_LB_MEMORY_CTRL)/sizeof(mmDSCL1_LB_MEMORY_CTRL[0]), 0, 0 }, + { "mmDSCL1_LB_V_COUNTER", REG_MMIO, 0x0d9a, 2, &mmDSCL1_LB_V_COUNTER[0], sizeof(mmDSCL1_LB_V_COUNTER)/sizeof(mmDSCL1_LB_V_COUNTER[0]), 0, 0 }, + { "mmDSCL1_DSCL_MEM_PWR_CTRL", REG_MMIO, 0x0d9b, 2, &mmDSCL1_DSCL_MEM_PWR_CTRL[0], sizeof(mmDSCL1_DSCL_MEM_PWR_CTRL)/sizeof(mmDSCL1_DSCL_MEM_PWR_CTRL[0]), 0, 0 }, + { "mmDSCL1_DSCL_MEM_PWR_STATUS", REG_MMIO, 0x0d9c, 2, &mmDSCL1_DSCL_MEM_PWR_STATUS[0], sizeof(mmDSCL1_DSCL_MEM_PWR_STATUS)/sizeof(mmDSCL1_DSCL_MEM_PWR_STATUS[0]), 0, 0 }, + { "mmDSCL1_OBUF_CONTROL", REG_MMIO, 0x0d9d, 2, &mmDSCL1_OBUF_CONTROL[0], sizeof(mmDSCL1_OBUF_CONTROL)/sizeof(mmDSCL1_OBUF_CONTROL[0]), 0, 0 }, + { "mmDSCL1_OBUF_MEM_PWR_CTRL", REG_MMIO, 0x0d9e, 2, &mmDSCL1_OBUF_MEM_PWR_CTRL[0], sizeof(mmDSCL1_OBUF_MEM_PWR_CTRL)/sizeof(mmDSCL1_OBUF_MEM_PWR_CTRL[0]), 0, 0 }, + { "mmCM1_CM_CONTROL", REG_MMIO, 0x0dad, 2, &mmCM1_CM_CONTROL[0], sizeof(mmCM1_CM_CONTROL)/sizeof(mmCM1_CM_CONTROL[0]), 0, 0 }, + { "mmCM1_CM_COMA_C11_C12", REG_MMIO, 0x0dae, 2, &mmCM1_CM_COMA_C11_C12[0], sizeof(mmCM1_CM_COMA_C11_C12)/sizeof(mmCM1_CM_COMA_C11_C12[0]), 0, 0 }, + { "mmCM1_CM_COMA_C13_C14", REG_MMIO, 0x0daf, 2, &mmCM1_CM_COMA_C13_C14[0], sizeof(mmCM1_CM_COMA_C13_C14)/sizeof(mmCM1_CM_COMA_C13_C14[0]), 0, 0 }, + { "mmCM1_CM_COMA_C21_C22", REG_MMIO, 0x0db0, 2, &mmCM1_CM_COMA_C21_C22[0], sizeof(mmCM1_CM_COMA_C21_C22)/sizeof(mmCM1_CM_COMA_C21_C22[0]), 0, 0 }, + { "mmCM1_CM_COMA_C23_C24", REG_MMIO, 0x0db1, 2, &mmCM1_CM_COMA_C23_C24[0], sizeof(mmCM1_CM_COMA_C23_C24)/sizeof(mmCM1_CM_COMA_C23_C24[0]), 0, 0 }, + { "mmCM1_CM_COMA_C31_C32", REG_MMIO, 0x0db2, 2, &mmCM1_CM_COMA_C31_C32[0], sizeof(mmCM1_CM_COMA_C31_C32)/sizeof(mmCM1_CM_COMA_C31_C32[0]), 0, 0 }, + { "mmCM1_CM_COMA_C33_C34", REG_MMIO, 0x0db3, 2, &mmCM1_CM_COMA_C33_C34[0], sizeof(mmCM1_CM_COMA_C33_C34)/sizeof(mmCM1_CM_COMA_C33_C34[0]), 0, 0 }, + { "mmCM1_CM_COMB_C11_C12", REG_MMIO, 0x0db4, 2, &mmCM1_CM_COMB_C11_C12[0], sizeof(mmCM1_CM_COMB_C11_C12)/sizeof(mmCM1_CM_COMB_C11_C12[0]), 0, 0 }, + { "mmCM1_CM_COMB_C13_C14", REG_MMIO, 0x0db5, 2, &mmCM1_CM_COMB_C13_C14[0], sizeof(mmCM1_CM_COMB_C13_C14)/sizeof(mmCM1_CM_COMB_C13_C14[0]), 0, 0 }, + { "mmCM1_CM_COMB_C21_C22", REG_MMIO, 0x0db6, 2, &mmCM1_CM_COMB_C21_C22[0], sizeof(mmCM1_CM_COMB_C21_C22)/sizeof(mmCM1_CM_COMB_C21_C22[0]), 0, 0 }, + { "mmCM1_CM_COMB_C23_C24", REG_MMIO, 0x0db7, 2, &mmCM1_CM_COMB_C23_C24[0], sizeof(mmCM1_CM_COMB_C23_C24)/sizeof(mmCM1_CM_COMB_C23_C24[0]), 0, 0 }, + { "mmCM1_CM_COMB_C31_C32", REG_MMIO, 0x0db8, 2, &mmCM1_CM_COMB_C31_C32[0], sizeof(mmCM1_CM_COMB_C31_C32)/sizeof(mmCM1_CM_COMB_C31_C32[0]), 0, 0 }, + { "mmCM1_CM_COMB_C33_C34", REG_MMIO, 0x0db9, 2, &mmCM1_CM_COMB_C33_C34[0], sizeof(mmCM1_CM_COMB_C33_C34)/sizeof(mmCM1_CM_COMB_C33_C34[0]), 0, 0 }, + { "mmCM1_CM_IGAM_CONTROL", REG_MMIO, 0x0dba, 2, &mmCM1_CM_IGAM_CONTROL[0], sizeof(mmCM1_CM_IGAM_CONTROL)/sizeof(mmCM1_CM_IGAM_CONTROL[0]), 0, 0 }, + { "mmCM1_CM_IGAM_LUT_RW_CONTROL", REG_MMIO, 0x0dbb, 2, &mmCM1_CM_IGAM_LUT_RW_CONTROL[0], sizeof(mmCM1_CM_IGAM_LUT_RW_CONTROL)/sizeof(mmCM1_CM_IGAM_LUT_RW_CONTROL[0]), 0, 0 }, + { "mmCM1_CM_IGAM_LUT_RW_INDEX", REG_MMIO, 0x0dbc, 2, &mmCM1_CM_IGAM_LUT_RW_INDEX[0], sizeof(mmCM1_CM_IGAM_LUT_RW_INDEX)/sizeof(mmCM1_CM_IGAM_LUT_RW_INDEX[0]), 0, 0 }, + { "mmCM1_CM_IGAM_LUT_SEQ_COLOR", REG_MMIO, 0x0dbd, 2, &mmCM1_CM_IGAM_LUT_SEQ_COLOR[0], sizeof(mmCM1_CM_IGAM_LUT_SEQ_COLOR)/sizeof(mmCM1_CM_IGAM_LUT_SEQ_COLOR[0]), 0, 0 }, + { "mmCM1_CM_IGAM_LUT_30_COLOR", REG_MMIO, 0x0dbe, 2, &mmCM1_CM_IGAM_LUT_30_COLOR[0], sizeof(mmCM1_CM_IGAM_LUT_30_COLOR)/sizeof(mmCM1_CM_IGAM_LUT_30_COLOR[0]), 0, 0 }, + { "mmCM1_CM_IGAM_LUT_PWL_DATA", REG_MMIO, 0x0dbf, 2, &mmCM1_CM_IGAM_LUT_PWL_DATA[0], sizeof(mmCM1_CM_IGAM_LUT_PWL_DATA)/sizeof(mmCM1_CM_IGAM_LUT_PWL_DATA[0]), 0, 0 }, + { "mmCM1_CM_IGAM_LUT_AUTOFILL", REG_MMIO, 0x0dc0, 2, &mmCM1_CM_IGAM_LUT_AUTOFILL[0], sizeof(mmCM1_CM_IGAM_LUT_AUTOFILL)/sizeof(mmCM1_CM_IGAM_LUT_AUTOFILL[0]), 0, 0 }, + { "mmCM1_CM_IGAM_LUT_BW_OFFSET_BLUE", REG_MMIO, 0x0dc1, 2, &mmCM1_CM_IGAM_LUT_BW_OFFSET_BLUE[0], sizeof(mmCM1_CM_IGAM_LUT_BW_OFFSET_BLUE)/sizeof(mmCM1_CM_IGAM_LUT_BW_OFFSET_BLUE[0]), 0, 0 }, + { "mmCM1_CM_IGAM_LUT_BW_OFFSET_GREEN", REG_MMIO, 0x0dc2, 2, &mmCM1_CM_IGAM_LUT_BW_OFFSET_GREEN[0], sizeof(mmCM1_CM_IGAM_LUT_BW_OFFSET_GREEN)/sizeof(mmCM1_CM_IGAM_LUT_BW_OFFSET_GREEN[0]), 0, 0 }, + { "mmCM1_CM_IGAM_LUT_BW_OFFSET_RED", REG_MMIO, 0x0dc3, 2, &mmCM1_CM_IGAM_LUT_BW_OFFSET_RED[0], sizeof(mmCM1_CM_IGAM_LUT_BW_OFFSET_RED)/sizeof(mmCM1_CM_IGAM_LUT_BW_OFFSET_RED[0]), 0, 0 }, + { "mmCM1_CM_ICSC_CONTROL", REG_MMIO, 0x0dc4, 2, &mmCM1_CM_ICSC_CONTROL[0], sizeof(mmCM1_CM_ICSC_CONTROL)/sizeof(mmCM1_CM_ICSC_CONTROL[0]), 0, 0 }, + { "mmCM1_CM_ICSC_C11_C12", REG_MMIO, 0x0dc5, 2, &mmCM1_CM_ICSC_C11_C12[0], sizeof(mmCM1_CM_ICSC_C11_C12)/sizeof(mmCM1_CM_ICSC_C11_C12[0]), 0, 0 }, + { "mmCM1_CM_ICSC_C13_C14", REG_MMIO, 0x0dc6, 2, &mmCM1_CM_ICSC_C13_C14[0], sizeof(mmCM1_CM_ICSC_C13_C14)/sizeof(mmCM1_CM_ICSC_C13_C14[0]), 0, 0 }, + { "mmCM1_CM_ICSC_C21_C22", REG_MMIO, 0x0dc7, 2, &mmCM1_CM_ICSC_C21_C22[0], sizeof(mmCM1_CM_ICSC_C21_C22)/sizeof(mmCM1_CM_ICSC_C21_C22[0]), 0, 0 }, + { "mmCM1_CM_ICSC_C23_C24", REG_MMIO, 0x0dc8, 2, &mmCM1_CM_ICSC_C23_C24[0], sizeof(mmCM1_CM_ICSC_C23_C24)/sizeof(mmCM1_CM_ICSC_C23_C24[0]), 0, 0 }, + { "mmCM1_CM_ICSC_C31_C32", REG_MMIO, 0x0dc9, 2, &mmCM1_CM_ICSC_C31_C32[0], sizeof(mmCM1_CM_ICSC_C31_C32)/sizeof(mmCM1_CM_ICSC_C31_C32[0]), 0, 0 }, + { "mmCM1_CM_ICSC_C33_C34", REG_MMIO, 0x0dca, 2, &mmCM1_CM_ICSC_C33_C34[0], sizeof(mmCM1_CM_ICSC_C33_C34)/sizeof(mmCM1_CM_ICSC_C33_C34[0]), 0, 0 }, + { "mmCM1_CM_GAMUT_REMAP_CONTROL", REG_MMIO, 0x0dcb, 2, &mmCM1_CM_GAMUT_REMAP_CONTROL[0], sizeof(mmCM1_CM_GAMUT_REMAP_CONTROL)/sizeof(mmCM1_CM_GAMUT_REMAP_CONTROL[0]), 0, 0 }, + { "mmCM1_CM_GAMUT_REMAP_C11_C12", REG_MMIO, 0x0dcc, 2, &mmCM1_CM_GAMUT_REMAP_C11_C12[0], sizeof(mmCM1_CM_GAMUT_REMAP_C11_C12)/sizeof(mmCM1_CM_GAMUT_REMAP_C11_C12[0]), 0, 0 }, + { "mmCM1_CM_GAMUT_REMAP_C13_C14", REG_MMIO, 0x0dcd, 2, &mmCM1_CM_GAMUT_REMAP_C13_C14[0], sizeof(mmCM1_CM_GAMUT_REMAP_C13_C14)/sizeof(mmCM1_CM_GAMUT_REMAP_C13_C14[0]), 0, 0 }, + { "mmCM1_CM_GAMUT_REMAP_C21_C22", REG_MMIO, 0x0dce, 2, &mmCM1_CM_GAMUT_REMAP_C21_C22[0], sizeof(mmCM1_CM_GAMUT_REMAP_C21_C22)/sizeof(mmCM1_CM_GAMUT_REMAP_C21_C22[0]), 0, 0 }, + { "mmCM1_CM_GAMUT_REMAP_C23_C24", REG_MMIO, 0x0dcf, 2, &mmCM1_CM_GAMUT_REMAP_C23_C24[0], sizeof(mmCM1_CM_GAMUT_REMAP_C23_C24)/sizeof(mmCM1_CM_GAMUT_REMAP_C23_C24[0]), 0, 0 }, + { "mmCM1_CM_GAMUT_REMAP_C31_C32", REG_MMIO, 0x0dd0, 2, &mmCM1_CM_GAMUT_REMAP_C31_C32[0], sizeof(mmCM1_CM_GAMUT_REMAP_C31_C32)/sizeof(mmCM1_CM_GAMUT_REMAP_C31_C32[0]), 0, 0 }, + { "mmCM1_CM_GAMUT_REMAP_C33_C34", REG_MMIO, 0x0dd1, 2, &mmCM1_CM_GAMUT_REMAP_C33_C34[0], sizeof(mmCM1_CM_GAMUT_REMAP_C33_C34)/sizeof(mmCM1_CM_GAMUT_REMAP_C33_C34[0]), 0, 0 }, + { "mmCM1_CM_OCSC_CONTROL", REG_MMIO, 0x0dd2, 2, &mmCM1_CM_OCSC_CONTROL[0], sizeof(mmCM1_CM_OCSC_CONTROL)/sizeof(mmCM1_CM_OCSC_CONTROL[0]), 0, 0 }, + { "mmCM1_CM_OCSC_C11_C12", REG_MMIO, 0x0dd3, 2, &mmCM1_CM_OCSC_C11_C12[0], sizeof(mmCM1_CM_OCSC_C11_C12)/sizeof(mmCM1_CM_OCSC_C11_C12[0]), 0, 0 }, + { "mmCM1_CM_OCSC_C13_C14", REG_MMIO, 0x0dd4, 2, &mmCM1_CM_OCSC_C13_C14[0], sizeof(mmCM1_CM_OCSC_C13_C14)/sizeof(mmCM1_CM_OCSC_C13_C14[0]), 0, 0 }, + { "mmCM1_CM_OCSC_C21_C22", REG_MMIO, 0x0dd5, 2, &mmCM1_CM_OCSC_C21_C22[0], sizeof(mmCM1_CM_OCSC_C21_C22)/sizeof(mmCM1_CM_OCSC_C21_C22[0]), 0, 0 }, + { "mmCM1_CM_OCSC_C23_C24", REG_MMIO, 0x0dd6, 2, &mmCM1_CM_OCSC_C23_C24[0], sizeof(mmCM1_CM_OCSC_C23_C24)/sizeof(mmCM1_CM_OCSC_C23_C24[0]), 0, 0 }, + { "mmCM1_CM_OCSC_C31_C32", REG_MMIO, 0x0dd7, 2, &mmCM1_CM_OCSC_C31_C32[0], sizeof(mmCM1_CM_OCSC_C31_C32)/sizeof(mmCM1_CM_OCSC_C31_C32[0]), 0, 0 }, + { "mmCM1_CM_OCSC_C33_C34", REG_MMIO, 0x0dd8, 2, &mmCM1_CM_OCSC_C33_C34[0], sizeof(mmCM1_CM_OCSC_C33_C34)/sizeof(mmCM1_CM_OCSC_C33_C34[0]), 0, 0 }, + { "mmCM1_CM_BNS_VALUES_R", REG_MMIO, 0x0dd9, 2, &mmCM1_CM_BNS_VALUES_R[0], sizeof(mmCM1_CM_BNS_VALUES_R)/sizeof(mmCM1_CM_BNS_VALUES_R[0]), 0, 0 }, + { "mmCM1_CM_BNS_VALUES_G", REG_MMIO, 0x0dda, 2, &mmCM1_CM_BNS_VALUES_G[0], sizeof(mmCM1_CM_BNS_VALUES_G)/sizeof(mmCM1_CM_BNS_VALUES_G[0]), 0, 0 }, + { "mmCM1_CM_BNS_VALUES_B", REG_MMIO, 0x0ddb, 2, &mmCM1_CM_BNS_VALUES_B[0], sizeof(mmCM1_CM_BNS_VALUES_B)/sizeof(mmCM1_CM_BNS_VALUES_B[0]), 0, 0 }, + { "mmCM1_CM_DGAM_CONTROL", REG_MMIO, 0x0ddc, 2, &mmCM1_CM_DGAM_CONTROL[0], sizeof(mmCM1_CM_DGAM_CONTROL)/sizeof(mmCM1_CM_DGAM_CONTROL[0]), 0, 0 }, + { "mmCM1_CM_DGAM_LUT_INDEX", REG_MMIO, 0x0ddd, 2, &mmCM1_CM_DGAM_LUT_INDEX[0], sizeof(mmCM1_CM_DGAM_LUT_INDEX)/sizeof(mmCM1_CM_DGAM_LUT_INDEX[0]), 0, 0 }, + { "mmCM1_CM_DGAM_LUT_DATA", REG_MMIO, 0x0dde, 2, &mmCM1_CM_DGAM_LUT_DATA[0], sizeof(mmCM1_CM_DGAM_LUT_DATA)/sizeof(mmCM1_CM_DGAM_LUT_DATA[0]), 0, 0 }, + { "mmCM1_CM_DGAM_LUT_WRITE_EN_MASK", REG_MMIO, 0x0ddf, 2, &mmCM1_CM_DGAM_LUT_WRITE_EN_MASK[0], sizeof(mmCM1_CM_DGAM_LUT_WRITE_EN_MASK)/sizeof(mmCM1_CM_DGAM_LUT_WRITE_EN_MASK[0]), 0, 0 }, + { "mmCM1_CM_DGAM_RAMA_START_CNTL_B", REG_MMIO, 0x0de0, 2, &mmCM1_CM_DGAM_RAMA_START_CNTL_B[0], sizeof(mmCM1_CM_DGAM_RAMA_START_CNTL_B)/sizeof(mmCM1_CM_DGAM_RAMA_START_CNTL_B[0]), 0, 0 }, + { "mmCM1_CM_DGAM_RAMA_START_CNTL_G", REG_MMIO, 0x0de1, 2, &mmCM1_CM_DGAM_RAMA_START_CNTL_G[0], sizeof(mmCM1_CM_DGAM_RAMA_START_CNTL_G)/sizeof(mmCM1_CM_DGAM_RAMA_START_CNTL_G[0]), 0, 0 }, + { "mmCM1_CM_DGAM_RAMA_START_CNTL_R", REG_MMIO, 0x0de2, 2, &mmCM1_CM_DGAM_RAMA_START_CNTL_R[0], sizeof(mmCM1_CM_DGAM_RAMA_START_CNTL_R)/sizeof(mmCM1_CM_DGAM_RAMA_START_CNTL_R[0]), 0, 0 }, + { "mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_B", REG_MMIO, 0x0de3, 2, &mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_B[0], sizeof(mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_B)/sizeof(mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_B[0]), 0, 0 }, + { "mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_G", REG_MMIO, 0x0de4, 2, &mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_G[0], sizeof(mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_G)/sizeof(mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_G[0]), 0, 0 }, + { "mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_R", REG_MMIO, 0x0de5, 2, &mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_R[0], sizeof(mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_R)/sizeof(mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_R[0]), 0, 0 }, + { "mmCM1_CM_DGAM_RAMA_END_CNTL1_B", REG_MMIO, 0x0de6, 2, &mmCM1_CM_DGAM_RAMA_END_CNTL1_B[0], sizeof(mmCM1_CM_DGAM_RAMA_END_CNTL1_B)/sizeof(mmCM1_CM_DGAM_RAMA_END_CNTL1_B[0]), 0, 0 }, + { "mmCM1_CM_DGAM_RAMA_END_CNTL2_B", REG_MMIO, 0x0de7, 2, &mmCM1_CM_DGAM_RAMA_END_CNTL2_B[0], sizeof(mmCM1_CM_DGAM_RAMA_END_CNTL2_B)/sizeof(mmCM1_CM_DGAM_RAMA_END_CNTL2_B[0]), 0, 0 }, + { "mmCM1_CM_DGAM_RAMA_END_CNTL1_G", REG_MMIO, 0x0de8, 2, &mmCM1_CM_DGAM_RAMA_END_CNTL1_G[0], sizeof(mmCM1_CM_DGAM_RAMA_END_CNTL1_G)/sizeof(mmCM1_CM_DGAM_RAMA_END_CNTL1_G[0]), 0, 0 }, + { "mmCM1_CM_DGAM_RAMA_END_CNTL2_G", REG_MMIO, 0x0de9, 2, &mmCM1_CM_DGAM_RAMA_END_CNTL2_G[0], sizeof(mmCM1_CM_DGAM_RAMA_END_CNTL2_G)/sizeof(mmCM1_CM_DGAM_RAMA_END_CNTL2_G[0]), 0, 0 }, + { "mmCM1_CM_DGAM_RAMA_END_CNTL1_R", REG_MMIO, 0x0dea, 2, &mmCM1_CM_DGAM_RAMA_END_CNTL1_R[0], sizeof(mmCM1_CM_DGAM_RAMA_END_CNTL1_R)/sizeof(mmCM1_CM_DGAM_RAMA_END_CNTL1_R[0]), 0, 0 }, + { "mmCM1_CM_DGAM_RAMA_END_CNTL2_R", REG_MMIO, 0x0deb, 2, &mmCM1_CM_DGAM_RAMA_END_CNTL2_R[0], sizeof(mmCM1_CM_DGAM_RAMA_END_CNTL2_R)/sizeof(mmCM1_CM_DGAM_RAMA_END_CNTL2_R[0]), 0, 0 }, + { "mmCM1_CM_DGAM_RAMA_REGION_0_1", REG_MMIO, 0x0dec, 2, &mmCM1_CM_DGAM_RAMA_REGION_0_1[0], sizeof(mmCM1_CM_DGAM_RAMA_REGION_0_1)/sizeof(mmCM1_CM_DGAM_RAMA_REGION_0_1[0]), 0, 0 }, + { "mmCM1_CM_DGAM_RAMA_REGION_2_3", REG_MMIO, 0x0ded, 2, &mmCM1_CM_DGAM_RAMA_REGION_2_3[0], sizeof(mmCM1_CM_DGAM_RAMA_REGION_2_3)/sizeof(mmCM1_CM_DGAM_RAMA_REGION_2_3[0]), 0, 0 }, + { "mmCM1_CM_DGAM_RAMA_REGION_4_5", REG_MMIO, 0x0dee, 2, &mmCM1_CM_DGAM_RAMA_REGION_4_5[0], sizeof(mmCM1_CM_DGAM_RAMA_REGION_4_5)/sizeof(mmCM1_CM_DGAM_RAMA_REGION_4_5[0]), 0, 0 }, + { "mmCM1_CM_DGAM_RAMA_REGION_6_7", REG_MMIO, 0x0def, 2, &mmCM1_CM_DGAM_RAMA_REGION_6_7[0], sizeof(mmCM1_CM_DGAM_RAMA_REGION_6_7)/sizeof(mmCM1_CM_DGAM_RAMA_REGION_6_7[0]), 0, 0 }, + { "mmCM1_CM_DGAM_RAMA_REGION_8_9", REG_MMIO, 0x0df0, 2, &mmCM1_CM_DGAM_RAMA_REGION_8_9[0], sizeof(mmCM1_CM_DGAM_RAMA_REGION_8_9)/sizeof(mmCM1_CM_DGAM_RAMA_REGION_8_9[0]), 0, 0 }, + { "mmCM1_CM_DGAM_RAMA_REGION_10_11", REG_MMIO, 0x0df1, 2, &mmCM1_CM_DGAM_RAMA_REGION_10_11[0], sizeof(mmCM1_CM_DGAM_RAMA_REGION_10_11)/sizeof(mmCM1_CM_DGAM_RAMA_REGION_10_11[0]), 0, 0 }, + { "mmCM1_CM_DGAM_RAMA_REGION_12_13", REG_MMIO, 0x0df2, 2, &mmCM1_CM_DGAM_RAMA_REGION_12_13[0], sizeof(mmCM1_CM_DGAM_RAMA_REGION_12_13)/sizeof(mmCM1_CM_DGAM_RAMA_REGION_12_13[0]), 0, 0 }, + { "mmCM1_CM_DGAM_RAMA_REGION_14_15", REG_MMIO, 0x0df3, 2, &mmCM1_CM_DGAM_RAMA_REGION_14_15[0], sizeof(mmCM1_CM_DGAM_RAMA_REGION_14_15)/sizeof(mmCM1_CM_DGAM_RAMA_REGION_14_15[0]), 0, 0 }, + { "mmCM1_CM_DGAM_RAMB_START_CNTL_B", REG_MMIO, 0x0df4, 2, &mmCM1_CM_DGAM_RAMB_START_CNTL_B[0], sizeof(mmCM1_CM_DGAM_RAMB_START_CNTL_B)/sizeof(mmCM1_CM_DGAM_RAMB_START_CNTL_B[0]), 0, 0 }, + { "mmCM1_CM_DGAM_RAMB_START_CNTL_G", REG_MMIO, 0x0df5, 2, &mmCM1_CM_DGAM_RAMB_START_CNTL_G[0], sizeof(mmCM1_CM_DGAM_RAMB_START_CNTL_G)/sizeof(mmCM1_CM_DGAM_RAMB_START_CNTL_G[0]), 0, 0 }, + { "mmCM1_CM_DGAM_RAMB_START_CNTL_R", REG_MMIO, 0x0df6, 2, &mmCM1_CM_DGAM_RAMB_START_CNTL_R[0], sizeof(mmCM1_CM_DGAM_RAMB_START_CNTL_R)/sizeof(mmCM1_CM_DGAM_RAMB_START_CNTL_R[0]), 0, 0 }, + { "mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_B", REG_MMIO, 0x0df7, 2, &mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_B[0], sizeof(mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_B)/sizeof(mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_B[0]), 0, 0 }, + { "mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_G", REG_MMIO, 0x0df8, 2, &mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_G[0], sizeof(mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_G)/sizeof(mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_G[0]), 0, 0 }, + { "mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_R", REG_MMIO, 0x0df9, 2, &mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_R[0], sizeof(mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_R)/sizeof(mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_R[0]), 0, 0 }, + { "mmCM1_CM_DGAM_RAMB_END_CNTL1_B", REG_MMIO, 0x0dfa, 2, &mmCM1_CM_DGAM_RAMB_END_CNTL1_B[0], sizeof(mmCM1_CM_DGAM_RAMB_END_CNTL1_B)/sizeof(mmCM1_CM_DGAM_RAMB_END_CNTL1_B[0]), 0, 0 }, + { "mmCM1_CM_DGAM_RAMB_END_CNTL2_B", REG_MMIO, 0x0dfb, 2, &mmCM1_CM_DGAM_RAMB_END_CNTL2_B[0], sizeof(mmCM1_CM_DGAM_RAMB_END_CNTL2_B)/sizeof(mmCM1_CM_DGAM_RAMB_END_CNTL2_B[0]), 0, 0 }, + { "mmCM1_CM_DGAM_RAMB_END_CNTL1_G", REG_MMIO, 0x0dfc, 2, &mmCM1_CM_DGAM_RAMB_END_CNTL1_G[0], sizeof(mmCM1_CM_DGAM_RAMB_END_CNTL1_G)/sizeof(mmCM1_CM_DGAM_RAMB_END_CNTL1_G[0]), 0, 0 }, + { "mmCM1_CM_DGAM_RAMB_END_CNTL2_G", REG_MMIO, 0x0dfd, 2, &mmCM1_CM_DGAM_RAMB_END_CNTL2_G[0], sizeof(mmCM1_CM_DGAM_RAMB_END_CNTL2_G)/sizeof(mmCM1_CM_DGAM_RAMB_END_CNTL2_G[0]), 0, 0 }, + { "mmCM1_CM_DGAM_RAMB_END_CNTL1_R", REG_MMIO, 0x0dfe, 2, &mmCM1_CM_DGAM_RAMB_END_CNTL1_R[0], sizeof(mmCM1_CM_DGAM_RAMB_END_CNTL1_R)/sizeof(mmCM1_CM_DGAM_RAMB_END_CNTL1_R[0]), 0, 0 }, + { "mmCM1_CM_DGAM_RAMB_END_CNTL2_R", REG_MMIO, 0x0dff, 2, &mmCM1_CM_DGAM_RAMB_END_CNTL2_R[0], sizeof(mmCM1_CM_DGAM_RAMB_END_CNTL2_R)/sizeof(mmCM1_CM_DGAM_RAMB_END_CNTL2_R[0]), 0, 0 }, + { "mmCM1_CM_DGAM_RAMB_REGION_0_1", REG_MMIO, 0x0e00, 2, &mmCM1_CM_DGAM_RAMB_REGION_0_1[0], sizeof(mmCM1_CM_DGAM_RAMB_REGION_0_1)/sizeof(mmCM1_CM_DGAM_RAMB_REGION_0_1[0]), 0, 0 }, + { "mmCM1_CM_DGAM_RAMB_REGION_2_3", REG_MMIO, 0x0e01, 2, &mmCM1_CM_DGAM_RAMB_REGION_2_3[0], sizeof(mmCM1_CM_DGAM_RAMB_REGION_2_3)/sizeof(mmCM1_CM_DGAM_RAMB_REGION_2_3[0]), 0, 0 }, + { "mmCM1_CM_DGAM_RAMB_REGION_4_5", REG_MMIO, 0x0e02, 2, &mmCM1_CM_DGAM_RAMB_REGION_4_5[0], sizeof(mmCM1_CM_DGAM_RAMB_REGION_4_5)/sizeof(mmCM1_CM_DGAM_RAMB_REGION_4_5[0]), 0, 0 }, + { "mmCM1_CM_DGAM_RAMB_REGION_6_7", REG_MMIO, 0x0e03, 2, &mmCM1_CM_DGAM_RAMB_REGION_6_7[0], sizeof(mmCM1_CM_DGAM_RAMB_REGION_6_7)/sizeof(mmCM1_CM_DGAM_RAMB_REGION_6_7[0]), 0, 0 }, + { "mmCM1_CM_DGAM_RAMB_REGION_8_9", REG_MMIO, 0x0e04, 2, &mmCM1_CM_DGAM_RAMB_REGION_8_9[0], sizeof(mmCM1_CM_DGAM_RAMB_REGION_8_9)/sizeof(mmCM1_CM_DGAM_RAMB_REGION_8_9[0]), 0, 0 }, + { "mmCM1_CM_DGAM_RAMB_REGION_10_11", REG_MMIO, 0x0e05, 2, &mmCM1_CM_DGAM_RAMB_REGION_10_11[0], sizeof(mmCM1_CM_DGAM_RAMB_REGION_10_11)/sizeof(mmCM1_CM_DGAM_RAMB_REGION_10_11[0]), 0, 0 }, + { "mmCM1_CM_DGAM_RAMB_REGION_12_13", REG_MMIO, 0x0e06, 2, &mmCM1_CM_DGAM_RAMB_REGION_12_13[0], sizeof(mmCM1_CM_DGAM_RAMB_REGION_12_13)/sizeof(mmCM1_CM_DGAM_RAMB_REGION_12_13[0]), 0, 0 }, + { "mmCM1_CM_DGAM_RAMB_REGION_14_15", REG_MMIO, 0x0e07, 2, &mmCM1_CM_DGAM_RAMB_REGION_14_15[0], sizeof(mmCM1_CM_DGAM_RAMB_REGION_14_15)/sizeof(mmCM1_CM_DGAM_RAMB_REGION_14_15[0]), 0, 0 }, + { "mmCM1_CM_RGAM_CONTROL", REG_MMIO, 0x0e08, 2, &mmCM1_CM_RGAM_CONTROL[0], sizeof(mmCM1_CM_RGAM_CONTROL)/sizeof(mmCM1_CM_RGAM_CONTROL[0]), 0, 0 }, + { "mmCM1_CM_RGAM_LUT_INDEX", REG_MMIO, 0x0e09, 2, &mmCM1_CM_RGAM_LUT_INDEX[0], sizeof(mmCM1_CM_RGAM_LUT_INDEX)/sizeof(mmCM1_CM_RGAM_LUT_INDEX[0]), 0, 0 }, + { "mmCM1_CM_RGAM_LUT_DATA", REG_MMIO, 0x0e0a, 2, &mmCM1_CM_RGAM_LUT_DATA[0], sizeof(mmCM1_CM_RGAM_LUT_DATA)/sizeof(mmCM1_CM_RGAM_LUT_DATA[0]), 0, 0 }, + { "mmCM1_CM_RGAM_LUT_WRITE_EN_MASK", REG_MMIO, 0x0e0b, 2, &mmCM1_CM_RGAM_LUT_WRITE_EN_MASK[0], sizeof(mmCM1_CM_RGAM_LUT_WRITE_EN_MASK)/sizeof(mmCM1_CM_RGAM_LUT_WRITE_EN_MASK[0]), 0, 0 }, + { "mmCM1_CM_RGAM_RAMA_START_CNTL_B", REG_MMIO, 0x0e0c, 2, &mmCM1_CM_RGAM_RAMA_START_CNTL_B[0], sizeof(mmCM1_CM_RGAM_RAMA_START_CNTL_B)/sizeof(mmCM1_CM_RGAM_RAMA_START_CNTL_B[0]), 0, 0 }, + { "mmCM1_CM_RGAM_RAMA_START_CNTL_G", REG_MMIO, 0x0e0d, 2, &mmCM1_CM_RGAM_RAMA_START_CNTL_G[0], sizeof(mmCM1_CM_RGAM_RAMA_START_CNTL_G)/sizeof(mmCM1_CM_RGAM_RAMA_START_CNTL_G[0]), 0, 0 }, + { "mmCM1_CM_RGAM_RAMA_START_CNTL_R", REG_MMIO, 0x0e0e, 2, &mmCM1_CM_RGAM_RAMA_START_CNTL_R[0], sizeof(mmCM1_CM_RGAM_RAMA_START_CNTL_R)/sizeof(mmCM1_CM_RGAM_RAMA_START_CNTL_R[0]), 0, 0 }, + { "mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_B", REG_MMIO, 0x0e0f, 2, &mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_B[0], sizeof(mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_B)/sizeof(mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_B[0]), 0, 0 }, + { "mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_G", REG_MMIO, 0x0e10, 2, &mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_G[0], sizeof(mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_G)/sizeof(mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_G[0]), 0, 0 }, + { "mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_R", REG_MMIO, 0x0e11, 2, &mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_R[0], sizeof(mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_R)/sizeof(mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_R[0]), 0, 0 }, + { "mmCM1_CM_RGAM_RAMA_END_CNTL1_B", REG_MMIO, 0x0e12, 2, &mmCM1_CM_RGAM_RAMA_END_CNTL1_B[0], sizeof(mmCM1_CM_RGAM_RAMA_END_CNTL1_B)/sizeof(mmCM1_CM_RGAM_RAMA_END_CNTL1_B[0]), 0, 0 }, + { "mmCM1_CM_RGAM_RAMA_END_CNTL2_B", REG_MMIO, 0x0e13, 2, &mmCM1_CM_RGAM_RAMA_END_CNTL2_B[0], sizeof(mmCM1_CM_RGAM_RAMA_END_CNTL2_B)/sizeof(mmCM1_CM_RGAM_RAMA_END_CNTL2_B[0]), 0, 0 }, + { "mmCM1_CM_RGAM_RAMA_END_CNTL1_G", REG_MMIO, 0x0e14, 2, &mmCM1_CM_RGAM_RAMA_END_CNTL1_G[0], sizeof(mmCM1_CM_RGAM_RAMA_END_CNTL1_G)/sizeof(mmCM1_CM_RGAM_RAMA_END_CNTL1_G[0]), 0, 0 }, + { "mmCM1_CM_RGAM_RAMA_END_CNTL2_G", REG_MMIO, 0x0e15, 2, &mmCM1_CM_RGAM_RAMA_END_CNTL2_G[0], sizeof(mmCM1_CM_RGAM_RAMA_END_CNTL2_G)/sizeof(mmCM1_CM_RGAM_RAMA_END_CNTL2_G[0]), 0, 0 }, + { "mmCM1_CM_RGAM_RAMA_END_CNTL1_R", REG_MMIO, 0x0e16, 2, &mmCM1_CM_RGAM_RAMA_END_CNTL1_R[0], sizeof(mmCM1_CM_RGAM_RAMA_END_CNTL1_R)/sizeof(mmCM1_CM_RGAM_RAMA_END_CNTL1_R[0]), 0, 0 }, + { "mmCM1_CM_RGAM_RAMA_END_CNTL2_R", REG_MMIO, 0x0e17, 2, &mmCM1_CM_RGAM_RAMA_END_CNTL2_R[0], sizeof(mmCM1_CM_RGAM_RAMA_END_CNTL2_R)/sizeof(mmCM1_CM_RGAM_RAMA_END_CNTL2_R[0]), 0, 0 }, + { "mmCM1_CM_RGAM_RAMA_REGION_0_1", REG_MMIO, 0x0e18, 2, &mmCM1_CM_RGAM_RAMA_REGION_0_1[0], sizeof(mmCM1_CM_RGAM_RAMA_REGION_0_1)/sizeof(mmCM1_CM_RGAM_RAMA_REGION_0_1[0]), 0, 0 }, + { "mmCM1_CM_RGAM_RAMA_REGION_2_3", REG_MMIO, 0x0e19, 2, &mmCM1_CM_RGAM_RAMA_REGION_2_3[0], sizeof(mmCM1_CM_RGAM_RAMA_REGION_2_3)/sizeof(mmCM1_CM_RGAM_RAMA_REGION_2_3[0]), 0, 0 }, + { "mmCM1_CM_RGAM_RAMA_REGION_4_5", REG_MMIO, 0x0e1a, 2, &mmCM1_CM_RGAM_RAMA_REGION_4_5[0], sizeof(mmCM1_CM_RGAM_RAMA_REGION_4_5)/sizeof(mmCM1_CM_RGAM_RAMA_REGION_4_5[0]), 0, 0 }, + { "mmCM1_CM_RGAM_RAMA_REGION_6_7", REG_MMIO, 0x0e1b, 2, &mmCM1_CM_RGAM_RAMA_REGION_6_7[0], sizeof(mmCM1_CM_RGAM_RAMA_REGION_6_7)/sizeof(mmCM1_CM_RGAM_RAMA_REGION_6_7[0]), 0, 0 }, + { "mmCM1_CM_RGAM_RAMA_REGION_8_9", REG_MMIO, 0x0e1c, 2, &mmCM1_CM_RGAM_RAMA_REGION_8_9[0], sizeof(mmCM1_CM_RGAM_RAMA_REGION_8_9)/sizeof(mmCM1_CM_RGAM_RAMA_REGION_8_9[0]), 0, 0 }, + { "mmCM1_CM_RGAM_RAMA_REGION_10_11", REG_MMIO, 0x0e1d, 2, &mmCM1_CM_RGAM_RAMA_REGION_10_11[0], sizeof(mmCM1_CM_RGAM_RAMA_REGION_10_11)/sizeof(mmCM1_CM_RGAM_RAMA_REGION_10_11[0]), 0, 0 }, + { "mmCM1_CM_RGAM_RAMA_REGION_12_13", REG_MMIO, 0x0e1e, 2, &mmCM1_CM_RGAM_RAMA_REGION_12_13[0], sizeof(mmCM1_CM_RGAM_RAMA_REGION_12_13)/sizeof(mmCM1_CM_RGAM_RAMA_REGION_12_13[0]), 0, 0 }, + { "mmCM1_CM_RGAM_RAMA_REGION_14_15", REG_MMIO, 0x0e1f, 2, &mmCM1_CM_RGAM_RAMA_REGION_14_15[0], sizeof(mmCM1_CM_RGAM_RAMA_REGION_14_15)/sizeof(mmCM1_CM_RGAM_RAMA_REGION_14_15[0]), 0, 0 }, + { "mmCM1_CM_RGAM_RAMA_REGION_16_17", REG_MMIO, 0x0e20, 2, &mmCM1_CM_RGAM_RAMA_REGION_16_17[0], sizeof(mmCM1_CM_RGAM_RAMA_REGION_16_17)/sizeof(mmCM1_CM_RGAM_RAMA_REGION_16_17[0]), 0, 0 }, + { "mmCM1_CM_RGAM_RAMA_REGION_18_19", REG_MMIO, 0x0e21, 2, &mmCM1_CM_RGAM_RAMA_REGION_18_19[0], sizeof(mmCM1_CM_RGAM_RAMA_REGION_18_19)/sizeof(mmCM1_CM_RGAM_RAMA_REGION_18_19[0]), 0, 0 }, + { "mmCM1_CM_RGAM_RAMA_REGION_20_21", REG_MMIO, 0x0e22, 2, &mmCM1_CM_RGAM_RAMA_REGION_20_21[0], sizeof(mmCM1_CM_RGAM_RAMA_REGION_20_21)/sizeof(mmCM1_CM_RGAM_RAMA_REGION_20_21[0]), 0, 0 }, + { "mmCM1_CM_RGAM_RAMA_REGION_22_23", REG_MMIO, 0x0e23, 2, &mmCM1_CM_RGAM_RAMA_REGION_22_23[0], sizeof(mmCM1_CM_RGAM_RAMA_REGION_22_23)/sizeof(mmCM1_CM_RGAM_RAMA_REGION_22_23[0]), 0, 0 }, + { "mmCM1_CM_RGAM_RAMA_REGION_24_25", REG_MMIO, 0x0e24, 2, &mmCM1_CM_RGAM_RAMA_REGION_24_25[0], sizeof(mmCM1_CM_RGAM_RAMA_REGION_24_25)/sizeof(mmCM1_CM_RGAM_RAMA_REGION_24_25[0]), 0, 0 }, + { "mmCM1_CM_RGAM_RAMA_REGION_26_27", REG_MMIO, 0x0e25, 2, &mmCM1_CM_RGAM_RAMA_REGION_26_27[0], sizeof(mmCM1_CM_RGAM_RAMA_REGION_26_27)/sizeof(mmCM1_CM_RGAM_RAMA_REGION_26_27[0]), 0, 0 }, + { "mmCM1_CM_RGAM_RAMA_REGION_28_29", REG_MMIO, 0x0e26, 2, &mmCM1_CM_RGAM_RAMA_REGION_28_29[0], sizeof(mmCM1_CM_RGAM_RAMA_REGION_28_29)/sizeof(mmCM1_CM_RGAM_RAMA_REGION_28_29[0]), 0, 0 }, + { "mmCM1_CM_RGAM_RAMA_REGION_30_31", REG_MMIO, 0x0e27, 2, &mmCM1_CM_RGAM_RAMA_REGION_30_31[0], sizeof(mmCM1_CM_RGAM_RAMA_REGION_30_31)/sizeof(mmCM1_CM_RGAM_RAMA_REGION_30_31[0]), 0, 0 }, + { "mmCM1_CM_RGAM_RAMA_REGION_32_33", REG_MMIO, 0x0e28, 2, &mmCM1_CM_RGAM_RAMA_REGION_32_33[0], sizeof(mmCM1_CM_RGAM_RAMA_REGION_32_33)/sizeof(mmCM1_CM_RGAM_RAMA_REGION_32_33[0]), 0, 0 }, + { "mmCM1_CM_RGAM_RAMB_START_CNTL_B", REG_MMIO, 0x0e29, 2, &mmCM1_CM_RGAM_RAMB_START_CNTL_B[0], sizeof(mmCM1_CM_RGAM_RAMB_START_CNTL_B)/sizeof(mmCM1_CM_RGAM_RAMB_START_CNTL_B[0]), 0, 0 }, + { "mmCM1_CM_RGAM_RAMB_START_CNTL_G", REG_MMIO, 0x0e2a, 2, &mmCM1_CM_RGAM_RAMB_START_CNTL_G[0], sizeof(mmCM1_CM_RGAM_RAMB_START_CNTL_G)/sizeof(mmCM1_CM_RGAM_RAMB_START_CNTL_G[0]), 0, 0 }, + { "mmCM1_CM_RGAM_RAMB_START_CNTL_R", REG_MMIO, 0x0e2b, 2, &mmCM1_CM_RGAM_RAMB_START_CNTL_R[0], sizeof(mmCM1_CM_RGAM_RAMB_START_CNTL_R)/sizeof(mmCM1_CM_RGAM_RAMB_START_CNTL_R[0]), 0, 0 }, + { "mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_B", REG_MMIO, 0x0e2c, 2, &mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_B[0], sizeof(mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_B)/sizeof(mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_B[0]), 0, 0 }, + { "mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_G", REG_MMIO, 0x0e2d, 2, &mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_G[0], sizeof(mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_G)/sizeof(mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_G[0]), 0, 0 }, + { "mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_R", REG_MMIO, 0x0e2e, 2, &mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_R[0], sizeof(mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_R)/sizeof(mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_R[0]), 0, 0 }, + { "mmCM1_CM_RGAM_RAMB_END_CNTL1_B", REG_MMIO, 0x0e2f, 2, &mmCM1_CM_RGAM_RAMB_END_CNTL1_B[0], sizeof(mmCM1_CM_RGAM_RAMB_END_CNTL1_B)/sizeof(mmCM1_CM_RGAM_RAMB_END_CNTL1_B[0]), 0, 0 }, + { "mmCM1_CM_RGAM_RAMB_END_CNTL2_B", REG_MMIO, 0x0e30, 2, &mmCM1_CM_RGAM_RAMB_END_CNTL2_B[0], sizeof(mmCM1_CM_RGAM_RAMB_END_CNTL2_B)/sizeof(mmCM1_CM_RGAM_RAMB_END_CNTL2_B[0]), 0, 0 }, + { "mmCM1_CM_RGAM_RAMB_END_CNTL1_G", REG_MMIO, 0x0e31, 2, &mmCM1_CM_RGAM_RAMB_END_CNTL1_G[0], sizeof(mmCM1_CM_RGAM_RAMB_END_CNTL1_G)/sizeof(mmCM1_CM_RGAM_RAMB_END_CNTL1_G[0]), 0, 0 }, + { "mmCM1_CM_RGAM_RAMB_END_CNTL2_G", REG_MMIO, 0x0e32, 2, &mmCM1_CM_RGAM_RAMB_END_CNTL2_G[0], sizeof(mmCM1_CM_RGAM_RAMB_END_CNTL2_G)/sizeof(mmCM1_CM_RGAM_RAMB_END_CNTL2_G[0]), 0, 0 }, + { "mmCM1_CM_RGAM_RAMB_END_CNTL1_R", REG_MMIO, 0x0e33, 2, &mmCM1_CM_RGAM_RAMB_END_CNTL1_R[0], sizeof(mmCM1_CM_RGAM_RAMB_END_CNTL1_R)/sizeof(mmCM1_CM_RGAM_RAMB_END_CNTL1_R[0]), 0, 0 }, + { "mmCM1_CM_RGAM_RAMB_END_CNTL2_R", REG_MMIO, 0x0e34, 2, &mmCM1_CM_RGAM_RAMB_END_CNTL2_R[0], sizeof(mmCM1_CM_RGAM_RAMB_END_CNTL2_R)/sizeof(mmCM1_CM_RGAM_RAMB_END_CNTL2_R[0]), 0, 0 }, + { "mmCM1_CM_RGAM_RAMB_REGION_0_1", REG_MMIO, 0x0e35, 2, &mmCM1_CM_RGAM_RAMB_REGION_0_1[0], sizeof(mmCM1_CM_RGAM_RAMB_REGION_0_1)/sizeof(mmCM1_CM_RGAM_RAMB_REGION_0_1[0]), 0, 0 }, + { "mmCM1_CM_RGAM_RAMB_REGION_2_3", REG_MMIO, 0x0e36, 2, &mmCM1_CM_RGAM_RAMB_REGION_2_3[0], sizeof(mmCM1_CM_RGAM_RAMB_REGION_2_3)/sizeof(mmCM1_CM_RGAM_RAMB_REGION_2_3[0]), 0, 0 }, + { "mmCM1_CM_RGAM_RAMB_REGION_4_5", REG_MMIO, 0x0e37, 2, &mmCM1_CM_RGAM_RAMB_REGION_4_5[0], sizeof(mmCM1_CM_RGAM_RAMB_REGION_4_5)/sizeof(mmCM1_CM_RGAM_RAMB_REGION_4_5[0]), 0, 0 }, + { "mmCM1_CM_RGAM_RAMB_REGION_6_7", REG_MMIO, 0x0e38, 2, &mmCM1_CM_RGAM_RAMB_REGION_6_7[0], sizeof(mmCM1_CM_RGAM_RAMB_REGION_6_7)/sizeof(mmCM1_CM_RGAM_RAMB_REGION_6_7[0]), 0, 0 }, + { "mmCM1_CM_RGAM_RAMB_REGION_8_9", REG_MMIO, 0x0e39, 2, &mmCM1_CM_RGAM_RAMB_REGION_8_9[0], sizeof(mmCM1_CM_RGAM_RAMB_REGION_8_9)/sizeof(mmCM1_CM_RGAM_RAMB_REGION_8_9[0]), 0, 0 }, + { "mmCM1_CM_RGAM_RAMB_REGION_10_11", REG_MMIO, 0x0e3a, 2, &mmCM1_CM_RGAM_RAMB_REGION_10_11[0], sizeof(mmCM1_CM_RGAM_RAMB_REGION_10_11)/sizeof(mmCM1_CM_RGAM_RAMB_REGION_10_11[0]), 0, 0 }, + { "mmCM1_CM_RGAM_RAMB_REGION_12_13", REG_MMIO, 0x0e3b, 2, &mmCM1_CM_RGAM_RAMB_REGION_12_13[0], sizeof(mmCM1_CM_RGAM_RAMB_REGION_12_13)/sizeof(mmCM1_CM_RGAM_RAMB_REGION_12_13[0]), 0, 0 }, + { "mmCM1_CM_RGAM_RAMB_REGION_14_15", REG_MMIO, 0x0e3c, 2, &mmCM1_CM_RGAM_RAMB_REGION_14_15[0], sizeof(mmCM1_CM_RGAM_RAMB_REGION_14_15)/sizeof(mmCM1_CM_RGAM_RAMB_REGION_14_15[0]), 0, 0 }, + { "mmCM1_CM_RGAM_RAMB_REGION_16_17", REG_MMIO, 0x0e3d, 2, &mmCM1_CM_RGAM_RAMB_REGION_16_17[0], sizeof(mmCM1_CM_RGAM_RAMB_REGION_16_17)/sizeof(mmCM1_CM_RGAM_RAMB_REGION_16_17[0]), 0, 0 }, + { "mmCM1_CM_RGAM_RAMB_REGION_18_19", REG_MMIO, 0x0e3e, 2, &mmCM1_CM_RGAM_RAMB_REGION_18_19[0], sizeof(mmCM1_CM_RGAM_RAMB_REGION_18_19)/sizeof(mmCM1_CM_RGAM_RAMB_REGION_18_19[0]), 0, 0 }, + { "mmCM1_CM_RGAM_RAMB_REGION_20_21", REG_MMIO, 0x0e3f, 2, &mmCM1_CM_RGAM_RAMB_REGION_20_21[0], sizeof(mmCM1_CM_RGAM_RAMB_REGION_20_21)/sizeof(mmCM1_CM_RGAM_RAMB_REGION_20_21[0]), 0, 0 }, + { "mmCM1_CM_RGAM_RAMB_REGION_22_23", REG_MMIO, 0x0e40, 2, &mmCM1_CM_RGAM_RAMB_REGION_22_23[0], sizeof(mmCM1_CM_RGAM_RAMB_REGION_22_23)/sizeof(mmCM1_CM_RGAM_RAMB_REGION_22_23[0]), 0, 0 }, + { "mmCM1_CM_RGAM_RAMB_REGION_24_25", REG_MMIO, 0x0e41, 2, &mmCM1_CM_RGAM_RAMB_REGION_24_25[0], sizeof(mmCM1_CM_RGAM_RAMB_REGION_24_25)/sizeof(mmCM1_CM_RGAM_RAMB_REGION_24_25[0]), 0, 0 }, + { "mmCM1_CM_RGAM_RAMB_REGION_26_27", REG_MMIO, 0x0e42, 2, &mmCM1_CM_RGAM_RAMB_REGION_26_27[0], sizeof(mmCM1_CM_RGAM_RAMB_REGION_26_27)/sizeof(mmCM1_CM_RGAM_RAMB_REGION_26_27[0]), 0, 0 }, + { "mmCM1_CM_RGAM_RAMB_REGION_28_29", REG_MMIO, 0x0e43, 2, &mmCM1_CM_RGAM_RAMB_REGION_28_29[0], sizeof(mmCM1_CM_RGAM_RAMB_REGION_28_29)/sizeof(mmCM1_CM_RGAM_RAMB_REGION_28_29[0]), 0, 0 }, + { "mmCM1_CM_RGAM_RAMB_REGION_30_31", REG_MMIO, 0x0e44, 2, &mmCM1_CM_RGAM_RAMB_REGION_30_31[0], sizeof(mmCM1_CM_RGAM_RAMB_REGION_30_31)/sizeof(mmCM1_CM_RGAM_RAMB_REGION_30_31[0]), 0, 0 }, + { "mmCM1_CM_RGAM_RAMB_REGION_32_33", REG_MMIO, 0x0e45, 2, &mmCM1_CM_RGAM_RAMB_REGION_32_33[0], sizeof(mmCM1_CM_RGAM_RAMB_REGION_32_33)/sizeof(mmCM1_CM_RGAM_RAMB_REGION_32_33[0]), 0, 0 }, + { "mmCM1_CM_HDR_MULT_COEF", REG_MMIO, 0x0e46, 2, &mmCM1_CM_HDR_MULT_COEF[0], sizeof(mmCM1_CM_HDR_MULT_COEF)/sizeof(mmCM1_CM_HDR_MULT_COEF[0]), 0, 0 }, + { "mmCM1_CM_RANGE_CLAMP_CONTROL_R", REG_MMIO, 0x0e47, 2, &mmCM1_CM_RANGE_CLAMP_CONTROL_R[0], sizeof(mmCM1_CM_RANGE_CLAMP_CONTROL_R)/sizeof(mmCM1_CM_RANGE_CLAMP_CONTROL_R[0]), 0, 0 }, + { "mmCM1_CM_RANGE_CLAMP_CONTROL_G", REG_MMIO, 0x0e48, 2, &mmCM1_CM_RANGE_CLAMP_CONTROL_G[0], sizeof(mmCM1_CM_RANGE_CLAMP_CONTROL_G)/sizeof(mmCM1_CM_RANGE_CLAMP_CONTROL_G[0]), 0, 0 }, + { "mmCM1_CM_RANGE_CLAMP_CONTROL_B", REG_MMIO, 0x0e49, 2, &mmCM1_CM_RANGE_CLAMP_CONTROL_B[0], sizeof(mmCM1_CM_RANGE_CLAMP_CONTROL_B)/sizeof(mmCM1_CM_RANGE_CLAMP_CONTROL_B[0]), 0, 0 }, + { "mmCM1_CM_DENORM_CONTROL", REG_MMIO, 0x0e4a, 2, &mmCM1_CM_DENORM_CONTROL[0], sizeof(mmCM1_CM_DENORM_CONTROL)/sizeof(mmCM1_CM_DENORM_CONTROL[0]), 0, 0 }, + { "mmCM1_CM_CMOUT_CONTROL", REG_MMIO, 0x0e4b, 2, &mmCM1_CM_CMOUT_CONTROL[0], sizeof(mmCM1_CM_CMOUT_CONTROL)/sizeof(mmCM1_CM_CMOUT_CONTROL[0]), 0, 0 }, + { "mmCM1_CM_CMOUT_RANDOM_SEEDS", REG_MMIO, 0x0e4c, 2, &mmCM1_CM_CMOUT_RANDOM_SEEDS[0], sizeof(mmCM1_CM_CMOUT_RANDOM_SEEDS)/sizeof(mmCM1_CM_CMOUT_RANDOM_SEEDS[0]), 0, 0 }, + { "mmCM1_CM_MEM_PWR_CTRL", REG_MMIO, 0x0e4d, 2, &mmCM1_CM_MEM_PWR_CTRL[0], sizeof(mmCM1_CM_MEM_PWR_CTRL)/sizeof(mmCM1_CM_MEM_PWR_CTRL[0]), 0, 0 }, + { "mmCM1_CM_MEM_PWR_STATUS", REG_MMIO, 0x0e4e, 2, &mmCM1_CM_MEM_PWR_STATUS[0], sizeof(mmCM1_CM_MEM_PWR_STATUS)/sizeof(mmCM1_CM_MEM_PWR_STATUS[0]), 0, 0 }, + { "mmDC_PERFMON13_PERFCOUNTER_CNTL", REG_MMIO, 0x0e67, 2, &mmDC_PERFMON13_PERFCOUNTER_CNTL[0], sizeof(mmDC_PERFMON13_PERFCOUNTER_CNTL)/sizeof(mmDC_PERFMON13_PERFCOUNTER_CNTL[0]), 0, 0 }, + { "mmDC_PERFMON13_PERFCOUNTER_CNTL2", REG_MMIO, 0x0e68, 2, &mmDC_PERFMON13_PERFCOUNTER_CNTL2[0], sizeof(mmDC_PERFMON13_PERFCOUNTER_CNTL2)/sizeof(mmDC_PERFMON13_PERFCOUNTER_CNTL2[0]), 0, 0 }, + { "mmDC_PERFMON13_PERFCOUNTER_STATE", REG_MMIO, 0x0e69, 2, &mmDC_PERFMON13_PERFCOUNTER_STATE[0], sizeof(mmDC_PERFMON13_PERFCOUNTER_STATE)/sizeof(mmDC_PERFMON13_PERFCOUNTER_STATE[0]), 0, 0 }, + { "mmDC_PERFMON13_PERFMON_CNTL", REG_MMIO, 0x0e6a, 2, &mmDC_PERFMON13_PERFMON_CNTL[0], sizeof(mmDC_PERFMON13_PERFMON_CNTL)/sizeof(mmDC_PERFMON13_PERFMON_CNTL[0]), 0, 0 }, + { "mmDC_PERFMON13_PERFMON_CNTL2", REG_MMIO, 0x0e6b, 2, &mmDC_PERFMON13_PERFMON_CNTL2[0], sizeof(mmDC_PERFMON13_PERFMON_CNTL2)/sizeof(mmDC_PERFMON13_PERFMON_CNTL2[0]), 0, 0 }, + { "mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC", REG_MMIO, 0x0e6c, 2, &mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC[0], sizeof(mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC)/sizeof(mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC[0]), 0, 0 }, + { "mmDC_PERFMON13_PERFMON_CVALUE_LOW", REG_MMIO, 0x0e6d, 2, &mmDC_PERFMON13_PERFMON_CVALUE_LOW[0], sizeof(mmDC_PERFMON13_PERFMON_CVALUE_LOW)/sizeof(mmDC_PERFMON13_PERFMON_CVALUE_LOW[0]), 0, 0 }, + { "mmDC_PERFMON13_PERFMON_HI", REG_MMIO, 0x0e6e, 2, &mmDC_PERFMON13_PERFMON_HI[0], sizeof(mmDC_PERFMON13_PERFMON_HI)/sizeof(mmDC_PERFMON13_PERFMON_HI[0]), 0, 0 }, + { "mmDC_PERFMON13_PERFMON_LOW", REG_MMIO, 0x0e6f, 2, &mmDC_PERFMON13_PERFMON_LOW[0], sizeof(mmDC_PERFMON13_PERFMON_LOW)/sizeof(mmDC_PERFMON13_PERFMON_LOW[0]), 0, 0 }, + { "mmDPP_TOP2_DPP_CONTROL", REG_MMIO, 0x0e73, 2, &mmDPP_TOP2_DPP_CONTROL[0], sizeof(mmDPP_TOP2_DPP_CONTROL)/sizeof(mmDPP_TOP2_DPP_CONTROL[0]), 0, 0 }, + { "mmDPP_TOP2_DPP_SOFT_RESET", REG_MMIO, 0x0e74, 2, &mmDPP_TOP2_DPP_SOFT_RESET[0], sizeof(mmDPP_TOP2_DPP_SOFT_RESET)/sizeof(mmDPP_TOP2_DPP_SOFT_RESET[0]), 0, 0 }, + { "mmDPP_TOP2_DPP_CRC_VAL_R_G", REG_MMIO, 0x0e75, 2, &mmDPP_TOP2_DPP_CRC_VAL_R_G[0], sizeof(mmDPP_TOP2_DPP_CRC_VAL_R_G)/sizeof(mmDPP_TOP2_DPP_CRC_VAL_R_G[0]), 0, 0 }, + { "mmDPP_TOP2_DPP_CRC_VAL_B_A", REG_MMIO, 0x0e76, 2, &mmDPP_TOP2_DPP_CRC_VAL_B_A[0], sizeof(mmDPP_TOP2_DPP_CRC_VAL_B_A)/sizeof(mmDPP_TOP2_DPP_CRC_VAL_B_A[0]), 0, 0 }, + { "mmDPP_TOP2_DPP_CRC_CTRL", REG_MMIO, 0x0e77, 2, &mmDPP_TOP2_DPP_CRC_CTRL[0], sizeof(mmDPP_TOP2_DPP_CRC_CTRL)/sizeof(mmDPP_TOP2_DPP_CRC_CTRL[0]), 0, 0 }, + { "mmDPP_TOP2_HOST_READ_CONTROL", REG_MMIO, 0x0e78, 2, &mmDPP_TOP2_HOST_READ_CONTROL[0], sizeof(mmDPP_TOP2_HOST_READ_CONTROL)/sizeof(mmDPP_TOP2_HOST_READ_CONTROL[0]), 0, 0 }, + { "mmCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT", REG_MMIO, 0x0e7d, 2, &mmCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT[0], sizeof(mmCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT)/sizeof(mmCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT[0]), 0, 0 }, + { "mmCNVC_CFG2_FORMAT_CONTROL", REG_MMIO, 0x0e7e, 2, &mmCNVC_CFG2_FORMAT_CONTROL[0], sizeof(mmCNVC_CFG2_FORMAT_CONTROL)/sizeof(mmCNVC_CFG2_FORMAT_CONTROL[0]), 0, 0 }, + { "mmCNVC_CFG2_FCNV_FP_SCALE_BIAS", REG_MMIO, 0x0e7f, 2, &mmCNVC_CFG2_FCNV_FP_SCALE_BIAS[0], sizeof(mmCNVC_CFG2_FCNV_FP_SCALE_BIAS)/sizeof(mmCNVC_CFG2_FCNV_FP_SCALE_BIAS[0]), 0, 0 }, + { "mmCNVC_CFG2_DENORM_CONTROL", REG_MMIO, 0x0e80, 2, &mmCNVC_CFG2_DENORM_CONTROL[0], sizeof(mmCNVC_CFG2_DENORM_CONTROL)/sizeof(mmCNVC_CFG2_DENORM_CONTROL[0]), 0, 0 }, + { "mmCNVC_CFG2_COLOR_KEYER_CONTROL", REG_MMIO, 0x0e82, 2, &mmCNVC_CFG2_COLOR_KEYER_CONTROL[0], sizeof(mmCNVC_CFG2_COLOR_KEYER_CONTROL)/sizeof(mmCNVC_CFG2_COLOR_KEYER_CONTROL[0]), 0, 0 }, + { "mmCNVC_CFG2_COLOR_KEYER_ALPHA", REG_MMIO, 0x0e83, 2, &mmCNVC_CFG2_COLOR_KEYER_ALPHA[0], sizeof(mmCNVC_CFG2_COLOR_KEYER_ALPHA)/sizeof(mmCNVC_CFG2_COLOR_KEYER_ALPHA[0]), 0, 0 }, + { "mmCNVC_CFG2_COLOR_KEYER_RED", REG_MMIO, 0x0e84, 2, &mmCNVC_CFG2_COLOR_KEYER_RED[0], sizeof(mmCNVC_CFG2_COLOR_KEYER_RED)/sizeof(mmCNVC_CFG2_COLOR_KEYER_RED[0]), 0, 0 }, + { "mmCNVC_CFG2_COLOR_KEYER_GREEN", REG_MMIO, 0x0e85, 2, &mmCNVC_CFG2_COLOR_KEYER_GREEN[0], sizeof(mmCNVC_CFG2_COLOR_KEYER_GREEN)/sizeof(mmCNVC_CFG2_COLOR_KEYER_GREEN[0]), 0, 0 }, + { "mmCNVC_CFG2_COLOR_KEYER_BLUE", REG_MMIO, 0x0e86, 2, &mmCNVC_CFG2_COLOR_KEYER_BLUE[0], sizeof(mmCNVC_CFG2_COLOR_KEYER_BLUE)/sizeof(mmCNVC_CFG2_COLOR_KEYER_BLUE[0]), 0, 0 }, + { "mmCNVC_CUR2_CURSOR0_CONTROL", REG_MMIO, 0x0e8e, 2, &mmCNVC_CUR2_CURSOR0_CONTROL[0], sizeof(mmCNVC_CUR2_CURSOR0_CONTROL)/sizeof(mmCNVC_CUR2_CURSOR0_CONTROL[0]), 0, 0 }, + { "mmCNVC_CUR2_CURSOR0_COLOR0", REG_MMIO, 0x0e8f, 2, &mmCNVC_CUR2_CURSOR0_COLOR0[0], sizeof(mmCNVC_CUR2_CURSOR0_COLOR0)/sizeof(mmCNVC_CUR2_CURSOR0_COLOR0[0]), 0, 0 }, + { "mmCNVC_CUR2_CURSOR0_COLOR1", REG_MMIO, 0x0e90, 2, &mmCNVC_CUR2_CURSOR0_COLOR1[0], sizeof(mmCNVC_CUR2_CURSOR0_COLOR1)/sizeof(mmCNVC_CUR2_CURSOR0_COLOR1[0]), 0, 0 }, + { "mmCNVC_CUR2_CURSOR0_FP_SCALE_BIAS", REG_MMIO, 0x0e91, 2, &mmCNVC_CUR2_CURSOR0_FP_SCALE_BIAS[0], sizeof(mmCNVC_CUR2_CURSOR0_FP_SCALE_BIAS)/sizeof(mmCNVC_CUR2_CURSOR0_FP_SCALE_BIAS[0]), 0, 0 }, + { "mmDSCL2_SCL_COEF_RAM_TAP_SELECT", REG_MMIO, 0x0e98, 2, &mmDSCL2_SCL_COEF_RAM_TAP_SELECT[0], sizeof(mmDSCL2_SCL_COEF_RAM_TAP_SELECT)/sizeof(mmDSCL2_SCL_COEF_RAM_TAP_SELECT[0]), 0, 0 }, + { "mmDSCL2_SCL_COEF_RAM_TAP_DATA", REG_MMIO, 0x0e99, 2, &mmDSCL2_SCL_COEF_RAM_TAP_DATA[0], sizeof(mmDSCL2_SCL_COEF_RAM_TAP_DATA)/sizeof(mmDSCL2_SCL_COEF_RAM_TAP_DATA[0]), 0, 0 }, + { "mmDSCL2_SCL_MODE", REG_MMIO, 0x0e9a, 2, &mmDSCL2_SCL_MODE[0], sizeof(mmDSCL2_SCL_MODE)/sizeof(mmDSCL2_SCL_MODE[0]), 0, 0 }, + { "mmDSCL2_SCL_TAP_CONTROL", REG_MMIO, 0x0e9b, 2, &mmDSCL2_SCL_TAP_CONTROL[0], sizeof(mmDSCL2_SCL_TAP_CONTROL)/sizeof(mmDSCL2_SCL_TAP_CONTROL[0]), 0, 0 }, + { "mmDSCL2_DSCL_CONTROL", REG_MMIO, 0x0e9c, 2, &mmDSCL2_DSCL_CONTROL[0], sizeof(mmDSCL2_DSCL_CONTROL)/sizeof(mmDSCL2_DSCL_CONTROL[0]), 0, 0 }, + { "mmDSCL2_DSCL_2TAP_CONTROL", REG_MMIO, 0x0e9d, 2, &mmDSCL2_DSCL_2TAP_CONTROL[0], sizeof(mmDSCL2_DSCL_2TAP_CONTROL)/sizeof(mmDSCL2_DSCL_2TAP_CONTROL[0]), 0, 0 }, + { "mmDSCL2_SCL_MANUAL_REPLICATE_CONTROL", REG_MMIO, 0x0e9e, 2, &mmDSCL2_SCL_MANUAL_REPLICATE_CONTROL[0], sizeof(mmDSCL2_SCL_MANUAL_REPLICATE_CONTROL)/sizeof(mmDSCL2_SCL_MANUAL_REPLICATE_CONTROL[0]), 0, 0 }, + { "mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO", REG_MMIO, 0x0e9f, 2, &mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO[0], sizeof(mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO)/sizeof(mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO[0]), 0, 0 }, + { "mmDSCL2_SCL_HORZ_FILTER_INIT", REG_MMIO, 0x0ea0, 2, &mmDSCL2_SCL_HORZ_FILTER_INIT[0], sizeof(mmDSCL2_SCL_HORZ_FILTER_INIT)/sizeof(mmDSCL2_SCL_HORZ_FILTER_INIT[0]), 0, 0 }, + { "mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C", REG_MMIO, 0x0ea1, 2, &mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C[0], sizeof(mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C)/sizeof(mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C[0]), 0, 0 }, + { "mmDSCL2_SCL_HORZ_FILTER_INIT_C", REG_MMIO, 0x0ea2, 2, &mmDSCL2_SCL_HORZ_FILTER_INIT_C[0], sizeof(mmDSCL2_SCL_HORZ_FILTER_INIT_C)/sizeof(mmDSCL2_SCL_HORZ_FILTER_INIT_C[0]), 0, 0 }, + { "mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO", REG_MMIO, 0x0ea3, 2, &mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO[0], sizeof(mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO)/sizeof(mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO[0]), 0, 0 }, + { "mmDSCL2_SCL_VERT_FILTER_INIT", REG_MMIO, 0x0ea4, 2, &mmDSCL2_SCL_VERT_FILTER_INIT[0], sizeof(mmDSCL2_SCL_VERT_FILTER_INIT)/sizeof(mmDSCL2_SCL_VERT_FILTER_INIT[0]), 0, 0 }, + { "mmDSCL2_SCL_VERT_FILTER_INIT_BOT", REG_MMIO, 0x0ea5, 2, &mmDSCL2_SCL_VERT_FILTER_INIT_BOT[0], sizeof(mmDSCL2_SCL_VERT_FILTER_INIT_BOT)/sizeof(mmDSCL2_SCL_VERT_FILTER_INIT_BOT[0]), 0, 0 }, + { "mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C", REG_MMIO, 0x0ea6, 2, &mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C[0], sizeof(mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C)/sizeof(mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C[0]), 0, 0 }, + { "mmDSCL2_SCL_VERT_FILTER_INIT_C", REG_MMIO, 0x0ea7, 2, &mmDSCL2_SCL_VERT_FILTER_INIT_C[0], sizeof(mmDSCL2_SCL_VERT_FILTER_INIT_C)/sizeof(mmDSCL2_SCL_VERT_FILTER_INIT_C[0]), 0, 0 }, + { "mmDSCL2_SCL_VERT_FILTER_INIT_BOT_C", REG_MMIO, 0x0ea8, 2, &mmDSCL2_SCL_VERT_FILTER_INIT_BOT_C[0], sizeof(mmDSCL2_SCL_VERT_FILTER_INIT_BOT_C)/sizeof(mmDSCL2_SCL_VERT_FILTER_INIT_BOT_C[0]), 0, 0 }, + { "mmDSCL2_SCL_BLACK_OFFSET", REG_MMIO, 0x0ea9, 2, &mmDSCL2_SCL_BLACK_OFFSET[0], sizeof(mmDSCL2_SCL_BLACK_OFFSET)/sizeof(mmDSCL2_SCL_BLACK_OFFSET[0]), 0, 0 }, + { "mmDSCL2_DSCL_UPDATE", REG_MMIO, 0x0eaa, 2, &mmDSCL2_DSCL_UPDATE[0], sizeof(mmDSCL2_DSCL_UPDATE)/sizeof(mmDSCL2_DSCL_UPDATE[0]), 0, 0 }, + { "mmDSCL2_DSCL_AUTOCAL", REG_MMIO, 0x0eab, 2, &mmDSCL2_DSCL_AUTOCAL[0], sizeof(mmDSCL2_DSCL_AUTOCAL)/sizeof(mmDSCL2_DSCL_AUTOCAL[0]), 0, 0 }, + { "mmDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT", REG_MMIO, 0x0eac, 2, &mmDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT[0], sizeof(mmDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT)/sizeof(mmDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT[0]), 0, 0 }, + { "mmDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM", REG_MMIO, 0x0ead, 2, &mmDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM[0], sizeof(mmDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM)/sizeof(mmDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM[0]), 0, 0 }, + { "mmDSCL2_OTG_H_BLANK", REG_MMIO, 0x0eae, 2, &mmDSCL2_OTG_H_BLANK[0], sizeof(mmDSCL2_OTG_H_BLANK)/sizeof(mmDSCL2_OTG_H_BLANK[0]), 0, 0 }, + { "mmDSCL2_OTG_V_BLANK", REG_MMIO, 0x0eaf, 2, &mmDSCL2_OTG_V_BLANK[0], sizeof(mmDSCL2_OTG_V_BLANK)/sizeof(mmDSCL2_OTG_V_BLANK[0]), 0, 0 }, + { "mmDSCL2_RECOUT_START", REG_MMIO, 0x0eb0, 2, &mmDSCL2_RECOUT_START[0], sizeof(mmDSCL2_RECOUT_START)/sizeof(mmDSCL2_RECOUT_START[0]), 0, 0 }, + { "mmDSCL2_RECOUT_SIZE", REG_MMIO, 0x0eb1, 2, &mmDSCL2_RECOUT_SIZE[0], sizeof(mmDSCL2_RECOUT_SIZE)/sizeof(mmDSCL2_RECOUT_SIZE[0]), 0, 0 }, + { "mmDSCL2_MPC_SIZE", REG_MMIO, 0x0eb2, 2, &mmDSCL2_MPC_SIZE[0], sizeof(mmDSCL2_MPC_SIZE)/sizeof(mmDSCL2_MPC_SIZE[0]), 0, 0 }, + { "mmDSCL2_LB_DATA_FORMAT", REG_MMIO, 0x0eb3, 2, &mmDSCL2_LB_DATA_FORMAT[0], sizeof(mmDSCL2_LB_DATA_FORMAT)/sizeof(mmDSCL2_LB_DATA_FORMAT[0]), 0, 0 }, + { "mmDSCL2_LB_MEMORY_CTRL", REG_MMIO, 0x0eb4, 2, &mmDSCL2_LB_MEMORY_CTRL[0], sizeof(mmDSCL2_LB_MEMORY_CTRL)/sizeof(mmDSCL2_LB_MEMORY_CTRL[0]), 0, 0 }, + { "mmDSCL2_LB_V_COUNTER", REG_MMIO, 0x0eb5, 2, &mmDSCL2_LB_V_COUNTER[0], sizeof(mmDSCL2_LB_V_COUNTER)/sizeof(mmDSCL2_LB_V_COUNTER[0]), 0, 0 }, + { "mmDSCL2_DSCL_MEM_PWR_CTRL", REG_MMIO, 0x0eb6, 2, &mmDSCL2_DSCL_MEM_PWR_CTRL[0], sizeof(mmDSCL2_DSCL_MEM_PWR_CTRL)/sizeof(mmDSCL2_DSCL_MEM_PWR_CTRL[0]), 0, 0 }, + { "mmDSCL2_DSCL_MEM_PWR_STATUS", REG_MMIO, 0x0eb7, 2, &mmDSCL2_DSCL_MEM_PWR_STATUS[0], sizeof(mmDSCL2_DSCL_MEM_PWR_STATUS)/sizeof(mmDSCL2_DSCL_MEM_PWR_STATUS[0]), 0, 0 }, + { "mmDSCL2_OBUF_CONTROL", REG_MMIO, 0x0eb8, 2, &mmDSCL2_OBUF_CONTROL[0], sizeof(mmDSCL2_OBUF_CONTROL)/sizeof(mmDSCL2_OBUF_CONTROL[0]), 0, 0 }, + { "mmDSCL2_OBUF_MEM_PWR_CTRL", REG_MMIO, 0x0eb9, 2, &mmDSCL2_OBUF_MEM_PWR_CTRL[0], sizeof(mmDSCL2_OBUF_MEM_PWR_CTRL)/sizeof(mmDSCL2_OBUF_MEM_PWR_CTRL[0]), 0, 0 }, + { "mmCM2_CM_CONTROL", REG_MMIO, 0x0ec8, 2, &mmCM2_CM_CONTROL[0], sizeof(mmCM2_CM_CONTROL)/sizeof(mmCM2_CM_CONTROL[0]), 0, 0 }, + { "mmCM2_CM_COMA_C11_C12", REG_MMIO, 0x0ec9, 2, &mmCM2_CM_COMA_C11_C12[0], sizeof(mmCM2_CM_COMA_C11_C12)/sizeof(mmCM2_CM_COMA_C11_C12[0]), 0, 0 }, + { "mmCM2_CM_COMA_C13_C14", REG_MMIO, 0x0eca, 2, &mmCM2_CM_COMA_C13_C14[0], sizeof(mmCM2_CM_COMA_C13_C14)/sizeof(mmCM2_CM_COMA_C13_C14[0]), 0, 0 }, + { "mmCM2_CM_COMA_C21_C22", REG_MMIO, 0x0ecb, 2, &mmCM2_CM_COMA_C21_C22[0], sizeof(mmCM2_CM_COMA_C21_C22)/sizeof(mmCM2_CM_COMA_C21_C22[0]), 0, 0 }, + { "mmCM2_CM_COMA_C23_C24", REG_MMIO, 0x0ecc, 2, &mmCM2_CM_COMA_C23_C24[0], sizeof(mmCM2_CM_COMA_C23_C24)/sizeof(mmCM2_CM_COMA_C23_C24[0]), 0, 0 }, + { "mmCM2_CM_COMA_C31_C32", REG_MMIO, 0x0ecd, 2, &mmCM2_CM_COMA_C31_C32[0], sizeof(mmCM2_CM_COMA_C31_C32)/sizeof(mmCM2_CM_COMA_C31_C32[0]), 0, 0 }, + { "mmCM2_CM_COMA_C33_C34", REG_MMIO, 0x0ece, 2, &mmCM2_CM_COMA_C33_C34[0], sizeof(mmCM2_CM_COMA_C33_C34)/sizeof(mmCM2_CM_COMA_C33_C34[0]), 0, 0 }, + { "mmCM2_CM_COMB_C11_C12", REG_MMIO, 0x0ecf, 2, &mmCM2_CM_COMB_C11_C12[0], sizeof(mmCM2_CM_COMB_C11_C12)/sizeof(mmCM2_CM_COMB_C11_C12[0]), 0, 0 }, + { "mmCM2_CM_COMB_C13_C14", REG_MMIO, 0x0ed0, 2, &mmCM2_CM_COMB_C13_C14[0], sizeof(mmCM2_CM_COMB_C13_C14)/sizeof(mmCM2_CM_COMB_C13_C14[0]), 0, 0 }, + { "mmCM2_CM_COMB_C21_C22", REG_MMIO, 0x0ed1, 2, &mmCM2_CM_COMB_C21_C22[0], sizeof(mmCM2_CM_COMB_C21_C22)/sizeof(mmCM2_CM_COMB_C21_C22[0]), 0, 0 }, + { "mmCM2_CM_COMB_C23_C24", REG_MMIO, 0x0ed2, 2, &mmCM2_CM_COMB_C23_C24[0], sizeof(mmCM2_CM_COMB_C23_C24)/sizeof(mmCM2_CM_COMB_C23_C24[0]), 0, 0 }, + { "mmCM2_CM_COMB_C31_C32", REG_MMIO, 0x0ed3, 2, &mmCM2_CM_COMB_C31_C32[0], sizeof(mmCM2_CM_COMB_C31_C32)/sizeof(mmCM2_CM_COMB_C31_C32[0]), 0, 0 }, + { "mmCM2_CM_COMB_C33_C34", REG_MMIO, 0x0ed4, 2, &mmCM2_CM_COMB_C33_C34[0], sizeof(mmCM2_CM_COMB_C33_C34)/sizeof(mmCM2_CM_COMB_C33_C34[0]), 0, 0 }, + { "mmCM2_CM_IGAM_CONTROL", REG_MMIO, 0x0ed5, 2, &mmCM2_CM_IGAM_CONTROL[0], sizeof(mmCM2_CM_IGAM_CONTROL)/sizeof(mmCM2_CM_IGAM_CONTROL[0]), 0, 0 }, + { "mmCM2_CM_IGAM_LUT_RW_CONTROL", REG_MMIO, 0x0ed6, 2, &mmCM2_CM_IGAM_LUT_RW_CONTROL[0], sizeof(mmCM2_CM_IGAM_LUT_RW_CONTROL)/sizeof(mmCM2_CM_IGAM_LUT_RW_CONTROL[0]), 0, 0 }, + { "mmCM2_CM_IGAM_LUT_RW_INDEX", REG_MMIO, 0x0ed7, 2, &mmCM2_CM_IGAM_LUT_RW_INDEX[0], sizeof(mmCM2_CM_IGAM_LUT_RW_INDEX)/sizeof(mmCM2_CM_IGAM_LUT_RW_INDEX[0]), 0, 0 }, + { "mmCM2_CM_IGAM_LUT_SEQ_COLOR", REG_MMIO, 0x0ed8, 2, &mmCM2_CM_IGAM_LUT_SEQ_COLOR[0], sizeof(mmCM2_CM_IGAM_LUT_SEQ_COLOR)/sizeof(mmCM2_CM_IGAM_LUT_SEQ_COLOR[0]), 0, 0 }, + { "mmCM2_CM_IGAM_LUT_30_COLOR", REG_MMIO, 0x0ed9, 2, &mmCM2_CM_IGAM_LUT_30_COLOR[0], sizeof(mmCM2_CM_IGAM_LUT_30_COLOR)/sizeof(mmCM2_CM_IGAM_LUT_30_COLOR[0]), 0, 0 }, + { "mmCM2_CM_IGAM_LUT_PWL_DATA", REG_MMIO, 0x0eda, 2, &mmCM2_CM_IGAM_LUT_PWL_DATA[0], sizeof(mmCM2_CM_IGAM_LUT_PWL_DATA)/sizeof(mmCM2_CM_IGAM_LUT_PWL_DATA[0]), 0, 0 }, + { "mmCM2_CM_IGAM_LUT_AUTOFILL", REG_MMIO, 0x0edb, 2, &mmCM2_CM_IGAM_LUT_AUTOFILL[0], sizeof(mmCM2_CM_IGAM_LUT_AUTOFILL)/sizeof(mmCM2_CM_IGAM_LUT_AUTOFILL[0]), 0, 0 }, + { "mmCM2_CM_IGAM_LUT_BW_OFFSET_BLUE", REG_MMIO, 0x0edc, 2, &mmCM2_CM_IGAM_LUT_BW_OFFSET_BLUE[0], sizeof(mmCM2_CM_IGAM_LUT_BW_OFFSET_BLUE)/sizeof(mmCM2_CM_IGAM_LUT_BW_OFFSET_BLUE[0]), 0, 0 }, + { "mmCM2_CM_IGAM_LUT_BW_OFFSET_GREEN", REG_MMIO, 0x0edd, 2, &mmCM2_CM_IGAM_LUT_BW_OFFSET_GREEN[0], sizeof(mmCM2_CM_IGAM_LUT_BW_OFFSET_GREEN)/sizeof(mmCM2_CM_IGAM_LUT_BW_OFFSET_GREEN[0]), 0, 0 }, + { "mmCM2_CM_IGAM_LUT_BW_OFFSET_RED", REG_MMIO, 0x0ede, 2, &mmCM2_CM_IGAM_LUT_BW_OFFSET_RED[0], sizeof(mmCM2_CM_IGAM_LUT_BW_OFFSET_RED)/sizeof(mmCM2_CM_IGAM_LUT_BW_OFFSET_RED[0]), 0, 0 }, + { "mmCM2_CM_ICSC_CONTROL", REG_MMIO, 0x0edf, 2, &mmCM2_CM_ICSC_CONTROL[0], sizeof(mmCM2_CM_ICSC_CONTROL)/sizeof(mmCM2_CM_ICSC_CONTROL[0]), 0, 0 }, + { "mmCM2_CM_ICSC_C11_C12", REG_MMIO, 0x0ee0, 2, &mmCM2_CM_ICSC_C11_C12[0], sizeof(mmCM2_CM_ICSC_C11_C12)/sizeof(mmCM2_CM_ICSC_C11_C12[0]), 0, 0 }, + { "mmCM2_CM_ICSC_C13_C14", REG_MMIO, 0x0ee1, 2, &mmCM2_CM_ICSC_C13_C14[0], sizeof(mmCM2_CM_ICSC_C13_C14)/sizeof(mmCM2_CM_ICSC_C13_C14[0]), 0, 0 }, + { "mmCM2_CM_ICSC_C21_C22", REG_MMIO, 0x0ee2, 2, &mmCM2_CM_ICSC_C21_C22[0], sizeof(mmCM2_CM_ICSC_C21_C22)/sizeof(mmCM2_CM_ICSC_C21_C22[0]), 0, 0 }, + { "mmCM2_CM_ICSC_C23_C24", REG_MMIO, 0x0ee3, 2, &mmCM2_CM_ICSC_C23_C24[0], sizeof(mmCM2_CM_ICSC_C23_C24)/sizeof(mmCM2_CM_ICSC_C23_C24[0]), 0, 0 }, + { "mmCM2_CM_ICSC_C31_C32", REG_MMIO, 0x0ee4, 2, &mmCM2_CM_ICSC_C31_C32[0], sizeof(mmCM2_CM_ICSC_C31_C32)/sizeof(mmCM2_CM_ICSC_C31_C32[0]), 0, 0 }, + { "mmCM2_CM_ICSC_C33_C34", REG_MMIO, 0x0ee5, 2, &mmCM2_CM_ICSC_C33_C34[0], sizeof(mmCM2_CM_ICSC_C33_C34)/sizeof(mmCM2_CM_ICSC_C33_C34[0]), 0, 0 }, + { "mmCM2_CM_GAMUT_REMAP_CONTROL", REG_MMIO, 0x0ee6, 2, &mmCM2_CM_GAMUT_REMAP_CONTROL[0], sizeof(mmCM2_CM_GAMUT_REMAP_CONTROL)/sizeof(mmCM2_CM_GAMUT_REMAP_CONTROL[0]), 0, 0 }, + { "mmCM2_CM_GAMUT_REMAP_C11_C12", REG_MMIO, 0x0ee7, 2, &mmCM2_CM_GAMUT_REMAP_C11_C12[0], sizeof(mmCM2_CM_GAMUT_REMAP_C11_C12)/sizeof(mmCM2_CM_GAMUT_REMAP_C11_C12[0]), 0, 0 }, + { "mmCM2_CM_GAMUT_REMAP_C13_C14", REG_MMIO, 0x0ee8, 2, &mmCM2_CM_GAMUT_REMAP_C13_C14[0], sizeof(mmCM2_CM_GAMUT_REMAP_C13_C14)/sizeof(mmCM2_CM_GAMUT_REMAP_C13_C14[0]), 0, 0 }, + { "mmCM2_CM_GAMUT_REMAP_C21_C22", REG_MMIO, 0x0ee9, 2, &mmCM2_CM_GAMUT_REMAP_C21_C22[0], sizeof(mmCM2_CM_GAMUT_REMAP_C21_C22)/sizeof(mmCM2_CM_GAMUT_REMAP_C21_C22[0]), 0, 0 }, + { "mmCM2_CM_GAMUT_REMAP_C23_C24", REG_MMIO, 0x0eea, 2, &mmCM2_CM_GAMUT_REMAP_C23_C24[0], sizeof(mmCM2_CM_GAMUT_REMAP_C23_C24)/sizeof(mmCM2_CM_GAMUT_REMAP_C23_C24[0]), 0, 0 }, + { "mmCM2_CM_GAMUT_REMAP_C31_C32", REG_MMIO, 0x0eeb, 2, &mmCM2_CM_GAMUT_REMAP_C31_C32[0], sizeof(mmCM2_CM_GAMUT_REMAP_C31_C32)/sizeof(mmCM2_CM_GAMUT_REMAP_C31_C32[0]), 0, 0 }, + { "mmCM2_CM_GAMUT_REMAP_C33_C34", REG_MMIO, 0x0eec, 2, &mmCM2_CM_GAMUT_REMAP_C33_C34[0], sizeof(mmCM2_CM_GAMUT_REMAP_C33_C34)/sizeof(mmCM2_CM_GAMUT_REMAP_C33_C34[0]), 0, 0 }, + { "mmCM2_CM_OCSC_CONTROL", REG_MMIO, 0x0eed, 2, &mmCM2_CM_OCSC_CONTROL[0], sizeof(mmCM2_CM_OCSC_CONTROL)/sizeof(mmCM2_CM_OCSC_CONTROL[0]), 0, 0 }, + { "mmCM2_CM_OCSC_C11_C12", REG_MMIO, 0x0eee, 2, &mmCM2_CM_OCSC_C11_C12[0], sizeof(mmCM2_CM_OCSC_C11_C12)/sizeof(mmCM2_CM_OCSC_C11_C12[0]), 0, 0 }, + { "mmCM2_CM_OCSC_C13_C14", REG_MMIO, 0x0eef, 2, &mmCM2_CM_OCSC_C13_C14[0], sizeof(mmCM2_CM_OCSC_C13_C14)/sizeof(mmCM2_CM_OCSC_C13_C14[0]), 0, 0 }, + { "mmCM2_CM_OCSC_C21_C22", REG_MMIO, 0x0ef0, 2, &mmCM2_CM_OCSC_C21_C22[0], sizeof(mmCM2_CM_OCSC_C21_C22)/sizeof(mmCM2_CM_OCSC_C21_C22[0]), 0, 0 }, + { "mmCM2_CM_OCSC_C23_C24", REG_MMIO, 0x0ef1, 2, &mmCM2_CM_OCSC_C23_C24[0], sizeof(mmCM2_CM_OCSC_C23_C24)/sizeof(mmCM2_CM_OCSC_C23_C24[0]), 0, 0 }, + { "mmCM2_CM_OCSC_C31_C32", REG_MMIO, 0x0ef2, 2, &mmCM2_CM_OCSC_C31_C32[0], sizeof(mmCM2_CM_OCSC_C31_C32)/sizeof(mmCM2_CM_OCSC_C31_C32[0]), 0, 0 }, + { "mmCM2_CM_OCSC_C33_C34", REG_MMIO, 0x0ef3, 2, &mmCM2_CM_OCSC_C33_C34[0], sizeof(mmCM2_CM_OCSC_C33_C34)/sizeof(mmCM2_CM_OCSC_C33_C34[0]), 0, 0 }, + { "mmCM2_CM_BNS_VALUES_R", REG_MMIO, 0x0ef4, 2, &mmCM2_CM_BNS_VALUES_R[0], sizeof(mmCM2_CM_BNS_VALUES_R)/sizeof(mmCM2_CM_BNS_VALUES_R[0]), 0, 0 }, + { "mmCM2_CM_BNS_VALUES_G", REG_MMIO, 0x0ef5, 2, &mmCM2_CM_BNS_VALUES_G[0], sizeof(mmCM2_CM_BNS_VALUES_G)/sizeof(mmCM2_CM_BNS_VALUES_G[0]), 0, 0 }, + { "mmCM2_CM_BNS_VALUES_B", REG_MMIO, 0x0ef6, 2, &mmCM2_CM_BNS_VALUES_B[0], sizeof(mmCM2_CM_BNS_VALUES_B)/sizeof(mmCM2_CM_BNS_VALUES_B[0]), 0, 0 }, + { "mmCM2_CM_DGAM_CONTROL", REG_MMIO, 0x0ef7, 2, &mmCM2_CM_DGAM_CONTROL[0], sizeof(mmCM2_CM_DGAM_CONTROL)/sizeof(mmCM2_CM_DGAM_CONTROL[0]), 0, 0 }, + { "mmCM2_CM_DGAM_LUT_INDEX", REG_MMIO, 0x0ef8, 2, &mmCM2_CM_DGAM_LUT_INDEX[0], sizeof(mmCM2_CM_DGAM_LUT_INDEX)/sizeof(mmCM2_CM_DGAM_LUT_INDEX[0]), 0, 0 }, + { "mmCM2_CM_DGAM_LUT_DATA", REG_MMIO, 0x0ef9, 2, &mmCM2_CM_DGAM_LUT_DATA[0], sizeof(mmCM2_CM_DGAM_LUT_DATA)/sizeof(mmCM2_CM_DGAM_LUT_DATA[0]), 0, 0 }, + { "mmCM2_CM_DGAM_LUT_WRITE_EN_MASK", REG_MMIO, 0x0efa, 2, &mmCM2_CM_DGAM_LUT_WRITE_EN_MASK[0], sizeof(mmCM2_CM_DGAM_LUT_WRITE_EN_MASK)/sizeof(mmCM2_CM_DGAM_LUT_WRITE_EN_MASK[0]), 0, 0 }, + { "mmCM2_CM_DGAM_RAMA_START_CNTL_B", REG_MMIO, 0x0efb, 2, &mmCM2_CM_DGAM_RAMA_START_CNTL_B[0], sizeof(mmCM2_CM_DGAM_RAMA_START_CNTL_B)/sizeof(mmCM2_CM_DGAM_RAMA_START_CNTL_B[0]), 0, 0 }, + { "mmCM2_CM_DGAM_RAMA_START_CNTL_G", REG_MMIO, 0x0efc, 2, &mmCM2_CM_DGAM_RAMA_START_CNTL_G[0], sizeof(mmCM2_CM_DGAM_RAMA_START_CNTL_G)/sizeof(mmCM2_CM_DGAM_RAMA_START_CNTL_G[0]), 0, 0 }, + { "mmCM2_CM_DGAM_RAMA_START_CNTL_R", REG_MMIO, 0x0efd, 2, &mmCM2_CM_DGAM_RAMA_START_CNTL_R[0], sizeof(mmCM2_CM_DGAM_RAMA_START_CNTL_R)/sizeof(mmCM2_CM_DGAM_RAMA_START_CNTL_R[0]), 0, 0 }, + { "mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_B", REG_MMIO, 0x0efe, 2, &mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_B[0], sizeof(mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_B)/sizeof(mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_B[0]), 0, 0 }, + { "mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_G", REG_MMIO, 0x0eff, 2, &mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_G[0], sizeof(mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_G)/sizeof(mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_G[0]), 0, 0 }, + { "mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_R", REG_MMIO, 0x0f00, 2, &mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_R[0], sizeof(mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_R)/sizeof(mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_R[0]), 0, 0 }, + { "mmCM2_CM_DGAM_RAMA_END_CNTL1_B", REG_MMIO, 0x0f01, 2, &mmCM2_CM_DGAM_RAMA_END_CNTL1_B[0], sizeof(mmCM2_CM_DGAM_RAMA_END_CNTL1_B)/sizeof(mmCM2_CM_DGAM_RAMA_END_CNTL1_B[0]), 0, 0 }, + { "mmCM2_CM_DGAM_RAMA_END_CNTL2_B", REG_MMIO, 0x0f02, 2, &mmCM2_CM_DGAM_RAMA_END_CNTL2_B[0], sizeof(mmCM2_CM_DGAM_RAMA_END_CNTL2_B)/sizeof(mmCM2_CM_DGAM_RAMA_END_CNTL2_B[0]), 0, 0 }, + { "mmCM2_CM_DGAM_RAMA_END_CNTL1_G", REG_MMIO, 0x0f03, 2, &mmCM2_CM_DGAM_RAMA_END_CNTL1_G[0], sizeof(mmCM2_CM_DGAM_RAMA_END_CNTL1_G)/sizeof(mmCM2_CM_DGAM_RAMA_END_CNTL1_G[0]), 0, 0 }, + { "mmCM2_CM_DGAM_RAMA_END_CNTL2_G", REG_MMIO, 0x0f04, 2, &mmCM2_CM_DGAM_RAMA_END_CNTL2_G[0], sizeof(mmCM2_CM_DGAM_RAMA_END_CNTL2_G)/sizeof(mmCM2_CM_DGAM_RAMA_END_CNTL2_G[0]), 0, 0 }, + { "mmCM2_CM_DGAM_RAMA_END_CNTL1_R", REG_MMIO, 0x0f05, 2, &mmCM2_CM_DGAM_RAMA_END_CNTL1_R[0], sizeof(mmCM2_CM_DGAM_RAMA_END_CNTL1_R)/sizeof(mmCM2_CM_DGAM_RAMA_END_CNTL1_R[0]), 0, 0 }, + { "mmCM2_CM_DGAM_RAMA_END_CNTL2_R", REG_MMIO, 0x0f06, 2, &mmCM2_CM_DGAM_RAMA_END_CNTL2_R[0], sizeof(mmCM2_CM_DGAM_RAMA_END_CNTL2_R)/sizeof(mmCM2_CM_DGAM_RAMA_END_CNTL2_R[0]), 0, 0 }, + { "mmCM2_CM_DGAM_RAMA_REGION_0_1", REG_MMIO, 0x0f07, 2, &mmCM2_CM_DGAM_RAMA_REGION_0_1[0], sizeof(mmCM2_CM_DGAM_RAMA_REGION_0_1)/sizeof(mmCM2_CM_DGAM_RAMA_REGION_0_1[0]), 0, 0 }, + { "mmCM2_CM_DGAM_RAMA_REGION_2_3", REG_MMIO, 0x0f08, 2, &mmCM2_CM_DGAM_RAMA_REGION_2_3[0], sizeof(mmCM2_CM_DGAM_RAMA_REGION_2_3)/sizeof(mmCM2_CM_DGAM_RAMA_REGION_2_3[0]), 0, 0 }, + { "mmCM2_CM_DGAM_RAMA_REGION_4_5", REG_MMIO, 0x0f09, 2, &mmCM2_CM_DGAM_RAMA_REGION_4_5[0], sizeof(mmCM2_CM_DGAM_RAMA_REGION_4_5)/sizeof(mmCM2_CM_DGAM_RAMA_REGION_4_5[0]), 0, 0 }, + { "mmCM2_CM_DGAM_RAMA_REGION_6_7", REG_MMIO, 0x0f0a, 2, &mmCM2_CM_DGAM_RAMA_REGION_6_7[0], sizeof(mmCM2_CM_DGAM_RAMA_REGION_6_7)/sizeof(mmCM2_CM_DGAM_RAMA_REGION_6_7[0]), 0, 0 }, + { "mmCM2_CM_DGAM_RAMA_REGION_8_9", REG_MMIO, 0x0f0b, 2, &mmCM2_CM_DGAM_RAMA_REGION_8_9[0], sizeof(mmCM2_CM_DGAM_RAMA_REGION_8_9)/sizeof(mmCM2_CM_DGAM_RAMA_REGION_8_9[0]), 0, 0 }, + { "mmCM2_CM_DGAM_RAMA_REGION_10_11", REG_MMIO, 0x0f0c, 2, &mmCM2_CM_DGAM_RAMA_REGION_10_11[0], sizeof(mmCM2_CM_DGAM_RAMA_REGION_10_11)/sizeof(mmCM2_CM_DGAM_RAMA_REGION_10_11[0]), 0, 0 }, + { "mmCM2_CM_DGAM_RAMA_REGION_12_13", REG_MMIO, 0x0f0d, 2, &mmCM2_CM_DGAM_RAMA_REGION_12_13[0], sizeof(mmCM2_CM_DGAM_RAMA_REGION_12_13)/sizeof(mmCM2_CM_DGAM_RAMA_REGION_12_13[0]), 0, 0 }, + { "mmCM2_CM_DGAM_RAMA_REGION_14_15", REG_MMIO, 0x0f0e, 2, &mmCM2_CM_DGAM_RAMA_REGION_14_15[0], sizeof(mmCM2_CM_DGAM_RAMA_REGION_14_15)/sizeof(mmCM2_CM_DGAM_RAMA_REGION_14_15[0]), 0, 0 }, + { "mmCM2_CM_DGAM_RAMB_START_CNTL_B", REG_MMIO, 0x0f0f, 2, &mmCM2_CM_DGAM_RAMB_START_CNTL_B[0], sizeof(mmCM2_CM_DGAM_RAMB_START_CNTL_B)/sizeof(mmCM2_CM_DGAM_RAMB_START_CNTL_B[0]), 0, 0 }, + { "mmCM2_CM_DGAM_RAMB_START_CNTL_G", REG_MMIO, 0x0f10, 2, &mmCM2_CM_DGAM_RAMB_START_CNTL_G[0], sizeof(mmCM2_CM_DGAM_RAMB_START_CNTL_G)/sizeof(mmCM2_CM_DGAM_RAMB_START_CNTL_G[0]), 0, 0 }, + { "mmCM2_CM_DGAM_RAMB_START_CNTL_R", REG_MMIO, 0x0f11, 2, &mmCM2_CM_DGAM_RAMB_START_CNTL_R[0], sizeof(mmCM2_CM_DGAM_RAMB_START_CNTL_R)/sizeof(mmCM2_CM_DGAM_RAMB_START_CNTL_R[0]), 0, 0 }, + { "mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_B", REG_MMIO, 0x0f12, 2, &mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_B[0], sizeof(mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_B)/sizeof(mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_B[0]), 0, 0 }, + { "mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_G", REG_MMIO, 0x0f13, 2, &mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_G[0], sizeof(mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_G)/sizeof(mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_G[0]), 0, 0 }, + { "mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_R", REG_MMIO, 0x0f14, 2, &mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_R[0], sizeof(mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_R)/sizeof(mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_R[0]), 0, 0 }, + { "mmCM2_CM_DGAM_RAMB_END_CNTL1_B", REG_MMIO, 0x0f15, 2, &mmCM2_CM_DGAM_RAMB_END_CNTL1_B[0], sizeof(mmCM2_CM_DGAM_RAMB_END_CNTL1_B)/sizeof(mmCM2_CM_DGAM_RAMB_END_CNTL1_B[0]), 0, 0 }, + { "mmCM2_CM_DGAM_RAMB_END_CNTL2_B", REG_MMIO, 0x0f16, 2, &mmCM2_CM_DGAM_RAMB_END_CNTL2_B[0], sizeof(mmCM2_CM_DGAM_RAMB_END_CNTL2_B)/sizeof(mmCM2_CM_DGAM_RAMB_END_CNTL2_B[0]), 0, 0 }, + { "mmCM2_CM_DGAM_RAMB_END_CNTL1_G", REG_MMIO, 0x0f17, 2, &mmCM2_CM_DGAM_RAMB_END_CNTL1_G[0], sizeof(mmCM2_CM_DGAM_RAMB_END_CNTL1_G)/sizeof(mmCM2_CM_DGAM_RAMB_END_CNTL1_G[0]), 0, 0 }, + { "mmCM2_CM_DGAM_RAMB_END_CNTL2_G", REG_MMIO, 0x0f18, 2, &mmCM2_CM_DGAM_RAMB_END_CNTL2_G[0], sizeof(mmCM2_CM_DGAM_RAMB_END_CNTL2_G)/sizeof(mmCM2_CM_DGAM_RAMB_END_CNTL2_G[0]), 0, 0 }, + { "mmCM2_CM_DGAM_RAMB_END_CNTL1_R", REG_MMIO, 0x0f19, 2, &mmCM2_CM_DGAM_RAMB_END_CNTL1_R[0], sizeof(mmCM2_CM_DGAM_RAMB_END_CNTL1_R)/sizeof(mmCM2_CM_DGAM_RAMB_END_CNTL1_R[0]), 0, 0 }, + { "mmCM2_CM_DGAM_RAMB_END_CNTL2_R", REG_MMIO, 0x0f1a, 2, &mmCM2_CM_DGAM_RAMB_END_CNTL2_R[0], sizeof(mmCM2_CM_DGAM_RAMB_END_CNTL2_R)/sizeof(mmCM2_CM_DGAM_RAMB_END_CNTL2_R[0]), 0, 0 }, + { "mmCM2_CM_DGAM_RAMB_REGION_0_1", REG_MMIO, 0x0f1b, 2, &mmCM2_CM_DGAM_RAMB_REGION_0_1[0], sizeof(mmCM2_CM_DGAM_RAMB_REGION_0_1)/sizeof(mmCM2_CM_DGAM_RAMB_REGION_0_1[0]), 0, 0 }, + { "mmCM2_CM_DGAM_RAMB_REGION_2_3", REG_MMIO, 0x0f1c, 2, &mmCM2_CM_DGAM_RAMB_REGION_2_3[0], sizeof(mmCM2_CM_DGAM_RAMB_REGION_2_3)/sizeof(mmCM2_CM_DGAM_RAMB_REGION_2_3[0]), 0, 0 }, + { "mmCM2_CM_DGAM_RAMB_REGION_4_5", REG_MMIO, 0x0f1d, 2, &mmCM2_CM_DGAM_RAMB_REGION_4_5[0], sizeof(mmCM2_CM_DGAM_RAMB_REGION_4_5)/sizeof(mmCM2_CM_DGAM_RAMB_REGION_4_5[0]), 0, 0 }, + { "mmCM2_CM_DGAM_RAMB_REGION_6_7", REG_MMIO, 0x0f1e, 2, &mmCM2_CM_DGAM_RAMB_REGION_6_7[0], sizeof(mmCM2_CM_DGAM_RAMB_REGION_6_7)/sizeof(mmCM2_CM_DGAM_RAMB_REGION_6_7[0]), 0, 0 }, + { "mmCM2_CM_DGAM_RAMB_REGION_8_9", REG_MMIO, 0x0f1f, 2, &mmCM2_CM_DGAM_RAMB_REGION_8_9[0], sizeof(mmCM2_CM_DGAM_RAMB_REGION_8_9)/sizeof(mmCM2_CM_DGAM_RAMB_REGION_8_9[0]), 0, 0 }, + { "mmCM2_CM_DGAM_RAMB_REGION_10_11", REG_MMIO, 0x0f20, 2, &mmCM2_CM_DGAM_RAMB_REGION_10_11[0], sizeof(mmCM2_CM_DGAM_RAMB_REGION_10_11)/sizeof(mmCM2_CM_DGAM_RAMB_REGION_10_11[0]), 0, 0 }, + { "mmCM2_CM_DGAM_RAMB_REGION_12_13", REG_MMIO, 0x0f21, 2, &mmCM2_CM_DGAM_RAMB_REGION_12_13[0], sizeof(mmCM2_CM_DGAM_RAMB_REGION_12_13)/sizeof(mmCM2_CM_DGAM_RAMB_REGION_12_13[0]), 0, 0 }, + { "mmCM2_CM_DGAM_RAMB_REGION_14_15", REG_MMIO, 0x0f22, 2, &mmCM2_CM_DGAM_RAMB_REGION_14_15[0], sizeof(mmCM2_CM_DGAM_RAMB_REGION_14_15)/sizeof(mmCM2_CM_DGAM_RAMB_REGION_14_15[0]), 0, 0 }, + { "mmCM2_CM_RGAM_CONTROL", REG_MMIO, 0x0f23, 2, &mmCM2_CM_RGAM_CONTROL[0], sizeof(mmCM2_CM_RGAM_CONTROL)/sizeof(mmCM2_CM_RGAM_CONTROL[0]), 0, 0 }, + { "mmCM2_CM_RGAM_LUT_INDEX", REG_MMIO, 0x0f24, 2, &mmCM2_CM_RGAM_LUT_INDEX[0], sizeof(mmCM2_CM_RGAM_LUT_INDEX)/sizeof(mmCM2_CM_RGAM_LUT_INDEX[0]), 0, 0 }, + { "mmCM2_CM_RGAM_LUT_DATA", REG_MMIO, 0x0f25, 2, &mmCM2_CM_RGAM_LUT_DATA[0], sizeof(mmCM2_CM_RGAM_LUT_DATA)/sizeof(mmCM2_CM_RGAM_LUT_DATA[0]), 0, 0 }, + { "mmCM2_CM_RGAM_LUT_WRITE_EN_MASK", REG_MMIO, 0x0f26, 2, &mmCM2_CM_RGAM_LUT_WRITE_EN_MASK[0], sizeof(mmCM2_CM_RGAM_LUT_WRITE_EN_MASK)/sizeof(mmCM2_CM_RGAM_LUT_WRITE_EN_MASK[0]), 0, 0 }, + { "mmCM2_CM_RGAM_RAMA_START_CNTL_B", REG_MMIO, 0x0f27, 2, &mmCM2_CM_RGAM_RAMA_START_CNTL_B[0], sizeof(mmCM2_CM_RGAM_RAMA_START_CNTL_B)/sizeof(mmCM2_CM_RGAM_RAMA_START_CNTL_B[0]), 0, 0 }, + { "mmCM2_CM_RGAM_RAMA_START_CNTL_G", REG_MMIO, 0x0f28, 2, &mmCM2_CM_RGAM_RAMA_START_CNTL_G[0], sizeof(mmCM2_CM_RGAM_RAMA_START_CNTL_G)/sizeof(mmCM2_CM_RGAM_RAMA_START_CNTL_G[0]), 0, 0 }, + { "mmCM2_CM_RGAM_RAMA_START_CNTL_R", REG_MMIO, 0x0f29, 2, &mmCM2_CM_RGAM_RAMA_START_CNTL_R[0], sizeof(mmCM2_CM_RGAM_RAMA_START_CNTL_R)/sizeof(mmCM2_CM_RGAM_RAMA_START_CNTL_R[0]), 0, 0 }, + { "mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_B", REG_MMIO, 0x0f2a, 2, &mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_B[0], sizeof(mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_B)/sizeof(mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_B[0]), 0, 0 }, + { "mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_G", REG_MMIO, 0x0f2b, 2, &mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_G[0], sizeof(mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_G)/sizeof(mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_G[0]), 0, 0 }, + { "mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_R", REG_MMIO, 0x0f2c, 2, &mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_R[0], sizeof(mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_R)/sizeof(mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_R[0]), 0, 0 }, + { "mmCM2_CM_RGAM_RAMA_END_CNTL1_B", REG_MMIO, 0x0f2d, 2, &mmCM2_CM_RGAM_RAMA_END_CNTL1_B[0], sizeof(mmCM2_CM_RGAM_RAMA_END_CNTL1_B)/sizeof(mmCM2_CM_RGAM_RAMA_END_CNTL1_B[0]), 0, 0 }, + { "mmCM2_CM_RGAM_RAMA_END_CNTL2_B", REG_MMIO, 0x0f2e, 2, &mmCM2_CM_RGAM_RAMA_END_CNTL2_B[0], sizeof(mmCM2_CM_RGAM_RAMA_END_CNTL2_B)/sizeof(mmCM2_CM_RGAM_RAMA_END_CNTL2_B[0]), 0, 0 }, + { "mmCM2_CM_RGAM_RAMA_END_CNTL1_G", REG_MMIO, 0x0f2f, 2, &mmCM2_CM_RGAM_RAMA_END_CNTL1_G[0], sizeof(mmCM2_CM_RGAM_RAMA_END_CNTL1_G)/sizeof(mmCM2_CM_RGAM_RAMA_END_CNTL1_G[0]), 0, 0 }, + { "mmCM2_CM_RGAM_RAMA_END_CNTL2_G", REG_MMIO, 0x0f30, 2, &mmCM2_CM_RGAM_RAMA_END_CNTL2_G[0], sizeof(mmCM2_CM_RGAM_RAMA_END_CNTL2_G)/sizeof(mmCM2_CM_RGAM_RAMA_END_CNTL2_G[0]), 0, 0 }, + { "mmCM2_CM_RGAM_RAMA_END_CNTL1_R", REG_MMIO, 0x0f31, 2, &mmCM2_CM_RGAM_RAMA_END_CNTL1_R[0], sizeof(mmCM2_CM_RGAM_RAMA_END_CNTL1_R)/sizeof(mmCM2_CM_RGAM_RAMA_END_CNTL1_R[0]), 0, 0 }, + { "mmCM2_CM_RGAM_RAMA_END_CNTL2_R", REG_MMIO, 0x0f32, 2, &mmCM2_CM_RGAM_RAMA_END_CNTL2_R[0], sizeof(mmCM2_CM_RGAM_RAMA_END_CNTL2_R)/sizeof(mmCM2_CM_RGAM_RAMA_END_CNTL2_R[0]), 0, 0 }, + { "mmCM2_CM_RGAM_RAMA_REGION_0_1", REG_MMIO, 0x0f33, 2, &mmCM2_CM_RGAM_RAMA_REGION_0_1[0], sizeof(mmCM2_CM_RGAM_RAMA_REGION_0_1)/sizeof(mmCM2_CM_RGAM_RAMA_REGION_0_1[0]), 0, 0 }, + { "mmCM2_CM_RGAM_RAMA_REGION_2_3", REG_MMIO, 0x0f34, 2, &mmCM2_CM_RGAM_RAMA_REGION_2_3[0], sizeof(mmCM2_CM_RGAM_RAMA_REGION_2_3)/sizeof(mmCM2_CM_RGAM_RAMA_REGION_2_3[0]), 0, 0 }, + { "mmCM2_CM_RGAM_RAMA_REGION_4_5", REG_MMIO, 0x0f35, 2, &mmCM2_CM_RGAM_RAMA_REGION_4_5[0], sizeof(mmCM2_CM_RGAM_RAMA_REGION_4_5)/sizeof(mmCM2_CM_RGAM_RAMA_REGION_4_5[0]), 0, 0 }, + { "mmCM2_CM_RGAM_RAMA_REGION_6_7", REG_MMIO, 0x0f36, 2, &mmCM2_CM_RGAM_RAMA_REGION_6_7[0], sizeof(mmCM2_CM_RGAM_RAMA_REGION_6_7)/sizeof(mmCM2_CM_RGAM_RAMA_REGION_6_7[0]), 0, 0 }, + { "mmCM2_CM_RGAM_RAMA_REGION_8_9", REG_MMIO, 0x0f37, 2, &mmCM2_CM_RGAM_RAMA_REGION_8_9[0], sizeof(mmCM2_CM_RGAM_RAMA_REGION_8_9)/sizeof(mmCM2_CM_RGAM_RAMA_REGION_8_9[0]), 0, 0 }, + { "mmCM2_CM_RGAM_RAMA_REGION_10_11", REG_MMIO, 0x0f38, 2, &mmCM2_CM_RGAM_RAMA_REGION_10_11[0], sizeof(mmCM2_CM_RGAM_RAMA_REGION_10_11)/sizeof(mmCM2_CM_RGAM_RAMA_REGION_10_11[0]), 0, 0 }, + { "mmCM2_CM_RGAM_RAMA_REGION_12_13", REG_MMIO, 0x0f39, 2, &mmCM2_CM_RGAM_RAMA_REGION_12_13[0], sizeof(mmCM2_CM_RGAM_RAMA_REGION_12_13)/sizeof(mmCM2_CM_RGAM_RAMA_REGION_12_13[0]), 0, 0 }, + { "mmCM2_CM_RGAM_RAMA_REGION_14_15", REG_MMIO, 0x0f3a, 2, &mmCM2_CM_RGAM_RAMA_REGION_14_15[0], sizeof(mmCM2_CM_RGAM_RAMA_REGION_14_15)/sizeof(mmCM2_CM_RGAM_RAMA_REGION_14_15[0]), 0, 0 }, + { "mmCM2_CM_RGAM_RAMA_REGION_16_17", REG_MMIO, 0x0f3b, 2, &mmCM2_CM_RGAM_RAMA_REGION_16_17[0], sizeof(mmCM2_CM_RGAM_RAMA_REGION_16_17)/sizeof(mmCM2_CM_RGAM_RAMA_REGION_16_17[0]), 0, 0 }, + { "mmCM2_CM_RGAM_RAMA_REGION_18_19", REG_MMIO, 0x0f3c, 2, &mmCM2_CM_RGAM_RAMA_REGION_18_19[0], sizeof(mmCM2_CM_RGAM_RAMA_REGION_18_19)/sizeof(mmCM2_CM_RGAM_RAMA_REGION_18_19[0]), 0, 0 }, + { "mmCM2_CM_RGAM_RAMA_REGION_20_21", REG_MMIO, 0x0f3d, 2, &mmCM2_CM_RGAM_RAMA_REGION_20_21[0], sizeof(mmCM2_CM_RGAM_RAMA_REGION_20_21)/sizeof(mmCM2_CM_RGAM_RAMA_REGION_20_21[0]), 0, 0 }, + { "mmCM2_CM_RGAM_RAMA_REGION_22_23", REG_MMIO, 0x0f3e, 2, &mmCM2_CM_RGAM_RAMA_REGION_22_23[0], sizeof(mmCM2_CM_RGAM_RAMA_REGION_22_23)/sizeof(mmCM2_CM_RGAM_RAMA_REGION_22_23[0]), 0, 0 }, + { "mmCM2_CM_RGAM_RAMA_REGION_24_25", REG_MMIO, 0x0f3f, 2, &mmCM2_CM_RGAM_RAMA_REGION_24_25[0], sizeof(mmCM2_CM_RGAM_RAMA_REGION_24_25)/sizeof(mmCM2_CM_RGAM_RAMA_REGION_24_25[0]), 0, 0 }, + { "mmCM2_CM_RGAM_RAMA_REGION_26_27", REG_MMIO, 0x0f40, 2, &mmCM2_CM_RGAM_RAMA_REGION_26_27[0], sizeof(mmCM2_CM_RGAM_RAMA_REGION_26_27)/sizeof(mmCM2_CM_RGAM_RAMA_REGION_26_27[0]), 0, 0 }, + { "mmCM2_CM_RGAM_RAMA_REGION_28_29", REG_MMIO, 0x0f41, 2, &mmCM2_CM_RGAM_RAMA_REGION_28_29[0], sizeof(mmCM2_CM_RGAM_RAMA_REGION_28_29)/sizeof(mmCM2_CM_RGAM_RAMA_REGION_28_29[0]), 0, 0 }, + { "mmCM2_CM_RGAM_RAMA_REGION_30_31", REG_MMIO, 0x0f42, 2, &mmCM2_CM_RGAM_RAMA_REGION_30_31[0], sizeof(mmCM2_CM_RGAM_RAMA_REGION_30_31)/sizeof(mmCM2_CM_RGAM_RAMA_REGION_30_31[0]), 0, 0 }, + { "mmCM2_CM_RGAM_RAMA_REGION_32_33", REG_MMIO, 0x0f43, 2, &mmCM2_CM_RGAM_RAMA_REGION_32_33[0], sizeof(mmCM2_CM_RGAM_RAMA_REGION_32_33)/sizeof(mmCM2_CM_RGAM_RAMA_REGION_32_33[0]), 0, 0 }, + { "mmCM2_CM_RGAM_RAMB_START_CNTL_B", REG_MMIO, 0x0f44, 2, &mmCM2_CM_RGAM_RAMB_START_CNTL_B[0], sizeof(mmCM2_CM_RGAM_RAMB_START_CNTL_B)/sizeof(mmCM2_CM_RGAM_RAMB_START_CNTL_B[0]), 0, 0 }, + { "mmCM2_CM_RGAM_RAMB_START_CNTL_G", REG_MMIO, 0x0f45, 2, &mmCM2_CM_RGAM_RAMB_START_CNTL_G[0], sizeof(mmCM2_CM_RGAM_RAMB_START_CNTL_G)/sizeof(mmCM2_CM_RGAM_RAMB_START_CNTL_G[0]), 0, 0 }, + { "mmCM2_CM_RGAM_RAMB_START_CNTL_R", REG_MMIO, 0x0f46, 2, &mmCM2_CM_RGAM_RAMB_START_CNTL_R[0], sizeof(mmCM2_CM_RGAM_RAMB_START_CNTL_R)/sizeof(mmCM2_CM_RGAM_RAMB_START_CNTL_R[0]), 0, 0 }, + { "mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_B", REG_MMIO, 0x0f47, 2, &mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_B[0], sizeof(mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_B)/sizeof(mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_B[0]), 0, 0 }, + { "mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_G", REG_MMIO, 0x0f48, 2, &mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_G[0], sizeof(mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_G)/sizeof(mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_G[0]), 0, 0 }, + { "mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_R", REG_MMIO, 0x0f49, 2, &mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_R[0], sizeof(mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_R)/sizeof(mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_R[0]), 0, 0 }, + { "mmCM2_CM_RGAM_RAMB_END_CNTL1_B", REG_MMIO, 0x0f4a, 2, &mmCM2_CM_RGAM_RAMB_END_CNTL1_B[0], sizeof(mmCM2_CM_RGAM_RAMB_END_CNTL1_B)/sizeof(mmCM2_CM_RGAM_RAMB_END_CNTL1_B[0]), 0, 0 }, + { "mmCM2_CM_RGAM_RAMB_END_CNTL2_B", REG_MMIO, 0x0f4b, 2, &mmCM2_CM_RGAM_RAMB_END_CNTL2_B[0], sizeof(mmCM2_CM_RGAM_RAMB_END_CNTL2_B)/sizeof(mmCM2_CM_RGAM_RAMB_END_CNTL2_B[0]), 0, 0 }, + { "mmCM2_CM_RGAM_RAMB_END_CNTL1_G", REG_MMIO, 0x0f4c, 2, &mmCM2_CM_RGAM_RAMB_END_CNTL1_G[0], sizeof(mmCM2_CM_RGAM_RAMB_END_CNTL1_G)/sizeof(mmCM2_CM_RGAM_RAMB_END_CNTL1_G[0]), 0, 0 }, + { "mmCM2_CM_RGAM_RAMB_END_CNTL2_G", REG_MMIO, 0x0f4d, 2, &mmCM2_CM_RGAM_RAMB_END_CNTL2_G[0], sizeof(mmCM2_CM_RGAM_RAMB_END_CNTL2_G)/sizeof(mmCM2_CM_RGAM_RAMB_END_CNTL2_G[0]), 0, 0 }, + { "mmCM2_CM_RGAM_RAMB_END_CNTL1_R", REG_MMIO, 0x0f4e, 2, &mmCM2_CM_RGAM_RAMB_END_CNTL1_R[0], sizeof(mmCM2_CM_RGAM_RAMB_END_CNTL1_R)/sizeof(mmCM2_CM_RGAM_RAMB_END_CNTL1_R[0]), 0, 0 }, + { "mmCM2_CM_RGAM_RAMB_END_CNTL2_R", REG_MMIO, 0x0f4f, 2, &mmCM2_CM_RGAM_RAMB_END_CNTL2_R[0], sizeof(mmCM2_CM_RGAM_RAMB_END_CNTL2_R)/sizeof(mmCM2_CM_RGAM_RAMB_END_CNTL2_R[0]), 0, 0 }, + { "mmCM2_CM_RGAM_RAMB_REGION_0_1", REG_MMIO, 0x0f50, 2, &mmCM2_CM_RGAM_RAMB_REGION_0_1[0], sizeof(mmCM2_CM_RGAM_RAMB_REGION_0_1)/sizeof(mmCM2_CM_RGAM_RAMB_REGION_0_1[0]), 0, 0 }, + { "mmCM2_CM_RGAM_RAMB_REGION_2_3", REG_MMIO, 0x0f51, 2, &mmCM2_CM_RGAM_RAMB_REGION_2_3[0], sizeof(mmCM2_CM_RGAM_RAMB_REGION_2_3)/sizeof(mmCM2_CM_RGAM_RAMB_REGION_2_3[0]), 0, 0 }, + { "mmCM2_CM_RGAM_RAMB_REGION_4_5", REG_MMIO, 0x0f52, 2, &mmCM2_CM_RGAM_RAMB_REGION_4_5[0], sizeof(mmCM2_CM_RGAM_RAMB_REGION_4_5)/sizeof(mmCM2_CM_RGAM_RAMB_REGION_4_5[0]), 0, 0 }, + { "mmCM2_CM_RGAM_RAMB_REGION_6_7", REG_MMIO, 0x0f53, 2, &mmCM2_CM_RGAM_RAMB_REGION_6_7[0], sizeof(mmCM2_CM_RGAM_RAMB_REGION_6_7)/sizeof(mmCM2_CM_RGAM_RAMB_REGION_6_7[0]), 0, 0 }, + { "mmCM2_CM_RGAM_RAMB_REGION_8_9", REG_MMIO, 0x0f54, 2, &mmCM2_CM_RGAM_RAMB_REGION_8_9[0], sizeof(mmCM2_CM_RGAM_RAMB_REGION_8_9)/sizeof(mmCM2_CM_RGAM_RAMB_REGION_8_9[0]), 0, 0 }, + { "mmCM2_CM_RGAM_RAMB_REGION_10_11", REG_MMIO, 0x0f55, 2, &mmCM2_CM_RGAM_RAMB_REGION_10_11[0], sizeof(mmCM2_CM_RGAM_RAMB_REGION_10_11)/sizeof(mmCM2_CM_RGAM_RAMB_REGION_10_11[0]), 0, 0 }, + { "mmCM2_CM_RGAM_RAMB_REGION_12_13", REG_MMIO, 0x0f56, 2, &mmCM2_CM_RGAM_RAMB_REGION_12_13[0], sizeof(mmCM2_CM_RGAM_RAMB_REGION_12_13)/sizeof(mmCM2_CM_RGAM_RAMB_REGION_12_13[0]), 0, 0 }, + { "mmCM2_CM_RGAM_RAMB_REGION_14_15", REG_MMIO, 0x0f57, 2, &mmCM2_CM_RGAM_RAMB_REGION_14_15[0], sizeof(mmCM2_CM_RGAM_RAMB_REGION_14_15)/sizeof(mmCM2_CM_RGAM_RAMB_REGION_14_15[0]), 0, 0 }, + { "mmCM2_CM_RGAM_RAMB_REGION_16_17", REG_MMIO, 0x0f58, 2, &mmCM2_CM_RGAM_RAMB_REGION_16_17[0], sizeof(mmCM2_CM_RGAM_RAMB_REGION_16_17)/sizeof(mmCM2_CM_RGAM_RAMB_REGION_16_17[0]), 0, 0 }, + { "mmCM2_CM_RGAM_RAMB_REGION_18_19", REG_MMIO, 0x0f59, 2, &mmCM2_CM_RGAM_RAMB_REGION_18_19[0], sizeof(mmCM2_CM_RGAM_RAMB_REGION_18_19)/sizeof(mmCM2_CM_RGAM_RAMB_REGION_18_19[0]), 0, 0 }, + { "mmCM2_CM_RGAM_RAMB_REGION_20_21", REG_MMIO, 0x0f5a, 2, &mmCM2_CM_RGAM_RAMB_REGION_20_21[0], sizeof(mmCM2_CM_RGAM_RAMB_REGION_20_21)/sizeof(mmCM2_CM_RGAM_RAMB_REGION_20_21[0]), 0, 0 }, + { "mmCM2_CM_RGAM_RAMB_REGION_22_23", REG_MMIO, 0x0f5b, 2, &mmCM2_CM_RGAM_RAMB_REGION_22_23[0], sizeof(mmCM2_CM_RGAM_RAMB_REGION_22_23)/sizeof(mmCM2_CM_RGAM_RAMB_REGION_22_23[0]), 0, 0 }, + { "mmCM2_CM_RGAM_RAMB_REGION_24_25", REG_MMIO, 0x0f5c, 2, &mmCM2_CM_RGAM_RAMB_REGION_24_25[0], sizeof(mmCM2_CM_RGAM_RAMB_REGION_24_25)/sizeof(mmCM2_CM_RGAM_RAMB_REGION_24_25[0]), 0, 0 }, + { "mmCM2_CM_RGAM_RAMB_REGION_26_27", REG_MMIO, 0x0f5d, 2, &mmCM2_CM_RGAM_RAMB_REGION_26_27[0], sizeof(mmCM2_CM_RGAM_RAMB_REGION_26_27)/sizeof(mmCM2_CM_RGAM_RAMB_REGION_26_27[0]), 0, 0 }, + { "mmCM2_CM_RGAM_RAMB_REGION_28_29", REG_MMIO, 0x0f5e, 2, &mmCM2_CM_RGAM_RAMB_REGION_28_29[0], sizeof(mmCM2_CM_RGAM_RAMB_REGION_28_29)/sizeof(mmCM2_CM_RGAM_RAMB_REGION_28_29[0]), 0, 0 }, + { "mmCM2_CM_RGAM_RAMB_REGION_30_31", REG_MMIO, 0x0f5f, 2, &mmCM2_CM_RGAM_RAMB_REGION_30_31[0], sizeof(mmCM2_CM_RGAM_RAMB_REGION_30_31)/sizeof(mmCM2_CM_RGAM_RAMB_REGION_30_31[0]), 0, 0 }, + { "mmCM2_CM_RGAM_RAMB_REGION_32_33", REG_MMIO, 0x0f60, 2, &mmCM2_CM_RGAM_RAMB_REGION_32_33[0], sizeof(mmCM2_CM_RGAM_RAMB_REGION_32_33)/sizeof(mmCM2_CM_RGAM_RAMB_REGION_32_33[0]), 0, 0 }, + { "mmCM2_CM_HDR_MULT_COEF", REG_MMIO, 0x0f61, 2, &mmCM2_CM_HDR_MULT_COEF[0], sizeof(mmCM2_CM_HDR_MULT_COEF)/sizeof(mmCM2_CM_HDR_MULT_COEF[0]), 0, 0 }, + { "mmCM2_CM_RANGE_CLAMP_CONTROL_R", REG_MMIO, 0x0f62, 2, &mmCM2_CM_RANGE_CLAMP_CONTROL_R[0], sizeof(mmCM2_CM_RANGE_CLAMP_CONTROL_R)/sizeof(mmCM2_CM_RANGE_CLAMP_CONTROL_R[0]), 0, 0 }, + { "mmCM2_CM_RANGE_CLAMP_CONTROL_G", REG_MMIO, 0x0f63, 2, &mmCM2_CM_RANGE_CLAMP_CONTROL_G[0], sizeof(mmCM2_CM_RANGE_CLAMP_CONTROL_G)/sizeof(mmCM2_CM_RANGE_CLAMP_CONTROL_G[0]), 0, 0 }, + { "mmCM2_CM_RANGE_CLAMP_CONTROL_B", REG_MMIO, 0x0f64, 2, &mmCM2_CM_RANGE_CLAMP_CONTROL_B[0], sizeof(mmCM2_CM_RANGE_CLAMP_CONTROL_B)/sizeof(mmCM2_CM_RANGE_CLAMP_CONTROL_B[0]), 0, 0 }, + { "mmCM2_CM_DENORM_CONTROL", REG_MMIO, 0x0f65, 2, &mmCM2_CM_DENORM_CONTROL[0], sizeof(mmCM2_CM_DENORM_CONTROL)/sizeof(mmCM2_CM_DENORM_CONTROL[0]), 0, 0 }, + { "mmCM2_CM_CMOUT_CONTROL", REG_MMIO, 0x0f66, 2, &mmCM2_CM_CMOUT_CONTROL[0], sizeof(mmCM2_CM_CMOUT_CONTROL)/sizeof(mmCM2_CM_CMOUT_CONTROL[0]), 0, 0 }, + { "mmCM2_CM_CMOUT_RANDOM_SEEDS", REG_MMIO, 0x0f67, 2, &mmCM2_CM_CMOUT_RANDOM_SEEDS[0], sizeof(mmCM2_CM_CMOUT_RANDOM_SEEDS)/sizeof(mmCM2_CM_CMOUT_RANDOM_SEEDS[0]), 0, 0 }, + { "mmCM2_CM_MEM_PWR_CTRL", REG_MMIO, 0x0f68, 2, &mmCM2_CM_MEM_PWR_CTRL[0], sizeof(mmCM2_CM_MEM_PWR_CTRL)/sizeof(mmCM2_CM_MEM_PWR_CTRL[0]), 0, 0 }, + { "mmCM2_CM_MEM_PWR_STATUS", REG_MMIO, 0x0f69, 2, &mmCM2_CM_MEM_PWR_STATUS[0], sizeof(mmCM2_CM_MEM_PWR_STATUS)/sizeof(mmCM2_CM_MEM_PWR_STATUS[0]), 0, 0 }, + { "mmDC_PERFMON14_PERFCOUNTER_CNTL", REG_MMIO, 0x0f82, 2, &mmDC_PERFMON14_PERFCOUNTER_CNTL[0], sizeof(mmDC_PERFMON14_PERFCOUNTER_CNTL)/sizeof(mmDC_PERFMON14_PERFCOUNTER_CNTL[0]), 0, 0 }, + { "mmDC_PERFMON14_PERFCOUNTER_CNTL2", REG_MMIO, 0x0f83, 2, &mmDC_PERFMON14_PERFCOUNTER_CNTL2[0], sizeof(mmDC_PERFMON14_PERFCOUNTER_CNTL2)/sizeof(mmDC_PERFMON14_PERFCOUNTER_CNTL2[0]), 0, 0 }, + { "mmDC_PERFMON14_PERFCOUNTER_STATE", REG_MMIO, 0x0f84, 2, &mmDC_PERFMON14_PERFCOUNTER_STATE[0], sizeof(mmDC_PERFMON14_PERFCOUNTER_STATE)/sizeof(mmDC_PERFMON14_PERFCOUNTER_STATE[0]), 0, 0 }, + { "mmDC_PERFMON14_PERFMON_CNTL", REG_MMIO, 0x0f85, 2, &mmDC_PERFMON14_PERFMON_CNTL[0], sizeof(mmDC_PERFMON14_PERFMON_CNTL)/sizeof(mmDC_PERFMON14_PERFMON_CNTL[0]), 0, 0 }, + { "mmDC_PERFMON14_PERFMON_CNTL2", REG_MMIO, 0x0f86, 2, &mmDC_PERFMON14_PERFMON_CNTL2[0], sizeof(mmDC_PERFMON14_PERFMON_CNTL2)/sizeof(mmDC_PERFMON14_PERFMON_CNTL2[0]), 0, 0 }, + { "mmDC_PERFMON14_PERFMON_CVALUE_INT_MISC", REG_MMIO, 0x0f87, 2, &mmDC_PERFMON14_PERFMON_CVALUE_INT_MISC[0], sizeof(mmDC_PERFMON14_PERFMON_CVALUE_INT_MISC)/sizeof(mmDC_PERFMON14_PERFMON_CVALUE_INT_MISC[0]), 0, 0 }, + { "mmDC_PERFMON14_PERFMON_CVALUE_LOW", REG_MMIO, 0x0f88, 2, &mmDC_PERFMON14_PERFMON_CVALUE_LOW[0], sizeof(mmDC_PERFMON14_PERFMON_CVALUE_LOW)/sizeof(mmDC_PERFMON14_PERFMON_CVALUE_LOW[0]), 0, 0 }, + { "mmDC_PERFMON14_PERFMON_HI", REG_MMIO, 0x0f89, 2, &mmDC_PERFMON14_PERFMON_HI[0], sizeof(mmDC_PERFMON14_PERFMON_HI)/sizeof(mmDC_PERFMON14_PERFMON_HI[0]), 0, 0 }, + { "mmDC_PERFMON14_PERFMON_LOW", REG_MMIO, 0x0f8a, 2, &mmDC_PERFMON14_PERFMON_LOW[0], sizeof(mmDC_PERFMON14_PERFMON_LOW)/sizeof(mmDC_PERFMON14_PERFMON_LOW[0]), 0, 0 }, + { "mmDPP_TOP3_DPP_CONTROL", REG_MMIO, 0x0f8e, 2, &mmDPP_TOP3_DPP_CONTROL[0], sizeof(mmDPP_TOP3_DPP_CONTROL)/sizeof(mmDPP_TOP3_DPP_CONTROL[0]), 0, 0 }, + { "mmDPP_TOP3_DPP_SOFT_RESET", REG_MMIO, 0x0f8f, 2, &mmDPP_TOP3_DPP_SOFT_RESET[0], sizeof(mmDPP_TOP3_DPP_SOFT_RESET)/sizeof(mmDPP_TOP3_DPP_SOFT_RESET[0]), 0, 0 }, + { "mmDPP_TOP3_DPP_CRC_VAL_R_G", REG_MMIO, 0x0f90, 2, &mmDPP_TOP3_DPP_CRC_VAL_R_G[0], sizeof(mmDPP_TOP3_DPP_CRC_VAL_R_G)/sizeof(mmDPP_TOP3_DPP_CRC_VAL_R_G[0]), 0, 0 }, + { "mmDPP_TOP3_DPP_CRC_VAL_B_A", REG_MMIO, 0x0f91, 2, &mmDPP_TOP3_DPP_CRC_VAL_B_A[0], sizeof(mmDPP_TOP3_DPP_CRC_VAL_B_A)/sizeof(mmDPP_TOP3_DPP_CRC_VAL_B_A[0]), 0, 0 }, + { "mmDPP_TOP3_DPP_CRC_CTRL", REG_MMIO, 0x0f92, 2, &mmDPP_TOP3_DPP_CRC_CTRL[0], sizeof(mmDPP_TOP3_DPP_CRC_CTRL)/sizeof(mmDPP_TOP3_DPP_CRC_CTRL[0]), 0, 0 }, + { "mmDPP_TOP3_HOST_READ_CONTROL", REG_MMIO, 0x0f93, 2, &mmDPP_TOP3_HOST_READ_CONTROL[0], sizeof(mmDPP_TOP3_HOST_READ_CONTROL)/sizeof(mmDPP_TOP3_HOST_READ_CONTROL[0]), 0, 0 }, + { "mmCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT", REG_MMIO, 0x0f98, 2, &mmCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT[0], sizeof(mmCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT)/sizeof(mmCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT[0]), 0, 0 }, + { "mmCNVC_CFG3_FORMAT_CONTROL", REG_MMIO, 0x0f99, 2, &mmCNVC_CFG3_FORMAT_CONTROL[0], sizeof(mmCNVC_CFG3_FORMAT_CONTROL)/sizeof(mmCNVC_CFG3_FORMAT_CONTROL[0]), 0, 0 }, + { "mmCNVC_CFG3_FCNV_FP_SCALE_BIAS", REG_MMIO, 0x0f9a, 2, &mmCNVC_CFG3_FCNV_FP_SCALE_BIAS[0], sizeof(mmCNVC_CFG3_FCNV_FP_SCALE_BIAS)/sizeof(mmCNVC_CFG3_FCNV_FP_SCALE_BIAS[0]), 0, 0 }, + { "mmCNVC_CFG3_DENORM_CONTROL", REG_MMIO, 0x0f9b, 2, &mmCNVC_CFG3_DENORM_CONTROL[0], sizeof(mmCNVC_CFG3_DENORM_CONTROL)/sizeof(mmCNVC_CFG3_DENORM_CONTROL[0]), 0, 0 }, + { "mmCNVC_CFG3_COLOR_KEYER_CONTROL", REG_MMIO, 0x0f9d, 2, &mmCNVC_CFG3_COLOR_KEYER_CONTROL[0], sizeof(mmCNVC_CFG3_COLOR_KEYER_CONTROL)/sizeof(mmCNVC_CFG3_COLOR_KEYER_CONTROL[0]), 0, 0 }, + { "mmCNVC_CFG3_COLOR_KEYER_ALPHA", REG_MMIO, 0x0f9e, 2, &mmCNVC_CFG3_COLOR_KEYER_ALPHA[0], sizeof(mmCNVC_CFG3_COLOR_KEYER_ALPHA)/sizeof(mmCNVC_CFG3_COLOR_KEYER_ALPHA[0]), 0, 0 }, + { "mmCNVC_CFG3_COLOR_KEYER_RED", REG_MMIO, 0x0f9f, 2, &mmCNVC_CFG3_COLOR_KEYER_RED[0], sizeof(mmCNVC_CFG3_COLOR_KEYER_RED)/sizeof(mmCNVC_CFG3_COLOR_KEYER_RED[0]), 0, 0 }, + { "mmCNVC_CFG3_COLOR_KEYER_GREEN", REG_MMIO, 0x0fa0, 2, &mmCNVC_CFG3_COLOR_KEYER_GREEN[0], sizeof(mmCNVC_CFG3_COLOR_KEYER_GREEN)/sizeof(mmCNVC_CFG3_COLOR_KEYER_GREEN[0]), 0, 0 }, + { "mmCNVC_CFG3_COLOR_KEYER_BLUE", REG_MMIO, 0x0fa1, 2, &mmCNVC_CFG3_COLOR_KEYER_BLUE[0], sizeof(mmCNVC_CFG3_COLOR_KEYER_BLUE)/sizeof(mmCNVC_CFG3_COLOR_KEYER_BLUE[0]), 0, 0 }, + { "mmCNVC_CUR3_CURSOR0_CONTROL", REG_MMIO, 0x0fa9, 2, &mmCNVC_CUR3_CURSOR0_CONTROL[0], sizeof(mmCNVC_CUR3_CURSOR0_CONTROL)/sizeof(mmCNVC_CUR3_CURSOR0_CONTROL[0]), 0, 0 }, + { "mmCNVC_CUR3_CURSOR0_COLOR0", REG_MMIO, 0x0faa, 2, &mmCNVC_CUR3_CURSOR0_COLOR0[0], sizeof(mmCNVC_CUR3_CURSOR0_COLOR0)/sizeof(mmCNVC_CUR3_CURSOR0_COLOR0[0]), 0, 0 }, + { "mmCNVC_CUR3_CURSOR0_COLOR1", REG_MMIO, 0x0fab, 2, &mmCNVC_CUR3_CURSOR0_COLOR1[0], sizeof(mmCNVC_CUR3_CURSOR0_COLOR1)/sizeof(mmCNVC_CUR3_CURSOR0_COLOR1[0]), 0, 0 }, + { "mmCNVC_CUR3_CURSOR0_FP_SCALE_BIAS", REG_MMIO, 0x0fac, 2, &mmCNVC_CUR3_CURSOR0_FP_SCALE_BIAS[0], sizeof(mmCNVC_CUR3_CURSOR0_FP_SCALE_BIAS)/sizeof(mmCNVC_CUR3_CURSOR0_FP_SCALE_BIAS[0]), 0, 0 }, + { "mmDSCL3_SCL_COEF_RAM_TAP_SELECT", REG_MMIO, 0x0fb3, 2, &mmDSCL3_SCL_COEF_RAM_TAP_SELECT[0], sizeof(mmDSCL3_SCL_COEF_RAM_TAP_SELECT)/sizeof(mmDSCL3_SCL_COEF_RAM_TAP_SELECT[0]), 0, 0 }, + { "mmDSCL3_SCL_COEF_RAM_TAP_DATA", REG_MMIO, 0x0fb4, 2, &mmDSCL3_SCL_COEF_RAM_TAP_DATA[0], sizeof(mmDSCL3_SCL_COEF_RAM_TAP_DATA)/sizeof(mmDSCL3_SCL_COEF_RAM_TAP_DATA[0]), 0, 0 }, + { "mmDSCL3_SCL_MODE", REG_MMIO, 0x0fb5, 2, &mmDSCL3_SCL_MODE[0], sizeof(mmDSCL3_SCL_MODE)/sizeof(mmDSCL3_SCL_MODE[0]), 0, 0 }, + { "mmDSCL3_SCL_TAP_CONTROL", REG_MMIO, 0x0fb6, 2, &mmDSCL3_SCL_TAP_CONTROL[0], sizeof(mmDSCL3_SCL_TAP_CONTROL)/sizeof(mmDSCL3_SCL_TAP_CONTROL[0]), 0, 0 }, + { "mmDSCL3_DSCL_CONTROL", REG_MMIO, 0x0fb7, 2, &mmDSCL3_DSCL_CONTROL[0], sizeof(mmDSCL3_DSCL_CONTROL)/sizeof(mmDSCL3_DSCL_CONTROL[0]), 0, 0 }, + { "mmDSCL3_DSCL_2TAP_CONTROL", REG_MMIO, 0x0fb8, 2, &mmDSCL3_DSCL_2TAP_CONTROL[0], sizeof(mmDSCL3_DSCL_2TAP_CONTROL)/sizeof(mmDSCL3_DSCL_2TAP_CONTROL[0]), 0, 0 }, + { "mmDSCL3_SCL_MANUAL_REPLICATE_CONTROL", REG_MMIO, 0x0fb9, 2, &mmDSCL3_SCL_MANUAL_REPLICATE_CONTROL[0], sizeof(mmDSCL3_SCL_MANUAL_REPLICATE_CONTROL)/sizeof(mmDSCL3_SCL_MANUAL_REPLICATE_CONTROL[0]), 0, 0 }, + { "mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO", REG_MMIO, 0x0fba, 2, &mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO[0], sizeof(mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO)/sizeof(mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO[0]), 0, 0 }, + { "mmDSCL3_SCL_HORZ_FILTER_INIT", REG_MMIO, 0x0fbb, 2, &mmDSCL3_SCL_HORZ_FILTER_INIT[0], sizeof(mmDSCL3_SCL_HORZ_FILTER_INIT)/sizeof(mmDSCL3_SCL_HORZ_FILTER_INIT[0]), 0, 0 }, + { "mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C", REG_MMIO, 0x0fbc, 2, &mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C[0], sizeof(mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C)/sizeof(mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C[0]), 0, 0 }, + { "mmDSCL3_SCL_HORZ_FILTER_INIT_C", REG_MMIO, 0x0fbd, 2, &mmDSCL3_SCL_HORZ_FILTER_INIT_C[0], sizeof(mmDSCL3_SCL_HORZ_FILTER_INIT_C)/sizeof(mmDSCL3_SCL_HORZ_FILTER_INIT_C[0]), 0, 0 }, + { "mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO", REG_MMIO, 0x0fbe, 2, &mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO[0], sizeof(mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO)/sizeof(mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO[0]), 0, 0 }, + { "mmDSCL3_SCL_VERT_FILTER_INIT", REG_MMIO, 0x0fbf, 2, &mmDSCL3_SCL_VERT_FILTER_INIT[0], sizeof(mmDSCL3_SCL_VERT_FILTER_INIT)/sizeof(mmDSCL3_SCL_VERT_FILTER_INIT[0]), 0, 0 }, + { "mmDSCL3_SCL_VERT_FILTER_INIT_BOT", REG_MMIO, 0x0fc0, 2, &mmDSCL3_SCL_VERT_FILTER_INIT_BOT[0], sizeof(mmDSCL3_SCL_VERT_FILTER_INIT_BOT)/sizeof(mmDSCL3_SCL_VERT_FILTER_INIT_BOT[0]), 0, 0 }, + { "mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C", REG_MMIO, 0x0fc1, 2, &mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C[0], sizeof(mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C)/sizeof(mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C[0]), 0, 0 }, + { "mmDSCL3_SCL_VERT_FILTER_INIT_C", REG_MMIO, 0x0fc2, 2, &mmDSCL3_SCL_VERT_FILTER_INIT_C[0], sizeof(mmDSCL3_SCL_VERT_FILTER_INIT_C)/sizeof(mmDSCL3_SCL_VERT_FILTER_INIT_C[0]), 0, 0 }, + { "mmDSCL3_SCL_VERT_FILTER_INIT_BOT_C", REG_MMIO, 0x0fc3, 2, &mmDSCL3_SCL_VERT_FILTER_INIT_BOT_C[0], sizeof(mmDSCL3_SCL_VERT_FILTER_INIT_BOT_C)/sizeof(mmDSCL3_SCL_VERT_FILTER_INIT_BOT_C[0]), 0, 0 }, + { "mmDSCL3_SCL_BLACK_OFFSET", REG_MMIO, 0x0fc4, 2, &mmDSCL3_SCL_BLACK_OFFSET[0], sizeof(mmDSCL3_SCL_BLACK_OFFSET)/sizeof(mmDSCL3_SCL_BLACK_OFFSET[0]), 0, 0 }, + { "mmDSCL3_DSCL_UPDATE", REG_MMIO, 0x0fc5, 2, &mmDSCL3_DSCL_UPDATE[0], sizeof(mmDSCL3_DSCL_UPDATE)/sizeof(mmDSCL3_DSCL_UPDATE[0]), 0, 0 }, + { "mmDSCL3_DSCL_AUTOCAL", REG_MMIO, 0x0fc6, 2, &mmDSCL3_DSCL_AUTOCAL[0], sizeof(mmDSCL3_DSCL_AUTOCAL)/sizeof(mmDSCL3_DSCL_AUTOCAL[0]), 0, 0 }, + { "mmDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT", REG_MMIO, 0x0fc7, 2, &mmDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT[0], sizeof(mmDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT)/sizeof(mmDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT[0]), 0, 0 }, + { "mmDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM", REG_MMIO, 0x0fc8, 2, &mmDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM[0], sizeof(mmDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM)/sizeof(mmDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM[0]), 0, 0 }, + { "mmDSCL3_OTG_H_BLANK", REG_MMIO, 0x0fc9, 2, &mmDSCL3_OTG_H_BLANK[0], sizeof(mmDSCL3_OTG_H_BLANK)/sizeof(mmDSCL3_OTG_H_BLANK[0]), 0, 0 }, + { "mmDSCL3_OTG_V_BLANK", REG_MMIO, 0x0fca, 2, &mmDSCL3_OTG_V_BLANK[0], sizeof(mmDSCL3_OTG_V_BLANK)/sizeof(mmDSCL3_OTG_V_BLANK[0]), 0, 0 }, + { "mmDSCL3_RECOUT_START", REG_MMIO, 0x0fcb, 2, &mmDSCL3_RECOUT_START[0], sizeof(mmDSCL3_RECOUT_START)/sizeof(mmDSCL3_RECOUT_START[0]), 0, 0 }, + { "mmDSCL3_RECOUT_SIZE", REG_MMIO, 0x0fcc, 2, &mmDSCL3_RECOUT_SIZE[0], sizeof(mmDSCL3_RECOUT_SIZE)/sizeof(mmDSCL3_RECOUT_SIZE[0]), 0, 0 }, + { "mmDSCL3_MPC_SIZE", REG_MMIO, 0x0fcd, 2, &mmDSCL3_MPC_SIZE[0], sizeof(mmDSCL3_MPC_SIZE)/sizeof(mmDSCL3_MPC_SIZE[0]), 0, 0 }, + { "mmDSCL3_LB_DATA_FORMAT", REG_MMIO, 0x0fce, 2, &mmDSCL3_LB_DATA_FORMAT[0], sizeof(mmDSCL3_LB_DATA_FORMAT)/sizeof(mmDSCL3_LB_DATA_FORMAT[0]), 0, 0 }, + { "mmDSCL3_LB_MEMORY_CTRL", REG_MMIO, 0x0fcf, 2, &mmDSCL3_LB_MEMORY_CTRL[0], sizeof(mmDSCL3_LB_MEMORY_CTRL)/sizeof(mmDSCL3_LB_MEMORY_CTRL[0]), 0, 0 }, + { "mmDSCL3_LB_V_COUNTER", REG_MMIO, 0x0fd0, 2, &mmDSCL3_LB_V_COUNTER[0], sizeof(mmDSCL3_LB_V_COUNTER)/sizeof(mmDSCL3_LB_V_COUNTER[0]), 0, 0 }, + { "mmDSCL3_DSCL_MEM_PWR_CTRL", REG_MMIO, 0x0fd1, 2, &mmDSCL3_DSCL_MEM_PWR_CTRL[0], sizeof(mmDSCL3_DSCL_MEM_PWR_CTRL)/sizeof(mmDSCL3_DSCL_MEM_PWR_CTRL[0]), 0, 0 }, + { "mmDSCL3_DSCL_MEM_PWR_STATUS", REG_MMIO, 0x0fd2, 2, &mmDSCL3_DSCL_MEM_PWR_STATUS[0], sizeof(mmDSCL3_DSCL_MEM_PWR_STATUS)/sizeof(mmDSCL3_DSCL_MEM_PWR_STATUS[0]), 0, 0 }, + { "mmDSCL3_OBUF_CONTROL", REG_MMIO, 0x0fd3, 2, &mmDSCL3_OBUF_CONTROL[0], sizeof(mmDSCL3_OBUF_CONTROL)/sizeof(mmDSCL3_OBUF_CONTROL[0]), 0, 0 }, + { "mmDSCL3_OBUF_MEM_PWR_CTRL", REG_MMIO, 0x0fd4, 2, &mmDSCL3_OBUF_MEM_PWR_CTRL[0], sizeof(mmDSCL3_OBUF_MEM_PWR_CTRL)/sizeof(mmDSCL3_OBUF_MEM_PWR_CTRL[0]), 0, 0 }, + { "mmCM3_CM_CONTROL", REG_MMIO, 0x0fe3, 2, &mmCM3_CM_CONTROL[0], sizeof(mmCM3_CM_CONTROL)/sizeof(mmCM3_CM_CONTROL[0]), 0, 0 }, + { "mmCM3_CM_COMA_C11_C12", REG_MMIO, 0x0fe4, 2, &mmCM3_CM_COMA_C11_C12[0], sizeof(mmCM3_CM_COMA_C11_C12)/sizeof(mmCM3_CM_COMA_C11_C12[0]), 0, 0 }, + { "mmCM3_CM_COMA_C13_C14", REG_MMIO, 0x0fe5, 2, &mmCM3_CM_COMA_C13_C14[0], sizeof(mmCM3_CM_COMA_C13_C14)/sizeof(mmCM3_CM_COMA_C13_C14[0]), 0, 0 }, + { "mmCM3_CM_COMA_C21_C22", REG_MMIO, 0x0fe6, 2, &mmCM3_CM_COMA_C21_C22[0], sizeof(mmCM3_CM_COMA_C21_C22)/sizeof(mmCM3_CM_COMA_C21_C22[0]), 0, 0 }, + { "mmCM3_CM_COMA_C23_C24", REG_MMIO, 0x0fe7, 2, &mmCM3_CM_COMA_C23_C24[0], sizeof(mmCM3_CM_COMA_C23_C24)/sizeof(mmCM3_CM_COMA_C23_C24[0]), 0, 0 }, + { "mmCM3_CM_COMA_C31_C32", REG_MMIO, 0x0fe8, 2, &mmCM3_CM_COMA_C31_C32[0], sizeof(mmCM3_CM_COMA_C31_C32)/sizeof(mmCM3_CM_COMA_C31_C32[0]), 0, 0 }, + { "mmCM3_CM_COMA_C33_C34", REG_MMIO, 0x0fe9, 2, &mmCM3_CM_COMA_C33_C34[0], sizeof(mmCM3_CM_COMA_C33_C34)/sizeof(mmCM3_CM_COMA_C33_C34[0]), 0, 0 }, + { "mmCM3_CM_COMB_C11_C12", REG_MMIO, 0x0fea, 2, &mmCM3_CM_COMB_C11_C12[0], sizeof(mmCM3_CM_COMB_C11_C12)/sizeof(mmCM3_CM_COMB_C11_C12[0]), 0, 0 }, + { "mmCM3_CM_COMB_C13_C14", REG_MMIO, 0x0feb, 2, &mmCM3_CM_COMB_C13_C14[0], sizeof(mmCM3_CM_COMB_C13_C14)/sizeof(mmCM3_CM_COMB_C13_C14[0]), 0, 0 }, + { "mmCM3_CM_COMB_C21_C22", REG_MMIO, 0x0fec, 2, &mmCM3_CM_COMB_C21_C22[0], sizeof(mmCM3_CM_COMB_C21_C22)/sizeof(mmCM3_CM_COMB_C21_C22[0]), 0, 0 }, + { "mmCM3_CM_COMB_C23_C24", REG_MMIO, 0x0fed, 2, &mmCM3_CM_COMB_C23_C24[0], sizeof(mmCM3_CM_COMB_C23_C24)/sizeof(mmCM3_CM_COMB_C23_C24[0]), 0, 0 }, + { "mmCM3_CM_COMB_C31_C32", REG_MMIO, 0x0fee, 2, &mmCM3_CM_COMB_C31_C32[0], sizeof(mmCM3_CM_COMB_C31_C32)/sizeof(mmCM3_CM_COMB_C31_C32[0]), 0, 0 }, + { "mmCM3_CM_COMB_C33_C34", REG_MMIO, 0x0fef, 2, &mmCM3_CM_COMB_C33_C34[0], sizeof(mmCM3_CM_COMB_C33_C34)/sizeof(mmCM3_CM_COMB_C33_C34[0]), 0, 0 }, + { "mmCM3_CM_IGAM_CONTROL", REG_MMIO, 0x0ff0, 2, &mmCM3_CM_IGAM_CONTROL[0], sizeof(mmCM3_CM_IGAM_CONTROL)/sizeof(mmCM3_CM_IGAM_CONTROL[0]), 0, 0 }, + { "mmCM3_CM_IGAM_LUT_RW_CONTROL", REG_MMIO, 0x0ff1, 2, &mmCM3_CM_IGAM_LUT_RW_CONTROL[0], sizeof(mmCM3_CM_IGAM_LUT_RW_CONTROL)/sizeof(mmCM3_CM_IGAM_LUT_RW_CONTROL[0]), 0, 0 }, + { "mmCM3_CM_IGAM_LUT_RW_INDEX", REG_MMIO, 0x0ff2, 2, &mmCM3_CM_IGAM_LUT_RW_INDEX[0], sizeof(mmCM3_CM_IGAM_LUT_RW_INDEX)/sizeof(mmCM3_CM_IGAM_LUT_RW_INDEX[0]), 0, 0 }, + { "mmCM3_CM_IGAM_LUT_SEQ_COLOR", REG_MMIO, 0x0ff3, 2, &mmCM3_CM_IGAM_LUT_SEQ_COLOR[0], sizeof(mmCM3_CM_IGAM_LUT_SEQ_COLOR)/sizeof(mmCM3_CM_IGAM_LUT_SEQ_COLOR[0]), 0, 0 }, + { "mmCM3_CM_IGAM_LUT_30_COLOR", REG_MMIO, 0x0ff4, 2, &mmCM3_CM_IGAM_LUT_30_COLOR[0], sizeof(mmCM3_CM_IGAM_LUT_30_COLOR)/sizeof(mmCM3_CM_IGAM_LUT_30_COLOR[0]), 0, 0 }, + { "mmCM3_CM_IGAM_LUT_PWL_DATA", REG_MMIO, 0x0ff5, 2, &mmCM3_CM_IGAM_LUT_PWL_DATA[0], sizeof(mmCM3_CM_IGAM_LUT_PWL_DATA)/sizeof(mmCM3_CM_IGAM_LUT_PWL_DATA[0]), 0, 0 }, + { "mmCM3_CM_IGAM_LUT_AUTOFILL", REG_MMIO, 0x0ff6, 2, &mmCM3_CM_IGAM_LUT_AUTOFILL[0], sizeof(mmCM3_CM_IGAM_LUT_AUTOFILL)/sizeof(mmCM3_CM_IGAM_LUT_AUTOFILL[0]), 0, 0 }, + { "mmCM3_CM_IGAM_LUT_BW_OFFSET_BLUE", REG_MMIO, 0x0ff7, 2, &mmCM3_CM_IGAM_LUT_BW_OFFSET_BLUE[0], sizeof(mmCM3_CM_IGAM_LUT_BW_OFFSET_BLUE)/sizeof(mmCM3_CM_IGAM_LUT_BW_OFFSET_BLUE[0]), 0, 0 }, + { "mmCM3_CM_IGAM_LUT_BW_OFFSET_GREEN", REG_MMIO, 0x0ff8, 2, &mmCM3_CM_IGAM_LUT_BW_OFFSET_GREEN[0], sizeof(mmCM3_CM_IGAM_LUT_BW_OFFSET_GREEN)/sizeof(mmCM3_CM_IGAM_LUT_BW_OFFSET_GREEN[0]), 0, 0 }, + { "mmCM3_CM_IGAM_LUT_BW_OFFSET_RED", REG_MMIO, 0x0ff9, 2, &mmCM3_CM_IGAM_LUT_BW_OFFSET_RED[0], sizeof(mmCM3_CM_IGAM_LUT_BW_OFFSET_RED)/sizeof(mmCM3_CM_IGAM_LUT_BW_OFFSET_RED[0]), 0, 0 }, + { "mmCM3_CM_ICSC_CONTROL", REG_MMIO, 0x0ffa, 2, &mmCM3_CM_ICSC_CONTROL[0], sizeof(mmCM3_CM_ICSC_CONTROL)/sizeof(mmCM3_CM_ICSC_CONTROL[0]), 0, 0 }, + { "mmCM3_CM_ICSC_C11_C12", REG_MMIO, 0x0ffb, 2, &mmCM3_CM_ICSC_C11_C12[0], sizeof(mmCM3_CM_ICSC_C11_C12)/sizeof(mmCM3_CM_ICSC_C11_C12[0]), 0, 0 }, + { "mmCM3_CM_ICSC_C13_C14", REG_MMIO, 0x0ffc, 2, &mmCM3_CM_ICSC_C13_C14[0], sizeof(mmCM3_CM_ICSC_C13_C14)/sizeof(mmCM3_CM_ICSC_C13_C14[0]), 0, 0 }, + { "mmCM3_CM_ICSC_C21_C22", REG_MMIO, 0x0ffd, 2, &mmCM3_CM_ICSC_C21_C22[0], sizeof(mmCM3_CM_ICSC_C21_C22)/sizeof(mmCM3_CM_ICSC_C21_C22[0]), 0, 0 }, + { "mmCM3_CM_ICSC_C23_C24", REG_MMIO, 0x0ffe, 2, &mmCM3_CM_ICSC_C23_C24[0], sizeof(mmCM3_CM_ICSC_C23_C24)/sizeof(mmCM3_CM_ICSC_C23_C24[0]), 0, 0 }, + { "mmCM3_CM_ICSC_C31_C32", REG_MMIO, 0x0fff, 2, &mmCM3_CM_ICSC_C31_C32[0], sizeof(mmCM3_CM_ICSC_C31_C32)/sizeof(mmCM3_CM_ICSC_C31_C32[0]), 0, 0 }, + { "mmCM3_CM_ICSC_C33_C34", REG_MMIO, 0x1000, 2, &mmCM3_CM_ICSC_C33_C34[0], sizeof(mmCM3_CM_ICSC_C33_C34)/sizeof(mmCM3_CM_ICSC_C33_C34[0]), 0, 0 }, + { "mmCM3_CM_GAMUT_REMAP_CONTROL", REG_MMIO, 0x1001, 2, &mmCM3_CM_GAMUT_REMAP_CONTROL[0], sizeof(mmCM3_CM_GAMUT_REMAP_CONTROL)/sizeof(mmCM3_CM_GAMUT_REMAP_CONTROL[0]), 0, 0 }, + { "mmCM3_CM_GAMUT_REMAP_C11_C12", REG_MMIO, 0x1002, 2, &mmCM3_CM_GAMUT_REMAP_C11_C12[0], sizeof(mmCM3_CM_GAMUT_REMAP_C11_C12)/sizeof(mmCM3_CM_GAMUT_REMAP_C11_C12[0]), 0, 0 }, + { "mmCM3_CM_GAMUT_REMAP_C13_C14", REG_MMIO, 0x1003, 2, &mmCM3_CM_GAMUT_REMAP_C13_C14[0], sizeof(mmCM3_CM_GAMUT_REMAP_C13_C14)/sizeof(mmCM3_CM_GAMUT_REMAP_C13_C14[0]), 0, 0 }, + { "mmCM3_CM_GAMUT_REMAP_C21_C22", REG_MMIO, 0x1004, 2, &mmCM3_CM_GAMUT_REMAP_C21_C22[0], sizeof(mmCM3_CM_GAMUT_REMAP_C21_C22)/sizeof(mmCM3_CM_GAMUT_REMAP_C21_C22[0]), 0, 0 }, + { "mmCM3_CM_GAMUT_REMAP_C23_C24", REG_MMIO, 0x1005, 2, &mmCM3_CM_GAMUT_REMAP_C23_C24[0], sizeof(mmCM3_CM_GAMUT_REMAP_C23_C24)/sizeof(mmCM3_CM_GAMUT_REMAP_C23_C24[0]), 0, 0 }, + { "mmCM3_CM_GAMUT_REMAP_C31_C32", REG_MMIO, 0x1006, 2, &mmCM3_CM_GAMUT_REMAP_C31_C32[0], sizeof(mmCM3_CM_GAMUT_REMAP_C31_C32)/sizeof(mmCM3_CM_GAMUT_REMAP_C31_C32[0]), 0, 0 }, + { "mmCM3_CM_GAMUT_REMAP_C33_C34", REG_MMIO, 0x1007, 2, &mmCM3_CM_GAMUT_REMAP_C33_C34[0], sizeof(mmCM3_CM_GAMUT_REMAP_C33_C34)/sizeof(mmCM3_CM_GAMUT_REMAP_C33_C34[0]), 0, 0 }, + { "mmCM3_CM_OCSC_CONTROL", REG_MMIO, 0x1008, 2, &mmCM3_CM_OCSC_CONTROL[0], sizeof(mmCM3_CM_OCSC_CONTROL)/sizeof(mmCM3_CM_OCSC_CONTROL[0]), 0, 0 }, + { "mmCM3_CM_OCSC_C11_C12", REG_MMIO, 0x1009, 2, &mmCM3_CM_OCSC_C11_C12[0], sizeof(mmCM3_CM_OCSC_C11_C12)/sizeof(mmCM3_CM_OCSC_C11_C12[0]), 0, 0 }, + { "mmCM3_CM_OCSC_C13_C14", REG_MMIO, 0x100a, 2, &mmCM3_CM_OCSC_C13_C14[0], sizeof(mmCM3_CM_OCSC_C13_C14)/sizeof(mmCM3_CM_OCSC_C13_C14[0]), 0, 0 }, + { "mmCM3_CM_OCSC_C21_C22", REG_MMIO, 0x100b, 2, &mmCM3_CM_OCSC_C21_C22[0], sizeof(mmCM3_CM_OCSC_C21_C22)/sizeof(mmCM3_CM_OCSC_C21_C22[0]), 0, 0 }, + { "mmCM3_CM_OCSC_C23_C24", REG_MMIO, 0x100c, 2, &mmCM3_CM_OCSC_C23_C24[0], sizeof(mmCM3_CM_OCSC_C23_C24)/sizeof(mmCM3_CM_OCSC_C23_C24[0]), 0, 0 }, + { "mmCM3_CM_OCSC_C31_C32", REG_MMIO, 0x100d, 2, &mmCM3_CM_OCSC_C31_C32[0], sizeof(mmCM3_CM_OCSC_C31_C32)/sizeof(mmCM3_CM_OCSC_C31_C32[0]), 0, 0 }, + { "mmCM3_CM_OCSC_C33_C34", REG_MMIO, 0x100e, 2, &mmCM3_CM_OCSC_C33_C34[0], sizeof(mmCM3_CM_OCSC_C33_C34)/sizeof(mmCM3_CM_OCSC_C33_C34[0]), 0, 0 }, + { "mmCM3_CM_BNS_VALUES_R", REG_MMIO, 0x100f, 2, &mmCM3_CM_BNS_VALUES_R[0], sizeof(mmCM3_CM_BNS_VALUES_R)/sizeof(mmCM3_CM_BNS_VALUES_R[0]), 0, 0 }, + { "mmCM3_CM_BNS_VALUES_G", REG_MMIO, 0x1010, 2, &mmCM3_CM_BNS_VALUES_G[0], sizeof(mmCM3_CM_BNS_VALUES_G)/sizeof(mmCM3_CM_BNS_VALUES_G[0]), 0, 0 }, + { "mmCM3_CM_BNS_VALUES_B", REG_MMIO, 0x1011, 2, &mmCM3_CM_BNS_VALUES_B[0], sizeof(mmCM3_CM_BNS_VALUES_B)/sizeof(mmCM3_CM_BNS_VALUES_B[0]), 0, 0 }, + { "mmCM3_CM_DGAM_CONTROL", REG_MMIO, 0x1012, 2, &mmCM3_CM_DGAM_CONTROL[0], sizeof(mmCM3_CM_DGAM_CONTROL)/sizeof(mmCM3_CM_DGAM_CONTROL[0]), 0, 0 }, + { "mmCM3_CM_DGAM_LUT_INDEX", REG_MMIO, 0x1013, 2, &mmCM3_CM_DGAM_LUT_INDEX[0], sizeof(mmCM3_CM_DGAM_LUT_INDEX)/sizeof(mmCM3_CM_DGAM_LUT_INDEX[0]), 0, 0 }, + { "mmCM3_CM_DGAM_LUT_DATA", REG_MMIO, 0x1014, 2, &mmCM3_CM_DGAM_LUT_DATA[0], sizeof(mmCM3_CM_DGAM_LUT_DATA)/sizeof(mmCM3_CM_DGAM_LUT_DATA[0]), 0, 0 }, + { "mmCM3_CM_DGAM_LUT_WRITE_EN_MASK", REG_MMIO, 0x1015, 2, &mmCM3_CM_DGAM_LUT_WRITE_EN_MASK[0], sizeof(mmCM3_CM_DGAM_LUT_WRITE_EN_MASK)/sizeof(mmCM3_CM_DGAM_LUT_WRITE_EN_MASK[0]), 0, 0 }, + { "mmCM3_CM_DGAM_RAMA_START_CNTL_B", REG_MMIO, 0x1016, 2, &mmCM3_CM_DGAM_RAMA_START_CNTL_B[0], sizeof(mmCM3_CM_DGAM_RAMA_START_CNTL_B)/sizeof(mmCM3_CM_DGAM_RAMA_START_CNTL_B[0]), 0, 0 }, + { "mmCM3_CM_DGAM_RAMA_START_CNTL_G", REG_MMIO, 0x1017, 2, &mmCM3_CM_DGAM_RAMA_START_CNTL_G[0], sizeof(mmCM3_CM_DGAM_RAMA_START_CNTL_G)/sizeof(mmCM3_CM_DGAM_RAMA_START_CNTL_G[0]), 0, 0 }, + { "mmCM3_CM_DGAM_RAMA_START_CNTL_R", REG_MMIO, 0x1018, 2, &mmCM3_CM_DGAM_RAMA_START_CNTL_R[0], sizeof(mmCM3_CM_DGAM_RAMA_START_CNTL_R)/sizeof(mmCM3_CM_DGAM_RAMA_START_CNTL_R[0]), 0, 0 }, + { "mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_B", REG_MMIO, 0x1019, 2, &mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_B[0], sizeof(mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_B)/sizeof(mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_B[0]), 0, 0 }, + { "mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_G", REG_MMIO, 0x101a, 2, &mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_G[0], sizeof(mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_G)/sizeof(mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_G[0]), 0, 0 }, + { "mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_R", REG_MMIO, 0x101b, 2, &mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_R[0], sizeof(mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_R)/sizeof(mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_R[0]), 0, 0 }, + { "mmCM3_CM_DGAM_RAMA_END_CNTL1_B", REG_MMIO, 0x101c, 2, &mmCM3_CM_DGAM_RAMA_END_CNTL1_B[0], sizeof(mmCM3_CM_DGAM_RAMA_END_CNTL1_B)/sizeof(mmCM3_CM_DGAM_RAMA_END_CNTL1_B[0]), 0, 0 }, + { "mmCM3_CM_DGAM_RAMA_END_CNTL2_B", REG_MMIO, 0x101d, 2, &mmCM3_CM_DGAM_RAMA_END_CNTL2_B[0], sizeof(mmCM3_CM_DGAM_RAMA_END_CNTL2_B)/sizeof(mmCM3_CM_DGAM_RAMA_END_CNTL2_B[0]), 0, 0 }, + { "mmCM3_CM_DGAM_RAMA_END_CNTL1_G", REG_MMIO, 0x101e, 2, &mmCM3_CM_DGAM_RAMA_END_CNTL1_G[0], sizeof(mmCM3_CM_DGAM_RAMA_END_CNTL1_G)/sizeof(mmCM3_CM_DGAM_RAMA_END_CNTL1_G[0]), 0, 0 }, + { "mmCM3_CM_DGAM_RAMA_END_CNTL2_G", REG_MMIO, 0x101f, 2, &mmCM3_CM_DGAM_RAMA_END_CNTL2_G[0], sizeof(mmCM3_CM_DGAM_RAMA_END_CNTL2_G)/sizeof(mmCM3_CM_DGAM_RAMA_END_CNTL2_G[0]), 0, 0 }, + { "mmCM3_CM_DGAM_RAMA_END_CNTL1_R", REG_MMIO, 0x1020, 2, &mmCM3_CM_DGAM_RAMA_END_CNTL1_R[0], sizeof(mmCM3_CM_DGAM_RAMA_END_CNTL1_R)/sizeof(mmCM3_CM_DGAM_RAMA_END_CNTL1_R[0]), 0, 0 }, + { "mmCM3_CM_DGAM_RAMA_END_CNTL2_R", REG_MMIO, 0x1021, 2, &mmCM3_CM_DGAM_RAMA_END_CNTL2_R[0], sizeof(mmCM3_CM_DGAM_RAMA_END_CNTL2_R)/sizeof(mmCM3_CM_DGAM_RAMA_END_CNTL2_R[0]), 0, 0 }, + { "mmCM3_CM_DGAM_RAMA_REGION_0_1", REG_MMIO, 0x1022, 2, &mmCM3_CM_DGAM_RAMA_REGION_0_1[0], sizeof(mmCM3_CM_DGAM_RAMA_REGION_0_1)/sizeof(mmCM3_CM_DGAM_RAMA_REGION_0_1[0]), 0, 0 }, + { "mmCM3_CM_DGAM_RAMA_REGION_2_3", REG_MMIO, 0x1023, 2, &mmCM3_CM_DGAM_RAMA_REGION_2_3[0], sizeof(mmCM3_CM_DGAM_RAMA_REGION_2_3)/sizeof(mmCM3_CM_DGAM_RAMA_REGION_2_3[0]), 0, 0 }, + { "mmCM3_CM_DGAM_RAMA_REGION_4_5", REG_MMIO, 0x1024, 2, &mmCM3_CM_DGAM_RAMA_REGION_4_5[0], sizeof(mmCM3_CM_DGAM_RAMA_REGION_4_5)/sizeof(mmCM3_CM_DGAM_RAMA_REGION_4_5[0]), 0, 0 }, + { "mmCM3_CM_DGAM_RAMA_REGION_6_7", REG_MMIO, 0x1025, 2, &mmCM3_CM_DGAM_RAMA_REGION_6_7[0], sizeof(mmCM3_CM_DGAM_RAMA_REGION_6_7)/sizeof(mmCM3_CM_DGAM_RAMA_REGION_6_7[0]), 0, 0 }, + { "mmCM3_CM_DGAM_RAMA_REGION_8_9", REG_MMIO, 0x1026, 2, &mmCM3_CM_DGAM_RAMA_REGION_8_9[0], sizeof(mmCM3_CM_DGAM_RAMA_REGION_8_9)/sizeof(mmCM3_CM_DGAM_RAMA_REGION_8_9[0]), 0, 0 }, + { "mmCM3_CM_DGAM_RAMA_REGION_10_11", REG_MMIO, 0x1027, 2, &mmCM3_CM_DGAM_RAMA_REGION_10_11[0], sizeof(mmCM3_CM_DGAM_RAMA_REGION_10_11)/sizeof(mmCM3_CM_DGAM_RAMA_REGION_10_11[0]), 0, 0 }, + { "mmCM3_CM_DGAM_RAMA_REGION_12_13", REG_MMIO, 0x1028, 2, &mmCM3_CM_DGAM_RAMA_REGION_12_13[0], sizeof(mmCM3_CM_DGAM_RAMA_REGION_12_13)/sizeof(mmCM3_CM_DGAM_RAMA_REGION_12_13[0]), 0, 0 }, + { "mmCM3_CM_DGAM_RAMA_REGION_14_15", REG_MMIO, 0x1029, 2, &mmCM3_CM_DGAM_RAMA_REGION_14_15[0], sizeof(mmCM3_CM_DGAM_RAMA_REGION_14_15)/sizeof(mmCM3_CM_DGAM_RAMA_REGION_14_15[0]), 0, 0 }, + { "mmCM3_CM_DGAM_RAMB_START_CNTL_B", REG_MMIO, 0x102a, 2, &mmCM3_CM_DGAM_RAMB_START_CNTL_B[0], sizeof(mmCM3_CM_DGAM_RAMB_START_CNTL_B)/sizeof(mmCM3_CM_DGAM_RAMB_START_CNTL_B[0]), 0, 0 }, + { "mmCM3_CM_DGAM_RAMB_START_CNTL_G", REG_MMIO, 0x102b, 2, &mmCM3_CM_DGAM_RAMB_START_CNTL_G[0], sizeof(mmCM3_CM_DGAM_RAMB_START_CNTL_G)/sizeof(mmCM3_CM_DGAM_RAMB_START_CNTL_G[0]), 0, 0 }, + { "mmCM3_CM_DGAM_RAMB_START_CNTL_R", REG_MMIO, 0x102c, 2, &mmCM3_CM_DGAM_RAMB_START_CNTL_R[0], sizeof(mmCM3_CM_DGAM_RAMB_START_CNTL_R)/sizeof(mmCM3_CM_DGAM_RAMB_START_CNTL_R[0]), 0, 0 }, + { "mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_B", REG_MMIO, 0x102d, 2, &mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_B[0], sizeof(mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_B)/sizeof(mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_B[0]), 0, 0 }, + { "mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_G", REG_MMIO, 0x102e, 2, &mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_G[0], sizeof(mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_G)/sizeof(mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_G[0]), 0, 0 }, + { "mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_R", REG_MMIO, 0x102f, 2, &mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_R[0], sizeof(mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_R)/sizeof(mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_R[0]), 0, 0 }, + { "mmCM3_CM_DGAM_RAMB_END_CNTL1_B", REG_MMIO, 0x1030, 2, &mmCM3_CM_DGAM_RAMB_END_CNTL1_B[0], sizeof(mmCM3_CM_DGAM_RAMB_END_CNTL1_B)/sizeof(mmCM3_CM_DGAM_RAMB_END_CNTL1_B[0]), 0, 0 }, + { "mmCM3_CM_DGAM_RAMB_END_CNTL2_B", REG_MMIO, 0x1031, 2, &mmCM3_CM_DGAM_RAMB_END_CNTL2_B[0], sizeof(mmCM3_CM_DGAM_RAMB_END_CNTL2_B)/sizeof(mmCM3_CM_DGAM_RAMB_END_CNTL2_B[0]), 0, 0 }, + { "mmCM3_CM_DGAM_RAMB_END_CNTL1_G", REG_MMIO, 0x1032, 2, &mmCM3_CM_DGAM_RAMB_END_CNTL1_G[0], sizeof(mmCM3_CM_DGAM_RAMB_END_CNTL1_G)/sizeof(mmCM3_CM_DGAM_RAMB_END_CNTL1_G[0]), 0, 0 }, + { "mmCM3_CM_DGAM_RAMB_END_CNTL2_G", REG_MMIO, 0x1033, 2, &mmCM3_CM_DGAM_RAMB_END_CNTL2_G[0], sizeof(mmCM3_CM_DGAM_RAMB_END_CNTL2_G)/sizeof(mmCM3_CM_DGAM_RAMB_END_CNTL2_G[0]), 0, 0 }, + { "mmCM3_CM_DGAM_RAMB_END_CNTL1_R", REG_MMIO, 0x1034, 2, &mmCM3_CM_DGAM_RAMB_END_CNTL1_R[0], sizeof(mmCM3_CM_DGAM_RAMB_END_CNTL1_R)/sizeof(mmCM3_CM_DGAM_RAMB_END_CNTL1_R[0]), 0, 0 }, + { "mmCM3_CM_DGAM_RAMB_END_CNTL2_R", REG_MMIO, 0x1035, 2, &mmCM3_CM_DGAM_RAMB_END_CNTL2_R[0], sizeof(mmCM3_CM_DGAM_RAMB_END_CNTL2_R)/sizeof(mmCM3_CM_DGAM_RAMB_END_CNTL2_R[0]), 0, 0 }, + { "mmCM3_CM_DGAM_RAMB_REGION_0_1", REG_MMIO, 0x1036, 2, &mmCM3_CM_DGAM_RAMB_REGION_0_1[0], sizeof(mmCM3_CM_DGAM_RAMB_REGION_0_1)/sizeof(mmCM3_CM_DGAM_RAMB_REGION_0_1[0]), 0, 0 }, + { "mmCM3_CM_DGAM_RAMB_REGION_2_3", REG_MMIO, 0x1037, 2, &mmCM3_CM_DGAM_RAMB_REGION_2_3[0], sizeof(mmCM3_CM_DGAM_RAMB_REGION_2_3)/sizeof(mmCM3_CM_DGAM_RAMB_REGION_2_3[0]), 0, 0 }, + { "mmCM3_CM_DGAM_RAMB_REGION_4_5", REG_MMIO, 0x1038, 2, &mmCM3_CM_DGAM_RAMB_REGION_4_5[0], sizeof(mmCM3_CM_DGAM_RAMB_REGION_4_5)/sizeof(mmCM3_CM_DGAM_RAMB_REGION_4_5[0]), 0, 0 }, + { "mmCM3_CM_DGAM_RAMB_REGION_6_7", REG_MMIO, 0x1039, 2, &mmCM3_CM_DGAM_RAMB_REGION_6_7[0], sizeof(mmCM3_CM_DGAM_RAMB_REGION_6_7)/sizeof(mmCM3_CM_DGAM_RAMB_REGION_6_7[0]), 0, 0 }, + { "mmCM3_CM_DGAM_RAMB_REGION_8_9", REG_MMIO, 0x103a, 2, &mmCM3_CM_DGAM_RAMB_REGION_8_9[0], sizeof(mmCM3_CM_DGAM_RAMB_REGION_8_9)/sizeof(mmCM3_CM_DGAM_RAMB_REGION_8_9[0]), 0, 0 }, + { "mmCM3_CM_DGAM_RAMB_REGION_10_11", REG_MMIO, 0x103b, 2, &mmCM3_CM_DGAM_RAMB_REGION_10_11[0], sizeof(mmCM3_CM_DGAM_RAMB_REGION_10_11)/sizeof(mmCM3_CM_DGAM_RAMB_REGION_10_11[0]), 0, 0 }, + { "mmCM3_CM_DGAM_RAMB_REGION_12_13", REG_MMIO, 0x103c, 2, &mmCM3_CM_DGAM_RAMB_REGION_12_13[0], sizeof(mmCM3_CM_DGAM_RAMB_REGION_12_13)/sizeof(mmCM3_CM_DGAM_RAMB_REGION_12_13[0]), 0, 0 }, + { "mmCM3_CM_DGAM_RAMB_REGION_14_15", REG_MMIO, 0x103d, 2, &mmCM3_CM_DGAM_RAMB_REGION_14_15[0], sizeof(mmCM3_CM_DGAM_RAMB_REGION_14_15)/sizeof(mmCM3_CM_DGAM_RAMB_REGION_14_15[0]), 0, 0 }, + { "mmCM3_CM_RGAM_CONTROL", REG_MMIO, 0x103e, 2, &mmCM3_CM_RGAM_CONTROL[0], sizeof(mmCM3_CM_RGAM_CONTROL)/sizeof(mmCM3_CM_RGAM_CONTROL[0]), 0, 0 }, + { "mmCM3_CM_RGAM_LUT_INDEX", REG_MMIO, 0x103f, 2, &mmCM3_CM_RGAM_LUT_INDEX[0], sizeof(mmCM3_CM_RGAM_LUT_INDEX)/sizeof(mmCM3_CM_RGAM_LUT_INDEX[0]), 0, 0 }, + { "mmCM3_CM_RGAM_LUT_DATA", REG_MMIO, 0x1040, 2, &mmCM3_CM_RGAM_LUT_DATA[0], sizeof(mmCM3_CM_RGAM_LUT_DATA)/sizeof(mmCM3_CM_RGAM_LUT_DATA[0]), 0, 0 }, + { "mmCM3_CM_RGAM_LUT_WRITE_EN_MASK", REG_MMIO, 0x1041, 2, &mmCM3_CM_RGAM_LUT_WRITE_EN_MASK[0], sizeof(mmCM3_CM_RGAM_LUT_WRITE_EN_MASK)/sizeof(mmCM3_CM_RGAM_LUT_WRITE_EN_MASK[0]), 0, 0 }, + { "mmCM3_CM_RGAM_RAMA_START_CNTL_B", REG_MMIO, 0x1042, 2, &mmCM3_CM_RGAM_RAMA_START_CNTL_B[0], sizeof(mmCM3_CM_RGAM_RAMA_START_CNTL_B)/sizeof(mmCM3_CM_RGAM_RAMA_START_CNTL_B[0]), 0, 0 }, + { "mmCM3_CM_RGAM_RAMA_START_CNTL_G", REG_MMIO, 0x1043, 2, &mmCM3_CM_RGAM_RAMA_START_CNTL_G[0], sizeof(mmCM3_CM_RGAM_RAMA_START_CNTL_G)/sizeof(mmCM3_CM_RGAM_RAMA_START_CNTL_G[0]), 0, 0 }, + { "mmCM3_CM_RGAM_RAMA_START_CNTL_R", REG_MMIO, 0x1044, 2, &mmCM3_CM_RGAM_RAMA_START_CNTL_R[0], sizeof(mmCM3_CM_RGAM_RAMA_START_CNTL_R)/sizeof(mmCM3_CM_RGAM_RAMA_START_CNTL_R[0]), 0, 0 }, + { "mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_B", REG_MMIO, 0x1045, 2, &mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_B[0], sizeof(mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_B)/sizeof(mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_B[0]), 0, 0 }, + { "mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_G", REG_MMIO, 0x1046, 2, &mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_G[0], sizeof(mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_G)/sizeof(mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_G[0]), 0, 0 }, + { "mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_R", REG_MMIO, 0x1047, 2, &mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_R[0], sizeof(mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_R)/sizeof(mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_R[0]), 0, 0 }, + { "mmCM3_CM_RGAM_RAMA_END_CNTL1_B", REG_MMIO, 0x1048, 2, &mmCM3_CM_RGAM_RAMA_END_CNTL1_B[0], sizeof(mmCM3_CM_RGAM_RAMA_END_CNTL1_B)/sizeof(mmCM3_CM_RGAM_RAMA_END_CNTL1_B[0]), 0, 0 }, + { "mmCM3_CM_RGAM_RAMA_END_CNTL2_B", REG_MMIO, 0x1049, 2, &mmCM3_CM_RGAM_RAMA_END_CNTL2_B[0], sizeof(mmCM3_CM_RGAM_RAMA_END_CNTL2_B)/sizeof(mmCM3_CM_RGAM_RAMA_END_CNTL2_B[0]), 0, 0 }, + { "mmCM3_CM_RGAM_RAMA_END_CNTL1_G", REG_MMIO, 0x104a, 2, &mmCM3_CM_RGAM_RAMA_END_CNTL1_G[0], sizeof(mmCM3_CM_RGAM_RAMA_END_CNTL1_G)/sizeof(mmCM3_CM_RGAM_RAMA_END_CNTL1_G[0]), 0, 0 }, + { "mmCM3_CM_RGAM_RAMA_END_CNTL2_G", REG_MMIO, 0x104b, 2, &mmCM3_CM_RGAM_RAMA_END_CNTL2_G[0], sizeof(mmCM3_CM_RGAM_RAMA_END_CNTL2_G)/sizeof(mmCM3_CM_RGAM_RAMA_END_CNTL2_G[0]), 0, 0 }, + { "mmCM3_CM_RGAM_RAMA_END_CNTL1_R", REG_MMIO, 0x104c, 2, &mmCM3_CM_RGAM_RAMA_END_CNTL1_R[0], sizeof(mmCM3_CM_RGAM_RAMA_END_CNTL1_R)/sizeof(mmCM3_CM_RGAM_RAMA_END_CNTL1_R[0]), 0, 0 }, + { "mmCM3_CM_RGAM_RAMA_END_CNTL2_R", REG_MMIO, 0x104d, 2, &mmCM3_CM_RGAM_RAMA_END_CNTL2_R[0], sizeof(mmCM3_CM_RGAM_RAMA_END_CNTL2_R)/sizeof(mmCM3_CM_RGAM_RAMA_END_CNTL2_R[0]), 0, 0 }, + { "mmCM3_CM_RGAM_RAMA_REGION_0_1", REG_MMIO, 0x104e, 2, &mmCM3_CM_RGAM_RAMA_REGION_0_1[0], sizeof(mmCM3_CM_RGAM_RAMA_REGION_0_1)/sizeof(mmCM3_CM_RGAM_RAMA_REGION_0_1[0]), 0, 0 }, + { "mmCM3_CM_RGAM_RAMA_REGION_2_3", REG_MMIO, 0x104f, 2, &mmCM3_CM_RGAM_RAMA_REGION_2_3[0], sizeof(mmCM3_CM_RGAM_RAMA_REGION_2_3)/sizeof(mmCM3_CM_RGAM_RAMA_REGION_2_3[0]), 0, 0 }, + { "mmCM3_CM_RGAM_RAMA_REGION_4_5", REG_MMIO, 0x1050, 2, &mmCM3_CM_RGAM_RAMA_REGION_4_5[0], sizeof(mmCM3_CM_RGAM_RAMA_REGION_4_5)/sizeof(mmCM3_CM_RGAM_RAMA_REGION_4_5[0]), 0, 0 }, + { "mmCM3_CM_RGAM_RAMA_REGION_6_7", REG_MMIO, 0x1051, 2, &mmCM3_CM_RGAM_RAMA_REGION_6_7[0], sizeof(mmCM3_CM_RGAM_RAMA_REGION_6_7)/sizeof(mmCM3_CM_RGAM_RAMA_REGION_6_7[0]), 0, 0 }, + { "mmCM3_CM_RGAM_RAMA_REGION_8_9", REG_MMIO, 0x1052, 2, &mmCM3_CM_RGAM_RAMA_REGION_8_9[0], sizeof(mmCM3_CM_RGAM_RAMA_REGION_8_9)/sizeof(mmCM3_CM_RGAM_RAMA_REGION_8_9[0]), 0, 0 }, + { "mmCM3_CM_RGAM_RAMA_REGION_10_11", REG_MMIO, 0x1053, 2, &mmCM3_CM_RGAM_RAMA_REGION_10_11[0], sizeof(mmCM3_CM_RGAM_RAMA_REGION_10_11)/sizeof(mmCM3_CM_RGAM_RAMA_REGION_10_11[0]), 0, 0 }, + { "mmCM3_CM_RGAM_RAMA_REGION_12_13", REG_MMIO, 0x1054, 2, &mmCM3_CM_RGAM_RAMA_REGION_12_13[0], sizeof(mmCM3_CM_RGAM_RAMA_REGION_12_13)/sizeof(mmCM3_CM_RGAM_RAMA_REGION_12_13[0]), 0, 0 }, + { "mmCM3_CM_RGAM_RAMA_REGION_14_15", REG_MMIO, 0x1055, 2, &mmCM3_CM_RGAM_RAMA_REGION_14_15[0], sizeof(mmCM3_CM_RGAM_RAMA_REGION_14_15)/sizeof(mmCM3_CM_RGAM_RAMA_REGION_14_15[0]), 0, 0 }, + { "mmCM3_CM_RGAM_RAMA_REGION_16_17", REG_MMIO, 0x1056, 2, &mmCM3_CM_RGAM_RAMA_REGION_16_17[0], sizeof(mmCM3_CM_RGAM_RAMA_REGION_16_17)/sizeof(mmCM3_CM_RGAM_RAMA_REGION_16_17[0]), 0, 0 }, + { "mmCM3_CM_RGAM_RAMA_REGION_18_19", REG_MMIO, 0x1057, 2, &mmCM3_CM_RGAM_RAMA_REGION_18_19[0], sizeof(mmCM3_CM_RGAM_RAMA_REGION_18_19)/sizeof(mmCM3_CM_RGAM_RAMA_REGION_18_19[0]), 0, 0 }, + { "mmCM3_CM_RGAM_RAMA_REGION_20_21", REG_MMIO, 0x1058, 2, &mmCM3_CM_RGAM_RAMA_REGION_20_21[0], sizeof(mmCM3_CM_RGAM_RAMA_REGION_20_21)/sizeof(mmCM3_CM_RGAM_RAMA_REGION_20_21[0]), 0, 0 }, + { "mmCM3_CM_RGAM_RAMA_REGION_22_23", REG_MMIO, 0x1059, 2, &mmCM3_CM_RGAM_RAMA_REGION_22_23[0], sizeof(mmCM3_CM_RGAM_RAMA_REGION_22_23)/sizeof(mmCM3_CM_RGAM_RAMA_REGION_22_23[0]), 0, 0 }, + { "mmCM3_CM_RGAM_RAMA_REGION_24_25", REG_MMIO, 0x105a, 2, &mmCM3_CM_RGAM_RAMA_REGION_24_25[0], sizeof(mmCM3_CM_RGAM_RAMA_REGION_24_25)/sizeof(mmCM3_CM_RGAM_RAMA_REGION_24_25[0]), 0, 0 }, + { "mmCM3_CM_RGAM_RAMA_REGION_26_27", REG_MMIO, 0x105b, 2, &mmCM3_CM_RGAM_RAMA_REGION_26_27[0], sizeof(mmCM3_CM_RGAM_RAMA_REGION_26_27)/sizeof(mmCM3_CM_RGAM_RAMA_REGION_26_27[0]), 0, 0 }, + { "mmCM3_CM_RGAM_RAMA_REGION_28_29", REG_MMIO, 0x105c, 2, &mmCM3_CM_RGAM_RAMA_REGION_28_29[0], sizeof(mmCM3_CM_RGAM_RAMA_REGION_28_29)/sizeof(mmCM3_CM_RGAM_RAMA_REGION_28_29[0]), 0, 0 }, + { "mmCM3_CM_RGAM_RAMA_REGION_30_31", REG_MMIO, 0x105d, 2, &mmCM3_CM_RGAM_RAMA_REGION_30_31[0], sizeof(mmCM3_CM_RGAM_RAMA_REGION_30_31)/sizeof(mmCM3_CM_RGAM_RAMA_REGION_30_31[0]), 0, 0 }, + { "mmCM3_CM_RGAM_RAMA_REGION_32_33", REG_MMIO, 0x105e, 2, &mmCM3_CM_RGAM_RAMA_REGION_32_33[0], sizeof(mmCM3_CM_RGAM_RAMA_REGION_32_33)/sizeof(mmCM3_CM_RGAM_RAMA_REGION_32_33[0]), 0, 0 }, + { "mmCM3_CM_RGAM_RAMB_START_CNTL_B", REG_MMIO, 0x105f, 2, &mmCM3_CM_RGAM_RAMB_START_CNTL_B[0], sizeof(mmCM3_CM_RGAM_RAMB_START_CNTL_B)/sizeof(mmCM3_CM_RGAM_RAMB_START_CNTL_B[0]), 0, 0 }, + { "mmCM3_CM_RGAM_RAMB_START_CNTL_G", REG_MMIO, 0x1060, 2, &mmCM3_CM_RGAM_RAMB_START_CNTL_G[0], sizeof(mmCM3_CM_RGAM_RAMB_START_CNTL_G)/sizeof(mmCM3_CM_RGAM_RAMB_START_CNTL_G[0]), 0, 0 }, + { "mmCM3_CM_RGAM_RAMB_START_CNTL_R", REG_MMIO, 0x1061, 2, &mmCM3_CM_RGAM_RAMB_START_CNTL_R[0], sizeof(mmCM3_CM_RGAM_RAMB_START_CNTL_R)/sizeof(mmCM3_CM_RGAM_RAMB_START_CNTL_R[0]), 0, 0 }, + { "mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_B", REG_MMIO, 0x1062, 2, &mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_B[0], sizeof(mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_B)/sizeof(mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_B[0]), 0, 0 }, + { "mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_G", REG_MMIO, 0x1063, 2, &mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_G[0], sizeof(mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_G)/sizeof(mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_G[0]), 0, 0 }, + { "mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_R", REG_MMIO, 0x1064, 2, &mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_R[0], sizeof(mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_R)/sizeof(mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_R[0]), 0, 0 }, + { "mmCM3_CM_RGAM_RAMB_END_CNTL1_B", REG_MMIO, 0x1065, 2, &mmCM3_CM_RGAM_RAMB_END_CNTL1_B[0], sizeof(mmCM3_CM_RGAM_RAMB_END_CNTL1_B)/sizeof(mmCM3_CM_RGAM_RAMB_END_CNTL1_B[0]), 0, 0 }, + { "mmCM3_CM_RGAM_RAMB_END_CNTL2_B", REG_MMIO, 0x1066, 2, &mmCM3_CM_RGAM_RAMB_END_CNTL2_B[0], sizeof(mmCM3_CM_RGAM_RAMB_END_CNTL2_B)/sizeof(mmCM3_CM_RGAM_RAMB_END_CNTL2_B[0]), 0, 0 }, + { "mmCM3_CM_RGAM_RAMB_END_CNTL1_G", REG_MMIO, 0x1067, 2, &mmCM3_CM_RGAM_RAMB_END_CNTL1_G[0], sizeof(mmCM3_CM_RGAM_RAMB_END_CNTL1_G)/sizeof(mmCM3_CM_RGAM_RAMB_END_CNTL1_G[0]), 0, 0 }, + { "mmCM3_CM_RGAM_RAMB_END_CNTL2_G", REG_MMIO, 0x1068, 2, &mmCM3_CM_RGAM_RAMB_END_CNTL2_G[0], sizeof(mmCM3_CM_RGAM_RAMB_END_CNTL2_G)/sizeof(mmCM3_CM_RGAM_RAMB_END_CNTL2_G[0]), 0, 0 }, + { "mmCM3_CM_RGAM_RAMB_END_CNTL1_R", REG_MMIO, 0x1069, 2, &mmCM3_CM_RGAM_RAMB_END_CNTL1_R[0], sizeof(mmCM3_CM_RGAM_RAMB_END_CNTL1_R)/sizeof(mmCM3_CM_RGAM_RAMB_END_CNTL1_R[0]), 0, 0 }, + { "mmCM3_CM_RGAM_RAMB_END_CNTL2_R", REG_MMIO, 0x106a, 2, &mmCM3_CM_RGAM_RAMB_END_CNTL2_R[0], sizeof(mmCM3_CM_RGAM_RAMB_END_CNTL2_R)/sizeof(mmCM3_CM_RGAM_RAMB_END_CNTL2_R[0]), 0, 0 }, + { "mmCM3_CM_RGAM_RAMB_REGION_0_1", REG_MMIO, 0x106b, 2, &mmCM3_CM_RGAM_RAMB_REGION_0_1[0], sizeof(mmCM3_CM_RGAM_RAMB_REGION_0_1)/sizeof(mmCM3_CM_RGAM_RAMB_REGION_0_1[0]), 0, 0 }, + { "mmCM3_CM_RGAM_RAMB_REGION_2_3", REG_MMIO, 0x106c, 2, &mmCM3_CM_RGAM_RAMB_REGION_2_3[0], sizeof(mmCM3_CM_RGAM_RAMB_REGION_2_3)/sizeof(mmCM3_CM_RGAM_RAMB_REGION_2_3[0]), 0, 0 }, + { "mmCM3_CM_RGAM_RAMB_REGION_4_5", REG_MMIO, 0x106d, 2, &mmCM3_CM_RGAM_RAMB_REGION_4_5[0], sizeof(mmCM3_CM_RGAM_RAMB_REGION_4_5)/sizeof(mmCM3_CM_RGAM_RAMB_REGION_4_5[0]), 0, 0 }, + { "mmCM3_CM_RGAM_RAMB_REGION_6_7", REG_MMIO, 0x106e, 2, &mmCM3_CM_RGAM_RAMB_REGION_6_7[0], sizeof(mmCM3_CM_RGAM_RAMB_REGION_6_7)/sizeof(mmCM3_CM_RGAM_RAMB_REGION_6_7[0]), 0, 0 }, + { "mmCM3_CM_RGAM_RAMB_REGION_8_9", REG_MMIO, 0x106f, 2, &mmCM3_CM_RGAM_RAMB_REGION_8_9[0], sizeof(mmCM3_CM_RGAM_RAMB_REGION_8_9)/sizeof(mmCM3_CM_RGAM_RAMB_REGION_8_9[0]), 0, 0 }, + { "mmCM3_CM_RGAM_RAMB_REGION_10_11", REG_MMIO, 0x1070, 2, &mmCM3_CM_RGAM_RAMB_REGION_10_11[0], sizeof(mmCM3_CM_RGAM_RAMB_REGION_10_11)/sizeof(mmCM3_CM_RGAM_RAMB_REGION_10_11[0]), 0, 0 }, + { "mmCM3_CM_RGAM_RAMB_REGION_12_13", REG_MMIO, 0x1071, 2, &mmCM3_CM_RGAM_RAMB_REGION_12_13[0], sizeof(mmCM3_CM_RGAM_RAMB_REGION_12_13)/sizeof(mmCM3_CM_RGAM_RAMB_REGION_12_13[0]), 0, 0 }, + { "mmCM3_CM_RGAM_RAMB_REGION_14_15", REG_MMIO, 0x1072, 2, &mmCM3_CM_RGAM_RAMB_REGION_14_15[0], sizeof(mmCM3_CM_RGAM_RAMB_REGION_14_15)/sizeof(mmCM3_CM_RGAM_RAMB_REGION_14_15[0]), 0, 0 }, + { "mmCM3_CM_RGAM_RAMB_REGION_16_17", REG_MMIO, 0x1073, 2, &mmCM3_CM_RGAM_RAMB_REGION_16_17[0], sizeof(mmCM3_CM_RGAM_RAMB_REGION_16_17)/sizeof(mmCM3_CM_RGAM_RAMB_REGION_16_17[0]), 0, 0 }, + { "mmCM3_CM_RGAM_RAMB_REGION_18_19", REG_MMIO, 0x1074, 2, &mmCM3_CM_RGAM_RAMB_REGION_18_19[0], sizeof(mmCM3_CM_RGAM_RAMB_REGION_18_19)/sizeof(mmCM3_CM_RGAM_RAMB_REGION_18_19[0]), 0, 0 }, + { "mmCM3_CM_RGAM_RAMB_REGION_20_21", REG_MMIO, 0x1075, 2, &mmCM3_CM_RGAM_RAMB_REGION_20_21[0], sizeof(mmCM3_CM_RGAM_RAMB_REGION_20_21)/sizeof(mmCM3_CM_RGAM_RAMB_REGION_20_21[0]), 0, 0 }, + { "mmCM3_CM_RGAM_RAMB_REGION_22_23", REG_MMIO, 0x1076, 2, &mmCM3_CM_RGAM_RAMB_REGION_22_23[0], sizeof(mmCM3_CM_RGAM_RAMB_REGION_22_23)/sizeof(mmCM3_CM_RGAM_RAMB_REGION_22_23[0]), 0, 0 }, + { "mmCM3_CM_RGAM_RAMB_REGION_24_25", REG_MMIO, 0x1077, 2, &mmCM3_CM_RGAM_RAMB_REGION_24_25[0], sizeof(mmCM3_CM_RGAM_RAMB_REGION_24_25)/sizeof(mmCM3_CM_RGAM_RAMB_REGION_24_25[0]), 0, 0 }, + { "mmCM3_CM_RGAM_RAMB_REGION_26_27", REG_MMIO, 0x1078, 2, &mmCM3_CM_RGAM_RAMB_REGION_26_27[0], sizeof(mmCM3_CM_RGAM_RAMB_REGION_26_27)/sizeof(mmCM3_CM_RGAM_RAMB_REGION_26_27[0]), 0, 0 }, + { "mmCM3_CM_RGAM_RAMB_REGION_28_29", REG_MMIO, 0x1079, 2, &mmCM3_CM_RGAM_RAMB_REGION_28_29[0], sizeof(mmCM3_CM_RGAM_RAMB_REGION_28_29)/sizeof(mmCM3_CM_RGAM_RAMB_REGION_28_29[0]), 0, 0 }, + { "mmCM3_CM_RGAM_RAMB_REGION_30_31", REG_MMIO, 0x107a, 2, &mmCM3_CM_RGAM_RAMB_REGION_30_31[0], sizeof(mmCM3_CM_RGAM_RAMB_REGION_30_31)/sizeof(mmCM3_CM_RGAM_RAMB_REGION_30_31[0]), 0, 0 }, + { "mmCM3_CM_RGAM_RAMB_REGION_32_33", REG_MMIO, 0x107b, 2, &mmCM3_CM_RGAM_RAMB_REGION_32_33[0], sizeof(mmCM3_CM_RGAM_RAMB_REGION_32_33)/sizeof(mmCM3_CM_RGAM_RAMB_REGION_32_33[0]), 0, 0 }, + { "mmCM3_CM_HDR_MULT_COEF", REG_MMIO, 0x107c, 2, &mmCM3_CM_HDR_MULT_COEF[0], sizeof(mmCM3_CM_HDR_MULT_COEF)/sizeof(mmCM3_CM_HDR_MULT_COEF[0]), 0, 0 }, + { "mmCM3_CM_RANGE_CLAMP_CONTROL_R", REG_MMIO, 0x107d, 2, &mmCM3_CM_RANGE_CLAMP_CONTROL_R[0], sizeof(mmCM3_CM_RANGE_CLAMP_CONTROL_R)/sizeof(mmCM3_CM_RANGE_CLAMP_CONTROL_R[0]), 0, 0 }, + { "mmCM3_CM_RANGE_CLAMP_CONTROL_G", REG_MMIO, 0x107e, 2, &mmCM3_CM_RANGE_CLAMP_CONTROL_G[0], sizeof(mmCM3_CM_RANGE_CLAMP_CONTROL_G)/sizeof(mmCM3_CM_RANGE_CLAMP_CONTROL_G[0]), 0, 0 }, + { "mmCM3_CM_RANGE_CLAMP_CONTROL_B", REG_MMIO, 0x107f, 2, &mmCM3_CM_RANGE_CLAMP_CONTROL_B[0], sizeof(mmCM3_CM_RANGE_CLAMP_CONTROL_B)/sizeof(mmCM3_CM_RANGE_CLAMP_CONTROL_B[0]), 0, 0 }, + { "mmCM3_CM_DENORM_CONTROL", REG_MMIO, 0x1080, 2, &mmCM3_CM_DENORM_CONTROL[0], sizeof(mmCM3_CM_DENORM_CONTROL)/sizeof(mmCM3_CM_DENORM_CONTROL[0]), 0, 0 }, + { "mmCM3_CM_CMOUT_CONTROL", REG_MMIO, 0x1081, 2, &mmCM3_CM_CMOUT_CONTROL[0], sizeof(mmCM3_CM_CMOUT_CONTROL)/sizeof(mmCM3_CM_CMOUT_CONTROL[0]), 0, 0 }, + { "mmCM3_CM_CMOUT_RANDOM_SEEDS", REG_MMIO, 0x1082, 2, &mmCM3_CM_CMOUT_RANDOM_SEEDS[0], sizeof(mmCM3_CM_CMOUT_RANDOM_SEEDS)/sizeof(mmCM3_CM_CMOUT_RANDOM_SEEDS[0]), 0, 0 }, + { "mmCM3_CM_MEM_PWR_CTRL", REG_MMIO, 0x1083, 2, &mmCM3_CM_MEM_PWR_CTRL[0], sizeof(mmCM3_CM_MEM_PWR_CTRL)/sizeof(mmCM3_CM_MEM_PWR_CTRL[0]), 0, 0 }, + { "mmCM3_CM_MEM_PWR_STATUS", REG_MMIO, 0x1084, 2, &mmCM3_CM_MEM_PWR_STATUS[0], sizeof(mmCM3_CM_MEM_PWR_STATUS)/sizeof(mmCM3_CM_MEM_PWR_STATUS[0]), 0, 0 }, + { "mmDC_PERFMON15_PERFCOUNTER_CNTL", REG_MMIO, 0x109d, 2, &mmDC_PERFMON15_PERFCOUNTER_CNTL[0], sizeof(mmDC_PERFMON15_PERFCOUNTER_CNTL)/sizeof(mmDC_PERFMON15_PERFCOUNTER_CNTL[0]), 0, 0 }, + { "mmDC_PERFMON15_PERFCOUNTER_CNTL2", REG_MMIO, 0x109e, 2, &mmDC_PERFMON15_PERFCOUNTER_CNTL2[0], sizeof(mmDC_PERFMON15_PERFCOUNTER_CNTL2)/sizeof(mmDC_PERFMON15_PERFCOUNTER_CNTL2[0]), 0, 0 }, + { "mmDC_PERFMON15_PERFCOUNTER_STATE", REG_MMIO, 0x109f, 2, &mmDC_PERFMON15_PERFCOUNTER_STATE[0], sizeof(mmDC_PERFMON15_PERFCOUNTER_STATE)/sizeof(mmDC_PERFMON15_PERFCOUNTER_STATE[0]), 0, 0 }, + { "mmDC_PERFMON15_PERFMON_CNTL", REG_MMIO, 0x10a0, 2, &mmDC_PERFMON15_PERFMON_CNTL[0], sizeof(mmDC_PERFMON15_PERFMON_CNTL)/sizeof(mmDC_PERFMON15_PERFMON_CNTL[0]), 0, 0 }, + { "mmDC_PERFMON15_PERFMON_CNTL2", REG_MMIO, 0x10a1, 2, &mmDC_PERFMON15_PERFMON_CNTL2[0], sizeof(mmDC_PERFMON15_PERFMON_CNTL2)/sizeof(mmDC_PERFMON15_PERFMON_CNTL2[0]), 0, 0 }, + { "mmDC_PERFMON15_PERFMON_CVALUE_INT_MISC", REG_MMIO, 0x10a2, 2, &mmDC_PERFMON15_PERFMON_CVALUE_INT_MISC[0], sizeof(mmDC_PERFMON15_PERFMON_CVALUE_INT_MISC)/sizeof(mmDC_PERFMON15_PERFMON_CVALUE_INT_MISC[0]), 0, 0 }, + { "mmDC_PERFMON15_PERFMON_CVALUE_LOW", REG_MMIO, 0x10a3, 2, &mmDC_PERFMON15_PERFMON_CVALUE_LOW[0], sizeof(mmDC_PERFMON15_PERFMON_CVALUE_LOW)/sizeof(mmDC_PERFMON15_PERFMON_CVALUE_LOW[0]), 0, 0 }, + { "mmDC_PERFMON15_PERFMON_HI", REG_MMIO, 0x10a4, 2, &mmDC_PERFMON15_PERFMON_HI[0], sizeof(mmDC_PERFMON15_PERFMON_HI)/sizeof(mmDC_PERFMON15_PERFMON_HI[0]), 0, 0 }, + { "mmDC_PERFMON15_PERFMON_LOW", REG_MMIO, 0x10a5, 2, &mmDC_PERFMON15_PERFMON_LOW[0], sizeof(mmDC_PERFMON15_PERFMON_LOW)/sizeof(mmDC_PERFMON15_PERFMON_LOW[0]), 0, 0 }, + { "mmMPCC0_MPCC_TOP_SEL", REG_MMIO, 0x1630, 2, &mmMPCC0_MPCC_TOP_SEL[0], sizeof(mmMPCC0_MPCC_TOP_SEL)/sizeof(mmMPCC0_MPCC_TOP_SEL[0]), 0, 0 }, + { "mmMPCC0_MPCC_BOT_SEL", REG_MMIO, 0x1631, 2, &mmMPCC0_MPCC_BOT_SEL[0], sizeof(mmMPCC0_MPCC_BOT_SEL)/sizeof(mmMPCC0_MPCC_BOT_SEL[0]), 0, 0 }, + { "mmMPCC0_MPCC_OPP_ID", REG_MMIO, 0x1632, 2, &mmMPCC0_MPCC_OPP_ID[0], sizeof(mmMPCC0_MPCC_OPP_ID)/sizeof(mmMPCC0_MPCC_OPP_ID[0]), 0, 0 }, + { "mmMPCC0_MPCC_CONTROL", REG_MMIO, 0x1633, 2, &mmMPCC0_MPCC_CONTROL[0], sizeof(mmMPCC0_MPCC_CONTROL)/sizeof(mmMPCC0_MPCC_CONTROL[0]), 0, 0 }, + { "mmMPCC0_MPCC_SM_CONTROL", REG_MMIO, 0x1634, 2, &mmMPCC0_MPCC_SM_CONTROL[0], sizeof(mmMPCC0_MPCC_SM_CONTROL)/sizeof(mmMPCC0_MPCC_SM_CONTROL[0]), 0, 0 }, + { "mmMPCC0_MPCC_UPDATE_LOCK_SEL", REG_MMIO, 0x1635, 2, &mmMPCC0_MPCC_UPDATE_LOCK_SEL[0], sizeof(mmMPCC0_MPCC_UPDATE_LOCK_SEL)/sizeof(mmMPCC0_MPCC_UPDATE_LOCK_SEL[0]), 0, 0 }, + { "mmMPCC0_MPCC_TOP_OFFSET", REG_MMIO, 0x1636, 2, &mmMPCC0_MPCC_TOP_OFFSET[0], sizeof(mmMPCC0_MPCC_TOP_OFFSET)/sizeof(mmMPCC0_MPCC_TOP_OFFSET[0]), 0, 0 }, + { "mmMPCC0_MPCC_BOT_OFFSET", REG_MMIO, 0x1637, 2, &mmMPCC0_MPCC_BOT_OFFSET[0], sizeof(mmMPCC0_MPCC_BOT_OFFSET)/sizeof(mmMPCC0_MPCC_BOT_OFFSET[0]), 0, 0 }, + { "mmMPCC0_MPCC_OFFSET", REG_MMIO, 0x1638, 2, &mmMPCC0_MPCC_OFFSET[0], sizeof(mmMPCC0_MPCC_OFFSET)/sizeof(mmMPCC0_MPCC_OFFSET[0]), 0, 0 }, + { "mmMPCC0_MPCC_BG_R_CR", REG_MMIO, 0x1639, 2, &mmMPCC0_MPCC_BG_R_CR[0], sizeof(mmMPCC0_MPCC_BG_R_CR)/sizeof(mmMPCC0_MPCC_BG_R_CR[0]), 0, 0 }, + { "mmMPCC0_MPCC_BG_G_Y", REG_MMIO, 0x163a, 2, &mmMPCC0_MPCC_BG_G_Y[0], sizeof(mmMPCC0_MPCC_BG_G_Y)/sizeof(mmMPCC0_MPCC_BG_G_Y[0]), 0, 0 }, + { "mmMPCC0_MPCC_BG_B_CB", REG_MMIO, 0x163b, 2, &mmMPCC0_MPCC_BG_B_CB[0], sizeof(mmMPCC0_MPCC_BG_B_CB)/sizeof(mmMPCC0_MPCC_BG_B_CB[0]), 0, 0 }, + { "mmMPCC0_MPCC_STALL_STATUS", REG_MMIO, 0x163c, 2, &mmMPCC0_MPCC_STALL_STATUS[0], sizeof(mmMPCC0_MPCC_STALL_STATUS)/sizeof(mmMPCC0_MPCC_STALL_STATUS[0]), 0, 0 }, + { "mmMPCC0_MPCC_STATUS", REG_MMIO, 0x163d, 2, &mmMPCC0_MPCC_STATUS[0], sizeof(mmMPCC0_MPCC_STATUS)/sizeof(mmMPCC0_MPCC_STATUS[0]), 0, 0 }, + { "mmMPCC1_MPCC_TOP_SEL", REG_MMIO, 0x164b, 2, &mmMPCC1_MPCC_TOP_SEL[0], sizeof(mmMPCC1_MPCC_TOP_SEL)/sizeof(mmMPCC1_MPCC_TOP_SEL[0]), 0, 0 }, + { "mmMPCC1_MPCC_BOT_SEL", REG_MMIO, 0x164c, 2, &mmMPCC1_MPCC_BOT_SEL[0], sizeof(mmMPCC1_MPCC_BOT_SEL)/sizeof(mmMPCC1_MPCC_BOT_SEL[0]), 0, 0 }, + { "mmMPCC1_MPCC_OPP_ID", REG_MMIO, 0x164d, 2, &mmMPCC1_MPCC_OPP_ID[0], sizeof(mmMPCC1_MPCC_OPP_ID)/sizeof(mmMPCC1_MPCC_OPP_ID[0]), 0, 0 }, + { "mmMPCC1_MPCC_CONTROL", REG_MMIO, 0x164e, 2, &mmMPCC1_MPCC_CONTROL[0], sizeof(mmMPCC1_MPCC_CONTROL)/sizeof(mmMPCC1_MPCC_CONTROL[0]), 0, 0 }, + { "mmMPCC1_MPCC_SM_CONTROL", REG_MMIO, 0x164f, 2, &mmMPCC1_MPCC_SM_CONTROL[0], sizeof(mmMPCC1_MPCC_SM_CONTROL)/sizeof(mmMPCC1_MPCC_SM_CONTROL[0]), 0, 0 }, + { "mmMPCC1_MPCC_UPDATE_LOCK_SEL", REG_MMIO, 0x1650, 2, &mmMPCC1_MPCC_UPDATE_LOCK_SEL[0], sizeof(mmMPCC1_MPCC_UPDATE_LOCK_SEL)/sizeof(mmMPCC1_MPCC_UPDATE_LOCK_SEL[0]), 0, 0 }, + { "mmMPCC1_MPCC_TOP_OFFSET", REG_MMIO, 0x1651, 2, &mmMPCC1_MPCC_TOP_OFFSET[0], sizeof(mmMPCC1_MPCC_TOP_OFFSET)/sizeof(mmMPCC1_MPCC_TOP_OFFSET[0]), 0, 0 }, + { "mmMPCC1_MPCC_BOT_OFFSET", REG_MMIO, 0x1652, 2, &mmMPCC1_MPCC_BOT_OFFSET[0], sizeof(mmMPCC1_MPCC_BOT_OFFSET)/sizeof(mmMPCC1_MPCC_BOT_OFFSET[0]), 0, 0 }, + { "mmMPCC1_MPCC_OFFSET", REG_MMIO, 0x1653, 2, &mmMPCC1_MPCC_OFFSET[0], sizeof(mmMPCC1_MPCC_OFFSET)/sizeof(mmMPCC1_MPCC_OFFSET[0]), 0, 0 }, + { "mmMPCC1_MPCC_BG_R_CR", REG_MMIO, 0x1654, 2, &mmMPCC1_MPCC_BG_R_CR[0], sizeof(mmMPCC1_MPCC_BG_R_CR)/sizeof(mmMPCC1_MPCC_BG_R_CR[0]), 0, 0 }, + { "mmMPCC1_MPCC_BG_G_Y", REG_MMIO, 0x1655, 2, &mmMPCC1_MPCC_BG_G_Y[0], sizeof(mmMPCC1_MPCC_BG_G_Y)/sizeof(mmMPCC1_MPCC_BG_G_Y[0]), 0, 0 }, + { "mmMPCC1_MPCC_BG_B_CB", REG_MMIO, 0x1656, 2, &mmMPCC1_MPCC_BG_B_CB[0], sizeof(mmMPCC1_MPCC_BG_B_CB)/sizeof(mmMPCC1_MPCC_BG_B_CB[0]), 0, 0 }, + { "mmMPCC1_MPCC_STALL_STATUS", REG_MMIO, 0x1657, 2, &mmMPCC1_MPCC_STALL_STATUS[0], sizeof(mmMPCC1_MPCC_STALL_STATUS)/sizeof(mmMPCC1_MPCC_STALL_STATUS[0]), 0, 0 }, + { "mmMPCC1_MPCC_STATUS", REG_MMIO, 0x1658, 2, &mmMPCC1_MPCC_STATUS[0], sizeof(mmMPCC1_MPCC_STATUS)/sizeof(mmMPCC1_MPCC_STATUS[0]), 0, 0 }, + { "mmMPCC2_MPCC_TOP_SEL", REG_MMIO, 0x1666, 2, &mmMPCC2_MPCC_TOP_SEL[0], sizeof(mmMPCC2_MPCC_TOP_SEL)/sizeof(mmMPCC2_MPCC_TOP_SEL[0]), 0, 0 }, + { "mmMPCC2_MPCC_BOT_SEL", REG_MMIO, 0x1667, 2, &mmMPCC2_MPCC_BOT_SEL[0], sizeof(mmMPCC2_MPCC_BOT_SEL)/sizeof(mmMPCC2_MPCC_BOT_SEL[0]), 0, 0 }, + { "mmMPCC2_MPCC_OPP_ID", REG_MMIO, 0x1668, 2, &mmMPCC2_MPCC_OPP_ID[0], sizeof(mmMPCC2_MPCC_OPP_ID)/sizeof(mmMPCC2_MPCC_OPP_ID[0]), 0, 0 }, + { "mmMPCC2_MPCC_CONTROL", REG_MMIO, 0x1669, 2, &mmMPCC2_MPCC_CONTROL[0], sizeof(mmMPCC2_MPCC_CONTROL)/sizeof(mmMPCC2_MPCC_CONTROL[0]), 0, 0 }, + { "mmMPCC2_MPCC_SM_CONTROL", REG_MMIO, 0x166a, 2, &mmMPCC2_MPCC_SM_CONTROL[0], sizeof(mmMPCC2_MPCC_SM_CONTROL)/sizeof(mmMPCC2_MPCC_SM_CONTROL[0]), 0, 0 }, + { "mmMPCC2_MPCC_UPDATE_LOCK_SEL", REG_MMIO, 0x166b, 2, &mmMPCC2_MPCC_UPDATE_LOCK_SEL[0], sizeof(mmMPCC2_MPCC_UPDATE_LOCK_SEL)/sizeof(mmMPCC2_MPCC_UPDATE_LOCK_SEL[0]), 0, 0 }, + { "mmMPCC2_MPCC_TOP_OFFSET", REG_MMIO, 0x166c, 2, &mmMPCC2_MPCC_TOP_OFFSET[0], sizeof(mmMPCC2_MPCC_TOP_OFFSET)/sizeof(mmMPCC2_MPCC_TOP_OFFSET[0]), 0, 0 }, + { "mmMPCC2_MPCC_BOT_OFFSET", REG_MMIO, 0x166d, 2, &mmMPCC2_MPCC_BOT_OFFSET[0], sizeof(mmMPCC2_MPCC_BOT_OFFSET)/sizeof(mmMPCC2_MPCC_BOT_OFFSET[0]), 0, 0 }, + { "mmMPCC2_MPCC_OFFSET", REG_MMIO, 0x166e, 2, &mmMPCC2_MPCC_OFFSET[0], sizeof(mmMPCC2_MPCC_OFFSET)/sizeof(mmMPCC2_MPCC_OFFSET[0]), 0, 0 }, + { "mmMPCC2_MPCC_BG_R_CR", REG_MMIO, 0x166f, 2, &mmMPCC2_MPCC_BG_R_CR[0], sizeof(mmMPCC2_MPCC_BG_R_CR)/sizeof(mmMPCC2_MPCC_BG_R_CR[0]), 0, 0 }, + { "mmMPCC2_MPCC_BG_G_Y", REG_MMIO, 0x1670, 2, &mmMPCC2_MPCC_BG_G_Y[0], sizeof(mmMPCC2_MPCC_BG_G_Y)/sizeof(mmMPCC2_MPCC_BG_G_Y[0]), 0, 0 }, + { "mmMPCC2_MPCC_BG_B_CB", REG_MMIO, 0x1671, 2, &mmMPCC2_MPCC_BG_B_CB[0], sizeof(mmMPCC2_MPCC_BG_B_CB)/sizeof(mmMPCC2_MPCC_BG_B_CB[0]), 0, 0 }, + { "mmMPCC2_MPCC_STALL_STATUS", REG_MMIO, 0x1672, 2, &mmMPCC2_MPCC_STALL_STATUS[0], sizeof(mmMPCC2_MPCC_STALL_STATUS)/sizeof(mmMPCC2_MPCC_STALL_STATUS[0]), 0, 0 }, + { "mmMPCC2_MPCC_STATUS", REG_MMIO, 0x1673, 2, &mmMPCC2_MPCC_STATUS[0], sizeof(mmMPCC2_MPCC_STATUS)/sizeof(mmMPCC2_MPCC_STATUS[0]), 0, 0 }, + { "mmMPCC3_MPCC_TOP_SEL", REG_MMIO, 0x1681, 2, &mmMPCC3_MPCC_TOP_SEL[0], sizeof(mmMPCC3_MPCC_TOP_SEL)/sizeof(mmMPCC3_MPCC_TOP_SEL[0]), 0, 0 }, + { "mmMPCC3_MPCC_BOT_SEL", REG_MMIO, 0x1682, 2, &mmMPCC3_MPCC_BOT_SEL[0], sizeof(mmMPCC3_MPCC_BOT_SEL)/sizeof(mmMPCC3_MPCC_BOT_SEL[0]), 0, 0 }, + { "mmMPCC3_MPCC_OPP_ID", REG_MMIO, 0x1683, 2, &mmMPCC3_MPCC_OPP_ID[0], sizeof(mmMPCC3_MPCC_OPP_ID)/sizeof(mmMPCC3_MPCC_OPP_ID[0]), 0, 0 }, + { "mmMPCC3_MPCC_CONTROL", REG_MMIO, 0x1684, 2, &mmMPCC3_MPCC_CONTROL[0], sizeof(mmMPCC3_MPCC_CONTROL)/sizeof(mmMPCC3_MPCC_CONTROL[0]), 0, 0 }, + { "mmMPCC3_MPCC_SM_CONTROL", REG_MMIO, 0x1685, 2, &mmMPCC3_MPCC_SM_CONTROL[0], sizeof(mmMPCC3_MPCC_SM_CONTROL)/sizeof(mmMPCC3_MPCC_SM_CONTROL[0]), 0, 0 }, + { "mmMPCC3_MPCC_UPDATE_LOCK_SEL", REG_MMIO, 0x1686, 2, &mmMPCC3_MPCC_UPDATE_LOCK_SEL[0], sizeof(mmMPCC3_MPCC_UPDATE_LOCK_SEL)/sizeof(mmMPCC3_MPCC_UPDATE_LOCK_SEL[0]), 0, 0 }, + { "mmMPCC3_MPCC_TOP_OFFSET", REG_MMIO, 0x1687, 2, &mmMPCC3_MPCC_TOP_OFFSET[0], sizeof(mmMPCC3_MPCC_TOP_OFFSET)/sizeof(mmMPCC3_MPCC_TOP_OFFSET[0]), 0, 0 }, + { "mmMPCC3_MPCC_BOT_OFFSET", REG_MMIO, 0x1688, 2, &mmMPCC3_MPCC_BOT_OFFSET[0], sizeof(mmMPCC3_MPCC_BOT_OFFSET)/sizeof(mmMPCC3_MPCC_BOT_OFFSET[0]), 0, 0 }, + { "mmMPCC3_MPCC_OFFSET", REG_MMIO, 0x1689, 2, &mmMPCC3_MPCC_OFFSET[0], sizeof(mmMPCC3_MPCC_OFFSET)/sizeof(mmMPCC3_MPCC_OFFSET[0]), 0, 0 }, + { "mmMPCC3_MPCC_BG_R_CR", REG_MMIO, 0x168a, 2, &mmMPCC3_MPCC_BG_R_CR[0], sizeof(mmMPCC3_MPCC_BG_R_CR)/sizeof(mmMPCC3_MPCC_BG_R_CR[0]), 0, 0 }, + { "mmMPCC3_MPCC_BG_G_Y", REG_MMIO, 0x168b, 2, &mmMPCC3_MPCC_BG_G_Y[0], sizeof(mmMPCC3_MPCC_BG_G_Y)/sizeof(mmMPCC3_MPCC_BG_G_Y[0]), 0, 0 }, + { "mmMPCC3_MPCC_BG_B_CB", REG_MMIO, 0x168c, 2, &mmMPCC3_MPCC_BG_B_CB[0], sizeof(mmMPCC3_MPCC_BG_B_CB)/sizeof(mmMPCC3_MPCC_BG_B_CB[0]), 0, 0 }, + { "mmMPCC3_MPCC_STALL_STATUS", REG_MMIO, 0x168d, 2, &mmMPCC3_MPCC_STALL_STATUS[0], sizeof(mmMPCC3_MPCC_STALL_STATUS)/sizeof(mmMPCC3_MPCC_STALL_STATUS[0]), 0, 0 }, + { "mmMPCC3_MPCC_STATUS", REG_MMIO, 0x168e, 2, &mmMPCC3_MPCC_STATUS[0], sizeof(mmMPCC3_MPCC_STATUS)/sizeof(mmMPCC3_MPCC_STATUS[0]), 0, 0 }, + { "mmMPC_CLOCK_CONTROL", REG_MMIO, 0x1723, 2, &mmMPC_CLOCK_CONTROL[0], sizeof(mmMPC_CLOCK_CONTROL)/sizeof(mmMPC_CLOCK_CONTROL[0]), 0, 0 }, + { "mmMPC_SOFT_RESET", REG_MMIO, 0x1724, 2, &mmMPC_SOFT_RESET[0], sizeof(mmMPC_SOFT_RESET)/sizeof(mmMPC_SOFT_RESET[0]), 0, 0 }, + { "mmMPC_CRC_CTRL", REG_MMIO, 0x1725, 2, &mmMPC_CRC_CTRL[0], sizeof(mmMPC_CRC_CTRL)/sizeof(mmMPC_CRC_CTRL[0]), 0, 0 }, + { "mmMPC_CRC_SEL_CONTROL", REG_MMIO, 0x1726, 2, &mmMPC_CRC_SEL_CONTROL[0], sizeof(mmMPC_CRC_SEL_CONTROL)/sizeof(mmMPC_CRC_SEL_CONTROL[0]), 0, 0 }, + { "mmMPC_CRC_RESULT_AR", REG_MMIO, 0x1727, 2, &mmMPC_CRC_RESULT_AR[0], sizeof(mmMPC_CRC_RESULT_AR)/sizeof(mmMPC_CRC_RESULT_AR[0]), 0, 0 }, + { "mmMPC_CRC_RESULT_GB", REG_MMIO, 0x1728, 2, &mmMPC_CRC_RESULT_GB[0], sizeof(mmMPC_CRC_RESULT_GB)/sizeof(mmMPC_CRC_RESULT_GB[0]), 0, 0 }, + { "mmMPC_CRC_RESULT_C", REG_MMIO, 0x1729, 2, &mmMPC_CRC_RESULT_C[0], sizeof(mmMPC_CRC_RESULT_C)/sizeof(mmMPC_CRC_RESULT_C[0]), 0, 0 }, + { "mmMPC_PERFMON_EVENT_CTRL", REG_MMIO, 0x172c, 2, &mmMPC_PERFMON_EVENT_CTRL[0], sizeof(mmMPC_PERFMON_EVENT_CTRL)/sizeof(mmMPC_PERFMON_EVENT_CTRL[0]), 0, 0 }, + { "mmMPC_BYPASS_BG_AR", REG_MMIO, 0x172d, 2, &mmMPC_BYPASS_BG_AR[0], sizeof(mmMPC_BYPASS_BG_AR)/sizeof(mmMPC_BYPASS_BG_AR[0]), 0, 0 }, + { "mmMPC_BYPASS_BG_GB", REG_MMIO, 0x172e, 2, &mmMPC_BYPASS_BG_GB[0], sizeof(mmMPC_BYPASS_BG_GB)/sizeof(mmMPC_BYPASS_BG_GB[0]), 0, 0 }, + { "mmMPC_OUT0_MUX", REG_MMIO, 0x172f, 2, &mmMPC_OUT0_MUX[0], sizeof(mmMPC_OUT0_MUX)/sizeof(mmMPC_OUT0_MUX[0]), 0, 0 }, + { "mmMPC_OUT1_MUX", REG_MMIO, 0x1730, 2, &mmMPC_OUT1_MUX[0], sizeof(mmMPC_OUT1_MUX)/sizeof(mmMPC_OUT1_MUX[0]), 0, 0 }, + { "mmMPC_OUT2_MUX", REG_MMIO, 0x1731, 2, &mmMPC_OUT2_MUX[0], sizeof(mmMPC_OUT2_MUX)/sizeof(mmMPC_OUT2_MUX[0]), 0, 0 }, + { "mmMPC_OUT3_MUX", REG_MMIO, 0x1732, 2, &mmMPC_OUT3_MUX[0], sizeof(mmMPC_OUT3_MUX)/sizeof(mmMPC_OUT3_MUX[0]), 0, 0 }, + { "mmMPC_STALL_GRACE_WINDOW", REG_MMIO, 0x1756, 2, &mmMPC_STALL_GRACE_WINDOW[0], sizeof(mmMPC_STALL_GRACE_WINDOW)/sizeof(mmMPC_STALL_GRACE_WINDOW[0]), 0, 0 }, + { "mmADR_CFG_VUPDATE_LOCK_SET0", REG_MMIO, 0x175b, 2, &mmADR_CFG_VUPDATE_LOCK_SET0[0], sizeof(mmADR_CFG_VUPDATE_LOCK_SET0)/sizeof(mmADR_CFG_VUPDATE_LOCK_SET0[0]), 0, 0 }, + { "mmADR_VUPDATE_LOCK_SET0", REG_MMIO, 0x175c, 2, &mmADR_VUPDATE_LOCK_SET0[0], sizeof(mmADR_VUPDATE_LOCK_SET0)/sizeof(mmADR_VUPDATE_LOCK_SET0[0]), 0, 0 }, + { "mmCUR0_VUPDATE_LOCK_SET0", REG_MMIO, 0x175d, 2, &mmCUR0_VUPDATE_LOCK_SET0[0], sizeof(mmCUR0_VUPDATE_LOCK_SET0)/sizeof(mmCUR0_VUPDATE_LOCK_SET0[0]), 0, 0 }, + { "mmCUR1_VUPDATE_LOCK_SET0", REG_MMIO, 0x175e, 2, &mmCUR1_VUPDATE_LOCK_SET0[0], sizeof(mmCUR1_VUPDATE_LOCK_SET0)/sizeof(mmCUR1_VUPDATE_LOCK_SET0[0]), 0, 0 }, + { "mmADR_CFG_VUPDATE_LOCK_SET1", REG_MMIO, 0x175f, 2, &mmADR_CFG_VUPDATE_LOCK_SET1[0], sizeof(mmADR_CFG_VUPDATE_LOCK_SET1)/sizeof(mmADR_CFG_VUPDATE_LOCK_SET1[0]), 0, 0 }, + { "mmADR_VUPDATE_LOCK_SET1", REG_MMIO, 0x1760, 2, &mmADR_VUPDATE_LOCK_SET1[0], sizeof(mmADR_VUPDATE_LOCK_SET1)/sizeof(mmADR_VUPDATE_LOCK_SET1[0]), 0, 0 }, + { "mmCUR0_VUPDATE_LOCK_SET1", REG_MMIO, 0x1761, 2, &mmCUR0_VUPDATE_LOCK_SET1[0], sizeof(mmCUR0_VUPDATE_LOCK_SET1)/sizeof(mmCUR0_VUPDATE_LOCK_SET1[0]), 0, 0 }, + { "mmCUR1_VUPDATE_LOCK_SET1", REG_MMIO, 0x1762, 2, &mmCUR1_VUPDATE_LOCK_SET1[0], sizeof(mmCUR1_VUPDATE_LOCK_SET1)/sizeof(mmCUR1_VUPDATE_LOCK_SET1[0]), 0, 0 }, + { "mmADR_CFG_VUPDATE_LOCK_SET2", REG_MMIO, 0x1763, 2, &mmADR_CFG_VUPDATE_LOCK_SET2[0], sizeof(mmADR_CFG_VUPDATE_LOCK_SET2)/sizeof(mmADR_CFG_VUPDATE_LOCK_SET2[0]), 0, 0 }, + { "mmADR_VUPDATE_LOCK_SET2", REG_MMIO, 0x1764, 2, &mmADR_VUPDATE_LOCK_SET2[0], sizeof(mmADR_VUPDATE_LOCK_SET2)/sizeof(mmADR_VUPDATE_LOCK_SET2[0]), 0, 0 }, + { "mmCUR0_VUPDATE_LOCK_SET2", REG_MMIO, 0x1765, 2, &mmCUR0_VUPDATE_LOCK_SET2[0], sizeof(mmCUR0_VUPDATE_LOCK_SET2)/sizeof(mmCUR0_VUPDATE_LOCK_SET2[0]), 0, 0 }, + { "mmCUR1_VUPDATE_LOCK_SET2", REG_MMIO, 0x1766, 2, &mmCUR1_VUPDATE_LOCK_SET2[0], sizeof(mmCUR1_VUPDATE_LOCK_SET2)/sizeof(mmCUR1_VUPDATE_LOCK_SET2[0]), 0, 0 }, + { "mmADR_CFG_VUPDATE_LOCK_SET3", REG_MMIO, 0x1767, 2, &mmADR_CFG_VUPDATE_LOCK_SET3[0], sizeof(mmADR_CFG_VUPDATE_LOCK_SET3)/sizeof(mmADR_CFG_VUPDATE_LOCK_SET3[0]), 0, 0 }, + { "mmADR_VUPDATE_LOCK_SET3", REG_MMIO, 0x1768, 2, &mmADR_VUPDATE_LOCK_SET3[0], sizeof(mmADR_VUPDATE_LOCK_SET3)/sizeof(mmADR_VUPDATE_LOCK_SET3[0]), 0, 0 }, + { "mmCUR0_VUPDATE_LOCK_SET3", REG_MMIO, 0x1769, 2, &mmCUR0_VUPDATE_LOCK_SET3[0], sizeof(mmCUR0_VUPDATE_LOCK_SET3)/sizeof(mmCUR0_VUPDATE_LOCK_SET3[0]), 0, 0 }, + { "mmCUR1_VUPDATE_LOCK_SET3", REG_MMIO, 0x176a, 2, &mmCUR1_VUPDATE_LOCK_SET3[0], sizeof(mmCUR1_VUPDATE_LOCK_SET3)/sizeof(mmCUR1_VUPDATE_LOCK_SET3[0]), 0, 0 }, + { "mmDC_PERFMON16_PERFCOUNTER_CNTL", REG_MMIO, 0x17a4, 2, &mmDC_PERFMON16_PERFCOUNTER_CNTL[0], sizeof(mmDC_PERFMON16_PERFCOUNTER_CNTL)/sizeof(mmDC_PERFMON16_PERFCOUNTER_CNTL[0]), 0, 0 }, + { "mmDC_PERFMON16_PERFCOUNTER_CNTL2", REG_MMIO, 0x17a5, 2, &mmDC_PERFMON16_PERFCOUNTER_CNTL2[0], sizeof(mmDC_PERFMON16_PERFCOUNTER_CNTL2)/sizeof(mmDC_PERFMON16_PERFCOUNTER_CNTL2[0]), 0, 0 }, + { "mmDC_PERFMON16_PERFCOUNTER_STATE", REG_MMIO, 0x17a6, 2, &mmDC_PERFMON16_PERFCOUNTER_STATE[0], sizeof(mmDC_PERFMON16_PERFCOUNTER_STATE)/sizeof(mmDC_PERFMON16_PERFCOUNTER_STATE[0]), 0, 0 }, + { "mmDC_PERFMON16_PERFMON_CNTL", REG_MMIO, 0x17a7, 2, &mmDC_PERFMON16_PERFMON_CNTL[0], sizeof(mmDC_PERFMON16_PERFMON_CNTL)/sizeof(mmDC_PERFMON16_PERFMON_CNTL[0]), 0, 0 }, + { "mmDC_PERFMON16_PERFMON_CNTL2", REG_MMIO, 0x17a8, 2, &mmDC_PERFMON16_PERFMON_CNTL2[0], sizeof(mmDC_PERFMON16_PERFMON_CNTL2)/sizeof(mmDC_PERFMON16_PERFMON_CNTL2[0]), 0, 0 }, + { "mmDC_PERFMON16_PERFMON_CVALUE_INT_MISC", REG_MMIO, 0x17a9, 2, &mmDC_PERFMON16_PERFMON_CVALUE_INT_MISC[0], sizeof(mmDC_PERFMON16_PERFMON_CVALUE_INT_MISC)/sizeof(mmDC_PERFMON16_PERFMON_CVALUE_INT_MISC[0]), 0, 0 }, + { "mmDC_PERFMON16_PERFMON_CVALUE_LOW", REG_MMIO, 0x17aa, 2, &mmDC_PERFMON16_PERFMON_CVALUE_LOW[0], sizeof(mmDC_PERFMON16_PERFMON_CVALUE_LOW)/sizeof(mmDC_PERFMON16_PERFMON_CVALUE_LOW[0]), 0, 0 }, + { "mmDC_PERFMON16_PERFMON_HI", REG_MMIO, 0x17ab, 2, &mmDC_PERFMON16_PERFMON_HI[0], sizeof(mmDC_PERFMON16_PERFMON_HI)/sizeof(mmDC_PERFMON16_PERFMON_HI[0]), 0, 0 }, + { "mmDC_PERFMON16_PERFMON_LOW", REG_MMIO, 0x17ac, 2, &mmDC_PERFMON16_PERFMON_LOW[0], sizeof(mmDC_PERFMON16_PERFMON_LOW)/sizeof(mmDC_PERFMON16_PERFMON_LOW[0]), 0, 0 }, + { "mmABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL", REG_MMIO, 0x17b0, 2, &mmABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL[0], sizeof(mmABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL)/sizeof(mmABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL[0]), 0, 0 }, + { "mmABM0_BL1_PWM_USER_LEVEL", REG_MMIO, 0x17b1, 2, &mmABM0_BL1_PWM_USER_LEVEL[0], sizeof(mmABM0_BL1_PWM_USER_LEVEL)/sizeof(mmABM0_BL1_PWM_USER_LEVEL[0]), 0, 0 }, + { "mmABM0_BL1_PWM_TARGET_ABM_LEVEL", REG_MMIO, 0x17b2, 2, &mmABM0_BL1_PWM_TARGET_ABM_LEVEL[0], sizeof(mmABM0_BL1_PWM_TARGET_ABM_LEVEL)/sizeof(mmABM0_BL1_PWM_TARGET_ABM_LEVEL[0]), 0, 0 }, + { "mmABM0_BL1_PWM_CURRENT_ABM_LEVEL", REG_MMIO, 0x17b3, 2, &mmABM0_BL1_PWM_CURRENT_ABM_LEVEL[0], sizeof(mmABM0_BL1_PWM_CURRENT_ABM_LEVEL)/sizeof(mmABM0_BL1_PWM_CURRENT_ABM_LEVEL[0]), 0, 0 }, + { "mmABM0_BL1_PWM_FINAL_DUTY_CYCLE", REG_MMIO, 0x17b4, 2, &mmABM0_BL1_PWM_FINAL_DUTY_CYCLE[0], sizeof(mmABM0_BL1_PWM_FINAL_DUTY_CYCLE)/sizeof(mmABM0_BL1_PWM_FINAL_DUTY_CYCLE[0]), 0, 0 }, + { "mmABM0_BL1_PWM_MINIMUM_DUTY_CYCLE", REG_MMIO, 0x17b5, 2, &mmABM0_BL1_PWM_MINIMUM_DUTY_CYCLE[0], sizeof(mmABM0_BL1_PWM_MINIMUM_DUTY_CYCLE)/sizeof(mmABM0_BL1_PWM_MINIMUM_DUTY_CYCLE[0]), 0, 0 }, + { "mmABM0_BL1_PWM_ABM_CNTL", REG_MMIO, 0x17b6, 2, &mmABM0_BL1_PWM_ABM_CNTL[0], sizeof(mmABM0_BL1_PWM_ABM_CNTL)/sizeof(mmABM0_BL1_PWM_ABM_CNTL[0]), 0, 0 }, + { "mmABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE", REG_MMIO, 0x17b7, 2, &mmABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE[0], sizeof(mmABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE)/sizeof(mmABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE[0]), 0, 0 }, + { "mmABM0_BL1_PWM_GRP2_REG_LOCK", REG_MMIO, 0x17b8, 2, &mmABM0_BL1_PWM_GRP2_REG_LOCK[0], sizeof(mmABM0_BL1_PWM_GRP2_REG_LOCK)/sizeof(mmABM0_BL1_PWM_GRP2_REG_LOCK[0]), 0, 0 }, + { "mmABM0_DC_ABM1_CNTL", REG_MMIO, 0x17b9, 2, &mmABM0_DC_ABM1_CNTL[0], sizeof(mmABM0_DC_ABM1_CNTL)/sizeof(mmABM0_DC_ABM1_CNTL[0]), 0, 0 }, + { "mmABM0_DC_ABM1_IPCSC_COEFF_SEL", REG_MMIO, 0x17ba, 2, &mmABM0_DC_ABM1_IPCSC_COEFF_SEL[0], sizeof(mmABM0_DC_ABM1_IPCSC_COEFF_SEL)/sizeof(mmABM0_DC_ABM1_IPCSC_COEFF_SEL[0]), 0, 0 }, + { "mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_0", REG_MMIO, 0x17bb, 2, &mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_0[0], sizeof(mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_0)/sizeof(mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_0[0]), 0, 0 }, + { "mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_1", REG_MMIO, 0x17bc, 2, &mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_1[0], sizeof(mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_1)/sizeof(mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_1[0]), 0, 0 }, + { "mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_2", REG_MMIO, 0x17bd, 2, &mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_2[0], sizeof(mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_2)/sizeof(mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_2[0]), 0, 0 }, + { "mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_3", REG_MMIO, 0x17be, 2, &mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_3[0], sizeof(mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_3)/sizeof(mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_3[0]), 0, 0 }, + { "mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_4", REG_MMIO, 0x17bf, 2, &mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_4[0], sizeof(mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_4)/sizeof(mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_4[0]), 0, 0 }, + { "mmABM0_DC_ABM1_ACE_THRES_12", REG_MMIO, 0x17c0, 2, &mmABM0_DC_ABM1_ACE_THRES_12[0], sizeof(mmABM0_DC_ABM1_ACE_THRES_12)/sizeof(mmABM0_DC_ABM1_ACE_THRES_12[0]), 0, 0 }, + { "mmABM0_DC_ABM1_ACE_THRES_34", REG_MMIO, 0x17c1, 2, &mmABM0_DC_ABM1_ACE_THRES_34[0], sizeof(mmABM0_DC_ABM1_ACE_THRES_34)/sizeof(mmABM0_DC_ABM1_ACE_THRES_34[0]), 0, 0 }, + { "mmABM0_DC_ABM1_ACE_CNTL_MISC", REG_MMIO, 0x17c2, 2, &mmABM0_DC_ABM1_ACE_CNTL_MISC[0], sizeof(mmABM0_DC_ABM1_ACE_CNTL_MISC)/sizeof(mmABM0_DC_ABM1_ACE_CNTL_MISC[0]), 0, 0 }, + { "mmABM0_DC_ABM1_HGLS_REG_READ_PROGRESS", REG_MMIO, 0x17c4, 2, &mmABM0_DC_ABM1_HGLS_REG_READ_PROGRESS[0], sizeof(mmABM0_DC_ABM1_HGLS_REG_READ_PROGRESS)/sizeof(mmABM0_DC_ABM1_HGLS_REG_READ_PROGRESS[0]), 0, 0 }, + { "mmABM0_DC_ABM1_HG_MISC_CTRL", REG_MMIO, 0x17c5, 2, &mmABM0_DC_ABM1_HG_MISC_CTRL[0], sizeof(mmABM0_DC_ABM1_HG_MISC_CTRL)/sizeof(mmABM0_DC_ABM1_HG_MISC_CTRL[0]), 0, 0 }, + { "mmABM0_DC_ABM1_LS_SUM_OF_LUMA", REG_MMIO, 0x17c6, 2, &mmABM0_DC_ABM1_LS_SUM_OF_LUMA[0], sizeof(mmABM0_DC_ABM1_LS_SUM_OF_LUMA)/sizeof(mmABM0_DC_ABM1_LS_SUM_OF_LUMA[0]), 0, 0 }, + { "mmABM0_DC_ABM1_LS_MIN_MAX_LUMA", REG_MMIO, 0x17c7, 2, &mmABM0_DC_ABM1_LS_MIN_MAX_LUMA[0], sizeof(mmABM0_DC_ABM1_LS_MIN_MAX_LUMA)/sizeof(mmABM0_DC_ABM1_LS_MIN_MAX_LUMA[0]), 0, 0 }, + { "mmABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA", REG_MMIO, 0x17c8, 2, &mmABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA[0], sizeof(mmABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA)/sizeof(mmABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA[0]), 0, 0 }, + { "mmABM0_DC_ABM1_LS_PIXEL_COUNT", REG_MMIO, 0x17c9, 2, &mmABM0_DC_ABM1_LS_PIXEL_COUNT[0], sizeof(mmABM0_DC_ABM1_LS_PIXEL_COUNT)/sizeof(mmABM0_DC_ABM1_LS_PIXEL_COUNT[0]), 0, 0 }, + { "mmABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES", REG_MMIO, 0x17ca, 2, &mmABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES[0], sizeof(mmABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES)/sizeof(mmABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES[0]), 0, 0 }, + { "mmABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT", REG_MMIO, 0x17cb, 2, &mmABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT[0], sizeof(mmABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT)/sizeof(mmABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT[0]), 0, 0 }, + { "mmABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT", REG_MMIO, 0x17cc, 2, &mmABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT[0], sizeof(mmABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT)/sizeof(mmABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT[0]), 0, 0 }, + { "mmABM0_DC_ABM1_HG_SAMPLE_RATE", REG_MMIO, 0x17cd, 2, &mmABM0_DC_ABM1_HG_SAMPLE_RATE[0], sizeof(mmABM0_DC_ABM1_HG_SAMPLE_RATE)/sizeof(mmABM0_DC_ABM1_HG_SAMPLE_RATE[0]), 0, 0 }, + { "mmABM0_DC_ABM1_LS_SAMPLE_RATE", REG_MMIO, 0x17ce, 2, &mmABM0_DC_ABM1_LS_SAMPLE_RATE[0], sizeof(mmABM0_DC_ABM1_LS_SAMPLE_RATE)/sizeof(mmABM0_DC_ABM1_LS_SAMPLE_RATE[0]), 0, 0 }, + { "mmABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG", REG_MMIO, 0x17cf, 2, &mmABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG[0], sizeof(mmABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG)/sizeof(mmABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG[0]), 0, 0 }, + { "mmABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX", REG_MMIO, 0x17d0, 2, &mmABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX[0], sizeof(mmABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX)/sizeof(mmABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX[0]), 0, 0 }, + { "mmABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX", REG_MMIO, 0x17d1, 2, &mmABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX[0], sizeof(mmABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX)/sizeof(mmABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX[0]), 0, 0 }, + { "mmABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX", REG_MMIO, 0x17d2, 2, &mmABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX[0], sizeof(mmABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX)/sizeof(mmABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX[0]), 0, 0 }, + { "mmABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX", REG_MMIO, 0x17d3, 2, &mmABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX[0], sizeof(mmABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX)/sizeof(mmABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX[0]), 0, 0 }, + { "mmABM0_DC_ABM1_HG_RESULT_1", REG_MMIO, 0x17d4, 2, &mmABM0_DC_ABM1_HG_RESULT_1[0], sizeof(mmABM0_DC_ABM1_HG_RESULT_1)/sizeof(mmABM0_DC_ABM1_HG_RESULT_1[0]), 0, 0 }, + { "mmABM0_DC_ABM1_HG_RESULT_2", REG_MMIO, 0x17d5, 2, &mmABM0_DC_ABM1_HG_RESULT_2[0], sizeof(mmABM0_DC_ABM1_HG_RESULT_2)/sizeof(mmABM0_DC_ABM1_HG_RESULT_2[0]), 0, 0 }, + { "mmABM0_DC_ABM1_HG_RESULT_3", REG_MMIO, 0x17d6, 2, &mmABM0_DC_ABM1_HG_RESULT_3[0], sizeof(mmABM0_DC_ABM1_HG_RESULT_3)/sizeof(mmABM0_DC_ABM1_HG_RESULT_3[0]), 0, 0 }, + { "mmABM0_DC_ABM1_HG_RESULT_4", REG_MMIO, 0x17d7, 2, &mmABM0_DC_ABM1_HG_RESULT_4[0], sizeof(mmABM0_DC_ABM1_HG_RESULT_4)/sizeof(mmABM0_DC_ABM1_HG_RESULT_4[0]), 0, 0 }, + { "mmABM0_DC_ABM1_HG_RESULT_5", REG_MMIO, 0x17d8, 2, &mmABM0_DC_ABM1_HG_RESULT_5[0], sizeof(mmABM0_DC_ABM1_HG_RESULT_5)/sizeof(mmABM0_DC_ABM1_HG_RESULT_5[0]), 0, 0 }, + { "mmABM0_DC_ABM1_HG_RESULT_6", REG_MMIO, 0x17d9, 2, &mmABM0_DC_ABM1_HG_RESULT_6[0], sizeof(mmABM0_DC_ABM1_HG_RESULT_6)/sizeof(mmABM0_DC_ABM1_HG_RESULT_6[0]), 0, 0 }, + { "mmABM0_DC_ABM1_HG_RESULT_7", REG_MMIO, 0x17da, 2, &mmABM0_DC_ABM1_HG_RESULT_7[0], sizeof(mmABM0_DC_ABM1_HG_RESULT_7)/sizeof(mmABM0_DC_ABM1_HG_RESULT_7[0]), 0, 0 }, + { "mmABM0_DC_ABM1_HG_RESULT_8", REG_MMIO, 0x17db, 2, &mmABM0_DC_ABM1_HG_RESULT_8[0], sizeof(mmABM0_DC_ABM1_HG_RESULT_8)/sizeof(mmABM0_DC_ABM1_HG_RESULT_8[0]), 0, 0 }, + { "mmABM0_DC_ABM1_HG_RESULT_9", REG_MMIO, 0x17dc, 2, &mmABM0_DC_ABM1_HG_RESULT_9[0], sizeof(mmABM0_DC_ABM1_HG_RESULT_9)/sizeof(mmABM0_DC_ABM1_HG_RESULT_9[0]), 0, 0 }, + { "mmABM0_DC_ABM1_HG_RESULT_10", REG_MMIO, 0x17dd, 2, &mmABM0_DC_ABM1_HG_RESULT_10[0], sizeof(mmABM0_DC_ABM1_HG_RESULT_10)/sizeof(mmABM0_DC_ABM1_HG_RESULT_10[0]), 0, 0 }, + { "mmABM0_DC_ABM1_HG_RESULT_11", REG_MMIO, 0x17de, 2, &mmABM0_DC_ABM1_HG_RESULT_11[0], sizeof(mmABM0_DC_ABM1_HG_RESULT_11)/sizeof(mmABM0_DC_ABM1_HG_RESULT_11[0]), 0, 0 }, + { "mmABM0_DC_ABM1_HG_RESULT_12", REG_MMIO, 0x17df, 2, &mmABM0_DC_ABM1_HG_RESULT_12[0], sizeof(mmABM0_DC_ABM1_HG_RESULT_12)/sizeof(mmABM0_DC_ABM1_HG_RESULT_12[0]), 0, 0 }, + { "mmABM0_DC_ABM1_HG_RESULT_13", REG_MMIO, 0x17e0, 2, &mmABM0_DC_ABM1_HG_RESULT_13[0], sizeof(mmABM0_DC_ABM1_HG_RESULT_13)/sizeof(mmABM0_DC_ABM1_HG_RESULT_13[0]), 0, 0 }, + { "mmABM0_DC_ABM1_HG_RESULT_14", REG_MMIO, 0x17e1, 2, &mmABM0_DC_ABM1_HG_RESULT_14[0], sizeof(mmABM0_DC_ABM1_HG_RESULT_14)/sizeof(mmABM0_DC_ABM1_HG_RESULT_14[0]), 0, 0 }, + { "mmABM0_DC_ABM1_HG_RESULT_15", REG_MMIO, 0x17e2, 2, &mmABM0_DC_ABM1_HG_RESULT_15[0], sizeof(mmABM0_DC_ABM1_HG_RESULT_15)/sizeof(mmABM0_DC_ABM1_HG_RESULT_15[0]), 0, 0 }, + { "mmABM0_DC_ABM1_HG_RESULT_16", REG_MMIO, 0x17e3, 2, &mmABM0_DC_ABM1_HG_RESULT_16[0], sizeof(mmABM0_DC_ABM1_HG_RESULT_16)/sizeof(mmABM0_DC_ABM1_HG_RESULT_16[0]), 0, 0 }, + { "mmABM0_DC_ABM1_HG_RESULT_17", REG_MMIO, 0x17e4, 2, &mmABM0_DC_ABM1_HG_RESULT_17[0], sizeof(mmABM0_DC_ABM1_HG_RESULT_17)/sizeof(mmABM0_DC_ABM1_HG_RESULT_17[0]), 0, 0 }, + { "mmABM0_DC_ABM1_HG_RESULT_18", REG_MMIO, 0x17e5, 2, &mmABM0_DC_ABM1_HG_RESULT_18[0], sizeof(mmABM0_DC_ABM1_HG_RESULT_18)/sizeof(mmABM0_DC_ABM1_HG_RESULT_18[0]), 0, 0 }, + { "mmABM0_DC_ABM1_HG_RESULT_19", REG_MMIO, 0x17e6, 2, &mmABM0_DC_ABM1_HG_RESULT_19[0], sizeof(mmABM0_DC_ABM1_HG_RESULT_19)/sizeof(mmABM0_DC_ABM1_HG_RESULT_19[0]), 0, 0 }, + { "mmABM0_DC_ABM1_HG_RESULT_20", REG_MMIO, 0x17e7, 2, &mmABM0_DC_ABM1_HG_RESULT_20[0], sizeof(mmABM0_DC_ABM1_HG_RESULT_20)/sizeof(mmABM0_DC_ABM1_HG_RESULT_20[0]), 0, 0 }, + { "mmABM0_DC_ABM1_HG_RESULT_21", REG_MMIO, 0x17e8, 2, &mmABM0_DC_ABM1_HG_RESULT_21[0], sizeof(mmABM0_DC_ABM1_HG_RESULT_21)/sizeof(mmABM0_DC_ABM1_HG_RESULT_21[0]), 0, 0 }, + { "mmABM0_DC_ABM1_HG_RESULT_22", REG_MMIO, 0x17e9, 2, &mmABM0_DC_ABM1_HG_RESULT_22[0], sizeof(mmABM0_DC_ABM1_HG_RESULT_22)/sizeof(mmABM0_DC_ABM1_HG_RESULT_22[0]), 0, 0 }, + { "mmABM0_DC_ABM1_HG_RESULT_23", REG_MMIO, 0x17ea, 2, &mmABM0_DC_ABM1_HG_RESULT_23[0], sizeof(mmABM0_DC_ABM1_HG_RESULT_23)/sizeof(mmABM0_DC_ABM1_HG_RESULT_23[0]), 0, 0 }, + { "mmABM0_DC_ABM1_HG_RESULT_24", REG_MMIO, 0x17eb, 2, &mmABM0_DC_ABM1_HG_RESULT_24[0], sizeof(mmABM0_DC_ABM1_HG_RESULT_24)/sizeof(mmABM0_DC_ABM1_HG_RESULT_24[0]), 0, 0 }, + { "mmABM0_DC_ABM1_BL_MASTER_LOCK", REG_MMIO, 0x17ec, 2, &mmABM0_DC_ABM1_BL_MASTER_LOCK[0], sizeof(mmABM0_DC_ABM1_BL_MASTER_LOCK)/sizeof(mmABM0_DC_ABM1_BL_MASTER_LOCK[0]), 0, 0 }, + { "mmABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL", REG_MMIO, 0x17f6, 2, &mmABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL[0], sizeof(mmABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL)/sizeof(mmABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL[0]), 0, 0 }, + { "mmABM1_BL1_PWM_USER_LEVEL", REG_MMIO, 0x17f7, 2, &mmABM1_BL1_PWM_USER_LEVEL[0], sizeof(mmABM1_BL1_PWM_USER_LEVEL)/sizeof(mmABM1_BL1_PWM_USER_LEVEL[0]), 0, 0 }, + { "mmABM1_BL1_PWM_TARGET_ABM_LEVEL", REG_MMIO, 0x17f8, 2, &mmABM1_BL1_PWM_TARGET_ABM_LEVEL[0], sizeof(mmABM1_BL1_PWM_TARGET_ABM_LEVEL)/sizeof(mmABM1_BL1_PWM_TARGET_ABM_LEVEL[0]), 0, 0 }, + { "mmABM1_BL1_PWM_CURRENT_ABM_LEVEL", REG_MMIO, 0x17f9, 2, &mmABM1_BL1_PWM_CURRENT_ABM_LEVEL[0], sizeof(mmABM1_BL1_PWM_CURRENT_ABM_LEVEL)/sizeof(mmABM1_BL1_PWM_CURRENT_ABM_LEVEL[0]), 0, 0 }, + { "mmABM1_BL1_PWM_FINAL_DUTY_CYCLE", REG_MMIO, 0x17fa, 2, &mmABM1_BL1_PWM_FINAL_DUTY_CYCLE[0], sizeof(mmABM1_BL1_PWM_FINAL_DUTY_CYCLE)/sizeof(mmABM1_BL1_PWM_FINAL_DUTY_CYCLE[0]), 0, 0 }, + { "mmABM1_BL1_PWM_MINIMUM_DUTY_CYCLE", REG_MMIO, 0x17fb, 2, &mmABM1_BL1_PWM_MINIMUM_DUTY_CYCLE[0], sizeof(mmABM1_BL1_PWM_MINIMUM_DUTY_CYCLE)/sizeof(mmABM1_BL1_PWM_MINIMUM_DUTY_CYCLE[0]), 0, 0 }, + { "mmABM1_BL1_PWM_ABM_CNTL", REG_MMIO, 0x17fc, 2, &mmABM1_BL1_PWM_ABM_CNTL[0], sizeof(mmABM1_BL1_PWM_ABM_CNTL)/sizeof(mmABM1_BL1_PWM_ABM_CNTL[0]), 0, 0 }, + { "mmABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE", REG_MMIO, 0x17fd, 2, &mmABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE[0], sizeof(mmABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE)/sizeof(mmABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE[0]), 0, 0 }, + { "mmABM1_BL1_PWM_GRP2_REG_LOCK", REG_MMIO, 0x17fe, 2, &mmABM1_BL1_PWM_GRP2_REG_LOCK[0], sizeof(mmABM1_BL1_PWM_GRP2_REG_LOCK)/sizeof(mmABM1_BL1_PWM_GRP2_REG_LOCK[0]), 0, 0 }, + { "mmABM1_DC_ABM1_CNTL", REG_MMIO, 0x17ff, 2, &mmABM1_DC_ABM1_CNTL[0], sizeof(mmABM1_DC_ABM1_CNTL)/sizeof(mmABM1_DC_ABM1_CNTL[0]), 0, 0 }, + { "mmABM1_DC_ABM1_IPCSC_COEFF_SEL", REG_MMIO, 0x1800, 2, &mmABM1_DC_ABM1_IPCSC_COEFF_SEL[0], sizeof(mmABM1_DC_ABM1_IPCSC_COEFF_SEL)/sizeof(mmABM1_DC_ABM1_IPCSC_COEFF_SEL[0]), 0, 0 }, + { "mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_0", REG_MMIO, 0x1801, 2, &mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_0[0], sizeof(mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_0)/sizeof(mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_0[0]), 0, 0 }, + { "mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_1", REG_MMIO, 0x1802, 2, &mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_1[0], sizeof(mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_1)/sizeof(mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_1[0]), 0, 0 }, + { "mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_2", REG_MMIO, 0x1803, 2, &mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_2[0], sizeof(mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_2)/sizeof(mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_2[0]), 0, 0 }, + { "mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_3", REG_MMIO, 0x1804, 2, &mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_3[0], sizeof(mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_3)/sizeof(mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_3[0]), 0, 0 }, + { "mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_4", REG_MMIO, 0x1805, 2, &mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_4[0], sizeof(mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_4)/sizeof(mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_4[0]), 0, 0 }, + { "mmABM1_DC_ABM1_ACE_THRES_12", REG_MMIO, 0x1806, 2, &mmABM1_DC_ABM1_ACE_THRES_12[0], sizeof(mmABM1_DC_ABM1_ACE_THRES_12)/sizeof(mmABM1_DC_ABM1_ACE_THRES_12[0]), 0, 0 }, + { "mmABM1_DC_ABM1_ACE_THRES_34", REG_MMIO, 0x1807, 2, &mmABM1_DC_ABM1_ACE_THRES_34[0], sizeof(mmABM1_DC_ABM1_ACE_THRES_34)/sizeof(mmABM1_DC_ABM1_ACE_THRES_34[0]), 0, 0 }, + { "mmABM1_DC_ABM1_ACE_CNTL_MISC", REG_MMIO, 0x1808, 2, &mmABM1_DC_ABM1_ACE_CNTL_MISC[0], sizeof(mmABM1_DC_ABM1_ACE_CNTL_MISC)/sizeof(mmABM1_DC_ABM1_ACE_CNTL_MISC[0]), 0, 0 }, + { "mmABM1_DC_ABM1_HGLS_REG_READ_PROGRESS", REG_MMIO, 0x180a, 2, &mmABM1_DC_ABM1_HGLS_REG_READ_PROGRESS[0], sizeof(mmABM1_DC_ABM1_HGLS_REG_READ_PROGRESS)/sizeof(mmABM1_DC_ABM1_HGLS_REG_READ_PROGRESS[0]), 0, 0 }, + { "mmABM1_DC_ABM1_HG_MISC_CTRL", REG_MMIO, 0x180b, 2, &mmABM1_DC_ABM1_HG_MISC_CTRL[0], sizeof(mmABM1_DC_ABM1_HG_MISC_CTRL)/sizeof(mmABM1_DC_ABM1_HG_MISC_CTRL[0]), 0, 0 }, + { "mmABM1_DC_ABM1_LS_SUM_OF_LUMA", REG_MMIO, 0x180c, 2, &mmABM1_DC_ABM1_LS_SUM_OF_LUMA[0], sizeof(mmABM1_DC_ABM1_LS_SUM_OF_LUMA)/sizeof(mmABM1_DC_ABM1_LS_SUM_OF_LUMA[0]), 0, 0 }, + { "mmABM1_DC_ABM1_LS_MIN_MAX_LUMA", REG_MMIO, 0x180d, 2, &mmABM1_DC_ABM1_LS_MIN_MAX_LUMA[0], sizeof(mmABM1_DC_ABM1_LS_MIN_MAX_LUMA)/sizeof(mmABM1_DC_ABM1_LS_MIN_MAX_LUMA[0]), 0, 0 }, + { "mmABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA", REG_MMIO, 0x180e, 2, &mmABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA[0], sizeof(mmABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA)/sizeof(mmABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA[0]), 0, 0 }, + { "mmABM1_DC_ABM1_LS_PIXEL_COUNT", REG_MMIO, 0x180f, 2, &mmABM1_DC_ABM1_LS_PIXEL_COUNT[0], sizeof(mmABM1_DC_ABM1_LS_PIXEL_COUNT)/sizeof(mmABM1_DC_ABM1_LS_PIXEL_COUNT[0]), 0, 0 }, + { "mmABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES", REG_MMIO, 0x1810, 2, &mmABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES[0], sizeof(mmABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES)/sizeof(mmABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES[0]), 0, 0 }, + { "mmABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT", REG_MMIO, 0x1811, 2, &mmABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT[0], sizeof(mmABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT)/sizeof(mmABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT[0]), 0, 0 }, + { "mmABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT", REG_MMIO, 0x1812, 2, &mmABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT[0], sizeof(mmABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT)/sizeof(mmABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT[0]), 0, 0 }, + { "mmABM1_DC_ABM1_HG_SAMPLE_RATE", REG_MMIO, 0x1813, 2, &mmABM1_DC_ABM1_HG_SAMPLE_RATE[0], sizeof(mmABM1_DC_ABM1_HG_SAMPLE_RATE)/sizeof(mmABM1_DC_ABM1_HG_SAMPLE_RATE[0]), 0, 0 }, + { "mmABM1_DC_ABM1_LS_SAMPLE_RATE", REG_MMIO, 0x1814, 2, &mmABM1_DC_ABM1_LS_SAMPLE_RATE[0], sizeof(mmABM1_DC_ABM1_LS_SAMPLE_RATE)/sizeof(mmABM1_DC_ABM1_LS_SAMPLE_RATE[0]), 0, 0 }, + { "mmABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG", REG_MMIO, 0x1815, 2, &mmABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG[0], sizeof(mmABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG)/sizeof(mmABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG[0]), 0, 0 }, + { "mmABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX", REG_MMIO, 0x1816, 2, &mmABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX[0], sizeof(mmABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX)/sizeof(mmABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX[0]), 0, 0 }, + { "mmABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX", REG_MMIO, 0x1817, 2, &mmABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX[0], sizeof(mmABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX)/sizeof(mmABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX[0]), 0, 0 }, + { "mmABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX", REG_MMIO, 0x1818, 2, &mmABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX[0], sizeof(mmABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX)/sizeof(mmABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX[0]), 0, 0 }, + { "mmABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX", REG_MMIO, 0x1819, 2, &mmABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX[0], sizeof(mmABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX)/sizeof(mmABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX[0]), 0, 0 }, + { "mmABM1_DC_ABM1_HG_RESULT_1", REG_MMIO, 0x181a, 2, &mmABM1_DC_ABM1_HG_RESULT_1[0], sizeof(mmABM1_DC_ABM1_HG_RESULT_1)/sizeof(mmABM1_DC_ABM1_HG_RESULT_1[0]), 0, 0 }, + { "mmABM1_DC_ABM1_HG_RESULT_2", REG_MMIO, 0x181b, 2, &mmABM1_DC_ABM1_HG_RESULT_2[0], sizeof(mmABM1_DC_ABM1_HG_RESULT_2)/sizeof(mmABM1_DC_ABM1_HG_RESULT_2[0]), 0, 0 }, + { "mmABM1_DC_ABM1_HG_RESULT_3", REG_MMIO, 0x181c, 2, &mmABM1_DC_ABM1_HG_RESULT_3[0], sizeof(mmABM1_DC_ABM1_HG_RESULT_3)/sizeof(mmABM1_DC_ABM1_HG_RESULT_3[0]), 0, 0 }, + { "mmABM1_DC_ABM1_HG_RESULT_4", REG_MMIO, 0x181d, 2, &mmABM1_DC_ABM1_HG_RESULT_4[0], sizeof(mmABM1_DC_ABM1_HG_RESULT_4)/sizeof(mmABM1_DC_ABM1_HG_RESULT_4[0]), 0, 0 }, + { "mmABM1_DC_ABM1_HG_RESULT_5", REG_MMIO, 0x181e, 2, &mmABM1_DC_ABM1_HG_RESULT_5[0], sizeof(mmABM1_DC_ABM1_HG_RESULT_5)/sizeof(mmABM1_DC_ABM1_HG_RESULT_5[0]), 0, 0 }, + { "mmABM1_DC_ABM1_HG_RESULT_6", REG_MMIO, 0x181f, 2, &mmABM1_DC_ABM1_HG_RESULT_6[0], sizeof(mmABM1_DC_ABM1_HG_RESULT_6)/sizeof(mmABM1_DC_ABM1_HG_RESULT_6[0]), 0, 0 }, + { "mmABM1_DC_ABM1_HG_RESULT_7", REG_MMIO, 0x1820, 2, &mmABM1_DC_ABM1_HG_RESULT_7[0], sizeof(mmABM1_DC_ABM1_HG_RESULT_7)/sizeof(mmABM1_DC_ABM1_HG_RESULT_7[0]), 0, 0 }, + { "mmABM1_DC_ABM1_HG_RESULT_8", REG_MMIO, 0x1821, 2, &mmABM1_DC_ABM1_HG_RESULT_8[0], sizeof(mmABM1_DC_ABM1_HG_RESULT_8)/sizeof(mmABM1_DC_ABM1_HG_RESULT_8[0]), 0, 0 }, + { "mmABM1_DC_ABM1_HG_RESULT_9", REG_MMIO, 0x1822, 2, &mmABM1_DC_ABM1_HG_RESULT_9[0], sizeof(mmABM1_DC_ABM1_HG_RESULT_9)/sizeof(mmABM1_DC_ABM1_HG_RESULT_9[0]), 0, 0 }, + { "mmABM1_DC_ABM1_HG_RESULT_10", REG_MMIO, 0x1823, 2, &mmABM1_DC_ABM1_HG_RESULT_10[0], sizeof(mmABM1_DC_ABM1_HG_RESULT_10)/sizeof(mmABM1_DC_ABM1_HG_RESULT_10[0]), 0, 0 }, + { "mmABM1_DC_ABM1_HG_RESULT_11", REG_MMIO, 0x1824, 2, &mmABM1_DC_ABM1_HG_RESULT_11[0], sizeof(mmABM1_DC_ABM1_HG_RESULT_11)/sizeof(mmABM1_DC_ABM1_HG_RESULT_11[0]), 0, 0 }, + { "mmABM1_DC_ABM1_HG_RESULT_12", REG_MMIO, 0x1825, 2, &mmABM1_DC_ABM1_HG_RESULT_12[0], sizeof(mmABM1_DC_ABM1_HG_RESULT_12)/sizeof(mmABM1_DC_ABM1_HG_RESULT_12[0]), 0, 0 }, + { "mmABM1_DC_ABM1_HG_RESULT_13", REG_MMIO, 0x1826, 2, &mmABM1_DC_ABM1_HG_RESULT_13[0], sizeof(mmABM1_DC_ABM1_HG_RESULT_13)/sizeof(mmABM1_DC_ABM1_HG_RESULT_13[0]), 0, 0 }, + { "mmABM1_DC_ABM1_HG_RESULT_14", REG_MMIO, 0x1827, 2, &mmABM1_DC_ABM1_HG_RESULT_14[0], sizeof(mmABM1_DC_ABM1_HG_RESULT_14)/sizeof(mmABM1_DC_ABM1_HG_RESULT_14[0]), 0, 0 }, + { "mmABM1_DC_ABM1_HG_RESULT_15", REG_MMIO, 0x1828, 2, &mmABM1_DC_ABM1_HG_RESULT_15[0], sizeof(mmABM1_DC_ABM1_HG_RESULT_15)/sizeof(mmABM1_DC_ABM1_HG_RESULT_15[0]), 0, 0 }, + { "mmABM1_DC_ABM1_HG_RESULT_16", REG_MMIO, 0x1829, 2, &mmABM1_DC_ABM1_HG_RESULT_16[0], sizeof(mmABM1_DC_ABM1_HG_RESULT_16)/sizeof(mmABM1_DC_ABM1_HG_RESULT_16[0]), 0, 0 }, + { "mmABM1_DC_ABM1_HG_RESULT_17", REG_MMIO, 0x182a, 2, &mmABM1_DC_ABM1_HG_RESULT_17[0], sizeof(mmABM1_DC_ABM1_HG_RESULT_17)/sizeof(mmABM1_DC_ABM1_HG_RESULT_17[0]), 0, 0 }, + { "mmABM1_DC_ABM1_HG_RESULT_18", REG_MMIO, 0x182b, 2, &mmABM1_DC_ABM1_HG_RESULT_18[0], sizeof(mmABM1_DC_ABM1_HG_RESULT_18)/sizeof(mmABM1_DC_ABM1_HG_RESULT_18[0]), 0, 0 }, + { "mmABM1_DC_ABM1_HG_RESULT_19", REG_MMIO, 0x182c, 2, &mmABM1_DC_ABM1_HG_RESULT_19[0], sizeof(mmABM1_DC_ABM1_HG_RESULT_19)/sizeof(mmABM1_DC_ABM1_HG_RESULT_19[0]), 0, 0 }, + { "mmABM1_DC_ABM1_HG_RESULT_20", REG_MMIO, 0x182d, 2, &mmABM1_DC_ABM1_HG_RESULT_20[0], sizeof(mmABM1_DC_ABM1_HG_RESULT_20)/sizeof(mmABM1_DC_ABM1_HG_RESULT_20[0]), 0, 0 }, + { "mmABM1_DC_ABM1_HG_RESULT_21", REG_MMIO, 0x182e, 2, &mmABM1_DC_ABM1_HG_RESULT_21[0], sizeof(mmABM1_DC_ABM1_HG_RESULT_21)/sizeof(mmABM1_DC_ABM1_HG_RESULT_21[0]), 0, 0 }, + { "mmABM1_DC_ABM1_HG_RESULT_22", REG_MMIO, 0x182f, 2, &mmABM1_DC_ABM1_HG_RESULT_22[0], sizeof(mmABM1_DC_ABM1_HG_RESULT_22)/sizeof(mmABM1_DC_ABM1_HG_RESULT_22[0]), 0, 0 }, + { "mmABM1_DC_ABM1_HG_RESULT_23", REG_MMIO, 0x1830, 2, &mmABM1_DC_ABM1_HG_RESULT_23[0], sizeof(mmABM1_DC_ABM1_HG_RESULT_23)/sizeof(mmABM1_DC_ABM1_HG_RESULT_23[0]), 0, 0 }, + { "mmABM1_DC_ABM1_HG_RESULT_24", REG_MMIO, 0x1831, 2, &mmABM1_DC_ABM1_HG_RESULT_24[0], sizeof(mmABM1_DC_ABM1_HG_RESULT_24)/sizeof(mmABM1_DC_ABM1_HG_RESULT_24[0]), 0, 0 }, + { "mmABM1_DC_ABM1_BL_MASTER_LOCK", REG_MMIO, 0x1832, 2, &mmABM1_DC_ABM1_BL_MASTER_LOCK[0], sizeof(mmABM1_DC_ABM1_BL_MASTER_LOCK)/sizeof(mmABM1_DC_ABM1_BL_MASTER_LOCK[0]), 0, 0 }, + { "mmFMT0_FMT_CLAMP_COMPONENT_R", REG_MMIO, 0x183c, 2, &mmFMT0_FMT_CLAMP_COMPONENT_R[0], sizeof(mmFMT0_FMT_CLAMP_COMPONENT_R)/sizeof(mmFMT0_FMT_CLAMP_COMPONENT_R[0]), 0, 0 }, + { "mmFMT0_FMT_CLAMP_COMPONENT_G", REG_MMIO, 0x183d, 2, &mmFMT0_FMT_CLAMP_COMPONENT_G[0], sizeof(mmFMT0_FMT_CLAMP_COMPONENT_G)/sizeof(mmFMT0_FMT_CLAMP_COMPONENT_G[0]), 0, 0 }, + { "mmFMT0_FMT_CLAMP_COMPONENT_B", REG_MMIO, 0x183e, 2, &mmFMT0_FMT_CLAMP_COMPONENT_B[0], sizeof(mmFMT0_FMT_CLAMP_COMPONENT_B)/sizeof(mmFMT0_FMT_CLAMP_COMPONENT_B[0]), 0, 0 }, + { "mmFMT0_FMT_DYNAMIC_EXP_CNTL", REG_MMIO, 0x183f, 2, &mmFMT0_FMT_DYNAMIC_EXP_CNTL[0], sizeof(mmFMT0_FMT_DYNAMIC_EXP_CNTL)/sizeof(mmFMT0_FMT_DYNAMIC_EXP_CNTL[0]), 0, 0 }, + { "mmFMT0_FMT_CONTROL", REG_MMIO, 0x1840, 2, &mmFMT0_FMT_CONTROL[0], sizeof(mmFMT0_FMT_CONTROL)/sizeof(mmFMT0_FMT_CONTROL[0]), 0, 0 }, + { "mmFMT0_FMT_BIT_DEPTH_CONTROL", REG_MMIO, 0x1841, 2, &mmFMT0_FMT_BIT_DEPTH_CONTROL[0], sizeof(mmFMT0_FMT_BIT_DEPTH_CONTROL)/sizeof(mmFMT0_FMT_BIT_DEPTH_CONTROL[0]), 0, 0 }, + { "mmFMT0_FMT_DITHER_RAND_R_SEED", REG_MMIO, 0x1842, 2, &mmFMT0_FMT_DITHER_RAND_R_SEED[0], sizeof(mmFMT0_FMT_DITHER_RAND_R_SEED)/sizeof(mmFMT0_FMT_DITHER_RAND_R_SEED[0]), 0, 0 }, + { "mmFMT0_FMT_DITHER_RAND_G_SEED", REG_MMIO, 0x1843, 2, &mmFMT0_FMT_DITHER_RAND_G_SEED[0], sizeof(mmFMT0_FMT_DITHER_RAND_G_SEED)/sizeof(mmFMT0_FMT_DITHER_RAND_G_SEED[0]), 0, 0 }, + { "mmFMT0_FMT_DITHER_RAND_B_SEED", REG_MMIO, 0x1844, 2, &mmFMT0_FMT_DITHER_RAND_B_SEED[0], sizeof(mmFMT0_FMT_DITHER_RAND_B_SEED)/sizeof(mmFMT0_FMT_DITHER_RAND_B_SEED[0]), 0, 0 }, + { "mmFMT0_FMT_CLAMP_CNTL", REG_MMIO, 0x1848, 2, &mmFMT0_FMT_CLAMP_CNTL[0], sizeof(mmFMT0_FMT_CLAMP_CNTL)/sizeof(mmFMT0_FMT_CLAMP_CNTL[0]), 0, 0 }, + { "mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL", REG_MMIO, 0x1849, 2, &mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL[0], sizeof(mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL)/sizeof(mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL[0]), 0, 0 }, + { "mmFMT0_FMT_MAP420_MEMORY_CONTROL", REG_MMIO, 0x184a, 2, &mmFMT0_FMT_MAP420_MEMORY_CONTROL[0], sizeof(mmFMT0_FMT_MAP420_MEMORY_CONTROL)/sizeof(mmFMT0_FMT_MAP420_MEMORY_CONTROL[0]), 0, 0 }, + { "mmOPPBUF0_OPPBUF_CONTROL", REG_MMIO, 0x1884, 2, &mmOPPBUF0_OPPBUF_CONTROL[0], sizeof(mmOPPBUF0_OPPBUF_CONTROL)/sizeof(mmOPPBUF0_OPPBUF_CONTROL[0]), 0, 0 }, + { "mmOPPBUF0_OPPBUF_3D_PARAMETERS_0", REG_MMIO, 0x1885, 2, &mmOPPBUF0_OPPBUF_3D_PARAMETERS_0[0], sizeof(mmOPPBUF0_OPPBUF_3D_PARAMETERS_0)/sizeof(mmOPPBUF0_OPPBUF_3D_PARAMETERS_0[0]), 0, 0 }, + { "mmOPPBUF0_OPPBUF_3D_PARAMETERS_1", REG_MMIO, 0x1886, 2, &mmOPPBUF0_OPPBUF_3D_PARAMETERS_1[0], sizeof(mmOPPBUF0_OPPBUF_3D_PARAMETERS_1)/sizeof(mmOPPBUF0_OPPBUF_3D_PARAMETERS_1[0]), 0, 0 }, + { "mmOPP_PIPE0_OPP_PIPE_CONTROL", REG_MMIO, 0x188c, 2, &mmOPP_PIPE0_OPP_PIPE_CONTROL[0], sizeof(mmOPP_PIPE0_OPP_PIPE_CONTROL)/sizeof(mmOPP_PIPE0_OPP_PIPE_CONTROL[0]), 0, 0 }, + { "mmOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL", REG_MMIO, 0x1891, 2, &mmOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL[0], sizeof(mmOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL)/sizeof(mmOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL[0]), 0, 0 }, + { "mmOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK", REG_MMIO, 0x1892, 2, &mmOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK[0], sizeof(mmOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK)/sizeof(mmOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK[0]), 0, 0 }, + { "mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0", REG_MMIO, 0x1893, 2, &mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0[0], sizeof(mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0)/sizeof(mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0[0]), 0, 0 }, + { "mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1", REG_MMIO, 0x1894, 2, &mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1[0], sizeof(mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1)/sizeof(mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1[0]), 0, 0 }, + { "mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2", REG_MMIO, 0x1895, 2, &mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2[0], sizeof(mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2)/sizeof(mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2[0]), 0, 0 }, + { "mmFMT1_FMT_CLAMP_COMPONENT_R", REG_MMIO, 0x1896, 2, &mmFMT1_FMT_CLAMP_COMPONENT_R[0], sizeof(mmFMT1_FMT_CLAMP_COMPONENT_R)/sizeof(mmFMT1_FMT_CLAMP_COMPONENT_R[0]), 0, 0 }, + { "mmFMT1_FMT_CLAMP_COMPONENT_G", REG_MMIO, 0x1897, 2, &mmFMT1_FMT_CLAMP_COMPONENT_G[0], sizeof(mmFMT1_FMT_CLAMP_COMPONENT_G)/sizeof(mmFMT1_FMT_CLAMP_COMPONENT_G[0]), 0, 0 }, + { "mmFMT1_FMT_CLAMP_COMPONENT_B", REG_MMIO, 0x1898, 2, &mmFMT1_FMT_CLAMP_COMPONENT_B[0], sizeof(mmFMT1_FMT_CLAMP_COMPONENT_B)/sizeof(mmFMT1_FMT_CLAMP_COMPONENT_B[0]), 0, 0 }, + { "mmFMT1_FMT_DYNAMIC_EXP_CNTL", REG_MMIO, 0x1899, 2, &mmFMT1_FMT_DYNAMIC_EXP_CNTL[0], sizeof(mmFMT1_FMT_DYNAMIC_EXP_CNTL)/sizeof(mmFMT1_FMT_DYNAMIC_EXP_CNTL[0]), 0, 0 }, + { "mmFMT1_FMT_CONTROL", REG_MMIO, 0x189a, 2, &mmFMT1_FMT_CONTROL[0], sizeof(mmFMT1_FMT_CONTROL)/sizeof(mmFMT1_FMT_CONTROL[0]), 0, 0 }, + { "mmFMT1_FMT_BIT_DEPTH_CONTROL", REG_MMIO, 0x189b, 2, &mmFMT1_FMT_BIT_DEPTH_CONTROL[0], sizeof(mmFMT1_FMT_BIT_DEPTH_CONTROL)/sizeof(mmFMT1_FMT_BIT_DEPTH_CONTROL[0]), 0, 0 }, + { "mmFMT1_FMT_DITHER_RAND_R_SEED", REG_MMIO, 0x189c, 2, &mmFMT1_FMT_DITHER_RAND_R_SEED[0], sizeof(mmFMT1_FMT_DITHER_RAND_R_SEED)/sizeof(mmFMT1_FMT_DITHER_RAND_R_SEED[0]), 0, 0 }, + { "mmFMT1_FMT_DITHER_RAND_G_SEED", REG_MMIO, 0x189d, 2, &mmFMT1_FMT_DITHER_RAND_G_SEED[0], sizeof(mmFMT1_FMT_DITHER_RAND_G_SEED)/sizeof(mmFMT1_FMT_DITHER_RAND_G_SEED[0]), 0, 0 }, + { "mmFMT1_FMT_DITHER_RAND_B_SEED", REG_MMIO, 0x189e, 2, &mmFMT1_FMT_DITHER_RAND_B_SEED[0], sizeof(mmFMT1_FMT_DITHER_RAND_B_SEED)/sizeof(mmFMT1_FMT_DITHER_RAND_B_SEED[0]), 0, 0 }, + { "mmFMT1_FMT_CLAMP_CNTL", REG_MMIO, 0x18a2, 2, &mmFMT1_FMT_CLAMP_CNTL[0], sizeof(mmFMT1_FMT_CLAMP_CNTL)/sizeof(mmFMT1_FMT_CLAMP_CNTL[0]), 0, 0 }, + { "mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL", REG_MMIO, 0x18a3, 2, &mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL[0], sizeof(mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL)/sizeof(mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL[0]), 0, 0 }, + { "mmFMT1_FMT_MAP420_MEMORY_CONTROL", REG_MMIO, 0x18a4, 2, &mmFMT1_FMT_MAP420_MEMORY_CONTROL[0], sizeof(mmFMT1_FMT_MAP420_MEMORY_CONTROL)/sizeof(mmFMT1_FMT_MAP420_MEMORY_CONTROL[0]), 0, 0 }, + { "mmOPPBUF1_OPPBUF_CONTROL", REG_MMIO, 0x18de, 2, &mmOPPBUF1_OPPBUF_CONTROL[0], sizeof(mmOPPBUF1_OPPBUF_CONTROL)/sizeof(mmOPPBUF1_OPPBUF_CONTROL[0]), 0, 0 }, + { "mmOPPBUF1_OPPBUF_3D_PARAMETERS_0", REG_MMIO, 0x18df, 2, &mmOPPBUF1_OPPBUF_3D_PARAMETERS_0[0], sizeof(mmOPPBUF1_OPPBUF_3D_PARAMETERS_0)/sizeof(mmOPPBUF1_OPPBUF_3D_PARAMETERS_0[0]), 0, 0 }, + { "mmOPPBUF1_OPPBUF_3D_PARAMETERS_1", REG_MMIO, 0x18e0, 2, &mmOPPBUF1_OPPBUF_3D_PARAMETERS_1[0], sizeof(mmOPPBUF1_OPPBUF_3D_PARAMETERS_1)/sizeof(mmOPPBUF1_OPPBUF_3D_PARAMETERS_1[0]), 0, 0 }, + { "mmOPP_PIPE1_OPP_PIPE_CONTROL", REG_MMIO, 0x18e6, 2, &mmOPP_PIPE1_OPP_PIPE_CONTROL[0], sizeof(mmOPP_PIPE1_OPP_PIPE_CONTROL)/sizeof(mmOPP_PIPE1_OPP_PIPE_CONTROL[0]), 0, 0 }, + { "mmOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL", REG_MMIO, 0x18eb, 2, &mmOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL[0], sizeof(mmOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL)/sizeof(mmOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL[0]), 0, 0 }, + { "mmOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK", REG_MMIO, 0x18ec, 2, &mmOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK[0], sizeof(mmOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK)/sizeof(mmOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK[0]), 0, 0 }, + { "mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0", REG_MMIO, 0x18ed, 2, &mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0[0], sizeof(mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0)/sizeof(mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0[0]), 0, 0 }, + { "mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1", REG_MMIO, 0x18ee, 2, &mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1[0], sizeof(mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1)/sizeof(mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1[0]), 0, 0 }, + { "mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2", REG_MMIO, 0x18ef, 2, &mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2[0], sizeof(mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2)/sizeof(mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2[0]), 0, 0 }, + { "mmFMT2_FMT_CLAMP_COMPONENT_R", REG_MMIO, 0x18f0, 2, &mmFMT2_FMT_CLAMP_COMPONENT_R[0], sizeof(mmFMT2_FMT_CLAMP_COMPONENT_R)/sizeof(mmFMT2_FMT_CLAMP_COMPONENT_R[0]), 0, 0 }, + { "mmFMT2_FMT_CLAMP_COMPONENT_G", REG_MMIO, 0x18f1, 2, &mmFMT2_FMT_CLAMP_COMPONENT_G[0], sizeof(mmFMT2_FMT_CLAMP_COMPONENT_G)/sizeof(mmFMT2_FMT_CLAMP_COMPONENT_G[0]), 0, 0 }, + { "mmFMT2_FMT_CLAMP_COMPONENT_B", REG_MMIO, 0x18f2, 2, &mmFMT2_FMT_CLAMP_COMPONENT_B[0], sizeof(mmFMT2_FMT_CLAMP_COMPONENT_B)/sizeof(mmFMT2_FMT_CLAMP_COMPONENT_B[0]), 0, 0 }, + { "mmFMT2_FMT_DYNAMIC_EXP_CNTL", REG_MMIO, 0x18f3, 2, &mmFMT2_FMT_DYNAMIC_EXP_CNTL[0], sizeof(mmFMT2_FMT_DYNAMIC_EXP_CNTL)/sizeof(mmFMT2_FMT_DYNAMIC_EXP_CNTL[0]), 0, 0 }, + { "mmFMT2_FMT_CONTROL", REG_MMIO, 0x18f4, 2, &mmFMT2_FMT_CONTROL[0], sizeof(mmFMT2_FMT_CONTROL)/sizeof(mmFMT2_FMT_CONTROL[0]), 0, 0 }, + { "mmFMT2_FMT_BIT_DEPTH_CONTROL", REG_MMIO, 0x18f5, 2, &mmFMT2_FMT_BIT_DEPTH_CONTROL[0], sizeof(mmFMT2_FMT_BIT_DEPTH_CONTROL)/sizeof(mmFMT2_FMT_BIT_DEPTH_CONTROL[0]), 0, 0 }, + { "mmFMT2_FMT_DITHER_RAND_R_SEED", REG_MMIO, 0x18f6, 2, &mmFMT2_FMT_DITHER_RAND_R_SEED[0], sizeof(mmFMT2_FMT_DITHER_RAND_R_SEED)/sizeof(mmFMT2_FMT_DITHER_RAND_R_SEED[0]), 0, 0 }, + { "mmFMT2_FMT_DITHER_RAND_G_SEED", REG_MMIO, 0x18f7, 2, &mmFMT2_FMT_DITHER_RAND_G_SEED[0], sizeof(mmFMT2_FMT_DITHER_RAND_G_SEED)/sizeof(mmFMT2_FMT_DITHER_RAND_G_SEED[0]), 0, 0 }, + { "mmFMT2_FMT_DITHER_RAND_B_SEED", REG_MMIO, 0x18f8, 2, &mmFMT2_FMT_DITHER_RAND_B_SEED[0], sizeof(mmFMT2_FMT_DITHER_RAND_B_SEED)/sizeof(mmFMT2_FMT_DITHER_RAND_B_SEED[0]), 0, 0 }, + { "mmFMT2_FMT_CLAMP_CNTL", REG_MMIO, 0x18fc, 2, &mmFMT2_FMT_CLAMP_CNTL[0], sizeof(mmFMT2_FMT_CLAMP_CNTL)/sizeof(mmFMT2_FMT_CLAMP_CNTL[0]), 0, 0 }, + { "mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL", REG_MMIO, 0x18fd, 2, &mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL[0], sizeof(mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL)/sizeof(mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL[0]), 0, 0 }, + { "mmFMT2_FMT_MAP420_MEMORY_CONTROL", REG_MMIO, 0x18fe, 2, &mmFMT2_FMT_MAP420_MEMORY_CONTROL[0], sizeof(mmFMT2_FMT_MAP420_MEMORY_CONTROL)/sizeof(mmFMT2_FMT_MAP420_MEMORY_CONTROL[0]), 0, 0 }, + { "mmOPPBUF2_OPPBUF_CONTROL", REG_MMIO, 0x1938, 2, &mmOPPBUF2_OPPBUF_CONTROL[0], sizeof(mmOPPBUF2_OPPBUF_CONTROL)/sizeof(mmOPPBUF2_OPPBUF_CONTROL[0]), 0, 0 }, + { "mmOPPBUF2_OPPBUF_3D_PARAMETERS_0", REG_MMIO, 0x1939, 2, &mmOPPBUF2_OPPBUF_3D_PARAMETERS_0[0], sizeof(mmOPPBUF2_OPPBUF_3D_PARAMETERS_0)/sizeof(mmOPPBUF2_OPPBUF_3D_PARAMETERS_0[0]), 0, 0 }, + { "mmOPPBUF2_OPPBUF_3D_PARAMETERS_1", REG_MMIO, 0x193a, 2, &mmOPPBUF2_OPPBUF_3D_PARAMETERS_1[0], sizeof(mmOPPBUF2_OPPBUF_3D_PARAMETERS_1)/sizeof(mmOPPBUF2_OPPBUF_3D_PARAMETERS_1[0]), 0, 0 }, + { "mmOPP_PIPE2_OPP_PIPE_CONTROL", REG_MMIO, 0x1940, 2, &mmOPP_PIPE2_OPP_PIPE_CONTROL[0], sizeof(mmOPP_PIPE2_OPP_PIPE_CONTROL)/sizeof(mmOPP_PIPE2_OPP_PIPE_CONTROL[0]), 0, 0 }, + { "mmOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL", REG_MMIO, 0x1945, 2, &mmOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL[0], sizeof(mmOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL)/sizeof(mmOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL[0]), 0, 0 }, + { "mmOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK", REG_MMIO, 0x1946, 2, &mmOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK[0], sizeof(mmOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK)/sizeof(mmOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK[0]), 0, 0 }, + { "mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0", REG_MMIO, 0x1947, 2, &mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0[0], sizeof(mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0)/sizeof(mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0[0]), 0, 0 }, + { "mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1", REG_MMIO, 0x1948, 2, &mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1[0], sizeof(mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1)/sizeof(mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1[0]), 0, 0 }, + { "mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2", REG_MMIO, 0x1949, 2, &mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2[0], sizeof(mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2)/sizeof(mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2[0]), 0, 0 }, + { "mmFMT3_FMT_CLAMP_COMPONENT_R", REG_MMIO, 0x194a, 2, &mmFMT3_FMT_CLAMP_COMPONENT_R[0], sizeof(mmFMT3_FMT_CLAMP_COMPONENT_R)/sizeof(mmFMT3_FMT_CLAMP_COMPONENT_R[0]), 0, 0 }, + { "mmFMT3_FMT_CLAMP_COMPONENT_G", REG_MMIO, 0x194b, 2, &mmFMT3_FMT_CLAMP_COMPONENT_G[0], sizeof(mmFMT3_FMT_CLAMP_COMPONENT_G)/sizeof(mmFMT3_FMT_CLAMP_COMPONENT_G[0]), 0, 0 }, + { "mmFMT3_FMT_CLAMP_COMPONENT_B", REG_MMIO, 0x194c, 2, &mmFMT3_FMT_CLAMP_COMPONENT_B[0], sizeof(mmFMT3_FMT_CLAMP_COMPONENT_B)/sizeof(mmFMT3_FMT_CLAMP_COMPONENT_B[0]), 0, 0 }, + { "mmFMT3_FMT_DYNAMIC_EXP_CNTL", REG_MMIO, 0x194d, 2, &mmFMT3_FMT_DYNAMIC_EXP_CNTL[0], sizeof(mmFMT3_FMT_DYNAMIC_EXP_CNTL)/sizeof(mmFMT3_FMT_DYNAMIC_EXP_CNTL[0]), 0, 0 }, + { "mmFMT3_FMT_CONTROL", REG_MMIO, 0x194e, 2, &mmFMT3_FMT_CONTROL[0], sizeof(mmFMT3_FMT_CONTROL)/sizeof(mmFMT3_FMT_CONTROL[0]), 0, 0 }, + { "mmFMT3_FMT_BIT_DEPTH_CONTROL", REG_MMIO, 0x194f, 2, &mmFMT3_FMT_BIT_DEPTH_CONTROL[0], sizeof(mmFMT3_FMT_BIT_DEPTH_CONTROL)/sizeof(mmFMT3_FMT_BIT_DEPTH_CONTROL[0]), 0, 0 }, + { "mmFMT3_FMT_DITHER_RAND_R_SEED", REG_MMIO, 0x1950, 2, &mmFMT3_FMT_DITHER_RAND_R_SEED[0], sizeof(mmFMT3_FMT_DITHER_RAND_R_SEED)/sizeof(mmFMT3_FMT_DITHER_RAND_R_SEED[0]), 0, 0 }, + { "mmFMT3_FMT_DITHER_RAND_G_SEED", REG_MMIO, 0x1951, 2, &mmFMT3_FMT_DITHER_RAND_G_SEED[0], sizeof(mmFMT3_FMT_DITHER_RAND_G_SEED)/sizeof(mmFMT3_FMT_DITHER_RAND_G_SEED[0]), 0, 0 }, + { "mmFMT3_FMT_DITHER_RAND_B_SEED", REG_MMIO, 0x1952, 2, &mmFMT3_FMT_DITHER_RAND_B_SEED[0], sizeof(mmFMT3_FMT_DITHER_RAND_B_SEED)/sizeof(mmFMT3_FMT_DITHER_RAND_B_SEED[0]), 0, 0 }, + { "mmFMT3_FMT_CLAMP_CNTL", REG_MMIO, 0x1956, 2, &mmFMT3_FMT_CLAMP_CNTL[0], sizeof(mmFMT3_FMT_CLAMP_CNTL)/sizeof(mmFMT3_FMT_CLAMP_CNTL[0]), 0, 0 }, + { "mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL", REG_MMIO, 0x1957, 2, &mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL[0], sizeof(mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL)/sizeof(mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL[0]), 0, 0 }, + { "mmFMT3_FMT_MAP420_MEMORY_CONTROL", REG_MMIO, 0x1958, 2, &mmFMT3_FMT_MAP420_MEMORY_CONTROL[0], sizeof(mmFMT3_FMT_MAP420_MEMORY_CONTROL)/sizeof(mmFMT3_FMT_MAP420_MEMORY_CONTROL[0]), 0, 0 }, + { "mmOPPBUF3_OPPBUF_CONTROL", REG_MMIO, 0x1992, 2, &mmOPPBUF3_OPPBUF_CONTROL[0], sizeof(mmOPPBUF3_OPPBUF_CONTROL)/sizeof(mmOPPBUF3_OPPBUF_CONTROL[0]), 0, 0 }, + { "mmOPPBUF3_OPPBUF_3D_PARAMETERS_0", REG_MMIO, 0x1993, 2, &mmOPPBUF3_OPPBUF_3D_PARAMETERS_0[0], sizeof(mmOPPBUF3_OPPBUF_3D_PARAMETERS_0)/sizeof(mmOPPBUF3_OPPBUF_3D_PARAMETERS_0[0]), 0, 0 }, + { "mmOPPBUF3_OPPBUF_3D_PARAMETERS_1", REG_MMIO, 0x1994, 2, &mmOPPBUF3_OPPBUF_3D_PARAMETERS_1[0], sizeof(mmOPPBUF3_OPPBUF_3D_PARAMETERS_1)/sizeof(mmOPPBUF3_OPPBUF_3D_PARAMETERS_1[0]), 0, 0 }, + { "mmOPP_PIPE3_OPP_PIPE_CONTROL", REG_MMIO, 0x199a, 2, &mmOPP_PIPE3_OPP_PIPE_CONTROL[0], sizeof(mmOPP_PIPE3_OPP_PIPE_CONTROL)/sizeof(mmOPP_PIPE3_OPP_PIPE_CONTROL[0]), 0, 0 }, + { "mmOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL", REG_MMIO, 0x199f, 2, &mmOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL[0], sizeof(mmOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL)/sizeof(mmOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL[0]), 0, 0 }, + { "mmOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK", REG_MMIO, 0x19a0, 2, &mmOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK[0], sizeof(mmOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK)/sizeof(mmOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK[0]), 0, 0 }, + { "mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0", REG_MMIO, 0x19a1, 2, &mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0[0], sizeof(mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0)/sizeof(mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0[0]), 0, 0 }, + { "mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1", REG_MMIO, 0x19a2, 2, &mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1[0], sizeof(mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1)/sizeof(mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1[0]), 0, 0 }, + { "mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2", REG_MMIO, 0x19a3, 2, &mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2[0], sizeof(mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2)/sizeof(mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2[0]), 0, 0 }, + { "mmFMT4_FMT_CLAMP_COMPONENT_R", REG_MMIO, 0x19a4, 2, &mmFMT4_FMT_CLAMP_COMPONENT_R[0], sizeof(mmFMT4_FMT_CLAMP_COMPONENT_R)/sizeof(mmFMT4_FMT_CLAMP_COMPONENT_R[0]), 0, 0 }, + { "mmFMT4_FMT_CLAMP_COMPONENT_G", REG_MMIO, 0x19a5, 2, &mmFMT4_FMT_CLAMP_COMPONENT_G[0], sizeof(mmFMT4_FMT_CLAMP_COMPONENT_G)/sizeof(mmFMT4_FMT_CLAMP_COMPONENT_G[0]), 0, 0 }, + { "mmFMT4_FMT_CLAMP_COMPONENT_B", REG_MMIO, 0x19a6, 2, &mmFMT4_FMT_CLAMP_COMPONENT_B[0], sizeof(mmFMT4_FMT_CLAMP_COMPONENT_B)/sizeof(mmFMT4_FMT_CLAMP_COMPONENT_B[0]), 0, 0 }, + { "mmFMT4_FMT_DYNAMIC_EXP_CNTL", REG_MMIO, 0x19a7, 2, &mmFMT4_FMT_DYNAMIC_EXP_CNTL[0], sizeof(mmFMT4_FMT_DYNAMIC_EXP_CNTL)/sizeof(mmFMT4_FMT_DYNAMIC_EXP_CNTL[0]), 0, 0 }, + { "mmFMT4_FMT_CONTROL", REG_MMIO, 0x19a8, 2, &mmFMT4_FMT_CONTROL[0], sizeof(mmFMT4_FMT_CONTROL)/sizeof(mmFMT4_FMT_CONTROL[0]), 0, 0 }, + { "mmFMT4_FMT_BIT_DEPTH_CONTROL", REG_MMIO, 0x19a9, 2, &mmFMT4_FMT_BIT_DEPTH_CONTROL[0], sizeof(mmFMT4_FMT_BIT_DEPTH_CONTROL)/sizeof(mmFMT4_FMT_BIT_DEPTH_CONTROL[0]), 0, 0 }, + { "mmFMT4_FMT_DITHER_RAND_R_SEED", REG_MMIO, 0x19aa, 2, &mmFMT4_FMT_DITHER_RAND_R_SEED[0], sizeof(mmFMT4_FMT_DITHER_RAND_R_SEED)/sizeof(mmFMT4_FMT_DITHER_RAND_R_SEED[0]), 0, 0 }, + { "mmFMT4_FMT_DITHER_RAND_G_SEED", REG_MMIO, 0x19ab, 2, &mmFMT4_FMT_DITHER_RAND_G_SEED[0], sizeof(mmFMT4_FMT_DITHER_RAND_G_SEED)/sizeof(mmFMT4_FMT_DITHER_RAND_G_SEED[0]), 0, 0 }, + { "mmFMT4_FMT_DITHER_RAND_B_SEED", REG_MMIO, 0x19ac, 2, &mmFMT4_FMT_DITHER_RAND_B_SEED[0], sizeof(mmFMT4_FMT_DITHER_RAND_B_SEED)/sizeof(mmFMT4_FMT_DITHER_RAND_B_SEED[0]), 0, 0 }, + { "mmFMT4_FMT_CLAMP_CNTL", REG_MMIO, 0x19b0, 2, &mmFMT4_FMT_CLAMP_CNTL[0], sizeof(mmFMT4_FMT_CLAMP_CNTL)/sizeof(mmFMT4_FMT_CLAMP_CNTL[0]), 0, 0 }, + { "mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL", REG_MMIO, 0x19b1, 2, &mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL[0], sizeof(mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL)/sizeof(mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL[0]), 0, 0 }, + { "mmFMT4_FMT_MAP420_MEMORY_CONTROL", REG_MMIO, 0x19b2, 2, &mmFMT4_FMT_MAP420_MEMORY_CONTROL[0], sizeof(mmFMT4_FMT_MAP420_MEMORY_CONTROL)/sizeof(mmFMT4_FMT_MAP420_MEMORY_CONTROL[0]), 0, 0 }, + { "mmOPPBUF4_OPPBUF_CONTROL", REG_MMIO, 0x19ec, 2, &mmOPPBUF4_OPPBUF_CONTROL[0], sizeof(mmOPPBUF4_OPPBUF_CONTROL)/sizeof(mmOPPBUF4_OPPBUF_CONTROL[0]), 0, 0 }, + { "mmOPPBUF4_OPPBUF_3D_PARAMETERS_0", REG_MMIO, 0x19ed, 2, &mmOPPBUF4_OPPBUF_3D_PARAMETERS_0[0], sizeof(mmOPPBUF4_OPPBUF_3D_PARAMETERS_0)/sizeof(mmOPPBUF4_OPPBUF_3D_PARAMETERS_0[0]), 0, 0 }, + { "mmOPPBUF4_OPPBUF_3D_PARAMETERS_1", REG_MMIO, 0x19ee, 2, &mmOPPBUF4_OPPBUF_3D_PARAMETERS_1[0], sizeof(mmOPPBUF4_OPPBUF_3D_PARAMETERS_1)/sizeof(mmOPPBUF4_OPPBUF_3D_PARAMETERS_1[0]), 0, 0 }, + { "mmOPP_PIPE4_OPP_PIPE_CONTROL", REG_MMIO, 0x19f4, 2, &mmOPP_PIPE4_OPP_PIPE_CONTROL[0], sizeof(mmOPP_PIPE4_OPP_PIPE_CONTROL)/sizeof(mmOPP_PIPE4_OPP_PIPE_CONTROL[0]), 0, 0 }, + { "mmOPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL", REG_MMIO, 0x19f9, 2, &mmOPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL[0], sizeof(mmOPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL)/sizeof(mmOPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL[0]), 0, 0 }, + { "mmOPP_PIPE_CRC4_OPP_PIPE_CRC_MASK", REG_MMIO, 0x19fa, 2, &mmOPP_PIPE_CRC4_OPP_PIPE_CRC_MASK[0], sizeof(mmOPP_PIPE_CRC4_OPP_PIPE_CRC_MASK)/sizeof(mmOPP_PIPE_CRC4_OPP_PIPE_CRC_MASK[0]), 0, 0 }, + { "mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0", REG_MMIO, 0x19fb, 2, &mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0[0], sizeof(mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0)/sizeof(mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0[0]), 0, 0 }, + { "mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1", REG_MMIO, 0x19fc, 2, &mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1[0], sizeof(mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1)/sizeof(mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1[0]), 0, 0 }, + { "mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2", REG_MMIO, 0x19fd, 2, &mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2[0], sizeof(mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2)/sizeof(mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2[0]), 0, 0 }, + { "mmFMT5_FMT_CLAMP_COMPONENT_R", REG_MMIO, 0x19fe, 2, &mmFMT5_FMT_CLAMP_COMPONENT_R[0], sizeof(mmFMT5_FMT_CLAMP_COMPONENT_R)/sizeof(mmFMT5_FMT_CLAMP_COMPONENT_R[0]), 0, 0 }, + { "mmFMT5_FMT_CLAMP_COMPONENT_G", REG_MMIO, 0x19ff, 2, &mmFMT5_FMT_CLAMP_COMPONENT_G[0], sizeof(mmFMT5_FMT_CLAMP_COMPONENT_G)/sizeof(mmFMT5_FMT_CLAMP_COMPONENT_G[0]), 0, 0 }, + { "mmFMT5_FMT_CLAMP_COMPONENT_B", REG_MMIO, 0x1a00, 2, &mmFMT5_FMT_CLAMP_COMPONENT_B[0], sizeof(mmFMT5_FMT_CLAMP_COMPONENT_B)/sizeof(mmFMT5_FMT_CLAMP_COMPONENT_B[0]), 0, 0 }, + { "mmFMT5_FMT_DYNAMIC_EXP_CNTL", REG_MMIO, 0x1a01, 2, &mmFMT5_FMT_DYNAMIC_EXP_CNTL[0], sizeof(mmFMT5_FMT_DYNAMIC_EXP_CNTL)/sizeof(mmFMT5_FMT_DYNAMIC_EXP_CNTL[0]), 0, 0 }, + { "mmFMT5_FMT_CONTROL", REG_MMIO, 0x1a02, 2, &mmFMT5_FMT_CONTROL[0], sizeof(mmFMT5_FMT_CONTROL)/sizeof(mmFMT5_FMT_CONTROL[0]), 0, 0 }, + { "mmFMT5_FMT_BIT_DEPTH_CONTROL", REG_MMIO, 0x1a03, 2, &mmFMT5_FMT_BIT_DEPTH_CONTROL[0], sizeof(mmFMT5_FMT_BIT_DEPTH_CONTROL)/sizeof(mmFMT5_FMT_BIT_DEPTH_CONTROL[0]), 0, 0 }, + { "mmFMT5_FMT_DITHER_RAND_R_SEED", REG_MMIO, 0x1a04, 2, &mmFMT5_FMT_DITHER_RAND_R_SEED[0], sizeof(mmFMT5_FMT_DITHER_RAND_R_SEED)/sizeof(mmFMT5_FMT_DITHER_RAND_R_SEED[0]), 0, 0 }, + { "mmFMT5_FMT_DITHER_RAND_G_SEED", REG_MMIO, 0x1a05, 2, &mmFMT5_FMT_DITHER_RAND_G_SEED[0], sizeof(mmFMT5_FMT_DITHER_RAND_G_SEED)/sizeof(mmFMT5_FMT_DITHER_RAND_G_SEED[0]), 0, 0 }, + { "mmFMT5_FMT_DITHER_RAND_B_SEED", REG_MMIO, 0x1a06, 2, &mmFMT5_FMT_DITHER_RAND_B_SEED[0], sizeof(mmFMT5_FMT_DITHER_RAND_B_SEED)/sizeof(mmFMT5_FMT_DITHER_RAND_B_SEED[0]), 0, 0 }, + { "mmFMT5_FMT_CLAMP_CNTL", REG_MMIO, 0x1a0a, 2, &mmFMT5_FMT_CLAMP_CNTL[0], sizeof(mmFMT5_FMT_CLAMP_CNTL)/sizeof(mmFMT5_FMT_CLAMP_CNTL[0]), 0, 0 }, + { "mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL", REG_MMIO, 0x1a0b, 2, &mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL[0], sizeof(mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL)/sizeof(mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL[0]), 0, 0 }, + { "mmFMT5_FMT_MAP420_MEMORY_CONTROL", REG_MMIO, 0x1a0c, 2, &mmFMT5_FMT_MAP420_MEMORY_CONTROL[0], sizeof(mmFMT5_FMT_MAP420_MEMORY_CONTROL)/sizeof(mmFMT5_FMT_MAP420_MEMORY_CONTROL[0]), 0, 0 }, + { "mmOPPBUF5_OPPBUF_CONTROL", REG_MMIO, 0x1a46, 2, &mmOPPBUF5_OPPBUF_CONTROL[0], sizeof(mmOPPBUF5_OPPBUF_CONTROL)/sizeof(mmOPPBUF5_OPPBUF_CONTROL[0]), 0, 0 }, + { "mmOPPBUF5_OPPBUF_3D_PARAMETERS_0", REG_MMIO, 0x1a47, 2, &mmOPPBUF5_OPPBUF_3D_PARAMETERS_0[0], sizeof(mmOPPBUF5_OPPBUF_3D_PARAMETERS_0)/sizeof(mmOPPBUF5_OPPBUF_3D_PARAMETERS_0[0]), 0, 0 }, + { "mmOPPBUF5_OPPBUF_3D_PARAMETERS_1", REG_MMIO, 0x1a48, 2, &mmOPPBUF5_OPPBUF_3D_PARAMETERS_1[0], sizeof(mmOPPBUF5_OPPBUF_3D_PARAMETERS_1)/sizeof(mmOPPBUF5_OPPBUF_3D_PARAMETERS_1[0]), 0, 0 }, + { "mmOPP_PIPE5_OPP_PIPE_CONTROL", REG_MMIO, 0x1a4e, 2, &mmOPP_PIPE5_OPP_PIPE_CONTROL[0], sizeof(mmOPP_PIPE5_OPP_PIPE_CONTROL)/sizeof(mmOPP_PIPE5_OPP_PIPE_CONTROL[0]), 0, 0 }, + { "mmOPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL", REG_MMIO, 0x1a53, 2, &mmOPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL[0], sizeof(mmOPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL)/sizeof(mmOPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL[0]), 0, 0 }, + { "mmOPP_PIPE_CRC5_OPP_PIPE_CRC_MASK", REG_MMIO, 0x1a54, 2, &mmOPP_PIPE_CRC5_OPP_PIPE_CRC_MASK[0], sizeof(mmOPP_PIPE_CRC5_OPP_PIPE_CRC_MASK)/sizeof(mmOPP_PIPE_CRC5_OPP_PIPE_CRC_MASK[0]), 0, 0 }, + { "mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0", REG_MMIO, 0x1a55, 2, &mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0[0], sizeof(mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0)/sizeof(mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0[0]), 0, 0 }, + { "mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1", REG_MMIO, 0x1a56, 2, &mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1[0], sizeof(mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1)/sizeof(mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1[0]), 0, 0 }, + { "mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT2", REG_MMIO, 0x1a57, 2, &mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT2[0], sizeof(mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT2)/sizeof(mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT2[0]), 0, 0 }, + { "mmOPP_TOP_CLK_CONTROL", REG_MMIO, 0x1a5e, 2, &mmOPP_TOP_CLK_CONTROL[0], sizeof(mmOPP_TOP_CLK_CONTROL)/sizeof(mmOPP_TOP_CLK_CONTROL[0]), 0, 0 }, + { "mmDC_PERFMON17_PERFCOUNTER_CNTL", REG_MMIO, 0x1abe, 2, &mmDC_PERFMON17_PERFCOUNTER_CNTL[0], sizeof(mmDC_PERFMON17_PERFCOUNTER_CNTL)/sizeof(mmDC_PERFMON17_PERFCOUNTER_CNTL[0]), 0, 0 }, + { "mmDC_PERFMON17_PERFCOUNTER_CNTL2", REG_MMIO, 0x1abf, 2, &mmDC_PERFMON17_PERFCOUNTER_CNTL2[0], sizeof(mmDC_PERFMON17_PERFCOUNTER_CNTL2)/sizeof(mmDC_PERFMON17_PERFCOUNTER_CNTL2[0]), 0, 0 }, + { "mmDC_PERFMON17_PERFCOUNTER_STATE", REG_MMIO, 0x1ac0, 2, &mmDC_PERFMON17_PERFCOUNTER_STATE[0], sizeof(mmDC_PERFMON17_PERFCOUNTER_STATE)/sizeof(mmDC_PERFMON17_PERFCOUNTER_STATE[0]), 0, 0 }, + { "mmDC_PERFMON17_PERFMON_CNTL", REG_MMIO, 0x1ac1, 2, &mmDC_PERFMON17_PERFMON_CNTL[0], sizeof(mmDC_PERFMON17_PERFMON_CNTL)/sizeof(mmDC_PERFMON17_PERFMON_CNTL[0]), 0, 0 }, + { "mmDC_PERFMON17_PERFMON_CNTL2", REG_MMIO, 0x1ac2, 2, &mmDC_PERFMON17_PERFMON_CNTL2[0], sizeof(mmDC_PERFMON17_PERFMON_CNTL2)/sizeof(mmDC_PERFMON17_PERFMON_CNTL2[0]), 0, 0 }, + { "mmDC_PERFMON17_PERFMON_CVALUE_INT_MISC", REG_MMIO, 0x1ac3, 2, &mmDC_PERFMON17_PERFMON_CVALUE_INT_MISC[0], sizeof(mmDC_PERFMON17_PERFMON_CVALUE_INT_MISC)/sizeof(mmDC_PERFMON17_PERFMON_CVALUE_INT_MISC[0]), 0, 0 }, + { "mmDC_PERFMON17_PERFMON_CVALUE_LOW", REG_MMIO, 0x1ac4, 2, &mmDC_PERFMON17_PERFMON_CVALUE_LOW[0], sizeof(mmDC_PERFMON17_PERFMON_CVALUE_LOW)/sizeof(mmDC_PERFMON17_PERFMON_CVALUE_LOW[0]), 0, 0 }, + { "mmDC_PERFMON17_PERFMON_HI", REG_MMIO, 0x1ac5, 2, &mmDC_PERFMON17_PERFMON_HI[0], sizeof(mmDC_PERFMON17_PERFMON_HI)/sizeof(mmDC_PERFMON17_PERFMON_HI[0]), 0, 0 }, + { "mmDC_PERFMON17_PERFMON_LOW", REG_MMIO, 0x1ac6, 2, &mmDC_PERFMON17_PERFMON_LOW[0], sizeof(mmDC_PERFMON17_PERFMON_LOW)/sizeof(mmDC_PERFMON17_PERFMON_LOW[0]), 0, 0 }, + { "mmODM0_OPTC_INPUT_GLOBAL_CONTROL", REG_MMIO, 0x1aca, 2, &mmODM0_OPTC_INPUT_GLOBAL_CONTROL[0], sizeof(mmODM0_OPTC_INPUT_GLOBAL_CONTROL)/sizeof(mmODM0_OPTC_INPUT_GLOBAL_CONTROL[0]), 0, 0 }, + { "mmODM0_OPTC_DATA_SOURCE_SELECT", REG_MMIO, 0x1acb, 2, &mmODM0_OPTC_DATA_SOURCE_SELECT[0], sizeof(mmODM0_OPTC_DATA_SOURCE_SELECT)/sizeof(mmODM0_OPTC_DATA_SOURCE_SELECT[0]), 0, 0 }, + { "mmODM0_OPTC_INPUT_CLOCK_CONTROL", REG_MMIO, 0x1acd, 2, &mmODM0_OPTC_INPUT_CLOCK_CONTROL[0], sizeof(mmODM0_OPTC_INPUT_CLOCK_CONTROL)/sizeof(mmODM0_OPTC_INPUT_CLOCK_CONTROL[0]), 0, 0 }, + { "mmODM0_OPTC_INPUT_SPARE_REGISTER", REG_MMIO, 0x1acf, 2, &mmODM0_OPTC_INPUT_SPARE_REGISTER[0], sizeof(mmODM0_OPTC_INPUT_SPARE_REGISTER)/sizeof(mmODM0_OPTC_INPUT_SPARE_REGISTER[0]), 0, 0 }, + { "mmODM1_OPTC_INPUT_GLOBAL_CONTROL", REG_MMIO, 0x1ada, 2, &mmODM1_OPTC_INPUT_GLOBAL_CONTROL[0], sizeof(mmODM1_OPTC_INPUT_GLOBAL_CONTROL)/sizeof(mmODM1_OPTC_INPUT_GLOBAL_CONTROL[0]), 0, 0 }, + { "mmODM1_OPTC_DATA_SOURCE_SELECT", REG_MMIO, 0x1adb, 2, &mmODM1_OPTC_DATA_SOURCE_SELECT[0], sizeof(mmODM1_OPTC_DATA_SOURCE_SELECT)/sizeof(mmODM1_OPTC_DATA_SOURCE_SELECT[0]), 0, 0 }, + { "mmODM1_OPTC_INPUT_CLOCK_CONTROL", REG_MMIO, 0x1add, 2, &mmODM1_OPTC_INPUT_CLOCK_CONTROL[0], sizeof(mmODM1_OPTC_INPUT_CLOCK_CONTROL)/sizeof(mmODM1_OPTC_INPUT_CLOCK_CONTROL[0]), 0, 0 }, + { "mmODM1_OPTC_INPUT_SPARE_REGISTER", REG_MMIO, 0x1adf, 2, &mmODM1_OPTC_INPUT_SPARE_REGISTER[0], sizeof(mmODM1_OPTC_INPUT_SPARE_REGISTER)/sizeof(mmODM1_OPTC_INPUT_SPARE_REGISTER[0]), 0, 0 }, + { "mmODM2_OPTC_INPUT_GLOBAL_CONTROL", REG_MMIO, 0x1aea, 2, &mmODM2_OPTC_INPUT_GLOBAL_CONTROL[0], sizeof(mmODM2_OPTC_INPUT_GLOBAL_CONTROL)/sizeof(mmODM2_OPTC_INPUT_GLOBAL_CONTROL[0]), 0, 0 }, + { "mmODM2_OPTC_DATA_SOURCE_SELECT", REG_MMIO, 0x1aeb, 2, &mmODM2_OPTC_DATA_SOURCE_SELECT[0], sizeof(mmODM2_OPTC_DATA_SOURCE_SELECT)/sizeof(mmODM2_OPTC_DATA_SOURCE_SELECT[0]), 0, 0 }, + { "mmODM2_OPTC_INPUT_CLOCK_CONTROL", REG_MMIO, 0x1aed, 2, &mmODM2_OPTC_INPUT_CLOCK_CONTROL[0], sizeof(mmODM2_OPTC_INPUT_CLOCK_CONTROL)/sizeof(mmODM2_OPTC_INPUT_CLOCK_CONTROL[0]), 0, 0 }, + { "mmODM2_OPTC_INPUT_SPARE_REGISTER", REG_MMIO, 0x1aef, 2, &mmODM2_OPTC_INPUT_SPARE_REGISTER[0], sizeof(mmODM2_OPTC_INPUT_SPARE_REGISTER)/sizeof(mmODM2_OPTC_INPUT_SPARE_REGISTER[0]), 0, 0 }, + { "mmODM3_OPTC_INPUT_GLOBAL_CONTROL", REG_MMIO, 0x1afa, 2, &mmODM3_OPTC_INPUT_GLOBAL_CONTROL[0], sizeof(mmODM3_OPTC_INPUT_GLOBAL_CONTROL)/sizeof(mmODM3_OPTC_INPUT_GLOBAL_CONTROL[0]), 0, 0 }, + { "mmODM3_OPTC_DATA_SOURCE_SELECT", REG_MMIO, 0x1afb, 2, &mmODM3_OPTC_DATA_SOURCE_SELECT[0], sizeof(mmODM3_OPTC_DATA_SOURCE_SELECT)/sizeof(mmODM3_OPTC_DATA_SOURCE_SELECT[0]), 0, 0 }, + { "mmODM3_OPTC_INPUT_CLOCK_CONTROL", REG_MMIO, 0x1afd, 2, &mmODM3_OPTC_INPUT_CLOCK_CONTROL[0], sizeof(mmODM3_OPTC_INPUT_CLOCK_CONTROL)/sizeof(mmODM3_OPTC_INPUT_CLOCK_CONTROL[0]), 0, 0 }, + { "mmODM3_OPTC_INPUT_SPARE_REGISTER", REG_MMIO, 0x1aff, 2, &mmODM3_OPTC_INPUT_SPARE_REGISTER[0], sizeof(mmODM3_OPTC_INPUT_SPARE_REGISTER)/sizeof(mmODM3_OPTC_INPUT_SPARE_REGISTER[0]), 0, 0 }, + { "mmODM4_OPTC_INPUT_GLOBAL_CONTROL", REG_MMIO, 0x1b0a, 2, &mmODM4_OPTC_INPUT_GLOBAL_CONTROL[0], sizeof(mmODM4_OPTC_INPUT_GLOBAL_CONTROL)/sizeof(mmODM4_OPTC_INPUT_GLOBAL_CONTROL[0]), 0, 0 }, + { "mmODM4_OPTC_DATA_SOURCE_SELECT", REG_MMIO, 0x1b0b, 2, &mmODM4_OPTC_DATA_SOURCE_SELECT[0], sizeof(mmODM4_OPTC_DATA_SOURCE_SELECT)/sizeof(mmODM4_OPTC_DATA_SOURCE_SELECT[0]), 0, 0 }, + { "mmODM4_OPTC_INPUT_CLOCK_CONTROL", REG_MMIO, 0x1b0d, 2, &mmODM4_OPTC_INPUT_CLOCK_CONTROL[0], sizeof(mmODM4_OPTC_INPUT_CLOCK_CONTROL)/sizeof(mmODM4_OPTC_INPUT_CLOCK_CONTROL[0]), 0, 0 }, + { "mmODM4_OPTC_INPUT_SPARE_REGISTER", REG_MMIO, 0x1b0f, 2, &mmODM4_OPTC_INPUT_SPARE_REGISTER[0], sizeof(mmODM4_OPTC_INPUT_SPARE_REGISTER)/sizeof(mmODM4_OPTC_INPUT_SPARE_REGISTER[0]), 0, 0 }, + { "mmODM5_OPTC_INPUT_GLOBAL_CONTROL", REG_MMIO, 0x1b1a, 2, &mmODM5_OPTC_INPUT_GLOBAL_CONTROL[0], sizeof(mmODM5_OPTC_INPUT_GLOBAL_CONTROL)/sizeof(mmODM5_OPTC_INPUT_GLOBAL_CONTROL[0]), 0, 0 }, + { "mmODM5_OPTC_DATA_SOURCE_SELECT", REG_MMIO, 0x1b1b, 2, &mmODM5_OPTC_DATA_SOURCE_SELECT[0], sizeof(mmODM5_OPTC_DATA_SOURCE_SELECT)/sizeof(mmODM5_OPTC_DATA_SOURCE_SELECT[0]), 0, 0 }, + { "mmODM5_OPTC_INPUT_CLOCK_CONTROL", REG_MMIO, 0x1b1d, 2, &mmODM5_OPTC_INPUT_CLOCK_CONTROL[0], sizeof(mmODM5_OPTC_INPUT_CLOCK_CONTROL)/sizeof(mmODM5_OPTC_INPUT_CLOCK_CONTROL[0]), 0, 0 }, + { "mmODM5_OPTC_INPUT_SPARE_REGISTER", REG_MMIO, 0x1b1f, 2, &mmODM5_OPTC_INPUT_SPARE_REGISTER[0], sizeof(mmODM5_OPTC_INPUT_SPARE_REGISTER)/sizeof(mmODM5_OPTC_INPUT_SPARE_REGISTER[0]), 0, 0 }, + { "mmOTG0_OTG_H_TOTAL", REG_MMIO, 0x1b2a, 2, &mmOTG0_OTG_H_TOTAL[0], sizeof(mmOTG0_OTG_H_TOTAL)/sizeof(mmOTG0_OTG_H_TOTAL[0]), 0, 0 }, + { "mmOTG0_OTG_H_BLANK_START_END", REG_MMIO, 0x1b2b, 2, &mmOTG0_OTG_H_BLANK_START_END[0], sizeof(mmOTG0_OTG_H_BLANK_START_END)/sizeof(mmOTG0_OTG_H_BLANK_START_END[0]), 0, 0 }, + { "mmOTG0_OTG_H_SYNC_A", REG_MMIO, 0x1b2c, 2, &mmOTG0_OTG_H_SYNC_A[0], sizeof(mmOTG0_OTG_H_SYNC_A)/sizeof(mmOTG0_OTG_H_SYNC_A[0]), 0, 0 }, + { "mmOTG0_OTG_H_SYNC_A_CNTL", REG_MMIO, 0x1b2d, 2, &mmOTG0_OTG_H_SYNC_A_CNTL[0], sizeof(mmOTG0_OTG_H_SYNC_A_CNTL)/sizeof(mmOTG0_OTG_H_SYNC_A_CNTL[0]), 0, 0 }, + { "mmOTG0_OTG_H_TIMING_CNTL", REG_MMIO, 0x1b2e, 2, &mmOTG0_OTG_H_TIMING_CNTL[0], sizeof(mmOTG0_OTG_H_TIMING_CNTL)/sizeof(mmOTG0_OTG_H_TIMING_CNTL[0]), 0, 0 }, + { "mmOTG0_OTG_V_TOTAL", REG_MMIO, 0x1b2f, 2, &mmOTG0_OTG_V_TOTAL[0], sizeof(mmOTG0_OTG_V_TOTAL)/sizeof(mmOTG0_OTG_V_TOTAL[0]), 0, 0 }, + { "mmOTG0_OTG_V_TOTAL_MIN", REG_MMIO, 0x1b30, 2, &mmOTG0_OTG_V_TOTAL_MIN[0], sizeof(mmOTG0_OTG_V_TOTAL_MIN)/sizeof(mmOTG0_OTG_V_TOTAL_MIN[0]), 0, 0 }, + { "mmOTG0_OTG_V_TOTAL_MAX", REG_MMIO, 0x1b31, 2, &mmOTG0_OTG_V_TOTAL_MAX[0], sizeof(mmOTG0_OTG_V_TOTAL_MAX)/sizeof(mmOTG0_OTG_V_TOTAL_MAX[0]), 0, 0 }, + { "mmOTG0_OTG_V_TOTAL_MID", REG_MMIO, 0x1b32, 2, &mmOTG0_OTG_V_TOTAL_MID[0], sizeof(mmOTG0_OTG_V_TOTAL_MID)/sizeof(mmOTG0_OTG_V_TOTAL_MID[0]), 0, 0 }, + { "mmOTG0_OTG_V_TOTAL_CONTROL", REG_MMIO, 0x1b33, 2, &mmOTG0_OTG_V_TOTAL_CONTROL[0], sizeof(mmOTG0_OTG_V_TOTAL_CONTROL)/sizeof(mmOTG0_OTG_V_TOTAL_CONTROL[0]), 0, 0 }, + { "mmOTG0_OTG_V_TOTAL_INT_STATUS", REG_MMIO, 0x1b34, 2, &mmOTG0_OTG_V_TOTAL_INT_STATUS[0], sizeof(mmOTG0_OTG_V_TOTAL_INT_STATUS)/sizeof(mmOTG0_OTG_V_TOTAL_INT_STATUS[0]), 0, 0 }, + { "mmOTG0_OTG_VSYNC_NOM_INT_STATUS", REG_MMIO, 0x1b35, 2, &mmOTG0_OTG_VSYNC_NOM_INT_STATUS[0], sizeof(mmOTG0_OTG_VSYNC_NOM_INT_STATUS)/sizeof(mmOTG0_OTG_VSYNC_NOM_INT_STATUS[0]), 0, 0 }, + { "mmOTG0_OTG_V_BLANK_START_END", REG_MMIO, 0x1b36, 2, &mmOTG0_OTG_V_BLANK_START_END[0], sizeof(mmOTG0_OTG_V_BLANK_START_END)/sizeof(mmOTG0_OTG_V_BLANK_START_END[0]), 0, 0 }, + { "mmOTG0_OTG_V_SYNC_A", REG_MMIO, 0x1b37, 2, &mmOTG0_OTG_V_SYNC_A[0], sizeof(mmOTG0_OTG_V_SYNC_A)/sizeof(mmOTG0_OTG_V_SYNC_A[0]), 0, 0 }, + { "mmOTG0_OTG_V_SYNC_A_CNTL", REG_MMIO, 0x1b38, 2, &mmOTG0_OTG_V_SYNC_A_CNTL[0], sizeof(mmOTG0_OTG_V_SYNC_A_CNTL)/sizeof(mmOTG0_OTG_V_SYNC_A_CNTL[0]), 0, 0 }, + { "mmOTG0_OTG_TRIGA_CNTL", REG_MMIO, 0x1b39, 2, &mmOTG0_OTG_TRIGA_CNTL[0], sizeof(mmOTG0_OTG_TRIGA_CNTL)/sizeof(mmOTG0_OTG_TRIGA_CNTL[0]), 0, 0 }, + { "mmOTG0_OTG_TRIGA_MANUAL_TRIG", REG_MMIO, 0x1b3a, 2, &mmOTG0_OTG_TRIGA_MANUAL_TRIG[0], sizeof(mmOTG0_OTG_TRIGA_MANUAL_TRIG)/sizeof(mmOTG0_OTG_TRIGA_MANUAL_TRIG[0]), 0, 0 }, + { "mmOTG0_OTG_TRIGB_CNTL", REG_MMIO, 0x1b3b, 2, &mmOTG0_OTG_TRIGB_CNTL[0], sizeof(mmOTG0_OTG_TRIGB_CNTL)/sizeof(mmOTG0_OTG_TRIGB_CNTL[0]), 0, 0 }, + { "mmOTG0_OTG_TRIGB_MANUAL_TRIG", REG_MMIO, 0x1b3c, 2, &mmOTG0_OTG_TRIGB_MANUAL_TRIG[0], sizeof(mmOTG0_OTG_TRIGB_MANUAL_TRIG)/sizeof(mmOTG0_OTG_TRIGB_MANUAL_TRIG[0]), 0, 0 }, + { "mmOTG0_OTG_FORCE_COUNT_NOW_CNTL", REG_MMIO, 0x1b3d, 2, &mmOTG0_OTG_FORCE_COUNT_NOW_CNTL[0], sizeof(mmOTG0_OTG_FORCE_COUNT_NOW_CNTL)/sizeof(mmOTG0_OTG_FORCE_COUNT_NOW_CNTL[0]), 0, 0 }, + { "mmOTG0_OTG_FLOW_CONTROL", REG_MMIO, 0x1b3e, 2, &mmOTG0_OTG_FLOW_CONTROL[0], sizeof(mmOTG0_OTG_FLOW_CONTROL)/sizeof(mmOTG0_OTG_FLOW_CONTROL[0]), 0, 0 }, + { "mmOTG0_OTG_STEREO_FORCE_NEXT_EYE", REG_MMIO, 0x1b3f, 2, &mmOTG0_OTG_STEREO_FORCE_NEXT_EYE[0], sizeof(mmOTG0_OTG_STEREO_FORCE_NEXT_EYE)/sizeof(mmOTG0_OTG_STEREO_FORCE_NEXT_EYE[0]), 0, 0 }, + { "mmOTG0_OTG_AVSYNC_COUNTER", REG_MMIO, 0x1b40, 2, &mmOTG0_OTG_AVSYNC_COUNTER[0], sizeof(mmOTG0_OTG_AVSYNC_COUNTER)/sizeof(mmOTG0_OTG_AVSYNC_COUNTER[0]), 0, 0 }, + { "mmOTG0_OTG_CONTROL", REG_MMIO, 0x1b41, 2, &mmOTG0_OTG_CONTROL[0], sizeof(mmOTG0_OTG_CONTROL)/sizeof(mmOTG0_OTG_CONTROL[0]), 0, 0 }, + { "mmOTG0_OTG_BLANK_CONTROL", REG_MMIO, 0x1b42, 2, &mmOTG0_OTG_BLANK_CONTROL[0], sizeof(mmOTG0_OTG_BLANK_CONTROL)/sizeof(mmOTG0_OTG_BLANK_CONTROL[0]), 0, 0 }, + { "mmOTG0_OTG_PIPE_ABORT_CONTROL", REG_MMIO, 0x1b43, 2, &mmOTG0_OTG_PIPE_ABORT_CONTROL[0], sizeof(mmOTG0_OTG_PIPE_ABORT_CONTROL)/sizeof(mmOTG0_OTG_PIPE_ABORT_CONTROL[0]), 0, 0 }, + { "mmOTG0_OTG_INTERLACE_CONTROL", REG_MMIO, 0x1b44, 2, &mmOTG0_OTG_INTERLACE_CONTROL[0], sizeof(mmOTG0_OTG_INTERLACE_CONTROL)/sizeof(mmOTG0_OTG_INTERLACE_CONTROL[0]), 0, 0 }, + { "mmOTG0_OTG_INTERLACE_STATUS", REG_MMIO, 0x1b45, 2, &mmOTG0_OTG_INTERLACE_STATUS[0], sizeof(mmOTG0_OTG_INTERLACE_STATUS)/sizeof(mmOTG0_OTG_INTERLACE_STATUS[0]), 0, 0 }, + { "mmOTG0_OTG_FIELD_INDICATION_CONTROL", REG_MMIO, 0x1b46, 2, &mmOTG0_OTG_FIELD_INDICATION_CONTROL[0], sizeof(mmOTG0_OTG_FIELD_INDICATION_CONTROL)/sizeof(mmOTG0_OTG_FIELD_INDICATION_CONTROL[0]), 0, 0 }, + { "mmOTG0_OTG_PIXEL_DATA_READBACK0", REG_MMIO, 0x1b47, 2, &mmOTG0_OTG_PIXEL_DATA_READBACK0[0], sizeof(mmOTG0_OTG_PIXEL_DATA_READBACK0)/sizeof(mmOTG0_OTG_PIXEL_DATA_READBACK0[0]), 0, 0 }, + { "mmOTG0_OTG_PIXEL_DATA_READBACK1", REG_MMIO, 0x1b48, 2, &mmOTG0_OTG_PIXEL_DATA_READBACK1[0], sizeof(mmOTG0_OTG_PIXEL_DATA_READBACK1)/sizeof(mmOTG0_OTG_PIXEL_DATA_READBACK1[0]), 0, 0 }, + { "mmOTG0_OTG_STATUS", REG_MMIO, 0x1b49, 2, &mmOTG0_OTG_STATUS[0], sizeof(mmOTG0_OTG_STATUS)/sizeof(mmOTG0_OTG_STATUS[0]), 0, 0 }, + { "mmOTG0_OTG_STATUS_POSITION", REG_MMIO, 0x1b4a, 2, &mmOTG0_OTG_STATUS_POSITION[0], sizeof(mmOTG0_OTG_STATUS_POSITION)/sizeof(mmOTG0_OTG_STATUS_POSITION[0]), 0, 0 }, + { "mmOTG0_OTG_NOM_VERT_POSITION", REG_MMIO, 0x1b4b, 2, &mmOTG0_OTG_NOM_VERT_POSITION[0], sizeof(mmOTG0_OTG_NOM_VERT_POSITION)/sizeof(mmOTG0_OTG_NOM_VERT_POSITION[0]), 0, 0 }, + { "mmOTG0_OTG_STATUS_FRAME_COUNT", REG_MMIO, 0x1b4c, 2, &mmOTG0_OTG_STATUS_FRAME_COUNT[0], sizeof(mmOTG0_OTG_STATUS_FRAME_COUNT)/sizeof(mmOTG0_OTG_STATUS_FRAME_COUNT[0]), 0, 0 }, + { "mmOTG0_OTG_STATUS_VF_COUNT", REG_MMIO, 0x1b4d, 2, &mmOTG0_OTG_STATUS_VF_COUNT[0], sizeof(mmOTG0_OTG_STATUS_VF_COUNT)/sizeof(mmOTG0_OTG_STATUS_VF_COUNT[0]), 0, 0 }, + { "mmOTG0_OTG_STATUS_HV_COUNT", REG_MMIO, 0x1b4e, 2, &mmOTG0_OTG_STATUS_HV_COUNT[0], sizeof(mmOTG0_OTG_STATUS_HV_COUNT)/sizeof(mmOTG0_OTG_STATUS_HV_COUNT[0]), 0, 0 }, + { "mmOTG0_OTG_COUNT_CONTROL", REG_MMIO, 0x1b4f, 2, &mmOTG0_OTG_COUNT_CONTROL[0], sizeof(mmOTG0_OTG_COUNT_CONTROL)/sizeof(mmOTG0_OTG_COUNT_CONTROL[0]), 0, 0 }, + { "mmOTG0_OTG_COUNT_RESET", REG_MMIO, 0x1b50, 2, &mmOTG0_OTG_COUNT_RESET[0], sizeof(mmOTG0_OTG_COUNT_RESET)/sizeof(mmOTG0_OTG_COUNT_RESET[0]), 0, 0 }, + { "mmOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE", REG_MMIO, 0x1b51, 2, &mmOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE[0], sizeof(mmOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE)/sizeof(mmOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE[0]), 0, 0 }, + { "mmOTG0_OTG_VERT_SYNC_CONTROL", REG_MMIO, 0x1b52, 2, &mmOTG0_OTG_VERT_SYNC_CONTROL[0], sizeof(mmOTG0_OTG_VERT_SYNC_CONTROL)/sizeof(mmOTG0_OTG_VERT_SYNC_CONTROL[0]), 0, 0 }, + { "mmOTG0_OTG_STEREO_STATUS", REG_MMIO, 0x1b53, 2, &mmOTG0_OTG_STEREO_STATUS[0], sizeof(mmOTG0_OTG_STEREO_STATUS)/sizeof(mmOTG0_OTG_STEREO_STATUS[0]), 0, 0 }, + { "mmOTG0_OTG_STEREO_CONTROL", REG_MMIO, 0x1b54, 2, &mmOTG0_OTG_STEREO_CONTROL[0], sizeof(mmOTG0_OTG_STEREO_CONTROL)/sizeof(mmOTG0_OTG_STEREO_CONTROL[0]), 0, 0 }, + { "mmOTG0_OTG_SNAPSHOT_STATUS", REG_MMIO, 0x1b55, 2, &mmOTG0_OTG_SNAPSHOT_STATUS[0], sizeof(mmOTG0_OTG_SNAPSHOT_STATUS)/sizeof(mmOTG0_OTG_SNAPSHOT_STATUS[0]), 0, 0 }, + { "mmOTG0_OTG_SNAPSHOT_CONTROL", REG_MMIO, 0x1b56, 2, &mmOTG0_OTG_SNAPSHOT_CONTROL[0], sizeof(mmOTG0_OTG_SNAPSHOT_CONTROL)/sizeof(mmOTG0_OTG_SNAPSHOT_CONTROL[0]), 0, 0 }, + { "mmOTG0_OTG_SNAPSHOT_POSITION", REG_MMIO, 0x1b57, 2, &mmOTG0_OTG_SNAPSHOT_POSITION[0], sizeof(mmOTG0_OTG_SNAPSHOT_POSITION)/sizeof(mmOTG0_OTG_SNAPSHOT_POSITION[0]), 0, 0 }, + { "mmOTG0_OTG_SNAPSHOT_FRAME", REG_MMIO, 0x1b58, 2, &mmOTG0_OTG_SNAPSHOT_FRAME[0], sizeof(mmOTG0_OTG_SNAPSHOT_FRAME)/sizeof(mmOTG0_OTG_SNAPSHOT_FRAME[0]), 0, 0 }, + { "mmOTG0_OTG_INTERRUPT_CONTROL", REG_MMIO, 0x1b59, 2, &mmOTG0_OTG_INTERRUPT_CONTROL[0], sizeof(mmOTG0_OTG_INTERRUPT_CONTROL)/sizeof(mmOTG0_OTG_INTERRUPT_CONTROL[0]), 0, 0 }, + { "mmOTG0_OTG_UPDATE_LOCK", REG_MMIO, 0x1b5a, 2, &mmOTG0_OTG_UPDATE_LOCK[0], sizeof(mmOTG0_OTG_UPDATE_LOCK)/sizeof(mmOTG0_OTG_UPDATE_LOCK[0]), 0, 0 }, + { "mmOTG0_OTG_DOUBLE_BUFFER_CONTROL", REG_MMIO, 0x1b5b, 2, &mmOTG0_OTG_DOUBLE_BUFFER_CONTROL[0], sizeof(mmOTG0_OTG_DOUBLE_BUFFER_CONTROL)/sizeof(mmOTG0_OTG_DOUBLE_BUFFER_CONTROL[0]), 0, 0 }, + { "mmOTG0_OTG_TEST_PATTERN_CONTROL", REG_MMIO, 0x1b5c, 2, &mmOTG0_OTG_TEST_PATTERN_CONTROL[0], sizeof(mmOTG0_OTG_TEST_PATTERN_CONTROL)/sizeof(mmOTG0_OTG_TEST_PATTERN_CONTROL[0]), 0, 0 }, + { "mmOTG0_OTG_TEST_PATTERN_PARAMETERS", REG_MMIO, 0x1b5d, 2, &mmOTG0_OTG_TEST_PATTERN_PARAMETERS[0], sizeof(mmOTG0_OTG_TEST_PATTERN_PARAMETERS)/sizeof(mmOTG0_OTG_TEST_PATTERN_PARAMETERS[0]), 0, 0 }, + { "mmOTG0_OTG_TEST_PATTERN_COLOR", REG_MMIO, 0x1b5e, 2, &mmOTG0_OTG_TEST_PATTERN_COLOR[0], sizeof(mmOTG0_OTG_TEST_PATTERN_COLOR)/sizeof(mmOTG0_OTG_TEST_PATTERN_COLOR[0]), 0, 0 }, + { "mmOTG0_OTG_MASTER_EN", REG_MMIO, 0x1b5f, 2, &mmOTG0_OTG_MASTER_EN[0], sizeof(mmOTG0_OTG_MASTER_EN)/sizeof(mmOTG0_OTG_MASTER_EN[0]), 0, 0 }, + { "mmOTG0_OTG_BLANK_DATA_COLOR", REG_MMIO, 0x1b61, 2, &mmOTG0_OTG_BLANK_DATA_COLOR[0], sizeof(mmOTG0_OTG_BLANK_DATA_COLOR)/sizeof(mmOTG0_OTG_BLANK_DATA_COLOR[0]), 0, 0 }, + { "mmOTG0_OTG_BLANK_DATA_COLOR_EXT", REG_MMIO, 0x1b62, 2, &mmOTG0_OTG_BLANK_DATA_COLOR_EXT[0], sizeof(mmOTG0_OTG_BLANK_DATA_COLOR_EXT)/sizeof(mmOTG0_OTG_BLANK_DATA_COLOR_EXT[0]), 0, 0 }, + { "mmOTG0_OTG_BLACK_COLOR", REG_MMIO, 0x1b63, 2, &mmOTG0_OTG_BLACK_COLOR[0], sizeof(mmOTG0_OTG_BLACK_COLOR)/sizeof(mmOTG0_OTG_BLACK_COLOR[0]), 0, 0 }, + { "mmOTG0_OTG_BLACK_COLOR_EXT", REG_MMIO, 0x1b64, 2, &mmOTG0_OTG_BLACK_COLOR_EXT[0], sizeof(mmOTG0_OTG_BLACK_COLOR_EXT)/sizeof(mmOTG0_OTG_BLACK_COLOR_EXT[0]), 0, 0 }, + { "mmOTG0_OTG_VERTICAL_INTERRUPT0_POSITION", REG_MMIO, 0x1b65, 2, &mmOTG0_OTG_VERTICAL_INTERRUPT0_POSITION[0], sizeof(mmOTG0_OTG_VERTICAL_INTERRUPT0_POSITION)/sizeof(mmOTG0_OTG_VERTICAL_INTERRUPT0_POSITION[0]), 0, 0 }, + { "mmOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL", REG_MMIO, 0x1b66, 2, &mmOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL[0], sizeof(mmOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL)/sizeof(mmOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL[0]), 0, 0 }, + { "mmOTG0_OTG_VERTICAL_INTERRUPT1_POSITION", REG_MMIO, 0x1b67, 2, &mmOTG0_OTG_VERTICAL_INTERRUPT1_POSITION[0], sizeof(mmOTG0_OTG_VERTICAL_INTERRUPT1_POSITION)/sizeof(mmOTG0_OTG_VERTICAL_INTERRUPT1_POSITION[0]), 0, 0 }, + { "mmOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL", REG_MMIO, 0x1b68, 2, &mmOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL[0], sizeof(mmOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL)/sizeof(mmOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL[0]), 0, 0 }, + { "mmOTG0_OTG_VERTICAL_INTERRUPT2_POSITION", REG_MMIO, 0x1b69, 2, &mmOTG0_OTG_VERTICAL_INTERRUPT2_POSITION[0], sizeof(mmOTG0_OTG_VERTICAL_INTERRUPT2_POSITION)/sizeof(mmOTG0_OTG_VERTICAL_INTERRUPT2_POSITION[0]), 0, 0 }, + { "mmOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL", REG_MMIO, 0x1b6a, 2, &mmOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL[0], sizeof(mmOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL)/sizeof(mmOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL[0]), 0, 0 }, + { "mmOTG0_OTG_CRC_CNTL", REG_MMIO, 0x1b6b, 2, &mmOTG0_OTG_CRC_CNTL[0], sizeof(mmOTG0_OTG_CRC_CNTL)/sizeof(mmOTG0_OTG_CRC_CNTL[0]), 0, 0 }, + { "mmOTG0_OTG_CRC0_WINDOWA_X_CONTROL", REG_MMIO, 0x1b6c, 2, &mmOTG0_OTG_CRC0_WINDOWA_X_CONTROL[0], sizeof(mmOTG0_OTG_CRC0_WINDOWA_X_CONTROL)/sizeof(mmOTG0_OTG_CRC0_WINDOWA_X_CONTROL[0]), 0, 0 }, + { "mmOTG0_OTG_CRC0_WINDOWA_Y_CONTROL", REG_MMIO, 0x1b6d, 2, &mmOTG0_OTG_CRC0_WINDOWA_Y_CONTROL[0], sizeof(mmOTG0_OTG_CRC0_WINDOWA_Y_CONTROL)/sizeof(mmOTG0_OTG_CRC0_WINDOWA_Y_CONTROL[0]), 0, 0 }, + { "mmOTG0_OTG_CRC0_WINDOWB_X_CONTROL", REG_MMIO, 0x1b6e, 2, &mmOTG0_OTG_CRC0_WINDOWB_X_CONTROL[0], sizeof(mmOTG0_OTG_CRC0_WINDOWB_X_CONTROL)/sizeof(mmOTG0_OTG_CRC0_WINDOWB_X_CONTROL[0]), 0, 0 }, + { "mmOTG0_OTG_CRC0_WINDOWB_Y_CONTROL", REG_MMIO, 0x1b6f, 2, &mmOTG0_OTG_CRC0_WINDOWB_Y_CONTROL[0], sizeof(mmOTG0_OTG_CRC0_WINDOWB_Y_CONTROL)/sizeof(mmOTG0_OTG_CRC0_WINDOWB_Y_CONTROL[0]), 0, 0 }, + { "mmOTG0_OTG_CRC0_DATA_RG", REG_MMIO, 0x1b70, 2, &mmOTG0_OTG_CRC0_DATA_RG[0], sizeof(mmOTG0_OTG_CRC0_DATA_RG)/sizeof(mmOTG0_OTG_CRC0_DATA_RG[0]), 0, 0 }, + { "mmOTG0_OTG_CRC0_DATA_B", REG_MMIO, 0x1b71, 2, &mmOTG0_OTG_CRC0_DATA_B[0], sizeof(mmOTG0_OTG_CRC0_DATA_B)/sizeof(mmOTG0_OTG_CRC0_DATA_B[0]), 0, 0 }, + { "mmOTG0_OTG_CRC1_WINDOWA_X_CONTROL", REG_MMIO, 0x1b72, 2, &mmOTG0_OTG_CRC1_WINDOWA_X_CONTROL[0], sizeof(mmOTG0_OTG_CRC1_WINDOWA_X_CONTROL)/sizeof(mmOTG0_OTG_CRC1_WINDOWA_X_CONTROL[0]), 0, 0 }, + { "mmOTG0_OTG_CRC1_WINDOWA_Y_CONTROL", REG_MMIO, 0x1b73, 2, &mmOTG0_OTG_CRC1_WINDOWA_Y_CONTROL[0], sizeof(mmOTG0_OTG_CRC1_WINDOWA_Y_CONTROL)/sizeof(mmOTG0_OTG_CRC1_WINDOWA_Y_CONTROL[0]), 0, 0 }, + { "mmOTG0_OTG_CRC1_WINDOWB_X_CONTROL", REG_MMIO, 0x1b74, 2, &mmOTG0_OTG_CRC1_WINDOWB_X_CONTROL[0], sizeof(mmOTG0_OTG_CRC1_WINDOWB_X_CONTROL)/sizeof(mmOTG0_OTG_CRC1_WINDOWB_X_CONTROL[0]), 0, 0 }, + { "mmOTG0_OTG_CRC1_WINDOWB_Y_CONTROL", REG_MMIO, 0x1b75, 2, &mmOTG0_OTG_CRC1_WINDOWB_Y_CONTROL[0], sizeof(mmOTG0_OTG_CRC1_WINDOWB_Y_CONTROL)/sizeof(mmOTG0_OTG_CRC1_WINDOWB_Y_CONTROL[0]), 0, 0 }, + { "mmOTG0_OTG_CRC1_DATA_RG", REG_MMIO, 0x1b76, 2, &mmOTG0_OTG_CRC1_DATA_RG[0], sizeof(mmOTG0_OTG_CRC1_DATA_RG)/sizeof(mmOTG0_OTG_CRC1_DATA_RG[0]), 0, 0 }, + { "mmOTG0_OTG_CRC1_DATA_B", REG_MMIO, 0x1b77, 2, &mmOTG0_OTG_CRC1_DATA_B[0], sizeof(mmOTG0_OTG_CRC1_DATA_B)/sizeof(mmOTG0_OTG_CRC1_DATA_B[0]), 0, 0 }, + { "mmOTG0_OTG_CRC2_DATA_RG", REG_MMIO, 0x1b78, 2, &mmOTG0_OTG_CRC2_DATA_RG[0], sizeof(mmOTG0_OTG_CRC2_DATA_RG)/sizeof(mmOTG0_OTG_CRC2_DATA_RG[0]), 0, 0 }, + { "mmOTG0_OTG_CRC2_DATA_B", REG_MMIO, 0x1b79, 2, &mmOTG0_OTG_CRC2_DATA_B[0], sizeof(mmOTG0_OTG_CRC2_DATA_B)/sizeof(mmOTG0_OTG_CRC2_DATA_B[0]), 0, 0 }, + { "mmOTG0_OTG_CRC3_DATA_RG", REG_MMIO, 0x1b7a, 2, &mmOTG0_OTG_CRC3_DATA_RG[0], sizeof(mmOTG0_OTG_CRC3_DATA_RG)/sizeof(mmOTG0_OTG_CRC3_DATA_RG[0]), 0, 0 }, + { "mmOTG0_OTG_CRC3_DATA_B", REG_MMIO, 0x1b7b, 2, &mmOTG0_OTG_CRC3_DATA_B[0], sizeof(mmOTG0_OTG_CRC3_DATA_B)/sizeof(mmOTG0_OTG_CRC3_DATA_B[0]), 0, 0 }, + { "mmOTG0_OTG_CRC_SIG_RED_GREEN_MASK", REG_MMIO, 0x1b7c, 2, &mmOTG0_OTG_CRC_SIG_RED_GREEN_MASK[0], sizeof(mmOTG0_OTG_CRC_SIG_RED_GREEN_MASK)/sizeof(mmOTG0_OTG_CRC_SIG_RED_GREEN_MASK[0]), 0, 0 }, + { "mmOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK", REG_MMIO, 0x1b7d, 2, &mmOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK[0], sizeof(mmOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK)/sizeof(mmOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK[0]), 0, 0 }, + { "mmOTG0_OTG_STATIC_SCREEN_CONTROL", REG_MMIO, 0x1b84, 2, &mmOTG0_OTG_STATIC_SCREEN_CONTROL[0], sizeof(mmOTG0_OTG_STATIC_SCREEN_CONTROL)/sizeof(mmOTG0_OTG_STATIC_SCREEN_CONTROL[0]), 0, 0 }, + { "mmOTG0_OTG_3D_STRUCTURE_CONTROL", REG_MMIO, 0x1b85, 2, &mmOTG0_OTG_3D_STRUCTURE_CONTROL[0], sizeof(mmOTG0_OTG_3D_STRUCTURE_CONTROL)/sizeof(mmOTG0_OTG_3D_STRUCTURE_CONTROL[0]), 0, 0 }, + { "mmOTG0_OTG_GSL_VSYNC_GAP", REG_MMIO, 0x1b86, 2, &mmOTG0_OTG_GSL_VSYNC_GAP[0], sizeof(mmOTG0_OTG_GSL_VSYNC_GAP)/sizeof(mmOTG0_OTG_GSL_VSYNC_GAP[0]), 0, 0 }, + { "mmOTG0_OTG_MASTER_UPDATE_MODE", REG_MMIO, 0x1b87, 2, &mmOTG0_OTG_MASTER_UPDATE_MODE[0], sizeof(mmOTG0_OTG_MASTER_UPDATE_MODE)/sizeof(mmOTG0_OTG_MASTER_UPDATE_MODE[0]), 0, 0 }, + { "mmOTG0_OTG_CLOCK_CONTROL", REG_MMIO, 0x1b88, 2, &mmOTG0_OTG_CLOCK_CONTROL[0], sizeof(mmOTG0_OTG_CLOCK_CONTROL)/sizeof(mmOTG0_OTG_CLOCK_CONTROL[0]), 0, 0 }, + { "mmOTG0_OTG_VSTARTUP_PARAM", REG_MMIO, 0x1b89, 2, &mmOTG0_OTG_VSTARTUP_PARAM[0], sizeof(mmOTG0_OTG_VSTARTUP_PARAM)/sizeof(mmOTG0_OTG_VSTARTUP_PARAM[0]), 0, 0 }, + { "mmOTG0_OTG_VUPDATE_PARAM", REG_MMIO, 0x1b8a, 2, &mmOTG0_OTG_VUPDATE_PARAM[0], sizeof(mmOTG0_OTG_VUPDATE_PARAM)/sizeof(mmOTG0_OTG_VUPDATE_PARAM[0]), 0, 0 }, + { "mmOTG0_OTG_VREADY_PARAM", REG_MMIO, 0x1b8b, 2, &mmOTG0_OTG_VREADY_PARAM[0], sizeof(mmOTG0_OTG_VREADY_PARAM)/sizeof(mmOTG0_OTG_VREADY_PARAM[0]), 0, 0 }, + { "mmOTG0_OTG_GLOBAL_SYNC_STATUS", REG_MMIO, 0x1b8c, 2, &mmOTG0_OTG_GLOBAL_SYNC_STATUS[0], sizeof(mmOTG0_OTG_GLOBAL_SYNC_STATUS)/sizeof(mmOTG0_OTG_GLOBAL_SYNC_STATUS[0]), 0, 0 }, + { "mmOTG0_OTG_MASTER_UPDATE_LOCK", REG_MMIO, 0x1b8d, 2, &mmOTG0_OTG_MASTER_UPDATE_LOCK[0], sizeof(mmOTG0_OTG_MASTER_UPDATE_LOCK)/sizeof(mmOTG0_OTG_MASTER_UPDATE_LOCK[0]), 0, 0 }, + { "mmOTG0_OTG_GSL_CONTROL", REG_MMIO, 0x1b8e, 2, &mmOTG0_OTG_GSL_CONTROL[0], sizeof(mmOTG0_OTG_GSL_CONTROL)/sizeof(mmOTG0_OTG_GSL_CONTROL[0]), 0, 0 }, + { "mmOTG0_OTG_GSL_WINDOW_X", REG_MMIO, 0x1b8f, 2, &mmOTG0_OTG_GSL_WINDOW_X[0], sizeof(mmOTG0_OTG_GSL_WINDOW_X)/sizeof(mmOTG0_OTG_GSL_WINDOW_X[0]), 0, 0 }, + { "mmOTG0_OTG_GSL_WINDOW_Y", REG_MMIO, 0x1b90, 2, &mmOTG0_OTG_GSL_WINDOW_Y[0], sizeof(mmOTG0_OTG_GSL_WINDOW_Y)/sizeof(mmOTG0_OTG_GSL_WINDOW_Y[0]), 0, 0 }, + { "mmOTG0_OTG_VUPDATE_KEEPOUT", REG_MMIO, 0x1b91, 2, &mmOTG0_OTG_VUPDATE_KEEPOUT[0], sizeof(mmOTG0_OTG_VUPDATE_KEEPOUT)/sizeof(mmOTG0_OTG_VUPDATE_KEEPOUT[0]), 0, 0 }, + { "mmOTG0_OTG_GLOBAL_CONTROL0", REG_MMIO, 0x1b92, 2, &mmOTG0_OTG_GLOBAL_CONTROL0[0], sizeof(mmOTG0_OTG_GLOBAL_CONTROL0)/sizeof(mmOTG0_OTG_GLOBAL_CONTROL0[0]), 0, 0 }, + { "mmOTG0_OTG_GLOBAL_CONTROL1", REG_MMIO, 0x1b93, 2, &mmOTG0_OTG_GLOBAL_CONTROL1[0], sizeof(mmOTG0_OTG_GLOBAL_CONTROL1)/sizeof(mmOTG0_OTG_GLOBAL_CONTROL1[0]), 0, 0 }, + { "mmOTG0_OTG_GLOBAL_CONTROL2", REG_MMIO, 0x1b94, 2, &mmOTG0_OTG_GLOBAL_CONTROL2[0], sizeof(mmOTG0_OTG_GLOBAL_CONTROL2)/sizeof(mmOTG0_OTG_GLOBAL_CONTROL2[0]), 0, 0 }, + { "mmOTG0_OTG_GLOBAL_CONTROL3", REG_MMIO, 0x1b95, 2, &mmOTG0_OTG_GLOBAL_CONTROL3[0], sizeof(mmOTG0_OTG_GLOBAL_CONTROL3)/sizeof(mmOTG0_OTG_GLOBAL_CONTROL3[0]), 0, 0 }, + { "mmOTG0_OTG_TRIG_MANUAL_CONTROL", REG_MMIO, 0x1b96, 2, &mmOTG0_OTG_TRIG_MANUAL_CONTROL[0], sizeof(mmOTG0_OTG_TRIG_MANUAL_CONTROL)/sizeof(mmOTG0_OTG_TRIG_MANUAL_CONTROL[0]), 0, 0 }, + { "mmOTG0_OTG_MANUAL_FLOW_CONTROL", REG_MMIO, 0x1b97, 2, &mmOTG0_OTG_MANUAL_FLOW_CONTROL[0], sizeof(mmOTG0_OTG_MANUAL_FLOW_CONTROL)/sizeof(mmOTG0_OTG_MANUAL_FLOW_CONTROL[0]), 0, 0 }, + { "mmOTG0_OTG_RANGE_TIMING_INT_STATUS", REG_MMIO, 0x1b98, 2, &mmOTG0_OTG_RANGE_TIMING_INT_STATUS[0], sizeof(mmOTG0_OTG_RANGE_TIMING_INT_STATUS)/sizeof(mmOTG0_OTG_RANGE_TIMING_INT_STATUS[0]), 0, 0 }, + { "mmOTG0_OTG_DRR_CONTROL", REG_MMIO, 0x1b99, 2, &mmOTG0_OTG_DRR_CONTROL[0], sizeof(mmOTG0_OTG_DRR_CONTROL)/sizeof(mmOTG0_OTG_DRR_CONTROL[0]), 0, 0 }, + { "mmOTG0_OTG_REQUEST_CONTROL", REG_MMIO, 0x1b9a, 2, &mmOTG0_OTG_REQUEST_CONTROL[0], sizeof(mmOTG0_OTG_REQUEST_CONTROL)/sizeof(mmOTG0_OTG_REQUEST_CONTROL[0]), 0, 0 }, + { "mmOTG0_OTG_SPARE_REGISTER", REG_MMIO, 0x1b9b, 2, &mmOTG0_OTG_SPARE_REGISTER[0], sizeof(mmOTG0_OTG_SPARE_REGISTER)/sizeof(mmOTG0_OTG_SPARE_REGISTER[0]), 0, 0 }, + { "mmOTG1_OTG_H_TOTAL", REG_MMIO, 0x1baa, 2, &mmOTG1_OTG_H_TOTAL[0], sizeof(mmOTG1_OTG_H_TOTAL)/sizeof(mmOTG1_OTG_H_TOTAL[0]), 0, 0 }, + { "mmOTG1_OTG_H_BLANK_START_END", REG_MMIO, 0x1bab, 2, &mmOTG1_OTG_H_BLANK_START_END[0], sizeof(mmOTG1_OTG_H_BLANK_START_END)/sizeof(mmOTG1_OTG_H_BLANK_START_END[0]), 0, 0 }, + { "mmOTG1_OTG_H_SYNC_A", REG_MMIO, 0x1bac, 2, &mmOTG1_OTG_H_SYNC_A[0], sizeof(mmOTG1_OTG_H_SYNC_A)/sizeof(mmOTG1_OTG_H_SYNC_A[0]), 0, 0 }, + { "mmOTG1_OTG_H_SYNC_A_CNTL", REG_MMIO, 0x1bad, 2, &mmOTG1_OTG_H_SYNC_A_CNTL[0], sizeof(mmOTG1_OTG_H_SYNC_A_CNTL)/sizeof(mmOTG1_OTG_H_SYNC_A_CNTL[0]), 0, 0 }, + { "mmOTG1_OTG_H_TIMING_CNTL", REG_MMIO, 0x1bae, 2, &mmOTG1_OTG_H_TIMING_CNTL[0], sizeof(mmOTG1_OTG_H_TIMING_CNTL)/sizeof(mmOTG1_OTG_H_TIMING_CNTL[0]), 0, 0 }, + { "mmOTG1_OTG_V_TOTAL", REG_MMIO, 0x1baf, 2, &mmOTG1_OTG_V_TOTAL[0], sizeof(mmOTG1_OTG_V_TOTAL)/sizeof(mmOTG1_OTG_V_TOTAL[0]), 0, 0 }, + { "mmOTG1_OTG_V_TOTAL_MIN", REG_MMIO, 0x1bb0, 2, &mmOTG1_OTG_V_TOTAL_MIN[0], sizeof(mmOTG1_OTG_V_TOTAL_MIN)/sizeof(mmOTG1_OTG_V_TOTAL_MIN[0]), 0, 0 }, + { "mmOTG1_OTG_V_TOTAL_MAX", REG_MMIO, 0x1bb1, 2, &mmOTG1_OTG_V_TOTAL_MAX[0], sizeof(mmOTG1_OTG_V_TOTAL_MAX)/sizeof(mmOTG1_OTG_V_TOTAL_MAX[0]), 0, 0 }, + { "mmOTG1_OTG_V_TOTAL_MID", REG_MMIO, 0x1bb2, 2, &mmOTG1_OTG_V_TOTAL_MID[0], sizeof(mmOTG1_OTG_V_TOTAL_MID)/sizeof(mmOTG1_OTG_V_TOTAL_MID[0]), 0, 0 }, + { "mmOTG1_OTG_V_TOTAL_CONTROL", REG_MMIO, 0x1bb3, 2, &mmOTG1_OTG_V_TOTAL_CONTROL[0], sizeof(mmOTG1_OTG_V_TOTAL_CONTROL)/sizeof(mmOTG1_OTG_V_TOTAL_CONTROL[0]), 0, 0 }, + { "mmOTG1_OTG_V_TOTAL_INT_STATUS", REG_MMIO, 0x1bb4, 2, &mmOTG1_OTG_V_TOTAL_INT_STATUS[0], sizeof(mmOTG1_OTG_V_TOTAL_INT_STATUS)/sizeof(mmOTG1_OTG_V_TOTAL_INT_STATUS[0]), 0, 0 }, + { "mmOTG1_OTG_VSYNC_NOM_INT_STATUS", REG_MMIO, 0x1bb5, 2, &mmOTG1_OTG_VSYNC_NOM_INT_STATUS[0], sizeof(mmOTG1_OTG_VSYNC_NOM_INT_STATUS)/sizeof(mmOTG1_OTG_VSYNC_NOM_INT_STATUS[0]), 0, 0 }, + { "mmOTG1_OTG_V_BLANK_START_END", REG_MMIO, 0x1bb6, 2, &mmOTG1_OTG_V_BLANK_START_END[0], sizeof(mmOTG1_OTG_V_BLANK_START_END)/sizeof(mmOTG1_OTG_V_BLANK_START_END[0]), 0, 0 }, + { "mmOTG1_OTG_V_SYNC_A", REG_MMIO, 0x1bb7, 2, &mmOTG1_OTG_V_SYNC_A[0], sizeof(mmOTG1_OTG_V_SYNC_A)/sizeof(mmOTG1_OTG_V_SYNC_A[0]), 0, 0 }, + { "mmOTG1_OTG_V_SYNC_A_CNTL", REG_MMIO, 0x1bb8, 2, &mmOTG1_OTG_V_SYNC_A_CNTL[0], sizeof(mmOTG1_OTG_V_SYNC_A_CNTL)/sizeof(mmOTG1_OTG_V_SYNC_A_CNTL[0]), 0, 0 }, + { "mmOTG1_OTG_TRIGA_CNTL", REG_MMIO, 0x1bb9, 2, &mmOTG1_OTG_TRIGA_CNTL[0], sizeof(mmOTG1_OTG_TRIGA_CNTL)/sizeof(mmOTG1_OTG_TRIGA_CNTL[0]), 0, 0 }, + { "mmOTG1_OTG_TRIGA_MANUAL_TRIG", REG_MMIO, 0x1bba, 2, &mmOTG1_OTG_TRIGA_MANUAL_TRIG[0], sizeof(mmOTG1_OTG_TRIGA_MANUAL_TRIG)/sizeof(mmOTG1_OTG_TRIGA_MANUAL_TRIG[0]), 0, 0 }, + { "mmOTG1_OTG_TRIGB_CNTL", REG_MMIO, 0x1bbb, 2, &mmOTG1_OTG_TRIGB_CNTL[0], sizeof(mmOTG1_OTG_TRIGB_CNTL)/sizeof(mmOTG1_OTG_TRIGB_CNTL[0]), 0, 0 }, + { "mmOTG1_OTG_TRIGB_MANUAL_TRIG", REG_MMIO, 0x1bbc, 2, &mmOTG1_OTG_TRIGB_MANUAL_TRIG[0], sizeof(mmOTG1_OTG_TRIGB_MANUAL_TRIG)/sizeof(mmOTG1_OTG_TRIGB_MANUAL_TRIG[0]), 0, 0 }, + { "mmOTG1_OTG_FORCE_COUNT_NOW_CNTL", REG_MMIO, 0x1bbd, 2, &mmOTG1_OTG_FORCE_COUNT_NOW_CNTL[0], sizeof(mmOTG1_OTG_FORCE_COUNT_NOW_CNTL)/sizeof(mmOTG1_OTG_FORCE_COUNT_NOW_CNTL[0]), 0, 0 }, + { "mmOTG1_OTG_FLOW_CONTROL", REG_MMIO, 0x1bbe, 2, &mmOTG1_OTG_FLOW_CONTROL[0], sizeof(mmOTG1_OTG_FLOW_CONTROL)/sizeof(mmOTG1_OTG_FLOW_CONTROL[0]), 0, 0 }, + { "mmOTG1_OTG_STEREO_FORCE_NEXT_EYE", REG_MMIO, 0x1bbf, 2, &mmOTG1_OTG_STEREO_FORCE_NEXT_EYE[0], sizeof(mmOTG1_OTG_STEREO_FORCE_NEXT_EYE)/sizeof(mmOTG1_OTG_STEREO_FORCE_NEXT_EYE[0]), 0, 0 }, + { "mmOTG1_OTG_AVSYNC_COUNTER", REG_MMIO, 0x1bc0, 2, &mmOTG1_OTG_AVSYNC_COUNTER[0], sizeof(mmOTG1_OTG_AVSYNC_COUNTER)/sizeof(mmOTG1_OTG_AVSYNC_COUNTER[0]), 0, 0 }, + { "mmOTG1_OTG_CONTROL", REG_MMIO, 0x1bc1, 2, &mmOTG1_OTG_CONTROL[0], sizeof(mmOTG1_OTG_CONTROL)/sizeof(mmOTG1_OTG_CONTROL[0]), 0, 0 }, + { "mmOTG1_OTG_BLANK_CONTROL", REG_MMIO, 0x1bc2, 2, &mmOTG1_OTG_BLANK_CONTROL[0], sizeof(mmOTG1_OTG_BLANK_CONTROL)/sizeof(mmOTG1_OTG_BLANK_CONTROL[0]), 0, 0 }, + { "mmOTG1_OTG_PIPE_ABORT_CONTROL", REG_MMIO, 0x1bc3, 2, &mmOTG1_OTG_PIPE_ABORT_CONTROL[0], sizeof(mmOTG1_OTG_PIPE_ABORT_CONTROL)/sizeof(mmOTG1_OTG_PIPE_ABORT_CONTROL[0]), 0, 0 }, + { "mmOTG1_OTG_INTERLACE_CONTROL", REG_MMIO, 0x1bc4, 2, &mmOTG1_OTG_INTERLACE_CONTROL[0], sizeof(mmOTG1_OTG_INTERLACE_CONTROL)/sizeof(mmOTG1_OTG_INTERLACE_CONTROL[0]), 0, 0 }, + { "mmOTG1_OTG_INTERLACE_STATUS", REG_MMIO, 0x1bc5, 2, &mmOTG1_OTG_INTERLACE_STATUS[0], sizeof(mmOTG1_OTG_INTERLACE_STATUS)/sizeof(mmOTG1_OTG_INTERLACE_STATUS[0]), 0, 0 }, + { "mmOTG1_OTG_FIELD_INDICATION_CONTROL", REG_MMIO, 0x1bc6, 2, &mmOTG1_OTG_FIELD_INDICATION_CONTROL[0], sizeof(mmOTG1_OTG_FIELD_INDICATION_CONTROL)/sizeof(mmOTG1_OTG_FIELD_INDICATION_CONTROL[0]), 0, 0 }, + { "mmOTG1_OTG_PIXEL_DATA_READBACK0", REG_MMIO, 0x1bc7, 2, &mmOTG1_OTG_PIXEL_DATA_READBACK0[0], sizeof(mmOTG1_OTG_PIXEL_DATA_READBACK0)/sizeof(mmOTG1_OTG_PIXEL_DATA_READBACK0[0]), 0, 0 }, + { "mmOTG1_OTG_PIXEL_DATA_READBACK1", REG_MMIO, 0x1bc8, 2, &mmOTG1_OTG_PIXEL_DATA_READBACK1[0], sizeof(mmOTG1_OTG_PIXEL_DATA_READBACK1)/sizeof(mmOTG1_OTG_PIXEL_DATA_READBACK1[0]), 0, 0 }, + { "mmOTG1_OTG_STATUS", REG_MMIO, 0x1bc9, 2, &mmOTG1_OTG_STATUS[0], sizeof(mmOTG1_OTG_STATUS)/sizeof(mmOTG1_OTG_STATUS[0]), 0, 0 }, + { "mmOTG1_OTG_STATUS_POSITION", REG_MMIO, 0x1bca, 2, &mmOTG1_OTG_STATUS_POSITION[0], sizeof(mmOTG1_OTG_STATUS_POSITION)/sizeof(mmOTG1_OTG_STATUS_POSITION[0]), 0, 0 }, + { "mmOTG1_OTG_NOM_VERT_POSITION", REG_MMIO, 0x1bcb, 2, &mmOTG1_OTG_NOM_VERT_POSITION[0], sizeof(mmOTG1_OTG_NOM_VERT_POSITION)/sizeof(mmOTG1_OTG_NOM_VERT_POSITION[0]), 0, 0 }, + { "mmOTG1_OTG_STATUS_FRAME_COUNT", REG_MMIO, 0x1bcc, 2, &mmOTG1_OTG_STATUS_FRAME_COUNT[0], sizeof(mmOTG1_OTG_STATUS_FRAME_COUNT)/sizeof(mmOTG1_OTG_STATUS_FRAME_COUNT[0]), 0, 0 }, + { "mmOTG1_OTG_STATUS_VF_COUNT", REG_MMIO, 0x1bcd, 2, &mmOTG1_OTG_STATUS_VF_COUNT[0], sizeof(mmOTG1_OTG_STATUS_VF_COUNT)/sizeof(mmOTG1_OTG_STATUS_VF_COUNT[0]), 0, 0 }, + { "mmOTG1_OTG_STATUS_HV_COUNT", REG_MMIO, 0x1bce, 2, &mmOTG1_OTG_STATUS_HV_COUNT[0], sizeof(mmOTG1_OTG_STATUS_HV_COUNT)/sizeof(mmOTG1_OTG_STATUS_HV_COUNT[0]), 0, 0 }, + { "mmOTG1_OTG_COUNT_CONTROL", REG_MMIO, 0x1bcf, 2, &mmOTG1_OTG_COUNT_CONTROL[0], sizeof(mmOTG1_OTG_COUNT_CONTROL)/sizeof(mmOTG1_OTG_COUNT_CONTROL[0]), 0, 0 }, + { "mmOTG1_OTG_COUNT_RESET", REG_MMIO, 0x1bd0, 2, &mmOTG1_OTG_COUNT_RESET[0], sizeof(mmOTG1_OTG_COUNT_RESET)/sizeof(mmOTG1_OTG_COUNT_RESET[0]), 0, 0 }, + { "mmOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE", REG_MMIO, 0x1bd1, 2, &mmOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE[0], sizeof(mmOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE)/sizeof(mmOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE[0]), 0, 0 }, + { "mmOTG1_OTG_VERT_SYNC_CONTROL", REG_MMIO, 0x1bd2, 2, &mmOTG1_OTG_VERT_SYNC_CONTROL[0], sizeof(mmOTG1_OTG_VERT_SYNC_CONTROL)/sizeof(mmOTG1_OTG_VERT_SYNC_CONTROL[0]), 0, 0 }, + { "mmOTG1_OTG_STEREO_STATUS", REG_MMIO, 0x1bd3, 2, &mmOTG1_OTG_STEREO_STATUS[0], sizeof(mmOTG1_OTG_STEREO_STATUS)/sizeof(mmOTG1_OTG_STEREO_STATUS[0]), 0, 0 }, + { "mmOTG1_OTG_STEREO_CONTROL", REG_MMIO, 0x1bd4, 2, &mmOTG1_OTG_STEREO_CONTROL[0], sizeof(mmOTG1_OTG_STEREO_CONTROL)/sizeof(mmOTG1_OTG_STEREO_CONTROL[0]), 0, 0 }, + { "mmOTG1_OTG_SNAPSHOT_STATUS", REG_MMIO, 0x1bd5, 2, &mmOTG1_OTG_SNAPSHOT_STATUS[0], sizeof(mmOTG1_OTG_SNAPSHOT_STATUS)/sizeof(mmOTG1_OTG_SNAPSHOT_STATUS[0]), 0, 0 }, + { "mmOTG1_OTG_SNAPSHOT_CONTROL", REG_MMIO, 0x1bd6, 2, &mmOTG1_OTG_SNAPSHOT_CONTROL[0], sizeof(mmOTG1_OTG_SNAPSHOT_CONTROL)/sizeof(mmOTG1_OTG_SNAPSHOT_CONTROL[0]), 0, 0 }, + { "mmOTG1_OTG_SNAPSHOT_POSITION", REG_MMIO, 0x1bd7, 2, &mmOTG1_OTG_SNAPSHOT_POSITION[0], sizeof(mmOTG1_OTG_SNAPSHOT_POSITION)/sizeof(mmOTG1_OTG_SNAPSHOT_POSITION[0]), 0, 0 }, + { "mmOTG1_OTG_SNAPSHOT_FRAME", REG_MMIO, 0x1bd8, 2, &mmOTG1_OTG_SNAPSHOT_FRAME[0], sizeof(mmOTG1_OTG_SNAPSHOT_FRAME)/sizeof(mmOTG1_OTG_SNAPSHOT_FRAME[0]), 0, 0 }, + { "mmOTG1_OTG_INTERRUPT_CONTROL", REG_MMIO, 0x1bd9, 2, &mmOTG1_OTG_INTERRUPT_CONTROL[0], sizeof(mmOTG1_OTG_INTERRUPT_CONTROL)/sizeof(mmOTG1_OTG_INTERRUPT_CONTROL[0]), 0, 0 }, + { "mmOTG1_OTG_UPDATE_LOCK", REG_MMIO, 0x1bda, 2, &mmOTG1_OTG_UPDATE_LOCK[0], sizeof(mmOTG1_OTG_UPDATE_LOCK)/sizeof(mmOTG1_OTG_UPDATE_LOCK[0]), 0, 0 }, + { "mmOTG1_OTG_DOUBLE_BUFFER_CONTROL", REG_MMIO, 0x1bdb, 2, &mmOTG1_OTG_DOUBLE_BUFFER_CONTROL[0], sizeof(mmOTG1_OTG_DOUBLE_BUFFER_CONTROL)/sizeof(mmOTG1_OTG_DOUBLE_BUFFER_CONTROL[0]), 0, 0 }, + { "mmOTG1_OTG_TEST_PATTERN_CONTROL", REG_MMIO, 0x1bdc, 2, &mmOTG1_OTG_TEST_PATTERN_CONTROL[0], sizeof(mmOTG1_OTG_TEST_PATTERN_CONTROL)/sizeof(mmOTG1_OTG_TEST_PATTERN_CONTROL[0]), 0, 0 }, + { "mmOTG1_OTG_TEST_PATTERN_PARAMETERS", REG_MMIO, 0x1bdd, 2, &mmOTG1_OTG_TEST_PATTERN_PARAMETERS[0], sizeof(mmOTG1_OTG_TEST_PATTERN_PARAMETERS)/sizeof(mmOTG1_OTG_TEST_PATTERN_PARAMETERS[0]), 0, 0 }, + { "mmOTG1_OTG_TEST_PATTERN_COLOR", REG_MMIO, 0x1bde, 2, &mmOTG1_OTG_TEST_PATTERN_COLOR[0], sizeof(mmOTG1_OTG_TEST_PATTERN_COLOR)/sizeof(mmOTG1_OTG_TEST_PATTERN_COLOR[0]), 0, 0 }, + { "mmOTG1_OTG_MASTER_EN", REG_MMIO, 0x1bdf, 2, &mmOTG1_OTG_MASTER_EN[0], sizeof(mmOTG1_OTG_MASTER_EN)/sizeof(mmOTG1_OTG_MASTER_EN[0]), 0, 0 }, + { "mmOTG1_OTG_BLANK_DATA_COLOR", REG_MMIO, 0x1be1, 2, &mmOTG1_OTG_BLANK_DATA_COLOR[0], sizeof(mmOTG1_OTG_BLANK_DATA_COLOR)/sizeof(mmOTG1_OTG_BLANK_DATA_COLOR[0]), 0, 0 }, + { "mmOTG1_OTG_BLANK_DATA_COLOR_EXT", REG_MMIO, 0x1be2, 2, &mmOTG1_OTG_BLANK_DATA_COLOR_EXT[0], sizeof(mmOTG1_OTG_BLANK_DATA_COLOR_EXT)/sizeof(mmOTG1_OTG_BLANK_DATA_COLOR_EXT[0]), 0, 0 }, + { "mmOTG1_OTG_BLACK_COLOR", REG_MMIO, 0x1be3, 2, &mmOTG1_OTG_BLACK_COLOR[0], sizeof(mmOTG1_OTG_BLACK_COLOR)/sizeof(mmOTG1_OTG_BLACK_COLOR[0]), 0, 0 }, + { "mmOTG1_OTG_BLACK_COLOR_EXT", REG_MMIO, 0x1be4, 2, &mmOTG1_OTG_BLACK_COLOR_EXT[0], sizeof(mmOTG1_OTG_BLACK_COLOR_EXT)/sizeof(mmOTG1_OTG_BLACK_COLOR_EXT[0]), 0, 0 }, + { "mmOTG1_OTG_VERTICAL_INTERRUPT0_POSITION", REG_MMIO, 0x1be5, 2, &mmOTG1_OTG_VERTICAL_INTERRUPT0_POSITION[0], sizeof(mmOTG1_OTG_VERTICAL_INTERRUPT0_POSITION)/sizeof(mmOTG1_OTG_VERTICAL_INTERRUPT0_POSITION[0]), 0, 0 }, + { "mmOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL", REG_MMIO, 0x1be6, 2, &mmOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL[0], sizeof(mmOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL)/sizeof(mmOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL[0]), 0, 0 }, + { "mmOTG1_OTG_VERTICAL_INTERRUPT1_POSITION", REG_MMIO, 0x1be7, 2, &mmOTG1_OTG_VERTICAL_INTERRUPT1_POSITION[0], sizeof(mmOTG1_OTG_VERTICAL_INTERRUPT1_POSITION)/sizeof(mmOTG1_OTG_VERTICAL_INTERRUPT1_POSITION[0]), 0, 0 }, + { "mmOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL", REG_MMIO, 0x1be8, 2, &mmOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL[0], sizeof(mmOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL)/sizeof(mmOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL[0]), 0, 0 }, + { "mmOTG1_OTG_VERTICAL_INTERRUPT2_POSITION", REG_MMIO, 0x1be9, 2, &mmOTG1_OTG_VERTICAL_INTERRUPT2_POSITION[0], sizeof(mmOTG1_OTG_VERTICAL_INTERRUPT2_POSITION)/sizeof(mmOTG1_OTG_VERTICAL_INTERRUPT2_POSITION[0]), 0, 0 }, + { "mmOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL", REG_MMIO, 0x1bea, 2, &mmOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL[0], sizeof(mmOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL)/sizeof(mmOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL[0]), 0, 0 }, + { "mmOTG1_OTG_CRC_CNTL", REG_MMIO, 0x1beb, 2, &mmOTG1_OTG_CRC_CNTL[0], sizeof(mmOTG1_OTG_CRC_CNTL)/sizeof(mmOTG1_OTG_CRC_CNTL[0]), 0, 0 }, + { "mmOTG1_OTG_CRC0_WINDOWA_X_CONTROL", REG_MMIO, 0x1bec, 2, &mmOTG1_OTG_CRC0_WINDOWA_X_CONTROL[0], sizeof(mmOTG1_OTG_CRC0_WINDOWA_X_CONTROL)/sizeof(mmOTG1_OTG_CRC0_WINDOWA_X_CONTROL[0]), 0, 0 }, + { "mmOTG1_OTG_CRC0_WINDOWA_Y_CONTROL", REG_MMIO, 0x1bed, 2, &mmOTG1_OTG_CRC0_WINDOWA_Y_CONTROL[0], sizeof(mmOTG1_OTG_CRC0_WINDOWA_Y_CONTROL)/sizeof(mmOTG1_OTG_CRC0_WINDOWA_Y_CONTROL[0]), 0, 0 }, + { "mmOTG1_OTG_CRC0_WINDOWB_X_CONTROL", REG_MMIO, 0x1bee, 2, &mmOTG1_OTG_CRC0_WINDOWB_X_CONTROL[0], sizeof(mmOTG1_OTG_CRC0_WINDOWB_X_CONTROL)/sizeof(mmOTG1_OTG_CRC0_WINDOWB_X_CONTROL[0]), 0, 0 }, + { "mmOTG1_OTG_CRC0_WINDOWB_Y_CONTROL", REG_MMIO, 0x1bef, 2, &mmOTG1_OTG_CRC0_WINDOWB_Y_CONTROL[0], sizeof(mmOTG1_OTG_CRC0_WINDOWB_Y_CONTROL)/sizeof(mmOTG1_OTG_CRC0_WINDOWB_Y_CONTROL[0]), 0, 0 }, + { "mmOTG1_OTG_CRC0_DATA_RG", REG_MMIO, 0x1bf0, 2, &mmOTG1_OTG_CRC0_DATA_RG[0], sizeof(mmOTG1_OTG_CRC0_DATA_RG)/sizeof(mmOTG1_OTG_CRC0_DATA_RG[0]), 0, 0 }, + { "mmOTG1_OTG_CRC0_DATA_B", REG_MMIO, 0x1bf1, 2, &mmOTG1_OTG_CRC0_DATA_B[0], sizeof(mmOTG1_OTG_CRC0_DATA_B)/sizeof(mmOTG1_OTG_CRC0_DATA_B[0]), 0, 0 }, + { "mmOTG1_OTG_CRC1_WINDOWA_X_CONTROL", REG_MMIO, 0x1bf2, 2, &mmOTG1_OTG_CRC1_WINDOWA_X_CONTROL[0], sizeof(mmOTG1_OTG_CRC1_WINDOWA_X_CONTROL)/sizeof(mmOTG1_OTG_CRC1_WINDOWA_X_CONTROL[0]), 0, 0 }, + { "mmOTG1_OTG_CRC1_WINDOWA_Y_CONTROL", REG_MMIO, 0x1bf3, 2, &mmOTG1_OTG_CRC1_WINDOWA_Y_CONTROL[0], sizeof(mmOTG1_OTG_CRC1_WINDOWA_Y_CONTROL)/sizeof(mmOTG1_OTG_CRC1_WINDOWA_Y_CONTROL[0]), 0, 0 }, + { "mmOTG1_OTG_CRC1_WINDOWB_X_CONTROL", REG_MMIO, 0x1bf4, 2, &mmOTG1_OTG_CRC1_WINDOWB_X_CONTROL[0], sizeof(mmOTG1_OTG_CRC1_WINDOWB_X_CONTROL)/sizeof(mmOTG1_OTG_CRC1_WINDOWB_X_CONTROL[0]), 0, 0 }, + { "mmOTG1_OTG_CRC1_WINDOWB_Y_CONTROL", REG_MMIO, 0x1bf5, 2, &mmOTG1_OTG_CRC1_WINDOWB_Y_CONTROL[0], sizeof(mmOTG1_OTG_CRC1_WINDOWB_Y_CONTROL)/sizeof(mmOTG1_OTG_CRC1_WINDOWB_Y_CONTROL[0]), 0, 0 }, + { "mmOTG1_OTG_CRC1_DATA_RG", REG_MMIO, 0x1bf6, 2, &mmOTG1_OTG_CRC1_DATA_RG[0], sizeof(mmOTG1_OTG_CRC1_DATA_RG)/sizeof(mmOTG1_OTG_CRC1_DATA_RG[0]), 0, 0 }, + { "mmOTG1_OTG_CRC1_DATA_B", REG_MMIO, 0x1bf7, 2, &mmOTG1_OTG_CRC1_DATA_B[0], sizeof(mmOTG1_OTG_CRC1_DATA_B)/sizeof(mmOTG1_OTG_CRC1_DATA_B[0]), 0, 0 }, + { "mmOTG1_OTG_CRC2_DATA_RG", REG_MMIO, 0x1bf8, 2, &mmOTG1_OTG_CRC2_DATA_RG[0], sizeof(mmOTG1_OTG_CRC2_DATA_RG)/sizeof(mmOTG1_OTG_CRC2_DATA_RG[0]), 0, 0 }, + { "mmOTG1_OTG_CRC2_DATA_B", REG_MMIO, 0x1bf9, 2, &mmOTG1_OTG_CRC2_DATA_B[0], sizeof(mmOTG1_OTG_CRC2_DATA_B)/sizeof(mmOTG1_OTG_CRC2_DATA_B[0]), 0, 0 }, + { "mmOTG1_OTG_CRC3_DATA_RG", REG_MMIO, 0x1bfa, 2, &mmOTG1_OTG_CRC3_DATA_RG[0], sizeof(mmOTG1_OTG_CRC3_DATA_RG)/sizeof(mmOTG1_OTG_CRC3_DATA_RG[0]), 0, 0 }, + { "mmOTG1_OTG_CRC3_DATA_B", REG_MMIO, 0x1bfb, 2, &mmOTG1_OTG_CRC3_DATA_B[0], sizeof(mmOTG1_OTG_CRC3_DATA_B)/sizeof(mmOTG1_OTG_CRC3_DATA_B[0]), 0, 0 }, + { "mmOTG1_OTG_CRC_SIG_RED_GREEN_MASK", REG_MMIO, 0x1bfc, 2, &mmOTG1_OTG_CRC_SIG_RED_GREEN_MASK[0], sizeof(mmOTG1_OTG_CRC_SIG_RED_GREEN_MASK)/sizeof(mmOTG1_OTG_CRC_SIG_RED_GREEN_MASK[0]), 0, 0 }, + { "mmOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK", REG_MMIO, 0x1bfd, 2, &mmOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK[0], sizeof(mmOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK)/sizeof(mmOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK[0]), 0, 0 }, + { "mmOTG1_OTG_STATIC_SCREEN_CONTROL", REG_MMIO, 0x1c04, 2, &mmOTG1_OTG_STATIC_SCREEN_CONTROL[0], sizeof(mmOTG1_OTG_STATIC_SCREEN_CONTROL)/sizeof(mmOTG1_OTG_STATIC_SCREEN_CONTROL[0]), 0, 0 }, + { "mmOTG1_OTG_3D_STRUCTURE_CONTROL", REG_MMIO, 0x1c05, 2, &mmOTG1_OTG_3D_STRUCTURE_CONTROL[0], sizeof(mmOTG1_OTG_3D_STRUCTURE_CONTROL)/sizeof(mmOTG1_OTG_3D_STRUCTURE_CONTROL[0]), 0, 0 }, + { "mmOTG1_OTG_GSL_VSYNC_GAP", REG_MMIO, 0x1c06, 2, &mmOTG1_OTG_GSL_VSYNC_GAP[0], sizeof(mmOTG1_OTG_GSL_VSYNC_GAP)/sizeof(mmOTG1_OTG_GSL_VSYNC_GAP[0]), 0, 0 }, + { "mmOTG1_OTG_MASTER_UPDATE_MODE", REG_MMIO, 0x1c07, 2, &mmOTG1_OTG_MASTER_UPDATE_MODE[0], sizeof(mmOTG1_OTG_MASTER_UPDATE_MODE)/sizeof(mmOTG1_OTG_MASTER_UPDATE_MODE[0]), 0, 0 }, + { "mmOTG1_OTG_CLOCK_CONTROL", REG_MMIO, 0x1c08, 2, &mmOTG1_OTG_CLOCK_CONTROL[0], sizeof(mmOTG1_OTG_CLOCK_CONTROL)/sizeof(mmOTG1_OTG_CLOCK_CONTROL[0]), 0, 0 }, + { "mmOTG1_OTG_VSTARTUP_PARAM", REG_MMIO, 0x1c09, 2, &mmOTG1_OTG_VSTARTUP_PARAM[0], sizeof(mmOTG1_OTG_VSTARTUP_PARAM)/sizeof(mmOTG1_OTG_VSTARTUP_PARAM[0]), 0, 0 }, + { "mmOTG1_OTG_VUPDATE_PARAM", REG_MMIO, 0x1c0a, 2, &mmOTG1_OTG_VUPDATE_PARAM[0], sizeof(mmOTG1_OTG_VUPDATE_PARAM)/sizeof(mmOTG1_OTG_VUPDATE_PARAM[0]), 0, 0 }, + { "mmOTG1_OTG_VREADY_PARAM", REG_MMIO, 0x1c0b, 2, &mmOTG1_OTG_VREADY_PARAM[0], sizeof(mmOTG1_OTG_VREADY_PARAM)/sizeof(mmOTG1_OTG_VREADY_PARAM[0]), 0, 0 }, + { "mmOTG1_OTG_GLOBAL_SYNC_STATUS", REG_MMIO, 0x1c0c, 2, &mmOTG1_OTG_GLOBAL_SYNC_STATUS[0], sizeof(mmOTG1_OTG_GLOBAL_SYNC_STATUS)/sizeof(mmOTG1_OTG_GLOBAL_SYNC_STATUS[0]), 0, 0 }, + { "mmOTG1_OTG_MASTER_UPDATE_LOCK", REG_MMIO, 0x1c0d, 2, &mmOTG1_OTG_MASTER_UPDATE_LOCK[0], sizeof(mmOTG1_OTG_MASTER_UPDATE_LOCK)/sizeof(mmOTG1_OTG_MASTER_UPDATE_LOCK[0]), 0, 0 }, + { "mmOTG1_OTG_GSL_CONTROL", REG_MMIO, 0x1c0e, 2, &mmOTG1_OTG_GSL_CONTROL[0], sizeof(mmOTG1_OTG_GSL_CONTROL)/sizeof(mmOTG1_OTG_GSL_CONTROL[0]), 0, 0 }, + { "mmOTG1_OTG_GSL_WINDOW_X", REG_MMIO, 0x1c0f, 2, &mmOTG1_OTG_GSL_WINDOW_X[0], sizeof(mmOTG1_OTG_GSL_WINDOW_X)/sizeof(mmOTG1_OTG_GSL_WINDOW_X[0]), 0, 0 }, + { "mmOTG1_OTG_GSL_WINDOW_Y", REG_MMIO, 0x1c10, 2, &mmOTG1_OTG_GSL_WINDOW_Y[0], sizeof(mmOTG1_OTG_GSL_WINDOW_Y)/sizeof(mmOTG1_OTG_GSL_WINDOW_Y[0]), 0, 0 }, + { "mmOTG1_OTG_VUPDATE_KEEPOUT", REG_MMIO, 0x1c11, 2, &mmOTG1_OTG_VUPDATE_KEEPOUT[0], sizeof(mmOTG1_OTG_VUPDATE_KEEPOUT)/sizeof(mmOTG1_OTG_VUPDATE_KEEPOUT[0]), 0, 0 }, + { "mmOTG1_OTG_GLOBAL_CONTROL0", REG_MMIO, 0x1c12, 2, &mmOTG1_OTG_GLOBAL_CONTROL0[0], sizeof(mmOTG1_OTG_GLOBAL_CONTROL0)/sizeof(mmOTG1_OTG_GLOBAL_CONTROL0[0]), 0, 0 }, + { "mmOTG1_OTG_GLOBAL_CONTROL1", REG_MMIO, 0x1c13, 2, &mmOTG1_OTG_GLOBAL_CONTROL1[0], sizeof(mmOTG1_OTG_GLOBAL_CONTROL1)/sizeof(mmOTG1_OTG_GLOBAL_CONTROL1[0]), 0, 0 }, + { "mmOTG1_OTG_GLOBAL_CONTROL2", REG_MMIO, 0x1c14, 2, &mmOTG1_OTG_GLOBAL_CONTROL2[0], sizeof(mmOTG1_OTG_GLOBAL_CONTROL2)/sizeof(mmOTG1_OTG_GLOBAL_CONTROL2[0]), 0, 0 }, + { "mmOTG1_OTG_GLOBAL_CONTROL3", REG_MMIO, 0x1c15, 2, &mmOTG1_OTG_GLOBAL_CONTROL3[0], sizeof(mmOTG1_OTG_GLOBAL_CONTROL3)/sizeof(mmOTG1_OTG_GLOBAL_CONTROL3[0]), 0, 0 }, + { "mmOTG1_OTG_TRIG_MANUAL_CONTROL", REG_MMIO, 0x1c16, 2, &mmOTG1_OTG_TRIG_MANUAL_CONTROL[0], sizeof(mmOTG1_OTG_TRIG_MANUAL_CONTROL)/sizeof(mmOTG1_OTG_TRIG_MANUAL_CONTROL[0]), 0, 0 }, + { "mmOTG1_OTG_MANUAL_FLOW_CONTROL", REG_MMIO, 0x1c17, 2, &mmOTG1_OTG_MANUAL_FLOW_CONTROL[0], sizeof(mmOTG1_OTG_MANUAL_FLOW_CONTROL)/sizeof(mmOTG1_OTG_MANUAL_FLOW_CONTROL[0]), 0, 0 }, + { "mmOTG1_OTG_RANGE_TIMING_INT_STATUS", REG_MMIO, 0x1c18, 2, &mmOTG1_OTG_RANGE_TIMING_INT_STATUS[0], sizeof(mmOTG1_OTG_RANGE_TIMING_INT_STATUS)/sizeof(mmOTG1_OTG_RANGE_TIMING_INT_STATUS[0]), 0, 0 }, + { "mmOTG1_OTG_DRR_CONTROL", REG_MMIO, 0x1c19, 2, &mmOTG1_OTG_DRR_CONTROL[0], sizeof(mmOTG1_OTG_DRR_CONTROL)/sizeof(mmOTG1_OTG_DRR_CONTROL[0]), 0, 0 }, + { "mmOTG1_OTG_REQUEST_CONTROL", REG_MMIO, 0x1c1a, 2, &mmOTG1_OTG_REQUEST_CONTROL[0], sizeof(mmOTG1_OTG_REQUEST_CONTROL)/sizeof(mmOTG1_OTG_REQUEST_CONTROL[0]), 0, 0 }, + { "mmOTG1_OTG_SPARE_REGISTER", REG_MMIO, 0x1c1b, 2, &mmOTG1_OTG_SPARE_REGISTER[0], sizeof(mmOTG1_OTG_SPARE_REGISTER)/sizeof(mmOTG1_OTG_SPARE_REGISTER[0]), 0, 0 }, + { "mmOTG2_OTG_H_TOTAL", REG_MMIO, 0x1c2a, 2, &mmOTG2_OTG_H_TOTAL[0], sizeof(mmOTG2_OTG_H_TOTAL)/sizeof(mmOTG2_OTG_H_TOTAL[0]), 0, 0 }, + { "mmOTG2_OTG_H_BLANK_START_END", REG_MMIO, 0x1c2b, 2, &mmOTG2_OTG_H_BLANK_START_END[0], sizeof(mmOTG2_OTG_H_BLANK_START_END)/sizeof(mmOTG2_OTG_H_BLANK_START_END[0]), 0, 0 }, + { "mmOTG2_OTG_H_SYNC_A", REG_MMIO, 0x1c2c, 2, &mmOTG2_OTG_H_SYNC_A[0], sizeof(mmOTG2_OTG_H_SYNC_A)/sizeof(mmOTG2_OTG_H_SYNC_A[0]), 0, 0 }, + { "mmOTG2_OTG_H_SYNC_A_CNTL", REG_MMIO, 0x1c2d, 2, &mmOTG2_OTG_H_SYNC_A_CNTL[0], sizeof(mmOTG2_OTG_H_SYNC_A_CNTL)/sizeof(mmOTG2_OTG_H_SYNC_A_CNTL[0]), 0, 0 }, + { "mmOTG2_OTG_H_TIMING_CNTL", REG_MMIO, 0x1c2e, 2, &mmOTG2_OTG_H_TIMING_CNTL[0], sizeof(mmOTG2_OTG_H_TIMING_CNTL)/sizeof(mmOTG2_OTG_H_TIMING_CNTL[0]), 0, 0 }, + { "mmOTG2_OTG_V_TOTAL", REG_MMIO, 0x1c2f, 2, &mmOTG2_OTG_V_TOTAL[0], sizeof(mmOTG2_OTG_V_TOTAL)/sizeof(mmOTG2_OTG_V_TOTAL[0]), 0, 0 }, + { "mmOTG2_OTG_V_TOTAL_MIN", REG_MMIO, 0x1c30, 2, &mmOTG2_OTG_V_TOTAL_MIN[0], sizeof(mmOTG2_OTG_V_TOTAL_MIN)/sizeof(mmOTG2_OTG_V_TOTAL_MIN[0]), 0, 0 }, + { "mmOTG2_OTG_V_TOTAL_MAX", REG_MMIO, 0x1c31, 2, &mmOTG2_OTG_V_TOTAL_MAX[0], sizeof(mmOTG2_OTG_V_TOTAL_MAX)/sizeof(mmOTG2_OTG_V_TOTAL_MAX[0]), 0, 0 }, + { "mmOTG2_OTG_V_TOTAL_MID", REG_MMIO, 0x1c32, 2, &mmOTG2_OTG_V_TOTAL_MID[0], sizeof(mmOTG2_OTG_V_TOTAL_MID)/sizeof(mmOTG2_OTG_V_TOTAL_MID[0]), 0, 0 }, + { "mmOTG2_OTG_V_TOTAL_CONTROL", REG_MMIO, 0x1c33, 2, &mmOTG2_OTG_V_TOTAL_CONTROL[0], sizeof(mmOTG2_OTG_V_TOTAL_CONTROL)/sizeof(mmOTG2_OTG_V_TOTAL_CONTROL[0]), 0, 0 }, + { "mmOTG2_OTG_V_TOTAL_INT_STATUS", REG_MMIO, 0x1c34, 2, &mmOTG2_OTG_V_TOTAL_INT_STATUS[0], sizeof(mmOTG2_OTG_V_TOTAL_INT_STATUS)/sizeof(mmOTG2_OTG_V_TOTAL_INT_STATUS[0]), 0, 0 }, + { "mmOTG2_OTG_VSYNC_NOM_INT_STATUS", REG_MMIO, 0x1c35, 2, &mmOTG2_OTG_VSYNC_NOM_INT_STATUS[0], sizeof(mmOTG2_OTG_VSYNC_NOM_INT_STATUS)/sizeof(mmOTG2_OTG_VSYNC_NOM_INT_STATUS[0]), 0, 0 }, + { "mmOTG2_OTG_V_BLANK_START_END", REG_MMIO, 0x1c36, 2, &mmOTG2_OTG_V_BLANK_START_END[0], sizeof(mmOTG2_OTG_V_BLANK_START_END)/sizeof(mmOTG2_OTG_V_BLANK_START_END[0]), 0, 0 }, + { "mmOTG2_OTG_V_SYNC_A", REG_MMIO, 0x1c37, 2, &mmOTG2_OTG_V_SYNC_A[0], sizeof(mmOTG2_OTG_V_SYNC_A)/sizeof(mmOTG2_OTG_V_SYNC_A[0]), 0, 0 }, + { "mmOTG2_OTG_V_SYNC_A_CNTL", REG_MMIO, 0x1c38, 2, &mmOTG2_OTG_V_SYNC_A_CNTL[0], sizeof(mmOTG2_OTG_V_SYNC_A_CNTL)/sizeof(mmOTG2_OTG_V_SYNC_A_CNTL[0]), 0, 0 }, + { "mmOTG2_OTG_TRIGA_CNTL", REG_MMIO, 0x1c39, 2, &mmOTG2_OTG_TRIGA_CNTL[0], sizeof(mmOTG2_OTG_TRIGA_CNTL)/sizeof(mmOTG2_OTG_TRIGA_CNTL[0]), 0, 0 }, + { "mmOTG2_OTG_TRIGA_MANUAL_TRIG", REG_MMIO, 0x1c3a, 2, &mmOTG2_OTG_TRIGA_MANUAL_TRIG[0], sizeof(mmOTG2_OTG_TRIGA_MANUAL_TRIG)/sizeof(mmOTG2_OTG_TRIGA_MANUAL_TRIG[0]), 0, 0 }, + { "mmOTG2_OTG_TRIGB_CNTL", REG_MMIO, 0x1c3b, 2, &mmOTG2_OTG_TRIGB_CNTL[0], sizeof(mmOTG2_OTG_TRIGB_CNTL)/sizeof(mmOTG2_OTG_TRIGB_CNTL[0]), 0, 0 }, + { "mmOTG2_OTG_TRIGB_MANUAL_TRIG", REG_MMIO, 0x1c3c, 2, &mmOTG2_OTG_TRIGB_MANUAL_TRIG[0], sizeof(mmOTG2_OTG_TRIGB_MANUAL_TRIG)/sizeof(mmOTG2_OTG_TRIGB_MANUAL_TRIG[0]), 0, 0 }, + { "mmOTG2_OTG_FORCE_COUNT_NOW_CNTL", REG_MMIO, 0x1c3d, 2, &mmOTG2_OTG_FORCE_COUNT_NOW_CNTL[0], sizeof(mmOTG2_OTG_FORCE_COUNT_NOW_CNTL)/sizeof(mmOTG2_OTG_FORCE_COUNT_NOW_CNTL[0]), 0, 0 }, + { "mmOTG2_OTG_FLOW_CONTROL", REG_MMIO, 0x1c3e, 2, &mmOTG2_OTG_FLOW_CONTROL[0], sizeof(mmOTG2_OTG_FLOW_CONTROL)/sizeof(mmOTG2_OTG_FLOW_CONTROL[0]), 0, 0 }, + { "mmOTG2_OTG_STEREO_FORCE_NEXT_EYE", REG_MMIO, 0x1c3f, 2, &mmOTG2_OTG_STEREO_FORCE_NEXT_EYE[0], sizeof(mmOTG2_OTG_STEREO_FORCE_NEXT_EYE)/sizeof(mmOTG2_OTG_STEREO_FORCE_NEXT_EYE[0]), 0, 0 }, + { "mmOTG2_OTG_AVSYNC_COUNTER", REG_MMIO, 0x1c40, 2, &mmOTG2_OTG_AVSYNC_COUNTER[0], sizeof(mmOTG2_OTG_AVSYNC_COUNTER)/sizeof(mmOTG2_OTG_AVSYNC_COUNTER[0]), 0, 0 }, + { "mmOTG2_OTG_CONTROL", REG_MMIO, 0x1c41, 2, &mmOTG2_OTG_CONTROL[0], sizeof(mmOTG2_OTG_CONTROL)/sizeof(mmOTG2_OTG_CONTROL[0]), 0, 0 }, + { "mmOTG2_OTG_BLANK_CONTROL", REG_MMIO, 0x1c42, 2, &mmOTG2_OTG_BLANK_CONTROL[0], sizeof(mmOTG2_OTG_BLANK_CONTROL)/sizeof(mmOTG2_OTG_BLANK_CONTROL[0]), 0, 0 }, + { "mmOTG2_OTG_PIPE_ABORT_CONTROL", REG_MMIO, 0x1c43, 2, &mmOTG2_OTG_PIPE_ABORT_CONTROL[0], sizeof(mmOTG2_OTG_PIPE_ABORT_CONTROL)/sizeof(mmOTG2_OTG_PIPE_ABORT_CONTROL[0]), 0, 0 }, + { "mmOTG2_OTG_INTERLACE_CONTROL", REG_MMIO, 0x1c44, 2, &mmOTG2_OTG_INTERLACE_CONTROL[0], sizeof(mmOTG2_OTG_INTERLACE_CONTROL)/sizeof(mmOTG2_OTG_INTERLACE_CONTROL[0]), 0, 0 }, + { "mmOTG2_OTG_INTERLACE_STATUS", REG_MMIO, 0x1c45, 2, &mmOTG2_OTG_INTERLACE_STATUS[0], sizeof(mmOTG2_OTG_INTERLACE_STATUS)/sizeof(mmOTG2_OTG_INTERLACE_STATUS[0]), 0, 0 }, + { "mmOTG2_OTG_FIELD_INDICATION_CONTROL", REG_MMIO, 0x1c46, 2, &mmOTG2_OTG_FIELD_INDICATION_CONTROL[0], sizeof(mmOTG2_OTG_FIELD_INDICATION_CONTROL)/sizeof(mmOTG2_OTG_FIELD_INDICATION_CONTROL[0]), 0, 0 }, + { "mmOTG2_OTG_PIXEL_DATA_READBACK0", REG_MMIO, 0x1c47, 2, &mmOTG2_OTG_PIXEL_DATA_READBACK0[0], sizeof(mmOTG2_OTG_PIXEL_DATA_READBACK0)/sizeof(mmOTG2_OTG_PIXEL_DATA_READBACK0[0]), 0, 0 }, + { "mmOTG2_OTG_PIXEL_DATA_READBACK1", REG_MMIO, 0x1c48, 2, &mmOTG2_OTG_PIXEL_DATA_READBACK1[0], sizeof(mmOTG2_OTG_PIXEL_DATA_READBACK1)/sizeof(mmOTG2_OTG_PIXEL_DATA_READBACK1[0]), 0, 0 }, + { "mmOTG2_OTG_STATUS", REG_MMIO, 0x1c49, 2, &mmOTG2_OTG_STATUS[0], sizeof(mmOTG2_OTG_STATUS)/sizeof(mmOTG2_OTG_STATUS[0]), 0, 0 }, + { "mmOTG2_OTG_STATUS_POSITION", REG_MMIO, 0x1c4a, 2, &mmOTG2_OTG_STATUS_POSITION[0], sizeof(mmOTG2_OTG_STATUS_POSITION)/sizeof(mmOTG2_OTG_STATUS_POSITION[0]), 0, 0 }, + { "mmOTG2_OTG_NOM_VERT_POSITION", REG_MMIO, 0x1c4b, 2, &mmOTG2_OTG_NOM_VERT_POSITION[0], sizeof(mmOTG2_OTG_NOM_VERT_POSITION)/sizeof(mmOTG2_OTG_NOM_VERT_POSITION[0]), 0, 0 }, + { "mmOTG2_OTG_STATUS_FRAME_COUNT", REG_MMIO, 0x1c4c, 2, &mmOTG2_OTG_STATUS_FRAME_COUNT[0], sizeof(mmOTG2_OTG_STATUS_FRAME_COUNT)/sizeof(mmOTG2_OTG_STATUS_FRAME_COUNT[0]), 0, 0 }, + { "mmOTG2_OTG_STATUS_VF_COUNT", REG_MMIO, 0x1c4d, 2, &mmOTG2_OTG_STATUS_VF_COUNT[0], sizeof(mmOTG2_OTG_STATUS_VF_COUNT)/sizeof(mmOTG2_OTG_STATUS_VF_COUNT[0]), 0, 0 }, + { "mmOTG2_OTG_STATUS_HV_COUNT", REG_MMIO, 0x1c4e, 2, &mmOTG2_OTG_STATUS_HV_COUNT[0], sizeof(mmOTG2_OTG_STATUS_HV_COUNT)/sizeof(mmOTG2_OTG_STATUS_HV_COUNT[0]), 0, 0 }, + { "mmOTG2_OTG_COUNT_CONTROL", REG_MMIO, 0x1c4f, 2, &mmOTG2_OTG_COUNT_CONTROL[0], sizeof(mmOTG2_OTG_COUNT_CONTROL)/sizeof(mmOTG2_OTG_COUNT_CONTROL[0]), 0, 0 }, + { "mmOTG2_OTG_COUNT_RESET", REG_MMIO, 0x1c50, 2, &mmOTG2_OTG_COUNT_RESET[0], sizeof(mmOTG2_OTG_COUNT_RESET)/sizeof(mmOTG2_OTG_COUNT_RESET[0]), 0, 0 }, + { "mmOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE", REG_MMIO, 0x1c51, 2, &mmOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE[0], sizeof(mmOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE)/sizeof(mmOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE[0]), 0, 0 }, + { "mmOTG2_OTG_VERT_SYNC_CONTROL", REG_MMIO, 0x1c52, 2, &mmOTG2_OTG_VERT_SYNC_CONTROL[0], sizeof(mmOTG2_OTG_VERT_SYNC_CONTROL)/sizeof(mmOTG2_OTG_VERT_SYNC_CONTROL[0]), 0, 0 }, + { "mmOTG2_OTG_STEREO_STATUS", REG_MMIO, 0x1c53, 2, &mmOTG2_OTG_STEREO_STATUS[0], sizeof(mmOTG2_OTG_STEREO_STATUS)/sizeof(mmOTG2_OTG_STEREO_STATUS[0]), 0, 0 }, + { "mmOTG2_OTG_STEREO_CONTROL", REG_MMIO, 0x1c54, 2, &mmOTG2_OTG_STEREO_CONTROL[0], sizeof(mmOTG2_OTG_STEREO_CONTROL)/sizeof(mmOTG2_OTG_STEREO_CONTROL[0]), 0, 0 }, + { "mmOTG2_OTG_SNAPSHOT_STATUS", REG_MMIO, 0x1c55, 2, &mmOTG2_OTG_SNAPSHOT_STATUS[0], sizeof(mmOTG2_OTG_SNAPSHOT_STATUS)/sizeof(mmOTG2_OTG_SNAPSHOT_STATUS[0]), 0, 0 }, + { "mmOTG2_OTG_SNAPSHOT_CONTROL", REG_MMIO, 0x1c56, 2, &mmOTG2_OTG_SNAPSHOT_CONTROL[0], sizeof(mmOTG2_OTG_SNAPSHOT_CONTROL)/sizeof(mmOTG2_OTG_SNAPSHOT_CONTROL[0]), 0, 0 }, + { "mmOTG2_OTG_SNAPSHOT_POSITION", REG_MMIO, 0x1c57, 2, &mmOTG2_OTG_SNAPSHOT_POSITION[0], sizeof(mmOTG2_OTG_SNAPSHOT_POSITION)/sizeof(mmOTG2_OTG_SNAPSHOT_POSITION[0]), 0, 0 }, + { "mmOTG2_OTG_SNAPSHOT_FRAME", REG_MMIO, 0x1c58, 2, &mmOTG2_OTG_SNAPSHOT_FRAME[0], sizeof(mmOTG2_OTG_SNAPSHOT_FRAME)/sizeof(mmOTG2_OTG_SNAPSHOT_FRAME[0]), 0, 0 }, + { "mmOTG2_OTG_INTERRUPT_CONTROL", REG_MMIO, 0x1c59, 2, &mmOTG2_OTG_INTERRUPT_CONTROL[0], sizeof(mmOTG2_OTG_INTERRUPT_CONTROL)/sizeof(mmOTG2_OTG_INTERRUPT_CONTROL[0]), 0, 0 }, + { "mmOTG2_OTG_UPDATE_LOCK", REG_MMIO, 0x1c5a, 2, &mmOTG2_OTG_UPDATE_LOCK[0], sizeof(mmOTG2_OTG_UPDATE_LOCK)/sizeof(mmOTG2_OTG_UPDATE_LOCK[0]), 0, 0 }, + { "mmOTG2_OTG_DOUBLE_BUFFER_CONTROL", REG_MMIO, 0x1c5b, 2, &mmOTG2_OTG_DOUBLE_BUFFER_CONTROL[0], sizeof(mmOTG2_OTG_DOUBLE_BUFFER_CONTROL)/sizeof(mmOTG2_OTG_DOUBLE_BUFFER_CONTROL[0]), 0, 0 }, + { "mmOTG2_OTG_TEST_PATTERN_CONTROL", REG_MMIO, 0x1c5c, 2, &mmOTG2_OTG_TEST_PATTERN_CONTROL[0], sizeof(mmOTG2_OTG_TEST_PATTERN_CONTROL)/sizeof(mmOTG2_OTG_TEST_PATTERN_CONTROL[0]), 0, 0 }, + { "mmOTG2_OTG_TEST_PATTERN_PARAMETERS", REG_MMIO, 0x1c5d, 2, &mmOTG2_OTG_TEST_PATTERN_PARAMETERS[0], sizeof(mmOTG2_OTG_TEST_PATTERN_PARAMETERS)/sizeof(mmOTG2_OTG_TEST_PATTERN_PARAMETERS[0]), 0, 0 }, + { "mmOTG2_OTG_TEST_PATTERN_COLOR", REG_MMIO, 0x1c5e, 2, &mmOTG2_OTG_TEST_PATTERN_COLOR[0], sizeof(mmOTG2_OTG_TEST_PATTERN_COLOR)/sizeof(mmOTG2_OTG_TEST_PATTERN_COLOR[0]), 0, 0 }, + { "mmOTG2_OTG_MASTER_EN", REG_MMIO, 0x1c5f, 2, &mmOTG2_OTG_MASTER_EN[0], sizeof(mmOTG2_OTG_MASTER_EN)/sizeof(mmOTG2_OTG_MASTER_EN[0]), 0, 0 }, + { "mmOTG2_OTG_BLANK_DATA_COLOR", REG_MMIO, 0x1c61, 2, &mmOTG2_OTG_BLANK_DATA_COLOR[0], sizeof(mmOTG2_OTG_BLANK_DATA_COLOR)/sizeof(mmOTG2_OTG_BLANK_DATA_COLOR[0]), 0, 0 }, + { "mmOTG2_OTG_BLANK_DATA_COLOR_EXT", REG_MMIO, 0x1c62, 2, &mmOTG2_OTG_BLANK_DATA_COLOR_EXT[0], sizeof(mmOTG2_OTG_BLANK_DATA_COLOR_EXT)/sizeof(mmOTG2_OTG_BLANK_DATA_COLOR_EXT[0]), 0, 0 }, + { "mmOTG2_OTG_BLACK_COLOR", REG_MMIO, 0x1c63, 2, &mmOTG2_OTG_BLACK_COLOR[0], sizeof(mmOTG2_OTG_BLACK_COLOR)/sizeof(mmOTG2_OTG_BLACK_COLOR[0]), 0, 0 }, + { "mmOTG2_OTG_BLACK_COLOR_EXT", REG_MMIO, 0x1c64, 2, &mmOTG2_OTG_BLACK_COLOR_EXT[0], sizeof(mmOTG2_OTG_BLACK_COLOR_EXT)/sizeof(mmOTG2_OTG_BLACK_COLOR_EXT[0]), 0, 0 }, + { "mmOTG2_OTG_VERTICAL_INTERRUPT0_POSITION", REG_MMIO, 0x1c65, 2, &mmOTG2_OTG_VERTICAL_INTERRUPT0_POSITION[0], sizeof(mmOTG2_OTG_VERTICAL_INTERRUPT0_POSITION)/sizeof(mmOTG2_OTG_VERTICAL_INTERRUPT0_POSITION[0]), 0, 0 }, + { "mmOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL", REG_MMIO, 0x1c66, 2, &mmOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL[0], sizeof(mmOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL)/sizeof(mmOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL[0]), 0, 0 }, + { "mmOTG2_OTG_VERTICAL_INTERRUPT1_POSITION", REG_MMIO, 0x1c67, 2, &mmOTG2_OTG_VERTICAL_INTERRUPT1_POSITION[0], sizeof(mmOTG2_OTG_VERTICAL_INTERRUPT1_POSITION)/sizeof(mmOTG2_OTG_VERTICAL_INTERRUPT1_POSITION[0]), 0, 0 }, + { "mmOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL", REG_MMIO, 0x1c68, 2, &mmOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL[0], sizeof(mmOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL)/sizeof(mmOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL[0]), 0, 0 }, + { "mmOTG2_OTG_VERTICAL_INTERRUPT2_POSITION", REG_MMIO, 0x1c69, 2, &mmOTG2_OTG_VERTICAL_INTERRUPT2_POSITION[0], sizeof(mmOTG2_OTG_VERTICAL_INTERRUPT2_POSITION)/sizeof(mmOTG2_OTG_VERTICAL_INTERRUPT2_POSITION[0]), 0, 0 }, + { "mmOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL", REG_MMIO, 0x1c6a, 2, &mmOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL[0], sizeof(mmOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL)/sizeof(mmOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL[0]), 0, 0 }, + { "mmOTG2_OTG_CRC_CNTL", REG_MMIO, 0x1c6b, 2, &mmOTG2_OTG_CRC_CNTL[0], sizeof(mmOTG2_OTG_CRC_CNTL)/sizeof(mmOTG2_OTG_CRC_CNTL[0]), 0, 0 }, + { "mmOTG2_OTG_CRC0_WINDOWA_X_CONTROL", REG_MMIO, 0x1c6c, 2, &mmOTG2_OTG_CRC0_WINDOWA_X_CONTROL[0], sizeof(mmOTG2_OTG_CRC0_WINDOWA_X_CONTROL)/sizeof(mmOTG2_OTG_CRC0_WINDOWA_X_CONTROL[0]), 0, 0 }, + { "mmOTG2_OTG_CRC0_WINDOWA_Y_CONTROL", REG_MMIO, 0x1c6d, 2, &mmOTG2_OTG_CRC0_WINDOWA_Y_CONTROL[0], sizeof(mmOTG2_OTG_CRC0_WINDOWA_Y_CONTROL)/sizeof(mmOTG2_OTG_CRC0_WINDOWA_Y_CONTROL[0]), 0, 0 }, + { "mmOTG2_OTG_CRC0_WINDOWB_X_CONTROL", REG_MMIO, 0x1c6e, 2, &mmOTG2_OTG_CRC0_WINDOWB_X_CONTROL[0], sizeof(mmOTG2_OTG_CRC0_WINDOWB_X_CONTROL)/sizeof(mmOTG2_OTG_CRC0_WINDOWB_X_CONTROL[0]), 0, 0 }, + { "mmOTG2_OTG_CRC0_WINDOWB_Y_CONTROL", REG_MMIO, 0x1c6f, 2, &mmOTG2_OTG_CRC0_WINDOWB_Y_CONTROL[0], sizeof(mmOTG2_OTG_CRC0_WINDOWB_Y_CONTROL)/sizeof(mmOTG2_OTG_CRC0_WINDOWB_Y_CONTROL[0]), 0, 0 }, + { "mmOTG2_OTG_CRC0_DATA_RG", REG_MMIO, 0x1c70, 2, &mmOTG2_OTG_CRC0_DATA_RG[0], sizeof(mmOTG2_OTG_CRC0_DATA_RG)/sizeof(mmOTG2_OTG_CRC0_DATA_RG[0]), 0, 0 }, + { "mmOTG2_OTG_CRC0_DATA_B", REG_MMIO, 0x1c71, 2, &mmOTG2_OTG_CRC0_DATA_B[0], sizeof(mmOTG2_OTG_CRC0_DATA_B)/sizeof(mmOTG2_OTG_CRC0_DATA_B[0]), 0, 0 }, + { "mmOTG2_OTG_CRC1_WINDOWA_X_CONTROL", REG_MMIO, 0x1c72, 2, &mmOTG2_OTG_CRC1_WINDOWA_X_CONTROL[0], sizeof(mmOTG2_OTG_CRC1_WINDOWA_X_CONTROL)/sizeof(mmOTG2_OTG_CRC1_WINDOWA_X_CONTROL[0]), 0, 0 }, + { "mmOTG2_OTG_CRC1_WINDOWA_Y_CONTROL", REG_MMIO, 0x1c73, 2, &mmOTG2_OTG_CRC1_WINDOWA_Y_CONTROL[0], sizeof(mmOTG2_OTG_CRC1_WINDOWA_Y_CONTROL)/sizeof(mmOTG2_OTG_CRC1_WINDOWA_Y_CONTROL[0]), 0, 0 }, + { "mmOTG2_OTG_CRC1_WINDOWB_X_CONTROL", REG_MMIO, 0x1c74, 2, &mmOTG2_OTG_CRC1_WINDOWB_X_CONTROL[0], sizeof(mmOTG2_OTG_CRC1_WINDOWB_X_CONTROL)/sizeof(mmOTG2_OTG_CRC1_WINDOWB_X_CONTROL[0]), 0, 0 }, + { "mmOTG2_OTG_CRC1_WINDOWB_Y_CONTROL", REG_MMIO, 0x1c75, 2, &mmOTG2_OTG_CRC1_WINDOWB_Y_CONTROL[0], sizeof(mmOTG2_OTG_CRC1_WINDOWB_Y_CONTROL)/sizeof(mmOTG2_OTG_CRC1_WINDOWB_Y_CONTROL[0]), 0, 0 }, + { "mmOTG2_OTG_CRC1_DATA_RG", REG_MMIO, 0x1c76, 2, &mmOTG2_OTG_CRC1_DATA_RG[0], sizeof(mmOTG2_OTG_CRC1_DATA_RG)/sizeof(mmOTG2_OTG_CRC1_DATA_RG[0]), 0, 0 }, + { "mmOTG2_OTG_CRC1_DATA_B", REG_MMIO, 0x1c77, 2, &mmOTG2_OTG_CRC1_DATA_B[0], sizeof(mmOTG2_OTG_CRC1_DATA_B)/sizeof(mmOTG2_OTG_CRC1_DATA_B[0]), 0, 0 }, + { "mmOTG2_OTG_CRC2_DATA_RG", REG_MMIO, 0x1c78, 2, &mmOTG2_OTG_CRC2_DATA_RG[0], sizeof(mmOTG2_OTG_CRC2_DATA_RG)/sizeof(mmOTG2_OTG_CRC2_DATA_RG[0]), 0, 0 }, + { "mmOTG2_OTG_CRC2_DATA_B", REG_MMIO, 0x1c79, 2, &mmOTG2_OTG_CRC2_DATA_B[0], sizeof(mmOTG2_OTG_CRC2_DATA_B)/sizeof(mmOTG2_OTG_CRC2_DATA_B[0]), 0, 0 }, + { "mmOTG2_OTG_CRC3_DATA_RG", REG_MMIO, 0x1c7a, 2, &mmOTG2_OTG_CRC3_DATA_RG[0], sizeof(mmOTG2_OTG_CRC3_DATA_RG)/sizeof(mmOTG2_OTG_CRC3_DATA_RG[0]), 0, 0 }, + { "mmOTG2_OTG_CRC3_DATA_B", REG_MMIO, 0x1c7b, 2, &mmOTG2_OTG_CRC3_DATA_B[0], sizeof(mmOTG2_OTG_CRC3_DATA_B)/sizeof(mmOTG2_OTG_CRC3_DATA_B[0]), 0, 0 }, + { "mmOTG2_OTG_CRC_SIG_RED_GREEN_MASK", REG_MMIO, 0x1c7c, 2, &mmOTG2_OTG_CRC_SIG_RED_GREEN_MASK[0], sizeof(mmOTG2_OTG_CRC_SIG_RED_GREEN_MASK)/sizeof(mmOTG2_OTG_CRC_SIG_RED_GREEN_MASK[0]), 0, 0 }, + { "mmOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK", REG_MMIO, 0x1c7d, 2, &mmOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK[0], sizeof(mmOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK)/sizeof(mmOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK[0]), 0, 0 }, + { "mmOTG2_OTG_STATIC_SCREEN_CONTROL", REG_MMIO, 0x1c84, 2, &mmOTG2_OTG_STATIC_SCREEN_CONTROL[0], sizeof(mmOTG2_OTG_STATIC_SCREEN_CONTROL)/sizeof(mmOTG2_OTG_STATIC_SCREEN_CONTROL[0]), 0, 0 }, + { "mmOTG2_OTG_3D_STRUCTURE_CONTROL", REG_MMIO, 0x1c85, 2, &mmOTG2_OTG_3D_STRUCTURE_CONTROL[0], sizeof(mmOTG2_OTG_3D_STRUCTURE_CONTROL)/sizeof(mmOTG2_OTG_3D_STRUCTURE_CONTROL[0]), 0, 0 }, + { "mmOTG2_OTG_GSL_VSYNC_GAP", REG_MMIO, 0x1c86, 2, &mmOTG2_OTG_GSL_VSYNC_GAP[0], sizeof(mmOTG2_OTG_GSL_VSYNC_GAP)/sizeof(mmOTG2_OTG_GSL_VSYNC_GAP[0]), 0, 0 }, + { "mmOTG2_OTG_MASTER_UPDATE_MODE", REG_MMIO, 0x1c87, 2, &mmOTG2_OTG_MASTER_UPDATE_MODE[0], sizeof(mmOTG2_OTG_MASTER_UPDATE_MODE)/sizeof(mmOTG2_OTG_MASTER_UPDATE_MODE[0]), 0, 0 }, + { "mmOTG2_OTG_CLOCK_CONTROL", REG_MMIO, 0x1c88, 2, &mmOTG2_OTG_CLOCK_CONTROL[0], sizeof(mmOTG2_OTG_CLOCK_CONTROL)/sizeof(mmOTG2_OTG_CLOCK_CONTROL[0]), 0, 0 }, + { "mmOTG2_OTG_VSTARTUP_PARAM", REG_MMIO, 0x1c89, 2, &mmOTG2_OTG_VSTARTUP_PARAM[0], sizeof(mmOTG2_OTG_VSTARTUP_PARAM)/sizeof(mmOTG2_OTG_VSTARTUP_PARAM[0]), 0, 0 }, + { "mmOTG2_OTG_VUPDATE_PARAM", REG_MMIO, 0x1c8a, 2, &mmOTG2_OTG_VUPDATE_PARAM[0], sizeof(mmOTG2_OTG_VUPDATE_PARAM)/sizeof(mmOTG2_OTG_VUPDATE_PARAM[0]), 0, 0 }, + { "mmOTG2_OTG_VREADY_PARAM", REG_MMIO, 0x1c8b, 2, &mmOTG2_OTG_VREADY_PARAM[0], sizeof(mmOTG2_OTG_VREADY_PARAM)/sizeof(mmOTG2_OTG_VREADY_PARAM[0]), 0, 0 }, + { "mmOTG2_OTG_GLOBAL_SYNC_STATUS", REG_MMIO, 0x1c8c, 2, &mmOTG2_OTG_GLOBAL_SYNC_STATUS[0], sizeof(mmOTG2_OTG_GLOBAL_SYNC_STATUS)/sizeof(mmOTG2_OTG_GLOBAL_SYNC_STATUS[0]), 0, 0 }, + { "mmOTG2_OTG_MASTER_UPDATE_LOCK", REG_MMIO, 0x1c8d, 2, &mmOTG2_OTG_MASTER_UPDATE_LOCK[0], sizeof(mmOTG2_OTG_MASTER_UPDATE_LOCK)/sizeof(mmOTG2_OTG_MASTER_UPDATE_LOCK[0]), 0, 0 }, + { "mmOTG2_OTG_GSL_CONTROL", REG_MMIO, 0x1c8e, 2, &mmOTG2_OTG_GSL_CONTROL[0], sizeof(mmOTG2_OTG_GSL_CONTROL)/sizeof(mmOTG2_OTG_GSL_CONTROL[0]), 0, 0 }, + { "mmOTG2_OTG_GSL_WINDOW_X", REG_MMIO, 0x1c8f, 2, &mmOTG2_OTG_GSL_WINDOW_X[0], sizeof(mmOTG2_OTG_GSL_WINDOW_X)/sizeof(mmOTG2_OTG_GSL_WINDOW_X[0]), 0, 0 }, + { "mmOTG2_OTG_GSL_WINDOW_Y", REG_MMIO, 0x1c90, 2, &mmOTG2_OTG_GSL_WINDOW_Y[0], sizeof(mmOTG2_OTG_GSL_WINDOW_Y)/sizeof(mmOTG2_OTG_GSL_WINDOW_Y[0]), 0, 0 }, + { "mmOTG2_OTG_VUPDATE_KEEPOUT", REG_MMIO, 0x1c91, 2, &mmOTG2_OTG_VUPDATE_KEEPOUT[0], sizeof(mmOTG2_OTG_VUPDATE_KEEPOUT)/sizeof(mmOTG2_OTG_VUPDATE_KEEPOUT[0]), 0, 0 }, + { "mmOTG2_OTG_GLOBAL_CONTROL0", REG_MMIO, 0x1c92, 2, &mmOTG2_OTG_GLOBAL_CONTROL0[0], sizeof(mmOTG2_OTG_GLOBAL_CONTROL0)/sizeof(mmOTG2_OTG_GLOBAL_CONTROL0[0]), 0, 0 }, + { "mmOTG2_OTG_GLOBAL_CONTROL1", REG_MMIO, 0x1c93, 2, &mmOTG2_OTG_GLOBAL_CONTROL1[0], sizeof(mmOTG2_OTG_GLOBAL_CONTROL1)/sizeof(mmOTG2_OTG_GLOBAL_CONTROL1[0]), 0, 0 }, + { "mmOTG2_OTG_GLOBAL_CONTROL2", REG_MMIO, 0x1c94, 2, &mmOTG2_OTG_GLOBAL_CONTROL2[0], sizeof(mmOTG2_OTG_GLOBAL_CONTROL2)/sizeof(mmOTG2_OTG_GLOBAL_CONTROL2[0]), 0, 0 }, + { "mmOTG2_OTG_GLOBAL_CONTROL3", REG_MMIO, 0x1c95, 2, &mmOTG2_OTG_GLOBAL_CONTROL3[0], sizeof(mmOTG2_OTG_GLOBAL_CONTROL3)/sizeof(mmOTG2_OTG_GLOBAL_CONTROL3[0]), 0, 0 }, + { "mmOTG2_OTG_TRIG_MANUAL_CONTROL", REG_MMIO, 0x1c96, 2, &mmOTG2_OTG_TRIG_MANUAL_CONTROL[0], sizeof(mmOTG2_OTG_TRIG_MANUAL_CONTROL)/sizeof(mmOTG2_OTG_TRIG_MANUAL_CONTROL[0]), 0, 0 }, + { "mmOTG2_OTG_MANUAL_FLOW_CONTROL", REG_MMIO, 0x1c97, 2, &mmOTG2_OTG_MANUAL_FLOW_CONTROL[0], sizeof(mmOTG2_OTG_MANUAL_FLOW_CONTROL)/sizeof(mmOTG2_OTG_MANUAL_FLOW_CONTROL[0]), 0, 0 }, + { "mmOTG2_OTG_RANGE_TIMING_INT_STATUS", REG_MMIO, 0x1c98, 2, &mmOTG2_OTG_RANGE_TIMING_INT_STATUS[0], sizeof(mmOTG2_OTG_RANGE_TIMING_INT_STATUS)/sizeof(mmOTG2_OTG_RANGE_TIMING_INT_STATUS[0]), 0, 0 }, + { "mmOTG2_OTG_DRR_CONTROL", REG_MMIO, 0x1c99, 2, &mmOTG2_OTG_DRR_CONTROL[0], sizeof(mmOTG2_OTG_DRR_CONTROL)/sizeof(mmOTG2_OTG_DRR_CONTROL[0]), 0, 0 }, + { "mmOTG2_OTG_REQUEST_CONTROL", REG_MMIO, 0x1c9a, 2, &mmOTG2_OTG_REQUEST_CONTROL[0], sizeof(mmOTG2_OTG_REQUEST_CONTROL)/sizeof(mmOTG2_OTG_REQUEST_CONTROL[0]), 0, 0 }, + { "mmOTG2_OTG_SPARE_REGISTER", REG_MMIO, 0x1c9b, 2, &mmOTG2_OTG_SPARE_REGISTER[0], sizeof(mmOTG2_OTG_SPARE_REGISTER)/sizeof(mmOTG2_OTG_SPARE_REGISTER[0]), 0, 0 }, + { "mmOTG3_OTG_H_TOTAL", REG_MMIO, 0x1caa, 2, &mmOTG3_OTG_H_TOTAL[0], sizeof(mmOTG3_OTG_H_TOTAL)/sizeof(mmOTG3_OTG_H_TOTAL[0]), 0, 0 }, + { "mmOTG3_OTG_H_BLANK_START_END", REG_MMIO, 0x1cab, 2, &mmOTG3_OTG_H_BLANK_START_END[0], sizeof(mmOTG3_OTG_H_BLANK_START_END)/sizeof(mmOTG3_OTG_H_BLANK_START_END[0]), 0, 0 }, + { "mmOTG3_OTG_H_SYNC_A", REG_MMIO, 0x1cac, 2, &mmOTG3_OTG_H_SYNC_A[0], sizeof(mmOTG3_OTG_H_SYNC_A)/sizeof(mmOTG3_OTG_H_SYNC_A[0]), 0, 0 }, + { "mmOTG3_OTG_H_SYNC_A_CNTL", REG_MMIO, 0x1cad, 2, &mmOTG3_OTG_H_SYNC_A_CNTL[0], sizeof(mmOTG3_OTG_H_SYNC_A_CNTL)/sizeof(mmOTG3_OTG_H_SYNC_A_CNTL[0]), 0, 0 }, + { "mmOTG3_OTG_H_TIMING_CNTL", REG_MMIO, 0x1cae, 2, &mmOTG3_OTG_H_TIMING_CNTL[0], sizeof(mmOTG3_OTG_H_TIMING_CNTL)/sizeof(mmOTG3_OTG_H_TIMING_CNTL[0]), 0, 0 }, + { "mmOTG3_OTG_V_TOTAL", REG_MMIO, 0x1caf, 2, &mmOTG3_OTG_V_TOTAL[0], sizeof(mmOTG3_OTG_V_TOTAL)/sizeof(mmOTG3_OTG_V_TOTAL[0]), 0, 0 }, + { "mmOTG3_OTG_V_TOTAL_MIN", REG_MMIO, 0x1cb0, 2, &mmOTG3_OTG_V_TOTAL_MIN[0], sizeof(mmOTG3_OTG_V_TOTAL_MIN)/sizeof(mmOTG3_OTG_V_TOTAL_MIN[0]), 0, 0 }, + { "mmOTG3_OTG_V_TOTAL_MAX", REG_MMIO, 0x1cb1, 2, &mmOTG3_OTG_V_TOTAL_MAX[0], sizeof(mmOTG3_OTG_V_TOTAL_MAX)/sizeof(mmOTG3_OTG_V_TOTAL_MAX[0]), 0, 0 }, + { "mmOTG3_OTG_V_TOTAL_MID", REG_MMIO, 0x1cb2, 2, &mmOTG3_OTG_V_TOTAL_MID[0], sizeof(mmOTG3_OTG_V_TOTAL_MID)/sizeof(mmOTG3_OTG_V_TOTAL_MID[0]), 0, 0 }, + { "mmOTG3_OTG_V_TOTAL_CONTROL", REG_MMIO, 0x1cb3, 2, &mmOTG3_OTG_V_TOTAL_CONTROL[0], sizeof(mmOTG3_OTG_V_TOTAL_CONTROL)/sizeof(mmOTG3_OTG_V_TOTAL_CONTROL[0]), 0, 0 }, + { "mmOTG3_OTG_V_TOTAL_INT_STATUS", REG_MMIO, 0x1cb4, 2, &mmOTG3_OTG_V_TOTAL_INT_STATUS[0], sizeof(mmOTG3_OTG_V_TOTAL_INT_STATUS)/sizeof(mmOTG3_OTG_V_TOTAL_INT_STATUS[0]), 0, 0 }, + { "mmOTG3_OTG_VSYNC_NOM_INT_STATUS", REG_MMIO, 0x1cb5, 2, &mmOTG3_OTG_VSYNC_NOM_INT_STATUS[0], sizeof(mmOTG3_OTG_VSYNC_NOM_INT_STATUS)/sizeof(mmOTG3_OTG_VSYNC_NOM_INT_STATUS[0]), 0, 0 }, + { "mmOTG3_OTG_V_BLANK_START_END", REG_MMIO, 0x1cb6, 2, &mmOTG3_OTG_V_BLANK_START_END[0], sizeof(mmOTG3_OTG_V_BLANK_START_END)/sizeof(mmOTG3_OTG_V_BLANK_START_END[0]), 0, 0 }, + { "mmOTG3_OTG_V_SYNC_A", REG_MMIO, 0x1cb7, 2, &mmOTG3_OTG_V_SYNC_A[0], sizeof(mmOTG3_OTG_V_SYNC_A)/sizeof(mmOTG3_OTG_V_SYNC_A[0]), 0, 0 }, + { "mmOTG3_OTG_V_SYNC_A_CNTL", REG_MMIO, 0x1cb8, 2, &mmOTG3_OTG_V_SYNC_A_CNTL[0], sizeof(mmOTG3_OTG_V_SYNC_A_CNTL)/sizeof(mmOTG3_OTG_V_SYNC_A_CNTL[0]), 0, 0 }, + { "mmOTG3_OTG_TRIGA_CNTL", REG_MMIO, 0x1cb9, 2, &mmOTG3_OTG_TRIGA_CNTL[0], sizeof(mmOTG3_OTG_TRIGA_CNTL)/sizeof(mmOTG3_OTG_TRIGA_CNTL[0]), 0, 0 }, + { "mmOTG3_OTG_TRIGA_MANUAL_TRIG", REG_MMIO, 0x1cba, 2, &mmOTG3_OTG_TRIGA_MANUAL_TRIG[0], sizeof(mmOTG3_OTG_TRIGA_MANUAL_TRIG)/sizeof(mmOTG3_OTG_TRIGA_MANUAL_TRIG[0]), 0, 0 }, + { "mmOTG3_OTG_TRIGB_CNTL", REG_MMIO, 0x1cbb, 2, &mmOTG3_OTG_TRIGB_CNTL[0], sizeof(mmOTG3_OTG_TRIGB_CNTL)/sizeof(mmOTG3_OTG_TRIGB_CNTL[0]), 0, 0 }, + { "mmOTG3_OTG_TRIGB_MANUAL_TRIG", REG_MMIO, 0x1cbc, 2, &mmOTG3_OTG_TRIGB_MANUAL_TRIG[0], sizeof(mmOTG3_OTG_TRIGB_MANUAL_TRIG)/sizeof(mmOTG3_OTG_TRIGB_MANUAL_TRIG[0]), 0, 0 }, + { "mmOTG3_OTG_FORCE_COUNT_NOW_CNTL", REG_MMIO, 0x1cbd, 2, &mmOTG3_OTG_FORCE_COUNT_NOW_CNTL[0], sizeof(mmOTG3_OTG_FORCE_COUNT_NOW_CNTL)/sizeof(mmOTG3_OTG_FORCE_COUNT_NOW_CNTL[0]), 0, 0 }, + { "mmOTG3_OTG_FLOW_CONTROL", REG_MMIO, 0x1cbe, 2, &mmOTG3_OTG_FLOW_CONTROL[0], sizeof(mmOTG3_OTG_FLOW_CONTROL)/sizeof(mmOTG3_OTG_FLOW_CONTROL[0]), 0, 0 }, + { "mmOTG3_OTG_STEREO_FORCE_NEXT_EYE", REG_MMIO, 0x1cbf, 2, &mmOTG3_OTG_STEREO_FORCE_NEXT_EYE[0], sizeof(mmOTG3_OTG_STEREO_FORCE_NEXT_EYE)/sizeof(mmOTG3_OTG_STEREO_FORCE_NEXT_EYE[0]), 0, 0 }, + { "mmOTG3_OTG_AVSYNC_COUNTER", REG_MMIO, 0x1cc0, 2, &mmOTG3_OTG_AVSYNC_COUNTER[0], sizeof(mmOTG3_OTG_AVSYNC_COUNTER)/sizeof(mmOTG3_OTG_AVSYNC_COUNTER[0]), 0, 0 }, + { "mmOTG3_OTG_CONTROL", REG_MMIO, 0x1cc1, 2, &mmOTG3_OTG_CONTROL[0], sizeof(mmOTG3_OTG_CONTROL)/sizeof(mmOTG3_OTG_CONTROL[0]), 0, 0 }, + { "mmOTG3_OTG_BLANK_CONTROL", REG_MMIO, 0x1cc2, 2, &mmOTG3_OTG_BLANK_CONTROL[0], sizeof(mmOTG3_OTG_BLANK_CONTROL)/sizeof(mmOTG3_OTG_BLANK_CONTROL[0]), 0, 0 }, + { "mmOTG3_OTG_PIPE_ABORT_CONTROL", REG_MMIO, 0x1cc3, 2, &mmOTG3_OTG_PIPE_ABORT_CONTROL[0], sizeof(mmOTG3_OTG_PIPE_ABORT_CONTROL)/sizeof(mmOTG3_OTG_PIPE_ABORT_CONTROL[0]), 0, 0 }, + { "mmOTG3_OTG_INTERLACE_CONTROL", REG_MMIO, 0x1cc4, 2, &mmOTG3_OTG_INTERLACE_CONTROL[0], sizeof(mmOTG3_OTG_INTERLACE_CONTROL)/sizeof(mmOTG3_OTG_INTERLACE_CONTROL[0]), 0, 0 }, + { "mmOTG3_OTG_INTERLACE_STATUS", REG_MMIO, 0x1cc5, 2, &mmOTG3_OTG_INTERLACE_STATUS[0], sizeof(mmOTG3_OTG_INTERLACE_STATUS)/sizeof(mmOTG3_OTG_INTERLACE_STATUS[0]), 0, 0 }, + { "mmOTG3_OTG_FIELD_INDICATION_CONTROL", REG_MMIO, 0x1cc6, 2, &mmOTG3_OTG_FIELD_INDICATION_CONTROL[0], sizeof(mmOTG3_OTG_FIELD_INDICATION_CONTROL)/sizeof(mmOTG3_OTG_FIELD_INDICATION_CONTROL[0]), 0, 0 }, + { "mmOTG3_OTG_PIXEL_DATA_READBACK0", REG_MMIO, 0x1cc7, 2, &mmOTG3_OTG_PIXEL_DATA_READBACK0[0], sizeof(mmOTG3_OTG_PIXEL_DATA_READBACK0)/sizeof(mmOTG3_OTG_PIXEL_DATA_READBACK0[0]), 0, 0 }, + { "mmOTG3_OTG_PIXEL_DATA_READBACK1", REG_MMIO, 0x1cc8, 2, &mmOTG3_OTG_PIXEL_DATA_READBACK1[0], sizeof(mmOTG3_OTG_PIXEL_DATA_READBACK1)/sizeof(mmOTG3_OTG_PIXEL_DATA_READBACK1[0]), 0, 0 }, + { "mmOTG3_OTG_STATUS", REG_MMIO, 0x1cc9, 2, &mmOTG3_OTG_STATUS[0], sizeof(mmOTG3_OTG_STATUS)/sizeof(mmOTG3_OTG_STATUS[0]), 0, 0 }, + { "mmOTG3_OTG_STATUS_POSITION", REG_MMIO, 0x1cca, 2, &mmOTG3_OTG_STATUS_POSITION[0], sizeof(mmOTG3_OTG_STATUS_POSITION)/sizeof(mmOTG3_OTG_STATUS_POSITION[0]), 0, 0 }, + { "mmOTG3_OTG_NOM_VERT_POSITION", REG_MMIO, 0x1ccb, 2, &mmOTG3_OTG_NOM_VERT_POSITION[0], sizeof(mmOTG3_OTG_NOM_VERT_POSITION)/sizeof(mmOTG3_OTG_NOM_VERT_POSITION[0]), 0, 0 }, + { "mmOTG3_OTG_STATUS_FRAME_COUNT", REG_MMIO, 0x1ccc, 2, &mmOTG3_OTG_STATUS_FRAME_COUNT[0], sizeof(mmOTG3_OTG_STATUS_FRAME_COUNT)/sizeof(mmOTG3_OTG_STATUS_FRAME_COUNT[0]), 0, 0 }, + { "mmOTG3_OTG_STATUS_VF_COUNT", REG_MMIO, 0x1ccd, 2, &mmOTG3_OTG_STATUS_VF_COUNT[0], sizeof(mmOTG3_OTG_STATUS_VF_COUNT)/sizeof(mmOTG3_OTG_STATUS_VF_COUNT[0]), 0, 0 }, + { "mmOTG3_OTG_STATUS_HV_COUNT", REG_MMIO, 0x1cce, 2, &mmOTG3_OTG_STATUS_HV_COUNT[0], sizeof(mmOTG3_OTG_STATUS_HV_COUNT)/sizeof(mmOTG3_OTG_STATUS_HV_COUNT[0]), 0, 0 }, + { "mmOTG3_OTG_COUNT_CONTROL", REG_MMIO, 0x1ccf, 2, &mmOTG3_OTG_COUNT_CONTROL[0], sizeof(mmOTG3_OTG_COUNT_CONTROL)/sizeof(mmOTG3_OTG_COUNT_CONTROL[0]), 0, 0 }, + { "mmOTG3_OTG_COUNT_RESET", REG_MMIO, 0x1cd0, 2, &mmOTG3_OTG_COUNT_RESET[0], sizeof(mmOTG3_OTG_COUNT_RESET)/sizeof(mmOTG3_OTG_COUNT_RESET[0]), 0, 0 }, + { "mmOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE", REG_MMIO, 0x1cd1, 2, &mmOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE[0], sizeof(mmOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE)/sizeof(mmOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE[0]), 0, 0 }, + { "mmOTG3_OTG_VERT_SYNC_CONTROL", REG_MMIO, 0x1cd2, 2, &mmOTG3_OTG_VERT_SYNC_CONTROL[0], sizeof(mmOTG3_OTG_VERT_SYNC_CONTROL)/sizeof(mmOTG3_OTG_VERT_SYNC_CONTROL[0]), 0, 0 }, + { "mmOTG3_OTG_STEREO_STATUS", REG_MMIO, 0x1cd3, 2, &mmOTG3_OTG_STEREO_STATUS[0], sizeof(mmOTG3_OTG_STEREO_STATUS)/sizeof(mmOTG3_OTG_STEREO_STATUS[0]), 0, 0 }, + { "mmOTG3_OTG_STEREO_CONTROL", REG_MMIO, 0x1cd4, 2, &mmOTG3_OTG_STEREO_CONTROL[0], sizeof(mmOTG3_OTG_STEREO_CONTROL)/sizeof(mmOTG3_OTG_STEREO_CONTROL[0]), 0, 0 }, + { "mmOTG3_OTG_SNAPSHOT_STATUS", REG_MMIO, 0x1cd5, 2, &mmOTG3_OTG_SNAPSHOT_STATUS[0], sizeof(mmOTG3_OTG_SNAPSHOT_STATUS)/sizeof(mmOTG3_OTG_SNAPSHOT_STATUS[0]), 0, 0 }, + { "mmOTG3_OTG_SNAPSHOT_CONTROL", REG_MMIO, 0x1cd6, 2, &mmOTG3_OTG_SNAPSHOT_CONTROL[0], sizeof(mmOTG3_OTG_SNAPSHOT_CONTROL)/sizeof(mmOTG3_OTG_SNAPSHOT_CONTROL[0]), 0, 0 }, + { "mmOTG3_OTG_SNAPSHOT_POSITION", REG_MMIO, 0x1cd7, 2, &mmOTG3_OTG_SNAPSHOT_POSITION[0], sizeof(mmOTG3_OTG_SNAPSHOT_POSITION)/sizeof(mmOTG3_OTG_SNAPSHOT_POSITION[0]), 0, 0 }, + { "mmOTG3_OTG_SNAPSHOT_FRAME", REG_MMIO, 0x1cd8, 2, &mmOTG3_OTG_SNAPSHOT_FRAME[0], sizeof(mmOTG3_OTG_SNAPSHOT_FRAME)/sizeof(mmOTG3_OTG_SNAPSHOT_FRAME[0]), 0, 0 }, + { "mmOTG3_OTG_INTERRUPT_CONTROL", REG_MMIO, 0x1cd9, 2, &mmOTG3_OTG_INTERRUPT_CONTROL[0], sizeof(mmOTG3_OTG_INTERRUPT_CONTROL)/sizeof(mmOTG3_OTG_INTERRUPT_CONTROL[0]), 0, 0 }, + { "mmOTG3_OTG_UPDATE_LOCK", REG_MMIO, 0x1cda, 2, &mmOTG3_OTG_UPDATE_LOCK[0], sizeof(mmOTG3_OTG_UPDATE_LOCK)/sizeof(mmOTG3_OTG_UPDATE_LOCK[0]), 0, 0 }, + { "mmOTG3_OTG_DOUBLE_BUFFER_CONTROL", REG_MMIO, 0x1cdb, 2, &mmOTG3_OTG_DOUBLE_BUFFER_CONTROL[0], sizeof(mmOTG3_OTG_DOUBLE_BUFFER_CONTROL)/sizeof(mmOTG3_OTG_DOUBLE_BUFFER_CONTROL[0]), 0, 0 }, + { "mmOTG3_OTG_TEST_PATTERN_CONTROL", REG_MMIO, 0x1cdc, 2, &mmOTG3_OTG_TEST_PATTERN_CONTROL[0], sizeof(mmOTG3_OTG_TEST_PATTERN_CONTROL)/sizeof(mmOTG3_OTG_TEST_PATTERN_CONTROL[0]), 0, 0 }, + { "mmOTG3_OTG_TEST_PATTERN_PARAMETERS", REG_MMIO, 0x1cdd, 2, &mmOTG3_OTG_TEST_PATTERN_PARAMETERS[0], sizeof(mmOTG3_OTG_TEST_PATTERN_PARAMETERS)/sizeof(mmOTG3_OTG_TEST_PATTERN_PARAMETERS[0]), 0, 0 }, + { "mmOTG3_OTG_TEST_PATTERN_COLOR", REG_MMIO, 0x1cde, 2, &mmOTG3_OTG_TEST_PATTERN_COLOR[0], sizeof(mmOTG3_OTG_TEST_PATTERN_COLOR)/sizeof(mmOTG3_OTG_TEST_PATTERN_COLOR[0]), 0, 0 }, + { "mmOTG3_OTG_MASTER_EN", REG_MMIO, 0x1cdf, 2, &mmOTG3_OTG_MASTER_EN[0], sizeof(mmOTG3_OTG_MASTER_EN)/sizeof(mmOTG3_OTG_MASTER_EN[0]), 0, 0 }, + { "mmOTG3_OTG_BLANK_DATA_COLOR", REG_MMIO, 0x1ce1, 2, &mmOTG3_OTG_BLANK_DATA_COLOR[0], sizeof(mmOTG3_OTG_BLANK_DATA_COLOR)/sizeof(mmOTG3_OTG_BLANK_DATA_COLOR[0]), 0, 0 }, + { "mmOTG3_OTG_BLANK_DATA_COLOR_EXT", REG_MMIO, 0x1ce2, 2, &mmOTG3_OTG_BLANK_DATA_COLOR_EXT[0], sizeof(mmOTG3_OTG_BLANK_DATA_COLOR_EXT)/sizeof(mmOTG3_OTG_BLANK_DATA_COLOR_EXT[0]), 0, 0 }, + { "mmOTG3_OTG_BLACK_COLOR", REG_MMIO, 0x1ce3, 2, &mmOTG3_OTG_BLACK_COLOR[0], sizeof(mmOTG3_OTG_BLACK_COLOR)/sizeof(mmOTG3_OTG_BLACK_COLOR[0]), 0, 0 }, + { "mmOTG3_OTG_BLACK_COLOR_EXT", REG_MMIO, 0x1ce4, 2, &mmOTG3_OTG_BLACK_COLOR_EXT[0], sizeof(mmOTG3_OTG_BLACK_COLOR_EXT)/sizeof(mmOTG3_OTG_BLACK_COLOR_EXT[0]), 0, 0 }, + { "mmOTG3_OTG_VERTICAL_INTERRUPT0_POSITION", REG_MMIO, 0x1ce5, 2, &mmOTG3_OTG_VERTICAL_INTERRUPT0_POSITION[0], sizeof(mmOTG3_OTG_VERTICAL_INTERRUPT0_POSITION)/sizeof(mmOTG3_OTG_VERTICAL_INTERRUPT0_POSITION[0]), 0, 0 }, + { "mmOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL", REG_MMIO, 0x1ce6, 2, &mmOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL[0], sizeof(mmOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL)/sizeof(mmOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL[0]), 0, 0 }, + { "mmOTG3_OTG_VERTICAL_INTERRUPT1_POSITION", REG_MMIO, 0x1ce7, 2, &mmOTG3_OTG_VERTICAL_INTERRUPT1_POSITION[0], sizeof(mmOTG3_OTG_VERTICAL_INTERRUPT1_POSITION)/sizeof(mmOTG3_OTG_VERTICAL_INTERRUPT1_POSITION[0]), 0, 0 }, + { "mmOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL", REG_MMIO, 0x1ce8, 2, &mmOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL[0], sizeof(mmOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL)/sizeof(mmOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL[0]), 0, 0 }, + { "mmOTG3_OTG_VERTICAL_INTERRUPT2_POSITION", REG_MMIO, 0x1ce9, 2, &mmOTG3_OTG_VERTICAL_INTERRUPT2_POSITION[0], sizeof(mmOTG3_OTG_VERTICAL_INTERRUPT2_POSITION)/sizeof(mmOTG3_OTG_VERTICAL_INTERRUPT2_POSITION[0]), 0, 0 }, + { "mmOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL", REG_MMIO, 0x1cea, 2, &mmOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL[0], sizeof(mmOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL)/sizeof(mmOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL[0]), 0, 0 }, + { "mmOTG3_OTG_CRC_CNTL", REG_MMIO, 0x1ceb, 2, &mmOTG3_OTG_CRC_CNTL[0], sizeof(mmOTG3_OTG_CRC_CNTL)/sizeof(mmOTG3_OTG_CRC_CNTL[0]), 0, 0 }, + { "mmOTG3_OTG_CRC0_WINDOWA_X_CONTROL", REG_MMIO, 0x1cec, 2, &mmOTG3_OTG_CRC0_WINDOWA_X_CONTROL[0], sizeof(mmOTG3_OTG_CRC0_WINDOWA_X_CONTROL)/sizeof(mmOTG3_OTG_CRC0_WINDOWA_X_CONTROL[0]), 0, 0 }, + { "mmOTG3_OTG_CRC0_WINDOWA_Y_CONTROL", REG_MMIO, 0x1ced, 2, &mmOTG3_OTG_CRC0_WINDOWA_Y_CONTROL[0], sizeof(mmOTG3_OTG_CRC0_WINDOWA_Y_CONTROL)/sizeof(mmOTG3_OTG_CRC0_WINDOWA_Y_CONTROL[0]), 0, 0 }, + { "mmOTG3_OTG_CRC0_WINDOWB_X_CONTROL", REG_MMIO, 0x1cee, 2, &mmOTG3_OTG_CRC0_WINDOWB_X_CONTROL[0], sizeof(mmOTG3_OTG_CRC0_WINDOWB_X_CONTROL)/sizeof(mmOTG3_OTG_CRC0_WINDOWB_X_CONTROL[0]), 0, 0 }, + { "mmOTG3_OTG_CRC0_WINDOWB_Y_CONTROL", REG_MMIO, 0x1cef, 2, &mmOTG3_OTG_CRC0_WINDOWB_Y_CONTROL[0], sizeof(mmOTG3_OTG_CRC0_WINDOWB_Y_CONTROL)/sizeof(mmOTG3_OTG_CRC0_WINDOWB_Y_CONTROL[0]), 0, 0 }, + { "mmOTG3_OTG_CRC0_DATA_RG", REG_MMIO, 0x1cf0, 2, &mmOTG3_OTG_CRC0_DATA_RG[0], sizeof(mmOTG3_OTG_CRC0_DATA_RG)/sizeof(mmOTG3_OTG_CRC0_DATA_RG[0]), 0, 0 }, + { "mmOTG3_OTG_CRC0_DATA_B", REG_MMIO, 0x1cf1, 2, &mmOTG3_OTG_CRC0_DATA_B[0], sizeof(mmOTG3_OTG_CRC0_DATA_B)/sizeof(mmOTG3_OTG_CRC0_DATA_B[0]), 0, 0 }, + { "mmOTG3_OTG_CRC1_WINDOWA_X_CONTROL", REG_MMIO, 0x1cf2, 2, &mmOTG3_OTG_CRC1_WINDOWA_X_CONTROL[0], sizeof(mmOTG3_OTG_CRC1_WINDOWA_X_CONTROL)/sizeof(mmOTG3_OTG_CRC1_WINDOWA_X_CONTROL[0]), 0, 0 }, + { "mmOTG3_OTG_CRC1_WINDOWA_Y_CONTROL", REG_MMIO, 0x1cf3, 2, &mmOTG3_OTG_CRC1_WINDOWA_Y_CONTROL[0], sizeof(mmOTG3_OTG_CRC1_WINDOWA_Y_CONTROL)/sizeof(mmOTG3_OTG_CRC1_WINDOWA_Y_CONTROL[0]), 0, 0 }, + { "mmOTG3_OTG_CRC1_WINDOWB_X_CONTROL", REG_MMIO, 0x1cf4, 2, &mmOTG3_OTG_CRC1_WINDOWB_X_CONTROL[0], sizeof(mmOTG3_OTG_CRC1_WINDOWB_X_CONTROL)/sizeof(mmOTG3_OTG_CRC1_WINDOWB_X_CONTROL[0]), 0, 0 }, + { "mmOTG3_OTG_CRC1_WINDOWB_Y_CONTROL", REG_MMIO, 0x1cf5, 2, &mmOTG3_OTG_CRC1_WINDOWB_Y_CONTROL[0], sizeof(mmOTG3_OTG_CRC1_WINDOWB_Y_CONTROL)/sizeof(mmOTG3_OTG_CRC1_WINDOWB_Y_CONTROL[0]), 0, 0 }, + { "mmOTG3_OTG_CRC1_DATA_RG", REG_MMIO, 0x1cf6, 2, &mmOTG3_OTG_CRC1_DATA_RG[0], sizeof(mmOTG3_OTG_CRC1_DATA_RG)/sizeof(mmOTG3_OTG_CRC1_DATA_RG[0]), 0, 0 }, + { "mmOTG3_OTG_CRC1_DATA_B", REG_MMIO, 0x1cf7, 2, &mmOTG3_OTG_CRC1_DATA_B[0], sizeof(mmOTG3_OTG_CRC1_DATA_B)/sizeof(mmOTG3_OTG_CRC1_DATA_B[0]), 0, 0 }, + { "mmOTG3_OTG_CRC2_DATA_RG", REG_MMIO, 0x1cf8, 2, &mmOTG3_OTG_CRC2_DATA_RG[0], sizeof(mmOTG3_OTG_CRC2_DATA_RG)/sizeof(mmOTG3_OTG_CRC2_DATA_RG[0]), 0, 0 }, + { "mmOTG3_OTG_CRC2_DATA_B", REG_MMIO, 0x1cf9, 2, &mmOTG3_OTG_CRC2_DATA_B[0], sizeof(mmOTG3_OTG_CRC2_DATA_B)/sizeof(mmOTG3_OTG_CRC2_DATA_B[0]), 0, 0 }, + { "mmOTG3_OTG_CRC3_DATA_RG", REG_MMIO, 0x1cfa, 2, &mmOTG3_OTG_CRC3_DATA_RG[0], sizeof(mmOTG3_OTG_CRC3_DATA_RG)/sizeof(mmOTG3_OTG_CRC3_DATA_RG[0]), 0, 0 }, + { "mmOTG3_OTG_CRC3_DATA_B", REG_MMIO, 0x1cfb, 2, &mmOTG3_OTG_CRC3_DATA_B[0], sizeof(mmOTG3_OTG_CRC3_DATA_B)/sizeof(mmOTG3_OTG_CRC3_DATA_B[0]), 0, 0 }, + { "mmOTG3_OTG_CRC_SIG_RED_GREEN_MASK", REG_MMIO, 0x1cfc, 2, &mmOTG3_OTG_CRC_SIG_RED_GREEN_MASK[0], sizeof(mmOTG3_OTG_CRC_SIG_RED_GREEN_MASK)/sizeof(mmOTG3_OTG_CRC_SIG_RED_GREEN_MASK[0]), 0, 0 }, + { "mmOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK", REG_MMIO, 0x1cfd, 2, &mmOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK[0], sizeof(mmOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK)/sizeof(mmOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK[0]), 0, 0 }, + { "mmOTG3_OTG_STATIC_SCREEN_CONTROL", REG_MMIO, 0x1d04, 2, &mmOTG3_OTG_STATIC_SCREEN_CONTROL[0], sizeof(mmOTG3_OTG_STATIC_SCREEN_CONTROL)/sizeof(mmOTG3_OTG_STATIC_SCREEN_CONTROL[0]), 0, 0 }, + { "mmOTG3_OTG_3D_STRUCTURE_CONTROL", REG_MMIO, 0x1d05, 2, &mmOTG3_OTG_3D_STRUCTURE_CONTROL[0], sizeof(mmOTG3_OTG_3D_STRUCTURE_CONTROL)/sizeof(mmOTG3_OTG_3D_STRUCTURE_CONTROL[0]), 0, 0 }, + { "mmOTG3_OTG_GSL_VSYNC_GAP", REG_MMIO, 0x1d06, 2, &mmOTG3_OTG_GSL_VSYNC_GAP[0], sizeof(mmOTG3_OTG_GSL_VSYNC_GAP)/sizeof(mmOTG3_OTG_GSL_VSYNC_GAP[0]), 0, 0 }, + { "mmOTG3_OTG_MASTER_UPDATE_MODE", REG_MMIO, 0x1d07, 2, &mmOTG3_OTG_MASTER_UPDATE_MODE[0], sizeof(mmOTG3_OTG_MASTER_UPDATE_MODE)/sizeof(mmOTG3_OTG_MASTER_UPDATE_MODE[0]), 0, 0 }, + { "mmOTG3_OTG_CLOCK_CONTROL", REG_MMIO, 0x1d08, 2, &mmOTG3_OTG_CLOCK_CONTROL[0], sizeof(mmOTG3_OTG_CLOCK_CONTROL)/sizeof(mmOTG3_OTG_CLOCK_CONTROL[0]), 0, 0 }, + { "mmOTG3_OTG_VSTARTUP_PARAM", REG_MMIO, 0x1d09, 2, &mmOTG3_OTG_VSTARTUP_PARAM[0], sizeof(mmOTG3_OTG_VSTARTUP_PARAM)/sizeof(mmOTG3_OTG_VSTARTUP_PARAM[0]), 0, 0 }, + { "mmOTG3_OTG_VUPDATE_PARAM", REG_MMIO, 0x1d0a, 2, &mmOTG3_OTG_VUPDATE_PARAM[0], sizeof(mmOTG3_OTG_VUPDATE_PARAM)/sizeof(mmOTG3_OTG_VUPDATE_PARAM[0]), 0, 0 }, + { "mmOTG3_OTG_VREADY_PARAM", REG_MMIO, 0x1d0b, 2, &mmOTG3_OTG_VREADY_PARAM[0], sizeof(mmOTG3_OTG_VREADY_PARAM)/sizeof(mmOTG3_OTG_VREADY_PARAM[0]), 0, 0 }, + { "mmOTG3_OTG_GLOBAL_SYNC_STATUS", REG_MMIO, 0x1d0c, 2, &mmOTG3_OTG_GLOBAL_SYNC_STATUS[0], sizeof(mmOTG3_OTG_GLOBAL_SYNC_STATUS)/sizeof(mmOTG3_OTG_GLOBAL_SYNC_STATUS[0]), 0, 0 }, + { "mmOTG3_OTG_MASTER_UPDATE_LOCK", REG_MMIO, 0x1d0d, 2, &mmOTG3_OTG_MASTER_UPDATE_LOCK[0], sizeof(mmOTG3_OTG_MASTER_UPDATE_LOCK)/sizeof(mmOTG3_OTG_MASTER_UPDATE_LOCK[0]), 0, 0 }, + { "mmOTG3_OTG_GSL_CONTROL", REG_MMIO, 0x1d0e, 2, &mmOTG3_OTG_GSL_CONTROL[0], sizeof(mmOTG3_OTG_GSL_CONTROL)/sizeof(mmOTG3_OTG_GSL_CONTROL[0]), 0, 0 }, + { "mmOTG3_OTG_GSL_WINDOW_X", REG_MMIO, 0x1d0f, 2, &mmOTG3_OTG_GSL_WINDOW_X[0], sizeof(mmOTG3_OTG_GSL_WINDOW_X)/sizeof(mmOTG3_OTG_GSL_WINDOW_X[0]), 0, 0 }, + { "mmOTG3_OTG_GSL_WINDOW_Y", REG_MMIO, 0x1d10, 2, &mmOTG3_OTG_GSL_WINDOW_Y[0], sizeof(mmOTG3_OTG_GSL_WINDOW_Y)/sizeof(mmOTG3_OTG_GSL_WINDOW_Y[0]), 0, 0 }, + { "mmOTG3_OTG_VUPDATE_KEEPOUT", REG_MMIO, 0x1d11, 2, &mmOTG3_OTG_VUPDATE_KEEPOUT[0], sizeof(mmOTG3_OTG_VUPDATE_KEEPOUT)/sizeof(mmOTG3_OTG_VUPDATE_KEEPOUT[0]), 0, 0 }, + { "mmOTG3_OTG_GLOBAL_CONTROL0", REG_MMIO, 0x1d12, 2, &mmOTG3_OTG_GLOBAL_CONTROL0[0], sizeof(mmOTG3_OTG_GLOBAL_CONTROL0)/sizeof(mmOTG3_OTG_GLOBAL_CONTROL0[0]), 0, 0 }, + { "mmOTG3_OTG_GLOBAL_CONTROL1", REG_MMIO, 0x1d13, 2, &mmOTG3_OTG_GLOBAL_CONTROL1[0], sizeof(mmOTG3_OTG_GLOBAL_CONTROL1)/sizeof(mmOTG3_OTG_GLOBAL_CONTROL1[0]), 0, 0 }, + { "mmOTG3_OTG_GLOBAL_CONTROL2", REG_MMIO, 0x1d14, 2, &mmOTG3_OTG_GLOBAL_CONTROL2[0], sizeof(mmOTG3_OTG_GLOBAL_CONTROL2)/sizeof(mmOTG3_OTG_GLOBAL_CONTROL2[0]), 0, 0 }, + { "mmOTG3_OTG_GLOBAL_CONTROL3", REG_MMIO, 0x1d15, 2, &mmOTG3_OTG_GLOBAL_CONTROL3[0], sizeof(mmOTG3_OTG_GLOBAL_CONTROL3)/sizeof(mmOTG3_OTG_GLOBAL_CONTROL3[0]), 0, 0 }, + { "mmOTG3_OTG_TRIG_MANUAL_CONTROL", REG_MMIO, 0x1d16, 2, &mmOTG3_OTG_TRIG_MANUAL_CONTROL[0], sizeof(mmOTG3_OTG_TRIG_MANUAL_CONTROL)/sizeof(mmOTG3_OTG_TRIG_MANUAL_CONTROL[0]), 0, 0 }, + { "mmOTG3_OTG_MANUAL_FLOW_CONTROL", REG_MMIO, 0x1d17, 2, &mmOTG3_OTG_MANUAL_FLOW_CONTROL[0], sizeof(mmOTG3_OTG_MANUAL_FLOW_CONTROL)/sizeof(mmOTG3_OTG_MANUAL_FLOW_CONTROL[0]), 0, 0 }, + { "mmOTG3_OTG_RANGE_TIMING_INT_STATUS", REG_MMIO, 0x1d18, 2, &mmOTG3_OTG_RANGE_TIMING_INT_STATUS[0], sizeof(mmOTG3_OTG_RANGE_TIMING_INT_STATUS)/sizeof(mmOTG3_OTG_RANGE_TIMING_INT_STATUS[0]), 0, 0 }, + { "mmOTG3_OTG_DRR_CONTROL", REG_MMIO, 0x1d19, 2, &mmOTG3_OTG_DRR_CONTROL[0], sizeof(mmOTG3_OTG_DRR_CONTROL)/sizeof(mmOTG3_OTG_DRR_CONTROL[0]), 0, 0 }, + { "mmOTG3_OTG_REQUEST_CONTROL", REG_MMIO, 0x1d1a, 2, &mmOTG3_OTG_REQUEST_CONTROL[0], sizeof(mmOTG3_OTG_REQUEST_CONTROL)/sizeof(mmOTG3_OTG_REQUEST_CONTROL[0]), 0, 0 }, + { "mmOTG3_OTG_SPARE_REGISTER", REG_MMIO, 0x1d1b, 2, &mmOTG3_OTG_SPARE_REGISTER[0], sizeof(mmOTG3_OTG_SPARE_REGISTER)/sizeof(mmOTG3_OTG_SPARE_REGISTER[0]), 0, 0 }, + { "mmOTG4_OTG_H_TOTAL", REG_MMIO, 0x1d2a, 2, &mmOTG4_OTG_H_TOTAL[0], sizeof(mmOTG4_OTG_H_TOTAL)/sizeof(mmOTG4_OTG_H_TOTAL[0]), 0, 0 }, + { "mmOTG4_OTG_H_BLANK_START_END", REG_MMIO, 0x1d2b, 2, &mmOTG4_OTG_H_BLANK_START_END[0], sizeof(mmOTG4_OTG_H_BLANK_START_END)/sizeof(mmOTG4_OTG_H_BLANK_START_END[0]), 0, 0 }, + { "mmOTG4_OTG_H_SYNC_A", REG_MMIO, 0x1d2c, 2, &mmOTG4_OTG_H_SYNC_A[0], sizeof(mmOTG4_OTG_H_SYNC_A)/sizeof(mmOTG4_OTG_H_SYNC_A[0]), 0, 0 }, + { "mmOTG4_OTG_H_SYNC_A_CNTL", REG_MMIO, 0x1d2d, 2, &mmOTG4_OTG_H_SYNC_A_CNTL[0], sizeof(mmOTG4_OTG_H_SYNC_A_CNTL)/sizeof(mmOTG4_OTG_H_SYNC_A_CNTL[0]), 0, 0 }, + { "mmOTG4_OTG_H_TIMING_CNTL", REG_MMIO, 0x1d2e, 2, &mmOTG4_OTG_H_TIMING_CNTL[0], sizeof(mmOTG4_OTG_H_TIMING_CNTL)/sizeof(mmOTG4_OTG_H_TIMING_CNTL[0]), 0, 0 }, + { "mmOTG4_OTG_V_TOTAL", REG_MMIO, 0x1d2f, 2, &mmOTG4_OTG_V_TOTAL[0], sizeof(mmOTG4_OTG_V_TOTAL)/sizeof(mmOTG4_OTG_V_TOTAL[0]), 0, 0 }, + { "mmOTG4_OTG_V_TOTAL_MIN", REG_MMIO, 0x1d30, 2, &mmOTG4_OTG_V_TOTAL_MIN[0], sizeof(mmOTG4_OTG_V_TOTAL_MIN)/sizeof(mmOTG4_OTG_V_TOTAL_MIN[0]), 0, 0 }, + { "mmOTG4_OTG_V_TOTAL_MAX", REG_MMIO, 0x1d31, 2, &mmOTG4_OTG_V_TOTAL_MAX[0], sizeof(mmOTG4_OTG_V_TOTAL_MAX)/sizeof(mmOTG4_OTG_V_TOTAL_MAX[0]), 0, 0 }, + { "mmOTG4_OTG_V_TOTAL_MID", REG_MMIO, 0x1d32, 2, &mmOTG4_OTG_V_TOTAL_MID[0], sizeof(mmOTG4_OTG_V_TOTAL_MID)/sizeof(mmOTG4_OTG_V_TOTAL_MID[0]), 0, 0 }, + { "mmOTG4_OTG_V_TOTAL_CONTROL", REG_MMIO, 0x1d33, 2, &mmOTG4_OTG_V_TOTAL_CONTROL[0], sizeof(mmOTG4_OTG_V_TOTAL_CONTROL)/sizeof(mmOTG4_OTG_V_TOTAL_CONTROL[0]), 0, 0 }, + { "mmOTG4_OTG_V_TOTAL_INT_STATUS", REG_MMIO, 0x1d34, 2, &mmOTG4_OTG_V_TOTAL_INT_STATUS[0], sizeof(mmOTG4_OTG_V_TOTAL_INT_STATUS)/sizeof(mmOTG4_OTG_V_TOTAL_INT_STATUS[0]), 0, 0 }, + { "mmOTG4_OTG_VSYNC_NOM_INT_STATUS", REG_MMIO, 0x1d35, 2, &mmOTG4_OTG_VSYNC_NOM_INT_STATUS[0], sizeof(mmOTG4_OTG_VSYNC_NOM_INT_STATUS)/sizeof(mmOTG4_OTG_VSYNC_NOM_INT_STATUS[0]), 0, 0 }, + { "mmOTG4_OTG_V_BLANK_START_END", REG_MMIO, 0x1d36, 2, &mmOTG4_OTG_V_BLANK_START_END[0], sizeof(mmOTG4_OTG_V_BLANK_START_END)/sizeof(mmOTG4_OTG_V_BLANK_START_END[0]), 0, 0 }, + { "mmOTG4_OTG_V_SYNC_A", REG_MMIO, 0x1d37, 2, &mmOTG4_OTG_V_SYNC_A[0], sizeof(mmOTG4_OTG_V_SYNC_A)/sizeof(mmOTG4_OTG_V_SYNC_A[0]), 0, 0 }, + { "mmOTG4_OTG_V_SYNC_A_CNTL", REG_MMIO, 0x1d38, 2, &mmOTG4_OTG_V_SYNC_A_CNTL[0], sizeof(mmOTG4_OTG_V_SYNC_A_CNTL)/sizeof(mmOTG4_OTG_V_SYNC_A_CNTL[0]), 0, 0 }, + { "mmOTG4_OTG_TRIGA_CNTL", REG_MMIO, 0x1d39, 2, &mmOTG4_OTG_TRIGA_CNTL[0], sizeof(mmOTG4_OTG_TRIGA_CNTL)/sizeof(mmOTG4_OTG_TRIGA_CNTL[0]), 0, 0 }, + { "mmOTG4_OTG_TRIGA_MANUAL_TRIG", REG_MMIO, 0x1d3a, 2, &mmOTG4_OTG_TRIGA_MANUAL_TRIG[0], sizeof(mmOTG4_OTG_TRIGA_MANUAL_TRIG)/sizeof(mmOTG4_OTG_TRIGA_MANUAL_TRIG[0]), 0, 0 }, + { "mmOTG4_OTG_TRIGB_CNTL", REG_MMIO, 0x1d3b, 2, &mmOTG4_OTG_TRIGB_CNTL[0], sizeof(mmOTG4_OTG_TRIGB_CNTL)/sizeof(mmOTG4_OTG_TRIGB_CNTL[0]), 0, 0 }, + { "mmOTG4_OTG_TRIGB_MANUAL_TRIG", REG_MMIO, 0x1d3c, 2, &mmOTG4_OTG_TRIGB_MANUAL_TRIG[0], sizeof(mmOTG4_OTG_TRIGB_MANUAL_TRIG)/sizeof(mmOTG4_OTG_TRIGB_MANUAL_TRIG[0]), 0, 0 }, + { "mmOTG4_OTG_FORCE_COUNT_NOW_CNTL", REG_MMIO, 0x1d3d, 2, &mmOTG4_OTG_FORCE_COUNT_NOW_CNTL[0], sizeof(mmOTG4_OTG_FORCE_COUNT_NOW_CNTL)/sizeof(mmOTG4_OTG_FORCE_COUNT_NOW_CNTL[0]), 0, 0 }, + { "mmOTG4_OTG_FLOW_CONTROL", REG_MMIO, 0x1d3e, 2, &mmOTG4_OTG_FLOW_CONTROL[0], sizeof(mmOTG4_OTG_FLOW_CONTROL)/sizeof(mmOTG4_OTG_FLOW_CONTROL[0]), 0, 0 }, + { "mmOTG4_OTG_STEREO_FORCE_NEXT_EYE", REG_MMIO, 0x1d3f, 2, &mmOTG4_OTG_STEREO_FORCE_NEXT_EYE[0], sizeof(mmOTG4_OTG_STEREO_FORCE_NEXT_EYE)/sizeof(mmOTG4_OTG_STEREO_FORCE_NEXT_EYE[0]), 0, 0 }, + { "mmOTG4_OTG_AVSYNC_COUNTER", REG_MMIO, 0x1d40, 2, &mmOTG4_OTG_AVSYNC_COUNTER[0], sizeof(mmOTG4_OTG_AVSYNC_COUNTER)/sizeof(mmOTG4_OTG_AVSYNC_COUNTER[0]), 0, 0 }, + { "mmOTG4_OTG_CONTROL", REG_MMIO, 0x1d41, 2, &mmOTG4_OTG_CONTROL[0], sizeof(mmOTG4_OTG_CONTROL)/sizeof(mmOTG4_OTG_CONTROL[0]), 0, 0 }, + { "mmOTG4_OTG_BLANK_CONTROL", REG_MMIO, 0x1d42, 2, &mmOTG4_OTG_BLANK_CONTROL[0], sizeof(mmOTG4_OTG_BLANK_CONTROL)/sizeof(mmOTG4_OTG_BLANK_CONTROL[0]), 0, 0 }, + { "mmOTG4_OTG_PIPE_ABORT_CONTROL", REG_MMIO, 0x1d43, 2, &mmOTG4_OTG_PIPE_ABORT_CONTROL[0], sizeof(mmOTG4_OTG_PIPE_ABORT_CONTROL)/sizeof(mmOTG4_OTG_PIPE_ABORT_CONTROL[0]), 0, 0 }, + { "mmOTG4_OTG_INTERLACE_CONTROL", REG_MMIO, 0x1d44, 2, &mmOTG4_OTG_INTERLACE_CONTROL[0], sizeof(mmOTG4_OTG_INTERLACE_CONTROL)/sizeof(mmOTG4_OTG_INTERLACE_CONTROL[0]), 0, 0 }, + { "mmOTG4_OTG_INTERLACE_STATUS", REG_MMIO, 0x1d45, 2, &mmOTG4_OTG_INTERLACE_STATUS[0], sizeof(mmOTG4_OTG_INTERLACE_STATUS)/sizeof(mmOTG4_OTG_INTERLACE_STATUS[0]), 0, 0 }, + { "mmOTG4_OTG_FIELD_INDICATION_CONTROL", REG_MMIO, 0x1d46, 2, &mmOTG4_OTG_FIELD_INDICATION_CONTROL[0], sizeof(mmOTG4_OTG_FIELD_INDICATION_CONTROL)/sizeof(mmOTG4_OTG_FIELD_INDICATION_CONTROL[0]), 0, 0 }, + { "mmOTG4_OTG_PIXEL_DATA_READBACK0", REG_MMIO, 0x1d47, 2, &mmOTG4_OTG_PIXEL_DATA_READBACK0[0], sizeof(mmOTG4_OTG_PIXEL_DATA_READBACK0)/sizeof(mmOTG4_OTG_PIXEL_DATA_READBACK0[0]), 0, 0 }, + { "mmOTG4_OTG_PIXEL_DATA_READBACK1", REG_MMIO, 0x1d48, 2, &mmOTG4_OTG_PIXEL_DATA_READBACK1[0], sizeof(mmOTG4_OTG_PIXEL_DATA_READBACK1)/sizeof(mmOTG4_OTG_PIXEL_DATA_READBACK1[0]), 0, 0 }, + { "mmOTG4_OTG_STATUS", REG_MMIO, 0x1d49, 2, &mmOTG4_OTG_STATUS[0], sizeof(mmOTG4_OTG_STATUS)/sizeof(mmOTG4_OTG_STATUS[0]), 0, 0 }, + { "mmOTG4_OTG_STATUS_POSITION", REG_MMIO, 0x1d4a, 2, &mmOTG4_OTG_STATUS_POSITION[0], sizeof(mmOTG4_OTG_STATUS_POSITION)/sizeof(mmOTG4_OTG_STATUS_POSITION[0]), 0, 0 }, + { "mmOTG4_OTG_NOM_VERT_POSITION", REG_MMIO, 0x1d4b, 2, &mmOTG4_OTG_NOM_VERT_POSITION[0], sizeof(mmOTG4_OTG_NOM_VERT_POSITION)/sizeof(mmOTG4_OTG_NOM_VERT_POSITION[0]), 0, 0 }, + { "mmOTG4_OTG_STATUS_FRAME_COUNT", REG_MMIO, 0x1d4c, 2, &mmOTG4_OTG_STATUS_FRAME_COUNT[0], sizeof(mmOTG4_OTG_STATUS_FRAME_COUNT)/sizeof(mmOTG4_OTG_STATUS_FRAME_COUNT[0]), 0, 0 }, + { "mmOTG4_OTG_STATUS_VF_COUNT", REG_MMIO, 0x1d4d, 2, &mmOTG4_OTG_STATUS_VF_COUNT[0], sizeof(mmOTG4_OTG_STATUS_VF_COUNT)/sizeof(mmOTG4_OTG_STATUS_VF_COUNT[0]), 0, 0 }, + { "mmOTG4_OTG_STATUS_HV_COUNT", REG_MMIO, 0x1d4e, 2, &mmOTG4_OTG_STATUS_HV_COUNT[0], sizeof(mmOTG4_OTG_STATUS_HV_COUNT)/sizeof(mmOTG4_OTG_STATUS_HV_COUNT[0]), 0, 0 }, + { "mmOTG4_OTG_COUNT_CONTROL", REG_MMIO, 0x1d4f, 2, &mmOTG4_OTG_COUNT_CONTROL[0], sizeof(mmOTG4_OTG_COUNT_CONTROL)/sizeof(mmOTG4_OTG_COUNT_CONTROL[0]), 0, 0 }, + { "mmOTG4_OTG_COUNT_RESET", REG_MMIO, 0x1d50, 2, &mmOTG4_OTG_COUNT_RESET[0], sizeof(mmOTG4_OTG_COUNT_RESET)/sizeof(mmOTG4_OTG_COUNT_RESET[0]), 0, 0 }, + { "mmOTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE", REG_MMIO, 0x1d51, 2, &mmOTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE[0], sizeof(mmOTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE)/sizeof(mmOTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE[0]), 0, 0 }, + { "mmOTG4_OTG_VERT_SYNC_CONTROL", REG_MMIO, 0x1d52, 2, &mmOTG4_OTG_VERT_SYNC_CONTROL[0], sizeof(mmOTG4_OTG_VERT_SYNC_CONTROL)/sizeof(mmOTG4_OTG_VERT_SYNC_CONTROL[0]), 0, 0 }, + { "mmOTG4_OTG_STEREO_STATUS", REG_MMIO, 0x1d53, 2, &mmOTG4_OTG_STEREO_STATUS[0], sizeof(mmOTG4_OTG_STEREO_STATUS)/sizeof(mmOTG4_OTG_STEREO_STATUS[0]), 0, 0 }, + { "mmOTG4_OTG_STEREO_CONTROL", REG_MMIO, 0x1d54, 2, &mmOTG4_OTG_STEREO_CONTROL[0], sizeof(mmOTG4_OTG_STEREO_CONTROL)/sizeof(mmOTG4_OTG_STEREO_CONTROL[0]), 0, 0 }, + { "mmOTG4_OTG_SNAPSHOT_STATUS", REG_MMIO, 0x1d55, 2, &mmOTG4_OTG_SNAPSHOT_STATUS[0], sizeof(mmOTG4_OTG_SNAPSHOT_STATUS)/sizeof(mmOTG4_OTG_SNAPSHOT_STATUS[0]), 0, 0 }, + { "mmOTG4_OTG_SNAPSHOT_CONTROL", REG_MMIO, 0x1d56, 2, &mmOTG4_OTG_SNAPSHOT_CONTROL[0], sizeof(mmOTG4_OTG_SNAPSHOT_CONTROL)/sizeof(mmOTG4_OTG_SNAPSHOT_CONTROL[0]), 0, 0 }, + { "mmOTG4_OTG_SNAPSHOT_POSITION", REG_MMIO, 0x1d57, 2, &mmOTG4_OTG_SNAPSHOT_POSITION[0], sizeof(mmOTG4_OTG_SNAPSHOT_POSITION)/sizeof(mmOTG4_OTG_SNAPSHOT_POSITION[0]), 0, 0 }, + { "mmOTG4_OTG_SNAPSHOT_FRAME", REG_MMIO, 0x1d58, 2, &mmOTG4_OTG_SNAPSHOT_FRAME[0], sizeof(mmOTG4_OTG_SNAPSHOT_FRAME)/sizeof(mmOTG4_OTG_SNAPSHOT_FRAME[0]), 0, 0 }, + { "mmOTG4_OTG_INTERRUPT_CONTROL", REG_MMIO, 0x1d59, 2, &mmOTG4_OTG_INTERRUPT_CONTROL[0], sizeof(mmOTG4_OTG_INTERRUPT_CONTROL)/sizeof(mmOTG4_OTG_INTERRUPT_CONTROL[0]), 0, 0 }, + { "mmOTG4_OTG_UPDATE_LOCK", REG_MMIO, 0x1d5a, 2, &mmOTG4_OTG_UPDATE_LOCK[0], sizeof(mmOTG4_OTG_UPDATE_LOCK)/sizeof(mmOTG4_OTG_UPDATE_LOCK[0]), 0, 0 }, + { "mmOTG4_OTG_DOUBLE_BUFFER_CONTROL", REG_MMIO, 0x1d5b, 2, &mmOTG4_OTG_DOUBLE_BUFFER_CONTROL[0], sizeof(mmOTG4_OTG_DOUBLE_BUFFER_CONTROL)/sizeof(mmOTG4_OTG_DOUBLE_BUFFER_CONTROL[0]), 0, 0 }, + { "mmOTG4_OTG_TEST_PATTERN_CONTROL", REG_MMIO, 0x1d5c, 2, &mmOTG4_OTG_TEST_PATTERN_CONTROL[0], sizeof(mmOTG4_OTG_TEST_PATTERN_CONTROL)/sizeof(mmOTG4_OTG_TEST_PATTERN_CONTROL[0]), 0, 0 }, + { "mmOTG4_OTG_TEST_PATTERN_PARAMETERS", REG_MMIO, 0x1d5d, 2, &mmOTG4_OTG_TEST_PATTERN_PARAMETERS[0], sizeof(mmOTG4_OTG_TEST_PATTERN_PARAMETERS)/sizeof(mmOTG4_OTG_TEST_PATTERN_PARAMETERS[0]), 0, 0 }, + { "mmOTG4_OTG_TEST_PATTERN_COLOR", REG_MMIO, 0x1d5e, 2, &mmOTG4_OTG_TEST_PATTERN_COLOR[0], sizeof(mmOTG4_OTG_TEST_PATTERN_COLOR)/sizeof(mmOTG4_OTG_TEST_PATTERN_COLOR[0]), 0, 0 }, + { "mmOTG4_OTG_MASTER_EN", REG_MMIO, 0x1d5f, 2, &mmOTG4_OTG_MASTER_EN[0], sizeof(mmOTG4_OTG_MASTER_EN)/sizeof(mmOTG4_OTG_MASTER_EN[0]), 0, 0 }, + { "mmOTG4_OTG_BLANK_DATA_COLOR", REG_MMIO, 0x1d61, 2, &mmOTG4_OTG_BLANK_DATA_COLOR[0], sizeof(mmOTG4_OTG_BLANK_DATA_COLOR)/sizeof(mmOTG4_OTG_BLANK_DATA_COLOR[0]), 0, 0 }, + { "mmOTG4_OTG_BLANK_DATA_COLOR_EXT", REG_MMIO, 0x1d62, 2, &mmOTG4_OTG_BLANK_DATA_COLOR_EXT[0], sizeof(mmOTG4_OTG_BLANK_DATA_COLOR_EXT)/sizeof(mmOTG4_OTG_BLANK_DATA_COLOR_EXT[0]), 0, 0 }, + { "mmOTG4_OTG_BLACK_COLOR", REG_MMIO, 0x1d63, 2, &mmOTG4_OTG_BLACK_COLOR[0], sizeof(mmOTG4_OTG_BLACK_COLOR)/sizeof(mmOTG4_OTG_BLACK_COLOR[0]), 0, 0 }, + { "mmOTG4_OTG_BLACK_COLOR_EXT", REG_MMIO, 0x1d64, 2, &mmOTG4_OTG_BLACK_COLOR_EXT[0], sizeof(mmOTG4_OTG_BLACK_COLOR_EXT)/sizeof(mmOTG4_OTG_BLACK_COLOR_EXT[0]), 0, 0 }, + { "mmOTG4_OTG_VERTICAL_INTERRUPT0_POSITION", REG_MMIO, 0x1d65, 2, &mmOTG4_OTG_VERTICAL_INTERRUPT0_POSITION[0], sizeof(mmOTG4_OTG_VERTICAL_INTERRUPT0_POSITION)/sizeof(mmOTG4_OTG_VERTICAL_INTERRUPT0_POSITION[0]), 0, 0 }, + { "mmOTG4_OTG_VERTICAL_INTERRUPT0_CONTROL", REG_MMIO, 0x1d66, 2, &mmOTG4_OTG_VERTICAL_INTERRUPT0_CONTROL[0], sizeof(mmOTG4_OTG_VERTICAL_INTERRUPT0_CONTROL)/sizeof(mmOTG4_OTG_VERTICAL_INTERRUPT0_CONTROL[0]), 0, 0 }, + { "mmOTG4_OTG_VERTICAL_INTERRUPT1_POSITION", REG_MMIO, 0x1d67, 2, &mmOTG4_OTG_VERTICAL_INTERRUPT1_POSITION[0], sizeof(mmOTG4_OTG_VERTICAL_INTERRUPT1_POSITION)/sizeof(mmOTG4_OTG_VERTICAL_INTERRUPT1_POSITION[0]), 0, 0 }, + { "mmOTG4_OTG_VERTICAL_INTERRUPT1_CONTROL", REG_MMIO, 0x1d68, 2, &mmOTG4_OTG_VERTICAL_INTERRUPT1_CONTROL[0], sizeof(mmOTG4_OTG_VERTICAL_INTERRUPT1_CONTROL)/sizeof(mmOTG4_OTG_VERTICAL_INTERRUPT1_CONTROL[0]), 0, 0 }, + { "mmOTG4_OTG_VERTICAL_INTERRUPT2_POSITION", REG_MMIO, 0x1d69, 2, &mmOTG4_OTG_VERTICAL_INTERRUPT2_POSITION[0], sizeof(mmOTG4_OTG_VERTICAL_INTERRUPT2_POSITION)/sizeof(mmOTG4_OTG_VERTICAL_INTERRUPT2_POSITION[0]), 0, 0 }, + { "mmOTG4_OTG_VERTICAL_INTERRUPT2_CONTROL", REG_MMIO, 0x1d6a, 2, &mmOTG4_OTG_VERTICAL_INTERRUPT2_CONTROL[0], sizeof(mmOTG4_OTG_VERTICAL_INTERRUPT2_CONTROL)/sizeof(mmOTG4_OTG_VERTICAL_INTERRUPT2_CONTROL[0]), 0, 0 }, + { "mmOTG4_OTG_CRC_CNTL", REG_MMIO, 0x1d6b, 2, &mmOTG4_OTG_CRC_CNTL[0], sizeof(mmOTG4_OTG_CRC_CNTL)/sizeof(mmOTG4_OTG_CRC_CNTL[0]), 0, 0 }, + { "mmOTG4_OTG_CRC0_WINDOWA_X_CONTROL", REG_MMIO, 0x1d6c, 2, &mmOTG4_OTG_CRC0_WINDOWA_X_CONTROL[0], sizeof(mmOTG4_OTG_CRC0_WINDOWA_X_CONTROL)/sizeof(mmOTG4_OTG_CRC0_WINDOWA_X_CONTROL[0]), 0, 0 }, + { "mmOTG4_OTG_CRC0_WINDOWA_Y_CONTROL", REG_MMIO, 0x1d6d, 2, &mmOTG4_OTG_CRC0_WINDOWA_Y_CONTROL[0], sizeof(mmOTG4_OTG_CRC0_WINDOWA_Y_CONTROL)/sizeof(mmOTG4_OTG_CRC0_WINDOWA_Y_CONTROL[0]), 0, 0 }, + { "mmOTG4_OTG_CRC0_WINDOWB_X_CONTROL", REG_MMIO, 0x1d6e, 2, &mmOTG4_OTG_CRC0_WINDOWB_X_CONTROL[0], sizeof(mmOTG4_OTG_CRC0_WINDOWB_X_CONTROL)/sizeof(mmOTG4_OTG_CRC0_WINDOWB_X_CONTROL[0]), 0, 0 }, + { "mmOTG4_OTG_CRC0_WINDOWB_Y_CONTROL", REG_MMIO, 0x1d6f, 2, &mmOTG4_OTG_CRC0_WINDOWB_Y_CONTROL[0], sizeof(mmOTG4_OTG_CRC0_WINDOWB_Y_CONTROL)/sizeof(mmOTG4_OTG_CRC0_WINDOWB_Y_CONTROL[0]), 0, 0 }, + { "mmOTG4_OTG_CRC0_DATA_RG", REG_MMIO, 0x1d70, 2, &mmOTG4_OTG_CRC0_DATA_RG[0], sizeof(mmOTG4_OTG_CRC0_DATA_RG)/sizeof(mmOTG4_OTG_CRC0_DATA_RG[0]), 0, 0 }, + { "mmOTG4_OTG_CRC0_DATA_B", REG_MMIO, 0x1d71, 2, &mmOTG4_OTG_CRC0_DATA_B[0], sizeof(mmOTG4_OTG_CRC0_DATA_B)/sizeof(mmOTG4_OTG_CRC0_DATA_B[0]), 0, 0 }, + { "mmOTG4_OTG_CRC1_WINDOWA_X_CONTROL", REG_MMIO, 0x1d72, 2, &mmOTG4_OTG_CRC1_WINDOWA_X_CONTROL[0], sizeof(mmOTG4_OTG_CRC1_WINDOWA_X_CONTROL)/sizeof(mmOTG4_OTG_CRC1_WINDOWA_X_CONTROL[0]), 0, 0 }, + { "mmOTG4_OTG_CRC1_WINDOWA_Y_CONTROL", REG_MMIO, 0x1d73, 2, &mmOTG4_OTG_CRC1_WINDOWA_Y_CONTROL[0], sizeof(mmOTG4_OTG_CRC1_WINDOWA_Y_CONTROL)/sizeof(mmOTG4_OTG_CRC1_WINDOWA_Y_CONTROL[0]), 0, 0 }, + { "mmOTG4_OTG_CRC1_WINDOWB_X_CONTROL", REG_MMIO, 0x1d74, 2, &mmOTG4_OTG_CRC1_WINDOWB_X_CONTROL[0], sizeof(mmOTG4_OTG_CRC1_WINDOWB_X_CONTROL)/sizeof(mmOTG4_OTG_CRC1_WINDOWB_X_CONTROL[0]), 0, 0 }, + { "mmOTG4_OTG_CRC1_WINDOWB_Y_CONTROL", REG_MMIO, 0x1d75, 2, &mmOTG4_OTG_CRC1_WINDOWB_Y_CONTROL[0], sizeof(mmOTG4_OTG_CRC1_WINDOWB_Y_CONTROL)/sizeof(mmOTG4_OTG_CRC1_WINDOWB_Y_CONTROL[0]), 0, 0 }, + { "mmOTG4_OTG_CRC1_DATA_RG", REG_MMIO, 0x1d76, 2, &mmOTG4_OTG_CRC1_DATA_RG[0], sizeof(mmOTG4_OTG_CRC1_DATA_RG)/sizeof(mmOTG4_OTG_CRC1_DATA_RG[0]), 0, 0 }, + { "mmOTG4_OTG_CRC1_DATA_B", REG_MMIO, 0x1d77, 2, &mmOTG4_OTG_CRC1_DATA_B[0], sizeof(mmOTG4_OTG_CRC1_DATA_B)/sizeof(mmOTG4_OTG_CRC1_DATA_B[0]), 0, 0 }, + { "mmOTG4_OTG_CRC2_DATA_RG", REG_MMIO, 0x1d78, 2, &mmOTG4_OTG_CRC2_DATA_RG[0], sizeof(mmOTG4_OTG_CRC2_DATA_RG)/sizeof(mmOTG4_OTG_CRC2_DATA_RG[0]), 0, 0 }, + { "mmOTG4_OTG_CRC2_DATA_B", REG_MMIO, 0x1d79, 2, &mmOTG4_OTG_CRC2_DATA_B[0], sizeof(mmOTG4_OTG_CRC2_DATA_B)/sizeof(mmOTG4_OTG_CRC2_DATA_B[0]), 0, 0 }, + { "mmOTG4_OTG_CRC3_DATA_RG", REG_MMIO, 0x1d7a, 2, &mmOTG4_OTG_CRC3_DATA_RG[0], sizeof(mmOTG4_OTG_CRC3_DATA_RG)/sizeof(mmOTG4_OTG_CRC3_DATA_RG[0]), 0, 0 }, + { "mmOTG4_OTG_CRC3_DATA_B", REG_MMIO, 0x1d7b, 2, &mmOTG4_OTG_CRC3_DATA_B[0], sizeof(mmOTG4_OTG_CRC3_DATA_B)/sizeof(mmOTG4_OTG_CRC3_DATA_B[0]), 0, 0 }, + { "mmOTG4_OTG_CRC_SIG_RED_GREEN_MASK", REG_MMIO, 0x1d7c, 2, &mmOTG4_OTG_CRC_SIG_RED_GREEN_MASK[0], sizeof(mmOTG4_OTG_CRC_SIG_RED_GREEN_MASK)/sizeof(mmOTG4_OTG_CRC_SIG_RED_GREEN_MASK[0]), 0, 0 }, + { "mmOTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK", REG_MMIO, 0x1d7d, 2, &mmOTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK[0], sizeof(mmOTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK)/sizeof(mmOTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK[0]), 0, 0 }, + { "mmOTG4_OTG_STATIC_SCREEN_CONTROL", REG_MMIO, 0x1d84, 2, &mmOTG4_OTG_STATIC_SCREEN_CONTROL[0], sizeof(mmOTG4_OTG_STATIC_SCREEN_CONTROL)/sizeof(mmOTG4_OTG_STATIC_SCREEN_CONTROL[0]), 0, 0 }, + { "mmOTG4_OTG_3D_STRUCTURE_CONTROL", REG_MMIO, 0x1d85, 2, &mmOTG4_OTG_3D_STRUCTURE_CONTROL[0], sizeof(mmOTG4_OTG_3D_STRUCTURE_CONTROL)/sizeof(mmOTG4_OTG_3D_STRUCTURE_CONTROL[0]), 0, 0 }, + { "mmOTG4_OTG_GSL_VSYNC_GAP", REG_MMIO, 0x1d86, 2, &mmOTG4_OTG_GSL_VSYNC_GAP[0], sizeof(mmOTG4_OTG_GSL_VSYNC_GAP)/sizeof(mmOTG4_OTG_GSL_VSYNC_GAP[0]), 0, 0 }, + { "mmOTG4_OTG_MASTER_UPDATE_MODE", REG_MMIO, 0x1d87, 2, &mmOTG4_OTG_MASTER_UPDATE_MODE[0], sizeof(mmOTG4_OTG_MASTER_UPDATE_MODE)/sizeof(mmOTG4_OTG_MASTER_UPDATE_MODE[0]), 0, 0 }, + { "mmOTG4_OTG_CLOCK_CONTROL", REG_MMIO, 0x1d88, 2, &mmOTG4_OTG_CLOCK_CONTROL[0], sizeof(mmOTG4_OTG_CLOCK_CONTROL)/sizeof(mmOTG4_OTG_CLOCK_CONTROL[0]), 0, 0 }, + { "mmOTG4_OTG_VSTARTUP_PARAM", REG_MMIO, 0x1d89, 2, &mmOTG4_OTG_VSTARTUP_PARAM[0], sizeof(mmOTG4_OTG_VSTARTUP_PARAM)/sizeof(mmOTG4_OTG_VSTARTUP_PARAM[0]), 0, 0 }, + { "mmOTG4_OTG_VUPDATE_PARAM", REG_MMIO, 0x1d8a, 2, &mmOTG4_OTG_VUPDATE_PARAM[0], sizeof(mmOTG4_OTG_VUPDATE_PARAM)/sizeof(mmOTG4_OTG_VUPDATE_PARAM[0]), 0, 0 }, + { "mmOTG4_OTG_VREADY_PARAM", REG_MMIO, 0x1d8b, 2, &mmOTG4_OTG_VREADY_PARAM[0], sizeof(mmOTG4_OTG_VREADY_PARAM)/sizeof(mmOTG4_OTG_VREADY_PARAM[0]), 0, 0 }, + { "mmOTG4_OTG_GLOBAL_SYNC_STATUS", REG_MMIO, 0x1d8c, 2, &mmOTG4_OTG_GLOBAL_SYNC_STATUS[0], sizeof(mmOTG4_OTG_GLOBAL_SYNC_STATUS)/sizeof(mmOTG4_OTG_GLOBAL_SYNC_STATUS[0]), 0, 0 }, + { "mmOTG4_OTG_MASTER_UPDATE_LOCK", REG_MMIO, 0x1d8d, 2, &mmOTG4_OTG_MASTER_UPDATE_LOCK[0], sizeof(mmOTG4_OTG_MASTER_UPDATE_LOCK)/sizeof(mmOTG4_OTG_MASTER_UPDATE_LOCK[0]), 0, 0 }, + { "mmOTG4_OTG_GSL_CONTROL", REG_MMIO, 0x1d8e, 2, &mmOTG4_OTG_GSL_CONTROL[0], sizeof(mmOTG4_OTG_GSL_CONTROL)/sizeof(mmOTG4_OTG_GSL_CONTROL[0]), 0, 0 }, + { "mmOTG4_OTG_GSL_WINDOW_X", REG_MMIO, 0x1d8f, 2, &mmOTG4_OTG_GSL_WINDOW_X[0], sizeof(mmOTG4_OTG_GSL_WINDOW_X)/sizeof(mmOTG4_OTG_GSL_WINDOW_X[0]), 0, 0 }, + { "mmOTG4_OTG_GSL_WINDOW_Y", REG_MMIO, 0x1d90, 2, &mmOTG4_OTG_GSL_WINDOW_Y[0], sizeof(mmOTG4_OTG_GSL_WINDOW_Y)/sizeof(mmOTG4_OTG_GSL_WINDOW_Y[0]), 0, 0 }, + { "mmOTG4_OTG_VUPDATE_KEEPOUT", REG_MMIO, 0x1d91, 2, &mmOTG4_OTG_VUPDATE_KEEPOUT[0], sizeof(mmOTG4_OTG_VUPDATE_KEEPOUT)/sizeof(mmOTG4_OTG_VUPDATE_KEEPOUT[0]), 0, 0 }, + { "mmOTG4_OTG_GLOBAL_CONTROL0", REG_MMIO, 0x1d92, 2, &mmOTG4_OTG_GLOBAL_CONTROL0[0], sizeof(mmOTG4_OTG_GLOBAL_CONTROL0)/sizeof(mmOTG4_OTG_GLOBAL_CONTROL0[0]), 0, 0 }, + { "mmOTG4_OTG_GLOBAL_CONTROL1", REG_MMIO, 0x1d93, 2, &mmOTG4_OTG_GLOBAL_CONTROL1[0], sizeof(mmOTG4_OTG_GLOBAL_CONTROL1)/sizeof(mmOTG4_OTG_GLOBAL_CONTROL1[0]), 0, 0 }, + { "mmOTG4_OTG_GLOBAL_CONTROL2", REG_MMIO, 0x1d94, 2, &mmOTG4_OTG_GLOBAL_CONTROL2[0], sizeof(mmOTG4_OTG_GLOBAL_CONTROL2)/sizeof(mmOTG4_OTG_GLOBAL_CONTROL2[0]), 0, 0 }, + { "mmOTG4_OTG_GLOBAL_CONTROL3", REG_MMIO, 0x1d95, 2, &mmOTG4_OTG_GLOBAL_CONTROL3[0], sizeof(mmOTG4_OTG_GLOBAL_CONTROL3)/sizeof(mmOTG4_OTG_GLOBAL_CONTROL3[0]), 0, 0 }, + { "mmOTG4_OTG_TRIG_MANUAL_CONTROL", REG_MMIO, 0x1d96, 2, &mmOTG4_OTG_TRIG_MANUAL_CONTROL[0], sizeof(mmOTG4_OTG_TRIG_MANUAL_CONTROL)/sizeof(mmOTG4_OTG_TRIG_MANUAL_CONTROL[0]), 0, 0 }, + { "mmOTG4_OTG_MANUAL_FLOW_CONTROL", REG_MMIO, 0x1d97, 2, &mmOTG4_OTG_MANUAL_FLOW_CONTROL[0], sizeof(mmOTG4_OTG_MANUAL_FLOW_CONTROL)/sizeof(mmOTG4_OTG_MANUAL_FLOW_CONTROL[0]), 0, 0 }, + { "mmOTG4_OTG_RANGE_TIMING_INT_STATUS", REG_MMIO, 0x1d98, 2, &mmOTG4_OTG_RANGE_TIMING_INT_STATUS[0], sizeof(mmOTG4_OTG_RANGE_TIMING_INT_STATUS)/sizeof(mmOTG4_OTG_RANGE_TIMING_INT_STATUS[0]), 0, 0 }, + { "mmOTG4_OTG_DRR_CONTROL", REG_MMIO, 0x1d99, 2, &mmOTG4_OTG_DRR_CONTROL[0], sizeof(mmOTG4_OTG_DRR_CONTROL)/sizeof(mmOTG4_OTG_DRR_CONTROL[0]), 0, 0 }, + { "mmOTG4_OTG_REQUEST_CONTROL", REG_MMIO, 0x1d9a, 2, &mmOTG4_OTG_REQUEST_CONTROL[0], sizeof(mmOTG4_OTG_REQUEST_CONTROL)/sizeof(mmOTG4_OTG_REQUEST_CONTROL[0]), 0, 0 }, + { "mmOTG4_OTG_SPARE_REGISTER", REG_MMIO, 0x1d9b, 2, &mmOTG4_OTG_SPARE_REGISTER[0], sizeof(mmOTG4_OTG_SPARE_REGISTER)/sizeof(mmOTG4_OTG_SPARE_REGISTER[0]), 0, 0 }, + { "mmOTG5_OTG_H_TOTAL", REG_MMIO, 0x1daa, 2, &mmOTG5_OTG_H_TOTAL[0], sizeof(mmOTG5_OTG_H_TOTAL)/sizeof(mmOTG5_OTG_H_TOTAL[0]), 0, 0 }, + { "mmOTG5_OTG_H_BLANK_START_END", REG_MMIO, 0x1dab, 2, &mmOTG5_OTG_H_BLANK_START_END[0], sizeof(mmOTG5_OTG_H_BLANK_START_END)/sizeof(mmOTG5_OTG_H_BLANK_START_END[0]), 0, 0 }, + { "mmOTG5_OTG_H_SYNC_A", REG_MMIO, 0x1dac, 2, &mmOTG5_OTG_H_SYNC_A[0], sizeof(mmOTG5_OTG_H_SYNC_A)/sizeof(mmOTG5_OTG_H_SYNC_A[0]), 0, 0 }, + { "mmOTG5_OTG_H_SYNC_A_CNTL", REG_MMIO, 0x1dad, 2, &mmOTG5_OTG_H_SYNC_A_CNTL[0], sizeof(mmOTG5_OTG_H_SYNC_A_CNTL)/sizeof(mmOTG5_OTG_H_SYNC_A_CNTL[0]), 0, 0 }, + { "mmOTG5_OTG_H_TIMING_CNTL", REG_MMIO, 0x1dae, 2, &mmOTG5_OTG_H_TIMING_CNTL[0], sizeof(mmOTG5_OTG_H_TIMING_CNTL)/sizeof(mmOTG5_OTG_H_TIMING_CNTL[0]), 0, 0 }, + { "mmOTG5_OTG_V_TOTAL", REG_MMIO, 0x1daf, 2, &mmOTG5_OTG_V_TOTAL[0], sizeof(mmOTG5_OTG_V_TOTAL)/sizeof(mmOTG5_OTG_V_TOTAL[0]), 0, 0 }, + { "mmOTG5_OTG_V_TOTAL_MIN", REG_MMIO, 0x1db0, 2, &mmOTG5_OTG_V_TOTAL_MIN[0], sizeof(mmOTG5_OTG_V_TOTAL_MIN)/sizeof(mmOTG5_OTG_V_TOTAL_MIN[0]), 0, 0 }, + { "mmOTG5_OTG_V_TOTAL_MAX", REG_MMIO, 0x1db1, 2, &mmOTG5_OTG_V_TOTAL_MAX[0], sizeof(mmOTG5_OTG_V_TOTAL_MAX)/sizeof(mmOTG5_OTG_V_TOTAL_MAX[0]), 0, 0 }, + { "mmOTG5_OTG_V_TOTAL_MID", REG_MMIO, 0x1db2, 2, &mmOTG5_OTG_V_TOTAL_MID[0], sizeof(mmOTG5_OTG_V_TOTAL_MID)/sizeof(mmOTG5_OTG_V_TOTAL_MID[0]), 0, 0 }, + { "mmOTG5_OTG_V_TOTAL_CONTROL", REG_MMIO, 0x1db3, 2, &mmOTG5_OTG_V_TOTAL_CONTROL[0], sizeof(mmOTG5_OTG_V_TOTAL_CONTROL)/sizeof(mmOTG5_OTG_V_TOTAL_CONTROL[0]), 0, 0 }, + { "mmOTG5_OTG_V_TOTAL_INT_STATUS", REG_MMIO, 0x1db4, 2, &mmOTG5_OTG_V_TOTAL_INT_STATUS[0], sizeof(mmOTG5_OTG_V_TOTAL_INT_STATUS)/sizeof(mmOTG5_OTG_V_TOTAL_INT_STATUS[0]), 0, 0 }, + { "mmOTG5_OTG_VSYNC_NOM_INT_STATUS", REG_MMIO, 0x1db5, 2, &mmOTG5_OTG_VSYNC_NOM_INT_STATUS[0], sizeof(mmOTG5_OTG_VSYNC_NOM_INT_STATUS)/sizeof(mmOTG5_OTG_VSYNC_NOM_INT_STATUS[0]), 0, 0 }, + { "mmOTG5_OTG_V_BLANK_START_END", REG_MMIO, 0x1db6, 2, &mmOTG5_OTG_V_BLANK_START_END[0], sizeof(mmOTG5_OTG_V_BLANK_START_END)/sizeof(mmOTG5_OTG_V_BLANK_START_END[0]), 0, 0 }, + { "mmOTG5_OTG_V_SYNC_A", REG_MMIO, 0x1db7, 2, &mmOTG5_OTG_V_SYNC_A[0], sizeof(mmOTG5_OTG_V_SYNC_A)/sizeof(mmOTG5_OTG_V_SYNC_A[0]), 0, 0 }, + { "mmOTG5_OTG_V_SYNC_A_CNTL", REG_MMIO, 0x1db8, 2, &mmOTG5_OTG_V_SYNC_A_CNTL[0], sizeof(mmOTG5_OTG_V_SYNC_A_CNTL)/sizeof(mmOTG5_OTG_V_SYNC_A_CNTL[0]), 0, 0 }, + { "mmOTG5_OTG_TRIGA_CNTL", REG_MMIO, 0x1db9, 2, &mmOTG5_OTG_TRIGA_CNTL[0], sizeof(mmOTG5_OTG_TRIGA_CNTL)/sizeof(mmOTG5_OTG_TRIGA_CNTL[0]), 0, 0 }, + { "mmOTG5_OTG_TRIGA_MANUAL_TRIG", REG_MMIO, 0x1dba, 2, &mmOTG5_OTG_TRIGA_MANUAL_TRIG[0], sizeof(mmOTG5_OTG_TRIGA_MANUAL_TRIG)/sizeof(mmOTG5_OTG_TRIGA_MANUAL_TRIG[0]), 0, 0 }, + { "mmOTG5_OTG_TRIGB_CNTL", REG_MMIO, 0x1dbb, 2, &mmOTG5_OTG_TRIGB_CNTL[0], sizeof(mmOTG5_OTG_TRIGB_CNTL)/sizeof(mmOTG5_OTG_TRIGB_CNTL[0]), 0, 0 }, + { "mmOTG5_OTG_TRIGB_MANUAL_TRIG", REG_MMIO, 0x1dbc, 2, &mmOTG5_OTG_TRIGB_MANUAL_TRIG[0], sizeof(mmOTG5_OTG_TRIGB_MANUAL_TRIG)/sizeof(mmOTG5_OTG_TRIGB_MANUAL_TRIG[0]), 0, 0 }, + { "mmOTG5_OTG_FORCE_COUNT_NOW_CNTL", REG_MMIO, 0x1dbd, 2, &mmOTG5_OTG_FORCE_COUNT_NOW_CNTL[0], sizeof(mmOTG5_OTG_FORCE_COUNT_NOW_CNTL)/sizeof(mmOTG5_OTG_FORCE_COUNT_NOW_CNTL[0]), 0, 0 }, + { "mmOTG5_OTG_FLOW_CONTROL", REG_MMIO, 0x1dbe, 2, &mmOTG5_OTG_FLOW_CONTROL[0], sizeof(mmOTG5_OTG_FLOW_CONTROL)/sizeof(mmOTG5_OTG_FLOW_CONTROL[0]), 0, 0 }, + { "mmOTG5_OTG_STEREO_FORCE_NEXT_EYE", REG_MMIO, 0x1dbf, 2, &mmOTG5_OTG_STEREO_FORCE_NEXT_EYE[0], sizeof(mmOTG5_OTG_STEREO_FORCE_NEXT_EYE)/sizeof(mmOTG5_OTG_STEREO_FORCE_NEXT_EYE[0]), 0, 0 }, + { "mmOTG5_OTG_AVSYNC_COUNTER", REG_MMIO, 0x1dc0, 2, &mmOTG5_OTG_AVSYNC_COUNTER[0], sizeof(mmOTG5_OTG_AVSYNC_COUNTER)/sizeof(mmOTG5_OTG_AVSYNC_COUNTER[0]), 0, 0 }, + { "mmOTG5_OTG_CONTROL", REG_MMIO, 0x1dc1, 2, &mmOTG5_OTG_CONTROL[0], sizeof(mmOTG5_OTG_CONTROL)/sizeof(mmOTG5_OTG_CONTROL[0]), 0, 0 }, + { "mmOTG5_OTG_BLANK_CONTROL", REG_MMIO, 0x1dc2, 2, &mmOTG5_OTG_BLANK_CONTROL[0], sizeof(mmOTG5_OTG_BLANK_CONTROL)/sizeof(mmOTG5_OTG_BLANK_CONTROL[0]), 0, 0 }, + { "mmOTG5_OTG_PIPE_ABORT_CONTROL", REG_MMIO, 0x1dc3, 2, &mmOTG5_OTG_PIPE_ABORT_CONTROL[0], sizeof(mmOTG5_OTG_PIPE_ABORT_CONTROL)/sizeof(mmOTG5_OTG_PIPE_ABORT_CONTROL[0]), 0, 0 }, + { "mmOTG5_OTG_INTERLACE_CONTROL", REG_MMIO, 0x1dc4, 2, &mmOTG5_OTG_INTERLACE_CONTROL[0], sizeof(mmOTG5_OTG_INTERLACE_CONTROL)/sizeof(mmOTG5_OTG_INTERLACE_CONTROL[0]), 0, 0 }, + { "mmOTG5_OTG_INTERLACE_STATUS", REG_MMIO, 0x1dc5, 2, &mmOTG5_OTG_INTERLACE_STATUS[0], sizeof(mmOTG5_OTG_INTERLACE_STATUS)/sizeof(mmOTG5_OTG_INTERLACE_STATUS[0]), 0, 0 }, + { "mmOTG5_OTG_FIELD_INDICATION_CONTROL", REG_MMIO, 0x1dc6, 2, &mmOTG5_OTG_FIELD_INDICATION_CONTROL[0], sizeof(mmOTG5_OTG_FIELD_INDICATION_CONTROL)/sizeof(mmOTG5_OTG_FIELD_INDICATION_CONTROL[0]), 0, 0 }, + { "mmOTG5_OTG_PIXEL_DATA_READBACK0", REG_MMIO, 0x1dc7, 2, &mmOTG5_OTG_PIXEL_DATA_READBACK0[0], sizeof(mmOTG5_OTG_PIXEL_DATA_READBACK0)/sizeof(mmOTG5_OTG_PIXEL_DATA_READBACK0[0]), 0, 0 }, + { "mmOTG5_OTG_PIXEL_DATA_READBACK1", REG_MMIO, 0x1dc8, 2, &mmOTG5_OTG_PIXEL_DATA_READBACK1[0], sizeof(mmOTG5_OTG_PIXEL_DATA_READBACK1)/sizeof(mmOTG5_OTG_PIXEL_DATA_READBACK1[0]), 0, 0 }, + { "mmOTG5_OTG_STATUS", REG_MMIO, 0x1dc9, 2, &mmOTG5_OTG_STATUS[0], sizeof(mmOTG5_OTG_STATUS)/sizeof(mmOTG5_OTG_STATUS[0]), 0, 0 }, + { "mmOTG5_OTG_STATUS_POSITION", REG_MMIO, 0x1dca, 2, &mmOTG5_OTG_STATUS_POSITION[0], sizeof(mmOTG5_OTG_STATUS_POSITION)/sizeof(mmOTG5_OTG_STATUS_POSITION[0]), 0, 0 }, + { "mmOTG5_OTG_NOM_VERT_POSITION", REG_MMIO, 0x1dcb, 2, &mmOTG5_OTG_NOM_VERT_POSITION[0], sizeof(mmOTG5_OTG_NOM_VERT_POSITION)/sizeof(mmOTG5_OTG_NOM_VERT_POSITION[0]), 0, 0 }, + { "mmOTG5_OTG_STATUS_FRAME_COUNT", REG_MMIO, 0x1dcc, 2, &mmOTG5_OTG_STATUS_FRAME_COUNT[0], sizeof(mmOTG5_OTG_STATUS_FRAME_COUNT)/sizeof(mmOTG5_OTG_STATUS_FRAME_COUNT[0]), 0, 0 }, + { "mmOTG5_OTG_STATUS_VF_COUNT", REG_MMIO, 0x1dcd, 2, &mmOTG5_OTG_STATUS_VF_COUNT[0], sizeof(mmOTG5_OTG_STATUS_VF_COUNT)/sizeof(mmOTG5_OTG_STATUS_VF_COUNT[0]), 0, 0 }, + { "mmOTG5_OTG_STATUS_HV_COUNT", REG_MMIO, 0x1dce, 2, &mmOTG5_OTG_STATUS_HV_COUNT[0], sizeof(mmOTG5_OTG_STATUS_HV_COUNT)/sizeof(mmOTG5_OTG_STATUS_HV_COUNT[0]), 0, 0 }, + { "mmOTG5_OTG_COUNT_CONTROL", REG_MMIO, 0x1dcf, 2, &mmOTG5_OTG_COUNT_CONTROL[0], sizeof(mmOTG5_OTG_COUNT_CONTROL)/sizeof(mmOTG5_OTG_COUNT_CONTROL[0]), 0, 0 }, + { "mmOTG5_OTG_COUNT_RESET", REG_MMIO, 0x1dd0, 2, &mmOTG5_OTG_COUNT_RESET[0], sizeof(mmOTG5_OTG_COUNT_RESET)/sizeof(mmOTG5_OTG_COUNT_RESET[0]), 0, 0 }, + { "mmOTG5_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE", REG_MMIO, 0x1dd1, 2, &mmOTG5_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE[0], sizeof(mmOTG5_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE)/sizeof(mmOTG5_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE[0]), 0, 0 }, + { "mmOTG5_OTG_VERT_SYNC_CONTROL", REG_MMIO, 0x1dd2, 2, &mmOTG5_OTG_VERT_SYNC_CONTROL[0], sizeof(mmOTG5_OTG_VERT_SYNC_CONTROL)/sizeof(mmOTG5_OTG_VERT_SYNC_CONTROL[0]), 0, 0 }, + { "mmOTG5_OTG_STEREO_STATUS", REG_MMIO, 0x1dd3, 2, &mmOTG5_OTG_STEREO_STATUS[0], sizeof(mmOTG5_OTG_STEREO_STATUS)/sizeof(mmOTG5_OTG_STEREO_STATUS[0]), 0, 0 }, + { "mmOTG5_OTG_STEREO_CONTROL", REG_MMIO, 0x1dd4, 2, &mmOTG5_OTG_STEREO_CONTROL[0], sizeof(mmOTG5_OTG_STEREO_CONTROL)/sizeof(mmOTG5_OTG_STEREO_CONTROL[0]), 0, 0 }, + { "mmOTG5_OTG_SNAPSHOT_STATUS", REG_MMIO, 0x1dd5, 2, &mmOTG5_OTG_SNAPSHOT_STATUS[0], sizeof(mmOTG5_OTG_SNAPSHOT_STATUS)/sizeof(mmOTG5_OTG_SNAPSHOT_STATUS[0]), 0, 0 }, + { "mmOTG5_OTG_SNAPSHOT_CONTROL", REG_MMIO, 0x1dd6, 2, &mmOTG5_OTG_SNAPSHOT_CONTROL[0], sizeof(mmOTG5_OTG_SNAPSHOT_CONTROL)/sizeof(mmOTG5_OTG_SNAPSHOT_CONTROL[0]), 0, 0 }, + { "mmOTG5_OTG_SNAPSHOT_POSITION", REG_MMIO, 0x1dd7, 2, &mmOTG5_OTG_SNAPSHOT_POSITION[0], sizeof(mmOTG5_OTG_SNAPSHOT_POSITION)/sizeof(mmOTG5_OTG_SNAPSHOT_POSITION[0]), 0, 0 }, + { "mmOTG5_OTG_SNAPSHOT_FRAME", REG_MMIO, 0x1dd8, 2, &mmOTG5_OTG_SNAPSHOT_FRAME[0], sizeof(mmOTG5_OTG_SNAPSHOT_FRAME)/sizeof(mmOTG5_OTG_SNAPSHOT_FRAME[0]), 0, 0 }, + { "mmOTG5_OTG_INTERRUPT_CONTROL", REG_MMIO, 0x1dd9, 2, &mmOTG5_OTG_INTERRUPT_CONTROL[0], sizeof(mmOTG5_OTG_INTERRUPT_CONTROL)/sizeof(mmOTG5_OTG_INTERRUPT_CONTROL[0]), 0, 0 }, + { "mmOTG5_OTG_UPDATE_LOCK", REG_MMIO, 0x1dda, 2, &mmOTG5_OTG_UPDATE_LOCK[0], sizeof(mmOTG5_OTG_UPDATE_LOCK)/sizeof(mmOTG5_OTG_UPDATE_LOCK[0]), 0, 0 }, + { "mmOTG5_OTG_DOUBLE_BUFFER_CONTROL", REG_MMIO, 0x1ddb, 2, &mmOTG5_OTG_DOUBLE_BUFFER_CONTROL[0], sizeof(mmOTG5_OTG_DOUBLE_BUFFER_CONTROL)/sizeof(mmOTG5_OTG_DOUBLE_BUFFER_CONTROL[0]), 0, 0 }, + { "mmOTG5_OTG_TEST_PATTERN_CONTROL", REG_MMIO, 0x1ddc, 2, &mmOTG5_OTG_TEST_PATTERN_CONTROL[0], sizeof(mmOTG5_OTG_TEST_PATTERN_CONTROL)/sizeof(mmOTG5_OTG_TEST_PATTERN_CONTROL[0]), 0, 0 }, + { "mmOTG5_OTG_TEST_PATTERN_PARAMETERS", REG_MMIO, 0x1ddd, 2, &mmOTG5_OTG_TEST_PATTERN_PARAMETERS[0], sizeof(mmOTG5_OTG_TEST_PATTERN_PARAMETERS)/sizeof(mmOTG5_OTG_TEST_PATTERN_PARAMETERS[0]), 0, 0 }, + { "mmOTG5_OTG_TEST_PATTERN_COLOR", REG_MMIO, 0x1dde, 2, &mmOTG5_OTG_TEST_PATTERN_COLOR[0], sizeof(mmOTG5_OTG_TEST_PATTERN_COLOR)/sizeof(mmOTG5_OTG_TEST_PATTERN_COLOR[0]), 0, 0 }, + { "mmOTG5_OTG_MASTER_EN", REG_MMIO, 0x1ddf, 2, &mmOTG5_OTG_MASTER_EN[0], sizeof(mmOTG5_OTG_MASTER_EN)/sizeof(mmOTG5_OTG_MASTER_EN[0]), 0, 0 }, + { "mmOTG5_OTG_BLANK_DATA_COLOR", REG_MMIO, 0x1de1, 2, &mmOTG5_OTG_BLANK_DATA_COLOR[0], sizeof(mmOTG5_OTG_BLANK_DATA_COLOR)/sizeof(mmOTG5_OTG_BLANK_DATA_COLOR[0]), 0, 0 }, + { "mmOTG5_OTG_BLANK_DATA_COLOR_EXT", REG_MMIO, 0x1de2, 2, &mmOTG5_OTG_BLANK_DATA_COLOR_EXT[0], sizeof(mmOTG5_OTG_BLANK_DATA_COLOR_EXT)/sizeof(mmOTG5_OTG_BLANK_DATA_COLOR_EXT[0]), 0, 0 }, + { "mmOTG5_OTG_BLACK_COLOR", REG_MMIO, 0x1de3, 2, &mmOTG5_OTG_BLACK_COLOR[0], sizeof(mmOTG5_OTG_BLACK_COLOR)/sizeof(mmOTG5_OTG_BLACK_COLOR[0]), 0, 0 }, + { "mmOTG5_OTG_BLACK_COLOR_EXT", REG_MMIO, 0x1de4, 2, &mmOTG5_OTG_BLACK_COLOR_EXT[0], sizeof(mmOTG5_OTG_BLACK_COLOR_EXT)/sizeof(mmOTG5_OTG_BLACK_COLOR_EXT[0]), 0, 0 }, + { "mmOTG5_OTG_VERTICAL_INTERRUPT0_POSITION", REG_MMIO, 0x1de5, 2, &mmOTG5_OTG_VERTICAL_INTERRUPT0_POSITION[0], sizeof(mmOTG5_OTG_VERTICAL_INTERRUPT0_POSITION)/sizeof(mmOTG5_OTG_VERTICAL_INTERRUPT0_POSITION[0]), 0, 0 }, + { "mmOTG5_OTG_VERTICAL_INTERRUPT0_CONTROL", REG_MMIO, 0x1de6, 2, &mmOTG5_OTG_VERTICAL_INTERRUPT0_CONTROL[0], sizeof(mmOTG5_OTG_VERTICAL_INTERRUPT0_CONTROL)/sizeof(mmOTG5_OTG_VERTICAL_INTERRUPT0_CONTROL[0]), 0, 0 }, + { "mmOTG5_OTG_VERTICAL_INTERRUPT1_POSITION", REG_MMIO, 0x1de7, 2, &mmOTG5_OTG_VERTICAL_INTERRUPT1_POSITION[0], sizeof(mmOTG5_OTG_VERTICAL_INTERRUPT1_POSITION)/sizeof(mmOTG5_OTG_VERTICAL_INTERRUPT1_POSITION[0]), 0, 0 }, + { "mmOTG5_OTG_VERTICAL_INTERRUPT1_CONTROL", REG_MMIO, 0x1de8, 2, &mmOTG5_OTG_VERTICAL_INTERRUPT1_CONTROL[0], sizeof(mmOTG5_OTG_VERTICAL_INTERRUPT1_CONTROL)/sizeof(mmOTG5_OTG_VERTICAL_INTERRUPT1_CONTROL[0]), 0, 0 }, + { "mmOTG5_OTG_VERTICAL_INTERRUPT2_POSITION", REG_MMIO, 0x1de9, 2, &mmOTG5_OTG_VERTICAL_INTERRUPT2_POSITION[0], sizeof(mmOTG5_OTG_VERTICAL_INTERRUPT2_POSITION)/sizeof(mmOTG5_OTG_VERTICAL_INTERRUPT2_POSITION[0]), 0, 0 }, + { "mmOTG5_OTG_VERTICAL_INTERRUPT2_CONTROL", REG_MMIO, 0x1dea, 2, &mmOTG5_OTG_VERTICAL_INTERRUPT2_CONTROL[0], sizeof(mmOTG5_OTG_VERTICAL_INTERRUPT2_CONTROL)/sizeof(mmOTG5_OTG_VERTICAL_INTERRUPT2_CONTROL[0]), 0, 0 }, + { "mmOTG5_OTG_CRC_CNTL", REG_MMIO, 0x1deb, 2, &mmOTG5_OTG_CRC_CNTL[0], sizeof(mmOTG5_OTG_CRC_CNTL)/sizeof(mmOTG5_OTG_CRC_CNTL[0]), 0, 0 }, + { "mmOTG5_OTG_CRC0_WINDOWA_X_CONTROL", REG_MMIO, 0x1dec, 2, &mmOTG5_OTG_CRC0_WINDOWA_X_CONTROL[0], sizeof(mmOTG5_OTG_CRC0_WINDOWA_X_CONTROL)/sizeof(mmOTG5_OTG_CRC0_WINDOWA_X_CONTROL[0]), 0, 0 }, + { "mmOTG5_OTG_CRC0_WINDOWA_Y_CONTROL", REG_MMIO, 0x1ded, 2, &mmOTG5_OTG_CRC0_WINDOWA_Y_CONTROL[0], sizeof(mmOTG5_OTG_CRC0_WINDOWA_Y_CONTROL)/sizeof(mmOTG5_OTG_CRC0_WINDOWA_Y_CONTROL[0]), 0, 0 }, + { "mmOTG5_OTG_CRC0_WINDOWB_X_CONTROL", REG_MMIO, 0x1dee, 2, &mmOTG5_OTG_CRC0_WINDOWB_X_CONTROL[0], sizeof(mmOTG5_OTG_CRC0_WINDOWB_X_CONTROL)/sizeof(mmOTG5_OTG_CRC0_WINDOWB_X_CONTROL[0]), 0, 0 }, + { "mmOTG5_OTG_CRC0_WINDOWB_Y_CONTROL", REG_MMIO, 0x1def, 2, &mmOTG5_OTG_CRC0_WINDOWB_Y_CONTROL[0], sizeof(mmOTG5_OTG_CRC0_WINDOWB_Y_CONTROL)/sizeof(mmOTG5_OTG_CRC0_WINDOWB_Y_CONTROL[0]), 0, 0 }, + { "mmOTG5_OTG_CRC0_DATA_RG", REG_MMIO, 0x1df0, 2, &mmOTG5_OTG_CRC0_DATA_RG[0], sizeof(mmOTG5_OTG_CRC0_DATA_RG)/sizeof(mmOTG5_OTG_CRC0_DATA_RG[0]), 0, 0 }, + { "mmOTG5_OTG_CRC0_DATA_B", REG_MMIO, 0x1df1, 2, &mmOTG5_OTG_CRC0_DATA_B[0], sizeof(mmOTG5_OTG_CRC0_DATA_B)/sizeof(mmOTG5_OTG_CRC0_DATA_B[0]), 0, 0 }, + { "mmOTG5_OTG_CRC1_WINDOWA_X_CONTROL", REG_MMIO, 0x1df2, 2, &mmOTG5_OTG_CRC1_WINDOWA_X_CONTROL[0], sizeof(mmOTG5_OTG_CRC1_WINDOWA_X_CONTROL)/sizeof(mmOTG5_OTG_CRC1_WINDOWA_X_CONTROL[0]), 0, 0 }, + { "mmOTG5_OTG_CRC1_WINDOWA_Y_CONTROL", REG_MMIO, 0x1df3, 2, &mmOTG5_OTG_CRC1_WINDOWA_Y_CONTROL[0], sizeof(mmOTG5_OTG_CRC1_WINDOWA_Y_CONTROL)/sizeof(mmOTG5_OTG_CRC1_WINDOWA_Y_CONTROL[0]), 0, 0 }, + { "mmOTG5_OTG_CRC1_WINDOWB_X_CONTROL", REG_MMIO, 0x1df4, 2, &mmOTG5_OTG_CRC1_WINDOWB_X_CONTROL[0], sizeof(mmOTG5_OTG_CRC1_WINDOWB_X_CONTROL)/sizeof(mmOTG5_OTG_CRC1_WINDOWB_X_CONTROL[0]), 0, 0 }, + { "mmOTG5_OTG_CRC1_WINDOWB_Y_CONTROL", REG_MMIO, 0x1df5, 2, &mmOTG5_OTG_CRC1_WINDOWB_Y_CONTROL[0], sizeof(mmOTG5_OTG_CRC1_WINDOWB_Y_CONTROL)/sizeof(mmOTG5_OTG_CRC1_WINDOWB_Y_CONTROL[0]), 0, 0 }, + { "mmOTG5_OTG_CRC1_DATA_RG", REG_MMIO, 0x1df6, 2, &mmOTG5_OTG_CRC1_DATA_RG[0], sizeof(mmOTG5_OTG_CRC1_DATA_RG)/sizeof(mmOTG5_OTG_CRC1_DATA_RG[0]), 0, 0 }, + { "mmOTG5_OTG_CRC1_DATA_B", REG_MMIO, 0x1df7, 2, &mmOTG5_OTG_CRC1_DATA_B[0], sizeof(mmOTG5_OTG_CRC1_DATA_B)/sizeof(mmOTG5_OTG_CRC1_DATA_B[0]), 0, 0 }, + { "mmOTG5_OTG_CRC2_DATA_RG", REG_MMIO, 0x1df8, 2, &mmOTG5_OTG_CRC2_DATA_RG[0], sizeof(mmOTG5_OTG_CRC2_DATA_RG)/sizeof(mmOTG5_OTG_CRC2_DATA_RG[0]), 0, 0 }, + { "mmOTG5_OTG_CRC2_DATA_B", REG_MMIO, 0x1df9, 2, &mmOTG5_OTG_CRC2_DATA_B[0], sizeof(mmOTG5_OTG_CRC2_DATA_B)/sizeof(mmOTG5_OTG_CRC2_DATA_B[0]), 0, 0 }, + { "mmOTG5_OTG_CRC3_DATA_RG", REG_MMIO, 0x1dfa, 2, &mmOTG5_OTG_CRC3_DATA_RG[0], sizeof(mmOTG5_OTG_CRC3_DATA_RG)/sizeof(mmOTG5_OTG_CRC3_DATA_RG[0]), 0, 0 }, + { "mmOTG5_OTG_CRC3_DATA_B", REG_MMIO, 0x1dfb, 2, &mmOTG5_OTG_CRC3_DATA_B[0], sizeof(mmOTG5_OTG_CRC3_DATA_B)/sizeof(mmOTG5_OTG_CRC3_DATA_B[0]), 0, 0 }, + { "mmOTG5_OTG_CRC_SIG_RED_GREEN_MASK", REG_MMIO, 0x1dfc, 2, &mmOTG5_OTG_CRC_SIG_RED_GREEN_MASK[0], sizeof(mmOTG5_OTG_CRC_SIG_RED_GREEN_MASK)/sizeof(mmOTG5_OTG_CRC_SIG_RED_GREEN_MASK[0]), 0, 0 }, + { "mmOTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK", REG_MMIO, 0x1dfd, 2, &mmOTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK[0], sizeof(mmOTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK)/sizeof(mmOTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK[0]), 0, 0 }, + { "mmOTG5_OTG_STATIC_SCREEN_CONTROL", REG_MMIO, 0x1e04, 2, &mmOTG5_OTG_STATIC_SCREEN_CONTROL[0], sizeof(mmOTG5_OTG_STATIC_SCREEN_CONTROL)/sizeof(mmOTG5_OTG_STATIC_SCREEN_CONTROL[0]), 0, 0 }, + { "mmOTG5_OTG_3D_STRUCTURE_CONTROL", REG_MMIO, 0x1e05, 2, &mmOTG5_OTG_3D_STRUCTURE_CONTROL[0], sizeof(mmOTG5_OTG_3D_STRUCTURE_CONTROL)/sizeof(mmOTG5_OTG_3D_STRUCTURE_CONTROL[0]), 0, 0 }, + { "mmOTG5_OTG_GSL_VSYNC_GAP", REG_MMIO, 0x1e06, 2, &mmOTG5_OTG_GSL_VSYNC_GAP[0], sizeof(mmOTG5_OTG_GSL_VSYNC_GAP)/sizeof(mmOTG5_OTG_GSL_VSYNC_GAP[0]), 0, 0 }, + { "mmOTG5_OTG_MASTER_UPDATE_MODE", REG_MMIO, 0x1e07, 2, &mmOTG5_OTG_MASTER_UPDATE_MODE[0], sizeof(mmOTG5_OTG_MASTER_UPDATE_MODE)/sizeof(mmOTG5_OTG_MASTER_UPDATE_MODE[0]), 0, 0 }, + { "mmOTG5_OTG_CLOCK_CONTROL", REG_MMIO, 0x1e08, 2, &mmOTG5_OTG_CLOCK_CONTROL[0], sizeof(mmOTG5_OTG_CLOCK_CONTROL)/sizeof(mmOTG5_OTG_CLOCK_CONTROL[0]), 0, 0 }, + { "mmOTG5_OTG_VSTARTUP_PARAM", REG_MMIO, 0x1e09, 2, &mmOTG5_OTG_VSTARTUP_PARAM[0], sizeof(mmOTG5_OTG_VSTARTUP_PARAM)/sizeof(mmOTG5_OTG_VSTARTUP_PARAM[0]), 0, 0 }, + { "mmOTG5_OTG_VUPDATE_PARAM", REG_MMIO, 0x1e0a, 2, &mmOTG5_OTG_VUPDATE_PARAM[0], sizeof(mmOTG5_OTG_VUPDATE_PARAM)/sizeof(mmOTG5_OTG_VUPDATE_PARAM[0]), 0, 0 }, + { "mmOTG5_OTG_VREADY_PARAM", REG_MMIO, 0x1e0b, 2, &mmOTG5_OTG_VREADY_PARAM[0], sizeof(mmOTG5_OTG_VREADY_PARAM)/sizeof(mmOTG5_OTG_VREADY_PARAM[0]), 0, 0 }, + { "mmOTG5_OTG_GLOBAL_SYNC_STATUS", REG_MMIO, 0x1e0c, 2, &mmOTG5_OTG_GLOBAL_SYNC_STATUS[0], sizeof(mmOTG5_OTG_GLOBAL_SYNC_STATUS)/sizeof(mmOTG5_OTG_GLOBAL_SYNC_STATUS[0]), 0, 0 }, + { "mmOTG5_OTG_MASTER_UPDATE_LOCK", REG_MMIO, 0x1e0d, 2, &mmOTG5_OTG_MASTER_UPDATE_LOCK[0], sizeof(mmOTG5_OTG_MASTER_UPDATE_LOCK)/sizeof(mmOTG5_OTG_MASTER_UPDATE_LOCK[0]), 0, 0 }, + { "mmOTG5_OTG_GSL_CONTROL", REG_MMIO, 0x1e0e, 2, &mmOTG5_OTG_GSL_CONTROL[0], sizeof(mmOTG5_OTG_GSL_CONTROL)/sizeof(mmOTG5_OTG_GSL_CONTROL[0]), 0, 0 }, + { "mmOTG5_OTG_GSL_WINDOW_X", REG_MMIO, 0x1e0f, 2, &mmOTG5_OTG_GSL_WINDOW_X[0], sizeof(mmOTG5_OTG_GSL_WINDOW_X)/sizeof(mmOTG5_OTG_GSL_WINDOW_X[0]), 0, 0 }, + { "mmOTG5_OTG_GSL_WINDOW_Y", REG_MMIO, 0x1e10, 2, &mmOTG5_OTG_GSL_WINDOW_Y[0], sizeof(mmOTG5_OTG_GSL_WINDOW_Y)/sizeof(mmOTG5_OTG_GSL_WINDOW_Y[0]), 0, 0 }, + { "mmOTG5_OTG_VUPDATE_KEEPOUT", REG_MMIO, 0x1e11, 2, &mmOTG5_OTG_VUPDATE_KEEPOUT[0], sizeof(mmOTG5_OTG_VUPDATE_KEEPOUT)/sizeof(mmOTG5_OTG_VUPDATE_KEEPOUT[0]), 0, 0 }, + { "mmOTG5_OTG_GLOBAL_CONTROL0", REG_MMIO, 0x1e12, 2, &mmOTG5_OTG_GLOBAL_CONTROL0[0], sizeof(mmOTG5_OTG_GLOBAL_CONTROL0)/sizeof(mmOTG5_OTG_GLOBAL_CONTROL0[0]), 0, 0 }, + { "mmOTG5_OTG_GLOBAL_CONTROL1", REG_MMIO, 0x1e13, 2, &mmOTG5_OTG_GLOBAL_CONTROL1[0], sizeof(mmOTG5_OTG_GLOBAL_CONTROL1)/sizeof(mmOTG5_OTG_GLOBAL_CONTROL1[0]), 0, 0 }, + { "mmOTG5_OTG_GLOBAL_CONTROL2", REG_MMIO, 0x1e14, 2, &mmOTG5_OTG_GLOBAL_CONTROL2[0], sizeof(mmOTG5_OTG_GLOBAL_CONTROL2)/sizeof(mmOTG5_OTG_GLOBAL_CONTROL2[0]), 0, 0 }, + { "mmOTG5_OTG_GLOBAL_CONTROL3", REG_MMIO, 0x1e15, 2, &mmOTG5_OTG_GLOBAL_CONTROL3[0], sizeof(mmOTG5_OTG_GLOBAL_CONTROL3)/sizeof(mmOTG5_OTG_GLOBAL_CONTROL3[0]), 0, 0 }, + { "mmOTG5_OTG_TRIG_MANUAL_CONTROL", REG_MMIO, 0x1e16, 2, &mmOTG5_OTG_TRIG_MANUAL_CONTROL[0], sizeof(mmOTG5_OTG_TRIG_MANUAL_CONTROL)/sizeof(mmOTG5_OTG_TRIG_MANUAL_CONTROL[0]), 0, 0 }, + { "mmOTG5_OTG_MANUAL_FLOW_CONTROL", REG_MMIO, 0x1e17, 2, &mmOTG5_OTG_MANUAL_FLOW_CONTROL[0], sizeof(mmOTG5_OTG_MANUAL_FLOW_CONTROL)/sizeof(mmOTG5_OTG_MANUAL_FLOW_CONTROL[0]), 0, 0 }, + { "mmOTG5_OTG_RANGE_TIMING_INT_STATUS", REG_MMIO, 0x1e18, 2, &mmOTG5_OTG_RANGE_TIMING_INT_STATUS[0], sizeof(mmOTG5_OTG_RANGE_TIMING_INT_STATUS)/sizeof(mmOTG5_OTG_RANGE_TIMING_INT_STATUS[0]), 0, 0 }, + { "mmOTG5_OTG_DRR_CONTROL", REG_MMIO, 0x1e19, 2, &mmOTG5_OTG_DRR_CONTROL[0], sizeof(mmOTG5_OTG_DRR_CONTROL)/sizeof(mmOTG5_OTG_DRR_CONTROL[0]), 0, 0 }, + { "mmOTG5_OTG_REQUEST_CONTROL", REG_MMIO, 0x1e1a, 2, &mmOTG5_OTG_REQUEST_CONTROL[0], sizeof(mmOTG5_OTG_REQUEST_CONTROL)/sizeof(mmOTG5_OTG_REQUEST_CONTROL[0]), 0, 0 }, + { "mmOTG5_OTG_SPARE_REGISTER", REG_MMIO, 0x1e1b, 2, &mmOTG5_OTG_SPARE_REGISTER[0], sizeof(mmOTG5_OTG_SPARE_REGISTER)/sizeof(mmOTG5_OTG_SPARE_REGISTER[0]), 0, 0 }, + { "mmDWB_SOURCE_SELECT", REG_MMIO, 0x1e2a, 2, &mmDWB_SOURCE_SELECT[0], sizeof(mmDWB_SOURCE_SELECT)/sizeof(mmDWB_SOURCE_SELECT[0]), 0, 0 }, + { "mmGSL_SOURCE_SELECT", REG_MMIO, 0x1e2b, 2, &mmGSL_SOURCE_SELECT[0], sizeof(mmGSL_SOURCE_SELECT)/sizeof(mmGSL_SOURCE_SELECT[0]), 0, 0 }, + { "mmOPTC_CLOCK_CONTROL", REG_MMIO, 0x1e2c, 2, &mmOPTC_CLOCK_CONTROL[0], sizeof(mmOPTC_CLOCK_CONTROL)/sizeof(mmOPTC_CLOCK_CONTROL[0]), 0, 0 }, + { "mmOPTC_MISC_SPARE_REGISTER", REG_MMIO, 0x1e2d, 2, &mmOPTC_MISC_SPARE_REGISTER[0], sizeof(mmOPTC_MISC_SPARE_REGISTER)/sizeof(mmOPTC_MISC_SPARE_REGISTER[0]), 0, 0 }, + { "mmDC_PERFMON18_PERFCOUNTER_CNTL", REG_MMIO, 0x1e6a, 2, &mmDC_PERFMON18_PERFCOUNTER_CNTL[0], sizeof(mmDC_PERFMON18_PERFCOUNTER_CNTL)/sizeof(mmDC_PERFMON18_PERFCOUNTER_CNTL[0]), 0, 0 }, + { "mmDC_PERFMON18_PERFCOUNTER_CNTL2", REG_MMIO, 0x1e6b, 2, &mmDC_PERFMON18_PERFCOUNTER_CNTL2[0], sizeof(mmDC_PERFMON18_PERFCOUNTER_CNTL2)/sizeof(mmDC_PERFMON18_PERFCOUNTER_CNTL2[0]), 0, 0 }, + { "mmDC_PERFMON18_PERFCOUNTER_STATE", REG_MMIO, 0x1e6c, 2, &mmDC_PERFMON18_PERFCOUNTER_STATE[0], sizeof(mmDC_PERFMON18_PERFCOUNTER_STATE)/sizeof(mmDC_PERFMON18_PERFCOUNTER_STATE[0]), 0, 0 }, + { "mmDC_PERFMON18_PERFMON_CNTL", REG_MMIO, 0x1e6d, 2, &mmDC_PERFMON18_PERFMON_CNTL[0], sizeof(mmDC_PERFMON18_PERFMON_CNTL)/sizeof(mmDC_PERFMON18_PERFMON_CNTL[0]), 0, 0 }, + { "mmDC_PERFMON18_PERFMON_CNTL2", REG_MMIO, 0x1e6e, 2, &mmDC_PERFMON18_PERFMON_CNTL2[0], sizeof(mmDC_PERFMON18_PERFMON_CNTL2)/sizeof(mmDC_PERFMON18_PERFMON_CNTL2[0]), 0, 0 }, + { "mmDC_PERFMON18_PERFMON_CVALUE_INT_MISC", REG_MMIO, 0x1e6f, 2, &mmDC_PERFMON18_PERFMON_CVALUE_INT_MISC[0], sizeof(mmDC_PERFMON18_PERFMON_CVALUE_INT_MISC)/sizeof(mmDC_PERFMON18_PERFMON_CVALUE_INT_MISC[0]), 0, 0 }, + { "mmDC_PERFMON18_PERFMON_CVALUE_LOW", REG_MMIO, 0x1e70, 2, &mmDC_PERFMON18_PERFMON_CVALUE_LOW[0], sizeof(mmDC_PERFMON18_PERFMON_CVALUE_LOW)/sizeof(mmDC_PERFMON18_PERFMON_CVALUE_LOW[0]), 0, 0 }, + { "mmDC_PERFMON18_PERFMON_HI", REG_MMIO, 0x1e71, 2, &mmDC_PERFMON18_PERFMON_HI[0], sizeof(mmDC_PERFMON18_PERFMON_HI)/sizeof(mmDC_PERFMON18_PERFMON_HI[0]), 0, 0 }, + { "mmDC_PERFMON18_PERFMON_LOW", REG_MMIO, 0x1e72, 2, &mmDC_PERFMON18_PERFMON_LOW[0], sizeof(mmDC_PERFMON18_PERFMON_LOW)/sizeof(mmDC_PERFMON18_PERFMON_LOW[0]), 0, 0 }, + { "mmDAC_ENABLE", REG_MMIO, 0x1e76, 2, &mmDAC_ENABLE[0], sizeof(mmDAC_ENABLE)/sizeof(mmDAC_ENABLE[0]), 0, 0 }, + { "mmDAC_SOURCE_SELECT", REG_MMIO, 0x1e77, 2, &mmDAC_SOURCE_SELECT[0], sizeof(mmDAC_SOURCE_SELECT)/sizeof(mmDAC_SOURCE_SELECT[0]), 0, 0 }, + { "mmDAC_CRC_EN", REG_MMIO, 0x1e78, 2, &mmDAC_CRC_EN[0], sizeof(mmDAC_CRC_EN)/sizeof(mmDAC_CRC_EN[0]), 0, 0 }, + { "mmDAC_CRC_CONTROL", REG_MMIO, 0x1e79, 2, &mmDAC_CRC_CONTROL[0], sizeof(mmDAC_CRC_CONTROL)/sizeof(mmDAC_CRC_CONTROL[0]), 0, 0 }, + { "mmDAC_CRC_SIG_RGB_MASK", REG_MMIO, 0x1e7a, 2, &mmDAC_CRC_SIG_RGB_MASK[0], sizeof(mmDAC_CRC_SIG_RGB_MASK)/sizeof(mmDAC_CRC_SIG_RGB_MASK[0]), 0, 0 }, + { "mmDAC_CRC_SIG_CONTROL_MASK", REG_MMIO, 0x1e7b, 2, &mmDAC_CRC_SIG_CONTROL_MASK[0], sizeof(mmDAC_CRC_SIG_CONTROL_MASK)/sizeof(mmDAC_CRC_SIG_CONTROL_MASK[0]), 0, 0 }, + { "mmDAC_CRC_SIG_RGB", REG_MMIO, 0x1e7c, 2, &mmDAC_CRC_SIG_RGB[0], sizeof(mmDAC_CRC_SIG_RGB)/sizeof(mmDAC_CRC_SIG_RGB[0]), 0, 0 }, + { "mmDAC_CRC_SIG_CONTROL", REG_MMIO, 0x1e7d, 2, &mmDAC_CRC_SIG_CONTROL[0], sizeof(mmDAC_CRC_SIG_CONTROL)/sizeof(mmDAC_CRC_SIG_CONTROL[0]), 0, 0 }, + { "mmDAC_SYNC_TRISTATE_CONTROL", REG_MMIO, 0x1e7e, 2, &mmDAC_SYNC_TRISTATE_CONTROL[0], sizeof(mmDAC_SYNC_TRISTATE_CONTROL)/sizeof(mmDAC_SYNC_TRISTATE_CONTROL[0]), 0, 0 }, + { "mmDAC_STEREOSYNC_SELECT", REG_MMIO, 0x1e7f, 2, &mmDAC_STEREOSYNC_SELECT[0], sizeof(mmDAC_STEREOSYNC_SELECT)/sizeof(mmDAC_STEREOSYNC_SELECT[0]), 0, 0 }, + { "mmDAC_AUTODETECT_CONTROL", REG_MMIO, 0x1e80, 2, &mmDAC_AUTODETECT_CONTROL[0], sizeof(mmDAC_AUTODETECT_CONTROL)/sizeof(mmDAC_AUTODETECT_CONTROL[0]), 0, 0 }, + { "mmDAC_AUTODETECT_CONTROL2", REG_MMIO, 0x1e81, 2, &mmDAC_AUTODETECT_CONTROL2[0], sizeof(mmDAC_AUTODETECT_CONTROL2)/sizeof(mmDAC_AUTODETECT_CONTROL2[0]), 0, 0 }, + { "mmDAC_AUTODETECT_CONTROL3", REG_MMIO, 0x1e82, 2, &mmDAC_AUTODETECT_CONTROL3[0], sizeof(mmDAC_AUTODETECT_CONTROL3)/sizeof(mmDAC_AUTODETECT_CONTROL3[0]), 0, 0 }, + { "mmDAC_AUTODETECT_STATUS", REG_MMIO, 0x1e83, 2, &mmDAC_AUTODETECT_STATUS[0], sizeof(mmDAC_AUTODETECT_STATUS)/sizeof(mmDAC_AUTODETECT_STATUS[0]), 0, 0 }, + { "mmDAC_AUTODETECT_INT_CONTROL", REG_MMIO, 0x1e84, 2, &mmDAC_AUTODETECT_INT_CONTROL[0], sizeof(mmDAC_AUTODETECT_INT_CONTROL)/sizeof(mmDAC_AUTODETECT_INT_CONTROL[0]), 0, 0 }, + { "mmDAC_FORCE_OUTPUT_CNTL", REG_MMIO, 0x1e85, 2, &mmDAC_FORCE_OUTPUT_CNTL[0], sizeof(mmDAC_FORCE_OUTPUT_CNTL)/sizeof(mmDAC_FORCE_OUTPUT_CNTL[0]), 0, 0 }, + { "mmDAC_FORCE_DATA", REG_MMIO, 0x1e86, 2, &mmDAC_FORCE_DATA[0], sizeof(mmDAC_FORCE_DATA)/sizeof(mmDAC_FORCE_DATA[0]), 0, 0 }, + { "mmDAC_POWERDOWN", REG_MMIO, 0x1e87, 2, &mmDAC_POWERDOWN[0], sizeof(mmDAC_POWERDOWN)/sizeof(mmDAC_POWERDOWN[0]), 0, 0 }, + { "mmDAC_CONTROL", REG_MMIO, 0x1e88, 2, &mmDAC_CONTROL[0], sizeof(mmDAC_CONTROL)/sizeof(mmDAC_CONTROL[0]), 0, 0 }, + { "mmDAC_COMPARATOR_ENABLE", REG_MMIO, 0x1e89, 2, &mmDAC_COMPARATOR_ENABLE[0], sizeof(mmDAC_COMPARATOR_ENABLE)/sizeof(mmDAC_COMPARATOR_ENABLE[0]), 0, 0 }, + { "mmDAC_COMPARATOR_OUTPUT", REG_MMIO, 0x1e8a, 2, &mmDAC_COMPARATOR_OUTPUT[0], sizeof(mmDAC_COMPARATOR_OUTPUT)/sizeof(mmDAC_COMPARATOR_OUTPUT[0]), 0, 0 }, + { "mmDAC_PWR_CNTL", REG_MMIO, 0x1e8b, 2, &mmDAC_PWR_CNTL[0], sizeof(mmDAC_PWR_CNTL)/sizeof(mmDAC_PWR_CNTL[0]), 0, 0 }, + { "mmDAC_DFT_CONFIG", REG_MMIO, 0x1e8c, 2, &mmDAC_DFT_CONFIG[0], sizeof(mmDAC_DFT_CONFIG)/sizeof(mmDAC_DFT_CONFIG[0]), 0, 0 }, + { "mmDAC_FIFO_STATUS", REG_MMIO, 0x1e8d, 2, &mmDAC_FIFO_STATUS[0], sizeof(mmDAC_FIFO_STATUS)/sizeof(mmDAC_FIFO_STATUS[0]), 0, 0 }, + { "mmDC_I2C_CONTROL", REG_MMIO, 0x1e98, 2, &mmDC_I2C_CONTROL[0], sizeof(mmDC_I2C_CONTROL)/sizeof(mmDC_I2C_CONTROL[0]), 0, 0 }, + { "mmDC_I2C_ARBITRATION", REG_MMIO, 0x1e99, 2, &mmDC_I2C_ARBITRATION[0], sizeof(mmDC_I2C_ARBITRATION)/sizeof(mmDC_I2C_ARBITRATION[0]), 0, 0 }, + { "mmDC_I2C_INTERRUPT_CONTROL", REG_MMIO, 0x1e9a, 2, &mmDC_I2C_INTERRUPT_CONTROL[0], sizeof(mmDC_I2C_INTERRUPT_CONTROL)/sizeof(mmDC_I2C_INTERRUPT_CONTROL[0]), 0, 0 }, + { "mmDC_I2C_SW_STATUS", REG_MMIO, 0x1e9b, 2, &mmDC_I2C_SW_STATUS[0], sizeof(mmDC_I2C_SW_STATUS)/sizeof(mmDC_I2C_SW_STATUS[0]), 0, 0 }, + { "mmDC_I2C_DDC1_HW_STATUS", REG_MMIO, 0x1e9c, 2, &mmDC_I2C_DDC1_HW_STATUS[0], sizeof(mmDC_I2C_DDC1_HW_STATUS)/sizeof(mmDC_I2C_DDC1_HW_STATUS[0]), 0, 0 }, + { "mmDC_I2C_DDC2_HW_STATUS", REG_MMIO, 0x1e9d, 2, &mmDC_I2C_DDC2_HW_STATUS[0], sizeof(mmDC_I2C_DDC2_HW_STATUS)/sizeof(mmDC_I2C_DDC2_HW_STATUS[0]), 0, 0 }, + { "mmDC_I2C_DDC3_HW_STATUS", REG_MMIO, 0x1e9e, 2, &mmDC_I2C_DDC3_HW_STATUS[0], sizeof(mmDC_I2C_DDC3_HW_STATUS)/sizeof(mmDC_I2C_DDC3_HW_STATUS[0]), 0, 0 }, + { "mmDC_I2C_DDC4_HW_STATUS", REG_MMIO, 0x1e9f, 2, &mmDC_I2C_DDC4_HW_STATUS[0], sizeof(mmDC_I2C_DDC4_HW_STATUS)/sizeof(mmDC_I2C_DDC4_HW_STATUS[0]), 0, 0 }, + { "mmDC_I2C_DDC5_HW_STATUS", REG_MMIO, 0x1ea0, 2, &mmDC_I2C_DDC5_HW_STATUS[0], sizeof(mmDC_I2C_DDC5_HW_STATUS)/sizeof(mmDC_I2C_DDC5_HW_STATUS[0]), 0, 0 }, + { "mmDC_I2C_DDC6_HW_STATUS", REG_MMIO, 0x1ea1, 2, &mmDC_I2C_DDC6_HW_STATUS[0], sizeof(mmDC_I2C_DDC6_HW_STATUS)/sizeof(mmDC_I2C_DDC6_HW_STATUS[0]), 0, 0 }, + { "mmDC_I2C_DDC1_SPEED", REG_MMIO, 0x1ea2, 2, &mmDC_I2C_DDC1_SPEED[0], sizeof(mmDC_I2C_DDC1_SPEED)/sizeof(mmDC_I2C_DDC1_SPEED[0]), 0, 0 }, + { "mmDC_I2C_DDC1_SETUP", REG_MMIO, 0x1ea3, 2, &mmDC_I2C_DDC1_SETUP[0], sizeof(mmDC_I2C_DDC1_SETUP)/sizeof(mmDC_I2C_DDC1_SETUP[0]), 0, 0 }, + { "mmDC_I2C_DDC2_SPEED", REG_MMIO, 0x1ea4, 2, &mmDC_I2C_DDC2_SPEED[0], sizeof(mmDC_I2C_DDC2_SPEED)/sizeof(mmDC_I2C_DDC2_SPEED[0]), 0, 0 }, + { "mmDC_I2C_DDC2_SETUP", REG_MMIO, 0x1ea5, 2, &mmDC_I2C_DDC2_SETUP[0], sizeof(mmDC_I2C_DDC2_SETUP)/sizeof(mmDC_I2C_DDC2_SETUP[0]), 0, 0 }, + { "mmDC_I2C_DDC3_SPEED", REG_MMIO, 0x1ea6, 2, &mmDC_I2C_DDC3_SPEED[0], sizeof(mmDC_I2C_DDC3_SPEED)/sizeof(mmDC_I2C_DDC3_SPEED[0]), 0, 0 }, + { "mmDC_I2C_DDC3_SETUP", REG_MMIO, 0x1ea7, 2, &mmDC_I2C_DDC3_SETUP[0], sizeof(mmDC_I2C_DDC3_SETUP)/sizeof(mmDC_I2C_DDC3_SETUP[0]), 0, 0 }, + { "mmDC_I2C_DDC4_SPEED", REG_MMIO, 0x1ea8, 2, &mmDC_I2C_DDC4_SPEED[0], sizeof(mmDC_I2C_DDC4_SPEED)/sizeof(mmDC_I2C_DDC4_SPEED[0]), 0, 0 }, + { "mmDC_I2C_DDC4_SETUP", REG_MMIO, 0x1ea9, 2, &mmDC_I2C_DDC4_SETUP[0], sizeof(mmDC_I2C_DDC4_SETUP)/sizeof(mmDC_I2C_DDC4_SETUP[0]), 0, 0 }, + { "mmDC_I2C_DDC5_SPEED", REG_MMIO, 0x1eaa, 2, &mmDC_I2C_DDC5_SPEED[0], sizeof(mmDC_I2C_DDC5_SPEED)/sizeof(mmDC_I2C_DDC5_SPEED[0]), 0, 0 }, + { "mmDC_I2C_DDC5_SETUP", REG_MMIO, 0x1eab, 2, &mmDC_I2C_DDC5_SETUP[0], sizeof(mmDC_I2C_DDC5_SETUP)/sizeof(mmDC_I2C_DDC5_SETUP[0]), 0, 0 }, + { "mmDC_I2C_DDC6_SPEED", REG_MMIO, 0x1eac, 2, &mmDC_I2C_DDC6_SPEED[0], sizeof(mmDC_I2C_DDC6_SPEED)/sizeof(mmDC_I2C_DDC6_SPEED[0]), 0, 0 }, + { "mmDC_I2C_DDC6_SETUP", REG_MMIO, 0x1ead, 2, &mmDC_I2C_DDC6_SETUP[0], sizeof(mmDC_I2C_DDC6_SETUP)/sizeof(mmDC_I2C_DDC6_SETUP[0]), 0, 0 }, + { "mmDC_I2C_TRANSACTION0", REG_MMIO, 0x1eae, 2, &mmDC_I2C_TRANSACTION0[0], sizeof(mmDC_I2C_TRANSACTION0)/sizeof(mmDC_I2C_TRANSACTION0[0]), 0, 0 }, + { "mmDC_I2C_TRANSACTION1", REG_MMIO, 0x1eaf, 2, &mmDC_I2C_TRANSACTION1[0], sizeof(mmDC_I2C_TRANSACTION1)/sizeof(mmDC_I2C_TRANSACTION1[0]), 0, 0 }, + { "mmDC_I2C_TRANSACTION2", REG_MMIO, 0x1eb0, 2, &mmDC_I2C_TRANSACTION2[0], sizeof(mmDC_I2C_TRANSACTION2)/sizeof(mmDC_I2C_TRANSACTION2[0]), 0, 0 }, + { "mmDC_I2C_TRANSACTION3", REG_MMIO, 0x1eb1, 2, &mmDC_I2C_TRANSACTION3[0], sizeof(mmDC_I2C_TRANSACTION3)/sizeof(mmDC_I2C_TRANSACTION3[0]), 0, 0 }, + { "mmDC_I2C_DATA", REG_MMIO, 0x1eb2, 2, &mmDC_I2C_DATA[0], sizeof(mmDC_I2C_DATA)/sizeof(mmDC_I2C_DATA[0]), 0, 0 }, + { "mmDC_I2C_DDCVGA_HW_STATUS", REG_MMIO, 0x1eb3, 2, &mmDC_I2C_DDCVGA_HW_STATUS[0], sizeof(mmDC_I2C_DDCVGA_HW_STATUS)/sizeof(mmDC_I2C_DDCVGA_HW_STATUS[0]), 0, 0 }, + { "mmDC_I2C_DDCVGA_SPEED", REG_MMIO, 0x1eb4, 2, &mmDC_I2C_DDCVGA_SPEED[0], sizeof(mmDC_I2C_DDCVGA_SPEED)/sizeof(mmDC_I2C_DDCVGA_SPEED[0]), 0, 0 }, + { "mmDC_I2C_DDCVGA_SETUP", REG_MMIO, 0x1eb5, 2, &mmDC_I2C_DDCVGA_SETUP[0], sizeof(mmDC_I2C_DDCVGA_SETUP)/sizeof(mmDC_I2C_DDCVGA_SETUP[0]), 0, 0 }, + { "mmDC_I2C_EDID_DETECT_CTRL", REG_MMIO, 0x1eb6, 2, &mmDC_I2C_EDID_DETECT_CTRL[0], sizeof(mmDC_I2C_EDID_DETECT_CTRL)/sizeof(mmDC_I2C_EDID_DETECT_CTRL[0]), 0, 0 }, + { "mmDC_I2C_READ_REQUEST_INTERRUPT", REG_MMIO, 0x1eb7, 2, &mmDC_I2C_READ_REQUEST_INTERRUPT[0], sizeof(mmDC_I2C_READ_REQUEST_INTERRUPT)/sizeof(mmDC_I2C_READ_REQUEST_INTERRUPT[0]), 0, 0 }, + { "mmGENERIC_I2C_CONTROL", REG_MMIO, 0x1eb8, 2, &mmGENERIC_I2C_CONTROL[0], sizeof(mmGENERIC_I2C_CONTROL)/sizeof(mmGENERIC_I2C_CONTROL[0]), 0, 0 }, + { "mmGENERIC_I2C_INTERRUPT_CONTROL", REG_MMIO, 0x1eb9, 2, &mmGENERIC_I2C_INTERRUPT_CONTROL[0], sizeof(mmGENERIC_I2C_INTERRUPT_CONTROL)/sizeof(mmGENERIC_I2C_INTERRUPT_CONTROL[0]), 0, 0 }, + { "mmGENERIC_I2C_STATUS", REG_MMIO, 0x1eba, 2, &mmGENERIC_I2C_STATUS[0], sizeof(mmGENERIC_I2C_STATUS)/sizeof(mmGENERIC_I2C_STATUS[0]), 0, 0 }, + { "mmGENERIC_I2C_SPEED", REG_MMIO, 0x1ebb, 2, &mmGENERIC_I2C_SPEED[0], sizeof(mmGENERIC_I2C_SPEED)/sizeof(mmGENERIC_I2C_SPEED[0]), 0, 0 }, + { "mmGENERIC_I2C_SETUP", REG_MMIO, 0x1ebc, 2, &mmGENERIC_I2C_SETUP[0], sizeof(mmGENERIC_I2C_SETUP)/sizeof(mmGENERIC_I2C_SETUP[0]), 0, 0 }, + { "mmGENERIC_I2C_TRANSACTION", REG_MMIO, 0x1ebd, 2, &mmGENERIC_I2C_TRANSACTION[0], sizeof(mmGENERIC_I2C_TRANSACTION)/sizeof(mmGENERIC_I2C_TRANSACTION[0]), 0, 0 }, + { "mmGENERIC_I2C_DATA", REG_MMIO, 0x1ebe, 2, &mmGENERIC_I2C_DATA[0], sizeof(mmGENERIC_I2C_DATA)/sizeof(mmGENERIC_I2C_DATA[0]), 0, 0 }, + { "mmGENERIC_I2C_PIN_SELECTION", REG_MMIO, 0x1ebf, 2, &mmGENERIC_I2C_PIN_SELECTION[0], sizeof(mmGENERIC_I2C_PIN_SELECTION)/sizeof(mmGENERIC_I2C_PIN_SELECTION[0]), 0, 0 }, + { "mmDIO_SCRATCH0", REG_MMIO, 0x1eca, 2, &mmDIO_SCRATCH0[0], sizeof(mmDIO_SCRATCH0)/sizeof(mmDIO_SCRATCH0[0]), 0, 0 }, + { "mmDIO_SCRATCH1", REG_MMIO, 0x1ecb, 2, &mmDIO_SCRATCH1[0], sizeof(mmDIO_SCRATCH1)/sizeof(mmDIO_SCRATCH1[0]), 0, 0 }, + { "mmDIO_SCRATCH2", REG_MMIO, 0x1ecc, 2, &mmDIO_SCRATCH2[0], sizeof(mmDIO_SCRATCH2)/sizeof(mmDIO_SCRATCH2[0]), 0, 0 }, + { "mmDIO_SCRATCH3", REG_MMIO, 0x1ecd, 2, &mmDIO_SCRATCH3[0], sizeof(mmDIO_SCRATCH3)/sizeof(mmDIO_SCRATCH3[0]), 0, 0 }, + { "mmDIO_SCRATCH4", REG_MMIO, 0x1ece, 2, &mmDIO_SCRATCH4[0], sizeof(mmDIO_SCRATCH4)/sizeof(mmDIO_SCRATCH4[0]), 0, 0 }, + { "mmDIO_SCRATCH5", REG_MMIO, 0x1ecf, 2, &mmDIO_SCRATCH5[0], sizeof(mmDIO_SCRATCH5)/sizeof(mmDIO_SCRATCH5[0]), 0, 0 }, + { "mmDIO_SCRATCH6", REG_MMIO, 0x1ed0, 2, &mmDIO_SCRATCH6[0], sizeof(mmDIO_SCRATCH6)/sizeof(mmDIO_SCRATCH6[0]), 0, 0 }, + { "mmDIO_SCRATCH7", REG_MMIO, 0x1ed1, 2, &mmDIO_SCRATCH7[0], sizeof(mmDIO_SCRATCH7)/sizeof(mmDIO_SCRATCH7[0]), 0, 0 }, + { "mmDCE_VCE_CONTROL", REG_MMIO, 0x1ed2, 2, &mmDCE_VCE_CONTROL[0], sizeof(mmDCE_VCE_CONTROL)/sizeof(mmDCE_VCE_CONTROL[0]), 0, 0 }, + { "mmDIO_MEM_PWR_STATUS", REG_MMIO, 0x1edd, 2, &mmDIO_MEM_PWR_STATUS[0], sizeof(mmDIO_MEM_PWR_STATUS)/sizeof(mmDIO_MEM_PWR_STATUS[0]), 0, 0 }, + { "mmDIO_MEM_PWR_CTRL", REG_MMIO, 0x1ede, 2, &mmDIO_MEM_PWR_CTRL[0], sizeof(mmDIO_MEM_PWR_CTRL)/sizeof(mmDIO_MEM_PWR_CTRL[0]), 0, 0 }, + { "mmDIO_MEM_PWR_CTRL2", REG_MMIO, 0x1edf, 2, &mmDIO_MEM_PWR_CTRL2[0], sizeof(mmDIO_MEM_PWR_CTRL2)/sizeof(mmDIO_MEM_PWR_CTRL2[0]), 0, 0 }, + { "mmDIO_CLK_CNTL", REG_MMIO, 0x1ee0, 2, &mmDIO_CLK_CNTL[0], sizeof(mmDIO_CLK_CNTL)/sizeof(mmDIO_CLK_CNTL[0]), 0, 0 }, + { "mmDIO_POWER_MANAGEMENT_CNTL", REG_MMIO, 0x1ee4, 2, &mmDIO_POWER_MANAGEMENT_CNTL[0], sizeof(mmDIO_POWER_MANAGEMENT_CNTL)/sizeof(mmDIO_POWER_MANAGEMENT_CNTL[0]), 0, 0 }, + { "mmDIO_STEREOSYNC_SEL", REG_MMIO, 0x1eea, 2, &mmDIO_STEREOSYNC_SEL[0], sizeof(mmDIO_STEREOSYNC_SEL)/sizeof(mmDIO_STEREOSYNC_SEL[0]), 0, 0 }, + { "mmDIO_SOFT_RESET", REG_MMIO, 0x1eed, 2, &mmDIO_SOFT_RESET[0], sizeof(mmDIO_SOFT_RESET)/sizeof(mmDIO_SOFT_RESET[0]), 0, 0 }, + { "mmDIG_SOFT_RESET", REG_MMIO, 0x1eee, 2, &mmDIG_SOFT_RESET[0], sizeof(mmDIG_SOFT_RESET)/sizeof(mmDIG_SOFT_RESET[0]), 0, 0 }, + { "mmDIO_MEM_PWR_STATUS1", REG_MMIO, 0x1ef0, 2, &mmDIO_MEM_PWR_STATUS1[0], sizeof(mmDIO_MEM_PWR_STATUS1)/sizeof(mmDIO_MEM_PWR_STATUS1[0]), 0, 0 }, + { "mmDIO_CLK_CNTL2", REG_MMIO, 0x1ef2, 2, &mmDIO_CLK_CNTL2[0], sizeof(mmDIO_CLK_CNTL2)/sizeof(mmDIO_CLK_CNTL2[0]), 0, 0 }, + { "mmDIO_CLK_CNTL3", REG_MMIO, 0x1ef3, 2, &mmDIO_CLK_CNTL3[0], sizeof(mmDIO_CLK_CNTL3)/sizeof(mmDIO_CLK_CNTL3[0]), 0, 0 }, + { "mmDIO_HDMI_RXSTATUS_TIMER_CONTROL", REG_MMIO, 0x1eff, 2, &mmDIO_HDMI_RXSTATUS_TIMER_CONTROL[0], sizeof(mmDIO_HDMI_RXSTATUS_TIMER_CONTROL)/sizeof(mmDIO_HDMI_RXSTATUS_TIMER_CONTROL[0]), 0, 0 }, + { "mmDIO_PSP_INTERRUPT_STATUS", REG_MMIO, 0x1f00, 2, &mmDIO_PSP_INTERRUPT_STATUS[0], sizeof(mmDIO_PSP_INTERRUPT_STATUS)/sizeof(mmDIO_PSP_INTERRUPT_STATUS[0]), 0, 0 }, + { "mmDIO_PSP_INTERRUPT_CLEAR", REG_MMIO, 0x1f01, 2, &mmDIO_PSP_INTERRUPT_CLEAR[0], sizeof(mmDIO_PSP_INTERRUPT_CLEAR)/sizeof(mmDIO_PSP_INTERRUPT_CLEAR[0]), 0, 0 }, + { "mmDIO_GENERIC_INTERRUPT_MESSAGE", REG_MMIO, 0x1f02, 2, &mmDIO_GENERIC_INTERRUPT_MESSAGE[0], sizeof(mmDIO_GENERIC_INTERRUPT_MESSAGE)/sizeof(mmDIO_GENERIC_INTERRUPT_MESSAGE[0]), 0, 0 }, + { "mmDIO_GENERIC_INTERRUPT_CLEAR", REG_MMIO, 0x1f03, 2, &mmDIO_GENERIC_INTERRUPT_CLEAR[0], sizeof(mmDIO_GENERIC_INTERRUPT_CLEAR)/sizeof(mmDIO_GENERIC_INTERRUPT_CLEAR[0]), 0, 0 }, + { "mmHPD0_DC_HPD_INT_STATUS", REG_MMIO, 0x1f14, 2, &mmHPD0_DC_HPD_INT_STATUS[0], sizeof(mmHPD0_DC_HPD_INT_STATUS)/sizeof(mmHPD0_DC_HPD_INT_STATUS[0]), 0, 0 }, + { "mmHPD0_DC_HPD_INT_CONTROL", REG_MMIO, 0x1f15, 2, &mmHPD0_DC_HPD_INT_CONTROL[0], sizeof(mmHPD0_DC_HPD_INT_CONTROL)/sizeof(mmHPD0_DC_HPD_INT_CONTROL[0]), 0, 0 }, + { "mmHPD0_DC_HPD_CONTROL", REG_MMIO, 0x1f16, 2, &mmHPD0_DC_HPD_CONTROL[0], sizeof(mmHPD0_DC_HPD_CONTROL)/sizeof(mmHPD0_DC_HPD_CONTROL[0]), 0, 0 }, + { "mmHPD0_DC_HPD_FAST_TRAIN_CNTL", REG_MMIO, 0x1f17, 2, &mmHPD0_DC_HPD_FAST_TRAIN_CNTL[0], sizeof(mmHPD0_DC_HPD_FAST_TRAIN_CNTL)/sizeof(mmHPD0_DC_HPD_FAST_TRAIN_CNTL[0]), 0, 0 }, + { "mmHPD0_DC_HPD_TOGGLE_FILT_CNTL", REG_MMIO, 0x1f18, 2, &mmHPD0_DC_HPD_TOGGLE_FILT_CNTL[0], sizeof(mmHPD0_DC_HPD_TOGGLE_FILT_CNTL)/sizeof(mmHPD0_DC_HPD_TOGGLE_FILT_CNTL[0]), 0, 0 }, + { "mmHPD1_DC_HPD_INT_STATUS", REG_MMIO, 0x1f1c, 2, &mmHPD1_DC_HPD_INT_STATUS[0], sizeof(mmHPD1_DC_HPD_INT_STATUS)/sizeof(mmHPD1_DC_HPD_INT_STATUS[0]), 0, 0 }, + { "mmHPD1_DC_HPD_INT_CONTROL", REG_MMIO, 0x1f1d, 2, &mmHPD1_DC_HPD_INT_CONTROL[0], sizeof(mmHPD1_DC_HPD_INT_CONTROL)/sizeof(mmHPD1_DC_HPD_INT_CONTROL[0]), 0, 0 }, + { "mmHPD1_DC_HPD_CONTROL", REG_MMIO, 0x1f1e, 2, &mmHPD1_DC_HPD_CONTROL[0], sizeof(mmHPD1_DC_HPD_CONTROL)/sizeof(mmHPD1_DC_HPD_CONTROL[0]), 0, 0 }, + { "mmHPD1_DC_HPD_FAST_TRAIN_CNTL", REG_MMIO, 0x1f1f, 2, &mmHPD1_DC_HPD_FAST_TRAIN_CNTL[0], sizeof(mmHPD1_DC_HPD_FAST_TRAIN_CNTL)/sizeof(mmHPD1_DC_HPD_FAST_TRAIN_CNTL[0]), 0, 0 }, + { "mmHPD1_DC_HPD_TOGGLE_FILT_CNTL", REG_MMIO, 0x1f20, 2, &mmHPD1_DC_HPD_TOGGLE_FILT_CNTL[0], sizeof(mmHPD1_DC_HPD_TOGGLE_FILT_CNTL)/sizeof(mmHPD1_DC_HPD_TOGGLE_FILT_CNTL[0]), 0, 0 }, + { "mmHPD2_DC_HPD_INT_STATUS", REG_MMIO, 0x1f24, 2, &mmHPD2_DC_HPD_INT_STATUS[0], sizeof(mmHPD2_DC_HPD_INT_STATUS)/sizeof(mmHPD2_DC_HPD_INT_STATUS[0]), 0, 0 }, + { "mmHPD2_DC_HPD_INT_CONTROL", REG_MMIO, 0x1f25, 2, &mmHPD2_DC_HPD_INT_CONTROL[0], sizeof(mmHPD2_DC_HPD_INT_CONTROL)/sizeof(mmHPD2_DC_HPD_INT_CONTROL[0]), 0, 0 }, + { "mmHPD2_DC_HPD_CONTROL", REG_MMIO, 0x1f26, 2, &mmHPD2_DC_HPD_CONTROL[0], sizeof(mmHPD2_DC_HPD_CONTROL)/sizeof(mmHPD2_DC_HPD_CONTROL[0]), 0, 0 }, + { "mmHPD2_DC_HPD_FAST_TRAIN_CNTL", REG_MMIO, 0x1f27, 2, &mmHPD2_DC_HPD_FAST_TRAIN_CNTL[0], sizeof(mmHPD2_DC_HPD_FAST_TRAIN_CNTL)/sizeof(mmHPD2_DC_HPD_FAST_TRAIN_CNTL[0]), 0, 0 }, + { "mmHPD2_DC_HPD_TOGGLE_FILT_CNTL", REG_MMIO, 0x1f28, 2, &mmHPD2_DC_HPD_TOGGLE_FILT_CNTL[0], sizeof(mmHPD2_DC_HPD_TOGGLE_FILT_CNTL)/sizeof(mmHPD2_DC_HPD_TOGGLE_FILT_CNTL[0]), 0, 0 }, + { "mmHPD3_DC_HPD_INT_STATUS", REG_MMIO, 0x1f2c, 2, &mmHPD3_DC_HPD_INT_STATUS[0], sizeof(mmHPD3_DC_HPD_INT_STATUS)/sizeof(mmHPD3_DC_HPD_INT_STATUS[0]), 0, 0 }, + { "mmHPD3_DC_HPD_INT_CONTROL", REG_MMIO, 0x1f2d, 2, &mmHPD3_DC_HPD_INT_CONTROL[0], sizeof(mmHPD3_DC_HPD_INT_CONTROL)/sizeof(mmHPD3_DC_HPD_INT_CONTROL[0]), 0, 0 }, + { "mmHPD3_DC_HPD_CONTROL", REG_MMIO, 0x1f2e, 2, &mmHPD3_DC_HPD_CONTROL[0], sizeof(mmHPD3_DC_HPD_CONTROL)/sizeof(mmHPD3_DC_HPD_CONTROL[0]), 0, 0 }, + { "mmHPD3_DC_HPD_FAST_TRAIN_CNTL", REG_MMIO, 0x1f2f, 2, &mmHPD3_DC_HPD_FAST_TRAIN_CNTL[0], sizeof(mmHPD3_DC_HPD_FAST_TRAIN_CNTL)/sizeof(mmHPD3_DC_HPD_FAST_TRAIN_CNTL[0]), 0, 0 }, + { "mmHPD3_DC_HPD_TOGGLE_FILT_CNTL", REG_MMIO, 0x1f30, 2, &mmHPD3_DC_HPD_TOGGLE_FILT_CNTL[0], sizeof(mmHPD3_DC_HPD_TOGGLE_FILT_CNTL)/sizeof(mmHPD3_DC_HPD_TOGGLE_FILT_CNTL[0]), 0, 0 }, + { "mmHPD4_DC_HPD_INT_STATUS", REG_MMIO, 0x1f34, 2, &mmHPD4_DC_HPD_INT_STATUS[0], sizeof(mmHPD4_DC_HPD_INT_STATUS)/sizeof(mmHPD4_DC_HPD_INT_STATUS[0]), 0, 0 }, + { "mmHPD4_DC_HPD_INT_CONTROL", REG_MMIO, 0x1f35, 2, &mmHPD4_DC_HPD_INT_CONTROL[0], sizeof(mmHPD4_DC_HPD_INT_CONTROL)/sizeof(mmHPD4_DC_HPD_INT_CONTROL[0]), 0, 0 }, + { "mmHPD4_DC_HPD_CONTROL", REG_MMIO, 0x1f36, 2, &mmHPD4_DC_HPD_CONTROL[0], sizeof(mmHPD4_DC_HPD_CONTROL)/sizeof(mmHPD4_DC_HPD_CONTROL[0]), 0, 0 }, + { "mmHPD4_DC_HPD_FAST_TRAIN_CNTL", REG_MMIO, 0x1f37, 2, &mmHPD4_DC_HPD_FAST_TRAIN_CNTL[0], sizeof(mmHPD4_DC_HPD_FAST_TRAIN_CNTL)/sizeof(mmHPD4_DC_HPD_FAST_TRAIN_CNTL[0]), 0, 0 }, + { "mmHPD4_DC_HPD_TOGGLE_FILT_CNTL", REG_MMIO, 0x1f38, 2, &mmHPD4_DC_HPD_TOGGLE_FILT_CNTL[0], sizeof(mmHPD4_DC_HPD_TOGGLE_FILT_CNTL)/sizeof(mmHPD4_DC_HPD_TOGGLE_FILT_CNTL[0]), 0, 0 }, + { "mmHPD5_DC_HPD_INT_STATUS", REG_MMIO, 0x1f3c, 2, &mmHPD5_DC_HPD_INT_STATUS[0], sizeof(mmHPD5_DC_HPD_INT_STATUS)/sizeof(mmHPD5_DC_HPD_INT_STATUS[0]), 0, 0 }, + { "mmHPD5_DC_HPD_INT_CONTROL", REG_MMIO, 0x1f3d, 2, &mmHPD5_DC_HPD_INT_CONTROL[0], sizeof(mmHPD5_DC_HPD_INT_CONTROL)/sizeof(mmHPD5_DC_HPD_INT_CONTROL[0]), 0, 0 }, + { "mmHPD5_DC_HPD_CONTROL", REG_MMIO, 0x1f3e, 2, &mmHPD5_DC_HPD_CONTROL[0], sizeof(mmHPD5_DC_HPD_CONTROL)/sizeof(mmHPD5_DC_HPD_CONTROL[0]), 0, 0 }, + { "mmHPD5_DC_HPD_FAST_TRAIN_CNTL", REG_MMIO, 0x1f3f, 2, &mmHPD5_DC_HPD_FAST_TRAIN_CNTL[0], sizeof(mmHPD5_DC_HPD_FAST_TRAIN_CNTL)/sizeof(mmHPD5_DC_HPD_FAST_TRAIN_CNTL[0]), 0, 0 }, + { "mmHPD5_DC_HPD_TOGGLE_FILT_CNTL", REG_MMIO, 0x1f40, 2, &mmHPD5_DC_HPD_TOGGLE_FILT_CNTL[0], sizeof(mmHPD5_DC_HPD_TOGGLE_FILT_CNTL)/sizeof(mmHPD5_DC_HPD_TOGGLE_FILT_CNTL[0]), 0, 0 }, + { "mmDC_PERFMON19_PERFCOUNTER_CNTL", REG_MMIO, 0x1f44, 2, &mmDC_PERFMON19_PERFCOUNTER_CNTL[0], sizeof(mmDC_PERFMON19_PERFCOUNTER_CNTL)/sizeof(mmDC_PERFMON19_PERFCOUNTER_CNTL[0]), 0, 0 }, + { "mmDC_PERFMON19_PERFCOUNTER_CNTL2", REG_MMIO, 0x1f45, 2, &mmDC_PERFMON19_PERFCOUNTER_CNTL2[0], sizeof(mmDC_PERFMON19_PERFCOUNTER_CNTL2)/sizeof(mmDC_PERFMON19_PERFCOUNTER_CNTL2[0]), 0, 0 }, + { "mmDC_PERFMON19_PERFCOUNTER_STATE", REG_MMIO, 0x1f46, 2, &mmDC_PERFMON19_PERFCOUNTER_STATE[0], sizeof(mmDC_PERFMON19_PERFCOUNTER_STATE)/sizeof(mmDC_PERFMON19_PERFCOUNTER_STATE[0]), 0, 0 }, + { "mmDC_PERFMON19_PERFMON_CNTL", REG_MMIO, 0x1f47, 2, &mmDC_PERFMON19_PERFMON_CNTL[0], sizeof(mmDC_PERFMON19_PERFMON_CNTL)/sizeof(mmDC_PERFMON19_PERFMON_CNTL[0]), 0, 0 }, + { "mmDC_PERFMON19_PERFMON_CNTL2", REG_MMIO, 0x1f48, 2, &mmDC_PERFMON19_PERFMON_CNTL2[0], sizeof(mmDC_PERFMON19_PERFMON_CNTL2)/sizeof(mmDC_PERFMON19_PERFMON_CNTL2[0]), 0, 0 }, + { "mmDC_PERFMON19_PERFMON_CVALUE_INT_MISC", REG_MMIO, 0x1f49, 2, &mmDC_PERFMON19_PERFMON_CVALUE_INT_MISC[0], sizeof(mmDC_PERFMON19_PERFMON_CVALUE_INT_MISC)/sizeof(mmDC_PERFMON19_PERFMON_CVALUE_INT_MISC[0]), 0, 0 }, + { "mmDC_PERFMON19_PERFMON_CVALUE_LOW", REG_MMIO, 0x1f4a, 2, &mmDC_PERFMON19_PERFMON_CVALUE_LOW[0], sizeof(mmDC_PERFMON19_PERFMON_CVALUE_LOW)/sizeof(mmDC_PERFMON19_PERFMON_CVALUE_LOW[0]), 0, 0 }, + { "mmDC_PERFMON19_PERFMON_HI", REG_MMIO, 0x1f4b, 2, &mmDC_PERFMON19_PERFMON_HI[0], sizeof(mmDC_PERFMON19_PERFMON_HI)/sizeof(mmDC_PERFMON19_PERFMON_HI[0]), 0, 0 }, + { "mmDC_PERFMON19_PERFMON_LOW", REG_MMIO, 0x1f4c, 2, &mmDC_PERFMON19_PERFMON_LOW[0], sizeof(mmDC_PERFMON19_PERFMON_LOW)/sizeof(mmDC_PERFMON19_PERFMON_LOW[0]), 0, 0 }, + { "mmDP_AUX0_AUX_CONTROL", REG_MMIO, 0x1f50, 2, &mmDP_AUX0_AUX_CONTROL[0], sizeof(mmDP_AUX0_AUX_CONTROL)/sizeof(mmDP_AUX0_AUX_CONTROL[0]), 0, 0 }, + { "mmDP_AUX0_AUX_SW_CONTROL", REG_MMIO, 0x1f51, 2, &mmDP_AUX0_AUX_SW_CONTROL[0], sizeof(mmDP_AUX0_AUX_SW_CONTROL)/sizeof(mmDP_AUX0_AUX_SW_CONTROL[0]), 0, 0 }, + { "mmDP_AUX0_AUX_ARB_CONTROL", REG_MMIO, 0x1f52, 2, &mmDP_AUX0_AUX_ARB_CONTROL[0], sizeof(mmDP_AUX0_AUX_ARB_CONTROL)/sizeof(mmDP_AUX0_AUX_ARB_CONTROL[0]), 0, 0 }, + { "mmDP_AUX0_AUX_INTERRUPT_CONTROL", REG_MMIO, 0x1f53, 2, &mmDP_AUX0_AUX_INTERRUPT_CONTROL[0], sizeof(mmDP_AUX0_AUX_INTERRUPT_CONTROL)/sizeof(mmDP_AUX0_AUX_INTERRUPT_CONTROL[0]), 0, 0 }, + { "mmDP_AUX0_AUX_SW_STATUS", REG_MMIO, 0x1f54, 2, &mmDP_AUX0_AUX_SW_STATUS[0], sizeof(mmDP_AUX0_AUX_SW_STATUS)/sizeof(mmDP_AUX0_AUX_SW_STATUS[0]), 0, 0 }, + { "mmDP_AUX0_AUX_LS_STATUS", REG_MMIO, 0x1f55, 2, &mmDP_AUX0_AUX_LS_STATUS[0], sizeof(mmDP_AUX0_AUX_LS_STATUS)/sizeof(mmDP_AUX0_AUX_LS_STATUS[0]), 0, 0 }, + { "mmDP_AUX0_AUX_SW_DATA", REG_MMIO, 0x1f56, 2, &mmDP_AUX0_AUX_SW_DATA[0], sizeof(mmDP_AUX0_AUX_SW_DATA)/sizeof(mmDP_AUX0_AUX_SW_DATA[0]), 0, 0 }, + { "mmDP_AUX0_AUX_LS_DATA", REG_MMIO, 0x1f57, 2, &mmDP_AUX0_AUX_LS_DATA[0], sizeof(mmDP_AUX0_AUX_LS_DATA)/sizeof(mmDP_AUX0_AUX_LS_DATA[0]), 0, 0 }, + { "mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL", REG_MMIO, 0x1f58, 2, &mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL[0], sizeof(mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL)/sizeof(mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL[0]), 0, 0 }, + { "mmDP_AUX0_AUX_DPHY_TX_CONTROL", REG_MMIO, 0x1f59, 2, &mmDP_AUX0_AUX_DPHY_TX_CONTROL[0], sizeof(mmDP_AUX0_AUX_DPHY_TX_CONTROL)/sizeof(mmDP_AUX0_AUX_DPHY_TX_CONTROL[0]), 0, 0 }, + { "mmDP_AUX0_AUX_DPHY_RX_CONTROL0", REG_MMIO, 0x1f5a, 2, &mmDP_AUX0_AUX_DPHY_RX_CONTROL0[0], sizeof(mmDP_AUX0_AUX_DPHY_RX_CONTROL0)/sizeof(mmDP_AUX0_AUX_DPHY_RX_CONTROL0[0]), 0, 0 }, + { "mmDP_AUX0_AUX_DPHY_RX_CONTROL1", REG_MMIO, 0x1f5b, 2, &mmDP_AUX0_AUX_DPHY_RX_CONTROL1[0], sizeof(mmDP_AUX0_AUX_DPHY_RX_CONTROL1)/sizeof(mmDP_AUX0_AUX_DPHY_RX_CONTROL1[0]), 0, 0 }, + { "mmDP_AUX0_AUX_DPHY_TX_STATUS", REG_MMIO, 0x1f5c, 2, &mmDP_AUX0_AUX_DPHY_TX_STATUS[0], sizeof(mmDP_AUX0_AUX_DPHY_TX_STATUS)/sizeof(mmDP_AUX0_AUX_DPHY_TX_STATUS[0]), 0, 0 }, + { "mmDP_AUX0_AUX_DPHY_RX_STATUS", REG_MMIO, 0x1f5d, 2, &mmDP_AUX0_AUX_DPHY_RX_STATUS[0], sizeof(mmDP_AUX0_AUX_DPHY_RX_STATUS)/sizeof(mmDP_AUX0_AUX_DPHY_RX_STATUS[0]), 0, 0 }, + { "mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL", REG_MMIO, 0x1f5f, 2, &mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL[0], sizeof(mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL)/sizeof(mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL[0]), 0, 0 }, + { "mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS", REG_MMIO, 0x1f60, 2, &mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS[0], sizeof(mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS)/sizeof(mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS[0]), 0, 0 }, + { "mmDP_AUX0_AUX_GTC_SYNC_STATUS", REG_MMIO, 0x1f61, 2, &mmDP_AUX0_AUX_GTC_SYNC_STATUS[0], sizeof(mmDP_AUX0_AUX_GTC_SYNC_STATUS)/sizeof(mmDP_AUX0_AUX_GTC_SYNC_STATUS[0]), 0, 0 }, + { "mmDP_AUX1_AUX_CONTROL", REG_MMIO, 0x1f6c, 2, &mmDP_AUX1_AUX_CONTROL[0], sizeof(mmDP_AUX1_AUX_CONTROL)/sizeof(mmDP_AUX1_AUX_CONTROL[0]), 0, 0 }, + { "mmDP_AUX1_AUX_SW_CONTROL", REG_MMIO, 0x1f6d, 2, &mmDP_AUX1_AUX_SW_CONTROL[0], sizeof(mmDP_AUX1_AUX_SW_CONTROL)/sizeof(mmDP_AUX1_AUX_SW_CONTROL[0]), 0, 0 }, + { "mmDP_AUX1_AUX_ARB_CONTROL", REG_MMIO, 0x1f6e, 2, &mmDP_AUX1_AUX_ARB_CONTROL[0], sizeof(mmDP_AUX1_AUX_ARB_CONTROL)/sizeof(mmDP_AUX1_AUX_ARB_CONTROL[0]), 0, 0 }, + { "mmDP_AUX1_AUX_INTERRUPT_CONTROL", REG_MMIO, 0x1f6f, 2, &mmDP_AUX1_AUX_INTERRUPT_CONTROL[0], sizeof(mmDP_AUX1_AUX_INTERRUPT_CONTROL)/sizeof(mmDP_AUX1_AUX_INTERRUPT_CONTROL[0]), 0, 0 }, + { "mmDP_AUX1_AUX_SW_STATUS", REG_MMIO, 0x1f70, 2, &mmDP_AUX1_AUX_SW_STATUS[0], sizeof(mmDP_AUX1_AUX_SW_STATUS)/sizeof(mmDP_AUX1_AUX_SW_STATUS[0]), 0, 0 }, + { "mmDP_AUX1_AUX_LS_STATUS", REG_MMIO, 0x1f71, 2, &mmDP_AUX1_AUX_LS_STATUS[0], sizeof(mmDP_AUX1_AUX_LS_STATUS)/sizeof(mmDP_AUX1_AUX_LS_STATUS[0]), 0, 0 }, + { "mmDP_AUX1_AUX_SW_DATA", REG_MMIO, 0x1f72, 2, &mmDP_AUX1_AUX_SW_DATA[0], sizeof(mmDP_AUX1_AUX_SW_DATA)/sizeof(mmDP_AUX1_AUX_SW_DATA[0]), 0, 0 }, + { "mmDP_AUX1_AUX_LS_DATA", REG_MMIO, 0x1f73, 2, &mmDP_AUX1_AUX_LS_DATA[0], sizeof(mmDP_AUX1_AUX_LS_DATA)/sizeof(mmDP_AUX1_AUX_LS_DATA[0]), 0, 0 }, + { "mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL", REG_MMIO, 0x1f74, 2, &mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL[0], sizeof(mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL)/sizeof(mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL[0]), 0, 0 }, + { "mmDP_AUX1_AUX_DPHY_TX_CONTROL", REG_MMIO, 0x1f75, 2, &mmDP_AUX1_AUX_DPHY_TX_CONTROL[0], sizeof(mmDP_AUX1_AUX_DPHY_TX_CONTROL)/sizeof(mmDP_AUX1_AUX_DPHY_TX_CONTROL[0]), 0, 0 }, + { "mmDP_AUX1_AUX_DPHY_RX_CONTROL0", REG_MMIO, 0x1f76, 2, &mmDP_AUX1_AUX_DPHY_RX_CONTROL0[0], sizeof(mmDP_AUX1_AUX_DPHY_RX_CONTROL0)/sizeof(mmDP_AUX1_AUX_DPHY_RX_CONTROL0[0]), 0, 0 }, + { "mmDP_AUX1_AUX_DPHY_RX_CONTROL1", REG_MMIO, 0x1f77, 2, &mmDP_AUX1_AUX_DPHY_RX_CONTROL1[0], sizeof(mmDP_AUX1_AUX_DPHY_RX_CONTROL1)/sizeof(mmDP_AUX1_AUX_DPHY_RX_CONTROL1[0]), 0, 0 }, + { "mmDP_AUX1_AUX_DPHY_TX_STATUS", REG_MMIO, 0x1f78, 2, &mmDP_AUX1_AUX_DPHY_TX_STATUS[0], sizeof(mmDP_AUX1_AUX_DPHY_TX_STATUS)/sizeof(mmDP_AUX1_AUX_DPHY_TX_STATUS[0]), 0, 0 }, + { "mmDP_AUX1_AUX_DPHY_RX_STATUS", REG_MMIO, 0x1f79, 2, &mmDP_AUX1_AUX_DPHY_RX_STATUS[0], sizeof(mmDP_AUX1_AUX_DPHY_RX_STATUS)/sizeof(mmDP_AUX1_AUX_DPHY_RX_STATUS[0]), 0, 0 }, + { "mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL", REG_MMIO, 0x1f7b, 2, &mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL[0], sizeof(mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL)/sizeof(mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL[0]), 0, 0 }, + { "mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS", REG_MMIO, 0x1f7c, 2, &mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS[0], sizeof(mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS)/sizeof(mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS[0]), 0, 0 }, + { "mmDP_AUX1_AUX_GTC_SYNC_STATUS", REG_MMIO, 0x1f7d, 2, &mmDP_AUX1_AUX_GTC_SYNC_STATUS[0], sizeof(mmDP_AUX1_AUX_GTC_SYNC_STATUS)/sizeof(mmDP_AUX1_AUX_GTC_SYNC_STATUS[0]), 0, 0 }, + { "mmDP_AUX2_AUX_CONTROL", REG_MMIO, 0x1f88, 2, &mmDP_AUX2_AUX_CONTROL[0], sizeof(mmDP_AUX2_AUX_CONTROL)/sizeof(mmDP_AUX2_AUX_CONTROL[0]), 0, 0 }, + { "mmDP_AUX2_AUX_SW_CONTROL", REG_MMIO, 0x1f89, 2, &mmDP_AUX2_AUX_SW_CONTROL[0], sizeof(mmDP_AUX2_AUX_SW_CONTROL)/sizeof(mmDP_AUX2_AUX_SW_CONTROL[0]), 0, 0 }, + { "mmDP_AUX2_AUX_ARB_CONTROL", REG_MMIO, 0x1f8a, 2, &mmDP_AUX2_AUX_ARB_CONTROL[0], sizeof(mmDP_AUX2_AUX_ARB_CONTROL)/sizeof(mmDP_AUX2_AUX_ARB_CONTROL[0]), 0, 0 }, + { "mmDP_AUX2_AUX_INTERRUPT_CONTROL", REG_MMIO, 0x1f8b, 2, &mmDP_AUX2_AUX_INTERRUPT_CONTROL[0], sizeof(mmDP_AUX2_AUX_INTERRUPT_CONTROL)/sizeof(mmDP_AUX2_AUX_INTERRUPT_CONTROL[0]), 0, 0 }, + { "mmDP_AUX2_AUX_SW_STATUS", REG_MMIO, 0x1f8c, 2, &mmDP_AUX2_AUX_SW_STATUS[0], sizeof(mmDP_AUX2_AUX_SW_STATUS)/sizeof(mmDP_AUX2_AUX_SW_STATUS[0]), 0, 0 }, + { "mmDP_AUX2_AUX_LS_STATUS", REG_MMIO, 0x1f8d, 2, &mmDP_AUX2_AUX_LS_STATUS[0], sizeof(mmDP_AUX2_AUX_LS_STATUS)/sizeof(mmDP_AUX2_AUX_LS_STATUS[0]), 0, 0 }, + { "mmDP_AUX2_AUX_SW_DATA", REG_MMIO, 0x1f8e, 2, &mmDP_AUX2_AUX_SW_DATA[0], sizeof(mmDP_AUX2_AUX_SW_DATA)/sizeof(mmDP_AUX2_AUX_SW_DATA[0]), 0, 0 }, + { "mmDP_AUX2_AUX_LS_DATA", REG_MMIO, 0x1f8f, 2, &mmDP_AUX2_AUX_LS_DATA[0], sizeof(mmDP_AUX2_AUX_LS_DATA)/sizeof(mmDP_AUX2_AUX_LS_DATA[0]), 0, 0 }, + { "mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL", REG_MMIO, 0x1f90, 2, &mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL[0], sizeof(mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL)/sizeof(mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL[0]), 0, 0 }, + { "mmDP_AUX2_AUX_DPHY_TX_CONTROL", REG_MMIO, 0x1f91, 2, &mmDP_AUX2_AUX_DPHY_TX_CONTROL[0], sizeof(mmDP_AUX2_AUX_DPHY_TX_CONTROL)/sizeof(mmDP_AUX2_AUX_DPHY_TX_CONTROL[0]), 0, 0 }, + { "mmDP_AUX2_AUX_DPHY_RX_CONTROL0", REG_MMIO, 0x1f92, 2, &mmDP_AUX2_AUX_DPHY_RX_CONTROL0[0], sizeof(mmDP_AUX2_AUX_DPHY_RX_CONTROL0)/sizeof(mmDP_AUX2_AUX_DPHY_RX_CONTROL0[0]), 0, 0 }, + { "mmDP_AUX2_AUX_DPHY_RX_CONTROL1", REG_MMIO, 0x1f93, 2, &mmDP_AUX2_AUX_DPHY_RX_CONTROL1[0], sizeof(mmDP_AUX2_AUX_DPHY_RX_CONTROL1)/sizeof(mmDP_AUX2_AUX_DPHY_RX_CONTROL1[0]), 0, 0 }, + { "mmDP_AUX2_AUX_DPHY_TX_STATUS", REG_MMIO, 0x1f94, 2, &mmDP_AUX2_AUX_DPHY_TX_STATUS[0], sizeof(mmDP_AUX2_AUX_DPHY_TX_STATUS)/sizeof(mmDP_AUX2_AUX_DPHY_TX_STATUS[0]), 0, 0 }, + { "mmDP_AUX2_AUX_DPHY_RX_STATUS", REG_MMIO, 0x1f95, 2, &mmDP_AUX2_AUX_DPHY_RX_STATUS[0], sizeof(mmDP_AUX2_AUX_DPHY_RX_STATUS)/sizeof(mmDP_AUX2_AUX_DPHY_RX_STATUS[0]), 0, 0 }, + { "mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL", REG_MMIO, 0x1f97, 2, &mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL[0], sizeof(mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL)/sizeof(mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL[0]), 0, 0 }, + { "mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS", REG_MMIO, 0x1f98, 2, &mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS[0], sizeof(mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS)/sizeof(mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS[0]), 0, 0 }, + { "mmDP_AUX2_AUX_GTC_SYNC_STATUS", REG_MMIO, 0x1f99, 2, &mmDP_AUX2_AUX_GTC_SYNC_STATUS[0], sizeof(mmDP_AUX2_AUX_GTC_SYNC_STATUS)/sizeof(mmDP_AUX2_AUX_GTC_SYNC_STATUS[0]), 0, 0 }, + { "mmDP_AUX3_AUX_CONTROL", REG_MMIO, 0x1fa4, 2, &mmDP_AUX3_AUX_CONTROL[0], sizeof(mmDP_AUX3_AUX_CONTROL)/sizeof(mmDP_AUX3_AUX_CONTROL[0]), 0, 0 }, + { "mmDP_AUX3_AUX_SW_CONTROL", REG_MMIO, 0x1fa5, 2, &mmDP_AUX3_AUX_SW_CONTROL[0], sizeof(mmDP_AUX3_AUX_SW_CONTROL)/sizeof(mmDP_AUX3_AUX_SW_CONTROL[0]), 0, 0 }, + { "mmDP_AUX3_AUX_ARB_CONTROL", REG_MMIO, 0x1fa6, 2, &mmDP_AUX3_AUX_ARB_CONTROL[0], sizeof(mmDP_AUX3_AUX_ARB_CONTROL)/sizeof(mmDP_AUX3_AUX_ARB_CONTROL[0]), 0, 0 }, + { "mmDP_AUX3_AUX_INTERRUPT_CONTROL", REG_MMIO, 0x1fa7, 2, &mmDP_AUX3_AUX_INTERRUPT_CONTROL[0], sizeof(mmDP_AUX3_AUX_INTERRUPT_CONTROL)/sizeof(mmDP_AUX3_AUX_INTERRUPT_CONTROL[0]), 0, 0 }, + { "mmDP_AUX3_AUX_SW_STATUS", REG_MMIO, 0x1fa8, 2, &mmDP_AUX3_AUX_SW_STATUS[0], sizeof(mmDP_AUX3_AUX_SW_STATUS)/sizeof(mmDP_AUX3_AUX_SW_STATUS[0]), 0, 0 }, + { "mmDP_AUX3_AUX_LS_STATUS", REG_MMIO, 0x1fa9, 2, &mmDP_AUX3_AUX_LS_STATUS[0], sizeof(mmDP_AUX3_AUX_LS_STATUS)/sizeof(mmDP_AUX3_AUX_LS_STATUS[0]), 0, 0 }, + { "mmDP_AUX3_AUX_SW_DATA", REG_MMIO, 0x1faa, 2, &mmDP_AUX3_AUX_SW_DATA[0], sizeof(mmDP_AUX3_AUX_SW_DATA)/sizeof(mmDP_AUX3_AUX_SW_DATA[0]), 0, 0 }, + { "mmDP_AUX3_AUX_LS_DATA", REG_MMIO, 0x1fab, 2, &mmDP_AUX3_AUX_LS_DATA[0], sizeof(mmDP_AUX3_AUX_LS_DATA)/sizeof(mmDP_AUX3_AUX_LS_DATA[0]), 0, 0 }, + { "mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL", REG_MMIO, 0x1fac, 2, &mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL[0], sizeof(mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL)/sizeof(mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL[0]), 0, 0 }, + { "mmDP_AUX3_AUX_DPHY_TX_CONTROL", REG_MMIO, 0x1fad, 2, &mmDP_AUX3_AUX_DPHY_TX_CONTROL[0], sizeof(mmDP_AUX3_AUX_DPHY_TX_CONTROL)/sizeof(mmDP_AUX3_AUX_DPHY_TX_CONTROL[0]), 0, 0 }, + { "mmDP_AUX3_AUX_DPHY_RX_CONTROL0", REG_MMIO, 0x1fae, 2, &mmDP_AUX3_AUX_DPHY_RX_CONTROL0[0], sizeof(mmDP_AUX3_AUX_DPHY_RX_CONTROL0)/sizeof(mmDP_AUX3_AUX_DPHY_RX_CONTROL0[0]), 0, 0 }, + { "mmDP_AUX3_AUX_DPHY_RX_CONTROL1", REG_MMIO, 0x1faf, 2, &mmDP_AUX3_AUX_DPHY_RX_CONTROL1[0], sizeof(mmDP_AUX3_AUX_DPHY_RX_CONTROL1)/sizeof(mmDP_AUX3_AUX_DPHY_RX_CONTROL1[0]), 0, 0 }, + { "mmDP_AUX3_AUX_DPHY_TX_STATUS", REG_MMIO, 0x1fb0, 2, &mmDP_AUX3_AUX_DPHY_TX_STATUS[0], sizeof(mmDP_AUX3_AUX_DPHY_TX_STATUS)/sizeof(mmDP_AUX3_AUX_DPHY_TX_STATUS[0]), 0, 0 }, + { "mmDP_AUX3_AUX_DPHY_RX_STATUS", REG_MMIO, 0x1fb1, 2, &mmDP_AUX3_AUX_DPHY_RX_STATUS[0], sizeof(mmDP_AUX3_AUX_DPHY_RX_STATUS)/sizeof(mmDP_AUX3_AUX_DPHY_RX_STATUS[0]), 0, 0 }, + { "mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL", REG_MMIO, 0x1fb3, 2, &mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL[0], sizeof(mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL)/sizeof(mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL[0]), 0, 0 }, + { "mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS", REG_MMIO, 0x1fb4, 2, &mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS[0], sizeof(mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS)/sizeof(mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS[0]), 0, 0 }, + { "mmDP_AUX3_AUX_GTC_SYNC_STATUS", REG_MMIO, 0x1fb5, 2, &mmDP_AUX3_AUX_GTC_SYNC_STATUS[0], sizeof(mmDP_AUX3_AUX_GTC_SYNC_STATUS)/sizeof(mmDP_AUX3_AUX_GTC_SYNC_STATUS[0]), 0, 0 }, + { "mmDP_AUX4_AUX_CONTROL", REG_MMIO, 0x1fc0, 2, &mmDP_AUX4_AUX_CONTROL[0], sizeof(mmDP_AUX4_AUX_CONTROL)/sizeof(mmDP_AUX4_AUX_CONTROL[0]), 0, 0 }, + { "mmDP_AUX4_AUX_SW_CONTROL", REG_MMIO, 0x1fc1, 2, &mmDP_AUX4_AUX_SW_CONTROL[0], sizeof(mmDP_AUX4_AUX_SW_CONTROL)/sizeof(mmDP_AUX4_AUX_SW_CONTROL[0]), 0, 0 }, + { "mmDP_AUX4_AUX_ARB_CONTROL", REG_MMIO, 0x1fc2, 2, &mmDP_AUX4_AUX_ARB_CONTROL[0], sizeof(mmDP_AUX4_AUX_ARB_CONTROL)/sizeof(mmDP_AUX4_AUX_ARB_CONTROL[0]), 0, 0 }, + { "mmDP_AUX4_AUX_INTERRUPT_CONTROL", REG_MMIO, 0x1fc3, 2, &mmDP_AUX4_AUX_INTERRUPT_CONTROL[0], sizeof(mmDP_AUX4_AUX_INTERRUPT_CONTROL)/sizeof(mmDP_AUX4_AUX_INTERRUPT_CONTROL[0]), 0, 0 }, + { "mmDP_AUX4_AUX_SW_STATUS", REG_MMIO, 0x1fc4, 2, &mmDP_AUX4_AUX_SW_STATUS[0], sizeof(mmDP_AUX4_AUX_SW_STATUS)/sizeof(mmDP_AUX4_AUX_SW_STATUS[0]), 0, 0 }, + { "mmDP_AUX4_AUX_LS_STATUS", REG_MMIO, 0x1fc5, 2, &mmDP_AUX4_AUX_LS_STATUS[0], sizeof(mmDP_AUX4_AUX_LS_STATUS)/sizeof(mmDP_AUX4_AUX_LS_STATUS[0]), 0, 0 }, + { "mmDP_AUX4_AUX_SW_DATA", REG_MMIO, 0x1fc6, 2, &mmDP_AUX4_AUX_SW_DATA[0], sizeof(mmDP_AUX4_AUX_SW_DATA)/sizeof(mmDP_AUX4_AUX_SW_DATA[0]), 0, 0 }, + { "mmDP_AUX4_AUX_LS_DATA", REG_MMIO, 0x1fc7, 2, &mmDP_AUX4_AUX_LS_DATA[0], sizeof(mmDP_AUX4_AUX_LS_DATA)/sizeof(mmDP_AUX4_AUX_LS_DATA[0]), 0, 0 }, + { "mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL", REG_MMIO, 0x1fc8, 2, &mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL[0], sizeof(mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL)/sizeof(mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL[0]), 0, 0 }, + { "mmDP_AUX4_AUX_DPHY_TX_CONTROL", REG_MMIO, 0x1fc9, 2, &mmDP_AUX4_AUX_DPHY_TX_CONTROL[0], sizeof(mmDP_AUX4_AUX_DPHY_TX_CONTROL)/sizeof(mmDP_AUX4_AUX_DPHY_TX_CONTROL[0]), 0, 0 }, + { "mmDP_AUX4_AUX_DPHY_RX_CONTROL0", REG_MMIO, 0x1fca, 2, &mmDP_AUX4_AUX_DPHY_RX_CONTROL0[0], sizeof(mmDP_AUX4_AUX_DPHY_RX_CONTROL0)/sizeof(mmDP_AUX4_AUX_DPHY_RX_CONTROL0[0]), 0, 0 }, + { "mmDP_AUX4_AUX_DPHY_RX_CONTROL1", REG_MMIO, 0x1fcb, 2, &mmDP_AUX4_AUX_DPHY_RX_CONTROL1[0], sizeof(mmDP_AUX4_AUX_DPHY_RX_CONTROL1)/sizeof(mmDP_AUX4_AUX_DPHY_RX_CONTROL1[0]), 0, 0 }, + { "mmDP_AUX4_AUX_DPHY_TX_STATUS", REG_MMIO, 0x1fcc, 2, &mmDP_AUX4_AUX_DPHY_TX_STATUS[0], sizeof(mmDP_AUX4_AUX_DPHY_TX_STATUS)/sizeof(mmDP_AUX4_AUX_DPHY_TX_STATUS[0]), 0, 0 }, + { "mmDP_AUX4_AUX_DPHY_RX_STATUS", REG_MMIO, 0x1fcd, 2, &mmDP_AUX4_AUX_DPHY_RX_STATUS[0], sizeof(mmDP_AUX4_AUX_DPHY_RX_STATUS)/sizeof(mmDP_AUX4_AUX_DPHY_RX_STATUS[0]), 0, 0 }, + { "mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL", REG_MMIO, 0x1fcf, 2, &mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL[0], sizeof(mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL)/sizeof(mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL[0]), 0, 0 }, + { "mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS", REG_MMIO, 0x1fd0, 2, &mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS[0], sizeof(mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS)/sizeof(mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS[0]), 0, 0 }, + { "mmDP_AUX4_AUX_GTC_SYNC_STATUS", REG_MMIO, 0x1fd1, 2, &mmDP_AUX4_AUX_GTC_SYNC_STATUS[0], sizeof(mmDP_AUX4_AUX_GTC_SYNC_STATUS)/sizeof(mmDP_AUX4_AUX_GTC_SYNC_STATUS[0]), 0, 0 }, + { "mmDP_AUX5_AUX_CONTROL", REG_MMIO, 0x1fdc, 2, &mmDP_AUX5_AUX_CONTROL[0], sizeof(mmDP_AUX5_AUX_CONTROL)/sizeof(mmDP_AUX5_AUX_CONTROL[0]), 0, 0 }, + { "mmDP_AUX5_AUX_SW_CONTROL", REG_MMIO, 0x1fdd, 2, &mmDP_AUX5_AUX_SW_CONTROL[0], sizeof(mmDP_AUX5_AUX_SW_CONTROL)/sizeof(mmDP_AUX5_AUX_SW_CONTROL[0]), 0, 0 }, + { "mmDP_AUX5_AUX_ARB_CONTROL", REG_MMIO, 0x1fde, 2, &mmDP_AUX5_AUX_ARB_CONTROL[0], sizeof(mmDP_AUX5_AUX_ARB_CONTROL)/sizeof(mmDP_AUX5_AUX_ARB_CONTROL[0]), 0, 0 }, + { "mmDP_AUX5_AUX_INTERRUPT_CONTROL", REG_MMIO, 0x1fdf, 2, &mmDP_AUX5_AUX_INTERRUPT_CONTROL[0], sizeof(mmDP_AUX5_AUX_INTERRUPT_CONTROL)/sizeof(mmDP_AUX5_AUX_INTERRUPT_CONTROL[0]), 0, 0 }, + { "mmDP_AUX5_AUX_SW_STATUS", REG_MMIO, 0x1fe0, 2, &mmDP_AUX5_AUX_SW_STATUS[0], sizeof(mmDP_AUX5_AUX_SW_STATUS)/sizeof(mmDP_AUX5_AUX_SW_STATUS[0]), 0, 0 }, + { "mmDP_AUX5_AUX_LS_STATUS", REG_MMIO, 0x1fe1, 2, &mmDP_AUX5_AUX_LS_STATUS[0], sizeof(mmDP_AUX5_AUX_LS_STATUS)/sizeof(mmDP_AUX5_AUX_LS_STATUS[0]), 0, 0 }, + { "mmDP_AUX5_AUX_SW_DATA", REG_MMIO, 0x1fe2, 2, &mmDP_AUX5_AUX_SW_DATA[0], sizeof(mmDP_AUX5_AUX_SW_DATA)/sizeof(mmDP_AUX5_AUX_SW_DATA[0]), 0, 0 }, + { "mmDP_AUX5_AUX_LS_DATA", REG_MMIO, 0x1fe3, 2, &mmDP_AUX5_AUX_LS_DATA[0], sizeof(mmDP_AUX5_AUX_LS_DATA)/sizeof(mmDP_AUX5_AUX_LS_DATA[0]), 0, 0 }, + { "mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL", REG_MMIO, 0x1fe4, 2, &mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL[0], sizeof(mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL)/sizeof(mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL[0]), 0, 0 }, + { "mmDP_AUX5_AUX_DPHY_TX_CONTROL", REG_MMIO, 0x1fe5, 2, &mmDP_AUX5_AUX_DPHY_TX_CONTROL[0], sizeof(mmDP_AUX5_AUX_DPHY_TX_CONTROL)/sizeof(mmDP_AUX5_AUX_DPHY_TX_CONTROL[0]), 0, 0 }, + { "mmDP_AUX5_AUX_DPHY_RX_CONTROL0", REG_MMIO, 0x1fe6, 2, &mmDP_AUX5_AUX_DPHY_RX_CONTROL0[0], sizeof(mmDP_AUX5_AUX_DPHY_RX_CONTROL0)/sizeof(mmDP_AUX5_AUX_DPHY_RX_CONTROL0[0]), 0, 0 }, + { "mmDP_AUX5_AUX_DPHY_RX_CONTROL1", REG_MMIO, 0x1fe7, 2, &mmDP_AUX5_AUX_DPHY_RX_CONTROL1[0], sizeof(mmDP_AUX5_AUX_DPHY_RX_CONTROL1)/sizeof(mmDP_AUX5_AUX_DPHY_RX_CONTROL1[0]), 0, 0 }, + { "mmDP_AUX5_AUX_DPHY_TX_STATUS", REG_MMIO, 0x1fe8, 2, &mmDP_AUX5_AUX_DPHY_TX_STATUS[0], sizeof(mmDP_AUX5_AUX_DPHY_TX_STATUS)/sizeof(mmDP_AUX5_AUX_DPHY_TX_STATUS[0]), 0, 0 }, + { "mmDP_AUX5_AUX_DPHY_RX_STATUS", REG_MMIO, 0x1fe9, 2, &mmDP_AUX5_AUX_DPHY_RX_STATUS[0], sizeof(mmDP_AUX5_AUX_DPHY_RX_STATUS)/sizeof(mmDP_AUX5_AUX_DPHY_RX_STATUS[0]), 0, 0 }, + { "mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL", REG_MMIO, 0x1feb, 2, &mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL[0], sizeof(mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL)/sizeof(mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL[0]), 0, 0 }, + { "mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS", REG_MMIO, 0x1fec, 2, &mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS[0], sizeof(mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS)/sizeof(mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS[0]), 0, 0 }, + { "mmDP_AUX5_AUX_GTC_SYNC_STATUS", REG_MMIO, 0x1fed, 2, &mmDP_AUX5_AUX_GTC_SYNC_STATUS[0], sizeof(mmDP_AUX5_AUX_GTC_SYNC_STATUS)/sizeof(mmDP_AUX5_AUX_GTC_SYNC_STATUS[0]), 0, 0 }, + { "mmDP_AUX6_AUX_CONTROL", REG_MMIO, 0x1ff8, 2, &mmDP_AUX6_AUX_CONTROL[0], sizeof(mmDP_AUX6_AUX_CONTROL)/sizeof(mmDP_AUX6_AUX_CONTROL[0]), 0, 0 }, + { "mmDP_AUX6_AUX_SW_CONTROL", REG_MMIO, 0x1ff9, 2, &mmDP_AUX6_AUX_SW_CONTROL[0], sizeof(mmDP_AUX6_AUX_SW_CONTROL)/sizeof(mmDP_AUX6_AUX_SW_CONTROL[0]), 0, 0 }, + { "mmDP_AUX6_AUX_ARB_CONTROL", REG_MMIO, 0x1ffa, 2, &mmDP_AUX6_AUX_ARB_CONTROL[0], sizeof(mmDP_AUX6_AUX_ARB_CONTROL)/sizeof(mmDP_AUX6_AUX_ARB_CONTROL[0]), 0, 0 }, + { "mmDP_AUX6_AUX_INTERRUPT_CONTROL", REG_MMIO, 0x1ffb, 2, &mmDP_AUX6_AUX_INTERRUPT_CONTROL[0], sizeof(mmDP_AUX6_AUX_INTERRUPT_CONTROL)/sizeof(mmDP_AUX6_AUX_INTERRUPT_CONTROL[0]), 0, 0 }, + { "mmDP_AUX6_AUX_SW_STATUS", REG_MMIO, 0x1ffc, 2, &mmDP_AUX6_AUX_SW_STATUS[0], sizeof(mmDP_AUX6_AUX_SW_STATUS)/sizeof(mmDP_AUX6_AUX_SW_STATUS[0]), 0, 0 }, + { "mmDP_AUX6_AUX_LS_STATUS", REG_MMIO, 0x1ffd, 2, &mmDP_AUX6_AUX_LS_STATUS[0], sizeof(mmDP_AUX6_AUX_LS_STATUS)/sizeof(mmDP_AUX6_AUX_LS_STATUS[0]), 0, 0 }, + { "mmDP_AUX6_AUX_SW_DATA", REG_MMIO, 0x1ffe, 2, &mmDP_AUX6_AUX_SW_DATA[0], sizeof(mmDP_AUX6_AUX_SW_DATA)/sizeof(mmDP_AUX6_AUX_SW_DATA[0]), 0, 0 }, + { "mmDP_AUX6_AUX_LS_DATA", REG_MMIO, 0x1fff, 2, &mmDP_AUX6_AUX_LS_DATA[0], sizeof(mmDP_AUX6_AUX_LS_DATA)/sizeof(mmDP_AUX6_AUX_LS_DATA[0]), 0, 0 }, + { "mmDP_AUX6_AUX_DPHY_TX_REF_CONTROL", REG_MMIO, 0x2000, 2, &mmDP_AUX6_AUX_DPHY_TX_REF_CONTROL[0], sizeof(mmDP_AUX6_AUX_DPHY_TX_REF_CONTROL)/sizeof(mmDP_AUX6_AUX_DPHY_TX_REF_CONTROL[0]), 0, 0 }, + { "mmDP_AUX6_AUX_DPHY_TX_CONTROL", REG_MMIO, 0x2001, 2, &mmDP_AUX6_AUX_DPHY_TX_CONTROL[0], sizeof(mmDP_AUX6_AUX_DPHY_TX_CONTROL)/sizeof(mmDP_AUX6_AUX_DPHY_TX_CONTROL[0]), 0, 0 }, + { "mmDP_AUX6_AUX_DPHY_RX_CONTROL0", REG_MMIO, 0x2002, 2, &mmDP_AUX6_AUX_DPHY_RX_CONTROL0[0], sizeof(mmDP_AUX6_AUX_DPHY_RX_CONTROL0)/sizeof(mmDP_AUX6_AUX_DPHY_RX_CONTROL0[0]), 0, 0 }, + { "mmDP_AUX6_AUX_DPHY_RX_CONTROL1", REG_MMIO, 0x2003, 2, &mmDP_AUX6_AUX_DPHY_RX_CONTROL1[0], sizeof(mmDP_AUX6_AUX_DPHY_RX_CONTROL1)/sizeof(mmDP_AUX6_AUX_DPHY_RX_CONTROL1[0]), 0, 0 }, + { "mmDP_AUX6_AUX_DPHY_TX_STATUS", REG_MMIO, 0x2004, 2, &mmDP_AUX6_AUX_DPHY_TX_STATUS[0], sizeof(mmDP_AUX6_AUX_DPHY_TX_STATUS)/sizeof(mmDP_AUX6_AUX_DPHY_TX_STATUS[0]), 0, 0 }, + { "mmDP_AUX6_AUX_DPHY_RX_STATUS", REG_MMIO, 0x2005, 2, &mmDP_AUX6_AUX_DPHY_RX_STATUS[0], sizeof(mmDP_AUX6_AUX_DPHY_RX_STATUS)/sizeof(mmDP_AUX6_AUX_DPHY_RX_STATUS[0]), 0, 0 }, + { "mmDP_AUX6_AUX_GTC_SYNC_ERROR_CONTROL", REG_MMIO, 0x2007, 2, &mmDP_AUX6_AUX_GTC_SYNC_ERROR_CONTROL[0], sizeof(mmDP_AUX6_AUX_GTC_SYNC_ERROR_CONTROL)/sizeof(mmDP_AUX6_AUX_GTC_SYNC_ERROR_CONTROL[0]), 0, 0 }, + { "mmDP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS", REG_MMIO, 0x2008, 2, &mmDP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS[0], sizeof(mmDP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS)/sizeof(mmDP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS[0]), 0, 0 }, + { "mmDP_AUX6_AUX_GTC_SYNC_STATUS", REG_MMIO, 0x2009, 2, &mmDP_AUX6_AUX_GTC_SYNC_STATUS[0], sizeof(mmDP_AUX6_AUX_GTC_SYNC_STATUS)/sizeof(mmDP_AUX6_AUX_GTC_SYNC_STATUS[0]), 0, 0 }, + { "mmDIG0_DIG_FE_CNTL", REG_MMIO, 0x2068, 2, &mmDIG0_DIG_FE_CNTL[0], sizeof(mmDIG0_DIG_FE_CNTL)/sizeof(mmDIG0_DIG_FE_CNTL[0]), 0, 0 }, + { "mmDIG0_DIG_OUTPUT_CRC_CNTL", REG_MMIO, 0x2069, 2, &mmDIG0_DIG_OUTPUT_CRC_CNTL[0], sizeof(mmDIG0_DIG_OUTPUT_CRC_CNTL)/sizeof(mmDIG0_DIG_OUTPUT_CRC_CNTL[0]), 0, 0 }, + { "mmDIG0_DIG_OUTPUT_CRC_RESULT", REG_MMIO, 0x206a, 2, &mmDIG0_DIG_OUTPUT_CRC_RESULT[0], sizeof(mmDIG0_DIG_OUTPUT_CRC_RESULT)/sizeof(mmDIG0_DIG_OUTPUT_CRC_RESULT[0]), 0, 0 }, + { "mmDIG0_DIG_CLOCK_PATTERN", REG_MMIO, 0x206b, 2, &mmDIG0_DIG_CLOCK_PATTERN[0], sizeof(mmDIG0_DIG_CLOCK_PATTERN)/sizeof(mmDIG0_DIG_CLOCK_PATTERN[0]), 0, 0 }, + { "mmDIG0_DIG_TEST_PATTERN", REG_MMIO, 0x206c, 2, &mmDIG0_DIG_TEST_PATTERN[0], sizeof(mmDIG0_DIG_TEST_PATTERN)/sizeof(mmDIG0_DIG_TEST_PATTERN[0]), 0, 0 }, + { "mmDIG0_DIG_RANDOM_PATTERN_SEED", REG_MMIO, 0x206d, 2, &mmDIG0_DIG_RANDOM_PATTERN_SEED[0], sizeof(mmDIG0_DIG_RANDOM_PATTERN_SEED)/sizeof(mmDIG0_DIG_RANDOM_PATTERN_SEED[0]), 0, 0 }, + { "mmDIG0_DIG_FIFO_STATUS", REG_MMIO, 0x206e, 2, &mmDIG0_DIG_FIFO_STATUS[0], sizeof(mmDIG0_DIG_FIFO_STATUS)/sizeof(mmDIG0_DIG_FIFO_STATUS[0]), 0, 0 }, + { "mmDIG0_HDMI_CONTROL", REG_MMIO, 0x2071, 2, &mmDIG0_HDMI_CONTROL[0], sizeof(mmDIG0_HDMI_CONTROL)/sizeof(mmDIG0_HDMI_CONTROL[0]), 0, 0 }, + { "mmDIG0_HDMI_STATUS", REG_MMIO, 0x2072, 2, &mmDIG0_HDMI_STATUS[0], sizeof(mmDIG0_HDMI_STATUS)/sizeof(mmDIG0_HDMI_STATUS[0]), 0, 0 }, + { "mmDIG0_HDMI_AUDIO_PACKET_CONTROL", REG_MMIO, 0x2073, 2, &mmDIG0_HDMI_AUDIO_PACKET_CONTROL[0], sizeof(mmDIG0_HDMI_AUDIO_PACKET_CONTROL)/sizeof(mmDIG0_HDMI_AUDIO_PACKET_CONTROL[0]), 0, 0 }, + { "mmDIG0_HDMI_ACR_PACKET_CONTROL", REG_MMIO, 0x2074, 2, &mmDIG0_HDMI_ACR_PACKET_CONTROL[0], sizeof(mmDIG0_HDMI_ACR_PACKET_CONTROL)/sizeof(mmDIG0_HDMI_ACR_PACKET_CONTROL[0]), 0, 0 }, + { "mmDIG0_HDMI_VBI_PACKET_CONTROL", REG_MMIO, 0x2075, 2, &mmDIG0_HDMI_VBI_PACKET_CONTROL[0], sizeof(mmDIG0_HDMI_VBI_PACKET_CONTROL)/sizeof(mmDIG0_HDMI_VBI_PACKET_CONTROL[0]), 0, 0 }, + { "mmDIG0_HDMI_INFOFRAME_CONTROL0", REG_MMIO, 0x2076, 2, &mmDIG0_HDMI_INFOFRAME_CONTROL0[0], sizeof(mmDIG0_HDMI_INFOFRAME_CONTROL0)/sizeof(mmDIG0_HDMI_INFOFRAME_CONTROL0[0]), 0, 0 }, + { "mmDIG0_HDMI_INFOFRAME_CONTROL1", REG_MMIO, 0x2077, 2, &mmDIG0_HDMI_INFOFRAME_CONTROL1[0], sizeof(mmDIG0_HDMI_INFOFRAME_CONTROL1)/sizeof(mmDIG0_HDMI_INFOFRAME_CONTROL1[0]), 0, 0 }, + { "mmDIG0_HDMI_GENERIC_PACKET_CONTROL0", REG_MMIO, 0x2078, 2, &mmDIG0_HDMI_GENERIC_PACKET_CONTROL0[0], sizeof(mmDIG0_HDMI_GENERIC_PACKET_CONTROL0)/sizeof(mmDIG0_HDMI_GENERIC_PACKET_CONTROL0[0]), 0, 0 }, + { "mmDIG0_AFMT_INTERRUPT_STATUS", REG_MMIO, 0x2079, 2, NULL, 0, 0, 0 }, + { "mmDIG0_HDMI_GC", REG_MMIO, 0x207b, 2, &mmDIG0_HDMI_GC[0], sizeof(mmDIG0_HDMI_GC)/sizeof(mmDIG0_HDMI_GC[0]), 0, 0 }, + { "mmDIG0_AFMT_AUDIO_PACKET_CONTROL2", REG_MMIO, 0x207c, 2, &mmDIG0_AFMT_AUDIO_PACKET_CONTROL2[0], sizeof(mmDIG0_AFMT_AUDIO_PACKET_CONTROL2)/sizeof(mmDIG0_AFMT_AUDIO_PACKET_CONTROL2[0]), 0, 0 }, + { "mmDIG0_AFMT_ISRC1_0", REG_MMIO, 0x207d, 2, &mmDIG0_AFMT_ISRC1_0[0], sizeof(mmDIG0_AFMT_ISRC1_0)/sizeof(mmDIG0_AFMT_ISRC1_0[0]), 0, 0 }, + { "mmDIG0_AFMT_ISRC1_1", REG_MMIO, 0x207e, 2, &mmDIG0_AFMT_ISRC1_1[0], sizeof(mmDIG0_AFMT_ISRC1_1)/sizeof(mmDIG0_AFMT_ISRC1_1[0]), 0, 0 }, + { "mmDIG0_AFMT_ISRC1_2", REG_MMIO, 0x207f, 2, &mmDIG0_AFMT_ISRC1_2[0], sizeof(mmDIG0_AFMT_ISRC1_2)/sizeof(mmDIG0_AFMT_ISRC1_2[0]), 0, 0 }, + { "mmDIG0_AFMT_ISRC1_3", REG_MMIO, 0x2080, 2, &mmDIG0_AFMT_ISRC1_3[0], sizeof(mmDIG0_AFMT_ISRC1_3)/sizeof(mmDIG0_AFMT_ISRC1_3[0]), 0, 0 }, + { "mmDIG0_AFMT_ISRC1_4", REG_MMIO, 0x2081, 2, &mmDIG0_AFMT_ISRC1_4[0], sizeof(mmDIG0_AFMT_ISRC1_4)/sizeof(mmDIG0_AFMT_ISRC1_4[0]), 0, 0 }, + { "mmDIG0_AFMT_ISRC2_0", REG_MMIO, 0x2082, 2, &mmDIG0_AFMT_ISRC2_0[0], sizeof(mmDIG0_AFMT_ISRC2_0)/sizeof(mmDIG0_AFMT_ISRC2_0[0]), 0, 0 }, + { "mmDIG0_AFMT_ISRC2_1", REG_MMIO, 0x2083, 2, &mmDIG0_AFMT_ISRC2_1[0], sizeof(mmDIG0_AFMT_ISRC2_1)/sizeof(mmDIG0_AFMT_ISRC2_1[0]), 0, 0 }, + { "mmDIG0_AFMT_ISRC2_2", REG_MMIO, 0x2084, 2, &mmDIG0_AFMT_ISRC2_2[0], sizeof(mmDIG0_AFMT_ISRC2_2)/sizeof(mmDIG0_AFMT_ISRC2_2[0]), 0, 0 }, + { "mmDIG0_AFMT_ISRC2_3", REG_MMIO, 0x2085, 2, &mmDIG0_AFMT_ISRC2_3[0], sizeof(mmDIG0_AFMT_ISRC2_3)/sizeof(mmDIG0_AFMT_ISRC2_3[0]), 0, 0 }, + { "mmDIG0_HDMI_GENERIC_PACKET_CONTROL2", REG_MMIO, 0x2086, 2, &mmDIG0_HDMI_GENERIC_PACKET_CONTROL2[0], sizeof(mmDIG0_HDMI_GENERIC_PACKET_CONTROL2)/sizeof(mmDIG0_HDMI_GENERIC_PACKET_CONTROL2[0]), 0, 0 }, + { "mmDIG0_HDMI_GENERIC_PACKET_CONTROL3", REG_MMIO, 0x2087, 2, &mmDIG0_HDMI_GENERIC_PACKET_CONTROL3[0], sizeof(mmDIG0_HDMI_GENERIC_PACKET_CONTROL3)/sizeof(mmDIG0_HDMI_GENERIC_PACKET_CONTROL3[0]), 0, 0 }, + { "mmDIG0_HDMI_DB_CONTROL", REG_MMIO, 0x2088, 2, &mmDIG0_HDMI_DB_CONTROL[0], sizeof(mmDIG0_HDMI_DB_CONTROL)/sizeof(mmDIG0_HDMI_DB_CONTROL[0]), 0, 0 }, + { "mmDIG0_AFMT_MPEG_INFO0", REG_MMIO, 0x208a, 2, &mmDIG0_AFMT_MPEG_INFO0[0], sizeof(mmDIG0_AFMT_MPEG_INFO0)/sizeof(mmDIG0_AFMT_MPEG_INFO0[0]), 0, 0 }, + { "mmDIG0_AFMT_MPEG_INFO1", REG_MMIO, 0x208b, 2, &mmDIG0_AFMT_MPEG_INFO1[0], sizeof(mmDIG0_AFMT_MPEG_INFO1)/sizeof(mmDIG0_AFMT_MPEG_INFO1[0]), 0, 0 }, + { "mmDIG0_AFMT_GENERIC_HDR", REG_MMIO, 0x208c, 2, &mmDIG0_AFMT_GENERIC_HDR[0], sizeof(mmDIG0_AFMT_GENERIC_HDR)/sizeof(mmDIG0_AFMT_GENERIC_HDR[0]), 0, 0 }, + { "mmDIG0_AFMT_GENERIC_0", REG_MMIO, 0x208d, 2, &mmDIG0_AFMT_GENERIC_0[0], sizeof(mmDIG0_AFMT_GENERIC_0)/sizeof(mmDIG0_AFMT_GENERIC_0[0]), 0, 0 }, + { "mmDIG0_AFMT_GENERIC_1", REG_MMIO, 0x208e, 2, &mmDIG0_AFMT_GENERIC_1[0], sizeof(mmDIG0_AFMT_GENERIC_1)/sizeof(mmDIG0_AFMT_GENERIC_1[0]), 0, 0 }, + { "mmDIG0_AFMT_GENERIC_2", REG_MMIO, 0x208f, 2, &mmDIG0_AFMT_GENERIC_2[0], sizeof(mmDIG0_AFMT_GENERIC_2)/sizeof(mmDIG0_AFMT_GENERIC_2[0]), 0, 0 }, + { "mmDIG0_AFMT_GENERIC_3", REG_MMIO, 0x2090, 2, &mmDIG0_AFMT_GENERIC_3[0], sizeof(mmDIG0_AFMT_GENERIC_3)/sizeof(mmDIG0_AFMT_GENERIC_3[0]), 0, 0 }, + { "mmDIG0_AFMT_GENERIC_4", REG_MMIO, 0x2091, 2, &mmDIG0_AFMT_GENERIC_4[0], sizeof(mmDIG0_AFMT_GENERIC_4)/sizeof(mmDIG0_AFMT_GENERIC_4[0]), 0, 0 }, + { "mmDIG0_AFMT_GENERIC_5", REG_MMIO, 0x2092, 2, &mmDIG0_AFMT_GENERIC_5[0], sizeof(mmDIG0_AFMT_GENERIC_5)/sizeof(mmDIG0_AFMT_GENERIC_5[0]), 0, 0 }, + { "mmDIG0_AFMT_GENERIC_6", REG_MMIO, 0x2093, 2, &mmDIG0_AFMT_GENERIC_6[0], sizeof(mmDIG0_AFMT_GENERIC_6)/sizeof(mmDIG0_AFMT_GENERIC_6[0]), 0, 0 }, + { "mmDIG0_AFMT_GENERIC_7", REG_MMIO, 0x2094, 2, &mmDIG0_AFMT_GENERIC_7[0], sizeof(mmDIG0_AFMT_GENERIC_7)/sizeof(mmDIG0_AFMT_GENERIC_7[0]), 0, 0 }, + { "mmDIG0_HDMI_GENERIC_PACKET_CONTROL1", REG_MMIO, 0x2095, 2, &mmDIG0_HDMI_GENERIC_PACKET_CONTROL1[0], sizeof(mmDIG0_HDMI_GENERIC_PACKET_CONTROL1)/sizeof(mmDIG0_HDMI_GENERIC_PACKET_CONTROL1[0]), 0, 0 }, + { "mmDIG0_HDMI_ACR_32_0", REG_MMIO, 0x2096, 2, &mmDIG0_HDMI_ACR_32_0[0], sizeof(mmDIG0_HDMI_ACR_32_0)/sizeof(mmDIG0_HDMI_ACR_32_0[0]), 0, 0 }, + { "mmDIG0_HDMI_ACR_32_1", REG_MMIO, 0x2097, 2, &mmDIG0_HDMI_ACR_32_1[0], sizeof(mmDIG0_HDMI_ACR_32_1)/sizeof(mmDIG0_HDMI_ACR_32_1[0]), 0, 0 }, + { "mmDIG0_HDMI_ACR_44_0", REG_MMIO, 0x2098, 2, &mmDIG0_HDMI_ACR_44_0[0], sizeof(mmDIG0_HDMI_ACR_44_0)/sizeof(mmDIG0_HDMI_ACR_44_0[0]), 0, 0 }, + { "mmDIG0_HDMI_ACR_44_1", REG_MMIO, 0x2099, 2, &mmDIG0_HDMI_ACR_44_1[0], sizeof(mmDIG0_HDMI_ACR_44_1)/sizeof(mmDIG0_HDMI_ACR_44_1[0]), 0, 0 }, + { "mmDIG0_HDMI_ACR_48_0", REG_MMIO, 0x209a, 2, &mmDIG0_HDMI_ACR_48_0[0], sizeof(mmDIG0_HDMI_ACR_48_0)/sizeof(mmDIG0_HDMI_ACR_48_0[0]), 0, 0 }, + { "mmDIG0_HDMI_ACR_48_1", REG_MMIO, 0x209b, 2, &mmDIG0_HDMI_ACR_48_1[0], sizeof(mmDIG0_HDMI_ACR_48_1)/sizeof(mmDIG0_HDMI_ACR_48_1[0]), 0, 0 }, + { "mmDIG0_HDMI_ACR_STATUS_0", REG_MMIO, 0x209c, 2, &mmDIG0_HDMI_ACR_STATUS_0[0], sizeof(mmDIG0_HDMI_ACR_STATUS_0)/sizeof(mmDIG0_HDMI_ACR_STATUS_0[0]), 0, 0 }, + { "mmDIG0_HDMI_ACR_STATUS_1", REG_MMIO, 0x209d, 2, &mmDIG0_HDMI_ACR_STATUS_1[0], sizeof(mmDIG0_HDMI_ACR_STATUS_1)/sizeof(mmDIG0_HDMI_ACR_STATUS_1[0]), 0, 0 }, + { "mmDIG0_AFMT_AUDIO_INFO0", REG_MMIO, 0x209e, 2, &mmDIG0_AFMT_AUDIO_INFO0[0], sizeof(mmDIG0_AFMT_AUDIO_INFO0)/sizeof(mmDIG0_AFMT_AUDIO_INFO0[0]), 0, 0 }, + { "mmDIG0_AFMT_AUDIO_INFO1", REG_MMIO, 0x209f, 2, &mmDIG0_AFMT_AUDIO_INFO1[0], sizeof(mmDIG0_AFMT_AUDIO_INFO1)/sizeof(mmDIG0_AFMT_AUDIO_INFO1[0]), 0, 0 }, + { "mmDIG0_AFMT_60958_0", REG_MMIO, 0x20a0, 2, &mmDIG0_AFMT_60958_0[0], sizeof(mmDIG0_AFMT_60958_0)/sizeof(mmDIG0_AFMT_60958_0[0]), 0, 0 }, + { "mmDIG0_AFMT_60958_1", REG_MMIO, 0x20a1, 2, &mmDIG0_AFMT_60958_1[0], sizeof(mmDIG0_AFMT_60958_1)/sizeof(mmDIG0_AFMT_60958_1[0]), 0, 0 }, + { "mmDIG0_AFMT_AUDIO_CRC_CONTROL", REG_MMIO, 0x20a2, 2, &mmDIG0_AFMT_AUDIO_CRC_CONTROL[0], sizeof(mmDIG0_AFMT_AUDIO_CRC_CONTROL)/sizeof(mmDIG0_AFMT_AUDIO_CRC_CONTROL[0]), 0, 0 }, + { "mmDIG0_AFMT_RAMP_CONTROL0", REG_MMIO, 0x20a3, 2, &mmDIG0_AFMT_RAMP_CONTROL0[0], sizeof(mmDIG0_AFMT_RAMP_CONTROL0)/sizeof(mmDIG0_AFMT_RAMP_CONTROL0[0]), 0, 0 }, + { "mmDIG0_AFMT_RAMP_CONTROL1", REG_MMIO, 0x20a4, 2, &mmDIG0_AFMT_RAMP_CONTROL1[0], sizeof(mmDIG0_AFMT_RAMP_CONTROL1)/sizeof(mmDIG0_AFMT_RAMP_CONTROL1[0]), 0, 0 }, + { "mmDIG0_AFMT_RAMP_CONTROL2", REG_MMIO, 0x20a5, 2, &mmDIG0_AFMT_RAMP_CONTROL2[0], sizeof(mmDIG0_AFMT_RAMP_CONTROL2)/sizeof(mmDIG0_AFMT_RAMP_CONTROL2[0]), 0, 0 }, + { "mmDIG0_AFMT_RAMP_CONTROL3", REG_MMIO, 0x20a6, 2, &mmDIG0_AFMT_RAMP_CONTROL3[0], sizeof(mmDIG0_AFMT_RAMP_CONTROL3)/sizeof(mmDIG0_AFMT_RAMP_CONTROL3[0]), 0, 0 }, + { "mmDIG0_AFMT_60958_2", REG_MMIO, 0x20a7, 2, &mmDIG0_AFMT_60958_2[0], sizeof(mmDIG0_AFMT_60958_2)/sizeof(mmDIG0_AFMT_60958_2[0]), 0, 0 }, + { "mmDIG0_AFMT_AUDIO_CRC_RESULT", REG_MMIO, 0x20a8, 2, &mmDIG0_AFMT_AUDIO_CRC_RESULT[0], sizeof(mmDIG0_AFMT_AUDIO_CRC_RESULT)/sizeof(mmDIG0_AFMT_AUDIO_CRC_RESULT[0]), 0, 0 }, + { "mmDIG0_AFMT_STATUS", REG_MMIO, 0x20a9, 2, &mmDIG0_AFMT_STATUS[0], sizeof(mmDIG0_AFMT_STATUS)/sizeof(mmDIG0_AFMT_STATUS[0]), 0, 0 }, + { "mmDIG0_AFMT_AUDIO_PACKET_CONTROL", REG_MMIO, 0x20aa, 2, &mmDIG0_AFMT_AUDIO_PACKET_CONTROL[0], sizeof(mmDIG0_AFMT_AUDIO_PACKET_CONTROL)/sizeof(mmDIG0_AFMT_AUDIO_PACKET_CONTROL[0]), 0, 0 }, + { "mmDIG0_AFMT_VBI_PACKET_CONTROL", REG_MMIO, 0x20ab, 2, &mmDIG0_AFMT_VBI_PACKET_CONTROL[0], sizeof(mmDIG0_AFMT_VBI_PACKET_CONTROL)/sizeof(mmDIG0_AFMT_VBI_PACKET_CONTROL[0]), 0, 0 }, + { "mmDIG0_AFMT_INFOFRAME_CONTROL0", REG_MMIO, 0x20ac, 2, &mmDIG0_AFMT_INFOFRAME_CONTROL0[0], sizeof(mmDIG0_AFMT_INFOFRAME_CONTROL0)/sizeof(mmDIG0_AFMT_INFOFRAME_CONTROL0[0]), 0, 0 }, + { "mmDIG0_AFMT_AUDIO_SRC_CONTROL", REG_MMIO, 0x20ad, 2, &mmDIG0_AFMT_AUDIO_SRC_CONTROL[0], sizeof(mmDIG0_AFMT_AUDIO_SRC_CONTROL)/sizeof(mmDIG0_AFMT_AUDIO_SRC_CONTROL[0]), 0, 0 }, + { "mmDIG0_DIG_BE_CNTL", REG_MMIO, 0x20af, 2, &mmDIG0_DIG_BE_CNTL[0], sizeof(mmDIG0_DIG_BE_CNTL)/sizeof(mmDIG0_DIG_BE_CNTL[0]), 0, 0 }, + { "mmDIG0_DIG_BE_EN_CNTL", REG_MMIO, 0x20b0, 2, &mmDIG0_DIG_BE_EN_CNTL[0], sizeof(mmDIG0_DIG_BE_EN_CNTL)/sizeof(mmDIG0_DIG_BE_EN_CNTL[0]), 0, 0 }, + { "mmDIG0_TMDS_CNTL", REG_MMIO, 0x20d3, 2, &mmDIG0_TMDS_CNTL[0], sizeof(mmDIG0_TMDS_CNTL)/sizeof(mmDIG0_TMDS_CNTL[0]), 0, 0 }, + { "mmDIG0_TMDS_CONTROL_CHAR", REG_MMIO, 0x20d4, 2, &mmDIG0_TMDS_CONTROL_CHAR[0], sizeof(mmDIG0_TMDS_CONTROL_CHAR)/sizeof(mmDIG0_TMDS_CONTROL_CHAR[0]), 0, 0 }, + { "mmDIG0_TMDS_CONTROL0_FEEDBACK", REG_MMIO, 0x20d5, 2, &mmDIG0_TMDS_CONTROL0_FEEDBACK[0], sizeof(mmDIG0_TMDS_CONTROL0_FEEDBACK)/sizeof(mmDIG0_TMDS_CONTROL0_FEEDBACK[0]), 0, 0 }, + { "mmDIG0_TMDS_STEREOSYNC_CTL_SEL", REG_MMIO, 0x20d6, 2, &mmDIG0_TMDS_STEREOSYNC_CTL_SEL[0], sizeof(mmDIG0_TMDS_STEREOSYNC_CTL_SEL)/sizeof(mmDIG0_TMDS_STEREOSYNC_CTL_SEL[0]), 0, 0 }, + { "mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1", REG_MMIO, 0x20d7, 2, &mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1[0], sizeof(mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1)/sizeof(mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1[0]), 0, 0 }, + { "mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3", REG_MMIO, 0x20d8, 2, &mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3[0], sizeof(mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3)/sizeof(mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3[0]), 0, 0 }, + { "mmDIG0_TMDS_CTL_BITS", REG_MMIO, 0x20da, 2, &mmDIG0_TMDS_CTL_BITS[0], sizeof(mmDIG0_TMDS_CTL_BITS)/sizeof(mmDIG0_TMDS_CTL_BITS[0]), 0, 0 }, + { "mmDIG0_TMDS_DCBALANCER_CONTROL", REG_MMIO, 0x20db, 2, &mmDIG0_TMDS_DCBALANCER_CONTROL[0], sizeof(mmDIG0_TMDS_DCBALANCER_CONTROL)/sizeof(mmDIG0_TMDS_DCBALANCER_CONTROL[0]), 0, 0 }, + { "mmDIG0_TMDS_CTL0_1_GEN_CNTL", REG_MMIO, 0x20dd, 2, &mmDIG0_TMDS_CTL0_1_GEN_CNTL[0], sizeof(mmDIG0_TMDS_CTL0_1_GEN_CNTL)/sizeof(mmDIG0_TMDS_CTL0_1_GEN_CNTL[0]), 0, 0 }, + { "mmDIG0_TMDS_CTL2_3_GEN_CNTL", REG_MMIO, 0x20de, 2, &mmDIG0_TMDS_CTL2_3_GEN_CNTL[0], sizeof(mmDIG0_TMDS_CTL2_3_GEN_CNTL)/sizeof(mmDIG0_TMDS_CTL2_3_GEN_CNTL[0]), 0, 0 }, + { "mmDIG0_DIG_VERSION", REG_MMIO, 0x20e0, 2, &mmDIG0_DIG_VERSION[0], sizeof(mmDIG0_DIG_VERSION)/sizeof(mmDIG0_DIG_VERSION[0]), 0, 0 }, + { "mmDIG0_DIG_LANE_ENABLE", REG_MMIO, 0x20e1, 2, &mmDIG0_DIG_LANE_ENABLE[0], sizeof(mmDIG0_DIG_LANE_ENABLE)/sizeof(mmDIG0_DIG_LANE_ENABLE[0]), 0, 0 }, + { "mmDIG0_AFMT_CNTL", REG_MMIO, 0x20e6, 2, &mmDIG0_AFMT_CNTL[0], sizeof(mmDIG0_AFMT_CNTL)/sizeof(mmDIG0_AFMT_CNTL[0]), 0, 0 }, + { "mmDIG0_AFMT_VBI_PACKET_CONTROL1", REG_MMIO, 0x20e7, 2, &mmDIG0_AFMT_VBI_PACKET_CONTROL1[0], sizeof(mmDIG0_AFMT_VBI_PACKET_CONTROL1)/sizeof(mmDIG0_AFMT_VBI_PACKET_CONTROL1[0]), 0, 0 }, + { "mmDP0_DP_LINK_CNTL", REG_MMIO, 0x2108, 2, &mmDP0_DP_LINK_CNTL[0], sizeof(mmDP0_DP_LINK_CNTL)/sizeof(mmDP0_DP_LINK_CNTL[0]), 0, 0 }, + { "mmDP0_DP_PIXEL_FORMAT", REG_MMIO, 0x2109, 2, &mmDP0_DP_PIXEL_FORMAT[0], sizeof(mmDP0_DP_PIXEL_FORMAT)/sizeof(mmDP0_DP_PIXEL_FORMAT[0]), 0, 0 }, + { "mmDP0_DP_MSA_COLORIMETRY", REG_MMIO, 0x210a, 2, &mmDP0_DP_MSA_COLORIMETRY[0], sizeof(mmDP0_DP_MSA_COLORIMETRY)/sizeof(mmDP0_DP_MSA_COLORIMETRY[0]), 0, 0 }, + { "mmDP0_DP_CONFIG", REG_MMIO, 0x210b, 2, &mmDP0_DP_CONFIG[0], sizeof(mmDP0_DP_CONFIG)/sizeof(mmDP0_DP_CONFIG[0]), 0, 0 }, + { "mmDP0_DP_VID_STREAM_CNTL", REG_MMIO, 0x210c, 2, &mmDP0_DP_VID_STREAM_CNTL[0], sizeof(mmDP0_DP_VID_STREAM_CNTL)/sizeof(mmDP0_DP_VID_STREAM_CNTL[0]), 0, 0 }, + { "mmDP0_DP_STEER_FIFO", REG_MMIO, 0x210d, 2, &mmDP0_DP_STEER_FIFO[0], sizeof(mmDP0_DP_STEER_FIFO)/sizeof(mmDP0_DP_STEER_FIFO[0]), 0, 0 }, + { "mmDP0_DP_MSA_MISC", REG_MMIO, 0x210e, 2, &mmDP0_DP_MSA_MISC[0], sizeof(mmDP0_DP_MSA_MISC)/sizeof(mmDP0_DP_MSA_MISC[0]), 0, 0 }, + { "mmDP0_DP_VID_TIMING", REG_MMIO, 0x2110, 2, &mmDP0_DP_VID_TIMING[0], sizeof(mmDP0_DP_VID_TIMING)/sizeof(mmDP0_DP_VID_TIMING[0]), 0, 0 }, + { "mmDP0_DP_VID_N", REG_MMIO, 0x2111, 2, &mmDP0_DP_VID_N[0], sizeof(mmDP0_DP_VID_N)/sizeof(mmDP0_DP_VID_N[0]), 0, 0 }, + { "mmDP0_DP_VID_M", REG_MMIO, 0x2112, 2, &mmDP0_DP_VID_M[0], sizeof(mmDP0_DP_VID_M)/sizeof(mmDP0_DP_VID_M[0]), 0, 0 }, + { "mmDP0_DP_LINK_FRAMING_CNTL", REG_MMIO, 0x2113, 2, &mmDP0_DP_LINK_FRAMING_CNTL[0], sizeof(mmDP0_DP_LINK_FRAMING_CNTL)/sizeof(mmDP0_DP_LINK_FRAMING_CNTL[0]), 0, 0 }, + { "mmDP0_DP_HBR2_EYE_PATTERN", REG_MMIO, 0x2114, 2, &mmDP0_DP_HBR2_EYE_PATTERN[0], sizeof(mmDP0_DP_HBR2_EYE_PATTERN)/sizeof(mmDP0_DP_HBR2_EYE_PATTERN[0]), 0, 0 }, + { "mmDP0_DP_VID_MSA_VBID", REG_MMIO, 0x2115, 2, &mmDP0_DP_VID_MSA_VBID[0], sizeof(mmDP0_DP_VID_MSA_VBID)/sizeof(mmDP0_DP_VID_MSA_VBID[0]), 0, 0 }, + { "mmDP0_DP_VID_INTERRUPT_CNTL", REG_MMIO, 0x2116, 2, &mmDP0_DP_VID_INTERRUPT_CNTL[0], sizeof(mmDP0_DP_VID_INTERRUPT_CNTL)/sizeof(mmDP0_DP_VID_INTERRUPT_CNTL[0]), 0, 0 }, + { "mmDP0_DP_DPHY_CNTL", REG_MMIO, 0x2117, 2, &mmDP0_DP_DPHY_CNTL[0], sizeof(mmDP0_DP_DPHY_CNTL)/sizeof(mmDP0_DP_DPHY_CNTL[0]), 0, 0 }, + { "mmDP0_DP_DPHY_TRAINING_PATTERN_SEL", REG_MMIO, 0x2118, 2, &mmDP0_DP_DPHY_TRAINING_PATTERN_SEL[0], sizeof(mmDP0_DP_DPHY_TRAINING_PATTERN_SEL)/sizeof(mmDP0_DP_DPHY_TRAINING_PATTERN_SEL[0]), 0, 0 }, + { "mmDP0_DP_DPHY_SYM0", REG_MMIO, 0x2119, 2, &mmDP0_DP_DPHY_SYM0[0], sizeof(mmDP0_DP_DPHY_SYM0)/sizeof(mmDP0_DP_DPHY_SYM0[0]), 0, 0 }, + { "mmDP0_DP_DPHY_SYM1", REG_MMIO, 0x211a, 2, &mmDP0_DP_DPHY_SYM1[0], sizeof(mmDP0_DP_DPHY_SYM1)/sizeof(mmDP0_DP_DPHY_SYM1[0]), 0, 0 }, + { "mmDP0_DP_DPHY_SYM2", REG_MMIO, 0x211b, 2, &mmDP0_DP_DPHY_SYM2[0], sizeof(mmDP0_DP_DPHY_SYM2)/sizeof(mmDP0_DP_DPHY_SYM2[0]), 0, 0 }, + { "mmDP0_DP_DPHY_8B10B_CNTL", REG_MMIO, 0x211c, 2, &mmDP0_DP_DPHY_8B10B_CNTL[0], sizeof(mmDP0_DP_DPHY_8B10B_CNTL)/sizeof(mmDP0_DP_DPHY_8B10B_CNTL[0]), 0, 0 }, + { "mmDP0_DP_DPHY_PRBS_CNTL", REG_MMIO, 0x211d, 2, &mmDP0_DP_DPHY_PRBS_CNTL[0], sizeof(mmDP0_DP_DPHY_PRBS_CNTL)/sizeof(mmDP0_DP_DPHY_PRBS_CNTL[0]), 0, 0 }, + { "mmDP0_DP_DPHY_SCRAM_CNTL", REG_MMIO, 0x211e, 2, &mmDP0_DP_DPHY_SCRAM_CNTL[0], sizeof(mmDP0_DP_DPHY_SCRAM_CNTL)/sizeof(mmDP0_DP_DPHY_SCRAM_CNTL[0]), 0, 0 }, + { "mmDP0_DP_DPHY_CRC_EN", REG_MMIO, 0x211f, 2, &mmDP0_DP_DPHY_CRC_EN[0], sizeof(mmDP0_DP_DPHY_CRC_EN)/sizeof(mmDP0_DP_DPHY_CRC_EN[0]), 0, 0 }, + { "mmDP0_DP_DPHY_CRC_CNTL", REG_MMIO, 0x2120, 2, &mmDP0_DP_DPHY_CRC_CNTL[0], sizeof(mmDP0_DP_DPHY_CRC_CNTL)/sizeof(mmDP0_DP_DPHY_CRC_CNTL[0]), 0, 0 }, + { "mmDP0_DP_DPHY_CRC_RESULT", REG_MMIO, 0x2121, 2, &mmDP0_DP_DPHY_CRC_RESULT[0], sizeof(mmDP0_DP_DPHY_CRC_RESULT)/sizeof(mmDP0_DP_DPHY_CRC_RESULT[0]), 0, 0 }, + { "mmDP0_DP_DPHY_CRC_MST_CNTL", REG_MMIO, 0x2122, 2, &mmDP0_DP_DPHY_CRC_MST_CNTL[0], sizeof(mmDP0_DP_DPHY_CRC_MST_CNTL)/sizeof(mmDP0_DP_DPHY_CRC_MST_CNTL[0]), 0, 0 }, + { "mmDP0_DP_DPHY_CRC_MST_STATUS", REG_MMIO, 0x2123, 2, &mmDP0_DP_DPHY_CRC_MST_STATUS[0], sizeof(mmDP0_DP_DPHY_CRC_MST_STATUS)/sizeof(mmDP0_DP_DPHY_CRC_MST_STATUS[0]), 0, 0 }, + { "mmDP0_DP_DPHY_FAST_TRAINING", REG_MMIO, 0x2124, 2, &mmDP0_DP_DPHY_FAST_TRAINING[0], sizeof(mmDP0_DP_DPHY_FAST_TRAINING)/sizeof(mmDP0_DP_DPHY_FAST_TRAINING[0]), 0, 0 }, + { "mmDP0_DP_DPHY_FAST_TRAINING_STATUS", REG_MMIO, 0x2125, 2, &mmDP0_DP_DPHY_FAST_TRAINING_STATUS[0], sizeof(mmDP0_DP_DPHY_FAST_TRAINING_STATUS)/sizeof(mmDP0_DP_DPHY_FAST_TRAINING_STATUS[0]), 0, 0 }, + { "mmDP0_DP_SEC_CNTL", REG_MMIO, 0x212b, 2, &mmDP0_DP_SEC_CNTL[0], sizeof(mmDP0_DP_SEC_CNTL)/sizeof(mmDP0_DP_SEC_CNTL[0]), 0, 0 }, + { "mmDP0_DP_SEC_CNTL1", REG_MMIO, 0x212c, 2, &mmDP0_DP_SEC_CNTL1[0], sizeof(mmDP0_DP_SEC_CNTL1)/sizeof(mmDP0_DP_SEC_CNTL1[0]), 0, 0 }, + { "mmDP0_DP_SEC_FRAMING1", REG_MMIO, 0x212d, 2, &mmDP0_DP_SEC_FRAMING1[0], sizeof(mmDP0_DP_SEC_FRAMING1)/sizeof(mmDP0_DP_SEC_FRAMING1[0]), 0, 0 }, + { "mmDP0_DP_SEC_FRAMING2", REG_MMIO, 0x212e, 2, &mmDP0_DP_SEC_FRAMING2[0], sizeof(mmDP0_DP_SEC_FRAMING2)/sizeof(mmDP0_DP_SEC_FRAMING2[0]), 0, 0 }, + { "mmDP0_DP_SEC_FRAMING3", REG_MMIO, 0x212f, 2, &mmDP0_DP_SEC_FRAMING3[0], sizeof(mmDP0_DP_SEC_FRAMING3)/sizeof(mmDP0_DP_SEC_FRAMING3[0]), 0, 0 }, + { "mmDP0_DP_SEC_FRAMING4", REG_MMIO, 0x2130, 2, &mmDP0_DP_SEC_FRAMING4[0], sizeof(mmDP0_DP_SEC_FRAMING4)/sizeof(mmDP0_DP_SEC_FRAMING4[0]), 0, 0 }, + { "mmDP0_DP_SEC_AUD_N", REG_MMIO, 0x2131, 2, &mmDP0_DP_SEC_AUD_N[0], sizeof(mmDP0_DP_SEC_AUD_N)/sizeof(mmDP0_DP_SEC_AUD_N[0]), 0, 0 }, + { "mmDP0_DP_SEC_AUD_N_READBACK", REG_MMIO, 0x2132, 2, &mmDP0_DP_SEC_AUD_N_READBACK[0], sizeof(mmDP0_DP_SEC_AUD_N_READBACK)/sizeof(mmDP0_DP_SEC_AUD_N_READBACK[0]), 0, 0 }, + { "mmDP0_DP_SEC_AUD_M", REG_MMIO, 0x2133, 2, &mmDP0_DP_SEC_AUD_M[0], sizeof(mmDP0_DP_SEC_AUD_M)/sizeof(mmDP0_DP_SEC_AUD_M[0]), 0, 0 }, + { "mmDP0_DP_SEC_AUD_M_READBACK", REG_MMIO, 0x2134, 2, &mmDP0_DP_SEC_AUD_M_READBACK[0], sizeof(mmDP0_DP_SEC_AUD_M_READBACK)/sizeof(mmDP0_DP_SEC_AUD_M_READBACK[0]), 0, 0 }, + { "mmDP0_DP_SEC_TIMESTAMP", REG_MMIO, 0x2135, 2, &mmDP0_DP_SEC_TIMESTAMP[0], sizeof(mmDP0_DP_SEC_TIMESTAMP)/sizeof(mmDP0_DP_SEC_TIMESTAMP[0]), 0, 0 }, + { "mmDP0_DP_SEC_PACKET_CNTL", REG_MMIO, 0x2136, 2, &mmDP0_DP_SEC_PACKET_CNTL[0], sizeof(mmDP0_DP_SEC_PACKET_CNTL)/sizeof(mmDP0_DP_SEC_PACKET_CNTL[0]), 0, 0 }, + { "mmDP0_DP_MSE_RATE_CNTL", REG_MMIO, 0x2137, 2, &mmDP0_DP_MSE_RATE_CNTL[0], sizeof(mmDP0_DP_MSE_RATE_CNTL)/sizeof(mmDP0_DP_MSE_RATE_CNTL[0]), 0, 0 }, + { "mmDP0_DP_MSE_RATE_UPDATE", REG_MMIO, 0x2139, 2, &mmDP0_DP_MSE_RATE_UPDATE[0], sizeof(mmDP0_DP_MSE_RATE_UPDATE)/sizeof(mmDP0_DP_MSE_RATE_UPDATE[0]), 0, 0 }, + { "mmDP0_DP_MSE_SAT0", REG_MMIO, 0x213a, 2, &mmDP0_DP_MSE_SAT0[0], sizeof(mmDP0_DP_MSE_SAT0)/sizeof(mmDP0_DP_MSE_SAT0[0]), 0, 0 }, + { "mmDP0_DP_MSE_SAT1", REG_MMIO, 0x213b, 2, &mmDP0_DP_MSE_SAT1[0], sizeof(mmDP0_DP_MSE_SAT1)/sizeof(mmDP0_DP_MSE_SAT1[0]), 0, 0 }, + { "mmDP0_DP_MSE_SAT2", REG_MMIO, 0x213c, 2, &mmDP0_DP_MSE_SAT2[0], sizeof(mmDP0_DP_MSE_SAT2)/sizeof(mmDP0_DP_MSE_SAT2[0]), 0, 0 }, + { "mmDP0_DP_MSE_SAT_UPDATE", REG_MMIO, 0x213d, 2, &mmDP0_DP_MSE_SAT_UPDATE[0], sizeof(mmDP0_DP_MSE_SAT_UPDATE)/sizeof(mmDP0_DP_MSE_SAT_UPDATE[0]), 0, 0 }, + { "mmDP0_DP_MSE_LINK_TIMING", REG_MMIO, 0x213e, 2, &mmDP0_DP_MSE_LINK_TIMING[0], sizeof(mmDP0_DP_MSE_LINK_TIMING)/sizeof(mmDP0_DP_MSE_LINK_TIMING[0]), 0, 0 }, + { "mmDP0_DP_MSE_MISC_CNTL", REG_MMIO, 0x213f, 2, &mmDP0_DP_MSE_MISC_CNTL[0], sizeof(mmDP0_DP_MSE_MISC_CNTL)/sizeof(mmDP0_DP_MSE_MISC_CNTL[0]), 0, 0 }, + { "mmDP0_DP_DPHY_BS_SR_SWAP_CNTL", REG_MMIO, 0x2144, 2, &mmDP0_DP_DPHY_BS_SR_SWAP_CNTL[0], sizeof(mmDP0_DP_DPHY_BS_SR_SWAP_CNTL)/sizeof(mmDP0_DP_DPHY_BS_SR_SWAP_CNTL[0]), 0, 0 }, + { "mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL", REG_MMIO, 0x2145, 2, &mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL[0], sizeof(mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL)/sizeof(mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL[0]), 0, 0 }, + { "mmDP0_DP_MSE_SAT0_STATUS", REG_MMIO, 0x2147, 2, &mmDP0_DP_MSE_SAT0_STATUS[0], sizeof(mmDP0_DP_MSE_SAT0_STATUS)/sizeof(mmDP0_DP_MSE_SAT0_STATUS[0]), 0, 0 }, + { "mmDP0_DP_MSE_SAT1_STATUS", REG_MMIO, 0x2148, 2, &mmDP0_DP_MSE_SAT1_STATUS[0], sizeof(mmDP0_DP_MSE_SAT1_STATUS)/sizeof(mmDP0_DP_MSE_SAT1_STATUS[0]), 0, 0 }, + { "mmDP0_DP_MSE_SAT2_STATUS", REG_MMIO, 0x2149, 2, &mmDP0_DP_MSE_SAT2_STATUS[0], sizeof(mmDP0_DP_MSE_SAT2_STATUS)/sizeof(mmDP0_DP_MSE_SAT2_STATUS[0]), 0, 0 }, + { "mmDP0_DP_MSA_TIMING_PARAM1", REG_MMIO, 0x214c, 2, &mmDP0_DP_MSA_TIMING_PARAM1[0], sizeof(mmDP0_DP_MSA_TIMING_PARAM1)/sizeof(mmDP0_DP_MSA_TIMING_PARAM1[0]), 0, 0 }, + { "mmDP0_DP_MSA_TIMING_PARAM2", REG_MMIO, 0x214d, 2, &mmDP0_DP_MSA_TIMING_PARAM2[0], sizeof(mmDP0_DP_MSA_TIMING_PARAM2)/sizeof(mmDP0_DP_MSA_TIMING_PARAM2[0]), 0, 0 }, + { "mmDP0_DP_MSA_TIMING_PARAM3", REG_MMIO, 0x214e, 2, &mmDP0_DP_MSA_TIMING_PARAM3[0], sizeof(mmDP0_DP_MSA_TIMING_PARAM3)/sizeof(mmDP0_DP_MSA_TIMING_PARAM3[0]), 0, 0 }, + { "mmDP0_DP_MSA_TIMING_PARAM4", REG_MMIO, 0x214f, 2, &mmDP0_DP_MSA_TIMING_PARAM4[0], sizeof(mmDP0_DP_MSA_TIMING_PARAM4)/sizeof(mmDP0_DP_MSA_TIMING_PARAM4[0]), 0, 0 }, + { "mmDP0_DP_MSO_CNTL", REG_MMIO, 0x2150, 2, &mmDP0_DP_MSO_CNTL[0], sizeof(mmDP0_DP_MSO_CNTL)/sizeof(mmDP0_DP_MSO_CNTL[0]), 0, 0 }, + { "mmDP0_DP_MSO_CNTL1", REG_MMIO, 0x2151, 2, &mmDP0_DP_MSO_CNTL1[0], sizeof(mmDP0_DP_MSO_CNTL1)/sizeof(mmDP0_DP_MSO_CNTL1[0]), 0, 0 }, + { "mmDP0_DP_DSC_CNTL", REG_MMIO, 0x2152, 2, &mmDP0_DP_DSC_CNTL[0], sizeof(mmDP0_DP_DSC_CNTL)/sizeof(mmDP0_DP_DSC_CNTL[0]), 0, 0 }, + { "mmDP0_DP_SEC_CNTL2", REG_MMIO, 0x2153, 2, &mmDP0_DP_SEC_CNTL2[0], sizeof(mmDP0_DP_SEC_CNTL2)/sizeof(mmDP0_DP_SEC_CNTL2[0]), 0, 0 }, + { "mmDP0_DP_SEC_CNTL3", REG_MMIO, 0x2154, 2, &mmDP0_DP_SEC_CNTL3[0], sizeof(mmDP0_DP_SEC_CNTL3)/sizeof(mmDP0_DP_SEC_CNTL3[0]), 0, 0 }, + { "mmDP0_DP_SEC_CNTL4", REG_MMIO, 0x2155, 2, &mmDP0_DP_SEC_CNTL4[0], sizeof(mmDP0_DP_SEC_CNTL4)/sizeof(mmDP0_DP_SEC_CNTL4[0]), 0, 0 }, + { "mmDP0_DP_SEC_CNTL5", REG_MMIO, 0x2156, 2, &mmDP0_DP_SEC_CNTL5[0], sizeof(mmDP0_DP_SEC_CNTL5)/sizeof(mmDP0_DP_SEC_CNTL5[0]), 0, 0 }, + { "mmDP0_DP_SEC_CNTL6", REG_MMIO, 0x2157, 2, &mmDP0_DP_SEC_CNTL6[0], sizeof(mmDP0_DP_SEC_CNTL6)/sizeof(mmDP0_DP_SEC_CNTL6[0]), 0, 0 }, + { "mmDP0_DP_SEC_CNTL7", REG_MMIO, 0x2158, 2, &mmDP0_DP_SEC_CNTL7[0], sizeof(mmDP0_DP_SEC_CNTL7)/sizeof(mmDP0_DP_SEC_CNTL7[0]), 0, 0 }, + { "mmDP0_DP_DB_CNTL", REG_MMIO, 0x2159, 2, &mmDP0_DP_DB_CNTL[0], sizeof(mmDP0_DP_DB_CNTL)/sizeof(mmDP0_DP_DB_CNTL[0]), 0, 0 }, + { "mmDP0_DP_MSA_VBID_MISC", REG_MMIO, 0x215a, 2, &mmDP0_DP_MSA_VBID_MISC[0], sizeof(mmDP0_DP_MSA_VBID_MISC)/sizeof(mmDP0_DP_MSA_VBID_MISC[0]), 0, 0 }, + { "mmDIG1_DIG_FE_CNTL", REG_MMIO, 0x2168, 2, &mmDIG1_DIG_FE_CNTL[0], sizeof(mmDIG1_DIG_FE_CNTL)/sizeof(mmDIG1_DIG_FE_CNTL[0]), 0, 0 }, + { "mmDIG1_DIG_OUTPUT_CRC_CNTL", REG_MMIO, 0x2169, 2, &mmDIG1_DIG_OUTPUT_CRC_CNTL[0], sizeof(mmDIG1_DIG_OUTPUT_CRC_CNTL)/sizeof(mmDIG1_DIG_OUTPUT_CRC_CNTL[0]), 0, 0 }, + { "mmDIG1_DIG_OUTPUT_CRC_RESULT", REG_MMIO, 0x216a, 2, &mmDIG1_DIG_OUTPUT_CRC_RESULT[0], sizeof(mmDIG1_DIG_OUTPUT_CRC_RESULT)/sizeof(mmDIG1_DIG_OUTPUT_CRC_RESULT[0]), 0, 0 }, + { "mmDIG1_DIG_CLOCK_PATTERN", REG_MMIO, 0x216b, 2, &mmDIG1_DIG_CLOCK_PATTERN[0], sizeof(mmDIG1_DIG_CLOCK_PATTERN)/sizeof(mmDIG1_DIG_CLOCK_PATTERN[0]), 0, 0 }, + { "mmDIG1_DIG_TEST_PATTERN", REG_MMIO, 0x216c, 2, &mmDIG1_DIG_TEST_PATTERN[0], sizeof(mmDIG1_DIG_TEST_PATTERN)/sizeof(mmDIG1_DIG_TEST_PATTERN[0]), 0, 0 }, + { "mmDIG1_DIG_RANDOM_PATTERN_SEED", REG_MMIO, 0x216d, 2, &mmDIG1_DIG_RANDOM_PATTERN_SEED[0], sizeof(mmDIG1_DIG_RANDOM_PATTERN_SEED)/sizeof(mmDIG1_DIG_RANDOM_PATTERN_SEED[0]), 0, 0 }, + { "mmDIG1_DIG_FIFO_STATUS", REG_MMIO, 0x216e, 2, &mmDIG1_DIG_FIFO_STATUS[0], sizeof(mmDIG1_DIG_FIFO_STATUS)/sizeof(mmDIG1_DIG_FIFO_STATUS[0]), 0, 0 }, + { "mmDIG1_HDMI_CONTROL", REG_MMIO, 0x2171, 2, &mmDIG1_HDMI_CONTROL[0], sizeof(mmDIG1_HDMI_CONTROL)/sizeof(mmDIG1_HDMI_CONTROL[0]), 0, 0 }, + { "mmDIG1_HDMI_STATUS", REG_MMIO, 0x2172, 2, &mmDIG1_HDMI_STATUS[0], sizeof(mmDIG1_HDMI_STATUS)/sizeof(mmDIG1_HDMI_STATUS[0]), 0, 0 }, + { "mmDIG1_HDMI_AUDIO_PACKET_CONTROL", REG_MMIO, 0x2173, 2, &mmDIG1_HDMI_AUDIO_PACKET_CONTROL[0], sizeof(mmDIG1_HDMI_AUDIO_PACKET_CONTROL)/sizeof(mmDIG1_HDMI_AUDIO_PACKET_CONTROL[0]), 0, 0 }, + { "mmDIG1_HDMI_ACR_PACKET_CONTROL", REG_MMIO, 0x2174, 2, &mmDIG1_HDMI_ACR_PACKET_CONTROL[0], sizeof(mmDIG1_HDMI_ACR_PACKET_CONTROL)/sizeof(mmDIG1_HDMI_ACR_PACKET_CONTROL[0]), 0, 0 }, + { "mmDIG1_HDMI_VBI_PACKET_CONTROL", REG_MMIO, 0x2175, 2, &mmDIG1_HDMI_VBI_PACKET_CONTROL[0], sizeof(mmDIG1_HDMI_VBI_PACKET_CONTROL)/sizeof(mmDIG1_HDMI_VBI_PACKET_CONTROL[0]), 0, 0 }, + { "mmDIG1_HDMI_INFOFRAME_CONTROL0", REG_MMIO, 0x2176, 2, &mmDIG1_HDMI_INFOFRAME_CONTROL0[0], sizeof(mmDIG1_HDMI_INFOFRAME_CONTROL0)/sizeof(mmDIG1_HDMI_INFOFRAME_CONTROL0[0]), 0, 0 }, + { "mmDIG1_HDMI_INFOFRAME_CONTROL1", REG_MMIO, 0x2177, 2, &mmDIG1_HDMI_INFOFRAME_CONTROL1[0], sizeof(mmDIG1_HDMI_INFOFRAME_CONTROL1)/sizeof(mmDIG1_HDMI_INFOFRAME_CONTROL1[0]), 0, 0 }, + { "mmDIG1_HDMI_GENERIC_PACKET_CONTROL0", REG_MMIO, 0x2178, 2, &mmDIG1_HDMI_GENERIC_PACKET_CONTROL0[0], sizeof(mmDIG1_HDMI_GENERIC_PACKET_CONTROL0)/sizeof(mmDIG1_HDMI_GENERIC_PACKET_CONTROL0[0]), 0, 0 }, + { "mmDIG1_AFMT_INTERRUPT_STATUS", REG_MMIO, 0x2179, 2, NULL, 0, 0, 0 }, + { "mmDIG1_HDMI_GC", REG_MMIO, 0x217b, 2, &mmDIG1_HDMI_GC[0], sizeof(mmDIG1_HDMI_GC)/sizeof(mmDIG1_HDMI_GC[0]), 0, 0 }, + { "mmDIG1_AFMT_AUDIO_PACKET_CONTROL2", REG_MMIO, 0x217c, 2, &mmDIG1_AFMT_AUDIO_PACKET_CONTROL2[0], sizeof(mmDIG1_AFMT_AUDIO_PACKET_CONTROL2)/sizeof(mmDIG1_AFMT_AUDIO_PACKET_CONTROL2[0]), 0, 0 }, + { "mmDIG1_AFMT_ISRC1_0", REG_MMIO, 0x217d, 2, &mmDIG1_AFMT_ISRC1_0[0], sizeof(mmDIG1_AFMT_ISRC1_0)/sizeof(mmDIG1_AFMT_ISRC1_0[0]), 0, 0 }, + { "mmDIG1_AFMT_ISRC1_1", REG_MMIO, 0x217e, 2, &mmDIG1_AFMT_ISRC1_1[0], sizeof(mmDIG1_AFMT_ISRC1_1)/sizeof(mmDIG1_AFMT_ISRC1_1[0]), 0, 0 }, + { "mmDIG1_AFMT_ISRC1_2", REG_MMIO, 0x217f, 2, &mmDIG1_AFMT_ISRC1_2[0], sizeof(mmDIG1_AFMT_ISRC1_2)/sizeof(mmDIG1_AFMT_ISRC1_2[0]), 0, 0 }, + { "mmDIG1_AFMT_ISRC1_3", REG_MMIO, 0x2180, 2, &mmDIG1_AFMT_ISRC1_3[0], sizeof(mmDIG1_AFMT_ISRC1_3)/sizeof(mmDIG1_AFMT_ISRC1_3[0]), 0, 0 }, + { "mmDIG1_AFMT_ISRC1_4", REG_MMIO, 0x2181, 2, &mmDIG1_AFMT_ISRC1_4[0], sizeof(mmDIG1_AFMT_ISRC1_4)/sizeof(mmDIG1_AFMT_ISRC1_4[0]), 0, 0 }, + { "mmDIG1_AFMT_ISRC2_0", REG_MMIO, 0x2182, 2, &mmDIG1_AFMT_ISRC2_0[0], sizeof(mmDIG1_AFMT_ISRC2_0)/sizeof(mmDIG1_AFMT_ISRC2_0[0]), 0, 0 }, + { "mmDIG1_AFMT_ISRC2_1", REG_MMIO, 0x2183, 2, &mmDIG1_AFMT_ISRC2_1[0], sizeof(mmDIG1_AFMT_ISRC2_1)/sizeof(mmDIG1_AFMT_ISRC2_1[0]), 0, 0 }, + { "mmDIG1_AFMT_ISRC2_2", REG_MMIO, 0x2184, 2, &mmDIG1_AFMT_ISRC2_2[0], sizeof(mmDIG1_AFMT_ISRC2_2)/sizeof(mmDIG1_AFMT_ISRC2_2[0]), 0, 0 }, + { "mmDIG1_AFMT_ISRC2_3", REG_MMIO, 0x2185, 2, &mmDIG1_AFMT_ISRC2_3[0], sizeof(mmDIG1_AFMT_ISRC2_3)/sizeof(mmDIG1_AFMT_ISRC2_3[0]), 0, 0 }, + { "mmDIG1_HDMI_GENERIC_PACKET_CONTROL2", REG_MMIO, 0x2186, 2, &mmDIG1_HDMI_GENERIC_PACKET_CONTROL2[0], sizeof(mmDIG1_HDMI_GENERIC_PACKET_CONTROL2)/sizeof(mmDIG1_HDMI_GENERIC_PACKET_CONTROL2[0]), 0, 0 }, + { "mmDIG1_HDMI_GENERIC_PACKET_CONTROL3", REG_MMIO, 0x2187, 2, &mmDIG1_HDMI_GENERIC_PACKET_CONTROL3[0], sizeof(mmDIG1_HDMI_GENERIC_PACKET_CONTROL3)/sizeof(mmDIG1_HDMI_GENERIC_PACKET_CONTROL3[0]), 0, 0 }, + { "mmDIG1_HDMI_DB_CONTROL", REG_MMIO, 0x2188, 2, &mmDIG1_HDMI_DB_CONTROL[0], sizeof(mmDIG1_HDMI_DB_CONTROL)/sizeof(mmDIG1_HDMI_DB_CONTROL[0]), 0, 0 }, + { "mmDIG1_AFMT_MPEG_INFO0", REG_MMIO, 0x218a, 2, &mmDIG1_AFMT_MPEG_INFO0[0], sizeof(mmDIG1_AFMT_MPEG_INFO0)/sizeof(mmDIG1_AFMT_MPEG_INFO0[0]), 0, 0 }, + { "mmDIG1_AFMT_MPEG_INFO1", REG_MMIO, 0x218b, 2, &mmDIG1_AFMT_MPEG_INFO1[0], sizeof(mmDIG1_AFMT_MPEG_INFO1)/sizeof(mmDIG1_AFMT_MPEG_INFO1[0]), 0, 0 }, + { "mmDIG1_AFMT_GENERIC_HDR", REG_MMIO, 0x218c, 2, &mmDIG1_AFMT_GENERIC_HDR[0], sizeof(mmDIG1_AFMT_GENERIC_HDR)/sizeof(mmDIG1_AFMT_GENERIC_HDR[0]), 0, 0 }, + { "mmDIG1_AFMT_GENERIC_0", REG_MMIO, 0x218d, 2, &mmDIG1_AFMT_GENERIC_0[0], sizeof(mmDIG1_AFMT_GENERIC_0)/sizeof(mmDIG1_AFMT_GENERIC_0[0]), 0, 0 }, + { "mmDIG1_AFMT_GENERIC_1", REG_MMIO, 0x218e, 2, &mmDIG1_AFMT_GENERIC_1[0], sizeof(mmDIG1_AFMT_GENERIC_1)/sizeof(mmDIG1_AFMT_GENERIC_1[0]), 0, 0 }, + { "mmDIG1_AFMT_GENERIC_2", REG_MMIO, 0x218f, 2, &mmDIG1_AFMT_GENERIC_2[0], sizeof(mmDIG1_AFMT_GENERIC_2)/sizeof(mmDIG1_AFMT_GENERIC_2[0]), 0, 0 }, + { "mmDIG1_AFMT_GENERIC_3", REG_MMIO, 0x2190, 2, &mmDIG1_AFMT_GENERIC_3[0], sizeof(mmDIG1_AFMT_GENERIC_3)/sizeof(mmDIG1_AFMT_GENERIC_3[0]), 0, 0 }, + { "mmDIG1_AFMT_GENERIC_4", REG_MMIO, 0x2191, 2, &mmDIG1_AFMT_GENERIC_4[0], sizeof(mmDIG1_AFMT_GENERIC_4)/sizeof(mmDIG1_AFMT_GENERIC_4[0]), 0, 0 }, + { "mmDIG1_AFMT_GENERIC_5", REG_MMIO, 0x2192, 2, &mmDIG1_AFMT_GENERIC_5[0], sizeof(mmDIG1_AFMT_GENERIC_5)/sizeof(mmDIG1_AFMT_GENERIC_5[0]), 0, 0 }, + { "mmDIG1_AFMT_GENERIC_6", REG_MMIO, 0x2193, 2, &mmDIG1_AFMT_GENERIC_6[0], sizeof(mmDIG1_AFMT_GENERIC_6)/sizeof(mmDIG1_AFMT_GENERIC_6[0]), 0, 0 }, + { "mmDIG1_AFMT_GENERIC_7", REG_MMIO, 0x2194, 2, &mmDIG1_AFMT_GENERIC_7[0], sizeof(mmDIG1_AFMT_GENERIC_7)/sizeof(mmDIG1_AFMT_GENERIC_7[0]), 0, 0 }, + { "mmDIG1_HDMI_GENERIC_PACKET_CONTROL1", REG_MMIO, 0x2195, 2, &mmDIG1_HDMI_GENERIC_PACKET_CONTROL1[0], sizeof(mmDIG1_HDMI_GENERIC_PACKET_CONTROL1)/sizeof(mmDIG1_HDMI_GENERIC_PACKET_CONTROL1[0]), 0, 0 }, + { "mmDIG1_HDMI_ACR_32_0", REG_MMIO, 0x2196, 2, &mmDIG1_HDMI_ACR_32_0[0], sizeof(mmDIG1_HDMI_ACR_32_0)/sizeof(mmDIG1_HDMI_ACR_32_0[0]), 0, 0 }, + { "mmDIG1_HDMI_ACR_32_1", REG_MMIO, 0x2197, 2, &mmDIG1_HDMI_ACR_32_1[0], sizeof(mmDIG1_HDMI_ACR_32_1)/sizeof(mmDIG1_HDMI_ACR_32_1[0]), 0, 0 }, + { "mmDIG1_HDMI_ACR_44_0", REG_MMIO, 0x2198, 2, &mmDIG1_HDMI_ACR_44_0[0], sizeof(mmDIG1_HDMI_ACR_44_0)/sizeof(mmDIG1_HDMI_ACR_44_0[0]), 0, 0 }, + { "mmDIG1_HDMI_ACR_44_1", REG_MMIO, 0x2199, 2, &mmDIG1_HDMI_ACR_44_1[0], sizeof(mmDIG1_HDMI_ACR_44_1)/sizeof(mmDIG1_HDMI_ACR_44_1[0]), 0, 0 }, + { "mmDIG1_HDMI_ACR_48_0", REG_MMIO, 0x219a, 2, &mmDIG1_HDMI_ACR_48_0[0], sizeof(mmDIG1_HDMI_ACR_48_0)/sizeof(mmDIG1_HDMI_ACR_48_0[0]), 0, 0 }, + { "mmDIG1_HDMI_ACR_48_1", REG_MMIO, 0x219b, 2, &mmDIG1_HDMI_ACR_48_1[0], sizeof(mmDIG1_HDMI_ACR_48_1)/sizeof(mmDIG1_HDMI_ACR_48_1[0]), 0, 0 }, + { "mmDIG1_HDMI_ACR_STATUS_0", REG_MMIO, 0x219c, 2, &mmDIG1_HDMI_ACR_STATUS_0[0], sizeof(mmDIG1_HDMI_ACR_STATUS_0)/sizeof(mmDIG1_HDMI_ACR_STATUS_0[0]), 0, 0 }, + { "mmDIG1_HDMI_ACR_STATUS_1", REG_MMIO, 0x219d, 2, &mmDIG1_HDMI_ACR_STATUS_1[0], sizeof(mmDIG1_HDMI_ACR_STATUS_1)/sizeof(mmDIG1_HDMI_ACR_STATUS_1[0]), 0, 0 }, + { "mmDIG1_AFMT_AUDIO_INFO0", REG_MMIO, 0x219e, 2, &mmDIG1_AFMT_AUDIO_INFO0[0], sizeof(mmDIG1_AFMT_AUDIO_INFO0)/sizeof(mmDIG1_AFMT_AUDIO_INFO0[0]), 0, 0 }, + { "mmDIG1_AFMT_AUDIO_INFO1", REG_MMIO, 0x219f, 2, &mmDIG1_AFMT_AUDIO_INFO1[0], sizeof(mmDIG1_AFMT_AUDIO_INFO1)/sizeof(mmDIG1_AFMT_AUDIO_INFO1[0]), 0, 0 }, + { "mmDIG1_AFMT_60958_0", REG_MMIO, 0x21a0, 2, &mmDIG1_AFMT_60958_0[0], sizeof(mmDIG1_AFMT_60958_0)/sizeof(mmDIG1_AFMT_60958_0[0]), 0, 0 }, + { "mmDIG1_AFMT_60958_1", REG_MMIO, 0x21a1, 2, &mmDIG1_AFMT_60958_1[0], sizeof(mmDIG1_AFMT_60958_1)/sizeof(mmDIG1_AFMT_60958_1[0]), 0, 0 }, + { "mmDIG1_AFMT_AUDIO_CRC_CONTROL", REG_MMIO, 0x21a2, 2, &mmDIG1_AFMT_AUDIO_CRC_CONTROL[0], sizeof(mmDIG1_AFMT_AUDIO_CRC_CONTROL)/sizeof(mmDIG1_AFMT_AUDIO_CRC_CONTROL[0]), 0, 0 }, + { "mmDIG1_AFMT_RAMP_CONTROL0", REG_MMIO, 0x21a3, 2, &mmDIG1_AFMT_RAMP_CONTROL0[0], sizeof(mmDIG1_AFMT_RAMP_CONTROL0)/sizeof(mmDIG1_AFMT_RAMP_CONTROL0[0]), 0, 0 }, + { "mmDIG1_AFMT_RAMP_CONTROL1", REG_MMIO, 0x21a4, 2, &mmDIG1_AFMT_RAMP_CONTROL1[0], sizeof(mmDIG1_AFMT_RAMP_CONTROL1)/sizeof(mmDIG1_AFMT_RAMP_CONTROL1[0]), 0, 0 }, + { "mmDIG1_AFMT_RAMP_CONTROL2", REG_MMIO, 0x21a5, 2, &mmDIG1_AFMT_RAMP_CONTROL2[0], sizeof(mmDIG1_AFMT_RAMP_CONTROL2)/sizeof(mmDIG1_AFMT_RAMP_CONTROL2[0]), 0, 0 }, + { "mmDIG1_AFMT_RAMP_CONTROL3", REG_MMIO, 0x21a6, 2, &mmDIG1_AFMT_RAMP_CONTROL3[0], sizeof(mmDIG1_AFMT_RAMP_CONTROL3)/sizeof(mmDIG1_AFMT_RAMP_CONTROL3[0]), 0, 0 }, + { "mmDIG1_AFMT_60958_2", REG_MMIO, 0x21a7, 2, &mmDIG1_AFMT_60958_2[0], sizeof(mmDIG1_AFMT_60958_2)/sizeof(mmDIG1_AFMT_60958_2[0]), 0, 0 }, + { "mmDIG1_AFMT_AUDIO_CRC_RESULT", REG_MMIO, 0x21a8, 2, &mmDIG1_AFMT_AUDIO_CRC_RESULT[0], sizeof(mmDIG1_AFMT_AUDIO_CRC_RESULT)/sizeof(mmDIG1_AFMT_AUDIO_CRC_RESULT[0]), 0, 0 }, + { "mmDIG1_AFMT_STATUS", REG_MMIO, 0x21a9, 2, &mmDIG1_AFMT_STATUS[0], sizeof(mmDIG1_AFMT_STATUS)/sizeof(mmDIG1_AFMT_STATUS[0]), 0, 0 }, + { "mmDIG1_AFMT_AUDIO_PACKET_CONTROL", REG_MMIO, 0x21aa, 2, &mmDIG1_AFMT_AUDIO_PACKET_CONTROL[0], sizeof(mmDIG1_AFMT_AUDIO_PACKET_CONTROL)/sizeof(mmDIG1_AFMT_AUDIO_PACKET_CONTROL[0]), 0, 0 }, + { "mmDIG1_AFMT_VBI_PACKET_CONTROL", REG_MMIO, 0x21ab, 2, &mmDIG1_AFMT_VBI_PACKET_CONTROL[0], sizeof(mmDIG1_AFMT_VBI_PACKET_CONTROL)/sizeof(mmDIG1_AFMT_VBI_PACKET_CONTROL[0]), 0, 0 }, + { "mmDIG1_AFMT_INFOFRAME_CONTROL0", REG_MMIO, 0x21ac, 2, &mmDIG1_AFMT_INFOFRAME_CONTROL0[0], sizeof(mmDIG1_AFMT_INFOFRAME_CONTROL0)/sizeof(mmDIG1_AFMT_INFOFRAME_CONTROL0[0]), 0, 0 }, + { "mmDIG1_AFMT_AUDIO_SRC_CONTROL", REG_MMIO, 0x21ad, 2, &mmDIG1_AFMT_AUDIO_SRC_CONTROL[0], sizeof(mmDIG1_AFMT_AUDIO_SRC_CONTROL)/sizeof(mmDIG1_AFMT_AUDIO_SRC_CONTROL[0]), 0, 0 }, + { "mmDIG1_DIG_BE_CNTL", REG_MMIO, 0x21af, 2, &mmDIG1_DIG_BE_CNTL[0], sizeof(mmDIG1_DIG_BE_CNTL)/sizeof(mmDIG1_DIG_BE_CNTL[0]), 0, 0 }, + { "mmDIG1_DIG_BE_EN_CNTL", REG_MMIO, 0x21b0, 2, &mmDIG1_DIG_BE_EN_CNTL[0], sizeof(mmDIG1_DIG_BE_EN_CNTL)/sizeof(mmDIG1_DIG_BE_EN_CNTL[0]), 0, 0 }, + { "mmDIG1_TMDS_CNTL", REG_MMIO, 0x21d3, 2, &mmDIG1_TMDS_CNTL[0], sizeof(mmDIG1_TMDS_CNTL)/sizeof(mmDIG1_TMDS_CNTL[0]), 0, 0 }, + { "mmDIG1_TMDS_CONTROL_CHAR", REG_MMIO, 0x21d4, 2, &mmDIG1_TMDS_CONTROL_CHAR[0], sizeof(mmDIG1_TMDS_CONTROL_CHAR)/sizeof(mmDIG1_TMDS_CONTROL_CHAR[0]), 0, 0 }, + { "mmDIG1_TMDS_CONTROL0_FEEDBACK", REG_MMIO, 0x21d5, 2, &mmDIG1_TMDS_CONTROL0_FEEDBACK[0], sizeof(mmDIG1_TMDS_CONTROL0_FEEDBACK)/sizeof(mmDIG1_TMDS_CONTROL0_FEEDBACK[0]), 0, 0 }, + { "mmDIG1_TMDS_STEREOSYNC_CTL_SEL", REG_MMIO, 0x21d6, 2, &mmDIG1_TMDS_STEREOSYNC_CTL_SEL[0], sizeof(mmDIG1_TMDS_STEREOSYNC_CTL_SEL)/sizeof(mmDIG1_TMDS_STEREOSYNC_CTL_SEL[0]), 0, 0 }, + { "mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1", REG_MMIO, 0x21d7, 2, &mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1[0], sizeof(mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1)/sizeof(mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1[0]), 0, 0 }, + { "mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3", REG_MMIO, 0x21d8, 2, &mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3[0], sizeof(mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3)/sizeof(mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3[0]), 0, 0 }, + { "mmDIG1_TMDS_CTL_BITS", REG_MMIO, 0x21da, 2, &mmDIG1_TMDS_CTL_BITS[0], sizeof(mmDIG1_TMDS_CTL_BITS)/sizeof(mmDIG1_TMDS_CTL_BITS[0]), 0, 0 }, + { "mmDIG1_TMDS_DCBALANCER_CONTROL", REG_MMIO, 0x21db, 2, &mmDIG1_TMDS_DCBALANCER_CONTROL[0], sizeof(mmDIG1_TMDS_DCBALANCER_CONTROL)/sizeof(mmDIG1_TMDS_DCBALANCER_CONTROL[0]), 0, 0 }, + { "mmDIG1_TMDS_CTL0_1_GEN_CNTL", REG_MMIO, 0x21dd, 2, &mmDIG1_TMDS_CTL0_1_GEN_CNTL[0], sizeof(mmDIG1_TMDS_CTL0_1_GEN_CNTL)/sizeof(mmDIG1_TMDS_CTL0_1_GEN_CNTL[0]), 0, 0 }, + { "mmDIG1_TMDS_CTL2_3_GEN_CNTL", REG_MMIO, 0x21de, 2, &mmDIG1_TMDS_CTL2_3_GEN_CNTL[0], sizeof(mmDIG1_TMDS_CTL2_3_GEN_CNTL)/sizeof(mmDIG1_TMDS_CTL2_3_GEN_CNTL[0]), 0, 0 }, + { "mmDIG1_DIG_VERSION", REG_MMIO, 0x21e0, 2, &mmDIG1_DIG_VERSION[0], sizeof(mmDIG1_DIG_VERSION)/sizeof(mmDIG1_DIG_VERSION[0]), 0, 0 }, + { "mmDIG1_DIG_LANE_ENABLE", REG_MMIO, 0x21e1, 2, &mmDIG1_DIG_LANE_ENABLE[0], sizeof(mmDIG1_DIG_LANE_ENABLE)/sizeof(mmDIG1_DIG_LANE_ENABLE[0]), 0, 0 }, + { "mmDIG1_AFMT_CNTL", REG_MMIO, 0x21e6, 2, &mmDIG1_AFMT_CNTL[0], sizeof(mmDIG1_AFMT_CNTL)/sizeof(mmDIG1_AFMT_CNTL[0]), 0, 0 }, + { "mmDIG1_AFMT_VBI_PACKET_CONTROL1", REG_MMIO, 0x21e7, 2, &mmDIG1_AFMT_VBI_PACKET_CONTROL1[0], sizeof(mmDIG1_AFMT_VBI_PACKET_CONTROL1)/sizeof(mmDIG1_AFMT_VBI_PACKET_CONTROL1[0]), 0, 0 }, + { "mmDP1_DP_LINK_CNTL", REG_MMIO, 0x2208, 2, &mmDP1_DP_LINK_CNTL[0], sizeof(mmDP1_DP_LINK_CNTL)/sizeof(mmDP1_DP_LINK_CNTL[0]), 0, 0 }, + { "mmDP1_DP_PIXEL_FORMAT", REG_MMIO, 0x2209, 2, &mmDP1_DP_PIXEL_FORMAT[0], sizeof(mmDP1_DP_PIXEL_FORMAT)/sizeof(mmDP1_DP_PIXEL_FORMAT[0]), 0, 0 }, + { "mmDP1_DP_MSA_COLORIMETRY", REG_MMIO, 0x220a, 2, &mmDP1_DP_MSA_COLORIMETRY[0], sizeof(mmDP1_DP_MSA_COLORIMETRY)/sizeof(mmDP1_DP_MSA_COLORIMETRY[0]), 0, 0 }, + { "mmDP1_DP_CONFIG", REG_MMIO, 0x220b, 2, &mmDP1_DP_CONFIG[0], sizeof(mmDP1_DP_CONFIG)/sizeof(mmDP1_DP_CONFIG[0]), 0, 0 }, + { "mmDP1_DP_VID_STREAM_CNTL", REG_MMIO, 0x220c, 2, &mmDP1_DP_VID_STREAM_CNTL[0], sizeof(mmDP1_DP_VID_STREAM_CNTL)/sizeof(mmDP1_DP_VID_STREAM_CNTL[0]), 0, 0 }, + { "mmDP1_DP_STEER_FIFO", REG_MMIO, 0x220d, 2, &mmDP1_DP_STEER_FIFO[0], sizeof(mmDP1_DP_STEER_FIFO)/sizeof(mmDP1_DP_STEER_FIFO[0]), 0, 0 }, + { "mmDP1_DP_MSA_MISC", REG_MMIO, 0x220e, 2, &mmDP1_DP_MSA_MISC[0], sizeof(mmDP1_DP_MSA_MISC)/sizeof(mmDP1_DP_MSA_MISC[0]), 0, 0 }, + { "mmDP1_DP_VID_TIMING", REG_MMIO, 0x2210, 2, &mmDP1_DP_VID_TIMING[0], sizeof(mmDP1_DP_VID_TIMING)/sizeof(mmDP1_DP_VID_TIMING[0]), 0, 0 }, + { "mmDP1_DP_VID_N", REG_MMIO, 0x2211, 2, &mmDP1_DP_VID_N[0], sizeof(mmDP1_DP_VID_N)/sizeof(mmDP1_DP_VID_N[0]), 0, 0 }, + { "mmDP1_DP_VID_M", REG_MMIO, 0x2212, 2, &mmDP1_DP_VID_M[0], sizeof(mmDP1_DP_VID_M)/sizeof(mmDP1_DP_VID_M[0]), 0, 0 }, + { "mmDP1_DP_LINK_FRAMING_CNTL", REG_MMIO, 0x2213, 2, &mmDP1_DP_LINK_FRAMING_CNTL[0], sizeof(mmDP1_DP_LINK_FRAMING_CNTL)/sizeof(mmDP1_DP_LINK_FRAMING_CNTL[0]), 0, 0 }, + { "mmDP1_DP_HBR2_EYE_PATTERN", REG_MMIO, 0x2214, 2, &mmDP1_DP_HBR2_EYE_PATTERN[0], sizeof(mmDP1_DP_HBR2_EYE_PATTERN)/sizeof(mmDP1_DP_HBR2_EYE_PATTERN[0]), 0, 0 }, + { "mmDP1_DP_VID_MSA_VBID", REG_MMIO, 0x2215, 2, &mmDP1_DP_VID_MSA_VBID[0], sizeof(mmDP1_DP_VID_MSA_VBID)/sizeof(mmDP1_DP_VID_MSA_VBID[0]), 0, 0 }, + { "mmDP1_DP_VID_INTERRUPT_CNTL", REG_MMIO, 0x2216, 2, &mmDP1_DP_VID_INTERRUPT_CNTL[0], sizeof(mmDP1_DP_VID_INTERRUPT_CNTL)/sizeof(mmDP1_DP_VID_INTERRUPT_CNTL[0]), 0, 0 }, + { "mmDP1_DP_DPHY_CNTL", REG_MMIO, 0x2217, 2, &mmDP1_DP_DPHY_CNTL[0], sizeof(mmDP1_DP_DPHY_CNTL)/sizeof(mmDP1_DP_DPHY_CNTL[0]), 0, 0 }, + { "mmDP1_DP_DPHY_TRAINING_PATTERN_SEL", REG_MMIO, 0x2218, 2, &mmDP1_DP_DPHY_TRAINING_PATTERN_SEL[0], sizeof(mmDP1_DP_DPHY_TRAINING_PATTERN_SEL)/sizeof(mmDP1_DP_DPHY_TRAINING_PATTERN_SEL[0]), 0, 0 }, + { "mmDP1_DP_DPHY_SYM0", REG_MMIO, 0x2219, 2, &mmDP1_DP_DPHY_SYM0[0], sizeof(mmDP1_DP_DPHY_SYM0)/sizeof(mmDP1_DP_DPHY_SYM0[0]), 0, 0 }, + { "mmDP1_DP_DPHY_SYM1", REG_MMIO, 0x221a, 2, &mmDP1_DP_DPHY_SYM1[0], sizeof(mmDP1_DP_DPHY_SYM1)/sizeof(mmDP1_DP_DPHY_SYM1[0]), 0, 0 }, + { "mmDP1_DP_DPHY_SYM2", REG_MMIO, 0x221b, 2, &mmDP1_DP_DPHY_SYM2[0], sizeof(mmDP1_DP_DPHY_SYM2)/sizeof(mmDP1_DP_DPHY_SYM2[0]), 0, 0 }, + { "mmDP1_DP_DPHY_8B10B_CNTL", REG_MMIO, 0x221c, 2, &mmDP1_DP_DPHY_8B10B_CNTL[0], sizeof(mmDP1_DP_DPHY_8B10B_CNTL)/sizeof(mmDP1_DP_DPHY_8B10B_CNTL[0]), 0, 0 }, + { "mmDP1_DP_DPHY_PRBS_CNTL", REG_MMIO, 0x221d, 2, &mmDP1_DP_DPHY_PRBS_CNTL[0], sizeof(mmDP1_DP_DPHY_PRBS_CNTL)/sizeof(mmDP1_DP_DPHY_PRBS_CNTL[0]), 0, 0 }, + { "mmDP1_DP_DPHY_SCRAM_CNTL", REG_MMIO, 0x221e, 2, &mmDP1_DP_DPHY_SCRAM_CNTL[0], sizeof(mmDP1_DP_DPHY_SCRAM_CNTL)/sizeof(mmDP1_DP_DPHY_SCRAM_CNTL[0]), 0, 0 }, + { "mmDP1_DP_DPHY_CRC_EN", REG_MMIO, 0x221f, 2, &mmDP1_DP_DPHY_CRC_EN[0], sizeof(mmDP1_DP_DPHY_CRC_EN)/sizeof(mmDP1_DP_DPHY_CRC_EN[0]), 0, 0 }, + { "mmDP1_DP_DPHY_CRC_CNTL", REG_MMIO, 0x2220, 2, &mmDP1_DP_DPHY_CRC_CNTL[0], sizeof(mmDP1_DP_DPHY_CRC_CNTL)/sizeof(mmDP1_DP_DPHY_CRC_CNTL[0]), 0, 0 }, + { "mmDP1_DP_DPHY_CRC_RESULT", REG_MMIO, 0x2221, 2, &mmDP1_DP_DPHY_CRC_RESULT[0], sizeof(mmDP1_DP_DPHY_CRC_RESULT)/sizeof(mmDP1_DP_DPHY_CRC_RESULT[0]), 0, 0 }, + { "mmDP1_DP_DPHY_CRC_MST_CNTL", REG_MMIO, 0x2222, 2, &mmDP1_DP_DPHY_CRC_MST_CNTL[0], sizeof(mmDP1_DP_DPHY_CRC_MST_CNTL)/sizeof(mmDP1_DP_DPHY_CRC_MST_CNTL[0]), 0, 0 }, + { "mmDP1_DP_DPHY_CRC_MST_STATUS", REG_MMIO, 0x2223, 2, &mmDP1_DP_DPHY_CRC_MST_STATUS[0], sizeof(mmDP1_DP_DPHY_CRC_MST_STATUS)/sizeof(mmDP1_DP_DPHY_CRC_MST_STATUS[0]), 0, 0 }, + { "mmDP1_DP_DPHY_FAST_TRAINING", REG_MMIO, 0x2224, 2, &mmDP1_DP_DPHY_FAST_TRAINING[0], sizeof(mmDP1_DP_DPHY_FAST_TRAINING)/sizeof(mmDP1_DP_DPHY_FAST_TRAINING[0]), 0, 0 }, + { "mmDP1_DP_DPHY_FAST_TRAINING_STATUS", REG_MMIO, 0x2225, 2, &mmDP1_DP_DPHY_FAST_TRAINING_STATUS[0], sizeof(mmDP1_DP_DPHY_FAST_TRAINING_STATUS)/sizeof(mmDP1_DP_DPHY_FAST_TRAINING_STATUS[0]), 0, 0 }, + { "mmDP1_DP_SEC_CNTL", REG_MMIO, 0x222b, 2, &mmDP1_DP_SEC_CNTL[0], sizeof(mmDP1_DP_SEC_CNTL)/sizeof(mmDP1_DP_SEC_CNTL[0]), 0, 0 }, + { "mmDP1_DP_SEC_CNTL1", REG_MMIO, 0x222c, 2, &mmDP1_DP_SEC_CNTL1[0], sizeof(mmDP1_DP_SEC_CNTL1)/sizeof(mmDP1_DP_SEC_CNTL1[0]), 0, 0 }, + { "mmDP1_DP_SEC_FRAMING1", REG_MMIO, 0x222d, 2, &mmDP1_DP_SEC_FRAMING1[0], sizeof(mmDP1_DP_SEC_FRAMING1)/sizeof(mmDP1_DP_SEC_FRAMING1[0]), 0, 0 }, + { "mmDP1_DP_SEC_FRAMING2", REG_MMIO, 0x222e, 2, &mmDP1_DP_SEC_FRAMING2[0], sizeof(mmDP1_DP_SEC_FRAMING2)/sizeof(mmDP1_DP_SEC_FRAMING2[0]), 0, 0 }, + { "mmDP1_DP_SEC_FRAMING3", REG_MMIO, 0x222f, 2, &mmDP1_DP_SEC_FRAMING3[0], sizeof(mmDP1_DP_SEC_FRAMING3)/sizeof(mmDP1_DP_SEC_FRAMING3[0]), 0, 0 }, + { "mmDP1_DP_SEC_FRAMING4", REG_MMIO, 0x2230, 2, &mmDP1_DP_SEC_FRAMING4[0], sizeof(mmDP1_DP_SEC_FRAMING4)/sizeof(mmDP1_DP_SEC_FRAMING4[0]), 0, 0 }, + { "mmDP1_DP_SEC_AUD_N", REG_MMIO, 0x2231, 2, &mmDP1_DP_SEC_AUD_N[0], sizeof(mmDP1_DP_SEC_AUD_N)/sizeof(mmDP1_DP_SEC_AUD_N[0]), 0, 0 }, + { "mmDP1_DP_SEC_AUD_N_READBACK", REG_MMIO, 0x2232, 2, &mmDP1_DP_SEC_AUD_N_READBACK[0], sizeof(mmDP1_DP_SEC_AUD_N_READBACK)/sizeof(mmDP1_DP_SEC_AUD_N_READBACK[0]), 0, 0 }, + { "mmDP1_DP_SEC_AUD_M", REG_MMIO, 0x2233, 2, &mmDP1_DP_SEC_AUD_M[0], sizeof(mmDP1_DP_SEC_AUD_M)/sizeof(mmDP1_DP_SEC_AUD_M[0]), 0, 0 }, + { "mmDP1_DP_SEC_AUD_M_READBACK", REG_MMIO, 0x2234, 2, &mmDP1_DP_SEC_AUD_M_READBACK[0], sizeof(mmDP1_DP_SEC_AUD_M_READBACK)/sizeof(mmDP1_DP_SEC_AUD_M_READBACK[0]), 0, 0 }, + { "mmDP1_DP_SEC_TIMESTAMP", REG_MMIO, 0x2235, 2, &mmDP1_DP_SEC_TIMESTAMP[0], sizeof(mmDP1_DP_SEC_TIMESTAMP)/sizeof(mmDP1_DP_SEC_TIMESTAMP[0]), 0, 0 }, + { "mmDP1_DP_SEC_PACKET_CNTL", REG_MMIO, 0x2236, 2, &mmDP1_DP_SEC_PACKET_CNTL[0], sizeof(mmDP1_DP_SEC_PACKET_CNTL)/sizeof(mmDP1_DP_SEC_PACKET_CNTL[0]), 0, 0 }, + { "mmDP1_DP_MSE_RATE_CNTL", REG_MMIO, 0x2237, 2, &mmDP1_DP_MSE_RATE_CNTL[0], sizeof(mmDP1_DP_MSE_RATE_CNTL)/sizeof(mmDP1_DP_MSE_RATE_CNTL[0]), 0, 0 }, + { "mmDP1_DP_MSE_RATE_UPDATE", REG_MMIO, 0x2239, 2, &mmDP1_DP_MSE_RATE_UPDATE[0], sizeof(mmDP1_DP_MSE_RATE_UPDATE)/sizeof(mmDP1_DP_MSE_RATE_UPDATE[0]), 0, 0 }, + { "mmDP1_DP_MSE_SAT0", REG_MMIO, 0x223a, 2, &mmDP1_DP_MSE_SAT0[0], sizeof(mmDP1_DP_MSE_SAT0)/sizeof(mmDP1_DP_MSE_SAT0[0]), 0, 0 }, + { "mmDP1_DP_MSE_SAT1", REG_MMIO, 0x223b, 2, &mmDP1_DP_MSE_SAT1[0], sizeof(mmDP1_DP_MSE_SAT1)/sizeof(mmDP1_DP_MSE_SAT1[0]), 0, 0 }, + { "mmDP1_DP_MSE_SAT2", REG_MMIO, 0x223c, 2, &mmDP1_DP_MSE_SAT2[0], sizeof(mmDP1_DP_MSE_SAT2)/sizeof(mmDP1_DP_MSE_SAT2[0]), 0, 0 }, + { "mmDP1_DP_MSE_SAT_UPDATE", REG_MMIO, 0x223d, 2, &mmDP1_DP_MSE_SAT_UPDATE[0], sizeof(mmDP1_DP_MSE_SAT_UPDATE)/sizeof(mmDP1_DP_MSE_SAT_UPDATE[0]), 0, 0 }, + { "mmDP1_DP_MSE_LINK_TIMING", REG_MMIO, 0x223e, 2, &mmDP1_DP_MSE_LINK_TIMING[0], sizeof(mmDP1_DP_MSE_LINK_TIMING)/sizeof(mmDP1_DP_MSE_LINK_TIMING[0]), 0, 0 }, + { "mmDP1_DP_MSE_MISC_CNTL", REG_MMIO, 0x223f, 2, &mmDP1_DP_MSE_MISC_CNTL[0], sizeof(mmDP1_DP_MSE_MISC_CNTL)/sizeof(mmDP1_DP_MSE_MISC_CNTL[0]), 0, 0 }, + { "mmDP1_DP_DPHY_BS_SR_SWAP_CNTL", REG_MMIO, 0x2244, 2, &mmDP1_DP_DPHY_BS_SR_SWAP_CNTL[0], sizeof(mmDP1_DP_DPHY_BS_SR_SWAP_CNTL)/sizeof(mmDP1_DP_DPHY_BS_SR_SWAP_CNTL[0]), 0, 0 }, + { "mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL", REG_MMIO, 0x2245, 2, &mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL[0], sizeof(mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL)/sizeof(mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL[0]), 0, 0 }, + { "mmDP1_DP_MSE_SAT0_STATUS", REG_MMIO, 0x2247, 2, &mmDP1_DP_MSE_SAT0_STATUS[0], sizeof(mmDP1_DP_MSE_SAT0_STATUS)/sizeof(mmDP1_DP_MSE_SAT0_STATUS[0]), 0, 0 }, + { "mmDP1_DP_MSE_SAT1_STATUS", REG_MMIO, 0x2248, 2, &mmDP1_DP_MSE_SAT1_STATUS[0], sizeof(mmDP1_DP_MSE_SAT1_STATUS)/sizeof(mmDP1_DP_MSE_SAT1_STATUS[0]), 0, 0 }, + { "mmDP1_DP_MSE_SAT2_STATUS", REG_MMIO, 0x2249, 2, &mmDP1_DP_MSE_SAT2_STATUS[0], sizeof(mmDP1_DP_MSE_SAT2_STATUS)/sizeof(mmDP1_DP_MSE_SAT2_STATUS[0]), 0, 0 }, + { "mmDP1_DP_MSA_TIMING_PARAM1", REG_MMIO, 0x224c, 2, &mmDP1_DP_MSA_TIMING_PARAM1[0], sizeof(mmDP1_DP_MSA_TIMING_PARAM1)/sizeof(mmDP1_DP_MSA_TIMING_PARAM1[0]), 0, 0 }, + { "mmDP1_DP_MSA_TIMING_PARAM2", REG_MMIO, 0x224d, 2, &mmDP1_DP_MSA_TIMING_PARAM2[0], sizeof(mmDP1_DP_MSA_TIMING_PARAM2)/sizeof(mmDP1_DP_MSA_TIMING_PARAM2[0]), 0, 0 }, + { "mmDP1_DP_MSA_TIMING_PARAM3", REG_MMIO, 0x224e, 2, &mmDP1_DP_MSA_TIMING_PARAM3[0], sizeof(mmDP1_DP_MSA_TIMING_PARAM3)/sizeof(mmDP1_DP_MSA_TIMING_PARAM3[0]), 0, 0 }, + { "mmDP1_DP_MSA_TIMING_PARAM4", REG_MMIO, 0x224f, 2, &mmDP1_DP_MSA_TIMING_PARAM4[0], sizeof(mmDP1_DP_MSA_TIMING_PARAM4)/sizeof(mmDP1_DP_MSA_TIMING_PARAM4[0]), 0, 0 }, + { "mmDP1_DP_MSO_CNTL", REG_MMIO, 0x2250, 2, &mmDP1_DP_MSO_CNTL[0], sizeof(mmDP1_DP_MSO_CNTL)/sizeof(mmDP1_DP_MSO_CNTL[0]), 0, 0 }, + { "mmDP1_DP_MSO_CNTL1", REG_MMIO, 0x2251, 2, &mmDP1_DP_MSO_CNTL1[0], sizeof(mmDP1_DP_MSO_CNTL1)/sizeof(mmDP1_DP_MSO_CNTL1[0]), 0, 0 }, + { "mmDP1_DP_DSC_CNTL", REG_MMIO, 0x2252, 2, &mmDP1_DP_DSC_CNTL[0], sizeof(mmDP1_DP_DSC_CNTL)/sizeof(mmDP1_DP_DSC_CNTL[0]), 0, 0 }, + { "mmDP1_DP_SEC_CNTL2", REG_MMIO, 0x2253, 2, &mmDP1_DP_SEC_CNTL2[0], sizeof(mmDP1_DP_SEC_CNTL2)/sizeof(mmDP1_DP_SEC_CNTL2[0]), 0, 0 }, + { "mmDP1_DP_SEC_CNTL3", REG_MMIO, 0x2254, 2, &mmDP1_DP_SEC_CNTL3[0], sizeof(mmDP1_DP_SEC_CNTL3)/sizeof(mmDP1_DP_SEC_CNTL3[0]), 0, 0 }, + { "mmDP1_DP_SEC_CNTL4", REG_MMIO, 0x2255, 2, &mmDP1_DP_SEC_CNTL4[0], sizeof(mmDP1_DP_SEC_CNTL4)/sizeof(mmDP1_DP_SEC_CNTL4[0]), 0, 0 }, + { "mmDP1_DP_SEC_CNTL5", REG_MMIO, 0x2256, 2, &mmDP1_DP_SEC_CNTL5[0], sizeof(mmDP1_DP_SEC_CNTL5)/sizeof(mmDP1_DP_SEC_CNTL5[0]), 0, 0 }, + { "mmDP1_DP_SEC_CNTL6", REG_MMIO, 0x2257, 2, &mmDP1_DP_SEC_CNTL6[0], sizeof(mmDP1_DP_SEC_CNTL6)/sizeof(mmDP1_DP_SEC_CNTL6[0]), 0, 0 }, + { "mmDP1_DP_SEC_CNTL7", REG_MMIO, 0x2258, 2, &mmDP1_DP_SEC_CNTL7[0], sizeof(mmDP1_DP_SEC_CNTL7)/sizeof(mmDP1_DP_SEC_CNTL7[0]), 0, 0 }, + { "mmDP1_DP_DB_CNTL", REG_MMIO, 0x2259, 2, &mmDP1_DP_DB_CNTL[0], sizeof(mmDP1_DP_DB_CNTL)/sizeof(mmDP1_DP_DB_CNTL[0]), 0, 0 }, + { "mmDP1_DP_MSA_VBID_MISC", REG_MMIO, 0x225a, 2, &mmDP1_DP_MSA_VBID_MISC[0], sizeof(mmDP1_DP_MSA_VBID_MISC)/sizeof(mmDP1_DP_MSA_VBID_MISC[0]), 0, 0 }, + { "mmDIG2_DIG_FE_CNTL", REG_MMIO, 0x2268, 2, &mmDIG2_DIG_FE_CNTL[0], sizeof(mmDIG2_DIG_FE_CNTL)/sizeof(mmDIG2_DIG_FE_CNTL[0]), 0, 0 }, + { "mmDIG2_DIG_OUTPUT_CRC_CNTL", REG_MMIO, 0x2269, 2, &mmDIG2_DIG_OUTPUT_CRC_CNTL[0], sizeof(mmDIG2_DIG_OUTPUT_CRC_CNTL)/sizeof(mmDIG2_DIG_OUTPUT_CRC_CNTL[0]), 0, 0 }, + { "mmDIG2_DIG_OUTPUT_CRC_RESULT", REG_MMIO, 0x226a, 2, &mmDIG2_DIG_OUTPUT_CRC_RESULT[0], sizeof(mmDIG2_DIG_OUTPUT_CRC_RESULT)/sizeof(mmDIG2_DIG_OUTPUT_CRC_RESULT[0]), 0, 0 }, + { "mmDIG2_DIG_CLOCK_PATTERN", REG_MMIO, 0x226b, 2, &mmDIG2_DIG_CLOCK_PATTERN[0], sizeof(mmDIG2_DIG_CLOCK_PATTERN)/sizeof(mmDIG2_DIG_CLOCK_PATTERN[0]), 0, 0 }, + { "mmDIG2_DIG_TEST_PATTERN", REG_MMIO, 0x226c, 2, &mmDIG2_DIG_TEST_PATTERN[0], sizeof(mmDIG2_DIG_TEST_PATTERN)/sizeof(mmDIG2_DIG_TEST_PATTERN[0]), 0, 0 }, + { "mmDIG2_DIG_RANDOM_PATTERN_SEED", REG_MMIO, 0x226d, 2, &mmDIG2_DIG_RANDOM_PATTERN_SEED[0], sizeof(mmDIG2_DIG_RANDOM_PATTERN_SEED)/sizeof(mmDIG2_DIG_RANDOM_PATTERN_SEED[0]), 0, 0 }, + { "mmDIG2_DIG_FIFO_STATUS", REG_MMIO, 0x226e, 2, &mmDIG2_DIG_FIFO_STATUS[0], sizeof(mmDIG2_DIG_FIFO_STATUS)/sizeof(mmDIG2_DIG_FIFO_STATUS[0]), 0, 0 }, + { "mmDIG2_HDMI_CONTROL", REG_MMIO, 0x2271, 2, &mmDIG2_HDMI_CONTROL[0], sizeof(mmDIG2_HDMI_CONTROL)/sizeof(mmDIG2_HDMI_CONTROL[0]), 0, 0 }, + { "mmDIG2_HDMI_STATUS", REG_MMIO, 0x2272, 2, &mmDIG2_HDMI_STATUS[0], sizeof(mmDIG2_HDMI_STATUS)/sizeof(mmDIG2_HDMI_STATUS[0]), 0, 0 }, + { "mmDIG2_HDMI_AUDIO_PACKET_CONTROL", REG_MMIO, 0x2273, 2, &mmDIG2_HDMI_AUDIO_PACKET_CONTROL[0], sizeof(mmDIG2_HDMI_AUDIO_PACKET_CONTROL)/sizeof(mmDIG2_HDMI_AUDIO_PACKET_CONTROL[0]), 0, 0 }, + { "mmDIG2_HDMI_ACR_PACKET_CONTROL", REG_MMIO, 0x2274, 2, &mmDIG2_HDMI_ACR_PACKET_CONTROL[0], sizeof(mmDIG2_HDMI_ACR_PACKET_CONTROL)/sizeof(mmDIG2_HDMI_ACR_PACKET_CONTROL[0]), 0, 0 }, + { "mmDIG2_HDMI_VBI_PACKET_CONTROL", REG_MMIO, 0x2275, 2, &mmDIG2_HDMI_VBI_PACKET_CONTROL[0], sizeof(mmDIG2_HDMI_VBI_PACKET_CONTROL)/sizeof(mmDIG2_HDMI_VBI_PACKET_CONTROL[0]), 0, 0 }, + { "mmDIG2_HDMI_INFOFRAME_CONTROL0", REG_MMIO, 0x2276, 2, &mmDIG2_HDMI_INFOFRAME_CONTROL0[0], sizeof(mmDIG2_HDMI_INFOFRAME_CONTROL0)/sizeof(mmDIG2_HDMI_INFOFRAME_CONTROL0[0]), 0, 0 }, + { "mmDIG2_HDMI_INFOFRAME_CONTROL1", REG_MMIO, 0x2277, 2, &mmDIG2_HDMI_INFOFRAME_CONTROL1[0], sizeof(mmDIG2_HDMI_INFOFRAME_CONTROL1)/sizeof(mmDIG2_HDMI_INFOFRAME_CONTROL1[0]), 0, 0 }, + { "mmDIG2_HDMI_GENERIC_PACKET_CONTROL0", REG_MMIO, 0x2278, 2, &mmDIG2_HDMI_GENERIC_PACKET_CONTROL0[0], sizeof(mmDIG2_HDMI_GENERIC_PACKET_CONTROL0)/sizeof(mmDIG2_HDMI_GENERIC_PACKET_CONTROL0[0]), 0, 0 }, + { "mmDIG2_AFMT_INTERRUPT_STATUS", REG_MMIO, 0x2279, 2, NULL, 0, 0, 0 }, + { "mmDIG2_HDMI_GC", REG_MMIO, 0x227b, 2, &mmDIG2_HDMI_GC[0], sizeof(mmDIG2_HDMI_GC)/sizeof(mmDIG2_HDMI_GC[0]), 0, 0 }, + { "mmDIG2_AFMT_AUDIO_PACKET_CONTROL2", REG_MMIO, 0x227c, 2, &mmDIG2_AFMT_AUDIO_PACKET_CONTROL2[0], sizeof(mmDIG2_AFMT_AUDIO_PACKET_CONTROL2)/sizeof(mmDIG2_AFMT_AUDIO_PACKET_CONTROL2[0]), 0, 0 }, + { "mmDIG2_AFMT_ISRC1_0", REG_MMIO, 0x227d, 2, &mmDIG2_AFMT_ISRC1_0[0], sizeof(mmDIG2_AFMT_ISRC1_0)/sizeof(mmDIG2_AFMT_ISRC1_0[0]), 0, 0 }, + { "mmDIG2_AFMT_ISRC1_1", REG_MMIO, 0x227e, 2, &mmDIG2_AFMT_ISRC1_1[0], sizeof(mmDIG2_AFMT_ISRC1_1)/sizeof(mmDIG2_AFMT_ISRC1_1[0]), 0, 0 }, + { "mmDIG2_AFMT_ISRC1_2", REG_MMIO, 0x227f, 2, &mmDIG2_AFMT_ISRC1_2[0], sizeof(mmDIG2_AFMT_ISRC1_2)/sizeof(mmDIG2_AFMT_ISRC1_2[0]), 0, 0 }, + { "mmDIG2_AFMT_ISRC1_3", REG_MMIO, 0x2280, 2, &mmDIG2_AFMT_ISRC1_3[0], sizeof(mmDIG2_AFMT_ISRC1_3)/sizeof(mmDIG2_AFMT_ISRC1_3[0]), 0, 0 }, + { "mmDIG2_AFMT_ISRC1_4", REG_MMIO, 0x2281, 2, &mmDIG2_AFMT_ISRC1_4[0], sizeof(mmDIG2_AFMT_ISRC1_4)/sizeof(mmDIG2_AFMT_ISRC1_4[0]), 0, 0 }, + { "mmDIG2_AFMT_ISRC2_0", REG_MMIO, 0x2282, 2, &mmDIG2_AFMT_ISRC2_0[0], sizeof(mmDIG2_AFMT_ISRC2_0)/sizeof(mmDIG2_AFMT_ISRC2_0[0]), 0, 0 }, + { "mmDIG2_AFMT_ISRC2_1", REG_MMIO, 0x2283, 2, &mmDIG2_AFMT_ISRC2_1[0], sizeof(mmDIG2_AFMT_ISRC2_1)/sizeof(mmDIG2_AFMT_ISRC2_1[0]), 0, 0 }, + { "mmDIG2_AFMT_ISRC2_2", REG_MMIO, 0x2284, 2, &mmDIG2_AFMT_ISRC2_2[0], sizeof(mmDIG2_AFMT_ISRC2_2)/sizeof(mmDIG2_AFMT_ISRC2_2[0]), 0, 0 }, + { "mmDIG2_AFMT_ISRC2_3", REG_MMIO, 0x2285, 2, &mmDIG2_AFMT_ISRC2_3[0], sizeof(mmDIG2_AFMT_ISRC2_3)/sizeof(mmDIG2_AFMT_ISRC2_3[0]), 0, 0 }, + { "mmDIG2_HDMI_GENERIC_PACKET_CONTROL2", REG_MMIO, 0x2286, 2, &mmDIG2_HDMI_GENERIC_PACKET_CONTROL2[0], sizeof(mmDIG2_HDMI_GENERIC_PACKET_CONTROL2)/sizeof(mmDIG2_HDMI_GENERIC_PACKET_CONTROL2[0]), 0, 0 }, + { "mmDIG2_HDMI_GENERIC_PACKET_CONTROL3", REG_MMIO, 0x2287, 2, &mmDIG2_HDMI_GENERIC_PACKET_CONTROL3[0], sizeof(mmDIG2_HDMI_GENERIC_PACKET_CONTROL3)/sizeof(mmDIG2_HDMI_GENERIC_PACKET_CONTROL3[0]), 0, 0 }, + { "mmDIG2_HDMI_DB_CONTROL", REG_MMIO, 0x2288, 2, &mmDIG2_HDMI_DB_CONTROL[0], sizeof(mmDIG2_HDMI_DB_CONTROL)/sizeof(mmDIG2_HDMI_DB_CONTROL[0]), 0, 0 }, + { "mmDIG2_AFMT_MPEG_INFO0", REG_MMIO, 0x228a, 2, &mmDIG2_AFMT_MPEG_INFO0[0], sizeof(mmDIG2_AFMT_MPEG_INFO0)/sizeof(mmDIG2_AFMT_MPEG_INFO0[0]), 0, 0 }, + { "mmDIG2_AFMT_MPEG_INFO1", REG_MMIO, 0x228b, 2, &mmDIG2_AFMT_MPEG_INFO1[0], sizeof(mmDIG2_AFMT_MPEG_INFO1)/sizeof(mmDIG2_AFMT_MPEG_INFO1[0]), 0, 0 }, + { "mmDIG2_AFMT_GENERIC_HDR", REG_MMIO, 0x228c, 2, &mmDIG2_AFMT_GENERIC_HDR[0], sizeof(mmDIG2_AFMT_GENERIC_HDR)/sizeof(mmDIG2_AFMT_GENERIC_HDR[0]), 0, 0 }, + { "mmDIG2_AFMT_GENERIC_0", REG_MMIO, 0x228d, 2, &mmDIG2_AFMT_GENERIC_0[0], sizeof(mmDIG2_AFMT_GENERIC_0)/sizeof(mmDIG2_AFMT_GENERIC_0[0]), 0, 0 }, + { "mmDIG2_AFMT_GENERIC_1", REG_MMIO, 0x228e, 2, &mmDIG2_AFMT_GENERIC_1[0], sizeof(mmDIG2_AFMT_GENERIC_1)/sizeof(mmDIG2_AFMT_GENERIC_1[0]), 0, 0 }, + { "mmDIG2_AFMT_GENERIC_2", REG_MMIO, 0x228f, 2, &mmDIG2_AFMT_GENERIC_2[0], sizeof(mmDIG2_AFMT_GENERIC_2)/sizeof(mmDIG2_AFMT_GENERIC_2[0]), 0, 0 }, + { "mmDIG2_AFMT_GENERIC_3", REG_MMIO, 0x2290, 2, &mmDIG2_AFMT_GENERIC_3[0], sizeof(mmDIG2_AFMT_GENERIC_3)/sizeof(mmDIG2_AFMT_GENERIC_3[0]), 0, 0 }, + { "mmDIG2_AFMT_GENERIC_4", REG_MMIO, 0x2291, 2, &mmDIG2_AFMT_GENERIC_4[0], sizeof(mmDIG2_AFMT_GENERIC_4)/sizeof(mmDIG2_AFMT_GENERIC_4[0]), 0, 0 }, + { "mmDIG2_AFMT_GENERIC_5", REG_MMIO, 0x2292, 2, &mmDIG2_AFMT_GENERIC_5[0], sizeof(mmDIG2_AFMT_GENERIC_5)/sizeof(mmDIG2_AFMT_GENERIC_5[0]), 0, 0 }, + { "mmDIG2_AFMT_GENERIC_6", REG_MMIO, 0x2293, 2, &mmDIG2_AFMT_GENERIC_6[0], sizeof(mmDIG2_AFMT_GENERIC_6)/sizeof(mmDIG2_AFMT_GENERIC_6[0]), 0, 0 }, + { "mmDIG2_AFMT_GENERIC_7", REG_MMIO, 0x2294, 2, &mmDIG2_AFMT_GENERIC_7[0], sizeof(mmDIG2_AFMT_GENERIC_7)/sizeof(mmDIG2_AFMT_GENERIC_7[0]), 0, 0 }, + { "mmDIG2_HDMI_GENERIC_PACKET_CONTROL1", REG_MMIO, 0x2295, 2, &mmDIG2_HDMI_GENERIC_PACKET_CONTROL1[0], sizeof(mmDIG2_HDMI_GENERIC_PACKET_CONTROL1)/sizeof(mmDIG2_HDMI_GENERIC_PACKET_CONTROL1[0]), 0, 0 }, + { "mmDIG2_HDMI_ACR_32_0", REG_MMIO, 0x2296, 2, &mmDIG2_HDMI_ACR_32_0[0], sizeof(mmDIG2_HDMI_ACR_32_0)/sizeof(mmDIG2_HDMI_ACR_32_0[0]), 0, 0 }, + { "mmDIG2_HDMI_ACR_32_1", REG_MMIO, 0x2297, 2, &mmDIG2_HDMI_ACR_32_1[0], sizeof(mmDIG2_HDMI_ACR_32_1)/sizeof(mmDIG2_HDMI_ACR_32_1[0]), 0, 0 }, + { "mmDIG2_HDMI_ACR_44_0", REG_MMIO, 0x2298, 2, &mmDIG2_HDMI_ACR_44_0[0], sizeof(mmDIG2_HDMI_ACR_44_0)/sizeof(mmDIG2_HDMI_ACR_44_0[0]), 0, 0 }, + { "mmDIG2_HDMI_ACR_44_1", REG_MMIO, 0x2299, 2, &mmDIG2_HDMI_ACR_44_1[0], sizeof(mmDIG2_HDMI_ACR_44_1)/sizeof(mmDIG2_HDMI_ACR_44_1[0]), 0, 0 }, + { "mmDIG2_HDMI_ACR_48_0", REG_MMIO, 0x229a, 2, &mmDIG2_HDMI_ACR_48_0[0], sizeof(mmDIG2_HDMI_ACR_48_0)/sizeof(mmDIG2_HDMI_ACR_48_0[0]), 0, 0 }, + { "mmDIG2_HDMI_ACR_48_1", REG_MMIO, 0x229b, 2, &mmDIG2_HDMI_ACR_48_1[0], sizeof(mmDIG2_HDMI_ACR_48_1)/sizeof(mmDIG2_HDMI_ACR_48_1[0]), 0, 0 }, + { "mmDIG2_HDMI_ACR_STATUS_0", REG_MMIO, 0x229c, 2, &mmDIG2_HDMI_ACR_STATUS_0[0], sizeof(mmDIG2_HDMI_ACR_STATUS_0)/sizeof(mmDIG2_HDMI_ACR_STATUS_0[0]), 0, 0 }, + { "mmDIG2_HDMI_ACR_STATUS_1", REG_MMIO, 0x229d, 2, &mmDIG2_HDMI_ACR_STATUS_1[0], sizeof(mmDIG2_HDMI_ACR_STATUS_1)/sizeof(mmDIG2_HDMI_ACR_STATUS_1[0]), 0, 0 }, + { "mmDIG2_AFMT_AUDIO_INFO0", REG_MMIO, 0x229e, 2, &mmDIG2_AFMT_AUDIO_INFO0[0], sizeof(mmDIG2_AFMT_AUDIO_INFO0)/sizeof(mmDIG2_AFMT_AUDIO_INFO0[0]), 0, 0 }, + { "mmDIG2_AFMT_AUDIO_INFO1", REG_MMIO, 0x229f, 2, &mmDIG2_AFMT_AUDIO_INFO1[0], sizeof(mmDIG2_AFMT_AUDIO_INFO1)/sizeof(mmDIG2_AFMT_AUDIO_INFO1[0]), 0, 0 }, + { "mmDIG2_AFMT_60958_0", REG_MMIO, 0x22a0, 2, &mmDIG2_AFMT_60958_0[0], sizeof(mmDIG2_AFMT_60958_0)/sizeof(mmDIG2_AFMT_60958_0[0]), 0, 0 }, + { "mmDIG2_AFMT_60958_1", REG_MMIO, 0x22a1, 2, &mmDIG2_AFMT_60958_1[0], sizeof(mmDIG2_AFMT_60958_1)/sizeof(mmDIG2_AFMT_60958_1[0]), 0, 0 }, + { "mmDIG2_AFMT_AUDIO_CRC_CONTROL", REG_MMIO, 0x22a2, 2, &mmDIG2_AFMT_AUDIO_CRC_CONTROL[0], sizeof(mmDIG2_AFMT_AUDIO_CRC_CONTROL)/sizeof(mmDIG2_AFMT_AUDIO_CRC_CONTROL[0]), 0, 0 }, + { "mmDIG2_AFMT_RAMP_CONTROL0", REG_MMIO, 0x22a3, 2, &mmDIG2_AFMT_RAMP_CONTROL0[0], sizeof(mmDIG2_AFMT_RAMP_CONTROL0)/sizeof(mmDIG2_AFMT_RAMP_CONTROL0[0]), 0, 0 }, + { "mmDIG2_AFMT_RAMP_CONTROL1", REG_MMIO, 0x22a4, 2, &mmDIG2_AFMT_RAMP_CONTROL1[0], sizeof(mmDIG2_AFMT_RAMP_CONTROL1)/sizeof(mmDIG2_AFMT_RAMP_CONTROL1[0]), 0, 0 }, + { "mmDIG2_AFMT_RAMP_CONTROL2", REG_MMIO, 0x22a5, 2, &mmDIG2_AFMT_RAMP_CONTROL2[0], sizeof(mmDIG2_AFMT_RAMP_CONTROL2)/sizeof(mmDIG2_AFMT_RAMP_CONTROL2[0]), 0, 0 }, + { "mmDIG2_AFMT_RAMP_CONTROL3", REG_MMIO, 0x22a6, 2, &mmDIG2_AFMT_RAMP_CONTROL3[0], sizeof(mmDIG2_AFMT_RAMP_CONTROL3)/sizeof(mmDIG2_AFMT_RAMP_CONTROL3[0]), 0, 0 }, + { "mmDIG2_AFMT_60958_2", REG_MMIO, 0x22a7, 2, &mmDIG2_AFMT_60958_2[0], sizeof(mmDIG2_AFMT_60958_2)/sizeof(mmDIG2_AFMT_60958_2[0]), 0, 0 }, + { "mmDIG2_AFMT_AUDIO_CRC_RESULT", REG_MMIO, 0x22a8, 2, &mmDIG2_AFMT_AUDIO_CRC_RESULT[0], sizeof(mmDIG2_AFMT_AUDIO_CRC_RESULT)/sizeof(mmDIG2_AFMT_AUDIO_CRC_RESULT[0]), 0, 0 }, + { "mmDIG2_AFMT_STATUS", REG_MMIO, 0x22a9, 2, &mmDIG2_AFMT_STATUS[0], sizeof(mmDIG2_AFMT_STATUS)/sizeof(mmDIG2_AFMT_STATUS[0]), 0, 0 }, + { "mmDIG2_AFMT_AUDIO_PACKET_CONTROL", REG_MMIO, 0x22aa, 2, &mmDIG2_AFMT_AUDIO_PACKET_CONTROL[0], sizeof(mmDIG2_AFMT_AUDIO_PACKET_CONTROL)/sizeof(mmDIG2_AFMT_AUDIO_PACKET_CONTROL[0]), 0, 0 }, + { "mmDIG2_AFMT_VBI_PACKET_CONTROL", REG_MMIO, 0x22ab, 2, &mmDIG2_AFMT_VBI_PACKET_CONTROL[0], sizeof(mmDIG2_AFMT_VBI_PACKET_CONTROL)/sizeof(mmDIG2_AFMT_VBI_PACKET_CONTROL[0]), 0, 0 }, + { "mmDIG2_AFMT_INFOFRAME_CONTROL0", REG_MMIO, 0x22ac, 2, &mmDIG2_AFMT_INFOFRAME_CONTROL0[0], sizeof(mmDIG2_AFMT_INFOFRAME_CONTROL0)/sizeof(mmDIG2_AFMT_INFOFRAME_CONTROL0[0]), 0, 0 }, + { "mmDIG2_AFMT_AUDIO_SRC_CONTROL", REG_MMIO, 0x22ad, 2, &mmDIG2_AFMT_AUDIO_SRC_CONTROL[0], sizeof(mmDIG2_AFMT_AUDIO_SRC_CONTROL)/sizeof(mmDIG2_AFMT_AUDIO_SRC_CONTROL[0]), 0, 0 }, + { "mmDIG2_DIG_BE_CNTL", REG_MMIO, 0x22af, 2, &mmDIG2_DIG_BE_CNTL[0], sizeof(mmDIG2_DIG_BE_CNTL)/sizeof(mmDIG2_DIG_BE_CNTL[0]), 0, 0 }, + { "mmDIG2_DIG_BE_EN_CNTL", REG_MMIO, 0x22b0, 2, &mmDIG2_DIG_BE_EN_CNTL[0], sizeof(mmDIG2_DIG_BE_EN_CNTL)/sizeof(mmDIG2_DIG_BE_EN_CNTL[0]), 0, 0 }, + { "mmDIG2_TMDS_CNTL", REG_MMIO, 0x22d3, 2, &mmDIG2_TMDS_CNTL[0], sizeof(mmDIG2_TMDS_CNTL)/sizeof(mmDIG2_TMDS_CNTL[0]), 0, 0 }, + { "mmDIG2_TMDS_CONTROL_CHAR", REG_MMIO, 0x22d4, 2, &mmDIG2_TMDS_CONTROL_CHAR[0], sizeof(mmDIG2_TMDS_CONTROL_CHAR)/sizeof(mmDIG2_TMDS_CONTROL_CHAR[0]), 0, 0 }, + { "mmDIG2_TMDS_CONTROL0_FEEDBACK", REG_MMIO, 0x22d5, 2, &mmDIG2_TMDS_CONTROL0_FEEDBACK[0], sizeof(mmDIG2_TMDS_CONTROL0_FEEDBACK)/sizeof(mmDIG2_TMDS_CONTROL0_FEEDBACK[0]), 0, 0 }, + { "mmDIG2_TMDS_STEREOSYNC_CTL_SEL", REG_MMIO, 0x22d6, 2, &mmDIG2_TMDS_STEREOSYNC_CTL_SEL[0], sizeof(mmDIG2_TMDS_STEREOSYNC_CTL_SEL)/sizeof(mmDIG2_TMDS_STEREOSYNC_CTL_SEL[0]), 0, 0 }, + { "mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1", REG_MMIO, 0x22d7, 2, &mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1[0], sizeof(mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1)/sizeof(mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1[0]), 0, 0 }, + { "mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3", REG_MMIO, 0x22d8, 2, &mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3[0], sizeof(mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3)/sizeof(mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3[0]), 0, 0 }, + { "mmDIG2_TMDS_CTL_BITS", REG_MMIO, 0x22da, 2, &mmDIG2_TMDS_CTL_BITS[0], sizeof(mmDIG2_TMDS_CTL_BITS)/sizeof(mmDIG2_TMDS_CTL_BITS[0]), 0, 0 }, + { "mmDIG2_TMDS_DCBALANCER_CONTROL", REG_MMIO, 0x22db, 2, &mmDIG2_TMDS_DCBALANCER_CONTROL[0], sizeof(mmDIG2_TMDS_DCBALANCER_CONTROL)/sizeof(mmDIG2_TMDS_DCBALANCER_CONTROL[0]), 0, 0 }, + { "mmDIG2_TMDS_CTL0_1_GEN_CNTL", REG_MMIO, 0x22dd, 2, &mmDIG2_TMDS_CTL0_1_GEN_CNTL[0], sizeof(mmDIG2_TMDS_CTL0_1_GEN_CNTL)/sizeof(mmDIG2_TMDS_CTL0_1_GEN_CNTL[0]), 0, 0 }, + { "mmDIG2_TMDS_CTL2_3_GEN_CNTL", REG_MMIO, 0x22de, 2, &mmDIG2_TMDS_CTL2_3_GEN_CNTL[0], sizeof(mmDIG2_TMDS_CTL2_3_GEN_CNTL)/sizeof(mmDIG2_TMDS_CTL2_3_GEN_CNTL[0]), 0, 0 }, + { "mmDIG2_DIG_VERSION", REG_MMIO, 0x22e0, 2, &mmDIG2_DIG_VERSION[0], sizeof(mmDIG2_DIG_VERSION)/sizeof(mmDIG2_DIG_VERSION[0]), 0, 0 }, + { "mmDIG2_DIG_LANE_ENABLE", REG_MMIO, 0x22e1, 2, &mmDIG2_DIG_LANE_ENABLE[0], sizeof(mmDIG2_DIG_LANE_ENABLE)/sizeof(mmDIG2_DIG_LANE_ENABLE[0]), 0, 0 }, + { "mmDIG2_AFMT_CNTL", REG_MMIO, 0x22e6, 2, &mmDIG2_AFMT_CNTL[0], sizeof(mmDIG2_AFMT_CNTL)/sizeof(mmDIG2_AFMT_CNTL[0]), 0, 0 }, + { "mmDIG2_AFMT_VBI_PACKET_CONTROL1", REG_MMIO, 0x22e7, 2, &mmDIG2_AFMT_VBI_PACKET_CONTROL1[0], sizeof(mmDIG2_AFMT_VBI_PACKET_CONTROL1)/sizeof(mmDIG2_AFMT_VBI_PACKET_CONTROL1[0]), 0, 0 }, + { "mmDP2_DP_LINK_CNTL", REG_MMIO, 0x2308, 2, &mmDP2_DP_LINK_CNTL[0], sizeof(mmDP2_DP_LINK_CNTL)/sizeof(mmDP2_DP_LINK_CNTL[0]), 0, 0 }, + { "mmDP2_DP_PIXEL_FORMAT", REG_MMIO, 0x2309, 2, &mmDP2_DP_PIXEL_FORMAT[0], sizeof(mmDP2_DP_PIXEL_FORMAT)/sizeof(mmDP2_DP_PIXEL_FORMAT[0]), 0, 0 }, + { "mmDP2_DP_MSA_COLORIMETRY", REG_MMIO, 0x230a, 2, &mmDP2_DP_MSA_COLORIMETRY[0], sizeof(mmDP2_DP_MSA_COLORIMETRY)/sizeof(mmDP2_DP_MSA_COLORIMETRY[0]), 0, 0 }, + { "mmDP2_DP_CONFIG", REG_MMIO, 0x230b, 2, &mmDP2_DP_CONFIG[0], sizeof(mmDP2_DP_CONFIG)/sizeof(mmDP2_DP_CONFIG[0]), 0, 0 }, + { "mmDP2_DP_VID_STREAM_CNTL", REG_MMIO, 0x230c, 2, &mmDP2_DP_VID_STREAM_CNTL[0], sizeof(mmDP2_DP_VID_STREAM_CNTL)/sizeof(mmDP2_DP_VID_STREAM_CNTL[0]), 0, 0 }, + { "mmDP2_DP_STEER_FIFO", REG_MMIO, 0x230d, 2, &mmDP2_DP_STEER_FIFO[0], sizeof(mmDP2_DP_STEER_FIFO)/sizeof(mmDP2_DP_STEER_FIFO[0]), 0, 0 }, + { "mmDP2_DP_MSA_MISC", REG_MMIO, 0x230e, 2, &mmDP2_DP_MSA_MISC[0], sizeof(mmDP2_DP_MSA_MISC)/sizeof(mmDP2_DP_MSA_MISC[0]), 0, 0 }, + { "mmDP2_DP_VID_TIMING", REG_MMIO, 0x2310, 2, &mmDP2_DP_VID_TIMING[0], sizeof(mmDP2_DP_VID_TIMING)/sizeof(mmDP2_DP_VID_TIMING[0]), 0, 0 }, + { "mmDP2_DP_VID_N", REG_MMIO, 0x2311, 2, &mmDP2_DP_VID_N[0], sizeof(mmDP2_DP_VID_N)/sizeof(mmDP2_DP_VID_N[0]), 0, 0 }, + { "mmDP2_DP_VID_M", REG_MMIO, 0x2312, 2, &mmDP2_DP_VID_M[0], sizeof(mmDP2_DP_VID_M)/sizeof(mmDP2_DP_VID_M[0]), 0, 0 }, + { "mmDP2_DP_LINK_FRAMING_CNTL", REG_MMIO, 0x2313, 2, &mmDP2_DP_LINK_FRAMING_CNTL[0], sizeof(mmDP2_DP_LINK_FRAMING_CNTL)/sizeof(mmDP2_DP_LINK_FRAMING_CNTL[0]), 0, 0 }, + { "mmDP2_DP_HBR2_EYE_PATTERN", REG_MMIO, 0x2314, 2, &mmDP2_DP_HBR2_EYE_PATTERN[0], sizeof(mmDP2_DP_HBR2_EYE_PATTERN)/sizeof(mmDP2_DP_HBR2_EYE_PATTERN[0]), 0, 0 }, + { "mmDP2_DP_VID_MSA_VBID", REG_MMIO, 0x2315, 2, &mmDP2_DP_VID_MSA_VBID[0], sizeof(mmDP2_DP_VID_MSA_VBID)/sizeof(mmDP2_DP_VID_MSA_VBID[0]), 0, 0 }, + { "mmDP2_DP_VID_INTERRUPT_CNTL", REG_MMIO, 0x2316, 2, &mmDP2_DP_VID_INTERRUPT_CNTL[0], sizeof(mmDP2_DP_VID_INTERRUPT_CNTL)/sizeof(mmDP2_DP_VID_INTERRUPT_CNTL[0]), 0, 0 }, + { "mmDP2_DP_DPHY_CNTL", REG_MMIO, 0x2317, 2, &mmDP2_DP_DPHY_CNTL[0], sizeof(mmDP2_DP_DPHY_CNTL)/sizeof(mmDP2_DP_DPHY_CNTL[0]), 0, 0 }, + { "mmDP2_DP_DPHY_TRAINING_PATTERN_SEL", REG_MMIO, 0x2318, 2, &mmDP2_DP_DPHY_TRAINING_PATTERN_SEL[0], sizeof(mmDP2_DP_DPHY_TRAINING_PATTERN_SEL)/sizeof(mmDP2_DP_DPHY_TRAINING_PATTERN_SEL[0]), 0, 0 }, + { "mmDP2_DP_DPHY_SYM0", REG_MMIO, 0x2319, 2, &mmDP2_DP_DPHY_SYM0[0], sizeof(mmDP2_DP_DPHY_SYM0)/sizeof(mmDP2_DP_DPHY_SYM0[0]), 0, 0 }, + { "mmDP2_DP_DPHY_SYM1", REG_MMIO, 0x231a, 2, &mmDP2_DP_DPHY_SYM1[0], sizeof(mmDP2_DP_DPHY_SYM1)/sizeof(mmDP2_DP_DPHY_SYM1[0]), 0, 0 }, + { "mmDP2_DP_DPHY_SYM2", REG_MMIO, 0x231b, 2, &mmDP2_DP_DPHY_SYM2[0], sizeof(mmDP2_DP_DPHY_SYM2)/sizeof(mmDP2_DP_DPHY_SYM2[0]), 0, 0 }, + { "mmDP2_DP_DPHY_8B10B_CNTL", REG_MMIO, 0x231c, 2, &mmDP2_DP_DPHY_8B10B_CNTL[0], sizeof(mmDP2_DP_DPHY_8B10B_CNTL)/sizeof(mmDP2_DP_DPHY_8B10B_CNTL[0]), 0, 0 }, + { "mmDP2_DP_DPHY_PRBS_CNTL", REG_MMIO, 0x231d, 2, &mmDP2_DP_DPHY_PRBS_CNTL[0], sizeof(mmDP2_DP_DPHY_PRBS_CNTL)/sizeof(mmDP2_DP_DPHY_PRBS_CNTL[0]), 0, 0 }, + { "mmDP2_DP_DPHY_SCRAM_CNTL", REG_MMIO, 0x231e, 2, &mmDP2_DP_DPHY_SCRAM_CNTL[0], sizeof(mmDP2_DP_DPHY_SCRAM_CNTL)/sizeof(mmDP2_DP_DPHY_SCRAM_CNTL[0]), 0, 0 }, + { "mmDP2_DP_DPHY_CRC_EN", REG_MMIO, 0x231f, 2, &mmDP2_DP_DPHY_CRC_EN[0], sizeof(mmDP2_DP_DPHY_CRC_EN)/sizeof(mmDP2_DP_DPHY_CRC_EN[0]), 0, 0 }, + { "mmDP2_DP_DPHY_CRC_CNTL", REG_MMIO, 0x2320, 2, &mmDP2_DP_DPHY_CRC_CNTL[0], sizeof(mmDP2_DP_DPHY_CRC_CNTL)/sizeof(mmDP2_DP_DPHY_CRC_CNTL[0]), 0, 0 }, + { "mmDP2_DP_DPHY_CRC_RESULT", REG_MMIO, 0x2321, 2, &mmDP2_DP_DPHY_CRC_RESULT[0], sizeof(mmDP2_DP_DPHY_CRC_RESULT)/sizeof(mmDP2_DP_DPHY_CRC_RESULT[0]), 0, 0 }, + { "mmDP2_DP_DPHY_CRC_MST_CNTL", REG_MMIO, 0x2322, 2, &mmDP2_DP_DPHY_CRC_MST_CNTL[0], sizeof(mmDP2_DP_DPHY_CRC_MST_CNTL)/sizeof(mmDP2_DP_DPHY_CRC_MST_CNTL[0]), 0, 0 }, + { "mmDP2_DP_DPHY_CRC_MST_STATUS", REG_MMIO, 0x2323, 2, &mmDP2_DP_DPHY_CRC_MST_STATUS[0], sizeof(mmDP2_DP_DPHY_CRC_MST_STATUS)/sizeof(mmDP2_DP_DPHY_CRC_MST_STATUS[0]), 0, 0 }, + { "mmDP2_DP_DPHY_FAST_TRAINING", REG_MMIO, 0x2324, 2, &mmDP2_DP_DPHY_FAST_TRAINING[0], sizeof(mmDP2_DP_DPHY_FAST_TRAINING)/sizeof(mmDP2_DP_DPHY_FAST_TRAINING[0]), 0, 0 }, + { "mmDP2_DP_DPHY_FAST_TRAINING_STATUS", REG_MMIO, 0x2325, 2, &mmDP2_DP_DPHY_FAST_TRAINING_STATUS[0], sizeof(mmDP2_DP_DPHY_FAST_TRAINING_STATUS)/sizeof(mmDP2_DP_DPHY_FAST_TRAINING_STATUS[0]), 0, 0 }, + { "mmDP2_DP_SEC_CNTL", REG_MMIO, 0x232b, 2, &mmDP2_DP_SEC_CNTL[0], sizeof(mmDP2_DP_SEC_CNTL)/sizeof(mmDP2_DP_SEC_CNTL[0]), 0, 0 }, + { "mmDP2_DP_SEC_CNTL1", REG_MMIO, 0x232c, 2, &mmDP2_DP_SEC_CNTL1[0], sizeof(mmDP2_DP_SEC_CNTL1)/sizeof(mmDP2_DP_SEC_CNTL1[0]), 0, 0 }, + { "mmDP2_DP_SEC_FRAMING1", REG_MMIO, 0x232d, 2, &mmDP2_DP_SEC_FRAMING1[0], sizeof(mmDP2_DP_SEC_FRAMING1)/sizeof(mmDP2_DP_SEC_FRAMING1[0]), 0, 0 }, + { "mmDP2_DP_SEC_FRAMING2", REG_MMIO, 0x232e, 2, &mmDP2_DP_SEC_FRAMING2[0], sizeof(mmDP2_DP_SEC_FRAMING2)/sizeof(mmDP2_DP_SEC_FRAMING2[0]), 0, 0 }, + { "mmDP2_DP_SEC_FRAMING3", REG_MMIO, 0x232f, 2, &mmDP2_DP_SEC_FRAMING3[0], sizeof(mmDP2_DP_SEC_FRAMING3)/sizeof(mmDP2_DP_SEC_FRAMING3[0]), 0, 0 }, + { "mmDP2_DP_SEC_FRAMING4", REG_MMIO, 0x2330, 2, &mmDP2_DP_SEC_FRAMING4[0], sizeof(mmDP2_DP_SEC_FRAMING4)/sizeof(mmDP2_DP_SEC_FRAMING4[0]), 0, 0 }, + { "mmDP2_DP_SEC_AUD_N", REG_MMIO, 0x2331, 2, &mmDP2_DP_SEC_AUD_N[0], sizeof(mmDP2_DP_SEC_AUD_N)/sizeof(mmDP2_DP_SEC_AUD_N[0]), 0, 0 }, + { "mmDP2_DP_SEC_AUD_N_READBACK", REG_MMIO, 0x2332, 2, &mmDP2_DP_SEC_AUD_N_READBACK[0], sizeof(mmDP2_DP_SEC_AUD_N_READBACK)/sizeof(mmDP2_DP_SEC_AUD_N_READBACK[0]), 0, 0 }, + { "mmDP2_DP_SEC_AUD_M", REG_MMIO, 0x2333, 2, &mmDP2_DP_SEC_AUD_M[0], sizeof(mmDP2_DP_SEC_AUD_M)/sizeof(mmDP2_DP_SEC_AUD_M[0]), 0, 0 }, + { "mmDP2_DP_SEC_AUD_M_READBACK", REG_MMIO, 0x2334, 2, &mmDP2_DP_SEC_AUD_M_READBACK[0], sizeof(mmDP2_DP_SEC_AUD_M_READBACK)/sizeof(mmDP2_DP_SEC_AUD_M_READBACK[0]), 0, 0 }, + { "mmDP2_DP_SEC_TIMESTAMP", REG_MMIO, 0x2335, 2, &mmDP2_DP_SEC_TIMESTAMP[0], sizeof(mmDP2_DP_SEC_TIMESTAMP)/sizeof(mmDP2_DP_SEC_TIMESTAMP[0]), 0, 0 }, + { "mmDP2_DP_SEC_PACKET_CNTL", REG_MMIO, 0x2336, 2, &mmDP2_DP_SEC_PACKET_CNTL[0], sizeof(mmDP2_DP_SEC_PACKET_CNTL)/sizeof(mmDP2_DP_SEC_PACKET_CNTL[0]), 0, 0 }, + { "mmDP2_DP_MSE_RATE_CNTL", REG_MMIO, 0x2337, 2, &mmDP2_DP_MSE_RATE_CNTL[0], sizeof(mmDP2_DP_MSE_RATE_CNTL)/sizeof(mmDP2_DP_MSE_RATE_CNTL[0]), 0, 0 }, + { "mmDP2_DP_MSE_RATE_UPDATE", REG_MMIO, 0x2339, 2, &mmDP2_DP_MSE_RATE_UPDATE[0], sizeof(mmDP2_DP_MSE_RATE_UPDATE)/sizeof(mmDP2_DP_MSE_RATE_UPDATE[0]), 0, 0 }, + { "mmDP2_DP_MSE_SAT0", REG_MMIO, 0x233a, 2, &mmDP2_DP_MSE_SAT0[0], sizeof(mmDP2_DP_MSE_SAT0)/sizeof(mmDP2_DP_MSE_SAT0[0]), 0, 0 }, + { "mmDP2_DP_MSE_SAT1", REG_MMIO, 0x233b, 2, &mmDP2_DP_MSE_SAT1[0], sizeof(mmDP2_DP_MSE_SAT1)/sizeof(mmDP2_DP_MSE_SAT1[0]), 0, 0 }, + { "mmDP2_DP_MSE_SAT2", REG_MMIO, 0x233c, 2, &mmDP2_DP_MSE_SAT2[0], sizeof(mmDP2_DP_MSE_SAT2)/sizeof(mmDP2_DP_MSE_SAT2[0]), 0, 0 }, + { "mmDP2_DP_MSE_SAT_UPDATE", REG_MMIO, 0x233d, 2, &mmDP2_DP_MSE_SAT_UPDATE[0], sizeof(mmDP2_DP_MSE_SAT_UPDATE)/sizeof(mmDP2_DP_MSE_SAT_UPDATE[0]), 0, 0 }, + { "mmDP2_DP_MSE_LINK_TIMING", REG_MMIO, 0x233e, 2, &mmDP2_DP_MSE_LINK_TIMING[0], sizeof(mmDP2_DP_MSE_LINK_TIMING)/sizeof(mmDP2_DP_MSE_LINK_TIMING[0]), 0, 0 }, + { "mmDP2_DP_MSE_MISC_CNTL", REG_MMIO, 0x233f, 2, &mmDP2_DP_MSE_MISC_CNTL[0], sizeof(mmDP2_DP_MSE_MISC_CNTL)/sizeof(mmDP2_DP_MSE_MISC_CNTL[0]), 0, 0 }, + { "mmDP2_DP_DPHY_BS_SR_SWAP_CNTL", REG_MMIO, 0x2344, 2, &mmDP2_DP_DPHY_BS_SR_SWAP_CNTL[0], sizeof(mmDP2_DP_DPHY_BS_SR_SWAP_CNTL)/sizeof(mmDP2_DP_DPHY_BS_SR_SWAP_CNTL[0]), 0, 0 }, + { "mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL", REG_MMIO, 0x2345, 2, &mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL[0], sizeof(mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL)/sizeof(mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL[0]), 0, 0 }, + { "mmDP2_DP_MSE_SAT0_STATUS", REG_MMIO, 0x2347, 2, &mmDP2_DP_MSE_SAT0_STATUS[0], sizeof(mmDP2_DP_MSE_SAT0_STATUS)/sizeof(mmDP2_DP_MSE_SAT0_STATUS[0]), 0, 0 }, + { "mmDP2_DP_MSE_SAT1_STATUS", REG_MMIO, 0x2348, 2, &mmDP2_DP_MSE_SAT1_STATUS[0], sizeof(mmDP2_DP_MSE_SAT1_STATUS)/sizeof(mmDP2_DP_MSE_SAT1_STATUS[0]), 0, 0 }, + { "mmDP2_DP_MSE_SAT2_STATUS", REG_MMIO, 0x2349, 2, &mmDP2_DP_MSE_SAT2_STATUS[0], sizeof(mmDP2_DP_MSE_SAT2_STATUS)/sizeof(mmDP2_DP_MSE_SAT2_STATUS[0]), 0, 0 }, + { "mmDP2_DP_MSA_TIMING_PARAM1", REG_MMIO, 0x234c, 2, &mmDP2_DP_MSA_TIMING_PARAM1[0], sizeof(mmDP2_DP_MSA_TIMING_PARAM1)/sizeof(mmDP2_DP_MSA_TIMING_PARAM1[0]), 0, 0 }, + { "mmDP2_DP_MSA_TIMING_PARAM2", REG_MMIO, 0x234d, 2, &mmDP2_DP_MSA_TIMING_PARAM2[0], sizeof(mmDP2_DP_MSA_TIMING_PARAM2)/sizeof(mmDP2_DP_MSA_TIMING_PARAM2[0]), 0, 0 }, + { "mmDP2_DP_MSA_TIMING_PARAM3", REG_MMIO, 0x234e, 2, &mmDP2_DP_MSA_TIMING_PARAM3[0], sizeof(mmDP2_DP_MSA_TIMING_PARAM3)/sizeof(mmDP2_DP_MSA_TIMING_PARAM3[0]), 0, 0 }, + { "mmDP2_DP_MSA_TIMING_PARAM4", REG_MMIO, 0x234f, 2, &mmDP2_DP_MSA_TIMING_PARAM4[0], sizeof(mmDP2_DP_MSA_TIMING_PARAM4)/sizeof(mmDP2_DP_MSA_TIMING_PARAM4[0]), 0, 0 }, + { "mmDP2_DP_MSO_CNTL", REG_MMIO, 0x2350, 2, &mmDP2_DP_MSO_CNTL[0], sizeof(mmDP2_DP_MSO_CNTL)/sizeof(mmDP2_DP_MSO_CNTL[0]), 0, 0 }, + { "mmDP2_DP_MSO_CNTL1", REG_MMIO, 0x2351, 2, &mmDP2_DP_MSO_CNTL1[0], sizeof(mmDP2_DP_MSO_CNTL1)/sizeof(mmDP2_DP_MSO_CNTL1[0]), 0, 0 }, + { "mmDP2_DP_DSC_CNTL", REG_MMIO, 0x2352, 2, &mmDP2_DP_DSC_CNTL[0], sizeof(mmDP2_DP_DSC_CNTL)/sizeof(mmDP2_DP_DSC_CNTL[0]), 0, 0 }, + { "mmDP2_DP_SEC_CNTL2", REG_MMIO, 0x2353, 2, &mmDP2_DP_SEC_CNTL2[0], sizeof(mmDP2_DP_SEC_CNTL2)/sizeof(mmDP2_DP_SEC_CNTL2[0]), 0, 0 }, + { "mmDP2_DP_SEC_CNTL3", REG_MMIO, 0x2354, 2, &mmDP2_DP_SEC_CNTL3[0], sizeof(mmDP2_DP_SEC_CNTL3)/sizeof(mmDP2_DP_SEC_CNTL3[0]), 0, 0 }, + { "mmDP2_DP_SEC_CNTL4", REG_MMIO, 0x2355, 2, &mmDP2_DP_SEC_CNTL4[0], sizeof(mmDP2_DP_SEC_CNTL4)/sizeof(mmDP2_DP_SEC_CNTL4[0]), 0, 0 }, + { "mmDP2_DP_SEC_CNTL5", REG_MMIO, 0x2356, 2, &mmDP2_DP_SEC_CNTL5[0], sizeof(mmDP2_DP_SEC_CNTL5)/sizeof(mmDP2_DP_SEC_CNTL5[0]), 0, 0 }, + { "mmDP2_DP_SEC_CNTL6", REG_MMIO, 0x2357, 2, &mmDP2_DP_SEC_CNTL6[0], sizeof(mmDP2_DP_SEC_CNTL6)/sizeof(mmDP2_DP_SEC_CNTL6[0]), 0, 0 }, + { "mmDP2_DP_SEC_CNTL7", REG_MMIO, 0x2358, 2, &mmDP2_DP_SEC_CNTL7[0], sizeof(mmDP2_DP_SEC_CNTL7)/sizeof(mmDP2_DP_SEC_CNTL7[0]), 0, 0 }, + { "mmDP2_DP_DB_CNTL", REG_MMIO, 0x2359, 2, &mmDP2_DP_DB_CNTL[0], sizeof(mmDP2_DP_DB_CNTL)/sizeof(mmDP2_DP_DB_CNTL[0]), 0, 0 }, + { "mmDP2_DP_MSA_VBID_MISC", REG_MMIO, 0x235a, 2, &mmDP2_DP_MSA_VBID_MISC[0], sizeof(mmDP2_DP_MSA_VBID_MISC)/sizeof(mmDP2_DP_MSA_VBID_MISC[0]), 0, 0 }, + { "mmDIG3_DIG_FE_CNTL", REG_MMIO, 0x2368, 2, &mmDIG3_DIG_FE_CNTL[0], sizeof(mmDIG3_DIG_FE_CNTL)/sizeof(mmDIG3_DIG_FE_CNTL[0]), 0, 0 }, + { "mmDIG3_DIG_OUTPUT_CRC_CNTL", REG_MMIO, 0x2369, 2, &mmDIG3_DIG_OUTPUT_CRC_CNTL[0], sizeof(mmDIG3_DIG_OUTPUT_CRC_CNTL)/sizeof(mmDIG3_DIG_OUTPUT_CRC_CNTL[0]), 0, 0 }, + { "mmDIG3_DIG_OUTPUT_CRC_RESULT", REG_MMIO, 0x236a, 2, &mmDIG3_DIG_OUTPUT_CRC_RESULT[0], sizeof(mmDIG3_DIG_OUTPUT_CRC_RESULT)/sizeof(mmDIG3_DIG_OUTPUT_CRC_RESULT[0]), 0, 0 }, + { "mmDIG3_DIG_CLOCK_PATTERN", REG_MMIO, 0x236b, 2, &mmDIG3_DIG_CLOCK_PATTERN[0], sizeof(mmDIG3_DIG_CLOCK_PATTERN)/sizeof(mmDIG3_DIG_CLOCK_PATTERN[0]), 0, 0 }, + { "mmDIG3_DIG_TEST_PATTERN", REG_MMIO, 0x236c, 2, &mmDIG3_DIG_TEST_PATTERN[0], sizeof(mmDIG3_DIG_TEST_PATTERN)/sizeof(mmDIG3_DIG_TEST_PATTERN[0]), 0, 0 }, + { "mmDIG3_DIG_RANDOM_PATTERN_SEED", REG_MMIO, 0x236d, 2, &mmDIG3_DIG_RANDOM_PATTERN_SEED[0], sizeof(mmDIG3_DIG_RANDOM_PATTERN_SEED)/sizeof(mmDIG3_DIG_RANDOM_PATTERN_SEED[0]), 0, 0 }, + { "mmDIG3_DIG_FIFO_STATUS", REG_MMIO, 0x236e, 2, &mmDIG3_DIG_FIFO_STATUS[0], sizeof(mmDIG3_DIG_FIFO_STATUS)/sizeof(mmDIG3_DIG_FIFO_STATUS[0]), 0, 0 }, + { "mmDIG3_HDMI_CONTROL", REG_MMIO, 0x2371, 2, &mmDIG3_HDMI_CONTROL[0], sizeof(mmDIG3_HDMI_CONTROL)/sizeof(mmDIG3_HDMI_CONTROL[0]), 0, 0 }, + { "mmDIG3_HDMI_STATUS", REG_MMIO, 0x2372, 2, &mmDIG3_HDMI_STATUS[0], sizeof(mmDIG3_HDMI_STATUS)/sizeof(mmDIG3_HDMI_STATUS[0]), 0, 0 }, + { "mmDIG3_HDMI_AUDIO_PACKET_CONTROL", REG_MMIO, 0x2373, 2, &mmDIG3_HDMI_AUDIO_PACKET_CONTROL[0], sizeof(mmDIG3_HDMI_AUDIO_PACKET_CONTROL)/sizeof(mmDIG3_HDMI_AUDIO_PACKET_CONTROL[0]), 0, 0 }, + { "mmDIG3_HDMI_ACR_PACKET_CONTROL", REG_MMIO, 0x2374, 2, &mmDIG3_HDMI_ACR_PACKET_CONTROL[0], sizeof(mmDIG3_HDMI_ACR_PACKET_CONTROL)/sizeof(mmDIG3_HDMI_ACR_PACKET_CONTROL[0]), 0, 0 }, + { "mmDIG3_HDMI_VBI_PACKET_CONTROL", REG_MMIO, 0x2375, 2, &mmDIG3_HDMI_VBI_PACKET_CONTROL[0], sizeof(mmDIG3_HDMI_VBI_PACKET_CONTROL)/sizeof(mmDIG3_HDMI_VBI_PACKET_CONTROL[0]), 0, 0 }, + { "mmDIG3_HDMI_INFOFRAME_CONTROL0", REG_MMIO, 0x2376, 2, &mmDIG3_HDMI_INFOFRAME_CONTROL0[0], sizeof(mmDIG3_HDMI_INFOFRAME_CONTROL0)/sizeof(mmDIG3_HDMI_INFOFRAME_CONTROL0[0]), 0, 0 }, + { "mmDIG3_HDMI_INFOFRAME_CONTROL1", REG_MMIO, 0x2377, 2, &mmDIG3_HDMI_INFOFRAME_CONTROL1[0], sizeof(mmDIG3_HDMI_INFOFRAME_CONTROL1)/sizeof(mmDIG3_HDMI_INFOFRAME_CONTROL1[0]), 0, 0 }, + { "mmDIG3_HDMI_GENERIC_PACKET_CONTROL0", REG_MMIO, 0x2378, 2, &mmDIG3_HDMI_GENERIC_PACKET_CONTROL0[0], sizeof(mmDIG3_HDMI_GENERIC_PACKET_CONTROL0)/sizeof(mmDIG3_HDMI_GENERIC_PACKET_CONTROL0[0]), 0, 0 }, + { "mmDIG3_AFMT_INTERRUPT_STATUS", REG_MMIO, 0x2379, 2, NULL, 0, 0, 0 }, + { "mmDIG3_HDMI_GC", REG_MMIO, 0x237b, 2, &mmDIG3_HDMI_GC[0], sizeof(mmDIG3_HDMI_GC)/sizeof(mmDIG3_HDMI_GC[0]), 0, 0 }, + { "mmDIG3_AFMT_AUDIO_PACKET_CONTROL2", REG_MMIO, 0x237c, 2, &mmDIG3_AFMT_AUDIO_PACKET_CONTROL2[0], sizeof(mmDIG3_AFMT_AUDIO_PACKET_CONTROL2)/sizeof(mmDIG3_AFMT_AUDIO_PACKET_CONTROL2[0]), 0, 0 }, + { "mmDIG3_AFMT_ISRC1_0", REG_MMIO, 0x237d, 2, &mmDIG3_AFMT_ISRC1_0[0], sizeof(mmDIG3_AFMT_ISRC1_0)/sizeof(mmDIG3_AFMT_ISRC1_0[0]), 0, 0 }, + { "mmDIG3_AFMT_ISRC1_1", REG_MMIO, 0x237e, 2, &mmDIG3_AFMT_ISRC1_1[0], sizeof(mmDIG3_AFMT_ISRC1_1)/sizeof(mmDIG3_AFMT_ISRC1_1[0]), 0, 0 }, + { "mmDIG3_AFMT_ISRC1_2", REG_MMIO, 0x237f, 2, &mmDIG3_AFMT_ISRC1_2[0], sizeof(mmDIG3_AFMT_ISRC1_2)/sizeof(mmDIG3_AFMT_ISRC1_2[0]), 0, 0 }, + { "mmDIG3_AFMT_ISRC1_3", REG_MMIO, 0x2380, 2, &mmDIG3_AFMT_ISRC1_3[0], sizeof(mmDIG3_AFMT_ISRC1_3)/sizeof(mmDIG3_AFMT_ISRC1_3[0]), 0, 0 }, + { "mmDIG3_AFMT_ISRC1_4", REG_MMIO, 0x2381, 2, &mmDIG3_AFMT_ISRC1_4[0], sizeof(mmDIG3_AFMT_ISRC1_4)/sizeof(mmDIG3_AFMT_ISRC1_4[0]), 0, 0 }, + { "mmDIG3_AFMT_ISRC2_0", REG_MMIO, 0x2382, 2, &mmDIG3_AFMT_ISRC2_0[0], sizeof(mmDIG3_AFMT_ISRC2_0)/sizeof(mmDIG3_AFMT_ISRC2_0[0]), 0, 0 }, + { "mmDIG3_AFMT_ISRC2_1", REG_MMIO, 0x2383, 2, &mmDIG3_AFMT_ISRC2_1[0], sizeof(mmDIG3_AFMT_ISRC2_1)/sizeof(mmDIG3_AFMT_ISRC2_1[0]), 0, 0 }, + { "mmDIG3_AFMT_ISRC2_2", REG_MMIO, 0x2384, 2, &mmDIG3_AFMT_ISRC2_2[0], sizeof(mmDIG3_AFMT_ISRC2_2)/sizeof(mmDIG3_AFMT_ISRC2_2[0]), 0, 0 }, + { "mmDIG3_AFMT_ISRC2_3", REG_MMIO, 0x2385, 2, &mmDIG3_AFMT_ISRC2_3[0], sizeof(mmDIG3_AFMT_ISRC2_3)/sizeof(mmDIG3_AFMT_ISRC2_3[0]), 0, 0 }, + { "mmDIG3_HDMI_GENERIC_PACKET_CONTROL2", REG_MMIO, 0x2386, 2, &mmDIG3_HDMI_GENERIC_PACKET_CONTROL2[0], sizeof(mmDIG3_HDMI_GENERIC_PACKET_CONTROL2)/sizeof(mmDIG3_HDMI_GENERIC_PACKET_CONTROL2[0]), 0, 0 }, + { "mmDIG3_HDMI_GENERIC_PACKET_CONTROL3", REG_MMIO, 0x2387, 2, &mmDIG3_HDMI_GENERIC_PACKET_CONTROL3[0], sizeof(mmDIG3_HDMI_GENERIC_PACKET_CONTROL3)/sizeof(mmDIG3_HDMI_GENERIC_PACKET_CONTROL3[0]), 0, 0 }, + { "mmDIG3_HDMI_DB_CONTROL", REG_MMIO, 0x2388, 2, &mmDIG3_HDMI_DB_CONTROL[0], sizeof(mmDIG3_HDMI_DB_CONTROL)/sizeof(mmDIG3_HDMI_DB_CONTROL[0]), 0, 0 }, + { "mmDIG3_AFMT_MPEG_INFO0", REG_MMIO, 0x238a, 2, &mmDIG3_AFMT_MPEG_INFO0[0], sizeof(mmDIG3_AFMT_MPEG_INFO0)/sizeof(mmDIG3_AFMT_MPEG_INFO0[0]), 0, 0 }, + { "mmDIG3_AFMT_MPEG_INFO1", REG_MMIO, 0x238b, 2, &mmDIG3_AFMT_MPEG_INFO1[0], sizeof(mmDIG3_AFMT_MPEG_INFO1)/sizeof(mmDIG3_AFMT_MPEG_INFO1[0]), 0, 0 }, + { "mmDIG3_AFMT_GENERIC_HDR", REG_MMIO, 0x238c, 2, &mmDIG3_AFMT_GENERIC_HDR[0], sizeof(mmDIG3_AFMT_GENERIC_HDR)/sizeof(mmDIG3_AFMT_GENERIC_HDR[0]), 0, 0 }, + { "mmDIG3_AFMT_GENERIC_0", REG_MMIO, 0x238d, 2, &mmDIG3_AFMT_GENERIC_0[0], sizeof(mmDIG3_AFMT_GENERIC_0)/sizeof(mmDIG3_AFMT_GENERIC_0[0]), 0, 0 }, + { "mmDIG3_AFMT_GENERIC_1", REG_MMIO, 0x238e, 2, &mmDIG3_AFMT_GENERIC_1[0], sizeof(mmDIG3_AFMT_GENERIC_1)/sizeof(mmDIG3_AFMT_GENERIC_1[0]), 0, 0 }, + { "mmDIG3_AFMT_GENERIC_2", REG_MMIO, 0x238f, 2, &mmDIG3_AFMT_GENERIC_2[0], sizeof(mmDIG3_AFMT_GENERIC_2)/sizeof(mmDIG3_AFMT_GENERIC_2[0]), 0, 0 }, + { "mmDIG3_AFMT_GENERIC_3", REG_MMIO, 0x2390, 2, &mmDIG3_AFMT_GENERIC_3[0], sizeof(mmDIG3_AFMT_GENERIC_3)/sizeof(mmDIG3_AFMT_GENERIC_3[0]), 0, 0 }, + { "mmDIG3_AFMT_GENERIC_4", REG_MMIO, 0x2391, 2, &mmDIG3_AFMT_GENERIC_4[0], sizeof(mmDIG3_AFMT_GENERIC_4)/sizeof(mmDIG3_AFMT_GENERIC_4[0]), 0, 0 }, + { "mmDIG3_AFMT_GENERIC_5", REG_MMIO, 0x2392, 2, &mmDIG3_AFMT_GENERIC_5[0], sizeof(mmDIG3_AFMT_GENERIC_5)/sizeof(mmDIG3_AFMT_GENERIC_5[0]), 0, 0 }, + { "mmDIG3_AFMT_GENERIC_6", REG_MMIO, 0x2393, 2, &mmDIG3_AFMT_GENERIC_6[0], sizeof(mmDIG3_AFMT_GENERIC_6)/sizeof(mmDIG3_AFMT_GENERIC_6[0]), 0, 0 }, + { "mmDIG3_AFMT_GENERIC_7", REG_MMIO, 0x2394, 2, &mmDIG3_AFMT_GENERIC_7[0], sizeof(mmDIG3_AFMT_GENERIC_7)/sizeof(mmDIG3_AFMT_GENERIC_7[0]), 0, 0 }, + { "mmDIG3_HDMI_GENERIC_PACKET_CONTROL1", REG_MMIO, 0x2395, 2, &mmDIG3_HDMI_GENERIC_PACKET_CONTROL1[0], sizeof(mmDIG3_HDMI_GENERIC_PACKET_CONTROL1)/sizeof(mmDIG3_HDMI_GENERIC_PACKET_CONTROL1[0]), 0, 0 }, + { "mmDIG3_HDMI_ACR_32_0", REG_MMIO, 0x2396, 2, &mmDIG3_HDMI_ACR_32_0[0], sizeof(mmDIG3_HDMI_ACR_32_0)/sizeof(mmDIG3_HDMI_ACR_32_0[0]), 0, 0 }, + { "mmDIG3_HDMI_ACR_32_1", REG_MMIO, 0x2397, 2, &mmDIG3_HDMI_ACR_32_1[0], sizeof(mmDIG3_HDMI_ACR_32_1)/sizeof(mmDIG3_HDMI_ACR_32_1[0]), 0, 0 }, + { "mmDIG3_HDMI_ACR_44_0", REG_MMIO, 0x2398, 2, &mmDIG3_HDMI_ACR_44_0[0], sizeof(mmDIG3_HDMI_ACR_44_0)/sizeof(mmDIG3_HDMI_ACR_44_0[0]), 0, 0 }, + { "mmDIG3_HDMI_ACR_44_1", REG_MMIO, 0x2399, 2, &mmDIG3_HDMI_ACR_44_1[0], sizeof(mmDIG3_HDMI_ACR_44_1)/sizeof(mmDIG3_HDMI_ACR_44_1[0]), 0, 0 }, + { "mmDIG3_HDMI_ACR_48_0", REG_MMIO, 0x239a, 2, &mmDIG3_HDMI_ACR_48_0[0], sizeof(mmDIG3_HDMI_ACR_48_0)/sizeof(mmDIG3_HDMI_ACR_48_0[0]), 0, 0 }, + { "mmDIG3_HDMI_ACR_48_1", REG_MMIO, 0x239b, 2, &mmDIG3_HDMI_ACR_48_1[0], sizeof(mmDIG3_HDMI_ACR_48_1)/sizeof(mmDIG3_HDMI_ACR_48_1[0]), 0, 0 }, + { "mmDIG3_HDMI_ACR_STATUS_0", REG_MMIO, 0x239c, 2, &mmDIG3_HDMI_ACR_STATUS_0[0], sizeof(mmDIG3_HDMI_ACR_STATUS_0)/sizeof(mmDIG3_HDMI_ACR_STATUS_0[0]), 0, 0 }, + { "mmDIG3_HDMI_ACR_STATUS_1", REG_MMIO, 0x239d, 2, &mmDIG3_HDMI_ACR_STATUS_1[0], sizeof(mmDIG3_HDMI_ACR_STATUS_1)/sizeof(mmDIG3_HDMI_ACR_STATUS_1[0]), 0, 0 }, + { "mmDIG3_AFMT_AUDIO_INFO0", REG_MMIO, 0x239e, 2, &mmDIG3_AFMT_AUDIO_INFO0[0], sizeof(mmDIG3_AFMT_AUDIO_INFO0)/sizeof(mmDIG3_AFMT_AUDIO_INFO0[0]), 0, 0 }, + { "mmDIG3_AFMT_AUDIO_INFO1", REG_MMIO, 0x239f, 2, &mmDIG3_AFMT_AUDIO_INFO1[0], sizeof(mmDIG3_AFMT_AUDIO_INFO1)/sizeof(mmDIG3_AFMT_AUDIO_INFO1[0]), 0, 0 }, + { "mmDIG3_AFMT_60958_0", REG_MMIO, 0x23a0, 2, &mmDIG3_AFMT_60958_0[0], sizeof(mmDIG3_AFMT_60958_0)/sizeof(mmDIG3_AFMT_60958_0[0]), 0, 0 }, + { "mmDIG3_AFMT_60958_1", REG_MMIO, 0x23a1, 2, &mmDIG3_AFMT_60958_1[0], sizeof(mmDIG3_AFMT_60958_1)/sizeof(mmDIG3_AFMT_60958_1[0]), 0, 0 }, + { "mmDIG3_AFMT_AUDIO_CRC_CONTROL", REG_MMIO, 0x23a2, 2, &mmDIG3_AFMT_AUDIO_CRC_CONTROL[0], sizeof(mmDIG3_AFMT_AUDIO_CRC_CONTROL)/sizeof(mmDIG3_AFMT_AUDIO_CRC_CONTROL[0]), 0, 0 }, + { "mmDIG3_AFMT_RAMP_CONTROL0", REG_MMIO, 0x23a3, 2, &mmDIG3_AFMT_RAMP_CONTROL0[0], sizeof(mmDIG3_AFMT_RAMP_CONTROL0)/sizeof(mmDIG3_AFMT_RAMP_CONTROL0[0]), 0, 0 }, + { "mmDIG3_AFMT_RAMP_CONTROL1", REG_MMIO, 0x23a4, 2, &mmDIG3_AFMT_RAMP_CONTROL1[0], sizeof(mmDIG3_AFMT_RAMP_CONTROL1)/sizeof(mmDIG3_AFMT_RAMP_CONTROL1[0]), 0, 0 }, + { "mmDIG3_AFMT_RAMP_CONTROL2", REG_MMIO, 0x23a5, 2, &mmDIG3_AFMT_RAMP_CONTROL2[0], sizeof(mmDIG3_AFMT_RAMP_CONTROL2)/sizeof(mmDIG3_AFMT_RAMP_CONTROL2[0]), 0, 0 }, + { "mmDIG3_AFMT_RAMP_CONTROL3", REG_MMIO, 0x23a6, 2, &mmDIG3_AFMT_RAMP_CONTROL3[0], sizeof(mmDIG3_AFMT_RAMP_CONTROL3)/sizeof(mmDIG3_AFMT_RAMP_CONTROL3[0]), 0, 0 }, + { "mmDIG3_AFMT_60958_2", REG_MMIO, 0x23a7, 2, &mmDIG3_AFMT_60958_2[0], sizeof(mmDIG3_AFMT_60958_2)/sizeof(mmDIG3_AFMT_60958_2[0]), 0, 0 }, + { "mmDIG3_AFMT_AUDIO_CRC_RESULT", REG_MMIO, 0x23a8, 2, &mmDIG3_AFMT_AUDIO_CRC_RESULT[0], sizeof(mmDIG3_AFMT_AUDIO_CRC_RESULT)/sizeof(mmDIG3_AFMT_AUDIO_CRC_RESULT[0]), 0, 0 }, + { "mmDIG3_AFMT_STATUS", REG_MMIO, 0x23a9, 2, &mmDIG3_AFMT_STATUS[0], sizeof(mmDIG3_AFMT_STATUS)/sizeof(mmDIG3_AFMT_STATUS[0]), 0, 0 }, + { "mmDIG3_AFMT_AUDIO_PACKET_CONTROL", REG_MMIO, 0x23aa, 2, &mmDIG3_AFMT_AUDIO_PACKET_CONTROL[0], sizeof(mmDIG3_AFMT_AUDIO_PACKET_CONTROL)/sizeof(mmDIG3_AFMT_AUDIO_PACKET_CONTROL[0]), 0, 0 }, + { "mmDIG3_AFMT_VBI_PACKET_CONTROL", REG_MMIO, 0x23ab, 2, &mmDIG3_AFMT_VBI_PACKET_CONTROL[0], sizeof(mmDIG3_AFMT_VBI_PACKET_CONTROL)/sizeof(mmDIG3_AFMT_VBI_PACKET_CONTROL[0]), 0, 0 }, + { "mmDIG3_AFMT_INFOFRAME_CONTROL0", REG_MMIO, 0x23ac, 2, &mmDIG3_AFMT_INFOFRAME_CONTROL0[0], sizeof(mmDIG3_AFMT_INFOFRAME_CONTROL0)/sizeof(mmDIG3_AFMT_INFOFRAME_CONTROL0[0]), 0, 0 }, + { "mmDIG3_AFMT_AUDIO_SRC_CONTROL", REG_MMIO, 0x23ad, 2, &mmDIG3_AFMT_AUDIO_SRC_CONTROL[0], sizeof(mmDIG3_AFMT_AUDIO_SRC_CONTROL)/sizeof(mmDIG3_AFMT_AUDIO_SRC_CONTROL[0]), 0, 0 }, + { "mmDIG3_DIG_BE_CNTL", REG_MMIO, 0x23af, 2, &mmDIG3_DIG_BE_CNTL[0], sizeof(mmDIG3_DIG_BE_CNTL)/sizeof(mmDIG3_DIG_BE_CNTL[0]), 0, 0 }, + { "mmDIG3_DIG_BE_EN_CNTL", REG_MMIO, 0x23b0, 2, &mmDIG3_DIG_BE_EN_CNTL[0], sizeof(mmDIG3_DIG_BE_EN_CNTL)/sizeof(mmDIG3_DIG_BE_EN_CNTL[0]), 0, 0 }, + { "mmDIG3_TMDS_CNTL", REG_MMIO, 0x23d3, 2, &mmDIG3_TMDS_CNTL[0], sizeof(mmDIG3_TMDS_CNTL)/sizeof(mmDIG3_TMDS_CNTL[0]), 0, 0 }, + { "mmDIG3_TMDS_CONTROL_CHAR", REG_MMIO, 0x23d4, 2, &mmDIG3_TMDS_CONTROL_CHAR[0], sizeof(mmDIG3_TMDS_CONTROL_CHAR)/sizeof(mmDIG3_TMDS_CONTROL_CHAR[0]), 0, 0 }, + { "mmDIG3_TMDS_CONTROL0_FEEDBACK", REG_MMIO, 0x23d5, 2, &mmDIG3_TMDS_CONTROL0_FEEDBACK[0], sizeof(mmDIG3_TMDS_CONTROL0_FEEDBACK)/sizeof(mmDIG3_TMDS_CONTROL0_FEEDBACK[0]), 0, 0 }, + { "mmDIG3_TMDS_STEREOSYNC_CTL_SEL", REG_MMIO, 0x23d6, 2, &mmDIG3_TMDS_STEREOSYNC_CTL_SEL[0], sizeof(mmDIG3_TMDS_STEREOSYNC_CTL_SEL)/sizeof(mmDIG3_TMDS_STEREOSYNC_CTL_SEL[0]), 0, 0 }, + { "mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1", REG_MMIO, 0x23d7, 2, &mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1[0], sizeof(mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1)/sizeof(mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1[0]), 0, 0 }, + { "mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3", REG_MMIO, 0x23d8, 2, &mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3[0], sizeof(mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3)/sizeof(mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3[0]), 0, 0 }, + { "mmDIG3_TMDS_CTL_BITS", REG_MMIO, 0x23da, 2, &mmDIG3_TMDS_CTL_BITS[0], sizeof(mmDIG3_TMDS_CTL_BITS)/sizeof(mmDIG3_TMDS_CTL_BITS[0]), 0, 0 }, + { "mmDIG3_TMDS_DCBALANCER_CONTROL", REG_MMIO, 0x23db, 2, &mmDIG3_TMDS_DCBALANCER_CONTROL[0], sizeof(mmDIG3_TMDS_DCBALANCER_CONTROL)/sizeof(mmDIG3_TMDS_DCBALANCER_CONTROL[0]), 0, 0 }, + { "mmDIG3_TMDS_CTL0_1_GEN_CNTL", REG_MMIO, 0x23dd, 2, &mmDIG3_TMDS_CTL0_1_GEN_CNTL[0], sizeof(mmDIG3_TMDS_CTL0_1_GEN_CNTL)/sizeof(mmDIG3_TMDS_CTL0_1_GEN_CNTL[0]), 0, 0 }, + { "mmDIG3_TMDS_CTL2_3_GEN_CNTL", REG_MMIO, 0x23de, 2, &mmDIG3_TMDS_CTL2_3_GEN_CNTL[0], sizeof(mmDIG3_TMDS_CTL2_3_GEN_CNTL)/sizeof(mmDIG3_TMDS_CTL2_3_GEN_CNTL[0]), 0, 0 }, + { "mmDIG3_DIG_VERSION", REG_MMIO, 0x23e0, 2, &mmDIG3_DIG_VERSION[0], sizeof(mmDIG3_DIG_VERSION)/sizeof(mmDIG3_DIG_VERSION[0]), 0, 0 }, + { "mmDIG3_DIG_LANE_ENABLE", REG_MMIO, 0x23e1, 2, &mmDIG3_DIG_LANE_ENABLE[0], sizeof(mmDIG3_DIG_LANE_ENABLE)/sizeof(mmDIG3_DIG_LANE_ENABLE[0]), 0, 0 }, + { "mmDIG3_AFMT_CNTL", REG_MMIO, 0x23e6, 2, &mmDIG3_AFMT_CNTL[0], sizeof(mmDIG3_AFMT_CNTL)/sizeof(mmDIG3_AFMT_CNTL[0]), 0, 0 }, + { "mmDIG3_AFMT_VBI_PACKET_CONTROL1", REG_MMIO, 0x23e7, 2, &mmDIG3_AFMT_VBI_PACKET_CONTROL1[0], sizeof(mmDIG3_AFMT_VBI_PACKET_CONTROL1)/sizeof(mmDIG3_AFMT_VBI_PACKET_CONTROL1[0]), 0, 0 }, + { "mmDP3_DP_LINK_CNTL", REG_MMIO, 0x2408, 2, &mmDP3_DP_LINK_CNTL[0], sizeof(mmDP3_DP_LINK_CNTL)/sizeof(mmDP3_DP_LINK_CNTL[0]), 0, 0 }, + { "mmDP3_DP_PIXEL_FORMAT", REG_MMIO, 0x2409, 2, &mmDP3_DP_PIXEL_FORMAT[0], sizeof(mmDP3_DP_PIXEL_FORMAT)/sizeof(mmDP3_DP_PIXEL_FORMAT[0]), 0, 0 }, + { "mmDP3_DP_MSA_COLORIMETRY", REG_MMIO, 0x240a, 2, &mmDP3_DP_MSA_COLORIMETRY[0], sizeof(mmDP3_DP_MSA_COLORIMETRY)/sizeof(mmDP3_DP_MSA_COLORIMETRY[0]), 0, 0 }, + { "mmDP3_DP_CONFIG", REG_MMIO, 0x240b, 2, &mmDP3_DP_CONFIG[0], sizeof(mmDP3_DP_CONFIG)/sizeof(mmDP3_DP_CONFIG[0]), 0, 0 }, + { "mmDP3_DP_VID_STREAM_CNTL", REG_MMIO, 0x240c, 2, &mmDP3_DP_VID_STREAM_CNTL[0], sizeof(mmDP3_DP_VID_STREAM_CNTL)/sizeof(mmDP3_DP_VID_STREAM_CNTL[0]), 0, 0 }, + { "mmDP3_DP_STEER_FIFO", REG_MMIO, 0x240d, 2, &mmDP3_DP_STEER_FIFO[0], sizeof(mmDP3_DP_STEER_FIFO)/sizeof(mmDP3_DP_STEER_FIFO[0]), 0, 0 }, + { "mmDP3_DP_MSA_MISC", REG_MMIO, 0x240e, 2, &mmDP3_DP_MSA_MISC[0], sizeof(mmDP3_DP_MSA_MISC)/sizeof(mmDP3_DP_MSA_MISC[0]), 0, 0 }, + { "mmDP3_DP_VID_TIMING", REG_MMIO, 0x2410, 2, &mmDP3_DP_VID_TIMING[0], sizeof(mmDP3_DP_VID_TIMING)/sizeof(mmDP3_DP_VID_TIMING[0]), 0, 0 }, + { "mmDP3_DP_VID_N", REG_MMIO, 0x2411, 2, &mmDP3_DP_VID_N[0], sizeof(mmDP3_DP_VID_N)/sizeof(mmDP3_DP_VID_N[0]), 0, 0 }, + { "mmDP3_DP_VID_M", REG_MMIO, 0x2412, 2, &mmDP3_DP_VID_M[0], sizeof(mmDP3_DP_VID_M)/sizeof(mmDP3_DP_VID_M[0]), 0, 0 }, + { "mmDP3_DP_LINK_FRAMING_CNTL", REG_MMIO, 0x2413, 2, &mmDP3_DP_LINK_FRAMING_CNTL[0], sizeof(mmDP3_DP_LINK_FRAMING_CNTL)/sizeof(mmDP3_DP_LINK_FRAMING_CNTL[0]), 0, 0 }, + { "mmDP3_DP_HBR2_EYE_PATTERN", REG_MMIO, 0x2414, 2, &mmDP3_DP_HBR2_EYE_PATTERN[0], sizeof(mmDP3_DP_HBR2_EYE_PATTERN)/sizeof(mmDP3_DP_HBR2_EYE_PATTERN[0]), 0, 0 }, + { "mmDP3_DP_VID_MSA_VBID", REG_MMIO, 0x2415, 2, &mmDP3_DP_VID_MSA_VBID[0], sizeof(mmDP3_DP_VID_MSA_VBID)/sizeof(mmDP3_DP_VID_MSA_VBID[0]), 0, 0 }, + { "mmDP3_DP_VID_INTERRUPT_CNTL", REG_MMIO, 0x2416, 2, &mmDP3_DP_VID_INTERRUPT_CNTL[0], sizeof(mmDP3_DP_VID_INTERRUPT_CNTL)/sizeof(mmDP3_DP_VID_INTERRUPT_CNTL[0]), 0, 0 }, + { "mmDP3_DP_DPHY_CNTL", REG_MMIO, 0x2417, 2, &mmDP3_DP_DPHY_CNTL[0], sizeof(mmDP3_DP_DPHY_CNTL)/sizeof(mmDP3_DP_DPHY_CNTL[0]), 0, 0 }, + { "mmDP3_DP_DPHY_TRAINING_PATTERN_SEL", REG_MMIO, 0x2418, 2, &mmDP3_DP_DPHY_TRAINING_PATTERN_SEL[0], sizeof(mmDP3_DP_DPHY_TRAINING_PATTERN_SEL)/sizeof(mmDP3_DP_DPHY_TRAINING_PATTERN_SEL[0]), 0, 0 }, + { "mmDP3_DP_DPHY_SYM0", REG_MMIO, 0x2419, 2, &mmDP3_DP_DPHY_SYM0[0], sizeof(mmDP3_DP_DPHY_SYM0)/sizeof(mmDP3_DP_DPHY_SYM0[0]), 0, 0 }, + { "mmDP3_DP_DPHY_SYM1", REG_MMIO, 0x241a, 2, &mmDP3_DP_DPHY_SYM1[0], sizeof(mmDP3_DP_DPHY_SYM1)/sizeof(mmDP3_DP_DPHY_SYM1[0]), 0, 0 }, + { "mmDP3_DP_DPHY_SYM2", REG_MMIO, 0x241b, 2, &mmDP3_DP_DPHY_SYM2[0], sizeof(mmDP3_DP_DPHY_SYM2)/sizeof(mmDP3_DP_DPHY_SYM2[0]), 0, 0 }, + { "mmDP3_DP_DPHY_8B10B_CNTL", REG_MMIO, 0x241c, 2, &mmDP3_DP_DPHY_8B10B_CNTL[0], sizeof(mmDP3_DP_DPHY_8B10B_CNTL)/sizeof(mmDP3_DP_DPHY_8B10B_CNTL[0]), 0, 0 }, + { "mmDP3_DP_DPHY_PRBS_CNTL", REG_MMIO, 0x241d, 2, &mmDP3_DP_DPHY_PRBS_CNTL[0], sizeof(mmDP3_DP_DPHY_PRBS_CNTL)/sizeof(mmDP3_DP_DPHY_PRBS_CNTL[0]), 0, 0 }, + { "mmDP3_DP_DPHY_SCRAM_CNTL", REG_MMIO, 0x241e, 2, &mmDP3_DP_DPHY_SCRAM_CNTL[0], sizeof(mmDP3_DP_DPHY_SCRAM_CNTL)/sizeof(mmDP3_DP_DPHY_SCRAM_CNTL[0]), 0, 0 }, + { "mmDP3_DP_DPHY_CRC_EN", REG_MMIO, 0x241f, 2, &mmDP3_DP_DPHY_CRC_EN[0], sizeof(mmDP3_DP_DPHY_CRC_EN)/sizeof(mmDP3_DP_DPHY_CRC_EN[0]), 0, 0 }, + { "mmDP3_DP_DPHY_CRC_CNTL", REG_MMIO, 0x2420, 2, &mmDP3_DP_DPHY_CRC_CNTL[0], sizeof(mmDP3_DP_DPHY_CRC_CNTL)/sizeof(mmDP3_DP_DPHY_CRC_CNTL[0]), 0, 0 }, + { "mmDP3_DP_DPHY_CRC_RESULT", REG_MMIO, 0x2421, 2, &mmDP3_DP_DPHY_CRC_RESULT[0], sizeof(mmDP3_DP_DPHY_CRC_RESULT)/sizeof(mmDP3_DP_DPHY_CRC_RESULT[0]), 0, 0 }, + { "mmDP3_DP_DPHY_CRC_MST_CNTL", REG_MMIO, 0x2422, 2, &mmDP3_DP_DPHY_CRC_MST_CNTL[0], sizeof(mmDP3_DP_DPHY_CRC_MST_CNTL)/sizeof(mmDP3_DP_DPHY_CRC_MST_CNTL[0]), 0, 0 }, + { "mmDP3_DP_DPHY_CRC_MST_STATUS", REG_MMIO, 0x2423, 2, &mmDP3_DP_DPHY_CRC_MST_STATUS[0], sizeof(mmDP3_DP_DPHY_CRC_MST_STATUS)/sizeof(mmDP3_DP_DPHY_CRC_MST_STATUS[0]), 0, 0 }, + { "mmDP3_DP_DPHY_FAST_TRAINING", REG_MMIO, 0x2424, 2, &mmDP3_DP_DPHY_FAST_TRAINING[0], sizeof(mmDP3_DP_DPHY_FAST_TRAINING)/sizeof(mmDP3_DP_DPHY_FAST_TRAINING[0]), 0, 0 }, + { "mmDP3_DP_DPHY_FAST_TRAINING_STATUS", REG_MMIO, 0x2425, 2, &mmDP3_DP_DPHY_FAST_TRAINING_STATUS[0], sizeof(mmDP3_DP_DPHY_FAST_TRAINING_STATUS)/sizeof(mmDP3_DP_DPHY_FAST_TRAINING_STATUS[0]), 0, 0 }, + { "mmDP3_DP_SEC_CNTL", REG_MMIO, 0x242b, 2, &mmDP3_DP_SEC_CNTL[0], sizeof(mmDP3_DP_SEC_CNTL)/sizeof(mmDP3_DP_SEC_CNTL[0]), 0, 0 }, + { "mmDP3_DP_SEC_CNTL1", REG_MMIO, 0x242c, 2, &mmDP3_DP_SEC_CNTL1[0], sizeof(mmDP3_DP_SEC_CNTL1)/sizeof(mmDP3_DP_SEC_CNTL1[0]), 0, 0 }, + { "mmDP3_DP_SEC_FRAMING1", REG_MMIO, 0x242d, 2, &mmDP3_DP_SEC_FRAMING1[0], sizeof(mmDP3_DP_SEC_FRAMING1)/sizeof(mmDP3_DP_SEC_FRAMING1[0]), 0, 0 }, + { "mmDP3_DP_SEC_FRAMING2", REG_MMIO, 0x242e, 2, &mmDP3_DP_SEC_FRAMING2[0], sizeof(mmDP3_DP_SEC_FRAMING2)/sizeof(mmDP3_DP_SEC_FRAMING2[0]), 0, 0 }, + { "mmDP3_DP_SEC_FRAMING3", REG_MMIO, 0x242f, 2, &mmDP3_DP_SEC_FRAMING3[0], sizeof(mmDP3_DP_SEC_FRAMING3)/sizeof(mmDP3_DP_SEC_FRAMING3[0]), 0, 0 }, + { "mmDP3_DP_SEC_FRAMING4", REG_MMIO, 0x2430, 2, &mmDP3_DP_SEC_FRAMING4[0], sizeof(mmDP3_DP_SEC_FRAMING4)/sizeof(mmDP3_DP_SEC_FRAMING4[0]), 0, 0 }, + { "mmDP3_DP_SEC_AUD_N", REG_MMIO, 0x2431, 2, &mmDP3_DP_SEC_AUD_N[0], sizeof(mmDP3_DP_SEC_AUD_N)/sizeof(mmDP3_DP_SEC_AUD_N[0]), 0, 0 }, + { "mmDP3_DP_SEC_AUD_N_READBACK", REG_MMIO, 0x2432, 2, &mmDP3_DP_SEC_AUD_N_READBACK[0], sizeof(mmDP3_DP_SEC_AUD_N_READBACK)/sizeof(mmDP3_DP_SEC_AUD_N_READBACK[0]), 0, 0 }, + { "mmDP3_DP_SEC_AUD_M", REG_MMIO, 0x2433, 2, &mmDP3_DP_SEC_AUD_M[0], sizeof(mmDP3_DP_SEC_AUD_M)/sizeof(mmDP3_DP_SEC_AUD_M[0]), 0, 0 }, + { "mmDP3_DP_SEC_AUD_M_READBACK", REG_MMIO, 0x2434, 2, &mmDP3_DP_SEC_AUD_M_READBACK[0], sizeof(mmDP3_DP_SEC_AUD_M_READBACK)/sizeof(mmDP3_DP_SEC_AUD_M_READBACK[0]), 0, 0 }, + { "mmDP3_DP_SEC_TIMESTAMP", REG_MMIO, 0x2435, 2, &mmDP3_DP_SEC_TIMESTAMP[0], sizeof(mmDP3_DP_SEC_TIMESTAMP)/sizeof(mmDP3_DP_SEC_TIMESTAMP[0]), 0, 0 }, + { "mmDP3_DP_SEC_PACKET_CNTL", REG_MMIO, 0x2436, 2, &mmDP3_DP_SEC_PACKET_CNTL[0], sizeof(mmDP3_DP_SEC_PACKET_CNTL)/sizeof(mmDP3_DP_SEC_PACKET_CNTL[0]), 0, 0 }, + { "mmDP3_DP_MSE_RATE_CNTL", REG_MMIO, 0x2437, 2, &mmDP3_DP_MSE_RATE_CNTL[0], sizeof(mmDP3_DP_MSE_RATE_CNTL)/sizeof(mmDP3_DP_MSE_RATE_CNTL[0]), 0, 0 }, + { "mmDP3_DP_MSE_RATE_UPDATE", REG_MMIO, 0x2439, 2, &mmDP3_DP_MSE_RATE_UPDATE[0], sizeof(mmDP3_DP_MSE_RATE_UPDATE)/sizeof(mmDP3_DP_MSE_RATE_UPDATE[0]), 0, 0 }, + { "mmDP3_DP_MSE_SAT0", REG_MMIO, 0x243a, 2, &mmDP3_DP_MSE_SAT0[0], sizeof(mmDP3_DP_MSE_SAT0)/sizeof(mmDP3_DP_MSE_SAT0[0]), 0, 0 }, + { "mmDP3_DP_MSE_SAT1", REG_MMIO, 0x243b, 2, &mmDP3_DP_MSE_SAT1[0], sizeof(mmDP3_DP_MSE_SAT1)/sizeof(mmDP3_DP_MSE_SAT1[0]), 0, 0 }, + { "mmDP3_DP_MSE_SAT2", REG_MMIO, 0x243c, 2, &mmDP3_DP_MSE_SAT2[0], sizeof(mmDP3_DP_MSE_SAT2)/sizeof(mmDP3_DP_MSE_SAT2[0]), 0, 0 }, + { "mmDP3_DP_MSE_SAT_UPDATE", REG_MMIO, 0x243d, 2, &mmDP3_DP_MSE_SAT_UPDATE[0], sizeof(mmDP3_DP_MSE_SAT_UPDATE)/sizeof(mmDP3_DP_MSE_SAT_UPDATE[0]), 0, 0 }, + { "mmDP3_DP_MSE_LINK_TIMING", REG_MMIO, 0x243e, 2, &mmDP3_DP_MSE_LINK_TIMING[0], sizeof(mmDP3_DP_MSE_LINK_TIMING)/sizeof(mmDP3_DP_MSE_LINK_TIMING[0]), 0, 0 }, + { "mmDP3_DP_MSE_MISC_CNTL", REG_MMIO, 0x243f, 2, &mmDP3_DP_MSE_MISC_CNTL[0], sizeof(mmDP3_DP_MSE_MISC_CNTL)/sizeof(mmDP3_DP_MSE_MISC_CNTL[0]), 0, 0 }, + { "mmDP3_DP_DPHY_BS_SR_SWAP_CNTL", REG_MMIO, 0x2444, 2, &mmDP3_DP_DPHY_BS_SR_SWAP_CNTL[0], sizeof(mmDP3_DP_DPHY_BS_SR_SWAP_CNTL)/sizeof(mmDP3_DP_DPHY_BS_SR_SWAP_CNTL[0]), 0, 0 }, + { "mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL", REG_MMIO, 0x2445, 2, &mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL[0], sizeof(mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL)/sizeof(mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL[0]), 0, 0 }, + { "mmDP3_DP_MSE_SAT0_STATUS", REG_MMIO, 0x2447, 2, &mmDP3_DP_MSE_SAT0_STATUS[0], sizeof(mmDP3_DP_MSE_SAT0_STATUS)/sizeof(mmDP3_DP_MSE_SAT0_STATUS[0]), 0, 0 }, + { "mmDP3_DP_MSE_SAT1_STATUS", REG_MMIO, 0x2448, 2, &mmDP3_DP_MSE_SAT1_STATUS[0], sizeof(mmDP3_DP_MSE_SAT1_STATUS)/sizeof(mmDP3_DP_MSE_SAT1_STATUS[0]), 0, 0 }, + { "mmDP3_DP_MSE_SAT2_STATUS", REG_MMIO, 0x2449, 2, &mmDP3_DP_MSE_SAT2_STATUS[0], sizeof(mmDP3_DP_MSE_SAT2_STATUS)/sizeof(mmDP3_DP_MSE_SAT2_STATUS[0]), 0, 0 }, + { "mmDP3_DP_MSA_TIMING_PARAM1", REG_MMIO, 0x244c, 2, &mmDP3_DP_MSA_TIMING_PARAM1[0], sizeof(mmDP3_DP_MSA_TIMING_PARAM1)/sizeof(mmDP3_DP_MSA_TIMING_PARAM1[0]), 0, 0 }, + { "mmDP3_DP_MSA_TIMING_PARAM2", REG_MMIO, 0x244d, 2, &mmDP3_DP_MSA_TIMING_PARAM2[0], sizeof(mmDP3_DP_MSA_TIMING_PARAM2)/sizeof(mmDP3_DP_MSA_TIMING_PARAM2[0]), 0, 0 }, + { "mmDP3_DP_MSA_TIMING_PARAM3", REG_MMIO, 0x244e, 2, &mmDP3_DP_MSA_TIMING_PARAM3[0], sizeof(mmDP3_DP_MSA_TIMING_PARAM3)/sizeof(mmDP3_DP_MSA_TIMING_PARAM3[0]), 0, 0 }, + { "mmDP3_DP_MSA_TIMING_PARAM4", REG_MMIO, 0x244f, 2, &mmDP3_DP_MSA_TIMING_PARAM4[0], sizeof(mmDP3_DP_MSA_TIMING_PARAM4)/sizeof(mmDP3_DP_MSA_TIMING_PARAM4[0]), 0, 0 }, + { "mmDP3_DP_MSO_CNTL", REG_MMIO, 0x2450, 2, &mmDP3_DP_MSO_CNTL[0], sizeof(mmDP3_DP_MSO_CNTL)/sizeof(mmDP3_DP_MSO_CNTL[0]), 0, 0 }, + { "mmDP3_DP_MSO_CNTL1", REG_MMIO, 0x2451, 2, &mmDP3_DP_MSO_CNTL1[0], sizeof(mmDP3_DP_MSO_CNTL1)/sizeof(mmDP3_DP_MSO_CNTL1[0]), 0, 0 }, + { "mmDP3_DP_DSC_CNTL", REG_MMIO, 0x2452, 2, &mmDP3_DP_DSC_CNTL[0], sizeof(mmDP3_DP_DSC_CNTL)/sizeof(mmDP3_DP_DSC_CNTL[0]), 0, 0 }, + { "mmDP3_DP_SEC_CNTL2", REG_MMIO, 0x2453, 2, &mmDP3_DP_SEC_CNTL2[0], sizeof(mmDP3_DP_SEC_CNTL2)/sizeof(mmDP3_DP_SEC_CNTL2[0]), 0, 0 }, + { "mmDP3_DP_SEC_CNTL3", REG_MMIO, 0x2454, 2, &mmDP3_DP_SEC_CNTL3[0], sizeof(mmDP3_DP_SEC_CNTL3)/sizeof(mmDP3_DP_SEC_CNTL3[0]), 0, 0 }, + { "mmDP3_DP_SEC_CNTL4", REG_MMIO, 0x2455, 2, &mmDP3_DP_SEC_CNTL4[0], sizeof(mmDP3_DP_SEC_CNTL4)/sizeof(mmDP3_DP_SEC_CNTL4[0]), 0, 0 }, + { "mmDP3_DP_SEC_CNTL5", REG_MMIO, 0x2456, 2, &mmDP3_DP_SEC_CNTL5[0], sizeof(mmDP3_DP_SEC_CNTL5)/sizeof(mmDP3_DP_SEC_CNTL5[0]), 0, 0 }, + { "mmDP3_DP_SEC_CNTL6", REG_MMIO, 0x2457, 2, &mmDP3_DP_SEC_CNTL6[0], sizeof(mmDP3_DP_SEC_CNTL6)/sizeof(mmDP3_DP_SEC_CNTL6[0]), 0, 0 }, + { "mmDP3_DP_SEC_CNTL7", REG_MMIO, 0x2458, 2, &mmDP3_DP_SEC_CNTL7[0], sizeof(mmDP3_DP_SEC_CNTL7)/sizeof(mmDP3_DP_SEC_CNTL7[0]), 0, 0 }, + { "mmDP3_DP_DB_CNTL", REG_MMIO, 0x2459, 2, &mmDP3_DP_DB_CNTL[0], sizeof(mmDP3_DP_DB_CNTL)/sizeof(mmDP3_DP_DB_CNTL[0]), 0, 0 }, + { "mmDP3_DP_MSA_VBID_MISC", REG_MMIO, 0x245a, 2, &mmDP3_DP_MSA_VBID_MISC[0], sizeof(mmDP3_DP_MSA_VBID_MISC)/sizeof(mmDP3_DP_MSA_VBID_MISC[0]), 0, 0 }, + { "mmDIG4_DIG_FE_CNTL", REG_MMIO, 0x2468, 2, &mmDIG4_DIG_FE_CNTL[0], sizeof(mmDIG4_DIG_FE_CNTL)/sizeof(mmDIG4_DIG_FE_CNTL[0]), 0, 0 }, + { "mmDIG4_DIG_OUTPUT_CRC_CNTL", REG_MMIO, 0x2469, 2, &mmDIG4_DIG_OUTPUT_CRC_CNTL[0], sizeof(mmDIG4_DIG_OUTPUT_CRC_CNTL)/sizeof(mmDIG4_DIG_OUTPUT_CRC_CNTL[0]), 0, 0 }, + { "mmDIG4_DIG_OUTPUT_CRC_RESULT", REG_MMIO, 0x246a, 2, &mmDIG4_DIG_OUTPUT_CRC_RESULT[0], sizeof(mmDIG4_DIG_OUTPUT_CRC_RESULT)/sizeof(mmDIG4_DIG_OUTPUT_CRC_RESULT[0]), 0, 0 }, + { "mmDIG4_DIG_CLOCK_PATTERN", REG_MMIO, 0x246b, 2, &mmDIG4_DIG_CLOCK_PATTERN[0], sizeof(mmDIG4_DIG_CLOCK_PATTERN)/sizeof(mmDIG4_DIG_CLOCK_PATTERN[0]), 0, 0 }, + { "mmDIG4_DIG_TEST_PATTERN", REG_MMIO, 0x246c, 2, &mmDIG4_DIG_TEST_PATTERN[0], sizeof(mmDIG4_DIG_TEST_PATTERN)/sizeof(mmDIG4_DIG_TEST_PATTERN[0]), 0, 0 }, + { "mmDIG4_DIG_RANDOM_PATTERN_SEED", REG_MMIO, 0x246d, 2, &mmDIG4_DIG_RANDOM_PATTERN_SEED[0], sizeof(mmDIG4_DIG_RANDOM_PATTERN_SEED)/sizeof(mmDIG4_DIG_RANDOM_PATTERN_SEED[0]), 0, 0 }, + { "mmDIG4_DIG_FIFO_STATUS", REG_MMIO, 0x246e, 2, &mmDIG4_DIG_FIFO_STATUS[0], sizeof(mmDIG4_DIG_FIFO_STATUS)/sizeof(mmDIG4_DIG_FIFO_STATUS[0]), 0, 0 }, + { "mmDIG4_HDMI_CONTROL", REG_MMIO, 0x2471, 2, &mmDIG4_HDMI_CONTROL[0], sizeof(mmDIG4_HDMI_CONTROL)/sizeof(mmDIG4_HDMI_CONTROL[0]), 0, 0 }, + { "mmDIG4_HDMI_STATUS", REG_MMIO, 0x2472, 2, &mmDIG4_HDMI_STATUS[0], sizeof(mmDIG4_HDMI_STATUS)/sizeof(mmDIG4_HDMI_STATUS[0]), 0, 0 }, + { "mmDIG4_HDMI_AUDIO_PACKET_CONTROL", REG_MMIO, 0x2473, 2, &mmDIG4_HDMI_AUDIO_PACKET_CONTROL[0], sizeof(mmDIG4_HDMI_AUDIO_PACKET_CONTROL)/sizeof(mmDIG4_HDMI_AUDIO_PACKET_CONTROL[0]), 0, 0 }, + { "mmDIG4_HDMI_ACR_PACKET_CONTROL", REG_MMIO, 0x2474, 2, &mmDIG4_HDMI_ACR_PACKET_CONTROL[0], sizeof(mmDIG4_HDMI_ACR_PACKET_CONTROL)/sizeof(mmDIG4_HDMI_ACR_PACKET_CONTROL[0]), 0, 0 }, + { "mmDIG4_HDMI_VBI_PACKET_CONTROL", REG_MMIO, 0x2475, 2, &mmDIG4_HDMI_VBI_PACKET_CONTROL[0], sizeof(mmDIG4_HDMI_VBI_PACKET_CONTROL)/sizeof(mmDIG4_HDMI_VBI_PACKET_CONTROL[0]), 0, 0 }, + { "mmDIG4_HDMI_INFOFRAME_CONTROL0", REG_MMIO, 0x2476, 2, &mmDIG4_HDMI_INFOFRAME_CONTROL0[0], sizeof(mmDIG4_HDMI_INFOFRAME_CONTROL0)/sizeof(mmDIG4_HDMI_INFOFRAME_CONTROL0[0]), 0, 0 }, + { "mmDIG4_HDMI_INFOFRAME_CONTROL1", REG_MMIO, 0x2477, 2, &mmDIG4_HDMI_INFOFRAME_CONTROL1[0], sizeof(mmDIG4_HDMI_INFOFRAME_CONTROL1)/sizeof(mmDIG4_HDMI_INFOFRAME_CONTROL1[0]), 0, 0 }, + { "mmDIG4_HDMI_GENERIC_PACKET_CONTROL0", REG_MMIO, 0x2478, 2, &mmDIG4_HDMI_GENERIC_PACKET_CONTROL0[0], sizeof(mmDIG4_HDMI_GENERIC_PACKET_CONTROL0)/sizeof(mmDIG4_HDMI_GENERIC_PACKET_CONTROL0[0]), 0, 0 }, + { "mmDIG4_AFMT_INTERRUPT_STATUS", REG_MMIO, 0x2479, 2, NULL, 0, 0, 0 }, + { "mmDIG4_HDMI_GC", REG_MMIO, 0x247b, 2, &mmDIG4_HDMI_GC[0], sizeof(mmDIG4_HDMI_GC)/sizeof(mmDIG4_HDMI_GC[0]), 0, 0 }, + { "mmDIG4_AFMT_AUDIO_PACKET_CONTROL2", REG_MMIO, 0x247c, 2, &mmDIG4_AFMT_AUDIO_PACKET_CONTROL2[0], sizeof(mmDIG4_AFMT_AUDIO_PACKET_CONTROL2)/sizeof(mmDIG4_AFMT_AUDIO_PACKET_CONTROL2[0]), 0, 0 }, + { "mmDIG4_AFMT_ISRC1_0", REG_MMIO, 0x247d, 2, &mmDIG4_AFMT_ISRC1_0[0], sizeof(mmDIG4_AFMT_ISRC1_0)/sizeof(mmDIG4_AFMT_ISRC1_0[0]), 0, 0 }, + { "mmDIG4_AFMT_ISRC1_1", REG_MMIO, 0x247e, 2, &mmDIG4_AFMT_ISRC1_1[0], sizeof(mmDIG4_AFMT_ISRC1_1)/sizeof(mmDIG4_AFMT_ISRC1_1[0]), 0, 0 }, + { "mmDIG4_AFMT_ISRC1_2", REG_MMIO, 0x247f, 2, &mmDIG4_AFMT_ISRC1_2[0], sizeof(mmDIG4_AFMT_ISRC1_2)/sizeof(mmDIG4_AFMT_ISRC1_2[0]), 0, 0 }, + { "mmDIG4_AFMT_ISRC1_3", REG_MMIO, 0x2480, 2, &mmDIG4_AFMT_ISRC1_3[0], sizeof(mmDIG4_AFMT_ISRC1_3)/sizeof(mmDIG4_AFMT_ISRC1_3[0]), 0, 0 }, + { "mmDIG4_AFMT_ISRC1_4", REG_MMIO, 0x2481, 2, &mmDIG4_AFMT_ISRC1_4[0], sizeof(mmDIG4_AFMT_ISRC1_4)/sizeof(mmDIG4_AFMT_ISRC1_4[0]), 0, 0 }, + { "mmDIG4_AFMT_ISRC2_0", REG_MMIO, 0x2482, 2, &mmDIG4_AFMT_ISRC2_0[0], sizeof(mmDIG4_AFMT_ISRC2_0)/sizeof(mmDIG4_AFMT_ISRC2_0[0]), 0, 0 }, + { "mmDIG4_AFMT_ISRC2_1", REG_MMIO, 0x2483, 2, &mmDIG4_AFMT_ISRC2_1[0], sizeof(mmDIG4_AFMT_ISRC2_1)/sizeof(mmDIG4_AFMT_ISRC2_1[0]), 0, 0 }, + { "mmDIG4_AFMT_ISRC2_2", REG_MMIO, 0x2484, 2, &mmDIG4_AFMT_ISRC2_2[0], sizeof(mmDIG4_AFMT_ISRC2_2)/sizeof(mmDIG4_AFMT_ISRC2_2[0]), 0, 0 }, + { "mmDIG4_AFMT_ISRC2_3", REG_MMIO, 0x2485, 2, &mmDIG4_AFMT_ISRC2_3[0], sizeof(mmDIG4_AFMT_ISRC2_3)/sizeof(mmDIG4_AFMT_ISRC2_3[0]), 0, 0 }, + { "mmDIG4_HDMI_GENERIC_PACKET_CONTROL2", REG_MMIO, 0x2486, 2, &mmDIG4_HDMI_GENERIC_PACKET_CONTROL2[0], sizeof(mmDIG4_HDMI_GENERIC_PACKET_CONTROL2)/sizeof(mmDIG4_HDMI_GENERIC_PACKET_CONTROL2[0]), 0, 0 }, + { "mmDIG4_HDMI_GENERIC_PACKET_CONTROL3", REG_MMIO, 0x2487, 2, &mmDIG4_HDMI_GENERIC_PACKET_CONTROL3[0], sizeof(mmDIG4_HDMI_GENERIC_PACKET_CONTROL3)/sizeof(mmDIG4_HDMI_GENERIC_PACKET_CONTROL3[0]), 0, 0 }, + { "mmDIG4_HDMI_DB_CONTROL", REG_MMIO, 0x2488, 2, &mmDIG4_HDMI_DB_CONTROL[0], sizeof(mmDIG4_HDMI_DB_CONTROL)/sizeof(mmDIG4_HDMI_DB_CONTROL[0]), 0, 0 }, + { "mmDIG4_AFMT_MPEG_INFO0", REG_MMIO, 0x248a, 2, &mmDIG4_AFMT_MPEG_INFO0[0], sizeof(mmDIG4_AFMT_MPEG_INFO0)/sizeof(mmDIG4_AFMT_MPEG_INFO0[0]), 0, 0 }, + { "mmDIG4_AFMT_MPEG_INFO1", REG_MMIO, 0x248b, 2, &mmDIG4_AFMT_MPEG_INFO1[0], sizeof(mmDIG4_AFMT_MPEG_INFO1)/sizeof(mmDIG4_AFMT_MPEG_INFO1[0]), 0, 0 }, + { "mmDIG4_AFMT_GENERIC_HDR", REG_MMIO, 0x248c, 2, &mmDIG4_AFMT_GENERIC_HDR[0], sizeof(mmDIG4_AFMT_GENERIC_HDR)/sizeof(mmDIG4_AFMT_GENERIC_HDR[0]), 0, 0 }, + { "mmDIG4_AFMT_GENERIC_0", REG_MMIO, 0x248d, 2, &mmDIG4_AFMT_GENERIC_0[0], sizeof(mmDIG4_AFMT_GENERIC_0)/sizeof(mmDIG4_AFMT_GENERIC_0[0]), 0, 0 }, + { "mmDIG4_AFMT_GENERIC_1", REG_MMIO, 0x248e, 2, &mmDIG4_AFMT_GENERIC_1[0], sizeof(mmDIG4_AFMT_GENERIC_1)/sizeof(mmDIG4_AFMT_GENERIC_1[0]), 0, 0 }, + { "mmDIG4_AFMT_GENERIC_2", REG_MMIO, 0x248f, 2, &mmDIG4_AFMT_GENERIC_2[0], sizeof(mmDIG4_AFMT_GENERIC_2)/sizeof(mmDIG4_AFMT_GENERIC_2[0]), 0, 0 }, + { "mmDIG4_AFMT_GENERIC_3", REG_MMIO, 0x2490, 2, &mmDIG4_AFMT_GENERIC_3[0], sizeof(mmDIG4_AFMT_GENERIC_3)/sizeof(mmDIG4_AFMT_GENERIC_3[0]), 0, 0 }, + { "mmDIG4_AFMT_GENERIC_4", REG_MMIO, 0x2491, 2, &mmDIG4_AFMT_GENERIC_4[0], sizeof(mmDIG4_AFMT_GENERIC_4)/sizeof(mmDIG4_AFMT_GENERIC_4[0]), 0, 0 }, + { "mmDIG4_AFMT_GENERIC_5", REG_MMIO, 0x2492, 2, &mmDIG4_AFMT_GENERIC_5[0], sizeof(mmDIG4_AFMT_GENERIC_5)/sizeof(mmDIG4_AFMT_GENERIC_5[0]), 0, 0 }, + { "mmDIG4_AFMT_GENERIC_6", REG_MMIO, 0x2493, 2, &mmDIG4_AFMT_GENERIC_6[0], sizeof(mmDIG4_AFMT_GENERIC_6)/sizeof(mmDIG4_AFMT_GENERIC_6[0]), 0, 0 }, + { "mmDIG4_AFMT_GENERIC_7", REG_MMIO, 0x2494, 2, &mmDIG4_AFMT_GENERIC_7[0], sizeof(mmDIG4_AFMT_GENERIC_7)/sizeof(mmDIG4_AFMT_GENERIC_7[0]), 0, 0 }, + { "mmDIG4_HDMI_GENERIC_PACKET_CONTROL1", REG_MMIO, 0x2495, 2, &mmDIG4_HDMI_GENERIC_PACKET_CONTROL1[0], sizeof(mmDIG4_HDMI_GENERIC_PACKET_CONTROL1)/sizeof(mmDIG4_HDMI_GENERIC_PACKET_CONTROL1[0]), 0, 0 }, + { "mmDIG4_HDMI_ACR_32_0", REG_MMIO, 0x2496, 2, &mmDIG4_HDMI_ACR_32_0[0], sizeof(mmDIG4_HDMI_ACR_32_0)/sizeof(mmDIG4_HDMI_ACR_32_0[0]), 0, 0 }, + { "mmDIG4_HDMI_ACR_32_1", REG_MMIO, 0x2497, 2, &mmDIG4_HDMI_ACR_32_1[0], sizeof(mmDIG4_HDMI_ACR_32_1)/sizeof(mmDIG4_HDMI_ACR_32_1[0]), 0, 0 }, + { "mmDIG4_HDMI_ACR_44_0", REG_MMIO, 0x2498, 2, &mmDIG4_HDMI_ACR_44_0[0], sizeof(mmDIG4_HDMI_ACR_44_0)/sizeof(mmDIG4_HDMI_ACR_44_0[0]), 0, 0 }, + { "mmDIG4_HDMI_ACR_44_1", REG_MMIO, 0x2499, 2, &mmDIG4_HDMI_ACR_44_1[0], sizeof(mmDIG4_HDMI_ACR_44_1)/sizeof(mmDIG4_HDMI_ACR_44_1[0]), 0, 0 }, + { "mmDIG4_HDMI_ACR_48_0", REG_MMIO, 0x249a, 2, &mmDIG4_HDMI_ACR_48_0[0], sizeof(mmDIG4_HDMI_ACR_48_0)/sizeof(mmDIG4_HDMI_ACR_48_0[0]), 0, 0 }, + { "mmDIG4_HDMI_ACR_48_1", REG_MMIO, 0x249b, 2, &mmDIG4_HDMI_ACR_48_1[0], sizeof(mmDIG4_HDMI_ACR_48_1)/sizeof(mmDIG4_HDMI_ACR_48_1[0]), 0, 0 }, + { "mmDIG4_HDMI_ACR_STATUS_0", REG_MMIO, 0x249c, 2, &mmDIG4_HDMI_ACR_STATUS_0[0], sizeof(mmDIG4_HDMI_ACR_STATUS_0)/sizeof(mmDIG4_HDMI_ACR_STATUS_0[0]), 0, 0 }, + { "mmDIG4_HDMI_ACR_STATUS_1", REG_MMIO, 0x249d, 2, &mmDIG4_HDMI_ACR_STATUS_1[0], sizeof(mmDIG4_HDMI_ACR_STATUS_1)/sizeof(mmDIG4_HDMI_ACR_STATUS_1[0]), 0, 0 }, + { "mmDIG4_AFMT_AUDIO_INFO0", REG_MMIO, 0x249e, 2, &mmDIG4_AFMT_AUDIO_INFO0[0], sizeof(mmDIG4_AFMT_AUDIO_INFO0)/sizeof(mmDIG4_AFMT_AUDIO_INFO0[0]), 0, 0 }, + { "mmDIG4_AFMT_AUDIO_INFO1", REG_MMIO, 0x249f, 2, &mmDIG4_AFMT_AUDIO_INFO1[0], sizeof(mmDIG4_AFMT_AUDIO_INFO1)/sizeof(mmDIG4_AFMT_AUDIO_INFO1[0]), 0, 0 }, + { "mmDIG4_AFMT_60958_0", REG_MMIO, 0x24a0, 2, &mmDIG4_AFMT_60958_0[0], sizeof(mmDIG4_AFMT_60958_0)/sizeof(mmDIG4_AFMT_60958_0[0]), 0, 0 }, + { "mmDIG4_AFMT_60958_1", REG_MMIO, 0x24a1, 2, &mmDIG4_AFMT_60958_1[0], sizeof(mmDIG4_AFMT_60958_1)/sizeof(mmDIG4_AFMT_60958_1[0]), 0, 0 }, + { "mmDIG4_AFMT_AUDIO_CRC_CONTROL", REG_MMIO, 0x24a2, 2, &mmDIG4_AFMT_AUDIO_CRC_CONTROL[0], sizeof(mmDIG4_AFMT_AUDIO_CRC_CONTROL)/sizeof(mmDIG4_AFMT_AUDIO_CRC_CONTROL[0]), 0, 0 }, + { "mmDIG4_AFMT_RAMP_CONTROL0", REG_MMIO, 0x24a3, 2, &mmDIG4_AFMT_RAMP_CONTROL0[0], sizeof(mmDIG4_AFMT_RAMP_CONTROL0)/sizeof(mmDIG4_AFMT_RAMP_CONTROL0[0]), 0, 0 }, + { "mmDIG4_AFMT_RAMP_CONTROL1", REG_MMIO, 0x24a4, 2, &mmDIG4_AFMT_RAMP_CONTROL1[0], sizeof(mmDIG4_AFMT_RAMP_CONTROL1)/sizeof(mmDIG4_AFMT_RAMP_CONTROL1[0]), 0, 0 }, + { "mmDIG4_AFMT_RAMP_CONTROL2", REG_MMIO, 0x24a5, 2, &mmDIG4_AFMT_RAMP_CONTROL2[0], sizeof(mmDIG4_AFMT_RAMP_CONTROL2)/sizeof(mmDIG4_AFMT_RAMP_CONTROL2[0]), 0, 0 }, + { "mmDIG4_AFMT_RAMP_CONTROL3", REG_MMIO, 0x24a6, 2, &mmDIG4_AFMT_RAMP_CONTROL3[0], sizeof(mmDIG4_AFMT_RAMP_CONTROL3)/sizeof(mmDIG4_AFMT_RAMP_CONTROL3[0]), 0, 0 }, + { "mmDIG4_AFMT_60958_2", REG_MMIO, 0x24a7, 2, &mmDIG4_AFMT_60958_2[0], sizeof(mmDIG4_AFMT_60958_2)/sizeof(mmDIG4_AFMT_60958_2[0]), 0, 0 }, + { "mmDIG4_AFMT_AUDIO_CRC_RESULT", REG_MMIO, 0x24a8, 2, &mmDIG4_AFMT_AUDIO_CRC_RESULT[0], sizeof(mmDIG4_AFMT_AUDIO_CRC_RESULT)/sizeof(mmDIG4_AFMT_AUDIO_CRC_RESULT[0]), 0, 0 }, + { "mmDIG4_AFMT_STATUS", REG_MMIO, 0x24a9, 2, &mmDIG4_AFMT_STATUS[0], sizeof(mmDIG4_AFMT_STATUS)/sizeof(mmDIG4_AFMT_STATUS[0]), 0, 0 }, + { "mmDIG4_AFMT_AUDIO_PACKET_CONTROL", REG_MMIO, 0x24aa, 2, &mmDIG4_AFMT_AUDIO_PACKET_CONTROL[0], sizeof(mmDIG4_AFMT_AUDIO_PACKET_CONTROL)/sizeof(mmDIG4_AFMT_AUDIO_PACKET_CONTROL[0]), 0, 0 }, + { "mmDIG4_AFMT_VBI_PACKET_CONTROL", REG_MMIO, 0x24ab, 2, &mmDIG4_AFMT_VBI_PACKET_CONTROL[0], sizeof(mmDIG4_AFMT_VBI_PACKET_CONTROL)/sizeof(mmDIG4_AFMT_VBI_PACKET_CONTROL[0]), 0, 0 }, + { "mmDIG4_AFMT_INFOFRAME_CONTROL0", REG_MMIO, 0x24ac, 2, &mmDIG4_AFMT_INFOFRAME_CONTROL0[0], sizeof(mmDIG4_AFMT_INFOFRAME_CONTROL0)/sizeof(mmDIG4_AFMT_INFOFRAME_CONTROL0[0]), 0, 0 }, + { "mmDIG4_AFMT_AUDIO_SRC_CONTROL", REG_MMIO, 0x24ad, 2, &mmDIG4_AFMT_AUDIO_SRC_CONTROL[0], sizeof(mmDIG4_AFMT_AUDIO_SRC_CONTROL)/sizeof(mmDIG4_AFMT_AUDIO_SRC_CONTROL[0]), 0, 0 }, + { "mmDIG4_DIG_BE_CNTL", REG_MMIO, 0x24af, 2, &mmDIG4_DIG_BE_CNTL[0], sizeof(mmDIG4_DIG_BE_CNTL)/sizeof(mmDIG4_DIG_BE_CNTL[0]), 0, 0 }, + { "mmDIG4_DIG_BE_EN_CNTL", REG_MMIO, 0x24b0, 2, &mmDIG4_DIG_BE_EN_CNTL[0], sizeof(mmDIG4_DIG_BE_EN_CNTL)/sizeof(mmDIG4_DIG_BE_EN_CNTL[0]), 0, 0 }, + { "mmDIG4_TMDS_CNTL", REG_MMIO, 0x24d3, 2, &mmDIG4_TMDS_CNTL[0], sizeof(mmDIG4_TMDS_CNTL)/sizeof(mmDIG4_TMDS_CNTL[0]), 0, 0 }, + { "mmDIG4_TMDS_CONTROL_CHAR", REG_MMIO, 0x24d4, 2, &mmDIG4_TMDS_CONTROL_CHAR[0], sizeof(mmDIG4_TMDS_CONTROL_CHAR)/sizeof(mmDIG4_TMDS_CONTROL_CHAR[0]), 0, 0 }, + { "mmDIG4_TMDS_CONTROL0_FEEDBACK", REG_MMIO, 0x24d5, 2, &mmDIG4_TMDS_CONTROL0_FEEDBACK[0], sizeof(mmDIG4_TMDS_CONTROL0_FEEDBACK)/sizeof(mmDIG4_TMDS_CONTROL0_FEEDBACK[0]), 0, 0 }, + { "mmDIG4_TMDS_STEREOSYNC_CTL_SEL", REG_MMIO, 0x24d6, 2, &mmDIG4_TMDS_STEREOSYNC_CTL_SEL[0], sizeof(mmDIG4_TMDS_STEREOSYNC_CTL_SEL)/sizeof(mmDIG4_TMDS_STEREOSYNC_CTL_SEL[0]), 0, 0 }, + { "mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1", REG_MMIO, 0x24d7, 2, &mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1[0], sizeof(mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1)/sizeof(mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1[0]), 0, 0 }, + { "mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3", REG_MMIO, 0x24d8, 2, &mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3[0], sizeof(mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3)/sizeof(mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3[0]), 0, 0 }, + { "mmDIG4_TMDS_CTL_BITS", REG_MMIO, 0x24da, 2, &mmDIG4_TMDS_CTL_BITS[0], sizeof(mmDIG4_TMDS_CTL_BITS)/sizeof(mmDIG4_TMDS_CTL_BITS[0]), 0, 0 }, + { "mmDIG4_TMDS_DCBALANCER_CONTROL", REG_MMIO, 0x24db, 2, &mmDIG4_TMDS_DCBALANCER_CONTROL[0], sizeof(mmDIG4_TMDS_DCBALANCER_CONTROL)/sizeof(mmDIG4_TMDS_DCBALANCER_CONTROL[0]), 0, 0 }, + { "mmDIG4_TMDS_CTL0_1_GEN_CNTL", REG_MMIO, 0x24dd, 2, &mmDIG4_TMDS_CTL0_1_GEN_CNTL[0], sizeof(mmDIG4_TMDS_CTL0_1_GEN_CNTL)/sizeof(mmDIG4_TMDS_CTL0_1_GEN_CNTL[0]), 0, 0 }, + { "mmDIG4_TMDS_CTL2_3_GEN_CNTL", REG_MMIO, 0x24de, 2, &mmDIG4_TMDS_CTL2_3_GEN_CNTL[0], sizeof(mmDIG4_TMDS_CTL2_3_GEN_CNTL)/sizeof(mmDIG4_TMDS_CTL2_3_GEN_CNTL[0]), 0, 0 }, + { "mmDIG4_DIG_VERSION", REG_MMIO, 0x24e0, 2, &mmDIG4_DIG_VERSION[0], sizeof(mmDIG4_DIG_VERSION)/sizeof(mmDIG4_DIG_VERSION[0]), 0, 0 }, + { "mmDIG4_DIG_LANE_ENABLE", REG_MMIO, 0x24e1, 2, &mmDIG4_DIG_LANE_ENABLE[0], sizeof(mmDIG4_DIG_LANE_ENABLE)/sizeof(mmDIG4_DIG_LANE_ENABLE[0]), 0, 0 }, + { "mmDIG4_AFMT_CNTL", REG_MMIO, 0x24e6, 2, &mmDIG4_AFMT_CNTL[0], sizeof(mmDIG4_AFMT_CNTL)/sizeof(mmDIG4_AFMT_CNTL[0]), 0, 0 }, + { "mmDIG4_AFMT_VBI_PACKET_CONTROL1", REG_MMIO, 0x24e7, 2, &mmDIG4_AFMT_VBI_PACKET_CONTROL1[0], sizeof(mmDIG4_AFMT_VBI_PACKET_CONTROL1)/sizeof(mmDIG4_AFMT_VBI_PACKET_CONTROL1[0]), 0, 0 }, + { "mmDP4_DP_LINK_CNTL", REG_MMIO, 0x2508, 2, &mmDP4_DP_LINK_CNTL[0], sizeof(mmDP4_DP_LINK_CNTL)/sizeof(mmDP4_DP_LINK_CNTL[0]), 0, 0 }, + { "mmDP4_DP_PIXEL_FORMAT", REG_MMIO, 0x2509, 2, &mmDP4_DP_PIXEL_FORMAT[0], sizeof(mmDP4_DP_PIXEL_FORMAT)/sizeof(mmDP4_DP_PIXEL_FORMAT[0]), 0, 0 }, + { "mmDP4_DP_MSA_COLORIMETRY", REG_MMIO, 0x250a, 2, &mmDP4_DP_MSA_COLORIMETRY[0], sizeof(mmDP4_DP_MSA_COLORIMETRY)/sizeof(mmDP4_DP_MSA_COLORIMETRY[0]), 0, 0 }, + { "mmDP4_DP_CONFIG", REG_MMIO, 0x250b, 2, &mmDP4_DP_CONFIG[0], sizeof(mmDP4_DP_CONFIG)/sizeof(mmDP4_DP_CONFIG[0]), 0, 0 }, + { "mmDP4_DP_VID_STREAM_CNTL", REG_MMIO, 0x250c, 2, &mmDP4_DP_VID_STREAM_CNTL[0], sizeof(mmDP4_DP_VID_STREAM_CNTL)/sizeof(mmDP4_DP_VID_STREAM_CNTL[0]), 0, 0 }, + { "mmDP4_DP_STEER_FIFO", REG_MMIO, 0x250d, 2, &mmDP4_DP_STEER_FIFO[0], sizeof(mmDP4_DP_STEER_FIFO)/sizeof(mmDP4_DP_STEER_FIFO[0]), 0, 0 }, + { "mmDP4_DP_MSA_MISC", REG_MMIO, 0x250e, 2, &mmDP4_DP_MSA_MISC[0], sizeof(mmDP4_DP_MSA_MISC)/sizeof(mmDP4_DP_MSA_MISC[0]), 0, 0 }, + { "mmDP4_DP_VID_TIMING", REG_MMIO, 0x2510, 2, &mmDP4_DP_VID_TIMING[0], sizeof(mmDP4_DP_VID_TIMING)/sizeof(mmDP4_DP_VID_TIMING[0]), 0, 0 }, + { "mmDP4_DP_VID_N", REG_MMIO, 0x2511, 2, &mmDP4_DP_VID_N[0], sizeof(mmDP4_DP_VID_N)/sizeof(mmDP4_DP_VID_N[0]), 0, 0 }, + { "mmDP4_DP_VID_M", REG_MMIO, 0x2512, 2, &mmDP4_DP_VID_M[0], sizeof(mmDP4_DP_VID_M)/sizeof(mmDP4_DP_VID_M[0]), 0, 0 }, + { "mmDP4_DP_LINK_FRAMING_CNTL", REG_MMIO, 0x2513, 2, &mmDP4_DP_LINK_FRAMING_CNTL[0], sizeof(mmDP4_DP_LINK_FRAMING_CNTL)/sizeof(mmDP4_DP_LINK_FRAMING_CNTL[0]), 0, 0 }, + { "mmDP4_DP_HBR2_EYE_PATTERN", REG_MMIO, 0x2514, 2, &mmDP4_DP_HBR2_EYE_PATTERN[0], sizeof(mmDP4_DP_HBR2_EYE_PATTERN)/sizeof(mmDP4_DP_HBR2_EYE_PATTERN[0]), 0, 0 }, + { "mmDP4_DP_VID_MSA_VBID", REG_MMIO, 0x2515, 2, &mmDP4_DP_VID_MSA_VBID[0], sizeof(mmDP4_DP_VID_MSA_VBID)/sizeof(mmDP4_DP_VID_MSA_VBID[0]), 0, 0 }, + { "mmDP4_DP_VID_INTERRUPT_CNTL", REG_MMIO, 0x2516, 2, &mmDP4_DP_VID_INTERRUPT_CNTL[0], sizeof(mmDP4_DP_VID_INTERRUPT_CNTL)/sizeof(mmDP4_DP_VID_INTERRUPT_CNTL[0]), 0, 0 }, + { "mmDP4_DP_DPHY_CNTL", REG_MMIO, 0x2517, 2, &mmDP4_DP_DPHY_CNTL[0], sizeof(mmDP4_DP_DPHY_CNTL)/sizeof(mmDP4_DP_DPHY_CNTL[0]), 0, 0 }, + { "mmDP4_DP_DPHY_TRAINING_PATTERN_SEL", REG_MMIO, 0x2518, 2, &mmDP4_DP_DPHY_TRAINING_PATTERN_SEL[0], sizeof(mmDP4_DP_DPHY_TRAINING_PATTERN_SEL)/sizeof(mmDP4_DP_DPHY_TRAINING_PATTERN_SEL[0]), 0, 0 }, + { "mmDP4_DP_DPHY_SYM0", REG_MMIO, 0x2519, 2, &mmDP4_DP_DPHY_SYM0[0], sizeof(mmDP4_DP_DPHY_SYM0)/sizeof(mmDP4_DP_DPHY_SYM0[0]), 0, 0 }, + { "mmDP4_DP_DPHY_SYM1", REG_MMIO, 0x251a, 2, &mmDP4_DP_DPHY_SYM1[0], sizeof(mmDP4_DP_DPHY_SYM1)/sizeof(mmDP4_DP_DPHY_SYM1[0]), 0, 0 }, + { "mmDP4_DP_DPHY_SYM2", REG_MMIO, 0x251b, 2, &mmDP4_DP_DPHY_SYM2[0], sizeof(mmDP4_DP_DPHY_SYM2)/sizeof(mmDP4_DP_DPHY_SYM2[0]), 0, 0 }, + { "mmDP4_DP_DPHY_8B10B_CNTL", REG_MMIO, 0x251c, 2, &mmDP4_DP_DPHY_8B10B_CNTL[0], sizeof(mmDP4_DP_DPHY_8B10B_CNTL)/sizeof(mmDP4_DP_DPHY_8B10B_CNTL[0]), 0, 0 }, + { "mmDP4_DP_DPHY_PRBS_CNTL", REG_MMIO, 0x251d, 2, &mmDP4_DP_DPHY_PRBS_CNTL[0], sizeof(mmDP4_DP_DPHY_PRBS_CNTL)/sizeof(mmDP4_DP_DPHY_PRBS_CNTL[0]), 0, 0 }, + { "mmDP4_DP_DPHY_SCRAM_CNTL", REG_MMIO, 0x251e, 2, &mmDP4_DP_DPHY_SCRAM_CNTL[0], sizeof(mmDP4_DP_DPHY_SCRAM_CNTL)/sizeof(mmDP4_DP_DPHY_SCRAM_CNTL[0]), 0, 0 }, + { "mmDP4_DP_DPHY_CRC_EN", REG_MMIO, 0x251f, 2, &mmDP4_DP_DPHY_CRC_EN[0], sizeof(mmDP4_DP_DPHY_CRC_EN)/sizeof(mmDP4_DP_DPHY_CRC_EN[0]), 0, 0 }, + { "mmDP4_DP_DPHY_CRC_CNTL", REG_MMIO, 0x2520, 2, &mmDP4_DP_DPHY_CRC_CNTL[0], sizeof(mmDP4_DP_DPHY_CRC_CNTL)/sizeof(mmDP4_DP_DPHY_CRC_CNTL[0]), 0, 0 }, + { "mmDP4_DP_DPHY_CRC_RESULT", REG_MMIO, 0x2521, 2, &mmDP4_DP_DPHY_CRC_RESULT[0], sizeof(mmDP4_DP_DPHY_CRC_RESULT)/sizeof(mmDP4_DP_DPHY_CRC_RESULT[0]), 0, 0 }, + { "mmDP4_DP_DPHY_CRC_MST_CNTL", REG_MMIO, 0x2522, 2, &mmDP4_DP_DPHY_CRC_MST_CNTL[0], sizeof(mmDP4_DP_DPHY_CRC_MST_CNTL)/sizeof(mmDP4_DP_DPHY_CRC_MST_CNTL[0]), 0, 0 }, + { "mmDP4_DP_DPHY_CRC_MST_STATUS", REG_MMIO, 0x2523, 2, &mmDP4_DP_DPHY_CRC_MST_STATUS[0], sizeof(mmDP4_DP_DPHY_CRC_MST_STATUS)/sizeof(mmDP4_DP_DPHY_CRC_MST_STATUS[0]), 0, 0 }, + { "mmDP4_DP_DPHY_FAST_TRAINING", REG_MMIO, 0x2524, 2, &mmDP4_DP_DPHY_FAST_TRAINING[0], sizeof(mmDP4_DP_DPHY_FAST_TRAINING)/sizeof(mmDP4_DP_DPHY_FAST_TRAINING[0]), 0, 0 }, + { "mmDP4_DP_DPHY_FAST_TRAINING_STATUS", REG_MMIO, 0x2525, 2, &mmDP4_DP_DPHY_FAST_TRAINING_STATUS[0], sizeof(mmDP4_DP_DPHY_FAST_TRAINING_STATUS)/sizeof(mmDP4_DP_DPHY_FAST_TRAINING_STATUS[0]), 0, 0 }, + { "mmDP4_DP_SEC_CNTL", REG_MMIO, 0x252b, 2, &mmDP4_DP_SEC_CNTL[0], sizeof(mmDP4_DP_SEC_CNTL)/sizeof(mmDP4_DP_SEC_CNTL[0]), 0, 0 }, + { "mmDP4_DP_SEC_CNTL1", REG_MMIO, 0x252c, 2, &mmDP4_DP_SEC_CNTL1[0], sizeof(mmDP4_DP_SEC_CNTL1)/sizeof(mmDP4_DP_SEC_CNTL1[0]), 0, 0 }, + { "mmDP4_DP_SEC_FRAMING1", REG_MMIO, 0x252d, 2, &mmDP4_DP_SEC_FRAMING1[0], sizeof(mmDP4_DP_SEC_FRAMING1)/sizeof(mmDP4_DP_SEC_FRAMING1[0]), 0, 0 }, + { "mmDP4_DP_SEC_FRAMING2", REG_MMIO, 0x252e, 2, &mmDP4_DP_SEC_FRAMING2[0], sizeof(mmDP4_DP_SEC_FRAMING2)/sizeof(mmDP4_DP_SEC_FRAMING2[0]), 0, 0 }, + { "mmDP4_DP_SEC_FRAMING3", REG_MMIO, 0x252f, 2, &mmDP4_DP_SEC_FRAMING3[0], sizeof(mmDP4_DP_SEC_FRAMING3)/sizeof(mmDP4_DP_SEC_FRAMING3[0]), 0, 0 }, + { "mmDP4_DP_SEC_FRAMING4", REG_MMIO, 0x2530, 2, &mmDP4_DP_SEC_FRAMING4[0], sizeof(mmDP4_DP_SEC_FRAMING4)/sizeof(mmDP4_DP_SEC_FRAMING4[0]), 0, 0 }, + { "mmDP4_DP_SEC_AUD_N", REG_MMIO, 0x2531, 2, &mmDP4_DP_SEC_AUD_N[0], sizeof(mmDP4_DP_SEC_AUD_N)/sizeof(mmDP4_DP_SEC_AUD_N[0]), 0, 0 }, + { "mmDP4_DP_SEC_AUD_N_READBACK", REG_MMIO, 0x2532, 2, &mmDP4_DP_SEC_AUD_N_READBACK[0], sizeof(mmDP4_DP_SEC_AUD_N_READBACK)/sizeof(mmDP4_DP_SEC_AUD_N_READBACK[0]), 0, 0 }, + { "mmDP4_DP_SEC_AUD_M", REG_MMIO, 0x2533, 2, &mmDP4_DP_SEC_AUD_M[0], sizeof(mmDP4_DP_SEC_AUD_M)/sizeof(mmDP4_DP_SEC_AUD_M[0]), 0, 0 }, + { "mmDP4_DP_SEC_AUD_M_READBACK", REG_MMIO, 0x2534, 2, &mmDP4_DP_SEC_AUD_M_READBACK[0], sizeof(mmDP4_DP_SEC_AUD_M_READBACK)/sizeof(mmDP4_DP_SEC_AUD_M_READBACK[0]), 0, 0 }, + { "mmDP4_DP_SEC_TIMESTAMP", REG_MMIO, 0x2535, 2, &mmDP4_DP_SEC_TIMESTAMP[0], sizeof(mmDP4_DP_SEC_TIMESTAMP)/sizeof(mmDP4_DP_SEC_TIMESTAMP[0]), 0, 0 }, + { "mmDP4_DP_SEC_PACKET_CNTL", REG_MMIO, 0x2536, 2, &mmDP4_DP_SEC_PACKET_CNTL[0], sizeof(mmDP4_DP_SEC_PACKET_CNTL)/sizeof(mmDP4_DP_SEC_PACKET_CNTL[0]), 0, 0 }, + { "mmDP4_DP_MSE_RATE_CNTL", REG_MMIO, 0x2537, 2, &mmDP4_DP_MSE_RATE_CNTL[0], sizeof(mmDP4_DP_MSE_RATE_CNTL)/sizeof(mmDP4_DP_MSE_RATE_CNTL[0]), 0, 0 }, + { "mmDP4_DP_MSE_RATE_UPDATE", REG_MMIO, 0x2539, 2, &mmDP4_DP_MSE_RATE_UPDATE[0], sizeof(mmDP4_DP_MSE_RATE_UPDATE)/sizeof(mmDP4_DP_MSE_RATE_UPDATE[0]), 0, 0 }, + { "mmDP4_DP_MSE_SAT0", REG_MMIO, 0x253a, 2, &mmDP4_DP_MSE_SAT0[0], sizeof(mmDP4_DP_MSE_SAT0)/sizeof(mmDP4_DP_MSE_SAT0[0]), 0, 0 }, + { "mmDP4_DP_MSE_SAT1", REG_MMIO, 0x253b, 2, &mmDP4_DP_MSE_SAT1[0], sizeof(mmDP4_DP_MSE_SAT1)/sizeof(mmDP4_DP_MSE_SAT1[0]), 0, 0 }, + { "mmDP4_DP_MSE_SAT2", REG_MMIO, 0x253c, 2, &mmDP4_DP_MSE_SAT2[0], sizeof(mmDP4_DP_MSE_SAT2)/sizeof(mmDP4_DP_MSE_SAT2[0]), 0, 0 }, + { "mmDP4_DP_MSE_SAT_UPDATE", REG_MMIO, 0x253d, 2, &mmDP4_DP_MSE_SAT_UPDATE[0], sizeof(mmDP4_DP_MSE_SAT_UPDATE)/sizeof(mmDP4_DP_MSE_SAT_UPDATE[0]), 0, 0 }, + { "mmDP4_DP_MSE_LINK_TIMING", REG_MMIO, 0x253e, 2, &mmDP4_DP_MSE_LINK_TIMING[0], sizeof(mmDP4_DP_MSE_LINK_TIMING)/sizeof(mmDP4_DP_MSE_LINK_TIMING[0]), 0, 0 }, + { "mmDP4_DP_MSE_MISC_CNTL", REG_MMIO, 0x253f, 2, &mmDP4_DP_MSE_MISC_CNTL[0], sizeof(mmDP4_DP_MSE_MISC_CNTL)/sizeof(mmDP4_DP_MSE_MISC_CNTL[0]), 0, 0 }, + { "mmDP4_DP_DPHY_BS_SR_SWAP_CNTL", REG_MMIO, 0x2544, 2, &mmDP4_DP_DPHY_BS_SR_SWAP_CNTL[0], sizeof(mmDP4_DP_DPHY_BS_SR_SWAP_CNTL)/sizeof(mmDP4_DP_DPHY_BS_SR_SWAP_CNTL[0]), 0, 0 }, + { "mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL", REG_MMIO, 0x2545, 2, &mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL[0], sizeof(mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL)/sizeof(mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL[0]), 0, 0 }, + { "mmDP4_DP_MSE_SAT0_STATUS", REG_MMIO, 0x2547, 2, &mmDP4_DP_MSE_SAT0_STATUS[0], sizeof(mmDP4_DP_MSE_SAT0_STATUS)/sizeof(mmDP4_DP_MSE_SAT0_STATUS[0]), 0, 0 }, + { "mmDP4_DP_MSE_SAT1_STATUS", REG_MMIO, 0x2548, 2, &mmDP4_DP_MSE_SAT1_STATUS[0], sizeof(mmDP4_DP_MSE_SAT1_STATUS)/sizeof(mmDP4_DP_MSE_SAT1_STATUS[0]), 0, 0 }, + { "mmDP4_DP_MSE_SAT2_STATUS", REG_MMIO, 0x2549, 2, &mmDP4_DP_MSE_SAT2_STATUS[0], sizeof(mmDP4_DP_MSE_SAT2_STATUS)/sizeof(mmDP4_DP_MSE_SAT2_STATUS[0]), 0, 0 }, + { "mmDP4_DP_MSA_TIMING_PARAM1", REG_MMIO, 0x254c, 2, &mmDP4_DP_MSA_TIMING_PARAM1[0], sizeof(mmDP4_DP_MSA_TIMING_PARAM1)/sizeof(mmDP4_DP_MSA_TIMING_PARAM1[0]), 0, 0 }, + { "mmDP4_DP_MSA_TIMING_PARAM2", REG_MMIO, 0x254d, 2, &mmDP4_DP_MSA_TIMING_PARAM2[0], sizeof(mmDP4_DP_MSA_TIMING_PARAM2)/sizeof(mmDP4_DP_MSA_TIMING_PARAM2[0]), 0, 0 }, + { "mmDP4_DP_MSA_TIMING_PARAM3", REG_MMIO, 0x254e, 2, &mmDP4_DP_MSA_TIMING_PARAM3[0], sizeof(mmDP4_DP_MSA_TIMING_PARAM3)/sizeof(mmDP4_DP_MSA_TIMING_PARAM3[0]), 0, 0 }, + { "mmDP4_DP_MSA_TIMING_PARAM4", REG_MMIO, 0x254f, 2, &mmDP4_DP_MSA_TIMING_PARAM4[0], sizeof(mmDP4_DP_MSA_TIMING_PARAM4)/sizeof(mmDP4_DP_MSA_TIMING_PARAM4[0]), 0, 0 }, + { "mmDP4_DP_MSO_CNTL", REG_MMIO, 0x2550, 2, &mmDP4_DP_MSO_CNTL[0], sizeof(mmDP4_DP_MSO_CNTL)/sizeof(mmDP4_DP_MSO_CNTL[0]), 0, 0 }, + { "mmDP4_DP_MSO_CNTL1", REG_MMIO, 0x2551, 2, &mmDP4_DP_MSO_CNTL1[0], sizeof(mmDP4_DP_MSO_CNTL1)/sizeof(mmDP4_DP_MSO_CNTL1[0]), 0, 0 }, + { "mmDP4_DP_DSC_CNTL", REG_MMIO, 0x2552, 2, &mmDP4_DP_DSC_CNTL[0], sizeof(mmDP4_DP_DSC_CNTL)/sizeof(mmDP4_DP_DSC_CNTL[0]), 0, 0 }, + { "mmDP4_DP_SEC_CNTL2", REG_MMIO, 0x2553, 2, &mmDP4_DP_SEC_CNTL2[0], sizeof(mmDP4_DP_SEC_CNTL2)/sizeof(mmDP4_DP_SEC_CNTL2[0]), 0, 0 }, + { "mmDP4_DP_SEC_CNTL3", REG_MMIO, 0x2554, 2, &mmDP4_DP_SEC_CNTL3[0], sizeof(mmDP4_DP_SEC_CNTL3)/sizeof(mmDP4_DP_SEC_CNTL3[0]), 0, 0 }, + { "mmDP4_DP_SEC_CNTL4", REG_MMIO, 0x2555, 2, &mmDP4_DP_SEC_CNTL4[0], sizeof(mmDP4_DP_SEC_CNTL4)/sizeof(mmDP4_DP_SEC_CNTL4[0]), 0, 0 }, + { "mmDP4_DP_SEC_CNTL5", REG_MMIO, 0x2556, 2, &mmDP4_DP_SEC_CNTL5[0], sizeof(mmDP4_DP_SEC_CNTL5)/sizeof(mmDP4_DP_SEC_CNTL5[0]), 0, 0 }, + { "mmDP4_DP_SEC_CNTL6", REG_MMIO, 0x2557, 2, &mmDP4_DP_SEC_CNTL6[0], sizeof(mmDP4_DP_SEC_CNTL6)/sizeof(mmDP4_DP_SEC_CNTL6[0]), 0, 0 }, + { "mmDP4_DP_SEC_CNTL7", REG_MMIO, 0x2558, 2, &mmDP4_DP_SEC_CNTL7[0], sizeof(mmDP4_DP_SEC_CNTL7)/sizeof(mmDP4_DP_SEC_CNTL7[0]), 0, 0 }, + { "mmDP4_DP_DB_CNTL", REG_MMIO, 0x2559, 2, &mmDP4_DP_DB_CNTL[0], sizeof(mmDP4_DP_DB_CNTL)/sizeof(mmDP4_DP_DB_CNTL[0]), 0, 0 }, + { "mmDP4_DP_MSA_VBID_MISC", REG_MMIO, 0x255a, 2, &mmDP4_DP_MSA_VBID_MISC[0], sizeof(mmDP4_DP_MSA_VBID_MISC)/sizeof(mmDP4_DP_MSA_VBID_MISC[0]), 0, 0 }, + { "mmDIG5_DIG_FE_CNTL", REG_MMIO, 0x2568, 2, &mmDIG5_DIG_FE_CNTL[0], sizeof(mmDIG5_DIG_FE_CNTL)/sizeof(mmDIG5_DIG_FE_CNTL[0]), 0, 0 }, + { "mmDIG5_DIG_OUTPUT_CRC_CNTL", REG_MMIO, 0x2569, 2, &mmDIG5_DIG_OUTPUT_CRC_CNTL[0], sizeof(mmDIG5_DIG_OUTPUT_CRC_CNTL)/sizeof(mmDIG5_DIG_OUTPUT_CRC_CNTL[0]), 0, 0 }, + { "mmDIG5_DIG_OUTPUT_CRC_RESULT", REG_MMIO, 0x256a, 2, &mmDIG5_DIG_OUTPUT_CRC_RESULT[0], sizeof(mmDIG5_DIG_OUTPUT_CRC_RESULT)/sizeof(mmDIG5_DIG_OUTPUT_CRC_RESULT[0]), 0, 0 }, + { "mmDIG5_DIG_CLOCK_PATTERN", REG_MMIO, 0x256b, 2, &mmDIG5_DIG_CLOCK_PATTERN[0], sizeof(mmDIG5_DIG_CLOCK_PATTERN)/sizeof(mmDIG5_DIG_CLOCK_PATTERN[0]), 0, 0 }, + { "mmDIG5_DIG_TEST_PATTERN", REG_MMIO, 0x256c, 2, &mmDIG5_DIG_TEST_PATTERN[0], sizeof(mmDIG5_DIG_TEST_PATTERN)/sizeof(mmDIG5_DIG_TEST_PATTERN[0]), 0, 0 }, + { "mmDIG5_DIG_RANDOM_PATTERN_SEED", REG_MMIO, 0x256d, 2, &mmDIG5_DIG_RANDOM_PATTERN_SEED[0], sizeof(mmDIG5_DIG_RANDOM_PATTERN_SEED)/sizeof(mmDIG5_DIG_RANDOM_PATTERN_SEED[0]), 0, 0 }, + { "mmDIG5_DIG_FIFO_STATUS", REG_MMIO, 0x256e, 2, &mmDIG5_DIG_FIFO_STATUS[0], sizeof(mmDIG5_DIG_FIFO_STATUS)/sizeof(mmDIG5_DIG_FIFO_STATUS[0]), 0, 0 }, + { "mmDIG5_HDMI_CONTROL", REG_MMIO, 0x2571, 2, &mmDIG5_HDMI_CONTROL[0], sizeof(mmDIG5_HDMI_CONTROL)/sizeof(mmDIG5_HDMI_CONTROL[0]), 0, 0 }, + { "mmDIG5_HDMI_STATUS", REG_MMIO, 0x2572, 2, &mmDIG5_HDMI_STATUS[0], sizeof(mmDIG5_HDMI_STATUS)/sizeof(mmDIG5_HDMI_STATUS[0]), 0, 0 }, + { "mmDIG5_HDMI_AUDIO_PACKET_CONTROL", REG_MMIO, 0x2573, 2, &mmDIG5_HDMI_AUDIO_PACKET_CONTROL[0], sizeof(mmDIG5_HDMI_AUDIO_PACKET_CONTROL)/sizeof(mmDIG5_HDMI_AUDIO_PACKET_CONTROL[0]), 0, 0 }, + { "mmDIG5_HDMI_ACR_PACKET_CONTROL", REG_MMIO, 0x2574, 2, &mmDIG5_HDMI_ACR_PACKET_CONTROL[0], sizeof(mmDIG5_HDMI_ACR_PACKET_CONTROL)/sizeof(mmDIG5_HDMI_ACR_PACKET_CONTROL[0]), 0, 0 }, + { "mmDIG5_HDMI_VBI_PACKET_CONTROL", REG_MMIO, 0x2575, 2, &mmDIG5_HDMI_VBI_PACKET_CONTROL[0], sizeof(mmDIG5_HDMI_VBI_PACKET_CONTROL)/sizeof(mmDIG5_HDMI_VBI_PACKET_CONTROL[0]), 0, 0 }, + { "mmDIG5_HDMI_INFOFRAME_CONTROL0", REG_MMIO, 0x2576, 2, &mmDIG5_HDMI_INFOFRAME_CONTROL0[0], sizeof(mmDIG5_HDMI_INFOFRAME_CONTROL0)/sizeof(mmDIG5_HDMI_INFOFRAME_CONTROL0[0]), 0, 0 }, + { "mmDIG5_HDMI_INFOFRAME_CONTROL1", REG_MMIO, 0x2577, 2, &mmDIG5_HDMI_INFOFRAME_CONTROL1[0], sizeof(mmDIG5_HDMI_INFOFRAME_CONTROL1)/sizeof(mmDIG5_HDMI_INFOFRAME_CONTROL1[0]), 0, 0 }, + { "mmDIG5_HDMI_GENERIC_PACKET_CONTROL0", REG_MMIO, 0x2578, 2, &mmDIG5_HDMI_GENERIC_PACKET_CONTROL0[0], sizeof(mmDIG5_HDMI_GENERIC_PACKET_CONTROL0)/sizeof(mmDIG5_HDMI_GENERIC_PACKET_CONTROL0[0]), 0, 0 }, + { "mmDIG5_AFMT_INTERRUPT_STATUS", REG_MMIO, 0x2579, 2, NULL, 0, 0, 0 }, + { "mmDIG5_HDMI_GC", REG_MMIO, 0x257b, 2, &mmDIG5_HDMI_GC[0], sizeof(mmDIG5_HDMI_GC)/sizeof(mmDIG5_HDMI_GC[0]), 0, 0 }, + { "mmDIG5_AFMT_AUDIO_PACKET_CONTROL2", REG_MMIO, 0x257c, 2, &mmDIG5_AFMT_AUDIO_PACKET_CONTROL2[0], sizeof(mmDIG5_AFMT_AUDIO_PACKET_CONTROL2)/sizeof(mmDIG5_AFMT_AUDIO_PACKET_CONTROL2[0]), 0, 0 }, + { "mmDIG5_AFMT_ISRC1_0", REG_MMIO, 0x257d, 2, &mmDIG5_AFMT_ISRC1_0[0], sizeof(mmDIG5_AFMT_ISRC1_0)/sizeof(mmDIG5_AFMT_ISRC1_0[0]), 0, 0 }, + { "mmDIG5_AFMT_ISRC1_1", REG_MMIO, 0x257e, 2, &mmDIG5_AFMT_ISRC1_1[0], sizeof(mmDIG5_AFMT_ISRC1_1)/sizeof(mmDIG5_AFMT_ISRC1_1[0]), 0, 0 }, + { "mmDIG5_AFMT_ISRC1_2", REG_MMIO, 0x257f, 2, &mmDIG5_AFMT_ISRC1_2[0], sizeof(mmDIG5_AFMT_ISRC1_2)/sizeof(mmDIG5_AFMT_ISRC1_2[0]), 0, 0 }, + { "mmDIG5_AFMT_ISRC1_3", REG_MMIO, 0x2580, 2, &mmDIG5_AFMT_ISRC1_3[0], sizeof(mmDIG5_AFMT_ISRC1_3)/sizeof(mmDIG5_AFMT_ISRC1_3[0]), 0, 0 }, + { "mmDIG5_AFMT_ISRC1_4", REG_MMIO, 0x2581, 2, &mmDIG5_AFMT_ISRC1_4[0], sizeof(mmDIG5_AFMT_ISRC1_4)/sizeof(mmDIG5_AFMT_ISRC1_4[0]), 0, 0 }, + { "mmDIG5_AFMT_ISRC2_0", REG_MMIO, 0x2582, 2, &mmDIG5_AFMT_ISRC2_0[0], sizeof(mmDIG5_AFMT_ISRC2_0)/sizeof(mmDIG5_AFMT_ISRC2_0[0]), 0, 0 }, + { "mmDIG5_AFMT_ISRC2_1", REG_MMIO, 0x2583, 2, &mmDIG5_AFMT_ISRC2_1[0], sizeof(mmDIG5_AFMT_ISRC2_1)/sizeof(mmDIG5_AFMT_ISRC2_1[0]), 0, 0 }, + { "mmDIG5_AFMT_ISRC2_2", REG_MMIO, 0x2584, 2, &mmDIG5_AFMT_ISRC2_2[0], sizeof(mmDIG5_AFMT_ISRC2_2)/sizeof(mmDIG5_AFMT_ISRC2_2[0]), 0, 0 }, + { "mmDIG5_AFMT_ISRC2_3", REG_MMIO, 0x2585, 2, &mmDIG5_AFMT_ISRC2_3[0], sizeof(mmDIG5_AFMT_ISRC2_3)/sizeof(mmDIG5_AFMT_ISRC2_3[0]), 0, 0 }, + { "mmDIG5_HDMI_GENERIC_PACKET_CONTROL2", REG_MMIO, 0x2586, 2, &mmDIG5_HDMI_GENERIC_PACKET_CONTROL2[0], sizeof(mmDIG5_HDMI_GENERIC_PACKET_CONTROL2)/sizeof(mmDIG5_HDMI_GENERIC_PACKET_CONTROL2[0]), 0, 0 }, + { "mmDIG5_HDMI_GENERIC_PACKET_CONTROL3", REG_MMIO, 0x2587, 2, &mmDIG5_HDMI_GENERIC_PACKET_CONTROL3[0], sizeof(mmDIG5_HDMI_GENERIC_PACKET_CONTROL3)/sizeof(mmDIG5_HDMI_GENERIC_PACKET_CONTROL3[0]), 0, 0 }, + { "mmDIG5_HDMI_DB_CONTROL", REG_MMIO, 0x2588, 2, &mmDIG5_HDMI_DB_CONTROL[0], sizeof(mmDIG5_HDMI_DB_CONTROL)/sizeof(mmDIG5_HDMI_DB_CONTROL[0]), 0, 0 }, + { "mmDIG5_AFMT_MPEG_INFO0", REG_MMIO, 0x258a, 2, &mmDIG5_AFMT_MPEG_INFO0[0], sizeof(mmDIG5_AFMT_MPEG_INFO0)/sizeof(mmDIG5_AFMT_MPEG_INFO0[0]), 0, 0 }, + { "mmDIG5_AFMT_MPEG_INFO1", REG_MMIO, 0x258b, 2, &mmDIG5_AFMT_MPEG_INFO1[0], sizeof(mmDIG5_AFMT_MPEG_INFO1)/sizeof(mmDIG5_AFMT_MPEG_INFO1[0]), 0, 0 }, + { "mmDIG5_AFMT_GENERIC_HDR", REG_MMIO, 0x258c, 2, &mmDIG5_AFMT_GENERIC_HDR[0], sizeof(mmDIG5_AFMT_GENERIC_HDR)/sizeof(mmDIG5_AFMT_GENERIC_HDR[0]), 0, 0 }, + { "mmDIG5_AFMT_GENERIC_0", REG_MMIO, 0x258d, 2, &mmDIG5_AFMT_GENERIC_0[0], sizeof(mmDIG5_AFMT_GENERIC_0)/sizeof(mmDIG5_AFMT_GENERIC_0[0]), 0, 0 }, + { "mmDIG5_AFMT_GENERIC_1", REG_MMIO, 0x258e, 2, &mmDIG5_AFMT_GENERIC_1[0], sizeof(mmDIG5_AFMT_GENERIC_1)/sizeof(mmDIG5_AFMT_GENERIC_1[0]), 0, 0 }, + { "mmDIG5_AFMT_GENERIC_2", REG_MMIO, 0x258f, 2, &mmDIG5_AFMT_GENERIC_2[0], sizeof(mmDIG5_AFMT_GENERIC_2)/sizeof(mmDIG5_AFMT_GENERIC_2[0]), 0, 0 }, + { "mmDIG5_AFMT_GENERIC_3", REG_MMIO, 0x2590, 2, &mmDIG5_AFMT_GENERIC_3[0], sizeof(mmDIG5_AFMT_GENERIC_3)/sizeof(mmDIG5_AFMT_GENERIC_3[0]), 0, 0 }, + { "mmDIG5_AFMT_GENERIC_4", REG_MMIO, 0x2591, 2, &mmDIG5_AFMT_GENERIC_4[0], sizeof(mmDIG5_AFMT_GENERIC_4)/sizeof(mmDIG5_AFMT_GENERIC_4[0]), 0, 0 }, + { "mmDIG5_AFMT_GENERIC_5", REG_MMIO, 0x2592, 2, &mmDIG5_AFMT_GENERIC_5[0], sizeof(mmDIG5_AFMT_GENERIC_5)/sizeof(mmDIG5_AFMT_GENERIC_5[0]), 0, 0 }, + { "mmDIG5_AFMT_GENERIC_6", REG_MMIO, 0x2593, 2, &mmDIG5_AFMT_GENERIC_6[0], sizeof(mmDIG5_AFMT_GENERIC_6)/sizeof(mmDIG5_AFMT_GENERIC_6[0]), 0, 0 }, + { "mmDIG5_AFMT_GENERIC_7", REG_MMIO, 0x2594, 2, &mmDIG5_AFMT_GENERIC_7[0], sizeof(mmDIG5_AFMT_GENERIC_7)/sizeof(mmDIG5_AFMT_GENERIC_7[0]), 0, 0 }, + { "mmDIG5_HDMI_GENERIC_PACKET_CONTROL1", REG_MMIO, 0x2595, 2, &mmDIG5_HDMI_GENERIC_PACKET_CONTROL1[0], sizeof(mmDIG5_HDMI_GENERIC_PACKET_CONTROL1)/sizeof(mmDIG5_HDMI_GENERIC_PACKET_CONTROL1[0]), 0, 0 }, + { "mmDIG5_HDMI_ACR_32_0", REG_MMIO, 0x2596, 2, &mmDIG5_HDMI_ACR_32_0[0], sizeof(mmDIG5_HDMI_ACR_32_0)/sizeof(mmDIG5_HDMI_ACR_32_0[0]), 0, 0 }, + { "mmDIG5_HDMI_ACR_32_1", REG_MMIO, 0x2597, 2, &mmDIG5_HDMI_ACR_32_1[0], sizeof(mmDIG5_HDMI_ACR_32_1)/sizeof(mmDIG5_HDMI_ACR_32_1[0]), 0, 0 }, + { "mmDIG5_HDMI_ACR_44_0", REG_MMIO, 0x2598, 2, &mmDIG5_HDMI_ACR_44_0[0], sizeof(mmDIG5_HDMI_ACR_44_0)/sizeof(mmDIG5_HDMI_ACR_44_0[0]), 0, 0 }, + { "mmDIG5_HDMI_ACR_44_1", REG_MMIO, 0x2599, 2, &mmDIG5_HDMI_ACR_44_1[0], sizeof(mmDIG5_HDMI_ACR_44_1)/sizeof(mmDIG5_HDMI_ACR_44_1[0]), 0, 0 }, + { "mmDIG5_HDMI_ACR_48_0", REG_MMIO, 0x259a, 2, &mmDIG5_HDMI_ACR_48_0[0], sizeof(mmDIG5_HDMI_ACR_48_0)/sizeof(mmDIG5_HDMI_ACR_48_0[0]), 0, 0 }, + { "mmDIG5_HDMI_ACR_48_1", REG_MMIO, 0x259b, 2, &mmDIG5_HDMI_ACR_48_1[0], sizeof(mmDIG5_HDMI_ACR_48_1)/sizeof(mmDIG5_HDMI_ACR_48_1[0]), 0, 0 }, + { "mmDIG5_HDMI_ACR_STATUS_0", REG_MMIO, 0x259c, 2, &mmDIG5_HDMI_ACR_STATUS_0[0], sizeof(mmDIG5_HDMI_ACR_STATUS_0)/sizeof(mmDIG5_HDMI_ACR_STATUS_0[0]), 0, 0 }, + { "mmDIG5_HDMI_ACR_STATUS_1", REG_MMIO, 0x259d, 2, &mmDIG5_HDMI_ACR_STATUS_1[0], sizeof(mmDIG5_HDMI_ACR_STATUS_1)/sizeof(mmDIG5_HDMI_ACR_STATUS_1[0]), 0, 0 }, + { "mmDIG5_AFMT_AUDIO_INFO0", REG_MMIO, 0x259e, 2, &mmDIG5_AFMT_AUDIO_INFO0[0], sizeof(mmDIG5_AFMT_AUDIO_INFO0)/sizeof(mmDIG5_AFMT_AUDIO_INFO0[0]), 0, 0 }, + { "mmDIG5_AFMT_AUDIO_INFO1", REG_MMIO, 0x259f, 2, &mmDIG5_AFMT_AUDIO_INFO1[0], sizeof(mmDIG5_AFMT_AUDIO_INFO1)/sizeof(mmDIG5_AFMT_AUDIO_INFO1[0]), 0, 0 }, + { "mmDIG5_AFMT_60958_0", REG_MMIO, 0x25a0, 2, &mmDIG5_AFMT_60958_0[0], sizeof(mmDIG5_AFMT_60958_0)/sizeof(mmDIG5_AFMT_60958_0[0]), 0, 0 }, + { "mmDIG5_AFMT_60958_1", REG_MMIO, 0x25a1, 2, &mmDIG5_AFMT_60958_1[0], sizeof(mmDIG5_AFMT_60958_1)/sizeof(mmDIG5_AFMT_60958_1[0]), 0, 0 }, + { "mmDIG5_AFMT_AUDIO_CRC_CONTROL", REG_MMIO, 0x25a2, 2, &mmDIG5_AFMT_AUDIO_CRC_CONTROL[0], sizeof(mmDIG5_AFMT_AUDIO_CRC_CONTROL)/sizeof(mmDIG5_AFMT_AUDIO_CRC_CONTROL[0]), 0, 0 }, + { "mmDIG5_AFMT_RAMP_CONTROL0", REG_MMIO, 0x25a3, 2, &mmDIG5_AFMT_RAMP_CONTROL0[0], sizeof(mmDIG5_AFMT_RAMP_CONTROL0)/sizeof(mmDIG5_AFMT_RAMP_CONTROL0[0]), 0, 0 }, + { "mmDIG5_AFMT_RAMP_CONTROL1", REG_MMIO, 0x25a4, 2, &mmDIG5_AFMT_RAMP_CONTROL1[0], sizeof(mmDIG5_AFMT_RAMP_CONTROL1)/sizeof(mmDIG5_AFMT_RAMP_CONTROL1[0]), 0, 0 }, + { "mmDIG5_AFMT_RAMP_CONTROL2", REG_MMIO, 0x25a5, 2, &mmDIG5_AFMT_RAMP_CONTROL2[0], sizeof(mmDIG5_AFMT_RAMP_CONTROL2)/sizeof(mmDIG5_AFMT_RAMP_CONTROL2[0]), 0, 0 }, + { "mmDIG5_AFMT_RAMP_CONTROL3", REG_MMIO, 0x25a6, 2, &mmDIG5_AFMT_RAMP_CONTROL3[0], sizeof(mmDIG5_AFMT_RAMP_CONTROL3)/sizeof(mmDIG5_AFMT_RAMP_CONTROL3[0]), 0, 0 }, + { "mmDIG5_AFMT_60958_2", REG_MMIO, 0x25a7, 2, &mmDIG5_AFMT_60958_2[0], sizeof(mmDIG5_AFMT_60958_2)/sizeof(mmDIG5_AFMT_60958_2[0]), 0, 0 }, + { "mmDIG5_AFMT_AUDIO_CRC_RESULT", REG_MMIO, 0x25a8, 2, &mmDIG5_AFMT_AUDIO_CRC_RESULT[0], sizeof(mmDIG5_AFMT_AUDIO_CRC_RESULT)/sizeof(mmDIG5_AFMT_AUDIO_CRC_RESULT[0]), 0, 0 }, + { "mmDIG5_AFMT_STATUS", REG_MMIO, 0x25a9, 2, &mmDIG5_AFMT_STATUS[0], sizeof(mmDIG5_AFMT_STATUS)/sizeof(mmDIG5_AFMT_STATUS[0]), 0, 0 }, + { "mmDIG5_AFMT_AUDIO_PACKET_CONTROL", REG_MMIO, 0x25aa, 2, &mmDIG5_AFMT_AUDIO_PACKET_CONTROL[0], sizeof(mmDIG5_AFMT_AUDIO_PACKET_CONTROL)/sizeof(mmDIG5_AFMT_AUDIO_PACKET_CONTROL[0]), 0, 0 }, + { "mmDIG5_AFMT_VBI_PACKET_CONTROL", REG_MMIO, 0x25ab, 2, &mmDIG5_AFMT_VBI_PACKET_CONTROL[0], sizeof(mmDIG5_AFMT_VBI_PACKET_CONTROL)/sizeof(mmDIG5_AFMT_VBI_PACKET_CONTROL[0]), 0, 0 }, + { "mmDIG5_AFMT_INFOFRAME_CONTROL0", REG_MMIO, 0x25ac, 2, &mmDIG5_AFMT_INFOFRAME_CONTROL0[0], sizeof(mmDIG5_AFMT_INFOFRAME_CONTROL0)/sizeof(mmDIG5_AFMT_INFOFRAME_CONTROL0[0]), 0, 0 }, + { "mmDIG5_AFMT_AUDIO_SRC_CONTROL", REG_MMIO, 0x25ad, 2, &mmDIG5_AFMT_AUDIO_SRC_CONTROL[0], sizeof(mmDIG5_AFMT_AUDIO_SRC_CONTROL)/sizeof(mmDIG5_AFMT_AUDIO_SRC_CONTROL[0]), 0, 0 }, + { "mmDIG5_DIG_BE_CNTL", REG_MMIO, 0x25af, 2, &mmDIG5_DIG_BE_CNTL[0], sizeof(mmDIG5_DIG_BE_CNTL)/sizeof(mmDIG5_DIG_BE_CNTL[0]), 0, 0 }, + { "mmDIG5_DIG_BE_EN_CNTL", REG_MMIO, 0x25b0, 2, &mmDIG5_DIG_BE_EN_CNTL[0], sizeof(mmDIG5_DIG_BE_EN_CNTL)/sizeof(mmDIG5_DIG_BE_EN_CNTL[0]), 0, 0 }, + { "mmDIG5_TMDS_CNTL", REG_MMIO, 0x25d3, 2, &mmDIG5_TMDS_CNTL[0], sizeof(mmDIG5_TMDS_CNTL)/sizeof(mmDIG5_TMDS_CNTL[0]), 0, 0 }, + { "mmDIG5_TMDS_CONTROL_CHAR", REG_MMIO, 0x25d4, 2, &mmDIG5_TMDS_CONTROL_CHAR[0], sizeof(mmDIG5_TMDS_CONTROL_CHAR)/sizeof(mmDIG5_TMDS_CONTROL_CHAR[0]), 0, 0 }, + { "mmDIG5_TMDS_CONTROL0_FEEDBACK", REG_MMIO, 0x25d5, 2, &mmDIG5_TMDS_CONTROL0_FEEDBACK[0], sizeof(mmDIG5_TMDS_CONTROL0_FEEDBACK)/sizeof(mmDIG5_TMDS_CONTROL0_FEEDBACK[0]), 0, 0 }, + { "mmDIG5_TMDS_STEREOSYNC_CTL_SEL", REG_MMIO, 0x25d6, 2, &mmDIG5_TMDS_STEREOSYNC_CTL_SEL[0], sizeof(mmDIG5_TMDS_STEREOSYNC_CTL_SEL)/sizeof(mmDIG5_TMDS_STEREOSYNC_CTL_SEL[0]), 0, 0 }, + { "mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1", REG_MMIO, 0x25d7, 2, &mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1[0], sizeof(mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1)/sizeof(mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1[0]), 0, 0 }, + { "mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3", REG_MMIO, 0x25d8, 2, &mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3[0], sizeof(mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3)/sizeof(mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3[0]), 0, 0 }, + { "mmDIG5_TMDS_CTL_BITS", REG_MMIO, 0x25da, 2, &mmDIG5_TMDS_CTL_BITS[0], sizeof(mmDIG5_TMDS_CTL_BITS)/sizeof(mmDIG5_TMDS_CTL_BITS[0]), 0, 0 }, + { "mmDIG5_TMDS_DCBALANCER_CONTROL", REG_MMIO, 0x25db, 2, &mmDIG5_TMDS_DCBALANCER_CONTROL[0], sizeof(mmDIG5_TMDS_DCBALANCER_CONTROL)/sizeof(mmDIG5_TMDS_DCBALANCER_CONTROL[0]), 0, 0 }, + { "mmDIG5_TMDS_CTL0_1_GEN_CNTL", REG_MMIO, 0x25dd, 2, &mmDIG5_TMDS_CTL0_1_GEN_CNTL[0], sizeof(mmDIG5_TMDS_CTL0_1_GEN_CNTL)/sizeof(mmDIG5_TMDS_CTL0_1_GEN_CNTL[0]), 0, 0 }, + { "mmDIG5_TMDS_CTL2_3_GEN_CNTL", REG_MMIO, 0x25de, 2, &mmDIG5_TMDS_CTL2_3_GEN_CNTL[0], sizeof(mmDIG5_TMDS_CTL2_3_GEN_CNTL)/sizeof(mmDIG5_TMDS_CTL2_3_GEN_CNTL[0]), 0, 0 }, + { "mmDIG5_DIG_VERSION", REG_MMIO, 0x25e0, 2, &mmDIG5_DIG_VERSION[0], sizeof(mmDIG5_DIG_VERSION)/sizeof(mmDIG5_DIG_VERSION[0]), 0, 0 }, + { "mmDIG5_DIG_LANE_ENABLE", REG_MMIO, 0x25e1, 2, &mmDIG5_DIG_LANE_ENABLE[0], sizeof(mmDIG5_DIG_LANE_ENABLE)/sizeof(mmDIG5_DIG_LANE_ENABLE[0]), 0, 0 }, + { "mmDIG5_AFMT_CNTL", REG_MMIO, 0x25e6, 2, &mmDIG5_AFMT_CNTL[0], sizeof(mmDIG5_AFMT_CNTL)/sizeof(mmDIG5_AFMT_CNTL[0]), 0, 0 }, + { "mmDIG5_AFMT_VBI_PACKET_CONTROL1", REG_MMIO, 0x25e7, 2, &mmDIG5_AFMT_VBI_PACKET_CONTROL1[0], sizeof(mmDIG5_AFMT_VBI_PACKET_CONTROL1)/sizeof(mmDIG5_AFMT_VBI_PACKET_CONTROL1[0]), 0, 0 }, + { "mmDP5_DP_LINK_CNTL", REG_MMIO, 0x2608, 2, &mmDP5_DP_LINK_CNTL[0], sizeof(mmDP5_DP_LINK_CNTL)/sizeof(mmDP5_DP_LINK_CNTL[0]), 0, 0 }, + { "mmDP5_DP_PIXEL_FORMAT", REG_MMIO, 0x2609, 2, &mmDP5_DP_PIXEL_FORMAT[0], sizeof(mmDP5_DP_PIXEL_FORMAT)/sizeof(mmDP5_DP_PIXEL_FORMAT[0]), 0, 0 }, + { "mmDP5_DP_MSA_COLORIMETRY", REG_MMIO, 0x260a, 2, &mmDP5_DP_MSA_COLORIMETRY[0], sizeof(mmDP5_DP_MSA_COLORIMETRY)/sizeof(mmDP5_DP_MSA_COLORIMETRY[0]), 0, 0 }, + { "mmDP5_DP_CONFIG", REG_MMIO, 0x260b, 2, &mmDP5_DP_CONFIG[0], sizeof(mmDP5_DP_CONFIG)/sizeof(mmDP5_DP_CONFIG[0]), 0, 0 }, + { "mmDP5_DP_VID_STREAM_CNTL", REG_MMIO, 0x260c, 2, &mmDP5_DP_VID_STREAM_CNTL[0], sizeof(mmDP5_DP_VID_STREAM_CNTL)/sizeof(mmDP5_DP_VID_STREAM_CNTL[0]), 0, 0 }, + { "mmDP5_DP_STEER_FIFO", REG_MMIO, 0x260d, 2, &mmDP5_DP_STEER_FIFO[0], sizeof(mmDP5_DP_STEER_FIFO)/sizeof(mmDP5_DP_STEER_FIFO[0]), 0, 0 }, + { "mmDP5_DP_MSA_MISC", REG_MMIO, 0x260e, 2, &mmDP5_DP_MSA_MISC[0], sizeof(mmDP5_DP_MSA_MISC)/sizeof(mmDP5_DP_MSA_MISC[0]), 0, 0 }, + { "mmDP5_DP_VID_TIMING", REG_MMIO, 0x2610, 2, &mmDP5_DP_VID_TIMING[0], sizeof(mmDP5_DP_VID_TIMING)/sizeof(mmDP5_DP_VID_TIMING[0]), 0, 0 }, + { "mmDP5_DP_VID_N", REG_MMIO, 0x2611, 2, &mmDP5_DP_VID_N[0], sizeof(mmDP5_DP_VID_N)/sizeof(mmDP5_DP_VID_N[0]), 0, 0 }, + { "mmDP5_DP_VID_M", REG_MMIO, 0x2612, 2, &mmDP5_DP_VID_M[0], sizeof(mmDP5_DP_VID_M)/sizeof(mmDP5_DP_VID_M[0]), 0, 0 }, + { "mmDP5_DP_LINK_FRAMING_CNTL", REG_MMIO, 0x2613, 2, &mmDP5_DP_LINK_FRAMING_CNTL[0], sizeof(mmDP5_DP_LINK_FRAMING_CNTL)/sizeof(mmDP5_DP_LINK_FRAMING_CNTL[0]), 0, 0 }, + { "mmDP5_DP_HBR2_EYE_PATTERN", REG_MMIO, 0x2614, 2, &mmDP5_DP_HBR2_EYE_PATTERN[0], sizeof(mmDP5_DP_HBR2_EYE_PATTERN)/sizeof(mmDP5_DP_HBR2_EYE_PATTERN[0]), 0, 0 }, + { "mmDP5_DP_VID_MSA_VBID", REG_MMIO, 0x2615, 2, &mmDP5_DP_VID_MSA_VBID[0], sizeof(mmDP5_DP_VID_MSA_VBID)/sizeof(mmDP5_DP_VID_MSA_VBID[0]), 0, 0 }, + { "mmDP5_DP_VID_INTERRUPT_CNTL", REG_MMIO, 0x2616, 2, &mmDP5_DP_VID_INTERRUPT_CNTL[0], sizeof(mmDP5_DP_VID_INTERRUPT_CNTL)/sizeof(mmDP5_DP_VID_INTERRUPT_CNTL[0]), 0, 0 }, + { "mmDP5_DP_DPHY_CNTL", REG_MMIO, 0x2617, 2, &mmDP5_DP_DPHY_CNTL[0], sizeof(mmDP5_DP_DPHY_CNTL)/sizeof(mmDP5_DP_DPHY_CNTL[0]), 0, 0 }, + { "mmDP5_DP_DPHY_TRAINING_PATTERN_SEL", REG_MMIO, 0x2618, 2, &mmDP5_DP_DPHY_TRAINING_PATTERN_SEL[0], sizeof(mmDP5_DP_DPHY_TRAINING_PATTERN_SEL)/sizeof(mmDP5_DP_DPHY_TRAINING_PATTERN_SEL[0]), 0, 0 }, + { "mmDP5_DP_DPHY_SYM0", REG_MMIO, 0x2619, 2, &mmDP5_DP_DPHY_SYM0[0], sizeof(mmDP5_DP_DPHY_SYM0)/sizeof(mmDP5_DP_DPHY_SYM0[0]), 0, 0 }, + { "mmDP5_DP_DPHY_SYM1", REG_MMIO, 0x261a, 2, &mmDP5_DP_DPHY_SYM1[0], sizeof(mmDP5_DP_DPHY_SYM1)/sizeof(mmDP5_DP_DPHY_SYM1[0]), 0, 0 }, + { "mmDP5_DP_DPHY_SYM2", REG_MMIO, 0x261b, 2, &mmDP5_DP_DPHY_SYM2[0], sizeof(mmDP5_DP_DPHY_SYM2)/sizeof(mmDP5_DP_DPHY_SYM2[0]), 0, 0 }, + { "mmDP5_DP_DPHY_8B10B_CNTL", REG_MMIO, 0x261c, 2, &mmDP5_DP_DPHY_8B10B_CNTL[0], sizeof(mmDP5_DP_DPHY_8B10B_CNTL)/sizeof(mmDP5_DP_DPHY_8B10B_CNTL[0]), 0, 0 }, + { "mmDP5_DP_DPHY_PRBS_CNTL", REG_MMIO, 0x261d, 2, &mmDP5_DP_DPHY_PRBS_CNTL[0], sizeof(mmDP5_DP_DPHY_PRBS_CNTL)/sizeof(mmDP5_DP_DPHY_PRBS_CNTL[0]), 0, 0 }, + { "mmDP5_DP_DPHY_SCRAM_CNTL", REG_MMIO, 0x261e, 2, &mmDP5_DP_DPHY_SCRAM_CNTL[0], sizeof(mmDP5_DP_DPHY_SCRAM_CNTL)/sizeof(mmDP5_DP_DPHY_SCRAM_CNTL[0]), 0, 0 }, + { "mmDP5_DP_DPHY_CRC_EN", REG_MMIO, 0x261f, 2, &mmDP5_DP_DPHY_CRC_EN[0], sizeof(mmDP5_DP_DPHY_CRC_EN)/sizeof(mmDP5_DP_DPHY_CRC_EN[0]), 0, 0 }, + { "mmDP5_DP_DPHY_CRC_CNTL", REG_MMIO, 0x2620, 2, &mmDP5_DP_DPHY_CRC_CNTL[0], sizeof(mmDP5_DP_DPHY_CRC_CNTL)/sizeof(mmDP5_DP_DPHY_CRC_CNTL[0]), 0, 0 }, + { "mmDP5_DP_DPHY_CRC_RESULT", REG_MMIO, 0x2621, 2, &mmDP5_DP_DPHY_CRC_RESULT[0], sizeof(mmDP5_DP_DPHY_CRC_RESULT)/sizeof(mmDP5_DP_DPHY_CRC_RESULT[0]), 0, 0 }, + { "mmDP5_DP_DPHY_CRC_MST_CNTL", REG_MMIO, 0x2622, 2, &mmDP5_DP_DPHY_CRC_MST_CNTL[0], sizeof(mmDP5_DP_DPHY_CRC_MST_CNTL)/sizeof(mmDP5_DP_DPHY_CRC_MST_CNTL[0]), 0, 0 }, + { "mmDP5_DP_DPHY_CRC_MST_STATUS", REG_MMIO, 0x2623, 2, &mmDP5_DP_DPHY_CRC_MST_STATUS[0], sizeof(mmDP5_DP_DPHY_CRC_MST_STATUS)/sizeof(mmDP5_DP_DPHY_CRC_MST_STATUS[0]), 0, 0 }, + { "mmDP5_DP_DPHY_FAST_TRAINING", REG_MMIO, 0x2624, 2, &mmDP5_DP_DPHY_FAST_TRAINING[0], sizeof(mmDP5_DP_DPHY_FAST_TRAINING)/sizeof(mmDP5_DP_DPHY_FAST_TRAINING[0]), 0, 0 }, + { "mmDP5_DP_DPHY_FAST_TRAINING_STATUS", REG_MMIO, 0x2625, 2, &mmDP5_DP_DPHY_FAST_TRAINING_STATUS[0], sizeof(mmDP5_DP_DPHY_FAST_TRAINING_STATUS)/sizeof(mmDP5_DP_DPHY_FAST_TRAINING_STATUS[0]), 0, 0 }, + { "mmDP5_DP_SEC_CNTL", REG_MMIO, 0x262b, 2, &mmDP5_DP_SEC_CNTL[0], sizeof(mmDP5_DP_SEC_CNTL)/sizeof(mmDP5_DP_SEC_CNTL[0]), 0, 0 }, + { "mmDP5_DP_SEC_CNTL1", REG_MMIO, 0x262c, 2, &mmDP5_DP_SEC_CNTL1[0], sizeof(mmDP5_DP_SEC_CNTL1)/sizeof(mmDP5_DP_SEC_CNTL1[0]), 0, 0 }, + { "mmDP5_DP_SEC_FRAMING1", REG_MMIO, 0x262d, 2, &mmDP5_DP_SEC_FRAMING1[0], sizeof(mmDP5_DP_SEC_FRAMING1)/sizeof(mmDP5_DP_SEC_FRAMING1[0]), 0, 0 }, + { "mmDP5_DP_SEC_FRAMING2", REG_MMIO, 0x262e, 2, &mmDP5_DP_SEC_FRAMING2[0], sizeof(mmDP5_DP_SEC_FRAMING2)/sizeof(mmDP5_DP_SEC_FRAMING2[0]), 0, 0 }, + { "mmDP5_DP_SEC_FRAMING3", REG_MMIO, 0x262f, 2, &mmDP5_DP_SEC_FRAMING3[0], sizeof(mmDP5_DP_SEC_FRAMING3)/sizeof(mmDP5_DP_SEC_FRAMING3[0]), 0, 0 }, + { "mmDP5_DP_SEC_FRAMING4", REG_MMIO, 0x2630, 2, &mmDP5_DP_SEC_FRAMING4[0], sizeof(mmDP5_DP_SEC_FRAMING4)/sizeof(mmDP5_DP_SEC_FRAMING4[0]), 0, 0 }, + { "mmDP5_DP_SEC_AUD_N", REG_MMIO, 0x2631, 2, &mmDP5_DP_SEC_AUD_N[0], sizeof(mmDP5_DP_SEC_AUD_N)/sizeof(mmDP5_DP_SEC_AUD_N[0]), 0, 0 }, + { "mmDP5_DP_SEC_AUD_N_READBACK", REG_MMIO, 0x2632, 2, &mmDP5_DP_SEC_AUD_N_READBACK[0], sizeof(mmDP5_DP_SEC_AUD_N_READBACK)/sizeof(mmDP5_DP_SEC_AUD_N_READBACK[0]), 0, 0 }, + { "mmDP5_DP_SEC_AUD_M", REG_MMIO, 0x2633, 2, &mmDP5_DP_SEC_AUD_M[0], sizeof(mmDP5_DP_SEC_AUD_M)/sizeof(mmDP5_DP_SEC_AUD_M[0]), 0, 0 }, + { "mmDP5_DP_SEC_AUD_M_READBACK", REG_MMIO, 0x2634, 2, &mmDP5_DP_SEC_AUD_M_READBACK[0], sizeof(mmDP5_DP_SEC_AUD_M_READBACK)/sizeof(mmDP5_DP_SEC_AUD_M_READBACK[0]), 0, 0 }, + { "mmDP5_DP_SEC_TIMESTAMP", REG_MMIO, 0x2635, 2, &mmDP5_DP_SEC_TIMESTAMP[0], sizeof(mmDP5_DP_SEC_TIMESTAMP)/sizeof(mmDP5_DP_SEC_TIMESTAMP[0]), 0, 0 }, + { "mmDP5_DP_SEC_PACKET_CNTL", REG_MMIO, 0x2636, 2, &mmDP5_DP_SEC_PACKET_CNTL[0], sizeof(mmDP5_DP_SEC_PACKET_CNTL)/sizeof(mmDP5_DP_SEC_PACKET_CNTL[0]), 0, 0 }, + { "mmDP5_DP_MSE_RATE_CNTL", REG_MMIO, 0x2637, 2, &mmDP5_DP_MSE_RATE_CNTL[0], sizeof(mmDP5_DP_MSE_RATE_CNTL)/sizeof(mmDP5_DP_MSE_RATE_CNTL[0]), 0, 0 }, + { "mmDP5_DP_MSE_RATE_UPDATE", REG_MMIO, 0x2639, 2, &mmDP5_DP_MSE_RATE_UPDATE[0], sizeof(mmDP5_DP_MSE_RATE_UPDATE)/sizeof(mmDP5_DP_MSE_RATE_UPDATE[0]), 0, 0 }, + { "mmDP5_DP_MSE_SAT0", REG_MMIO, 0x263a, 2, &mmDP5_DP_MSE_SAT0[0], sizeof(mmDP5_DP_MSE_SAT0)/sizeof(mmDP5_DP_MSE_SAT0[0]), 0, 0 }, + { "mmDP5_DP_MSE_SAT1", REG_MMIO, 0x263b, 2, &mmDP5_DP_MSE_SAT1[0], sizeof(mmDP5_DP_MSE_SAT1)/sizeof(mmDP5_DP_MSE_SAT1[0]), 0, 0 }, + { "mmDP5_DP_MSE_SAT2", REG_MMIO, 0x263c, 2, &mmDP5_DP_MSE_SAT2[0], sizeof(mmDP5_DP_MSE_SAT2)/sizeof(mmDP5_DP_MSE_SAT2[0]), 0, 0 }, + { "mmDP5_DP_MSE_SAT_UPDATE", REG_MMIO, 0x263d, 2, &mmDP5_DP_MSE_SAT_UPDATE[0], sizeof(mmDP5_DP_MSE_SAT_UPDATE)/sizeof(mmDP5_DP_MSE_SAT_UPDATE[0]), 0, 0 }, + { "mmDP5_DP_MSE_LINK_TIMING", REG_MMIO, 0x263e, 2, &mmDP5_DP_MSE_LINK_TIMING[0], sizeof(mmDP5_DP_MSE_LINK_TIMING)/sizeof(mmDP5_DP_MSE_LINK_TIMING[0]), 0, 0 }, + { "mmDP5_DP_MSE_MISC_CNTL", REG_MMIO, 0x263f, 2, &mmDP5_DP_MSE_MISC_CNTL[0], sizeof(mmDP5_DP_MSE_MISC_CNTL)/sizeof(mmDP5_DP_MSE_MISC_CNTL[0]), 0, 0 }, + { "mmDP5_DP_DPHY_BS_SR_SWAP_CNTL", REG_MMIO, 0x2644, 2, &mmDP5_DP_DPHY_BS_SR_SWAP_CNTL[0], sizeof(mmDP5_DP_DPHY_BS_SR_SWAP_CNTL)/sizeof(mmDP5_DP_DPHY_BS_SR_SWAP_CNTL[0]), 0, 0 }, + { "mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL", REG_MMIO, 0x2645, 2, &mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL[0], sizeof(mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL)/sizeof(mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL[0]), 0, 0 }, + { "mmDP5_DP_MSE_SAT0_STATUS", REG_MMIO, 0x2647, 2, &mmDP5_DP_MSE_SAT0_STATUS[0], sizeof(mmDP5_DP_MSE_SAT0_STATUS)/sizeof(mmDP5_DP_MSE_SAT0_STATUS[0]), 0, 0 }, + { "mmDP5_DP_MSE_SAT1_STATUS", REG_MMIO, 0x2648, 2, &mmDP5_DP_MSE_SAT1_STATUS[0], sizeof(mmDP5_DP_MSE_SAT1_STATUS)/sizeof(mmDP5_DP_MSE_SAT1_STATUS[0]), 0, 0 }, + { "mmDP5_DP_MSE_SAT2_STATUS", REG_MMIO, 0x2649, 2, &mmDP5_DP_MSE_SAT2_STATUS[0], sizeof(mmDP5_DP_MSE_SAT2_STATUS)/sizeof(mmDP5_DP_MSE_SAT2_STATUS[0]), 0, 0 }, + { "mmDP5_DP_MSA_TIMING_PARAM1", REG_MMIO, 0x264c, 2, &mmDP5_DP_MSA_TIMING_PARAM1[0], sizeof(mmDP5_DP_MSA_TIMING_PARAM1)/sizeof(mmDP5_DP_MSA_TIMING_PARAM1[0]), 0, 0 }, + { "mmDP5_DP_MSA_TIMING_PARAM2", REG_MMIO, 0x264d, 2, &mmDP5_DP_MSA_TIMING_PARAM2[0], sizeof(mmDP5_DP_MSA_TIMING_PARAM2)/sizeof(mmDP5_DP_MSA_TIMING_PARAM2[0]), 0, 0 }, + { "mmDP5_DP_MSA_TIMING_PARAM3", REG_MMIO, 0x264e, 2, &mmDP5_DP_MSA_TIMING_PARAM3[0], sizeof(mmDP5_DP_MSA_TIMING_PARAM3)/sizeof(mmDP5_DP_MSA_TIMING_PARAM3[0]), 0, 0 }, + { "mmDP5_DP_MSA_TIMING_PARAM4", REG_MMIO, 0x264f, 2, &mmDP5_DP_MSA_TIMING_PARAM4[0], sizeof(mmDP5_DP_MSA_TIMING_PARAM4)/sizeof(mmDP5_DP_MSA_TIMING_PARAM4[0]), 0, 0 }, + { "mmDP5_DP_MSO_CNTL", REG_MMIO, 0x2650, 2, &mmDP5_DP_MSO_CNTL[0], sizeof(mmDP5_DP_MSO_CNTL)/sizeof(mmDP5_DP_MSO_CNTL[0]), 0, 0 }, + { "mmDP5_DP_MSO_CNTL1", REG_MMIO, 0x2651, 2, &mmDP5_DP_MSO_CNTL1[0], sizeof(mmDP5_DP_MSO_CNTL1)/sizeof(mmDP5_DP_MSO_CNTL1[0]), 0, 0 }, + { "mmDP5_DP_DSC_CNTL", REG_MMIO, 0x2652, 2, &mmDP5_DP_DSC_CNTL[0], sizeof(mmDP5_DP_DSC_CNTL)/sizeof(mmDP5_DP_DSC_CNTL[0]), 0, 0 }, + { "mmDP5_DP_SEC_CNTL2", REG_MMIO, 0x2653, 2, &mmDP5_DP_SEC_CNTL2[0], sizeof(mmDP5_DP_SEC_CNTL2)/sizeof(mmDP5_DP_SEC_CNTL2[0]), 0, 0 }, + { "mmDP5_DP_SEC_CNTL3", REG_MMIO, 0x2654, 2, &mmDP5_DP_SEC_CNTL3[0], sizeof(mmDP5_DP_SEC_CNTL3)/sizeof(mmDP5_DP_SEC_CNTL3[0]), 0, 0 }, + { "mmDP5_DP_SEC_CNTL4", REG_MMIO, 0x2655, 2, &mmDP5_DP_SEC_CNTL4[0], sizeof(mmDP5_DP_SEC_CNTL4)/sizeof(mmDP5_DP_SEC_CNTL4[0]), 0, 0 }, + { "mmDP5_DP_SEC_CNTL5", REG_MMIO, 0x2656, 2, &mmDP5_DP_SEC_CNTL5[0], sizeof(mmDP5_DP_SEC_CNTL5)/sizeof(mmDP5_DP_SEC_CNTL5[0]), 0, 0 }, + { "mmDP5_DP_SEC_CNTL6", REG_MMIO, 0x2657, 2, &mmDP5_DP_SEC_CNTL6[0], sizeof(mmDP5_DP_SEC_CNTL6)/sizeof(mmDP5_DP_SEC_CNTL6[0]), 0, 0 }, + { "mmDP5_DP_SEC_CNTL7", REG_MMIO, 0x2658, 2, &mmDP5_DP_SEC_CNTL7[0], sizeof(mmDP5_DP_SEC_CNTL7)/sizeof(mmDP5_DP_SEC_CNTL7[0]), 0, 0 }, + { "mmDP5_DP_DB_CNTL", REG_MMIO, 0x2659, 2, &mmDP5_DP_DB_CNTL[0], sizeof(mmDP5_DP_DB_CNTL)/sizeof(mmDP5_DP_DB_CNTL[0]), 0, 0 }, + { "mmDP5_DP_MSA_VBID_MISC", REG_MMIO, 0x265a, 2, &mmDP5_DP_MSA_VBID_MISC[0], sizeof(mmDP5_DP_MSA_VBID_MISC)/sizeof(mmDP5_DP_MSA_VBID_MISC[0]), 0, 0 }, + { "mmDIG6_DIG_FE_CNTL", REG_MMIO, 0x2668, 2, &mmDIG6_DIG_FE_CNTL[0], sizeof(mmDIG6_DIG_FE_CNTL)/sizeof(mmDIG6_DIG_FE_CNTL[0]), 0, 0 }, + { "mmDIG6_DIG_OUTPUT_CRC_CNTL", REG_MMIO, 0x2669, 2, &mmDIG6_DIG_OUTPUT_CRC_CNTL[0], sizeof(mmDIG6_DIG_OUTPUT_CRC_CNTL)/sizeof(mmDIG6_DIG_OUTPUT_CRC_CNTL[0]), 0, 0 }, + { "mmDIG6_DIG_OUTPUT_CRC_RESULT", REG_MMIO, 0x266a, 2, &mmDIG6_DIG_OUTPUT_CRC_RESULT[0], sizeof(mmDIG6_DIG_OUTPUT_CRC_RESULT)/sizeof(mmDIG6_DIG_OUTPUT_CRC_RESULT[0]), 0, 0 }, + { "mmDIG6_DIG_CLOCK_PATTERN", REG_MMIO, 0x266b, 2, &mmDIG6_DIG_CLOCK_PATTERN[0], sizeof(mmDIG6_DIG_CLOCK_PATTERN)/sizeof(mmDIG6_DIG_CLOCK_PATTERN[0]), 0, 0 }, + { "mmDIG6_DIG_TEST_PATTERN", REG_MMIO, 0x266c, 2, &mmDIG6_DIG_TEST_PATTERN[0], sizeof(mmDIG6_DIG_TEST_PATTERN)/sizeof(mmDIG6_DIG_TEST_PATTERN[0]), 0, 0 }, + { "mmDIG6_DIG_RANDOM_PATTERN_SEED", REG_MMIO, 0x266d, 2, &mmDIG6_DIG_RANDOM_PATTERN_SEED[0], sizeof(mmDIG6_DIG_RANDOM_PATTERN_SEED)/sizeof(mmDIG6_DIG_RANDOM_PATTERN_SEED[0]), 0, 0 }, + { "mmDIG6_DIG_FIFO_STATUS", REG_MMIO, 0x266e, 2, &mmDIG6_DIG_FIFO_STATUS[0], sizeof(mmDIG6_DIG_FIFO_STATUS)/sizeof(mmDIG6_DIG_FIFO_STATUS[0]), 0, 0 }, + { "mmDIG6_HDMI_CONTROL", REG_MMIO, 0x2671, 2, &mmDIG6_HDMI_CONTROL[0], sizeof(mmDIG6_HDMI_CONTROL)/sizeof(mmDIG6_HDMI_CONTROL[0]), 0, 0 }, + { "mmDIG6_HDMI_STATUS", REG_MMIO, 0x2672, 2, &mmDIG6_HDMI_STATUS[0], sizeof(mmDIG6_HDMI_STATUS)/sizeof(mmDIG6_HDMI_STATUS[0]), 0, 0 }, + { "mmDIG6_HDMI_AUDIO_PACKET_CONTROL", REG_MMIO, 0x2673, 2, &mmDIG6_HDMI_AUDIO_PACKET_CONTROL[0], sizeof(mmDIG6_HDMI_AUDIO_PACKET_CONTROL)/sizeof(mmDIG6_HDMI_AUDIO_PACKET_CONTROL[0]), 0, 0 }, + { "mmDIG6_HDMI_ACR_PACKET_CONTROL", REG_MMIO, 0x2674, 2, &mmDIG6_HDMI_ACR_PACKET_CONTROL[0], sizeof(mmDIG6_HDMI_ACR_PACKET_CONTROL)/sizeof(mmDIG6_HDMI_ACR_PACKET_CONTROL[0]), 0, 0 }, + { "mmDIG6_HDMI_VBI_PACKET_CONTROL", REG_MMIO, 0x2675, 2, &mmDIG6_HDMI_VBI_PACKET_CONTROL[0], sizeof(mmDIG6_HDMI_VBI_PACKET_CONTROL)/sizeof(mmDIG6_HDMI_VBI_PACKET_CONTROL[0]), 0, 0 }, + { "mmDIG6_HDMI_INFOFRAME_CONTROL0", REG_MMIO, 0x2676, 2, &mmDIG6_HDMI_INFOFRAME_CONTROL0[0], sizeof(mmDIG6_HDMI_INFOFRAME_CONTROL0)/sizeof(mmDIG6_HDMI_INFOFRAME_CONTROL0[0]), 0, 0 }, + { "mmDIG6_HDMI_INFOFRAME_CONTROL1", REG_MMIO, 0x2677, 2, &mmDIG6_HDMI_INFOFRAME_CONTROL1[0], sizeof(mmDIG6_HDMI_INFOFRAME_CONTROL1)/sizeof(mmDIG6_HDMI_INFOFRAME_CONTROL1[0]), 0, 0 }, + { "mmDIG6_HDMI_GENERIC_PACKET_CONTROL0", REG_MMIO, 0x2678, 2, &mmDIG6_HDMI_GENERIC_PACKET_CONTROL0[0], sizeof(mmDIG6_HDMI_GENERIC_PACKET_CONTROL0)/sizeof(mmDIG6_HDMI_GENERIC_PACKET_CONTROL0[0]), 0, 0 }, + { "mmDIG6_AFMT_INTERRUPT_STATUS", REG_MMIO, 0x2679, 2, NULL, 0, 0, 0 }, + { "mmDIG6_HDMI_GC", REG_MMIO, 0x267b, 2, &mmDIG6_HDMI_GC[0], sizeof(mmDIG6_HDMI_GC)/sizeof(mmDIG6_HDMI_GC[0]), 0, 0 }, + { "mmDIG6_AFMT_AUDIO_PACKET_CONTROL2", REG_MMIO, 0x267c, 2, &mmDIG6_AFMT_AUDIO_PACKET_CONTROL2[0], sizeof(mmDIG6_AFMT_AUDIO_PACKET_CONTROL2)/sizeof(mmDIG6_AFMT_AUDIO_PACKET_CONTROL2[0]), 0, 0 }, + { "mmDIG6_AFMT_ISRC1_0", REG_MMIO, 0x267d, 2, &mmDIG6_AFMT_ISRC1_0[0], sizeof(mmDIG6_AFMT_ISRC1_0)/sizeof(mmDIG6_AFMT_ISRC1_0[0]), 0, 0 }, + { "mmDIG6_AFMT_ISRC1_1", REG_MMIO, 0x267e, 2, &mmDIG6_AFMT_ISRC1_1[0], sizeof(mmDIG6_AFMT_ISRC1_1)/sizeof(mmDIG6_AFMT_ISRC1_1[0]), 0, 0 }, + { "mmDIG6_AFMT_ISRC1_2", REG_MMIO, 0x267f, 2, &mmDIG6_AFMT_ISRC1_2[0], sizeof(mmDIG6_AFMT_ISRC1_2)/sizeof(mmDIG6_AFMT_ISRC1_2[0]), 0, 0 }, + { "mmDIG6_AFMT_ISRC1_3", REG_MMIO, 0x2680, 2, &mmDIG6_AFMT_ISRC1_3[0], sizeof(mmDIG6_AFMT_ISRC1_3)/sizeof(mmDIG6_AFMT_ISRC1_3[0]), 0, 0 }, + { "mmDIG6_AFMT_ISRC1_4", REG_MMIO, 0x2681, 2, &mmDIG6_AFMT_ISRC1_4[0], sizeof(mmDIG6_AFMT_ISRC1_4)/sizeof(mmDIG6_AFMT_ISRC1_4[0]), 0, 0 }, + { "mmDIG6_AFMT_ISRC2_0", REG_MMIO, 0x2682, 2, &mmDIG6_AFMT_ISRC2_0[0], sizeof(mmDIG6_AFMT_ISRC2_0)/sizeof(mmDIG6_AFMT_ISRC2_0[0]), 0, 0 }, + { "mmDIG6_AFMT_ISRC2_1", REG_MMIO, 0x2683, 2, &mmDIG6_AFMT_ISRC2_1[0], sizeof(mmDIG6_AFMT_ISRC2_1)/sizeof(mmDIG6_AFMT_ISRC2_1[0]), 0, 0 }, + { "mmDIG6_AFMT_ISRC2_2", REG_MMIO, 0x2684, 2, &mmDIG6_AFMT_ISRC2_2[0], sizeof(mmDIG6_AFMT_ISRC2_2)/sizeof(mmDIG6_AFMT_ISRC2_2[0]), 0, 0 }, + { "mmDIG6_AFMT_ISRC2_3", REG_MMIO, 0x2685, 2, &mmDIG6_AFMT_ISRC2_3[0], sizeof(mmDIG6_AFMT_ISRC2_3)/sizeof(mmDIG6_AFMT_ISRC2_3[0]), 0, 0 }, + { "mmDIG6_HDMI_GENERIC_PACKET_CONTROL2", REG_MMIO, 0x2686, 2, &mmDIG6_HDMI_GENERIC_PACKET_CONTROL2[0], sizeof(mmDIG6_HDMI_GENERIC_PACKET_CONTROL2)/sizeof(mmDIG6_HDMI_GENERIC_PACKET_CONTROL2[0]), 0, 0 }, + { "mmDIG6_HDMI_GENERIC_PACKET_CONTROL3", REG_MMIO, 0x2687, 2, &mmDIG6_HDMI_GENERIC_PACKET_CONTROL3[0], sizeof(mmDIG6_HDMI_GENERIC_PACKET_CONTROL3)/sizeof(mmDIG6_HDMI_GENERIC_PACKET_CONTROL3[0]), 0, 0 }, + { "mmDIG6_HDMI_DB_CONTROL", REG_MMIO, 0x2688, 2, &mmDIG6_HDMI_DB_CONTROL[0], sizeof(mmDIG6_HDMI_DB_CONTROL)/sizeof(mmDIG6_HDMI_DB_CONTROL[0]), 0, 0 }, + { "mmDIG6_AFMT_MPEG_INFO0", REG_MMIO, 0x268a, 2, &mmDIG6_AFMT_MPEG_INFO0[0], sizeof(mmDIG6_AFMT_MPEG_INFO0)/sizeof(mmDIG6_AFMT_MPEG_INFO0[0]), 0, 0 }, + { "mmDIG6_AFMT_MPEG_INFO1", REG_MMIO, 0x268b, 2, &mmDIG6_AFMT_MPEG_INFO1[0], sizeof(mmDIG6_AFMT_MPEG_INFO1)/sizeof(mmDIG6_AFMT_MPEG_INFO1[0]), 0, 0 }, + { "mmDIG6_AFMT_GENERIC_HDR", REG_MMIO, 0x268c, 2, &mmDIG6_AFMT_GENERIC_HDR[0], sizeof(mmDIG6_AFMT_GENERIC_HDR)/sizeof(mmDIG6_AFMT_GENERIC_HDR[0]), 0, 0 }, + { "mmDIG6_AFMT_GENERIC_0", REG_MMIO, 0x268d, 2, &mmDIG6_AFMT_GENERIC_0[0], sizeof(mmDIG6_AFMT_GENERIC_0)/sizeof(mmDIG6_AFMT_GENERIC_0[0]), 0, 0 }, + { "mmDIG6_AFMT_GENERIC_1", REG_MMIO, 0x268e, 2, &mmDIG6_AFMT_GENERIC_1[0], sizeof(mmDIG6_AFMT_GENERIC_1)/sizeof(mmDIG6_AFMT_GENERIC_1[0]), 0, 0 }, + { "mmDIG6_AFMT_GENERIC_2", REG_MMIO, 0x268f, 2, &mmDIG6_AFMT_GENERIC_2[0], sizeof(mmDIG6_AFMT_GENERIC_2)/sizeof(mmDIG6_AFMT_GENERIC_2[0]), 0, 0 }, + { "mmDIG6_AFMT_GENERIC_3", REG_MMIO, 0x2690, 2, &mmDIG6_AFMT_GENERIC_3[0], sizeof(mmDIG6_AFMT_GENERIC_3)/sizeof(mmDIG6_AFMT_GENERIC_3[0]), 0, 0 }, + { "mmDIG6_AFMT_GENERIC_4", REG_MMIO, 0x2691, 2, &mmDIG6_AFMT_GENERIC_4[0], sizeof(mmDIG6_AFMT_GENERIC_4)/sizeof(mmDIG6_AFMT_GENERIC_4[0]), 0, 0 }, + { "mmDIG6_AFMT_GENERIC_5", REG_MMIO, 0x2692, 2, &mmDIG6_AFMT_GENERIC_5[0], sizeof(mmDIG6_AFMT_GENERIC_5)/sizeof(mmDIG6_AFMT_GENERIC_5[0]), 0, 0 }, + { "mmDIG6_AFMT_GENERIC_6", REG_MMIO, 0x2693, 2, &mmDIG6_AFMT_GENERIC_6[0], sizeof(mmDIG6_AFMT_GENERIC_6)/sizeof(mmDIG6_AFMT_GENERIC_6[0]), 0, 0 }, + { "mmDIG6_AFMT_GENERIC_7", REG_MMIO, 0x2694, 2, &mmDIG6_AFMT_GENERIC_7[0], sizeof(mmDIG6_AFMT_GENERIC_7)/sizeof(mmDIG6_AFMT_GENERIC_7[0]), 0, 0 }, + { "mmDIG6_HDMI_GENERIC_PACKET_CONTROL1", REG_MMIO, 0x2695, 2, &mmDIG6_HDMI_GENERIC_PACKET_CONTROL1[0], sizeof(mmDIG6_HDMI_GENERIC_PACKET_CONTROL1)/sizeof(mmDIG6_HDMI_GENERIC_PACKET_CONTROL1[0]), 0, 0 }, + { "mmDIG6_HDMI_ACR_32_0", REG_MMIO, 0x2696, 2, &mmDIG6_HDMI_ACR_32_0[0], sizeof(mmDIG6_HDMI_ACR_32_0)/sizeof(mmDIG6_HDMI_ACR_32_0[0]), 0, 0 }, + { "mmDIG6_HDMI_ACR_32_1", REG_MMIO, 0x2697, 2, &mmDIG6_HDMI_ACR_32_1[0], sizeof(mmDIG6_HDMI_ACR_32_1)/sizeof(mmDIG6_HDMI_ACR_32_1[0]), 0, 0 }, + { "mmDIG6_HDMI_ACR_44_0", REG_MMIO, 0x2698, 2, &mmDIG6_HDMI_ACR_44_0[0], sizeof(mmDIG6_HDMI_ACR_44_0)/sizeof(mmDIG6_HDMI_ACR_44_0[0]), 0, 0 }, + { "mmDIG6_HDMI_ACR_44_1", REG_MMIO, 0x2699, 2, &mmDIG6_HDMI_ACR_44_1[0], sizeof(mmDIG6_HDMI_ACR_44_1)/sizeof(mmDIG6_HDMI_ACR_44_1[0]), 0, 0 }, + { "mmDIG6_HDMI_ACR_48_0", REG_MMIO, 0x269a, 2, &mmDIG6_HDMI_ACR_48_0[0], sizeof(mmDIG6_HDMI_ACR_48_0)/sizeof(mmDIG6_HDMI_ACR_48_0[0]), 0, 0 }, + { "mmDIG6_HDMI_ACR_48_1", REG_MMIO, 0x269b, 2, &mmDIG6_HDMI_ACR_48_1[0], sizeof(mmDIG6_HDMI_ACR_48_1)/sizeof(mmDIG6_HDMI_ACR_48_1[0]), 0, 0 }, + { "mmDIG6_HDMI_ACR_STATUS_0", REG_MMIO, 0x269c, 2, &mmDIG6_HDMI_ACR_STATUS_0[0], sizeof(mmDIG6_HDMI_ACR_STATUS_0)/sizeof(mmDIG6_HDMI_ACR_STATUS_0[0]), 0, 0 }, + { "mmDIG6_HDMI_ACR_STATUS_1", REG_MMIO, 0x269d, 2, &mmDIG6_HDMI_ACR_STATUS_1[0], sizeof(mmDIG6_HDMI_ACR_STATUS_1)/sizeof(mmDIG6_HDMI_ACR_STATUS_1[0]), 0, 0 }, + { "mmDIG6_AFMT_AUDIO_INFO0", REG_MMIO, 0x269e, 2, &mmDIG6_AFMT_AUDIO_INFO0[0], sizeof(mmDIG6_AFMT_AUDIO_INFO0)/sizeof(mmDIG6_AFMT_AUDIO_INFO0[0]), 0, 0 }, + { "mmDIG6_AFMT_AUDIO_INFO1", REG_MMIO, 0x269f, 2, &mmDIG6_AFMT_AUDIO_INFO1[0], sizeof(mmDIG6_AFMT_AUDIO_INFO1)/sizeof(mmDIG6_AFMT_AUDIO_INFO1[0]), 0, 0 }, + { "mmDIG6_AFMT_60958_0", REG_MMIO, 0x26a0, 2, &mmDIG6_AFMT_60958_0[0], sizeof(mmDIG6_AFMT_60958_0)/sizeof(mmDIG6_AFMT_60958_0[0]), 0, 0 }, + { "mmDIG6_AFMT_60958_1", REG_MMIO, 0x26a1, 2, &mmDIG6_AFMT_60958_1[0], sizeof(mmDIG6_AFMT_60958_1)/sizeof(mmDIG6_AFMT_60958_1[0]), 0, 0 }, + { "mmDIG6_AFMT_AUDIO_CRC_CONTROL", REG_MMIO, 0x26a2, 2, &mmDIG6_AFMT_AUDIO_CRC_CONTROL[0], sizeof(mmDIG6_AFMT_AUDIO_CRC_CONTROL)/sizeof(mmDIG6_AFMT_AUDIO_CRC_CONTROL[0]), 0, 0 }, + { "mmDIG6_AFMT_RAMP_CONTROL0", REG_MMIO, 0x26a3, 2, &mmDIG6_AFMT_RAMP_CONTROL0[0], sizeof(mmDIG6_AFMT_RAMP_CONTROL0)/sizeof(mmDIG6_AFMT_RAMP_CONTROL0[0]), 0, 0 }, + { "mmDIG6_AFMT_RAMP_CONTROL1", REG_MMIO, 0x26a4, 2, &mmDIG6_AFMT_RAMP_CONTROL1[0], sizeof(mmDIG6_AFMT_RAMP_CONTROL1)/sizeof(mmDIG6_AFMT_RAMP_CONTROL1[0]), 0, 0 }, + { "mmDIG6_AFMT_RAMP_CONTROL2", REG_MMIO, 0x26a5, 2, &mmDIG6_AFMT_RAMP_CONTROL2[0], sizeof(mmDIG6_AFMT_RAMP_CONTROL2)/sizeof(mmDIG6_AFMT_RAMP_CONTROL2[0]), 0, 0 }, + { "mmDIG6_AFMT_RAMP_CONTROL3", REG_MMIO, 0x26a6, 2, &mmDIG6_AFMT_RAMP_CONTROL3[0], sizeof(mmDIG6_AFMT_RAMP_CONTROL3)/sizeof(mmDIG6_AFMT_RAMP_CONTROL3[0]), 0, 0 }, + { "mmDIG6_AFMT_60958_2", REG_MMIO, 0x26a7, 2, &mmDIG6_AFMT_60958_2[0], sizeof(mmDIG6_AFMT_60958_2)/sizeof(mmDIG6_AFMT_60958_2[0]), 0, 0 }, + { "mmDIG6_AFMT_AUDIO_CRC_RESULT", REG_MMIO, 0x26a8, 2, &mmDIG6_AFMT_AUDIO_CRC_RESULT[0], sizeof(mmDIG6_AFMT_AUDIO_CRC_RESULT)/sizeof(mmDIG6_AFMT_AUDIO_CRC_RESULT[0]), 0, 0 }, + { "mmDIG6_AFMT_STATUS", REG_MMIO, 0x26a9, 2, &mmDIG6_AFMT_STATUS[0], sizeof(mmDIG6_AFMT_STATUS)/sizeof(mmDIG6_AFMT_STATUS[0]), 0, 0 }, + { "mmDIG6_AFMT_AUDIO_PACKET_CONTROL", REG_MMIO, 0x26aa, 2, &mmDIG6_AFMT_AUDIO_PACKET_CONTROL[0], sizeof(mmDIG6_AFMT_AUDIO_PACKET_CONTROL)/sizeof(mmDIG6_AFMT_AUDIO_PACKET_CONTROL[0]), 0, 0 }, + { "mmDIG6_AFMT_VBI_PACKET_CONTROL", REG_MMIO, 0x26ab, 2, &mmDIG6_AFMT_VBI_PACKET_CONTROL[0], sizeof(mmDIG6_AFMT_VBI_PACKET_CONTROL)/sizeof(mmDIG6_AFMT_VBI_PACKET_CONTROL[0]), 0, 0 }, + { "mmDIG6_AFMT_INFOFRAME_CONTROL0", REG_MMIO, 0x26ac, 2, &mmDIG6_AFMT_INFOFRAME_CONTROL0[0], sizeof(mmDIG6_AFMT_INFOFRAME_CONTROL0)/sizeof(mmDIG6_AFMT_INFOFRAME_CONTROL0[0]), 0, 0 }, + { "mmDIG6_AFMT_AUDIO_SRC_CONTROL", REG_MMIO, 0x26ad, 2, &mmDIG6_AFMT_AUDIO_SRC_CONTROL[0], sizeof(mmDIG6_AFMT_AUDIO_SRC_CONTROL)/sizeof(mmDIG6_AFMT_AUDIO_SRC_CONTROL[0]), 0, 0 }, + { "mmDIG6_DIG_BE_CNTL", REG_MMIO, 0x26af, 2, &mmDIG6_DIG_BE_CNTL[0], sizeof(mmDIG6_DIG_BE_CNTL)/sizeof(mmDIG6_DIG_BE_CNTL[0]), 0, 0 }, + { "mmDIG6_DIG_BE_EN_CNTL", REG_MMIO, 0x26b0, 2, &mmDIG6_DIG_BE_EN_CNTL[0], sizeof(mmDIG6_DIG_BE_EN_CNTL)/sizeof(mmDIG6_DIG_BE_EN_CNTL[0]), 0, 0 }, + { "mmDIG6_TMDS_CNTL", REG_MMIO, 0x26d3, 2, &mmDIG6_TMDS_CNTL[0], sizeof(mmDIG6_TMDS_CNTL)/sizeof(mmDIG6_TMDS_CNTL[0]), 0, 0 }, + { "mmDIG6_TMDS_CONTROL_CHAR", REG_MMIO, 0x26d4, 2, &mmDIG6_TMDS_CONTROL_CHAR[0], sizeof(mmDIG6_TMDS_CONTROL_CHAR)/sizeof(mmDIG6_TMDS_CONTROL_CHAR[0]), 0, 0 }, + { "mmDIG6_TMDS_CONTROL0_FEEDBACK", REG_MMIO, 0x26d5, 2, &mmDIG6_TMDS_CONTROL0_FEEDBACK[0], sizeof(mmDIG6_TMDS_CONTROL0_FEEDBACK)/sizeof(mmDIG6_TMDS_CONTROL0_FEEDBACK[0]), 0, 0 }, + { "mmDIG6_TMDS_STEREOSYNC_CTL_SEL", REG_MMIO, 0x26d6, 2, &mmDIG6_TMDS_STEREOSYNC_CTL_SEL[0], sizeof(mmDIG6_TMDS_STEREOSYNC_CTL_SEL)/sizeof(mmDIG6_TMDS_STEREOSYNC_CTL_SEL[0]), 0, 0 }, + { "mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1", REG_MMIO, 0x26d7, 2, &mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1[0], sizeof(mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1)/sizeof(mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1[0]), 0, 0 }, + { "mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3", REG_MMIO, 0x26d8, 2, &mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3[0], sizeof(mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3)/sizeof(mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3[0]), 0, 0 }, + { "mmDIG6_TMDS_CTL_BITS", REG_MMIO, 0x26da, 2, &mmDIG6_TMDS_CTL_BITS[0], sizeof(mmDIG6_TMDS_CTL_BITS)/sizeof(mmDIG6_TMDS_CTL_BITS[0]), 0, 0 }, + { "mmDIG6_TMDS_DCBALANCER_CONTROL", REG_MMIO, 0x26db, 2, &mmDIG6_TMDS_DCBALANCER_CONTROL[0], sizeof(mmDIG6_TMDS_DCBALANCER_CONTROL)/sizeof(mmDIG6_TMDS_DCBALANCER_CONTROL[0]), 0, 0 }, + { "mmDIG6_TMDS_CTL0_1_GEN_CNTL", REG_MMIO, 0x26dd, 2, &mmDIG6_TMDS_CTL0_1_GEN_CNTL[0], sizeof(mmDIG6_TMDS_CTL0_1_GEN_CNTL)/sizeof(mmDIG6_TMDS_CTL0_1_GEN_CNTL[0]), 0, 0 }, + { "mmDIG6_TMDS_CTL2_3_GEN_CNTL", REG_MMIO, 0x26de, 2, &mmDIG6_TMDS_CTL2_3_GEN_CNTL[0], sizeof(mmDIG6_TMDS_CTL2_3_GEN_CNTL)/sizeof(mmDIG6_TMDS_CTL2_3_GEN_CNTL[0]), 0, 0 }, + { "mmDIG6_DIG_VERSION", REG_MMIO, 0x26e0, 2, &mmDIG6_DIG_VERSION[0], sizeof(mmDIG6_DIG_VERSION)/sizeof(mmDIG6_DIG_VERSION[0]), 0, 0 }, + { "mmDIG6_DIG_LANE_ENABLE", REG_MMIO, 0x26e1, 2, &mmDIG6_DIG_LANE_ENABLE[0], sizeof(mmDIG6_DIG_LANE_ENABLE)/sizeof(mmDIG6_DIG_LANE_ENABLE[0]), 0, 0 }, + { "mmDIG6_AFMT_CNTL", REG_MMIO, 0x26e6, 2, &mmDIG6_AFMT_CNTL[0], sizeof(mmDIG6_AFMT_CNTL)/sizeof(mmDIG6_AFMT_CNTL[0]), 0, 0 }, + { "mmDIG6_AFMT_VBI_PACKET_CONTROL1", REG_MMIO, 0x26e7, 2, &mmDIG6_AFMT_VBI_PACKET_CONTROL1[0], sizeof(mmDIG6_AFMT_VBI_PACKET_CONTROL1)/sizeof(mmDIG6_AFMT_VBI_PACKET_CONTROL1[0]), 0, 0 }, + { "mmDP6_DP_LINK_CNTL", REG_MMIO, 0x2708, 2, &mmDP6_DP_LINK_CNTL[0], sizeof(mmDP6_DP_LINK_CNTL)/sizeof(mmDP6_DP_LINK_CNTL[0]), 0, 0 }, + { "mmDP6_DP_PIXEL_FORMAT", REG_MMIO, 0x2709, 2, &mmDP6_DP_PIXEL_FORMAT[0], sizeof(mmDP6_DP_PIXEL_FORMAT)/sizeof(mmDP6_DP_PIXEL_FORMAT[0]), 0, 0 }, + { "mmDP6_DP_MSA_COLORIMETRY", REG_MMIO, 0x270a, 2, &mmDP6_DP_MSA_COLORIMETRY[0], sizeof(mmDP6_DP_MSA_COLORIMETRY)/sizeof(mmDP6_DP_MSA_COLORIMETRY[0]), 0, 0 }, + { "mmDP6_DP_CONFIG", REG_MMIO, 0x270b, 2, &mmDP6_DP_CONFIG[0], sizeof(mmDP6_DP_CONFIG)/sizeof(mmDP6_DP_CONFIG[0]), 0, 0 }, + { "mmDP6_DP_VID_STREAM_CNTL", REG_MMIO, 0x270c, 2, &mmDP6_DP_VID_STREAM_CNTL[0], sizeof(mmDP6_DP_VID_STREAM_CNTL)/sizeof(mmDP6_DP_VID_STREAM_CNTL[0]), 0, 0 }, + { "mmDP6_DP_STEER_FIFO", REG_MMIO, 0x270d, 2, &mmDP6_DP_STEER_FIFO[0], sizeof(mmDP6_DP_STEER_FIFO)/sizeof(mmDP6_DP_STEER_FIFO[0]), 0, 0 }, + { "mmDP6_DP_MSA_MISC", REG_MMIO, 0x270e, 2, &mmDP6_DP_MSA_MISC[0], sizeof(mmDP6_DP_MSA_MISC)/sizeof(mmDP6_DP_MSA_MISC[0]), 0, 0 }, + { "mmDP6_DP_VID_TIMING", REG_MMIO, 0x2710, 2, &mmDP6_DP_VID_TIMING[0], sizeof(mmDP6_DP_VID_TIMING)/sizeof(mmDP6_DP_VID_TIMING[0]), 0, 0 }, + { "mmDP6_DP_VID_N", REG_MMIO, 0x2711, 2, &mmDP6_DP_VID_N[0], sizeof(mmDP6_DP_VID_N)/sizeof(mmDP6_DP_VID_N[0]), 0, 0 }, + { "mmDP6_DP_VID_M", REG_MMIO, 0x2712, 2, &mmDP6_DP_VID_M[0], sizeof(mmDP6_DP_VID_M)/sizeof(mmDP6_DP_VID_M[0]), 0, 0 }, + { "mmDP6_DP_LINK_FRAMING_CNTL", REG_MMIO, 0x2713, 2, &mmDP6_DP_LINK_FRAMING_CNTL[0], sizeof(mmDP6_DP_LINK_FRAMING_CNTL)/sizeof(mmDP6_DP_LINK_FRAMING_CNTL[0]), 0, 0 }, + { "mmDP6_DP_HBR2_EYE_PATTERN", REG_MMIO, 0x2714, 2, &mmDP6_DP_HBR2_EYE_PATTERN[0], sizeof(mmDP6_DP_HBR2_EYE_PATTERN)/sizeof(mmDP6_DP_HBR2_EYE_PATTERN[0]), 0, 0 }, + { "mmDP6_DP_VID_MSA_VBID", REG_MMIO, 0x2715, 2, &mmDP6_DP_VID_MSA_VBID[0], sizeof(mmDP6_DP_VID_MSA_VBID)/sizeof(mmDP6_DP_VID_MSA_VBID[0]), 0, 0 }, + { "mmDP6_DP_VID_INTERRUPT_CNTL", REG_MMIO, 0x2716, 2, &mmDP6_DP_VID_INTERRUPT_CNTL[0], sizeof(mmDP6_DP_VID_INTERRUPT_CNTL)/sizeof(mmDP6_DP_VID_INTERRUPT_CNTL[0]), 0, 0 }, + { "mmDP6_DP_DPHY_CNTL", REG_MMIO, 0x2717, 2, &mmDP6_DP_DPHY_CNTL[0], sizeof(mmDP6_DP_DPHY_CNTL)/sizeof(mmDP6_DP_DPHY_CNTL[0]), 0, 0 }, + { "mmDP6_DP_DPHY_TRAINING_PATTERN_SEL", REG_MMIO, 0x2718, 2, &mmDP6_DP_DPHY_TRAINING_PATTERN_SEL[0], sizeof(mmDP6_DP_DPHY_TRAINING_PATTERN_SEL)/sizeof(mmDP6_DP_DPHY_TRAINING_PATTERN_SEL[0]), 0, 0 }, + { "mmDP6_DP_DPHY_SYM0", REG_MMIO, 0x2719, 2, &mmDP6_DP_DPHY_SYM0[0], sizeof(mmDP6_DP_DPHY_SYM0)/sizeof(mmDP6_DP_DPHY_SYM0[0]), 0, 0 }, + { "mmDP6_DP_DPHY_SYM1", REG_MMIO, 0x271a, 2, &mmDP6_DP_DPHY_SYM1[0], sizeof(mmDP6_DP_DPHY_SYM1)/sizeof(mmDP6_DP_DPHY_SYM1[0]), 0, 0 }, + { "mmDP6_DP_DPHY_SYM2", REG_MMIO, 0x271b, 2, &mmDP6_DP_DPHY_SYM2[0], sizeof(mmDP6_DP_DPHY_SYM2)/sizeof(mmDP6_DP_DPHY_SYM2[0]), 0, 0 }, + { "mmDP6_DP_DPHY_8B10B_CNTL", REG_MMIO, 0x271c, 2, &mmDP6_DP_DPHY_8B10B_CNTL[0], sizeof(mmDP6_DP_DPHY_8B10B_CNTL)/sizeof(mmDP6_DP_DPHY_8B10B_CNTL[0]), 0, 0 }, + { "mmDP6_DP_DPHY_PRBS_CNTL", REG_MMIO, 0x271d, 2, &mmDP6_DP_DPHY_PRBS_CNTL[0], sizeof(mmDP6_DP_DPHY_PRBS_CNTL)/sizeof(mmDP6_DP_DPHY_PRBS_CNTL[0]), 0, 0 }, + { "mmDP6_DP_DPHY_SCRAM_CNTL", REG_MMIO, 0x271e, 2, &mmDP6_DP_DPHY_SCRAM_CNTL[0], sizeof(mmDP6_DP_DPHY_SCRAM_CNTL)/sizeof(mmDP6_DP_DPHY_SCRAM_CNTL[0]), 0, 0 }, + { "mmDP6_DP_DPHY_CRC_EN", REG_MMIO, 0x271f, 2, &mmDP6_DP_DPHY_CRC_EN[0], sizeof(mmDP6_DP_DPHY_CRC_EN)/sizeof(mmDP6_DP_DPHY_CRC_EN[0]), 0, 0 }, + { "mmDP6_DP_DPHY_CRC_CNTL", REG_MMIO, 0x2720, 2, &mmDP6_DP_DPHY_CRC_CNTL[0], sizeof(mmDP6_DP_DPHY_CRC_CNTL)/sizeof(mmDP6_DP_DPHY_CRC_CNTL[0]), 0, 0 }, + { "mmDP6_DP_DPHY_CRC_RESULT", REG_MMIO, 0x2721, 2, &mmDP6_DP_DPHY_CRC_RESULT[0], sizeof(mmDP6_DP_DPHY_CRC_RESULT)/sizeof(mmDP6_DP_DPHY_CRC_RESULT[0]), 0, 0 }, + { "mmDP6_DP_DPHY_CRC_MST_CNTL", REG_MMIO, 0x2722, 2, &mmDP6_DP_DPHY_CRC_MST_CNTL[0], sizeof(mmDP6_DP_DPHY_CRC_MST_CNTL)/sizeof(mmDP6_DP_DPHY_CRC_MST_CNTL[0]), 0, 0 }, + { "mmDP6_DP_DPHY_CRC_MST_STATUS", REG_MMIO, 0x2723, 2, &mmDP6_DP_DPHY_CRC_MST_STATUS[0], sizeof(mmDP6_DP_DPHY_CRC_MST_STATUS)/sizeof(mmDP6_DP_DPHY_CRC_MST_STATUS[0]), 0, 0 }, + { "mmDP6_DP_DPHY_FAST_TRAINING", REG_MMIO, 0x2724, 2, &mmDP6_DP_DPHY_FAST_TRAINING[0], sizeof(mmDP6_DP_DPHY_FAST_TRAINING)/sizeof(mmDP6_DP_DPHY_FAST_TRAINING[0]), 0, 0 }, + { "mmDP6_DP_DPHY_FAST_TRAINING_STATUS", REG_MMIO, 0x2725, 2, &mmDP6_DP_DPHY_FAST_TRAINING_STATUS[0], sizeof(mmDP6_DP_DPHY_FAST_TRAINING_STATUS)/sizeof(mmDP6_DP_DPHY_FAST_TRAINING_STATUS[0]), 0, 0 }, + { "mmDP6_DP_SEC_CNTL", REG_MMIO, 0x272b, 2, &mmDP6_DP_SEC_CNTL[0], sizeof(mmDP6_DP_SEC_CNTL)/sizeof(mmDP6_DP_SEC_CNTL[0]), 0, 0 }, + { "mmDP6_DP_SEC_CNTL1", REG_MMIO, 0x272c, 2, &mmDP6_DP_SEC_CNTL1[0], sizeof(mmDP6_DP_SEC_CNTL1)/sizeof(mmDP6_DP_SEC_CNTL1[0]), 0, 0 }, + { "mmDP6_DP_SEC_FRAMING1", REG_MMIO, 0x272d, 2, &mmDP6_DP_SEC_FRAMING1[0], sizeof(mmDP6_DP_SEC_FRAMING1)/sizeof(mmDP6_DP_SEC_FRAMING1[0]), 0, 0 }, + { "mmDP6_DP_SEC_FRAMING2", REG_MMIO, 0x272e, 2, &mmDP6_DP_SEC_FRAMING2[0], sizeof(mmDP6_DP_SEC_FRAMING2)/sizeof(mmDP6_DP_SEC_FRAMING2[0]), 0, 0 }, + { "mmDP6_DP_SEC_FRAMING3", REG_MMIO, 0x272f, 2, &mmDP6_DP_SEC_FRAMING3[0], sizeof(mmDP6_DP_SEC_FRAMING3)/sizeof(mmDP6_DP_SEC_FRAMING3[0]), 0, 0 }, + { "mmDP6_DP_SEC_FRAMING4", REG_MMIO, 0x2730, 2, &mmDP6_DP_SEC_FRAMING4[0], sizeof(mmDP6_DP_SEC_FRAMING4)/sizeof(mmDP6_DP_SEC_FRAMING4[0]), 0, 0 }, + { "mmDP6_DP_SEC_AUD_N", REG_MMIO, 0x2731, 2, &mmDP6_DP_SEC_AUD_N[0], sizeof(mmDP6_DP_SEC_AUD_N)/sizeof(mmDP6_DP_SEC_AUD_N[0]), 0, 0 }, + { "mmDP6_DP_SEC_AUD_N_READBACK", REG_MMIO, 0x2732, 2, &mmDP6_DP_SEC_AUD_N_READBACK[0], sizeof(mmDP6_DP_SEC_AUD_N_READBACK)/sizeof(mmDP6_DP_SEC_AUD_N_READBACK[0]), 0, 0 }, + { "mmDP6_DP_SEC_AUD_M", REG_MMIO, 0x2733, 2, &mmDP6_DP_SEC_AUD_M[0], sizeof(mmDP6_DP_SEC_AUD_M)/sizeof(mmDP6_DP_SEC_AUD_M[0]), 0, 0 }, + { "mmDP6_DP_SEC_AUD_M_READBACK", REG_MMIO, 0x2734, 2, &mmDP6_DP_SEC_AUD_M_READBACK[0], sizeof(mmDP6_DP_SEC_AUD_M_READBACK)/sizeof(mmDP6_DP_SEC_AUD_M_READBACK[0]), 0, 0 }, + { "mmDP6_DP_SEC_TIMESTAMP", REG_MMIO, 0x2735, 2, &mmDP6_DP_SEC_TIMESTAMP[0], sizeof(mmDP6_DP_SEC_TIMESTAMP)/sizeof(mmDP6_DP_SEC_TIMESTAMP[0]), 0, 0 }, + { "mmDP6_DP_SEC_PACKET_CNTL", REG_MMIO, 0x2736, 2, &mmDP6_DP_SEC_PACKET_CNTL[0], sizeof(mmDP6_DP_SEC_PACKET_CNTL)/sizeof(mmDP6_DP_SEC_PACKET_CNTL[0]), 0, 0 }, + { "mmDP6_DP_MSE_RATE_CNTL", REG_MMIO, 0x2737, 2, &mmDP6_DP_MSE_RATE_CNTL[0], sizeof(mmDP6_DP_MSE_RATE_CNTL)/sizeof(mmDP6_DP_MSE_RATE_CNTL[0]), 0, 0 }, + { "mmDP6_DP_MSE_RATE_UPDATE", REG_MMIO, 0x2739, 2, &mmDP6_DP_MSE_RATE_UPDATE[0], sizeof(mmDP6_DP_MSE_RATE_UPDATE)/sizeof(mmDP6_DP_MSE_RATE_UPDATE[0]), 0, 0 }, + { "mmDP6_DP_MSE_SAT0", REG_MMIO, 0x273a, 2, &mmDP6_DP_MSE_SAT0[0], sizeof(mmDP6_DP_MSE_SAT0)/sizeof(mmDP6_DP_MSE_SAT0[0]), 0, 0 }, + { "mmDP6_DP_MSE_SAT1", REG_MMIO, 0x273b, 2, &mmDP6_DP_MSE_SAT1[0], sizeof(mmDP6_DP_MSE_SAT1)/sizeof(mmDP6_DP_MSE_SAT1[0]), 0, 0 }, + { "mmDP6_DP_MSE_SAT2", REG_MMIO, 0x273c, 2, &mmDP6_DP_MSE_SAT2[0], sizeof(mmDP6_DP_MSE_SAT2)/sizeof(mmDP6_DP_MSE_SAT2[0]), 0, 0 }, + { "mmDP6_DP_MSE_SAT_UPDATE", REG_MMIO, 0x273d, 2, &mmDP6_DP_MSE_SAT_UPDATE[0], sizeof(mmDP6_DP_MSE_SAT_UPDATE)/sizeof(mmDP6_DP_MSE_SAT_UPDATE[0]), 0, 0 }, + { "mmDP6_DP_MSE_LINK_TIMING", REG_MMIO, 0x273e, 2, &mmDP6_DP_MSE_LINK_TIMING[0], sizeof(mmDP6_DP_MSE_LINK_TIMING)/sizeof(mmDP6_DP_MSE_LINK_TIMING[0]), 0, 0 }, + { "mmDP6_DP_MSE_MISC_CNTL", REG_MMIO, 0x273f, 2, &mmDP6_DP_MSE_MISC_CNTL[0], sizeof(mmDP6_DP_MSE_MISC_CNTL)/sizeof(mmDP6_DP_MSE_MISC_CNTL[0]), 0, 0 }, + { "mmDP6_DP_DPHY_BS_SR_SWAP_CNTL", REG_MMIO, 0x2744, 2, &mmDP6_DP_DPHY_BS_SR_SWAP_CNTL[0], sizeof(mmDP6_DP_DPHY_BS_SR_SWAP_CNTL)/sizeof(mmDP6_DP_DPHY_BS_SR_SWAP_CNTL[0]), 0, 0 }, + { "mmDP6_DP_DPHY_HBR2_PATTERN_CONTROL", REG_MMIO, 0x2745, 2, &mmDP6_DP_DPHY_HBR2_PATTERN_CONTROL[0], sizeof(mmDP6_DP_DPHY_HBR2_PATTERN_CONTROL)/sizeof(mmDP6_DP_DPHY_HBR2_PATTERN_CONTROL[0]), 0, 0 }, + { "mmDP6_DP_MSE_SAT0_STATUS", REG_MMIO, 0x2747, 2, &mmDP6_DP_MSE_SAT0_STATUS[0], sizeof(mmDP6_DP_MSE_SAT0_STATUS)/sizeof(mmDP6_DP_MSE_SAT0_STATUS[0]), 0, 0 }, + { "mmDP6_DP_MSE_SAT1_STATUS", REG_MMIO, 0x2748, 2, &mmDP6_DP_MSE_SAT1_STATUS[0], sizeof(mmDP6_DP_MSE_SAT1_STATUS)/sizeof(mmDP6_DP_MSE_SAT1_STATUS[0]), 0, 0 }, + { "mmDP6_DP_MSE_SAT2_STATUS", REG_MMIO, 0x2749, 2, &mmDP6_DP_MSE_SAT2_STATUS[0], sizeof(mmDP6_DP_MSE_SAT2_STATUS)/sizeof(mmDP6_DP_MSE_SAT2_STATUS[0]), 0, 0 }, + { "mmDP6_DP_MSA_TIMING_PARAM1", REG_MMIO, 0x274c, 2, &mmDP6_DP_MSA_TIMING_PARAM1[0], sizeof(mmDP6_DP_MSA_TIMING_PARAM1)/sizeof(mmDP6_DP_MSA_TIMING_PARAM1[0]), 0, 0 }, + { "mmDP6_DP_MSA_TIMING_PARAM2", REG_MMIO, 0x274d, 2, &mmDP6_DP_MSA_TIMING_PARAM2[0], sizeof(mmDP6_DP_MSA_TIMING_PARAM2)/sizeof(mmDP6_DP_MSA_TIMING_PARAM2[0]), 0, 0 }, + { "mmDP6_DP_MSA_TIMING_PARAM3", REG_MMIO, 0x274e, 2, &mmDP6_DP_MSA_TIMING_PARAM3[0], sizeof(mmDP6_DP_MSA_TIMING_PARAM3)/sizeof(mmDP6_DP_MSA_TIMING_PARAM3[0]), 0, 0 }, + { "mmDP6_DP_MSA_TIMING_PARAM4", REG_MMIO, 0x274f, 2, &mmDP6_DP_MSA_TIMING_PARAM4[0], sizeof(mmDP6_DP_MSA_TIMING_PARAM4)/sizeof(mmDP6_DP_MSA_TIMING_PARAM4[0]), 0, 0 }, + { "mmDP6_DP_MSO_CNTL", REG_MMIO, 0x2750, 2, &mmDP6_DP_MSO_CNTL[0], sizeof(mmDP6_DP_MSO_CNTL)/sizeof(mmDP6_DP_MSO_CNTL[0]), 0, 0 }, + { "mmDP6_DP_MSO_CNTL1", REG_MMIO, 0x2751, 2, &mmDP6_DP_MSO_CNTL1[0], sizeof(mmDP6_DP_MSO_CNTL1)/sizeof(mmDP6_DP_MSO_CNTL1[0]), 0, 0 }, + { "mmDP6_DP_DSC_CNTL", REG_MMIO, 0x2752, 2, &mmDP6_DP_DSC_CNTL[0], sizeof(mmDP6_DP_DSC_CNTL)/sizeof(mmDP6_DP_DSC_CNTL[0]), 0, 0 }, + { "mmDP6_DP_SEC_CNTL2", REG_MMIO, 0x2753, 2, &mmDP6_DP_SEC_CNTL2[0], sizeof(mmDP6_DP_SEC_CNTL2)/sizeof(mmDP6_DP_SEC_CNTL2[0]), 0, 0 }, + { "mmDP6_DP_SEC_CNTL3", REG_MMIO, 0x2754, 2, &mmDP6_DP_SEC_CNTL3[0], sizeof(mmDP6_DP_SEC_CNTL3)/sizeof(mmDP6_DP_SEC_CNTL3[0]), 0, 0 }, + { "mmDP6_DP_SEC_CNTL4", REG_MMIO, 0x2755, 2, &mmDP6_DP_SEC_CNTL4[0], sizeof(mmDP6_DP_SEC_CNTL4)/sizeof(mmDP6_DP_SEC_CNTL4[0]), 0, 0 }, + { "mmDP6_DP_SEC_CNTL5", REG_MMIO, 0x2756, 2, &mmDP6_DP_SEC_CNTL5[0], sizeof(mmDP6_DP_SEC_CNTL5)/sizeof(mmDP6_DP_SEC_CNTL5[0]), 0, 0 }, + { "mmDP6_DP_SEC_CNTL6", REG_MMIO, 0x2757, 2, &mmDP6_DP_SEC_CNTL6[0], sizeof(mmDP6_DP_SEC_CNTL6)/sizeof(mmDP6_DP_SEC_CNTL6[0]), 0, 0 }, + { "mmDP6_DP_SEC_CNTL7", REG_MMIO, 0x2758, 2, &mmDP6_DP_SEC_CNTL7[0], sizeof(mmDP6_DP_SEC_CNTL7)/sizeof(mmDP6_DP_SEC_CNTL7[0]), 0, 0 }, + { "mmDP6_DP_DB_CNTL", REG_MMIO, 0x2759, 2, &mmDP6_DP_DB_CNTL[0], sizeof(mmDP6_DP_DB_CNTL)/sizeof(mmDP6_DP_DB_CNTL[0]), 0, 0 }, + { "mmDP6_DP_MSA_VBID_MISC", REG_MMIO, 0x275a, 2, &mmDP6_DP_MSA_VBID_MISC[0], sizeof(mmDP6_DP_MSA_VBID_MISC)/sizeof(mmDP6_DP_MSA_VBID_MISC[0]), 0, 0 }, + { "mmDC_GENERICA", REG_MMIO, 0x2868, 2, &mmDC_GENERICA[0], sizeof(mmDC_GENERICA)/sizeof(mmDC_GENERICA[0]), 0, 0 }, + { "mmDC_GENERICB", REG_MMIO, 0x2869, 2, &mmDC_GENERICB[0], sizeof(mmDC_GENERICB)/sizeof(mmDC_GENERICB[0]), 0, 0 }, + { "mmDC_REF_CLK_CNTL", REG_MMIO, 0x286b, 2, &mmDC_REF_CLK_CNTL[0], sizeof(mmDC_REF_CLK_CNTL)/sizeof(mmDC_REF_CLK_CNTL[0]), 0, 0 }, + { "mmDC_GPIO_DEBUG", REG_MMIO, 0x286c, 2, &mmDC_GPIO_DEBUG[0], sizeof(mmDC_GPIO_DEBUG)/sizeof(mmDC_GPIO_DEBUG[0]), 0, 0 }, + { "mmUNIPHYA_LINK_CNTL", REG_MMIO, 0x286d, 2, &mmUNIPHYA_LINK_CNTL[0], sizeof(mmUNIPHYA_LINK_CNTL)/sizeof(mmUNIPHYA_LINK_CNTL[0]), 0, 0 }, + { "mmUNIPHYA_CHANNEL_XBAR_CNTL", REG_MMIO, 0x286e, 2, &mmUNIPHYA_CHANNEL_XBAR_CNTL[0], sizeof(mmUNIPHYA_CHANNEL_XBAR_CNTL)/sizeof(mmUNIPHYA_CHANNEL_XBAR_CNTL[0]), 0, 0 }, + { "mmUNIPHYB_LINK_CNTL", REG_MMIO, 0x286f, 2, &mmUNIPHYB_LINK_CNTL[0], sizeof(mmUNIPHYB_LINK_CNTL)/sizeof(mmUNIPHYB_LINK_CNTL[0]), 0, 0 }, + { "mmUNIPHYB_CHANNEL_XBAR_CNTL", REG_MMIO, 0x2870, 2, &mmUNIPHYB_CHANNEL_XBAR_CNTL[0], sizeof(mmUNIPHYB_CHANNEL_XBAR_CNTL)/sizeof(mmUNIPHYB_CHANNEL_XBAR_CNTL[0]), 0, 0 }, + { "mmUNIPHYC_LINK_CNTL", REG_MMIO, 0x2871, 2, &mmUNIPHYC_LINK_CNTL[0], sizeof(mmUNIPHYC_LINK_CNTL)/sizeof(mmUNIPHYC_LINK_CNTL[0]), 0, 0 }, + { "mmUNIPHYC_CHANNEL_XBAR_CNTL", REG_MMIO, 0x2872, 2, &mmUNIPHYC_CHANNEL_XBAR_CNTL[0], sizeof(mmUNIPHYC_CHANNEL_XBAR_CNTL)/sizeof(mmUNIPHYC_CHANNEL_XBAR_CNTL[0]), 0, 0 }, + { "mmUNIPHYD_LINK_CNTL", REG_MMIO, 0x2873, 2, &mmUNIPHYD_LINK_CNTL[0], sizeof(mmUNIPHYD_LINK_CNTL)/sizeof(mmUNIPHYD_LINK_CNTL[0]), 0, 0 }, + { "mmUNIPHYD_CHANNEL_XBAR_CNTL", REG_MMIO, 0x2874, 2, &mmUNIPHYD_CHANNEL_XBAR_CNTL[0], sizeof(mmUNIPHYD_CHANNEL_XBAR_CNTL)/sizeof(mmUNIPHYD_CHANNEL_XBAR_CNTL[0]), 0, 0 }, + { "mmUNIPHYE_LINK_CNTL", REG_MMIO, 0x2875, 2, &mmUNIPHYE_LINK_CNTL[0], sizeof(mmUNIPHYE_LINK_CNTL)/sizeof(mmUNIPHYE_LINK_CNTL[0]), 0, 0 }, + { "mmUNIPHYE_CHANNEL_XBAR_CNTL", REG_MMIO, 0x2876, 2, &mmUNIPHYE_CHANNEL_XBAR_CNTL[0], sizeof(mmUNIPHYE_CHANNEL_XBAR_CNTL)/sizeof(mmUNIPHYE_CHANNEL_XBAR_CNTL[0]), 0, 0 }, + { "mmUNIPHYF_LINK_CNTL", REG_MMIO, 0x2877, 2, &mmUNIPHYF_LINK_CNTL[0], sizeof(mmUNIPHYF_LINK_CNTL)/sizeof(mmUNIPHYF_LINK_CNTL[0]), 0, 0 }, + { "mmUNIPHYF_CHANNEL_XBAR_CNTL", REG_MMIO, 0x2878, 2, &mmUNIPHYF_CHANNEL_XBAR_CNTL[0], sizeof(mmUNIPHYF_CHANNEL_XBAR_CNTL)/sizeof(mmUNIPHYF_CHANNEL_XBAR_CNTL[0]), 0, 0 }, + { "mmUNIPHYG_LINK_CNTL", REG_MMIO, 0x2879, 2, &mmUNIPHYG_LINK_CNTL[0], sizeof(mmUNIPHYG_LINK_CNTL)/sizeof(mmUNIPHYG_LINK_CNTL[0]), 0, 0 }, + { "mmUNIPHYG_CHANNEL_XBAR_CNTL", REG_MMIO, 0x287a, 2, &mmUNIPHYG_CHANNEL_XBAR_CNTL[0], sizeof(mmUNIPHYG_CHANNEL_XBAR_CNTL)/sizeof(mmUNIPHYG_CHANNEL_XBAR_CNTL[0]), 0, 0 }, + { "mmDCIO_WRCMD_DELAY", REG_MMIO, 0x287e, 2, &mmDCIO_WRCMD_DELAY[0], sizeof(mmDCIO_WRCMD_DELAY)/sizeof(mmDCIO_WRCMD_DELAY[0]), 0, 0 }, + { "mmDC_DVODATA_CONFIG", REG_MMIO, 0x2882, 2, &mmDC_DVODATA_CONFIG[0], sizeof(mmDC_DVODATA_CONFIG)/sizeof(mmDC_DVODATA_CONFIG[0]), 0, 0 }, + { "mmLVTMA_PWRSEQ_CNTL", REG_MMIO, 0x2883, 2, &mmLVTMA_PWRSEQ_CNTL[0], sizeof(mmLVTMA_PWRSEQ_CNTL)/sizeof(mmLVTMA_PWRSEQ_CNTL[0]), 0, 0 }, + { "mmLVTMA_PWRSEQ_STATE", REG_MMIO, 0x2884, 2, &mmLVTMA_PWRSEQ_STATE[0], sizeof(mmLVTMA_PWRSEQ_STATE)/sizeof(mmLVTMA_PWRSEQ_STATE[0]), 0, 0 }, + { "mmLVTMA_PWRSEQ_REF_DIV", REG_MMIO, 0x2885, 2, &mmLVTMA_PWRSEQ_REF_DIV[0], sizeof(mmLVTMA_PWRSEQ_REF_DIV)/sizeof(mmLVTMA_PWRSEQ_REF_DIV[0]), 0, 0 }, + { "mmLVTMA_PWRSEQ_DELAY1", REG_MMIO, 0x2886, 2, &mmLVTMA_PWRSEQ_DELAY1[0], sizeof(mmLVTMA_PWRSEQ_DELAY1)/sizeof(mmLVTMA_PWRSEQ_DELAY1[0]), 0, 0 }, + { "mmLVTMA_PWRSEQ_DELAY2", REG_MMIO, 0x2887, 2, &mmLVTMA_PWRSEQ_DELAY2[0], sizeof(mmLVTMA_PWRSEQ_DELAY2)/sizeof(mmLVTMA_PWRSEQ_DELAY2[0]), 0, 0 }, + { "mmBL_PWM_CNTL", REG_MMIO, 0x2888, 2, &mmBL_PWM_CNTL[0], sizeof(mmBL_PWM_CNTL)/sizeof(mmBL_PWM_CNTL[0]), 0, 0 }, + { "mmBL_PWM_CNTL2", REG_MMIO, 0x2889, 2, &mmBL_PWM_CNTL2[0], sizeof(mmBL_PWM_CNTL2)/sizeof(mmBL_PWM_CNTL2[0]), 0, 0 }, + { "mmBL_PWM_PERIOD_CNTL", REG_MMIO, 0x288a, 2, &mmBL_PWM_PERIOD_CNTL[0], sizeof(mmBL_PWM_PERIOD_CNTL)/sizeof(mmBL_PWM_PERIOD_CNTL[0]), 0, 0 }, + { "mmBL_PWM_GRP1_REG_LOCK", REG_MMIO, 0x288b, 2, &mmBL_PWM_GRP1_REG_LOCK[0], sizeof(mmBL_PWM_GRP1_REG_LOCK)/sizeof(mmBL_PWM_GRP1_REG_LOCK[0]), 0, 0 }, + { "mmDCIO_GSL_GENLK_PAD_CNTL", REG_MMIO, 0x288c, 2, &mmDCIO_GSL_GENLK_PAD_CNTL[0], sizeof(mmDCIO_GSL_GENLK_PAD_CNTL)/sizeof(mmDCIO_GSL_GENLK_PAD_CNTL[0]), 0, 0 }, + { "mmDCIO_GSL_SWAPLOCK_PAD_CNTL", REG_MMIO, 0x288d, 2, &mmDCIO_GSL_SWAPLOCK_PAD_CNTL[0], sizeof(mmDCIO_GSL_SWAPLOCK_PAD_CNTL)/sizeof(mmDCIO_GSL_SWAPLOCK_PAD_CNTL[0]), 0, 0 }, + { "mmDCIO_CLOCK_CNTL", REG_MMIO, 0x2895, 2, &mmDCIO_CLOCK_CNTL[0], sizeof(mmDCIO_CLOCK_CNTL)/sizeof(mmDCIO_CLOCK_CNTL[0]), 0, 0 }, + { "mmDIO_OTG_EXT_VSYNC_CNTL", REG_MMIO, 0x2898, 2, &mmDIO_OTG_EXT_VSYNC_CNTL[0], sizeof(mmDIO_OTG_EXT_VSYNC_CNTL)/sizeof(mmDIO_OTG_EXT_VSYNC_CNTL[0]), 0, 0 }, + { "mmDCIO_SOFT_RESET", REG_MMIO, 0x289e, 2, &mmDCIO_SOFT_RESET[0], sizeof(mmDCIO_SOFT_RESET)/sizeof(mmDCIO_SOFT_RESET[0]), 0, 0 }, + { "mmDCIO_DPHY_SEL", REG_MMIO, 0x289f, 2, &mmDCIO_DPHY_SEL[0], sizeof(mmDCIO_DPHY_SEL)/sizeof(mmDCIO_DPHY_SEL[0]), 0, 0 }, + { "mmUNIPHY_IMPCAL_LINKA", REG_MMIO, 0x28a0, 2, &mmUNIPHY_IMPCAL_LINKA[0], sizeof(mmUNIPHY_IMPCAL_LINKA)/sizeof(mmUNIPHY_IMPCAL_LINKA[0]), 0, 0 }, + { "mmUNIPHY_IMPCAL_LINKB", REG_MMIO, 0x28a1, 2, &mmUNIPHY_IMPCAL_LINKB[0], sizeof(mmUNIPHY_IMPCAL_LINKB)/sizeof(mmUNIPHY_IMPCAL_LINKB[0]), 0, 0 }, + { "mmUNIPHY_IMPCAL_PERIOD", REG_MMIO, 0x28a2, 2, &mmUNIPHY_IMPCAL_PERIOD[0], sizeof(mmUNIPHY_IMPCAL_PERIOD)/sizeof(mmUNIPHY_IMPCAL_PERIOD[0]), 0, 0 }, + { "mmAUXP_IMPCAL", REG_MMIO, 0x28a3, 2, &mmAUXP_IMPCAL[0], sizeof(mmAUXP_IMPCAL)/sizeof(mmAUXP_IMPCAL[0]), 0, 0 }, + { "mmAUXN_IMPCAL", REG_MMIO, 0x28a4, 2, &mmAUXN_IMPCAL[0], sizeof(mmAUXN_IMPCAL)/sizeof(mmAUXN_IMPCAL[0]), 0, 0 }, + { "mmDCIO_IMPCAL_CNTL", REG_MMIO, 0x28a5, 2, &mmDCIO_IMPCAL_CNTL[0], sizeof(mmDCIO_IMPCAL_CNTL)/sizeof(mmDCIO_IMPCAL_CNTL[0]), 0, 0 }, + { "mmUNIPHY_IMPCAL_PSW_AB", REG_MMIO, 0x28a6, 2, &mmUNIPHY_IMPCAL_PSW_AB[0], sizeof(mmUNIPHY_IMPCAL_PSW_AB)/sizeof(mmUNIPHY_IMPCAL_PSW_AB[0]), 0, 0 }, + { "mmUNIPHY_IMPCAL_LINKC", REG_MMIO, 0x28a7, 2, &mmUNIPHY_IMPCAL_LINKC[0], sizeof(mmUNIPHY_IMPCAL_LINKC)/sizeof(mmUNIPHY_IMPCAL_LINKC[0]), 0, 0 }, + { "mmUNIPHY_IMPCAL_LINKD", REG_MMIO, 0x28a8, 2, &mmUNIPHY_IMPCAL_LINKD[0], sizeof(mmUNIPHY_IMPCAL_LINKD)/sizeof(mmUNIPHY_IMPCAL_LINKD[0]), 0, 0 }, + { "mmDCIO_IMPCAL_CNTL_CD", REG_MMIO, 0x28a9, 2, &mmDCIO_IMPCAL_CNTL_CD[0], sizeof(mmDCIO_IMPCAL_CNTL_CD)/sizeof(mmDCIO_IMPCAL_CNTL_CD[0]), 0, 0 }, + { "mmUNIPHY_IMPCAL_PSW_CD", REG_MMIO, 0x28aa, 2, &mmUNIPHY_IMPCAL_PSW_CD[0], sizeof(mmUNIPHY_IMPCAL_PSW_CD)/sizeof(mmUNIPHY_IMPCAL_PSW_CD[0]), 0, 0 }, + { "mmUNIPHY_IMPCAL_LINKE", REG_MMIO, 0x28ab, 2, &mmUNIPHY_IMPCAL_LINKE[0], sizeof(mmUNIPHY_IMPCAL_LINKE)/sizeof(mmUNIPHY_IMPCAL_LINKE[0]), 0, 0 }, + { "mmUNIPHY_IMPCAL_LINKF", REG_MMIO, 0x28ac, 2, &mmUNIPHY_IMPCAL_LINKF[0], sizeof(mmUNIPHY_IMPCAL_LINKF)/sizeof(mmUNIPHY_IMPCAL_LINKF[0]), 0, 0 }, + { "mmDCIO_IMPCAL_CNTL_EF", REG_MMIO, 0x28ad, 2, &mmDCIO_IMPCAL_CNTL_EF[0], sizeof(mmDCIO_IMPCAL_CNTL_EF)/sizeof(mmDCIO_IMPCAL_CNTL_EF[0]), 0, 0 }, + { "mmUNIPHY_IMPCAL_PSW_EF", REG_MMIO, 0x28ae, 2, &mmUNIPHY_IMPCAL_PSW_EF[0], sizeof(mmUNIPHY_IMPCAL_PSW_EF)/sizeof(mmUNIPHY_IMPCAL_PSW_EF[0]), 0, 0 }, + { "mmDCIO_DPCS_TX_INTERRUPT", REG_MMIO, 0x28b3, 2, &mmDCIO_DPCS_TX_INTERRUPT[0], sizeof(mmDCIO_DPCS_TX_INTERRUPT)/sizeof(mmDCIO_DPCS_TX_INTERRUPT[0]), 0, 0 }, + { "mmDCIO_DPCS_RX_INTERRUPT", REG_MMIO, 0x28b4, 2, &mmDCIO_DPCS_RX_INTERRUPT[0], sizeof(mmDCIO_DPCS_RX_INTERRUPT)/sizeof(mmDCIO_DPCS_RX_INTERRUPT[0]), 0, 0 }, + { "mmDCIO_SEMAPHORE0", REG_MMIO, 0x28b5, 2, &mmDCIO_SEMAPHORE0[0], sizeof(mmDCIO_SEMAPHORE0)/sizeof(mmDCIO_SEMAPHORE0[0]), 0, 0 }, + { "mmDCIO_SEMAPHORE1", REG_MMIO, 0x28b6, 2, &mmDCIO_SEMAPHORE1[0], sizeof(mmDCIO_SEMAPHORE1)/sizeof(mmDCIO_SEMAPHORE1[0]), 0, 0 }, + { "mmDCIO_SEMAPHORE2", REG_MMIO, 0x28b7, 2, &mmDCIO_SEMAPHORE2[0], sizeof(mmDCIO_SEMAPHORE2)/sizeof(mmDCIO_SEMAPHORE2[0]), 0, 0 }, + { "mmDCIO_SEMAPHORE3", REG_MMIO, 0x28b8, 2, &mmDCIO_SEMAPHORE3[0], sizeof(mmDCIO_SEMAPHORE3)/sizeof(mmDCIO_SEMAPHORE3[0]), 0, 0 }, + { "mmDCIO_SEMAPHORE4", REG_MMIO, 0x28b9, 2, &mmDCIO_SEMAPHORE4[0], sizeof(mmDCIO_SEMAPHORE4)/sizeof(mmDCIO_SEMAPHORE4[0]), 0, 0 }, + { "mmDCIO_SEMAPHORE5", REG_MMIO, 0x28ba, 2, &mmDCIO_SEMAPHORE5[0], sizeof(mmDCIO_SEMAPHORE5)/sizeof(mmDCIO_SEMAPHORE5[0]), 0, 0 }, + { "mmDCIO_SEMAPHORE6", REG_MMIO, 0x28bb, 2, &mmDCIO_SEMAPHORE6[0], sizeof(mmDCIO_SEMAPHORE6)/sizeof(mmDCIO_SEMAPHORE6[0]), 0, 0 }, + { "mmDCIO_SEMAPHORE7", REG_MMIO, 0x28bc, 2, &mmDCIO_SEMAPHORE7[0], sizeof(mmDCIO_SEMAPHORE7)/sizeof(mmDCIO_SEMAPHORE7[0]), 0, 0 }, + { "mmDCIO_USBC_FLIP_EN_SEL", REG_MMIO, 0x28bd, 2, &mmDCIO_USBC_FLIP_EN_SEL[0], sizeof(mmDCIO_USBC_FLIP_EN_SEL)/sizeof(mmDCIO_USBC_FLIP_EN_SEL[0]), 0, 0 }, + { "mmDC_GPIO_GENERIC_MASK", REG_MMIO, 0x28c8, 2, &mmDC_GPIO_GENERIC_MASK[0], sizeof(mmDC_GPIO_GENERIC_MASK)/sizeof(mmDC_GPIO_GENERIC_MASK[0]), 0, 0 }, + { "mmDC_GPIO_GENERIC_A", REG_MMIO, 0x28c9, 2, &mmDC_GPIO_GENERIC_A[0], sizeof(mmDC_GPIO_GENERIC_A)/sizeof(mmDC_GPIO_GENERIC_A[0]), 0, 0 }, + { "mmDC_GPIO_GENERIC_EN", REG_MMIO, 0x28ca, 2, &mmDC_GPIO_GENERIC_EN[0], sizeof(mmDC_GPIO_GENERIC_EN)/sizeof(mmDC_GPIO_GENERIC_EN[0]), 0, 0 }, + { "mmDC_GPIO_GENERIC_Y", REG_MMIO, 0x28cb, 2, &mmDC_GPIO_GENERIC_Y[0], sizeof(mmDC_GPIO_GENERIC_Y)/sizeof(mmDC_GPIO_GENERIC_Y[0]), 0, 0 }, + { "mmDC_GPIO_DVODATA_MASK", REG_MMIO, 0x28cc, 2, &mmDC_GPIO_DVODATA_MASK[0], sizeof(mmDC_GPIO_DVODATA_MASK)/sizeof(mmDC_GPIO_DVODATA_MASK[0]), 0, 0 }, + { "mmDC_GPIO_DVODATA_A", REG_MMIO, 0x28cd, 2, &mmDC_GPIO_DVODATA_A[0], sizeof(mmDC_GPIO_DVODATA_A)/sizeof(mmDC_GPIO_DVODATA_A[0]), 0, 0 }, + { "mmDC_GPIO_DVODATA_EN", REG_MMIO, 0x28ce, 2, &mmDC_GPIO_DVODATA_EN[0], sizeof(mmDC_GPIO_DVODATA_EN)/sizeof(mmDC_GPIO_DVODATA_EN[0]), 0, 0 }, + { "mmDC_GPIO_DVODATA_Y", REG_MMIO, 0x28cf, 2, &mmDC_GPIO_DVODATA_Y[0], sizeof(mmDC_GPIO_DVODATA_Y)/sizeof(mmDC_GPIO_DVODATA_Y[0]), 0, 0 }, + { "mmDC_GPIO_DDC1_MASK", REG_MMIO, 0x28d0, 2, &mmDC_GPIO_DDC1_MASK[0], sizeof(mmDC_GPIO_DDC1_MASK)/sizeof(mmDC_GPIO_DDC1_MASK[0]), 0, 0 }, + { "mmDC_GPIO_DDC1_A", REG_MMIO, 0x28d1, 2, &mmDC_GPIO_DDC1_A[0], sizeof(mmDC_GPIO_DDC1_A)/sizeof(mmDC_GPIO_DDC1_A[0]), 0, 0 }, + { "mmDC_GPIO_DDC1_EN", REG_MMIO, 0x28d2, 2, &mmDC_GPIO_DDC1_EN[0], sizeof(mmDC_GPIO_DDC1_EN)/sizeof(mmDC_GPIO_DDC1_EN[0]), 0, 0 }, + { "mmDC_GPIO_DDC1_Y", REG_MMIO, 0x28d3, 2, &mmDC_GPIO_DDC1_Y[0], sizeof(mmDC_GPIO_DDC1_Y)/sizeof(mmDC_GPIO_DDC1_Y[0]), 0, 0 }, + { "mmDC_GPIO_DDC2_MASK", REG_MMIO, 0x28d4, 2, &mmDC_GPIO_DDC2_MASK[0], sizeof(mmDC_GPIO_DDC2_MASK)/sizeof(mmDC_GPIO_DDC2_MASK[0]), 0, 0 }, + { "mmDC_GPIO_DDC2_A", REG_MMIO, 0x28d5, 2, &mmDC_GPIO_DDC2_A[0], sizeof(mmDC_GPIO_DDC2_A)/sizeof(mmDC_GPIO_DDC2_A[0]), 0, 0 }, + { "mmDC_GPIO_DDC2_EN", REG_MMIO, 0x28d6, 2, &mmDC_GPIO_DDC2_EN[0], sizeof(mmDC_GPIO_DDC2_EN)/sizeof(mmDC_GPIO_DDC2_EN[0]), 0, 0 }, + { "mmDC_GPIO_DDC2_Y", REG_MMIO, 0x28d7, 2, &mmDC_GPIO_DDC2_Y[0], sizeof(mmDC_GPIO_DDC2_Y)/sizeof(mmDC_GPIO_DDC2_Y[0]), 0, 0 }, + { "mmDC_GPIO_DDC3_MASK", REG_MMIO, 0x28d8, 2, &mmDC_GPIO_DDC3_MASK[0], sizeof(mmDC_GPIO_DDC3_MASK)/sizeof(mmDC_GPIO_DDC3_MASK[0]), 0, 0 }, + { "mmDC_GPIO_DDC3_A", REG_MMIO, 0x28d9, 2, &mmDC_GPIO_DDC3_A[0], sizeof(mmDC_GPIO_DDC3_A)/sizeof(mmDC_GPIO_DDC3_A[0]), 0, 0 }, + { "mmDC_GPIO_DDC3_EN", REG_MMIO, 0x28da, 2, &mmDC_GPIO_DDC3_EN[0], sizeof(mmDC_GPIO_DDC3_EN)/sizeof(mmDC_GPIO_DDC3_EN[0]), 0, 0 }, + { "mmDC_GPIO_DDC3_Y", REG_MMIO, 0x28db, 2, &mmDC_GPIO_DDC3_Y[0], sizeof(mmDC_GPIO_DDC3_Y)/sizeof(mmDC_GPIO_DDC3_Y[0]), 0, 0 }, + { "mmDC_GPIO_DDC4_MASK", REG_MMIO, 0x28dc, 2, &mmDC_GPIO_DDC4_MASK[0], sizeof(mmDC_GPIO_DDC4_MASK)/sizeof(mmDC_GPIO_DDC4_MASK[0]), 0, 0 }, + { "mmDC_GPIO_DDC4_A", REG_MMIO, 0x28dd, 2, &mmDC_GPIO_DDC4_A[0], sizeof(mmDC_GPIO_DDC4_A)/sizeof(mmDC_GPIO_DDC4_A[0]), 0, 0 }, + { "mmDC_GPIO_DDC4_EN", REG_MMIO, 0x28de, 2, &mmDC_GPIO_DDC4_EN[0], sizeof(mmDC_GPIO_DDC4_EN)/sizeof(mmDC_GPIO_DDC4_EN[0]), 0, 0 }, + { "mmDC_GPIO_DDC4_Y", REG_MMIO, 0x28df, 2, &mmDC_GPIO_DDC4_Y[0], sizeof(mmDC_GPIO_DDC4_Y)/sizeof(mmDC_GPIO_DDC4_Y[0]), 0, 0 }, + { "mmDC_GPIO_DDC5_MASK", REG_MMIO, 0x28e0, 2, &mmDC_GPIO_DDC5_MASK[0], sizeof(mmDC_GPIO_DDC5_MASK)/sizeof(mmDC_GPIO_DDC5_MASK[0]), 0, 0 }, + { "mmDC_GPIO_DDC5_A", REG_MMIO, 0x28e1, 2, &mmDC_GPIO_DDC5_A[0], sizeof(mmDC_GPIO_DDC5_A)/sizeof(mmDC_GPIO_DDC5_A[0]), 0, 0 }, + { "mmDC_GPIO_DDC5_EN", REG_MMIO, 0x28e2, 2, &mmDC_GPIO_DDC5_EN[0], sizeof(mmDC_GPIO_DDC5_EN)/sizeof(mmDC_GPIO_DDC5_EN[0]), 0, 0 }, + { "mmDC_GPIO_DDC5_Y", REG_MMIO, 0x28e3, 2, &mmDC_GPIO_DDC5_Y[0], sizeof(mmDC_GPIO_DDC5_Y)/sizeof(mmDC_GPIO_DDC5_Y[0]), 0, 0 }, + { "mmDC_GPIO_DDC6_MASK", REG_MMIO, 0x28e4, 2, &mmDC_GPIO_DDC6_MASK[0], sizeof(mmDC_GPIO_DDC6_MASK)/sizeof(mmDC_GPIO_DDC6_MASK[0]), 0, 0 }, + { "mmDC_GPIO_DDC6_A", REG_MMIO, 0x28e5, 2, &mmDC_GPIO_DDC6_A[0], sizeof(mmDC_GPIO_DDC6_A)/sizeof(mmDC_GPIO_DDC6_A[0]), 0, 0 }, + { "mmDC_GPIO_DDC6_EN", REG_MMIO, 0x28e6, 2, &mmDC_GPIO_DDC6_EN[0], sizeof(mmDC_GPIO_DDC6_EN)/sizeof(mmDC_GPIO_DDC6_EN[0]), 0, 0 }, + { "mmDC_GPIO_DDC6_Y", REG_MMIO, 0x28e7, 2, &mmDC_GPIO_DDC6_Y[0], sizeof(mmDC_GPIO_DDC6_Y)/sizeof(mmDC_GPIO_DDC6_Y[0]), 0, 0 }, + { "mmDC_GPIO_DDCVGA_MASK", REG_MMIO, 0x28e8, 2, &mmDC_GPIO_DDCVGA_MASK[0], sizeof(mmDC_GPIO_DDCVGA_MASK)/sizeof(mmDC_GPIO_DDCVGA_MASK[0]), 0, 0 }, + { "mmDC_GPIO_DDCVGA_A", REG_MMIO, 0x28e9, 2, &mmDC_GPIO_DDCVGA_A[0], sizeof(mmDC_GPIO_DDCVGA_A)/sizeof(mmDC_GPIO_DDCVGA_A[0]), 0, 0 }, + { "mmDC_GPIO_DDCVGA_EN", REG_MMIO, 0x28ea, 2, &mmDC_GPIO_DDCVGA_EN[0], sizeof(mmDC_GPIO_DDCVGA_EN)/sizeof(mmDC_GPIO_DDCVGA_EN[0]), 0, 0 }, + { "mmDC_GPIO_DDCVGA_Y", REG_MMIO, 0x28eb, 2, &mmDC_GPIO_DDCVGA_Y[0], sizeof(mmDC_GPIO_DDCVGA_Y)/sizeof(mmDC_GPIO_DDCVGA_Y[0]), 0, 0 }, + { "mmDC_GPIO_SYNCA_MASK", REG_MMIO, 0x28ec, 2, &mmDC_GPIO_SYNCA_MASK[0], sizeof(mmDC_GPIO_SYNCA_MASK)/sizeof(mmDC_GPIO_SYNCA_MASK[0]), 0, 0 }, + { "mmDC_GPIO_SYNCA_A", REG_MMIO, 0x28ed, 2, &mmDC_GPIO_SYNCA_A[0], sizeof(mmDC_GPIO_SYNCA_A)/sizeof(mmDC_GPIO_SYNCA_A[0]), 0, 0 }, + { "mmDC_GPIO_SYNCA_EN", REG_MMIO, 0x28ee, 2, &mmDC_GPIO_SYNCA_EN[0], sizeof(mmDC_GPIO_SYNCA_EN)/sizeof(mmDC_GPIO_SYNCA_EN[0]), 0, 0 }, + { "mmDC_GPIO_SYNCA_Y", REG_MMIO, 0x28ef, 2, &mmDC_GPIO_SYNCA_Y[0], sizeof(mmDC_GPIO_SYNCA_Y)/sizeof(mmDC_GPIO_SYNCA_Y[0]), 0, 0 }, + { "mmDC_GPIO_GENLK_MASK", REG_MMIO, 0x28f0, 2, &mmDC_GPIO_GENLK_MASK[0], sizeof(mmDC_GPIO_GENLK_MASK)/sizeof(mmDC_GPIO_GENLK_MASK[0]), 0, 0 }, + { "mmDC_GPIO_GENLK_A", REG_MMIO, 0x28f1, 2, &mmDC_GPIO_GENLK_A[0], sizeof(mmDC_GPIO_GENLK_A)/sizeof(mmDC_GPIO_GENLK_A[0]), 0, 0 }, + { "mmDC_GPIO_GENLK_EN", REG_MMIO, 0x28f2, 2, &mmDC_GPIO_GENLK_EN[0], sizeof(mmDC_GPIO_GENLK_EN)/sizeof(mmDC_GPIO_GENLK_EN[0]), 0, 0 }, + { "mmDC_GPIO_GENLK_Y", REG_MMIO, 0x28f3, 2, &mmDC_GPIO_GENLK_Y[0], sizeof(mmDC_GPIO_GENLK_Y)/sizeof(mmDC_GPIO_GENLK_Y[0]), 0, 0 }, + { "mmDC_GPIO_HPD_MASK", REG_MMIO, 0x28f4, 2, &mmDC_GPIO_HPD_MASK[0], sizeof(mmDC_GPIO_HPD_MASK)/sizeof(mmDC_GPIO_HPD_MASK[0]), 0, 0 }, + { "mmDC_GPIO_HPD_A", REG_MMIO, 0x28f5, 2, &mmDC_GPIO_HPD_A[0], sizeof(mmDC_GPIO_HPD_A)/sizeof(mmDC_GPIO_HPD_A[0]), 0, 0 }, + { "mmDC_GPIO_HPD_EN", REG_MMIO, 0x28f6, 2, &mmDC_GPIO_HPD_EN[0], sizeof(mmDC_GPIO_HPD_EN)/sizeof(mmDC_GPIO_HPD_EN[0]), 0, 0 }, + { "mmDC_GPIO_HPD_Y", REG_MMIO, 0x28f7, 2, &mmDC_GPIO_HPD_Y[0], sizeof(mmDC_GPIO_HPD_Y)/sizeof(mmDC_GPIO_HPD_Y[0]), 0, 0 }, + { "mmDC_GPIO_PWRSEQ_MASK", REG_MMIO, 0x28f8, 2, &mmDC_GPIO_PWRSEQ_MASK[0], sizeof(mmDC_GPIO_PWRSEQ_MASK)/sizeof(mmDC_GPIO_PWRSEQ_MASK[0]), 0, 0 }, + { "mmDC_GPIO_PWRSEQ_A", REG_MMIO, 0x28f9, 2, &mmDC_GPIO_PWRSEQ_A[0], sizeof(mmDC_GPIO_PWRSEQ_A)/sizeof(mmDC_GPIO_PWRSEQ_A[0]), 0, 0 }, + { "mmDC_GPIO_PWRSEQ_EN", REG_MMIO, 0x28fa, 2, &mmDC_GPIO_PWRSEQ_EN[0], sizeof(mmDC_GPIO_PWRSEQ_EN)/sizeof(mmDC_GPIO_PWRSEQ_EN[0]), 0, 0 }, + { "mmDC_GPIO_PWRSEQ_Y", REG_MMIO, 0x28fb, 2, &mmDC_GPIO_PWRSEQ_Y[0], sizeof(mmDC_GPIO_PWRSEQ_Y)/sizeof(mmDC_GPIO_PWRSEQ_Y[0]), 0, 0 }, + { "mmDC_GPIO_PAD_STRENGTH_1", REG_MMIO, 0x28fc, 2, &mmDC_GPIO_PAD_STRENGTH_1[0], sizeof(mmDC_GPIO_PAD_STRENGTH_1)/sizeof(mmDC_GPIO_PAD_STRENGTH_1[0]), 0, 0 }, + { "mmDC_GPIO_PAD_STRENGTH_2", REG_MMIO, 0x28fd, 2, &mmDC_GPIO_PAD_STRENGTH_2[0], sizeof(mmDC_GPIO_PAD_STRENGTH_2)/sizeof(mmDC_GPIO_PAD_STRENGTH_2[0]), 0, 0 }, + { "mmPHY_AUX_CNTL", REG_MMIO, 0x28ff, 2, &mmPHY_AUX_CNTL[0], sizeof(mmPHY_AUX_CNTL)/sizeof(mmPHY_AUX_CNTL[0]), 0, 0 }, + { "mmDC_GPIO_I2CPAD_MASK", REG_MMIO, 0x2900, 2, &mmDC_GPIO_I2CPAD_MASK[0], sizeof(mmDC_GPIO_I2CPAD_MASK)/sizeof(mmDC_GPIO_I2CPAD_MASK[0]), 0, 0 }, + { "mmDC_GPIO_I2CPAD_A", REG_MMIO, 0x2901, 2, &mmDC_GPIO_I2CPAD_A[0], sizeof(mmDC_GPIO_I2CPAD_A)/sizeof(mmDC_GPIO_I2CPAD_A[0]), 0, 0 }, + { "mmDC_GPIO_I2CPAD_EN", REG_MMIO, 0x2902, 2, &mmDC_GPIO_I2CPAD_EN[0], sizeof(mmDC_GPIO_I2CPAD_EN)/sizeof(mmDC_GPIO_I2CPAD_EN[0]), 0, 0 }, + { "mmDC_GPIO_I2CPAD_Y", REG_MMIO, 0x2903, 2, &mmDC_GPIO_I2CPAD_Y[0], sizeof(mmDC_GPIO_I2CPAD_Y)/sizeof(mmDC_GPIO_I2CPAD_Y[0]), 0, 0 }, + { "mmDC_GPIO_I2CPAD_STRENGTH", REG_MMIO, 0x2904, 2, &mmDC_GPIO_I2CPAD_STRENGTH[0], sizeof(mmDC_GPIO_I2CPAD_STRENGTH)/sizeof(mmDC_GPIO_I2CPAD_STRENGTH[0]), 0, 0 }, + { "mmDVO_STRENGTH_CONTROL", REG_MMIO, 0x2905, 2, &mmDVO_STRENGTH_CONTROL[0], sizeof(mmDVO_STRENGTH_CONTROL)/sizeof(mmDVO_STRENGTH_CONTROL[0]), 0, 0 }, + { "mmDVO_VREF_CONTROL", REG_MMIO, 0x2906, 2, &mmDVO_VREF_CONTROL[0], sizeof(mmDVO_VREF_CONTROL)/sizeof(mmDVO_VREF_CONTROL[0]), 0, 0 }, + { "mmDVO_SKEW_ADJUST", REG_MMIO, 0x2907, 2, &mmDVO_SKEW_ADJUST[0], sizeof(mmDVO_SKEW_ADJUST)/sizeof(mmDVO_SKEW_ADJUST[0]), 0, 0 }, + { "mmDC_GPIO_I2S_SPDIF_MASK", REG_MMIO, 0x2910, 2, &mmDC_GPIO_I2S_SPDIF_MASK[0], sizeof(mmDC_GPIO_I2S_SPDIF_MASK)/sizeof(mmDC_GPIO_I2S_SPDIF_MASK[0]), 0, 0 }, + { "mmDC_GPIO_I2S_SPDIF_A", REG_MMIO, 0x2911, 2, &mmDC_GPIO_I2S_SPDIF_A[0], sizeof(mmDC_GPIO_I2S_SPDIF_A)/sizeof(mmDC_GPIO_I2S_SPDIF_A[0]), 0, 0 }, + { "mmDC_GPIO_I2S_SPDIF_EN", REG_MMIO, 0x2912, 2, &mmDC_GPIO_I2S_SPDIF_EN[0], sizeof(mmDC_GPIO_I2S_SPDIF_EN)/sizeof(mmDC_GPIO_I2S_SPDIF_EN[0]), 0, 0 }, + { "mmDC_GPIO_I2S_SPDIF_Y", REG_MMIO, 0x2913, 2, &mmDC_GPIO_I2S_SPDIF_Y[0], sizeof(mmDC_GPIO_I2S_SPDIF_Y)/sizeof(mmDC_GPIO_I2S_SPDIF_Y[0]), 0, 0 }, + { "mmDC_GPIO_I2S_SPDIF_STRENGTH", REG_MMIO, 0x2914, 2, &mmDC_GPIO_I2S_SPDIF_STRENGTH[0], sizeof(mmDC_GPIO_I2S_SPDIF_STRENGTH)/sizeof(mmDC_GPIO_I2S_SPDIF_STRENGTH[0]), 0, 0 }, + { "mmDC_GPIO_TX12_EN", REG_MMIO, 0x2915, 2, &mmDC_GPIO_TX12_EN[0], sizeof(mmDC_GPIO_TX12_EN)/sizeof(mmDC_GPIO_TX12_EN[0]), 0, 0 }, + { "mmDC_GPIO_AUX_CTRL_0", REG_MMIO, 0x2916, 2, &mmDC_GPIO_AUX_CTRL_0[0], sizeof(mmDC_GPIO_AUX_CTRL_0)/sizeof(mmDC_GPIO_AUX_CTRL_0[0]), 0, 0 }, + { "mmDC_GPIO_AUX_CTRL_1", REG_MMIO, 0x2917, 2, &mmDC_GPIO_AUX_CTRL_1[0], sizeof(mmDC_GPIO_AUX_CTRL_1)/sizeof(mmDC_GPIO_AUX_CTRL_1[0]), 0, 0 }, + { "mmDC_GPIO_AUX_CTRL_2", REG_MMIO, 0x2918, 2, &mmDC_GPIO_AUX_CTRL_2[0], sizeof(mmDC_GPIO_AUX_CTRL_2)/sizeof(mmDC_GPIO_AUX_CTRL_2[0]), 0, 0 }, + { "mmDC_GPIO_RXEN", REG_MMIO, 0x2919, 2, &mmDC_GPIO_RXEN[0], sizeof(mmDC_GPIO_RXEN)/sizeof(mmDC_GPIO_RXEN[0]), 0, 0 }, + { "mmDC_GPIO_PULLUPEN", REG_MMIO, 0x291a, 2, &mmDC_GPIO_PULLUPEN[0], sizeof(mmDC_GPIO_PULLUPEN)/sizeof(mmDC_GPIO_PULLUPEN[0]), 0, 0 }, + { "mmDAC_MACRO_CNTL_RESERVED0", REG_MMIO, 0x2920, 2, &mmDAC_MACRO_CNTL_RESERVED0[0], sizeof(mmDAC_MACRO_CNTL_RESERVED0)/sizeof(mmDAC_MACRO_CNTL_RESERVED0[0]), 0, 0 }, + { "mmDAC_MACRO_CNTL_RESERVED1", REG_MMIO, 0x2921, 2, &mmDAC_MACRO_CNTL_RESERVED1[0], sizeof(mmDAC_MACRO_CNTL_RESERVED1)/sizeof(mmDAC_MACRO_CNTL_RESERVED1[0]), 0, 0 }, + { "mmDAC_MACRO_CNTL_RESERVED2", REG_MMIO, 0x2922, 2, &mmDAC_MACRO_CNTL_RESERVED2[0], sizeof(mmDAC_MACRO_CNTL_RESERVED2)/sizeof(mmDAC_MACRO_CNTL_RESERVED2[0]), 0, 0 }, + { "mmDAC_MACRO_CNTL_RESERVED3", REG_MMIO, 0x2923, 2, &mmDAC_MACRO_CNTL_RESERVED3[0], sizeof(mmDAC_MACRO_CNTL_RESERVED3)/sizeof(mmDAC_MACRO_CNTL_RESERVED3[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0", REG_MMIO, 0x2928, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1", REG_MMIO, 0x2929, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2", REG_MMIO, 0x292a, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3", REG_MMIO, 0x292b, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4", REG_MMIO, 0x292c, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5", REG_MMIO, 0x292d, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6", REG_MMIO, 0x292e, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7", REG_MMIO, 0x292f, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8", REG_MMIO, 0x2930, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9", REG_MMIO, 0x2931, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10", REG_MMIO, 0x2932, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11", REG_MMIO, 0x2933, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12", REG_MMIO, 0x2934, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13", REG_MMIO, 0x2935, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14", REG_MMIO, 0x2936, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15", REG_MMIO, 0x2937, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16", REG_MMIO, 0x2938, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17", REG_MMIO, 0x2939, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18", REG_MMIO, 0x293a, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19", REG_MMIO, 0x293b, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20", REG_MMIO, 0x293c, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21", REG_MMIO, 0x293d, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22", REG_MMIO, 0x293e, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23", REG_MMIO, 0x293f, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24", REG_MMIO, 0x2940, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25", REG_MMIO, 0x2941, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26", REG_MMIO, 0x2942, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27", REG_MMIO, 0x2943, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28", REG_MMIO, 0x2944, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29", REG_MMIO, 0x2945, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30", REG_MMIO, 0x2946, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31", REG_MMIO, 0x2947, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32", REG_MMIO, 0x2948, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33", REG_MMIO, 0x2949, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34", REG_MMIO, 0x294a, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35", REG_MMIO, 0x294b, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36", REG_MMIO, 0x294c, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37", REG_MMIO, 0x294d, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38", REG_MMIO, 0x294e, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39", REG_MMIO, 0x294f, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40", REG_MMIO, 0x2950, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41", REG_MMIO, 0x2951, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42", REG_MMIO, 0x2952, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43", REG_MMIO, 0x2953, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44", REG_MMIO, 0x2954, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45", REG_MMIO, 0x2955, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46", REG_MMIO, 0x2956, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47", REG_MMIO, 0x2957, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48", REG_MMIO, 0x2958, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49", REG_MMIO, 0x2959, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50", REG_MMIO, 0x295a, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51", REG_MMIO, 0x295b, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52", REG_MMIO, 0x295c, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53", REG_MMIO, 0x295d, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54", REG_MMIO, 0x295e, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55", REG_MMIO, 0x295f, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56", REG_MMIO, 0x2960, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57", REG_MMIO, 0x2961, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58", REG_MMIO, 0x2962, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59", REG_MMIO, 0x2963, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60", REG_MMIO, 0x2964, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61", REG_MMIO, 0x2965, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62", REG_MMIO, 0x2966, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63", REG_MMIO, 0x2967, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64", REG_MMIO, 0x2968, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65", REG_MMIO, 0x2969, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66", REG_MMIO, 0x296a, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67", REG_MMIO, 0x296b, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68", REG_MMIO, 0x296c, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69", REG_MMIO, 0x296d, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70", REG_MMIO, 0x296e, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71", REG_MMIO, 0x296f, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72", REG_MMIO, 0x2970, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73", REG_MMIO, 0x2971, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74", REG_MMIO, 0x2972, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75", REG_MMIO, 0x2973, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76", REG_MMIO, 0x2974, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77", REG_MMIO, 0x2975, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78", REG_MMIO, 0x2976, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79", REG_MMIO, 0x2977, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80", REG_MMIO, 0x2978, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81", REG_MMIO, 0x2979, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82", REG_MMIO, 0x297a, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83", REG_MMIO, 0x297b, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84", REG_MMIO, 0x297c, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85", REG_MMIO, 0x297d, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86", REG_MMIO, 0x297e, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87", REG_MMIO, 0x297f, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88", REG_MMIO, 0x2980, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89", REG_MMIO, 0x2981, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90", REG_MMIO, 0x2982, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91", REG_MMIO, 0x2983, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92", REG_MMIO, 0x2984, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93", REG_MMIO, 0x2985, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94", REG_MMIO, 0x2986, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95", REG_MMIO, 0x2987, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96", REG_MMIO, 0x2988, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97", REG_MMIO, 0x2989, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98", REG_MMIO, 0x298a, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99", REG_MMIO, 0x298b, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100", REG_MMIO, 0x298c, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101", REG_MMIO, 0x298d, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102", REG_MMIO, 0x298e, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103", REG_MMIO, 0x298f, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104", REG_MMIO, 0x2990, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105", REG_MMIO, 0x2991, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106", REG_MMIO, 0x2992, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107", REG_MMIO, 0x2993, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108", REG_MMIO, 0x2994, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109", REG_MMIO, 0x2995, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110", REG_MMIO, 0x2996, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111", REG_MMIO, 0x2997, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112", REG_MMIO, 0x2998, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113", REG_MMIO, 0x2999, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114", REG_MMIO, 0x299a, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115", REG_MMIO, 0x299b, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116", REG_MMIO, 0x299c, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117", REG_MMIO, 0x299d, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118", REG_MMIO, 0x299e, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119", REG_MMIO, 0x299f, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120", REG_MMIO, 0x29a0, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121", REG_MMIO, 0x29a1, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122", REG_MMIO, 0x29a2, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123", REG_MMIO, 0x29a3, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124", REG_MMIO, 0x29a4, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125", REG_MMIO, 0x29a5, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126", REG_MMIO, 0x29a6, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127", REG_MMIO, 0x29a7, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128", REG_MMIO, 0x29a8, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129", REG_MMIO, 0x29a9, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130", REG_MMIO, 0x29aa, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131", REG_MMIO, 0x29ab, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132", REG_MMIO, 0x29ac, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133", REG_MMIO, 0x29ad, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134", REG_MMIO, 0x29ae, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135", REG_MMIO, 0x29af, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136", REG_MMIO, 0x29b0, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137", REG_MMIO, 0x29b1, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138", REG_MMIO, 0x29b2, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139", REG_MMIO, 0x29b3, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140", REG_MMIO, 0x29b4, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141", REG_MMIO, 0x29b5, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142", REG_MMIO, 0x29b6, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143", REG_MMIO, 0x29b7, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144", REG_MMIO, 0x29b8, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145", REG_MMIO, 0x29b9, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146", REG_MMIO, 0x29ba, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147", REG_MMIO, 0x29bb, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148", REG_MMIO, 0x29bc, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149", REG_MMIO, 0x29bd, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150", REG_MMIO, 0x29be, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151", REG_MMIO, 0x29bf, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152", REG_MMIO, 0x29c0, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153", REG_MMIO, 0x29c1, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154", REG_MMIO, 0x29c2, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155", REG_MMIO, 0x29c3, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156", REG_MMIO, 0x29c4, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157", REG_MMIO, 0x29c5, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158", REG_MMIO, 0x29c6, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158[0]), 0, 0 }, + { "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159", REG_MMIO, 0x29c7, 2, &mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159[0], sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159)/sizeof(mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159[0]), 0, 0 }, + { "mmDC_COMBOPHYCMREGS0_COMMON_FUSE1", REG_MMIO, 0x2928, 2, &mmDC_COMBOPHYCMREGS0_COMMON_FUSE1[0], sizeof(mmDC_COMBOPHYCMREGS0_COMMON_FUSE1)/sizeof(mmDC_COMBOPHYCMREGS0_COMMON_FUSE1[0]), 0, 0 }, + { "mmDC_COMBOPHYCMREGS0_COMMON_FUSE2", REG_MMIO, 0x2929, 2, &mmDC_COMBOPHYCMREGS0_COMMON_FUSE2[0], sizeof(mmDC_COMBOPHYCMREGS0_COMMON_FUSE2)/sizeof(mmDC_COMBOPHYCMREGS0_COMMON_FUSE2[0]), 0, 0 }, + { "mmDC_COMBOPHYCMREGS0_COMMON_FUSE3", REG_MMIO, 0x292a, 2, &mmDC_COMBOPHYCMREGS0_COMMON_FUSE3[0], sizeof(mmDC_COMBOPHYCMREGS0_COMMON_FUSE3)/sizeof(mmDC_COMBOPHYCMREGS0_COMMON_FUSE3[0]), 0, 0 }, + { "mmDC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM", REG_MMIO, 0x292b, 2, &mmDC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM[0], sizeof(mmDC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM)/sizeof(mmDC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM[0]), 0, 0 }, + { "mmDC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT", REG_MMIO, 0x292c, 2, &mmDC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT[0], sizeof(mmDC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT)/sizeof(mmDC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT[0]), 0, 0 }, + { "mmDC_COMBOPHYCMREGS0_COMMON_TXCNTRL", REG_MMIO, 0x292d, 2, &mmDC_COMBOPHYCMREGS0_COMMON_TXCNTRL[0], sizeof(mmDC_COMBOPHYCMREGS0_COMMON_TXCNTRL)/sizeof(mmDC_COMBOPHYCMREGS0_COMMON_TXCNTRL[0]), 0, 0 }, + { "mmDC_COMBOPHYCMREGS0_COMMON_TMDP", REG_MMIO, 0x292e, 2, &mmDC_COMBOPHYCMREGS0_COMMON_TMDP[0], sizeof(mmDC_COMBOPHYCMREGS0_COMMON_TMDP)/sizeof(mmDC_COMBOPHYCMREGS0_COMMON_TMDP[0]), 0, 0 }, + { "mmDC_COMBOPHYCMREGS0_COMMON_LANE_RESETS", REG_MMIO, 0x292f, 2, &mmDC_COMBOPHYCMREGS0_COMMON_LANE_RESETS[0], sizeof(mmDC_COMBOPHYCMREGS0_COMMON_LANE_RESETS)/sizeof(mmDC_COMBOPHYCMREGS0_COMMON_LANE_RESETS[0]), 0, 0 }, + { "mmDC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL", REG_MMIO, 0x2930, 2, &mmDC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL[0], sizeof(mmDC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL)/sizeof(mmDC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL[0]), 0, 0 }, + { "mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU1", REG_MMIO, 0x2931, 2, &mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU1[0], sizeof(mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU1)/sizeof(mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU1[0]), 0, 0 }, + { "mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU2", REG_MMIO, 0x2932, 2, &mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU2[0], sizeof(mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU2)/sizeof(mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU2[0]), 0, 0 }, + { "mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU3", REG_MMIO, 0x2933, 2, &mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU3[0], sizeof(mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU3)/sizeof(mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU3[0]), 0, 0 }, + { "mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU4", REG_MMIO, 0x2934, 2, &mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU4[0], sizeof(mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU4)/sizeof(mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU4[0]), 0, 0 }, + { "mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU5", REG_MMIO, 0x2935, 2, &mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU5[0], sizeof(mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU5)/sizeof(mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU5[0]), 0, 0 }, + { "mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU6", REG_MMIO, 0x2936, 2, &mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU6[0], sizeof(mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU6)/sizeof(mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU6[0]), 0, 0 }, + { "mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU7", REG_MMIO, 0x2937, 2, &mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU7[0], sizeof(mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU7)/sizeof(mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU7[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0", REG_MMIO, 0x2948, 2, &mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0[0], sizeof(mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0)/sizeof(mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0", REG_MMIO, 0x2949, 2, &mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0[0], sizeof(mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0)/sizeof(mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0", REG_MMIO, 0x294a, 2, &mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0[0], sizeof(mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0)/sizeof(mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0", REG_MMIO, 0x294b, 2, &mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0[0], sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0)/sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0", REG_MMIO, 0x294c, 2, &mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0[0], sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0)/sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0", REG_MMIO, 0x294d, 2, &mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0[0], sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0)/sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0", REG_MMIO, 0x294e, 2, &mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0[0], sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0)/sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0", REG_MMIO, 0x294f, 2, &mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0[0], sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0)/sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0", REG_MMIO, 0x2950, 2, &mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0[0], sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0)/sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0", REG_MMIO, 0x2951, 2, &mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0[0], sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0)/sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0", REG_MMIO, 0x2952, 2, &mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0[0], sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0)/sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0", REG_MMIO, 0x2953, 2, &mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0[0], sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0)/sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0", REG_MMIO, 0x2954, 2, &mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0[0], sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0)/sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0", REG_MMIO, 0x2955, 2, &mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0[0], sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0)/sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0", REG_MMIO, 0x2956, 2, &mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0[0], sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0)/sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0", REG_MMIO, 0x2957, 2, &mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0[0], sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0)/sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1", REG_MMIO, 0x2958, 2, &mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1[0], sizeof(mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1)/sizeof(mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1", REG_MMIO, 0x2959, 2, &mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1[0], sizeof(mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1)/sizeof(mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1", REG_MMIO, 0x295a, 2, &mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1[0], sizeof(mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1)/sizeof(mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1", REG_MMIO, 0x295b, 2, &mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1[0], sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1)/sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1", REG_MMIO, 0x295c, 2, &mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1[0], sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1)/sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1", REG_MMIO, 0x295d, 2, &mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1[0], sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1)/sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1", REG_MMIO, 0x295e, 2, &mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1[0], sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1)/sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1", REG_MMIO, 0x295f, 2, &mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1[0], sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1)/sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1", REG_MMIO, 0x2960, 2, &mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1[0], sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1)/sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1", REG_MMIO, 0x2961, 2, &mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1[0], sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1)/sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1", REG_MMIO, 0x2962, 2, &mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1[0], sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1)/sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1", REG_MMIO, 0x2963, 2, &mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1[0], sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1)/sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1", REG_MMIO, 0x2964, 2, &mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1[0], sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1)/sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1", REG_MMIO, 0x2965, 2, &mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1[0], sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1)/sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1", REG_MMIO, 0x2966, 2, &mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1[0], sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1)/sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1", REG_MMIO, 0x2967, 2, &mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1[0], sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1)/sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2", REG_MMIO, 0x2968, 2, &mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2[0], sizeof(mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2)/sizeof(mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2", REG_MMIO, 0x2969, 2, &mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2[0], sizeof(mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2)/sizeof(mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2", REG_MMIO, 0x296a, 2, &mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2[0], sizeof(mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2)/sizeof(mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2", REG_MMIO, 0x296b, 2, &mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2[0], sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2)/sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2", REG_MMIO, 0x296c, 2, &mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2[0], sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2)/sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2", REG_MMIO, 0x296d, 2, &mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2[0], sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2)/sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2", REG_MMIO, 0x296e, 2, &mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2[0], sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2)/sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2", REG_MMIO, 0x296f, 2, &mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2[0], sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2)/sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2", REG_MMIO, 0x2970, 2, &mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2[0], sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2)/sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2", REG_MMIO, 0x2971, 2, &mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2[0], sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2)/sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2", REG_MMIO, 0x2972, 2, &mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2[0], sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2)/sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2", REG_MMIO, 0x2973, 2, &mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2[0], sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2)/sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2", REG_MMIO, 0x2974, 2, &mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2[0], sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2)/sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2", REG_MMIO, 0x2975, 2, &mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2[0], sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2)/sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2", REG_MMIO, 0x2976, 2, &mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2[0], sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2)/sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2", REG_MMIO, 0x2977, 2, &mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2[0], sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2)/sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3", REG_MMIO, 0x2978, 2, &mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3[0], sizeof(mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3)/sizeof(mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3", REG_MMIO, 0x2979, 2, &mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3[0], sizeof(mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3)/sizeof(mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3", REG_MMIO, 0x297a, 2, &mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3[0], sizeof(mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3)/sizeof(mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3", REG_MMIO, 0x297b, 2, &mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3[0], sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3)/sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3", REG_MMIO, 0x297c, 2, &mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3[0], sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3)/sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3", REG_MMIO, 0x297d, 2, &mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3[0], sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3)/sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3", REG_MMIO, 0x297e, 2, &mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3[0], sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3)/sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3", REG_MMIO, 0x297f, 2, &mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3[0], sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3)/sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3", REG_MMIO, 0x2980, 2, &mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3[0], sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3)/sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3", REG_MMIO, 0x2981, 2, &mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3[0], sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3)/sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3", REG_MMIO, 0x2982, 2, &mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3[0], sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3)/sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3", REG_MMIO, 0x2983, 2, &mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3[0], sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3)/sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3", REG_MMIO, 0x2984, 2, &mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3[0], sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3)/sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3", REG_MMIO, 0x2985, 2, &mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3[0], sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3)/sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3", REG_MMIO, 0x2986, 2, &mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3[0], sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3)/sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3", REG_MMIO, 0x2987, 2, &mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3[0], sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3)/sizeof(mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3[0]), 0, 0 }, + { "mmDC_COMBOPHYPLLREGS0_FREQ_CTRL0", REG_MMIO, 0x2988, 2, &mmDC_COMBOPHYPLLREGS0_FREQ_CTRL0[0], sizeof(mmDC_COMBOPHYPLLREGS0_FREQ_CTRL0)/sizeof(mmDC_COMBOPHYPLLREGS0_FREQ_CTRL0[0]), 0, 0 }, + { "mmDC_COMBOPHYPLLREGS0_FREQ_CTRL1", REG_MMIO, 0x2989, 2, &mmDC_COMBOPHYPLLREGS0_FREQ_CTRL1[0], sizeof(mmDC_COMBOPHYPLLREGS0_FREQ_CTRL1)/sizeof(mmDC_COMBOPHYPLLREGS0_FREQ_CTRL1[0]), 0, 0 }, + { "mmDC_COMBOPHYPLLREGS0_FREQ_CTRL2", REG_MMIO, 0x298a, 2, &mmDC_COMBOPHYPLLREGS0_FREQ_CTRL2[0], sizeof(mmDC_COMBOPHYPLLREGS0_FREQ_CTRL2)/sizeof(mmDC_COMBOPHYPLLREGS0_FREQ_CTRL2[0]), 0, 0 }, + { "mmDC_COMBOPHYPLLREGS0_FREQ_CTRL3", REG_MMIO, 0x298b, 2, &mmDC_COMBOPHYPLLREGS0_FREQ_CTRL3[0], sizeof(mmDC_COMBOPHYPLLREGS0_FREQ_CTRL3)/sizeof(mmDC_COMBOPHYPLLREGS0_FREQ_CTRL3[0]), 0, 0 }, + { "mmDC_COMBOPHYPLLREGS0_BW_CTRL_COARSE", REG_MMIO, 0x298c, 2, &mmDC_COMBOPHYPLLREGS0_BW_CTRL_COARSE[0], sizeof(mmDC_COMBOPHYPLLREGS0_BW_CTRL_COARSE)/sizeof(mmDC_COMBOPHYPLLREGS0_BW_CTRL_COARSE[0]), 0, 0 }, + { "mmDC_COMBOPHYPLLREGS0_BW_CTRL_FINE", REG_MMIO, 0x298d, 2, &mmDC_COMBOPHYPLLREGS0_BW_CTRL_FINE[0], sizeof(mmDC_COMBOPHYPLLREGS0_BW_CTRL_FINE)/sizeof(mmDC_COMBOPHYPLLREGS0_BW_CTRL_FINE[0]), 0, 0 }, + { "mmDC_COMBOPHYPLLREGS0_CAL_CTRL", REG_MMIO, 0x298e, 2, &mmDC_COMBOPHYPLLREGS0_CAL_CTRL[0], sizeof(mmDC_COMBOPHYPLLREGS0_CAL_CTRL)/sizeof(mmDC_COMBOPHYPLLREGS0_CAL_CTRL[0]), 0, 0 }, + { "mmDC_COMBOPHYPLLREGS0_LOOP_CTRL", REG_MMIO, 0x298f, 2, &mmDC_COMBOPHYPLLREGS0_LOOP_CTRL[0], sizeof(mmDC_COMBOPHYPLLREGS0_LOOP_CTRL)/sizeof(mmDC_COMBOPHYPLLREGS0_LOOP_CTRL[0]), 0, 0 }, + { "mmDC_COMBOPHYPLLREGS0_VREG_CFG", REG_MMIO, 0x2991, 2, &mmDC_COMBOPHYPLLREGS0_VREG_CFG[0], sizeof(mmDC_COMBOPHYPLLREGS0_VREG_CFG)/sizeof(mmDC_COMBOPHYPLLREGS0_VREG_CFG[0]), 0, 0 }, + { "mmDC_COMBOPHYPLLREGS0_OBSERVE0", REG_MMIO, 0x2992, 2, &mmDC_COMBOPHYPLLREGS0_OBSERVE0[0], sizeof(mmDC_COMBOPHYPLLREGS0_OBSERVE0)/sizeof(mmDC_COMBOPHYPLLREGS0_OBSERVE0[0]), 0, 0 }, + { "mmDC_COMBOPHYPLLREGS0_OBSERVE1", REG_MMIO, 0x2993, 2, &mmDC_COMBOPHYPLLREGS0_OBSERVE1[0], sizeof(mmDC_COMBOPHYPLLREGS0_OBSERVE1)/sizeof(mmDC_COMBOPHYPLLREGS0_OBSERVE1[0]), 0, 0 }, + { "mmDC_COMBOPHYPLLREGS0_DFT_OUT", REG_MMIO, 0x2994, 2, &mmDC_COMBOPHYPLLREGS0_DFT_OUT[0], sizeof(mmDC_COMBOPHYPLLREGS0_DFT_OUT)/sizeof(mmDC_COMBOPHYPLLREGS0_DFT_OUT[0]), 0, 0 }, + { "mmDC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL1", REG_MMIO, 0x29c6, 2, &mmDC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL1[0], sizeof(mmDC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL1)/sizeof(mmDC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL1[0]), 0, 0 }, + { "mmDC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL", REG_MMIO, 0x29c7, 2, &mmDC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL[0], sizeof(mmDC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL)/sizeof(mmDC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0", REG_MMIO, 0x2a00, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1", REG_MMIO, 0x2a01, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2", REG_MMIO, 0x2a02, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3", REG_MMIO, 0x2a03, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4", REG_MMIO, 0x2a04, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5", REG_MMIO, 0x2a05, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6", REG_MMIO, 0x2a06, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7", REG_MMIO, 0x2a07, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8", REG_MMIO, 0x2a08, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9", REG_MMIO, 0x2a09, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10", REG_MMIO, 0x2a0a, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11", REG_MMIO, 0x2a0b, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12", REG_MMIO, 0x2a0c, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13", REG_MMIO, 0x2a0d, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14", REG_MMIO, 0x2a0e, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15", REG_MMIO, 0x2a0f, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16", REG_MMIO, 0x2a10, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17", REG_MMIO, 0x2a11, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18", REG_MMIO, 0x2a12, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19", REG_MMIO, 0x2a13, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20", REG_MMIO, 0x2a14, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21", REG_MMIO, 0x2a15, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22", REG_MMIO, 0x2a16, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23", REG_MMIO, 0x2a17, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24", REG_MMIO, 0x2a18, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25", REG_MMIO, 0x2a19, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26", REG_MMIO, 0x2a1a, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27", REG_MMIO, 0x2a1b, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28", REG_MMIO, 0x2a1c, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29", REG_MMIO, 0x2a1d, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30", REG_MMIO, 0x2a1e, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31", REG_MMIO, 0x2a1f, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32", REG_MMIO, 0x2a20, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33", REG_MMIO, 0x2a21, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34", REG_MMIO, 0x2a22, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35", REG_MMIO, 0x2a23, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36", REG_MMIO, 0x2a24, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37", REG_MMIO, 0x2a25, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38", REG_MMIO, 0x2a26, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39", REG_MMIO, 0x2a27, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40", REG_MMIO, 0x2a28, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41", REG_MMIO, 0x2a29, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42", REG_MMIO, 0x2a2a, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43", REG_MMIO, 0x2a2b, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44", REG_MMIO, 0x2a2c, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45", REG_MMIO, 0x2a2d, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46", REG_MMIO, 0x2a2e, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47", REG_MMIO, 0x2a2f, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48", REG_MMIO, 0x2a30, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49", REG_MMIO, 0x2a31, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50", REG_MMIO, 0x2a32, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51", REG_MMIO, 0x2a33, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52", REG_MMIO, 0x2a34, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53", REG_MMIO, 0x2a35, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54", REG_MMIO, 0x2a36, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55", REG_MMIO, 0x2a37, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56", REG_MMIO, 0x2a38, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57", REG_MMIO, 0x2a39, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58", REG_MMIO, 0x2a3a, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59", REG_MMIO, 0x2a3b, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60", REG_MMIO, 0x2a3c, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61", REG_MMIO, 0x2a3d, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62", REG_MMIO, 0x2a3e, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63", REG_MMIO, 0x2a3f, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64", REG_MMIO, 0x2a40, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65", REG_MMIO, 0x2a41, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66", REG_MMIO, 0x2a42, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67", REG_MMIO, 0x2a43, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68", REG_MMIO, 0x2a44, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69", REG_MMIO, 0x2a45, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70", REG_MMIO, 0x2a46, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71", REG_MMIO, 0x2a47, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72", REG_MMIO, 0x2a48, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73", REG_MMIO, 0x2a49, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74", REG_MMIO, 0x2a4a, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75", REG_MMIO, 0x2a4b, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76", REG_MMIO, 0x2a4c, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77", REG_MMIO, 0x2a4d, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78", REG_MMIO, 0x2a4e, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79", REG_MMIO, 0x2a4f, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80", REG_MMIO, 0x2a50, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81", REG_MMIO, 0x2a51, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82", REG_MMIO, 0x2a52, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83", REG_MMIO, 0x2a53, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84", REG_MMIO, 0x2a54, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85", REG_MMIO, 0x2a55, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86", REG_MMIO, 0x2a56, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87", REG_MMIO, 0x2a57, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88", REG_MMIO, 0x2a58, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89", REG_MMIO, 0x2a59, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90", REG_MMIO, 0x2a5a, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91", REG_MMIO, 0x2a5b, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92", REG_MMIO, 0x2a5c, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93", REG_MMIO, 0x2a5d, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94", REG_MMIO, 0x2a5e, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95", REG_MMIO, 0x2a5f, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96", REG_MMIO, 0x2a60, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97", REG_MMIO, 0x2a61, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98", REG_MMIO, 0x2a62, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99", REG_MMIO, 0x2a63, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100", REG_MMIO, 0x2a64, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101", REG_MMIO, 0x2a65, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102", REG_MMIO, 0x2a66, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103", REG_MMIO, 0x2a67, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104", REG_MMIO, 0x2a68, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105", REG_MMIO, 0x2a69, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106", REG_MMIO, 0x2a6a, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107", REG_MMIO, 0x2a6b, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108", REG_MMIO, 0x2a6c, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109", REG_MMIO, 0x2a6d, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110", REG_MMIO, 0x2a6e, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111", REG_MMIO, 0x2a6f, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112", REG_MMIO, 0x2a70, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113", REG_MMIO, 0x2a71, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114", REG_MMIO, 0x2a72, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115", REG_MMIO, 0x2a73, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116", REG_MMIO, 0x2a74, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117", REG_MMIO, 0x2a75, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118", REG_MMIO, 0x2a76, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119", REG_MMIO, 0x2a77, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120", REG_MMIO, 0x2a78, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121", REG_MMIO, 0x2a79, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122", REG_MMIO, 0x2a7a, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123", REG_MMIO, 0x2a7b, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124", REG_MMIO, 0x2a7c, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125", REG_MMIO, 0x2a7d, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126", REG_MMIO, 0x2a7e, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127", REG_MMIO, 0x2a7f, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128", REG_MMIO, 0x2a80, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129", REG_MMIO, 0x2a81, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130", REG_MMIO, 0x2a82, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131", REG_MMIO, 0x2a83, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132", REG_MMIO, 0x2a84, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133", REG_MMIO, 0x2a85, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134", REG_MMIO, 0x2a86, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135", REG_MMIO, 0x2a87, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136", REG_MMIO, 0x2a88, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137", REG_MMIO, 0x2a89, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138", REG_MMIO, 0x2a8a, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139", REG_MMIO, 0x2a8b, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140", REG_MMIO, 0x2a8c, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141", REG_MMIO, 0x2a8d, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142", REG_MMIO, 0x2a8e, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143", REG_MMIO, 0x2a8f, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144", REG_MMIO, 0x2a90, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145", REG_MMIO, 0x2a91, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146", REG_MMIO, 0x2a92, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147", REG_MMIO, 0x2a93, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148", REG_MMIO, 0x2a94, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149", REG_MMIO, 0x2a95, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150", REG_MMIO, 0x2a96, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151", REG_MMIO, 0x2a97, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152", REG_MMIO, 0x2a98, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153", REG_MMIO, 0x2a99, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154", REG_MMIO, 0x2a9a, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155", REG_MMIO, 0x2a9b, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156", REG_MMIO, 0x2a9c, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157", REG_MMIO, 0x2a9d, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158", REG_MMIO, 0x2a9e, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158[0]), 0, 0 }, + { "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159", REG_MMIO, 0x2a9f, 2, &mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159[0], sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159)/sizeof(mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159[0]), 0, 0 }, + { "mmDC_COMBOPHYCMREGS1_COMMON_FUSE1", REG_MMIO, 0x2a00, 2, &mmDC_COMBOPHYCMREGS1_COMMON_FUSE1[0], sizeof(mmDC_COMBOPHYCMREGS1_COMMON_FUSE1)/sizeof(mmDC_COMBOPHYCMREGS1_COMMON_FUSE1[0]), 0, 0 }, + { "mmDC_COMBOPHYCMREGS1_COMMON_FUSE2", REG_MMIO, 0x2a01, 2, &mmDC_COMBOPHYCMREGS1_COMMON_FUSE2[0], sizeof(mmDC_COMBOPHYCMREGS1_COMMON_FUSE2)/sizeof(mmDC_COMBOPHYCMREGS1_COMMON_FUSE2[0]), 0, 0 }, + { "mmDC_COMBOPHYCMREGS1_COMMON_FUSE3", REG_MMIO, 0x2a02, 2, &mmDC_COMBOPHYCMREGS1_COMMON_FUSE3[0], sizeof(mmDC_COMBOPHYCMREGS1_COMMON_FUSE3)/sizeof(mmDC_COMBOPHYCMREGS1_COMMON_FUSE3[0]), 0, 0 }, + { "mmDC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM", REG_MMIO, 0x2a03, 2, &mmDC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM[0], sizeof(mmDC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM)/sizeof(mmDC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM[0]), 0, 0 }, + { "mmDC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT", REG_MMIO, 0x2a04, 2, &mmDC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT[0], sizeof(mmDC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT)/sizeof(mmDC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT[0]), 0, 0 }, + { "mmDC_COMBOPHYCMREGS1_COMMON_TXCNTRL", REG_MMIO, 0x2a05, 2, &mmDC_COMBOPHYCMREGS1_COMMON_TXCNTRL[0], sizeof(mmDC_COMBOPHYCMREGS1_COMMON_TXCNTRL)/sizeof(mmDC_COMBOPHYCMREGS1_COMMON_TXCNTRL[0]), 0, 0 }, + { "mmDC_COMBOPHYCMREGS1_COMMON_TMDP", REG_MMIO, 0x2a06, 2, &mmDC_COMBOPHYCMREGS1_COMMON_TMDP[0], sizeof(mmDC_COMBOPHYCMREGS1_COMMON_TMDP)/sizeof(mmDC_COMBOPHYCMREGS1_COMMON_TMDP[0]), 0, 0 }, + { "mmDC_COMBOPHYCMREGS1_COMMON_LANE_RESETS", REG_MMIO, 0x2a07, 2, &mmDC_COMBOPHYCMREGS1_COMMON_LANE_RESETS[0], sizeof(mmDC_COMBOPHYCMREGS1_COMMON_LANE_RESETS)/sizeof(mmDC_COMBOPHYCMREGS1_COMMON_LANE_RESETS[0]), 0, 0 }, + { "mmDC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL", REG_MMIO, 0x2a08, 2, &mmDC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL[0], sizeof(mmDC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL)/sizeof(mmDC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL[0]), 0, 0 }, + { "mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU1", REG_MMIO, 0x2a09, 2, &mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU1[0], sizeof(mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU1)/sizeof(mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU1[0]), 0, 0 }, + { "mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU2", REG_MMIO, 0x2a0a, 2, &mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU2[0], sizeof(mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU2)/sizeof(mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU2[0]), 0, 0 }, + { "mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU3", REG_MMIO, 0x2a0b, 2, &mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU3[0], sizeof(mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU3)/sizeof(mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU3[0]), 0, 0 }, + { "mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU4", REG_MMIO, 0x2a0c, 2, &mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU4[0], sizeof(mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU4)/sizeof(mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU4[0]), 0, 0 }, + { "mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU5", REG_MMIO, 0x2a0d, 2, &mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU5[0], sizeof(mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU5)/sizeof(mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU5[0]), 0, 0 }, + { "mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU6", REG_MMIO, 0x2a0e, 2, &mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU6[0], sizeof(mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU6)/sizeof(mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU6[0]), 0, 0 }, + { "mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU7", REG_MMIO, 0x2a0f, 2, &mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU7[0], sizeof(mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU7)/sizeof(mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU7[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0", REG_MMIO, 0x2a20, 2, &mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0[0], sizeof(mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0)/sizeof(mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0", REG_MMIO, 0x2a21, 2, &mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0[0], sizeof(mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0)/sizeof(mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0", REG_MMIO, 0x2a22, 2, &mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0[0], sizeof(mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0)/sizeof(mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0", REG_MMIO, 0x2a23, 2, &mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0[0], sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0)/sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0", REG_MMIO, 0x2a24, 2, &mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0[0], sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0)/sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0", REG_MMIO, 0x2a25, 2, &mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0[0], sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0)/sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0", REG_MMIO, 0x2a26, 2, &mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0[0], sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0)/sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0", REG_MMIO, 0x2a27, 2, &mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0[0], sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0)/sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0", REG_MMIO, 0x2a28, 2, &mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0[0], sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0)/sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0", REG_MMIO, 0x2a29, 2, &mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0[0], sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0)/sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0", REG_MMIO, 0x2a2a, 2, &mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0[0], sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0)/sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0", REG_MMIO, 0x2a2b, 2, &mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0[0], sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0)/sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0", REG_MMIO, 0x2a2c, 2, &mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0[0], sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0)/sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0", REG_MMIO, 0x2a2d, 2, &mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0[0], sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0)/sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0", REG_MMIO, 0x2a2e, 2, &mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0[0], sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0)/sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0", REG_MMIO, 0x2a2f, 2, &mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0[0], sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0)/sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1", REG_MMIO, 0x2a30, 2, &mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1[0], sizeof(mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1)/sizeof(mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1", REG_MMIO, 0x2a31, 2, &mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1[0], sizeof(mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1)/sizeof(mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1", REG_MMIO, 0x2a32, 2, &mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1[0], sizeof(mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1)/sizeof(mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1", REG_MMIO, 0x2a33, 2, &mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1[0], sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1)/sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1", REG_MMIO, 0x2a34, 2, &mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1[0], sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1)/sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1", REG_MMIO, 0x2a35, 2, &mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1[0], sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1)/sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1", REG_MMIO, 0x2a36, 2, &mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1[0], sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1)/sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1", REG_MMIO, 0x2a37, 2, &mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1[0], sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1)/sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1", REG_MMIO, 0x2a38, 2, &mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1[0], sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1)/sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1", REG_MMIO, 0x2a39, 2, &mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1[0], sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1)/sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1", REG_MMIO, 0x2a3a, 2, &mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1[0], sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1)/sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1", REG_MMIO, 0x2a3b, 2, &mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1[0], sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1)/sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1", REG_MMIO, 0x2a3c, 2, &mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1[0], sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1)/sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1", REG_MMIO, 0x2a3d, 2, &mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1[0], sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1)/sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1", REG_MMIO, 0x2a3e, 2, &mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1[0], sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1)/sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1", REG_MMIO, 0x2a3f, 2, &mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1[0], sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1)/sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2", REG_MMIO, 0x2a40, 2, &mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2[0], sizeof(mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2)/sizeof(mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2", REG_MMIO, 0x2a41, 2, &mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2[0], sizeof(mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2)/sizeof(mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2", REG_MMIO, 0x2a42, 2, &mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2[0], sizeof(mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2)/sizeof(mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2", REG_MMIO, 0x2a43, 2, &mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2[0], sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2)/sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2", REG_MMIO, 0x2a44, 2, &mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2[0], sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2)/sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2", REG_MMIO, 0x2a45, 2, &mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2[0], sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2)/sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2", REG_MMIO, 0x2a46, 2, &mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2[0], sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2)/sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2", REG_MMIO, 0x2a47, 2, &mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2[0], sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2)/sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2", REG_MMIO, 0x2a48, 2, &mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2[0], sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2)/sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2", REG_MMIO, 0x2a49, 2, &mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2[0], sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2)/sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2", REG_MMIO, 0x2a4a, 2, &mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2[0], sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2)/sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2", REG_MMIO, 0x2a4b, 2, &mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2[0], sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2)/sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2", REG_MMIO, 0x2a4c, 2, &mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2[0], sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2)/sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2", REG_MMIO, 0x2a4d, 2, &mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2[0], sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2)/sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2", REG_MMIO, 0x2a4e, 2, &mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2[0], sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2)/sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2", REG_MMIO, 0x2a4f, 2, &mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2[0], sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2)/sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3", REG_MMIO, 0x2a50, 2, &mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3[0], sizeof(mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3)/sizeof(mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3", REG_MMIO, 0x2a51, 2, &mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3[0], sizeof(mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3)/sizeof(mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3", REG_MMIO, 0x2a52, 2, &mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3[0], sizeof(mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3)/sizeof(mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3", REG_MMIO, 0x2a53, 2, &mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3[0], sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3)/sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3", REG_MMIO, 0x2a54, 2, &mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3[0], sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3)/sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3", REG_MMIO, 0x2a55, 2, &mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3[0], sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3)/sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3", REG_MMIO, 0x2a56, 2, &mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3[0], sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3)/sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3", REG_MMIO, 0x2a57, 2, &mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3[0], sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3)/sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3", REG_MMIO, 0x2a58, 2, &mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3[0], sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3)/sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3", REG_MMIO, 0x2a59, 2, &mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3[0], sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3)/sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3", REG_MMIO, 0x2a5a, 2, &mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3[0], sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3)/sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3", REG_MMIO, 0x2a5b, 2, &mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3[0], sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3)/sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3", REG_MMIO, 0x2a5c, 2, &mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3[0], sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3)/sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3", REG_MMIO, 0x2a5d, 2, &mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3[0], sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3)/sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3", REG_MMIO, 0x2a5e, 2, &mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3[0], sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3)/sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3", REG_MMIO, 0x2a5f, 2, &mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3[0], sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3)/sizeof(mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3[0]), 0, 0 }, + { "mmDC_COMBOPHYPLLREGS1_FREQ_CTRL0", REG_MMIO, 0x2a60, 2, &mmDC_COMBOPHYPLLREGS1_FREQ_CTRL0[0], sizeof(mmDC_COMBOPHYPLLREGS1_FREQ_CTRL0)/sizeof(mmDC_COMBOPHYPLLREGS1_FREQ_CTRL0[0]), 0, 0 }, + { "mmDC_COMBOPHYPLLREGS1_FREQ_CTRL1", REG_MMIO, 0x2a61, 2, &mmDC_COMBOPHYPLLREGS1_FREQ_CTRL1[0], sizeof(mmDC_COMBOPHYPLLREGS1_FREQ_CTRL1)/sizeof(mmDC_COMBOPHYPLLREGS1_FREQ_CTRL1[0]), 0, 0 }, + { "mmDC_COMBOPHYPLLREGS1_FREQ_CTRL2", REG_MMIO, 0x2a62, 2, &mmDC_COMBOPHYPLLREGS1_FREQ_CTRL2[0], sizeof(mmDC_COMBOPHYPLLREGS1_FREQ_CTRL2)/sizeof(mmDC_COMBOPHYPLLREGS1_FREQ_CTRL2[0]), 0, 0 }, + { "mmDC_COMBOPHYPLLREGS1_FREQ_CTRL3", REG_MMIO, 0x2a63, 2, &mmDC_COMBOPHYPLLREGS1_FREQ_CTRL3[0], sizeof(mmDC_COMBOPHYPLLREGS1_FREQ_CTRL3)/sizeof(mmDC_COMBOPHYPLLREGS1_FREQ_CTRL3[0]), 0, 0 }, + { "mmDC_COMBOPHYPLLREGS1_BW_CTRL_COARSE", REG_MMIO, 0x2a64, 2, &mmDC_COMBOPHYPLLREGS1_BW_CTRL_COARSE[0], sizeof(mmDC_COMBOPHYPLLREGS1_BW_CTRL_COARSE)/sizeof(mmDC_COMBOPHYPLLREGS1_BW_CTRL_COARSE[0]), 0, 0 }, + { "mmDC_COMBOPHYPLLREGS1_BW_CTRL_FINE", REG_MMIO, 0x2a65, 2, &mmDC_COMBOPHYPLLREGS1_BW_CTRL_FINE[0], sizeof(mmDC_COMBOPHYPLLREGS1_BW_CTRL_FINE)/sizeof(mmDC_COMBOPHYPLLREGS1_BW_CTRL_FINE[0]), 0, 0 }, + { "mmDC_COMBOPHYPLLREGS1_CAL_CTRL", REG_MMIO, 0x2a66, 2, &mmDC_COMBOPHYPLLREGS1_CAL_CTRL[0], sizeof(mmDC_COMBOPHYPLLREGS1_CAL_CTRL)/sizeof(mmDC_COMBOPHYPLLREGS1_CAL_CTRL[0]), 0, 0 }, + { "mmDC_COMBOPHYPLLREGS1_LOOP_CTRL", REG_MMIO, 0x2a67, 2, &mmDC_COMBOPHYPLLREGS1_LOOP_CTRL[0], sizeof(mmDC_COMBOPHYPLLREGS1_LOOP_CTRL)/sizeof(mmDC_COMBOPHYPLLREGS1_LOOP_CTRL[0]), 0, 0 }, + { "mmDC_COMBOPHYPLLREGS1_VREG_CFG", REG_MMIO, 0x2a69, 2, &mmDC_COMBOPHYPLLREGS1_VREG_CFG[0], sizeof(mmDC_COMBOPHYPLLREGS1_VREG_CFG)/sizeof(mmDC_COMBOPHYPLLREGS1_VREG_CFG[0]), 0, 0 }, + { "mmDC_COMBOPHYPLLREGS1_OBSERVE0", REG_MMIO, 0x2a6a, 2, &mmDC_COMBOPHYPLLREGS1_OBSERVE0[0], sizeof(mmDC_COMBOPHYPLLREGS1_OBSERVE0)/sizeof(mmDC_COMBOPHYPLLREGS1_OBSERVE0[0]), 0, 0 }, + { "mmDC_COMBOPHYPLLREGS1_OBSERVE1", REG_MMIO, 0x2a6b, 2, &mmDC_COMBOPHYPLLREGS1_OBSERVE1[0], sizeof(mmDC_COMBOPHYPLLREGS1_OBSERVE1)/sizeof(mmDC_COMBOPHYPLLREGS1_OBSERVE1[0]), 0, 0 }, + { "mmDC_COMBOPHYPLLREGS1_DFT_OUT", REG_MMIO, 0x2a6c, 2, &mmDC_COMBOPHYPLLREGS1_DFT_OUT[0], sizeof(mmDC_COMBOPHYPLLREGS1_DFT_OUT)/sizeof(mmDC_COMBOPHYPLLREGS1_DFT_OUT[0]), 0, 0 }, + { "mmDC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL1", REG_MMIO, 0x2a9e, 2, &mmDC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL1[0], sizeof(mmDC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL1)/sizeof(mmDC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL1[0]), 0, 0 }, + { "mmDC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL", REG_MMIO, 0x2a9f, 2, &mmDC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL[0], sizeof(mmDC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL)/sizeof(mmDC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0", REG_MMIO, 0x2ad8, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1", REG_MMIO, 0x2ad9, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2", REG_MMIO, 0x2ada, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3", REG_MMIO, 0x2adb, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4", REG_MMIO, 0x2adc, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5", REG_MMIO, 0x2add, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6", REG_MMIO, 0x2ade, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7", REG_MMIO, 0x2adf, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8", REG_MMIO, 0x2ae0, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9", REG_MMIO, 0x2ae1, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10", REG_MMIO, 0x2ae2, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11", REG_MMIO, 0x2ae3, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12", REG_MMIO, 0x2ae4, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13", REG_MMIO, 0x2ae5, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14", REG_MMIO, 0x2ae6, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15", REG_MMIO, 0x2ae7, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16", REG_MMIO, 0x2ae8, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17", REG_MMIO, 0x2ae9, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18", REG_MMIO, 0x2aea, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19", REG_MMIO, 0x2aeb, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20", REG_MMIO, 0x2aec, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21", REG_MMIO, 0x2aed, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22", REG_MMIO, 0x2aee, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23", REG_MMIO, 0x2aef, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24", REG_MMIO, 0x2af0, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25", REG_MMIO, 0x2af1, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26", REG_MMIO, 0x2af2, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27", REG_MMIO, 0x2af3, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28", REG_MMIO, 0x2af4, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29", REG_MMIO, 0x2af5, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30", REG_MMIO, 0x2af6, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31", REG_MMIO, 0x2af7, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32", REG_MMIO, 0x2af8, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33", REG_MMIO, 0x2af9, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34", REG_MMIO, 0x2afa, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35", REG_MMIO, 0x2afb, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36", REG_MMIO, 0x2afc, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37", REG_MMIO, 0x2afd, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38", REG_MMIO, 0x2afe, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39", REG_MMIO, 0x2aff, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40", REG_MMIO, 0x2b00, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41", REG_MMIO, 0x2b01, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42", REG_MMIO, 0x2b02, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43", REG_MMIO, 0x2b03, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44", REG_MMIO, 0x2b04, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45", REG_MMIO, 0x2b05, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46", REG_MMIO, 0x2b06, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47", REG_MMIO, 0x2b07, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48", REG_MMIO, 0x2b08, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49", REG_MMIO, 0x2b09, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50", REG_MMIO, 0x2b0a, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51", REG_MMIO, 0x2b0b, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52", REG_MMIO, 0x2b0c, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53", REG_MMIO, 0x2b0d, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54", REG_MMIO, 0x2b0e, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55", REG_MMIO, 0x2b0f, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56", REG_MMIO, 0x2b10, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57", REG_MMIO, 0x2b11, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58", REG_MMIO, 0x2b12, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59", REG_MMIO, 0x2b13, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60", REG_MMIO, 0x2b14, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61", REG_MMIO, 0x2b15, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62", REG_MMIO, 0x2b16, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63", REG_MMIO, 0x2b17, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64", REG_MMIO, 0x2b18, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65", REG_MMIO, 0x2b19, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66", REG_MMIO, 0x2b1a, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67", REG_MMIO, 0x2b1b, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68", REG_MMIO, 0x2b1c, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69", REG_MMIO, 0x2b1d, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70", REG_MMIO, 0x2b1e, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71", REG_MMIO, 0x2b1f, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72", REG_MMIO, 0x2b20, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73", REG_MMIO, 0x2b21, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74", REG_MMIO, 0x2b22, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75", REG_MMIO, 0x2b23, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76", REG_MMIO, 0x2b24, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77", REG_MMIO, 0x2b25, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78", REG_MMIO, 0x2b26, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79", REG_MMIO, 0x2b27, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80", REG_MMIO, 0x2b28, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81", REG_MMIO, 0x2b29, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82", REG_MMIO, 0x2b2a, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83", REG_MMIO, 0x2b2b, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84", REG_MMIO, 0x2b2c, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85", REG_MMIO, 0x2b2d, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86", REG_MMIO, 0x2b2e, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87", REG_MMIO, 0x2b2f, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88", REG_MMIO, 0x2b30, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89", REG_MMIO, 0x2b31, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90", REG_MMIO, 0x2b32, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91", REG_MMIO, 0x2b33, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92", REG_MMIO, 0x2b34, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93", REG_MMIO, 0x2b35, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94", REG_MMIO, 0x2b36, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95", REG_MMIO, 0x2b37, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96", REG_MMIO, 0x2b38, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97", REG_MMIO, 0x2b39, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98", REG_MMIO, 0x2b3a, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99", REG_MMIO, 0x2b3b, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100", REG_MMIO, 0x2b3c, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101", REG_MMIO, 0x2b3d, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102", REG_MMIO, 0x2b3e, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103", REG_MMIO, 0x2b3f, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104", REG_MMIO, 0x2b40, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105", REG_MMIO, 0x2b41, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106", REG_MMIO, 0x2b42, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107", REG_MMIO, 0x2b43, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108", REG_MMIO, 0x2b44, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109", REG_MMIO, 0x2b45, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110", REG_MMIO, 0x2b46, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111", REG_MMIO, 0x2b47, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112", REG_MMIO, 0x2b48, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113", REG_MMIO, 0x2b49, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114", REG_MMIO, 0x2b4a, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115", REG_MMIO, 0x2b4b, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116", REG_MMIO, 0x2b4c, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117", REG_MMIO, 0x2b4d, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118", REG_MMIO, 0x2b4e, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119", REG_MMIO, 0x2b4f, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120", REG_MMIO, 0x2b50, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121", REG_MMIO, 0x2b51, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122", REG_MMIO, 0x2b52, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123", REG_MMIO, 0x2b53, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124", REG_MMIO, 0x2b54, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125", REG_MMIO, 0x2b55, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126", REG_MMIO, 0x2b56, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127", REG_MMIO, 0x2b57, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128", REG_MMIO, 0x2b58, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129", REG_MMIO, 0x2b59, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130", REG_MMIO, 0x2b5a, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131", REG_MMIO, 0x2b5b, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132", REG_MMIO, 0x2b5c, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133", REG_MMIO, 0x2b5d, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134", REG_MMIO, 0x2b5e, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135", REG_MMIO, 0x2b5f, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136", REG_MMIO, 0x2b60, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137", REG_MMIO, 0x2b61, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138", REG_MMIO, 0x2b62, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139", REG_MMIO, 0x2b63, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140", REG_MMIO, 0x2b64, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141", REG_MMIO, 0x2b65, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142", REG_MMIO, 0x2b66, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143", REG_MMIO, 0x2b67, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144", REG_MMIO, 0x2b68, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145", REG_MMIO, 0x2b69, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146", REG_MMIO, 0x2b6a, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147", REG_MMIO, 0x2b6b, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148", REG_MMIO, 0x2b6c, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149", REG_MMIO, 0x2b6d, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150", REG_MMIO, 0x2b6e, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151", REG_MMIO, 0x2b6f, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152", REG_MMIO, 0x2b70, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153", REG_MMIO, 0x2b71, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154", REG_MMIO, 0x2b72, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155", REG_MMIO, 0x2b73, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156", REG_MMIO, 0x2b74, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157", REG_MMIO, 0x2b75, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158", REG_MMIO, 0x2b76, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158[0]), 0, 0 }, + { "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159", REG_MMIO, 0x2b77, 2, &mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159[0], sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159)/sizeof(mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159[0]), 0, 0 }, + { "mmDC_COMBOPHYCMREGS2_COMMON_FUSE1", REG_MMIO, 0x2ad8, 2, &mmDC_COMBOPHYCMREGS2_COMMON_FUSE1[0], sizeof(mmDC_COMBOPHYCMREGS2_COMMON_FUSE1)/sizeof(mmDC_COMBOPHYCMREGS2_COMMON_FUSE1[0]), 0, 0 }, + { "mmDC_COMBOPHYCMREGS2_COMMON_FUSE2", REG_MMIO, 0x2ad9, 2, &mmDC_COMBOPHYCMREGS2_COMMON_FUSE2[0], sizeof(mmDC_COMBOPHYCMREGS2_COMMON_FUSE2)/sizeof(mmDC_COMBOPHYCMREGS2_COMMON_FUSE2[0]), 0, 0 }, + { "mmDC_COMBOPHYCMREGS2_COMMON_FUSE3", REG_MMIO, 0x2ada, 2, &mmDC_COMBOPHYCMREGS2_COMMON_FUSE3[0], sizeof(mmDC_COMBOPHYCMREGS2_COMMON_FUSE3)/sizeof(mmDC_COMBOPHYCMREGS2_COMMON_FUSE3[0]), 0, 0 }, + { "mmDC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM", REG_MMIO, 0x2adb, 2, &mmDC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM[0], sizeof(mmDC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM)/sizeof(mmDC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM[0]), 0, 0 }, + { "mmDC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT", REG_MMIO, 0x2adc, 2, &mmDC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT[0], sizeof(mmDC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT)/sizeof(mmDC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT[0]), 0, 0 }, + { "mmDC_COMBOPHYCMREGS2_COMMON_TXCNTRL", REG_MMIO, 0x2add, 2, &mmDC_COMBOPHYCMREGS2_COMMON_TXCNTRL[0], sizeof(mmDC_COMBOPHYCMREGS2_COMMON_TXCNTRL)/sizeof(mmDC_COMBOPHYCMREGS2_COMMON_TXCNTRL[0]), 0, 0 }, + { "mmDC_COMBOPHYCMREGS2_COMMON_TMDP", REG_MMIO, 0x2ade, 2, &mmDC_COMBOPHYCMREGS2_COMMON_TMDP[0], sizeof(mmDC_COMBOPHYCMREGS2_COMMON_TMDP)/sizeof(mmDC_COMBOPHYCMREGS2_COMMON_TMDP[0]), 0, 0 }, + { "mmDC_COMBOPHYCMREGS2_COMMON_LANE_RESETS", REG_MMIO, 0x2adf, 2, &mmDC_COMBOPHYCMREGS2_COMMON_LANE_RESETS[0], sizeof(mmDC_COMBOPHYCMREGS2_COMMON_LANE_RESETS)/sizeof(mmDC_COMBOPHYCMREGS2_COMMON_LANE_RESETS[0]), 0, 0 }, + { "mmDC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL", REG_MMIO, 0x2ae0, 2, &mmDC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL[0], sizeof(mmDC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL)/sizeof(mmDC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL[0]), 0, 0 }, + { "mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU1", REG_MMIO, 0x2ae1, 2, &mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU1[0], sizeof(mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU1)/sizeof(mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU1[0]), 0, 0 }, + { "mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU2", REG_MMIO, 0x2ae2, 2, &mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU2[0], sizeof(mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU2)/sizeof(mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU2[0]), 0, 0 }, + { "mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU3", REG_MMIO, 0x2ae3, 2, &mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU3[0], sizeof(mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU3)/sizeof(mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU3[0]), 0, 0 }, + { "mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU4", REG_MMIO, 0x2ae4, 2, &mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU4[0], sizeof(mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU4)/sizeof(mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU4[0]), 0, 0 }, + { "mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU5", REG_MMIO, 0x2ae5, 2, &mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU5[0], sizeof(mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU5)/sizeof(mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU5[0]), 0, 0 }, + { "mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU6", REG_MMIO, 0x2ae6, 2, &mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU6[0], sizeof(mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU6)/sizeof(mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU6[0]), 0, 0 }, + { "mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU7", REG_MMIO, 0x2ae7, 2, &mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU7[0], sizeof(mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU7)/sizeof(mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU7[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0", REG_MMIO, 0x2af8, 2, &mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0[0], sizeof(mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0)/sizeof(mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0", REG_MMIO, 0x2af9, 2, &mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0[0], sizeof(mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0)/sizeof(mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0", REG_MMIO, 0x2afa, 2, &mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0[0], sizeof(mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0)/sizeof(mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0", REG_MMIO, 0x2afb, 2, &mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0[0], sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0)/sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0", REG_MMIO, 0x2afc, 2, &mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0[0], sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0)/sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0", REG_MMIO, 0x2afd, 2, &mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0[0], sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0)/sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0", REG_MMIO, 0x2afe, 2, &mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0[0], sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0)/sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0", REG_MMIO, 0x2aff, 2, &mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0[0], sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0)/sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0", REG_MMIO, 0x2b00, 2, &mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0[0], sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0)/sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0", REG_MMIO, 0x2b01, 2, &mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0[0], sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0)/sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0", REG_MMIO, 0x2b02, 2, &mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0[0], sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0)/sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0", REG_MMIO, 0x2b03, 2, &mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0[0], sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0)/sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0", REG_MMIO, 0x2b04, 2, &mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0[0], sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0)/sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0", REG_MMIO, 0x2b05, 2, &mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0[0], sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0)/sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0", REG_MMIO, 0x2b06, 2, &mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0[0], sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0)/sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0", REG_MMIO, 0x2b07, 2, &mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0[0], sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0)/sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1", REG_MMIO, 0x2b08, 2, &mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1[0], sizeof(mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1)/sizeof(mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1", REG_MMIO, 0x2b09, 2, &mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1[0], sizeof(mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1)/sizeof(mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1", REG_MMIO, 0x2b0a, 2, &mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1[0], sizeof(mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1)/sizeof(mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1", REG_MMIO, 0x2b0b, 2, &mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1[0], sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1)/sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1", REG_MMIO, 0x2b0c, 2, &mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1[0], sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1)/sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1", REG_MMIO, 0x2b0d, 2, &mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1[0], sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1)/sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1", REG_MMIO, 0x2b0e, 2, &mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1[0], sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1)/sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1", REG_MMIO, 0x2b0f, 2, &mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1[0], sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1)/sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1", REG_MMIO, 0x2b10, 2, &mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1[0], sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1)/sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1", REG_MMIO, 0x2b11, 2, &mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1[0], sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1)/sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1", REG_MMIO, 0x2b12, 2, &mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1[0], sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1)/sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1", REG_MMIO, 0x2b13, 2, &mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1[0], sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1)/sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1", REG_MMIO, 0x2b14, 2, &mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1[0], sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1)/sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1", REG_MMIO, 0x2b15, 2, &mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1[0], sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1)/sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1", REG_MMIO, 0x2b16, 2, &mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1[0], sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1)/sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1", REG_MMIO, 0x2b17, 2, &mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1[0], sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1)/sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2", REG_MMIO, 0x2b18, 2, &mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2[0], sizeof(mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2)/sizeof(mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2", REG_MMIO, 0x2b19, 2, &mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2[0], sizeof(mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2)/sizeof(mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2", REG_MMIO, 0x2b1a, 2, &mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2[0], sizeof(mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2)/sizeof(mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2", REG_MMIO, 0x2b1b, 2, &mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2[0], sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2)/sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2", REG_MMIO, 0x2b1c, 2, &mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2[0], sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2)/sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2", REG_MMIO, 0x2b1d, 2, &mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2[0], sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2)/sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2", REG_MMIO, 0x2b1e, 2, &mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2[0], sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2)/sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2", REG_MMIO, 0x2b1f, 2, &mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2[0], sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2)/sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2", REG_MMIO, 0x2b20, 2, &mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2[0], sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2)/sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2", REG_MMIO, 0x2b21, 2, &mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2[0], sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2)/sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2", REG_MMIO, 0x2b22, 2, &mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2[0], sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2)/sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2", REG_MMIO, 0x2b23, 2, &mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2[0], sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2)/sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2", REG_MMIO, 0x2b24, 2, &mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2[0], sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2)/sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2", REG_MMIO, 0x2b25, 2, &mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2[0], sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2)/sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2", REG_MMIO, 0x2b26, 2, &mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2[0], sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2)/sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2", REG_MMIO, 0x2b27, 2, &mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2[0], sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2)/sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3", REG_MMIO, 0x2b28, 2, &mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3[0], sizeof(mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3)/sizeof(mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3", REG_MMIO, 0x2b29, 2, &mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3[0], sizeof(mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3)/sizeof(mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3", REG_MMIO, 0x2b2a, 2, &mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3[0], sizeof(mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3)/sizeof(mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3", REG_MMIO, 0x2b2b, 2, &mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3[0], sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3)/sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3", REG_MMIO, 0x2b2c, 2, &mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3[0], sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3)/sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3", REG_MMIO, 0x2b2d, 2, &mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3[0], sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3)/sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3", REG_MMIO, 0x2b2e, 2, &mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3[0], sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3)/sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3", REG_MMIO, 0x2b2f, 2, &mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3[0], sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3)/sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3", REG_MMIO, 0x2b30, 2, &mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3[0], sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3)/sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3", REG_MMIO, 0x2b31, 2, &mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3[0], sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3)/sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3", REG_MMIO, 0x2b32, 2, &mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3[0], sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3)/sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3", REG_MMIO, 0x2b33, 2, &mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3[0], sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3)/sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3", REG_MMIO, 0x2b34, 2, &mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3[0], sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3)/sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3", REG_MMIO, 0x2b35, 2, &mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3[0], sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3)/sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3", REG_MMIO, 0x2b36, 2, &mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3[0], sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3)/sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3", REG_MMIO, 0x2b37, 2, &mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3[0], sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3)/sizeof(mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3[0]), 0, 0 }, + { "mmDC_COMBOPHYPLLREGS2_FREQ_CTRL0", REG_MMIO, 0x2b38, 2, &mmDC_COMBOPHYPLLREGS2_FREQ_CTRL0[0], sizeof(mmDC_COMBOPHYPLLREGS2_FREQ_CTRL0)/sizeof(mmDC_COMBOPHYPLLREGS2_FREQ_CTRL0[0]), 0, 0 }, + { "mmDC_COMBOPHYPLLREGS2_FREQ_CTRL1", REG_MMIO, 0x2b39, 2, &mmDC_COMBOPHYPLLREGS2_FREQ_CTRL1[0], sizeof(mmDC_COMBOPHYPLLREGS2_FREQ_CTRL1)/sizeof(mmDC_COMBOPHYPLLREGS2_FREQ_CTRL1[0]), 0, 0 }, + { "mmDC_COMBOPHYPLLREGS2_FREQ_CTRL2", REG_MMIO, 0x2b3a, 2, &mmDC_COMBOPHYPLLREGS2_FREQ_CTRL2[0], sizeof(mmDC_COMBOPHYPLLREGS2_FREQ_CTRL2)/sizeof(mmDC_COMBOPHYPLLREGS2_FREQ_CTRL2[0]), 0, 0 }, + { "mmDC_COMBOPHYPLLREGS2_FREQ_CTRL3", REG_MMIO, 0x2b3b, 2, &mmDC_COMBOPHYPLLREGS2_FREQ_CTRL3[0], sizeof(mmDC_COMBOPHYPLLREGS2_FREQ_CTRL3)/sizeof(mmDC_COMBOPHYPLLREGS2_FREQ_CTRL3[0]), 0, 0 }, + { "mmDC_COMBOPHYPLLREGS2_BW_CTRL_COARSE", REG_MMIO, 0x2b3c, 2, &mmDC_COMBOPHYPLLREGS2_BW_CTRL_COARSE[0], sizeof(mmDC_COMBOPHYPLLREGS2_BW_CTRL_COARSE)/sizeof(mmDC_COMBOPHYPLLREGS2_BW_CTRL_COARSE[0]), 0, 0 }, + { "mmDC_COMBOPHYPLLREGS2_BW_CTRL_FINE", REG_MMIO, 0x2b3d, 2, &mmDC_COMBOPHYPLLREGS2_BW_CTRL_FINE[0], sizeof(mmDC_COMBOPHYPLLREGS2_BW_CTRL_FINE)/sizeof(mmDC_COMBOPHYPLLREGS2_BW_CTRL_FINE[0]), 0, 0 }, + { "mmDC_COMBOPHYPLLREGS2_CAL_CTRL", REG_MMIO, 0x2b3e, 2, &mmDC_COMBOPHYPLLREGS2_CAL_CTRL[0], sizeof(mmDC_COMBOPHYPLLREGS2_CAL_CTRL)/sizeof(mmDC_COMBOPHYPLLREGS2_CAL_CTRL[0]), 0, 0 }, + { "mmDC_COMBOPHYPLLREGS2_LOOP_CTRL", REG_MMIO, 0x2b3f, 2, &mmDC_COMBOPHYPLLREGS2_LOOP_CTRL[0], sizeof(mmDC_COMBOPHYPLLREGS2_LOOP_CTRL)/sizeof(mmDC_COMBOPHYPLLREGS2_LOOP_CTRL[0]), 0, 0 }, + { "mmDC_COMBOPHYPLLREGS2_VREG_CFG", REG_MMIO, 0x2b41, 2, &mmDC_COMBOPHYPLLREGS2_VREG_CFG[0], sizeof(mmDC_COMBOPHYPLLREGS2_VREG_CFG)/sizeof(mmDC_COMBOPHYPLLREGS2_VREG_CFG[0]), 0, 0 }, + { "mmDC_COMBOPHYPLLREGS2_OBSERVE0", REG_MMIO, 0x2b42, 2, &mmDC_COMBOPHYPLLREGS2_OBSERVE0[0], sizeof(mmDC_COMBOPHYPLLREGS2_OBSERVE0)/sizeof(mmDC_COMBOPHYPLLREGS2_OBSERVE0[0]), 0, 0 }, + { "mmDC_COMBOPHYPLLREGS2_OBSERVE1", REG_MMIO, 0x2b43, 2, &mmDC_COMBOPHYPLLREGS2_OBSERVE1[0], sizeof(mmDC_COMBOPHYPLLREGS2_OBSERVE1)/sizeof(mmDC_COMBOPHYPLLREGS2_OBSERVE1[0]), 0, 0 }, + { "mmDC_COMBOPHYPLLREGS2_DFT_OUT", REG_MMIO, 0x2b44, 2, &mmDC_COMBOPHYPLLREGS2_DFT_OUT[0], sizeof(mmDC_COMBOPHYPLLREGS2_DFT_OUT)/sizeof(mmDC_COMBOPHYPLLREGS2_DFT_OUT[0]), 0, 0 }, + { "mmDC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL1", REG_MMIO, 0x2b76, 2, &mmDC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL1[0], sizeof(mmDC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL1)/sizeof(mmDC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL1[0]), 0, 0 }, + { "mmDC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL", REG_MMIO, 0x2b77, 2, &mmDC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL[0], sizeof(mmDC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL)/sizeof(mmDC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0", REG_MMIO, 0x2bb0, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1", REG_MMIO, 0x2bb1, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2", REG_MMIO, 0x2bb2, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3", REG_MMIO, 0x2bb3, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4", REG_MMIO, 0x2bb4, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5", REG_MMIO, 0x2bb5, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6", REG_MMIO, 0x2bb6, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7", REG_MMIO, 0x2bb7, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8", REG_MMIO, 0x2bb8, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9", REG_MMIO, 0x2bb9, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10", REG_MMIO, 0x2bba, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11", REG_MMIO, 0x2bbb, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12", REG_MMIO, 0x2bbc, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13", REG_MMIO, 0x2bbd, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14", REG_MMIO, 0x2bbe, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15", REG_MMIO, 0x2bbf, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16", REG_MMIO, 0x2bc0, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17", REG_MMIO, 0x2bc1, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18", REG_MMIO, 0x2bc2, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19", REG_MMIO, 0x2bc3, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20", REG_MMIO, 0x2bc4, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21", REG_MMIO, 0x2bc5, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22", REG_MMIO, 0x2bc6, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23", REG_MMIO, 0x2bc7, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24", REG_MMIO, 0x2bc8, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25", REG_MMIO, 0x2bc9, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26", REG_MMIO, 0x2bca, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27", REG_MMIO, 0x2bcb, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28", REG_MMIO, 0x2bcc, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29", REG_MMIO, 0x2bcd, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30", REG_MMIO, 0x2bce, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31", REG_MMIO, 0x2bcf, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32", REG_MMIO, 0x2bd0, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33", REG_MMIO, 0x2bd1, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34", REG_MMIO, 0x2bd2, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35", REG_MMIO, 0x2bd3, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36", REG_MMIO, 0x2bd4, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37", REG_MMIO, 0x2bd5, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38", REG_MMIO, 0x2bd6, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39", REG_MMIO, 0x2bd7, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40", REG_MMIO, 0x2bd8, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41", REG_MMIO, 0x2bd9, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42", REG_MMIO, 0x2bda, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43", REG_MMIO, 0x2bdb, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44", REG_MMIO, 0x2bdc, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45", REG_MMIO, 0x2bdd, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46", REG_MMIO, 0x2bde, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47", REG_MMIO, 0x2bdf, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48", REG_MMIO, 0x2be0, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49", REG_MMIO, 0x2be1, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50", REG_MMIO, 0x2be2, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51", REG_MMIO, 0x2be3, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52", REG_MMIO, 0x2be4, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53", REG_MMIO, 0x2be5, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54", REG_MMIO, 0x2be6, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55", REG_MMIO, 0x2be7, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56", REG_MMIO, 0x2be8, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57", REG_MMIO, 0x2be9, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58", REG_MMIO, 0x2bea, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59", REG_MMIO, 0x2beb, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60", REG_MMIO, 0x2bec, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61", REG_MMIO, 0x2bed, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62", REG_MMIO, 0x2bee, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63", REG_MMIO, 0x2bef, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64", REG_MMIO, 0x2bf0, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65", REG_MMIO, 0x2bf1, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66", REG_MMIO, 0x2bf2, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67", REG_MMIO, 0x2bf3, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68", REG_MMIO, 0x2bf4, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69", REG_MMIO, 0x2bf5, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70", REG_MMIO, 0x2bf6, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71", REG_MMIO, 0x2bf7, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72", REG_MMIO, 0x2bf8, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73", REG_MMIO, 0x2bf9, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74", REG_MMIO, 0x2bfa, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75", REG_MMIO, 0x2bfb, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76", REG_MMIO, 0x2bfc, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77", REG_MMIO, 0x2bfd, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78", REG_MMIO, 0x2bfe, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79", REG_MMIO, 0x2bff, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80", REG_MMIO, 0x2c00, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81", REG_MMIO, 0x2c01, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82", REG_MMIO, 0x2c02, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83", REG_MMIO, 0x2c03, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84", REG_MMIO, 0x2c04, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85", REG_MMIO, 0x2c05, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86", REG_MMIO, 0x2c06, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87", REG_MMIO, 0x2c07, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88", REG_MMIO, 0x2c08, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89", REG_MMIO, 0x2c09, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90", REG_MMIO, 0x2c0a, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91", REG_MMIO, 0x2c0b, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92", REG_MMIO, 0x2c0c, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93", REG_MMIO, 0x2c0d, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94", REG_MMIO, 0x2c0e, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95", REG_MMIO, 0x2c0f, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96", REG_MMIO, 0x2c10, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97", REG_MMIO, 0x2c11, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98", REG_MMIO, 0x2c12, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99", REG_MMIO, 0x2c13, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100", REG_MMIO, 0x2c14, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101", REG_MMIO, 0x2c15, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102", REG_MMIO, 0x2c16, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103", REG_MMIO, 0x2c17, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104", REG_MMIO, 0x2c18, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105", REG_MMIO, 0x2c19, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106", REG_MMIO, 0x2c1a, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107", REG_MMIO, 0x2c1b, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108", REG_MMIO, 0x2c1c, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109", REG_MMIO, 0x2c1d, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110", REG_MMIO, 0x2c1e, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111", REG_MMIO, 0x2c1f, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112", REG_MMIO, 0x2c20, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113", REG_MMIO, 0x2c21, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114", REG_MMIO, 0x2c22, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115", REG_MMIO, 0x2c23, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116", REG_MMIO, 0x2c24, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117", REG_MMIO, 0x2c25, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118", REG_MMIO, 0x2c26, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119", REG_MMIO, 0x2c27, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120", REG_MMIO, 0x2c28, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121", REG_MMIO, 0x2c29, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122", REG_MMIO, 0x2c2a, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123", REG_MMIO, 0x2c2b, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124", REG_MMIO, 0x2c2c, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125", REG_MMIO, 0x2c2d, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126", REG_MMIO, 0x2c2e, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127", REG_MMIO, 0x2c2f, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128", REG_MMIO, 0x2c30, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129", REG_MMIO, 0x2c31, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130", REG_MMIO, 0x2c32, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131", REG_MMIO, 0x2c33, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132", REG_MMIO, 0x2c34, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133", REG_MMIO, 0x2c35, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134", REG_MMIO, 0x2c36, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135", REG_MMIO, 0x2c37, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136", REG_MMIO, 0x2c38, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137", REG_MMIO, 0x2c39, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138", REG_MMIO, 0x2c3a, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139", REG_MMIO, 0x2c3b, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140", REG_MMIO, 0x2c3c, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141", REG_MMIO, 0x2c3d, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142", REG_MMIO, 0x2c3e, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143", REG_MMIO, 0x2c3f, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144", REG_MMIO, 0x2c40, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145", REG_MMIO, 0x2c41, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146", REG_MMIO, 0x2c42, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147", REG_MMIO, 0x2c43, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148", REG_MMIO, 0x2c44, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149", REG_MMIO, 0x2c45, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150", REG_MMIO, 0x2c46, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151", REG_MMIO, 0x2c47, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152", REG_MMIO, 0x2c48, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153", REG_MMIO, 0x2c49, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154", REG_MMIO, 0x2c4a, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155", REG_MMIO, 0x2c4b, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156", REG_MMIO, 0x2c4c, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157", REG_MMIO, 0x2c4d, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158", REG_MMIO, 0x2c4e, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158[0]), 0, 0 }, + { "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159", REG_MMIO, 0x2c4f, 2, &mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159[0], sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159)/sizeof(mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159[0]), 0, 0 }, + { "mmDC_COMBOPHYCMREGS3_COMMON_FUSE1", REG_MMIO, 0x2bb0, 2, &mmDC_COMBOPHYCMREGS3_COMMON_FUSE1[0], sizeof(mmDC_COMBOPHYCMREGS3_COMMON_FUSE1)/sizeof(mmDC_COMBOPHYCMREGS3_COMMON_FUSE1[0]), 0, 0 }, + { "mmDC_COMBOPHYCMREGS3_COMMON_FUSE2", REG_MMIO, 0x2bb1, 2, &mmDC_COMBOPHYCMREGS3_COMMON_FUSE2[0], sizeof(mmDC_COMBOPHYCMREGS3_COMMON_FUSE2)/sizeof(mmDC_COMBOPHYCMREGS3_COMMON_FUSE2[0]), 0, 0 }, + { "mmDC_COMBOPHYCMREGS3_COMMON_FUSE3", REG_MMIO, 0x2bb2, 2, &mmDC_COMBOPHYCMREGS3_COMMON_FUSE3[0], sizeof(mmDC_COMBOPHYCMREGS3_COMMON_FUSE3)/sizeof(mmDC_COMBOPHYCMREGS3_COMMON_FUSE3[0]), 0, 0 }, + { "mmDC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM", REG_MMIO, 0x2bb3, 2, &mmDC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM[0], sizeof(mmDC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM)/sizeof(mmDC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM[0]), 0, 0 }, + { "mmDC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT", REG_MMIO, 0x2bb4, 2, &mmDC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT[0], sizeof(mmDC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT)/sizeof(mmDC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT[0]), 0, 0 }, + { "mmDC_COMBOPHYCMREGS3_COMMON_TXCNTRL", REG_MMIO, 0x2bb5, 2, &mmDC_COMBOPHYCMREGS3_COMMON_TXCNTRL[0], sizeof(mmDC_COMBOPHYCMREGS3_COMMON_TXCNTRL)/sizeof(mmDC_COMBOPHYCMREGS3_COMMON_TXCNTRL[0]), 0, 0 }, + { "mmDC_COMBOPHYCMREGS3_COMMON_TMDP", REG_MMIO, 0x2bb6, 2, &mmDC_COMBOPHYCMREGS3_COMMON_TMDP[0], sizeof(mmDC_COMBOPHYCMREGS3_COMMON_TMDP)/sizeof(mmDC_COMBOPHYCMREGS3_COMMON_TMDP[0]), 0, 0 }, + { "mmDC_COMBOPHYCMREGS3_COMMON_LANE_RESETS", REG_MMIO, 0x2bb7, 2, &mmDC_COMBOPHYCMREGS3_COMMON_LANE_RESETS[0], sizeof(mmDC_COMBOPHYCMREGS3_COMMON_LANE_RESETS)/sizeof(mmDC_COMBOPHYCMREGS3_COMMON_LANE_RESETS[0]), 0, 0 }, + { "mmDC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL", REG_MMIO, 0x2bb8, 2, &mmDC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL[0], sizeof(mmDC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL)/sizeof(mmDC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL[0]), 0, 0 }, + { "mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU1", REG_MMIO, 0x2bb9, 2, &mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU1[0], sizeof(mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU1)/sizeof(mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU1[0]), 0, 0 }, + { "mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU2", REG_MMIO, 0x2bba, 2, &mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU2[0], sizeof(mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU2)/sizeof(mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU2[0]), 0, 0 }, + { "mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU3", REG_MMIO, 0x2bbb, 2, &mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU3[0], sizeof(mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU3)/sizeof(mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU3[0]), 0, 0 }, + { "mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU4", REG_MMIO, 0x2bbc, 2, &mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU4[0], sizeof(mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU4)/sizeof(mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU4[0]), 0, 0 }, + { "mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU5", REG_MMIO, 0x2bbd, 2, &mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU5[0], sizeof(mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU5)/sizeof(mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU5[0]), 0, 0 }, + { "mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU6", REG_MMIO, 0x2bbe, 2, &mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU6[0], sizeof(mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU6)/sizeof(mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU6[0]), 0, 0 }, + { "mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU7", REG_MMIO, 0x2bbf, 2, &mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU7[0], sizeof(mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU7)/sizeof(mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU7[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0", REG_MMIO, 0x2bd0, 2, &mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0[0], sizeof(mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0)/sizeof(mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0", REG_MMIO, 0x2bd1, 2, &mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0[0], sizeof(mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0)/sizeof(mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0", REG_MMIO, 0x2bd2, 2, &mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0[0], sizeof(mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0)/sizeof(mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0", REG_MMIO, 0x2bd3, 2, &mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0[0], sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0)/sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0", REG_MMIO, 0x2bd4, 2, &mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0[0], sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0)/sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0", REG_MMIO, 0x2bd5, 2, &mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0[0], sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0)/sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0", REG_MMIO, 0x2bd6, 2, &mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0[0], sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0)/sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0", REG_MMIO, 0x2bd7, 2, &mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0[0], sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0)/sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0", REG_MMIO, 0x2bd8, 2, &mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0[0], sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0)/sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0", REG_MMIO, 0x2bd9, 2, &mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0[0], sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0)/sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0", REG_MMIO, 0x2bda, 2, &mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0[0], sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0)/sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0", REG_MMIO, 0x2bdb, 2, &mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0[0], sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0)/sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0", REG_MMIO, 0x2bdc, 2, &mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0[0], sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0)/sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0", REG_MMIO, 0x2bdd, 2, &mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0[0], sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0)/sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0", REG_MMIO, 0x2bde, 2, &mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0[0], sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0)/sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0", REG_MMIO, 0x2bdf, 2, &mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0[0], sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0)/sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1", REG_MMIO, 0x2be0, 2, &mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1[0], sizeof(mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1)/sizeof(mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1", REG_MMIO, 0x2be1, 2, &mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1[0], sizeof(mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1)/sizeof(mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1", REG_MMIO, 0x2be2, 2, &mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1[0], sizeof(mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1)/sizeof(mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1", REG_MMIO, 0x2be3, 2, &mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1[0], sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1)/sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1", REG_MMIO, 0x2be4, 2, &mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1[0], sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1)/sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1", REG_MMIO, 0x2be5, 2, &mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1[0], sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1)/sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1", REG_MMIO, 0x2be6, 2, &mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1[0], sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1)/sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1", REG_MMIO, 0x2be7, 2, &mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1[0], sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1)/sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1", REG_MMIO, 0x2be8, 2, &mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1[0], sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1)/sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1", REG_MMIO, 0x2be9, 2, &mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1[0], sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1)/sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1", REG_MMIO, 0x2bea, 2, &mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1[0], sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1)/sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1", REG_MMIO, 0x2beb, 2, &mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1[0], sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1)/sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1", REG_MMIO, 0x2bec, 2, &mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1[0], sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1)/sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1", REG_MMIO, 0x2bed, 2, &mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1[0], sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1)/sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1", REG_MMIO, 0x2bee, 2, &mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1[0], sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1)/sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1", REG_MMIO, 0x2bef, 2, &mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1[0], sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1)/sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2", REG_MMIO, 0x2bf0, 2, &mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2[0], sizeof(mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2)/sizeof(mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2", REG_MMIO, 0x2bf1, 2, &mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2[0], sizeof(mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2)/sizeof(mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2", REG_MMIO, 0x2bf2, 2, &mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2[0], sizeof(mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2)/sizeof(mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2", REG_MMIO, 0x2bf3, 2, &mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2[0], sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2)/sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2", REG_MMIO, 0x2bf4, 2, &mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2[0], sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2)/sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2", REG_MMIO, 0x2bf5, 2, &mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2[0], sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2)/sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2", REG_MMIO, 0x2bf6, 2, &mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2[0], sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2)/sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2", REG_MMIO, 0x2bf7, 2, &mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2[0], sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2)/sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2", REG_MMIO, 0x2bf8, 2, &mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2[0], sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2)/sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2", REG_MMIO, 0x2bf9, 2, &mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2[0], sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2)/sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2", REG_MMIO, 0x2bfa, 2, &mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2[0], sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2)/sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2", REG_MMIO, 0x2bfb, 2, &mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2[0], sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2)/sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2", REG_MMIO, 0x2bfc, 2, &mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2[0], sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2)/sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2", REG_MMIO, 0x2bfd, 2, &mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2[0], sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2)/sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2", REG_MMIO, 0x2bfe, 2, &mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2[0], sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2)/sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2", REG_MMIO, 0x2bff, 2, &mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2[0], sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2)/sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3", REG_MMIO, 0x2c00, 2, &mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3[0], sizeof(mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3)/sizeof(mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3", REG_MMIO, 0x2c01, 2, &mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3[0], sizeof(mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3)/sizeof(mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3", REG_MMIO, 0x2c02, 2, &mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3[0], sizeof(mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3)/sizeof(mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3", REG_MMIO, 0x2c03, 2, &mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3[0], sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3)/sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3", REG_MMIO, 0x2c04, 2, &mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3[0], sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3)/sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3", REG_MMIO, 0x2c05, 2, &mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3[0], sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3)/sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3", REG_MMIO, 0x2c06, 2, &mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3[0], sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3)/sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3", REG_MMIO, 0x2c07, 2, &mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3[0], sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3)/sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3", REG_MMIO, 0x2c08, 2, &mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3[0], sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3)/sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3", REG_MMIO, 0x2c09, 2, &mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3[0], sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3)/sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3", REG_MMIO, 0x2c0a, 2, &mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3[0], sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3)/sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3", REG_MMIO, 0x2c0b, 2, &mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3[0], sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3)/sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3", REG_MMIO, 0x2c0c, 2, &mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3[0], sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3)/sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3", REG_MMIO, 0x2c0d, 2, &mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3[0], sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3)/sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3", REG_MMIO, 0x2c0e, 2, &mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3[0], sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3)/sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3[0]), 0, 0 }, + { "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3", REG_MMIO, 0x2c0f, 2, &mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3[0], sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3)/sizeof(mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3[0]), 0, 0 }, + { "mmDC_COMBOPHYPLLREGS3_FREQ_CTRL0", REG_MMIO, 0x2c10, 2, &mmDC_COMBOPHYPLLREGS3_FREQ_CTRL0[0], sizeof(mmDC_COMBOPHYPLLREGS3_FREQ_CTRL0)/sizeof(mmDC_COMBOPHYPLLREGS3_FREQ_CTRL0[0]), 0, 0 }, + { "mmDC_COMBOPHYPLLREGS3_FREQ_CTRL1", REG_MMIO, 0x2c11, 2, &mmDC_COMBOPHYPLLREGS3_FREQ_CTRL1[0], sizeof(mmDC_COMBOPHYPLLREGS3_FREQ_CTRL1)/sizeof(mmDC_COMBOPHYPLLREGS3_FREQ_CTRL1[0]), 0, 0 }, + { "mmDC_COMBOPHYPLLREGS3_FREQ_CTRL2", REG_MMIO, 0x2c12, 2, &mmDC_COMBOPHYPLLREGS3_FREQ_CTRL2[0], sizeof(mmDC_COMBOPHYPLLREGS3_FREQ_CTRL2)/sizeof(mmDC_COMBOPHYPLLREGS3_FREQ_CTRL2[0]), 0, 0 }, + { "mmDC_COMBOPHYPLLREGS3_FREQ_CTRL3", REG_MMIO, 0x2c13, 2, &mmDC_COMBOPHYPLLREGS3_FREQ_CTRL3[0], sizeof(mmDC_COMBOPHYPLLREGS3_FREQ_CTRL3)/sizeof(mmDC_COMBOPHYPLLREGS3_FREQ_CTRL3[0]), 0, 0 }, + { "mmDC_COMBOPHYPLLREGS3_BW_CTRL_COARSE", REG_MMIO, 0x2c14, 2, &mmDC_COMBOPHYPLLREGS3_BW_CTRL_COARSE[0], sizeof(mmDC_COMBOPHYPLLREGS3_BW_CTRL_COARSE)/sizeof(mmDC_COMBOPHYPLLREGS3_BW_CTRL_COARSE[0]), 0, 0 }, + { "mmDC_COMBOPHYPLLREGS3_BW_CTRL_FINE", REG_MMIO, 0x2c15, 2, &mmDC_COMBOPHYPLLREGS3_BW_CTRL_FINE[0], sizeof(mmDC_COMBOPHYPLLREGS3_BW_CTRL_FINE)/sizeof(mmDC_COMBOPHYPLLREGS3_BW_CTRL_FINE[0]), 0, 0 }, + { "mmDC_COMBOPHYPLLREGS3_CAL_CTRL", REG_MMIO, 0x2c16, 2, &mmDC_COMBOPHYPLLREGS3_CAL_CTRL[0], sizeof(mmDC_COMBOPHYPLLREGS3_CAL_CTRL)/sizeof(mmDC_COMBOPHYPLLREGS3_CAL_CTRL[0]), 0, 0 }, + { "mmDC_COMBOPHYPLLREGS3_LOOP_CTRL", REG_MMIO, 0x2c17, 2, &mmDC_COMBOPHYPLLREGS3_LOOP_CTRL[0], sizeof(mmDC_COMBOPHYPLLREGS3_LOOP_CTRL)/sizeof(mmDC_COMBOPHYPLLREGS3_LOOP_CTRL[0]), 0, 0 }, + { "mmDC_COMBOPHYPLLREGS3_VREG_CFG", REG_MMIO, 0x2c19, 2, &mmDC_COMBOPHYPLLREGS3_VREG_CFG[0], sizeof(mmDC_COMBOPHYPLLREGS3_VREG_CFG)/sizeof(mmDC_COMBOPHYPLLREGS3_VREG_CFG[0]), 0, 0 }, + { "mmDC_COMBOPHYPLLREGS3_OBSERVE0", REG_MMIO, 0x2c1a, 2, &mmDC_COMBOPHYPLLREGS3_OBSERVE0[0], sizeof(mmDC_COMBOPHYPLLREGS3_OBSERVE0)/sizeof(mmDC_COMBOPHYPLLREGS3_OBSERVE0[0]), 0, 0 }, + { "mmDC_COMBOPHYPLLREGS3_OBSERVE1", REG_MMIO, 0x2c1b, 2, &mmDC_COMBOPHYPLLREGS3_OBSERVE1[0], sizeof(mmDC_COMBOPHYPLLREGS3_OBSERVE1)/sizeof(mmDC_COMBOPHYPLLREGS3_OBSERVE1[0]), 0, 0 }, + { "mmDC_COMBOPHYPLLREGS3_DFT_OUT", REG_MMIO, 0x2c1c, 2, &mmDC_COMBOPHYPLLREGS3_DFT_OUT[0], sizeof(mmDC_COMBOPHYPLLREGS3_DFT_OUT)/sizeof(mmDC_COMBOPHYPLLREGS3_DFT_OUT[0]), 0, 0 }, + { "mmDC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL1", REG_MMIO, 0x2c4e, 2, &mmDC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL1[0], sizeof(mmDC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL1)/sizeof(mmDC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL1[0]), 0, 0 }, + { "mmDC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL", REG_MMIO, 0x2c4f, 2, &mmDC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL[0], sizeof(mmDC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL)/sizeof(mmDC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL[0]), 0, 0 }, + { "mmZCAL_MACRO_CNTL_RESERVED0", REG_MMIO, 0x2fe8, 2, &mmZCAL_MACRO_CNTL_RESERVED0[0], sizeof(mmZCAL_MACRO_CNTL_RESERVED0)/sizeof(mmZCAL_MACRO_CNTL_RESERVED0[0]), 0, 0 }, + { "mmZCAL_MACRO_CNTL_RESERVED1", REG_MMIO, 0x2fe9, 2, &mmZCAL_MACRO_CNTL_RESERVED1[0], sizeof(mmZCAL_MACRO_CNTL_RESERVED1)/sizeof(mmZCAL_MACRO_CNTL_RESERVED1[0]), 0, 0 }, + { "mmZCAL_MACRO_CNTL_RESERVED2", REG_MMIO, 0x2fea, 2, &mmZCAL_MACRO_CNTL_RESERVED2[0], sizeof(mmZCAL_MACRO_CNTL_RESERVED2)/sizeof(mmZCAL_MACRO_CNTL_RESERVED2[0]), 0, 0 }, + { "mmZCAL_MACRO_CNTL_RESERVED3", REG_MMIO, 0x2feb, 2, &mmZCAL_MACRO_CNTL_RESERVED3[0], sizeof(mmZCAL_MACRO_CNTL_RESERVED3)/sizeof(mmZCAL_MACRO_CNTL_RESERVED3[0]), 0, 0 }, + { "mmZCAL_MACRO_CNTL_RESERVED4", REG_MMIO, 0x2fec, 2, &mmZCAL_MACRO_CNTL_RESERVED4[0], sizeof(mmZCAL_MACRO_CNTL_RESERVED4)/sizeof(mmZCAL_MACRO_CNTL_RESERVED4[0]), 0, 0 }, + { "mmCOMP_EN_CTL", REG_MMIO, 0x2fe8, 2, &mmCOMP_EN_CTL[0], sizeof(mmCOMP_EN_CTL)/sizeof(mmCOMP_EN_CTL[0]), 0, 0 }, + { "mmCOMP_EN_DFX", REG_MMIO, 0x2fe9, 2, &mmCOMP_EN_DFX[0], sizeof(mmCOMP_EN_DFX)/sizeof(mmCOMP_EN_DFX[0]), 0, 0 }, + { "mmZCAL_FUSES", REG_MMIO, 0x2fea, 2, &mmZCAL_FUSES[0], sizeof(mmZCAL_FUSES)/sizeof(mmZCAL_FUSES[0]), 0, 0 }, + { "ixSEQ00", REG_SMC, 0x0000, 0, &ixSEQ00[0], sizeof(ixSEQ00)/sizeof(ixSEQ00[0]), 0, 0 }, + { "ixSEQ01", REG_SMC, 0x0001, 0, &ixSEQ01[0], sizeof(ixSEQ01)/sizeof(ixSEQ01[0]), 0, 0 }, + { "ixSEQ02", REG_SMC, 0x0002, 0, &ixSEQ02[0], sizeof(ixSEQ02)/sizeof(ixSEQ02[0]), 0, 0 }, + { "ixSEQ03", REG_SMC, 0x0003, 0, &ixSEQ03[0], sizeof(ixSEQ03)/sizeof(ixSEQ03[0]), 0, 0 }, + { "ixSEQ04", REG_SMC, 0x0004, 0, &ixSEQ04[0], sizeof(ixSEQ04)/sizeof(ixSEQ04[0]), 0, 0 }, + { "ixCRT00", REG_SMC, 0x0000, 0, &ixCRT00[0], sizeof(ixCRT00)/sizeof(ixCRT00[0]), 0, 0 }, + { "ixCRT01", REG_SMC, 0x0001, 0, &ixCRT01[0], sizeof(ixCRT01)/sizeof(ixCRT01[0]), 0, 0 }, + { "ixCRT02", REG_SMC, 0x0002, 0, &ixCRT02[0], sizeof(ixCRT02)/sizeof(ixCRT02[0]), 0, 0 }, + { "ixCRT03", REG_SMC, 0x0003, 0, &ixCRT03[0], sizeof(ixCRT03)/sizeof(ixCRT03[0]), 0, 0 }, + { "ixCRT04", REG_SMC, 0x0004, 0, &ixCRT04[0], sizeof(ixCRT04)/sizeof(ixCRT04[0]), 0, 0 }, + { "ixCRT05", REG_SMC, 0x0005, 0, &ixCRT05[0], sizeof(ixCRT05)/sizeof(ixCRT05[0]), 0, 0 }, + { "ixCRT06", REG_SMC, 0x0006, 0, &ixCRT06[0], sizeof(ixCRT06)/sizeof(ixCRT06[0]), 0, 0 }, + { "ixCRT07", REG_SMC, 0x0007, 0, &ixCRT07[0], sizeof(ixCRT07)/sizeof(ixCRT07[0]), 0, 0 }, + { "ixCRT08", REG_SMC, 0x0008, 0, &ixCRT08[0], sizeof(ixCRT08)/sizeof(ixCRT08[0]), 0, 0 }, + { "ixCRT09", REG_SMC, 0x0009, 0, &ixCRT09[0], sizeof(ixCRT09)/sizeof(ixCRT09[0]), 0, 0 }, + { "ixCRT0A", REG_SMC, 0x000a, 0, &ixCRT0A[0], sizeof(ixCRT0A)/sizeof(ixCRT0A[0]), 0, 0 }, + { "ixCRT0B", REG_SMC, 0x000b, 0, &ixCRT0B[0], sizeof(ixCRT0B)/sizeof(ixCRT0B[0]), 0, 0 }, + { "ixCRT0C", REG_SMC, 0x000c, 0, &ixCRT0C[0], sizeof(ixCRT0C)/sizeof(ixCRT0C[0]), 0, 0 }, + { "ixCRT0D", REG_SMC, 0x000d, 0, &ixCRT0D[0], sizeof(ixCRT0D)/sizeof(ixCRT0D[0]), 0, 0 }, + { "ixCRT0E", REG_SMC, 0x000e, 0, &ixCRT0E[0], sizeof(ixCRT0E)/sizeof(ixCRT0E[0]), 0, 0 }, + { "ixCRT0F", REG_SMC, 0x000f, 0, &ixCRT0F[0], sizeof(ixCRT0F)/sizeof(ixCRT0F[0]), 0, 0 }, + { "ixCRT10", REG_SMC, 0x0010, 0, &ixCRT10[0], sizeof(ixCRT10)/sizeof(ixCRT10[0]), 0, 0 }, + { "ixCRT11", REG_SMC, 0x0011, 0, &ixCRT11[0], sizeof(ixCRT11)/sizeof(ixCRT11[0]), 0, 0 }, + { "ixCRT12", REG_SMC, 0x0012, 0, &ixCRT12[0], sizeof(ixCRT12)/sizeof(ixCRT12[0]), 0, 0 }, + { "ixCRT13", REG_SMC, 0x0013, 0, &ixCRT13[0], sizeof(ixCRT13)/sizeof(ixCRT13[0]), 0, 0 }, + { "ixCRT14", REG_SMC, 0x0014, 0, &ixCRT14[0], sizeof(ixCRT14)/sizeof(ixCRT14[0]), 0, 0 }, + { "ixCRT15", REG_SMC, 0x0015, 0, &ixCRT15[0], sizeof(ixCRT15)/sizeof(ixCRT15[0]), 0, 0 }, + { "ixCRT16", REG_SMC, 0x0016, 0, &ixCRT16[0], sizeof(ixCRT16)/sizeof(ixCRT16[0]), 0, 0 }, + { "ixCRT17", REG_SMC, 0x0017, 0, &ixCRT17[0], sizeof(ixCRT17)/sizeof(ixCRT17[0]), 0, 0 }, + { "ixCRT18", REG_SMC, 0x0018, 0, &ixCRT18[0], sizeof(ixCRT18)/sizeof(ixCRT18[0]), 0, 0 }, + { "ixCRT1E", REG_SMC, 0x001e, 0, &ixCRT1E[0], sizeof(ixCRT1E)/sizeof(ixCRT1E[0]), 0, 0 }, + { "ixCRT1F", REG_SMC, 0x001f, 0, &ixCRT1F[0], sizeof(ixCRT1F)/sizeof(ixCRT1F[0]), 0, 0 }, + { "ixCRT22", REG_SMC, 0x0022, 0, &ixCRT22[0], sizeof(ixCRT22)/sizeof(ixCRT22[0]), 0, 0 }, + { "ixGRA00", REG_SMC, 0x0000, 0, &ixGRA00[0], sizeof(ixGRA00)/sizeof(ixGRA00[0]), 0, 0 }, + { "ixGRA01", REG_SMC, 0x0001, 0, &ixGRA01[0], sizeof(ixGRA01)/sizeof(ixGRA01[0]), 0, 0 }, + { "ixGRA02", REG_SMC, 0x0002, 0, &ixGRA02[0], sizeof(ixGRA02)/sizeof(ixGRA02[0]), 0, 0 }, + { "ixGRA03", REG_SMC, 0x0003, 0, &ixGRA03[0], sizeof(ixGRA03)/sizeof(ixGRA03[0]), 0, 0 }, + { "ixGRA04", REG_SMC, 0x0004, 0, &ixGRA04[0], sizeof(ixGRA04)/sizeof(ixGRA04[0]), 0, 0 }, + { "ixGRA05", REG_SMC, 0x0005, 0, &ixGRA05[0], sizeof(ixGRA05)/sizeof(ixGRA05[0]), 0, 0 }, + { "ixGRA06", REG_SMC, 0x0006, 0, &ixGRA06[0], sizeof(ixGRA06)/sizeof(ixGRA06[0]), 0, 0 }, + { "ixGRA07", REG_SMC, 0x0007, 0, &ixGRA07[0], sizeof(ixGRA07)/sizeof(ixGRA07[0]), 0, 0 }, + { "ixGRA08", REG_SMC, 0x0008, 0, &ixGRA08[0], sizeof(ixGRA08)/sizeof(ixGRA08[0]), 0, 0 }, + { "ixATTR00", REG_SMC, 0x0000, 0, &ixATTR00[0], sizeof(ixATTR00)/sizeof(ixATTR00[0]), 0, 0 }, + { "ixATTR01", REG_SMC, 0x0001, 0, &ixATTR01[0], sizeof(ixATTR01)/sizeof(ixATTR01[0]), 0, 0 }, + { "ixATTR02", REG_SMC, 0x0002, 0, &ixATTR02[0], sizeof(ixATTR02)/sizeof(ixATTR02[0]), 0, 0 }, + { "ixATTR03", REG_SMC, 0x0003, 0, &ixATTR03[0], sizeof(ixATTR03)/sizeof(ixATTR03[0]), 0, 0 }, + { "ixATTR04", REG_SMC, 0x0004, 0, &ixATTR04[0], sizeof(ixATTR04)/sizeof(ixATTR04[0]), 0, 0 }, + { "ixATTR05", REG_SMC, 0x0005, 0, &ixATTR05[0], sizeof(ixATTR05)/sizeof(ixATTR05[0]), 0, 0 }, + { "ixATTR06", REG_SMC, 0x0006, 0, &ixATTR06[0], sizeof(ixATTR06)/sizeof(ixATTR06[0]), 0, 0 }, + { "ixATTR07", REG_SMC, 0x0007, 0, &ixATTR07[0], sizeof(ixATTR07)/sizeof(ixATTR07[0]), 0, 0 }, + { "ixATTR08", REG_SMC, 0x0008, 0, &ixATTR08[0], sizeof(ixATTR08)/sizeof(ixATTR08[0]), 0, 0 }, + { "ixATTR09", REG_SMC, 0x0009, 0, &ixATTR09[0], sizeof(ixATTR09)/sizeof(ixATTR09[0]), 0, 0 }, + { "ixATTR0A", REG_SMC, 0x000a, 0, &ixATTR0A[0], sizeof(ixATTR0A)/sizeof(ixATTR0A[0]), 0, 0 }, + { "ixATTR0B", REG_SMC, 0x000b, 0, &ixATTR0B[0], sizeof(ixATTR0B)/sizeof(ixATTR0B[0]), 0, 0 }, + { "ixATTR0C", REG_SMC, 0x000c, 0, &ixATTR0C[0], sizeof(ixATTR0C)/sizeof(ixATTR0C[0]), 0, 0 }, + { "ixATTR0D", REG_SMC, 0x000d, 0, &ixATTR0D[0], sizeof(ixATTR0D)/sizeof(ixATTR0D[0]), 0, 0 }, + { "ixATTR0E", REG_SMC, 0x000e, 0, &ixATTR0E[0], sizeof(ixATTR0E)/sizeof(ixATTR0E[0]), 0, 0 }, + { "ixATTR0F", REG_SMC, 0x000f, 0, &ixATTR0F[0], sizeof(ixATTR0F)/sizeof(ixATTR0F[0]), 0, 0 }, + { "ixATTR10", REG_SMC, 0x0010, 0, &ixATTR10[0], sizeof(ixATTR10)/sizeof(ixATTR10[0]), 0, 0 }, + { "ixATTR11", REG_SMC, 0x0011, 0, &ixATTR11[0], sizeof(ixATTR11)/sizeof(ixATTR11[0]), 0, 0 }, + { "ixATTR12", REG_SMC, 0x0012, 0, &ixATTR12[0], sizeof(ixATTR12)/sizeof(ixATTR12[0]), 0, 0 }, + { "ixATTR13", REG_SMC, 0x0013, 0, &ixATTR13[0], sizeof(ixATTR13)/sizeof(ixATTR13[0]), 0, 0 }, + { "ixATTR14", REG_SMC, 0x0014, 0, &ixATTR14[0], sizeof(ixATTR14)/sizeof(ixATTR14[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT", REG_SMC, 0x2200, 0, &ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT[0], sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT)/sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID", REG_SMC, 0x2706, 0, &ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID[0], sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID)/sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER", REG_SMC, 0x270d, 0, &ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER[0], sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER)/sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2", REG_SMC, 0x270e, 0, &ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2[0], sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2)/sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL", REG_SMC, 0x2724, 0, &ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL[0], sizeof(ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL)/sizeof(ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3", REG_SMC, 0x273e, 0, &ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3[0], sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3)/sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE", REG_SMC, 0x2770, 0, &ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE[0], sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE)/sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING", REG_SMC, 0x2771, 0, &ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING[0], sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING)/sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES", REG_SMC, 0x2f09, 0, &ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0], sizeof(ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES)/sizeof(ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES", REG_SMC, 0x2f0a, 0, &ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[0], sizeof(ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES)/sizeof(ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS", REG_SMC, 0x2f0b, 0, &ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS[0], sizeof(ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS)/sizeof(ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY", REG_SMC, 0x3702, 0, &ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL", REG_SMC, 0x3707, 0, &ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE", REG_SMC, 0x3708, 0, &ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE", REG_SMC, 0x3709, 0, &ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT", REG_SMC, 0x371c, 0, &ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2", REG_SMC, 0x371d, 0, &ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3", REG_SMC, 0x371e, 0, &ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4", REG_SMC, 0x371f, 0, &ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION", REG_SMC, 0x3770, 0, &ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION", REG_SMC, 0x3771, 0, &ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO", REG_SMC, 0x3772, 0, &ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR", REG_SMC, 0x3776, 0, &ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA", REG_SMC, 0x3776, 0, &ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE", REG_SMC, 0x3777, 0, &ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE", REG_SMC, 0x3778, 0, &ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE", REG_SMC, 0x3779, 0, &ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE", REG_SMC, 0x377a, 0, &ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC", REG_SMC, 0x377b, 0, &ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_PIN_CONTROL_HBR", REG_SMC, 0x377c, 0, &ixAZALIA_F2_CODEC_PIN_CONTROL_HBR[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_HBR)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_HBR[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX", REG_SMC, 0x3780, 0, &ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA", REG_SMC, 0x3781, 0, &ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE", REG_SMC, 0x3785, 0, &ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE", REG_SMC, 0x3786, 0, &ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE", REG_SMC, 0x3787, 0, &ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE", REG_SMC, 0x3788, 0, &ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE", REG_SMC, 0x3789, 0, &ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE[0]), 0, 0 }, + { "ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0", REG_SMC, 0x378a, 0, &ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0[0], sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0)/sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0[0]), 0, 0 }, + { "ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1", REG_SMC, 0x378b, 0, &ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1[0], sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1)/sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1[0]), 0, 0 }, + { "ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2", REG_SMC, 0x378c, 0, &ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2[0], sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2)/sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2[0]), 0, 0 }, + { "ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3", REG_SMC, 0x378d, 0, &ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3[0], sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3)/sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3[0]), 0, 0 }, + { "ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4", REG_SMC, 0x378e, 0, &ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4[0], sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4)/sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4[0]), 0, 0 }, + { "ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5", REG_SMC, 0x378f, 0, &ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5[0], sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5)/sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5[0]), 0, 0 }, + { "ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6", REG_SMC, 0x3790, 0, &ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6[0], sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6)/sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6[0]), 0, 0 }, + { "ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7", REG_SMC, 0x3791, 0, &ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7[0], sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7)/sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7[0]), 0, 0 }, + { "ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8", REG_SMC, 0x3792, 0, &ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8[0], sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8)/sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO", REG_SMC, 0x3793, 0, &ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO[0], sizeof(ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO)/sizeof(ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS", REG_SMC, 0x3797, 0, &ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL", REG_SMC, 0x3798, 0, &ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB", REG_SMC, 0x3799, 0, &ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT", REG_SMC, 0x379a, 0, &ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE", REG_SMC, 0x379b, 0, &ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED", REG_SMC, 0x379c, 0, &ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION", REG_SMC, 0x379d, 0, &ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE", REG_SMC, 0x379e, 0, &ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES", REG_SMC, 0x3f09, 0, &ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0], sizeof(ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES)/sizeof(ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES", REG_SMC, 0x3f0c, 0, &ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES[0], sizeof(ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES)/sizeof(ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH", REG_SMC, 0x3f0e, 0, &ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH[0], sizeof(ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH)/sizeof(ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH[0]), 0, 0 }, + { "ixAUDIO_DESCRIPTOR0", REG_SMC, 0x0001, 0, &ixAUDIO_DESCRIPTOR0[0], sizeof(ixAUDIO_DESCRIPTOR0)/sizeof(ixAUDIO_DESCRIPTOR0[0]), 0, 0 }, + { "ixAUDIO_DESCRIPTOR1", REG_SMC, 0x0002, 0, &ixAUDIO_DESCRIPTOR1[0], sizeof(ixAUDIO_DESCRIPTOR1)/sizeof(ixAUDIO_DESCRIPTOR1[0]), 0, 0 }, + { "ixAUDIO_DESCRIPTOR2", REG_SMC, 0x0003, 0, &ixAUDIO_DESCRIPTOR2[0], sizeof(ixAUDIO_DESCRIPTOR2)/sizeof(ixAUDIO_DESCRIPTOR2[0]), 0, 0 }, + { "ixAUDIO_DESCRIPTOR3", REG_SMC, 0x0004, 0, &ixAUDIO_DESCRIPTOR3[0], sizeof(ixAUDIO_DESCRIPTOR3)/sizeof(ixAUDIO_DESCRIPTOR3[0]), 0, 0 }, + { "ixAUDIO_DESCRIPTOR4", REG_SMC, 0x0005, 0, &ixAUDIO_DESCRIPTOR4[0], sizeof(ixAUDIO_DESCRIPTOR4)/sizeof(ixAUDIO_DESCRIPTOR4[0]), 0, 0 }, + { "ixAUDIO_DESCRIPTOR5", REG_SMC, 0x0006, 0, &ixAUDIO_DESCRIPTOR5[0], sizeof(ixAUDIO_DESCRIPTOR5)/sizeof(ixAUDIO_DESCRIPTOR5[0]), 0, 0 }, + { "ixAUDIO_DESCRIPTOR6", REG_SMC, 0x0007, 0, &ixAUDIO_DESCRIPTOR6[0], sizeof(ixAUDIO_DESCRIPTOR6)/sizeof(ixAUDIO_DESCRIPTOR6[0]), 0, 0 }, + { "ixAUDIO_DESCRIPTOR7", REG_SMC, 0x0008, 0, &ixAUDIO_DESCRIPTOR7[0], sizeof(ixAUDIO_DESCRIPTOR7)/sizeof(ixAUDIO_DESCRIPTOR7[0]), 0, 0 }, + { "ixAUDIO_DESCRIPTOR8", REG_SMC, 0x0009, 0, &ixAUDIO_DESCRIPTOR8[0], sizeof(ixAUDIO_DESCRIPTOR8)/sizeof(ixAUDIO_DESCRIPTOR8[0]), 0, 0 }, + { "ixAUDIO_DESCRIPTOR9", REG_SMC, 0x000a, 0, &ixAUDIO_DESCRIPTOR9[0], sizeof(ixAUDIO_DESCRIPTOR9)/sizeof(ixAUDIO_DESCRIPTOR9[0]), 0, 0 }, + { "ixAUDIO_DESCRIPTOR10", REG_SMC, 0x000b, 0, &ixAUDIO_DESCRIPTOR10[0], sizeof(ixAUDIO_DESCRIPTOR10)/sizeof(ixAUDIO_DESCRIPTOR10[0]), 0, 0 }, + { "ixAUDIO_DESCRIPTOR11", REG_SMC, 0x000c, 0, &ixAUDIO_DESCRIPTOR11[0], sizeof(ixAUDIO_DESCRIPTOR11)/sizeof(ixAUDIO_DESCRIPTOR11[0]), 0, 0 }, + { "ixAUDIO_DESCRIPTOR12", REG_SMC, 0x000d, 0, &ixAUDIO_DESCRIPTOR12[0], sizeof(ixAUDIO_DESCRIPTOR12)/sizeof(ixAUDIO_DESCRIPTOR12[0]), 0, 0 }, + { "ixAUDIO_DESCRIPTOR13", REG_SMC, 0x000e, 0, &ixAUDIO_DESCRIPTOR13[0], sizeof(ixAUDIO_DESCRIPTOR13)/sizeof(ixAUDIO_DESCRIPTOR13[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID", REG_SMC, 0x0000, 0, &ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID", REG_SMC, 0x0001, 0, &ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN", REG_SMC, 0x0002, 0, &ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0", REG_SMC, 0x0003, 0, &ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1", REG_SMC, 0x0004, 0, &ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1[0]), 0, 0 }, + { "ixSINK_DESCRIPTION0", REG_SMC, 0x0005, 0, &ixSINK_DESCRIPTION0[0], sizeof(ixSINK_DESCRIPTION0)/sizeof(ixSINK_DESCRIPTION0[0]), 0, 0 }, + { "ixSINK_DESCRIPTION1", REG_SMC, 0x0006, 0, &ixSINK_DESCRIPTION1[0], sizeof(ixSINK_DESCRIPTION1)/sizeof(ixSINK_DESCRIPTION1[0]), 0, 0 }, + { "ixSINK_DESCRIPTION2", REG_SMC, 0x0007, 0, &ixSINK_DESCRIPTION2[0], sizeof(ixSINK_DESCRIPTION2)/sizeof(ixSINK_DESCRIPTION2[0]), 0, 0 }, + { "ixSINK_DESCRIPTION3", REG_SMC, 0x0008, 0, &ixSINK_DESCRIPTION3[0], sizeof(ixSINK_DESCRIPTION3)/sizeof(ixSINK_DESCRIPTION3[0]), 0, 0 }, + { "ixSINK_DESCRIPTION4", REG_SMC, 0x0009, 0, &ixSINK_DESCRIPTION4[0], sizeof(ixSINK_DESCRIPTION4)/sizeof(ixSINK_DESCRIPTION4[0]), 0, 0 }, + { "ixSINK_DESCRIPTION5", REG_SMC, 0x000a, 0, &ixSINK_DESCRIPTION5[0], sizeof(ixSINK_DESCRIPTION5)/sizeof(ixSINK_DESCRIPTION5[0]), 0, 0 }, + { "ixSINK_DESCRIPTION6", REG_SMC, 0x000b, 0, &ixSINK_DESCRIPTION6[0], sizeof(ixSINK_DESCRIPTION6)/sizeof(ixSINK_DESCRIPTION6[0]), 0, 0 }, + { "ixSINK_DESCRIPTION7", REG_SMC, 0x000c, 0, &ixSINK_DESCRIPTION7[0], sizeof(ixSINK_DESCRIPTION7)/sizeof(ixSINK_DESCRIPTION7[0]), 0, 0 }, + { "ixSINK_DESCRIPTION8", REG_SMC, 0x000d, 0, &ixSINK_DESCRIPTION8[0], sizeof(ixSINK_DESCRIPTION8)/sizeof(ixSINK_DESCRIPTION8[0]), 0, 0 }, + { "ixSINK_DESCRIPTION9", REG_SMC, 0x000e, 0, &ixSINK_DESCRIPTION9[0], sizeof(ixSINK_DESCRIPTION9)/sizeof(ixSINK_DESCRIPTION9[0]), 0, 0 }, + { "ixSINK_DESCRIPTION10", REG_SMC, 0x000f, 0, &ixSINK_DESCRIPTION10[0], sizeof(ixSINK_DESCRIPTION10)/sizeof(ixSINK_DESCRIPTION10[0]), 0, 0 }, + { "ixSINK_DESCRIPTION11", REG_SMC, 0x0010, 0, &ixSINK_DESCRIPTION11[0], sizeof(ixSINK_DESCRIPTION11)/sizeof(ixSINK_DESCRIPTION11[0]), 0, 0 }, + { "ixSINK_DESCRIPTION12", REG_SMC, 0x0011, 0, &ixSINK_DESCRIPTION12[0], sizeof(ixSINK_DESCRIPTION12)/sizeof(ixSINK_DESCRIPTION12[0]), 0, 0 }, + { "ixSINK_DESCRIPTION13", REG_SMC, 0x0012, 0, &ixSINK_DESCRIPTION13[0], sizeof(ixSINK_DESCRIPTION13)/sizeof(ixSINK_DESCRIPTION13[0]), 0, 0 }, + { "ixSINK_DESCRIPTION14", REG_SMC, 0x0013, 0, &ixSINK_DESCRIPTION14[0], sizeof(ixSINK_DESCRIPTION14)/sizeof(ixSINK_DESCRIPTION14[0]), 0, 0 }, + { "ixSINK_DESCRIPTION15", REG_SMC, 0x0014, 0, &ixSINK_DESCRIPTION15[0], sizeof(ixSINK_DESCRIPTION15)/sizeof(ixSINK_DESCRIPTION15[0]), 0, 0 }, + { "ixSINK_DESCRIPTION16", REG_SMC, 0x0015, 0, &ixSINK_DESCRIPTION16[0], sizeof(ixSINK_DESCRIPTION16)/sizeof(ixSINK_DESCRIPTION16[0]), 0, 0 }, + { "ixSINK_DESCRIPTION17", REG_SMC, 0x0016, 0, &ixSINK_DESCRIPTION17[0], sizeof(ixSINK_DESCRIPTION17)/sizeof(ixSINK_DESCRIPTION17[0]), 0, 0 }, + { "ixAZALIA_INPUT_CRC0_CHANNEL0", REG_SMC, 0x0000, 0, &ixAZALIA_INPUT_CRC0_CHANNEL0[0], sizeof(ixAZALIA_INPUT_CRC0_CHANNEL0)/sizeof(ixAZALIA_INPUT_CRC0_CHANNEL0[0]), 0, 0 }, + { "ixAZALIA_INPUT_CRC0_CHANNEL1", REG_SMC, 0x0001, 0, &ixAZALIA_INPUT_CRC0_CHANNEL1[0], sizeof(ixAZALIA_INPUT_CRC0_CHANNEL1)/sizeof(ixAZALIA_INPUT_CRC0_CHANNEL1[0]), 0, 0 }, + { "ixAZALIA_INPUT_CRC0_CHANNEL2", REG_SMC, 0x0002, 0, &ixAZALIA_INPUT_CRC0_CHANNEL2[0], sizeof(ixAZALIA_INPUT_CRC0_CHANNEL2)/sizeof(ixAZALIA_INPUT_CRC0_CHANNEL2[0]), 0, 0 }, + { "ixAZALIA_INPUT_CRC0_CHANNEL3", REG_SMC, 0x0003, 0, &ixAZALIA_INPUT_CRC0_CHANNEL3[0], sizeof(ixAZALIA_INPUT_CRC0_CHANNEL3)/sizeof(ixAZALIA_INPUT_CRC0_CHANNEL3[0]), 0, 0 }, + { "ixAZALIA_INPUT_CRC0_CHANNEL4", REG_SMC, 0x0004, 0, &ixAZALIA_INPUT_CRC0_CHANNEL4[0], sizeof(ixAZALIA_INPUT_CRC0_CHANNEL4)/sizeof(ixAZALIA_INPUT_CRC0_CHANNEL4[0]), 0, 0 }, + { "ixAZALIA_INPUT_CRC0_CHANNEL5", REG_SMC, 0x0005, 0, &ixAZALIA_INPUT_CRC0_CHANNEL5[0], sizeof(ixAZALIA_INPUT_CRC0_CHANNEL5)/sizeof(ixAZALIA_INPUT_CRC0_CHANNEL5[0]), 0, 0 }, + { "ixAZALIA_INPUT_CRC0_CHANNEL6", REG_SMC, 0x0006, 0, &ixAZALIA_INPUT_CRC0_CHANNEL6[0], sizeof(ixAZALIA_INPUT_CRC0_CHANNEL6)/sizeof(ixAZALIA_INPUT_CRC0_CHANNEL6[0]), 0, 0 }, + { "ixAZALIA_INPUT_CRC0_CHANNEL7", REG_SMC, 0x0007, 0, &ixAZALIA_INPUT_CRC0_CHANNEL7[0], sizeof(ixAZALIA_INPUT_CRC0_CHANNEL7)/sizeof(ixAZALIA_INPUT_CRC0_CHANNEL7[0]), 0, 0 }, + { "ixAZALIA_INPUT_CRC1_CHANNEL0", REG_SMC, 0x0000, 0, &ixAZALIA_INPUT_CRC1_CHANNEL0[0], sizeof(ixAZALIA_INPUT_CRC1_CHANNEL0)/sizeof(ixAZALIA_INPUT_CRC1_CHANNEL0[0]), 0, 0 }, + { "ixAZALIA_INPUT_CRC1_CHANNEL1", REG_SMC, 0x0001, 0, &ixAZALIA_INPUT_CRC1_CHANNEL1[0], sizeof(ixAZALIA_INPUT_CRC1_CHANNEL1)/sizeof(ixAZALIA_INPUT_CRC1_CHANNEL1[0]), 0, 0 }, + { "ixAZALIA_INPUT_CRC1_CHANNEL2", REG_SMC, 0x0002, 0, &ixAZALIA_INPUT_CRC1_CHANNEL2[0], sizeof(ixAZALIA_INPUT_CRC1_CHANNEL2)/sizeof(ixAZALIA_INPUT_CRC1_CHANNEL2[0]), 0, 0 }, + { "ixAZALIA_INPUT_CRC1_CHANNEL3", REG_SMC, 0x0003, 0, &ixAZALIA_INPUT_CRC1_CHANNEL3[0], sizeof(ixAZALIA_INPUT_CRC1_CHANNEL3)/sizeof(ixAZALIA_INPUT_CRC1_CHANNEL3[0]), 0, 0 }, + { "ixAZALIA_INPUT_CRC1_CHANNEL4", REG_SMC, 0x0004, 0, &ixAZALIA_INPUT_CRC1_CHANNEL4[0], sizeof(ixAZALIA_INPUT_CRC1_CHANNEL4)/sizeof(ixAZALIA_INPUT_CRC1_CHANNEL4[0]), 0, 0 }, + { "ixAZALIA_INPUT_CRC1_CHANNEL5", REG_SMC, 0x0005, 0, &ixAZALIA_INPUT_CRC1_CHANNEL5[0], sizeof(ixAZALIA_INPUT_CRC1_CHANNEL5)/sizeof(ixAZALIA_INPUT_CRC1_CHANNEL5[0]), 0, 0 }, + { "ixAZALIA_INPUT_CRC1_CHANNEL6", REG_SMC, 0x0006, 0, &ixAZALIA_INPUT_CRC1_CHANNEL6[0], sizeof(ixAZALIA_INPUT_CRC1_CHANNEL6)/sizeof(ixAZALIA_INPUT_CRC1_CHANNEL6[0]), 0, 0 }, + { "ixAZALIA_INPUT_CRC1_CHANNEL7", REG_SMC, 0x0007, 0, &ixAZALIA_INPUT_CRC1_CHANNEL7[0], sizeof(ixAZALIA_INPUT_CRC1_CHANNEL7)/sizeof(ixAZALIA_INPUT_CRC1_CHANNEL7[0]), 0, 0 }, + { "ixAZALIA_CRC0_CHANNEL0", REG_SMC, 0x0000, 0, &ixAZALIA_CRC0_CHANNEL0[0], sizeof(ixAZALIA_CRC0_CHANNEL0)/sizeof(ixAZALIA_CRC0_CHANNEL0[0]), 0, 0 }, + { "ixAZALIA_CRC0_CHANNEL1", REG_SMC, 0x0001, 0, &ixAZALIA_CRC0_CHANNEL1[0], sizeof(ixAZALIA_CRC0_CHANNEL1)/sizeof(ixAZALIA_CRC0_CHANNEL1[0]), 0, 0 }, + { "ixAZALIA_CRC0_CHANNEL2", REG_SMC, 0x0002, 0, &ixAZALIA_CRC0_CHANNEL2[0], sizeof(ixAZALIA_CRC0_CHANNEL2)/sizeof(ixAZALIA_CRC0_CHANNEL2[0]), 0, 0 }, + { "ixAZALIA_CRC0_CHANNEL3", REG_SMC, 0x0003, 0, &ixAZALIA_CRC0_CHANNEL3[0], sizeof(ixAZALIA_CRC0_CHANNEL3)/sizeof(ixAZALIA_CRC0_CHANNEL3[0]), 0, 0 }, + { "ixAZALIA_CRC0_CHANNEL4", REG_SMC, 0x0004, 0, &ixAZALIA_CRC0_CHANNEL4[0], sizeof(ixAZALIA_CRC0_CHANNEL4)/sizeof(ixAZALIA_CRC0_CHANNEL4[0]), 0, 0 }, + { "ixAZALIA_CRC0_CHANNEL5", REG_SMC, 0x0005, 0, &ixAZALIA_CRC0_CHANNEL5[0], sizeof(ixAZALIA_CRC0_CHANNEL5)/sizeof(ixAZALIA_CRC0_CHANNEL5[0]), 0, 0 }, + { "ixAZALIA_CRC0_CHANNEL6", REG_SMC, 0x0006, 0, &ixAZALIA_CRC0_CHANNEL6[0], sizeof(ixAZALIA_CRC0_CHANNEL6)/sizeof(ixAZALIA_CRC0_CHANNEL6[0]), 0, 0 }, + { "ixAZALIA_CRC0_CHANNEL7", REG_SMC, 0x0007, 0, &ixAZALIA_CRC0_CHANNEL7[0], sizeof(ixAZALIA_CRC0_CHANNEL7)/sizeof(ixAZALIA_CRC0_CHANNEL7[0]), 0, 0 }, + { "ixAZALIA_CRC1_CHANNEL0", REG_SMC, 0x0000, 0, &ixAZALIA_CRC1_CHANNEL0[0], sizeof(ixAZALIA_CRC1_CHANNEL0)/sizeof(ixAZALIA_CRC1_CHANNEL0[0]), 0, 0 }, + { "ixAZALIA_CRC1_CHANNEL1", REG_SMC, 0x0001, 0, &ixAZALIA_CRC1_CHANNEL1[0], sizeof(ixAZALIA_CRC1_CHANNEL1)/sizeof(ixAZALIA_CRC1_CHANNEL1[0]), 0, 0 }, + { "ixAZALIA_CRC1_CHANNEL2", REG_SMC, 0x0002, 0, &ixAZALIA_CRC1_CHANNEL2[0], sizeof(ixAZALIA_CRC1_CHANNEL2)/sizeof(ixAZALIA_CRC1_CHANNEL2[0]), 0, 0 }, + { "ixAZALIA_CRC1_CHANNEL3", REG_SMC, 0x0003, 0, &ixAZALIA_CRC1_CHANNEL3[0], sizeof(ixAZALIA_CRC1_CHANNEL3)/sizeof(ixAZALIA_CRC1_CHANNEL3[0]), 0, 0 }, + { "ixAZALIA_CRC1_CHANNEL4", REG_SMC, 0x0004, 0, &ixAZALIA_CRC1_CHANNEL4[0], sizeof(ixAZALIA_CRC1_CHANNEL4)/sizeof(ixAZALIA_CRC1_CHANNEL4[0]), 0, 0 }, + { "ixAZALIA_CRC1_CHANNEL5", REG_SMC, 0x0005, 0, &ixAZALIA_CRC1_CHANNEL5[0], sizeof(ixAZALIA_CRC1_CHANNEL5)/sizeof(ixAZALIA_CRC1_CHANNEL5[0]), 0, 0 }, + { "ixAZALIA_CRC1_CHANNEL6", REG_SMC, 0x0006, 0, &ixAZALIA_CRC1_CHANNEL6[0], sizeof(ixAZALIA_CRC1_CHANNEL6)/sizeof(ixAZALIA_CRC1_CHANNEL6[0]), 0, 0 }, + { "ixAZALIA_CRC1_CHANNEL7", REG_SMC, 0x0007, 0, &ixAZALIA_CRC1_CHANNEL7[0], sizeof(ixAZALIA_CRC1_CHANNEL7)/sizeof(ixAZALIA_CRC1_CHANNEL7[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT", REG_SMC, 0x6200, 0, &ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT[0], sizeof(ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT)/sizeof(ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID", REG_SMC, 0x6706, 0, &ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID[0], sizeof(ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID)/sizeof(ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER", REG_SMC, 0x670d, 0, &ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER[0], sizeof(ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER)/sizeof(ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES", REG_SMC, 0x6f09, 0, &ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0], sizeof(ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES)/sizeof(ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES", REG_SMC, 0x6f0a, 0, &ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[0], sizeof(ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES)/sizeof(ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS", REG_SMC, 0x6f0b, 0, &ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS[0], sizeof(ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS)/sizeof(ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL", REG_SMC, 0x7707, 0, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE", REG_SMC, 0x7708, 0, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE", REG_SMC, 0x7709, 0, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT", REG_SMC, 0x771c, 0, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2", REG_SMC, 0x771d, 0, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3", REG_SMC, 0x771e, 0, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4", REG_SMC, 0x771f, 0, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION", REG_SMC, 0x7771, 0, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE", REG_SMC, 0x7777, 0, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE", REG_SMC, 0x7778, 0, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE", REG_SMC, 0x7779, 0, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE", REG_SMC, 0x777a, 0, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR", REG_SMC, 0x777c, 0, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE", REG_SMC, 0x7785, 0, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE", REG_SMC, 0x7786, 0, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE", REG_SMC, 0x7787, 0, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE", REG_SMC, 0x7788, 0, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL", REG_SMC, 0x7798, 0, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB", REG_SMC, 0x7799, 0, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT", REG_SMC, 0x779a, 0, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL", REG_SMC, 0x779b, 0, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME", REG_SMC, 0x779c, 0, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L", REG_SMC, 0x779d, 0, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H", REG_SMC, 0x779e, 0, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES", REG_SMC, 0x7f09, 0, &ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES", REG_SMC, 0x7f0c, 0, &ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID", REG_SMC, 0x0f00, 0, &ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID[0], sizeof(ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID)/sizeof(ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID", REG_SMC, 0x0f02, 0, &ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID[0], sizeof(ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID)/sizeof(ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT", REG_SMC, 0x0f04, 0, &ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT[0], sizeof(ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT)/sizeof(ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE", REG_SMC, 0x1705, 0, &ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID", REG_SMC, 0x1720, 0, &ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2", REG_SMC, 0x1721, 0, &ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3", REG_SMC, 0x1722, 0, &ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4", REG_SMC, 0x1723, 0, &ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION", REG_SMC, 0x1770, 0, &ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET", REG_SMC, 0x17ff, 0, &ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT", REG_SMC, 0x1f04, 0, &ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE", REG_SMC, 0x1f05, 0, &ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES", REG_SMC, 0x1f0a, 0, &ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS", REG_SMC, 0x1f0b, 0, &ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS[0]), 0, 0 }, + { "ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES", REG_SMC, 0x1f0f, 0, &ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES[0]), 0, 0 }, + { "ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL", REG_SMC, 0x0000, 0, &ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL[0], sizeof(ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL)/sizeof(ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL[0]), 0, 0 }, + { "ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL", REG_SMC, 0x0001, 0, &ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL[0], sizeof(ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL)/sizeof(ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL[0]), 0, 0 }, + { "ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT", REG_SMC, 0x0002, 0, &ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT[0], sizeof(ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT)/sizeof(ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT[0]), 0, 0 }, + { "ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT", REG_SMC, 0x0003, 0, &ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT[0], sizeof(ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT)/sizeof(ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT[0]), 0, 0 }, + { "ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT", REG_SMC, 0x0004, 0, &ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT[0], sizeof(ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT)/sizeof(ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT[0]), 0, 0 }, + { "ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL", REG_SMC, 0x0000, 0, &ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL[0], sizeof(ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL)/sizeof(ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL[0]), 0, 0 }, + { "ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL", REG_SMC, 0x0001, 0, &ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL[0], sizeof(ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL)/sizeof(ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL[0]), 0, 0 }, + { "ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT", REG_SMC, 0x0002, 0, &ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT[0], sizeof(ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT)/sizeof(ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT[0]), 0, 0 }, + { "ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT", REG_SMC, 0x0003, 0, &ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT[0], sizeof(ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT)/sizeof(ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT[0]), 0, 0 }, + { "ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT", REG_SMC, 0x0004, 0, &ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT[0], sizeof(ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT)/sizeof(ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT[0]), 0, 0 }, + { "ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL", REG_SMC, 0x0000, 0, &ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL[0], sizeof(ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL)/sizeof(ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL[0]), 0, 0 }, + { "ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL", REG_SMC, 0x0001, 0, &ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL[0], sizeof(ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL)/sizeof(ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL[0]), 0, 0 }, + { "ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT", REG_SMC, 0x0002, 0, &ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT[0], sizeof(ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT)/sizeof(ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT[0]), 0, 0 }, + { "ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT", REG_SMC, 0x0003, 0, &ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT[0], sizeof(ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT)/sizeof(ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT[0]), 0, 0 }, + { "ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT", REG_SMC, 0x0004, 0, &ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT[0], sizeof(ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT)/sizeof(ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT[0]), 0, 0 }, + { "ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL", REG_SMC, 0x0000, 0, &ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL[0], sizeof(ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL)/sizeof(ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL[0]), 0, 0 }, + { "ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL", REG_SMC, 0x0001, 0, &ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL[0], sizeof(ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL)/sizeof(ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL[0]), 0, 0 }, + { "ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT", REG_SMC, 0x0002, 0, &ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT[0], sizeof(ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT)/sizeof(ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT[0]), 0, 0 }, + { "ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT", REG_SMC, 0x0003, 0, &ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT[0], sizeof(ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT)/sizeof(ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT[0]), 0, 0 }, + { "ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT", REG_SMC, 0x0004, 0, &ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT[0], sizeof(ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT)/sizeof(ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT[0]), 0, 0 }, + { "ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL", REG_SMC, 0x0000, 0, &ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL[0], sizeof(ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL)/sizeof(ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL[0]), 0, 0 }, + { "ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL", REG_SMC, 0x0001, 0, &ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL[0], sizeof(ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL)/sizeof(ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL[0]), 0, 0 }, + { "ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT", REG_SMC, 0x0002, 0, &ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT[0], sizeof(ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT)/sizeof(ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT[0]), 0, 0 }, + { "ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT", REG_SMC, 0x0003, 0, &ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT[0], sizeof(ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT)/sizeof(ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT[0]), 0, 0 }, + { "ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT", REG_SMC, 0x0004, 0, &ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT[0], sizeof(ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT)/sizeof(ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT[0]), 0, 0 }, + { "ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL", REG_SMC, 0x0000, 0, &ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL[0], sizeof(ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL)/sizeof(ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL[0]), 0, 0 }, + { "ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL", REG_SMC, 0x0001, 0, &ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL[0], sizeof(ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL)/sizeof(ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL[0]), 0, 0 }, + { "ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT", REG_SMC, 0x0002, 0, &ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT[0], sizeof(ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT)/sizeof(ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT[0]), 0, 0 }, + { "ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT", REG_SMC, 0x0003, 0, &ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT[0], sizeof(ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT)/sizeof(ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT[0]), 0, 0 }, + { "ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT", REG_SMC, 0x0004, 0, &ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT[0], sizeof(ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT)/sizeof(ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT[0]), 0, 0 }, + { "ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL", REG_SMC, 0x0000, 0, &ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL[0], sizeof(ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL)/sizeof(ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL[0]), 0, 0 }, + { "ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL", REG_SMC, 0x0001, 0, &ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL[0], sizeof(ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL)/sizeof(ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL[0]), 0, 0 }, + { "ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT", REG_SMC, 0x0002, 0, &ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT[0], sizeof(ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT)/sizeof(ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT[0]), 0, 0 }, + { "ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT", REG_SMC, 0x0003, 0, &ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT[0], sizeof(ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT)/sizeof(ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT[0]), 0, 0 }, + { "ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT", REG_SMC, 0x0004, 0, &ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT[0], sizeof(ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT)/sizeof(ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT[0]), 0, 0 }, + { "ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL", REG_SMC, 0x0000, 0, &ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL[0], sizeof(ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL)/sizeof(ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL[0]), 0, 0 }, + { "ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL", REG_SMC, 0x0001, 0, &ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL[0], sizeof(ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL)/sizeof(ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL[0]), 0, 0 }, + { "ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT", REG_SMC, 0x0002, 0, &ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT[0], sizeof(ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT)/sizeof(ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT[0]), 0, 0 }, + { "ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT", REG_SMC, 0x0003, 0, &ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT[0], sizeof(ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT)/sizeof(ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT[0]), 0, 0 }, + { "ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT", REG_SMC, 0x0004, 0, &ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT[0], sizeof(ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT)/sizeof(ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT[0]), 0, 0 }, + { "ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL", REG_SMC, 0x0000, 0, &ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL[0], sizeof(ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL)/sizeof(ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL[0]), 0, 0 }, + { "ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL", REG_SMC, 0x0001, 0, &ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL[0], sizeof(ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL)/sizeof(ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL[0]), 0, 0 }, + { "ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT", REG_SMC, 0x0002, 0, &ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT[0], sizeof(ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT)/sizeof(ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT[0]), 0, 0 }, + { "ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT", REG_SMC, 0x0003, 0, &ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT[0], sizeof(ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT)/sizeof(ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT[0]), 0, 0 }, + { "ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT", REG_SMC, 0x0004, 0, &ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT[0], sizeof(ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT)/sizeof(ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT[0]), 0, 0 }, + { "ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL", REG_SMC, 0x0000, 0, &ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL[0], sizeof(ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL)/sizeof(ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL[0]), 0, 0 }, + { "ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL", REG_SMC, 0x0001, 0, &ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL[0], sizeof(ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL)/sizeof(ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL[0]), 0, 0 }, + { "ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT", REG_SMC, 0x0002, 0, &ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT[0], sizeof(ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT)/sizeof(ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT[0]), 0, 0 }, + { "ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT", REG_SMC, 0x0003, 0, &ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT[0], sizeof(ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT)/sizeof(ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT[0]), 0, 0 }, + { "ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT", REG_SMC, 0x0004, 0, &ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT[0], sizeof(ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT)/sizeof(ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT[0]), 0, 0 }, + { "ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL", REG_SMC, 0x0000, 0, &ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL[0], sizeof(ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL)/sizeof(ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL[0]), 0, 0 }, + { "ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL", REG_SMC, 0x0001, 0, &ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL[0], sizeof(ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL)/sizeof(ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL[0]), 0, 0 }, + { "ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT", REG_SMC, 0x0002, 0, &ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT[0], sizeof(ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT)/sizeof(ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT[0]), 0, 0 }, + { "ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT", REG_SMC, 0x0003, 0, &ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT[0], sizeof(ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT)/sizeof(ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT[0]), 0, 0 }, + { "ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT", REG_SMC, 0x0004, 0, &ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT[0], sizeof(ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT)/sizeof(ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT[0]), 0, 0 }, + { "ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL", REG_SMC, 0x0000, 0, &ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL[0], sizeof(ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL)/sizeof(ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL[0]), 0, 0 }, + { "ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL", REG_SMC, 0x0001, 0, &ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL[0], sizeof(ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL)/sizeof(ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL[0]), 0, 0 }, + { "ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT", REG_SMC, 0x0002, 0, &ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT[0], sizeof(ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT)/sizeof(ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT[0]), 0, 0 }, + { "ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT", REG_SMC, 0x0003, 0, &ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT[0], sizeof(ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT)/sizeof(ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT[0]), 0, 0 }, + { "ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT", REG_SMC, 0x0004, 0, &ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT[0], sizeof(ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT)/sizeof(ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT[0]), 0, 0 }, + { "ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL", REG_SMC, 0x0000, 0, &ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL[0], sizeof(ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL)/sizeof(ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL[0]), 0, 0 }, + { "ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL", REG_SMC, 0x0001, 0, &ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL[0], sizeof(ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL)/sizeof(ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL[0]), 0, 0 }, + { "ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT", REG_SMC, 0x0002, 0, &ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT[0], sizeof(ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT)/sizeof(ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT[0]), 0, 0 }, + { "ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT", REG_SMC, 0x0003, 0, &ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT[0], sizeof(ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT)/sizeof(ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT[0]), 0, 0 }, + { "ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT", REG_SMC, 0x0004, 0, &ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT[0], sizeof(ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT)/sizeof(ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT[0]), 0, 0 }, + { "ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL", REG_SMC, 0x0000, 0, &ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL[0], sizeof(ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL)/sizeof(ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL[0]), 0, 0 }, + { "ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL", REG_SMC, 0x0001, 0, &ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL[0], sizeof(ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL)/sizeof(ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL[0]), 0, 0 }, + { "ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT", REG_SMC, 0x0002, 0, &ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT[0], sizeof(ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT)/sizeof(ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT[0]), 0, 0 }, + { "ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT", REG_SMC, 0x0003, 0, &ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT[0], sizeof(ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT)/sizeof(ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT[0]), 0, 0 }, + { "ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT", REG_SMC, 0x0004, 0, &ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT[0], sizeof(ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT)/sizeof(ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT[0]), 0, 0 }, + { "ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL", REG_SMC, 0x0000, 0, &ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL[0], sizeof(ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL)/sizeof(ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL[0]), 0, 0 }, + { "ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL", REG_SMC, 0x0001, 0, &ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL[0], sizeof(ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL)/sizeof(ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL[0]), 0, 0 }, + { "ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT", REG_SMC, 0x0002, 0, &ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT[0], sizeof(ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT)/sizeof(ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT[0]), 0, 0 }, + { "ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT", REG_SMC, 0x0003, 0, &ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT[0], sizeof(ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT)/sizeof(ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT[0]), 0, 0 }, + { "ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT", REG_SMC, 0x0004, 0, &ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT[0], sizeof(ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT)/sizeof(ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT[0]), 0, 0 }, + { "ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL", REG_SMC, 0x0000, 0, &ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL[0], sizeof(ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL)/sizeof(ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL[0]), 0, 0 }, + { "ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL", REG_SMC, 0x0001, 0, &ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL[0], sizeof(ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL)/sizeof(ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL[0]), 0, 0 }, + { "ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT", REG_SMC, 0x0002, 0, &ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT[0], sizeof(ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT)/sizeof(ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT[0]), 0, 0 }, + { "ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT", REG_SMC, 0x0003, 0, &ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT[0], sizeof(ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT)/sizeof(ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT[0]), 0, 0 }, + { "ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT", REG_SMC, 0x0004, 0, &ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT[0], sizeof(ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT)/sizeof(ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES", REG_SMC, 0x0001, 0, &ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT", REG_SMC, 0x0002, 0, &ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID", REG_SMC, 0x0003, 0, &ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER", REG_SMC, 0x0004, 0, &ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS", REG_SMC, 0x0005, 0, &ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES", REG_SMC, 0x0006, 0, &ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL", REG_SMC, 0x0007, 0, &ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE", REG_SMC, 0x0008, 0, &ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING", REG_SMC, 0x0009, 0, &ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA", REG_SMC, 0x000c, 0, &ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN", REG_SMC, 0x000d, 0, &ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX", REG_SMC, 0x000e, 0, &ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES", REG_SMC, 0x0020, 0, &ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES", REG_SMC, 0x0021, 0, &ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE", REG_SMC, 0x0022, 0, &ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE", REG_SMC, 0x0023, 0, &ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL", REG_SMC, 0x0024, 0, &ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER", REG_SMC, 0x0025, 0, &ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0", REG_SMC, 0x0028, 0, &ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1", REG_SMC, 0x0029, 0, &ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2", REG_SMC, 0x002a, 0, &ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3", REG_SMC, 0x002b, 0, &ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4", REG_SMC, 0x002c, 0, &ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5", REG_SMC, 0x002d, 0, &ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6", REG_SMC, 0x002e, 0, &ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7", REG_SMC, 0x002f, 0, &ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8", REG_SMC, 0x0030, 0, &ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9", REG_SMC, 0x0031, 0, &ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10", REG_SMC, 0x0032, 0, &ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11", REG_SMC, 0x0033, 0, &ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12", REG_SMC, 0x0034, 0, &ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13", REG_SMC, 0x0035, 0, &ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE", REG_SMC, 0x0036, 0, &ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC", REG_SMC, 0x0037, 0, &ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR", REG_SMC, 0x0038, 0, &ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0", REG_SMC, 0x003a, 0, &ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1", REG_SMC, 0x003b, 0, &ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2", REG_SMC, 0x003c, 0, &ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3", REG_SMC, 0x003d, 0, &ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4", REG_SMC, 0x003e, 0, &ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5", REG_SMC, 0x003f, 0, &ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6", REG_SMC, 0x0040, 0, &ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7", REG_SMC, 0x0041, 0, &ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8", REG_SMC, 0x0042, 0, &ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL", REG_SMC, 0x0054, 0, &ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE", REG_SMC, 0x0055, 0, &ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT", REG_SMC, 0x0056, 0, &ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2", REG_SMC, 0x0057, 0, &ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE", REG_SMC, 0x0058, 0, &ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0", REG_SMC, 0x0059, 0, &ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1", REG_SMC, 0x005a, 0, &ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2", REG_SMC, 0x005b, 0, &ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3", REG_SMC, 0x005c, 0, &ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4", REG_SMC, 0x005d, 0, &ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5", REG_SMC, 0x005e, 0, &ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6", REG_SMC, 0x005f, 0, &ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7", REG_SMC, 0x0060, 0, &ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8", REG_SMC, 0x0061, 0, &ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO", REG_SMC, 0x0062, 0, &ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS", REG_SMC, 0x0063, 0, &ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL", REG_SMC, 0x0064, 0, &ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB", REG_SMC, 0x0065, 0, &ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT", REG_SMC, 0x0066, 0, &ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE", REG_SMC, 0x0067, 0, &ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED", REG_SMC, 0x0068, 0, &ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION", REG_SMC, 0x0069, 0, &ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE", REG_SMC, 0x006a, 0, &ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS", REG_SMC, 0x006b, 0, &ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS", REG_SMC, 0x006c, 0, &ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS", REG_SMC, 0x006d, 0, &ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS[0]), 0, 0 }, + { "ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS", REG_SMC, 0x006e, 0, &ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS[0], sizeof(ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS)/sizeof(ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES", REG_SMC, 0x0001, 0, &ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT", REG_SMC, 0x0002, 0, &ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID", REG_SMC, 0x0003, 0, &ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER", REG_SMC, 0x0004, 0, &ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS", REG_SMC, 0x0005, 0, &ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES", REG_SMC, 0x0006, 0, &ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL", REG_SMC, 0x0007, 0, &ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE", REG_SMC, 0x0008, 0, &ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING", REG_SMC, 0x0009, 0, &ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA", REG_SMC, 0x000c, 0, &ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN", REG_SMC, 0x000d, 0, &ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX", REG_SMC, 0x000e, 0, &ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES", REG_SMC, 0x0020, 0, &ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES", REG_SMC, 0x0021, 0, &ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE", REG_SMC, 0x0022, 0, &ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE", REG_SMC, 0x0023, 0, &ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL", REG_SMC, 0x0024, 0, &ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER", REG_SMC, 0x0025, 0, &ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0", REG_SMC, 0x0028, 0, &ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1", REG_SMC, 0x0029, 0, &ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2", REG_SMC, 0x002a, 0, &ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3", REG_SMC, 0x002b, 0, &ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4", REG_SMC, 0x002c, 0, &ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5", REG_SMC, 0x002d, 0, &ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6", REG_SMC, 0x002e, 0, &ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7", REG_SMC, 0x002f, 0, &ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8", REG_SMC, 0x0030, 0, &ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9", REG_SMC, 0x0031, 0, &ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10", REG_SMC, 0x0032, 0, &ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11", REG_SMC, 0x0033, 0, &ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12", REG_SMC, 0x0034, 0, &ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13", REG_SMC, 0x0035, 0, &ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE", REG_SMC, 0x0036, 0, &ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC", REG_SMC, 0x0037, 0, &ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR", REG_SMC, 0x0038, 0, &ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0", REG_SMC, 0x003a, 0, &ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1", REG_SMC, 0x003b, 0, &ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2", REG_SMC, 0x003c, 0, &ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3", REG_SMC, 0x003d, 0, &ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4", REG_SMC, 0x003e, 0, &ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5", REG_SMC, 0x003f, 0, &ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6", REG_SMC, 0x0040, 0, &ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7", REG_SMC, 0x0041, 0, &ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8", REG_SMC, 0x0042, 0, &ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL", REG_SMC, 0x0054, 0, &ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE", REG_SMC, 0x0055, 0, &ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT", REG_SMC, 0x0056, 0, &ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2", REG_SMC, 0x0057, 0, &ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE", REG_SMC, 0x0058, 0, &ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0", REG_SMC, 0x0059, 0, &ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1", REG_SMC, 0x005a, 0, &ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2", REG_SMC, 0x005b, 0, &ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3", REG_SMC, 0x005c, 0, &ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4", REG_SMC, 0x005d, 0, &ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5", REG_SMC, 0x005e, 0, &ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6", REG_SMC, 0x005f, 0, &ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7", REG_SMC, 0x0060, 0, &ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8", REG_SMC, 0x0061, 0, &ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO", REG_SMC, 0x0062, 0, &ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS", REG_SMC, 0x0063, 0, &ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL", REG_SMC, 0x0064, 0, &ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB", REG_SMC, 0x0065, 0, &ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT", REG_SMC, 0x0066, 0, &ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE", REG_SMC, 0x0067, 0, &ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED", REG_SMC, 0x0068, 0, &ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION", REG_SMC, 0x0069, 0, &ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE", REG_SMC, 0x006a, 0, &ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS", REG_SMC, 0x006b, 0, &ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS", REG_SMC, 0x006c, 0, &ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS", REG_SMC, 0x006d, 0, &ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS[0]), 0, 0 }, + { "ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS", REG_SMC, 0x006e, 0, &ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS[0], sizeof(ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS)/sizeof(ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES", REG_SMC, 0x0001, 0, &ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT", REG_SMC, 0x0002, 0, &ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID", REG_SMC, 0x0003, 0, &ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER", REG_SMC, 0x0004, 0, &ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS", REG_SMC, 0x0005, 0, &ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES", REG_SMC, 0x0006, 0, &ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL", REG_SMC, 0x0007, 0, &ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE", REG_SMC, 0x0008, 0, &ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING", REG_SMC, 0x0009, 0, &ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA", REG_SMC, 0x000c, 0, &ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN", REG_SMC, 0x000d, 0, &ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX", REG_SMC, 0x000e, 0, &ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES", REG_SMC, 0x0020, 0, &ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES", REG_SMC, 0x0021, 0, &ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE", REG_SMC, 0x0022, 0, &ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE", REG_SMC, 0x0023, 0, &ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL", REG_SMC, 0x0024, 0, &ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER", REG_SMC, 0x0025, 0, &ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0", REG_SMC, 0x0028, 0, &ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1", REG_SMC, 0x0029, 0, &ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2", REG_SMC, 0x002a, 0, &ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3", REG_SMC, 0x002b, 0, &ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4", REG_SMC, 0x002c, 0, &ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5", REG_SMC, 0x002d, 0, &ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6", REG_SMC, 0x002e, 0, &ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7", REG_SMC, 0x002f, 0, &ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8", REG_SMC, 0x0030, 0, &ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9", REG_SMC, 0x0031, 0, &ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10", REG_SMC, 0x0032, 0, &ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11", REG_SMC, 0x0033, 0, &ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12", REG_SMC, 0x0034, 0, &ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13", REG_SMC, 0x0035, 0, &ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE", REG_SMC, 0x0036, 0, &ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC", REG_SMC, 0x0037, 0, &ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR", REG_SMC, 0x0038, 0, &ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0", REG_SMC, 0x003a, 0, &ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1", REG_SMC, 0x003b, 0, &ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2", REG_SMC, 0x003c, 0, &ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3", REG_SMC, 0x003d, 0, &ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4", REG_SMC, 0x003e, 0, &ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5", REG_SMC, 0x003f, 0, &ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6", REG_SMC, 0x0040, 0, &ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7", REG_SMC, 0x0041, 0, &ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8", REG_SMC, 0x0042, 0, &ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL", REG_SMC, 0x0054, 0, &ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE", REG_SMC, 0x0055, 0, &ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT", REG_SMC, 0x0056, 0, &ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2", REG_SMC, 0x0057, 0, &ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE", REG_SMC, 0x0058, 0, &ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0", REG_SMC, 0x0059, 0, &ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1", REG_SMC, 0x005a, 0, &ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2", REG_SMC, 0x005b, 0, &ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3", REG_SMC, 0x005c, 0, &ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4", REG_SMC, 0x005d, 0, &ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5", REG_SMC, 0x005e, 0, &ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6", REG_SMC, 0x005f, 0, &ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7", REG_SMC, 0x0060, 0, &ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8", REG_SMC, 0x0061, 0, &ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO", REG_SMC, 0x0062, 0, &ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS", REG_SMC, 0x0063, 0, &ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL", REG_SMC, 0x0064, 0, &ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB", REG_SMC, 0x0065, 0, &ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT", REG_SMC, 0x0066, 0, &ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE", REG_SMC, 0x0067, 0, &ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED", REG_SMC, 0x0068, 0, &ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION", REG_SMC, 0x0069, 0, &ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE", REG_SMC, 0x006a, 0, &ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS", REG_SMC, 0x006b, 0, &ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS", REG_SMC, 0x006c, 0, &ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS", REG_SMC, 0x006d, 0, &ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS[0]), 0, 0 }, + { "ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS", REG_SMC, 0x006e, 0, &ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS[0], sizeof(ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS)/sizeof(ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES", REG_SMC, 0x0001, 0, &ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT", REG_SMC, 0x0002, 0, &ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID", REG_SMC, 0x0003, 0, &ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER", REG_SMC, 0x0004, 0, &ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS", REG_SMC, 0x0005, 0, &ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES", REG_SMC, 0x0006, 0, &ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL", REG_SMC, 0x0007, 0, &ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE", REG_SMC, 0x0008, 0, &ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING", REG_SMC, 0x0009, 0, &ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA", REG_SMC, 0x000c, 0, &ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN", REG_SMC, 0x000d, 0, &ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX", REG_SMC, 0x000e, 0, &ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES", REG_SMC, 0x0020, 0, &ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES", REG_SMC, 0x0021, 0, &ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE", REG_SMC, 0x0022, 0, &ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE", REG_SMC, 0x0023, 0, &ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL", REG_SMC, 0x0024, 0, &ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER", REG_SMC, 0x0025, 0, &ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0", REG_SMC, 0x0028, 0, &ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1", REG_SMC, 0x0029, 0, &ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2", REG_SMC, 0x002a, 0, &ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3", REG_SMC, 0x002b, 0, &ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4", REG_SMC, 0x002c, 0, &ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5", REG_SMC, 0x002d, 0, &ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6", REG_SMC, 0x002e, 0, &ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7", REG_SMC, 0x002f, 0, &ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8", REG_SMC, 0x0030, 0, &ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9", REG_SMC, 0x0031, 0, &ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10", REG_SMC, 0x0032, 0, &ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11", REG_SMC, 0x0033, 0, &ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12", REG_SMC, 0x0034, 0, &ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13", REG_SMC, 0x0035, 0, &ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE", REG_SMC, 0x0036, 0, &ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC", REG_SMC, 0x0037, 0, &ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR", REG_SMC, 0x0038, 0, &ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0", REG_SMC, 0x003a, 0, &ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1", REG_SMC, 0x003b, 0, &ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2", REG_SMC, 0x003c, 0, &ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3", REG_SMC, 0x003d, 0, &ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4", REG_SMC, 0x003e, 0, &ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5", REG_SMC, 0x003f, 0, &ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6", REG_SMC, 0x0040, 0, &ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7", REG_SMC, 0x0041, 0, &ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8", REG_SMC, 0x0042, 0, &ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL", REG_SMC, 0x0054, 0, &ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE", REG_SMC, 0x0055, 0, &ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT", REG_SMC, 0x0056, 0, &ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2", REG_SMC, 0x0057, 0, &ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE", REG_SMC, 0x0058, 0, &ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0", REG_SMC, 0x0059, 0, &ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1", REG_SMC, 0x005a, 0, &ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2", REG_SMC, 0x005b, 0, &ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3", REG_SMC, 0x005c, 0, &ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4", REG_SMC, 0x005d, 0, &ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5", REG_SMC, 0x005e, 0, &ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6", REG_SMC, 0x005f, 0, &ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7", REG_SMC, 0x0060, 0, &ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8", REG_SMC, 0x0061, 0, &ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO", REG_SMC, 0x0062, 0, &ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS", REG_SMC, 0x0063, 0, &ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL", REG_SMC, 0x0064, 0, &ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB", REG_SMC, 0x0065, 0, &ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT", REG_SMC, 0x0066, 0, &ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE", REG_SMC, 0x0067, 0, &ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED", REG_SMC, 0x0068, 0, &ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION", REG_SMC, 0x0069, 0, &ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE", REG_SMC, 0x006a, 0, &ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS", REG_SMC, 0x006b, 0, &ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS", REG_SMC, 0x006c, 0, &ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS", REG_SMC, 0x006d, 0, &ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS[0]), 0, 0 }, + { "ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS", REG_SMC, 0x006e, 0, &ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS[0], sizeof(ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS)/sizeof(ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES", REG_SMC, 0x0001, 0, &ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT", REG_SMC, 0x0002, 0, &ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID", REG_SMC, 0x0003, 0, &ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER", REG_SMC, 0x0004, 0, &ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS", REG_SMC, 0x0005, 0, &ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES", REG_SMC, 0x0006, 0, &ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL", REG_SMC, 0x0007, 0, &ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE", REG_SMC, 0x0008, 0, &ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING", REG_SMC, 0x0009, 0, &ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA", REG_SMC, 0x000c, 0, &ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN", REG_SMC, 0x000d, 0, &ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX", REG_SMC, 0x000e, 0, &ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES", REG_SMC, 0x0020, 0, &ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES", REG_SMC, 0x0021, 0, &ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE", REG_SMC, 0x0022, 0, &ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE", REG_SMC, 0x0023, 0, &ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL", REG_SMC, 0x0024, 0, &ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER", REG_SMC, 0x0025, 0, &ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0", REG_SMC, 0x0028, 0, &ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1", REG_SMC, 0x0029, 0, &ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2", REG_SMC, 0x002a, 0, &ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3", REG_SMC, 0x002b, 0, &ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4", REG_SMC, 0x002c, 0, &ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5", REG_SMC, 0x002d, 0, &ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6", REG_SMC, 0x002e, 0, &ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7", REG_SMC, 0x002f, 0, &ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8", REG_SMC, 0x0030, 0, &ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9", REG_SMC, 0x0031, 0, &ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10", REG_SMC, 0x0032, 0, &ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11", REG_SMC, 0x0033, 0, &ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12", REG_SMC, 0x0034, 0, &ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13", REG_SMC, 0x0035, 0, &ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE", REG_SMC, 0x0036, 0, &ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC", REG_SMC, 0x0037, 0, &ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR", REG_SMC, 0x0038, 0, &ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0", REG_SMC, 0x003a, 0, &ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1", REG_SMC, 0x003b, 0, &ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2", REG_SMC, 0x003c, 0, &ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3", REG_SMC, 0x003d, 0, &ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4", REG_SMC, 0x003e, 0, &ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5", REG_SMC, 0x003f, 0, &ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6", REG_SMC, 0x0040, 0, &ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7", REG_SMC, 0x0041, 0, &ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8", REG_SMC, 0x0042, 0, &ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL", REG_SMC, 0x0054, 0, &ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE", REG_SMC, 0x0055, 0, &ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT", REG_SMC, 0x0056, 0, &ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2", REG_SMC, 0x0057, 0, &ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE", REG_SMC, 0x0058, 0, &ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0", REG_SMC, 0x0059, 0, &ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1", REG_SMC, 0x005a, 0, &ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2", REG_SMC, 0x005b, 0, &ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3", REG_SMC, 0x005c, 0, &ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4", REG_SMC, 0x005d, 0, &ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5", REG_SMC, 0x005e, 0, &ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6", REG_SMC, 0x005f, 0, &ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7", REG_SMC, 0x0060, 0, &ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8", REG_SMC, 0x0061, 0, &ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO", REG_SMC, 0x0062, 0, &ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS", REG_SMC, 0x0063, 0, &ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL", REG_SMC, 0x0064, 0, &ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB", REG_SMC, 0x0065, 0, &ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT", REG_SMC, 0x0066, 0, &ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE", REG_SMC, 0x0067, 0, &ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED", REG_SMC, 0x0068, 0, &ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION", REG_SMC, 0x0069, 0, &ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE", REG_SMC, 0x006a, 0, &ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS", REG_SMC, 0x006b, 0, &ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS", REG_SMC, 0x006c, 0, &ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS", REG_SMC, 0x006d, 0, &ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS[0]), 0, 0 }, + { "ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS", REG_SMC, 0x006e, 0, &ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS[0], sizeof(ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS)/sizeof(ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES", REG_SMC, 0x0001, 0, &ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT", REG_SMC, 0x0002, 0, &ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID", REG_SMC, 0x0003, 0, &ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER", REG_SMC, 0x0004, 0, &ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS", REG_SMC, 0x0005, 0, &ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES", REG_SMC, 0x0006, 0, &ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL", REG_SMC, 0x0007, 0, &ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE", REG_SMC, 0x0008, 0, &ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING", REG_SMC, 0x0009, 0, &ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA", REG_SMC, 0x000c, 0, &ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN", REG_SMC, 0x000d, 0, &ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX", REG_SMC, 0x000e, 0, &ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES", REG_SMC, 0x0020, 0, &ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES", REG_SMC, 0x0021, 0, &ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE", REG_SMC, 0x0022, 0, &ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE", REG_SMC, 0x0023, 0, &ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL", REG_SMC, 0x0024, 0, &ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER", REG_SMC, 0x0025, 0, &ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0", REG_SMC, 0x0028, 0, &ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1", REG_SMC, 0x0029, 0, &ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2", REG_SMC, 0x002a, 0, &ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3", REG_SMC, 0x002b, 0, &ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4", REG_SMC, 0x002c, 0, &ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5", REG_SMC, 0x002d, 0, &ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6", REG_SMC, 0x002e, 0, &ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7", REG_SMC, 0x002f, 0, &ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8", REG_SMC, 0x0030, 0, &ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9", REG_SMC, 0x0031, 0, &ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10", REG_SMC, 0x0032, 0, &ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11", REG_SMC, 0x0033, 0, &ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12", REG_SMC, 0x0034, 0, &ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13", REG_SMC, 0x0035, 0, &ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE", REG_SMC, 0x0036, 0, &ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC", REG_SMC, 0x0037, 0, &ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR", REG_SMC, 0x0038, 0, &ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0", REG_SMC, 0x003a, 0, &ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1", REG_SMC, 0x003b, 0, &ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2", REG_SMC, 0x003c, 0, &ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3", REG_SMC, 0x003d, 0, &ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4", REG_SMC, 0x003e, 0, &ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5", REG_SMC, 0x003f, 0, &ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6", REG_SMC, 0x0040, 0, &ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7", REG_SMC, 0x0041, 0, &ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8", REG_SMC, 0x0042, 0, &ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL", REG_SMC, 0x0054, 0, &ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE", REG_SMC, 0x0055, 0, &ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT", REG_SMC, 0x0056, 0, &ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2", REG_SMC, 0x0057, 0, &ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE", REG_SMC, 0x0058, 0, &ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0", REG_SMC, 0x0059, 0, &ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1", REG_SMC, 0x005a, 0, &ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2", REG_SMC, 0x005b, 0, &ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3", REG_SMC, 0x005c, 0, &ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4", REG_SMC, 0x005d, 0, &ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5", REG_SMC, 0x005e, 0, &ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6", REG_SMC, 0x005f, 0, &ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7", REG_SMC, 0x0060, 0, &ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8", REG_SMC, 0x0061, 0, &ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO", REG_SMC, 0x0062, 0, &ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS", REG_SMC, 0x0063, 0, &ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL", REG_SMC, 0x0064, 0, &ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB", REG_SMC, 0x0065, 0, &ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT", REG_SMC, 0x0066, 0, &ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE", REG_SMC, 0x0067, 0, &ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED", REG_SMC, 0x0068, 0, &ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION", REG_SMC, 0x0069, 0, &ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE", REG_SMC, 0x006a, 0, &ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS", REG_SMC, 0x006b, 0, &ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS", REG_SMC, 0x006c, 0, &ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS", REG_SMC, 0x006d, 0, &ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS[0]), 0, 0 }, + { "ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS", REG_SMC, 0x006e, 0, &ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS[0], sizeof(ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS)/sizeof(ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES", REG_SMC, 0x0001, 0, &ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT", REG_SMC, 0x0002, 0, &ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID", REG_SMC, 0x0003, 0, &ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER", REG_SMC, 0x0004, 0, &ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS", REG_SMC, 0x0005, 0, &ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES", REG_SMC, 0x0006, 0, &ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL", REG_SMC, 0x0007, 0, &ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE", REG_SMC, 0x0008, 0, &ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING", REG_SMC, 0x0009, 0, &ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA", REG_SMC, 0x000c, 0, &ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN", REG_SMC, 0x000d, 0, &ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX", REG_SMC, 0x000e, 0, &ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES", REG_SMC, 0x0020, 0, &ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES", REG_SMC, 0x0021, 0, &ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE", REG_SMC, 0x0022, 0, &ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE", REG_SMC, 0x0023, 0, &ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL", REG_SMC, 0x0024, 0, &ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER", REG_SMC, 0x0025, 0, &ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0", REG_SMC, 0x0028, 0, &ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1", REG_SMC, 0x0029, 0, &ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2", REG_SMC, 0x002a, 0, &ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3", REG_SMC, 0x002b, 0, &ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4", REG_SMC, 0x002c, 0, &ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5", REG_SMC, 0x002d, 0, &ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6", REG_SMC, 0x002e, 0, &ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7", REG_SMC, 0x002f, 0, &ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8", REG_SMC, 0x0030, 0, &ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9", REG_SMC, 0x0031, 0, &ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10", REG_SMC, 0x0032, 0, &ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11", REG_SMC, 0x0033, 0, &ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12", REG_SMC, 0x0034, 0, &ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13", REG_SMC, 0x0035, 0, &ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE", REG_SMC, 0x0036, 0, &ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC", REG_SMC, 0x0037, 0, &ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR", REG_SMC, 0x0038, 0, &ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0", REG_SMC, 0x003a, 0, &ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1", REG_SMC, 0x003b, 0, &ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2", REG_SMC, 0x003c, 0, &ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3", REG_SMC, 0x003d, 0, &ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4", REG_SMC, 0x003e, 0, &ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5", REG_SMC, 0x003f, 0, &ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6", REG_SMC, 0x0040, 0, &ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7", REG_SMC, 0x0041, 0, &ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8", REG_SMC, 0x0042, 0, &ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL", REG_SMC, 0x0054, 0, &ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE", REG_SMC, 0x0055, 0, &ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT", REG_SMC, 0x0056, 0, &ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2", REG_SMC, 0x0057, 0, &ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE", REG_SMC, 0x0058, 0, &ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0", REG_SMC, 0x0059, 0, &ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1", REG_SMC, 0x005a, 0, &ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2", REG_SMC, 0x005b, 0, &ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3", REG_SMC, 0x005c, 0, &ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4", REG_SMC, 0x005d, 0, &ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5", REG_SMC, 0x005e, 0, &ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6", REG_SMC, 0x005f, 0, &ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7", REG_SMC, 0x0060, 0, &ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8", REG_SMC, 0x0061, 0, &ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO", REG_SMC, 0x0062, 0, &ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS", REG_SMC, 0x0063, 0, &ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL", REG_SMC, 0x0064, 0, &ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB", REG_SMC, 0x0065, 0, &ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT", REG_SMC, 0x0066, 0, &ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE", REG_SMC, 0x0067, 0, &ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED", REG_SMC, 0x0068, 0, &ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION", REG_SMC, 0x0069, 0, &ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE", REG_SMC, 0x006a, 0, &ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS", REG_SMC, 0x006b, 0, &ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS", REG_SMC, 0x006c, 0, &ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS", REG_SMC, 0x006d, 0, &ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS[0]), 0, 0 }, + { "ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS", REG_SMC, 0x006e, 0, &ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS[0], sizeof(ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS)/sizeof(ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES", REG_SMC, 0x0001, 0, &ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT", REG_SMC, 0x0002, 0, &ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID", REG_SMC, 0x0003, 0, &ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER", REG_SMC, 0x0004, 0, &ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS", REG_SMC, 0x0005, 0, &ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES", REG_SMC, 0x0006, 0, &ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL", REG_SMC, 0x0007, 0, &ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE", REG_SMC, 0x0008, 0, &ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING", REG_SMC, 0x0009, 0, &ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA", REG_SMC, 0x000c, 0, &ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN", REG_SMC, 0x000d, 0, &ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX", REG_SMC, 0x000e, 0, &ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES", REG_SMC, 0x0020, 0, &ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES", REG_SMC, 0x0021, 0, &ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE", REG_SMC, 0x0022, 0, &ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE", REG_SMC, 0x0023, 0, &ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL", REG_SMC, 0x0024, 0, &ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER", REG_SMC, 0x0025, 0, &ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0", REG_SMC, 0x0028, 0, &ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1", REG_SMC, 0x0029, 0, &ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2", REG_SMC, 0x002a, 0, &ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3", REG_SMC, 0x002b, 0, &ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4", REG_SMC, 0x002c, 0, &ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5", REG_SMC, 0x002d, 0, &ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6", REG_SMC, 0x002e, 0, &ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7", REG_SMC, 0x002f, 0, &ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8", REG_SMC, 0x0030, 0, &ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9", REG_SMC, 0x0031, 0, &ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10", REG_SMC, 0x0032, 0, &ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11", REG_SMC, 0x0033, 0, &ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12", REG_SMC, 0x0034, 0, &ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13", REG_SMC, 0x0035, 0, &ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE", REG_SMC, 0x0036, 0, &ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC", REG_SMC, 0x0037, 0, &ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR", REG_SMC, 0x0038, 0, &ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0", REG_SMC, 0x003a, 0, &ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1", REG_SMC, 0x003b, 0, &ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2", REG_SMC, 0x003c, 0, &ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3", REG_SMC, 0x003d, 0, &ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4", REG_SMC, 0x003e, 0, &ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5", REG_SMC, 0x003f, 0, &ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6", REG_SMC, 0x0040, 0, &ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7", REG_SMC, 0x0041, 0, &ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8", REG_SMC, 0x0042, 0, &ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL", REG_SMC, 0x0054, 0, &ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE", REG_SMC, 0x0055, 0, &ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT", REG_SMC, 0x0056, 0, &ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2", REG_SMC, 0x0057, 0, &ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE", REG_SMC, 0x0058, 0, &ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0", REG_SMC, 0x0059, 0, &ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1", REG_SMC, 0x005a, 0, &ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2", REG_SMC, 0x005b, 0, &ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3", REG_SMC, 0x005c, 0, &ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4", REG_SMC, 0x005d, 0, &ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5", REG_SMC, 0x005e, 0, &ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6", REG_SMC, 0x005f, 0, &ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7", REG_SMC, 0x0060, 0, &ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8", REG_SMC, 0x0061, 0, &ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO", REG_SMC, 0x0062, 0, &ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS", REG_SMC, 0x0063, 0, &ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL", REG_SMC, 0x0064, 0, &ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB", REG_SMC, 0x0065, 0, &ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT", REG_SMC, 0x0066, 0, &ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE", REG_SMC, 0x0067, 0, &ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED", REG_SMC, 0x0068, 0, &ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION", REG_SMC, 0x0069, 0, &ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE", REG_SMC, 0x006a, 0, &ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS", REG_SMC, 0x006b, 0, &ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS", REG_SMC, 0x006c, 0, &ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS", REG_SMC, 0x006d, 0, &ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS[0]), 0, 0 }, + { "ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS", REG_SMC, 0x006e, 0, &ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS[0], sizeof(ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS)/sizeof(ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES", REG_SMC, 0x0001, 0, &ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0], sizeof(ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES)/sizeof(ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT", REG_SMC, 0x0002, 0, &ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT[0], sizeof(ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT)/sizeof(ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID", REG_SMC, 0x0003, 0, &ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID[0], sizeof(ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID)/sizeof(ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER", REG_SMC, 0x0004, 0, &ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER[0], sizeof(ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER)/sizeof(ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS", REG_SMC, 0x0005, 0, &ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS[0], sizeof(ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS)/sizeof(ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES", REG_SMC, 0x0006, 0, &ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[0], sizeof(ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES)/sizeof(ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES", REG_SMC, 0x0020, 0, &ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0], sizeof(ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES)/sizeof(ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES", REG_SMC, 0x0021, 0, &ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES[0], sizeof(ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES)/sizeof(ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE", REG_SMC, 0x0022, 0, &ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE[0], sizeof(ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE)/sizeof(ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE", REG_SMC, 0x0023, 0, &ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE[0], sizeof(ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE)/sizeof(ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL", REG_SMC, 0x0024, 0, &ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL[0], sizeof(ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL)/sizeof(ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE", REG_SMC, 0x0036, 0, &ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE[0], sizeof(ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE)/sizeof(ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2", REG_SMC, 0x0037, 0, &ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2[0], sizeof(ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2)/sizeof(ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR", REG_SMC, 0x0038, 0, &ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR[0], sizeof(ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR)/sizeof(ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION", REG_SMC, 0x0053, 0, &ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION[0], sizeof(ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION)/sizeof(ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL", REG_SMC, 0x0054, 0, &ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL[0], sizeof(ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL)/sizeof(ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE", REG_SMC, 0x0055, 0, &ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[0], sizeof(ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE)/sizeof(ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT", REG_SMC, 0x0056, 0, &ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[0], sizeof(ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT)/sizeof(ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL", REG_SMC, 0x0064, 0, &ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[0], sizeof(ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL)/sizeof(ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB", REG_SMC, 0x0065, 0, &ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB[0], sizeof(ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB)/sizeof(ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT", REG_SMC, 0x0066, 0, &ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[0], sizeof(ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT)/sizeof(ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL", REG_SMC, 0x0067, 0, &ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL[0], sizeof(ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL)/sizeof(ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME", REG_SMC, 0x0068, 0, &ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME[0], sizeof(ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME)/sizeof(ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES", REG_SMC, 0x0001, 0, &ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0], sizeof(ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES)/sizeof(ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT", REG_SMC, 0x0002, 0, &ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT[0], sizeof(ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT)/sizeof(ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID", REG_SMC, 0x0003, 0, &ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID[0], sizeof(ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID)/sizeof(ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER", REG_SMC, 0x0004, 0, &ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER[0], sizeof(ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER)/sizeof(ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS", REG_SMC, 0x0005, 0, &ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS[0], sizeof(ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS)/sizeof(ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES", REG_SMC, 0x0006, 0, &ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[0], sizeof(ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES)/sizeof(ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES", REG_SMC, 0x0020, 0, &ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0], sizeof(ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES)/sizeof(ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES", REG_SMC, 0x0021, 0, &ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES[0], sizeof(ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES)/sizeof(ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE", REG_SMC, 0x0022, 0, &ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE[0], sizeof(ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE)/sizeof(ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE", REG_SMC, 0x0023, 0, &ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE[0], sizeof(ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE)/sizeof(ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL", REG_SMC, 0x0024, 0, &ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL[0], sizeof(ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL)/sizeof(ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE", REG_SMC, 0x0036, 0, &ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE[0], sizeof(ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE)/sizeof(ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2", REG_SMC, 0x0037, 0, &ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2[0], sizeof(ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2)/sizeof(ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR", REG_SMC, 0x0038, 0, &ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR[0], sizeof(ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR)/sizeof(ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION", REG_SMC, 0x0053, 0, &ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION[0], sizeof(ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION)/sizeof(ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL", REG_SMC, 0x0054, 0, &ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL[0], sizeof(ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL)/sizeof(ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE", REG_SMC, 0x0055, 0, &ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[0], sizeof(ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE)/sizeof(ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT", REG_SMC, 0x0056, 0, &ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[0], sizeof(ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT)/sizeof(ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL", REG_SMC, 0x0064, 0, &ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[0], sizeof(ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL)/sizeof(ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB", REG_SMC, 0x0065, 0, &ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB[0], sizeof(ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB)/sizeof(ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT", REG_SMC, 0x0066, 0, &ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[0], sizeof(ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT)/sizeof(ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL", REG_SMC, 0x0067, 0, &ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL[0], sizeof(ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL)/sizeof(ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME", REG_SMC, 0x0068, 0, &ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME[0], sizeof(ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME)/sizeof(ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES", REG_SMC, 0x0001, 0, &ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0], sizeof(ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES)/sizeof(ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT", REG_SMC, 0x0002, 0, &ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT[0], sizeof(ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT)/sizeof(ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID", REG_SMC, 0x0003, 0, &ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID[0], sizeof(ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID)/sizeof(ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER", REG_SMC, 0x0004, 0, &ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER[0], sizeof(ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER)/sizeof(ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS", REG_SMC, 0x0005, 0, &ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS[0], sizeof(ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS)/sizeof(ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES", REG_SMC, 0x0006, 0, &ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[0], sizeof(ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES)/sizeof(ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES", REG_SMC, 0x0020, 0, &ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0], sizeof(ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES)/sizeof(ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES", REG_SMC, 0x0021, 0, &ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES[0], sizeof(ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES)/sizeof(ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE", REG_SMC, 0x0022, 0, &ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE[0], sizeof(ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE)/sizeof(ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE", REG_SMC, 0x0023, 0, &ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE[0], sizeof(ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE)/sizeof(ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL", REG_SMC, 0x0024, 0, &ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL[0], sizeof(ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL)/sizeof(ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE", REG_SMC, 0x0036, 0, &ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE[0], sizeof(ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE)/sizeof(ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2", REG_SMC, 0x0037, 0, &ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2[0], sizeof(ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2)/sizeof(ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR", REG_SMC, 0x0038, 0, &ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR[0], sizeof(ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR)/sizeof(ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION", REG_SMC, 0x0053, 0, &ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION[0], sizeof(ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION)/sizeof(ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL", REG_SMC, 0x0054, 0, &ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL[0], sizeof(ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL)/sizeof(ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE", REG_SMC, 0x0055, 0, &ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[0], sizeof(ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE)/sizeof(ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT", REG_SMC, 0x0056, 0, &ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[0], sizeof(ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT)/sizeof(ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL", REG_SMC, 0x0064, 0, &ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[0], sizeof(ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL)/sizeof(ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB", REG_SMC, 0x0065, 0, &ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB[0], sizeof(ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB)/sizeof(ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT", REG_SMC, 0x0066, 0, &ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[0], sizeof(ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT)/sizeof(ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL", REG_SMC, 0x0067, 0, &ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL[0], sizeof(ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL)/sizeof(ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME", REG_SMC, 0x0068, 0, &ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME[0], sizeof(ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME)/sizeof(ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES", REG_SMC, 0x0001, 0, &ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0], sizeof(ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES)/sizeof(ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT", REG_SMC, 0x0002, 0, &ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT[0], sizeof(ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT)/sizeof(ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID", REG_SMC, 0x0003, 0, &ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID[0], sizeof(ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID)/sizeof(ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER", REG_SMC, 0x0004, 0, &ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER[0], sizeof(ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER)/sizeof(ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS", REG_SMC, 0x0005, 0, &ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS[0], sizeof(ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS)/sizeof(ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES", REG_SMC, 0x0006, 0, &ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[0], sizeof(ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES)/sizeof(ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES", REG_SMC, 0x0020, 0, &ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0], sizeof(ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES)/sizeof(ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES", REG_SMC, 0x0021, 0, &ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES[0], sizeof(ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES)/sizeof(ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE", REG_SMC, 0x0022, 0, &ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE[0], sizeof(ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE)/sizeof(ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE", REG_SMC, 0x0023, 0, &ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE[0], sizeof(ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE)/sizeof(ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL", REG_SMC, 0x0024, 0, &ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL[0], sizeof(ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL)/sizeof(ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE", REG_SMC, 0x0036, 0, &ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE[0], sizeof(ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE)/sizeof(ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2", REG_SMC, 0x0037, 0, &ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2[0], sizeof(ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2)/sizeof(ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR", REG_SMC, 0x0038, 0, &ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR[0], sizeof(ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR)/sizeof(ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION", REG_SMC, 0x0053, 0, &ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION[0], sizeof(ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION)/sizeof(ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL", REG_SMC, 0x0054, 0, &ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL[0], sizeof(ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL)/sizeof(ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE", REG_SMC, 0x0055, 0, &ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[0], sizeof(ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE)/sizeof(ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT", REG_SMC, 0x0056, 0, &ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[0], sizeof(ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT)/sizeof(ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL", REG_SMC, 0x0064, 0, &ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[0], sizeof(ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL)/sizeof(ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB", REG_SMC, 0x0065, 0, &ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB[0], sizeof(ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB)/sizeof(ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT", REG_SMC, 0x0066, 0, &ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[0], sizeof(ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT)/sizeof(ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL", REG_SMC, 0x0067, 0, &ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL[0], sizeof(ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL)/sizeof(ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME", REG_SMC, 0x0068, 0, &ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME[0], sizeof(ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME)/sizeof(ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES", REG_SMC, 0x0001, 0, &ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0], sizeof(ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES)/sizeof(ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT", REG_SMC, 0x0002, 0, &ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT[0], sizeof(ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT)/sizeof(ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID", REG_SMC, 0x0003, 0, &ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID[0], sizeof(ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID)/sizeof(ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER", REG_SMC, 0x0004, 0, &ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER[0], sizeof(ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER)/sizeof(ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS", REG_SMC, 0x0005, 0, &ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS[0], sizeof(ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS)/sizeof(ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES", REG_SMC, 0x0006, 0, &ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[0], sizeof(ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES)/sizeof(ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES", REG_SMC, 0x0020, 0, &ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0], sizeof(ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES)/sizeof(ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES", REG_SMC, 0x0021, 0, &ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES[0], sizeof(ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES)/sizeof(ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE", REG_SMC, 0x0022, 0, &ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE[0], sizeof(ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE)/sizeof(ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE", REG_SMC, 0x0023, 0, &ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE[0], sizeof(ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE)/sizeof(ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL", REG_SMC, 0x0024, 0, &ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL[0], sizeof(ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL)/sizeof(ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE", REG_SMC, 0x0036, 0, &ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE[0], sizeof(ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE)/sizeof(ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2", REG_SMC, 0x0037, 0, &ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2[0], sizeof(ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2)/sizeof(ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR", REG_SMC, 0x0038, 0, &ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR[0], sizeof(ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR)/sizeof(ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION", REG_SMC, 0x0053, 0, &ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION[0], sizeof(ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION)/sizeof(ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL", REG_SMC, 0x0054, 0, &ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL[0], sizeof(ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL)/sizeof(ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE", REG_SMC, 0x0055, 0, &ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[0], sizeof(ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE)/sizeof(ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT", REG_SMC, 0x0056, 0, &ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[0], sizeof(ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT)/sizeof(ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL", REG_SMC, 0x0064, 0, &ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[0], sizeof(ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL)/sizeof(ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB", REG_SMC, 0x0065, 0, &ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB[0], sizeof(ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB)/sizeof(ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT", REG_SMC, 0x0066, 0, &ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[0], sizeof(ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT)/sizeof(ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL", REG_SMC, 0x0067, 0, &ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL[0], sizeof(ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL)/sizeof(ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME", REG_SMC, 0x0068, 0, &ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME[0], sizeof(ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME)/sizeof(ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES", REG_SMC, 0x0001, 0, &ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0], sizeof(ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES)/sizeof(ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT", REG_SMC, 0x0002, 0, &ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT[0], sizeof(ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT)/sizeof(ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID", REG_SMC, 0x0003, 0, &ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID[0], sizeof(ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID)/sizeof(ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER", REG_SMC, 0x0004, 0, &ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER[0], sizeof(ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER)/sizeof(ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS", REG_SMC, 0x0005, 0, &ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS[0], sizeof(ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS)/sizeof(ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES", REG_SMC, 0x0006, 0, &ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[0], sizeof(ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES)/sizeof(ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES", REG_SMC, 0x0020, 0, &ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0], sizeof(ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES)/sizeof(ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES", REG_SMC, 0x0021, 0, &ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES[0], sizeof(ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES)/sizeof(ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE", REG_SMC, 0x0022, 0, &ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE[0], sizeof(ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE)/sizeof(ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE", REG_SMC, 0x0023, 0, &ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE[0], sizeof(ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE)/sizeof(ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL", REG_SMC, 0x0024, 0, &ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL[0], sizeof(ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL)/sizeof(ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE", REG_SMC, 0x0036, 0, &ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE[0], sizeof(ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE)/sizeof(ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2", REG_SMC, 0x0037, 0, &ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2[0], sizeof(ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2)/sizeof(ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR", REG_SMC, 0x0038, 0, &ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR[0], sizeof(ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR)/sizeof(ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION", REG_SMC, 0x0053, 0, &ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION[0], sizeof(ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION)/sizeof(ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL", REG_SMC, 0x0054, 0, &ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL[0], sizeof(ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL)/sizeof(ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE", REG_SMC, 0x0055, 0, &ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[0], sizeof(ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE)/sizeof(ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT", REG_SMC, 0x0056, 0, &ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[0], sizeof(ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT)/sizeof(ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL", REG_SMC, 0x0064, 0, &ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[0], sizeof(ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL)/sizeof(ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB", REG_SMC, 0x0065, 0, &ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB[0], sizeof(ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB)/sizeof(ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT", REG_SMC, 0x0066, 0, &ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[0], sizeof(ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT)/sizeof(ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL", REG_SMC, 0x0067, 0, &ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL[0], sizeof(ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL)/sizeof(ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME", REG_SMC, 0x0068, 0, &ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME[0], sizeof(ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME)/sizeof(ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES", REG_SMC, 0x0001, 0, &ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0], sizeof(ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES)/sizeof(ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT", REG_SMC, 0x0002, 0, &ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT[0], sizeof(ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT)/sizeof(ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID", REG_SMC, 0x0003, 0, &ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID[0], sizeof(ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID)/sizeof(ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER", REG_SMC, 0x0004, 0, &ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER[0], sizeof(ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER)/sizeof(ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS", REG_SMC, 0x0005, 0, &ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS[0], sizeof(ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS)/sizeof(ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES", REG_SMC, 0x0006, 0, &ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[0], sizeof(ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES)/sizeof(ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES", REG_SMC, 0x0020, 0, &ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0], sizeof(ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES)/sizeof(ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES", REG_SMC, 0x0021, 0, &ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES[0], sizeof(ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES)/sizeof(ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE", REG_SMC, 0x0022, 0, &ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE[0], sizeof(ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE)/sizeof(ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE", REG_SMC, 0x0023, 0, &ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE[0], sizeof(ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE)/sizeof(ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL", REG_SMC, 0x0024, 0, &ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL[0], sizeof(ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL)/sizeof(ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE", REG_SMC, 0x0036, 0, &ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE[0], sizeof(ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE)/sizeof(ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2", REG_SMC, 0x0037, 0, &ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2[0], sizeof(ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2)/sizeof(ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR", REG_SMC, 0x0038, 0, &ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR[0], sizeof(ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR)/sizeof(ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION", REG_SMC, 0x0053, 0, &ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION[0], sizeof(ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION)/sizeof(ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL", REG_SMC, 0x0054, 0, &ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL[0], sizeof(ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL)/sizeof(ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE", REG_SMC, 0x0055, 0, &ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[0], sizeof(ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE)/sizeof(ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT", REG_SMC, 0x0056, 0, &ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[0], sizeof(ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT)/sizeof(ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL", REG_SMC, 0x0064, 0, &ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[0], sizeof(ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL)/sizeof(ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB", REG_SMC, 0x0065, 0, &ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB[0], sizeof(ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB)/sizeof(ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT", REG_SMC, 0x0066, 0, &ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[0], sizeof(ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT)/sizeof(ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL", REG_SMC, 0x0067, 0, &ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL[0], sizeof(ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL)/sizeof(ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME", REG_SMC, 0x0068, 0, &ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME[0], sizeof(ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME)/sizeof(ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES", REG_SMC, 0x0001, 0, &ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0], sizeof(ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES)/sizeof(ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT", REG_SMC, 0x0002, 0, &ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT[0], sizeof(ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT)/sizeof(ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID", REG_SMC, 0x0003, 0, &ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID[0], sizeof(ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID)/sizeof(ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER", REG_SMC, 0x0004, 0, &ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER[0], sizeof(ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER)/sizeof(ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS", REG_SMC, 0x0005, 0, &ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS[0], sizeof(ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS)/sizeof(ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES", REG_SMC, 0x0006, 0, &ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[0], sizeof(ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES)/sizeof(ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES", REG_SMC, 0x0020, 0, &ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0], sizeof(ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES)/sizeof(ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES", REG_SMC, 0x0021, 0, &ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES[0], sizeof(ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES)/sizeof(ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE", REG_SMC, 0x0022, 0, &ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE[0], sizeof(ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE)/sizeof(ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE", REG_SMC, 0x0023, 0, &ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE[0], sizeof(ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE)/sizeof(ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL", REG_SMC, 0x0024, 0, &ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL[0], sizeof(ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL)/sizeof(ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE", REG_SMC, 0x0036, 0, &ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE[0], sizeof(ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE)/sizeof(ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2", REG_SMC, 0x0037, 0, &ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2[0], sizeof(ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2)/sizeof(ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR", REG_SMC, 0x0038, 0, &ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR[0], sizeof(ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR)/sizeof(ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION", REG_SMC, 0x0053, 0, &ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION[0], sizeof(ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION)/sizeof(ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL", REG_SMC, 0x0054, 0, &ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL[0], sizeof(ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL)/sizeof(ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE", REG_SMC, 0x0055, 0, &ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[0], sizeof(ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE)/sizeof(ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT", REG_SMC, 0x0056, 0, &ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[0], sizeof(ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT)/sizeof(ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL", REG_SMC, 0x0064, 0, &ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[0], sizeof(ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL)/sizeof(ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB", REG_SMC, 0x0065, 0, &ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB[0], sizeof(ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB)/sizeof(ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT", REG_SMC, 0x0066, 0, &ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[0], sizeof(ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT)/sizeof(ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL", REG_SMC, 0x0067, 0, &ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL[0], sizeof(ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL)/sizeof(ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL[0]), 0, 0 }, + { "ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME", REG_SMC, 0x0068, 0, &ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME[0], sizeof(ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME)/sizeof(ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME[0]), 0, 0 }, diff --git a/src/lib/ip/gfx91.c b/src/lib/ip/gfx91.c new file mode 100644 index 0000000..14ca0fd --- /dev/null +++ b/src/lib/ip/gfx91.c @@ -0,0 +1,68 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Tom St Denis <tom.stdenis@amd.com> + * + */ +#include "umr.h" + +#include "gfx91_bits.i" + +static const struct umr_reg_soc15 gfx91_registers[] = { +#include "gfx91_regs.i" +}; + +static int grant(struct umr_asic *asic) +{ + (void)asic; + return 0; +} + +static int deny(struct umr_asic *asic) +{ + (void)asic; + return -1; +} + +struct umr_ip_block *umr_create_gfx91(struct umr_ip_offsets_soc15 *soc15_offsets, struct umr_options *options) +{ + struct umr_ip_block *ip; + + ip = calloc(1, sizeof *ip); + if (!ip) + return NULL; + + ip->ipname = "gfx91"; + ip->no_regs = sizeof(gfx91_registers)/sizeof(gfx91_registers[0]); + ip->regs = calloc(ip->no_regs, sizeof(ip->regs[0])); + if (!ip->regs) { + free(ip); + return NULL; + } + ip->grant = (options->risky >= 1) ? grant : deny; + + if (umr_transfer_soc15_to_reg(options, soc15_offsets, "GC", gfx91_registers, ip)) { + free(ip); + return NULL; + } + + return ip; +} diff --git a/src/lib/ip/gfx91_bits.i b/src/lib/ip/gfx91_bits.i new file mode 100644 index 0000000..e89e6ec --- /dev/null +++ b/src/lib/ip/gfx91_bits.i @@ -0,0 +1,21248 @@ +static struct umr_bitfield mmGRBM_CNTL[] = { + { "READ_TIMEOUT", 0, 7, &umr_bitfield_default }, + { "REPORT_LAST_RDERR", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRBM_SKEW_CNTL[] = { + { "SKEW_TOP_THRESHOLD", 0, 5, &umr_bitfield_default }, + { "SKEW_COUNT", 6, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRBM_STATUS2[] = { + { "ME0PIPE1_CMDFIFO_AVAIL", 0, 3, &umr_bitfield_default }, + { "ME0PIPE1_CF_RQ_PENDING", 4, 4, &umr_bitfield_default }, + { "ME0PIPE1_PF_RQ_PENDING", 5, 5, &umr_bitfield_default }, + { "ME1PIPE0_RQ_PENDING", 6, 6, &umr_bitfield_default }, + { "ME1PIPE1_RQ_PENDING", 7, 7, &umr_bitfield_default }, + { "ME1PIPE2_RQ_PENDING", 8, 8, &umr_bitfield_default }, + { "ME1PIPE3_RQ_PENDING", 9, 9, &umr_bitfield_default }, + { "ME2PIPE0_RQ_PENDING", 10, 10, &umr_bitfield_default }, + { "ME2PIPE1_RQ_PENDING", 11, 11, &umr_bitfield_default }, + { "ME2PIPE2_RQ_PENDING", 12, 12, &umr_bitfield_default }, + { "ME2PIPE3_RQ_PENDING", 13, 13, &umr_bitfield_default }, + { "RLC_RQ_PENDING", 14, 14, &umr_bitfield_default }, + { "UTCL2_BUSY", 15, 15, &umr_bitfield_default }, + { "EA_BUSY", 16, 16, &umr_bitfield_default }, + { "RMI_BUSY", 17, 17, &umr_bitfield_default }, + { "UTCL2_RQ_PENDING", 18, 18, &umr_bitfield_default }, + { "CPF_RQ_PENDING", 19, 19, &umr_bitfield_default }, + { "EA_LINK_BUSY", 20, 20, &umr_bitfield_default }, + { "RLC_BUSY", 24, 24, &umr_bitfield_default }, + { "TC_BUSY", 25, 25, &umr_bitfield_default }, + { "TCC_CC_RESIDENT", 26, 26, &umr_bitfield_default }, + { "CPF_BUSY", 28, 28, &umr_bitfield_default }, + { "CPC_BUSY", 29, 29, &umr_bitfield_default }, + { "CPG_BUSY", 30, 30, &umr_bitfield_default }, + { "CPAXI_BUSY", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRBM_PWR_CNTL[] = { + { "ALL_REQ_TYPE", 0, 1, &umr_bitfield_default }, + { "GFX_REQ_TYPE", 2, 3, &umr_bitfield_default }, + { "ALL_RSP_TYPE", 4, 5, &umr_bitfield_default }, + { "GFX_RSP_TYPE", 6, 7, &umr_bitfield_default }, + { "GFX_REQ_EN", 14, 14, &umr_bitfield_default }, + { "ALL_REQ_EN", 15, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRBM_STATUS[] = { + { "ME0PIPE0_CMDFIFO_AVAIL", 0, 3, &umr_bitfield_default }, + { "RSMU_RQ_PENDING", 5, 5, &umr_bitfield_default }, + { "ME0PIPE0_CF_RQ_PENDING", 7, 7, &umr_bitfield_default }, + { "ME0PIPE0_PF_RQ_PENDING", 8, 8, &umr_bitfield_default }, + { "GDS_DMA_RQ_PENDING", 9, 9, &umr_bitfield_default }, + { "DB_CLEAN", 12, 12, &umr_bitfield_default }, + { "CB_CLEAN", 13, 13, &umr_bitfield_default }, + { "TA_BUSY", 14, 14, &umr_bitfield_default }, + { "GDS_BUSY", 15, 15, &umr_bitfield_default }, + { "WD_BUSY_NO_DMA", 16, 16, &umr_bitfield_default }, + { "VGT_BUSY", 17, 17, &umr_bitfield_default }, + { "IA_BUSY_NO_DMA", 18, 18, &umr_bitfield_default }, + { "IA_BUSY", 19, 19, &umr_bitfield_default }, + { "SX_BUSY", 20, 20, &umr_bitfield_default }, + { "WD_BUSY", 21, 21, &umr_bitfield_default }, + { "SPI_BUSY", 22, 22, &umr_bitfield_default }, + { "BCI_BUSY", 23, 23, &umr_bitfield_default }, + { "SC_BUSY", 24, 24, &umr_bitfield_default }, + { "PA_BUSY", 25, 25, &umr_bitfield_default }, + { "DB_BUSY", 26, 26, &umr_bitfield_default }, + { "CP_COHERENCY_BUSY", 28, 28, &umr_bitfield_default }, + { "CP_BUSY", 29, 29, &umr_bitfield_default }, + { "CB_BUSY", 30, 30, &umr_bitfield_default }, + { "GUI_ACTIVE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRBM_STATUS_SE0[] = { + { "DB_CLEAN", 1, 1, &umr_bitfield_default }, + { "CB_CLEAN", 2, 2, &umr_bitfield_default }, + { "RMI_BUSY", 21, 21, &umr_bitfield_default }, + { "BCI_BUSY", 22, 22, &umr_bitfield_default }, + { "VGT_BUSY", 23, 23, &umr_bitfield_default }, + { "PA_BUSY", 24, 24, &umr_bitfield_default }, + { "TA_BUSY", 25, 25, &umr_bitfield_default }, + { "SX_BUSY", 26, 26, &umr_bitfield_default }, + { "SPI_BUSY", 27, 27, &umr_bitfield_default }, + { "SC_BUSY", 29, 29, &umr_bitfield_default }, + { "DB_BUSY", 30, 30, &umr_bitfield_default }, + { "CB_BUSY", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRBM_STATUS_SE1[] = { + { "DB_CLEAN", 1, 1, &umr_bitfield_default }, + { "CB_CLEAN", 2, 2, &umr_bitfield_default }, + { "RMI_BUSY", 21, 21, &umr_bitfield_default }, + { "BCI_BUSY", 22, 22, &umr_bitfield_default }, + { "VGT_BUSY", 23, 23, &umr_bitfield_default }, + { "PA_BUSY", 24, 24, &umr_bitfield_default }, + { "TA_BUSY", 25, 25, &umr_bitfield_default }, + { "SX_BUSY", 26, 26, &umr_bitfield_default }, + { "SPI_BUSY", 27, 27, &umr_bitfield_default }, + { "SC_BUSY", 29, 29, &umr_bitfield_default }, + { "DB_BUSY", 30, 30, &umr_bitfield_default }, + { "CB_BUSY", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRBM_SOFT_RESET[] = { + { "SOFT_RESET_CP", 0, 0, &umr_bitfield_default }, + { "SOFT_RESET_RLC", 2, 2, &umr_bitfield_default }, + { "SOFT_RESET_GFX", 16, 16, &umr_bitfield_default }, + { "SOFT_RESET_CPF", 17, 17, &umr_bitfield_default }, + { "SOFT_RESET_CPC", 18, 18, &umr_bitfield_default }, + { "SOFT_RESET_CPG", 19, 19, &umr_bitfield_default }, + { "SOFT_RESET_CAC", 20, 20, &umr_bitfield_default }, + { "SOFT_RESET_CPAXI", 21, 21, &umr_bitfield_default }, + { "SOFT_RESET_EA", 22, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRBM_CGTT_CLK_CNTL[] = { + { "ON_DELAY", 0, 3, &umr_bitfield_default }, + { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE7", 16, 16, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE6", 17, 17, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE5", 18, 18, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE4", 19, 19, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE3", 20, 20, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE2", 21, 21, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE1", 22, 22, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE0", 23, 23, &umr_bitfield_default }, + { "SOFT_OVERRIDE_DYN", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRBM_GFX_CLKEN_CNTL[] = { + { "PREFIX_DELAY_CNT", 0, 3, &umr_bitfield_default }, + { "POST_DELAY_CNT", 8, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRBM_WAIT_IDLE_CLOCKS[] = { + { "WAIT_IDLE_CLOCKS", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRBM_STATUS_SE2[] = { + { "DB_CLEAN", 1, 1, &umr_bitfield_default }, + { "CB_CLEAN", 2, 2, &umr_bitfield_default }, + { "RMI_BUSY", 21, 21, &umr_bitfield_default }, + { "BCI_BUSY", 22, 22, &umr_bitfield_default }, + { "VGT_BUSY", 23, 23, &umr_bitfield_default }, + { "PA_BUSY", 24, 24, &umr_bitfield_default }, + { "TA_BUSY", 25, 25, &umr_bitfield_default }, + { "SX_BUSY", 26, 26, &umr_bitfield_default }, + { "SPI_BUSY", 27, 27, &umr_bitfield_default }, + { "SC_BUSY", 29, 29, &umr_bitfield_default }, + { "DB_BUSY", 30, 30, &umr_bitfield_default }, + { "CB_BUSY", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRBM_STATUS_SE3[] = { + { "DB_CLEAN", 1, 1, &umr_bitfield_default }, + { "CB_CLEAN", 2, 2, &umr_bitfield_default }, + { "RMI_BUSY", 21, 21, &umr_bitfield_default }, + { "BCI_BUSY", 22, 22, &umr_bitfield_default }, + { "VGT_BUSY", 23, 23, &umr_bitfield_default }, + { "PA_BUSY", 24, 24, &umr_bitfield_default }, + { "TA_BUSY", 25, 25, &umr_bitfield_default }, + { "SX_BUSY", 26, 26, &umr_bitfield_default }, + { "SPI_BUSY", 27, 27, &umr_bitfield_default }, + { "SC_BUSY", 29, 29, &umr_bitfield_default }, + { "DB_BUSY", 30, 30, &umr_bitfield_default }, + { "CB_BUSY", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRBM_READ_ERROR[] = { + { "READ_ADDRESS", 2, 17, &umr_bitfield_default }, + { "READ_PIPEID", 20, 21, &umr_bitfield_default }, + { "READ_MEID", 22, 23, &umr_bitfield_default }, + { "READ_ERROR", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRBM_READ_ERROR2[] = { + { "READ_REQUESTER_CPF", 16, 16, &umr_bitfield_default }, + { "READ_REQUESTER_RSMU", 17, 17, &umr_bitfield_default }, + { "READ_REQUESTER_RLC", 18, 18, &umr_bitfield_default }, + { "READ_REQUESTER_GDS_DMA", 19, 19, &umr_bitfield_default }, + { "READ_REQUESTER_ME0PIPE0_CF", 20, 20, &umr_bitfield_default }, + { "READ_REQUESTER_ME0PIPE0_PF", 21, 21, &umr_bitfield_default }, + { "READ_REQUESTER_ME0PIPE1_CF", 22, 22, &umr_bitfield_default }, + { "READ_REQUESTER_ME0PIPE1_PF", 23, 23, &umr_bitfield_default }, + { "READ_REQUESTER_ME1PIPE0", 24, 24, &umr_bitfield_default }, + { "READ_REQUESTER_ME1PIPE1", 25, 25, &umr_bitfield_default }, + { "READ_REQUESTER_ME1PIPE2", 26, 26, &umr_bitfield_default }, + { "READ_REQUESTER_ME1PIPE3", 27, 27, &umr_bitfield_default }, + { "READ_REQUESTER_ME2PIPE0", 28, 28, &umr_bitfield_default }, + { "READ_REQUESTER_ME2PIPE1", 29, 29, &umr_bitfield_default }, + { "READ_REQUESTER_ME2PIPE2", 30, 30, &umr_bitfield_default }, + { "READ_REQUESTER_ME2PIPE3", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRBM_INT_CNTL[] = { + { "RDERR_INT_ENABLE", 0, 0, &umr_bitfield_default }, + { "GUI_IDLE_INT_ENABLE", 19, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRBM_TRAP_OP[] = { + { "RW", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRBM_TRAP_ADDR[] = { + { "DATA", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRBM_TRAP_ADDR_MSK[] = { + { "DATA", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRBM_TRAP_WD[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRBM_TRAP_WD_MSK[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRBM_DSM_BYPASS[] = { + { "BYPASS_BITS", 0, 1, &umr_bitfield_default }, + { "BYPASS_EN", 2, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRBM_WRITE_ERROR[] = { + { "WRITE_REQUESTER_RLC", 0, 0, &umr_bitfield_default }, + { "WRITE_REQUESTER_RSMU", 1, 1, &umr_bitfield_default }, + { "WRITE_SSRCID", 2, 4, &umr_bitfield_default }, + { "WRITE_VFID", 5, 8, &umr_bitfield_default }, + { "WRITE_VF", 12, 12, &umr_bitfield_default }, + { "WRITE_VMID", 13, 16, &umr_bitfield_default }, + { "WRITE_PIPEID", 20, 21, &umr_bitfield_default }, + { "WRITE_MEID", 22, 23, &umr_bitfield_default }, + { "WRITE_ERROR", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRBM_IOV_ERROR[] = { + { "IOV_ADDR", 2, 19, &umr_bitfield_default }, + { "IOV_VFID", 20, 25, &umr_bitfield_default }, + { "IOV_VF", 26, 26, &umr_bitfield_default }, + { "IOV_OP", 27, 27, &umr_bitfield_default }, + { "IOV_ERROR", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRBM_CHIP_REVISION[] = { + { "CHIP_REVISION", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRBM_GFX_CNTL[] = { + { "PIPEID", 0, 1, &umr_bitfield_default }, + { "MEID", 2, 3, &umr_bitfield_default }, + { "VMID", 4, 7, &umr_bitfield_default }, + { "QUEUEID", 8, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRBM_RSMU_CFG[] = { + { "APERTURE_ID", 0, 11, &umr_bitfield_default }, + { "QOS", 12, 15, &umr_bitfield_default }, + { "POSTED_WR", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRBM_IH_CREDIT[] = { + { "CREDIT_VALUE", 0, 1, &umr_bitfield_default }, + { "IH_CLIENT_ID", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRBM_PWR_CNTL2[] = { + { "PWR_REQUEST_HALT", 16, 16, &umr_bitfield_default }, + { "PWR_GFX3D_REQUEST_HALT", 20, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRBM_UTCL2_INVAL_RANGE_START[] = { + { "DATA", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRBM_UTCL2_INVAL_RANGE_END[] = { + { "DATA", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRBM_RSMU_READ_ERROR[] = { + { "RSMU_READ_ADDRESS", 2, 19, &umr_bitfield_default }, + { "RSMU_READ_VF", 20, 20, &umr_bitfield_default }, + { "RSMU_READ_VFID", 21, 26, &umr_bitfield_default }, + { "RSMU_READ_ERROR_TYPE", 27, 27, &umr_bitfield_default }, + { "RSMU_READ_ERROR", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRBM_CHICKEN_BITS[] = { + { "DISABLE_CP_VMID_RESET_REQ", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRBM_NOWHERE[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRBM_SCRATCH_REG0[] = { + { "SCRATCH_REG0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRBM_SCRATCH_REG1[] = { + { "SCRATCH_REG1", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRBM_SCRATCH_REG2[] = { + { "SCRATCH_REG2", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRBM_SCRATCH_REG3[] = { + { "SCRATCH_REG3", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRBM_SCRATCH_REG4[] = { + { "SCRATCH_REG4", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRBM_SCRATCH_REG5[] = { + { "SCRATCH_REG5", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRBM_SCRATCH_REG6[] = { + { "SCRATCH_REG6", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRBM_SCRATCH_REG7[] = { + { "SCRATCH_REG7", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_CPC_STATUS[] = { + { "MEC1_BUSY", 0, 0, &umr_bitfield_default }, + { "MEC2_BUSY", 1, 1, &umr_bitfield_default }, + { "DC0_BUSY", 2, 2, &umr_bitfield_default }, + { "DC1_BUSY", 3, 3, &umr_bitfield_default }, + { "RCIU1_BUSY", 4, 4, &umr_bitfield_default }, + { "RCIU2_BUSY", 5, 5, &umr_bitfield_default }, + { "ROQ1_BUSY", 6, 6, &umr_bitfield_default }, + { "ROQ2_BUSY", 7, 7, &umr_bitfield_default }, + { "TCIU_BUSY", 10, 10, &umr_bitfield_default }, + { "SCRATCH_RAM_BUSY", 11, 11, &umr_bitfield_default }, + { "QU_BUSY", 12, 12, &umr_bitfield_default }, + { "UTCL2IU_BUSY", 13, 13, &umr_bitfield_default }, + { "SAVE_RESTORE_BUSY", 14, 14, &umr_bitfield_default }, + { "CPG_CPC_BUSY", 29, 29, &umr_bitfield_default }, + { "CPF_CPC_BUSY", 30, 30, &umr_bitfield_default }, + { "CPC_BUSY", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_CPC_BUSY_STAT[] = { + { "MEC1_LOAD_BUSY", 0, 0, &umr_bitfield_default }, + { "MEC1_SEMAPOHRE_BUSY", 1, 1, &umr_bitfield_default }, + { "MEC1_MUTEX_BUSY", 2, 2, &umr_bitfield_default }, + { "MEC1_MESSAGE_BUSY", 3, 3, &umr_bitfield_default }, + { "MEC1_EOP_QUEUE_BUSY", 4, 4, &umr_bitfield_default }, + { "MEC1_IQ_QUEUE_BUSY", 5, 5, &umr_bitfield_default }, + { "MEC1_IB_QUEUE_BUSY", 6, 6, &umr_bitfield_default }, + { "MEC1_TC_BUSY", 7, 7, &umr_bitfield_default }, + { "MEC1_DMA_BUSY", 8, 8, &umr_bitfield_default }, + { "MEC1_PARTIAL_FLUSH_BUSY", 9, 9, &umr_bitfield_default }, + { "MEC1_PIPE0_BUSY", 10, 10, &umr_bitfield_default }, + { "MEC1_PIPE1_BUSY", 11, 11, &umr_bitfield_default }, + { "MEC1_PIPE2_BUSY", 12, 12, &umr_bitfield_default }, + { "MEC1_PIPE3_BUSY", 13, 13, &umr_bitfield_default }, + { "MEC2_LOAD_BUSY", 16, 16, &umr_bitfield_default }, + { "MEC2_SEMAPOHRE_BUSY", 17, 17, &umr_bitfield_default }, + { "MEC2_MUTEX_BUSY", 18, 18, &umr_bitfield_default }, + { "MEC2_MESSAGE_BUSY", 19, 19, &umr_bitfield_default }, + { "MEC2_EOP_QUEUE_BUSY", 20, 20, &umr_bitfield_default }, + { "MEC2_IQ_QUEUE_BUSY", 21, 21, &umr_bitfield_default }, + { "MEC2_IB_QUEUE_BUSY", 22, 22, &umr_bitfield_default }, + { "MEC2_TC_BUSY", 23, 23, &umr_bitfield_default }, + { "MEC2_DMA_BUSY", 24, 24, &umr_bitfield_default }, + { "MEC2_PARTIAL_FLUSH_BUSY", 25, 25, &umr_bitfield_default }, + { "MEC2_PIPE0_BUSY", 26, 26, &umr_bitfield_default }, + { "MEC2_PIPE1_BUSY", 27, 27, &umr_bitfield_default }, + { "MEC2_PIPE2_BUSY", 28, 28, &umr_bitfield_default }, + { "MEC2_PIPE3_BUSY", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_CPC_STALLED_STAT1[] = { + { "RCIU_TX_FREE_STALL", 3, 3, &umr_bitfield_default }, + { "RCIU_PRIV_VIOLATION", 4, 4, &umr_bitfield_default }, + { "TCIU_TX_FREE_STALL", 6, 6, &umr_bitfield_default }, + { "MEC1_DECODING_PACKET", 8, 8, &umr_bitfield_default }, + { "MEC1_WAIT_ON_RCIU", 9, 9, &umr_bitfield_default }, + { "MEC1_WAIT_ON_RCIU_READ", 10, 10, &umr_bitfield_default }, + { "MEC1_WAIT_ON_ROQ_DATA", 13, 13, &umr_bitfield_default }, + { "MEC2_DECODING_PACKET", 16, 16, &umr_bitfield_default }, + { "MEC2_WAIT_ON_RCIU", 17, 17, &umr_bitfield_default }, + { "MEC2_WAIT_ON_RCIU_READ", 18, 18, &umr_bitfield_default }, + { "MEC2_WAIT_ON_ROQ_DATA", 21, 21, &umr_bitfield_default }, + { "UTCL2IU_WAITING_ON_FREE", 22, 22, &umr_bitfield_default }, + { "UTCL2IU_WAITING_ON_TAGS", 23, 23, &umr_bitfield_default }, + { "UTCL1_WAITING_ON_TRANS", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_CPF_STATUS[] = { + { "POST_WPTR_GFX_BUSY", 0, 0, &umr_bitfield_default }, + { "CSF_BUSY", 1, 1, &umr_bitfield_default }, + { "ROQ_ALIGN_BUSY", 4, 4, &umr_bitfield_default }, + { "ROQ_RING_BUSY", 5, 5, &umr_bitfield_default }, + { "ROQ_INDIRECT1_BUSY", 6, 6, &umr_bitfield_default }, + { "ROQ_INDIRECT2_BUSY", 7, 7, &umr_bitfield_default }, + { "ROQ_STATE_BUSY", 8, 8, &umr_bitfield_default }, + { "ROQ_CE_RING_BUSY", 9, 9, &umr_bitfield_default }, + { "ROQ_CE_INDIRECT1_BUSY", 10, 10, &umr_bitfield_default }, + { "ROQ_CE_INDIRECT2_BUSY", 11, 11, &umr_bitfield_default }, + { "SEMAPHORE_BUSY", 12, 12, &umr_bitfield_default }, + { "INTERRUPT_BUSY", 13, 13, &umr_bitfield_default }, + { "TCIU_BUSY", 14, 14, &umr_bitfield_default }, + { "HQD_BUSY", 15, 15, &umr_bitfield_default }, + { "PRT_BUSY", 16, 16, &umr_bitfield_default }, + { "UTCL2IU_BUSY", 17, 17, &umr_bitfield_default }, + { "CPF_GFX_BUSY", 26, 26, &umr_bitfield_default }, + { "CPF_CMP_BUSY", 27, 27, &umr_bitfield_default }, + { "GRBM_CPF_STAT_BUSY", 28, 29, &umr_bitfield_default }, + { "CPC_CPF_BUSY", 30, 30, &umr_bitfield_default }, + { "CPF_BUSY", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_CPF_BUSY_STAT[] = { + { "REG_BUS_FIFO_BUSY", 0, 0, &umr_bitfield_default }, + { "CSF_RING_BUSY", 1, 1, &umr_bitfield_default }, + { "CSF_INDIRECT1_BUSY", 2, 2, &umr_bitfield_default }, + { "CSF_INDIRECT2_BUSY", 3, 3, &umr_bitfield_default }, + { "CSF_STATE_BUSY", 4, 4, &umr_bitfield_default }, + { "CSF_CE_INDR1_BUSY", 5, 5, &umr_bitfield_default }, + { "CSF_CE_INDR2_BUSY", 6, 6, &umr_bitfield_default }, + { "CSF_ARBITER_BUSY", 7, 7, &umr_bitfield_default }, + { "CSF_INPUT_BUSY", 8, 8, &umr_bitfield_default }, + { "OUTSTANDING_READ_TAGS", 9, 9, &umr_bitfield_default }, + { "HPD_PROCESSING_EOP_BUSY", 11, 11, &umr_bitfield_default }, + { "HQD_DISPATCH_BUSY", 12, 12, &umr_bitfield_default }, + { "HQD_IQ_TIMER_BUSY", 13, 13, &umr_bitfield_default }, + { "HQD_DMA_OFFLOAD_BUSY", 14, 14, &umr_bitfield_default }, + { "HQD_WAIT_SEMAPHORE_BUSY", 15, 15, &umr_bitfield_default }, + { "HQD_SIGNAL_SEMAPHORE_BUSY", 16, 16, &umr_bitfield_default }, + { "HQD_MESSAGE_BUSY", 17, 17, &umr_bitfield_default }, + { "HQD_PQ_FETCHER_BUSY", 18, 18, &umr_bitfield_default }, + { "HQD_IB_FETCHER_BUSY", 19, 19, &umr_bitfield_default }, + { "HQD_IQ_FETCHER_BUSY", 20, 20, &umr_bitfield_default }, + { "HQD_EOP_FETCHER_BUSY", 21, 21, &umr_bitfield_default }, + { "HQD_CONSUMED_RPTR_BUSY", 22, 22, &umr_bitfield_default }, + { "HQD_FETCHER_ARB_BUSY", 23, 23, &umr_bitfield_default }, + { "HQD_ROQ_ALIGN_BUSY", 24, 24, &umr_bitfield_default }, + { "HQD_ROQ_EOP_BUSY", 25, 25, &umr_bitfield_default }, + { "HQD_ROQ_IQ_BUSY", 26, 26, &umr_bitfield_default }, + { "HQD_ROQ_PQ_BUSY", 27, 27, &umr_bitfield_default }, + { "HQD_ROQ_IB_BUSY", 28, 28, &umr_bitfield_default }, + { "HQD_WPTR_POLL_BUSY", 29, 29, &umr_bitfield_default }, + { "HQD_PQ_BUSY", 30, 30, &umr_bitfield_default }, + { "HQD_IB_BUSY", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_CPF_STALLED_STAT1[] = { + { "RING_FETCHING_DATA", 0, 0, &umr_bitfield_default }, + { "INDR1_FETCHING_DATA", 1, 1, &umr_bitfield_default }, + { "INDR2_FETCHING_DATA", 2, 2, &umr_bitfield_default }, + { "STATE_FETCHING_DATA", 3, 3, &umr_bitfield_default }, + { "TCIU_WAITING_ON_FREE", 5, 5, &umr_bitfield_default }, + { "TCIU_WAITING_ON_TAGS", 6, 6, &umr_bitfield_default }, + { "UTCL2IU_WAITING_ON_FREE", 7, 7, &umr_bitfield_default }, + { "UTCL2IU_WAITING_ON_TAGS", 8, 8, &umr_bitfield_default }, + { "GFX_UTCL1_WAITING_ON_TRANS", 9, 9, &umr_bitfield_default }, + { "CMP_UTCL1_WAITING_ON_TRANS", 10, 10, &umr_bitfield_default }, + { "RCIU_WAITING_ON_FREE", 11, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_CPC_GRBM_FREE_COUNT[] = { + { "FREE_COUNT", 0, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_MEC_CNTL[] = { + { "MEC_INVALIDATE_ICACHE", 4, 4, &umr_bitfield_default }, + { "MEC_ME1_PIPE0_RESET", 16, 16, &umr_bitfield_default }, + { "MEC_ME1_PIPE1_RESET", 17, 17, &umr_bitfield_default }, + { "MEC_ME1_PIPE2_RESET", 18, 18, &umr_bitfield_default }, + { "MEC_ME1_PIPE3_RESET", 19, 19, &umr_bitfield_default }, + { "MEC_ME2_PIPE0_RESET", 20, 20, &umr_bitfield_default }, + { "MEC_ME2_PIPE1_RESET", 21, 21, &umr_bitfield_default }, + { "MEC_ME2_HALT", 28, 28, &umr_bitfield_default }, + { "MEC_ME2_STEP", 29, 29, &umr_bitfield_default }, + { "MEC_ME1_HALT", 30, 30, &umr_bitfield_default }, + { "MEC_ME1_STEP", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_MEC_ME1_HEADER_DUMP[] = { + { "HEADER_DUMP", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_MEC_ME2_HEADER_DUMP[] = { + { "HEADER_DUMP", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_CPC_SCRATCH_INDEX[] = { + { "SCRATCH_INDEX", 0, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_CPC_SCRATCH_DATA[] = { + { "SCRATCH_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_CPF_GRBM_FREE_COUNT[] = { + { "FREE_COUNT", 0, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_CPC_HALT_HYST_COUNT[] = { + { "COUNT", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_PRT_LOD_STATS_CNTL0[] = { + { "BU_SIZE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_PRT_LOD_STATS_CNTL1[] = { + { "BASE_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_PRT_LOD_STATS_CNTL2[] = { + { "BASE_HI", 0, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_PRT_LOD_STATS_CNTL3[] = { + { "INTERVAL", 2, 9, &umr_bitfield_default }, + { "RESET_CNT", 10, 17, &umr_bitfield_default }, + { "RESET_FORCE", 18, 18, &umr_bitfield_default }, + { "REPORT_AND_RESET", 19, 19, &umr_bitfield_default }, + { "MC_VMID", 23, 26, &umr_bitfield_default }, + { "CACHE_POLICY", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_CE_COMPARE_COUNT[] = { + { "COMPARE_COUNT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_CE_DE_COUNT[] = { + { "DRAW_ENGINE_COUNT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_DE_CE_COUNT[] = { + { "CONST_ENGINE_COUNT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_DE_LAST_INVAL_COUNT[] = { + { "LAST_INVAL_COUNT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_DE_DE_COUNT[] = { + { "DRAW_ENGINE_COUNT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_STALLED_STAT3[] = { + { "CE_TO_CSF_NOT_RDY_TO_RCV", 0, 0, &umr_bitfield_default }, + { "CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV", 1, 1, &umr_bitfield_default }, + { "CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER", 2, 2, &umr_bitfield_default }, + { "CE_TO_RAM_INIT_NOT_RDY", 3, 3, &umr_bitfield_default }, + { "CE_TO_RAM_DUMP_NOT_RDY", 4, 4, &umr_bitfield_default }, + { "CE_TO_RAM_WRITE_NOT_RDY", 5, 5, &umr_bitfield_default }, + { "CE_TO_INC_FIFO_NOT_RDY_TO_RCV", 6, 6, &umr_bitfield_default }, + { "CE_TO_WR_FIFO_NOT_RDY_TO_RCV", 7, 7, &umr_bitfield_default }, + { "CE_WAITING_ON_BUFFER_DATA", 10, 10, &umr_bitfield_default }, + { "CE_WAITING_ON_CE_BUFFER_FLAG", 11, 11, &umr_bitfield_default }, + { "CE_WAITING_ON_DE_COUNTER", 12, 12, &umr_bitfield_default }, + { "CE_WAITING_ON_DE_COUNTER_UNDERFLOW", 13, 13, &umr_bitfield_default }, + { "TCIU_WAITING_ON_FREE", 14, 14, &umr_bitfield_default }, + { "TCIU_WAITING_ON_TAGS", 15, 15, &umr_bitfield_default }, + { "CE_STALLED_ON_TC_WR_CONFIRM", 16, 16, &umr_bitfield_default }, + { "CE_STALLED_ON_ATOMIC_RTN_DATA", 17, 17, &umr_bitfield_default }, + { "UTCL2IU_WAITING_ON_FREE", 18, 18, &umr_bitfield_default }, + { "UTCL2IU_WAITING_ON_TAGS", 19, 19, &umr_bitfield_default }, + { "UTCL1_WAITING_ON_TRANS", 20, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_STALLED_STAT1[] = { + { "RBIU_TO_DMA_NOT_RDY_TO_RCV", 0, 0, &umr_bitfield_default }, + { "RBIU_TO_SEM_NOT_RDY_TO_RCV", 2, 2, &umr_bitfield_default }, + { "RBIU_TO_MEMWR_NOT_RDY_TO_RCV", 4, 4, &umr_bitfield_default }, + { "ME_HAS_ACTIVE_CE_BUFFER_FLAG", 10, 10, &umr_bitfield_default }, + { "ME_HAS_ACTIVE_DE_BUFFER_FLAG", 11, 11, &umr_bitfield_default }, + { "ME_STALLED_ON_TC_WR_CONFIRM", 12, 12, &umr_bitfield_default }, + { "ME_STALLED_ON_ATOMIC_RTN_DATA", 13, 13, &umr_bitfield_default }, + { "ME_WAITING_ON_TC_READ_DATA", 14, 14, &umr_bitfield_default }, + { "ME_WAITING_ON_REG_READ_DATA", 15, 15, &umr_bitfield_default }, + { "RCIU_WAITING_ON_GDS_FREE", 23, 23, &umr_bitfield_default }, + { "RCIU_WAITING_ON_GRBM_FREE", 24, 24, &umr_bitfield_default }, + { "RCIU_WAITING_ON_VGT_FREE", 25, 25, &umr_bitfield_default }, + { "RCIU_STALLED_ON_ME_READ", 26, 26, &umr_bitfield_default }, + { "RCIU_STALLED_ON_DMA_READ", 27, 27, &umr_bitfield_default }, + { "RCIU_STALLED_ON_APPEND_READ", 28, 28, &umr_bitfield_default }, + { "RCIU_HALTED_BY_REG_VIOLATION", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_STALLED_STAT2[] = { + { "PFP_TO_CSF_NOT_RDY_TO_RCV", 0, 0, &umr_bitfield_default }, + { "PFP_TO_MEQ_NOT_RDY_TO_RCV", 1, 1, &umr_bitfield_default }, + { "PFP_TO_RCIU_NOT_RDY_TO_RCV", 2, 2, &umr_bitfield_default }, + { "PFP_TO_VGT_WRITES_PENDING", 4, 4, &umr_bitfield_default }, + { "PFP_RCIU_READ_PENDING", 5, 5, &umr_bitfield_default }, + { "PFP_WAITING_ON_BUFFER_DATA", 8, 8, &umr_bitfield_default }, + { "ME_WAIT_ON_CE_COUNTER", 9, 9, &umr_bitfield_default }, + { "ME_WAIT_ON_AVAIL_BUFFER", 10, 10, &umr_bitfield_default }, + { "GFX_CNTX_NOT_AVAIL_TO_ME", 11, 11, &umr_bitfield_default }, + { "ME_RCIU_NOT_RDY_TO_RCV", 12, 12, &umr_bitfield_default }, + { "ME_TO_CONST_NOT_RDY_TO_RCV", 13, 13, &umr_bitfield_default }, + { "ME_WAITING_DATA_FROM_PFP", 14, 14, &umr_bitfield_default }, + { "ME_WAITING_ON_PARTIAL_FLUSH", 15, 15, &umr_bitfield_default }, + { "MEQ_TO_ME_NOT_RDY_TO_RCV", 16, 16, &umr_bitfield_default }, + { "STQ_TO_ME_NOT_RDY_TO_RCV", 17, 17, &umr_bitfield_default }, + { "ME_WAITING_DATA_FROM_STQ", 18, 18, &umr_bitfield_default }, + { "PFP_STALLED_ON_TC_WR_CONFIRM", 19, 19, &umr_bitfield_default }, + { "PFP_STALLED_ON_ATOMIC_RTN_DATA", 20, 20, &umr_bitfield_default }, + { "EOPD_FIFO_NEEDS_SC_EOP_DONE", 21, 21, &umr_bitfield_default }, + { "EOPD_FIFO_NEEDS_WR_CONFIRM", 22, 22, &umr_bitfield_default }, + { "STRMO_WR_OF_PRIM_DATA_PENDING", 23, 23, &umr_bitfield_default }, + { "PIPE_STATS_WR_DATA_PENDING", 24, 24, &umr_bitfield_default }, + { "APPEND_RDY_WAIT_ON_CS_DONE", 25, 25, &umr_bitfield_default }, + { "APPEND_RDY_WAIT_ON_PS_DONE", 26, 26, &umr_bitfield_default }, + { "APPEND_WAIT_ON_WR_CONFIRM", 27, 27, &umr_bitfield_default }, + { "APPEND_ACTIVE_PARTITION", 28, 28, &umr_bitfield_default }, + { "APPEND_WAITING_TO_SEND_MEMWRITE", 29, 29, &umr_bitfield_default }, + { "SURF_SYNC_NEEDS_IDLE_CNTXS", 30, 30, &umr_bitfield_default }, + { "SURF_SYNC_NEEDS_ALL_CLEAN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_BUSY_STAT[] = { + { "REG_BUS_FIFO_BUSY", 0, 0, &umr_bitfield_default }, + { "COHER_CNT_NEQ_ZERO", 6, 6, &umr_bitfield_default }, + { "PFP_PARSING_PACKETS", 7, 7, &umr_bitfield_default }, + { "ME_PARSING_PACKETS", 8, 8, &umr_bitfield_default }, + { "RCIU_PFP_BUSY", 9, 9, &umr_bitfield_default }, + { "RCIU_ME_BUSY", 10, 10, &umr_bitfield_default }, + { "SEM_CMDFIFO_NOT_EMPTY", 12, 12, &umr_bitfield_default }, + { "SEM_FAILED_AND_HOLDING", 13, 13, &umr_bitfield_default }, + { "SEM_POLLING_FOR_PASS", 14, 14, &umr_bitfield_default }, + { "GFX_CONTEXT_BUSY", 15, 15, &umr_bitfield_default }, + { "ME_PARSER_BUSY", 17, 17, &umr_bitfield_default }, + { "EOP_DONE_BUSY", 18, 18, &umr_bitfield_default }, + { "STRM_OUT_BUSY", 19, 19, &umr_bitfield_default }, + { "PIPE_STATS_BUSY", 20, 20, &umr_bitfield_default }, + { "RCIU_CE_BUSY", 21, 21, &umr_bitfield_default }, + { "CE_PARSING_PACKETS", 22, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_STAT[] = { + { "ROQ_RING_BUSY", 9, 9, &umr_bitfield_default }, + { "ROQ_INDIRECT1_BUSY", 10, 10, &umr_bitfield_default }, + { "ROQ_INDIRECT2_BUSY", 11, 11, &umr_bitfield_default }, + { "ROQ_STATE_BUSY", 12, 12, &umr_bitfield_default }, + { "DC_BUSY", 13, 13, &umr_bitfield_default }, + { "UTCL2IU_BUSY", 14, 14, &umr_bitfield_default }, + { "PFP_BUSY", 15, 15, &umr_bitfield_default }, + { "MEQ_BUSY", 16, 16, &umr_bitfield_default }, + { "ME_BUSY", 17, 17, &umr_bitfield_default }, + { "QUERY_BUSY", 18, 18, &umr_bitfield_default }, + { "SEMAPHORE_BUSY", 19, 19, &umr_bitfield_default }, + { "INTERRUPT_BUSY", 20, 20, &umr_bitfield_default }, + { "SURFACE_SYNC_BUSY", 21, 21, &umr_bitfield_default }, + { "DMA_BUSY", 22, 22, &umr_bitfield_default }, + { "RCIU_BUSY", 23, 23, &umr_bitfield_default }, + { "SCRATCH_RAM_BUSY", 24, 24, &umr_bitfield_default }, + { "CE_BUSY", 26, 26, &umr_bitfield_default }, + { "TCIU_BUSY", 27, 27, &umr_bitfield_default }, + { "ROQ_CE_RING_BUSY", 28, 28, &umr_bitfield_default }, + { "ROQ_CE_INDIRECT1_BUSY", 29, 29, &umr_bitfield_default }, + { "ROQ_CE_INDIRECT2_BUSY", 30, 30, &umr_bitfield_default }, + { "CP_BUSY", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ME_HEADER_DUMP[] = { + { "ME_HEADER_DUMP", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_PFP_HEADER_DUMP[] = { + { "PFP_HEADER_DUMP", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_GRBM_FREE_COUNT[] = { + { "FREE_COUNT", 0, 5, &umr_bitfield_default }, + { "FREE_COUNT_GDS", 8, 13, &umr_bitfield_default }, + { "FREE_COUNT_PFP", 16, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_CE_HEADER_DUMP[] = { + { "CE_HEADER_DUMP", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_PFP_INSTR_PNTR[] = { + { "INSTR_PNTR", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ME_INSTR_PNTR[] = { + { "INSTR_PNTR", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_CE_INSTR_PNTR[] = { + { "INSTR_PNTR", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_MEC1_INSTR_PNTR[] = { + { "INSTR_PNTR", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_MEC2_INSTR_PNTR[] = { + { "INSTR_PNTR", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_CSF_STAT[] = { + { "BUFFER_REQUEST_COUNT", 8, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ME_CNTL[] = { + { "CE_INVALIDATE_ICACHE", 4, 4, &umr_bitfield_default }, + { "PFP_INVALIDATE_ICACHE", 6, 6, &umr_bitfield_default }, + { "ME_INVALIDATE_ICACHE", 8, 8, &umr_bitfield_default }, + { "CE_PIPE0_RESET", 16, 16, &umr_bitfield_default }, + { "CE_PIPE1_RESET", 17, 17, &umr_bitfield_default }, + { "PFP_PIPE0_RESET", 18, 18, &umr_bitfield_default }, + { "PFP_PIPE1_RESET", 19, 19, &umr_bitfield_default }, + { "ME_PIPE0_RESET", 20, 20, &umr_bitfield_default }, + { "ME_PIPE1_RESET", 21, 21, &umr_bitfield_default }, + { "CE_HALT", 24, 24, &umr_bitfield_default }, + { "CE_STEP", 25, 25, &umr_bitfield_default }, + { "PFP_HALT", 26, 26, &umr_bitfield_default }, + { "PFP_STEP", 27, 27, &umr_bitfield_default }, + { "ME_HALT", 28, 28, &umr_bitfield_default }, + { "ME_STEP", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_CNTX_STAT[] = { + { "ACTIVE_HP3D_CONTEXTS", 0, 7, &umr_bitfield_default }, + { "CURRENT_HP3D_CONTEXT", 8, 10, &umr_bitfield_default }, + { "ACTIVE_GFX_CONTEXTS", 20, 27, &umr_bitfield_default }, + { "CURRENT_GFX_CONTEXT", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ME_PREEMPTION[] = { + { "OBSOLETE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ROQ_THRESHOLDS[] = { + { "IB1_START", 0, 7, &umr_bitfield_default }, + { "IB2_START", 8, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_MEQ_STQ_THRESHOLD[] = { + { "STQ_START", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_RB2_RPTR[] = { + { "RB_RPTR", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_RB1_RPTR[] = { + { "RB_RPTR", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_RB0_RPTR[] = { + { "RB_RPTR", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_RB_RPTR[] = { + { "RB_RPTR", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_RB_WPTR_DELAY[] = { + { "PRE_WRITE_TIMER", 0, 27, &umr_bitfield_default }, + { "PRE_WRITE_LIMIT", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_RB_WPTR_POLL_CNTL[] = { + { "POLL_FREQUENCY", 0, 15, &umr_bitfield_default }, + { "IDLE_POLL_COUNT", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ROQ1_THRESHOLDS[] = { + { "RB1_START", 0, 7, &umr_bitfield_default }, + { "RB2_START", 8, 15, &umr_bitfield_default }, + { "R0_IB1_START", 16, 23, &umr_bitfield_default }, + { "R1_IB1_START", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ROQ2_THRESHOLDS[] = { + { "R2_IB1_START", 0, 7, &umr_bitfield_default }, + { "R0_IB2_START", 8, 15, &umr_bitfield_default }, + { "R1_IB2_START", 16, 23, &umr_bitfield_default }, + { "R2_IB2_START", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_STQ_THRESHOLDS[] = { + { "STQ0_START", 0, 7, &umr_bitfield_default }, + { "STQ1_START", 8, 15, &umr_bitfield_default }, + { "STQ2_START", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_QUEUE_THRESHOLDS[] = { + { "ROQ_IB1_START", 0, 5, &umr_bitfield_default }, + { "ROQ_IB2_START", 8, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_MEQ_THRESHOLDS[] = { + { "MEQ1_START", 0, 7, &umr_bitfield_default }, + { "MEQ2_START", 8, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ROQ_AVAIL[] = { + { "ROQ_CNT_RING", 0, 10, &umr_bitfield_default }, + { "ROQ_CNT_IB1", 16, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_STQ_AVAIL[] = { + { "STQ_CNT", 0, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ROQ2_AVAIL[] = { + { "ROQ_CNT_IB2", 0, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_MEQ_AVAIL[] = { + { "MEQ_CNT", 0, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_CMD_INDEX[] = { + { "CMD_INDEX", 0, 10, &umr_bitfield_default }, + { "CMD_ME_SEL", 12, 13, &umr_bitfield_default }, + { "CMD_QUEUE_SEL", 16, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_CMD_DATA[] = { + { "CMD_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ROQ_RB_STAT[] = { + { "ROQ_RPTR_PRIMARY", 0, 9, &umr_bitfield_default }, + { "ROQ_WPTR_PRIMARY", 16, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ROQ_IB1_STAT[] = { + { "ROQ_RPTR_INDIRECT1", 0, 9, &umr_bitfield_default }, + { "ROQ_WPTR_INDIRECT1", 16, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ROQ_IB2_STAT[] = { + { "ROQ_RPTR_INDIRECT2", 0, 9, &umr_bitfield_default }, + { "ROQ_WPTR_INDIRECT2", 16, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_STQ_STAT[] = { + { "STQ_RPTR", 0, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_STQ_WR_STAT[] = { + { "STQ_WPTR", 0, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_MEQ_STAT[] = { + { "MEQ_RPTR", 0, 9, &umr_bitfield_default }, + { "MEQ_WPTR", 16, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_CEQ1_AVAIL[] = { + { "CEQ_CNT_RING", 0, 10, &umr_bitfield_default }, + { "CEQ_CNT_IB1", 16, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_CEQ2_AVAIL[] = { + { "CEQ_CNT_IB2", 0, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_CE_ROQ_RB_STAT[] = { + { "CEQ_RPTR_PRIMARY", 0, 9, &umr_bitfield_default }, + { "CEQ_WPTR_PRIMARY", 16, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_CE_ROQ_IB1_STAT[] = { + { "CEQ_RPTR_INDIRECT1", 0, 9, &umr_bitfield_default }, + { "CEQ_WPTR_INDIRECT1", 16, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_CE_ROQ_IB2_STAT[] = { + { "CEQ_RPTR_INDIRECT2", 0, 9, &umr_bitfield_default }, + { "CEQ_WPTR_INDIRECT2", 16, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_VTX_VECT_EJECT_REG[] = { + { "PRIM_COUNT", 0, 6, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_DMA_DATA_FIFO_DEPTH[] = { + { "DMA_DATA_FIFO_DEPTH", 0, 8, &umr_bitfield_default }, + { "DMA2DRAW_FIFO_DEPTH", 9, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_DMA_REQ_FIFO_DEPTH[] = { + { "DMA_REQ_FIFO_DEPTH", 0, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_DRAW_INIT_FIFO_DEPTH[] = { + { "DRAW_INIT_FIFO_DEPTH", 0, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_LAST_COPY_STATE[] = { + { "SRC_STATE_ID", 0, 2, &umr_bitfield_default }, + { "DST_STATE_ID", 16, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_CACHE_INVALIDATION[] = { + { "CACHE_INVALIDATION", 0, 1, &umr_bitfield_default }, + { "DIS_INSTANCING_OPT", 4, 4, &umr_bitfield_default }, + { "VS_NO_EXTRA_BUFFER", 5, 5, &umr_bitfield_default }, + { "AUTO_INVLD_EN", 6, 7, &umr_bitfield_default }, + { "USE_GS_DONE", 9, 9, &umr_bitfield_default }, + { "DIS_RANGE_FULL_INVLD", 11, 11, &umr_bitfield_default }, + { "GS_LATE_ALLOC_EN", 12, 12, &umr_bitfield_default }, + { "STREAMOUT_FULL_FLUSH", 13, 13, &umr_bitfield_default }, + { "ES_LIMIT", 16, 20, &umr_bitfield_default }, + { "ENABLE_PING_PONG", 21, 21, &umr_bitfield_default }, + { "OPT_FLOW_CNTL_1", 22, 24, &umr_bitfield_default }, + { "OPT_FLOW_CNTL_2", 25, 27, &umr_bitfield_default }, + { "EN_WAVE_MERGE", 28, 28, &umr_bitfield_default }, + { "ENABLE_PING_PONG_EOI", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_STRMOUT_DELAY[] = { + { "SKIP_DELAY", 0, 7, &umr_bitfield_default }, + { "SE0_WD_DELAY", 8, 10, &umr_bitfield_default }, + { "SE1_WD_DELAY", 11, 13, &umr_bitfield_default }, + { "SE2_WD_DELAY", 14, 16, &umr_bitfield_default }, + { "SE3_WD_DELAY", 17, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_FIFO_DEPTHS[] = { + { "VS_DEALLOC_TBL_DEPTH", 0, 6, &umr_bitfield_default }, + { "RESERVED_0", 7, 7, &umr_bitfield_default }, + { "CLIPP_FIFO_DEPTH", 8, 21, &umr_bitfield_default }, + { "HSINPUT_FIFO_DEPTH", 22, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_GS_VERTEX_REUSE[] = { + { "VERT_REUSE", 0, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_MC_LAT_CNTL[] = { + { "MC_TIME_STAMP_RES", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIA_CNTL_STATUS[] = { + { "IA_BUSY", 0, 0, &umr_bitfield_default }, + { "IA_DMA_BUSY", 1, 1, &umr_bitfield_default }, + { "IA_DMA_REQ_BUSY", 2, 2, &umr_bitfield_default }, + { "IA_GRP_BUSY", 3, 3, &umr_bitfield_default }, + { "IA_ADC_BUSY", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_CNTL_STATUS[] = { + { "VGT_BUSY", 0, 0, &umr_bitfield_default }, + { "VGT_OUT_INDX_BUSY", 1, 1, &umr_bitfield_default }, + { "VGT_OUT_BUSY", 2, 2, &umr_bitfield_default }, + { "VGT_PT_BUSY", 3, 3, &umr_bitfield_default }, + { "VGT_TE_BUSY", 4, 4, &umr_bitfield_default }, + { "VGT_VR_BUSY", 5, 5, &umr_bitfield_default }, + { "VGT_PI_BUSY", 6, 6, &umr_bitfield_default }, + { "VGT_GS_BUSY", 7, 7, &umr_bitfield_default }, + { "VGT_HS_BUSY", 8, 8, &umr_bitfield_default }, + { "VGT_TE11_BUSY", 9, 9, &umr_bitfield_default }, + { "VGT_PRIMGEN_BUSY", 10, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWD_CNTL_STATUS[] = { + { "WD_BUSY", 0, 0, &umr_bitfield_default }, + { "WD_SPL_DMA_BUSY", 1, 1, &umr_bitfield_default }, + { "WD_SPL_DI_BUSY", 2, 2, &umr_bitfield_default }, + { "WD_ADC_BUSY", 3, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCC_GC_PRIM_CONFIG[] = { + { "INACTIVE_IA", 16, 17, &umr_bitfield_default }, + { "INACTIVE_VGT_PA", 24, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGC_USER_PRIM_CONFIG[] = { + { "INACTIVE_IA", 16, 17, &umr_bitfield_default }, + { "INACTIVE_VGT_PA", 24, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWD_QOS[] = { + { "DRAW_STALL", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWD_UTCL1_CNTL[] = { + { "XNACK_REDO_TIMER_CNT", 0, 19, &umr_bitfield_default }, + { "VMID_RESET_MODE", 23, 23, &umr_bitfield_default }, + { "DROP_MODE", 24, 24, &umr_bitfield_default }, + { "BYPASS", 25, 25, &umr_bitfield_default }, + { "INVALIDATE", 26, 26, &umr_bitfield_default }, + { "FRAG_LIMIT_MODE", 27, 27, &umr_bitfield_default }, + { "FORCE_SNOOP", 28, 28, &umr_bitfield_default }, + { "FORCE_SD_VMID_DIRTY", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWD_UTCL1_STATUS[] = { + { "FAULT_DETECTED", 0, 0, &umr_bitfield_default }, + { "RETRY_DETECTED", 1, 1, &umr_bitfield_default }, + { "PRT_DETECTED", 2, 2, &umr_bitfield_default }, + { "FAULT_UTCL1ID", 8, 13, &umr_bitfield_default }, + { "RETRY_UTCL1ID", 16, 21, &umr_bitfield_default }, + { "PRT_UTCL1ID", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIA_UTCL1_CNTL[] = { + { "XNACK_REDO_TIMER_CNT", 0, 19, &umr_bitfield_default }, + { "VMID_RESET_MODE", 23, 23, &umr_bitfield_default }, + { "DROP_MODE", 24, 24, &umr_bitfield_default }, + { "BYPASS", 25, 25, &umr_bitfield_default }, + { "INVALIDATE", 26, 26, &umr_bitfield_default }, + { "FRAG_LIMIT_MODE", 27, 27, &umr_bitfield_default }, + { "FORCE_SNOOP", 28, 28, &umr_bitfield_default }, + { "FORCE_SD_VMID_DIRTY", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIA_UTCL1_STATUS[] = { + { "FAULT_DETECTED", 0, 0, &umr_bitfield_default }, + { "RETRY_DETECTED", 1, 1, &umr_bitfield_default }, + { "PRT_DETECTED", 2, 2, &umr_bitfield_default }, + { "FAULT_UTCL1ID", 8, 13, &umr_bitfield_default }, + { "RETRY_UTCL1ID", 16, 21, &umr_bitfield_default }, + { "PRT_UTCL1ID", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_SYS_CONFIG[] = { + { "DUAL_CORE_EN", 0, 0, &umr_bitfield_default }, + { "MAX_LS_HS_THDGRP", 1, 6, &umr_bitfield_default }, + { "ADC_EVENT_FILTER_DISABLE", 7, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_VS_MAX_WAVE_ID[] = { + { "MAX_WAVE_ID", 0, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_GS_MAX_WAVE_ID[] = { + { "MAX_WAVE_ID", 0, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGFX_PIPE_CONTROL[] = { + { "HYSTERESIS_CNT", 0, 12, &umr_bitfield_default }, + { "RESERVED", 13, 15, &umr_bitfield_default }, + { "CONTEXT_SUSPEND_EN", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCC_GC_SHADER_ARRAY_CONFIG[] = { + { "INACTIVE_CUS", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGC_USER_SHADER_ARRAY_CONFIG[] = { + { "INACTIVE_CUS", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_DMA_PRIMITIVE_TYPE[] = { + { "PRIM_TYPE", 0, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_DMA_CONTROL[] = { + { "PRIMGROUP_SIZE", 0, 15, &umr_bitfield_default }, + { "IA_SWITCH_ON_EOP", 17, 17, &umr_bitfield_default }, + { "SWITCH_ON_EOI", 19, 19, &umr_bitfield_default }, + { "WD_SWITCH_ON_EOP", 20, 20, &umr_bitfield_default }, + { "EN_INST_OPT_BASIC", 21, 21, &umr_bitfield_default }, + { "EN_INST_OPT_ADV", 22, 22, &umr_bitfield_default }, + { "HW_USE_ONLY", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_DMA_LS_HS_CONFIG[] = { + { "HS_NUM_INPUT_CP", 8, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWD_BUF_RESOURCE_1[] = { + { "POS_BUF_SIZE", 0, 15, &umr_bitfield_default }, + { "INDEX_BUF_SIZE", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWD_BUF_RESOURCE_2[] = { + { "PARAM_BUF_SIZE", 0, 12, &umr_bitfield_default }, + { "ADDR_MODE", 15, 15, &umr_bitfield_default }, + { "CNTL_SB_BUF_SIZE", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_CNTL_STATUS[] = { + { "UTC_FAULT_DETECTED", 0, 0, &umr_bitfield_default }, + { "UTC_RETRY_DETECTED", 1, 1, &umr_bitfield_default }, + { "UTC_PRT_DETECTED", 2, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_ENHANCE[] = { + { "CLIP_VTX_REORDER_ENA", 0, 0, &umr_bitfield_default }, + { "NUM_CLIP_SEQ", 1, 2, &umr_bitfield_default }, + { "CLIPPED_PRIM_SEQ_STALL", 3, 3, &umr_bitfield_default }, + { "VE_NAN_PROC_DISABLE", 4, 4, &umr_bitfield_default }, + { "IGNORE_PIPELINE_RESET", 6, 6, &umr_bitfield_default }, + { "KILL_INNER_EDGE_FLAGS", 7, 7, &umr_bitfield_default }, + { "NGG_PA_TO_ALL_SC", 8, 8, &umr_bitfield_default }, + { "TC_LATENCY_TIME_STAMP_RESOLUTION", 9, 10, &umr_bitfield_default }, + { "NGG_BYPASS_PRIM_FILTER", 11, 11, &umr_bitfield_default }, + { "NGG_SIDEBAND_MEMORY_DEPTH", 12, 13, &umr_bitfield_default }, + { "NGG_PRIM_INDICES_FIFO_DEPTH", 14, 16, &umr_bitfield_default }, + { "ECO_SPARE3", 28, 28, &umr_bitfield_default }, + { "ECO_SPARE2", 29, 29, &umr_bitfield_default }, + { "ECO_SPARE1", 30, 30, &umr_bitfield_default }, + { "ECO_SPARE0", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SU_CNTL_STATUS[] = { + { "SU_BUSY", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_FIFO_DEPTH_CNTL[] = { + { "DEPTH", 0, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK[] = { + { "DISABLE_NON_PRIV_WRITES", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK[] = { + { "DISABLE_NON_PRIV_WRITES", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_TRAP_SCREEN_HV_LOCK[] = { + { "DISABLE_NON_PRIV_WRITES", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_FORCE_EOV_MAX_CNTS[] = { + { "FORCE_EOV_MAX_CLK_CNT", 0, 15, &umr_bitfield_default }, + { "FORCE_EOV_MAX_REZ_CNT", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_BINNER_EVENT_CNTL_0[] = { + { "RESERVED_0", 0, 1, &umr_bitfield_default }, + { "SAMPLE_STREAMOUTSTATS1", 2, 3, &umr_bitfield_default }, + { "SAMPLE_STREAMOUTSTATS2", 4, 5, &umr_bitfield_default }, + { "SAMPLE_STREAMOUTSTATS3", 6, 7, &umr_bitfield_default }, + { "CACHE_FLUSH_TS", 8, 9, &umr_bitfield_default }, + { "CONTEXT_DONE", 10, 11, &umr_bitfield_default }, + { "CACHE_FLUSH", 12, 13, &umr_bitfield_default }, + { "CS_PARTIAL_FLUSH", 14, 15, &umr_bitfield_default }, + { "VGT_STREAMOUT_SYNC", 16, 17, &umr_bitfield_default }, + { "RESERVED_9", 18, 19, &umr_bitfield_default }, + { "VGT_STREAMOUT_RESET", 20, 21, &umr_bitfield_default }, + { "END_OF_PIPE_INCR_DE", 22, 23, &umr_bitfield_default }, + { "END_OF_PIPE_IB_END", 24, 25, &umr_bitfield_default }, + { "RST_PIX_CNT", 26, 27, &umr_bitfield_default }, + { "BREAK_BATCH", 28, 29, &umr_bitfield_default }, + { "VS_PARTIAL_FLUSH", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_BINNER_EVENT_CNTL_1[] = { + { "PS_PARTIAL_FLUSH", 0, 1, &umr_bitfield_default }, + { "FLUSH_HS_OUTPUT", 2, 3, &umr_bitfield_default }, + { "FLUSH_DFSM", 4, 5, &umr_bitfield_default }, + { "RESET_TO_LOWEST_VGT", 6, 7, &umr_bitfield_default }, + { "CACHE_FLUSH_AND_INV_TS_EVENT", 8, 9, &umr_bitfield_default }, + { "ZPASS_DONE", 10, 11, &umr_bitfield_default }, + { "CACHE_FLUSH_AND_INV_EVENT", 12, 13, &umr_bitfield_default }, + { "PERFCOUNTER_START", 14, 15, &umr_bitfield_default }, + { "PERFCOUNTER_STOP", 16, 17, &umr_bitfield_default }, + { "PIPELINESTAT_START", 18, 19, &umr_bitfield_default }, + { "PIPELINESTAT_STOP", 20, 21, &umr_bitfield_default }, + { "PERFCOUNTER_SAMPLE", 22, 23, &umr_bitfield_default }, + { "FLUSH_ES_OUTPUT", 24, 25, &umr_bitfield_default }, + { "FLUSH_GS_OUTPUT", 26, 27, &umr_bitfield_default }, + { "SAMPLE_PIPELINESTAT", 28, 29, &umr_bitfield_default }, + { "SO_VGTSTREAMOUT_FLUSH", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_BINNER_EVENT_CNTL_2[] = { + { "SAMPLE_STREAMOUTSTATS", 0, 1, &umr_bitfield_default }, + { "RESET_VTX_CNT", 2, 3, &umr_bitfield_default }, + { "BLOCK_CONTEXT_DONE", 4, 5, &umr_bitfield_default }, + { "CS_CONTEXT_DONE", 6, 7, &umr_bitfield_default }, + { "VGT_FLUSH", 8, 9, &umr_bitfield_default }, + { "TGID_ROLLOVER", 10, 11, &umr_bitfield_default }, + { "SQ_NON_EVENT", 12, 13, &umr_bitfield_default }, + { "SC_SEND_DB_VPZ", 14, 15, &umr_bitfield_default }, + { "BOTTOM_OF_PIPE_TS", 16, 17, &umr_bitfield_default }, + { "FLUSH_SX_TS", 18, 19, &umr_bitfield_default }, + { "DB_CACHE_FLUSH_AND_INV", 20, 21, &umr_bitfield_default }, + { "FLUSH_AND_INV_DB_DATA_TS", 22, 23, &umr_bitfield_default }, + { "FLUSH_AND_INV_DB_META", 24, 25, &umr_bitfield_default }, + { "FLUSH_AND_INV_CB_DATA_TS", 26, 27, &umr_bitfield_default }, + { "FLUSH_AND_INV_CB_META", 28, 29, &umr_bitfield_default }, + { "CS_DONE", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_BINNER_EVENT_CNTL_3[] = { + { "PS_DONE", 0, 1, &umr_bitfield_default }, + { "FLUSH_AND_INV_CB_PIXEL_DATA", 2, 3, &umr_bitfield_default }, + { "SX_CB_RAT_ACK_REQUEST", 4, 5, &umr_bitfield_default }, + { "THREAD_TRACE_START", 6, 7, &umr_bitfield_default }, + { "THREAD_TRACE_STOP", 8, 9, &umr_bitfield_default }, + { "THREAD_TRACE_MARKER", 10, 11, &umr_bitfield_default }, + { "THREAD_TRACE_FLUSH", 12, 13, &umr_bitfield_default }, + { "THREAD_TRACE_FINISH", 14, 15, &umr_bitfield_default }, + { "PIXEL_PIPE_STAT_CONTROL", 16, 17, &umr_bitfield_default }, + { "PIXEL_PIPE_STAT_DUMP", 18, 19, &umr_bitfield_default }, + { "PIXEL_PIPE_STAT_RESET", 20, 21, &umr_bitfield_default }, + { "CONTEXT_SUSPEND", 22, 23, &umr_bitfield_default }, + { "OFFCHIP_HS_DEALLOC", 24, 25, &umr_bitfield_default }, + { "ENABLE_NGG_PIPELINE", 26, 27, &umr_bitfield_default }, + { "ENABLE_LEGACY_PIPELINE", 28, 29, &umr_bitfield_default }, + { "RESERVED_63", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_BINNER_TIMEOUT_COUNTER[] = { + { "THRESHOLD", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_BINNER_PERF_CNTL_0[] = { + { "BIN_HIST_NUM_PRIMS_THRESHOLD", 0, 9, &umr_bitfield_default }, + { "BATCH_HIST_NUM_PRIMS_THRESHOLD", 10, 19, &umr_bitfield_default }, + { "BIN_HIST_NUM_CONTEXT_THRESHOLD", 20, 22, &umr_bitfield_default }, + { "BATCH_HIST_NUM_CONTEXT_THRESHOLD", 23, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_BINNER_PERF_CNTL_1[] = { + { "BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD", 0, 4, &umr_bitfield_default }, + { "BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD", 5, 9, &umr_bitfield_default }, + { "BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD", 10, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_BINNER_PERF_CNTL_2[] = { + { "BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD", 0, 10, &umr_bitfield_default }, + { "BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD", 11, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_BINNER_PERF_CNTL_3[] = { + { "BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_FIFO_SIZE[] = { + { "SC_FRONTEND_PRIM_FIFO_SIZE", 0, 5, &umr_bitfield_default }, + { "SC_BACKEND_PRIM_FIFO_SIZE", 6, 14, &umr_bitfield_default }, + { "SC_HIZ_TILE_FIFO_SIZE", 15, 20, &umr_bitfield_default }, + { "SC_EARLYZ_TILE_FIFO_SIZE", 21, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_IF_FIFO_SIZE[] = { + { "SC_DB_TILE_IF_FIFO_SIZE", 0, 5, &umr_bitfield_default }, + { "SC_DB_QUAD_IF_FIFO_SIZE", 6, 11, &umr_bitfield_default }, + { "SC_SPI_IF_FIFO_SIZE", 12, 17, &umr_bitfield_default }, + { "SC_BCI_IF_FIFO_SIZE", 18, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_PKR_WAVE_TABLE_CNTL[] = { + { "SIZE", 0, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_UTCL1_CNTL1[] = { + { "FORCE_4K_L2_RESP", 0, 0, &umr_bitfield_default }, + { "GPUVM_64K_DEFAULT", 1, 1, &umr_bitfield_default }, + { "GPUVM_PERM_MODE", 2, 2, &umr_bitfield_default }, + { "RESP_MODE", 3, 4, &umr_bitfield_default }, + { "RESP_FAULT_MODE", 5, 6, &umr_bitfield_default }, + { "CLIENTID", 7, 15, &umr_bitfield_default }, + { "SPARE", 16, 16, &umr_bitfield_default }, + { "ENABLE_PUSH_LFIFO", 17, 17, &umr_bitfield_default }, + { "ENABLE_LFIFO_PRI_ARB", 18, 18, &umr_bitfield_default }, + { "REG_INV_VMID", 19, 22, &umr_bitfield_default }, + { "REG_INV_ALL_VMID", 23, 23, &umr_bitfield_default }, + { "REG_INV_TOGGLE", 24, 24, &umr_bitfield_default }, + { "INVALIDATE_ALL_VMID", 25, 25, &umr_bitfield_default }, + { "FORCE_MISS", 26, 26, &umr_bitfield_default }, + { "FORCE_IN_ORDER", 27, 27, &umr_bitfield_default }, + { "REDUCE_FIFO_DEPTH_BY_2", 28, 29, &umr_bitfield_default }, + { "REDUCE_CACHE_SIZE_BY_2", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_UTCL1_CNTL2[] = { + { "SPARE1", 0, 7, &umr_bitfield_default }, + { "SPARE2", 8, 8, &umr_bitfield_default }, + { "MTYPE_OVRD_DIS", 9, 9, &umr_bitfield_default }, + { "LINE_VALID", 10, 10, &umr_bitfield_default }, + { "SPARE3", 11, 11, &umr_bitfield_default }, + { "GPUVM_INV_MODE", 12, 12, &umr_bitfield_default }, + { "ENABLE_SHOOTDOWN_OPT", 13, 13, &umr_bitfield_default }, + { "FORCE_SNOOP", 14, 14, &umr_bitfield_default }, + { "FORCE_GPUVM_INV_ACK", 15, 15, &umr_bitfield_default }, + { "SPARE4", 16, 17, &umr_bitfield_default }, + { "ENABLE_PERF_EVENT_RD_WR", 18, 18, &umr_bitfield_default }, + { "PERF_EVENT_RD_WR", 19, 19, &umr_bitfield_default }, + { "ENABLE_PERF_EVENT_VMID", 20, 20, &umr_bitfield_default }, + { "PERF_EVENT_VMID", 21, 24, &umr_bitfield_default }, + { "SPARE5", 25, 25, &umr_bitfield_default }, + { "FORCE_FRAG_2M_TO_64K", 26, 26, &umr_bitfield_default }, + { "RESERVED", 27, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SIDEBAND_REQUEST_DELAYS[] = { + { "RETRY_DELAY", 0, 15, &umr_bitfield_default }, + { "INITIAL_DELAY", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_ENHANCE[] = { + { "ENABLE_PA_SC_OUT_OF_ORDER", 0, 0, &umr_bitfield_default }, + { "DISABLE_SC_DB_TILE_FIX", 1, 1, &umr_bitfield_default }, + { "DISABLE_AA_MASK_FULL_FIX", 2, 2, &umr_bitfield_default }, + { "ENABLE_1XMSAA_SAMPLE_LOCATIONS", 3, 3, &umr_bitfield_default }, + { "ENABLE_1XMSAA_SAMPLE_LOC_CENTROID", 4, 4, &umr_bitfield_default }, + { "DISABLE_SCISSOR_FIX", 5, 5, &umr_bitfield_default }, + { "SEND_UNLIT_STILES_TO_PACKER", 6, 6, &umr_bitfield_default }, + { "DISABLE_DUALGRAD_PERF_OPTIMIZATION", 7, 7, &umr_bitfield_default }, + { "DISABLE_SC_PROCESS_RESET_PRIM", 8, 8, &umr_bitfield_default }, + { "DISABLE_SC_PROCESS_RESET_SUPERTILE", 9, 9, &umr_bitfield_default }, + { "DISABLE_SC_PROCESS_RESET_TILE", 10, 10, &umr_bitfield_default }, + { "DISABLE_PA_SC_GUIDANCE", 11, 11, &umr_bitfield_default }, + { "DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS", 12, 12, &umr_bitfield_default }, + { "ENABLE_MULTICYCLE_BUBBLE_FREEZE", 13, 13, &umr_bitfield_default }, + { "DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE", 14, 14, &umr_bitfield_default }, + { "ENABLE_OUT_OF_ORDER_POLY_MODE", 15, 15, &umr_bitfield_default }, + { "DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST", 16, 16, &umr_bitfield_default }, + { "DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING", 17, 17, &umr_bitfield_default }, + { "ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY", 18, 18, &umr_bitfield_default }, + { "DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING", 19, 19, &umr_bitfield_default }, + { "DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING", 20, 20, &umr_bitfield_default }, + { "DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS", 21, 21, &umr_bitfield_default }, + { "ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID", 22, 22, &umr_bitfield_default }, + { "DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO", 23, 23, &umr_bitfield_default }, + { "OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT", 24, 24, &umr_bitfield_default }, + { "OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING", 25, 25, &umr_bitfield_default }, + { "DISABLE_EOP_LINE_STIPPLE_RESET", 26, 26, &umr_bitfield_default }, + { "DISABLE_VPZ_EOP_LINE_STIPPLE_RESET", 27, 27, &umr_bitfield_default }, + { "IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE", 28, 28, &umr_bitfield_default }, + { "OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_ENHANCE_1[] = { + { "REALIGN_DQUADS_OVERRIDE_ENABLE", 0, 0, &umr_bitfield_default }, + { "REALIGN_DQUADS_OVERRIDE", 1, 2, &umr_bitfield_default }, + { "DISABLE_SC_BINNING", 3, 3, &umr_bitfield_default }, + { "BYPASS_PBB", 4, 4, &umr_bitfield_default }, + { "ECO_SPARE0", 5, 5, &umr_bitfield_default }, + { "ECO_SPARE1", 6, 6, &umr_bitfield_default }, + { "ECO_SPARE2", 7, 7, &umr_bitfield_default }, + { "ECO_SPARE3", 8, 8, &umr_bitfield_default }, + { "DISABLE_SC_PROCESS_RESET_PBB", 9, 9, &umr_bitfield_default }, + { "DISABLE_PBB_SCISSOR_OPT", 10, 10, &umr_bitfield_default }, + { "ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM", 11, 11, &umr_bitfield_default }, + { "DISABLE_PACKER_GRAD_FDCE_ENHANCE", 13, 13, &umr_bitfield_default }, + { "DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE", 14, 14, &umr_bitfield_default }, + { "DISABLE_SC_PIPELINE_RESET_LEGACY_MODE_TRANSITION", 15, 15, &umr_bitfield_default }, + { "DISABLE_PACKER_ODC_ENHANCE", 16, 16, &umr_bitfield_default }, + { "ALLOW_SCALE_LINE_WIDTH_PAD_WITH_BINNING", 17, 17, &umr_bitfield_default }, + { "OPTIMAL_BIN_SELECTION", 18, 18, &umr_bitfield_default }, + { "DISABLE_FORCE_SOP_ALL_EVENTS", 19, 19, &umr_bitfield_default }, + { "DISABLE_PBB_CLK_OPTIMIZATION", 20, 20, &umr_bitfield_default }, + { "DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION", 21, 21, &umr_bitfield_default }, + { "DISABLE_PBB_BINNING_CLK_OPTIMIZATION", 22, 22, &umr_bitfield_default }, + { "RSVD", 23, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_DSM_CNTL[] = { + { "FORCE_EOV_REZ_0", 0, 0, &umr_bitfield_default }, + { "FORCE_EOV_REZ_1", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_TILE_STEERING_CREST_OVERRIDE[] = { + { "ONE_RB_MODE_ENABLE", 0, 0, &umr_bitfield_default }, + { "SE_SELECT", 1, 2, &umr_bitfield_default }, + { "RB_SELECT", 5, 6, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_CONFIG[] = { + { "UNUSED", 0, 6, &umr_bitfield_default }, + { "OVERRIDE_ALU_BUSY", 7, 7, &umr_bitfield_default }, + { "OVERRIDE_LDS_IDX_BUSY", 11, 11, &umr_bitfield_default }, + { "EARLY_TA_DONE_DISABLE", 12, 12, &umr_bitfield_default }, + { "DUA_FLAT_LOCK_ENABLE", 13, 13, &umr_bitfield_default }, + { "DUA_LDS_BYPASS_DISABLE", 14, 14, &umr_bitfield_default }, + { "DUA_FLAT_LDS_PINGPONG_DISABLE", 15, 15, &umr_bitfield_default }, + { "DISABLE_VMEM_SOFT_CLAUSE", 16, 16, &umr_bitfield_default }, + { "DISABLE_SMEM_SOFT_CLAUSE", 17, 17, &umr_bitfield_default }, + { "ENABLE_HIPRIO_ON_EXP_RDY_VS", 18, 18, &umr_bitfield_default }, + { "PRIO_VAL_ON_EXP_RDY_VS", 19, 20, &umr_bitfield_default }, + { "REPLAY_SLEEP_CNT", 21, 27, &umr_bitfield_default }, + { "DISABLE_SP_VGPR_WRITE_SKIP", 28, 28, &umr_bitfield_default }, + { "DISABLE_SP_REDUNDANT_THREAD_GATING", 29, 29, &umr_bitfield_default }, + { "DISABLE_FLAT_SOFT_CLAUSE", 30, 30, &umr_bitfield_default }, + { "DISABLE_MIMG_SOFT_CLAUSE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQC_CONFIG[] = { + { "INST_CACHE_SIZE", 0, 1, &umr_bitfield_default }, + { "DATA_CACHE_SIZE", 2, 3, &umr_bitfield_default }, + { "MISS_FIFO_DEPTH", 4, 5, &umr_bitfield_default }, + { "HIT_FIFO_DEPTH", 6, 6, &umr_bitfield_default }, + { "FORCE_ALWAYS_MISS", 7, 7, &umr_bitfield_default }, + { "FORCE_IN_ORDER", 8, 8, &umr_bitfield_default }, + { "IDENTITY_HASH_BANK", 9, 9, &umr_bitfield_default }, + { "IDENTITY_HASH_SET", 10, 10, &umr_bitfield_default }, + { "PER_VMID_INV_DISABLE", 11, 11, &umr_bitfield_default }, + { "EVICT_LRU", 12, 13, &umr_bitfield_default }, + { "FORCE_2_BANK", 14, 14, &umr_bitfield_default }, + { "FORCE_1_BANK", 15, 15, &umr_bitfield_default }, + { "LS_DISABLE_CLOCKS", 16, 23, &umr_bitfield_default }, + { "INST_PRF_COUNT", 24, 25, &umr_bitfield_default }, + { "INST_PRF_FILTER_DIS", 26, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmLDS_CONFIG[] = { + { "ADDR_OUT_OF_RANGE_REPORTING", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_RANDOM_WAVE_PRI[] = { + { "RET", 0, 6, &umr_bitfield_default }, + { "RUI", 7, 9, &umr_bitfield_default }, + { "RNG", 10, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_REG_CREDITS[] = { + { "SRBM_CREDITS", 0, 5, &umr_bitfield_default }, + { "CMD_CREDITS", 8, 11, &umr_bitfield_default }, + { "REG_BUSY", 28, 28, &umr_bitfield_default }, + { "SRBM_OVERFLOW", 29, 29, &umr_bitfield_default }, + { "IMMED_OVERFLOW", 30, 30, &umr_bitfield_default }, + { "CMD_OVERFLOW", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_FIFO_SIZES[] = { + { "INTERRUPT_FIFO_SIZE", 0, 3, &umr_bitfield_default }, + { "TTRACE_FIFO_SIZE", 8, 11, &umr_bitfield_default }, + { "EXPORT_BUF_SIZE", 16, 17, &umr_bitfield_default }, + { "VMEM_DATA_FIFO_SIZE", 18, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_DSM_CNTL[] = { + { "WAVEFRONT_STALL_0", 0, 0, &umr_bitfield_default }, + { "WAVEFRONT_STALL_1", 1, 1, &umr_bitfield_default }, + { "SPI_BACKPRESSURE_0", 2, 2, &umr_bitfield_default }, + { "SPI_BACKPRESSURE_1", 3, 3, &umr_bitfield_default }, + { "SEL_DSM_SGPR_IRRITATOR_DATA0", 8, 8, &umr_bitfield_default }, + { "SEL_DSM_SGPR_IRRITATOR_DATA1", 9, 9, &umr_bitfield_default }, + { "SGPR_ENABLE_SINGLE_WRITE", 10, 10, &umr_bitfield_default }, + { "SEL_DSM_LDS_IRRITATOR_DATA0", 16, 16, &umr_bitfield_default }, + { "SEL_DSM_LDS_IRRITATOR_DATA1", 17, 17, &umr_bitfield_default }, + { "LDS_ENABLE_SINGLE_WRITE01", 18, 18, &umr_bitfield_default }, + { "SEL_DSM_LDS_IRRITATOR_DATA2", 19, 19, &umr_bitfield_default }, + { "SEL_DSM_LDS_IRRITATOR_DATA3", 20, 20, &umr_bitfield_default }, + { "LDS_ENABLE_SINGLE_WRITE23", 21, 21, &umr_bitfield_default }, + { "SEL_DSM_SP_IRRITATOR_DATA0", 24, 24, &umr_bitfield_default }, + { "SEL_DSM_SP_IRRITATOR_DATA1", 25, 25, &umr_bitfield_default }, + { "SP_ENABLE_SINGLE_WRITE", 26, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_DSM_CNTL2[] = { + { "SGPR_ENABLE_ERROR_INJECT", 0, 1, &umr_bitfield_default }, + { "SGPR_SELECT_INJECT_DELAY", 2, 2, &umr_bitfield_default }, + { "LDS_D_ENABLE_ERROR_INJECT", 3, 4, &umr_bitfield_default }, + { "LDS_D_SELECT_INJECT_DELAY", 5, 5, &umr_bitfield_default }, + { "LDS_I_ENABLE_ERROR_INJECT", 6, 7, &umr_bitfield_default }, + { "LDS_I_SELECT_INJECT_DELAY", 8, 8, &umr_bitfield_default }, + { "SP_ENABLE_ERROR_INJECT", 9, 10, &umr_bitfield_default }, + { "SP_SELECT_INJECT_DELAY", 11, 11, &umr_bitfield_default }, + { "LDS_INJECT_DELAY", 14, 19, &umr_bitfield_default }, + { "SP_INJECT_DELAY", 20, 25, &umr_bitfield_default }, + { "SQ_INJECT_DELAY", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_RUNTIME_CONFIG[] = { + { "ENABLE_TEX_ARB_OLDEST", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSH_MEM_BASES[] = { + { "PRIVATE_BASE", 0, 15, &umr_bitfield_default }, + { "SHARED_BASE", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSH_MEM_CONFIG[] = { + { "ADDRESS_MODE", 0, 0, &umr_bitfield_default }, + { "ALIGNMENT_MODE", 3, 4, &umr_bitfield_default }, + { "RETRY_DISABLE", 12, 12, &umr_bitfield_default }, + { "PRIVATE_NV", 13, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCC_GC_SHADER_RATE_CONFIG[] = { + { "DPFP_RATE", 1, 2, &umr_bitfield_default }, + { "SQC_BALANCE_DISABLE", 3, 3, &umr_bitfield_default }, + { "HALF_LDS", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGC_USER_SHADER_RATE_CONFIG[] = { + { "DPFP_RATE", 1, 2, &umr_bitfield_default }, + { "SQC_BALANCE_DISABLE", 3, 3, &umr_bitfield_default }, + { "HALF_LDS", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_INTERRUPT_AUTO_MASK[] = { + { "MASK", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_INTERRUPT_MSG_CTRL[] = { + { "STALL", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_UTCL1_CNTL1[] = { + { "FORCE_4K_L2_RESP", 0, 0, &umr_bitfield_default }, + { "GPUVM_64K_DEF", 1, 1, &umr_bitfield_default }, + { "GPUVM_PERM_MODE", 2, 2, &umr_bitfield_default }, + { "RESP_MODE", 3, 4, &umr_bitfield_default }, + { "RESP_FAULT_MODE", 5, 6, &umr_bitfield_default }, + { "CLIENTID", 7, 15, &umr_bitfield_default }, + { "USERVM_DIS", 16, 16, &umr_bitfield_default }, + { "ENABLE_PUSH_LFIFO", 17, 17, &umr_bitfield_default }, + { "ENABLE_LFIFO_PRI_ARB", 18, 18, &umr_bitfield_default }, + { "REG_INVALIDATE_VMID", 19, 22, &umr_bitfield_default }, + { "REG_INVALIDATE_ALL_VMID", 23, 23, &umr_bitfield_default }, + { "REG_INVALIDATE_TOGGLE", 24, 24, &umr_bitfield_default }, + { "REG_INVALIDATE_ALL", 25, 25, &umr_bitfield_default }, + { "FORCE_MISS", 26, 26, &umr_bitfield_default }, + { "FORCE_IN_ORDER", 27, 27, &umr_bitfield_default }, + { "REDUCE_FIFO_DEPTH_BY_2", 28, 29, &umr_bitfield_default }, + { "REDUCE_CACHE_SIZE_BY_2", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_UTCL1_CNTL2[] = { + { "SPARE", 0, 7, &umr_bitfield_default }, + { "LFIFO_SCAN_DISABLE", 8, 8, &umr_bitfield_default }, + { "MTYPE_OVRD_DIS", 9, 9, &umr_bitfield_default }, + { "LINE_VALID", 10, 10, &umr_bitfield_default }, + { "DIS_EDC", 11, 11, &umr_bitfield_default }, + { "GPUVM_INV_MODE", 12, 12, &umr_bitfield_default }, + { "SHOOTDOWN_OPT", 13, 13, &umr_bitfield_default }, + { "FORCE_SNOOP", 14, 14, &umr_bitfield_default }, + { "FORCE_GPUVM_INV_ACK", 15, 15, &umr_bitfield_default }, + { "RETRY_TIMER", 16, 22, &umr_bitfield_default }, + { "FORCE_FRAG_2M_TO_64K", 26, 26, &umr_bitfield_default }, + { "PREFETCH_PAGE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_UTCL1_STATUS[] = { + { "FAULT_DETECTED", 0, 0, &umr_bitfield_default }, + { "RETRY_DETECTED", 1, 1, &umr_bitfield_default }, + { "PRT_DETECTED", 2, 2, &umr_bitfield_default }, + { "RESERVED", 3, 15, &umr_bitfield_default }, + { "UNUSED", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_SHADER_TBA_LO[] = { + { "ADDR_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_SHADER_TBA_HI[] = { + { "ADDR_HI", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_SHADER_TMA_LO[] = { + { "ADDR_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_SHADER_TMA_HI[] = { + { "ADDR_HI", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQC_DSM_CNTL[] = { + { "INST_UTCL1_LFIFO_DSM_IRRITATOR_DATA", 0, 1, &umr_bitfield_default }, + { "INST_UTCL1_LFIFO_ENABLE_SINGLE_WRITE", 2, 2, &umr_bitfield_default }, + { "DATA_CU0_WRITE_DATA_BUF_DSM_IRRITATOR_DATA", 3, 4, &umr_bitfield_default }, + { "DATA_CU0_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE", 5, 5, &umr_bitfield_default }, + { "DATA_CU0_UTCL1_LFIFO_DSM_IRRITATOR_DATA", 6, 7, &umr_bitfield_default }, + { "DATA_CU0_UTCL1_LFIFO_ENABLE_SINGLE_WRITE", 8, 8, &umr_bitfield_default }, + { "DATA_CU1_WRITE_DATA_BUF_DSM_IRRITATOR_DATA", 9, 10, &umr_bitfield_default }, + { "DATA_CU1_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE", 11, 11, &umr_bitfield_default }, + { "DATA_CU1_UTCL1_LFIFO_DSM_IRRITATOR_DATA", 12, 13, &umr_bitfield_default }, + { "DATA_CU1_UTCL1_LFIFO_ENABLE_SINGLE_WRITE", 14, 14, &umr_bitfield_default }, + { "DATA_CU2_WRITE_DATA_BUF_DSM_IRRITATOR_DATA", 15, 16, &umr_bitfield_default }, + { "DATA_CU2_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE", 17, 17, &umr_bitfield_default }, + { "DATA_CU2_UTCL1_LFIFO_DSM_IRRITATOR_DATA", 18, 19, &umr_bitfield_default }, + { "DATA_CU2_UTCL1_LFIFO_ENABLE_SINGLE_WRITE", 20, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQC_DSM_CNTLA[] = { + { "INST_TAG_RAM_DSM_IRRITATOR_DATA", 0, 1, &umr_bitfield_default }, + { "INST_TAG_RAM_ENABLE_SINGLE_WRITE", 2, 2, &umr_bitfield_default }, + { "INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA", 3, 4, &umr_bitfield_default }, + { "INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE", 5, 5, &umr_bitfield_default }, + { "INST_MISS_FIFO_DSM_IRRITATOR_DATA", 6, 7, &umr_bitfield_default }, + { "INST_MISS_FIFO_ENABLE_SINGLE_WRITE", 8, 8, &umr_bitfield_default }, + { "INST_BANK_RAM_DSM_IRRITATOR_DATA", 9, 10, &umr_bitfield_default }, + { "INST_BANK_RAM_ENABLE_SINGLE_WRITE", 11, 11, &umr_bitfield_default }, + { "DATA_TAG_RAM_DSM_IRRITATOR_DATA", 12, 13, &umr_bitfield_default }, + { "DATA_TAG_RAM_ENABLE_SINGLE_WRITE", 14, 14, &umr_bitfield_default }, + { "DATA_HIT_FIFO_DSM_IRRITATOR_DATA", 15, 16, &umr_bitfield_default }, + { "DATA_HIT_FIFO_ENABLE_SINGLE_WRITE", 17, 17, &umr_bitfield_default }, + { "DATA_MISS_FIFO_DSM_IRRITATOR_DATA", 18, 19, &umr_bitfield_default }, + { "DATA_MISS_FIFO_ENABLE_SINGLE_WRITE", 20, 20, &umr_bitfield_default }, + { "DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA", 21, 22, &umr_bitfield_default }, + { "DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE", 23, 23, &umr_bitfield_default }, + { "DATA_BANK_RAM_DSM_IRRITATOR_DATA", 24, 25, &umr_bitfield_default }, + { "DATA_BANK_RAM_ENABLE_SINGLE_WRITE", 26, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQC_DSM_CNTLB[] = { + { "INST_TAG_RAM_DSM_IRRITATOR_DATA", 0, 1, &umr_bitfield_default }, + { "INST_TAG_RAM_ENABLE_SINGLE_WRITE", 2, 2, &umr_bitfield_default }, + { "INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA", 3, 4, &umr_bitfield_default }, + { "INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE", 5, 5, &umr_bitfield_default }, + { "INST_MISS_FIFO_DSM_IRRITATOR_DATA", 6, 7, &umr_bitfield_default }, + { "INST_MISS_FIFO_ENABLE_SINGLE_WRITE", 8, 8, &umr_bitfield_default }, + { "INST_BANK_RAM_DSM_IRRITATOR_DATA", 9, 10, &umr_bitfield_default }, + { "INST_BANK_RAM_ENABLE_SINGLE_WRITE", 11, 11, &umr_bitfield_default }, + { "DATA_TAG_RAM_DSM_IRRITATOR_DATA", 12, 13, &umr_bitfield_default }, + { "DATA_TAG_RAM_ENABLE_SINGLE_WRITE", 14, 14, &umr_bitfield_default }, + { "DATA_HIT_FIFO_DSM_IRRITATOR_DATA", 15, 16, &umr_bitfield_default }, + { "DATA_HIT_FIFO_ENABLE_SINGLE_WRITE", 17, 17, &umr_bitfield_default }, + { "DATA_MISS_FIFO_DSM_IRRITATOR_DATA", 18, 19, &umr_bitfield_default }, + { "DATA_MISS_FIFO_ENABLE_SINGLE_WRITE", 20, 20, &umr_bitfield_default }, + { "DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA", 21, 22, &umr_bitfield_default }, + { "DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE", 23, 23, &umr_bitfield_default }, + { "DATA_BANK_RAM_DSM_IRRITATOR_DATA", 24, 25, &umr_bitfield_default }, + { "DATA_BANK_RAM_ENABLE_SINGLE_WRITE", 26, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQC_DSM_CNTL2[] = { + { "INST_UTCL1_LFIFO_ENABLE_ERROR_INJECT", 0, 1, &umr_bitfield_default }, + { "INST_UTCL1_LFIFO_SELECT_INJECT_DELAY", 2, 2, &umr_bitfield_default }, + { "DATA_CU0_WRITE_DATA_BUF_ENABLE_ERROR_INJECT", 3, 4, &umr_bitfield_default }, + { "DATA_CU0_WRITE_DATA_BUF_SELECT_INJECT_DELAY", 5, 5, &umr_bitfield_default }, + { "DATA_CU0_UTCL1_LFIFO_ENABLE_ERROR_INJECT", 6, 7, &umr_bitfield_default }, + { "DATA_CU0_UTCL1_LFIFO_SELECT_INJECT_DELAY", 8, 8, &umr_bitfield_default }, + { "DATA_CU1_WRITE_DATA_BUF_ENABLE_ERROR_INJECT", 9, 10, &umr_bitfield_default }, + { "DATA_CU1_WRITE_DATA_BUF_SELECT_INJECT_DELAY", 11, 11, &umr_bitfield_default }, + { "DATA_CU1_UTCL1_LFIFO_ENABLE_ERROR_INJECT", 12, 13, &umr_bitfield_default }, + { "DATA_CU1_UTCL1_LFIFO_SELECT_INJECT_DELAY", 14, 14, &umr_bitfield_default }, + { "DATA_CU2_WRITE_DATA_BUF_ENABLE_ERROR_INJECT", 15, 16, &umr_bitfield_default }, + { "DATA_CU2_WRITE_DATA_BUF_SELECT_INJECT_DELAY", 17, 17, &umr_bitfield_default }, + { "DATA_CU2_UTCL1_LFIFO_ENABLE_ERROR_INJECT", 18, 19, &umr_bitfield_default }, + { "DATA_CU2_UTCL1_LFIFO_SELECT_INJECT_DELAY", 20, 20, &umr_bitfield_default }, + { "INJECT_DELAY", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQC_DSM_CNTL2A[] = { + { "INST_TAG_RAM_ENABLE_ERROR_INJECT", 0, 1, &umr_bitfield_default }, + { "INST_TAG_RAM_SELECT_INJECT_DELAY", 2, 2, &umr_bitfield_default }, + { "INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT", 3, 4, &umr_bitfield_default }, + { "INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY", 5, 5, &umr_bitfield_default }, + { "INST_MISS_FIFO_ENABLE_ERROR_INJECT", 6, 7, &umr_bitfield_default }, + { "INST_MISS_FIFO_SELECT_INJECT_DELAY", 8, 8, &umr_bitfield_default }, + { "INST_BANK_RAM_ENABLE_ERROR_INJECT", 9, 10, &umr_bitfield_default }, + { "INST_BANK_RAM_SELECT_INJECT_DELAY", 11, 11, &umr_bitfield_default }, + { "DATA_TAG_RAM_ENABLE_ERROR_INJECT", 12, 13, &umr_bitfield_default }, + { "DATA_TAG_RAM_SELECT_INJECT_DELAY", 14, 14, &umr_bitfield_default }, + { "DATA_HIT_FIFO_ENABLE_ERROR_INJECT", 15, 16, &umr_bitfield_default }, + { "DATA_HIT_FIFO_SELECT_INJECT_DELAY", 17, 17, &umr_bitfield_default }, + { "DATA_MISS_FIFO_ENABLE_ERROR_INJECT", 18, 19, &umr_bitfield_default }, + { "DATA_MISS_FIFO_SELECT_INJECT_DELAY", 20, 20, &umr_bitfield_default }, + { "DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT", 21, 22, &umr_bitfield_default }, + { "DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY", 23, 23, &umr_bitfield_default }, + { "DATA_BANK_RAM_ENABLE_ERROR_INJECT", 24, 25, &umr_bitfield_default }, + { "DATA_BANK_RAM_SELECT_INJECT_DELAY", 26, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQC_DSM_CNTL2B[] = { + { "INST_TAG_RAM_ENABLE_ERROR_INJECT", 0, 1, &umr_bitfield_default }, + { "INST_TAG_RAM_SELECT_INJECT_DELAY", 2, 2, &umr_bitfield_default }, + { "INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT", 3, 4, &umr_bitfield_default }, + { "INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY", 5, 5, &umr_bitfield_default }, + { "INST_MISS_FIFO_ENABLE_ERROR_INJECT", 6, 7, &umr_bitfield_default }, + { "INST_MISS_FIFO_SELECT_INJECT_DELAY", 8, 8, &umr_bitfield_default }, + { "INST_BANK_RAM_ENABLE_ERROR_INJECT", 9, 10, &umr_bitfield_default }, + { "INST_BANK_RAM_SELECT_INJECT_DELAY", 11, 11, &umr_bitfield_default }, + { "DATA_TAG_RAM_ENABLE_ERROR_INJECT", 12, 13, &umr_bitfield_default }, + { "DATA_TAG_RAM_SELECT_INJECT_DELAY", 14, 14, &umr_bitfield_default }, + { "DATA_HIT_FIFO_ENABLE_ERROR_INJECT", 15, 16, &umr_bitfield_default }, + { "DATA_HIT_FIFO_SELECT_INJECT_DELAY", 17, 17, &umr_bitfield_default }, + { "DATA_MISS_FIFO_ENABLE_ERROR_INJECT", 18, 19, &umr_bitfield_default }, + { "DATA_MISS_FIFO_SELECT_INJECT_DELAY", 20, 20, &umr_bitfield_default }, + { "DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT", 21, 22, &umr_bitfield_default }, + { "DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY", 23, 23, &umr_bitfield_default }, + { "DATA_BANK_RAM_ENABLE_ERROR_INJECT", 24, 25, &umr_bitfield_default }, + { "DATA_BANK_RAM_SELECT_INJECT_DELAY", 26, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQC_EDC_FUE_CNTL[] = { + { "BLOCK_FUE_FLAGS", 0, 15, &umr_bitfield_default }, + { "FUE_INTERRUPT_ENABLES", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQC_EDC_CNT2[] = { + { "INST_BANKA_TAG_RAM_SEC_COUNT", 0, 1, &umr_bitfield_default }, + { "INST_BANKA_TAG_RAM_DED_COUNT", 2, 3, &umr_bitfield_default }, + { "INST_BANKA_BANK_RAM_SEC_COUNT", 4, 5, &umr_bitfield_default }, + { "INST_BANKA_BANK_RAM_DED_COUNT", 6, 7, &umr_bitfield_default }, + { "DATA_BANKA_TAG_RAM_SEC_COUNT", 8, 9, &umr_bitfield_default }, + { "DATA_BANKA_TAG_RAM_DED_COUNT", 10, 11, &umr_bitfield_default }, + { "DATA_BANKA_BANK_RAM_SEC_COUNT", 12, 13, &umr_bitfield_default }, + { "DATA_BANKA_BANK_RAM_DED_COUNT", 14, 15, &umr_bitfield_default }, + { "INST_BANKA_UTCL1_MISS_FIFO_SED_COUNT", 16, 17, &umr_bitfield_default }, + { "INST_BANKA_MISS_FIFO_SED_COUNT", 18, 19, &umr_bitfield_default }, + { "DATA_BANKA_HIT_FIFO_SED_COUNT", 20, 21, &umr_bitfield_default }, + { "DATA_BANKA_MISS_FIFO_SED_COUNT", 22, 23, &umr_bitfield_default }, + { "DATA_BANKA_DIRTY_BIT_RAM_SED_COUNT", 24, 25, &umr_bitfield_default }, + { "INST_UTCL1_LFIFO_SEC_COUNT", 26, 27, &umr_bitfield_default }, + { "INST_UTCL1_LFIFO_DED_COUNT", 28, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQC_EDC_CNT3[] = { + { "INST_BANKB_TAG_RAM_SEC_COUNT", 0, 1, &umr_bitfield_default }, + { "INST_BANKB_TAG_RAM_DED_COUNT", 2, 3, &umr_bitfield_default }, + { "INST_BANKB_BANK_RAM_SEC_COUNT", 4, 5, &umr_bitfield_default }, + { "INST_BANKB_BANK_RAM_DED_COUNT", 6, 7, &umr_bitfield_default }, + { "DATA_BANKB_TAG_RAM_SEC_COUNT", 8, 9, &umr_bitfield_default }, + { "DATA_BANKB_TAG_RAM_DED_COUNT", 10, 11, &umr_bitfield_default }, + { "DATA_BANKB_BANK_RAM_SEC_COUNT", 12, 13, &umr_bitfield_default }, + { "DATA_BANKB_BANK_RAM_DED_COUNT", 14, 15, &umr_bitfield_default }, + { "INST_BANKB_UTCL1_MISS_FIFO_SED_COUNT", 16, 17, &umr_bitfield_default }, + { "INST_BANKB_MISS_FIFO_SED_COUNT", 18, 19, &umr_bitfield_default }, + { "DATA_BANKB_HIT_FIFO_SED_COUNT", 20, 21, &umr_bitfield_default }, + { "DATA_BANKB_MISS_FIFO_SED_COUNT", 22, 23, &umr_bitfield_default }, + { "DATA_BANKB_DIRTY_BIT_RAM_SED_COUNT", 24, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_REG_TIMESTAMP[] = { + { "TIMESTAMP", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_CMD_TIMESTAMP[] = { + { "TIMESTAMP", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_IND_INDEX[] = { + { "WAVE_ID", 0, 3, &umr_bitfield_default }, + { "SIMD_ID", 4, 5, &umr_bitfield_default }, + { "THREAD_ID", 6, 11, &umr_bitfield_default }, + { "AUTO_INCR", 12, 12, &umr_bitfield_default }, + { "FORCE_READ", 13, 13, &umr_bitfield_default }, + { "READ_TIMEOUT", 14, 14, &umr_bitfield_default }, + { "UNINDEXED", 15, 15, &umr_bitfield_default }, + { "INDEX", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_IND_DATA[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_CMD[] = { + { "CMD", 0, 2, &umr_bitfield_default }, + { "MODE", 4, 6, &umr_bitfield_default }, + { "CHECK_VMID", 7, 7, &umr_bitfield_default }, + { "DATA", 8, 11, &umr_bitfield_default }, + { "WAVE_ID", 16, 19, &umr_bitfield_default }, + { "SIMD_ID", 20, 21, &umr_bitfield_default }, + { "QUEUE_ID", 24, 26, &umr_bitfield_default }, + { "VM_ID", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_TIME_HI[] = { + { "TIME", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_TIME_LO[] = { + { "TIME", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_DS_0[] = { + { "OFFSET0", 0, 7, &umr_bitfield_default }, + { "OFFSET1", 8, 15, &umr_bitfield_default }, + { "GDS", 16, 16, &umr_bitfield_default }, + { "OP", 17, 24, &umr_bitfield_default }, + { "ENCODING", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_DS_1[] = { + { "ADDR", 0, 7, &umr_bitfield_default }, + { "DATA0", 8, 15, &umr_bitfield_default }, + { "DATA1", 16, 23, &umr_bitfield_default }, + { "VDST", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_EXP_0[] = { + { "EN", 0, 3, &umr_bitfield_default }, + { "TGT", 4, 9, &umr_bitfield_default }, + { "COMPR", 10, 10, &umr_bitfield_default }, + { "DONE", 11, 11, &umr_bitfield_default }, + { "VM", 12, 12, &umr_bitfield_default }, + { "ENCODING", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_EXP_1[] = { + { "VSRC0", 0, 7, &umr_bitfield_default }, + { "VSRC1", 8, 15, &umr_bitfield_default }, + { "VSRC2", 16, 23, &umr_bitfield_default }, + { "VSRC3", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_FLAT_0[] = { + { "OFFSET", 0, 11, &umr_bitfield_default }, + { "LDS", 13, 13, &umr_bitfield_default }, + { "SEG", 14, 15, &umr_bitfield_default }, + { "GLC", 16, 16, &umr_bitfield_default }, + { "SLC", 17, 17, &umr_bitfield_default }, + { "OP", 18, 24, &umr_bitfield_default }, + { "ENCODING", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_FLAT_1[] = { + { "ADDR", 0, 7, &umr_bitfield_default }, + { "DATA", 8, 15, &umr_bitfield_default }, + { "SADDR", 16, 22, &umr_bitfield_default }, + { "NV", 23, 23, &umr_bitfield_default }, + { "VDST", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_GLBL_0[] = { + { "OFFSET", 0, 12, &umr_bitfield_default }, + { "LDS", 13, 13, &umr_bitfield_default }, + { "SEG", 14, 15, &umr_bitfield_default }, + { "GLC", 16, 16, &umr_bitfield_default }, + { "SLC", 17, 17, &umr_bitfield_default }, + { "OP", 18, 24, &umr_bitfield_default }, + { "ENCODING", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_GLBL_1[] = { + { "ADDR", 0, 7, &umr_bitfield_default }, + { "DATA", 8, 15, &umr_bitfield_default }, + { "SADDR", 16, 22, &umr_bitfield_default }, + { "NV", 23, 23, &umr_bitfield_default }, + { "VDST", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_INST[] = { + { "ENCODING", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_MIMG_0[] = { + { "OPM", 0, 0, &umr_bitfield_default }, + { "DMASK", 8, 11, &umr_bitfield_default }, + { "UNORM", 12, 12, &umr_bitfield_default }, + { "GLC", 13, 13, &umr_bitfield_default }, + { "DA", 14, 14, &umr_bitfield_default }, + { "A16", 15, 15, &umr_bitfield_default }, + { "TFE", 16, 16, &umr_bitfield_default }, + { "LWE", 17, 17, &umr_bitfield_default }, + { "OP", 18, 24, &umr_bitfield_default }, + { "SLC", 25, 25, &umr_bitfield_default }, + { "ENCODING", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_MIMG_1[] = { + { "VADDR", 0, 7, &umr_bitfield_default }, + { "VDATA", 8, 15, &umr_bitfield_default }, + { "SRSRC", 16, 20, &umr_bitfield_default }, + { "SSAMP", 21, 25, &umr_bitfield_default }, + { "D16", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_MTBUF_0[] = { + { "OFFSET", 0, 11, &umr_bitfield_default }, + { "OFFEN", 12, 12, &umr_bitfield_default }, + { "IDXEN", 13, 13, &umr_bitfield_default }, + { "GLC", 14, 14, &umr_bitfield_default }, + { "OP", 15, 18, &umr_bitfield_default }, + { "DFMT", 19, 22, &umr_bitfield_default }, + { "NFMT", 23, 25, &umr_bitfield_default }, + { "ENCODING", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_MTBUF_1[] = { + { "VADDR", 0, 7, &umr_bitfield_default }, + { "VDATA", 8, 15, &umr_bitfield_default }, + { "SRSRC", 16, 20, &umr_bitfield_default }, + { "SLC", 22, 22, &umr_bitfield_default }, + { "TFE", 23, 23, &umr_bitfield_default }, + { "SOFFSET", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_MUBUF_0[] = { + { "OFFSET", 0, 11, &umr_bitfield_default }, + { "OFFEN", 12, 12, &umr_bitfield_default }, + { "IDXEN", 13, 13, &umr_bitfield_default }, + { "GLC", 14, 14, &umr_bitfield_default }, + { "LDS", 16, 16, &umr_bitfield_default }, + { "SLC", 17, 17, &umr_bitfield_default }, + { "OP", 18, 24, &umr_bitfield_default }, + { "ENCODING", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_MUBUF_1[] = { + { "VADDR", 0, 7, &umr_bitfield_default }, + { "VDATA", 8, 15, &umr_bitfield_default }, + { "SRSRC", 16, 20, &umr_bitfield_default }, + { "TFE", 23, 23, &umr_bitfield_default }, + { "SOFFSET", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_SCRATCH_0[] = { + { "OFFSET", 0, 12, &umr_bitfield_default }, + { "LDS", 13, 13, &umr_bitfield_default }, + { "SEG", 14, 15, &umr_bitfield_default }, + { "GLC", 16, 16, &umr_bitfield_default }, + { "SLC", 17, 17, &umr_bitfield_default }, + { "OP", 18, 24, &umr_bitfield_default }, + { "ENCODING", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_SCRATCH_1[] = { + { "ADDR", 0, 7, &umr_bitfield_default }, + { "DATA", 8, 15, &umr_bitfield_default }, + { "SADDR", 16, 22, &umr_bitfield_default }, + { "NV", 23, 23, &umr_bitfield_default }, + { "VDST", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_SMEM_0[] = { + { "SBASE", 0, 5, &umr_bitfield_default }, + { "SDATA", 6, 12, &umr_bitfield_default }, + { "SOFFSET_EN", 14, 14, &umr_bitfield_default }, + { "NV", 15, 15, &umr_bitfield_default }, + { "GLC", 16, 16, &umr_bitfield_default }, + { "IMM", 17, 17, &umr_bitfield_default }, + { "OP", 18, 25, &umr_bitfield_default }, + { "ENCODING", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_SMEM_1[] = { + { "OFFSET", 0, 20, &umr_bitfield_default }, + { "SOFFSET", 25, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_SOP1[] = { + { "SSRC0", 0, 7, &umr_bitfield_default }, + { "OP", 8, 15, &umr_bitfield_default }, + { "SDST", 16, 22, &umr_bitfield_default }, + { "ENCODING", 23, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_SOP2[] = { + { "SSRC0", 0, 7, &umr_bitfield_default }, + { "SSRC1", 8, 15, &umr_bitfield_default }, + { "SDST", 16, 22, &umr_bitfield_default }, + { "OP", 23, 29, &umr_bitfield_default }, + { "ENCODING", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_SOPC[] = { + { "SSRC0", 0, 7, &umr_bitfield_default }, + { "SSRC1", 8, 15, &umr_bitfield_default }, + { "OP", 16, 22, &umr_bitfield_default }, + { "ENCODING", 23, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_SOPK[] = { + { "SIMM16", 0, 15, &umr_bitfield_default }, + { "SDST", 16, 22, &umr_bitfield_default }, + { "OP", 23, 27, &umr_bitfield_default }, + { "ENCODING", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_SOPP[] = { + { "SIMM16", 0, 15, &umr_bitfield_default }, + { "OP", 16, 22, &umr_bitfield_default }, + { "ENCODING", 23, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_VINTRP[] = { + { "VSRC", 0, 7, &umr_bitfield_default }, + { "ATTRCHAN", 8, 9, &umr_bitfield_default }, + { "ATTR", 10, 15, &umr_bitfield_default }, + { "OP", 16, 17, &umr_bitfield_default }, + { "VDST", 18, 25, &umr_bitfield_default }, + { "ENCODING", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_VOP1[] = { + { "SRC0", 0, 8, &umr_bitfield_default }, + { "OP", 9, 16, &umr_bitfield_default }, + { "VDST", 17, 24, &umr_bitfield_default }, + { "ENCODING", 25, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_VOP2[] = { + { "SRC0", 0, 8, &umr_bitfield_default }, + { "VSRC1", 9, 16, &umr_bitfield_default }, + { "VDST", 17, 24, &umr_bitfield_default }, + { "OP", 25, 30, &umr_bitfield_default }, + { "ENCODING", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_VOP3P_0[] = { + { "VDST", 0, 7, &umr_bitfield_default }, + { "NEG_HI", 8, 10, &umr_bitfield_default }, + { "OP_SEL", 11, 13, &umr_bitfield_default }, + { "OP_SEL_HI_2", 14, 14, &umr_bitfield_default }, + { "CLAMP", 15, 15, &umr_bitfield_default }, + { "OP", 16, 22, &umr_bitfield_default }, + { "ENCODING", 23, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_VOP3P_1[] = { + { "SRC0", 0, 8, &umr_bitfield_default }, + { "SRC1", 9, 17, &umr_bitfield_default }, + { "SRC2", 18, 26, &umr_bitfield_default }, + { "OP_SEL_HI", 27, 28, &umr_bitfield_default }, + { "NEG", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_VOP3_0[] = { + { "VDST", 0, 7, &umr_bitfield_default }, + { "ABS", 8, 10, &umr_bitfield_default }, + { "OP_SEL", 11, 14, &umr_bitfield_default }, + { "CLAMP", 15, 15, &umr_bitfield_default }, + { "OP", 16, 25, &umr_bitfield_default }, + { "ENCODING", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_VOP3_0_SDST_ENC[] = { + { "VDST", 0, 7, &umr_bitfield_default }, + { "SDST", 8, 14, &umr_bitfield_default }, + { "CLAMP", 15, 15, &umr_bitfield_default }, + { "OP", 16, 25, &umr_bitfield_default }, + { "ENCODING", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_VOP3_1[] = { + { "SRC0", 0, 8, &umr_bitfield_default }, + { "SRC1", 9, 17, &umr_bitfield_default }, + { "SRC2", 18, 26, &umr_bitfield_default }, + { "OMOD", 27, 28, &umr_bitfield_default }, + { "NEG", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_VOPC[] = { + { "SRC0", 0, 8, &umr_bitfield_default }, + { "VSRC1", 9, 16, &umr_bitfield_default }, + { "OP", 17, 24, &umr_bitfield_default }, + { "ENCODING", 25, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_VOP_DPP[] = { + { "SRC0", 0, 7, &umr_bitfield_default }, + { "DPP_CTRL", 8, 16, &umr_bitfield_default }, + { "BOUND_CTRL", 19, 19, &umr_bitfield_default }, + { "SRC0_NEG", 20, 20, &umr_bitfield_default }, + { "SRC0_ABS", 21, 21, &umr_bitfield_default }, + { "SRC1_NEG", 22, 22, &umr_bitfield_default }, + { "SRC1_ABS", 23, 23, &umr_bitfield_default }, + { "BANK_MASK", 24, 27, &umr_bitfield_default }, + { "ROW_MASK", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_VOP_SDWA[] = { + { "SRC0", 0, 7, &umr_bitfield_default }, + { "DST_SEL", 8, 10, &umr_bitfield_default }, + { "DST_UNUSED", 11, 12, &umr_bitfield_default }, + { "CLAMP", 13, 13, &umr_bitfield_default }, + { "OMOD", 14, 15, &umr_bitfield_default }, + { "SRC0_SEL", 16, 18, &umr_bitfield_default }, + { "SRC0_SEXT", 19, 19, &umr_bitfield_default }, + { "SRC0_NEG", 20, 20, &umr_bitfield_default }, + { "SRC0_ABS", 21, 21, &umr_bitfield_default }, + { "S0", 23, 23, &umr_bitfield_default }, + { "SRC1_SEL", 24, 26, &umr_bitfield_default }, + { "SRC1_SEXT", 27, 27, &umr_bitfield_default }, + { "SRC1_NEG", 28, 28, &umr_bitfield_default }, + { "SRC1_ABS", 29, 29, &umr_bitfield_default }, + { "S1", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_VOP_SDWA_SDST_ENC[] = { + { "SRC0", 0, 7, &umr_bitfield_default }, + { "SDST", 8, 14, &umr_bitfield_default }, + { "SD", 15, 15, &umr_bitfield_default }, + { "SRC0_SEL", 16, 18, &umr_bitfield_default }, + { "SRC0_SEXT", 19, 19, &umr_bitfield_default }, + { "SRC0_NEG", 20, 20, &umr_bitfield_default }, + { "SRC0_ABS", 21, 21, &umr_bitfield_default }, + { "S0", 23, 23, &umr_bitfield_default }, + { "SRC1_SEL", 24, 26, &umr_bitfield_default }, + { "SRC1_SEXT", 27, 27, &umr_bitfield_default }, + { "SRC1_NEG", 28, 28, &umr_bitfield_default }, + { "SRC1_ABS", 29, 29, &umr_bitfield_default }, + { "S1", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_LB_CTR_CTRL[] = { + { "START", 0, 0, &umr_bitfield_default }, + { "LOAD", 1, 1, &umr_bitfield_default }, + { "CLEAR", 2, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_LB_DATA0[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_LB_DATA1[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_LB_DATA2[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_LB_DATA3[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_LB_CTR_SEL[] = { + { "SEL0", 0, 3, &umr_bitfield_default }, + { "SEL1", 4, 7, &umr_bitfield_default }, + { "SEL2", 8, 11, &umr_bitfield_default }, + { "SEL3", 12, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_LB_CTR0_CU[] = { + { "SH0_MASK", 0, 15, &umr_bitfield_default }, + { "SH1_MASK", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_LB_CTR1_CU[] = { + { "SH0_MASK", 0, 15, &umr_bitfield_default }, + { "SH1_MASK", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_LB_CTR2_CU[] = { + { "SH0_MASK", 0, 15, &umr_bitfield_default }, + { "SH1_MASK", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_LB_CTR3_CU[] = { + { "SH0_MASK", 0, 15, &umr_bitfield_default }, + { "SH1_MASK", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQC_EDC_CNT[] = { + { "DATA_CU0_WRITE_DATA_BUF_SEC_COUNT", 0, 1, &umr_bitfield_default }, + { "DATA_CU0_WRITE_DATA_BUF_DED_COUNT", 2, 3, &umr_bitfield_default }, + { "DATA_CU0_UTCL1_LFIFO_SEC_COUNT", 4, 5, &umr_bitfield_default }, + { "DATA_CU0_UTCL1_LFIFO_DED_COUNT", 6, 7, &umr_bitfield_default }, + { "DATA_CU1_WRITE_DATA_BUF_SEC_COUNT", 8, 9, &umr_bitfield_default }, + { "DATA_CU1_WRITE_DATA_BUF_DED_COUNT", 10, 11, &umr_bitfield_default }, + { "DATA_CU1_UTCL1_LFIFO_SEC_COUNT", 12, 13, &umr_bitfield_default }, + { "DATA_CU1_UTCL1_LFIFO_DED_COUNT", 14, 15, &umr_bitfield_default }, + { "DATA_CU2_WRITE_DATA_BUF_SEC_COUNT", 16, 17, &umr_bitfield_default }, + { "DATA_CU2_WRITE_DATA_BUF_DED_COUNT", 18, 19, &umr_bitfield_default }, + { "DATA_CU2_UTCL1_LFIFO_SEC_COUNT", 20, 21, &umr_bitfield_default }, + { "DATA_CU2_UTCL1_LFIFO_DED_COUNT", 22, 23, &umr_bitfield_default }, + { "DATA_CU3_WRITE_DATA_BUF_SEC_COUNT", 24, 25, &umr_bitfield_default }, + { "DATA_CU3_WRITE_DATA_BUF_DED_COUNT", 26, 27, &umr_bitfield_default }, + { "DATA_CU3_UTCL1_LFIFO_SEC_COUNT", 28, 29, &umr_bitfield_default }, + { "DATA_CU3_UTCL1_LFIFO_DED_COUNT", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_EDC_SEC_CNT[] = { + { "LDS_SEC", 0, 7, &umr_bitfield_default }, + { "SGPR_SEC", 8, 15, &umr_bitfield_default }, + { "VGPR_SEC", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_EDC_DED_CNT[] = { + { "LDS_DED", 0, 7, &umr_bitfield_default }, + { "SGPR_DED", 8, 15, &umr_bitfield_default }, + { "VGPR_DED", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_EDC_INFO[] = { + { "WAVE_ID", 0, 3, &umr_bitfield_default }, + { "SIMD_ID", 4, 5, &umr_bitfield_default }, + { "SOURCE", 6, 8, &umr_bitfield_default }, + { "VM_ID", 9, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_EDC_CNT[] = { + { "LDS_D_SEC_COUNT", 0, 1, &umr_bitfield_default }, + { "LDS_D_DED_COUNT", 2, 3, &umr_bitfield_default }, + { "LDS_I_SEC_COUNT", 4, 5, &umr_bitfield_default }, + { "LDS_I_DED_COUNT", 6, 7, &umr_bitfield_default }, + { "SGPR_SEC_COUNT", 8, 9, &umr_bitfield_default }, + { "SGPR_DED_COUNT", 10, 11, &umr_bitfield_default }, + { "VGPR0_SEC_COUNT", 12, 13, &umr_bitfield_default }, + { "VGPR0_DED_COUNT", 14, 15, &umr_bitfield_default }, + { "VGPR1_SEC_COUNT", 16, 17, &umr_bitfield_default }, + { "VGPR1_DED_COUNT", 18, 19, &umr_bitfield_default }, + { "VGPR2_SEC_COUNT", 20, 21, &umr_bitfield_default }, + { "VGPR2_DED_COUNT", 22, 23, &umr_bitfield_default }, + { "VGPR3_SEC_COUNT", 24, 25, &umr_bitfield_default }, + { "VGPR3_DED_COUNT", 26, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_EDC_FUE_CNTL[] = { + { "BLOCK_FUE_FLAGS", 0, 15, &umr_bitfield_default }, + { "FUE_INTERRUPT_ENABLES", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_THREAD_TRACE_WORD_CMN[] = { + { "TOKEN_TYPE", 0, 3, &umr_bitfield_default }, + { "TIME_DELTA", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_THREAD_TRACE_WORD_EVENT[] = { + { "TOKEN_TYPE", 0, 3, &umr_bitfield_default }, + { "TIME_DELTA", 4, 4, &umr_bitfield_default }, + { "SH_ID", 5, 5, &umr_bitfield_default }, + { "STAGE", 6, 8, &umr_bitfield_default }, + { "EVENT_TYPE", 10, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_THREAD_TRACE_WORD_INST[] = { + { "TOKEN_TYPE", 0, 3, &umr_bitfield_default }, + { "TIME_DELTA", 4, 4, &umr_bitfield_default }, + { "WAVE_ID", 5, 8, &umr_bitfield_default }, + { "SIMD_ID", 9, 10, &umr_bitfield_default }, + { "INST_TYPE", 11, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2[] = { + { "TOKEN_TYPE", 0, 3, &umr_bitfield_default }, + { "TIME_DELTA", 4, 4, &umr_bitfield_default }, + { "WAVE_ID", 5, 8, &umr_bitfield_default }, + { "SIMD_ID", 9, 10, &umr_bitfield_default }, + { "TRAP_ERROR", 15, 15, &umr_bitfield_default }, + { "PC_LO", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2[] = { + { "TOKEN_TYPE", 0, 3, &umr_bitfield_default }, + { "TIME_DELTA", 4, 4, &umr_bitfield_default }, + { "SH_ID", 5, 5, &umr_bitfield_default }, + { "CU_ID", 6, 9, &umr_bitfield_default }, + { "WAVE_ID", 10, 13, &umr_bitfield_default }, + { "SIMD_ID", 14, 15, &umr_bitfield_default }, + { "DATA_LO", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_THREAD_TRACE_WORD_ISSUE[] = { + { "TOKEN_TYPE", 0, 3, &umr_bitfield_default }, + { "TIME_DELTA", 4, 4, &umr_bitfield_default }, + { "SIMD_ID", 5, 6, &umr_bitfield_default }, + { "INST0", 8, 9, &umr_bitfield_default }, + { "INST1", 10, 11, &umr_bitfield_default }, + { "INST2", 12, 13, &umr_bitfield_default }, + { "INST3", 14, 15, &umr_bitfield_default }, + { "INST4", 16, 17, &umr_bitfield_default }, + { "INST5", 18, 19, &umr_bitfield_default }, + { "INST6", 20, 21, &umr_bitfield_default }, + { "INST7", 22, 23, &umr_bitfield_default }, + { "INST8", 24, 25, &umr_bitfield_default }, + { "INST9", 26, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_THREAD_TRACE_WORD_MISC[] = { + { "TOKEN_TYPE", 0, 3, &umr_bitfield_default }, + { "TIME_DELTA", 4, 11, &umr_bitfield_default }, + { "SH_ID", 12, 12, &umr_bitfield_default }, + { "MISC_TOKEN_TYPE", 13, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2[] = { + { "TOKEN_TYPE", 0, 3, &umr_bitfield_default }, + { "TIME_DELTA", 4, 4, &umr_bitfield_default }, + { "SH_ID", 5, 5, &umr_bitfield_default }, + { "CU_ID", 6, 9, &umr_bitfield_default }, + { "CNTR_BANK", 10, 11, &umr_bitfield_default }, + { "CNTR0", 12, 24, &umr_bitfield_default }, + { "CNTR1_LO", 25, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_THREAD_TRACE_WORD_REG_1_OF_2[] = { + { "TOKEN_TYPE", 0, 3, &umr_bitfield_default }, + { "TIME_DELTA", 4, 4, &umr_bitfield_default }, + { "PIPE_ID", 5, 6, &umr_bitfield_default }, + { "ME_ID", 7, 8, &umr_bitfield_default }, + { "REG_DROPPED_PREV", 9, 9, &umr_bitfield_default }, + { "REG_TYPE", 10, 12, &umr_bitfield_default }, + { "REG_PRIV", 14, 14, &umr_bitfield_default }, + { "REG_OP", 15, 15, &umr_bitfield_default }, + { "REG_ADDR", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_THREAD_TRACE_WORD_REG_2_OF_2[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2[] = { + { "TOKEN_TYPE", 0, 3, &umr_bitfield_default }, + { "TIME_DELTA", 4, 4, &umr_bitfield_default }, + { "PIPE_ID", 5, 6, &umr_bitfield_default }, + { "ME_ID", 7, 8, &umr_bitfield_default }, + { "REG_ADDR", 9, 15, &umr_bitfield_default }, + { "DATA_LO", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2[] = { + { "DATA_HI", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2[] = { + { "TOKEN_TYPE", 0, 3, &umr_bitfield_default }, + { "TIME_LO", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_THREAD_TRACE_WORD_WAVE[] = { + { "TOKEN_TYPE", 0, 3, &umr_bitfield_default }, + { "TIME_DELTA", 4, 4, &umr_bitfield_default }, + { "SH_ID", 5, 5, &umr_bitfield_default }, + { "CU_ID", 6, 9, &umr_bitfield_default }, + { "WAVE_ID", 10, 13, &umr_bitfield_default }, + { "SIMD_ID", 14, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_THREAD_TRACE_WORD_WAVE_START[] = { + { "TOKEN_TYPE", 0, 3, &umr_bitfield_default }, + { "TIME_DELTA", 4, 4, &umr_bitfield_default }, + { "SH_ID", 5, 5, &umr_bitfield_default }, + { "CU_ID", 6, 9, &umr_bitfield_default }, + { "WAVE_ID", 10, 13, &umr_bitfield_default }, + { "SIMD_ID", 14, 15, &umr_bitfield_default }, + { "DISPATCHER", 16, 20, &umr_bitfield_default }, + { "VS_NO_ALLOC_OR_GROUPED", 21, 21, &umr_bitfield_default }, + { "COUNT", 22, 28, &umr_bitfield_default }, + { "TG_ID", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2[] = { + { "PC_HI", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2[] = { + { "DATA_HI", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2[] = { + { "CNTR1_HI", 0, 5, &umr_bitfield_default }, + { "CNTR2", 6, 18, &umr_bitfield_default }, + { "CNTR3", 19, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2[] = { + { "TIME_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_WREXEC_EXEC_HI[] = { + { "ADDR_HI", 0, 15, &umr_bitfield_default }, + { "FIRST_WAVE", 26, 26, &umr_bitfield_default }, + { "ATC", 27, 27, &umr_bitfield_default }, + { "MTYPE", 28, 30, &umr_bitfield_default }, + { "MSB", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_WREXEC_EXEC_LO[] = { + { "ADDR_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_BUF_RSRC_WORD0[] = { + { "BASE_ADDRESS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_BUF_RSRC_WORD1[] = { + { "BASE_ADDRESS_HI", 0, 15, &umr_bitfield_default }, + { "STRIDE", 16, 29, &umr_bitfield_default }, + { "CACHE_SWIZZLE", 30, 30, &umr_bitfield_default }, + { "SWIZZLE_ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_BUF_RSRC_WORD2[] = { + { "NUM_RECORDS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_BUF_RSRC_WORD3[] = { + { "DST_SEL_X", 0, 2, &umr_bitfield_default }, + { "DST_SEL_Y", 3, 5, &umr_bitfield_default }, + { "DST_SEL_Z", 6, 8, &umr_bitfield_default }, + { "DST_SEL_W", 9, 11, &umr_bitfield_default }, + { "NUM_FORMAT", 12, 14, &umr_bitfield_default }, + { "DATA_FORMAT", 15, 18, &umr_bitfield_default }, + { "USER_VM_ENABLE", 19, 19, &umr_bitfield_default }, + { "USER_VM_MODE", 20, 20, &umr_bitfield_default }, + { "INDEX_STRIDE", 21, 22, &umr_bitfield_default }, + { "ADD_TID_ENABLE", 23, 23, &umr_bitfield_default }, + { "NV", 27, 27, &umr_bitfield_default }, + { "TYPE", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_IMG_RSRC_WORD0[] = { + { "BASE_ADDRESS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_IMG_RSRC_WORD1[] = { + { "BASE_ADDRESS_HI", 0, 7, &umr_bitfield_default }, + { "MIN_LOD", 8, 19, &umr_bitfield_default }, + { "DATA_FORMAT", 20, 25, &umr_bitfield_default }, + { "NUM_FORMAT", 26, 29, &umr_bitfield_default }, + { "NV", 30, 30, &umr_bitfield_default }, + { "META_DIRECT", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_IMG_RSRC_WORD2[] = { + { "WIDTH", 0, 13, &umr_bitfield_default }, + { "HEIGHT", 14, 27, &umr_bitfield_default }, + { "PERF_MOD", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_IMG_RSRC_WORD3[] = { + { "DST_SEL_X", 0, 2, &umr_bitfield_default }, + { "DST_SEL_Y", 3, 5, &umr_bitfield_default }, + { "DST_SEL_Z", 6, 8, &umr_bitfield_default }, + { "DST_SEL_W", 9, 11, &umr_bitfield_default }, + { "BASE_LEVEL", 12, 15, &umr_bitfield_default }, + { "LAST_LEVEL", 16, 19, &umr_bitfield_default }, + { "SW_MODE", 20, 24, &umr_bitfield_default }, + { "TYPE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_IMG_RSRC_WORD4[] = { + { "DEPTH", 0, 12, &umr_bitfield_default }, + { "PITCH", 13, 28, &umr_bitfield_default }, + { "BC_SWIZZLE", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_IMG_RSRC_WORD5[] = { + { "BASE_ARRAY", 0, 12, &umr_bitfield_default }, + { "ARRAY_PITCH", 13, 16, &umr_bitfield_default }, + { "META_DATA_ADDRESS", 17, 24, &umr_bitfield_default }, + { "META_LINEAR", 25, 25, &umr_bitfield_default }, + { "META_PIPE_ALIGNED", 26, 26, &umr_bitfield_default }, + { "META_RB_ALIGNED", 27, 27, &umr_bitfield_default }, + { "MAX_MIP", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_IMG_RSRC_WORD6[] = { + { "MIN_LOD_WARN", 0, 11, &umr_bitfield_default }, + { "COUNTER_BANK_ID", 12, 19, &umr_bitfield_default }, + { "LOD_HDW_CNT_EN", 20, 20, &umr_bitfield_default }, + { "COMPRESSION_EN", 21, 21, &umr_bitfield_default }, + { "ALPHA_IS_ON_MSB", 22, 22, &umr_bitfield_default }, + { "COLOR_TRANSFORM", 23, 23, &umr_bitfield_default }, + { "LOST_ALPHA_BITS", 24, 27, &umr_bitfield_default }, + { "LOST_COLOR_BITS", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_IMG_RSRC_WORD7[] = { + { "META_DATA_ADDRESS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_IMG_SAMP_WORD0[] = { + { "CLAMP_X", 0, 2, &umr_bitfield_default }, + { "CLAMP_Y", 3, 5, &umr_bitfield_default }, + { "CLAMP_Z", 6, 8, &umr_bitfield_default }, + { "MAX_ANISO_RATIO", 9, 11, &umr_bitfield_default }, + { "DEPTH_COMPARE_FUNC", 12, 14, &umr_bitfield_default }, + { "FORCE_UNNORMALIZED", 15, 15, &umr_bitfield_default }, + { "ANISO_THRESHOLD", 16, 18, &umr_bitfield_default }, + { "MC_COORD_TRUNC", 19, 19, &umr_bitfield_default }, + { "FORCE_DEGAMMA", 20, 20, &umr_bitfield_default }, + { "ANISO_BIAS", 21, 26, &umr_bitfield_default }, + { "TRUNC_COORD", 27, 27, &umr_bitfield_default }, + { "DISABLE_CUBE_WRAP", 28, 28, &umr_bitfield_default }, + { "FILTER_MODE", 29, 30, &umr_bitfield_default }, + { "COMPAT_MODE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_IMG_SAMP_WORD1[] = { + { "MIN_LOD", 0, 11, &umr_bitfield_default }, + { "MAX_LOD", 12, 23, &umr_bitfield_default }, + { "PERF_MIP", 24, 27, &umr_bitfield_default }, + { "PERF_Z", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_IMG_SAMP_WORD2[] = { + { "LOD_BIAS", 0, 13, &umr_bitfield_default }, + { "LOD_BIAS_SEC", 14, 19, &umr_bitfield_default }, + { "XY_MAG_FILTER", 20, 21, &umr_bitfield_default }, + { "XY_MIN_FILTER", 22, 23, &umr_bitfield_default }, + { "Z_FILTER", 24, 25, &umr_bitfield_default }, + { "MIP_FILTER", 26, 27, &umr_bitfield_default }, + { "MIP_POINT_PRECLAMP", 28, 28, &umr_bitfield_default }, + { "BLEND_ZERO_PRT", 29, 29, &umr_bitfield_default }, + { "FILTER_PREC_FIX", 30, 30, &umr_bitfield_default }, + { "ANISO_OVERRIDE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_IMG_SAMP_WORD3[] = { + { "BORDER_COLOR_PTR", 0, 11, &umr_bitfield_default }, + { "SKIP_DEGAMMA", 12, 12, &umr_bitfield_default }, + { "BORDER_COLOR_TYPE", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_FLAT_SCRATCH_WORD0[] = { + { "SIZE", 0, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_FLAT_SCRATCH_WORD1[] = { + { "OFFSET", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_M0_GPR_IDX_WORD[] = { + { "INDEX", 0, 7, &umr_bitfield_default }, + { "VSRC0_REL", 12, 12, &umr_bitfield_default }, + { "VSRC1_REL", 13, 13, &umr_bitfield_default }, + { "VSRC2_REL", 14, 14, &umr_bitfield_default }, + { "VDST_REL", 15, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQC_ICACHE_UTCL1_CNTL1[] = { + { "FORCE_4K_L2_RESP", 0, 0, &umr_bitfield_default }, + { "GPUVM_64K_DEF", 1, 1, &umr_bitfield_default }, + { "GPUVM_PERM_MODE", 2, 2, &umr_bitfield_default }, + { "RESP_MODE", 3, 4, &umr_bitfield_default }, + { "RESP_FAULT_MODE", 5, 6, &umr_bitfield_default }, + { "CLIENTID", 7, 15, &umr_bitfield_default }, + { "ENABLE_PUSH_LFIFO", 17, 17, &umr_bitfield_default }, + { "ENABLE_LFIFO_PRI_ARB", 18, 18, &umr_bitfield_default }, + { "REG_INVALIDATE_VMID", 19, 22, &umr_bitfield_default }, + { "REG_INVALIDATE_ALL_VMID", 23, 23, &umr_bitfield_default }, + { "REG_INVALIDATE_TOGGLE", 24, 24, &umr_bitfield_default }, + { "CLIENT_INVALIDATE_ALL_VMID", 25, 25, &umr_bitfield_default }, + { "FORCE_MISS", 26, 26, &umr_bitfield_default }, + { "FORCE_IN_ORDER", 27, 27, &umr_bitfield_default }, + { "REDUCE_FIFO_DEPTH_BY_2", 28, 29, &umr_bitfield_default }, + { "REDUCE_CACHE_SIZE_BY_2", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQC_ICACHE_UTCL1_CNTL2[] = { + { "SPARE", 0, 7, &umr_bitfield_default }, + { "LFIFO_SCAN_DISABLE", 8, 8, &umr_bitfield_default }, + { "MTYPE_OVRD_DIS", 9, 9, &umr_bitfield_default }, + { "LINE_VALID", 10, 10, &umr_bitfield_default }, + { "DIS_EDC", 11, 11, &umr_bitfield_default }, + { "GPUVM_INV_MODE", 12, 12, &umr_bitfield_default }, + { "SHOOTDOWN_OPT", 13, 13, &umr_bitfield_default }, + { "FORCE_SNOOP", 14, 14, &umr_bitfield_default }, + { "FORCE_GPUVM_INV_ACK", 15, 15, &umr_bitfield_default }, + { "ARB_BURST_MODE", 16, 17, &umr_bitfield_default }, + { "ENABLE_PERF_EVENT_RD_WR", 18, 18, &umr_bitfield_default }, + { "PERF_EVENT_RD_WR", 19, 19, &umr_bitfield_default }, + { "ENABLE_PERF_EVENT_VMID", 20, 20, &umr_bitfield_default }, + { "PERF_EVENT_VMID", 21, 24, &umr_bitfield_default }, + { "FORCE_FRAG_2M_TO_64K", 26, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQC_DCACHE_UTCL1_CNTL1[] = { + { "FORCE_4K_L2_RESP", 0, 0, &umr_bitfield_default }, + { "GPUVM_64K_DEF", 1, 1, &umr_bitfield_default }, + { "GPUVM_PERM_MODE", 2, 2, &umr_bitfield_default }, + { "RESP_MODE", 3, 4, &umr_bitfield_default }, + { "RESP_FAULT_MODE", 5, 6, &umr_bitfield_default }, + { "CLIENTID", 7, 15, &umr_bitfield_default }, + { "ENABLE_PUSH_LFIFO", 17, 17, &umr_bitfield_default }, + { "ENABLE_LFIFO_PRI_ARB", 18, 18, &umr_bitfield_default }, + { "REG_INVALIDATE_VMID", 19, 22, &umr_bitfield_default }, + { "REG_INVALIDATE_ALL_VMID", 23, 23, &umr_bitfield_default }, + { "REG_INVALIDATE_TOGGLE", 24, 24, &umr_bitfield_default }, + { "CLIENT_INVALIDATE_ALL_VMID", 25, 25, &umr_bitfield_default }, + { "FORCE_MISS", 26, 26, &umr_bitfield_default }, + { "FORCE_IN_ORDER", 27, 27, &umr_bitfield_default }, + { "REDUCE_FIFO_DEPTH_BY_2", 28, 29, &umr_bitfield_default }, + { "REDUCE_CACHE_SIZE_BY_2", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQC_DCACHE_UTCL1_CNTL2[] = { + { "SPARE", 0, 7, &umr_bitfield_default }, + { "LFIFO_SCAN_DISABLE", 8, 8, &umr_bitfield_default }, + { "MTYPE_OVRD_DIS", 9, 9, &umr_bitfield_default }, + { "LINE_VALID", 10, 10, &umr_bitfield_default }, + { "DIS_EDC", 11, 11, &umr_bitfield_default }, + { "GPUVM_INV_MODE", 12, 12, &umr_bitfield_default }, + { "SHOOTDOWN_OPT", 13, 13, &umr_bitfield_default }, + { "FORCE_SNOOP", 14, 14, &umr_bitfield_default }, + { "FORCE_GPUVM_INV_ACK", 15, 15, &umr_bitfield_default }, + { "ARB_BURST_MODE", 16, 17, &umr_bitfield_default }, + { "ENABLE_PERF_EVENT_RD_WR", 18, 18, &umr_bitfield_default }, + { "PERF_EVENT_RD_WR", 19, 19, &umr_bitfield_default }, + { "ENABLE_PERF_EVENT_VMID", 20, 20, &umr_bitfield_default }, + { "PERF_EVENT_VMID", 21, 24, &umr_bitfield_default }, + { "FORCE_FRAG_2M_TO_64K", 26, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQC_ICACHE_UTCL1_STATUS[] = { + { "FAULT_DETECTED", 0, 0, &umr_bitfield_default }, + { "RETRY_DETECTED", 1, 1, &umr_bitfield_default }, + { "PRT_DETECTED", 2, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQC_DCACHE_UTCL1_STATUS[] = { + { "FAULT_DETECTED", 0, 0, &umr_bitfield_default }, + { "RETRY_DETECTED", 1, 1, &umr_bitfield_default }, + { "PRT_DETECTED", 2, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSX_DEBUG_1[] = { + { "SX_DB_QUAD_CREDIT", 0, 6, &umr_bitfield_default }, + { "DISABLE_BLEND_OPT_DONT_RD_DST", 8, 8, &umr_bitfield_default }, + { "DISABLE_BLEND_OPT_BYPASS", 9, 9, &umr_bitfield_default }, + { "DISABLE_BLEND_OPT_DISCARD_PIXEL", 10, 10, &umr_bitfield_default }, + { "DISABLE_QUAD_PAIR_OPT", 11, 11, &umr_bitfield_default }, + { "DISABLE_PIX_EN_ZERO_OPT", 12, 12, &umr_bitfield_default }, + { "PC_CFG", 13, 13, &umr_bitfield_default }, + { "DEBUG_DATA", 14, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_PS_MAX_WAVE_ID[] = { + { "MAX_WAVE_ID", 0, 11, &umr_bitfield_default }, + { "MAX_COLLISION_WAVE_ID", 16, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_START_PHASE[] = { + { "VGPR_START_PHASE", 0, 1, &umr_bitfield_default }, + { "SGPR_START_PHASE", 2, 3, &umr_bitfield_default }, + { "WAVE_START_PHASE", 4, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_GFX_CNTL[] = { + { "RESET_COUNTS", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_DSM_CNTL[] = { + { "SPI_SR_MEM_DSM_IRRITATOR_DATA", 0, 1, &umr_bitfield_default }, + { "SPI_SR_MEM_ENABLE_SINGLE_WRITE", 2, 2, &umr_bitfield_default }, + { "UNUSED", 3, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_DSM_CNTL2[] = { + { "SPI_SR_MEM_ENABLE_ERROR_INJECT", 0, 1, &umr_bitfield_default }, + { "SPI_SR_MEM_SELECT_INJECT_DELAY", 2, 2, &umr_bitfield_default }, + { "SPI_SR_MEM_INJECT_DELAY", 4, 9, &umr_bitfield_default }, + { "UNUSED", 10, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_EDC_CNT[] = { + { "SPI_SR_MEM_SED_COUNT", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_CONFIG_PS_CU_EN[] = { + { "ENABLE", 0, 0, &umr_bitfield_default }, + { "PKR0_CU_EN", 1, 15, &umr_bitfield_default }, + { "PKR1_CU_EN", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_WF_LIFETIME_CNTL[] = { + { "SAMPLE_PERIOD", 0, 3, &umr_bitfield_default }, + { "EN", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_WF_LIFETIME_LIMIT_0[] = { + { "MAX_CNT", 0, 30, &umr_bitfield_default }, + { "EN_WARN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_WF_LIFETIME_LIMIT_1[] = { + { "MAX_CNT", 0, 30, &umr_bitfield_default }, + { "EN_WARN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_WF_LIFETIME_LIMIT_2[] = { + { "MAX_CNT", 0, 30, &umr_bitfield_default }, + { "EN_WARN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_WF_LIFETIME_LIMIT_3[] = { + { "MAX_CNT", 0, 30, &umr_bitfield_default }, + { "EN_WARN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_WF_LIFETIME_LIMIT_4[] = { + { "MAX_CNT", 0, 30, &umr_bitfield_default }, + { "EN_WARN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_WF_LIFETIME_LIMIT_5[] = { + { "MAX_CNT", 0, 30, &umr_bitfield_default }, + { "EN_WARN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_WF_LIFETIME_LIMIT_6[] = { + { "MAX_CNT", 0, 30, &umr_bitfield_default }, + { "EN_WARN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_WF_LIFETIME_LIMIT_7[] = { + { "MAX_CNT", 0, 30, &umr_bitfield_default }, + { "EN_WARN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_WF_LIFETIME_LIMIT_8[] = { + { "MAX_CNT", 0, 30, &umr_bitfield_default }, + { "EN_WARN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_WF_LIFETIME_LIMIT_9[] = { + { "MAX_CNT", 0, 30, &umr_bitfield_default }, + { "EN_WARN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_0[] = { + { "MAX_CNT", 0, 30, &umr_bitfield_default }, + { "INT_SENT", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_1[] = { + { "MAX_CNT", 0, 30, &umr_bitfield_default }, + { "INT_SENT", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_2[] = { + { "MAX_CNT", 0, 30, &umr_bitfield_default }, + { "INT_SENT", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_3[] = { + { "MAX_CNT", 0, 30, &umr_bitfield_default }, + { "INT_SENT", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_4[] = { + { "MAX_CNT", 0, 30, &umr_bitfield_default }, + { "INT_SENT", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_5[] = { + { "MAX_CNT", 0, 30, &umr_bitfield_default }, + { "INT_SENT", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_6[] = { + { "MAX_CNT", 0, 30, &umr_bitfield_default }, + { "INT_SENT", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_7[] = { + { "MAX_CNT", 0, 30, &umr_bitfield_default }, + { "INT_SENT", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_8[] = { + { "MAX_CNT", 0, 30, &umr_bitfield_default }, + { "INT_SENT", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_9[] = { + { "MAX_CNT", 0, 30, &umr_bitfield_default }, + { "INT_SENT", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_10[] = { + { "MAX_CNT", 0, 30, &umr_bitfield_default }, + { "INT_SENT", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_11[] = { + { "MAX_CNT", 0, 30, &umr_bitfield_default }, + { "INT_SENT", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_12[] = { + { "MAX_CNT", 0, 30, &umr_bitfield_default }, + { "INT_SENT", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_13[] = { + { "MAX_CNT", 0, 30, &umr_bitfield_default }, + { "INT_SENT", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_14[] = { + { "MAX_CNT", 0, 30, &umr_bitfield_default }, + { "INT_SENT", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_15[] = { + { "MAX_CNT", 0, 30, &umr_bitfield_default }, + { "INT_SENT", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_16[] = { + { "MAX_CNT", 0, 30, &umr_bitfield_default }, + { "INT_SENT", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_17[] = { + { "MAX_CNT", 0, 30, &umr_bitfield_default }, + { "INT_SENT", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_18[] = { + { "MAX_CNT", 0, 30, &umr_bitfield_default }, + { "INT_SENT", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_19[] = { + { "MAX_CNT", 0, 30, &umr_bitfield_default }, + { "INT_SENT", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_20[] = { + { "MAX_CNT", 0, 30, &umr_bitfield_default }, + { "INT_SENT", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_LB_CTR_CTRL[] = { + { "LOAD", 0, 0, &umr_bitfield_default }, + { "WAVES_SELECT", 1, 2, &umr_bitfield_default }, + { "CLEAR_ON_READ", 3, 3, &umr_bitfield_default }, + { "RESET_COUNTS", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_LB_CU_MASK[] = { + { "CU_MASK", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_LB_DATA_REG[] = { + { "CNT_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_PG_ENABLE_STATIC_CU_MASK[] = { + { "CU_MASK", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_GDS_CREDITS[] = { + { "DS_DATA_CREDITS", 0, 7, &umr_bitfield_default }, + { "DS_CMD_CREDITS", 8, 15, &umr_bitfield_default }, + { "UNUSED", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SX_EXPORT_BUFFER_SIZES[] = { + { "COLOR_BUFFER_SIZE", 0, 15, &umr_bitfield_default }, + { "POSITION_BUFFER_SIZE", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SX_SCOREBOARD_BUFFER_SIZES[] = { + { "COLOR_SCOREBOARD_SIZE", 0, 15, &umr_bitfield_default }, + { "POSITION_SCOREBOARD_SIZE", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_CSQ_WF_ACTIVE_STATUS[] = { + { "ACTIVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_CSQ_WF_ACTIVE_COUNT_0[] = { + { "COUNT", 0, 10, &umr_bitfield_default }, + { "EVENTS", 16, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_CSQ_WF_ACTIVE_COUNT_1[] = { + { "COUNT", 0, 10, &umr_bitfield_default }, + { "EVENTS", 16, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_CSQ_WF_ACTIVE_COUNT_2[] = { + { "COUNT", 0, 10, &umr_bitfield_default }, + { "EVENTS", 16, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_CSQ_WF_ACTIVE_COUNT_3[] = { + { "COUNT", 0, 10, &umr_bitfield_default }, + { "EVENTS", 16, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_CSQ_WF_ACTIVE_COUNT_4[] = { + { "COUNT", 0, 10, &umr_bitfield_default }, + { "EVENTS", 16, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_CSQ_WF_ACTIVE_COUNT_5[] = { + { "COUNT", 0, 10, &umr_bitfield_default }, + { "EVENTS", 16, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_CSQ_WF_ACTIVE_COUNT_6[] = { + { "COUNT", 0, 10, &umr_bitfield_default }, + { "EVENTS", 16, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_CSQ_WF_ACTIVE_COUNT_7[] = { + { "COUNT", 0, 10, &umr_bitfield_default }, + { "EVENTS", 16, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_LB_DATA_WAVES[] = { + { "COUNT0", 0, 15, &umr_bitfield_default }, + { "COUNT1", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_LB_DATA_PERCU_WAVE_HSGS[] = { + { "CU_USED_HS", 0, 15, &umr_bitfield_default }, + { "CU_USED_GS", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_LB_DATA_PERCU_WAVE_VSPS[] = { + { "CU_USED_VS", 0, 15, &umr_bitfield_default }, + { "CU_USED_PS", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_LB_DATA_PERCU_WAVE_CS[] = { + { "ACTIVE", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_P0_TRAP_SCREEN_PSBA_LO[] = { + { "MEM_BASE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_P0_TRAP_SCREEN_PSBA_HI[] = { + { "MEM_BASE", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_P0_TRAP_SCREEN_PSMA_LO[] = { + { "MEM_BASE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_P0_TRAP_SCREEN_PSMA_HI[] = { + { "MEM_BASE", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_P0_TRAP_SCREEN_GPR_MIN[] = { + { "VGPR_MIN", 0, 5, &umr_bitfield_default }, + { "SGPR_MIN", 6, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_P1_TRAP_SCREEN_PSBA_LO[] = { + { "MEM_BASE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_P1_TRAP_SCREEN_PSBA_HI[] = { + { "MEM_BASE", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_P1_TRAP_SCREEN_PSMA_LO[] = { + { "MEM_BASE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_P1_TRAP_SCREEN_PSMA_HI[] = { + { "MEM_BASE", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_P1_TRAP_SCREEN_GPR_MIN[] = { + { "VGPR_MIN", 0, 5, &umr_bitfield_default }, + { "SGPR_MIN", 6, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTD_CNTL[] = { + { "SYNC_PHASE_SH", 0, 1, &umr_bitfield_default }, + { "SYNC_PHASE_VC_SMX", 4, 5, &umr_bitfield_default }, + { "PAD_STALL_EN", 8, 8, &umr_bitfield_default }, + { "EXTEND_LDS_STALL", 9, 10, &umr_bitfield_default }, + { "LDS_STALL_PHASE_ADJUST", 11, 12, &umr_bitfield_default }, + { "PRECISION_COMPATIBILITY", 15, 15, &umr_bitfield_default }, + { "GATHER4_FLOAT_MODE", 16, 16, &umr_bitfield_default }, + { "LD_FLOAT_MODE", 18, 18, &umr_bitfield_default }, + { "GATHER4_DX9_MODE", 19, 19, &umr_bitfield_default }, + { "DISABLE_POWER_THROTTLE", 20, 20, &umr_bitfield_default }, + { "ENABLE_ROUND_TO_ZERO", 21, 21, &umr_bitfield_default }, + { "DISABLE_2BIT_SIGNED_FORMAT", 23, 23, &umr_bitfield_default }, + { "DISABLE_MM_QNAN_COMPARE_RESULT", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTD_STATUS[] = { + { "BUSY", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTD_DSM_CNTL[] = { + { "TD_SS_FIFO_LO_DSM_IRRITATOR_DATA", 0, 1, &umr_bitfield_default }, + { "TD_SS_FIFO_LO_ENABLE_SINGLE_WRITE", 2, 2, &umr_bitfield_default }, + { "TD_SS_FIFO_HI_DSM_IRRITATOR_DATA", 3, 4, &umr_bitfield_default }, + { "TD_SS_FIFO_HI_ENABLE_SINGLE_WRITE", 5, 5, &umr_bitfield_default }, + { "TD_CS_FIFO_DSM_IRRITATOR_DATA", 6, 7, &umr_bitfield_default }, + { "TD_CS_FIFO_ENABLE_SINGLE_WRITE", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTD_DSM_CNTL2[] = { + { "TD_SS_FIFO_LO_ENABLE_ERROR_INJECT", 0, 1, &umr_bitfield_default }, + { "TD_SS_FIFO_LO_SELECT_INJECT_DELAY", 2, 2, &umr_bitfield_default }, + { "TD_SS_FIFO_HI_ENABLE_ERROR_INJECT", 3, 4, &umr_bitfield_default }, + { "TD_SS_FIFO_HI_SELECT_INJECT_DELAY", 5, 5, &umr_bitfield_default }, + { "TD_CS_FIFO_ENABLE_ERROR_INJECT", 6, 7, &umr_bitfield_default }, + { "TD_CS_FIFO_SELECT_INJECT_DELAY", 8, 8, &umr_bitfield_default }, + { "TD_INJECT_DELAY", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTD_SCRATCH[] = { + { "SCRATCH", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTA_CNTL[] = { + { "FX_XNACK_CREDIT", 0, 6, &umr_bitfield_default }, + { "SQ_XNACK_CREDIT", 9, 12, &umr_bitfield_default }, + { "TC_DATA_CREDIT", 13, 15, &umr_bitfield_default }, + { "ALIGNER_CREDIT", 16, 20, &umr_bitfield_default }, + { "TD_FIFO_CREDIT", 22, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTA_CNTL_AUX[] = { + { "SCOAL_DSWIZZLE_N", 0, 0, &umr_bitfield_default }, + { "RESERVED", 1, 3, &umr_bitfield_default }, + { "TFAULT_EN_OVERRIDE", 5, 5, &umr_bitfield_default }, + { "GATHERH_DST_SEL", 6, 6, &umr_bitfield_default }, + { "DISABLE_GATHER4_BC_SWIZZLE", 7, 7, &umr_bitfield_default }, + { "NONIMG_ANISO_BYPASS", 9, 9, &umr_bitfield_default }, + { "ANISO_HALF_THRESH", 10, 11, &umr_bitfield_default }, + { "ANISO_ERROR_FP_VBIAS", 12, 12, &umr_bitfield_default }, + { "ANISO_STEP_ORDER", 13, 13, &umr_bitfield_default }, + { "ANISO_STEP", 14, 14, &umr_bitfield_default }, + { "MINMAG_UNNORM", 15, 15, &umr_bitfield_default }, + { "ANISO_WEIGHT_MODE", 16, 16, &umr_bitfield_default }, + { "ANISO_RATIO_LUT", 17, 17, &umr_bitfield_default }, + { "ANISO_TAP", 18, 18, &umr_bitfield_default }, + { "ANISO_MIP_ADJ_MODE", 19, 19, &umr_bitfield_default }, + { "DETERMINISM_RESERVED_DISABLE", 20, 20, &umr_bitfield_default }, + { "DETERMINISM_OPCODE_STRICT_DISABLE", 21, 21, &umr_bitfield_default }, + { "DETERMINISM_MISC_DISABLE", 22, 22, &umr_bitfield_default }, + { "DETERMINISM_SAMPLE_C_DFMT_DISABLE", 23, 23, &umr_bitfield_default }, + { "DETERMINISM_SAMPLER_MSAA_DISABLE", 24, 24, &umr_bitfield_default }, + { "DETERMINISM_WRITEOP_READFMT_DISABLE", 25, 25, &umr_bitfield_default }, + { "DETERMINISM_DFMT_NFMT_DISABLE", 26, 26, &umr_bitfield_default }, + { "DISABLE_DWORD_X2_COALESCE", 27, 27, &umr_bitfield_default }, + { "CUBEMAP_SLICE_CLAMP", 28, 28, &umr_bitfield_default }, + { "TRUNC_SMALL_NEG", 29, 29, &umr_bitfield_default }, + { "ARRAY_ROUND_MODE", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTA_RESERVED_010C[] = { + { "Unused", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTA_GRAD_ADJ[] = { + { "GRAD_ADJ_0", 0, 7, &umr_bitfield_default }, + { "GRAD_ADJ_1", 8, 15, &umr_bitfield_default }, + { "GRAD_ADJ_2", 16, 23, &umr_bitfield_default }, + { "GRAD_ADJ_3", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTA_STATUS[] = { + { "FG_PFIFO_EMPTYB", 12, 12, &umr_bitfield_default }, + { "FG_LFIFO_EMPTYB", 13, 13, &umr_bitfield_default }, + { "FG_SFIFO_EMPTYB", 14, 14, &umr_bitfield_default }, + { "FL_PFIFO_EMPTYB", 16, 16, &umr_bitfield_default }, + { "FL_LFIFO_EMPTYB", 17, 17, &umr_bitfield_default }, + { "FL_SFIFO_EMPTYB", 18, 18, &umr_bitfield_default }, + { "FA_PFIFO_EMPTYB", 20, 20, &umr_bitfield_default }, + { "FA_LFIFO_EMPTYB", 21, 21, &umr_bitfield_default }, + { "FA_SFIFO_EMPTYB", 22, 22, &umr_bitfield_default }, + { "IN_BUSY", 24, 24, &umr_bitfield_default }, + { "FG_BUSY", 25, 25, &umr_bitfield_default }, + { "LA_BUSY", 26, 26, &umr_bitfield_default }, + { "FL_BUSY", 27, 27, &umr_bitfield_default }, + { "TA_BUSY", 28, 28, &umr_bitfield_default }, + { "FA_BUSY", 29, 29, &umr_bitfield_default }, + { "AL_BUSY", 30, 30, &umr_bitfield_default }, + { "BUSY", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTA_SCRATCH[] = { + { "SCRATCH", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_CONFIG[] = { + { "SH0_GPR_PHASE_SEL", 1, 2, &umr_bitfield_default }, + { "SH1_GPR_PHASE_SEL", 3, 4, &umr_bitfield_default }, + { "SH2_GPR_PHASE_SEL", 5, 6, &umr_bitfield_default }, + { "SH3_GPR_PHASE_SEL", 7, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_CNTL_STATUS[] = { + { "GDS_BUSY", 0, 0, &umr_bitfield_default }, + { "GRBM_WBUF_BUSY", 1, 1, &umr_bitfield_default }, + { "ORD_APP_BUSY", 2, 2, &umr_bitfield_default }, + { "DS_BANK_CONFLICT", 3, 3, &umr_bitfield_default }, + { "DS_ADDR_CONFLICT", 4, 4, &umr_bitfield_default }, + { "DS_WR_CLAMP", 5, 5, &umr_bitfield_default }, + { "DS_RD_CLAMP", 6, 6, &umr_bitfield_default }, + { "GRBM_RBUF_BUSY", 7, 7, &umr_bitfield_default }, + { "DS_BUSY", 8, 8, &umr_bitfield_default }, + { "GWS_BUSY", 9, 9, &umr_bitfield_default }, + { "ORD_FIFO_BUSY", 10, 10, &umr_bitfield_default }, + { "CREDIT_BUSY0", 11, 11, &umr_bitfield_default }, + { "CREDIT_BUSY1", 12, 12, &umr_bitfield_default }, + { "CREDIT_BUSY2", 13, 13, &umr_bitfield_default }, + { "CREDIT_BUSY3", 14, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_ENHANCE2[] = { + { "MISC", 0, 15, &umr_bitfield_default }, + { "UNUSED", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_PROTECTION_FAULT[] = { + { "WRITE_DIS", 0, 0, &umr_bitfield_default }, + { "FAULT_DETECTED", 1, 1, &umr_bitfield_default }, + { "GRBM", 2, 2, &umr_bitfield_default }, + { "SH_ID", 3, 5, &umr_bitfield_default }, + { "CU_ID", 6, 9, &umr_bitfield_default }, + { "SIMD_ID", 10, 11, &umr_bitfield_default }, + { "WAVE_ID", 12, 15, &umr_bitfield_default }, + { "ADDRESS", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_VM_PROTECTION_FAULT[] = { + { "WRITE_DIS", 0, 0, &umr_bitfield_default }, + { "FAULT_DETECTED", 1, 1, &umr_bitfield_default }, + { "GWS", 2, 2, &umr_bitfield_default }, + { "OA", 3, 3, &umr_bitfield_default }, + { "GRBM", 4, 4, &umr_bitfield_default }, + { "TMZ", 5, 5, &umr_bitfield_default }, + { "VMID", 8, 11, &umr_bitfield_default }, + { "ADDRESS", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_EDC_CNT[] = { + { "GDS_MEM_DED", 0, 1, &umr_bitfield_default }, + { "GDS_INPUT_QUEUE_SED", 2, 3, &umr_bitfield_default }, + { "GDS_MEM_SEC", 4, 5, &umr_bitfield_default }, + { "UNUSED", 6, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_EDC_GRBM_CNT[] = { + { "DED", 0, 1, &umr_bitfield_default }, + { "SEC", 2, 3, &umr_bitfield_default }, + { "UNUSED", 4, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_EDC_OA_DED[] = { + { "ME0_GFXHP3D_PIX_DED", 0, 0, &umr_bitfield_default }, + { "ME0_GFXHP3D_VTX_DED", 1, 1, &umr_bitfield_default }, + { "ME0_CS_DED", 2, 2, &umr_bitfield_default }, + { "ME0_GFXHP3D_GS_DED", 3, 3, &umr_bitfield_default }, + { "ME1_PIPE0_DED", 4, 4, &umr_bitfield_default }, + { "ME1_PIPE1_DED", 5, 5, &umr_bitfield_default }, + { "ME1_PIPE2_DED", 6, 6, &umr_bitfield_default }, + { "ME1_PIPE3_DED", 7, 7, &umr_bitfield_default }, + { "ME2_PIPE0_DED", 8, 8, &umr_bitfield_default }, + { "ME2_PIPE1_DED", 9, 9, &umr_bitfield_default }, + { "ME2_PIPE2_DED", 10, 10, &umr_bitfield_default }, + { "ME2_PIPE3_DED", 11, 11, &umr_bitfield_default }, + { "UNUSED1", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_DSM_CNTL[] = { + { "SEL_DSM_GDS_MEM_IRRITATOR_DATA_0", 0, 0, &umr_bitfield_default }, + { "SEL_DSM_GDS_MEM_IRRITATOR_DATA_1", 1, 1, &umr_bitfield_default }, + { "GDS_MEM_ENABLE_SINGLE_WRITE", 2, 2, &umr_bitfield_default }, + { "SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0", 3, 3, &umr_bitfield_default }, + { "SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1", 4, 4, &umr_bitfield_default }, + { "GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE", 5, 5, &umr_bitfield_default }, + { "SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0", 6, 6, &umr_bitfield_default }, + { "SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1", 7, 7, &umr_bitfield_default }, + { "GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE", 8, 8, &umr_bitfield_default }, + { "SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0", 9, 9, &umr_bitfield_default }, + { "SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1", 10, 10, &umr_bitfield_default }, + { "GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE", 11, 11, &umr_bitfield_default }, + { "SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0", 12, 12, &umr_bitfield_default }, + { "SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1", 13, 13, &umr_bitfield_default }, + { "GDS_PIPE_MEM_ENABLE_SINGLE_WRITE", 14, 14, &umr_bitfield_default }, + { "UNUSED", 15, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_EDC_OA_PHY_CNT[] = { + { "ME0_CS_PIPE_MEM_SEC", 0, 1, &umr_bitfield_default }, + { "ME0_CS_PIPE_MEM_DED", 2, 3, &umr_bitfield_default }, + { "PHY_CMD_RAM_MEM_SEC", 4, 5, &umr_bitfield_default }, + { "PHY_CMD_RAM_MEM_DED", 6, 7, &umr_bitfield_default }, + { "PHY_DATA_RAM_MEM_SED", 8, 9, &umr_bitfield_default }, + { "UNUSED1", 10, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_EDC_OA_PIPE_CNT[] = { + { "ME1_PIPE0_PIPE_MEM_SEC", 0, 1, &umr_bitfield_default }, + { "ME1_PIPE0_PIPE_MEM_DED", 2, 3, &umr_bitfield_default }, + { "ME1_PIPE1_PIPE_MEM_SEC", 4, 5, &umr_bitfield_default }, + { "ME1_PIPE1_PIPE_MEM_DED", 6, 7, &umr_bitfield_default }, + { "ME1_PIPE2_PIPE_MEM_SEC", 8, 9, &umr_bitfield_default }, + { "ME1_PIPE2_PIPE_MEM_DED", 10, 11, &umr_bitfield_default }, + { "ME1_PIPE3_PIPE_MEM_SEC", 12, 13, &umr_bitfield_default }, + { "ME1_PIPE3_PIPE_MEM_DED", 14, 15, &umr_bitfield_default }, + { "UNUSED", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_DSM_CNTL2[] = { + { "GDS_MEM_ENABLE_ERROR_INJECT", 0, 1, &umr_bitfield_default }, + { "GDS_MEM_SELECT_INJECT_DELAY", 2, 2, &umr_bitfield_default }, + { "GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT", 3, 4, &umr_bitfield_default }, + { "GDS_INPUT_QUEUE_SELECT_INJECT_DELAY", 5, 5, &umr_bitfield_default }, + { "GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT", 6, 7, &umr_bitfield_default }, + { "GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY", 8, 8, &umr_bitfield_default }, + { "GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT", 9, 10, &umr_bitfield_default }, + { "GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY", 11, 11, &umr_bitfield_default }, + { "GDS_PIPE_MEM_ENABLE_ERROR_INJECT", 12, 13, &umr_bitfield_default }, + { "GDS_PIPE_MEM_SELECT_INJECT_DELAY", 14, 14, &umr_bitfield_default }, + { "UNUSED", 15, 25, &umr_bitfield_default }, + { "GDS_INJECT_DELAY", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_WD_GDS_CSB[] = { + { "COUNTER", 0, 12, &umr_bitfield_default }, + { "UNUSED", 13, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_DEBUG[] = { + { "DEBUG_STENCIL_COMPRESS_DISABLE", 0, 0, &umr_bitfield_default }, + { "DEBUG_DEPTH_COMPRESS_DISABLE", 1, 1, &umr_bitfield_default }, + { "FETCH_FULL_Z_TILE", 2, 2, &umr_bitfield_default }, + { "FETCH_FULL_STENCIL_TILE", 3, 3, &umr_bitfield_default }, + { "FORCE_Z_MODE", 4, 5, &umr_bitfield_default }, + { "DEBUG_FORCE_DEPTH_READ", 6, 6, &umr_bitfield_default }, + { "DEBUG_FORCE_STENCIL_READ", 7, 7, &umr_bitfield_default }, + { "DEBUG_FORCE_HIZ_ENABLE", 8, 9, &umr_bitfield_default }, + { "DEBUG_FORCE_HIS_ENABLE0", 10, 11, &umr_bitfield_default }, + { "DEBUG_FORCE_HIS_ENABLE1", 12, 13, &umr_bitfield_default }, + { "DEBUG_FAST_Z_DISABLE", 14, 14, &umr_bitfield_default }, + { "DEBUG_FAST_STENCIL_DISABLE", 15, 15, &umr_bitfield_default }, + { "DEBUG_NOOP_CULL_DISABLE", 16, 16, &umr_bitfield_default }, + { "DISABLE_SUMM_SQUADS", 17, 17, &umr_bitfield_default }, + { "DEPTH_CACHE_FORCE_MISS", 18, 18, &umr_bitfield_default }, + { "DEBUG_FORCE_FULL_Z_RANGE", 19, 20, &umr_bitfield_default }, + { "NEVER_FREE_Z_ONLY", 21, 21, &umr_bitfield_default }, + { "ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS", 22, 22, &umr_bitfield_default }, + { "DISABLE_VPORT_ZPLANE_OPTIMIZATION", 23, 23, &umr_bitfield_default }, + { "DECOMPRESS_AFTER_N_ZPLANES", 24, 27, &umr_bitfield_default }, + { "ONE_FREE_IN_FLIGHT", 28, 28, &umr_bitfield_default }, + { "FORCE_MISS_IF_NOT_INFLIGHT", 29, 29, &umr_bitfield_default }, + { "DISABLE_DEPTH_SURFACE_SYNC", 30, 30, &umr_bitfield_default }, + { "DISABLE_HTILE_SURFACE_SYNC", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_DEBUG2[] = { + { "ALLOW_COMPZ_BYTE_MASKING", 0, 0, &umr_bitfield_default }, + { "DISABLE_TC_ZRANGE_L0_CACHE", 1, 1, &umr_bitfield_default }, + { "DISABLE_TC_MASK_L0_CACHE", 2, 2, &umr_bitfield_default }, + { "DTR_ROUND_ROBIN_ARB", 3, 3, &umr_bitfield_default }, + { "DTR_PREZ_STALLS_FOR_ETF_ROOM", 4, 4, &umr_bitfield_default }, + { "DISABLE_PREZL_FIFO_STALL", 5, 5, &umr_bitfield_default }, + { "DISABLE_PREZL_FIFO_STALL_REZ", 6, 6, &umr_bitfield_default }, + { "ENABLE_VIEWPORT_STALL_ON_ALL", 7, 7, &umr_bitfield_default }, + { "OPTIMIZE_HIZ_MATCHES_FB_DISABLE", 8, 8, &umr_bitfield_default }, + { "CLK_OFF_DELAY", 9, 13, &umr_bitfield_default }, + { "DISABLE_TILE_COVERED_FOR_PS_ITER", 14, 14, &umr_bitfield_default }, + { "ENABLE_SUBTILE_GROUPING", 15, 15, &umr_bitfield_default }, + { "RESERVED", 16, 16, &umr_bitfield_default }, + { "DISABLE_NULL_EOT_FORWARDING", 17, 17, &umr_bitfield_default }, + { "DISABLE_DTT_DATA_FORWARDING", 18, 18, &umr_bitfield_default }, + { "DISABLE_QUAD_COHERENCY_STALL", 19, 19, &umr_bitfield_default }, + { "ENABLE_PREZ_OF_REZ_SUMM", 28, 28, &umr_bitfield_default }, + { "DISABLE_PREZL_VIEWPORT_STALL", 29, 29, &umr_bitfield_default }, + { "DISABLE_SINGLE_STENCIL_QUAD_SUMM", 30, 30, &umr_bitfield_default }, + { "DISABLE_WRITE_STALL_ON_RDWR_CONFLICT", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_DEBUG3[] = { + { "DISABLE_CLEAR_ZRANGE_CORRECTION", 0, 0, &umr_bitfield_default }, + { "ROUND_ZRANGE_CORRECTION", 1, 1, &umr_bitfield_default }, + { "FORCE_DB_IS_GOOD", 2, 2, &umr_bitfield_default }, + { "DISABLE_TL_SSO_NULL_SUPPRESSION", 3, 3, &umr_bitfield_default }, + { "DISABLE_HIZ_ON_VPORT_CLAMP", 4, 4, &umr_bitfield_default }, + { "EQAA_INTERPOLATE_COMP_Z", 5, 5, &umr_bitfield_default }, + { "EQAA_INTERPOLATE_SRC_Z", 6, 6, &umr_bitfield_default }, + { "DISABLE_TCP_CAM_BYPASS", 7, 7, &umr_bitfield_default }, + { "DISABLE_ZCMP_DIRTY_SUPPRESSION", 8, 8, &umr_bitfield_default }, + { "DISABLE_REDUNDANT_PLANE_FLUSHES_OPT", 9, 9, &umr_bitfield_default }, + { "DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP", 10, 10, &umr_bitfield_default }, + { "ENABLE_INCOHERENT_EQAA_READS", 11, 11, &umr_bitfield_default }, + { "DISABLE_OP_Z_DATA_FORWARDING", 12, 12, &umr_bitfield_default }, + { "DISABLE_OP_DF_BYPASS", 13, 13, &umr_bitfield_default }, + { "DISABLE_OP_DF_WRITE_COMBINE", 14, 14, &umr_bitfield_default }, + { "DISABLE_OP_DF_DIRECT_FEEDBACK", 15, 15, &umr_bitfield_default }, + { "ALLOW_RF2P_RW_COLLISION", 16, 16, &umr_bitfield_default }, + { "SLOW_PREZ_TO_A2M_OMASK_RATE", 17, 17, &umr_bitfield_default }, + { "DISABLE_OP_S_DATA_FORWARDING", 18, 18, &umr_bitfield_default }, + { "DISABLE_TC_UPDATE_WRITE_COMBINE", 19, 19, &umr_bitfield_default }, + { "DISABLE_HZ_TC_WRITE_COMBINE", 20, 20, &umr_bitfield_default }, + { "ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT", 21, 21, &umr_bitfield_default }, + { "ENABLE_TC_MA_ROUND_ROBIN_ARB", 22, 22, &umr_bitfield_default }, + { "DISABLE_RAM_READ_SUPPRESION_ON_FWD", 23, 23, &umr_bitfield_default }, + { "DISABLE_EQAA_A2M_PERF_OPT", 24, 24, &umr_bitfield_default }, + { "DISABLE_DI_DT_STALL", 25, 25, &umr_bitfield_default }, + { "ENABLE_DB_PROCESS_RESET", 26, 26, &umr_bitfield_default }, + { "DISABLE_OVERRASTERIZATION_FIX", 27, 27, &umr_bitfield_default }, + { "DONT_INSERT_CONTEXT_SUSPEND", 28, 28, &umr_bitfield_default }, + { "DONT_DELETE_CONTEXT_SUSPEND", 29, 29, &umr_bitfield_default }, + { "DISABLE_4XAA_2P_DELAYED_WRITE", 30, 30, &umr_bitfield_default }, + { "DISABLE_4XAA_2P_INTERLEAVED_PMASK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_DEBUG4[] = { + { "DISABLE_QC_Z_MASK_SUMMATION", 0, 0, &umr_bitfield_default }, + { "DISABLE_QC_STENCIL_MASK_SUMMATION", 1, 1, &umr_bitfield_default }, + { "DISABLE_RESUMM_TO_SINGLE_STENCIL", 2, 2, &umr_bitfield_default }, + { "DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL", 3, 3, &umr_bitfield_default }, + { "DISABLE_4XAA_2P_ZD_HOLDOFF", 4, 4, &umr_bitfield_default }, + { "ENABLE_A2M_DQUAD_OPTIMIZATION", 5, 5, &umr_bitfield_default }, + { "ENABLE_DBCB_SLOW_FORMAT_COLLAPSE", 6, 6, &umr_bitfield_default }, + { "ALWAYS_ON_RMI_CLK_EN", 7, 7, &umr_bitfield_default }, + { "DFSM_CONVERT_PASSTHROUGH_TO_BYPASS", 8, 8, &umr_bitfield_default }, + { "DISABLE_UNMAPPED_Z_INDICATOR", 9, 9, &umr_bitfield_default }, + { "DISABLE_UNMAPPED_S_INDICATOR", 10, 10, &umr_bitfield_default }, + { "DISABLE_UNMAPPED_H_INDICATOR", 11, 11, &umr_bitfield_default }, + { "DISABLE_SEPARATE_DFSM_CLK", 12, 12, &umr_bitfield_default }, + { "DISABLE_DTT_FAST_HTILENACK_LOOKUP", 13, 13, &umr_bitfield_default }, + { "DISABLE_RESCHECK_MEMCOHER_OPTIMIZATION", 14, 14, &umr_bitfield_default }, + { "DISABLE_TS_WRITE_L0", 15, 15, &umr_bitfield_default }, + { "DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE", 16, 16, &umr_bitfield_default }, + { "DISABLE_HIZ_Q1_TS_COLLISION_DETECT", 17, 17, &umr_bitfield_default }, + { "DISABLE_HIZ_Q2_TS_COLLISION_DETECT", 18, 18, &umr_bitfield_default }, + { "DB_EXTRA_DEBUG4", 19, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_CREDIT_LIMIT[] = { + { "DB_SC_TILE_CREDITS", 0, 4, &umr_bitfield_default }, + { "DB_SC_QUAD_CREDITS", 5, 9, &umr_bitfield_default }, + { "DB_CB_LQUAD_CREDITS", 10, 12, &umr_bitfield_default }, + { "DB_CB_TILE_CREDITS", 24, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_WATERMARKS[] = { + { "DEPTH_FREE", 0, 4, &umr_bitfield_default }, + { "DEPTH_FLUSH", 5, 10, &umr_bitfield_default }, + { "FORCE_SUMMARIZE", 11, 14, &umr_bitfield_default }, + { "DEPTH_PENDING_FREE", 15, 19, &umr_bitfield_default }, + { "DEPTH_CACHELINE_FREE", 20, 27, &umr_bitfield_default }, + { "AUTO_FLUSH_HTILE", 30, 30, &umr_bitfield_default }, + { "AUTO_FLUSH_QUAD", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_SUBTILE_CONTROL[] = { + { "MSAA1_X", 0, 1, &umr_bitfield_default }, + { "MSAA1_Y", 2, 3, &umr_bitfield_default }, + { "MSAA2_X", 4, 5, &umr_bitfield_default }, + { "MSAA2_Y", 6, 7, &umr_bitfield_default }, + { "MSAA4_X", 8, 9, &umr_bitfield_default }, + { "MSAA4_Y", 10, 11, &umr_bitfield_default }, + { "MSAA8_X", 12, 13, &umr_bitfield_default }, + { "MSAA8_Y", 14, 15, &umr_bitfield_default }, + { "MSAA16_X", 16, 17, &umr_bitfield_default }, + { "MSAA16_Y", 18, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_FREE_CACHELINES[] = { + { "FREE_DTILE_DEPTH", 0, 6, &umr_bitfield_default }, + { "FREE_PLANE_DEPTH", 7, 13, &umr_bitfield_default }, + { "FREE_Z_DEPTH", 14, 19, &umr_bitfield_default }, + { "FREE_HTILE_DEPTH", 20, 23, &umr_bitfield_default }, + { "QUAD_READ_REQS", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_FIFO_DEPTH1[] = { + { "DB_RMI_RDREQ_CREDITS", 0, 4, &umr_bitfield_default }, + { "DB_RMI_WRREQ_CREDITS", 5, 9, &umr_bitfield_default }, + { "MCC_DEPTH", 10, 15, &umr_bitfield_default }, + { "QC_DEPTH", 16, 20, &umr_bitfield_default }, + { "LTILE_PROBE_FIFO_DEPTH", 21, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_FIFO_DEPTH2[] = { + { "EQUAD_FIFO_DEPTH", 0, 7, &umr_bitfield_default }, + { "ETILE_OP_FIFO_DEPTH", 8, 14, &umr_bitfield_default }, + { "LQUAD_FIFO_DEPTH", 15, 24, &umr_bitfield_default }, + { "LTILE_OP_FIFO_DEPTH", 25, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_EXCEPTION_CONTROL[] = { + { "EARLY_Z_PANIC_DISABLE", 0, 0, &umr_bitfield_default }, + { "LATE_Z_PANIC_DISABLE", 1, 1, &umr_bitfield_default }, + { "RE_Z_PANIC_DISABLE", 2, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_RING_CONTROL[] = { + { "COUNTER_CONTROL", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_MEM_ARB_WATERMARKS[] = { + { "CLIENT0_WATERMARK", 0, 2, &umr_bitfield_default }, + { "CLIENT1_WATERMARK", 8, 10, &umr_bitfield_default }, + { "CLIENT2_WATERMARK", 16, 18, &umr_bitfield_default }, + { "CLIENT3_WATERMARK", 24, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_RMI_CACHE_POLICY[] = { + { "Z_RD", 0, 0, &umr_bitfield_default }, + { "S_RD", 1, 1, &umr_bitfield_default }, + { "HTILE_RD", 2, 2, &umr_bitfield_default }, + { "Z_WR", 8, 8, &umr_bitfield_default }, + { "S_WR", 9, 9, &umr_bitfield_default }, + { "HTILE_WR", 10, 10, &umr_bitfield_default }, + { "ZPCPSD_WR", 11, 11, &umr_bitfield_default }, + { "CC_RD", 16, 16, &umr_bitfield_default }, + { "FMASK_RD", 17, 17, &umr_bitfield_default }, + { "CMASK_RD", 18, 18, &umr_bitfield_default }, + { "DCC_RD", 19, 19, &umr_bitfield_default }, + { "CC_WR", 24, 24, &umr_bitfield_default }, + { "FMASK_WR", 25, 25, &umr_bitfield_default }, + { "CMASK_WR", 26, 26, &umr_bitfield_default }, + { "DCC_WR", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_DFSM_CONFIG[] = { + { "BYPASS_DFSM", 0, 0, &umr_bitfield_default }, + { "DISABLE_PUNCHOUT", 1, 1, &umr_bitfield_default }, + { "DISABLE_POPS", 2, 2, &umr_bitfield_default }, + { "FORCE_FLUSH", 3, 3, &umr_bitfield_default }, + { "MIDDLE_PIPE_MAX_DEPTH", 8, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_DFSM_WATERMARK[] = { + { "DFSM_HIGH_WATERMARK", 0, 15, &umr_bitfield_default }, + { "POPS_HIGH_WATERMARK", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_DFSM_TILES_IN_FLIGHT[] = { + { "HIGH_WATERMARK", 0, 15, &umr_bitfield_default }, + { "HARD_LIMIT", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_DFSM_PRIMS_IN_FLIGHT[] = { + { "HIGH_WATERMARK", 0, 15, &umr_bitfield_default }, + { "HARD_LIMIT", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_DFSM_WATCHDOG[] = { + { "TIMER_TARGET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_DFSM_FLUSH_ENABLE[] = { + { "PRIMARY_EVENTS", 0, 9, &umr_bitfield_default }, + { "AUX_FORCE_PASSTHRU", 24, 27, &umr_bitfield_default }, + { "AUX_EVENTS", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_DFSM_FLUSH_AUX_EVENT[] = { + { "EVENT_A", 0, 7, &umr_bitfield_default }, + { "EVENT_B", 8, 15, &umr_bitfield_default }, + { "EVENT_C", 16, 23, &umr_bitfield_default }, + { "EVENT_D", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCC_RB_REDUNDANCY[] = { + { "FAILED_RB0", 8, 11, &umr_bitfield_default }, + { "EN_REDUNDANCY0", 12, 12, &umr_bitfield_default }, + { "FAILED_RB1", 16, 19, &umr_bitfield_default }, + { "EN_REDUNDANCY1", 20, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCC_RB_BACKEND_DISABLE[] = { + { "BACKEND_DISABLE", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGB_ADDR_CONFIG[] = { + { "NUM_PIPES", 0, 2, &umr_bitfield_default }, + { "PIPE_INTERLEAVE_SIZE", 3, 5, &umr_bitfield_default }, + { "MAX_COMPRESSED_FRAGS", 6, 7, &umr_bitfield_default }, + { "BANK_INTERLEAVE_SIZE", 8, 10, &umr_bitfield_default }, + { "NUM_BANKS", 12, 14, &umr_bitfield_default }, + { "SHADER_ENGINE_TILE_SIZE", 16, 18, &umr_bitfield_default }, + { "NUM_SHADER_ENGINES", 19, 20, &umr_bitfield_default }, + { "NUM_GPUS", 21, 23, &umr_bitfield_default }, + { "MULTI_GPU_TILE_SIZE", 24, 25, &umr_bitfield_default }, + { "NUM_RB_PER_SE", 26, 27, &umr_bitfield_default }, + { "ROW_SIZE", 28, 29, &umr_bitfield_default }, + { "NUM_LOWER_PIPES", 30, 30, &umr_bitfield_default }, + { "SE_ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGB_BACKEND_MAP[] = { + { "BACKEND_MAP", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGB_GPU_ID[] = { + { "GPU_ID", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCC_RB_DAISY_CHAIN[] = { + { "RB_0", 0, 3, &umr_bitfield_default }, + { "RB_1", 4, 7, &umr_bitfield_default }, + { "RB_2", 8, 11, &umr_bitfield_default }, + { "RB_3", 12, 15, &umr_bitfield_default }, + { "RB_4", 16, 19, &umr_bitfield_default }, + { "RB_5", 20, 23, &umr_bitfield_default }, + { "RB_6", 24, 27, &umr_bitfield_default }, + { "RB_7", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGB_ADDR_CONFIG_READ[] = { + { "NUM_PIPES", 0, 2, &umr_bitfield_default }, + { "PIPE_INTERLEAVE_SIZE", 3, 5, &umr_bitfield_default }, + { "MAX_COMPRESSED_FRAGS", 6, 7, &umr_bitfield_default }, + { "BANK_INTERLEAVE_SIZE", 8, 10, &umr_bitfield_default }, + { "NUM_BANKS", 12, 14, &umr_bitfield_default }, + { "SHADER_ENGINE_TILE_SIZE", 16, 18, &umr_bitfield_default }, + { "NUM_SHADER_ENGINES", 19, 20, &umr_bitfield_default }, + { "NUM_GPUS", 21, 23, &umr_bitfield_default }, + { "MULTI_GPU_TILE_SIZE", 24, 25, &umr_bitfield_default }, + { "NUM_RB_PER_SE", 26, 27, &umr_bitfield_default }, + { "ROW_SIZE", 28, 29, &umr_bitfield_default }, + { "NUM_LOWER_PIPES", 30, 30, &umr_bitfield_default }, + { "SE_ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGB_TILE_MODE0[] = { + { "ARRAY_MODE", 2, 5, &umr_bitfield_default }, + { "PIPE_CONFIG", 6, 10, &umr_bitfield_default }, + { "TILE_SPLIT", 11, 13, &umr_bitfield_default }, + { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default }, + { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGB_TILE_MODE1[] = { + { "ARRAY_MODE", 2, 5, &umr_bitfield_default }, + { "PIPE_CONFIG", 6, 10, &umr_bitfield_default }, + { "TILE_SPLIT", 11, 13, &umr_bitfield_default }, + { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default }, + { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGB_TILE_MODE2[] = { + { "ARRAY_MODE", 2, 5, &umr_bitfield_default }, + { "PIPE_CONFIG", 6, 10, &umr_bitfield_default }, + { "TILE_SPLIT", 11, 13, &umr_bitfield_default }, + { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default }, + { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGB_TILE_MODE3[] = { + { "ARRAY_MODE", 2, 5, &umr_bitfield_default }, + { "PIPE_CONFIG", 6, 10, &umr_bitfield_default }, + { "TILE_SPLIT", 11, 13, &umr_bitfield_default }, + { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default }, + { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGB_TILE_MODE4[] = { + { "ARRAY_MODE", 2, 5, &umr_bitfield_default }, + { "PIPE_CONFIG", 6, 10, &umr_bitfield_default }, + { "TILE_SPLIT", 11, 13, &umr_bitfield_default }, + { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default }, + { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGB_TILE_MODE5[] = { + { "ARRAY_MODE", 2, 5, &umr_bitfield_default }, + { "PIPE_CONFIG", 6, 10, &umr_bitfield_default }, + { "TILE_SPLIT", 11, 13, &umr_bitfield_default }, + { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default }, + { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGB_TILE_MODE6[] = { + { "ARRAY_MODE", 2, 5, &umr_bitfield_default }, + { "PIPE_CONFIG", 6, 10, &umr_bitfield_default }, + { "TILE_SPLIT", 11, 13, &umr_bitfield_default }, + { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default }, + { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGB_TILE_MODE7[] = { + { "ARRAY_MODE", 2, 5, &umr_bitfield_default }, + { "PIPE_CONFIG", 6, 10, &umr_bitfield_default }, + { "TILE_SPLIT", 11, 13, &umr_bitfield_default }, + { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default }, + { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGB_TILE_MODE8[] = { + { "ARRAY_MODE", 2, 5, &umr_bitfield_default }, + { "PIPE_CONFIG", 6, 10, &umr_bitfield_default }, + { "TILE_SPLIT", 11, 13, &umr_bitfield_default }, + { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default }, + { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGB_TILE_MODE9[] = { + { "ARRAY_MODE", 2, 5, &umr_bitfield_default }, + { "PIPE_CONFIG", 6, 10, &umr_bitfield_default }, + { "TILE_SPLIT", 11, 13, &umr_bitfield_default }, + { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default }, + { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGB_TILE_MODE10[] = { + { "ARRAY_MODE", 2, 5, &umr_bitfield_default }, + { "PIPE_CONFIG", 6, 10, &umr_bitfield_default }, + { "TILE_SPLIT", 11, 13, &umr_bitfield_default }, + { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default }, + { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGB_TILE_MODE11[] = { + { "ARRAY_MODE", 2, 5, &umr_bitfield_default }, + { "PIPE_CONFIG", 6, 10, &umr_bitfield_default }, + { "TILE_SPLIT", 11, 13, &umr_bitfield_default }, + { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default }, + { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGB_TILE_MODE12[] = { + { "ARRAY_MODE", 2, 5, &umr_bitfield_default }, + { "PIPE_CONFIG", 6, 10, &umr_bitfield_default }, + { "TILE_SPLIT", 11, 13, &umr_bitfield_default }, + { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default }, + { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGB_TILE_MODE13[] = { + { "ARRAY_MODE", 2, 5, &umr_bitfield_default }, + { "PIPE_CONFIG", 6, 10, &umr_bitfield_default }, + { "TILE_SPLIT", 11, 13, &umr_bitfield_default }, + { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default }, + { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGB_TILE_MODE14[] = { + { "ARRAY_MODE", 2, 5, &umr_bitfield_default }, + { "PIPE_CONFIG", 6, 10, &umr_bitfield_default }, + { "TILE_SPLIT", 11, 13, &umr_bitfield_default }, + { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default }, + { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGB_TILE_MODE15[] = { + { "ARRAY_MODE", 2, 5, &umr_bitfield_default }, + { "PIPE_CONFIG", 6, 10, &umr_bitfield_default }, + { "TILE_SPLIT", 11, 13, &umr_bitfield_default }, + { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default }, + { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGB_TILE_MODE16[] = { + { "ARRAY_MODE", 2, 5, &umr_bitfield_default }, + { "PIPE_CONFIG", 6, 10, &umr_bitfield_default }, + { "TILE_SPLIT", 11, 13, &umr_bitfield_default }, + { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default }, + { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGB_TILE_MODE17[] = { + { "ARRAY_MODE", 2, 5, &umr_bitfield_default }, + { "PIPE_CONFIG", 6, 10, &umr_bitfield_default }, + { "TILE_SPLIT", 11, 13, &umr_bitfield_default }, + { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default }, + { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGB_TILE_MODE18[] = { + { "ARRAY_MODE", 2, 5, &umr_bitfield_default }, + { "PIPE_CONFIG", 6, 10, &umr_bitfield_default }, + { "TILE_SPLIT", 11, 13, &umr_bitfield_default }, + { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default }, + { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGB_TILE_MODE19[] = { + { "ARRAY_MODE", 2, 5, &umr_bitfield_default }, + { "PIPE_CONFIG", 6, 10, &umr_bitfield_default }, + { "TILE_SPLIT", 11, 13, &umr_bitfield_default }, + { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default }, + { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGB_TILE_MODE20[] = { + { "ARRAY_MODE", 2, 5, &umr_bitfield_default }, + { "PIPE_CONFIG", 6, 10, &umr_bitfield_default }, + { "TILE_SPLIT", 11, 13, &umr_bitfield_default }, + { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default }, + { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGB_TILE_MODE21[] = { + { "ARRAY_MODE", 2, 5, &umr_bitfield_default }, + { "PIPE_CONFIG", 6, 10, &umr_bitfield_default }, + { "TILE_SPLIT", 11, 13, &umr_bitfield_default }, + { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default }, + { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGB_TILE_MODE22[] = { + { "ARRAY_MODE", 2, 5, &umr_bitfield_default }, + { "PIPE_CONFIG", 6, 10, &umr_bitfield_default }, + { "TILE_SPLIT", 11, 13, &umr_bitfield_default }, + { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default }, + { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGB_TILE_MODE23[] = { + { "ARRAY_MODE", 2, 5, &umr_bitfield_default }, + { "PIPE_CONFIG", 6, 10, &umr_bitfield_default }, + { "TILE_SPLIT", 11, 13, &umr_bitfield_default }, + { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default }, + { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGB_TILE_MODE24[] = { + { "ARRAY_MODE", 2, 5, &umr_bitfield_default }, + { "PIPE_CONFIG", 6, 10, &umr_bitfield_default }, + { "TILE_SPLIT", 11, 13, &umr_bitfield_default }, + { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default }, + { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGB_TILE_MODE25[] = { + { "ARRAY_MODE", 2, 5, &umr_bitfield_default }, + { "PIPE_CONFIG", 6, 10, &umr_bitfield_default }, + { "TILE_SPLIT", 11, 13, &umr_bitfield_default }, + { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default }, + { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGB_TILE_MODE26[] = { + { "ARRAY_MODE", 2, 5, &umr_bitfield_default }, + { "PIPE_CONFIG", 6, 10, &umr_bitfield_default }, + { "TILE_SPLIT", 11, 13, &umr_bitfield_default }, + { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default }, + { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGB_TILE_MODE27[] = { + { "ARRAY_MODE", 2, 5, &umr_bitfield_default }, + { "PIPE_CONFIG", 6, 10, &umr_bitfield_default }, + { "TILE_SPLIT", 11, 13, &umr_bitfield_default }, + { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default }, + { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGB_TILE_MODE28[] = { + { "ARRAY_MODE", 2, 5, &umr_bitfield_default }, + { "PIPE_CONFIG", 6, 10, &umr_bitfield_default }, + { "TILE_SPLIT", 11, 13, &umr_bitfield_default }, + { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default }, + { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGB_TILE_MODE29[] = { + { "ARRAY_MODE", 2, 5, &umr_bitfield_default }, + { "PIPE_CONFIG", 6, 10, &umr_bitfield_default }, + { "TILE_SPLIT", 11, 13, &umr_bitfield_default }, + { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default }, + { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGB_TILE_MODE30[] = { + { "ARRAY_MODE", 2, 5, &umr_bitfield_default }, + { "PIPE_CONFIG", 6, 10, &umr_bitfield_default }, + { "TILE_SPLIT", 11, 13, &umr_bitfield_default }, + { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default }, + { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGB_TILE_MODE31[] = { + { "ARRAY_MODE", 2, 5, &umr_bitfield_default }, + { "PIPE_CONFIG", 6, 10, &umr_bitfield_default }, + { "TILE_SPLIT", 11, 13, &umr_bitfield_default }, + { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default }, + { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGB_MACROTILE_MODE0[] = { + { "BANK_WIDTH", 0, 1, &umr_bitfield_default }, + { "BANK_HEIGHT", 2, 3, &umr_bitfield_default }, + { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default }, + { "NUM_BANKS", 6, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGB_MACROTILE_MODE1[] = { + { "BANK_WIDTH", 0, 1, &umr_bitfield_default }, + { "BANK_HEIGHT", 2, 3, &umr_bitfield_default }, + { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default }, + { "NUM_BANKS", 6, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGB_MACROTILE_MODE2[] = { + { "BANK_WIDTH", 0, 1, &umr_bitfield_default }, + { "BANK_HEIGHT", 2, 3, &umr_bitfield_default }, + { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default }, + { "NUM_BANKS", 6, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGB_MACROTILE_MODE3[] = { + { "BANK_WIDTH", 0, 1, &umr_bitfield_default }, + { "BANK_HEIGHT", 2, 3, &umr_bitfield_default }, + { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default }, + { "NUM_BANKS", 6, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGB_MACROTILE_MODE4[] = { + { "BANK_WIDTH", 0, 1, &umr_bitfield_default }, + { "BANK_HEIGHT", 2, 3, &umr_bitfield_default }, + { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default }, + { "NUM_BANKS", 6, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGB_MACROTILE_MODE5[] = { + { "BANK_WIDTH", 0, 1, &umr_bitfield_default }, + { "BANK_HEIGHT", 2, 3, &umr_bitfield_default }, + { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default }, + { "NUM_BANKS", 6, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGB_MACROTILE_MODE6[] = { + { "BANK_WIDTH", 0, 1, &umr_bitfield_default }, + { "BANK_HEIGHT", 2, 3, &umr_bitfield_default }, + { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default }, + { "NUM_BANKS", 6, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGB_MACROTILE_MODE7[] = { + { "BANK_WIDTH", 0, 1, &umr_bitfield_default }, + { "BANK_HEIGHT", 2, 3, &umr_bitfield_default }, + { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default }, + { "NUM_BANKS", 6, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGB_MACROTILE_MODE8[] = { + { "BANK_WIDTH", 0, 1, &umr_bitfield_default }, + { "BANK_HEIGHT", 2, 3, &umr_bitfield_default }, + { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default }, + { "NUM_BANKS", 6, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGB_MACROTILE_MODE9[] = { + { "BANK_WIDTH", 0, 1, &umr_bitfield_default }, + { "BANK_HEIGHT", 2, 3, &umr_bitfield_default }, + { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default }, + { "NUM_BANKS", 6, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGB_MACROTILE_MODE10[] = { + { "BANK_WIDTH", 0, 1, &umr_bitfield_default }, + { "BANK_HEIGHT", 2, 3, &umr_bitfield_default }, + { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default }, + { "NUM_BANKS", 6, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGB_MACROTILE_MODE11[] = { + { "BANK_WIDTH", 0, 1, &umr_bitfield_default }, + { "BANK_HEIGHT", 2, 3, &umr_bitfield_default }, + { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default }, + { "NUM_BANKS", 6, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGB_MACROTILE_MODE12[] = { + { "BANK_WIDTH", 0, 1, &umr_bitfield_default }, + { "BANK_HEIGHT", 2, 3, &umr_bitfield_default }, + { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default }, + { "NUM_BANKS", 6, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGB_MACROTILE_MODE13[] = { + { "BANK_WIDTH", 0, 1, &umr_bitfield_default }, + { "BANK_HEIGHT", 2, 3, &umr_bitfield_default }, + { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default }, + { "NUM_BANKS", 6, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGB_MACROTILE_MODE14[] = { + { "BANK_WIDTH", 0, 1, &umr_bitfield_default }, + { "BANK_HEIGHT", 2, 3, &umr_bitfield_default }, + { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default }, + { "NUM_BANKS", 6, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGB_MACROTILE_MODE15[] = { + { "BANK_WIDTH", 0, 1, &umr_bitfield_default }, + { "BANK_HEIGHT", 2, 3, &umr_bitfield_default }, + { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default }, + { "NUM_BANKS", 6, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_HW_CONTROL[] = { + { "CM_CACHE_EVICT_POINT", 0, 3, &umr_bitfield_default }, + { "FC_CACHE_EVICT_POINT", 6, 9, &umr_bitfield_default }, + { "CC_CACHE_EVICT_POINT", 12, 15, &umr_bitfield_default }, + { "ALLOW_MRT_WITH_DUAL_SOURCE", 16, 16, &umr_bitfield_default }, + { "DISABLE_INTNORM_LE11BPC_CLAMPING", 18, 18, &umr_bitfield_default }, + { "FORCE_NEEDS_DST", 19, 19, &umr_bitfield_default }, + { "FORCE_ALWAYS_TOGGLE", 20, 20, &umr_bitfield_default }, + { "DISABLE_BLEND_OPT_RESULT_EQ_DEST", 21, 21, &umr_bitfield_default }, + { "DISABLE_FULL_WRITE_MASK", 22, 22, &umr_bitfield_default }, + { "DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG", 23, 23, &umr_bitfield_default }, + { "DISABLE_BLEND_OPT_DONT_RD_DST", 24, 24, &umr_bitfield_default }, + { "DISABLE_BLEND_OPT_BYPASS", 25, 25, &umr_bitfield_default }, + { "DISABLE_BLEND_OPT_DISCARD_PIXEL", 26, 26, &umr_bitfield_default }, + { "DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED", 27, 27, &umr_bitfield_default }, + { "PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT", 28, 28, &umr_bitfield_default }, + { "PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT", 29, 29, &umr_bitfield_default }, + { "DISABLE_CC_IB_SERIALIZER_STATE_OPT", 30, 30, &umr_bitfield_default }, + { "DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_HW_CONTROL_1[] = { + { "CM_CACHE_NUM_TAGS", 0, 4, &umr_bitfield_default }, + { "FC_CACHE_NUM_TAGS", 5, 10, &umr_bitfield_default }, + { "CC_CACHE_NUM_TAGS", 11, 16, &umr_bitfield_default }, + { "CM_TILE_FIFO_DEPTH", 17, 25, &umr_bitfield_default }, + { "RMI_CREDITS", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_HW_CONTROL_2[] = { + { "CC_EVEN_ODD_FIFO_DEPTH", 0, 7, &umr_bitfield_default }, + { "FC_RDLAT_TILE_FIFO_DEPTH", 8, 14, &umr_bitfield_default }, + { "FC_RDLAT_QUAD_FIFO_DEPTH", 15, 22, &umr_bitfield_default }, + { "DRR_ASSUMED_FIFO_DEPTH_DIV8", 24, 27, &umr_bitfield_default }, + { "CHICKEN_BITS", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_HW_CONTROL_3[] = { + { "DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL", 0, 0, &umr_bitfield_default }, + { "RAM_ADDRESS_CONFLICTS_DISALLOWED", 1, 1, &umr_bitfield_default }, + { "DISABLE_FAST_CLEAR_FETCH_OPT", 2, 2, &umr_bitfield_default }, + { "DISABLE_QUAD_MARKER_DROP_STOP", 3, 3, &umr_bitfield_default }, + { "DISABLE_OVERWRITE_COMBINER_CAM_CLR", 4, 4, &umr_bitfield_default }, + { "DISABLE_CC_CACHE_OVWR_STATUS_ACCUM", 5, 5, &umr_bitfield_default }, + { "DISABLE_CC_CACHE_OVWR_KEY_MOD", 6, 6, &umr_bitfield_default }, + { "DISABLE_CC_CACHE_PANIC_GATING", 7, 7, &umr_bitfield_default }, + { "DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION", 8, 8, &umr_bitfield_default }, + { "SPLIT_ALL_FAST_MODE_TRANSFERS", 9, 9, &umr_bitfield_default }, + { "DISABLE_SHADER_BLEND_OPTS", 10, 10, &umr_bitfield_default }, + { "DISABLE_CMASK_LAST_QUAD_INSERTION", 11, 11, &umr_bitfield_default }, + { "DISABLE_ROP3_FIXES_OF_BUG_511967", 12, 12, &umr_bitfield_default }, + { "DISABLE_ROP3_FIXES_OF_BUG_520657", 13, 13, &umr_bitfield_default }, + { "DISABLE_OC_FIXES_OF_BUG_522542", 14, 14, &umr_bitfield_default }, + { "FORCE_RMI_LAST_HIGH", 15, 15, &umr_bitfield_default }, + { "FORCE_RMI_CLKEN_HIGH", 16, 16, &umr_bitfield_default }, + { "DISABLE_EARLY_WRACKS_CC", 17, 17, &umr_bitfield_default }, + { "DISABLE_EARLY_WRACKS_FC", 18, 18, &umr_bitfield_default }, + { "DISABLE_EARLY_WRACKS_DC", 19, 19, &umr_bitfield_default }, + { "DISABLE_EARLY_WRACKS_CM", 20, 20, &umr_bitfield_default }, + { "DISABLE_NACK_PROCESSING_CC", 21, 21, &umr_bitfield_default }, + { "DISABLE_NACK_PROCESSING_FC", 22, 22, &umr_bitfield_default }, + { "DISABLE_NACK_PROCESSING_DC", 23, 23, &umr_bitfield_default }, + { "DISABLE_NACK_PROCESSING_CM", 24, 24, &umr_bitfield_default }, + { "DISABLE_NACK_COLOR_RD_WR_OPT", 25, 25, &umr_bitfield_default }, + { "DISABLE_BLENDER_CLOCK_GATING", 26, 26, &umr_bitfield_default }, + { "DISABLE_DUALSRC_WITH_OBJPRIMID_FIX", 27, 27, &umr_bitfield_default }, + { "COLOR_CACHE_PREFETCH_NUM_CLS", 28, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_HW_MEM_ARBITER_RD[] = { + { "MODE", 0, 1, &umr_bitfield_default }, + { "IGNORE_URGENT_AGE", 2, 5, &umr_bitfield_default }, + { "BREAK_GROUP_AGE", 6, 9, &umr_bitfield_default }, + { "WEIGHT_CC", 10, 11, &umr_bitfield_default }, + { "WEIGHT_FC", 12, 13, &umr_bitfield_default }, + { "WEIGHT_CM", 14, 15, &umr_bitfield_default }, + { "WEIGHT_DC", 16, 17, &umr_bitfield_default }, + { "WEIGHT_DECAY_REQS", 18, 19, &umr_bitfield_default }, + { "WEIGHT_DECAY_NOREQS", 20, 21, &umr_bitfield_default }, + { "WEIGHT_IGNORE_NUM_TIDS", 22, 22, &umr_bitfield_default }, + { "SCALE_AGE", 23, 25, &umr_bitfield_default }, + { "SCALE_WEIGHT", 26, 28, &umr_bitfield_default }, + { "SEND_LASTS_WITHIN_GROUPS", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_HW_MEM_ARBITER_WR[] = { + { "MODE", 0, 1, &umr_bitfield_default }, + { "IGNORE_URGENT_AGE", 2, 5, &umr_bitfield_default }, + { "BREAK_GROUP_AGE", 6, 9, &umr_bitfield_default }, + { "WEIGHT_CC", 10, 11, &umr_bitfield_default }, + { "WEIGHT_FC", 12, 13, &umr_bitfield_default }, + { "WEIGHT_CM", 14, 15, &umr_bitfield_default }, + { "WEIGHT_DC", 16, 17, &umr_bitfield_default }, + { "WEIGHT_DECAY_REQS", 18, 19, &umr_bitfield_default }, + { "WEIGHT_DECAY_NOREQS", 20, 21, &umr_bitfield_default }, + { "WEIGHT_IGNORE_BYTE_MASK", 22, 22, &umr_bitfield_default }, + { "SCALE_AGE", 23, 25, &umr_bitfield_default }, + { "SCALE_WEIGHT", 26, 28, &umr_bitfield_default }, + { "SEND_LASTS_WITHIN_GROUPS", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_DCC_CONFIG[] = { + { "OVERWRITE_COMBINER_DEPTH", 0, 4, &umr_bitfield_default }, + { "OVERWRITE_COMBINER_DISABLE", 5, 5, &umr_bitfield_default }, + { "OVERWRITE_COMBINER_CC_POP_DISABLE", 6, 6, &umr_bitfield_default }, + { "FC_RDLAT_KEYID_FIFO_DEPTH", 8, 15, &umr_bitfield_default }, + { "READ_RETURN_SKID_FIFO_DEPTH", 16, 22, &umr_bitfield_default }, + { "DCC_CACHE_EVICT_POINT", 24, 27, &umr_bitfield_default }, + { "DCC_CACHE_NUM_TAGS", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGC_USER_RB_REDUNDANCY[] = { + { "FAILED_RB0", 8, 11, &umr_bitfield_default }, + { "EN_REDUNDANCY0", 12, 12, &umr_bitfield_default }, + { "FAILED_RB1", 16, 19, &umr_bitfield_default }, + { "EN_REDUNDANCY1", 20, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGC_USER_RB_BACKEND_DISABLE[] = { + { "BACKEND_DISABLE", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_EDC_CNT[] = { + { "DRAMRD_CMDMEM_SEC_COUNT", 0, 1, &umr_bitfield_default }, + { "DRAMRD_CMDMEM_DED_COUNT", 2, 3, &umr_bitfield_default }, + { "DRAMWR_CMDMEM_SEC_COUNT", 4, 5, &umr_bitfield_default }, + { "DRAMWR_CMDMEM_DED_COUNT", 6, 7, &umr_bitfield_default }, + { "DRAMWR_DATAMEM_SEC_COUNT", 8, 9, &umr_bitfield_default }, + { "DRAMWR_DATAMEM_DED_COUNT", 10, 11, &umr_bitfield_default }, + { "RRET_TAGMEM_SEC_COUNT", 12, 13, &umr_bitfield_default }, + { "RRET_TAGMEM_DED_COUNT", 14, 15, &umr_bitfield_default }, + { "WRET_TAGMEM_SEC_COUNT", 16, 17, &umr_bitfield_default }, + { "WRET_TAGMEM_DED_COUNT", 18, 19, &umr_bitfield_default }, + { "DRAMRD_PAGEMEM_SED_COUNT", 20, 21, &umr_bitfield_default }, + { "DRAMWR_PAGEMEM_SED_COUNT", 22, 23, &umr_bitfield_default }, + { "IORD_CMDMEM_SED_COUNT", 24, 25, &umr_bitfield_default }, + { "IOWR_CMDMEM_SED_COUNT", 26, 27, &umr_bitfield_default }, + { "IOWR_DATAMEM_SED_COUNT", 28, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_EDC_CNT2[] = { + { "GMIRD_CMDMEM_SEC_COUNT", 0, 1, &umr_bitfield_default }, + { "GMIRD_CMDMEM_DED_COUNT", 2, 3, &umr_bitfield_default }, + { "GMIWR_CMDMEM_SEC_COUNT", 4, 5, &umr_bitfield_default }, + { "GMIWR_CMDMEM_DED_COUNT", 6, 7, &umr_bitfield_default }, + { "GMIWR_DATAMEM_SEC_COUNT", 8, 9, &umr_bitfield_default }, + { "GMIWR_DATAMEM_DED_COUNT", 10, 11, &umr_bitfield_default }, + { "GMIRD_PAGEMEM_SED_COUNT", 12, 13, &umr_bitfield_default }, + { "GMIWR_PAGEMEM_SED_COUNT", 14, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_DSM_CNTL[] = { + { "DRAMRD_CMDMEM_DSM_IRRITATOR_DATA", 0, 1, &umr_bitfield_default }, + { "DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE", 2, 2, &umr_bitfield_default }, + { "DRAMWR_CMDMEM_DSM_IRRITATOR_DATA", 3, 4, &umr_bitfield_default }, + { "DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE", 5, 5, &umr_bitfield_default }, + { "DRAMWR_DATAMEM_DSM_IRRITATOR_DATA", 6, 7, &umr_bitfield_default }, + { "DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE", 8, 8, &umr_bitfield_default }, + { "RRET_TAGMEM_DSM_IRRITATOR_DATA", 9, 10, &umr_bitfield_default }, + { "RRET_TAGMEM_ENABLE_SINGLE_WRITE", 11, 11, &umr_bitfield_default }, + { "WRET_TAGMEM_DSM_IRRITATOR_DATA", 12, 13, &umr_bitfield_default }, + { "WRET_TAGMEM_ENABLE_SINGLE_WRITE", 14, 14, &umr_bitfield_default }, + { "GMIRD_CMDMEM_DSM_IRRITATOR_DATA", 15, 16, &umr_bitfield_default }, + { "GMIRD_CMDMEM_ENABLE_SINGLE_WRITE", 17, 17, &umr_bitfield_default }, + { "GMIWR_CMDMEM_DSM_IRRITATOR_DATA", 18, 19, &umr_bitfield_default }, + { "GMIWR_CMDMEM_ENABLE_SINGLE_WRITE", 20, 20, &umr_bitfield_default }, + { "GMIWR_DATAMEM_DSM_IRRITATOR_DATA", 21, 22, &umr_bitfield_default }, + { "GMIWR_DATAMEM_ENABLE_SINGLE_WRITE", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_DSM_CNTLA[] = { + { "DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA", 0, 1, &umr_bitfield_default }, + { "DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE", 2, 2, &umr_bitfield_default }, + { "DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA", 3, 4, &umr_bitfield_default }, + { "DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE", 5, 5, &umr_bitfield_default }, + { "IORD_CMDMEM_DSM_IRRITATOR_DATA", 6, 7, &umr_bitfield_default }, + { "IORD_CMDMEM_ENABLE_SINGLE_WRITE", 8, 8, &umr_bitfield_default }, + { "IOWR_CMDMEM_DSM_IRRITATOR_DATA", 9, 10, &umr_bitfield_default }, + { "IOWR_CMDMEM_ENABLE_SINGLE_WRITE", 11, 11, &umr_bitfield_default }, + { "IOWR_DATAMEM_DSM_IRRITATOR_DATA", 12, 13, &umr_bitfield_default }, + { "IOWR_DATAMEM_ENABLE_SINGLE_WRITE", 14, 14, &umr_bitfield_default }, + { "GMIRD_PAGEMEM_DSM_IRRITATOR_DATA", 15, 16, &umr_bitfield_default }, + { "GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE", 17, 17, &umr_bitfield_default }, + { "GMIWR_PAGEMEM_DSM_IRRITATOR_DATA", 18, 19, &umr_bitfield_default }, + { "GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE", 20, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_DSM_CNTL2[] = { + { "DRAMRD_CMDMEM_ENABLE_ERROR_INJECT", 0, 1, &umr_bitfield_default }, + { "DRAMRD_CMDMEM_SELECT_INJECT_DELAY", 2, 2, &umr_bitfield_default }, + { "DRAMWR_CMDMEM_ENABLE_ERROR_INJECT", 3, 4, &umr_bitfield_default }, + { "DRAMWR_CMDMEM_SELECT_INJECT_DELAY", 5, 5, &umr_bitfield_default }, + { "DRAMWR_DATAMEM_ENABLE_ERROR_INJECT", 6, 7, &umr_bitfield_default }, + { "DRAMWR_DATAMEM_SELECT_INJECT_DELAY", 8, 8, &umr_bitfield_default }, + { "RRET_TAGMEM_ENABLE_ERROR_INJECT", 9, 10, &umr_bitfield_default }, + { "RRET_TAGMEM_SELECT_INJECT_DELAY", 11, 11, &umr_bitfield_default }, + { "WRET_TAGMEM_ENABLE_ERROR_INJECT", 12, 13, &umr_bitfield_default }, + { "WRET_TAGMEM_SELECT_INJECT_DELAY", 14, 14, &umr_bitfield_default }, + { "GMIRD_CMDMEM_ENABLE_ERROR_INJECT", 15, 16, &umr_bitfield_default }, + { "GMIRD_CMDMEM_SELECT_INJECT_DELAY", 17, 17, &umr_bitfield_default }, + { "GMIWR_CMDMEM_ENABLE_ERROR_INJECT", 18, 19, &umr_bitfield_default }, + { "GMIWR_CMDMEM_SELECT_INJECT_DELAY", 20, 20, &umr_bitfield_default }, + { "GMIWR_DATAMEM_ENABLE_ERROR_INJECT", 21, 22, &umr_bitfield_default }, + { "GMIWR_DATAMEM_SELECT_INJECT_DELAY", 23, 23, &umr_bitfield_default }, + { "INJECT_DELAY", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_DSM_CNTL2A[] = { + { "DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT", 0, 1, &umr_bitfield_default }, + { "DRAMRD_PAGEMEM_SELECT_INJECT_DELAY", 2, 2, &umr_bitfield_default }, + { "DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT", 3, 4, &umr_bitfield_default }, + { "DRAMWR_PAGEMEM_SELECT_INJECT_DELAY", 5, 5, &umr_bitfield_default }, + { "IORD_CMDMEM_ENABLE_ERROR_INJECT", 6, 7, &umr_bitfield_default }, + { "IORD_CMDMEM_SELECT_INJECT_DELAY", 8, 8, &umr_bitfield_default }, + { "IOWR_CMDMEM_ENABLE_ERROR_INJECT", 9, 10, &umr_bitfield_default }, + { "IOWR_CMDMEM_SELECT_INJECT_DELAY", 11, 11, &umr_bitfield_default }, + { "IOWR_DATAMEM_ENABLE_ERROR_INJECT", 12, 13, &umr_bitfield_default }, + { "IOWR_DATAMEM_SELECT_INJECT_DELAY", 14, 14, &umr_bitfield_default }, + { "GMIRD_PAGEMEM_ENABLE_ERROR_INJECT", 15, 16, &umr_bitfield_default }, + { "GMIRD_PAGEMEM_SELECT_INJECT_DELAY", 17, 17, &umr_bitfield_default }, + { "GMIWR_PAGEMEM_ENABLE_ERROR_INJECT", 18, 19, &umr_bitfield_default }, + { "GMIWR_PAGEMEM_SELECT_INJECT_DELAY", 20, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_TCC_XBR_CREDITS[] = { + { "DRAM_RD_LIMIT", 0, 5, &umr_bitfield_default }, + { "DRAM_RD_RESERVE", 6, 7, &umr_bitfield_default }, + { "IO_RD_LIMIT", 8, 13, &umr_bitfield_default }, + { "IO_RD_RESERVE", 14, 15, &umr_bitfield_default }, + { "DRAM_WR_LIMIT", 16, 21, &umr_bitfield_default }, + { "DRAM_WR_RESERVE", 22, 23, &umr_bitfield_default }, + { "IO_WR_LIMIT", 24, 29, &umr_bitfield_default }, + { "IO_WR_RESERVE", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_TCC_XBR_MAXBURST[] = { + { "DRAM_RD", 0, 3, &umr_bitfield_default }, + { "IO_RD", 4, 7, &umr_bitfield_default }, + { "DRAM_WR", 8, 11, &umr_bitfield_default }, + { "IO_WR", 12, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_PROBE_CNTL[] = { + { "REQ2RSP_DELAY", 0, 4, &umr_bitfield_default }, + { "PRB_FILTER_DISABLE", 5, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_PROBE_MAP[] = { + { "CHADDR0_TO_RIGHTTCC", 0, 0, &umr_bitfield_default }, + { "CHADDR1_TO_RIGHTTCC", 1, 1, &umr_bitfield_default }, + { "CHADDR2_TO_RIGHTTCC", 2, 2, &umr_bitfield_default }, + { "CHADDR3_TO_RIGHTTCC", 3, 3, &umr_bitfield_default }, + { "CHADDR4_TO_RIGHTTCC", 4, 4, &umr_bitfield_default }, + { "CHADDR5_TO_RIGHTTCC", 5, 5, &umr_bitfield_default }, + { "CHADDR6_TO_RIGHTTCC", 6, 6, &umr_bitfield_default }, + { "CHADDR7_TO_RIGHTTCC", 7, 7, &umr_bitfield_default }, + { "CHADDR8_TO_RIGHTTCC", 8, 8, &umr_bitfield_default }, + { "CHADDR9_TO_RIGHTTCC", 9, 9, &umr_bitfield_default }, + { "CHADDR10_TO_RIGHTTCC", 10, 10, &umr_bitfield_default }, + { "CHADDR11_TO_RIGHTTCC", 11, 11, &umr_bitfield_default }, + { "CHADDR12_TO_RIGHTTCC", 12, 12, &umr_bitfield_default }, + { "CHADDR13_TO_RIGHTTCC", 13, 13, &umr_bitfield_default }, + { "CHADDR14_TO_RIGHTTCC", 14, 14, &umr_bitfield_default }, + { "CHADDR15_TO_RIGHTTCC", 15, 15, &umr_bitfield_default }, + { "INTLV_SIZE", 16, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_ERR_STATUS[] = { + { "SDP_RDRSP_STATUS", 0, 3, &umr_bitfield_default }, + { "SDP_WRRSP_STATUS", 4, 7, &umr_bitfield_default }, + { "SDP_RDRSP_DATAPARITY_ERROR", 8, 8, &umr_bitfield_default }, + { "CLEAR_ERROR_STATUS", 9, 9, &umr_bitfield_default }, + { "BUSY_ON_ERROR", 10, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_MISC2[] = { + { "CSGROUP_SWAP_IN_DRAM_ARB", 0, 0, &umr_bitfield_default }, + { "CSGROUP_SWAP_IN_GMI_ARB", 1, 1, &umr_bitfield_default }, + { "CSGRP_BURST_LIMIT_DATA_DRAM", 2, 6, &umr_bitfield_default }, + { "CSGRP_BURST_LIMIT_DATA_GMI", 7, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_SDP_BACKDOOR_CMDCREDITS0[] = { + { "CREDITS_RECEIVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_SDP_BACKDOOR_CMDCREDITS1[] = { + { "CREDITS_RECEIVED", 0, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_SDP_BACKDOOR_DATACREDITS0[] = { + { "CREDITS_RECEIVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_SDP_BACKDOOR_DATACREDITS1[] = { + { "CREDITS_RECEIVED", 0, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_SDP_BACKDOOR_MISCCREDITS[] = { + { "RDRSP_CREDITS_RELEASED", 0, 7, &umr_bitfield_default }, + { "WRRSP_CREDITS_RELEASED", 8, 15, &umr_bitfield_default }, + { "PRB_REQ_CREDITS_RELEASED", 16, 22, &umr_bitfield_default }, + { "PRB_RSP_CREDITS_RECEIVED", 23, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_SDP_ENABLE[] = { + { "ENABLE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRMI_GENERAL_CNTL[] = { + { "BURST_DISABLE", 0, 0, &umr_bitfield_default }, + { "VMID_BYPASS_ENABLE", 1, 16, &umr_bitfield_default }, + { "XBAR_MUX_CONFIG", 17, 18, &umr_bitfield_default }, + { "RB0_HARVEST_EN", 19, 19, &umr_bitfield_default }, + { "RB1_HARVEST_EN", 20, 20, &umr_bitfield_default }, + { "LOOPBACK_DIS_BY_REQ_TYPE", 21, 24, &umr_bitfield_default }, + { "XBAR_MUX_CONFIG_UPDATE", 25, 25, &umr_bitfield_default }, + { "SKID_FIFO_0_OVERFLOW_ERROR_MASK", 26, 26, &umr_bitfield_default }, + { "SKID_FIFO_0_UNDERFLOW_ERROR_MASK", 27, 27, &umr_bitfield_default }, + { "SKID_FIFO_1_OVERFLOW_ERROR_MASK", 28, 28, &umr_bitfield_default }, + { "SKID_FIFO_1_UNDERFLOW_ERROR_MASK", 29, 29, &umr_bitfield_default }, + { "SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRMI_GENERAL_CNTL1[] = { + { "EARLY_WRACK_ENABLE_PER_MTYPE", 0, 3, &umr_bitfield_default }, + { "TCIW0_64B_RD_STALL_MODE", 4, 5, &umr_bitfield_default }, + { "TCIW1_64B_RD_STALL_MODE", 6, 7, &umr_bitfield_default }, + { "EARLY_WRACK_DISABLE_FOR_LOOPBACK", 8, 8, &umr_bitfield_default }, + { "POLICY_OVERRIDE_VALUE", 9, 9, &umr_bitfield_default }, + { "POLICY_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "UTCL1_PROBE0_RR_ARB_BURST_HINT_EN", 11, 11, &umr_bitfield_default }, + { "UTCL1_PROBE1_RR_ARB_BURST_HINT_EN", 12, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRMI_GENERAL_STATUS[] = { + { "GENERAL_RMI_ERRORS_COMBINED", 0, 0, &umr_bitfield_default }, + { "SKID_FIFO_0_OVERFLOW_ERROR", 1, 1, &umr_bitfield_default }, + { "SKID_FIFO_0_UNDERFLOW_ERROR", 2, 2, &umr_bitfield_default }, + { "SKID_FIFO_1_OVERFLOW_ERROR", 3, 3, &umr_bitfield_default }, + { "SKID_FIFO_1_UNDERFLOW_ERROR", 4, 4, &umr_bitfield_default }, + { "RMI_XBAR_BUSY", 5, 5, &umr_bitfield_default }, + { "RMI_UTCL1_BUSY", 6, 6, &umr_bitfield_default }, + { "RMI_SCOREBOARD_BUSY", 7, 7, &umr_bitfield_default }, + { "TCIW0_PRT_FIFO_BUSY", 8, 8, &umr_bitfield_default }, + { "TCIW_FRMTR0_BUSY", 9, 9, &umr_bitfield_default }, + { "TCIW_RTN_FRMTR0_BUSY", 10, 10, &umr_bitfield_default }, + { "WRREQ_CONSUMER_FIFO_0_BUSY", 11, 11, &umr_bitfield_default }, + { "RDREQ_CONSUMER_FIFO_0_BUSY", 12, 12, &umr_bitfield_default }, + { "TCIW1_PRT_FIFO_BUSY", 13, 13, &umr_bitfield_default }, + { "TCIW_FRMTR1_BUSY", 14, 14, &umr_bitfield_default }, + { "TCIW_RTN_FRMTR1_BUSY", 15, 15, &umr_bitfield_default }, + { "WRREQ_CONSUMER_FIFO_1_BUSY", 16, 16, &umr_bitfield_default }, + { "RDREQ_CONSUMER_FIFO_1_BUSY", 17, 17, &umr_bitfield_default }, + { "UTC_PROBE1_BUSY", 18, 18, &umr_bitfield_default }, + { "UTC_PROBE0_BUSY", 19, 19, &umr_bitfield_default }, + { "RMI_XNACK_BUSY", 20, 20, &umr_bitfield_default }, + { "XNACK_FIFO_NUM_USED", 21, 28, &umr_bitfield_default }, + { "XNACK_FIFO_EMPTY", 29, 29, &umr_bitfield_default }, + { "XNACK_FIFO_FULL", 30, 30, &umr_bitfield_default }, + { "SKID_FIFO_FREESPACE_IS_ZERO_ERROR", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRMI_SUBBLOCK_STATUS0[] = { + { "UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0", 0, 6, &umr_bitfield_default }, + { "UTC_EXT_LAT_HID_FIFO_FULL_PROBE0", 7, 7, &umr_bitfield_default }, + { "UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0", 8, 8, &umr_bitfield_default }, + { "UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1", 9, 15, &umr_bitfield_default }, + { "UTC_EXT_LAT_HID_FIFO_FULL_PROBE1", 16, 16, &umr_bitfield_default }, + { "UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1", 17, 17, &umr_bitfield_default }, + { "TCIW0_INFLIGHT_CNT", 18, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRMI_SUBBLOCK_STATUS1[] = { + { "SKID_FIFO_0_FREE_SPACE", 0, 9, &umr_bitfield_default }, + { "SKID_FIFO_1_FREE_SPACE", 10, 19, &umr_bitfield_default }, + { "TCIW1_INFLIGHT_CNT", 20, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRMI_SUBBLOCK_STATUS2[] = { + { "PRT_FIFO_0_NUM_USED", 0, 8, &umr_bitfield_default }, + { "PRT_FIFO_1_NUM_USED", 9, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRMI_SUBBLOCK_STATUS3[] = { + { "SKID_FIFO_0_FREE_SPACE_TOTAL", 0, 9, &umr_bitfield_default }, + { "SKID_FIFO_1_FREE_SPACE_TOTAL", 10, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRMI_XBAR_CONFIG[] = { + { "XBAR_MUX_CONFIG_OVERRIDE", 0, 1, &umr_bitfield_default }, + { "XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE", 2, 5, &umr_bitfield_default }, + { "XBAR_MUX_CONFIG_CB_DB_OVERRIDE", 6, 6, &umr_bitfield_default }, + { "ARBITER_DIS", 7, 7, &umr_bitfield_default }, + { "XBAR_EN_IN_REQ", 8, 11, &umr_bitfield_default }, + { "XBAR_EN_IN_REQ_OVERRIDE", 12, 12, &umr_bitfield_default }, + { "XBAR_EN_IN_RB0", 13, 13, &umr_bitfield_default }, + { "XBAR_EN_IN_RB1", 14, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRMI_PROBE_POP_LOGIC_CNTL[] = { + { "EXT_LAT_FIFO_0_MAX_DEPTH", 0, 6, &umr_bitfield_default }, + { "XLAT_COMBINE0_DIS", 7, 7, &umr_bitfield_default }, + { "REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2", 8, 9, &umr_bitfield_default }, + { "EXT_LAT_FIFO_1_MAX_DEPTH", 10, 16, &umr_bitfield_default }, + { "XLAT_COMBINE1_DIS", 17, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRMI_UTC_XNACK_N_MISC_CNTL[] = { + { "MASTER_XNACK_TIMER_INC", 0, 7, &umr_bitfield_default }, + { "IND_XNACK_TIMER_START_VALUE", 8, 11, &umr_bitfield_default }, + { "UTCL1_PERM_MODE", 12, 12, &umr_bitfield_default }, + { "CP_VMID_RESET_REQUEST_DISABLE", 13, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRMI_DEMUX_CNTL[] = { + { "DEMUX_ARB0_STALL", 0, 0, &umr_bitfield_default }, + { "DEMUX_ARB0_BREAK_LOB_ON_IDLEIN", 1, 1, &umr_bitfield_default }, + { "DEMUX_ARB0_STALL_TIMER_OVERRIDE", 4, 5, &umr_bitfield_default }, + { "DEMUX_ARB0_STALL_TIMER_START_VALUE", 6, 13, &umr_bitfield_default }, + { "DEMUX_ARB0_MODE", 14, 15, &umr_bitfield_default }, + { "DEMUX_ARB1_STALL", 16, 16, &umr_bitfield_default }, + { "DEMUX_ARB1_BREAK_LOB_ON_IDLEIN", 17, 17, &umr_bitfield_default }, + { "DEMUX_ARB1_STALL_TIMER_OVERRIDE", 20, 21, &umr_bitfield_default }, + { "DEMUX_ARB1_STALL_TIMER_START_VALUE", 22, 29, &umr_bitfield_default }, + { "DEMUX_ARB1_MODE", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRMI_UTCL1_CNTL1[] = { + { "FORCE_4K_L2_RESP", 0, 0, &umr_bitfield_default }, + { "GPUVM_64K_DEF", 1, 1, &umr_bitfield_default }, + { "GPUVM_PERM_MODE", 2, 2, &umr_bitfield_default }, + { "RESP_MODE", 3, 4, &umr_bitfield_default }, + { "RESP_FAULT_MODE", 5, 6, &umr_bitfield_default }, + { "CLIENTID", 7, 15, &umr_bitfield_default }, + { "USERVM_DIS", 16, 16, &umr_bitfield_default }, + { "ENABLE_PUSH_LFIFO", 17, 17, &umr_bitfield_default }, + { "ENABLE_LFIFO_PRI_ARB", 18, 18, &umr_bitfield_default }, + { "REG_INV_VMID", 19, 22, &umr_bitfield_default }, + { "REG_INV_ALL_VMID", 23, 23, &umr_bitfield_default }, + { "REG_INV_TOGGLE", 24, 24, &umr_bitfield_default }, + { "CLIENT_INVALIDATE_ALL_VMID", 25, 25, &umr_bitfield_default }, + { "FORCE_MISS", 26, 26, &umr_bitfield_default }, + { "FORCE_IN_ORDER", 27, 27, &umr_bitfield_default }, + { "REDUCE_FIFO_DEPTH_BY_2", 28, 29, &umr_bitfield_default }, + { "REDUCE_CACHE_SIZE_BY_2", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRMI_UTCL1_CNTL2[] = { + { "UTC_SPARE", 0, 7, &umr_bitfield_default }, + { "MTYPE_OVRD_DIS", 9, 9, &umr_bitfield_default }, + { "LINE_VALID", 10, 10, &umr_bitfield_default }, + { "DIS_EDC", 11, 11, &umr_bitfield_default }, + { "GPUVM_INV_MODE", 12, 12, &umr_bitfield_default }, + { "SHOOTDOWN_OPT", 13, 13, &umr_bitfield_default }, + { "FORCE_SNOOP", 14, 14, &umr_bitfield_default }, + { "FORCE_GPUVM_INV_ACK", 15, 15, &umr_bitfield_default }, + { "UTCL1_ARB_BURST_MODE", 16, 17, &umr_bitfield_default }, + { "UTCL1_ENABLE_PERF_EVENT_RD_WR", 18, 18, &umr_bitfield_default }, + { "UTCL1_PERF_EVENT_RD_WR", 19, 19, &umr_bitfield_default }, + { "UTCL1_ENABLE_PERF_EVENT_VMID", 20, 20, &umr_bitfield_default }, + { "UTCL1_PERF_EVENT_VMID", 21, 24, &umr_bitfield_default }, + { "UTCL1_DIS_DUAL_L2_REQ", 25, 25, &umr_bitfield_default }, + { "UTCL1_FORCE_FRAG_2M_TO_64K", 26, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRMI_TCIW_FORMATTER0_CNTL[] = { + { "WR_COMBINE0_DIS_OVERRIDE", 0, 0, &umr_bitfield_default }, + { "WR_COMBINE0_TIME_OUT_WINDOW", 1, 8, &umr_bitfield_default }, + { "TCIW0_MAX_ALLOWED_INFLIGHT_REQ", 9, 18, &umr_bitfield_default }, + { "SKID_FIFO_0_FREE_SPACE_DELTA", 19, 26, &umr_bitfield_default }, + { "SKID_FIFO_0_FREE_SPACE_DELTA_UPDATE", 27, 27, &umr_bitfield_default }, + { "TCIW0_REQ_SAFE_MODE", 28, 28, &umr_bitfield_default }, + { "RMI_IN0_REORDER_DIS", 29, 29, &umr_bitfield_default }, + { "WR_COMBINE0_DIS_AT_LAST_OF_BURST", 30, 30, &umr_bitfield_default }, + { "ALL_FAULT_RET0_DATA", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRMI_TCIW_FORMATTER1_CNTL[] = { + { "WR_COMBINE1_DIS_OVERRIDE", 0, 0, &umr_bitfield_default }, + { "WR_COMBINE1_TIME_OUT_WINDOW", 1, 8, &umr_bitfield_default }, + { "TCIW1_MAX_ALLOWED_INFLIGHT_REQ", 9, 18, &umr_bitfield_default }, + { "SKID_FIFO_1_FREE_SPACE_DELTA", 19, 26, &umr_bitfield_default }, + { "SKID_FIFO_1_FREE_SPACE_DELTA_UPDATE", 27, 27, &umr_bitfield_default }, + { "TCIW1_REQ_SAFE_MODE", 28, 28, &umr_bitfield_default }, + { "RMI_IN1_REORDER_DIS", 29, 29, &umr_bitfield_default }, + { "WR_COMBINE1_DIS_AT_LAST_OF_BURST", 30, 30, &umr_bitfield_default }, + { "ALL_FAULT_RET1_DATA", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRMI_SCOREBOARD_CNTL[] = { + { "COMPLETE_RB0_FLUSH", 0, 0, &umr_bitfield_default }, + { "REQ_IN_RE_EN_AFTER_FLUSH_RB0", 1, 1, &umr_bitfield_default }, + { "COMPLETE_RB1_FLUSH", 2, 2, &umr_bitfield_default }, + { "REQ_IN_RE_EN_AFTER_FLUSH_RB1", 3, 3, &umr_bitfield_default }, + { "TIME_STAMP_FLUSH_RB1", 4, 4, &umr_bitfield_default }, + { "VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN", 5, 5, &umr_bitfield_default }, + { "VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE", 6, 6, &umr_bitfield_default }, + { "TIME_STAMP_FLUSH_RB0", 7, 7, &umr_bitfield_default }, + { "FORCE_VMID_INVAL_DONE_EN", 8, 8, &umr_bitfield_default }, + { "FORCE_VMID_INVAL_DONE_TIMER_START_VALUE", 9, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRMI_SCOREBOARD_STATUS0[] = { + { "CURRENT_SESSION_ID", 0, 0, &umr_bitfield_default }, + { "CP_VMID_INV_IN_PROG", 1, 1, &umr_bitfield_default }, + { "CP_VMID_INV_REQ_VMID", 2, 17, &umr_bitfield_default }, + { "CP_VMID_INV_UTC_DONE", 18, 18, &umr_bitfield_default }, + { "CP_VMID_INV_DONE", 19, 19, &umr_bitfield_default }, + { "CP_VMID_INV_FLUSH_TYPE", 20, 20, &umr_bitfield_default }, + { "FORCE_VMID_INV_DONE", 21, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRMI_SCOREBOARD_STATUS1[] = { + { "RUNNING_CNT_RB0", 0, 11, &umr_bitfield_default }, + { "RUNNING_CNT_UNDERFLOW_RB0", 12, 12, &umr_bitfield_default }, + { "RUNNING_CNT_OVERFLOW_RB0", 13, 13, &umr_bitfield_default }, + { "MULTI_VMID_INVAL_FROM_CP_DETECTED", 14, 14, &umr_bitfield_default }, + { "RUNNING_CNT_RB1", 15, 26, &umr_bitfield_default }, + { "RUNNING_CNT_UNDERFLOW_RB1", 27, 27, &umr_bitfield_default }, + { "RUNNING_CNT_OVERFLOW_RB1", 28, 28, &umr_bitfield_default }, + { "COM_FLUSH_IN_PROG_RB1", 29, 29, &umr_bitfield_default }, + { "COM_FLUSH_IN_PROG_RB0", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRMI_SCOREBOARD_STATUS2[] = { + { "SNAPSHOT_CNT_RB0", 0, 11, &umr_bitfield_default }, + { "SNAPSHOT_CNT_UNDERFLOW_RB0", 12, 12, &umr_bitfield_default }, + { "SNAPSHOT_CNT_RB1", 13, 24, &umr_bitfield_default }, + { "SNAPSHOT_CNT_UNDERFLOW_RB1", 25, 25, &umr_bitfield_default }, + { "COM_FLUSH_DONE_RB1", 26, 26, &umr_bitfield_default }, + { "COM_FLUSH_DONE_RB0", 27, 27, &umr_bitfield_default }, + { "TIME_STAMP_FLUSH_IN_PROG_RB0", 28, 28, &umr_bitfield_default }, + { "TIME_STAMP_FLUSH_IN_PROG_RB1", 29, 29, &umr_bitfield_default }, + { "TIME_STAMP_FLUSH_DONE_RB0", 30, 30, &umr_bitfield_default }, + { "TIME_STAMP_FLUSH_DONE_RB1", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRMI_XBAR_ARBITER_CONFIG[] = { + { "XBAR_ARB0_MODE", 0, 1, &umr_bitfield_default }, + { "XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR", 2, 2, &umr_bitfield_default }, + { "XBAR_ARB0_STALL", 3, 3, &umr_bitfield_default }, + { "XBAR_ARB0_BREAK_LOB_ON_IDLEIN", 4, 4, &umr_bitfield_default }, + { "XBAR_ARB0_STALL_TIMER_OVERRIDE", 6, 7, &umr_bitfield_default }, + { "XBAR_ARB0_STALL_TIMER_START_VALUE", 8, 15, &umr_bitfield_default }, + { "XBAR_ARB1_MODE", 16, 17, &umr_bitfield_default }, + { "XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR", 18, 18, &umr_bitfield_default }, + { "XBAR_ARB1_STALL", 19, 19, &umr_bitfield_default }, + { "XBAR_ARB1_BREAK_LOB_ON_IDLEIN", 20, 20, &umr_bitfield_default }, + { "XBAR_ARB1_STALL_TIMER_OVERRIDE", 22, 23, &umr_bitfield_default }, + { "XBAR_ARB1_STALL_TIMER_START_VALUE", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRMI_XBAR_ARBITER_CONFIG_1[] = { + { "XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD", 0, 7, &umr_bitfield_default }, + { "XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR", 8, 15, &umr_bitfield_default }, + { "XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_RD", 16, 23, &umr_bitfield_default }, + { "XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_WR", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRMI_CLOCK_CNTRL[] = { + { "DYN_CLK_RB0_BUSY_MASK", 0, 4, &umr_bitfield_default }, + { "DYN_CLK_CMN_BUSY_MASK", 5, 9, &umr_bitfield_default }, + { "DYN_CLK_RB0_WAKEUP_MASK", 10, 14, &umr_bitfield_default }, + { "DYN_CLK_CMN_WAKEUP_MASK", 15, 19, &umr_bitfield_default }, + { "DYN_CLK_RB1_BUSY_MASK", 20, 24, &umr_bitfield_default }, + { "DYN_CLK_RB1_WAKEUP_MASK", 25, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRMI_UTCL1_STATUS[] = { + { "FAULT_DETECTED", 0, 0, &umr_bitfield_default }, + { "RETRY_DETECTED", 1, 1, &umr_bitfield_default }, + { "PRT_DETECTED", 2, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRMI_SPARE[] = { + { "RMI_ARBITER_STALL_TIMER_ENABLED_ALLOW_STREAMING", 0, 0, &umr_bitfield_default }, + { "SPARE_BIT_1", 1, 1, &umr_bitfield_default }, + { "SPARE_BIT_2", 2, 2, &umr_bitfield_default }, + { "SPARE_BIT_3", 3, 3, &umr_bitfield_default }, + { "SPARE_BIT_4", 4, 4, &umr_bitfield_default }, + { "SPARE_BIT_5", 5, 5, &umr_bitfield_default }, + { "SPARE_BIT_6", 6, 6, &umr_bitfield_default }, + { "SPARE_BIT_7", 7, 7, &umr_bitfield_default }, + { "SPARE_BIT_8_0", 8, 15, &umr_bitfield_default }, + { "SPARE_BIT_16_0", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRMI_SPARE_1[] = { + { "SPARE_BIT_8", 0, 0, &umr_bitfield_default }, + { "SPARE_BIT_9", 1, 1, &umr_bitfield_default }, + { "SPARE_BIT_10", 2, 2, &umr_bitfield_default }, + { "SPARE_BIT_11", 3, 3, &umr_bitfield_default }, + { "SPARE_BIT_12", 4, 4, &umr_bitfield_default }, + { "SPARE_BIT_13", 5, 5, &umr_bitfield_default }, + { "SPARE_BIT_14", 6, 6, &umr_bitfield_default }, + { "SPARE_BIT_15", 7, 7, &umr_bitfield_default }, + { "SPARE_BIT_8_1", 8, 15, &umr_bitfield_default }, + { "SPARE_BIT_16_1", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRMI_SPARE_2[] = { + { "SPARE_BIT_16", 0, 0, &umr_bitfield_default }, + { "SPARE_BIT_17", 1, 1, &umr_bitfield_default }, + { "SPARE_BIT_18", 2, 2, &umr_bitfield_default }, + { "SPARE_BIT_19", 3, 3, &umr_bitfield_default }, + { "SPARE_BIT_20", 4, 4, &umr_bitfield_default }, + { "SPARE_BIT_21", 5, 5, &umr_bitfield_default }, + { "SPARE_BIT_22", 6, 6, &umr_bitfield_default }, + { "SPARE_BIT_23", 7, 7, &umr_bitfield_default }, + { "SPARE_BIT_4_0", 8, 11, &umr_bitfield_default }, + { "SPARE_BIT_4_1", 12, 15, &umr_bitfield_default }, + { "SPARE_BIT_8_2", 16, 23, &umr_bitfield_default }, + { "SPARE_BIT_8_3", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmport_a_addr[] = { + { "Index", 0, 7, &umr_bitfield_default }, + { "Reserved", 8, 30, &umr_bitfield_default }, + { "ReadEnable", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmport_a_data_lo[] = { + { "Data", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmport_a_data_hi[] = { + { "Data", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmport_b_addr[] = { + { "Index", 0, 7, &umr_bitfield_default }, + { "Reserved", 8, 30, &umr_bitfield_default }, + { "ReadEnable", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmport_b_data_lo[] = { + { "Data", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmport_b_data_hi[] = { + { "Data", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmport_c_addr[] = { + { "Index", 0, 7, &umr_bitfield_default }, + { "Reserved", 8, 30, &umr_bitfield_default }, + { "ReadEnable", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmport_c_data_lo[] = { + { "Data", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmport_c_data_hi[] = { + { "Data", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmport_d_addr[] = { + { "Index", 0, 7, &umr_bitfield_default }, + { "Reserved", 8, 30, &umr_bitfield_default }, + { "ReadEnable", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmport_d_data_lo[] = { + { "Data", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmport_d_data_hi[] = { + { "Data", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmATC_L2_CNTL[] = { + { "NUMBER_OF_TRANSLATION_READ_REQUESTS", 0, 1, &umr_bitfield_default }, + { "NUMBER_OF_TRANSLATION_WRITE_REQUESTS", 3, 4, &umr_bitfield_default }, + { "NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD", 6, 6, &umr_bitfield_default }, + { "NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD", 7, 7, &umr_bitfield_default }, + { "CACHE_INVALIDATE_MODE", 8, 10, &umr_bitfield_default }, + { "ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY", 11, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmATC_L2_CNTL2[] = { + { "BANK_SELECT", 0, 5, &umr_bitfield_default }, + { "L2_CACHE_UPDATE_MODE", 6, 7, &umr_bitfield_default }, + { "ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE", 8, 8, &umr_bitfield_default }, + { "L2_CACHE_SWAP_TAG_INDEX_LSBS", 9, 11, &umr_bitfield_default }, + { "L2_CACHE_VMID_MODE", 12, 14, &umr_bitfield_default }, + { "L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE", 15, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmATC_L2_CACHE_DATA0[] = { + { "DATA_REGISTER_VALID", 0, 0, &umr_bitfield_default }, + { "CACHE_ENTRY_VALID", 1, 1, &umr_bitfield_default }, + { "CACHED_ATTRIBUTES", 2, 22, &umr_bitfield_default }, + { "VIRTUAL_PAGE_ADDRESS_HIGH", 23, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmATC_L2_CACHE_DATA1[] = { + { "VIRTUAL_PAGE_ADDRESS_LOW", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmATC_L2_CACHE_DATA2[] = { + { "PHYSICAL_PAGE_ADDRESS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmATC_L2_CNTL3[] = { + { "DELAY_SEND_INVALIDATION_REQUEST", 0, 2, &umr_bitfield_default }, + { "ATS_REQUEST_CREDIT_MINUS1", 3, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmATC_L2_STATUS[] = { + { "BUSY", 0, 0, &umr_bitfield_default }, + { "PARITY_ERROR_INFO", 1, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmATC_L2_STATUS2[] = { + { "IFIFO_NON_FATAL_PARITY_ERROR_INFO", 0, 7, &umr_bitfield_default }, + { "IFIFO_FATAL_PARITY_ERROR_INFO", 8, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmATC_L2_MISC_CG[] = { + { "OFFDLY", 6, 11, &umr_bitfield_default }, + { "ENABLE", 18, 18, &umr_bitfield_default }, + { "MEM_LS_ENABLE", 19, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmATC_L2_MEM_POWER_LS[] = { + { "LS_SETUP", 0, 5, &umr_bitfield_default }, + { "LS_HOLD", 6, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmATC_L2_CGTT_CLK_CTRL[] = { + { "ON_DELAY", 0, 3, &umr_bitfield_default }, + { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default }, + { "MGLS_OVERRIDE", 15, 15, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE", 16, 23, &umr_bitfield_default }, + { "SOFT_OVERRIDE", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_L2_CNTL[] = { + { "ENABLE_L2_CACHE", 0, 0, &umr_bitfield_default }, + { "ENABLE_L2_FRAGMENT_PROCESSING", 1, 1, &umr_bitfield_default }, + { "L2_CACHE_PTE_ENDIAN_SWAP_MODE", 2, 3, &umr_bitfield_default }, + { "L2_CACHE_PDE_ENDIAN_SWAP_MODE", 4, 5, &umr_bitfield_default }, + { "L2_PDE0_CACHE_TAG_GENERATION_MODE", 8, 8, &umr_bitfield_default }, + { "ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE", 9, 9, &umr_bitfield_default }, + { "ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE", 10, 10, &umr_bitfield_default }, + { "ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY", 11, 11, &umr_bitfield_default }, + { "L2_PDE0_CACHE_SPLIT_MODE", 12, 14, &umr_bitfield_default }, + { "EFFECTIVE_L2_QUEUE_SIZE", 15, 17, &umr_bitfield_default }, + { "PDE_FAULT_CLASSIFICATION", 18, 18, &umr_bitfield_default }, + { "CONTEXT1_IDENTITY_ACCESS_MODE", 19, 20, &umr_bitfield_default }, + { "IDENTITY_MODE_FRAGMENT_SIZE", 21, 25, &umr_bitfield_default }, + { "L2_PTE_CACHE_ADDR_MODE", 26, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_L2_CNTL2[] = { + { "INVALIDATE_ALL_L1_TLBS", 0, 0, &umr_bitfield_default }, + { "INVALIDATE_L2_CACHE", 1, 1, &umr_bitfield_default }, + { "DISABLE_INVALIDATE_PER_DOMAIN", 21, 21, &umr_bitfield_default }, + { "DISABLE_BIGK_CACHE_OPTIMIZATION", 22, 22, &umr_bitfield_default }, + { "L2_PTE_CACHE_VMID_MODE", 23, 25, &umr_bitfield_default }, + { "INVALIDATE_CACHE_MODE", 26, 27, &umr_bitfield_default }, + { "PDE_CACHE_EFFECTIVE_SIZE", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_L2_CNTL3[] = { + { "BANK_SELECT", 0, 5, &umr_bitfield_default }, + { "L2_CACHE_UPDATE_MODE", 6, 7, &umr_bitfield_default }, + { "L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE", 8, 12, &umr_bitfield_default }, + { "L2_CACHE_BIGK_FRAGMENT_SIZE", 15, 19, &umr_bitfield_default }, + { "L2_CACHE_BIGK_ASSOCIATIVITY", 20, 20, &umr_bitfield_default }, + { "L2_CACHE_4K_EFFECTIVE_SIZE", 21, 23, &umr_bitfield_default }, + { "L2_CACHE_BIGK_EFFECTIVE_SIZE", 24, 27, &umr_bitfield_default }, + { "L2_CACHE_4K_FORCE_MISS", 28, 28, &umr_bitfield_default }, + { "L2_CACHE_BIGK_FORCE_MISS", 29, 29, &umr_bitfield_default }, + { "PDE_CACHE_FORCE_MISS", 30, 30, &umr_bitfield_default }, + { "L2_CACHE_4K_ASSOCIATIVITY", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_L2_STATUS[] = { + { "L2_BUSY", 0, 0, &umr_bitfield_default }, + { "CONTEXT_DOMAIN_BUSY", 1, 16, &umr_bitfield_default }, + { "FOUND_4K_PTE_CACHE_PARITY_ERRORS", 17, 17, &umr_bitfield_default }, + { "FOUND_BIGK_PTE_CACHE_PARITY_ERRORS", 18, 18, &umr_bitfield_default }, + { "FOUND_PDE0_CACHE_PARITY_ERRORS", 19, 19, &umr_bitfield_default }, + { "FOUND_PDE1_CACHE_PARITY_ERRORS", 20, 20, &umr_bitfield_default }, + { "FOUND_PDE2_CACHE_PARITY_ERRORS", 21, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_DUMMY_PAGE_FAULT_CNTL[] = { + { "DUMMY_PAGE_FAULT_ENABLE", 0, 0, &umr_bitfield_default }, + { "DUMMY_PAGE_ADDRESS_LOGICAL", 1, 1, &umr_bitfield_default }, + { "DUMMY_PAGE_COMPARE_MSBS", 2, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_DUMMY_PAGE_FAULT_ADDR_LO32[] = { + { "DUMMY_PAGE_ADDR_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_DUMMY_PAGE_FAULT_ADDR_HI32[] = { + { "DUMMY_PAGE_ADDR_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_L2_PROTECTION_FAULT_CNTL[] = { + { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 0, 0, &umr_bitfield_default }, + { "ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES", 1, 1, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 2, 2, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_DEFAULT", 3, 3, &umr_bitfield_default }, + { "PDE1_PROTECTION_FAULT_ENABLE_DEFAULT", 4, 4, &umr_bitfield_default }, + { "PDE2_PROTECTION_FAULT_ENABLE_DEFAULT", 5, 5, &umr_bitfield_default }, + { "TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT", 6, 6, &umr_bitfield_default }, + { "NACK_PROTECTION_FAULT_ENABLE_DEFAULT", 7, 7, &umr_bitfield_default }, + { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT", 8, 8, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 9, 9, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 10, 10, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_DEFAULT", 11, 11, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT", 12, 12, &umr_bitfield_default }, + { "CLIENT_ID_NO_RETRY_FAULT_INTERRUPT", 13, 28, &umr_bitfield_default }, + { "OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT", 29, 29, &umr_bitfield_default }, + { "CRASH_ON_NO_RETRY_FAULT", 30, 30, &umr_bitfield_default }, + { "CRASH_ON_RETRY_FAULT", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_L2_PROTECTION_FAULT_CNTL2[] = { + { "CLIENT_ID_PRT_FAULT_INTERRUPT", 0, 15, &umr_bitfield_default }, + { "OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT", 16, 16, &umr_bitfield_default }, + { "ACTIVE_PAGE_MIGRATION_PTE", 17, 17, &umr_bitfield_default }, + { "ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY", 18, 18, &umr_bitfield_default }, + { "ENABLE_RETRY_FAULT_INTERRUPT", 19, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_L2_PROTECTION_FAULT_MM_CNTL3[] = { + { "VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_L2_PROTECTION_FAULT_MM_CNTL4[] = { + { "VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_L2_PROTECTION_FAULT_STATUS[] = { + { "MORE_FAULTS", 0, 0, &umr_bitfield_default }, + { "WALKER_ERROR", 1, 3, &umr_bitfield_default }, + { "PERMISSION_FAULTS", 4, 7, &umr_bitfield_default }, + { "MAPPING_ERROR", 8, 8, &umr_bitfield_default }, + { "CID", 9, 17, &umr_bitfield_default }, + { "RW", 18, 18, &umr_bitfield_default }, + { "ATOMIC", 19, 19, &umr_bitfield_default }, + { "VMID", 20, 23, &umr_bitfield_default }, + { "VF", 24, 24, &umr_bitfield_default }, + { "VFID", 25, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_L2_PROTECTION_FAULT_ADDR_LO32[] = { + { "LOGICAL_PAGE_ADDR_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_L2_PROTECTION_FAULT_ADDR_HI32[] = { + { "LOGICAL_PAGE_ADDR_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32[] = { + { "PHYSICAL_PAGE_ADDR_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32[] = { + { "PHYSICAL_PAGE_ADDR_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32[] = { + { "PHYSICAL_PAGE_OFFSET_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32[] = { + { "PHYSICAL_PAGE_OFFSET_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_L2_CNTL4[] = { + { "L2_CACHE_4K_PARTITION_COUNT", 0, 5, &umr_bitfield_default }, + { "VMC_TAP_PDE_REQUEST_PHYSICAL", 6, 6, &umr_bitfield_default }, + { "VMC_TAP_PTE_REQUEST_PHYSICAL", 7, 7, &umr_bitfield_default }, + { "MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT", 8, 17, &umr_bitfield_default }, + { "MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT", 18, 27, &umr_bitfield_default }, + { "BPM_CGCGLS_OVERRIDE", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_L2_MM_GROUP_RT_CLASSES[] = { + { "GROUP_0_RT_CLASS", 0, 0, &umr_bitfield_default }, + { "GROUP_1_RT_CLASS", 1, 1, &umr_bitfield_default }, + { "GROUP_2_RT_CLASS", 2, 2, &umr_bitfield_default }, + { "GROUP_3_RT_CLASS", 3, 3, &umr_bitfield_default }, + { "GROUP_4_RT_CLASS", 4, 4, &umr_bitfield_default }, + { "GROUP_5_RT_CLASS", 5, 5, &umr_bitfield_default }, + { "GROUP_6_RT_CLASS", 6, 6, &umr_bitfield_default }, + { "GROUP_7_RT_CLASS", 7, 7, &umr_bitfield_default }, + { "GROUP_8_RT_CLASS", 8, 8, &umr_bitfield_default }, + { "GROUP_9_RT_CLASS", 9, 9, &umr_bitfield_default }, + { "GROUP_10_RT_CLASS", 10, 10, &umr_bitfield_default }, + { "GROUP_11_RT_CLASS", 11, 11, &umr_bitfield_default }, + { "GROUP_12_RT_CLASS", 12, 12, &umr_bitfield_default }, + { "GROUP_13_RT_CLASS", 13, 13, &umr_bitfield_default }, + { "GROUP_14_RT_CLASS", 14, 14, &umr_bitfield_default }, + { "GROUP_15_RT_CLASS", 15, 15, &umr_bitfield_default }, + { "GROUP_16_RT_CLASS", 16, 16, &umr_bitfield_default }, + { "GROUP_17_RT_CLASS", 17, 17, &umr_bitfield_default }, + { "GROUP_18_RT_CLASS", 18, 18, &umr_bitfield_default }, + { "GROUP_19_RT_CLASS", 19, 19, &umr_bitfield_default }, + { "GROUP_20_RT_CLASS", 20, 20, &umr_bitfield_default }, + { "GROUP_21_RT_CLASS", 21, 21, &umr_bitfield_default }, + { "GROUP_22_RT_CLASS", 22, 22, &umr_bitfield_default }, + { "GROUP_23_RT_CLASS", 23, 23, &umr_bitfield_default }, + { "GROUP_24_RT_CLASS", 24, 24, &umr_bitfield_default }, + { "GROUP_25_RT_CLASS", 25, 25, &umr_bitfield_default }, + { "GROUP_26_RT_CLASS", 26, 26, &umr_bitfield_default }, + { "GROUP_27_RT_CLASS", 27, 27, &umr_bitfield_default }, + { "GROUP_28_RT_CLASS", 28, 28, &umr_bitfield_default }, + { "GROUP_29_RT_CLASS", 29, 29, &umr_bitfield_default }, + { "GROUP_30_RT_CLASS", 30, 30, &umr_bitfield_default }, + { "GROUP_31_RT_CLASS", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_L2_BANK_SELECT_RESERVED_CID[] = { + { "RESERVED_READ_CLIENT_ID", 0, 8, &umr_bitfield_default }, + { "RESERVED_WRITE_CLIENT_ID", 10, 18, &umr_bitfield_default }, + { "ENABLE", 20, 20, &umr_bitfield_default }, + { "RESERVED_CACHE_INVALIDATION_MODE", 24, 24, &umr_bitfield_default }, + { "RESERVED_CACHE_PRIVATE_INVALIDATION", 25, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_L2_BANK_SELECT_RESERVED_CID2[] = { + { "RESERVED_READ_CLIENT_ID", 0, 8, &umr_bitfield_default }, + { "RESERVED_WRITE_CLIENT_ID", 10, 18, &umr_bitfield_default }, + { "ENABLE", 20, 20, &umr_bitfield_default }, + { "RESERVED_CACHE_INVALIDATION_MODE", 24, 24, &umr_bitfield_default }, + { "RESERVED_CACHE_PRIVATE_INVALIDATION", 25, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_L2_CACHE_PARITY_CNTL[] = { + { "ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES", 0, 0, &umr_bitfield_default }, + { "ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES", 1, 1, &umr_bitfield_default }, + { "ENABLE_PARITY_CHECKS_IN_PDE_CACHES", 2, 2, &umr_bitfield_default }, + { "FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE", 3, 3, &umr_bitfield_default }, + { "FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE", 4, 4, &umr_bitfield_default }, + { "FORCE_PARITY_MISMATCH_IN_PDE_CACHE", 5, 5, &umr_bitfield_default }, + { "FORCE_CACHE_BANK", 6, 8, &umr_bitfield_default }, + { "FORCE_CACHE_NUMBER", 9, 11, &umr_bitfield_default }, + { "FORCE_CACHE_ASSOC", 12, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_L2_CGTT_CLK_CTRL[] = { + { "ON_DELAY", 0, 3, &umr_bitfield_default }, + { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default }, + { "MGLS_OVERRIDE", 15, 15, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE", 16, 23, &umr_bitfield_default }, + { "SOFT_OVERRIDE", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT0_CNTL[] = { + { "ENABLE_CONTEXT", 0, 0, &umr_bitfield_default }, + { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default }, + { "PAGE_TABLE_BLOCK_SIZE", 3, 6, &umr_bitfield_default }, + { "RETRY_PERMISSION_OR_INVALID_PAGE_FAULT", 7, 7, &umr_bitfield_default }, + { "RETRY_OTHER_FAULT", 8, 8, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 9, 9, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 10, 10, &umr_bitfield_default }, + { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 11, 11, &umr_bitfield_default }, + { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT", 12, 12, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT", 13, 13, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_DEFAULT", 14, 14, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 17, 17, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 18, 18, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT", 19, 19, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_DEFAULT", 20, 20, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT", 21, 21, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT", 22, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT1_CNTL[] = { + { "ENABLE_CONTEXT", 0, 0, &umr_bitfield_default }, + { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default }, + { "PAGE_TABLE_BLOCK_SIZE", 3, 6, &umr_bitfield_default }, + { "RETRY_PERMISSION_OR_INVALID_PAGE_FAULT", 7, 7, &umr_bitfield_default }, + { "RETRY_OTHER_FAULT", 8, 8, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 9, 9, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 10, 10, &umr_bitfield_default }, + { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 11, 11, &umr_bitfield_default }, + { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT", 12, 12, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT", 13, 13, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_DEFAULT", 14, 14, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 17, 17, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 18, 18, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT", 19, 19, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_DEFAULT", 20, 20, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT", 21, 21, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT", 22, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT2_CNTL[] = { + { "ENABLE_CONTEXT", 0, 0, &umr_bitfield_default }, + { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default }, + { "PAGE_TABLE_BLOCK_SIZE", 3, 6, &umr_bitfield_default }, + { "RETRY_PERMISSION_OR_INVALID_PAGE_FAULT", 7, 7, &umr_bitfield_default }, + { "RETRY_OTHER_FAULT", 8, 8, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 9, 9, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 10, 10, &umr_bitfield_default }, + { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 11, 11, &umr_bitfield_default }, + { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT", 12, 12, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT", 13, 13, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_DEFAULT", 14, 14, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 17, 17, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 18, 18, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT", 19, 19, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_DEFAULT", 20, 20, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT", 21, 21, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT", 22, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT3_CNTL[] = { + { "ENABLE_CONTEXT", 0, 0, &umr_bitfield_default }, + { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default }, + { "PAGE_TABLE_BLOCK_SIZE", 3, 6, &umr_bitfield_default }, + { "RETRY_PERMISSION_OR_INVALID_PAGE_FAULT", 7, 7, &umr_bitfield_default }, + { "RETRY_OTHER_FAULT", 8, 8, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 9, 9, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 10, 10, &umr_bitfield_default }, + { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 11, 11, &umr_bitfield_default }, + { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT", 12, 12, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT", 13, 13, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_DEFAULT", 14, 14, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 17, 17, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 18, 18, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT", 19, 19, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_DEFAULT", 20, 20, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT", 21, 21, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT", 22, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT4_CNTL[] = { + { "ENABLE_CONTEXT", 0, 0, &umr_bitfield_default }, + { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default }, + { "PAGE_TABLE_BLOCK_SIZE", 3, 6, &umr_bitfield_default }, + { "RETRY_PERMISSION_OR_INVALID_PAGE_FAULT", 7, 7, &umr_bitfield_default }, + { "RETRY_OTHER_FAULT", 8, 8, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 9, 9, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 10, 10, &umr_bitfield_default }, + { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 11, 11, &umr_bitfield_default }, + { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT", 12, 12, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT", 13, 13, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_DEFAULT", 14, 14, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 17, 17, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 18, 18, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT", 19, 19, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_DEFAULT", 20, 20, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT", 21, 21, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT", 22, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT5_CNTL[] = { + { "ENABLE_CONTEXT", 0, 0, &umr_bitfield_default }, + { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default }, + { "PAGE_TABLE_BLOCK_SIZE", 3, 6, &umr_bitfield_default }, + { "RETRY_PERMISSION_OR_INVALID_PAGE_FAULT", 7, 7, &umr_bitfield_default }, + { "RETRY_OTHER_FAULT", 8, 8, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 9, 9, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 10, 10, &umr_bitfield_default }, + { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 11, 11, &umr_bitfield_default }, + { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT", 12, 12, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT", 13, 13, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_DEFAULT", 14, 14, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 17, 17, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 18, 18, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT", 19, 19, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_DEFAULT", 20, 20, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT", 21, 21, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT", 22, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT6_CNTL[] = { + { "ENABLE_CONTEXT", 0, 0, &umr_bitfield_default }, + { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default }, + { "PAGE_TABLE_BLOCK_SIZE", 3, 6, &umr_bitfield_default }, + { "RETRY_PERMISSION_OR_INVALID_PAGE_FAULT", 7, 7, &umr_bitfield_default }, + { "RETRY_OTHER_FAULT", 8, 8, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 9, 9, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 10, 10, &umr_bitfield_default }, + { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 11, 11, &umr_bitfield_default }, + { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT", 12, 12, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT", 13, 13, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_DEFAULT", 14, 14, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 17, 17, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 18, 18, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT", 19, 19, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_DEFAULT", 20, 20, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT", 21, 21, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT", 22, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT7_CNTL[] = { + { "ENABLE_CONTEXT", 0, 0, &umr_bitfield_default }, + { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default }, + { "PAGE_TABLE_BLOCK_SIZE", 3, 6, &umr_bitfield_default }, + { "RETRY_PERMISSION_OR_INVALID_PAGE_FAULT", 7, 7, &umr_bitfield_default }, + { "RETRY_OTHER_FAULT", 8, 8, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 9, 9, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 10, 10, &umr_bitfield_default }, + { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 11, 11, &umr_bitfield_default }, + { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT", 12, 12, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT", 13, 13, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_DEFAULT", 14, 14, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 17, 17, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 18, 18, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT", 19, 19, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_DEFAULT", 20, 20, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT", 21, 21, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT", 22, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT8_CNTL[] = { + { "ENABLE_CONTEXT", 0, 0, &umr_bitfield_default }, + { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default }, + { "PAGE_TABLE_BLOCK_SIZE", 3, 6, &umr_bitfield_default }, + { "RETRY_PERMISSION_OR_INVALID_PAGE_FAULT", 7, 7, &umr_bitfield_default }, + { "RETRY_OTHER_FAULT", 8, 8, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 9, 9, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 10, 10, &umr_bitfield_default }, + { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 11, 11, &umr_bitfield_default }, + { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT", 12, 12, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT", 13, 13, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_DEFAULT", 14, 14, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 17, 17, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 18, 18, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT", 19, 19, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_DEFAULT", 20, 20, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT", 21, 21, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT", 22, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT9_CNTL[] = { + { "ENABLE_CONTEXT", 0, 0, &umr_bitfield_default }, + { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default }, + { "PAGE_TABLE_BLOCK_SIZE", 3, 6, &umr_bitfield_default }, + { "RETRY_PERMISSION_OR_INVALID_PAGE_FAULT", 7, 7, &umr_bitfield_default }, + { "RETRY_OTHER_FAULT", 8, 8, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 9, 9, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 10, 10, &umr_bitfield_default }, + { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 11, 11, &umr_bitfield_default }, + { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT", 12, 12, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT", 13, 13, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_DEFAULT", 14, 14, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 17, 17, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 18, 18, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT", 19, 19, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_DEFAULT", 20, 20, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT", 21, 21, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT", 22, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT10_CNTL[] = { + { "ENABLE_CONTEXT", 0, 0, &umr_bitfield_default }, + { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default }, + { "PAGE_TABLE_BLOCK_SIZE", 3, 6, &umr_bitfield_default }, + { "RETRY_PERMISSION_OR_INVALID_PAGE_FAULT", 7, 7, &umr_bitfield_default }, + { "RETRY_OTHER_FAULT", 8, 8, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 9, 9, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 10, 10, &umr_bitfield_default }, + { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 11, 11, &umr_bitfield_default }, + { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT", 12, 12, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT", 13, 13, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_DEFAULT", 14, 14, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 17, 17, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 18, 18, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT", 19, 19, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_DEFAULT", 20, 20, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT", 21, 21, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT", 22, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT11_CNTL[] = { + { "ENABLE_CONTEXT", 0, 0, &umr_bitfield_default }, + { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default }, + { "PAGE_TABLE_BLOCK_SIZE", 3, 6, &umr_bitfield_default }, + { "RETRY_PERMISSION_OR_INVALID_PAGE_FAULT", 7, 7, &umr_bitfield_default }, + { "RETRY_OTHER_FAULT", 8, 8, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 9, 9, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 10, 10, &umr_bitfield_default }, + { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 11, 11, &umr_bitfield_default }, + { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT", 12, 12, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT", 13, 13, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_DEFAULT", 14, 14, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 17, 17, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 18, 18, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT", 19, 19, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_DEFAULT", 20, 20, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT", 21, 21, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT", 22, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT12_CNTL[] = { + { "ENABLE_CONTEXT", 0, 0, &umr_bitfield_default }, + { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default }, + { "PAGE_TABLE_BLOCK_SIZE", 3, 6, &umr_bitfield_default }, + { "RETRY_PERMISSION_OR_INVALID_PAGE_FAULT", 7, 7, &umr_bitfield_default }, + { "RETRY_OTHER_FAULT", 8, 8, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 9, 9, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 10, 10, &umr_bitfield_default }, + { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 11, 11, &umr_bitfield_default }, + { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT", 12, 12, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT", 13, 13, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_DEFAULT", 14, 14, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 17, 17, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 18, 18, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT", 19, 19, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_DEFAULT", 20, 20, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT", 21, 21, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT", 22, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT13_CNTL[] = { + { "ENABLE_CONTEXT", 0, 0, &umr_bitfield_default }, + { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default }, + { "PAGE_TABLE_BLOCK_SIZE", 3, 6, &umr_bitfield_default }, + { "RETRY_PERMISSION_OR_INVALID_PAGE_FAULT", 7, 7, &umr_bitfield_default }, + { "RETRY_OTHER_FAULT", 8, 8, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 9, 9, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 10, 10, &umr_bitfield_default }, + { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 11, 11, &umr_bitfield_default }, + { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT", 12, 12, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT", 13, 13, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_DEFAULT", 14, 14, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 17, 17, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 18, 18, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT", 19, 19, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_DEFAULT", 20, 20, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT", 21, 21, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT", 22, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT14_CNTL[] = { + { "ENABLE_CONTEXT", 0, 0, &umr_bitfield_default }, + { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default }, + { "PAGE_TABLE_BLOCK_SIZE", 3, 6, &umr_bitfield_default }, + { "RETRY_PERMISSION_OR_INVALID_PAGE_FAULT", 7, 7, &umr_bitfield_default }, + { "RETRY_OTHER_FAULT", 8, 8, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 9, 9, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 10, 10, &umr_bitfield_default }, + { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 11, 11, &umr_bitfield_default }, + { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT", 12, 12, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT", 13, 13, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_DEFAULT", 14, 14, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 17, 17, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 18, 18, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT", 19, 19, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_DEFAULT", 20, 20, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT", 21, 21, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT", 22, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT15_CNTL[] = { + { "ENABLE_CONTEXT", 0, 0, &umr_bitfield_default }, + { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default }, + { "PAGE_TABLE_BLOCK_SIZE", 3, 6, &umr_bitfield_default }, + { "RETRY_PERMISSION_OR_INVALID_PAGE_FAULT", 7, 7, &umr_bitfield_default }, + { "RETRY_OTHER_FAULT", 8, 8, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 9, 9, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 10, 10, &umr_bitfield_default }, + { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 11, 11, &umr_bitfield_default }, + { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT", 12, 12, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT", 13, 13, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_DEFAULT", 14, 14, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 17, 17, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 18, 18, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT", 19, 19, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_DEFAULT", 20, 20, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT", 21, 21, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT", 22, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXTS_DISABLE[] = { + { "DISABLE_CONTEXT_0", 0, 0, &umr_bitfield_default }, + { "DISABLE_CONTEXT_1", 1, 1, &umr_bitfield_default }, + { "DISABLE_CONTEXT_2", 2, 2, &umr_bitfield_default }, + { "DISABLE_CONTEXT_3", 3, 3, &umr_bitfield_default }, + { "DISABLE_CONTEXT_4", 4, 4, &umr_bitfield_default }, + { "DISABLE_CONTEXT_5", 5, 5, &umr_bitfield_default }, + { "DISABLE_CONTEXT_6", 6, 6, &umr_bitfield_default }, + { "DISABLE_CONTEXT_7", 7, 7, &umr_bitfield_default }, + { "DISABLE_CONTEXT_8", 8, 8, &umr_bitfield_default }, + { "DISABLE_CONTEXT_9", 9, 9, &umr_bitfield_default }, + { "DISABLE_CONTEXT_10", 10, 10, &umr_bitfield_default }, + { "DISABLE_CONTEXT_11", 11, 11, &umr_bitfield_default }, + { "DISABLE_CONTEXT_12", 12, 12, &umr_bitfield_default }, + { "DISABLE_CONTEXT_13", 13, 13, &umr_bitfield_default }, + { "DISABLE_CONTEXT_14", 14, 14, &umr_bitfield_default }, + { "DISABLE_CONTEXT_15", 15, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG0_SEM[] = { + { "SEMAPHORE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG1_SEM[] = { + { "SEMAPHORE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG2_SEM[] = { + { "SEMAPHORE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG3_SEM[] = { + { "SEMAPHORE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG4_SEM[] = { + { "SEMAPHORE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG5_SEM[] = { + { "SEMAPHORE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG6_SEM[] = { + { "SEMAPHORE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG7_SEM[] = { + { "SEMAPHORE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG8_SEM[] = { + { "SEMAPHORE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG9_SEM[] = { + { "SEMAPHORE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG10_SEM[] = { + { "SEMAPHORE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG11_SEM[] = { + { "SEMAPHORE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG12_SEM[] = { + { "SEMAPHORE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG13_SEM[] = { + { "SEMAPHORE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG14_SEM[] = { + { "SEMAPHORE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG15_SEM[] = { + { "SEMAPHORE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG16_SEM[] = { + { "SEMAPHORE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG17_SEM[] = { + { "SEMAPHORE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG0_REQ[] = { + { "PER_VMID_INVALIDATE_REQ", 0, 15, &umr_bitfield_default }, + { "FLUSH_TYPE", 16, 17, &umr_bitfield_default }, + { "INVALIDATE_L2_PTES", 18, 18, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE0", 19, 19, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE1", 20, 20, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE2", 21, 21, &umr_bitfield_default }, + { "INVALIDATE_L1_PTES", 22, 22, &umr_bitfield_default }, + { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG1_REQ[] = { + { "PER_VMID_INVALIDATE_REQ", 0, 15, &umr_bitfield_default }, + { "FLUSH_TYPE", 16, 17, &umr_bitfield_default }, + { "INVALIDATE_L2_PTES", 18, 18, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE0", 19, 19, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE1", 20, 20, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE2", 21, 21, &umr_bitfield_default }, + { "INVALIDATE_L1_PTES", 22, 22, &umr_bitfield_default }, + { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG2_REQ[] = { + { "PER_VMID_INVALIDATE_REQ", 0, 15, &umr_bitfield_default }, + { "FLUSH_TYPE", 16, 17, &umr_bitfield_default }, + { "INVALIDATE_L2_PTES", 18, 18, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE0", 19, 19, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE1", 20, 20, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE2", 21, 21, &umr_bitfield_default }, + { "INVALIDATE_L1_PTES", 22, 22, &umr_bitfield_default }, + { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG3_REQ[] = { + { "PER_VMID_INVALIDATE_REQ", 0, 15, &umr_bitfield_default }, + { "FLUSH_TYPE", 16, 17, &umr_bitfield_default }, + { "INVALIDATE_L2_PTES", 18, 18, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE0", 19, 19, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE1", 20, 20, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE2", 21, 21, &umr_bitfield_default }, + { "INVALIDATE_L1_PTES", 22, 22, &umr_bitfield_default }, + { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG4_REQ[] = { + { "PER_VMID_INVALIDATE_REQ", 0, 15, &umr_bitfield_default }, + { "FLUSH_TYPE", 16, 17, &umr_bitfield_default }, + { "INVALIDATE_L2_PTES", 18, 18, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE0", 19, 19, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE1", 20, 20, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE2", 21, 21, &umr_bitfield_default }, + { "INVALIDATE_L1_PTES", 22, 22, &umr_bitfield_default }, + { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG5_REQ[] = { + { "PER_VMID_INVALIDATE_REQ", 0, 15, &umr_bitfield_default }, + { "FLUSH_TYPE", 16, 17, &umr_bitfield_default }, + { "INVALIDATE_L2_PTES", 18, 18, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE0", 19, 19, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE1", 20, 20, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE2", 21, 21, &umr_bitfield_default }, + { "INVALIDATE_L1_PTES", 22, 22, &umr_bitfield_default }, + { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG6_REQ[] = { + { "PER_VMID_INVALIDATE_REQ", 0, 15, &umr_bitfield_default }, + { "FLUSH_TYPE", 16, 17, &umr_bitfield_default }, + { "INVALIDATE_L2_PTES", 18, 18, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE0", 19, 19, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE1", 20, 20, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE2", 21, 21, &umr_bitfield_default }, + { "INVALIDATE_L1_PTES", 22, 22, &umr_bitfield_default }, + { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG7_REQ[] = { + { "PER_VMID_INVALIDATE_REQ", 0, 15, &umr_bitfield_default }, + { "FLUSH_TYPE", 16, 17, &umr_bitfield_default }, + { "INVALIDATE_L2_PTES", 18, 18, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE0", 19, 19, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE1", 20, 20, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE2", 21, 21, &umr_bitfield_default }, + { "INVALIDATE_L1_PTES", 22, 22, &umr_bitfield_default }, + { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG8_REQ[] = { + { "PER_VMID_INVALIDATE_REQ", 0, 15, &umr_bitfield_default }, + { "FLUSH_TYPE", 16, 17, &umr_bitfield_default }, + { "INVALIDATE_L2_PTES", 18, 18, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE0", 19, 19, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE1", 20, 20, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE2", 21, 21, &umr_bitfield_default }, + { "INVALIDATE_L1_PTES", 22, 22, &umr_bitfield_default }, + { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG9_REQ[] = { + { "PER_VMID_INVALIDATE_REQ", 0, 15, &umr_bitfield_default }, + { "FLUSH_TYPE", 16, 17, &umr_bitfield_default }, + { "INVALIDATE_L2_PTES", 18, 18, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE0", 19, 19, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE1", 20, 20, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE2", 21, 21, &umr_bitfield_default }, + { "INVALIDATE_L1_PTES", 22, 22, &umr_bitfield_default }, + { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG10_REQ[] = { + { "PER_VMID_INVALIDATE_REQ", 0, 15, &umr_bitfield_default }, + { "FLUSH_TYPE", 16, 17, &umr_bitfield_default }, + { "INVALIDATE_L2_PTES", 18, 18, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE0", 19, 19, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE1", 20, 20, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE2", 21, 21, &umr_bitfield_default }, + { "INVALIDATE_L1_PTES", 22, 22, &umr_bitfield_default }, + { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG11_REQ[] = { + { "PER_VMID_INVALIDATE_REQ", 0, 15, &umr_bitfield_default }, + { "FLUSH_TYPE", 16, 17, &umr_bitfield_default }, + { "INVALIDATE_L2_PTES", 18, 18, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE0", 19, 19, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE1", 20, 20, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE2", 21, 21, &umr_bitfield_default }, + { "INVALIDATE_L1_PTES", 22, 22, &umr_bitfield_default }, + { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG12_REQ[] = { + { "PER_VMID_INVALIDATE_REQ", 0, 15, &umr_bitfield_default }, + { "FLUSH_TYPE", 16, 17, &umr_bitfield_default }, + { "INVALIDATE_L2_PTES", 18, 18, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE0", 19, 19, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE1", 20, 20, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE2", 21, 21, &umr_bitfield_default }, + { "INVALIDATE_L1_PTES", 22, 22, &umr_bitfield_default }, + { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG13_REQ[] = { + { "PER_VMID_INVALIDATE_REQ", 0, 15, &umr_bitfield_default }, + { "FLUSH_TYPE", 16, 17, &umr_bitfield_default }, + { "INVALIDATE_L2_PTES", 18, 18, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE0", 19, 19, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE1", 20, 20, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE2", 21, 21, &umr_bitfield_default }, + { "INVALIDATE_L1_PTES", 22, 22, &umr_bitfield_default }, + { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG14_REQ[] = { + { "PER_VMID_INVALIDATE_REQ", 0, 15, &umr_bitfield_default }, + { "FLUSH_TYPE", 16, 17, &umr_bitfield_default }, + { "INVALIDATE_L2_PTES", 18, 18, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE0", 19, 19, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE1", 20, 20, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE2", 21, 21, &umr_bitfield_default }, + { "INVALIDATE_L1_PTES", 22, 22, &umr_bitfield_default }, + { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG15_REQ[] = { + { "PER_VMID_INVALIDATE_REQ", 0, 15, &umr_bitfield_default }, + { "FLUSH_TYPE", 16, 17, &umr_bitfield_default }, + { "INVALIDATE_L2_PTES", 18, 18, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE0", 19, 19, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE1", 20, 20, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE2", 21, 21, &umr_bitfield_default }, + { "INVALIDATE_L1_PTES", 22, 22, &umr_bitfield_default }, + { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG16_REQ[] = { + { "PER_VMID_INVALIDATE_REQ", 0, 15, &umr_bitfield_default }, + { "FLUSH_TYPE", 16, 17, &umr_bitfield_default }, + { "INVALIDATE_L2_PTES", 18, 18, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE0", 19, 19, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE1", 20, 20, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE2", 21, 21, &umr_bitfield_default }, + { "INVALIDATE_L1_PTES", 22, 22, &umr_bitfield_default }, + { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG17_REQ[] = { + { "PER_VMID_INVALIDATE_REQ", 0, 15, &umr_bitfield_default }, + { "FLUSH_TYPE", 16, 17, &umr_bitfield_default }, + { "INVALIDATE_L2_PTES", 18, 18, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE0", 19, 19, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE1", 20, 20, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE2", 21, 21, &umr_bitfield_default }, + { "INVALIDATE_L1_PTES", 22, 22, &umr_bitfield_default }, + { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG0_ACK[] = { + { "PER_VMID_INVALIDATE_ACK", 0, 15, &umr_bitfield_default }, + { "SEMAPHORE", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG1_ACK[] = { + { "PER_VMID_INVALIDATE_ACK", 0, 15, &umr_bitfield_default }, + { "SEMAPHORE", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG2_ACK[] = { + { "PER_VMID_INVALIDATE_ACK", 0, 15, &umr_bitfield_default }, + { "SEMAPHORE", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG3_ACK[] = { + { "PER_VMID_INVALIDATE_ACK", 0, 15, &umr_bitfield_default }, + { "SEMAPHORE", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG4_ACK[] = { + { "PER_VMID_INVALIDATE_ACK", 0, 15, &umr_bitfield_default }, + { "SEMAPHORE", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG5_ACK[] = { + { "PER_VMID_INVALIDATE_ACK", 0, 15, &umr_bitfield_default }, + { "SEMAPHORE", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG6_ACK[] = { + { "PER_VMID_INVALIDATE_ACK", 0, 15, &umr_bitfield_default }, + { "SEMAPHORE", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG7_ACK[] = { + { "PER_VMID_INVALIDATE_ACK", 0, 15, &umr_bitfield_default }, + { "SEMAPHORE", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG8_ACK[] = { + { "PER_VMID_INVALIDATE_ACK", 0, 15, &umr_bitfield_default }, + { "SEMAPHORE", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG9_ACK[] = { + { "PER_VMID_INVALIDATE_ACK", 0, 15, &umr_bitfield_default }, + { "SEMAPHORE", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG10_ACK[] = { + { "PER_VMID_INVALIDATE_ACK", 0, 15, &umr_bitfield_default }, + { "SEMAPHORE", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG11_ACK[] = { + { "PER_VMID_INVALIDATE_ACK", 0, 15, &umr_bitfield_default }, + { "SEMAPHORE", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG12_ACK[] = { + { "PER_VMID_INVALIDATE_ACK", 0, 15, &umr_bitfield_default }, + { "SEMAPHORE", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG13_ACK[] = { + { "PER_VMID_INVALIDATE_ACK", 0, 15, &umr_bitfield_default }, + { "SEMAPHORE", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG14_ACK[] = { + { "PER_VMID_INVALIDATE_ACK", 0, 15, &umr_bitfield_default }, + { "SEMAPHORE", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG15_ACK[] = { + { "PER_VMID_INVALIDATE_ACK", 0, 15, &umr_bitfield_default }, + { "SEMAPHORE", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG16_ACK[] = { + { "PER_VMID_INVALIDATE_ACK", 0, 15, &umr_bitfield_default }, + { "SEMAPHORE", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG17_ACK[] = { + { "PER_VMID_INVALIDATE_ACK", 0, 15, &umr_bitfield_default }, + { "SEMAPHORE", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32[] = { + { "S_BIT", 0, 0, &umr_bitfield_default }, + { "LOGI_PAGE_ADDR_RANGE_LO31", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32[] = { + { "LOGI_PAGE_ADDR_RANGE_HI5", 0, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32[] = { + { "S_BIT", 0, 0, &umr_bitfield_default }, + { "LOGI_PAGE_ADDR_RANGE_LO31", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG1_ADDR_RANGE_HI32[] = { + { "LOGI_PAGE_ADDR_RANGE_HI5", 0, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG2_ADDR_RANGE_LO32[] = { + { "S_BIT", 0, 0, &umr_bitfield_default }, + { "LOGI_PAGE_ADDR_RANGE_LO31", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG2_ADDR_RANGE_HI32[] = { + { "LOGI_PAGE_ADDR_RANGE_HI5", 0, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG3_ADDR_RANGE_LO32[] = { + { "S_BIT", 0, 0, &umr_bitfield_default }, + { "LOGI_PAGE_ADDR_RANGE_LO31", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG3_ADDR_RANGE_HI32[] = { + { "LOGI_PAGE_ADDR_RANGE_HI5", 0, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG4_ADDR_RANGE_LO32[] = { + { "S_BIT", 0, 0, &umr_bitfield_default }, + { "LOGI_PAGE_ADDR_RANGE_LO31", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG4_ADDR_RANGE_HI32[] = { + { "LOGI_PAGE_ADDR_RANGE_HI5", 0, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG5_ADDR_RANGE_LO32[] = { + { "S_BIT", 0, 0, &umr_bitfield_default }, + { "LOGI_PAGE_ADDR_RANGE_LO31", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG5_ADDR_RANGE_HI32[] = { + { "LOGI_PAGE_ADDR_RANGE_HI5", 0, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG6_ADDR_RANGE_LO32[] = { + { "S_BIT", 0, 0, &umr_bitfield_default }, + { "LOGI_PAGE_ADDR_RANGE_LO31", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG6_ADDR_RANGE_HI32[] = { + { "LOGI_PAGE_ADDR_RANGE_HI5", 0, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG7_ADDR_RANGE_LO32[] = { + { "S_BIT", 0, 0, &umr_bitfield_default }, + { "LOGI_PAGE_ADDR_RANGE_LO31", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG7_ADDR_RANGE_HI32[] = { + { "LOGI_PAGE_ADDR_RANGE_HI5", 0, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG8_ADDR_RANGE_LO32[] = { + { "S_BIT", 0, 0, &umr_bitfield_default }, + { "LOGI_PAGE_ADDR_RANGE_LO31", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG8_ADDR_RANGE_HI32[] = { + { "LOGI_PAGE_ADDR_RANGE_HI5", 0, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG9_ADDR_RANGE_LO32[] = { + { "S_BIT", 0, 0, &umr_bitfield_default }, + { "LOGI_PAGE_ADDR_RANGE_LO31", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG9_ADDR_RANGE_HI32[] = { + { "LOGI_PAGE_ADDR_RANGE_HI5", 0, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG10_ADDR_RANGE_LO32[] = { + { "S_BIT", 0, 0, &umr_bitfield_default }, + { "LOGI_PAGE_ADDR_RANGE_LO31", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG10_ADDR_RANGE_HI32[] = { + { "LOGI_PAGE_ADDR_RANGE_HI5", 0, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG11_ADDR_RANGE_LO32[] = { + { "S_BIT", 0, 0, &umr_bitfield_default }, + { "LOGI_PAGE_ADDR_RANGE_LO31", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG11_ADDR_RANGE_HI32[] = { + { "LOGI_PAGE_ADDR_RANGE_HI5", 0, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG12_ADDR_RANGE_LO32[] = { + { "S_BIT", 0, 0, &umr_bitfield_default }, + { "LOGI_PAGE_ADDR_RANGE_LO31", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG12_ADDR_RANGE_HI32[] = { + { "LOGI_PAGE_ADDR_RANGE_HI5", 0, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG13_ADDR_RANGE_LO32[] = { + { "S_BIT", 0, 0, &umr_bitfield_default }, + { "LOGI_PAGE_ADDR_RANGE_LO31", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG13_ADDR_RANGE_HI32[] = { + { "LOGI_PAGE_ADDR_RANGE_HI5", 0, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG14_ADDR_RANGE_LO32[] = { + { "S_BIT", 0, 0, &umr_bitfield_default }, + { "LOGI_PAGE_ADDR_RANGE_LO31", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG14_ADDR_RANGE_HI32[] = { + { "LOGI_PAGE_ADDR_RANGE_HI5", 0, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG15_ADDR_RANGE_LO32[] = { + { "S_BIT", 0, 0, &umr_bitfield_default }, + { "LOGI_PAGE_ADDR_RANGE_LO31", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG15_ADDR_RANGE_HI32[] = { + { "LOGI_PAGE_ADDR_RANGE_HI5", 0, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG16_ADDR_RANGE_LO32[] = { + { "S_BIT", 0, 0, &umr_bitfield_default }, + { "LOGI_PAGE_ADDR_RANGE_LO31", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG16_ADDR_RANGE_HI32[] = { + { "LOGI_PAGE_ADDR_RANGE_HI5", 0, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG17_ADDR_RANGE_LO32[] = { + { "S_BIT", 0, 0, &umr_bitfield_default }, + { "LOGI_PAGE_ADDR_RANGE_LO31", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG17_ADDR_RANGE_HI32[] = { + { "LOGI_PAGE_ADDR_RANGE_HI5", 0, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32[] = { + { "PAGE_DIRECTORY_ENTRY_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32[] = { + { "PAGE_DIRECTORY_ENTRY_HI32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32[] = { + { "PAGE_DIRECTORY_ENTRY_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32[] = { + { "PAGE_DIRECTORY_ENTRY_HI32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32[] = { + { "PAGE_DIRECTORY_ENTRY_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32[] = { + { "PAGE_DIRECTORY_ENTRY_HI32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32[] = { + { "PAGE_DIRECTORY_ENTRY_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32[] = { + { "PAGE_DIRECTORY_ENTRY_HI32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32[] = { + { "PAGE_DIRECTORY_ENTRY_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32[] = { + { "PAGE_DIRECTORY_ENTRY_HI32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32[] = { + { "PAGE_DIRECTORY_ENTRY_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32[] = { + { "PAGE_DIRECTORY_ENTRY_HI32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32[] = { + { "PAGE_DIRECTORY_ENTRY_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32[] = { + { "PAGE_DIRECTORY_ENTRY_HI32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32[] = { + { "PAGE_DIRECTORY_ENTRY_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32[] = { + { "PAGE_DIRECTORY_ENTRY_HI32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32[] = { + { "PAGE_DIRECTORY_ENTRY_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32[] = { + { "PAGE_DIRECTORY_ENTRY_HI32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32[] = { + { "PAGE_DIRECTORY_ENTRY_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32[] = { + { "PAGE_DIRECTORY_ENTRY_HI32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32[] = { + { "PAGE_DIRECTORY_ENTRY_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32[] = { + { "PAGE_DIRECTORY_ENTRY_HI32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32[] = { + { "PAGE_DIRECTORY_ENTRY_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32[] = { + { "PAGE_DIRECTORY_ENTRY_HI32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32[] = { + { "PAGE_DIRECTORY_ENTRY_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32[] = { + { "PAGE_DIRECTORY_ENTRY_HI32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32[] = { + { "PAGE_DIRECTORY_ENTRY_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32[] = { + { "PAGE_DIRECTORY_ENTRY_HI32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32[] = { + { "PAGE_DIRECTORY_ENTRY_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32[] = { + { "PAGE_DIRECTORY_ENTRY_HI32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32[] = { + { "PAGE_DIRECTORY_ENTRY_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32[] = { + { "PAGE_DIRECTORY_ENTRY_HI32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_NB_MMIOBASE[] = { + { "MMIOBASE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_NB_MMIOLIMIT[] = { + { "MMIOLIMIT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_NB_PCI_CTRL[] = { + { "MMIOENABLE", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_NB_PCI_ARB[] = { + { "VGA_HOLE", 3, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_NB_TOP_OF_DRAM_SLOT1[] = { + { "TOP_OF_DRAM", 23, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_NB_LOWER_TOP_OF_DRAM2[] = { + { "ENABLE", 0, 0, &umr_bitfield_default }, + { "LOWER_TOM2", 23, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_NB_UPPER_TOP_OF_DRAM2[] = { + { "UPPER_TOM2", 0, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_FB_OFFSET[] = { + { "FB_OFFSET", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB[] = { + { "PHYSICAL_PAGE_NUMBER_LSB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB[] = { + { "PHYSICAL_PAGE_NUMBER_MSB", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_STEERING[] = { + { "DEFAULT_STEERING", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_SHARED_VIRT_RESET_REQ[] = { + { "VF", 0, 15, &umr_bitfield_default }, + { "PF", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_MEM_POWER_LS[] = { + { "LS_SETUP", 0, 5, &umr_bitfield_default }, + { "LS_HOLD", 6, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_CACHEABLE_DRAM_ADDRESS_START[] = { + { "ADDRESS", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_CACHEABLE_DRAM_ADDRESS_END[] = { + { "ADDRESS", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_APT_CNTL[] = { + { "FORCE_MTYPE_UC", 0, 0, &umr_bitfield_default }, + { "DIRECT_SYSTEM_EN", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_LOCAL_HBM_ADDRESS_START[] = { + { "ADDRESS", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_LOCAL_HBM_ADDRESS_END[] = { + { "ADDRESS", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL[] = { + { "LOCK", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_FB_LOCATION_BASE[] = { + { "FB_BASE", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_FB_LOCATION_TOP[] = { + { "FB_TOP", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_AGP_TOP[] = { + { "AGP_TOP", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_AGP_BOT[] = { + { "AGP_BOT", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_AGP_BASE[] = { + { "AGP_BASE", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_SYSTEM_APERTURE_LOW_ADDR[] = { + { "LOGICAL_ADDR", 0, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR[] = { + { "LOGICAL_ADDR", 0, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_MX_L1_TLB_CNTL[] = { + { "ENABLE_L1_TLB", 0, 0, &umr_bitfield_default }, + { "SYSTEM_ACCESS_MODE", 3, 4, &umr_bitfield_default }, + { "SYSTEM_APERTURE_UNMAPPED_ACCESS", 5, 5, &umr_bitfield_default }, + { "ENABLE_ADVANCED_DRIVER_MODEL", 6, 6, &umr_bitfield_default }, + { "ECO_BITS", 7, 10, &umr_bitfield_default }, + { "MTYPE", 11, 12, &umr_bitfield_default }, + { "ATC_EN", 13, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_DRAM_RD_CLI2GRP_MAP0[] = { + { "CID0_GROUP", 0, 1, &umr_bitfield_default }, + { "CID1_GROUP", 2, 3, &umr_bitfield_default }, + { "CID2_GROUP", 4, 5, &umr_bitfield_default }, + { "CID3_GROUP", 6, 7, &umr_bitfield_default }, + { "CID4_GROUP", 8, 9, &umr_bitfield_default }, + { "CID5_GROUP", 10, 11, &umr_bitfield_default }, + { "CID6_GROUP", 12, 13, &umr_bitfield_default }, + { "CID7_GROUP", 14, 15, &umr_bitfield_default }, + { "CID8_GROUP", 16, 17, &umr_bitfield_default }, + { "CID9_GROUP", 18, 19, &umr_bitfield_default }, + { "CID10_GROUP", 20, 21, &umr_bitfield_default }, + { "CID11_GROUP", 22, 23, &umr_bitfield_default }, + { "CID12_GROUP", 24, 25, &umr_bitfield_default }, + { "CID13_GROUP", 26, 27, &umr_bitfield_default }, + { "CID14_GROUP", 28, 29, &umr_bitfield_default }, + { "CID15_GROUP", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_DRAM_RD_CLI2GRP_MAP1[] = { + { "CID16_GROUP", 0, 1, &umr_bitfield_default }, + { "CID17_GROUP", 2, 3, &umr_bitfield_default }, + { "CID18_GROUP", 4, 5, &umr_bitfield_default }, + { "CID19_GROUP", 6, 7, &umr_bitfield_default }, + { "CID20_GROUP", 8, 9, &umr_bitfield_default }, + { "CID21_GROUP", 10, 11, &umr_bitfield_default }, + { "CID22_GROUP", 12, 13, &umr_bitfield_default }, + { "CID23_GROUP", 14, 15, &umr_bitfield_default }, + { "CID24_GROUP", 16, 17, &umr_bitfield_default }, + { "CID25_GROUP", 18, 19, &umr_bitfield_default }, + { "CID26_GROUP", 20, 21, &umr_bitfield_default }, + { "CID27_GROUP", 22, 23, &umr_bitfield_default }, + { "CID28_GROUP", 24, 25, &umr_bitfield_default }, + { "CID29_GROUP", 26, 27, &umr_bitfield_default }, + { "CID30_GROUP", 28, 29, &umr_bitfield_default }, + { "CID31_GROUP", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_DRAM_WR_CLI2GRP_MAP0[] = { + { "CID0_GROUP", 0, 1, &umr_bitfield_default }, + { "CID1_GROUP", 2, 3, &umr_bitfield_default }, + { "CID2_GROUP", 4, 5, &umr_bitfield_default }, + { "CID3_GROUP", 6, 7, &umr_bitfield_default }, + { "CID4_GROUP", 8, 9, &umr_bitfield_default }, + { "CID5_GROUP", 10, 11, &umr_bitfield_default }, + { "CID6_GROUP", 12, 13, &umr_bitfield_default }, + { "CID7_GROUP", 14, 15, &umr_bitfield_default }, + { "CID8_GROUP", 16, 17, &umr_bitfield_default }, + { "CID9_GROUP", 18, 19, &umr_bitfield_default }, + { "CID10_GROUP", 20, 21, &umr_bitfield_default }, + { "CID11_GROUP", 22, 23, &umr_bitfield_default }, + { "CID12_GROUP", 24, 25, &umr_bitfield_default }, + { "CID13_GROUP", 26, 27, &umr_bitfield_default }, + { "CID14_GROUP", 28, 29, &umr_bitfield_default }, + { "CID15_GROUP", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_DRAM_WR_CLI2GRP_MAP1[] = { + { "CID16_GROUP", 0, 1, &umr_bitfield_default }, + { "CID17_GROUP", 2, 3, &umr_bitfield_default }, + { "CID18_GROUP", 4, 5, &umr_bitfield_default }, + { "CID19_GROUP", 6, 7, &umr_bitfield_default }, + { "CID20_GROUP", 8, 9, &umr_bitfield_default }, + { "CID21_GROUP", 10, 11, &umr_bitfield_default }, + { "CID22_GROUP", 12, 13, &umr_bitfield_default }, + { "CID23_GROUP", 14, 15, &umr_bitfield_default }, + { "CID24_GROUP", 16, 17, &umr_bitfield_default }, + { "CID25_GROUP", 18, 19, &umr_bitfield_default }, + { "CID26_GROUP", 20, 21, &umr_bitfield_default }, + { "CID27_GROUP", 22, 23, &umr_bitfield_default }, + { "CID28_GROUP", 24, 25, &umr_bitfield_default }, + { "CID29_GROUP", 26, 27, &umr_bitfield_default }, + { "CID30_GROUP", 28, 29, &umr_bitfield_default }, + { "CID31_GROUP", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_DRAM_RD_GRP2VC_MAP[] = { + { "GROUP0_VC", 0, 2, &umr_bitfield_default }, + { "GROUP1_VC", 3, 5, &umr_bitfield_default }, + { "GROUP2_VC", 6, 8, &umr_bitfield_default }, + { "GROUP3_VC", 9, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_DRAM_WR_GRP2VC_MAP[] = { + { "GROUP0_VC", 0, 2, &umr_bitfield_default }, + { "GROUP1_VC", 3, 5, &umr_bitfield_default }, + { "GROUP2_VC", 6, 8, &umr_bitfield_default }, + { "GROUP3_VC", 9, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_DRAM_RD_LAZY[] = { + { "GROUP0_DELAY", 0, 2, &umr_bitfield_default }, + { "GROUP1_DELAY", 3, 5, &umr_bitfield_default }, + { "GROUP2_DELAY", 6, 8, &umr_bitfield_default }, + { "GROUP3_DELAY", 9, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_DRAM_WR_LAZY[] = { + { "GROUP0_DELAY", 0, 2, &umr_bitfield_default }, + { "GROUP1_DELAY", 3, 5, &umr_bitfield_default }, + { "GROUP2_DELAY", 6, 8, &umr_bitfield_default }, + { "GROUP3_DELAY", 9, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_DRAM_RD_CAM_CNTL[] = { + { "DEPTH_GROUP0", 0, 3, &umr_bitfield_default }, + { "DEPTH_GROUP1", 4, 7, &umr_bitfield_default }, + { "DEPTH_GROUP2", 8, 11, &umr_bitfield_default }, + { "DEPTH_GROUP3", 12, 15, &umr_bitfield_default }, + { "REORDER_LIMIT_GROUP0", 16, 18, &umr_bitfield_default }, + { "REORDER_LIMIT_GROUP1", 19, 21, &umr_bitfield_default }, + { "REORDER_LIMIT_GROUP2", 22, 24, &umr_bitfield_default }, + { "REORDER_LIMIT_GROUP3", 25, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_DRAM_WR_CAM_CNTL[] = { + { "DEPTH_GROUP0", 0, 3, &umr_bitfield_default }, + { "DEPTH_GROUP1", 4, 7, &umr_bitfield_default }, + { "DEPTH_GROUP2", 8, 11, &umr_bitfield_default }, + { "DEPTH_GROUP3", 12, 15, &umr_bitfield_default }, + { "REORDER_LIMIT_GROUP0", 16, 18, &umr_bitfield_default }, + { "REORDER_LIMIT_GROUP1", 19, 21, &umr_bitfield_default }, + { "REORDER_LIMIT_GROUP2", 22, 24, &umr_bitfield_default }, + { "REORDER_LIMIT_GROUP3", 25, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_DRAM_PAGE_BURST[] = { + { "RD_LIMIT_LO", 0, 7, &umr_bitfield_default }, + { "RD_LIMIT_HI", 8, 15, &umr_bitfield_default }, + { "WR_LIMIT_LO", 16, 23, &umr_bitfield_default }, + { "WR_LIMIT_HI", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_DRAM_RD_PRI_AGE[] = { + { "GROUP0_AGING_RATE", 0, 2, &umr_bitfield_default }, + { "GROUP1_AGING_RATE", 3, 5, &umr_bitfield_default }, + { "GROUP2_AGING_RATE", 6, 8, &umr_bitfield_default }, + { "GROUP3_AGING_RATE", 9, 11, &umr_bitfield_default }, + { "GROUP0_AGE_COEFFICIENT", 12, 14, &umr_bitfield_default }, + { "GROUP1_AGE_COEFFICIENT", 15, 17, &umr_bitfield_default }, + { "GROUP2_AGE_COEFFICIENT", 18, 20, &umr_bitfield_default }, + { "GROUP3_AGE_COEFFICIENT", 21, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_DRAM_WR_PRI_AGE[] = { + { "GROUP0_AGING_RATE", 0, 2, &umr_bitfield_default }, + { "GROUP1_AGING_RATE", 3, 5, &umr_bitfield_default }, + { "GROUP2_AGING_RATE", 6, 8, &umr_bitfield_default }, + { "GROUP3_AGING_RATE", 9, 11, &umr_bitfield_default }, + { "GROUP0_AGE_COEFFICIENT", 12, 14, &umr_bitfield_default }, + { "GROUP1_AGE_COEFFICIENT", 15, 17, &umr_bitfield_default }, + { "GROUP2_AGE_COEFFICIENT", 18, 20, &umr_bitfield_default }, + { "GROUP3_AGE_COEFFICIENT", 21, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_DRAM_RD_PRI_QUEUING[] = { + { "GROUP0_QUEUING_COEFFICIENT", 0, 2, &umr_bitfield_default }, + { "GROUP1_QUEUING_COEFFICIENT", 3, 5, &umr_bitfield_default }, + { "GROUP2_QUEUING_COEFFICIENT", 6, 8, &umr_bitfield_default }, + { "GROUP3_QUEUING_COEFFICIENT", 9, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_DRAM_WR_PRI_QUEUING[] = { + { "GROUP0_QUEUING_COEFFICIENT", 0, 2, &umr_bitfield_default }, + { "GROUP1_QUEUING_COEFFICIENT", 3, 5, &umr_bitfield_default }, + { "GROUP2_QUEUING_COEFFICIENT", 6, 8, &umr_bitfield_default }, + { "GROUP3_QUEUING_COEFFICIENT", 9, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_DRAM_RD_PRI_FIXED[] = { + { "GROUP0_FIXED_COEFFICIENT", 0, 2, &umr_bitfield_default }, + { "GROUP1_FIXED_COEFFICIENT", 3, 5, &umr_bitfield_default }, + { "GROUP2_FIXED_COEFFICIENT", 6, 8, &umr_bitfield_default }, + { "GROUP3_FIXED_COEFFICIENT", 9, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_DRAM_WR_PRI_FIXED[] = { + { "GROUP0_FIXED_COEFFICIENT", 0, 2, &umr_bitfield_default }, + { "GROUP1_FIXED_COEFFICIENT", 3, 5, &umr_bitfield_default }, + { "GROUP2_FIXED_COEFFICIENT", 6, 8, &umr_bitfield_default }, + { "GROUP3_FIXED_COEFFICIENT", 9, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_DRAM_RD_PRI_URGENCY[] = { + { "GROUP0_URGENCY_COEFFICIENT", 0, 2, &umr_bitfield_default }, + { "GROUP1_URGENCY_COEFFICIENT", 3, 5, &umr_bitfield_default }, + { "GROUP2_URGENCY_COEFFICIENT", 6, 8, &umr_bitfield_default }, + { "GROUP3_URGENCY_COEFFICIENT", 9, 11, &umr_bitfield_default }, + { "GROUP0_URGENCY_MODE", 12, 12, &umr_bitfield_default }, + { "GROUP1_URGENCY_MODE", 13, 13, &umr_bitfield_default }, + { "GROUP2_URGENCY_MODE", 14, 14, &umr_bitfield_default }, + { "GROUP3_URGENCY_MODE", 15, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_DRAM_WR_PRI_URGENCY[] = { + { "GROUP0_URGENCY_COEFFICIENT", 0, 2, &umr_bitfield_default }, + { "GROUP1_URGENCY_COEFFICIENT", 3, 5, &umr_bitfield_default }, + { "GROUP2_URGENCY_COEFFICIENT", 6, 8, &umr_bitfield_default }, + { "GROUP3_URGENCY_COEFFICIENT", 9, 11, &umr_bitfield_default }, + { "GROUP0_URGENCY_MODE", 12, 12, &umr_bitfield_default }, + { "GROUP1_URGENCY_MODE", 13, 13, &umr_bitfield_default }, + { "GROUP2_URGENCY_MODE", 14, 14, &umr_bitfield_default }, + { "GROUP3_URGENCY_MODE", 15, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_DRAM_RD_PRI_QUANT_PRI1[] = { + { "GROUP0_THRESHOLD", 0, 7, &umr_bitfield_default }, + { "GROUP1_THRESHOLD", 8, 15, &umr_bitfield_default }, + { "GROUP2_THRESHOLD", 16, 23, &umr_bitfield_default }, + { "GROUP3_THRESHOLD", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_DRAM_RD_PRI_QUANT_PRI2[] = { + { "GROUP0_THRESHOLD", 0, 7, &umr_bitfield_default }, + { "GROUP1_THRESHOLD", 8, 15, &umr_bitfield_default }, + { "GROUP2_THRESHOLD", 16, 23, &umr_bitfield_default }, + { "GROUP3_THRESHOLD", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_DRAM_RD_PRI_QUANT_PRI3[] = { + { "GROUP0_THRESHOLD", 0, 7, &umr_bitfield_default }, + { "GROUP1_THRESHOLD", 8, 15, &umr_bitfield_default }, + { "GROUP2_THRESHOLD", 16, 23, &umr_bitfield_default }, + { "GROUP3_THRESHOLD", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_DRAM_WR_PRI_QUANT_PRI1[] = { + { "GROUP0_THRESHOLD", 0, 7, &umr_bitfield_default }, + { "GROUP1_THRESHOLD", 8, 15, &umr_bitfield_default }, + { "GROUP2_THRESHOLD", 16, 23, &umr_bitfield_default }, + { "GROUP3_THRESHOLD", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_DRAM_WR_PRI_QUANT_PRI2[] = { + { "GROUP0_THRESHOLD", 0, 7, &umr_bitfield_default }, + { "GROUP1_THRESHOLD", 8, 15, &umr_bitfield_default }, + { "GROUP2_THRESHOLD", 16, 23, &umr_bitfield_default }, + { "GROUP3_THRESHOLD", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_DRAM_WR_PRI_QUANT_PRI3[] = { + { "GROUP0_THRESHOLD", 0, 7, &umr_bitfield_default }, + { "GROUP1_THRESHOLD", 8, 15, &umr_bitfield_default }, + { "GROUP2_THRESHOLD", 16, 23, &umr_bitfield_default }, + { "GROUP3_THRESHOLD", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_ADDRNORM_BASE_ADDR0[] = { + { "ADDR_RNG_VAL", 0, 0, &umr_bitfield_default }, + { "LGCY_MMIO_HOLE_EN", 1, 1, &umr_bitfield_default }, + { "INTLV_NUM_CHAN", 4, 7, &umr_bitfield_default }, + { "INTLV_ADDR_SEL", 8, 10, &umr_bitfield_default }, + { "BASE_ADDR", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_ADDRNORM_LIMIT_ADDR0[] = { + { "DST_FABRIC_ID", 0, 3, &umr_bitfield_default }, + { "INTLV_NUM_SOCKETS", 8, 8, &umr_bitfield_default }, + { "INTLV_NUM_DIES", 10, 11, &umr_bitfield_default }, + { "LIMIT_ADDR", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_ADDRNORM_BASE_ADDR1[] = { + { "ADDR_RNG_VAL", 0, 0, &umr_bitfield_default }, + { "LGCY_MMIO_HOLE_EN", 1, 1, &umr_bitfield_default }, + { "INTLV_NUM_CHAN", 4, 7, &umr_bitfield_default }, + { "INTLV_ADDR_SEL", 8, 10, &umr_bitfield_default }, + { "BASE_ADDR", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_ADDRNORM_LIMIT_ADDR1[] = { + { "DST_FABRIC_ID", 0, 3, &umr_bitfield_default }, + { "INTLV_NUM_SOCKETS", 8, 8, &umr_bitfield_default }, + { "INTLV_NUM_DIES", 10, 11, &umr_bitfield_default }, + { "LIMIT_ADDR", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_ADDRNORM_OFFSET_ADDR1[] = { + { "HI_ADDR_OFFSET_EN", 0, 0, &umr_bitfield_default }, + { "HI_ADDR_OFFSET", 20, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_ADDRNORM_HOLE_CNTL[] = { + { "DRAM_HOLE_VALID", 0, 0, &umr_bitfield_default }, + { "DRAM_HOLE_OFFSET", 7, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_ADDRDEC_BANK_CFG[] = { + { "BANK_MASK_DRAM", 0, 4, &umr_bitfield_default }, + { "BANK_MASK_GMI", 5, 9, &umr_bitfield_default }, + { "BANKGROUP_SEL_DRAM", 10, 12, &umr_bitfield_default }, + { "BANKGROUP_SEL_GMI", 13, 15, &umr_bitfield_default }, + { "BANKGROUP_INTERLEAVE_DRAM", 16, 16, &umr_bitfield_default }, + { "BANKGROUP_INTERLEAVE_GMI", 17, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_ADDRDEC_MISC_CFG[] = { + { "VCM_EN0", 0, 0, &umr_bitfield_default }, + { "VCM_EN1", 1, 1, &umr_bitfield_default }, + { "VCM_EN2", 2, 2, &umr_bitfield_default }, + { "VCM_EN3", 3, 3, &umr_bitfield_default }, + { "VCM_EN4", 4, 4, &umr_bitfield_default }, + { "PCH_MASK_DRAM", 8, 8, &umr_bitfield_default }, + { "PCH_MASK_GMI", 9, 9, &umr_bitfield_default }, + { "CH_MASK_DRAM", 12, 15, &umr_bitfield_default }, + { "CH_MASK_GMI", 16, 19, &umr_bitfield_default }, + { "CS_MASK_DRAM", 20, 21, &umr_bitfield_default }, + { "CS_MASK_GMI", 22, 23, &umr_bitfield_default }, + { "RM_MASK_DRAM", 24, 26, &umr_bitfield_default }, + { "RM_MASK_GMI", 27, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK0[] = { + { "XOR_ENABLE", 0, 0, &umr_bitfield_default }, + { "COL_XOR", 1, 13, &umr_bitfield_default }, + { "ROW_XOR", 14, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK1[] = { + { "XOR_ENABLE", 0, 0, &umr_bitfield_default }, + { "COL_XOR", 1, 13, &umr_bitfield_default }, + { "ROW_XOR", 14, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK2[] = { + { "XOR_ENABLE", 0, 0, &umr_bitfield_default }, + { "COL_XOR", 1, 13, &umr_bitfield_default }, + { "ROW_XOR", 14, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK3[] = { + { "XOR_ENABLE", 0, 0, &umr_bitfield_default }, + { "COL_XOR", 1, 13, &umr_bitfield_default }, + { "ROW_XOR", 14, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK4[] = { + { "XOR_ENABLE", 0, 0, &umr_bitfield_default }, + { "COL_XOR", 1, 13, &umr_bitfield_default }, + { "ROW_XOR", 14, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_ADDRDECDRAM_ADDR_HASH_PC[] = { + { "XOR_ENABLE", 0, 0, &umr_bitfield_default }, + { "COL_XOR", 1, 13, &umr_bitfield_default }, + { "ROW_XOR", 14, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_ADDRDECDRAM_ADDR_HASH_PC2[] = { + { "BANK_XOR", 0, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_ADDRDECDRAM_ADDR_HASH_CS0[] = { + { "XOR_ENABLE", 0, 0, &umr_bitfield_default }, + { "NA_XOR", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_ADDRDECDRAM_ADDR_HASH_CS1[] = { + { "XOR_ENABLE", 0, 0, &umr_bitfield_default }, + { "NA_XOR", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_ADDRDECDRAM_HARVEST_ENABLE[] = { + { "FORCE_B3_EN", 0, 0, &umr_bitfield_default }, + { "FORCE_B3_VAL", 1, 1, &umr_bitfield_default }, + { "FORCE_B4_EN", 2, 2, &umr_bitfield_default }, + { "FORCE_B4_VAL", 3, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_ADDRDEC0_BASE_ADDR_CS0[] = { + { "CS_ENABLE", 0, 0, &umr_bitfield_default }, + { "BASE_ADDR", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_ADDRDEC0_BASE_ADDR_CS1[] = { + { "CS_ENABLE", 0, 0, &umr_bitfield_default }, + { "BASE_ADDR", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_ADDRDEC0_BASE_ADDR_CS2[] = { + { "CS_ENABLE", 0, 0, &umr_bitfield_default }, + { "BASE_ADDR", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_ADDRDEC0_BASE_ADDR_CS3[] = { + { "CS_ENABLE", 0, 0, &umr_bitfield_default }, + { "BASE_ADDR", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_ADDRDEC0_BASE_ADDR_SECCS0[] = { + { "CS_ENABLE", 0, 0, &umr_bitfield_default }, + { "BASE_ADDR", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_ADDRDEC0_BASE_ADDR_SECCS1[] = { + { "CS_ENABLE", 0, 0, &umr_bitfield_default }, + { "BASE_ADDR", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_ADDRDEC0_BASE_ADDR_SECCS2[] = { + { "CS_ENABLE", 0, 0, &umr_bitfield_default }, + { "BASE_ADDR", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_ADDRDEC0_BASE_ADDR_SECCS3[] = { + { "CS_ENABLE", 0, 0, &umr_bitfield_default }, + { "BASE_ADDR", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_ADDRDEC0_ADDR_MASK_CS01[] = { + { "ADDR_MASK", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_ADDRDEC0_ADDR_MASK_CS23[] = { + { "ADDR_MASK", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_ADDRDEC0_ADDR_MASK_SECCS01[] = { + { "ADDR_MASK", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_ADDRDEC0_ADDR_MASK_SECCS23[] = { + { "ADDR_MASK", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_ADDRDEC0_ADDR_CFG_CS01[] = { + { "NUM_BANK_GROUPS", 2, 3, &umr_bitfield_default }, + { "NUM_RM", 4, 5, &umr_bitfield_default }, + { "NUM_ROW_LO", 8, 11, &umr_bitfield_default }, + { "NUM_ROW_HI", 12, 15, &umr_bitfield_default }, + { "NUM_COL", 16, 19, &umr_bitfield_default }, + { "NUM_BANKS", 20, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_ADDRDEC0_ADDR_CFG_CS23[] = { + { "NUM_BANK_GROUPS", 2, 3, &umr_bitfield_default }, + { "NUM_RM", 4, 5, &umr_bitfield_default }, + { "NUM_ROW_LO", 8, 11, &umr_bitfield_default }, + { "NUM_ROW_HI", 12, 15, &umr_bitfield_default }, + { "NUM_COL", 16, 19, &umr_bitfield_default }, + { "NUM_BANKS", 20, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_ADDRDEC0_ADDR_SEL_CS01[] = { + { "BANK0", 0, 3, &umr_bitfield_default }, + { "BANK1", 4, 7, &umr_bitfield_default }, + { "BANK2", 8, 11, &umr_bitfield_default }, + { "BANK3", 12, 15, &umr_bitfield_default }, + { "BANK4", 16, 19, &umr_bitfield_default }, + { "ROW_LO", 24, 27, &umr_bitfield_default }, + { "ROW_HI", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_ADDRDEC0_ADDR_SEL_CS23[] = { + { "BANK0", 0, 3, &umr_bitfield_default }, + { "BANK1", 4, 7, &umr_bitfield_default }, + { "BANK2", 8, 11, &umr_bitfield_default }, + { "BANK3", 12, 15, &umr_bitfield_default }, + { "BANK4", 16, 19, &umr_bitfield_default }, + { "ROW_LO", 24, 27, &umr_bitfield_default }, + { "ROW_HI", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_ADDRDEC0_COL_SEL_LO_CS01[] = { + { "COL0", 0, 3, &umr_bitfield_default }, + { "COL1", 4, 7, &umr_bitfield_default }, + { "COL2", 8, 11, &umr_bitfield_default }, + { "COL3", 12, 15, &umr_bitfield_default }, + { "COL4", 16, 19, &umr_bitfield_default }, + { "COL5", 20, 23, &umr_bitfield_default }, + { "COL6", 24, 27, &umr_bitfield_default }, + { "COL7", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_ADDRDEC0_COL_SEL_LO_CS23[] = { + { "COL0", 0, 3, &umr_bitfield_default }, + { "COL1", 4, 7, &umr_bitfield_default }, + { "COL2", 8, 11, &umr_bitfield_default }, + { "COL3", 12, 15, &umr_bitfield_default }, + { "COL4", 16, 19, &umr_bitfield_default }, + { "COL5", 20, 23, &umr_bitfield_default }, + { "COL6", 24, 27, &umr_bitfield_default }, + { "COL7", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_ADDRDEC0_COL_SEL_HI_CS01[] = { + { "COL8", 0, 3, &umr_bitfield_default }, + { "COL9", 4, 7, &umr_bitfield_default }, + { "COL10", 8, 11, &umr_bitfield_default }, + { "COL11", 12, 15, &umr_bitfield_default }, + { "COL12", 16, 19, &umr_bitfield_default }, + { "COL13", 20, 23, &umr_bitfield_default }, + { "COL14", 24, 27, &umr_bitfield_default }, + { "COL15", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_ADDRDEC0_COL_SEL_HI_CS23[] = { + { "COL8", 0, 3, &umr_bitfield_default }, + { "COL9", 4, 7, &umr_bitfield_default }, + { "COL10", 8, 11, &umr_bitfield_default }, + { "COL11", 12, 15, &umr_bitfield_default }, + { "COL12", 16, 19, &umr_bitfield_default }, + { "COL13", 20, 23, &umr_bitfield_default }, + { "COL14", 24, 27, &umr_bitfield_default }, + { "COL15", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_ADDRDEC0_RM_SEL_CS01[] = { + { "RM0", 0, 3, &umr_bitfield_default }, + { "RM1", 4, 7, &umr_bitfield_default }, + { "RM2", 8, 11, &umr_bitfield_default }, + { "CHAN_BIT", 12, 15, &umr_bitfield_default }, + { "INVERT_ROW_MSBS_EVEN", 16, 17, &umr_bitfield_default }, + { "INVERT_ROW_MSBS_ODD", 18, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_ADDRDEC0_RM_SEL_CS23[] = { + { "RM0", 0, 3, &umr_bitfield_default }, + { "RM1", 4, 7, &umr_bitfield_default }, + { "RM2", 8, 11, &umr_bitfield_default }, + { "CHAN_BIT", 12, 15, &umr_bitfield_default }, + { "INVERT_ROW_MSBS_EVEN", 16, 17, &umr_bitfield_default }, + { "INVERT_ROW_MSBS_ODD", 18, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_ADDRDEC0_RM_SEL_SECCS01[] = { + { "RM0", 0, 3, &umr_bitfield_default }, + { "RM1", 4, 7, &umr_bitfield_default }, + { "RM2", 8, 11, &umr_bitfield_default }, + { "CHAN_BIT", 12, 15, &umr_bitfield_default }, + { "INVERT_ROW_MSBS_EVEN", 16, 17, &umr_bitfield_default }, + { "INVERT_ROW_MSBS_ODD", 18, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_ADDRDEC0_RM_SEL_SECCS23[] = { + { "RM0", 0, 3, &umr_bitfield_default }, + { "RM1", 4, 7, &umr_bitfield_default }, + { "RM2", 8, 11, &umr_bitfield_default }, + { "CHAN_BIT", 12, 15, &umr_bitfield_default }, + { "INVERT_ROW_MSBS_EVEN", 16, 17, &umr_bitfield_default }, + { "INVERT_ROW_MSBS_ODD", 18, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_ADDRDEC1_BASE_ADDR_CS0[] = { + { "CS_ENABLE", 0, 0, &umr_bitfield_default }, + { "BASE_ADDR", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_ADDRDEC1_BASE_ADDR_CS1[] = { + { "CS_ENABLE", 0, 0, &umr_bitfield_default }, + { "BASE_ADDR", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_ADDRDEC1_BASE_ADDR_CS2[] = { + { "CS_ENABLE", 0, 0, &umr_bitfield_default }, + { "BASE_ADDR", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_ADDRDEC1_BASE_ADDR_CS3[] = { + { "CS_ENABLE", 0, 0, &umr_bitfield_default }, + { "BASE_ADDR", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_ADDRDEC1_BASE_ADDR_SECCS0[] = { + { "CS_ENABLE", 0, 0, &umr_bitfield_default }, + { "BASE_ADDR", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_ADDRDEC1_BASE_ADDR_SECCS1[] = { + { "CS_ENABLE", 0, 0, &umr_bitfield_default }, + { "BASE_ADDR", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_ADDRDEC1_BASE_ADDR_SECCS2[] = { + { "CS_ENABLE", 0, 0, &umr_bitfield_default }, + { "BASE_ADDR", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_ADDRDEC1_BASE_ADDR_SECCS3[] = { + { "CS_ENABLE", 0, 0, &umr_bitfield_default }, + { "BASE_ADDR", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_ADDRDEC1_ADDR_MASK_CS01[] = { + { "ADDR_MASK", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_ADDRDEC1_ADDR_MASK_CS23[] = { + { "ADDR_MASK", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_ADDRDEC1_ADDR_MASK_SECCS01[] = { + { "ADDR_MASK", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_ADDRDEC1_ADDR_MASK_SECCS23[] = { + { "ADDR_MASK", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_ADDRDEC1_ADDR_CFG_CS01[] = { + { "NUM_BANK_GROUPS", 2, 3, &umr_bitfield_default }, + { "NUM_RM", 4, 5, &umr_bitfield_default }, + { "NUM_ROW_LO", 8, 11, &umr_bitfield_default }, + { "NUM_ROW_HI", 12, 15, &umr_bitfield_default }, + { "NUM_COL", 16, 19, &umr_bitfield_default }, + { "NUM_BANKS", 20, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_ADDRDEC1_ADDR_CFG_CS23[] = { + { "NUM_BANK_GROUPS", 2, 3, &umr_bitfield_default }, + { "NUM_RM", 4, 5, &umr_bitfield_default }, + { "NUM_ROW_LO", 8, 11, &umr_bitfield_default }, + { "NUM_ROW_HI", 12, 15, &umr_bitfield_default }, + { "NUM_COL", 16, 19, &umr_bitfield_default }, + { "NUM_BANKS", 20, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_ADDRDEC1_ADDR_SEL_CS01[] = { + { "BANK0", 0, 3, &umr_bitfield_default }, + { "BANK1", 4, 7, &umr_bitfield_default }, + { "BANK2", 8, 11, &umr_bitfield_default }, + { "BANK3", 12, 15, &umr_bitfield_default }, + { "BANK4", 16, 19, &umr_bitfield_default }, + { "ROW_LO", 24, 27, &umr_bitfield_default }, + { "ROW_HI", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_ADDRDEC1_ADDR_SEL_CS23[] = { + { "BANK0", 0, 3, &umr_bitfield_default }, + { "BANK1", 4, 7, &umr_bitfield_default }, + { "BANK2", 8, 11, &umr_bitfield_default }, + { "BANK3", 12, 15, &umr_bitfield_default }, + { "BANK4", 16, 19, &umr_bitfield_default }, + { "ROW_LO", 24, 27, &umr_bitfield_default }, + { "ROW_HI", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_ADDRDEC1_COL_SEL_LO_CS01[] = { + { "COL0", 0, 3, &umr_bitfield_default }, + { "COL1", 4, 7, &umr_bitfield_default }, + { "COL2", 8, 11, &umr_bitfield_default }, + { "COL3", 12, 15, &umr_bitfield_default }, + { "COL4", 16, 19, &umr_bitfield_default }, + { "COL5", 20, 23, &umr_bitfield_default }, + { "COL6", 24, 27, &umr_bitfield_default }, + { "COL7", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_ADDRDEC1_COL_SEL_LO_CS23[] = { + { "COL0", 0, 3, &umr_bitfield_default }, + { "COL1", 4, 7, &umr_bitfield_default }, + { "COL2", 8, 11, &umr_bitfield_default }, + { "COL3", 12, 15, &umr_bitfield_default }, + { "COL4", 16, 19, &umr_bitfield_default }, + { "COL5", 20, 23, &umr_bitfield_default }, + { "COL6", 24, 27, &umr_bitfield_default }, + { "COL7", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_ADDRDEC1_COL_SEL_HI_CS01[] = { + { "COL8", 0, 3, &umr_bitfield_default }, + { "COL9", 4, 7, &umr_bitfield_default }, + { "COL10", 8, 11, &umr_bitfield_default }, + { "COL11", 12, 15, &umr_bitfield_default }, + { "COL12", 16, 19, &umr_bitfield_default }, + { "COL13", 20, 23, &umr_bitfield_default }, + { "COL14", 24, 27, &umr_bitfield_default }, + { "COL15", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_ADDRDEC1_COL_SEL_HI_CS23[] = { + { "COL8", 0, 3, &umr_bitfield_default }, + { "COL9", 4, 7, &umr_bitfield_default }, + { "COL10", 8, 11, &umr_bitfield_default }, + { "COL11", 12, 15, &umr_bitfield_default }, + { "COL12", 16, 19, &umr_bitfield_default }, + { "COL13", 20, 23, &umr_bitfield_default }, + { "COL14", 24, 27, &umr_bitfield_default }, + { "COL15", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_ADDRDEC1_RM_SEL_CS01[] = { + { "RM0", 0, 3, &umr_bitfield_default }, + { "RM1", 4, 7, &umr_bitfield_default }, + { "RM2", 8, 11, &umr_bitfield_default }, + { "CHAN_BIT", 12, 15, &umr_bitfield_default }, + { "INVERT_ROW_MSBS_EVEN", 16, 17, &umr_bitfield_default }, + { "INVERT_ROW_MSBS_ODD", 18, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_ADDRDEC1_RM_SEL_CS23[] = { + { "RM0", 0, 3, &umr_bitfield_default }, + { "RM1", 4, 7, &umr_bitfield_default }, + { "RM2", 8, 11, &umr_bitfield_default }, + { "CHAN_BIT", 12, 15, &umr_bitfield_default }, + { "INVERT_ROW_MSBS_EVEN", 16, 17, &umr_bitfield_default }, + { "INVERT_ROW_MSBS_ODD", 18, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_ADDRDEC1_RM_SEL_SECCS01[] = { + { "RM0", 0, 3, &umr_bitfield_default }, + { "RM1", 4, 7, &umr_bitfield_default }, + { "RM2", 8, 11, &umr_bitfield_default }, + { "CHAN_BIT", 12, 15, &umr_bitfield_default }, + { "INVERT_ROW_MSBS_EVEN", 16, 17, &umr_bitfield_default }, + { "INVERT_ROW_MSBS_ODD", 18, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_ADDRDEC1_RM_SEL_SECCS23[] = { + { "RM0", 0, 3, &umr_bitfield_default }, + { "RM1", 4, 7, &umr_bitfield_default }, + { "RM2", 8, 11, &umr_bitfield_default }, + { "CHAN_BIT", 12, 15, &umr_bitfield_default }, + { "INVERT_ROW_MSBS_EVEN", 16, 17, &umr_bitfield_default }, + { "INVERT_ROW_MSBS_ODD", 18, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_IO_RD_CLI2GRP_MAP0[] = { + { "CID0_GROUP", 0, 1, &umr_bitfield_default }, + { "CID1_GROUP", 2, 3, &umr_bitfield_default }, + { "CID2_GROUP", 4, 5, &umr_bitfield_default }, + { "CID3_GROUP", 6, 7, &umr_bitfield_default }, + { "CID4_GROUP", 8, 9, &umr_bitfield_default }, + { "CID5_GROUP", 10, 11, &umr_bitfield_default }, + { "CID6_GROUP", 12, 13, &umr_bitfield_default }, + { "CID7_GROUP", 14, 15, &umr_bitfield_default }, + { "CID8_GROUP", 16, 17, &umr_bitfield_default }, + { "CID9_GROUP", 18, 19, &umr_bitfield_default }, + { "CID10_GROUP", 20, 21, &umr_bitfield_default }, + { "CID11_GROUP", 22, 23, &umr_bitfield_default }, + { "CID12_GROUP", 24, 25, &umr_bitfield_default }, + { "CID13_GROUP", 26, 27, &umr_bitfield_default }, + { "CID14_GROUP", 28, 29, &umr_bitfield_default }, + { "CID15_GROUP", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_IO_RD_CLI2GRP_MAP1[] = { + { "CID16_GROUP", 0, 1, &umr_bitfield_default }, + { "CID17_GROUP", 2, 3, &umr_bitfield_default }, + { "CID18_GROUP", 4, 5, &umr_bitfield_default }, + { "CID19_GROUP", 6, 7, &umr_bitfield_default }, + { "CID20_GROUP", 8, 9, &umr_bitfield_default }, + { "CID21_GROUP", 10, 11, &umr_bitfield_default }, + { "CID22_GROUP", 12, 13, &umr_bitfield_default }, + { "CID23_GROUP", 14, 15, &umr_bitfield_default }, + { "CID24_GROUP", 16, 17, &umr_bitfield_default }, + { "CID25_GROUP", 18, 19, &umr_bitfield_default }, + { "CID26_GROUP", 20, 21, &umr_bitfield_default }, + { "CID27_GROUP", 22, 23, &umr_bitfield_default }, + { "CID28_GROUP", 24, 25, &umr_bitfield_default }, + { "CID29_GROUP", 26, 27, &umr_bitfield_default }, + { "CID30_GROUP", 28, 29, &umr_bitfield_default }, + { "CID31_GROUP", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_IO_WR_CLI2GRP_MAP0[] = { + { "CID0_GROUP", 0, 1, &umr_bitfield_default }, + { "CID1_GROUP", 2, 3, &umr_bitfield_default }, + { "CID2_GROUP", 4, 5, &umr_bitfield_default }, + { "CID3_GROUP", 6, 7, &umr_bitfield_default }, + { "CID4_GROUP", 8, 9, &umr_bitfield_default }, + { "CID5_GROUP", 10, 11, &umr_bitfield_default }, + { "CID6_GROUP", 12, 13, &umr_bitfield_default }, + { "CID7_GROUP", 14, 15, &umr_bitfield_default }, + { "CID8_GROUP", 16, 17, &umr_bitfield_default }, + { "CID9_GROUP", 18, 19, &umr_bitfield_default }, + { "CID10_GROUP", 20, 21, &umr_bitfield_default }, + { "CID11_GROUP", 22, 23, &umr_bitfield_default }, + { "CID12_GROUP", 24, 25, &umr_bitfield_default }, + { "CID13_GROUP", 26, 27, &umr_bitfield_default }, + { "CID14_GROUP", 28, 29, &umr_bitfield_default }, + { "CID15_GROUP", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_IO_WR_CLI2GRP_MAP1[] = { + { "CID16_GROUP", 0, 1, &umr_bitfield_default }, + { "CID17_GROUP", 2, 3, &umr_bitfield_default }, + { "CID18_GROUP", 4, 5, &umr_bitfield_default }, + { "CID19_GROUP", 6, 7, &umr_bitfield_default }, + { "CID20_GROUP", 8, 9, &umr_bitfield_default }, + { "CID21_GROUP", 10, 11, &umr_bitfield_default }, + { "CID22_GROUP", 12, 13, &umr_bitfield_default }, + { "CID23_GROUP", 14, 15, &umr_bitfield_default }, + { "CID24_GROUP", 16, 17, &umr_bitfield_default }, + { "CID25_GROUP", 18, 19, &umr_bitfield_default }, + { "CID26_GROUP", 20, 21, &umr_bitfield_default }, + { "CID27_GROUP", 22, 23, &umr_bitfield_default }, + { "CID28_GROUP", 24, 25, &umr_bitfield_default }, + { "CID29_GROUP", 26, 27, &umr_bitfield_default }, + { "CID30_GROUP", 28, 29, &umr_bitfield_default }, + { "CID31_GROUP", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_IO_RD_COMBINE_FLUSH[] = { + { "GROUP0_TIMER", 0, 3, &umr_bitfield_default }, + { "GROUP1_TIMER", 4, 7, &umr_bitfield_default }, + { "GROUP2_TIMER", 8, 11, &umr_bitfield_default }, + { "GROUP3_TIMER", 12, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_IO_WR_COMBINE_FLUSH[] = { + { "GROUP0_TIMER", 0, 3, &umr_bitfield_default }, + { "GROUP1_TIMER", 4, 7, &umr_bitfield_default }, + { "GROUP2_TIMER", 8, 11, &umr_bitfield_default }, + { "GROUP3_TIMER", 12, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_IO_GROUP_BURST[] = { + { "RD_LIMIT_LO", 0, 7, &umr_bitfield_default }, + { "RD_LIMIT_HI", 8, 15, &umr_bitfield_default }, + { "WR_LIMIT_LO", 16, 23, &umr_bitfield_default }, + { "WR_LIMIT_HI", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_IO_RD_PRI_AGE[] = { + { "GROUP0_AGING_RATE", 0, 2, &umr_bitfield_default }, + { "GROUP1_AGING_RATE", 3, 5, &umr_bitfield_default }, + { "GROUP2_AGING_RATE", 6, 8, &umr_bitfield_default }, + { "GROUP3_AGING_RATE", 9, 11, &umr_bitfield_default }, + { "GROUP0_AGE_COEFFICIENT", 12, 14, &umr_bitfield_default }, + { "GROUP1_AGE_COEFFICIENT", 15, 17, &umr_bitfield_default }, + { "GROUP2_AGE_COEFFICIENT", 18, 20, &umr_bitfield_default }, + { "GROUP3_AGE_COEFFICIENT", 21, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_IO_WR_PRI_AGE[] = { + { "GROUP0_AGING_RATE", 0, 2, &umr_bitfield_default }, + { "GROUP1_AGING_RATE", 3, 5, &umr_bitfield_default }, + { "GROUP2_AGING_RATE", 6, 8, &umr_bitfield_default }, + { "GROUP3_AGING_RATE", 9, 11, &umr_bitfield_default }, + { "GROUP0_AGE_COEFFICIENT", 12, 14, &umr_bitfield_default }, + { "GROUP1_AGE_COEFFICIENT", 15, 17, &umr_bitfield_default }, + { "GROUP2_AGE_COEFFICIENT", 18, 20, &umr_bitfield_default }, + { "GROUP3_AGE_COEFFICIENT", 21, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_IO_RD_PRI_QUEUING[] = { + { "GROUP0_QUEUING_COEFFICIENT", 0, 2, &umr_bitfield_default }, + { "GROUP1_QUEUING_COEFFICIENT", 3, 5, &umr_bitfield_default }, + { "GROUP2_QUEUING_COEFFICIENT", 6, 8, &umr_bitfield_default }, + { "GROUP3_QUEUING_COEFFICIENT", 9, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_IO_WR_PRI_QUEUING[] = { + { "GROUP0_QUEUING_COEFFICIENT", 0, 2, &umr_bitfield_default }, + { "GROUP1_QUEUING_COEFFICIENT", 3, 5, &umr_bitfield_default }, + { "GROUP2_QUEUING_COEFFICIENT", 6, 8, &umr_bitfield_default }, + { "GROUP3_QUEUING_COEFFICIENT", 9, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_IO_RD_PRI_FIXED[] = { + { "GROUP0_FIXED_COEFFICIENT", 0, 2, &umr_bitfield_default }, + { "GROUP1_FIXED_COEFFICIENT", 3, 5, &umr_bitfield_default }, + { "GROUP2_FIXED_COEFFICIENT", 6, 8, &umr_bitfield_default }, + { "GROUP3_FIXED_COEFFICIENT", 9, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_IO_WR_PRI_FIXED[] = { + { "GROUP0_FIXED_COEFFICIENT", 0, 2, &umr_bitfield_default }, + { "GROUP1_FIXED_COEFFICIENT", 3, 5, &umr_bitfield_default }, + { "GROUP2_FIXED_COEFFICIENT", 6, 8, &umr_bitfield_default }, + { "GROUP3_FIXED_COEFFICIENT", 9, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_IO_RD_PRI_URGENCY[] = { + { "GROUP0_URGENCY_COEFFICIENT", 0, 2, &umr_bitfield_default }, + { "GROUP1_URGENCY_COEFFICIENT", 3, 5, &umr_bitfield_default }, + { "GROUP2_URGENCY_COEFFICIENT", 6, 8, &umr_bitfield_default }, + { "GROUP3_URGENCY_COEFFICIENT", 9, 11, &umr_bitfield_default }, + { "GROUP0_URGENCY_MODE", 12, 12, &umr_bitfield_default }, + { "GROUP1_URGENCY_MODE", 13, 13, &umr_bitfield_default }, + { "GROUP2_URGENCY_MODE", 14, 14, &umr_bitfield_default }, + { "GROUP3_URGENCY_MODE", 15, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_IO_WR_PRI_URGENCY[] = { + { "GROUP0_URGENCY_COEFFICIENT", 0, 2, &umr_bitfield_default }, + { "GROUP1_URGENCY_COEFFICIENT", 3, 5, &umr_bitfield_default }, + { "GROUP2_URGENCY_COEFFICIENT", 6, 8, &umr_bitfield_default }, + { "GROUP3_URGENCY_COEFFICIENT", 9, 11, &umr_bitfield_default }, + { "GROUP0_URGENCY_MODE", 12, 12, &umr_bitfield_default }, + { "GROUP1_URGENCY_MODE", 13, 13, &umr_bitfield_default }, + { "GROUP2_URGENCY_MODE", 14, 14, &umr_bitfield_default }, + { "GROUP3_URGENCY_MODE", 15, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_IO_RD_PRI_URGENCY_MASK[] = { + { "CID0_MASK", 0, 0, &umr_bitfield_default }, + { "CID1_MASK", 1, 1, &umr_bitfield_default }, + { "CID2_MASK", 2, 2, &umr_bitfield_default }, + { "CID3_MASK", 3, 3, &umr_bitfield_default }, + { "CID4_MASK", 4, 4, &umr_bitfield_default }, + { "CID5_MASK", 5, 5, &umr_bitfield_default }, + { "CID6_MASK", 6, 6, &umr_bitfield_default }, + { "CID7_MASK", 7, 7, &umr_bitfield_default }, + { "CID8_MASK", 8, 8, &umr_bitfield_default }, + { "CID9_MASK", 9, 9, &umr_bitfield_default }, + { "CID10_MASK", 10, 10, &umr_bitfield_default }, + { "CID11_MASK", 11, 11, &umr_bitfield_default }, + { "CID12_MASK", 12, 12, &umr_bitfield_default }, + { "CID13_MASK", 13, 13, &umr_bitfield_default }, + { "CID14_MASK", 14, 14, &umr_bitfield_default }, + { "CID15_MASK", 15, 15, &umr_bitfield_default }, + { "CID16_MASK", 16, 16, &umr_bitfield_default }, + { "CID17_MASK", 17, 17, &umr_bitfield_default }, + { "CID18_MASK", 18, 18, &umr_bitfield_default }, + { "CID19_MASK", 19, 19, &umr_bitfield_default }, + { "CID20_MASK", 20, 20, &umr_bitfield_default }, + { "CID21_MASK", 21, 21, &umr_bitfield_default }, + { "CID22_MASK", 22, 22, &umr_bitfield_default }, + { "CID23_MASK", 23, 23, &umr_bitfield_default }, + { "CID24_MASK", 24, 24, &umr_bitfield_default }, + { "CID25_MASK", 25, 25, &umr_bitfield_default }, + { "CID26_MASK", 26, 26, &umr_bitfield_default }, + { "CID27_MASK", 27, 27, &umr_bitfield_default }, + { "CID28_MASK", 28, 28, &umr_bitfield_default }, + { "CID29_MASK", 29, 29, &umr_bitfield_default }, + { "CID30_MASK", 30, 30, &umr_bitfield_default }, + { "CID31_MASK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_IO_WR_PRI_URGENCY_MASK[] = { + { "CID0_MASK", 0, 0, &umr_bitfield_default }, + { "CID1_MASK", 1, 1, &umr_bitfield_default }, + { "CID2_MASK", 2, 2, &umr_bitfield_default }, + { "CID3_MASK", 3, 3, &umr_bitfield_default }, + { "CID4_MASK", 4, 4, &umr_bitfield_default }, + { "CID5_MASK", 5, 5, &umr_bitfield_default }, + { "CID6_MASK", 6, 6, &umr_bitfield_default }, + { "CID7_MASK", 7, 7, &umr_bitfield_default }, + { "CID8_MASK", 8, 8, &umr_bitfield_default }, + { "CID9_MASK", 9, 9, &umr_bitfield_default }, + { "CID10_MASK", 10, 10, &umr_bitfield_default }, + { "CID11_MASK", 11, 11, &umr_bitfield_default }, + { "CID12_MASK", 12, 12, &umr_bitfield_default }, + { "CID13_MASK", 13, 13, &umr_bitfield_default }, + { "CID14_MASK", 14, 14, &umr_bitfield_default }, + { "CID15_MASK", 15, 15, &umr_bitfield_default }, + { "CID16_MASK", 16, 16, &umr_bitfield_default }, + { "CID17_MASK", 17, 17, &umr_bitfield_default }, + { "CID18_MASK", 18, 18, &umr_bitfield_default }, + { "CID19_MASK", 19, 19, &umr_bitfield_default }, + { "CID20_MASK", 20, 20, &umr_bitfield_default }, + { "CID21_MASK", 21, 21, &umr_bitfield_default }, + { "CID22_MASK", 22, 22, &umr_bitfield_default }, + { "CID23_MASK", 23, 23, &umr_bitfield_default }, + { "CID24_MASK", 24, 24, &umr_bitfield_default }, + { "CID25_MASK", 25, 25, &umr_bitfield_default }, + { "CID26_MASK", 26, 26, &umr_bitfield_default }, + { "CID27_MASK", 27, 27, &umr_bitfield_default }, + { "CID28_MASK", 28, 28, &umr_bitfield_default }, + { "CID29_MASK", 29, 29, &umr_bitfield_default }, + { "CID30_MASK", 30, 30, &umr_bitfield_default }, + { "CID31_MASK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_IO_RD_PRI_QUANT_PRI1[] = { + { "GROUP0_THRESHOLD", 0, 7, &umr_bitfield_default }, + { "GROUP1_THRESHOLD", 8, 15, &umr_bitfield_default }, + { "GROUP2_THRESHOLD", 16, 23, &umr_bitfield_default }, + { "GROUP3_THRESHOLD", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_IO_RD_PRI_QUANT_PRI2[] = { + { "GROUP0_THRESHOLD", 0, 7, &umr_bitfield_default }, + { "GROUP1_THRESHOLD", 8, 15, &umr_bitfield_default }, + { "GROUP2_THRESHOLD", 16, 23, &umr_bitfield_default }, + { "GROUP3_THRESHOLD", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_IO_RD_PRI_QUANT_PRI3[] = { + { "GROUP0_THRESHOLD", 0, 7, &umr_bitfield_default }, + { "GROUP1_THRESHOLD", 8, 15, &umr_bitfield_default }, + { "GROUP2_THRESHOLD", 16, 23, &umr_bitfield_default }, + { "GROUP3_THRESHOLD", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_IO_WR_PRI_QUANT_PRI1[] = { + { "GROUP0_THRESHOLD", 0, 7, &umr_bitfield_default }, + { "GROUP1_THRESHOLD", 8, 15, &umr_bitfield_default }, + { "GROUP2_THRESHOLD", 16, 23, &umr_bitfield_default }, + { "GROUP3_THRESHOLD", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_IO_WR_PRI_QUANT_PRI2[] = { + { "GROUP0_THRESHOLD", 0, 7, &umr_bitfield_default }, + { "GROUP1_THRESHOLD", 8, 15, &umr_bitfield_default }, + { "GROUP2_THRESHOLD", 16, 23, &umr_bitfield_default }, + { "GROUP3_THRESHOLD", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_IO_WR_PRI_QUANT_PRI3[] = { + { "GROUP0_THRESHOLD", 0, 7, &umr_bitfield_default }, + { "GROUP1_THRESHOLD", 8, 15, &umr_bitfield_default }, + { "GROUP2_THRESHOLD", 16, 23, &umr_bitfield_default }, + { "GROUP3_THRESHOLD", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_SDP_ARB_DRAM[] = { + { "RDWR_BURST_LIMIT_CYCL", 0, 6, &umr_bitfield_default }, + { "RDWR_BURST_LIMIT_DATA", 8, 14, &umr_bitfield_default }, + { "EARLY_SW2RD_ON_PRI", 16, 16, &umr_bitfield_default }, + { "EARLY_SW2WR_ON_PRI", 17, 17, &umr_bitfield_default }, + { "EARLY_SW2RD_ON_RES", 18, 18, &umr_bitfield_default }, + { "EARLY_SW2WR_ON_RES", 19, 19, &umr_bitfield_default }, + { "EOB_ON_EXPIRE", 20, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_SDP_ARB_FINAL[] = { + { "DRAM_BURST_LIMIT", 0, 4, &umr_bitfield_default }, + { "GMI_BURST_LIMIT", 5, 9, &umr_bitfield_default }, + { "IO_BURST_LIMIT", 10, 14, &umr_bitfield_default }, + { "BURST_LIMIT_MULTIPLIER", 15, 16, &umr_bitfield_default }, + { "RDONLY_VC0", 17, 17, &umr_bitfield_default }, + { "RDONLY_VC1", 18, 18, &umr_bitfield_default }, + { "RDONLY_VC2", 19, 19, &umr_bitfield_default }, + { "RDONLY_VC3", 20, 20, &umr_bitfield_default }, + { "RDONLY_VC4", 21, 21, &umr_bitfield_default }, + { "RDONLY_VC5", 22, 22, &umr_bitfield_default }, + { "RDONLY_VC6", 23, 23, &umr_bitfield_default }, + { "RDONLY_VC7", 24, 24, &umr_bitfield_default }, + { "ERREVENT_ON_ERROR", 25, 25, &umr_bitfield_default }, + { "HALTREQ_ON_ERROR", 26, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_SDP_DRAM_PRIORITY[] = { + { "RD_GROUP0_PRIORITY", 0, 3, &umr_bitfield_default }, + { "RD_GROUP1_PRIORITY", 4, 7, &umr_bitfield_default }, + { "RD_GROUP2_PRIORITY", 8, 11, &umr_bitfield_default }, + { "RD_GROUP3_PRIORITY", 12, 15, &umr_bitfield_default }, + { "WR_GROUP0_PRIORITY", 16, 19, &umr_bitfield_default }, + { "WR_GROUP1_PRIORITY", 20, 23, &umr_bitfield_default }, + { "WR_GROUP2_PRIORITY", 24, 27, &umr_bitfield_default }, + { "WR_GROUP3_PRIORITY", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_SDP_IO_PRIORITY[] = { + { "RD_GROUP0_PRIORITY", 0, 3, &umr_bitfield_default }, + { "RD_GROUP1_PRIORITY", 4, 7, &umr_bitfield_default }, + { "RD_GROUP2_PRIORITY", 8, 11, &umr_bitfield_default }, + { "RD_GROUP3_PRIORITY", 12, 15, &umr_bitfield_default }, + { "WR_GROUP0_PRIORITY", 16, 19, &umr_bitfield_default }, + { "WR_GROUP1_PRIORITY", 20, 23, &umr_bitfield_default }, + { "WR_GROUP2_PRIORITY", 24, 27, &umr_bitfield_default }, + { "WR_GROUP3_PRIORITY", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_SDP_CREDITS[] = { + { "TAG_LIMIT", 0, 7, &umr_bitfield_default }, + { "WR_RESP_CREDITS", 8, 14, &umr_bitfield_default }, + { "RD_RESP_CREDITS", 16, 22, &umr_bitfield_default }, + { "PRB_REQ_CREDITS", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_SDP_TAG_RESERVE0[] = { + { "VC0", 0, 7, &umr_bitfield_default }, + { "VC1", 8, 15, &umr_bitfield_default }, + { "VC2", 16, 23, &umr_bitfield_default }, + { "VC3", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_SDP_TAG_RESERVE1[] = { + { "VC4", 0, 7, &umr_bitfield_default }, + { "VC5", 8, 15, &umr_bitfield_default }, + { "VC6", 16, 23, &umr_bitfield_default }, + { "VC7", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_SDP_VCC_RESERVE0[] = { + { "VC0_CREDITS", 0, 5, &umr_bitfield_default }, + { "VC1_CREDITS", 6, 11, &umr_bitfield_default }, + { "VC2_CREDITS", 12, 17, &umr_bitfield_default }, + { "VC3_CREDITS", 18, 23, &umr_bitfield_default }, + { "VC4_CREDITS", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_SDP_VCC_RESERVE1[] = { + { "VC5_CREDITS", 0, 5, &umr_bitfield_default }, + { "VC6_CREDITS", 6, 11, &umr_bitfield_default }, + { "VC7_CREDITS", 12, 17, &umr_bitfield_default }, + { "DISTRIBUTE_POOL", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_SDP_VCD_RESERVE0[] = { + { "VC0_CREDITS", 0, 5, &umr_bitfield_default }, + { "VC1_CREDITS", 6, 11, &umr_bitfield_default }, + { "VC2_CREDITS", 12, 17, &umr_bitfield_default }, + { "VC3_CREDITS", 18, 23, &umr_bitfield_default }, + { "VC4_CREDITS", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_SDP_VCD_RESERVE1[] = { + { "VC5_CREDITS", 0, 5, &umr_bitfield_default }, + { "VC6_CREDITS", 6, 11, &umr_bitfield_default }, + { "VC7_CREDITS", 12, 17, &umr_bitfield_default }, + { "DISTRIBUTE_POOL", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_SDP_REQ_CNTL[] = { + { "REQ_PASS_PW_OVERRIDE_READ", 0, 0, &umr_bitfield_default }, + { "REQ_PASS_PW_OVERRIDE_WRITE", 1, 1, &umr_bitfield_default }, + { "REQ_PASS_PW_OVERRIDE_ATOMIC", 2, 2, &umr_bitfield_default }, + { "REQ_CHAIN_OVERRIDE_DRAM", 3, 3, &umr_bitfield_default }, + { "INNER_DOMAIN_MODE", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_MISC[] = { + { "RELATIVE_PRI_IN_DRAM_RD_ARB", 0, 0, &umr_bitfield_default }, + { "RELATIVE_PRI_IN_DRAM_WR_ARB", 1, 1, &umr_bitfield_default }, + { "RELATIVE_PRI_IN_GMI_RD_ARB", 2, 2, &umr_bitfield_default }, + { "RELATIVE_PRI_IN_GMI_WR_ARB", 3, 3, &umr_bitfield_default }, + { "RELATIVE_PRI_IN_IO_RD_ARB", 4, 4, &umr_bitfield_default }, + { "RELATIVE_PRI_IN_IO_WR_ARB", 5, 5, &umr_bitfield_default }, + { "EARLYWRRET_ENABLE_VC0", 6, 6, &umr_bitfield_default }, + { "EARLYWRRET_ENABLE_VC1", 7, 7, &umr_bitfield_default }, + { "EARLYWRRET_ENABLE_VC2", 8, 8, &umr_bitfield_default }, + { "EARLYWRRET_ENABLE_VC3", 9, 9, &umr_bitfield_default }, + { "EARLYWRRET_ENABLE_VC4", 10, 10, &umr_bitfield_default }, + { "EARLYWRRET_ENABLE_VC5", 11, 11, &umr_bitfield_default }, + { "EARLYWRRET_ENABLE_VC6", 12, 12, &umr_bitfield_default }, + { "EARLYWRRET_ENABLE_VC7", 13, 13, &umr_bitfield_default }, + { "EARLY_SDP_ORIGDATA", 14, 14, &umr_bitfield_default }, + { "LINKMGR_DYNAMIC_MODE", 15, 16, &umr_bitfield_default }, + { "LINKMGR_HALT_THRESHOLD", 17, 18, &umr_bitfield_default }, + { "LINKMGR_RECONNECT_DELAY", 19, 20, &umr_bitfield_default }, + { "LINKMGR_IDLE_THRESHOLD", 21, 25, &umr_bitfield_default }, + { "FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB", 26, 26, &umr_bitfield_default }, + { "FAVOUR_MIDCHAIN_CS_IN_GMI_ARB", 27, 27, &umr_bitfield_default }, + { "FAVOUR_LAST_CS_IN_DRAM_ARB", 28, 28, &umr_bitfield_default }, + { "FAVOUR_LAST_CS_IN_GMI_ARB", 29, 29, &umr_bitfield_default }, + { "SWITCH_CS_ON_W2R_IN_DRAM_ARB", 30, 30, &umr_bitfield_default }, + { "SWITCH_CS_ON_W2R_IN_GMI_ARB", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_LATENCY_SAMPLING[] = { + { "SAMPLER0_DRAM", 0, 0, &umr_bitfield_default }, + { "SAMPLER1_DRAM", 1, 1, &umr_bitfield_default }, + { "SAMPLER0_GMI", 2, 2, &umr_bitfield_default }, + { "SAMPLER1_GMI", 3, 3, &umr_bitfield_default }, + { "SAMPLER0_IO", 4, 4, &umr_bitfield_default }, + { "SAMPLER1_IO", 5, 5, &umr_bitfield_default }, + { "SAMPLER0_READ", 6, 6, &umr_bitfield_default }, + { "SAMPLER1_READ", 7, 7, &umr_bitfield_default }, + { "SAMPLER0_WRITE", 8, 8, &umr_bitfield_default }, + { "SAMPLER1_WRITE", 9, 9, &umr_bitfield_default }, + { "SAMPLER0_ATOMIC_RET", 10, 10, &umr_bitfield_default }, + { "SAMPLER1_ATOMIC_RET", 11, 11, &umr_bitfield_default }, + { "SAMPLER0_ATOMIC_NORET", 12, 12, &umr_bitfield_default }, + { "SAMPLER1_ATOMIC_NORET", 13, 13, &umr_bitfield_default }, + { "SAMPLER0_VC", 14, 21, &umr_bitfield_default }, + { "SAMPLER1_VC", 22, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_PERFCOUNTER_LO[] = { + { "COUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_PERFCOUNTER_HI[] = { + { "COUNTER_HI", 0, 15, &umr_bitfield_default }, + { "COMPARE_VALUE", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_PERFCOUNTER0_CFG[] = { + { "PERF_SEL", 0, 7, &umr_bitfield_default }, + { "PERF_SEL_END", 8, 15, &umr_bitfield_default }, + { "PERF_MODE", 24, 27, &umr_bitfield_default }, + { "ENABLE", 28, 28, &umr_bitfield_default }, + { "CLEAR", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_PERFCOUNTER1_CFG[] = { + { "PERF_SEL", 0, 7, &umr_bitfield_default }, + { "PERF_SEL_END", 8, 15, &umr_bitfield_default }, + { "PERF_MODE", 24, 27, &umr_bitfield_default }, + { "ENABLE", 28, 28, &umr_bitfield_default }, + { "CLEAR", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_PERFCOUNTER_RSLT_CNTL[] = { + { "PERF_COUNTER_SELECT", 0, 3, &umr_bitfield_default }, + { "START_TRIGGER", 8, 15, &umr_bitfield_default }, + { "STOP_TRIGGER", 16, 23, &umr_bitfield_default }, + { "ENABLE_ANY", 24, 24, &umr_bitfield_default }, + { "CLEAR_ALL", 25, 25, &umr_bitfield_default }, + { "STOP_ALL_ON_SATURATE", 26, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCP_INVALIDATE[] = { + { "START", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCP_STATUS[] = { + { "TCP_BUSY", 0, 0, &umr_bitfield_default }, + { "INPUT_BUSY", 1, 1, &umr_bitfield_default }, + { "ADRS_BUSY", 2, 2, &umr_bitfield_default }, + { "TAGRAMS_BUSY", 3, 3, &umr_bitfield_default }, + { "CNTRL_BUSY", 4, 4, &umr_bitfield_default }, + { "LFIFO_BUSY", 5, 5, &umr_bitfield_default }, + { "READ_BUSY", 6, 6, &umr_bitfield_default }, + { "FORMAT_BUSY", 7, 7, &umr_bitfield_default }, + { "VM_BUSY", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCP_CNTL[] = { + { "FORCE_HIT", 0, 0, &umr_bitfield_default }, + { "FORCE_MISS", 1, 1, &umr_bitfield_default }, + { "L1_SIZE", 2, 3, &umr_bitfield_default }, + { "FLAT_BUF_HASH_ENABLE", 4, 4, &umr_bitfield_default }, + { "FLAT_BUF_CACHE_SWIZZLE", 5, 5, &umr_bitfield_default }, + { "FORCE_EOW_TOTAL_CNT", 15, 20, &umr_bitfield_default }, + { "FORCE_EOW_TAGRAM_CNT", 22, 27, &umr_bitfield_default }, + { "DISABLE_Z_MAP", 28, 28, &umr_bitfield_default }, + { "INV_ALL_VMIDS", 29, 29, &umr_bitfield_default }, + { "ASTC_VE_MSB_TOLERANT", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCP_CHAN_STEER_LO[] = { + { "CHAN0", 0, 3, &umr_bitfield_default }, + { "CHAN1", 4, 7, &umr_bitfield_default }, + { "CHAN2", 8, 11, &umr_bitfield_default }, + { "CHAN3", 12, 15, &umr_bitfield_default }, + { "CHAN4", 16, 19, &umr_bitfield_default }, + { "CHAN5", 20, 23, &umr_bitfield_default }, + { "CHAN6", 24, 27, &umr_bitfield_default }, + { "CHAN7", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCP_CHAN_STEER_HI[] = { + { "CHAN8", 0, 3, &umr_bitfield_default }, + { "CHAN9", 4, 7, &umr_bitfield_default }, + { "CHANA", 8, 11, &umr_bitfield_default }, + { "CHANB", 12, 15, &umr_bitfield_default }, + { "CHANC", 16, 19, &umr_bitfield_default }, + { "CHAND", 20, 23, &umr_bitfield_default }, + { "CHANE", 24, 27, &umr_bitfield_default }, + { "CHANF", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCP_ADDR_CONFIG[] = { + { "NUM_TCC_BANKS", 0, 3, &umr_bitfield_default }, + { "NUM_BANKS", 4, 5, &umr_bitfield_default }, + { "COLHI_WIDTH", 6, 8, &umr_bitfield_default }, + { "RB_SPLIT_COLHI", 9, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCP_CREDIT[] = { + { "LFIFO_CREDIT", 0, 9, &umr_bitfield_default }, + { "REQ_FIFO_CREDIT", 16, 22, &umr_bitfield_default }, + { "TD_CREDIT", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCP_BUFFER_ADDR_HASH_CNTL[] = { + { "CHANNEL_BITS", 0, 2, &umr_bitfield_default }, + { "BANK_BITS", 8, 10, &umr_bitfield_default }, + { "CHANNEL_XOR_COUNT", 16, 18, &umr_bitfield_default }, + { "BANK_XOR_COUNT", 24, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCP_EDC_CNT[] = { + { "SEC_COUNT", 0, 7, &umr_bitfield_default }, + { "LFIFO_SED_COUNT", 8, 15, &umr_bitfield_default }, + { "DED_COUNT", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTC_CFG_L1_LOAD_POLICY0[] = { + { "POLICY_0", 0, 1, &umr_bitfield_default }, + { "POLICY_1", 2, 3, &umr_bitfield_default }, + { "POLICY_2", 4, 5, &umr_bitfield_default }, + { "POLICY_3", 6, 7, &umr_bitfield_default }, + { "POLICY_4", 8, 9, &umr_bitfield_default }, + { "POLICY_5", 10, 11, &umr_bitfield_default }, + { "POLICY_6", 12, 13, &umr_bitfield_default }, + { "POLICY_7", 14, 15, &umr_bitfield_default }, + { "POLICY_8", 16, 17, &umr_bitfield_default }, + { "POLICY_9", 18, 19, &umr_bitfield_default }, + { "POLICY_10", 20, 21, &umr_bitfield_default }, + { "POLICY_11", 22, 23, &umr_bitfield_default }, + { "POLICY_12", 24, 25, &umr_bitfield_default }, + { "POLICY_13", 26, 27, &umr_bitfield_default }, + { "POLICY_14", 28, 29, &umr_bitfield_default }, + { "POLICY_15", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTC_CFG_L1_LOAD_POLICY1[] = { + { "POLICY_16", 0, 1, &umr_bitfield_default }, + { "POLICY_17", 2, 3, &umr_bitfield_default }, + { "POLICY_18", 4, 5, &umr_bitfield_default }, + { "POLICY_19", 6, 7, &umr_bitfield_default }, + { "POLICY_20", 8, 9, &umr_bitfield_default }, + { "POLICY_21", 10, 11, &umr_bitfield_default }, + { "POLICY_22", 12, 13, &umr_bitfield_default }, + { "POLICY_23", 14, 15, &umr_bitfield_default }, + { "POLICY_24", 16, 17, &umr_bitfield_default }, + { "POLICY_25", 18, 19, &umr_bitfield_default }, + { "POLICY_26", 20, 21, &umr_bitfield_default }, + { "POLICY_27", 22, 23, &umr_bitfield_default }, + { "POLICY_28", 24, 25, &umr_bitfield_default }, + { "POLICY_29", 26, 27, &umr_bitfield_default }, + { "POLICY_30", 28, 29, &umr_bitfield_default }, + { "POLICY_31", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTC_CFG_L1_STORE_POLICY[] = { + { "POLICY_0", 0, 0, &umr_bitfield_default }, + { "POLICY_1", 1, 1, &umr_bitfield_default }, + { "POLICY_2", 2, 2, &umr_bitfield_default }, + { "POLICY_3", 3, 3, &umr_bitfield_default }, + { "POLICY_4", 4, 4, &umr_bitfield_default }, + { "POLICY_5", 5, 5, &umr_bitfield_default }, + { "POLICY_6", 6, 6, &umr_bitfield_default }, + { "POLICY_7", 7, 7, &umr_bitfield_default }, + { "POLICY_8", 8, 8, &umr_bitfield_default }, + { "POLICY_9", 9, 9, &umr_bitfield_default }, + { "POLICY_10", 10, 10, &umr_bitfield_default }, + { "POLICY_11", 11, 11, &umr_bitfield_default }, + { "POLICY_12", 12, 12, &umr_bitfield_default }, + { "POLICY_13", 13, 13, &umr_bitfield_default }, + { "POLICY_14", 14, 14, &umr_bitfield_default }, + { "POLICY_15", 15, 15, &umr_bitfield_default }, + { "POLICY_16", 16, 16, &umr_bitfield_default }, + { "POLICY_17", 17, 17, &umr_bitfield_default }, + { "POLICY_18", 18, 18, &umr_bitfield_default }, + { "POLICY_19", 19, 19, &umr_bitfield_default }, + { "POLICY_20", 20, 20, &umr_bitfield_default }, + { "POLICY_21", 21, 21, &umr_bitfield_default }, + { "POLICY_22", 22, 22, &umr_bitfield_default }, + { "POLICY_23", 23, 23, &umr_bitfield_default }, + { "POLICY_24", 24, 24, &umr_bitfield_default }, + { "POLICY_25", 25, 25, &umr_bitfield_default }, + { "POLICY_26", 26, 26, &umr_bitfield_default }, + { "POLICY_27", 27, 27, &umr_bitfield_default }, + { "POLICY_28", 28, 28, &umr_bitfield_default }, + { "POLICY_29", 29, 29, &umr_bitfield_default }, + { "POLICY_30", 30, 30, &umr_bitfield_default }, + { "POLICY_31", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTC_CFG_L2_LOAD_POLICY0[] = { + { "POLICY_0", 0, 1, &umr_bitfield_default }, + { "POLICY_1", 2, 3, &umr_bitfield_default }, + { "POLICY_2", 4, 5, &umr_bitfield_default }, + { "POLICY_3", 6, 7, &umr_bitfield_default }, + { "POLICY_4", 8, 9, &umr_bitfield_default }, + { "POLICY_5", 10, 11, &umr_bitfield_default }, + { "POLICY_6", 12, 13, &umr_bitfield_default }, + { "POLICY_7", 14, 15, &umr_bitfield_default }, + { "POLICY_8", 16, 17, &umr_bitfield_default }, + { "POLICY_9", 18, 19, &umr_bitfield_default }, + { "POLICY_10", 20, 21, &umr_bitfield_default }, + { "POLICY_11", 22, 23, &umr_bitfield_default }, + { "POLICY_12", 24, 25, &umr_bitfield_default }, + { "POLICY_13", 26, 27, &umr_bitfield_default }, + { "POLICY_14", 28, 29, &umr_bitfield_default }, + { "POLICY_15", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTC_CFG_L2_LOAD_POLICY1[] = { + { "POLICY_16", 0, 1, &umr_bitfield_default }, + { "POLICY_17", 2, 3, &umr_bitfield_default }, + { "POLICY_18", 4, 5, &umr_bitfield_default }, + { "POLICY_19", 6, 7, &umr_bitfield_default }, + { "POLICY_20", 8, 9, &umr_bitfield_default }, + { "POLICY_21", 10, 11, &umr_bitfield_default }, + { "POLICY_22", 12, 13, &umr_bitfield_default }, + { "POLICY_23", 14, 15, &umr_bitfield_default }, + { "POLICY_24", 16, 17, &umr_bitfield_default }, + { "POLICY_25", 18, 19, &umr_bitfield_default }, + { "POLICY_26", 20, 21, &umr_bitfield_default }, + { "POLICY_27", 22, 23, &umr_bitfield_default }, + { "POLICY_28", 24, 25, &umr_bitfield_default }, + { "POLICY_29", 26, 27, &umr_bitfield_default }, + { "POLICY_30", 28, 29, &umr_bitfield_default }, + { "POLICY_31", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTC_CFG_L2_STORE_POLICY0[] = { + { "POLICY_0", 0, 1, &umr_bitfield_default }, + { "POLICY_1", 2, 3, &umr_bitfield_default }, + { "POLICY_2", 4, 5, &umr_bitfield_default }, + { "POLICY_3", 6, 7, &umr_bitfield_default }, + { "POLICY_4", 8, 9, &umr_bitfield_default }, + { "POLICY_5", 10, 11, &umr_bitfield_default }, + { "POLICY_6", 12, 13, &umr_bitfield_default }, + { "POLICY_7", 14, 15, &umr_bitfield_default }, + { "POLICY_8", 16, 17, &umr_bitfield_default }, + { "POLICY_9", 18, 19, &umr_bitfield_default }, + { "POLICY_10", 20, 21, &umr_bitfield_default }, + { "POLICY_11", 22, 23, &umr_bitfield_default }, + { "POLICY_12", 24, 25, &umr_bitfield_default }, + { "POLICY_13", 26, 27, &umr_bitfield_default }, + { "POLICY_14", 28, 29, &umr_bitfield_default }, + { "POLICY_15", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTC_CFG_L2_STORE_POLICY1[] = { + { "POLICY_16", 0, 1, &umr_bitfield_default }, + { "POLICY_17", 2, 3, &umr_bitfield_default }, + { "POLICY_18", 4, 5, &umr_bitfield_default }, + { "POLICY_19", 6, 7, &umr_bitfield_default }, + { "POLICY_20", 8, 9, &umr_bitfield_default }, + { "POLICY_21", 10, 11, &umr_bitfield_default }, + { "POLICY_22", 12, 13, &umr_bitfield_default }, + { "POLICY_23", 14, 15, &umr_bitfield_default }, + { "POLICY_24", 16, 17, &umr_bitfield_default }, + { "POLICY_25", 18, 19, &umr_bitfield_default }, + { "POLICY_26", 20, 21, &umr_bitfield_default }, + { "POLICY_27", 22, 23, &umr_bitfield_default }, + { "POLICY_28", 24, 25, &umr_bitfield_default }, + { "POLICY_29", 26, 27, &umr_bitfield_default }, + { "POLICY_30", 28, 29, &umr_bitfield_default }, + { "POLICY_31", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTC_CFG_L2_ATOMIC_POLICY[] = { + { "POLICY_0", 0, 1, &umr_bitfield_default }, + { "POLICY_1", 2, 3, &umr_bitfield_default }, + { "POLICY_2", 4, 5, &umr_bitfield_default }, + { "POLICY_3", 6, 7, &umr_bitfield_default }, + { "POLICY_4", 8, 9, &umr_bitfield_default }, + { "POLICY_5", 10, 11, &umr_bitfield_default }, + { "POLICY_6", 12, 13, &umr_bitfield_default }, + { "POLICY_7", 14, 15, &umr_bitfield_default }, + { "POLICY_8", 16, 17, &umr_bitfield_default }, + { "POLICY_9", 18, 19, &umr_bitfield_default }, + { "POLICY_10", 20, 21, &umr_bitfield_default }, + { "POLICY_11", 22, 23, &umr_bitfield_default }, + { "POLICY_12", 24, 25, &umr_bitfield_default }, + { "POLICY_13", 26, 27, &umr_bitfield_default }, + { "POLICY_14", 28, 29, &umr_bitfield_default }, + { "POLICY_15", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTC_CFG_L1_VOLATILE[] = { + { "VOL", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTC_CFG_L2_VOLATILE[] = { + { "VOL", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCI_STATUS[] = { + { "TCI_BUSY", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCI_CNTL_1[] = { + { "WBINVL1_NUM_CYCLES", 0, 15, &umr_bitfield_default }, + { "REQ_FIFO_DEPTH", 16, 23, &umr_bitfield_default }, + { "WDATA_RAM_DEPTH", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCI_CNTL_2[] = { + { "L1_INVAL_ON_WBINVL2", 0, 0, &umr_bitfield_default }, + { "TCA_MAX_CREDIT", 1, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCC_CTRL[] = { + { "CACHE_SIZE", 0, 1, &umr_bitfield_default }, + { "RATE", 2, 3, &umr_bitfield_default }, + { "WRITEBACK_MARGIN", 4, 7, &umr_bitfield_default }, + { "METADATA_LATENCY_FIFO_SIZE", 8, 11, &umr_bitfield_default }, + { "SRC_FIFO_SIZE", 12, 15, &umr_bitfield_default }, + { "LATENCY_FIFO_SIZE", 16, 19, &umr_bitfield_default }, + { "LINEAR_SET_HASH", 21, 21, &umr_bitfield_default }, + { "MDC_SIZE", 24, 25, &umr_bitfield_default }, + { "MDC_SECTOR_SIZE", 26, 27, &umr_bitfield_default }, + { "MDC_SIDEBAND_FIFO_SIZE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCC_CTRL2[] = { + { "PROBE_FIFO_SIZE", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCC_EDC_CNT[] = { + { "CACHE_DATA_SEC_COUNT", 0, 1, &umr_bitfield_default }, + { "CACHE_DATA_DED_COUNT", 2, 3, &umr_bitfield_default }, + { "CACHE_DIRTY_SEC_COUNT", 4, 5, &umr_bitfield_default }, + { "CACHE_DIRTY_DED_COUNT", 6, 7, &umr_bitfield_default }, + { "HIGH_RATE_TAG_SEC_COUNT", 8, 9, &umr_bitfield_default }, + { "HIGH_RATE_TAG_DED_COUNT", 10, 11, &umr_bitfield_default }, + { "LOW_RATE_TAG_SEC_COUNT", 12, 13, &umr_bitfield_default }, + { "LOW_RATE_TAG_DED_COUNT", 14, 15, &umr_bitfield_default }, + { "SRC_FIFO_SEC_COUNT", 16, 17, &umr_bitfield_default }, + { "SRC_FIFO_DED_COUNT", 18, 19, &umr_bitfield_default }, + { "IN_USE_DEC_SED_COUNT", 20, 21, &umr_bitfield_default }, + { "IN_USE_TRANSFER_SED_COUNT", 22, 23, &umr_bitfield_default }, + { "LATENCY_FIFO_SED_COUNT", 24, 25, &umr_bitfield_default }, + { "RETURN_DATA_SED_COUNT", 26, 27, &umr_bitfield_default }, + { "RETURN_CONTROL_SED_COUNT", 28, 29, &umr_bitfield_default }, + { "UC_ATOMIC_FIFO_SED_COUNT", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCC_EDC_CNT2[] = { + { "WRITE_RETURN_SED_COUNT", 0, 1, &umr_bitfield_default }, + { "WRITE_CACHE_READ_SED_COUNT", 2, 3, &umr_bitfield_default }, + { "SRC_FIFO_NEXT_RAM_SED_COUNT", 4, 5, &umr_bitfield_default }, + { "LATENCY_FIFO_NEXT_RAM_SED_COUNT", 6, 7, &umr_bitfield_default }, + { "CACHE_TAG_PROBE_FIFO_SED_COUNT", 8, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCC_REDUNDANCY[] = { + { "MC_SEL0", 0, 0, &umr_bitfield_default }, + { "MC_SEL1", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCC_EXE_DISABLE[] = { + { "EXE_DISABLE", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCC_DSM_CNTL[] = { + { "CACHE_DATA_IRRITATOR_DATA_SEL", 0, 1, &umr_bitfield_default }, + { "CACHE_DATA_IRRITATOR_SINGLE_WRITE", 2, 2, &umr_bitfield_default }, + { "CACHE_DATA_BANK_0_1_IRRITATOR_DATA_SEL", 3, 4, &umr_bitfield_default }, + { "CACHE_DATA_BANK_0_1_IRRITATOR_SINGLE_WRITE", 5, 5, &umr_bitfield_default }, + { "CACHE_DATA_BANK_1_0_IRRITATOR_DATA_SEL", 6, 7, &umr_bitfield_default }, + { "CACHE_DATA_BANK_1_0_IRRITATOR_SINGLE_WRITE", 8, 8, &umr_bitfield_default }, + { "CACHE_DATA_BANK_1_1_IRRITATOR_DATA_SEL", 9, 10, &umr_bitfield_default }, + { "CACHE_DATA_BANK_1_1_IRRITATOR_SINGLE_WRITE", 11, 11, &umr_bitfield_default }, + { "CACHE_DIRTY_BANK_0_IRRITATOR_DATA_SEL", 12, 13, &umr_bitfield_default }, + { "CACHE_DIRTY_BANK_0_IRRITATOR_SINGLE_WRITE", 14, 14, &umr_bitfield_default }, + { "CACHE_DIRTY_BANK_1_IRRITATOR_DATA_SEL", 15, 16, &umr_bitfield_default }, + { "CACHE_DIRTY_BANK_1_IRRITATOR_SINGLE_WRITE", 17, 17, &umr_bitfield_default }, + { "HIGH_RATE_TAG_IRRITATOR_DATA_SEL", 18, 19, &umr_bitfield_default }, + { "HIGH_RATE_TAG_IRRITATOR_SINGLE_WRITE", 20, 20, &umr_bitfield_default }, + { "LOW_RATE_TAG_IRRITATOR_DATA_SEL", 21, 22, &umr_bitfield_default }, + { "LOW_RATE_TAG_IRRITATOR_SINGLE_WRITE", 23, 23, &umr_bitfield_default }, + { "IN_USE_DEC_IRRITATOR_DATA_SEL", 24, 25, &umr_bitfield_default }, + { "IN_USE_DEC_IRRITATOR_SINGLE_WRITE", 26, 26, &umr_bitfield_default }, + { "IN_USE_TRANSFER_IRRITATOR_DATA_SEL", 27, 28, &umr_bitfield_default }, + { "IN_USE_TRANSFER_IRRITATOR_SINGLE_WRITE", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCC_DSM_CNTLA[] = { + { "SRC_FIFO_IRRITATOR_DATA_SEL", 0, 1, &umr_bitfield_default }, + { "SRC_FIFO_IRRITATOR_SINGLE_WRITE", 2, 2, &umr_bitfield_default }, + { "UC_ATOMIC_FIFO_IRRITATOR_DATA_SEL", 3, 4, &umr_bitfield_default }, + { "UC_ATOMIC_FIFO_IRRITATOR_SINGLE_WRITE", 5, 5, &umr_bitfield_default }, + { "WRITE_RETURN_IRRITATOR_DATA_SEL", 6, 7, &umr_bitfield_default }, + { "WRITE_RETURN_IRRITATOR_SINGLE_WRITE", 8, 8, &umr_bitfield_default }, + { "WRITE_CACHE_READ_IRRITATOR_DATA_SEL", 9, 10, &umr_bitfield_default }, + { "WRITE_CACHE_READ_IRRITATOR_SINGLE_WRITE", 11, 11, &umr_bitfield_default }, + { "SRC_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL", 12, 13, &umr_bitfield_default }, + { "SRC_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE", 14, 14, &umr_bitfield_default }, + { "LATENCY_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL", 15, 16, &umr_bitfield_default }, + { "LATENCY_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE", 17, 17, &umr_bitfield_default }, + { "CACHE_TAG_PROBE_FIFO_IRRITATOR_DATA_SEL", 18, 19, &umr_bitfield_default }, + { "CACHE_TAG_PROBE_FIFO_IRRITATOR_SINGLE_WRITE", 20, 20, &umr_bitfield_default }, + { "LATENCY_FIFO_IRRITATOR_DATA_SEL", 21, 22, &umr_bitfield_default }, + { "LATENCY_FIFO_IRRITATOR_SINGLE_WRITE", 23, 23, &umr_bitfield_default }, + { "RETURN_DATA_IRRITATOR_DATA_SEL", 24, 25, &umr_bitfield_default }, + { "RETURN_DATA_IRRITATOR_SINGLE_WRITE", 26, 26, &umr_bitfield_default }, + { "RETURN_CONTROL_IRRITATOR_DATA_SEL", 27, 28, &umr_bitfield_default }, + { "RETURN_CONTROL_IRRITATOR_SINGLE_WRITE", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCC_DSM_CNTL2[] = { + { "CACHE_DATA_ENABLE_ERROR_INJECT", 0, 1, &umr_bitfield_default }, + { "CACHE_DATA_SELECT_INJECT_DELAY", 2, 2, &umr_bitfield_default }, + { "CACHE_DATA_BANK_0_1_ENABLE_ERROR_INJECT", 3, 4, &umr_bitfield_default }, + { "CACHE_DATA_BANK_0_1_SELECT_INJECT_DELAY", 5, 5, &umr_bitfield_default }, + { "CACHE_DATA_BANK_1_0_ENABLE_ERROR_INJECT", 6, 7, &umr_bitfield_default }, + { "CACHE_DATA_BANK_1_0_SELECT_INJECT_DELAY", 8, 8, &umr_bitfield_default }, + { "CACHE_DATA_BANK_1_1_ENABLE_ERROR_INJECT", 9, 10, &umr_bitfield_default }, + { "CACHE_DATA_BANK_1_1_SELECT_INJECT_DELAY", 11, 11, &umr_bitfield_default }, + { "CACHE_DIRTY_BANK_0_ENABLE_ERROR_INJECT", 12, 13, &umr_bitfield_default }, + { "CACHE_DIRTY_BANK_0_SELECT_INJECT_DELAY", 14, 14, &umr_bitfield_default }, + { "CACHE_DIRTY_BANK_1_ENABLE_ERROR_INJECT", 15, 16, &umr_bitfield_default }, + { "CACHE_DIRTY_BANK_1_SELECT_INJECT_DELAY", 17, 17, &umr_bitfield_default }, + { "HIGH_RATE_TAG_ENABLE_ERROR_INJECT", 18, 19, &umr_bitfield_default }, + { "HIGH_RATE_TAG_SELECT_INJECT_DELAY", 20, 20, &umr_bitfield_default }, + { "LOW_RATE_TAG_ENABLE_ERROR_INJECT", 21, 22, &umr_bitfield_default }, + { "LOW_RATE_TAG_SELECT_INJECT_DELAY", 23, 23, &umr_bitfield_default }, + { "INJECT_DELAY", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCC_DSM_CNTL2A[] = { + { "IN_USE_DEC_ENABLE_ERROR_INJECT", 0, 1, &umr_bitfield_default }, + { "IN_USE_DEC_SELECT_INJECT_DELAY", 2, 2, &umr_bitfield_default }, + { "IN_USE_TRANSFER_ENABLE_ERROR_INJECT", 3, 4, &umr_bitfield_default }, + { "IN_USE_TRANSFER_SELECT_INJECT_DELAY", 5, 5, &umr_bitfield_default }, + { "RETURN_DATA_ENABLE_ERROR_INJECT", 6, 7, &umr_bitfield_default }, + { "RETURN_DATA_SELECT_INJECT_DELAY", 8, 8, &umr_bitfield_default }, + { "RETURN_CONTROL_ENABLE_ERROR_INJECT", 9, 10, &umr_bitfield_default }, + { "RETURN_CONTROL_SELECT_INJECT_DELAY", 11, 11, &umr_bitfield_default }, + { "UC_ATOMIC_FIFO_ENABLE_ERROR_INJECT", 12, 13, &umr_bitfield_default }, + { "UC_ATOMIC_FIFO_SELECT_INJECT_DELAY", 14, 14, &umr_bitfield_default }, + { "WRITE_RETURN_ENABLE_ERROR_INJECT", 15, 16, &umr_bitfield_default }, + { "WRITE_RETURN_SELECT_INJECT_DELAY", 17, 17, &umr_bitfield_default }, + { "WRITE_CACHE_READ_ENABLE_ERROR_INJECT", 18, 19, &umr_bitfield_default }, + { "WRITE_CACHE_READ_SELECT_INJECT_DELAY", 20, 20, &umr_bitfield_default }, + { "SRC_FIFO_ENABLE_ERROR_INJECT", 21, 22, &umr_bitfield_default }, + { "SRC_FIFO_SELECT_INJECT_DELAY", 23, 23, &umr_bitfield_default }, + { "SRC_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT", 24, 25, &umr_bitfield_default }, + { "SRC_FIFO_NEXT_RAM_SELECT_INJECT_DELAY", 26, 26, &umr_bitfield_default }, + { "CACHE_TAG_PROBE_FIFO_ENABLE_ERROR_INJECT", 27, 28, &umr_bitfield_default }, + { "CACHE_TAG_PROBE_FIFO_SELECT_INJECT_DELAY", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCC_DSM_CNTL2B[] = { + { "LATENCY_FIFO_ENABLE_ERROR_INJECT", 0, 1, &umr_bitfield_default }, + { "LATENCY_FIFO_SELECT_INJECT_DELAY", 2, 2, &umr_bitfield_default }, + { "LATENCY_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT", 3, 4, &umr_bitfield_default }, + { "LATENCY_FIFO_NEXT_RAM_SELECT_INJECT_DELAY", 5, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCC_WBINVL2[] = { + { "DONE", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCC_SOFT_RESET[] = { + { "HALT_FOR_RESET", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCA_CTRL[] = { + { "HOLE_TIMEOUT", 0, 3, &umr_bitfield_default }, + { "RB_STILL_4_PHASE", 4, 4, &umr_bitfield_default }, + { "RB_AS_TCI", 5, 5, &umr_bitfield_default }, + { "DISABLE_UTCL2_PRIORITY", 6, 6, &umr_bitfield_default }, + { "DISABLE_RB_ONLY_TCA_ARBITER", 7, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCA_BURST_MASK[] = { + { "ADDR_MASK", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCA_BURST_CTRL[] = { + { "MAX_BURST", 0, 2, &umr_bitfield_default }, + { "RB_DISABLE", 3, 3, &umr_bitfield_default }, + { "TCP_DISABLE", 4, 4, &umr_bitfield_default }, + { "SQC_DISABLE", 5, 5, &umr_bitfield_default }, + { "CPF_DISABLE", 6, 6, &umr_bitfield_default }, + { "CPG_DISABLE", 7, 7, &umr_bitfield_default }, + { "IA_DISABLE", 8, 8, &umr_bitfield_default }, + { "WD_DISABLE", 9, 9, &umr_bitfield_default }, + { "SQG_DISABLE", 10, 10, &umr_bitfield_default }, + { "UTCL2_DISABLE", 11, 11, &umr_bitfield_default }, + { "TPI_DISABLE", 12, 12, &umr_bitfield_default }, + { "RLC_DISABLE", 13, 13, &umr_bitfield_default }, + { "PA_DISABLE", 14, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCA_DSM_CNTL[] = { + { "HOLE_FIFO_SED_IRRITATOR_DATA_SEL", 0, 1, &umr_bitfield_default }, + { "HOLE_FIFO_SED_IRRITATOR_SINGLE_WRITE", 2, 2, &umr_bitfield_default }, + { "REQ_FIFO_SED_IRRITATOR_DATA_SEL", 3, 4, &umr_bitfield_default }, + { "REQ_FIFO_SED_IRRITATOR_SINGLE_WRITE", 5, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCA_DSM_CNTL2[] = { + { "HOLE_FIFO_SED_ENABLE_ERROR_INJECT", 0, 1, &umr_bitfield_default }, + { "HOLE_FIFO_SED_SELECT_INJECT_DELAY", 2, 2, &umr_bitfield_default }, + { "REQ_FIFO_SED_ENABLE_ERROR_INJECT", 3, 4, &umr_bitfield_default }, + { "REQ_FIFO_SED_SELECT_INJECT_DELAY", 5, 5, &umr_bitfield_default }, + { "INJECT_DELAY", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCA_EDC_CNT[] = { + { "HOLE_FIFO_SED_COUNT", 0, 1, &umr_bitfield_default }, + { "REQ_FIFO_SED_COUNT", 2, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_PGM_RSRC3_PS[] = { + { "CU_EN", 0, 15, &umr_bitfield_default }, + { "WAVE_LIMIT", 16, 21, &umr_bitfield_default }, + { "LOCK_LOW_THRESHOLD", 22, 25, &umr_bitfield_default }, + { "SIMD_DISABLE", 26, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_PGM_LO_PS[] = { + { "MEM_BASE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_PGM_HI_PS[] = { + { "MEM_BASE", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_PGM_RSRC1_PS[] = { + { "VGPRS", 0, 5, &umr_bitfield_default }, + { "SGPRS", 6, 9, &umr_bitfield_default }, + { "PRIORITY", 10, 11, &umr_bitfield_default }, + { "FLOAT_MODE", 12, 19, &umr_bitfield_default }, + { "PRIV", 20, 20, &umr_bitfield_default }, + { "DX10_CLAMP", 21, 21, &umr_bitfield_default }, + { "IEEE_MODE", 23, 23, &umr_bitfield_default }, + { "CU_GROUP_DISABLE", 24, 24, &umr_bitfield_default }, + { "FP16_OVFL", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_PGM_RSRC2_PS[] = { + { "SCRATCH_EN", 0, 0, &umr_bitfield_default }, + { "USER_SGPR", 1, 5, &umr_bitfield_default }, + { "TRAP_PRESENT", 6, 6, &umr_bitfield_default }, + { "WAVE_CNT_EN", 7, 7, &umr_bitfield_default }, + { "EXTRA_LDS_SIZE", 8, 15, &umr_bitfield_default }, + { "EXCP_EN", 16, 24, &umr_bitfield_default }, + { "LOAD_COLLISION_WAVEID", 25, 25, &umr_bitfield_default }, + { "LOAD_INTRAWAVE_COLLISION", 26, 26, &umr_bitfield_default }, + { "SKIP_USGPR0", 27, 27, &umr_bitfield_default }, + { "USER_SGPR_MSB", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_0[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_1[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_2[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_3[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_4[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_5[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_6[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_7[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_8[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_9[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_10[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_11[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_12[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_13[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_14[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_15[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_16[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_17[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_18[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_19[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_20[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_21[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_22[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_23[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_24[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_25[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_26[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_27[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_28[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_29[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_30[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_31[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_PGM_RSRC3_VS[] = { + { "CU_EN", 0, 15, &umr_bitfield_default }, + { "WAVE_LIMIT", 16, 21, &umr_bitfield_default }, + { "LOCK_LOW_THRESHOLD", 22, 25, &umr_bitfield_default }, + { "SIMD_DISABLE", 26, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_LATE_ALLOC_VS[] = { + { "LIMIT", 0, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_PGM_LO_VS[] = { + { "MEM_BASE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_PGM_HI_VS[] = { + { "MEM_BASE", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_PGM_RSRC1_VS[] = { + { "VGPRS", 0, 5, &umr_bitfield_default }, + { "SGPRS", 6, 9, &umr_bitfield_default }, + { "PRIORITY", 10, 11, &umr_bitfield_default }, + { "FLOAT_MODE", 12, 19, &umr_bitfield_default }, + { "PRIV", 20, 20, &umr_bitfield_default }, + { "DX10_CLAMP", 21, 21, &umr_bitfield_default }, + { "IEEE_MODE", 23, 23, &umr_bitfield_default }, + { "VGPR_COMP_CNT", 24, 25, &umr_bitfield_default }, + { "CU_GROUP_ENABLE", 26, 26, &umr_bitfield_default }, + { "FP16_OVFL", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_PGM_RSRC2_VS[] = { + { "SCRATCH_EN", 0, 0, &umr_bitfield_default }, + { "USER_SGPR", 1, 5, &umr_bitfield_default }, + { "TRAP_PRESENT", 6, 6, &umr_bitfield_default }, + { "OC_LDS_EN", 7, 7, &umr_bitfield_default }, + { "SO_BASE0_EN", 8, 8, &umr_bitfield_default }, + { "SO_BASE1_EN", 9, 9, &umr_bitfield_default }, + { "SO_BASE2_EN", 10, 10, &umr_bitfield_default }, + { "SO_BASE3_EN", 11, 11, &umr_bitfield_default }, + { "SO_EN", 12, 12, &umr_bitfield_default }, + { "EXCP_EN", 13, 21, &umr_bitfield_default }, + { "PC_BASE_EN", 22, 22, &umr_bitfield_default }, + { "DISPATCH_DRAW_EN", 24, 24, &umr_bitfield_default }, + { "SKIP_USGPR0", 27, 27, &umr_bitfield_default }, + { "USER_SGPR_MSB", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_0[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_1[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_2[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_3[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_4[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_5[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_6[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_7[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_8[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_9[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_10[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_11[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_12[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_13[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_14[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_15[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_16[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_17[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_18[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_19[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_20[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_21[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_22[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_23[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_24[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_25[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_26[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_27[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_28[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_29[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_30[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_31[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_PGM_RSRC2_GS_VS[] = { + { "SCRATCH_EN", 0, 0, &umr_bitfield_default }, + { "USER_SGPR", 1, 5, &umr_bitfield_default }, + { "TRAP_PRESENT", 6, 6, &umr_bitfield_default }, + { "EXCP_EN", 7, 15, &umr_bitfield_default }, + { "VGPR_COMP_CNT", 16, 17, &umr_bitfield_default }, + { "OC_LDS_EN", 18, 18, &umr_bitfield_default }, + { "LDS_SIZE", 19, 26, &umr_bitfield_default }, + { "SKIP_USGPR0", 27, 27, &umr_bitfield_default }, + { "USER_SGPR_MSB", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_PGM_RSRC4_GS[] = { + { "GROUP_FIFO_DEPTH", 0, 6, &umr_bitfield_default }, + { "SPI_SHADER_LATE_ALLOC_GS", 7, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_ADDR_LO_GS[] = { + { "MEM_BASE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_ADDR_HI_GS[] = { + { "MEM_BASE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_PGM_LO_ES[] = { + { "MEM_BASE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_PGM_HI_ES[] = { + { "MEM_BASE", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_PGM_RSRC3_GS[] = { + { "CU_EN", 0, 15, &umr_bitfield_default }, + { "WAVE_LIMIT", 16, 21, &umr_bitfield_default }, + { "LOCK_LOW_THRESHOLD", 22, 25, &umr_bitfield_default }, + { "SIMD_DISABLE", 26, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_PGM_LO_GS[] = { + { "MEM_BASE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_PGM_HI_GS[] = { + { "MEM_BASE", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_PGM_RSRC1_GS[] = { + { "VGPRS", 0, 5, &umr_bitfield_default }, + { "SGPRS", 6, 9, &umr_bitfield_default }, + { "PRIORITY", 10, 11, &umr_bitfield_default }, + { "FLOAT_MODE", 12, 19, &umr_bitfield_default }, + { "PRIV", 20, 20, &umr_bitfield_default }, + { "DX10_CLAMP", 21, 21, &umr_bitfield_default }, + { "IEEE_MODE", 23, 23, &umr_bitfield_default }, + { "CU_GROUP_ENABLE", 24, 24, &umr_bitfield_default }, + { "GS_VGPR_COMP_CNT", 29, 30, &umr_bitfield_default }, + { "FP16_OVFL", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_PGM_RSRC2_GS[] = { + { "SCRATCH_EN", 0, 0, &umr_bitfield_default }, + { "USER_SGPR", 1, 5, &umr_bitfield_default }, + { "TRAP_PRESENT", 6, 6, &umr_bitfield_default }, + { "EXCP_EN", 7, 15, &umr_bitfield_default }, + { "ES_VGPR_COMP_CNT", 16, 17, &umr_bitfield_default }, + { "OC_LDS_EN", 18, 18, &umr_bitfield_default }, + { "LDS_SIZE", 19, 26, &umr_bitfield_default }, + { "SKIP_USGPR0", 27, 27, &umr_bitfield_default }, + { "USER_SGPR_MSB", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_0[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_1[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_2[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_3[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_4[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_5[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_6[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_7[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_8[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_9[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_10[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_11[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_12[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_13[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_14[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_15[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_16[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_17[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_18[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_19[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_20[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_21[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_22[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_23[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_24[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_25[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_26[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_27[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_28[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_29[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_30[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_31[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_PGM_RSRC4_HS[] = { + { "GROUP_FIFO_DEPTH", 0, 6, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_ADDR_LO_HS[] = { + { "MEM_BASE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_ADDR_HI_HS[] = { + { "MEM_BASE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_PGM_LO_LS[] = { + { "MEM_BASE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_PGM_HI_LS[] = { + { "MEM_BASE", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_PGM_RSRC3_HS[] = { + { "WAVE_LIMIT", 0, 5, &umr_bitfield_default }, + { "LOCK_LOW_THRESHOLD", 6, 9, &umr_bitfield_default }, + { "SIMD_DISABLE", 10, 13, &umr_bitfield_default }, + { "CU_EN", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_PGM_LO_HS[] = { + { "MEM_BASE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_PGM_HI_HS[] = { + { "MEM_BASE", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_PGM_RSRC1_HS[] = { + { "VGPRS", 0, 5, &umr_bitfield_default }, + { "SGPRS", 6, 9, &umr_bitfield_default }, + { "PRIORITY", 10, 11, &umr_bitfield_default }, + { "FLOAT_MODE", 12, 19, &umr_bitfield_default }, + { "PRIV", 20, 20, &umr_bitfield_default }, + { "DX10_CLAMP", 21, 21, &umr_bitfield_default }, + { "IEEE_MODE", 23, 23, &umr_bitfield_default }, + { "LS_VGPR_COMP_CNT", 28, 29, &umr_bitfield_default }, + { "FP16_OVFL", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_PGM_RSRC2_HS[] = { + { "SCRATCH_EN", 0, 0, &umr_bitfield_default }, + { "USER_SGPR", 1, 5, &umr_bitfield_default }, + { "TRAP_PRESENT", 6, 6, &umr_bitfield_default }, + { "EXCP_EN", 7, 15, &umr_bitfield_default }, + { "LDS_SIZE", 16, 24, &umr_bitfield_default }, + { "SKIP_USGPR0", 27, 27, &umr_bitfield_default }, + { "USER_SGPR_MSB", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_0[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_1[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_2[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_3[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_4[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_5[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_6[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_7[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_8[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_9[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_10[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_11[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_12[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_13[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_14[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_15[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_16[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_17[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_18[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_19[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_20[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_21[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_22[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_23[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_24[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_25[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_26[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_27[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_28[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_29[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_30[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_31[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_COMMON_0[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_COMMON_1[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_COMMON_2[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_COMMON_3[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_COMMON_4[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_COMMON_5[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_COMMON_6[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_COMMON_7[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_COMMON_8[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_COMMON_9[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_COMMON_10[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_COMMON_11[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_COMMON_12[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_COMMON_13[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_COMMON_14[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_COMMON_15[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_COMMON_16[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_COMMON_17[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_COMMON_18[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_COMMON_19[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_COMMON_20[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_COMMON_21[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_COMMON_22[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_COMMON_23[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_COMMON_24[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_COMMON_25[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_COMMON_26[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_COMMON_27[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_COMMON_28[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_COMMON_29[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_COMMON_30[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_USER_DATA_COMMON_31[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCOMPUTE_DISPATCH_INITIATOR[] = { + { "COMPUTE_SHADER_EN", 0, 0, &umr_bitfield_default }, + { "PARTIAL_TG_EN", 1, 1, &umr_bitfield_default }, + { "FORCE_START_AT_000", 2, 2, &umr_bitfield_default }, + { "ORDERED_APPEND_ENBL", 3, 3, &umr_bitfield_default }, + { "ORDERED_APPEND_MODE", 4, 4, &umr_bitfield_default }, + { "USE_THREAD_DIMENSIONS", 5, 5, &umr_bitfield_default }, + { "ORDER_MODE", 6, 6, &umr_bitfield_default }, + { "SCALAR_L1_INV_VOL", 10, 10, &umr_bitfield_default }, + { "VECTOR_L1_INV_VOL", 11, 11, &umr_bitfield_default }, + { "RESERVED", 12, 12, &umr_bitfield_default }, + { "RESTORE", 14, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCOMPUTE_DIM_X[] = { + { "SIZE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCOMPUTE_DIM_Y[] = { + { "SIZE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCOMPUTE_DIM_Z[] = { + { "SIZE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCOMPUTE_START_X[] = { + { "START", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCOMPUTE_START_Y[] = { + { "START", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCOMPUTE_START_Z[] = { + { "START", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCOMPUTE_NUM_THREAD_X[] = { + { "NUM_THREAD_FULL", 0, 15, &umr_bitfield_default }, + { "NUM_THREAD_PARTIAL", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCOMPUTE_NUM_THREAD_Y[] = { + { "NUM_THREAD_FULL", 0, 15, &umr_bitfield_default }, + { "NUM_THREAD_PARTIAL", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCOMPUTE_NUM_THREAD_Z[] = { + { "NUM_THREAD_FULL", 0, 15, &umr_bitfield_default }, + { "NUM_THREAD_PARTIAL", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCOMPUTE_PIPELINESTAT_ENABLE[] = { + { "PIPELINESTAT_ENABLE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCOMPUTE_PERFCOUNT_ENABLE[] = { + { "PERFCOUNT_ENABLE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCOMPUTE_PGM_LO[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCOMPUTE_PGM_HI[] = { + { "DATA", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCOMPUTE_DISPATCH_PKT_ADDR_LO[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCOMPUTE_DISPATCH_PKT_ADDR_HI[] = { + { "DATA", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCOMPUTE_DISPATCH_SCRATCH_BASE_LO[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCOMPUTE_DISPATCH_SCRATCH_BASE_HI[] = { + { "DATA", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCOMPUTE_PGM_RSRC1[] = { + { "VGPRS", 0, 5, &umr_bitfield_default }, + { "SGPRS", 6, 9, &umr_bitfield_default }, + { "PRIORITY", 10, 11, &umr_bitfield_default }, + { "FLOAT_MODE", 12, 19, &umr_bitfield_default }, + { "PRIV", 20, 20, &umr_bitfield_default }, + { "DX10_CLAMP", 21, 21, &umr_bitfield_default }, + { "IEEE_MODE", 23, 23, &umr_bitfield_default }, + { "BULKY", 24, 24, &umr_bitfield_default }, + { "FP16_OVFL", 26, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCOMPUTE_PGM_RSRC2[] = { + { "SCRATCH_EN", 0, 0, &umr_bitfield_default }, + { "USER_SGPR", 1, 5, &umr_bitfield_default }, + { "TRAP_PRESENT", 6, 6, &umr_bitfield_default }, + { "TGID_X_EN", 7, 7, &umr_bitfield_default }, + { "TGID_Y_EN", 8, 8, &umr_bitfield_default }, + { "TGID_Z_EN", 9, 9, &umr_bitfield_default }, + { "TG_SIZE_EN", 10, 10, &umr_bitfield_default }, + { "TIDIG_COMP_CNT", 11, 12, &umr_bitfield_default }, + { "EXCP_EN_MSB", 13, 14, &umr_bitfield_default }, + { "LDS_SIZE", 15, 23, &umr_bitfield_default }, + { "EXCP_EN", 24, 30, &umr_bitfield_default }, + { "SKIP_USGPR0", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCOMPUTE_VMID[] = { + { "DATA", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCOMPUTE_RESOURCE_LIMITS[] = { + { "WAVES_PER_SH", 0, 9, &umr_bitfield_default }, + { "TG_PER_CU", 12, 15, &umr_bitfield_default }, + { "LOCK_THRESHOLD", 16, 21, &umr_bitfield_default }, + { "SIMD_DEST_CNTL", 22, 22, &umr_bitfield_default }, + { "FORCE_SIMD_DIST", 23, 23, &umr_bitfield_default }, + { "CU_GROUP_COUNT", 24, 26, &umr_bitfield_default }, + { "SIMD_DISABLE", 27, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCOMPUTE_STATIC_THREAD_MGMT_SE0[] = { + { "SH0_CU_EN", 0, 15, &umr_bitfield_default }, + { "SH1_CU_EN", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCOMPUTE_STATIC_THREAD_MGMT_SE1[] = { + { "SH0_CU_EN", 0, 15, &umr_bitfield_default }, + { "SH1_CU_EN", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCOMPUTE_TMPRING_SIZE[] = { + { "WAVES", 0, 11, &umr_bitfield_default }, + { "WAVESIZE", 12, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCOMPUTE_STATIC_THREAD_MGMT_SE2[] = { + { "SH0_CU_EN", 0, 15, &umr_bitfield_default }, + { "SH1_CU_EN", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCOMPUTE_STATIC_THREAD_MGMT_SE3[] = { + { "SH0_CU_EN", 0, 15, &umr_bitfield_default }, + { "SH1_CU_EN", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCOMPUTE_RESTART_X[] = { + { "RESTART", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCOMPUTE_RESTART_Y[] = { + { "RESTART", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCOMPUTE_RESTART_Z[] = { + { "RESTART", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCOMPUTE_THREAD_TRACE_ENABLE[] = { + { "THREAD_TRACE_ENABLE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCOMPUTE_MISC_RESERVED[] = { + { "SEND_SEID", 0, 1, &umr_bitfield_default }, + { "RESERVED2", 2, 2, &umr_bitfield_default }, + { "RESERVED3", 3, 3, &umr_bitfield_default }, + { "RESERVED4", 4, 4, &umr_bitfield_default }, + { "WAVE_ID_BASE", 5, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCOMPUTE_DISPATCH_ID[] = { + { "DISPATCH_ID", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCOMPUTE_THREADGROUP_ID[] = { + { "THREADGROUP_ID", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCOMPUTE_RELAUNCH[] = { + { "PAYLOAD", 0, 29, &umr_bitfield_default }, + { "IS_EVENT", 30, 30, &umr_bitfield_default }, + { "IS_STATE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCOMPUTE_WAVE_RESTORE_ADDR_LO[] = { + { "ADDR", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCOMPUTE_WAVE_RESTORE_ADDR_HI[] = { + { "ADDR", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCOMPUTE_USER_DATA_0[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCOMPUTE_USER_DATA_1[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCOMPUTE_USER_DATA_2[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCOMPUTE_USER_DATA_3[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCOMPUTE_USER_DATA_4[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCOMPUTE_USER_DATA_5[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCOMPUTE_USER_DATA_6[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCOMPUTE_USER_DATA_7[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCOMPUTE_USER_DATA_8[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCOMPUTE_USER_DATA_9[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCOMPUTE_USER_DATA_10[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCOMPUTE_USER_DATA_11[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCOMPUTE_USER_DATA_12[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCOMPUTE_USER_DATA_13[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCOMPUTE_USER_DATA_14[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCOMPUTE_USER_DATA_15[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCOMPUTE_NOWHERE[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_DFY_CNTL[] = { + { "POLICY", 0, 0, &umr_bitfield_default }, + { "MTYPE", 2, 3, &umr_bitfield_default }, + { "TPI_SDP_SEL", 26, 26, &umr_bitfield_default }, + { "LFSR_RESET", 28, 28, &umr_bitfield_default }, + { "MODE", 29, 30, &umr_bitfield_default }, + { "ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_DFY_STAT[] = { + { "BURST_COUNT", 0, 15, &umr_bitfield_default }, + { "TAGS_PENDING", 16, 26, &umr_bitfield_default }, + { "BUSY", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_DFY_ADDR_HI[] = { + { "ADDR_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_DFY_ADDR_LO[] = { + { "ADDR_LO", 5, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_DFY_DATA_0[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_DFY_DATA_1[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_DFY_DATA_2[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_DFY_DATA_3[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_DFY_DATA_4[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_DFY_DATA_5[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_DFY_DATA_6[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_DFY_DATA_7[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_DFY_DATA_8[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_DFY_DATA_9[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_DFY_DATA_10[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_DFY_DATA_11[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_DFY_DATA_12[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_DFY_DATA_13[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_DFY_DATA_14[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_DFY_DATA_15[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_DFY_CMD[] = { + { "OFFSET", 0, 8, &umr_bitfield_default }, + { "SIZE", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_EOPQ_WAIT_TIME[] = { + { "WAIT_TIME", 0, 9, &umr_bitfield_default }, + { "SCALE_COUNT", 10, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_CPC_MGCG_SYNC_CNTL[] = { + { "COOLDOWN_PERIOD", 0, 7, &umr_bitfield_default }, + { "WARMUP_PERIOD", 8, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCPC_INT_INFO[] = { + { "ADDR_HI", 0, 15, &umr_bitfield_default }, + { "TYPE", 16, 16, &umr_bitfield_default }, + { "VMID", 20, 23, &umr_bitfield_default }, + { "QUEUE_ID", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_VIRT_STATUS[] = { + { "VIRT_STATUS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCPC_INT_ADDR[] = { + { "ADDR", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCPC_INT_PASID[] = { + { "PASID", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_GFX_ERROR[] = { + { "EDC_ERROR_ID", 0, 3, &umr_bitfield_default }, + { "SUA_ERROR", 4, 4, &umr_bitfield_default }, + { "RSVD1_ERROR", 5, 5, &umr_bitfield_default }, + { "RSVD2_ERROR", 6, 6, &umr_bitfield_default }, + { "SEM_UTCL1_ERROR", 7, 7, &umr_bitfield_default }, + { "QU_STRM_UTCL1_ERROR", 8, 8, &umr_bitfield_default }, + { "QU_EOP_UTCL1_ERROR", 9, 9, &umr_bitfield_default }, + { "QU_PIPE_UTCL1_ERROR", 10, 10, &umr_bitfield_default }, + { "QU_READ_UTCL1_ERROR", 11, 11, &umr_bitfield_default }, + { "SYNC_MEMRD_UTCL1_ERROR", 12, 12, &umr_bitfield_default }, + { "SYNC_MEMWR_UTCL1_ERROR", 13, 13, &umr_bitfield_default }, + { "SHADOW_UTCL1_ERROR", 14, 14, &umr_bitfield_default }, + { "APPEND_UTCL1_ERROR", 15, 15, &umr_bitfield_default }, + { "CE_DMA_UTCL1_ERROR", 16, 16, &umr_bitfield_default }, + { "PFP_VGTDMA_UTCL1_ERROR", 17, 17, &umr_bitfield_default }, + { "DMA_SRC_UTCL1_ERROR", 18, 18, &umr_bitfield_default }, + { "DMA_DST_UTCL1_ERROR", 19, 19, &umr_bitfield_default }, + { "PFP_TC_UTCL1_ERROR", 20, 20, &umr_bitfield_default }, + { "ME_TC_UTCL1_ERROR", 21, 21, &umr_bitfield_default }, + { "CE_TC_UTCL1_ERROR", 22, 22, &umr_bitfield_default }, + { "PRT_LOD_UTCL1_ERROR", 23, 23, &umr_bitfield_default }, + { "RDPTR_RPT_UTCL1_ERROR", 24, 24, &umr_bitfield_default }, + { "RB_FETCHER_UTCL1_ERROR", 25, 25, &umr_bitfield_default }, + { "I1_FETCHER_UTCL1_ERROR", 26, 26, &umr_bitfield_default }, + { "I2_FETCHER_UTCL1_ERROR", 27, 27, &umr_bitfield_default }, + { "C1_FETCHER_UTCL1_ERROR", 28, 28, &umr_bitfield_default }, + { "C2_FETCHER_UTCL1_ERROR", 29, 29, &umr_bitfield_default }, + { "ST_FETCHER_UTCL1_ERROR", 30, 30, &umr_bitfield_default }, + { "CE_INIT_UTCL1_ERROR", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCPG_UTCL1_CNTL[] = { + { "XNACK_REDO_TIMER_CNT", 0, 19, &umr_bitfield_default }, + { "VMID_RESET_MODE", 23, 23, &umr_bitfield_default }, + { "DROP_MODE", 24, 24, &umr_bitfield_default }, + { "BYPASS", 25, 25, &umr_bitfield_default }, + { "INVALIDATE", 26, 26, &umr_bitfield_default }, + { "FRAG_LIMIT_MODE", 27, 27, &umr_bitfield_default }, + { "FORCE_SNOOP", 28, 28, &umr_bitfield_default }, + { "FORCE_SD_VMID_DIRTY", 29, 29, &umr_bitfield_default }, + { "MTYPE_NO_PTE_MODE", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCPC_UTCL1_CNTL[] = { + { "XNACK_REDO_TIMER_CNT", 0, 19, &umr_bitfield_default }, + { "DROP_MODE", 24, 24, &umr_bitfield_default }, + { "BYPASS", 25, 25, &umr_bitfield_default }, + { "INVALIDATE", 26, 26, &umr_bitfield_default }, + { "FRAG_LIMIT_MODE", 27, 27, &umr_bitfield_default }, + { "FORCE_SNOOP", 28, 28, &umr_bitfield_default }, + { "FORCE_SD_VMID_DIRTY", 29, 29, &umr_bitfield_default }, + { "MTYPE_NO_PTE_MODE", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCPF_UTCL1_CNTL[] = { + { "XNACK_REDO_TIMER_CNT", 0, 19, &umr_bitfield_default }, + { "VMID_RESET_MODE", 23, 23, &umr_bitfield_default }, + { "DROP_MODE", 24, 24, &umr_bitfield_default }, + { "BYPASS", 25, 25, &umr_bitfield_default }, + { "INVALIDATE", 26, 26, &umr_bitfield_default }, + { "FRAG_LIMIT_MODE", 27, 27, &umr_bitfield_default }, + { "FORCE_SNOOP", 28, 28, &umr_bitfield_default }, + { "FORCE_SD_VMID_DIRTY", 29, 29, &umr_bitfield_default }, + { "MTYPE_NO_PTE_MODE", 30, 30, &umr_bitfield_default }, + { "FORCE_NO_EXE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_AQL_SMM_STATUS[] = { + { "AQL_QUEUE_SMM", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_RB0_BASE[] = { + { "RB_BASE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_RB_BASE[] = { + { "RB_BASE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_RB0_CNTL[] = { + { "RB_BUFSZ", 0, 5, &umr_bitfield_default }, + { "RB_BLKSZ", 8, 13, &umr_bitfield_default }, + { "BUF_SWAP", 17, 18, &umr_bitfield_default }, + { "MIN_AVAILSZ", 20, 21, &umr_bitfield_default }, + { "MIN_IB_AVAILSZ", 22, 23, &umr_bitfield_default }, + { "CACHE_POLICY", 24, 24, &umr_bitfield_default }, + { "RB_NO_UPDATE", 27, 27, &umr_bitfield_default }, + { "RB_RPTR_WR_ENA", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_RB_CNTL[] = { + { "RB_BUFSZ", 0, 5, &umr_bitfield_default }, + { "RB_BLKSZ", 8, 13, &umr_bitfield_default }, + { "MIN_AVAILSZ", 20, 21, &umr_bitfield_default }, + { "MIN_IB_AVAILSZ", 22, 23, &umr_bitfield_default }, + { "CACHE_POLICY", 24, 24, &umr_bitfield_default }, + { "RB_NO_UPDATE", 27, 27, &umr_bitfield_default }, + { "RB_RPTR_WR_ENA", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_RB_RPTR_WR[] = { + { "RB_RPTR_WR", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_RB0_RPTR_ADDR[] = { + { "RB_RPTR_ADDR", 2, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_RB_RPTR_ADDR[] = { + { "RB_RPTR_ADDR", 2, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_RB0_RPTR_ADDR_HI[] = { + { "RB_RPTR_ADDR_HI", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_RB_RPTR_ADDR_HI[] = { + { "RB_RPTR_ADDR_HI", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_RB0_BUFSZ_MASK[] = { + { "DATA", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_RB_BUFSZ_MASK[] = { + { "DATA", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_RB_WPTR_POLL_ADDR_LO[] = { + { "RB_WPTR_POLL_ADDR_LO", 2, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_RB_WPTR_POLL_ADDR_HI[] = { + { "RB_WPTR_POLL_ADDR_HI", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_INT_CNTL[] = { + { "CP_VM_DOORBELL_WR_INT_ENABLE", 11, 11, &umr_bitfield_default }, + { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default }, + { "GPF_INT_ENABLE", 16, 16, &umr_bitfield_default }, + { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default }, + { "CMP_BUSY_INT_ENABLE", 18, 18, &umr_bitfield_default }, + { "CNTX_BUSY_INT_ENABLE", 19, 19, &umr_bitfield_default }, + { "CNTX_EMPTY_INT_ENABLE", 20, 20, &umr_bitfield_default }, + { "GFX_IDLE_INT_ENABLE", 21, 21, &umr_bitfield_default }, + { "PRIV_INSTR_INT_ENABLE", 22, 22, &umr_bitfield_default }, + { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default }, + { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default }, + { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default }, + { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default }, + { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default }, + { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default }, + { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_INT_STATUS[] = { + { "CP_VM_DOORBELL_WR_INT_STAT", 11, 11, &umr_bitfield_default }, + { "CP_ECC_ERROR_INT_STAT", 14, 14, &umr_bitfield_default }, + { "GPF_INT_STAT", 16, 16, &umr_bitfield_default }, + { "WRM_POLL_TIMEOUT_INT_STAT", 17, 17, &umr_bitfield_default }, + { "CMP_BUSY_INT_STAT", 18, 18, &umr_bitfield_default }, + { "CNTX_BUSY_INT_STAT", 19, 19, &umr_bitfield_default }, + { "CNTX_EMPTY_INT_STAT", 20, 20, &umr_bitfield_default }, + { "GFX_IDLE_INT_STAT", 21, 21, &umr_bitfield_default }, + { "PRIV_INSTR_INT_STAT", 22, 22, &umr_bitfield_default }, + { "PRIV_REG_INT_STAT", 23, 23, &umr_bitfield_default }, + { "OPCODE_ERROR_INT_STAT", 24, 24, &umr_bitfield_default }, + { "TIME_STAMP_INT_STAT", 26, 26, &umr_bitfield_default }, + { "RESERVED_BIT_ERROR_INT_STAT", 27, 27, &umr_bitfield_default }, + { "GENERIC2_INT_STAT", 29, 29, &umr_bitfield_default }, + { "GENERIC1_INT_STAT", 30, 30, &umr_bitfield_default }, + { "GENERIC0_INT_STAT", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_DEVICE_ID[] = { + { "DEVICE_ID", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ME0_PIPE_PRIORITY_CNTS[] = { + { "PRIORITY1_CNT", 0, 7, &umr_bitfield_default }, + { "PRIORITY2A_CNT", 8, 15, &umr_bitfield_default }, + { "PRIORITY2B_CNT", 16, 23, &umr_bitfield_default }, + { "PRIORITY3_CNT", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_RING_PRIORITY_CNTS[] = { + { "PRIORITY1_CNT", 0, 7, &umr_bitfield_default }, + { "PRIORITY2A_CNT", 8, 15, &umr_bitfield_default }, + { "PRIORITY2B_CNT", 16, 23, &umr_bitfield_default }, + { "PRIORITY3_CNT", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ME0_PIPE0_PRIORITY[] = { + { "PRIORITY", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_RING0_PRIORITY[] = { + { "PRIORITY", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ME0_PIPE1_PRIORITY[] = { + { "PRIORITY", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_RING1_PRIORITY[] = { + { "PRIORITY", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ME0_PIPE2_PRIORITY[] = { + { "PRIORITY", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_RING2_PRIORITY[] = { + { "PRIORITY", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_FATAL_ERROR[] = { + { "CPF_FATAL_ERROR", 0, 0, &umr_bitfield_default }, + { "CPG_FATAL_ERROR", 1, 1, &umr_bitfield_default }, + { "GFX_HALT_PROC", 2, 2, &umr_bitfield_default }, + { "DIS_CPG_FATAL_ERROR", 3, 3, &umr_bitfield_default }, + { "CPG_TAG_FATAL_ERROR_EN", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_RB_VMID[] = { + { "RB0_VMID", 0, 3, &umr_bitfield_default }, + { "RB1_VMID", 8, 11, &umr_bitfield_default }, + { "RB2_VMID", 16, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ME0_PIPE0_VMID[] = { + { "VMID", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ME0_PIPE1_VMID[] = { + { "VMID", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_RB0_WPTR[] = { + { "RB_WPTR", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_RB_WPTR[] = { + { "RB_WPTR", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_RB0_WPTR_HI[] = { + { "RB_WPTR", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_RB_WPTR_HI[] = { + { "RB_WPTR", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_RB1_WPTR[] = { + { "RB_WPTR", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_RB1_WPTR_HI[] = { + { "RB_WPTR", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_RB2_WPTR[] = { + { "RB_WPTR", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_RB_DOORBELL_CONTROL[] = { + { "DOORBELL_BIF_DROP", 1, 1, &umr_bitfield_default }, + { "DOORBELL_OFFSET", 2, 27, &umr_bitfield_default }, + { "DOORBELL_EN", 30, 30, &umr_bitfield_default }, + { "DOORBELL_HIT", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_RB_DOORBELL_RANGE_LOWER[] = { + { "DOORBELL_RANGE_LOWER", 2, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_RB_DOORBELL_RANGE_UPPER[] = { + { "DOORBELL_RANGE_UPPER", 2, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_MEC_DOORBELL_RANGE_LOWER[] = { + { "DOORBELL_RANGE_LOWER", 2, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_MEC_DOORBELL_RANGE_UPPER[] = { + { "DOORBELL_RANGE_UPPER", 2, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCPG_UTCL1_ERROR[] = { + { "ERROR_DETECTED_HALT", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCPC_UTCL1_ERROR[] = { + { "ERROR_DETECTED_HALT", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_RB1_BASE[] = { + { "RB_BASE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_RB1_CNTL[] = { + { "RB_BUFSZ", 0, 5, &umr_bitfield_default }, + { "RB_BLKSZ", 8, 13, &umr_bitfield_default }, + { "MIN_AVAILSZ", 20, 21, &umr_bitfield_default }, + { "MIN_IB_AVAILSZ", 22, 23, &umr_bitfield_default }, + { "CACHE_POLICY", 24, 24, &umr_bitfield_default }, + { "RB_NO_UPDATE", 27, 27, &umr_bitfield_default }, + { "RB_RPTR_WR_ENA", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_RB1_RPTR_ADDR[] = { + { "RB_RPTR_ADDR", 2, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_RB1_RPTR_ADDR_HI[] = { + { "RB_RPTR_ADDR_HI", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_RB2_BASE[] = { + { "RB_BASE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_RB2_CNTL[] = { + { "RB_BUFSZ", 0, 5, &umr_bitfield_default }, + { "RB_BLKSZ", 8, 13, &umr_bitfield_default }, + { "MIN_AVAILSZ", 20, 21, &umr_bitfield_default }, + { "MIN_IB_AVAILSZ", 22, 23, &umr_bitfield_default }, + { "CACHE_POLICY", 24, 24, &umr_bitfield_default }, + { "RB_NO_UPDATE", 27, 27, &umr_bitfield_default }, + { "RB_RPTR_WR_ENA", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_RB2_RPTR_ADDR[] = { + { "RB_RPTR_ADDR", 2, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_RB2_RPTR_ADDR_HI[] = { + { "RB_RPTR_ADDR_HI", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_RB0_ACTIVE[] = { + { "ACTIVE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_RB_ACTIVE[] = { + { "ACTIVE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_INT_CNTL_RING0[] = { + { "CP_VM_DOORBELL_WR_INT_ENABLE", 11, 11, &umr_bitfield_default }, + { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default }, + { "GPF_INT_ENABLE", 16, 16, &umr_bitfield_default }, + { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default }, + { "CMP_BUSY_INT_ENABLE", 18, 18, &umr_bitfield_default }, + { "CNTX_BUSY_INT_ENABLE", 19, 19, &umr_bitfield_default }, + { "CNTX_EMPTY_INT_ENABLE", 20, 20, &umr_bitfield_default }, + { "GFX_IDLE_INT_ENABLE", 21, 21, &umr_bitfield_default }, + { "PRIV_INSTR_INT_ENABLE", 22, 22, &umr_bitfield_default }, + { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default }, + { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default }, + { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default }, + { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default }, + { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default }, + { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default }, + { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_INT_CNTL_RING1[] = { + { "CP_VM_DOORBELL_WR_INT_ENABLE", 11, 11, &umr_bitfield_default }, + { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default }, + { "GPF_INT_ENABLE", 16, 16, &umr_bitfield_default }, + { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default }, + { "CMP_BUSY_INT_ENABLE", 18, 18, &umr_bitfield_default }, + { "CNTX_BUSY_INT_ENABLE", 19, 19, &umr_bitfield_default }, + { "CNTX_EMPTY_INT_ENABLE", 20, 20, &umr_bitfield_default }, + { "GFX_IDLE_INT_ENABLE", 21, 21, &umr_bitfield_default }, + { "PRIV_INSTR_INT_ENABLE", 22, 22, &umr_bitfield_default }, + { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default }, + { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default }, + { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default }, + { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default }, + { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default }, + { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default }, + { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_INT_CNTL_RING2[] = { + { "CP_VM_DOORBELL_WR_INT_ENABLE", 11, 11, &umr_bitfield_default }, + { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default }, + { "GPF_INT_ENABLE", 16, 16, &umr_bitfield_default }, + { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default }, + { "CMP_BUSY_INT_ENABLE", 18, 18, &umr_bitfield_default }, + { "CNTX_BUSY_INT_ENABLE", 19, 19, &umr_bitfield_default }, + { "CNTX_EMPTY_INT_ENABLE", 20, 20, &umr_bitfield_default }, + { "GFX_IDLE_INT_ENABLE", 21, 21, &umr_bitfield_default }, + { "PRIV_INSTR_INT_ENABLE", 22, 22, &umr_bitfield_default }, + { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default }, + { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default }, + { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default }, + { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default }, + { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default }, + { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default }, + { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_INT_STATUS_RING0[] = { + { "CP_VM_DOORBELL_WR_INT_STAT", 11, 11, &umr_bitfield_default }, + { "CP_ECC_ERROR_INT_STAT", 14, 14, &umr_bitfield_default }, + { "GPF_INT_STAT", 16, 16, &umr_bitfield_default }, + { "WRM_POLL_TIMEOUT_INT_STAT", 17, 17, &umr_bitfield_default }, + { "CMP_BUSY_INT_STAT", 18, 18, &umr_bitfield_default }, + { "GCNTX_BUSY_INT_STAT", 19, 19, &umr_bitfield_default }, + { "CNTX_EMPTY_INT_STAT", 20, 20, &umr_bitfield_default }, + { "GFX_IDLE_INT_STAT", 21, 21, &umr_bitfield_default }, + { "PRIV_INSTR_INT_STAT", 22, 22, &umr_bitfield_default }, + { "PRIV_REG_INT_STAT", 23, 23, &umr_bitfield_default }, + { "OPCODE_ERROR_INT_STAT", 24, 24, &umr_bitfield_default }, + { "TIME_STAMP_INT_STAT", 26, 26, &umr_bitfield_default }, + { "RESERVED_BIT_ERROR_INT_STAT", 27, 27, &umr_bitfield_default }, + { "GENERIC2_INT_STAT", 29, 29, &umr_bitfield_default }, + { "GENERIC1_INT_STAT", 30, 30, &umr_bitfield_default }, + { "GENERIC0_INT_STAT", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_INT_STATUS_RING1[] = { + { "CP_VM_DOORBELL_WR_INT_STAT", 11, 11, &umr_bitfield_default }, + { "CP_ECC_ERROR_INT_STAT", 14, 14, &umr_bitfield_default }, + { "GPF_INT_STAT", 16, 16, &umr_bitfield_default }, + { "WRM_POLL_TIMEOUT_INT_STAT", 17, 17, &umr_bitfield_default }, + { "CMP_BUSY_INT_STAT", 18, 18, &umr_bitfield_default }, + { "CNTX_BUSY_INT_STAT", 19, 19, &umr_bitfield_default }, + { "CNTX_EMPTY_INT_STAT", 20, 20, &umr_bitfield_default }, + { "GFX_IDLE_INT_STAT", 21, 21, &umr_bitfield_default }, + { "PRIV_INSTR_INT_STAT", 22, 22, &umr_bitfield_default }, + { "PRIV_REG_INT_STAT", 23, 23, &umr_bitfield_default }, + { "OPCODE_ERROR_INT_STAT", 24, 24, &umr_bitfield_default }, + { "TIME_STAMP_INT_STAT", 26, 26, &umr_bitfield_default }, + { "RESERVED_BIT_ERROR_INT_STAT", 27, 27, &umr_bitfield_default }, + { "GENERIC2_INT_STAT", 29, 29, &umr_bitfield_default }, + { "GENERIC1_INT_STAT", 30, 30, &umr_bitfield_default }, + { "GENERIC0_INT_STAT", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_INT_STATUS_RING2[] = { + { "CP_VM_DOORBELL_WR_INT_STAT", 11, 11, &umr_bitfield_default }, + { "CP_ECC_ERROR_INT_STAT", 14, 14, &umr_bitfield_default }, + { "GPF_INT_STAT", 16, 16, &umr_bitfield_default }, + { "WRM_POLL_TIMEOUT_INT_STAT", 17, 17, &umr_bitfield_default }, + { "CMP_BUSY_INT_STAT", 18, 18, &umr_bitfield_default }, + { "CNTX_BUSY_INT_STAT", 19, 19, &umr_bitfield_default }, + { "CNTX_EMPTY_INT_STAT", 20, 20, &umr_bitfield_default }, + { "GFX_IDLE_INT_STAT", 21, 21, &umr_bitfield_default }, + { "PRIV_INSTR_INT_STAT", 22, 22, &umr_bitfield_default }, + { "PRIV_REG_INT_STAT", 23, 23, &umr_bitfield_default }, + { "OPCODE_ERROR_INT_STAT", 24, 24, &umr_bitfield_default }, + { "TIME_STAMP_INT_STAT", 26, 26, &umr_bitfield_default }, + { "RESERVED_BIT_ERROR_INT_STAT", 27, 27, &umr_bitfield_default }, + { "GENERIC2_INT_STAT", 29, 29, &umr_bitfield_default }, + { "GENERIC1_INT_STAT", 30, 30, &umr_bitfield_default }, + { "GENERIC0_INT_STAT", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_PWR_CNTL[] = { + { "GFX_CLK_HALT_ME0_PIPE0", 0, 0, &umr_bitfield_default }, + { "GFX_CLK_HALT_ME0_PIPE1", 1, 1, &umr_bitfield_default }, + { "CMP_CLK_HALT_ME1_PIPE0", 8, 8, &umr_bitfield_default }, + { "CMP_CLK_HALT_ME1_PIPE1", 9, 9, &umr_bitfield_default }, + { "CMP_CLK_HALT_ME1_PIPE2", 10, 10, &umr_bitfield_default }, + { "CMP_CLK_HALT_ME1_PIPE3", 11, 11, &umr_bitfield_default }, + { "CMP_CLK_HALT_ME2_PIPE0", 16, 16, &umr_bitfield_default }, + { "CMP_CLK_HALT_ME2_PIPE1", 17, 17, &umr_bitfield_default }, + { "CMP_CLK_HALT_ME2_PIPE2", 18, 18, &umr_bitfield_default }, + { "CMP_CLK_HALT_ME2_PIPE3", 19, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_MEM_SLP_CNTL[] = { + { "CP_MEM_LS_EN", 0, 0, &umr_bitfield_default }, + { "CP_MEM_DS_EN", 1, 1, &umr_bitfield_default }, + { "RESERVED", 2, 6, &umr_bitfield_default }, + { "CP_LS_DS_BUSY_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "CP_MEM_LS_ON_DELAY", 8, 15, &umr_bitfield_default }, + { "CP_MEM_LS_OFF_DELAY", 16, 23, &umr_bitfield_default }, + { "RESERVED1", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ECC_FIRSTOCCURRENCE[] = { + { "INTERFACE", 0, 1, &umr_bitfield_default }, + { "CLIENT", 4, 7, &umr_bitfield_default }, + { "ME", 8, 9, &umr_bitfield_default }, + { "PIPE", 10, 11, &umr_bitfield_default }, + { "QUEUE", 12, 14, &umr_bitfield_default }, + { "VMID", 16, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ECC_FIRSTOCCURRENCE_RING0[] = { + { "OBSOLETE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ECC_FIRSTOCCURRENCE_RING1[] = { + { "OBSOLETE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ECC_FIRSTOCCURRENCE_RING2[] = { + { "OBSOLETE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGB_EDC_MODE[] = { + { "FORCE_SEC_ON_DED", 15, 15, &umr_bitfield_default }, + { "COUNT_FED_OUT", 16, 16, &umr_bitfield_default }, + { "GATE_FUE", 17, 17, &umr_bitfield_default }, + { "DED_MODE", 20, 21, &umr_bitfield_default }, + { "PROP_FED", 29, 29, &umr_bitfield_default }, + { "BYPASS", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_PQ_WPTR_POLL_CNTL[] = { + { "PERIOD", 0, 7, &umr_bitfield_default }, + { "DISABLE_PEND_REQ_ONE_SHOT", 29, 29, &umr_bitfield_default }, + { "POLL_ACTIVE", 30, 30, &umr_bitfield_default }, + { "EN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_PQ_WPTR_POLL_CNTL1[] = { + { "QUEUE_MASK", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ME1_PIPE0_INT_CNTL[] = { + { "CMP_QUERY_STATUS_INT_ENABLE", 12, 12, &umr_bitfield_default }, + { "DEQUEUE_REQUEST_INT_ENABLE", 13, 13, &umr_bitfield_default }, + { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default }, + { "SUA_VIOLATION_INT_ENABLE", 15, 15, &umr_bitfield_default }, + { "GPF_INT_ENABLE", 16, 16, &umr_bitfield_default }, + { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default }, + { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default }, + { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default }, + { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default }, + { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default }, + { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default }, + { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default }, + { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ME1_PIPE1_INT_CNTL[] = { + { "CMP_QUERY_STATUS_INT_ENABLE", 12, 12, &umr_bitfield_default }, + { "DEQUEUE_REQUEST_INT_ENABLE", 13, 13, &umr_bitfield_default }, + { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default }, + { "SUA_VIOLATION_INT_ENABLE", 15, 15, &umr_bitfield_default }, + { "GPF_INT_ENABLE", 16, 16, &umr_bitfield_default }, + { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default }, + { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default }, + { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default }, + { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default }, + { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default }, + { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default }, + { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default }, + { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ME1_PIPE2_INT_CNTL[] = { + { "CMP_QUERY_STATUS_INT_ENABLE", 12, 12, &umr_bitfield_default }, + { "DEQUEUE_REQUEST_INT_ENABLE", 13, 13, &umr_bitfield_default }, + { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default }, + { "SUA_VIOLATION_INT_ENABLE", 15, 15, &umr_bitfield_default }, + { "GPF_INT_ENABLE", 16, 16, &umr_bitfield_default }, + { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default }, + { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default }, + { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default }, + { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default }, + { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default }, + { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default }, + { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default }, + { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ME1_PIPE3_INT_CNTL[] = { + { "CMP_QUERY_STATUS_INT_ENABLE", 12, 12, &umr_bitfield_default }, + { "DEQUEUE_REQUEST_INT_ENABLE", 13, 13, &umr_bitfield_default }, + { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default }, + { "SUA_VIOLATION_INT_ENABLE", 15, 15, &umr_bitfield_default }, + { "GPF_INT_ENABLE", 16, 16, &umr_bitfield_default }, + { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default }, + { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default }, + { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default }, + { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default }, + { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default }, + { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default }, + { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default }, + { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ME2_PIPE0_INT_CNTL[] = { + { "CMP_QUERY_STATUS_INT_ENABLE", 12, 12, &umr_bitfield_default }, + { "DEQUEUE_REQUEST_INT_ENABLE", 13, 13, &umr_bitfield_default }, + { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default }, + { "SUA_VIOLATION_INT_ENABLE", 15, 15, &umr_bitfield_default }, + { "GPF_INT_ENABLE", 16, 16, &umr_bitfield_default }, + { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default }, + { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default }, + { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default }, + { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default }, + { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default }, + { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default }, + { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default }, + { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ME2_PIPE1_INT_CNTL[] = { + { "CMP_QUERY_STATUS_INT_ENABLE", 12, 12, &umr_bitfield_default }, + { "DEQUEUE_REQUEST_INT_ENABLE", 13, 13, &umr_bitfield_default }, + { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default }, + { "SUA_VIOLATION_INT_ENABLE", 15, 15, &umr_bitfield_default }, + { "GPF_INT_ENABLE", 16, 16, &umr_bitfield_default }, + { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default }, + { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default }, + { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default }, + { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default }, + { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default }, + { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default }, + { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default }, + { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ME2_PIPE2_INT_CNTL[] = { + { "CMP_QUERY_STATUS_INT_ENABLE", 12, 12, &umr_bitfield_default }, + { "DEQUEUE_REQUEST_INT_ENABLE", 13, 13, &umr_bitfield_default }, + { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default }, + { "SUA_VIOLATION_INT_ENABLE", 15, 15, &umr_bitfield_default }, + { "GPF_INT_ENABLE", 16, 16, &umr_bitfield_default }, + { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default }, + { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default }, + { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default }, + { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default }, + { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default }, + { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default }, + { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default }, + { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ME2_PIPE3_INT_CNTL[] = { + { "CMP_QUERY_STATUS_INT_ENABLE", 12, 12, &umr_bitfield_default }, + { "DEQUEUE_REQUEST_INT_ENABLE", 13, 13, &umr_bitfield_default }, + { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default }, + { "SUA_VIOLATION_INT_ENABLE", 15, 15, &umr_bitfield_default }, + { "GPF_INT_ENABLE", 16, 16, &umr_bitfield_default }, + { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default }, + { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default }, + { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default }, + { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default }, + { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default }, + { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default }, + { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default }, + { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ME1_PIPE0_INT_STATUS[] = { + { "CMP_QUERY_STATUS_INT_STATUS", 12, 12, &umr_bitfield_default }, + { "DEQUEUE_REQUEST_INT_STATUS", 13, 13, &umr_bitfield_default }, + { "CP_ECC_ERROR_INT_STATUS", 14, 14, &umr_bitfield_default }, + { "SUA_VIOLATION_INT_STATUS", 15, 15, &umr_bitfield_default }, + { "GPF_INT_STATUS", 16, 16, &umr_bitfield_default }, + { "WRM_POLL_TIMEOUT_INT_STATUS", 17, 17, &umr_bitfield_default }, + { "PRIV_REG_INT_STATUS", 23, 23, &umr_bitfield_default }, + { "OPCODE_ERROR_INT_STATUS", 24, 24, &umr_bitfield_default }, + { "TIME_STAMP_INT_STATUS", 26, 26, &umr_bitfield_default }, + { "RESERVED_BIT_ERROR_INT_STATUS", 27, 27, &umr_bitfield_default }, + { "GENERIC2_INT_STATUS", 29, 29, &umr_bitfield_default }, + { "GENERIC1_INT_STATUS", 30, 30, &umr_bitfield_default }, + { "GENERIC0_INT_STATUS", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ME1_PIPE1_INT_STATUS[] = { + { "CMP_QUERY_STATUS_INT_STATUS", 12, 12, &umr_bitfield_default }, + { "DEQUEUE_REQUEST_INT_STATUS", 13, 13, &umr_bitfield_default }, + { "CP_ECC_ERROR_INT_STATUS", 14, 14, &umr_bitfield_default }, + { "SUA_VIOLATION_INT_STATUS", 15, 15, &umr_bitfield_default }, + { "GPF_INT_STATUS", 16, 16, &umr_bitfield_default }, + { "WRM_POLL_TIMEOUT_INT_STATUS", 17, 17, &umr_bitfield_default }, + { "PRIV_REG_INT_STATUS", 23, 23, &umr_bitfield_default }, + { "OPCODE_ERROR_INT_STATUS", 24, 24, &umr_bitfield_default }, + { "TIME_STAMP_INT_STATUS", 26, 26, &umr_bitfield_default }, + { "RESERVED_BIT_ERROR_INT_STATUS", 27, 27, &umr_bitfield_default }, + { "GENERIC2_INT_STATUS", 29, 29, &umr_bitfield_default }, + { "GENERIC1_INT_STATUS", 30, 30, &umr_bitfield_default }, + { "GENERIC0_INT_STATUS", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ME1_PIPE2_INT_STATUS[] = { + { "CMP_QUERY_STATUS_INT_STATUS", 12, 12, &umr_bitfield_default }, + { "DEQUEUE_REQUEST_INT_STATUS", 13, 13, &umr_bitfield_default }, + { "CP_ECC_ERROR_INT_STATUS", 14, 14, &umr_bitfield_default }, + { "SUA_VIOLATION_INT_STATUS", 15, 15, &umr_bitfield_default }, + { "GPF_INT_STATUS", 16, 16, &umr_bitfield_default }, + { "WRM_POLL_TIMEOUT_INT_STATUS", 17, 17, &umr_bitfield_default }, + { "PRIV_REG_INT_STATUS", 23, 23, &umr_bitfield_default }, + { "OPCODE_ERROR_INT_STATUS", 24, 24, &umr_bitfield_default }, + { "TIME_STAMP_INT_STATUS", 26, 26, &umr_bitfield_default }, + { "RESERVED_BIT_ERROR_INT_STATUS", 27, 27, &umr_bitfield_default }, + { "GENERIC2_INT_STATUS", 29, 29, &umr_bitfield_default }, + { "GENERIC1_INT_STATUS", 30, 30, &umr_bitfield_default }, + { "GENERIC0_INT_STATUS", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ME1_PIPE3_INT_STATUS[] = { + { "CMP_QUERY_STATUS_INT_STATUS", 12, 12, &umr_bitfield_default }, + { "DEQUEUE_REQUEST_INT_STATUS", 13, 13, &umr_bitfield_default }, + { "CP_ECC_ERROR_INT_STATUS", 14, 14, &umr_bitfield_default }, + { "SUA_VIOLATION_INT_STATUS", 15, 15, &umr_bitfield_default }, + { "GPF_INT_STATUS", 16, 16, &umr_bitfield_default }, + { "WRM_POLL_TIMEOUT_INT_STATUS", 17, 17, &umr_bitfield_default }, + { "PRIV_REG_INT_STATUS", 23, 23, &umr_bitfield_default }, + { "OPCODE_ERROR_INT_STATUS", 24, 24, &umr_bitfield_default }, + { "TIME_STAMP_INT_STATUS", 26, 26, &umr_bitfield_default }, + { "RESERVED_BIT_ERROR_INT_STATUS", 27, 27, &umr_bitfield_default }, + { "GENERIC2_INT_STATUS", 29, 29, &umr_bitfield_default }, + { "GENERIC1_INT_STATUS", 30, 30, &umr_bitfield_default }, + { "GENERIC0_INT_STATUS", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ME2_PIPE0_INT_STATUS[] = { + { "CMP_QUERY_STATUS_INT_STATUS", 12, 12, &umr_bitfield_default }, + { "DEQUEUE_REQUEST_INT_STATUS", 13, 13, &umr_bitfield_default }, + { "CP_ECC_ERROR_INT_STATUS", 14, 14, &umr_bitfield_default }, + { "SUA_VIOLATION_INT_STATUS", 15, 15, &umr_bitfield_default }, + { "GPF_INT_STATUS", 16, 16, &umr_bitfield_default }, + { "WRM_POLL_TIMEOUT_INT_STATUS", 17, 17, &umr_bitfield_default }, + { "PRIV_REG_INT_STATUS", 23, 23, &umr_bitfield_default }, + { "OPCODE_ERROR_INT_STATUS", 24, 24, &umr_bitfield_default }, + { "TIME_STAMP_INT_STATUS", 26, 26, &umr_bitfield_default }, + { "RESERVED_BIT_ERROR_INT_STATUS", 27, 27, &umr_bitfield_default }, + { "GENERIC2_INT_STATUS", 29, 29, &umr_bitfield_default }, + { "GENERIC1_INT_STATUS", 30, 30, &umr_bitfield_default }, + { "GENERIC0_INT_STATUS", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ME2_PIPE1_INT_STATUS[] = { + { "CMP_QUERY_STATUS_INT_STATUS", 12, 12, &umr_bitfield_default }, + { "DEQUEUE_REQUEST_INT_STATUS", 13, 13, &umr_bitfield_default }, + { "CP_ECC_ERROR_INT_STATUS", 14, 14, &umr_bitfield_default }, + { "SUA_VIOLATION_INT_STATUS", 15, 15, &umr_bitfield_default }, + { "GPF_INT_STATUS", 16, 16, &umr_bitfield_default }, + { "WRM_POLL_TIMEOUT_INT_STATUS", 17, 17, &umr_bitfield_default }, + { "PRIV_REG_INT_STATUS", 23, 23, &umr_bitfield_default }, + { "OPCODE_ERROR_INT_STATUS", 24, 24, &umr_bitfield_default }, + { "TIME_STAMP_INT_STATUS", 26, 26, &umr_bitfield_default }, + { "RESERVED_BIT_ERROR_INT_STATUS", 27, 27, &umr_bitfield_default }, + { "GENERIC2_INT_STATUS", 29, 29, &umr_bitfield_default }, + { "GENERIC1_INT_STATUS", 30, 30, &umr_bitfield_default }, + { "GENERIC0_INT_STATUS", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ME2_PIPE2_INT_STATUS[] = { + { "CMP_QUERY_STATUS_INT_STATUS", 12, 12, &umr_bitfield_default }, + { "DEQUEUE_REQUEST_INT_STATUS", 13, 13, &umr_bitfield_default }, + { "CP_ECC_ERROR_INT_STATUS", 14, 14, &umr_bitfield_default }, + { "SUA_VIOLATION_INT_STATUS", 15, 15, &umr_bitfield_default }, + { "GPF_INT_STATUS", 16, 16, &umr_bitfield_default }, + { "WRM_POLL_TIMEOUT_INT_STATUS", 17, 17, &umr_bitfield_default }, + { "PRIV_REG_INT_STATUS", 23, 23, &umr_bitfield_default }, + { "OPCODE_ERROR_INT_STATUS", 24, 24, &umr_bitfield_default }, + { "TIME_STAMP_INT_STATUS", 26, 26, &umr_bitfield_default }, + { "RESERVED_BIT_ERROR_INT_STATUS", 27, 27, &umr_bitfield_default }, + { "GENERIC2_INT_STATUS", 29, 29, &umr_bitfield_default }, + { "GENERIC1_INT_STATUS", 30, 30, &umr_bitfield_default }, + { "GENERIC0_INT_STATUS", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ME2_PIPE3_INT_STATUS[] = { + { "CMP_QUERY_STATUS_INT_STATUS", 12, 12, &umr_bitfield_default }, + { "DEQUEUE_REQUEST_INT_STATUS", 13, 13, &umr_bitfield_default }, + { "CP_ECC_ERROR_INT_STATUS", 14, 14, &umr_bitfield_default }, + { "SUA_VIOLATION_INT_STATUS", 15, 15, &umr_bitfield_default }, + { "GPF_INT_STATUS", 16, 16, &umr_bitfield_default }, + { "WRM_POLL_TIMEOUT_INT_STATUS", 17, 17, &umr_bitfield_default }, + { "PRIV_REG_INT_STATUS", 23, 23, &umr_bitfield_default }, + { "OPCODE_ERROR_INT_STATUS", 24, 24, &umr_bitfield_default }, + { "TIME_STAMP_INT_STATUS", 26, 26, &umr_bitfield_default }, + { "RESERVED_BIT_ERROR_INT_STATUS", 27, 27, &umr_bitfield_default }, + { "GENERIC2_INT_STATUS", 29, 29, &umr_bitfield_default }, + { "GENERIC1_INT_STATUS", 30, 30, &umr_bitfield_default }, + { "GENERIC0_INT_STATUS", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCC_GC_EDC_CONFIG[] = { + { "DIS_EDC", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ME1_PIPE_PRIORITY_CNTS[] = { + { "PRIORITY1_CNT", 0, 7, &umr_bitfield_default }, + { "PRIORITY2A_CNT", 8, 15, &umr_bitfield_default }, + { "PRIORITY2B_CNT", 16, 23, &umr_bitfield_default }, + { "PRIORITY3_CNT", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ME1_PIPE0_PRIORITY[] = { + { "PRIORITY", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ME1_PIPE1_PRIORITY[] = { + { "PRIORITY", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ME1_PIPE2_PRIORITY[] = { + { "PRIORITY", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ME1_PIPE3_PRIORITY[] = { + { "PRIORITY", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ME2_PIPE_PRIORITY_CNTS[] = { + { "PRIORITY1_CNT", 0, 7, &umr_bitfield_default }, + { "PRIORITY2A_CNT", 8, 15, &umr_bitfield_default }, + { "PRIORITY2B_CNT", 16, 23, &umr_bitfield_default }, + { "PRIORITY3_CNT", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ME2_PIPE0_PRIORITY[] = { + { "PRIORITY", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ME2_PIPE1_PRIORITY[] = { + { "PRIORITY", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ME2_PIPE2_PRIORITY[] = { + { "PRIORITY", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ME2_PIPE3_PRIORITY[] = { + { "PRIORITY", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_CE_PRGRM_CNTR_START[] = { + { "IP_START", 0, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_PFP_PRGRM_CNTR_START[] = { + { "IP_START", 0, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ME_PRGRM_CNTR_START[] = { + { "IP_START", 0, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_MEC1_PRGRM_CNTR_START[] = { + { "IP_START", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_MEC2_PRGRM_CNTR_START[] = { + { "IP_START", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_CE_INTR_ROUTINE_START[] = { + { "IR_START", 0, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_PFP_INTR_ROUTINE_START[] = { + { "IR_START", 0, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ME_INTR_ROUTINE_START[] = { + { "IR_START", 0, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_MEC1_INTR_ROUTINE_START[] = { + { "IR_START", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_MEC2_INTR_ROUTINE_START[] = { + { "IR_START", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_CONTEXT_CNTL[] = { + { "ME0PIPE0_MAX_WD_CNTX", 0, 2, &umr_bitfield_default }, + { "ME0PIPE0_MAX_PIPE_CNTX", 4, 6, &umr_bitfield_default }, + { "ME0PIPE1_MAX_WD_CNTX", 16, 18, &umr_bitfield_default }, + { "ME0PIPE1_MAX_PIPE_CNTX", 20, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_MAX_CONTEXT[] = { + { "MAX_CONTEXT", 0, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_IQ_WAIT_TIME1[] = { + { "IB_OFFLOAD", 0, 7, &umr_bitfield_default }, + { "ATOMIC_OFFLOAD", 8, 15, &umr_bitfield_default }, + { "WRM_OFFLOAD", 16, 23, &umr_bitfield_default }, + { "GWS", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_IQ_WAIT_TIME2[] = { + { "QUE_SLEEP", 0, 7, &umr_bitfield_default }, + { "SCH_WAVE", 8, 15, &umr_bitfield_default }, + { "SEM_REARM", 16, 23, &umr_bitfield_default }, + { "DEQ_RETRY", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_RB0_BASE_HI[] = { + { "RB_BASE_HI", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_RB1_BASE_HI[] = { + { "RB_BASE_HI", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_VMID_RESET[] = { + { "RESET_REQUEST", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCPC_INT_CNTL[] = { + { "CMP_QUERY_STATUS_INT_ENABLE", 12, 12, &umr_bitfield_default }, + { "DEQUEUE_REQUEST_INT_ENABLE", 13, 13, &umr_bitfield_default }, + { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default }, + { "SUA_VIOLATION_INT_ENABLE", 15, 15, &umr_bitfield_default }, + { "GPF_INT_ENABLE", 16, 16, &umr_bitfield_default }, + { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default }, + { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default }, + { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default }, + { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default }, + { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default }, + { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default }, + { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default }, + { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCPC_INT_STATUS[] = { + { "CMP_QUERY_STATUS_INT_STATUS", 12, 12, &umr_bitfield_default }, + { "DEQUEUE_REQUEST_INT_STATUS", 13, 13, &umr_bitfield_default }, + { "CP_ECC_ERROR_INT_STATUS", 14, 14, &umr_bitfield_default }, + { "SUA_VIOLATION_INT_STATUS", 15, 15, &umr_bitfield_default }, + { "GPF_INT_STATUS", 16, 16, &umr_bitfield_default }, + { "WRM_POLL_TIMEOUT_INT_STATUS", 17, 17, &umr_bitfield_default }, + { "PRIV_REG_INT_STATUS", 23, 23, &umr_bitfield_default }, + { "OPCODE_ERROR_INT_STATUS", 24, 24, &umr_bitfield_default }, + { "TIME_STAMP_INT_STATUS", 26, 26, &umr_bitfield_default }, + { "RESERVED_BIT_ERROR_INT_STATUS", 27, 27, &umr_bitfield_default }, + { "GENERIC2_INT_STATUS", 29, 29, &umr_bitfield_default }, + { "GENERIC1_INT_STATUS", 30, 30, &umr_bitfield_default }, + { "GENERIC0_INT_STATUS", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_VMID_PREEMPT[] = { + { "PREEMPT_REQUEST", 0, 15, &umr_bitfield_default }, + { "VIRT_COMMAND", 16, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCPC_INT_CNTX_ID[] = { + { "CNTX_ID", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_PQ_STATUS[] = { + { "DOORBELL_UPDATED", 0, 0, &umr_bitfield_default }, + { "DOORBELL_ENABLE", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_CPC_IC_BASE_LO[] = { + { "IC_BASE_LO", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_CPC_IC_BASE_HI[] = { + { "IC_BASE_HI", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_CPC_IC_BASE_CNTL[] = { + { "VMID", 0, 3, &umr_bitfield_default }, + { "CACHE_POLICY", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_CPC_IC_OP_CNTL[] = { + { "INVALIDATE_CACHE", 0, 0, &umr_bitfield_default }, + { "PRIME_ICACHE", 4, 4, &umr_bitfield_default }, + { "ICACHE_PRIMED", 5, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_MEC1_F32_INT_DIS[] = { + { "EDC_ROQ_FED_INT", 0, 0, &umr_bitfield_default }, + { "PRIV_REG_INT", 1, 1, &umr_bitfield_default }, + { "RESERVED_BIT_ERR_INT", 2, 2, &umr_bitfield_default }, + { "EDC_TC_FED_INT", 3, 3, &umr_bitfield_default }, + { "EDC_GDS_FED_INT", 4, 4, &umr_bitfield_default }, + { "EDC_SCRATCH_FED_INT", 5, 5, &umr_bitfield_default }, + { "WAVE_RESTORE_INT", 6, 6, &umr_bitfield_default }, + { "SUA_VIOLATION_INT", 7, 7, &umr_bitfield_default }, + { "EDC_DMA_FED_INT", 8, 8, &umr_bitfield_default }, + { "IQ_TIMER_INT", 9, 9, &umr_bitfield_default }, + { "GPF_INT_CPF", 10, 10, &umr_bitfield_default }, + { "GPF_INT_DMA", 11, 11, &umr_bitfield_default }, + { "GPF_INT_CPC", 12, 12, &umr_bitfield_default }, + { "EDC_SR_MEM_FED_INT", 13, 13, &umr_bitfield_default }, + { "QUEUE_MESSAGE_INT", 14, 14, &umr_bitfield_default }, + { "FATAL_EDC_ERROR_INT", 15, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_MEC2_F32_INT_DIS[] = { + { "EDC_ROQ_FED_INT", 0, 0, &umr_bitfield_default }, + { "PRIV_REG_INT", 1, 1, &umr_bitfield_default }, + { "RESERVED_BIT_ERR_INT", 2, 2, &umr_bitfield_default }, + { "EDC_TC_FED_INT", 3, 3, &umr_bitfield_default }, + { "EDC_GDS_FED_INT", 4, 4, &umr_bitfield_default }, + { "EDC_SCRATCH_FED_INT", 5, 5, &umr_bitfield_default }, + { "WAVE_RESTORE_INT", 6, 6, &umr_bitfield_default }, + { "SUA_VIOLATION_INT", 7, 7, &umr_bitfield_default }, + { "EDC_DMA_FED_INT", 8, 8, &umr_bitfield_default }, + { "IQ_TIMER_INT", 9, 9, &umr_bitfield_default }, + { "GPF_INT_CPF", 10, 10, &umr_bitfield_default }, + { "GPF_INT_DMA", 11, 11, &umr_bitfield_default }, + { "GPF_INT_CPC", 12, 12, &umr_bitfield_default }, + { "EDC_SR_MEM_FED_INT", 13, 13, &umr_bitfield_default }, + { "QUEUE_MESSAGE_INT", 14, 14, &umr_bitfield_default }, + { "FATAL_EDC_ERROR_INT", 15, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_VMID_STATUS[] = { + { "PREEMPT_DE_STATUS", 0, 15, &umr_bitfield_default }, + { "PREEMPT_CE_STATUS", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_RB_DOORBELL_CONTROL_SCH_0[] = { + { "DOORBELL_OFFSET", 2, 27, &umr_bitfield_default }, + { "DOORBELL_EN", 30, 30, &umr_bitfield_default }, + { "DOORBELL_HIT", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_RB_DOORBELL_CONTROL_SCH_1[] = { + { "DOORBELL_OFFSET", 2, 27, &umr_bitfield_default }, + { "DOORBELL_EN", 30, 30, &umr_bitfield_default }, + { "DOORBELL_HIT", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_RB_DOORBELL_CONTROL_SCH_2[] = { + { "DOORBELL_OFFSET", 2, 27, &umr_bitfield_default }, + { "DOORBELL_EN", 30, 30, &umr_bitfield_default }, + { "DOORBELL_HIT", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_RB_DOORBELL_CONTROL_SCH_3[] = { + { "DOORBELL_OFFSET", 2, 27, &umr_bitfield_default }, + { "DOORBELL_EN", 30, 30, &umr_bitfield_default }, + { "DOORBELL_HIT", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_RB_DOORBELL_CONTROL_SCH_4[] = { + { "DOORBELL_OFFSET", 2, 27, &umr_bitfield_default }, + { "DOORBELL_EN", 30, 30, &umr_bitfield_default }, + { "DOORBELL_HIT", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_RB_DOORBELL_CONTROL_SCH_5[] = { + { "DOORBELL_OFFSET", 2, 27, &umr_bitfield_default }, + { "DOORBELL_EN", 30, 30, &umr_bitfield_default }, + { "DOORBELL_HIT", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_RB_DOORBELL_CONTROL_SCH_6[] = { + { "DOORBELL_OFFSET", 2, 27, &umr_bitfield_default }, + { "DOORBELL_EN", 30, 30, &umr_bitfield_default }, + { "DOORBELL_HIT", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_RB_DOORBELL_CONTROL_SCH_7[] = { + { "DOORBELL_OFFSET", 2, 27, &umr_bitfield_default }, + { "DOORBELL_EN", 30, 30, &umr_bitfield_default }, + { "DOORBELL_HIT", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_RB_DOORBELL_CLEAR[] = { + { "MAPPED_QUEUE", 0, 2, &umr_bitfield_default }, + { "MAPPED_QUE_DOORBELL_EN_CLEAR", 8, 8, &umr_bitfield_default }, + { "MAPPED_QUE_DOORBELL_HIT_CLEAR", 9, 9, &umr_bitfield_default }, + { "MASTER_DOORBELL_EN_CLEAR", 10, 10, &umr_bitfield_default }, + { "MASTER_DOORBELL_HIT_CLEAR", 11, 11, &umr_bitfield_default }, + { "QUEUES_DOORBELL_EN_CLEAR", 12, 12, &umr_bitfield_default }, + { "QUEUES_DOORBELL_HIT_CLEAR", 13, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_GFX_MQD_CONTROL[] = { + { "VMID", 0, 3, &umr_bitfield_default }, + { "EXE_DISABLE", 23, 23, &umr_bitfield_default }, + { "CACHE_POLICY", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_GFX_MQD_BASE_ADDR[] = { + { "BASE_ADDR", 2, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_GFX_MQD_BASE_ADDR_HI[] = { + { "BASE_ADDR_HI", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_RB_STATUS[] = { + { "DOORBELL_UPDATED", 0, 0, &umr_bitfield_default }, + { "DOORBELL_ENABLE", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCPG_UTCL1_STATUS[] = { + { "FAULT_DETECTED", 0, 0, &umr_bitfield_default }, + { "RETRY_DETECTED", 1, 1, &umr_bitfield_default }, + { "PRT_DETECTED", 2, 2, &umr_bitfield_default }, + { "FAULT_UTCL1ID", 8, 13, &umr_bitfield_default }, + { "RETRY_UTCL1ID", 16, 21, &umr_bitfield_default }, + { "PRT_UTCL1ID", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCPC_UTCL1_STATUS[] = { + { "FAULT_DETECTED", 0, 0, &umr_bitfield_default }, + { "RETRY_DETECTED", 1, 1, &umr_bitfield_default }, + { "PRT_DETECTED", 2, 2, &umr_bitfield_default }, + { "FAULT_UTCL1ID", 8, 13, &umr_bitfield_default }, + { "RETRY_UTCL1ID", 16, 21, &umr_bitfield_default }, + { "PRT_UTCL1ID", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCPF_UTCL1_STATUS[] = { + { "FAULT_DETECTED", 0, 0, &umr_bitfield_default }, + { "RETRY_DETECTED", 1, 1, &umr_bitfield_default }, + { "PRT_DETECTED", 2, 2, &umr_bitfield_default }, + { "FAULT_UTCL1ID", 8, 13, &umr_bitfield_default }, + { "RETRY_UTCL1ID", 16, 21, &umr_bitfield_default }, + { "PRT_UTCL1ID", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_SD_CNTL[] = { + { "CPF_EN", 0, 0, &umr_bitfield_default }, + { "CPG_EN", 1, 1, &umr_bitfield_default }, + { "CPC_EN", 2, 2, &umr_bitfield_default }, + { "RLC_EN", 3, 3, &umr_bitfield_default }, + { "SPI_EN", 4, 4, &umr_bitfield_default }, + { "WD_EN", 5, 5, &umr_bitfield_default }, + { "IA_EN", 6, 6, &umr_bitfield_default }, + { "PA_EN", 7, 7, &umr_bitfield_default }, + { "RMI_EN", 8, 8, &umr_bitfield_default }, + { "EA_EN", 9, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_SOFT_RESET_CNTL[] = { + { "CMP_ONLY_SOFT_RESET", 0, 0, &umr_bitfield_default }, + { "GFX_ONLY_SOFT_RESET", 1, 1, &umr_bitfield_default }, + { "CMP_HQD_REG_RESET", 2, 2, &umr_bitfield_default }, + { "CMP_INTR_REG_RESET", 3, 3, &umr_bitfield_default }, + { "CMP_HQD_QUEUE_DOORBELL_RESET", 4, 4, &umr_bitfield_default }, + { "GFX_RB_DOORBELL_RESET", 5, 5, &umr_bitfield_default }, + { "GFX_INTR_REG_RESET", 6, 6, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_CPC_GFX_CNTL[] = { + { "QUEUEID", 0, 2, &umr_bitfield_default }, + { "PIPEID", 3, 4, &umr_bitfield_default }, + { "MEID", 5, 6, &umr_bitfield_default }, + { "VALID", 7, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_ARB_PRIORITY[] = { + { "PIPE_ORDER_TS0", 0, 2, &umr_bitfield_default }, + { "PIPE_ORDER_TS1", 3, 5, &umr_bitfield_default }, + { "PIPE_ORDER_TS2", 6, 8, &umr_bitfield_default }, + { "PIPE_ORDER_TS3", 9, 11, &umr_bitfield_default }, + { "TS0_DUR_MULT", 12, 13, &umr_bitfield_default }, + { "TS1_DUR_MULT", 14, 15, &umr_bitfield_default }, + { "TS2_DUR_MULT", 16, 17, &umr_bitfield_default }, + { "TS3_DUR_MULT", 18, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_ARB_CYCLES_0[] = { + { "TS0_DURATION", 0, 15, &umr_bitfield_default }, + { "TS1_DURATION", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_ARB_CYCLES_1[] = { + { "TS2_DURATION", 0, 15, &umr_bitfield_default }, + { "TS3_DURATION", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_WCL_PIPE_PERCENT_GFX[] = { + { "VALUE", 0, 6, &umr_bitfield_default }, + { "LS_GRP_VALUE", 7, 11, &umr_bitfield_default }, + { "HS_GRP_VALUE", 12, 16, &umr_bitfield_default }, + { "ES_GRP_VALUE", 17, 21, &umr_bitfield_default }, + { "GS_GRP_VALUE", 22, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_WCL_PIPE_PERCENT_HP3D[] = { + { "VALUE", 0, 6, &umr_bitfield_default }, + { "HS_GRP_VALUE", 12, 16, &umr_bitfield_default }, + { "GS_GRP_VALUE", 22, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_WCL_PIPE_PERCENT_CS0[] = { + { "VALUE", 0, 6, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_WCL_PIPE_PERCENT_CS1[] = { + { "VALUE", 0, 6, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_WCL_PIPE_PERCENT_CS2[] = { + { "VALUE", 0, 6, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_WCL_PIPE_PERCENT_CS3[] = { + { "VALUE", 0, 6, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_WCL_PIPE_PERCENT_CS4[] = { + { "VALUE", 0, 6, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_WCL_PIPE_PERCENT_CS5[] = { + { "VALUE", 0, 6, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_WCL_PIPE_PERCENT_CS6[] = { + { "VALUE", 0, 6, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_WCL_PIPE_PERCENT_CS7[] = { + { "VALUE", 0, 6, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_COMPUTE_QUEUE_RESET[] = { + { "RESET", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_RESOURCE_RESERVE_CU_0[] = { + { "VGPR", 0, 3, &umr_bitfield_default }, + { "SGPR", 4, 7, &umr_bitfield_default }, + { "LDS", 8, 11, &umr_bitfield_default }, + { "WAVES", 12, 14, &umr_bitfield_default }, + { "BARRIERS", 15, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_RESOURCE_RESERVE_CU_1[] = { + { "VGPR", 0, 3, &umr_bitfield_default }, + { "SGPR", 4, 7, &umr_bitfield_default }, + { "LDS", 8, 11, &umr_bitfield_default }, + { "WAVES", 12, 14, &umr_bitfield_default }, + { "BARRIERS", 15, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_RESOURCE_RESERVE_CU_2[] = { + { "VGPR", 0, 3, &umr_bitfield_default }, + { "SGPR", 4, 7, &umr_bitfield_default }, + { "LDS", 8, 11, &umr_bitfield_default }, + { "WAVES", 12, 14, &umr_bitfield_default }, + { "BARRIERS", 15, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_RESOURCE_RESERVE_CU_3[] = { + { "VGPR", 0, 3, &umr_bitfield_default }, + { "SGPR", 4, 7, &umr_bitfield_default }, + { "LDS", 8, 11, &umr_bitfield_default }, + { "WAVES", 12, 14, &umr_bitfield_default }, + { "BARRIERS", 15, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_RESOURCE_RESERVE_CU_4[] = { + { "VGPR", 0, 3, &umr_bitfield_default }, + { "SGPR", 4, 7, &umr_bitfield_default }, + { "LDS", 8, 11, &umr_bitfield_default }, + { "WAVES", 12, 14, &umr_bitfield_default }, + { "BARRIERS", 15, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_RESOURCE_RESERVE_CU_5[] = { + { "VGPR", 0, 3, &umr_bitfield_default }, + { "SGPR", 4, 7, &umr_bitfield_default }, + { "LDS", 8, 11, &umr_bitfield_default }, + { "WAVES", 12, 14, &umr_bitfield_default }, + { "BARRIERS", 15, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_RESOURCE_RESERVE_CU_6[] = { + { "VGPR", 0, 3, &umr_bitfield_default }, + { "SGPR", 4, 7, &umr_bitfield_default }, + { "LDS", 8, 11, &umr_bitfield_default }, + { "WAVES", 12, 14, &umr_bitfield_default }, + { "BARRIERS", 15, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_RESOURCE_RESERVE_CU_7[] = { + { "VGPR", 0, 3, &umr_bitfield_default }, + { "SGPR", 4, 7, &umr_bitfield_default }, + { "LDS", 8, 11, &umr_bitfield_default }, + { "WAVES", 12, 14, &umr_bitfield_default }, + { "BARRIERS", 15, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_RESOURCE_RESERVE_CU_8[] = { + { "VGPR", 0, 3, &umr_bitfield_default }, + { "SGPR", 4, 7, &umr_bitfield_default }, + { "LDS", 8, 11, &umr_bitfield_default }, + { "WAVES", 12, 14, &umr_bitfield_default }, + { "BARRIERS", 15, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_RESOURCE_RESERVE_CU_9[] = { + { "VGPR", 0, 3, &umr_bitfield_default }, + { "SGPR", 4, 7, &umr_bitfield_default }, + { "LDS", 8, 11, &umr_bitfield_default }, + { "WAVES", 12, 14, &umr_bitfield_default }, + { "BARRIERS", 15, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_RESOURCE_RESERVE_EN_CU_0[] = { + { "EN", 0, 0, &umr_bitfield_default }, + { "TYPE_MASK", 1, 15, &umr_bitfield_default }, + { "QUEUE_MASK", 16, 23, &umr_bitfield_default }, + { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_RESOURCE_RESERVE_EN_CU_1[] = { + { "EN", 0, 0, &umr_bitfield_default }, + { "TYPE_MASK", 1, 15, &umr_bitfield_default }, + { "QUEUE_MASK", 16, 23, &umr_bitfield_default }, + { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_RESOURCE_RESERVE_EN_CU_2[] = { + { "EN", 0, 0, &umr_bitfield_default }, + { "TYPE_MASK", 1, 15, &umr_bitfield_default }, + { "QUEUE_MASK", 16, 23, &umr_bitfield_default }, + { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_RESOURCE_RESERVE_EN_CU_3[] = { + { "EN", 0, 0, &umr_bitfield_default }, + { "TYPE_MASK", 1, 15, &umr_bitfield_default }, + { "QUEUE_MASK", 16, 23, &umr_bitfield_default }, + { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_RESOURCE_RESERVE_EN_CU_4[] = { + { "EN", 0, 0, &umr_bitfield_default }, + { "TYPE_MASK", 1, 15, &umr_bitfield_default }, + { "QUEUE_MASK", 16, 23, &umr_bitfield_default }, + { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_RESOURCE_RESERVE_EN_CU_5[] = { + { "EN", 0, 0, &umr_bitfield_default }, + { "TYPE_MASK", 1, 15, &umr_bitfield_default }, + { "QUEUE_MASK", 16, 23, &umr_bitfield_default }, + { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_RESOURCE_RESERVE_EN_CU_6[] = { + { "EN", 0, 0, &umr_bitfield_default }, + { "TYPE_MASK", 1, 15, &umr_bitfield_default }, + { "QUEUE_MASK", 16, 23, &umr_bitfield_default }, + { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_RESOURCE_RESERVE_EN_CU_7[] = { + { "EN", 0, 0, &umr_bitfield_default }, + { "TYPE_MASK", 1, 15, &umr_bitfield_default }, + { "QUEUE_MASK", 16, 23, &umr_bitfield_default }, + { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_RESOURCE_RESERVE_EN_CU_8[] = { + { "EN", 0, 0, &umr_bitfield_default }, + { "TYPE_MASK", 1, 15, &umr_bitfield_default }, + { "QUEUE_MASK", 16, 23, &umr_bitfield_default }, + { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_RESOURCE_RESERVE_EN_CU_9[] = { + { "EN", 0, 0, &umr_bitfield_default }, + { "TYPE_MASK", 1, 15, &umr_bitfield_default }, + { "QUEUE_MASK", 16, 23, &umr_bitfield_default }, + { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_RESOURCE_RESERVE_CU_10[] = { + { "VGPR", 0, 3, &umr_bitfield_default }, + { "SGPR", 4, 7, &umr_bitfield_default }, + { "LDS", 8, 11, &umr_bitfield_default }, + { "WAVES", 12, 14, &umr_bitfield_default }, + { "BARRIERS", 15, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_RESOURCE_RESERVE_CU_11[] = { + { "VGPR", 0, 3, &umr_bitfield_default }, + { "SGPR", 4, 7, &umr_bitfield_default }, + { "LDS", 8, 11, &umr_bitfield_default }, + { "WAVES", 12, 14, &umr_bitfield_default }, + { "BARRIERS", 15, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_RESOURCE_RESERVE_EN_CU_10[] = { + { "EN", 0, 0, &umr_bitfield_default }, + { "TYPE_MASK", 1, 15, &umr_bitfield_default }, + { "QUEUE_MASK", 16, 23, &umr_bitfield_default }, + { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_RESOURCE_RESERVE_EN_CU_11[] = { + { "EN", 0, 0, &umr_bitfield_default }, + { "TYPE_MASK", 1, 15, &umr_bitfield_default }, + { "QUEUE_MASK", 16, 23, &umr_bitfield_default }, + { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_RESOURCE_RESERVE_CU_12[] = { + { "VGPR", 0, 3, &umr_bitfield_default }, + { "SGPR", 4, 7, &umr_bitfield_default }, + { "LDS", 8, 11, &umr_bitfield_default }, + { "WAVES", 12, 14, &umr_bitfield_default }, + { "BARRIERS", 15, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_RESOURCE_RESERVE_CU_13[] = { + { "VGPR", 0, 3, &umr_bitfield_default }, + { "SGPR", 4, 7, &umr_bitfield_default }, + { "LDS", 8, 11, &umr_bitfield_default }, + { "WAVES", 12, 14, &umr_bitfield_default }, + { "BARRIERS", 15, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_RESOURCE_RESERVE_CU_14[] = { + { "VGPR", 0, 3, &umr_bitfield_default }, + { "SGPR", 4, 7, &umr_bitfield_default }, + { "LDS", 8, 11, &umr_bitfield_default }, + { "WAVES", 12, 14, &umr_bitfield_default }, + { "BARRIERS", 15, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_RESOURCE_RESERVE_CU_15[] = { + { "VGPR", 0, 3, &umr_bitfield_default }, + { "SGPR", 4, 7, &umr_bitfield_default }, + { "LDS", 8, 11, &umr_bitfield_default }, + { "WAVES", 12, 14, &umr_bitfield_default }, + { "BARRIERS", 15, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_RESOURCE_RESERVE_EN_CU_12[] = { + { "EN", 0, 0, &umr_bitfield_default }, + { "TYPE_MASK", 1, 15, &umr_bitfield_default }, + { "QUEUE_MASK", 16, 23, &umr_bitfield_default }, + { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_RESOURCE_RESERVE_EN_CU_13[] = { + { "EN", 0, 0, &umr_bitfield_default }, + { "TYPE_MASK", 1, 15, &umr_bitfield_default }, + { "QUEUE_MASK", 16, 23, &umr_bitfield_default }, + { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_RESOURCE_RESERVE_EN_CU_14[] = { + { "EN", 0, 0, &umr_bitfield_default }, + { "TYPE_MASK", 1, 15, &umr_bitfield_default }, + { "QUEUE_MASK", 16, 23, &umr_bitfield_default }, + { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_RESOURCE_RESERVE_EN_CU_15[] = { + { "EN", 0, 0, &umr_bitfield_default }, + { "TYPE_MASK", 1, 15, &umr_bitfield_default }, + { "QUEUE_MASK", 16, 23, &umr_bitfield_default }, + { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_COMPUTE_WF_CTX_SAVE[] = { + { "INITIATE", 0, 0, &umr_bitfield_default }, + { "GDS_INTERRUPT_EN", 1, 1, &umr_bitfield_default }, + { "DONE_INTERRUPT_EN", 2, 2, &umr_bitfield_default }, + { "GDS_REQ_BUSY", 30, 30, &umr_bitfield_default }, + { "SAVE_BUSY", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_ARB_CNTL_0[] = { + { "EXP_ARB_COL_WT", 0, 3, &umr_bitfield_default }, + { "EXP_ARB_POS_WT", 4, 7, &umr_bitfield_default }, + { "EXP_ARB_GDS_WT", 8, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HQD_GFX_CONTROL[] = { + { "MESSAGE", 0, 3, &umr_bitfield_default }, + { "MISC", 4, 14, &umr_bitfield_default }, + { "DB_UPDATED_MSG_EN", 15, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HQD_GFX_STATUS[] = { + { "STATUS", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HPD_ROQ_OFFSETS[] = { + { "IQ_OFFSET", 0, 2, &umr_bitfield_default }, + { "PQ_OFFSET", 8, 13, &umr_bitfield_default }, + { "IB_OFFSET", 16, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HPD_STATUS0[] = { + { "QUEUE_STATE", 0, 4, &umr_bitfield_default }, + { "MAPPED_QUEUE", 5, 7, &umr_bitfield_default }, + { "QUEUE_AVAILABLE", 8, 15, &umr_bitfield_default }, + { "FETCHING_MQD", 16, 16, &umr_bitfield_default }, + { "PEND_TXFER_SIZE_PQIB", 17, 17, &umr_bitfield_default }, + { "PEND_TXFER_SIZE_IQ", 18, 18, &umr_bitfield_default }, + { "FORCE_QUEUE_STATE", 20, 24, &umr_bitfield_default }, + { "FORCE_QUEUE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HPD_UTCL1_CNTL[] = { + { "SELECT", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HPD_UTCL1_ERROR[] = { + { "ADDR_HI", 0, 15, &umr_bitfield_default }, + { "TYPE", 16, 16, &umr_bitfield_default }, + { "VMID", 20, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HPD_UTCL1_ERROR_ADDR[] = { + { "ADDR", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_MQD_BASE_ADDR[] = { + { "BASE_ADDR", 2, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_MQD_BASE_ADDR_HI[] = { + { "BASE_ADDR_HI", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HQD_ACTIVE[] = { + { "ACTIVE", 0, 0, &umr_bitfield_default }, + { "BUSY_GATE", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HQD_VMID[] = { + { "VMID", 0, 3, &umr_bitfield_default }, + { "IB_VMID", 8, 11, &umr_bitfield_default }, + { "VQID", 16, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HQD_PERSISTENT_STATE[] = { + { "PRELOAD_REQ", 0, 0, &umr_bitfield_default }, + { "PRELOAD_SIZE", 8, 17, &umr_bitfield_default }, + { "WPP_SWITCH_QOS_EN", 21, 21, &umr_bitfield_default }, + { "IQ_SWITCH_QOS_EN", 22, 22, &umr_bitfield_default }, + { "IB_SWITCH_QOS_EN", 23, 23, &umr_bitfield_default }, + { "EOP_SWITCH_QOS_EN", 24, 24, &umr_bitfield_default }, + { "PQ_SWITCH_QOS_EN", 25, 25, &umr_bitfield_default }, + { "TC_OFFLOAD_QOS_EN", 26, 26, &umr_bitfield_default }, + { "CACHE_FULL_PACKET_EN", 27, 27, &umr_bitfield_default }, + { "RESTORE_ACTIVE", 28, 28, &umr_bitfield_default }, + { "RELAUNCH_WAVES", 29, 29, &umr_bitfield_default }, + { "QSWITCH_MODE", 30, 30, &umr_bitfield_default }, + { "DISP_ACTIVE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HQD_PIPE_PRIORITY[] = { + { "PIPE_PRIORITY", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HQD_QUEUE_PRIORITY[] = { + { "PRIORITY_LEVEL", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HQD_QUANTUM[] = { + { "QUANTUM_EN", 0, 0, &umr_bitfield_default }, + { "QUANTUM_SCALE", 4, 4, &umr_bitfield_default }, + { "QUANTUM_DURATION", 8, 13, &umr_bitfield_default }, + { "QUANTUM_ACTIVE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HQD_PQ_BASE[] = { + { "ADDR", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HQD_PQ_BASE_HI[] = { + { "ADDR_HI", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HQD_PQ_RPTR[] = { + { "CONSUMED_OFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HQD_PQ_RPTR_REPORT_ADDR[] = { + { "RPTR_REPORT_ADDR", 2, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI[] = { + { "RPTR_REPORT_ADDR_HI", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HQD_PQ_WPTR_POLL_ADDR[] = { + { "WPTR_ADDR", 3, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HQD_PQ_WPTR_POLL_ADDR_HI[] = { + { "WPTR_ADDR_HI", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HQD_PQ_DOORBELL_CONTROL[] = { + { "DOORBELL_MODE", 0, 0, &umr_bitfield_default }, + { "DOORBELL_BIF_DROP", 1, 1, &umr_bitfield_default }, + { "DOORBELL_OFFSET", 2, 27, &umr_bitfield_default }, + { "DOORBELL_SOURCE", 28, 28, &umr_bitfield_default }, + { "DOORBELL_SCHD_HIT", 29, 29, &umr_bitfield_default }, + { "DOORBELL_EN", 30, 30, &umr_bitfield_default }, + { "DOORBELL_HIT", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HQD_PQ_CONTROL[] = { + { "QUEUE_SIZE", 0, 5, &umr_bitfield_default }, + { "WPTR_CARRY", 6, 6, &umr_bitfield_default }, + { "RPTR_CARRY", 7, 7, &umr_bitfield_default }, + { "RPTR_BLOCK_SIZE", 8, 13, &umr_bitfield_default }, + { "QUEUE_FULL_EN", 14, 14, &umr_bitfield_default }, + { "PQ_EMPTY", 15, 15, &umr_bitfield_default }, + { "WPP_CLAMP_EN", 16, 16, &umr_bitfield_default }, + { "ENDIAN_SWAP", 17, 18, &umr_bitfield_default }, + { "MIN_AVAIL_SIZE", 20, 21, &umr_bitfield_default }, + { "EXE_DISABLE", 23, 23, &umr_bitfield_default }, + { "CACHE_POLICY", 24, 24, &umr_bitfield_default }, + { "SLOT_BASED_WPTR", 25, 26, &umr_bitfield_default }, + { "NO_UPDATE_RPTR", 27, 27, &umr_bitfield_default }, + { "UNORD_DISPATCH", 28, 28, &umr_bitfield_default }, + { "ROQ_PQ_IB_FLIP", 29, 29, &umr_bitfield_default }, + { "PRIV_STATE", 30, 30, &umr_bitfield_default }, + { "KMD_QUEUE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HQD_IB_BASE_ADDR[] = { + { "IB_BASE_ADDR", 2, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HQD_IB_BASE_ADDR_HI[] = { + { "IB_BASE_ADDR_HI", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HQD_IB_RPTR[] = { + { "CONSUMED_OFFSET", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HQD_IB_CONTROL[] = { + { "IB_SIZE", 0, 19, &umr_bitfield_default }, + { "MIN_IB_AVAIL_SIZE", 20, 21, &umr_bitfield_default }, + { "IB_EXE_DISABLE", 23, 23, &umr_bitfield_default }, + { "IB_CACHE_POLICY", 24, 24, &umr_bitfield_default }, + { "PROCESSING_IB", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HQD_IQ_TIMER[] = { + { "WAIT_TIME", 0, 7, &umr_bitfield_default }, + { "RETRY_TYPE", 8, 10, &umr_bitfield_default }, + { "IMMEDIATE_EXPIRE", 11, 11, &umr_bitfield_default }, + { "INTERRUPT_TYPE", 12, 13, &umr_bitfield_default }, + { "CLOCK_COUNT", 14, 15, &umr_bitfield_default }, + { "INTERRUPT_SIZE", 16, 21, &umr_bitfield_default }, + { "QUANTUM_TIMER", 22, 22, &umr_bitfield_default }, + { "EXE_DISABLE", 23, 23, &umr_bitfield_default }, + { "CACHE_POLICY", 24, 24, &umr_bitfield_default }, + { "QUEUE_TYPE", 25, 25, &umr_bitfield_default }, + { "REARM_TIMER", 28, 28, &umr_bitfield_default }, + { "PROCESS_IQ_EN", 29, 29, &umr_bitfield_default }, + { "PROCESSING_IQ", 30, 30, &umr_bitfield_default }, + { "ACTIVE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HQD_IQ_RPTR[] = { + { "OFFSET", 0, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HQD_DEQUEUE_REQUEST[] = { + { "DEQUEUE_REQ", 0, 2, &umr_bitfield_default }, + { "IQ_REQ_PEND", 4, 4, &umr_bitfield_default }, + { "DEQUEUE_INT", 8, 8, &umr_bitfield_default }, + { "IQ_REQ_PEND_EN", 9, 9, &umr_bitfield_default }, + { "DEQUEUE_REQ_EN", 10, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HQD_DMA_OFFLOAD[] = { + { "DMA_OFFLOAD", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HQD_OFFLOAD[] = { + { "DMA_OFFLOAD", 0, 0, &umr_bitfield_default }, + { "DMA_OFFLOAD_EN", 1, 1, &umr_bitfield_default }, + { "AQL_OFFLOAD", 2, 2, &umr_bitfield_default }, + { "AQL_OFFLOAD_EN", 3, 3, &umr_bitfield_default }, + { "EOP_OFFLOAD", 4, 4, &umr_bitfield_default }, + { "EOP_OFFLOAD_EN", 5, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HQD_SEMA_CMD[] = { + { "RETRY", 0, 0, &umr_bitfield_default }, + { "RESULT", 1, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HQD_MSG_TYPE[] = { + { "ACTION", 0, 2, &umr_bitfield_default }, + { "SAVE_STATE", 4, 6, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HQD_ATOMIC0_PREOP_LO[] = { + { "ATOMIC0_PREOP_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HQD_ATOMIC0_PREOP_HI[] = { + { "ATOMIC0_PREOP_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HQD_ATOMIC1_PREOP_LO[] = { + { "ATOMIC1_PREOP_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HQD_ATOMIC1_PREOP_HI[] = { + { "ATOMIC1_PREOP_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HQD_HQ_SCHEDULER0[] = { + { "SCHEDULER", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HQD_HQ_STATUS0[] = { + { "DEQUEUE_STATUS", 0, 1, &umr_bitfield_default }, + { "DEQUEUE_RETRY_CNT", 2, 3, &umr_bitfield_default }, + { "RSV_6_4", 4, 6, &umr_bitfield_default }, + { "SCRATCH_RAM_INIT", 7, 7, &umr_bitfield_default }, + { "TCL2_DIRTY", 8, 8, &umr_bitfield_default }, + { "PG_ACTIVATED", 9, 9, &umr_bitfield_default }, + { "RSVR_29_10", 10, 29, &umr_bitfield_default }, + { "QUEUE_IDLE", 30, 30, &umr_bitfield_default }, + { "DB_UPDATED_MSG_EN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HQD_HQ_CONTROL0[] = { + { "CONTROL", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HQD_HQ_SCHEDULER1[] = { + { "SCHEDULER", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_MQD_CONTROL[] = { + { "VMID", 0, 3, &umr_bitfield_default }, + { "PRIV_STATE", 8, 8, &umr_bitfield_default }, + { "PROCESSING_MQD", 12, 12, &umr_bitfield_default }, + { "PROCESSING_MQD_EN", 13, 13, &umr_bitfield_default }, + { "EXE_DISABLE", 23, 23, &umr_bitfield_default }, + { "CACHE_POLICY", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HQD_HQ_STATUS1[] = { + { "STATUS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HQD_HQ_CONTROL1[] = { + { "CONTROL", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HQD_EOP_BASE_ADDR[] = { + { "BASE_ADDR", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HQD_EOP_BASE_ADDR_HI[] = { + { "BASE_ADDR_HI", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HQD_EOP_CONTROL[] = { + { "EOP_SIZE", 0, 5, &umr_bitfield_default }, + { "PROCESSING_EOP", 8, 8, &umr_bitfield_default }, + { "PROCESS_EOP_EN", 12, 12, &umr_bitfield_default }, + { "PROCESSING_EOPIB", 13, 13, &umr_bitfield_default }, + { "PROCESS_EOPIB_EN", 14, 14, &umr_bitfield_default }, + { "HALT_FETCHER", 21, 21, &umr_bitfield_default }, + { "HALT_FETCHER_EN", 22, 22, &umr_bitfield_default }, + { "EXE_DISABLE", 23, 23, &umr_bitfield_default }, + { "CACHE_POLICY", 24, 24, &umr_bitfield_default }, + { "SIG_SEM_RESULT", 29, 30, &umr_bitfield_default }, + { "PEND_SIG_SEM", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HQD_EOP_RPTR[] = { + { "RPTR", 0, 12, &umr_bitfield_default }, + { "RESET_FETCHER", 28, 28, &umr_bitfield_default }, + { "DEQUEUE_PEND", 29, 29, &umr_bitfield_default }, + { "RPTR_EQ_CSMD_WPTR", 30, 30, &umr_bitfield_default }, + { "INIT_FETCHER", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HQD_EOP_WPTR[] = { + { "WPTR", 0, 12, &umr_bitfield_default }, + { "EOP_EMPTY", 15, 15, &umr_bitfield_default }, + { "EOP_AVAIL", 16, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HQD_EOP_EVENTS[] = { + { "EVENT_COUNT", 0, 11, &umr_bitfield_default }, + { "CS_PARTIAL_FLUSH_PEND", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HQD_CTX_SAVE_BASE_ADDR_LO[] = { + { "ADDR", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HQD_CTX_SAVE_BASE_ADDR_HI[] = { + { "ADDR_HI", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HQD_CTX_SAVE_CONTROL[] = { + { "POLICY", 3, 3, &umr_bitfield_default }, + { "EXE_DISABLE", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HQD_CNTL_STACK_OFFSET[] = { + { "OFFSET", 2, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HQD_CNTL_STACK_SIZE[] = { + { "SIZE", 12, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HQD_WG_STATE_OFFSET[] = { + { "OFFSET", 2, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HQD_CTX_SAVE_SIZE[] = { + { "SIZE", 12, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HQD_GDS_RESOURCE_STATE[] = { + { "OA_REQUIRED", 0, 0, &umr_bitfield_default }, + { "OA_ACQUIRED", 1, 1, &umr_bitfield_default }, + { "GWS_SIZE", 4, 9, &umr_bitfield_default }, + { "GWS_PNTR", 12, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HQD_ERROR[] = { + { "EDC_ERROR_ID", 0, 3, &umr_bitfield_default }, + { "SUA_ERROR", 4, 4, &umr_bitfield_default }, + { "AQL_ERROR", 5, 5, &umr_bitfield_default }, + { "PQ_UTCL1_ERROR", 8, 8, &umr_bitfield_default }, + { "IB_UTCL1_ERROR", 9, 9, &umr_bitfield_default }, + { "EOP_UTCL1_ERROR", 10, 10, &umr_bitfield_default }, + { "IQ_UTCL1_ERROR", 11, 11, &umr_bitfield_default }, + { "RRPT_UTCL1_ERROR", 12, 12, &umr_bitfield_default }, + { "WPP_UTCL1_ERROR", 13, 13, &umr_bitfield_default }, + { "SEM_UTCL1_ERROR", 14, 14, &umr_bitfield_default }, + { "DMA_SRC_UTCL1_ERROR", 15, 15, &umr_bitfield_default }, + { "DMA_DST_UTCL1_ERROR", 16, 16, &umr_bitfield_default }, + { "SR_UTCL1_ERROR", 17, 17, &umr_bitfield_default }, + { "QU_UTCL1_ERROR", 18, 18, &umr_bitfield_default }, + { "TC_UTCL1_ERROR", 19, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HQD_EOP_WPTR_MEM[] = { + { "WPTR", 0, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HQD_AQL_CONTROL[] = { + { "CONTROL0", 0, 14, &umr_bitfield_default }, + { "CONTROL0_EN", 15, 15, &umr_bitfield_default }, + { "CONTROL1", 16, 30, &umr_bitfield_default }, + { "CONTROL1_EN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HQD_PQ_WPTR_LO[] = { + { "OFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HQD_PQ_WPTR_HI[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIDT_IND_INDEX[] = { + { "DIDT_IND_INDEX", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDIDT_IND_DATA[] = { + { "DIDT_IND_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGC_CAC_CTRL_1[] = { + { "CAC_WINDOW", 0, 23, &umr_bitfield_default }, + { "TDP_WINDOW", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGC_CAC_CTRL_2[] = { + { "CAC_ENABLE", 0, 0, &umr_bitfield_default }, + { "CAC_SOFT_CTRL_ENABLE", 1, 1, &umr_bitfield_default }, + { "UNUSED_0", 2, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGC_CAC_CGTT_CLK_CTRL[] = { + { "ON_DELAY", 0, 3, &umr_bitfield_default }, + { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default }, + { "SOFT_OVERRIDE_DYN", 30, 30, &umr_bitfield_default }, + { "SOFT_OVERRIDE_REG", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGC_CAC_AGGR_LOWER[] = { + { "AGGR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGC_CAC_AGGR_UPPER[] = { + { "AGGR_63_32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGC_CAC_PG_AGGR_LOWER[] = { + { "LKG_AGGR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGC_CAC_PG_AGGR_UPPER[] = { + { "LKG_AGGR_63_32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGC_CAC_SOFT_CTRL[] = { + { "SOFT_SNAP", 0, 0, &umr_bitfield_default }, + { "UNUSED", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGC_DIDT_CTRL0[] = { + { "DIDT_CTRL_EN", 0, 0, &umr_bitfield_default }, + { "PHASE_OFFSET", 1, 2, &umr_bitfield_default }, + { "DIDT_SW_RST", 3, 3, &umr_bitfield_default }, + { "DIDT_CLK_EN_OVERRIDE", 4, 4, &umr_bitfield_default }, + { "DIDT_TRIGGER_THROTTLE_LOWBIT", 5, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGC_DIDT_CTRL1[] = { + { "MIN_POWER", 0, 15, &umr_bitfield_default }, + { "MAX_POWER", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGC_DIDT_CTRL2[] = { + { "MAX_POWER_DELTA", 0, 13, &umr_bitfield_default }, + { "UNUSED_0", 14, 15, &umr_bitfield_default }, + { "SHORT_TERM_INTERVAL_SIZE", 16, 25, &umr_bitfield_default }, + { "UNUSED_1", 26, 26, &umr_bitfield_default }, + { "LONG_TERM_INTERVAL_RATIO", 27, 30, &umr_bitfield_default }, + { "UNUSED_2", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGC_DIDT_WEIGHT[] = { + { "SQ_WEIGHT", 0, 7, &umr_bitfield_default }, + { "DB_WEIGHT", 8, 15, &umr_bitfield_default }, + { "TD_WEIGHT", 16, 23, &umr_bitfield_default }, + { "TCP_WEIGHT", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGC_EDC_CTRL[] = { + { "EDC_EN", 0, 0, &umr_bitfield_default }, + { "EDC_SW_RST", 1, 1, &umr_bitfield_default }, + { "EDC_CLK_EN_OVERRIDE", 2, 2, &umr_bitfield_default }, + { "EDC_FORCE_STALL", 3, 3, &umr_bitfield_default }, + { "EDC_TRIGGER_THROTTLE_LOWBIT", 4, 8, &umr_bitfield_default }, + { "EDC_ALLOW_WRITE_PWRDELTA", 9, 9, &umr_bitfield_default }, + { "UNUSED_0", 10, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGC_EDC_THRESHOLD[] = { + { "EDC_THRESHOLD", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGC_EDC_STATUS[] = { + { "EDC_THROTTLE_LEVEL", 0, 2, &umr_bitfield_default }, + { "EDC_ROLLING_DROOP_DELTA", 3, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGC_EDC_OVERFLOW[] = { + { "EDC_ROLLING_POWER_DELTA_OVERFLOW", 0, 0, &umr_bitfield_default }, + { "EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER", 1, 16, &umr_bitfield_default }, + { "EDC_DROOP_LEVEL_OVERFLOW", 17, 17, &umr_bitfield_default }, + { "PSM_COUNTER", 18, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGC_EDC_ROLLING_POWER_DELTA[] = { + { "EDC_ROLLING_POWER_DELTA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGC_DIDT_DROOP_CTRL[] = { + { "DIDT_DROOP_LEVEL_EN", 0, 0, &umr_bitfield_default }, + { "DIDT_DROOP_THRESHOLD", 1, 14, &umr_bitfield_default }, + { "DIDT_DROOP_LEVEL_INDEX", 15, 18, &umr_bitfield_default }, + { "DIDT_LEVEL_SEL", 19, 19, &umr_bitfield_default }, + { "DIDT_DROOP_LEVEL_OVERFLOW", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGC_EDC_DROOP_CTRL[] = { + { "EDC_DROOP_LEVEL_EN", 0, 0, &umr_bitfield_default }, + { "EDC_DROOP_THRESHOLD", 1, 14, &umr_bitfield_default }, + { "EDC_DROOP_LEVEL_INDEX", 15, 19, &umr_bitfield_default }, + { "AVG_PSM_SEL", 20, 20, &umr_bitfield_default }, + { "EDC_LEVEL_SEL", 21, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGC_CAC_IND_INDEX[] = { + { "GC_CAC_IND_ADDR", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGC_CAC_IND_DATA[] = { + { "GC_CAC_IND_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSE_CAC_CGTT_CLK_CTRL[] = { + { "ON_DELAY", 0, 3, &umr_bitfield_default }, + { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default }, + { "SOFT_OVERRIDE_DYN", 30, 30, &umr_bitfield_default }, + { "SOFT_OVERRIDE_REG", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSE_CAC_IND_INDEX[] = { + { "SE_CAC_IND_ADDR", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSE_CAC_IND_DATA[] = { + { "SE_CAC_IND_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCP_WATCH0_ADDR_H[] = { + { "ADDR", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCP_WATCH0_ADDR_L[] = { + { "ADDR", 6, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCP_WATCH0_CNTL[] = { + { "MASK", 0, 23, &umr_bitfield_default }, + { "VMID", 24, 27, &umr_bitfield_default }, + { "ATC", 28, 28, &umr_bitfield_default }, + { "MODE", 29, 30, &umr_bitfield_default }, + { "VALID", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCP_WATCH1_ADDR_H[] = { + { "ADDR", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCP_WATCH1_ADDR_L[] = { + { "ADDR", 6, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCP_WATCH1_CNTL[] = { + { "MASK", 0, 23, &umr_bitfield_default }, + { "VMID", 24, 27, &umr_bitfield_default }, + { "ATC", 28, 28, &umr_bitfield_default }, + { "MODE", 29, 30, &umr_bitfield_default }, + { "VALID", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCP_WATCH2_ADDR_H[] = { + { "ADDR", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCP_WATCH2_ADDR_L[] = { + { "ADDR", 6, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCP_WATCH2_CNTL[] = { + { "MASK", 0, 23, &umr_bitfield_default }, + { "VMID", 24, 27, &umr_bitfield_default }, + { "ATC", 28, 28, &umr_bitfield_default }, + { "MODE", 29, 30, &umr_bitfield_default }, + { "VALID", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCP_WATCH3_ADDR_H[] = { + { "ADDR", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCP_WATCH3_ADDR_L[] = { + { "ADDR", 6, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCP_WATCH3_CNTL[] = { + { "MASK", 0, 23, &umr_bitfield_default }, + { "VMID", 24, 27, &umr_bitfield_default }, + { "ATC", 28, 28, &umr_bitfield_default }, + { "MODE", 29, 30, &umr_bitfield_default }, + { "VALID", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCP_GATCL1_CNTL[] = { + { "INVALIDATE_ALL_VMID", 25, 25, &umr_bitfield_default }, + { "FORCE_MISS", 26, 26, &umr_bitfield_default }, + { "FORCE_IN_ORDER", 27, 27, &umr_bitfield_default }, + { "REDUCE_FIFO_DEPTH_BY_2", 28, 29, &umr_bitfield_default }, + { "REDUCE_CACHE_SIZE_BY_2", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCP_ATC_EDC_GATCL1_CNT[] = { + { "DATA_SEC", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCP_GATCL1_DSM_CNTL[] = { + { "SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0", 0, 0, &umr_bitfield_default }, + { "SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1", 1, 1, &umr_bitfield_default }, + { "TCP_GATCL1_ENABLE_SINGLE_WRITE_A", 2, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCP_CNTL2[] = { + { "LS_DISABLE_CLOCKS", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCP_UTCL1_CNTL1[] = { + { "FORCE_4K_L2_RESP", 0, 0, &umr_bitfield_default }, + { "GPUVM_64K_DEFAULT", 1, 1, &umr_bitfield_default }, + { "GPUVM_PERM_MODE", 2, 2, &umr_bitfield_default }, + { "RESP_MODE", 3, 4, &umr_bitfield_default }, + { "RESP_FAULT_MODE", 5, 6, &umr_bitfield_default }, + { "CLIENTID", 7, 15, &umr_bitfield_default }, + { "REG_INV_VMID", 19, 22, &umr_bitfield_default }, + { "REG_INV_ALL_VMID", 23, 23, &umr_bitfield_default }, + { "REG_INV_TOGGLE", 24, 24, &umr_bitfield_default }, + { "CLIENT_INVALIDATE_ALL_VMID", 25, 25, &umr_bitfield_default }, + { "FORCE_MISS", 26, 26, &umr_bitfield_default }, + { "REDUCE_FIFO_DEPTH_BY_2", 28, 29, &umr_bitfield_default }, + { "REDUCE_CACHE_SIZE_BY_2", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCP_UTCL1_CNTL2[] = { + { "SPARE", 0, 7, &umr_bitfield_default }, + { "MTYPE_OVRD_DIS", 9, 9, &umr_bitfield_default }, + { "ANY_LINE_VALID", 10, 10, &umr_bitfield_default }, + { "GPUVM_INV_MODE", 12, 12, &umr_bitfield_default }, + { "FORCE_SNOOP", 14, 14, &umr_bitfield_default }, + { "FORCE_GPUVM_INV_ACK", 15, 15, &umr_bitfield_default }, + { "FORCE_FRAG_2M_TO_64K", 26, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCP_UTCL1_STATUS[] = { + { "FAULT_DETECTED", 0, 0, &umr_bitfield_default }, + { "RETRY_DETECTED", 1, 1, &umr_bitfield_default }, + { "PRT_DETECTED", 2, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCP_PERFCOUNTER_FILTER[] = { + { "BUFFER", 0, 0, &umr_bitfield_default }, + { "FLAT", 1, 1, &umr_bitfield_default }, + { "DIM", 2, 4, &umr_bitfield_default }, + { "DATA_FORMAT", 5, 10, &umr_bitfield_default }, + { "NUM_FORMAT", 11, 14, &umr_bitfield_default }, + { "SW_MODE", 15, 19, &umr_bitfield_default }, + { "NUM_SAMPLES", 20, 21, &umr_bitfield_default }, + { "OPCODE_TYPE", 22, 24, &umr_bitfield_default }, + { "GLC", 25, 25, &umr_bitfield_default }, + { "SLC", 26, 26, &umr_bitfield_default }, + { "COMPRESSION_ENABLE", 27, 27, &umr_bitfield_default }, + { "ADDR_MODE", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCP_PERFCOUNTER_FILTER_EN[] = { + { "BUFFER", 0, 0, &umr_bitfield_default }, + { "FLAT", 1, 1, &umr_bitfield_default }, + { "DIM", 2, 2, &umr_bitfield_default }, + { "DATA_FORMAT", 3, 3, &umr_bitfield_default }, + { "NUM_FORMAT", 4, 4, &umr_bitfield_default }, + { "SW_MODE", 5, 5, &umr_bitfield_default }, + { "NUM_SAMPLES", 6, 6, &umr_bitfield_default }, + { "OPCODE_TYPE", 7, 7, &umr_bitfield_default }, + { "GLC", 8, 8, &umr_bitfield_default }, + { "SLC", 9, 9, &umr_bitfield_default }, + { "COMPRESSION_ENABLE", 10, 10, &umr_bitfield_default }, + { "ADDR_MODE", 11, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_VMID0_BASE[] = { + { "BASE", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_VMID0_SIZE[] = { + { "SIZE", 0, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_VMID1_BASE[] = { + { "BASE", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_VMID1_SIZE[] = { + { "SIZE", 0, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_VMID2_BASE[] = { + { "BASE", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_VMID2_SIZE[] = { + { "SIZE", 0, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_VMID3_BASE[] = { + { "BASE", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_VMID3_SIZE[] = { + { "SIZE", 0, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_VMID4_BASE[] = { + { "BASE", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_VMID4_SIZE[] = { + { "SIZE", 0, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_VMID5_BASE[] = { + { "BASE", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_VMID5_SIZE[] = { + { "SIZE", 0, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_VMID6_BASE[] = { + { "BASE", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_VMID6_SIZE[] = { + { "SIZE", 0, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_VMID7_BASE[] = { + { "BASE", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_VMID7_SIZE[] = { + { "SIZE", 0, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_VMID8_BASE[] = { + { "BASE", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_VMID8_SIZE[] = { + { "SIZE", 0, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_VMID9_BASE[] = { + { "BASE", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_VMID9_SIZE[] = { + { "SIZE", 0, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_VMID10_BASE[] = { + { "BASE", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_VMID10_SIZE[] = { + { "SIZE", 0, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_VMID11_BASE[] = { + { "BASE", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_VMID11_SIZE[] = { + { "SIZE", 0, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_VMID12_BASE[] = { + { "BASE", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_VMID12_SIZE[] = { + { "SIZE", 0, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_VMID13_BASE[] = { + { "BASE", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_VMID13_SIZE[] = { + { "SIZE", 0, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_VMID14_BASE[] = { + { "BASE", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_VMID14_SIZE[] = { + { "SIZE", 0, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_VMID15_BASE[] = { + { "BASE", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_VMID15_SIZE[] = { + { "SIZE", 0, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_GWS_VMID0[] = { + { "BASE", 0, 5, &umr_bitfield_default }, + { "SIZE", 16, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_GWS_VMID1[] = { + { "BASE", 0, 5, &umr_bitfield_default }, + { "SIZE", 16, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_GWS_VMID2[] = { + { "BASE", 0, 5, &umr_bitfield_default }, + { "SIZE", 16, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_GWS_VMID3[] = { + { "BASE", 0, 5, &umr_bitfield_default }, + { "SIZE", 16, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_GWS_VMID4[] = { + { "BASE", 0, 5, &umr_bitfield_default }, + { "SIZE", 16, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_GWS_VMID5[] = { + { "BASE", 0, 5, &umr_bitfield_default }, + { "SIZE", 16, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_GWS_VMID6[] = { + { "BASE", 0, 5, &umr_bitfield_default }, + { "SIZE", 16, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_GWS_VMID7[] = { + { "BASE", 0, 5, &umr_bitfield_default }, + { "SIZE", 16, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_GWS_VMID8[] = { + { "BASE", 0, 5, &umr_bitfield_default }, + { "SIZE", 16, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_GWS_VMID9[] = { + { "BASE", 0, 5, &umr_bitfield_default }, + { "SIZE", 16, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_GWS_VMID10[] = { + { "BASE", 0, 5, &umr_bitfield_default }, + { "SIZE", 16, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_GWS_VMID11[] = { + { "BASE", 0, 5, &umr_bitfield_default }, + { "SIZE", 16, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_GWS_VMID12[] = { + { "BASE", 0, 5, &umr_bitfield_default }, + { "SIZE", 16, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_GWS_VMID13[] = { + { "BASE", 0, 5, &umr_bitfield_default }, + { "SIZE", 16, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_GWS_VMID14[] = { + { "BASE", 0, 5, &umr_bitfield_default }, + { "SIZE", 16, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_GWS_VMID15[] = { + { "BASE", 0, 5, &umr_bitfield_default }, + { "SIZE", 16, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_OA_VMID0[] = { + { "MASK", 0, 15, &umr_bitfield_default }, + { "UNUSED", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_OA_VMID1[] = { + { "MASK", 0, 15, &umr_bitfield_default }, + { "UNUSED", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_OA_VMID2[] = { + { "MASK", 0, 15, &umr_bitfield_default }, + { "UNUSED", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_OA_VMID3[] = { + { "MASK", 0, 15, &umr_bitfield_default }, + { "UNUSED", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_OA_VMID4[] = { + { "MASK", 0, 15, &umr_bitfield_default }, + { "UNUSED", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_OA_VMID5[] = { + { "MASK", 0, 15, &umr_bitfield_default }, + { "UNUSED", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_OA_VMID6[] = { + { "MASK", 0, 15, &umr_bitfield_default }, + { "UNUSED", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_OA_VMID7[] = { + { "MASK", 0, 15, &umr_bitfield_default }, + { "UNUSED", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_OA_VMID8[] = { + { "MASK", 0, 15, &umr_bitfield_default }, + { "UNUSED", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_OA_VMID9[] = { + { "MASK", 0, 15, &umr_bitfield_default }, + { "UNUSED", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_OA_VMID10[] = { + { "MASK", 0, 15, &umr_bitfield_default }, + { "UNUSED", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_OA_VMID11[] = { + { "MASK", 0, 15, &umr_bitfield_default }, + { "UNUSED", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_OA_VMID12[] = { + { "MASK", 0, 15, &umr_bitfield_default }, + { "UNUSED", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_OA_VMID13[] = { + { "MASK", 0, 15, &umr_bitfield_default }, + { "UNUSED", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_OA_VMID14[] = { + { "MASK", 0, 15, &umr_bitfield_default }, + { "UNUSED", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_OA_VMID15[] = { + { "MASK", 0, 15, &umr_bitfield_default }, + { "UNUSED", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_GWS_RESET0[] = { + { "RESOURCE0_RESET", 0, 0, &umr_bitfield_default }, + { "RESOURCE1_RESET", 1, 1, &umr_bitfield_default }, + { "RESOURCE2_RESET", 2, 2, &umr_bitfield_default }, + { "RESOURCE3_RESET", 3, 3, &umr_bitfield_default }, + { "RESOURCE4_RESET", 4, 4, &umr_bitfield_default }, + { "RESOURCE5_RESET", 5, 5, &umr_bitfield_default }, + { "RESOURCE6_RESET", 6, 6, &umr_bitfield_default }, + { "RESOURCE7_RESET", 7, 7, &umr_bitfield_default }, + { "RESOURCE8_RESET", 8, 8, &umr_bitfield_default }, + { "RESOURCE9_RESET", 9, 9, &umr_bitfield_default }, + { "RESOURCE10_RESET", 10, 10, &umr_bitfield_default }, + { "RESOURCE11_RESET", 11, 11, &umr_bitfield_default }, + { "RESOURCE12_RESET", 12, 12, &umr_bitfield_default }, + { "RESOURCE13_RESET", 13, 13, &umr_bitfield_default }, + { "RESOURCE14_RESET", 14, 14, &umr_bitfield_default }, + { "RESOURCE15_RESET", 15, 15, &umr_bitfield_default }, + { "RESOURCE16_RESET", 16, 16, &umr_bitfield_default }, + { "RESOURCE17_RESET", 17, 17, &umr_bitfield_default }, + { "RESOURCE18_RESET", 18, 18, &umr_bitfield_default }, + { "RESOURCE19_RESET", 19, 19, &umr_bitfield_default }, + { "RESOURCE20_RESET", 20, 20, &umr_bitfield_default }, + { "RESOURCE21_RESET", 21, 21, &umr_bitfield_default }, + { "RESOURCE22_RESET", 22, 22, &umr_bitfield_default }, + { "RESOURCE23_RESET", 23, 23, &umr_bitfield_default }, + { "RESOURCE24_RESET", 24, 24, &umr_bitfield_default }, + { "RESOURCE25_RESET", 25, 25, &umr_bitfield_default }, + { "RESOURCE26_RESET", 26, 26, &umr_bitfield_default }, + { "RESOURCE27_RESET", 27, 27, &umr_bitfield_default }, + { "RESOURCE28_RESET", 28, 28, &umr_bitfield_default }, + { "RESOURCE29_RESET", 29, 29, &umr_bitfield_default }, + { "RESOURCE30_RESET", 30, 30, &umr_bitfield_default }, + { "RESOURCE31_RESET", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_GWS_RESET1[] = { + { "RESOURCE32_RESET", 0, 0, &umr_bitfield_default }, + { "RESOURCE33_RESET", 1, 1, &umr_bitfield_default }, + { "RESOURCE34_RESET", 2, 2, &umr_bitfield_default }, + { "RESOURCE35_RESET", 3, 3, &umr_bitfield_default }, + { "RESOURCE36_RESET", 4, 4, &umr_bitfield_default }, + { "RESOURCE37_RESET", 5, 5, &umr_bitfield_default }, + { "RESOURCE38_RESET", 6, 6, &umr_bitfield_default }, + { "RESOURCE39_RESET", 7, 7, &umr_bitfield_default }, + { "RESOURCE40_RESET", 8, 8, &umr_bitfield_default }, + { "RESOURCE41_RESET", 9, 9, &umr_bitfield_default }, + { "RESOURCE42_RESET", 10, 10, &umr_bitfield_default }, + { "RESOURCE43_RESET", 11, 11, &umr_bitfield_default }, + { "RESOURCE44_RESET", 12, 12, &umr_bitfield_default }, + { "RESOURCE45_RESET", 13, 13, &umr_bitfield_default }, + { "RESOURCE46_RESET", 14, 14, &umr_bitfield_default }, + { "RESOURCE47_RESET", 15, 15, &umr_bitfield_default }, + { "RESOURCE48_RESET", 16, 16, &umr_bitfield_default }, + { "RESOURCE49_RESET", 17, 17, &umr_bitfield_default }, + { "RESOURCE50_RESET", 18, 18, &umr_bitfield_default }, + { "RESOURCE51_RESET", 19, 19, &umr_bitfield_default }, + { "RESOURCE52_RESET", 20, 20, &umr_bitfield_default }, + { "RESOURCE53_RESET", 21, 21, &umr_bitfield_default }, + { "RESOURCE54_RESET", 22, 22, &umr_bitfield_default }, + { "RESOURCE55_RESET", 23, 23, &umr_bitfield_default }, + { "RESOURCE56_RESET", 24, 24, &umr_bitfield_default }, + { "RESOURCE57_RESET", 25, 25, &umr_bitfield_default }, + { "RESOURCE58_RESET", 26, 26, &umr_bitfield_default }, + { "RESOURCE59_RESET", 27, 27, &umr_bitfield_default }, + { "RESOURCE60_RESET", 28, 28, &umr_bitfield_default }, + { "RESOURCE61_RESET", 29, 29, &umr_bitfield_default }, + { "RESOURCE62_RESET", 30, 30, &umr_bitfield_default }, + { "RESOURCE63_RESET", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_GWS_RESOURCE_RESET[] = { + { "RESET", 0, 0, &umr_bitfield_default }, + { "RESOURCE_ID", 8, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_COMPUTE_MAX_WAVE_ID[] = { + { "MAX_WAVE_ID", 0, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_OA_RESET_MASK[] = { + { "ME0_GFXHP3D_PIX_RESET", 0, 0, &umr_bitfield_default }, + { "ME0_GFXHP3D_VTX_RESET", 1, 1, &umr_bitfield_default }, + { "ME0_CS_RESET", 2, 2, &umr_bitfield_default }, + { "ME0_GFXHP3D_GS_RESET", 3, 3, &umr_bitfield_default }, + { "ME1_PIPE0_RESET", 4, 4, &umr_bitfield_default }, + { "ME1_PIPE1_RESET", 5, 5, &umr_bitfield_default }, + { "ME1_PIPE2_RESET", 6, 6, &umr_bitfield_default }, + { "ME1_PIPE3_RESET", 7, 7, &umr_bitfield_default }, + { "ME2_PIPE0_RESET", 8, 8, &umr_bitfield_default }, + { "ME2_PIPE1_RESET", 9, 9, &umr_bitfield_default }, + { "ME2_PIPE2_RESET", 10, 10, &umr_bitfield_default }, + { "ME2_PIPE3_RESET", 11, 11, &umr_bitfield_default }, + { "UNUSED1", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_OA_RESET[] = { + { "RESET", 0, 0, &umr_bitfield_default }, + { "PIPE_ID", 8, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_ENHANCE[] = { + { "MISC", 0, 15, &umr_bitfield_default }, + { "AUTO_INC_INDEX", 16, 16, &umr_bitfield_default }, + { "CGPG_RESTORE", 17, 17, &umr_bitfield_default }, + { "RD_BUF_TAG_MISS", 18, 18, &umr_bitfield_default }, + { "GDSA_PC_CGTS_DIS", 19, 19, &umr_bitfield_default }, + { "GDSO_PC_CGTS_DIS", 20, 20, &umr_bitfield_default }, + { "WD_GDS_CSB_OVERRIDE", 21, 21, &umr_bitfield_default }, + { "UNUSED", 22, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_OA_CGPG_RESTORE[] = { + { "VMID", 0, 7, &umr_bitfield_default }, + { "MEID", 8, 11, &umr_bitfield_default }, + { "PIPEID", 12, 15, &umr_bitfield_default }, + { "QUEUEID", 16, 19, &umr_bitfield_default }, + { "UNUSED", 20, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_CS_CTXSW_STATUS[] = { + { "R", 0, 0, &umr_bitfield_default }, + { "W", 1, 1, &umr_bitfield_default }, + { "UNUSED", 2, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_CS_CTXSW_CNT0[] = { + { "UPDN", 0, 15, &umr_bitfield_default }, + { "PTR", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_CS_CTXSW_CNT1[] = { + { "UPDN", 0, 15, &umr_bitfield_default }, + { "PTR", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_CS_CTXSW_CNT2[] = { + { "UPDN", 0, 15, &umr_bitfield_default }, + { "PTR", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_CS_CTXSW_CNT3[] = { + { "UPDN", 0, 15, &umr_bitfield_default }, + { "PTR", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_GFX_CTXSW_STATUS[] = { + { "R", 0, 0, &umr_bitfield_default }, + { "W", 1, 1, &umr_bitfield_default }, + { "UNUSED", 2, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_VS_CTXSW_CNT0[] = { + { "UPDN", 0, 15, &umr_bitfield_default }, + { "PTR", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_VS_CTXSW_CNT1[] = { + { "UPDN", 0, 15, &umr_bitfield_default }, + { "PTR", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_VS_CTXSW_CNT2[] = { + { "UPDN", 0, 15, &umr_bitfield_default }, + { "PTR", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_VS_CTXSW_CNT3[] = { + { "UPDN", 0, 15, &umr_bitfield_default }, + { "PTR", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_PS0_CTXSW_CNT0[] = { + { "UPDN", 0, 15, &umr_bitfield_default }, + { "PTR", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_PS0_CTXSW_CNT1[] = { + { "UPDN", 0, 15, &umr_bitfield_default }, + { "PTR", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_PS0_CTXSW_CNT2[] = { + { "UPDN", 0, 15, &umr_bitfield_default }, + { "PTR", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_PS0_CTXSW_CNT3[] = { + { "UPDN", 0, 15, &umr_bitfield_default }, + { "PTR", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_PS1_CTXSW_CNT0[] = { + { "UPDN", 0, 15, &umr_bitfield_default }, + { "PTR", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_PS1_CTXSW_CNT1[] = { + { "UPDN", 0, 15, &umr_bitfield_default }, + { "PTR", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_PS1_CTXSW_CNT2[] = { + { "UPDN", 0, 15, &umr_bitfield_default }, + { "PTR", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_PS1_CTXSW_CNT3[] = { + { "UPDN", 0, 15, &umr_bitfield_default }, + { "PTR", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_PS2_CTXSW_CNT0[] = { + { "UPDN", 0, 15, &umr_bitfield_default }, + { "PTR", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_PS2_CTXSW_CNT1[] = { + { "UPDN", 0, 15, &umr_bitfield_default }, + { "PTR", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_PS2_CTXSW_CNT2[] = { + { "UPDN", 0, 15, &umr_bitfield_default }, + { "PTR", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_PS2_CTXSW_CNT3[] = { + { "UPDN", 0, 15, &umr_bitfield_default }, + { "PTR", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_PS3_CTXSW_CNT0[] = { + { "UPDN", 0, 15, &umr_bitfield_default }, + { "PTR", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_PS3_CTXSW_CNT1[] = { + { "UPDN", 0, 15, &umr_bitfield_default }, + { "PTR", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_PS3_CTXSW_CNT2[] = { + { "UPDN", 0, 15, &umr_bitfield_default }, + { "PTR", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_PS3_CTXSW_CNT3[] = { + { "UPDN", 0, 15, &umr_bitfield_default }, + { "PTR", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_PS4_CTXSW_CNT0[] = { + { "UPDN", 0, 15, &umr_bitfield_default }, + { "PTR", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_PS4_CTXSW_CNT1[] = { + { "UPDN", 0, 15, &umr_bitfield_default }, + { "PTR", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_PS4_CTXSW_CNT2[] = { + { "UPDN", 0, 15, &umr_bitfield_default }, + { "PTR", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_PS4_CTXSW_CNT3[] = { + { "UPDN", 0, 15, &umr_bitfield_default }, + { "PTR", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_PS5_CTXSW_CNT0[] = { + { "UPDN", 0, 15, &umr_bitfield_default }, + { "PTR", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_PS5_CTXSW_CNT1[] = { + { "UPDN", 0, 15, &umr_bitfield_default }, + { "PTR", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_PS5_CTXSW_CNT2[] = { + { "UPDN", 0, 15, &umr_bitfield_default }, + { "PTR", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_PS5_CTXSW_CNT3[] = { + { "UPDN", 0, 15, &umr_bitfield_default }, + { "PTR", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_PS6_CTXSW_CNT0[] = { + { "UPDN", 0, 15, &umr_bitfield_default }, + { "PTR", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_PS6_CTXSW_CNT1[] = { + { "UPDN", 0, 15, &umr_bitfield_default }, + { "PTR", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_PS6_CTXSW_CNT2[] = { + { "UPDN", 0, 15, &umr_bitfield_default }, + { "PTR", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_PS6_CTXSW_CNT3[] = { + { "UPDN", 0, 15, &umr_bitfield_default }, + { "PTR", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_PS7_CTXSW_CNT0[] = { + { "UPDN", 0, 15, &umr_bitfield_default }, + { "PTR", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_PS7_CTXSW_CNT1[] = { + { "UPDN", 0, 15, &umr_bitfield_default }, + { "PTR", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_PS7_CTXSW_CNT2[] = { + { "UPDN", 0, 15, &umr_bitfield_default }, + { "PTR", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_PS7_CTXSW_CNT3[] = { + { "UPDN", 0, 15, &umr_bitfield_default }, + { "PTR", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_GS_CTXSW_CNT0[] = { + { "UPDN", 0, 15, &umr_bitfield_default }, + { "PTR", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_GS_CTXSW_CNT1[] = { + { "UPDN", 0, 15, &umr_bitfield_default }, + { "PTR", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_GS_CTXSW_CNT2[] = { + { "UPDN", 0, 15, &umr_bitfield_default }, + { "PTR", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_GS_CTXSW_CNT3[] = { + { "UPDN", 0, 15, &umr_bitfield_default }, + { "PTR", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRAS_SIGNATURE_CONTROL[] = { + { "ENABLE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRAS_SIGNATURE_MASK[] = { + { "INPUT_BUS_MASK", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRAS_SX_SIGNATURE0[] = { + { "SIGNATURE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRAS_SX_SIGNATURE1[] = { + { "SIGNATURE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRAS_SX_SIGNATURE2[] = { + { "SIGNATURE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRAS_SX_SIGNATURE3[] = { + { "SIGNATURE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRAS_DB_SIGNATURE0[] = { + { "SIGNATURE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRAS_PA_SIGNATURE0[] = { + { "SIGNATURE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRAS_VGT_SIGNATURE0[] = { + { "SIGNATURE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRAS_SQ_SIGNATURE0[] = { + { "SIGNATURE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRAS_SC_SIGNATURE0[] = { + { "SIGNATURE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRAS_SC_SIGNATURE1[] = { + { "SIGNATURE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRAS_SC_SIGNATURE2[] = { + { "SIGNATURE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRAS_SC_SIGNATURE3[] = { + { "SIGNATURE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRAS_SC_SIGNATURE4[] = { + { "SIGNATURE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRAS_SC_SIGNATURE5[] = { + { "SIGNATURE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRAS_SC_SIGNATURE6[] = { + { "SIGNATURE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRAS_SC_SIGNATURE7[] = { + { "SIGNATURE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRAS_IA_SIGNATURE0[] = { + { "SIGNATURE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRAS_IA_SIGNATURE1[] = { + { "SIGNATURE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRAS_SPI_SIGNATURE0[] = { + { "SIGNATURE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRAS_SPI_SIGNATURE1[] = { + { "SIGNATURE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRAS_TA_SIGNATURE0[] = { + { "SIGNATURE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRAS_TD_SIGNATURE0[] = { + { "SIGNATURE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRAS_CB_SIGNATURE0[] = { + { "SIGNATURE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRAS_BCI_SIGNATURE0[] = { + { "SIGNATURE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRAS_BCI_SIGNATURE1[] = { + { "SIGNATURE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRAS_TA_SIGNATURE1[] = { + { "SIGNATURE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_RENDER_CONTROL[] = { + { "DEPTH_CLEAR_ENABLE", 0, 0, &umr_bitfield_default }, + { "STENCIL_CLEAR_ENABLE", 1, 1, &umr_bitfield_default }, + { "DEPTH_COPY", 2, 2, &umr_bitfield_default }, + { "STENCIL_COPY", 3, 3, &umr_bitfield_default }, + { "RESUMMARIZE_ENABLE", 4, 4, &umr_bitfield_default }, + { "STENCIL_COMPRESS_DISABLE", 5, 5, &umr_bitfield_default }, + { "DEPTH_COMPRESS_DISABLE", 6, 6, &umr_bitfield_default }, + { "COPY_CENTROID", 7, 7, &umr_bitfield_default }, + { "COPY_SAMPLE", 8, 11, &umr_bitfield_default }, + { "DECOMPRESS_ENABLE", 12, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_COUNT_CONTROL[] = { + { "ZPASS_INCREMENT_DISABLE", 0, 0, &umr_bitfield_default }, + { "PERFECT_ZPASS_COUNTS", 1, 1, &umr_bitfield_default }, + { "SAMPLE_RATE", 4, 6, &umr_bitfield_default }, + { "ZPASS_ENABLE", 8, 11, &umr_bitfield_default }, + { "ZFAIL_ENABLE", 12, 15, &umr_bitfield_default }, + { "SFAIL_ENABLE", 16, 19, &umr_bitfield_default }, + { "DBFAIL_ENABLE", 20, 23, &umr_bitfield_default }, + { "SLICE_EVEN_ENABLE", 24, 27, &umr_bitfield_default }, + { "SLICE_ODD_ENABLE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_DEPTH_VIEW[] = { + { "SLICE_START", 0, 10, &umr_bitfield_default }, + { "SLICE_MAX", 13, 23, &umr_bitfield_default }, + { "Z_READ_ONLY", 24, 24, &umr_bitfield_default }, + { "STENCIL_READ_ONLY", 25, 25, &umr_bitfield_default }, + { "MIPID", 26, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_RENDER_OVERRIDE[] = { + { "FORCE_HIZ_ENABLE", 0, 1, &umr_bitfield_default }, + { "FORCE_HIS_ENABLE0", 2, 3, &umr_bitfield_default }, + { "FORCE_HIS_ENABLE1", 4, 5, &umr_bitfield_default }, + { "FORCE_SHADER_Z_ORDER", 6, 6, &umr_bitfield_default }, + { "FAST_Z_DISABLE", 7, 7, &umr_bitfield_default }, + { "FAST_STENCIL_DISABLE", 8, 8, &umr_bitfield_default }, + { "NOOP_CULL_DISABLE", 9, 9, &umr_bitfield_default }, + { "FORCE_COLOR_KILL", 10, 10, &umr_bitfield_default }, + { "FORCE_Z_READ", 11, 11, &umr_bitfield_default }, + { "FORCE_STENCIL_READ", 12, 12, &umr_bitfield_default }, + { "FORCE_FULL_Z_RANGE", 13, 14, &umr_bitfield_default }, + { "FORCE_QC_SMASK_CONFLICT", 15, 15, &umr_bitfield_default }, + { "DISABLE_VIEWPORT_CLAMP", 16, 16, &umr_bitfield_default }, + { "IGNORE_SC_ZRANGE", 17, 17, &umr_bitfield_default }, + { "DISABLE_FULLY_COVERED", 18, 18, &umr_bitfield_default }, + { "FORCE_Z_LIMIT_SUMM", 19, 20, &umr_bitfield_default }, + { "MAX_TILES_IN_DTT", 21, 25, &umr_bitfield_default }, + { "DISABLE_TILE_RATE_TILES", 26, 26, &umr_bitfield_default }, + { "FORCE_Z_DIRTY", 27, 27, &umr_bitfield_default }, + { "FORCE_STENCIL_DIRTY", 28, 28, &umr_bitfield_default }, + { "FORCE_Z_VALID", 29, 29, &umr_bitfield_default }, + { "FORCE_STENCIL_VALID", 30, 30, &umr_bitfield_default }, + { "PRESERVE_COMPRESSION", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_RENDER_OVERRIDE2[] = { + { "PARTIAL_SQUAD_LAUNCH_CONTROL", 0, 1, &umr_bitfield_default }, + { "PARTIAL_SQUAD_LAUNCH_COUNTDOWN", 2, 4, &umr_bitfield_default }, + { "DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION", 5, 5, &umr_bitfield_default }, + { "DISABLE_SMEM_EXPCLEAR_OPTIMIZATION", 6, 6, &umr_bitfield_default }, + { "DISABLE_COLOR_ON_VALIDATION", 7, 7, &umr_bitfield_default }, + { "DECOMPRESS_Z_ON_FLUSH", 8, 8, &umr_bitfield_default }, + { "DISABLE_REG_SNOOP", 9, 9, &umr_bitfield_default }, + { "DEPTH_BOUNDS_HIER_DEPTH_DISABLE", 10, 10, &umr_bitfield_default }, + { "SEPARATE_HIZS_FUNC_ENABLE", 11, 11, &umr_bitfield_default }, + { "HIZ_ZFUNC", 12, 14, &umr_bitfield_default }, + { "HIS_SFUNC_FF", 15, 17, &umr_bitfield_default }, + { "HIS_SFUNC_BF", 18, 20, &umr_bitfield_default }, + { "PRESERVE_ZRANGE", 21, 21, &umr_bitfield_default }, + { "PRESERVE_SRESULTS", 22, 22, &umr_bitfield_default }, + { "DISABLE_FAST_PASS", 23, 23, &umr_bitfield_default }, + { "ALLOW_PARTIAL_RES_HIER_KILL", 25, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_HTILE_DATA_BASE[] = { + { "BASE_256B", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_HTILE_DATA_BASE_HI[] = { + { "BASE_HI", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_DEPTH_SIZE[] = { + { "X_MAX", 0, 13, &umr_bitfield_default }, + { "Y_MAX", 16, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_DEPTH_BOUNDS_MIN[] = { + { "MIN", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_DEPTH_BOUNDS_MAX[] = { + { "MAX", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_STENCIL_CLEAR[] = { + { "CLEAR", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_DEPTH_CLEAR[] = { + { "DEPTH_CLEAR", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_SCREEN_SCISSOR_TL[] = { + { "TL_X", 0, 15, &umr_bitfield_default }, + { "TL_Y", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_SCREEN_SCISSOR_BR[] = { + { "BR_X", 0, 15, &umr_bitfield_default }, + { "BR_Y", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_Z_INFO[] = { + { "FORMAT", 0, 1, &umr_bitfield_default }, + { "NUM_SAMPLES", 2, 3, &umr_bitfield_default }, + { "SW_MODE", 4, 8, &umr_bitfield_default }, + { "PARTIALLY_RESIDENT", 12, 12, &umr_bitfield_default }, + { "FAULT_BEHAVIOR", 13, 14, &umr_bitfield_default }, + { "ITERATE_FLUSH", 15, 15, &umr_bitfield_default }, + { "MAXMIP", 16, 19, &umr_bitfield_default }, + { "DECOMPRESS_ON_N_ZPLANES", 23, 26, &umr_bitfield_default }, + { "ALLOW_EXPCLEAR", 27, 27, &umr_bitfield_default }, + { "READ_SIZE", 28, 28, &umr_bitfield_default }, + { "TILE_SURFACE_ENABLE", 29, 29, &umr_bitfield_default }, + { "CLEAR_DISALLOWED", 30, 30, &umr_bitfield_default }, + { "ZRANGE_PRECISION", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_STENCIL_INFO[] = { + { "FORMAT", 0, 0, &umr_bitfield_default }, + { "SW_MODE", 4, 8, &umr_bitfield_default }, + { "PARTIALLY_RESIDENT", 12, 12, &umr_bitfield_default }, + { "FAULT_BEHAVIOR", 13, 14, &umr_bitfield_default }, + { "ITERATE_FLUSH", 15, 15, &umr_bitfield_default }, + { "ALLOW_EXPCLEAR", 27, 27, &umr_bitfield_default }, + { "TILE_STENCIL_DISABLE", 29, 29, &umr_bitfield_default }, + { "CLEAR_DISALLOWED", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_Z_READ_BASE[] = { + { "BASE_256B", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_Z_READ_BASE_HI[] = { + { "BASE_HI", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_STENCIL_READ_BASE[] = { + { "BASE_256B", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_STENCIL_READ_BASE_HI[] = { + { "BASE_HI", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_Z_WRITE_BASE[] = { + { "BASE_256B", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_Z_WRITE_BASE_HI[] = { + { "BASE_HI", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_STENCIL_WRITE_BASE[] = { + { "BASE_256B", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_STENCIL_WRITE_BASE_HI[] = { + { "BASE_HI", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_DFSM_CONTROL[] = { + { "PUNCHOUT_MODE", 0, 1, &umr_bitfield_default }, + { "POPS_DRAIN_PS_ON_OVERLAP", 2, 2, &umr_bitfield_default }, + { "DISALLOW_OVERFLOW", 3, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_RENDER_FILTER[] = { + { "PS_INVOKE_MASK", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_Z_INFO2[] = { + { "EPITCH", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_STENCIL_INFO2[] = { + { "EPITCH", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTA_BC_BASE_ADDR[] = { + { "ADDRESS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTA_BC_BASE_ADDR_HI[] = { + { "ADDRESS", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCOHER_DEST_BASE_HI_0[] = { + { "DEST_BASE_HI_256B", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCOHER_DEST_BASE_HI_1[] = { + { "DEST_BASE_HI_256B", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCOHER_DEST_BASE_HI_2[] = { + { "DEST_BASE_HI_256B", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCOHER_DEST_BASE_HI_3[] = { + { "DEST_BASE_HI_256B", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCOHER_DEST_BASE_2[] = { + { "DEST_BASE_256B", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCOHER_DEST_BASE_3[] = { + { "DEST_BASE_256B", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_WINDOW_OFFSET[] = { + { "WINDOW_X_OFFSET", 0, 15, &umr_bitfield_default }, + { "WINDOW_Y_OFFSET", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_WINDOW_SCISSOR_TL[] = { + { "TL_X", 0, 14, &umr_bitfield_default }, + { "TL_Y", 16, 30, &umr_bitfield_default }, + { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_WINDOW_SCISSOR_BR[] = { + { "BR_X", 0, 14, &umr_bitfield_default }, + { "BR_Y", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_CLIPRECT_RULE[] = { + { "CLIP_RULE", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_CLIPRECT_0_TL[] = { + { "TL_X", 0, 14, &umr_bitfield_default }, + { "TL_Y", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_CLIPRECT_0_BR[] = { + { "BR_X", 0, 14, &umr_bitfield_default }, + { "BR_Y", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_CLIPRECT_1_TL[] = { + { "TL_X", 0, 14, &umr_bitfield_default }, + { "TL_Y", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_CLIPRECT_1_BR[] = { + { "BR_X", 0, 14, &umr_bitfield_default }, + { "BR_Y", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_CLIPRECT_2_TL[] = { + { "TL_X", 0, 14, &umr_bitfield_default }, + { "TL_Y", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_CLIPRECT_2_BR[] = { + { "BR_X", 0, 14, &umr_bitfield_default }, + { "BR_Y", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_CLIPRECT_3_TL[] = { + { "TL_X", 0, 14, &umr_bitfield_default }, + { "TL_Y", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_CLIPRECT_3_BR[] = { + { "BR_X", 0, 14, &umr_bitfield_default }, + { "BR_Y", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_EDGERULE[] = { + { "ER_TRI", 0, 3, &umr_bitfield_default }, + { "ER_POINT", 4, 7, &umr_bitfield_default }, + { "ER_RECT", 8, 11, &umr_bitfield_default }, + { "ER_LINE_LR", 12, 17, &umr_bitfield_default }, + { "ER_LINE_RL", 18, 23, &umr_bitfield_default }, + { "ER_LINE_TB", 24, 27, &umr_bitfield_default }, + { "ER_LINE_BT", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SU_HARDWARE_SCREEN_OFFSET[] = { + { "HW_SCREEN_OFFSET_X", 0, 8, &umr_bitfield_default }, + { "HW_SCREEN_OFFSET_Y", 16, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_TARGET_MASK[] = { + { "TARGET0_ENABLE", 0, 3, &umr_bitfield_default }, + { "TARGET1_ENABLE", 4, 7, &umr_bitfield_default }, + { "TARGET2_ENABLE", 8, 11, &umr_bitfield_default }, + { "TARGET3_ENABLE", 12, 15, &umr_bitfield_default }, + { "TARGET4_ENABLE", 16, 19, &umr_bitfield_default }, + { "TARGET5_ENABLE", 20, 23, &umr_bitfield_default }, + { "TARGET6_ENABLE", 24, 27, &umr_bitfield_default }, + { "TARGET7_ENABLE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_SHADER_MASK[] = { + { "OUTPUT0_ENABLE", 0, 3, &umr_bitfield_default }, + { "OUTPUT1_ENABLE", 4, 7, &umr_bitfield_default }, + { "OUTPUT2_ENABLE", 8, 11, &umr_bitfield_default }, + { "OUTPUT3_ENABLE", 12, 15, &umr_bitfield_default }, + { "OUTPUT4_ENABLE", 16, 19, &umr_bitfield_default }, + { "OUTPUT5_ENABLE", 20, 23, &umr_bitfield_default }, + { "OUTPUT6_ENABLE", 24, 27, &umr_bitfield_default }, + { "OUTPUT7_ENABLE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_GENERIC_SCISSOR_TL[] = { + { "TL_X", 0, 14, &umr_bitfield_default }, + { "TL_Y", 16, 30, &umr_bitfield_default }, + { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_GENERIC_SCISSOR_BR[] = { + { "BR_X", 0, 14, &umr_bitfield_default }, + { "BR_Y", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCOHER_DEST_BASE_0[] = { + { "DEST_BASE_256B", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCOHER_DEST_BASE_1[] = { + { "DEST_BASE_256B", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_0_TL[] = { + { "TL_X", 0, 14, &umr_bitfield_default }, + { "TL_Y", 16, 30, &umr_bitfield_default }, + { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_0_BR[] = { + { "BR_X", 0, 14, &umr_bitfield_default }, + { "BR_Y", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_1_TL[] = { + { "TL_X", 0, 14, &umr_bitfield_default }, + { "TL_Y", 16, 30, &umr_bitfield_default }, + { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_1_BR[] = { + { "BR_X", 0, 14, &umr_bitfield_default }, + { "BR_Y", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_2_TL[] = { + { "TL_X", 0, 14, &umr_bitfield_default }, + { "TL_Y", 16, 30, &umr_bitfield_default }, + { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_2_BR[] = { + { "BR_X", 0, 14, &umr_bitfield_default }, + { "BR_Y", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_3_TL[] = { + { "TL_X", 0, 14, &umr_bitfield_default }, + { "TL_Y", 16, 30, &umr_bitfield_default }, + { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_3_BR[] = { + { "BR_X", 0, 14, &umr_bitfield_default }, + { "BR_Y", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_4_TL[] = { + { "TL_X", 0, 14, &umr_bitfield_default }, + { "TL_Y", 16, 30, &umr_bitfield_default }, + { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_4_BR[] = { + { "BR_X", 0, 14, &umr_bitfield_default }, + { "BR_Y", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_5_TL[] = { + { "TL_X", 0, 14, &umr_bitfield_default }, + { "TL_Y", 16, 30, &umr_bitfield_default }, + { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_5_BR[] = { + { "BR_X", 0, 14, &umr_bitfield_default }, + { "BR_Y", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_6_TL[] = { + { "TL_X", 0, 14, &umr_bitfield_default }, + { "TL_Y", 16, 30, &umr_bitfield_default }, + { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_6_BR[] = { + { "BR_X", 0, 14, &umr_bitfield_default }, + { "BR_Y", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_7_TL[] = { + { "TL_X", 0, 14, &umr_bitfield_default }, + { "TL_Y", 16, 30, &umr_bitfield_default }, + { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_7_BR[] = { + { "BR_X", 0, 14, &umr_bitfield_default }, + { "BR_Y", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_8_TL[] = { + { "TL_X", 0, 14, &umr_bitfield_default }, + { "TL_Y", 16, 30, &umr_bitfield_default }, + { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_8_BR[] = { + { "BR_X", 0, 14, &umr_bitfield_default }, + { "BR_Y", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_9_TL[] = { + { "TL_X", 0, 14, &umr_bitfield_default }, + { "TL_Y", 16, 30, &umr_bitfield_default }, + { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_9_BR[] = { + { "BR_X", 0, 14, &umr_bitfield_default }, + { "BR_Y", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_10_TL[] = { + { "TL_X", 0, 14, &umr_bitfield_default }, + { "TL_Y", 16, 30, &umr_bitfield_default }, + { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_10_BR[] = { + { "BR_X", 0, 14, &umr_bitfield_default }, + { "BR_Y", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_11_TL[] = { + { "TL_X", 0, 14, &umr_bitfield_default }, + { "TL_Y", 16, 30, &umr_bitfield_default }, + { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_11_BR[] = { + { "BR_X", 0, 14, &umr_bitfield_default }, + { "BR_Y", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_12_TL[] = { + { "TL_X", 0, 14, &umr_bitfield_default }, + { "TL_Y", 16, 30, &umr_bitfield_default }, + { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_12_BR[] = { + { "BR_X", 0, 14, &umr_bitfield_default }, + { "BR_Y", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_13_TL[] = { + { "TL_X", 0, 14, &umr_bitfield_default }, + { "TL_Y", 16, 30, &umr_bitfield_default }, + { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_13_BR[] = { + { "BR_X", 0, 14, &umr_bitfield_default }, + { "BR_Y", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_14_TL[] = { + { "TL_X", 0, 14, &umr_bitfield_default }, + { "TL_Y", 16, 30, &umr_bitfield_default }, + { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_14_BR[] = { + { "BR_X", 0, 14, &umr_bitfield_default }, + { "BR_Y", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_15_TL[] = { + { "TL_X", 0, 14, &umr_bitfield_default }, + { "TL_Y", 16, 30, &umr_bitfield_default }, + { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_15_BR[] = { + { "BR_X", 0, 14, &umr_bitfield_default }, + { "BR_Y", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_VPORT_ZMIN_0[] = { + { "VPORT_ZMIN", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_VPORT_ZMAX_0[] = { + { "VPORT_ZMAX", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_VPORT_ZMIN_1[] = { + { "VPORT_ZMIN", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_VPORT_ZMAX_1[] = { + { "VPORT_ZMAX", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_VPORT_ZMIN_2[] = { + { "VPORT_ZMIN", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_VPORT_ZMAX_2[] = { + { "VPORT_ZMAX", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_VPORT_ZMIN_3[] = { + { "VPORT_ZMIN", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_VPORT_ZMAX_3[] = { + { "VPORT_ZMAX", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_VPORT_ZMIN_4[] = { + { "VPORT_ZMIN", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_VPORT_ZMAX_4[] = { + { "VPORT_ZMAX", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_VPORT_ZMIN_5[] = { + { "VPORT_ZMIN", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_VPORT_ZMAX_5[] = { + { "VPORT_ZMAX", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_VPORT_ZMIN_6[] = { + { "VPORT_ZMIN", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_VPORT_ZMAX_6[] = { + { "VPORT_ZMAX", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_VPORT_ZMIN_7[] = { + { "VPORT_ZMIN", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_VPORT_ZMAX_7[] = { + { "VPORT_ZMAX", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_VPORT_ZMIN_8[] = { + { "VPORT_ZMIN", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_VPORT_ZMAX_8[] = { + { "VPORT_ZMAX", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_VPORT_ZMIN_9[] = { + { "VPORT_ZMIN", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_VPORT_ZMAX_9[] = { + { "VPORT_ZMAX", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_VPORT_ZMIN_10[] = { + { "VPORT_ZMIN", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_VPORT_ZMAX_10[] = { + { "VPORT_ZMAX", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_VPORT_ZMIN_11[] = { + { "VPORT_ZMIN", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_VPORT_ZMAX_11[] = { + { "VPORT_ZMAX", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_VPORT_ZMIN_12[] = { + { "VPORT_ZMIN", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_VPORT_ZMAX_12[] = { + { "VPORT_ZMAX", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_VPORT_ZMIN_13[] = { + { "VPORT_ZMIN", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_VPORT_ZMAX_13[] = { + { "VPORT_ZMAX", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_VPORT_ZMIN_14[] = { + { "VPORT_ZMIN", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_VPORT_ZMAX_14[] = { + { "VPORT_ZMAX", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_VPORT_ZMIN_15[] = { + { "VPORT_ZMIN", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_VPORT_ZMAX_15[] = { + { "VPORT_ZMAX", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_RASTER_CONFIG[] = { + { "RB_MAP_PKR0", 0, 1, &umr_bitfield_default }, + { "RB_MAP_PKR1", 2, 3, &umr_bitfield_default }, + { "RB_XSEL2", 4, 5, &umr_bitfield_default }, + { "RB_XSEL", 6, 6, &umr_bitfield_default }, + { "RB_YSEL", 7, 7, &umr_bitfield_default }, + { "PKR_MAP", 8, 9, &umr_bitfield_default }, + { "PKR_XSEL", 10, 11, &umr_bitfield_default }, + { "PKR_YSEL", 12, 13, &umr_bitfield_default }, + { "PKR_XSEL2", 14, 15, &umr_bitfield_default }, + { "SC_MAP", 16, 17, &umr_bitfield_default }, + { "SC_XSEL", 18, 19, &umr_bitfield_default }, + { "SC_YSEL", 20, 21, &umr_bitfield_default }, + { "SE_MAP", 24, 25, &umr_bitfield_default }, + { "SE_XSEL", 26, 28, &umr_bitfield_default }, + { "SE_YSEL", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_RASTER_CONFIG_1[] = { + { "SE_PAIR_MAP", 0, 1, &umr_bitfield_default }, + { "SE_PAIR_XSEL", 2, 4, &umr_bitfield_default }, + { "SE_PAIR_YSEL", 5, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_SCREEN_EXTENT_CONTROL[] = { + { "SLICE_EVEN_ENABLE", 0, 1, &umr_bitfield_default }, + { "SLICE_ODD_ENABLE", 2, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_TILE_STEERING_OVERRIDE[] = { + { "ENABLE", 0, 0, &umr_bitfield_default }, + { "NUM_SE", 1, 2, &umr_bitfield_default }, + { "NUM_RB_PER_SE", 5, 6, &umr_bitfield_default }, + { "DISABLE_SRBSL_DB_OPTIMIZED_PACKING", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_PERFMON_CNTX_CNTL[] = { + { "PERFMON_ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_PIPEID[] = { + { "PIPE_ID", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_RINGID[] = { + { "RINGID", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_VMID[] = { + { "VMID", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_RIGHT_VERT_GRID[] = { + { "LEFT_QTR", 0, 7, &umr_bitfield_default }, + { "LEFT_HALF", 8, 15, &umr_bitfield_default }, + { "RIGHT_HALF", 16, 23, &umr_bitfield_default }, + { "RIGHT_QTR", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_LEFT_VERT_GRID[] = { + { "LEFT_QTR", 0, 7, &umr_bitfield_default }, + { "LEFT_HALF", 8, 15, &umr_bitfield_default }, + { "RIGHT_HALF", 16, 23, &umr_bitfield_default }, + { "RIGHT_QTR", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_HORIZ_GRID[] = { + { "TOP_QTR", 0, 7, &umr_bitfield_default }, + { "TOP_HALF", 8, 15, &umr_bitfield_default }, + { "BOT_HALF", 16, 23, &umr_bitfield_default }, + { "BOT_QTR", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_FOV_WINDOW_LR[] = { + { "LEFT_EYE_FOV_LEFT", 0, 7, &umr_bitfield_default }, + { "LEFT_EYE_FOV_RIGHT", 8, 15, &umr_bitfield_default }, + { "RIGHT_EYE_FOV_LEFT", 16, 23, &umr_bitfield_default }, + { "RIGHT_EYE_FOV_RIGHT", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_FOV_WINDOW_TB[] = { + { "FOV_TOP", 0, 7, &umr_bitfield_default }, + { "FOV_BOT", 8, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_MULTI_PRIM_IB_RESET_INDX[] = { + { "RESET_INDX", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_BLEND_RED[] = { + { "BLEND_RED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_BLEND_GREEN[] = { + { "BLEND_GREEN", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_BLEND_BLUE[] = { + { "BLEND_BLUE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_BLEND_ALPHA[] = { + { "BLEND_ALPHA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_DCC_CONTROL[] = { + { "OVERWRITE_COMBINER_DISABLE", 0, 0, &umr_bitfield_default }, + { "OVERWRITE_COMBINER_MRT_SHARING_DISABLE", 1, 1, &umr_bitfield_default }, + { "OVERWRITE_COMBINER_WATERMARK", 2, 6, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_STENCIL_CONTROL[] = { + { "STENCILFAIL", 0, 3, &umr_bitfield_default }, + { "STENCILZPASS", 4, 7, &umr_bitfield_default }, + { "STENCILZFAIL", 8, 11, &umr_bitfield_default }, + { "STENCILFAIL_BF", 12, 15, &umr_bitfield_default }, + { "STENCILZPASS_BF", 16, 19, &umr_bitfield_default }, + { "STENCILZFAIL_BF", 20, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_STENCILREFMASK[] = { + { "STENCILTESTVAL", 0, 7, &umr_bitfield_default }, + { "STENCILMASK", 8, 15, &umr_bitfield_default }, + { "STENCILWRITEMASK", 16, 23, &umr_bitfield_default }, + { "STENCILOPVAL", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_STENCILREFMASK_BF[] = { + { "STENCILTESTVAL_BF", 0, 7, &umr_bitfield_default }, + { "STENCILMASK_BF", 8, 15, &umr_bitfield_default }, + { "STENCILWRITEMASK_BF", 16, 23, &umr_bitfield_default }, + { "STENCILOPVAL_BF", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_XSCALE[] = { + { "VPORT_XSCALE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_XOFFSET[] = { + { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_YSCALE[] = { + { "VPORT_YSCALE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_YOFFSET[] = { + { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_ZSCALE[] = { + { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET[] = { + { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_XSCALE_1[] = { + { "VPORT_XSCALE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_1[] = { + { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_YSCALE_1[] = { + { "VPORT_YSCALE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_1[] = { + { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_1[] = { + { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_1[] = { + { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_XSCALE_2[] = { + { "VPORT_XSCALE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_2[] = { + { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_YSCALE_2[] = { + { "VPORT_YSCALE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_2[] = { + { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_2[] = { + { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_2[] = { + { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_XSCALE_3[] = { + { "VPORT_XSCALE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_3[] = { + { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_YSCALE_3[] = { + { "VPORT_YSCALE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_3[] = { + { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_3[] = { + { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_3[] = { + { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_XSCALE_4[] = { + { "VPORT_XSCALE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_4[] = { + { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_YSCALE_4[] = { + { "VPORT_YSCALE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_4[] = { + { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_4[] = { + { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_4[] = { + { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_XSCALE_5[] = { + { "VPORT_XSCALE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_5[] = { + { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_YSCALE_5[] = { + { "VPORT_YSCALE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_5[] = { + { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_5[] = { + { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_5[] = { + { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_XSCALE_6[] = { + { "VPORT_XSCALE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_6[] = { + { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_YSCALE_6[] = { + { "VPORT_YSCALE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_6[] = { + { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_6[] = { + { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_6[] = { + { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_XSCALE_7[] = { + { "VPORT_XSCALE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_7[] = { + { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_YSCALE_7[] = { + { "VPORT_YSCALE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_7[] = { + { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_7[] = { + { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_7[] = { + { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_XSCALE_8[] = { + { "VPORT_XSCALE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_8[] = { + { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_YSCALE_8[] = { + { "VPORT_YSCALE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_8[] = { + { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_8[] = { + { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_8[] = { + { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_XSCALE_9[] = { + { "VPORT_XSCALE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_9[] = { + { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_YSCALE_9[] = { + { "VPORT_YSCALE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_9[] = { + { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_9[] = { + { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_9[] = { + { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_XSCALE_10[] = { + { "VPORT_XSCALE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_10[] = { + { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_YSCALE_10[] = { + { "VPORT_YSCALE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_10[] = { + { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_10[] = { + { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_10[] = { + { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_XSCALE_11[] = { + { "VPORT_XSCALE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_11[] = { + { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_YSCALE_11[] = { + { "VPORT_YSCALE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_11[] = { + { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_11[] = { + { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_11[] = { + { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_XSCALE_12[] = { + { "VPORT_XSCALE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_12[] = { + { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_YSCALE_12[] = { + { "VPORT_YSCALE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_12[] = { + { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_12[] = { + { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_12[] = { + { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_XSCALE_13[] = { + { "VPORT_XSCALE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_13[] = { + { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_YSCALE_13[] = { + { "VPORT_YSCALE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_13[] = { + { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_13[] = { + { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_13[] = { + { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_XSCALE_14[] = { + { "VPORT_XSCALE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_14[] = { + { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_YSCALE_14[] = { + { "VPORT_YSCALE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_14[] = { + { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_14[] = { + { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_14[] = { + { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_XSCALE_15[] = { + { "VPORT_XSCALE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_15[] = { + { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_YSCALE_15[] = { + { "VPORT_YSCALE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_15[] = { + { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_15[] = { + { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_15[] = { + { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_UCP_0_X[] = { + { "DATA_REGISTER", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_UCP_0_Y[] = { + { "DATA_REGISTER", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_UCP_0_Z[] = { + { "DATA_REGISTER", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_UCP_0_W[] = { + { "DATA_REGISTER", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_UCP_1_X[] = { + { "DATA_REGISTER", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_UCP_1_Y[] = { + { "DATA_REGISTER", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_UCP_1_Z[] = { + { "DATA_REGISTER", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_UCP_1_W[] = { + { "DATA_REGISTER", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_UCP_2_X[] = { + { "DATA_REGISTER", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_UCP_2_Y[] = { + { "DATA_REGISTER", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_UCP_2_Z[] = { + { "DATA_REGISTER", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_UCP_2_W[] = { + { "DATA_REGISTER", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_UCP_3_X[] = { + { "DATA_REGISTER", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_UCP_3_Y[] = { + { "DATA_REGISTER", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_UCP_3_Z[] = { + { "DATA_REGISTER", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_UCP_3_W[] = { + { "DATA_REGISTER", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_UCP_4_X[] = { + { "DATA_REGISTER", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_UCP_4_Y[] = { + { "DATA_REGISTER", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_UCP_4_Z[] = { + { "DATA_REGISTER", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_UCP_4_W[] = { + { "DATA_REGISTER", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_UCP_5_X[] = { + { "DATA_REGISTER", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_UCP_5_Y[] = { + { "DATA_REGISTER", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_UCP_5_Z[] = { + { "DATA_REGISTER", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_UCP_5_W[] = { + { "DATA_REGISTER", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_PS_INPUT_CNTL_0[] = { + { "OFFSET", 0, 5, &umr_bitfield_default }, + { "DEFAULT_VAL", 8, 9, &umr_bitfield_default }, + { "FLAT_SHADE", 10, 10, &umr_bitfield_default }, + { "CYL_WRAP", 13, 16, &umr_bitfield_default }, + { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default }, + { "DUP", 18, 18, &umr_bitfield_default }, + { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default }, + { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default }, + { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default }, + { "PT_SPRITE_TEX_ATTR1", 23, 23, &umr_bitfield_default }, + { "ATTR0_VALID", 24, 24, &umr_bitfield_default }, + { "ATTR1_VALID", 25, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_PS_INPUT_CNTL_1[] = { + { "OFFSET", 0, 5, &umr_bitfield_default }, + { "DEFAULT_VAL", 8, 9, &umr_bitfield_default }, + { "FLAT_SHADE", 10, 10, &umr_bitfield_default }, + { "CYL_WRAP", 13, 16, &umr_bitfield_default }, + { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default }, + { "DUP", 18, 18, &umr_bitfield_default }, + { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default }, + { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default }, + { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default }, + { "PT_SPRITE_TEX_ATTR1", 23, 23, &umr_bitfield_default }, + { "ATTR0_VALID", 24, 24, &umr_bitfield_default }, + { "ATTR1_VALID", 25, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_PS_INPUT_CNTL_2[] = { + { "OFFSET", 0, 5, &umr_bitfield_default }, + { "DEFAULT_VAL", 8, 9, &umr_bitfield_default }, + { "FLAT_SHADE", 10, 10, &umr_bitfield_default }, + { "CYL_WRAP", 13, 16, &umr_bitfield_default }, + { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default }, + { "DUP", 18, 18, &umr_bitfield_default }, + { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default }, + { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default }, + { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default }, + { "PT_SPRITE_TEX_ATTR1", 23, 23, &umr_bitfield_default }, + { "ATTR0_VALID", 24, 24, &umr_bitfield_default }, + { "ATTR1_VALID", 25, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_PS_INPUT_CNTL_3[] = { + { "OFFSET", 0, 5, &umr_bitfield_default }, + { "DEFAULT_VAL", 8, 9, &umr_bitfield_default }, + { "FLAT_SHADE", 10, 10, &umr_bitfield_default }, + { "CYL_WRAP", 13, 16, &umr_bitfield_default }, + { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default }, + { "DUP", 18, 18, &umr_bitfield_default }, + { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default }, + { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default }, + { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default }, + { "PT_SPRITE_TEX_ATTR1", 23, 23, &umr_bitfield_default }, + { "ATTR0_VALID", 24, 24, &umr_bitfield_default }, + { "ATTR1_VALID", 25, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_PS_INPUT_CNTL_4[] = { + { "OFFSET", 0, 5, &umr_bitfield_default }, + { "DEFAULT_VAL", 8, 9, &umr_bitfield_default }, + { "FLAT_SHADE", 10, 10, &umr_bitfield_default }, + { "CYL_WRAP", 13, 16, &umr_bitfield_default }, + { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default }, + { "DUP", 18, 18, &umr_bitfield_default }, + { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default }, + { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default }, + { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default }, + { "PT_SPRITE_TEX_ATTR1", 23, 23, &umr_bitfield_default }, + { "ATTR0_VALID", 24, 24, &umr_bitfield_default }, + { "ATTR1_VALID", 25, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_PS_INPUT_CNTL_5[] = { + { "OFFSET", 0, 5, &umr_bitfield_default }, + { "DEFAULT_VAL", 8, 9, &umr_bitfield_default }, + { "FLAT_SHADE", 10, 10, &umr_bitfield_default }, + { "CYL_WRAP", 13, 16, &umr_bitfield_default }, + { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default }, + { "DUP", 18, 18, &umr_bitfield_default }, + { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default }, + { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default }, + { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default }, + { "PT_SPRITE_TEX_ATTR1", 23, 23, &umr_bitfield_default }, + { "ATTR0_VALID", 24, 24, &umr_bitfield_default }, + { "ATTR1_VALID", 25, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_PS_INPUT_CNTL_6[] = { + { "OFFSET", 0, 5, &umr_bitfield_default }, + { "DEFAULT_VAL", 8, 9, &umr_bitfield_default }, + { "FLAT_SHADE", 10, 10, &umr_bitfield_default }, + { "CYL_WRAP", 13, 16, &umr_bitfield_default }, + { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default }, + { "DUP", 18, 18, &umr_bitfield_default }, + { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default }, + { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default }, + { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default }, + { "PT_SPRITE_TEX_ATTR1", 23, 23, &umr_bitfield_default }, + { "ATTR0_VALID", 24, 24, &umr_bitfield_default }, + { "ATTR1_VALID", 25, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_PS_INPUT_CNTL_7[] = { + { "OFFSET", 0, 5, &umr_bitfield_default }, + { "DEFAULT_VAL", 8, 9, &umr_bitfield_default }, + { "FLAT_SHADE", 10, 10, &umr_bitfield_default }, + { "CYL_WRAP", 13, 16, &umr_bitfield_default }, + { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default }, + { "DUP", 18, 18, &umr_bitfield_default }, + { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default }, + { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default }, + { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default }, + { "PT_SPRITE_TEX_ATTR1", 23, 23, &umr_bitfield_default }, + { "ATTR0_VALID", 24, 24, &umr_bitfield_default }, + { "ATTR1_VALID", 25, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_PS_INPUT_CNTL_8[] = { + { "OFFSET", 0, 5, &umr_bitfield_default }, + { "DEFAULT_VAL", 8, 9, &umr_bitfield_default }, + { "FLAT_SHADE", 10, 10, &umr_bitfield_default }, + { "CYL_WRAP", 13, 16, &umr_bitfield_default }, + { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default }, + { "DUP", 18, 18, &umr_bitfield_default }, + { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default }, + { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default }, + { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default }, + { "PT_SPRITE_TEX_ATTR1", 23, 23, &umr_bitfield_default }, + { "ATTR0_VALID", 24, 24, &umr_bitfield_default }, + { "ATTR1_VALID", 25, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_PS_INPUT_CNTL_9[] = { + { "OFFSET", 0, 5, &umr_bitfield_default }, + { "DEFAULT_VAL", 8, 9, &umr_bitfield_default }, + { "FLAT_SHADE", 10, 10, &umr_bitfield_default }, + { "CYL_WRAP", 13, 16, &umr_bitfield_default }, + { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default }, + { "DUP", 18, 18, &umr_bitfield_default }, + { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default }, + { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default }, + { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default }, + { "PT_SPRITE_TEX_ATTR1", 23, 23, &umr_bitfield_default }, + { "ATTR0_VALID", 24, 24, &umr_bitfield_default }, + { "ATTR1_VALID", 25, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_PS_INPUT_CNTL_10[] = { + { "OFFSET", 0, 5, &umr_bitfield_default }, + { "DEFAULT_VAL", 8, 9, &umr_bitfield_default }, + { "FLAT_SHADE", 10, 10, &umr_bitfield_default }, + { "CYL_WRAP", 13, 16, &umr_bitfield_default }, + { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default }, + { "DUP", 18, 18, &umr_bitfield_default }, + { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default }, + { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default }, + { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default }, + { "PT_SPRITE_TEX_ATTR1", 23, 23, &umr_bitfield_default }, + { "ATTR0_VALID", 24, 24, &umr_bitfield_default }, + { "ATTR1_VALID", 25, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_PS_INPUT_CNTL_11[] = { + { "OFFSET", 0, 5, &umr_bitfield_default }, + { "DEFAULT_VAL", 8, 9, &umr_bitfield_default }, + { "FLAT_SHADE", 10, 10, &umr_bitfield_default }, + { "CYL_WRAP", 13, 16, &umr_bitfield_default }, + { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default }, + { "DUP", 18, 18, &umr_bitfield_default }, + { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default }, + { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default }, + { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default }, + { "PT_SPRITE_TEX_ATTR1", 23, 23, &umr_bitfield_default }, + { "ATTR0_VALID", 24, 24, &umr_bitfield_default }, + { "ATTR1_VALID", 25, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_PS_INPUT_CNTL_12[] = { + { "OFFSET", 0, 5, &umr_bitfield_default }, + { "DEFAULT_VAL", 8, 9, &umr_bitfield_default }, + { "FLAT_SHADE", 10, 10, &umr_bitfield_default }, + { "CYL_WRAP", 13, 16, &umr_bitfield_default }, + { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default }, + { "DUP", 18, 18, &umr_bitfield_default }, + { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default }, + { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default }, + { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default }, + { "PT_SPRITE_TEX_ATTR1", 23, 23, &umr_bitfield_default }, + { "ATTR0_VALID", 24, 24, &umr_bitfield_default }, + { "ATTR1_VALID", 25, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_PS_INPUT_CNTL_13[] = { + { "OFFSET", 0, 5, &umr_bitfield_default }, + { "DEFAULT_VAL", 8, 9, &umr_bitfield_default }, + { "FLAT_SHADE", 10, 10, &umr_bitfield_default }, + { "CYL_WRAP", 13, 16, &umr_bitfield_default }, + { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default }, + { "DUP", 18, 18, &umr_bitfield_default }, + { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default }, + { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default }, + { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default }, + { "PT_SPRITE_TEX_ATTR1", 23, 23, &umr_bitfield_default }, + { "ATTR0_VALID", 24, 24, &umr_bitfield_default }, + { "ATTR1_VALID", 25, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_PS_INPUT_CNTL_14[] = { + { "OFFSET", 0, 5, &umr_bitfield_default }, + { "DEFAULT_VAL", 8, 9, &umr_bitfield_default }, + { "FLAT_SHADE", 10, 10, &umr_bitfield_default }, + { "CYL_WRAP", 13, 16, &umr_bitfield_default }, + { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default }, + { "DUP", 18, 18, &umr_bitfield_default }, + { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default }, + { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default }, + { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default }, + { "PT_SPRITE_TEX_ATTR1", 23, 23, &umr_bitfield_default }, + { "ATTR0_VALID", 24, 24, &umr_bitfield_default }, + { "ATTR1_VALID", 25, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_PS_INPUT_CNTL_15[] = { + { "OFFSET", 0, 5, &umr_bitfield_default }, + { "DEFAULT_VAL", 8, 9, &umr_bitfield_default }, + { "FLAT_SHADE", 10, 10, &umr_bitfield_default }, + { "CYL_WRAP", 13, 16, &umr_bitfield_default }, + { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default }, + { "DUP", 18, 18, &umr_bitfield_default }, + { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default }, + { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default }, + { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default }, + { "PT_SPRITE_TEX_ATTR1", 23, 23, &umr_bitfield_default }, + { "ATTR0_VALID", 24, 24, &umr_bitfield_default }, + { "ATTR1_VALID", 25, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_PS_INPUT_CNTL_16[] = { + { "OFFSET", 0, 5, &umr_bitfield_default }, + { "DEFAULT_VAL", 8, 9, &umr_bitfield_default }, + { "FLAT_SHADE", 10, 10, &umr_bitfield_default }, + { "CYL_WRAP", 13, 16, &umr_bitfield_default }, + { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default }, + { "DUP", 18, 18, &umr_bitfield_default }, + { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default }, + { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default }, + { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default }, + { "PT_SPRITE_TEX_ATTR1", 23, 23, &umr_bitfield_default }, + { "ATTR0_VALID", 24, 24, &umr_bitfield_default }, + { "ATTR1_VALID", 25, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_PS_INPUT_CNTL_17[] = { + { "OFFSET", 0, 5, &umr_bitfield_default }, + { "DEFAULT_VAL", 8, 9, &umr_bitfield_default }, + { "FLAT_SHADE", 10, 10, &umr_bitfield_default }, + { "CYL_WRAP", 13, 16, &umr_bitfield_default }, + { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default }, + { "DUP", 18, 18, &umr_bitfield_default }, + { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default }, + { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default }, + { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default }, + { "PT_SPRITE_TEX_ATTR1", 23, 23, &umr_bitfield_default }, + { "ATTR0_VALID", 24, 24, &umr_bitfield_default }, + { "ATTR1_VALID", 25, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_PS_INPUT_CNTL_18[] = { + { "OFFSET", 0, 5, &umr_bitfield_default }, + { "DEFAULT_VAL", 8, 9, &umr_bitfield_default }, + { "FLAT_SHADE", 10, 10, &umr_bitfield_default }, + { "CYL_WRAP", 13, 16, &umr_bitfield_default }, + { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default }, + { "DUP", 18, 18, &umr_bitfield_default }, + { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default }, + { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default }, + { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default }, + { "PT_SPRITE_TEX_ATTR1", 23, 23, &umr_bitfield_default }, + { "ATTR0_VALID", 24, 24, &umr_bitfield_default }, + { "ATTR1_VALID", 25, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_PS_INPUT_CNTL_19[] = { + { "OFFSET", 0, 5, &umr_bitfield_default }, + { "DEFAULT_VAL", 8, 9, &umr_bitfield_default }, + { "FLAT_SHADE", 10, 10, &umr_bitfield_default }, + { "CYL_WRAP", 13, 16, &umr_bitfield_default }, + { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default }, + { "DUP", 18, 18, &umr_bitfield_default }, + { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default }, + { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default }, + { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default }, + { "PT_SPRITE_TEX_ATTR1", 23, 23, &umr_bitfield_default }, + { "ATTR0_VALID", 24, 24, &umr_bitfield_default }, + { "ATTR1_VALID", 25, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_PS_INPUT_CNTL_20[] = { + { "OFFSET", 0, 5, &umr_bitfield_default }, + { "DEFAULT_VAL", 8, 9, &umr_bitfield_default }, + { "FLAT_SHADE", 10, 10, &umr_bitfield_default }, + { "DUP", 18, 18, &umr_bitfield_default }, + { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default }, + { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default }, + { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default }, + { "ATTR0_VALID", 24, 24, &umr_bitfield_default }, + { "ATTR1_VALID", 25, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_PS_INPUT_CNTL_21[] = { + { "OFFSET", 0, 5, &umr_bitfield_default }, + { "DEFAULT_VAL", 8, 9, &umr_bitfield_default }, + { "FLAT_SHADE", 10, 10, &umr_bitfield_default }, + { "DUP", 18, 18, &umr_bitfield_default }, + { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default }, + { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default }, + { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default }, + { "ATTR0_VALID", 24, 24, &umr_bitfield_default }, + { "ATTR1_VALID", 25, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_PS_INPUT_CNTL_22[] = { + { "OFFSET", 0, 5, &umr_bitfield_default }, + { "DEFAULT_VAL", 8, 9, &umr_bitfield_default }, + { "FLAT_SHADE", 10, 10, &umr_bitfield_default }, + { "DUP", 18, 18, &umr_bitfield_default }, + { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default }, + { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default }, + { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default }, + { "ATTR0_VALID", 24, 24, &umr_bitfield_default }, + { "ATTR1_VALID", 25, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_PS_INPUT_CNTL_23[] = { + { "OFFSET", 0, 5, &umr_bitfield_default }, + { "DEFAULT_VAL", 8, 9, &umr_bitfield_default }, + { "FLAT_SHADE", 10, 10, &umr_bitfield_default }, + { "DUP", 18, 18, &umr_bitfield_default }, + { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default }, + { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default }, + { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default }, + { "ATTR0_VALID", 24, 24, &umr_bitfield_default }, + { "ATTR1_VALID", 25, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_PS_INPUT_CNTL_24[] = { + { "OFFSET", 0, 5, &umr_bitfield_default }, + { "DEFAULT_VAL", 8, 9, &umr_bitfield_default }, + { "FLAT_SHADE", 10, 10, &umr_bitfield_default }, + { "DUP", 18, 18, &umr_bitfield_default }, + { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default }, + { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default }, + { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default }, + { "ATTR0_VALID", 24, 24, &umr_bitfield_default }, + { "ATTR1_VALID", 25, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_PS_INPUT_CNTL_25[] = { + { "OFFSET", 0, 5, &umr_bitfield_default }, + { "DEFAULT_VAL", 8, 9, &umr_bitfield_default }, + { "FLAT_SHADE", 10, 10, &umr_bitfield_default }, + { "DUP", 18, 18, &umr_bitfield_default }, + { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default }, + { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default }, + { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default }, + { "ATTR0_VALID", 24, 24, &umr_bitfield_default }, + { "ATTR1_VALID", 25, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_PS_INPUT_CNTL_26[] = { + { "OFFSET", 0, 5, &umr_bitfield_default }, + { "DEFAULT_VAL", 8, 9, &umr_bitfield_default }, + { "FLAT_SHADE", 10, 10, &umr_bitfield_default }, + { "DUP", 18, 18, &umr_bitfield_default }, + { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default }, + { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default }, + { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default }, + { "ATTR0_VALID", 24, 24, &umr_bitfield_default }, + { "ATTR1_VALID", 25, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_PS_INPUT_CNTL_27[] = { + { "OFFSET", 0, 5, &umr_bitfield_default }, + { "DEFAULT_VAL", 8, 9, &umr_bitfield_default }, + { "FLAT_SHADE", 10, 10, &umr_bitfield_default }, + { "DUP", 18, 18, &umr_bitfield_default }, + { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default }, + { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default }, + { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default }, + { "ATTR0_VALID", 24, 24, &umr_bitfield_default }, + { "ATTR1_VALID", 25, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_PS_INPUT_CNTL_28[] = { + { "OFFSET", 0, 5, &umr_bitfield_default }, + { "DEFAULT_VAL", 8, 9, &umr_bitfield_default }, + { "FLAT_SHADE", 10, 10, &umr_bitfield_default }, + { "DUP", 18, 18, &umr_bitfield_default }, + { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default }, + { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default }, + { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default }, + { "ATTR0_VALID", 24, 24, &umr_bitfield_default }, + { "ATTR1_VALID", 25, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_PS_INPUT_CNTL_29[] = { + { "OFFSET", 0, 5, &umr_bitfield_default }, + { "DEFAULT_VAL", 8, 9, &umr_bitfield_default }, + { "FLAT_SHADE", 10, 10, &umr_bitfield_default }, + { "DUP", 18, 18, &umr_bitfield_default }, + { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default }, + { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default }, + { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default }, + { "ATTR0_VALID", 24, 24, &umr_bitfield_default }, + { "ATTR1_VALID", 25, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_PS_INPUT_CNTL_30[] = { + { "OFFSET", 0, 5, &umr_bitfield_default }, + { "DEFAULT_VAL", 8, 9, &umr_bitfield_default }, + { "FLAT_SHADE", 10, 10, &umr_bitfield_default }, + { "DUP", 18, 18, &umr_bitfield_default }, + { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default }, + { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default }, + { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default }, + { "ATTR0_VALID", 24, 24, &umr_bitfield_default }, + { "ATTR1_VALID", 25, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_PS_INPUT_CNTL_31[] = { + { "OFFSET", 0, 5, &umr_bitfield_default }, + { "DEFAULT_VAL", 8, 9, &umr_bitfield_default }, + { "FLAT_SHADE", 10, 10, &umr_bitfield_default }, + { "DUP", 18, 18, &umr_bitfield_default }, + { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default }, + { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default }, + { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default }, + { "ATTR0_VALID", 24, 24, &umr_bitfield_default }, + { "ATTR1_VALID", 25, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_VS_OUT_CONFIG[] = { + { "VS_EXPORT_COUNT", 1, 5, &umr_bitfield_default }, + { "VS_HALF_PACK", 6, 6, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_PS_INPUT_ENA[] = { + { "PERSP_SAMPLE_ENA", 0, 0, &umr_bitfield_default }, + { "PERSP_CENTER_ENA", 1, 1, &umr_bitfield_default }, + { "PERSP_CENTROID_ENA", 2, 2, &umr_bitfield_default }, + { "PERSP_PULL_MODEL_ENA", 3, 3, &umr_bitfield_default }, + { "LINEAR_SAMPLE_ENA", 4, 4, &umr_bitfield_default }, + { "LINEAR_CENTER_ENA", 5, 5, &umr_bitfield_default }, + { "LINEAR_CENTROID_ENA", 6, 6, &umr_bitfield_default }, + { "LINE_STIPPLE_TEX_ENA", 7, 7, &umr_bitfield_default }, + { "POS_X_FLOAT_ENA", 8, 8, &umr_bitfield_default }, + { "POS_Y_FLOAT_ENA", 9, 9, &umr_bitfield_default }, + { "POS_Z_FLOAT_ENA", 10, 10, &umr_bitfield_default }, + { "POS_W_FLOAT_ENA", 11, 11, &umr_bitfield_default }, + { "FRONT_FACE_ENA", 12, 12, &umr_bitfield_default }, + { "ANCILLARY_ENA", 13, 13, &umr_bitfield_default }, + { "SAMPLE_COVERAGE_ENA", 14, 14, &umr_bitfield_default }, + { "POS_FIXED_PT_ENA", 15, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_PS_INPUT_ADDR[] = { + { "PERSP_SAMPLE_ENA", 0, 0, &umr_bitfield_default }, + { "PERSP_CENTER_ENA", 1, 1, &umr_bitfield_default }, + { "PERSP_CENTROID_ENA", 2, 2, &umr_bitfield_default }, + { "PERSP_PULL_MODEL_ENA", 3, 3, &umr_bitfield_default }, + { "LINEAR_SAMPLE_ENA", 4, 4, &umr_bitfield_default }, + { "LINEAR_CENTER_ENA", 5, 5, &umr_bitfield_default }, + { "LINEAR_CENTROID_ENA", 6, 6, &umr_bitfield_default }, + { "LINE_STIPPLE_TEX_ENA", 7, 7, &umr_bitfield_default }, + { "POS_X_FLOAT_ENA", 8, 8, &umr_bitfield_default }, + { "POS_Y_FLOAT_ENA", 9, 9, &umr_bitfield_default }, + { "POS_Z_FLOAT_ENA", 10, 10, &umr_bitfield_default }, + { "POS_W_FLOAT_ENA", 11, 11, &umr_bitfield_default }, + { "FRONT_FACE_ENA", 12, 12, &umr_bitfield_default }, + { "ANCILLARY_ENA", 13, 13, &umr_bitfield_default }, + { "SAMPLE_COVERAGE_ENA", 14, 14, &umr_bitfield_default }, + { "POS_FIXED_PT_ENA", 15, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_INTERP_CONTROL_0[] = { + { "FLAT_SHADE_ENA", 0, 0, &umr_bitfield_default }, + { "PNT_SPRITE_ENA", 1, 1, &umr_bitfield_default }, + { "PNT_SPRITE_OVRD_X", 2, 4, &umr_bitfield_default }, + { "PNT_SPRITE_OVRD_Y", 5, 7, &umr_bitfield_default }, + { "PNT_SPRITE_OVRD_Z", 8, 10, &umr_bitfield_default }, + { "PNT_SPRITE_OVRD_W", 11, 13, &umr_bitfield_default }, + { "PNT_SPRITE_TOP_1", 14, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_PS_IN_CONTROL[] = { + { "NUM_INTERP", 0, 5, &umr_bitfield_default }, + { "PARAM_GEN", 6, 6, &umr_bitfield_default }, + { "OFFCHIP_PARAM_EN", 7, 7, &umr_bitfield_default }, + { "LATE_PC_DEALLOC", 8, 8, &umr_bitfield_default }, + { "BC_OPTIMIZE_DISABLE", 14, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_BARYC_CNTL[] = { + { "PERSP_CENTER_CNTL", 0, 0, &umr_bitfield_default }, + { "PERSP_CENTROID_CNTL", 4, 4, &umr_bitfield_default }, + { "LINEAR_CENTER_CNTL", 8, 8, &umr_bitfield_default }, + { "LINEAR_CENTROID_CNTL", 12, 12, &umr_bitfield_default }, + { "POS_FLOAT_LOCATION", 16, 17, &umr_bitfield_default }, + { "POS_FLOAT_ULC", 20, 20, &umr_bitfield_default }, + { "FRONT_FACE_ALL_BITS", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_TMPRING_SIZE[] = { + { "WAVES", 0, 11, &umr_bitfield_default }, + { "WAVESIZE", 12, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_POS_FORMAT[] = { + { "POS0_EXPORT_FORMAT", 0, 3, &umr_bitfield_default }, + { "POS1_EXPORT_FORMAT", 4, 7, &umr_bitfield_default }, + { "POS2_EXPORT_FORMAT", 8, 11, &umr_bitfield_default }, + { "POS3_EXPORT_FORMAT", 12, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_Z_FORMAT[] = { + { "Z_EXPORT_FORMAT", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_SHADER_COL_FORMAT[] = { + { "COL0_EXPORT_FORMAT", 0, 3, &umr_bitfield_default }, + { "COL1_EXPORT_FORMAT", 4, 7, &umr_bitfield_default }, + { "COL2_EXPORT_FORMAT", 8, 11, &umr_bitfield_default }, + { "COL3_EXPORT_FORMAT", 12, 15, &umr_bitfield_default }, + { "COL4_EXPORT_FORMAT", 16, 19, &umr_bitfield_default }, + { "COL5_EXPORT_FORMAT", 20, 23, &umr_bitfield_default }, + { "COL6_EXPORT_FORMAT", 24, 27, &umr_bitfield_default }, + { "COL7_EXPORT_FORMAT", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSX_PS_DOWNCONVERT[] = { + { "MRT0", 0, 3, &umr_bitfield_default }, + { "MRT1", 4, 7, &umr_bitfield_default }, + { "MRT2", 8, 11, &umr_bitfield_default }, + { "MRT3", 12, 15, &umr_bitfield_default }, + { "MRT4", 16, 19, &umr_bitfield_default }, + { "MRT5", 20, 23, &umr_bitfield_default }, + { "MRT6", 24, 27, &umr_bitfield_default }, + { "MRT7", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSX_BLEND_OPT_EPSILON[] = { + { "MRT0_EPSILON", 0, 3, &umr_bitfield_default }, + { "MRT1_EPSILON", 4, 7, &umr_bitfield_default }, + { "MRT2_EPSILON", 8, 11, &umr_bitfield_default }, + { "MRT3_EPSILON", 12, 15, &umr_bitfield_default }, + { "MRT4_EPSILON", 16, 19, &umr_bitfield_default }, + { "MRT5_EPSILON", 20, 23, &umr_bitfield_default }, + { "MRT6_EPSILON", 24, 27, &umr_bitfield_default }, + { "MRT7_EPSILON", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSX_BLEND_OPT_CONTROL[] = { + { "MRT0_COLOR_OPT_DISABLE", 0, 0, &umr_bitfield_default }, + { "MRT0_ALPHA_OPT_DISABLE", 1, 1, &umr_bitfield_default }, + { "MRT1_COLOR_OPT_DISABLE", 4, 4, &umr_bitfield_default }, + { "MRT1_ALPHA_OPT_DISABLE", 5, 5, &umr_bitfield_default }, + { "MRT2_COLOR_OPT_DISABLE", 8, 8, &umr_bitfield_default }, + { "MRT2_ALPHA_OPT_DISABLE", 9, 9, &umr_bitfield_default }, + { "MRT3_COLOR_OPT_DISABLE", 12, 12, &umr_bitfield_default }, + { "MRT3_ALPHA_OPT_DISABLE", 13, 13, &umr_bitfield_default }, + { "MRT4_COLOR_OPT_DISABLE", 16, 16, &umr_bitfield_default }, + { "MRT4_ALPHA_OPT_DISABLE", 17, 17, &umr_bitfield_default }, + { "MRT5_COLOR_OPT_DISABLE", 20, 20, &umr_bitfield_default }, + { "MRT5_ALPHA_OPT_DISABLE", 21, 21, &umr_bitfield_default }, + { "MRT6_COLOR_OPT_DISABLE", 24, 24, &umr_bitfield_default }, + { "MRT6_ALPHA_OPT_DISABLE", 25, 25, &umr_bitfield_default }, + { "MRT7_COLOR_OPT_DISABLE", 28, 28, &umr_bitfield_default }, + { "MRT7_ALPHA_OPT_DISABLE", 29, 29, &umr_bitfield_default }, + { "PIXEN_ZERO_OPT_DISABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSX_MRT0_BLEND_OPT[] = { + { "COLOR_SRC_OPT", 0, 2, &umr_bitfield_default }, + { "COLOR_DST_OPT", 4, 6, &umr_bitfield_default }, + { "COLOR_COMB_FCN", 8, 10, &umr_bitfield_default }, + { "ALPHA_SRC_OPT", 16, 18, &umr_bitfield_default }, + { "ALPHA_DST_OPT", 20, 22, &umr_bitfield_default }, + { "ALPHA_COMB_FCN", 24, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSX_MRT1_BLEND_OPT[] = { + { "COLOR_SRC_OPT", 0, 2, &umr_bitfield_default }, + { "COLOR_DST_OPT", 4, 6, &umr_bitfield_default }, + { "COLOR_COMB_FCN", 8, 10, &umr_bitfield_default }, + { "ALPHA_SRC_OPT", 16, 18, &umr_bitfield_default }, + { "ALPHA_DST_OPT", 20, 22, &umr_bitfield_default }, + { "ALPHA_COMB_FCN", 24, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSX_MRT2_BLEND_OPT[] = { + { "COLOR_SRC_OPT", 0, 2, &umr_bitfield_default }, + { "COLOR_DST_OPT", 4, 6, &umr_bitfield_default }, + { "COLOR_COMB_FCN", 8, 10, &umr_bitfield_default }, + { "ALPHA_SRC_OPT", 16, 18, &umr_bitfield_default }, + { "ALPHA_DST_OPT", 20, 22, &umr_bitfield_default }, + { "ALPHA_COMB_FCN", 24, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSX_MRT3_BLEND_OPT[] = { + { "COLOR_SRC_OPT", 0, 2, &umr_bitfield_default }, + { "COLOR_DST_OPT", 4, 6, &umr_bitfield_default }, + { "COLOR_COMB_FCN", 8, 10, &umr_bitfield_default }, + { "ALPHA_SRC_OPT", 16, 18, &umr_bitfield_default }, + { "ALPHA_DST_OPT", 20, 22, &umr_bitfield_default }, + { "ALPHA_COMB_FCN", 24, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSX_MRT4_BLEND_OPT[] = { + { "COLOR_SRC_OPT", 0, 2, &umr_bitfield_default }, + { "COLOR_DST_OPT", 4, 6, &umr_bitfield_default }, + { "COLOR_COMB_FCN", 8, 10, &umr_bitfield_default }, + { "ALPHA_SRC_OPT", 16, 18, &umr_bitfield_default }, + { "ALPHA_DST_OPT", 20, 22, &umr_bitfield_default }, + { "ALPHA_COMB_FCN", 24, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSX_MRT5_BLEND_OPT[] = { + { "COLOR_SRC_OPT", 0, 2, &umr_bitfield_default }, + { "COLOR_DST_OPT", 4, 6, &umr_bitfield_default }, + { "COLOR_COMB_FCN", 8, 10, &umr_bitfield_default }, + { "ALPHA_SRC_OPT", 16, 18, &umr_bitfield_default }, + { "ALPHA_DST_OPT", 20, 22, &umr_bitfield_default }, + { "ALPHA_COMB_FCN", 24, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSX_MRT6_BLEND_OPT[] = { + { "COLOR_SRC_OPT", 0, 2, &umr_bitfield_default }, + { "COLOR_DST_OPT", 4, 6, &umr_bitfield_default }, + { "COLOR_COMB_FCN", 8, 10, &umr_bitfield_default }, + { "ALPHA_SRC_OPT", 16, 18, &umr_bitfield_default }, + { "ALPHA_DST_OPT", 20, 22, &umr_bitfield_default }, + { "ALPHA_COMB_FCN", 24, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSX_MRT7_BLEND_OPT[] = { + { "COLOR_SRC_OPT", 0, 2, &umr_bitfield_default }, + { "COLOR_DST_OPT", 4, 6, &umr_bitfield_default }, + { "COLOR_COMB_FCN", 8, 10, &umr_bitfield_default }, + { "ALPHA_SRC_OPT", 16, 18, &umr_bitfield_default }, + { "ALPHA_DST_OPT", 20, 22, &umr_bitfield_default }, + { "ALPHA_COMB_FCN", 24, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_BLEND0_CONTROL[] = { + { "COLOR_SRCBLEND", 0, 4, &umr_bitfield_default }, + { "COLOR_COMB_FCN", 5, 7, &umr_bitfield_default }, + { "COLOR_DESTBLEND", 8, 12, &umr_bitfield_default }, + { "ALPHA_SRCBLEND", 16, 20, &umr_bitfield_default }, + { "ALPHA_COMB_FCN", 21, 23, &umr_bitfield_default }, + { "ALPHA_DESTBLEND", 24, 28, &umr_bitfield_default }, + { "SEPARATE_ALPHA_BLEND", 29, 29, &umr_bitfield_default }, + { "ENABLE", 30, 30, &umr_bitfield_default }, + { "DISABLE_ROP3", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_BLEND1_CONTROL[] = { + { "COLOR_SRCBLEND", 0, 4, &umr_bitfield_default }, + { "COLOR_COMB_FCN", 5, 7, &umr_bitfield_default }, + { "COLOR_DESTBLEND", 8, 12, &umr_bitfield_default }, + { "ALPHA_SRCBLEND", 16, 20, &umr_bitfield_default }, + { "ALPHA_COMB_FCN", 21, 23, &umr_bitfield_default }, + { "ALPHA_DESTBLEND", 24, 28, &umr_bitfield_default }, + { "SEPARATE_ALPHA_BLEND", 29, 29, &umr_bitfield_default }, + { "ENABLE", 30, 30, &umr_bitfield_default }, + { "DISABLE_ROP3", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_BLEND2_CONTROL[] = { + { "COLOR_SRCBLEND", 0, 4, &umr_bitfield_default }, + { "COLOR_COMB_FCN", 5, 7, &umr_bitfield_default }, + { "COLOR_DESTBLEND", 8, 12, &umr_bitfield_default }, + { "ALPHA_SRCBLEND", 16, 20, &umr_bitfield_default }, + { "ALPHA_COMB_FCN", 21, 23, &umr_bitfield_default }, + { "ALPHA_DESTBLEND", 24, 28, &umr_bitfield_default }, + { "SEPARATE_ALPHA_BLEND", 29, 29, &umr_bitfield_default }, + { "ENABLE", 30, 30, &umr_bitfield_default }, + { "DISABLE_ROP3", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_BLEND3_CONTROL[] = { + { "COLOR_SRCBLEND", 0, 4, &umr_bitfield_default }, + { "COLOR_COMB_FCN", 5, 7, &umr_bitfield_default }, + { "COLOR_DESTBLEND", 8, 12, &umr_bitfield_default }, + { "ALPHA_SRCBLEND", 16, 20, &umr_bitfield_default }, + { "ALPHA_COMB_FCN", 21, 23, &umr_bitfield_default }, + { "ALPHA_DESTBLEND", 24, 28, &umr_bitfield_default }, + { "SEPARATE_ALPHA_BLEND", 29, 29, &umr_bitfield_default }, + { "ENABLE", 30, 30, &umr_bitfield_default }, + { "DISABLE_ROP3", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_BLEND4_CONTROL[] = { + { "COLOR_SRCBLEND", 0, 4, &umr_bitfield_default }, + { "COLOR_COMB_FCN", 5, 7, &umr_bitfield_default }, + { "COLOR_DESTBLEND", 8, 12, &umr_bitfield_default }, + { "ALPHA_SRCBLEND", 16, 20, &umr_bitfield_default }, + { "ALPHA_COMB_FCN", 21, 23, &umr_bitfield_default }, + { "ALPHA_DESTBLEND", 24, 28, &umr_bitfield_default }, + { "SEPARATE_ALPHA_BLEND", 29, 29, &umr_bitfield_default }, + { "ENABLE", 30, 30, &umr_bitfield_default }, + { "DISABLE_ROP3", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_BLEND5_CONTROL[] = { + { "COLOR_SRCBLEND", 0, 4, &umr_bitfield_default }, + { "COLOR_COMB_FCN", 5, 7, &umr_bitfield_default }, + { "COLOR_DESTBLEND", 8, 12, &umr_bitfield_default }, + { "ALPHA_SRCBLEND", 16, 20, &umr_bitfield_default }, + { "ALPHA_COMB_FCN", 21, 23, &umr_bitfield_default }, + { "ALPHA_DESTBLEND", 24, 28, &umr_bitfield_default }, + { "SEPARATE_ALPHA_BLEND", 29, 29, &umr_bitfield_default }, + { "ENABLE", 30, 30, &umr_bitfield_default }, + { "DISABLE_ROP3", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_BLEND6_CONTROL[] = { + { "COLOR_SRCBLEND", 0, 4, &umr_bitfield_default }, + { "COLOR_COMB_FCN", 5, 7, &umr_bitfield_default }, + { "COLOR_DESTBLEND", 8, 12, &umr_bitfield_default }, + { "ALPHA_SRCBLEND", 16, 20, &umr_bitfield_default }, + { "ALPHA_COMB_FCN", 21, 23, &umr_bitfield_default }, + { "ALPHA_DESTBLEND", 24, 28, &umr_bitfield_default }, + { "SEPARATE_ALPHA_BLEND", 29, 29, &umr_bitfield_default }, + { "ENABLE", 30, 30, &umr_bitfield_default }, + { "DISABLE_ROP3", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_BLEND7_CONTROL[] = { + { "COLOR_SRCBLEND", 0, 4, &umr_bitfield_default }, + { "COLOR_COMB_FCN", 5, 7, &umr_bitfield_default }, + { "COLOR_DESTBLEND", 8, 12, &umr_bitfield_default }, + { "ALPHA_SRCBLEND", 16, 20, &umr_bitfield_default }, + { "ALPHA_COMB_FCN", 21, 23, &umr_bitfield_default }, + { "ALPHA_DESTBLEND", 24, 28, &umr_bitfield_default }, + { "SEPARATE_ALPHA_BLEND", 29, 29, &umr_bitfield_default }, + { "ENABLE", 30, 30, &umr_bitfield_default }, + { "DISABLE_ROP3", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_MRT0_EPITCH[] = { + { "EPITCH", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_MRT1_EPITCH[] = { + { "EPITCH", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_MRT2_EPITCH[] = { + { "EPITCH", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_MRT3_EPITCH[] = { + { "EPITCH", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_MRT4_EPITCH[] = { + { "EPITCH", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_MRT5_EPITCH[] = { + { "EPITCH", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_MRT6_EPITCH[] = { + { "EPITCH", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_MRT7_EPITCH[] = { + { "EPITCH", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCS_COPY_STATE[] = { + { "SRC_STATE_ID", 0, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGFX_COPY_STATE[] = { + { "SRC_STATE_ID", 0, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_POINT_X_RAD[] = { + { "DATA_REGISTER", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_POINT_Y_RAD[] = { + { "DATA_REGISTER", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_POINT_SIZE[] = { + { "DATA_REGISTER", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_POINT_CULL_RAD[] = { + { "DATA_REGISTER", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_DMA_BASE_HI[] = { + { "BASE_ADDR", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_DMA_BASE[] = { + { "BASE_ADDR", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_DRAW_INITIATOR[] = { + { "SOURCE_SELECT", 0, 1, &umr_bitfield_default }, + { "MAJOR_MODE", 2, 3, &umr_bitfield_default }, + { "SPRITE_EN_R6XX", 4, 4, &umr_bitfield_default }, + { "NOT_EOP", 5, 5, &umr_bitfield_default }, + { "USE_OPAQUE", 6, 6, &umr_bitfield_default }, + { "UNROLLED_INST", 7, 7, &umr_bitfield_default }, + { "GRBM_SKEW_NO_DEC", 8, 8, &umr_bitfield_default }, + { "REG_RT_INDEX", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_IMMED_DATA[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_EVENT_ADDRESS_REG[] = { + { "ADDRESS_LOW", 0, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_DEPTH_CONTROL[] = { + { "STENCIL_ENABLE", 0, 0, &umr_bitfield_default }, + { "Z_ENABLE", 1, 1, &umr_bitfield_default }, + { "Z_WRITE_ENABLE", 2, 2, &umr_bitfield_default }, + { "DEPTH_BOUNDS_ENABLE", 3, 3, &umr_bitfield_default }, + { "ZFUNC", 4, 6, &umr_bitfield_default }, + { "BACKFACE_ENABLE", 7, 7, &umr_bitfield_default }, + { "STENCILFUNC", 8, 10, &umr_bitfield_default }, + { "STENCILFUNC_BF", 20, 22, &umr_bitfield_default }, + { "ENABLE_COLOR_WRITES_ON_DEPTH_FAIL", 30, 30, &umr_bitfield_default }, + { "DISABLE_COLOR_WRITES_ON_DEPTH_PASS", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_EQAA[] = { + { "MAX_ANCHOR_SAMPLES", 0, 2, &umr_bitfield_default }, + { "PS_ITER_SAMPLES", 4, 6, &umr_bitfield_default }, + { "MASK_EXPORT_NUM_SAMPLES", 8, 10, &umr_bitfield_default }, + { "ALPHA_TO_MASK_NUM_SAMPLES", 12, 14, &umr_bitfield_default }, + { "HIGH_QUALITY_INTERSECTIONS", 16, 16, &umr_bitfield_default }, + { "INCOHERENT_EQAA_READS", 17, 17, &umr_bitfield_default }, + { "INTERPOLATE_COMP_Z", 18, 18, &umr_bitfield_default }, + { "INTERPOLATE_SRC_Z", 19, 19, &umr_bitfield_default }, + { "STATIC_ANCHOR_ASSOCIATIONS", 20, 20, &umr_bitfield_default }, + { "ALPHA_TO_MASK_EQAA_DISABLE", 21, 21, &umr_bitfield_default }, + { "OVERRASTERIZATION_AMOUNT", 24, 26, &umr_bitfield_default }, + { "ENABLE_POSTZ_OVERRASTERIZATION", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR_CONTROL[] = { + { "DISABLE_DUAL_QUAD", 0, 0, &umr_bitfield_default }, + { "DEGAMMA_ENABLE", 3, 3, &umr_bitfield_default }, + { "MODE", 4, 6, &umr_bitfield_default }, + { "ROP3", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_SHADER_CONTROL[] = { + { "Z_EXPORT_ENABLE", 0, 0, &umr_bitfield_default }, + { "STENCIL_TEST_VAL_EXPORT_ENABLE", 1, 1, &umr_bitfield_default }, + { "STENCIL_OP_VAL_EXPORT_ENABLE", 2, 2, &umr_bitfield_default }, + { "Z_ORDER", 4, 5, &umr_bitfield_default }, + { "KILL_ENABLE", 6, 6, &umr_bitfield_default }, + { "COVERAGE_TO_MASK_ENABLE", 7, 7, &umr_bitfield_default }, + { "MASK_EXPORT_ENABLE", 8, 8, &umr_bitfield_default }, + { "EXEC_ON_HIER_FAIL", 9, 9, &umr_bitfield_default }, + { "EXEC_ON_NOOP", 10, 10, &umr_bitfield_default }, + { "ALPHA_TO_MASK_DISABLE", 11, 11, &umr_bitfield_default }, + { "DEPTH_BEFORE_SHADER", 12, 12, &umr_bitfield_default }, + { "CONSERVATIVE_Z_EXPORT", 13, 14, &umr_bitfield_default }, + { "DUAL_QUAD_DISABLE", 15, 15, &umr_bitfield_default }, + { "PRIMITIVE_ORDERED_PIXEL_SHADER", 16, 16, &umr_bitfield_default }, + { "EXEC_IF_OVERLAPPED", 17, 17, &umr_bitfield_default }, + { "POPS_OVERLAP_NUM_SAMPLES", 20, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_CLIP_CNTL[] = { + { "UCP_ENA_0", 0, 0, &umr_bitfield_default }, + { "UCP_ENA_1", 1, 1, &umr_bitfield_default }, + { "UCP_ENA_2", 2, 2, &umr_bitfield_default }, + { "UCP_ENA_3", 3, 3, &umr_bitfield_default }, + { "UCP_ENA_4", 4, 4, &umr_bitfield_default }, + { "UCP_ENA_5", 5, 5, &umr_bitfield_default }, + { "PS_UCP_Y_SCALE_NEG", 13, 13, &umr_bitfield_default }, + { "PS_UCP_MODE", 14, 15, &umr_bitfield_default }, + { "CLIP_DISABLE", 16, 16, &umr_bitfield_default }, + { "UCP_CULL_ONLY_ENA", 17, 17, &umr_bitfield_default }, + { "BOUNDARY_EDGE_FLAG_ENA", 18, 18, &umr_bitfield_default }, + { "DX_CLIP_SPACE_DEF", 19, 19, &umr_bitfield_default }, + { "DIS_CLIP_ERR_DETECT", 20, 20, &umr_bitfield_default }, + { "VTX_KILL_OR", 21, 21, &umr_bitfield_default }, + { "DX_RASTERIZATION_KILL", 22, 22, &umr_bitfield_default }, + { "DX_LINEAR_ATTR_CLIP_ENA", 24, 24, &umr_bitfield_default }, + { "VTE_VPORT_PROVOKE_DISABLE", 25, 25, &umr_bitfield_default }, + { "ZCLIP_NEAR_DISABLE", 26, 26, &umr_bitfield_default }, + { "ZCLIP_FAR_DISABLE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SU_SC_MODE_CNTL[] = { + { "CULL_FRONT", 0, 0, &umr_bitfield_default }, + { "CULL_BACK", 1, 1, &umr_bitfield_default }, + { "FACE", 2, 2, &umr_bitfield_default }, + { "POLY_MODE", 3, 4, &umr_bitfield_default }, + { "POLYMODE_FRONT_PTYPE", 5, 7, &umr_bitfield_default }, + { "POLYMODE_BACK_PTYPE", 8, 10, &umr_bitfield_default }, + { "POLY_OFFSET_FRONT_ENABLE", 11, 11, &umr_bitfield_default }, + { "POLY_OFFSET_BACK_ENABLE", 12, 12, &umr_bitfield_default }, + { "POLY_OFFSET_PARA_ENABLE", 13, 13, &umr_bitfield_default }, + { "VTX_WINDOW_OFFSET_ENABLE", 16, 16, &umr_bitfield_default }, + { "PROVOKING_VTX_LAST", 19, 19, &umr_bitfield_default }, + { "PERSP_CORR_DIS", 20, 20, &umr_bitfield_default }, + { "MULTI_PRIM_IB_ENA", 21, 21, &umr_bitfield_default }, + { "RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF", 22, 22, &umr_bitfield_default }, + { "NEW_QUAD_DECOMPOSITION", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VTE_CNTL[] = { + { "VPORT_X_SCALE_ENA", 0, 0, &umr_bitfield_default }, + { "VPORT_X_OFFSET_ENA", 1, 1, &umr_bitfield_default }, + { "VPORT_Y_SCALE_ENA", 2, 2, &umr_bitfield_default }, + { "VPORT_Y_OFFSET_ENA", 3, 3, &umr_bitfield_default }, + { "VPORT_Z_SCALE_ENA", 4, 4, &umr_bitfield_default }, + { "VPORT_Z_OFFSET_ENA", 5, 5, &umr_bitfield_default }, + { "VTX_XY_FMT", 8, 8, &umr_bitfield_default }, + { "VTX_Z_FMT", 9, 9, &umr_bitfield_default }, + { "VTX_W0_FMT", 10, 10, &umr_bitfield_default }, + { "PERFCOUNTER_REF", 11, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_VS_OUT_CNTL[] = { + { "CLIP_DIST_ENA_0", 0, 0, &umr_bitfield_default }, + { "CLIP_DIST_ENA_1", 1, 1, &umr_bitfield_default }, + { "CLIP_DIST_ENA_2", 2, 2, &umr_bitfield_default }, + { "CLIP_DIST_ENA_3", 3, 3, &umr_bitfield_default }, + { "CLIP_DIST_ENA_4", 4, 4, &umr_bitfield_default }, + { "CLIP_DIST_ENA_5", 5, 5, &umr_bitfield_default }, + { "CLIP_DIST_ENA_6", 6, 6, &umr_bitfield_default }, + { "CLIP_DIST_ENA_7", 7, 7, &umr_bitfield_default }, + { "CULL_DIST_ENA_0", 8, 8, &umr_bitfield_default }, + { "CULL_DIST_ENA_1", 9, 9, &umr_bitfield_default }, + { "CULL_DIST_ENA_2", 10, 10, &umr_bitfield_default }, + { "CULL_DIST_ENA_3", 11, 11, &umr_bitfield_default }, + { "CULL_DIST_ENA_4", 12, 12, &umr_bitfield_default }, + { "CULL_DIST_ENA_5", 13, 13, &umr_bitfield_default }, + { "CULL_DIST_ENA_6", 14, 14, &umr_bitfield_default }, + { "CULL_DIST_ENA_7", 15, 15, &umr_bitfield_default }, + { "USE_VTX_POINT_SIZE", 16, 16, &umr_bitfield_default }, + { "USE_VTX_EDGE_FLAG", 17, 17, &umr_bitfield_default }, + { "USE_VTX_RENDER_TARGET_INDX", 18, 18, &umr_bitfield_default }, + { "USE_VTX_VIEWPORT_INDX", 19, 19, &umr_bitfield_default }, + { "USE_VTX_KILL_FLAG", 20, 20, &umr_bitfield_default }, + { "VS_OUT_MISC_VEC_ENA", 21, 21, &umr_bitfield_default }, + { "VS_OUT_CCDIST0_VEC_ENA", 22, 22, &umr_bitfield_default }, + { "VS_OUT_CCDIST1_VEC_ENA", 23, 23, &umr_bitfield_default }, + { "VS_OUT_MISC_SIDE_BUS_ENA", 24, 24, &umr_bitfield_default }, + { "USE_VTX_GS_CUT_FLAG", 25, 25, &umr_bitfield_default }, + { "USE_VTX_LINE_WIDTH", 26, 26, &umr_bitfield_default }, + { "USE_VTX_SHD_OBJPRIM_ID", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_NANINF_CNTL[] = { + { "VTE_XY_INF_DISCARD", 0, 0, &umr_bitfield_default }, + { "VTE_Z_INF_DISCARD", 1, 1, &umr_bitfield_default }, + { "VTE_W_INF_DISCARD", 2, 2, &umr_bitfield_default }, + { "VTE_0XNANINF_IS_0", 3, 3, &umr_bitfield_default }, + { "VTE_XY_NAN_RETAIN", 4, 4, &umr_bitfield_default }, + { "VTE_Z_NAN_RETAIN", 5, 5, &umr_bitfield_default }, + { "VTE_W_NAN_RETAIN", 6, 6, &umr_bitfield_default }, + { "VTE_W_RECIP_NAN_IS_0", 7, 7, &umr_bitfield_default }, + { "VS_XY_NAN_TO_INF", 8, 8, &umr_bitfield_default }, + { "VS_XY_INF_RETAIN", 9, 9, &umr_bitfield_default }, + { "VS_Z_NAN_TO_INF", 10, 10, &umr_bitfield_default }, + { "VS_Z_INF_RETAIN", 11, 11, &umr_bitfield_default }, + { "VS_W_NAN_TO_INF", 12, 12, &umr_bitfield_default }, + { "VS_W_INF_RETAIN", 13, 13, &umr_bitfield_default }, + { "VS_CLIP_DIST_INF_DISCARD", 14, 14, &umr_bitfield_default }, + { "VTE_NO_OUTPUT_NEG_0", 20, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SU_LINE_STIPPLE_CNTL[] = { + { "LINE_STIPPLE_RESET", 0, 1, &umr_bitfield_default }, + { "EXPAND_FULL_LENGTH", 2, 2, &umr_bitfield_default }, + { "FRACTIONAL_ACCUM", 3, 3, &umr_bitfield_default }, + { "DIAMOND_ADJUST", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SU_LINE_STIPPLE_SCALE[] = { + { "LINE_STIPPLE_SCALE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SU_PRIM_FILTER_CNTL[] = { + { "TRIANGLE_FILTER_DISABLE", 0, 0, &umr_bitfield_default }, + { "LINE_FILTER_DISABLE", 1, 1, &umr_bitfield_default }, + { "POINT_FILTER_DISABLE", 2, 2, &umr_bitfield_default }, + { "RECTANGLE_FILTER_DISABLE", 3, 3, &umr_bitfield_default }, + { "TRIANGLE_EXPAND_ENA", 4, 4, &umr_bitfield_default }, + { "LINE_EXPAND_ENA", 5, 5, &umr_bitfield_default }, + { "POINT_EXPAND_ENA", 6, 6, &umr_bitfield_default }, + { "RECTANGLE_EXPAND_ENA", 7, 7, &umr_bitfield_default }, + { "PRIM_EXPAND_CONSTANT", 8, 15, &umr_bitfield_default }, + { "XMAX_RIGHT_EXCLUSION", 30, 30, &umr_bitfield_default }, + { "YMAX_BOTTOM_EXCLUSION", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SU_SMALL_PRIM_FILTER_CNTL[] = { + { "SMALL_PRIM_FILTER_ENABLE", 0, 0, &umr_bitfield_default }, + { "TRIANGLE_FILTER_DISABLE", 1, 1, &umr_bitfield_default }, + { "LINE_FILTER_DISABLE", 2, 2, &umr_bitfield_default }, + { "POINT_FILTER_DISABLE", 3, 3, &umr_bitfield_default }, + { "RECTANGLE_FILTER_DISABLE", 4, 4, &umr_bitfield_default }, + { "SRBSL_ENABLE", 5, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_OBJPRIM_ID_CNTL[] = { + { "OBJ_ID_SEL", 0, 0, &umr_bitfield_default }, + { "ADD_PIPED_PRIM_ID", 1, 1, &umr_bitfield_default }, + { "EN_32BIT_OBJPRIMID", 2, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_NGG_CNTL[] = { + { "VERTEX_REUSE_OFF", 0, 0, &umr_bitfield_default }, + { "INDEX_BUF_EDGE_FLAG_ENA", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SU_OVER_RASTERIZATION_CNTL[] = { + { "DISCARD_0_AREA_TRIANGLES", 0, 0, &umr_bitfield_default }, + { "DISCARD_0_AREA_LINES", 1, 1, &umr_bitfield_default }, + { "DISCARD_0_AREA_POINTS", 2, 2, &umr_bitfield_default }, + { "DISCARD_0_AREA_RECTANGLES", 3, 3, &umr_bitfield_default }, + { "USE_PROVOKING_ZW", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SU_POINT_SIZE[] = { + { "HEIGHT", 0, 15, &umr_bitfield_default }, + { "WIDTH", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SU_POINT_MINMAX[] = { + { "MIN_SIZE", 0, 15, &umr_bitfield_default }, + { "MAX_SIZE", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SU_LINE_CNTL[] = { + { "WIDTH", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_LINE_STIPPLE[] = { + { "LINE_PATTERN", 0, 15, &umr_bitfield_default }, + { "REPEAT_COUNT", 16, 23, &umr_bitfield_default }, + { "PATTERN_BIT_ORDER", 28, 28, &umr_bitfield_default }, + { "AUTO_RESET_CNTL", 29, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_OUTPUT_PATH_CNTL[] = { + { "PATH_SELECT", 0, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_HOS_CNTL[] = { + { "TESS_MODE", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_HOS_MAX_TESS_LEVEL[] = { + { "MAX_TESS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_HOS_MIN_TESS_LEVEL[] = { + { "MIN_TESS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_HOS_REUSE_DEPTH[] = { + { "REUSE_DEPTH", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_GROUP_PRIM_TYPE[] = { + { "PRIM_TYPE", 0, 4, &umr_bitfield_default }, + { "RETAIN_ORDER", 14, 14, &umr_bitfield_default }, + { "RETAIN_QUADS", 15, 15, &umr_bitfield_default }, + { "PRIM_ORDER", 16, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_GROUP_FIRST_DECR[] = { + { "FIRST_DECR", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_GROUP_DECR[] = { + { "DECR", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_GROUP_VECT_0_CNTL[] = { + { "COMP_X_EN", 0, 0, &umr_bitfield_default }, + { "COMP_Y_EN", 1, 1, &umr_bitfield_default }, + { "COMP_Z_EN", 2, 2, &umr_bitfield_default }, + { "COMP_W_EN", 3, 3, &umr_bitfield_default }, + { "STRIDE", 8, 15, &umr_bitfield_default }, + { "SHIFT", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_GROUP_VECT_1_CNTL[] = { + { "COMP_X_EN", 0, 0, &umr_bitfield_default }, + { "COMP_Y_EN", 1, 1, &umr_bitfield_default }, + { "COMP_Z_EN", 2, 2, &umr_bitfield_default }, + { "COMP_W_EN", 3, 3, &umr_bitfield_default }, + { "STRIDE", 8, 15, &umr_bitfield_default }, + { "SHIFT", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_GROUP_VECT_0_FMT_CNTL[] = { + { "X_CONV", 0, 3, &umr_bitfield_default }, + { "X_OFFSET", 4, 7, &umr_bitfield_default }, + { "Y_CONV", 8, 11, &umr_bitfield_default }, + { "Y_OFFSET", 12, 15, &umr_bitfield_default }, + { "Z_CONV", 16, 19, &umr_bitfield_default }, + { "Z_OFFSET", 20, 23, &umr_bitfield_default }, + { "W_CONV", 24, 27, &umr_bitfield_default }, + { "W_OFFSET", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_GROUP_VECT_1_FMT_CNTL[] = { + { "X_CONV", 0, 3, &umr_bitfield_default }, + { "X_OFFSET", 4, 7, &umr_bitfield_default }, + { "Y_CONV", 8, 11, &umr_bitfield_default }, + { "Y_OFFSET", 12, 15, &umr_bitfield_default }, + { "Z_CONV", 16, 19, &umr_bitfield_default }, + { "Z_OFFSET", 20, 23, &umr_bitfield_default }, + { "W_CONV", 24, 27, &umr_bitfield_default }, + { "W_OFFSET", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_GS_MODE[] = { + { "MODE", 0, 2, &umr_bitfield_default }, + { "RESERVED_0", 3, 3, &umr_bitfield_default }, + { "CUT_MODE", 4, 5, &umr_bitfield_default }, + { "RESERVED_1", 6, 10, &umr_bitfield_default }, + { "GS_C_PACK_EN", 11, 11, &umr_bitfield_default }, + { "RESERVED_2", 12, 12, &umr_bitfield_default }, + { "ES_PASSTHRU", 13, 13, &umr_bitfield_default }, + { "RESERVED_3", 14, 14, &umr_bitfield_default }, + { "RESERVED_4", 15, 15, &umr_bitfield_default }, + { "RESERVED_5", 16, 16, &umr_bitfield_default }, + { "PARTIAL_THD_AT_EOI", 17, 17, &umr_bitfield_default }, + { "SUPPRESS_CUTS", 18, 18, &umr_bitfield_default }, + { "ES_WRITE_OPTIMIZE", 19, 19, &umr_bitfield_default }, + { "GS_WRITE_OPTIMIZE", 20, 20, &umr_bitfield_default }, + { "ONCHIP", 21, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_GS_ONCHIP_CNTL[] = { + { "ES_VERTS_PER_SUBGRP", 0, 10, &umr_bitfield_default }, + { "GS_PRIMS_PER_SUBGRP", 11, 21, &umr_bitfield_default }, + { "GS_INST_PRIMS_IN_SUBGRP", 22, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_MODE_CNTL_0[] = { + { "MSAA_ENABLE", 0, 0, &umr_bitfield_default }, + { "VPORT_SCISSOR_ENABLE", 1, 1, &umr_bitfield_default }, + { "LINE_STIPPLE_ENABLE", 2, 2, &umr_bitfield_default }, + { "SEND_UNLIT_STILES_TO_PKR", 3, 3, &umr_bitfield_default }, + { "SCALE_LINE_WIDTH_PAD", 4, 4, &umr_bitfield_default }, + { "ALTERNATE_RBS_PER_TILE", 5, 5, &umr_bitfield_default }, + { "COARSE_TILE_STARTS_ON_EVEN_RB", 6, 6, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_MODE_CNTL_1[] = { + { "WALK_SIZE", 0, 0, &umr_bitfield_default }, + { "WALK_ALIGNMENT", 1, 1, &umr_bitfield_default }, + { "WALK_ALIGN8_PRIM_FITS_ST", 2, 2, &umr_bitfield_default }, + { "WALK_FENCE_ENABLE", 3, 3, &umr_bitfield_default }, + { "WALK_FENCE_SIZE", 4, 6, &umr_bitfield_default }, + { "SUPERTILE_WALK_ORDER_ENABLE", 7, 7, &umr_bitfield_default }, + { "TILE_WALK_ORDER_ENABLE", 8, 8, &umr_bitfield_default }, + { "TILE_COVER_DISABLE", 9, 9, &umr_bitfield_default }, + { "TILE_COVER_NO_SCISSOR", 10, 10, &umr_bitfield_default }, + { "ZMM_LINE_EXTENT", 11, 11, &umr_bitfield_default }, + { "ZMM_LINE_OFFSET", 12, 12, &umr_bitfield_default }, + { "ZMM_RECT_EXTENT", 13, 13, &umr_bitfield_default }, + { "KILL_PIX_POST_HI_Z", 14, 14, &umr_bitfield_default }, + { "KILL_PIX_POST_DETAIL_MASK", 15, 15, &umr_bitfield_default }, + { "PS_ITER_SAMPLE", 16, 16, &umr_bitfield_default }, + { "MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE", 17, 17, &umr_bitfield_default }, + { "MULTI_GPU_SUPERTILE_ENABLE", 18, 18, &umr_bitfield_default }, + { "GPU_ID_OVERRIDE_ENABLE", 19, 19, &umr_bitfield_default }, + { "GPU_ID_OVERRIDE", 20, 23, &umr_bitfield_default }, + { "MULTI_GPU_PRIM_DISCARD_ENABLE", 24, 24, &umr_bitfield_default }, + { "FORCE_EOV_CNTDWN_ENABLE", 25, 25, &umr_bitfield_default }, + { "FORCE_EOV_REZ_ENABLE", 26, 26, &umr_bitfield_default }, + { "OUT_OF_ORDER_PRIMITIVE_ENABLE", 27, 27, &umr_bitfield_default }, + { "OUT_OF_ORDER_WATER_MARK", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_ENHANCE[] = { + { "MISC", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_GS_PER_ES[] = { + { "GS_PER_ES", 0, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_ES_PER_GS[] = { + { "ES_PER_GS", 0, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_GS_PER_VS[] = { + { "GS_PER_VS", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_GSVS_RING_OFFSET_1[] = { + { "OFFSET", 0, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_GSVS_RING_OFFSET_2[] = { + { "OFFSET", 0, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_GSVS_RING_OFFSET_3[] = { + { "OFFSET", 0, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_GS_OUT_PRIM_TYPE[] = { + { "OUTPRIM_TYPE", 0, 5, &umr_bitfield_default }, + { "OUTPRIM_TYPE_1", 8, 13, &umr_bitfield_default }, + { "OUTPRIM_TYPE_2", 16, 21, &umr_bitfield_default }, + { "OUTPRIM_TYPE_3", 22, 27, &umr_bitfield_default }, + { "UNIQUE_TYPE_PER_STREAM", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIA_ENHANCE[] = { + { "MISC", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_DMA_SIZE[] = { + { "NUM_INDICES", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_DMA_MAX_SIZE[] = { + { "MAX_SIZE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_DMA_INDEX_TYPE[] = { + { "INDEX_TYPE", 0, 1, &umr_bitfield_default }, + { "SWAP_MODE", 2, 3, &umr_bitfield_default }, + { "BUF_TYPE", 4, 5, &umr_bitfield_default }, + { "RDREQ_POLICY", 6, 6, &umr_bitfield_default }, + { "PRIMGEN_EN", 8, 8, &umr_bitfield_default }, + { "NOT_EOP", 9, 9, &umr_bitfield_default }, + { "REQ_PATH", 10, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWD_ENHANCE[] = { + { "MISC", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_PRIMITIVEID_EN[] = { + { "PRIMITIVEID_EN", 0, 0, &umr_bitfield_default }, + { "DISABLE_RESET_ON_EOI", 1, 1, &umr_bitfield_default }, + { "NGG_DISABLE_PROVOK_REUSE", 2, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_DMA_NUM_INSTANCES[] = { + { "NUM_INSTANCES", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_PRIMITIVEID_RESET[] = { + { "VALUE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_EVENT_INITIATOR[] = { + { "EVENT_TYPE", 0, 5, &umr_bitfield_default }, + { "ADDRESS_HI", 10, 26, &umr_bitfield_default }, + { "EXTENDED_EVENT", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_GS_MAX_PRIMS_PER_SUBGROUP[] = { + { "MAX_PRIMS_PER_SUBGROUP", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_DRAW_PAYLOAD_CNTL[] = { + { "OBJPRIM_ID_EN", 0, 0, &umr_bitfield_default }, + { "EN_REG_RT_INDEX", 1, 1, &umr_bitfield_default }, + { "EN_PIPELINE_PRIMID", 2, 2, &umr_bitfield_default }, + { "OBJECT_ID_INST_EN", 3, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_INDEX_PAYLOAD_CNTL[] = { + { "COMPOUND_INDEX_EN", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_INSTANCE_STEP_RATE_0[] = { + { "STEP_RATE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_INSTANCE_STEP_RATE_1[] = { + { "STEP_RATE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_ESGS_RING_ITEMSIZE[] = { + { "ITEMSIZE", 0, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_GSVS_RING_ITEMSIZE[] = { + { "ITEMSIZE", 0, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_REUSE_OFF[] = { + { "REUSE_OFF", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_VTX_CNT_EN[] = { + { "VTX_CNT_EN", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_HTILE_SURFACE[] = { + { "FULL_CACHE", 1, 1, &umr_bitfield_default }, + { "HTILE_USES_PRELOAD_WIN", 2, 2, &umr_bitfield_default }, + { "PRELOAD", 3, 3, &umr_bitfield_default }, + { "PREFETCH_WIDTH", 4, 9, &umr_bitfield_default }, + { "PREFETCH_HEIGHT", 10, 15, &umr_bitfield_default }, + { "DST_OUTSIDE_ZERO_TO_ONE", 16, 16, &umr_bitfield_default }, + { "PIPE_ALIGNED", 18, 18, &umr_bitfield_default }, + { "RB_ALIGNED", 19, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_SRESULTS_COMPARE_STATE0[] = { + { "COMPAREFUNC0", 0, 2, &umr_bitfield_default }, + { "COMPAREVALUE0", 4, 11, &umr_bitfield_default }, + { "COMPAREMASK0", 12, 19, &umr_bitfield_default }, + { "ENABLE0", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_SRESULTS_COMPARE_STATE1[] = { + { "COMPAREFUNC1", 0, 2, &umr_bitfield_default }, + { "COMPAREVALUE1", 4, 11, &umr_bitfield_default }, + { "COMPAREMASK1", 12, 19, &umr_bitfield_default }, + { "ENABLE1", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_PRELOAD_CONTROL[] = { + { "START_X", 0, 7, &umr_bitfield_default }, + { "START_Y", 8, 15, &umr_bitfield_default }, + { "MAX_X", 16, 23, &umr_bitfield_default }, + { "MAX_Y", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_STRMOUT_BUFFER_SIZE_0[] = { + { "SIZE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_STRMOUT_VTX_STRIDE_0[] = { + { "STRIDE", 0, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_STRMOUT_BUFFER_OFFSET_0[] = { + { "OFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_STRMOUT_BUFFER_SIZE_1[] = { + { "SIZE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_STRMOUT_VTX_STRIDE_1[] = { + { "STRIDE", 0, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_STRMOUT_BUFFER_OFFSET_1[] = { + { "OFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_STRMOUT_BUFFER_SIZE_2[] = { + { "SIZE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_STRMOUT_VTX_STRIDE_2[] = { + { "STRIDE", 0, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_STRMOUT_BUFFER_OFFSET_2[] = { + { "OFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_STRMOUT_BUFFER_SIZE_3[] = { + { "SIZE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_STRMOUT_VTX_STRIDE_3[] = { + { "STRIDE", 0, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_STRMOUT_BUFFER_OFFSET_3[] = { + { "OFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET[] = { + { "OFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE[] = { + { "SIZE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE[] = { + { "VERTEX_STRIDE", 0, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_GS_MAX_VERT_OUT[] = { + { "MAX_VERT_OUT", 0, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_TESS_DISTRIBUTION[] = { + { "ACCUM_ISOLINE", 0, 7, &umr_bitfield_default }, + { "ACCUM_TRI", 8, 15, &umr_bitfield_default }, + { "ACCUM_QUAD", 16, 23, &umr_bitfield_default }, + { "DONUT_SPLIT", 24, 28, &umr_bitfield_default }, + { "TRAP_SPLIT", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_SHADER_STAGES_EN[] = { + { "LS_EN", 0, 1, &umr_bitfield_default }, + { "HS_EN", 2, 2, &umr_bitfield_default }, + { "ES_EN", 3, 4, &umr_bitfield_default }, + { "GS_EN", 5, 5, &umr_bitfield_default }, + { "VS_EN", 6, 7, &umr_bitfield_default }, + { "DISPATCH_DRAW_EN", 9, 9, &umr_bitfield_default }, + { "DIS_DEALLOC_ACCUM_0", 10, 10, &umr_bitfield_default }, + { "DIS_DEALLOC_ACCUM_1", 11, 11, &umr_bitfield_default }, + { "VS_WAVE_ID_EN", 12, 12, &umr_bitfield_default }, + { "PRIMGEN_EN", 13, 13, &umr_bitfield_default }, + { "ORDERED_ID_MODE", 14, 14, &umr_bitfield_default }, + { "MAX_PRIMGRP_IN_WAVE", 15, 18, &umr_bitfield_default }, + { "GS_FAST_LAUNCH", 19, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_LS_HS_CONFIG[] = { + { "NUM_PATCHES", 0, 7, &umr_bitfield_default }, + { "HS_NUM_INPUT_CP", 8, 13, &umr_bitfield_default }, + { "HS_NUM_OUTPUT_CP", 14, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_GS_VERT_ITEMSIZE[] = { + { "ITEMSIZE", 0, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_GS_VERT_ITEMSIZE_1[] = { + { "ITEMSIZE", 0, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_GS_VERT_ITEMSIZE_2[] = { + { "ITEMSIZE", 0, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_GS_VERT_ITEMSIZE_3[] = { + { "ITEMSIZE", 0, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_TF_PARAM[] = { + { "TYPE", 0, 1, &umr_bitfield_default }, + { "PARTITIONING", 2, 4, &umr_bitfield_default }, + { "TOPOLOGY", 5, 7, &umr_bitfield_default }, + { "RESERVED_REDUC_AXIS", 8, 8, &umr_bitfield_default }, + { "DEPRECATED", 9, 9, &umr_bitfield_default }, + { "DISABLE_DONUTS", 14, 14, &umr_bitfield_default }, + { "RDREQ_POLICY", 15, 15, &umr_bitfield_default }, + { "DISTRIBUTION_MODE", 17, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_ALPHA_TO_MASK[] = { + { "ALPHA_TO_MASK_ENABLE", 0, 0, &umr_bitfield_default }, + { "ALPHA_TO_MASK_OFFSET0", 8, 9, &umr_bitfield_default }, + { "ALPHA_TO_MASK_OFFSET1", 10, 11, &umr_bitfield_default }, + { "ALPHA_TO_MASK_OFFSET2", 12, 13, &umr_bitfield_default }, + { "ALPHA_TO_MASK_OFFSET3", 14, 15, &umr_bitfield_default }, + { "OFFSET_ROUND", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_DISPATCH_DRAW_INDEX[] = { + { "MATCH_INDEX", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SU_POLY_OFFSET_DB_FMT_CNTL[] = { + { "POLY_OFFSET_NEG_NUM_DB_BITS", 0, 7, &umr_bitfield_default }, + { "POLY_OFFSET_DB_IS_FLOAT_FMT", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SU_POLY_OFFSET_CLAMP[] = { + { "CLAMP", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SU_POLY_OFFSET_FRONT_SCALE[] = { + { "SCALE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SU_POLY_OFFSET_FRONT_OFFSET[] = { + { "OFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SU_POLY_OFFSET_BACK_SCALE[] = { + { "SCALE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SU_POLY_OFFSET_BACK_OFFSET[] = { + { "OFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_GS_INSTANCE_CNT[] = { + { "ENABLE", 0, 0, &umr_bitfield_default }, + { "CNT", 2, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_STRMOUT_CONFIG[] = { + { "STREAMOUT_0_EN", 0, 0, &umr_bitfield_default }, + { "STREAMOUT_1_EN", 1, 1, &umr_bitfield_default }, + { "STREAMOUT_2_EN", 2, 2, &umr_bitfield_default }, + { "STREAMOUT_3_EN", 3, 3, &umr_bitfield_default }, + { "RAST_STREAM", 4, 6, &umr_bitfield_default }, + { "EN_PRIMS_NEEDED_CNT", 7, 7, &umr_bitfield_default }, + { "RAST_STREAM_MASK", 8, 11, &umr_bitfield_default }, + { "USE_RAST_STREAM_MASK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_STRMOUT_BUFFER_CONFIG[] = { + { "STREAM_0_BUFFER_EN", 0, 3, &umr_bitfield_default }, + { "STREAM_1_BUFFER_EN", 4, 7, &umr_bitfield_default }, + { "STREAM_2_BUFFER_EN", 8, 11, &umr_bitfield_default }, + { "STREAM_3_BUFFER_EN", 12, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_DMA_EVENT_INITIATOR[] = { + { "EVENT_TYPE", 0, 5, &umr_bitfield_default }, + { "ADDRESS_HI", 10, 26, &umr_bitfield_default }, + { "EXTENDED_EVENT", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_CENTROID_PRIORITY_0[] = { + { "DISTANCE_0", 0, 3, &umr_bitfield_default }, + { "DISTANCE_1", 4, 7, &umr_bitfield_default }, + { "DISTANCE_2", 8, 11, &umr_bitfield_default }, + { "DISTANCE_3", 12, 15, &umr_bitfield_default }, + { "DISTANCE_4", 16, 19, &umr_bitfield_default }, + { "DISTANCE_5", 20, 23, &umr_bitfield_default }, + { "DISTANCE_6", 24, 27, &umr_bitfield_default }, + { "DISTANCE_7", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_CENTROID_PRIORITY_1[] = { + { "DISTANCE_8", 0, 3, &umr_bitfield_default }, + { "DISTANCE_9", 4, 7, &umr_bitfield_default }, + { "DISTANCE_10", 8, 11, &umr_bitfield_default }, + { "DISTANCE_11", 12, 15, &umr_bitfield_default }, + { "DISTANCE_12", 16, 19, &umr_bitfield_default }, + { "DISTANCE_13", 20, 23, &umr_bitfield_default }, + { "DISTANCE_14", 24, 27, &umr_bitfield_default }, + { "DISTANCE_15", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_LINE_CNTL[] = { + { "EXPAND_LINE_WIDTH", 9, 9, &umr_bitfield_default }, + { "LAST_PIXEL", 10, 10, &umr_bitfield_default }, + { "PERPENDICULAR_ENDCAP_ENA", 11, 11, &umr_bitfield_default }, + { "DX10_DIAMOND_TEST_ENA", 12, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_AA_CONFIG[] = { + { "MSAA_NUM_SAMPLES", 0, 2, &umr_bitfield_default }, + { "AA_MASK_CENTROID_DTMN", 4, 4, &umr_bitfield_default }, + { "MAX_SAMPLE_DIST", 13, 16, &umr_bitfield_default }, + { "MSAA_EXPOSED_SAMPLES", 20, 22, &umr_bitfield_default }, + { "DETAIL_TO_EXPOSED_MODE", 24, 25, &umr_bitfield_default }, + { "COVERAGE_TO_SHADER_SELECT", 26, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SU_VTX_CNTL[] = { + { "PIX_CENTER", 0, 0, &umr_bitfield_default }, + { "ROUND_MODE", 1, 2, &umr_bitfield_default }, + { "QUANT_MODE", 3, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_GB_VERT_CLIP_ADJ[] = { + { "DATA_REGISTER", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_GB_VERT_DISC_ADJ[] = { + { "DATA_REGISTER", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_GB_HORZ_CLIP_ADJ[] = { + { "DATA_REGISTER", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_CL_GB_HORZ_DISC_ADJ[] = { + { "DATA_REGISTER", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0[] = { + { "S0_X", 0, 3, &umr_bitfield_default }, + { "S0_Y", 4, 7, &umr_bitfield_default }, + { "S1_X", 8, 11, &umr_bitfield_default }, + { "S1_Y", 12, 15, &umr_bitfield_default }, + { "S2_X", 16, 19, &umr_bitfield_default }, + { "S2_Y", 20, 23, &umr_bitfield_default }, + { "S3_X", 24, 27, &umr_bitfield_default }, + { "S3_Y", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1[] = { + { "S4_X", 0, 3, &umr_bitfield_default }, + { "S4_Y", 4, 7, &umr_bitfield_default }, + { "S5_X", 8, 11, &umr_bitfield_default }, + { "S5_Y", 12, 15, &umr_bitfield_default }, + { "S6_X", 16, 19, &umr_bitfield_default }, + { "S6_Y", 20, 23, &umr_bitfield_default }, + { "S7_X", 24, 27, &umr_bitfield_default }, + { "S7_Y", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2[] = { + { "S8_X", 0, 3, &umr_bitfield_default }, + { "S8_Y", 4, 7, &umr_bitfield_default }, + { "S9_X", 8, 11, &umr_bitfield_default }, + { "S9_Y", 12, 15, &umr_bitfield_default }, + { "S10_X", 16, 19, &umr_bitfield_default }, + { "S10_Y", 20, 23, &umr_bitfield_default }, + { "S11_X", 24, 27, &umr_bitfield_default }, + { "S11_Y", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3[] = { + { "S12_X", 0, 3, &umr_bitfield_default }, + { "S12_Y", 4, 7, &umr_bitfield_default }, + { "S13_X", 8, 11, &umr_bitfield_default }, + { "S13_Y", 12, 15, &umr_bitfield_default }, + { "S14_X", 16, 19, &umr_bitfield_default }, + { "S14_Y", 20, 23, &umr_bitfield_default }, + { "S15_X", 24, 27, &umr_bitfield_default }, + { "S15_Y", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0[] = { + { "S0_X", 0, 3, &umr_bitfield_default }, + { "S0_Y", 4, 7, &umr_bitfield_default }, + { "S1_X", 8, 11, &umr_bitfield_default }, + { "S1_Y", 12, 15, &umr_bitfield_default }, + { "S2_X", 16, 19, &umr_bitfield_default }, + { "S2_Y", 20, 23, &umr_bitfield_default }, + { "S3_X", 24, 27, &umr_bitfield_default }, + { "S3_Y", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1[] = { + { "S4_X", 0, 3, &umr_bitfield_default }, + { "S4_Y", 4, 7, &umr_bitfield_default }, + { "S5_X", 8, 11, &umr_bitfield_default }, + { "S5_Y", 12, 15, &umr_bitfield_default }, + { "S6_X", 16, 19, &umr_bitfield_default }, + { "S6_Y", 20, 23, &umr_bitfield_default }, + { "S7_X", 24, 27, &umr_bitfield_default }, + { "S7_Y", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2[] = { + { "S8_X", 0, 3, &umr_bitfield_default }, + { "S8_Y", 4, 7, &umr_bitfield_default }, + { "S9_X", 8, 11, &umr_bitfield_default }, + { "S9_Y", 12, 15, &umr_bitfield_default }, + { "S10_X", 16, 19, &umr_bitfield_default }, + { "S10_Y", 20, 23, &umr_bitfield_default }, + { "S11_X", 24, 27, &umr_bitfield_default }, + { "S11_Y", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3[] = { + { "S12_X", 0, 3, &umr_bitfield_default }, + { "S12_Y", 4, 7, &umr_bitfield_default }, + { "S13_X", 8, 11, &umr_bitfield_default }, + { "S13_Y", 12, 15, &umr_bitfield_default }, + { "S14_X", 16, 19, &umr_bitfield_default }, + { "S14_Y", 20, 23, &umr_bitfield_default }, + { "S15_X", 24, 27, &umr_bitfield_default }, + { "S15_Y", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0[] = { + { "S0_X", 0, 3, &umr_bitfield_default }, + { "S0_Y", 4, 7, &umr_bitfield_default }, + { "S1_X", 8, 11, &umr_bitfield_default }, + { "S1_Y", 12, 15, &umr_bitfield_default }, + { "S2_X", 16, 19, &umr_bitfield_default }, + { "S2_Y", 20, 23, &umr_bitfield_default }, + { "S3_X", 24, 27, &umr_bitfield_default }, + { "S3_Y", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1[] = { + { "S4_X", 0, 3, &umr_bitfield_default }, + { "S4_Y", 4, 7, &umr_bitfield_default }, + { "S5_X", 8, 11, &umr_bitfield_default }, + { "S5_Y", 12, 15, &umr_bitfield_default }, + { "S6_X", 16, 19, &umr_bitfield_default }, + { "S6_Y", 20, 23, &umr_bitfield_default }, + { "S7_X", 24, 27, &umr_bitfield_default }, + { "S7_Y", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2[] = { + { "S8_X", 0, 3, &umr_bitfield_default }, + { "S8_Y", 4, 7, &umr_bitfield_default }, + { "S9_X", 8, 11, &umr_bitfield_default }, + { "S9_Y", 12, 15, &umr_bitfield_default }, + { "S10_X", 16, 19, &umr_bitfield_default }, + { "S10_Y", 20, 23, &umr_bitfield_default }, + { "S11_X", 24, 27, &umr_bitfield_default }, + { "S11_Y", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3[] = { + { "S12_X", 0, 3, &umr_bitfield_default }, + { "S12_Y", 4, 7, &umr_bitfield_default }, + { "S13_X", 8, 11, &umr_bitfield_default }, + { "S13_Y", 12, 15, &umr_bitfield_default }, + { "S14_X", 16, 19, &umr_bitfield_default }, + { "S14_Y", 20, 23, &umr_bitfield_default }, + { "S15_X", 24, 27, &umr_bitfield_default }, + { "S15_Y", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0[] = { + { "S0_X", 0, 3, &umr_bitfield_default }, + { "S0_Y", 4, 7, &umr_bitfield_default }, + { "S1_X", 8, 11, &umr_bitfield_default }, + { "S1_Y", 12, 15, &umr_bitfield_default }, + { "S2_X", 16, 19, &umr_bitfield_default }, + { "S2_Y", 20, 23, &umr_bitfield_default }, + { "S3_X", 24, 27, &umr_bitfield_default }, + { "S3_Y", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1[] = { + { "S4_X", 0, 3, &umr_bitfield_default }, + { "S4_Y", 4, 7, &umr_bitfield_default }, + { "S5_X", 8, 11, &umr_bitfield_default }, + { "S5_Y", 12, 15, &umr_bitfield_default }, + { "S6_X", 16, 19, &umr_bitfield_default }, + { "S6_Y", 20, 23, &umr_bitfield_default }, + { "S7_X", 24, 27, &umr_bitfield_default }, + { "S7_Y", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2[] = { + { "S8_X", 0, 3, &umr_bitfield_default }, + { "S8_Y", 4, 7, &umr_bitfield_default }, + { "S9_X", 8, 11, &umr_bitfield_default }, + { "S9_Y", 12, 15, &umr_bitfield_default }, + { "S10_X", 16, 19, &umr_bitfield_default }, + { "S10_Y", 20, 23, &umr_bitfield_default }, + { "S11_X", 24, 27, &umr_bitfield_default }, + { "S11_Y", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3[] = { + { "S12_X", 0, 3, &umr_bitfield_default }, + { "S12_Y", 4, 7, &umr_bitfield_default }, + { "S13_X", 8, 11, &umr_bitfield_default }, + { "S13_Y", 12, 15, &umr_bitfield_default }, + { "S14_X", 16, 19, &umr_bitfield_default }, + { "S14_Y", 20, 23, &umr_bitfield_default }, + { "S15_X", 24, 27, &umr_bitfield_default }, + { "S15_Y", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_AA_MASK_X0Y0_X1Y0[] = { + { "AA_MASK_X0Y0", 0, 15, &umr_bitfield_default }, + { "AA_MASK_X1Y0", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_AA_MASK_X0Y1_X1Y1[] = { + { "AA_MASK_X0Y1", 0, 15, &umr_bitfield_default }, + { "AA_MASK_X1Y1", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_SHADER_CONTROL[] = { + { "REALIGN_DQUADS_AFTER_N_WAVES", 0, 1, &umr_bitfield_default }, + { "LOAD_COLLISION_WAVEID", 2, 2, &umr_bitfield_default }, + { "LOAD_INTRAWAVE_COLLISION", 3, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_BINNER_CNTL_0[] = { + { "BINNING_MODE", 0, 1, &umr_bitfield_default }, + { "BIN_SIZE_X", 2, 2, &umr_bitfield_default }, + { "BIN_SIZE_Y", 3, 3, &umr_bitfield_default }, + { "BIN_SIZE_X_EXTEND", 4, 6, &umr_bitfield_default }, + { "BIN_SIZE_Y_EXTEND", 7, 9, &umr_bitfield_default }, + { "CONTEXT_STATES_PER_BIN", 10, 12, &umr_bitfield_default }, + { "PERSISTENT_STATES_PER_BIN", 13, 17, &umr_bitfield_default }, + { "DISABLE_START_OF_PRIM", 18, 18, &umr_bitfield_default }, + { "FPOVS_PER_BATCH", 19, 26, &umr_bitfield_default }, + { "OPTIMAL_BIN_SELECTION", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_BINNER_CNTL_1[] = { + { "MAX_ALLOC_COUNT", 0, 15, &umr_bitfield_default }, + { "MAX_PRIM_PER_BATCH", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_CONSERVATIVE_RASTERIZATION_CNTL[] = { + { "OVER_RAST_ENABLE", 0, 0, &umr_bitfield_default }, + { "OVER_RAST_SAMPLE_SELECT", 1, 4, &umr_bitfield_default }, + { "UNDER_RAST_ENABLE", 5, 5, &umr_bitfield_default }, + { "UNDER_RAST_SAMPLE_SELECT", 6, 9, &umr_bitfield_default }, + { "PBB_UNCERTAINTY_REGION_ENABLE", 10, 10, &umr_bitfield_default }, + { "ZMM_TRI_EXTENT", 11, 11, &umr_bitfield_default }, + { "ZMM_TRI_OFFSET", 12, 12, &umr_bitfield_default }, + { "OVERRIDE_OVER_RAST_INNER_TO_NORMAL", 13, 13, &umr_bitfield_default }, + { "OVERRIDE_UNDER_RAST_INNER_TO_NORMAL", 14, 14, &umr_bitfield_default }, + { "DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE", 15, 15, &umr_bitfield_default }, + { "UNCERTAINTY_REGION_MODE", 16, 17, &umr_bitfield_default }, + { "OUTER_UNCERTAINTY_EDGERULE_OVERRIDE", 18, 18, &umr_bitfield_default }, + { "INNER_UNCERTAINTY_EDGERULE_OVERRIDE", 19, 19, &umr_bitfield_default }, + { "NULL_SQUAD_AA_MASK_ENABLE", 20, 20, &umr_bitfield_default }, + { "COVERAGE_AA_MASK_ENABLE", 21, 21, &umr_bitfield_default }, + { "PREZ_AA_MASK_ENABLE", 22, 22, &umr_bitfield_default }, + { "POSTZ_AA_MASK_ENABLE", 23, 23, &umr_bitfield_default }, + { "CENTROID_SAMPLE_OVERRIDE", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_NGG_MODE_CNTL[] = { + { "MAX_DEALLOCS_IN_WAVE", 0, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_VERTEX_REUSE_BLOCK_CNTL[] = { + { "VTX_REUSE_DEPTH", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_OUT_DEALLOC_CNTL[] = { + { "DEALLOC_DIST", 0, 6, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR0_BASE[] = { + { "BASE_256B", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR0_BASE_EXT[] = { + { "BASE_256B", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR0_ATTRIB2[] = { + { "MIP0_HEIGHT", 0, 13, &umr_bitfield_default }, + { "MIP0_WIDTH", 14, 27, &umr_bitfield_default }, + { "MAX_MIP", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR0_VIEW[] = { + { "SLICE_START", 0, 10, &umr_bitfield_default }, + { "SLICE_MAX", 13, 23, &umr_bitfield_default }, + { "MIP_LEVEL", 24, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR0_INFO[] = { + { "ENDIAN", 0, 1, &umr_bitfield_default }, + { "FORMAT", 2, 6, &umr_bitfield_default }, + { "NUMBER_TYPE", 8, 10, &umr_bitfield_default }, + { "COMP_SWAP", 11, 12, &umr_bitfield_default }, + { "FAST_CLEAR", 13, 13, &umr_bitfield_default }, + { "COMPRESSION", 14, 14, &umr_bitfield_default }, + { "BLEND_CLAMP", 15, 15, &umr_bitfield_default }, + { "BLEND_BYPASS", 16, 16, &umr_bitfield_default }, + { "SIMPLE_FLOAT", 17, 17, &umr_bitfield_default }, + { "ROUND_MODE", 18, 18, &umr_bitfield_default }, + { "BLEND_OPT_DONT_RD_DST", 20, 22, &umr_bitfield_default }, + { "BLEND_OPT_DISCARD_PIXEL", 23, 25, &umr_bitfield_default }, + { "FMASK_COMPRESSION_DISABLE", 26, 26, &umr_bitfield_default }, + { "FMASK_COMPRESS_1FRAG_ONLY", 27, 27, &umr_bitfield_default }, + { "DCC_ENABLE", 28, 28, &umr_bitfield_default }, + { "CMASK_ADDR_TYPE", 29, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR0_ATTRIB[] = { + { "MIP0_DEPTH", 0, 10, &umr_bitfield_default }, + { "META_LINEAR", 11, 11, &umr_bitfield_default }, + { "NUM_SAMPLES", 12, 14, &umr_bitfield_default }, + { "NUM_FRAGMENTS", 15, 16, &umr_bitfield_default }, + { "FORCE_DST_ALPHA_1", 17, 17, &umr_bitfield_default }, + { "COLOR_SW_MODE", 18, 22, &umr_bitfield_default }, + { "FMASK_SW_MODE", 23, 27, &umr_bitfield_default }, + { "RESOURCE_TYPE", 28, 29, &umr_bitfield_default }, + { "RB_ALIGNED", 30, 30, &umr_bitfield_default }, + { "PIPE_ALIGNED", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR0_DCC_CONTROL[] = { + { "OVERWRITE_COMBINER_DISABLE", 0, 0, &umr_bitfield_default }, + { "KEY_CLEAR_ENABLE", 1, 1, &umr_bitfield_default }, + { "MAX_UNCOMPRESSED_BLOCK_SIZE", 2, 3, &umr_bitfield_default }, + { "MIN_COMPRESSED_BLOCK_SIZE", 4, 4, &umr_bitfield_default }, + { "MAX_COMPRESSED_BLOCK_SIZE", 5, 6, &umr_bitfield_default }, + { "COLOR_TRANSFORM", 7, 8, &umr_bitfield_default }, + { "INDEPENDENT_64B_BLOCKS", 9, 9, &umr_bitfield_default }, + { "LOSSY_RGB_PRECISION", 10, 13, &umr_bitfield_default }, + { "LOSSY_ALPHA_PRECISION", 14, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR0_CMASK[] = { + { "BASE_256B", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR0_CMASK_BASE_EXT[] = { + { "BASE_256B", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR0_FMASK[] = { + { "BASE_256B", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR0_FMASK_BASE_EXT[] = { + { "BASE_256B", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR0_CLEAR_WORD0[] = { + { "CLEAR_WORD0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR0_CLEAR_WORD1[] = { + { "CLEAR_WORD1", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR0_DCC_BASE[] = { + { "BASE_256B", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR0_DCC_BASE_EXT[] = { + { "BASE_256B", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR1_BASE[] = { + { "BASE_256B", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR1_BASE_EXT[] = { + { "BASE_256B", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR1_ATTRIB2[] = { + { "MIP0_HEIGHT", 0, 13, &umr_bitfield_default }, + { "MIP0_WIDTH", 14, 27, &umr_bitfield_default }, + { "MAX_MIP", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR1_VIEW[] = { + { "SLICE_START", 0, 10, &umr_bitfield_default }, + { "SLICE_MAX", 13, 23, &umr_bitfield_default }, + { "MIP_LEVEL", 24, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR1_INFO[] = { + { "ENDIAN", 0, 1, &umr_bitfield_default }, + { "FORMAT", 2, 6, &umr_bitfield_default }, + { "NUMBER_TYPE", 8, 10, &umr_bitfield_default }, + { "COMP_SWAP", 11, 12, &umr_bitfield_default }, + { "FAST_CLEAR", 13, 13, &umr_bitfield_default }, + { "COMPRESSION", 14, 14, &umr_bitfield_default }, + { "BLEND_CLAMP", 15, 15, &umr_bitfield_default }, + { "BLEND_BYPASS", 16, 16, &umr_bitfield_default }, + { "SIMPLE_FLOAT", 17, 17, &umr_bitfield_default }, + { "ROUND_MODE", 18, 18, &umr_bitfield_default }, + { "BLEND_OPT_DONT_RD_DST", 20, 22, &umr_bitfield_default }, + { "BLEND_OPT_DISCARD_PIXEL", 23, 25, &umr_bitfield_default }, + { "FMASK_COMPRESSION_DISABLE", 26, 26, &umr_bitfield_default }, + { "FMASK_COMPRESS_1FRAG_ONLY", 27, 27, &umr_bitfield_default }, + { "DCC_ENABLE", 28, 28, &umr_bitfield_default }, + { "CMASK_ADDR_TYPE", 29, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR1_ATTRIB[] = { + { "MIP0_DEPTH", 0, 10, &umr_bitfield_default }, + { "META_LINEAR", 11, 11, &umr_bitfield_default }, + { "NUM_SAMPLES", 12, 14, &umr_bitfield_default }, + { "NUM_FRAGMENTS", 15, 16, &umr_bitfield_default }, + { "FORCE_DST_ALPHA_1", 17, 17, &umr_bitfield_default }, + { "COLOR_SW_MODE", 18, 22, &umr_bitfield_default }, + { "FMASK_SW_MODE", 23, 27, &umr_bitfield_default }, + { "RESOURCE_TYPE", 28, 29, &umr_bitfield_default }, + { "RB_ALIGNED", 30, 30, &umr_bitfield_default }, + { "PIPE_ALIGNED", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR1_DCC_CONTROL[] = { + { "OVERWRITE_COMBINER_DISABLE", 0, 0, &umr_bitfield_default }, + { "KEY_CLEAR_ENABLE", 1, 1, &umr_bitfield_default }, + { "MAX_UNCOMPRESSED_BLOCK_SIZE", 2, 3, &umr_bitfield_default }, + { "MIN_COMPRESSED_BLOCK_SIZE", 4, 4, &umr_bitfield_default }, + { "MAX_COMPRESSED_BLOCK_SIZE", 5, 6, &umr_bitfield_default }, + { "COLOR_TRANSFORM", 7, 8, &umr_bitfield_default }, + { "INDEPENDENT_64B_BLOCKS", 9, 9, &umr_bitfield_default }, + { "LOSSY_RGB_PRECISION", 10, 13, &umr_bitfield_default }, + { "LOSSY_ALPHA_PRECISION", 14, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR1_CMASK[] = { + { "BASE_256B", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR1_CMASK_BASE_EXT[] = { + { "BASE_256B", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR1_FMASK[] = { + { "BASE_256B", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR1_FMASK_BASE_EXT[] = { + { "BASE_256B", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR1_CLEAR_WORD0[] = { + { "CLEAR_WORD0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR1_CLEAR_WORD1[] = { + { "CLEAR_WORD1", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR1_DCC_BASE[] = { + { "BASE_256B", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR1_DCC_BASE_EXT[] = { + { "BASE_256B", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR2_BASE[] = { + { "BASE_256B", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR2_BASE_EXT[] = { + { "BASE_256B", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR2_ATTRIB2[] = { + { "MIP0_HEIGHT", 0, 13, &umr_bitfield_default }, + { "MIP0_WIDTH", 14, 27, &umr_bitfield_default }, + { "MAX_MIP", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR2_VIEW[] = { + { "SLICE_START", 0, 10, &umr_bitfield_default }, + { "SLICE_MAX", 13, 23, &umr_bitfield_default }, + { "MIP_LEVEL", 24, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR2_INFO[] = { + { "ENDIAN", 0, 1, &umr_bitfield_default }, + { "FORMAT", 2, 6, &umr_bitfield_default }, + { "NUMBER_TYPE", 8, 10, &umr_bitfield_default }, + { "COMP_SWAP", 11, 12, &umr_bitfield_default }, + { "FAST_CLEAR", 13, 13, &umr_bitfield_default }, + { "COMPRESSION", 14, 14, &umr_bitfield_default }, + { "BLEND_CLAMP", 15, 15, &umr_bitfield_default }, + { "BLEND_BYPASS", 16, 16, &umr_bitfield_default }, + { "SIMPLE_FLOAT", 17, 17, &umr_bitfield_default }, + { "ROUND_MODE", 18, 18, &umr_bitfield_default }, + { "BLEND_OPT_DONT_RD_DST", 20, 22, &umr_bitfield_default }, + { "BLEND_OPT_DISCARD_PIXEL", 23, 25, &umr_bitfield_default }, + { "FMASK_COMPRESSION_DISABLE", 26, 26, &umr_bitfield_default }, + { "FMASK_COMPRESS_1FRAG_ONLY", 27, 27, &umr_bitfield_default }, + { "DCC_ENABLE", 28, 28, &umr_bitfield_default }, + { "CMASK_ADDR_TYPE", 29, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR2_ATTRIB[] = { + { "MIP0_DEPTH", 0, 10, &umr_bitfield_default }, + { "META_LINEAR", 11, 11, &umr_bitfield_default }, + { "NUM_SAMPLES", 12, 14, &umr_bitfield_default }, + { "NUM_FRAGMENTS", 15, 16, &umr_bitfield_default }, + { "FORCE_DST_ALPHA_1", 17, 17, &umr_bitfield_default }, + { "COLOR_SW_MODE", 18, 22, &umr_bitfield_default }, + { "FMASK_SW_MODE", 23, 27, &umr_bitfield_default }, + { "RESOURCE_TYPE", 28, 29, &umr_bitfield_default }, + { "RB_ALIGNED", 30, 30, &umr_bitfield_default }, + { "PIPE_ALIGNED", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR2_DCC_CONTROL[] = { + { "OVERWRITE_COMBINER_DISABLE", 0, 0, &umr_bitfield_default }, + { "KEY_CLEAR_ENABLE", 1, 1, &umr_bitfield_default }, + { "MAX_UNCOMPRESSED_BLOCK_SIZE", 2, 3, &umr_bitfield_default }, + { "MIN_COMPRESSED_BLOCK_SIZE", 4, 4, &umr_bitfield_default }, + { "MAX_COMPRESSED_BLOCK_SIZE", 5, 6, &umr_bitfield_default }, + { "COLOR_TRANSFORM", 7, 8, &umr_bitfield_default }, + { "INDEPENDENT_64B_BLOCKS", 9, 9, &umr_bitfield_default }, + { "LOSSY_RGB_PRECISION", 10, 13, &umr_bitfield_default }, + { "LOSSY_ALPHA_PRECISION", 14, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR2_CMASK[] = { + { "BASE_256B", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR2_CMASK_BASE_EXT[] = { + { "BASE_256B", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR2_FMASK[] = { + { "BASE_256B", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR2_FMASK_BASE_EXT[] = { + { "BASE_256B", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR2_CLEAR_WORD0[] = { + { "CLEAR_WORD0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR2_CLEAR_WORD1[] = { + { "CLEAR_WORD1", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR2_DCC_BASE[] = { + { "BASE_256B", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR2_DCC_BASE_EXT[] = { + { "BASE_256B", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR3_BASE[] = { + { "BASE_256B", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR3_BASE_EXT[] = { + { "BASE_256B", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR3_ATTRIB2[] = { + { "MIP0_HEIGHT", 0, 13, &umr_bitfield_default }, + { "MIP0_WIDTH", 14, 27, &umr_bitfield_default }, + { "MAX_MIP", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR3_VIEW[] = { + { "SLICE_START", 0, 10, &umr_bitfield_default }, + { "SLICE_MAX", 13, 23, &umr_bitfield_default }, + { "MIP_LEVEL", 24, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR3_INFO[] = { + { "ENDIAN", 0, 1, &umr_bitfield_default }, + { "FORMAT", 2, 6, &umr_bitfield_default }, + { "NUMBER_TYPE", 8, 10, &umr_bitfield_default }, + { "COMP_SWAP", 11, 12, &umr_bitfield_default }, + { "FAST_CLEAR", 13, 13, &umr_bitfield_default }, + { "COMPRESSION", 14, 14, &umr_bitfield_default }, + { "BLEND_CLAMP", 15, 15, &umr_bitfield_default }, + { "BLEND_BYPASS", 16, 16, &umr_bitfield_default }, + { "SIMPLE_FLOAT", 17, 17, &umr_bitfield_default }, + { "ROUND_MODE", 18, 18, &umr_bitfield_default }, + { "BLEND_OPT_DONT_RD_DST", 20, 22, &umr_bitfield_default }, + { "BLEND_OPT_DISCARD_PIXEL", 23, 25, &umr_bitfield_default }, + { "FMASK_COMPRESSION_DISABLE", 26, 26, &umr_bitfield_default }, + { "FMASK_COMPRESS_1FRAG_ONLY", 27, 27, &umr_bitfield_default }, + { "DCC_ENABLE", 28, 28, &umr_bitfield_default }, + { "CMASK_ADDR_TYPE", 29, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR3_ATTRIB[] = { + { "MIP0_DEPTH", 0, 10, &umr_bitfield_default }, + { "META_LINEAR", 11, 11, &umr_bitfield_default }, + { "NUM_SAMPLES", 12, 14, &umr_bitfield_default }, + { "NUM_FRAGMENTS", 15, 16, &umr_bitfield_default }, + { "FORCE_DST_ALPHA_1", 17, 17, &umr_bitfield_default }, + { "COLOR_SW_MODE", 18, 22, &umr_bitfield_default }, + { "FMASK_SW_MODE", 23, 27, &umr_bitfield_default }, + { "RESOURCE_TYPE", 28, 29, &umr_bitfield_default }, + { "RB_ALIGNED", 30, 30, &umr_bitfield_default }, + { "PIPE_ALIGNED", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR3_DCC_CONTROL[] = { + { "OVERWRITE_COMBINER_DISABLE", 0, 0, &umr_bitfield_default }, + { "KEY_CLEAR_ENABLE", 1, 1, &umr_bitfield_default }, + { "MAX_UNCOMPRESSED_BLOCK_SIZE", 2, 3, &umr_bitfield_default }, + { "MIN_COMPRESSED_BLOCK_SIZE", 4, 4, &umr_bitfield_default }, + { "MAX_COMPRESSED_BLOCK_SIZE", 5, 6, &umr_bitfield_default }, + { "COLOR_TRANSFORM", 7, 8, &umr_bitfield_default }, + { "INDEPENDENT_64B_BLOCKS", 9, 9, &umr_bitfield_default }, + { "LOSSY_RGB_PRECISION", 10, 13, &umr_bitfield_default }, + { "LOSSY_ALPHA_PRECISION", 14, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR3_CMASK[] = { + { "BASE_256B", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR3_CMASK_BASE_EXT[] = { + { "BASE_256B", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR3_FMASK[] = { + { "BASE_256B", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR3_FMASK_BASE_EXT[] = { + { "BASE_256B", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR3_CLEAR_WORD0[] = { + { "CLEAR_WORD0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR3_CLEAR_WORD1[] = { + { "CLEAR_WORD1", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR3_DCC_BASE[] = { + { "BASE_256B", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR3_DCC_BASE_EXT[] = { + { "BASE_256B", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR4_BASE[] = { + { "BASE_256B", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR4_BASE_EXT[] = { + { "BASE_256B", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR4_ATTRIB2[] = { + { "MIP0_HEIGHT", 0, 13, &umr_bitfield_default }, + { "MIP0_WIDTH", 14, 27, &umr_bitfield_default }, + { "MAX_MIP", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR4_VIEW[] = { + { "SLICE_START", 0, 10, &umr_bitfield_default }, + { "SLICE_MAX", 13, 23, &umr_bitfield_default }, + { "MIP_LEVEL", 24, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR4_INFO[] = { + { "ENDIAN", 0, 1, &umr_bitfield_default }, + { "FORMAT", 2, 6, &umr_bitfield_default }, + { "NUMBER_TYPE", 8, 10, &umr_bitfield_default }, + { "COMP_SWAP", 11, 12, &umr_bitfield_default }, + { "FAST_CLEAR", 13, 13, &umr_bitfield_default }, + { "COMPRESSION", 14, 14, &umr_bitfield_default }, + { "BLEND_CLAMP", 15, 15, &umr_bitfield_default }, + { "BLEND_BYPASS", 16, 16, &umr_bitfield_default }, + { "SIMPLE_FLOAT", 17, 17, &umr_bitfield_default }, + { "ROUND_MODE", 18, 18, &umr_bitfield_default }, + { "BLEND_OPT_DONT_RD_DST", 20, 22, &umr_bitfield_default }, + { "BLEND_OPT_DISCARD_PIXEL", 23, 25, &umr_bitfield_default }, + { "FMASK_COMPRESSION_DISABLE", 26, 26, &umr_bitfield_default }, + { "FMASK_COMPRESS_1FRAG_ONLY", 27, 27, &umr_bitfield_default }, + { "DCC_ENABLE", 28, 28, &umr_bitfield_default }, + { "CMASK_ADDR_TYPE", 29, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR4_ATTRIB[] = { + { "MIP0_DEPTH", 0, 10, &umr_bitfield_default }, + { "META_LINEAR", 11, 11, &umr_bitfield_default }, + { "NUM_SAMPLES", 12, 14, &umr_bitfield_default }, + { "NUM_FRAGMENTS", 15, 16, &umr_bitfield_default }, + { "FORCE_DST_ALPHA_1", 17, 17, &umr_bitfield_default }, + { "COLOR_SW_MODE", 18, 22, &umr_bitfield_default }, + { "FMASK_SW_MODE", 23, 27, &umr_bitfield_default }, + { "RESOURCE_TYPE", 28, 29, &umr_bitfield_default }, + { "RB_ALIGNED", 30, 30, &umr_bitfield_default }, + { "PIPE_ALIGNED", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR4_DCC_CONTROL[] = { + { "OVERWRITE_COMBINER_DISABLE", 0, 0, &umr_bitfield_default }, + { "KEY_CLEAR_ENABLE", 1, 1, &umr_bitfield_default }, + { "MAX_UNCOMPRESSED_BLOCK_SIZE", 2, 3, &umr_bitfield_default }, + { "MIN_COMPRESSED_BLOCK_SIZE", 4, 4, &umr_bitfield_default }, + { "MAX_COMPRESSED_BLOCK_SIZE", 5, 6, &umr_bitfield_default }, + { "COLOR_TRANSFORM", 7, 8, &umr_bitfield_default }, + { "INDEPENDENT_64B_BLOCKS", 9, 9, &umr_bitfield_default }, + { "LOSSY_RGB_PRECISION", 10, 13, &umr_bitfield_default }, + { "LOSSY_ALPHA_PRECISION", 14, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR4_CMASK[] = { + { "BASE_256B", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR4_CMASK_BASE_EXT[] = { + { "BASE_256B", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR4_FMASK[] = { + { "BASE_256B", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR4_FMASK_BASE_EXT[] = { + { "BASE_256B", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR4_CLEAR_WORD0[] = { + { "CLEAR_WORD0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR4_CLEAR_WORD1[] = { + { "CLEAR_WORD1", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR4_DCC_BASE[] = { + { "BASE_256B", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR4_DCC_BASE_EXT[] = { + { "BASE_256B", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR5_BASE[] = { + { "BASE_256B", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR5_BASE_EXT[] = { + { "BASE_256B", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR5_ATTRIB2[] = { + { "MIP0_HEIGHT", 0, 13, &umr_bitfield_default }, + { "MIP0_WIDTH", 14, 27, &umr_bitfield_default }, + { "MAX_MIP", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR5_VIEW[] = { + { "SLICE_START", 0, 10, &umr_bitfield_default }, + { "SLICE_MAX", 13, 23, &umr_bitfield_default }, + { "MIP_LEVEL", 24, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR5_INFO[] = { + { "ENDIAN", 0, 1, &umr_bitfield_default }, + { "FORMAT", 2, 6, &umr_bitfield_default }, + { "NUMBER_TYPE", 8, 10, &umr_bitfield_default }, + { "COMP_SWAP", 11, 12, &umr_bitfield_default }, + { "FAST_CLEAR", 13, 13, &umr_bitfield_default }, + { "COMPRESSION", 14, 14, &umr_bitfield_default }, + { "BLEND_CLAMP", 15, 15, &umr_bitfield_default }, + { "BLEND_BYPASS", 16, 16, &umr_bitfield_default }, + { "SIMPLE_FLOAT", 17, 17, &umr_bitfield_default }, + { "ROUND_MODE", 18, 18, &umr_bitfield_default }, + { "BLEND_OPT_DONT_RD_DST", 20, 22, &umr_bitfield_default }, + { "BLEND_OPT_DISCARD_PIXEL", 23, 25, &umr_bitfield_default }, + { "FMASK_COMPRESSION_DISABLE", 26, 26, &umr_bitfield_default }, + { "FMASK_COMPRESS_1FRAG_ONLY", 27, 27, &umr_bitfield_default }, + { "DCC_ENABLE", 28, 28, &umr_bitfield_default }, + { "CMASK_ADDR_TYPE", 29, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR5_ATTRIB[] = { + { "MIP0_DEPTH", 0, 10, &umr_bitfield_default }, + { "META_LINEAR", 11, 11, &umr_bitfield_default }, + { "NUM_SAMPLES", 12, 14, &umr_bitfield_default }, + { "NUM_FRAGMENTS", 15, 16, &umr_bitfield_default }, + { "FORCE_DST_ALPHA_1", 17, 17, &umr_bitfield_default }, + { "COLOR_SW_MODE", 18, 22, &umr_bitfield_default }, + { "FMASK_SW_MODE", 23, 27, &umr_bitfield_default }, + { "RESOURCE_TYPE", 28, 29, &umr_bitfield_default }, + { "RB_ALIGNED", 30, 30, &umr_bitfield_default }, + { "PIPE_ALIGNED", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR5_DCC_CONTROL[] = { + { "OVERWRITE_COMBINER_DISABLE", 0, 0, &umr_bitfield_default }, + { "KEY_CLEAR_ENABLE", 1, 1, &umr_bitfield_default }, + { "MAX_UNCOMPRESSED_BLOCK_SIZE", 2, 3, &umr_bitfield_default }, + { "MIN_COMPRESSED_BLOCK_SIZE", 4, 4, &umr_bitfield_default }, + { "MAX_COMPRESSED_BLOCK_SIZE", 5, 6, &umr_bitfield_default }, + { "COLOR_TRANSFORM", 7, 8, &umr_bitfield_default }, + { "INDEPENDENT_64B_BLOCKS", 9, 9, &umr_bitfield_default }, + { "LOSSY_RGB_PRECISION", 10, 13, &umr_bitfield_default }, + { "LOSSY_ALPHA_PRECISION", 14, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR5_CMASK[] = { + { "BASE_256B", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR5_CMASK_BASE_EXT[] = { + { "BASE_256B", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR5_FMASK[] = { + { "BASE_256B", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR5_FMASK_BASE_EXT[] = { + { "BASE_256B", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR5_CLEAR_WORD0[] = { + { "CLEAR_WORD0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR5_CLEAR_WORD1[] = { + { "CLEAR_WORD1", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR5_DCC_BASE[] = { + { "BASE_256B", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR5_DCC_BASE_EXT[] = { + { "BASE_256B", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR6_BASE[] = { + { "BASE_256B", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR6_BASE_EXT[] = { + { "BASE_256B", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR6_ATTRIB2[] = { + { "MIP0_HEIGHT", 0, 13, &umr_bitfield_default }, + { "MIP0_WIDTH", 14, 27, &umr_bitfield_default }, + { "MAX_MIP", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR6_VIEW[] = { + { "SLICE_START", 0, 10, &umr_bitfield_default }, + { "SLICE_MAX", 13, 23, &umr_bitfield_default }, + { "MIP_LEVEL", 24, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR6_INFO[] = { + { "ENDIAN", 0, 1, &umr_bitfield_default }, + { "FORMAT", 2, 6, &umr_bitfield_default }, + { "NUMBER_TYPE", 8, 10, &umr_bitfield_default }, + { "COMP_SWAP", 11, 12, &umr_bitfield_default }, + { "FAST_CLEAR", 13, 13, &umr_bitfield_default }, + { "COMPRESSION", 14, 14, &umr_bitfield_default }, + { "BLEND_CLAMP", 15, 15, &umr_bitfield_default }, + { "BLEND_BYPASS", 16, 16, &umr_bitfield_default }, + { "SIMPLE_FLOAT", 17, 17, &umr_bitfield_default }, + { "ROUND_MODE", 18, 18, &umr_bitfield_default }, + { "BLEND_OPT_DONT_RD_DST", 20, 22, &umr_bitfield_default }, + { "BLEND_OPT_DISCARD_PIXEL", 23, 25, &umr_bitfield_default }, + { "FMASK_COMPRESSION_DISABLE", 26, 26, &umr_bitfield_default }, + { "FMASK_COMPRESS_1FRAG_ONLY", 27, 27, &umr_bitfield_default }, + { "DCC_ENABLE", 28, 28, &umr_bitfield_default }, + { "CMASK_ADDR_TYPE", 29, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR6_ATTRIB[] = { + { "MIP0_DEPTH", 0, 10, &umr_bitfield_default }, + { "META_LINEAR", 11, 11, &umr_bitfield_default }, + { "NUM_SAMPLES", 12, 14, &umr_bitfield_default }, + { "NUM_FRAGMENTS", 15, 16, &umr_bitfield_default }, + { "FORCE_DST_ALPHA_1", 17, 17, &umr_bitfield_default }, + { "COLOR_SW_MODE", 18, 22, &umr_bitfield_default }, + { "FMASK_SW_MODE", 23, 27, &umr_bitfield_default }, + { "RESOURCE_TYPE", 28, 29, &umr_bitfield_default }, + { "RB_ALIGNED", 30, 30, &umr_bitfield_default }, + { "PIPE_ALIGNED", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR6_DCC_CONTROL[] = { + { "OVERWRITE_COMBINER_DISABLE", 0, 0, &umr_bitfield_default }, + { "KEY_CLEAR_ENABLE", 1, 1, &umr_bitfield_default }, + { "MAX_UNCOMPRESSED_BLOCK_SIZE", 2, 3, &umr_bitfield_default }, + { "MIN_COMPRESSED_BLOCK_SIZE", 4, 4, &umr_bitfield_default }, + { "MAX_COMPRESSED_BLOCK_SIZE", 5, 6, &umr_bitfield_default }, + { "COLOR_TRANSFORM", 7, 8, &umr_bitfield_default }, + { "INDEPENDENT_64B_BLOCKS", 9, 9, &umr_bitfield_default }, + { "LOSSY_RGB_PRECISION", 10, 13, &umr_bitfield_default }, + { "LOSSY_ALPHA_PRECISION", 14, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR6_CMASK[] = { + { "BASE_256B", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR6_CMASK_BASE_EXT[] = { + { "BASE_256B", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR6_FMASK[] = { + { "BASE_256B", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR6_FMASK_BASE_EXT[] = { + { "BASE_256B", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR6_CLEAR_WORD0[] = { + { "CLEAR_WORD0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR6_CLEAR_WORD1[] = { + { "CLEAR_WORD1", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR6_DCC_BASE[] = { + { "BASE_256B", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR6_DCC_BASE_EXT[] = { + { "BASE_256B", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR7_BASE[] = { + { "BASE_256B", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR7_BASE_EXT[] = { + { "BASE_256B", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR7_ATTRIB2[] = { + { "MIP0_HEIGHT", 0, 13, &umr_bitfield_default }, + { "MIP0_WIDTH", 14, 27, &umr_bitfield_default }, + { "MAX_MIP", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR7_VIEW[] = { + { "SLICE_START", 0, 10, &umr_bitfield_default }, + { "SLICE_MAX", 13, 23, &umr_bitfield_default }, + { "MIP_LEVEL", 24, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR7_INFO[] = { + { "ENDIAN", 0, 1, &umr_bitfield_default }, + { "FORMAT", 2, 6, &umr_bitfield_default }, + { "NUMBER_TYPE", 8, 10, &umr_bitfield_default }, + { "COMP_SWAP", 11, 12, &umr_bitfield_default }, + { "FAST_CLEAR", 13, 13, &umr_bitfield_default }, + { "COMPRESSION", 14, 14, &umr_bitfield_default }, + { "BLEND_CLAMP", 15, 15, &umr_bitfield_default }, + { "BLEND_BYPASS", 16, 16, &umr_bitfield_default }, + { "SIMPLE_FLOAT", 17, 17, &umr_bitfield_default }, + { "ROUND_MODE", 18, 18, &umr_bitfield_default }, + { "BLEND_OPT_DONT_RD_DST", 20, 22, &umr_bitfield_default }, + { "BLEND_OPT_DISCARD_PIXEL", 23, 25, &umr_bitfield_default }, + { "FMASK_COMPRESSION_DISABLE", 26, 26, &umr_bitfield_default }, + { "FMASK_COMPRESS_1FRAG_ONLY", 27, 27, &umr_bitfield_default }, + { "DCC_ENABLE", 28, 28, &umr_bitfield_default }, + { "CMASK_ADDR_TYPE", 29, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR7_ATTRIB[] = { + { "MIP0_DEPTH", 0, 10, &umr_bitfield_default }, + { "META_LINEAR", 11, 11, &umr_bitfield_default }, + { "NUM_SAMPLES", 12, 14, &umr_bitfield_default }, + { "NUM_FRAGMENTS", 15, 16, &umr_bitfield_default }, + { "FORCE_DST_ALPHA_1", 17, 17, &umr_bitfield_default }, + { "COLOR_SW_MODE", 18, 22, &umr_bitfield_default }, + { "FMASK_SW_MODE", 23, 27, &umr_bitfield_default }, + { "RESOURCE_TYPE", 28, 29, &umr_bitfield_default }, + { "RB_ALIGNED", 30, 30, &umr_bitfield_default }, + { "PIPE_ALIGNED", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR7_DCC_CONTROL[] = { + { "OVERWRITE_COMBINER_DISABLE", 0, 0, &umr_bitfield_default }, + { "KEY_CLEAR_ENABLE", 1, 1, &umr_bitfield_default }, + { "MAX_UNCOMPRESSED_BLOCK_SIZE", 2, 3, &umr_bitfield_default }, + { "MIN_COMPRESSED_BLOCK_SIZE", 4, 4, &umr_bitfield_default }, + { "MAX_COMPRESSED_BLOCK_SIZE", 5, 6, &umr_bitfield_default }, + { "COLOR_TRANSFORM", 7, 8, &umr_bitfield_default }, + { "INDEPENDENT_64B_BLOCKS", 9, 9, &umr_bitfield_default }, + { "LOSSY_RGB_PRECISION", 10, 13, &umr_bitfield_default }, + { "LOSSY_ALPHA_PRECISION", 14, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR7_CMASK[] = { + { "BASE_256B", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR7_CMASK_BASE_EXT[] = { + { "BASE_256B", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR7_FMASK[] = { + { "BASE_256B", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR7_FMASK_BASE_EXT[] = { + { "BASE_256B", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR7_CLEAR_WORD0[] = { + { "CLEAR_WORD0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR7_CLEAR_WORD1[] = { + { "CLEAR_WORD1", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR7_DCC_BASE[] = { + { "BASE_256B", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_COLOR7_DCC_BASE_EXT[] = { + { "BASE_256B", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_EOP_DONE_ADDR_LO[] = { + { "ADDR_LO", 2, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_EOP_DONE_ADDR_HI[] = { + { "ADDR_HI", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_EOP_DONE_DATA_LO[] = { + { "DATA_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_EOP_DONE_DATA_HI[] = { + { "DATA_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_EOP_LAST_FENCE_LO[] = { + { "LAST_FENCE_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_EOP_LAST_FENCE_HI[] = { + { "LAST_FENCE_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_STREAM_OUT_ADDR_LO[] = { + { "STREAM_OUT_ADDR_LO", 2, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_STREAM_OUT_ADDR_HI[] = { + { "STREAM_OUT_ADDR_HI", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_NUM_PRIM_WRITTEN_COUNT0_LO[] = { + { "NUM_PRIM_WRITTEN_CNT0_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_NUM_PRIM_WRITTEN_COUNT0_HI[] = { + { "NUM_PRIM_WRITTEN_CNT0_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_NUM_PRIM_NEEDED_COUNT0_LO[] = { + { "NUM_PRIM_NEEDED_CNT0_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_NUM_PRIM_NEEDED_COUNT0_HI[] = { + { "NUM_PRIM_NEEDED_CNT0_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_NUM_PRIM_WRITTEN_COUNT1_LO[] = { + { "NUM_PRIM_WRITTEN_CNT1_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_NUM_PRIM_WRITTEN_COUNT1_HI[] = { + { "NUM_PRIM_WRITTEN_CNT1_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_NUM_PRIM_NEEDED_COUNT1_LO[] = { + { "NUM_PRIM_NEEDED_CNT1_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_NUM_PRIM_NEEDED_COUNT1_HI[] = { + { "NUM_PRIM_NEEDED_CNT1_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_NUM_PRIM_WRITTEN_COUNT2_LO[] = { + { "NUM_PRIM_WRITTEN_CNT2_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_NUM_PRIM_WRITTEN_COUNT2_HI[] = { + { "NUM_PRIM_WRITTEN_CNT2_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_NUM_PRIM_NEEDED_COUNT2_LO[] = { + { "NUM_PRIM_NEEDED_CNT2_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_NUM_PRIM_NEEDED_COUNT2_HI[] = { + { "NUM_PRIM_NEEDED_CNT2_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_NUM_PRIM_WRITTEN_COUNT3_LO[] = { + { "NUM_PRIM_WRITTEN_CNT3_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_NUM_PRIM_WRITTEN_COUNT3_HI[] = { + { "NUM_PRIM_WRITTEN_CNT3_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_NUM_PRIM_NEEDED_COUNT3_LO[] = { + { "NUM_PRIM_NEEDED_CNT3_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_NUM_PRIM_NEEDED_COUNT3_HI[] = { + { "NUM_PRIM_NEEDED_CNT3_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_PIPE_STATS_ADDR_LO[] = { + { "PIPE_STATS_ADDR_LO", 2, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_PIPE_STATS_ADDR_HI[] = { + { "PIPE_STATS_ADDR_HI", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_VGT_IAVERT_COUNT_LO[] = { + { "IAVERT_COUNT_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_VGT_IAVERT_COUNT_HI[] = { + { "IAVERT_COUNT_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_VGT_IAPRIM_COUNT_LO[] = { + { "IAPRIM_COUNT_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_VGT_IAPRIM_COUNT_HI[] = { + { "IAPRIM_COUNT_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_VGT_GSPRIM_COUNT_LO[] = { + { "GSPRIM_COUNT_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_VGT_GSPRIM_COUNT_HI[] = { + { "GSPRIM_COUNT_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_VGT_VSINVOC_COUNT_LO[] = { + { "VSINVOC_COUNT_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_VGT_VSINVOC_COUNT_HI[] = { + { "VSINVOC_COUNT_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_VGT_GSINVOC_COUNT_LO[] = { + { "GSINVOC_COUNT_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_VGT_GSINVOC_COUNT_HI[] = { + { "GSINVOC_COUNT_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_VGT_HSINVOC_COUNT_LO[] = { + { "HSINVOC_COUNT_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_VGT_HSINVOC_COUNT_HI[] = { + { "HSINVOC_COUNT_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_VGT_DSINVOC_COUNT_LO[] = { + { "DSINVOC_COUNT_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_VGT_DSINVOC_COUNT_HI[] = { + { "DSINVOC_COUNT_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_PA_CINVOC_COUNT_LO[] = { + { "CINVOC_COUNT_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_PA_CINVOC_COUNT_HI[] = { + { "CINVOC_COUNT_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_PA_CPRIM_COUNT_LO[] = { + { "CPRIM_COUNT_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_PA_CPRIM_COUNT_HI[] = { + { "CPRIM_COUNT_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_SC_PSINVOC_COUNT0_LO[] = { + { "PSINVOC_COUNT0_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_SC_PSINVOC_COUNT0_HI[] = { + { "PSINVOC_COUNT0_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_SC_PSINVOC_COUNT1_LO[] = { + { "OBSOLETE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_SC_PSINVOC_COUNT1_HI[] = { + { "OBSOLETE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_VGT_CSINVOC_COUNT_LO[] = { + { "CSINVOC_COUNT_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_VGT_CSINVOC_COUNT_HI[] = { + { "CSINVOC_COUNT_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_PIPE_STATS_CONTROL[] = { + { "CACHE_POLICY", 25, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_STREAM_OUT_CONTROL[] = { + { "CACHE_POLICY", 25, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_STRMOUT_CNTL[] = { + { "OFFSET_UPDATE_DONE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSCRATCH_REG0[] = { + { "SCRATCH_REG0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSCRATCH_REG1[] = { + { "SCRATCH_REG1", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSCRATCH_REG2[] = { + { "SCRATCH_REG2", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSCRATCH_REG3[] = { + { "SCRATCH_REG3", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSCRATCH_REG4[] = { + { "SCRATCH_REG4", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSCRATCH_REG5[] = { + { "SCRATCH_REG5", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSCRATCH_REG6[] = { + { "SCRATCH_REG6", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSCRATCH_REG7[] = { + { "SCRATCH_REG7", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_APPEND_DATA_HI[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_APPEND_LAST_CS_FENCE_HI[] = { + { "LAST_FENCE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_APPEND_LAST_PS_FENCE_HI[] = { + { "LAST_FENCE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSCRATCH_UMSK[] = { + { "OBSOLETE_UMSK", 0, 7, &umr_bitfield_default }, + { "OBSOLETE_SWAP", 16, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSCRATCH_ADDR[] = { + { "OBSOLETE_ADDR", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_PFP_ATOMIC_PREOP_LO[] = { + { "ATOMIC_PREOP_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_PFP_ATOMIC_PREOP_HI[] = { + { "ATOMIC_PREOP_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_PFP_GDS_ATOMIC0_PREOP_LO[] = { + { "GDS_ATOMIC0_PREOP_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_PFP_GDS_ATOMIC0_PREOP_HI[] = { + { "GDS_ATOMIC0_PREOP_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_PFP_GDS_ATOMIC1_PREOP_LO[] = { + { "GDS_ATOMIC1_PREOP_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_PFP_GDS_ATOMIC1_PREOP_HI[] = { + { "GDS_ATOMIC1_PREOP_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_APPEND_ADDR_LO[] = { + { "MEM_ADDR_LO", 2, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_APPEND_ADDR_HI[] = { + { "MEM_ADDR_HI", 0, 15, &umr_bitfield_default }, + { "CS_PS_SEL", 16, 16, &umr_bitfield_default }, + { "CACHE_POLICY", 25, 25, &umr_bitfield_default }, + { "COMMAND", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_APPEND_DATA_LO[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_APPEND_LAST_CS_FENCE_LO[] = { + { "LAST_FENCE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_APPEND_LAST_PS_FENCE_LO[] = { + { "LAST_FENCE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ATOMIC_PREOP_LO[] = { + { "ATOMIC_PREOP_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ME_ATOMIC_PREOP_LO[] = { + { "ATOMIC_PREOP_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ATOMIC_PREOP_HI[] = { + { "ATOMIC_PREOP_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ME_ATOMIC_PREOP_HI[] = { + { "ATOMIC_PREOP_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_GDS_ATOMIC0_PREOP_LO[] = { + { "GDS_ATOMIC0_PREOP_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ME_GDS_ATOMIC0_PREOP_LO[] = { + { "GDS_ATOMIC0_PREOP_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_GDS_ATOMIC0_PREOP_HI[] = { + { "GDS_ATOMIC0_PREOP_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ME_GDS_ATOMIC0_PREOP_HI[] = { + { "GDS_ATOMIC0_PREOP_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_GDS_ATOMIC1_PREOP_LO[] = { + { "GDS_ATOMIC1_PREOP_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ME_GDS_ATOMIC1_PREOP_LO[] = { + { "GDS_ATOMIC1_PREOP_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_GDS_ATOMIC1_PREOP_HI[] = { + { "GDS_ATOMIC1_PREOP_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ME_GDS_ATOMIC1_PREOP_HI[] = { + { "GDS_ATOMIC1_PREOP_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ME_MC_WADDR_LO[] = { + { "ME_MC_WADDR_LO", 2, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ME_MC_WADDR_HI[] = { + { "ME_MC_WADDR_HI", 0, 15, &umr_bitfield_default }, + { "CACHE_POLICY", 22, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ME_MC_WDATA_LO[] = { + { "ME_MC_WDATA_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ME_MC_WDATA_HI[] = { + { "ME_MC_WDATA_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ME_MC_RADDR_LO[] = { + { "ME_MC_RADDR_LO", 2, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ME_MC_RADDR_HI[] = { + { "ME_MC_RADDR_HI", 0, 15, &umr_bitfield_default }, + { "CACHE_POLICY", 22, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_SEM_WAIT_TIMER[] = { + { "SEM_WAIT_TIMER", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_SIG_SEM_ADDR_LO[] = { + { "SEM_ADDR_SWAP", 0, 1, &umr_bitfield_default }, + { "SEM_ADDR_LO", 3, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_SIG_SEM_ADDR_HI[] = { + { "SEM_ADDR_HI", 0, 15, &umr_bitfield_default }, + { "SEM_USE_MAILBOX", 16, 16, &umr_bitfield_default }, + { "SEM_SIGNAL_TYPE", 20, 20, &umr_bitfield_default }, + { "SEM_CLIENT_CODE", 24, 25, &umr_bitfield_default }, + { "SEM_SELECT", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_WAIT_REG_MEM_TIMEOUT[] = { + { "WAIT_REG_MEM_TIMEOUT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_WAIT_SEM_ADDR_LO[] = { + { "SEM_ADDR_SWAP", 0, 1, &umr_bitfield_default }, + { "SEM_ADDR_LO", 3, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_WAIT_SEM_ADDR_HI[] = { + { "SEM_ADDR_HI", 0, 15, &umr_bitfield_default }, + { "SEM_USE_MAILBOX", 16, 16, &umr_bitfield_default }, + { "SEM_SIGNAL_TYPE", 20, 20, &umr_bitfield_default }, + { "SEM_CLIENT_CODE", 24, 25, &umr_bitfield_default }, + { "SEM_SELECT", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_DMA_PFP_CONTROL[] = { + { "MEMLOG_CLEAR", 10, 10, &umr_bitfield_default }, + { "SRC_CACHE_POLICY", 13, 13, &umr_bitfield_default }, + { "DST_SELECT", 20, 21, &umr_bitfield_default }, + { "DST_CACHE_POLICY", 25, 25, &umr_bitfield_default }, + { "SRC_SELECT", 29, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_DMA_ME_CONTROL[] = { + { "MEMLOG_CLEAR", 10, 10, &umr_bitfield_default }, + { "SRC_CACHE_POLICY", 13, 13, &umr_bitfield_default }, + { "DST_SELECT", 20, 21, &umr_bitfield_default }, + { "DST_CACHE_POLICY", 25, 25, &umr_bitfield_default }, + { "SRC_SELECT", 29, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_COHER_BASE_HI[] = { + { "COHER_BASE_HI_256B", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_COHER_START_DELAY[] = { + { "START_DELAY_COUNT", 0, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_COHER_CNTL[] = { + { "TC_NC_ACTION_ENA", 3, 3, &umr_bitfield_default }, + { "TC_WC_ACTION_ENA", 4, 4, &umr_bitfield_default }, + { "TC_INV_METADATA_ACTION_ENA", 5, 5, &umr_bitfield_default }, + { "TCL1_VOL_ACTION_ENA", 15, 15, &umr_bitfield_default }, + { "TC_WB_ACTION_ENA", 18, 18, &umr_bitfield_default }, + { "TCL1_ACTION_ENA", 22, 22, &umr_bitfield_default }, + { "TC_ACTION_ENA", 23, 23, &umr_bitfield_default }, + { "CB_ACTION_ENA", 25, 25, &umr_bitfield_default }, + { "DB_ACTION_ENA", 26, 26, &umr_bitfield_default }, + { "SH_KCACHE_ACTION_ENA", 27, 27, &umr_bitfield_default }, + { "SH_KCACHE_VOL_ACTION_ENA", 28, 28, &umr_bitfield_default }, + { "SH_ICACHE_ACTION_ENA", 29, 29, &umr_bitfield_default }, + { "SH_KCACHE_WB_ACTION_ENA", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_COHER_SIZE[] = { + { "COHER_SIZE_256B", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_COHER_BASE[] = { + { "COHER_BASE_256B", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_COHER_STATUS[] = { + { "MEID", 24, 25, &umr_bitfield_default }, + { "STATUS", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_DMA_ME_SRC_ADDR[] = { + { "SRC_ADDR", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_DMA_ME_SRC_ADDR_HI[] = { + { "SRC_ADDR_HI", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_DMA_ME_DST_ADDR[] = { + { "DST_ADDR", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_DMA_ME_DST_ADDR_HI[] = { + { "DST_ADDR_HI", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_DMA_ME_COMMAND[] = { + { "BYTE_COUNT", 0, 25, &umr_bitfield_default }, + { "SAS", 26, 26, &umr_bitfield_default }, + { "DAS", 27, 27, &umr_bitfield_default }, + { "SAIC", 28, 28, &umr_bitfield_default }, + { "DAIC", 29, 29, &umr_bitfield_default }, + { "RAW_WAIT", 30, 30, &umr_bitfield_default }, + { "DIS_WC", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_DMA_PFP_SRC_ADDR[] = { + { "SRC_ADDR", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_DMA_PFP_SRC_ADDR_HI[] = { + { "SRC_ADDR_HI", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_DMA_PFP_DST_ADDR[] = { + { "DST_ADDR", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_DMA_PFP_DST_ADDR_HI[] = { + { "DST_ADDR_HI", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_DMA_PFP_COMMAND[] = { + { "BYTE_COUNT", 0, 25, &umr_bitfield_default }, + { "SAS", 26, 26, &umr_bitfield_default }, + { "DAS", 27, 27, &umr_bitfield_default }, + { "SAIC", 28, 28, &umr_bitfield_default }, + { "DAIC", 29, 29, &umr_bitfield_default }, + { "RAW_WAIT", 30, 30, &umr_bitfield_default }, + { "DIS_WC", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_DMA_CNTL[] = { + { "UTCL1_FAULT_CONTROL", 0, 0, &umr_bitfield_default }, + { "MIN_AVAILSZ", 4, 5, &umr_bitfield_default }, + { "BUFFER_DEPTH", 16, 19, &umr_bitfield_default }, + { "PIO_FIFO_EMPTY", 28, 28, &umr_bitfield_default }, + { "PIO_FIFO_FULL", 29, 29, &umr_bitfield_default }, + { "PIO_COUNT", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_DMA_READ_TAGS[] = { + { "DMA_READ_TAG", 0, 25, &umr_bitfield_default }, + { "DMA_READ_TAG_VALID", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_COHER_SIZE_HI[] = { + { "COHER_SIZE_HI_256B", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_PFP_IB_CONTROL[] = { + { "IB_EN", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_PFP_LOAD_CONTROL[] = { + { "CONFIG_REG_EN", 0, 0, &umr_bitfield_default }, + { "CNTX_REG_EN", 1, 1, &umr_bitfield_default }, + { "SH_GFX_REG_EN", 16, 16, &umr_bitfield_default }, + { "SH_CS_REG_EN", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_SCRATCH_INDEX[] = { + { "SCRATCH_INDEX", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_SCRATCH_DATA[] = { + { "SCRATCH_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_RB_OFFSET[] = { + { "RB_OFFSET", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_IB1_OFFSET[] = { + { "IB1_OFFSET", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_IB2_OFFSET[] = { + { "IB2_OFFSET", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_IB1_PREAMBLE_BEGIN[] = { + { "IB1_PREAMBLE_BEGIN", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_IB1_PREAMBLE_END[] = { + { "IB1_PREAMBLE_END", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_IB2_PREAMBLE_BEGIN[] = { + { "IB2_PREAMBLE_BEGIN", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_IB2_PREAMBLE_END[] = { + { "IB2_PREAMBLE_END", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_CE_IB1_OFFSET[] = { + { "IB1_OFFSET", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_CE_IB2_OFFSET[] = { + { "IB2_OFFSET", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_CE_COUNTER[] = { + { "CONST_ENGINE_COUNT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_CE_RB_OFFSET[] = { + { "RB_OFFSET", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_CE_INIT_CMD_BUFSZ[] = { + { "INIT_CMD_REQSZ", 0, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_CE_IB1_CMD_BUFSZ[] = { + { "IB1_CMD_REQSZ", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_CE_IB2_CMD_BUFSZ[] = { + { "IB2_CMD_REQSZ", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_IB1_CMD_BUFSZ[] = { + { "IB1_CMD_REQSZ", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_IB2_CMD_BUFSZ[] = { + { "IB2_CMD_REQSZ", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ST_CMD_BUFSZ[] = { + { "ST_CMD_REQSZ", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_CE_INIT_BASE_LO[] = { + { "INIT_BASE_LO", 5, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_CE_INIT_BASE_HI[] = { + { "INIT_BASE_HI", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_CE_INIT_BUFSZ[] = { + { "INIT_BUFSZ", 0, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_CE_IB1_BASE_LO[] = { + { "IB1_BASE_LO", 2, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_CE_IB1_BASE_HI[] = { + { "IB1_BASE_HI", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_CE_IB1_BUFSZ[] = { + { "IB1_BUFSZ", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_CE_IB2_BASE_LO[] = { + { "IB2_BASE_LO", 2, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_CE_IB2_BASE_HI[] = { + { "IB2_BASE_HI", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_CE_IB2_BUFSZ[] = { + { "IB2_BUFSZ", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_IB1_BASE_LO[] = { + { "IB1_BASE_LO", 2, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_IB1_BASE_HI[] = { + { "IB1_BASE_HI", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_IB1_BUFSZ[] = { + { "IB1_BUFSZ", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_IB2_BASE_LO[] = { + { "IB2_BASE_LO", 2, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_IB2_BASE_HI[] = { + { "IB2_BASE_HI", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_IB2_BUFSZ[] = { + { "IB2_BUFSZ", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ST_BASE_LO[] = { + { "ST_BASE_LO", 2, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ST_BASE_HI[] = { + { "ST_BASE_HI", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ST_BUFSZ[] = { + { "ST_BUFSZ", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_EOP_DONE_EVENT_CNTL[] = { + { "WBINV_TC_OP", 0, 6, &umr_bitfield_default }, + { "WBINV_ACTION_ENA", 12, 17, &umr_bitfield_default }, + { "CACHE_POLICY", 25, 25, &umr_bitfield_default }, + { "EXECUTE", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_EOP_DONE_DATA_CNTL[] = { + { "DST_SEL", 16, 17, &umr_bitfield_default }, + { "INT_SEL", 24, 26, &umr_bitfield_default }, + { "DATA_SEL", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_EOP_DONE_CNTX_ID[] = { + { "CNTX_ID", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_PFP_COMPLETION_STATUS[] = { + { "STATUS", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_CE_COMPLETION_STATUS[] = { + { "STATUS", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_PRED_NOT_VISIBLE[] = { + { "NOT_VISIBLE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_PFP_METADATA_BASE_ADDR[] = { + { "ADDR_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_PFP_METADATA_BASE_ADDR_HI[] = { + { "ADDR_HI", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_CE_METADATA_BASE_ADDR[] = { + { "ADDR_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_CE_METADATA_BASE_ADDR_HI[] = { + { "ADDR_HI", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_DRAW_INDX_INDR_ADDR[] = { + { "ADDR_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_DRAW_INDX_INDR_ADDR_HI[] = { + { "ADDR_HI", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_DISPATCH_INDR_ADDR[] = { + { "ADDR_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_DISPATCH_INDR_ADDR_HI[] = { + { "ADDR_HI", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_INDEX_BASE_ADDR[] = { + { "ADDR_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_INDEX_BASE_ADDR_HI[] = { + { "ADDR_HI", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_INDEX_TYPE[] = { + { "INDEX_TYPE", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_GDS_BKUP_ADDR[] = { + { "ADDR_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_GDS_BKUP_ADDR_HI[] = { + { "ADDR_HI", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_SAMPLE_STATUS[] = { + { "Z_PASS_ACITVE", 0, 0, &umr_bitfield_default }, + { "STREAMOUT_ACTIVE", 1, 1, &umr_bitfield_default }, + { "PIPELINE_ACTIVE", 2, 2, &umr_bitfield_default }, + { "STIPPLE_ACTIVE", 3, 3, &umr_bitfield_default }, + { "VGT_BUFFERS_ACTIVE", 4, 4, &umr_bitfield_default }, + { "SCREEN_EXT_ACTIVE", 5, 5, &umr_bitfield_default }, + { "DRAW_INDIRECT_ACTIVE", 6, 6, &umr_bitfield_default }, + { "DISP_INDIRECT_ACTIVE", 7, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ME_COHER_CNTL[] = { + { "DEST_BASE_0_ENA", 0, 0, &umr_bitfield_default }, + { "DEST_BASE_1_ENA", 1, 1, &umr_bitfield_default }, + { "CB0_DEST_BASE_ENA", 6, 6, &umr_bitfield_default }, + { "CB1_DEST_BASE_ENA", 7, 7, &umr_bitfield_default }, + { "CB2_DEST_BASE_ENA", 8, 8, &umr_bitfield_default }, + { "CB3_DEST_BASE_ENA", 9, 9, &umr_bitfield_default }, + { "CB4_DEST_BASE_ENA", 10, 10, &umr_bitfield_default }, + { "CB5_DEST_BASE_ENA", 11, 11, &umr_bitfield_default }, + { "CB6_DEST_BASE_ENA", 12, 12, &umr_bitfield_default }, + { "CB7_DEST_BASE_ENA", 13, 13, &umr_bitfield_default }, + { "DB_DEST_BASE_ENA", 14, 14, &umr_bitfield_default }, + { "DEST_BASE_2_ENA", 19, 19, &umr_bitfield_default }, + { "DEST_BASE_3_ENA", 21, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ME_COHER_SIZE[] = { + { "COHER_SIZE_256B", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ME_COHER_SIZE_HI[] = { + { "COHER_SIZE_HI_256B", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ME_COHER_BASE[] = { + { "COHER_BASE_256B", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ME_COHER_BASE_HI[] = { + { "COHER_BASE_HI_256B", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ME_COHER_STATUS[] = { + { "MATCHING_GFX_CNTX", 0, 7, &umr_bitfield_default }, + { "STATUS", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPM_PERF_COUNT_0[] = { + { "FEATURE_SEL", 0, 3, &umr_bitfield_default }, + { "SE_INDEX", 4, 7, &umr_bitfield_default }, + { "SH_INDEX", 8, 11, &umr_bitfield_default }, + { "CU_INDEX", 12, 15, &umr_bitfield_default }, + { "EVENT_SEL", 16, 17, &umr_bitfield_default }, + { "UNUSED", 18, 19, &umr_bitfield_default }, + { "ENABLE", 20, 20, &umr_bitfield_default }, + { "RESERVED", 21, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPM_PERF_COUNT_1[] = { + { "FEATURE_SEL", 0, 3, &umr_bitfield_default }, + { "SE_INDEX", 4, 7, &umr_bitfield_default }, + { "SH_INDEX", 8, 11, &umr_bitfield_default }, + { "CU_INDEX", 12, 15, &umr_bitfield_default }, + { "EVENT_SEL", 16, 17, &umr_bitfield_default }, + { "UNUSED", 18, 19, &umr_bitfield_default }, + { "ENABLE", 20, 20, &umr_bitfield_default }, + { "RESERVED", 21, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRBM_GFX_INDEX[] = { + { "INSTANCE_INDEX", 0, 7, &umr_bitfield_default }, + { "SH_INDEX", 8, 15, &umr_bitfield_default }, + { "SE_INDEX", 16, 23, &umr_bitfield_default }, + { "SH_BROADCAST_WRITES", 29, 29, &umr_bitfield_default }, + { "INSTANCE_BROADCAST_WRITES", 30, 30, &umr_bitfield_default }, + { "SE_BROADCAST_WRITES", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_GSVS_RING_SIZE[] = { + { "MEM_SIZE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_PRIMITIVE_TYPE[] = { + { "PRIM_TYPE", 0, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_INDEX_TYPE[] = { + { "INDEX_TYPE", 0, 1, &umr_bitfield_default }, + { "PRIMGEN_EN", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0[] = { + { "SIZE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1[] = { + { "SIZE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2[] = { + { "SIZE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3[] = { + { "SIZE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_MAX_VTX_INDX[] = { + { "MAX_INDX", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_MIN_VTX_INDX[] = { + { "MIN_INDX", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_INDX_OFFSET[] = { + { "INDX_OFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_MULTI_PRIM_IB_RESET_EN[] = { + { "RESET_EN", 0, 0, &umr_bitfield_default }, + { "MATCH_ALL_BITS", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_NUM_INDICES[] = { + { "NUM_INDICES", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_NUM_INSTANCES[] = { + { "NUM_INSTANCES", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_TF_RING_SIZE[] = { + { "SIZE", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_HS_OFFCHIP_PARAM[] = { + { "OFFCHIP_BUFFERING", 0, 8, &umr_bitfield_default }, + { "OFFCHIP_GRANULARITY", 9, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_TF_MEMORY_BASE[] = { + { "BASE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_TF_MEMORY_BASE_HI[] = { + { "BASE_HI", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWD_POS_BUF_BASE[] = { + { "BASE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWD_POS_BUF_BASE_HI[] = { + { "BASE_HI", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWD_CNTL_SB_BUF_BASE[] = { + { "BASE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWD_CNTL_SB_BUF_BASE_HI[] = { + { "BASE_HI", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWD_INDEX_BUF_BASE[] = { + { "BASE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWD_INDEX_BUF_BASE_HI[] = { + { "BASE_HI", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIA_MULTI_VGT_PARAM[] = { + { "PRIMGROUP_SIZE", 0, 15, &umr_bitfield_default }, + { "PARTIAL_VS_WAVE_ON", 16, 16, &umr_bitfield_default }, + { "SWITCH_ON_EOP", 17, 17, &umr_bitfield_default }, + { "PARTIAL_ES_WAVE_ON", 18, 18, &umr_bitfield_default }, + { "SWITCH_ON_EOI", 19, 19, &umr_bitfield_default }, + { "WD_SWITCH_ON_EOP", 20, 20, &umr_bitfield_default }, + { "EN_INST_OPT_BASIC", 21, 21, &umr_bitfield_default }, + { "EN_INST_OPT_ADV", 22, 22, &umr_bitfield_default }, + { "HW_USE_ONLY", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_OBJECT_ID[] = { + { "REG_OBJ_ID", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_INSTANCE_BASE_ID[] = { + { "INSTANCE_BASE_ID", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SU_LINE_STIPPLE_VALUE[] = { + { "LINE_STIPPLE_VALUE", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_LINE_STIPPLE_STATE[] = { + { "CURRENT_PTR", 0, 3, &umr_bitfield_default }, + { "CURRENT_COUNT", 8, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_SCREEN_EXTENT_MIN_0[] = { + { "X", 0, 15, &umr_bitfield_default }, + { "Y", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_SCREEN_EXTENT_MAX_0[] = { + { "X", 0, 15, &umr_bitfield_default }, + { "Y", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_SCREEN_EXTENT_MIN_1[] = { + { "X", 0, 15, &umr_bitfield_default }, + { "Y", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_SCREEN_EXTENT_MAX_1[] = { + { "X", 0, 15, &umr_bitfield_default }, + { "Y", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_P3D_TRAP_SCREEN_HV_EN[] = { + { "ENABLE_HV_PRE_SHADER", 0, 0, &umr_bitfield_default }, + { "FORCE_PRE_SHADER_ALL_PIXELS", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_P3D_TRAP_SCREEN_H[] = { + { "X_COORD", 0, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_P3D_TRAP_SCREEN_V[] = { + { "Y_COORD", 0, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE[] = { + { "COUNT", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_P3D_TRAP_SCREEN_COUNT[] = { + { "COUNT", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_HP3D_TRAP_SCREEN_HV_EN[] = { + { "ENABLE_HV_PRE_SHADER", 0, 0, &umr_bitfield_default }, + { "FORCE_PRE_SHADER_ALL_PIXELS", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_HP3D_TRAP_SCREEN_H[] = { + { "X_COORD", 0, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_HP3D_TRAP_SCREEN_V[] = { + { "Y_COORD", 0, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE[] = { + { "COUNT", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_HP3D_TRAP_SCREEN_COUNT[] = { + { "COUNT", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_TRAP_SCREEN_HV_EN[] = { + { "ENABLE_HV_PRE_SHADER", 0, 0, &umr_bitfield_default }, + { "FORCE_PRE_SHADER_ALL_PIXELS", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_TRAP_SCREEN_H[] = { + { "X_COORD", 0, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_TRAP_SCREEN_V[] = { + { "Y_COORD", 0, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_TRAP_SCREEN_OCCURRENCE[] = { + { "COUNT", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_TRAP_SCREEN_COUNT[] = { + { "COUNT", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_THREAD_TRACE_BASE[] = { + { "ADDR", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_THREAD_TRACE_SIZE[] = { + { "SIZE", 0, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_THREAD_TRACE_MASK[] = { + { "CU_SEL", 0, 4, &umr_bitfield_default }, + { "SH_SEL", 5, 5, &umr_bitfield_default }, + { "REG_STALL_EN", 7, 7, &umr_bitfield_default }, + { "SIMD_EN", 8, 11, &umr_bitfield_default }, + { "VM_ID_MASK", 12, 13, &umr_bitfield_default }, + { "SPI_STALL_EN", 14, 14, &umr_bitfield_default }, + { "SQ_STALL_EN", 15, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_THREAD_TRACE_TOKEN_MASK[] = { + { "TOKEN_MASK", 0, 15, &umr_bitfield_default }, + { "REG_MASK", 16, 23, &umr_bitfield_default }, + { "REG_DROP_ON_STALL", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_THREAD_TRACE_PERF_MASK[] = { + { "SH0_MASK", 0, 15, &umr_bitfield_default }, + { "SH1_MASK", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_THREAD_TRACE_CTRL[] = { + { "RESET_BUFFER", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_THREAD_TRACE_MODE[] = { + { "MASK_PS", 0, 2, &umr_bitfield_default }, + { "MASK_VS", 3, 5, &umr_bitfield_default }, + { "MASK_GS", 6, 8, &umr_bitfield_default }, + { "MASK_ES", 9, 11, &umr_bitfield_default }, + { "MASK_HS", 12, 14, &umr_bitfield_default }, + { "MASK_LS", 15, 17, &umr_bitfield_default }, + { "MASK_CS", 18, 20, &umr_bitfield_default }, + { "MODE", 21, 22, &umr_bitfield_default }, + { "CAPTURE_MODE", 23, 24, &umr_bitfield_default }, + { "AUTOFLUSH_EN", 25, 25, &umr_bitfield_default }, + { "TC_PERF_EN", 26, 26, &umr_bitfield_default }, + { "ISSUE_MASK", 27, 28, &umr_bitfield_default }, + { "TEST_MODE", 29, 29, &umr_bitfield_default }, + { "INTERRUPT_EN", 30, 30, &umr_bitfield_default }, + { "WRAP", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_THREAD_TRACE_BASE2[] = { + { "ADDR_HI", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_THREAD_TRACE_TOKEN_MASK2[] = { + { "INST_MASK", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_THREAD_TRACE_WPTR[] = { + { "WPTR", 0, 29, &umr_bitfield_default }, + { "READ_OFFSET", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_THREAD_TRACE_STATUS[] = { + { "FINISH_PENDING", 0, 9, &umr_bitfield_default }, + { "FINISH_DONE", 16, 25, &umr_bitfield_default }, + { "UTC_ERROR", 28, 28, &umr_bitfield_default }, + { "NEW_BUF", 29, 29, &umr_bitfield_default }, + { "BUSY", 30, 30, &umr_bitfield_default }, + { "FULL", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_THREAD_TRACE_HIWATER[] = { + { "HIWATER", 0, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_THREAD_TRACE_CNTR[] = { + { "CNTR", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_THREAD_TRACE_USERDATA_0[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_THREAD_TRACE_USERDATA_1[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_THREAD_TRACE_USERDATA_2[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_THREAD_TRACE_USERDATA_3[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQC_CACHES[] = { + { "TARGET_INST", 0, 0, &umr_bitfield_default }, + { "TARGET_DATA", 1, 1, &umr_bitfield_default }, + { "INVALIDATE", 2, 2, &umr_bitfield_default }, + { "WRITEBACK", 3, 3, &umr_bitfield_default }, + { "VOL", 4, 4, &umr_bitfield_default }, + { "COMPLETE", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQC_WRITEBACK[] = { + { "DWB", 0, 0, &umr_bitfield_default }, + { "DIRTY", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTA_CS_BC_BASE_ADDR[] = { + { "ADDRESS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTA_CS_BC_BASE_ADDR_HI[] = { + { "ADDRESS", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTA_GRAD_ADJ_UCONFIG[] = { + { "GRAD_ADJ_0", 0, 7, &umr_bitfield_default }, + { "GRAD_ADJ_1", 8, 15, &umr_bitfield_default }, + { "GRAD_ADJ_2", 16, 23, &umr_bitfield_default }, + { "GRAD_ADJ_3", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_OCCLUSION_COUNT0_LOW[] = { + { "COUNT_LOW", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_OCCLUSION_COUNT0_HI[] = { + { "COUNT_HI", 0, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_OCCLUSION_COUNT1_LOW[] = { + { "COUNT_LOW", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_OCCLUSION_COUNT1_HI[] = { + { "COUNT_HI", 0, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_OCCLUSION_COUNT2_LOW[] = { + { "COUNT_LOW", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_OCCLUSION_COUNT2_HI[] = { + { "COUNT_HI", 0, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_OCCLUSION_COUNT3_LOW[] = { + { "COUNT_LOW", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_OCCLUSION_COUNT3_HI[] = { + { "COUNT_HI", 0, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_ZPASS_COUNT_LOW[] = { + { "COUNT_LOW", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_ZPASS_COUNT_HI[] = { + { "COUNT_HI", 0, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_RD_ADDR[] = { + { "READ_ADDR", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_RD_DATA[] = { + { "READ_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_RD_BURST_ADDR[] = { + { "BURST_ADDR", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_RD_BURST_COUNT[] = { + { "BURST_COUNT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_RD_BURST_DATA[] = { + { "BURST_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_WR_ADDR[] = { + { "WRITE_ADDR", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_WR_DATA[] = { + { "WRITE_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_WR_BURST_ADDR[] = { + { "WRITE_ADDR", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_WR_BURST_DATA[] = { + { "WRITE_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_WRITE_COMPLETE[] = { + { "WRITE_COMPLETE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_ATOM_CNTL[] = { + { "AINC", 0, 5, &umr_bitfield_default }, + { "UNUSED1", 6, 7, &umr_bitfield_default }, + { "DMODE", 8, 9, &umr_bitfield_default }, + { "UNUSED2", 10, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_ATOM_COMPLETE[] = { + { "COMPLETE", 0, 0, &umr_bitfield_default }, + { "UNUSED", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_ATOM_BASE[] = { + { "BASE", 0, 15, &umr_bitfield_default }, + { "UNUSED", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_ATOM_SIZE[] = { + { "SIZE", 0, 15, &umr_bitfield_default }, + { "UNUSED", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_ATOM_OFFSET0[] = { + { "OFFSET0", 0, 7, &umr_bitfield_default }, + { "UNUSED", 8, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_ATOM_OFFSET1[] = { + { "OFFSET1", 0, 7, &umr_bitfield_default }, + { "UNUSED", 8, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_ATOM_DST[] = { + { "DST", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_ATOM_OP[] = { + { "OP", 0, 7, &umr_bitfield_default }, + { "UNUSED", 8, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_ATOM_SRC0[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_ATOM_SRC0_U[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_ATOM_SRC1[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_ATOM_SRC1_U[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_ATOM_READ0[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_ATOM_READ0_U[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_ATOM_READ1[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_ATOM_READ1_U[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_GWS_RESOURCE_CNTL[] = { + { "INDEX", 0, 5, &umr_bitfield_default }, + { "UNUSED", 6, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_GWS_RESOURCE[] = { + { "FLAG", 0, 0, &umr_bitfield_default }, + { "COUNTER", 1, 12, &umr_bitfield_default }, + { "TYPE", 13, 13, &umr_bitfield_default }, + { "DED", 14, 14, &umr_bitfield_default }, + { "RELEASE_ALL", 15, 15, &umr_bitfield_default }, + { "HEAD_QUEUE", 16, 27, &umr_bitfield_default }, + { "HEAD_VALID", 28, 28, &umr_bitfield_default }, + { "HEAD_FLAG", 29, 29, &umr_bitfield_default }, + { "HALTED", 30, 30, &umr_bitfield_default }, + { "UNUSED1", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_GWS_RESOURCE_CNT[] = { + { "RESOURCE_CNT", 0, 15, &umr_bitfield_default }, + { "UNUSED", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_OA_CNTL[] = { + { "INDEX", 0, 3, &umr_bitfield_default }, + { "UNUSED", 4, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_OA_COUNTER[] = { + { "SPACE_AVAILABLE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_OA_ADDRESS[] = { + { "DS_ADDRESS", 0, 15, &umr_bitfield_default }, + { "CRAWLER", 16, 19, &umr_bitfield_default }, + { "CRAWLER_TYPE", 20, 21, &umr_bitfield_default }, + { "UNUSED", 22, 29, &umr_bitfield_default }, + { "NO_ALLOC", 30, 30, &umr_bitfield_default }, + { "ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_OA_INCDEC[] = { + { "VALUE", 0, 30, &umr_bitfield_default }, + { "INCDEC", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_OA_RING_SIZE[] = { + { "RING_SIZE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_CONFIG_CNTL[] = { + { "GPR_WRITE_PRIORITY", 0, 20, &umr_bitfield_default }, + { "EXP_PRIORITY_ORDER", 21, 23, &umr_bitfield_default }, + { "ENABLE_SQG_TOP_EVENTS", 24, 24, &umr_bitfield_default }, + { "ENABLE_SQG_BOP_EVENTS", 25, 25, &umr_bitfield_default }, + { "RSRC_MGMT_RESET", 26, 26, &umr_bitfield_default }, + { "TTRACE_STALL_ALL", 27, 27, &umr_bitfield_default }, + { "ALLOC_ARB_LRU_ENA", 28, 28, &umr_bitfield_default }, + { "EXP_ARB_LRU_ENA", 29, 29, &umr_bitfield_default }, + { "PS_PKR_PRIORITY_CNTL", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_CONFIG_CNTL_1[] = { + { "VTX_DONE_DELAY", 0, 3, &umr_bitfield_default }, + { "INTERP_ONE_PRIM_PER_ROW", 4, 4, &umr_bitfield_default }, + { "BATON_RESET_DISABLE", 5, 5, &umr_bitfield_default }, + { "PC_LIMIT_ENABLE", 6, 6, &umr_bitfield_default }, + { "PC_LIMIT_STRICT", 7, 7, &umr_bitfield_default }, + { "CRC_SIMD_ID_WADDR_DISABLE", 8, 8, &umr_bitfield_default }, + { "LBPW_CU_CHK_MODE", 9, 9, &umr_bitfield_default }, + { "LBPW_CU_CHK_CNT", 10, 13, &umr_bitfield_default }, + { "CSC_PWR_SAVE_DISABLE", 14, 14, &umr_bitfield_default }, + { "CSG_PWR_SAVE_DISABLE", 15, 15, &umr_bitfield_default }, + { "PC_LIMIT_SIZE", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_CONFIG_CNTL_2[] = { + { "CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD", 0, 3, &umr_bitfield_default }, + { "CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCPG_PERFCOUNTER1_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCPG_PERFCOUNTER1_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCPG_PERFCOUNTER0_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCPG_PERFCOUNTER0_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCPC_PERFCOUNTER1_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCPC_PERFCOUNTER1_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCPC_PERFCOUNTER0_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCPC_PERFCOUNTER0_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCPF_PERFCOUNTER1_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCPF_PERFCOUNTER1_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCPF_PERFCOUNTER0_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCPF_PERFCOUNTER0_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCPF_LATENCY_STATS_DATA[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCPG_LATENCY_STATS_DATA[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCPC_LATENCY_STATS_DATA[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRBM_PERFCOUNTER0_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRBM_PERFCOUNTER0_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRBM_PERFCOUNTER1_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRBM_PERFCOUNTER1_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRBM_SE0_PERFCOUNTER_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRBM_SE0_PERFCOUNTER_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRBM_SE1_PERFCOUNTER_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRBM_SE1_PERFCOUNTER_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRBM_SE2_PERFCOUNTER_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRBM_SE2_PERFCOUNTER_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRBM_SE3_PERFCOUNTER_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRBM_SE3_PERFCOUNTER_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWD_PERFCOUNTER0_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWD_PERFCOUNTER0_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWD_PERFCOUNTER1_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWD_PERFCOUNTER1_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWD_PERFCOUNTER2_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWD_PERFCOUNTER2_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWD_PERFCOUNTER3_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWD_PERFCOUNTER3_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIA_PERFCOUNTER0_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIA_PERFCOUNTER0_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIA_PERFCOUNTER1_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIA_PERFCOUNTER1_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIA_PERFCOUNTER2_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIA_PERFCOUNTER2_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIA_PERFCOUNTER3_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIA_PERFCOUNTER3_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_PERFCOUNTER0_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_PERFCOUNTER0_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_PERFCOUNTER1_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_PERFCOUNTER1_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_PERFCOUNTER2_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_PERFCOUNTER2_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_PERFCOUNTER3_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_PERFCOUNTER3_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SU_PERFCOUNTER0_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SU_PERFCOUNTER0_HI[] = { + { "PERFCOUNTER_HI", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SU_PERFCOUNTER1_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SU_PERFCOUNTER1_HI[] = { + { "PERFCOUNTER_HI", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SU_PERFCOUNTER2_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SU_PERFCOUNTER2_HI[] = { + { "PERFCOUNTER_HI", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SU_PERFCOUNTER3_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SU_PERFCOUNTER3_HI[] = { + { "PERFCOUNTER_HI", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_PERFCOUNTER0_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_PERFCOUNTER0_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_PERFCOUNTER1_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_PERFCOUNTER1_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_PERFCOUNTER2_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_PERFCOUNTER2_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_PERFCOUNTER3_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_PERFCOUNTER3_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_PERFCOUNTER4_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_PERFCOUNTER4_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_PERFCOUNTER5_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_PERFCOUNTER5_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_PERFCOUNTER6_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_PERFCOUNTER6_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_PERFCOUNTER7_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_PERFCOUNTER7_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_PERFCOUNTER0_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_PERFCOUNTER0_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_PERFCOUNTER1_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_PERFCOUNTER1_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_PERFCOUNTER2_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_PERFCOUNTER2_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_PERFCOUNTER3_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_PERFCOUNTER3_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_PERFCOUNTER4_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_PERFCOUNTER4_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_PERFCOUNTER5_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_PERFCOUNTER5_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_PERFCOUNTER0_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_PERFCOUNTER0_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_PERFCOUNTER1_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_PERFCOUNTER1_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_PERFCOUNTER2_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_PERFCOUNTER2_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_PERFCOUNTER3_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_PERFCOUNTER3_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_PERFCOUNTER4_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_PERFCOUNTER4_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_PERFCOUNTER5_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_PERFCOUNTER5_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_PERFCOUNTER6_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_PERFCOUNTER6_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_PERFCOUNTER7_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_PERFCOUNTER7_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_PERFCOUNTER8_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_PERFCOUNTER8_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_PERFCOUNTER9_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_PERFCOUNTER9_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_PERFCOUNTER10_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_PERFCOUNTER10_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_PERFCOUNTER11_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_PERFCOUNTER11_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_PERFCOUNTER12_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_PERFCOUNTER12_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_PERFCOUNTER13_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_PERFCOUNTER13_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_PERFCOUNTER14_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_PERFCOUNTER14_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_PERFCOUNTER15_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_PERFCOUNTER15_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSX_PERFCOUNTER0_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSX_PERFCOUNTER0_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSX_PERFCOUNTER1_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSX_PERFCOUNTER1_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSX_PERFCOUNTER2_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSX_PERFCOUNTER2_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSX_PERFCOUNTER3_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSX_PERFCOUNTER3_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_PERFCOUNTER0_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_PERFCOUNTER0_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_PERFCOUNTER1_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_PERFCOUNTER1_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_PERFCOUNTER2_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_PERFCOUNTER2_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_PERFCOUNTER3_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_PERFCOUNTER3_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTA_PERFCOUNTER0_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTA_PERFCOUNTER0_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTA_PERFCOUNTER1_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTA_PERFCOUNTER1_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTD_PERFCOUNTER0_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTD_PERFCOUNTER0_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTD_PERFCOUNTER1_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTD_PERFCOUNTER1_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCP_PERFCOUNTER0_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCP_PERFCOUNTER0_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCP_PERFCOUNTER1_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCP_PERFCOUNTER1_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCP_PERFCOUNTER2_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCP_PERFCOUNTER2_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCP_PERFCOUNTER3_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCP_PERFCOUNTER3_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCC_PERFCOUNTER0_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCC_PERFCOUNTER0_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCC_PERFCOUNTER1_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCC_PERFCOUNTER1_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCC_PERFCOUNTER2_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCC_PERFCOUNTER2_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCC_PERFCOUNTER3_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCC_PERFCOUNTER3_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCA_PERFCOUNTER0_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCA_PERFCOUNTER0_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCA_PERFCOUNTER1_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCA_PERFCOUNTER1_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCA_PERFCOUNTER2_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCA_PERFCOUNTER2_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCA_PERFCOUNTER3_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCA_PERFCOUNTER3_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_PERFCOUNTER0_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_PERFCOUNTER0_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_PERFCOUNTER1_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_PERFCOUNTER1_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_PERFCOUNTER2_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_PERFCOUNTER2_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_PERFCOUNTER3_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_PERFCOUNTER3_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_PERFCOUNTER0_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_PERFCOUNTER0_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_PERFCOUNTER1_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_PERFCOUNTER1_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_PERFCOUNTER2_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_PERFCOUNTER2_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_PERFCOUNTER3_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_PERFCOUNTER3_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_PERFCOUNTER0_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_PERFCOUNTER0_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_PERFCOUNTER1_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_PERFCOUNTER1_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRMI_PERFCOUNTER0_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRMI_PERFCOUNTER0_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRMI_PERFCOUNTER1_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRMI_PERFCOUNTER1_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRMI_PERFCOUNTER2_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRMI_PERFCOUNTER2_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRMI_PERFCOUNTER3_LO[] = { + { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRMI_PERFCOUNTER3_HI[] = { + { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmATC_L2_PERFCOUNTER_LO[] = { + { "COUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmATC_L2_PERFCOUNTER_HI[] = { + { "COUNTER_HI", 0, 15, &umr_bitfield_default }, + { "COMPARE_VALUE", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_L2_PERFCOUNTER_LO[] = { + { "COUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_L2_PERFCOUNTER_HI[] = { + { "COUNTER_HI", 0, 15, &umr_bitfield_default }, + { "COMPARE_VALUE", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCPG_PERFCOUNTER1_SELECT[] = { + { "CNTR_SEL0", 0, 9, &umr_bitfield_default }, + { "CNTR_SEL1", 10, 19, &umr_bitfield_default }, + { "SPM_MODE", 20, 23, &umr_bitfield_default }, + { "CNTR_MODE1", 24, 27, &umr_bitfield_default }, + { "CNTR_MODE0", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCPG_PERFCOUNTER0_SELECT1[] = { + { "CNTR_SEL2", 0, 9, &umr_bitfield_default }, + { "CNTR_SEL3", 10, 19, &umr_bitfield_default }, + { "CNTR_MODE3", 24, 27, &umr_bitfield_default }, + { "CNTR_MODE2", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCPG_PERFCOUNTER0_SELECT[] = { + { "CNTR_SEL0", 0, 9, &umr_bitfield_default }, + { "CNTR_SEL1", 10, 19, &umr_bitfield_default }, + { "SPM_MODE", 20, 23, &umr_bitfield_default }, + { "CNTR_MODE1", 24, 27, &umr_bitfield_default }, + { "CNTR_MODE0", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCPC_PERFCOUNTER1_SELECT[] = { + { "CNTR_SEL0", 0, 9, &umr_bitfield_default }, + { "CNTR_SEL1", 10, 19, &umr_bitfield_default }, + { "SPM_MODE", 20, 23, &umr_bitfield_default }, + { "CNTR_MODE1", 24, 27, &umr_bitfield_default }, + { "CNTR_MODE0", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCPC_PERFCOUNTER0_SELECT1[] = { + { "CNTR_SEL2", 0, 9, &umr_bitfield_default }, + { "CNTR_SEL3", 10, 19, &umr_bitfield_default }, + { "CNTR_MODE3", 24, 27, &umr_bitfield_default }, + { "CNTR_MODE2", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCPF_PERFCOUNTER1_SELECT[] = { + { "CNTR_SEL0", 0, 9, &umr_bitfield_default }, + { "CNTR_SEL1", 10, 19, &umr_bitfield_default }, + { "SPM_MODE", 20, 23, &umr_bitfield_default }, + { "CNTR_MODE1", 24, 27, &umr_bitfield_default }, + { "CNTR_MODE0", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCPF_PERFCOUNTER0_SELECT1[] = { + { "CNTR_SEL2", 0, 9, &umr_bitfield_default }, + { "CNTR_SEL3", 10, 19, &umr_bitfield_default }, + { "CNTR_MODE3", 24, 27, &umr_bitfield_default }, + { "CNTR_MODE2", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCPF_PERFCOUNTER0_SELECT[] = { + { "CNTR_SEL0", 0, 9, &umr_bitfield_default }, + { "CNTR_SEL1", 10, 19, &umr_bitfield_default }, + { "SPM_MODE", 20, 23, &umr_bitfield_default }, + { "CNTR_MODE1", 24, 27, &umr_bitfield_default }, + { "CNTR_MODE0", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_PERFMON_CNTL[] = { + { "PERFMON_STATE", 0, 3, &umr_bitfield_default }, + { "SPM_PERFMON_STATE", 4, 7, &umr_bitfield_default }, + { "PERFMON_ENABLE_MODE", 8, 9, &umr_bitfield_default }, + { "PERFMON_SAMPLE_ENABLE", 10, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCPC_PERFCOUNTER0_SELECT[] = { + { "CNTR_SEL0", 0, 9, &umr_bitfield_default }, + { "CNTR_SEL1", 10, 19, &umr_bitfield_default }, + { "SPM_MODE", 20, 23, &umr_bitfield_default }, + { "CNTR_MODE1", 24, 27, &umr_bitfield_default }, + { "CNTR_MODE0", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCPF_TC_PERF_COUNTER_WINDOW_SELECT[] = { + { "INDEX", 0, 2, &umr_bitfield_default }, + { "ALWAYS", 30, 30, &umr_bitfield_default }, + { "ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCPG_TC_PERF_COUNTER_WINDOW_SELECT[] = { + { "INDEX", 0, 4, &umr_bitfield_default }, + { "ALWAYS", 30, 30, &umr_bitfield_default }, + { "ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCPF_LATENCY_STATS_SELECT[] = { + { "INDEX", 0, 3, &umr_bitfield_default }, + { "CLEAR", 30, 30, &umr_bitfield_default }, + { "ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCPG_LATENCY_STATS_SELECT[] = { + { "INDEX", 0, 4, &umr_bitfield_default }, + { "CLEAR", 30, 30, &umr_bitfield_default }, + { "ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCPC_LATENCY_STATS_SELECT[] = { + { "INDEX", 0, 2, &umr_bitfield_default }, + { "CLEAR", 30, 30, &umr_bitfield_default }, + { "ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_DRAW_OBJECT[] = { + { "OBJECT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_DRAW_OBJECT_COUNTER[] = { + { "COUNT", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_DRAW_WINDOW_MASK_HI[] = { + { "WINDOW_MASK_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_DRAW_WINDOW_HI[] = { + { "WINDOW_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_DRAW_WINDOW_LO[] = { + { "MIN", 0, 15, &umr_bitfield_default }, + { "MAX", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_DRAW_WINDOW_CNTL[] = { + { "DISABLE_DRAW_WINDOW_LO_MAX", 0, 0, &umr_bitfield_default }, + { "DISABLE_DRAW_WINDOW_LO_MIN", 1, 1, &umr_bitfield_default }, + { "DISABLE_DRAW_WINDOW_HI", 2, 2, &umr_bitfield_default }, + { "MODE", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRBM_PERFCOUNTER0_SELECT[] = { + { "PERF_SEL", 0, 5, &umr_bitfield_default }, + { "DB_CLEAN_USER_DEFINED_MASK", 10, 10, &umr_bitfield_default }, + { "CB_CLEAN_USER_DEFINED_MASK", 11, 11, &umr_bitfield_default }, + { "VGT_BUSY_USER_DEFINED_MASK", 12, 12, &umr_bitfield_default }, + { "TA_BUSY_USER_DEFINED_MASK", 13, 13, &umr_bitfield_default }, + { "SX_BUSY_USER_DEFINED_MASK", 14, 14, &umr_bitfield_default }, + { "SPI_BUSY_USER_DEFINED_MASK", 16, 16, &umr_bitfield_default }, + { "SC_BUSY_USER_DEFINED_MASK", 17, 17, &umr_bitfield_default }, + { "PA_BUSY_USER_DEFINED_MASK", 18, 18, &umr_bitfield_default }, + { "GRBM_BUSY_USER_DEFINED_MASK", 19, 19, &umr_bitfield_default }, + { "DB_BUSY_USER_DEFINED_MASK", 20, 20, &umr_bitfield_default }, + { "CB_BUSY_USER_DEFINED_MASK", 21, 21, &umr_bitfield_default }, + { "CP_BUSY_USER_DEFINED_MASK", 22, 22, &umr_bitfield_default }, + { "IA_BUSY_USER_DEFINED_MASK", 23, 23, &umr_bitfield_default }, + { "GDS_BUSY_USER_DEFINED_MASK", 24, 24, &umr_bitfield_default }, + { "BCI_BUSY_USER_DEFINED_MASK", 25, 25, &umr_bitfield_default }, + { "RLC_BUSY_USER_DEFINED_MASK", 26, 26, &umr_bitfield_default }, + { "TC_BUSY_USER_DEFINED_MASK", 27, 27, &umr_bitfield_default }, + { "WD_BUSY_USER_DEFINED_MASK", 28, 28, &umr_bitfield_default }, + { "UTCL2_BUSY_USER_DEFINED_MASK", 29, 29, &umr_bitfield_default }, + { "EA_BUSY_USER_DEFINED_MASK", 30, 30, &umr_bitfield_default }, + { "RMI_BUSY_USER_DEFINED_MASK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRBM_PERFCOUNTER1_SELECT[] = { + { "PERF_SEL", 0, 5, &umr_bitfield_default }, + { "DB_CLEAN_USER_DEFINED_MASK", 10, 10, &umr_bitfield_default }, + { "CB_CLEAN_USER_DEFINED_MASK", 11, 11, &umr_bitfield_default }, + { "VGT_BUSY_USER_DEFINED_MASK", 12, 12, &umr_bitfield_default }, + { "TA_BUSY_USER_DEFINED_MASK", 13, 13, &umr_bitfield_default }, + { "SX_BUSY_USER_DEFINED_MASK", 14, 14, &umr_bitfield_default }, + { "SPI_BUSY_USER_DEFINED_MASK", 16, 16, &umr_bitfield_default }, + { "SC_BUSY_USER_DEFINED_MASK", 17, 17, &umr_bitfield_default }, + { "PA_BUSY_USER_DEFINED_MASK", 18, 18, &umr_bitfield_default }, + { "GRBM_BUSY_USER_DEFINED_MASK", 19, 19, &umr_bitfield_default }, + { "DB_BUSY_USER_DEFINED_MASK", 20, 20, &umr_bitfield_default }, + { "CB_BUSY_USER_DEFINED_MASK", 21, 21, &umr_bitfield_default }, + { "CP_BUSY_USER_DEFINED_MASK", 22, 22, &umr_bitfield_default }, + { "IA_BUSY_USER_DEFINED_MASK", 23, 23, &umr_bitfield_default }, + { "GDS_BUSY_USER_DEFINED_MASK", 24, 24, &umr_bitfield_default }, + { "BCI_BUSY_USER_DEFINED_MASK", 25, 25, &umr_bitfield_default }, + { "RLC_BUSY_USER_DEFINED_MASK", 26, 26, &umr_bitfield_default }, + { "TC_BUSY_USER_DEFINED_MASK", 27, 27, &umr_bitfield_default }, + { "WD_BUSY_USER_DEFINED_MASK", 28, 28, &umr_bitfield_default }, + { "UTCL2_BUSY_USER_DEFINED_MASK", 29, 29, &umr_bitfield_default }, + { "EA_BUSY_USER_DEFINED_MASK", 30, 30, &umr_bitfield_default }, + { "RMI_BUSY_USER_DEFINED_MASK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRBM_SE0_PERFCOUNTER_SELECT[] = { + { "PERF_SEL", 0, 5, &umr_bitfield_default }, + { "DB_CLEAN_USER_DEFINED_MASK", 10, 10, &umr_bitfield_default }, + { "CB_CLEAN_USER_DEFINED_MASK", 11, 11, &umr_bitfield_default }, + { "TA_BUSY_USER_DEFINED_MASK", 12, 12, &umr_bitfield_default }, + { "SX_BUSY_USER_DEFINED_MASK", 13, 13, &umr_bitfield_default }, + { "SPI_BUSY_USER_DEFINED_MASK", 15, 15, &umr_bitfield_default }, + { "SC_BUSY_USER_DEFINED_MASK", 16, 16, &umr_bitfield_default }, + { "DB_BUSY_USER_DEFINED_MASK", 17, 17, &umr_bitfield_default }, + { "CB_BUSY_USER_DEFINED_MASK", 18, 18, &umr_bitfield_default }, + { "VGT_BUSY_USER_DEFINED_MASK", 19, 19, &umr_bitfield_default }, + { "PA_BUSY_USER_DEFINED_MASK", 20, 20, &umr_bitfield_default }, + { "BCI_BUSY_USER_DEFINED_MASK", 21, 21, &umr_bitfield_default }, + { "RMI_BUSY_USER_DEFINED_MASK", 22, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRBM_SE1_PERFCOUNTER_SELECT[] = { + { "PERF_SEL", 0, 5, &umr_bitfield_default }, + { "DB_CLEAN_USER_DEFINED_MASK", 10, 10, &umr_bitfield_default }, + { "CB_CLEAN_USER_DEFINED_MASK", 11, 11, &umr_bitfield_default }, + { "TA_BUSY_USER_DEFINED_MASK", 12, 12, &umr_bitfield_default }, + { "SX_BUSY_USER_DEFINED_MASK", 13, 13, &umr_bitfield_default }, + { "SPI_BUSY_USER_DEFINED_MASK", 15, 15, &umr_bitfield_default }, + { "SC_BUSY_USER_DEFINED_MASK", 16, 16, &umr_bitfield_default }, + { "DB_BUSY_USER_DEFINED_MASK", 17, 17, &umr_bitfield_default }, + { "CB_BUSY_USER_DEFINED_MASK", 18, 18, &umr_bitfield_default }, + { "VGT_BUSY_USER_DEFINED_MASK", 19, 19, &umr_bitfield_default }, + { "PA_BUSY_USER_DEFINED_MASK", 20, 20, &umr_bitfield_default }, + { "BCI_BUSY_USER_DEFINED_MASK", 21, 21, &umr_bitfield_default }, + { "RMI_BUSY_USER_DEFINED_MASK", 22, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRBM_SE2_PERFCOUNTER_SELECT[] = { + { "PERF_SEL", 0, 5, &umr_bitfield_default }, + { "DB_CLEAN_USER_DEFINED_MASK", 10, 10, &umr_bitfield_default }, + { "CB_CLEAN_USER_DEFINED_MASK", 11, 11, &umr_bitfield_default }, + { "TA_BUSY_USER_DEFINED_MASK", 12, 12, &umr_bitfield_default }, + { "SX_BUSY_USER_DEFINED_MASK", 13, 13, &umr_bitfield_default }, + { "SPI_BUSY_USER_DEFINED_MASK", 15, 15, &umr_bitfield_default }, + { "SC_BUSY_USER_DEFINED_MASK", 16, 16, &umr_bitfield_default }, + { "DB_BUSY_USER_DEFINED_MASK", 17, 17, &umr_bitfield_default }, + { "CB_BUSY_USER_DEFINED_MASK", 18, 18, &umr_bitfield_default }, + { "VGT_BUSY_USER_DEFINED_MASK", 19, 19, &umr_bitfield_default }, + { "PA_BUSY_USER_DEFINED_MASK", 20, 20, &umr_bitfield_default }, + { "BCI_BUSY_USER_DEFINED_MASK", 21, 21, &umr_bitfield_default }, + { "RMI_BUSY_USER_DEFINED_MASK", 22, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRBM_SE3_PERFCOUNTER_SELECT[] = { + { "PERF_SEL", 0, 5, &umr_bitfield_default }, + { "DB_CLEAN_USER_DEFINED_MASK", 10, 10, &umr_bitfield_default }, + { "CB_CLEAN_USER_DEFINED_MASK", 11, 11, &umr_bitfield_default }, + { "TA_BUSY_USER_DEFINED_MASK", 12, 12, &umr_bitfield_default }, + { "SX_BUSY_USER_DEFINED_MASK", 13, 13, &umr_bitfield_default }, + { "SPI_BUSY_USER_DEFINED_MASK", 15, 15, &umr_bitfield_default }, + { "SC_BUSY_USER_DEFINED_MASK", 16, 16, &umr_bitfield_default }, + { "DB_BUSY_USER_DEFINED_MASK", 17, 17, &umr_bitfield_default }, + { "CB_BUSY_USER_DEFINED_MASK", 18, 18, &umr_bitfield_default }, + { "VGT_BUSY_USER_DEFINED_MASK", 19, 19, &umr_bitfield_default }, + { "PA_BUSY_USER_DEFINED_MASK", 20, 20, &umr_bitfield_default }, + { "BCI_BUSY_USER_DEFINED_MASK", 21, 21, &umr_bitfield_default }, + { "RMI_BUSY_USER_DEFINED_MASK", 22, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWD_PERFCOUNTER0_SELECT[] = { + { "PERF_SEL", 0, 7, &umr_bitfield_default }, + { "PERF_MODE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWD_PERFCOUNTER1_SELECT[] = { + { "PERF_SEL", 0, 7, &umr_bitfield_default }, + { "PERF_MODE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWD_PERFCOUNTER2_SELECT[] = { + { "PERF_SEL", 0, 7, &umr_bitfield_default }, + { "PERF_MODE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmWD_PERFCOUNTER3_SELECT[] = { + { "PERF_SEL", 0, 7, &umr_bitfield_default }, + { "PERF_MODE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIA_PERFCOUNTER0_SELECT[] = { + { "PERF_SEL", 0, 9, &umr_bitfield_default }, + { "PERF_SEL1", 10, 19, &umr_bitfield_default }, + { "CNTR_MODE", 20, 23, &umr_bitfield_default }, + { "PERF_MODE1", 24, 27, &umr_bitfield_default }, + { "PERF_MODE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIA_PERFCOUNTER1_SELECT[] = { + { "PERF_SEL", 0, 7, &umr_bitfield_default }, + { "PERF_MODE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIA_PERFCOUNTER2_SELECT[] = { + { "PERF_SEL", 0, 7, &umr_bitfield_default }, + { "PERF_MODE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIA_PERFCOUNTER3_SELECT[] = { + { "PERF_SEL", 0, 7, &umr_bitfield_default }, + { "PERF_MODE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIA_PERFCOUNTER0_SELECT1[] = { + { "PERF_SEL2", 0, 9, &umr_bitfield_default }, + { "PERF_SEL3", 10, 19, &umr_bitfield_default }, + { "PERF_MODE3", 24, 27, &umr_bitfield_default }, + { "PERF_MODE2", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_PERFCOUNTER0_SELECT[] = { + { "PERF_SEL", 0, 9, &umr_bitfield_default }, + { "PERF_SEL1", 10, 19, &umr_bitfield_default }, + { "CNTR_MODE", 20, 23, &umr_bitfield_default }, + { "PERF_MODE1", 24, 27, &umr_bitfield_default }, + { "PERF_MODE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_PERFCOUNTER1_SELECT[] = { + { "PERF_SEL", 0, 9, &umr_bitfield_default }, + { "PERF_SEL1", 10, 19, &umr_bitfield_default }, + { "CNTR_MODE", 20, 23, &umr_bitfield_default }, + { "PERF_MODE1", 24, 27, &umr_bitfield_default }, + { "PERF_MODE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_PERFCOUNTER2_SELECT[] = { + { "PERF_SEL", 0, 7, &umr_bitfield_default }, + { "PERF_MODE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_PERFCOUNTER3_SELECT[] = { + { "PERF_SEL", 0, 7, &umr_bitfield_default }, + { "PERF_MODE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_PERFCOUNTER0_SELECT1[] = { + { "PERF_SEL2", 0, 9, &umr_bitfield_default }, + { "PERF_SEL3", 10, 19, &umr_bitfield_default }, + { "PERF_MODE3", 24, 27, &umr_bitfield_default }, + { "PERF_MODE2", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_PERFCOUNTER1_SELECT1[] = { + { "PERF_SEL2", 0, 9, &umr_bitfield_default }, + { "PERF_SEL3", 10, 19, &umr_bitfield_default }, + { "PERF_MODE3", 24, 27, &umr_bitfield_default }, + { "PERF_MODE2", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVGT_PERFCOUNTER_SEID_MASK[] = { + { "PERF_SEID_IGNORE_MASK", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SU_PERFCOUNTER0_SELECT[] = { + { "PERF_SEL", 0, 9, &umr_bitfield_default }, + { "PERF_SEL1", 10, 19, &umr_bitfield_default }, + { "CNTR_MODE", 20, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SU_PERFCOUNTER0_SELECT1[] = { + { "PERF_SEL2", 0, 9, &umr_bitfield_default }, + { "PERF_SEL3", 10, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SU_PERFCOUNTER1_SELECT[] = { + { "PERF_SEL", 0, 9, &umr_bitfield_default }, + { "PERF_SEL1", 10, 19, &umr_bitfield_default }, + { "CNTR_MODE", 20, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SU_PERFCOUNTER1_SELECT1[] = { + { "PERF_SEL2", 0, 9, &umr_bitfield_default }, + { "PERF_SEL3", 10, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SU_PERFCOUNTER2_SELECT[] = { + { "PERF_SEL", 0, 9, &umr_bitfield_default }, + { "CNTR_MODE", 20, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SU_PERFCOUNTER3_SELECT[] = { + { "PERF_SEL", 0, 9, &umr_bitfield_default }, + { "CNTR_MODE", 20, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_PERFCOUNTER0_SELECT[] = { + { "PERF_SEL", 0, 9, &umr_bitfield_default }, + { "PERF_SEL1", 10, 19, &umr_bitfield_default }, + { "CNTR_MODE", 20, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_PERFCOUNTER0_SELECT1[] = { + { "PERF_SEL2", 0, 9, &umr_bitfield_default }, + { "PERF_SEL3", 10, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_PERFCOUNTER1_SELECT[] = { + { "PERF_SEL", 0, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_PERFCOUNTER2_SELECT[] = { + { "PERF_SEL", 0, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_PERFCOUNTER3_SELECT[] = { + { "PERF_SEL", 0, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_PERFCOUNTER4_SELECT[] = { + { "PERF_SEL", 0, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_PERFCOUNTER5_SELECT[] = { + { "PERF_SEL", 0, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_PERFCOUNTER6_SELECT[] = { + { "PERF_SEL", 0, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPA_SC_PERFCOUNTER7_SELECT[] = { + { "PERF_SEL", 0, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_PERFCOUNTER0_SELECT[] = { + { "PERF_SEL", 0, 9, &umr_bitfield_default }, + { "PERF_SEL1", 10, 19, &umr_bitfield_default }, + { "CNTR_MODE", 20, 23, &umr_bitfield_default }, + { "PERF_MODE1", 24, 27, &umr_bitfield_default }, + { "PERF_MODE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_PERFCOUNTER1_SELECT[] = { + { "PERF_SEL", 0, 9, &umr_bitfield_default }, + { "PERF_SEL1", 10, 19, &umr_bitfield_default }, + { "CNTR_MODE", 20, 23, &umr_bitfield_default }, + { "PERF_MODE1", 24, 27, &umr_bitfield_default }, + { "PERF_MODE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_PERFCOUNTER2_SELECT[] = { + { "PERF_SEL", 0, 9, &umr_bitfield_default }, + { "PERF_SEL1", 10, 19, &umr_bitfield_default }, + { "CNTR_MODE", 20, 23, &umr_bitfield_default }, + { "PERF_MODE1", 24, 27, &umr_bitfield_default }, + { "PERF_MODE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_PERFCOUNTER3_SELECT[] = { + { "PERF_SEL", 0, 9, &umr_bitfield_default }, + { "PERF_SEL1", 10, 19, &umr_bitfield_default }, + { "CNTR_MODE", 20, 23, &umr_bitfield_default }, + { "PERF_MODE1", 24, 27, &umr_bitfield_default }, + { "PERF_MODE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_PERFCOUNTER0_SELECT1[] = { + { "PERF_SEL2", 0, 9, &umr_bitfield_default }, + { "PERF_SEL3", 10, 19, &umr_bitfield_default }, + { "PERF_MODE3", 24, 27, &umr_bitfield_default }, + { "PERF_MODE2", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_PERFCOUNTER1_SELECT1[] = { + { "PERF_SEL2", 0, 9, &umr_bitfield_default }, + { "PERF_SEL3", 10, 19, &umr_bitfield_default }, + { "PERF_MODE3", 24, 27, &umr_bitfield_default }, + { "PERF_MODE2", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_PERFCOUNTER2_SELECT1[] = { + { "PERF_SEL2", 0, 9, &umr_bitfield_default }, + { "PERF_SEL3", 10, 19, &umr_bitfield_default }, + { "PERF_MODE3", 24, 27, &umr_bitfield_default }, + { "PERF_MODE2", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_PERFCOUNTER3_SELECT1[] = { + { "PERF_SEL2", 0, 9, &umr_bitfield_default }, + { "PERF_SEL3", 10, 19, &umr_bitfield_default }, + { "PERF_MODE3", 24, 27, &umr_bitfield_default }, + { "PERF_MODE2", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_PERFCOUNTER4_SELECT[] = { + { "PERF_SEL", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_PERFCOUNTER5_SELECT[] = { + { "PERF_SEL", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSPI_PERFCOUNTER_BINS[] = { + { "BIN0_MIN", 0, 3, &umr_bitfield_default }, + { "BIN0_MAX", 4, 7, &umr_bitfield_default }, + { "BIN1_MIN", 8, 11, &umr_bitfield_default }, + { "BIN1_MAX", 12, 15, &umr_bitfield_default }, + { "BIN2_MIN", 16, 19, &umr_bitfield_default }, + { "BIN2_MAX", 20, 23, &umr_bitfield_default }, + { "BIN3_MIN", 24, 27, &umr_bitfield_default }, + { "BIN3_MAX", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_PERFCOUNTER0_SELECT[] = { + { "PERF_SEL", 0, 8, &umr_bitfield_default }, + { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default }, + { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default }, + { "SPM_MODE", 20, 23, &umr_bitfield_default }, + { "SIMD_MASK", 24, 27, &umr_bitfield_default }, + { "PERF_MODE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_PERFCOUNTER1_SELECT[] = { + { "PERF_SEL", 0, 8, &umr_bitfield_default }, + { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default }, + { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default }, + { "SPM_MODE", 20, 23, &umr_bitfield_default }, + { "SIMD_MASK", 24, 27, &umr_bitfield_default }, + { "PERF_MODE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_PERFCOUNTER2_SELECT[] = { + { "PERF_SEL", 0, 8, &umr_bitfield_default }, + { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default }, + { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default }, + { "SPM_MODE", 20, 23, &umr_bitfield_default }, + { "SIMD_MASK", 24, 27, &umr_bitfield_default }, + { "PERF_MODE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_PERFCOUNTER3_SELECT[] = { + { "PERF_SEL", 0, 8, &umr_bitfield_default }, + { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default }, + { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default }, + { "SPM_MODE", 20, 23, &umr_bitfield_default }, + { "SIMD_MASK", 24, 27, &umr_bitfield_default }, + { "PERF_MODE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_PERFCOUNTER4_SELECT[] = { + { "PERF_SEL", 0, 8, &umr_bitfield_default }, + { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default }, + { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default }, + { "SPM_MODE", 20, 23, &umr_bitfield_default }, + { "SIMD_MASK", 24, 27, &umr_bitfield_default }, + { "PERF_MODE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_PERFCOUNTER5_SELECT[] = { + { "PERF_SEL", 0, 8, &umr_bitfield_default }, + { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default }, + { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default }, + { "SPM_MODE", 20, 23, &umr_bitfield_default }, + { "SIMD_MASK", 24, 27, &umr_bitfield_default }, + { "PERF_MODE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_PERFCOUNTER6_SELECT[] = { + { "PERF_SEL", 0, 8, &umr_bitfield_default }, + { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default }, + { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default }, + { "SPM_MODE", 20, 23, &umr_bitfield_default }, + { "SIMD_MASK", 24, 27, &umr_bitfield_default }, + { "PERF_MODE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_PERFCOUNTER7_SELECT[] = { + { "PERF_SEL", 0, 8, &umr_bitfield_default }, + { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default }, + { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default }, + { "SPM_MODE", 20, 23, &umr_bitfield_default }, + { "SIMD_MASK", 24, 27, &umr_bitfield_default }, + { "PERF_MODE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_PERFCOUNTER8_SELECT[] = { + { "PERF_SEL", 0, 8, &umr_bitfield_default }, + { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default }, + { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default }, + { "SPM_MODE", 20, 23, &umr_bitfield_default }, + { "SIMD_MASK", 24, 27, &umr_bitfield_default }, + { "PERF_MODE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_PERFCOUNTER9_SELECT[] = { + { "PERF_SEL", 0, 8, &umr_bitfield_default }, + { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default }, + { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default }, + { "SPM_MODE", 20, 23, &umr_bitfield_default }, + { "SIMD_MASK", 24, 27, &umr_bitfield_default }, + { "PERF_MODE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_PERFCOUNTER10_SELECT[] = { + { "PERF_SEL", 0, 8, &umr_bitfield_default }, + { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default }, + { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default }, + { "SPM_MODE", 20, 23, &umr_bitfield_default }, + { "SIMD_MASK", 24, 27, &umr_bitfield_default }, + { "PERF_MODE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_PERFCOUNTER11_SELECT[] = { + { "PERF_SEL", 0, 8, &umr_bitfield_default }, + { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default }, + { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default }, + { "SPM_MODE", 20, 23, &umr_bitfield_default }, + { "SIMD_MASK", 24, 27, &umr_bitfield_default }, + { "PERF_MODE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_PERFCOUNTER12_SELECT[] = { + { "PERF_SEL", 0, 8, &umr_bitfield_default }, + { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default }, + { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default }, + { "SPM_MODE", 20, 23, &umr_bitfield_default }, + { "SIMD_MASK", 24, 27, &umr_bitfield_default }, + { "PERF_MODE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_PERFCOUNTER13_SELECT[] = { + { "PERF_SEL", 0, 8, &umr_bitfield_default }, + { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default }, + { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default }, + { "SPM_MODE", 20, 23, &umr_bitfield_default }, + { "SIMD_MASK", 24, 27, &umr_bitfield_default }, + { "PERF_MODE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_PERFCOUNTER14_SELECT[] = { + { "PERF_SEL", 0, 8, &umr_bitfield_default }, + { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default }, + { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default }, + { "SPM_MODE", 20, 23, &umr_bitfield_default }, + { "SIMD_MASK", 24, 27, &umr_bitfield_default }, + { "PERF_MODE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_PERFCOUNTER15_SELECT[] = { + { "PERF_SEL", 0, 8, &umr_bitfield_default }, + { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default }, + { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default }, + { "SPM_MODE", 20, 23, &umr_bitfield_default }, + { "SIMD_MASK", 24, 27, &umr_bitfield_default }, + { "PERF_MODE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_PERFCOUNTER_CTRL[] = { + { "PS_EN", 0, 0, &umr_bitfield_default }, + { "VS_EN", 1, 1, &umr_bitfield_default }, + { "GS_EN", 2, 2, &umr_bitfield_default }, + { "ES_EN", 3, 3, &umr_bitfield_default }, + { "HS_EN", 4, 4, &umr_bitfield_default }, + { "LS_EN", 5, 5, &umr_bitfield_default }, + { "CS_EN", 6, 6, &umr_bitfield_default }, + { "CNTR_RATE", 8, 12, &umr_bitfield_default }, + { "DISABLE_FLUSH", 13, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_PERFCOUNTER_MASK[] = { + { "SH0_MASK", 0, 15, &umr_bitfield_default }, + { "SH1_MASK", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_PERFCOUNTER_CTRL2[] = { + { "FORCE_EN", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSX_PERFCOUNTER0_SELECT[] = { + { "PERFCOUNTER_SELECT", 0, 9, &umr_bitfield_default }, + { "PERFCOUNTER_SELECT1", 10, 19, &umr_bitfield_default }, + { "CNTR_MODE", 20, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSX_PERFCOUNTER1_SELECT[] = { + { "PERFCOUNTER_SELECT", 0, 9, &umr_bitfield_default }, + { "PERFCOUNTER_SELECT1", 10, 19, &umr_bitfield_default }, + { "CNTR_MODE", 20, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSX_PERFCOUNTER2_SELECT[] = { + { "PERFCOUNTER_SELECT", 0, 9, &umr_bitfield_default }, + { "PERFCOUNTER_SELECT1", 10, 19, &umr_bitfield_default }, + { "CNTR_MODE", 20, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSX_PERFCOUNTER3_SELECT[] = { + { "PERFCOUNTER_SELECT", 0, 9, &umr_bitfield_default }, + { "PERFCOUNTER_SELECT1", 10, 19, &umr_bitfield_default }, + { "CNTR_MODE", 20, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSX_PERFCOUNTER0_SELECT1[] = { + { "PERFCOUNTER_SELECT2", 0, 9, &umr_bitfield_default }, + { "PERFCOUNTER_SELECT3", 10, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSX_PERFCOUNTER1_SELECT1[] = { + { "PERFCOUNTER_SELECT2", 0, 9, &umr_bitfield_default }, + { "PERFCOUNTER_SELECT3", 10, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_PERFCOUNTER0_SELECT[] = { + { "PERFCOUNTER_SELECT", 0, 9, &umr_bitfield_default }, + { "PERFCOUNTER_SELECT1", 10, 19, &umr_bitfield_default }, + { "CNTR_MODE", 20, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_PERFCOUNTER1_SELECT[] = { + { "PERFCOUNTER_SELECT", 0, 9, &umr_bitfield_default }, + { "PERFCOUNTER_SELECT1", 10, 19, &umr_bitfield_default }, + { "CNTR_MODE", 20, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_PERFCOUNTER2_SELECT[] = { + { "PERFCOUNTER_SELECT", 0, 9, &umr_bitfield_default }, + { "PERFCOUNTER_SELECT1", 10, 19, &umr_bitfield_default }, + { "CNTR_MODE", 20, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_PERFCOUNTER3_SELECT[] = { + { "PERFCOUNTER_SELECT", 0, 9, &umr_bitfield_default }, + { "PERFCOUNTER_SELECT1", 10, 19, &umr_bitfield_default }, + { "CNTR_MODE", 20, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDS_PERFCOUNTER0_SELECT1[] = { + { "PERFCOUNTER_SELECT2", 0, 9, &umr_bitfield_default }, + { "PERFCOUNTER_SELECT3", 10, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTA_PERFCOUNTER0_SELECT[] = { + { "PERF_SEL", 0, 7, &umr_bitfield_default }, + { "PERF_SEL1", 10, 17, &umr_bitfield_default }, + { "CNTR_MODE", 20, 23, &umr_bitfield_default }, + { "PERF_MODE1", 24, 27, &umr_bitfield_default }, + { "PERF_MODE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTA_PERFCOUNTER0_SELECT1[] = { + { "PERF_SEL2", 0, 7, &umr_bitfield_default }, + { "PERF_SEL3", 10, 17, &umr_bitfield_default }, + { "PERF_MODE3", 24, 27, &umr_bitfield_default }, + { "PERF_MODE2", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTA_PERFCOUNTER1_SELECT[] = { + { "PERF_SEL", 0, 7, &umr_bitfield_default }, + { "PERF_SEL1", 10, 17, &umr_bitfield_default }, + { "CNTR_MODE", 20, 23, &umr_bitfield_default }, + { "PERF_MODE1", 24, 27, &umr_bitfield_default }, + { "PERF_MODE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTD_PERFCOUNTER0_SELECT[] = { + { "PERF_SEL", 0, 7, &umr_bitfield_default }, + { "PERF_SEL1", 10, 17, &umr_bitfield_default }, + { "CNTR_MODE", 20, 23, &umr_bitfield_default }, + { "PERF_MODE1", 24, 27, &umr_bitfield_default }, + { "PERF_MODE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTD_PERFCOUNTER0_SELECT1[] = { + { "PERF_SEL2", 0, 7, &umr_bitfield_default }, + { "PERF_SEL3", 10, 17, &umr_bitfield_default }, + { "PERF_MODE3", 24, 27, &umr_bitfield_default }, + { "PERF_MODE2", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTD_PERFCOUNTER1_SELECT[] = { + { "PERF_SEL", 0, 7, &umr_bitfield_default }, + { "PERF_SEL1", 10, 17, &umr_bitfield_default }, + { "CNTR_MODE", 20, 23, &umr_bitfield_default }, + { "PERF_MODE1", 24, 27, &umr_bitfield_default }, + { "PERF_MODE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCP_PERFCOUNTER0_SELECT[] = { + { "PERF_SEL", 0, 9, &umr_bitfield_default }, + { "PERF_SEL1", 10, 19, &umr_bitfield_default }, + { "CNTR_MODE", 20, 23, &umr_bitfield_default }, + { "PERF_MODE1", 24, 27, &umr_bitfield_default }, + { "PERF_MODE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCP_PERFCOUNTER0_SELECT1[] = { + { "PERF_SEL2", 0, 9, &umr_bitfield_default }, + { "PERF_SEL3", 10, 19, &umr_bitfield_default }, + { "PERF_MODE3", 24, 27, &umr_bitfield_default }, + { "PERF_MODE2", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCP_PERFCOUNTER1_SELECT[] = { + { "PERF_SEL", 0, 9, &umr_bitfield_default }, + { "PERF_SEL1", 10, 19, &umr_bitfield_default }, + { "CNTR_MODE", 20, 23, &umr_bitfield_default }, + { "PERF_MODE1", 24, 27, &umr_bitfield_default }, + { "PERF_MODE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCP_PERFCOUNTER1_SELECT1[] = { + { "PERF_SEL2", 0, 9, &umr_bitfield_default }, + { "PERF_SEL3", 10, 19, &umr_bitfield_default }, + { "PERF_MODE3", 24, 27, &umr_bitfield_default }, + { "PERF_MODE2", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCP_PERFCOUNTER2_SELECT[] = { + { "PERF_SEL", 0, 9, &umr_bitfield_default }, + { "CNTR_MODE", 20, 23, &umr_bitfield_default }, + { "PERF_MODE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCP_PERFCOUNTER3_SELECT[] = { + { "PERF_SEL", 0, 9, &umr_bitfield_default }, + { "CNTR_MODE", 20, 23, &umr_bitfield_default }, + { "PERF_MODE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCC_PERFCOUNTER0_SELECT[] = { + { "PERF_SEL", 0, 9, &umr_bitfield_default }, + { "PERF_SEL1", 10, 19, &umr_bitfield_default }, + { "CNTR_MODE", 20, 23, &umr_bitfield_default }, + { "PERF_MODE1", 24, 27, &umr_bitfield_default }, + { "PERF_MODE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCC_PERFCOUNTER0_SELECT1[] = { + { "PERF_SEL2", 0, 9, &umr_bitfield_default }, + { "PERF_SEL3", 10, 19, &umr_bitfield_default }, + { "PERF_MODE2", 24, 27, &umr_bitfield_default }, + { "PERF_MODE3", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCC_PERFCOUNTER1_SELECT[] = { + { "PERF_SEL", 0, 9, &umr_bitfield_default }, + { "PERF_SEL1", 10, 19, &umr_bitfield_default }, + { "CNTR_MODE", 20, 23, &umr_bitfield_default }, + { "PERF_MODE1", 24, 27, &umr_bitfield_default }, + { "PERF_MODE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCC_PERFCOUNTER1_SELECT1[] = { + { "PERF_SEL2", 0, 9, &umr_bitfield_default }, + { "PERF_SEL3", 10, 19, &umr_bitfield_default }, + { "PERF_MODE2", 24, 27, &umr_bitfield_default }, + { "PERF_MODE3", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCC_PERFCOUNTER2_SELECT[] = { + { "PERF_SEL", 0, 9, &umr_bitfield_default }, + { "CNTR_MODE", 20, 23, &umr_bitfield_default }, + { "PERF_MODE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCC_PERFCOUNTER3_SELECT[] = { + { "PERF_SEL", 0, 9, &umr_bitfield_default }, + { "CNTR_MODE", 20, 23, &umr_bitfield_default }, + { "PERF_MODE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCA_PERFCOUNTER0_SELECT[] = { + { "PERF_SEL", 0, 9, &umr_bitfield_default }, + { "PERF_SEL1", 10, 19, &umr_bitfield_default }, + { "CNTR_MODE", 20, 23, &umr_bitfield_default }, + { "PERF_MODE1", 24, 27, &umr_bitfield_default }, + { "PERF_MODE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCA_PERFCOUNTER0_SELECT1[] = { + { "PERF_SEL2", 0, 9, &umr_bitfield_default }, + { "PERF_SEL3", 10, 19, &umr_bitfield_default }, + { "PERF_MODE2", 24, 27, &umr_bitfield_default }, + { "PERF_MODE3", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCA_PERFCOUNTER1_SELECT[] = { + { "PERF_SEL", 0, 9, &umr_bitfield_default }, + { "PERF_SEL1", 10, 19, &umr_bitfield_default }, + { "CNTR_MODE", 20, 23, &umr_bitfield_default }, + { "PERF_MODE1", 24, 27, &umr_bitfield_default }, + { "PERF_MODE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCA_PERFCOUNTER1_SELECT1[] = { + { "PERF_SEL2", 0, 9, &umr_bitfield_default }, + { "PERF_SEL3", 10, 19, &umr_bitfield_default }, + { "PERF_MODE2", 24, 27, &umr_bitfield_default }, + { "PERF_MODE3", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCA_PERFCOUNTER2_SELECT[] = { + { "PERF_SEL", 0, 9, &umr_bitfield_default }, + { "CNTR_MODE", 20, 23, &umr_bitfield_default }, + { "PERF_MODE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCA_PERFCOUNTER3_SELECT[] = { + { "PERF_SEL", 0, 9, &umr_bitfield_default }, + { "CNTR_MODE", 20, 23, &umr_bitfield_default }, + { "PERF_MODE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_PERFCOUNTER_FILTER[] = { + { "OP_FILTER_ENABLE", 0, 0, &umr_bitfield_default }, + { "OP_FILTER_SEL", 1, 3, &umr_bitfield_default }, + { "FORMAT_FILTER_ENABLE", 4, 4, &umr_bitfield_default }, + { "FORMAT_FILTER_SEL", 5, 9, &umr_bitfield_default }, + { "CLEAR_FILTER_ENABLE", 10, 10, &umr_bitfield_default }, + { "CLEAR_FILTER_SEL", 11, 11, &umr_bitfield_default }, + { "MRT_FILTER_ENABLE", 12, 12, &umr_bitfield_default }, + { "MRT_FILTER_SEL", 13, 15, &umr_bitfield_default }, + { "NUM_SAMPLES_FILTER_ENABLE", 17, 17, &umr_bitfield_default }, + { "NUM_SAMPLES_FILTER_SEL", 18, 20, &umr_bitfield_default }, + { "NUM_FRAGMENTS_FILTER_ENABLE", 21, 21, &umr_bitfield_default }, + { "NUM_FRAGMENTS_FILTER_SEL", 22, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_PERFCOUNTER0_SELECT[] = { + { "PERF_SEL", 0, 8, &umr_bitfield_default }, + { "PERF_SEL1", 10, 18, &umr_bitfield_default }, + { "CNTR_MODE", 20, 23, &umr_bitfield_default }, + { "PERF_MODE1", 24, 27, &umr_bitfield_default }, + { "PERF_MODE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_PERFCOUNTER0_SELECT1[] = { + { "PERF_SEL2", 0, 8, &umr_bitfield_default }, + { "PERF_SEL3", 10, 18, &umr_bitfield_default }, + { "PERF_MODE3", 24, 27, &umr_bitfield_default }, + { "PERF_MODE2", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_PERFCOUNTER1_SELECT[] = { + { "PERF_SEL", 0, 8, &umr_bitfield_default }, + { "PERF_MODE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_PERFCOUNTER2_SELECT[] = { + { "PERF_SEL", 0, 8, &umr_bitfield_default }, + { "PERF_MODE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_PERFCOUNTER3_SELECT[] = { + { "PERF_SEL", 0, 8, &umr_bitfield_default }, + { "PERF_MODE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_PERFCOUNTER0_SELECT[] = { + { "PERF_SEL", 0, 9, &umr_bitfield_default }, + { "PERF_SEL1", 10, 19, &umr_bitfield_default }, + { "CNTR_MODE", 20, 23, &umr_bitfield_default }, + { "PERF_MODE1", 24, 27, &umr_bitfield_default }, + { "PERF_MODE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_PERFCOUNTER0_SELECT1[] = { + { "PERF_SEL2", 0, 9, &umr_bitfield_default }, + { "PERF_SEL3", 10, 19, &umr_bitfield_default }, + { "PERF_MODE3", 24, 27, &umr_bitfield_default }, + { "PERF_MODE2", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_PERFCOUNTER1_SELECT[] = { + { "PERF_SEL", 0, 9, &umr_bitfield_default }, + { "PERF_SEL1", 10, 19, &umr_bitfield_default }, + { "CNTR_MODE", 20, 23, &umr_bitfield_default }, + { "PERF_MODE1", 24, 27, &umr_bitfield_default }, + { "PERF_MODE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_PERFCOUNTER1_SELECT1[] = { + { "PERF_SEL2", 0, 9, &umr_bitfield_default }, + { "PERF_SEL3", 10, 19, &umr_bitfield_default }, + { "PERF_MODE3", 24, 27, &umr_bitfield_default }, + { "PERF_MODE2", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_PERFCOUNTER2_SELECT[] = { + { "PERF_SEL", 0, 9, &umr_bitfield_default }, + { "PERF_SEL1", 10, 19, &umr_bitfield_default }, + { "CNTR_MODE", 20, 23, &umr_bitfield_default }, + { "PERF_MODE1", 24, 27, &umr_bitfield_default }, + { "PERF_MODE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_PERFCOUNTER3_SELECT[] = { + { "PERF_SEL", 0, 9, &umr_bitfield_default }, + { "PERF_SEL1", 10, 19, &umr_bitfield_default }, + { "CNTR_MODE", 20, 23, &umr_bitfield_default }, + { "PERF_MODE1", 24, 27, &umr_bitfield_default }, + { "PERF_MODE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SPM_PERFMON_CNTL[] = { + { "RESERVED1", 2, 11, &umr_bitfield_default }, + { "PERFMON_RING_MODE", 12, 13, &umr_bitfield_default }, + { "RESERVED", 14, 15, &umr_bitfield_default }, + { "PERFMON_SAMPLE_INTERVAL", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SPM_PERFMON_RING_BASE_LO[] = { + { "RING_BASE_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SPM_PERFMON_RING_BASE_HI[] = { + { "RING_BASE_HI", 0, 15, &umr_bitfield_default }, + { "RESERVED", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SPM_PERFMON_RING_SIZE[] = { + { "RING_BASE_SIZE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SPM_PERFMON_SEGMENT_SIZE[] = { + { "PERFMON_SEGMENT_SIZE", 0, 7, &umr_bitfield_default }, + { "RESERVED1", 8, 10, &umr_bitfield_default }, + { "GLOBAL_NUM_LINE", 11, 15, &umr_bitfield_default }, + { "SE0_NUM_LINE", 16, 20, &umr_bitfield_default }, + { "SE1_NUM_LINE", 21, 25, &umr_bitfield_default }, + { "SE2_NUM_LINE", 26, 30, &umr_bitfield_default }, + { "RESERVED", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SPM_SE_MUXSEL_ADDR[] = { + { "PERFMON_SEL_ADDR", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SPM_SE_MUXSEL_DATA[] = { + { "PERFMON_SEL_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY[] = { + { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default }, + { "RESERVED", 8, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY[] = { + { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default }, + { "RESERVED", 8, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY[] = { + { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default }, + { "RESERVED", 8, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY[] = { + { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default }, + { "RESERVED", 8, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY[] = { + { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default }, + { "RESERVED", 8, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY[] = { + { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default }, + { "RESERVED", 8, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY[] = { + { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default }, + { "RESERVED", 8, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY[] = { + { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default }, + { "RESERVED", 8, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY[] = { + { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default }, + { "RESERVED", 8, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY[] = { + { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default }, + { "RESERVED", 8, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY[] = { + { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default }, + { "RESERVED", 8, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY[] = { + { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default }, + { "RESERVED", 8, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY[] = { + { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default }, + { "RESERVED", 8, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY[] = { + { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default }, + { "RESERVED", 8, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY[] = { + { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default }, + { "RESERVED", 8, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY[] = { + { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default }, + { "RESERVED", 8, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY[] = { + { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default }, + { "RESERVED", 8, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY[] = { + { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default }, + { "RESERVED", 8, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SPM_GLOBAL_MUXSEL_ADDR[] = { + { "PERFMON_SEL_ADDR", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SPM_GLOBAL_MUXSEL_DATA[] = { + { "PERFMON_SEL_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SPM_RING_RDPTR[] = { + { "PERFMON_RING_RDPTR", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SPM_SEGMENT_THRESHOLD[] = { + { "NUM_SEGMENT_THRESHOLD", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SPM_RMI_PERFMON_SAMPLE_DELAY[] = { + { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default }, + { "RESERVED", 8, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_PERFMON_CLK_CNTL[] = { + { "PERFMON_CLOCK_STATE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_PERFMON_CNTL[] = { + { "PERFMON_STATE", 0, 2, &umr_bitfield_default }, + { "PERFMON_SAMPLE_ENABLE", 10, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_PERFCOUNTER0_SELECT[] = { + { "PERFCOUNTER_SELECT", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_PERFCOUNTER1_SELECT[] = { + { "PERFCOUNTER_SELECT", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPU_IOV_PERF_CNT_CNTL[] = { + { "ENABLE", 0, 0, &umr_bitfield_default }, + { "MODE_SELECT", 1, 1, &umr_bitfield_default }, + { "RESET", 2, 2, &umr_bitfield_default }, + { "RESERVED", 3, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPU_IOV_PERF_CNT_WR_ADDR[] = { + { "VFID", 0, 3, &umr_bitfield_default }, + { "CNT_ID", 4, 5, &umr_bitfield_default }, + { "RESERVED", 6, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPU_IOV_PERF_CNT_WR_DATA[] = { + { "DATA", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPU_IOV_PERF_CNT_RD_ADDR[] = { + { "VFID", 0, 3, &umr_bitfield_default }, + { "CNT_ID", 4, 5, &umr_bitfield_default }, + { "RESERVED", 6, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPU_IOV_PERF_CNT_RD_DATA[] = { + { "DATA", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRMI_PERFCOUNTER0_SELECT[] = { + { "PERF_SEL", 0, 8, &umr_bitfield_default }, + { "PERF_SEL1", 10, 18, &umr_bitfield_default }, + { "CNTR_MODE", 20, 23, &umr_bitfield_default }, + { "PERF_MODE1", 24, 27, &umr_bitfield_default }, + { "PERF_MODE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRMI_PERFCOUNTER0_SELECT1[] = { + { "PERF_SEL2", 0, 8, &umr_bitfield_default }, + { "PERF_SEL3", 10, 18, &umr_bitfield_default }, + { "PERF_MODE3", 24, 27, &umr_bitfield_default }, + { "PERF_MODE2", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRMI_PERFCOUNTER1_SELECT[] = { + { "PERF_SEL", 0, 8, &umr_bitfield_default }, + { "PERF_MODE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRMI_PERFCOUNTER2_SELECT[] = { + { "PERF_SEL", 0, 8, &umr_bitfield_default }, + { "PERF_SEL1", 10, 18, &umr_bitfield_default }, + { "CNTR_MODE", 20, 23, &umr_bitfield_default }, + { "PERF_MODE1", 24, 27, &umr_bitfield_default }, + { "PERF_MODE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRMI_PERFCOUNTER2_SELECT1[] = { + { "PERF_SEL2", 0, 8, &umr_bitfield_default }, + { "PERF_SEL3", 10, 18, &umr_bitfield_default }, + { "PERF_MODE3", 24, 27, &umr_bitfield_default }, + { "PERF_MODE2", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRMI_PERFCOUNTER3_SELECT[] = { + { "PERF_SEL", 0, 8, &umr_bitfield_default }, + { "PERF_MODE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRMI_PERF_COUNTER_CNTL[] = { + { "TRANS_BASED_PERF_EN_SEL", 0, 1, &umr_bitfield_default }, + { "EVENT_BASED_PERF_EN_SEL", 2, 3, &umr_bitfield_default }, + { "TC_PERF_EN_SEL", 4, 5, &umr_bitfield_default }, + { "PERF_EVENT_WINDOW_MASK0", 6, 7, &umr_bitfield_default }, + { "PERF_EVENT_WINDOW_MASK1", 8, 9, &umr_bitfield_default }, + { "PERF_COUNTER_CID", 10, 13, &umr_bitfield_default }, + { "PERF_COUNTER_VMID", 14, 18, &umr_bitfield_default }, + { "PERF_COUNTER_BURST_LENGTH_THRESHOLD", 19, 24, &umr_bitfield_default }, + { "PERF_SOFT_RESET", 25, 25, &umr_bitfield_default }, + { "PERF_CNTR_SPM_SEL", 26, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmATC_L2_PERFCOUNTER0_CFG[] = { + { "PERF_SEL", 0, 7, &umr_bitfield_default }, + { "PERF_SEL_END", 8, 15, &umr_bitfield_default }, + { "PERF_MODE", 24, 27, &umr_bitfield_default }, + { "ENABLE", 28, 28, &umr_bitfield_default }, + { "CLEAR", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmATC_L2_PERFCOUNTER1_CFG[] = { + { "PERF_SEL", 0, 7, &umr_bitfield_default }, + { "PERF_SEL_END", 8, 15, &umr_bitfield_default }, + { "PERF_MODE", 24, 27, &umr_bitfield_default }, + { "ENABLE", 28, 28, &umr_bitfield_default }, + { "CLEAR", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmATC_L2_PERFCOUNTER_RSLT_CNTL[] = { + { "PERF_COUNTER_SELECT", 0, 3, &umr_bitfield_default }, + { "START_TRIGGER", 8, 15, &umr_bitfield_default }, + { "STOP_TRIGGER", 16, 23, &umr_bitfield_default }, + { "ENABLE_ANY", 24, 24, &umr_bitfield_default }, + { "CLEAR_ALL", 25, 25, &umr_bitfield_default }, + { "STOP_ALL_ON_SATURATE", 26, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_L2_PERFCOUNTER0_CFG[] = { + { "PERF_SEL", 0, 7, &umr_bitfield_default }, + { "PERF_SEL_END", 8, 15, &umr_bitfield_default }, + { "PERF_MODE", 24, 27, &umr_bitfield_default }, + { "ENABLE", 28, 28, &umr_bitfield_default }, + { "CLEAR", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_L2_PERFCOUNTER1_CFG[] = { + { "PERF_SEL", 0, 7, &umr_bitfield_default }, + { "PERF_SEL_END", 8, 15, &umr_bitfield_default }, + { "PERF_MODE", 24, 27, &umr_bitfield_default }, + { "ENABLE", 28, 28, &umr_bitfield_default }, + { "CLEAR", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_L2_PERFCOUNTER2_CFG[] = { + { "PERF_SEL", 0, 7, &umr_bitfield_default }, + { "PERF_SEL_END", 8, 15, &umr_bitfield_default }, + { "PERF_MODE", 24, 27, &umr_bitfield_default }, + { "ENABLE", 28, 28, &umr_bitfield_default }, + { "CLEAR", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_L2_PERFCOUNTER3_CFG[] = { + { "PERF_SEL", 0, 7, &umr_bitfield_default }, + { "PERF_SEL_END", 8, 15, &umr_bitfield_default }, + { "PERF_MODE", 24, 27, &umr_bitfield_default }, + { "ENABLE", 28, 28, &umr_bitfield_default }, + { "CLEAR", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_L2_PERFCOUNTER4_CFG[] = { + { "PERF_SEL", 0, 7, &umr_bitfield_default }, + { "PERF_SEL_END", 8, 15, &umr_bitfield_default }, + { "PERF_MODE", 24, 27, &umr_bitfield_default }, + { "ENABLE", 28, 28, &umr_bitfield_default }, + { "CLEAR", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_L2_PERFCOUNTER5_CFG[] = { + { "PERF_SEL", 0, 7, &umr_bitfield_default }, + { "PERF_SEL_END", 8, 15, &umr_bitfield_default }, + { "PERF_MODE", 24, 27, &umr_bitfield_default }, + { "ENABLE", 28, 28, &umr_bitfield_default }, + { "CLEAR", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_L2_PERFCOUNTER6_CFG[] = { + { "PERF_SEL", 0, 7, &umr_bitfield_default }, + { "PERF_SEL_END", 8, 15, &umr_bitfield_default }, + { "PERF_MODE", 24, 27, &umr_bitfield_default }, + { "ENABLE", 28, 28, &umr_bitfield_default }, + { "CLEAR", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_L2_PERFCOUNTER7_CFG[] = { + { "PERF_SEL", 0, 7, &umr_bitfield_default }, + { "PERF_SEL_END", 8, 15, &umr_bitfield_default }, + { "PERF_MODE", 24, 27, &umr_bitfield_default }, + { "ENABLE", 28, 28, &umr_bitfield_default }, + { "CLEAR", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL[] = { + { "PERF_COUNTER_SELECT", 0, 3, &umr_bitfield_default }, + { "START_TRIGGER", 8, 15, &umr_bitfield_default }, + { "STOP_TRIGGER", 16, 23, &umr_bitfield_default }, + { "ENABLE_ANY", 24, 24, &umr_bitfield_default }, + { "CLEAR_ALL", 25, 25, &umr_bitfield_default }, + { "STOP_ALL_ON_SATURATE", 26, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_CNTL[] = { + { "RLC_ENABLE_F32", 0, 0, &umr_bitfield_default }, + { "FORCE_RETRY", 1, 1, &umr_bitfield_default }, + { "READ_CACHE_DISABLE", 2, 2, &umr_bitfield_default }, + { "RLC_STEP_F32", 3, 3, &umr_bitfield_default }, + { "RESERVED", 4, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_STAT[] = { + { "RLC_BUSY", 0, 0, &umr_bitfield_default }, + { "RLC_GPM_BUSY", 1, 1, &umr_bitfield_default }, + { "RLC_SPM_BUSY", 2, 2, &umr_bitfield_default }, + { "RLC_SRM_BUSY", 3, 3, &umr_bitfield_default }, + { "MC_BUSY", 4, 4, &umr_bitfield_default }, + { "RLC_THREAD_0_BUSY", 5, 5, &umr_bitfield_default }, + { "RLC_THREAD_1_BUSY", 6, 6, &umr_bitfield_default }, + { "RLC_THREAD_2_BUSY", 7, 7, &umr_bitfield_default }, + { "RESERVED", 8, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SAFE_MODE[] = { + { "CMD", 0, 0, &umr_bitfield_default }, + { "MESSAGE", 1, 4, &umr_bitfield_default }, + { "RESERVED1", 5, 7, &umr_bitfield_default }, + { "RESPONSE", 8, 11, &umr_bitfield_default }, + { "RESERVED", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_MEM_SLP_CNTL[] = { + { "RLC_MEM_LS_EN", 0, 0, &umr_bitfield_default }, + { "RLC_MEM_DS_EN", 1, 1, &umr_bitfield_default }, + { "RESERVED", 2, 6, &umr_bitfield_default }, + { "RLC_LS_DS_BUSY_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "RLC_MEM_LS_ON_DELAY", 8, 15, &umr_bitfield_default }, + { "RLC_MEM_LS_OFF_DELAY", 16, 23, &umr_bitfield_default }, + { "RESERVED1", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSMU_RLC_RESPONSE[] = { + { "RESP", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_RLCV_SAFE_MODE[] = { + { "CMD", 0, 0, &umr_bitfield_default }, + { "MESSAGE", 1, 4, &umr_bitfield_default }, + { "RESERVED1", 5, 7, &umr_bitfield_default }, + { "RESPONSE", 8, 11, &umr_bitfield_default }, + { "RESERVED", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SMU_SAFE_MODE[] = { + { "CMD", 0, 0, &umr_bitfield_default }, + { "MESSAGE", 1, 4, &umr_bitfield_default }, + { "RESERVED1", 5, 7, &umr_bitfield_default }, + { "RESPONSE", 8, 11, &umr_bitfield_default }, + { "RESERVED", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_RLCV_COMMAND[] = { + { "CMD", 0, 3, &umr_bitfield_default }, + { "RESERVED", 4, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_REFCLOCK_TIMESTAMP_LSB[] = { + { "TIMESTAMP_LSB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_REFCLOCK_TIMESTAMP_MSB[] = { + { "TIMESTAMP_MSB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPM_TIMER_INT_0[] = { + { "TIMER", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPM_TIMER_INT_1[] = { + { "TIMER", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPM_TIMER_INT_2[] = { + { "TIMER", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPM_TIMER_CTRL[] = { + { "TIMER_0_EN", 0, 0, &umr_bitfield_default }, + { "TIMER_1_EN", 1, 1, &umr_bitfield_default }, + { "TIMER_2_EN", 2, 2, &umr_bitfield_default }, + { "TIMER_3_EN", 3, 3, &umr_bitfield_default }, + { "RESERVED", 4, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_LB_CNTR_MAX[] = { + { "LB_CNTR_MAX", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPM_TIMER_STAT[] = { + { "TIMER_0_STAT", 0, 0, &umr_bitfield_default }, + { "TIMER_1_STAT", 1, 1, &umr_bitfield_default }, + { "TIMER_2_STAT", 2, 2, &umr_bitfield_default }, + { "TIMER_3_STAT", 3, 3, &umr_bitfield_default }, + { "RESERVED", 4, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPM_TIMER_INT_3[] = { + { "TIMER", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SERDES_WR_NONCU_MASTER_MASK_1[] = { + { "SE_MASTER_MASK_1", 0, 15, &umr_bitfield_default }, + { "GC_MASTER_MASK_1", 16, 16, &umr_bitfield_default }, + { "GC_GFX_MASTER_MASK_1", 17, 17, &umr_bitfield_default }, + { "TC0_1_MASTER_MASK", 18, 18, &umr_bitfield_default }, + { "RESERVED_1", 19, 19, &umr_bitfield_default }, + { "SPARE4_MASTER_MASK", 20, 20, &umr_bitfield_default }, + { "SPARE5_MASTER_MASK", 21, 21, &umr_bitfield_default }, + { "SPARE6_MASTER_MASK", 22, 22, &umr_bitfield_default }, + { "SPARE7_MASTER_MASK", 23, 23, &umr_bitfield_default }, + { "EA_1_MASTER_MASK", 24, 24, &umr_bitfield_default }, + { "RESERVED", 25, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SERDES_NONCU_MASTER_BUSY_1[] = { + { "SE_MASTER_BUSY_1", 0, 15, &umr_bitfield_default }, + { "GC_MASTER_BUSY_1", 16, 16, &umr_bitfield_default }, + { "GC_GFX_MASTER_BUSY_1", 17, 17, &umr_bitfield_default }, + { "TC0_MASTER_BUSY_1", 18, 18, &umr_bitfield_default }, + { "RESERVED_1", 19, 19, &umr_bitfield_default }, + { "SPARE4_MASTER_BUSY", 20, 20, &umr_bitfield_default }, + { "SPARE5_MASTER_BUSY", 21, 21, &umr_bitfield_default }, + { "SPARE6_MASTER_BUSY", 22, 22, &umr_bitfield_default }, + { "SPARE7_MASTER_BUSY", 23, 23, &umr_bitfield_default }, + { "EA_1_MASTER_BUSY", 24, 24, &umr_bitfield_default }, + { "RESERVED", 25, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_INT_STAT[] = { + { "LAST_CP_RLC_INT_ID", 0, 7, &umr_bitfield_default }, + { "CP_RLC_INT_PENDING", 8, 8, &umr_bitfield_default }, + { "RESERVED", 9, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_LB_CNTL[] = { + { "LOAD_BALANCE_ENABLE", 0, 0, &umr_bitfield_default }, + { "LB_CNT_CP_BUSY", 1, 1, &umr_bitfield_default }, + { "LB_CNT_SPIM_ACTIVE", 2, 2, &umr_bitfield_default }, + { "LB_CNT_REG_INC", 3, 3, &umr_bitfield_default }, + { "CU_MASK_USED_OFF_HYST", 4, 11, &umr_bitfield_default }, + { "RESERVED", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_MGCG_CTRL[] = { + { "MGCG_EN", 0, 0, &umr_bitfield_default }, + { "SILICON_EN", 1, 1, &umr_bitfield_default }, + { "SIMULATION_EN", 2, 2, &umr_bitfield_default }, + { "ON_DELAY", 3, 6, &umr_bitfield_default }, + { "OFF_HYSTERESIS", 7, 14, &umr_bitfield_default }, + { "GC_CAC_MGCG_CLK_CNTL", 15, 15, &umr_bitfield_default }, + { "SE_CAC_MGCG_CLK_CNTL", 16, 16, &umr_bitfield_default }, + { "SPARE", 17, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_LB_CNTR_INIT[] = { + { "LB_CNTR_INIT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_LOAD_BALANCE_CNTR[] = { + { "RLC_LOAD_BALANCE_CNTR", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_JUMP_TABLE_RESTORE[] = { + { "ADDR", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_PG_DELAY_2[] = { + { "SERDES_TIMEOUT_VALUE", 0, 7, &umr_bitfield_default }, + { "SERDES_CMD_DELAY", 8, 15, &umr_bitfield_default }, + { "PERCU_TIMEOUT_VALUE", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPU_CLOCK_COUNT_LSB[] = { + { "GPU_CLOCKS_LSB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPU_CLOCK_COUNT_MSB[] = { + { "GPU_CLOCKS_MSB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_CAPTURE_GPU_CLOCK_COUNT[] = { + { "CAPTURE", 0, 0, &umr_bitfield_default }, + { "RESERVED", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_UCODE_CNTL[] = { + { "RLC_UCODE_FLAGS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPM_THREAD_RESET[] = { + { "THREAD0_RESET", 0, 0, &umr_bitfield_default }, + { "THREAD1_RESET", 1, 1, &umr_bitfield_default }, + { "THREAD2_RESET", 2, 2, &umr_bitfield_default }, + { "THREAD3_RESET", 3, 3, &umr_bitfield_default }, + { "RESERVED", 4, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPM_CP_DMA_COMPLETE_T0[] = { + { "DATA", 0, 0, &umr_bitfield_default }, + { "RESERVED", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPM_CP_DMA_COMPLETE_T1[] = { + { "DATA", 0, 0, &umr_bitfield_default }, + { "RESERVED", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_FIREWALL_VIOLATION[] = { + { "ADDR", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPM_STAT[] = { + { "RLC_BUSY", 0, 0, &umr_bitfield_default }, + { "GFX_POWER_STATUS", 1, 1, &umr_bitfield_default }, + { "GFX_CLOCK_STATUS", 2, 2, &umr_bitfield_default }, + { "GFX_LS_STATUS", 3, 3, &umr_bitfield_default }, + { "GFX_PIPELINE_POWER_STATUS", 4, 4, &umr_bitfield_default }, + { "CNTX_IDLE_BEING_PROCESSED", 5, 5, &umr_bitfield_default }, + { "CNTX_BUSY_BEING_PROCESSED", 6, 6, &umr_bitfield_default }, + { "GFX_IDLE_BEING_PROCESSED", 7, 7, &umr_bitfield_default }, + { "CMP_BUSY_BEING_PROCESSED", 8, 8, &umr_bitfield_default }, + { "SAVING_REGISTERS", 9, 9, &umr_bitfield_default }, + { "RESTORING_REGISTERS", 10, 10, &umr_bitfield_default }, + { "GFX3D_BLOCKS_CHANGING_POWER_STATE", 11, 11, &umr_bitfield_default }, + { "CMP_BLOCKS_CHANGING_POWER_STATE", 12, 12, &umr_bitfield_default }, + { "STATIC_CU_POWERING_UP", 13, 13, &umr_bitfield_default }, + { "STATIC_CU_POWERING_DOWN", 14, 14, &umr_bitfield_default }, + { "DYN_CU_POWERING_UP", 15, 15, &umr_bitfield_default }, + { "DYN_CU_POWERING_DOWN", 16, 16, &umr_bitfield_default }, + { "ABORTED_PD_SEQUENCE", 17, 17, &umr_bitfield_default }, + { "CMP_power_status", 18, 18, &umr_bitfield_default }, + { "GFX_LS_STATUS_3D", 19, 19, &umr_bitfield_default }, + { "GFX_CLOCK_STATUS_3D", 20, 20, &umr_bitfield_default }, + { "MGCG_OVERRIDE_STATUS", 21, 21, &umr_bitfield_default }, + { "RLC_EXEC_ROM_CODE", 22, 22, &umr_bitfield_default }, + { "RESERVED", 23, 23, &umr_bitfield_default }, + { "PG_ERROR_STATUS", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPU_CLOCK_32_RES_SEL[] = { + { "RES_SEL", 0, 5, &umr_bitfield_default }, + { "RESERVED", 6, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPU_CLOCK_32[] = { + { "GPU_CLOCK_32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_PG_CNTL[] = { + { "GFX_POWER_GATING_ENABLE", 0, 0, &umr_bitfield_default }, + { "GFX_POWER_GATING_SRC", 1, 1, &umr_bitfield_default }, + { "DYN_PER_CU_PG_ENABLE", 2, 2, &umr_bitfield_default }, + { "STATIC_PER_CU_PG_ENABLE", 3, 3, &umr_bitfield_default }, + { "GFX_PIPELINE_PG_ENABLE", 4, 4, &umr_bitfield_default }, + { "RESERVED", 5, 13, &umr_bitfield_default }, + { "PG_OVERRIDE", 14, 14, &umr_bitfield_default }, + { "CP_PG_DISABLE", 15, 15, &umr_bitfield_default }, + { "CHUB_HANDSHAKE_ENABLE", 16, 16, &umr_bitfield_default }, + { "SMU_CLK_SLOWDOWN_ON_PU_ENABLE", 17, 17, &umr_bitfield_default }, + { "SMU_CLK_SLOWDOWN_ON_PD_ENABLE", 18, 18, &umr_bitfield_default }, + { "SMU_HANDSHAKE_ENABLE", 19, 19, &umr_bitfield_default }, + { "RESERVED1", 20, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPM_THREAD_PRIORITY[] = { + { "THREAD0_PRIORITY", 0, 7, &umr_bitfield_default }, + { "THREAD1_PRIORITY", 8, 15, &umr_bitfield_default }, + { "THREAD2_PRIORITY", 16, 23, &umr_bitfield_default }, + { "THREAD3_PRIORITY", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPM_THREAD_ENABLE[] = { + { "THREAD0_ENABLE", 0, 0, &umr_bitfield_default }, + { "THREAD1_ENABLE", 1, 1, &umr_bitfield_default }, + { "THREAD2_ENABLE", 2, 2, &umr_bitfield_default }, + { "THREAD3_ENABLE", 3, 3, &umr_bitfield_default }, + { "RESERVED", 4, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_CGTT_MGCG_OVERRIDE[] = { + { "CPF_CGTT_SCLK_OVERRIDE", 0, 0, &umr_bitfield_default }, + { "RLC_CGTT_SCLK_OVERRIDE", 1, 1, &umr_bitfield_default }, + { "GFXIP_MGCG_OVERRIDE", 2, 2, &umr_bitfield_default }, + { "GFXIP_CGCG_OVERRIDE", 3, 3, &umr_bitfield_default }, + { "GFXIP_CGLS_OVERRIDE", 4, 4, &umr_bitfield_default }, + { "GRBM_CGTT_SCLK_OVERRIDE", 5, 5, &umr_bitfield_default }, + { "GFXIP_MGLS_OVERRIDE", 6, 6, &umr_bitfield_default }, + { "GFXIP_GFX3D_CG_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "RESERVED", 8, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_CGCG_CGLS_CTRL[] = { + { "CGCG_EN", 0, 0, &umr_bitfield_default }, + { "CGLS_EN", 1, 1, &umr_bitfield_default }, + { "CGLS_REP_COMPANSAT_DELAY", 2, 7, &umr_bitfield_default }, + { "CGCG_GFX_IDLE_THRESHOLD", 8, 26, &umr_bitfield_default }, + { "CGCG_CONTROLLER", 27, 27, &umr_bitfield_default }, + { "CGCG_REG_CTRL", 28, 28, &umr_bitfield_default }, + { "SLEEP_MODE", 29, 30, &umr_bitfield_default }, + { "SIM_SILICON_EN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_CGCG_RAMP_CTRL[] = { + { "DOWN_DIV_START_UNIT", 0, 3, &umr_bitfield_default }, + { "DOWN_DIV_STEP_UNIT", 4, 7, &umr_bitfield_default }, + { "UP_DIV_START_UNIT", 8, 11, &umr_bitfield_default }, + { "UP_DIV_STEP_UNIT", 12, 15, &umr_bitfield_default }, + { "STEP_DELAY_CNT", 16, 27, &umr_bitfield_default }, + { "STEP_DELAY_UNIT", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_DYN_PG_STATUS[] = { + { "PG_STATUS_CU_MASK", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_DYN_PG_REQUEST[] = { + { "PG_REQUEST_CU_MASK", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_PG_DELAY[] = { + { "POWER_UP_DELAY", 0, 7, &umr_bitfield_default }, + { "POWER_DOWN_DELAY", 8, 15, &umr_bitfield_default }, + { "CMD_PROPAGATE_DELAY", 16, 23, &umr_bitfield_default }, + { "MEM_SLEEP_DELAY", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_CU_STATUS[] = { + { "WORK_PENDING", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_LB_INIT_CU_MASK[] = { + { "INIT_CU_MASK", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_LB_ALWAYS_ACTIVE_CU_MASK[] = { + { "ALWAYS_ACTIVE_CU_MASK", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_LB_PARAMS[] = { + { "SKIP_L2_CHECK", 0, 0, &umr_bitfield_default }, + { "FIFO_SAMPLES", 1, 7, &umr_bitfield_default }, + { "PG_IDLE_SAMPLES", 8, 15, &umr_bitfield_default }, + { "PG_IDLE_SAMPLE_INTERVAL", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_THREAD1_DELAY[] = { + { "CU_IDEL_DELAY", 0, 7, &umr_bitfield_default }, + { "LBPW_INNER_LOOP_DELAY", 8, 15, &umr_bitfield_default }, + { "LBPW_OUTER_LOOP_DELAY", 16, 23, &umr_bitfield_default }, + { "SPARE", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_PG_ALWAYS_ON_CU_MASK[] = { + { "AON_CU_MASK", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_MAX_PG_CU[] = { + { "MAX_POWERED_UP_CU", 0, 7, &umr_bitfield_default }, + { "SPARE", 8, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_AUTO_PG_CTRL[] = { + { "AUTO_PG_EN", 0, 0, &umr_bitfield_default }, + { "AUTO_GRBM_REG_SAVE_ON_IDLE_EN", 1, 1, &umr_bitfield_default }, + { "AUTO_WAKE_UP_EN", 2, 2, &umr_bitfield_default }, + { "GRBM_REG_SAVE_GFX_IDLE_THRESHOLD", 3, 18, &umr_bitfield_default }, + { "PG_AFTER_GRBM_REG_SAVE_THRESHOLD", 19, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SMU_GRBM_REG_SAVE_CTRL[] = { + { "START_GRBM_REG_SAVE", 0, 0, &umr_bitfield_default }, + { "SPARE", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SERDES_RD_MASTER_INDEX[] = { + { "CU_ID", 0, 3, &umr_bitfield_default }, + { "SH_ID", 4, 5, &umr_bitfield_default }, + { "SE_ID", 6, 8, &umr_bitfield_default }, + { "SE_NONCU_ID", 9, 11, &umr_bitfield_default }, + { "SE_NONCU", 12, 12, &umr_bitfield_default }, + { "NON_SE", 13, 16, &umr_bitfield_default }, + { "DATA_REG_ID", 17, 18, &umr_bitfield_default }, + { "SPARE", 19, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SERDES_RD_DATA_0[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SERDES_RD_DATA_1[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SERDES_RD_DATA_2[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SERDES_WR_CU_MASTER_MASK[] = { + { "MASTER_MASK", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SERDES_WR_NONCU_MASTER_MASK[] = { + { "SE_MASTER_MASK", 0, 15, &umr_bitfield_default }, + { "GC_MASTER_MASK", 16, 16, &umr_bitfield_default }, + { "GC_GFX_MASTER_MASK", 17, 17, &umr_bitfield_default }, + { "TC0_MASTER_MASK", 18, 18, &umr_bitfield_default }, + { "TC1_MASTER_MASK", 19, 19, &umr_bitfield_default }, + { "SPARE0_MASTER_MASK", 20, 20, &umr_bitfield_default }, + { "SPARE1_MASTER_MASK", 21, 21, &umr_bitfield_default }, + { "SPARE2_MASTER_MASK", 22, 22, &umr_bitfield_default }, + { "SPARE3_MASTER_MASK", 23, 23, &umr_bitfield_default }, + { "EA_0_MASTER_MASK", 24, 24, &umr_bitfield_default }, + { "TC2_MASTER_MASK", 25, 25, &umr_bitfield_default }, + { "RESERVED", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SERDES_WR_CTRL[] = { + { "BPM_ADDR", 0, 7, &umr_bitfield_default }, + { "POWER_DOWN", 8, 8, &umr_bitfield_default }, + { "POWER_UP", 9, 9, &umr_bitfield_default }, + { "P1_SELECT", 10, 10, &umr_bitfield_default }, + { "P2_SELECT", 11, 11, &umr_bitfield_default }, + { "WRITE_COMMAND", 12, 12, &umr_bitfield_default }, + { "READ_COMMAND", 13, 13, &umr_bitfield_default }, + { "RDDATA_RESET", 14, 14, &umr_bitfield_default }, + { "SHORT_FORMAT", 15, 15, &umr_bitfield_default }, + { "BPM_DATA", 16, 25, &umr_bitfield_default }, + { "SRBM_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "RSVD_BPM_ADDR", 27, 27, &umr_bitfield_default }, + { "REG_ADDR", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SERDES_WR_DATA[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SERDES_CU_MASTER_BUSY[] = { + { "BUSY_BUSY", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SERDES_NONCU_MASTER_BUSY[] = { + { "SE_MASTER_BUSY", 0, 15, &umr_bitfield_default }, + { "GC_MASTER_BUSY", 16, 16, &umr_bitfield_default }, + { "GC_GFX_MASTER_BUSY", 17, 17, &umr_bitfield_default }, + { "TC0_MASTER_BUSY", 18, 18, &umr_bitfield_default }, + { "TC1_MASTER_BUSY", 19, 19, &umr_bitfield_default }, + { "SPARE0_MASTER_BUSY", 20, 20, &umr_bitfield_default }, + { "SPARE1_MASTER_BUSY", 21, 21, &umr_bitfield_default }, + { "SPARE2_MASTER_BUSY", 22, 22, &umr_bitfield_default }, + { "SPARE3_MASTER_BUSY", 23, 23, &umr_bitfield_default }, + { "EA_0_MASTER_BUSY", 24, 24, &umr_bitfield_default }, + { "TC2_MASTER_BUSY", 25, 25, &umr_bitfield_default }, + { "RESERVED", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPM_GENERAL_0[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPM_GENERAL_1[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPM_GENERAL_2[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPM_GENERAL_3[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPM_GENERAL_4[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPM_GENERAL_5[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPM_GENERAL_6[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPM_GENERAL_7[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPM_SCRATCH_ADDR[] = { + { "ADDR", 0, 8, &umr_bitfield_default }, + { "RESERVED", 9, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPM_SCRATCH_DATA[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_STATIC_PG_STATUS[] = { + { "PG_STATUS_CU_MASK", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SPM_MC_CNTL[] = { + { "RLC_SPM_VMID", 0, 3, &umr_bitfield_default }, + { "RLC_SPM_POLICY", 4, 4, &umr_bitfield_default }, + { "RLC_SPM_PERF_CNTR", 5, 5, &umr_bitfield_default }, + { "RLC_SPM_FED", 6, 6, &umr_bitfield_default }, + { "RLC_SPM_MTYPE_OVER", 7, 7, &umr_bitfield_default }, + { "RLC_SPM_MTYPE", 8, 9, &umr_bitfield_default }, + { "RESERVED", 10, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SPM_INT_CNTL[] = { + { "RLC_SPM_INT_CNTL", 0, 0, &umr_bitfield_default }, + { "RESERVED", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SPM_INT_STATUS[] = { + { "RLC_SPM_INT_STATUS", 0, 0, &umr_bitfield_default }, + { "RESERVED", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SMU_MESSAGE[] = { + { "CMD", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPM_LOG_SIZE[] = { + { "SIZE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_PG_DELAY_3[] = { + { "CGCG_ACTIVE_BEFORE_CGPG", 0, 7, &umr_bitfield_default }, + { "RESERVED", 8, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPR_REG1[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPR_REG2[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPM_LOG_CONT[] = { + { "CONT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPM_INT_DISABLE_TH0[] = { + { "DISABLE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPM_INT_DISABLE_TH1[] = { + { "DISABLE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPM_INT_FORCE_TH0[] = { + { "FORCE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPM_INT_FORCE_TH1[] = { + { "FORCE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SRM_CNTL[] = { + { "SRM_ENABLE", 0, 0, &umr_bitfield_default }, + { "AUTO_INCR_ADDR", 1, 1, &umr_bitfield_default }, + { "RESERVED", 2, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SRM_ARAM_ADDR[] = { + { "ADDR", 0, 11, &umr_bitfield_default }, + { "RESERVED", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SRM_ARAM_DATA[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SRM_DRAM_ADDR[] = { + { "ADDR", 0, 11, &umr_bitfield_default }, + { "RESERVED", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SRM_DRAM_DATA[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SRM_GPM_COMMAND[] = { + { "OP", 0, 0, &umr_bitfield_default }, + { "INDEX_CNTL", 1, 1, &umr_bitfield_default }, + { "INDEX_CNTL_NUM", 2, 4, &umr_bitfield_default }, + { "SIZE", 5, 16, &umr_bitfield_default }, + { "START_OFFSET", 17, 28, &umr_bitfield_default }, + { "RESERVED1", 29, 30, &umr_bitfield_default }, + { "DEST_MEMORY", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SRM_GPM_COMMAND_STATUS[] = { + { "FIFO_EMPTY", 0, 0, &umr_bitfield_default }, + { "FIFO_FULL", 1, 1, &umr_bitfield_default }, + { "RESERVED", 2, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SRM_RLCV_COMMAND[] = { + { "OP", 0, 0, &umr_bitfield_default }, + { "RESERVED", 1, 3, &umr_bitfield_default }, + { "SIZE", 4, 15, &umr_bitfield_default }, + { "START_OFFSET", 16, 27, &umr_bitfield_default }, + { "RESERVED1", 28, 30, &umr_bitfield_default }, + { "DEST_MEMORY", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SRM_RLCV_COMMAND_STATUS[] = { + { "FIFO_EMPTY", 0, 0, &umr_bitfield_default }, + { "FIFO_FULL", 1, 1, &umr_bitfield_default }, + { "RESERVED", 2, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SRM_INDEX_CNTL_ADDR_0[] = { + { "ADDRESS", 0, 15, &umr_bitfield_default }, + { "RESERVED", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SRM_INDEX_CNTL_ADDR_1[] = { + { "ADDRESS", 0, 15, &umr_bitfield_default }, + { "RESERVED", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SRM_INDEX_CNTL_ADDR_2[] = { + { "ADDRESS", 0, 15, &umr_bitfield_default }, + { "RESERVED", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SRM_INDEX_CNTL_ADDR_3[] = { + { "ADDRESS", 0, 15, &umr_bitfield_default }, + { "RESERVED", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SRM_INDEX_CNTL_ADDR_4[] = { + { "ADDRESS", 0, 15, &umr_bitfield_default }, + { "RESERVED", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SRM_INDEX_CNTL_ADDR_5[] = { + { "ADDRESS", 0, 15, &umr_bitfield_default }, + { "RESERVED", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SRM_INDEX_CNTL_ADDR_6[] = { + { "ADDRESS", 0, 15, &umr_bitfield_default }, + { "RESERVED", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SRM_INDEX_CNTL_ADDR_7[] = { + { "ADDRESS", 0, 15, &umr_bitfield_default }, + { "RESERVED", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SRM_INDEX_CNTL_DATA_0[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SRM_INDEX_CNTL_DATA_1[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SRM_INDEX_CNTL_DATA_2[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SRM_INDEX_CNTL_DATA_3[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SRM_INDEX_CNTL_DATA_4[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SRM_INDEX_CNTL_DATA_5[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SRM_INDEX_CNTL_DATA_6[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SRM_INDEX_CNTL_DATA_7[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SRM_STAT[] = { + { "SRM_BUSY", 0, 0, &umr_bitfield_default }, + { "SRM_BUSY_DELAY", 1, 1, &umr_bitfield_default }, + { "RESERVED", 2, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SRM_GPM_ABORT[] = { + { "ABORT", 0, 0, &umr_bitfield_default }, + { "RESERVED", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_CSIB_ADDR_LO[] = { + { "ADDRESS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_CSIB_ADDR_HI[] = { + { "ADDRESS", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_CSIB_LENGTH[] = { + { "LENGTH", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SMU_COMMAND[] = { + { "CMD", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_CP_SCHEDULERS[] = { + { "scheduler0", 0, 7, &umr_bitfield_default }, + { "scheduler1", 8, 15, &umr_bitfield_default }, + { "scheduler2", 16, 23, &umr_bitfield_default }, + { "scheduler3", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SMU_ARGUMENT_1[] = { + { "ARG", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SMU_ARGUMENT_2[] = { + { "ARG", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPM_GENERAL_8[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPM_GENERAL_9[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPM_GENERAL_10[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPM_GENERAL_11[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPM_GENERAL_12[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPM_UTCL1_CNTL_0[] = { + { "XNACK_REDO_TIMER_CNT", 0, 19, &umr_bitfield_default }, + { "DROP_MODE", 24, 24, &umr_bitfield_default }, + { "BYPASS", 25, 25, &umr_bitfield_default }, + { "INVALIDATE", 26, 26, &umr_bitfield_default }, + { "FRAG_LIMIT_MODE", 27, 27, &umr_bitfield_default }, + { "FORCE_SNOOP", 28, 28, &umr_bitfield_default }, + { "FORCE_SD_VMID_DIRTY", 29, 29, &umr_bitfield_default }, + { "RESERVED", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPM_UTCL1_CNTL_1[] = { + { "XNACK_REDO_TIMER_CNT", 0, 19, &umr_bitfield_default }, + { "DROP_MODE", 24, 24, &umr_bitfield_default }, + { "BYPASS", 25, 25, &umr_bitfield_default }, + { "INVALIDATE", 26, 26, &umr_bitfield_default }, + { "FRAG_LIMIT_MODE", 27, 27, &umr_bitfield_default }, + { "FORCE_SNOOP", 28, 28, &umr_bitfield_default }, + { "FORCE_SD_VMID_DIRTY", 29, 29, &umr_bitfield_default }, + { "RESERVED", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPM_UTCL1_CNTL_2[] = { + { "XNACK_REDO_TIMER_CNT", 0, 19, &umr_bitfield_default }, + { "DROP_MODE", 24, 24, &umr_bitfield_default }, + { "BYPASS", 25, 25, &umr_bitfield_default }, + { "INVALIDATE", 26, 26, &umr_bitfield_default }, + { "FRAG_LIMIT_MODE", 27, 27, &umr_bitfield_default }, + { "FORCE_SNOOP", 28, 28, &umr_bitfield_default }, + { "FORCE_SD_VMID_DIRTY", 29, 29, &umr_bitfield_default }, + { "RESERVED", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SPM_UTCL1_CNTL[] = { + { "XNACK_REDO_TIMER_CNT", 0, 19, &umr_bitfield_default }, + { "DROP_MODE", 24, 24, &umr_bitfield_default }, + { "BYPASS", 25, 25, &umr_bitfield_default }, + { "INVALIDATE", 26, 26, &umr_bitfield_default }, + { "FRAG_LIMIT_MODE", 27, 27, &umr_bitfield_default }, + { "FORCE_SNOOP", 28, 28, &umr_bitfield_default }, + { "FORCE_SD_VMID_DIRTY", 29, 29, &umr_bitfield_default }, + { "RESERVED", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_UTCL1_STATUS_2[] = { + { "GPM_TH0_UTCL1_BUSY", 0, 0, &umr_bitfield_default }, + { "GPM_TH1_UTCL1_BUSY", 1, 1, &umr_bitfield_default }, + { "GPM_TH2_UTCL1_BUSY", 2, 2, &umr_bitfield_default }, + { "SPM_UTCL1_BUSY", 3, 3, &umr_bitfield_default }, + { "PREWALKER_UTCL1_BUSY", 4, 4, &umr_bitfield_default }, + { "GPM_TH0_UTCL1_StallOnTrans", 5, 5, &umr_bitfield_default }, + { "GPM_TH1_UTCL1_StallOnTrans", 6, 6, &umr_bitfield_default }, + { "GPM_TH2_UTCL1_StallOnTrans", 7, 7, &umr_bitfield_default }, + { "SPM_UTCL1_StallOnTrans", 8, 8, &umr_bitfield_default }, + { "PREWALKER_UTCL1_StallOnTrans", 9, 9, &umr_bitfield_default }, + { "RESERVED", 10, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_LB_THR_CONFIG_2[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_LB_THR_CONFIG_3[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_LB_THR_CONFIG_4[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SPM_UTCL1_ERROR_1[] = { + { "Translated_ReqError", 0, 1, &umr_bitfield_default }, + { "Translated_ReqErrorVmid", 2, 5, &umr_bitfield_default }, + { "Translated_ReqErrorAddr_MSB", 6, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SPM_UTCL1_ERROR_2[] = { + { "Translated_ReqErrorAddr_LSB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPM_UTCL1_TH0_ERROR_1[] = { + { "Translated_ReqError", 0, 1, &umr_bitfield_default }, + { "Translated_ReqErrorVmid", 2, 5, &umr_bitfield_default }, + { "Translated_ReqErrorAddr_MSB", 6, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_LB_THR_CONFIG_1[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPM_UTCL1_TH0_ERROR_2[] = { + { "Translated_ReqErrorAddr_LSB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPM_UTCL1_TH1_ERROR_1[] = { + { "Translated_ReqError", 0, 1, &umr_bitfield_default }, + { "Translated_ReqErrorVmid", 2, 5, &umr_bitfield_default }, + { "Translated_ReqErrorAddr_MSB", 6, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPM_UTCL1_TH1_ERROR_2[] = { + { "Translated_ReqErrorAddr_LSB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPM_UTCL1_TH2_ERROR_1[] = { + { "Translated_ReqError", 0, 1, &umr_bitfield_default }, + { "Translated_ReqErrorVmid", 2, 5, &umr_bitfield_default }, + { "Translated_ReqErrorAddr_MSB", 6, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPM_UTCL1_TH2_ERROR_2[] = { + { "Translated_ReqErrorAddr_LSB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_CGCG_CGLS_CTRL_3D[] = { + { "CGCG_EN", 0, 0, &umr_bitfield_default }, + { "CGLS_EN", 1, 1, &umr_bitfield_default }, + { "CGLS_REP_COMPANSAT_DELAY", 2, 7, &umr_bitfield_default }, + { "CGCG_GFX_IDLE_THRESHOLD", 8, 26, &umr_bitfield_default }, + { "CGCG_CONTROLLER", 27, 27, &umr_bitfield_default }, + { "CGCG_REG_CTRL", 28, 28, &umr_bitfield_default }, + { "SLEEP_MODE", 29, 30, &umr_bitfield_default }, + { "SIM_SILICON_EN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_CGCG_RAMP_CTRL_3D[] = { + { "DOWN_DIV_START_UNIT", 0, 3, &umr_bitfield_default }, + { "DOWN_DIV_STEP_UNIT", 4, 7, &umr_bitfield_default }, + { "UP_DIV_START_UNIT", 8, 11, &umr_bitfield_default }, + { "UP_DIV_STEP_UNIT", 12, 15, &umr_bitfield_default }, + { "STEP_DELAY_CNT", 16, 27, &umr_bitfield_default }, + { "STEP_DELAY_UNIT", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SEMAPHORE_0[] = { + { "CLIENT_ID", 0, 4, &umr_bitfield_default }, + { "RESERVED", 5, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SEMAPHORE_1[] = { + { "CLIENT_ID", 0, 4, &umr_bitfield_default }, + { "RESERVED", 5, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_CP_EOF_INT[] = { + { "INTERRUPT", 0, 0, &umr_bitfield_default }, + { "RESERVED", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_CP_EOF_INT_CNT[] = { + { "CNT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_SPARE_INT[] = { + { "INTERRUPT", 0, 0, &umr_bitfield_default }, + { "RESERVED", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_PREWALKER_UTCL1_CNTL[] = { + { "XNACK_REDO_TIMER_CNT", 0, 19, &umr_bitfield_default }, + { "DROP_MODE", 24, 24, &umr_bitfield_default }, + { "BYPASS", 25, 25, &umr_bitfield_default }, + { "INVALIDATE", 26, 26, &umr_bitfield_default }, + { "FRAG_LIMIT_MODE", 27, 27, &umr_bitfield_default }, + { "FORCE_SNOOP", 28, 28, &umr_bitfield_default }, + { "FORCE_SD_VMID_DIRTY", 29, 29, &umr_bitfield_default }, + { "RESERVED", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_PREWALKER_UTCL1_TRIG[] = { + { "VALID", 0, 0, &umr_bitfield_default }, + { "VMID", 1, 4, &umr_bitfield_default }, + { "PRIME_MODE", 5, 5, &umr_bitfield_default }, + { "READ_PERM", 6, 6, &umr_bitfield_default }, + { "WRITE_PERM", 7, 7, &umr_bitfield_default }, + { "EXEC_PERM", 8, 8, &umr_bitfield_default }, + { "RESERVED", 9, 30, &umr_bitfield_default }, + { "READY", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_PREWALKER_UTCL1_ADDR_LSB[] = { + { "ADDR_LSB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_PREWALKER_UTCL1_ADDR_MSB[] = { + { "ADDR_MSB", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_PREWALKER_UTCL1_SIZE_LSB[] = { + { "SIZE_LSB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_PREWALKER_UTCL1_SIZE_MSB[] = { + { "SIZE_MSB", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_UTCL1_STATUS[] = { + { "FAULT_DETECTED", 0, 0, &umr_bitfield_default }, + { "RETRY_DETECTED", 1, 1, &umr_bitfield_default }, + { "PRT_DETECTED", 2, 2, &umr_bitfield_default }, + { "RESERVED", 3, 7, &umr_bitfield_default }, + { "FAULT_UTCL1ID", 8, 13, &umr_bitfield_default }, + { "RESERVED_1", 14, 15, &umr_bitfield_default }, + { "RETRY_UTCL1ID", 16, 21, &umr_bitfield_default }, + { "RESERVED_2", 22, 23, &umr_bitfield_default }, + { "PRT_UTCL1ID", 24, 29, &umr_bitfield_default }, + { "RESERVED_3", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_R2I_CNTL_0[] = { + { "Data", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_R2I_CNTL_1[] = { + { "Data", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_R2I_CNTL_2[] = { + { "Data", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_R2I_CNTL_3[] = { + { "Data", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_UTCL2_CNTL[] = { + { "MTYPE_NO_PTE_MODE", 0, 0, &umr_bitfield_default }, + { "RESERVED", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_LBPW_CU_STAT[] = { + { "MAX_CU", 0, 15, &umr_bitfield_default }, + { "ON_CU", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_DS_CNTL[] = { + { "GFX_CLK_DS_RLC_BUSY_MASK", 0, 0, &umr_bitfield_default }, + { "GFX_CLK_DS_CP_BUSY_MASK", 1, 1, &umr_bitfield_default }, + { "RESRVED", 2, 15, &umr_bitfield_default }, + { "SOC_CLK_DS_RLC_BUSY_MASK", 16, 16, &umr_bitfield_default }, + { "SOC_CLK_DS_CP_BUSY_MASK", 17, 17, &umr_bitfield_default }, + { "RESRVED_1", 18, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_RLCV_SPARE_INT[] = { + { "INTERRUPT", 0, 0, &umr_bitfield_default }, + { "RESERVED", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_SM_CTRL_REG[] = { + { "ON_SEQ_DELAY", 0, 3, &umr_bitfield_default }, + { "OFF_SEQ_DELAY", 4, 11, &umr_bitfield_default }, + { "MGCG_ENABLED", 12, 12, &umr_bitfield_default }, + { "BASE_MODE", 16, 16, &umr_bitfield_default }, + { "SM_MODE", 17, 19, &umr_bitfield_default }, + { "SM_MODE_ENABLE", 20, 20, &umr_bitfield_default }, + { "OVERRIDE", 21, 21, &umr_bitfield_default }, + { "LS_OVERRIDE", 22, 22, &umr_bitfield_default }, + { "ON_MONITOR_ADD_EN", 23, 23, &umr_bitfield_default }, + { "ON_MONITOR_ADD", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_RD_CTRL_REG[] = { + { "ROW_MUX_SEL", 0, 4, &umr_bitfield_default }, + { "REG_MUX_SEL", 8, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_RD_REG[] = { + { "READ_DATA", 0, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_TCC_DISABLE[] = { + { "TCC_DISABLE", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_USER_TCC_DISABLE[] = { + { "TCC_DISABLE", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU0_SP0_CTRL_REG[] = { + { "SP00", 0, 6, &umr_bitfield_default }, + { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "SP01", 16, 22, &umr_bitfield_default }, + { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU0_LDS_SQ_CTRL_REG[] = { + { "LDS", 0, 6, &umr_bitfield_default }, + { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "SQ", 16, 22, &umr_bitfield_default }, + { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU0_TA_SQC_CTRL_REG[] = { + { "TA", 0, 6, &umr_bitfield_default }, + { "TA_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "SQC", 16, 22, &umr_bitfield_default }, + { "SQC_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "SQC_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "SQC_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "SQC_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU0_SP1_CTRL_REG[] = { + { "SP10", 0, 6, &umr_bitfield_default }, + { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "SP11", 16, 22, &umr_bitfield_default }, + { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU0_TD_TCP_CTRL_REG[] = { + { "TD", 0, 6, &umr_bitfield_default }, + { "TD_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "TCPF", 16, 22, &umr_bitfield_default }, + { "TCPF_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "TCPF_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "TCPF_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "TCPF_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU1_SP0_CTRL_REG[] = { + { "SP00", 0, 6, &umr_bitfield_default }, + { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "SP01", 16, 22, &umr_bitfield_default }, + { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU1_LDS_SQ_CTRL_REG[] = { + { "LDS", 0, 6, &umr_bitfield_default }, + { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "SQ", 16, 22, &umr_bitfield_default }, + { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU1_TA_SQC_CTRL_REG[] = { + { "TA", 0, 6, &umr_bitfield_default }, + { "TA_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU1_SP1_CTRL_REG[] = { + { "SP10", 0, 6, &umr_bitfield_default }, + { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "SP11", 16, 22, &umr_bitfield_default }, + { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU1_TD_TCP_CTRL_REG[] = { + { "TD", 0, 6, &umr_bitfield_default }, + { "TD_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "TCPF", 16, 22, &umr_bitfield_default }, + { "TCPF_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "TCPF_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "TCPF_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "TCPF_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU2_SP0_CTRL_REG[] = { + { "SP00", 0, 6, &umr_bitfield_default }, + { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "SP01", 16, 22, &umr_bitfield_default }, + { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU2_LDS_SQ_CTRL_REG[] = { + { "LDS", 0, 6, &umr_bitfield_default }, + { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "SQ", 16, 22, &umr_bitfield_default }, + { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU2_TA_SQC_CTRL_REG[] = { + { "TA", 0, 6, &umr_bitfield_default }, + { "TA_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU2_SP1_CTRL_REG[] = { + { "SP10", 0, 6, &umr_bitfield_default }, + { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "SP11", 16, 22, &umr_bitfield_default }, + { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU2_TD_TCP_CTRL_REG[] = { + { "TD", 0, 6, &umr_bitfield_default }, + { "TD_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "TCPF", 16, 22, &umr_bitfield_default }, + { "TCPF_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "TCPF_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "TCPF_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "TCPF_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU3_SP0_CTRL_REG[] = { + { "SP00", 0, 6, &umr_bitfield_default }, + { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "SP01", 16, 22, &umr_bitfield_default }, + { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU3_LDS_SQ_CTRL_REG[] = { + { "LDS", 0, 6, &umr_bitfield_default }, + { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "SQ", 16, 22, &umr_bitfield_default }, + { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU3_TA_SQC_CTRL_REG[] = { + { "TA", 0, 6, &umr_bitfield_default }, + { "TA_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "SQC", 16, 22, &umr_bitfield_default }, + { "SQC_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "SQC_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "SQC_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "SQC_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU3_SP1_CTRL_REG[] = { + { "SP10", 0, 6, &umr_bitfield_default }, + { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "SP11", 16, 22, &umr_bitfield_default }, + { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU3_TD_TCP_CTRL_REG[] = { + { "TD", 0, 6, &umr_bitfield_default }, + { "TD_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "TCPF", 16, 22, &umr_bitfield_default }, + { "TCPF_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "TCPF_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "TCPF_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "TCPF_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU4_SP0_CTRL_REG[] = { + { "SP00", 0, 6, &umr_bitfield_default }, + { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "SP01", 16, 22, &umr_bitfield_default }, + { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU4_LDS_SQ_CTRL_REG[] = { + { "LDS", 0, 6, &umr_bitfield_default }, + { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "SQ", 16, 22, &umr_bitfield_default }, + { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU4_TA_SQC_CTRL_REG[] = { + { "TA", 0, 6, &umr_bitfield_default }, + { "TA_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU4_SP1_CTRL_REG[] = { + { "SP10", 0, 6, &umr_bitfield_default }, + { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "SP11", 16, 22, &umr_bitfield_default }, + { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU4_TD_TCP_CTRL_REG[] = { + { "TD", 0, 6, &umr_bitfield_default }, + { "TD_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "TCPF", 16, 22, &umr_bitfield_default }, + { "TCPF_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "TCPF_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "TCPF_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "TCPF_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU5_SP0_CTRL_REG[] = { + { "SP00", 0, 6, &umr_bitfield_default }, + { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "SP01", 16, 22, &umr_bitfield_default }, + { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU5_LDS_SQ_CTRL_REG[] = { + { "LDS", 0, 6, &umr_bitfield_default }, + { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "SQ", 16, 22, &umr_bitfield_default }, + { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU5_TA_SQC_CTRL_REG[] = { + { "TA", 0, 6, &umr_bitfield_default }, + { "TA_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU5_SP1_CTRL_REG[] = { + { "SP10", 0, 6, &umr_bitfield_default }, + { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "SP11", 16, 22, &umr_bitfield_default }, + { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU5_TD_TCP_CTRL_REG[] = { + { "TD", 0, 6, &umr_bitfield_default }, + { "TD_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "TCPF", 16, 22, &umr_bitfield_default }, + { "TCPF_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "TCPF_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "TCPF_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "TCPF_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU6_SP0_CTRL_REG[] = { + { "SP00", 0, 6, &umr_bitfield_default }, + { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "SP01", 16, 22, &umr_bitfield_default }, + { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU6_LDS_SQ_CTRL_REG[] = { + { "LDS", 0, 6, &umr_bitfield_default }, + { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "SQ", 16, 22, &umr_bitfield_default }, + { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU6_TA_SQC_CTRL_REG[] = { + { "TA", 0, 6, &umr_bitfield_default }, + { "TA_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "SQC", 16, 22, &umr_bitfield_default }, + { "SQC_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "SQC_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "SQC_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "SQC_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU6_SP1_CTRL_REG[] = { + { "SP10", 0, 6, &umr_bitfield_default }, + { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "SP11", 16, 22, &umr_bitfield_default }, + { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU6_TD_TCP_CTRL_REG[] = { + { "TD", 0, 6, &umr_bitfield_default }, + { "TD_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "TCPF", 16, 22, &umr_bitfield_default }, + { "TCPF_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "TCPF_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "TCPF_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "TCPF_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU7_SP0_CTRL_REG[] = { + { "SP00", 0, 6, &umr_bitfield_default }, + { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "SP01", 16, 22, &umr_bitfield_default }, + { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU7_LDS_SQ_CTRL_REG[] = { + { "LDS", 0, 6, &umr_bitfield_default }, + { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "SQ", 16, 22, &umr_bitfield_default }, + { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU7_TA_SQC_CTRL_REG[] = { + { "TA", 0, 6, &umr_bitfield_default }, + { "TA_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU7_SP1_CTRL_REG[] = { + { "SP10", 0, 6, &umr_bitfield_default }, + { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "SP11", 16, 22, &umr_bitfield_default }, + { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU7_TD_TCP_CTRL_REG[] = { + { "TD", 0, 6, &umr_bitfield_default }, + { "TD_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "TCPF", 16, 22, &umr_bitfield_default }, + { "TCPF_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "TCPF_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "TCPF_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "TCPF_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU8_SP0_CTRL_REG[] = { + { "SP00", 0, 6, &umr_bitfield_default }, + { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "SP01", 16, 22, &umr_bitfield_default }, + { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU8_LDS_SQ_CTRL_REG[] = { + { "LDS", 0, 6, &umr_bitfield_default }, + { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "SQ", 16, 22, &umr_bitfield_default }, + { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU8_TA_SQC_CTRL_REG[] = { + { "TA", 0, 6, &umr_bitfield_default }, + { "TA_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU8_SP1_CTRL_REG[] = { + { "SP10", 0, 6, &umr_bitfield_default }, + { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "SP11", 16, 22, &umr_bitfield_default }, + { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU8_TD_TCP_CTRL_REG[] = { + { "TD", 0, 6, &umr_bitfield_default }, + { "TD_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "TCPF", 16, 22, &umr_bitfield_default }, + { "TCPF_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "TCPF_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "TCPF_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "TCPF_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU9_SP0_CTRL_REG[] = { + { "SP00", 0, 6, &umr_bitfield_default }, + { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "SP01", 16, 22, &umr_bitfield_default }, + { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU9_LDS_SQ_CTRL_REG[] = { + { "LDS", 0, 6, &umr_bitfield_default }, + { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "SQ", 16, 22, &umr_bitfield_default }, + { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU9_TA_SQC_CTRL_REG[] = { + { "TA", 0, 6, &umr_bitfield_default }, + { "TA_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "SQC", 16, 22, &umr_bitfield_default }, + { "SQC_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "SQC_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "SQC_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "SQC_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU9_SP1_CTRL_REG[] = { + { "SP10", 0, 6, &umr_bitfield_default }, + { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "SP11", 16, 22, &umr_bitfield_default }, + { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU9_TD_TCP_CTRL_REG[] = { + { "TD", 0, 6, &umr_bitfield_default }, + { "TD_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "TCPF", 16, 22, &umr_bitfield_default }, + { "TCPF_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "TCPF_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "TCPF_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "TCPF_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU10_SP0_CTRL_REG[] = { + { "SP00", 0, 6, &umr_bitfield_default }, + { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "SP01", 16, 22, &umr_bitfield_default }, + { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU10_LDS_SQ_CTRL_REG[] = { + { "LDS", 0, 6, &umr_bitfield_default }, + { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "SQ", 16, 22, &umr_bitfield_default }, + { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU10_TA_SQC_CTRL_REG[] = { + { "TA", 0, 6, &umr_bitfield_default }, + { "TA_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU10_SP1_CTRL_REG[] = { + { "SP10", 0, 6, &umr_bitfield_default }, + { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "SP11", 16, 22, &umr_bitfield_default }, + { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU10_TD_TCP_CTRL_REG[] = { + { "TD", 0, 6, &umr_bitfield_default }, + { "TD_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "TCPF", 16, 22, &umr_bitfield_default }, + { "TCPF_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "TCPF_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "TCPF_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "TCPF_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU11_SP0_CTRL_REG[] = { + { "SP00", 0, 6, &umr_bitfield_default }, + { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "SP01", 16, 22, &umr_bitfield_default }, + { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU11_LDS_SQ_CTRL_REG[] = { + { "LDS", 0, 6, &umr_bitfield_default }, + { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "SQ", 16, 22, &umr_bitfield_default }, + { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU11_TA_SQC_CTRL_REG[] = { + { "TA", 0, 6, &umr_bitfield_default }, + { "TA_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU11_SP1_CTRL_REG[] = { + { "SP10", 0, 6, &umr_bitfield_default }, + { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "SP11", 16, 22, &umr_bitfield_default }, + { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU11_TD_TCP_CTRL_REG[] = { + { "TD", 0, 6, &umr_bitfield_default }, + { "TD_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "TCPF", 16, 22, &umr_bitfield_default }, + { "TCPF_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "TCPF_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "TCPF_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "TCPF_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU12_SP0_CTRL_REG[] = { + { "SP00", 0, 6, &umr_bitfield_default }, + { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "SP01", 16, 22, &umr_bitfield_default }, + { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU12_LDS_SQ_CTRL_REG[] = { + { "LDS", 0, 6, &umr_bitfield_default }, + { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "SQ", 16, 22, &umr_bitfield_default }, + { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU12_TA_SQC_CTRL_REG[] = { + { "TA", 0, 6, &umr_bitfield_default }, + { "TA_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "SQC", 16, 22, &umr_bitfield_default }, + { "SQC_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "SQC_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "SQC_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "SQC_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU12_SP1_CTRL_REG[] = { + { "SP10", 0, 6, &umr_bitfield_default }, + { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "SP11", 16, 22, &umr_bitfield_default }, + { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU12_TD_TCP_CTRL_REG[] = { + { "TD", 0, 6, &umr_bitfield_default }, + { "TD_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "TCPF", 16, 22, &umr_bitfield_default }, + { "TCPF_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "TCPF_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "TCPF_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "TCPF_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU13_SP0_CTRL_REG[] = { + { "SP00", 0, 6, &umr_bitfield_default }, + { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "SP01", 16, 22, &umr_bitfield_default }, + { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU13_LDS_SQ_CTRL_REG[] = { + { "LDS", 0, 6, &umr_bitfield_default }, + { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "SQ", 16, 22, &umr_bitfield_default }, + { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU13_TA_SQC_CTRL_REG[] = { + { "TA", 0, 6, &umr_bitfield_default }, + { "TA_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU13_SP1_CTRL_REG[] = { + { "SP10", 0, 6, &umr_bitfield_default }, + { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "SP11", 16, 22, &umr_bitfield_default }, + { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU13_TD_TCP_CTRL_REG[] = { + { "TD", 0, 6, &umr_bitfield_default }, + { "TD_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "TCPF", 16, 22, &umr_bitfield_default }, + { "TCPF_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "TCPF_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "TCPF_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "TCPF_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU14_SP0_CTRL_REG[] = { + { "SP00", 0, 6, &umr_bitfield_default }, + { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "SP01", 16, 22, &umr_bitfield_default }, + { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU14_LDS_SQ_CTRL_REG[] = { + { "LDS", 0, 6, &umr_bitfield_default }, + { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "SQ", 16, 22, &umr_bitfield_default }, + { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU14_TA_SQC_CTRL_REG[] = { + { "TA", 0, 6, &umr_bitfield_default }, + { "TA_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU14_SP1_CTRL_REG[] = { + { "SP10", 0, 6, &umr_bitfield_default }, + { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "SP11", 16, 22, &umr_bitfield_default }, + { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU14_TD_TCP_CTRL_REG[] = { + { "TD", 0, 6, &umr_bitfield_default }, + { "TD_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "TCPF", 16, 22, &umr_bitfield_default }, + { "TCPF_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "TCPF_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "TCPF_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "TCPF_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU15_SP0_CTRL_REG[] = { + { "SP00", 0, 6, &umr_bitfield_default }, + { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "SP01", 16, 22, &umr_bitfield_default }, + { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU15_LDS_SQ_CTRL_REG[] = { + { "LDS", 0, 6, &umr_bitfield_default }, + { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "SQ", 16, 22, &umr_bitfield_default }, + { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU15_TA_SQC_CTRL_REG[] = { + { "TA", 0, 6, &umr_bitfield_default }, + { "TA_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "SQC", 16, 22, &umr_bitfield_default }, + { "SQC_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "SQC_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "SQC_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "SQC_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU15_SP1_CTRL_REG[] = { + { "SP10", 0, 6, &umr_bitfield_default }, + { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "SP11", 16, 22, &umr_bitfield_default }, + { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU15_TD_TCP_CTRL_REG[] = { + { "TD", 0, 6, &umr_bitfield_default }, + { "TD_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "TCPF", 16, 22, &umr_bitfield_default }, + { "TCPF_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "TCPF_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default }, + { "TCPF_LS_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "TCPF_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU0_TCPI_CTRL_REG[] = { + { "TCPI", 0, 6, &umr_bitfield_default }, + { "TCPI_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "TCPI_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "TCPI_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "TCPI_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "RESERVED", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU1_TCPI_CTRL_REG[] = { + { "TCPI", 0, 6, &umr_bitfield_default }, + { "TCPI_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "TCPI_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "TCPI_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "TCPI_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "RESERVED", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU2_TCPI_CTRL_REG[] = { + { "TCPI", 0, 6, &umr_bitfield_default }, + { "TCPI_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "TCPI_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "TCPI_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "TCPI_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "RESERVED", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU3_TCPI_CTRL_REG[] = { + { "TCPI", 0, 6, &umr_bitfield_default }, + { "TCPI_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "TCPI_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "TCPI_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "TCPI_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "RESERVED", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU4_TCPI_CTRL_REG[] = { + { "TCPI", 0, 6, &umr_bitfield_default }, + { "TCPI_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "TCPI_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "TCPI_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "TCPI_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "RESERVED", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU5_TCPI_CTRL_REG[] = { + { "TCPI", 0, 6, &umr_bitfield_default }, + { "TCPI_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "TCPI_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "TCPI_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "TCPI_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "RESERVED", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU6_TCPI_CTRL_REG[] = { + { "TCPI", 0, 6, &umr_bitfield_default }, + { "TCPI_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "TCPI_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "TCPI_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "TCPI_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "RESERVED", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU7_TCPI_CTRL_REG[] = { + { "TCPI", 0, 6, &umr_bitfield_default }, + { "TCPI_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "TCPI_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "TCPI_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "TCPI_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "RESERVED", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU8_TCPI_CTRL_REG[] = { + { "TCPI", 0, 6, &umr_bitfield_default }, + { "TCPI_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "TCPI_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "TCPI_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "TCPI_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "RESERVED", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU9_TCPI_CTRL_REG[] = { + { "TCPI", 0, 6, &umr_bitfield_default }, + { "TCPI_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "TCPI_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "TCPI_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "TCPI_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "RESERVED", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU10_TCPI_CTRL_REG[] = { + { "TCPI", 0, 6, &umr_bitfield_default }, + { "TCPI_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "TCPI_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "TCPI_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "TCPI_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "RESERVED", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU11_TCPI_CTRL_REG[] = { + { "TCPI", 0, 6, &umr_bitfield_default }, + { "TCPI_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "TCPI_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "TCPI_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "TCPI_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "RESERVED", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU12_TCPI_CTRL_REG[] = { + { "TCPI", 0, 6, &umr_bitfield_default }, + { "TCPI_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "TCPI_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "TCPI_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "TCPI_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "RESERVED", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU13_TCPI_CTRL_REG[] = { + { "TCPI", 0, 6, &umr_bitfield_default }, + { "TCPI_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "TCPI_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "TCPI_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "TCPI_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "RESERVED", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU14_TCPI_CTRL_REG[] = { + { "TCPI", 0, 6, &umr_bitfield_default }, + { "TCPI_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "TCPI_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "TCPI_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "TCPI_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "RESERVED", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTS_CU15_TCPI_CTRL_REG[] = { + { "TCPI", 0, 6, &umr_bitfield_default }, + { "TCPI_OVERRIDE", 7, 7, &umr_bitfield_default }, + { "TCPI_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default }, + { "TCPI_LS_OVERRIDE", 10, 10, &umr_bitfield_default }, + { "TCPI_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default }, + { "RESERVED", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTT_SPI_CLK_CTRL[] = { + { "ON_DELAY", 0, 3, &umr_bitfield_default }, + { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default }, + { "GRP5_CG_OFF_HYST", 18, 23, &umr_bitfield_default }, + { "GRP5_CG_OVERRIDE", 24, 24, &umr_bitfield_default }, + { "ALL_CLK_ON_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "GRP3_OVERRIDE", 27, 27, &umr_bitfield_default }, + { "GRP2_OVERRIDE", 28, 28, &umr_bitfield_default }, + { "GRP1_OVERRIDE", 29, 29, &umr_bitfield_default }, + { "GRP0_OVERRIDE", 30, 30, &umr_bitfield_default }, + { "REG_OVERRIDE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTT_PC_CLK_CTRL[] = { + { "ON_DELAY", 0, 3, &umr_bitfield_default }, + { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default }, + { "GRP5_CG_OFF_HYST", 18, 23, &umr_bitfield_default }, + { "GRP5_CG_OVERRIDE", 24, 24, &umr_bitfield_default }, + { "PC_WRITE_CLK_EN_OVERRIDE", 25, 25, &umr_bitfield_default }, + { "PC_READ_CLK_EN_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "CORE3_OVERRIDE", 27, 27, &umr_bitfield_default }, + { "CORE2_OVERRIDE", 28, 28, &umr_bitfield_default }, + { "CORE1_OVERRIDE", 29, 29, &umr_bitfield_default }, + { "CORE0_OVERRIDE", 30, 30, &umr_bitfield_default }, + { "REG_OVERRIDE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTT_BCI_CLK_CTRL[] = { + { "ON_DELAY", 0, 3, &umr_bitfield_default }, + { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default }, + { "RESERVED", 12, 15, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE7", 16, 16, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE6", 17, 17, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE5", 18, 18, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE4", 19, 19, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE3", 20, 20, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE2", 21, 21, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE1", 22, 22, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE0", 23, 23, &umr_bitfield_default }, + { "CORE6_OVERRIDE", 24, 24, &umr_bitfield_default }, + { "CORE5_OVERRIDE", 25, 25, &umr_bitfield_default }, + { "CORE4_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "CORE3_OVERRIDE", 27, 27, &umr_bitfield_default }, + { "CORE2_OVERRIDE", 28, 28, &umr_bitfield_default }, + { "CORE1_OVERRIDE", 29, 29, &umr_bitfield_default }, + { "CORE0_OVERRIDE", 30, 30, &umr_bitfield_default }, + { "REG_OVERRIDE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTT_VGT_CLK_CTRL[] = { + { "ON_DELAY", 0, 3, &umr_bitfield_default }, + { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default }, + { "PERF_ENABLE", 15, 15, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE6", 17, 17, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE5", 18, 18, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE4", 19, 19, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE3", 20, 20, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE2", 21, 21, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE1", 22, 22, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE0", 23, 23, &umr_bitfield_default }, + { "SOFT_OVERRIDE9", 24, 24, &umr_bitfield_default }, + { "SOFT_OVERRIDE8", 25, 25, &umr_bitfield_default }, + { "SOFT_OVERRIDE7", 26, 26, &umr_bitfield_default }, + { "PRIMGEN_OVERRIDE", 27, 27, &umr_bitfield_default }, + { "TESS_OVERRIDE", 28, 28, &umr_bitfield_default }, + { "GS_OVERRIDE", 29, 29, &umr_bitfield_default }, + { "CORE_OVERRIDE", 30, 30, &umr_bitfield_default }, + { "REG_OVERRIDE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTT_IA_CLK_CTRL[] = { + { "ON_DELAY", 0, 3, &umr_bitfield_default }, + { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE7", 16, 16, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE6", 17, 17, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE5", 18, 18, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE4", 19, 19, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE3", 20, 20, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE2", 21, 21, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE1", 22, 22, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE0", 23, 23, &umr_bitfield_default }, + { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default }, + { "PERF_ENABLE", 25, 25, &umr_bitfield_default }, + { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default }, + { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default }, + { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default }, + { "CORE_OVERRIDE", 30, 30, &umr_bitfield_default }, + { "REG_OVERRIDE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTT_WD_CLK_CTRL[] = { + { "ON_DELAY", 0, 3, &umr_bitfield_default }, + { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default }, + { "PERF_ENABLE", 15, 15, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE6", 17, 17, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE5", 18, 18, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE4", 19, 19, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE3", 20, 20, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE2", 21, 21, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE1", 22, 22, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE0", 23, 23, &umr_bitfield_default }, + { "SOFT_OVERRIDE8", 25, 25, &umr_bitfield_default }, + { "SOFT_OVERRIDE7", 26, 26, &umr_bitfield_default }, + { "PRIMGEN_OVERRIDE", 27, 27, &umr_bitfield_default }, + { "TESS_OVERRIDE", 28, 28, &umr_bitfield_default }, + { "CORE_OVERRIDE", 29, 29, &umr_bitfield_default }, + { "RBIU_INPUT_OVERRIDE", 30, 30, &umr_bitfield_default }, + { "REG_OVERRIDE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTT_PA_CLK_CTRL[] = { + { "ON_DELAY", 0, 3, &umr_bitfield_default }, + { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE7", 16, 16, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE6", 17, 17, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE5", 18, 18, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE4", 19, 19, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE3", 20, 20, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE2", 21, 21, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE1", 22, 22, &umr_bitfield_default }, + { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default }, + { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default }, + { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default }, + { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default }, + { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default }, + { "SU_CLK_OVERRIDE", 29, 29, &umr_bitfield_default }, + { "CL_CLK_OVERRIDE", 30, 30, &umr_bitfield_default }, + { "REG_CLK_OVERRIDE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTT_SC_CLK_CTRL0[] = { + { "ON_DELAY", 0, 3, &umr_bitfield_default }, + { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default }, + { "PFF_ZFF_MEM_CLK_STALL_OVERRIDE", 16, 16, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE5", 17, 17, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE4", 18, 18, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE3", 19, 19, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE2", 20, 20, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE1", 21, 21, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE0", 22, 22, &umr_bitfield_default }, + { "REG_CLK_STALL_OVERRIDE", 23, 23, &umr_bitfield_default }, + { "PFF_ZFF_MEM_CLK_OVERRIDE", 24, 24, &umr_bitfield_default }, + { "SOFT_OVERRIDE5", 25, 25, &umr_bitfield_default }, + { "SOFT_OVERRIDE4", 26, 26, &umr_bitfield_default }, + { "SOFT_OVERRIDE3", 27, 27, &umr_bitfield_default }, + { "SOFT_OVERRIDE2", 28, 28, &umr_bitfield_default }, + { "SOFT_OVERRIDE1", 29, 29, &umr_bitfield_default }, + { "SOFT_OVERRIDE0", 30, 30, &umr_bitfield_default }, + { "REG_CLK_OVERRIDE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTT_SC_CLK_CTRL1[] = { + { "ON_DELAY", 0, 3, &umr_bitfield_default }, + { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default }, + { "PBB_BINNING_CLK_STALL_OVERRIDE", 17, 17, &umr_bitfield_default }, + { "PBB_SCISSOR_CLK_STALL_OVERRIDE", 18, 18, &umr_bitfield_default }, + { "OTHER_SPECIAL_SC_REG_CLK_STALL_OVERRIDE", 19, 19, &umr_bitfield_default }, + { "SCREEN_EXT_REG_CLK_STALL_OVERRIDE", 20, 20, &umr_bitfield_default }, + { "VPORT_REG_MEM_CLK_STALL_OVERRIDE", 21, 21, &umr_bitfield_default }, + { "PBB_CLK_STALL_OVERRIDE", 22, 22, &umr_bitfield_default }, + { "PBB_BINNING_CLK_OVERRIDE", 25, 25, &umr_bitfield_default }, + { "PBB_SCISSOR_CLK_OVERRIDE", 26, 26, &umr_bitfield_default }, + { "OTHER_SPECIAL_SC_REG_CLK_OVERRIDE", 27, 27, &umr_bitfield_default }, + { "SCREEN_EXT_REG_CLK_OVERRIDE", 28, 28, &umr_bitfield_default }, + { "VPORT_REG_MEM_CLK_OVERRIDE", 29, 29, &umr_bitfield_default }, + { "PBB_CLK_OVERRIDE", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTT_SQ_CLK_CTRL[] = { + { "ON_DELAY", 0, 3, &umr_bitfield_default }, + { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE7", 16, 16, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE6", 17, 17, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE5", 18, 18, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE4", 19, 19, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE3", 20, 20, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE2", 21, 21, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE1", 22, 22, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE0", 23, 23, &umr_bitfield_default }, + { "PERFMON_OVERRIDE", 29, 29, &umr_bitfield_default }, + { "CORE_OVERRIDE", 30, 30, &umr_bitfield_default }, + { "REG_OVERRIDE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTT_SQG_CLK_CTRL[] = { + { "ON_DELAY", 0, 3, &umr_bitfield_default }, + { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE7", 16, 16, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE6", 17, 17, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE5", 18, 18, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE4", 19, 19, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE3", 20, 20, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE2", 21, 21, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE1", 22, 22, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE0", 23, 23, &umr_bitfield_default }, + { "TTRACE_OVERRIDE", 28, 28, &umr_bitfield_default }, + { "PERFMON_OVERRIDE", 29, 29, &umr_bitfield_default }, + { "CORE_OVERRIDE", 30, 30, &umr_bitfield_default }, + { "REG_OVERRIDE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_ALU_CLK_CTRL[] = { + { "FORCE_CU_ON_SH0", 0, 15, &umr_bitfield_default }, + { "FORCE_CU_ON_SH1", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_TEX_CLK_CTRL[] = { + { "FORCE_CU_ON_SH0", 0, 15, &umr_bitfield_default }, + { "FORCE_CU_ON_SH1", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_LDS_CLK_CTRL[] = { + { "FORCE_CU_ON_SH0", 0, 15, &umr_bitfield_default }, + { "FORCE_CU_ON_SH1", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_POWER_THROTTLE[] = { + { "MIN_POWER", 0, 13, &umr_bitfield_default }, + { "MAX_POWER", 16, 29, &umr_bitfield_default }, + { "PHASE_OFFSET", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSQ_POWER_THROTTLE2[] = { + { "MAX_POWER_DELTA", 0, 13, &umr_bitfield_default }, + { "SHORT_TERM_INTERVAL_SIZE", 16, 25, &umr_bitfield_default }, + { "LONG_TERM_INTERVAL_RATIO", 27, 30, &umr_bitfield_default }, + { "USE_REF_CLOCK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTT_SX_CLK_CTRL0[] = { + { "ON_DELAY", 0, 3, &umr_bitfield_default }, + { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default }, + { "RESERVED", 12, 15, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE7", 16, 16, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE6", 17, 17, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE5", 18, 18, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE4", 19, 19, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE3", 20, 20, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE2", 21, 21, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE1", 22, 22, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE0", 23, 23, &umr_bitfield_default }, + { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default }, + { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default }, + { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default }, + { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default }, + { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default }, + { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default }, + { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default }, + { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTT_SX_CLK_CTRL1[] = { + { "ON_DELAY", 0, 3, &umr_bitfield_default }, + { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default }, + { "RESERVED", 12, 15, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE7", 16, 16, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE6", 17, 17, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE5", 18, 18, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE4", 19, 19, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE3", 20, 20, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE2", 21, 21, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE1", 22, 22, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE0", 23, 23, &umr_bitfield_default }, + { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default }, + { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default }, + { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default }, + { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default }, + { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default }, + { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default }, + { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTT_SX_CLK_CTRL2[] = { + { "ON_DELAY", 0, 3, &umr_bitfield_default }, + { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default }, + { "RESERVED", 13, 15, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE7", 16, 16, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE6", 17, 17, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE5", 18, 18, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE4", 19, 19, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE3", 20, 20, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE2", 21, 21, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE1", 22, 22, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE0", 23, 23, &umr_bitfield_default }, + { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default }, + { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default }, + { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default }, + { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default }, + { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default }, + { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default }, + { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTT_SX_CLK_CTRL3[] = { + { "ON_DELAY", 0, 3, &umr_bitfield_default }, + { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default }, + { "RESERVED", 13, 15, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE7", 16, 16, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE6", 17, 17, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE5", 18, 18, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE4", 19, 19, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE3", 20, 20, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE2", 21, 21, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE1", 22, 22, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE0", 23, 23, &umr_bitfield_default }, + { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default }, + { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default }, + { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default }, + { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default }, + { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default }, + { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default }, + { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTT_SX_CLK_CTRL4[] = { + { "ON_DELAY", 0, 3, &umr_bitfield_default }, + { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default }, + { "RESERVED", 12, 15, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE7", 16, 16, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE6", 17, 17, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE5", 18, 18, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE4", 19, 19, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE3", 20, 20, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE2", 21, 21, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE1", 22, 22, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE0", 23, 23, &umr_bitfield_default }, + { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default }, + { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default }, + { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default }, + { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default }, + { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default }, + { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default }, + { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTD_CGTT_CTRL[] = { + { "ON_DELAY", 0, 3, &umr_bitfield_default }, + { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE7", 16, 16, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE6", 17, 17, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE5", 18, 18, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE4", 19, 19, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE3", 20, 20, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE2", 21, 21, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE1", 22, 22, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE0", 23, 23, &umr_bitfield_default }, + { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default }, + { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default }, + { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default }, + { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default }, + { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default }, + { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default }, + { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default }, + { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTA_CGTT_CTRL[] = { + { "ON_DELAY", 0, 3, &umr_bitfield_default }, + { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE7", 16, 16, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE6", 17, 17, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE5", 18, 18, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE4", 19, 19, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE3", 20, 20, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE2", 21, 21, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE1", 22, 22, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE0", 23, 23, &umr_bitfield_default }, + { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default }, + { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default }, + { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default }, + { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default }, + { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default }, + { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default }, + { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default }, + { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTT_TCPI_CLK_CTRL[] = { + { "ON_DELAY", 0, 3, &umr_bitfield_default }, + { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default }, + { "SPARE", 12, 15, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE7", 16, 16, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE6", 17, 17, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE5", 18, 18, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE4", 19, 19, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE3", 20, 20, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE2", 21, 21, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE1", 22, 22, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE0", 23, 23, &umr_bitfield_default }, + { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default }, + { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default }, + { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default }, + { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default }, + { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default }, + { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default }, + { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default }, + { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTT_TCI_CLK_CTRL[] = { + { "ON_DELAY", 0, 3, &umr_bitfield_default }, + { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE7", 16, 16, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE6", 17, 17, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE5", 18, 18, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE4", 19, 19, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE3", 20, 20, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE2", 21, 21, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE1", 22, 22, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE0", 23, 23, &umr_bitfield_default }, + { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default }, + { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default }, + { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default }, + { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default }, + { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default }, + { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default }, + { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default }, + { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTT_GDS_CLK_CTRL[] = { + { "ON_DELAY", 0, 3, &umr_bitfield_default }, + { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE7", 16, 16, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE6", 17, 17, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE5", 18, 18, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE4", 19, 19, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE3", 20, 20, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE2", 21, 21, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE1", 22, 22, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE0", 23, 23, &umr_bitfield_default }, + { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default }, + { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default }, + { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default }, + { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default }, + { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default }, + { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default }, + { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default }, + { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDB_CGTT_CLK_CTRL_0[] = { + { "ON_DELAY", 0, 3, &umr_bitfield_default }, + { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default }, + { "RESERVED", 12, 15, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE7", 16, 16, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE6", 17, 17, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE5", 18, 18, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE4", 19, 19, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE3", 20, 20, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE2", 21, 21, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE1", 22, 22, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE0", 23, 23, &umr_bitfield_default }, + { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default }, + { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default }, + { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default }, + { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default }, + { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default }, + { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default }, + { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default }, + { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCB_CGTT_SCLK_CTRL[] = { + { "ON_DELAY", 0, 3, &umr_bitfield_default }, + { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE7", 16, 16, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE6", 17, 17, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE5", 18, 18, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE4", 19, 19, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE3", 20, 20, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE2", 21, 21, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE1", 22, 22, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE0", 23, 23, &umr_bitfield_default }, + { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default }, + { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default }, + { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default }, + { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default }, + { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default }, + { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default }, + { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default }, + { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCC_CGTT_SCLK_CTRL[] = { + { "ON_DELAY", 0, 3, &umr_bitfield_default }, + { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE7", 16, 16, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE6", 17, 17, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE5", 18, 18, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE4", 19, 19, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE3", 20, 20, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE2", 21, 21, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE1", 22, 22, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE0", 23, 23, &umr_bitfield_default }, + { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default }, + { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default }, + { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default }, + { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default }, + { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default }, + { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default }, + { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default }, + { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmTCA_CGTT_SCLK_CTRL[] = { + { "ON_DELAY", 0, 3, &umr_bitfield_default }, + { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE7", 16, 16, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE6", 17, 17, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE5", 18, 18, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE4", 19, 19, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE3", 20, 20, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE2", 21, 21, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE1", 22, 22, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE0", 23, 23, &umr_bitfield_default }, + { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default }, + { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default }, + { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default }, + { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default }, + { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default }, + { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default }, + { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default }, + { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTT_CP_CLK_CTRL[] = { + { "ON_DELAY", 0, 3, &umr_bitfield_default }, + { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default }, + { "MGLS_OVERRIDE", 15, 15, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE7", 16, 16, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE6", 17, 17, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE5", 18, 18, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE4", 19, 19, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE3", 20, 20, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE2", 21, 21, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE1", 22, 22, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE0", 23, 23, &umr_bitfield_default }, + { "SOFT_OVERRIDE_PERFMON", 29, 29, &umr_bitfield_default }, + { "SOFT_OVERRIDE_DYN", 30, 30, &umr_bitfield_default }, + { "SOFT_OVERRIDE_REG", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTT_CPF_CLK_CTRL[] = { + { "ON_DELAY", 0, 3, &umr_bitfield_default }, + { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default }, + { "MGLS_OVERRIDE", 15, 15, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE7", 16, 16, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE6", 17, 17, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE5", 18, 18, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE4", 19, 19, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE3", 20, 20, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE2", 21, 21, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE1", 22, 22, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE0", 23, 23, &umr_bitfield_default }, + { "SOFT_OVERRIDE_PERFMON", 29, 29, &umr_bitfield_default }, + { "SOFT_OVERRIDE_DYN", 30, 30, &umr_bitfield_default }, + { "SOFT_OVERRIDE_REG", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTT_CPC_CLK_CTRL[] = { + { "ON_DELAY", 0, 3, &umr_bitfield_default }, + { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default }, + { "MGLS_OVERRIDE", 15, 15, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE7", 16, 16, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE6", 17, 17, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE5", 18, 18, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE4", 19, 19, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE3", 20, 20, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE2", 21, 21, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE1", 22, 22, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE0", 23, 23, &umr_bitfield_default }, + { "SOFT_OVERRIDE_PERFMON", 29, 29, &umr_bitfield_default }, + { "SOFT_OVERRIDE_DYN", 30, 30, &umr_bitfield_default }, + { "SOFT_OVERRIDE_REG", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_PWR_CTRL[] = { + { "MON_CGPG_RTN_EN", 0, 0, &umr_bitfield_default }, + { "RESERVED", 1, 7, &umr_bitfield_default }, + { "DLDO_STATUS", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTT_RLC_CLK_CTRL[] = { + { "ON_DELAY", 0, 3, &umr_bitfield_default }, + { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE7", 16, 16, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE6", 17, 17, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE5", 18, 18, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE4", 19, 19, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE3", 20, 20, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE2", 21, 21, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE1", 22, 22, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE0", 23, 23, &umr_bitfield_default }, + { "SOFT_OVERRIDE_DYN", 30, 30, &umr_bitfield_default }, + { "SOFT_OVERRIDE_REG", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GFX_RM_CNTL[] = { + { "RLC_GFX_RM_VALID", 0, 0, &umr_bitfield_default }, + { "RESERVED", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRMI_CGTT_SCLK_CTRL[] = { + { "ON_DELAY", 0, 3, &umr_bitfield_default }, + { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE7", 16, 16, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE6", 17, 17, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE5", 18, 18, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE4", 19, 19, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE3", 20, 20, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE2", 21, 21, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE1", 22, 22, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE0", 23, 23, &umr_bitfield_default }, + { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default }, + { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default }, + { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default }, + { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default }, + { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default }, + { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default }, + { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCGTT_TCPF_CLK_CTRL[] = { + { "ON_DELAY", 0, 3, &umr_bitfield_default }, + { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default }, + { "SPARE", 12, 15, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE7", 16, 16, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE6", 17, 17, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE5", 18, 18, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE4", 19, 19, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE3", 20, 20, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE2", 21, 21, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE1", 22, 22, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE0", 23, 23, &umr_bitfield_default }, + { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default }, + { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default }, + { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default }, + { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default }, + { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default }, + { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default }, + { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default }, + { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGCEA_CGTT_CLK_CTRL[] = { + { "ON_DELAY", 0, 3, &umr_bitfield_default }, + { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE", 22, 22, &umr_bitfield_default }, + { "SOFT_OVERRIDE_RETURN", 30, 30, &umr_bitfield_default }, + { "SOFT_OVERRIDE_REGISTER", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF0[] = { + { "VF_FB_SIZE", 0, 15, &umr_bitfield_default }, + { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF1[] = { + { "VF_FB_SIZE", 0, 15, &umr_bitfield_default }, + { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF2[] = { + { "VF_FB_SIZE", 0, 15, &umr_bitfield_default }, + { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF3[] = { + { "VF_FB_SIZE", 0, 15, &umr_bitfield_default }, + { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF4[] = { + { "VF_FB_SIZE", 0, 15, &umr_bitfield_default }, + { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF5[] = { + { "VF_FB_SIZE", 0, 15, &umr_bitfield_default }, + { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF6[] = { + { "VF_FB_SIZE", 0, 15, &umr_bitfield_default }, + { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF7[] = { + { "VF_FB_SIZE", 0, 15, &umr_bitfield_default }, + { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF8[] = { + { "VF_FB_SIZE", 0, 15, &umr_bitfield_default }, + { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF9[] = { + { "VF_FB_SIZE", 0, 15, &umr_bitfield_default }, + { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF10[] = { + { "VF_FB_SIZE", 0, 15, &umr_bitfield_default }, + { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF11[] = { + { "VF_FB_SIZE", 0, 15, &umr_bitfield_default }, + { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF12[] = { + { "VF_FB_SIZE", 0, 15, &umr_bitfield_default }, + { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF13[] = { + { "VF_FB_SIZE", 0, 15, &umr_bitfield_default }, + { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF14[] = { + { "VF_FB_SIZE", 0, 15, &umr_bitfield_default }, + { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF15[] = { + { "VF_FB_SIZE", 0, 15, &umr_bitfield_default }, + { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_IOMMU_MMIO_CNTRL_1[] = { + { "MARC_EN", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_MARC_BASE_LO_0[] = { + { "MARC_BASE_LO_0", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_MARC_BASE_LO_1[] = { + { "MARC_BASE_LO_1", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_MARC_BASE_LO_2[] = { + { "MARC_BASE_LO_2", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_MARC_BASE_LO_3[] = { + { "MARC_BASE_LO_3", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_MARC_BASE_HI_0[] = { + { "MARC_BASE_HI_0", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_MARC_BASE_HI_1[] = { + { "MARC_BASE_HI_1", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_MARC_BASE_HI_2[] = { + { "MARC_BASE_HI_2", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_MARC_BASE_HI_3[] = { + { "MARC_BASE_HI_3", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_MARC_RELOC_LO_0[] = { + { "MARC_ENABLE_0", 0, 0, &umr_bitfield_default }, + { "MARC_READONLY_0", 1, 1, &umr_bitfield_default }, + { "MARC_RELOC_LO_0", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_MARC_RELOC_LO_1[] = { + { "MARC_ENABLE_1", 0, 0, &umr_bitfield_default }, + { "MARC_READONLY_1", 1, 1, &umr_bitfield_default }, + { "MARC_RELOC_LO_1", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_MARC_RELOC_LO_2[] = { + { "MARC_ENABLE_2", 0, 0, &umr_bitfield_default }, + { "MARC_READONLY_2", 1, 1, &umr_bitfield_default }, + { "MARC_RELOC_LO_2", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_MARC_RELOC_LO_3[] = { + { "MARC_ENABLE_3", 0, 0, &umr_bitfield_default }, + { "MARC_READONLY_3", 1, 1, &umr_bitfield_default }, + { "MARC_RELOC_LO_3", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_MARC_RELOC_HI_0[] = { + { "MARC_RELOC_HI_0", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_MARC_RELOC_HI_1[] = { + { "MARC_RELOC_HI_1", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_MARC_RELOC_HI_2[] = { + { "MARC_RELOC_HI_2", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_MARC_RELOC_HI_3[] = { + { "MARC_RELOC_HI_3", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_MARC_LEN_LO_0[] = { + { "MARC_LEN_LO_0", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_MARC_LEN_LO_1[] = { + { "MARC_LEN_LO_1", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_MARC_LEN_LO_2[] = { + { "MARC_LEN_LO_2", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_MARC_LEN_LO_3[] = { + { "MARC_LEN_LO_3", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_MARC_LEN_HI_0[] = { + { "MARC_LEN_HI_0", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_MARC_LEN_HI_1[] = { + { "MARC_LEN_HI_1", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_MARC_LEN_HI_2[] = { + { "MARC_LEN_HI_2", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_MARC_LEN_HI_3[] = { + { "MARC_LEN_HI_3", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_IOMMU_CONTROL_REGISTER[] = { + { "IOMMUEN", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER[] = { + { "PERFOPTEN", 13, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_PCIE_ATS_CNTL[] = { + { "STU", 16, 20, &umr_bitfield_default }, + { "ATC_ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_PCIE_ATS_CNTL_VF_0[] = { + { "ATC_ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_PCIE_ATS_CNTL_VF_1[] = { + { "ATC_ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_PCIE_ATS_CNTL_VF_2[] = { + { "ATC_ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_PCIE_ATS_CNTL_VF_3[] = { + { "ATC_ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_PCIE_ATS_CNTL_VF_4[] = { + { "ATC_ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_PCIE_ATS_CNTL_VF_5[] = { + { "ATC_ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_PCIE_ATS_CNTL_VF_6[] = { + { "ATC_ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_PCIE_ATS_CNTL_VF_7[] = { + { "ATC_ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_PCIE_ATS_CNTL_VF_8[] = { + { "ATC_ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_PCIE_ATS_CNTL_VF_9[] = { + { "ATC_ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_PCIE_ATS_CNTL_VF_10[] = { + { "ATC_ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_PCIE_ATS_CNTL_VF_11[] = { + { "ATC_ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_PCIE_ATS_CNTL_VF_12[] = { + { "ATC_ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_PCIE_ATS_CNTL_VF_13[] = { + { "ATC_ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_PCIE_ATS_CNTL_VF_14[] = { + { "ATC_ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_PCIE_ATS_CNTL_VF_15[] = { + { "ATC_ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUTCL2_CGTT_CLK_CTRL[] = { + { "ON_DELAY", 0, 3, &umr_bitfield_default }, + { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default }, + { "SOFT_OVERRIDE_EXTRA", 12, 14, &umr_bitfield_default }, + { "MGLS_OVERRIDE", 15, 15, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE", 16, 23, &umr_bitfield_default }, + { "SOFT_OVERRIDE", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HYP_PFP_UCODE_ADDR[] = { + { "UCODE_ADDR", 0, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_PFP_UCODE_ADDR[] = { + { "UCODE_ADDR", 0, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HYP_PFP_UCODE_DATA[] = { + { "UCODE_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_PFP_UCODE_DATA[] = { + { "UCODE_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HYP_ME_UCODE_ADDR[] = { + { "UCODE_ADDR", 0, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ME_RAM_RADDR[] = { + { "ME_RAM_RADDR", 0, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ME_RAM_WADDR[] = { + { "ME_RAM_WADDR", 0, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HYP_ME_UCODE_DATA[] = { + { "UCODE_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_ME_RAM_DATA[] = { + { "ME_RAM_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_CE_UCODE_ADDR[] = { + { "UCODE_ADDR", 0, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HYP_CE_UCODE_ADDR[] = { + { "UCODE_ADDR", 0, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_CE_UCODE_DATA[] = { + { "UCODE_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HYP_CE_UCODE_DATA[] = { + { "UCODE_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HYP_MEC1_UCODE_ADDR[] = { + { "UCODE_ADDR", 0, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_MEC_ME1_UCODE_ADDR[] = { + { "UCODE_ADDR", 0, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HYP_MEC1_UCODE_DATA[] = { + { "UCODE_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_MEC_ME1_UCODE_DATA[] = { + { "UCODE_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HYP_MEC2_UCODE_ADDR[] = { + { "UCODE_ADDR", 0, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_MEC_ME2_UCODE_ADDR[] = { + { "UCODE_ADDR", 0, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_HYP_MEC2_UCODE_DATA[] = { + { "UCODE_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCP_MEC_ME2_UCODE_DATA[] = { + { "UCODE_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPM_UCODE_ADDR[] = { + { "UCODE_ADDR", 0, 13, &umr_bitfield_default }, + { "RESERVED", 14, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPM_UCODE_DATA[] = { + { "UCODE_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRBM_GFX_INDEX_SR_SELECT[] = { + { "INDEX", 0, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRBM_GFX_INDEX_SR_DATA[] = { + { "INSTANCE_INDEX", 0, 7, &umr_bitfield_default }, + { "SH_INDEX", 8, 15, &umr_bitfield_default }, + { "SE_INDEX", 16, 23, &umr_bitfield_default }, + { "SH_BROADCAST_WRITES", 29, 29, &umr_bitfield_default }, + { "INSTANCE_BROADCAST_WRITES", 30, 30, &umr_bitfield_default }, + { "SE_BROADCAST_WRITES", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRBM_GFX_CNTL_SR_SELECT[] = { + { "INDEX", 0, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRBM_GFX_CNTL_SR_DATA[] = { + { "PIPEID", 0, 1, &umr_bitfield_default }, + { "MEID", 2, 3, &umr_bitfield_default }, + { "VMID", 4, 7, &umr_bitfield_default }, + { "QUEUEID", 8, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRBM_CAM_INDEX[] = { + { "CAM_INDEX", 0, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRBM_HYP_CAM_INDEX[] = { + { "CAM_INDEX", 0, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRBM_CAM_DATA[] = { + { "CAM_ADDR", 0, 15, &umr_bitfield_default }, + { "CAM_REMAPADDR", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGRBM_HYP_CAM_DATA[] = { + { "CAM_ADDR", 0, 15, &umr_bitfield_default }, + { "CAM_REMAPADDR", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPU_IOV_VF_ENABLE[] = { + { "VF_ENABLE", 0, 0, &umr_bitfield_default }, + { "RESERVED", 1, 15, &umr_bitfield_default }, + { "VF_NUM", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GFX_RM_CNTL_ADJ[] = { + { "RLC_GFX_RM_VALID", 0, 0, &umr_bitfield_default }, + { "RESERVED", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPU_IOV_CFG_REG6[] = { + { "CNTXT_SIZE", 0, 6, &umr_bitfield_default }, + { "CNTXT_LOCATION", 7, 7, &umr_bitfield_default }, + { "RESERVED", 8, 9, &umr_bitfield_default }, + { "CNTXT_OFFSET", 10, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPU_IOV_CFG_REG8[] = { + { "VM_BUSY_STATUS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_RLCV_TIMER_INT_0[] = { + { "TIMER", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_RLCV_TIMER_CTRL[] = { + { "TIMER_0_EN", 0, 0, &umr_bitfield_default }, + { "RESERVED", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_RLCV_TIMER_STAT[] = { + { "TIMER_0_STAT", 0, 0, &umr_bitfield_default }, + { "RESERVED", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPU_IOV_VF_DOORBELL_STATUS[] = { + { "VF_DOORBELL_STATUS", 0, 15, &umr_bitfield_default }, + { "RESERVED", 16, 30, &umr_bitfield_default }, + { "PF_DOORBELL_STATUS", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPU_IOV_VF_DOORBELL_STATUS_SET[] = { + { "VF_DOORBELL_STATUS_SET", 0, 15, &umr_bitfield_default }, + { "RESERVED", 16, 30, &umr_bitfield_default }, + { "PF_DOORBELL_STATUS_SET", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR[] = { + { "VF_DOORBELL_STATUS_CLR", 0, 15, &umr_bitfield_default }, + { "RESERVED", 16, 30, &umr_bitfield_default }, + { "PF_DOORBELL_STATUS_CLR", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPU_IOV_VF_MASK[] = { + { "VF_MASK", 0, 15, &umr_bitfield_default }, + { "RESERVED", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_HYP_SEMAPHORE_2[] = { + { "CLIENT_ID", 0, 4, &umr_bitfield_default }, + { "RESERVED", 5, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_HYP_SEMAPHORE_3[] = { + { "CLIENT_ID", 0, 4, &umr_bitfield_default }, + { "RESERVED", 5, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_CLK_CNTL[] = { + { "RLC_SRM_CLK_CNTL", 0, 0, &umr_bitfield_default }, + { "RLC_SPM_CLK_CNTL", 1, 1, &umr_bitfield_default }, + { "RESERVED", 2, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPU_IOV_SCH_BLOCK[] = { + { "Sch_Block_ID", 0, 3, &umr_bitfield_default }, + { "Sch_Block_Ver", 4, 7, &umr_bitfield_default }, + { "Sch_Block_Size", 8, 14, &umr_bitfield_default }, + { "RESERVED", 16, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPU_IOV_CFG_REG1[] = { + { "CMD_TYPE", 0, 3, &umr_bitfield_default }, + { "CMD_EXECUTE", 4, 4, &umr_bitfield_default }, + { "CMD_EXECUTE_INTR_EN", 5, 5, &umr_bitfield_default }, + { "RESERVED", 6, 7, &umr_bitfield_default }, + { "FCN_ID", 8, 15, &umr_bitfield_default }, + { "NEXT_FCN_ID", 16, 23, &umr_bitfield_default }, + { "RESERVED1", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPU_IOV_CFG_REG2[] = { + { "CMD_STATUS", 0, 3, &umr_bitfield_default }, + { "RESERVED", 4, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPU_IOV_VM_BUSY_STATUS[] = { + { "VM_BUSY_STATUS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPU_IOV_SCH_0[] = { + { "ACTIVE_FUNCTIONS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPU_IOV_ACTIVE_FCN_ID[] = { + { "VF_ID", 0, 3, &umr_bitfield_default }, + { "RESERVED", 4, 30, &umr_bitfield_default }, + { "PF_VF", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPU_IOV_SCH_3[] = { + { "Time_Quanta_Def", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPU_IOV_SCH_1[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPU_IOV_SCH_2[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPU_IOV_UCODE_ADDR[] = { + { "UCODE_ADDR", 0, 11, &umr_bitfield_default }, + { "RESERVED", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPU_IOV_UCODE_DATA[] = { + { "UCODE_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPU_IOV_SCRATCH_ADDR[] = { + { "ADDR", 0, 8, &umr_bitfield_default }, + { "RESERVED", 9, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPU_IOV_SCRATCH_DATA[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPU_IOV_F32_CNTL[] = { + { "ENABLE", 0, 0, &umr_bitfield_default }, + { "RESERVED", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPU_IOV_F32_RESET[] = { + { "RESET", 0, 0, &umr_bitfield_default }, + { "RESERVED", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPU_IOV_SDMA0_STATUS[] = { + { "PREEMPTED", 0, 0, &umr_bitfield_default }, + { "RESERVED", 1, 7, &umr_bitfield_default }, + { "SAVED", 8, 8, &umr_bitfield_default }, + { "RESERVED1", 9, 11, &umr_bitfield_default }, + { "RESTORED", 12, 12, &umr_bitfield_default }, + { "RESERVED2", 13, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPU_IOV_SDMA1_STATUS[] = { + { "PREEMPTED", 0, 0, &umr_bitfield_default }, + { "RESERVED", 1, 7, &umr_bitfield_default }, + { "SAVED", 8, 8, &umr_bitfield_default }, + { "RESERVED1", 9, 11, &umr_bitfield_default }, + { "RESTORED", 12, 12, &umr_bitfield_default }, + { "RESERVED2", 13, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPU_IOV_SMU_RESPONSE[] = { + { "RESP", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPU_IOV_VIRT_RESET_REQ[] = { + { "VF_FLR", 0, 15, &umr_bitfield_default }, + { "RESERVED", 16, 30, &umr_bitfield_default }, + { "SOFT_PF_FLR", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPU_IOV_RLC_RESPONSE[] = { + { "RESP", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPU_IOV_INT_DISABLE[] = { + { "DISABLE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPU_IOV_INT_FORCE[] = { + { "FORCE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPU_IOV_SDMA0_BUSY_STATUS[] = { + { "VM_BUSY_STATUS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRLC_GPU_IOV_SDMA1_BUSY_STATUS[] = { + { "VM_BUSY_STATUS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_CNTL[] = { + { "CAC_ENABLE", 0, 0, &umr_bitfield_default }, + { "CAC_THRESHOLD", 1, 16, &umr_bitfield_default }, + { "CAC_BLOCK_ID", 17, 22, &umr_bitfield_default }, + { "CAC_SIGNAL_ID", 23, 30, &umr_bitfield_default }, + { "UNUSED_0", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_OVR_SEL[] = { + { "CAC_OVR_SEL", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_OVR_VAL[] = { + { "CAC_OVR_VAL", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_WEIGHT_BCI_0[] = { + { "WEIGHT_BCI_SIG0", 0, 15, &umr_bitfield_default }, + { "WEIGHT_BCI_SIG1", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_WEIGHT_CB_0[] = { + { "WEIGHT_CB_SIG0", 0, 15, &umr_bitfield_default }, + { "WEIGHT_CB_SIG1", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_WEIGHT_CB_1[] = { + { "WEIGHT_CB_SIG2", 0, 15, &umr_bitfield_default }, + { "WEIGHT_CB_SIG3", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_WEIGHT_CP_0[] = { + { "WEIGHT_CP_SIG0", 0, 15, &umr_bitfield_default }, + { "WEIGHT_CP_SIG1", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_WEIGHT_CP_1[] = { + { "WEIGHT_CP_SIG2", 0, 15, &umr_bitfield_default }, + { "UNUSED_0", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_WEIGHT_DB_0[] = { + { "WEIGHT_DB_SIG0", 0, 15, &umr_bitfield_default }, + { "WEIGHT_DB_SIG1", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_WEIGHT_DB_1[] = { + { "WEIGHT_DB_SIG2", 0, 15, &umr_bitfield_default }, + { "WEIGHT_DB_SIG3", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_WEIGHT_GDS_0[] = { + { "WEIGHT_GDS_SIG0", 0, 15, &umr_bitfield_default }, + { "WEIGHT_GDS_SIG1", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_WEIGHT_GDS_1[] = { + { "WEIGHT_GDS_SIG2", 0, 15, &umr_bitfield_default }, + { "WEIGHT_GDS_SIG3", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_WEIGHT_IA_0[] = { + { "WEIGHT_IA_SIG0", 0, 15, &umr_bitfield_default }, + { "UNUSED_0", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_WEIGHT_LDS_0[] = { + { "WEIGHT_LDS_SIG0", 0, 15, &umr_bitfield_default }, + { "WEIGHT_LDS_SIG1", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_WEIGHT_LDS_1[] = { + { "WEIGHT_LDS_SIG2", 0, 15, &umr_bitfield_default }, + { "WEIGHT_LDS_SIG3", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_WEIGHT_PA_0[] = { + { "WEIGHT_PA_SIG0", 0, 15, &umr_bitfield_default }, + { "WEIGHT_PA_SIG1", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_WEIGHT_PC_0[] = { + { "WEIGHT_PC_SIG0", 0, 15, &umr_bitfield_default }, + { "UNUSED_0", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_WEIGHT_SC_0[] = { + { "WEIGHT_SC_SIG0", 0, 15, &umr_bitfield_default }, + { "UNUSED_0", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_WEIGHT_SPI_0[] = { + { "WEIGHT_SPI_SIG0", 0, 15, &umr_bitfield_default }, + { "WEIGHT_SPI_SIG1", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_WEIGHT_SPI_1[] = { + { "WEIGHT_SPI_SIG2", 0, 15, &umr_bitfield_default }, + { "WEIGHT_SPI_SIG3", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_WEIGHT_SPI_2[] = { + { "WEIGHT_SPI_SIG4", 0, 15, &umr_bitfield_default }, + { "WEIGHT_SPI_SIG5", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_WEIGHT_SQ_0[] = { + { "WEIGHT_SQ_SIG0", 0, 15, &umr_bitfield_default }, + { "WEIGHT_SQ_SIG1", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_WEIGHT_SQ_1[] = { + { "WEIGHT_SQ_SIG2", 0, 15, &umr_bitfield_default }, + { "WEIGHT_SQ_SIG3", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_WEIGHT_SQ_2[] = { + { "WEIGHT_SQ_SIG4", 0, 15, &umr_bitfield_default }, + { "WEIGHT_SQ_SIG5", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_WEIGHT_SQ_3[] = { + { "WEIGHT_SQ_SIG6", 0, 15, &umr_bitfield_default }, + { "WEIGHT_SQ_SIG7", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_WEIGHT_SQ_4[] = { + { "WEIGHT_SQ_SIG8", 0, 15, &umr_bitfield_default }, + { "UNUSED_0", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_WEIGHT_SX_0[] = { + { "WEIGHT_SX_SIG0", 0, 15, &umr_bitfield_default }, + { "UNUSED_0", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_WEIGHT_SXRB_0[] = { + { "WEIGHT_SXRB_SIG0", 0, 15, &umr_bitfield_default }, + { "WEIGHT_SXRB_SIG1", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_WEIGHT_TA_0[] = { + { "WEIGHT_TA_SIG0", 0, 15, &umr_bitfield_default }, + { "UNUSED_0", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_WEIGHT_TCC_0[] = { + { "WEIGHT_TCC_SIG0", 0, 15, &umr_bitfield_default }, + { "WEIGHT_TCC_SIG1", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_WEIGHT_TCC_1[] = { + { "WEIGHT_TCC_SIG2", 0, 15, &umr_bitfield_default }, + { "WEIGHT_TCC_SIG3", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_WEIGHT_TCC_2[] = { + { "WEIGHT_TCC_SIG4", 0, 15, &umr_bitfield_default }, + { "UNUSED_0", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_WEIGHT_TCP_0[] = { + { "WEIGHT_TCP_SIG0", 0, 15, &umr_bitfield_default }, + { "WEIGHT_TCP_SIG1", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_WEIGHT_TCP_1[] = { + { "WEIGHT_TCP_SIG2", 0, 15, &umr_bitfield_default }, + { "WEIGHT_TCP_SIG3", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_WEIGHT_TCP_2[] = { + { "WEIGHT_TCP_SIG4", 0, 15, &umr_bitfield_default }, + { "UNUSED_0", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_WEIGHT_TD_0[] = { + { "WEIGHT_TD_SIG0", 0, 15, &umr_bitfield_default }, + { "WEIGHT_TD_SIG1", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_WEIGHT_TD_1[] = { + { "WEIGHT_TD_SIG2", 0, 15, &umr_bitfield_default }, + { "WEIGHT_TD_SIG3", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_WEIGHT_TD_2[] = { + { "WEIGHT_TD_SIG4", 0, 15, &umr_bitfield_default }, + { "WEIGHT_TD_SIG5", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_WEIGHT_VGT_0[] = { + { "WEIGHT_VGT_SIG0", 0, 15, &umr_bitfield_default }, + { "WEIGHT_VGT_SIG1", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_WEIGHT_VGT_1[] = { + { "WEIGHT_VGT_SIG2", 0, 15, &umr_bitfield_default }, + { "UNUSED_0", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_WEIGHT_WD_0[] = { + { "WEIGHT_WD_SIG0", 0, 15, &umr_bitfield_default }, + { "UNUSED_0", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_WEIGHT_CU_0[] = { + { "WEIGHT_CU_SIG0", 0, 15, &umr_bitfield_default }, + { "WEIGHT_CU_SIG1", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_WEIGHT_CU_1[] = { + { "WEIGHT_CU_SIG2", 0, 15, &umr_bitfield_default }, + { "WEIGHT_CU_SIG3", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_WEIGHT_CU_2[] = { + { "WEIGHT_CU_SIG4", 0, 15, &umr_bitfield_default }, + { "WEIGHT_CU_SIG5", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_WEIGHT_CU_3[] = { + { "WEIGHT_CU_SIG6", 0, 15, &umr_bitfield_default }, + { "WEIGHT_CU_SIG7", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_WEIGHT_CU_4[] = { + { "WEIGHT_CU_SIG8", 0, 15, &umr_bitfield_default }, + { "WEIGHT_CU_SIG9", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_WEIGHT_CU_5[] = { + { "WEIGHT_CU_SIG10", 0, 15, &umr_bitfield_default }, + { "WEIGHT_CU_SIG11", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_BCI0[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_CB0[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_CB1[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_CB2[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_CB3[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_CP0[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_CP1[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_CP2[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_DB0[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_DB1[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_DB2[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_DB3[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_GDS0[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_GDS1[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_GDS2[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_GDS3[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_IA0[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_LDS0[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_LDS1[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_LDS2[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_LDS3[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_PA0[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_PA1[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_PC0[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_SC0[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_SPI0[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_SPI1[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_SPI2[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_SPI3[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_SPI4[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_SPI5[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_WEIGHT_PG_0[] = { + { "WEIGHT_PG_SIG0", 0, 15, &umr_bitfield_default }, + { "unused", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_PG0[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_OVRD_PG[] = { + { "OVRRD_SELECT", 0, 15, &umr_bitfield_default }, + { "OVRRD_VALUE", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_WEIGHT_UTCL2_ATCL2_0[] = { + { "WEIGHT_UTCL2_ATCL2_SIG0", 0, 15, &umr_bitfield_default }, + { "WEIGHT_UTCL2_ATCL2_SIG1", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_EA0[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_EA1[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_EA2[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_EA3[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_UTCL2_ATCL20[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_OVRD_EA[] = { + { "OVRRD_SELECT", 0, 5, &umr_bitfield_default }, + { "OVRRD_VALUE", 6, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_OVRD_UTCL2_ATCL2[] = { + { "OVRRD_SELECT", 0, 4, &umr_bitfield_default }, + { "OVRRD_VALUE", 5, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_WEIGHT_EA_0[] = { + { "WEIGHT_EA_SIG0", 0, 15, &umr_bitfield_default }, + { "WEIGHT_EA_SIG1", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_WEIGHT_EA_1[] = { + { "WEIGHT_EA_SIG2", 0, 15, &umr_bitfield_default }, + { "WEIGHT_EA_SIG3", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_WEIGHT_RMI_0[] = { + { "WEIGHT_RMI_SIG0", 0, 15, &umr_bitfield_default }, + { "UNUSED", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_RMI0[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_OVRD_RMI[] = { + { "OVRRD_SELECT", 0, 0, &umr_bitfield_default }, + { "OVRRD_VALUE", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_WEIGHT_UTCL2_ATCL2_1[] = { + { "WEIGHT_UTCL2_ATCL2_SIG2", 0, 15, &umr_bitfield_default }, + { "WEIGHT_UTCL2_ATCL2_SIG3", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_UTCL2_ATCL21[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_UTCL2_ATCL22[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_UTCL2_ATCL23[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_EA4[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_EA5[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_WEIGHT_EA_2[] = { + { "WEIGHT_EA_SIG4", 0, 15, &umr_bitfield_default }, + { "WEIGHT_EA_SIG5", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_SQ0_LOWER[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_SQ0_UPPER[] = { + { "ACCUMULATOR_39_32", 0, 7, &umr_bitfield_default }, + { "UNUSED_0", 8, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_SQ1_LOWER[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_SQ1_UPPER[] = { + { "ACCUMULATOR_39_32", 0, 7, &umr_bitfield_default }, + { "UNUSED_0", 8, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_SQ2_LOWER[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_SQ2_UPPER[] = { + { "ACCUMULATOR_39_32", 0, 7, &umr_bitfield_default }, + { "UNUSED_0", 8, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_SQ3_LOWER[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_SQ3_UPPER[] = { + { "ACCUMULATOR_39_32", 0, 7, &umr_bitfield_default }, + { "UNUSED_0", 8, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_SQ4_LOWER[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_SQ4_UPPER[] = { + { "ACCUMULATOR_39_32", 0, 7, &umr_bitfield_default }, + { "UNUSED_0", 8, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_SQ5_LOWER[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_SQ5_UPPER[] = { + { "ACCUMULATOR_39_32", 0, 7, &umr_bitfield_default }, + { "UNUSED_0", 8, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_SQ6_LOWER[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_SQ6_UPPER[] = { + { "ACCUMULATOR_39_32", 0, 7, &umr_bitfield_default }, + { "UNUSED_0", 8, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_SQ7_LOWER[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_SQ7_UPPER[] = { + { "ACCUMULATOR_39_32", 0, 7, &umr_bitfield_default }, + { "UNUSED_0", 8, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_SQ8_LOWER[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_SQ8_UPPER[] = { + { "ACCUMULATOR_39_32", 0, 7, &umr_bitfield_default }, + { "UNUSED_0", 8, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_SX0[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_SXRB0[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_SXRB1[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_TA0[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_TCC0[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_TCC1[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_TCC2[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_TCC3[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_TCC4[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_TCP0[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_TCP1[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_TCP2[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_TCP3[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_TCP4[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_TD0[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_TD1[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_TD2[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_TD3[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_TD4[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_TD5[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_VGT0[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_VGT1[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_VGT2[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_WD0[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_CU0[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_CU1[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_CU2[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_CU3[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_CU4[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_CU5[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_CU6[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_CU7[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_CU8[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_CU9[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_CU10[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_OVRD_BCI[] = { + { "OVRRD_SELECT", 0, 1, &umr_bitfield_default }, + { "OVRRD_VALUE", 2, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_OVRD_CB[] = { + { "OVRRD_SELECT", 0, 3, &umr_bitfield_default }, + { "OVRRD_VALUE", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_OVRD_CP[] = { + { "OVRRD_SELECT", 0, 2, &umr_bitfield_default }, + { "OVRRD_VALUE", 3, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_OVRD_DB[] = { + { "OVRRD_SELECT", 0, 3, &umr_bitfield_default }, + { "OVRRD_VALUE", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_OVRD_GDS[] = { + { "OVRRD_SELECT", 0, 3, &umr_bitfield_default }, + { "OVRRD_VALUE", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_OVRD_IA[] = { + { "OVRRD_SELECT", 0, 0, &umr_bitfield_default }, + { "OVRRD_VALUE", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_OVRD_LDS[] = { + { "OVRRD_SELECT", 0, 3, &umr_bitfield_default }, + { "OVRRD_VALUE", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_OVRD_PA[] = { + { "OVRRD_SELECT", 0, 1, &umr_bitfield_default }, + { "OVRRD_VALUE", 2, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_OVRD_PC[] = { + { "OVRRD_SELECT", 0, 0, &umr_bitfield_default }, + { "OVRRD_VALUE", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_OVRD_SC[] = { + { "OVRRD_SELECT", 0, 0, &umr_bitfield_default }, + { "OVRRD_VALUE", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_OVRD_SPI[] = { + { "OVRRD_SELECT", 0, 5, &umr_bitfield_default }, + { "OVRRD_VALUE", 6, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_OVRD_CU[] = { + { "OVRRD_SELECT", 0, 0, &umr_bitfield_default }, + { "OVRRD_VALUE", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_OVRD_SQ[] = { + { "OVRRD_SELECT", 0, 8, &umr_bitfield_default }, + { "OVRRD_VALUE", 9, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_OVRD_SX[] = { + { "OVRRD_SELECT", 0, 0, &umr_bitfield_default }, + { "OVRRD_VALUE", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_OVRD_SXRB[] = { + { "OVRRD_SELECT", 0, 0, &umr_bitfield_default }, + { "OVRRD_VALUE", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_OVRD_TA[] = { + { "OVRRD_SELECT", 0, 0, &umr_bitfield_default }, + { "OVRRD_VALUE", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_OVRD_TCC[] = { + { "OVRRD_SELECT", 0, 4, &umr_bitfield_default }, + { "OVRRD_VALUE", 5, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_OVRD_TCP[] = { + { "OVRRD_SELECT", 0, 4, &umr_bitfield_default }, + { "OVRRD_VALUE", 5, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_OVRD_TD[] = { + { "OVRRD_SELECT", 0, 5, &umr_bitfield_default }, + { "OVRRD_VALUE", 6, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_OVRD_VGT[] = { + { "OVRRD_SELECT", 0, 2, &umr_bitfield_default }, + { "OVRRD_VALUE", 3, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_OVRD_WD[] = { + { "OVRRD_SELECT", 0, 0, &umr_bitfield_default }, + { "OVRRD_VALUE", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_BCI1[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_WEIGHT_UTCL2_ATCL2_2[] = { + { "WEIGHT_UTCL2_ATCL2_SIG4", 0, 15, &umr_bitfield_default }, + { "WEIGHT_UTCL2_ATCL2_SIG5", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_WEIGHT_UTCL2_ROUTER_0[] = { + { "WEIGHT_UTCL2_ROUTER_SIG0", 0, 15, &umr_bitfield_default }, + { "WEIGHT_UTCL2_ROUTER_SIG1", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_WEIGHT_UTCL2_ROUTER_1[] = { + { "WEIGHT_UTCL2_ROUTER_SIG2", 0, 15, &umr_bitfield_default }, + { "WEIGHT_UTCL2_ROUTER_SIG3", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_WEIGHT_UTCL2_ROUTER_2[] = { + { "WEIGHT_UTCL2_ROUTER_SIG4", 0, 15, &umr_bitfield_default }, + { "WEIGHT_UTCL2_ROUTER_SIG5", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_WEIGHT_UTCL2_ROUTER_3[] = { + { "WEIGHT_UTCL2_ROUTER_SIG6", 0, 15, &umr_bitfield_default }, + { "WEIGHT_UTCL2_ROUTER_SIG7", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_WEIGHT_UTCL2_ROUTER_4[] = { + { "WEIGHT_UTCL2_ROUTER_SIG8", 0, 15, &umr_bitfield_default }, + { "WEIGHT_UTCL2_ROUTER_SIG9", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_WEIGHT_UTCL2_VML2_0[] = { + { "WEIGHT_UTCL2_VML2_SIG0", 0, 15, &umr_bitfield_default }, + { "WEIGHT_UTCL2_VML2_SIG1", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_WEIGHT_UTCL2_VML2_1[] = { + { "WEIGHT_UTCL2_VML2_SIG2", 0, 15, &umr_bitfield_default }, + { "WEIGHT_UTCL2_VML2_SIG3", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_WEIGHT_UTCL2_VML2_2[] = { + { "WEIGHT_UTCL2_VML2_SIG4", 0, 15, &umr_bitfield_default }, + { "WEIGHT_UTCL2_VML2_SIG5", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_UTCL2_ATCL24[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_UTCL2_ROUTER0[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_UTCL2_ROUTER1[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_UTCL2_ROUTER2[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_UTCL2_ROUTER3[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_UTCL2_ROUTER4[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_UTCL2_ROUTER5[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_UTCL2_ROUTER6[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_UTCL2_ROUTER7[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_UTCL2_ROUTER8[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_UTCL2_ROUTER9[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_UTCL2_VML20[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_UTCL2_VML21[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_UTCL2_VML22[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_UTCL2_VML23[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_UTCL2_VML24[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_OVRD_UTCL2_ROUTER[] = { + { "OVRRD_SELECT", 0, 9, &umr_bitfield_default }, + { "OVRRD_VALUE", 10, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_OVRD_UTCL2_VML2[] = { + { "OVRRD_SELECT", 0, 4, &umr_bitfield_default }, + { "OVRRD_VALUE", 5, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_WEIGHT_UTCL2_WALKER_0[] = { + { "WEIGHT_UTCL2_WALKER_SIG0", 0, 15, &umr_bitfield_default }, + { "WEIGHT_UTCL2_WALKER_SIG1", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_WEIGHT_UTCL2_WALKER_1[] = { + { "WEIGHT_UTCL2_WALKER_SIG2", 0, 15, &umr_bitfield_default }, + { "WEIGHT_UTCL2_WALKER_SIG3", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_WEIGHT_UTCL2_WALKER_2[] = { + { "WEIGHT_UTCL2_WALKER_SIG4", 0, 15, &umr_bitfield_default }, + { "WEIGHT_UTCL2_WALKER_SIG5", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_UTCL2_WALKER0[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_UTCL2_WALKER1[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_UTCL2_WALKER2[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_UTCL2_WALKER3[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_ACC_UTCL2_WALKER4[] = { + { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixGC_CAC_OVRD_UTCL2_WALKER[] = { + { "OVRRD_SELECT", 0, 4, &umr_bitfield_default }, + { "OVRRD_VALUE", 5, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSE_CAC_CNTL[] = { + { "CAC_ENABLE", 0, 0, &umr_bitfield_default }, + { "CAC_THRESHOLD", 1, 16, &umr_bitfield_default }, + { "CAC_BLOCK_ID", 17, 22, &umr_bitfield_default }, + { "CAC_SIGNAL_ID", 23, 30, &umr_bitfield_default }, + { "UNUSED_0", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSE_CAC_OVR_SEL[] = { + { "CAC_OVR_SEL", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSE_CAC_OVR_VAL[] = { + { "CAC_OVR_VAL", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSQ_WAVE_MODE[] = { + { "FP_ROUND", 0, 3, &umr_bitfield_default }, + { "FP_DENORM", 4, 7, &umr_bitfield_default }, + { "DX10_CLAMP", 8, 8, &umr_bitfield_default }, + { "IEEE", 9, 9, &umr_bitfield_default }, + { "LOD_CLAMPED", 10, 10, &umr_bitfield_default }, + { "EXCP_EN", 12, 20, &umr_bitfield_default }, + { "FP16_OVFL", 23, 23, &umr_bitfield_default }, + { "POPS_PACKER0", 24, 24, &umr_bitfield_default }, + { "POPS_PACKER1", 25, 25, &umr_bitfield_default }, + { "DISABLE_PERF", 26, 26, &umr_bitfield_default }, + { "GPR_IDX_EN", 27, 27, &umr_bitfield_default }, + { "VSKIP", 28, 28, &umr_bitfield_default }, + { "CSP", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSQ_WAVE_STATUS[] = { + { "SCC", 0, 0, &umr_bitfield_default }, + { "SPI_PRIO", 1, 2, &umr_bitfield_default }, + { "USER_PRIO", 3, 4, &umr_bitfield_default }, + { "PRIV", 5, 5, &umr_bitfield_default }, + { "TRAP_EN", 6, 6, &umr_bitfield_default }, + { "TTRACE_EN", 7, 7, &umr_bitfield_default }, + { "EXPORT_RDY", 8, 8, &umr_bitfield_default }, + { "EXECZ", 9, 9, &umr_bitfield_default }, + { "VCCZ", 10, 10, &umr_bitfield_default }, + { "IN_TG", 11, 11, &umr_bitfield_default }, + { "IN_BARRIER", 12, 12, &umr_bitfield_default }, + { "HALT", 13, 13, &umr_bitfield_default }, + { "TRAP", 14, 14, &umr_bitfield_default }, + { "TTRACE_CU_EN", 15, 15, &umr_bitfield_default }, + { "VALID", 16, 16, &umr_bitfield_default }, + { "ECC_ERR", 17, 17, &umr_bitfield_default }, + { "SKIP_EXPORT", 18, 18, &umr_bitfield_default }, + { "PERF_EN", 19, 19, &umr_bitfield_default }, + { "ALLOW_REPLAY", 22, 22, &umr_bitfield_default }, + { "FATAL_HALT", 23, 23, &umr_bitfield_default }, + { "MUST_EXPORT", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSQ_WAVE_TRAPSTS[] = { + { "EXCP", 0, 8, &umr_bitfield_default }, + { "SAVECTX", 10, 10, &umr_bitfield_default }, + { "ILLEGAL_INST", 11, 11, &umr_bitfield_default }, + { "EXCP_HI", 12, 14, &umr_bitfield_default }, + { "EXCP_CYCLE", 16, 21, &umr_bitfield_default }, + { "XNACK_ERROR", 28, 28, &umr_bitfield_default }, + { "DP_RATE", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSQ_WAVE_HW_ID[] = { + { "WAVE_ID", 0, 3, &umr_bitfield_default }, + { "SIMD_ID", 4, 5, &umr_bitfield_default }, + { "PIPE_ID", 6, 7, &umr_bitfield_default }, + { "CU_ID", 8, 11, &umr_bitfield_default }, + { "SH_ID", 12, 12, &umr_bitfield_default }, + { "SE_ID", 13, 14, &umr_bitfield_default }, + { "TG_ID", 16, 19, &umr_bitfield_default }, + { "VM_ID", 20, 23, &umr_bitfield_default }, + { "QUEUE_ID", 24, 26, &umr_bitfield_default }, + { "STATE_ID", 27, 29, &umr_bitfield_default }, + { "ME_ID", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSQ_WAVE_GPR_ALLOC[] = { + { "VGPR_BASE", 0, 5, &umr_bitfield_default }, + { "VGPR_SIZE", 8, 13, &umr_bitfield_default }, + { "SGPR_BASE", 16, 21, &umr_bitfield_default }, + { "SGPR_SIZE", 24, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSQ_WAVE_LDS_ALLOC[] = { + { "LDS_BASE", 0, 7, &umr_bitfield_default }, + { "LDS_SIZE", 12, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSQ_WAVE_IB_STS[] = { + { "VM_CNT", 0, 3, &umr_bitfield_default }, + { "EXP_CNT", 4, 6, &umr_bitfield_default }, + { "LGKM_CNT", 8, 11, &umr_bitfield_default }, + { "VALU_CNT", 12, 14, &umr_bitfield_default }, + { "FIRST_REPLAY", 15, 15, &umr_bitfield_default }, + { "RCNT", 16, 20, &umr_bitfield_default }, + { "VM_CNT_HI", 22, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSQ_WAVE_PC_LO[] = { + { "PC_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSQ_WAVE_PC_HI[] = { + { "PC_HI", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSQ_WAVE_INST_DW0[] = { + { "INST_DW0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSQ_WAVE_INST_DW1[] = { + { "INST_DW1", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSQ_WAVE_IB_DBG0[] = { + { "IBUF_ST", 0, 2, &umr_bitfield_default }, + { "PC_INVALID", 3, 3, &umr_bitfield_default }, + { "NEED_NEXT_DW", 4, 4, &umr_bitfield_default }, + { "NO_PREFETCH_CNT", 5, 7, &umr_bitfield_default }, + { "IBUF_RPTR", 8, 9, &umr_bitfield_default }, + { "IBUF_WPTR", 10, 11, &umr_bitfield_default }, + { "INST_STR_ST", 16, 19, &umr_bitfield_default }, + { "ECC_ST", 24, 25, &umr_bitfield_default }, + { "IS_HYB", 26, 26, &umr_bitfield_default }, + { "HYB_CNT", 27, 28, &umr_bitfield_default }, + { "KILL", 29, 29, &umr_bitfield_default }, + { "NEED_KILL_IFETCH", 30, 30, &umr_bitfield_default }, + { "NO_PREFETCH_CNT_HI", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSQ_WAVE_IB_DBG1[] = { + { "IXNACK", 0, 0, &umr_bitfield_default }, + { "XNACK", 1, 1, &umr_bitfield_default }, + { "TA_NEED_RESET", 2, 2, &umr_bitfield_default }, + { "XCNT", 4, 8, &umr_bitfield_default }, + { "QCNT", 11, 15, &umr_bitfield_default }, + { "RCNT", 18, 22, &umr_bitfield_default }, + { "MISC_CNT", 25, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSQ_WAVE_FLUSH_IB[] = { + { "UNUSED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSQ_WAVE_TTMP0[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSQ_WAVE_TTMP1[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSQ_WAVE_TTMP2[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSQ_WAVE_TTMP3[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSQ_WAVE_TTMP4[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSQ_WAVE_TTMP5[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSQ_WAVE_TTMP6[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSQ_WAVE_TTMP7[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSQ_WAVE_TTMP8[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSQ_WAVE_TTMP9[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSQ_WAVE_TTMP10[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSQ_WAVE_TTMP11[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSQ_WAVE_TTMP12[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSQ_WAVE_TTMP13[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSQ_WAVE_TTMP14[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSQ_WAVE_TTMP15[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSQ_WAVE_M0[] = { + { "M0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSQ_WAVE_EXEC_LO[] = { + { "EXEC_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSQ_WAVE_EXEC_HI[] = { + { "EXEC_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSQ_INTERRUPT_WORD_AUTO_CTXID[] = { + { "THREAD_TRACE", 0, 0, &umr_bitfield_default }, + { "WLT", 1, 1, &umr_bitfield_default }, + { "THREAD_TRACE_BUF_FULL", 2, 2, &umr_bitfield_default }, + { "REG_TIMESTAMP", 3, 3, &umr_bitfield_default }, + { "CMD_TIMESTAMP", 4, 4, &umr_bitfield_default }, + { "HOST_CMD_OVERFLOW", 5, 5, &umr_bitfield_default }, + { "HOST_REG_OVERFLOW", 6, 6, &umr_bitfield_default }, + { "IMMED_OVERFLOW", 7, 7, &umr_bitfield_default }, + { "THREAD_TRACE_UTC_ERROR", 8, 8, &umr_bitfield_default }, + { "SE_ID", 24, 25, &umr_bitfield_default }, + { "ENCODING", 26, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSQ_INTERRUPT_WORD_AUTO_HI[] = { + { "SE_ID", 8, 9, &umr_bitfield_default }, + { "ENCODING", 10, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSQ_INTERRUPT_WORD_AUTO_LO[] = { + { "THREAD_TRACE", 0, 0, &umr_bitfield_default }, + { "WLT", 1, 1, &umr_bitfield_default }, + { "THREAD_TRACE_BUF_FULL", 2, 2, &umr_bitfield_default }, + { "REG_TIMESTAMP", 3, 3, &umr_bitfield_default }, + { "CMD_TIMESTAMP", 4, 4, &umr_bitfield_default }, + { "HOST_CMD_OVERFLOW", 5, 5, &umr_bitfield_default }, + { "HOST_REG_OVERFLOW", 6, 6, &umr_bitfield_default }, + { "IMMED_OVERFLOW", 7, 7, &umr_bitfield_default }, + { "THREAD_TRACE_UTC_ERROR", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSQ_INTERRUPT_WORD_CMN_CTXID[] = { + { "SE_ID", 24, 25, &umr_bitfield_default }, + { "ENCODING", 26, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSQ_INTERRUPT_WORD_CMN_HI[] = { + { "SE_ID", 8, 9, &umr_bitfield_default }, + { "ENCODING", 10, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSQ_INTERRUPT_WORD_WAVE_CTXID[] = { + { "DATA", 0, 11, &umr_bitfield_default }, + { "SH_ID", 12, 12, &umr_bitfield_default }, + { "PRIV", 13, 13, &umr_bitfield_default }, + { "WAVE_ID", 14, 17, &umr_bitfield_default }, + { "SIMD_ID", 18, 19, &umr_bitfield_default }, + { "CU_ID", 20, 23, &umr_bitfield_default }, + { "SE_ID", 24, 25, &umr_bitfield_default }, + { "ENCODING", 26, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSQ_INTERRUPT_WORD_WAVE_HI[] = { + { "CU_ID", 0, 3, &umr_bitfield_default }, + { "VM_ID", 4, 7, &umr_bitfield_default }, + { "SE_ID", 8, 9, &umr_bitfield_default }, + { "ENCODING", 10, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSQ_INTERRUPT_WORD_WAVE_LO[] = { + { "DATA", 0, 23, &umr_bitfield_default }, + { "SH_ID", 24, 24, &umr_bitfield_default }, + { "PRIV", 25, 25, &umr_bitfield_default }, + { "WAVE_ID", 26, 29, &umr_bitfield_default }, + { "SIMD_ID", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_SQ_CTRL0[] = { + { "DIDT_CTRL_EN", 0, 0, &umr_bitfield_default }, + { "PHASE_OFFSET", 1, 2, &umr_bitfield_default }, + { "DIDT_CTRL_RST", 3, 3, &umr_bitfield_default }, + { "DIDT_CLK_EN_OVERRIDE", 4, 4, &umr_bitfield_default }, + { "DIDT_STALL_CTRL_EN", 5, 5, &umr_bitfield_default }, + { "DIDT_TUNING_CTRL_EN", 6, 6, &umr_bitfield_default }, + { "DIDT_STALL_AUTO_RELEASE_EN", 7, 7, &umr_bitfield_default }, + { "DIDT_HI_POWER_THRESHOLD", 8, 23, &umr_bitfield_default }, + { "DIDT_AUTO_MPD_EN", 24, 24, &umr_bitfield_default }, + { "DIDT_STALL_EVENT_EN", 25, 25, &umr_bitfield_default }, + { "DIDT_STALL_EVENT_COUNTER_CLEAR", 26, 26, &umr_bitfield_default }, + { "UNUSED_0", 27, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_SQ_CTRL1[] = { + { "MIN_POWER", 0, 15, &umr_bitfield_default }, + { "MAX_POWER", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_SQ_CTRL2[] = { + { "MAX_POWER_DELTA", 0, 13, &umr_bitfield_default }, + { "UNUSED_0", 14, 15, &umr_bitfield_default }, + { "SHORT_TERM_INTERVAL_SIZE", 16, 25, &umr_bitfield_default }, + { "UNUSED_1", 26, 26, &umr_bitfield_default }, + { "LONG_TERM_INTERVAL_RATIO", 27, 30, &umr_bitfield_default }, + { "UNUSED_2", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_SQ_STALL_CTRL[] = { + { "DIDT_STALL_DELAY_HI", 0, 5, &umr_bitfield_default }, + { "DIDT_STALL_DELAY_LO", 6, 11, &umr_bitfield_default }, + { "DIDT_MAX_STALLS_ALLOWED_HI", 12, 17, &umr_bitfield_default }, + { "DIDT_MAX_STALLS_ALLOWED_LO", 18, 23, &umr_bitfield_default }, + { "UNUSED_0", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_SQ_TUNING_CTRL[] = { + { "MAX_POWER_DELTA_HI", 0, 13, &umr_bitfield_default }, + { "MAX_POWER_DELTA_LO", 14, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_SQ_STALL_AUTO_RELEASE_CTRL[] = { + { "DIDT_STALL_AUTO_RELEASE_TIME", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_SQ_CTRL3[] = { + { "GC_DIDT_ENABLE", 0, 0, &umr_bitfield_default }, + { "GC_DIDT_CLK_EN_OVERRIDE", 1, 1, &umr_bitfield_default }, + { "THROTTLE_POLICY", 2, 3, &umr_bitfield_default }, + { "DIDT_TRIGGER_THROTTLE_LOWBIT", 4, 8, &umr_bitfield_default }, + { "DIDT_POWER_LEVEL_LOWBIT", 9, 13, &umr_bitfield_default }, + { "DIDT_STALL_PATTERN_BIT_NUMS", 14, 21, &umr_bitfield_default }, + { "GC_DIDT_LEVEL_COMB_EN", 22, 22, &umr_bitfield_default }, + { "SE_DIDT_LEVEL_COMB_EN", 23, 23, &umr_bitfield_default }, + { "QUALIFY_STALL_EN", 24, 24, &umr_bitfield_default }, + { "DIDT_STALL_SEL", 25, 26, &umr_bitfield_default }, + { "DIDT_FORCE_STALL", 27, 27, &umr_bitfield_default }, + { "DIDT_STALL_DELAY_EN", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_SQ_STALL_PATTERN_1_2[] = { + { "DIDT_STALL_PATTERN_1", 0, 14, &umr_bitfield_default }, + { "UNUSED_0", 15, 15, &umr_bitfield_default }, + { "DIDT_STALL_PATTERN_2", 16, 30, &umr_bitfield_default }, + { "UNUSED_1", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_SQ_STALL_PATTERN_3_4[] = { + { "DIDT_STALL_PATTERN_3", 0, 14, &umr_bitfield_default }, + { "UNUSED_0", 15, 15, &umr_bitfield_default }, + { "DIDT_STALL_PATTERN_4", 16, 30, &umr_bitfield_default }, + { "UNUSED_1", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_SQ_STALL_PATTERN_5_6[] = { + { "DIDT_STALL_PATTERN_5", 0, 14, &umr_bitfield_default }, + { "UNUSED_0", 15, 15, &umr_bitfield_default }, + { "DIDT_STALL_PATTERN_6", 16, 30, &umr_bitfield_default }, + { "UNUSED_1", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_SQ_STALL_PATTERN_7[] = { + { "DIDT_STALL_PATTERN_7", 0, 14, &umr_bitfield_default }, + { "UNUSED_0", 15, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_SQ_WEIGHT0_3[] = { + { "WEIGHT0", 0, 7, &umr_bitfield_default }, + { "WEIGHT1", 8, 15, &umr_bitfield_default }, + { "WEIGHT2", 16, 23, &umr_bitfield_default }, + { "WEIGHT3", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_SQ_WEIGHT4_7[] = { + { "WEIGHT4", 0, 7, &umr_bitfield_default }, + { "WEIGHT5", 8, 15, &umr_bitfield_default }, + { "WEIGHT6", 16, 23, &umr_bitfield_default }, + { "WEIGHT7", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_SQ_WEIGHT8_11[] = { + { "WEIGHT8", 0, 7, &umr_bitfield_default }, + { "WEIGHT9", 8, 15, &umr_bitfield_default }, + { "WEIGHT10", 16, 23, &umr_bitfield_default }, + { "WEIGHT11", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_SQ_EDC_CTRL[] = { + { "EDC_EN", 0, 0, &umr_bitfield_default }, + { "EDC_SW_RST", 1, 1, &umr_bitfield_default }, + { "EDC_CLK_EN_OVERRIDE", 2, 2, &umr_bitfield_default }, + { "EDC_FORCE_STALL", 3, 3, &umr_bitfield_default }, + { "EDC_TRIGGER_THROTTLE_LOWBIT", 4, 8, &umr_bitfield_default }, + { "EDC_STALL_PATTERN_BIT_NUMS", 9, 16, &umr_bitfield_default }, + { "EDC_ALLOW_WRITE_PWRDELTA", 17, 17, &umr_bitfield_default }, + { "GC_EDC_EN", 18, 18, &umr_bitfield_default }, + { "GC_EDC_STALL_POLICY", 19, 20, &umr_bitfield_default }, + { "GC_EDC_LEVEL_COMB_EN", 21, 21, &umr_bitfield_default }, + { "SE_EDC_LEVEL_COMB_EN", 22, 22, &umr_bitfield_default }, + { "UNUSED_0", 23, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_SQ_EDC_THRESHOLD[] = { + { "EDC_THRESHOLD", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_SQ_EDC_STALL_PATTERN_1_2[] = { + { "EDC_STALL_PATTERN_1", 0, 14, &umr_bitfield_default }, + { "UNUSED_0", 15, 15, &umr_bitfield_default }, + { "EDC_STALL_PATTERN_2", 16, 30, &umr_bitfield_default }, + { "UNUSED_1", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_SQ_EDC_STALL_PATTERN_3_4[] = { + { "EDC_STALL_PATTERN_3", 0, 14, &umr_bitfield_default }, + { "UNUSED_0", 15, 15, &umr_bitfield_default }, + { "EDC_STALL_PATTERN_4", 16, 30, &umr_bitfield_default }, + { "UNUSED_1", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_SQ_EDC_STALL_PATTERN_5_6[] = { + { "EDC_STALL_PATTERN_5", 0, 14, &umr_bitfield_default }, + { "UNUSED_0", 15, 15, &umr_bitfield_default }, + { "EDC_STALL_PATTERN_6", 16, 30, &umr_bitfield_default }, + { "UNUSED_1", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_SQ_EDC_STALL_PATTERN_7[] = { + { "EDC_STALL_PATTERN_7", 0, 14, &umr_bitfield_default }, + { "UNUSED_0", 15, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_SQ_EDC_STATUS[] = { + { "EDC_FSM_STATE", 0, 0, &umr_bitfield_default }, + { "EDC_THROTTLE_LEVEL", 1, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_SQ_EDC_STALL_DELAY_1[] = { + { "EDC_STALL_DELAY_SQ0", 0, 5, &umr_bitfield_default }, + { "EDC_STALL_DELAY_SQ1", 6, 11, &umr_bitfield_default }, + { "EDC_STALL_DELAY_SQ2", 12, 17, &umr_bitfield_default }, + { "EDC_STALL_DELAY_SQ3", 18, 23, &umr_bitfield_default }, + { "UNUSED", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_SQ_EDC_STALL_DELAY_2[] = { + { "EDC_STALL_DELAY_SQ4", 0, 5, &umr_bitfield_default }, + { "EDC_STALL_DELAY_SQ5", 6, 11, &umr_bitfield_default }, + { "EDC_STALL_DELAY_SQ6", 12, 17, &umr_bitfield_default }, + { "EDC_STALL_DELAY_SQ7", 18, 23, &umr_bitfield_default }, + { "UNUSED", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_SQ_EDC_STALL_DELAY_3[] = { + { "EDC_STALL_DELAY_SQ8", 0, 5, &umr_bitfield_default }, + { "EDC_STALL_DELAY_SQ9", 6, 11, &umr_bitfield_default }, + { "EDC_STALL_DELAY_SQ10", 12, 17, &umr_bitfield_default }, + { "UNUSED", 18, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_SQ_EDC_OVERFLOW[] = { + { "EDC_ROLLING_POWER_DELTA_OVERFLOW", 0, 0, &umr_bitfield_default }, + { "EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER", 1, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_SQ_EDC_ROLLING_POWER_DELTA[] = { + { "EDC_ROLLING_POWER_DELTA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_DB_CTRL0[] = { + { "DIDT_CTRL_EN", 0, 0, &umr_bitfield_default }, + { "PHASE_OFFSET", 1, 2, &umr_bitfield_default }, + { "DIDT_CTRL_RST", 3, 3, &umr_bitfield_default }, + { "DIDT_CLK_EN_OVERRIDE", 4, 4, &umr_bitfield_default }, + { "DIDT_STALL_CTRL_EN", 5, 5, &umr_bitfield_default }, + { "DIDT_TUNING_CTRL_EN", 6, 6, &umr_bitfield_default }, + { "DIDT_STALL_AUTO_RELEASE_EN", 7, 7, &umr_bitfield_default }, + { "DIDT_HI_POWER_THRESHOLD", 8, 23, &umr_bitfield_default }, + { "DIDT_AUTO_MPD_EN", 24, 24, &umr_bitfield_default }, + { "DIDT_STALL_EVENT_EN", 25, 25, &umr_bitfield_default }, + { "DIDT_STALL_EVENT_COUNTER_CLEAR", 26, 26, &umr_bitfield_default }, + { "UNUSED_0", 27, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_DB_CTRL1[] = { + { "MIN_POWER", 0, 15, &umr_bitfield_default }, + { "MAX_POWER", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_DB_CTRL2[] = { + { "MAX_POWER_DELTA", 0, 13, &umr_bitfield_default }, + { "UNUSED_0", 14, 15, &umr_bitfield_default }, + { "SHORT_TERM_INTERVAL_SIZE", 16, 25, &umr_bitfield_default }, + { "UNUSED_1", 26, 26, &umr_bitfield_default }, + { "LONG_TERM_INTERVAL_RATIO", 27, 30, &umr_bitfield_default }, + { "UNUSED_2", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_DB_STALL_CTRL[] = { + { "DIDT_STALL_DELAY_HI", 0, 5, &umr_bitfield_default }, + { "DIDT_STALL_DELAY_LO", 6, 11, &umr_bitfield_default }, + { "DIDT_MAX_STALLS_ALLOWED_HI", 12, 17, &umr_bitfield_default }, + { "DIDT_MAX_STALLS_ALLOWED_LO", 18, 23, &umr_bitfield_default }, + { "UNUSED_0", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_DB_TUNING_CTRL[] = { + { "MAX_POWER_DELTA_HI", 0, 13, &umr_bitfield_default }, + { "MAX_POWER_DELTA_LO", 14, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_DB_STALL_AUTO_RELEASE_CTRL[] = { + { "DIDT_STALL_AUTO_RELEASE_TIME", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_DB_CTRL3[] = { + { "GC_DIDT_ENABLE", 0, 0, &umr_bitfield_default }, + { "GC_DIDT_CLK_EN_OVERRIDE", 1, 1, &umr_bitfield_default }, + { "THROTTLE_POLICY", 2, 3, &umr_bitfield_default }, + { "DIDT_TRIGGER_THROTTLE_LOWBIT", 4, 8, &umr_bitfield_default }, + { "DIDT_POWER_LEVEL_LOWBIT", 9, 13, &umr_bitfield_default }, + { "DIDT_STALL_PATTERN_BIT_NUMS", 14, 21, &umr_bitfield_default }, + { "GC_DIDT_LEVEL_COMB_EN", 22, 22, &umr_bitfield_default }, + { "SE_DIDT_LEVEL_COMB_EN", 23, 23, &umr_bitfield_default }, + { "QUALIFY_STALL_EN", 24, 24, &umr_bitfield_default }, + { "DIDT_STALL_SEL", 25, 26, &umr_bitfield_default }, + { "DIDT_FORCE_STALL", 27, 27, &umr_bitfield_default }, + { "DIDT_STALL_DELAY_EN", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_DB_STALL_PATTERN_1_2[] = { + { "DIDT_STALL_PATTERN_1", 0, 14, &umr_bitfield_default }, + { "UNUSED_0", 15, 15, &umr_bitfield_default }, + { "DIDT_STALL_PATTERN_2", 16, 30, &umr_bitfield_default }, + { "UNUSED_1", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_DB_STALL_PATTERN_3_4[] = { + { "DIDT_STALL_PATTERN_3", 0, 14, &umr_bitfield_default }, + { "UNUSED_0", 15, 15, &umr_bitfield_default }, + { "DIDT_STALL_PATTERN_4", 16, 30, &umr_bitfield_default }, + { "UNUSED_1", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_DB_STALL_PATTERN_5_6[] = { + { "DIDT_STALL_PATTERN_5", 0, 14, &umr_bitfield_default }, + { "UNUSED_0", 15, 15, &umr_bitfield_default }, + { "DIDT_STALL_PATTERN_6", 16, 30, &umr_bitfield_default }, + { "UNUSED_1", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_DB_STALL_PATTERN_7[] = { + { "DIDT_STALL_PATTERN_7", 0, 14, &umr_bitfield_default }, + { "UNUSED_0", 15, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_DB_WEIGHT0_3[] = { + { "WEIGHT0", 0, 7, &umr_bitfield_default }, + { "WEIGHT1", 8, 15, &umr_bitfield_default }, + { "WEIGHT2", 16, 23, &umr_bitfield_default }, + { "WEIGHT3", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_DB_WEIGHT4_7[] = { + { "WEIGHT4", 0, 7, &umr_bitfield_default }, + { "WEIGHT5", 8, 15, &umr_bitfield_default }, + { "WEIGHT6", 16, 23, &umr_bitfield_default }, + { "WEIGHT7", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_DB_WEIGHT8_11[] = { + { "WEIGHT8", 0, 7, &umr_bitfield_default }, + { "WEIGHT9", 8, 15, &umr_bitfield_default }, + { "WEIGHT10", 16, 23, &umr_bitfield_default }, + { "WEIGHT11", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_DB_EDC_CTRL[] = { + { "EDC_EN", 0, 0, &umr_bitfield_default }, + { "EDC_SW_RST", 1, 1, &umr_bitfield_default }, + { "EDC_CLK_EN_OVERRIDE", 2, 2, &umr_bitfield_default }, + { "EDC_FORCE_STALL", 3, 3, &umr_bitfield_default }, + { "EDC_TRIGGER_THROTTLE_LOWBIT", 4, 8, &umr_bitfield_default }, + { "EDC_STALL_PATTERN_BIT_NUMS", 9, 16, &umr_bitfield_default }, + { "EDC_ALLOW_WRITE_PWRDELTA", 17, 17, &umr_bitfield_default }, + { "GC_EDC_EN", 18, 18, &umr_bitfield_default }, + { "GC_EDC_STALL_POLICY", 19, 20, &umr_bitfield_default }, + { "GC_EDC_LEVEL_COMB_EN", 21, 21, &umr_bitfield_default }, + { "SE_EDC_LEVEL_COMB_EN", 22, 22, &umr_bitfield_default }, + { "UNUSED_0", 23, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_DB_EDC_THRESHOLD[] = { + { "EDC_THRESHOLD", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_DB_EDC_STALL_PATTERN_1_2[] = { + { "EDC_STALL_PATTERN_1", 0, 14, &umr_bitfield_default }, + { "UNUSED_0", 15, 15, &umr_bitfield_default }, + { "EDC_STALL_PATTERN_2", 16, 30, &umr_bitfield_default }, + { "UNUSED_1", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_DB_EDC_STALL_PATTERN_3_4[] = { + { "EDC_STALL_PATTERN_3", 0, 14, &umr_bitfield_default }, + { "UNUSED_0", 15, 15, &umr_bitfield_default }, + { "EDC_STALL_PATTERN_4", 16, 30, &umr_bitfield_default }, + { "UNUSED_1", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_DB_EDC_STALL_PATTERN_5_6[] = { + { "EDC_STALL_PATTERN_5", 0, 14, &umr_bitfield_default }, + { "UNUSED_0", 15, 15, &umr_bitfield_default }, + { "EDC_STALL_PATTERN_6", 16, 30, &umr_bitfield_default }, + { "UNUSED_1", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_DB_EDC_STALL_PATTERN_7[] = { + { "EDC_STALL_PATTERN_7", 0, 14, &umr_bitfield_default }, + { "UNUSED_0", 15, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_DB_EDC_STATUS[] = { + { "EDC_FSM_STATE", 0, 0, &umr_bitfield_default }, + { "EDC_THROTTLE_LEVEL", 1, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_DB_EDC_STALL_DELAY_1[] = { + { "EDC_STALL_DELAY_DB0", 0, 2, &umr_bitfield_default }, + { "EDC_STALL_DELAY_DB1", 3, 5, &umr_bitfield_default }, + { "UNUSED", 6, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_DB_EDC_OVERFLOW[] = { + { "EDC_ROLLING_POWER_DELTA_OVERFLOW", 0, 0, &umr_bitfield_default }, + { "EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER", 1, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_DB_EDC_ROLLING_POWER_DELTA[] = { + { "EDC_ROLLING_POWER_DELTA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_TD_CTRL0[] = { + { "DIDT_CTRL_EN", 0, 0, &umr_bitfield_default }, + { "PHASE_OFFSET", 1, 2, &umr_bitfield_default }, + { "DIDT_CTRL_RST", 3, 3, &umr_bitfield_default }, + { "DIDT_CLK_EN_OVERRIDE", 4, 4, &umr_bitfield_default }, + { "DIDT_STALL_CTRL_EN", 5, 5, &umr_bitfield_default }, + { "DIDT_TUNING_CTRL_EN", 6, 6, &umr_bitfield_default }, + { "DIDT_STALL_AUTO_RELEASE_EN", 7, 7, &umr_bitfield_default }, + { "DIDT_HI_POWER_THRESHOLD", 8, 23, &umr_bitfield_default }, + { "DIDT_AUTO_MPD_EN", 24, 24, &umr_bitfield_default }, + { "DIDT_STALL_EVENT_EN", 25, 25, &umr_bitfield_default }, + { "DIDT_STALL_EVENT_COUNTER_CLEAR", 26, 26, &umr_bitfield_default }, + { "UNUSED_0", 27, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_TD_CTRL1[] = { + { "MIN_POWER", 0, 15, &umr_bitfield_default }, + { "MAX_POWER", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_TD_CTRL2[] = { + { "MAX_POWER_DELTA", 0, 13, &umr_bitfield_default }, + { "UNUSED_0", 14, 15, &umr_bitfield_default }, + { "SHORT_TERM_INTERVAL_SIZE", 16, 25, &umr_bitfield_default }, + { "UNUSED_1", 26, 26, &umr_bitfield_default }, + { "LONG_TERM_INTERVAL_RATIO", 27, 30, &umr_bitfield_default }, + { "UNUSED_2", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_TD_STALL_CTRL[] = { + { "DIDT_STALL_DELAY_HI", 0, 5, &umr_bitfield_default }, + { "DIDT_STALL_DELAY_LO", 6, 11, &umr_bitfield_default }, + { "DIDT_MAX_STALLS_ALLOWED_HI", 12, 17, &umr_bitfield_default }, + { "DIDT_MAX_STALLS_ALLOWED_LO", 18, 23, &umr_bitfield_default }, + { "UNUSED_0", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_TD_TUNING_CTRL[] = { + { "MAX_POWER_DELTA_HI", 0, 13, &umr_bitfield_default }, + { "MAX_POWER_DELTA_LO", 14, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_TD_STALL_AUTO_RELEASE_CTRL[] = { + { "DIDT_STALL_AUTO_RELEASE_TIME", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_TD_CTRL3[] = { + { "GC_DIDT_ENABLE", 0, 0, &umr_bitfield_default }, + { "GC_DIDT_CLK_EN_OVERRIDE", 1, 1, &umr_bitfield_default }, + { "THROTTLE_POLICY", 2, 3, &umr_bitfield_default }, + { "DIDT_TRIGGER_THROTTLE_LOWBIT", 4, 8, &umr_bitfield_default }, + { "DIDT_POWER_LEVEL_LOWBIT", 9, 13, &umr_bitfield_default }, + { "DIDT_STALL_PATTERN_BIT_NUMS", 14, 21, &umr_bitfield_default }, + { "GC_DIDT_LEVEL_COMB_EN", 22, 22, &umr_bitfield_default }, + { "SE_DIDT_LEVEL_COMB_EN", 23, 23, &umr_bitfield_default }, + { "QUALIFY_STALL_EN", 24, 24, &umr_bitfield_default }, + { "DIDT_STALL_SEL", 25, 26, &umr_bitfield_default }, + { "DIDT_FORCE_STALL", 27, 27, &umr_bitfield_default }, + { "DIDT_STALL_DELAY_EN", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_TD_STALL_PATTERN_1_2[] = { + { "DIDT_STALL_PATTERN_1", 0, 14, &umr_bitfield_default }, + { "UNUSED_0", 15, 15, &umr_bitfield_default }, + { "DIDT_STALL_PATTERN_2", 16, 30, &umr_bitfield_default }, + { "UNUSED_1", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_TD_STALL_PATTERN_3_4[] = { + { "DIDT_STALL_PATTERN_3", 0, 14, &umr_bitfield_default }, + { "UNUSED_0", 15, 15, &umr_bitfield_default }, + { "DIDT_STALL_PATTERN_4", 16, 30, &umr_bitfield_default }, + { "UNUSED_1", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_TD_STALL_PATTERN_5_6[] = { + { "DIDT_STALL_PATTERN_5", 0, 14, &umr_bitfield_default }, + { "UNUSED_0", 15, 15, &umr_bitfield_default }, + { "DIDT_STALL_PATTERN_6", 16, 30, &umr_bitfield_default }, + { "UNUSED_1", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_TD_STALL_PATTERN_7[] = { + { "DIDT_STALL_PATTERN_7", 0, 14, &umr_bitfield_default }, + { "UNUSED_0", 15, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_TD_WEIGHT0_3[] = { + { "WEIGHT0", 0, 7, &umr_bitfield_default }, + { "WEIGHT1", 8, 15, &umr_bitfield_default }, + { "WEIGHT2", 16, 23, &umr_bitfield_default }, + { "WEIGHT3", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_TD_WEIGHT4_7[] = { + { "WEIGHT4", 0, 7, &umr_bitfield_default }, + { "WEIGHT5", 8, 15, &umr_bitfield_default }, + { "WEIGHT6", 16, 23, &umr_bitfield_default }, + { "WEIGHT7", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_TD_WEIGHT8_11[] = { + { "WEIGHT8", 0, 7, &umr_bitfield_default }, + { "WEIGHT9", 8, 15, &umr_bitfield_default }, + { "WEIGHT10", 16, 23, &umr_bitfield_default }, + { "WEIGHT11", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_TD_EDC_CTRL[] = { + { "EDC_EN", 0, 0, &umr_bitfield_default }, + { "EDC_SW_RST", 1, 1, &umr_bitfield_default }, + { "EDC_CLK_EN_OVERRIDE", 2, 2, &umr_bitfield_default }, + { "EDC_FORCE_STALL", 3, 3, &umr_bitfield_default }, + { "EDC_TRIGGER_THROTTLE_LOWBIT", 4, 8, &umr_bitfield_default }, + { "EDC_STALL_PATTERN_BIT_NUMS", 9, 16, &umr_bitfield_default }, + { "EDC_ALLOW_WRITE_PWRDELTA", 17, 17, &umr_bitfield_default }, + { "GC_EDC_EN", 18, 18, &umr_bitfield_default }, + { "GC_EDC_STALL_POLICY", 19, 20, &umr_bitfield_default }, + { "GC_EDC_LEVEL_COMB_EN", 21, 21, &umr_bitfield_default }, + { "SE_EDC_LEVEL_COMB_EN", 22, 22, &umr_bitfield_default }, + { "UNUSED_0", 23, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_TD_EDC_THRESHOLD[] = { + { "EDC_THRESHOLD", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_TD_EDC_STALL_PATTERN_1_2[] = { + { "EDC_STALL_PATTERN_1", 0, 14, &umr_bitfield_default }, + { "UNUSED_0", 15, 15, &umr_bitfield_default }, + { "EDC_STALL_PATTERN_2", 16, 30, &umr_bitfield_default }, + { "UNUSED_1", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_TD_EDC_STALL_PATTERN_3_4[] = { + { "EDC_STALL_PATTERN_3", 0, 14, &umr_bitfield_default }, + { "UNUSED_0", 15, 15, &umr_bitfield_default }, + { "EDC_STALL_PATTERN_4", 16, 30, &umr_bitfield_default }, + { "UNUSED_1", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_TD_EDC_STALL_PATTERN_5_6[] = { + { "EDC_STALL_PATTERN_5", 0, 14, &umr_bitfield_default }, + { "UNUSED_0", 15, 15, &umr_bitfield_default }, + { "EDC_STALL_PATTERN_6", 16, 30, &umr_bitfield_default }, + { "UNUSED_1", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_TD_EDC_STALL_PATTERN_7[] = { + { "EDC_STALL_PATTERN_7", 0, 14, &umr_bitfield_default }, + { "UNUSED_0", 15, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_TD_EDC_STATUS[] = { + { "EDC_FSM_STATE", 0, 0, &umr_bitfield_default }, + { "EDC_THROTTLE_LEVEL", 1, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_TD_EDC_STALL_DELAY_1[] = { + { "EDC_STALL_DELAY_TD0", 0, 5, &umr_bitfield_default }, + { "EDC_STALL_DELAY_TD1", 6, 11, &umr_bitfield_default }, + { "EDC_STALL_DELAY_TD2", 12, 17, &umr_bitfield_default }, + { "EDC_STALL_DELAY_TD3", 18, 23, &umr_bitfield_default }, + { "UNUSED", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_TD_EDC_STALL_DELAY_2[] = { + { "EDC_STALL_DELAY_TD4", 0, 5, &umr_bitfield_default }, + { "EDC_STALL_DELAY_TD5", 6, 11, &umr_bitfield_default }, + { "EDC_STALL_DELAY_TD6", 12, 17, &umr_bitfield_default }, + { "EDC_STALL_DELAY_TD7", 18, 23, &umr_bitfield_default }, + { "UNUSED", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_TD_EDC_STALL_DELAY_3[] = { + { "EDC_STALL_DELAY_TD8", 0, 5, &umr_bitfield_default }, + { "EDC_STALL_DELAY_TD9", 6, 11, &umr_bitfield_default }, + { "EDC_STALL_DELAY_TD10", 12, 17, &umr_bitfield_default }, + { "UNUSED", 18, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_TD_EDC_OVERFLOW[] = { + { "EDC_ROLLING_POWER_DELTA_OVERFLOW", 0, 0, &umr_bitfield_default }, + { "EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER", 1, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_TD_EDC_ROLLING_POWER_DELTA[] = { + { "EDC_ROLLING_POWER_DELTA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_TCP_CTRL0[] = { + { "DIDT_CTRL_EN", 0, 0, &umr_bitfield_default }, + { "PHASE_OFFSET", 1, 2, &umr_bitfield_default }, + { "DIDT_CTRL_RST", 3, 3, &umr_bitfield_default }, + { "DIDT_CLK_EN_OVERRIDE", 4, 4, &umr_bitfield_default }, + { "DIDT_STALL_CTRL_EN", 5, 5, &umr_bitfield_default }, + { "DIDT_TUNING_CTRL_EN", 6, 6, &umr_bitfield_default }, + { "DIDT_STALL_AUTO_RELEASE_EN", 7, 7, &umr_bitfield_default }, + { "DIDT_HI_POWER_THRESHOLD", 8, 23, &umr_bitfield_default }, + { "DIDT_AUTO_MPD_EN", 24, 24, &umr_bitfield_default }, + { "DIDT_STALL_EVENT_EN", 25, 25, &umr_bitfield_default }, + { "DIDT_STALL_EVENT_COUNTER_CLEAR", 26, 26, &umr_bitfield_default }, + { "UNUSED_0", 27, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_TCP_CTRL1[] = { + { "MIN_POWER", 0, 15, &umr_bitfield_default }, + { "MAX_POWER", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_TCP_CTRL2[] = { + { "MAX_POWER_DELTA", 0, 13, &umr_bitfield_default }, + { "UNUSED_0", 14, 15, &umr_bitfield_default }, + { "SHORT_TERM_INTERVAL_SIZE", 16, 25, &umr_bitfield_default }, + { "UNUSED_1", 26, 26, &umr_bitfield_default }, + { "LONG_TERM_INTERVAL_RATIO", 27, 30, &umr_bitfield_default }, + { "UNUSED_2", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_TCP_STALL_CTRL[] = { + { "DIDT_STALL_DELAY_HI", 0, 5, &umr_bitfield_default }, + { "DIDT_STALL_DELAY_LO", 6, 11, &umr_bitfield_default }, + { "DIDT_MAX_STALLS_ALLOWED_HI", 12, 17, &umr_bitfield_default }, + { "DIDT_MAX_STALLS_ALLOWED_LO", 18, 23, &umr_bitfield_default }, + { "UNUSED_0", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_TCP_TUNING_CTRL[] = { + { "MAX_POWER_DELTA_HI", 0, 13, &umr_bitfield_default }, + { "MAX_POWER_DELTA_LO", 14, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_TCP_STALL_AUTO_RELEASE_CTRL[] = { + { "DIDT_STALL_AUTO_RELEASE_TIME", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_TCP_CTRL3[] = { + { "GC_DIDT_ENABLE", 0, 0, &umr_bitfield_default }, + { "GC_DIDT_CLK_EN_OVERRIDE", 1, 1, &umr_bitfield_default }, + { "THROTTLE_POLICY", 2, 3, &umr_bitfield_default }, + { "DIDT_TRIGGER_THROTTLE_LOWBIT", 4, 8, &umr_bitfield_default }, + { "DIDT_POWER_LEVEL_LOWBIT", 9, 13, &umr_bitfield_default }, + { "DIDT_STALL_PATTERN_BIT_NUMS", 14, 21, &umr_bitfield_default }, + { "GC_DIDT_LEVEL_COMB_EN", 22, 22, &umr_bitfield_default }, + { "SE_DIDT_LEVEL_COMB_EN", 23, 23, &umr_bitfield_default }, + { "QUALIFY_STALL_EN", 24, 24, &umr_bitfield_default }, + { "DIDT_STALL_SEL", 25, 26, &umr_bitfield_default }, + { "DIDT_FORCE_STALL", 27, 27, &umr_bitfield_default }, + { "DIDT_STALL_DELAY_EN", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_TCP_STALL_PATTERN_1_2[] = { + { "DIDT_STALL_PATTERN_1", 0, 14, &umr_bitfield_default }, + { "UNUSED_0", 15, 15, &umr_bitfield_default }, + { "DIDT_STALL_PATTERN_2", 16, 30, &umr_bitfield_default }, + { "UNUSED_1", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_TCP_STALL_PATTERN_3_4[] = { + { "DIDT_STALL_PATTERN_3", 0, 14, &umr_bitfield_default }, + { "UNUSED_0", 15, 15, &umr_bitfield_default }, + { "DIDT_STALL_PATTERN_4", 16, 30, &umr_bitfield_default }, + { "UNUSED_1", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_TCP_STALL_PATTERN_5_6[] = { + { "DIDT_STALL_PATTERN_5", 0, 14, &umr_bitfield_default }, + { "UNUSED_0", 15, 15, &umr_bitfield_default }, + { "DIDT_STALL_PATTERN_6", 16, 30, &umr_bitfield_default }, + { "UNUSED_1", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_TCP_STALL_PATTERN_7[] = { + { "DIDT_STALL_PATTERN_7", 0, 14, &umr_bitfield_default }, + { "UNUSED_0", 15, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_TCP_WEIGHT0_3[] = { + { "WEIGHT0", 0, 7, &umr_bitfield_default }, + { "WEIGHT1", 8, 15, &umr_bitfield_default }, + { "WEIGHT2", 16, 23, &umr_bitfield_default }, + { "WEIGHT3", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_TCP_WEIGHT4_7[] = { + { "WEIGHT4", 0, 7, &umr_bitfield_default }, + { "WEIGHT5", 8, 15, &umr_bitfield_default }, + { "WEIGHT6", 16, 23, &umr_bitfield_default }, + { "WEIGHT7", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_TCP_WEIGHT8_11[] = { + { "WEIGHT8", 0, 7, &umr_bitfield_default }, + { "WEIGHT9", 8, 15, &umr_bitfield_default }, + { "WEIGHT10", 16, 23, &umr_bitfield_default }, + { "WEIGHT11", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_TCP_EDC_CTRL[] = { + { "EDC_EN", 0, 0, &umr_bitfield_default }, + { "EDC_SW_RST", 1, 1, &umr_bitfield_default }, + { "EDC_CLK_EN_OVERRIDE", 2, 2, &umr_bitfield_default }, + { "EDC_FORCE_STALL", 3, 3, &umr_bitfield_default }, + { "EDC_TRIGGER_THROTTLE_LOWBIT", 4, 8, &umr_bitfield_default }, + { "EDC_STALL_PATTERN_BIT_NUMS", 9, 16, &umr_bitfield_default }, + { "EDC_ALLOW_WRITE_PWRDELTA", 17, 17, &umr_bitfield_default }, + { "GC_EDC_EN", 18, 18, &umr_bitfield_default }, + { "GC_EDC_STALL_POLICY", 19, 20, &umr_bitfield_default }, + { "GC_EDC_LEVEL_COMB_EN", 21, 21, &umr_bitfield_default }, + { "SE_EDC_LEVEL_COMB_EN", 22, 22, &umr_bitfield_default }, + { "UNUSED_0", 23, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_TCP_EDC_THRESHOLD[] = { + { "EDC_THRESHOLD", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_TCP_EDC_STALL_PATTERN_1_2[] = { + { "EDC_STALL_PATTERN_1", 0, 14, &umr_bitfield_default }, + { "UNUSED_0", 15, 15, &umr_bitfield_default }, + { "EDC_STALL_PATTERN_2", 16, 30, &umr_bitfield_default }, + { "UNUSED_1", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_TCP_EDC_STALL_PATTERN_3_4[] = { + { "EDC_STALL_PATTERN_3", 0, 14, &umr_bitfield_default }, + { "UNUSED_0", 15, 15, &umr_bitfield_default }, + { "EDC_STALL_PATTERN_4", 16, 30, &umr_bitfield_default }, + { "UNUSED_1", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_TCP_EDC_STALL_PATTERN_5_6[] = { + { "EDC_STALL_PATTERN_5", 0, 14, &umr_bitfield_default }, + { "UNUSED_0", 15, 15, &umr_bitfield_default }, + { "EDC_STALL_PATTERN_6", 16, 30, &umr_bitfield_default }, + { "UNUSED_1", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_TCP_EDC_STALL_PATTERN_7[] = { + { "EDC_STALL_PATTERN_7", 0, 14, &umr_bitfield_default }, + { "UNUSED_0", 15, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_TCP_EDC_STATUS[] = { + { "EDC_FSM_STATE", 0, 0, &umr_bitfield_default }, + { "EDC_THROTTLE_LEVEL", 1, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_TCP_EDC_STALL_DELAY_1[] = { + { "EDC_STALL_DELAY_TCP0", 0, 5, &umr_bitfield_default }, + { "EDC_STALL_DELAY_TCP1", 6, 11, &umr_bitfield_default }, + { "EDC_STALL_DELAY_TCP2", 12, 17, &umr_bitfield_default }, + { "EDC_STALL_DELAY_TCP3", 18, 23, &umr_bitfield_default }, + { "UNUSED", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_TCP_EDC_STALL_DELAY_2[] = { + { "EDC_STALL_DELAY_TCP4", 0, 5, &umr_bitfield_default }, + { "EDC_STALL_DELAY_TCP5", 6, 11, &umr_bitfield_default }, + { "EDC_STALL_DELAY_TCP6", 12, 17, &umr_bitfield_default }, + { "EDC_STALL_DELAY_TCP7", 18, 23, &umr_bitfield_default }, + { "UNUSED", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_TCP_EDC_STALL_DELAY_3[] = { + { "EDC_STALL_DELAY_TCP8", 0, 5, &umr_bitfield_default }, + { "EDC_STALL_DELAY_TCP9", 6, 11, &umr_bitfield_default }, + { "EDC_STALL_DELAY_TCP10", 12, 17, &umr_bitfield_default }, + { "UNUSED", 18, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_TCP_EDC_OVERFLOW[] = { + { "EDC_ROLLING_POWER_DELTA_OVERFLOW", 0, 0, &umr_bitfield_default }, + { "EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER", 1, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_TCP_EDC_ROLLING_POWER_DELTA[] = { + { "EDC_ROLLING_POWER_DELTA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_DBR_CTRL0[] = { + { "DIDT_CTRL_EN", 0, 0, &umr_bitfield_default }, + { "PHASE_OFFSET", 1, 2, &umr_bitfield_default }, + { "DIDT_CTRL_RST", 3, 3, &umr_bitfield_default }, + { "DIDT_CLK_EN_OVERRIDE", 4, 4, &umr_bitfield_default }, + { "DIDT_STALL_CTRL_EN", 5, 5, &umr_bitfield_default }, + { "DIDT_TUNING_CTRL_EN", 6, 6, &umr_bitfield_default }, + { "DIDT_STALL_AUTO_RELEASE_EN", 7, 7, &umr_bitfield_default }, + { "DIDT_HI_POWER_THRESHOLD", 8, 23, &umr_bitfield_default }, + { "DIDT_AUTO_MPD_EN", 24, 24, &umr_bitfield_default }, + { "DIDT_STALL_EVENT_EN", 25, 25, &umr_bitfield_default }, + { "DIDT_STALL_EVENT_COUNTER_CLEAR", 26, 26, &umr_bitfield_default }, + { "UNUSED_0", 27, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_DBR_CTRL1[] = { + { "MIN_POWER", 0, 15, &umr_bitfield_default }, + { "MAX_POWER", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_DBR_CTRL2[] = { + { "MAX_POWER_DELTA", 0, 13, &umr_bitfield_default }, + { "UNUSED_0", 14, 15, &umr_bitfield_default }, + { "SHORT_TERM_INTERVAL_SIZE", 16, 25, &umr_bitfield_default }, + { "UNUSED_1", 26, 26, &umr_bitfield_default }, + { "LONG_TERM_INTERVAL_RATIO", 27, 30, &umr_bitfield_default }, + { "UNUSED_2", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_DBR_STALL_CTRL[] = { + { "DIDT_STALL_DELAY_HI", 0, 5, &umr_bitfield_default }, + { "DIDT_STALL_DELAY_LO", 6, 11, &umr_bitfield_default }, + { "DIDT_MAX_STALLS_ALLOWED_HI", 12, 17, &umr_bitfield_default }, + { "DIDT_MAX_STALLS_ALLOWED_LO", 18, 23, &umr_bitfield_default }, + { "UNUSED_0", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_DBR_TUNING_CTRL[] = { + { "MAX_POWER_DELTA_HI", 0, 13, &umr_bitfield_default }, + { "MAX_POWER_DELTA_LO", 14, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_DBR_STALL_AUTO_RELEASE_CTRL[] = { + { "DIDT_STALL_AUTO_RELEASE_TIME", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_DBR_CTRL3[] = { + { "GC_DIDT_ENABLE", 0, 0, &umr_bitfield_default }, + { "GC_DIDT_CLK_EN_OVERRIDE", 1, 1, &umr_bitfield_default }, + { "THROTTLE_POLICY", 2, 3, &umr_bitfield_default }, + { "DIDT_TRIGGER_THROTTLE_LOWBIT", 4, 8, &umr_bitfield_default }, + { "DIDT_POWER_LEVEL_LOWBIT", 9, 13, &umr_bitfield_default }, + { "DIDT_STALL_PATTERN_BIT_NUMS", 14, 21, &umr_bitfield_default }, + { "GC_DIDT_LEVEL_COMB_EN", 22, 22, &umr_bitfield_default }, + { "SE_DIDT_LEVEL_COMB_EN", 23, 23, &umr_bitfield_default }, + { "QUALIFY_STALL_EN", 24, 24, &umr_bitfield_default }, + { "DIDT_STALL_SEL", 25, 26, &umr_bitfield_default }, + { "DIDT_FORCE_STALL", 27, 27, &umr_bitfield_default }, + { "DIDT_STALL_DELAY_EN", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_DBR_STALL_PATTERN_1_2[] = { + { "DIDT_STALL_PATTERN_1", 0, 14, &umr_bitfield_default }, + { "UNUSED_0", 15, 15, &umr_bitfield_default }, + { "DIDT_STALL_PATTERN_2", 16, 30, &umr_bitfield_default }, + { "UNUSED_1", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_DBR_STALL_PATTERN_3_4[] = { + { "DIDT_STALL_PATTERN_3", 0, 14, &umr_bitfield_default }, + { "UNUSED_0", 15, 15, &umr_bitfield_default }, + { "DIDT_STALL_PATTERN_4", 16, 30, &umr_bitfield_default }, + { "UNUSED_1", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_DBR_STALL_PATTERN_5_6[] = { + { "DIDT_STALL_PATTERN_5", 0, 14, &umr_bitfield_default }, + { "UNUSED_0", 15, 15, &umr_bitfield_default }, + { "DIDT_STALL_PATTERN_6", 16, 30, &umr_bitfield_default }, + { "UNUSED_1", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_DBR_STALL_PATTERN_7[] = { + { "DIDT_STALL_PATTERN_7", 0, 14, &umr_bitfield_default }, + { "UNUSED_0", 15, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_DBR_WEIGHT0_3[] = { + { "WEIGHT0", 0, 7, &umr_bitfield_default }, + { "WEIGHT1", 8, 15, &umr_bitfield_default }, + { "WEIGHT2", 16, 23, &umr_bitfield_default }, + { "WEIGHT3", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_DBR_WEIGHT4_7[] = { + { "WEIGHT4", 0, 7, &umr_bitfield_default }, + { "WEIGHT5", 8, 15, &umr_bitfield_default }, + { "WEIGHT6", 16, 23, &umr_bitfield_default }, + { "WEIGHT7", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_DBR_WEIGHT8_11[] = { + { "WEIGHT8", 0, 7, &umr_bitfield_default }, + { "WEIGHT9", 8, 15, &umr_bitfield_default }, + { "WEIGHT10", 16, 23, &umr_bitfield_default }, + { "WEIGHT11", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_DBR_EDC_CTRL[] = { + { "EDC_EN", 0, 0, &umr_bitfield_default }, + { "EDC_SW_RST", 1, 1, &umr_bitfield_default }, + { "EDC_CLK_EN_OVERRIDE", 2, 2, &umr_bitfield_default }, + { "EDC_FORCE_STALL", 3, 3, &umr_bitfield_default }, + { "EDC_TRIGGER_THROTTLE_LOWBIT", 4, 8, &umr_bitfield_default }, + { "EDC_STALL_PATTERN_BIT_NUMS", 9, 16, &umr_bitfield_default }, + { "EDC_ALLOW_WRITE_PWRDELTA", 17, 17, &umr_bitfield_default }, + { "GC_EDC_EN", 18, 18, &umr_bitfield_default }, + { "GC_EDC_STALL_POLICY", 19, 20, &umr_bitfield_default }, + { "GC_EDC_LEVEL_COMB_EN", 21, 21, &umr_bitfield_default }, + { "SE_EDC_LEVEL_COMB_EN", 22, 22, &umr_bitfield_default }, + { "UNUSED_0", 23, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_DBR_EDC_THRESHOLD[] = { + { "EDC_THRESHOLD", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_DBR_EDC_STALL_PATTERN_1_2[] = { + { "EDC_STALL_PATTERN_1", 0, 14, &umr_bitfield_default }, + { "UNUSED_0", 15, 15, &umr_bitfield_default }, + { "EDC_STALL_PATTERN_2", 16, 30, &umr_bitfield_default }, + { "UNUSED_1", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_DBR_EDC_STALL_PATTERN_3_4[] = { + { "EDC_STALL_PATTERN_3", 0, 14, &umr_bitfield_default }, + { "UNUSED_0", 15, 15, &umr_bitfield_default }, + { "EDC_STALL_PATTERN_4", 16, 30, &umr_bitfield_default }, + { "UNUSED_1", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_DBR_EDC_STALL_PATTERN_5_6[] = { + { "EDC_STALL_PATTERN_5", 0, 14, &umr_bitfield_default }, + { "UNUSED_0", 15, 15, &umr_bitfield_default }, + { "EDC_STALL_PATTERN_6", 16, 30, &umr_bitfield_default }, + { "UNUSED_1", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_DBR_EDC_STALL_PATTERN_7[] = { + { "EDC_STALL_PATTERN_7", 0, 14, &umr_bitfield_default }, + { "UNUSED_0", 15, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_DBR_EDC_STATUS[] = { + { "EDC_FSM_STATE", 0, 0, &umr_bitfield_default }, + { "EDC_THROTTLE_LEVEL", 1, 3, &umr_bitfield_default }, + { "UNUSED_0", 4, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_DBR_EDC_STALL_DELAY_1[] = { + { "EDC_STALL_DELAY_DBR0", 0, 0, &umr_bitfield_default }, + { "UNUSED", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_DBR_EDC_OVERFLOW[] = { + { "EDC_ROLLING_POWER_DELTA_OVERFLOW", 0, 0, &umr_bitfield_default }, + { "EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER", 1, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_DBR_EDC_ROLLING_POWER_DELTA[] = { + { "EDC_ROLLING_POWER_DELTA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_SQ_STALL_EVENT_COUNTER[] = { + { "DIDT_STALL_EVENT_COUNTER", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_DB_STALL_EVENT_COUNTER[] = { + { "DIDT_STALL_EVENT_COUNTER", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_TD_STALL_EVENT_COUNTER[] = { + { "DIDT_STALL_EVENT_COUNTER", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_TCP_STALL_EVENT_COUNTER[] = { + { "DIDT_STALL_EVENT_COUNTER", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixDIDT_DBR_STALL_EVENT_COUNTER[] = { + { "DIDT_STALL_EVENT_COUNTER", 0, 31, &umr_bitfield_default }, +}; diff --git a/src/lib/ip/gfx91_regs.i b/src/lib/ip/gfx91_regs.i new file mode 100644 index 0000000..d329e08 --- /dev/null +++ b/src/lib/ip/gfx91_regs.i @@ -0,0 +1,3836 @@ + { "mmGRBM_CNTL", REG_MMIO, 0x0000, 0, &mmGRBM_CNTL[0], sizeof(mmGRBM_CNTL)/sizeof(mmGRBM_CNTL[0]), 0, 0 }, + { "mmGRBM_SKEW_CNTL", REG_MMIO, 0x0001, 0, &mmGRBM_SKEW_CNTL[0], sizeof(mmGRBM_SKEW_CNTL)/sizeof(mmGRBM_SKEW_CNTL[0]), 0, 0 }, + { "mmGRBM_STATUS2", REG_MMIO, 0x0002, 0, &mmGRBM_STATUS2[0], sizeof(mmGRBM_STATUS2)/sizeof(mmGRBM_STATUS2[0]), 0, 0 }, + { "mmGRBM_PWR_CNTL", REG_MMIO, 0x0003, 0, &mmGRBM_PWR_CNTL[0], sizeof(mmGRBM_PWR_CNTL)/sizeof(mmGRBM_PWR_CNTL[0]), 0, 0 }, + { "mmGRBM_STATUS", REG_MMIO, 0x0004, 0, &mmGRBM_STATUS[0], sizeof(mmGRBM_STATUS)/sizeof(mmGRBM_STATUS[0]), 0, 0 }, + { "mmGRBM_STATUS_SE0", REG_MMIO, 0x0005, 0, &mmGRBM_STATUS_SE0[0], sizeof(mmGRBM_STATUS_SE0)/sizeof(mmGRBM_STATUS_SE0[0]), 0, 0 }, + { "mmGRBM_STATUS_SE1", REG_MMIO, 0x0006, 0, &mmGRBM_STATUS_SE1[0], sizeof(mmGRBM_STATUS_SE1)/sizeof(mmGRBM_STATUS_SE1[0]), 0, 0 }, + { "mmGRBM_SOFT_RESET", REG_MMIO, 0x0008, 0, &mmGRBM_SOFT_RESET[0], sizeof(mmGRBM_SOFT_RESET)/sizeof(mmGRBM_SOFT_RESET[0]), 0, 0 }, + { "mmGRBM_CGTT_CLK_CNTL", REG_MMIO, 0x000b, 0, &mmGRBM_CGTT_CLK_CNTL[0], sizeof(mmGRBM_CGTT_CLK_CNTL)/sizeof(mmGRBM_CGTT_CLK_CNTL[0]), 0, 0 }, + { "mmGRBM_GFX_CLKEN_CNTL", REG_MMIO, 0x000c, 0, &mmGRBM_GFX_CLKEN_CNTL[0], sizeof(mmGRBM_GFX_CLKEN_CNTL)/sizeof(mmGRBM_GFX_CLKEN_CNTL[0]), 0, 0 }, + { "mmGRBM_WAIT_IDLE_CLOCKS", REG_MMIO, 0x000d, 0, &mmGRBM_WAIT_IDLE_CLOCKS[0], sizeof(mmGRBM_WAIT_IDLE_CLOCKS)/sizeof(mmGRBM_WAIT_IDLE_CLOCKS[0]), 0, 0 }, + { "mmGRBM_STATUS_SE2", REG_MMIO, 0x000e, 0, &mmGRBM_STATUS_SE2[0], sizeof(mmGRBM_STATUS_SE2)/sizeof(mmGRBM_STATUS_SE2[0]), 0, 0 }, + { "mmGRBM_STATUS_SE3", REG_MMIO, 0x000f, 0, &mmGRBM_STATUS_SE3[0], sizeof(mmGRBM_STATUS_SE3)/sizeof(mmGRBM_STATUS_SE3[0]), 0, 0 }, + { "mmGRBM_READ_ERROR", REG_MMIO, 0x0016, 0, &mmGRBM_READ_ERROR[0], sizeof(mmGRBM_READ_ERROR)/sizeof(mmGRBM_READ_ERROR[0]), 0, 0 }, + { "mmGRBM_READ_ERROR2", REG_MMIO, 0x0017, 0, &mmGRBM_READ_ERROR2[0], sizeof(mmGRBM_READ_ERROR2)/sizeof(mmGRBM_READ_ERROR2[0]), 0, 0 }, + { "mmGRBM_INT_CNTL", REG_MMIO, 0x0018, 0, &mmGRBM_INT_CNTL[0], sizeof(mmGRBM_INT_CNTL)/sizeof(mmGRBM_INT_CNTL[0]), 0, 0 }, + { "mmGRBM_TRAP_OP", REG_MMIO, 0x0019, 0, &mmGRBM_TRAP_OP[0], sizeof(mmGRBM_TRAP_OP)/sizeof(mmGRBM_TRAP_OP[0]), 0, 0 }, + { "mmGRBM_TRAP_ADDR", REG_MMIO, 0x001a, 0, &mmGRBM_TRAP_ADDR[0], sizeof(mmGRBM_TRAP_ADDR)/sizeof(mmGRBM_TRAP_ADDR[0]), 0, 0 }, + { "mmGRBM_TRAP_ADDR_MSK", REG_MMIO, 0x001b, 0, &mmGRBM_TRAP_ADDR_MSK[0], sizeof(mmGRBM_TRAP_ADDR_MSK)/sizeof(mmGRBM_TRAP_ADDR_MSK[0]), 0, 0 }, + { "mmGRBM_TRAP_WD", REG_MMIO, 0x001c, 0, &mmGRBM_TRAP_WD[0], sizeof(mmGRBM_TRAP_WD)/sizeof(mmGRBM_TRAP_WD[0]), 0, 0 }, + { "mmGRBM_TRAP_WD_MSK", REG_MMIO, 0x001d, 0, &mmGRBM_TRAP_WD_MSK[0], sizeof(mmGRBM_TRAP_WD_MSK)/sizeof(mmGRBM_TRAP_WD_MSK[0]), 0, 0 }, + { "mmGRBM_DSM_BYPASS", REG_MMIO, 0x001e, 0, &mmGRBM_DSM_BYPASS[0], sizeof(mmGRBM_DSM_BYPASS)/sizeof(mmGRBM_DSM_BYPASS[0]), 0, 0 }, + { "mmGRBM_WRITE_ERROR", REG_MMIO, 0x001f, 0, &mmGRBM_WRITE_ERROR[0], sizeof(mmGRBM_WRITE_ERROR)/sizeof(mmGRBM_WRITE_ERROR[0]), 0, 0 }, + { "mmGRBM_IOV_ERROR", REG_MMIO, 0x0020, 0, &mmGRBM_IOV_ERROR[0], sizeof(mmGRBM_IOV_ERROR)/sizeof(mmGRBM_IOV_ERROR[0]), 0, 0 }, + { "mmGRBM_CHIP_REVISION", REG_MMIO, 0x0021, 0, &mmGRBM_CHIP_REVISION[0], sizeof(mmGRBM_CHIP_REVISION)/sizeof(mmGRBM_CHIP_REVISION[0]), 0, 0 }, + { "mmGRBM_GFX_CNTL", REG_MMIO, 0x0022, 0, &mmGRBM_GFX_CNTL[0], sizeof(mmGRBM_GFX_CNTL)/sizeof(mmGRBM_GFX_CNTL[0]), 0, 0 }, + { "mmGRBM_RSMU_CFG", REG_MMIO, 0x0023, 0, &mmGRBM_RSMU_CFG[0], sizeof(mmGRBM_RSMU_CFG)/sizeof(mmGRBM_RSMU_CFG[0]), 0, 0 }, + { "mmGRBM_IH_CREDIT", REG_MMIO, 0x0024, 0, &mmGRBM_IH_CREDIT[0], sizeof(mmGRBM_IH_CREDIT)/sizeof(mmGRBM_IH_CREDIT[0]), 0, 0 }, + { "mmGRBM_PWR_CNTL2", REG_MMIO, 0x0025, 0, &mmGRBM_PWR_CNTL2[0], sizeof(mmGRBM_PWR_CNTL2)/sizeof(mmGRBM_PWR_CNTL2[0]), 0, 0 }, + { "mmGRBM_UTCL2_INVAL_RANGE_START", REG_MMIO, 0x0026, 0, &mmGRBM_UTCL2_INVAL_RANGE_START[0], sizeof(mmGRBM_UTCL2_INVAL_RANGE_START)/sizeof(mmGRBM_UTCL2_INVAL_RANGE_START[0]), 0, 0 }, + { "mmGRBM_UTCL2_INVAL_RANGE_END", REG_MMIO, 0x0027, 0, &mmGRBM_UTCL2_INVAL_RANGE_END[0], sizeof(mmGRBM_UTCL2_INVAL_RANGE_END)/sizeof(mmGRBM_UTCL2_INVAL_RANGE_END[0]), 0, 0 }, + { "mmGRBM_RSMU_READ_ERROR", REG_MMIO, 0x0028, 0, &mmGRBM_RSMU_READ_ERROR[0], sizeof(mmGRBM_RSMU_READ_ERROR)/sizeof(mmGRBM_RSMU_READ_ERROR[0]), 0, 0 }, + { "mmGRBM_CHICKEN_BITS", REG_MMIO, 0x0029, 0, &mmGRBM_CHICKEN_BITS[0], sizeof(mmGRBM_CHICKEN_BITS)/sizeof(mmGRBM_CHICKEN_BITS[0]), 0, 0 }, + { "mmGRBM_NOWHERE", REG_MMIO, 0x003f, 0, &mmGRBM_NOWHERE[0], sizeof(mmGRBM_NOWHERE)/sizeof(mmGRBM_NOWHERE[0]), 0, 0 }, + { "mmGRBM_SCRATCH_REG0", REG_MMIO, 0x0040, 0, &mmGRBM_SCRATCH_REG0[0], sizeof(mmGRBM_SCRATCH_REG0)/sizeof(mmGRBM_SCRATCH_REG0[0]), 0, 0 }, + { "mmGRBM_SCRATCH_REG1", REG_MMIO, 0x0041, 0, &mmGRBM_SCRATCH_REG1[0], sizeof(mmGRBM_SCRATCH_REG1)/sizeof(mmGRBM_SCRATCH_REG1[0]), 0, 0 }, + { "mmGRBM_SCRATCH_REG2", REG_MMIO, 0x0042, 0, &mmGRBM_SCRATCH_REG2[0], sizeof(mmGRBM_SCRATCH_REG2)/sizeof(mmGRBM_SCRATCH_REG2[0]), 0, 0 }, + { "mmGRBM_SCRATCH_REG3", REG_MMIO, 0x0043, 0, &mmGRBM_SCRATCH_REG3[0], sizeof(mmGRBM_SCRATCH_REG3)/sizeof(mmGRBM_SCRATCH_REG3[0]), 0, 0 }, + { "mmGRBM_SCRATCH_REG4", REG_MMIO, 0x0044, 0, &mmGRBM_SCRATCH_REG4[0], sizeof(mmGRBM_SCRATCH_REG4)/sizeof(mmGRBM_SCRATCH_REG4[0]), 0, 0 }, + { "mmGRBM_SCRATCH_REG5", REG_MMIO, 0x0045, 0, &mmGRBM_SCRATCH_REG5[0], sizeof(mmGRBM_SCRATCH_REG5)/sizeof(mmGRBM_SCRATCH_REG5[0]), 0, 0 }, + { "mmGRBM_SCRATCH_REG6", REG_MMIO, 0x0046, 0, &mmGRBM_SCRATCH_REG6[0], sizeof(mmGRBM_SCRATCH_REG6)/sizeof(mmGRBM_SCRATCH_REG6[0]), 0, 0 }, + { "mmGRBM_SCRATCH_REG7", REG_MMIO, 0x0047, 0, &mmGRBM_SCRATCH_REG7[0], sizeof(mmGRBM_SCRATCH_REG7)/sizeof(mmGRBM_SCRATCH_REG7[0]), 0, 0 }, + { "mmCP_CPC_STATUS", REG_MMIO, 0x0084, 0, &mmCP_CPC_STATUS[0], sizeof(mmCP_CPC_STATUS)/sizeof(mmCP_CPC_STATUS[0]), 0, 0 }, + { "mmCP_CPC_BUSY_STAT", REG_MMIO, 0x0085, 0, &mmCP_CPC_BUSY_STAT[0], sizeof(mmCP_CPC_BUSY_STAT)/sizeof(mmCP_CPC_BUSY_STAT[0]), 0, 0 }, + { "mmCP_CPC_STALLED_STAT1", REG_MMIO, 0x0086, 0, &mmCP_CPC_STALLED_STAT1[0], sizeof(mmCP_CPC_STALLED_STAT1)/sizeof(mmCP_CPC_STALLED_STAT1[0]), 0, 0 }, + { "mmCP_CPF_STATUS", REG_MMIO, 0x0087, 0, &mmCP_CPF_STATUS[0], sizeof(mmCP_CPF_STATUS)/sizeof(mmCP_CPF_STATUS[0]), 0, 0 }, + { "mmCP_CPF_BUSY_STAT", REG_MMIO, 0x0088, 0, &mmCP_CPF_BUSY_STAT[0], sizeof(mmCP_CPF_BUSY_STAT)/sizeof(mmCP_CPF_BUSY_STAT[0]), 0, 0 }, + { "mmCP_CPF_STALLED_STAT1", REG_MMIO, 0x0089, 0, &mmCP_CPF_STALLED_STAT1[0], sizeof(mmCP_CPF_STALLED_STAT1)/sizeof(mmCP_CPF_STALLED_STAT1[0]), 0, 0 }, + { "mmCP_CPC_GRBM_FREE_COUNT", REG_MMIO, 0x008b, 0, &mmCP_CPC_GRBM_FREE_COUNT[0], sizeof(mmCP_CPC_GRBM_FREE_COUNT)/sizeof(mmCP_CPC_GRBM_FREE_COUNT[0]), 0, 0 }, + { "mmCP_MEC_CNTL", REG_MMIO, 0x008d, 0, &mmCP_MEC_CNTL[0], sizeof(mmCP_MEC_CNTL)/sizeof(mmCP_MEC_CNTL[0]), 0, 0 }, + { "mmCP_MEC_ME1_HEADER_DUMP", REG_MMIO, 0x008e, 0, &mmCP_MEC_ME1_HEADER_DUMP[0], sizeof(mmCP_MEC_ME1_HEADER_DUMP)/sizeof(mmCP_MEC_ME1_HEADER_DUMP[0]), 0, 0 }, + { "mmCP_MEC_ME2_HEADER_DUMP", REG_MMIO, 0x008f, 0, &mmCP_MEC_ME2_HEADER_DUMP[0], sizeof(mmCP_MEC_ME2_HEADER_DUMP)/sizeof(mmCP_MEC_ME2_HEADER_DUMP[0]), 0, 0 }, + { "mmCP_CPC_SCRATCH_INDEX", REG_MMIO, 0x0090, 0, &mmCP_CPC_SCRATCH_INDEX[0], sizeof(mmCP_CPC_SCRATCH_INDEX)/sizeof(mmCP_CPC_SCRATCH_INDEX[0]), 0, 0 }, + { "mmCP_CPC_SCRATCH_DATA", REG_MMIO, 0x0091, 0, &mmCP_CPC_SCRATCH_DATA[0], sizeof(mmCP_CPC_SCRATCH_DATA)/sizeof(mmCP_CPC_SCRATCH_DATA[0]), 0, 0 }, + { "mmCP_CPF_GRBM_FREE_COUNT", REG_MMIO, 0x0092, 0, &mmCP_CPF_GRBM_FREE_COUNT[0], sizeof(mmCP_CPF_GRBM_FREE_COUNT)/sizeof(mmCP_CPF_GRBM_FREE_COUNT[0]), 0, 0 }, + { "mmCP_CPC_HALT_HYST_COUNT", REG_MMIO, 0x00a7, 0, &mmCP_CPC_HALT_HYST_COUNT[0], sizeof(mmCP_CPC_HALT_HYST_COUNT)/sizeof(mmCP_CPC_HALT_HYST_COUNT[0]), 0, 0 }, + { "mmCP_PRT_LOD_STATS_CNTL0", REG_MMIO, 0x00ad, 0, &mmCP_PRT_LOD_STATS_CNTL0[0], sizeof(mmCP_PRT_LOD_STATS_CNTL0)/sizeof(mmCP_PRT_LOD_STATS_CNTL0[0]), 0, 0 }, + { "mmCP_PRT_LOD_STATS_CNTL1", REG_MMIO, 0x00ae, 0, &mmCP_PRT_LOD_STATS_CNTL1[0], sizeof(mmCP_PRT_LOD_STATS_CNTL1)/sizeof(mmCP_PRT_LOD_STATS_CNTL1[0]), 0, 0 }, + { "mmCP_PRT_LOD_STATS_CNTL2", REG_MMIO, 0x00af, 0, &mmCP_PRT_LOD_STATS_CNTL2[0], sizeof(mmCP_PRT_LOD_STATS_CNTL2)/sizeof(mmCP_PRT_LOD_STATS_CNTL2[0]), 0, 0 }, + { "mmCP_PRT_LOD_STATS_CNTL3", REG_MMIO, 0x00b0, 0, &mmCP_PRT_LOD_STATS_CNTL3[0], sizeof(mmCP_PRT_LOD_STATS_CNTL3)/sizeof(mmCP_PRT_LOD_STATS_CNTL3[0]), 0, 0 }, + { "mmCP_CE_COMPARE_COUNT", REG_MMIO, 0x00c0, 0, &mmCP_CE_COMPARE_COUNT[0], sizeof(mmCP_CE_COMPARE_COUNT)/sizeof(mmCP_CE_COMPARE_COUNT[0]), 0, 0 }, + { "mmCP_CE_DE_COUNT", REG_MMIO, 0x00c1, 0, &mmCP_CE_DE_COUNT[0], sizeof(mmCP_CE_DE_COUNT)/sizeof(mmCP_CE_DE_COUNT[0]), 0, 0 }, + { "mmCP_DE_CE_COUNT", REG_MMIO, 0x00c2, 0, &mmCP_DE_CE_COUNT[0], sizeof(mmCP_DE_CE_COUNT)/sizeof(mmCP_DE_CE_COUNT[0]), 0, 0 }, + { "mmCP_DE_LAST_INVAL_COUNT", REG_MMIO, 0x00c3, 0, &mmCP_DE_LAST_INVAL_COUNT[0], sizeof(mmCP_DE_LAST_INVAL_COUNT)/sizeof(mmCP_DE_LAST_INVAL_COUNT[0]), 0, 0 }, + { "mmCP_DE_DE_COUNT", REG_MMIO, 0x00c4, 0, &mmCP_DE_DE_COUNT[0], sizeof(mmCP_DE_DE_COUNT)/sizeof(mmCP_DE_DE_COUNT[0]), 0, 0 }, + { "mmCP_STALLED_STAT3", REG_MMIO, 0x019c, 0, &mmCP_STALLED_STAT3[0], sizeof(mmCP_STALLED_STAT3)/sizeof(mmCP_STALLED_STAT3[0]), 0, 0 }, + { "mmCP_STALLED_STAT1", REG_MMIO, 0x019d, 0, &mmCP_STALLED_STAT1[0], sizeof(mmCP_STALLED_STAT1)/sizeof(mmCP_STALLED_STAT1[0]), 0, 0 }, + { "mmCP_STALLED_STAT2", REG_MMIO, 0x019e, 0, &mmCP_STALLED_STAT2[0], sizeof(mmCP_STALLED_STAT2)/sizeof(mmCP_STALLED_STAT2[0]), 0, 0 }, + { "mmCP_BUSY_STAT", REG_MMIO, 0x019f, 0, &mmCP_BUSY_STAT[0], sizeof(mmCP_BUSY_STAT)/sizeof(mmCP_BUSY_STAT[0]), 0, 0 }, + { "mmCP_STAT", REG_MMIO, 0x01a0, 0, &mmCP_STAT[0], sizeof(mmCP_STAT)/sizeof(mmCP_STAT[0]), 0, 0 }, + { "mmCP_ME_HEADER_DUMP", REG_MMIO, 0x01a1, 0, &mmCP_ME_HEADER_DUMP[0], sizeof(mmCP_ME_HEADER_DUMP)/sizeof(mmCP_ME_HEADER_DUMP[0]), 0, 0 }, + { "mmCP_PFP_HEADER_DUMP", REG_MMIO, 0x01a2, 0, &mmCP_PFP_HEADER_DUMP[0], sizeof(mmCP_PFP_HEADER_DUMP)/sizeof(mmCP_PFP_HEADER_DUMP[0]), 0, 0 }, + { "mmCP_GRBM_FREE_COUNT", REG_MMIO, 0x01a3, 0, &mmCP_GRBM_FREE_COUNT[0], sizeof(mmCP_GRBM_FREE_COUNT)/sizeof(mmCP_GRBM_FREE_COUNT[0]), 0, 0 }, + { "mmCP_CE_HEADER_DUMP", REG_MMIO, 0x01a4, 0, &mmCP_CE_HEADER_DUMP[0], sizeof(mmCP_CE_HEADER_DUMP)/sizeof(mmCP_CE_HEADER_DUMP[0]), 0, 0 }, + { "mmCP_PFP_INSTR_PNTR", REG_MMIO, 0x01a5, 0, &mmCP_PFP_INSTR_PNTR[0], sizeof(mmCP_PFP_INSTR_PNTR)/sizeof(mmCP_PFP_INSTR_PNTR[0]), 0, 0 }, + { "mmCP_ME_INSTR_PNTR", REG_MMIO, 0x01a6, 0, &mmCP_ME_INSTR_PNTR[0], sizeof(mmCP_ME_INSTR_PNTR)/sizeof(mmCP_ME_INSTR_PNTR[0]), 0, 0 }, + { "mmCP_CE_INSTR_PNTR", REG_MMIO, 0x01a7, 0, &mmCP_CE_INSTR_PNTR[0], sizeof(mmCP_CE_INSTR_PNTR)/sizeof(mmCP_CE_INSTR_PNTR[0]), 0, 0 }, + { "mmCP_MEC1_INSTR_PNTR", REG_MMIO, 0x01a8, 0, &mmCP_MEC1_INSTR_PNTR[0], sizeof(mmCP_MEC1_INSTR_PNTR)/sizeof(mmCP_MEC1_INSTR_PNTR[0]), 0, 0 }, + { "mmCP_MEC2_INSTR_PNTR", REG_MMIO, 0x01a9, 0, &mmCP_MEC2_INSTR_PNTR[0], sizeof(mmCP_MEC2_INSTR_PNTR)/sizeof(mmCP_MEC2_INSTR_PNTR[0]), 0, 0 }, + { "mmCP_CSF_STAT", REG_MMIO, 0x01b4, 0, &mmCP_CSF_STAT[0], sizeof(mmCP_CSF_STAT)/sizeof(mmCP_CSF_STAT[0]), 0, 0 }, + { "mmCP_ME_CNTL", REG_MMIO, 0x01b6, 0, &mmCP_ME_CNTL[0], sizeof(mmCP_ME_CNTL)/sizeof(mmCP_ME_CNTL[0]), 0, 0 }, + { "mmCP_CNTX_STAT", REG_MMIO, 0x01b8, 0, &mmCP_CNTX_STAT[0], sizeof(mmCP_CNTX_STAT)/sizeof(mmCP_CNTX_STAT[0]), 0, 0 }, + { "mmCP_ME_PREEMPTION", REG_MMIO, 0x01b9, 0, &mmCP_ME_PREEMPTION[0], sizeof(mmCP_ME_PREEMPTION)/sizeof(mmCP_ME_PREEMPTION[0]), 0, 0 }, + { "mmCP_ROQ_THRESHOLDS", REG_MMIO, 0x01bc, 0, &mmCP_ROQ_THRESHOLDS[0], sizeof(mmCP_ROQ_THRESHOLDS)/sizeof(mmCP_ROQ_THRESHOLDS[0]), 0, 0 }, + { "mmCP_MEQ_STQ_THRESHOLD", REG_MMIO, 0x01bd, 0, &mmCP_MEQ_STQ_THRESHOLD[0], sizeof(mmCP_MEQ_STQ_THRESHOLD)/sizeof(mmCP_MEQ_STQ_THRESHOLD[0]), 0, 0 }, + { "mmCP_RB2_RPTR", REG_MMIO, 0x01be, 0, &mmCP_RB2_RPTR[0], sizeof(mmCP_RB2_RPTR)/sizeof(mmCP_RB2_RPTR[0]), 0, 0 }, + { "mmCP_RB1_RPTR", REG_MMIO, 0x01bf, 0, &mmCP_RB1_RPTR[0], sizeof(mmCP_RB1_RPTR)/sizeof(mmCP_RB1_RPTR[0]), 0, 0 }, + { "mmCP_RB0_RPTR", REG_MMIO, 0x01c0, 0, &mmCP_RB0_RPTR[0], sizeof(mmCP_RB0_RPTR)/sizeof(mmCP_RB0_RPTR[0]), 0, 0 }, + { "mmCP_RB_RPTR", REG_MMIO, 0x01c0, 0, &mmCP_RB_RPTR[0], sizeof(mmCP_RB_RPTR)/sizeof(mmCP_RB_RPTR[0]), 0, 0 }, + { "mmCP_RB_WPTR_DELAY", REG_MMIO, 0x01c1, 0, &mmCP_RB_WPTR_DELAY[0], sizeof(mmCP_RB_WPTR_DELAY)/sizeof(mmCP_RB_WPTR_DELAY[0]), 0, 0 }, + { "mmCP_RB_WPTR_POLL_CNTL", REG_MMIO, 0x01c2, 0, &mmCP_RB_WPTR_POLL_CNTL[0], sizeof(mmCP_RB_WPTR_POLL_CNTL)/sizeof(mmCP_RB_WPTR_POLL_CNTL[0]), 0, 0 }, + { "mmCP_ROQ1_THRESHOLDS", REG_MMIO, 0x01d5, 0, &mmCP_ROQ1_THRESHOLDS[0], sizeof(mmCP_ROQ1_THRESHOLDS)/sizeof(mmCP_ROQ1_THRESHOLDS[0]), 0, 0 }, + { "mmCP_ROQ2_THRESHOLDS", REG_MMIO, 0x01d6, 0, &mmCP_ROQ2_THRESHOLDS[0], sizeof(mmCP_ROQ2_THRESHOLDS)/sizeof(mmCP_ROQ2_THRESHOLDS[0]), 0, 0 }, + { "mmCP_STQ_THRESHOLDS", REG_MMIO, 0x01d7, 0, &mmCP_STQ_THRESHOLDS[0], sizeof(mmCP_STQ_THRESHOLDS)/sizeof(mmCP_STQ_THRESHOLDS[0]), 0, 0 }, + { "mmCP_QUEUE_THRESHOLDS", REG_MMIO, 0x01d8, 0, &mmCP_QUEUE_THRESHOLDS[0], sizeof(mmCP_QUEUE_THRESHOLDS)/sizeof(mmCP_QUEUE_THRESHOLDS[0]), 0, 0 }, + { "mmCP_MEQ_THRESHOLDS", REG_MMIO, 0x01d9, 0, &mmCP_MEQ_THRESHOLDS[0], sizeof(mmCP_MEQ_THRESHOLDS)/sizeof(mmCP_MEQ_THRESHOLDS[0]), 0, 0 }, + { "mmCP_ROQ_AVAIL", REG_MMIO, 0x01da, 0, &mmCP_ROQ_AVAIL[0], sizeof(mmCP_ROQ_AVAIL)/sizeof(mmCP_ROQ_AVAIL[0]), 0, 0 }, + { "mmCP_STQ_AVAIL", REG_MMIO, 0x01db, 0, &mmCP_STQ_AVAIL[0], sizeof(mmCP_STQ_AVAIL)/sizeof(mmCP_STQ_AVAIL[0]), 0, 0 }, + { "mmCP_ROQ2_AVAIL", REG_MMIO, 0x01dc, 0, &mmCP_ROQ2_AVAIL[0], sizeof(mmCP_ROQ2_AVAIL)/sizeof(mmCP_ROQ2_AVAIL[0]), 0, 0 }, + { "mmCP_MEQ_AVAIL", REG_MMIO, 0x01dd, 0, &mmCP_MEQ_AVAIL[0], sizeof(mmCP_MEQ_AVAIL)/sizeof(mmCP_MEQ_AVAIL[0]), 0, 0 }, + { "mmCP_CMD_INDEX", REG_MMIO, 0x01de, 0, &mmCP_CMD_INDEX[0], sizeof(mmCP_CMD_INDEX)/sizeof(mmCP_CMD_INDEX[0]), 0, 0 }, + { "mmCP_CMD_DATA", REG_MMIO, 0x01df, 0, &mmCP_CMD_DATA[0], sizeof(mmCP_CMD_DATA)/sizeof(mmCP_CMD_DATA[0]), 0, 0 }, + { "mmCP_ROQ_RB_STAT", REG_MMIO, 0x01e0, 0, &mmCP_ROQ_RB_STAT[0], sizeof(mmCP_ROQ_RB_STAT)/sizeof(mmCP_ROQ_RB_STAT[0]), 0, 0 }, + { "mmCP_ROQ_IB1_STAT", REG_MMIO, 0x01e1, 0, &mmCP_ROQ_IB1_STAT[0], sizeof(mmCP_ROQ_IB1_STAT)/sizeof(mmCP_ROQ_IB1_STAT[0]), 0, 0 }, + { "mmCP_ROQ_IB2_STAT", REG_MMIO, 0x01e2, 0, &mmCP_ROQ_IB2_STAT[0], sizeof(mmCP_ROQ_IB2_STAT)/sizeof(mmCP_ROQ_IB2_STAT[0]), 0, 0 }, + { "mmCP_STQ_STAT", REG_MMIO, 0x01e3, 0, &mmCP_STQ_STAT[0], sizeof(mmCP_STQ_STAT)/sizeof(mmCP_STQ_STAT[0]), 0, 0 }, + { "mmCP_STQ_WR_STAT", REG_MMIO, 0x01e4, 0, &mmCP_STQ_WR_STAT[0], sizeof(mmCP_STQ_WR_STAT)/sizeof(mmCP_STQ_WR_STAT[0]), 0, 0 }, + { "mmCP_MEQ_STAT", REG_MMIO, 0x01e5, 0, &mmCP_MEQ_STAT[0], sizeof(mmCP_MEQ_STAT)/sizeof(mmCP_MEQ_STAT[0]), 0, 0 }, + { "mmCP_CEQ1_AVAIL", REG_MMIO, 0x01e6, 0, &mmCP_CEQ1_AVAIL[0], sizeof(mmCP_CEQ1_AVAIL)/sizeof(mmCP_CEQ1_AVAIL[0]), 0, 0 }, + { "mmCP_CEQ2_AVAIL", REG_MMIO, 0x01e7, 0, &mmCP_CEQ2_AVAIL[0], sizeof(mmCP_CEQ2_AVAIL)/sizeof(mmCP_CEQ2_AVAIL[0]), 0, 0 }, + { "mmCP_CE_ROQ_RB_STAT", REG_MMIO, 0x01e8, 0, &mmCP_CE_ROQ_RB_STAT[0], sizeof(mmCP_CE_ROQ_RB_STAT)/sizeof(mmCP_CE_ROQ_RB_STAT[0]), 0, 0 }, + { "mmCP_CE_ROQ_IB1_STAT", REG_MMIO, 0x01e9, 0, &mmCP_CE_ROQ_IB1_STAT[0], sizeof(mmCP_CE_ROQ_IB1_STAT)/sizeof(mmCP_CE_ROQ_IB1_STAT[0]), 0, 0 }, + { "mmCP_CE_ROQ_IB2_STAT", REG_MMIO, 0x01ea, 0, &mmCP_CE_ROQ_IB2_STAT[0], sizeof(mmCP_CE_ROQ_IB2_STAT)/sizeof(mmCP_CE_ROQ_IB2_STAT[0]), 0, 0 }, + { "mmVGT_VTX_VECT_EJECT_REG", REG_MMIO, 0x022c, 0, &mmVGT_VTX_VECT_EJECT_REG[0], sizeof(mmVGT_VTX_VECT_EJECT_REG)/sizeof(mmVGT_VTX_VECT_EJECT_REG[0]), 0, 0 }, + { "mmVGT_DMA_DATA_FIFO_DEPTH", REG_MMIO, 0x022d, 0, &mmVGT_DMA_DATA_FIFO_DEPTH[0], sizeof(mmVGT_DMA_DATA_FIFO_DEPTH)/sizeof(mmVGT_DMA_DATA_FIFO_DEPTH[0]), 0, 0 }, + { "mmVGT_DMA_REQ_FIFO_DEPTH", REG_MMIO, 0x022e, 0, &mmVGT_DMA_REQ_FIFO_DEPTH[0], sizeof(mmVGT_DMA_REQ_FIFO_DEPTH)/sizeof(mmVGT_DMA_REQ_FIFO_DEPTH[0]), 0, 0 }, + { "mmVGT_DRAW_INIT_FIFO_DEPTH", REG_MMIO, 0x022f, 0, &mmVGT_DRAW_INIT_FIFO_DEPTH[0], sizeof(mmVGT_DRAW_INIT_FIFO_DEPTH)/sizeof(mmVGT_DRAW_INIT_FIFO_DEPTH[0]), 0, 0 }, + { "mmVGT_LAST_COPY_STATE", REG_MMIO, 0x0230, 0, &mmVGT_LAST_COPY_STATE[0], sizeof(mmVGT_LAST_COPY_STATE)/sizeof(mmVGT_LAST_COPY_STATE[0]), 0, 0 }, + { "mmVGT_CACHE_INVALIDATION", REG_MMIO, 0x0231, 0, &mmVGT_CACHE_INVALIDATION[0], sizeof(mmVGT_CACHE_INVALIDATION)/sizeof(mmVGT_CACHE_INVALIDATION[0]), 0, 0 }, + { "mmVGT_STRMOUT_DELAY", REG_MMIO, 0x0233, 0, &mmVGT_STRMOUT_DELAY[0], sizeof(mmVGT_STRMOUT_DELAY)/sizeof(mmVGT_STRMOUT_DELAY[0]), 0, 0 }, + { "mmVGT_FIFO_DEPTHS", REG_MMIO, 0x0234, 0, &mmVGT_FIFO_DEPTHS[0], sizeof(mmVGT_FIFO_DEPTHS)/sizeof(mmVGT_FIFO_DEPTHS[0]), 0, 0 }, + { "mmVGT_GS_VERTEX_REUSE", REG_MMIO, 0x0235, 0, &mmVGT_GS_VERTEX_REUSE[0], sizeof(mmVGT_GS_VERTEX_REUSE)/sizeof(mmVGT_GS_VERTEX_REUSE[0]), 0, 0 }, + { "mmVGT_MC_LAT_CNTL", REG_MMIO, 0x0236, 0, &mmVGT_MC_LAT_CNTL[0], sizeof(mmVGT_MC_LAT_CNTL)/sizeof(mmVGT_MC_LAT_CNTL[0]), 0, 0 }, + { "mmIA_CNTL_STATUS", REG_MMIO, 0x0237, 0, &mmIA_CNTL_STATUS[0], sizeof(mmIA_CNTL_STATUS)/sizeof(mmIA_CNTL_STATUS[0]), 0, 0 }, + { "mmVGT_CNTL_STATUS", REG_MMIO, 0x023c, 0, &mmVGT_CNTL_STATUS[0], sizeof(mmVGT_CNTL_STATUS)/sizeof(mmVGT_CNTL_STATUS[0]), 0, 0 }, + { "mmWD_CNTL_STATUS", REG_MMIO, 0x023f, 0, &mmWD_CNTL_STATUS[0], sizeof(mmWD_CNTL_STATUS)/sizeof(mmWD_CNTL_STATUS[0]), 0, 0 }, + { "mmCC_GC_PRIM_CONFIG", REG_MMIO, 0x0240, 0, &mmCC_GC_PRIM_CONFIG[0], sizeof(mmCC_GC_PRIM_CONFIG)/sizeof(mmCC_GC_PRIM_CONFIG[0]), 0, 0 }, + { "mmGC_USER_PRIM_CONFIG", REG_MMIO, 0x0241, 0, &mmGC_USER_PRIM_CONFIG[0], sizeof(mmGC_USER_PRIM_CONFIG)/sizeof(mmGC_USER_PRIM_CONFIG[0]), 0, 0 }, + { "mmWD_QOS", REG_MMIO, 0x0242, 0, &mmWD_QOS[0], sizeof(mmWD_QOS)/sizeof(mmWD_QOS[0]), 0, 0 }, + { "mmWD_UTCL1_CNTL", REG_MMIO, 0x0243, 0, &mmWD_UTCL1_CNTL[0], sizeof(mmWD_UTCL1_CNTL)/sizeof(mmWD_UTCL1_CNTL[0]), 0, 0 }, + { "mmWD_UTCL1_STATUS", REG_MMIO, 0x0244, 0, &mmWD_UTCL1_STATUS[0], sizeof(mmWD_UTCL1_STATUS)/sizeof(mmWD_UTCL1_STATUS[0]), 0, 0 }, + { "mmIA_UTCL1_CNTL", REG_MMIO, 0x0246, 0, &mmIA_UTCL1_CNTL[0], sizeof(mmIA_UTCL1_CNTL)/sizeof(mmIA_UTCL1_CNTL[0]), 0, 0 }, + { "mmIA_UTCL1_STATUS", REG_MMIO, 0x0247, 0, &mmIA_UTCL1_STATUS[0], sizeof(mmIA_UTCL1_STATUS)/sizeof(mmIA_UTCL1_STATUS[0]), 0, 0 }, + { "mmVGT_SYS_CONFIG", REG_MMIO, 0x0263, 0, &mmVGT_SYS_CONFIG[0], sizeof(mmVGT_SYS_CONFIG)/sizeof(mmVGT_SYS_CONFIG[0]), 0, 0 }, + { "mmVGT_VS_MAX_WAVE_ID", REG_MMIO, 0x0268, 0, &mmVGT_VS_MAX_WAVE_ID[0], sizeof(mmVGT_VS_MAX_WAVE_ID)/sizeof(mmVGT_VS_MAX_WAVE_ID[0]), 0, 0 }, + { "mmVGT_GS_MAX_WAVE_ID", REG_MMIO, 0x0269, 0, &mmVGT_GS_MAX_WAVE_ID[0], sizeof(mmVGT_GS_MAX_WAVE_ID)/sizeof(mmVGT_GS_MAX_WAVE_ID[0]), 0, 0 }, + { "mmGFX_PIPE_CONTROL", REG_MMIO, 0x026d, 0, &mmGFX_PIPE_CONTROL[0], sizeof(mmGFX_PIPE_CONTROL)/sizeof(mmGFX_PIPE_CONTROL[0]), 0, 0 }, + { "mmCC_GC_SHADER_ARRAY_CONFIG", REG_MMIO, 0x026f, 0, &mmCC_GC_SHADER_ARRAY_CONFIG[0], sizeof(mmCC_GC_SHADER_ARRAY_CONFIG)/sizeof(mmCC_GC_SHADER_ARRAY_CONFIG[0]), 0, 0 }, + { "mmGC_USER_SHADER_ARRAY_CONFIG", REG_MMIO, 0x0270, 0, &mmGC_USER_SHADER_ARRAY_CONFIG[0], sizeof(mmGC_USER_SHADER_ARRAY_CONFIG)/sizeof(mmGC_USER_SHADER_ARRAY_CONFIG[0]), 0, 0 }, + { "mmVGT_DMA_PRIMITIVE_TYPE", REG_MMIO, 0x0271, 0, &mmVGT_DMA_PRIMITIVE_TYPE[0], sizeof(mmVGT_DMA_PRIMITIVE_TYPE)/sizeof(mmVGT_DMA_PRIMITIVE_TYPE[0]), 0, 0 }, + { "mmVGT_DMA_CONTROL", REG_MMIO, 0x0272, 0, &mmVGT_DMA_CONTROL[0], sizeof(mmVGT_DMA_CONTROL)/sizeof(mmVGT_DMA_CONTROL[0]), 0, 0 }, + { "mmVGT_DMA_LS_HS_CONFIG", REG_MMIO, 0x0273, 0, &mmVGT_DMA_LS_HS_CONFIG[0], sizeof(mmVGT_DMA_LS_HS_CONFIG)/sizeof(mmVGT_DMA_LS_HS_CONFIG[0]), 0, 0 }, + { "mmWD_BUF_RESOURCE_1", REG_MMIO, 0x0276, 0, &mmWD_BUF_RESOURCE_1[0], sizeof(mmWD_BUF_RESOURCE_1)/sizeof(mmWD_BUF_RESOURCE_1[0]), 0, 0 }, + { "mmWD_BUF_RESOURCE_2", REG_MMIO, 0x0277, 0, &mmWD_BUF_RESOURCE_2[0], sizeof(mmWD_BUF_RESOURCE_2)/sizeof(mmWD_BUF_RESOURCE_2[0]), 0, 0 }, + { "mmPA_CL_CNTL_STATUS", REG_MMIO, 0x0284, 0, &mmPA_CL_CNTL_STATUS[0], sizeof(mmPA_CL_CNTL_STATUS)/sizeof(mmPA_CL_CNTL_STATUS[0]), 0, 0 }, + { "mmPA_CL_ENHANCE", REG_MMIO, 0x0285, 0, &mmPA_CL_ENHANCE[0], sizeof(mmPA_CL_ENHANCE)/sizeof(mmPA_CL_ENHANCE[0]), 0, 0 }, + { "mmPA_SU_CNTL_STATUS", REG_MMIO, 0x0294, 0, &mmPA_SU_CNTL_STATUS[0], sizeof(mmPA_SU_CNTL_STATUS)/sizeof(mmPA_SU_CNTL_STATUS[0]), 0, 0 }, + { "mmPA_SC_FIFO_DEPTH_CNTL", REG_MMIO, 0x0295, 0, &mmPA_SC_FIFO_DEPTH_CNTL[0], sizeof(mmPA_SC_FIFO_DEPTH_CNTL)/sizeof(mmPA_SC_FIFO_DEPTH_CNTL[0]), 0, 0 }, + { "mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK", REG_MMIO, 0x02c0, 0, &mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK[0], sizeof(mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK)/sizeof(mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK[0]), 0, 0 }, + { "mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK", REG_MMIO, 0x02c1, 0, &mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK[0], sizeof(mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK)/sizeof(mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK[0]), 0, 0 }, + { "mmPA_SC_TRAP_SCREEN_HV_LOCK", REG_MMIO, 0x02c2, 0, &mmPA_SC_TRAP_SCREEN_HV_LOCK[0], sizeof(mmPA_SC_TRAP_SCREEN_HV_LOCK)/sizeof(mmPA_SC_TRAP_SCREEN_HV_LOCK[0]), 0, 0 }, + { "mmPA_SC_FORCE_EOV_MAX_CNTS", REG_MMIO, 0x02c9, 0, &mmPA_SC_FORCE_EOV_MAX_CNTS[0], sizeof(mmPA_SC_FORCE_EOV_MAX_CNTS)/sizeof(mmPA_SC_FORCE_EOV_MAX_CNTS[0]), 0, 0 }, + { "mmPA_SC_BINNER_EVENT_CNTL_0", REG_MMIO, 0x02cc, 0, &mmPA_SC_BINNER_EVENT_CNTL_0[0], sizeof(mmPA_SC_BINNER_EVENT_CNTL_0)/sizeof(mmPA_SC_BINNER_EVENT_CNTL_0[0]), 0, 0 }, + { "mmPA_SC_BINNER_EVENT_CNTL_1", REG_MMIO, 0x02cd, 0, &mmPA_SC_BINNER_EVENT_CNTL_1[0], sizeof(mmPA_SC_BINNER_EVENT_CNTL_1)/sizeof(mmPA_SC_BINNER_EVENT_CNTL_1[0]), 0, 0 }, + { "mmPA_SC_BINNER_EVENT_CNTL_2", REG_MMIO, 0x02ce, 0, &mmPA_SC_BINNER_EVENT_CNTL_2[0], sizeof(mmPA_SC_BINNER_EVENT_CNTL_2)/sizeof(mmPA_SC_BINNER_EVENT_CNTL_2[0]), 0, 0 }, + { "mmPA_SC_BINNER_EVENT_CNTL_3", REG_MMIO, 0x02cf, 0, &mmPA_SC_BINNER_EVENT_CNTL_3[0], sizeof(mmPA_SC_BINNER_EVENT_CNTL_3)/sizeof(mmPA_SC_BINNER_EVENT_CNTL_3[0]), 0, 0 }, + { "mmPA_SC_BINNER_TIMEOUT_COUNTER", REG_MMIO, 0x02d0, 0, &mmPA_SC_BINNER_TIMEOUT_COUNTER[0], sizeof(mmPA_SC_BINNER_TIMEOUT_COUNTER)/sizeof(mmPA_SC_BINNER_TIMEOUT_COUNTER[0]), 0, 0 }, + { "mmPA_SC_BINNER_PERF_CNTL_0", REG_MMIO, 0x02d1, 0, &mmPA_SC_BINNER_PERF_CNTL_0[0], sizeof(mmPA_SC_BINNER_PERF_CNTL_0)/sizeof(mmPA_SC_BINNER_PERF_CNTL_0[0]), 0, 0 }, + { "mmPA_SC_BINNER_PERF_CNTL_1", REG_MMIO, 0x02d2, 0, &mmPA_SC_BINNER_PERF_CNTL_1[0], sizeof(mmPA_SC_BINNER_PERF_CNTL_1)/sizeof(mmPA_SC_BINNER_PERF_CNTL_1[0]), 0, 0 }, + { "mmPA_SC_BINNER_PERF_CNTL_2", REG_MMIO, 0x02d3, 0, &mmPA_SC_BINNER_PERF_CNTL_2[0], sizeof(mmPA_SC_BINNER_PERF_CNTL_2)/sizeof(mmPA_SC_BINNER_PERF_CNTL_2[0]), 0, 0 }, + { "mmPA_SC_BINNER_PERF_CNTL_3", REG_MMIO, 0x02d4, 0, &mmPA_SC_BINNER_PERF_CNTL_3[0], sizeof(mmPA_SC_BINNER_PERF_CNTL_3)/sizeof(mmPA_SC_BINNER_PERF_CNTL_3[0]), 0, 0 }, + { "mmPA_SC_FIFO_SIZE", REG_MMIO, 0x02f3, 0, &mmPA_SC_FIFO_SIZE[0], sizeof(mmPA_SC_FIFO_SIZE)/sizeof(mmPA_SC_FIFO_SIZE[0]), 0, 0 }, + { "mmPA_SC_IF_FIFO_SIZE", REG_MMIO, 0x02f5, 0, &mmPA_SC_IF_FIFO_SIZE[0], sizeof(mmPA_SC_IF_FIFO_SIZE)/sizeof(mmPA_SC_IF_FIFO_SIZE[0]), 0, 0 }, + { "mmPA_SC_PKR_WAVE_TABLE_CNTL", REG_MMIO, 0x02f8, 0, &mmPA_SC_PKR_WAVE_TABLE_CNTL[0], sizeof(mmPA_SC_PKR_WAVE_TABLE_CNTL)/sizeof(mmPA_SC_PKR_WAVE_TABLE_CNTL[0]), 0, 0 }, + { "mmPA_UTCL1_CNTL1", REG_MMIO, 0x02f9, 0, &mmPA_UTCL1_CNTL1[0], sizeof(mmPA_UTCL1_CNTL1)/sizeof(mmPA_UTCL1_CNTL1[0]), 0, 0 }, + { "mmPA_UTCL1_CNTL2", REG_MMIO, 0x02fa, 0, &mmPA_UTCL1_CNTL2[0], sizeof(mmPA_UTCL1_CNTL2)/sizeof(mmPA_UTCL1_CNTL2[0]), 0, 0 }, + { "mmPA_SIDEBAND_REQUEST_DELAYS", REG_MMIO, 0x02fb, 0, &mmPA_SIDEBAND_REQUEST_DELAYS[0], sizeof(mmPA_SIDEBAND_REQUEST_DELAYS)/sizeof(mmPA_SIDEBAND_REQUEST_DELAYS[0]), 0, 0 }, + { "mmPA_SC_ENHANCE", REG_MMIO, 0x02fc, 0, &mmPA_SC_ENHANCE[0], sizeof(mmPA_SC_ENHANCE)/sizeof(mmPA_SC_ENHANCE[0]), 0, 0 }, + { "mmPA_SC_ENHANCE_1", REG_MMIO, 0x02fd, 0, &mmPA_SC_ENHANCE_1[0], sizeof(mmPA_SC_ENHANCE_1)/sizeof(mmPA_SC_ENHANCE_1[0]), 0, 0 }, + { "mmPA_SC_DSM_CNTL", REG_MMIO, 0x02fe, 0, &mmPA_SC_DSM_CNTL[0], sizeof(mmPA_SC_DSM_CNTL)/sizeof(mmPA_SC_DSM_CNTL[0]), 0, 0 }, + { "mmPA_SC_TILE_STEERING_CREST_OVERRIDE", REG_MMIO, 0x02ff, 0, &mmPA_SC_TILE_STEERING_CREST_OVERRIDE[0], sizeof(mmPA_SC_TILE_STEERING_CREST_OVERRIDE)/sizeof(mmPA_SC_TILE_STEERING_CREST_OVERRIDE[0]), 0, 0 }, + { "mmSQ_CONFIG", REG_MMIO, 0x0300, 0, &mmSQ_CONFIG[0], sizeof(mmSQ_CONFIG)/sizeof(mmSQ_CONFIG[0]), 0, 0 }, + { "mmSQC_CONFIG", REG_MMIO, 0x0301, 0, &mmSQC_CONFIG[0], sizeof(mmSQC_CONFIG)/sizeof(mmSQC_CONFIG[0]), 0, 0 }, + { "mmLDS_CONFIG", REG_MMIO, 0x0302, 0, &mmLDS_CONFIG[0], sizeof(mmLDS_CONFIG)/sizeof(mmLDS_CONFIG[0]), 0, 0 }, + { "mmSQ_RANDOM_WAVE_PRI", REG_MMIO, 0x0303, 0, &mmSQ_RANDOM_WAVE_PRI[0], sizeof(mmSQ_RANDOM_WAVE_PRI)/sizeof(mmSQ_RANDOM_WAVE_PRI[0]), 0, 0 }, + { "mmSQ_REG_CREDITS", REG_MMIO, 0x0304, 0, &mmSQ_REG_CREDITS[0], sizeof(mmSQ_REG_CREDITS)/sizeof(mmSQ_REG_CREDITS[0]), 0, 0 }, + { "mmSQ_FIFO_SIZES", REG_MMIO, 0x0305, 0, &mmSQ_FIFO_SIZES[0], sizeof(mmSQ_FIFO_SIZES)/sizeof(mmSQ_FIFO_SIZES[0]), 0, 0 }, + { "mmSQ_DSM_CNTL", REG_MMIO, 0x0306, 0, &mmSQ_DSM_CNTL[0], sizeof(mmSQ_DSM_CNTL)/sizeof(mmSQ_DSM_CNTL[0]), 0, 0 }, + { "mmSQ_DSM_CNTL2", REG_MMIO, 0x0307, 0, &mmSQ_DSM_CNTL2[0], sizeof(mmSQ_DSM_CNTL2)/sizeof(mmSQ_DSM_CNTL2[0]), 0, 0 }, + { "mmSQ_RUNTIME_CONFIG", REG_MMIO, 0x0308, 0, &mmSQ_RUNTIME_CONFIG[0], sizeof(mmSQ_RUNTIME_CONFIG)/sizeof(mmSQ_RUNTIME_CONFIG[0]), 0, 0 }, + { "mmSH_MEM_BASES", REG_MMIO, 0x030a, 0, &mmSH_MEM_BASES[0], sizeof(mmSH_MEM_BASES)/sizeof(mmSH_MEM_BASES[0]), 0, 0 }, + { "mmSH_MEM_CONFIG", REG_MMIO, 0x030d, 0, &mmSH_MEM_CONFIG[0], sizeof(mmSH_MEM_CONFIG)/sizeof(mmSH_MEM_CONFIG[0]), 0, 0 }, + { "mmCC_GC_SHADER_RATE_CONFIG", REG_MMIO, 0x0312, 0, &mmCC_GC_SHADER_RATE_CONFIG[0], sizeof(mmCC_GC_SHADER_RATE_CONFIG)/sizeof(mmCC_GC_SHADER_RATE_CONFIG[0]), 0, 0 }, + { "mmGC_USER_SHADER_RATE_CONFIG", REG_MMIO, 0x0313, 0, &mmGC_USER_SHADER_RATE_CONFIG[0], sizeof(mmGC_USER_SHADER_RATE_CONFIG)/sizeof(mmGC_USER_SHADER_RATE_CONFIG[0]), 0, 0 }, + { "mmSQ_INTERRUPT_AUTO_MASK", REG_MMIO, 0x0314, 0, &mmSQ_INTERRUPT_AUTO_MASK[0], sizeof(mmSQ_INTERRUPT_AUTO_MASK)/sizeof(mmSQ_INTERRUPT_AUTO_MASK[0]), 0, 0 }, + { "mmSQ_INTERRUPT_MSG_CTRL", REG_MMIO, 0x0315, 0, &mmSQ_INTERRUPT_MSG_CTRL[0], sizeof(mmSQ_INTERRUPT_MSG_CTRL)/sizeof(mmSQ_INTERRUPT_MSG_CTRL[0]), 0, 0 }, + { "mmSQ_UTCL1_CNTL1", REG_MMIO, 0x0317, 0, &mmSQ_UTCL1_CNTL1[0], sizeof(mmSQ_UTCL1_CNTL1)/sizeof(mmSQ_UTCL1_CNTL1[0]), 0, 0 }, + { "mmSQ_UTCL1_CNTL2", REG_MMIO, 0x0318, 0, &mmSQ_UTCL1_CNTL2[0], sizeof(mmSQ_UTCL1_CNTL2)/sizeof(mmSQ_UTCL1_CNTL2[0]), 0, 0 }, + { "mmSQ_UTCL1_STATUS", REG_MMIO, 0x0319, 0, &mmSQ_UTCL1_STATUS[0], sizeof(mmSQ_UTCL1_STATUS)/sizeof(mmSQ_UTCL1_STATUS[0]), 0, 0 }, + { "mmSQ_SHADER_TBA_LO", REG_MMIO, 0x031c, 0, &mmSQ_SHADER_TBA_LO[0], sizeof(mmSQ_SHADER_TBA_LO)/sizeof(mmSQ_SHADER_TBA_LO[0]), 0, 0 }, + { "mmSQ_SHADER_TBA_HI", REG_MMIO, 0x031d, 0, &mmSQ_SHADER_TBA_HI[0], sizeof(mmSQ_SHADER_TBA_HI)/sizeof(mmSQ_SHADER_TBA_HI[0]), 0, 0 }, + { "mmSQ_SHADER_TMA_LO", REG_MMIO, 0x031e, 0, &mmSQ_SHADER_TMA_LO[0], sizeof(mmSQ_SHADER_TMA_LO)/sizeof(mmSQ_SHADER_TMA_LO[0]), 0, 0 }, + { "mmSQ_SHADER_TMA_HI", REG_MMIO, 0x031f, 0, &mmSQ_SHADER_TMA_HI[0], sizeof(mmSQ_SHADER_TMA_HI)/sizeof(mmSQ_SHADER_TMA_HI[0]), 0, 0 }, + { "mmSQC_DSM_CNTL", REG_MMIO, 0x0320, 0, &mmSQC_DSM_CNTL[0], sizeof(mmSQC_DSM_CNTL)/sizeof(mmSQC_DSM_CNTL[0]), 0, 0 }, + { "mmSQC_DSM_CNTLA", REG_MMIO, 0x0321, 0, &mmSQC_DSM_CNTLA[0], sizeof(mmSQC_DSM_CNTLA)/sizeof(mmSQC_DSM_CNTLA[0]), 0, 0 }, + { "mmSQC_DSM_CNTLB", REG_MMIO, 0x0322, 0, &mmSQC_DSM_CNTLB[0], sizeof(mmSQC_DSM_CNTLB)/sizeof(mmSQC_DSM_CNTLB[0]), 0, 0 }, + { "mmSQC_DSM_CNTL2", REG_MMIO, 0x0325, 0, &mmSQC_DSM_CNTL2[0], sizeof(mmSQC_DSM_CNTL2)/sizeof(mmSQC_DSM_CNTL2[0]), 0, 0 }, + { "mmSQC_DSM_CNTL2A", REG_MMIO, 0x0326, 0, &mmSQC_DSM_CNTL2A[0], sizeof(mmSQC_DSM_CNTL2A)/sizeof(mmSQC_DSM_CNTL2A[0]), 0, 0 }, + { "mmSQC_DSM_CNTL2B", REG_MMIO, 0x0327, 0, &mmSQC_DSM_CNTL2B[0], sizeof(mmSQC_DSM_CNTL2B)/sizeof(mmSQC_DSM_CNTL2B[0]), 0, 0 }, + { "mmSQC_EDC_FUE_CNTL", REG_MMIO, 0x032b, 0, &mmSQC_EDC_FUE_CNTL[0], sizeof(mmSQC_EDC_FUE_CNTL)/sizeof(mmSQC_EDC_FUE_CNTL[0]), 0, 0 }, + { "mmSQC_EDC_CNT2", REG_MMIO, 0x032c, 0, &mmSQC_EDC_CNT2[0], sizeof(mmSQC_EDC_CNT2)/sizeof(mmSQC_EDC_CNT2[0]), 0, 0 }, + { "mmSQC_EDC_CNT3", REG_MMIO, 0x032d, 0, &mmSQC_EDC_CNT3[0], sizeof(mmSQC_EDC_CNT3)/sizeof(mmSQC_EDC_CNT3[0]), 0, 0 }, + { "mmSQ_REG_TIMESTAMP", REG_MMIO, 0x0374, 0, &mmSQ_REG_TIMESTAMP[0], sizeof(mmSQ_REG_TIMESTAMP)/sizeof(mmSQ_REG_TIMESTAMP[0]), 0, 0 }, + { "mmSQ_CMD_TIMESTAMP", REG_MMIO, 0x0375, 0, &mmSQ_CMD_TIMESTAMP[0], sizeof(mmSQ_CMD_TIMESTAMP)/sizeof(mmSQ_CMD_TIMESTAMP[0]), 0, 0 }, + { "mmSQ_IND_INDEX", REG_MMIO, 0x0378, 0, &mmSQ_IND_INDEX[0], sizeof(mmSQ_IND_INDEX)/sizeof(mmSQ_IND_INDEX[0]), 0, 0 }, + { "mmSQ_IND_DATA", REG_MMIO, 0x0379, 0, &mmSQ_IND_DATA[0], sizeof(mmSQ_IND_DATA)/sizeof(mmSQ_IND_DATA[0]), 0, 0 }, + { "mmSQ_CMD", REG_MMIO, 0x037b, 0, &mmSQ_CMD[0], sizeof(mmSQ_CMD)/sizeof(mmSQ_CMD[0]), 0, 0 }, + { "mmSQ_TIME_HI", REG_MMIO, 0x037c, 0, &mmSQ_TIME_HI[0], sizeof(mmSQ_TIME_HI)/sizeof(mmSQ_TIME_HI[0]), 0, 0 }, + { "mmSQ_TIME_LO", REG_MMIO, 0x037d, 0, &mmSQ_TIME_LO[0], sizeof(mmSQ_TIME_LO)/sizeof(mmSQ_TIME_LO[0]), 0, 0 }, + { "mmSQ_DS_0", REG_MMIO, 0x037f, 0, &mmSQ_DS_0[0], sizeof(mmSQ_DS_0)/sizeof(mmSQ_DS_0[0]), 0, 0 }, + { "mmSQ_DS_1", REG_MMIO, 0x037f, 0, &mmSQ_DS_1[0], sizeof(mmSQ_DS_1)/sizeof(mmSQ_DS_1[0]), 0, 0 }, + { "mmSQ_EXP_0", REG_MMIO, 0x037f, 0, &mmSQ_EXP_0[0], sizeof(mmSQ_EXP_0)/sizeof(mmSQ_EXP_0[0]), 0, 0 }, + { "mmSQ_EXP_1", REG_MMIO, 0x037f, 0, &mmSQ_EXP_1[0], sizeof(mmSQ_EXP_1)/sizeof(mmSQ_EXP_1[0]), 0, 0 }, + { "mmSQ_FLAT_0", REG_MMIO, 0x037f, 0, &mmSQ_FLAT_0[0], sizeof(mmSQ_FLAT_0)/sizeof(mmSQ_FLAT_0[0]), 0, 0 }, + { "mmSQ_FLAT_1", REG_MMIO, 0x037f, 0, &mmSQ_FLAT_1[0], sizeof(mmSQ_FLAT_1)/sizeof(mmSQ_FLAT_1[0]), 0, 0 }, + { "mmSQ_GLBL_0", REG_MMIO, 0x037f, 0, &mmSQ_GLBL_0[0], sizeof(mmSQ_GLBL_0)/sizeof(mmSQ_GLBL_0[0]), 0, 0 }, + { "mmSQ_GLBL_1", REG_MMIO, 0x037f, 0, &mmSQ_GLBL_1[0], sizeof(mmSQ_GLBL_1)/sizeof(mmSQ_GLBL_1[0]), 0, 0 }, + { "mmSQ_INST", REG_MMIO, 0x037f, 0, &mmSQ_INST[0], sizeof(mmSQ_INST)/sizeof(mmSQ_INST[0]), 0, 0 }, + { "mmSQ_MIMG_0", REG_MMIO, 0x037f, 0, &mmSQ_MIMG_0[0], sizeof(mmSQ_MIMG_0)/sizeof(mmSQ_MIMG_0[0]), 0, 0 }, + { "mmSQ_MIMG_1", REG_MMIO, 0x037f, 0, &mmSQ_MIMG_1[0], sizeof(mmSQ_MIMG_1)/sizeof(mmSQ_MIMG_1[0]), 0, 0 }, + { "mmSQ_MTBUF_0", REG_MMIO, 0x037f, 0, &mmSQ_MTBUF_0[0], sizeof(mmSQ_MTBUF_0)/sizeof(mmSQ_MTBUF_0[0]), 0, 0 }, + { "mmSQ_MTBUF_1", REG_MMIO, 0x037f, 0, &mmSQ_MTBUF_1[0], sizeof(mmSQ_MTBUF_1)/sizeof(mmSQ_MTBUF_1[0]), 0, 0 }, + { "mmSQ_MUBUF_0", REG_MMIO, 0x037f, 0, &mmSQ_MUBUF_0[0], sizeof(mmSQ_MUBUF_0)/sizeof(mmSQ_MUBUF_0[0]), 0, 0 }, + { "mmSQ_MUBUF_1", REG_MMIO, 0x037f, 0, &mmSQ_MUBUF_1[0], sizeof(mmSQ_MUBUF_1)/sizeof(mmSQ_MUBUF_1[0]), 0, 0 }, + { "mmSQ_SCRATCH_0", REG_MMIO, 0x037f, 0, &mmSQ_SCRATCH_0[0], sizeof(mmSQ_SCRATCH_0)/sizeof(mmSQ_SCRATCH_0[0]), 0, 0 }, + { "mmSQ_SCRATCH_1", REG_MMIO, 0x037f, 0, &mmSQ_SCRATCH_1[0], sizeof(mmSQ_SCRATCH_1)/sizeof(mmSQ_SCRATCH_1[0]), 0, 0 }, + { "mmSQ_SMEM_0", REG_MMIO, 0x037f, 0, &mmSQ_SMEM_0[0], sizeof(mmSQ_SMEM_0)/sizeof(mmSQ_SMEM_0[0]), 0, 0 }, + { "mmSQ_SMEM_1", REG_MMIO, 0x037f, 0, &mmSQ_SMEM_1[0], sizeof(mmSQ_SMEM_1)/sizeof(mmSQ_SMEM_1[0]), 0, 0 }, + { "mmSQ_SOP1", REG_MMIO, 0x037f, 0, &mmSQ_SOP1[0], sizeof(mmSQ_SOP1)/sizeof(mmSQ_SOP1[0]), 0, 0 }, + { "mmSQ_SOP2", REG_MMIO, 0x037f, 0, &mmSQ_SOP2[0], sizeof(mmSQ_SOP2)/sizeof(mmSQ_SOP2[0]), 0, 0 }, + { "mmSQ_SOPC", REG_MMIO, 0x037f, 0, &mmSQ_SOPC[0], sizeof(mmSQ_SOPC)/sizeof(mmSQ_SOPC[0]), 0, 0 }, + { "mmSQ_SOPK", REG_MMIO, 0x037f, 0, &mmSQ_SOPK[0], sizeof(mmSQ_SOPK)/sizeof(mmSQ_SOPK[0]), 0, 0 }, + { "mmSQ_SOPP", REG_MMIO, 0x037f, 0, &mmSQ_SOPP[0], sizeof(mmSQ_SOPP)/sizeof(mmSQ_SOPP[0]), 0, 0 }, + { "mmSQ_VINTRP", REG_MMIO, 0x037f, 0, &mmSQ_VINTRP[0], sizeof(mmSQ_VINTRP)/sizeof(mmSQ_VINTRP[0]), 0, 0 }, + { "mmSQ_VOP1", REG_MMIO, 0x037f, 0, &mmSQ_VOP1[0], sizeof(mmSQ_VOP1)/sizeof(mmSQ_VOP1[0]), 0, 0 }, + { "mmSQ_VOP2", REG_MMIO, 0x037f, 0, &mmSQ_VOP2[0], sizeof(mmSQ_VOP2)/sizeof(mmSQ_VOP2[0]), 0, 0 }, + { "mmSQ_VOP3P_0", REG_MMIO, 0x037f, 0, &mmSQ_VOP3P_0[0], sizeof(mmSQ_VOP3P_0)/sizeof(mmSQ_VOP3P_0[0]), 0, 0 }, + { "mmSQ_VOP3P_1", REG_MMIO, 0x037f, 0, &mmSQ_VOP3P_1[0], sizeof(mmSQ_VOP3P_1)/sizeof(mmSQ_VOP3P_1[0]), 0, 0 }, + { "mmSQ_VOP3_0", REG_MMIO, 0x037f, 0, &mmSQ_VOP3_0[0], sizeof(mmSQ_VOP3_0)/sizeof(mmSQ_VOP3_0[0]), 0, 0 }, + { "mmSQ_VOP3_0_SDST_ENC", REG_MMIO, 0x037f, 0, &mmSQ_VOP3_0_SDST_ENC[0], sizeof(mmSQ_VOP3_0_SDST_ENC)/sizeof(mmSQ_VOP3_0_SDST_ENC[0]), 0, 0 }, + { "mmSQ_VOP3_1", REG_MMIO, 0x037f, 0, &mmSQ_VOP3_1[0], sizeof(mmSQ_VOP3_1)/sizeof(mmSQ_VOP3_1[0]), 0, 0 }, + { "mmSQ_VOPC", REG_MMIO, 0x037f, 0, &mmSQ_VOPC[0], sizeof(mmSQ_VOPC)/sizeof(mmSQ_VOPC[0]), 0, 0 }, + { "mmSQ_VOP_DPP", REG_MMIO, 0x037f, 0, &mmSQ_VOP_DPP[0], sizeof(mmSQ_VOP_DPP)/sizeof(mmSQ_VOP_DPP[0]), 0, 0 }, + { "mmSQ_VOP_SDWA", REG_MMIO, 0x037f, 0, &mmSQ_VOP_SDWA[0], sizeof(mmSQ_VOP_SDWA)/sizeof(mmSQ_VOP_SDWA[0]), 0, 0 }, + { "mmSQ_VOP_SDWA_SDST_ENC", REG_MMIO, 0x037f, 0, &mmSQ_VOP_SDWA_SDST_ENC[0], sizeof(mmSQ_VOP_SDWA_SDST_ENC)/sizeof(mmSQ_VOP_SDWA_SDST_ENC[0]), 0, 0 }, + { "mmSQ_LB_CTR_CTRL", REG_MMIO, 0x0398, 0, &mmSQ_LB_CTR_CTRL[0], sizeof(mmSQ_LB_CTR_CTRL)/sizeof(mmSQ_LB_CTR_CTRL[0]), 0, 0 }, + { "mmSQ_LB_DATA0", REG_MMIO, 0x0399, 0, &mmSQ_LB_DATA0[0], sizeof(mmSQ_LB_DATA0)/sizeof(mmSQ_LB_DATA0[0]), 0, 0 }, + { "mmSQ_LB_DATA1", REG_MMIO, 0x039a, 0, &mmSQ_LB_DATA1[0], sizeof(mmSQ_LB_DATA1)/sizeof(mmSQ_LB_DATA1[0]), 0, 0 }, + { "mmSQ_LB_DATA2", REG_MMIO, 0x039b, 0, &mmSQ_LB_DATA2[0], sizeof(mmSQ_LB_DATA2)/sizeof(mmSQ_LB_DATA2[0]), 0, 0 }, + { "mmSQ_LB_DATA3", REG_MMIO, 0x039c, 0, &mmSQ_LB_DATA3[0], sizeof(mmSQ_LB_DATA3)/sizeof(mmSQ_LB_DATA3[0]), 0, 0 }, + { "mmSQ_LB_CTR_SEL", REG_MMIO, 0x039d, 0, &mmSQ_LB_CTR_SEL[0], sizeof(mmSQ_LB_CTR_SEL)/sizeof(mmSQ_LB_CTR_SEL[0]), 0, 0 }, + { "mmSQ_LB_CTR0_CU", REG_MMIO, 0x039e, 0, &mmSQ_LB_CTR0_CU[0], sizeof(mmSQ_LB_CTR0_CU)/sizeof(mmSQ_LB_CTR0_CU[0]), 0, 0 }, + { "mmSQ_LB_CTR1_CU", REG_MMIO, 0x039f, 0, &mmSQ_LB_CTR1_CU[0], sizeof(mmSQ_LB_CTR1_CU)/sizeof(mmSQ_LB_CTR1_CU[0]), 0, 0 }, + { "mmSQ_LB_CTR2_CU", REG_MMIO, 0x03a0, 0, &mmSQ_LB_CTR2_CU[0], sizeof(mmSQ_LB_CTR2_CU)/sizeof(mmSQ_LB_CTR2_CU[0]), 0, 0 }, + { "mmSQ_LB_CTR3_CU", REG_MMIO, 0x03a1, 0, &mmSQ_LB_CTR3_CU[0], sizeof(mmSQ_LB_CTR3_CU)/sizeof(mmSQ_LB_CTR3_CU[0]), 0, 0 }, + { "mmSQC_EDC_CNT", REG_MMIO, 0x03a2, 0, &mmSQC_EDC_CNT[0], sizeof(mmSQC_EDC_CNT)/sizeof(mmSQC_EDC_CNT[0]), 0, 0 }, + { "mmSQ_EDC_SEC_CNT", REG_MMIO, 0x03a3, 0, &mmSQ_EDC_SEC_CNT[0], sizeof(mmSQ_EDC_SEC_CNT)/sizeof(mmSQ_EDC_SEC_CNT[0]), 0, 0 }, + { "mmSQ_EDC_DED_CNT", REG_MMIO, 0x03a4, 0, &mmSQ_EDC_DED_CNT[0], sizeof(mmSQ_EDC_DED_CNT)/sizeof(mmSQ_EDC_DED_CNT[0]), 0, 0 }, + { "mmSQ_EDC_INFO", REG_MMIO, 0x03a5, 0, &mmSQ_EDC_INFO[0], sizeof(mmSQ_EDC_INFO)/sizeof(mmSQ_EDC_INFO[0]), 0, 0 }, + { "mmSQ_EDC_CNT", REG_MMIO, 0x03a6, 0, &mmSQ_EDC_CNT[0], sizeof(mmSQ_EDC_CNT)/sizeof(mmSQ_EDC_CNT[0]), 0, 0 }, + { "mmSQ_EDC_FUE_CNTL", REG_MMIO, 0x03a7, 0, &mmSQ_EDC_FUE_CNTL[0], sizeof(mmSQ_EDC_FUE_CNTL)/sizeof(mmSQ_EDC_FUE_CNTL[0]), 0, 0 }, + { "mmSQ_THREAD_TRACE_WORD_CMN", REG_MMIO, 0x03b0, 0, &mmSQ_THREAD_TRACE_WORD_CMN[0], sizeof(mmSQ_THREAD_TRACE_WORD_CMN)/sizeof(mmSQ_THREAD_TRACE_WORD_CMN[0]), 0, 0 }, + { "mmSQ_THREAD_TRACE_WORD_EVENT", REG_MMIO, 0x03b0, 0, &mmSQ_THREAD_TRACE_WORD_EVENT[0], sizeof(mmSQ_THREAD_TRACE_WORD_EVENT)/sizeof(mmSQ_THREAD_TRACE_WORD_EVENT[0]), 0, 0 }, + { "mmSQ_THREAD_TRACE_WORD_INST", REG_MMIO, 0x03b0, 0, &mmSQ_THREAD_TRACE_WORD_INST[0], sizeof(mmSQ_THREAD_TRACE_WORD_INST)/sizeof(mmSQ_THREAD_TRACE_WORD_INST[0]), 0, 0 }, + { "mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2", REG_MMIO, 0x03b0, 0, &mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2[0], sizeof(mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2)/sizeof(mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2[0]), 0, 0 }, + { "mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2", REG_MMIO, 0x03b0, 0, &mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2[0], sizeof(mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2)/sizeof(mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2[0]), 0, 0 }, + { "mmSQ_THREAD_TRACE_WORD_ISSUE", REG_MMIO, 0x03b0, 0, &mmSQ_THREAD_TRACE_WORD_ISSUE[0], sizeof(mmSQ_THREAD_TRACE_WORD_ISSUE)/sizeof(mmSQ_THREAD_TRACE_WORD_ISSUE[0]), 0, 0 }, + { "mmSQ_THREAD_TRACE_WORD_MISC", REG_MMIO, 0x03b0, 0, &mmSQ_THREAD_TRACE_WORD_MISC[0], sizeof(mmSQ_THREAD_TRACE_WORD_MISC)/sizeof(mmSQ_THREAD_TRACE_WORD_MISC[0]), 0, 0 }, + { "mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2", REG_MMIO, 0x03b0, 0, &mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2[0], sizeof(mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2)/sizeof(mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2[0]), 0, 0 }, + { "mmSQ_THREAD_TRACE_WORD_REG_1_OF_2", REG_MMIO, 0x03b0, 0, &mmSQ_THREAD_TRACE_WORD_REG_1_OF_2[0], sizeof(mmSQ_THREAD_TRACE_WORD_REG_1_OF_2)/sizeof(mmSQ_THREAD_TRACE_WORD_REG_1_OF_2[0]), 0, 0 }, + { "mmSQ_THREAD_TRACE_WORD_REG_2_OF_2", REG_MMIO, 0x03b0, 0, &mmSQ_THREAD_TRACE_WORD_REG_2_OF_2[0], sizeof(mmSQ_THREAD_TRACE_WORD_REG_2_OF_2)/sizeof(mmSQ_THREAD_TRACE_WORD_REG_2_OF_2[0]), 0, 0 }, + { "mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2", REG_MMIO, 0x03b0, 0, &mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2[0], sizeof(mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2)/sizeof(mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2[0]), 0, 0 }, + { "mmSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2", REG_MMIO, 0x03b0, 0, &mmSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2[0], sizeof(mmSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2)/sizeof(mmSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2[0]), 0, 0 }, + { "mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2", REG_MMIO, 0x03b0, 0, &mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2[0], sizeof(mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2)/sizeof(mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2[0]), 0, 0 }, + { "mmSQ_THREAD_TRACE_WORD_WAVE", REG_MMIO, 0x03b0, 0, &mmSQ_THREAD_TRACE_WORD_WAVE[0], sizeof(mmSQ_THREAD_TRACE_WORD_WAVE)/sizeof(mmSQ_THREAD_TRACE_WORD_WAVE[0]), 0, 0 }, + { "mmSQ_THREAD_TRACE_WORD_WAVE_START", REG_MMIO, 0x03b0, 0, &mmSQ_THREAD_TRACE_WORD_WAVE_START[0], sizeof(mmSQ_THREAD_TRACE_WORD_WAVE_START)/sizeof(mmSQ_THREAD_TRACE_WORD_WAVE_START[0]), 0, 0 }, + { "mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2", REG_MMIO, 0x03b1, 0, &mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2[0], sizeof(mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2)/sizeof(mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2[0]), 0, 0 }, + { "mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2", REG_MMIO, 0x03b1, 0, &mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2[0], sizeof(mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2)/sizeof(mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2[0]), 0, 0 }, + { "mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2", REG_MMIO, 0x03b1, 0, &mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2[0], sizeof(mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2)/sizeof(mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2[0]), 0, 0 }, + { "mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2", REG_MMIO, 0x03b1, 0, &mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2[0], sizeof(mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2)/sizeof(mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2[0]), 0, 0 }, + { "mmSQ_WREXEC_EXEC_HI", REG_MMIO, 0x03b1, 0, &mmSQ_WREXEC_EXEC_HI[0], sizeof(mmSQ_WREXEC_EXEC_HI)/sizeof(mmSQ_WREXEC_EXEC_HI[0]), 0, 0 }, + { "mmSQ_WREXEC_EXEC_LO", REG_MMIO, 0x03b1, 0, &mmSQ_WREXEC_EXEC_LO[0], sizeof(mmSQ_WREXEC_EXEC_LO)/sizeof(mmSQ_WREXEC_EXEC_LO[0]), 0, 0 }, + { "mmSQ_BUF_RSRC_WORD0", REG_MMIO, 0x03c0, 0, &mmSQ_BUF_RSRC_WORD0[0], sizeof(mmSQ_BUF_RSRC_WORD0)/sizeof(mmSQ_BUF_RSRC_WORD0[0]), 0, 0 }, + { "mmSQ_BUF_RSRC_WORD1", REG_MMIO, 0x03c1, 0, &mmSQ_BUF_RSRC_WORD1[0], sizeof(mmSQ_BUF_RSRC_WORD1)/sizeof(mmSQ_BUF_RSRC_WORD1[0]), 0, 0 }, + { "mmSQ_BUF_RSRC_WORD2", REG_MMIO, 0x03c2, 0, &mmSQ_BUF_RSRC_WORD2[0], sizeof(mmSQ_BUF_RSRC_WORD2)/sizeof(mmSQ_BUF_RSRC_WORD2[0]), 0, 0 }, + { "mmSQ_BUF_RSRC_WORD3", REG_MMIO, 0x03c3, 0, &mmSQ_BUF_RSRC_WORD3[0], sizeof(mmSQ_BUF_RSRC_WORD3)/sizeof(mmSQ_BUF_RSRC_WORD3[0]), 0, 0 }, + { "mmSQ_IMG_RSRC_WORD0", REG_MMIO, 0x03c4, 0, &mmSQ_IMG_RSRC_WORD0[0], sizeof(mmSQ_IMG_RSRC_WORD0)/sizeof(mmSQ_IMG_RSRC_WORD0[0]), 0, 0 }, + { "mmSQ_IMG_RSRC_WORD1", REG_MMIO, 0x03c5, 0, &mmSQ_IMG_RSRC_WORD1[0], sizeof(mmSQ_IMG_RSRC_WORD1)/sizeof(mmSQ_IMG_RSRC_WORD1[0]), 0, 0 }, + { "mmSQ_IMG_RSRC_WORD2", REG_MMIO, 0x03c6, 0, &mmSQ_IMG_RSRC_WORD2[0], sizeof(mmSQ_IMG_RSRC_WORD2)/sizeof(mmSQ_IMG_RSRC_WORD2[0]), 0, 0 }, + { "mmSQ_IMG_RSRC_WORD3", REG_MMIO, 0x03c7, 0, &mmSQ_IMG_RSRC_WORD3[0], sizeof(mmSQ_IMG_RSRC_WORD3)/sizeof(mmSQ_IMG_RSRC_WORD3[0]), 0, 0 }, + { "mmSQ_IMG_RSRC_WORD4", REG_MMIO, 0x03c8, 0, &mmSQ_IMG_RSRC_WORD4[0], sizeof(mmSQ_IMG_RSRC_WORD4)/sizeof(mmSQ_IMG_RSRC_WORD4[0]), 0, 0 }, + { "mmSQ_IMG_RSRC_WORD5", REG_MMIO, 0x03c9, 0, &mmSQ_IMG_RSRC_WORD5[0], sizeof(mmSQ_IMG_RSRC_WORD5)/sizeof(mmSQ_IMG_RSRC_WORD5[0]), 0, 0 }, + { "mmSQ_IMG_RSRC_WORD6", REG_MMIO, 0x03ca, 0, &mmSQ_IMG_RSRC_WORD6[0], sizeof(mmSQ_IMG_RSRC_WORD6)/sizeof(mmSQ_IMG_RSRC_WORD6[0]), 0, 0 }, + { "mmSQ_IMG_RSRC_WORD7", REG_MMIO, 0x03cb, 0, &mmSQ_IMG_RSRC_WORD7[0], sizeof(mmSQ_IMG_RSRC_WORD7)/sizeof(mmSQ_IMG_RSRC_WORD7[0]), 0, 0 }, + { "mmSQ_IMG_SAMP_WORD0", REG_MMIO, 0x03cc, 0, &mmSQ_IMG_SAMP_WORD0[0], sizeof(mmSQ_IMG_SAMP_WORD0)/sizeof(mmSQ_IMG_SAMP_WORD0[0]), 0, 0 }, + { "mmSQ_IMG_SAMP_WORD1", REG_MMIO, 0x03cd, 0, &mmSQ_IMG_SAMP_WORD1[0], sizeof(mmSQ_IMG_SAMP_WORD1)/sizeof(mmSQ_IMG_SAMP_WORD1[0]), 0, 0 }, + { "mmSQ_IMG_SAMP_WORD2", REG_MMIO, 0x03ce, 0, &mmSQ_IMG_SAMP_WORD2[0], sizeof(mmSQ_IMG_SAMP_WORD2)/sizeof(mmSQ_IMG_SAMP_WORD2[0]), 0, 0 }, + { "mmSQ_IMG_SAMP_WORD3", REG_MMIO, 0x03cf, 0, &mmSQ_IMG_SAMP_WORD3[0], sizeof(mmSQ_IMG_SAMP_WORD3)/sizeof(mmSQ_IMG_SAMP_WORD3[0]), 0, 0 }, + { "mmSQ_FLAT_SCRATCH_WORD0", REG_MMIO, 0x03d0, 0, &mmSQ_FLAT_SCRATCH_WORD0[0], sizeof(mmSQ_FLAT_SCRATCH_WORD0)/sizeof(mmSQ_FLAT_SCRATCH_WORD0[0]), 0, 0 }, + { "mmSQ_FLAT_SCRATCH_WORD1", REG_MMIO, 0x03d1, 0, &mmSQ_FLAT_SCRATCH_WORD1[0], sizeof(mmSQ_FLAT_SCRATCH_WORD1)/sizeof(mmSQ_FLAT_SCRATCH_WORD1[0]), 0, 0 }, + { "mmSQ_M0_GPR_IDX_WORD", REG_MMIO, 0x03d2, 0, &mmSQ_M0_GPR_IDX_WORD[0], sizeof(mmSQ_M0_GPR_IDX_WORD)/sizeof(mmSQ_M0_GPR_IDX_WORD[0]), 0, 0 }, + { "mmSQC_ICACHE_UTCL1_CNTL1", REG_MMIO, 0x03d3, 0, &mmSQC_ICACHE_UTCL1_CNTL1[0], sizeof(mmSQC_ICACHE_UTCL1_CNTL1)/sizeof(mmSQC_ICACHE_UTCL1_CNTL1[0]), 0, 0 }, + { "mmSQC_ICACHE_UTCL1_CNTL2", REG_MMIO, 0x03d4, 0, &mmSQC_ICACHE_UTCL1_CNTL2[0], sizeof(mmSQC_ICACHE_UTCL1_CNTL2)/sizeof(mmSQC_ICACHE_UTCL1_CNTL2[0]), 0, 0 }, + { "mmSQC_DCACHE_UTCL1_CNTL1", REG_MMIO, 0x03d5, 0, &mmSQC_DCACHE_UTCL1_CNTL1[0], sizeof(mmSQC_DCACHE_UTCL1_CNTL1)/sizeof(mmSQC_DCACHE_UTCL1_CNTL1[0]), 0, 0 }, + { "mmSQC_DCACHE_UTCL1_CNTL2", REG_MMIO, 0x03d6, 0, &mmSQC_DCACHE_UTCL1_CNTL2[0], sizeof(mmSQC_DCACHE_UTCL1_CNTL2)/sizeof(mmSQC_DCACHE_UTCL1_CNTL2[0]), 0, 0 }, + { "mmSQC_ICACHE_UTCL1_STATUS", REG_MMIO, 0x03d7, 0, &mmSQC_ICACHE_UTCL1_STATUS[0], sizeof(mmSQC_ICACHE_UTCL1_STATUS)/sizeof(mmSQC_ICACHE_UTCL1_STATUS[0]), 0, 0 }, + { "mmSQC_DCACHE_UTCL1_STATUS", REG_MMIO, 0x03d8, 0, &mmSQC_DCACHE_UTCL1_STATUS[0], sizeof(mmSQC_DCACHE_UTCL1_STATUS)/sizeof(mmSQC_DCACHE_UTCL1_STATUS[0]), 0, 0 }, + { "mmSX_DEBUG_1", REG_MMIO, 0x0419, 0, &mmSX_DEBUG_1[0], sizeof(mmSX_DEBUG_1)/sizeof(mmSX_DEBUG_1[0]), 0, 0 }, + { "mmSPI_PS_MAX_WAVE_ID", REG_MMIO, 0x043a, 0, &mmSPI_PS_MAX_WAVE_ID[0], sizeof(mmSPI_PS_MAX_WAVE_ID)/sizeof(mmSPI_PS_MAX_WAVE_ID[0]), 0, 0 }, + { "mmSPI_START_PHASE", REG_MMIO, 0x043b, 0, &mmSPI_START_PHASE[0], sizeof(mmSPI_START_PHASE)/sizeof(mmSPI_START_PHASE[0]), 0, 0 }, + { "mmSPI_GFX_CNTL", REG_MMIO, 0x043c, 0, &mmSPI_GFX_CNTL[0], sizeof(mmSPI_GFX_CNTL)/sizeof(mmSPI_GFX_CNTL[0]), 0, 0 }, + { "mmSPI_DSM_CNTL", REG_MMIO, 0x0443, 0, &mmSPI_DSM_CNTL[0], sizeof(mmSPI_DSM_CNTL)/sizeof(mmSPI_DSM_CNTL[0]), 0, 0 }, + { "mmSPI_DSM_CNTL2", REG_MMIO, 0x0444, 0, &mmSPI_DSM_CNTL2[0], sizeof(mmSPI_DSM_CNTL2)/sizeof(mmSPI_DSM_CNTL2[0]), 0, 0 }, + { "mmSPI_EDC_CNT", REG_MMIO, 0x0445, 0, &mmSPI_EDC_CNT[0], sizeof(mmSPI_EDC_CNT)/sizeof(mmSPI_EDC_CNT[0]), 0, 0 }, + { "mmSPI_CONFIG_PS_CU_EN", REG_MMIO, 0x0452, 0, &mmSPI_CONFIG_PS_CU_EN[0], sizeof(mmSPI_CONFIG_PS_CU_EN)/sizeof(mmSPI_CONFIG_PS_CU_EN[0]), 0, 0 }, + { "mmSPI_WF_LIFETIME_CNTL", REG_MMIO, 0x04aa, 0, &mmSPI_WF_LIFETIME_CNTL[0], sizeof(mmSPI_WF_LIFETIME_CNTL)/sizeof(mmSPI_WF_LIFETIME_CNTL[0]), 0, 0 }, + { "mmSPI_WF_LIFETIME_LIMIT_0", REG_MMIO, 0x04ab, 0, &mmSPI_WF_LIFETIME_LIMIT_0[0], sizeof(mmSPI_WF_LIFETIME_LIMIT_0)/sizeof(mmSPI_WF_LIFETIME_LIMIT_0[0]), 0, 0 }, + { "mmSPI_WF_LIFETIME_LIMIT_1", REG_MMIO, 0x04ac, 0, &mmSPI_WF_LIFETIME_LIMIT_1[0], sizeof(mmSPI_WF_LIFETIME_LIMIT_1)/sizeof(mmSPI_WF_LIFETIME_LIMIT_1[0]), 0, 0 }, + { "mmSPI_WF_LIFETIME_LIMIT_2", REG_MMIO, 0x04ad, 0, &mmSPI_WF_LIFETIME_LIMIT_2[0], sizeof(mmSPI_WF_LIFETIME_LIMIT_2)/sizeof(mmSPI_WF_LIFETIME_LIMIT_2[0]), 0, 0 }, + { "mmSPI_WF_LIFETIME_LIMIT_3", REG_MMIO, 0x04ae, 0, &mmSPI_WF_LIFETIME_LIMIT_3[0], sizeof(mmSPI_WF_LIFETIME_LIMIT_3)/sizeof(mmSPI_WF_LIFETIME_LIMIT_3[0]), 0, 0 }, + { "mmSPI_WF_LIFETIME_LIMIT_4", REG_MMIO, 0x04af, 0, &mmSPI_WF_LIFETIME_LIMIT_4[0], sizeof(mmSPI_WF_LIFETIME_LIMIT_4)/sizeof(mmSPI_WF_LIFETIME_LIMIT_4[0]), 0, 0 }, + { "mmSPI_WF_LIFETIME_LIMIT_5", REG_MMIO, 0x04b0, 0, &mmSPI_WF_LIFETIME_LIMIT_5[0], sizeof(mmSPI_WF_LIFETIME_LIMIT_5)/sizeof(mmSPI_WF_LIFETIME_LIMIT_5[0]), 0, 0 }, + { "mmSPI_WF_LIFETIME_LIMIT_6", REG_MMIO, 0x04b1, 0, &mmSPI_WF_LIFETIME_LIMIT_6[0], sizeof(mmSPI_WF_LIFETIME_LIMIT_6)/sizeof(mmSPI_WF_LIFETIME_LIMIT_6[0]), 0, 0 }, + { "mmSPI_WF_LIFETIME_LIMIT_7", REG_MMIO, 0x04b2, 0, &mmSPI_WF_LIFETIME_LIMIT_7[0], sizeof(mmSPI_WF_LIFETIME_LIMIT_7)/sizeof(mmSPI_WF_LIFETIME_LIMIT_7[0]), 0, 0 }, + { "mmSPI_WF_LIFETIME_LIMIT_8", REG_MMIO, 0x04b3, 0, &mmSPI_WF_LIFETIME_LIMIT_8[0], sizeof(mmSPI_WF_LIFETIME_LIMIT_8)/sizeof(mmSPI_WF_LIFETIME_LIMIT_8[0]), 0, 0 }, + { "mmSPI_WF_LIFETIME_LIMIT_9", REG_MMIO, 0x04b4, 0, &mmSPI_WF_LIFETIME_LIMIT_9[0], sizeof(mmSPI_WF_LIFETIME_LIMIT_9)/sizeof(mmSPI_WF_LIFETIME_LIMIT_9[0]), 0, 0 }, + { "mmSPI_WF_LIFETIME_STATUS_0", REG_MMIO, 0x04b5, 0, &mmSPI_WF_LIFETIME_STATUS_0[0], sizeof(mmSPI_WF_LIFETIME_STATUS_0)/sizeof(mmSPI_WF_LIFETIME_STATUS_0[0]), 0, 0 }, + { "mmSPI_WF_LIFETIME_STATUS_1", REG_MMIO, 0x04b6, 0, &mmSPI_WF_LIFETIME_STATUS_1[0], sizeof(mmSPI_WF_LIFETIME_STATUS_1)/sizeof(mmSPI_WF_LIFETIME_STATUS_1[0]), 0, 0 }, + { "mmSPI_WF_LIFETIME_STATUS_2", REG_MMIO, 0x04b7, 0, &mmSPI_WF_LIFETIME_STATUS_2[0], sizeof(mmSPI_WF_LIFETIME_STATUS_2)/sizeof(mmSPI_WF_LIFETIME_STATUS_2[0]), 0, 0 }, + { "mmSPI_WF_LIFETIME_STATUS_3", REG_MMIO, 0x04b8, 0, &mmSPI_WF_LIFETIME_STATUS_3[0], sizeof(mmSPI_WF_LIFETIME_STATUS_3)/sizeof(mmSPI_WF_LIFETIME_STATUS_3[0]), 0, 0 }, + { "mmSPI_WF_LIFETIME_STATUS_4", REG_MMIO, 0x04b9, 0, &mmSPI_WF_LIFETIME_STATUS_4[0], sizeof(mmSPI_WF_LIFETIME_STATUS_4)/sizeof(mmSPI_WF_LIFETIME_STATUS_4[0]), 0, 0 }, + { "mmSPI_WF_LIFETIME_STATUS_5", REG_MMIO, 0x04ba, 0, &mmSPI_WF_LIFETIME_STATUS_5[0], sizeof(mmSPI_WF_LIFETIME_STATUS_5)/sizeof(mmSPI_WF_LIFETIME_STATUS_5[0]), 0, 0 }, + { "mmSPI_WF_LIFETIME_STATUS_6", REG_MMIO, 0x04bb, 0, &mmSPI_WF_LIFETIME_STATUS_6[0], sizeof(mmSPI_WF_LIFETIME_STATUS_6)/sizeof(mmSPI_WF_LIFETIME_STATUS_6[0]), 0, 0 }, + { "mmSPI_WF_LIFETIME_STATUS_7", REG_MMIO, 0x04bc, 0, &mmSPI_WF_LIFETIME_STATUS_7[0], sizeof(mmSPI_WF_LIFETIME_STATUS_7)/sizeof(mmSPI_WF_LIFETIME_STATUS_7[0]), 0, 0 }, + { "mmSPI_WF_LIFETIME_STATUS_8", REG_MMIO, 0x04bd, 0, &mmSPI_WF_LIFETIME_STATUS_8[0], sizeof(mmSPI_WF_LIFETIME_STATUS_8)/sizeof(mmSPI_WF_LIFETIME_STATUS_8[0]), 0, 0 }, + { "mmSPI_WF_LIFETIME_STATUS_9", REG_MMIO, 0x04be, 0, &mmSPI_WF_LIFETIME_STATUS_9[0], sizeof(mmSPI_WF_LIFETIME_STATUS_9)/sizeof(mmSPI_WF_LIFETIME_STATUS_9[0]), 0, 0 }, + { "mmSPI_WF_LIFETIME_STATUS_10", REG_MMIO, 0x04bf, 0, &mmSPI_WF_LIFETIME_STATUS_10[0], sizeof(mmSPI_WF_LIFETIME_STATUS_10)/sizeof(mmSPI_WF_LIFETIME_STATUS_10[0]), 0, 0 }, + { "mmSPI_WF_LIFETIME_STATUS_11", REG_MMIO, 0x04c0, 0, &mmSPI_WF_LIFETIME_STATUS_11[0], sizeof(mmSPI_WF_LIFETIME_STATUS_11)/sizeof(mmSPI_WF_LIFETIME_STATUS_11[0]), 0, 0 }, + { "mmSPI_WF_LIFETIME_STATUS_12", REG_MMIO, 0x04c1, 0, &mmSPI_WF_LIFETIME_STATUS_12[0], sizeof(mmSPI_WF_LIFETIME_STATUS_12)/sizeof(mmSPI_WF_LIFETIME_STATUS_12[0]), 0, 0 }, + { "mmSPI_WF_LIFETIME_STATUS_13", REG_MMIO, 0x04c2, 0, &mmSPI_WF_LIFETIME_STATUS_13[0], sizeof(mmSPI_WF_LIFETIME_STATUS_13)/sizeof(mmSPI_WF_LIFETIME_STATUS_13[0]), 0, 0 }, + { "mmSPI_WF_LIFETIME_STATUS_14", REG_MMIO, 0x04c3, 0, &mmSPI_WF_LIFETIME_STATUS_14[0], sizeof(mmSPI_WF_LIFETIME_STATUS_14)/sizeof(mmSPI_WF_LIFETIME_STATUS_14[0]), 0, 0 }, + { "mmSPI_WF_LIFETIME_STATUS_15", REG_MMIO, 0x04c4, 0, &mmSPI_WF_LIFETIME_STATUS_15[0], sizeof(mmSPI_WF_LIFETIME_STATUS_15)/sizeof(mmSPI_WF_LIFETIME_STATUS_15[0]), 0, 0 }, + { "mmSPI_WF_LIFETIME_STATUS_16", REG_MMIO, 0x04c5, 0, &mmSPI_WF_LIFETIME_STATUS_16[0], sizeof(mmSPI_WF_LIFETIME_STATUS_16)/sizeof(mmSPI_WF_LIFETIME_STATUS_16[0]), 0, 0 }, + { "mmSPI_WF_LIFETIME_STATUS_17", REG_MMIO, 0x04c6, 0, &mmSPI_WF_LIFETIME_STATUS_17[0], sizeof(mmSPI_WF_LIFETIME_STATUS_17)/sizeof(mmSPI_WF_LIFETIME_STATUS_17[0]), 0, 0 }, + { "mmSPI_WF_LIFETIME_STATUS_18", REG_MMIO, 0x04c7, 0, &mmSPI_WF_LIFETIME_STATUS_18[0], sizeof(mmSPI_WF_LIFETIME_STATUS_18)/sizeof(mmSPI_WF_LIFETIME_STATUS_18[0]), 0, 0 }, + { "mmSPI_WF_LIFETIME_STATUS_19", REG_MMIO, 0x04c8, 0, &mmSPI_WF_LIFETIME_STATUS_19[0], sizeof(mmSPI_WF_LIFETIME_STATUS_19)/sizeof(mmSPI_WF_LIFETIME_STATUS_19[0]), 0, 0 }, + { "mmSPI_WF_LIFETIME_STATUS_20", REG_MMIO, 0x04c9, 0, &mmSPI_WF_LIFETIME_STATUS_20[0], sizeof(mmSPI_WF_LIFETIME_STATUS_20)/sizeof(mmSPI_WF_LIFETIME_STATUS_20[0]), 0, 0 }, + { "mmSPI_LB_CTR_CTRL", REG_MMIO, 0x04d4, 0, &mmSPI_LB_CTR_CTRL[0], sizeof(mmSPI_LB_CTR_CTRL)/sizeof(mmSPI_LB_CTR_CTRL[0]), 0, 0 }, + { "mmSPI_LB_CU_MASK", REG_MMIO, 0x04d5, 0, &mmSPI_LB_CU_MASK[0], sizeof(mmSPI_LB_CU_MASK)/sizeof(mmSPI_LB_CU_MASK[0]), 0, 0 }, + { "mmSPI_LB_DATA_REG", REG_MMIO, 0x04d6, 0, &mmSPI_LB_DATA_REG[0], sizeof(mmSPI_LB_DATA_REG)/sizeof(mmSPI_LB_DATA_REG[0]), 0, 0 }, + { "mmSPI_PG_ENABLE_STATIC_CU_MASK", REG_MMIO, 0x04d7, 0, &mmSPI_PG_ENABLE_STATIC_CU_MASK[0], sizeof(mmSPI_PG_ENABLE_STATIC_CU_MASK)/sizeof(mmSPI_PG_ENABLE_STATIC_CU_MASK[0]), 0, 0 }, + { "mmSPI_GDS_CREDITS", REG_MMIO, 0x04d8, 0, &mmSPI_GDS_CREDITS[0], sizeof(mmSPI_GDS_CREDITS)/sizeof(mmSPI_GDS_CREDITS[0]), 0, 0 }, + { "mmSPI_SX_EXPORT_BUFFER_SIZES", REG_MMIO, 0x04d9, 0, &mmSPI_SX_EXPORT_BUFFER_SIZES[0], sizeof(mmSPI_SX_EXPORT_BUFFER_SIZES)/sizeof(mmSPI_SX_EXPORT_BUFFER_SIZES[0]), 0, 0 }, + { "mmSPI_SX_SCOREBOARD_BUFFER_SIZES", REG_MMIO, 0x04da, 0, &mmSPI_SX_SCOREBOARD_BUFFER_SIZES[0], sizeof(mmSPI_SX_SCOREBOARD_BUFFER_SIZES)/sizeof(mmSPI_SX_SCOREBOARD_BUFFER_SIZES[0]), 0, 0 }, + { "mmSPI_CSQ_WF_ACTIVE_STATUS", REG_MMIO, 0x04db, 0, &mmSPI_CSQ_WF_ACTIVE_STATUS[0], sizeof(mmSPI_CSQ_WF_ACTIVE_STATUS)/sizeof(mmSPI_CSQ_WF_ACTIVE_STATUS[0]), 0, 0 }, + { "mmSPI_CSQ_WF_ACTIVE_COUNT_0", REG_MMIO, 0x04dc, 0, &mmSPI_CSQ_WF_ACTIVE_COUNT_0[0], sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_0)/sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_0[0]), 0, 0 }, + { "mmSPI_CSQ_WF_ACTIVE_COUNT_1", REG_MMIO, 0x04dd, 0, &mmSPI_CSQ_WF_ACTIVE_COUNT_1[0], sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_1)/sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_1[0]), 0, 0 }, + { "mmSPI_CSQ_WF_ACTIVE_COUNT_2", REG_MMIO, 0x04de, 0, &mmSPI_CSQ_WF_ACTIVE_COUNT_2[0], sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_2)/sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_2[0]), 0, 0 }, + { "mmSPI_CSQ_WF_ACTIVE_COUNT_3", REG_MMIO, 0x04df, 0, &mmSPI_CSQ_WF_ACTIVE_COUNT_3[0], sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_3)/sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_3[0]), 0, 0 }, + { "mmSPI_CSQ_WF_ACTIVE_COUNT_4", REG_MMIO, 0x04e0, 0, &mmSPI_CSQ_WF_ACTIVE_COUNT_4[0], sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_4)/sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_4[0]), 0, 0 }, + { "mmSPI_CSQ_WF_ACTIVE_COUNT_5", REG_MMIO, 0x04e1, 0, &mmSPI_CSQ_WF_ACTIVE_COUNT_5[0], sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_5)/sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_5[0]), 0, 0 }, + { "mmSPI_CSQ_WF_ACTIVE_COUNT_6", REG_MMIO, 0x04e2, 0, &mmSPI_CSQ_WF_ACTIVE_COUNT_6[0], sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_6)/sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_6[0]), 0, 0 }, + { "mmSPI_CSQ_WF_ACTIVE_COUNT_7", REG_MMIO, 0x04e3, 0, &mmSPI_CSQ_WF_ACTIVE_COUNT_7[0], sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_7)/sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_7[0]), 0, 0 }, + { "mmSPI_LB_DATA_WAVES", REG_MMIO, 0x04e4, 0, &mmSPI_LB_DATA_WAVES[0], sizeof(mmSPI_LB_DATA_WAVES)/sizeof(mmSPI_LB_DATA_WAVES[0]), 0, 0 }, + { "mmSPI_LB_DATA_PERCU_WAVE_HSGS", REG_MMIO, 0x04e5, 0, &mmSPI_LB_DATA_PERCU_WAVE_HSGS[0], sizeof(mmSPI_LB_DATA_PERCU_WAVE_HSGS)/sizeof(mmSPI_LB_DATA_PERCU_WAVE_HSGS[0]), 0, 0 }, + { "mmSPI_LB_DATA_PERCU_WAVE_VSPS", REG_MMIO, 0x04e6, 0, &mmSPI_LB_DATA_PERCU_WAVE_VSPS[0], sizeof(mmSPI_LB_DATA_PERCU_WAVE_VSPS)/sizeof(mmSPI_LB_DATA_PERCU_WAVE_VSPS[0]), 0, 0 }, + { "mmSPI_LB_DATA_PERCU_WAVE_CS", REG_MMIO, 0x04e7, 0, &mmSPI_LB_DATA_PERCU_WAVE_CS[0], sizeof(mmSPI_LB_DATA_PERCU_WAVE_CS)/sizeof(mmSPI_LB_DATA_PERCU_WAVE_CS[0]), 0, 0 }, + { "mmSPI_P0_TRAP_SCREEN_PSBA_LO", REG_MMIO, 0x04ec, 0, &mmSPI_P0_TRAP_SCREEN_PSBA_LO[0], sizeof(mmSPI_P0_TRAP_SCREEN_PSBA_LO)/sizeof(mmSPI_P0_TRAP_SCREEN_PSBA_LO[0]), 0, 0 }, + { "mmSPI_P0_TRAP_SCREEN_PSBA_HI", REG_MMIO, 0x04ed, 0, &mmSPI_P0_TRAP_SCREEN_PSBA_HI[0], sizeof(mmSPI_P0_TRAP_SCREEN_PSBA_HI)/sizeof(mmSPI_P0_TRAP_SCREEN_PSBA_HI[0]), 0, 0 }, + { "mmSPI_P0_TRAP_SCREEN_PSMA_LO", REG_MMIO, 0x04ee, 0, &mmSPI_P0_TRAP_SCREEN_PSMA_LO[0], sizeof(mmSPI_P0_TRAP_SCREEN_PSMA_LO)/sizeof(mmSPI_P0_TRAP_SCREEN_PSMA_LO[0]), 0, 0 }, + { "mmSPI_P0_TRAP_SCREEN_PSMA_HI", REG_MMIO, 0x04ef, 0, &mmSPI_P0_TRAP_SCREEN_PSMA_HI[0], sizeof(mmSPI_P0_TRAP_SCREEN_PSMA_HI)/sizeof(mmSPI_P0_TRAP_SCREEN_PSMA_HI[0]), 0, 0 }, + { "mmSPI_P0_TRAP_SCREEN_GPR_MIN", REG_MMIO, 0x04f0, 0, &mmSPI_P0_TRAP_SCREEN_GPR_MIN[0], sizeof(mmSPI_P0_TRAP_SCREEN_GPR_MIN)/sizeof(mmSPI_P0_TRAP_SCREEN_GPR_MIN[0]), 0, 0 }, + { "mmSPI_P1_TRAP_SCREEN_PSBA_LO", REG_MMIO, 0x04f1, 0, &mmSPI_P1_TRAP_SCREEN_PSBA_LO[0], sizeof(mmSPI_P1_TRAP_SCREEN_PSBA_LO)/sizeof(mmSPI_P1_TRAP_SCREEN_PSBA_LO[0]), 0, 0 }, + { "mmSPI_P1_TRAP_SCREEN_PSBA_HI", REG_MMIO, 0x04f2, 0, &mmSPI_P1_TRAP_SCREEN_PSBA_HI[0], sizeof(mmSPI_P1_TRAP_SCREEN_PSBA_HI)/sizeof(mmSPI_P1_TRAP_SCREEN_PSBA_HI[0]), 0, 0 }, + { "mmSPI_P1_TRAP_SCREEN_PSMA_LO", REG_MMIO, 0x04f3, 0, &mmSPI_P1_TRAP_SCREEN_PSMA_LO[0], sizeof(mmSPI_P1_TRAP_SCREEN_PSMA_LO)/sizeof(mmSPI_P1_TRAP_SCREEN_PSMA_LO[0]), 0, 0 }, + { "mmSPI_P1_TRAP_SCREEN_PSMA_HI", REG_MMIO, 0x04f4, 0, &mmSPI_P1_TRAP_SCREEN_PSMA_HI[0], sizeof(mmSPI_P1_TRAP_SCREEN_PSMA_HI)/sizeof(mmSPI_P1_TRAP_SCREEN_PSMA_HI[0]), 0, 0 }, + { "mmSPI_P1_TRAP_SCREEN_GPR_MIN", REG_MMIO, 0x04f5, 0, &mmSPI_P1_TRAP_SCREEN_GPR_MIN[0], sizeof(mmSPI_P1_TRAP_SCREEN_GPR_MIN)/sizeof(mmSPI_P1_TRAP_SCREEN_GPR_MIN[0]), 0, 0 }, + { "mmTD_CNTL", REG_MMIO, 0x0525, 0, &mmTD_CNTL[0], sizeof(mmTD_CNTL)/sizeof(mmTD_CNTL[0]), 0, 0 }, + { "mmTD_STATUS", REG_MMIO, 0x0526, 0, &mmTD_STATUS[0], sizeof(mmTD_STATUS)/sizeof(mmTD_STATUS[0]), 0, 0 }, + { "mmTD_DSM_CNTL", REG_MMIO, 0x052f, 0, &mmTD_DSM_CNTL[0], sizeof(mmTD_DSM_CNTL)/sizeof(mmTD_DSM_CNTL[0]), 0, 0 }, + { "mmTD_DSM_CNTL2", REG_MMIO, 0x0530, 0, &mmTD_DSM_CNTL2[0], sizeof(mmTD_DSM_CNTL2)/sizeof(mmTD_DSM_CNTL2[0]), 0, 0 }, + { "mmTD_SCRATCH", REG_MMIO, 0x0533, 0, &mmTD_SCRATCH[0], sizeof(mmTD_SCRATCH)/sizeof(mmTD_SCRATCH[0]), 0, 0 }, + { "mmTA_CNTL", REG_MMIO, 0x0541, 0, &mmTA_CNTL[0], sizeof(mmTA_CNTL)/sizeof(mmTA_CNTL[0]), 0, 0 }, + { "mmTA_CNTL_AUX", REG_MMIO, 0x0542, 0, &mmTA_CNTL_AUX[0], sizeof(mmTA_CNTL_AUX)/sizeof(mmTA_CNTL_AUX[0]), 0, 0 }, + { "mmTA_RESERVED_010C", REG_MMIO, 0x0543, 0, &mmTA_RESERVED_010C[0], sizeof(mmTA_RESERVED_010C)/sizeof(mmTA_RESERVED_010C[0]), 0, 0 }, + { "mmTA_GRAD_ADJ", REG_MMIO, 0x0544, 0, &mmTA_GRAD_ADJ[0], sizeof(mmTA_GRAD_ADJ)/sizeof(mmTA_GRAD_ADJ[0]), 0, 0 }, + { "mmTA_STATUS", REG_MMIO, 0x0548, 0, &mmTA_STATUS[0], sizeof(mmTA_STATUS)/sizeof(mmTA_STATUS[0]), 0, 0 }, + { "mmTA_SCRATCH", REG_MMIO, 0x0564, 0, &mmTA_SCRATCH[0], sizeof(mmTA_SCRATCH)/sizeof(mmTA_SCRATCH[0]), 0, 0 }, + { "mmGDS_CONFIG", REG_MMIO, 0x05c0, 0, &mmGDS_CONFIG[0], sizeof(mmGDS_CONFIG)/sizeof(mmGDS_CONFIG[0]), 0, 0 }, + { "mmGDS_CNTL_STATUS", REG_MMIO, 0x05c1, 0, &mmGDS_CNTL_STATUS[0], sizeof(mmGDS_CNTL_STATUS)/sizeof(mmGDS_CNTL_STATUS[0]), 0, 0 }, + { "mmGDS_ENHANCE2", REG_MMIO, 0x05c2, 0, &mmGDS_ENHANCE2[0], sizeof(mmGDS_ENHANCE2)/sizeof(mmGDS_ENHANCE2[0]), 0, 0 }, + { "mmGDS_PROTECTION_FAULT", REG_MMIO, 0x05c3, 0, &mmGDS_PROTECTION_FAULT[0], sizeof(mmGDS_PROTECTION_FAULT)/sizeof(mmGDS_PROTECTION_FAULT[0]), 0, 0 }, + { "mmGDS_VM_PROTECTION_FAULT", REG_MMIO, 0x05c4, 0, &mmGDS_VM_PROTECTION_FAULT[0], sizeof(mmGDS_VM_PROTECTION_FAULT)/sizeof(mmGDS_VM_PROTECTION_FAULT[0]), 0, 0 }, + { "mmGDS_EDC_CNT", REG_MMIO, 0x05c5, 0, &mmGDS_EDC_CNT[0], sizeof(mmGDS_EDC_CNT)/sizeof(mmGDS_EDC_CNT[0]), 0, 0 }, + { "mmGDS_EDC_GRBM_CNT", REG_MMIO, 0x05c6, 0, &mmGDS_EDC_GRBM_CNT[0], sizeof(mmGDS_EDC_GRBM_CNT)/sizeof(mmGDS_EDC_GRBM_CNT[0]), 0, 0 }, + { "mmGDS_EDC_OA_DED", REG_MMIO, 0x05c7, 0, &mmGDS_EDC_OA_DED[0], sizeof(mmGDS_EDC_OA_DED)/sizeof(mmGDS_EDC_OA_DED[0]), 0, 0 }, + { "mmGDS_DSM_CNTL", REG_MMIO, 0x05ca, 0, &mmGDS_DSM_CNTL[0], sizeof(mmGDS_DSM_CNTL)/sizeof(mmGDS_DSM_CNTL[0]), 0, 0 }, + { "mmGDS_EDC_OA_PHY_CNT", REG_MMIO, 0x05cb, 0, &mmGDS_EDC_OA_PHY_CNT[0], sizeof(mmGDS_EDC_OA_PHY_CNT)/sizeof(mmGDS_EDC_OA_PHY_CNT[0]), 0, 0 }, + { "mmGDS_EDC_OA_PIPE_CNT", REG_MMIO, 0x05cc, 0, &mmGDS_EDC_OA_PIPE_CNT[0], sizeof(mmGDS_EDC_OA_PIPE_CNT)/sizeof(mmGDS_EDC_OA_PIPE_CNT[0]), 0, 0 }, + { "mmGDS_DSM_CNTL2", REG_MMIO, 0x05cd, 0, &mmGDS_DSM_CNTL2[0], sizeof(mmGDS_DSM_CNTL2)/sizeof(mmGDS_DSM_CNTL2[0]), 0, 0 }, + { "mmGDS_WD_GDS_CSB", REG_MMIO, 0x05ce, 0, &mmGDS_WD_GDS_CSB[0], sizeof(mmGDS_WD_GDS_CSB)/sizeof(mmGDS_WD_GDS_CSB[0]), 0, 0 }, + { "mmDB_DEBUG", REG_MMIO, 0x060c, 0, &mmDB_DEBUG[0], sizeof(mmDB_DEBUG)/sizeof(mmDB_DEBUG[0]), 0, 0 }, + { "mmDB_DEBUG2", REG_MMIO, 0x060d, 0, &mmDB_DEBUG2[0], sizeof(mmDB_DEBUG2)/sizeof(mmDB_DEBUG2[0]), 0, 0 }, + { "mmDB_DEBUG3", REG_MMIO, 0x060e, 0, &mmDB_DEBUG3[0], sizeof(mmDB_DEBUG3)/sizeof(mmDB_DEBUG3[0]), 0, 0 }, + { "mmDB_DEBUG4", REG_MMIO, 0x060f, 0, &mmDB_DEBUG4[0], sizeof(mmDB_DEBUG4)/sizeof(mmDB_DEBUG4[0]), 0, 0 }, + { "mmDB_CREDIT_LIMIT", REG_MMIO, 0x0614, 0, &mmDB_CREDIT_LIMIT[0], sizeof(mmDB_CREDIT_LIMIT)/sizeof(mmDB_CREDIT_LIMIT[0]), 0, 0 }, + { "mmDB_WATERMARKS", REG_MMIO, 0x0615, 0, &mmDB_WATERMARKS[0], sizeof(mmDB_WATERMARKS)/sizeof(mmDB_WATERMARKS[0]), 0, 0 }, + { "mmDB_SUBTILE_CONTROL", REG_MMIO, 0x0616, 0, &mmDB_SUBTILE_CONTROL[0], sizeof(mmDB_SUBTILE_CONTROL)/sizeof(mmDB_SUBTILE_CONTROL[0]), 0, 0 }, + { "mmDB_FREE_CACHELINES", REG_MMIO, 0x0617, 0, &mmDB_FREE_CACHELINES[0], sizeof(mmDB_FREE_CACHELINES)/sizeof(mmDB_FREE_CACHELINES[0]), 0, 0 }, + { "mmDB_FIFO_DEPTH1", REG_MMIO, 0x0618, 0, &mmDB_FIFO_DEPTH1[0], sizeof(mmDB_FIFO_DEPTH1)/sizeof(mmDB_FIFO_DEPTH1[0]), 0, 0 }, + { "mmDB_FIFO_DEPTH2", REG_MMIO, 0x0619, 0, &mmDB_FIFO_DEPTH2[0], sizeof(mmDB_FIFO_DEPTH2)/sizeof(mmDB_FIFO_DEPTH2[0]), 0, 0 }, + { "mmDB_EXCEPTION_CONTROL", REG_MMIO, 0x061a, 0, &mmDB_EXCEPTION_CONTROL[0], sizeof(mmDB_EXCEPTION_CONTROL)/sizeof(mmDB_EXCEPTION_CONTROL[0]), 0, 0 }, + { "mmDB_RING_CONTROL", REG_MMIO, 0x061b, 0, &mmDB_RING_CONTROL[0], sizeof(mmDB_RING_CONTROL)/sizeof(mmDB_RING_CONTROL[0]), 0, 0 }, + { "mmDB_MEM_ARB_WATERMARKS", REG_MMIO, 0x061c, 0, &mmDB_MEM_ARB_WATERMARKS[0], sizeof(mmDB_MEM_ARB_WATERMARKS)/sizeof(mmDB_MEM_ARB_WATERMARKS[0]), 0, 0 }, + { "mmDB_RMI_CACHE_POLICY", REG_MMIO, 0x061e, 0, &mmDB_RMI_CACHE_POLICY[0], sizeof(mmDB_RMI_CACHE_POLICY)/sizeof(mmDB_RMI_CACHE_POLICY[0]), 0, 0 }, + { "mmDB_DFSM_CONFIG", REG_MMIO, 0x0630, 0, &mmDB_DFSM_CONFIG[0], sizeof(mmDB_DFSM_CONFIG)/sizeof(mmDB_DFSM_CONFIG[0]), 0, 0 }, + { "mmDB_DFSM_WATERMARK", REG_MMIO, 0x0631, 0, &mmDB_DFSM_WATERMARK[0], sizeof(mmDB_DFSM_WATERMARK)/sizeof(mmDB_DFSM_WATERMARK[0]), 0, 0 }, + { "mmDB_DFSM_TILES_IN_FLIGHT", REG_MMIO, 0x0632, 0, &mmDB_DFSM_TILES_IN_FLIGHT[0], sizeof(mmDB_DFSM_TILES_IN_FLIGHT)/sizeof(mmDB_DFSM_TILES_IN_FLIGHT[0]), 0, 0 }, + { "mmDB_DFSM_PRIMS_IN_FLIGHT", REG_MMIO, 0x0633, 0, &mmDB_DFSM_PRIMS_IN_FLIGHT[0], sizeof(mmDB_DFSM_PRIMS_IN_FLIGHT)/sizeof(mmDB_DFSM_PRIMS_IN_FLIGHT[0]), 0, 0 }, + { "mmDB_DFSM_WATCHDOG", REG_MMIO, 0x0634, 0, &mmDB_DFSM_WATCHDOG[0], sizeof(mmDB_DFSM_WATCHDOG)/sizeof(mmDB_DFSM_WATCHDOG[0]), 0, 0 }, + { "mmDB_DFSM_FLUSH_ENABLE", REG_MMIO, 0x0635, 0, &mmDB_DFSM_FLUSH_ENABLE[0], sizeof(mmDB_DFSM_FLUSH_ENABLE)/sizeof(mmDB_DFSM_FLUSH_ENABLE[0]), 0, 0 }, + { "mmDB_DFSM_FLUSH_AUX_EVENT", REG_MMIO, 0x0636, 0, &mmDB_DFSM_FLUSH_AUX_EVENT[0], sizeof(mmDB_DFSM_FLUSH_AUX_EVENT)/sizeof(mmDB_DFSM_FLUSH_AUX_EVENT[0]), 0, 0 }, + { "mmCC_RB_REDUNDANCY", REG_MMIO, 0x063c, 0, &mmCC_RB_REDUNDANCY[0], sizeof(mmCC_RB_REDUNDANCY)/sizeof(mmCC_RB_REDUNDANCY[0]), 0, 0 }, + { "mmCC_RB_BACKEND_DISABLE", REG_MMIO, 0x063d, 0, &mmCC_RB_BACKEND_DISABLE[0], sizeof(mmCC_RB_BACKEND_DISABLE)/sizeof(mmCC_RB_BACKEND_DISABLE[0]), 0, 0 }, + { "mmGB_ADDR_CONFIG", REG_MMIO, 0x063e, 0, &mmGB_ADDR_CONFIG[0], sizeof(mmGB_ADDR_CONFIG)/sizeof(mmGB_ADDR_CONFIG[0]), 0, 0 }, + { "mmGB_BACKEND_MAP", REG_MMIO, 0x063f, 0, &mmGB_BACKEND_MAP[0], sizeof(mmGB_BACKEND_MAP)/sizeof(mmGB_BACKEND_MAP[0]), 0, 0 }, + { "mmGB_GPU_ID", REG_MMIO, 0x0640, 0, &mmGB_GPU_ID[0], sizeof(mmGB_GPU_ID)/sizeof(mmGB_GPU_ID[0]), 0, 0 }, + { "mmCC_RB_DAISY_CHAIN", REG_MMIO, 0x0641, 0, &mmCC_RB_DAISY_CHAIN[0], sizeof(mmCC_RB_DAISY_CHAIN)/sizeof(mmCC_RB_DAISY_CHAIN[0]), 0, 0 }, + { "mmGB_ADDR_CONFIG_READ", REG_MMIO, 0x0642, 0, &mmGB_ADDR_CONFIG_READ[0], sizeof(mmGB_ADDR_CONFIG_READ)/sizeof(mmGB_ADDR_CONFIG_READ[0]), 0, 0 }, + { "mmGB_TILE_MODE0", REG_MMIO, 0x0644, 0, &mmGB_TILE_MODE0[0], sizeof(mmGB_TILE_MODE0)/sizeof(mmGB_TILE_MODE0[0]), 0, 0 }, + { "mmGB_TILE_MODE1", REG_MMIO, 0x0645, 0, &mmGB_TILE_MODE1[0], sizeof(mmGB_TILE_MODE1)/sizeof(mmGB_TILE_MODE1[0]), 0, 0 }, + { "mmGB_TILE_MODE2", REG_MMIO, 0x0646, 0, &mmGB_TILE_MODE2[0], sizeof(mmGB_TILE_MODE2)/sizeof(mmGB_TILE_MODE2[0]), 0, 0 }, + { "mmGB_TILE_MODE3", REG_MMIO, 0x0647, 0, &mmGB_TILE_MODE3[0], sizeof(mmGB_TILE_MODE3)/sizeof(mmGB_TILE_MODE3[0]), 0, 0 }, + { "mmGB_TILE_MODE4", REG_MMIO, 0x0648, 0, &mmGB_TILE_MODE4[0], sizeof(mmGB_TILE_MODE4)/sizeof(mmGB_TILE_MODE4[0]), 0, 0 }, + { "mmGB_TILE_MODE5", REG_MMIO, 0x0649, 0, &mmGB_TILE_MODE5[0], sizeof(mmGB_TILE_MODE5)/sizeof(mmGB_TILE_MODE5[0]), 0, 0 }, + { "mmGB_TILE_MODE6", REG_MMIO, 0x064a, 0, &mmGB_TILE_MODE6[0], sizeof(mmGB_TILE_MODE6)/sizeof(mmGB_TILE_MODE6[0]), 0, 0 }, + { "mmGB_TILE_MODE7", REG_MMIO, 0x064b, 0, &mmGB_TILE_MODE7[0], sizeof(mmGB_TILE_MODE7)/sizeof(mmGB_TILE_MODE7[0]), 0, 0 }, + { "mmGB_TILE_MODE8", REG_MMIO, 0x064c, 0, &mmGB_TILE_MODE8[0], sizeof(mmGB_TILE_MODE8)/sizeof(mmGB_TILE_MODE8[0]), 0, 0 }, + { "mmGB_TILE_MODE9", REG_MMIO, 0x064d, 0, &mmGB_TILE_MODE9[0], sizeof(mmGB_TILE_MODE9)/sizeof(mmGB_TILE_MODE9[0]), 0, 0 }, + { "mmGB_TILE_MODE10", REG_MMIO, 0x064e, 0, &mmGB_TILE_MODE10[0], sizeof(mmGB_TILE_MODE10)/sizeof(mmGB_TILE_MODE10[0]), 0, 0 }, + { "mmGB_TILE_MODE11", REG_MMIO, 0x064f, 0, &mmGB_TILE_MODE11[0], sizeof(mmGB_TILE_MODE11)/sizeof(mmGB_TILE_MODE11[0]), 0, 0 }, + { "mmGB_TILE_MODE12", REG_MMIO, 0x0650, 0, &mmGB_TILE_MODE12[0], sizeof(mmGB_TILE_MODE12)/sizeof(mmGB_TILE_MODE12[0]), 0, 0 }, + { "mmGB_TILE_MODE13", REG_MMIO, 0x0651, 0, &mmGB_TILE_MODE13[0], sizeof(mmGB_TILE_MODE13)/sizeof(mmGB_TILE_MODE13[0]), 0, 0 }, + { "mmGB_TILE_MODE14", REG_MMIO, 0x0652, 0, &mmGB_TILE_MODE14[0], sizeof(mmGB_TILE_MODE14)/sizeof(mmGB_TILE_MODE14[0]), 0, 0 }, + { "mmGB_TILE_MODE15", REG_MMIO, 0x0653, 0, &mmGB_TILE_MODE15[0], sizeof(mmGB_TILE_MODE15)/sizeof(mmGB_TILE_MODE15[0]), 0, 0 }, + { "mmGB_TILE_MODE16", REG_MMIO, 0x0654, 0, &mmGB_TILE_MODE16[0], sizeof(mmGB_TILE_MODE16)/sizeof(mmGB_TILE_MODE16[0]), 0, 0 }, + { "mmGB_TILE_MODE17", REG_MMIO, 0x0655, 0, &mmGB_TILE_MODE17[0], sizeof(mmGB_TILE_MODE17)/sizeof(mmGB_TILE_MODE17[0]), 0, 0 }, + { "mmGB_TILE_MODE18", REG_MMIO, 0x0656, 0, &mmGB_TILE_MODE18[0], sizeof(mmGB_TILE_MODE18)/sizeof(mmGB_TILE_MODE18[0]), 0, 0 }, + { "mmGB_TILE_MODE19", REG_MMIO, 0x0657, 0, &mmGB_TILE_MODE19[0], sizeof(mmGB_TILE_MODE19)/sizeof(mmGB_TILE_MODE19[0]), 0, 0 }, + { "mmGB_TILE_MODE20", REG_MMIO, 0x0658, 0, &mmGB_TILE_MODE20[0], sizeof(mmGB_TILE_MODE20)/sizeof(mmGB_TILE_MODE20[0]), 0, 0 }, + { "mmGB_TILE_MODE21", REG_MMIO, 0x0659, 0, &mmGB_TILE_MODE21[0], sizeof(mmGB_TILE_MODE21)/sizeof(mmGB_TILE_MODE21[0]), 0, 0 }, + { "mmGB_TILE_MODE22", REG_MMIO, 0x065a, 0, &mmGB_TILE_MODE22[0], sizeof(mmGB_TILE_MODE22)/sizeof(mmGB_TILE_MODE22[0]), 0, 0 }, + { "mmGB_TILE_MODE23", REG_MMIO, 0x065b, 0, &mmGB_TILE_MODE23[0], sizeof(mmGB_TILE_MODE23)/sizeof(mmGB_TILE_MODE23[0]), 0, 0 }, + { "mmGB_TILE_MODE24", REG_MMIO, 0x065c, 0, &mmGB_TILE_MODE24[0], sizeof(mmGB_TILE_MODE24)/sizeof(mmGB_TILE_MODE24[0]), 0, 0 }, + { "mmGB_TILE_MODE25", REG_MMIO, 0x065d, 0, &mmGB_TILE_MODE25[0], sizeof(mmGB_TILE_MODE25)/sizeof(mmGB_TILE_MODE25[0]), 0, 0 }, + { "mmGB_TILE_MODE26", REG_MMIO, 0x065e, 0, &mmGB_TILE_MODE26[0], sizeof(mmGB_TILE_MODE26)/sizeof(mmGB_TILE_MODE26[0]), 0, 0 }, + { "mmGB_TILE_MODE27", REG_MMIO, 0x065f, 0, &mmGB_TILE_MODE27[0], sizeof(mmGB_TILE_MODE27)/sizeof(mmGB_TILE_MODE27[0]), 0, 0 }, + { "mmGB_TILE_MODE28", REG_MMIO, 0x0660, 0, &mmGB_TILE_MODE28[0], sizeof(mmGB_TILE_MODE28)/sizeof(mmGB_TILE_MODE28[0]), 0, 0 }, + { "mmGB_TILE_MODE29", REG_MMIO, 0x0661, 0, &mmGB_TILE_MODE29[0], sizeof(mmGB_TILE_MODE29)/sizeof(mmGB_TILE_MODE29[0]), 0, 0 }, + { "mmGB_TILE_MODE30", REG_MMIO, 0x0662, 0, &mmGB_TILE_MODE30[0], sizeof(mmGB_TILE_MODE30)/sizeof(mmGB_TILE_MODE30[0]), 0, 0 }, + { "mmGB_TILE_MODE31", REG_MMIO, 0x0663, 0, &mmGB_TILE_MODE31[0], sizeof(mmGB_TILE_MODE31)/sizeof(mmGB_TILE_MODE31[0]), 0, 0 }, + { "mmGB_MACROTILE_MODE0", REG_MMIO, 0x0664, 0, &mmGB_MACROTILE_MODE0[0], sizeof(mmGB_MACROTILE_MODE0)/sizeof(mmGB_MACROTILE_MODE0[0]), 0, 0 }, + { "mmGB_MACROTILE_MODE1", REG_MMIO, 0x0665, 0, &mmGB_MACROTILE_MODE1[0], sizeof(mmGB_MACROTILE_MODE1)/sizeof(mmGB_MACROTILE_MODE1[0]), 0, 0 }, + { "mmGB_MACROTILE_MODE2", REG_MMIO, 0x0666, 0, &mmGB_MACROTILE_MODE2[0], sizeof(mmGB_MACROTILE_MODE2)/sizeof(mmGB_MACROTILE_MODE2[0]), 0, 0 }, + { "mmGB_MACROTILE_MODE3", REG_MMIO, 0x0667, 0, &mmGB_MACROTILE_MODE3[0], sizeof(mmGB_MACROTILE_MODE3)/sizeof(mmGB_MACROTILE_MODE3[0]), 0, 0 }, + { "mmGB_MACROTILE_MODE4", REG_MMIO, 0x0668, 0, &mmGB_MACROTILE_MODE4[0], sizeof(mmGB_MACROTILE_MODE4)/sizeof(mmGB_MACROTILE_MODE4[0]), 0, 0 }, + { "mmGB_MACROTILE_MODE5", REG_MMIO, 0x0669, 0, &mmGB_MACROTILE_MODE5[0], sizeof(mmGB_MACROTILE_MODE5)/sizeof(mmGB_MACROTILE_MODE5[0]), 0, 0 }, + { "mmGB_MACROTILE_MODE6", REG_MMIO, 0x066a, 0, &mmGB_MACROTILE_MODE6[0], sizeof(mmGB_MACROTILE_MODE6)/sizeof(mmGB_MACROTILE_MODE6[0]), 0, 0 }, + { "mmGB_MACROTILE_MODE7", REG_MMIO, 0x066b, 0, &mmGB_MACROTILE_MODE7[0], sizeof(mmGB_MACROTILE_MODE7)/sizeof(mmGB_MACROTILE_MODE7[0]), 0, 0 }, + { "mmGB_MACROTILE_MODE8", REG_MMIO, 0x066c, 0, &mmGB_MACROTILE_MODE8[0], sizeof(mmGB_MACROTILE_MODE8)/sizeof(mmGB_MACROTILE_MODE8[0]), 0, 0 }, + { "mmGB_MACROTILE_MODE9", REG_MMIO, 0x066d, 0, &mmGB_MACROTILE_MODE9[0], sizeof(mmGB_MACROTILE_MODE9)/sizeof(mmGB_MACROTILE_MODE9[0]), 0, 0 }, + { "mmGB_MACROTILE_MODE10", REG_MMIO, 0x066e, 0, &mmGB_MACROTILE_MODE10[0], sizeof(mmGB_MACROTILE_MODE10)/sizeof(mmGB_MACROTILE_MODE10[0]), 0, 0 }, + { "mmGB_MACROTILE_MODE11", REG_MMIO, 0x066f, 0, &mmGB_MACROTILE_MODE11[0], sizeof(mmGB_MACROTILE_MODE11)/sizeof(mmGB_MACROTILE_MODE11[0]), 0, 0 }, + { "mmGB_MACROTILE_MODE12", REG_MMIO, 0x0670, 0, &mmGB_MACROTILE_MODE12[0], sizeof(mmGB_MACROTILE_MODE12)/sizeof(mmGB_MACROTILE_MODE12[0]), 0, 0 }, + { "mmGB_MACROTILE_MODE13", REG_MMIO, 0x0671, 0, &mmGB_MACROTILE_MODE13[0], sizeof(mmGB_MACROTILE_MODE13)/sizeof(mmGB_MACROTILE_MODE13[0]), 0, 0 }, + { "mmGB_MACROTILE_MODE14", REG_MMIO, 0x0672, 0, &mmGB_MACROTILE_MODE14[0], sizeof(mmGB_MACROTILE_MODE14)/sizeof(mmGB_MACROTILE_MODE14[0]), 0, 0 }, + { "mmGB_MACROTILE_MODE15", REG_MMIO, 0x0673, 0, &mmGB_MACROTILE_MODE15[0], sizeof(mmGB_MACROTILE_MODE15)/sizeof(mmGB_MACROTILE_MODE15[0]), 0, 0 }, + { "mmCB_HW_CONTROL", REG_MMIO, 0x0680, 0, &mmCB_HW_CONTROL[0], sizeof(mmCB_HW_CONTROL)/sizeof(mmCB_HW_CONTROL[0]), 0, 0 }, + { "mmCB_HW_CONTROL_1", REG_MMIO, 0x0681, 0, &mmCB_HW_CONTROL_1[0], sizeof(mmCB_HW_CONTROL_1)/sizeof(mmCB_HW_CONTROL_1[0]), 0, 0 }, + { "mmCB_HW_CONTROL_2", REG_MMIO, 0x0682, 0, &mmCB_HW_CONTROL_2[0], sizeof(mmCB_HW_CONTROL_2)/sizeof(mmCB_HW_CONTROL_2[0]), 0, 0 }, + { "mmCB_HW_CONTROL_3", REG_MMIO, 0x0683, 0, &mmCB_HW_CONTROL_3[0], sizeof(mmCB_HW_CONTROL_3)/sizeof(mmCB_HW_CONTROL_3[0]), 0, 0 }, + { "mmCB_HW_MEM_ARBITER_RD", REG_MMIO, 0x0686, 0, &mmCB_HW_MEM_ARBITER_RD[0], sizeof(mmCB_HW_MEM_ARBITER_RD)/sizeof(mmCB_HW_MEM_ARBITER_RD[0]), 0, 0 }, + { "mmCB_HW_MEM_ARBITER_WR", REG_MMIO, 0x0687, 0, &mmCB_HW_MEM_ARBITER_WR[0], sizeof(mmCB_HW_MEM_ARBITER_WR)/sizeof(mmCB_HW_MEM_ARBITER_WR[0]), 0, 0 }, + { "mmCB_DCC_CONFIG", REG_MMIO, 0x0688, 0, &mmCB_DCC_CONFIG[0], sizeof(mmCB_DCC_CONFIG)/sizeof(mmCB_DCC_CONFIG[0]), 0, 0 }, + { "mmGC_USER_RB_REDUNDANCY", REG_MMIO, 0x06de, 0, &mmGC_USER_RB_REDUNDANCY[0], sizeof(mmGC_USER_RB_REDUNDANCY)/sizeof(mmGC_USER_RB_REDUNDANCY[0]), 0, 0 }, + { "mmGC_USER_RB_BACKEND_DISABLE", REG_MMIO, 0x06df, 0, &mmGC_USER_RB_BACKEND_DISABLE[0], sizeof(mmGC_USER_RB_BACKEND_DISABLE)/sizeof(mmGC_USER_RB_BACKEND_DISABLE[0]), 0, 0 }, + { "mmGCEA_EDC_CNT", REG_MMIO, 0x0701, 0, &mmGCEA_EDC_CNT[0], sizeof(mmGCEA_EDC_CNT)/sizeof(mmGCEA_EDC_CNT[0]), 0, 0 }, + { "mmGCEA_EDC_CNT2", REG_MMIO, 0x0702, 0, &mmGCEA_EDC_CNT2[0], sizeof(mmGCEA_EDC_CNT2)/sizeof(mmGCEA_EDC_CNT2[0]), 0, 0 }, + { "mmGCEA_DSM_CNTL", REG_MMIO, 0x0703, 0, &mmGCEA_DSM_CNTL[0], sizeof(mmGCEA_DSM_CNTL)/sizeof(mmGCEA_DSM_CNTL[0]), 0, 0 }, + { "mmGCEA_DSM_CNTLA", REG_MMIO, 0x0704, 0, &mmGCEA_DSM_CNTLA[0], sizeof(mmGCEA_DSM_CNTLA)/sizeof(mmGCEA_DSM_CNTLA[0]), 0, 0 }, + { "mmGCEA_DSM_CNTLB", REG_MMIO, 0x0705, 0, NULL, 0, 0, 0 }, + { "mmGCEA_DSM_CNTL2", REG_MMIO, 0x0706, 0, &mmGCEA_DSM_CNTL2[0], sizeof(mmGCEA_DSM_CNTL2)/sizeof(mmGCEA_DSM_CNTL2[0]), 0, 0 }, + { "mmGCEA_DSM_CNTL2A", REG_MMIO, 0x0707, 0, &mmGCEA_DSM_CNTL2A[0], sizeof(mmGCEA_DSM_CNTL2A)/sizeof(mmGCEA_DSM_CNTL2A[0]), 0, 0 }, + { "mmGCEA_DSM_CNTL2B", REG_MMIO, 0x0708, 0, NULL, 0, 0, 0 }, + { "mmGCEA_TCC_XBR_CREDITS", REG_MMIO, 0x0709, 0, &mmGCEA_TCC_XBR_CREDITS[0], sizeof(mmGCEA_TCC_XBR_CREDITS)/sizeof(mmGCEA_TCC_XBR_CREDITS[0]), 0, 0 }, + { "mmGCEA_TCC_XBR_MAXBURST", REG_MMIO, 0x070a, 0, &mmGCEA_TCC_XBR_MAXBURST[0], sizeof(mmGCEA_TCC_XBR_MAXBURST)/sizeof(mmGCEA_TCC_XBR_MAXBURST[0]), 0, 0 }, + { "mmGCEA_PROBE_CNTL", REG_MMIO, 0x070b, 0, &mmGCEA_PROBE_CNTL[0], sizeof(mmGCEA_PROBE_CNTL)/sizeof(mmGCEA_PROBE_CNTL[0]), 0, 0 }, + { "mmGCEA_PROBE_MAP", REG_MMIO, 0x070c, 0, &mmGCEA_PROBE_MAP[0], sizeof(mmGCEA_PROBE_MAP)/sizeof(mmGCEA_PROBE_MAP[0]), 0, 0 }, + { "mmGCEA_ERR_STATUS", REG_MMIO, 0x070d, 0, &mmGCEA_ERR_STATUS[0], sizeof(mmGCEA_ERR_STATUS)/sizeof(mmGCEA_ERR_STATUS[0]), 0, 0 }, + { "mmGCEA_MISC2", REG_MMIO, 0x070e, 0, &mmGCEA_MISC2[0], sizeof(mmGCEA_MISC2)/sizeof(mmGCEA_MISC2[0]), 0, 0 }, + { "mmGCEA_SDP_BACKDOOR_CMDCREDITS0", REG_MMIO, 0x070f, 0, &mmGCEA_SDP_BACKDOOR_CMDCREDITS0[0], sizeof(mmGCEA_SDP_BACKDOOR_CMDCREDITS0)/sizeof(mmGCEA_SDP_BACKDOOR_CMDCREDITS0[0]), 0, 0 }, + { "mmGCEA_SDP_BACKDOOR_CMDCREDITS1", REG_MMIO, 0x0710, 0, &mmGCEA_SDP_BACKDOOR_CMDCREDITS1[0], sizeof(mmGCEA_SDP_BACKDOOR_CMDCREDITS1)/sizeof(mmGCEA_SDP_BACKDOOR_CMDCREDITS1[0]), 0, 0 }, + { "mmGCEA_SDP_BACKDOOR_DATACREDITS0", REG_MMIO, 0x0711, 0, &mmGCEA_SDP_BACKDOOR_DATACREDITS0[0], sizeof(mmGCEA_SDP_BACKDOOR_DATACREDITS0)/sizeof(mmGCEA_SDP_BACKDOOR_DATACREDITS0[0]), 0, 0 }, + { "mmGCEA_SDP_BACKDOOR_DATACREDITS1", REG_MMIO, 0x0712, 0, &mmGCEA_SDP_BACKDOOR_DATACREDITS1[0], sizeof(mmGCEA_SDP_BACKDOOR_DATACREDITS1)/sizeof(mmGCEA_SDP_BACKDOOR_DATACREDITS1[0]), 0, 0 }, + { "mmGCEA_SDP_BACKDOOR_MISCCREDITS", REG_MMIO, 0x0713, 0, &mmGCEA_SDP_BACKDOOR_MISCCREDITS[0], sizeof(mmGCEA_SDP_BACKDOOR_MISCCREDITS)/sizeof(mmGCEA_SDP_BACKDOOR_MISCCREDITS[0]), 0, 0 }, + { "mmGCEA_SDP_ENABLE", REG_MMIO, 0x0714, 0, &mmGCEA_SDP_ENABLE[0], sizeof(mmGCEA_SDP_ENABLE)/sizeof(mmGCEA_SDP_ENABLE[0]), 0, 0 }, + { "mmRMI_GENERAL_CNTL", REG_MMIO, 0x0780, 0, &mmRMI_GENERAL_CNTL[0], sizeof(mmRMI_GENERAL_CNTL)/sizeof(mmRMI_GENERAL_CNTL[0]), 0, 0 }, + { "mmRMI_GENERAL_CNTL1", REG_MMIO, 0x0781, 0, &mmRMI_GENERAL_CNTL1[0], sizeof(mmRMI_GENERAL_CNTL1)/sizeof(mmRMI_GENERAL_CNTL1[0]), 0, 0 }, + { "mmRMI_GENERAL_STATUS", REG_MMIO, 0x0782, 0, &mmRMI_GENERAL_STATUS[0], sizeof(mmRMI_GENERAL_STATUS)/sizeof(mmRMI_GENERAL_STATUS[0]), 0, 0 }, + { "mmRMI_SUBBLOCK_STATUS0", REG_MMIO, 0x0783, 0, &mmRMI_SUBBLOCK_STATUS0[0], sizeof(mmRMI_SUBBLOCK_STATUS0)/sizeof(mmRMI_SUBBLOCK_STATUS0[0]), 0, 0 }, + { "mmRMI_SUBBLOCK_STATUS1", REG_MMIO, 0x0784, 0, &mmRMI_SUBBLOCK_STATUS1[0], sizeof(mmRMI_SUBBLOCK_STATUS1)/sizeof(mmRMI_SUBBLOCK_STATUS1[0]), 0, 0 }, + { "mmRMI_SUBBLOCK_STATUS2", REG_MMIO, 0x0785, 0, &mmRMI_SUBBLOCK_STATUS2[0], sizeof(mmRMI_SUBBLOCK_STATUS2)/sizeof(mmRMI_SUBBLOCK_STATUS2[0]), 0, 0 }, + { "mmRMI_SUBBLOCK_STATUS3", REG_MMIO, 0x0786, 0, &mmRMI_SUBBLOCK_STATUS3[0], sizeof(mmRMI_SUBBLOCK_STATUS3)/sizeof(mmRMI_SUBBLOCK_STATUS3[0]), 0, 0 }, + { "mmRMI_XBAR_CONFIG", REG_MMIO, 0x0787, 0, &mmRMI_XBAR_CONFIG[0], sizeof(mmRMI_XBAR_CONFIG)/sizeof(mmRMI_XBAR_CONFIG[0]), 0, 0 }, + { "mmRMI_PROBE_POP_LOGIC_CNTL", REG_MMIO, 0x0788, 0, &mmRMI_PROBE_POP_LOGIC_CNTL[0], sizeof(mmRMI_PROBE_POP_LOGIC_CNTL)/sizeof(mmRMI_PROBE_POP_LOGIC_CNTL[0]), 0, 0 }, + { "mmRMI_UTC_XNACK_N_MISC_CNTL", REG_MMIO, 0x0789, 0, &mmRMI_UTC_XNACK_N_MISC_CNTL[0], sizeof(mmRMI_UTC_XNACK_N_MISC_CNTL)/sizeof(mmRMI_UTC_XNACK_N_MISC_CNTL[0]), 0, 0 }, + { "mmRMI_DEMUX_CNTL", REG_MMIO, 0x078a, 0, &mmRMI_DEMUX_CNTL[0], sizeof(mmRMI_DEMUX_CNTL)/sizeof(mmRMI_DEMUX_CNTL[0]), 0, 0 }, + { "mmRMI_UTCL1_CNTL1", REG_MMIO, 0x078b, 0, &mmRMI_UTCL1_CNTL1[0], sizeof(mmRMI_UTCL1_CNTL1)/sizeof(mmRMI_UTCL1_CNTL1[0]), 0, 0 }, + { "mmRMI_UTCL1_CNTL2", REG_MMIO, 0x078c, 0, &mmRMI_UTCL1_CNTL2[0], sizeof(mmRMI_UTCL1_CNTL2)/sizeof(mmRMI_UTCL1_CNTL2[0]), 0, 0 }, + { "mmRMI_UTC_UNIT_CONFIG", REG_MMIO, 0x078d, 0, NULL, 0, 0, 0 }, + { "mmRMI_TCIW_FORMATTER0_CNTL", REG_MMIO, 0x078e, 0, &mmRMI_TCIW_FORMATTER0_CNTL[0], sizeof(mmRMI_TCIW_FORMATTER0_CNTL)/sizeof(mmRMI_TCIW_FORMATTER0_CNTL[0]), 0, 0 }, + { "mmRMI_TCIW_FORMATTER1_CNTL", REG_MMIO, 0x078f, 0, &mmRMI_TCIW_FORMATTER1_CNTL[0], sizeof(mmRMI_TCIW_FORMATTER1_CNTL)/sizeof(mmRMI_TCIW_FORMATTER1_CNTL[0]), 0, 0 }, + { "mmRMI_SCOREBOARD_CNTL", REG_MMIO, 0x0790, 0, &mmRMI_SCOREBOARD_CNTL[0], sizeof(mmRMI_SCOREBOARD_CNTL)/sizeof(mmRMI_SCOREBOARD_CNTL[0]), 0, 0 }, + { "mmRMI_SCOREBOARD_STATUS0", REG_MMIO, 0x0791, 0, &mmRMI_SCOREBOARD_STATUS0[0], sizeof(mmRMI_SCOREBOARD_STATUS0)/sizeof(mmRMI_SCOREBOARD_STATUS0[0]), 0, 0 }, + { "mmRMI_SCOREBOARD_STATUS1", REG_MMIO, 0x0792, 0, &mmRMI_SCOREBOARD_STATUS1[0], sizeof(mmRMI_SCOREBOARD_STATUS1)/sizeof(mmRMI_SCOREBOARD_STATUS1[0]), 0, 0 }, + { "mmRMI_SCOREBOARD_STATUS2", REG_MMIO, 0x0793, 0, &mmRMI_SCOREBOARD_STATUS2[0], sizeof(mmRMI_SCOREBOARD_STATUS2)/sizeof(mmRMI_SCOREBOARD_STATUS2[0]), 0, 0 }, + { "mmRMI_XBAR_ARBITER_CONFIG", REG_MMIO, 0x0794, 0, &mmRMI_XBAR_ARBITER_CONFIG[0], sizeof(mmRMI_XBAR_ARBITER_CONFIG)/sizeof(mmRMI_XBAR_ARBITER_CONFIG[0]), 0, 0 }, + { "mmRMI_XBAR_ARBITER_CONFIG_1", REG_MMIO, 0x0795, 0, &mmRMI_XBAR_ARBITER_CONFIG_1[0], sizeof(mmRMI_XBAR_ARBITER_CONFIG_1)/sizeof(mmRMI_XBAR_ARBITER_CONFIG_1[0]), 0, 0 }, + { "mmRMI_CLOCK_CNTRL", REG_MMIO, 0x0796, 0, &mmRMI_CLOCK_CNTRL[0], sizeof(mmRMI_CLOCK_CNTRL)/sizeof(mmRMI_CLOCK_CNTRL[0]), 0, 0 }, + { "mmRMI_UTCL1_STATUS", REG_MMIO, 0x0797, 0, &mmRMI_UTCL1_STATUS[0], sizeof(mmRMI_UTCL1_STATUS)/sizeof(mmRMI_UTCL1_STATUS[0]), 0, 0 }, + { "mmRMI_SPARE", REG_MMIO, 0x079e, 0, &mmRMI_SPARE[0], sizeof(mmRMI_SPARE)/sizeof(mmRMI_SPARE[0]), 0, 0 }, + { "mmRMI_SPARE_1", REG_MMIO, 0x079f, 0, &mmRMI_SPARE_1[0], sizeof(mmRMI_SPARE_1)/sizeof(mmRMI_SPARE_1[0]), 0, 0 }, + { "mmRMI_SPARE_2", REG_MMIO, 0x07a0, 0, &mmRMI_SPARE_2[0], sizeof(mmRMI_SPARE_2)/sizeof(mmRMI_SPARE_2[0]), 0, 0 }, + { "mmport_a_addr", REG_MMIO, 0x07c0, 0, &mmport_a_addr[0], sizeof(mmport_a_addr)/sizeof(mmport_a_addr[0]), 0, 0 }, + { "mmport_a_data_lo", REG_MMIO, 0x07c1, 0, &mmport_a_data_lo[0], sizeof(mmport_a_data_lo)/sizeof(mmport_a_data_lo[0]), 0, 0 }, + { "mmport_a_data_hi", REG_MMIO, 0x07c2, 0, &mmport_a_data_hi[0], sizeof(mmport_a_data_hi)/sizeof(mmport_a_data_hi[0]), 0, 0 }, + { "mmport_b_addr", REG_MMIO, 0x07c3, 0, &mmport_b_addr[0], sizeof(mmport_b_addr)/sizeof(mmport_b_addr[0]), 0, 0 }, + { "mmport_b_data_lo", REG_MMIO, 0x07c4, 0, &mmport_b_data_lo[0], sizeof(mmport_b_data_lo)/sizeof(mmport_b_data_lo[0]), 0, 0 }, + { "mmport_b_data_hi", REG_MMIO, 0x07c5, 0, &mmport_b_data_hi[0], sizeof(mmport_b_data_hi)/sizeof(mmport_b_data_hi[0]), 0, 0 }, + { "mmport_c_addr", REG_MMIO, 0x07c6, 0, &mmport_c_addr[0], sizeof(mmport_c_addr)/sizeof(mmport_c_addr[0]), 0, 0 }, + { "mmport_c_data_lo", REG_MMIO, 0x07c7, 0, &mmport_c_data_lo[0], sizeof(mmport_c_data_lo)/sizeof(mmport_c_data_lo[0]), 0, 0 }, + { "mmport_c_data_hi", REG_MMIO, 0x07c8, 0, &mmport_c_data_hi[0], sizeof(mmport_c_data_hi)/sizeof(mmport_c_data_hi[0]), 0, 0 }, + { "mmport_d_addr", REG_MMIO, 0x07c9, 0, &mmport_d_addr[0], sizeof(mmport_d_addr)/sizeof(mmport_d_addr[0]), 0, 0 }, + { "mmport_d_data_lo", REG_MMIO, 0x07ca, 0, &mmport_d_data_lo[0], sizeof(mmport_d_data_lo)/sizeof(mmport_d_data_lo[0]), 0, 0 }, + { "mmport_d_data_hi", REG_MMIO, 0x07cb, 0, &mmport_d_data_hi[0], sizeof(mmport_d_data_hi)/sizeof(mmport_d_data_hi[0]), 0, 0 }, + { "mmATC_L2_CNTL", REG_MMIO, 0x0800, 0, &mmATC_L2_CNTL[0], sizeof(mmATC_L2_CNTL)/sizeof(mmATC_L2_CNTL[0]), 0, 0 }, + { "mmATC_L2_CNTL2", REG_MMIO, 0x0801, 0, &mmATC_L2_CNTL2[0], sizeof(mmATC_L2_CNTL2)/sizeof(mmATC_L2_CNTL2[0]), 0, 0 }, + { "mmATC_L2_CACHE_DATA0", REG_MMIO, 0x0804, 0, &mmATC_L2_CACHE_DATA0[0], sizeof(mmATC_L2_CACHE_DATA0)/sizeof(mmATC_L2_CACHE_DATA0[0]), 0, 0 }, + { "mmATC_L2_CACHE_DATA1", REG_MMIO, 0x0805, 0, &mmATC_L2_CACHE_DATA1[0], sizeof(mmATC_L2_CACHE_DATA1)/sizeof(mmATC_L2_CACHE_DATA1[0]), 0, 0 }, + { "mmATC_L2_CACHE_DATA2", REG_MMIO, 0x0806, 0, &mmATC_L2_CACHE_DATA2[0], sizeof(mmATC_L2_CACHE_DATA2)/sizeof(mmATC_L2_CACHE_DATA2[0]), 0, 0 }, + { "mmATC_L2_CNTL3", REG_MMIO, 0x0807, 0, &mmATC_L2_CNTL3[0], sizeof(mmATC_L2_CNTL3)/sizeof(mmATC_L2_CNTL3[0]), 0, 0 }, + { "mmATC_L2_STATUS", REG_MMIO, 0x0808, 0, &mmATC_L2_STATUS[0], sizeof(mmATC_L2_STATUS)/sizeof(mmATC_L2_STATUS[0]), 0, 0 }, + { "mmATC_L2_STATUS2", REG_MMIO, 0x0809, 0, &mmATC_L2_STATUS2[0], sizeof(mmATC_L2_STATUS2)/sizeof(mmATC_L2_STATUS2[0]), 0, 0 }, + { "mmATC_L2_MISC_CG", REG_MMIO, 0x080a, 0, &mmATC_L2_MISC_CG[0], sizeof(mmATC_L2_MISC_CG)/sizeof(mmATC_L2_MISC_CG[0]), 0, 0 }, + { "mmATC_L2_MEM_POWER_LS", REG_MMIO, 0x080b, 0, &mmATC_L2_MEM_POWER_LS[0], sizeof(mmATC_L2_MEM_POWER_LS)/sizeof(mmATC_L2_MEM_POWER_LS[0]), 0, 0 }, + { "mmATC_L2_CGTT_CLK_CTRL", REG_MMIO, 0x080c, 0, &mmATC_L2_CGTT_CLK_CTRL[0], sizeof(mmATC_L2_CGTT_CLK_CTRL)/sizeof(mmATC_L2_CGTT_CLK_CTRL[0]), 0, 0 }, + { "mmVM_L2_CNTL", REG_MMIO, 0x0840, 0, &mmVM_L2_CNTL[0], sizeof(mmVM_L2_CNTL)/sizeof(mmVM_L2_CNTL[0]), 0, 0 }, + { "mmVM_L2_CNTL2", REG_MMIO, 0x0841, 0, &mmVM_L2_CNTL2[0], sizeof(mmVM_L2_CNTL2)/sizeof(mmVM_L2_CNTL2[0]), 0, 0 }, + { "mmVM_L2_CNTL3", REG_MMIO, 0x0842, 0, &mmVM_L2_CNTL3[0], sizeof(mmVM_L2_CNTL3)/sizeof(mmVM_L2_CNTL3[0]), 0, 0 }, + { "mmVM_L2_STATUS", REG_MMIO, 0x0843, 0, &mmVM_L2_STATUS[0], sizeof(mmVM_L2_STATUS)/sizeof(mmVM_L2_STATUS[0]), 0, 0 }, + { "mmVM_DUMMY_PAGE_FAULT_CNTL", REG_MMIO, 0x0844, 0, &mmVM_DUMMY_PAGE_FAULT_CNTL[0], sizeof(mmVM_DUMMY_PAGE_FAULT_CNTL)/sizeof(mmVM_DUMMY_PAGE_FAULT_CNTL[0]), 0, 0 }, + { "mmVM_DUMMY_PAGE_FAULT_ADDR_LO32", REG_MMIO, 0x0845, 0, &mmVM_DUMMY_PAGE_FAULT_ADDR_LO32[0], sizeof(mmVM_DUMMY_PAGE_FAULT_ADDR_LO32)/sizeof(mmVM_DUMMY_PAGE_FAULT_ADDR_LO32[0]), 0, 0 }, + { "mmVM_DUMMY_PAGE_FAULT_ADDR_HI32", REG_MMIO, 0x0846, 0, &mmVM_DUMMY_PAGE_FAULT_ADDR_HI32[0], sizeof(mmVM_DUMMY_PAGE_FAULT_ADDR_HI32)/sizeof(mmVM_DUMMY_PAGE_FAULT_ADDR_HI32[0]), 0, 0 }, + { "mmVM_L2_PROTECTION_FAULT_CNTL", REG_MMIO, 0x0847, 0, &mmVM_L2_PROTECTION_FAULT_CNTL[0], sizeof(mmVM_L2_PROTECTION_FAULT_CNTL)/sizeof(mmVM_L2_PROTECTION_FAULT_CNTL[0]), 0, 0 }, + { "mmVM_L2_PROTECTION_FAULT_CNTL2", REG_MMIO, 0x0848, 0, &mmVM_L2_PROTECTION_FAULT_CNTL2[0], sizeof(mmVM_L2_PROTECTION_FAULT_CNTL2)/sizeof(mmVM_L2_PROTECTION_FAULT_CNTL2[0]), 0, 0 }, + { "mmVM_L2_PROTECTION_FAULT_MM_CNTL3", REG_MMIO, 0x0849, 0, &mmVM_L2_PROTECTION_FAULT_MM_CNTL3[0], sizeof(mmVM_L2_PROTECTION_FAULT_MM_CNTL3)/sizeof(mmVM_L2_PROTECTION_FAULT_MM_CNTL3[0]), 0, 0 }, + { "mmVM_L2_PROTECTION_FAULT_MM_CNTL4", REG_MMIO, 0x084a, 0, &mmVM_L2_PROTECTION_FAULT_MM_CNTL4[0], sizeof(mmVM_L2_PROTECTION_FAULT_MM_CNTL4)/sizeof(mmVM_L2_PROTECTION_FAULT_MM_CNTL4[0]), 0, 0 }, + { "mmVM_L2_PROTECTION_FAULT_STATUS", REG_MMIO, 0x084b, 0, &mmVM_L2_PROTECTION_FAULT_STATUS[0], sizeof(mmVM_L2_PROTECTION_FAULT_STATUS)/sizeof(mmVM_L2_PROTECTION_FAULT_STATUS[0]), 0, 0 }, + { "mmVM_L2_PROTECTION_FAULT_ADDR_LO32", REG_MMIO, 0x084c, 0, &mmVM_L2_PROTECTION_FAULT_ADDR_LO32[0], sizeof(mmVM_L2_PROTECTION_FAULT_ADDR_LO32)/sizeof(mmVM_L2_PROTECTION_FAULT_ADDR_LO32[0]), 0, 0 }, + { "mmVM_L2_PROTECTION_FAULT_ADDR_HI32", REG_MMIO, 0x084d, 0, &mmVM_L2_PROTECTION_FAULT_ADDR_HI32[0], sizeof(mmVM_L2_PROTECTION_FAULT_ADDR_HI32)/sizeof(mmVM_L2_PROTECTION_FAULT_ADDR_HI32[0]), 0, 0 }, + { "mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32", REG_MMIO, 0x084e, 0, &mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32[0], sizeof(mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32)/sizeof(mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32[0]), 0, 0 }, + { "mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32", REG_MMIO, 0x084f, 0, &mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32[0], sizeof(mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32)/sizeof(mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32[0]), 0, 0 }, + { "mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32", REG_MMIO, 0x0851, 0, &mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32[0], sizeof(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32)/sizeof(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32[0]), 0, 0 }, + { "mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32", REG_MMIO, 0x0852, 0, &mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32[0], sizeof(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32)/sizeof(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32[0]), 0, 0 }, + { "mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32", REG_MMIO, 0x0853, 0, &mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32[0], sizeof(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32)/sizeof(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32[0]), 0, 0 }, + { "mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32", REG_MMIO, 0x0854, 0, &mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32[0], sizeof(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32)/sizeof(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32[0]), 0, 0 }, + { "mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32", REG_MMIO, 0x0855, 0, &mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32[0], sizeof(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32)/sizeof(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32[0]), 0, 0 }, + { "mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32", REG_MMIO, 0x0856, 0, &mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32[0], sizeof(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32)/sizeof(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32[0]), 0, 0 }, + { "mmVM_L2_CNTL4", REG_MMIO, 0x0857, 0, &mmVM_L2_CNTL4[0], sizeof(mmVM_L2_CNTL4)/sizeof(mmVM_L2_CNTL4[0]), 0, 0 }, + { "mmVM_L2_MM_GROUP_RT_CLASSES", REG_MMIO, 0x0858, 0, &mmVM_L2_MM_GROUP_RT_CLASSES[0], sizeof(mmVM_L2_MM_GROUP_RT_CLASSES)/sizeof(mmVM_L2_MM_GROUP_RT_CLASSES[0]), 0, 0 }, + { "mmVM_L2_BANK_SELECT_RESERVED_CID", REG_MMIO, 0x0859, 0, &mmVM_L2_BANK_SELECT_RESERVED_CID[0], sizeof(mmVM_L2_BANK_SELECT_RESERVED_CID)/sizeof(mmVM_L2_BANK_SELECT_RESERVED_CID[0]), 0, 0 }, + { "mmVM_L2_BANK_SELECT_RESERVED_CID2", REG_MMIO, 0x085a, 0, &mmVM_L2_BANK_SELECT_RESERVED_CID2[0], sizeof(mmVM_L2_BANK_SELECT_RESERVED_CID2)/sizeof(mmVM_L2_BANK_SELECT_RESERVED_CID2[0]), 0, 0 }, + { "mmVM_L2_CACHE_PARITY_CNTL", REG_MMIO, 0x085b, 0, &mmVM_L2_CACHE_PARITY_CNTL[0], sizeof(mmVM_L2_CACHE_PARITY_CNTL)/sizeof(mmVM_L2_CACHE_PARITY_CNTL[0]), 0, 0 }, + { "mmVM_L2_CGTT_CLK_CTRL", REG_MMIO, 0x085e, 0, &mmVM_L2_CGTT_CLK_CTRL[0], sizeof(mmVM_L2_CGTT_CLK_CTRL)/sizeof(mmVM_L2_CGTT_CLK_CTRL[0]), 0, 0 }, + { "mmVM_CONTEXT0_CNTL", REG_MMIO, 0x0880, 0, &mmVM_CONTEXT0_CNTL[0], sizeof(mmVM_CONTEXT0_CNTL)/sizeof(mmVM_CONTEXT0_CNTL[0]), 0, 0 }, + { "mmVM_CONTEXT1_CNTL", REG_MMIO, 0x0881, 0, &mmVM_CONTEXT1_CNTL[0], sizeof(mmVM_CONTEXT1_CNTL)/sizeof(mmVM_CONTEXT1_CNTL[0]), 0, 0 }, + { "mmVM_CONTEXT2_CNTL", REG_MMIO, 0x0882, 0, &mmVM_CONTEXT2_CNTL[0], sizeof(mmVM_CONTEXT2_CNTL)/sizeof(mmVM_CONTEXT2_CNTL[0]), 0, 0 }, + { "mmVM_CONTEXT3_CNTL", REG_MMIO, 0x0883, 0, &mmVM_CONTEXT3_CNTL[0], sizeof(mmVM_CONTEXT3_CNTL)/sizeof(mmVM_CONTEXT3_CNTL[0]), 0, 0 }, + { "mmVM_CONTEXT4_CNTL", REG_MMIO, 0x0884, 0, &mmVM_CONTEXT4_CNTL[0], sizeof(mmVM_CONTEXT4_CNTL)/sizeof(mmVM_CONTEXT4_CNTL[0]), 0, 0 }, + { "mmVM_CONTEXT5_CNTL", REG_MMIO, 0x0885, 0, &mmVM_CONTEXT5_CNTL[0], sizeof(mmVM_CONTEXT5_CNTL)/sizeof(mmVM_CONTEXT5_CNTL[0]), 0, 0 }, + { "mmVM_CONTEXT6_CNTL", REG_MMIO, 0x0886, 0, &mmVM_CONTEXT6_CNTL[0], sizeof(mmVM_CONTEXT6_CNTL)/sizeof(mmVM_CONTEXT6_CNTL[0]), 0, 0 }, + { "mmVM_CONTEXT7_CNTL", REG_MMIO, 0x0887, 0, &mmVM_CONTEXT7_CNTL[0], sizeof(mmVM_CONTEXT7_CNTL)/sizeof(mmVM_CONTEXT7_CNTL[0]), 0, 0 }, + { "mmVM_CONTEXT8_CNTL", REG_MMIO, 0x0888, 0, &mmVM_CONTEXT8_CNTL[0], sizeof(mmVM_CONTEXT8_CNTL)/sizeof(mmVM_CONTEXT8_CNTL[0]), 0, 0 }, + { "mmVM_CONTEXT9_CNTL", REG_MMIO, 0x0889, 0, &mmVM_CONTEXT9_CNTL[0], sizeof(mmVM_CONTEXT9_CNTL)/sizeof(mmVM_CONTEXT9_CNTL[0]), 0, 0 }, + { "mmVM_CONTEXT10_CNTL", REG_MMIO, 0x088a, 0, &mmVM_CONTEXT10_CNTL[0], sizeof(mmVM_CONTEXT10_CNTL)/sizeof(mmVM_CONTEXT10_CNTL[0]), 0, 0 }, + { "mmVM_CONTEXT11_CNTL", REG_MMIO, 0x088b, 0, &mmVM_CONTEXT11_CNTL[0], sizeof(mmVM_CONTEXT11_CNTL)/sizeof(mmVM_CONTEXT11_CNTL[0]), 0, 0 }, + { "mmVM_CONTEXT12_CNTL", REG_MMIO, 0x088c, 0, &mmVM_CONTEXT12_CNTL[0], sizeof(mmVM_CONTEXT12_CNTL)/sizeof(mmVM_CONTEXT12_CNTL[0]), 0, 0 }, + { "mmVM_CONTEXT13_CNTL", REG_MMIO, 0x088d, 0, &mmVM_CONTEXT13_CNTL[0], sizeof(mmVM_CONTEXT13_CNTL)/sizeof(mmVM_CONTEXT13_CNTL[0]), 0, 0 }, + { "mmVM_CONTEXT14_CNTL", REG_MMIO, 0x088e, 0, &mmVM_CONTEXT14_CNTL[0], sizeof(mmVM_CONTEXT14_CNTL)/sizeof(mmVM_CONTEXT14_CNTL[0]), 0, 0 }, + { "mmVM_CONTEXT15_CNTL", REG_MMIO, 0x088f, 0, &mmVM_CONTEXT15_CNTL[0], sizeof(mmVM_CONTEXT15_CNTL)/sizeof(mmVM_CONTEXT15_CNTL[0]), 0, 0 }, + { "mmVM_CONTEXTS_DISABLE", REG_MMIO, 0x0890, 0, &mmVM_CONTEXTS_DISABLE[0], sizeof(mmVM_CONTEXTS_DISABLE)/sizeof(mmVM_CONTEXTS_DISABLE[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG0_SEM", REG_MMIO, 0x0891, 0, &mmVM_INVALIDATE_ENG0_SEM[0], sizeof(mmVM_INVALIDATE_ENG0_SEM)/sizeof(mmVM_INVALIDATE_ENG0_SEM[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG1_SEM", REG_MMIO, 0x0892, 0, &mmVM_INVALIDATE_ENG1_SEM[0], sizeof(mmVM_INVALIDATE_ENG1_SEM)/sizeof(mmVM_INVALIDATE_ENG1_SEM[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG2_SEM", REG_MMIO, 0x0893, 0, &mmVM_INVALIDATE_ENG2_SEM[0], sizeof(mmVM_INVALIDATE_ENG2_SEM)/sizeof(mmVM_INVALIDATE_ENG2_SEM[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG3_SEM", REG_MMIO, 0x0894, 0, &mmVM_INVALIDATE_ENG3_SEM[0], sizeof(mmVM_INVALIDATE_ENG3_SEM)/sizeof(mmVM_INVALIDATE_ENG3_SEM[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG4_SEM", REG_MMIO, 0x0895, 0, &mmVM_INVALIDATE_ENG4_SEM[0], sizeof(mmVM_INVALIDATE_ENG4_SEM)/sizeof(mmVM_INVALIDATE_ENG4_SEM[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG5_SEM", REG_MMIO, 0x0896, 0, &mmVM_INVALIDATE_ENG5_SEM[0], sizeof(mmVM_INVALIDATE_ENG5_SEM)/sizeof(mmVM_INVALIDATE_ENG5_SEM[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG6_SEM", REG_MMIO, 0x0897, 0, &mmVM_INVALIDATE_ENG6_SEM[0], sizeof(mmVM_INVALIDATE_ENG6_SEM)/sizeof(mmVM_INVALIDATE_ENG6_SEM[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG7_SEM", REG_MMIO, 0x0898, 0, &mmVM_INVALIDATE_ENG7_SEM[0], sizeof(mmVM_INVALIDATE_ENG7_SEM)/sizeof(mmVM_INVALIDATE_ENG7_SEM[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG8_SEM", REG_MMIO, 0x0899, 0, &mmVM_INVALIDATE_ENG8_SEM[0], sizeof(mmVM_INVALIDATE_ENG8_SEM)/sizeof(mmVM_INVALIDATE_ENG8_SEM[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG9_SEM", REG_MMIO, 0x089a, 0, &mmVM_INVALIDATE_ENG9_SEM[0], sizeof(mmVM_INVALIDATE_ENG9_SEM)/sizeof(mmVM_INVALIDATE_ENG9_SEM[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG10_SEM", REG_MMIO, 0x089b, 0, &mmVM_INVALIDATE_ENG10_SEM[0], sizeof(mmVM_INVALIDATE_ENG10_SEM)/sizeof(mmVM_INVALIDATE_ENG10_SEM[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG11_SEM", REG_MMIO, 0x089c, 0, &mmVM_INVALIDATE_ENG11_SEM[0], sizeof(mmVM_INVALIDATE_ENG11_SEM)/sizeof(mmVM_INVALIDATE_ENG11_SEM[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG12_SEM", REG_MMIO, 0x089d, 0, &mmVM_INVALIDATE_ENG12_SEM[0], sizeof(mmVM_INVALIDATE_ENG12_SEM)/sizeof(mmVM_INVALIDATE_ENG12_SEM[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG13_SEM", REG_MMIO, 0x089e, 0, &mmVM_INVALIDATE_ENG13_SEM[0], sizeof(mmVM_INVALIDATE_ENG13_SEM)/sizeof(mmVM_INVALIDATE_ENG13_SEM[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG14_SEM", REG_MMIO, 0x089f, 0, &mmVM_INVALIDATE_ENG14_SEM[0], sizeof(mmVM_INVALIDATE_ENG14_SEM)/sizeof(mmVM_INVALIDATE_ENG14_SEM[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG15_SEM", REG_MMIO, 0x08a0, 0, &mmVM_INVALIDATE_ENG15_SEM[0], sizeof(mmVM_INVALIDATE_ENG15_SEM)/sizeof(mmVM_INVALIDATE_ENG15_SEM[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG16_SEM", REG_MMIO, 0x08a1, 0, &mmVM_INVALIDATE_ENG16_SEM[0], sizeof(mmVM_INVALIDATE_ENG16_SEM)/sizeof(mmVM_INVALIDATE_ENG16_SEM[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG17_SEM", REG_MMIO, 0x08a2, 0, &mmVM_INVALIDATE_ENG17_SEM[0], sizeof(mmVM_INVALIDATE_ENG17_SEM)/sizeof(mmVM_INVALIDATE_ENG17_SEM[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG0_REQ", REG_MMIO, 0x08a3, 0, &mmVM_INVALIDATE_ENG0_REQ[0], sizeof(mmVM_INVALIDATE_ENG0_REQ)/sizeof(mmVM_INVALIDATE_ENG0_REQ[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG1_REQ", REG_MMIO, 0x08a4, 0, &mmVM_INVALIDATE_ENG1_REQ[0], sizeof(mmVM_INVALIDATE_ENG1_REQ)/sizeof(mmVM_INVALIDATE_ENG1_REQ[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG2_REQ", REG_MMIO, 0x08a5, 0, &mmVM_INVALIDATE_ENG2_REQ[0], sizeof(mmVM_INVALIDATE_ENG2_REQ)/sizeof(mmVM_INVALIDATE_ENG2_REQ[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG3_REQ", REG_MMIO, 0x08a6, 0, &mmVM_INVALIDATE_ENG3_REQ[0], sizeof(mmVM_INVALIDATE_ENG3_REQ)/sizeof(mmVM_INVALIDATE_ENG3_REQ[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG4_REQ", REG_MMIO, 0x08a7, 0, &mmVM_INVALIDATE_ENG4_REQ[0], sizeof(mmVM_INVALIDATE_ENG4_REQ)/sizeof(mmVM_INVALIDATE_ENG4_REQ[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG5_REQ", REG_MMIO, 0x08a8, 0, &mmVM_INVALIDATE_ENG5_REQ[0], sizeof(mmVM_INVALIDATE_ENG5_REQ)/sizeof(mmVM_INVALIDATE_ENG5_REQ[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG6_REQ", REG_MMIO, 0x08a9, 0, &mmVM_INVALIDATE_ENG6_REQ[0], sizeof(mmVM_INVALIDATE_ENG6_REQ)/sizeof(mmVM_INVALIDATE_ENG6_REQ[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG7_REQ", REG_MMIO, 0x08aa, 0, &mmVM_INVALIDATE_ENG7_REQ[0], sizeof(mmVM_INVALIDATE_ENG7_REQ)/sizeof(mmVM_INVALIDATE_ENG7_REQ[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG8_REQ", REG_MMIO, 0x08ab, 0, &mmVM_INVALIDATE_ENG8_REQ[0], sizeof(mmVM_INVALIDATE_ENG8_REQ)/sizeof(mmVM_INVALIDATE_ENG8_REQ[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG9_REQ", REG_MMIO, 0x08ac, 0, &mmVM_INVALIDATE_ENG9_REQ[0], sizeof(mmVM_INVALIDATE_ENG9_REQ)/sizeof(mmVM_INVALIDATE_ENG9_REQ[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG10_REQ", REG_MMIO, 0x08ad, 0, &mmVM_INVALIDATE_ENG10_REQ[0], sizeof(mmVM_INVALIDATE_ENG10_REQ)/sizeof(mmVM_INVALIDATE_ENG10_REQ[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG11_REQ", REG_MMIO, 0x08ae, 0, &mmVM_INVALIDATE_ENG11_REQ[0], sizeof(mmVM_INVALIDATE_ENG11_REQ)/sizeof(mmVM_INVALIDATE_ENG11_REQ[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG12_REQ", REG_MMIO, 0x08af, 0, &mmVM_INVALIDATE_ENG12_REQ[0], sizeof(mmVM_INVALIDATE_ENG12_REQ)/sizeof(mmVM_INVALIDATE_ENG12_REQ[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG13_REQ", REG_MMIO, 0x08b0, 0, &mmVM_INVALIDATE_ENG13_REQ[0], sizeof(mmVM_INVALIDATE_ENG13_REQ)/sizeof(mmVM_INVALIDATE_ENG13_REQ[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG14_REQ", REG_MMIO, 0x08b1, 0, &mmVM_INVALIDATE_ENG14_REQ[0], sizeof(mmVM_INVALIDATE_ENG14_REQ)/sizeof(mmVM_INVALIDATE_ENG14_REQ[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG15_REQ", REG_MMIO, 0x08b2, 0, &mmVM_INVALIDATE_ENG15_REQ[0], sizeof(mmVM_INVALIDATE_ENG15_REQ)/sizeof(mmVM_INVALIDATE_ENG15_REQ[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG16_REQ", REG_MMIO, 0x08b3, 0, &mmVM_INVALIDATE_ENG16_REQ[0], sizeof(mmVM_INVALIDATE_ENG16_REQ)/sizeof(mmVM_INVALIDATE_ENG16_REQ[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG17_REQ", REG_MMIO, 0x08b4, 0, &mmVM_INVALIDATE_ENG17_REQ[0], sizeof(mmVM_INVALIDATE_ENG17_REQ)/sizeof(mmVM_INVALIDATE_ENG17_REQ[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG0_ACK", REG_MMIO, 0x08b5, 0, &mmVM_INVALIDATE_ENG0_ACK[0], sizeof(mmVM_INVALIDATE_ENG0_ACK)/sizeof(mmVM_INVALIDATE_ENG0_ACK[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG1_ACK", REG_MMIO, 0x08b6, 0, &mmVM_INVALIDATE_ENG1_ACK[0], sizeof(mmVM_INVALIDATE_ENG1_ACK)/sizeof(mmVM_INVALIDATE_ENG1_ACK[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG2_ACK", REG_MMIO, 0x08b7, 0, &mmVM_INVALIDATE_ENG2_ACK[0], sizeof(mmVM_INVALIDATE_ENG2_ACK)/sizeof(mmVM_INVALIDATE_ENG2_ACK[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG3_ACK", REG_MMIO, 0x08b8, 0, &mmVM_INVALIDATE_ENG3_ACK[0], sizeof(mmVM_INVALIDATE_ENG3_ACK)/sizeof(mmVM_INVALIDATE_ENG3_ACK[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG4_ACK", REG_MMIO, 0x08b9, 0, &mmVM_INVALIDATE_ENG4_ACK[0], sizeof(mmVM_INVALIDATE_ENG4_ACK)/sizeof(mmVM_INVALIDATE_ENG4_ACK[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG5_ACK", REG_MMIO, 0x08ba, 0, &mmVM_INVALIDATE_ENG5_ACK[0], sizeof(mmVM_INVALIDATE_ENG5_ACK)/sizeof(mmVM_INVALIDATE_ENG5_ACK[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG6_ACK", REG_MMIO, 0x08bb, 0, &mmVM_INVALIDATE_ENG6_ACK[0], sizeof(mmVM_INVALIDATE_ENG6_ACK)/sizeof(mmVM_INVALIDATE_ENG6_ACK[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG7_ACK", REG_MMIO, 0x08bc, 0, &mmVM_INVALIDATE_ENG7_ACK[0], sizeof(mmVM_INVALIDATE_ENG7_ACK)/sizeof(mmVM_INVALIDATE_ENG7_ACK[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG8_ACK", REG_MMIO, 0x08bd, 0, &mmVM_INVALIDATE_ENG8_ACK[0], sizeof(mmVM_INVALIDATE_ENG8_ACK)/sizeof(mmVM_INVALIDATE_ENG8_ACK[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG9_ACK", REG_MMIO, 0x08be, 0, &mmVM_INVALIDATE_ENG9_ACK[0], sizeof(mmVM_INVALIDATE_ENG9_ACK)/sizeof(mmVM_INVALIDATE_ENG9_ACK[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG10_ACK", REG_MMIO, 0x08bf, 0, &mmVM_INVALIDATE_ENG10_ACK[0], sizeof(mmVM_INVALIDATE_ENG10_ACK)/sizeof(mmVM_INVALIDATE_ENG10_ACK[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG11_ACK", REG_MMIO, 0x08c0, 0, &mmVM_INVALIDATE_ENG11_ACK[0], sizeof(mmVM_INVALIDATE_ENG11_ACK)/sizeof(mmVM_INVALIDATE_ENG11_ACK[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG12_ACK", REG_MMIO, 0x08c1, 0, &mmVM_INVALIDATE_ENG12_ACK[0], sizeof(mmVM_INVALIDATE_ENG12_ACK)/sizeof(mmVM_INVALIDATE_ENG12_ACK[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG13_ACK", REG_MMIO, 0x08c2, 0, &mmVM_INVALIDATE_ENG13_ACK[0], sizeof(mmVM_INVALIDATE_ENG13_ACK)/sizeof(mmVM_INVALIDATE_ENG13_ACK[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG14_ACK", REG_MMIO, 0x08c3, 0, &mmVM_INVALIDATE_ENG14_ACK[0], sizeof(mmVM_INVALIDATE_ENG14_ACK)/sizeof(mmVM_INVALIDATE_ENG14_ACK[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG15_ACK", REG_MMIO, 0x08c4, 0, &mmVM_INVALIDATE_ENG15_ACK[0], sizeof(mmVM_INVALIDATE_ENG15_ACK)/sizeof(mmVM_INVALIDATE_ENG15_ACK[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG16_ACK", REG_MMIO, 0x08c5, 0, &mmVM_INVALIDATE_ENG16_ACK[0], sizeof(mmVM_INVALIDATE_ENG16_ACK)/sizeof(mmVM_INVALIDATE_ENG16_ACK[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG17_ACK", REG_MMIO, 0x08c6, 0, &mmVM_INVALIDATE_ENG17_ACK[0], sizeof(mmVM_INVALIDATE_ENG17_ACK)/sizeof(mmVM_INVALIDATE_ENG17_ACK[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32", REG_MMIO, 0x08c7, 0, &mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32[0], sizeof(mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32)/sizeof(mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32", REG_MMIO, 0x08c8, 0, &mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32[0], sizeof(mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32)/sizeof(mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32", REG_MMIO, 0x08c9, 0, &mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32[0], sizeof(mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32)/sizeof(mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG1_ADDR_RANGE_HI32", REG_MMIO, 0x08ca, 0, &mmVM_INVALIDATE_ENG1_ADDR_RANGE_HI32[0], sizeof(mmVM_INVALIDATE_ENG1_ADDR_RANGE_HI32)/sizeof(mmVM_INVALIDATE_ENG1_ADDR_RANGE_HI32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG2_ADDR_RANGE_LO32", REG_MMIO, 0x08cb, 0, &mmVM_INVALIDATE_ENG2_ADDR_RANGE_LO32[0], sizeof(mmVM_INVALIDATE_ENG2_ADDR_RANGE_LO32)/sizeof(mmVM_INVALIDATE_ENG2_ADDR_RANGE_LO32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG2_ADDR_RANGE_HI32", REG_MMIO, 0x08cc, 0, &mmVM_INVALIDATE_ENG2_ADDR_RANGE_HI32[0], sizeof(mmVM_INVALIDATE_ENG2_ADDR_RANGE_HI32)/sizeof(mmVM_INVALIDATE_ENG2_ADDR_RANGE_HI32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG3_ADDR_RANGE_LO32", REG_MMIO, 0x08cd, 0, &mmVM_INVALIDATE_ENG3_ADDR_RANGE_LO32[0], sizeof(mmVM_INVALIDATE_ENG3_ADDR_RANGE_LO32)/sizeof(mmVM_INVALIDATE_ENG3_ADDR_RANGE_LO32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG3_ADDR_RANGE_HI32", REG_MMIO, 0x08ce, 0, &mmVM_INVALIDATE_ENG3_ADDR_RANGE_HI32[0], sizeof(mmVM_INVALIDATE_ENG3_ADDR_RANGE_HI32)/sizeof(mmVM_INVALIDATE_ENG3_ADDR_RANGE_HI32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG4_ADDR_RANGE_LO32", REG_MMIO, 0x08cf, 0, &mmVM_INVALIDATE_ENG4_ADDR_RANGE_LO32[0], sizeof(mmVM_INVALIDATE_ENG4_ADDR_RANGE_LO32)/sizeof(mmVM_INVALIDATE_ENG4_ADDR_RANGE_LO32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG4_ADDR_RANGE_HI32", REG_MMIO, 0x08d0, 0, &mmVM_INVALIDATE_ENG4_ADDR_RANGE_HI32[0], sizeof(mmVM_INVALIDATE_ENG4_ADDR_RANGE_HI32)/sizeof(mmVM_INVALIDATE_ENG4_ADDR_RANGE_HI32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG5_ADDR_RANGE_LO32", REG_MMIO, 0x08d1, 0, &mmVM_INVALIDATE_ENG5_ADDR_RANGE_LO32[0], sizeof(mmVM_INVALIDATE_ENG5_ADDR_RANGE_LO32)/sizeof(mmVM_INVALIDATE_ENG5_ADDR_RANGE_LO32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG5_ADDR_RANGE_HI32", REG_MMIO, 0x08d2, 0, &mmVM_INVALIDATE_ENG5_ADDR_RANGE_HI32[0], sizeof(mmVM_INVALIDATE_ENG5_ADDR_RANGE_HI32)/sizeof(mmVM_INVALIDATE_ENG5_ADDR_RANGE_HI32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG6_ADDR_RANGE_LO32", REG_MMIO, 0x08d3, 0, &mmVM_INVALIDATE_ENG6_ADDR_RANGE_LO32[0], sizeof(mmVM_INVALIDATE_ENG6_ADDR_RANGE_LO32)/sizeof(mmVM_INVALIDATE_ENG6_ADDR_RANGE_LO32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG6_ADDR_RANGE_HI32", REG_MMIO, 0x08d4, 0, &mmVM_INVALIDATE_ENG6_ADDR_RANGE_HI32[0], sizeof(mmVM_INVALIDATE_ENG6_ADDR_RANGE_HI32)/sizeof(mmVM_INVALIDATE_ENG6_ADDR_RANGE_HI32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG7_ADDR_RANGE_LO32", REG_MMIO, 0x08d5, 0, &mmVM_INVALIDATE_ENG7_ADDR_RANGE_LO32[0], sizeof(mmVM_INVALIDATE_ENG7_ADDR_RANGE_LO32)/sizeof(mmVM_INVALIDATE_ENG7_ADDR_RANGE_LO32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG7_ADDR_RANGE_HI32", REG_MMIO, 0x08d6, 0, &mmVM_INVALIDATE_ENG7_ADDR_RANGE_HI32[0], sizeof(mmVM_INVALIDATE_ENG7_ADDR_RANGE_HI32)/sizeof(mmVM_INVALIDATE_ENG7_ADDR_RANGE_HI32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG8_ADDR_RANGE_LO32", REG_MMIO, 0x08d7, 0, &mmVM_INVALIDATE_ENG8_ADDR_RANGE_LO32[0], sizeof(mmVM_INVALIDATE_ENG8_ADDR_RANGE_LO32)/sizeof(mmVM_INVALIDATE_ENG8_ADDR_RANGE_LO32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG8_ADDR_RANGE_HI32", REG_MMIO, 0x08d8, 0, &mmVM_INVALIDATE_ENG8_ADDR_RANGE_HI32[0], sizeof(mmVM_INVALIDATE_ENG8_ADDR_RANGE_HI32)/sizeof(mmVM_INVALIDATE_ENG8_ADDR_RANGE_HI32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG9_ADDR_RANGE_LO32", REG_MMIO, 0x08d9, 0, &mmVM_INVALIDATE_ENG9_ADDR_RANGE_LO32[0], sizeof(mmVM_INVALIDATE_ENG9_ADDR_RANGE_LO32)/sizeof(mmVM_INVALIDATE_ENG9_ADDR_RANGE_LO32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG9_ADDR_RANGE_HI32", REG_MMIO, 0x08da, 0, &mmVM_INVALIDATE_ENG9_ADDR_RANGE_HI32[0], sizeof(mmVM_INVALIDATE_ENG9_ADDR_RANGE_HI32)/sizeof(mmVM_INVALIDATE_ENG9_ADDR_RANGE_HI32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG10_ADDR_RANGE_LO32", REG_MMIO, 0x08db, 0, &mmVM_INVALIDATE_ENG10_ADDR_RANGE_LO32[0], sizeof(mmVM_INVALIDATE_ENG10_ADDR_RANGE_LO32)/sizeof(mmVM_INVALIDATE_ENG10_ADDR_RANGE_LO32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG10_ADDR_RANGE_HI32", REG_MMIO, 0x08dc, 0, &mmVM_INVALIDATE_ENG10_ADDR_RANGE_HI32[0], sizeof(mmVM_INVALIDATE_ENG10_ADDR_RANGE_HI32)/sizeof(mmVM_INVALIDATE_ENG10_ADDR_RANGE_HI32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG11_ADDR_RANGE_LO32", REG_MMIO, 0x08dd, 0, &mmVM_INVALIDATE_ENG11_ADDR_RANGE_LO32[0], sizeof(mmVM_INVALIDATE_ENG11_ADDR_RANGE_LO32)/sizeof(mmVM_INVALIDATE_ENG11_ADDR_RANGE_LO32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG11_ADDR_RANGE_HI32", REG_MMIO, 0x08de, 0, &mmVM_INVALIDATE_ENG11_ADDR_RANGE_HI32[0], sizeof(mmVM_INVALIDATE_ENG11_ADDR_RANGE_HI32)/sizeof(mmVM_INVALIDATE_ENG11_ADDR_RANGE_HI32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG12_ADDR_RANGE_LO32", REG_MMIO, 0x08df, 0, &mmVM_INVALIDATE_ENG12_ADDR_RANGE_LO32[0], sizeof(mmVM_INVALIDATE_ENG12_ADDR_RANGE_LO32)/sizeof(mmVM_INVALIDATE_ENG12_ADDR_RANGE_LO32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG12_ADDR_RANGE_HI32", REG_MMIO, 0x08e0, 0, &mmVM_INVALIDATE_ENG12_ADDR_RANGE_HI32[0], sizeof(mmVM_INVALIDATE_ENG12_ADDR_RANGE_HI32)/sizeof(mmVM_INVALIDATE_ENG12_ADDR_RANGE_HI32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG13_ADDR_RANGE_LO32", REG_MMIO, 0x08e1, 0, &mmVM_INVALIDATE_ENG13_ADDR_RANGE_LO32[0], sizeof(mmVM_INVALIDATE_ENG13_ADDR_RANGE_LO32)/sizeof(mmVM_INVALIDATE_ENG13_ADDR_RANGE_LO32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG13_ADDR_RANGE_HI32", REG_MMIO, 0x08e2, 0, &mmVM_INVALIDATE_ENG13_ADDR_RANGE_HI32[0], sizeof(mmVM_INVALIDATE_ENG13_ADDR_RANGE_HI32)/sizeof(mmVM_INVALIDATE_ENG13_ADDR_RANGE_HI32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG14_ADDR_RANGE_LO32", REG_MMIO, 0x08e3, 0, &mmVM_INVALIDATE_ENG14_ADDR_RANGE_LO32[0], sizeof(mmVM_INVALIDATE_ENG14_ADDR_RANGE_LO32)/sizeof(mmVM_INVALIDATE_ENG14_ADDR_RANGE_LO32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG14_ADDR_RANGE_HI32", REG_MMIO, 0x08e4, 0, &mmVM_INVALIDATE_ENG14_ADDR_RANGE_HI32[0], sizeof(mmVM_INVALIDATE_ENG14_ADDR_RANGE_HI32)/sizeof(mmVM_INVALIDATE_ENG14_ADDR_RANGE_HI32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG15_ADDR_RANGE_LO32", REG_MMIO, 0x08e5, 0, &mmVM_INVALIDATE_ENG15_ADDR_RANGE_LO32[0], sizeof(mmVM_INVALIDATE_ENG15_ADDR_RANGE_LO32)/sizeof(mmVM_INVALIDATE_ENG15_ADDR_RANGE_LO32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG15_ADDR_RANGE_HI32", REG_MMIO, 0x08e6, 0, &mmVM_INVALIDATE_ENG15_ADDR_RANGE_HI32[0], sizeof(mmVM_INVALIDATE_ENG15_ADDR_RANGE_HI32)/sizeof(mmVM_INVALIDATE_ENG15_ADDR_RANGE_HI32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG16_ADDR_RANGE_LO32", REG_MMIO, 0x08e7, 0, &mmVM_INVALIDATE_ENG16_ADDR_RANGE_LO32[0], sizeof(mmVM_INVALIDATE_ENG16_ADDR_RANGE_LO32)/sizeof(mmVM_INVALIDATE_ENG16_ADDR_RANGE_LO32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG16_ADDR_RANGE_HI32", REG_MMIO, 0x08e8, 0, &mmVM_INVALIDATE_ENG16_ADDR_RANGE_HI32[0], sizeof(mmVM_INVALIDATE_ENG16_ADDR_RANGE_HI32)/sizeof(mmVM_INVALIDATE_ENG16_ADDR_RANGE_HI32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG17_ADDR_RANGE_LO32", REG_MMIO, 0x08e9, 0, &mmVM_INVALIDATE_ENG17_ADDR_RANGE_LO32[0], sizeof(mmVM_INVALIDATE_ENG17_ADDR_RANGE_LO32)/sizeof(mmVM_INVALIDATE_ENG17_ADDR_RANGE_LO32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG17_ADDR_RANGE_HI32", REG_MMIO, 0x08ea, 0, &mmVM_INVALIDATE_ENG17_ADDR_RANGE_HI32[0], sizeof(mmVM_INVALIDATE_ENG17_ADDR_RANGE_HI32)/sizeof(mmVM_INVALIDATE_ENG17_ADDR_RANGE_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32", REG_MMIO, 0x08eb, 0, &mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32[0], sizeof(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32)/sizeof(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32", REG_MMIO, 0x08ec, 0, &mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32[0], sizeof(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32)/sizeof(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32", REG_MMIO, 0x08ed, 0, &mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32[0], sizeof(mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32)/sizeof(mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32", REG_MMIO, 0x08ee, 0, &mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32[0], sizeof(mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32)/sizeof(mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32", REG_MMIO, 0x08ef, 0, &mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32[0], sizeof(mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32)/sizeof(mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32", REG_MMIO, 0x08f0, 0, &mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32[0], sizeof(mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32)/sizeof(mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32", REG_MMIO, 0x08f1, 0, &mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32[0], sizeof(mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32)/sizeof(mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32", REG_MMIO, 0x08f2, 0, &mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32[0], sizeof(mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32)/sizeof(mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32", REG_MMIO, 0x08f3, 0, &mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32[0], sizeof(mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32)/sizeof(mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32", REG_MMIO, 0x08f4, 0, &mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32[0], sizeof(mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32)/sizeof(mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32", REG_MMIO, 0x08f5, 0, &mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32[0], sizeof(mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32)/sizeof(mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32", REG_MMIO, 0x08f6, 0, &mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32[0], sizeof(mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32)/sizeof(mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32", REG_MMIO, 0x08f7, 0, &mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32[0], sizeof(mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32)/sizeof(mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32", REG_MMIO, 0x08f8, 0, &mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32[0], sizeof(mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32)/sizeof(mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32", REG_MMIO, 0x08f9, 0, &mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32[0], sizeof(mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32)/sizeof(mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32", REG_MMIO, 0x08fa, 0, &mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32[0], sizeof(mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32)/sizeof(mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32", REG_MMIO, 0x08fb, 0, &mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32[0], sizeof(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32)/sizeof(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32", REG_MMIO, 0x08fc, 0, &mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32[0], sizeof(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32)/sizeof(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32", REG_MMIO, 0x08fd, 0, &mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32[0], sizeof(mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32)/sizeof(mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32", REG_MMIO, 0x08fe, 0, &mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32[0], sizeof(mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32)/sizeof(mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32", REG_MMIO, 0x08ff, 0, &mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32[0], sizeof(mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32)/sizeof(mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32", REG_MMIO, 0x0900, 0, &mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32[0], sizeof(mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32)/sizeof(mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32", REG_MMIO, 0x0901, 0, &mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32[0], sizeof(mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32)/sizeof(mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32", REG_MMIO, 0x0902, 0, &mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32[0], sizeof(mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32)/sizeof(mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32", REG_MMIO, 0x0903, 0, &mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32[0], sizeof(mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32)/sizeof(mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32", REG_MMIO, 0x0904, 0, &mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32[0], sizeof(mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32)/sizeof(mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32", REG_MMIO, 0x0905, 0, &mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32[0], sizeof(mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32)/sizeof(mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32", REG_MMIO, 0x0906, 0, &mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32[0], sizeof(mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32)/sizeof(mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32", REG_MMIO, 0x0907, 0, &mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32[0], sizeof(mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32)/sizeof(mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32", REG_MMIO, 0x0908, 0, &mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32[0], sizeof(mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32)/sizeof(mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32", REG_MMIO, 0x0909, 0, &mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32[0], sizeof(mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32)/sizeof(mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32", REG_MMIO, 0x090a, 0, &mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32[0], sizeof(mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32)/sizeof(mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32", REG_MMIO, 0x090b, 0, &mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32[0], sizeof(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32)/sizeof(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32", REG_MMIO, 0x090c, 0, &mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32[0], sizeof(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32)/sizeof(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32", REG_MMIO, 0x090d, 0, &mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32[0], sizeof(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32)/sizeof(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32", REG_MMIO, 0x090e, 0, &mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32[0], sizeof(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32)/sizeof(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32", REG_MMIO, 0x090f, 0, &mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32[0], sizeof(mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32)/sizeof(mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32", REG_MMIO, 0x0910, 0, &mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32[0], sizeof(mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32)/sizeof(mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32", REG_MMIO, 0x0911, 0, &mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32[0], sizeof(mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32)/sizeof(mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32", REG_MMIO, 0x0912, 0, &mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32[0], sizeof(mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32)/sizeof(mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32", REG_MMIO, 0x0913, 0, &mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32[0], sizeof(mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32)/sizeof(mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32", REG_MMIO, 0x0914, 0, &mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32[0], sizeof(mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32)/sizeof(mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32", REG_MMIO, 0x0915, 0, &mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32[0], sizeof(mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32)/sizeof(mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32", REG_MMIO, 0x0916, 0, &mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32[0], sizeof(mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32)/sizeof(mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32", REG_MMIO, 0x0917, 0, &mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32[0], sizeof(mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32)/sizeof(mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32", REG_MMIO, 0x0918, 0, &mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32[0], sizeof(mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32)/sizeof(mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32", REG_MMIO, 0x0919, 0, &mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32[0], sizeof(mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32)/sizeof(mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32", REG_MMIO, 0x091a, 0, &mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32[0], sizeof(mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32)/sizeof(mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32", REG_MMIO, 0x091b, 0, &mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32[0], sizeof(mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32)/sizeof(mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32", REG_MMIO, 0x091c, 0, &mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32[0], sizeof(mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32)/sizeof(mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32", REG_MMIO, 0x091d, 0, &mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32[0], sizeof(mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32)/sizeof(mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32", REG_MMIO, 0x091e, 0, &mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32[0], sizeof(mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32)/sizeof(mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32", REG_MMIO, 0x091f, 0, &mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32[0], sizeof(mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32)/sizeof(mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32", REG_MMIO, 0x0920, 0, &mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32[0], sizeof(mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32)/sizeof(mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32", REG_MMIO, 0x0921, 0, &mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32[0], sizeof(mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32)/sizeof(mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32", REG_MMIO, 0x0922, 0, &mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32[0], sizeof(mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32)/sizeof(mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32", REG_MMIO, 0x0923, 0, &mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32[0], sizeof(mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32)/sizeof(mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32", REG_MMIO, 0x0924, 0, &mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32[0], sizeof(mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32)/sizeof(mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32", REG_MMIO, 0x0925, 0, &mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32[0], sizeof(mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32)/sizeof(mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32", REG_MMIO, 0x0926, 0, &mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32[0], sizeof(mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32)/sizeof(mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32", REG_MMIO, 0x0927, 0, &mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32[0], sizeof(mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32)/sizeof(mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32", REG_MMIO, 0x0928, 0, &mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32[0], sizeof(mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32)/sizeof(mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32", REG_MMIO, 0x0929, 0, &mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32[0], sizeof(mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32)/sizeof(mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32", REG_MMIO, 0x092a, 0, &mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32[0], sizeof(mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32)/sizeof(mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32", REG_MMIO, 0x092b, 0, &mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32[0], sizeof(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32)/sizeof(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32", REG_MMIO, 0x092c, 0, &mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32[0], sizeof(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32)/sizeof(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32", REG_MMIO, 0x092d, 0, &mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32[0], sizeof(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32)/sizeof(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32", REG_MMIO, 0x092e, 0, &mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32[0], sizeof(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32)/sizeof(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32", REG_MMIO, 0x092f, 0, &mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32[0], sizeof(mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32)/sizeof(mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32", REG_MMIO, 0x0930, 0, &mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32[0], sizeof(mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32)/sizeof(mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32", REG_MMIO, 0x0931, 0, &mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32[0], sizeof(mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32)/sizeof(mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32", REG_MMIO, 0x0932, 0, &mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32[0], sizeof(mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32)/sizeof(mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32", REG_MMIO, 0x0933, 0, &mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32[0], sizeof(mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32)/sizeof(mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32", REG_MMIO, 0x0934, 0, &mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32[0], sizeof(mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32)/sizeof(mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32", REG_MMIO, 0x0935, 0, &mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32[0], sizeof(mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32)/sizeof(mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32", REG_MMIO, 0x0936, 0, &mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32[0], sizeof(mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32)/sizeof(mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32", REG_MMIO, 0x0937, 0, &mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32[0], sizeof(mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32)/sizeof(mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32", REG_MMIO, 0x0938, 0, &mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32[0], sizeof(mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32)/sizeof(mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32", REG_MMIO, 0x0939, 0, &mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32[0], sizeof(mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32)/sizeof(mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32", REG_MMIO, 0x093a, 0, &mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32[0], sizeof(mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32)/sizeof(mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32", REG_MMIO, 0x093b, 0, &mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32[0], sizeof(mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32)/sizeof(mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32", REG_MMIO, 0x093c, 0, &mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32[0], sizeof(mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32)/sizeof(mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32", REG_MMIO, 0x093d, 0, &mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32[0], sizeof(mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32)/sizeof(mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32", REG_MMIO, 0x093e, 0, &mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32[0], sizeof(mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32)/sizeof(mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32", REG_MMIO, 0x093f, 0, &mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32[0], sizeof(mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32)/sizeof(mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32", REG_MMIO, 0x0940, 0, &mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32[0], sizeof(mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32)/sizeof(mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32", REG_MMIO, 0x0941, 0, &mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32[0], sizeof(mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32)/sizeof(mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32", REG_MMIO, 0x0942, 0, &mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32[0], sizeof(mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32)/sizeof(mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32", REG_MMIO, 0x0943, 0, &mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32[0], sizeof(mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32)/sizeof(mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32", REG_MMIO, 0x0944, 0, &mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32[0], sizeof(mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32)/sizeof(mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32", REG_MMIO, 0x0945, 0, &mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32[0], sizeof(mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32)/sizeof(mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32", REG_MMIO, 0x0946, 0, &mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32[0], sizeof(mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32)/sizeof(mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32", REG_MMIO, 0x0947, 0, &mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32[0], sizeof(mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32)/sizeof(mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32", REG_MMIO, 0x0948, 0, &mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32[0], sizeof(mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32)/sizeof(mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32", REG_MMIO, 0x0949, 0, &mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32[0], sizeof(mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32)/sizeof(mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32", REG_MMIO, 0x094a, 0, &mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32[0], sizeof(mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32)/sizeof(mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32[0]), 0, 0 }, + { "mmMC_VM_NB_MMIOBASE", REG_MMIO, 0x0964, 0, &mmMC_VM_NB_MMIOBASE[0], sizeof(mmMC_VM_NB_MMIOBASE)/sizeof(mmMC_VM_NB_MMIOBASE[0]), 0, 0 }, + { "mmMC_VM_NB_MMIOLIMIT", REG_MMIO, 0x0965, 0, &mmMC_VM_NB_MMIOLIMIT[0], sizeof(mmMC_VM_NB_MMIOLIMIT)/sizeof(mmMC_VM_NB_MMIOLIMIT[0]), 0, 0 }, + { "mmMC_VM_NB_PCI_CTRL", REG_MMIO, 0x0966, 0, &mmMC_VM_NB_PCI_CTRL[0], sizeof(mmMC_VM_NB_PCI_CTRL)/sizeof(mmMC_VM_NB_PCI_CTRL[0]), 0, 0 }, + { "mmMC_VM_NB_PCI_ARB", REG_MMIO, 0x0967, 0, &mmMC_VM_NB_PCI_ARB[0], sizeof(mmMC_VM_NB_PCI_ARB)/sizeof(mmMC_VM_NB_PCI_ARB[0]), 0, 0 }, + { "mmMC_VM_NB_TOP_OF_DRAM_SLOT1", REG_MMIO, 0x0968, 0, &mmMC_VM_NB_TOP_OF_DRAM_SLOT1[0], sizeof(mmMC_VM_NB_TOP_OF_DRAM_SLOT1)/sizeof(mmMC_VM_NB_TOP_OF_DRAM_SLOT1[0]), 0, 0 }, + { "mmMC_VM_NB_LOWER_TOP_OF_DRAM2", REG_MMIO, 0x0969, 0, &mmMC_VM_NB_LOWER_TOP_OF_DRAM2[0], sizeof(mmMC_VM_NB_LOWER_TOP_OF_DRAM2)/sizeof(mmMC_VM_NB_LOWER_TOP_OF_DRAM2[0]), 0, 0 }, + { "mmMC_VM_NB_UPPER_TOP_OF_DRAM2", REG_MMIO, 0x096a, 0, &mmMC_VM_NB_UPPER_TOP_OF_DRAM2[0], sizeof(mmMC_VM_NB_UPPER_TOP_OF_DRAM2)/sizeof(mmMC_VM_NB_UPPER_TOP_OF_DRAM2[0]), 0, 0 }, + { "mmMC_VM_FB_OFFSET", REG_MMIO, 0x096b, 0, &mmMC_VM_FB_OFFSET[0], sizeof(mmMC_VM_FB_OFFSET)/sizeof(mmMC_VM_FB_OFFSET[0]), 0, 0 }, + { "mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB", REG_MMIO, 0x096c, 0, &mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB[0], sizeof(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB)/sizeof(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB[0]), 0, 0 }, + { "mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB", REG_MMIO, 0x096d, 0, &mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB[0], sizeof(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB)/sizeof(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB[0]), 0, 0 }, + { "mmMC_VM_STEERING", REG_MMIO, 0x096e, 0, &mmMC_VM_STEERING[0], sizeof(mmMC_VM_STEERING)/sizeof(mmMC_VM_STEERING[0]), 0, 0 }, + { "mmMC_SHARED_VIRT_RESET_REQ", REG_MMIO, 0x096f, 0, &mmMC_SHARED_VIRT_RESET_REQ[0], sizeof(mmMC_SHARED_VIRT_RESET_REQ)/sizeof(mmMC_SHARED_VIRT_RESET_REQ[0]), 0, 0 }, + { "mmMC_MEM_POWER_LS", REG_MMIO, 0x0970, 0, &mmMC_MEM_POWER_LS[0], sizeof(mmMC_MEM_POWER_LS)/sizeof(mmMC_MEM_POWER_LS[0]), 0, 0 }, + { "mmMC_VM_CACHEABLE_DRAM_ADDRESS_START", REG_MMIO, 0x0971, 0, &mmMC_VM_CACHEABLE_DRAM_ADDRESS_START[0], sizeof(mmMC_VM_CACHEABLE_DRAM_ADDRESS_START)/sizeof(mmMC_VM_CACHEABLE_DRAM_ADDRESS_START[0]), 0, 0 }, + { "mmMC_VM_CACHEABLE_DRAM_ADDRESS_END", REG_MMIO, 0x0972, 0, &mmMC_VM_CACHEABLE_DRAM_ADDRESS_END[0], sizeof(mmMC_VM_CACHEABLE_DRAM_ADDRESS_END)/sizeof(mmMC_VM_CACHEABLE_DRAM_ADDRESS_END[0]), 0, 0 }, + { "mmMC_VM_APT_CNTL", REG_MMIO, 0x0973, 0, &mmMC_VM_APT_CNTL[0], sizeof(mmMC_VM_APT_CNTL)/sizeof(mmMC_VM_APT_CNTL[0]), 0, 0 }, + { "mmMC_VM_LOCAL_HBM_ADDRESS_START", REG_MMIO, 0x0974, 0, &mmMC_VM_LOCAL_HBM_ADDRESS_START[0], sizeof(mmMC_VM_LOCAL_HBM_ADDRESS_START)/sizeof(mmMC_VM_LOCAL_HBM_ADDRESS_START[0]), 0, 0 }, + { "mmMC_VM_LOCAL_HBM_ADDRESS_END", REG_MMIO, 0x0975, 0, &mmMC_VM_LOCAL_HBM_ADDRESS_END[0], sizeof(mmMC_VM_LOCAL_HBM_ADDRESS_END)/sizeof(mmMC_VM_LOCAL_HBM_ADDRESS_END[0]), 0, 0 }, + { "mmMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL", REG_MMIO, 0x0976, 0, &mmMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL[0], sizeof(mmMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL)/sizeof(mmMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL[0]), 0, 0 }, + { "mmMC_VM_FB_LOCATION_BASE", REG_MMIO, 0x0980, 0, &mmMC_VM_FB_LOCATION_BASE[0], sizeof(mmMC_VM_FB_LOCATION_BASE)/sizeof(mmMC_VM_FB_LOCATION_BASE[0]), 0, 0 }, + { "mmMC_VM_FB_LOCATION_TOP", REG_MMIO, 0x0981, 0, &mmMC_VM_FB_LOCATION_TOP[0], sizeof(mmMC_VM_FB_LOCATION_TOP)/sizeof(mmMC_VM_FB_LOCATION_TOP[0]), 0, 0 }, + { "mmMC_VM_AGP_TOP", REG_MMIO, 0x0982, 0, &mmMC_VM_AGP_TOP[0], sizeof(mmMC_VM_AGP_TOP)/sizeof(mmMC_VM_AGP_TOP[0]), 0, 0 }, + { "mmMC_VM_AGP_BOT", REG_MMIO, 0x0983, 0, &mmMC_VM_AGP_BOT[0], sizeof(mmMC_VM_AGP_BOT)/sizeof(mmMC_VM_AGP_BOT[0]), 0, 0 }, + { "mmMC_VM_AGP_BASE", REG_MMIO, 0x0984, 0, &mmMC_VM_AGP_BASE[0], sizeof(mmMC_VM_AGP_BASE)/sizeof(mmMC_VM_AGP_BASE[0]), 0, 0 }, + { "mmMC_VM_SYSTEM_APERTURE_LOW_ADDR", REG_MMIO, 0x0985, 0, &mmMC_VM_SYSTEM_APERTURE_LOW_ADDR[0], sizeof(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR)/sizeof(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR[0]), 0, 0 }, + { "mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR", REG_MMIO, 0x0986, 0, &mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR[0], sizeof(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR)/sizeof(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR[0]), 0, 0 }, + { "mmMC_VM_MX_L1_TLB_CNTL", REG_MMIO, 0x0987, 0, &mmMC_VM_MX_L1_TLB_CNTL[0], sizeof(mmMC_VM_MX_L1_TLB_CNTL)/sizeof(mmMC_VM_MX_L1_TLB_CNTL[0]), 0, 0 }, + { "mmGCEA_DRAM_RD_CLI2GRP_MAP0", REG_MMIO, 0x0a00, 0, &mmGCEA_DRAM_RD_CLI2GRP_MAP0[0], sizeof(mmGCEA_DRAM_RD_CLI2GRP_MAP0)/sizeof(mmGCEA_DRAM_RD_CLI2GRP_MAP0[0]), 0, 0 }, + { "mmGCEA_DRAM_RD_CLI2GRP_MAP1", REG_MMIO, 0x0a01, 0, &mmGCEA_DRAM_RD_CLI2GRP_MAP1[0], sizeof(mmGCEA_DRAM_RD_CLI2GRP_MAP1)/sizeof(mmGCEA_DRAM_RD_CLI2GRP_MAP1[0]), 0, 0 }, + { "mmGCEA_DRAM_WR_CLI2GRP_MAP0", REG_MMIO, 0x0a02, 0, &mmGCEA_DRAM_WR_CLI2GRP_MAP0[0], sizeof(mmGCEA_DRAM_WR_CLI2GRP_MAP0)/sizeof(mmGCEA_DRAM_WR_CLI2GRP_MAP0[0]), 0, 0 }, + { "mmGCEA_DRAM_WR_CLI2GRP_MAP1", REG_MMIO, 0x0a03, 0, &mmGCEA_DRAM_WR_CLI2GRP_MAP1[0], sizeof(mmGCEA_DRAM_WR_CLI2GRP_MAP1)/sizeof(mmGCEA_DRAM_WR_CLI2GRP_MAP1[0]), 0, 0 }, + { "mmGCEA_DRAM_RD_GRP2VC_MAP", REG_MMIO, 0x0a04, 0, &mmGCEA_DRAM_RD_GRP2VC_MAP[0], sizeof(mmGCEA_DRAM_RD_GRP2VC_MAP)/sizeof(mmGCEA_DRAM_RD_GRP2VC_MAP[0]), 0, 0 }, + { "mmGCEA_DRAM_WR_GRP2VC_MAP", REG_MMIO, 0x0a05, 0, &mmGCEA_DRAM_WR_GRP2VC_MAP[0], sizeof(mmGCEA_DRAM_WR_GRP2VC_MAP)/sizeof(mmGCEA_DRAM_WR_GRP2VC_MAP[0]), 0, 0 }, + { "mmGCEA_DRAM_RD_LAZY", REG_MMIO, 0x0a06, 0, &mmGCEA_DRAM_RD_LAZY[0], sizeof(mmGCEA_DRAM_RD_LAZY)/sizeof(mmGCEA_DRAM_RD_LAZY[0]), 0, 0 }, + { "mmGCEA_DRAM_WR_LAZY", REG_MMIO, 0x0a07, 0, &mmGCEA_DRAM_WR_LAZY[0], sizeof(mmGCEA_DRAM_WR_LAZY)/sizeof(mmGCEA_DRAM_WR_LAZY[0]), 0, 0 }, + { "mmGCEA_DRAM_RD_CAM_CNTL", REG_MMIO, 0x0a08, 0, &mmGCEA_DRAM_RD_CAM_CNTL[0], sizeof(mmGCEA_DRAM_RD_CAM_CNTL)/sizeof(mmGCEA_DRAM_RD_CAM_CNTL[0]), 0, 0 }, + { "mmGCEA_DRAM_WR_CAM_CNTL", REG_MMIO, 0x0a09, 0, &mmGCEA_DRAM_WR_CAM_CNTL[0], sizeof(mmGCEA_DRAM_WR_CAM_CNTL)/sizeof(mmGCEA_DRAM_WR_CAM_CNTL[0]), 0, 0 }, + { "mmGCEA_DRAM_PAGE_BURST", REG_MMIO, 0x0a0a, 0, &mmGCEA_DRAM_PAGE_BURST[0], sizeof(mmGCEA_DRAM_PAGE_BURST)/sizeof(mmGCEA_DRAM_PAGE_BURST[0]), 0, 0 }, + { "mmGCEA_DRAM_RD_PRI_AGE", REG_MMIO, 0x0a0b, 0, &mmGCEA_DRAM_RD_PRI_AGE[0], sizeof(mmGCEA_DRAM_RD_PRI_AGE)/sizeof(mmGCEA_DRAM_RD_PRI_AGE[0]), 0, 0 }, + { "mmGCEA_DRAM_WR_PRI_AGE", REG_MMIO, 0x0a0c, 0, &mmGCEA_DRAM_WR_PRI_AGE[0], sizeof(mmGCEA_DRAM_WR_PRI_AGE)/sizeof(mmGCEA_DRAM_WR_PRI_AGE[0]), 0, 0 }, + { "mmGCEA_DRAM_RD_PRI_QUEUING", REG_MMIO, 0x0a0d, 0, &mmGCEA_DRAM_RD_PRI_QUEUING[0], sizeof(mmGCEA_DRAM_RD_PRI_QUEUING)/sizeof(mmGCEA_DRAM_RD_PRI_QUEUING[0]), 0, 0 }, + { "mmGCEA_DRAM_WR_PRI_QUEUING", REG_MMIO, 0x0a0e, 0, &mmGCEA_DRAM_WR_PRI_QUEUING[0], sizeof(mmGCEA_DRAM_WR_PRI_QUEUING)/sizeof(mmGCEA_DRAM_WR_PRI_QUEUING[0]), 0, 0 }, + { "mmGCEA_DRAM_RD_PRI_FIXED", REG_MMIO, 0x0a0f, 0, &mmGCEA_DRAM_RD_PRI_FIXED[0], sizeof(mmGCEA_DRAM_RD_PRI_FIXED)/sizeof(mmGCEA_DRAM_RD_PRI_FIXED[0]), 0, 0 }, + { "mmGCEA_DRAM_WR_PRI_FIXED", REG_MMIO, 0x0a10, 0, &mmGCEA_DRAM_WR_PRI_FIXED[0], sizeof(mmGCEA_DRAM_WR_PRI_FIXED)/sizeof(mmGCEA_DRAM_WR_PRI_FIXED[0]), 0, 0 }, + { "mmGCEA_DRAM_RD_PRI_URGENCY", REG_MMIO, 0x0a11, 0, &mmGCEA_DRAM_RD_PRI_URGENCY[0], sizeof(mmGCEA_DRAM_RD_PRI_URGENCY)/sizeof(mmGCEA_DRAM_RD_PRI_URGENCY[0]), 0, 0 }, + { "mmGCEA_DRAM_WR_PRI_URGENCY", REG_MMIO, 0x0a12, 0, &mmGCEA_DRAM_WR_PRI_URGENCY[0], sizeof(mmGCEA_DRAM_WR_PRI_URGENCY)/sizeof(mmGCEA_DRAM_WR_PRI_URGENCY[0]), 0, 0 }, + { "mmGCEA_DRAM_RD_PRI_QUANT_PRI1", REG_MMIO, 0x0a13, 0, &mmGCEA_DRAM_RD_PRI_QUANT_PRI1[0], sizeof(mmGCEA_DRAM_RD_PRI_QUANT_PRI1)/sizeof(mmGCEA_DRAM_RD_PRI_QUANT_PRI1[0]), 0, 0 }, + { "mmGCEA_DRAM_RD_PRI_QUANT_PRI2", REG_MMIO, 0x0a14, 0, &mmGCEA_DRAM_RD_PRI_QUANT_PRI2[0], sizeof(mmGCEA_DRAM_RD_PRI_QUANT_PRI2)/sizeof(mmGCEA_DRAM_RD_PRI_QUANT_PRI2[0]), 0, 0 }, + { "mmGCEA_DRAM_RD_PRI_QUANT_PRI3", REG_MMIO, 0x0a15, 0, &mmGCEA_DRAM_RD_PRI_QUANT_PRI3[0], sizeof(mmGCEA_DRAM_RD_PRI_QUANT_PRI3)/sizeof(mmGCEA_DRAM_RD_PRI_QUANT_PRI3[0]), 0, 0 }, + { "mmGCEA_DRAM_WR_PRI_QUANT_PRI1", REG_MMIO, 0x0a16, 0, &mmGCEA_DRAM_WR_PRI_QUANT_PRI1[0], sizeof(mmGCEA_DRAM_WR_PRI_QUANT_PRI1)/sizeof(mmGCEA_DRAM_WR_PRI_QUANT_PRI1[0]), 0, 0 }, + { "mmGCEA_DRAM_WR_PRI_QUANT_PRI2", REG_MMIO, 0x0a17, 0, &mmGCEA_DRAM_WR_PRI_QUANT_PRI2[0], sizeof(mmGCEA_DRAM_WR_PRI_QUANT_PRI2)/sizeof(mmGCEA_DRAM_WR_PRI_QUANT_PRI2[0]), 0, 0 }, + { "mmGCEA_DRAM_WR_PRI_QUANT_PRI3", REG_MMIO, 0x0a18, 0, &mmGCEA_DRAM_WR_PRI_QUANT_PRI3[0], sizeof(mmGCEA_DRAM_WR_PRI_QUANT_PRI3)/sizeof(mmGCEA_DRAM_WR_PRI_QUANT_PRI3[0]), 0, 0 }, + { "mmGCEA_ADDRNORM_BASE_ADDR0", REG_MMIO, 0x0a32, 0, &mmGCEA_ADDRNORM_BASE_ADDR0[0], sizeof(mmGCEA_ADDRNORM_BASE_ADDR0)/sizeof(mmGCEA_ADDRNORM_BASE_ADDR0[0]), 0, 0 }, + { "mmGCEA_ADDRNORM_LIMIT_ADDR0", REG_MMIO, 0x0a33, 0, &mmGCEA_ADDRNORM_LIMIT_ADDR0[0], sizeof(mmGCEA_ADDRNORM_LIMIT_ADDR0)/sizeof(mmGCEA_ADDRNORM_LIMIT_ADDR0[0]), 0, 0 }, + { "mmGCEA_ADDRNORM_BASE_ADDR1", REG_MMIO, 0x0a34, 0, &mmGCEA_ADDRNORM_BASE_ADDR1[0], sizeof(mmGCEA_ADDRNORM_BASE_ADDR1)/sizeof(mmGCEA_ADDRNORM_BASE_ADDR1[0]), 0, 0 }, + { "mmGCEA_ADDRNORM_LIMIT_ADDR1", REG_MMIO, 0x0a35, 0, &mmGCEA_ADDRNORM_LIMIT_ADDR1[0], sizeof(mmGCEA_ADDRNORM_LIMIT_ADDR1)/sizeof(mmGCEA_ADDRNORM_LIMIT_ADDR1[0]), 0, 0 }, + { "mmGCEA_ADDRNORM_OFFSET_ADDR1", REG_MMIO, 0x0a36, 0, &mmGCEA_ADDRNORM_OFFSET_ADDR1[0], sizeof(mmGCEA_ADDRNORM_OFFSET_ADDR1)/sizeof(mmGCEA_ADDRNORM_OFFSET_ADDR1[0]), 0, 0 }, + { "mmGCEA_ADDRNORM_HOLE_CNTL", REG_MMIO, 0x0a41, 0, &mmGCEA_ADDRNORM_HOLE_CNTL[0], sizeof(mmGCEA_ADDRNORM_HOLE_CNTL)/sizeof(mmGCEA_ADDRNORM_HOLE_CNTL[0]), 0, 0 }, + { "mmGCEA_ADDRDEC_BANK_CFG", REG_MMIO, 0x0a42, 0, &mmGCEA_ADDRDEC_BANK_CFG[0], sizeof(mmGCEA_ADDRDEC_BANK_CFG)/sizeof(mmGCEA_ADDRDEC_BANK_CFG[0]), 0, 0 }, + { "mmGCEA_ADDRDEC_MISC_CFG", REG_MMIO, 0x0a43, 0, &mmGCEA_ADDRDEC_MISC_CFG[0], sizeof(mmGCEA_ADDRDEC_MISC_CFG)/sizeof(mmGCEA_ADDRDEC_MISC_CFG[0]), 0, 0 }, + { "mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK0", REG_MMIO, 0x0a44, 0, &mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK0[0], sizeof(mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK0)/sizeof(mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK0[0]), 0, 0 }, + { "mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK1", REG_MMIO, 0x0a45, 0, &mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK1[0], sizeof(mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK1)/sizeof(mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK1[0]), 0, 0 }, + { "mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK2", REG_MMIO, 0x0a46, 0, &mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK2[0], sizeof(mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK2)/sizeof(mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK2[0]), 0, 0 }, + { "mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK3", REG_MMIO, 0x0a47, 0, &mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK3[0], sizeof(mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK3)/sizeof(mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK3[0]), 0, 0 }, + { "mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK4", REG_MMIO, 0x0a48, 0, &mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK4[0], sizeof(mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK4)/sizeof(mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK4[0]), 0, 0 }, + { "mmGCEA_ADDRDECDRAM_ADDR_HASH_PC", REG_MMIO, 0x0a49, 0, &mmGCEA_ADDRDECDRAM_ADDR_HASH_PC[0], sizeof(mmGCEA_ADDRDECDRAM_ADDR_HASH_PC)/sizeof(mmGCEA_ADDRDECDRAM_ADDR_HASH_PC[0]), 0, 0 }, + { "mmGCEA_ADDRDECDRAM_ADDR_HASH_PC2", REG_MMIO, 0x0a4a, 0, &mmGCEA_ADDRDECDRAM_ADDR_HASH_PC2[0], sizeof(mmGCEA_ADDRDECDRAM_ADDR_HASH_PC2)/sizeof(mmGCEA_ADDRDECDRAM_ADDR_HASH_PC2[0]), 0, 0 }, + { "mmGCEA_ADDRDECDRAM_ADDR_HASH_CS0", REG_MMIO, 0x0a4b, 0, &mmGCEA_ADDRDECDRAM_ADDR_HASH_CS0[0], sizeof(mmGCEA_ADDRDECDRAM_ADDR_HASH_CS0)/sizeof(mmGCEA_ADDRDECDRAM_ADDR_HASH_CS0[0]), 0, 0 }, + { "mmGCEA_ADDRDECDRAM_ADDR_HASH_CS1", REG_MMIO, 0x0a4c, 0, &mmGCEA_ADDRDECDRAM_ADDR_HASH_CS1[0], sizeof(mmGCEA_ADDRDECDRAM_ADDR_HASH_CS1)/sizeof(mmGCEA_ADDRDECDRAM_ADDR_HASH_CS1[0]), 0, 0 }, + { "mmGCEA_ADDRDECDRAM_HARVEST_ENABLE", REG_MMIO, 0x0a4d, 0, &mmGCEA_ADDRDECDRAM_HARVEST_ENABLE[0], sizeof(mmGCEA_ADDRDECDRAM_HARVEST_ENABLE)/sizeof(mmGCEA_ADDRDECDRAM_HARVEST_ENABLE[0]), 0, 0 }, + { "mmGCEA_ADDRDEC0_BASE_ADDR_CS0", REG_MMIO, 0x0a58, 0, &mmGCEA_ADDRDEC0_BASE_ADDR_CS0[0], sizeof(mmGCEA_ADDRDEC0_BASE_ADDR_CS0)/sizeof(mmGCEA_ADDRDEC0_BASE_ADDR_CS0[0]), 0, 0 }, + { "mmGCEA_ADDRDEC0_BASE_ADDR_CS1", REG_MMIO, 0x0a59, 0, &mmGCEA_ADDRDEC0_BASE_ADDR_CS1[0], sizeof(mmGCEA_ADDRDEC0_BASE_ADDR_CS1)/sizeof(mmGCEA_ADDRDEC0_BASE_ADDR_CS1[0]), 0, 0 }, + { "mmGCEA_ADDRDEC0_BASE_ADDR_CS2", REG_MMIO, 0x0a5a, 0, &mmGCEA_ADDRDEC0_BASE_ADDR_CS2[0], sizeof(mmGCEA_ADDRDEC0_BASE_ADDR_CS2)/sizeof(mmGCEA_ADDRDEC0_BASE_ADDR_CS2[0]), 0, 0 }, + { "mmGCEA_ADDRDEC0_BASE_ADDR_CS3", REG_MMIO, 0x0a5b, 0, &mmGCEA_ADDRDEC0_BASE_ADDR_CS3[0], sizeof(mmGCEA_ADDRDEC0_BASE_ADDR_CS3)/sizeof(mmGCEA_ADDRDEC0_BASE_ADDR_CS3[0]), 0, 0 }, + { "mmGCEA_ADDRDEC0_BASE_ADDR_SECCS0", REG_MMIO, 0x0a5c, 0, &mmGCEA_ADDRDEC0_BASE_ADDR_SECCS0[0], sizeof(mmGCEA_ADDRDEC0_BASE_ADDR_SECCS0)/sizeof(mmGCEA_ADDRDEC0_BASE_ADDR_SECCS0[0]), 0, 0 }, + { "mmGCEA_ADDRDEC0_BASE_ADDR_SECCS1", REG_MMIO, 0x0a5d, 0, &mmGCEA_ADDRDEC0_BASE_ADDR_SECCS1[0], sizeof(mmGCEA_ADDRDEC0_BASE_ADDR_SECCS1)/sizeof(mmGCEA_ADDRDEC0_BASE_ADDR_SECCS1[0]), 0, 0 }, + { "mmGCEA_ADDRDEC0_BASE_ADDR_SECCS2", REG_MMIO, 0x0a5e, 0, &mmGCEA_ADDRDEC0_BASE_ADDR_SECCS2[0], sizeof(mmGCEA_ADDRDEC0_BASE_ADDR_SECCS2)/sizeof(mmGCEA_ADDRDEC0_BASE_ADDR_SECCS2[0]), 0, 0 }, + { "mmGCEA_ADDRDEC0_BASE_ADDR_SECCS3", REG_MMIO, 0x0a5f, 0, &mmGCEA_ADDRDEC0_BASE_ADDR_SECCS3[0], sizeof(mmGCEA_ADDRDEC0_BASE_ADDR_SECCS3)/sizeof(mmGCEA_ADDRDEC0_BASE_ADDR_SECCS3[0]), 0, 0 }, + { "mmGCEA_ADDRDEC0_ADDR_MASK_CS01", REG_MMIO, 0x0a60, 0, &mmGCEA_ADDRDEC0_ADDR_MASK_CS01[0], sizeof(mmGCEA_ADDRDEC0_ADDR_MASK_CS01)/sizeof(mmGCEA_ADDRDEC0_ADDR_MASK_CS01[0]), 0, 0 }, + { "mmGCEA_ADDRDEC0_ADDR_MASK_CS23", REG_MMIO, 0x0a61, 0, &mmGCEA_ADDRDEC0_ADDR_MASK_CS23[0], sizeof(mmGCEA_ADDRDEC0_ADDR_MASK_CS23)/sizeof(mmGCEA_ADDRDEC0_ADDR_MASK_CS23[0]), 0, 0 }, + { "mmGCEA_ADDRDEC0_ADDR_MASK_SECCS01", REG_MMIO, 0x0a62, 0, &mmGCEA_ADDRDEC0_ADDR_MASK_SECCS01[0], sizeof(mmGCEA_ADDRDEC0_ADDR_MASK_SECCS01)/sizeof(mmGCEA_ADDRDEC0_ADDR_MASK_SECCS01[0]), 0, 0 }, + { "mmGCEA_ADDRDEC0_ADDR_MASK_SECCS23", REG_MMIO, 0x0a63, 0, &mmGCEA_ADDRDEC0_ADDR_MASK_SECCS23[0], sizeof(mmGCEA_ADDRDEC0_ADDR_MASK_SECCS23)/sizeof(mmGCEA_ADDRDEC0_ADDR_MASK_SECCS23[0]), 0, 0 }, + { "mmGCEA_ADDRDEC0_ADDR_CFG_CS01", REG_MMIO, 0x0a64, 0, &mmGCEA_ADDRDEC0_ADDR_CFG_CS01[0], sizeof(mmGCEA_ADDRDEC0_ADDR_CFG_CS01)/sizeof(mmGCEA_ADDRDEC0_ADDR_CFG_CS01[0]), 0, 0 }, + { "mmGCEA_ADDRDEC0_ADDR_CFG_CS23", REG_MMIO, 0x0a65, 0, &mmGCEA_ADDRDEC0_ADDR_CFG_CS23[0], sizeof(mmGCEA_ADDRDEC0_ADDR_CFG_CS23)/sizeof(mmGCEA_ADDRDEC0_ADDR_CFG_CS23[0]), 0, 0 }, + { "mmGCEA_ADDRDEC0_ADDR_SEL_CS01", REG_MMIO, 0x0a66, 0, &mmGCEA_ADDRDEC0_ADDR_SEL_CS01[0], sizeof(mmGCEA_ADDRDEC0_ADDR_SEL_CS01)/sizeof(mmGCEA_ADDRDEC0_ADDR_SEL_CS01[0]), 0, 0 }, + { "mmGCEA_ADDRDEC0_ADDR_SEL_CS23", REG_MMIO, 0x0a67, 0, &mmGCEA_ADDRDEC0_ADDR_SEL_CS23[0], sizeof(mmGCEA_ADDRDEC0_ADDR_SEL_CS23)/sizeof(mmGCEA_ADDRDEC0_ADDR_SEL_CS23[0]), 0, 0 }, + { "mmGCEA_ADDRDEC0_COL_SEL_LO_CS01", REG_MMIO, 0x0a68, 0, &mmGCEA_ADDRDEC0_COL_SEL_LO_CS01[0], sizeof(mmGCEA_ADDRDEC0_COL_SEL_LO_CS01)/sizeof(mmGCEA_ADDRDEC0_COL_SEL_LO_CS01[0]), 0, 0 }, + { "mmGCEA_ADDRDEC0_COL_SEL_LO_CS23", REG_MMIO, 0x0a69, 0, &mmGCEA_ADDRDEC0_COL_SEL_LO_CS23[0], sizeof(mmGCEA_ADDRDEC0_COL_SEL_LO_CS23)/sizeof(mmGCEA_ADDRDEC0_COL_SEL_LO_CS23[0]), 0, 0 }, + { "mmGCEA_ADDRDEC0_COL_SEL_HI_CS01", REG_MMIO, 0x0a6a, 0, &mmGCEA_ADDRDEC0_COL_SEL_HI_CS01[0], sizeof(mmGCEA_ADDRDEC0_COL_SEL_HI_CS01)/sizeof(mmGCEA_ADDRDEC0_COL_SEL_HI_CS01[0]), 0, 0 }, + { "mmGCEA_ADDRDEC0_COL_SEL_HI_CS23", REG_MMIO, 0x0a6b, 0, &mmGCEA_ADDRDEC0_COL_SEL_HI_CS23[0], sizeof(mmGCEA_ADDRDEC0_COL_SEL_HI_CS23)/sizeof(mmGCEA_ADDRDEC0_COL_SEL_HI_CS23[0]), 0, 0 }, + { "mmGCEA_ADDRDEC0_RM_SEL_CS01", REG_MMIO, 0x0a6c, 0, &mmGCEA_ADDRDEC0_RM_SEL_CS01[0], sizeof(mmGCEA_ADDRDEC0_RM_SEL_CS01)/sizeof(mmGCEA_ADDRDEC0_RM_SEL_CS01[0]), 0, 0 }, + { "mmGCEA_ADDRDEC0_RM_SEL_CS23", REG_MMIO, 0x0a6d, 0, &mmGCEA_ADDRDEC0_RM_SEL_CS23[0], sizeof(mmGCEA_ADDRDEC0_RM_SEL_CS23)/sizeof(mmGCEA_ADDRDEC0_RM_SEL_CS23[0]), 0, 0 }, + { "mmGCEA_ADDRDEC0_RM_SEL_SECCS01", REG_MMIO, 0x0a6e, 0, &mmGCEA_ADDRDEC0_RM_SEL_SECCS01[0], sizeof(mmGCEA_ADDRDEC0_RM_SEL_SECCS01)/sizeof(mmGCEA_ADDRDEC0_RM_SEL_SECCS01[0]), 0, 0 }, + { "mmGCEA_ADDRDEC0_RM_SEL_SECCS23", REG_MMIO, 0x0a6f, 0, &mmGCEA_ADDRDEC0_RM_SEL_SECCS23[0], sizeof(mmGCEA_ADDRDEC0_RM_SEL_SECCS23)/sizeof(mmGCEA_ADDRDEC0_RM_SEL_SECCS23[0]), 0, 0 }, + { "mmGCEA_ADDRDEC1_BASE_ADDR_CS0", REG_MMIO, 0x0a70, 0, &mmGCEA_ADDRDEC1_BASE_ADDR_CS0[0], sizeof(mmGCEA_ADDRDEC1_BASE_ADDR_CS0)/sizeof(mmGCEA_ADDRDEC1_BASE_ADDR_CS0[0]), 0, 0 }, + { "mmGCEA_ADDRDEC1_BASE_ADDR_CS1", REG_MMIO, 0x0a71, 0, &mmGCEA_ADDRDEC1_BASE_ADDR_CS1[0], sizeof(mmGCEA_ADDRDEC1_BASE_ADDR_CS1)/sizeof(mmGCEA_ADDRDEC1_BASE_ADDR_CS1[0]), 0, 0 }, + { "mmGCEA_ADDRDEC1_BASE_ADDR_CS2", REG_MMIO, 0x0a72, 0, &mmGCEA_ADDRDEC1_BASE_ADDR_CS2[0], sizeof(mmGCEA_ADDRDEC1_BASE_ADDR_CS2)/sizeof(mmGCEA_ADDRDEC1_BASE_ADDR_CS2[0]), 0, 0 }, + { "mmGCEA_ADDRDEC1_BASE_ADDR_CS3", REG_MMIO, 0x0a73, 0, &mmGCEA_ADDRDEC1_BASE_ADDR_CS3[0], sizeof(mmGCEA_ADDRDEC1_BASE_ADDR_CS3)/sizeof(mmGCEA_ADDRDEC1_BASE_ADDR_CS3[0]), 0, 0 }, + { "mmGCEA_ADDRDEC1_BASE_ADDR_SECCS0", REG_MMIO, 0x0a74, 0, &mmGCEA_ADDRDEC1_BASE_ADDR_SECCS0[0], sizeof(mmGCEA_ADDRDEC1_BASE_ADDR_SECCS0)/sizeof(mmGCEA_ADDRDEC1_BASE_ADDR_SECCS0[0]), 0, 0 }, + { "mmGCEA_ADDRDEC1_BASE_ADDR_SECCS1", REG_MMIO, 0x0a75, 0, &mmGCEA_ADDRDEC1_BASE_ADDR_SECCS1[0], sizeof(mmGCEA_ADDRDEC1_BASE_ADDR_SECCS1)/sizeof(mmGCEA_ADDRDEC1_BASE_ADDR_SECCS1[0]), 0, 0 }, + { "mmGCEA_ADDRDEC1_BASE_ADDR_SECCS2", REG_MMIO, 0x0a76, 0, &mmGCEA_ADDRDEC1_BASE_ADDR_SECCS2[0], sizeof(mmGCEA_ADDRDEC1_BASE_ADDR_SECCS2)/sizeof(mmGCEA_ADDRDEC1_BASE_ADDR_SECCS2[0]), 0, 0 }, + { "mmGCEA_ADDRDEC1_BASE_ADDR_SECCS3", REG_MMIO, 0x0a77, 0, &mmGCEA_ADDRDEC1_BASE_ADDR_SECCS3[0], sizeof(mmGCEA_ADDRDEC1_BASE_ADDR_SECCS3)/sizeof(mmGCEA_ADDRDEC1_BASE_ADDR_SECCS3[0]), 0, 0 }, + { "mmGCEA_ADDRDEC1_ADDR_MASK_CS01", REG_MMIO, 0x0a78, 0, &mmGCEA_ADDRDEC1_ADDR_MASK_CS01[0], sizeof(mmGCEA_ADDRDEC1_ADDR_MASK_CS01)/sizeof(mmGCEA_ADDRDEC1_ADDR_MASK_CS01[0]), 0, 0 }, + { "mmGCEA_ADDRDEC1_ADDR_MASK_CS23", REG_MMIO, 0x0a79, 0, &mmGCEA_ADDRDEC1_ADDR_MASK_CS23[0], sizeof(mmGCEA_ADDRDEC1_ADDR_MASK_CS23)/sizeof(mmGCEA_ADDRDEC1_ADDR_MASK_CS23[0]), 0, 0 }, + { "mmGCEA_ADDRDEC1_ADDR_MASK_SECCS01", REG_MMIO, 0x0a7a, 0, &mmGCEA_ADDRDEC1_ADDR_MASK_SECCS01[0], sizeof(mmGCEA_ADDRDEC1_ADDR_MASK_SECCS01)/sizeof(mmGCEA_ADDRDEC1_ADDR_MASK_SECCS01[0]), 0, 0 }, + { "mmGCEA_ADDRDEC1_ADDR_MASK_SECCS23", REG_MMIO, 0x0a7b, 0, &mmGCEA_ADDRDEC1_ADDR_MASK_SECCS23[0], sizeof(mmGCEA_ADDRDEC1_ADDR_MASK_SECCS23)/sizeof(mmGCEA_ADDRDEC1_ADDR_MASK_SECCS23[0]), 0, 0 }, + { "mmGCEA_ADDRDEC1_ADDR_CFG_CS01", REG_MMIO, 0x0a7c, 0, &mmGCEA_ADDRDEC1_ADDR_CFG_CS01[0], sizeof(mmGCEA_ADDRDEC1_ADDR_CFG_CS01)/sizeof(mmGCEA_ADDRDEC1_ADDR_CFG_CS01[0]), 0, 0 }, + { "mmGCEA_ADDRDEC1_ADDR_CFG_CS23", REG_MMIO, 0x0a7d, 0, &mmGCEA_ADDRDEC1_ADDR_CFG_CS23[0], sizeof(mmGCEA_ADDRDEC1_ADDR_CFG_CS23)/sizeof(mmGCEA_ADDRDEC1_ADDR_CFG_CS23[0]), 0, 0 }, + { "mmGCEA_ADDRDEC1_ADDR_SEL_CS01", REG_MMIO, 0x0a7e, 0, &mmGCEA_ADDRDEC1_ADDR_SEL_CS01[0], sizeof(mmGCEA_ADDRDEC1_ADDR_SEL_CS01)/sizeof(mmGCEA_ADDRDEC1_ADDR_SEL_CS01[0]), 0, 0 }, + { "mmGCEA_ADDRDEC1_ADDR_SEL_CS23", REG_MMIO, 0x0a7f, 0, &mmGCEA_ADDRDEC1_ADDR_SEL_CS23[0], sizeof(mmGCEA_ADDRDEC1_ADDR_SEL_CS23)/sizeof(mmGCEA_ADDRDEC1_ADDR_SEL_CS23[0]), 0, 0 }, + { "mmGCEA_ADDRDEC1_COL_SEL_LO_CS01", REG_MMIO, 0x0a80, 0, &mmGCEA_ADDRDEC1_COL_SEL_LO_CS01[0], sizeof(mmGCEA_ADDRDEC1_COL_SEL_LO_CS01)/sizeof(mmGCEA_ADDRDEC1_COL_SEL_LO_CS01[0]), 0, 0 }, + { "mmGCEA_ADDRDEC1_COL_SEL_LO_CS23", REG_MMIO, 0x0a81, 0, &mmGCEA_ADDRDEC1_COL_SEL_LO_CS23[0], sizeof(mmGCEA_ADDRDEC1_COL_SEL_LO_CS23)/sizeof(mmGCEA_ADDRDEC1_COL_SEL_LO_CS23[0]), 0, 0 }, + { "mmGCEA_ADDRDEC1_COL_SEL_HI_CS01", REG_MMIO, 0x0a82, 0, &mmGCEA_ADDRDEC1_COL_SEL_HI_CS01[0], sizeof(mmGCEA_ADDRDEC1_COL_SEL_HI_CS01)/sizeof(mmGCEA_ADDRDEC1_COL_SEL_HI_CS01[0]), 0, 0 }, + { "mmGCEA_ADDRDEC1_COL_SEL_HI_CS23", REG_MMIO, 0x0a83, 0, &mmGCEA_ADDRDEC1_COL_SEL_HI_CS23[0], sizeof(mmGCEA_ADDRDEC1_COL_SEL_HI_CS23)/sizeof(mmGCEA_ADDRDEC1_COL_SEL_HI_CS23[0]), 0, 0 }, + { "mmGCEA_ADDRDEC1_RM_SEL_CS01", REG_MMIO, 0x0a84, 0, &mmGCEA_ADDRDEC1_RM_SEL_CS01[0], sizeof(mmGCEA_ADDRDEC1_RM_SEL_CS01)/sizeof(mmGCEA_ADDRDEC1_RM_SEL_CS01[0]), 0, 0 }, + { "mmGCEA_ADDRDEC1_RM_SEL_CS23", REG_MMIO, 0x0a85, 0, &mmGCEA_ADDRDEC1_RM_SEL_CS23[0], sizeof(mmGCEA_ADDRDEC1_RM_SEL_CS23)/sizeof(mmGCEA_ADDRDEC1_RM_SEL_CS23[0]), 0, 0 }, + { "mmGCEA_ADDRDEC1_RM_SEL_SECCS01", REG_MMIO, 0x0a86, 0, &mmGCEA_ADDRDEC1_RM_SEL_SECCS01[0], sizeof(mmGCEA_ADDRDEC1_RM_SEL_SECCS01)/sizeof(mmGCEA_ADDRDEC1_RM_SEL_SECCS01[0]), 0, 0 }, + { "mmGCEA_ADDRDEC1_RM_SEL_SECCS23", REG_MMIO, 0x0a87, 0, &mmGCEA_ADDRDEC1_RM_SEL_SECCS23[0], sizeof(mmGCEA_ADDRDEC1_RM_SEL_SECCS23)/sizeof(mmGCEA_ADDRDEC1_RM_SEL_SECCS23[0]), 0, 0 }, + { "mmGCEA_IO_RD_CLI2GRP_MAP0", REG_MMIO, 0x0ad0, 0, &mmGCEA_IO_RD_CLI2GRP_MAP0[0], sizeof(mmGCEA_IO_RD_CLI2GRP_MAP0)/sizeof(mmGCEA_IO_RD_CLI2GRP_MAP0[0]), 0, 0 }, + { "mmGCEA_IO_RD_CLI2GRP_MAP1", REG_MMIO, 0x0ad1, 0, &mmGCEA_IO_RD_CLI2GRP_MAP1[0], sizeof(mmGCEA_IO_RD_CLI2GRP_MAP1)/sizeof(mmGCEA_IO_RD_CLI2GRP_MAP1[0]), 0, 0 }, + { "mmGCEA_IO_WR_CLI2GRP_MAP0", REG_MMIO, 0x0ad2, 0, &mmGCEA_IO_WR_CLI2GRP_MAP0[0], sizeof(mmGCEA_IO_WR_CLI2GRP_MAP0)/sizeof(mmGCEA_IO_WR_CLI2GRP_MAP0[0]), 0, 0 }, + { "mmGCEA_IO_WR_CLI2GRP_MAP1", REG_MMIO, 0x0ad3, 0, &mmGCEA_IO_WR_CLI2GRP_MAP1[0], sizeof(mmGCEA_IO_WR_CLI2GRP_MAP1)/sizeof(mmGCEA_IO_WR_CLI2GRP_MAP1[0]), 0, 0 }, + { "mmGCEA_IO_RD_COMBINE_FLUSH", REG_MMIO, 0x0ad4, 0, &mmGCEA_IO_RD_COMBINE_FLUSH[0], sizeof(mmGCEA_IO_RD_COMBINE_FLUSH)/sizeof(mmGCEA_IO_RD_COMBINE_FLUSH[0]), 0, 0 }, + { "mmGCEA_IO_WR_COMBINE_FLUSH", REG_MMIO, 0x0ad5, 0, &mmGCEA_IO_WR_COMBINE_FLUSH[0], sizeof(mmGCEA_IO_WR_COMBINE_FLUSH)/sizeof(mmGCEA_IO_WR_COMBINE_FLUSH[0]), 0, 0 }, + { "mmGCEA_IO_GROUP_BURST", REG_MMIO, 0x0ad6, 0, &mmGCEA_IO_GROUP_BURST[0], sizeof(mmGCEA_IO_GROUP_BURST)/sizeof(mmGCEA_IO_GROUP_BURST[0]), 0, 0 }, + { "mmGCEA_IO_RD_PRI_AGE", REG_MMIO, 0x0ad7, 0, &mmGCEA_IO_RD_PRI_AGE[0], sizeof(mmGCEA_IO_RD_PRI_AGE)/sizeof(mmGCEA_IO_RD_PRI_AGE[0]), 0, 0 }, + { "mmGCEA_IO_WR_PRI_AGE", REG_MMIO, 0x0ad8, 0, &mmGCEA_IO_WR_PRI_AGE[0], sizeof(mmGCEA_IO_WR_PRI_AGE)/sizeof(mmGCEA_IO_WR_PRI_AGE[0]), 0, 0 }, + { "mmGCEA_IO_RD_PRI_QUEUING", REG_MMIO, 0x0ad9, 0, &mmGCEA_IO_RD_PRI_QUEUING[0], sizeof(mmGCEA_IO_RD_PRI_QUEUING)/sizeof(mmGCEA_IO_RD_PRI_QUEUING[0]), 0, 0 }, + { "mmGCEA_IO_WR_PRI_QUEUING", REG_MMIO, 0x0ada, 0, &mmGCEA_IO_WR_PRI_QUEUING[0], sizeof(mmGCEA_IO_WR_PRI_QUEUING)/sizeof(mmGCEA_IO_WR_PRI_QUEUING[0]), 0, 0 }, + { "mmGCEA_IO_RD_PRI_FIXED", REG_MMIO, 0x0adb, 0, &mmGCEA_IO_RD_PRI_FIXED[0], sizeof(mmGCEA_IO_RD_PRI_FIXED)/sizeof(mmGCEA_IO_RD_PRI_FIXED[0]), 0, 0 }, + { "mmGCEA_IO_WR_PRI_FIXED", REG_MMIO, 0x0adc, 0, &mmGCEA_IO_WR_PRI_FIXED[0], sizeof(mmGCEA_IO_WR_PRI_FIXED)/sizeof(mmGCEA_IO_WR_PRI_FIXED[0]), 0, 0 }, + { "mmGCEA_IO_RD_PRI_URGENCY", REG_MMIO, 0x0add, 0, &mmGCEA_IO_RD_PRI_URGENCY[0], sizeof(mmGCEA_IO_RD_PRI_URGENCY)/sizeof(mmGCEA_IO_RD_PRI_URGENCY[0]), 0, 0 }, + { "mmGCEA_IO_WR_PRI_URGENCY", REG_MMIO, 0x0ade, 0, &mmGCEA_IO_WR_PRI_URGENCY[0], sizeof(mmGCEA_IO_WR_PRI_URGENCY)/sizeof(mmGCEA_IO_WR_PRI_URGENCY[0]), 0, 0 }, + { "mmGCEA_IO_RD_PRI_URGENCY_MASK", REG_MMIO, 0x0adf, 0, &mmGCEA_IO_RD_PRI_URGENCY_MASK[0], sizeof(mmGCEA_IO_RD_PRI_URGENCY_MASK)/sizeof(mmGCEA_IO_RD_PRI_URGENCY_MASK[0]), 0, 0 }, + { "mmGCEA_IO_WR_PRI_URGENCY_MASK", REG_MMIO, 0x0ae0, 0, &mmGCEA_IO_WR_PRI_URGENCY_MASK[0], sizeof(mmGCEA_IO_WR_PRI_URGENCY_MASK)/sizeof(mmGCEA_IO_WR_PRI_URGENCY_MASK[0]), 0, 0 }, + { "mmGCEA_IO_RD_PRI_QUANT_PRI1", REG_MMIO, 0x0ae1, 0, &mmGCEA_IO_RD_PRI_QUANT_PRI1[0], sizeof(mmGCEA_IO_RD_PRI_QUANT_PRI1)/sizeof(mmGCEA_IO_RD_PRI_QUANT_PRI1[0]), 0, 0 }, + { "mmGCEA_IO_RD_PRI_QUANT_PRI2", REG_MMIO, 0x0ae2, 0, &mmGCEA_IO_RD_PRI_QUANT_PRI2[0], sizeof(mmGCEA_IO_RD_PRI_QUANT_PRI2)/sizeof(mmGCEA_IO_RD_PRI_QUANT_PRI2[0]), 0, 0 }, + { "mmGCEA_IO_RD_PRI_QUANT_PRI3", REG_MMIO, 0x0ae3, 0, &mmGCEA_IO_RD_PRI_QUANT_PRI3[0], sizeof(mmGCEA_IO_RD_PRI_QUANT_PRI3)/sizeof(mmGCEA_IO_RD_PRI_QUANT_PRI3[0]), 0, 0 }, + { "mmGCEA_IO_WR_PRI_QUANT_PRI1", REG_MMIO, 0x0ae4, 0, &mmGCEA_IO_WR_PRI_QUANT_PRI1[0], sizeof(mmGCEA_IO_WR_PRI_QUANT_PRI1)/sizeof(mmGCEA_IO_WR_PRI_QUANT_PRI1[0]), 0, 0 }, + { "mmGCEA_IO_WR_PRI_QUANT_PRI2", REG_MMIO, 0x0ae5, 0, &mmGCEA_IO_WR_PRI_QUANT_PRI2[0], sizeof(mmGCEA_IO_WR_PRI_QUANT_PRI2)/sizeof(mmGCEA_IO_WR_PRI_QUANT_PRI2[0]), 0, 0 }, + { "mmGCEA_IO_WR_PRI_QUANT_PRI3", REG_MMIO, 0x0ae6, 0, &mmGCEA_IO_WR_PRI_QUANT_PRI3[0], sizeof(mmGCEA_IO_WR_PRI_QUANT_PRI3)/sizeof(mmGCEA_IO_WR_PRI_QUANT_PRI3[0]), 0, 0 }, + { "mmGCEA_SDP_ARB_DRAM", REG_MMIO, 0x0ae7, 0, &mmGCEA_SDP_ARB_DRAM[0], sizeof(mmGCEA_SDP_ARB_DRAM)/sizeof(mmGCEA_SDP_ARB_DRAM[0]), 0, 0 }, + { "mmGCEA_SDP_ARB_FINAL", REG_MMIO, 0x0ae9, 0, &mmGCEA_SDP_ARB_FINAL[0], sizeof(mmGCEA_SDP_ARB_FINAL)/sizeof(mmGCEA_SDP_ARB_FINAL[0]), 0, 0 }, + { "mmGCEA_SDP_DRAM_PRIORITY", REG_MMIO, 0x0aea, 0, &mmGCEA_SDP_DRAM_PRIORITY[0], sizeof(mmGCEA_SDP_DRAM_PRIORITY)/sizeof(mmGCEA_SDP_DRAM_PRIORITY[0]), 0, 0 }, + { "mmGCEA_SDP_IO_PRIORITY", REG_MMIO, 0x0aec, 0, &mmGCEA_SDP_IO_PRIORITY[0], sizeof(mmGCEA_SDP_IO_PRIORITY)/sizeof(mmGCEA_SDP_IO_PRIORITY[0]), 0, 0 }, + { "mmGCEA_SDP_CREDITS", REG_MMIO, 0x0aed, 0, &mmGCEA_SDP_CREDITS[0], sizeof(mmGCEA_SDP_CREDITS)/sizeof(mmGCEA_SDP_CREDITS[0]), 0, 0 }, + { "mmGCEA_SDP_TAG_RESERVE0", REG_MMIO, 0x0aee, 0, &mmGCEA_SDP_TAG_RESERVE0[0], sizeof(mmGCEA_SDP_TAG_RESERVE0)/sizeof(mmGCEA_SDP_TAG_RESERVE0[0]), 0, 0 }, + { "mmGCEA_SDP_TAG_RESERVE1", REG_MMIO, 0x0aef, 0, &mmGCEA_SDP_TAG_RESERVE1[0], sizeof(mmGCEA_SDP_TAG_RESERVE1)/sizeof(mmGCEA_SDP_TAG_RESERVE1[0]), 0, 0 }, + { "mmGCEA_SDP_VCC_RESERVE0", REG_MMIO, 0x0af0, 0, &mmGCEA_SDP_VCC_RESERVE0[0], sizeof(mmGCEA_SDP_VCC_RESERVE0)/sizeof(mmGCEA_SDP_VCC_RESERVE0[0]), 0, 0 }, + { "mmGCEA_SDP_VCC_RESERVE1", REG_MMIO, 0x0af1, 0, &mmGCEA_SDP_VCC_RESERVE1[0], sizeof(mmGCEA_SDP_VCC_RESERVE1)/sizeof(mmGCEA_SDP_VCC_RESERVE1[0]), 0, 0 }, + { "mmGCEA_SDP_VCD_RESERVE0", REG_MMIO, 0x0af2, 0, &mmGCEA_SDP_VCD_RESERVE0[0], sizeof(mmGCEA_SDP_VCD_RESERVE0)/sizeof(mmGCEA_SDP_VCD_RESERVE0[0]), 0, 0 }, + { "mmGCEA_SDP_VCD_RESERVE1", REG_MMIO, 0x0af3, 0, &mmGCEA_SDP_VCD_RESERVE1[0], sizeof(mmGCEA_SDP_VCD_RESERVE1)/sizeof(mmGCEA_SDP_VCD_RESERVE1[0]), 0, 0 }, + { "mmGCEA_SDP_REQ_CNTL", REG_MMIO, 0x0af4, 0, &mmGCEA_SDP_REQ_CNTL[0], sizeof(mmGCEA_SDP_REQ_CNTL)/sizeof(mmGCEA_SDP_REQ_CNTL[0]), 0, 0 }, + { "mmGCEA_MISC", REG_MMIO, 0x0af5, 0, &mmGCEA_MISC[0], sizeof(mmGCEA_MISC)/sizeof(mmGCEA_MISC[0]), 0, 0 }, + { "mmGCEA_LATENCY_SAMPLING", REG_MMIO, 0x0af6, 0, &mmGCEA_LATENCY_SAMPLING[0], sizeof(mmGCEA_LATENCY_SAMPLING)/sizeof(mmGCEA_LATENCY_SAMPLING[0]), 0, 0 }, + { "mmGCEA_PERFCOUNTER_LO", REG_MMIO, 0x0af7, 0, &mmGCEA_PERFCOUNTER_LO[0], sizeof(mmGCEA_PERFCOUNTER_LO)/sizeof(mmGCEA_PERFCOUNTER_LO[0]), 0, 0 }, + { "mmGCEA_PERFCOUNTER_HI", REG_MMIO, 0x0af8, 0, &mmGCEA_PERFCOUNTER_HI[0], sizeof(mmGCEA_PERFCOUNTER_HI)/sizeof(mmGCEA_PERFCOUNTER_HI[0]), 0, 0 }, + { "mmGCEA_PERFCOUNTER0_CFG", REG_MMIO, 0x0af9, 0, &mmGCEA_PERFCOUNTER0_CFG[0], sizeof(mmGCEA_PERFCOUNTER0_CFG)/sizeof(mmGCEA_PERFCOUNTER0_CFG[0]), 0, 0 }, + { "mmGCEA_PERFCOUNTER1_CFG", REG_MMIO, 0x0afa, 0, &mmGCEA_PERFCOUNTER1_CFG[0], sizeof(mmGCEA_PERFCOUNTER1_CFG)/sizeof(mmGCEA_PERFCOUNTER1_CFG[0]), 0, 0 }, + { "mmGCEA_PERFCOUNTER_RSLT_CNTL", REG_MMIO, 0x0afb, 0, &mmGCEA_PERFCOUNTER_RSLT_CNTL[0], sizeof(mmGCEA_PERFCOUNTER_RSLT_CNTL)/sizeof(mmGCEA_PERFCOUNTER_RSLT_CNTL[0]), 0, 0 }, + { "mmTCP_INVALIDATE", REG_MMIO, 0x0b00, 0, &mmTCP_INVALIDATE[0], sizeof(mmTCP_INVALIDATE)/sizeof(mmTCP_INVALIDATE[0]), 0, 0 }, + { "mmTCP_STATUS", REG_MMIO, 0x0b01, 0, &mmTCP_STATUS[0], sizeof(mmTCP_STATUS)/sizeof(mmTCP_STATUS[0]), 0, 0 }, + { "mmTCP_CNTL", REG_MMIO, 0x0b02, 0, &mmTCP_CNTL[0], sizeof(mmTCP_CNTL)/sizeof(mmTCP_CNTL[0]), 0, 0 }, + { "mmTCP_CHAN_STEER_LO", REG_MMIO, 0x0b03, 0, &mmTCP_CHAN_STEER_LO[0], sizeof(mmTCP_CHAN_STEER_LO)/sizeof(mmTCP_CHAN_STEER_LO[0]), 0, 0 }, + { "mmTCP_CHAN_STEER_HI", REG_MMIO, 0x0b04, 0, &mmTCP_CHAN_STEER_HI[0], sizeof(mmTCP_CHAN_STEER_HI)/sizeof(mmTCP_CHAN_STEER_HI[0]), 0, 0 }, + { "mmTCP_ADDR_CONFIG", REG_MMIO, 0x0b05, 0, &mmTCP_ADDR_CONFIG[0], sizeof(mmTCP_ADDR_CONFIG)/sizeof(mmTCP_ADDR_CONFIG[0]), 0, 0 }, + { "mmTCP_CREDIT", REG_MMIO, 0x0b06, 0, &mmTCP_CREDIT[0], sizeof(mmTCP_CREDIT)/sizeof(mmTCP_CREDIT[0]), 0, 0 }, + { "mmTCP_BUFFER_ADDR_HASH_CNTL", REG_MMIO, 0x0b16, 0, &mmTCP_BUFFER_ADDR_HASH_CNTL[0], sizeof(mmTCP_BUFFER_ADDR_HASH_CNTL)/sizeof(mmTCP_BUFFER_ADDR_HASH_CNTL[0]), 0, 0 }, + { "mmTCP_EDC_CNT", REG_MMIO, 0x0b17, 0, &mmTCP_EDC_CNT[0], sizeof(mmTCP_EDC_CNT)/sizeof(mmTCP_EDC_CNT[0]), 0, 0 }, + { "mmTC_CFG_L1_LOAD_POLICY0", REG_MMIO, 0x0b1a, 0, &mmTC_CFG_L1_LOAD_POLICY0[0], sizeof(mmTC_CFG_L1_LOAD_POLICY0)/sizeof(mmTC_CFG_L1_LOAD_POLICY0[0]), 0, 0 }, + { "mmTC_CFG_L1_LOAD_POLICY1", REG_MMIO, 0x0b1b, 0, &mmTC_CFG_L1_LOAD_POLICY1[0], sizeof(mmTC_CFG_L1_LOAD_POLICY1)/sizeof(mmTC_CFG_L1_LOAD_POLICY1[0]), 0, 0 }, + { "mmTC_CFG_L1_STORE_POLICY", REG_MMIO, 0x0b1c, 0, &mmTC_CFG_L1_STORE_POLICY[0], sizeof(mmTC_CFG_L1_STORE_POLICY)/sizeof(mmTC_CFG_L1_STORE_POLICY[0]), 0, 0 }, + { "mmTC_CFG_L2_LOAD_POLICY0", REG_MMIO, 0x0b1d, 0, &mmTC_CFG_L2_LOAD_POLICY0[0], sizeof(mmTC_CFG_L2_LOAD_POLICY0)/sizeof(mmTC_CFG_L2_LOAD_POLICY0[0]), 0, 0 }, + { "mmTC_CFG_L2_LOAD_POLICY1", REG_MMIO, 0x0b1e, 0, &mmTC_CFG_L2_LOAD_POLICY1[0], sizeof(mmTC_CFG_L2_LOAD_POLICY1)/sizeof(mmTC_CFG_L2_LOAD_POLICY1[0]), 0, 0 }, + { "mmTC_CFG_L2_STORE_POLICY0", REG_MMIO, 0x0b1f, 0, &mmTC_CFG_L2_STORE_POLICY0[0], sizeof(mmTC_CFG_L2_STORE_POLICY0)/sizeof(mmTC_CFG_L2_STORE_POLICY0[0]), 0, 0 }, + { "mmTC_CFG_L2_STORE_POLICY1", REG_MMIO, 0x0b20, 0, &mmTC_CFG_L2_STORE_POLICY1[0], sizeof(mmTC_CFG_L2_STORE_POLICY1)/sizeof(mmTC_CFG_L2_STORE_POLICY1[0]), 0, 0 }, + { "mmTC_CFG_L2_ATOMIC_POLICY", REG_MMIO, 0x0b21, 0, &mmTC_CFG_L2_ATOMIC_POLICY[0], sizeof(mmTC_CFG_L2_ATOMIC_POLICY)/sizeof(mmTC_CFG_L2_ATOMIC_POLICY[0]), 0, 0 }, + { "mmTC_CFG_L1_VOLATILE", REG_MMIO, 0x0b22, 0, &mmTC_CFG_L1_VOLATILE[0], sizeof(mmTC_CFG_L1_VOLATILE)/sizeof(mmTC_CFG_L1_VOLATILE[0]), 0, 0 }, + { "mmTC_CFG_L2_VOLATILE", REG_MMIO, 0x0b23, 0, &mmTC_CFG_L2_VOLATILE[0], sizeof(mmTC_CFG_L2_VOLATILE)/sizeof(mmTC_CFG_L2_VOLATILE[0]), 0, 0 }, + { "mmTCI_STATUS", REG_MMIO, 0x0b61, 0, &mmTCI_STATUS[0], sizeof(mmTCI_STATUS)/sizeof(mmTCI_STATUS[0]), 0, 0 }, + { "mmTCI_CNTL_1", REG_MMIO, 0x0b62, 0, &mmTCI_CNTL_1[0], sizeof(mmTCI_CNTL_1)/sizeof(mmTCI_CNTL_1[0]), 0, 0 }, + { "mmTCI_CNTL_2", REG_MMIO, 0x0b63, 0, &mmTCI_CNTL_2[0], sizeof(mmTCI_CNTL_2)/sizeof(mmTCI_CNTL_2[0]), 0, 0 }, + { "mmTCC_CTRL", REG_MMIO, 0x0b80, 0, &mmTCC_CTRL[0], sizeof(mmTCC_CTRL)/sizeof(mmTCC_CTRL[0]), 0, 0 }, + { "mmTCC_CTRL2", REG_MMIO, 0x0b81, 0, &mmTCC_CTRL2[0], sizeof(mmTCC_CTRL2)/sizeof(mmTCC_CTRL2[0]), 0, 0 }, + { "mmTCC_EDC_CNT", REG_MMIO, 0x0b82, 0, &mmTCC_EDC_CNT[0], sizeof(mmTCC_EDC_CNT)/sizeof(mmTCC_EDC_CNT[0]), 0, 0 }, + { "mmTCC_EDC_CNT2", REG_MMIO, 0x0b83, 0, &mmTCC_EDC_CNT2[0], sizeof(mmTCC_EDC_CNT2)/sizeof(mmTCC_EDC_CNT2[0]), 0, 0 }, + { "mmTCC_REDUNDANCY", REG_MMIO, 0x0b84, 0, &mmTCC_REDUNDANCY[0], sizeof(mmTCC_REDUNDANCY)/sizeof(mmTCC_REDUNDANCY[0]), 0, 0 }, + { "mmTCC_EXE_DISABLE", REG_MMIO, 0x0b85, 0, &mmTCC_EXE_DISABLE[0], sizeof(mmTCC_EXE_DISABLE)/sizeof(mmTCC_EXE_DISABLE[0]), 0, 0 }, + { "mmTCC_DSM_CNTL", REG_MMIO, 0x0b86, 0, &mmTCC_DSM_CNTL[0], sizeof(mmTCC_DSM_CNTL)/sizeof(mmTCC_DSM_CNTL[0]), 0, 0 }, + { "mmTCC_DSM_CNTLA", REG_MMIO, 0x0b87, 0, &mmTCC_DSM_CNTLA[0], sizeof(mmTCC_DSM_CNTLA)/sizeof(mmTCC_DSM_CNTLA[0]), 0, 0 }, + { "mmTCC_DSM_CNTL2", REG_MMIO, 0x0b88, 0, &mmTCC_DSM_CNTL2[0], sizeof(mmTCC_DSM_CNTL2)/sizeof(mmTCC_DSM_CNTL2[0]), 0, 0 }, + { "mmTCC_DSM_CNTL2A", REG_MMIO, 0x0b89, 0, &mmTCC_DSM_CNTL2A[0], sizeof(mmTCC_DSM_CNTL2A)/sizeof(mmTCC_DSM_CNTL2A[0]), 0, 0 }, + { "mmTCC_DSM_CNTL2B", REG_MMIO, 0x0b8a, 0, &mmTCC_DSM_CNTL2B[0], sizeof(mmTCC_DSM_CNTL2B)/sizeof(mmTCC_DSM_CNTL2B[0]), 0, 0 }, + { "mmTCC_WBINVL2", REG_MMIO, 0x0b8b, 0, &mmTCC_WBINVL2[0], sizeof(mmTCC_WBINVL2)/sizeof(mmTCC_WBINVL2[0]), 0, 0 }, + { "mmTCC_SOFT_RESET", REG_MMIO, 0x0b8c, 0, &mmTCC_SOFT_RESET[0], sizeof(mmTCC_SOFT_RESET)/sizeof(mmTCC_SOFT_RESET[0]), 0, 0 }, + { "mmTCA_CTRL", REG_MMIO, 0x0bc0, 0, &mmTCA_CTRL[0], sizeof(mmTCA_CTRL)/sizeof(mmTCA_CTRL[0]), 0, 0 }, + { "mmTCA_BURST_MASK", REG_MMIO, 0x0bc1, 0, &mmTCA_BURST_MASK[0], sizeof(mmTCA_BURST_MASK)/sizeof(mmTCA_BURST_MASK[0]), 0, 0 }, + { "mmTCA_BURST_CTRL", REG_MMIO, 0x0bc2, 0, &mmTCA_BURST_CTRL[0], sizeof(mmTCA_BURST_CTRL)/sizeof(mmTCA_BURST_CTRL[0]), 0, 0 }, + { "mmTCA_DSM_CNTL", REG_MMIO, 0x0bc3, 0, &mmTCA_DSM_CNTL[0], sizeof(mmTCA_DSM_CNTL)/sizeof(mmTCA_DSM_CNTL[0]), 0, 0 }, + { "mmTCA_DSM_CNTL2", REG_MMIO, 0x0bc4, 0, &mmTCA_DSM_CNTL2[0], sizeof(mmTCA_DSM_CNTL2)/sizeof(mmTCA_DSM_CNTL2[0]), 0, 0 }, + { "mmTCA_EDC_CNT", REG_MMIO, 0x0bc5, 0, &mmTCA_EDC_CNT[0], sizeof(mmTCA_EDC_CNT)/sizeof(mmTCA_EDC_CNT[0]), 0, 0 }, + { "mmSPI_SHADER_PGM_RSRC3_PS", REG_MMIO, 0x0c07, 0, &mmSPI_SHADER_PGM_RSRC3_PS[0], sizeof(mmSPI_SHADER_PGM_RSRC3_PS)/sizeof(mmSPI_SHADER_PGM_RSRC3_PS[0]), 0, 0 }, + { "mmSPI_SHADER_PGM_LO_PS", REG_MMIO, 0x0c08, 0, &mmSPI_SHADER_PGM_LO_PS[0], sizeof(mmSPI_SHADER_PGM_LO_PS)/sizeof(mmSPI_SHADER_PGM_LO_PS[0]), 0, 0 }, + { "mmSPI_SHADER_PGM_HI_PS", REG_MMIO, 0x0c09, 0, &mmSPI_SHADER_PGM_HI_PS[0], sizeof(mmSPI_SHADER_PGM_HI_PS)/sizeof(mmSPI_SHADER_PGM_HI_PS[0]), 0, 0 }, + { "mmSPI_SHADER_PGM_RSRC1_PS", REG_MMIO, 0x0c0a, 0, &mmSPI_SHADER_PGM_RSRC1_PS[0], sizeof(mmSPI_SHADER_PGM_RSRC1_PS)/sizeof(mmSPI_SHADER_PGM_RSRC1_PS[0]), 0, 0 }, + { "mmSPI_SHADER_PGM_RSRC2_PS", REG_MMIO, 0x0c0b, 0, &mmSPI_SHADER_PGM_RSRC2_PS[0], sizeof(mmSPI_SHADER_PGM_RSRC2_PS)/sizeof(mmSPI_SHADER_PGM_RSRC2_PS[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_PS_0", REG_MMIO, 0x0c0c, 0, &mmSPI_SHADER_USER_DATA_PS_0[0], sizeof(mmSPI_SHADER_USER_DATA_PS_0)/sizeof(mmSPI_SHADER_USER_DATA_PS_0[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_PS_1", REG_MMIO, 0x0c0d, 0, &mmSPI_SHADER_USER_DATA_PS_1[0], sizeof(mmSPI_SHADER_USER_DATA_PS_1)/sizeof(mmSPI_SHADER_USER_DATA_PS_1[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_PS_2", REG_MMIO, 0x0c0e, 0, &mmSPI_SHADER_USER_DATA_PS_2[0], sizeof(mmSPI_SHADER_USER_DATA_PS_2)/sizeof(mmSPI_SHADER_USER_DATA_PS_2[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_PS_3", REG_MMIO, 0x0c0f, 0, &mmSPI_SHADER_USER_DATA_PS_3[0], sizeof(mmSPI_SHADER_USER_DATA_PS_3)/sizeof(mmSPI_SHADER_USER_DATA_PS_3[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_PS_4", REG_MMIO, 0x0c10, 0, &mmSPI_SHADER_USER_DATA_PS_4[0], sizeof(mmSPI_SHADER_USER_DATA_PS_4)/sizeof(mmSPI_SHADER_USER_DATA_PS_4[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_PS_5", REG_MMIO, 0x0c11, 0, &mmSPI_SHADER_USER_DATA_PS_5[0], sizeof(mmSPI_SHADER_USER_DATA_PS_5)/sizeof(mmSPI_SHADER_USER_DATA_PS_5[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_PS_6", REG_MMIO, 0x0c12, 0, &mmSPI_SHADER_USER_DATA_PS_6[0], sizeof(mmSPI_SHADER_USER_DATA_PS_6)/sizeof(mmSPI_SHADER_USER_DATA_PS_6[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_PS_7", REG_MMIO, 0x0c13, 0, &mmSPI_SHADER_USER_DATA_PS_7[0], sizeof(mmSPI_SHADER_USER_DATA_PS_7)/sizeof(mmSPI_SHADER_USER_DATA_PS_7[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_PS_8", REG_MMIO, 0x0c14, 0, &mmSPI_SHADER_USER_DATA_PS_8[0], sizeof(mmSPI_SHADER_USER_DATA_PS_8)/sizeof(mmSPI_SHADER_USER_DATA_PS_8[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_PS_9", REG_MMIO, 0x0c15, 0, &mmSPI_SHADER_USER_DATA_PS_9[0], sizeof(mmSPI_SHADER_USER_DATA_PS_9)/sizeof(mmSPI_SHADER_USER_DATA_PS_9[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_PS_10", REG_MMIO, 0x0c16, 0, &mmSPI_SHADER_USER_DATA_PS_10[0], sizeof(mmSPI_SHADER_USER_DATA_PS_10)/sizeof(mmSPI_SHADER_USER_DATA_PS_10[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_PS_11", REG_MMIO, 0x0c17, 0, &mmSPI_SHADER_USER_DATA_PS_11[0], sizeof(mmSPI_SHADER_USER_DATA_PS_11)/sizeof(mmSPI_SHADER_USER_DATA_PS_11[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_PS_12", REG_MMIO, 0x0c18, 0, &mmSPI_SHADER_USER_DATA_PS_12[0], sizeof(mmSPI_SHADER_USER_DATA_PS_12)/sizeof(mmSPI_SHADER_USER_DATA_PS_12[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_PS_13", REG_MMIO, 0x0c19, 0, &mmSPI_SHADER_USER_DATA_PS_13[0], sizeof(mmSPI_SHADER_USER_DATA_PS_13)/sizeof(mmSPI_SHADER_USER_DATA_PS_13[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_PS_14", REG_MMIO, 0x0c1a, 0, &mmSPI_SHADER_USER_DATA_PS_14[0], sizeof(mmSPI_SHADER_USER_DATA_PS_14)/sizeof(mmSPI_SHADER_USER_DATA_PS_14[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_PS_15", REG_MMIO, 0x0c1b, 0, &mmSPI_SHADER_USER_DATA_PS_15[0], sizeof(mmSPI_SHADER_USER_DATA_PS_15)/sizeof(mmSPI_SHADER_USER_DATA_PS_15[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_PS_16", REG_MMIO, 0x0c1c, 0, &mmSPI_SHADER_USER_DATA_PS_16[0], sizeof(mmSPI_SHADER_USER_DATA_PS_16)/sizeof(mmSPI_SHADER_USER_DATA_PS_16[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_PS_17", REG_MMIO, 0x0c1d, 0, &mmSPI_SHADER_USER_DATA_PS_17[0], sizeof(mmSPI_SHADER_USER_DATA_PS_17)/sizeof(mmSPI_SHADER_USER_DATA_PS_17[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_PS_18", REG_MMIO, 0x0c1e, 0, &mmSPI_SHADER_USER_DATA_PS_18[0], sizeof(mmSPI_SHADER_USER_DATA_PS_18)/sizeof(mmSPI_SHADER_USER_DATA_PS_18[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_PS_19", REG_MMIO, 0x0c1f, 0, &mmSPI_SHADER_USER_DATA_PS_19[0], sizeof(mmSPI_SHADER_USER_DATA_PS_19)/sizeof(mmSPI_SHADER_USER_DATA_PS_19[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_PS_20", REG_MMIO, 0x0c20, 0, &mmSPI_SHADER_USER_DATA_PS_20[0], sizeof(mmSPI_SHADER_USER_DATA_PS_20)/sizeof(mmSPI_SHADER_USER_DATA_PS_20[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_PS_21", REG_MMIO, 0x0c21, 0, &mmSPI_SHADER_USER_DATA_PS_21[0], sizeof(mmSPI_SHADER_USER_DATA_PS_21)/sizeof(mmSPI_SHADER_USER_DATA_PS_21[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_PS_22", REG_MMIO, 0x0c22, 0, &mmSPI_SHADER_USER_DATA_PS_22[0], sizeof(mmSPI_SHADER_USER_DATA_PS_22)/sizeof(mmSPI_SHADER_USER_DATA_PS_22[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_PS_23", REG_MMIO, 0x0c23, 0, &mmSPI_SHADER_USER_DATA_PS_23[0], sizeof(mmSPI_SHADER_USER_DATA_PS_23)/sizeof(mmSPI_SHADER_USER_DATA_PS_23[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_PS_24", REG_MMIO, 0x0c24, 0, &mmSPI_SHADER_USER_DATA_PS_24[0], sizeof(mmSPI_SHADER_USER_DATA_PS_24)/sizeof(mmSPI_SHADER_USER_DATA_PS_24[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_PS_25", REG_MMIO, 0x0c25, 0, &mmSPI_SHADER_USER_DATA_PS_25[0], sizeof(mmSPI_SHADER_USER_DATA_PS_25)/sizeof(mmSPI_SHADER_USER_DATA_PS_25[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_PS_26", REG_MMIO, 0x0c26, 0, &mmSPI_SHADER_USER_DATA_PS_26[0], sizeof(mmSPI_SHADER_USER_DATA_PS_26)/sizeof(mmSPI_SHADER_USER_DATA_PS_26[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_PS_27", REG_MMIO, 0x0c27, 0, &mmSPI_SHADER_USER_DATA_PS_27[0], sizeof(mmSPI_SHADER_USER_DATA_PS_27)/sizeof(mmSPI_SHADER_USER_DATA_PS_27[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_PS_28", REG_MMIO, 0x0c28, 0, &mmSPI_SHADER_USER_DATA_PS_28[0], sizeof(mmSPI_SHADER_USER_DATA_PS_28)/sizeof(mmSPI_SHADER_USER_DATA_PS_28[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_PS_29", REG_MMIO, 0x0c29, 0, &mmSPI_SHADER_USER_DATA_PS_29[0], sizeof(mmSPI_SHADER_USER_DATA_PS_29)/sizeof(mmSPI_SHADER_USER_DATA_PS_29[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_PS_30", REG_MMIO, 0x0c2a, 0, &mmSPI_SHADER_USER_DATA_PS_30[0], sizeof(mmSPI_SHADER_USER_DATA_PS_30)/sizeof(mmSPI_SHADER_USER_DATA_PS_30[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_PS_31", REG_MMIO, 0x0c2b, 0, &mmSPI_SHADER_USER_DATA_PS_31[0], sizeof(mmSPI_SHADER_USER_DATA_PS_31)/sizeof(mmSPI_SHADER_USER_DATA_PS_31[0]), 0, 0 }, + { "mmSPI_SHADER_PGM_RSRC3_VS", REG_MMIO, 0x0c46, 0, &mmSPI_SHADER_PGM_RSRC3_VS[0], sizeof(mmSPI_SHADER_PGM_RSRC3_VS)/sizeof(mmSPI_SHADER_PGM_RSRC3_VS[0]), 0, 0 }, + { "mmSPI_SHADER_LATE_ALLOC_VS", REG_MMIO, 0x0c47, 0, &mmSPI_SHADER_LATE_ALLOC_VS[0], sizeof(mmSPI_SHADER_LATE_ALLOC_VS)/sizeof(mmSPI_SHADER_LATE_ALLOC_VS[0]), 0, 0 }, + { "mmSPI_SHADER_PGM_LO_VS", REG_MMIO, 0x0c48, 0, &mmSPI_SHADER_PGM_LO_VS[0], sizeof(mmSPI_SHADER_PGM_LO_VS)/sizeof(mmSPI_SHADER_PGM_LO_VS[0]), 0, 0 }, + { "mmSPI_SHADER_PGM_HI_VS", REG_MMIO, 0x0c49, 0, &mmSPI_SHADER_PGM_HI_VS[0], sizeof(mmSPI_SHADER_PGM_HI_VS)/sizeof(mmSPI_SHADER_PGM_HI_VS[0]), 0, 0 }, + { "mmSPI_SHADER_PGM_RSRC1_VS", REG_MMIO, 0x0c4a, 0, &mmSPI_SHADER_PGM_RSRC1_VS[0], sizeof(mmSPI_SHADER_PGM_RSRC1_VS)/sizeof(mmSPI_SHADER_PGM_RSRC1_VS[0]), 0, 0 }, + { "mmSPI_SHADER_PGM_RSRC2_VS", REG_MMIO, 0x0c4b, 0, &mmSPI_SHADER_PGM_RSRC2_VS[0], sizeof(mmSPI_SHADER_PGM_RSRC2_VS)/sizeof(mmSPI_SHADER_PGM_RSRC2_VS[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_VS_0", REG_MMIO, 0x0c4c, 0, &mmSPI_SHADER_USER_DATA_VS_0[0], sizeof(mmSPI_SHADER_USER_DATA_VS_0)/sizeof(mmSPI_SHADER_USER_DATA_VS_0[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_VS_1", REG_MMIO, 0x0c4d, 0, &mmSPI_SHADER_USER_DATA_VS_1[0], sizeof(mmSPI_SHADER_USER_DATA_VS_1)/sizeof(mmSPI_SHADER_USER_DATA_VS_1[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_VS_2", REG_MMIO, 0x0c4e, 0, &mmSPI_SHADER_USER_DATA_VS_2[0], sizeof(mmSPI_SHADER_USER_DATA_VS_2)/sizeof(mmSPI_SHADER_USER_DATA_VS_2[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_VS_3", REG_MMIO, 0x0c4f, 0, &mmSPI_SHADER_USER_DATA_VS_3[0], sizeof(mmSPI_SHADER_USER_DATA_VS_3)/sizeof(mmSPI_SHADER_USER_DATA_VS_3[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_VS_4", REG_MMIO, 0x0c50, 0, &mmSPI_SHADER_USER_DATA_VS_4[0], sizeof(mmSPI_SHADER_USER_DATA_VS_4)/sizeof(mmSPI_SHADER_USER_DATA_VS_4[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_VS_5", REG_MMIO, 0x0c51, 0, &mmSPI_SHADER_USER_DATA_VS_5[0], sizeof(mmSPI_SHADER_USER_DATA_VS_5)/sizeof(mmSPI_SHADER_USER_DATA_VS_5[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_VS_6", REG_MMIO, 0x0c52, 0, &mmSPI_SHADER_USER_DATA_VS_6[0], sizeof(mmSPI_SHADER_USER_DATA_VS_6)/sizeof(mmSPI_SHADER_USER_DATA_VS_6[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_VS_7", REG_MMIO, 0x0c53, 0, &mmSPI_SHADER_USER_DATA_VS_7[0], sizeof(mmSPI_SHADER_USER_DATA_VS_7)/sizeof(mmSPI_SHADER_USER_DATA_VS_7[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_VS_8", REG_MMIO, 0x0c54, 0, &mmSPI_SHADER_USER_DATA_VS_8[0], sizeof(mmSPI_SHADER_USER_DATA_VS_8)/sizeof(mmSPI_SHADER_USER_DATA_VS_8[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_VS_9", REG_MMIO, 0x0c55, 0, &mmSPI_SHADER_USER_DATA_VS_9[0], sizeof(mmSPI_SHADER_USER_DATA_VS_9)/sizeof(mmSPI_SHADER_USER_DATA_VS_9[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_VS_10", REG_MMIO, 0x0c56, 0, &mmSPI_SHADER_USER_DATA_VS_10[0], sizeof(mmSPI_SHADER_USER_DATA_VS_10)/sizeof(mmSPI_SHADER_USER_DATA_VS_10[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_VS_11", REG_MMIO, 0x0c57, 0, &mmSPI_SHADER_USER_DATA_VS_11[0], sizeof(mmSPI_SHADER_USER_DATA_VS_11)/sizeof(mmSPI_SHADER_USER_DATA_VS_11[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_VS_12", REG_MMIO, 0x0c58, 0, &mmSPI_SHADER_USER_DATA_VS_12[0], sizeof(mmSPI_SHADER_USER_DATA_VS_12)/sizeof(mmSPI_SHADER_USER_DATA_VS_12[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_VS_13", REG_MMIO, 0x0c59, 0, &mmSPI_SHADER_USER_DATA_VS_13[0], sizeof(mmSPI_SHADER_USER_DATA_VS_13)/sizeof(mmSPI_SHADER_USER_DATA_VS_13[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_VS_14", REG_MMIO, 0x0c5a, 0, &mmSPI_SHADER_USER_DATA_VS_14[0], sizeof(mmSPI_SHADER_USER_DATA_VS_14)/sizeof(mmSPI_SHADER_USER_DATA_VS_14[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_VS_15", REG_MMIO, 0x0c5b, 0, &mmSPI_SHADER_USER_DATA_VS_15[0], sizeof(mmSPI_SHADER_USER_DATA_VS_15)/sizeof(mmSPI_SHADER_USER_DATA_VS_15[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_VS_16", REG_MMIO, 0x0c5c, 0, &mmSPI_SHADER_USER_DATA_VS_16[0], sizeof(mmSPI_SHADER_USER_DATA_VS_16)/sizeof(mmSPI_SHADER_USER_DATA_VS_16[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_VS_17", REG_MMIO, 0x0c5d, 0, &mmSPI_SHADER_USER_DATA_VS_17[0], sizeof(mmSPI_SHADER_USER_DATA_VS_17)/sizeof(mmSPI_SHADER_USER_DATA_VS_17[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_VS_18", REG_MMIO, 0x0c5e, 0, &mmSPI_SHADER_USER_DATA_VS_18[0], sizeof(mmSPI_SHADER_USER_DATA_VS_18)/sizeof(mmSPI_SHADER_USER_DATA_VS_18[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_VS_19", REG_MMIO, 0x0c5f, 0, &mmSPI_SHADER_USER_DATA_VS_19[0], sizeof(mmSPI_SHADER_USER_DATA_VS_19)/sizeof(mmSPI_SHADER_USER_DATA_VS_19[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_VS_20", REG_MMIO, 0x0c60, 0, &mmSPI_SHADER_USER_DATA_VS_20[0], sizeof(mmSPI_SHADER_USER_DATA_VS_20)/sizeof(mmSPI_SHADER_USER_DATA_VS_20[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_VS_21", REG_MMIO, 0x0c61, 0, &mmSPI_SHADER_USER_DATA_VS_21[0], sizeof(mmSPI_SHADER_USER_DATA_VS_21)/sizeof(mmSPI_SHADER_USER_DATA_VS_21[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_VS_22", REG_MMIO, 0x0c62, 0, &mmSPI_SHADER_USER_DATA_VS_22[0], sizeof(mmSPI_SHADER_USER_DATA_VS_22)/sizeof(mmSPI_SHADER_USER_DATA_VS_22[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_VS_23", REG_MMIO, 0x0c63, 0, &mmSPI_SHADER_USER_DATA_VS_23[0], sizeof(mmSPI_SHADER_USER_DATA_VS_23)/sizeof(mmSPI_SHADER_USER_DATA_VS_23[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_VS_24", REG_MMIO, 0x0c64, 0, &mmSPI_SHADER_USER_DATA_VS_24[0], sizeof(mmSPI_SHADER_USER_DATA_VS_24)/sizeof(mmSPI_SHADER_USER_DATA_VS_24[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_VS_25", REG_MMIO, 0x0c65, 0, &mmSPI_SHADER_USER_DATA_VS_25[0], sizeof(mmSPI_SHADER_USER_DATA_VS_25)/sizeof(mmSPI_SHADER_USER_DATA_VS_25[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_VS_26", REG_MMIO, 0x0c66, 0, &mmSPI_SHADER_USER_DATA_VS_26[0], sizeof(mmSPI_SHADER_USER_DATA_VS_26)/sizeof(mmSPI_SHADER_USER_DATA_VS_26[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_VS_27", REG_MMIO, 0x0c67, 0, &mmSPI_SHADER_USER_DATA_VS_27[0], sizeof(mmSPI_SHADER_USER_DATA_VS_27)/sizeof(mmSPI_SHADER_USER_DATA_VS_27[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_VS_28", REG_MMIO, 0x0c68, 0, &mmSPI_SHADER_USER_DATA_VS_28[0], sizeof(mmSPI_SHADER_USER_DATA_VS_28)/sizeof(mmSPI_SHADER_USER_DATA_VS_28[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_VS_29", REG_MMIO, 0x0c69, 0, &mmSPI_SHADER_USER_DATA_VS_29[0], sizeof(mmSPI_SHADER_USER_DATA_VS_29)/sizeof(mmSPI_SHADER_USER_DATA_VS_29[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_VS_30", REG_MMIO, 0x0c6a, 0, &mmSPI_SHADER_USER_DATA_VS_30[0], sizeof(mmSPI_SHADER_USER_DATA_VS_30)/sizeof(mmSPI_SHADER_USER_DATA_VS_30[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_VS_31", REG_MMIO, 0x0c6b, 0, &mmSPI_SHADER_USER_DATA_VS_31[0], sizeof(mmSPI_SHADER_USER_DATA_VS_31)/sizeof(mmSPI_SHADER_USER_DATA_VS_31[0]), 0, 0 }, + { "mmSPI_SHADER_PGM_RSRC2_GS_VS", REG_MMIO, 0x0c7c, 0, &mmSPI_SHADER_PGM_RSRC2_GS_VS[0], sizeof(mmSPI_SHADER_PGM_RSRC2_GS_VS)/sizeof(mmSPI_SHADER_PGM_RSRC2_GS_VS[0]), 0, 0 }, + { "mmSPI_SHADER_PGM_RSRC4_GS", REG_MMIO, 0x0c81, 0, &mmSPI_SHADER_PGM_RSRC4_GS[0], sizeof(mmSPI_SHADER_PGM_RSRC4_GS)/sizeof(mmSPI_SHADER_PGM_RSRC4_GS[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_ADDR_LO_GS", REG_MMIO, 0x0c82, 0, &mmSPI_SHADER_USER_DATA_ADDR_LO_GS[0], sizeof(mmSPI_SHADER_USER_DATA_ADDR_LO_GS)/sizeof(mmSPI_SHADER_USER_DATA_ADDR_LO_GS[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_ADDR_HI_GS", REG_MMIO, 0x0c83, 0, &mmSPI_SHADER_USER_DATA_ADDR_HI_GS[0], sizeof(mmSPI_SHADER_USER_DATA_ADDR_HI_GS)/sizeof(mmSPI_SHADER_USER_DATA_ADDR_HI_GS[0]), 0, 0 }, + { "mmSPI_SHADER_PGM_LO_ES", REG_MMIO, 0x0c84, 0, &mmSPI_SHADER_PGM_LO_ES[0], sizeof(mmSPI_SHADER_PGM_LO_ES)/sizeof(mmSPI_SHADER_PGM_LO_ES[0]), 0, 0 }, + { "mmSPI_SHADER_PGM_HI_ES", REG_MMIO, 0x0c85, 0, &mmSPI_SHADER_PGM_HI_ES[0], sizeof(mmSPI_SHADER_PGM_HI_ES)/sizeof(mmSPI_SHADER_PGM_HI_ES[0]), 0, 0 }, + { "mmSPI_SHADER_PGM_RSRC3_GS", REG_MMIO, 0x0c87, 0, &mmSPI_SHADER_PGM_RSRC3_GS[0], sizeof(mmSPI_SHADER_PGM_RSRC3_GS)/sizeof(mmSPI_SHADER_PGM_RSRC3_GS[0]), 0, 0 }, + { "mmSPI_SHADER_PGM_LO_GS", REG_MMIO, 0x0c88, 0, &mmSPI_SHADER_PGM_LO_GS[0], sizeof(mmSPI_SHADER_PGM_LO_GS)/sizeof(mmSPI_SHADER_PGM_LO_GS[0]), 0, 0 }, + { "mmSPI_SHADER_PGM_HI_GS", REG_MMIO, 0x0c89, 0, &mmSPI_SHADER_PGM_HI_GS[0], sizeof(mmSPI_SHADER_PGM_HI_GS)/sizeof(mmSPI_SHADER_PGM_HI_GS[0]), 0, 0 }, + { "mmSPI_SHADER_PGM_RSRC1_GS", REG_MMIO, 0x0c8a, 0, &mmSPI_SHADER_PGM_RSRC1_GS[0], sizeof(mmSPI_SHADER_PGM_RSRC1_GS)/sizeof(mmSPI_SHADER_PGM_RSRC1_GS[0]), 0, 0 }, + { "mmSPI_SHADER_PGM_RSRC2_GS", REG_MMIO, 0x0c8b, 0, &mmSPI_SHADER_PGM_RSRC2_GS[0], sizeof(mmSPI_SHADER_PGM_RSRC2_GS)/sizeof(mmSPI_SHADER_PGM_RSRC2_GS[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_ES_0", REG_MMIO, 0x0ccc, 0, &mmSPI_SHADER_USER_DATA_ES_0[0], sizeof(mmSPI_SHADER_USER_DATA_ES_0)/sizeof(mmSPI_SHADER_USER_DATA_ES_0[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_ES_1", REG_MMIO, 0x0ccd, 0, &mmSPI_SHADER_USER_DATA_ES_1[0], sizeof(mmSPI_SHADER_USER_DATA_ES_1)/sizeof(mmSPI_SHADER_USER_DATA_ES_1[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_ES_2", REG_MMIO, 0x0cce, 0, &mmSPI_SHADER_USER_DATA_ES_2[0], sizeof(mmSPI_SHADER_USER_DATA_ES_2)/sizeof(mmSPI_SHADER_USER_DATA_ES_2[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_ES_3", REG_MMIO, 0x0ccf, 0, &mmSPI_SHADER_USER_DATA_ES_3[0], sizeof(mmSPI_SHADER_USER_DATA_ES_3)/sizeof(mmSPI_SHADER_USER_DATA_ES_3[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_ES_4", REG_MMIO, 0x0cd0, 0, &mmSPI_SHADER_USER_DATA_ES_4[0], sizeof(mmSPI_SHADER_USER_DATA_ES_4)/sizeof(mmSPI_SHADER_USER_DATA_ES_4[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_ES_5", REG_MMIO, 0x0cd1, 0, &mmSPI_SHADER_USER_DATA_ES_5[0], sizeof(mmSPI_SHADER_USER_DATA_ES_5)/sizeof(mmSPI_SHADER_USER_DATA_ES_5[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_ES_6", REG_MMIO, 0x0cd2, 0, &mmSPI_SHADER_USER_DATA_ES_6[0], sizeof(mmSPI_SHADER_USER_DATA_ES_6)/sizeof(mmSPI_SHADER_USER_DATA_ES_6[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_ES_7", REG_MMIO, 0x0cd3, 0, &mmSPI_SHADER_USER_DATA_ES_7[0], sizeof(mmSPI_SHADER_USER_DATA_ES_7)/sizeof(mmSPI_SHADER_USER_DATA_ES_7[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_ES_8", REG_MMIO, 0x0cd4, 0, &mmSPI_SHADER_USER_DATA_ES_8[0], sizeof(mmSPI_SHADER_USER_DATA_ES_8)/sizeof(mmSPI_SHADER_USER_DATA_ES_8[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_ES_9", REG_MMIO, 0x0cd5, 0, &mmSPI_SHADER_USER_DATA_ES_9[0], sizeof(mmSPI_SHADER_USER_DATA_ES_9)/sizeof(mmSPI_SHADER_USER_DATA_ES_9[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_ES_10", REG_MMIO, 0x0cd6, 0, &mmSPI_SHADER_USER_DATA_ES_10[0], sizeof(mmSPI_SHADER_USER_DATA_ES_10)/sizeof(mmSPI_SHADER_USER_DATA_ES_10[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_ES_11", REG_MMIO, 0x0cd7, 0, &mmSPI_SHADER_USER_DATA_ES_11[0], sizeof(mmSPI_SHADER_USER_DATA_ES_11)/sizeof(mmSPI_SHADER_USER_DATA_ES_11[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_ES_12", REG_MMIO, 0x0cd8, 0, &mmSPI_SHADER_USER_DATA_ES_12[0], sizeof(mmSPI_SHADER_USER_DATA_ES_12)/sizeof(mmSPI_SHADER_USER_DATA_ES_12[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_ES_13", REG_MMIO, 0x0cd9, 0, &mmSPI_SHADER_USER_DATA_ES_13[0], sizeof(mmSPI_SHADER_USER_DATA_ES_13)/sizeof(mmSPI_SHADER_USER_DATA_ES_13[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_ES_14", REG_MMIO, 0x0cda, 0, &mmSPI_SHADER_USER_DATA_ES_14[0], sizeof(mmSPI_SHADER_USER_DATA_ES_14)/sizeof(mmSPI_SHADER_USER_DATA_ES_14[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_ES_15", REG_MMIO, 0x0cdb, 0, &mmSPI_SHADER_USER_DATA_ES_15[0], sizeof(mmSPI_SHADER_USER_DATA_ES_15)/sizeof(mmSPI_SHADER_USER_DATA_ES_15[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_ES_16", REG_MMIO, 0x0cdc, 0, &mmSPI_SHADER_USER_DATA_ES_16[0], sizeof(mmSPI_SHADER_USER_DATA_ES_16)/sizeof(mmSPI_SHADER_USER_DATA_ES_16[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_ES_17", REG_MMIO, 0x0cdd, 0, &mmSPI_SHADER_USER_DATA_ES_17[0], sizeof(mmSPI_SHADER_USER_DATA_ES_17)/sizeof(mmSPI_SHADER_USER_DATA_ES_17[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_ES_18", REG_MMIO, 0x0cde, 0, &mmSPI_SHADER_USER_DATA_ES_18[0], sizeof(mmSPI_SHADER_USER_DATA_ES_18)/sizeof(mmSPI_SHADER_USER_DATA_ES_18[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_ES_19", REG_MMIO, 0x0cdf, 0, &mmSPI_SHADER_USER_DATA_ES_19[0], sizeof(mmSPI_SHADER_USER_DATA_ES_19)/sizeof(mmSPI_SHADER_USER_DATA_ES_19[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_ES_20", REG_MMIO, 0x0ce0, 0, &mmSPI_SHADER_USER_DATA_ES_20[0], sizeof(mmSPI_SHADER_USER_DATA_ES_20)/sizeof(mmSPI_SHADER_USER_DATA_ES_20[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_ES_21", REG_MMIO, 0x0ce1, 0, &mmSPI_SHADER_USER_DATA_ES_21[0], sizeof(mmSPI_SHADER_USER_DATA_ES_21)/sizeof(mmSPI_SHADER_USER_DATA_ES_21[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_ES_22", REG_MMIO, 0x0ce2, 0, &mmSPI_SHADER_USER_DATA_ES_22[0], sizeof(mmSPI_SHADER_USER_DATA_ES_22)/sizeof(mmSPI_SHADER_USER_DATA_ES_22[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_ES_23", REG_MMIO, 0x0ce3, 0, &mmSPI_SHADER_USER_DATA_ES_23[0], sizeof(mmSPI_SHADER_USER_DATA_ES_23)/sizeof(mmSPI_SHADER_USER_DATA_ES_23[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_ES_24", REG_MMIO, 0x0ce4, 0, &mmSPI_SHADER_USER_DATA_ES_24[0], sizeof(mmSPI_SHADER_USER_DATA_ES_24)/sizeof(mmSPI_SHADER_USER_DATA_ES_24[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_ES_25", REG_MMIO, 0x0ce5, 0, &mmSPI_SHADER_USER_DATA_ES_25[0], sizeof(mmSPI_SHADER_USER_DATA_ES_25)/sizeof(mmSPI_SHADER_USER_DATA_ES_25[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_ES_26", REG_MMIO, 0x0ce6, 0, &mmSPI_SHADER_USER_DATA_ES_26[0], sizeof(mmSPI_SHADER_USER_DATA_ES_26)/sizeof(mmSPI_SHADER_USER_DATA_ES_26[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_ES_27", REG_MMIO, 0x0ce7, 0, &mmSPI_SHADER_USER_DATA_ES_27[0], sizeof(mmSPI_SHADER_USER_DATA_ES_27)/sizeof(mmSPI_SHADER_USER_DATA_ES_27[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_ES_28", REG_MMIO, 0x0ce8, 0, &mmSPI_SHADER_USER_DATA_ES_28[0], sizeof(mmSPI_SHADER_USER_DATA_ES_28)/sizeof(mmSPI_SHADER_USER_DATA_ES_28[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_ES_29", REG_MMIO, 0x0ce9, 0, &mmSPI_SHADER_USER_DATA_ES_29[0], sizeof(mmSPI_SHADER_USER_DATA_ES_29)/sizeof(mmSPI_SHADER_USER_DATA_ES_29[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_ES_30", REG_MMIO, 0x0cea, 0, &mmSPI_SHADER_USER_DATA_ES_30[0], sizeof(mmSPI_SHADER_USER_DATA_ES_30)/sizeof(mmSPI_SHADER_USER_DATA_ES_30[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_ES_31", REG_MMIO, 0x0ceb, 0, &mmSPI_SHADER_USER_DATA_ES_31[0], sizeof(mmSPI_SHADER_USER_DATA_ES_31)/sizeof(mmSPI_SHADER_USER_DATA_ES_31[0]), 0, 0 }, + { "mmSPI_SHADER_PGM_RSRC4_HS", REG_MMIO, 0x0d01, 0, &mmSPI_SHADER_PGM_RSRC4_HS[0], sizeof(mmSPI_SHADER_PGM_RSRC4_HS)/sizeof(mmSPI_SHADER_PGM_RSRC4_HS[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_ADDR_LO_HS", REG_MMIO, 0x0d02, 0, &mmSPI_SHADER_USER_DATA_ADDR_LO_HS[0], sizeof(mmSPI_SHADER_USER_DATA_ADDR_LO_HS)/sizeof(mmSPI_SHADER_USER_DATA_ADDR_LO_HS[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_ADDR_HI_HS", REG_MMIO, 0x0d03, 0, &mmSPI_SHADER_USER_DATA_ADDR_HI_HS[0], sizeof(mmSPI_SHADER_USER_DATA_ADDR_HI_HS)/sizeof(mmSPI_SHADER_USER_DATA_ADDR_HI_HS[0]), 0, 0 }, + { "mmSPI_SHADER_PGM_LO_LS", REG_MMIO, 0x0d04, 0, &mmSPI_SHADER_PGM_LO_LS[0], sizeof(mmSPI_SHADER_PGM_LO_LS)/sizeof(mmSPI_SHADER_PGM_LO_LS[0]), 0, 0 }, + { "mmSPI_SHADER_PGM_HI_LS", REG_MMIO, 0x0d05, 0, &mmSPI_SHADER_PGM_HI_LS[0], sizeof(mmSPI_SHADER_PGM_HI_LS)/sizeof(mmSPI_SHADER_PGM_HI_LS[0]), 0, 0 }, + { "mmSPI_SHADER_PGM_RSRC3_HS", REG_MMIO, 0x0d07, 0, &mmSPI_SHADER_PGM_RSRC3_HS[0], sizeof(mmSPI_SHADER_PGM_RSRC3_HS)/sizeof(mmSPI_SHADER_PGM_RSRC3_HS[0]), 0, 0 }, + { "mmSPI_SHADER_PGM_LO_HS", REG_MMIO, 0x0d08, 0, &mmSPI_SHADER_PGM_LO_HS[0], sizeof(mmSPI_SHADER_PGM_LO_HS)/sizeof(mmSPI_SHADER_PGM_LO_HS[0]), 0, 0 }, + { "mmSPI_SHADER_PGM_HI_HS", REG_MMIO, 0x0d09, 0, &mmSPI_SHADER_PGM_HI_HS[0], sizeof(mmSPI_SHADER_PGM_HI_HS)/sizeof(mmSPI_SHADER_PGM_HI_HS[0]), 0, 0 }, + { "mmSPI_SHADER_PGM_RSRC1_HS", REG_MMIO, 0x0d0a, 0, &mmSPI_SHADER_PGM_RSRC1_HS[0], sizeof(mmSPI_SHADER_PGM_RSRC1_HS)/sizeof(mmSPI_SHADER_PGM_RSRC1_HS[0]), 0, 0 }, + { "mmSPI_SHADER_PGM_RSRC2_HS", REG_MMIO, 0x0d0b, 0, &mmSPI_SHADER_PGM_RSRC2_HS[0], sizeof(mmSPI_SHADER_PGM_RSRC2_HS)/sizeof(mmSPI_SHADER_PGM_RSRC2_HS[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_LS_0", REG_MMIO, 0x0d0c, 0, &mmSPI_SHADER_USER_DATA_LS_0[0], sizeof(mmSPI_SHADER_USER_DATA_LS_0)/sizeof(mmSPI_SHADER_USER_DATA_LS_0[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_LS_1", REG_MMIO, 0x0d0d, 0, &mmSPI_SHADER_USER_DATA_LS_1[0], sizeof(mmSPI_SHADER_USER_DATA_LS_1)/sizeof(mmSPI_SHADER_USER_DATA_LS_1[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_LS_2", REG_MMIO, 0x0d0e, 0, &mmSPI_SHADER_USER_DATA_LS_2[0], sizeof(mmSPI_SHADER_USER_DATA_LS_2)/sizeof(mmSPI_SHADER_USER_DATA_LS_2[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_LS_3", REG_MMIO, 0x0d0f, 0, &mmSPI_SHADER_USER_DATA_LS_3[0], sizeof(mmSPI_SHADER_USER_DATA_LS_3)/sizeof(mmSPI_SHADER_USER_DATA_LS_3[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_LS_4", REG_MMIO, 0x0d10, 0, &mmSPI_SHADER_USER_DATA_LS_4[0], sizeof(mmSPI_SHADER_USER_DATA_LS_4)/sizeof(mmSPI_SHADER_USER_DATA_LS_4[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_LS_5", REG_MMIO, 0x0d11, 0, &mmSPI_SHADER_USER_DATA_LS_5[0], sizeof(mmSPI_SHADER_USER_DATA_LS_5)/sizeof(mmSPI_SHADER_USER_DATA_LS_5[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_LS_6", REG_MMIO, 0x0d12, 0, &mmSPI_SHADER_USER_DATA_LS_6[0], sizeof(mmSPI_SHADER_USER_DATA_LS_6)/sizeof(mmSPI_SHADER_USER_DATA_LS_6[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_LS_7", REG_MMIO, 0x0d13, 0, &mmSPI_SHADER_USER_DATA_LS_7[0], sizeof(mmSPI_SHADER_USER_DATA_LS_7)/sizeof(mmSPI_SHADER_USER_DATA_LS_7[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_LS_8", REG_MMIO, 0x0d14, 0, &mmSPI_SHADER_USER_DATA_LS_8[0], sizeof(mmSPI_SHADER_USER_DATA_LS_8)/sizeof(mmSPI_SHADER_USER_DATA_LS_8[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_LS_9", REG_MMIO, 0x0d15, 0, &mmSPI_SHADER_USER_DATA_LS_9[0], sizeof(mmSPI_SHADER_USER_DATA_LS_9)/sizeof(mmSPI_SHADER_USER_DATA_LS_9[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_LS_10", REG_MMIO, 0x0d16, 0, &mmSPI_SHADER_USER_DATA_LS_10[0], sizeof(mmSPI_SHADER_USER_DATA_LS_10)/sizeof(mmSPI_SHADER_USER_DATA_LS_10[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_LS_11", REG_MMIO, 0x0d17, 0, &mmSPI_SHADER_USER_DATA_LS_11[0], sizeof(mmSPI_SHADER_USER_DATA_LS_11)/sizeof(mmSPI_SHADER_USER_DATA_LS_11[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_LS_12", REG_MMIO, 0x0d18, 0, &mmSPI_SHADER_USER_DATA_LS_12[0], sizeof(mmSPI_SHADER_USER_DATA_LS_12)/sizeof(mmSPI_SHADER_USER_DATA_LS_12[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_LS_13", REG_MMIO, 0x0d19, 0, &mmSPI_SHADER_USER_DATA_LS_13[0], sizeof(mmSPI_SHADER_USER_DATA_LS_13)/sizeof(mmSPI_SHADER_USER_DATA_LS_13[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_LS_14", REG_MMIO, 0x0d1a, 0, &mmSPI_SHADER_USER_DATA_LS_14[0], sizeof(mmSPI_SHADER_USER_DATA_LS_14)/sizeof(mmSPI_SHADER_USER_DATA_LS_14[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_LS_15", REG_MMIO, 0x0d1b, 0, &mmSPI_SHADER_USER_DATA_LS_15[0], sizeof(mmSPI_SHADER_USER_DATA_LS_15)/sizeof(mmSPI_SHADER_USER_DATA_LS_15[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_LS_16", REG_MMIO, 0x0d1c, 0, &mmSPI_SHADER_USER_DATA_LS_16[0], sizeof(mmSPI_SHADER_USER_DATA_LS_16)/sizeof(mmSPI_SHADER_USER_DATA_LS_16[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_LS_17", REG_MMIO, 0x0d1d, 0, &mmSPI_SHADER_USER_DATA_LS_17[0], sizeof(mmSPI_SHADER_USER_DATA_LS_17)/sizeof(mmSPI_SHADER_USER_DATA_LS_17[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_LS_18", REG_MMIO, 0x0d1e, 0, &mmSPI_SHADER_USER_DATA_LS_18[0], sizeof(mmSPI_SHADER_USER_DATA_LS_18)/sizeof(mmSPI_SHADER_USER_DATA_LS_18[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_LS_19", REG_MMIO, 0x0d1f, 0, &mmSPI_SHADER_USER_DATA_LS_19[0], sizeof(mmSPI_SHADER_USER_DATA_LS_19)/sizeof(mmSPI_SHADER_USER_DATA_LS_19[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_LS_20", REG_MMIO, 0x0d20, 0, &mmSPI_SHADER_USER_DATA_LS_20[0], sizeof(mmSPI_SHADER_USER_DATA_LS_20)/sizeof(mmSPI_SHADER_USER_DATA_LS_20[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_LS_21", REG_MMIO, 0x0d21, 0, &mmSPI_SHADER_USER_DATA_LS_21[0], sizeof(mmSPI_SHADER_USER_DATA_LS_21)/sizeof(mmSPI_SHADER_USER_DATA_LS_21[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_LS_22", REG_MMIO, 0x0d22, 0, &mmSPI_SHADER_USER_DATA_LS_22[0], sizeof(mmSPI_SHADER_USER_DATA_LS_22)/sizeof(mmSPI_SHADER_USER_DATA_LS_22[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_LS_23", REG_MMIO, 0x0d23, 0, &mmSPI_SHADER_USER_DATA_LS_23[0], sizeof(mmSPI_SHADER_USER_DATA_LS_23)/sizeof(mmSPI_SHADER_USER_DATA_LS_23[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_LS_24", REG_MMIO, 0x0d24, 0, &mmSPI_SHADER_USER_DATA_LS_24[0], sizeof(mmSPI_SHADER_USER_DATA_LS_24)/sizeof(mmSPI_SHADER_USER_DATA_LS_24[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_LS_25", REG_MMIO, 0x0d25, 0, &mmSPI_SHADER_USER_DATA_LS_25[0], sizeof(mmSPI_SHADER_USER_DATA_LS_25)/sizeof(mmSPI_SHADER_USER_DATA_LS_25[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_LS_26", REG_MMIO, 0x0d26, 0, &mmSPI_SHADER_USER_DATA_LS_26[0], sizeof(mmSPI_SHADER_USER_DATA_LS_26)/sizeof(mmSPI_SHADER_USER_DATA_LS_26[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_LS_27", REG_MMIO, 0x0d27, 0, &mmSPI_SHADER_USER_DATA_LS_27[0], sizeof(mmSPI_SHADER_USER_DATA_LS_27)/sizeof(mmSPI_SHADER_USER_DATA_LS_27[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_LS_28", REG_MMIO, 0x0d28, 0, &mmSPI_SHADER_USER_DATA_LS_28[0], sizeof(mmSPI_SHADER_USER_DATA_LS_28)/sizeof(mmSPI_SHADER_USER_DATA_LS_28[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_LS_29", REG_MMIO, 0x0d29, 0, &mmSPI_SHADER_USER_DATA_LS_29[0], sizeof(mmSPI_SHADER_USER_DATA_LS_29)/sizeof(mmSPI_SHADER_USER_DATA_LS_29[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_LS_30", REG_MMIO, 0x0d2a, 0, &mmSPI_SHADER_USER_DATA_LS_30[0], sizeof(mmSPI_SHADER_USER_DATA_LS_30)/sizeof(mmSPI_SHADER_USER_DATA_LS_30[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_LS_31", REG_MMIO, 0x0d2b, 0, &mmSPI_SHADER_USER_DATA_LS_31[0], sizeof(mmSPI_SHADER_USER_DATA_LS_31)/sizeof(mmSPI_SHADER_USER_DATA_LS_31[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_COMMON_0", REG_MMIO, 0x0d4c, 0, &mmSPI_SHADER_USER_DATA_COMMON_0[0], sizeof(mmSPI_SHADER_USER_DATA_COMMON_0)/sizeof(mmSPI_SHADER_USER_DATA_COMMON_0[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_COMMON_1", REG_MMIO, 0x0d4d, 0, &mmSPI_SHADER_USER_DATA_COMMON_1[0], sizeof(mmSPI_SHADER_USER_DATA_COMMON_1)/sizeof(mmSPI_SHADER_USER_DATA_COMMON_1[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_COMMON_2", REG_MMIO, 0x0d4e, 0, &mmSPI_SHADER_USER_DATA_COMMON_2[0], sizeof(mmSPI_SHADER_USER_DATA_COMMON_2)/sizeof(mmSPI_SHADER_USER_DATA_COMMON_2[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_COMMON_3", REG_MMIO, 0x0d4f, 0, &mmSPI_SHADER_USER_DATA_COMMON_3[0], sizeof(mmSPI_SHADER_USER_DATA_COMMON_3)/sizeof(mmSPI_SHADER_USER_DATA_COMMON_3[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_COMMON_4", REG_MMIO, 0x0d50, 0, &mmSPI_SHADER_USER_DATA_COMMON_4[0], sizeof(mmSPI_SHADER_USER_DATA_COMMON_4)/sizeof(mmSPI_SHADER_USER_DATA_COMMON_4[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_COMMON_5", REG_MMIO, 0x0d51, 0, &mmSPI_SHADER_USER_DATA_COMMON_5[0], sizeof(mmSPI_SHADER_USER_DATA_COMMON_5)/sizeof(mmSPI_SHADER_USER_DATA_COMMON_5[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_COMMON_6", REG_MMIO, 0x0d52, 0, &mmSPI_SHADER_USER_DATA_COMMON_6[0], sizeof(mmSPI_SHADER_USER_DATA_COMMON_6)/sizeof(mmSPI_SHADER_USER_DATA_COMMON_6[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_COMMON_7", REG_MMIO, 0x0d53, 0, &mmSPI_SHADER_USER_DATA_COMMON_7[0], sizeof(mmSPI_SHADER_USER_DATA_COMMON_7)/sizeof(mmSPI_SHADER_USER_DATA_COMMON_7[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_COMMON_8", REG_MMIO, 0x0d54, 0, &mmSPI_SHADER_USER_DATA_COMMON_8[0], sizeof(mmSPI_SHADER_USER_DATA_COMMON_8)/sizeof(mmSPI_SHADER_USER_DATA_COMMON_8[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_COMMON_9", REG_MMIO, 0x0d55, 0, &mmSPI_SHADER_USER_DATA_COMMON_9[0], sizeof(mmSPI_SHADER_USER_DATA_COMMON_9)/sizeof(mmSPI_SHADER_USER_DATA_COMMON_9[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_COMMON_10", REG_MMIO, 0x0d56, 0, &mmSPI_SHADER_USER_DATA_COMMON_10[0], sizeof(mmSPI_SHADER_USER_DATA_COMMON_10)/sizeof(mmSPI_SHADER_USER_DATA_COMMON_10[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_COMMON_11", REG_MMIO, 0x0d57, 0, &mmSPI_SHADER_USER_DATA_COMMON_11[0], sizeof(mmSPI_SHADER_USER_DATA_COMMON_11)/sizeof(mmSPI_SHADER_USER_DATA_COMMON_11[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_COMMON_12", REG_MMIO, 0x0d58, 0, &mmSPI_SHADER_USER_DATA_COMMON_12[0], sizeof(mmSPI_SHADER_USER_DATA_COMMON_12)/sizeof(mmSPI_SHADER_USER_DATA_COMMON_12[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_COMMON_13", REG_MMIO, 0x0d59, 0, &mmSPI_SHADER_USER_DATA_COMMON_13[0], sizeof(mmSPI_SHADER_USER_DATA_COMMON_13)/sizeof(mmSPI_SHADER_USER_DATA_COMMON_13[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_COMMON_14", REG_MMIO, 0x0d5a, 0, &mmSPI_SHADER_USER_DATA_COMMON_14[0], sizeof(mmSPI_SHADER_USER_DATA_COMMON_14)/sizeof(mmSPI_SHADER_USER_DATA_COMMON_14[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_COMMON_15", REG_MMIO, 0x0d5b, 0, &mmSPI_SHADER_USER_DATA_COMMON_15[0], sizeof(mmSPI_SHADER_USER_DATA_COMMON_15)/sizeof(mmSPI_SHADER_USER_DATA_COMMON_15[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_COMMON_16", REG_MMIO, 0x0d5c, 0, &mmSPI_SHADER_USER_DATA_COMMON_16[0], sizeof(mmSPI_SHADER_USER_DATA_COMMON_16)/sizeof(mmSPI_SHADER_USER_DATA_COMMON_16[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_COMMON_17", REG_MMIO, 0x0d5d, 0, &mmSPI_SHADER_USER_DATA_COMMON_17[0], sizeof(mmSPI_SHADER_USER_DATA_COMMON_17)/sizeof(mmSPI_SHADER_USER_DATA_COMMON_17[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_COMMON_18", REG_MMIO, 0x0d5e, 0, &mmSPI_SHADER_USER_DATA_COMMON_18[0], sizeof(mmSPI_SHADER_USER_DATA_COMMON_18)/sizeof(mmSPI_SHADER_USER_DATA_COMMON_18[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_COMMON_19", REG_MMIO, 0x0d5f, 0, &mmSPI_SHADER_USER_DATA_COMMON_19[0], sizeof(mmSPI_SHADER_USER_DATA_COMMON_19)/sizeof(mmSPI_SHADER_USER_DATA_COMMON_19[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_COMMON_20", REG_MMIO, 0x0d60, 0, &mmSPI_SHADER_USER_DATA_COMMON_20[0], sizeof(mmSPI_SHADER_USER_DATA_COMMON_20)/sizeof(mmSPI_SHADER_USER_DATA_COMMON_20[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_COMMON_21", REG_MMIO, 0x0d61, 0, &mmSPI_SHADER_USER_DATA_COMMON_21[0], sizeof(mmSPI_SHADER_USER_DATA_COMMON_21)/sizeof(mmSPI_SHADER_USER_DATA_COMMON_21[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_COMMON_22", REG_MMIO, 0x0d62, 0, &mmSPI_SHADER_USER_DATA_COMMON_22[0], sizeof(mmSPI_SHADER_USER_DATA_COMMON_22)/sizeof(mmSPI_SHADER_USER_DATA_COMMON_22[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_COMMON_23", REG_MMIO, 0x0d63, 0, &mmSPI_SHADER_USER_DATA_COMMON_23[0], sizeof(mmSPI_SHADER_USER_DATA_COMMON_23)/sizeof(mmSPI_SHADER_USER_DATA_COMMON_23[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_COMMON_24", REG_MMIO, 0x0d64, 0, &mmSPI_SHADER_USER_DATA_COMMON_24[0], sizeof(mmSPI_SHADER_USER_DATA_COMMON_24)/sizeof(mmSPI_SHADER_USER_DATA_COMMON_24[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_COMMON_25", REG_MMIO, 0x0d65, 0, &mmSPI_SHADER_USER_DATA_COMMON_25[0], sizeof(mmSPI_SHADER_USER_DATA_COMMON_25)/sizeof(mmSPI_SHADER_USER_DATA_COMMON_25[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_COMMON_26", REG_MMIO, 0x0d66, 0, &mmSPI_SHADER_USER_DATA_COMMON_26[0], sizeof(mmSPI_SHADER_USER_DATA_COMMON_26)/sizeof(mmSPI_SHADER_USER_DATA_COMMON_26[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_COMMON_27", REG_MMIO, 0x0d67, 0, &mmSPI_SHADER_USER_DATA_COMMON_27[0], sizeof(mmSPI_SHADER_USER_DATA_COMMON_27)/sizeof(mmSPI_SHADER_USER_DATA_COMMON_27[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_COMMON_28", REG_MMIO, 0x0d68, 0, &mmSPI_SHADER_USER_DATA_COMMON_28[0], sizeof(mmSPI_SHADER_USER_DATA_COMMON_28)/sizeof(mmSPI_SHADER_USER_DATA_COMMON_28[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_COMMON_29", REG_MMIO, 0x0d69, 0, &mmSPI_SHADER_USER_DATA_COMMON_29[0], sizeof(mmSPI_SHADER_USER_DATA_COMMON_29)/sizeof(mmSPI_SHADER_USER_DATA_COMMON_29[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_COMMON_30", REG_MMIO, 0x0d6a, 0, &mmSPI_SHADER_USER_DATA_COMMON_30[0], sizeof(mmSPI_SHADER_USER_DATA_COMMON_30)/sizeof(mmSPI_SHADER_USER_DATA_COMMON_30[0]), 0, 0 }, + { "mmSPI_SHADER_USER_DATA_COMMON_31", REG_MMIO, 0x0d6b, 0, &mmSPI_SHADER_USER_DATA_COMMON_31[0], sizeof(mmSPI_SHADER_USER_DATA_COMMON_31)/sizeof(mmSPI_SHADER_USER_DATA_COMMON_31[0]), 0, 0 }, + { "mmCOMPUTE_DISPATCH_INITIATOR", REG_MMIO, 0x0e00, 0, &mmCOMPUTE_DISPATCH_INITIATOR[0], sizeof(mmCOMPUTE_DISPATCH_INITIATOR)/sizeof(mmCOMPUTE_DISPATCH_INITIATOR[0]), 0, 0 }, + { "mmCOMPUTE_DIM_X", REG_MMIO, 0x0e01, 0, &mmCOMPUTE_DIM_X[0], sizeof(mmCOMPUTE_DIM_X)/sizeof(mmCOMPUTE_DIM_X[0]), 0, 0 }, + { "mmCOMPUTE_DIM_Y", REG_MMIO, 0x0e02, 0, &mmCOMPUTE_DIM_Y[0], sizeof(mmCOMPUTE_DIM_Y)/sizeof(mmCOMPUTE_DIM_Y[0]), 0, 0 }, + { "mmCOMPUTE_DIM_Z", REG_MMIO, 0x0e03, 0, &mmCOMPUTE_DIM_Z[0], sizeof(mmCOMPUTE_DIM_Z)/sizeof(mmCOMPUTE_DIM_Z[0]), 0, 0 }, + { "mmCOMPUTE_START_X", REG_MMIO, 0x0e04, 0, &mmCOMPUTE_START_X[0], sizeof(mmCOMPUTE_START_X)/sizeof(mmCOMPUTE_START_X[0]), 0, 0 }, + { "mmCOMPUTE_START_Y", REG_MMIO, 0x0e05, 0, &mmCOMPUTE_START_Y[0], sizeof(mmCOMPUTE_START_Y)/sizeof(mmCOMPUTE_START_Y[0]), 0, 0 }, + { "mmCOMPUTE_START_Z", REG_MMIO, 0x0e06, 0, &mmCOMPUTE_START_Z[0], sizeof(mmCOMPUTE_START_Z)/sizeof(mmCOMPUTE_START_Z[0]), 0, 0 }, + { "mmCOMPUTE_NUM_THREAD_X", REG_MMIO, 0x0e07, 0, &mmCOMPUTE_NUM_THREAD_X[0], sizeof(mmCOMPUTE_NUM_THREAD_X)/sizeof(mmCOMPUTE_NUM_THREAD_X[0]), 0, 0 }, + { "mmCOMPUTE_NUM_THREAD_Y", REG_MMIO, 0x0e08, 0, &mmCOMPUTE_NUM_THREAD_Y[0], sizeof(mmCOMPUTE_NUM_THREAD_Y)/sizeof(mmCOMPUTE_NUM_THREAD_Y[0]), 0, 0 }, + { "mmCOMPUTE_NUM_THREAD_Z", REG_MMIO, 0x0e09, 0, &mmCOMPUTE_NUM_THREAD_Z[0], sizeof(mmCOMPUTE_NUM_THREAD_Z)/sizeof(mmCOMPUTE_NUM_THREAD_Z[0]), 0, 0 }, + { "mmCOMPUTE_PIPELINESTAT_ENABLE", REG_MMIO, 0x0e0a, 0, &mmCOMPUTE_PIPELINESTAT_ENABLE[0], sizeof(mmCOMPUTE_PIPELINESTAT_ENABLE)/sizeof(mmCOMPUTE_PIPELINESTAT_ENABLE[0]), 0, 0 }, + { "mmCOMPUTE_PERFCOUNT_ENABLE", REG_MMIO, 0x0e0b, 0, &mmCOMPUTE_PERFCOUNT_ENABLE[0], sizeof(mmCOMPUTE_PERFCOUNT_ENABLE)/sizeof(mmCOMPUTE_PERFCOUNT_ENABLE[0]), 0, 0 }, + { "mmCOMPUTE_PGM_LO", REG_MMIO, 0x0e0c, 0, &mmCOMPUTE_PGM_LO[0], sizeof(mmCOMPUTE_PGM_LO)/sizeof(mmCOMPUTE_PGM_LO[0]), 0, 0 }, + { "mmCOMPUTE_PGM_HI", REG_MMIO, 0x0e0d, 0, &mmCOMPUTE_PGM_HI[0], sizeof(mmCOMPUTE_PGM_HI)/sizeof(mmCOMPUTE_PGM_HI[0]), 0, 0 }, + { "mmCOMPUTE_DISPATCH_PKT_ADDR_LO", REG_MMIO, 0x0e0e, 0, &mmCOMPUTE_DISPATCH_PKT_ADDR_LO[0], sizeof(mmCOMPUTE_DISPATCH_PKT_ADDR_LO)/sizeof(mmCOMPUTE_DISPATCH_PKT_ADDR_LO[0]), 0, 0 }, + { "mmCOMPUTE_DISPATCH_PKT_ADDR_HI", REG_MMIO, 0x0e0f, 0, &mmCOMPUTE_DISPATCH_PKT_ADDR_HI[0], sizeof(mmCOMPUTE_DISPATCH_PKT_ADDR_HI)/sizeof(mmCOMPUTE_DISPATCH_PKT_ADDR_HI[0]), 0, 0 }, + { "mmCOMPUTE_DISPATCH_SCRATCH_BASE_LO", REG_MMIO, 0x0e10, 0, &mmCOMPUTE_DISPATCH_SCRATCH_BASE_LO[0], sizeof(mmCOMPUTE_DISPATCH_SCRATCH_BASE_LO)/sizeof(mmCOMPUTE_DISPATCH_SCRATCH_BASE_LO[0]), 0, 0 }, + { "mmCOMPUTE_DISPATCH_SCRATCH_BASE_HI", REG_MMIO, 0x0e11, 0, &mmCOMPUTE_DISPATCH_SCRATCH_BASE_HI[0], sizeof(mmCOMPUTE_DISPATCH_SCRATCH_BASE_HI)/sizeof(mmCOMPUTE_DISPATCH_SCRATCH_BASE_HI[0]), 0, 0 }, + { "mmCOMPUTE_PGM_RSRC1", REG_MMIO, 0x0e12, 0, &mmCOMPUTE_PGM_RSRC1[0], sizeof(mmCOMPUTE_PGM_RSRC1)/sizeof(mmCOMPUTE_PGM_RSRC1[0]), 0, 0 }, + { "mmCOMPUTE_PGM_RSRC2", REG_MMIO, 0x0e13, 0, &mmCOMPUTE_PGM_RSRC2[0], sizeof(mmCOMPUTE_PGM_RSRC2)/sizeof(mmCOMPUTE_PGM_RSRC2[0]), 0, 0 }, + { "mmCOMPUTE_VMID", REG_MMIO, 0x0e14, 0, &mmCOMPUTE_VMID[0], sizeof(mmCOMPUTE_VMID)/sizeof(mmCOMPUTE_VMID[0]), 0, 0 }, + { "mmCOMPUTE_RESOURCE_LIMITS", REG_MMIO, 0x0e15, 0, &mmCOMPUTE_RESOURCE_LIMITS[0], sizeof(mmCOMPUTE_RESOURCE_LIMITS)/sizeof(mmCOMPUTE_RESOURCE_LIMITS[0]), 0, 0 }, + { "mmCOMPUTE_STATIC_THREAD_MGMT_SE0", REG_MMIO, 0x0e16, 0, &mmCOMPUTE_STATIC_THREAD_MGMT_SE0[0], sizeof(mmCOMPUTE_STATIC_THREAD_MGMT_SE0)/sizeof(mmCOMPUTE_STATIC_THREAD_MGMT_SE0[0]), 0, 0 }, + { "mmCOMPUTE_STATIC_THREAD_MGMT_SE1", REG_MMIO, 0x0e17, 0, &mmCOMPUTE_STATIC_THREAD_MGMT_SE1[0], sizeof(mmCOMPUTE_STATIC_THREAD_MGMT_SE1)/sizeof(mmCOMPUTE_STATIC_THREAD_MGMT_SE1[0]), 0, 0 }, + { "mmCOMPUTE_TMPRING_SIZE", REG_MMIO, 0x0e18, 0, &mmCOMPUTE_TMPRING_SIZE[0], sizeof(mmCOMPUTE_TMPRING_SIZE)/sizeof(mmCOMPUTE_TMPRING_SIZE[0]), 0, 0 }, + { "mmCOMPUTE_STATIC_THREAD_MGMT_SE2", REG_MMIO, 0x0e19, 0, &mmCOMPUTE_STATIC_THREAD_MGMT_SE2[0], sizeof(mmCOMPUTE_STATIC_THREAD_MGMT_SE2)/sizeof(mmCOMPUTE_STATIC_THREAD_MGMT_SE2[0]), 0, 0 }, + { "mmCOMPUTE_STATIC_THREAD_MGMT_SE3", REG_MMIO, 0x0e1a, 0, &mmCOMPUTE_STATIC_THREAD_MGMT_SE3[0], sizeof(mmCOMPUTE_STATIC_THREAD_MGMT_SE3)/sizeof(mmCOMPUTE_STATIC_THREAD_MGMT_SE3[0]), 0, 0 }, + { "mmCOMPUTE_RESTART_X", REG_MMIO, 0x0e1b, 0, &mmCOMPUTE_RESTART_X[0], sizeof(mmCOMPUTE_RESTART_X)/sizeof(mmCOMPUTE_RESTART_X[0]), 0, 0 }, + { "mmCOMPUTE_RESTART_Y", REG_MMIO, 0x0e1c, 0, &mmCOMPUTE_RESTART_Y[0], sizeof(mmCOMPUTE_RESTART_Y)/sizeof(mmCOMPUTE_RESTART_Y[0]), 0, 0 }, + { "mmCOMPUTE_RESTART_Z", REG_MMIO, 0x0e1d, 0, &mmCOMPUTE_RESTART_Z[0], sizeof(mmCOMPUTE_RESTART_Z)/sizeof(mmCOMPUTE_RESTART_Z[0]), 0, 0 }, + { "mmCOMPUTE_THREAD_TRACE_ENABLE", REG_MMIO, 0x0e1e, 0, &mmCOMPUTE_THREAD_TRACE_ENABLE[0], sizeof(mmCOMPUTE_THREAD_TRACE_ENABLE)/sizeof(mmCOMPUTE_THREAD_TRACE_ENABLE[0]), 0, 0 }, + { "mmCOMPUTE_MISC_RESERVED", REG_MMIO, 0x0e1f, 0, &mmCOMPUTE_MISC_RESERVED[0], sizeof(mmCOMPUTE_MISC_RESERVED)/sizeof(mmCOMPUTE_MISC_RESERVED[0]), 0, 0 }, + { "mmCOMPUTE_DISPATCH_ID", REG_MMIO, 0x0e20, 0, &mmCOMPUTE_DISPATCH_ID[0], sizeof(mmCOMPUTE_DISPATCH_ID)/sizeof(mmCOMPUTE_DISPATCH_ID[0]), 0, 0 }, + { "mmCOMPUTE_THREADGROUP_ID", REG_MMIO, 0x0e21, 0, &mmCOMPUTE_THREADGROUP_ID[0], sizeof(mmCOMPUTE_THREADGROUP_ID)/sizeof(mmCOMPUTE_THREADGROUP_ID[0]), 0, 0 }, + { "mmCOMPUTE_RELAUNCH", REG_MMIO, 0x0e22, 0, &mmCOMPUTE_RELAUNCH[0], sizeof(mmCOMPUTE_RELAUNCH)/sizeof(mmCOMPUTE_RELAUNCH[0]), 0, 0 }, + { "mmCOMPUTE_WAVE_RESTORE_ADDR_LO", REG_MMIO, 0x0e23, 0, &mmCOMPUTE_WAVE_RESTORE_ADDR_LO[0], sizeof(mmCOMPUTE_WAVE_RESTORE_ADDR_LO)/sizeof(mmCOMPUTE_WAVE_RESTORE_ADDR_LO[0]), 0, 0 }, + { "mmCOMPUTE_WAVE_RESTORE_ADDR_HI", REG_MMIO, 0x0e24, 0, &mmCOMPUTE_WAVE_RESTORE_ADDR_HI[0], sizeof(mmCOMPUTE_WAVE_RESTORE_ADDR_HI)/sizeof(mmCOMPUTE_WAVE_RESTORE_ADDR_HI[0]), 0, 0 }, + { "mmCOMPUTE_USER_DATA_0", REG_MMIO, 0x0e40, 0, &mmCOMPUTE_USER_DATA_0[0], sizeof(mmCOMPUTE_USER_DATA_0)/sizeof(mmCOMPUTE_USER_DATA_0[0]), 0, 0 }, + { "mmCOMPUTE_USER_DATA_1", REG_MMIO, 0x0e41, 0, &mmCOMPUTE_USER_DATA_1[0], sizeof(mmCOMPUTE_USER_DATA_1)/sizeof(mmCOMPUTE_USER_DATA_1[0]), 0, 0 }, + { "mmCOMPUTE_USER_DATA_2", REG_MMIO, 0x0e42, 0, &mmCOMPUTE_USER_DATA_2[0], sizeof(mmCOMPUTE_USER_DATA_2)/sizeof(mmCOMPUTE_USER_DATA_2[0]), 0, 0 }, + { "mmCOMPUTE_USER_DATA_3", REG_MMIO, 0x0e43, 0, &mmCOMPUTE_USER_DATA_3[0], sizeof(mmCOMPUTE_USER_DATA_3)/sizeof(mmCOMPUTE_USER_DATA_3[0]), 0, 0 }, + { "mmCOMPUTE_USER_DATA_4", REG_MMIO, 0x0e44, 0, &mmCOMPUTE_USER_DATA_4[0], sizeof(mmCOMPUTE_USER_DATA_4)/sizeof(mmCOMPUTE_USER_DATA_4[0]), 0, 0 }, + { "mmCOMPUTE_USER_DATA_5", REG_MMIO, 0x0e45, 0, &mmCOMPUTE_USER_DATA_5[0], sizeof(mmCOMPUTE_USER_DATA_5)/sizeof(mmCOMPUTE_USER_DATA_5[0]), 0, 0 }, + { "mmCOMPUTE_USER_DATA_6", REG_MMIO, 0x0e46, 0, &mmCOMPUTE_USER_DATA_6[0], sizeof(mmCOMPUTE_USER_DATA_6)/sizeof(mmCOMPUTE_USER_DATA_6[0]), 0, 0 }, + { "mmCOMPUTE_USER_DATA_7", REG_MMIO, 0x0e47, 0, &mmCOMPUTE_USER_DATA_7[0], sizeof(mmCOMPUTE_USER_DATA_7)/sizeof(mmCOMPUTE_USER_DATA_7[0]), 0, 0 }, + { "mmCOMPUTE_USER_DATA_8", REG_MMIO, 0x0e48, 0, &mmCOMPUTE_USER_DATA_8[0], sizeof(mmCOMPUTE_USER_DATA_8)/sizeof(mmCOMPUTE_USER_DATA_8[0]), 0, 0 }, + { "mmCOMPUTE_USER_DATA_9", REG_MMIO, 0x0e49, 0, &mmCOMPUTE_USER_DATA_9[0], sizeof(mmCOMPUTE_USER_DATA_9)/sizeof(mmCOMPUTE_USER_DATA_9[0]), 0, 0 }, + { "mmCOMPUTE_USER_DATA_10", REG_MMIO, 0x0e4a, 0, &mmCOMPUTE_USER_DATA_10[0], sizeof(mmCOMPUTE_USER_DATA_10)/sizeof(mmCOMPUTE_USER_DATA_10[0]), 0, 0 }, + { "mmCOMPUTE_USER_DATA_11", REG_MMIO, 0x0e4b, 0, &mmCOMPUTE_USER_DATA_11[0], sizeof(mmCOMPUTE_USER_DATA_11)/sizeof(mmCOMPUTE_USER_DATA_11[0]), 0, 0 }, + { "mmCOMPUTE_USER_DATA_12", REG_MMIO, 0x0e4c, 0, &mmCOMPUTE_USER_DATA_12[0], sizeof(mmCOMPUTE_USER_DATA_12)/sizeof(mmCOMPUTE_USER_DATA_12[0]), 0, 0 }, + { "mmCOMPUTE_USER_DATA_13", REG_MMIO, 0x0e4d, 0, &mmCOMPUTE_USER_DATA_13[0], sizeof(mmCOMPUTE_USER_DATA_13)/sizeof(mmCOMPUTE_USER_DATA_13[0]), 0, 0 }, + { "mmCOMPUTE_USER_DATA_14", REG_MMIO, 0x0e4e, 0, &mmCOMPUTE_USER_DATA_14[0], sizeof(mmCOMPUTE_USER_DATA_14)/sizeof(mmCOMPUTE_USER_DATA_14[0]), 0, 0 }, + { "mmCOMPUTE_USER_DATA_15", REG_MMIO, 0x0e4f, 0, &mmCOMPUTE_USER_DATA_15[0], sizeof(mmCOMPUTE_USER_DATA_15)/sizeof(mmCOMPUTE_USER_DATA_15[0]), 0, 0 }, + { "mmCOMPUTE_NOWHERE", REG_MMIO, 0x0e7f, 0, &mmCOMPUTE_NOWHERE[0], sizeof(mmCOMPUTE_NOWHERE)/sizeof(mmCOMPUTE_NOWHERE[0]), 0, 0 }, + { "mmCP_DFY_CNTL", REG_MMIO, 0x1020, 0, &mmCP_DFY_CNTL[0], sizeof(mmCP_DFY_CNTL)/sizeof(mmCP_DFY_CNTL[0]), 0, 0 }, + { "mmCP_DFY_STAT", REG_MMIO, 0x1021, 0, &mmCP_DFY_STAT[0], sizeof(mmCP_DFY_STAT)/sizeof(mmCP_DFY_STAT[0]), 0, 0 }, + { "mmCP_DFY_ADDR_HI", REG_MMIO, 0x1022, 0, &mmCP_DFY_ADDR_HI[0], sizeof(mmCP_DFY_ADDR_HI)/sizeof(mmCP_DFY_ADDR_HI[0]), 0, 0 }, + { "mmCP_DFY_ADDR_LO", REG_MMIO, 0x1023, 0, &mmCP_DFY_ADDR_LO[0], sizeof(mmCP_DFY_ADDR_LO)/sizeof(mmCP_DFY_ADDR_LO[0]), 0, 0 }, + { "mmCP_DFY_DATA_0", REG_MMIO, 0x1024, 0, &mmCP_DFY_DATA_0[0], sizeof(mmCP_DFY_DATA_0)/sizeof(mmCP_DFY_DATA_0[0]), 0, 0 }, + { "mmCP_DFY_DATA_1", REG_MMIO, 0x1025, 0, &mmCP_DFY_DATA_1[0], sizeof(mmCP_DFY_DATA_1)/sizeof(mmCP_DFY_DATA_1[0]), 0, 0 }, + { "mmCP_DFY_DATA_2", REG_MMIO, 0x1026, 0, &mmCP_DFY_DATA_2[0], sizeof(mmCP_DFY_DATA_2)/sizeof(mmCP_DFY_DATA_2[0]), 0, 0 }, + { "mmCP_DFY_DATA_3", REG_MMIO, 0x1027, 0, &mmCP_DFY_DATA_3[0], sizeof(mmCP_DFY_DATA_3)/sizeof(mmCP_DFY_DATA_3[0]), 0, 0 }, + { "mmCP_DFY_DATA_4", REG_MMIO, 0x1028, 0, &mmCP_DFY_DATA_4[0], sizeof(mmCP_DFY_DATA_4)/sizeof(mmCP_DFY_DATA_4[0]), 0, 0 }, + { "mmCP_DFY_DATA_5", REG_MMIO, 0x1029, 0, &mmCP_DFY_DATA_5[0], sizeof(mmCP_DFY_DATA_5)/sizeof(mmCP_DFY_DATA_5[0]), 0, 0 }, + { "mmCP_DFY_DATA_6", REG_MMIO, 0x102a, 0, &mmCP_DFY_DATA_6[0], sizeof(mmCP_DFY_DATA_6)/sizeof(mmCP_DFY_DATA_6[0]), 0, 0 }, + { "mmCP_DFY_DATA_7", REG_MMIO, 0x102b, 0, &mmCP_DFY_DATA_7[0], sizeof(mmCP_DFY_DATA_7)/sizeof(mmCP_DFY_DATA_7[0]), 0, 0 }, + { "mmCP_DFY_DATA_8", REG_MMIO, 0x102c, 0, &mmCP_DFY_DATA_8[0], sizeof(mmCP_DFY_DATA_8)/sizeof(mmCP_DFY_DATA_8[0]), 0, 0 }, + { "mmCP_DFY_DATA_9", REG_MMIO, 0x102d, 0, &mmCP_DFY_DATA_9[0], sizeof(mmCP_DFY_DATA_9)/sizeof(mmCP_DFY_DATA_9[0]), 0, 0 }, + { "mmCP_DFY_DATA_10", REG_MMIO, 0x102e, 0, &mmCP_DFY_DATA_10[0], sizeof(mmCP_DFY_DATA_10)/sizeof(mmCP_DFY_DATA_10[0]), 0, 0 }, + { "mmCP_DFY_DATA_11", REG_MMIO, 0x102f, 0, &mmCP_DFY_DATA_11[0], sizeof(mmCP_DFY_DATA_11)/sizeof(mmCP_DFY_DATA_11[0]), 0, 0 }, + { "mmCP_DFY_DATA_12", REG_MMIO, 0x1030, 0, &mmCP_DFY_DATA_12[0], sizeof(mmCP_DFY_DATA_12)/sizeof(mmCP_DFY_DATA_12[0]), 0, 0 }, + { "mmCP_DFY_DATA_13", REG_MMIO, 0x1031, 0, &mmCP_DFY_DATA_13[0], sizeof(mmCP_DFY_DATA_13)/sizeof(mmCP_DFY_DATA_13[0]), 0, 0 }, + { "mmCP_DFY_DATA_14", REG_MMIO, 0x1032, 0, &mmCP_DFY_DATA_14[0], sizeof(mmCP_DFY_DATA_14)/sizeof(mmCP_DFY_DATA_14[0]), 0, 0 }, + { "mmCP_DFY_DATA_15", REG_MMIO, 0x1033, 0, &mmCP_DFY_DATA_15[0], sizeof(mmCP_DFY_DATA_15)/sizeof(mmCP_DFY_DATA_15[0]), 0, 0 }, + { "mmCP_DFY_CMD", REG_MMIO, 0x1034, 0, &mmCP_DFY_CMD[0], sizeof(mmCP_DFY_CMD)/sizeof(mmCP_DFY_CMD[0]), 0, 0 }, + { "mmCP_EOPQ_WAIT_TIME", REG_MMIO, 0x1035, 0, &mmCP_EOPQ_WAIT_TIME[0], sizeof(mmCP_EOPQ_WAIT_TIME)/sizeof(mmCP_EOPQ_WAIT_TIME[0]), 0, 0 }, + { "mmCP_CPC_MGCG_SYNC_CNTL", REG_MMIO, 0x1036, 0, &mmCP_CPC_MGCG_SYNC_CNTL[0], sizeof(mmCP_CPC_MGCG_SYNC_CNTL)/sizeof(mmCP_CPC_MGCG_SYNC_CNTL[0]), 0, 0 }, + { "mmCPC_INT_INFO", REG_MMIO, 0x1037, 0, &mmCPC_INT_INFO[0], sizeof(mmCPC_INT_INFO)/sizeof(mmCPC_INT_INFO[0]), 0, 0 }, + { "mmCP_VIRT_STATUS", REG_MMIO, 0x1038, 0, &mmCP_VIRT_STATUS[0], sizeof(mmCP_VIRT_STATUS)/sizeof(mmCP_VIRT_STATUS[0]), 0, 0 }, + { "mmCPC_INT_ADDR", REG_MMIO, 0x1039, 0, &mmCPC_INT_ADDR[0], sizeof(mmCPC_INT_ADDR)/sizeof(mmCPC_INT_ADDR[0]), 0, 0 }, + { "mmCPC_INT_PASID", REG_MMIO, 0x103a, 0, &mmCPC_INT_PASID[0], sizeof(mmCPC_INT_PASID)/sizeof(mmCPC_INT_PASID[0]), 0, 0 }, + { "mmCP_GFX_ERROR", REG_MMIO, 0x103b, 0, &mmCP_GFX_ERROR[0], sizeof(mmCP_GFX_ERROR)/sizeof(mmCP_GFX_ERROR[0]), 0, 0 }, + { "mmCPG_UTCL1_CNTL", REG_MMIO, 0x103c, 0, &mmCPG_UTCL1_CNTL[0], sizeof(mmCPG_UTCL1_CNTL)/sizeof(mmCPG_UTCL1_CNTL[0]), 0, 0 }, + { "mmCPC_UTCL1_CNTL", REG_MMIO, 0x103d, 0, &mmCPC_UTCL1_CNTL[0], sizeof(mmCPC_UTCL1_CNTL)/sizeof(mmCPC_UTCL1_CNTL[0]), 0, 0 }, + { "mmCPF_UTCL1_CNTL", REG_MMIO, 0x103e, 0, &mmCPF_UTCL1_CNTL[0], sizeof(mmCPF_UTCL1_CNTL)/sizeof(mmCPF_UTCL1_CNTL[0]), 0, 0 }, + { "mmCP_AQL_SMM_STATUS", REG_MMIO, 0x103f, 0, &mmCP_AQL_SMM_STATUS[0], sizeof(mmCP_AQL_SMM_STATUS)/sizeof(mmCP_AQL_SMM_STATUS[0]), 0, 0 }, + { "mmCP_RB0_BASE", REG_MMIO, 0x1040, 0, &mmCP_RB0_BASE[0], sizeof(mmCP_RB0_BASE)/sizeof(mmCP_RB0_BASE[0]), 0, 0 }, + { "mmCP_RB_BASE", REG_MMIO, 0x1040, 0, &mmCP_RB_BASE[0], sizeof(mmCP_RB_BASE)/sizeof(mmCP_RB_BASE[0]), 0, 0 }, + { "mmCP_RB0_CNTL", REG_MMIO, 0x1041, 0, &mmCP_RB0_CNTL[0], sizeof(mmCP_RB0_CNTL)/sizeof(mmCP_RB0_CNTL[0]), 0, 0 }, + { "mmCP_RB_CNTL", REG_MMIO, 0x1041, 0, &mmCP_RB_CNTL[0], sizeof(mmCP_RB_CNTL)/sizeof(mmCP_RB_CNTL[0]), 0, 0 }, + { "mmCP_RB_RPTR_WR", REG_MMIO, 0x1042, 0, &mmCP_RB_RPTR_WR[0], sizeof(mmCP_RB_RPTR_WR)/sizeof(mmCP_RB_RPTR_WR[0]), 0, 0 }, + { "mmCP_RB0_RPTR_ADDR", REG_MMIO, 0x1043, 0, &mmCP_RB0_RPTR_ADDR[0], sizeof(mmCP_RB0_RPTR_ADDR)/sizeof(mmCP_RB0_RPTR_ADDR[0]), 0, 0 }, + { "mmCP_RB_RPTR_ADDR", REG_MMIO, 0x1043, 0, &mmCP_RB_RPTR_ADDR[0], sizeof(mmCP_RB_RPTR_ADDR)/sizeof(mmCP_RB_RPTR_ADDR[0]), 0, 0 }, + { "mmCP_RB0_RPTR_ADDR_HI", REG_MMIO, 0x1044, 0, &mmCP_RB0_RPTR_ADDR_HI[0], sizeof(mmCP_RB0_RPTR_ADDR_HI)/sizeof(mmCP_RB0_RPTR_ADDR_HI[0]), 0, 0 }, + { "mmCP_RB_RPTR_ADDR_HI", REG_MMIO, 0x1044, 0, &mmCP_RB_RPTR_ADDR_HI[0], sizeof(mmCP_RB_RPTR_ADDR_HI)/sizeof(mmCP_RB_RPTR_ADDR_HI[0]), 0, 0 }, + { "mmCP_RB0_BUFSZ_MASK", REG_MMIO, 0x1045, 0, &mmCP_RB0_BUFSZ_MASK[0], sizeof(mmCP_RB0_BUFSZ_MASK)/sizeof(mmCP_RB0_BUFSZ_MASK[0]), 0, 0 }, + { "mmCP_RB_BUFSZ_MASK", REG_MMIO, 0x1045, 0, &mmCP_RB_BUFSZ_MASK[0], sizeof(mmCP_RB_BUFSZ_MASK)/sizeof(mmCP_RB_BUFSZ_MASK[0]), 0, 0 }, + { "mmCP_RB_WPTR_POLL_ADDR_LO", REG_MMIO, 0x1046, 0, &mmCP_RB_WPTR_POLL_ADDR_LO[0], sizeof(mmCP_RB_WPTR_POLL_ADDR_LO)/sizeof(mmCP_RB_WPTR_POLL_ADDR_LO[0]), 0, 0 }, + { "mmCP_RB_WPTR_POLL_ADDR_HI", REG_MMIO, 0x1047, 0, &mmCP_RB_WPTR_POLL_ADDR_HI[0], sizeof(mmCP_RB_WPTR_POLL_ADDR_HI)/sizeof(mmCP_RB_WPTR_POLL_ADDR_HI[0]), 0, 0 }, + { "mmGC_PRIV_MODE", REG_MMIO, 0x1048, 0, NULL, 0, 0, 0 }, + { "mmCP_INT_CNTL", REG_MMIO, 0x1049, 0, &mmCP_INT_CNTL[0], sizeof(mmCP_INT_CNTL)/sizeof(mmCP_INT_CNTL[0]), 0, 0 }, + { "mmCP_INT_STATUS", REG_MMIO, 0x104a, 0, &mmCP_INT_STATUS[0], sizeof(mmCP_INT_STATUS)/sizeof(mmCP_INT_STATUS[0]), 0, 0 }, + { "mmCP_DEVICE_ID", REG_MMIO, 0x104b, 0, &mmCP_DEVICE_ID[0], sizeof(mmCP_DEVICE_ID)/sizeof(mmCP_DEVICE_ID[0]), 0, 0 }, + { "mmCP_ME0_PIPE_PRIORITY_CNTS", REG_MMIO, 0x104c, 0, &mmCP_ME0_PIPE_PRIORITY_CNTS[0], sizeof(mmCP_ME0_PIPE_PRIORITY_CNTS)/sizeof(mmCP_ME0_PIPE_PRIORITY_CNTS[0]), 0, 0 }, + { "mmCP_RING_PRIORITY_CNTS", REG_MMIO, 0x104c, 0, &mmCP_RING_PRIORITY_CNTS[0], sizeof(mmCP_RING_PRIORITY_CNTS)/sizeof(mmCP_RING_PRIORITY_CNTS[0]), 0, 0 }, + { "mmCP_ME0_PIPE0_PRIORITY", REG_MMIO, 0x104d, 0, &mmCP_ME0_PIPE0_PRIORITY[0], sizeof(mmCP_ME0_PIPE0_PRIORITY)/sizeof(mmCP_ME0_PIPE0_PRIORITY[0]), 0, 0 }, + { "mmCP_RING0_PRIORITY", REG_MMIO, 0x104d, 0, &mmCP_RING0_PRIORITY[0], sizeof(mmCP_RING0_PRIORITY)/sizeof(mmCP_RING0_PRIORITY[0]), 0, 0 }, + { "mmCP_ME0_PIPE1_PRIORITY", REG_MMIO, 0x104e, 0, &mmCP_ME0_PIPE1_PRIORITY[0], sizeof(mmCP_ME0_PIPE1_PRIORITY)/sizeof(mmCP_ME0_PIPE1_PRIORITY[0]), 0, 0 }, + { "mmCP_RING1_PRIORITY", REG_MMIO, 0x104e, 0, &mmCP_RING1_PRIORITY[0], sizeof(mmCP_RING1_PRIORITY)/sizeof(mmCP_RING1_PRIORITY[0]), 0, 0 }, + { "mmCP_ME0_PIPE2_PRIORITY", REG_MMIO, 0x104f, 0, &mmCP_ME0_PIPE2_PRIORITY[0], sizeof(mmCP_ME0_PIPE2_PRIORITY)/sizeof(mmCP_ME0_PIPE2_PRIORITY[0]), 0, 0 }, + { "mmCP_RING2_PRIORITY", REG_MMIO, 0x104f, 0, &mmCP_RING2_PRIORITY[0], sizeof(mmCP_RING2_PRIORITY)/sizeof(mmCP_RING2_PRIORITY[0]), 0, 0 }, + { "mmCP_FATAL_ERROR", REG_MMIO, 0x1050, 0, &mmCP_FATAL_ERROR[0], sizeof(mmCP_FATAL_ERROR)/sizeof(mmCP_FATAL_ERROR[0]), 0, 0 }, + { "mmCP_RB_VMID", REG_MMIO, 0x1051, 0, &mmCP_RB_VMID[0], sizeof(mmCP_RB_VMID)/sizeof(mmCP_RB_VMID[0]), 0, 0 }, + { "mmCP_ME0_PIPE0_VMID", REG_MMIO, 0x1052, 0, &mmCP_ME0_PIPE0_VMID[0], sizeof(mmCP_ME0_PIPE0_VMID)/sizeof(mmCP_ME0_PIPE0_VMID[0]), 0, 0 }, + { "mmCP_ME0_PIPE1_VMID", REG_MMIO, 0x1053, 0, &mmCP_ME0_PIPE1_VMID[0], sizeof(mmCP_ME0_PIPE1_VMID)/sizeof(mmCP_ME0_PIPE1_VMID[0]), 0, 0 }, + { "mmCP_RB0_WPTR", REG_MMIO, 0x1054, 0, &mmCP_RB0_WPTR[0], sizeof(mmCP_RB0_WPTR)/sizeof(mmCP_RB0_WPTR[0]), 0, 0 }, + { "mmCP_RB_WPTR", REG_MMIO, 0x1054, 0, &mmCP_RB_WPTR[0], sizeof(mmCP_RB_WPTR)/sizeof(mmCP_RB_WPTR[0]), 0, 0 }, + { "mmCP_RB0_WPTR_HI", REG_MMIO, 0x1055, 0, &mmCP_RB0_WPTR_HI[0], sizeof(mmCP_RB0_WPTR_HI)/sizeof(mmCP_RB0_WPTR_HI[0]), 0, 0 }, + { "mmCP_RB_WPTR_HI", REG_MMIO, 0x1055, 0, &mmCP_RB_WPTR_HI[0], sizeof(mmCP_RB_WPTR_HI)/sizeof(mmCP_RB_WPTR_HI[0]), 0, 0 }, + { "mmCP_RB1_WPTR", REG_MMIO, 0x1056, 0, &mmCP_RB1_WPTR[0], sizeof(mmCP_RB1_WPTR)/sizeof(mmCP_RB1_WPTR[0]), 0, 0 }, + { "mmCP_RB1_WPTR_HI", REG_MMIO, 0x1057, 0, &mmCP_RB1_WPTR_HI[0], sizeof(mmCP_RB1_WPTR_HI)/sizeof(mmCP_RB1_WPTR_HI[0]), 0, 0 }, + { "mmCP_RB2_WPTR", REG_MMIO, 0x1058, 0, &mmCP_RB2_WPTR[0], sizeof(mmCP_RB2_WPTR)/sizeof(mmCP_RB2_WPTR[0]), 0, 0 }, + { "mmCP_RB_DOORBELL_CONTROL", REG_MMIO, 0x1059, 0, &mmCP_RB_DOORBELL_CONTROL[0], sizeof(mmCP_RB_DOORBELL_CONTROL)/sizeof(mmCP_RB_DOORBELL_CONTROL[0]), 0, 0 }, + { "mmCP_RB_DOORBELL_RANGE_LOWER", REG_MMIO, 0x105a, 0, &mmCP_RB_DOORBELL_RANGE_LOWER[0], sizeof(mmCP_RB_DOORBELL_RANGE_LOWER)/sizeof(mmCP_RB_DOORBELL_RANGE_LOWER[0]), 0, 0 }, + { "mmCP_RB_DOORBELL_RANGE_UPPER", REG_MMIO, 0x105b, 0, &mmCP_RB_DOORBELL_RANGE_UPPER[0], sizeof(mmCP_RB_DOORBELL_RANGE_UPPER)/sizeof(mmCP_RB_DOORBELL_RANGE_UPPER[0]), 0, 0 }, + { "mmCP_MEC_DOORBELL_RANGE_LOWER", REG_MMIO, 0x105c, 0, &mmCP_MEC_DOORBELL_RANGE_LOWER[0], sizeof(mmCP_MEC_DOORBELL_RANGE_LOWER)/sizeof(mmCP_MEC_DOORBELL_RANGE_LOWER[0]), 0, 0 }, + { "mmCP_MEC_DOORBELL_RANGE_UPPER", REG_MMIO, 0x105d, 0, &mmCP_MEC_DOORBELL_RANGE_UPPER[0], sizeof(mmCP_MEC_DOORBELL_RANGE_UPPER)/sizeof(mmCP_MEC_DOORBELL_RANGE_UPPER[0]), 0, 0 }, + { "mmCPG_UTCL1_ERROR", REG_MMIO, 0x105e, 0, &mmCPG_UTCL1_ERROR[0], sizeof(mmCPG_UTCL1_ERROR)/sizeof(mmCPG_UTCL1_ERROR[0]), 0, 0 }, + { "mmCPC_UTCL1_ERROR", REG_MMIO, 0x105f, 0, &mmCPC_UTCL1_ERROR[0], sizeof(mmCPC_UTCL1_ERROR)/sizeof(mmCPC_UTCL1_ERROR[0]), 0, 0 }, + { "mmCP_RB1_BASE", REG_MMIO, 0x1060, 0, &mmCP_RB1_BASE[0], sizeof(mmCP_RB1_BASE)/sizeof(mmCP_RB1_BASE[0]), 0, 0 }, + { "mmCP_RB1_CNTL", REG_MMIO, 0x1061, 0, &mmCP_RB1_CNTL[0], sizeof(mmCP_RB1_CNTL)/sizeof(mmCP_RB1_CNTL[0]), 0, 0 }, + { "mmCP_RB1_RPTR_ADDR", REG_MMIO, 0x1062, 0, &mmCP_RB1_RPTR_ADDR[0], sizeof(mmCP_RB1_RPTR_ADDR)/sizeof(mmCP_RB1_RPTR_ADDR[0]), 0, 0 }, + { "mmCP_RB1_RPTR_ADDR_HI", REG_MMIO, 0x1063, 0, &mmCP_RB1_RPTR_ADDR_HI[0], sizeof(mmCP_RB1_RPTR_ADDR_HI)/sizeof(mmCP_RB1_RPTR_ADDR_HI[0]), 0, 0 }, + { "mmCP_RB2_BASE", REG_MMIO, 0x1065, 0, &mmCP_RB2_BASE[0], sizeof(mmCP_RB2_BASE)/sizeof(mmCP_RB2_BASE[0]), 0, 0 }, + { "mmCP_RB2_CNTL", REG_MMIO, 0x1066, 0, &mmCP_RB2_CNTL[0], sizeof(mmCP_RB2_CNTL)/sizeof(mmCP_RB2_CNTL[0]), 0, 0 }, + { "mmCP_RB2_RPTR_ADDR", REG_MMIO, 0x1067, 0, &mmCP_RB2_RPTR_ADDR[0], sizeof(mmCP_RB2_RPTR_ADDR)/sizeof(mmCP_RB2_RPTR_ADDR[0]), 0, 0 }, + { "mmCP_RB2_RPTR_ADDR_HI", REG_MMIO, 0x1068, 0, &mmCP_RB2_RPTR_ADDR_HI[0], sizeof(mmCP_RB2_RPTR_ADDR_HI)/sizeof(mmCP_RB2_RPTR_ADDR_HI[0]), 0, 0 }, + { "mmCP_RB0_ACTIVE", REG_MMIO, 0x1069, 0, &mmCP_RB0_ACTIVE[0], sizeof(mmCP_RB0_ACTIVE)/sizeof(mmCP_RB0_ACTIVE[0]), 0, 0 }, + { "mmCP_RB_ACTIVE", REG_MMIO, 0x1069, 0, &mmCP_RB_ACTIVE[0], sizeof(mmCP_RB_ACTIVE)/sizeof(mmCP_RB_ACTIVE[0]), 0, 0 }, + { "mmCP_INT_CNTL_RING0", REG_MMIO, 0x106a, 0, &mmCP_INT_CNTL_RING0[0], sizeof(mmCP_INT_CNTL_RING0)/sizeof(mmCP_INT_CNTL_RING0[0]), 0, 0 }, + { "mmCP_INT_CNTL_RING1", REG_MMIO, 0x106b, 0, &mmCP_INT_CNTL_RING1[0], sizeof(mmCP_INT_CNTL_RING1)/sizeof(mmCP_INT_CNTL_RING1[0]), 0, 0 }, + { "mmCP_INT_CNTL_RING2", REG_MMIO, 0x106c, 0, &mmCP_INT_CNTL_RING2[0], sizeof(mmCP_INT_CNTL_RING2)/sizeof(mmCP_INT_CNTL_RING2[0]), 0, 0 }, + { "mmCP_INT_STATUS_RING0", REG_MMIO, 0x106d, 0, &mmCP_INT_STATUS_RING0[0], sizeof(mmCP_INT_STATUS_RING0)/sizeof(mmCP_INT_STATUS_RING0[0]), 0, 0 }, + { "mmCP_INT_STATUS_RING1", REG_MMIO, 0x106e, 0, &mmCP_INT_STATUS_RING1[0], sizeof(mmCP_INT_STATUS_RING1)/sizeof(mmCP_INT_STATUS_RING1[0]), 0, 0 }, + { "mmCP_INT_STATUS_RING2", REG_MMIO, 0x106f, 0, &mmCP_INT_STATUS_RING2[0], sizeof(mmCP_INT_STATUS_RING2)/sizeof(mmCP_INT_STATUS_RING2[0]), 0, 0 }, + { "mmCP_PWR_CNTL", REG_MMIO, 0x1078, 0, &mmCP_PWR_CNTL[0], sizeof(mmCP_PWR_CNTL)/sizeof(mmCP_PWR_CNTL[0]), 0, 0 }, + { "mmCP_MEM_SLP_CNTL", REG_MMIO, 0x1079, 0, &mmCP_MEM_SLP_CNTL[0], sizeof(mmCP_MEM_SLP_CNTL)/sizeof(mmCP_MEM_SLP_CNTL[0]), 0, 0 }, + { "mmCP_ECC_FIRSTOCCURRENCE", REG_MMIO, 0x107a, 0, &mmCP_ECC_FIRSTOCCURRENCE[0], sizeof(mmCP_ECC_FIRSTOCCURRENCE)/sizeof(mmCP_ECC_FIRSTOCCURRENCE[0]), 0, 0 }, + { "mmCP_ECC_FIRSTOCCURRENCE_RING0", REG_MMIO, 0x107b, 0, &mmCP_ECC_FIRSTOCCURRENCE_RING0[0], sizeof(mmCP_ECC_FIRSTOCCURRENCE_RING0)/sizeof(mmCP_ECC_FIRSTOCCURRENCE_RING0[0]), 0, 0 }, + { "mmCP_ECC_FIRSTOCCURRENCE_RING1", REG_MMIO, 0x107c, 0, &mmCP_ECC_FIRSTOCCURRENCE_RING1[0], sizeof(mmCP_ECC_FIRSTOCCURRENCE_RING1)/sizeof(mmCP_ECC_FIRSTOCCURRENCE_RING1[0]), 0, 0 }, + { "mmCP_ECC_FIRSTOCCURRENCE_RING2", REG_MMIO, 0x107d, 0, &mmCP_ECC_FIRSTOCCURRENCE_RING2[0], sizeof(mmCP_ECC_FIRSTOCCURRENCE_RING2)/sizeof(mmCP_ECC_FIRSTOCCURRENCE_RING2[0]), 0, 0 }, + { "mmGB_EDC_MODE", REG_MMIO, 0x107e, 0, &mmGB_EDC_MODE[0], sizeof(mmGB_EDC_MODE)/sizeof(mmGB_EDC_MODE[0]), 0, 0 }, + { "mmCP_PQ_WPTR_POLL_CNTL", REG_MMIO, 0x1083, 0, &mmCP_PQ_WPTR_POLL_CNTL[0], sizeof(mmCP_PQ_WPTR_POLL_CNTL)/sizeof(mmCP_PQ_WPTR_POLL_CNTL[0]), 0, 0 }, + { "mmCP_PQ_WPTR_POLL_CNTL1", REG_MMIO, 0x1084, 0, &mmCP_PQ_WPTR_POLL_CNTL1[0], sizeof(mmCP_PQ_WPTR_POLL_CNTL1)/sizeof(mmCP_PQ_WPTR_POLL_CNTL1[0]), 0, 0 }, + { "mmCP_ME1_PIPE0_INT_CNTL", REG_MMIO, 0x1085, 0, &mmCP_ME1_PIPE0_INT_CNTL[0], sizeof(mmCP_ME1_PIPE0_INT_CNTL)/sizeof(mmCP_ME1_PIPE0_INT_CNTL[0]), 0, 0 }, + { "mmCP_ME1_PIPE1_INT_CNTL", REG_MMIO, 0x1086, 0, &mmCP_ME1_PIPE1_INT_CNTL[0], sizeof(mmCP_ME1_PIPE1_INT_CNTL)/sizeof(mmCP_ME1_PIPE1_INT_CNTL[0]), 0, 0 }, + { "mmCP_ME1_PIPE2_INT_CNTL", REG_MMIO, 0x1087, 0, &mmCP_ME1_PIPE2_INT_CNTL[0], sizeof(mmCP_ME1_PIPE2_INT_CNTL)/sizeof(mmCP_ME1_PIPE2_INT_CNTL[0]), 0, 0 }, + { "mmCP_ME1_PIPE3_INT_CNTL", REG_MMIO, 0x1088, 0, &mmCP_ME1_PIPE3_INT_CNTL[0], sizeof(mmCP_ME1_PIPE3_INT_CNTL)/sizeof(mmCP_ME1_PIPE3_INT_CNTL[0]), 0, 0 }, + { "mmCP_ME2_PIPE0_INT_CNTL", REG_MMIO, 0x1089, 0, &mmCP_ME2_PIPE0_INT_CNTL[0], sizeof(mmCP_ME2_PIPE0_INT_CNTL)/sizeof(mmCP_ME2_PIPE0_INT_CNTL[0]), 0, 0 }, + { "mmCP_ME2_PIPE1_INT_CNTL", REG_MMIO, 0x108a, 0, &mmCP_ME2_PIPE1_INT_CNTL[0], sizeof(mmCP_ME2_PIPE1_INT_CNTL)/sizeof(mmCP_ME2_PIPE1_INT_CNTL[0]), 0, 0 }, + { "mmCP_ME2_PIPE2_INT_CNTL", REG_MMIO, 0x108b, 0, &mmCP_ME2_PIPE2_INT_CNTL[0], sizeof(mmCP_ME2_PIPE2_INT_CNTL)/sizeof(mmCP_ME2_PIPE2_INT_CNTL[0]), 0, 0 }, + { "mmCP_ME2_PIPE3_INT_CNTL", REG_MMIO, 0x108c, 0, &mmCP_ME2_PIPE3_INT_CNTL[0], sizeof(mmCP_ME2_PIPE3_INT_CNTL)/sizeof(mmCP_ME2_PIPE3_INT_CNTL[0]), 0, 0 }, + { "mmCP_ME1_PIPE0_INT_STATUS", REG_MMIO, 0x108d, 0, &mmCP_ME1_PIPE0_INT_STATUS[0], sizeof(mmCP_ME1_PIPE0_INT_STATUS)/sizeof(mmCP_ME1_PIPE0_INT_STATUS[0]), 0, 0 }, + { "mmCP_ME1_PIPE1_INT_STATUS", REG_MMIO, 0x108e, 0, &mmCP_ME1_PIPE1_INT_STATUS[0], sizeof(mmCP_ME1_PIPE1_INT_STATUS)/sizeof(mmCP_ME1_PIPE1_INT_STATUS[0]), 0, 0 }, + { "mmCP_ME1_PIPE2_INT_STATUS", REG_MMIO, 0x108f, 0, &mmCP_ME1_PIPE2_INT_STATUS[0], sizeof(mmCP_ME1_PIPE2_INT_STATUS)/sizeof(mmCP_ME1_PIPE2_INT_STATUS[0]), 0, 0 }, + { "mmCP_ME1_PIPE3_INT_STATUS", REG_MMIO, 0x1090, 0, &mmCP_ME1_PIPE3_INT_STATUS[0], sizeof(mmCP_ME1_PIPE3_INT_STATUS)/sizeof(mmCP_ME1_PIPE3_INT_STATUS[0]), 0, 0 }, + { "mmCP_ME2_PIPE0_INT_STATUS", REG_MMIO, 0x1091, 0, &mmCP_ME2_PIPE0_INT_STATUS[0], sizeof(mmCP_ME2_PIPE0_INT_STATUS)/sizeof(mmCP_ME2_PIPE0_INT_STATUS[0]), 0, 0 }, + { "mmCP_ME2_PIPE1_INT_STATUS", REG_MMIO, 0x1092, 0, &mmCP_ME2_PIPE1_INT_STATUS[0], sizeof(mmCP_ME2_PIPE1_INT_STATUS)/sizeof(mmCP_ME2_PIPE1_INT_STATUS[0]), 0, 0 }, + { "mmCP_ME2_PIPE2_INT_STATUS", REG_MMIO, 0x1093, 0, &mmCP_ME2_PIPE2_INT_STATUS[0], sizeof(mmCP_ME2_PIPE2_INT_STATUS)/sizeof(mmCP_ME2_PIPE2_INT_STATUS[0]), 0, 0 }, + { "mmCP_ME2_PIPE3_INT_STATUS", REG_MMIO, 0x1094, 0, &mmCP_ME2_PIPE3_INT_STATUS[0], sizeof(mmCP_ME2_PIPE3_INT_STATUS)/sizeof(mmCP_ME2_PIPE3_INT_STATUS[0]), 0, 0 }, + { "mmCC_GC_EDC_CONFIG", REG_MMIO, 0x1098, 0, &mmCC_GC_EDC_CONFIG[0], sizeof(mmCC_GC_EDC_CONFIG)/sizeof(mmCC_GC_EDC_CONFIG[0]), 0, 0 }, + { "mmCP_ME1_PIPE_PRIORITY_CNTS", REG_MMIO, 0x1099, 0, &mmCP_ME1_PIPE_PRIORITY_CNTS[0], sizeof(mmCP_ME1_PIPE_PRIORITY_CNTS)/sizeof(mmCP_ME1_PIPE_PRIORITY_CNTS[0]), 0, 0 }, + { "mmCP_ME1_PIPE0_PRIORITY", REG_MMIO, 0x109a, 0, &mmCP_ME1_PIPE0_PRIORITY[0], sizeof(mmCP_ME1_PIPE0_PRIORITY)/sizeof(mmCP_ME1_PIPE0_PRIORITY[0]), 0, 0 }, + { "mmCP_ME1_PIPE1_PRIORITY", REG_MMIO, 0x109b, 0, &mmCP_ME1_PIPE1_PRIORITY[0], sizeof(mmCP_ME1_PIPE1_PRIORITY)/sizeof(mmCP_ME1_PIPE1_PRIORITY[0]), 0, 0 }, + { "mmCP_ME1_PIPE2_PRIORITY", REG_MMIO, 0x109c, 0, &mmCP_ME1_PIPE2_PRIORITY[0], sizeof(mmCP_ME1_PIPE2_PRIORITY)/sizeof(mmCP_ME1_PIPE2_PRIORITY[0]), 0, 0 }, + { "mmCP_ME1_PIPE3_PRIORITY", REG_MMIO, 0x109d, 0, &mmCP_ME1_PIPE3_PRIORITY[0], sizeof(mmCP_ME1_PIPE3_PRIORITY)/sizeof(mmCP_ME1_PIPE3_PRIORITY[0]), 0, 0 }, + { "mmCP_ME2_PIPE_PRIORITY_CNTS", REG_MMIO, 0x109e, 0, &mmCP_ME2_PIPE_PRIORITY_CNTS[0], sizeof(mmCP_ME2_PIPE_PRIORITY_CNTS)/sizeof(mmCP_ME2_PIPE_PRIORITY_CNTS[0]), 0, 0 }, + { "mmCP_ME2_PIPE0_PRIORITY", REG_MMIO, 0x109f, 0, &mmCP_ME2_PIPE0_PRIORITY[0], sizeof(mmCP_ME2_PIPE0_PRIORITY)/sizeof(mmCP_ME2_PIPE0_PRIORITY[0]), 0, 0 }, + { "mmCP_ME2_PIPE1_PRIORITY", REG_MMIO, 0x10a0, 0, &mmCP_ME2_PIPE1_PRIORITY[0], sizeof(mmCP_ME2_PIPE1_PRIORITY)/sizeof(mmCP_ME2_PIPE1_PRIORITY[0]), 0, 0 }, + { "mmCP_ME2_PIPE2_PRIORITY", REG_MMIO, 0x10a1, 0, &mmCP_ME2_PIPE2_PRIORITY[0], sizeof(mmCP_ME2_PIPE2_PRIORITY)/sizeof(mmCP_ME2_PIPE2_PRIORITY[0]), 0, 0 }, + { "mmCP_ME2_PIPE3_PRIORITY", REG_MMIO, 0x10a2, 0, &mmCP_ME2_PIPE3_PRIORITY[0], sizeof(mmCP_ME2_PIPE3_PRIORITY)/sizeof(mmCP_ME2_PIPE3_PRIORITY[0]), 0, 0 }, + { "mmCP_CE_PRGRM_CNTR_START", REG_MMIO, 0x10a3, 0, &mmCP_CE_PRGRM_CNTR_START[0], sizeof(mmCP_CE_PRGRM_CNTR_START)/sizeof(mmCP_CE_PRGRM_CNTR_START[0]), 0, 0 }, + { "mmCP_PFP_PRGRM_CNTR_START", REG_MMIO, 0x10a4, 0, &mmCP_PFP_PRGRM_CNTR_START[0], sizeof(mmCP_PFP_PRGRM_CNTR_START)/sizeof(mmCP_PFP_PRGRM_CNTR_START[0]), 0, 0 }, + { "mmCP_ME_PRGRM_CNTR_START", REG_MMIO, 0x10a5, 0, &mmCP_ME_PRGRM_CNTR_START[0], sizeof(mmCP_ME_PRGRM_CNTR_START)/sizeof(mmCP_ME_PRGRM_CNTR_START[0]), 0, 0 }, + { "mmCP_MEC1_PRGRM_CNTR_START", REG_MMIO, 0x10a6, 0, &mmCP_MEC1_PRGRM_CNTR_START[0], sizeof(mmCP_MEC1_PRGRM_CNTR_START)/sizeof(mmCP_MEC1_PRGRM_CNTR_START[0]), 0, 0 }, + { "mmCP_MEC2_PRGRM_CNTR_START", REG_MMIO, 0x10a7, 0, &mmCP_MEC2_PRGRM_CNTR_START[0], sizeof(mmCP_MEC2_PRGRM_CNTR_START)/sizeof(mmCP_MEC2_PRGRM_CNTR_START[0]), 0, 0 }, + { "mmCP_CE_INTR_ROUTINE_START", REG_MMIO, 0x10a8, 0, &mmCP_CE_INTR_ROUTINE_START[0], sizeof(mmCP_CE_INTR_ROUTINE_START)/sizeof(mmCP_CE_INTR_ROUTINE_START[0]), 0, 0 }, + { "mmCP_PFP_INTR_ROUTINE_START", REG_MMIO, 0x10a9, 0, &mmCP_PFP_INTR_ROUTINE_START[0], sizeof(mmCP_PFP_INTR_ROUTINE_START)/sizeof(mmCP_PFP_INTR_ROUTINE_START[0]), 0, 0 }, + { "mmCP_ME_INTR_ROUTINE_START", REG_MMIO, 0x10aa, 0, &mmCP_ME_INTR_ROUTINE_START[0], sizeof(mmCP_ME_INTR_ROUTINE_START)/sizeof(mmCP_ME_INTR_ROUTINE_START[0]), 0, 0 }, + { "mmCP_MEC1_INTR_ROUTINE_START", REG_MMIO, 0x10ab, 0, &mmCP_MEC1_INTR_ROUTINE_START[0], sizeof(mmCP_MEC1_INTR_ROUTINE_START)/sizeof(mmCP_MEC1_INTR_ROUTINE_START[0]), 0, 0 }, + { "mmCP_MEC2_INTR_ROUTINE_START", REG_MMIO, 0x10ac, 0, &mmCP_MEC2_INTR_ROUTINE_START[0], sizeof(mmCP_MEC2_INTR_ROUTINE_START)/sizeof(mmCP_MEC2_INTR_ROUTINE_START[0]), 0, 0 }, + { "mmCP_CONTEXT_CNTL", REG_MMIO, 0x10ad, 0, &mmCP_CONTEXT_CNTL[0], sizeof(mmCP_CONTEXT_CNTL)/sizeof(mmCP_CONTEXT_CNTL[0]), 0, 0 }, + { "mmCP_MAX_CONTEXT", REG_MMIO, 0x10ae, 0, &mmCP_MAX_CONTEXT[0], sizeof(mmCP_MAX_CONTEXT)/sizeof(mmCP_MAX_CONTEXT[0]), 0, 0 }, + { "mmCP_IQ_WAIT_TIME1", REG_MMIO, 0x10af, 0, &mmCP_IQ_WAIT_TIME1[0], sizeof(mmCP_IQ_WAIT_TIME1)/sizeof(mmCP_IQ_WAIT_TIME1[0]), 0, 0 }, + { "mmCP_IQ_WAIT_TIME2", REG_MMIO, 0x10b0, 0, &mmCP_IQ_WAIT_TIME2[0], sizeof(mmCP_IQ_WAIT_TIME2)/sizeof(mmCP_IQ_WAIT_TIME2[0]), 0, 0 }, + { "mmCP_RB0_BASE_HI", REG_MMIO, 0x10b1, 0, &mmCP_RB0_BASE_HI[0], sizeof(mmCP_RB0_BASE_HI)/sizeof(mmCP_RB0_BASE_HI[0]), 0, 0 }, + { "mmCP_RB1_BASE_HI", REG_MMIO, 0x10b2, 0, &mmCP_RB1_BASE_HI[0], sizeof(mmCP_RB1_BASE_HI)/sizeof(mmCP_RB1_BASE_HI[0]), 0, 0 }, + { "mmCP_VMID_RESET", REG_MMIO, 0x10b3, 0, &mmCP_VMID_RESET[0], sizeof(mmCP_VMID_RESET)/sizeof(mmCP_VMID_RESET[0]), 0, 0 }, + { "mmCPC_INT_CNTL", REG_MMIO, 0x10b4, 0, &mmCPC_INT_CNTL[0], sizeof(mmCPC_INT_CNTL)/sizeof(mmCPC_INT_CNTL[0]), 0, 0 }, + { "mmCPC_INT_STATUS", REG_MMIO, 0x10b5, 0, &mmCPC_INT_STATUS[0], sizeof(mmCPC_INT_STATUS)/sizeof(mmCPC_INT_STATUS[0]), 0, 0 }, + { "mmCP_VMID_PREEMPT", REG_MMIO, 0x10b6, 0, &mmCP_VMID_PREEMPT[0], sizeof(mmCP_VMID_PREEMPT)/sizeof(mmCP_VMID_PREEMPT[0]), 0, 0 }, + { "mmCPC_INT_CNTX_ID", REG_MMIO, 0x10b7, 0, &mmCPC_INT_CNTX_ID[0], sizeof(mmCPC_INT_CNTX_ID)/sizeof(mmCPC_INT_CNTX_ID[0]), 0, 0 }, + { "mmCP_PQ_STATUS", REG_MMIO, 0x10b8, 0, &mmCP_PQ_STATUS[0], sizeof(mmCP_PQ_STATUS)/sizeof(mmCP_PQ_STATUS[0]), 0, 0 }, + { "mmCP_CPC_IC_BASE_LO", REG_MMIO, 0x10b9, 0, &mmCP_CPC_IC_BASE_LO[0], sizeof(mmCP_CPC_IC_BASE_LO)/sizeof(mmCP_CPC_IC_BASE_LO[0]), 0, 0 }, + { "mmCP_CPC_IC_BASE_HI", REG_MMIO, 0x10ba, 0, &mmCP_CPC_IC_BASE_HI[0], sizeof(mmCP_CPC_IC_BASE_HI)/sizeof(mmCP_CPC_IC_BASE_HI[0]), 0, 0 }, + { "mmCP_CPC_IC_BASE_CNTL", REG_MMIO, 0x10bb, 0, &mmCP_CPC_IC_BASE_CNTL[0], sizeof(mmCP_CPC_IC_BASE_CNTL)/sizeof(mmCP_CPC_IC_BASE_CNTL[0]), 0, 0 }, + { "mmCP_CPC_IC_OP_CNTL", REG_MMIO, 0x10bc, 0, &mmCP_CPC_IC_OP_CNTL[0], sizeof(mmCP_CPC_IC_OP_CNTL)/sizeof(mmCP_CPC_IC_OP_CNTL[0]), 0, 0 }, + { "mmCP_MEC1_F32_INT_DIS", REG_MMIO, 0x10bd, 0, &mmCP_MEC1_F32_INT_DIS[0], sizeof(mmCP_MEC1_F32_INT_DIS)/sizeof(mmCP_MEC1_F32_INT_DIS[0]), 0, 0 }, + { "mmCP_MEC2_F32_INT_DIS", REG_MMIO, 0x10be, 0, &mmCP_MEC2_F32_INT_DIS[0], sizeof(mmCP_MEC2_F32_INT_DIS)/sizeof(mmCP_MEC2_F32_INT_DIS[0]), 0, 0 }, + { "mmCP_VMID_STATUS", REG_MMIO, 0x10bf, 0, &mmCP_VMID_STATUS[0], sizeof(mmCP_VMID_STATUS)/sizeof(mmCP_VMID_STATUS[0]), 0, 0 }, + { "mmCP_RB_DOORBELL_CONTROL_SCH_0", REG_MMIO, 0x1180, 0, &mmCP_RB_DOORBELL_CONTROL_SCH_0[0], sizeof(mmCP_RB_DOORBELL_CONTROL_SCH_0)/sizeof(mmCP_RB_DOORBELL_CONTROL_SCH_0[0]), 0, 0 }, + { "mmCP_RB_DOORBELL_CONTROL_SCH_1", REG_MMIO, 0x1181, 0, &mmCP_RB_DOORBELL_CONTROL_SCH_1[0], sizeof(mmCP_RB_DOORBELL_CONTROL_SCH_1)/sizeof(mmCP_RB_DOORBELL_CONTROL_SCH_1[0]), 0, 0 }, + { "mmCP_RB_DOORBELL_CONTROL_SCH_2", REG_MMIO, 0x1182, 0, &mmCP_RB_DOORBELL_CONTROL_SCH_2[0], sizeof(mmCP_RB_DOORBELL_CONTROL_SCH_2)/sizeof(mmCP_RB_DOORBELL_CONTROL_SCH_2[0]), 0, 0 }, + { "mmCP_RB_DOORBELL_CONTROL_SCH_3", REG_MMIO, 0x1183, 0, &mmCP_RB_DOORBELL_CONTROL_SCH_3[0], sizeof(mmCP_RB_DOORBELL_CONTROL_SCH_3)/sizeof(mmCP_RB_DOORBELL_CONTROL_SCH_3[0]), 0, 0 }, + { "mmCP_RB_DOORBELL_CONTROL_SCH_4", REG_MMIO, 0x1184, 0, &mmCP_RB_DOORBELL_CONTROL_SCH_4[0], sizeof(mmCP_RB_DOORBELL_CONTROL_SCH_4)/sizeof(mmCP_RB_DOORBELL_CONTROL_SCH_4[0]), 0, 0 }, + { "mmCP_RB_DOORBELL_CONTROL_SCH_5", REG_MMIO, 0x1185, 0, &mmCP_RB_DOORBELL_CONTROL_SCH_5[0], sizeof(mmCP_RB_DOORBELL_CONTROL_SCH_5)/sizeof(mmCP_RB_DOORBELL_CONTROL_SCH_5[0]), 0, 0 }, + { "mmCP_RB_DOORBELL_CONTROL_SCH_6", REG_MMIO, 0x1186, 0, &mmCP_RB_DOORBELL_CONTROL_SCH_6[0], sizeof(mmCP_RB_DOORBELL_CONTROL_SCH_6)/sizeof(mmCP_RB_DOORBELL_CONTROL_SCH_6[0]), 0, 0 }, + { "mmCP_RB_DOORBELL_CONTROL_SCH_7", REG_MMIO, 0x1187, 0, &mmCP_RB_DOORBELL_CONTROL_SCH_7[0], sizeof(mmCP_RB_DOORBELL_CONTROL_SCH_7)/sizeof(mmCP_RB_DOORBELL_CONTROL_SCH_7[0]), 0, 0 }, + { "mmCP_RB_DOORBELL_CLEAR", REG_MMIO, 0x1188, 0, &mmCP_RB_DOORBELL_CLEAR[0], sizeof(mmCP_RB_DOORBELL_CLEAR)/sizeof(mmCP_RB_DOORBELL_CLEAR[0]), 0, 0 }, + { "mmCP_GFX_MQD_CONTROL", REG_MMIO, 0x11a0, 0, &mmCP_GFX_MQD_CONTROL[0], sizeof(mmCP_GFX_MQD_CONTROL)/sizeof(mmCP_GFX_MQD_CONTROL[0]), 0, 0 }, + { "mmCP_GFX_MQD_BASE_ADDR", REG_MMIO, 0x11a1, 0, &mmCP_GFX_MQD_BASE_ADDR[0], sizeof(mmCP_GFX_MQD_BASE_ADDR)/sizeof(mmCP_GFX_MQD_BASE_ADDR[0]), 0, 0 }, + { "mmCP_GFX_MQD_BASE_ADDR_HI", REG_MMIO, 0x11a2, 0, &mmCP_GFX_MQD_BASE_ADDR_HI[0], sizeof(mmCP_GFX_MQD_BASE_ADDR_HI)/sizeof(mmCP_GFX_MQD_BASE_ADDR_HI[0]), 0, 0 }, + { "mmCP_RB_STATUS", REG_MMIO, 0x11a3, 0, &mmCP_RB_STATUS[0], sizeof(mmCP_RB_STATUS)/sizeof(mmCP_RB_STATUS[0]), 0, 0 }, + { "mmCPG_UTCL1_STATUS", REG_MMIO, 0x11b4, 0, &mmCPG_UTCL1_STATUS[0], sizeof(mmCPG_UTCL1_STATUS)/sizeof(mmCPG_UTCL1_STATUS[0]), 0, 0 }, + { "mmCPC_UTCL1_STATUS", REG_MMIO, 0x11b5, 0, &mmCPC_UTCL1_STATUS[0], sizeof(mmCPC_UTCL1_STATUS)/sizeof(mmCPC_UTCL1_STATUS[0]), 0, 0 }, + { "mmCPF_UTCL1_STATUS", REG_MMIO, 0x11b6, 0, &mmCPF_UTCL1_STATUS[0], sizeof(mmCPF_UTCL1_STATUS)/sizeof(mmCPF_UTCL1_STATUS[0]), 0, 0 }, + { "mmCP_SD_CNTL", REG_MMIO, 0x11b7, 0, &mmCP_SD_CNTL[0], sizeof(mmCP_SD_CNTL)/sizeof(mmCP_SD_CNTL[0]), 0, 0 }, + { "mmCP_SOFT_RESET_CNTL", REG_MMIO, 0x11b9, 0, &mmCP_SOFT_RESET_CNTL[0], sizeof(mmCP_SOFT_RESET_CNTL)/sizeof(mmCP_SOFT_RESET_CNTL[0]), 0, 0 }, + { "mmCP_CPC_GFX_CNTL", REG_MMIO, 0x11ba, 0, &mmCP_CPC_GFX_CNTL[0], sizeof(mmCP_CPC_GFX_CNTL)/sizeof(mmCP_CPC_GFX_CNTL[0]), 0, 0 }, + { "mmSPI_ARB_PRIORITY", REG_MMIO, 0x11c0, 0, &mmSPI_ARB_PRIORITY[0], sizeof(mmSPI_ARB_PRIORITY)/sizeof(mmSPI_ARB_PRIORITY[0]), 0, 0 }, + { "mmSPI_ARB_CYCLES_0", REG_MMIO, 0x11c1, 0, &mmSPI_ARB_CYCLES_0[0], sizeof(mmSPI_ARB_CYCLES_0)/sizeof(mmSPI_ARB_CYCLES_0[0]), 0, 0 }, + { "mmSPI_ARB_CYCLES_1", REG_MMIO, 0x11c2, 0, &mmSPI_ARB_CYCLES_1[0], sizeof(mmSPI_ARB_CYCLES_1)/sizeof(mmSPI_ARB_CYCLES_1[0]), 0, 0 }, + { "mmSPI_WCL_PIPE_PERCENT_GFX", REG_MMIO, 0x11c7, 0, &mmSPI_WCL_PIPE_PERCENT_GFX[0], sizeof(mmSPI_WCL_PIPE_PERCENT_GFX)/sizeof(mmSPI_WCL_PIPE_PERCENT_GFX[0]), 0, 0 }, + { "mmSPI_WCL_PIPE_PERCENT_HP3D", REG_MMIO, 0x11c8, 0, &mmSPI_WCL_PIPE_PERCENT_HP3D[0], sizeof(mmSPI_WCL_PIPE_PERCENT_HP3D)/sizeof(mmSPI_WCL_PIPE_PERCENT_HP3D[0]), 0, 0 }, + { "mmSPI_WCL_PIPE_PERCENT_CS0", REG_MMIO, 0x11c9, 0, &mmSPI_WCL_PIPE_PERCENT_CS0[0], sizeof(mmSPI_WCL_PIPE_PERCENT_CS0)/sizeof(mmSPI_WCL_PIPE_PERCENT_CS0[0]), 0, 0 }, + { "mmSPI_WCL_PIPE_PERCENT_CS1", REG_MMIO, 0x11ca, 0, &mmSPI_WCL_PIPE_PERCENT_CS1[0], sizeof(mmSPI_WCL_PIPE_PERCENT_CS1)/sizeof(mmSPI_WCL_PIPE_PERCENT_CS1[0]), 0, 0 }, + { "mmSPI_WCL_PIPE_PERCENT_CS2", REG_MMIO, 0x11cb, 0, &mmSPI_WCL_PIPE_PERCENT_CS2[0], sizeof(mmSPI_WCL_PIPE_PERCENT_CS2)/sizeof(mmSPI_WCL_PIPE_PERCENT_CS2[0]), 0, 0 }, + { "mmSPI_WCL_PIPE_PERCENT_CS3", REG_MMIO, 0x11cc, 0, &mmSPI_WCL_PIPE_PERCENT_CS3[0], sizeof(mmSPI_WCL_PIPE_PERCENT_CS3)/sizeof(mmSPI_WCL_PIPE_PERCENT_CS3[0]), 0, 0 }, + { "mmSPI_WCL_PIPE_PERCENT_CS4", REG_MMIO, 0x11cd, 0, &mmSPI_WCL_PIPE_PERCENT_CS4[0], sizeof(mmSPI_WCL_PIPE_PERCENT_CS4)/sizeof(mmSPI_WCL_PIPE_PERCENT_CS4[0]), 0, 0 }, + { "mmSPI_WCL_PIPE_PERCENT_CS5", REG_MMIO, 0x11ce, 0, &mmSPI_WCL_PIPE_PERCENT_CS5[0], sizeof(mmSPI_WCL_PIPE_PERCENT_CS5)/sizeof(mmSPI_WCL_PIPE_PERCENT_CS5[0]), 0, 0 }, + { "mmSPI_WCL_PIPE_PERCENT_CS6", REG_MMIO, 0x11cf, 0, &mmSPI_WCL_PIPE_PERCENT_CS6[0], sizeof(mmSPI_WCL_PIPE_PERCENT_CS6)/sizeof(mmSPI_WCL_PIPE_PERCENT_CS6[0]), 0, 0 }, + { "mmSPI_WCL_PIPE_PERCENT_CS7", REG_MMIO, 0x11d0, 0, &mmSPI_WCL_PIPE_PERCENT_CS7[0], sizeof(mmSPI_WCL_PIPE_PERCENT_CS7)/sizeof(mmSPI_WCL_PIPE_PERCENT_CS7[0]), 0, 0 }, + { "mmSPI_COMPUTE_QUEUE_RESET", REG_MMIO, 0x11db, 0, &mmSPI_COMPUTE_QUEUE_RESET[0], sizeof(mmSPI_COMPUTE_QUEUE_RESET)/sizeof(mmSPI_COMPUTE_QUEUE_RESET[0]), 0, 0 }, + { "mmSPI_RESOURCE_RESERVE_CU_0", REG_MMIO, 0x11dc, 0, &mmSPI_RESOURCE_RESERVE_CU_0[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_0)/sizeof(mmSPI_RESOURCE_RESERVE_CU_0[0]), 0, 0 }, + { "mmSPI_RESOURCE_RESERVE_CU_1", REG_MMIO, 0x11dd, 0, &mmSPI_RESOURCE_RESERVE_CU_1[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_1)/sizeof(mmSPI_RESOURCE_RESERVE_CU_1[0]), 0, 0 }, + { "mmSPI_RESOURCE_RESERVE_CU_2", REG_MMIO, 0x11de, 0, &mmSPI_RESOURCE_RESERVE_CU_2[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_2)/sizeof(mmSPI_RESOURCE_RESERVE_CU_2[0]), 0, 0 }, + { "mmSPI_RESOURCE_RESERVE_CU_3", REG_MMIO, 0x11df, 0, &mmSPI_RESOURCE_RESERVE_CU_3[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_3)/sizeof(mmSPI_RESOURCE_RESERVE_CU_3[0]), 0, 0 }, + { "mmSPI_RESOURCE_RESERVE_CU_4", REG_MMIO, 0x11e0, 0, &mmSPI_RESOURCE_RESERVE_CU_4[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_4)/sizeof(mmSPI_RESOURCE_RESERVE_CU_4[0]), 0, 0 }, + { "mmSPI_RESOURCE_RESERVE_CU_5", REG_MMIO, 0x11e1, 0, &mmSPI_RESOURCE_RESERVE_CU_5[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_5)/sizeof(mmSPI_RESOURCE_RESERVE_CU_5[0]), 0, 0 }, + { "mmSPI_RESOURCE_RESERVE_CU_6", REG_MMIO, 0x11e2, 0, &mmSPI_RESOURCE_RESERVE_CU_6[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_6)/sizeof(mmSPI_RESOURCE_RESERVE_CU_6[0]), 0, 0 }, + { "mmSPI_RESOURCE_RESERVE_CU_7", REG_MMIO, 0x11e3, 0, &mmSPI_RESOURCE_RESERVE_CU_7[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_7)/sizeof(mmSPI_RESOURCE_RESERVE_CU_7[0]), 0, 0 }, + { "mmSPI_RESOURCE_RESERVE_CU_8", REG_MMIO, 0x11e4, 0, &mmSPI_RESOURCE_RESERVE_CU_8[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_8)/sizeof(mmSPI_RESOURCE_RESERVE_CU_8[0]), 0, 0 }, + { "mmSPI_RESOURCE_RESERVE_CU_9", REG_MMIO, 0x11e5, 0, &mmSPI_RESOURCE_RESERVE_CU_9[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_9)/sizeof(mmSPI_RESOURCE_RESERVE_CU_9[0]), 0, 0 }, + { "mmSPI_RESOURCE_RESERVE_EN_CU_0", REG_MMIO, 0x11e6, 0, &mmSPI_RESOURCE_RESERVE_EN_CU_0[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_0)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_0[0]), 0, 0 }, + { "mmSPI_RESOURCE_RESERVE_EN_CU_1", REG_MMIO, 0x11e7, 0, &mmSPI_RESOURCE_RESERVE_EN_CU_1[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_1)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_1[0]), 0, 0 }, + { "mmSPI_RESOURCE_RESERVE_EN_CU_2", REG_MMIO, 0x11e8, 0, &mmSPI_RESOURCE_RESERVE_EN_CU_2[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_2)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_2[0]), 0, 0 }, + { "mmSPI_RESOURCE_RESERVE_EN_CU_3", REG_MMIO, 0x11e9, 0, &mmSPI_RESOURCE_RESERVE_EN_CU_3[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_3)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_3[0]), 0, 0 }, + { "mmSPI_RESOURCE_RESERVE_EN_CU_4", REG_MMIO, 0x11ea, 0, &mmSPI_RESOURCE_RESERVE_EN_CU_4[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_4)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_4[0]), 0, 0 }, + { "mmSPI_RESOURCE_RESERVE_EN_CU_5", REG_MMIO, 0x11eb, 0, &mmSPI_RESOURCE_RESERVE_EN_CU_5[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_5)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_5[0]), 0, 0 }, + { "mmSPI_RESOURCE_RESERVE_EN_CU_6", REG_MMIO, 0x11ec, 0, &mmSPI_RESOURCE_RESERVE_EN_CU_6[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_6)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_6[0]), 0, 0 }, + { "mmSPI_RESOURCE_RESERVE_EN_CU_7", REG_MMIO, 0x11ed, 0, &mmSPI_RESOURCE_RESERVE_EN_CU_7[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_7)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_7[0]), 0, 0 }, + { "mmSPI_RESOURCE_RESERVE_EN_CU_8", REG_MMIO, 0x11ee, 0, &mmSPI_RESOURCE_RESERVE_EN_CU_8[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_8)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_8[0]), 0, 0 }, + { "mmSPI_RESOURCE_RESERVE_EN_CU_9", REG_MMIO, 0x11ef, 0, &mmSPI_RESOURCE_RESERVE_EN_CU_9[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_9)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_9[0]), 0, 0 }, + { "mmSPI_RESOURCE_RESERVE_CU_10", REG_MMIO, 0x11f0, 0, &mmSPI_RESOURCE_RESERVE_CU_10[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_10)/sizeof(mmSPI_RESOURCE_RESERVE_CU_10[0]), 0, 0 }, + { "mmSPI_RESOURCE_RESERVE_CU_11", REG_MMIO, 0x11f1, 0, &mmSPI_RESOURCE_RESERVE_CU_11[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_11)/sizeof(mmSPI_RESOURCE_RESERVE_CU_11[0]), 0, 0 }, + { "mmSPI_RESOURCE_RESERVE_EN_CU_10", REG_MMIO, 0x11f2, 0, &mmSPI_RESOURCE_RESERVE_EN_CU_10[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_10)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_10[0]), 0, 0 }, + { "mmSPI_RESOURCE_RESERVE_EN_CU_11", REG_MMIO, 0x11f3, 0, &mmSPI_RESOURCE_RESERVE_EN_CU_11[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_11)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_11[0]), 0, 0 }, + { "mmSPI_RESOURCE_RESERVE_CU_12", REG_MMIO, 0x11f4, 0, &mmSPI_RESOURCE_RESERVE_CU_12[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_12)/sizeof(mmSPI_RESOURCE_RESERVE_CU_12[0]), 0, 0 }, + { "mmSPI_RESOURCE_RESERVE_CU_13", REG_MMIO, 0x11f5, 0, &mmSPI_RESOURCE_RESERVE_CU_13[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_13)/sizeof(mmSPI_RESOURCE_RESERVE_CU_13[0]), 0, 0 }, + { "mmSPI_RESOURCE_RESERVE_CU_14", REG_MMIO, 0x11f6, 0, &mmSPI_RESOURCE_RESERVE_CU_14[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_14)/sizeof(mmSPI_RESOURCE_RESERVE_CU_14[0]), 0, 0 }, + { "mmSPI_RESOURCE_RESERVE_CU_15", REG_MMIO, 0x11f7, 0, &mmSPI_RESOURCE_RESERVE_CU_15[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_15)/sizeof(mmSPI_RESOURCE_RESERVE_CU_15[0]), 0, 0 }, + { "mmSPI_RESOURCE_RESERVE_EN_CU_12", REG_MMIO, 0x11f8, 0, &mmSPI_RESOURCE_RESERVE_EN_CU_12[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_12)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_12[0]), 0, 0 }, + { "mmSPI_RESOURCE_RESERVE_EN_CU_13", REG_MMIO, 0x11f9, 0, &mmSPI_RESOURCE_RESERVE_EN_CU_13[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_13)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_13[0]), 0, 0 }, + { "mmSPI_RESOURCE_RESERVE_EN_CU_14", REG_MMIO, 0x11fa, 0, &mmSPI_RESOURCE_RESERVE_EN_CU_14[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_14)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_14[0]), 0, 0 }, + { "mmSPI_RESOURCE_RESERVE_EN_CU_15", REG_MMIO, 0x11fb, 0, &mmSPI_RESOURCE_RESERVE_EN_CU_15[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_15)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_15[0]), 0, 0 }, + { "mmSPI_COMPUTE_WF_CTX_SAVE", REG_MMIO, 0x11fc, 0, &mmSPI_COMPUTE_WF_CTX_SAVE[0], sizeof(mmSPI_COMPUTE_WF_CTX_SAVE)/sizeof(mmSPI_COMPUTE_WF_CTX_SAVE[0]), 0, 0 }, + { "mmSPI_ARB_CNTL_0", REG_MMIO, 0x11fd, 0, &mmSPI_ARB_CNTL_0[0], sizeof(mmSPI_ARB_CNTL_0)/sizeof(mmSPI_ARB_CNTL_0[0]), 0, 0 }, + { "mmCP_HQD_GFX_CONTROL", REG_MMIO, 0x123e, 0, &mmCP_HQD_GFX_CONTROL[0], sizeof(mmCP_HQD_GFX_CONTROL)/sizeof(mmCP_HQD_GFX_CONTROL[0]), 0, 0 }, + { "mmCP_HQD_GFX_STATUS", REG_MMIO, 0x123f, 0, &mmCP_HQD_GFX_STATUS[0], sizeof(mmCP_HQD_GFX_STATUS)/sizeof(mmCP_HQD_GFX_STATUS[0]), 0, 0 }, + { "mmCP_HPD_ROQ_OFFSETS", REG_MMIO, 0x1240, 0, &mmCP_HPD_ROQ_OFFSETS[0], sizeof(mmCP_HPD_ROQ_OFFSETS)/sizeof(mmCP_HPD_ROQ_OFFSETS[0]), 0, 0 }, + { "mmCP_HPD_STATUS0", REG_MMIO, 0x1241, 0, &mmCP_HPD_STATUS0[0], sizeof(mmCP_HPD_STATUS0)/sizeof(mmCP_HPD_STATUS0[0]), 0, 0 }, + { "mmCP_HPD_UTCL1_CNTL", REG_MMIO, 0x1242, 0, &mmCP_HPD_UTCL1_CNTL[0], sizeof(mmCP_HPD_UTCL1_CNTL)/sizeof(mmCP_HPD_UTCL1_CNTL[0]), 0, 0 }, + { "mmCP_HPD_UTCL1_ERROR", REG_MMIO, 0x1243, 0, &mmCP_HPD_UTCL1_ERROR[0], sizeof(mmCP_HPD_UTCL1_ERROR)/sizeof(mmCP_HPD_UTCL1_ERROR[0]), 0, 0 }, + { "mmCP_HPD_UTCL1_ERROR_ADDR", REG_MMIO, 0x1244, 0, &mmCP_HPD_UTCL1_ERROR_ADDR[0], sizeof(mmCP_HPD_UTCL1_ERROR_ADDR)/sizeof(mmCP_HPD_UTCL1_ERROR_ADDR[0]), 0, 0 }, + { "mmCP_MQD_BASE_ADDR", REG_MMIO, 0x1245, 0, &mmCP_MQD_BASE_ADDR[0], sizeof(mmCP_MQD_BASE_ADDR)/sizeof(mmCP_MQD_BASE_ADDR[0]), 0, 0 }, + { "mmCP_MQD_BASE_ADDR_HI", REG_MMIO, 0x1246, 0, &mmCP_MQD_BASE_ADDR_HI[0], sizeof(mmCP_MQD_BASE_ADDR_HI)/sizeof(mmCP_MQD_BASE_ADDR_HI[0]), 0, 0 }, + { "mmCP_HQD_ACTIVE", REG_MMIO, 0x1247, 0, &mmCP_HQD_ACTIVE[0], sizeof(mmCP_HQD_ACTIVE)/sizeof(mmCP_HQD_ACTIVE[0]), 0, 0 }, + { "mmCP_HQD_VMID", REG_MMIO, 0x1248, 0, &mmCP_HQD_VMID[0], sizeof(mmCP_HQD_VMID)/sizeof(mmCP_HQD_VMID[0]), 0, 0 }, + { "mmCP_HQD_PERSISTENT_STATE", REG_MMIO, 0x1249, 0, &mmCP_HQD_PERSISTENT_STATE[0], sizeof(mmCP_HQD_PERSISTENT_STATE)/sizeof(mmCP_HQD_PERSISTENT_STATE[0]), 0, 0 }, + { "mmCP_HQD_PIPE_PRIORITY", REG_MMIO, 0x124a, 0, &mmCP_HQD_PIPE_PRIORITY[0], sizeof(mmCP_HQD_PIPE_PRIORITY)/sizeof(mmCP_HQD_PIPE_PRIORITY[0]), 0, 0 }, + { "mmCP_HQD_QUEUE_PRIORITY", REG_MMIO, 0x124b, 0, &mmCP_HQD_QUEUE_PRIORITY[0], sizeof(mmCP_HQD_QUEUE_PRIORITY)/sizeof(mmCP_HQD_QUEUE_PRIORITY[0]), 0, 0 }, + { "mmCP_HQD_QUANTUM", REG_MMIO, 0x124c, 0, &mmCP_HQD_QUANTUM[0], sizeof(mmCP_HQD_QUANTUM)/sizeof(mmCP_HQD_QUANTUM[0]), 0, 0 }, + { "mmCP_HQD_PQ_BASE", REG_MMIO, 0x124d, 0, &mmCP_HQD_PQ_BASE[0], sizeof(mmCP_HQD_PQ_BASE)/sizeof(mmCP_HQD_PQ_BASE[0]), 0, 0 }, + { "mmCP_HQD_PQ_BASE_HI", REG_MMIO, 0x124e, 0, &mmCP_HQD_PQ_BASE_HI[0], sizeof(mmCP_HQD_PQ_BASE_HI)/sizeof(mmCP_HQD_PQ_BASE_HI[0]), 0, 0 }, + { "mmCP_HQD_PQ_RPTR", REG_MMIO, 0x124f, 0, &mmCP_HQD_PQ_RPTR[0], sizeof(mmCP_HQD_PQ_RPTR)/sizeof(mmCP_HQD_PQ_RPTR[0]), 0, 0 }, + { "mmCP_HQD_PQ_RPTR_REPORT_ADDR", REG_MMIO, 0x1250, 0, &mmCP_HQD_PQ_RPTR_REPORT_ADDR[0], sizeof(mmCP_HQD_PQ_RPTR_REPORT_ADDR)/sizeof(mmCP_HQD_PQ_RPTR_REPORT_ADDR[0]), 0, 0 }, + { "mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI", REG_MMIO, 0x1251, 0, &mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI[0], sizeof(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI)/sizeof(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI[0]), 0, 0 }, + { "mmCP_HQD_PQ_WPTR_POLL_ADDR", REG_MMIO, 0x1252, 0, &mmCP_HQD_PQ_WPTR_POLL_ADDR[0], sizeof(mmCP_HQD_PQ_WPTR_POLL_ADDR)/sizeof(mmCP_HQD_PQ_WPTR_POLL_ADDR[0]), 0, 0 }, + { "mmCP_HQD_PQ_WPTR_POLL_ADDR_HI", REG_MMIO, 0x1253, 0, &mmCP_HQD_PQ_WPTR_POLL_ADDR_HI[0], sizeof(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI)/sizeof(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI[0]), 0, 0 }, + { "mmCP_HQD_PQ_DOORBELL_CONTROL", REG_MMIO, 0x1254, 0, &mmCP_HQD_PQ_DOORBELL_CONTROL[0], sizeof(mmCP_HQD_PQ_DOORBELL_CONTROL)/sizeof(mmCP_HQD_PQ_DOORBELL_CONTROL[0]), 0, 0 }, + { "mmCP_HQD_PQ_CONTROL", REG_MMIO, 0x1256, 0, &mmCP_HQD_PQ_CONTROL[0], sizeof(mmCP_HQD_PQ_CONTROL)/sizeof(mmCP_HQD_PQ_CONTROL[0]), 0, 0 }, + { "mmCP_HQD_IB_BASE_ADDR", REG_MMIO, 0x1257, 0, &mmCP_HQD_IB_BASE_ADDR[0], sizeof(mmCP_HQD_IB_BASE_ADDR)/sizeof(mmCP_HQD_IB_BASE_ADDR[0]), 0, 0 }, + { "mmCP_HQD_IB_BASE_ADDR_HI", REG_MMIO, 0x1258, 0, &mmCP_HQD_IB_BASE_ADDR_HI[0], sizeof(mmCP_HQD_IB_BASE_ADDR_HI)/sizeof(mmCP_HQD_IB_BASE_ADDR_HI[0]), 0, 0 }, + { "mmCP_HQD_IB_RPTR", REG_MMIO, 0x1259, 0, &mmCP_HQD_IB_RPTR[0], sizeof(mmCP_HQD_IB_RPTR)/sizeof(mmCP_HQD_IB_RPTR[0]), 0, 0 }, + { "mmCP_HQD_IB_CONTROL", REG_MMIO, 0x125a, 0, &mmCP_HQD_IB_CONTROL[0], sizeof(mmCP_HQD_IB_CONTROL)/sizeof(mmCP_HQD_IB_CONTROL[0]), 0, 0 }, + { "mmCP_HQD_IQ_TIMER", REG_MMIO, 0x125b, 0, &mmCP_HQD_IQ_TIMER[0], sizeof(mmCP_HQD_IQ_TIMER)/sizeof(mmCP_HQD_IQ_TIMER[0]), 0, 0 }, + { "mmCP_HQD_IQ_RPTR", REG_MMIO, 0x125c, 0, &mmCP_HQD_IQ_RPTR[0], sizeof(mmCP_HQD_IQ_RPTR)/sizeof(mmCP_HQD_IQ_RPTR[0]), 0, 0 }, + { "mmCP_HQD_DEQUEUE_REQUEST", REG_MMIO, 0x125d, 0, &mmCP_HQD_DEQUEUE_REQUEST[0], sizeof(mmCP_HQD_DEQUEUE_REQUEST)/sizeof(mmCP_HQD_DEQUEUE_REQUEST[0]), 0, 0 }, + { "mmCP_HQD_DMA_OFFLOAD", REG_MMIO, 0x125e, 0, &mmCP_HQD_DMA_OFFLOAD[0], sizeof(mmCP_HQD_DMA_OFFLOAD)/sizeof(mmCP_HQD_DMA_OFFLOAD[0]), 0, 0 }, + { "mmCP_HQD_OFFLOAD", REG_MMIO, 0x125e, 0, &mmCP_HQD_OFFLOAD[0], sizeof(mmCP_HQD_OFFLOAD)/sizeof(mmCP_HQD_OFFLOAD[0]), 0, 0 }, + { "mmCP_HQD_SEMA_CMD", REG_MMIO, 0x125f, 0, &mmCP_HQD_SEMA_CMD[0], sizeof(mmCP_HQD_SEMA_CMD)/sizeof(mmCP_HQD_SEMA_CMD[0]), 0, 0 }, + { "mmCP_HQD_MSG_TYPE", REG_MMIO, 0x1260, 0, &mmCP_HQD_MSG_TYPE[0], sizeof(mmCP_HQD_MSG_TYPE)/sizeof(mmCP_HQD_MSG_TYPE[0]), 0, 0 }, + { "mmCP_HQD_ATOMIC0_PREOP_LO", REG_MMIO, 0x1261, 0, &mmCP_HQD_ATOMIC0_PREOP_LO[0], sizeof(mmCP_HQD_ATOMIC0_PREOP_LO)/sizeof(mmCP_HQD_ATOMIC0_PREOP_LO[0]), 0, 0 }, + { "mmCP_HQD_ATOMIC0_PREOP_HI", REG_MMIO, 0x1262, 0, &mmCP_HQD_ATOMIC0_PREOP_HI[0], sizeof(mmCP_HQD_ATOMIC0_PREOP_HI)/sizeof(mmCP_HQD_ATOMIC0_PREOP_HI[0]), 0, 0 }, + { "mmCP_HQD_ATOMIC1_PREOP_LO", REG_MMIO, 0x1263, 0, &mmCP_HQD_ATOMIC1_PREOP_LO[0], sizeof(mmCP_HQD_ATOMIC1_PREOP_LO)/sizeof(mmCP_HQD_ATOMIC1_PREOP_LO[0]), 0, 0 }, + { "mmCP_HQD_ATOMIC1_PREOP_HI", REG_MMIO, 0x1264, 0, &mmCP_HQD_ATOMIC1_PREOP_HI[0], sizeof(mmCP_HQD_ATOMIC1_PREOP_HI)/sizeof(mmCP_HQD_ATOMIC1_PREOP_HI[0]), 0, 0 }, + { "mmCP_HQD_HQ_SCHEDULER0", REG_MMIO, 0x1265, 0, &mmCP_HQD_HQ_SCHEDULER0[0], sizeof(mmCP_HQD_HQ_SCHEDULER0)/sizeof(mmCP_HQD_HQ_SCHEDULER0[0]), 0, 0 }, + { "mmCP_HQD_HQ_STATUS0", REG_MMIO, 0x1265, 0, &mmCP_HQD_HQ_STATUS0[0], sizeof(mmCP_HQD_HQ_STATUS0)/sizeof(mmCP_HQD_HQ_STATUS0[0]), 0, 0 }, + { "mmCP_HQD_HQ_CONTROL0", REG_MMIO, 0x1266, 0, &mmCP_HQD_HQ_CONTROL0[0], sizeof(mmCP_HQD_HQ_CONTROL0)/sizeof(mmCP_HQD_HQ_CONTROL0[0]), 0, 0 }, + { "mmCP_HQD_HQ_SCHEDULER1", REG_MMIO, 0x1266, 0, &mmCP_HQD_HQ_SCHEDULER1[0], sizeof(mmCP_HQD_HQ_SCHEDULER1)/sizeof(mmCP_HQD_HQ_SCHEDULER1[0]), 0, 0 }, + { "mmCP_MQD_CONTROL", REG_MMIO, 0x1267, 0, &mmCP_MQD_CONTROL[0], sizeof(mmCP_MQD_CONTROL)/sizeof(mmCP_MQD_CONTROL[0]), 0, 0 }, + { "mmCP_HQD_HQ_STATUS1", REG_MMIO, 0x1268, 0, &mmCP_HQD_HQ_STATUS1[0], sizeof(mmCP_HQD_HQ_STATUS1)/sizeof(mmCP_HQD_HQ_STATUS1[0]), 0, 0 }, + { "mmCP_HQD_HQ_CONTROL1", REG_MMIO, 0x1269, 0, &mmCP_HQD_HQ_CONTROL1[0], sizeof(mmCP_HQD_HQ_CONTROL1)/sizeof(mmCP_HQD_HQ_CONTROL1[0]), 0, 0 }, + { "mmCP_HQD_EOP_BASE_ADDR", REG_MMIO, 0x126a, 0, &mmCP_HQD_EOP_BASE_ADDR[0], sizeof(mmCP_HQD_EOP_BASE_ADDR)/sizeof(mmCP_HQD_EOP_BASE_ADDR[0]), 0, 0 }, + { "mmCP_HQD_EOP_BASE_ADDR_HI", REG_MMIO, 0x126b, 0, &mmCP_HQD_EOP_BASE_ADDR_HI[0], sizeof(mmCP_HQD_EOP_BASE_ADDR_HI)/sizeof(mmCP_HQD_EOP_BASE_ADDR_HI[0]), 0, 0 }, + { "mmCP_HQD_EOP_CONTROL", REG_MMIO, 0x126c, 0, &mmCP_HQD_EOP_CONTROL[0], sizeof(mmCP_HQD_EOP_CONTROL)/sizeof(mmCP_HQD_EOP_CONTROL[0]), 0, 0 }, + { "mmCP_HQD_EOP_RPTR", REG_MMIO, 0x126d, 0, &mmCP_HQD_EOP_RPTR[0], sizeof(mmCP_HQD_EOP_RPTR)/sizeof(mmCP_HQD_EOP_RPTR[0]), 0, 0 }, + { "mmCP_HQD_EOP_WPTR", REG_MMIO, 0x126e, 0, &mmCP_HQD_EOP_WPTR[0], sizeof(mmCP_HQD_EOP_WPTR)/sizeof(mmCP_HQD_EOP_WPTR[0]), 0, 0 }, + { "mmCP_HQD_EOP_EVENTS", REG_MMIO, 0x126f, 0, &mmCP_HQD_EOP_EVENTS[0], sizeof(mmCP_HQD_EOP_EVENTS)/sizeof(mmCP_HQD_EOP_EVENTS[0]), 0, 0 }, + { "mmCP_HQD_CTX_SAVE_BASE_ADDR_LO", REG_MMIO, 0x1270, 0, &mmCP_HQD_CTX_SAVE_BASE_ADDR_LO[0], sizeof(mmCP_HQD_CTX_SAVE_BASE_ADDR_LO)/sizeof(mmCP_HQD_CTX_SAVE_BASE_ADDR_LO[0]), 0, 0 }, + { "mmCP_HQD_CTX_SAVE_BASE_ADDR_HI", REG_MMIO, 0x1271, 0, &mmCP_HQD_CTX_SAVE_BASE_ADDR_HI[0], sizeof(mmCP_HQD_CTX_SAVE_BASE_ADDR_HI)/sizeof(mmCP_HQD_CTX_SAVE_BASE_ADDR_HI[0]), 0, 0 }, + { "mmCP_HQD_CTX_SAVE_CONTROL", REG_MMIO, 0x1272, 0, &mmCP_HQD_CTX_SAVE_CONTROL[0], sizeof(mmCP_HQD_CTX_SAVE_CONTROL)/sizeof(mmCP_HQD_CTX_SAVE_CONTROL[0]), 0, 0 }, + { "mmCP_HQD_CNTL_STACK_OFFSET", REG_MMIO, 0x1273, 0, &mmCP_HQD_CNTL_STACK_OFFSET[0], sizeof(mmCP_HQD_CNTL_STACK_OFFSET)/sizeof(mmCP_HQD_CNTL_STACK_OFFSET[0]), 0, 0 }, + { "mmCP_HQD_CNTL_STACK_SIZE", REG_MMIO, 0x1274, 0, &mmCP_HQD_CNTL_STACK_SIZE[0], sizeof(mmCP_HQD_CNTL_STACK_SIZE)/sizeof(mmCP_HQD_CNTL_STACK_SIZE[0]), 0, 0 }, + { "mmCP_HQD_WG_STATE_OFFSET", REG_MMIO, 0x1275, 0, &mmCP_HQD_WG_STATE_OFFSET[0], sizeof(mmCP_HQD_WG_STATE_OFFSET)/sizeof(mmCP_HQD_WG_STATE_OFFSET[0]), 0, 0 }, + { "mmCP_HQD_CTX_SAVE_SIZE", REG_MMIO, 0x1276, 0, &mmCP_HQD_CTX_SAVE_SIZE[0], sizeof(mmCP_HQD_CTX_SAVE_SIZE)/sizeof(mmCP_HQD_CTX_SAVE_SIZE[0]), 0, 0 }, + { "mmCP_HQD_GDS_RESOURCE_STATE", REG_MMIO, 0x1277, 0, &mmCP_HQD_GDS_RESOURCE_STATE[0], sizeof(mmCP_HQD_GDS_RESOURCE_STATE)/sizeof(mmCP_HQD_GDS_RESOURCE_STATE[0]), 0, 0 }, + { "mmCP_HQD_ERROR", REG_MMIO, 0x1278, 0, &mmCP_HQD_ERROR[0], sizeof(mmCP_HQD_ERROR)/sizeof(mmCP_HQD_ERROR[0]), 0, 0 }, + { "mmCP_HQD_EOP_WPTR_MEM", REG_MMIO, 0x1279, 0, &mmCP_HQD_EOP_WPTR_MEM[0], sizeof(mmCP_HQD_EOP_WPTR_MEM)/sizeof(mmCP_HQD_EOP_WPTR_MEM[0]), 0, 0 }, + { "mmCP_HQD_AQL_CONTROL", REG_MMIO, 0x127a, 0, &mmCP_HQD_AQL_CONTROL[0], sizeof(mmCP_HQD_AQL_CONTROL)/sizeof(mmCP_HQD_AQL_CONTROL[0]), 0, 0 }, + { "mmCP_HQD_PQ_WPTR_LO", REG_MMIO, 0x127b, 0, &mmCP_HQD_PQ_WPTR_LO[0], sizeof(mmCP_HQD_PQ_WPTR_LO)/sizeof(mmCP_HQD_PQ_WPTR_LO[0]), 0, 0 }, + { "mmCP_HQD_PQ_WPTR_HI", REG_MMIO, 0x127c, 0, &mmCP_HQD_PQ_WPTR_HI[0], sizeof(mmCP_HQD_PQ_WPTR_HI)/sizeof(mmCP_HQD_PQ_WPTR_HI[0]), 0, 0 }, + { "mmDIDT_IND_INDEX", REG_MMIO, 0x1280, 0, &mmDIDT_IND_INDEX[0], sizeof(mmDIDT_IND_INDEX)/sizeof(mmDIDT_IND_INDEX[0]), 0, 0 }, + { "mmDIDT_IND_DATA", REG_MMIO, 0x1281, 0, &mmDIDT_IND_DATA[0], sizeof(mmDIDT_IND_DATA)/sizeof(mmDIDT_IND_DATA[0]), 0, 0 }, + { "mmGC_CAC_CTRL_1", REG_MMIO, 0x1284, 0, &mmGC_CAC_CTRL_1[0], sizeof(mmGC_CAC_CTRL_1)/sizeof(mmGC_CAC_CTRL_1[0]), 0, 0 }, + { "mmGC_CAC_CTRL_2", REG_MMIO, 0x1285, 0, &mmGC_CAC_CTRL_2[0], sizeof(mmGC_CAC_CTRL_2)/sizeof(mmGC_CAC_CTRL_2[0]), 0, 0 }, + { "mmGC_CAC_CGTT_CLK_CTRL", REG_MMIO, 0x1286, 0, &mmGC_CAC_CGTT_CLK_CTRL[0], sizeof(mmGC_CAC_CGTT_CLK_CTRL)/sizeof(mmGC_CAC_CGTT_CLK_CTRL[0]), 0, 0 }, + { "mmGC_CAC_AGGR_LOWER", REG_MMIO, 0x1287, 0, &mmGC_CAC_AGGR_LOWER[0], sizeof(mmGC_CAC_AGGR_LOWER)/sizeof(mmGC_CAC_AGGR_LOWER[0]), 0, 0 }, + { "mmGC_CAC_AGGR_UPPER", REG_MMIO, 0x1288, 0, &mmGC_CAC_AGGR_UPPER[0], sizeof(mmGC_CAC_AGGR_UPPER)/sizeof(mmGC_CAC_AGGR_UPPER[0]), 0, 0 }, + { "mmGC_CAC_PG_AGGR_LOWER", REG_MMIO, 0x128b, 0, &mmGC_CAC_PG_AGGR_LOWER[0], sizeof(mmGC_CAC_PG_AGGR_LOWER)/sizeof(mmGC_CAC_PG_AGGR_LOWER[0]), 0, 0 }, + { "mmGC_CAC_PG_AGGR_UPPER", REG_MMIO, 0x128c, 0, &mmGC_CAC_PG_AGGR_UPPER[0], sizeof(mmGC_CAC_PG_AGGR_UPPER)/sizeof(mmGC_CAC_PG_AGGR_UPPER[0]), 0, 0 }, + { "mmGC_CAC_SOFT_CTRL", REG_MMIO, 0x128d, 0, &mmGC_CAC_SOFT_CTRL[0], sizeof(mmGC_CAC_SOFT_CTRL)/sizeof(mmGC_CAC_SOFT_CTRL[0]), 0, 0 }, + { "mmGC_DIDT_CTRL0", REG_MMIO, 0x128e, 0, &mmGC_DIDT_CTRL0[0], sizeof(mmGC_DIDT_CTRL0)/sizeof(mmGC_DIDT_CTRL0[0]), 0, 0 }, + { "mmGC_DIDT_CTRL1", REG_MMIO, 0x128f, 0, &mmGC_DIDT_CTRL1[0], sizeof(mmGC_DIDT_CTRL1)/sizeof(mmGC_DIDT_CTRL1[0]), 0, 0 }, + { "mmGC_DIDT_CTRL2", REG_MMIO, 0x1290, 0, &mmGC_DIDT_CTRL2[0], sizeof(mmGC_DIDT_CTRL2)/sizeof(mmGC_DIDT_CTRL2[0]), 0, 0 }, + { "mmGC_DIDT_WEIGHT", REG_MMIO, 0x1291, 0, &mmGC_DIDT_WEIGHT[0], sizeof(mmGC_DIDT_WEIGHT)/sizeof(mmGC_DIDT_WEIGHT[0]), 0, 0 }, + { "mmGC_EDC_CTRL", REG_MMIO, 0x1293, 0, &mmGC_EDC_CTRL[0], sizeof(mmGC_EDC_CTRL)/sizeof(mmGC_EDC_CTRL[0]), 0, 0 }, + { "mmGC_EDC_THRESHOLD", REG_MMIO, 0x1294, 0, &mmGC_EDC_THRESHOLD[0], sizeof(mmGC_EDC_THRESHOLD)/sizeof(mmGC_EDC_THRESHOLD[0]), 0, 0 }, + { "mmGC_EDC_STATUS", REG_MMIO, 0x1295, 0, &mmGC_EDC_STATUS[0], sizeof(mmGC_EDC_STATUS)/sizeof(mmGC_EDC_STATUS[0]), 0, 0 }, + { "mmGC_EDC_OVERFLOW", REG_MMIO, 0x1296, 0, &mmGC_EDC_OVERFLOW[0], sizeof(mmGC_EDC_OVERFLOW)/sizeof(mmGC_EDC_OVERFLOW[0]), 0, 0 }, + { "mmGC_EDC_ROLLING_POWER_DELTA", REG_MMIO, 0x1297, 0, &mmGC_EDC_ROLLING_POWER_DELTA[0], sizeof(mmGC_EDC_ROLLING_POWER_DELTA)/sizeof(mmGC_EDC_ROLLING_POWER_DELTA[0]), 0, 0 }, + { "mmGC_DIDT_DROOP_CTRL", REG_MMIO, 0x1298, 0, &mmGC_DIDT_DROOP_CTRL[0], sizeof(mmGC_DIDT_DROOP_CTRL)/sizeof(mmGC_DIDT_DROOP_CTRL[0]), 0, 0 }, + { "mmGC_EDC_DROOP_CTRL", REG_MMIO, 0x1299, 0, &mmGC_EDC_DROOP_CTRL[0], sizeof(mmGC_EDC_DROOP_CTRL)/sizeof(mmGC_EDC_DROOP_CTRL[0]), 0, 0 }, + { "mmGC_CAC_IND_INDEX", REG_MMIO, 0x129a, 0, &mmGC_CAC_IND_INDEX[0], sizeof(mmGC_CAC_IND_INDEX)/sizeof(mmGC_CAC_IND_INDEX[0]), 0, 0 }, + { "mmGC_CAC_IND_DATA", REG_MMIO, 0x129b, 0, &mmGC_CAC_IND_DATA[0], sizeof(mmGC_CAC_IND_DATA)/sizeof(mmGC_CAC_IND_DATA[0]), 0, 0 }, + { "mmSE_CAC_CGTT_CLK_CTRL", REG_MMIO, 0x129c, 0, &mmSE_CAC_CGTT_CLK_CTRL[0], sizeof(mmSE_CAC_CGTT_CLK_CTRL)/sizeof(mmSE_CAC_CGTT_CLK_CTRL[0]), 0, 0 }, + { "mmSE_CAC_IND_INDEX", REG_MMIO, 0x129d, 0, &mmSE_CAC_IND_INDEX[0], sizeof(mmSE_CAC_IND_INDEX)/sizeof(mmSE_CAC_IND_INDEX[0]), 0, 0 }, + { "mmSE_CAC_IND_DATA", REG_MMIO, 0x129e, 0, &mmSE_CAC_IND_DATA[0], sizeof(mmSE_CAC_IND_DATA)/sizeof(mmSE_CAC_IND_DATA[0]), 0, 0 }, + { "mmTCP_WATCH0_ADDR_H", REG_MMIO, 0x12a0, 0, &mmTCP_WATCH0_ADDR_H[0], sizeof(mmTCP_WATCH0_ADDR_H)/sizeof(mmTCP_WATCH0_ADDR_H[0]), 0, 0 }, + { "mmTCP_WATCH0_ADDR_L", REG_MMIO, 0x12a1, 0, &mmTCP_WATCH0_ADDR_L[0], sizeof(mmTCP_WATCH0_ADDR_L)/sizeof(mmTCP_WATCH0_ADDR_L[0]), 0, 0 }, + { "mmTCP_WATCH0_CNTL", REG_MMIO, 0x12a2, 0, &mmTCP_WATCH0_CNTL[0], sizeof(mmTCP_WATCH0_CNTL)/sizeof(mmTCP_WATCH0_CNTL[0]), 0, 0 }, + { "mmTCP_WATCH1_ADDR_H", REG_MMIO, 0x12a3, 0, &mmTCP_WATCH1_ADDR_H[0], sizeof(mmTCP_WATCH1_ADDR_H)/sizeof(mmTCP_WATCH1_ADDR_H[0]), 0, 0 }, + { "mmTCP_WATCH1_ADDR_L", REG_MMIO, 0x12a4, 0, &mmTCP_WATCH1_ADDR_L[0], sizeof(mmTCP_WATCH1_ADDR_L)/sizeof(mmTCP_WATCH1_ADDR_L[0]), 0, 0 }, + { "mmTCP_WATCH1_CNTL", REG_MMIO, 0x12a5, 0, &mmTCP_WATCH1_CNTL[0], sizeof(mmTCP_WATCH1_CNTL)/sizeof(mmTCP_WATCH1_CNTL[0]), 0, 0 }, + { "mmTCP_WATCH2_ADDR_H", REG_MMIO, 0x12a6, 0, &mmTCP_WATCH2_ADDR_H[0], sizeof(mmTCP_WATCH2_ADDR_H)/sizeof(mmTCP_WATCH2_ADDR_H[0]), 0, 0 }, + { "mmTCP_WATCH2_ADDR_L", REG_MMIO, 0x12a7, 0, &mmTCP_WATCH2_ADDR_L[0], sizeof(mmTCP_WATCH2_ADDR_L)/sizeof(mmTCP_WATCH2_ADDR_L[0]), 0, 0 }, + { "mmTCP_WATCH2_CNTL", REG_MMIO, 0x12a8, 0, &mmTCP_WATCH2_CNTL[0], sizeof(mmTCP_WATCH2_CNTL)/sizeof(mmTCP_WATCH2_CNTL[0]), 0, 0 }, + { "mmTCP_WATCH3_ADDR_H", REG_MMIO, 0x12a9, 0, &mmTCP_WATCH3_ADDR_H[0], sizeof(mmTCP_WATCH3_ADDR_H)/sizeof(mmTCP_WATCH3_ADDR_H[0]), 0, 0 }, + { "mmTCP_WATCH3_ADDR_L", REG_MMIO, 0x12aa, 0, &mmTCP_WATCH3_ADDR_L[0], sizeof(mmTCP_WATCH3_ADDR_L)/sizeof(mmTCP_WATCH3_ADDR_L[0]), 0, 0 }, + { "mmTCP_WATCH3_CNTL", REG_MMIO, 0x12ab, 0, &mmTCP_WATCH3_CNTL[0], sizeof(mmTCP_WATCH3_CNTL)/sizeof(mmTCP_WATCH3_CNTL[0]), 0, 0 }, + { "mmTCP_GATCL1_CNTL", REG_MMIO, 0x12b0, 0, &mmTCP_GATCL1_CNTL[0], sizeof(mmTCP_GATCL1_CNTL)/sizeof(mmTCP_GATCL1_CNTL[0]), 0, 0 }, + { "mmTCP_ATC_EDC_GATCL1_CNT", REG_MMIO, 0x12b1, 0, &mmTCP_ATC_EDC_GATCL1_CNT[0], sizeof(mmTCP_ATC_EDC_GATCL1_CNT)/sizeof(mmTCP_ATC_EDC_GATCL1_CNT[0]), 0, 0 }, + { "mmTCP_GATCL1_DSM_CNTL", REG_MMIO, 0x12b2, 0, &mmTCP_GATCL1_DSM_CNTL[0], sizeof(mmTCP_GATCL1_DSM_CNTL)/sizeof(mmTCP_GATCL1_DSM_CNTL[0]), 0, 0 }, + { "mmTCP_CNTL2", REG_MMIO, 0x12b4, 0, &mmTCP_CNTL2[0], sizeof(mmTCP_CNTL2)/sizeof(mmTCP_CNTL2[0]), 0, 0 }, + { "mmTCP_UTCL1_CNTL1", REG_MMIO, 0x12b5, 0, &mmTCP_UTCL1_CNTL1[0], sizeof(mmTCP_UTCL1_CNTL1)/sizeof(mmTCP_UTCL1_CNTL1[0]), 0, 0 }, + { "mmTCP_UTCL1_CNTL2", REG_MMIO, 0x12b6, 0, &mmTCP_UTCL1_CNTL2[0], sizeof(mmTCP_UTCL1_CNTL2)/sizeof(mmTCP_UTCL1_CNTL2[0]), 0, 0 }, + { "mmTCP_UTCL1_STATUS", REG_MMIO, 0x12b7, 0, &mmTCP_UTCL1_STATUS[0], sizeof(mmTCP_UTCL1_STATUS)/sizeof(mmTCP_UTCL1_STATUS[0]), 0, 0 }, + { "mmTCP_PERFCOUNTER_FILTER", REG_MMIO, 0x12b9, 0, &mmTCP_PERFCOUNTER_FILTER[0], sizeof(mmTCP_PERFCOUNTER_FILTER)/sizeof(mmTCP_PERFCOUNTER_FILTER[0]), 0, 0 }, + { "mmTCP_PERFCOUNTER_FILTER_EN", REG_MMIO, 0x12ba, 0, &mmTCP_PERFCOUNTER_FILTER_EN[0], sizeof(mmTCP_PERFCOUNTER_FILTER_EN)/sizeof(mmTCP_PERFCOUNTER_FILTER_EN[0]), 0, 0 }, + { "mmGDS_VMID0_BASE", REG_MMIO, 0x1300, 0, &mmGDS_VMID0_BASE[0], sizeof(mmGDS_VMID0_BASE)/sizeof(mmGDS_VMID0_BASE[0]), 0, 0 }, + { "mmGDS_VMID0_SIZE", REG_MMIO, 0x1301, 0, &mmGDS_VMID0_SIZE[0], sizeof(mmGDS_VMID0_SIZE)/sizeof(mmGDS_VMID0_SIZE[0]), 0, 0 }, + { "mmGDS_VMID1_BASE", REG_MMIO, 0x1302, 0, &mmGDS_VMID1_BASE[0], sizeof(mmGDS_VMID1_BASE)/sizeof(mmGDS_VMID1_BASE[0]), 0, 0 }, + { "mmGDS_VMID1_SIZE", REG_MMIO, 0x1303, 0, &mmGDS_VMID1_SIZE[0], sizeof(mmGDS_VMID1_SIZE)/sizeof(mmGDS_VMID1_SIZE[0]), 0, 0 }, + { "mmGDS_VMID2_BASE", REG_MMIO, 0x1304, 0, &mmGDS_VMID2_BASE[0], sizeof(mmGDS_VMID2_BASE)/sizeof(mmGDS_VMID2_BASE[0]), 0, 0 }, + { "mmGDS_VMID2_SIZE", REG_MMIO, 0x1305, 0, &mmGDS_VMID2_SIZE[0], sizeof(mmGDS_VMID2_SIZE)/sizeof(mmGDS_VMID2_SIZE[0]), 0, 0 }, + { "mmGDS_VMID3_BASE", REG_MMIO, 0x1306, 0, &mmGDS_VMID3_BASE[0], sizeof(mmGDS_VMID3_BASE)/sizeof(mmGDS_VMID3_BASE[0]), 0, 0 }, + { "mmGDS_VMID3_SIZE", REG_MMIO, 0x1307, 0, &mmGDS_VMID3_SIZE[0], sizeof(mmGDS_VMID3_SIZE)/sizeof(mmGDS_VMID3_SIZE[0]), 0, 0 }, + { "mmGDS_VMID4_BASE", REG_MMIO, 0x1308, 0, &mmGDS_VMID4_BASE[0], sizeof(mmGDS_VMID4_BASE)/sizeof(mmGDS_VMID4_BASE[0]), 0, 0 }, + { "mmGDS_VMID4_SIZE", REG_MMIO, 0x1309, 0, &mmGDS_VMID4_SIZE[0], sizeof(mmGDS_VMID4_SIZE)/sizeof(mmGDS_VMID4_SIZE[0]), 0, 0 }, + { "mmGDS_VMID5_BASE", REG_MMIO, 0x130a, 0, &mmGDS_VMID5_BASE[0], sizeof(mmGDS_VMID5_BASE)/sizeof(mmGDS_VMID5_BASE[0]), 0, 0 }, + { "mmGDS_VMID5_SIZE", REG_MMIO, 0x130b, 0, &mmGDS_VMID5_SIZE[0], sizeof(mmGDS_VMID5_SIZE)/sizeof(mmGDS_VMID5_SIZE[0]), 0, 0 }, + { "mmGDS_VMID6_BASE", REG_MMIO, 0x130c, 0, &mmGDS_VMID6_BASE[0], sizeof(mmGDS_VMID6_BASE)/sizeof(mmGDS_VMID6_BASE[0]), 0, 0 }, + { "mmGDS_VMID6_SIZE", REG_MMIO, 0x130d, 0, &mmGDS_VMID6_SIZE[0], sizeof(mmGDS_VMID6_SIZE)/sizeof(mmGDS_VMID6_SIZE[0]), 0, 0 }, + { "mmGDS_VMID7_BASE", REG_MMIO, 0x130e, 0, &mmGDS_VMID7_BASE[0], sizeof(mmGDS_VMID7_BASE)/sizeof(mmGDS_VMID7_BASE[0]), 0, 0 }, + { "mmGDS_VMID7_SIZE", REG_MMIO, 0x130f, 0, &mmGDS_VMID7_SIZE[0], sizeof(mmGDS_VMID7_SIZE)/sizeof(mmGDS_VMID7_SIZE[0]), 0, 0 }, + { "mmGDS_VMID8_BASE", REG_MMIO, 0x1310, 0, &mmGDS_VMID8_BASE[0], sizeof(mmGDS_VMID8_BASE)/sizeof(mmGDS_VMID8_BASE[0]), 0, 0 }, + { "mmGDS_VMID8_SIZE", REG_MMIO, 0x1311, 0, &mmGDS_VMID8_SIZE[0], sizeof(mmGDS_VMID8_SIZE)/sizeof(mmGDS_VMID8_SIZE[0]), 0, 0 }, + { "mmGDS_VMID9_BASE", REG_MMIO, 0x1312, 0, &mmGDS_VMID9_BASE[0], sizeof(mmGDS_VMID9_BASE)/sizeof(mmGDS_VMID9_BASE[0]), 0, 0 }, + { "mmGDS_VMID9_SIZE", REG_MMIO, 0x1313, 0, &mmGDS_VMID9_SIZE[0], sizeof(mmGDS_VMID9_SIZE)/sizeof(mmGDS_VMID9_SIZE[0]), 0, 0 }, + { "mmGDS_VMID10_BASE", REG_MMIO, 0x1314, 0, &mmGDS_VMID10_BASE[0], sizeof(mmGDS_VMID10_BASE)/sizeof(mmGDS_VMID10_BASE[0]), 0, 0 }, + { "mmGDS_VMID10_SIZE", REG_MMIO, 0x1315, 0, &mmGDS_VMID10_SIZE[0], sizeof(mmGDS_VMID10_SIZE)/sizeof(mmGDS_VMID10_SIZE[0]), 0, 0 }, + { "mmGDS_VMID11_BASE", REG_MMIO, 0x1316, 0, &mmGDS_VMID11_BASE[0], sizeof(mmGDS_VMID11_BASE)/sizeof(mmGDS_VMID11_BASE[0]), 0, 0 }, + { "mmGDS_VMID11_SIZE", REG_MMIO, 0x1317, 0, &mmGDS_VMID11_SIZE[0], sizeof(mmGDS_VMID11_SIZE)/sizeof(mmGDS_VMID11_SIZE[0]), 0, 0 }, + { "mmGDS_VMID12_BASE", REG_MMIO, 0x1318, 0, &mmGDS_VMID12_BASE[0], sizeof(mmGDS_VMID12_BASE)/sizeof(mmGDS_VMID12_BASE[0]), 0, 0 }, + { "mmGDS_VMID12_SIZE", REG_MMIO, 0x1319, 0, &mmGDS_VMID12_SIZE[0], sizeof(mmGDS_VMID12_SIZE)/sizeof(mmGDS_VMID12_SIZE[0]), 0, 0 }, + { "mmGDS_VMID13_BASE", REG_MMIO, 0x131a, 0, &mmGDS_VMID13_BASE[0], sizeof(mmGDS_VMID13_BASE)/sizeof(mmGDS_VMID13_BASE[0]), 0, 0 }, + { "mmGDS_VMID13_SIZE", REG_MMIO, 0x131b, 0, &mmGDS_VMID13_SIZE[0], sizeof(mmGDS_VMID13_SIZE)/sizeof(mmGDS_VMID13_SIZE[0]), 0, 0 }, + { "mmGDS_VMID14_BASE", REG_MMIO, 0x131c, 0, &mmGDS_VMID14_BASE[0], sizeof(mmGDS_VMID14_BASE)/sizeof(mmGDS_VMID14_BASE[0]), 0, 0 }, + { "mmGDS_VMID14_SIZE", REG_MMIO, 0x131d, 0, &mmGDS_VMID14_SIZE[0], sizeof(mmGDS_VMID14_SIZE)/sizeof(mmGDS_VMID14_SIZE[0]), 0, 0 }, + { "mmGDS_VMID15_BASE", REG_MMIO, 0x131e, 0, &mmGDS_VMID15_BASE[0], sizeof(mmGDS_VMID15_BASE)/sizeof(mmGDS_VMID15_BASE[0]), 0, 0 }, + { "mmGDS_VMID15_SIZE", REG_MMIO, 0x131f, 0, &mmGDS_VMID15_SIZE[0], sizeof(mmGDS_VMID15_SIZE)/sizeof(mmGDS_VMID15_SIZE[0]), 0, 0 }, + { "mmGDS_GWS_VMID0", REG_MMIO, 0x1320, 0, &mmGDS_GWS_VMID0[0], sizeof(mmGDS_GWS_VMID0)/sizeof(mmGDS_GWS_VMID0[0]), 0, 0 }, + { "mmGDS_GWS_VMID1", REG_MMIO, 0x1321, 0, &mmGDS_GWS_VMID1[0], sizeof(mmGDS_GWS_VMID1)/sizeof(mmGDS_GWS_VMID1[0]), 0, 0 }, + { "mmGDS_GWS_VMID2", REG_MMIO, 0x1322, 0, &mmGDS_GWS_VMID2[0], sizeof(mmGDS_GWS_VMID2)/sizeof(mmGDS_GWS_VMID2[0]), 0, 0 }, + { "mmGDS_GWS_VMID3", REG_MMIO, 0x1323, 0, &mmGDS_GWS_VMID3[0], sizeof(mmGDS_GWS_VMID3)/sizeof(mmGDS_GWS_VMID3[0]), 0, 0 }, + { "mmGDS_GWS_VMID4", REG_MMIO, 0x1324, 0, &mmGDS_GWS_VMID4[0], sizeof(mmGDS_GWS_VMID4)/sizeof(mmGDS_GWS_VMID4[0]), 0, 0 }, + { "mmGDS_GWS_VMID5", REG_MMIO, 0x1325, 0, &mmGDS_GWS_VMID5[0], sizeof(mmGDS_GWS_VMID5)/sizeof(mmGDS_GWS_VMID5[0]), 0, 0 }, + { "mmGDS_GWS_VMID6", REG_MMIO, 0x1326, 0, &mmGDS_GWS_VMID6[0], sizeof(mmGDS_GWS_VMID6)/sizeof(mmGDS_GWS_VMID6[0]), 0, 0 }, + { "mmGDS_GWS_VMID7", REG_MMIO, 0x1327, 0, &mmGDS_GWS_VMID7[0], sizeof(mmGDS_GWS_VMID7)/sizeof(mmGDS_GWS_VMID7[0]), 0, 0 }, + { "mmGDS_GWS_VMID8", REG_MMIO, 0x1328, 0, &mmGDS_GWS_VMID8[0], sizeof(mmGDS_GWS_VMID8)/sizeof(mmGDS_GWS_VMID8[0]), 0, 0 }, + { "mmGDS_GWS_VMID9", REG_MMIO, 0x1329, 0, &mmGDS_GWS_VMID9[0], sizeof(mmGDS_GWS_VMID9)/sizeof(mmGDS_GWS_VMID9[0]), 0, 0 }, + { "mmGDS_GWS_VMID10", REG_MMIO, 0x132a, 0, &mmGDS_GWS_VMID10[0], sizeof(mmGDS_GWS_VMID10)/sizeof(mmGDS_GWS_VMID10[0]), 0, 0 }, + { "mmGDS_GWS_VMID11", REG_MMIO, 0x132b, 0, &mmGDS_GWS_VMID11[0], sizeof(mmGDS_GWS_VMID11)/sizeof(mmGDS_GWS_VMID11[0]), 0, 0 }, + { "mmGDS_GWS_VMID12", REG_MMIO, 0x132c, 0, &mmGDS_GWS_VMID12[0], sizeof(mmGDS_GWS_VMID12)/sizeof(mmGDS_GWS_VMID12[0]), 0, 0 }, + { "mmGDS_GWS_VMID13", REG_MMIO, 0x132d, 0, &mmGDS_GWS_VMID13[0], sizeof(mmGDS_GWS_VMID13)/sizeof(mmGDS_GWS_VMID13[0]), 0, 0 }, + { "mmGDS_GWS_VMID14", REG_MMIO, 0x132e, 0, &mmGDS_GWS_VMID14[0], sizeof(mmGDS_GWS_VMID14)/sizeof(mmGDS_GWS_VMID14[0]), 0, 0 }, + { "mmGDS_GWS_VMID15", REG_MMIO, 0x132f, 0, &mmGDS_GWS_VMID15[0], sizeof(mmGDS_GWS_VMID15)/sizeof(mmGDS_GWS_VMID15[0]), 0, 0 }, + { "mmGDS_OA_VMID0", REG_MMIO, 0x1330, 0, &mmGDS_OA_VMID0[0], sizeof(mmGDS_OA_VMID0)/sizeof(mmGDS_OA_VMID0[0]), 0, 0 }, + { "mmGDS_OA_VMID1", REG_MMIO, 0x1331, 0, &mmGDS_OA_VMID1[0], sizeof(mmGDS_OA_VMID1)/sizeof(mmGDS_OA_VMID1[0]), 0, 0 }, + { "mmGDS_OA_VMID2", REG_MMIO, 0x1332, 0, &mmGDS_OA_VMID2[0], sizeof(mmGDS_OA_VMID2)/sizeof(mmGDS_OA_VMID2[0]), 0, 0 }, + { "mmGDS_OA_VMID3", REG_MMIO, 0x1333, 0, &mmGDS_OA_VMID3[0], sizeof(mmGDS_OA_VMID3)/sizeof(mmGDS_OA_VMID3[0]), 0, 0 }, + { "mmGDS_OA_VMID4", REG_MMIO, 0x1334, 0, &mmGDS_OA_VMID4[0], sizeof(mmGDS_OA_VMID4)/sizeof(mmGDS_OA_VMID4[0]), 0, 0 }, + { "mmGDS_OA_VMID5", REG_MMIO, 0x1335, 0, &mmGDS_OA_VMID5[0], sizeof(mmGDS_OA_VMID5)/sizeof(mmGDS_OA_VMID5[0]), 0, 0 }, + { "mmGDS_OA_VMID6", REG_MMIO, 0x1336, 0, &mmGDS_OA_VMID6[0], sizeof(mmGDS_OA_VMID6)/sizeof(mmGDS_OA_VMID6[0]), 0, 0 }, + { "mmGDS_OA_VMID7", REG_MMIO, 0x1337, 0, &mmGDS_OA_VMID7[0], sizeof(mmGDS_OA_VMID7)/sizeof(mmGDS_OA_VMID7[0]), 0, 0 }, + { "mmGDS_OA_VMID8", REG_MMIO, 0x1338, 0, &mmGDS_OA_VMID8[0], sizeof(mmGDS_OA_VMID8)/sizeof(mmGDS_OA_VMID8[0]), 0, 0 }, + { "mmGDS_OA_VMID9", REG_MMIO, 0x1339, 0, &mmGDS_OA_VMID9[0], sizeof(mmGDS_OA_VMID9)/sizeof(mmGDS_OA_VMID9[0]), 0, 0 }, + { "mmGDS_OA_VMID10", REG_MMIO, 0x133a, 0, &mmGDS_OA_VMID10[0], sizeof(mmGDS_OA_VMID10)/sizeof(mmGDS_OA_VMID10[0]), 0, 0 }, + { "mmGDS_OA_VMID11", REG_MMIO, 0x133b, 0, &mmGDS_OA_VMID11[0], sizeof(mmGDS_OA_VMID11)/sizeof(mmGDS_OA_VMID11[0]), 0, 0 }, + { "mmGDS_OA_VMID12", REG_MMIO, 0x133c, 0, &mmGDS_OA_VMID12[0], sizeof(mmGDS_OA_VMID12)/sizeof(mmGDS_OA_VMID12[0]), 0, 0 }, + { "mmGDS_OA_VMID13", REG_MMIO, 0x133d, 0, &mmGDS_OA_VMID13[0], sizeof(mmGDS_OA_VMID13)/sizeof(mmGDS_OA_VMID13[0]), 0, 0 }, + { "mmGDS_OA_VMID14", REG_MMIO, 0x133e, 0, &mmGDS_OA_VMID14[0], sizeof(mmGDS_OA_VMID14)/sizeof(mmGDS_OA_VMID14[0]), 0, 0 }, + { "mmGDS_OA_VMID15", REG_MMIO, 0x133f, 0, &mmGDS_OA_VMID15[0], sizeof(mmGDS_OA_VMID15)/sizeof(mmGDS_OA_VMID15[0]), 0, 0 }, + { "mmGDS_GWS_RESET0", REG_MMIO, 0x1344, 0, &mmGDS_GWS_RESET0[0], sizeof(mmGDS_GWS_RESET0)/sizeof(mmGDS_GWS_RESET0[0]), 0, 0 }, + { "mmGDS_GWS_RESET1", REG_MMIO, 0x1345, 0, &mmGDS_GWS_RESET1[0], sizeof(mmGDS_GWS_RESET1)/sizeof(mmGDS_GWS_RESET1[0]), 0, 0 }, + { "mmGDS_GWS_RESOURCE_RESET", REG_MMIO, 0x1346, 0, &mmGDS_GWS_RESOURCE_RESET[0], sizeof(mmGDS_GWS_RESOURCE_RESET)/sizeof(mmGDS_GWS_RESOURCE_RESET[0]), 0, 0 }, + { "mmGDS_COMPUTE_MAX_WAVE_ID", REG_MMIO, 0x1348, 0, &mmGDS_COMPUTE_MAX_WAVE_ID[0], sizeof(mmGDS_COMPUTE_MAX_WAVE_ID)/sizeof(mmGDS_COMPUTE_MAX_WAVE_ID[0]), 0, 0 }, + { "mmGDS_OA_RESET_MASK", REG_MMIO, 0x1349, 0, &mmGDS_OA_RESET_MASK[0], sizeof(mmGDS_OA_RESET_MASK)/sizeof(mmGDS_OA_RESET_MASK[0]), 0, 0 }, + { "mmGDS_OA_RESET", REG_MMIO, 0x134a, 0, &mmGDS_OA_RESET[0], sizeof(mmGDS_OA_RESET)/sizeof(mmGDS_OA_RESET[0]), 0, 0 }, + { "mmGDS_ENHANCE", REG_MMIO, 0x134b, 0, &mmGDS_ENHANCE[0], sizeof(mmGDS_ENHANCE)/sizeof(mmGDS_ENHANCE[0]), 0, 0 }, + { "mmGDS_OA_CGPG_RESTORE", REG_MMIO, 0x134c, 0, &mmGDS_OA_CGPG_RESTORE[0], sizeof(mmGDS_OA_CGPG_RESTORE)/sizeof(mmGDS_OA_CGPG_RESTORE[0]), 0, 0 }, + { "mmGDS_CS_CTXSW_STATUS", REG_MMIO, 0x134d, 0, &mmGDS_CS_CTXSW_STATUS[0], sizeof(mmGDS_CS_CTXSW_STATUS)/sizeof(mmGDS_CS_CTXSW_STATUS[0]), 0, 0 }, + { "mmGDS_CS_CTXSW_CNT0", REG_MMIO, 0x134e, 0, &mmGDS_CS_CTXSW_CNT0[0], sizeof(mmGDS_CS_CTXSW_CNT0)/sizeof(mmGDS_CS_CTXSW_CNT0[0]), 0, 0 }, + { "mmGDS_CS_CTXSW_CNT1", REG_MMIO, 0x134f, 0, &mmGDS_CS_CTXSW_CNT1[0], sizeof(mmGDS_CS_CTXSW_CNT1)/sizeof(mmGDS_CS_CTXSW_CNT1[0]), 0, 0 }, + { "mmGDS_CS_CTXSW_CNT2", REG_MMIO, 0x1350, 0, &mmGDS_CS_CTXSW_CNT2[0], sizeof(mmGDS_CS_CTXSW_CNT2)/sizeof(mmGDS_CS_CTXSW_CNT2[0]), 0, 0 }, + { "mmGDS_CS_CTXSW_CNT3", REG_MMIO, 0x1351, 0, &mmGDS_CS_CTXSW_CNT3[0], sizeof(mmGDS_CS_CTXSW_CNT3)/sizeof(mmGDS_CS_CTXSW_CNT3[0]), 0, 0 }, + { "mmGDS_GFX_CTXSW_STATUS", REG_MMIO, 0x1352, 0, &mmGDS_GFX_CTXSW_STATUS[0], sizeof(mmGDS_GFX_CTXSW_STATUS)/sizeof(mmGDS_GFX_CTXSW_STATUS[0]), 0, 0 }, + { "mmGDS_VS_CTXSW_CNT0", REG_MMIO, 0x1353, 0, &mmGDS_VS_CTXSW_CNT0[0], sizeof(mmGDS_VS_CTXSW_CNT0)/sizeof(mmGDS_VS_CTXSW_CNT0[0]), 0, 0 }, + { "mmGDS_VS_CTXSW_CNT1", REG_MMIO, 0x1354, 0, &mmGDS_VS_CTXSW_CNT1[0], sizeof(mmGDS_VS_CTXSW_CNT1)/sizeof(mmGDS_VS_CTXSW_CNT1[0]), 0, 0 }, + { "mmGDS_VS_CTXSW_CNT2", REG_MMIO, 0x1355, 0, &mmGDS_VS_CTXSW_CNT2[0], sizeof(mmGDS_VS_CTXSW_CNT2)/sizeof(mmGDS_VS_CTXSW_CNT2[0]), 0, 0 }, + { "mmGDS_VS_CTXSW_CNT3", REG_MMIO, 0x1356, 0, &mmGDS_VS_CTXSW_CNT3[0], sizeof(mmGDS_VS_CTXSW_CNT3)/sizeof(mmGDS_VS_CTXSW_CNT3[0]), 0, 0 }, + { "mmGDS_PS0_CTXSW_CNT0", REG_MMIO, 0x1357, 0, &mmGDS_PS0_CTXSW_CNT0[0], sizeof(mmGDS_PS0_CTXSW_CNT0)/sizeof(mmGDS_PS0_CTXSW_CNT0[0]), 0, 0 }, + { "mmGDS_PS0_CTXSW_CNT1", REG_MMIO, 0x1358, 0, &mmGDS_PS0_CTXSW_CNT1[0], sizeof(mmGDS_PS0_CTXSW_CNT1)/sizeof(mmGDS_PS0_CTXSW_CNT1[0]), 0, 0 }, + { "mmGDS_PS0_CTXSW_CNT2", REG_MMIO, 0x1359, 0, &mmGDS_PS0_CTXSW_CNT2[0], sizeof(mmGDS_PS0_CTXSW_CNT2)/sizeof(mmGDS_PS0_CTXSW_CNT2[0]), 0, 0 }, + { "mmGDS_PS0_CTXSW_CNT3", REG_MMIO, 0x135a, 0, &mmGDS_PS0_CTXSW_CNT3[0], sizeof(mmGDS_PS0_CTXSW_CNT3)/sizeof(mmGDS_PS0_CTXSW_CNT3[0]), 0, 0 }, + { "mmGDS_PS1_CTXSW_CNT0", REG_MMIO, 0x135b, 0, &mmGDS_PS1_CTXSW_CNT0[0], sizeof(mmGDS_PS1_CTXSW_CNT0)/sizeof(mmGDS_PS1_CTXSW_CNT0[0]), 0, 0 }, + { "mmGDS_PS1_CTXSW_CNT1", REG_MMIO, 0x135c, 0, &mmGDS_PS1_CTXSW_CNT1[0], sizeof(mmGDS_PS1_CTXSW_CNT1)/sizeof(mmGDS_PS1_CTXSW_CNT1[0]), 0, 0 }, + { "mmGDS_PS1_CTXSW_CNT2", REG_MMIO, 0x135d, 0, &mmGDS_PS1_CTXSW_CNT2[0], sizeof(mmGDS_PS1_CTXSW_CNT2)/sizeof(mmGDS_PS1_CTXSW_CNT2[0]), 0, 0 }, + { "mmGDS_PS1_CTXSW_CNT3", REG_MMIO, 0x135e, 0, &mmGDS_PS1_CTXSW_CNT3[0], sizeof(mmGDS_PS1_CTXSW_CNT3)/sizeof(mmGDS_PS1_CTXSW_CNT3[0]), 0, 0 }, + { "mmGDS_PS2_CTXSW_CNT0", REG_MMIO, 0x135f, 0, &mmGDS_PS2_CTXSW_CNT0[0], sizeof(mmGDS_PS2_CTXSW_CNT0)/sizeof(mmGDS_PS2_CTXSW_CNT0[0]), 0, 0 }, + { "mmGDS_PS2_CTXSW_CNT1", REG_MMIO, 0x1360, 0, &mmGDS_PS2_CTXSW_CNT1[0], sizeof(mmGDS_PS2_CTXSW_CNT1)/sizeof(mmGDS_PS2_CTXSW_CNT1[0]), 0, 0 }, + { "mmGDS_PS2_CTXSW_CNT2", REG_MMIO, 0x1361, 0, &mmGDS_PS2_CTXSW_CNT2[0], sizeof(mmGDS_PS2_CTXSW_CNT2)/sizeof(mmGDS_PS2_CTXSW_CNT2[0]), 0, 0 }, + { "mmGDS_PS2_CTXSW_CNT3", REG_MMIO, 0x1362, 0, &mmGDS_PS2_CTXSW_CNT3[0], sizeof(mmGDS_PS2_CTXSW_CNT3)/sizeof(mmGDS_PS2_CTXSW_CNT3[0]), 0, 0 }, + { "mmGDS_PS3_CTXSW_CNT0", REG_MMIO, 0x1363, 0, &mmGDS_PS3_CTXSW_CNT0[0], sizeof(mmGDS_PS3_CTXSW_CNT0)/sizeof(mmGDS_PS3_CTXSW_CNT0[0]), 0, 0 }, + { "mmGDS_PS3_CTXSW_CNT1", REG_MMIO, 0x1364, 0, &mmGDS_PS3_CTXSW_CNT1[0], sizeof(mmGDS_PS3_CTXSW_CNT1)/sizeof(mmGDS_PS3_CTXSW_CNT1[0]), 0, 0 }, + { "mmGDS_PS3_CTXSW_CNT2", REG_MMIO, 0x1365, 0, &mmGDS_PS3_CTXSW_CNT2[0], sizeof(mmGDS_PS3_CTXSW_CNT2)/sizeof(mmGDS_PS3_CTXSW_CNT2[0]), 0, 0 }, + { "mmGDS_PS3_CTXSW_CNT3", REG_MMIO, 0x1366, 0, &mmGDS_PS3_CTXSW_CNT3[0], sizeof(mmGDS_PS3_CTXSW_CNT3)/sizeof(mmGDS_PS3_CTXSW_CNT3[0]), 0, 0 }, + { "mmGDS_PS4_CTXSW_CNT0", REG_MMIO, 0x1367, 0, &mmGDS_PS4_CTXSW_CNT0[0], sizeof(mmGDS_PS4_CTXSW_CNT0)/sizeof(mmGDS_PS4_CTXSW_CNT0[0]), 0, 0 }, + { "mmGDS_PS4_CTXSW_CNT1", REG_MMIO, 0x1368, 0, &mmGDS_PS4_CTXSW_CNT1[0], sizeof(mmGDS_PS4_CTXSW_CNT1)/sizeof(mmGDS_PS4_CTXSW_CNT1[0]), 0, 0 }, + { "mmGDS_PS4_CTXSW_CNT2", REG_MMIO, 0x1369, 0, &mmGDS_PS4_CTXSW_CNT2[0], sizeof(mmGDS_PS4_CTXSW_CNT2)/sizeof(mmGDS_PS4_CTXSW_CNT2[0]), 0, 0 }, + { "mmGDS_PS4_CTXSW_CNT3", REG_MMIO, 0x136a, 0, &mmGDS_PS4_CTXSW_CNT3[0], sizeof(mmGDS_PS4_CTXSW_CNT3)/sizeof(mmGDS_PS4_CTXSW_CNT3[0]), 0, 0 }, + { "mmGDS_PS5_CTXSW_CNT0", REG_MMIO, 0x136b, 0, &mmGDS_PS5_CTXSW_CNT0[0], sizeof(mmGDS_PS5_CTXSW_CNT0)/sizeof(mmGDS_PS5_CTXSW_CNT0[0]), 0, 0 }, + { "mmGDS_PS5_CTXSW_CNT1", REG_MMIO, 0x136c, 0, &mmGDS_PS5_CTXSW_CNT1[0], sizeof(mmGDS_PS5_CTXSW_CNT1)/sizeof(mmGDS_PS5_CTXSW_CNT1[0]), 0, 0 }, + { "mmGDS_PS5_CTXSW_CNT2", REG_MMIO, 0x136d, 0, &mmGDS_PS5_CTXSW_CNT2[0], sizeof(mmGDS_PS5_CTXSW_CNT2)/sizeof(mmGDS_PS5_CTXSW_CNT2[0]), 0, 0 }, + { "mmGDS_PS5_CTXSW_CNT3", REG_MMIO, 0x136e, 0, &mmGDS_PS5_CTXSW_CNT3[0], sizeof(mmGDS_PS5_CTXSW_CNT3)/sizeof(mmGDS_PS5_CTXSW_CNT3[0]), 0, 0 }, + { "mmGDS_PS6_CTXSW_CNT0", REG_MMIO, 0x136f, 0, &mmGDS_PS6_CTXSW_CNT0[0], sizeof(mmGDS_PS6_CTXSW_CNT0)/sizeof(mmGDS_PS6_CTXSW_CNT0[0]), 0, 0 }, + { "mmGDS_PS6_CTXSW_CNT1", REG_MMIO, 0x1370, 0, &mmGDS_PS6_CTXSW_CNT1[0], sizeof(mmGDS_PS6_CTXSW_CNT1)/sizeof(mmGDS_PS6_CTXSW_CNT1[0]), 0, 0 }, + { "mmGDS_PS6_CTXSW_CNT2", REG_MMIO, 0x1371, 0, &mmGDS_PS6_CTXSW_CNT2[0], sizeof(mmGDS_PS6_CTXSW_CNT2)/sizeof(mmGDS_PS6_CTXSW_CNT2[0]), 0, 0 }, + { "mmGDS_PS6_CTXSW_CNT3", REG_MMIO, 0x1372, 0, &mmGDS_PS6_CTXSW_CNT3[0], sizeof(mmGDS_PS6_CTXSW_CNT3)/sizeof(mmGDS_PS6_CTXSW_CNT3[0]), 0, 0 }, + { "mmGDS_PS7_CTXSW_CNT0", REG_MMIO, 0x1373, 0, &mmGDS_PS7_CTXSW_CNT0[0], sizeof(mmGDS_PS7_CTXSW_CNT0)/sizeof(mmGDS_PS7_CTXSW_CNT0[0]), 0, 0 }, + { "mmGDS_PS7_CTXSW_CNT1", REG_MMIO, 0x1374, 0, &mmGDS_PS7_CTXSW_CNT1[0], sizeof(mmGDS_PS7_CTXSW_CNT1)/sizeof(mmGDS_PS7_CTXSW_CNT1[0]), 0, 0 }, + { "mmGDS_PS7_CTXSW_CNT2", REG_MMIO, 0x1375, 0, &mmGDS_PS7_CTXSW_CNT2[0], sizeof(mmGDS_PS7_CTXSW_CNT2)/sizeof(mmGDS_PS7_CTXSW_CNT2[0]), 0, 0 }, + { "mmGDS_PS7_CTXSW_CNT3", REG_MMIO, 0x1376, 0, &mmGDS_PS7_CTXSW_CNT3[0], sizeof(mmGDS_PS7_CTXSW_CNT3)/sizeof(mmGDS_PS7_CTXSW_CNT3[0]), 0, 0 }, + { "mmGDS_GS_CTXSW_CNT0", REG_MMIO, 0x1377, 0, &mmGDS_GS_CTXSW_CNT0[0], sizeof(mmGDS_GS_CTXSW_CNT0)/sizeof(mmGDS_GS_CTXSW_CNT0[0]), 0, 0 }, + { "mmGDS_GS_CTXSW_CNT1", REG_MMIO, 0x1378, 0, &mmGDS_GS_CTXSW_CNT1[0], sizeof(mmGDS_GS_CTXSW_CNT1)/sizeof(mmGDS_GS_CTXSW_CNT1[0]), 0, 0 }, + { "mmGDS_GS_CTXSW_CNT2", REG_MMIO, 0x1379, 0, &mmGDS_GS_CTXSW_CNT2[0], sizeof(mmGDS_GS_CTXSW_CNT2)/sizeof(mmGDS_GS_CTXSW_CNT2[0]), 0, 0 }, + { "mmGDS_GS_CTXSW_CNT3", REG_MMIO, 0x137a, 0, &mmGDS_GS_CTXSW_CNT3[0], sizeof(mmGDS_GS_CTXSW_CNT3)/sizeof(mmGDS_GS_CTXSW_CNT3[0]), 0, 0 }, + { "mmRAS_SIGNATURE_CONTROL", REG_MMIO, 0x1380, 0, &mmRAS_SIGNATURE_CONTROL[0], sizeof(mmRAS_SIGNATURE_CONTROL)/sizeof(mmRAS_SIGNATURE_CONTROL[0]), 0, 0 }, + { "mmRAS_SIGNATURE_MASK", REG_MMIO, 0x1381, 0, &mmRAS_SIGNATURE_MASK[0], sizeof(mmRAS_SIGNATURE_MASK)/sizeof(mmRAS_SIGNATURE_MASK[0]), 0, 0 }, + { "mmRAS_SX_SIGNATURE0", REG_MMIO, 0x1382, 0, &mmRAS_SX_SIGNATURE0[0], sizeof(mmRAS_SX_SIGNATURE0)/sizeof(mmRAS_SX_SIGNATURE0[0]), 0, 0 }, + { "mmRAS_SX_SIGNATURE1", REG_MMIO, 0x1383, 0, &mmRAS_SX_SIGNATURE1[0], sizeof(mmRAS_SX_SIGNATURE1)/sizeof(mmRAS_SX_SIGNATURE1[0]), 0, 0 }, + { "mmRAS_SX_SIGNATURE2", REG_MMIO, 0x1384, 0, &mmRAS_SX_SIGNATURE2[0], sizeof(mmRAS_SX_SIGNATURE2)/sizeof(mmRAS_SX_SIGNATURE2[0]), 0, 0 }, + { "mmRAS_SX_SIGNATURE3", REG_MMIO, 0x1385, 0, &mmRAS_SX_SIGNATURE3[0], sizeof(mmRAS_SX_SIGNATURE3)/sizeof(mmRAS_SX_SIGNATURE3[0]), 0, 0 }, + { "mmRAS_DB_SIGNATURE0", REG_MMIO, 0x138b, 0, &mmRAS_DB_SIGNATURE0[0], sizeof(mmRAS_DB_SIGNATURE0)/sizeof(mmRAS_DB_SIGNATURE0[0]), 0, 0 }, + { "mmRAS_PA_SIGNATURE0", REG_MMIO, 0x138c, 0, &mmRAS_PA_SIGNATURE0[0], sizeof(mmRAS_PA_SIGNATURE0)/sizeof(mmRAS_PA_SIGNATURE0[0]), 0, 0 }, + { "mmRAS_VGT_SIGNATURE0", REG_MMIO, 0x138d, 0, &mmRAS_VGT_SIGNATURE0[0], sizeof(mmRAS_VGT_SIGNATURE0)/sizeof(mmRAS_VGT_SIGNATURE0[0]), 0, 0 }, + { "mmRAS_SQ_SIGNATURE0", REG_MMIO, 0x138e, 0, &mmRAS_SQ_SIGNATURE0[0], sizeof(mmRAS_SQ_SIGNATURE0)/sizeof(mmRAS_SQ_SIGNATURE0[0]), 0, 0 }, + { "mmRAS_SC_SIGNATURE0", REG_MMIO, 0x138f, 0, &mmRAS_SC_SIGNATURE0[0], sizeof(mmRAS_SC_SIGNATURE0)/sizeof(mmRAS_SC_SIGNATURE0[0]), 0, 0 }, + { "mmRAS_SC_SIGNATURE1", REG_MMIO, 0x1390, 0, &mmRAS_SC_SIGNATURE1[0], sizeof(mmRAS_SC_SIGNATURE1)/sizeof(mmRAS_SC_SIGNATURE1[0]), 0, 0 }, + { "mmRAS_SC_SIGNATURE2", REG_MMIO, 0x1391, 0, &mmRAS_SC_SIGNATURE2[0], sizeof(mmRAS_SC_SIGNATURE2)/sizeof(mmRAS_SC_SIGNATURE2[0]), 0, 0 }, + { "mmRAS_SC_SIGNATURE3", REG_MMIO, 0x1392, 0, &mmRAS_SC_SIGNATURE3[0], sizeof(mmRAS_SC_SIGNATURE3)/sizeof(mmRAS_SC_SIGNATURE3[0]), 0, 0 }, + { "mmRAS_SC_SIGNATURE4", REG_MMIO, 0x1393, 0, &mmRAS_SC_SIGNATURE4[0], sizeof(mmRAS_SC_SIGNATURE4)/sizeof(mmRAS_SC_SIGNATURE4[0]), 0, 0 }, + { "mmRAS_SC_SIGNATURE5", REG_MMIO, 0x1394, 0, &mmRAS_SC_SIGNATURE5[0], sizeof(mmRAS_SC_SIGNATURE5)/sizeof(mmRAS_SC_SIGNATURE5[0]), 0, 0 }, + { "mmRAS_SC_SIGNATURE6", REG_MMIO, 0x1395, 0, &mmRAS_SC_SIGNATURE6[0], sizeof(mmRAS_SC_SIGNATURE6)/sizeof(mmRAS_SC_SIGNATURE6[0]), 0, 0 }, + { "mmRAS_SC_SIGNATURE7", REG_MMIO, 0x1396, 0, &mmRAS_SC_SIGNATURE7[0], sizeof(mmRAS_SC_SIGNATURE7)/sizeof(mmRAS_SC_SIGNATURE7[0]), 0, 0 }, + { "mmRAS_IA_SIGNATURE0", REG_MMIO, 0x1397, 0, &mmRAS_IA_SIGNATURE0[0], sizeof(mmRAS_IA_SIGNATURE0)/sizeof(mmRAS_IA_SIGNATURE0[0]), 0, 0 }, + { "mmRAS_IA_SIGNATURE1", REG_MMIO, 0x1398, 0, &mmRAS_IA_SIGNATURE1[0], sizeof(mmRAS_IA_SIGNATURE1)/sizeof(mmRAS_IA_SIGNATURE1[0]), 0, 0 }, + { "mmRAS_SPI_SIGNATURE0", REG_MMIO, 0x1399, 0, &mmRAS_SPI_SIGNATURE0[0], sizeof(mmRAS_SPI_SIGNATURE0)/sizeof(mmRAS_SPI_SIGNATURE0[0]), 0, 0 }, + { "mmRAS_SPI_SIGNATURE1", REG_MMIO, 0x139a, 0, &mmRAS_SPI_SIGNATURE1[0], sizeof(mmRAS_SPI_SIGNATURE1)/sizeof(mmRAS_SPI_SIGNATURE1[0]), 0, 0 }, + { "mmRAS_TA_SIGNATURE0", REG_MMIO, 0x139b, 0, &mmRAS_TA_SIGNATURE0[0], sizeof(mmRAS_TA_SIGNATURE0)/sizeof(mmRAS_TA_SIGNATURE0[0]), 0, 0 }, + { "mmRAS_TD_SIGNATURE0", REG_MMIO, 0x139c, 0, &mmRAS_TD_SIGNATURE0[0], sizeof(mmRAS_TD_SIGNATURE0)/sizeof(mmRAS_TD_SIGNATURE0[0]), 0, 0 }, + { "mmRAS_CB_SIGNATURE0", REG_MMIO, 0x139d, 0, &mmRAS_CB_SIGNATURE0[0], sizeof(mmRAS_CB_SIGNATURE0)/sizeof(mmRAS_CB_SIGNATURE0[0]), 0, 0 }, + { "mmRAS_BCI_SIGNATURE0", REG_MMIO, 0x139e, 0, &mmRAS_BCI_SIGNATURE0[0], sizeof(mmRAS_BCI_SIGNATURE0)/sizeof(mmRAS_BCI_SIGNATURE0[0]), 0, 0 }, + { "mmRAS_BCI_SIGNATURE1", REG_MMIO, 0x139f, 0, &mmRAS_BCI_SIGNATURE1[0], sizeof(mmRAS_BCI_SIGNATURE1)/sizeof(mmRAS_BCI_SIGNATURE1[0]), 0, 0 }, + { "mmRAS_TA_SIGNATURE1", REG_MMIO, 0x13a0, 0, &mmRAS_TA_SIGNATURE1[0], sizeof(mmRAS_TA_SIGNATURE1)/sizeof(mmRAS_TA_SIGNATURE1[0]), 0, 0 }, + { "mmDB_RENDER_CONTROL", REG_MMIO, 0x0000, 1, &mmDB_RENDER_CONTROL[0], sizeof(mmDB_RENDER_CONTROL)/sizeof(mmDB_RENDER_CONTROL[0]), 0, 0 }, + { "mmDB_COUNT_CONTROL", REG_MMIO, 0x0001, 1, &mmDB_COUNT_CONTROL[0], sizeof(mmDB_COUNT_CONTROL)/sizeof(mmDB_COUNT_CONTROL[0]), 0, 0 }, + { "mmDB_DEPTH_VIEW", REG_MMIO, 0x0002, 1, &mmDB_DEPTH_VIEW[0], sizeof(mmDB_DEPTH_VIEW)/sizeof(mmDB_DEPTH_VIEW[0]), 0, 0 }, + { "mmDB_RENDER_OVERRIDE", REG_MMIO, 0x0003, 1, &mmDB_RENDER_OVERRIDE[0], sizeof(mmDB_RENDER_OVERRIDE)/sizeof(mmDB_RENDER_OVERRIDE[0]), 0, 0 }, + { "mmDB_RENDER_OVERRIDE2", REG_MMIO, 0x0004, 1, &mmDB_RENDER_OVERRIDE2[0], sizeof(mmDB_RENDER_OVERRIDE2)/sizeof(mmDB_RENDER_OVERRIDE2[0]), 0, 0 }, + { "mmDB_HTILE_DATA_BASE", REG_MMIO, 0x0005, 1, &mmDB_HTILE_DATA_BASE[0], sizeof(mmDB_HTILE_DATA_BASE)/sizeof(mmDB_HTILE_DATA_BASE[0]), 0, 0 }, + { "mmDB_HTILE_DATA_BASE_HI", REG_MMIO, 0x0006, 1, &mmDB_HTILE_DATA_BASE_HI[0], sizeof(mmDB_HTILE_DATA_BASE_HI)/sizeof(mmDB_HTILE_DATA_BASE_HI[0]), 0, 0 }, + { "mmDB_DEPTH_SIZE", REG_MMIO, 0x0007, 1, &mmDB_DEPTH_SIZE[0], sizeof(mmDB_DEPTH_SIZE)/sizeof(mmDB_DEPTH_SIZE[0]), 0, 0 }, + { "mmDB_DEPTH_BOUNDS_MIN", REG_MMIO, 0x0008, 1, &mmDB_DEPTH_BOUNDS_MIN[0], sizeof(mmDB_DEPTH_BOUNDS_MIN)/sizeof(mmDB_DEPTH_BOUNDS_MIN[0]), 0, 0 }, + { "mmDB_DEPTH_BOUNDS_MAX", REG_MMIO, 0x0009, 1, &mmDB_DEPTH_BOUNDS_MAX[0], sizeof(mmDB_DEPTH_BOUNDS_MAX)/sizeof(mmDB_DEPTH_BOUNDS_MAX[0]), 0, 0 }, + { "mmDB_STENCIL_CLEAR", REG_MMIO, 0x000a, 1, &mmDB_STENCIL_CLEAR[0], sizeof(mmDB_STENCIL_CLEAR)/sizeof(mmDB_STENCIL_CLEAR[0]), 0, 0 }, + { "mmDB_DEPTH_CLEAR", REG_MMIO, 0x000b, 1, &mmDB_DEPTH_CLEAR[0], sizeof(mmDB_DEPTH_CLEAR)/sizeof(mmDB_DEPTH_CLEAR[0]), 0, 0 }, + { "mmPA_SC_SCREEN_SCISSOR_TL", REG_MMIO, 0x000c, 1, &mmPA_SC_SCREEN_SCISSOR_TL[0], sizeof(mmPA_SC_SCREEN_SCISSOR_TL)/sizeof(mmPA_SC_SCREEN_SCISSOR_TL[0]), 0, 0 }, + { "mmPA_SC_SCREEN_SCISSOR_BR", REG_MMIO, 0x000d, 1, &mmPA_SC_SCREEN_SCISSOR_BR[0], sizeof(mmPA_SC_SCREEN_SCISSOR_BR)/sizeof(mmPA_SC_SCREEN_SCISSOR_BR[0]), 0, 0 }, + { "mmDB_Z_INFO", REG_MMIO, 0x000e, 1, &mmDB_Z_INFO[0], sizeof(mmDB_Z_INFO)/sizeof(mmDB_Z_INFO[0]), 0, 0 }, + { "mmDB_STENCIL_INFO", REG_MMIO, 0x000f, 1, &mmDB_STENCIL_INFO[0], sizeof(mmDB_STENCIL_INFO)/sizeof(mmDB_STENCIL_INFO[0]), 0, 0 }, + { "mmDB_Z_READ_BASE", REG_MMIO, 0x0010, 1, &mmDB_Z_READ_BASE[0], sizeof(mmDB_Z_READ_BASE)/sizeof(mmDB_Z_READ_BASE[0]), 0, 0 }, + { "mmDB_Z_READ_BASE_HI", REG_MMIO, 0x0011, 1, &mmDB_Z_READ_BASE_HI[0], sizeof(mmDB_Z_READ_BASE_HI)/sizeof(mmDB_Z_READ_BASE_HI[0]), 0, 0 }, + { "mmDB_STENCIL_READ_BASE", REG_MMIO, 0x0012, 1, &mmDB_STENCIL_READ_BASE[0], sizeof(mmDB_STENCIL_READ_BASE)/sizeof(mmDB_STENCIL_READ_BASE[0]), 0, 0 }, + { "mmDB_STENCIL_READ_BASE_HI", REG_MMIO, 0x0013, 1, &mmDB_STENCIL_READ_BASE_HI[0], sizeof(mmDB_STENCIL_READ_BASE_HI)/sizeof(mmDB_STENCIL_READ_BASE_HI[0]), 0, 0 }, + { "mmDB_Z_WRITE_BASE", REG_MMIO, 0x0014, 1, &mmDB_Z_WRITE_BASE[0], sizeof(mmDB_Z_WRITE_BASE)/sizeof(mmDB_Z_WRITE_BASE[0]), 0, 0 }, + { "mmDB_Z_WRITE_BASE_HI", REG_MMIO, 0x0015, 1, &mmDB_Z_WRITE_BASE_HI[0], sizeof(mmDB_Z_WRITE_BASE_HI)/sizeof(mmDB_Z_WRITE_BASE_HI[0]), 0, 0 }, + { "mmDB_STENCIL_WRITE_BASE", REG_MMIO, 0x0016, 1, &mmDB_STENCIL_WRITE_BASE[0], sizeof(mmDB_STENCIL_WRITE_BASE)/sizeof(mmDB_STENCIL_WRITE_BASE[0]), 0, 0 }, + { "mmDB_STENCIL_WRITE_BASE_HI", REG_MMIO, 0x0017, 1, &mmDB_STENCIL_WRITE_BASE_HI[0], sizeof(mmDB_STENCIL_WRITE_BASE_HI)/sizeof(mmDB_STENCIL_WRITE_BASE_HI[0]), 0, 0 }, + { "mmDB_DFSM_CONTROL", REG_MMIO, 0x0018, 1, &mmDB_DFSM_CONTROL[0], sizeof(mmDB_DFSM_CONTROL)/sizeof(mmDB_DFSM_CONTROL[0]), 0, 0 }, + { "mmDB_RENDER_FILTER", REG_MMIO, 0x0019, 1, &mmDB_RENDER_FILTER[0], sizeof(mmDB_RENDER_FILTER)/sizeof(mmDB_RENDER_FILTER[0]), 0, 0 }, + { "mmDB_Z_INFO2", REG_MMIO, 0x001a, 1, &mmDB_Z_INFO2[0], sizeof(mmDB_Z_INFO2)/sizeof(mmDB_Z_INFO2[0]), 0, 0 }, + { "mmDB_STENCIL_INFO2", REG_MMIO, 0x001b, 1, &mmDB_STENCIL_INFO2[0], sizeof(mmDB_STENCIL_INFO2)/sizeof(mmDB_STENCIL_INFO2[0]), 0, 0 }, + { "mmTA_BC_BASE_ADDR", REG_MMIO, 0x0020, 1, &mmTA_BC_BASE_ADDR[0], sizeof(mmTA_BC_BASE_ADDR)/sizeof(mmTA_BC_BASE_ADDR[0]), 0, 0 }, + { "mmTA_BC_BASE_ADDR_HI", REG_MMIO, 0x0021, 1, &mmTA_BC_BASE_ADDR_HI[0], sizeof(mmTA_BC_BASE_ADDR_HI)/sizeof(mmTA_BC_BASE_ADDR_HI[0]), 0, 0 }, + { "mmCOHER_DEST_BASE_HI_0", REG_MMIO, 0x007a, 1, &mmCOHER_DEST_BASE_HI_0[0], sizeof(mmCOHER_DEST_BASE_HI_0)/sizeof(mmCOHER_DEST_BASE_HI_0[0]), 0, 0 }, + { "mmCOHER_DEST_BASE_HI_1", REG_MMIO, 0x007b, 1, &mmCOHER_DEST_BASE_HI_1[0], sizeof(mmCOHER_DEST_BASE_HI_1)/sizeof(mmCOHER_DEST_BASE_HI_1[0]), 0, 0 }, + { "mmCOHER_DEST_BASE_HI_2", REG_MMIO, 0x007c, 1, &mmCOHER_DEST_BASE_HI_2[0], sizeof(mmCOHER_DEST_BASE_HI_2)/sizeof(mmCOHER_DEST_BASE_HI_2[0]), 0, 0 }, + { "mmCOHER_DEST_BASE_HI_3", REG_MMIO, 0x007d, 1, &mmCOHER_DEST_BASE_HI_3[0], sizeof(mmCOHER_DEST_BASE_HI_3)/sizeof(mmCOHER_DEST_BASE_HI_3[0]), 0, 0 }, + { "mmCOHER_DEST_BASE_2", REG_MMIO, 0x007e, 1, &mmCOHER_DEST_BASE_2[0], sizeof(mmCOHER_DEST_BASE_2)/sizeof(mmCOHER_DEST_BASE_2[0]), 0, 0 }, + { "mmCOHER_DEST_BASE_3", REG_MMIO, 0x007f, 1, &mmCOHER_DEST_BASE_3[0], sizeof(mmCOHER_DEST_BASE_3)/sizeof(mmCOHER_DEST_BASE_3[0]), 0, 0 }, + { "mmPA_SC_WINDOW_OFFSET", REG_MMIO, 0x0080, 1, &mmPA_SC_WINDOW_OFFSET[0], sizeof(mmPA_SC_WINDOW_OFFSET)/sizeof(mmPA_SC_WINDOW_OFFSET[0]), 0, 0 }, + { "mmPA_SC_WINDOW_SCISSOR_TL", REG_MMIO, 0x0081, 1, &mmPA_SC_WINDOW_SCISSOR_TL[0], sizeof(mmPA_SC_WINDOW_SCISSOR_TL)/sizeof(mmPA_SC_WINDOW_SCISSOR_TL[0]), 0, 0 }, + { "mmPA_SC_WINDOW_SCISSOR_BR", REG_MMIO, 0x0082, 1, &mmPA_SC_WINDOW_SCISSOR_BR[0], sizeof(mmPA_SC_WINDOW_SCISSOR_BR)/sizeof(mmPA_SC_WINDOW_SCISSOR_BR[0]), 0, 0 }, + { "mmPA_SC_CLIPRECT_RULE", REG_MMIO, 0x0083, 1, &mmPA_SC_CLIPRECT_RULE[0], sizeof(mmPA_SC_CLIPRECT_RULE)/sizeof(mmPA_SC_CLIPRECT_RULE[0]), 0, 0 }, + { "mmPA_SC_CLIPRECT_0_TL", REG_MMIO, 0x0084, 1, &mmPA_SC_CLIPRECT_0_TL[0], sizeof(mmPA_SC_CLIPRECT_0_TL)/sizeof(mmPA_SC_CLIPRECT_0_TL[0]), 0, 0 }, + { "mmPA_SC_CLIPRECT_0_BR", REG_MMIO, 0x0085, 1, &mmPA_SC_CLIPRECT_0_BR[0], sizeof(mmPA_SC_CLIPRECT_0_BR)/sizeof(mmPA_SC_CLIPRECT_0_BR[0]), 0, 0 }, + { "mmPA_SC_CLIPRECT_1_TL", REG_MMIO, 0x0086, 1, &mmPA_SC_CLIPRECT_1_TL[0], sizeof(mmPA_SC_CLIPRECT_1_TL)/sizeof(mmPA_SC_CLIPRECT_1_TL[0]), 0, 0 }, + { "mmPA_SC_CLIPRECT_1_BR", REG_MMIO, 0x0087, 1, &mmPA_SC_CLIPRECT_1_BR[0], sizeof(mmPA_SC_CLIPRECT_1_BR)/sizeof(mmPA_SC_CLIPRECT_1_BR[0]), 0, 0 }, + { "mmPA_SC_CLIPRECT_2_TL", REG_MMIO, 0x0088, 1, &mmPA_SC_CLIPRECT_2_TL[0], sizeof(mmPA_SC_CLIPRECT_2_TL)/sizeof(mmPA_SC_CLIPRECT_2_TL[0]), 0, 0 }, + { "mmPA_SC_CLIPRECT_2_BR", REG_MMIO, 0x0089, 1, &mmPA_SC_CLIPRECT_2_BR[0], sizeof(mmPA_SC_CLIPRECT_2_BR)/sizeof(mmPA_SC_CLIPRECT_2_BR[0]), 0, 0 }, + { "mmPA_SC_CLIPRECT_3_TL", REG_MMIO, 0x008a, 1, &mmPA_SC_CLIPRECT_3_TL[0], sizeof(mmPA_SC_CLIPRECT_3_TL)/sizeof(mmPA_SC_CLIPRECT_3_TL[0]), 0, 0 }, + { "mmPA_SC_CLIPRECT_3_BR", REG_MMIO, 0x008b, 1, &mmPA_SC_CLIPRECT_3_BR[0], sizeof(mmPA_SC_CLIPRECT_3_BR)/sizeof(mmPA_SC_CLIPRECT_3_BR[0]), 0, 0 }, + { "mmPA_SC_EDGERULE", REG_MMIO, 0x008c, 1, &mmPA_SC_EDGERULE[0], sizeof(mmPA_SC_EDGERULE)/sizeof(mmPA_SC_EDGERULE[0]), 0, 0 }, + { "mmPA_SU_HARDWARE_SCREEN_OFFSET", REG_MMIO, 0x008d, 1, &mmPA_SU_HARDWARE_SCREEN_OFFSET[0], sizeof(mmPA_SU_HARDWARE_SCREEN_OFFSET)/sizeof(mmPA_SU_HARDWARE_SCREEN_OFFSET[0]), 0, 0 }, + { "mmCB_TARGET_MASK", REG_MMIO, 0x008e, 1, &mmCB_TARGET_MASK[0], sizeof(mmCB_TARGET_MASK)/sizeof(mmCB_TARGET_MASK[0]), 0, 0 }, + { "mmCB_SHADER_MASK", REG_MMIO, 0x008f, 1, &mmCB_SHADER_MASK[0], sizeof(mmCB_SHADER_MASK)/sizeof(mmCB_SHADER_MASK[0]), 0, 0 }, + { "mmPA_SC_GENERIC_SCISSOR_TL", REG_MMIO, 0x0090, 1, &mmPA_SC_GENERIC_SCISSOR_TL[0], sizeof(mmPA_SC_GENERIC_SCISSOR_TL)/sizeof(mmPA_SC_GENERIC_SCISSOR_TL[0]), 0, 0 }, + { "mmPA_SC_GENERIC_SCISSOR_BR", REG_MMIO, 0x0091, 1, &mmPA_SC_GENERIC_SCISSOR_BR[0], sizeof(mmPA_SC_GENERIC_SCISSOR_BR)/sizeof(mmPA_SC_GENERIC_SCISSOR_BR[0]), 0, 0 }, + { "mmCOHER_DEST_BASE_0", REG_MMIO, 0x0092, 1, &mmCOHER_DEST_BASE_0[0], sizeof(mmCOHER_DEST_BASE_0)/sizeof(mmCOHER_DEST_BASE_0[0]), 0, 0 }, + { "mmCOHER_DEST_BASE_1", REG_MMIO, 0x0093, 1, &mmCOHER_DEST_BASE_1[0], sizeof(mmCOHER_DEST_BASE_1)/sizeof(mmCOHER_DEST_BASE_1[0]), 0, 0 }, + { "mmPA_SC_VPORT_SCISSOR_0_TL", REG_MMIO, 0x0094, 1, &mmPA_SC_VPORT_SCISSOR_0_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_0_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_0_TL[0]), 0, 0 }, + { "mmPA_SC_VPORT_SCISSOR_0_BR", REG_MMIO, 0x0095, 1, &mmPA_SC_VPORT_SCISSOR_0_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_0_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_0_BR[0]), 0, 0 }, + { "mmPA_SC_VPORT_SCISSOR_1_TL", REG_MMIO, 0x0096, 1, &mmPA_SC_VPORT_SCISSOR_1_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_1_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_1_TL[0]), 0, 0 }, + { "mmPA_SC_VPORT_SCISSOR_1_BR", REG_MMIO, 0x0097, 1, &mmPA_SC_VPORT_SCISSOR_1_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_1_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_1_BR[0]), 0, 0 }, + { "mmPA_SC_VPORT_SCISSOR_2_TL", REG_MMIO, 0x0098, 1, &mmPA_SC_VPORT_SCISSOR_2_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_2_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_2_TL[0]), 0, 0 }, + { "mmPA_SC_VPORT_SCISSOR_2_BR", REG_MMIO, 0x0099, 1, &mmPA_SC_VPORT_SCISSOR_2_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_2_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_2_BR[0]), 0, 0 }, + { "mmPA_SC_VPORT_SCISSOR_3_TL", REG_MMIO, 0x009a, 1, &mmPA_SC_VPORT_SCISSOR_3_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_3_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_3_TL[0]), 0, 0 }, + { "mmPA_SC_VPORT_SCISSOR_3_BR", REG_MMIO, 0x009b, 1, &mmPA_SC_VPORT_SCISSOR_3_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_3_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_3_BR[0]), 0, 0 }, + { "mmPA_SC_VPORT_SCISSOR_4_TL", REG_MMIO, 0x009c, 1, &mmPA_SC_VPORT_SCISSOR_4_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_4_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_4_TL[0]), 0, 0 }, + { "mmPA_SC_VPORT_SCISSOR_4_BR", REG_MMIO, 0x009d, 1, &mmPA_SC_VPORT_SCISSOR_4_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_4_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_4_BR[0]), 0, 0 }, + { "mmPA_SC_VPORT_SCISSOR_5_TL", REG_MMIO, 0x009e, 1, &mmPA_SC_VPORT_SCISSOR_5_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_5_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_5_TL[0]), 0, 0 }, + { "mmPA_SC_VPORT_SCISSOR_5_BR", REG_MMIO, 0x009f, 1, &mmPA_SC_VPORT_SCISSOR_5_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_5_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_5_BR[0]), 0, 0 }, + { "mmPA_SC_VPORT_SCISSOR_6_TL", REG_MMIO, 0x00a0, 1, &mmPA_SC_VPORT_SCISSOR_6_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_6_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_6_TL[0]), 0, 0 }, + { "mmPA_SC_VPORT_SCISSOR_6_BR", REG_MMIO, 0x00a1, 1, &mmPA_SC_VPORT_SCISSOR_6_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_6_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_6_BR[0]), 0, 0 }, + { "mmPA_SC_VPORT_SCISSOR_7_TL", REG_MMIO, 0x00a2, 1, &mmPA_SC_VPORT_SCISSOR_7_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_7_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_7_TL[0]), 0, 0 }, + { "mmPA_SC_VPORT_SCISSOR_7_BR", REG_MMIO, 0x00a3, 1, &mmPA_SC_VPORT_SCISSOR_7_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_7_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_7_BR[0]), 0, 0 }, + { "mmPA_SC_VPORT_SCISSOR_8_TL", REG_MMIO, 0x00a4, 1, &mmPA_SC_VPORT_SCISSOR_8_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_8_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_8_TL[0]), 0, 0 }, + { "mmPA_SC_VPORT_SCISSOR_8_BR", REG_MMIO, 0x00a5, 1, &mmPA_SC_VPORT_SCISSOR_8_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_8_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_8_BR[0]), 0, 0 }, + { "mmPA_SC_VPORT_SCISSOR_9_TL", REG_MMIO, 0x00a6, 1, &mmPA_SC_VPORT_SCISSOR_9_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_9_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_9_TL[0]), 0, 0 }, + { "mmPA_SC_VPORT_SCISSOR_9_BR", REG_MMIO, 0x00a7, 1, &mmPA_SC_VPORT_SCISSOR_9_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_9_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_9_BR[0]), 0, 0 }, + { "mmPA_SC_VPORT_SCISSOR_10_TL", REG_MMIO, 0x00a8, 1, &mmPA_SC_VPORT_SCISSOR_10_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_10_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_10_TL[0]), 0, 0 }, + { "mmPA_SC_VPORT_SCISSOR_10_BR", REG_MMIO, 0x00a9, 1, &mmPA_SC_VPORT_SCISSOR_10_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_10_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_10_BR[0]), 0, 0 }, + { "mmPA_SC_VPORT_SCISSOR_11_TL", REG_MMIO, 0x00aa, 1, &mmPA_SC_VPORT_SCISSOR_11_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_11_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_11_TL[0]), 0, 0 }, + { "mmPA_SC_VPORT_SCISSOR_11_BR", REG_MMIO, 0x00ab, 1, &mmPA_SC_VPORT_SCISSOR_11_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_11_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_11_BR[0]), 0, 0 }, + { "mmPA_SC_VPORT_SCISSOR_12_TL", REG_MMIO, 0x00ac, 1, &mmPA_SC_VPORT_SCISSOR_12_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_12_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_12_TL[0]), 0, 0 }, + { "mmPA_SC_VPORT_SCISSOR_12_BR", REG_MMIO, 0x00ad, 1, &mmPA_SC_VPORT_SCISSOR_12_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_12_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_12_BR[0]), 0, 0 }, + { "mmPA_SC_VPORT_SCISSOR_13_TL", REG_MMIO, 0x00ae, 1, &mmPA_SC_VPORT_SCISSOR_13_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_13_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_13_TL[0]), 0, 0 }, + { "mmPA_SC_VPORT_SCISSOR_13_BR", REG_MMIO, 0x00af, 1, &mmPA_SC_VPORT_SCISSOR_13_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_13_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_13_BR[0]), 0, 0 }, + { "mmPA_SC_VPORT_SCISSOR_14_TL", REG_MMIO, 0x00b0, 1, &mmPA_SC_VPORT_SCISSOR_14_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_14_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_14_TL[0]), 0, 0 }, + { "mmPA_SC_VPORT_SCISSOR_14_BR", REG_MMIO, 0x00b1, 1, &mmPA_SC_VPORT_SCISSOR_14_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_14_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_14_BR[0]), 0, 0 }, + { "mmPA_SC_VPORT_SCISSOR_15_TL", REG_MMIO, 0x00b2, 1, &mmPA_SC_VPORT_SCISSOR_15_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_15_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_15_TL[0]), 0, 0 }, + { "mmPA_SC_VPORT_SCISSOR_15_BR", REG_MMIO, 0x00b3, 1, &mmPA_SC_VPORT_SCISSOR_15_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_15_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_15_BR[0]), 0, 0 }, + { "mmPA_SC_VPORT_ZMIN_0", REG_MMIO, 0x00b4, 1, &mmPA_SC_VPORT_ZMIN_0[0], sizeof(mmPA_SC_VPORT_ZMIN_0)/sizeof(mmPA_SC_VPORT_ZMIN_0[0]), 0, 0 }, + { "mmPA_SC_VPORT_ZMAX_0", REG_MMIO, 0x00b5, 1, &mmPA_SC_VPORT_ZMAX_0[0], sizeof(mmPA_SC_VPORT_ZMAX_0)/sizeof(mmPA_SC_VPORT_ZMAX_0[0]), 0, 0 }, + { "mmPA_SC_VPORT_ZMIN_1", REG_MMIO, 0x00b6, 1, &mmPA_SC_VPORT_ZMIN_1[0], sizeof(mmPA_SC_VPORT_ZMIN_1)/sizeof(mmPA_SC_VPORT_ZMIN_1[0]), 0, 0 }, + { "mmPA_SC_VPORT_ZMAX_1", REG_MMIO, 0x00b7, 1, &mmPA_SC_VPORT_ZMAX_1[0], sizeof(mmPA_SC_VPORT_ZMAX_1)/sizeof(mmPA_SC_VPORT_ZMAX_1[0]), 0, 0 }, + { "mmPA_SC_VPORT_ZMIN_2", REG_MMIO, 0x00b8, 1, &mmPA_SC_VPORT_ZMIN_2[0], sizeof(mmPA_SC_VPORT_ZMIN_2)/sizeof(mmPA_SC_VPORT_ZMIN_2[0]), 0, 0 }, + { "mmPA_SC_VPORT_ZMAX_2", REG_MMIO, 0x00b9, 1, &mmPA_SC_VPORT_ZMAX_2[0], sizeof(mmPA_SC_VPORT_ZMAX_2)/sizeof(mmPA_SC_VPORT_ZMAX_2[0]), 0, 0 }, + { "mmPA_SC_VPORT_ZMIN_3", REG_MMIO, 0x00ba, 1, &mmPA_SC_VPORT_ZMIN_3[0], sizeof(mmPA_SC_VPORT_ZMIN_3)/sizeof(mmPA_SC_VPORT_ZMIN_3[0]), 0, 0 }, + { "mmPA_SC_VPORT_ZMAX_3", REG_MMIO, 0x00bb, 1, &mmPA_SC_VPORT_ZMAX_3[0], sizeof(mmPA_SC_VPORT_ZMAX_3)/sizeof(mmPA_SC_VPORT_ZMAX_3[0]), 0, 0 }, + { "mmPA_SC_VPORT_ZMIN_4", REG_MMIO, 0x00bc, 1, &mmPA_SC_VPORT_ZMIN_4[0], sizeof(mmPA_SC_VPORT_ZMIN_4)/sizeof(mmPA_SC_VPORT_ZMIN_4[0]), 0, 0 }, + { "mmPA_SC_VPORT_ZMAX_4", REG_MMIO, 0x00bd, 1, &mmPA_SC_VPORT_ZMAX_4[0], sizeof(mmPA_SC_VPORT_ZMAX_4)/sizeof(mmPA_SC_VPORT_ZMAX_4[0]), 0, 0 }, + { "mmPA_SC_VPORT_ZMIN_5", REG_MMIO, 0x00be, 1, &mmPA_SC_VPORT_ZMIN_5[0], sizeof(mmPA_SC_VPORT_ZMIN_5)/sizeof(mmPA_SC_VPORT_ZMIN_5[0]), 0, 0 }, + { "mmPA_SC_VPORT_ZMAX_5", REG_MMIO, 0x00bf, 1, &mmPA_SC_VPORT_ZMAX_5[0], sizeof(mmPA_SC_VPORT_ZMAX_5)/sizeof(mmPA_SC_VPORT_ZMAX_5[0]), 0, 0 }, + { "mmPA_SC_VPORT_ZMIN_6", REG_MMIO, 0x00c0, 1, &mmPA_SC_VPORT_ZMIN_6[0], sizeof(mmPA_SC_VPORT_ZMIN_6)/sizeof(mmPA_SC_VPORT_ZMIN_6[0]), 0, 0 }, + { "mmPA_SC_VPORT_ZMAX_6", REG_MMIO, 0x00c1, 1, &mmPA_SC_VPORT_ZMAX_6[0], sizeof(mmPA_SC_VPORT_ZMAX_6)/sizeof(mmPA_SC_VPORT_ZMAX_6[0]), 0, 0 }, + { "mmPA_SC_VPORT_ZMIN_7", REG_MMIO, 0x00c2, 1, &mmPA_SC_VPORT_ZMIN_7[0], sizeof(mmPA_SC_VPORT_ZMIN_7)/sizeof(mmPA_SC_VPORT_ZMIN_7[0]), 0, 0 }, + { "mmPA_SC_VPORT_ZMAX_7", REG_MMIO, 0x00c3, 1, &mmPA_SC_VPORT_ZMAX_7[0], sizeof(mmPA_SC_VPORT_ZMAX_7)/sizeof(mmPA_SC_VPORT_ZMAX_7[0]), 0, 0 }, + { "mmPA_SC_VPORT_ZMIN_8", REG_MMIO, 0x00c4, 1, &mmPA_SC_VPORT_ZMIN_8[0], sizeof(mmPA_SC_VPORT_ZMIN_8)/sizeof(mmPA_SC_VPORT_ZMIN_8[0]), 0, 0 }, + { "mmPA_SC_VPORT_ZMAX_8", REG_MMIO, 0x00c5, 1, &mmPA_SC_VPORT_ZMAX_8[0], sizeof(mmPA_SC_VPORT_ZMAX_8)/sizeof(mmPA_SC_VPORT_ZMAX_8[0]), 0, 0 }, + { "mmPA_SC_VPORT_ZMIN_9", REG_MMIO, 0x00c6, 1, &mmPA_SC_VPORT_ZMIN_9[0], sizeof(mmPA_SC_VPORT_ZMIN_9)/sizeof(mmPA_SC_VPORT_ZMIN_9[0]), 0, 0 }, + { "mmPA_SC_VPORT_ZMAX_9", REG_MMIO, 0x00c7, 1, &mmPA_SC_VPORT_ZMAX_9[0], sizeof(mmPA_SC_VPORT_ZMAX_9)/sizeof(mmPA_SC_VPORT_ZMAX_9[0]), 0, 0 }, + { "mmPA_SC_VPORT_ZMIN_10", REG_MMIO, 0x00c8, 1, &mmPA_SC_VPORT_ZMIN_10[0], sizeof(mmPA_SC_VPORT_ZMIN_10)/sizeof(mmPA_SC_VPORT_ZMIN_10[0]), 0, 0 }, + { "mmPA_SC_VPORT_ZMAX_10", REG_MMIO, 0x00c9, 1, &mmPA_SC_VPORT_ZMAX_10[0], sizeof(mmPA_SC_VPORT_ZMAX_10)/sizeof(mmPA_SC_VPORT_ZMAX_10[0]), 0, 0 }, + { "mmPA_SC_VPORT_ZMIN_11", REG_MMIO, 0x00ca, 1, &mmPA_SC_VPORT_ZMIN_11[0], sizeof(mmPA_SC_VPORT_ZMIN_11)/sizeof(mmPA_SC_VPORT_ZMIN_11[0]), 0, 0 }, + { "mmPA_SC_VPORT_ZMAX_11", REG_MMIO, 0x00cb, 1, &mmPA_SC_VPORT_ZMAX_11[0], sizeof(mmPA_SC_VPORT_ZMAX_11)/sizeof(mmPA_SC_VPORT_ZMAX_11[0]), 0, 0 }, + { "mmPA_SC_VPORT_ZMIN_12", REG_MMIO, 0x00cc, 1, &mmPA_SC_VPORT_ZMIN_12[0], sizeof(mmPA_SC_VPORT_ZMIN_12)/sizeof(mmPA_SC_VPORT_ZMIN_12[0]), 0, 0 }, + { "mmPA_SC_VPORT_ZMAX_12", REG_MMIO, 0x00cd, 1, &mmPA_SC_VPORT_ZMAX_12[0], sizeof(mmPA_SC_VPORT_ZMAX_12)/sizeof(mmPA_SC_VPORT_ZMAX_12[0]), 0, 0 }, + { "mmPA_SC_VPORT_ZMIN_13", REG_MMIO, 0x00ce, 1, &mmPA_SC_VPORT_ZMIN_13[0], sizeof(mmPA_SC_VPORT_ZMIN_13)/sizeof(mmPA_SC_VPORT_ZMIN_13[0]), 0, 0 }, + { "mmPA_SC_VPORT_ZMAX_13", REG_MMIO, 0x00cf, 1, &mmPA_SC_VPORT_ZMAX_13[0], sizeof(mmPA_SC_VPORT_ZMAX_13)/sizeof(mmPA_SC_VPORT_ZMAX_13[0]), 0, 0 }, + { "mmPA_SC_VPORT_ZMIN_14", REG_MMIO, 0x00d0, 1, &mmPA_SC_VPORT_ZMIN_14[0], sizeof(mmPA_SC_VPORT_ZMIN_14)/sizeof(mmPA_SC_VPORT_ZMIN_14[0]), 0, 0 }, + { "mmPA_SC_VPORT_ZMAX_14", REG_MMIO, 0x00d1, 1, &mmPA_SC_VPORT_ZMAX_14[0], sizeof(mmPA_SC_VPORT_ZMAX_14)/sizeof(mmPA_SC_VPORT_ZMAX_14[0]), 0, 0 }, + { "mmPA_SC_VPORT_ZMIN_15", REG_MMIO, 0x00d2, 1, &mmPA_SC_VPORT_ZMIN_15[0], sizeof(mmPA_SC_VPORT_ZMIN_15)/sizeof(mmPA_SC_VPORT_ZMIN_15[0]), 0, 0 }, + { "mmPA_SC_VPORT_ZMAX_15", REG_MMIO, 0x00d3, 1, &mmPA_SC_VPORT_ZMAX_15[0], sizeof(mmPA_SC_VPORT_ZMAX_15)/sizeof(mmPA_SC_VPORT_ZMAX_15[0]), 0, 0 }, + { "mmPA_SC_RASTER_CONFIG", REG_MMIO, 0x00d4, 1, &mmPA_SC_RASTER_CONFIG[0], sizeof(mmPA_SC_RASTER_CONFIG)/sizeof(mmPA_SC_RASTER_CONFIG[0]), 0, 0 }, + { "mmPA_SC_RASTER_CONFIG_1", REG_MMIO, 0x00d5, 1, &mmPA_SC_RASTER_CONFIG_1[0], sizeof(mmPA_SC_RASTER_CONFIG_1)/sizeof(mmPA_SC_RASTER_CONFIG_1[0]), 0, 0 }, + { "mmPA_SC_SCREEN_EXTENT_CONTROL", REG_MMIO, 0x00d6, 1, &mmPA_SC_SCREEN_EXTENT_CONTROL[0], sizeof(mmPA_SC_SCREEN_EXTENT_CONTROL)/sizeof(mmPA_SC_SCREEN_EXTENT_CONTROL[0]), 0, 0 }, + { "mmPA_SC_TILE_STEERING_OVERRIDE", REG_MMIO, 0x00d7, 1, &mmPA_SC_TILE_STEERING_OVERRIDE[0], sizeof(mmPA_SC_TILE_STEERING_OVERRIDE)/sizeof(mmPA_SC_TILE_STEERING_OVERRIDE[0]), 0, 0 }, + { "mmCP_PERFMON_CNTX_CNTL", REG_MMIO, 0x00d8, 1, &mmCP_PERFMON_CNTX_CNTL[0], sizeof(mmCP_PERFMON_CNTX_CNTL)/sizeof(mmCP_PERFMON_CNTX_CNTL[0]), 0, 0 }, + { "mmCP_PIPEID", REG_MMIO, 0x00d9, 1, &mmCP_PIPEID[0], sizeof(mmCP_PIPEID)/sizeof(mmCP_PIPEID[0]), 0, 0 }, + { "mmCP_RINGID", REG_MMIO, 0x00d9, 1, &mmCP_RINGID[0], sizeof(mmCP_RINGID)/sizeof(mmCP_RINGID[0]), 0, 0 }, + { "mmCP_VMID", REG_MMIO, 0x00da, 1, &mmCP_VMID[0], sizeof(mmCP_VMID)/sizeof(mmCP_VMID[0]), 0, 0 }, + { "mmPA_SC_RIGHT_VERT_GRID", REG_MMIO, 0x00e8, 1, &mmPA_SC_RIGHT_VERT_GRID[0], sizeof(mmPA_SC_RIGHT_VERT_GRID)/sizeof(mmPA_SC_RIGHT_VERT_GRID[0]), 0, 0 }, + { "mmPA_SC_LEFT_VERT_GRID", REG_MMIO, 0x00e9, 1, &mmPA_SC_LEFT_VERT_GRID[0], sizeof(mmPA_SC_LEFT_VERT_GRID)/sizeof(mmPA_SC_LEFT_VERT_GRID[0]), 0, 0 }, + { "mmPA_SC_HORIZ_GRID", REG_MMIO, 0x00ea, 1, &mmPA_SC_HORIZ_GRID[0], sizeof(mmPA_SC_HORIZ_GRID)/sizeof(mmPA_SC_HORIZ_GRID[0]), 0, 0 }, + { "mmPA_SC_FOV_WINDOW_LR", REG_MMIO, 0x00eb, 1, &mmPA_SC_FOV_WINDOW_LR[0], sizeof(mmPA_SC_FOV_WINDOW_LR)/sizeof(mmPA_SC_FOV_WINDOW_LR[0]), 0, 0 }, + { "mmPA_SC_FOV_WINDOW_TB", REG_MMIO, 0x00ec, 1, &mmPA_SC_FOV_WINDOW_TB[0], sizeof(mmPA_SC_FOV_WINDOW_TB)/sizeof(mmPA_SC_FOV_WINDOW_TB[0]), 0, 0 }, + { "mmVGT_MULTI_PRIM_IB_RESET_INDX", REG_MMIO, 0x0103, 1, &mmVGT_MULTI_PRIM_IB_RESET_INDX[0], sizeof(mmVGT_MULTI_PRIM_IB_RESET_INDX)/sizeof(mmVGT_MULTI_PRIM_IB_RESET_INDX[0]), 0, 0 }, + { "mmCB_BLEND_RED", REG_MMIO, 0x0105, 1, &mmCB_BLEND_RED[0], sizeof(mmCB_BLEND_RED)/sizeof(mmCB_BLEND_RED[0]), 0, 0 }, + { "mmCB_BLEND_GREEN", REG_MMIO, 0x0106, 1, &mmCB_BLEND_GREEN[0], sizeof(mmCB_BLEND_GREEN)/sizeof(mmCB_BLEND_GREEN[0]), 0, 0 }, + { "mmCB_BLEND_BLUE", REG_MMIO, 0x0107, 1, &mmCB_BLEND_BLUE[0], sizeof(mmCB_BLEND_BLUE)/sizeof(mmCB_BLEND_BLUE[0]), 0, 0 }, + { "mmCB_BLEND_ALPHA", REG_MMIO, 0x0108, 1, &mmCB_BLEND_ALPHA[0], sizeof(mmCB_BLEND_ALPHA)/sizeof(mmCB_BLEND_ALPHA[0]), 0, 0 }, + { "mmCB_DCC_CONTROL", REG_MMIO, 0x0109, 1, &mmCB_DCC_CONTROL[0], sizeof(mmCB_DCC_CONTROL)/sizeof(mmCB_DCC_CONTROL[0]), 0, 0 }, + { "mmDB_STENCIL_CONTROL", REG_MMIO, 0x010b, 1, &mmDB_STENCIL_CONTROL[0], sizeof(mmDB_STENCIL_CONTROL)/sizeof(mmDB_STENCIL_CONTROL[0]), 0, 0 }, + { "mmDB_STENCILREFMASK", REG_MMIO, 0x010c, 1, &mmDB_STENCILREFMASK[0], sizeof(mmDB_STENCILREFMASK)/sizeof(mmDB_STENCILREFMASK[0]), 0, 0 }, + { "mmDB_STENCILREFMASK_BF", REG_MMIO, 0x010d, 1, &mmDB_STENCILREFMASK_BF[0], sizeof(mmDB_STENCILREFMASK_BF)/sizeof(mmDB_STENCILREFMASK_BF[0]), 0, 0 }, + { "mmPA_CL_VPORT_XSCALE", REG_MMIO, 0x010f, 1, &mmPA_CL_VPORT_XSCALE[0], sizeof(mmPA_CL_VPORT_XSCALE)/sizeof(mmPA_CL_VPORT_XSCALE[0]), 0, 0 }, + { "mmPA_CL_VPORT_XOFFSET", REG_MMIO, 0x0110, 1, &mmPA_CL_VPORT_XOFFSET[0], sizeof(mmPA_CL_VPORT_XOFFSET)/sizeof(mmPA_CL_VPORT_XOFFSET[0]), 0, 0 }, + { "mmPA_CL_VPORT_YSCALE", REG_MMIO, 0x0111, 1, &mmPA_CL_VPORT_YSCALE[0], sizeof(mmPA_CL_VPORT_YSCALE)/sizeof(mmPA_CL_VPORT_YSCALE[0]), 0, 0 }, + { "mmPA_CL_VPORT_YOFFSET", REG_MMIO, 0x0112, 1, &mmPA_CL_VPORT_YOFFSET[0], sizeof(mmPA_CL_VPORT_YOFFSET)/sizeof(mmPA_CL_VPORT_YOFFSET[0]), 0, 0 }, + { "mmPA_CL_VPORT_ZSCALE", REG_MMIO, 0x0113, 1, &mmPA_CL_VPORT_ZSCALE[0], sizeof(mmPA_CL_VPORT_ZSCALE)/sizeof(mmPA_CL_VPORT_ZSCALE[0]), 0, 0 }, + { "mmPA_CL_VPORT_ZOFFSET", REG_MMIO, 0x0114, 1, &mmPA_CL_VPORT_ZOFFSET[0], sizeof(mmPA_CL_VPORT_ZOFFSET)/sizeof(mmPA_CL_VPORT_ZOFFSET[0]), 0, 0 }, + { "mmPA_CL_VPORT_XSCALE_1", REG_MMIO, 0x0115, 1, &mmPA_CL_VPORT_XSCALE_1[0], sizeof(mmPA_CL_VPORT_XSCALE_1)/sizeof(mmPA_CL_VPORT_XSCALE_1[0]), 0, 0 }, + { "mmPA_CL_VPORT_XOFFSET_1", REG_MMIO, 0x0116, 1, &mmPA_CL_VPORT_XOFFSET_1[0], sizeof(mmPA_CL_VPORT_XOFFSET_1)/sizeof(mmPA_CL_VPORT_XOFFSET_1[0]), 0, 0 }, + { "mmPA_CL_VPORT_YSCALE_1", REG_MMIO, 0x0117, 1, &mmPA_CL_VPORT_YSCALE_1[0], sizeof(mmPA_CL_VPORT_YSCALE_1)/sizeof(mmPA_CL_VPORT_YSCALE_1[0]), 0, 0 }, + { "mmPA_CL_VPORT_YOFFSET_1", REG_MMIO, 0x0118, 1, &mmPA_CL_VPORT_YOFFSET_1[0], sizeof(mmPA_CL_VPORT_YOFFSET_1)/sizeof(mmPA_CL_VPORT_YOFFSET_1[0]), 0, 0 }, + { "mmPA_CL_VPORT_ZSCALE_1", REG_MMIO, 0x0119, 1, &mmPA_CL_VPORT_ZSCALE_1[0], sizeof(mmPA_CL_VPORT_ZSCALE_1)/sizeof(mmPA_CL_VPORT_ZSCALE_1[0]), 0, 0 }, + { "mmPA_CL_VPORT_ZOFFSET_1", REG_MMIO, 0x011a, 1, &mmPA_CL_VPORT_ZOFFSET_1[0], sizeof(mmPA_CL_VPORT_ZOFFSET_1)/sizeof(mmPA_CL_VPORT_ZOFFSET_1[0]), 0, 0 }, + { "mmPA_CL_VPORT_XSCALE_2", REG_MMIO, 0x011b, 1, &mmPA_CL_VPORT_XSCALE_2[0], sizeof(mmPA_CL_VPORT_XSCALE_2)/sizeof(mmPA_CL_VPORT_XSCALE_2[0]), 0, 0 }, + { "mmPA_CL_VPORT_XOFFSET_2", REG_MMIO, 0x011c, 1, &mmPA_CL_VPORT_XOFFSET_2[0], sizeof(mmPA_CL_VPORT_XOFFSET_2)/sizeof(mmPA_CL_VPORT_XOFFSET_2[0]), 0, 0 }, + { "mmPA_CL_VPORT_YSCALE_2", REG_MMIO, 0x011d, 1, &mmPA_CL_VPORT_YSCALE_2[0], sizeof(mmPA_CL_VPORT_YSCALE_2)/sizeof(mmPA_CL_VPORT_YSCALE_2[0]), 0, 0 }, + { "mmPA_CL_VPORT_YOFFSET_2", REG_MMIO, 0x011e, 1, &mmPA_CL_VPORT_YOFFSET_2[0], sizeof(mmPA_CL_VPORT_YOFFSET_2)/sizeof(mmPA_CL_VPORT_YOFFSET_2[0]), 0, 0 }, + { "mmPA_CL_VPORT_ZSCALE_2", REG_MMIO, 0x011f, 1, &mmPA_CL_VPORT_ZSCALE_2[0], sizeof(mmPA_CL_VPORT_ZSCALE_2)/sizeof(mmPA_CL_VPORT_ZSCALE_2[0]), 0, 0 }, + { "mmPA_CL_VPORT_ZOFFSET_2", REG_MMIO, 0x0120, 1, &mmPA_CL_VPORT_ZOFFSET_2[0], sizeof(mmPA_CL_VPORT_ZOFFSET_2)/sizeof(mmPA_CL_VPORT_ZOFFSET_2[0]), 0, 0 }, + { "mmPA_CL_VPORT_XSCALE_3", REG_MMIO, 0x0121, 1, &mmPA_CL_VPORT_XSCALE_3[0], sizeof(mmPA_CL_VPORT_XSCALE_3)/sizeof(mmPA_CL_VPORT_XSCALE_3[0]), 0, 0 }, + { "mmPA_CL_VPORT_XOFFSET_3", REG_MMIO, 0x0122, 1, &mmPA_CL_VPORT_XOFFSET_3[0], sizeof(mmPA_CL_VPORT_XOFFSET_3)/sizeof(mmPA_CL_VPORT_XOFFSET_3[0]), 0, 0 }, + { "mmPA_CL_VPORT_YSCALE_3", REG_MMIO, 0x0123, 1, &mmPA_CL_VPORT_YSCALE_3[0], sizeof(mmPA_CL_VPORT_YSCALE_3)/sizeof(mmPA_CL_VPORT_YSCALE_3[0]), 0, 0 }, + { "mmPA_CL_VPORT_YOFFSET_3", REG_MMIO, 0x0124, 1, &mmPA_CL_VPORT_YOFFSET_3[0], sizeof(mmPA_CL_VPORT_YOFFSET_3)/sizeof(mmPA_CL_VPORT_YOFFSET_3[0]), 0, 0 }, + { "mmPA_CL_VPORT_ZSCALE_3", REG_MMIO, 0x0125, 1, &mmPA_CL_VPORT_ZSCALE_3[0], sizeof(mmPA_CL_VPORT_ZSCALE_3)/sizeof(mmPA_CL_VPORT_ZSCALE_3[0]), 0, 0 }, + { "mmPA_CL_VPORT_ZOFFSET_3", REG_MMIO, 0x0126, 1, &mmPA_CL_VPORT_ZOFFSET_3[0], sizeof(mmPA_CL_VPORT_ZOFFSET_3)/sizeof(mmPA_CL_VPORT_ZOFFSET_3[0]), 0, 0 }, + { "mmPA_CL_VPORT_XSCALE_4", REG_MMIO, 0x0127, 1, &mmPA_CL_VPORT_XSCALE_4[0], sizeof(mmPA_CL_VPORT_XSCALE_4)/sizeof(mmPA_CL_VPORT_XSCALE_4[0]), 0, 0 }, + { "mmPA_CL_VPORT_XOFFSET_4", REG_MMIO, 0x0128, 1, &mmPA_CL_VPORT_XOFFSET_4[0], sizeof(mmPA_CL_VPORT_XOFFSET_4)/sizeof(mmPA_CL_VPORT_XOFFSET_4[0]), 0, 0 }, + { "mmPA_CL_VPORT_YSCALE_4", REG_MMIO, 0x0129, 1, &mmPA_CL_VPORT_YSCALE_4[0], sizeof(mmPA_CL_VPORT_YSCALE_4)/sizeof(mmPA_CL_VPORT_YSCALE_4[0]), 0, 0 }, + { "mmPA_CL_VPORT_YOFFSET_4", REG_MMIO, 0x012a, 1, &mmPA_CL_VPORT_YOFFSET_4[0], sizeof(mmPA_CL_VPORT_YOFFSET_4)/sizeof(mmPA_CL_VPORT_YOFFSET_4[0]), 0, 0 }, + { "mmPA_CL_VPORT_ZSCALE_4", REG_MMIO, 0x012b, 1, &mmPA_CL_VPORT_ZSCALE_4[0], sizeof(mmPA_CL_VPORT_ZSCALE_4)/sizeof(mmPA_CL_VPORT_ZSCALE_4[0]), 0, 0 }, + { "mmPA_CL_VPORT_ZOFFSET_4", REG_MMIO, 0x012c, 1, &mmPA_CL_VPORT_ZOFFSET_4[0], sizeof(mmPA_CL_VPORT_ZOFFSET_4)/sizeof(mmPA_CL_VPORT_ZOFFSET_4[0]), 0, 0 }, + { "mmPA_CL_VPORT_XSCALE_5", REG_MMIO, 0x012d, 1, &mmPA_CL_VPORT_XSCALE_5[0], sizeof(mmPA_CL_VPORT_XSCALE_5)/sizeof(mmPA_CL_VPORT_XSCALE_5[0]), 0, 0 }, + { "mmPA_CL_VPORT_XOFFSET_5", REG_MMIO, 0x012e, 1, &mmPA_CL_VPORT_XOFFSET_5[0], sizeof(mmPA_CL_VPORT_XOFFSET_5)/sizeof(mmPA_CL_VPORT_XOFFSET_5[0]), 0, 0 }, + { "mmPA_CL_VPORT_YSCALE_5", REG_MMIO, 0x012f, 1, &mmPA_CL_VPORT_YSCALE_5[0], sizeof(mmPA_CL_VPORT_YSCALE_5)/sizeof(mmPA_CL_VPORT_YSCALE_5[0]), 0, 0 }, + { "mmPA_CL_VPORT_YOFFSET_5", REG_MMIO, 0x0130, 1, &mmPA_CL_VPORT_YOFFSET_5[0], sizeof(mmPA_CL_VPORT_YOFFSET_5)/sizeof(mmPA_CL_VPORT_YOFFSET_5[0]), 0, 0 }, + { "mmPA_CL_VPORT_ZSCALE_5", REG_MMIO, 0x0131, 1, &mmPA_CL_VPORT_ZSCALE_5[0], sizeof(mmPA_CL_VPORT_ZSCALE_5)/sizeof(mmPA_CL_VPORT_ZSCALE_5[0]), 0, 0 }, + { "mmPA_CL_VPORT_ZOFFSET_5", REG_MMIO, 0x0132, 1, &mmPA_CL_VPORT_ZOFFSET_5[0], sizeof(mmPA_CL_VPORT_ZOFFSET_5)/sizeof(mmPA_CL_VPORT_ZOFFSET_5[0]), 0, 0 }, + { "mmPA_CL_VPORT_XSCALE_6", REG_MMIO, 0x0133, 1, &mmPA_CL_VPORT_XSCALE_6[0], sizeof(mmPA_CL_VPORT_XSCALE_6)/sizeof(mmPA_CL_VPORT_XSCALE_6[0]), 0, 0 }, + { "mmPA_CL_VPORT_XOFFSET_6", REG_MMIO, 0x0134, 1, &mmPA_CL_VPORT_XOFFSET_6[0], sizeof(mmPA_CL_VPORT_XOFFSET_6)/sizeof(mmPA_CL_VPORT_XOFFSET_6[0]), 0, 0 }, + { "mmPA_CL_VPORT_YSCALE_6", REG_MMIO, 0x0135, 1, &mmPA_CL_VPORT_YSCALE_6[0], sizeof(mmPA_CL_VPORT_YSCALE_6)/sizeof(mmPA_CL_VPORT_YSCALE_6[0]), 0, 0 }, + { "mmPA_CL_VPORT_YOFFSET_6", REG_MMIO, 0x0136, 1, &mmPA_CL_VPORT_YOFFSET_6[0], sizeof(mmPA_CL_VPORT_YOFFSET_6)/sizeof(mmPA_CL_VPORT_YOFFSET_6[0]), 0, 0 }, + { "mmPA_CL_VPORT_ZSCALE_6", REG_MMIO, 0x0137, 1, &mmPA_CL_VPORT_ZSCALE_6[0], sizeof(mmPA_CL_VPORT_ZSCALE_6)/sizeof(mmPA_CL_VPORT_ZSCALE_6[0]), 0, 0 }, + { "mmPA_CL_VPORT_ZOFFSET_6", REG_MMIO, 0x0138, 1, &mmPA_CL_VPORT_ZOFFSET_6[0], sizeof(mmPA_CL_VPORT_ZOFFSET_6)/sizeof(mmPA_CL_VPORT_ZOFFSET_6[0]), 0, 0 }, + { "mmPA_CL_VPORT_XSCALE_7", REG_MMIO, 0x0139, 1, &mmPA_CL_VPORT_XSCALE_7[0], sizeof(mmPA_CL_VPORT_XSCALE_7)/sizeof(mmPA_CL_VPORT_XSCALE_7[0]), 0, 0 }, + { "mmPA_CL_VPORT_XOFFSET_7", REG_MMIO, 0x013a, 1, &mmPA_CL_VPORT_XOFFSET_7[0], sizeof(mmPA_CL_VPORT_XOFFSET_7)/sizeof(mmPA_CL_VPORT_XOFFSET_7[0]), 0, 0 }, + { "mmPA_CL_VPORT_YSCALE_7", REG_MMIO, 0x013b, 1, &mmPA_CL_VPORT_YSCALE_7[0], sizeof(mmPA_CL_VPORT_YSCALE_7)/sizeof(mmPA_CL_VPORT_YSCALE_7[0]), 0, 0 }, + { "mmPA_CL_VPORT_YOFFSET_7", REG_MMIO, 0x013c, 1, &mmPA_CL_VPORT_YOFFSET_7[0], sizeof(mmPA_CL_VPORT_YOFFSET_7)/sizeof(mmPA_CL_VPORT_YOFFSET_7[0]), 0, 0 }, + { "mmPA_CL_VPORT_ZSCALE_7", REG_MMIO, 0x013d, 1, &mmPA_CL_VPORT_ZSCALE_7[0], sizeof(mmPA_CL_VPORT_ZSCALE_7)/sizeof(mmPA_CL_VPORT_ZSCALE_7[0]), 0, 0 }, + { "mmPA_CL_VPORT_ZOFFSET_7", REG_MMIO, 0x013e, 1, &mmPA_CL_VPORT_ZOFFSET_7[0], sizeof(mmPA_CL_VPORT_ZOFFSET_7)/sizeof(mmPA_CL_VPORT_ZOFFSET_7[0]), 0, 0 }, + { "mmPA_CL_VPORT_XSCALE_8", REG_MMIO, 0x013f, 1, &mmPA_CL_VPORT_XSCALE_8[0], sizeof(mmPA_CL_VPORT_XSCALE_8)/sizeof(mmPA_CL_VPORT_XSCALE_8[0]), 0, 0 }, + { "mmPA_CL_VPORT_XOFFSET_8", REG_MMIO, 0x0140, 1, &mmPA_CL_VPORT_XOFFSET_8[0], sizeof(mmPA_CL_VPORT_XOFFSET_8)/sizeof(mmPA_CL_VPORT_XOFFSET_8[0]), 0, 0 }, + { "mmPA_CL_VPORT_YSCALE_8", REG_MMIO, 0x0141, 1, &mmPA_CL_VPORT_YSCALE_8[0], sizeof(mmPA_CL_VPORT_YSCALE_8)/sizeof(mmPA_CL_VPORT_YSCALE_8[0]), 0, 0 }, + { "mmPA_CL_VPORT_YOFFSET_8", REG_MMIO, 0x0142, 1, &mmPA_CL_VPORT_YOFFSET_8[0], sizeof(mmPA_CL_VPORT_YOFFSET_8)/sizeof(mmPA_CL_VPORT_YOFFSET_8[0]), 0, 0 }, + { "mmPA_CL_VPORT_ZSCALE_8", REG_MMIO, 0x0143, 1, &mmPA_CL_VPORT_ZSCALE_8[0], sizeof(mmPA_CL_VPORT_ZSCALE_8)/sizeof(mmPA_CL_VPORT_ZSCALE_8[0]), 0, 0 }, + { "mmPA_CL_VPORT_ZOFFSET_8", REG_MMIO, 0x0144, 1, &mmPA_CL_VPORT_ZOFFSET_8[0], sizeof(mmPA_CL_VPORT_ZOFFSET_8)/sizeof(mmPA_CL_VPORT_ZOFFSET_8[0]), 0, 0 }, + { "mmPA_CL_VPORT_XSCALE_9", REG_MMIO, 0x0145, 1, &mmPA_CL_VPORT_XSCALE_9[0], sizeof(mmPA_CL_VPORT_XSCALE_9)/sizeof(mmPA_CL_VPORT_XSCALE_9[0]), 0, 0 }, + { "mmPA_CL_VPORT_XOFFSET_9", REG_MMIO, 0x0146, 1, &mmPA_CL_VPORT_XOFFSET_9[0], sizeof(mmPA_CL_VPORT_XOFFSET_9)/sizeof(mmPA_CL_VPORT_XOFFSET_9[0]), 0, 0 }, + { "mmPA_CL_VPORT_YSCALE_9", REG_MMIO, 0x0147, 1, &mmPA_CL_VPORT_YSCALE_9[0], sizeof(mmPA_CL_VPORT_YSCALE_9)/sizeof(mmPA_CL_VPORT_YSCALE_9[0]), 0, 0 }, + { "mmPA_CL_VPORT_YOFFSET_9", REG_MMIO, 0x0148, 1, &mmPA_CL_VPORT_YOFFSET_9[0], sizeof(mmPA_CL_VPORT_YOFFSET_9)/sizeof(mmPA_CL_VPORT_YOFFSET_9[0]), 0, 0 }, + { "mmPA_CL_VPORT_ZSCALE_9", REG_MMIO, 0x0149, 1, &mmPA_CL_VPORT_ZSCALE_9[0], sizeof(mmPA_CL_VPORT_ZSCALE_9)/sizeof(mmPA_CL_VPORT_ZSCALE_9[0]), 0, 0 }, + { "mmPA_CL_VPORT_ZOFFSET_9", REG_MMIO, 0x014a, 1, &mmPA_CL_VPORT_ZOFFSET_9[0], sizeof(mmPA_CL_VPORT_ZOFFSET_9)/sizeof(mmPA_CL_VPORT_ZOFFSET_9[0]), 0, 0 }, + { "mmPA_CL_VPORT_XSCALE_10", REG_MMIO, 0x014b, 1, &mmPA_CL_VPORT_XSCALE_10[0], sizeof(mmPA_CL_VPORT_XSCALE_10)/sizeof(mmPA_CL_VPORT_XSCALE_10[0]), 0, 0 }, + { "mmPA_CL_VPORT_XOFFSET_10", REG_MMIO, 0x014c, 1, &mmPA_CL_VPORT_XOFFSET_10[0], sizeof(mmPA_CL_VPORT_XOFFSET_10)/sizeof(mmPA_CL_VPORT_XOFFSET_10[0]), 0, 0 }, + { "mmPA_CL_VPORT_YSCALE_10", REG_MMIO, 0x014d, 1, &mmPA_CL_VPORT_YSCALE_10[0], sizeof(mmPA_CL_VPORT_YSCALE_10)/sizeof(mmPA_CL_VPORT_YSCALE_10[0]), 0, 0 }, + { "mmPA_CL_VPORT_YOFFSET_10", REG_MMIO, 0x014e, 1, &mmPA_CL_VPORT_YOFFSET_10[0], sizeof(mmPA_CL_VPORT_YOFFSET_10)/sizeof(mmPA_CL_VPORT_YOFFSET_10[0]), 0, 0 }, + { "mmPA_CL_VPORT_ZSCALE_10", REG_MMIO, 0x014f, 1, &mmPA_CL_VPORT_ZSCALE_10[0], sizeof(mmPA_CL_VPORT_ZSCALE_10)/sizeof(mmPA_CL_VPORT_ZSCALE_10[0]), 0, 0 }, + { "mmPA_CL_VPORT_ZOFFSET_10", REG_MMIO, 0x0150, 1, &mmPA_CL_VPORT_ZOFFSET_10[0], sizeof(mmPA_CL_VPORT_ZOFFSET_10)/sizeof(mmPA_CL_VPORT_ZOFFSET_10[0]), 0, 0 }, + { "mmPA_CL_VPORT_XSCALE_11", REG_MMIO, 0x0151, 1, &mmPA_CL_VPORT_XSCALE_11[0], sizeof(mmPA_CL_VPORT_XSCALE_11)/sizeof(mmPA_CL_VPORT_XSCALE_11[0]), 0, 0 }, + { "mmPA_CL_VPORT_XOFFSET_11", REG_MMIO, 0x0152, 1, &mmPA_CL_VPORT_XOFFSET_11[0], sizeof(mmPA_CL_VPORT_XOFFSET_11)/sizeof(mmPA_CL_VPORT_XOFFSET_11[0]), 0, 0 }, + { "mmPA_CL_VPORT_YSCALE_11", REG_MMIO, 0x0153, 1, &mmPA_CL_VPORT_YSCALE_11[0], sizeof(mmPA_CL_VPORT_YSCALE_11)/sizeof(mmPA_CL_VPORT_YSCALE_11[0]), 0, 0 }, + { "mmPA_CL_VPORT_YOFFSET_11", REG_MMIO, 0x0154, 1, &mmPA_CL_VPORT_YOFFSET_11[0], sizeof(mmPA_CL_VPORT_YOFFSET_11)/sizeof(mmPA_CL_VPORT_YOFFSET_11[0]), 0, 0 }, + { "mmPA_CL_VPORT_ZSCALE_11", REG_MMIO, 0x0155, 1, &mmPA_CL_VPORT_ZSCALE_11[0], sizeof(mmPA_CL_VPORT_ZSCALE_11)/sizeof(mmPA_CL_VPORT_ZSCALE_11[0]), 0, 0 }, + { "mmPA_CL_VPORT_ZOFFSET_11", REG_MMIO, 0x0156, 1, &mmPA_CL_VPORT_ZOFFSET_11[0], sizeof(mmPA_CL_VPORT_ZOFFSET_11)/sizeof(mmPA_CL_VPORT_ZOFFSET_11[0]), 0, 0 }, + { "mmPA_CL_VPORT_XSCALE_12", REG_MMIO, 0x0157, 1, &mmPA_CL_VPORT_XSCALE_12[0], sizeof(mmPA_CL_VPORT_XSCALE_12)/sizeof(mmPA_CL_VPORT_XSCALE_12[0]), 0, 0 }, + { "mmPA_CL_VPORT_XOFFSET_12", REG_MMIO, 0x0158, 1, &mmPA_CL_VPORT_XOFFSET_12[0], sizeof(mmPA_CL_VPORT_XOFFSET_12)/sizeof(mmPA_CL_VPORT_XOFFSET_12[0]), 0, 0 }, + { "mmPA_CL_VPORT_YSCALE_12", REG_MMIO, 0x0159, 1, &mmPA_CL_VPORT_YSCALE_12[0], sizeof(mmPA_CL_VPORT_YSCALE_12)/sizeof(mmPA_CL_VPORT_YSCALE_12[0]), 0, 0 }, + { "mmPA_CL_VPORT_YOFFSET_12", REG_MMIO, 0x015a, 1, &mmPA_CL_VPORT_YOFFSET_12[0], sizeof(mmPA_CL_VPORT_YOFFSET_12)/sizeof(mmPA_CL_VPORT_YOFFSET_12[0]), 0, 0 }, + { "mmPA_CL_VPORT_ZSCALE_12", REG_MMIO, 0x015b, 1, &mmPA_CL_VPORT_ZSCALE_12[0], sizeof(mmPA_CL_VPORT_ZSCALE_12)/sizeof(mmPA_CL_VPORT_ZSCALE_12[0]), 0, 0 }, + { "mmPA_CL_VPORT_ZOFFSET_12", REG_MMIO, 0x015c, 1, &mmPA_CL_VPORT_ZOFFSET_12[0], sizeof(mmPA_CL_VPORT_ZOFFSET_12)/sizeof(mmPA_CL_VPORT_ZOFFSET_12[0]), 0, 0 }, + { "mmPA_CL_VPORT_XSCALE_13", REG_MMIO, 0x015d, 1, &mmPA_CL_VPORT_XSCALE_13[0], sizeof(mmPA_CL_VPORT_XSCALE_13)/sizeof(mmPA_CL_VPORT_XSCALE_13[0]), 0, 0 }, + { "mmPA_CL_VPORT_XOFFSET_13", REG_MMIO, 0x015e, 1, &mmPA_CL_VPORT_XOFFSET_13[0], sizeof(mmPA_CL_VPORT_XOFFSET_13)/sizeof(mmPA_CL_VPORT_XOFFSET_13[0]), 0, 0 }, + { "mmPA_CL_VPORT_YSCALE_13", REG_MMIO, 0x015f, 1, &mmPA_CL_VPORT_YSCALE_13[0], sizeof(mmPA_CL_VPORT_YSCALE_13)/sizeof(mmPA_CL_VPORT_YSCALE_13[0]), 0, 0 }, + { "mmPA_CL_VPORT_YOFFSET_13", REG_MMIO, 0x0160, 1, &mmPA_CL_VPORT_YOFFSET_13[0], sizeof(mmPA_CL_VPORT_YOFFSET_13)/sizeof(mmPA_CL_VPORT_YOFFSET_13[0]), 0, 0 }, + { "mmPA_CL_VPORT_ZSCALE_13", REG_MMIO, 0x0161, 1, &mmPA_CL_VPORT_ZSCALE_13[0], sizeof(mmPA_CL_VPORT_ZSCALE_13)/sizeof(mmPA_CL_VPORT_ZSCALE_13[0]), 0, 0 }, + { "mmPA_CL_VPORT_ZOFFSET_13", REG_MMIO, 0x0162, 1, &mmPA_CL_VPORT_ZOFFSET_13[0], sizeof(mmPA_CL_VPORT_ZOFFSET_13)/sizeof(mmPA_CL_VPORT_ZOFFSET_13[0]), 0, 0 }, + { "mmPA_CL_VPORT_XSCALE_14", REG_MMIO, 0x0163, 1, &mmPA_CL_VPORT_XSCALE_14[0], sizeof(mmPA_CL_VPORT_XSCALE_14)/sizeof(mmPA_CL_VPORT_XSCALE_14[0]), 0, 0 }, + { "mmPA_CL_VPORT_XOFFSET_14", REG_MMIO, 0x0164, 1, &mmPA_CL_VPORT_XOFFSET_14[0], sizeof(mmPA_CL_VPORT_XOFFSET_14)/sizeof(mmPA_CL_VPORT_XOFFSET_14[0]), 0, 0 }, + { "mmPA_CL_VPORT_YSCALE_14", REG_MMIO, 0x0165, 1, &mmPA_CL_VPORT_YSCALE_14[0], sizeof(mmPA_CL_VPORT_YSCALE_14)/sizeof(mmPA_CL_VPORT_YSCALE_14[0]), 0, 0 }, + { "mmPA_CL_VPORT_YOFFSET_14", REG_MMIO, 0x0166, 1, &mmPA_CL_VPORT_YOFFSET_14[0], sizeof(mmPA_CL_VPORT_YOFFSET_14)/sizeof(mmPA_CL_VPORT_YOFFSET_14[0]), 0, 0 }, + { "mmPA_CL_VPORT_ZSCALE_14", REG_MMIO, 0x0167, 1, &mmPA_CL_VPORT_ZSCALE_14[0], sizeof(mmPA_CL_VPORT_ZSCALE_14)/sizeof(mmPA_CL_VPORT_ZSCALE_14[0]), 0, 0 }, + { "mmPA_CL_VPORT_ZOFFSET_14", REG_MMIO, 0x0168, 1, &mmPA_CL_VPORT_ZOFFSET_14[0], sizeof(mmPA_CL_VPORT_ZOFFSET_14)/sizeof(mmPA_CL_VPORT_ZOFFSET_14[0]), 0, 0 }, + { "mmPA_CL_VPORT_XSCALE_15", REG_MMIO, 0x0169, 1, &mmPA_CL_VPORT_XSCALE_15[0], sizeof(mmPA_CL_VPORT_XSCALE_15)/sizeof(mmPA_CL_VPORT_XSCALE_15[0]), 0, 0 }, + { "mmPA_CL_VPORT_XOFFSET_15", REG_MMIO, 0x016a, 1, &mmPA_CL_VPORT_XOFFSET_15[0], sizeof(mmPA_CL_VPORT_XOFFSET_15)/sizeof(mmPA_CL_VPORT_XOFFSET_15[0]), 0, 0 }, + { "mmPA_CL_VPORT_YSCALE_15", REG_MMIO, 0x016b, 1, &mmPA_CL_VPORT_YSCALE_15[0], sizeof(mmPA_CL_VPORT_YSCALE_15)/sizeof(mmPA_CL_VPORT_YSCALE_15[0]), 0, 0 }, + { "mmPA_CL_VPORT_YOFFSET_15", REG_MMIO, 0x016c, 1, &mmPA_CL_VPORT_YOFFSET_15[0], sizeof(mmPA_CL_VPORT_YOFFSET_15)/sizeof(mmPA_CL_VPORT_YOFFSET_15[0]), 0, 0 }, + { "mmPA_CL_VPORT_ZSCALE_15", REG_MMIO, 0x016d, 1, &mmPA_CL_VPORT_ZSCALE_15[0], sizeof(mmPA_CL_VPORT_ZSCALE_15)/sizeof(mmPA_CL_VPORT_ZSCALE_15[0]), 0, 0 }, + { "mmPA_CL_VPORT_ZOFFSET_15", REG_MMIO, 0x016e, 1, &mmPA_CL_VPORT_ZOFFSET_15[0], sizeof(mmPA_CL_VPORT_ZOFFSET_15)/sizeof(mmPA_CL_VPORT_ZOFFSET_15[0]), 0, 0 }, + { "mmPA_CL_UCP_0_X", REG_MMIO, 0x016f, 1, &mmPA_CL_UCP_0_X[0], sizeof(mmPA_CL_UCP_0_X)/sizeof(mmPA_CL_UCP_0_X[0]), 0, 0 }, + { "mmPA_CL_UCP_0_Y", REG_MMIO, 0x0170, 1, &mmPA_CL_UCP_0_Y[0], sizeof(mmPA_CL_UCP_0_Y)/sizeof(mmPA_CL_UCP_0_Y[0]), 0, 0 }, + { "mmPA_CL_UCP_0_Z", REG_MMIO, 0x0171, 1, &mmPA_CL_UCP_0_Z[0], sizeof(mmPA_CL_UCP_0_Z)/sizeof(mmPA_CL_UCP_0_Z[0]), 0, 0 }, + { "mmPA_CL_UCP_0_W", REG_MMIO, 0x0172, 1, &mmPA_CL_UCP_0_W[0], sizeof(mmPA_CL_UCP_0_W)/sizeof(mmPA_CL_UCP_0_W[0]), 0, 0 }, + { "mmPA_CL_UCP_1_X", REG_MMIO, 0x0173, 1, &mmPA_CL_UCP_1_X[0], sizeof(mmPA_CL_UCP_1_X)/sizeof(mmPA_CL_UCP_1_X[0]), 0, 0 }, + { "mmPA_CL_UCP_1_Y", REG_MMIO, 0x0174, 1, &mmPA_CL_UCP_1_Y[0], sizeof(mmPA_CL_UCP_1_Y)/sizeof(mmPA_CL_UCP_1_Y[0]), 0, 0 }, + { "mmPA_CL_UCP_1_Z", REG_MMIO, 0x0175, 1, &mmPA_CL_UCP_1_Z[0], sizeof(mmPA_CL_UCP_1_Z)/sizeof(mmPA_CL_UCP_1_Z[0]), 0, 0 }, + { "mmPA_CL_UCP_1_W", REG_MMIO, 0x0176, 1, &mmPA_CL_UCP_1_W[0], sizeof(mmPA_CL_UCP_1_W)/sizeof(mmPA_CL_UCP_1_W[0]), 0, 0 }, + { "mmPA_CL_UCP_2_X", REG_MMIO, 0x0177, 1, &mmPA_CL_UCP_2_X[0], sizeof(mmPA_CL_UCP_2_X)/sizeof(mmPA_CL_UCP_2_X[0]), 0, 0 }, + { "mmPA_CL_UCP_2_Y", REG_MMIO, 0x0178, 1, &mmPA_CL_UCP_2_Y[0], sizeof(mmPA_CL_UCP_2_Y)/sizeof(mmPA_CL_UCP_2_Y[0]), 0, 0 }, + { "mmPA_CL_UCP_2_Z", REG_MMIO, 0x0179, 1, &mmPA_CL_UCP_2_Z[0], sizeof(mmPA_CL_UCP_2_Z)/sizeof(mmPA_CL_UCP_2_Z[0]), 0, 0 }, + { "mmPA_CL_UCP_2_W", REG_MMIO, 0x017a, 1, &mmPA_CL_UCP_2_W[0], sizeof(mmPA_CL_UCP_2_W)/sizeof(mmPA_CL_UCP_2_W[0]), 0, 0 }, + { "mmPA_CL_UCP_3_X", REG_MMIO, 0x017b, 1, &mmPA_CL_UCP_3_X[0], sizeof(mmPA_CL_UCP_3_X)/sizeof(mmPA_CL_UCP_3_X[0]), 0, 0 }, + { "mmPA_CL_UCP_3_Y", REG_MMIO, 0x017c, 1, &mmPA_CL_UCP_3_Y[0], sizeof(mmPA_CL_UCP_3_Y)/sizeof(mmPA_CL_UCP_3_Y[0]), 0, 0 }, + { "mmPA_CL_UCP_3_Z", REG_MMIO, 0x017d, 1, &mmPA_CL_UCP_3_Z[0], sizeof(mmPA_CL_UCP_3_Z)/sizeof(mmPA_CL_UCP_3_Z[0]), 0, 0 }, + { "mmPA_CL_UCP_3_W", REG_MMIO, 0x017e, 1, &mmPA_CL_UCP_3_W[0], sizeof(mmPA_CL_UCP_3_W)/sizeof(mmPA_CL_UCP_3_W[0]), 0, 0 }, + { "mmPA_CL_UCP_4_X", REG_MMIO, 0x017f, 1, &mmPA_CL_UCP_4_X[0], sizeof(mmPA_CL_UCP_4_X)/sizeof(mmPA_CL_UCP_4_X[0]), 0, 0 }, + { "mmPA_CL_UCP_4_Y", REG_MMIO, 0x0180, 1, &mmPA_CL_UCP_4_Y[0], sizeof(mmPA_CL_UCP_4_Y)/sizeof(mmPA_CL_UCP_4_Y[0]), 0, 0 }, + { "mmPA_CL_UCP_4_Z", REG_MMIO, 0x0181, 1, &mmPA_CL_UCP_4_Z[0], sizeof(mmPA_CL_UCP_4_Z)/sizeof(mmPA_CL_UCP_4_Z[0]), 0, 0 }, + { "mmPA_CL_UCP_4_W", REG_MMIO, 0x0182, 1, &mmPA_CL_UCP_4_W[0], sizeof(mmPA_CL_UCP_4_W)/sizeof(mmPA_CL_UCP_4_W[0]), 0, 0 }, + { "mmPA_CL_UCP_5_X", REG_MMIO, 0x0183, 1, &mmPA_CL_UCP_5_X[0], sizeof(mmPA_CL_UCP_5_X)/sizeof(mmPA_CL_UCP_5_X[0]), 0, 0 }, + { "mmPA_CL_UCP_5_Y", REG_MMIO, 0x0184, 1, &mmPA_CL_UCP_5_Y[0], sizeof(mmPA_CL_UCP_5_Y)/sizeof(mmPA_CL_UCP_5_Y[0]), 0, 0 }, + { "mmPA_CL_UCP_5_Z", REG_MMIO, 0x0185, 1, &mmPA_CL_UCP_5_Z[0], sizeof(mmPA_CL_UCP_5_Z)/sizeof(mmPA_CL_UCP_5_Z[0]), 0, 0 }, + { "mmPA_CL_UCP_5_W", REG_MMIO, 0x0186, 1, &mmPA_CL_UCP_5_W[0], sizeof(mmPA_CL_UCP_5_W)/sizeof(mmPA_CL_UCP_5_W[0]), 0, 0 }, + { "mmSPI_PS_INPUT_CNTL_0", REG_MMIO, 0x0191, 1, &mmSPI_PS_INPUT_CNTL_0[0], sizeof(mmSPI_PS_INPUT_CNTL_0)/sizeof(mmSPI_PS_INPUT_CNTL_0[0]), 0, 0 }, + { "mmSPI_PS_INPUT_CNTL_1", REG_MMIO, 0x0192, 1, &mmSPI_PS_INPUT_CNTL_1[0], sizeof(mmSPI_PS_INPUT_CNTL_1)/sizeof(mmSPI_PS_INPUT_CNTL_1[0]), 0, 0 }, + { "mmSPI_PS_INPUT_CNTL_2", REG_MMIO, 0x0193, 1, &mmSPI_PS_INPUT_CNTL_2[0], sizeof(mmSPI_PS_INPUT_CNTL_2)/sizeof(mmSPI_PS_INPUT_CNTL_2[0]), 0, 0 }, + { "mmSPI_PS_INPUT_CNTL_3", REG_MMIO, 0x0194, 1, &mmSPI_PS_INPUT_CNTL_3[0], sizeof(mmSPI_PS_INPUT_CNTL_3)/sizeof(mmSPI_PS_INPUT_CNTL_3[0]), 0, 0 }, + { "mmSPI_PS_INPUT_CNTL_4", REG_MMIO, 0x0195, 1, &mmSPI_PS_INPUT_CNTL_4[0], sizeof(mmSPI_PS_INPUT_CNTL_4)/sizeof(mmSPI_PS_INPUT_CNTL_4[0]), 0, 0 }, + { "mmSPI_PS_INPUT_CNTL_5", REG_MMIO, 0x0196, 1, &mmSPI_PS_INPUT_CNTL_5[0], sizeof(mmSPI_PS_INPUT_CNTL_5)/sizeof(mmSPI_PS_INPUT_CNTL_5[0]), 0, 0 }, + { "mmSPI_PS_INPUT_CNTL_6", REG_MMIO, 0x0197, 1, &mmSPI_PS_INPUT_CNTL_6[0], sizeof(mmSPI_PS_INPUT_CNTL_6)/sizeof(mmSPI_PS_INPUT_CNTL_6[0]), 0, 0 }, + { "mmSPI_PS_INPUT_CNTL_7", REG_MMIO, 0x0198, 1, &mmSPI_PS_INPUT_CNTL_7[0], sizeof(mmSPI_PS_INPUT_CNTL_7)/sizeof(mmSPI_PS_INPUT_CNTL_7[0]), 0, 0 }, + { "mmSPI_PS_INPUT_CNTL_8", REG_MMIO, 0x0199, 1, &mmSPI_PS_INPUT_CNTL_8[0], sizeof(mmSPI_PS_INPUT_CNTL_8)/sizeof(mmSPI_PS_INPUT_CNTL_8[0]), 0, 0 }, + { "mmSPI_PS_INPUT_CNTL_9", REG_MMIO, 0x019a, 1, &mmSPI_PS_INPUT_CNTL_9[0], sizeof(mmSPI_PS_INPUT_CNTL_9)/sizeof(mmSPI_PS_INPUT_CNTL_9[0]), 0, 0 }, + { "mmSPI_PS_INPUT_CNTL_10", REG_MMIO, 0x019b, 1, &mmSPI_PS_INPUT_CNTL_10[0], sizeof(mmSPI_PS_INPUT_CNTL_10)/sizeof(mmSPI_PS_INPUT_CNTL_10[0]), 0, 0 }, + { "mmSPI_PS_INPUT_CNTL_11", REG_MMIO, 0x019c, 1, &mmSPI_PS_INPUT_CNTL_11[0], sizeof(mmSPI_PS_INPUT_CNTL_11)/sizeof(mmSPI_PS_INPUT_CNTL_11[0]), 0, 0 }, + { "mmSPI_PS_INPUT_CNTL_12", REG_MMIO, 0x019d, 1, &mmSPI_PS_INPUT_CNTL_12[0], sizeof(mmSPI_PS_INPUT_CNTL_12)/sizeof(mmSPI_PS_INPUT_CNTL_12[0]), 0, 0 }, + { "mmSPI_PS_INPUT_CNTL_13", REG_MMIO, 0x019e, 1, &mmSPI_PS_INPUT_CNTL_13[0], sizeof(mmSPI_PS_INPUT_CNTL_13)/sizeof(mmSPI_PS_INPUT_CNTL_13[0]), 0, 0 }, + { "mmSPI_PS_INPUT_CNTL_14", REG_MMIO, 0x019f, 1, &mmSPI_PS_INPUT_CNTL_14[0], sizeof(mmSPI_PS_INPUT_CNTL_14)/sizeof(mmSPI_PS_INPUT_CNTL_14[0]), 0, 0 }, + { "mmSPI_PS_INPUT_CNTL_15", REG_MMIO, 0x01a0, 1, &mmSPI_PS_INPUT_CNTL_15[0], sizeof(mmSPI_PS_INPUT_CNTL_15)/sizeof(mmSPI_PS_INPUT_CNTL_15[0]), 0, 0 }, + { "mmSPI_PS_INPUT_CNTL_16", REG_MMIO, 0x01a1, 1, &mmSPI_PS_INPUT_CNTL_16[0], sizeof(mmSPI_PS_INPUT_CNTL_16)/sizeof(mmSPI_PS_INPUT_CNTL_16[0]), 0, 0 }, + { "mmSPI_PS_INPUT_CNTL_17", REG_MMIO, 0x01a2, 1, &mmSPI_PS_INPUT_CNTL_17[0], sizeof(mmSPI_PS_INPUT_CNTL_17)/sizeof(mmSPI_PS_INPUT_CNTL_17[0]), 0, 0 }, + { "mmSPI_PS_INPUT_CNTL_18", REG_MMIO, 0x01a3, 1, &mmSPI_PS_INPUT_CNTL_18[0], sizeof(mmSPI_PS_INPUT_CNTL_18)/sizeof(mmSPI_PS_INPUT_CNTL_18[0]), 0, 0 }, + { "mmSPI_PS_INPUT_CNTL_19", REG_MMIO, 0x01a4, 1, &mmSPI_PS_INPUT_CNTL_19[0], sizeof(mmSPI_PS_INPUT_CNTL_19)/sizeof(mmSPI_PS_INPUT_CNTL_19[0]), 0, 0 }, + { "mmSPI_PS_INPUT_CNTL_20", REG_MMIO, 0x01a5, 1, &mmSPI_PS_INPUT_CNTL_20[0], sizeof(mmSPI_PS_INPUT_CNTL_20)/sizeof(mmSPI_PS_INPUT_CNTL_20[0]), 0, 0 }, + { "mmSPI_PS_INPUT_CNTL_21", REG_MMIO, 0x01a6, 1, &mmSPI_PS_INPUT_CNTL_21[0], sizeof(mmSPI_PS_INPUT_CNTL_21)/sizeof(mmSPI_PS_INPUT_CNTL_21[0]), 0, 0 }, + { "mmSPI_PS_INPUT_CNTL_22", REG_MMIO, 0x01a7, 1, &mmSPI_PS_INPUT_CNTL_22[0], sizeof(mmSPI_PS_INPUT_CNTL_22)/sizeof(mmSPI_PS_INPUT_CNTL_22[0]), 0, 0 }, + { "mmSPI_PS_INPUT_CNTL_23", REG_MMIO, 0x01a8, 1, &mmSPI_PS_INPUT_CNTL_23[0], sizeof(mmSPI_PS_INPUT_CNTL_23)/sizeof(mmSPI_PS_INPUT_CNTL_23[0]), 0, 0 }, + { "mmSPI_PS_INPUT_CNTL_24", REG_MMIO, 0x01a9, 1, &mmSPI_PS_INPUT_CNTL_24[0], sizeof(mmSPI_PS_INPUT_CNTL_24)/sizeof(mmSPI_PS_INPUT_CNTL_24[0]), 0, 0 }, + { "mmSPI_PS_INPUT_CNTL_25", REG_MMIO, 0x01aa, 1, &mmSPI_PS_INPUT_CNTL_25[0], sizeof(mmSPI_PS_INPUT_CNTL_25)/sizeof(mmSPI_PS_INPUT_CNTL_25[0]), 0, 0 }, + { "mmSPI_PS_INPUT_CNTL_26", REG_MMIO, 0x01ab, 1, &mmSPI_PS_INPUT_CNTL_26[0], sizeof(mmSPI_PS_INPUT_CNTL_26)/sizeof(mmSPI_PS_INPUT_CNTL_26[0]), 0, 0 }, + { "mmSPI_PS_INPUT_CNTL_27", REG_MMIO, 0x01ac, 1, &mmSPI_PS_INPUT_CNTL_27[0], sizeof(mmSPI_PS_INPUT_CNTL_27)/sizeof(mmSPI_PS_INPUT_CNTL_27[0]), 0, 0 }, + { "mmSPI_PS_INPUT_CNTL_28", REG_MMIO, 0x01ad, 1, &mmSPI_PS_INPUT_CNTL_28[0], sizeof(mmSPI_PS_INPUT_CNTL_28)/sizeof(mmSPI_PS_INPUT_CNTL_28[0]), 0, 0 }, + { "mmSPI_PS_INPUT_CNTL_29", REG_MMIO, 0x01ae, 1, &mmSPI_PS_INPUT_CNTL_29[0], sizeof(mmSPI_PS_INPUT_CNTL_29)/sizeof(mmSPI_PS_INPUT_CNTL_29[0]), 0, 0 }, + { "mmSPI_PS_INPUT_CNTL_30", REG_MMIO, 0x01af, 1, &mmSPI_PS_INPUT_CNTL_30[0], sizeof(mmSPI_PS_INPUT_CNTL_30)/sizeof(mmSPI_PS_INPUT_CNTL_30[0]), 0, 0 }, + { "mmSPI_PS_INPUT_CNTL_31", REG_MMIO, 0x01b0, 1, &mmSPI_PS_INPUT_CNTL_31[0], sizeof(mmSPI_PS_INPUT_CNTL_31)/sizeof(mmSPI_PS_INPUT_CNTL_31[0]), 0, 0 }, + { "mmSPI_VS_OUT_CONFIG", REG_MMIO, 0x01b1, 1, &mmSPI_VS_OUT_CONFIG[0], sizeof(mmSPI_VS_OUT_CONFIG)/sizeof(mmSPI_VS_OUT_CONFIG[0]), 0, 0 }, + { "mmSPI_PS_INPUT_ENA", REG_MMIO, 0x01b3, 1, &mmSPI_PS_INPUT_ENA[0], sizeof(mmSPI_PS_INPUT_ENA)/sizeof(mmSPI_PS_INPUT_ENA[0]), 0, 0 }, + { "mmSPI_PS_INPUT_ADDR", REG_MMIO, 0x01b4, 1, &mmSPI_PS_INPUT_ADDR[0], sizeof(mmSPI_PS_INPUT_ADDR)/sizeof(mmSPI_PS_INPUT_ADDR[0]), 0, 0 }, + { "mmSPI_INTERP_CONTROL_0", REG_MMIO, 0x01b5, 1, &mmSPI_INTERP_CONTROL_0[0], sizeof(mmSPI_INTERP_CONTROL_0)/sizeof(mmSPI_INTERP_CONTROL_0[0]), 0, 0 }, + { "mmSPI_PS_IN_CONTROL", REG_MMIO, 0x01b6, 1, &mmSPI_PS_IN_CONTROL[0], sizeof(mmSPI_PS_IN_CONTROL)/sizeof(mmSPI_PS_IN_CONTROL[0]), 0, 0 }, + { "mmSPI_BARYC_CNTL", REG_MMIO, 0x01b8, 1, &mmSPI_BARYC_CNTL[0], sizeof(mmSPI_BARYC_CNTL)/sizeof(mmSPI_BARYC_CNTL[0]), 0, 0 }, + { "mmSPI_TMPRING_SIZE", REG_MMIO, 0x01ba, 1, &mmSPI_TMPRING_SIZE[0], sizeof(mmSPI_TMPRING_SIZE)/sizeof(mmSPI_TMPRING_SIZE[0]), 0, 0 }, + { "mmSPI_SHADER_POS_FORMAT", REG_MMIO, 0x01c3, 1, &mmSPI_SHADER_POS_FORMAT[0], sizeof(mmSPI_SHADER_POS_FORMAT)/sizeof(mmSPI_SHADER_POS_FORMAT[0]), 0, 0 }, + { "mmSPI_SHADER_Z_FORMAT", REG_MMIO, 0x01c4, 1, &mmSPI_SHADER_Z_FORMAT[0], sizeof(mmSPI_SHADER_Z_FORMAT)/sizeof(mmSPI_SHADER_Z_FORMAT[0]), 0, 0 }, + { "mmSPI_SHADER_COL_FORMAT", REG_MMIO, 0x01c5, 1, &mmSPI_SHADER_COL_FORMAT[0], sizeof(mmSPI_SHADER_COL_FORMAT)/sizeof(mmSPI_SHADER_COL_FORMAT[0]), 0, 0 }, + { "mmSX_PS_DOWNCONVERT", REG_MMIO, 0x01d5, 1, &mmSX_PS_DOWNCONVERT[0], sizeof(mmSX_PS_DOWNCONVERT)/sizeof(mmSX_PS_DOWNCONVERT[0]), 0, 0 }, + { "mmSX_BLEND_OPT_EPSILON", REG_MMIO, 0x01d6, 1, &mmSX_BLEND_OPT_EPSILON[0], sizeof(mmSX_BLEND_OPT_EPSILON)/sizeof(mmSX_BLEND_OPT_EPSILON[0]), 0, 0 }, + { "mmSX_BLEND_OPT_CONTROL", REG_MMIO, 0x01d7, 1, &mmSX_BLEND_OPT_CONTROL[0], sizeof(mmSX_BLEND_OPT_CONTROL)/sizeof(mmSX_BLEND_OPT_CONTROL[0]), 0, 0 }, + { "mmSX_MRT0_BLEND_OPT", REG_MMIO, 0x01d8, 1, &mmSX_MRT0_BLEND_OPT[0], sizeof(mmSX_MRT0_BLEND_OPT)/sizeof(mmSX_MRT0_BLEND_OPT[0]), 0, 0 }, + { "mmSX_MRT1_BLEND_OPT", REG_MMIO, 0x01d9, 1, &mmSX_MRT1_BLEND_OPT[0], sizeof(mmSX_MRT1_BLEND_OPT)/sizeof(mmSX_MRT1_BLEND_OPT[0]), 0, 0 }, + { "mmSX_MRT2_BLEND_OPT", REG_MMIO, 0x01da, 1, &mmSX_MRT2_BLEND_OPT[0], sizeof(mmSX_MRT2_BLEND_OPT)/sizeof(mmSX_MRT2_BLEND_OPT[0]), 0, 0 }, + { "mmSX_MRT3_BLEND_OPT", REG_MMIO, 0x01db, 1, &mmSX_MRT3_BLEND_OPT[0], sizeof(mmSX_MRT3_BLEND_OPT)/sizeof(mmSX_MRT3_BLEND_OPT[0]), 0, 0 }, + { "mmSX_MRT4_BLEND_OPT", REG_MMIO, 0x01dc, 1, &mmSX_MRT4_BLEND_OPT[0], sizeof(mmSX_MRT4_BLEND_OPT)/sizeof(mmSX_MRT4_BLEND_OPT[0]), 0, 0 }, + { "mmSX_MRT5_BLEND_OPT", REG_MMIO, 0x01dd, 1, &mmSX_MRT5_BLEND_OPT[0], sizeof(mmSX_MRT5_BLEND_OPT)/sizeof(mmSX_MRT5_BLEND_OPT[0]), 0, 0 }, + { "mmSX_MRT6_BLEND_OPT", REG_MMIO, 0x01de, 1, &mmSX_MRT6_BLEND_OPT[0], sizeof(mmSX_MRT6_BLEND_OPT)/sizeof(mmSX_MRT6_BLEND_OPT[0]), 0, 0 }, + { "mmSX_MRT7_BLEND_OPT", REG_MMIO, 0x01df, 1, &mmSX_MRT7_BLEND_OPT[0], sizeof(mmSX_MRT7_BLEND_OPT)/sizeof(mmSX_MRT7_BLEND_OPT[0]), 0, 0 }, + { "mmCB_BLEND0_CONTROL", REG_MMIO, 0x01e0, 1, &mmCB_BLEND0_CONTROL[0], sizeof(mmCB_BLEND0_CONTROL)/sizeof(mmCB_BLEND0_CONTROL[0]), 0, 0 }, + { "mmCB_BLEND1_CONTROL", REG_MMIO, 0x01e1, 1, &mmCB_BLEND1_CONTROL[0], sizeof(mmCB_BLEND1_CONTROL)/sizeof(mmCB_BLEND1_CONTROL[0]), 0, 0 }, + { "mmCB_BLEND2_CONTROL", REG_MMIO, 0x01e2, 1, &mmCB_BLEND2_CONTROL[0], sizeof(mmCB_BLEND2_CONTROL)/sizeof(mmCB_BLEND2_CONTROL[0]), 0, 0 }, + { "mmCB_BLEND3_CONTROL", REG_MMIO, 0x01e3, 1, &mmCB_BLEND3_CONTROL[0], sizeof(mmCB_BLEND3_CONTROL)/sizeof(mmCB_BLEND3_CONTROL[0]), 0, 0 }, + { "mmCB_BLEND4_CONTROL", REG_MMIO, 0x01e4, 1, &mmCB_BLEND4_CONTROL[0], sizeof(mmCB_BLEND4_CONTROL)/sizeof(mmCB_BLEND4_CONTROL[0]), 0, 0 }, + { "mmCB_BLEND5_CONTROL", REG_MMIO, 0x01e5, 1, &mmCB_BLEND5_CONTROL[0], sizeof(mmCB_BLEND5_CONTROL)/sizeof(mmCB_BLEND5_CONTROL[0]), 0, 0 }, + { "mmCB_BLEND6_CONTROL", REG_MMIO, 0x01e6, 1, &mmCB_BLEND6_CONTROL[0], sizeof(mmCB_BLEND6_CONTROL)/sizeof(mmCB_BLEND6_CONTROL[0]), 0, 0 }, + { "mmCB_BLEND7_CONTROL", REG_MMIO, 0x01e7, 1, &mmCB_BLEND7_CONTROL[0], sizeof(mmCB_BLEND7_CONTROL)/sizeof(mmCB_BLEND7_CONTROL[0]), 0, 0 }, + { "mmCB_MRT0_EPITCH", REG_MMIO, 0x01e8, 1, &mmCB_MRT0_EPITCH[0], sizeof(mmCB_MRT0_EPITCH)/sizeof(mmCB_MRT0_EPITCH[0]), 0, 0 }, + { "mmCB_MRT1_EPITCH", REG_MMIO, 0x01e9, 1, &mmCB_MRT1_EPITCH[0], sizeof(mmCB_MRT1_EPITCH)/sizeof(mmCB_MRT1_EPITCH[0]), 0, 0 }, + { "mmCB_MRT2_EPITCH", REG_MMIO, 0x01ea, 1, &mmCB_MRT2_EPITCH[0], sizeof(mmCB_MRT2_EPITCH)/sizeof(mmCB_MRT2_EPITCH[0]), 0, 0 }, + { "mmCB_MRT3_EPITCH", REG_MMIO, 0x01eb, 1, &mmCB_MRT3_EPITCH[0], sizeof(mmCB_MRT3_EPITCH)/sizeof(mmCB_MRT3_EPITCH[0]), 0, 0 }, + { "mmCB_MRT4_EPITCH", REG_MMIO, 0x01ec, 1, &mmCB_MRT4_EPITCH[0], sizeof(mmCB_MRT4_EPITCH)/sizeof(mmCB_MRT4_EPITCH[0]), 0, 0 }, + { "mmCB_MRT5_EPITCH", REG_MMIO, 0x01ed, 1, &mmCB_MRT5_EPITCH[0], sizeof(mmCB_MRT5_EPITCH)/sizeof(mmCB_MRT5_EPITCH[0]), 0, 0 }, + { "mmCB_MRT6_EPITCH", REG_MMIO, 0x01ee, 1, &mmCB_MRT6_EPITCH[0], sizeof(mmCB_MRT6_EPITCH)/sizeof(mmCB_MRT6_EPITCH[0]), 0, 0 }, + { "mmCB_MRT7_EPITCH", REG_MMIO, 0x01ef, 1, &mmCB_MRT7_EPITCH[0], sizeof(mmCB_MRT7_EPITCH)/sizeof(mmCB_MRT7_EPITCH[0]), 0, 0 }, + { "mmCS_COPY_STATE", REG_MMIO, 0x01f3, 1, &mmCS_COPY_STATE[0], sizeof(mmCS_COPY_STATE)/sizeof(mmCS_COPY_STATE[0]), 0, 0 }, + { "mmGFX_COPY_STATE", REG_MMIO, 0x01f4, 1, &mmGFX_COPY_STATE[0], sizeof(mmGFX_COPY_STATE)/sizeof(mmGFX_COPY_STATE[0]), 0, 0 }, + { "mmPA_CL_POINT_X_RAD", REG_MMIO, 0x01f5, 1, &mmPA_CL_POINT_X_RAD[0], sizeof(mmPA_CL_POINT_X_RAD)/sizeof(mmPA_CL_POINT_X_RAD[0]), 0, 0 }, + { "mmPA_CL_POINT_Y_RAD", REG_MMIO, 0x01f6, 1, &mmPA_CL_POINT_Y_RAD[0], sizeof(mmPA_CL_POINT_Y_RAD)/sizeof(mmPA_CL_POINT_Y_RAD[0]), 0, 0 }, + { "mmPA_CL_POINT_SIZE", REG_MMIO, 0x01f7, 1, &mmPA_CL_POINT_SIZE[0], sizeof(mmPA_CL_POINT_SIZE)/sizeof(mmPA_CL_POINT_SIZE[0]), 0, 0 }, + { "mmPA_CL_POINT_CULL_RAD", REG_MMIO, 0x01f8, 1, &mmPA_CL_POINT_CULL_RAD[0], sizeof(mmPA_CL_POINT_CULL_RAD)/sizeof(mmPA_CL_POINT_CULL_RAD[0]), 0, 0 }, + { "mmVGT_DMA_BASE_HI", REG_MMIO, 0x01f9, 1, &mmVGT_DMA_BASE_HI[0], sizeof(mmVGT_DMA_BASE_HI)/sizeof(mmVGT_DMA_BASE_HI[0]), 0, 0 }, + { "mmVGT_DMA_BASE", REG_MMIO, 0x01fa, 1, &mmVGT_DMA_BASE[0], sizeof(mmVGT_DMA_BASE)/sizeof(mmVGT_DMA_BASE[0]), 0, 0 }, + { "mmVGT_DRAW_INITIATOR", REG_MMIO, 0x01fc, 1, &mmVGT_DRAW_INITIATOR[0], sizeof(mmVGT_DRAW_INITIATOR)/sizeof(mmVGT_DRAW_INITIATOR[0]), 0, 0 }, + { "mmVGT_IMMED_DATA", REG_MMIO, 0x01fd, 1, &mmVGT_IMMED_DATA[0], sizeof(mmVGT_IMMED_DATA)/sizeof(mmVGT_IMMED_DATA[0]), 0, 0 }, + { "mmVGT_EVENT_ADDRESS_REG", REG_MMIO, 0x01fe, 1, &mmVGT_EVENT_ADDRESS_REG[0], sizeof(mmVGT_EVENT_ADDRESS_REG)/sizeof(mmVGT_EVENT_ADDRESS_REG[0]), 0, 0 }, + { "mmDB_DEPTH_CONTROL", REG_MMIO, 0x0200, 1, &mmDB_DEPTH_CONTROL[0], sizeof(mmDB_DEPTH_CONTROL)/sizeof(mmDB_DEPTH_CONTROL[0]), 0, 0 }, + { "mmDB_EQAA", REG_MMIO, 0x0201, 1, &mmDB_EQAA[0], sizeof(mmDB_EQAA)/sizeof(mmDB_EQAA[0]), 0, 0 }, + { "mmCB_COLOR_CONTROL", REG_MMIO, 0x0202, 1, &mmCB_COLOR_CONTROL[0], sizeof(mmCB_COLOR_CONTROL)/sizeof(mmCB_COLOR_CONTROL[0]), 0, 0 }, + { "mmDB_SHADER_CONTROL", REG_MMIO, 0x0203, 1, &mmDB_SHADER_CONTROL[0], sizeof(mmDB_SHADER_CONTROL)/sizeof(mmDB_SHADER_CONTROL[0]), 0, 0 }, + { "mmPA_CL_CLIP_CNTL", REG_MMIO, 0x0204, 1, &mmPA_CL_CLIP_CNTL[0], sizeof(mmPA_CL_CLIP_CNTL)/sizeof(mmPA_CL_CLIP_CNTL[0]), 0, 0 }, + { "mmPA_SU_SC_MODE_CNTL", REG_MMIO, 0x0205, 1, &mmPA_SU_SC_MODE_CNTL[0], sizeof(mmPA_SU_SC_MODE_CNTL)/sizeof(mmPA_SU_SC_MODE_CNTL[0]), 0, 0 }, + { "mmPA_CL_VTE_CNTL", REG_MMIO, 0x0206, 1, &mmPA_CL_VTE_CNTL[0], sizeof(mmPA_CL_VTE_CNTL)/sizeof(mmPA_CL_VTE_CNTL[0]), 0, 0 }, + { "mmPA_CL_VS_OUT_CNTL", REG_MMIO, 0x0207, 1, &mmPA_CL_VS_OUT_CNTL[0], sizeof(mmPA_CL_VS_OUT_CNTL)/sizeof(mmPA_CL_VS_OUT_CNTL[0]), 0, 0 }, + { "mmPA_CL_NANINF_CNTL", REG_MMIO, 0x0208, 1, &mmPA_CL_NANINF_CNTL[0], sizeof(mmPA_CL_NANINF_CNTL)/sizeof(mmPA_CL_NANINF_CNTL[0]), 0, 0 }, + { "mmPA_SU_LINE_STIPPLE_CNTL", REG_MMIO, 0x0209, 1, &mmPA_SU_LINE_STIPPLE_CNTL[0], sizeof(mmPA_SU_LINE_STIPPLE_CNTL)/sizeof(mmPA_SU_LINE_STIPPLE_CNTL[0]), 0, 0 }, + { "mmPA_SU_LINE_STIPPLE_SCALE", REG_MMIO, 0x020a, 1, &mmPA_SU_LINE_STIPPLE_SCALE[0], sizeof(mmPA_SU_LINE_STIPPLE_SCALE)/sizeof(mmPA_SU_LINE_STIPPLE_SCALE[0]), 0, 0 }, + { "mmPA_SU_PRIM_FILTER_CNTL", REG_MMIO, 0x020b, 1, &mmPA_SU_PRIM_FILTER_CNTL[0], sizeof(mmPA_SU_PRIM_FILTER_CNTL)/sizeof(mmPA_SU_PRIM_FILTER_CNTL[0]), 0, 0 }, + { "mmPA_SU_SMALL_PRIM_FILTER_CNTL", REG_MMIO, 0x020c, 1, &mmPA_SU_SMALL_PRIM_FILTER_CNTL[0], sizeof(mmPA_SU_SMALL_PRIM_FILTER_CNTL)/sizeof(mmPA_SU_SMALL_PRIM_FILTER_CNTL[0]), 0, 0 }, + { "mmPA_CL_OBJPRIM_ID_CNTL", REG_MMIO, 0x020d, 1, &mmPA_CL_OBJPRIM_ID_CNTL[0], sizeof(mmPA_CL_OBJPRIM_ID_CNTL)/sizeof(mmPA_CL_OBJPRIM_ID_CNTL[0]), 0, 0 }, + { "mmPA_CL_NGG_CNTL", REG_MMIO, 0x020e, 1, &mmPA_CL_NGG_CNTL[0], sizeof(mmPA_CL_NGG_CNTL)/sizeof(mmPA_CL_NGG_CNTL[0]), 0, 0 }, + { "mmPA_SU_OVER_RASTERIZATION_CNTL", REG_MMIO, 0x020f, 1, &mmPA_SU_OVER_RASTERIZATION_CNTL[0], sizeof(mmPA_SU_OVER_RASTERIZATION_CNTL)/sizeof(mmPA_SU_OVER_RASTERIZATION_CNTL[0]), 0, 0 }, + { "mmPA_SU_POINT_SIZE", REG_MMIO, 0x0280, 1, &mmPA_SU_POINT_SIZE[0], sizeof(mmPA_SU_POINT_SIZE)/sizeof(mmPA_SU_POINT_SIZE[0]), 0, 0 }, + { "mmPA_SU_POINT_MINMAX", REG_MMIO, 0x0281, 1, &mmPA_SU_POINT_MINMAX[0], sizeof(mmPA_SU_POINT_MINMAX)/sizeof(mmPA_SU_POINT_MINMAX[0]), 0, 0 }, + { "mmPA_SU_LINE_CNTL", REG_MMIO, 0x0282, 1, &mmPA_SU_LINE_CNTL[0], sizeof(mmPA_SU_LINE_CNTL)/sizeof(mmPA_SU_LINE_CNTL[0]), 0, 0 }, + { "mmPA_SC_LINE_STIPPLE", REG_MMIO, 0x0283, 1, &mmPA_SC_LINE_STIPPLE[0], sizeof(mmPA_SC_LINE_STIPPLE)/sizeof(mmPA_SC_LINE_STIPPLE[0]), 0, 0 }, + { "mmVGT_OUTPUT_PATH_CNTL", REG_MMIO, 0x0284, 1, &mmVGT_OUTPUT_PATH_CNTL[0], sizeof(mmVGT_OUTPUT_PATH_CNTL)/sizeof(mmVGT_OUTPUT_PATH_CNTL[0]), 0, 0 }, + { "mmVGT_HOS_CNTL", REG_MMIO, 0x0285, 1, &mmVGT_HOS_CNTL[0], sizeof(mmVGT_HOS_CNTL)/sizeof(mmVGT_HOS_CNTL[0]), 0, 0 }, + { "mmVGT_HOS_MAX_TESS_LEVEL", REG_MMIO, 0x0286, 1, &mmVGT_HOS_MAX_TESS_LEVEL[0], sizeof(mmVGT_HOS_MAX_TESS_LEVEL)/sizeof(mmVGT_HOS_MAX_TESS_LEVEL[0]), 0, 0 }, + { "mmVGT_HOS_MIN_TESS_LEVEL", REG_MMIO, 0x0287, 1, &mmVGT_HOS_MIN_TESS_LEVEL[0], sizeof(mmVGT_HOS_MIN_TESS_LEVEL)/sizeof(mmVGT_HOS_MIN_TESS_LEVEL[0]), 0, 0 }, + { "mmVGT_HOS_REUSE_DEPTH", REG_MMIO, 0x0288, 1, &mmVGT_HOS_REUSE_DEPTH[0], sizeof(mmVGT_HOS_REUSE_DEPTH)/sizeof(mmVGT_HOS_REUSE_DEPTH[0]), 0, 0 }, + { "mmVGT_GROUP_PRIM_TYPE", REG_MMIO, 0x0289, 1, &mmVGT_GROUP_PRIM_TYPE[0], sizeof(mmVGT_GROUP_PRIM_TYPE)/sizeof(mmVGT_GROUP_PRIM_TYPE[0]), 0, 0 }, + { "mmVGT_GROUP_FIRST_DECR", REG_MMIO, 0x028a, 1, &mmVGT_GROUP_FIRST_DECR[0], sizeof(mmVGT_GROUP_FIRST_DECR)/sizeof(mmVGT_GROUP_FIRST_DECR[0]), 0, 0 }, + { "mmVGT_GROUP_DECR", REG_MMIO, 0x028b, 1, &mmVGT_GROUP_DECR[0], sizeof(mmVGT_GROUP_DECR)/sizeof(mmVGT_GROUP_DECR[0]), 0, 0 }, + { "mmVGT_GROUP_VECT_0_CNTL", REG_MMIO, 0x028c, 1, &mmVGT_GROUP_VECT_0_CNTL[0], sizeof(mmVGT_GROUP_VECT_0_CNTL)/sizeof(mmVGT_GROUP_VECT_0_CNTL[0]), 0, 0 }, + { "mmVGT_GROUP_VECT_1_CNTL", REG_MMIO, 0x028d, 1, &mmVGT_GROUP_VECT_1_CNTL[0], sizeof(mmVGT_GROUP_VECT_1_CNTL)/sizeof(mmVGT_GROUP_VECT_1_CNTL[0]), 0, 0 }, + { "mmVGT_GROUP_VECT_0_FMT_CNTL", REG_MMIO, 0x028e, 1, &mmVGT_GROUP_VECT_0_FMT_CNTL[0], sizeof(mmVGT_GROUP_VECT_0_FMT_CNTL)/sizeof(mmVGT_GROUP_VECT_0_FMT_CNTL[0]), 0, 0 }, + { "mmVGT_GROUP_VECT_1_FMT_CNTL", REG_MMIO, 0x028f, 1, &mmVGT_GROUP_VECT_1_FMT_CNTL[0], sizeof(mmVGT_GROUP_VECT_1_FMT_CNTL)/sizeof(mmVGT_GROUP_VECT_1_FMT_CNTL[0]), 0, 0 }, + { "mmVGT_GS_MODE", REG_MMIO, 0x0290, 1, &mmVGT_GS_MODE[0], sizeof(mmVGT_GS_MODE)/sizeof(mmVGT_GS_MODE[0]), 0, 0 }, + { "mmVGT_GS_ONCHIP_CNTL", REG_MMIO, 0x0291, 1, &mmVGT_GS_ONCHIP_CNTL[0], sizeof(mmVGT_GS_ONCHIP_CNTL)/sizeof(mmVGT_GS_ONCHIP_CNTL[0]), 0, 0 }, + { "mmPA_SC_MODE_CNTL_0", REG_MMIO, 0x0292, 1, &mmPA_SC_MODE_CNTL_0[0], sizeof(mmPA_SC_MODE_CNTL_0)/sizeof(mmPA_SC_MODE_CNTL_0[0]), 0, 0 }, + { "mmPA_SC_MODE_CNTL_1", REG_MMIO, 0x0293, 1, &mmPA_SC_MODE_CNTL_1[0], sizeof(mmPA_SC_MODE_CNTL_1)/sizeof(mmPA_SC_MODE_CNTL_1[0]), 0, 0 }, + { "mmVGT_ENHANCE", REG_MMIO, 0x0294, 1, &mmVGT_ENHANCE[0], sizeof(mmVGT_ENHANCE)/sizeof(mmVGT_ENHANCE[0]), 0, 0 }, + { "mmVGT_GS_PER_ES", REG_MMIO, 0x0295, 1, &mmVGT_GS_PER_ES[0], sizeof(mmVGT_GS_PER_ES)/sizeof(mmVGT_GS_PER_ES[0]), 0, 0 }, + { "mmVGT_ES_PER_GS", REG_MMIO, 0x0296, 1, &mmVGT_ES_PER_GS[0], sizeof(mmVGT_ES_PER_GS)/sizeof(mmVGT_ES_PER_GS[0]), 0, 0 }, + { "mmVGT_GS_PER_VS", REG_MMIO, 0x0297, 1, &mmVGT_GS_PER_VS[0], sizeof(mmVGT_GS_PER_VS)/sizeof(mmVGT_GS_PER_VS[0]), 0, 0 }, + { "mmVGT_GSVS_RING_OFFSET_1", REG_MMIO, 0x0298, 1, &mmVGT_GSVS_RING_OFFSET_1[0], sizeof(mmVGT_GSVS_RING_OFFSET_1)/sizeof(mmVGT_GSVS_RING_OFFSET_1[0]), 0, 0 }, + { "mmVGT_GSVS_RING_OFFSET_2", REG_MMIO, 0x0299, 1, &mmVGT_GSVS_RING_OFFSET_2[0], sizeof(mmVGT_GSVS_RING_OFFSET_2)/sizeof(mmVGT_GSVS_RING_OFFSET_2[0]), 0, 0 }, + { "mmVGT_GSVS_RING_OFFSET_3", REG_MMIO, 0x029a, 1, &mmVGT_GSVS_RING_OFFSET_3[0], sizeof(mmVGT_GSVS_RING_OFFSET_3)/sizeof(mmVGT_GSVS_RING_OFFSET_3[0]), 0, 0 }, + { "mmVGT_GS_OUT_PRIM_TYPE", REG_MMIO, 0x029b, 1, &mmVGT_GS_OUT_PRIM_TYPE[0], sizeof(mmVGT_GS_OUT_PRIM_TYPE)/sizeof(mmVGT_GS_OUT_PRIM_TYPE[0]), 0, 0 }, + { "mmIA_ENHANCE", REG_MMIO, 0x029c, 1, &mmIA_ENHANCE[0], sizeof(mmIA_ENHANCE)/sizeof(mmIA_ENHANCE[0]), 0, 0 }, + { "mmVGT_DMA_SIZE", REG_MMIO, 0x029d, 1, &mmVGT_DMA_SIZE[0], sizeof(mmVGT_DMA_SIZE)/sizeof(mmVGT_DMA_SIZE[0]), 0, 0 }, + { "mmVGT_DMA_MAX_SIZE", REG_MMIO, 0x029e, 1, &mmVGT_DMA_MAX_SIZE[0], sizeof(mmVGT_DMA_MAX_SIZE)/sizeof(mmVGT_DMA_MAX_SIZE[0]), 0, 0 }, + { "mmVGT_DMA_INDEX_TYPE", REG_MMIO, 0x029f, 1, &mmVGT_DMA_INDEX_TYPE[0], sizeof(mmVGT_DMA_INDEX_TYPE)/sizeof(mmVGT_DMA_INDEX_TYPE[0]), 0, 0 }, + { "mmWD_ENHANCE", REG_MMIO, 0x02a0, 1, &mmWD_ENHANCE[0], sizeof(mmWD_ENHANCE)/sizeof(mmWD_ENHANCE[0]), 0, 0 }, + { "mmVGT_PRIMITIVEID_EN", REG_MMIO, 0x02a1, 1, &mmVGT_PRIMITIVEID_EN[0], sizeof(mmVGT_PRIMITIVEID_EN)/sizeof(mmVGT_PRIMITIVEID_EN[0]), 0, 0 }, + { "mmVGT_DMA_NUM_INSTANCES", REG_MMIO, 0x02a2, 1, &mmVGT_DMA_NUM_INSTANCES[0], sizeof(mmVGT_DMA_NUM_INSTANCES)/sizeof(mmVGT_DMA_NUM_INSTANCES[0]), 0, 0 }, + { "mmVGT_PRIMITIVEID_RESET", REG_MMIO, 0x02a3, 1, &mmVGT_PRIMITIVEID_RESET[0], sizeof(mmVGT_PRIMITIVEID_RESET)/sizeof(mmVGT_PRIMITIVEID_RESET[0]), 0, 0 }, + { "mmVGT_EVENT_INITIATOR", REG_MMIO, 0x02a4, 1, &mmVGT_EVENT_INITIATOR[0], sizeof(mmVGT_EVENT_INITIATOR)/sizeof(mmVGT_EVENT_INITIATOR[0]), 0, 0 }, + { "mmVGT_GS_MAX_PRIMS_PER_SUBGROUP", REG_MMIO, 0x02a5, 1, &mmVGT_GS_MAX_PRIMS_PER_SUBGROUP[0], sizeof(mmVGT_GS_MAX_PRIMS_PER_SUBGROUP)/sizeof(mmVGT_GS_MAX_PRIMS_PER_SUBGROUP[0]), 0, 0 }, + { "mmVGT_DRAW_PAYLOAD_CNTL", REG_MMIO, 0x02a6, 1, &mmVGT_DRAW_PAYLOAD_CNTL[0], sizeof(mmVGT_DRAW_PAYLOAD_CNTL)/sizeof(mmVGT_DRAW_PAYLOAD_CNTL[0]), 0, 0 }, + { "mmVGT_INDEX_PAYLOAD_CNTL", REG_MMIO, 0x02a7, 1, &mmVGT_INDEX_PAYLOAD_CNTL[0], sizeof(mmVGT_INDEX_PAYLOAD_CNTL)/sizeof(mmVGT_INDEX_PAYLOAD_CNTL[0]), 0, 0 }, + { "mmVGT_INSTANCE_STEP_RATE_0", REG_MMIO, 0x02a8, 1, &mmVGT_INSTANCE_STEP_RATE_0[0], sizeof(mmVGT_INSTANCE_STEP_RATE_0)/sizeof(mmVGT_INSTANCE_STEP_RATE_0[0]), 0, 0 }, + { "mmVGT_INSTANCE_STEP_RATE_1", REG_MMIO, 0x02a9, 1, &mmVGT_INSTANCE_STEP_RATE_1[0], sizeof(mmVGT_INSTANCE_STEP_RATE_1)/sizeof(mmVGT_INSTANCE_STEP_RATE_1[0]), 0, 0 }, + { "mmVGT_ESGS_RING_ITEMSIZE", REG_MMIO, 0x02ab, 1, &mmVGT_ESGS_RING_ITEMSIZE[0], sizeof(mmVGT_ESGS_RING_ITEMSIZE)/sizeof(mmVGT_ESGS_RING_ITEMSIZE[0]), 0, 0 }, + { "mmVGT_GSVS_RING_ITEMSIZE", REG_MMIO, 0x02ac, 1, &mmVGT_GSVS_RING_ITEMSIZE[0], sizeof(mmVGT_GSVS_RING_ITEMSIZE)/sizeof(mmVGT_GSVS_RING_ITEMSIZE[0]), 0, 0 }, + { "mmVGT_REUSE_OFF", REG_MMIO, 0x02ad, 1, &mmVGT_REUSE_OFF[0], sizeof(mmVGT_REUSE_OFF)/sizeof(mmVGT_REUSE_OFF[0]), 0, 0 }, + { "mmVGT_VTX_CNT_EN", REG_MMIO, 0x02ae, 1, &mmVGT_VTX_CNT_EN[0], sizeof(mmVGT_VTX_CNT_EN)/sizeof(mmVGT_VTX_CNT_EN[0]), 0, 0 }, + { "mmDB_HTILE_SURFACE", REG_MMIO, 0x02af, 1, &mmDB_HTILE_SURFACE[0], sizeof(mmDB_HTILE_SURFACE)/sizeof(mmDB_HTILE_SURFACE[0]), 0, 0 }, + { "mmDB_SRESULTS_COMPARE_STATE0", REG_MMIO, 0x02b0, 1, &mmDB_SRESULTS_COMPARE_STATE0[0], sizeof(mmDB_SRESULTS_COMPARE_STATE0)/sizeof(mmDB_SRESULTS_COMPARE_STATE0[0]), 0, 0 }, + { "mmDB_SRESULTS_COMPARE_STATE1", REG_MMIO, 0x02b1, 1, &mmDB_SRESULTS_COMPARE_STATE1[0], sizeof(mmDB_SRESULTS_COMPARE_STATE1)/sizeof(mmDB_SRESULTS_COMPARE_STATE1[0]), 0, 0 }, + { "mmDB_PRELOAD_CONTROL", REG_MMIO, 0x02b2, 1, &mmDB_PRELOAD_CONTROL[0], sizeof(mmDB_PRELOAD_CONTROL)/sizeof(mmDB_PRELOAD_CONTROL[0]), 0, 0 }, + { "mmVGT_STRMOUT_BUFFER_SIZE_0", REG_MMIO, 0x02b4, 1, &mmVGT_STRMOUT_BUFFER_SIZE_0[0], sizeof(mmVGT_STRMOUT_BUFFER_SIZE_0)/sizeof(mmVGT_STRMOUT_BUFFER_SIZE_0[0]), 0, 0 }, + { "mmVGT_STRMOUT_VTX_STRIDE_0", REG_MMIO, 0x02b5, 1, &mmVGT_STRMOUT_VTX_STRIDE_0[0], sizeof(mmVGT_STRMOUT_VTX_STRIDE_0)/sizeof(mmVGT_STRMOUT_VTX_STRIDE_0[0]), 0, 0 }, + { "mmVGT_STRMOUT_BUFFER_OFFSET_0", REG_MMIO, 0x02b7, 1, &mmVGT_STRMOUT_BUFFER_OFFSET_0[0], sizeof(mmVGT_STRMOUT_BUFFER_OFFSET_0)/sizeof(mmVGT_STRMOUT_BUFFER_OFFSET_0[0]), 0, 0 }, + { "mmVGT_STRMOUT_BUFFER_SIZE_1", REG_MMIO, 0x02b8, 1, &mmVGT_STRMOUT_BUFFER_SIZE_1[0], sizeof(mmVGT_STRMOUT_BUFFER_SIZE_1)/sizeof(mmVGT_STRMOUT_BUFFER_SIZE_1[0]), 0, 0 }, + { "mmVGT_STRMOUT_VTX_STRIDE_1", REG_MMIO, 0x02b9, 1, &mmVGT_STRMOUT_VTX_STRIDE_1[0], sizeof(mmVGT_STRMOUT_VTX_STRIDE_1)/sizeof(mmVGT_STRMOUT_VTX_STRIDE_1[0]), 0, 0 }, + { "mmVGT_STRMOUT_BUFFER_OFFSET_1", REG_MMIO, 0x02bb, 1, &mmVGT_STRMOUT_BUFFER_OFFSET_1[0], sizeof(mmVGT_STRMOUT_BUFFER_OFFSET_1)/sizeof(mmVGT_STRMOUT_BUFFER_OFFSET_1[0]), 0, 0 }, + { "mmVGT_STRMOUT_BUFFER_SIZE_2", REG_MMIO, 0x02bc, 1, &mmVGT_STRMOUT_BUFFER_SIZE_2[0], sizeof(mmVGT_STRMOUT_BUFFER_SIZE_2)/sizeof(mmVGT_STRMOUT_BUFFER_SIZE_2[0]), 0, 0 }, + { "mmVGT_STRMOUT_VTX_STRIDE_2", REG_MMIO, 0x02bd, 1, &mmVGT_STRMOUT_VTX_STRIDE_2[0], sizeof(mmVGT_STRMOUT_VTX_STRIDE_2)/sizeof(mmVGT_STRMOUT_VTX_STRIDE_2[0]), 0, 0 }, + { "mmVGT_STRMOUT_BUFFER_OFFSET_2", REG_MMIO, 0x02bf, 1, &mmVGT_STRMOUT_BUFFER_OFFSET_2[0], sizeof(mmVGT_STRMOUT_BUFFER_OFFSET_2)/sizeof(mmVGT_STRMOUT_BUFFER_OFFSET_2[0]), 0, 0 }, + { "mmVGT_STRMOUT_BUFFER_SIZE_3", REG_MMIO, 0x02c0, 1, &mmVGT_STRMOUT_BUFFER_SIZE_3[0], sizeof(mmVGT_STRMOUT_BUFFER_SIZE_3)/sizeof(mmVGT_STRMOUT_BUFFER_SIZE_3[0]), 0, 0 }, + { "mmVGT_STRMOUT_VTX_STRIDE_3", REG_MMIO, 0x02c1, 1, &mmVGT_STRMOUT_VTX_STRIDE_3[0], sizeof(mmVGT_STRMOUT_VTX_STRIDE_3)/sizeof(mmVGT_STRMOUT_VTX_STRIDE_3[0]), 0, 0 }, + { "mmVGT_STRMOUT_BUFFER_OFFSET_3", REG_MMIO, 0x02c3, 1, &mmVGT_STRMOUT_BUFFER_OFFSET_3[0], sizeof(mmVGT_STRMOUT_BUFFER_OFFSET_3)/sizeof(mmVGT_STRMOUT_BUFFER_OFFSET_3[0]), 0, 0 }, + { "mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET", REG_MMIO, 0x02ca, 1, &mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET[0], sizeof(mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET)/sizeof(mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET[0]), 0, 0 }, + { "mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE", REG_MMIO, 0x02cb, 1, &mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE[0], sizeof(mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE)/sizeof(mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE[0]), 0, 0 }, + { "mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE", REG_MMIO, 0x02cc, 1, &mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE[0], sizeof(mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE)/sizeof(mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE[0]), 0, 0 }, + { "mmVGT_GS_MAX_VERT_OUT", REG_MMIO, 0x02ce, 1, &mmVGT_GS_MAX_VERT_OUT[0], sizeof(mmVGT_GS_MAX_VERT_OUT)/sizeof(mmVGT_GS_MAX_VERT_OUT[0]), 0, 0 }, + { "mmVGT_TESS_DISTRIBUTION", REG_MMIO, 0x02d4, 1, &mmVGT_TESS_DISTRIBUTION[0], sizeof(mmVGT_TESS_DISTRIBUTION)/sizeof(mmVGT_TESS_DISTRIBUTION[0]), 0, 0 }, + { "mmVGT_SHADER_STAGES_EN", REG_MMIO, 0x02d5, 1, &mmVGT_SHADER_STAGES_EN[0], sizeof(mmVGT_SHADER_STAGES_EN)/sizeof(mmVGT_SHADER_STAGES_EN[0]), 0, 0 }, + { "mmVGT_LS_HS_CONFIG", REG_MMIO, 0x02d6, 1, &mmVGT_LS_HS_CONFIG[0], sizeof(mmVGT_LS_HS_CONFIG)/sizeof(mmVGT_LS_HS_CONFIG[0]), 0, 0 }, + { "mmVGT_GS_VERT_ITEMSIZE", REG_MMIO, 0x02d7, 1, &mmVGT_GS_VERT_ITEMSIZE[0], sizeof(mmVGT_GS_VERT_ITEMSIZE)/sizeof(mmVGT_GS_VERT_ITEMSIZE[0]), 0, 0 }, + { "mmVGT_GS_VERT_ITEMSIZE_1", REG_MMIO, 0x02d8, 1, &mmVGT_GS_VERT_ITEMSIZE_1[0], sizeof(mmVGT_GS_VERT_ITEMSIZE_1)/sizeof(mmVGT_GS_VERT_ITEMSIZE_1[0]), 0, 0 }, + { "mmVGT_GS_VERT_ITEMSIZE_2", REG_MMIO, 0x02d9, 1, &mmVGT_GS_VERT_ITEMSIZE_2[0], sizeof(mmVGT_GS_VERT_ITEMSIZE_2)/sizeof(mmVGT_GS_VERT_ITEMSIZE_2[0]), 0, 0 }, + { "mmVGT_GS_VERT_ITEMSIZE_3", REG_MMIO, 0x02da, 1, &mmVGT_GS_VERT_ITEMSIZE_3[0], sizeof(mmVGT_GS_VERT_ITEMSIZE_3)/sizeof(mmVGT_GS_VERT_ITEMSIZE_3[0]), 0, 0 }, + { "mmVGT_TF_PARAM", REG_MMIO, 0x02db, 1, &mmVGT_TF_PARAM[0], sizeof(mmVGT_TF_PARAM)/sizeof(mmVGT_TF_PARAM[0]), 0, 0 }, + { "mmDB_ALPHA_TO_MASK", REG_MMIO, 0x02dc, 1, &mmDB_ALPHA_TO_MASK[0], sizeof(mmDB_ALPHA_TO_MASK)/sizeof(mmDB_ALPHA_TO_MASK[0]), 0, 0 }, + { "mmVGT_DISPATCH_DRAW_INDEX", REG_MMIO, 0x02dd, 1, &mmVGT_DISPATCH_DRAW_INDEX[0], sizeof(mmVGT_DISPATCH_DRAW_INDEX)/sizeof(mmVGT_DISPATCH_DRAW_INDEX[0]), 0, 0 }, + { "mmPA_SU_POLY_OFFSET_DB_FMT_CNTL", REG_MMIO, 0x02de, 1, &mmPA_SU_POLY_OFFSET_DB_FMT_CNTL[0], sizeof(mmPA_SU_POLY_OFFSET_DB_FMT_CNTL)/sizeof(mmPA_SU_POLY_OFFSET_DB_FMT_CNTL[0]), 0, 0 }, + { "mmPA_SU_POLY_OFFSET_CLAMP", REG_MMIO, 0x02df, 1, &mmPA_SU_POLY_OFFSET_CLAMP[0], sizeof(mmPA_SU_POLY_OFFSET_CLAMP)/sizeof(mmPA_SU_POLY_OFFSET_CLAMP[0]), 0, 0 }, + { "mmPA_SU_POLY_OFFSET_FRONT_SCALE", REG_MMIO, 0x02e0, 1, &mmPA_SU_POLY_OFFSET_FRONT_SCALE[0], sizeof(mmPA_SU_POLY_OFFSET_FRONT_SCALE)/sizeof(mmPA_SU_POLY_OFFSET_FRONT_SCALE[0]), 0, 0 }, + { "mmPA_SU_POLY_OFFSET_FRONT_OFFSET", REG_MMIO, 0x02e1, 1, &mmPA_SU_POLY_OFFSET_FRONT_OFFSET[0], sizeof(mmPA_SU_POLY_OFFSET_FRONT_OFFSET)/sizeof(mmPA_SU_POLY_OFFSET_FRONT_OFFSET[0]), 0, 0 }, + { "mmPA_SU_POLY_OFFSET_BACK_SCALE", REG_MMIO, 0x02e2, 1, &mmPA_SU_POLY_OFFSET_BACK_SCALE[0], sizeof(mmPA_SU_POLY_OFFSET_BACK_SCALE)/sizeof(mmPA_SU_POLY_OFFSET_BACK_SCALE[0]), 0, 0 }, + { "mmPA_SU_POLY_OFFSET_BACK_OFFSET", REG_MMIO, 0x02e3, 1, &mmPA_SU_POLY_OFFSET_BACK_OFFSET[0], sizeof(mmPA_SU_POLY_OFFSET_BACK_OFFSET)/sizeof(mmPA_SU_POLY_OFFSET_BACK_OFFSET[0]), 0, 0 }, + { "mmVGT_GS_INSTANCE_CNT", REG_MMIO, 0x02e4, 1, &mmVGT_GS_INSTANCE_CNT[0], sizeof(mmVGT_GS_INSTANCE_CNT)/sizeof(mmVGT_GS_INSTANCE_CNT[0]), 0, 0 }, + { "mmVGT_STRMOUT_CONFIG", REG_MMIO, 0x02e5, 1, &mmVGT_STRMOUT_CONFIG[0], sizeof(mmVGT_STRMOUT_CONFIG)/sizeof(mmVGT_STRMOUT_CONFIG[0]), 0, 0 }, + { "mmVGT_STRMOUT_BUFFER_CONFIG", REG_MMIO, 0x02e6, 1, &mmVGT_STRMOUT_BUFFER_CONFIG[0], sizeof(mmVGT_STRMOUT_BUFFER_CONFIG)/sizeof(mmVGT_STRMOUT_BUFFER_CONFIG[0]), 0, 0 }, + { "mmVGT_DMA_EVENT_INITIATOR", REG_MMIO, 0x02e7, 1, &mmVGT_DMA_EVENT_INITIATOR[0], sizeof(mmVGT_DMA_EVENT_INITIATOR)/sizeof(mmVGT_DMA_EVENT_INITIATOR[0]), 0, 0 }, + { "mmPA_SC_CENTROID_PRIORITY_0", REG_MMIO, 0x02f5, 1, &mmPA_SC_CENTROID_PRIORITY_0[0], sizeof(mmPA_SC_CENTROID_PRIORITY_0)/sizeof(mmPA_SC_CENTROID_PRIORITY_0[0]), 0, 0 }, + { "mmPA_SC_CENTROID_PRIORITY_1", REG_MMIO, 0x02f6, 1, &mmPA_SC_CENTROID_PRIORITY_1[0], sizeof(mmPA_SC_CENTROID_PRIORITY_1)/sizeof(mmPA_SC_CENTROID_PRIORITY_1[0]), 0, 0 }, + { "mmPA_SC_LINE_CNTL", REG_MMIO, 0x02f7, 1, &mmPA_SC_LINE_CNTL[0], sizeof(mmPA_SC_LINE_CNTL)/sizeof(mmPA_SC_LINE_CNTL[0]), 0, 0 }, + { "mmPA_SC_AA_CONFIG", REG_MMIO, 0x02f8, 1, &mmPA_SC_AA_CONFIG[0], sizeof(mmPA_SC_AA_CONFIG)/sizeof(mmPA_SC_AA_CONFIG[0]), 0, 0 }, + { "mmPA_SU_VTX_CNTL", REG_MMIO, 0x02f9, 1, &mmPA_SU_VTX_CNTL[0], sizeof(mmPA_SU_VTX_CNTL)/sizeof(mmPA_SU_VTX_CNTL[0]), 0, 0 }, + { "mmPA_CL_GB_VERT_CLIP_ADJ", REG_MMIO, 0x02fa, 1, &mmPA_CL_GB_VERT_CLIP_ADJ[0], sizeof(mmPA_CL_GB_VERT_CLIP_ADJ)/sizeof(mmPA_CL_GB_VERT_CLIP_ADJ[0]), 0, 0 }, + { "mmPA_CL_GB_VERT_DISC_ADJ", REG_MMIO, 0x02fb, 1, &mmPA_CL_GB_VERT_DISC_ADJ[0], sizeof(mmPA_CL_GB_VERT_DISC_ADJ)/sizeof(mmPA_CL_GB_VERT_DISC_ADJ[0]), 0, 0 }, + { "mmPA_CL_GB_HORZ_CLIP_ADJ", REG_MMIO, 0x02fc, 1, &mmPA_CL_GB_HORZ_CLIP_ADJ[0], sizeof(mmPA_CL_GB_HORZ_CLIP_ADJ)/sizeof(mmPA_CL_GB_HORZ_CLIP_ADJ[0]), 0, 0 }, + { "mmPA_CL_GB_HORZ_DISC_ADJ", REG_MMIO, 0x02fd, 1, &mmPA_CL_GB_HORZ_DISC_ADJ[0], sizeof(mmPA_CL_GB_HORZ_DISC_ADJ)/sizeof(mmPA_CL_GB_HORZ_DISC_ADJ[0]), 0, 0 }, + { "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0", REG_MMIO, 0x02fe, 1, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0[0]), 0, 0 }, + { "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1", REG_MMIO, 0x02ff, 1, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1[0]), 0, 0 }, + { "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2", REG_MMIO, 0x0300, 1, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2[0]), 0, 0 }, + { "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3", REG_MMIO, 0x0301, 1, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3[0]), 0, 0 }, + { "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0", REG_MMIO, 0x0302, 1, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0[0]), 0, 0 }, + { "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1", REG_MMIO, 0x0303, 1, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1[0]), 0, 0 }, + { "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2", REG_MMIO, 0x0304, 1, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2[0]), 0, 0 }, + { "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3", REG_MMIO, 0x0305, 1, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3[0]), 0, 0 }, + { "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0", REG_MMIO, 0x0306, 1, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0[0]), 0, 0 }, + { "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1", REG_MMIO, 0x0307, 1, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1[0]), 0, 0 }, + { "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2", REG_MMIO, 0x0308, 1, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2[0]), 0, 0 }, + { "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3", REG_MMIO, 0x0309, 1, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3[0]), 0, 0 }, + { "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0", REG_MMIO, 0x030a, 1, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0[0]), 0, 0 }, + { "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1", REG_MMIO, 0x030b, 1, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1[0]), 0, 0 }, + { "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2", REG_MMIO, 0x030c, 1, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2[0]), 0, 0 }, + { "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3", REG_MMIO, 0x030d, 1, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3[0]), 0, 0 }, + { "mmPA_SC_AA_MASK_X0Y0_X1Y0", REG_MMIO, 0x030e, 1, &mmPA_SC_AA_MASK_X0Y0_X1Y0[0], sizeof(mmPA_SC_AA_MASK_X0Y0_X1Y0)/sizeof(mmPA_SC_AA_MASK_X0Y0_X1Y0[0]), 0, 0 }, + { "mmPA_SC_AA_MASK_X0Y1_X1Y1", REG_MMIO, 0x030f, 1, &mmPA_SC_AA_MASK_X0Y1_X1Y1[0], sizeof(mmPA_SC_AA_MASK_X0Y1_X1Y1)/sizeof(mmPA_SC_AA_MASK_X0Y1_X1Y1[0]), 0, 0 }, + { "mmPA_SC_SHADER_CONTROL", REG_MMIO, 0x0310, 1, &mmPA_SC_SHADER_CONTROL[0], sizeof(mmPA_SC_SHADER_CONTROL)/sizeof(mmPA_SC_SHADER_CONTROL[0]), 0, 0 }, + { "mmPA_SC_BINNER_CNTL_0", REG_MMIO, 0x0311, 1, &mmPA_SC_BINNER_CNTL_0[0], sizeof(mmPA_SC_BINNER_CNTL_0)/sizeof(mmPA_SC_BINNER_CNTL_0[0]), 0, 0 }, + { "mmPA_SC_BINNER_CNTL_1", REG_MMIO, 0x0312, 1, &mmPA_SC_BINNER_CNTL_1[0], sizeof(mmPA_SC_BINNER_CNTL_1)/sizeof(mmPA_SC_BINNER_CNTL_1[0]), 0, 0 }, + { "mmPA_SC_CONSERVATIVE_RASTERIZATION_CNTL", REG_MMIO, 0x0313, 1, &mmPA_SC_CONSERVATIVE_RASTERIZATION_CNTL[0], sizeof(mmPA_SC_CONSERVATIVE_RASTERIZATION_CNTL)/sizeof(mmPA_SC_CONSERVATIVE_RASTERIZATION_CNTL[0]), 0, 0 }, + { "mmPA_SC_NGG_MODE_CNTL", REG_MMIO, 0x0314, 1, &mmPA_SC_NGG_MODE_CNTL[0], sizeof(mmPA_SC_NGG_MODE_CNTL)/sizeof(mmPA_SC_NGG_MODE_CNTL[0]), 0, 0 }, + { "mmVGT_VERTEX_REUSE_BLOCK_CNTL", REG_MMIO, 0x0316, 1, &mmVGT_VERTEX_REUSE_BLOCK_CNTL[0], sizeof(mmVGT_VERTEX_REUSE_BLOCK_CNTL)/sizeof(mmVGT_VERTEX_REUSE_BLOCK_CNTL[0]), 0, 0 }, + { "mmVGT_OUT_DEALLOC_CNTL", REG_MMIO, 0x0317, 1, &mmVGT_OUT_DEALLOC_CNTL[0], sizeof(mmVGT_OUT_DEALLOC_CNTL)/sizeof(mmVGT_OUT_DEALLOC_CNTL[0]), 0, 0 }, + { "mmCB_COLOR0_BASE", REG_MMIO, 0x0318, 1, &mmCB_COLOR0_BASE[0], sizeof(mmCB_COLOR0_BASE)/sizeof(mmCB_COLOR0_BASE[0]), 0, 0 }, + { "mmCB_COLOR0_BASE_EXT", REG_MMIO, 0x0319, 1, &mmCB_COLOR0_BASE_EXT[0], sizeof(mmCB_COLOR0_BASE_EXT)/sizeof(mmCB_COLOR0_BASE_EXT[0]), 0, 0 }, + { "mmCB_COLOR0_ATTRIB2", REG_MMIO, 0x031a, 1, &mmCB_COLOR0_ATTRIB2[0], sizeof(mmCB_COLOR0_ATTRIB2)/sizeof(mmCB_COLOR0_ATTRIB2[0]), 0, 0 }, + { "mmCB_COLOR0_VIEW", REG_MMIO, 0x031b, 1, &mmCB_COLOR0_VIEW[0], sizeof(mmCB_COLOR0_VIEW)/sizeof(mmCB_COLOR0_VIEW[0]), 0, 0 }, + { "mmCB_COLOR0_INFO", REG_MMIO, 0x031c, 1, &mmCB_COLOR0_INFO[0], sizeof(mmCB_COLOR0_INFO)/sizeof(mmCB_COLOR0_INFO[0]), 0, 0 }, + { "mmCB_COLOR0_ATTRIB", REG_MMIO, 0x031d, 1, &mmCB_COLOR0_ATTRIB[0], sizeof(mmCB_COLOR0_ATTRIB)/sizeof(mmCB_COLOR0_ATTRIB[0]), 0, 0 }, + { "mmCB_COLOR0_DCC_CONTROL", REG_MMIO, 0x031e, 1, &mmCB_COLOR0_DCC_CONTROL[0], sizeof(mmCB_COLOR0_DCC_CONTROL)/sizeof(mmCB_COLOR0_DCC_CONTROL[0]), 0, 0 }, + { "mmCB_COLOR0_CMASK", REG_MMIO, 0x031f, 1, &mmCB_COLOR0_CMASK[0], sizeof(mmCB_COLOR0_CMASK)/sizeof(mmCB_COLOR0_CMASK[0]), 0, 0 }, + { "mmCB_COLOR0_CMASK_BASE_EXT", REG_MMIO, 0x0320, 1, &mmCB_COLOR0_CMASK_BASE_EXT[0], sizeof(mmCB_COLOR0_CMASK_BASE_EXT)/sizeof(mmCB_COLOR0_CMASK_BASE_EXT[0]), 0, 0 }, + { "mmCB_COLOR0_FMASK", REG_MMIO, 0x0321, 1, &mmCB_COLOR0_FMASK[0], sizeof(mmCB_COLOR0_FMASK)/sizeof(mmCB_COLOR0_FMASK[0]), 0, 0 }, + { "mmCB_COLOR0_FMASK_BASE_EXT", REG_MMIO, 0x0322, 1, &mmCB_COLOR0_FMASK_BASE_EXT[0], sizeof(mmCB_COLOR0_FMASK_BASE_EXT)/sizeof(mmCB_COLOR0_FMASK_BASE_EXT[0]), 0, 0 }, + { "mmCB_COLOR0_CLEAR_WORD0", REG_MMIO, 0x0323, 1, &mmCB_COLOR0_CLEAR_WORD0[0], sizeof(mmCB_COLOR0_CLEAR_WORD0)/sizeof(mmCB_COLOR0_CLEAR_WORD0[0]), 0, 0 }, + { "mmCB_COLOR0_CLEAR_WORD1", REG_MMIO, 0x0324, 1, &mmCB_COLOR0_CLEAR_WORD1[0], sizeof(mmCB_COLOR0_CLEAR_WORD1)/sizeof(mmCB_COLOR0_CLEAR_WORD1[0]), 0, 0 }, + { "mmCB_COLOR0_DCC_BASE", REG_MMIO, 0x0325, 1, &mmCB_COLOR0_DCC_BASE[0], sizeof(mmCB_COLOR0_DCC_BASE)/sizeof(mmCB_COLOR0_DCC_BASE[0]), 0, 0 }, + { "mmCB_COLOR0_DCC_BASE_EXT", REG_MMIO, 0x0326, 1, &mmCB_COLOR0_DCC_BASE_EXT[0], sizeof(mmCB_COLOR0_DCC_BASE_EXT)/sizeof(mmCB_COLOR0_DCC_BASE_EXT[0]), 0, 0 }, + { "mmCB_COLOR1_BASE", REG_MMIO, 0x0327, 1, &mmCB_COLOR1_BASE[0], sizeof(mmCB_COLOR1_BASE)/sizeof(mmCB_COLOR1_BASE[0]), 0, 0 }, + { "mmCB_COLOR1_BASE_EXT", REG_MMIO, 0x0328, 1, &mmCB_COLOR1_BASE_EXT[0], sizeof(mmCB_COLOR1_BASE_EXT)/sizeof(mmCB_COLOR1_BASE_EXT[0]), 0, 0 }, + { "mmCB_COLOR1_ATTRIB2", REG_MMIO, 0x0329, 1, &mmCB_COLOR1_ATTRIB2[0], sizeof(mmCB_COLOR1_ATTRIB2)/sizeof(mmCB_COLOR1_ATTRIB2[0]), 0, 0 }, + { "mmCB_COLOR1_VIEW", REG_MMIO, 0x032a, 1, &mmCB_COLOR1_VIEW[0], sizeof(mmCB_COLOR1_VIEW)/sizeof(mmCB_COLOR1_VIEW[0]), 0, 0 }, + { "mmCB_COLOR1_INFO", REG_MMIO, 0x032b, 1, &mmCB_COLOR1_INFO[0], sizeof(mmCB_COLOR1_INFO)/sizeof(mmCB_COLOR1_INFO[0]), 0, 0 }, + { "mmCB_COLOR1_ATTRIB", REG_MMIO, 0x032c, 1, &mmCB_COLOR1_ATTRIB[0], sizeof(mmCB_COLOR1_ATTRIB)/sizeof(mmCB_COLOR1_ATTRIB[0]), 0, 0 }, + { "mmCB_COLOR1_DCC_CONTROL", REG_MMIO, 0x032d, 1, &mmCB_COLOR1_DCC_CONTROL[0], sizeof(mmCB_COLOR1_DCC_CONTROL)/sizeof(mmCB_COLOR1_DCC_CONTROL[0]), 0, 0 }, + { "mmCB_COLOR1_CMASK", REG_MMIO, 0x032e, 1, &mmCB_COLOR1_CMASK[0], sizeof(mmCB_COLOR1_CMASK)/sizeof(mmCB_COLOR1_CMASK[0]), 0, 0 }, + { "mmCB_COLOR1_CMASK_BASE_EXT", REG_MMIO, 0x032f, 1, &mmCB_COLOR1_CMASK_BASE_EXT[0], sizeof(mmCB_COLOR1_CMASK_BASE_EXT)/sizeof(mmCB_COLOR1_CMASK_BASE_EXT[0]), 0, 0 }, + { "mmCB_COLOR1_FMASK", REG_MMIO, 0x0330, 1, &mmCB_COLOR1_FMASK[0], sizeof(mmCB_COLOR1_FMASK)/sizeof(mmCB_COLOR1_FMASK[0]), 0, 0 }, + { "mmCB_COLOR1_FMASK_BASE_EXT", REG_MMIO, 0x0331, 1, &mmCB_COLOR1_FMASK_BASE_EXT[0], sizeof(mmCB_COLOR1_FMASK_BASE_EXT)/sizeof(mmCB_COLOR1_FMASK_BASE_EXT[0]), 0, 0 }, + { "mmCB_COLOR1_CLEAR_WORD0", REG_MMIO, 0x0332, 1, &mmCB_COLOR1_CLEAR_WORD0[0], sizeof(mmCB_COLOR1_CLEAR_WORD0)/sizeof(mmCB_COLOR1_CLEAR_WORD0[0]), 0, 0 }, + { "mmCB_COLOR1_CLEAR_WORD1", REG_MMIO, 0x0333, 1, &mmCB_COLOR1_CLEAR_WORD1[0], sizeof(mmCB_COLOR1_CLEAR_WORD1)/sizeof(mmCB_COLOR1_CLEAR_WORD1[0]), 0, 0 }, + { "mmCB_COLOR1_DCC_BASE", REG_MMIO, 0x0334, 1, &mmCB_COLOR1_DCC_BASE[0], sizeof(mmCB_COLOR1_DCC_BASE)/sizeof(mmCB_COLOR1_DCC_BASE[0]), 0, 0 }, + { "mmCB_COLOR1_DCC_BASE_EXT", REG_MMIO, 0x0335, 1, &mmCB_COLOR1_DCC_BASE_EXT[0], sizeof(mmCB_COLOR1_DCC_BASE_EXT)/sizeof(mmCB_COLOR1_DCC_BASE_EXT[0]), 0, 0 }, + { "mmCB_COLOR2_BASE", REG_MMIO, 0x0336, 1, &mmCB_COLOR2_BASE[0], sizeof(mmCB_COLOR2_BASE)/sizeof(mmCB_COLOR2_BASE[0]), 0, 0 }, + { "mmCB_COLOR2_BASE_EXT", REG_MMIO, 0x0337, 1, &mmCB_COLOR2_BASE_EXT[0], sizeof(mmCB_COLOR2_BASE_EXT)/sizeof(mmCB_COLOR2_BASE_EXT[0]), 0, 0 }, + { "mmCB_COLOR2_ATTRIB2", REG_MMIO, 0x0338, 1, &mmCB_COLOR2_ATTRIB2[0], sizeof(mmCB_COLOR2_ATTRIB2)/sizeof(mmCB_COLOR2_ATTRIB2[0]), 0, 0 }, + { "mmCB_COLOR2_VIEW", REG_MMIO, 0x0339, 1, &mmCB_COLOR2_VIEW[0], sizeof(mmCB_COLOR2_VIEW)/sizeof(mmCB_COLOR2_VIEW[0]), 0, 0 }, + { "mmCB_COLOR2_INFO", REG_MMIO, 0x033a, 1, &mmCB_COLOR2_INFO[0], sizeof(mmCB_COLOR2_INFO)/sizeof(mmCB_COLOR2_INFO[0]), 0, 0 }, + { "mmCB_COLOR2_ATTRIB", REG_MMIO, 0x033b, 1, &mmCB_COLOR2_ATTRIB[0], sizeof(mmCB_COLOR2_ATTRIB)/sizeof(mmCB_COLOR2_ATTRIB[0]), 0, 0 }, + { "mmCB_COLOR2_DCC_CONTROL", REG_MMIO, 0x033c, 1, &mmCB_COLOR2_DCC_CONTROL[0], sizeof(mmCB_COLOR2_DCC_CONTROL)/sizeof(mmCB_COLOR2_DCC_CONTROL[0]), 0, 0 }, + { "mmCB_COLOR2_CMASK", REG_MMIO, 0x033d, 1, &mmCB_COLOR2_CMASK[0], sizeof(mmCB_COLOR2_CMASK)/sizeof(mmCB_COLOR2_CMASK[0]), 0, 0 }, + { "mmCB_COLOR2_CMASK_BASE_EXT", REG_MMIO, 0x033e, 1, &mmCB_COLOR2_CMASK_BASE_EXT[0], sizeof(mmCB_COLOR2_CMASK_BASE_EXT)/sizeof(mmCB_COLOR2_CMASK_BASE_EXT[0]), 0, 0 }, + { "mmCB_COLOR2_FMASK", REG_MMIO, 0x033f, 1, &mmCB_COLOR2_FMASK[0], sizeof(mmCB_COLOR2_FMASK)/sizeof(mmCB_COLOR2_FMASK[0]), 0, 0 }, + { "mmCB_COLOR2_FMASK_BASE_EXT", REG_MMIO, 0x0340, 1, &mmCB_COLOR2_FMASK_BASE_EXT[0], sizeof(mmCB_COLOR2_FMASK_BASE_EXT)/sizeof(mmCB_COLOR2_FMASK_BASE_EXT[0]), 0, 0 }, + { "mmCB_COLOR2_CLEAR_WORD0", REG_MMIO, 0x0341, 1, &mmCB_COLOR2_CLEAR_WORD0[0], sizeof(mmCB_COLOR2_CLEAR_WORD0)/sizeof(mmCB_COLOR2_CLEAR_WORD0[0]), 0, 0 }, + { "mmCB_COLOR2_CLEAR_WORD1", REG_MMIO, 0x0342, 1, &mmCB_COLOR2_CLEAR_WORD1[0], sizeof(mmCB_COLOR2_CLEAR_WORD1)/sizeof(mmCB_COLOR2_CLEAR_WORD1[0]), 0, 0 }, + { "mmCB_COLOR2_DCC_BASE", REG_MMIO, 0x0343, 1, &mmCB_COLOR2_DCC_BASE[0], sizeof(mmCB_COLOR2_DCC_BASE)/sizeof(mmCB_COLOR2_DCC_BASE[0]), 0, 0 }, + { "mmCB_COLOR2_DCC_BASE_EXT", REG_MMIO, 0x0344, 1, &mmCB_COLOR2_DCC_BASE_EXT[0], sizeof(mmCB_COLOR2_DCC_BASE_EXT)/sizeof(mmCB_COLOR2_DCC_BASE_EXT[0]), 0, 0 }, + { "mmCB_COLOR3_BASE", REG_MMIO, 0x0345, 1, &mmCB_COLOR3_BASE[0], sizeof(mmCB_COLOR3_BASE)/sizeof(mmCB_COLOR3_BASE[0]), 0, 0 }, + { "mmCB_COLOR3_BASE_EXT", REG_MMIO, 0x0346, 1, &mmCB_COLOR3_BASE_EXT[0], sizeof(mmCB_COLOR3_BASE_EXT)/sizeof(mmCB_COLOR3_BASE_EXT[0]), 0, 0 }, + { "mmCB_COLOR3_ATTRIB2", REG_MMIO, 0x0347, 1, &mmCB_COLOR3_ATTRIB2[0], sizeof(mmCB_COLOR3_ATTRIB2)/sizeof(mmCB_COLOR3_ATTRIB2[0]), 0, 0 }, + { "mmCB_COLOR3_VIEW", REG_MMIO, 0x0348, 1, &mmCB_COLOR3_VIEW[0], sizeof(mmCB_COLOR3_VIEW)/sizeof(mmCB_COLOR3_VIEW[0]), 0, 0 }, + { "mmCB_COLOR3_INFO", REG_MMIO, 0x0349, 1, &mmCB_COLOR3_INFO[0], sizeof(mmCB_COLOR3_INFO)/sizeof(mmCB_COLOR3_INFO[0]), 0, 0 }, + { "mmCB_COLOR3_ATTRIB", REG_MMIO, 0x034a, 1, &mmCB_COLOR3_ATTRIB[0], sizeof(mmCB_COLOR3_ATTRIB)/sizeof(mmCB_COLOR3_ATTRIB[0]), 0, 0 }, + { "mmCB_COLOR3_DCC_CONTROL", REG_MMIO, 0x034b, 1, &mmCB_COLOR3_DCC_CONTROL[0], sizeof(mmCB_COLOR3_DCC_CONTROL)/sizeof(mmCB_COLOR3_DCC_CONTROL[0]), 0, 0 }, + { "mmCB_COLOR3_CMASK", REG_MMIO, 0x034c, 1, &mmCB_COLOR3_CMASK[0], sizeof(mmCB_COLOR3_CMASK)/sizeof(mmCB_COLOR3_CMASK[0]), 0, 0 }, + { "mmCB_COLOR3_CMASK_BASE_EXT", REG_MMIO, 0x034d, 1, &mmCB_COLOR3_CMASK_BASE_EXT[0], sizeof(mmCB_COLOR3_CMASK_BASE_EXT)/sizeof(mmCB_COLOR3_CMASK_BASE_EXT[0]), 0, 0 }, + { "mmCB_COLOR3_FMASK", REG_MMIO, 0x034e, 1, &mmCB_COLOR3_FMASK[0], sizeof(mmCB_COLOR3_FMASK)/sizeof(mmCB_COLOR3_FMASK[0]), 0, 0 }, + { "mmCB_COLOR3_FMASK_BASE_EXT", REG_MMIO, 0x034f, 1, &mmCB_COLOR3_FMASK_BASE_EXT[0], sizeof(mmCB_COLOR3_FMASK_BASE_EXT)/sizeof(mmCB_COLOR3_FMASK_BASE_EXT[0]), 0, 0 }, + { "mmCB_COLOR3_CLEAR_WORD0", REG_MMIO, 0x0350, 1, &mmCB_COLOR3_CLEAR_WORD0[0], sizeof(mmCB_COLOR3_CLEAR_WORD0)/sizeof(mmCB_COLOR3_CLEAR_WORD0[0]), 0, 0 }, + { "mmCB_COLOR3_CLEAR_WORD1", REG_MMIO, 0x0351, 1, &mmCB_COLOR3_CLEAR_WORD1[0], sizeof(mmCB_COLOR3_CLEAR_WORD1)/sizeof(mmCB_COLOR3_CLEAR_WORD1[0]), 0, 0 }, + { "mmCB_COLOR3_DCC_BASE", REG_MMIO, 0x0352, 1, &mmCB_COLOR3_DCC_BASE[0], sizeof(mmCB_COLOR3_DCC_BASE)/sizeof(mmCB_COLOR3_DCC_BASE[0]), 0, 0 }, + { "mmCB_COLOR3_DCC_BASE_EXT", REG_MMIO, 0x0353, 1, &mmCB_COLOR3_DCC_BASE_EXT[0], sizeof(mmCB_COLOR3_DCC_BASE_EXT)/sizeof(mmCB_COLOR3_DCC_BASE_EXT[0]), 0, 0 }, + { "mmCB_COLOR4_BASE", REG_MMIO, 0x0354, 1, &mmCB_COLOR4_BASE[0], sizeof(mmCB_COLOR4_BASE)/sizeof(mmCB_COLOR4_BASE[0]), 0, 0 }, + { "mmCB_COLOR4_BASE_EXT", REG_MMIO, 0x0355, 1, &mmCB_COLOR4_BASE_EXT[0], sizeof(mmCB_COLOR4_BASE_EXT)/sizeof(mmCB_COLOR4_BASE_EXT[0]), 0, 0 }, + { "mmCB_COLOR4_ATTRIB2", REG_MMIO, 0x0356, 1, &mmCB_COLOR4_ATTRIB2[0], sizeof(mmCB_COLOR4_ATTRIB2)/sizeof(mmCB_COLOR4_ATTRIB2[0]), 0, 0 }, + { "mmCB_COLOR4_VIEW", REG_MMIO, 0x0357, 1, &mmCB_COLOR4_VIEW[0], sizeof(mmCB_COLOR4_VIEW)/sizeof(mmCB_COLOR4_VIEW[0]), 0, 0 }, + { "mmCB_COLOR4_INFO", REG_MMIO, 0x0358, 1, &mmCB_COLOR4_INFO[0], sizeof(mmCB_COLOR4_INFO)/sizeof(mmCB_COLOR4_INFO[0]), 0, 0 }, + { "mmCB_COLOR4_ATTRIB", REG_MMIO, 0x0359, 1, &mmCB_COLOR4_ATTRIB[0], sizeof(mmCB_COLOR4_ATTRIB)/sizeof(mmCB_COLOR4_ATTRIB[0]), 0, 0 }, + { "mmCB_COLOR4_DCC_CONTROL", REG_MMIO, 0x035a, 1, &mmCB_COLOR4_DCC_CONTROL[0], sizeof(mmCB_COLOR4_DCC_CONTROL)/sizeof(mmCB_COLOR4_DCC_CONTROL[0]), 0, 0 }, + { "mmCB_COLOR4_CMASK", REG_MMIO, 0x035b, 1, &mmCB_COLOR4_CMASK[0], sizeof(mmCB_COLOR4_CMASK)/sizeof(mmCB_COLOR4_CMASK[0]), 0, 0 }, + { "mmCB_COLOR4_CMASK_BASE_EXT", REG_MMIO, 0x035c, 1, &mmCB_COLOR4_CMASK_BASE_EXT[0], sizeof(mmCB_COLOR4_CMASK_BASE_EXT)/sizeof(mmCB_COLOR4_CMASK_BASE_EXT[0]), 0, 0 }, + { "mmCB_COLOR4_FMASK", REG_MMIO, 0x035d, 1, &mmCB_COLOR4_FMASK[0], sizeof(mmCB_COLOR4_FMASK)/sizeof(mmCB_COLOR4_FMASK[0]), 0, 0 }, + { "mmCB_COLOR4_FMASK_BASE_EXT", REG_MMIO, 0x035e, 1, &mmCB_COLOR4_FMASK_BASE_EXT[0], sizeof(mmCB_COLOR4_FMASK_BASE_EXT)/sizeof(mmCB_COLOR4_FMASK_BASE_EXT[0]), 0, 0 }, + { "mmCB_COLOR4_CLEAR_WORD0", REG_MMIO, 0x035f, 1, &mmCB_COLOR4_CLEAR_WORD0[0], sizeof(mmCB_COLOR4_CLEAR_WORD0)/sizeof(mmCB_COLOR4_CLEAR_WORD0[0]), 0, 0 }, + { "mmCB_COLOR4_CLEAR_WORD1", REG_MMIO, 0x0360, 1, &mmCB_COLOR4_CLEAR_WORD1[0], sizeof(mmCB_COLOR4_CLEAR_WORD1)/sizeof(mmCB_COLOR4_CLEAR_WORD1[0]), 0, 0 }, + { "mmCB_COLOR4_DCC_BASE", REG_MMIO, 0x0361, 1, &mmCB_COLOR4_DCC_BASE[0], sizeof(mmCB_COLOR4_DCC_BASE)/sizeof(mmCB_COLOR4_DCC_BASE[0]), 0, 0 }, + { "mmCB_COLOR4_DCC_BASE_EXT", REG_MMIO, 0x0362, 1, &mmCB_COLOR4_DCC_BASE_EXT[0], sizeof(mmCB_COLOR4_DCC_BASE_EXT)/sizeof(mmCB_COLOR4_DCC_BASE_EXT[0]), 0, 0 }, + { "mmCB_COLOR5_BASE", REG_MMIO, 0x0363, 1, &mmCB_COLOR5_BASE[0], sizeof(mmCB_COLOR5_BASE)/sizeof(mmCB_COLOR5_BASE[0]), 0, 0 }, + { "mmCB_COLOR5_BASE_EXT", REG_MMIO, 0x0364, 1, &mmCB_COLOR5_BASE_EXT[0], sizeof(mmCB_COLOR5_BASE_EXT)/sizeof(mmCB_COLOR5_BASE_EXT[0]), 0, 0 }, + { "mmCB_COLOR5_ATTRIB2", REG_MMIO, 0x0365, 1, &mmCB_COLOR5_ATTRIB2[0], sizeof(mmCB_COLOR5_ATTRIB2)/sizeof(mmCB_COLOR5_ATTRIB2[0]), 0, 0 }, + { "mmCB_COLOR5_VIEW", REG_MMIO, 0x0366, 1, &mmCB_COLOR5_VIEW[0], sizeof(mmCB_COLOR5_VIEW)/sizeof(mmCB_COLOR5_VIEW[0]), 0, 0 }, + { "mmCB_COLOR5_INFO", REG_MMIO, 0x0367, 1, &mmCB_COLOR5_INFO[0], sizeof(mmCB_COLOR5_INFO)/sizeof(mmCB_COLOR5_INFO[0]), 0, 0 }, + { "mmCB_COLOR5_ATTRIB", REG_MMIO, 0x0368, 1, &mmCB_COLOR5_ATTRIB[0], sizeof(mmCB_COLOR5_ATTRIB)/sizeof(mmCB_COLOR5_ATTRIB[0]), 0, 0 }, + { "mmCB_COLOR5_DCC_CONTROL", REG_MMIO, 0x0369, 1, &mmCB_COLOR5_DCC_CONTROL[0], sizeof(mmCB_COLOR5_DCC_CONTROL)/sizeof(mmCB_COLOR5_DCC_CONTROL[0]), 0, 0 }, + { "mmCB_COLOR5_CMASK", REG_MMIO, 0x036a, 1, &mmCB_COLOR5_CMASK[0], sizeof(mmCB_COLOR5_CMASK)/sizeof(mmCB_COLOR5_CMASK[0]), 0, 0 }, + { "mmCB_COLOR5_CMASK_BASE_EXT", REG_MMIO, 0x036b, 1, &mmCB_COLOR5_CMASK_BASE_EXT[0], sizeof(mmCB_COLOR5_CMASK_BASE_EXT)/sizeof(mmCB_COLOR5_CMASK_BASE_EXT[0]), 0, 0 }, + { "mmCB_COLOR5_FMASK", REG_MMIO, 0x036c, 1, &mmCB_COLOR5_FMASK[0], sizeof(mmCB_COLOR5_FMASK)/sizeof(mmCB_COLOR5_FMASK[0]), 0, 0 }, + { "mmCB_COLOR5_FMASK_BASE_EXT", REG_MMIO, 0x036d, 1, &mmCB_COLOR5_FMASK_BASE_EXT[0], sizeof(mmCB_COLOR5_FMASK_BASE_EXT)/sizeof(mmCB_COLOR5_FMASK_BASE_EXT[0]), 0, 0 }, + { "mmCB_COLOR5_CLEAR_WORD0", REG_MMIO, 0x036e, 1, &mmCB_COLOR5_CLEAR_WORD0[0], sizeof(mmCB_COLOR5_CLEAR_WORD0)/sizeof(mmCB_COLOR5_CLEAR_WORD0[0]), 0, 0 }, + { "mmCB_COLOR5_CLEAR_WORD1", REG_MMIO, 0x036f, 1, &mmCB_COLOR5_CLEAR_WORD1[0], sizeof(mmCB_COLOR5_CLEAR_WORD1)/sizeof(mmCB_COLOR5_CLEAR_WORD1[0]), 0, 0 }, + { "mmCB_COLOR5_DCC_BASE", REG_MMIO, 0x0370, 1, &mmCB_COLOR5_DCC_BASE[0], sizeof(mmCB_COLOR5_DCC_BASE)/sizeof(mmCB_COLOR5_DCC_BASE[0]), 0, 0 }, + { "mmCB_COLOR5_DCC_BASE_EXT", REG_MMIO, 0x0371, 1, &mmCB_COLOR5_DCC_BASE_EXT[0], sizeof(mmCB_COLOR5_DCC_BASE_EXT)/sizeof(mmCB_COLOR5_DCC_BASE_EXT[0]), 0, 0 }, + { "mmCB_COLOR6_BASE", REG_MMIO, 0x0372, 1, &mmCB_COLOR6_BASE[0], sizeof(mmCB_COLOR6_BASE)/sizeof(mmCB_COLOR6_BASE[0]), 0, 0 }, + { "mmCB_COLOR6_BASE_EXT", REG_MMIO, 0x0373, 1, &mmCB_COLOR6_BASE_EXT[0], sizeof(mmCB_COLOR6_BASE_EXT)/sizeof(mmCB_COLOR6_BASE_EXT[0]), 0, 0 }, + { "mmCB_COLOR6_ATTRIB2", REG_MMIO, 0x0374, 1, &mmCB_COLOR6_ATTRIB2[0], sizeof(mmCB_COLOR6_ATTRIB2)/sizeof(mmCB_COLOR6_ATTRIB2[0]), 0, 0 }, + { "mmCB_COLOR6_VIEW", REG_MMIO, 0x0375, 1, &mmCB_COLOR6_VIEW[0], sizeof(mmCB_COLOR6_VIEW)/sizeof(mmCB_COLOR6_VIEW[0]), 0, 0 }, + { "mmCB_COLOR6_INFO", REG_MMIO, 0x0376, 1, &mmCB_COLOR6_INFO[0], sizeof(mmCB_COLOR6_INFO)/sizeof(mmCB_COLOR6_INFO[0]), 0, 0 }, + { "mmCB_COLOR6_ATTRIB", REG_MMIO, 0x0377, 1, &mmCB_COLOR6_ATTRIB[0], sizeof(mmCB_COLOR6_ATTRIB)/sizeof(mmCB_COLOR6_ATTRIB[0]), 0, 0 }, + { "mmCB_COLOR6_DCC_CONTROL", REG_MMIO, 0x0378, 1, &mmCB_COLOR6_DCC_CONTROL[0], sizeof(mmCB_COLOR6_DCC_CONTROL)/sizeof(mmCB_COLOR6_DCC_CONTROL[0]), 0, 0 }, + { "mmCB_COLOR6_CMASK", REG_MMIO, 0x0379, 1, &mmCB_COLOR6_CMASK[0], sizeof(mmCB_COLOR6_CMASK)/sizeof(mmCB_COLOR6_CMASK[0]), 0, 0 }, + { "mmCB_COLOR6_CMASK_BASE_EXT", REG_MMIO, 0x037a, 1, &mmCB_COLOR6_CMASK_BASE_EXT[0], sizeof(mmCB_COLOR6_CMASK_BASE_EXT)/sizeof(mmCB_COLOR6_CMASK_BASE_EXT[0]), 0, 0 }, + { "mmCB_COLOR6_FMASK", REG_MMIO, 0x037b, 1, &mmCB_COLOR6_FMASK[0], sizeof(mmCB_COLOR6_FMASK)/sizeof(mmCB_COLOR6_FMASK[0]), 0, 0 }, + { "mmCB_COLOR6_FMASK_BASE_EXT", REG_MMIO, 0x037c, 1, &mmCB_COLOR6_FMASK_BASE_EXT[0], sizeof(mmCB_COLOR6_FMASK_BASE_EXT)/sizeof(mmCB_COLOR6_FMASK_BASE_EXT[0]), 0, 0 }, + { "mmCB_COLOR6_CLEAR_WORD0", REG_MMIO, 0x037d, 1, &mmCB_COLOR6_CLEAR_WORD0[0], sizeof(mmCB_COLOR6_CLEAR_WORD0)/sizeof(mmCB_COLOR6_CLEAR_WORD0[0]), 0, 0 }, + { "mmCB_COLOR6_CLEAR_WORD1", REG_MMIO, 0x037e, 1, &mmCB_COLOR6_CLEAR_WORD1[0], sizeof(mmCB_COLOR6_CLEAR_WORD1)/sizeof(mmCB_COLOR6_CLEAR_WORD1[0]), 0, 0 }, + { "mmCB_COLOR6_DCC_BASE", REG_MMIO, 0x037f, 1, &mmCB_COLOR6_DCC_BASE[0], sizeof(mmCB_COLOR6_DCC_BASE)/sizeof(mmCB_COLOR6_DCC_BASE[0]), 0, 0 }, + { "mmCB_COLOR6_DCC_BASE_EXT", REG_MMIO, 0x0380, 1, &mmCB_COLOR6_DCC_BASE_EXT[0], sizeof(mmCB_COLOR6_DCC_BASE_EXT)/sizeof(mmCB_COLOR6_DCC_BASE_EXT[0]), 0, 0 }, + { "mmCB_COLOR7_BASE", REG_MMIO, 0x0381, 1, &mmCB_COLOR7_BASE[0], sizeof(mmCB_COLOR7_BASE)/sizeof(mmCB_COLOR7_BASE[0]), 0, 0 }, + { "mmCB_COLOR7_BASE_EXT", REG_MMIO, 0x0382, 1, &mmCB_COLOR7_BASE_EXT[0], sizeof(mmCB_COLOR7_BASE_EXT)/sizeof(mmCB_COLOR7_BASE_EXT[0]), 0, 0 }, + { "mmCB_COLOR7_ATTRIB2", REG_MMIO, 0x0383, 1, &mmCB_COLOR7_ATTRIB2[0], sizeof(mmCB_COLOR7_ATTRIB2)/sizeof(mmCB_COLOR7_ATTRIB2[0]), 0, 0 }, + { "mmCB_COLOR7_VIEW", REG_MMIO, 0x0384, 1, &mmCB_COLOR7_VIEW[0], sizeof(mmCB_COLOR7_VIEW)/sizeof(mmCB_COLOR7_VIEW[0]), 0, 0 }, + { "mmCB_COLOR7_INFO", REG_MMIO, 0x0385, 1, &mmCB_COLOR7_INFO[0], sizeof(mmCB_COLOR7_INFO)/sizeof(mmCB_COLOR7_INFO[0]), 0, 0 }, + { "mmCB_COLOR7_ATTRIB", REG_MMIO, 0x0386, 1, &mmCB_COLOR7_ATTRIB[0], sizeof(mmCB_COLOR7_ATTRIB)/sizeof(mmCB_COLOR7_ATTRIB[0]), 0, 0 }, + { "mmCB_COLOR7_DCC_CONTROL", REG_MMIO, 0x0387, 1, &mmCB_COLOR7_DCC_CONTROL[0], sizeof(mmCB_COLOR7_DCC_CONTROL)/sizeof(mmCB_COLOR7_DCC_CONTROL[0]), 0, 0 }, + { "mmCB_COLOR7_CMASK", REG_MMIO, 0x0388, 1, &mmCB_COLOR7_CMASK[0], sizeof(mmCB_COLOR7_CMASK)/sizeof(mmCB_COLOR7_CMASK[0]), 0, 0 }, + { "mmCB_COLOR7_CMASK_BASE_EXT", REG_MMIO, 0x0389, 1, &mmCB_COLOR7_CMASK_BASE_EXT[0], sizeof(mmCB_COLOR7_CMASK_BASE_EXT)/sizeof(mmCB_COLOR7_CMASK_BASE_EXT[0]), 0, 0 }, + { "mmCB_COLOR7_FMASK", REG_MMIO, 0x038a, 1, &mmCB_COLOR7_FMASK[0], sizeof(mmCB_COLOR7_FMASK)/sizeof(mmCB_COLOR7_FMASK[0]), 0, 0 }, + { "mmCB_COLOR7_FMASK_BASE_EXT", REG_MMIO, 0x038b, 1, &mmCB_COLOR7_FMASK_BASE_EXT[0], sizeof(mmCB_COLOR7_FMASK_BASE_EXT)/sizeof(mmCB_COLOR7_FMASK_BASE_EXT[0]), 0, 0 }, + { "mmCB_COLOR7_CLEAR_WORD0", REG_MMIO, 0x038c, 1, &mmCB_COLOR7_CLEAR_WORD0[0], sizeof(mmCB_COLOR7_CLEAR_WORD0)/sizeof(mmCB_COLOR7_CLEAR_WORD0[0]), 0, 0 }, + { "mmCB_COLOR7_CLEAR_WORD1", REG_MMIO, 0x038d, 1, &mmCB_COLOR7_CLEAR_WORD1[0], sizeof(mmCB_COLOR7_CLEAR_WORD1)/sizeof(mmCB_COLOR7_CLEAR_WORD1[0]), 0, 0 }, + { "mmCB_COLOR7_DCC_BASE", REG_MMIO, 0x038e, 1, &mmCB_COLOR7_DCC_BASE[0], sizeof(mmCB_COLOR7_DCC_BASE)/sizeof(mmCB_COLOR7_DCC_BASE[0]), 0, 0 }, + { "mmCB_COLOR7_DCC_BASE_EXT", REG_MMIO, 0x038f, 1, &mmCB_COLOR7_DCC_BASE_EXT[0], sizeof(mmCB_COLOR7_DCC_BASE_EXT)/sizeof(mmCB_COLOR7_DCC_BASE_EXT[0]), 0, 0 }, + { "mmCP_EOP_DONE_ADDR_LO", REG_MMIO, 0x2000, 1, &mmCP_EOP_DONE_ADDR_LO[0], sizeof(mmCP_EOP_DONE_ADDR_LO)/sizeof(mmCP_EOP_DONE_ADDR_LO[0]), 0, 0 }, + { "mmCP_EOP_DONE_ADDR_HI", REG_MMIO, 0x2001, 1, &mmCP_EOP_DONE_ADDR_HI[0], sizeof(mmCP_EOP_DONE_ADDR_HI)/sizeof(mmCP_EOP_DONE_ADDR_HI[0]), 0, 0 }, + { "mmCP_EOP_DONE_DATA_LO", REG_MMIO, 0x2002, 1, &mmCP_EOP_DONE_DATA_LO[0], sizeof(mmCP_EOP_DONE_DATA_LO)/sizeof(mmCP_EOP_DONE_DATA_LO[0]), 0, 0 }, + { "mmCP_EOP_DONE_DATA_HI", REG_MMIO, 0x2003, 1, &mmCP_EOP_DONE_DATA_HI[0], sizeof(mmCP_EOP_DONE_DATA_HI)/sizeof(mmCP_EOP_DONE_DATA_HI[0]), 0, 0 }, + { "mmCP_EOP_LAST_FENCE_LO", REG_MMIO, 0x2004, 1, &mmCP_EOP_LAST_FENCE_LO[0], sizeof(mmCP_EOP_LAST_FENCE_LO)/sizeof(mmCP_EOP_LAST_FENCE_LO[0]), 0, 0 }, + { "mmCP_EOP_LAST_FENCE_HI", REG_MMIO, 0x2005, 1, &mmCP_EOP_LAST_FENCE_HI[0], sizeof(mmCP_EOP_LAST_FENCE_HI)/sizeof(mmCP_EOP_LAST_FENCE_HI[0]), 0, 0 }, + { "mmCP_STREAM_OUT_ADDR_LO", REG_MMIO, 0x2006, 1, &mmCP_STREAM_OUT_ADDR_LO[0], sizeof(mmCP_STREAM_OUT_ADDR_LO)/sizeof(mmCP_STREAM_OUT_ADDR_LO[0]), 0, 0 }, + { "mmCP_STREAM_OUT_ADDR_HI", REG_MMIO, 0x2007, 1, &mmCP_STREAM_OUT_ADDR_HI[0], sizeof(mmCP_STREAM_OUT_ADDR_HI)/sizeof(mmCP_STREAM_OUT_ADDR_HI[0]), 0, 0 }, + { "mmCP_NUM_PRIM_WRITTEN_COUNT0_LO", REG_MMIO, 0x2008, 1, &mmCP_NUM_PRIM_WRITTEN_COUNT0_LO[0], sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT0_LO)/sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT0_LO[0]), 0, 0 }, + { "mmCP_NUM_PRIM_WRITTEN_COUNT0_HI", REG_MMIO, 0x2009, 1, &mmCP_NUM_PRIM_WRITTEN_COUNT0_HI[0], sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT0_HI)/sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT0_HI[0]), 0, 0 }, + { "mmCP_NUM_PRIM_NEEDED_COUNT0_LO", REG_MMIO, 0x200a, 1, &mmCP_NUM_PRIM_NEEDED_COUNT0_LO[0], sizeof(mmCP_NUM_PRIM_NEEDED_COUNT0_LO)/sizeof(mmCP_NUM_PRIM_NEEDED_COUNT0_LO[0]), 0, 0 }, + { "mmCP_NUM_PRIM_NEEDED_COUNT0_HI", REG_MMIO, 0x200b, 1, &mmCP_NUM_PRIM_NEEDED_COUNT0_HI[0], sizeof(mmCP_NUM_PRIM_NEEDED_COUNT0_HI)/sizeof(mmCP_NUM_PRIM_NEEDED_COUNT0_HI[0]), 0, 0 }, + { "mmCP_NUM_PRIM_WRITTEN_COUNT1_LO", REG_MMIO, 0x200c, 1, &mmCP_NUM_PRIM_WRITTEN_COUNT1_LO[0], sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT1_LO)/sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT1_LO[0]), 0, 0 }, + { "mmCP_NUM_PRIM_WRITTEN_COUNT1_HI", REG_MMIO, 0x200d, 1, &mmCP_NUM_PRIM_WRITTEN_COUNT1_HI[0], sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT1_HI)/sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT1_HI[0]), 0, 0 }, + { "mmCP_NUM_PRIM_NEEDED_COUNT1_LO", REG_MMIO, 0x200e, 1, &mmCP_NUM_PRIM_NEEDED_COUNT1_LO[0], sizeof(mmCP_NUM_PRIM_NEEDED_COUNT1_LO)/sizeof(mmCP_NUM_PRIM_NEEDED_COUNT1_LO[0]), 0, 0 }, + { "mmCP_NUM_PRIM_NEEDED_COUNT1_HI", REG_MMIO, 0x200f, 1, &mmCP_NUM_PRIM_NEEDED_COUNT1_HI[0], sizeof(mmCP_NUM_PRIM_NEEDED_COUNT1_HI)/sizeof(mmCP_NUM_PRIM_NEEDED_COUNT1_HI[0]), 0, 0 }, + { "mmCP_NUM_PRIM_WRITTEN_COUNT2_LO", REG_MMIO, 0x2010, 1, &mmCP_NUM_PRIM_WRITTEN_COUNT2_LO[0], sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT2_LO)/sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT2_LO[0]), 0, 0 }, + { "mmCP_NUM_PRIM_WRITTEN_COUNT2_HI", REG_MMIO, 0x2011, 1, &mmCP_NUM_PRIM_WRITTEN_COUNT2_HI[0], sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT2_HI)/sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT2_HI[0]), 0, 0 }, + { "mmCP_NUM_PRIM_NEEDED_COUNT2_LO", REG_MMIO, 0x2012, 1, &mmCP_NUM_PRIM_NEEDED_COUNT2_LO[0], sizeof(mmCP_NUM_PRIM_NEEDED_COUNT2_LO)/sizeof(mmCP_NUM_PRIM_NEEDED_COUNT2_LO[0]), 0, 0 }, + { "mmCP_NUM_PRIM_NEEDED_COUNT2_HI", REG_MMIO, 0x2013, 1, &mmCP_NUM_PRIM_NEEDED_COUNT2_HI[0], sizeof(mmCP_NUM_PRIM_NEEDED_COUNT2_HI)/sizeof(mmCP_NUM_PRIM_NEEDED_COUNT2_HI[0]), 0, 0 }, + { "mmCP_NUM_PRIM_WRITTEN_COUNT3_LO", REG_MMIO, 0x2014, 1, &mmCP_NUM_PRIM_WRITTEN_COUNT3_LO[0], sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT3_LO)/sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT3_LO[0]), 0, 0 }, + { "mmCP_NUM_PRIM_WRITTEN_COUNT3_HI", REG_MMIO, 0x2015, 1, &mmCP_NUM_PRIM_WRITTEN_COUNT3_HI[0], sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT3_HI)/sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT3_HI[0]), 0, 0 }, + { "mmCP_NUM_PRIM_NEEDED_COUNT3_LO", REG_MMIO, 0x2016, 1, &mmCP_NUM_PRIM_NEEDED_COUNT3_LO[0], sizeof(mmCP_NUM_PRIM_NEEDED_COUNT3_LO)/sizeof(mmCP_NUM_PRIM_NEEDED_COUNT3_LO[0]), 0, 0 }, + { "mmCP_NUM_PRIM_NEEDED_COUNT3_HI", REG_MMIO, 0x2017, 1, &mmCP_NUM_PRIM_NEEDED_COUNT3_HI[0], sizeof(mmCP_NUM_PRIM_NEEDED_COUNT3_HI)/sizeof(mmCP_NUM_PRIM_NEEDED_COUNT3_HI[0]), 0, 0 }, + { "mmCP_PIPE_STATS_ADDR_LO", REG_MMIO, 0x2018, 1, &mmCP_PIPE_STATS_ADDR_LO[0], sizeof(mmCP_PIPE_STATS_ADDR_LO)/sizeof(mmCP_PIPE_STATS_ADDR_LO[0]), 0, 0 }, + { "mmCP_PIPE_STATS_ADDR_HI", REG_MMIO, 0x2019, 1, &mmCP_PIPE_STATS_ADDR_HI[0], sizeof(mmCP_PIPE_STATS_ADDR_HI)/sizeof(mmCP_PIPE_STATS_ADDR_HI[0]), 0, 0 }, + { "mmCP_VGT_IAVERT_COUNT_LO", REG_MMIO, 0x201a, 1, &mmCP_VGT_IAVERT_COUNT_LO[0], sizeof(mmCP_VGT_IAVERT_COUNT_LO)/sizeof(mmCP_VGT_IAVERT_COUNT_LO[0]), 0, 0 }, + { "mmCP_VGT_IAVERT_COUNT_HI", REG_MMIO, 0x201b, 1, &mmCP_VGT_IAVERT_COUNT_HI[0], sizeof(mmCP_VGT_IAVERT_COUNT_HI)/sizeof(mmCP_VGT_IAVERT_COUNT_HI[0]), 0, 0 }, + { "mmCP_VGT_IAPRIM_COUNT_LO", REG_MMIO, 0x201c, 1, &mmCP_VGT_IAPRIM_COUNT_LO[0], sizeof(mmCP_VGT_IAPRIM_COUNT_LO)/sizeof(mmCP_VGT_IAPRIM_COUNT_LO[0]), 0, 0 }, + { "mmCP_VGT_IAPRIM_COUNT_HI", REG_MMIO, 0x201d, 1, &mmCP_VGT_IAPRIM_COUNT_HI[0], sizeof(mmCP_VGT_IAPRIM_COUNT_HI)/sizeof(mmCP_VGT_IAPRIM_COUNT_HI[0]), 0, 0 }, + { "mmCP_VGT_GSPRIM_COUNT_LO", REG_MMIO, 0x201e, 1, &mmCP_VGT_GSPRIM_COUNT_LO[0], sizeof(mmCP_VGT_GSPRIM_COUNT_LO)/sizeof(mmCP_VGT_GSPRIM_COUNT_LO[0]), 0, 0 }, + { "mmCP_VGT_GSPRIM_COUNT_HI", REG_MMIO, 0x201f, 1, &mmCP_VGT_GSPRIM_COUNT_HI[0], sizeof(mmCP_VGT_GSPRIM_COUNT_HI)/sizeof(mmCP_VGT_GSPRIM_COUNT_HI[0]), 0, 0 }, + { "mmCP_VGT_VSINVOC_COUNT_LO", REG_MMIO, 0x2020, 1, &mmCP_VGT_VSINVOC_COUNT_LO[0], sizeof(mmCP_VGT_VSINVOC_COUNT_LO)/sizeof(mmCP_VGT_VSINVOC_COUNT_LO[0]), 0, 0 }, + { "mmCP_VGT_VSINVOC_COUNT_HI", REG_MMIO, 0x2021, 1, &mmCP_VGT_VSINVOC_COUNT_HI[0], sizeof(mmCP_VGT_VSINVOC_COUNT_HI)/sizeof(mmCP_VGT_VSINVOC_COUNT_HI[0]), 0, 0 }, + { "mmCP_VGT_GSINVOC_COUNT_LO", REG_MMIO, 0x2022, 1, &mmCP_VGT_GSINVOC_COUNT_LO[0], sizeof(mmCP_VGT_GSINVOC_COUNT_LO)/sizeof(mmCP_VGT_GSINVOC_COUNT_LO[0]), 0, 0 }, + { "mmCP_VGT_GSINVOC_COUNT_HI", REG_MMIO, 0x2023, 1, &mmCP_VGT_GSINVOC_COUNT_HI[0], sizeof(mmCP_VGT_GSINVOC_COUNT_HI)/sizeof(mmCP_VGT_GSINVOC_COUNT_HI[0]), 0, 0 }, + { "mmCP_VGT_HSINVOC_COUNT_LO", REG_MMIO, 0x2024, 1, &mmCP_VGT_HSINVOC_COUNT_LO[0], sizeof(mmCP_VGT_HSINVOC_COUNT_LO)/sizeof(mmCP_VGT_HSINVOC_COUNT_LO[0]), 0, 0 }, + { "mmCP_VGT_HSINVOC_COUNT_HI", REG_MMIO, 0x2025, 1, &mmCP_VGT_HSINVOC_COUNT_HI[0], sizeof(mmCP_VGT_HSINVOC_COUNT_HI)/sizeof(mmCP_VGT_HSINVOC_COUNT_HI[0]), 0, 0 }, + { "mmCP_VGT_DSINVOC_COUNT_LO", REG_MMIO, 0x2026, 1, &mmCP_VGT_DSINVOC_COUNT_LO[0], sizeof(mmCP_VGT_DSINVOC_COUNT_LO)/sizeof(mmCP_VGT_DSINVOC_COUNT_LO[0]), 0, 0 }, + { "mmCP_VGT_DSINVOC_COUNT_HI", REG_MMIO, 0x2027, 1, &mmCP_VGT_DSINVOC_COUNT_HI[0], sizeof(mmCP_VGT_DSINVOC_COUNT_HI)/sizeof(mmCP_VGT_DSINVOC_COUNT_HI[0]), 0, 0 }, + { "mmCP_PA_CINVOC_COUNT_LO", REG_MMIO, 0x2028, 1, &mmCP_PA_CINVOC_COUNT_LO[0], sizeof(mmCP_PA_CINVOC_COUNT_LO)/sizeof(mmCP_PA_CINVOC_COUNT_LO[0]), 0, 0 }, + { "mmCP_PA_CINVOC_COUNT_HI", REG_MMIO, 0x2029, 1, &mmCP_PA_CINVOC_COUNT_HI[0], sizeof(mmCP_PA_CINVOC_COUNT_HI)/sizeof(mmCP_PA_CINVOC_COUNT_HI[0]), 0, 0 }, + { "mmCP_PA_CPRIM_COUNT_LO", REG_MMIO, 0x202a, 1, &mmCP_PA_CPRIM_COUNT_LO[0], sizeof(mmCP_PA_CPRIM_COUNT_LO)/sizeof(mmCP_PA_CPRIM_COUNT_LO[0]), 0, 0 }, + { "mmCP_PA_CPRIM_COUNT_HI", REG_MMIO, 0x202b, 1, &mmCP_PA_CPRIM_COUNT_HI[0], sizeof(mmCP_PA_CPRIM_COUNT_HI)/sizeof(mmCP_PA_CPRIM_COUNT_HI[0]), 0, 0 }, + { "mmCP_SC_PSINVOC_COUNT0_LO", REG_MMIO, 0x202c, 1, &mmCP_SC_PSINVOC_COUNT0_LO[0], sizeof(mmCP_SC_PSINVOC_COUNT0_LO)/sizeof(mmCP_SC_PSINVOC_COUNT0_LO[0]), 0, 0 }, + { "mmCP_SC_PSINVOC_COUNT0_HI", REG_MMIO, 0x202d, 1, &mmCP_SC_PSINVOC_COUNT0_HI[0], sizeof(mmCP_SC_PSINVOC_COUNT0_HI)/sizeof(mmCP_SC_PSINVOC_COUNT0_HI[0]), 0, 0 }, + { "mmCP_SC_PSINVOC_COUNT1_LO", REG_MMIO, 0x202e, 1, &mmCP_SC_PSINVOC_COUNT1_LO[0], sizeof(mmCP_SC_PSINVOC_COUNT1_LO)/sizeof(mmCP_SC_PSINVOC_COUNT1_LO[0]), 0, 0 }, + { "mmCP_SC_PSINVOC_COUNT1_HI", REG_MMIO, 0x202f, 1, &mmCP_SC_PSINVOC_COUNT1_HI[0], sizeof(mmCP_SC_PSINVOC_COUNT1_HI)/sizeof(mmCP_SC_PSINVOC_COUNT1_HI[0]), 0, 0 }, + { "mmCP_VGT_CSINVOC_COUNT_LO", REG_MMIO, 0x2030, 1, &mmCP_VGT_CSINVOC_COUNT_LO[0], sizeof(mmCP_VGT_CSINVOC_COUNT_LO)/sizeof(mmCP_VGT_CSINVOC_COUNT_LO[0]), 0, 0 }, + { "mmCP_VGT_CSINVOC_COUNT_HI", REG_MMIO, 0x2031, 1, &mmCP_VGT_CSINVOC_COUNT_HI[0], sizeof(mmCP_VGT_CSINVOC_COUNT_HI)/sizeof(mmCP_VGT_CSINVOC_COUNT_HI[0]), 0, 0 }, + { "mmCP_PIPE_STATS_CONTROL", REG_MMIO, 0x203d, 1, &mmCP_PIPE_STATS_CONTROL[0], sizeof(mmCP_PIPE_STATS_CONTROL)/sizeof(mmCP_PIPE_STATS_CONTROL[0]), 0, 0 }, + { "mmCP_STREAM_OUT_CONTROL", REG_MMIO, 0x203e, 1, &mmCP_STREAM_OUT_CONTROL[0], sizeof(mmCP_STREAM_OUT_CONTROL)/sizeof(mmCP_STREAM_OUT_CONTROL[0]), 0, 0 }, + { "mmCP_STRMOUT_CNTL", REG_MMIO, 0x203f, 1, &mmCP_STRMOUT_CNTL[0], sizeof(mmCP_STRMOUT_CNTL)/sizeof(mmCP_STRMOUT_CNTL[0]), 0, 0 }, + { "mmSCRATCH_REG0", REG_MMIO, 0x2040, 1, &mmSCRATCH_REG0[0], sizeof(mmSCRATCH_REG0)/sizeof(mmSCRATCH_REG0[0]), 0, 0 }, + { "mmSCRATCH_REG1", REG_MMIO, 0x2041, 1, &mmSCRATCH_REG1[0], sizeof(mmSCRATCH_REG1)/sizeof(mmSCRATCH_REG1[0]), 0, 0 }, + { "mmSCRATCH_REG2", REG_MMIO, 0x2042, 1, &mmSCRATCH_REG2[0], sizeof(mmSCRATCH_REG2)/sizeof(mmSCRATCH_REG2[0]), 0, 0 }, + { "mmSCRATCH_REG3", REG_MMIO, 0x2043, 1, &mmSCRATCH_REG3[0], sizeof(mmSCRATCH_REG3)/sizeof(mmSCRATCH_REG3[0]), 0, 0 }, + { "mmSCRATCH_REG4", REG_MMIO, 0x2044, 1, &mmSCRATCH_REG4[0], sizeof(mmSCRATCH_REG4)/sizeof(mmSCRATCH_REG4[0]), 0, 0 }, + { "mmSCRATCH_REG5", REG_MMIO, 0x2045, 1, &mmSCRATCH_REG5[0], sizeof(mmSCRATCH_REG5)/sizeof(mmSCRATCH_REG5[0]), 0, 0 }, + { "mmSCRATCH_REG6", REG_MMIO, 0x2046, 1, &mmSCRATCH_REG6[0], sizeof(mmSCRATCH_REG6)/sizeof(mmSCRATCH_REG6[0]), 0, 0 }, + { "mmSCRATCH_REG7", REG_MMIO, 0x2047, 1, &mmSCRATCH_REG7[0], sizeof(mmSCRATCH_REG7)/sizeof(mmSCRATCH_REG7[0]), 0, 0 }, + { "mmCP_APPEND_DATA_HI", REG_MMIO, 0x204c, 1, &mmCP_APPEND_DATA_HI[0], sizeof(mmCP_APPEND_DATA_HI)/sizeof(mmCP_APPEND_DATA_HI[0]), 0, 0 }, + { "mmCP_APPEND_LAST_CS_FENCE_HI", REG_MMIO, 0x204d, 1, &mmCP_APPEND_LAST_CS_FENCE_HI[0], sizeof(mmCP_APPEND_LAST_CS_FENCE_HI)/sizeof(mmCP_APPEND_LAST_CS_FENCE_HI[0]), 0, 0 }, + { "mmCP_APPEND_LAST_PS_FENCE_HI", REG_MMIO, 0x204e, 1, &mmCP_APPEND_LAST_PS_FENCE_HI[0], sizeof(mmCP_APPEND_LAST_PS_FENCE_HI)/sizeof(mmCP_APPEND_LAST_PS_FENCE_HI[0]), 0, 0 }, + { "mmSCRATCH_UMSK", REG_MMIO, 0x2050, 1, &mmSCRATCH_UMSK[0], sizeof(mmSCRATCH_UMSK)/sizeof(mmSCRATCH_UMSK[0]), 0, 0 }, + { "mmSCRATCH_ADDR", REG_MMIO, 0x2051, 1, &mmSCRATCH_ADDR[0], sizeof(mmSCRATCH_ADDR)/sizeof(mmSCRATCH_ADDR[0]), 0, 0 }, + { "mmCP_PFP_ATOMIC_PREOP_LO", REG_MMIO, 0x2052, 1, &mmCP_PFP_ATOMIC_PREOP_LO[0], sizeof(mmCP_PFP_ATOMIC_PREOP_LO)/sizeof(mmCP_PFP_ATOMIC_PREOP_LO[0]), 0, 0 }, + { "mmCP_PFP_ATOMIC_PREOP_HI", REG_MMIO, 0x2053, 1, &mmCP_PFP_ATOMIC_PREOP_HI[0], sizeof(mmCP_PFP_ATOMIC_PREOP_HI)/sizeof(mmCP_PFP_ATOMIC_PREOP_HI[0]), 0, 0 }, + { "mmCP_PFP_GDS_ATOMIC0_PREOP_LO", REG_MMIO, 0x2054, 1, &mmCP_PFP_GDS_ATOMIC0_PREOP_LO[0], sizeof(mmCP_PFP_GDS_ATOMIC0_PREOP_LO)/sizeof(mmCP_PFP_GDS_ATOMIC0_PREOP_LO[0]), 0, 0 }, + { "mmCP_PFP_GDS_ATOMIC0_PREOP_HI", REG_MMIO, 0x2055, 1, &mmCP_PFP_GDS_ATOMIC0_PREOP_HI[0], sizeof(mmCP_PFP_GDS_ATOMIC0_PREOP_HI)/sizeof(mmCP_PFP_GDS_ATOMIC0_PREOP_HI[0]), 0, 0 }, + { "mmCP_PFP_GDS_ATOMIC1_PREOP_LO", REG_MMIO, 0x2056, 1, &mmCP_PFP_GDS_ATOMIC1_PREOP_LO[0], sizeof(mmCP_PFP_GDS_ATOMIC1_PREOP_LO)/sizeof(mmCP_PFP_GDS_ATOMIC1_PREOP_LO[0]), 0, 0 }, + { "mmCP_PFP_GDS_ATOMIC1_PREOP_HI", REG_MMIO, 0x2057, 1, &mmCP_PFP_GDS_ATOMIC1_PREOP_HI[0], sizeof(mmCP_PFP_GDS_ATOMIC1_PREOP_HI)/sizeof(mmCP_PFP_GDS_ATOMIC1_PREOP_HI[0]), 0, 0 }, + { "mmCP_APPEND_ADDR_LO", REG_MMIO, 0x2058, 1, &mmCP_APPEND_ADDR_LO[0], sizeof(mmCP_APPEND_ADDR_LO)/sizeof(mmCP_APPEND_ADDR_LO[0]), 0, 0 }, + { "mmCP_APPEND_ADDR_HI", REG_MMIO, 0x2059, 1, &mmCP_APPEND_ADDR_HI[0], sizeof(mmCP_APPEND_ADDR_HI)/sizeof(mmCP_APPEND_ADDR_HI[0]), 0, 0 }, + { "mmCP_APPEND_DATA_LO", REG_MMIO, 0x205a, 1, &mmCP_APPEND_DATA_LO[0], sizeof(mmCP_APPEND_DATA_LO)/sizeof(mmCP_APPEND_DATA_LO[0]), 0, 0 }, + { "mmCP_APPEND_LAST_CS_FENCE_LO", REG_MMIO, 0x205b, 1, &mmCP_APPEND_LAST_CS_FENCE_LO[0], sizeof(mmCP_APPEND_LAST_CS_FENCE_LO)/sizeof(mmCP_APPEND_LAST_CS_FENCE_LO[0]), 0, 0 }, + { "mmCP_APPEND_LAST_PS_FENCE_LO", REG_MMIO, 0x205c, 1, &mmCP_APPEND_LAST_PS_FENCE_LO[0], sizeof(mmCP_APPEND_LAST_PS_FENCE_LO)/sizeof(mmCP_APPEND_LAST_PS_FENCE_LO[0]), 0, 0 }, + { "mmCP_ATOMIC_PREOP_LO", REG_MMIO, 0x205d, 1, &mmCP_ATOMIC_PREOP_LO[0], sizeof(mmCP_ATOMIC_PREOP_LO)/sizeof(mmCP_ATOMIC_PREOP_LO[0]), 0, 0 }, + { "mmCP_ME_ATOMIC_PREOP_LO", REG_MMIO, 0x205d, 1, &mmCP_ME_ATOMIC_PREOP_LO[0], sizeof(mmCP_ME_ATOMIC_PREOP_LO)/sizeof(mmCP_ME_ATOMIC_PREOP_LO[0]), 0, 0 }, + { "mmCP_ATOMIC_PREOP_HI", REG_MMIO, 0x205e, 1, &mmCP_ATOMIC_PREOP_HI[0], sizeof(mmCP_ATOMIC_PREOP_HI)/sizeof(mmCP_ATOMIC_PREOP_HI[0]), 0, 0 }, + { "mmCP_ME_ATOMIC_PREOP_HI", REG_MMIO, 0x205e, 1, &mmCP_ME_ATOMIC_PREOP_HI[0], sizeof(mmCP_ME_ATOMIC_PREOP_HI)/sizeof(mmCP_ME_ATOMIC_PREOP_HI[0]), 0, 0 }, + { "mmCP_GDS_ATOMIC0_PREOP_LO", REG_MMIO, 0x205f, 1, &mmCP_GDS_ATOMIC0_PREOP_LO[0], sizeof(mmCP_GDS_ATOMIC0_PREOP_LO)/sizeof(mmCP_GDS_ATOMIC0_PREOP_LO[0]), 0, 0 }, + { "mmCP_ME_GDS_ATOMIC0_PREOP_LO", REG_MMIO, 0x205f, 1, &mmCP_ME_GDS_ATOMIC0_PREOP_LO[0], sizeof(mmCP_ME_GDS_ATOMIC0_PREOP_LO)/sizeof(mmCP_ME_GDS_ATOMIC0_PREOP_LO[0]), 0, 0 }, + { "mmCP_GDS_ATOMIC0_PREOP_HI", REG_MMIO, 0x2060, 1, &mmCP_GDS_ATOMIC0_PREOP_HI[0], sizeof(mmCP_GDS_ATOMIC0_PREOP_HI)/sizeof(mmCP_GDS_ATOMIC0_PREOP_HI[0]), 0, 0 }, + { "mmCP_ME_GDS_ATOMIC0_PREOP_HI", REG_MMIO, 0x2060, 1, &mmCP_ME_GDS_ATOMIC0_PREOP_HI[0], sizeof(mmCP_ME_GDS_ATOMIC0_PREOP_HI)/sizeof(mmCP_ME_GDS_ATOMIC0_PREOP_HI[0]), 0, 0 }, + { "mmCP_GDS_ATOMIC1_PREOP_LO", REG_MMIO, 0x2061, 1, &mmCP_GDS_ATOMIC1_PREOP_LO[0], sizeof(mmCP_GDS_ATOMIC1_PREOP_LO)/sizeof(mmCP_GDS_ATOMIC1_PREOP_LO[0]), 0, 0 }, + { "mmCP_ME_GDS_ATOMIC1_PREOP_LO", REG_MMIO, 0x2061, 1, &mmCP_ME_GDS_ATOMIC1_PREOP_LO[0], sizeof(mmCP_ME_GDS_ATOMIC1_PREOP_LO)/sizeof(mmCP_ME_GDS_ATOMIC1_PREOP_LO[0]), 0, 0 }, + { "mmCP_GDS_ATOMIC1_PREOP_HI", REG_MMIO, 0x2062, 1, &mmCP_GDS_ATOMIC1_PREOP_HI[0], sizeof(mmCP_GDS_ATOMIC1_PREOP_HI)/sizeof(mmCP_GDS_ATOMIC1_PREOP_HI[0]), 0, 0 }, + { "mmCP_ME_GDS_ATOMIC1_PREOP_HI", REG_MMIO, 0x2062, 1, &mmCP_ME_GDS_ATOMIC1_PREOP_HI[0], sizeof(mmCP_ME_GDS_ATOMIC1_PREOP_HI)/sizeof(mmCP_ME_GDS_ATOMIC1_PREOP_HI[0]), 0, 0 }, + { "mmCP_ME_MC_WADDR_LO", REG_MMIO, 0x2069, 1, &mmCP_ME_MC_WADDR_LO[0], sizeof(mmCP_ME_MC_WADDR_LO)/sizeof(mmCP_ME_MC_WADDR_LO[0]), 0, 0 }, + { "mmCP_ME_MC_WADDR_HI", REG_MMIO, 0x206a, 1, &mmCP_ME_MC_WADDR_HI[0], sizeof(mmCP_ME_MC_WADDR_HI)/sizeof(mmCP_ME_MC_WADDR_HI[0]), 0, 0 }, + { "mmCP_ME_MC_WDATA_LO", REG_MMIO, 0x206b, 1, &mmCP_ME_MC_WDATA_LO[0], sizeof(mmCP_ME_MC_WDATA_LO)/sizeof(mmCP_ME_MC_WDATA_LO[0]), 0, 0 }, + { "mmCP_ME_MC_WDATA_HI", REG_MMIO, 0x206c, 1, &mmCP_ME_MC_WDATA_HI[0], sizeof(mmCP_ME_MC_WDATA_HI)/sizeof(mmCP_ME_MC_WDATA_HI[0]), 0, 0 }, + { "mmCP_ME_MC_RADDR_LO", REG_MMIO, 0x206d, 1, &mmCP_ME_MC_RADDR_LO[0], sizeof(mmCP_ME_MC_RADDR_LO)/sizeof(mmCP_ME_MC_RADDR_LO[0]), 0, 0 }, + { "mmCP_ME_MC_RADDR_HI", REG_MMIO, 0x206e, 1, &mmCP_ME_MC_RADDR_HI[0], sizeof(mmCP_ME_MC_RADDR_HI)/sizeof(mmCP_ME_MC_RADDR_HI[0]), 0, 0 }, + { "mmCP_SEM_WAIT_TIMER", REG_MMIO, 0x206f, 1, &mmCP_SEM_WAIT_TIMER[0], sizeof(mmCP_SEM_WAIT_TIMER)/sizeof(mmCP_SEM_WAIT_TIMER[0]), 0, 0 }, + { "mmCP_SIG_SEM_ADDR_LO", REG_MMIO, 0x2070, 1, &mmCP_SIG_SEM_ADDR_LO[0], sizeof(mmCP_SIG_SEM_ADDR_LO)/sizeof(mmCP_SIG_SEM_ADDR_LO[0]), 0, 0 }, + { "mmCP_SIG_SEM_ADDR_HI", REG_MMIO, 0x2071, 1, &mmCP_SIG_SEM_ADDR_HI[0], sizeof(mmCP_SIG_SEM_ADDR_HI)/sizeof(mmCP_SIG_SEM_ADDR_HI[0]), 0, 0 }, + { "mmCP_WAIT_REG_MEM_TIMEOUT", REG_MMIO, 0x2074, 1, &mmCP_WAIT_REG_MEM_TIMEOUT[0], sizeof(mmCP_WAIT_REG_MEM_TIMEOUT)/sizeof(mmCP_WAIT_REG_MEM_TIMEOUT[0]), 0, 0 }, + { "mmCP_WAIT_SEM_ADDR_LO", REG_MMIO, 0x2075, 1, &mmCP_WAIT_SEM_ADDR_LO[0], sizeof(mmCP_WAIT_SEM_ADDR_LO)/sizeof(mmCP_WAIT_SEM_ADDR_LO[0]), 0, 0 }, + { "mmCP_WAIT_SEM_ADDR_HI", REG_MMIO, 0x2076, 1, &mmCP_WAIT_SEM_ADDR_HI[0], sizeof(mmCP_WAIT_SEM_ADDR_HI)/sizeof(mmCP_WAIT_SEM_ADDR_HI[0]), 0, 0 }, + { "mmCP_DMA_PFP_CONTROL", REG_MMIO, 0x2077, 1, &mmCP_DMA_PFP_CONTROL[0], sizeof(mmCP_DMA_PFP_CONTROL)/sizeof(mmCP_DMA_PFP_CONTROL[0]), 0, 0 }, + { "mmCP_DMA_ME_CONTROL", REG_MMIO, 0x2078, 1, &mmCP_DMA_ME_CONTROL[0], sizeof(mmCP_DMA_ME_CONTROL)/sizeof(mmCP_DMA_ME_CONTROL[0]), 0, 0 }, + { "mmCP_COHER_BASE_HI", REG_MMIO, 0x2079, 1, &mmCP_COHER_BASE_HI[0], sizeof(mmCP_COHER_BASE_HI)/sizeof(mmCP_COHER_BASE_HI[0]), 0, 0 }, + { "mmCP_COHER_START_DELAY", REG_MMIO, 0x207b, 1, &mmCP_COHER_START_DELAY[0], sizeof(mmCP_COHER_START_DELAY)/sizeof(mmCP_COHER_START_DELAY[0]), 0, 0 }, + { "mmCP_COHER_CNTL", REG_MMIO, 0x207c, 1, &mmCP_COHER_CNTL[0], sizeof(mmCP_COHER_CNTL)/sizeof(mmCP_COHER_CNTL[0]), 0, 0 }, + { "mmCP_COHER_SIZE", REG_MMIO, 0x207d, 1, &mmCP_COHER_SIZE[0], sizeof(mmCP_COHER_SIZE)/sizeof(mmCP_COHER_SIZE[0]), 0, 0 }, + { "mmCP_COHER_BASE", REG_MMIO, 0x207e, 1, &mmCP_COHER_BASE[0], sizeof(mmCP_COHER_BASE)/sizeof(mmCP_COHER_BASE[0]), 0, 0 }, + { "mmCP_COHER_STATUS", REG_MMIO, 0x207f, 1, &mmCP_COHER_STATUS[0], sizeof(mmCP_COHER_STATUS)/sizeof(mmCP_COHER_STATUS[0]), 0, 0 }, + { "mmCP_DMA_ME_SRC_ADDR", REG_MMIO, 0x2080, 1, &mmCP_DMA_ME_SRC_ADDR[0], sizeof(mmCP_DMA_ME_SRC_ADDR)/sizeof(mmCP_DMA_ME_SRC_ADDR[0]), 0, 0 }, + { "mmCP_DMA_ME_SRC_ADDR_HI", REG_MMIO, 0x2081, 1, &mmCP_DMA_ME_SRC_ADDR_HI[0], sizeof(mmCP_DMA_ME_SRC_ADDR_HI)/sizeof(mmCP_DMA_ME_SRC_ADDR_HI[0]), 0, 0 }, + { "mmCP_DMA_ME_DST_ADDR", REG_MMIO, 0x2082, 1, &mmCP_DMA_ME_DST_ADDR[0], sizeof(mmCP_DMA_ME_DST_ADDR)/sizeof(mmCP_DMA_ME_DST_ADDR[0]), 0, 0 }, + { "mmCP_DMA_ME_DST_ADDR_HI", REG_MMIO, 0x2083, 1, &mmCP_DMA_ME_DST_ADDR_HI[0], sizeof(mmCP_DMA_ME_DST_ADDR_HI)/sizeof(mmCP_DMA_ME_DST_ADDR_HI[0]), 0, 0 }, + { "mmCP_DMA_ME_COMMAND", REG_MMIO, 0x2084, 1, &mmCP_DMA_ME_COMMAND[0], sizeof(mmCP_DMA_ME_COMMAND)/sizeof(mmCP_DMA_ME_COMMAND[0]), 0, 0 }, + { "mmCP_DMA_PFP_SRC_ADDR", REG_MMIO, 0x2085, 1, &mmCP_DMA_PFP_SRC_ADDR[0], sizeof(mmCP_DMA_PFP_SRC_ADDR)/sizeof(mmCP_DMA_PFP_SRC_ADDR[0]), 0, 0 }, + { "mmCP_DMA_PFP_SRC_ADDR_HI", REG_MMIO, 0x2086, 1, &mmCP_DMA_PFP_SRC_ADDR_HI[0], sizeof(mmCP_DMA_PFP_SRC_ADDR_HI)/sizeof(mmCP_DMA_PFP_SRC_ADDR_HI[0]), 0, 0 }, + { "mmCP_DMA_PFP_DST_ADDR", REG_MMIO, 0x2087, 1, &mmCP_DMA_PFP_DST_ADDR[0], sizeof(mmCP_DMA_PFP_DST_ADDR)/sizeof(mmCP_DMA_PFP_DST_ADDR[0]), 0, 0 }, + { "mmCP_DMA_PFP_DST_ADDR_HI", REG_MMIO, 0x2088, 1, &mmCP_DMA_PFP_DST_ADDR_HI[0], sizeof(mmCP_DMA_PFP_DST_ADDR_HI)/sizeof(mmCP_DMA_PFP_DST_ADDR_HI[0]), 0, 0 }, + { "mmCP_DMA_PFP_COMMAND", REG_MMIO, 0x2089, 1, &mmCP_DMA_PFP_COMMAND[0], sizeof(mmCP_DMA_PFP_COMMAND)/sizeof(mmCP_DMA_PFP_COMMAND[0]), 0, 0 }, + { "mmCP_DMA_CNTL", REG_MMIO, 0x208a, 1, &mmCP_DMA_CNTL[0], sizeof(mmCP_DMA_CNTL)/sizeof(mmCP_DMA_CNTL[0]), 0, 0 }, + { "mmCP_DMA_READ_TAGS", REG_MMIO, 0x208b, 1, &mmCP_DMA_READ_TAGS[0], sizeof(mmCP_DMA_READ_TAGS)/sizeof(mmCP_DMA_READ_TAGS[0]), 0, 0 }, + { "mmCP_COHER_SIZE_HI", REG_MMIO, 0x208c, 1, &mmCP_COHER_SIZE_HI[0], sizeof(mmCP_COHER_SIZE_HI)/sizeof(mmCP_COHER_SIZE_HI[0]), 0, 0 }, + { "mmCP_PFP_IB_CONTROL", REG_MMIO, 0x208d, 1, &mmCP_PFP_IB_CONTROL[0], sizeof(mmCP_PFP_IB_CONTROL)/sizeof(mmCP_PFP_IB_CONTROL[0]), 0, 0 }, + { "mmCP_PFP_LOAD_CONTROL", REG_MMIO, 0x208e, 1, &mmCP_PFP_LOAD_CONTROL[0], sizeof(mmCP_PFP_LOAD_CONTROL)/sizeof(mmCP_PFP_LOAD_CONTROL[0]), 0, 0 }, + { "mmCP_SCRATCH_INDEX", REG_MMIO, 0x208f, 1, &mmCP_SCRATCH_INDEX[0], sizeof(mmCP_SCRATCH_INDEX)/sizeof(mmCP_SCRATCH_INDEX[0]), 0, 0 }, + { "mmCP_SCRATCH_DATA", REG_MMIO, 0x2090, 1, &mmCP_SCRATCH_DATA[0], sizeof(mmCP_SCRATCH_DATA)/sizeof(mmCP_SCRATCH_DATA[0]), 0, 0 }, + { "mmCP_RB_OFFSET", REG_MMIO, 0x2091, 1, &mmCP_RB_OFFSET[0], sizeof(mmCP_RB_OFFSET)/sizeof(mmCP_RB_OFFSET[0]), 0, 0 }, + { "mmCP_IB1_OFFSET", REG_MMIO, 0x2092, 1, &mmCP_IB1_OFFSET[0], sizeof(mmCP_IB1_OFFSET)/sizeof(mmCP_IB1_OFFSET[0]), 0, 0 }, + { "mmCP_IB2_OFFSET", REG_MMIO, 0x2093, 1, &mmCP_IB2_OFFSET[0], sizeof(mmCP_IB2_OFFSET)/sizeof(mmCP_IB2_OFFSET[0]), 0, 0 }, + { "mmCP_IB1_PREAMBLE_BEGIN", REG_MMIO, 0x2094, 1, &mmCP_IB1_PREAMBLE_BEGIN[0], sizeof(mmCP_IB1_PREAMBLE_BEGIN)/sizeof(mmCP_IB1_PREAMBLE_BEGIN[0]), 0, 0 }, + { "mmCP_IB1_PREAMBLE_END", REG_MMIO, 0x2095, 1, &mmCP_IB1_PREAMBLE_END[0], sizeof(mmCP_IB1_PREAMBLE_END)/sizeof(mmCP_IB1_PREAMBLE_END[0]), 0, 0 }, + { "mmCP_IB2_PREAMBLE_BEGIN", REG_MMIO, 0x2096, 1, &mmCP_IB2_PREAMBLE_BEGIN[0], sizeof(mmCP_IB2_PREAMBLE_BEGIN)/sizeof(mmCP_IB2_PREAMBLE_BEGIN[0]), 0, 0 }, + { "mmCP_IB2_PREAMBLE_END", REG_MMIO, 0x2097, 1, &mmCP_IB2_PREAMBLE_END[0], sizeof(mmCP_IB2_PREAMBLE_END)/sizeof(mmCP_IB2_PREAMBLE_END[0]), 0, 0 }, + { "mmCP_CE_IB1_OFFSET", REG_MMIO, 0x2098, 1, &mmCP_CE_IB1_OFFSET[0], sizeof(mmCP_CE_IB1_OFFSET)/sizeof(mmCP_CE_IB1_OFFSET[0]), 0, 0 }, + { "mmCP_CE_IB2_OFFSET", REG_MMIO, 0x2099, 1, &mmCP_CE_IB2_OFFSET[0], sizeof(mmCP_CE_IB2_OFFSET)/sizeof(mmCP_CE_IB2_OFFSET[0]), 0, 0 }, + { "mmCP_CE_COUNTER", REG_MMIO, 0x209a, 1, &mmCP_CE_COUNTER[0], sizeof(mmCP_CE_COUNTER)/sizeof(mmCP_CE_COUNTER[0]), 0, 0 }, + { "mmCP_CE_RB_OFFSET", REG_MMIO, 0x209b, 1, &mmCP_CE_RB_OFFSET[0], sizeof(mmCP_CE_RB_OFFSET)/sizeof(mmCP_CE_RB_OFFSET[0]), 0, 0 }, + { "mmCP_CE_INIT_CMD_BUFSZ", REG_MMIO, 0x20bd, 1, &mmCP_CE_INIT_CMD_BUFSZ[0], sizeof(mmCP_CE_INIT_CMD_BUFSZ)/sizeof(mmCP_CE_INIT_CMD_BUFSZ[0]), 0, 0 }, + { "mmCP_CE_IB1_CMD_BUFSZ", REG_MMIO, 0x20be, 1, &mmCP_CE_IB1_CMD_BUFSZ[0], sizeof(mmCP_CE_IB1_CMD_BUFSZ)/sizeof(mmCP_CE_IB1_CMD_BUFSZ[0]), 0, 0 }, + { "mmCP_CE_IB2_CMD_BUFSZ", REG_MMIO, 0x20bf, 1, &mmCP_CE_IB2_CMD_BUFSZ[0], sizeof(mmCP_CE_IB2_CMD_BUFSZ)/sizeof(mmCP_CE_IB2_CMD_BUFSZ[0]), 0, 0 }, + { "mmCP_IB1_CMD_BUFSZ", REG_MMIO, 0x20c0, 1, &mmCP_IB1_CMD_BUFSZ[0], sizeof(mmCP_IB1_CMD_BUFSZ)/sizeof(mmCP_IB1_CMD_BUFSZ[0]), 0, 0 }, + { "mmCP_IB2_CMD_BUFSZ", REG_MMIO, 0x20c1, 1, &mmCP_IB2_CMD_BUFSZ[0], sizeof(mmCP_IB2_CMD_BUFSZ)/sizeof(mmCP_IB2_CMD_BUFSZ[0]), 0, 0 }, + { "mmCP_ST_CMD_BUFSZ", REG_MMIO, 0x20c2, 1, &mmCP_ST_CMD_BUFSZ[0], sizeof(mmCP_ST_CMD_BUFSZ)/sizeof(mmCP_ST_CMD_BUFSZ[0]), 0, 0 }, + { "mmCP_CE_INIT_BASE_LO", REG_MMIO, 0x20c3, 1, &mmCP_CE_INIT_BASE_LO[0], sizeof(mmCP_CE_INIT_BASE_LO)/sizeof(mmCP_CE_INIT_BASE_LO[0]), 0, 0 }, + { "mmCP_CE_INIT_BASE_HI", REG_MMIO, 0x20c4, 1, &mmCP_CE_INIT_BASE_HI[0], sizeof(mmCP_CE_INIT_BASE_HI)/sizeof(mmCP_CE_INIT_BASE_HI[0]), 0, 0 }, + { "mmCP_CE_INIT_BUFSZ", REG_MMIO, 0x20c5, 1, &mmCP_CE_INIT_BUFSZ[0], sizeof(mmCP_CE_INIT_BUFSZ)/sizeof(mmCP_CE_INIT_BUFSZ[0]), 0, 0 }, + { "mmCP_CE_IB1_BASE_LO", REG_MMIO, 0x20c6, 1, &mmCP_CE_IB1_BASE_LO[0], sizeof(mmCP_CE_IB1_BASE_LO)/sizeof(mmCP_CE_IB1_BASE_LO[0]), 0, 0 }, + { "mmCP_CE_IB1_BASE_HI", REG_MMIO, 0x20c7, 1, &mmCP_CE_IB1_BASE_HI[0], sizeof(mmCP_CE_IB1_BASE_HI)/sizeof(mmCP_CE_IB1_BASE_HI[0]), 0, 0 }, + { "mmCP_CE_IB1_BUFSZ", REG_MMIO, 0x20c8, 1, &mmCP_CE_IB1_BUFSZ[0], sizeof(mmCP_CE_IB1_BUFSZ)/sizeof(mmCP_CE_IB1_BUFSZ[0]), 0, 0 }, + { "mmCP_CE_IB2_BASE_LO", REG_MMIO, 0x20c9, 1, &mmCP_CE_IB2_BASE_LO[0], sizeof(mmCP_CE_IB2_BASE_LO)/sizeof(mmCP_CE_IB2_BASE_LO[0]), 0, 0 }, + { "mmCP_CE_IB2_BASE_HI", REG_MMIO, 0x20ca, 1, &mmCP_CE_IB2_BASE_HI[0], sizeof(mmCP_CE_IB2_BASE_HI)/sizeof(mmCP_CE_IB2_BASE_HI[0]), 0, 0 }, + { "mmCP_CE_IB2_BUFSZ", REG_MMIO, 0x20cb, 1, &mmCP_CE_IB2_BUFSZ[0], sizeof(mmCP_CE_IB2_BUFSZ)/sizeof(mmCP_CE_IB2_BUFSZ[0]), 0, 0 }, + { "mmCP_IB1_BASE_LO", REG_MMIO, 0x20cc, 1, &mmCP_IB1_BASE_LO[0], sizeof(mmCP_IB1_BASE_LO)/sizeof(mmCP_IB1_BASE_LO[0]), 0, 0 }, + { "mmCP_IB1_BASE_HI", REG_MMIO, 0x20cd, 1, &mmCP_IB1_BASE_HI[0], sizeof(mmCP_IB1_BASE_HI)/sizeof(mmCP_IB1_BASE_HI[0]), 0, 0 }, + { "mmCP_IB1_BUFSZ", REG_MMIO, 0x20ce, 1, &mmCP_IB1_BUFSZ[0], sizeof(mmCP_IB1_BUFSZ)/sizeof(mmCP_IB1_BUFSZ[0]), 0, 0 }, + { "mmCP_IB2_BASE_LO", REG_MMIO, 0x20cf, 1, &mmCP_IB2_BASE_LO[0], sizeof(mmCP_IB2_BASE_LO)/sizeof(mmCP_IB2_BASE_LO[0]), 0, 0 }, + { "mmCP_IB2_BASE_HI", REG_MMIO, 0x20d0, 1, &mmCP_IB2_BASE_HI[0], sizeof(mmCP_IB2_BASE_HI)/sizeof(mmCP_IB2_BASE_HI[0]), 0, 0 }, + { "mmCP_IB2_BUFSZ", REG_MMIO, 0x20d1, 1, &mmCP_IB2_BUFSZ[0], sizeof(mmCP_IB2_BUFSZ)/sizeof(mmCP_IB2_BUFSZ[0]), 0, 0 }, + { "mmCP_ST_BASE_LO", REG_MMIO, 0x20d2, 1, &mmCP_ST_BASE_LO[0], sizeof(mmCP_ST_BASE_LO)/sizeof(mmCP_ST_BASE_LO[0]), 0, 0 }, + { "mmCP_ST_BASE_HI", REG_MMIO, 0x20d3, 1, &mmCP_ST_BASE_HI[0], sizeof(mmCP_ST_BASE_HI)/sizeof(mmCP_ST_BASE_HI[0]), 0, 0 }, + { "mmCP_ST_BUFSZ", REG_MMIO, 0x20d4, 1, &mmCP_ST_BUFSZ[0], sizeof(mmCP_ST_BUFSZ)/sizeof(mmCP_ST_BUFSZ[0]), 0, 0 }, + { "mmCP_EOP_DONE_EVENT_CNTL", REG_MMIO, 0x20d5, 1, &mmCP_EOP_DONE_EVENT_CNTL[0], sizeof(mmCP_EOP_DONE_EVENT_CNTL)/sizeof(mmCP_EOP_DONE_EVENT_CNTL[0]), 0, 0 }, + { "mmCP_EOP_DONE_DATA_CNTL", REG_MMIO, 0x20d6, 1, &mmCP_EOP_DONE_DATA_CNTL[0], sizeof(mmCP_EOP_DONE_DATA_CNTL)/sizeof(mmCP_EOP_DONE_DATA_CNTL[0]), 0, 0 }, + { "mmCP_EOP_DONE_CNTX_ID", REG_MMIO, 0x20d7, 1, &mmCP_EOP_DONE_CNTX_ID[0], sizeof(mmCP_EOP_DONE_CNTX_ID)/sizeof(mmCP_EOP_DONE_CNTX_ID[0]), 0, 0 }, + { "mmCP_PFP_COMPLETION_STATUS", REG_MMIO, 0x20ec, 1, &mmCP_PFP_COMPLETION_STATUS[0], sizeof(mmCP_PFP_COMPLETION_STATUS)/sizeof(mmCP_PFP_COMPLETION_STATUS[0]), 0, 0 }, + { "mmCP_CE_COMPLETION_STATUS", REG_MMIO, 0x20ed, 1, &mmCP_CE_COMPLETION_STATUS[0], sizeof(mmCP_CE_COMPLETION_STATUS)/sizeof(mmCP_CE_COMPLETION_STATUS[0]), 0, 0 }, + { "mmCP_PRED_NOT_VISIBLE", REG_MMIO, 0x20ee, 1, &mmCP_PRED_NOT_VISIBLE[0], sizeof(mmCP_PRED_NOT_VISIBLE)/sizeof(mmCP_PRED_NOT_VISIBLE[0]), 0, 0 }, + { "mmCP_PFP_METADATA_BASE_ADDR", REG_MMIO, 0x20f0, 1, &mmCP_PFP_METADATA_BASE_ADDR[0], sizeof(mmCP_PFP_METADATA_BASE_ADDR)/sizeof(mmCP_PFP_METADATA_BASE_ADDR[0]), 0, 0 }, + { "mmCP_PFP_METADATA_BASE_ADDR_HI", REG_MMIO, 0x20f1, 1, &mmCP_PFP_METADATA_BASE_ADDR_HI[0], sizeof(mmCP_PFP_METADATA_BASE_ADDR_HI)/sizeof(mmCP_PFP_METADATA_BASE_ADDR_HI[0]), 0, 0 }, + { "mmCP_CE_METADATA_BASE_ADDR", REG_MMIO, 0x20f2, 1, &mmCP_CE_METADATA_BASE_ADDR[0], sizeof(mmCP_CE_METADATA_BASE_ADDR)/sizeof(mmCP_CE_METADATA_BASE_ADDR[0]), 0, 0 }, + { "mmCP_CE_METADATA_BASE_ADDR_HI", REG_MMIO, 0x20f3, 1, &mmCP_CE_METADATA_BASE_ADDR_HI[0], sizeof(mmCP_CE_METADATA_BASE_ADDR_HI)/sizeof(mmCP_CE_METADATA_BASE_ADDR_HI[0]), 0, 0 }, + { "mmCP_DRAW_INDX_INDR_ADDR", REG_MMIO, 0x20f4, 1, &mmCP_DRAW_INDX_INDR_ADDR[0], sizeof(mmCP_DRAW_INDX_INDR_ADDR)/sizeof(mmCP_DRAW_INDX_INDR_ADDR[0]), 0, 0 }, + { "mmCP_DRAW_INDX_INDR_ADDR_HI", REG_MMIO, 0x20f5, 1, &mmCP_DRAW_INDX_INDR_ADDR_HI[0], sizeof(mmCP_DRAW_INDX_INDR_ADDR_HI)/sizeof(mmCP_DRAW_INDX_INDR_ADDR_HI[0]), 0, 0 }, + { "mmCP_DISPATCH_INDR_ADDR", REG_MMIO, 0x20f6, 1, &mmCP_DISPATCH_INDR_ADDR[0], sizeof(mmCP_DISPATCH_INDR_ADDR)/sizeof(mmCP_DISPATCH_INDR_ADDR[0]), 0, 0 }, + { "mmCP_DISPATCH_INDR_ADDR_HI", REG_MMIO, 0x20f7, 1, &mmCP_DISPATCH_INDR_ADDR_HI[0], sizeof(mmCP_DISPATCH_INDR_ADDR_HI)/sizeof(mmCP_DISPATCH_INDR_ADDR_HI[0]), 0, 0 }, + { "mmCP_INDEX_BASE_ADDR", REG_MMIO, 0x20f8, 1, &mmCP_INDEX_BASE_ADDR[0], sizeof(mmCP_INDEX_BASE_ADDR)/sizeof(mmCP_INDEX_BASE_ADDR[0]), 0, 0 }, + { "mmCP_INDEX_BASE_ADDR_HI", REG_MMIO, 0x20f9, 1, &mmCP_INDEX_BASE_ADDR_HI[0], sizeof(mmCP_INDEX_BASE_ADDR_HI)/sizeof(mmCP_INDEX_BASE_ADDR_HI[0]), 0, 0 }, + { "mmCP_INDEX_TYPE", REG_MMIO, 0x20fa, 1, &mmCP_INDEX_TYPE[0], sizeof(mmCP_INDEX_TYPE)/sizeof(mmCP_INDEX_TYPE[0]), 0, 0 }, + { "mmCP_GDS_BKUP_ADDR", REG_MMIO, 0x20fb, 1, &mmCP_GDS_BKUP_ADDR[0], sizeof(mmCP_GDS_BKUP_ADDR)/sizeof(mmCP_GDS_BKUP_ADDR[0]), 0, 0 }, + { "mmCP_GDS_BKUP_ADDR_HI", REG_MMIO, 0x20fc, 1, &mmCP_GDS_BKUP_ADDR_HI[0], sizeof(mmCP_GDS_BKUP_ADDR_HI)/sizeof(mmCP_GDS_BKUP_ADDR_HI[0]), 0, 0 }, + { "mmCP_SAMPLE_STATUS", REG_MMIO, 0x20fd, 1, &mmCP_SAMPLE_STATUS[0], sizeof(mmCP_SAMPLE_STATUS)/sizeof(mmCP_SAMPLE_STATUS[0]), 0, 0 }, + { "mmCP_ME_COHER_CNTL", REG_MMIO, 0x20fe, 1, &mmCP_ME_COHER_CNTL[0], sizeof(mmCP_ME_COHER_CNTL)/sizeof(mmCP_ME_COHER_CNTL[0]), 0, 0 }, + { "mmCP_ME_COHER_SIZE", REG_MMIO, 0x20ff, 1, &mmCP_ME_COHER_SIZE[0], sizeof(mmCP_ME_COHER_SIZE)/sizeof(mmCP_ME_COHER_SIZE[0]), 0, 0 }, + { "mmCP_ME_COHER_SIZE_HI", REG_MMIO, 0x2100, 1, &mmCP_ME_COHER_SIZE_HI[0], sizeof(mmCP_ME_COHER_SIZE_HI)/sizeof(mmCP_ME_COHER_SIZE_HI[0]), 0, 0 }, + { "mmCP_ME_COHER_BASE", REG_MMIO, 0x2101, 1, &mmCP_ME_COHER_BASE[0], sizeof(mmCP_ME_COHER_BASE)/sizeof(mmCP_ME_COHER_BASE[0]), 0, 0 }, + { "mmCP_ME_COHER_BASE_HI", REG_MMIO, 0x2102, 1, &mmCP_ME_COHER_BASE_HI[0], sizeof(mmCP_ME_COHER_BASE_HI)/sizeof(mmCP_ME_COHER_BASE_HI[0]), 0, 0 }, + { "mmCP_ME_COHER_STATUS", REG_MMIO, 0x2103, 1, &mmCP_ME_COHER_STATUS[0], sizeof(mmCP_ME_COHER_STATUS)/sizeof(mmCP_ME_COHER_STATUS[0]), 0, 0 }, + { "mmRLC_GPM_PERF_COUNT_0", REG_MMIO, 0x2140, 1, &mmRLC_GPM_PERF_COUNT_0[0], sizeof(mmRLC_GPM_PERF_COUNT_0)/sizeof(mmRLC_GPM_PERF_COUNT_0[0]), 0, 0 }, + { "mmRLC_GPM_PERF_COUNT_1", REG_MMIO, 0x2141, 1, &mmRLC_GPM_PERF_COUNT_1[0], sizeof(mmRLC_GPM_PERF_COUNT_1)/sizeof(mmRLC_GPM_PERF_COUNT_1[0]), 0, 0 }, + { "mmGRBM_GFX_INDEX", REG_MMIO, 0x2200, 1, &mmGRBM_GFX_INDEX[0], sizeof(mmGRBM_GFX_INDEX)/sizeof(mmGRBM_GFX_INDEX[0]), 0, 0 }, + { "mmVGT_GSVS_RING_SIZE", REG_MMIO, 0x2241, 1, &mmVGT_GSVS_RING_SIZE[0], sizeof(mmVGT_GSVS_RING_SIZE)/sizeof(mmVGT_GSVS_RING_SIZE[0]), 0, 0 }, + { "mmVGT_PRIMITIVE_TYPE", REG_MMIO, 0x2242, 1, &mmVGT_PRIMITIVE_TYPE[0], sizeof(mmVGT_PRIMITIVE_TYPE)/sizeof(mmVGT_PRIMITIVE_TYPE[0]), 0, 0 }, + { "mmVGT_INDEX_TYPE", REG_MMIO, 0x2243, 1, &mmVGT_INDEX_TYPE[0], sizeof(mmVGT_INDEX_TYPE)/sizeof(mmVGT_INDEX_TYPE[0]), 0, 0 }, + { "mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0", REG_MMIO, 0x2244, 1, &mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0[0], sizeof(mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0)/sizeof(mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0[0]), 0, 0 }, + { "mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1", REG_MMIO, 0x2245, 1, &mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1[0], sizeof(mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1)/sizeof(mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1[0]), 0, 0 }, + { "mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2", REG_MMIO, 0x2246, 1, &mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2[0], sizeof(mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2)/sizeof(mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2[0]), 0, 0 }, + { "mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3", REG_MMIO, 0x2247, 1, &mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3[0], sizeof(mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3)/sizeof(mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3[0]), 0, 0 }, + { "mmVGT_MAX_VTX_INDX", REG_MMIO, 0x2248, 1, &mmVGT_MAX_VTX_INDX[0], sizeof(mmVGT_MAX_VTX_INDX)/sizeof(mmVGT_MAX_VTX_INDX[0]), 0, 0 }, + { "mmVGT_MIN_VTX_INDX", REG_MMIO, 0x2249, 1, &mmVGT_MIN_VTX_INDX[0], sizeof(mmVGT_MIN_VTX_INDX)/sizeof(mmVGT_MIN_VTX_INDX[0]), 0, 0 }, + { "mmVGT_INDX_OFFSET", REG_MMIO, 0x224a, 1, &mmVGT_INDX_OFFSET[0], sizeof(mmVGT_INDX_OFFSET)/sizeof(mmVGT_INDX_OFFSET[0]), 0, 0 }, + { "mmVGT_MULTI_PRIM_IB_RESET_EN", REG_MMIO, 0x224b, 1, &mmVGT_MULTI_PRIM_IB_RESET_EN[0], sizeof(mmVGT_MULTI_PRIM_IB_RESET_EN)/sizeof(mmVGT_MULTI_PRIM_IB_RESET_EN[0]), 0, 0 }, + { "mmVGT_NUM_INDICES", REG_MMIO, 0x224c, 1, &mmVGT_NUM_INDICES[0], sizeof(mmVGT_NUM_INDICES)/sizeof(mmVGT_NUM_INDICES[0]), 0, 0 }, + { "mmVGT_NUM_INSTANCES", REG_MMIO, 0x224d, 1, &mmVGT_NUM_INSTANCES[0], sizeof(mmVGT_NUM_INSTANCES)/sizeof(mmVGT_NUM_INSTANCES[0]), 0, 0 }, + { "mmVGT_TF_RING_SIZE", REG_MMIO, 0x224e, 1, &mmVGT_TF_RING_SIZE[0], sizeof(mmVGT_TF_RING_SIZE)/sizeof(mmVGT_TF_RING_SIZE[0]), 0, 0 }, + { "mmVGT_HS_OFFCHIP_PARAM", REG_MMIO, 0x224f, 1, &mmVGT_HS_OFFCHIP_PARAM[0], sizeof(mmVGT_HS_OFFCHIP_PARAM)/sizeof(mmVGT_HS_OFFCHIP_PARAM[0]), 0, 0 }, + { "mmVGT_TF_MEMORY_BASE", REG_MMIO, 0x2250, 1, &mmVGT_TF_MEMORY_BASE[0], sizeof(mmVGT_TF_MEMORY_BASE)/sizeof(mmVGT_TF_MEMORY_BASE[0]), 0, 0 }, + { "mmVGT_TF_MEMORY_BASE_HI", REG_MMIO, 0x2251, 1, &mmVGT_TF_MEMORY_BASE_HI[0], sizeof(mmVGT_TF_MEMORY_BASE_HI)/sizeof(mmVGT_TF_MEMORY_BASE_HI[0]), 0, 0 }, + { "mmWD_POS_BUF_BASE", REG_MMIO, 0x2252, 1, &mmWD_POS_BUF_BASE[0], sizeof(mmWD_POS_BUF_BASE)/sizeof(mmWD_POS_BUF_BASE[0]), 0, 0 }, + { "mmWD_POS_BUF_BASE_HI", REG_MMIO, 0x2253, 1, &mmWD_POS_BUF_BASE_HI[0], sizeof(mmWD_POS_BUF_BASE_HI)/sizeof(mmWD_POS_BUF_BASE_HI[0]), 0, 0 }, + { "mmWD_CNTL_SB_BUF_BASE", REG_MMIO, 0x2254, 1, &mmWD_CNTL_SB_BUF_BASE[0], sizeof(mmWD_CNTL_SB_BUF_BASE)/sizeof(mmWD_CNTL_SB_BUF_BASE[0]), 0, 0 }, + { "mmWD_CNTL_SB_BUF_BASE_HI", REG_MMIO, 0x2255, 1, &mmWD_CNTL_SB_BUF_BASE_HI[0], sizeof(mmWD_CNTL_SB_BUF_BASE_HI)/sizeof(mmWD_CNTL_SB_BUF_BASE_HI[0]), 0, 0 }, + { "mmWD_INDEX_BUF_BASE", REG_MMIO, 0x2256, 1, &mmWD_INDEX_BUF_BASE[0], sizeof(mmWD_INDEX_BUF_BASE)/sizeof(mmWD_INDEX_BUF_BASE[0]), 0, 0 }, + { "mmWD_INDEX_BUF_BASE_HI", REG_MMIO, 0x2257, 1, &mmWD_INDEX_BUF_BASE_HI[0], sizeof(mmWD_INDEX_BUF_BASE_HI)/sizeof(mmWD_INDEX_BUF_BASE_HI[0]), 0, 0 }, + { "mmIA_MULTI_VGT_PARAM", REG_MMIO, 0x2258, 1, &mmIA_MULTI_VGT_PARAM[0], sizeof(mmIA_MULTI_VGT_PARAM)/sizeof(mmIA_MULTI_VGT_PARAM[0]), 0, 0 }, + { "mmVGT_OBJECT_ID", REG_MMIO, 0x2259, 1, &mmVGT_OBJECT_ID[0], sizeof(mmVGT_OBJECT_ID)/sizeof(mmVGT_OBJECT_ID[0]), 0, 0 }, + { "mmVGT_INSTANCE_BASE_ID", REG_MMIO, 0x225a, 1, &mmVGT_INSTANCE_BASE_ID[0], sizeof(mmVGT_INSTANCE_BASE_ID)/sizeof(mmVGT_INSTANCE_BASE_ID[0]), 0, 0 }, + { "mmPA_SU_LINE_STIPPLE_VALUE", REG_MMIO, 0x2280, 1, &mmPA_SU_LINE_STIPPLE_VALUE[0], sizeof(mmPA_SU_LINE_STIPPLE_VALUE)/sizeof(mmPA_SU_LINE_STIPPLE_VALUE[0]), 0, 0 }, + { "mmPA_SC_LINE_STIPPLE_STATE", REG_MMIO, 0x2281, 1, &mmPA_SC_LINE_STIPPLE_STATE[0], sizeof(mmPA_SC_LINE_STIPPLE_STATE)/sizeof(mmPA_SC_LINE_STIPPLE_STATE[0]), 0, 0 }, + { "mmPA_SC_SCREEN_EXTENT_MIN_0", REG_MMIO, 0x2284, 1, &mmPA_SC_SCREEN_EXTENT_MIN_0[0], sizeof(mmPA_SC_SCREEN_EXTENT_MIN_0)/sizeof(mmPA_SC_SCREEN_EXTENT_MIN_0[0]), 0, 0 }, + { "mmPA_SC_SCREEN_EXTENT_MAX_0", REG_MMIO, 0x2285, 1, &mmPA_SC_SCREEN_EXTENT_MAX_0[0], sizeof(mmPA_SC_SCREEN_EXTENT_MAX_0)/sizeof(mmPA_SC_SCREEN_EXTENT_MAX_0[0]), 0, 0 }, + { "mmPA_SC_SCREEN_EXTENT_MIN_1", REG_MMIO, 0x2286, 1, &mmPA_SC_SCREEN_EXTENT_MIN_1[0], sizeof(mmPA_SC_SCREEN_EXTENT_MIN_1)/sizeof(mmPA_SC_SCREEN_EXTENT_MIN_1[0]), 0, 0 }, + { "mmPA_SC_SCREEN_EXTENT_MAX_1", REG_MMIO, 0x228b, 1, &mmPA_SC_SCREEN_EXTENT_MAX_1[0], sizeof(mmPA_SC_SCREEN_EXTENT_MAX_1)/sizeof(mmPA_SC_SCREEN_EXTENT_MAX_1[0]), 0, 0 }, + { "mmPA_SC_P3D_TRAP_SCREEN_HV_EN", REG_MMIO, 0x22a0, 1, &mmPA_SC_P3D_TRAP_SCREEN_HV_EN[0], sizeof(mmPA_SC_P3D_TRAP_SCREEN_HV_EN)/sizeof(mmPA_SC_P3D_TRAP_SCREEN_HV_EN[0]), 0, 0 }, + { "mmPA_SC_P3D_TRAP_SCREEN_H", REG_MMIO, 0x22a1, 1, &mmPA_SC_P3D_TRAP_SCREEN_H[0], sizeof(mmPA_SC_P3D_TRAP_SCREEN_H)/sizeof(mmPA_SC_P3D_TRAP_SCREEN_H[0]), 0, 0 }, + { "mmPA_SC_P3D_TRAP_SCREEN_V", REG_MMIO, 0x22a2, 1, &mmPA_SC_P3D_TRAP_SCREEN_V[0], sizeof(mmPA_SC_P3D_TRAP_SCREEN_V)/sizeof(mmPA_SC_P3D_TRAP_SCREEN_V[0]), 0, 0 }, + { "mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE", REG_MMIO, 0x22a3, 1, &mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE[0], sizeof(mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE)/sizeof(mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE[0]), 0, 0 }, + { "mmPA_SC_P3D_TRAP_SCREEN_COUNT", REG_MMIO, 0x22a4, 1, &mmPA_SC_P3D_TRAP_SCREEN_COUNT[0], sizeof(mmPA_SC_P3D_TRAP_SCREEN_COUNT)/sizeof(mmPA_SC_P3D_TRAP_SCREEN_COUNT[0]), 0, 0 }, + { "mmPA_SC_HP3D_TRAP_SCREEN_HV_EN", REG_MMIO, 0x22a8, 1, &mmPA_SC_HP3D_TRAP_SCREEN_HV_EN[0], sizeof(mmPA_SC_HP3D_TRAP_SCREEN_HV_EN)/sizeof(mmPA_SC_HP3D_TRAP_SCREEN_HV_EN[0]), 0, 0 }, + { "mmPA_SC_HP3D_TRAP_SCREEN_H", REG_MMIO, 0x22a9, 1, &mmPA_SC_HP3D_TRAP_SCREEN_H[0], sizeof(mmPA_SC_HP3D_TRAP_SCREEN_H)/sizeof(mmPA_SC_HP3D_TRAP_SCREEN_H[0]), 0, 0 }, + { "mmPA_SC_HP3D_TRAP_SCREEN_V", REG_MMIO, 0x22aa, 1, &mmPA_SC_HP3D_TRAP_SCREEN_V[0], sizeof(mmPA_SC_HP3D_TRAP_SCREEN_V)/sizeof(mmPA_SC_HP3D_TRAP_SCREEN_V[0]), 0, 0 }, + { "mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE", REG_MMIO, 0x22ab, 1, &mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE[0], sizeof(mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE)/sizeof(mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE[0]), 0, 0 }, + { "mmPA_SC_HP3D_TRAP_SCREEN_COUNT", REG_MMIO, 0x22ac, 1, &mmPA_SC_HP3D_TRAP_SCREEN_COUNT[0], sizeof(mmPA_SC_HP3D_TRAP_SCREEN_COUNT)/sizeof(mmPA_SC_HP3D_TRAP_SCREEN_COUNT[0]), 0, 0 }, + { "mmPA_SC_TRAP_SCREEN_HV_EN", REG_MMIO, 0x22b0, 1, &mmPA_SC_TRAP_SCREEN_HV_EN[0], sizeof(mmPA_SC_TRAP_SCREEN_HV_EN)/sizeof(mmPA_SC_TRAP_SCREEN_HV_EN[0]), 0, 0 }, + { "mmPA_SC_TRAP_SCREEN_H", REG_MMIO, 0x22b1, 1, &mmPA_SC_TRAP_SCREEN_H[0], sizeof(mmPA_SC_TRAP_SCREEN_H)/sizeof(mmPA_SC_TRAP_SCREEN_H[0]), 0, 0 }, + { "mmPA_SC_TRAP_SCREEN_V", REG_MMIO, 0x22b2, 1, &mmPA_SC_TRAP_SCREEN_V[0], sizeof(mmPA_SC_TRAP_SCREEN_V)/sizeof(mmPA_SC_TRAP_SCREEN_V[0]), 0, 0 }, + { "mmPA_SC_TRAP_SCREEN_OCCURRENCE", REG_MMIO, 0x22b3, 1, &mmPA_SC_TRAP_SCREEN_OCCURRENCE[0], sizeof(mmPA_SC_TRAP_SCREEN_OCCURRENCE)/sizeof(mmPA_SC_TRAP_SCREEN_OCCURRENCE[0]), 0, 0 }, + { "mmPA_SC_TRAP_SCREEN_COUNT", REG_MMIO, 0x22b4, 1, &mmPA_SC_TRAP_SCREEN_COUNT[0], sizeof(mmPA_SC_TRAP_SCREEN_COUNT)/sizeof(mmPA_SC_TRAP_SCREEN_COUNT[0]), 0, 0 }, + { "mmSQ_THREAD_TRACE_BASE", REG_MMIO, 0x2330, 1, &mmSQ_THREAD_TRACE_BASE[0], sizeof(mmSQ_THREAD_TRACE_BASE)/sizeof(mmSQ_THREAD_TRACE_BASE[0]), 0, 0 }, + { "mmSQ_THREAD_TRACE_SIZE", REG_MMIO, 0x2331, 1, &mmSQ_THREAD_TRACE_SIZE[0], sizeof(mmSQ_THREAD_TRACE_SIZE)/sizeof(mmSQ_THREAD_TRACE_SIZE[0]), 0, 0 }, + { "mmSQ_THREAD_TRACE_MASK", REG_MMIO, 0x2332, 1, &mmSQ_THREAD_TRACE_MASK[0], sizeof(mmSQ_THREAD_TRACE_MASK)/sizeof(mmSQ_THREAD_TRACE_MASK[0]), 0, 0 }, + { "mmSQ_THREAD_TRACE_TOKEN_MASK", REG_MMIO, 0x2333, 1, &mmSQ_THREAD_TRACE_TOKEN_MASK[0], sizeof(mmSQ_THREAD_TRACE_TOKEN_MASK)/sizeof(mmSQ_THREAD_TRACE_TOKEN_MASK[0]), 0, 0 }, + { "mmSQ_THREAD_TRACE_PERF_MASK", REG_MMIO, 0x2334, 1, &mmSQ_THREAD_TRACE_PERF_MASK[0], sizeof(mmSQ_THREAD_TRACE_PERF_MASK)/sizeof(mmSQ_THREAD_TRACE_PERF_MASK[0]), 0, 0 }, + { "mmSQ_THREAD_TRACE_CTRL", REG_MMIO, 0x2335, 1, &mmSQ_THREAD_TRACE_CTRL[0], sizeof(mmSQ_THREAD_TRACE_CTRL)/sizeof(mmSQ_THREAD_TRACE_CTRL[0]), 0, 0 }, + { "mmSQ_THREAD_TRACE_MODE", REG_MMIO, 0x2336, 1, &mmSQ_THREAD_TRACE_MODE[0], sizeof(mmSQ_THREAD_TRACE_MODE)/sizeof(mmSQ_THREAD_TRACE_MODE[0]), 0, 0 }, + { "mmSQ_THREAD_TRACE_BASE2", REG_MMIO, 0x2337, 1, &mmSQ_THREAD_TRACE_BASE2[0], sizeof(mmSQ_THREAD_TRACE_BASE2)/sizeof(mmSQ_THREAD_TRACE_BASE2[0]), 0, 0 }, + { "mmSQ_THREAD_TRACE_TOKEN_MASK2", REG_MMIO, 0x2338, 1, &mmSQ_THREAD_TRACE_TOKEN_MASK2[0], sizeof(mmSQ_THREAD_TRACE_TOKEN_MASK2)/sizeof(mmSQ_THREAD_TRACE_TOKEN_MASK2[0]), 0, 0 }, + { "mmSQ_THREAD_TRACE_WPTR", REG_MMIO, 0x2339, 1, &mmSQ_THREAD_TRACE_WPTR[0], sizeof(mmSQ_THREAD_TRACE_WPTR)/sizeof(mmSQ_THREAD_TRACE_WPTR[0]), 0, 0 }, + { "mmSQ_THREAD_TRACE_STATUS", REG_MMIO, 0x233a, 1, &mmSQ_THREAD_TRACE_STATUS[0], sizeof(mmSQ_THREAD_TRACE_STATUS)/sizeof(mmSQ_THREAD_TRACE_STATUS[0]), 0, 0 }, + { "mmSQ_THREAD_TRACE_HIWATER", REG_MMIO, 0x233b, 1, &mmSQ_THREAD_TRACE_HIWATER[0], sizeof(mmSQ_THREAD_TRACE_HIWATER)/sizeof(mmSQ_THREAD_TRACE_HIWATER[0]), 0, 0 }, + { "mmSQ_THREAD_TRACE_CNTR", REG_MMIO, 0x233c, 1, &mmSQ_THREAD_TRACE_CNTR[0], sizeof(mmSQ_THREAD_TRACE_CNTR)/sizeof(mmSQ_THREAD_TRACE_CNTR[0]), 0, 0 }, + { "mmSQ_THREAD_TRACE_USERDATA_0", REG_MMIO, 0x2340, 1, &mmSQ_THREAD_TRACE_USERDATA_0[0], sizeof(mmSQ_THREAD_TRACE_USERDATA_0)/sizeof(mmSQ_THREAD_TRACE_USERDATA_0[0]), 0, 0 }, + { "mmSQ_THREAD_TRACE_USERDATA_1", REG_MMIO, 0x2341, 1, &mmSQ_THREAD_TRACE_USERDATA_1[0], sizeof(mmSQ_THREAD_TRACE_USERDATA_1)/sizeof(mmSQ_THREAD_TRACE_USERDATA_1[0]), 0, 0 }, + { "mmSQ_THREAD_TRACE_USERDATA_2", REG_MMIO, 0x2342, 1, &mmSQ_THREAD_TRACE_USERDATA_2[0], sizeof(mmSQ_THREAD_TRACE_USERDATA_2)/sizeof(mmSQ_THREAD_TRACE_USERDATA_2[0]), 0, 0 }, + { "mmSQ_THREAD_TRACE_USERDATA_3", REG_MMIO, 0x2343, 1, &mmSQ_THREAD_TRACE_USERDATA_3[0], sizeof(mmSQ_THREAD_TRACE_USERDATA_3)/sizeof(mmSQ_THREAD_TRACE_USERDATA_3[0]), 0, 0 }, + { "mmSQC_CACHES", REG_MMIO, 0x2348, 1, &mmSQC_CACHES[0], sizeof(mmSQC_CACHES)/sizeof(mmSQC_CACHES[0]), 0, 0 }, + { "mmSQC_WRITEBACK", REG_MMIO, 0x2349, 1, &mmSQC_WRITEBACK[0], sizeof(mmSQC_WRITEBACK)/sizeof(mmSQC_WRITEBACK[0]), 0, 0 }, + { "mmTA_CS_BC_BASE_ADDR", REG_MMIO, 0x2380, 1, &mmTA_CS_BC_BASE_ADDR[0], sizeof(mmTA_CS_BC_BASE_ADDR)/sizeof(mmTA_CS_BC_BASE_ADDR[0]), 0, 0 }, + { "mmTA_CS_BC_BASE_ADDR_HI", REG_MMIO, 0x2381, 1, &mmTA_CS_BC_BASE_ADDR_HI[0], sizeof(mmTA_CS_BC_BASE_ADDR_HI)/sizeof(mmTA_CS_BC_BASE_ADDR_HI[0]), 0, 0 }, + { "mmTA_GRAD_ADJ_UCONFIG", REG_MMIO, 0x2382, 1, &mmTA_GRAD_ADJ_UCONFIG[0], sizeof(mmTA_GRAD_ADJ_UCONFIG)/sizeof(mmTA_GRAD_ADJ_UCONFIG[0]), 0, 0 }, + { "mmDB_OCCLUSION_COUNT0_LOW", REG_MMIO, 0x23c0, 1, &mmDB_OCCLUSION_COUNT0_LOW[0], sizeof(mmDB_OCCLUSION_COUNT0_LOW)/sizeof(mmDB_OCCLUSION_COUNT0_LOW[0]), 0, 0 }, + { "mmDB_OCCLUSION_COUNT0_HI", REG_MMIO, 0x23c1, 1, &mmDB_OCCLUSION_COUNT0_HI[0], sizeof(mmDB_OCCLUSION_COUNT0_HI)/sizeof(mmDB_OCCLUSION_COUNT0_HI[0]), 0, 0 }, + { "mmDB_OCCLUSION_COUNT1_LOW", REG_MMIO, 0x23c2, 1, &mmDB_OCCLUSION_COUNT1_LOW[0], sizeof(mmDB_OCCLUSION_COUNT1_LOW)/sizeof(mmDB_OCCLUSION_COUNT1_LOW[0]), 0, 0 }, + { "mmDB_OCCLUSION_COUNT1_HI", REG_MMIO, 0x23c3, 1, &mmDB_OCCLUSION_COUNT1_HI[0], sizeof(mmDB_OCCLUSION_COUNT1_HI)/sizeof(mmDB_OCCLUSION_COUNT1_HI[0]), 0, 0 }, + { "mmDB_OCCLUSION_COUNT2_LOW", REG_MMIO, 0x23c4, 1, &mmDB_OCCLUSION_COUNT2_LOW[0], sizeof(mmDB_OCCLUSION_COUNT2_LOW)/sizeof(mmDB_OCCLUSION_COUNT2_LOW[0]), 0, 0 }, + { "mmDB_OCCLUSION_COUNT2_HI", REG_MMIO, 0x23c5, 1, &mmDB_OCCLUSION_COUNT2_HI[0], sizeof(mmDB_OCCLUSION_COUNT2_HI)/sizeof(mmDB_OCCLUSION_COUNT2_HI[0]), 0, 0 }, + { "mmDB_OCCLUSION_COUNT3_LOW", REG_MMIO, 0x23c6, 1, &mmDB_OCCLUSION_COUNT3_LOW[0], sizeof(mmDB_OCCLUSION_COUNT3_LOW)/sizeof(mmDB_OCCLUSION_COUNT3_LOW[0]), 0, 0 }, + { "mmDB_OCCLUSION_COUNT3_HI", REG_MMIO, 0x23c7, 1, &mmDB_OCCLUSION_COUNT3_HI[0], sizeof(mmDB_OCCLUSION_COUNT3_HI)/sizeof(mmDB_OCCLUSION_COUNT3_HI[0]), 0, 0 }, + { "mmDB_ZPASS_COUNT_LOW", REG_MMIO, 0x23fe, 1, &mmDB_ZPASS_COUNT_LOW[0], sizeof(mmDB_ZPASS_COUNT_LOW)/sizeof(mmDB_ZPASS_COUNT_LOW[0]), 0, 0 }, + { "mmDB_ZPASS_COUNT_HI", REG_MMIO, 0x23ff, 1, &mmDB_ZPASS_COUNT_HI[0], sizeof(mmDB_ZPASS_COUNT_HI)/sizeof(mmDB_ZPASS_COUNT_HI[0]), 0, 0 }, + { "mmGDS_RD_ADDR", REG_MMIO, 0x2400, 1, &mmGDS_RD_ADDR[0], sizeof(mmGDS_RD_ADDR)/sizeof(mmGDS_RD_ADDR[0]), 0, 0 }, + { "mmGDS_RD_DATA", REG_MMIO, 0x2401, 1, &mmGDS_RD_DATA[0], sizeof(mmGDS_RD_DATA)/sizeof(mmGDS_RD_DATA[0]), 0, 0 }, + { "mmGDS_RD_BURST_ADDR", REG_MMIO, 0x2402, 1, &mmGDS_RD_BURST_ADDR[0], sizeof(mmGDS_RD_BURST_ADDR)/sizeof(mmGDS_RD_BURST_ADDR[0]), 0, 0 }, + { "mmGDS_RD_BURST_COUNT", REG_MMIO, 0x2403, 1, &mmGDS_RD_BURST_COUNT[0], sizeof(mmGDS_RD_BURST_COUNT)/sizeof(mmGDS_RD_BURST_COUNT[0]), 0, 0 }, + { "mmGDS_RD_BURST_DATA", REG_MMIO, 0x2404, 1, &mmGDS_RD_BURST_DATA[0], sizeof(mmGDS_RD_BURST_DATA)/sizeof(mmGDS_RD_BURST_DATA[0]), 0, 0 }, + { "mmGDS_WR_ADDR", REG_MMIO, 0x2405, 1, &mmGDS_WR_ADDR[0], sizeof(mmGDS_WR_ADDR)/sizeof(mmGDS_WR_ADDR[0]), 0, 0 }, + { "mmGDS_WR_DATA", REG_MMIO, 0x2406, 1, &mmGDS_WR_DATA[0], sizeof(mmGDS_WR_DATA)/sizeof(mmGDS_WR_DATA[0]), 0, 0 }, + { "mmGDS_WR_BURST_ADDR", REG_MMIO, 0x2407, 1, &mmGDS_WR_BURST_ADDR[0], sizeof(mmGDS_WR_BURST_ADDR)/sizeof(mmGDS_WR_BURST_ADDR[0]), 0, 0 }, + { "mmGDS_WR_BURST_DATA", REG_MMIO, 0x2408, 1, &mmGDS_WR_BURST_DATA[0], sizeof(mmGDS_WR_BURST_DATA)/sizeof(mmGDS_WR_BURST_DATA[0]), 0, 0 }, + { "mmGDS_WRITE_COMPLETE", REG_MMIO, 0x2409, 1, &mmGDS_WRITE_COMPLETE[0], sizeof(mmGDS_WRITE_COMPLETE)/sizeof(mmGDS_WRITE_COMPLETE[0]), 0, 0 }, + { "mmGDS_ATOM_CNTL", REG_MMIO, 0x240a, 1, &mmGDS_ATOM_CNTL[0], sizeof(mmGDS_ATOM_CNTL)/sizeof(mmGDS_ATOM_CNTL[0]), 0, 0 }, + { "mmGDS_ATOM_COMPLETE", REG_MMIO, 0x240b, 1, &mmGDS_ATOM_COMPLETE[0], sizeof(mmGDS_ATOM_COMPLETE)/sizeof(mmGDS_ATOM_COMPLETE[0]), 0, 0 }, + { "mmGDS_ATOM_BASE", REG_MMIO, 0x240c, 1, &mmGDS_ATOM_BASE[0], sizeof(mmGDS_ATOM_BASE)/sizeof(mmGDS_ATOM_BASE[0]), 0, 0 }, + { "mmGDS_ATOM_SIZE", REG_MMIO, 0x240d, 1, &mmGDS_ATOM_SIZE[0], sizeof(mmGDS_ATOM_SIZE)/sizeof(mmGDS_ATOM_SIZE[0]), 0, 0 }, + { "mmGDS_ATOM_OFFSET0", REG_MMIO, 0x240e, 1, &mmGDS_ATOM_OFFSET0[0], sizeof(mmGDS_ATOM_OFFSET0)/sizeof(mmGDS_ATOM_OFFSET0[0]), 0, 0 }, + { "mmGDS_ATOM_OFFSET1", REG_MMIO, 0x240f, 1, &mmGDS_ATOM_OFFSET1[0], sizeof(mmGDS_ATOM_OFFSET1)/sizeof(mmGDS_ATOM_OFFSET1[0]), 0, 0 }, + { "mmGDS_ATOM_DST", REG_MMIO, 0x2410, 1, &mmGDS_ATOM_DST[0], sizeof(mmGDS_ATOM_DST)/sizeof(mmGDS_ATOM_DST[0]), 0, 0 }, + { "mmGDS_ATOM_OP", REG_MMIO, 0x2411, 1, &mmGDS_ATOM_OP[0], sizeof(mmGDS_ATOM_OP)/sizeof(mmGDS_ATOM_OP[0]), 0, 0 }, + { "mmGDS_ATOM_SRC0", REG_MMIO, 0x2412, 1, &mmGDS_ATOM_SRC0[0], sizeof(mmGDS_ATOM_SRC0)/sizeof(mmGDS_ATOM_SRC0[0]), 0, 0 }, + { "mmGDS_ATOM_SRC0_U", REG_MMIO, 0x2413, 1, &mmGDS_ATOM_SRC0_U[0], sizeof(mmGDS_ATOM_SRC0_U)/sizeof(mmGDS_ATOM_SRC0_U[0]), 0, 0 }, + { "mmGDS_ATOM_SRC1", REG_MMIO, 0x2414, 1, &mmGDS_ATOM_SRC1[0], sizeof(mmGDS_ATOM_SRC1)/sizeof(mmGDS_ATOM_SRC1[0]), 0, 0 }, + { "mmGDS_ATOM_SRC1_U", REG_MMIO, 0x2415, 1, &mmGDS_ATOM_SRC1_U[0], sizeof(mmGDS_ATOM_SRC1_U)/sizeof(mmGDS_ATOM_SRC1_U[0]), 0, 0 }, + { "mmGDS_ATOM_READ0", REG_MMIO, 0x2416, 1, &mmGDS_ATOM_READ0[0], sizeof(mmGDS_ATOM_READ0)/sizeof(mmGDS_ATOM_READ0[0]), 0, 0 }, + { "mmGDS_ATOM_READ0_U", REG_MMIO, 0x2417, 1, &mmGDS_ATOM_READ0_U[0], sizeof(mmGDS_ATOM_READ0_U)/sizeof(mmGDS_ATOM_READ0_U[0]), 0, 0 }, + { "mmGDS_ATOM_READ1", REG_MMIO, 0x2418, 1, &mmGDS_ATOM_READ1[0], sizeof(mmGDS_ATOM_READ1)/sizeof(mmGDS_ATOM_READ1[0]), 0, 0 }, + { "mmGDS_ATOM_READ1_U", REG_MMIO, 0x2419, 1, &mmGDS_ATOM_READ1_U[0], sizeof(mmGDS_ATOM_READ1_U)/sizeof(mmGDS_ATOM_READ1_U[0]), 0, 0 }, + { "mmGDS_GWS_RESOURCE_CNTL", REG_MMIO, 0x241a, 1, &mmGDS_GWS_RESOURCE_CNTL[0], sizeof(mmGDS_GWS_RESOURCE_CNTL)/sizeof(mmGDS_GWS_RESOURCE_CNTL[0]), 0, 0 }, + { "mmGDS_GWS_RESOURCE", REG_MMIO, 0x241b, 1, &mmGDS_GWS_RESOURCE[0], sizeof(mmGDS_GWS_RESOURCE)/sizeof(mmGDS_GWS_RESOURCE[0]), 0, 0 }, + { "mmGDS_GWS_RESOURCE_CNT", REG_MMIO, 0x241c, 1, &mmGDS_GWS_RESOURCE_CNT[0], sizeof(mmGDS_GWS_RESOURCE_CNT)/sizeof(mmGDS_GWS_RESOURCE_CNT[0]), 0, 0 }, + { "mmGDS_OA_CNTL", REG_MMIO, 0x241d, 1, &mmGDS_OA_CNTL[0], sizeof(mmGDS_OA_CNTL)/sizeof(mmGDS_OA_CNTL[0]), 0, 0 }, + { "mmGDS_OA_COUNTER", REG_MMIO, 0x241e, 1, &mmGDS_OA_COUNTER[0], sizeof(mmGDS_OA_COUNTER)/sizeof(mmGDS_OA_COUNTER[0]), 0, 0 }, + { "mmGDS_OA_ADDRESS", REG_MMIO, 0x241f, 1, &mmGDS_OA_ADDRESS[0], sizeof(mmGDS_OA_ADDRESS)/sizeof(mmGDS_OA_ADDRESS[0]), 0, 0 }, + { "mmGDS_OA_INCDEC", REG_MMIO, 0x2420, 1, &mmGDS_OA_INCDEC[0], sizeof(mmGDS_OA_INCDEC)/sizeof(mmGDS_OA_INCDEC[0]), 0, 0 }, + { "mmGDS_OA_RING_SIZE", REG_MMIO, 0x2421, 1, &mmGDS_OA_RING_SIZE[0], sizeof(mmGDS_OA_RING_SIZE)/sizeof(mmGDS_OA_RING_SIZE[0]), 0, 0 }, + { "mmSPI_CONFIG_CNTL", REG_MMIO, 0x2440, 1, &mmSPI_CONFIG_CNTL[0], sizeof(mmSPI_CONFIG_CNTL)/sizeof(mmSPI_CONFIG_CNTL[0]), 0, 0 }, + { "mmSPI_CONFIG_CNTL_1", REG_MMIO, 0x2441, 1, &mmSPI_CONFIG_CNTL_1[0], sizeof(mmSPI_CONFIG_CNTL_1)/sizeof(mmSPI_CONFIG_CNTL_1[0]), 0, 0 }, + { "mmSPI_CONFIG_CNTL_2", REG_MMIO, 0x2442, 1, &mmSPI_CONFIG_CNTL_2[0], sizeof(mmSPI_CONFIG_CNTL_2)/sizeof(mmSPI_CONFIG_CNTL_2[0]), 0, 0 }, + { "mmCPG_PERFCOUNTER1_LO", REG_MMIO, 0x3000, 1, &mmCPG_PERFCOUNTER1_LO[0], sizeof(mmCPG_PERFCOUNTER1_LO)/sizeof(mmCPG_PERFCOUNTER1_LO[0]), 0, 0 }, + { "mmCPG_PERFCOUNTER1_HI", REG_MMIO, 0x3001, 1, &mmCPG_PERFCOUNTER1_HI[0], sizeof(mmCPG_PERFCOUNTER1_HI)/sizeof(mmCPG_PERFCOUNTER1_HI[0]), 0, 0 }, + { "mmCPG_PERFCOUNTER0_LO", REG_MMIO, 0x3002, 1, &mmCPG_PERFCOUNTER0_LO[0], sizeof(mmCPG_PERFCOUNTER0_LO)/sizeof(mmCPG_PERFCOUNTER0_LO[0]), 0, 0 }, + { "mmCPG_PERFCOUNTER0_HI", REG_MMIO, 0x3003, 1, &mmCPG_PERFCOUNTER0_HI[0], sizeof(mmCPG_PERFCOUNTER0_HI)/sizeof(mmCPG_PERFCOUNTER0_HI[0]), 0, 0 }, + { "mmCPC_PERFCOUNTER1_LO", REG_MMIO, 0x3004, 1, &mmCPC_PERFCOUNTER1_LO[0], sizeof(mmCPC_PERFCOUNTER1_LO)/sizeof(mmCPC_PERFCOUNTER1_LO[0]), 0, 0 }, + { "mmCPC_PERFCOUNTER1_HI", REG_MMIO, 0x3005, 1, &mmCPC_PERFCOUNTER1_HI[0], sizeof(mmCPC_PERFCOUNTER1_HI)/sizeof(mmCPC_PERFCOUNTER1_HI[0]), 0, 0 }, + { "mmCPC_PERFCOUNTER0_LO", REG_MMIO, 0x3006, 1, &mmCPC_PERFCOUNTER0_LO[0], sizeof(mmCPC_PERFCOUNTER0_LO)/sizeof(mmCPC_PERFCOUNTER0_LO[0]), 0, 0 }, + { "mmCPC_PERFCOUNTER0_HI", REG_MMIO, 0x3007, 1, &mmCPC_PERFCOUNTER0_HI[0], sizeof(mmCPC_PERFCOUNTER0_HI)/sizeof(mmCPC_PERFCOUNTER0_HI[0]), 0, 0 }, + { "mmCPF_PERFCOUNTER1_LO", REG_MMIO, 0x3008, 1, &mmCPF_PERFCOUNTER1_LO[0], sizeof(mmCPF_PERFCOUNTER1_LO)/sizeof(mmCPF_PERFCOUNTER1_LO[0]), 0, 0 }, + { "mmCPF_PERFCOUNTER1_HI", REG_MMIO, 0x3009, 1, &mmCPF_PERFCOUNTER1_HI[0], sizeof(mmCPF_PERFCOUNTER1_HI)/sizeof(mmCPF_PERFCOUNTER1_HI[0]), 0, 0 }, + { "mmCPF_PERFCOUNTER0_LO", REG_MMIO, 0x300a, 1, &mmCPF_PERFCOUNTER0_LO[0], sizeof(mmCPF_PERFCOUNTER0_LO)/sizeof(mmCPF_PERFCOUNTER0_LO[0]), 0, 0 }, + { "mmCPF_PERFCOUNTER0_HI", REG_MMIO, 0x300b, 1, &mmCPF_PERFCOUNTER0_HI[0], sizeof(mmCPF_PERFCOUNTER0_HI)/sizeof(mmCPF_PERFCOUNTER0_HI[0]), 0, 0 }, + { "mmCPF_LATENCY_STATS_DATA", REG_MMIO, 0x300c, 1, &mmCPF_LATENCY_STATS_DATA[0], sizeof(mmCPF_LATENCY_STATS_DATA)/sizeof(mmCPF_LATENCY_STATS_DATA[0]), 0, 0 }, + { "mmCPG_LATENCY_STATS_DATA", REG_MMIO, 0x300d, 1, &mmCPG_LATENCY_STATS_DATA[0], sizeof(mmCPG_LATENCY_STATS_DATA)/sizeof(mmCPG_LATENCY_STATS_DATA[0]), 0, 0 }, + { "mmCPC_LATENCY_STATS_DATA", REG_MMIO, 0x300e, 1, &mmCPC_LATENCY_STATS_DATA[0], sizeof(mmCPC_LATENCY_STATS_DATA)/sizeof(mmCPC_LATENCY_STATS_DATA[0]), 0, 0 }, + { "mmGRBM_PERFCOUNTER0_LO", REG_MMIO, 0x3040, 1, &mmGRBM_PERFCOUNTER0_LO[0], sizeof(mmGRBM_PERFCOUNTER0_LO)/sizeof(mmGRBM_PERFCOUNTER0_LO[0]), 0, 0 }, + { "mmGRBM_PERFCOUNTER0_HI", REG_MMIO, 0x3041, 1, &mmGRBM_PERFCOUNTER0_HI[0], sizeof(mmGRBM_PERFCOUNTER0_HI)/sizeof(mmGRBM_PERFCOUNTER0_HI[0]), 0, 0 }, + { "mmGRBM_PERFCOUNTER1_LO", REG_MMIO, 0x3043, 1, &mmGRBM_PERFCOUNTER1_LO[0], sizeof(mmGRBM_PERFCOUNTER1_LO)/sizeof(mmGRBM_PERFCOUNTER1_LO[0]), 0, 0 }, + { "mmGRBM_PERFCOUNTER1_HI", REG_MMIO, 0x3044, 1, &mmGRBM_PERFCOUNTER1_HI[0], sizeof(mmGRBM_PERFCOUNTER1_HI)/sizeof(mmGRBM_PERFCOUNTER1_HI[0]), 0, 0 }, + { "mmGRBM_SE0_PERFCOUNTER_LO", REG_MMIO, 0x3045, 1, &mmGRBM_SE0_PERFCOUNTER_LO[0], sizeof(mmGRBM_SE0_PERFCOUNTER_LO)/sizeof(mmGRBM_SE0_PERFCOUNTER_LO[0]), 0, 0 }, + { "mmGRBM_SE0_PERFCOUNTER_HI", REG_MMIO, 0x3046, 1, &mmGRBM_SE0_PERFCOUNTER_HI[0], sizeof(mmGRBM_SE0_PERFCOUNTER_HI)/sizeof(mmGRBM_SE0_PERFCOUNTER_HI[0]), 0, 0 }, + { "mmGRBM_SE1_PERFCOUNTER_LO", REG_MMIO, 0x3047, 1, &mmGRBM_SE1_PERFCOUNTER_LO[0], sizeof(mmGRBM_SE1_PERFCOUNTER_LO)/sizeof(mmGRBM_SE1_PERFCOUNTER_LO[0]), 0, 0 }, + { "mmGRBM_SE1_PERFCOUNTER_HI", REG_MMIO, 0x3048, 1, &mmGRBM_SE1_PERFCOUNTER_HI[0], sizeof(mmGRBM_SE1_PERFCOUNTER_HI)/sizeof(mmGRBM_SE1_PERFCOUNTER_HI[0]), 0, 0 }, + { "mmGRBM_SE2_PERFCOUNTER_LO", REG_MMIO, 0x3049, 1, &mmGRBM_SE2_PERFCOUNTER_LO[0], sizeof(mmGRBM_SE2_PERFCOUNTER_LO)/sizeof(mmGRBM_SE2_PERFCOUNTER_LO[0]), 0, 0 }, + { "mmGRBM_SE2_PERFCOUNTER_HI", REG_MMIO, 0x304a, 1, &mmGRBM_SE2_PERFCOUNTER_HI[0], sizeof(mmGRBM_SE2_PERFCOUNTER_HI)/sizeof(mmGRBM_SE2_PERFCOUNTER_HI[0]), 0, 0 }, + { "mmGRBM_SE3_PERFCOUNTER_LO", REG_MMIO, 0x304b, 1, &mmGRBM_SE3_PERFCOUNTER_LO[0], sizeof(mmGRBM_SE3_PERFCOUNTER_LO)/sizeof(mmGRBM_SE3_PERFCOUNTER_LO[0]), 0, 0 }, + { "mmGRBM_SE3_PERFCOUNTER_HI", REG_MMIO, 0x304c, 1, &mmGRBM_SE3_PERFCOUNTER_HI[0], sizeof(mmGRBM_SE3_PERFCOUNTER_HI)/sizeof(mmGRBM_SE3_PERFCOUNTER_HI[0]), 0, 0 }, + { "mmWD_PERFCOUNTER0_LO", REG_MMIO, 0x3080, 1, &mmWD_PERFCOUNTER0_LO[0], sizeof(mmWD_PERFCOUNTER0_LO)/sizeof(mmWD_PERFCOUNTER0_LO[0]), 0, 0 }, + { "mmWD_PERFCOUNTER0_HI", REG_MMIO, 0x3081, 1, &mmWD_PERFCOUNTER0_HI[0], sizeof(mmWD_PERFCOUNTER0_HI)/sizeof(mmWD_PERFCOUNTER0_HI[0]), 0, 0 }, + { "mmWD_PERFCOUNTER1_LO", REG_MMIO, 0x3082, 1, &mmWD_PERFCOUNTER1_LO[0], sizeof(mmWD_PERFCOUNTER1_LO)/sizeof(mmWD_PERFCOUNTER1_LO[0]), 0, 0 }, + { "mmWD_PERFCOUNTER1_HI", REG_MMIO, 0x3083, 1, &mmWD_PERFCOUNTER1_HI[0], sizeof(mmWD_PERFCOUNTER1_HI)/sizeof(mmWD_PERFCOUNTER1_HI[0]), 0, 0 }, + { "mmWD_PERFCOUNTER2_LO", REG_MMIO, 0x3084, 1, &mmWD_PERFCOUNTER2_LO[0], sizeof(mmWD_PERFCOUNTER2_LO)/sizeof(mmWD_PERFCOUNTER2_LO[0]), 0, 0 }, + { "mmWD_PERFCOUNTER2_HI", REG_MMIO, 0x3085, 1, &mmWD_PERFCOUNTER2_HI[0], sizeof(mmWD_PERFCOUNTER2_HI)/sizeof(mmWD_PERFCOUNTER2_HI[0]), 0, 0 }, + { "mmWD_PERFCOUNTER3_LO", REG_MMIO, 0x3086, 1, &mmWD_PERFCOUNTER3_LO[0], sizeof(mmWD_PERFCOUNTER3_LO)/sizeof(mmWD_PERFCOUNTER3_LO[0]), 0, 0 }, + { "mmWD_PERFCOUNTER3_HI", REG_MMIO, 0x3087, 1, &mmWD_PERFCOUNTER3_HI[0], sizeof(mmWD_PERFCOUNTER3_HI)/sizeof(mmWD_PERFCOUNTER3_HI[0]), 0, 0 }, + { "mmIA_PERFCOUNTER0_LO", REG_MMIO, 0x3088, 1, &mmIA_PERFCOUNTER0_LO[0], sizeof(mmIA_PERFCOUNTER0_LO)/sizeof(mmIA_PERFCOUNTER0_LO[0]), 0, 0 }, + { "mmIA_PERFCOUNTER0_HI", REG_MMIO, 0x3089, 1, &mmIA_PERFCOUNTER0_HI[0], sizeof(mmIA_PERFCOUNTER0_HI)/sizeof(mmIA_PERFCOUNTER0_HI[0]), 0, 0 }, + { "mmIA_PERFCOUNTER1_LO", REG_MMIO, 0x308a, 1, &mmIA_PERFCOUNTER1_LO[0], sizeof(mmIA_PERFCOUNTER1_LO)/sizeof(mmIA_PERFCOUNTER1_LO[0]), 0, 0 }, + { "mmIA_PERFCOUNTER1_HI", REG_MMIO, 0x308b, 1, &mmIA_PERFCOUNTER1_HI[0], sizeof(mmIA_PERFCOUNTER1_HI)/sizeof(mmIA_PERFCOUNTER1_HI[0]), 0, 0 }, + { "mmIA_PERFCOUNTER2_LO", REG_MMIO, 0x308c, 1, &mmIA_PERFCOUNTER2_LO[0], sizeof(mmIA_PERFCOUNTER2_LO)/sizeof(mmIA_PERFCOUNTER2_LO[0]), 0, 0 }, + { "mmIA_PERFCOUNTER2_HI", REG_MMIO, 0x308d, 1, &mmIA_PERFCOUNTER2_HI[0], sizeof(mmIA_PERFCOUNTER2_HI)/sizeof(mmIA_PERFCOUNTER2_HI[0]), 0, 0 }, + { "mmIA_PERFCOUNTER3_LO", REG_MMIO, 0x308e, 1, &mmIA_PERFCOUNTER3_LO[0], sizeof(mmIA_PERFCOUNTER3_LO)/sizeof(mmIA_PERFCOUNTER3_LO[0]), 0, 0 }, + { "mmIA_PERFCOUNTER3_HI", REG_MMIO, 0x308f, 1, &mmIA_PERFCOUNTER3_HI[0], sizeof(mmIA_PERFCOUNTER3_HI)/sizeof(mmIA_PERFCOUNTER3_HI[0]), 0, 0 }, + { "mmVGT_PERFCOUNTER0_LO", REG_MMIO, 0x3090, 1, &mmVGT_PERFCOUNTER0_LO[0], sizeof(mmVGT_PERFCOUNTER0_LO)/sizeof(mmVGT_PERFCOUNTER0_LO[0]), 0, 0 }, + { "mmVGT_PERFCOUNTER0_HI", REG_MMIO, 0x3091, 1, &mmVGT_PERFCOUNTER0_HI[0], sizeof(mmVGT_PERFCOUNTER0_HI)/sizeof(mmVGT_PERFCOUNTER0_HI[0]), 0, 0 }, + { "mmVGT_PERFCOUNTER1_LO", REG_MMIO, 0x3092, 1, &mmVGT_PERFCOUNTER1_LO[0], sizeof(mmVGT_PERFCOUNTER1_LO)/sizeof(mmVGT_PERFCOUNTER1_LO[0]), 0, 0 }, + { "mmVGT_PERFCOUNTER1_HI", REG_MMIO, 0x3093, 1, &mmVGT_PERFCOUNTER1_HI[0], sizeof(mmVGT_PERFCOUNTER1_HI)/sizeof(mmVGT_PERFCOUNTER1_HI[0]), 0, 0 }, + { "mmVGT_PERFCOUNTER2_LO", REG_MMIO, 0x3094, 1, &mmVGT_PERFCOUNTER2_LO[0], sizeof(mmVGT_PERFCOUNTER2_LO)/sizeof(mmVGT_PERFCOUNTER2_LO[0]), 0, 0 }, + { "mmVGT_PERFCOUNTER2_HI", REG_MMIO, 0x3095, 1, &mmVGT_PERFCOUNTER2_HI[0], sizeof(mmVGT_PERFCOUNTER2_HI)/sizeof(mmVGT_PERFCOUNTER2_HI[0]), 0, 0 }, + { "mmVGT_PERFCOUNTER3_LO", REG_MMIO, 0x3096, 1, &mmVGT_PERFCOUNTER3_LO[0], sizeof(mmVGT_PERFCOUNTER3_LO)/sizeof(mmVGT_PERFCOUNTER3_LO[0]), 0, 0 }, + { "mmVGT_PERFCOUNTER3_HI", REG_MMIO, 0x3097, 1, &mmVGT_PERFCOUNTER3_HI[0], sizeof(mmVGT_PERFCOUNTER3_HI)/sizeof(mmVGT_PERFCOUNTER3_HI[0]), 0, 0 }, + { "mmPA_SU_PERFCOUNTER0_LO", REG_MMIO, 0x3100, 1, &mmPA_SU_PERFCOUNTER0_LO[0], sizeof(mmPA_SU_PERFCOUNTER0_LO)/sizeof(mmPA_SU_PERFCOUNTER0_LO[0]), 0, 0 }, + { "mmPA_SU_PERFCOUNTER0_HI", REG_MMIO, 0x3101, 1, &mmPA_SU_PERFCOUNTER0_HI[0], sizeof(mmPA_SU_PERFCOUNTER0_HI)/sizeof(mmPA_SU_PERFCOUNTER0_HI[0]), 0, 0 }, + { "mmPA_SU_PERFCOUNTER1_LO", REG_MMIO, 0x3102, 1, &mmPA_SU_PERFCOUNTER1_LO[0], sizeof(mmPA_SU_PERFCOUNTER1_LO)/sizeof(mmPA_SU_PERFCOUNTER1_LO[0]), 0, 0 }, + { "mmPA_SU_PERFCOUNTER1_HI", REG_MMIO, 0x3103, 1, &mmPA_SU_PERFCOUNTER1_HI[0], sizeof(mmPA_SU_PERFCOUNTER1_HI)/sizeof(mmPA_SU_PERFCOUNTER1_HI[0]), 0, 0 }, + { "mmPA_SU_PERFCOUNTER2_LO", REG_MMIO, 0x3104, 1, &mmPA_SU_PERFCOUNTER2_LO[0], sizeof(mmPA_SU_PERFCOUNTER2_LO)/sizeof(mmPA_SU_PERFCOUNTER2_LO[0]), 0, 0 }, + { "mmPA_SU_PERFCOUNTER2_HI", REG_MMIO, 0x3105, 1, &mmPA_SU_PERFCOUNTER2_HI[0], sizeof(mmPA_SU_PERFCOUNTER2_HI)/sizeof(mmPA_SU_PERFCOUNTER2_HI[0]), 0, 0 }, + { "mmPA_SU_PERFCOUNTER3_LO", REG_MMIO, 0x3106, 1, &mmPA_SU_PERFCOUNTER3_LO[0], sizeof(mmPA_SU_PERFCOUNTER3_LO)/sizeof(mmPA_SU_PERFCOUNTER3_LO[0]), 0, 0 }, + { "mmPA_SU_PERFCOUNTER3_HI", REG_MMIO, 0x3107, 1, &mmPA_SU_PERFCOUNTER3_HI[0], sizeof(mmPA_SU_PERFCOUNTER3_HI)/sizeof(mmPA_SU_PERFCOUNTER3_HI[0]), 0, 0 }, + { "mmPA_SC_PERFCOUNTER0_LO", REG_MMIO, 0x3140, 1, &mmPA_SC_PERFCOUNTER0_LO[0], sizeof(mmPA_SC_PERFCOUNTER0_LO)/sizeof(mmPA_SC_PERFCOUNTER0_LO[0]), 0, 0 }, + { "mmPA_SC_PERFCOUNTER0_HI", REG_MMIO, 0x3141, 1, &mmPA_SC_PERFCOUNTER0_HI[0], sizeof(mmPA_SC_PERFCOUNTER0_HI)/sizeof(mmPA_SC_PERFCOUNTER0_HI[0]), 0, 0 }, + { "mmPA_SC_PERFCOUNTER1_LO", REG_MMIO, 0x3142, 1, &mmPA_SC_PERFCOUNTER1_LO[0], sizeof(mmPA_SC_PERFCOUNTER1_LO)/sizeof(mmPA_SC_PERFCOUNTER1_LO[0]), 0, 0 }, + { "mmPA_SC_PERFCOUNTER1_HI", REG_MMIO, 0x3143, 1, &mmPA_SC_PERFCOUNTER1_HI[0], sizeof(mmPA_SC_PERFCOUNTER1_HI)/sizeof(mmPA_SC_PERFCOUNTER1_HI[0]), 0, 0 }, + { "mmPA_SC_PERFCOUNTER2_LO", REG_MMIO, 0x3144, 1, &mmPA_SC_PERFCOUNTER2_LO[0], sizeof(mmPA_SC_PERFCOUNTER2_LO)/sizeof(mmPA_SC_PERFCOUNTER2_LO[0]), 0, 0 }, + { "mmPA_SC_PERFCOUNTER2_HI", REG_MMIO, 0x3145, 1, &mmPA_SC_PERFCOUNTER2_HI[0], sizeof(mmPA_SC_PERFCOUNTER2_HI)/sizeof(mmPA_SC_PERFCOUNTER2_HI[0]), 0, 0 }, + { "mmPA_SC_PERFCOUNTER3_LO", REG_MMIO, 0x3146, 1, &mmPA_SC_PERFCOUNTER3_LO[0], sizeof(mmPA_SC_PERFCOUNTER3_LO)/sizeof(mmPA_SC_PERFCOUNTER3_LO[0]), 0, 0 }, + { "mmPA_SC_PERFCOUNTER3_HI", REG_MMIO, 0x3147, 1, &mmPA_SC_PERFCOUNTER3_HI[0], sizeof(mmPA_SC_PERFCOUNTER3_HI)/sizeof(mmPA_SC_PERFCOUNTER3_HI[0]), 0, 0 }, + { "mmPA_SC_PERFCOUNTER4_LO", REG_MMIO, 0x3148, 1, &mmPA_SC_PERFCOUNTER4_LO[0], sizeof(mmPA_SC_PERFCOUNTER4_LO)/sizeof(mmPA_SC_PERFCOUNTER4_LO[0]), 0, 0 }, + { "mmPA_SC_PERFCOUNTER4_HI", REG_MMIO, 0x3149, 1, &mmPA_SC_PERFCOUNTER4_HI[0], sizeof(mmPA_SC_PERFCOUNTER4_HI)/sizeof(mmPA_SC_PERFCOUNTER4_HI[0]), 0, 0 }, + { "mmPA_SC_PERFCOUNTER5_LO", REG_MMIO, 0x314a, 1, &mmPA_SC_PERFCOUNTER5_LO[0], sizeof(mmPA_SC_PERFCOUNTER5_LO)/sizeof(mmPA_SC_PERFCOUNTER5_LO[0]), 0, 0 }, + { "mmPA_SC_PERFCOUNTER5_HI", REG_MMIO, 0x314b, 1, &mmPA_SC_PERFCOUNTER5_HI[0], sizeof(mmPA_SC_PERFCOUNTER5_HI)/sizeof(mmPA_SC_PERFCOUNTER5_HI[0]), 0, 0 }, + { "mmPA_SC_PERFCOUNTER6_LO", REG_MMIO, 0x314c, 1, &mmPA_SC_PERFCOUNTER6_LO[0], sizeof(mmPA_SC_PERFCOUNTER6_LO)/sizeof(mmPA_SC_PERFCOUNTER6_LO[0]), 0, 0 }, + { "mmPA_SC_PERFCOUNTER6_HI", REG_MMIO, 0x314d, 1, &mmPA_SC_PERFCOUNTER6_HI[0], sizeof(mmPA_SC_PERFCOUNTER6_HI)/sizeof(mmPA_SC_PERFCOUNTER6_HI[0]), 0, 0 }, + { "mmPA_SC_PERFCOUNTER7_LO", REG_MMIO, 0x314e, 1, &mmPA_SC_PERFCOUNTER7_LO[0], sizeof(mmPA_SC_PERFCOUNTER7_LO)/sizeof(mmPA_SC_PERFCOUNTER7_LO[0]), 0, 0 }, + { "mmPA_SC_PERFCOUNTER7_HI", REG_MMIO, 0x314f, 1, &mmPA_SC_PERFCOUNTER7_HI[0], sizeof(mmPA_SC_PERFCOUNTER7_HI)/sizeof(mmPA_SC_PERFCOUNTER7_HI[0]), 0, 0 }, + { "mmSPI_PERFCOUNTER0_HI", REG_MMIO, 0x3180, 1, &mmSPI_PERFCOUNTER0_HI[0], sizeof(mmSPI_PERFCOUNTER0_HI)/sizeof(mmSPI_PERFCOUNTER0_HI[0]), 0, 0 }, + { "mmSPI_PERFCOUNTER0_LO", REG_MMIO, 0x3181, 1, &mmSPI_PERFCOUNTER0_LO[0], sizeof(mmSPI_PERFCOUNTER0_LO)/sizeof(mmSPI_PERFCOUNTER0_LO[0]), 0, 0 }, + { "mmSPI_PERFCOUNTER1_HI", REG_MMIO, 0x3182, 1, &mmSPI_PERFCOUNTER1_HI[0], sizeof(mmSPI_PERFCOUNTER1_HI)/sizeof(mmSPI_PERFCOUNTER1_HI[0]), 0, 0 }, + { "mmSPI_PERFCOUNTER1_LO", REG_MMIO, 0x3183, 1, &mmSPI_PERFCOUNTER1_LO[0], sizeof(mmSPI_PERFCOUNTER1_LO)/sizeof(mmSPI_PERFCOUNTER1_LO[0]), 0, 0 }, + { "mmSPI_PERFCOUNTER2_HI", REG_MMIO, 0x3184, 1, &mmSPI_PERFCOUNTER2_HI[0], sizeof(mmSPI_PERFCOUNTER2_HI)/sizeof(mmSPI_PERFCOUNTER2_HI[0]), 0, 0 }, + { "mmSPI_PERFCOUNTER2_LO", REG_MMIO, 0x3185, 1, &mmSPI_PERFCOUNTER2_LO[0], sizeof(mmSPI_PERFCOUNTER2_LO)/sizeof(mmSPI_PERFCOUNTER2_LO[0]), 0, 0 }, + { "mmSPI_PERFCOUNTER3_HI", REG_MMIO, 0x3186, 1, &mmSPI_PERFCOUNTER3_HI[0], sizeof(mmSPI_PERFCOUNTER3_HI)/sizeof(mmSPI_PERFCOUNTER3_HI[0]), 0, 0 }, + { "mmSPI_PERFCOUNTER3_LO", REG_MMIO, 0x3187, 1, &mmSPI_PERFCOUNTER3_LO[0], sizeof(mmSPI_PERFCOUNTER3_LO)/sizeof(mmSPI_PERFCOUNTER3_LO[0]), 0, 0 }, + { "mmSPI_PERFCOUNTER4_HI", REG_MMIO, 0x3188, 1, &mmSPI_PERFCOUNTER4_HI[0], sizeof(mmSPI_PERFCOUNTER4_HI)/sizeof(mmSPI_PERFCOUNTER4_HI[0]), 0, 0 }, + { "mmSPI_PERFCOUNTER4_LO", REG_MMIO, 0x3189, 1, &mmSPI_PERFCOUNTER4_LO[0], sizeof(mmSPI_PERFCOUNTER4_LO)/sizeof(mmSPI_PERFCOUNTER4_LO[0]), 0, 0 }, + { "mmSPI_PERFCOUNTER5_HI", REG_MMIO, 0x318a, 1, &mmSPI_PERFCOUNTER5_HI[0], sizeof(mmSPI_PERFCOUNTER5_HI)/sizeof(mmSPI_PERFCOUNTER5_HI[0]), 0, 0 }, + { "mmSPI_PERFCOUNTER5_LO", REG_MMIO, 0x318b, 1, &mmSPI_PERFCOUNTER5_LO[0], sizeof(mmSPI_PERFCOUNTER5_LO)/sizeof(mmSPI_PERFCOUNTER5_LO[0]), 0, 0 }, + { "mmSQ_PERFCOUNTER0_LO", REG_MMIO, 0x31c0, 1, &mmSQ_PERFCOUNTER0_LO[0], sizeof(mmSQ_PERFCOUNTER0_LO)/sizeof(mmSQ_PERFCOUNTER0_LO[0]), 0, 0 }, + { "mmSQ_PERFCOUNTER0_HI", REG_MMIO, 0x31c1, 1, &mmSQ_PERFCOUNTER0_HI[0], sizeof(mmSQ_PERFCOUNTER0_HI)/sizeof(mmSQ_PERFCOUNTER0_HI[0]), 0, 0 }, + { "mmSQ_PERFCOUNTER1_LO", REG_MMIO, 0x31c2, 1, &mmSQ_PERFCOUNTER1_LO[0], sizeof(mmSQ_PERFCOUNTER1_LO)/sizeof(mmSQ_PERFCOUNTER1_LO[0]), 0, 0 }, + { "mmSQ_PERFCOUNTER1_HI", REG_MMIO, 0x31c3, 1, &mmSQ_PERFCOUNTER1_HI[0], sizeof(mmSQ_PERFCOUNTER1_HI)/sizeof(mmSQ_PERFCOUNTER1_HI[0]), 0, 0 }, + { "mmSQ_PERFCOUNTER2_LO", REG_MMIO, 0x31c4, 1, &mmSQ_PERFCOUNTER2_LO[0], sizeof(mmSQ_PERFCOUNTER2_LO)/sizeof(mmSQ_PERFCOUNTER2_LO[0]), 0, 0 }, + { "mmSQ_PERFCOUNTER2_HI", REG_MMIO, 0x31c5, 1, &mmSQ_PERFCOUNTER2_HI[0], sizeof(mmSQ_PERFCOUNTER2_HI)/sizeof(mmSQ_PERFCOUNTER2_HI[0]), 0, 0 }, + { "mmSQ_PERFCOUNTER3_LO", REG_MMIO, 0x31c6, 1, &mmSQ_PERFCOUNTER3_LO[0], sizeof(mmSQ_PERFCOUNTER3_LO)/sizeof(mmSQ_PERFCOUNTER3_LO[0]), 0, 0 }, + { "mmSQ_PERFCOUNTER3_HI", REG_MMIO, 0x31c7, 1, &mmSQ_PERFCOUNTER3_HI[0], sizeof(mmSQ_PERFCOUNTER3_HI)/sizeof(mmSQ_PERFCOUNTER3_HI[0]), 0, 0 }, + { "mmSQ_PERFCOUNTER4_LO", REG_MMIO, 0x31c8, 1, &mmSQ_PERFCOUNTER4_LO[0], sizeof(mmSQ_PERFCOUNTER4_LO)/sizeof(mmSQ_PERFCOUNTER4_LO[0]), 0, 0 }, + { "mmSQ_PERFCOUNTER4_HI", REG_MMIO, 0x31c9, 1, &mmSQ_PERFCOUNTER4_HI[0], sizeof(mmSQ_PERFCOUNTER4_HI)/sizeof(mmSQ_PERFCOUNTER4_HI[0]), 0, 0 }, + { "mmSQ_PERFCOUNTER5_LO", REG_MMIO, 0x31ca, 1, &mmSQ_PERFCOUNTER5_LO[0], sizeof(mmSQ_PERFCOUNTER5_LO)/sizeof(mmSQ_PERFCOUNTER5_LO[0]), 0, 0 }, + { "mmSQ_PERFCOUNTER5_HI", REG_MMIO, 0x31cb, 1, &mmSQ_PERFCOUNTER5_HI[0], sizeof(mmSQ_PERFCOUNTER5_HI)/sizeof(mmSQ_PERFCOUNTER5_HI[0]), 0, 0 }, + { "mmSQ_PERFCOUNTER6_LO", REG_MMIO, 0x31cc, 1, &mmSQ_PERFCOUNTER6_LO[0], sizeof(mmSQ_PERFCOUNTER6_LO)/sizeof(mmSQ_PERFCOUNTER6_LO[0]), 0, 0 }, + { "mmSQ_PERFCOUNTER6_HI", REG_MMIO, 0x31cd, 1, &mmSQ_PERFCOUNTER6_HI[0], sizeof(mmSQ_PERFCOUNTER6_HI)/sizeof(mmSQ_PERFCOUNTER6_HI[0]), 0, 0 }, + { "mmSQ_PERFCOUNTER7_LO", REG_MMIO, 0x31ce, 1, &mmSQ_PERFCOUNTER7_LO[0], sizeof(mmSQ_PERFCOUNTER7_LO)/sizeof(mmSQ_PERFCOUNTER7_LO[0]), 0, 0 }, + { "mmSQ_PERFCOUNTER7_HI", REG_MMIO, 0x31cf, 1, &mmSQ_PERFCOUNTER7_HI[0], sizeof(mmSQ_PERFCOUNTER7_HI)/sizeof(mmSQ_PERFCOUNTER7_HI[0]), 0, 0 }, + { "mmSQ_PERFCOUNTER8_LO", REG_MMIO, 0x31d0, 1, &mmSQ_PERFCOUNTER8_LO[0], sizeof(mmSQ_PERFCOUNTER8_LO)/sizeof(mmSQ_PERFCOUNTER8_LO[0]), 0, 0 }, + { "mmSQ_PERFCOUNTER8_HI", REG_MMIO, 0x31d1, 1, &mmSQ_PERFCOUNTER8_HI[0], sizeof(mmSQ_PERFCOUNTER8_HI)/sizeof(mmSQ_PERFCOUNTER8_HI[0]), 0, 0 }, + { "mmSQ_PERFCOUNTER9_LO", REG_MMIO, 0x31d2, 1, &mmSQ_PERFCOUNTER9_LO[0], sizeof(mmSQ_PERFCOUNTER9_LO)/sizeof(mmSQ_PERFCOUNTER9_LO[0]), 0, 0 }, + { "mmSQ_PERFCOUNTER9_HI", REG_MMIO, 0x31d3, 1, &mmSQ_PERFCOUNTER9_HI[0], sizeof(mmSQ_PERFCOUNTER9_HI)/sizeof(mmSQ_PERFCOUNTER9_HI[0]), 0, 0 }, + { "mmSQ_PERFCOUNTER10_LO", REG_MMIO, 0x31d4, 1, &mmSQ_PERFCOUNTER10_LO[0], sizeof(mmSQ_PERFCOUNTER10_LO)/sizeof(mmSQ_PERFCOUNTER10_LO[0]), 0, 0 }, + { "mmSQ_PERFCOUNTER10_HI", REG_MMIO, 0x31d5, 1, &mmSQ_PERFCOUNTER10_HI[0], sizeof(mmSQ_PERFCOUNTER10_HI)/sizeof(mmSQ_PERFCOUNTER10_HI[0]), 0, 0 }, + { "mmSQ_PERFCOUNTER11_LO", REG_MMIO, 0x31d6, 1, &mmSQ_PERFCOUNTER11_LO[0], sizeof(mmSQ_PERFCOUNTER11_LO)/sizeof(mmSQ_PERFCOUNTER11_LO[0]), 0, 0 }, + { "mmSQ_PERFCOUNTER11_HI", REG_MMIO, 0x31d7, 1, &mmSQ_PERFCOUNTER11_HI[0], sizeof(mmSQ_PERFCOUNTER11_HI)/sizeof(mmSQ_PERFCOUNTER11_HI[0]), 0, 0 }, + { "mmSQ_PERFCOUNTER12_LO", REG_MMIO, 0x31d8, 1, &mmSQ_PERFCOUNTER12_LO[0], sizeof(mmSQ_PERFCOUNTER12_LO)/sizeof(mmSQ_PERFCOUNTER12_LO[0]), 0, 0 }, + { "mmSQ_PERFCOUNTER12_HI", REG_MMIO, 0x31d9, 1, &mmSQ_PERFCOUNTER12_HI[0], sizeof(mmSQ_PERFCOUNTER12_HI)/sizeof(mmSQ_PERFCOUNTER12_HI[0]), 0, 0 }, + { "mmSQ_PERFCOUNTER13_LO", REG_MMIO, 0x31da, 1, &mmSQ_PERFCOUNTER13_LO[0], sizeof(mmSQ_PERFCOUNTER13_LO)/sizeof(mmSQ_PERFCOUNTER13_LO[0]), 0, 0 }, + { "mmSQ_PERFCOUNTER13_HI", REG_MMIO, 0x31db, 1, &mmSQ_PERFCOUNTER13_HI[0], sizeof(mmSQ_PERFCOUNTER13_HI)/sizeof(mmSQ_PERFCOUNTER13_HI[0]), 0, 0 }, + { "mmSQ_PERFCOUNTER14_LO", REG_MMIO, 0x31dc, 1, &mmSQ_PERFCOUNTER14_LO[0], sizeof(mmSQ_PERFCOUNTER14_LO)/sizeof(mmSQ_PERFCOUNTER14_LO[0]), 0, 0 }, + { "mmSQ_PERFCOUNTER14_HI", REG_MMIO, 0x31dd, 1, &mmSQ_PERFCOUNTER14_HI[0], sizeof(mmSQ_PERFCOUNTER14_HI)/sizeof(mmSQ_PERFCOUNTER14_HI[0]), 0, 0 }, + { "mmSQ_PERFCOUNTER15_LO", REG_MMIO, 0x31de, 1, &mmSQ_PERFCOUNTER15_LO[0], sizeof(mmSQ_PERFCOUNTER15_LO)/sizeof(mmSQ_PERFCOUNTER15_LO[0]), 0, 0 }, + { "mmSQ_PERFCOUNTER15_HI", REG_MMIO, 0x31df, 1, &mmSQ_PERFCOUNTER15_HI[0], sizeof(mmSQ_PERFCOUNTER15_HI)/sizeof(mmSQ_PERFCOUNTER15_HI[0]), 0, 0 }, + { "mmSX_PERFCOUNTER0_LO", REG_MMIO, 0x3240, 1, &mmSX_PERFCOUNTER0_LO[0], sizeof(mmSX_PERFCOUNTER0_LO)/sizeof(mmSX_PERFCOUNTER0_LO[0]), 0, 0 }, + { "mmSX_PERFCOUNTER0_HI", REG_MMIO, 0x3241, 1, &mmSX_PERFCOUNTER0_HI[0], sizeof(mmSX_PERFCOUNTER0_HI)/sizeof(mmSX_PERFCOUNTER0_HI[0]), 0, 0 }, + { "mmSX_PERFCOUNTER1_LO", REG_MMIO, 0x3242, 1, &mmSX_PERFCOUNTER1_LO[0], sizeof(mmSX_PERFCOUNTER1_LO)/sizeof(mmSX_PERFCOUNTER1_LO[0]), 0, 0 }, + { "mmSX_PERFCOUNTER1_HI", REG_MMIO, 0x3243, 1, &mmSX_PERFCOUNTER1_HI[0], sizeof(mmSX_PERFCOUNTER1_HI)/sizeof(mmSX_PERFCOUNTER1_HI[0]), 0, 0 }, + { "mmSX_PERFCOUNTER2_LO", REG_MMIO, 0x3244, 1, &mmSX_PERFCOUNTER2_LO[0], sizeof(mmSX_PERFCOUNTER2_LO)/sizeof(mmSX_PERFCOUNTER2_LO[0]), 0, 0 }, + { "mmSX_PERFCOUNTER2_HI", REG_MMIO, 0x3245, 1, &mmSX_PERFCOUNTER2_HI[0], sizeof(mmSX_PERFCOUNTER2_HI)/sizeof(mmSX_PERFCOUNTER2_HI[0]), 0, 0 }, + { "mmSX_PERFCOUNTER3_LO", REG_MMIO, 0x3246, 1, &mmSX_PERFCOUNTER3_LO[0], sizeof(mmSX_PERFCOUNTER3_LO)/sizeof(mmSX_PERFCOUNTER3_LO[0]), 0, 0 }, + { "mmSX_PERFCOUNTER3_HI", REG_MMIO, 0x3247, 1, &mmSX_PERFCOUNTER3_HI[0], sizeof(mmSX_PERFCOUNTER3_HI)/sizeof(mmSX_PERFCOUNTER3_HI[0]), 0, 0 }, + { "mmGDS_PERFCOUNTER0_LO", REG_MMIO, 0x3280, 1, &mmGDS_PERFCOUNTER0_LO[0], sizeof(mmGDS_PERFCOUNTER0_LO)/sizeof(mmGDS_PERFCOUNTER0_LO[0]), 0, 0 }, + { "mmGDS_PERFCOUNTER0_HI", REG_MMIO, 0x3281, 1, &mmGDS_PERFCOUNTER0_HI[0], sizeof(mmGDS_PERFCOUNTER0_HI)/sizeof(mmGDS_PERFCOUNTER0_HI[0]), 0, 0 }, + { "mmGDS_PERFCOUNTER1_LO", REG_MMIO, 0x3282, 1, &mmGDS_PERFCOUNTER1_LO[0], sizeof(mmGDS_PERFCOUNTER1_LO)/sizeof(mmGDS_PERFCOUNTER1_LO[0]), 0, 0 }, + { "mmGDS_PERFCOUNTER1_HI", REG_MMIO, 0x3283, 1, &mmGDS_PERFCOUNTER1_HI[0], sizeof(mmGDS_PERFCOUNTER1_HI)/sizeof(mmGDS_PERFCOUNTER1_HI[0]), 0, 0 }, + { "mmGDS_PERFCOUNTER2_LO", REG_MMIO, 0x3284, 1, &mmGDS_PERFCOUNTER2_LO[0], sizeof(mmGDS_PERFCOUNTER2_LO)/sizeof(mmGDS_PERFCOUNTER2_LO[0]), 0, 0 }, + { "mmGDS_PERFCOUNTER2_HI", REG_MMIO, 0x3285, 1, &mmGDS_PERFCOUNTER2_HI[0], sizeof(mmGDS_PERFCOUNTER2_HI)/sizeof(mmGDS_PERFCOUNTER2_HI[0]), 0, 0 }, + { "mmGDS_PERFCOUNTER3_LO", REG_MMIO, 0x3286, 1, &mmGDS_PERFCOUNTER3_LO[0], sizeof(mmGDS_PERFCOUNTER3_LO)/sizeof(mmGDS_PERFCOUNTER3_LO[0]), 0, 0 }, + { "mmGDS_PERFCOUNTER3_HI", REG_MMIO, 0x3287, 1, &mmGDS_PERFCOUNTER3_HI[0], sizeof(mmGDS_PERFCOUNTER3_HI)/sizeof(mmGDS_PERFCOUNTER3_HI[0]), 0, 0 }, + { "mmTA_PERFCOUNTER0_LO", REG_MMIO, 0x32c0, 1, &mmTA_PERFCOUNTER0_LO[0], sizeof(mmTA_PERFCOUNTER0_LO)/sizeof(mmTA_PERFCOUNTER0_LO[0]), 0, 0 }, + { "mmTA_PERFCOUNTER0_HI", REG_MMIO, 0x32c1, 1, &mmTA_PERFCOUNTER0_HI[0], sizeof(mmTA_PERFCOUNTER0_HI)/sizeof(mmTA_PERFCOUNTER0_HI[0]), 0, 0 }, + { "mmTA_PERFCOUNTER1_LO", REG_MMIO, 0x32c2, 1, &mmTA_PERFCOUNTER1_LO[0], sizeof(mmTA_PERFCOUNTER1_LO)/sizeof(mmTA_PERFCOUNTER1_LO[0]), 0, 0 }, + { "mmTA_PERFCOUNTER1_HI", REG_MMIO, 0x32c3, 1, &mmTA_PERFCOUNTER1_HI[0], sizeof(mmTA_PERFCOUNTER1_HI)/sizeof(mmTA_PERFCOUNTER1_HI[0]), 0, 0 }, + { "mmTD_PERFCOUNTER0_LO", REG_MMIO, 0x3300, 1, &mmTD_PERFCOUNTER0_LO[0], sizeof(mmTD_PERFCOUNTER0_LO)/sizeof(mmTD_PERFCOUNTER0_LO[0]), 0, 0 }, + { "mmTD_PERFCOUNTER0_HI", REG_MMIO, 0x3301, 1, &mmTD_PERFCOUNTER0_HI[0], sizeof(mmTD_PERFCOUNTER0_HI)/sizeof(mmTD_PERFCOUNTER0_HI[0]), 0, 0 }, + { "mmTD_PERFCOUNTER1_LO", REG_MMIO, 0x3302, 1, &mmTD_PERFCOUNTER1_LO[0], sizeof(mmTD_PERFCOUNTER1_LO)/sizeof(mmTD_PERFCOUNTER1_LO[0]), 0, 0 }, + { "mmTD_PERFCOUNTER1_HI", REG_MMIO, 0x3303, 1, &mmTD_PERFCOUNTER1_HI[0], sizeof(mmTD_PERFCOUNTER1_HI)/sizeof(mmTD_PERFCOUNTER1_HI[0]), 0, 0 }, + { "mmTCP_PERFCOUNTER0_LO", REG_MMIO, 0x3340, 1, &mmTCP_PERFCOUNTER0_LO[0], sizeof(mmTCP_PERFCOUNTER0_LO)/sizeof(mmTCP_PERFCOUNTER0_LO[0]), 0, 0 }, + { "mmTCP_PERFCOUNTER0_HI", REG_MMIO, 0x3341, 1, &mmTCP_PERFCOUNTER0_HI[0], sizeof(mmTCP_PERFCOUNTER0_HI)/sizeof(mmTCP_PERFCOUNTER0_HI[0]), 0, 0 }, + { "mmTCP_PERFCOUNTER1_LO", REG_MMIO, 0x3342, 1, &mmTCP_PERFCOUNTER1_LO[0], sizeof(mmTCP_PERFCOUNTER1_LO)/sizeof(mmTCP_PERFCOUNTER1_LO[0]), 0, 0 }, + { "mmTCP_PERFCOUNTER1_HI", REG_MMIO, 0x3343, 1, &mmTCP_PERFCOUNTER1_HI[0], sizeof(mmTCP_PERFCOUNTER1_HI)/sizeof(mmTCP_PERFCOUNTER1_HI[0]), 0, 0 }, + { "mmTCP_PERFCOUNTER2_LO", REG_MMIO, 0x3344, 1, &mmTCP_PERFCOUNTER2_LO[0], sizeof(mmTCP_PERFCOUNTER2_LO)/sizeof(mmTCP_PERFCOUNTER2_LO[0]), 0, 0 }, + { "mmTCP_PERFCOUNTER2_HI", REG_MMIO, 0x3345, 1, &mmTCP_PERFCOUNTER2_HI[0], sizeof(mmTCP_PERFCOUNTER2_HI)/sizeof(mmTCP_PERFCOUNTER2_HI[0]), 0, 0 }, + { "mmTCP_PERFCOUNTER3_LO", REG_MMIO, 0x3346, 1, &mmTCP_PERFCOUNTER3_LO[0], sizeof(mmTCP_PERFCOUNTER3_LO)/sizeof(mmTCP_PERFCOUNTER3_LO[0]), 0, 0 }, + { "mmTCP_PERFCOUNTER3_HI", REG_MMIO, 0x3347, 1, &mmTCP_PERFCOUNTER3_HI[0], sizeof(mmTCP_PERFCOUNTER3_HI)/sizeof(mmTCP_PERFCOUNTER3_HI[0]), 0, 0 }, + { "mmTCC_PERFCOUNTER0_LO", REG_MMIO, 0x3380, 1, &mmTCC_PERFCOUNTER0_LO[0], sizeof(mmTCC_PERFCOUNTER0_LO)/sizeof(mmTCC_PERFCOUNTER0_LO[0]), 0, 0 }, + { "mmTCC_PERFCOUNTER0_HI", REG_MMIO, 0x3381, 1, &mmTCC_PERFCOUNTER0_HI[0], sizeof(mmTCC_PERFCOUNTER0_HI)/sizeof(mmTCC_PERFCOUNTER0_HI[0]), 0, 0 }, + { "mmTCC_PERFCOUNTER1_LO", REG_MMIO, 0x3382, 1, &mmTCC_PERFCOUNTER1_LO[0], sizeof(mmTCC_PERFCOUNTER1_LO)/sizeof(mmTCC_PERFCOUNTER1_LO[0]), 0, 0 }, + { "mmTCC_PERFCOUNTER1_HI", REG_MMIO, 0x3383, 1, &mmTCC_PERFCOUNTER1_HI[0], sizeof(mmTCC_PERFCOUNTER1_HI)/sizeof(mmTCC_PERFCOUNTER1_HI[0]), 0, 0 }, + { "mmTCC_PERFCOUNTER2_LO", REG_MMIO, 0x3384, 1, &mmTCC_PERFCOUNTER2_LO[0], sizeof(mmTCC_PERFCOUNTER2_LO)/sizeof(mmTCC_PERFCOUNTER2_LO[0]), 0, 0 }, + { "mmTCC_PERFCOUNTER2_HI", REG_MMIO, 0x3385, 1, &mmTCC_PERFCOUNTER2_HI[0], sizeof(mmTCC_PERFCOUNTER2_HI)/sizeof(mmTCC_PERFCOUNTER2_HI[0]), 0, 0 }, + { "mmTCC_PERFCOUNTER3_LO", REG_MMIO, 0x3386, 1, &mmTCC_PERFCOUNTER3_LO[0], sizeof(mmTCC_PERFCOUNTER3_LO)/sizeof(mmTCC_PERFCOUNTER3_LO[0]), 0, 0 }, + { "mmTCC_PERFCOUNTER3_HI", REG_MMIO, 0x3387, 1, &mmTCC_PERFCOUNTER3_HI[0], sizeof(mmTCC_PERFCOUNTER3_HI)/sizeof(mmTCC_PERFCOUNTER3_HI[0]), 0, 0 }, + { "mmTCA_PERFCOUNTER0_LO", REG_MMIO, 0x3390, 1, &mmTCA_PERFCOUNTER0_LO[0], sizeof(mmTCA_PERFCOUNTER0_LO)/sizeof(mmTCA_PERFCOUNTER0_LO[0]), 0, 0 }, + { "mmTCA_PERFCOUNTER0_HI", REG_MMIO, 0x3391, 1, &mmTCA_PERFCOUNTER0_HI[0], sizeof(mmTCA_PERFCOUNTER0_HI)/sizeof(mmTCA_PERFCOUNTER0_HI[0]), 0, 0 }, + { "mmTCA_PERFCOUNTER1_LO", REG_MMIO, 0x3392, 1, &mmTCA_PERFCOUNTER1_LO[0], sizeof(mmTCA_PERFCOUNTER1_LO)/sizeof(mmTCA_PERFCOUNTER1_LO[0]), 0, 0 }, + { "mmTCA_PERFCOUNTER1_HI", REG_MMIO, 0x3393, 1, &mmTCA_PERFCOUNTER1_HI[0], sizeof(mmTCA_PERFCOUNTER1_HI)/sizeof(mmTCA_PERFCOUNTER1_HI[0]), 0, 0 }, + { "mmTCA_PERFCOUNTER2_LO", REG_MMIO, 0x3394, 1, &mmTCA_PERFCOUNTER2_LO[0], sizeof(mmTCA_PERFCOUNTER2_LO)/sizeof(mmTCA_PERFCOUNTER2_LO[0]), 0, 0 }, + { "mmTCA_PERFCOUNTER2_HI", REG_MMIO, 0x3395, 1, &mmTCA_PERFCOUNTER2_HI[0], sizeof(mmTCA_PERFCOUNTER2_HI)/sizeof(mmTCA_PERFCOUNTER2_HI[0]), 0, 0 }, + { "mmTCA_PERFCOUNTER3_LO", REG_MMIO, 0x3396, 1, &mmTCA_PERFCOUNTER3_LO[0], sizeof(mmTCA_PERFCOUNTER3_LO)/sizeof(mmTCA_PERFCOUNTER3_LO[0]), 0, 0 }, + { "mmTCA_PERFCOUNTER3_HI", REG_MMIO, 0x3397, 1, &mmTCA_PERFCOUNTER3_HI[0], sizeof(mmTCA_PERFCOUNTER3_HI)/sizeof(mmTCA_PERFCOUNTER3_HI[0]), 0, 0 }, + { "mmCB_PERFCOUNTER0_LO", REG_MMIO, 0x3406, 1, &mmCB_PERFCOUNTER0_LO[0], sizeof(mmCB_PERFCOUNTER0_LO)/sizeof(mmCB_PERFCOUNTER0_LO[0]), 0, 0 }, + { "mmCB_PERFCOUNTER0_HI", REG_MMIO, 0x3407, 1, &mmCB_PERFCOUNTER0_HI[0], sizeof(mmCB_PERFCOUNTER0_HI)/sizeof(mmCB_PERFCOUNTER0_HI[0]), 0, 0 }, + { "mmCB_PERFCOUNTER1_LO", REG_MMIO, 0x3408, 1, &mmCB_PERFCOUNTER1_LO[0], sizeof(mmCB_PERFCOUNTER1_LO)/sizeof(mmCB_PERFCOUNTER1_LO[0]), 0, 0 }, + { "mmCB_PERFCOUNTER1_HI", REG_MMIO, 0x3409, 1, &mmCB_PERFCOUNTER1_HI[0], sizeof(mmCB_PERFCOUNTER1_HI)/sizeof(mmCB_PERFCOUNTER1_HI[0]), 0, 0 }, + { "mmCB_PERFCOUNTER2_LO", REG_MMIO, 0x340a, 1, &mmCB_PERFCOUNTER2_LO[0], sizeof(mmCB_PERFCOUNTER2_LO)/sizeof(mmCB_PERFCOUNTER2_LO[0]), 0, 0 }, + { "mmCB_PERFCOUNTER2_HI", REG_MMIO, 0x340b, 1, &mmCB_PERFCOUNTER2_HI[0], sizeof(mmCB_PERFCOUNTER2_HI)/sizeof(mmCB_PERFCOUNTER2_HI[0]), 0, 0 }, + { "mmCB_PERFCOUNTER3_LO", REG_MMIO, 0x340c, 1, &mmCB_PERFCOUNTER3_LO[0], sizeof(mmCB_PERFCOUNTER3_LO)/sizeof(mmCB_PERFCOUNTER3_LO[0]), 0, 0 }, + { "mmCB_PERFCOUNTER3_HI", REG_MMIO, 0x340d, 1, &mmCB_PERFCOUNTER3_HI[0], sizeof(mmCB_PERFCOUNTER3_HI)/sizeof(mmCB_PERFCOUNTER3_HI[0]), 0, 0 }, + { "mmDB_PERFCOUNTER0_LO", REG_MMIO, 0x3440, 1, &mmDB_PERFCOUNTER0_LO[0], sizeof(mmDB_PERFCOUNTER0_LO)/sizeof(mmDB_PERFCOUNTER0_LO[0]), 0, 0 }, + { "mmDB_PERFCOUNTER0_HI", REG_MMIO, 0x3441, 1, &mmDB_PERFCOUNTER0_HI[0], sizeof(mmDB_PERFCOUNTER0_HI)/sizeof(mmDB_PERFCOUNTER0_HI[0]), 0, 0 }, + { "mmDB_PERFCOUNTER1_LO", REG_MMIO, 0x3442, 1, &mmDB_PERFCOUNTER1_LO[0], sizeof(mmDB_PERFCOUNTER1_LO)/sizeof(mmDB_PERFCOUNTER1_LO[0]), 0, 0 }, + { "mmDB_PERFCOUNTER1_HI", REG_MMIO, 0x3443, 1, &mmDB_PERFCOUNTER1_HI[0], sizeof(mmDB_PERFCOUNTER1_HI)/sizeof(mmDB_PERFCOUNTER1_HI[0]), 0, 0 }, + { "mmDB_PERFCOUNTER2_LO", REG_MMIO, 0x3444, 1, &mmDB_PERFCOUNTER2_LO[0], sizeof(mmDB_PERFCOUNTER2_LO)/sizeof(mmDB_PERFCOUNTER2_LO[0]), 0, 0 }, + { "mmDB_PERFCOUNTER2_HI", REG_MMIO, 0x3445, 1, &mmDB_PERFCOUNTER2_HI[0], sizeof(mmDB_PERFCOUNTER2_HI)/sizeof(mmDB_PERFCOUNTER2_HI[0]), 0, 0 }, + { "mmDB_PERFCOUNTER3_LO", REG_MMIO, 0x3446, 1, &mmDB_PERFCOUNTER3_LO[0], sizeof(mmDB_PERFCOUNTER3_LO)/sizeof(mmDB_PERFCOUNTER3_LO[0]), 0, 0 }, + { "mmDB_PERFCOUNTER3_HI", REG_MMIO, 0x3447, 1, &mmDB_PERFCOUNTER3_HI[0], sizeof(mmDB_PERFCOUNTER3_HI)/sizeof(mmDB_PERFCOUNTER3_HI[0]), 0, 0 }, + { "mmRLC_PERFCOUNTER0_LO", REG_MMIO, 0x3480, 1, &mmRLC_PERFCOUNTER0_LO[0], sizeof(mmRLC_PERFCOUNTER0_LO)/sizeof(mmRLC_PERFCOUNTER0_LO[0]), 0, 0 }, + { "mmRLC_PERFCOUNTER0_HI", REG_MMIO, 0x3481, 1, &mmRLC_PERFCOUNTER0_HI[0], sizeof(mmRLC_PERFCOUNTER0_HI)/sizeof(mmRLC_PERFCOUNTER0_HI[0]), 0, 0 }, + { "mmRLC_PERFCOUNTER1_LO", REG_MMIO, 0x3482, 1, &mmRLC_PERFCOUNTER1_LO[0], sizeof(mmRLC_PERFCOUNTER1_LO)/sizeof(mmRLC_PERFCOUNTER1_LO[0]), 0, 0 }, + { "mmRLC_PERFCOUNTER1_HI", REG_MMIO, 0x3483, 1, &mmRLC_PERFCOUNTER1_HI[0], sizeof(mmRLC_PERFCOUNTER1_HI)/sizeof(mmRLC_PERFCOUNTER1_HI[0]), 0, 0 }, + { "mmRMI_PERFCOUNTER0_LO", REG_MMIO, 0x34c0, 1, &mmRMI_PERFCOUNTER0_LO[0], sizeof(mmRMI_PERFCOUNTER0_LO)/sizeof(mmRMI_PERFCOUNTER0_LO[0]), 0, 0 }, + { "mmRMI_PERFCOUNTER0_HI", REG_MMIO, 0x34c1, 1, &mmRMI_PERFCOUNTER0_HI[0], sizeof(mmRMI_PERFCOUNTER0_HI)/sizeof(mmRMI_PERFCOUNTER0_HI[0]), 0, 0 }, + { "mmRMI_PERFCOUNTER1_LO", REG_MMIO, 0x34c2, 1, &mmRMI_PERFCOUNTER1_LO[0], sizeof(mmRMI_PERFCOUNTER1_LO)/sizeof(mmRMI_PERFCOUNTER1_LO[0]), 0, 0 }, + { "mmRMI_PERFCOUNTER1_HI", REG_MMIO, 0x34c3, 1, &mmRMI_PERFCOUNTER1_HI[0], sizeof(mmRMI_PERFCOUNTER1_HI)/sizeof(mmRMI_PERFCOUNTER1_HI[0]), 0, 0 }, + { "mmRMI_PERFCOUNTER2_LO", REG_MMIO, 0x34c4, 1, &mmRMI_PERFCOUNTER2_LO[0], sizeof(mmRMI_PERFCOUNTER2_LO)/sizeof(mmRMI_PERFCOUNTER2_LO[0]), 0, 0 }, + { "mmRMI_PERFCOUNTER2_HI", REG_MMIO, 0x34c5, 1, &mmRMI_PERFCOUNTER2_HI[0], sizeof(mmRMI_PERFCOUNTER2_HI)/sizeof(mmRMI_PERFCOUNTER2_HI[0]), 0, 0 }, + { "mmRMI_PERFCOUNTER3_LO", REG_MMIO, 0x34c6, 1, &mmRMI_PERFCOUNTER3_LO[0], sizeof(mmRMI_PERFCOUNTER3_LO)/sizeof(mmRMI_PERFCOUNTER3_LO[0]), 0, 0 }, + { "mmRMI_PERFCOUNTER3_HI", REG_MMIO, 0x34c7, 1, &mmRMI_PERFCOUNTER3_HI[0], sizeof(mmRMI_PERFCOUNTER3_HI)/sizeof(mmRMI_PERFCOUNTER3_HI[0]), 0, 0 }, + { "mmATC_L2_PERFCOUNTER_LO", REG_MMIO, 0x3500, 1, &mmATC_L2_PERFCOUNTER_LO[0], sizeof(mmATC_L2_PERFCOUNTER_LO)/sizeof(mmATC_L2_PERFCOUNTER_LO[0]), 0, 0 }, + { "mmATC_L2_PERFCOUNTER_HI", REG_MMIO, 0x3501, 1, &mmATC_L2_PERFCOUNTER_HI[0], sizeof(mmATC_L2_PERFCOUNTER_HI)/sizeof(mmATC_L2_PERFCOUNTER_HI[0]), 0, 0 }, + { "mmMC_VM_L2_PERFCOUNTER_LO", REG_MMIO, 0x3508, 1, &mmMC_VM_L2_PERFCOUNTER_LO[0], sizeof(mmMC_VM_L2_PERFCOUNTER_LO)/sizeof(mmMC_VM_L2_PERFCOUNTER_LO[0]), 0, 0 }, + { "mmMC_VM_L2_PERFCOUNTER_HI", REG_MMIO, 0x3509, 1, &mmMC_VM_L2_PERFCOUNTER_HI[0], sizeof(mmMC_VM_L2_PERFCOUNTER_HI)/sizeof(mmMC_VM_L2_PERFCOUNTER_HI[0]), 0, 0 }, + { "mmCPG_PERFCOUNTER1_SELECT", REG_MMIO, 0x3800, 1, &mmCPG_PERFCOUNTER1_SELECT[0], sizeof(mmCPG_PERFCOUNTER1_SELECT)/sizeof(mmCPG_PERFCOUNTER1_SELECT[0]), 0, 0 }, + { "mmCPG_PERFCOUNTER0_SELECT1", REG_MMIO, 0x3801, 1, &mmCPG_PERFCOUNTER0_SELECT1[0], sizeof(mmCPG_PERFCOUNTER0_SELECT1)/sizeof(mmCPG_PERFCOUNTER0_SELECT1[0]), 0, 0 }, + { "mmCPG_PERFCOUNTER0_SELECT", REG_MMIO, 0x3802, 1, &mmCPG_PERFCOUNTER0_SELECT[0], sizeof(mmCPG_PERFCOUNTER0_SELECT)/sizeof(mmCPG_PERFCOUNTER0_SELECT[0]), 0, 0 }, + { "mmCPC_PERFCOUNTER1_SELECT", REG_MMIO, 0x3803, 1, &mmCPC_PERFCOUNTER1_SELECT[0], sizeof(mmCPC_PERFCOUNTER1_SELECT)/sizeof(mmCPC_PERFCOUNTER1_SELECT[0]), 0, 0 }, + { "mmCPC_PERFCOUNTER0_SELECT1", REG_MMIO, 0x3804, 1, &mmCPC_PERFCOUNTER0_SELECT1[0], sizeof(mmCPC_PERFCOUNTER0_SELECT1)/sizeof(mmCPC_PERFCOUNTER0_SELECT1[0]), 0, 0 }, + { "mmCPF_PERFCOUNTER1_SELECT", REG_MMIO, 0x3805, 1, &mmCPF_PERFCOUNTER1_SELECT[0], sizeof(mmCPF_PERFCOUNTER1_SELECT)/sizeof(mmCPF_PERFCOUNTER1_SELECT[0]), 0, 0 }, + { "mmCPF_PERFCOUNTER0_SELECT1", REG_MMIO, 0x3806, 1, &mmCPF_PERFCOUNTER0_SELECT1[0], sizeof(mmCPF_PERFCOUNTER0_SELECT1)/sizeof(mmCPF_PERFCOUNTER0_SELECT1[0]), 0, 0 }, + { "mmCPF_PERFCOUNTER0_SELECT", REG_MMIO, 0x3807, 1, &mmCPF_PERFCOUNTER0_SELECT[0], sizeof(mmCPF_PERFCOUNTER0_SELECT)/sizeof(mmCPF_PERFCOUNTER0_SELECT[0]), 0, 0 }, + { "mmCP_PERFMON_CNTL", REG_MMIO, 0x3808, 1, &mmCP_PERFMON_CNTL[0], sizeof(mmCP_PERFMON_CNTL)/sizeof(mmCP_PERFMON_CNTL[0]), 0, 0 }, + { "mmCPC_PERFCOUNTER0_SELECT", REG_MMIO, 0x3809, 1, &mmCPC_PERFCOUNTER0_SELECT[0], sizeof(mmCPC_PERFCOUNTER0_SELECT)/sizeof(mmCPC_PERFCOUNTER0_SELECT[0]), 0, 0 }, + { "mmCPF_TC_PERF_COUNTER_WINDOW_SELECT", REG_MMIO, 0x380a, 1, &mmCPF_TC_PERF_COUNTER_WINDOW_SELECT[0], sizeof(mmCPF_TC_PERF_COUNTER_WINDOW_SELECT)/sizeof(mmCPF_TC_PERF_COUNTER_WINDOW_SELECT[0]), 0, 0 }, + { "mmCPG_TC_PERF_COUNTER_WINDOW_SELECT", REG_MMIO, 0x380b, 1, &mmCPG_TC_PERF_COUNTER_WINDOW_SELECT[0], sizeof(mmCPG_TC_PERF_COUNTER_WINDOW_SELECT)/sizeof(mmCPG_TC_PERF_COUNTER_WINDOW_SELECT[0]), 0, 0 }, + { "mmCPF_LATENCY_STATS_SELECT", REG_MMIO, 0x380c, 1, &mmCPF_LATENCY_STATS_SELECT[0], sizeof(mmCPF_LATENCY_STATS_SELECT)/sizeof(mmCPF_LATENCY_STATS_SELECT[0]), 0, 0 }, + { "mmCPG_LATENCY_STATS_SELECT", REG_MMIO, 0x380d, 1, &mmCPG_LATENCY_STATS_SELECT[0], sizeof(mmCPG_LATENCY_STATS_SELECT)/sizeof(mmCPG_LATENCY_STATS_SELECT[0]), 0, 0 }, + { "mmCPC_LATENCY_STATS_SELECT", REG_MMIO, 0x380e, 1, &mmCPC_LATENCY_STATS_SELECT[0], sizeof(mmCPC_LATENCY_STATS_SELECT)/sizeof(mmCPC_LATENCY_STATS_SELECT[0]), 0, 0 }, + { "mmCP_DRAW_OBJECT", REG_MMIO, 0x3810, 1, &mmCP_DRAW_OBJECT[0], sizeof(mmCP_DRAW_OBJECT)/sizeof(mmCP_DRAW_OBJECT[0]), 0, 0 }, + { "mmCP_DRAW_OBJECT_COUNTER", REG_MMIO, 0x3811, 1, &mmCP_DRAW_OBJECT_COUNTER[0], sizeof(mmCP_DRAW_OBJECT_COUNTER)/sizeof(mmCP_DRAW_OBJECT_COUNTER[0]), 0, 0 }, + { "mmCP_DRAW_WINDOW_MASK_HI", REG_MMIO, 0x3812, 1, &mmCP_DRAW_WINDOW_MASK_HI[0], sizeof(mmCP_DRAW_WINDOW_MASK_HI)/sizeof(mmCP_DRAW_WINDOW_MASK_HI[0]), 0, 0 }, + { "mmCP_DRAW_WINDOW_HI", REG_MMIO, 0x3813, 1, &mmCP_DRAW_WINDOW_HI[0], sizeof(mmCP_DRAW_WINDOW_HI)/sizeof(mmCP_DRAW_WINDOW_HI[0]), 0, 0 }, + { "mmCP_DRAW_WINDOW_LO", REG_MMIO, 0x3814, 1, &mmCP_DRAW_WINDOW_LO[0], sizeof(mmCP_DRAW_WINDOW_LO)/sizeof(mmCP_DRAW_WINDOW_LO[0]), 0, 0 }, + { "mmCP_DRAW_WINDOW_CNTL", REG_MMIO, 0x3815, 1, &mmCP_DRAW_WINDOW_CNTL[0], sizeof(mmCP_DRAW_WINDOW_CNTL)/sizeof(mmCP_DRAW_WINDOW_CNTL[0]), 0, 0 }, + { "mmGRBM_PERFCOUNTER0_SELECT", REG_MMIO, 0x3840, 1, &mmGRBM_PERFCOUNTER0_SELECT[0], sizeof(mmGRBM_PERFCOUNTER0_SELECT)/sizeof(mmGRBM_PERFCOUNTER0_SELECT[0]), 0, 0 }, + { "mmGRBM_PERFCOUNTER1_SELECT", REG_MMIO, 0x3841, 1, &mmGRBM_PERFCOUNTER1_SELECT[0], sizeof(mmGRBM_PERFCOUNTER1_SELECT)/sizeof(mmGRBM_PERFCOUNTER1_SELECT[0]), 0, 0 }, + { "mmGRBM_SE0_PERFCOUNTER_SELECT", REG_MMIO, 0x3842, 1, &mmGRBM_SE0_PERFCOUNTER_SELECT[0], sizeof(mmGRBM_SE0_PERFCOUNTER_SELECT)/sizeof(mmGRBM_SE0_PERFCOUNTER_SELECT[0]), 0, 0 }, + { "mmGRBM_SE1_PERFCOUNTER_SELECT", REG_MMIO, 0x3843, 1, &mmGRBM_SE1_PERFCOUNTER_SELECT[0], sizeof(mmGRBM_SE1_PERFCOUNTER_SELECT)/sizeof(mmGRBM_SE1_PERFCOUNTER_SELECT[0]), 0, 0 }, + { "mmGRBM_SE2_PERFCOUNTER_SELECT", REG_MMIO, 0x3844, 1, &mmGRBM_SE2_PERFCOUNTER_SELECT[0], sizeof(mmGRBM_SE2_PERFCOUNTER_SELECT)/sizeof(mmGRBM_SE2_PERFCOUNTER_SELECT[0]), 0, 0 }, + { "mmGRBM_SE3_PERFCOUNTER_SELECT", REG_MMIO, 0x3845, 1, &mmGRBM_SE3_PERFCOUNTER_SELECT[0], sizeof(mmGRBM_SE3_PERFCOUNTER_SELECT)/sizeof(mmGRBM_SE3_PERFCOUNTER_SELECT[0]), 0, 0 }, + { "mmWD_PERFCOUNTER0_SELECT", REG_MMIO, 0x3880, 1, &mmWD_PERFCOUNTER0_SELECT[0], sizeof(mmWD_PERFCOUNTER0_SELECT)/sizeof(mmWD_PERFCOUNTER0_SELECT[0]), 0, 0 }, + { "mmWD_PERFCOUNTER1_SELECT", REG_MMIO, 0x3881, 1, &mmWD_PERFCOUNTER1_SELECT[0], sizeof(mmWD_PERFCOUNTER1_SELECT)/sizeof(mmWD_PERFCOUNTER1_SELECT[0]), 0, 0 }, + { "mmWD_PERFCOUNTER2_SELECT", REG_MMIO, 0x3882, 1, &mmWD_PERFCOUNTER2_SELECT[0], sizeof(mmWD_PERFCOUNTER2_SELECT)/sizeof(mmWD_PERFCOUNTER2_SELECT[0]), 0, 0 }, + { "mmWD_PERFCOUNTER3_SELECT", REG_MMIO, 0x3883, 1, &mmWD_PERFCOUNTER3_SELECT[0], sizeof(mmWD_PERFCOUNTER3_SELECT)/sizeof(mmWD_PERFCOUNTER3_SELECT[0]), 0, 0 }, + { "mmIA_PERFCOUNTER0_SELECT", REG_MMIO, 0x3884, 1, &mmIA_PERFCOUNTER0_SELECT[0], sizeof(mmIA_PERFCOUNTER0_SELECT)/sizeof(mmIA_PERFCOUNTER0_SELECT[0]), 0, 0 }, + { "mmIA_PERFCOUNTER1_SELECT", REG_MMIO, 0x3885, 1, &mmIA_PERFCOUNTER1_SELECT[0], sizeof(mmIA_PERFCOUNTER1_SELECT)/sizeof(mmIA_PERFCOUNTER1_SELECT[0]), 0, 0 }, + { "mmIA_PERFCOUNTER2_SELECT", REG_MMIO, 0x3886, 1, &mmIA_PERFCOUNTER2_SELECT[0], sizeof(mmIA_PERFCOUNTER2_SELECT)/sizeof(mmIA_PERFCOUNTER2_SELECT[0]), 0, 0 }, + { "mmIA_PERFCOUNTER3_SELECT", REG_MMIO, 0x3887, 1, &mmIA_PERFCOUNTER3_SELECT[0], sizeof(mmIA_PERFCOUNTER3_SELECT)/sizeof(mmIA_PERFCOUNTER3_SELECT[0]), 0, 0 }, + { "mmIA_PERFCOUNTER0_SELECT1", REG_MMIO, 0x3888, 1, &mmIA_PERFCOUNTER0_SELECT1[0], sizeof(mmIA_PERFCOUNTER0_SELECT1)/sizeof(mmIA_PERFCOUNTER0_SELECT1[0]), 0, 0 }, + { "mmVGT_PERFCOUNTER0_SELECT", REG_MMIO, 0x388c, 1, &mmVGT_PERFCOUNTER0_SELECT[0], sizeof(mmVGT_PERFCOUNTER0_SELECT)/sizeof(mmVGT_PERFCOUNTER0_SELECT[0]), 0, 0 }, + { "mmVGT_PERFCOUNTER1_SELECT", REG_MMIO, 0x388d, 1, &mmVGT_PERFCOUNTER1_SELECT[0], sizeof(mmVGT_PERFCOUNTER1_SELECT)/sizeof(mmVGT_PERFCOUNTER1_SELECT[0]), 0, 0 }, + { "mmVGT_PERFCOUNTER2_SELECT", REG_MMIO, 0x388e, 1, &mmVGT_PERFCOUNTER2_SELECT[0], sizeof(mmVGT_PERFCOUNTER2_SELECT)/sizeof(mmVGT_PERFCOUNTER2_SELECT[0]), 0, 0 }, + { "mmVGT_PERFCOUNTER3_SELECT", REG_MMIO, 0x388f, 1, &mmVGT_PERFCOUNTER3_SELECT[0], sizeof(mmVGT_PERFCOUNTER3_SELECT)/sizeof(mmVGT_PERFCOUNTER3_SELECT[0]), 0, 0 }, + { "mmVGT_PERFCOUNTER0_SELECT1", REG_MMIO, 0x3890, 1, &mmVGT_PERFCOUNTER0_SELECT1[0], sizeof(mmVGT_PERFCOUNTER0_SELECT1)/sizeof(mmVGT_PERFCOUNTER0_SELECT1[0]), 0, 0 }, + { "mmVGT_PERFCOUNTER1_SELECT1", REG_MMIO, 0x3891, 1, &mmVGT_PERFCOUNTER1_SELECT1[0], sizeof(mmVGT_PERFCOUNTER1_SELECT1)/sizeof(mmVGT_PERFCOUNTER1_SELECT1[0]), 0, 0 }, + { "mmVGT_PERFCOUNTER_SEID_MASK", REG_MMIO, 0x3894, 1, &mmVGT_PERFCOUNTER_SEID_MASK[0], sizeof(mmVGT_PERFCOUNTER_SEID_MASK)/sizeof(mmVGT_PERFCOUNTER_SEID_MASK[0]), 0, 0 }, + { "mmPA_SU_PERFCOUNTER0_SELECT", REG_MMIO, 0x3900, 1, &mmPA_SU_PERFCOUNTER0_SELECT[0], sizeof(mmPA_SU_PERFCOUNTER0_SELECT)/sizeof(mmPA_SU_PERFCOUNTER0_SELECT[0]), 0, 0 }, + { "mmPA_SU_PERFCOUNTER0_SELECT1", REG_MMIO, 0x3901, 1, &mmPA_SU_PERFCOUNTER0_SELECT1[0], sizeof(mmPA_SU_PERFCOUNTER0_SELECT1)/sizeof(mmPA_SU_PERFCOUNTER0_SELECT1[0]), 0, 0 }, + { "mmPA_SU_PERFCOUNTER1_SELECT", REG_MMIO, 0x3902, 1, &mmPA_SU_PERFCOUNTER1_SELECT[0], sizeof(mmPA_SU_PERFCOUNTER1_SELECT)/sizeof(mmPA_SU_PERFCOUNTER1_SELECT[0]), 0, 0 }, + { "mmPA_SU_PERFCOUNTER1_SELECT1", REG_MMIO, 0x3903, 1, &mmPA_SU_PERFCOUNTER1_SELECT1[0], sizeof(mmPA_SU_PERFCOUNTER1_SELECT1)/sizeof(mmPA_SU_PERFCOUNTER1_SELECT1[0]), 0, 0 }, + { "mmPA_SU_PERFCOUNTER2_SELECT", REG_MMIO, 0x3904, 1, &mmPA_SU_PERFCOUNTER2_SELECT[0], sizeof(mmPA_SU_PERFCOUNTER2_SELECT)/sizeof(mmPA_SU_PERFCOUNTER2_SELECT[0]), 0, 0 }, + { "mmPA_SU_PERFCOUNTER3_SELECT", REG_MMIO, 0x3905, 1, &mmPA_SU_PERFCOUNTER3_SELECT[0], sizeof(mmPA_SU_PERFCOUNTER3_SELECT)/sizeof(mmPA_SU_PERFCOUNTER3_SELECT[0]), 0, 0 }, + { "mmPA_SC_PERFCOUNTER0_SELECT", REG_MMIO, 0x3940, 1, &mmPA_SC_PERFCOUNTER0_SELECT[0], sizeof(mmPA_SC_PERFCOUNTER0_SELECT)/sizeof(mmPA_SC_PERFCOUNTER0_SELECT[0]), 0, 0 }, + { "mmPA_SC_PERFCOUNTER0_SELECT1", REG_MMIO, 0x3941, 1, &mmPA_SC_PERFCOUNTER0_SELECT1[0], sizeof(mmPA_SC_PERFCOUNTER0_SELECT1)/sizeof(mmPA_SC_PERFCOUNTER0_SELECT1[0]), 0, 0 }, + { "mmPA_SC_PERFCOUNTER1_SELECT", REG_MMIO, 0x3942, 1, &mmPA_SC_PERFCOUNTER1_SELECT[0], sizeof(mmPA_SC_PERFCOUNTER1_SELECT)/sizeof(mmPA_SC_PERFCOUNTER1_SELECT[0]), 0, 0 }, + { "mmPA_SC_PERFCOUNTER2_SELECT", REG_MMIO, 0x3943, 1, &mmPA_SC_PERFCOUNTER2_SELECT[0], sizeof(mmPA_SC_PERFCOUNTER2_SELECT)/sizeof(mmPA_SC_PERFCOUNTER2_SELECT[0]), 0, 0 }, + { "mmPA_SC_PERFCOUNTER3_SELECT", REG_MMIO, 0x3944, 1, &mmPA_SC_PERFCOUNTER3_SELECT[0], sizeof(mmPA_SC_PERFCOUNTER3_SELECT)/sizeof(mmPA_SC_PERFCOUNTER3_SELECT[0]), 0, 0 }, + { "mmPA_SC_PERFCOUNTER4_SELECT", REG_MMIO, 0x3945, 1, &mmPA_SC_PERFCOUNTER4_SELECT[0], sizeof(mmPA_SC_PERFCOUNTER4_SELECT)/sizeof(mmPA_SC_PERFCOUNTER4_SELECT[0]), 0, 0 }, + { "mmPA_SC_PERFCOUNTER5_SELECT", REG_MMIO, 0x3946, 1, &mmPA_SC_PERFCOUNTER5_SELECT[0], sizeof(mmPA_SC_PERFCOUNTER5_SELECT)/sizeof(mmPA_SC_PERFCOUNTER5_SELECT[0]), 0, 0 }, + { "mmPA_SC_PERFCOUNTER6_SELECT", REG_MMIO, 0x3947, 1, &mmPA_SC_PERFCOUNTER6_SELECT[0], sizeof(mmPA_SC_PERFCOUNTER6_SELECT)/sizeof(mmPA_SC_PERFCOUNTER6_SELECT[0]), 0, 0 }, + { "mmPA_SC_PERFCOUNTER7_SELECT", REG_MMIO, 0x3948, 1, &mmPA_SC_PERFCOUNTER7_SELECT[0], sizeof(mmPA_SC_PERFCOUNTER7_SELECT)/sizeof(mmPA_SC_PERFCOUNTER7_SELECT[0]), 0, 0 }, + { "mmSPI_PERFCOUNTER0_SELECT", REG_MMIO, 0x3980, 1, &mmSPI_PERFCOUNTER0_SELECT[0], sizeof(mmSPI_PERFCOUNTER0_SELECT)/sizeof(mmSPI_PERFCOUNTER0_SELECT[0]), 0, 0 }, + { "mmSPI_PERFCOUNTER1_SELECT", REG_MMIO, 0x3981, 1, &mmSPI_PERFCOUNTER1_SELECT[0], sizeof(mmSPI_PERFCOUNTER1_SELECT)/sizeof(mmSPI_PERFCOUNTER1_SELECT[0]), 0, 0 }, + { "mmSPI_PERFCOUNTER2_SELECT", REG_MMIO, 0x3982, 1, &mmSPI_PERFCOUNTER2_SELECT[0], sizeof(mmSPI_PERFCOUNTER2_SELECT)/sizeof(mmSPI_PERFCOUNTER2_SELECT[0]), 0, 0 }, + { "mmSPI_PERFCOUNTER3_SELECT", REG_MMIO, 0x3983, 1, &mmSPI_PERFCOUNTER3_SELECT[0], sizeof(mmSPI_PERFCOUNTER3_SELECT)/sizeof(mmSPI_PERFCOUNTER3_SELECT[0]), 0, 0 }, + { "mmSPI_PERFCOUNTER0_SELECT1", REG_MMIO, 0x3984, 1, &mmSPI_PERFCOUNTER0_SELECT1[0], sizeof(mmSPI_PERFCOUNTER0_SELECT1)/sizeof(mmSPI_PERFCOUNTER0_SELECT1[0]), 0, 0 }, + { "mmSPI_PERFCOUNTER1_SELECT1", REG_MMIO, 0x3985, 1, &mmSPI_PERFCOUNTER1_SELECT1[0], sizeof(mmSPI_PERFCOUNTER1_SELECT1)/sizeof(mmSPI_PERFCOUNTER1_SELECT1[0]), 0, 0 }, + { "mmSPI_PERFCOUNTER2_SELECT1", REG_MMIO, 0x3986, 1, &mmSPI_PERFCOUNTER2_SELECT1[0], sizeof(mmSPI_PERFCOUNTER2_SELECT1)/sizeof(mmSPI_PERFCOUNTER2_SELECT1[0]), 0, 0 }, + { "mmSPI_PERFCOUNTER3_SELECT1", REG_MMIO, 0x3987, 1, &mmSPI_PERFCOUNTER3_SELECT1[0], sizeof(mmSPI_PERFCOUNTER3_SELECT1)/sizeof(mmSPI_PERFCOUNTER3_SELECT1[0]), 0, 0 }, + { "mmSPI_PERFCOUNTER4_SELECT", REG_MMIO, 0x3988, 1, &mmSPI_PERFCOUNTER4_SELECT[0], sizeof(mmSPI_PERFCOUNTER4_SELECT)/sizeof(mmSPI_PERFCOUNTER4_SELECT[0]), 0, 0 }, + { "mmSPI_PERFCOUNTER5_SELECT", REG_MMIO, 0x3989, 1, &mmSPI_PERFCOUNTER5_SELECT[0], sizeof(mmSPI_PERFCOUNTER5_SELECT)/sizeof(mmSPI_PERFCOUNTER5_SELECT[0]), 0, 0 }, + { "mmSPI_PERFCOUNTER_BINS", REG_MMIO, 0x398a, 1, &mmSPI_PERFCOUNTER_BINS[0], sizeof(mmSPI_PERFCOUNTER_BINS)/sizeof(mmSPI_PERFCOUNTER_BINS[0]), 0, 0 }, + { "mmSQ_PERFCOUNTER0_SELECT", REG_MMIO, 0x39c0, 1, &mmSQ_PERFCOUNTER0_SELECT[0], sizeof(mmSQ_PERFCOUNTER0_SELECT)/sizeof(mmSQ_PERFCOUNTER0_SELECT[0]), 0, 0 }, + { "mmSQ_PERFCOUNTER1_SELECT", REG_MMIO, 0x39c1, 1, &mmSQ_PERFCOUNTER1_SELECT[0], sizeof(mmSQ_PERFCOUNTER1_SELECT)/sizeof(mmSQ_PERFCOUNTER1_SELECT[0]), 0, 0 }, + { "mmSQ_PERFCOUNTER2_SELECT", REG_MMIO, 0x39c2, 1, &mmSQ_PERFCOUNTER2_SELECT[0], sizeof(mmSQ_PERFCOUNTER2_SELECT)/sizeof(mmSQ_PERFCOUNTER2_SELECT[0]), 0, 0 }, + { "mmSQ_PERFCOUNTER3_SELECT", REG_MMIO, 0x39c3, 1, &mmSQ_PERFCOUNTER3_SELECT[0], sizeof(mmSQ_PERFCOUNTER3_SELECT)/sizeof(mmSQ_PERFCOUNTER3_SELECT[0]), 0, 0 }, + { "mmSQ_PERFCOUNTER4_SELECT", REG_MMIO, 0x39c4, 1, &mmSQ_PERFCOUNTER4_SELECT[0], sizeof(mmSQ_PERFCOUNTER4_SELECT)/sizeof(mmSQ_PERFCOUNTER4_SELECT[0]), 0, 0 }, + { "mmSQ_PERFCOUNTER5_SELECT", REG_MMIO, 0x39c5, 1, &mmSQ_PERFCOUNTER5_SELECT[0], sizeof(mmSQ_PERFCOUNTER5_SELECT)/sizeof(mmSQ_PERFCOUNTER5_SELECT[0]), 0, 0 }, + { "mmSQ_PERFCOUNTER6_SELECT", REG_MMIO, 0x39c6, 1, &mmSQ_PERFCOUNTER6_SELECT[0], sizeof(mmSQ_PERFCOUNTER6_SELECT)/sizeof(mmSQ_PERFCOUNTER6_SELECT[0]), 0, 0 }, + { "mmSQ_PERFCOUNTER7_SELECT", REG_MMIO, 0x39c7, 1, &mmSQ_PERFCOUNTER7_SELECT[0], sizeof(mmSQ_PERFCOUNTER7_SELECT)/sizeof(mmSQ_PERFCOUNTER7_SELECT[0]), 0, 0 }, + { "mmSQ_PERFCOUNTER8_SELECT", REG_MMIO, 0x39c8, 1, &mmSQ_PERFCOUNTER8_SELECT[0], sizeof(mmSQ_PERFCOUNTER8_SELECT)/sizeof(mmSQ_PERFCOUNTER8_SELECT[0]), 0, 0 }, + { "mmSQ_PERFCOUNTER9_SELECT", REG_MMIO, 0x39c9, 1, &mmSQ_PERFCOUNTER9_SELECT[0], sizeof(mmSQ_PERFCOUNTER9_SELECT)/sizeof(mmSQ_PERFCOUNTER9_SELECT[0]), 0, 0 }, + { "mmSQ_PERFCOUNTER10_SELECT", REG_MMIO, 0x39ca, 1, &mmSQ_PERFCOUNTER10_SELECT[0], sizeof(mmSQ_PERFCOUNTER10_SELECT)/sizeof(mmSQ_PERFCOUNTER10_SELECT[0]), 0, 0 }, + { "mmSQ_PERFCOUNTER11_SELECT", REG_MMIO, 0x39cb, 1, &mmSQ_PERFCOUNTER11_SELECT[0], sizeof(mmSQ_PERFCOUNTER11_SELECT)/sizeof(mmSQ_PERFCOUNTER11_SELECT[0]), 0, 0 }, + { "mmSQ_PERFCOUNTER12_SELECT", REG_MMIO, 0x39cc, 1, &mmSQ_PERFCOUNTER12_SELECT[0], sizeof(mmSQ_PERFCOUNTER12_SELECT)/sizeof(mmSQ_PERFCOUNTER12_SELECT[0]), 0, 0 }, + { "mmSQ_PERFCOUNTER13_SELECT", REG_MMIO, 0x39cd, 1, &mmSQ_PERFCOUNTER13_SELECT[0], sizeof(mmSQ_PERFCOUNTER13_SELECT)/sizeof(mmSQ_PERFCOUNTER13_SELECT[0]), 0, 0 }, + { "mmSQ_PERFCOUNTER14_SELECT", REG_MMIO, 0x39ce, 1, &mmSQ_PERFCOUNTER14_SELECT[0], sizeof(mmSQ_PERFCOUNTER14_SELECT)/sizeof(mmSQ_PERFCOUNTER14_SELECT[0]), 0, 0 }, + { "mmSQ_PERFCOUNTER15_SELECT", REG_MMIO, 0x39cf, 1, &mmSQ_PERFCOUNTER15_SELECT[0], sizeof(mmSQ_PERFCOUNTER15_SELECT)/sizeof(mmSQ_PERFCOUNTER15_SELECT[0]), 0, 0 }, + { "mmSQ_PERFCOUNTER_CTRL", REG_MMIO, 0x39e0, 1, &mmSQ_PERFCOUNTER_CTRL[0], sizeof(mmSQ_PERFCOUNTER_CTRL)/sizeof(mmSQ_PERFCOUNTER_CTRL[0]), 0, 0 }, + { "mmSQ_PERFCOUNTER_MASK", REG_MMIO, 0x39e1, 1, &mmSQ_PERFCOUNTER_MASK[0], sizeof(mmSQ_PERFCOUNTER_MASK)/sizeof(mmSQ_PERFCOUNTER_MASK[0]), 0, 0 }, + { "mmSQ_PERFCOUNTER_CTRL2", REG_MMIO, 0x39e2, 1, &mmSQ_PERFCOUNTER_CTRL2[0], sizeof(mmSQ_PERFCOUNTER_CTRL2)/sizeof(mmSQ_PERFCOUNTER_CTRL2[0]), 0, 0 }, + { "mmSX_PERFCOUNTER0_SELECT", REG_MMIO, 0x3a40, 1, &mmSX_PERFCOUNTER0_SELECT[0], sizeof(mmSX_PERFCOUNTER0_SELECT)/sizeof(mmSX_PERFCOUNTER0_SELECT[0]), 0, 0 }, + { "mmSX_PERFCOUNTER1_SELECT", REG_MMIO, 0x3a41, 1, &mmSX_PERFCOUNTER1_SELECT[0], sizeof(mmSX_PERFCOUNTER1_SELECT)/sizeof(mmSX_PERFCOUNTER1_SELECT[0]), 0, 0 }, + { "mmSX_PERFCOUNTER2_SELECT", REG_MMIO, 0x3a42, 1, &mmSX_PERFCOUNTER2_SELECT[0], sizeof(mmSX_PERFCOUNTER2_SELECT)/sizeof(mmSX_PERFCOUNTER2_SELECT[0]), 0, 0 }, + { "mmSX_PERFCOUNTER3_SELECT", REG_MMIO, 0x3a43, 1, &mmSX_PERFCOUNTER3_SELECT[0], sizeof(mmSX_PERFCOUNTER3_SELECT)/sizeof(mmSX_PERFCOUNTER3_SELECT[0]), 0, 0 }, + { "mmSX_PERFCOUNTER0_SELECT1", REG_MMIO, 0x3a44, 1, &mmSX_PERFCOUNTER0_SELECT1[0], sizeof(mmSX_PERFCOUNTER0_SELECT1)/sizeof(mmSX_PERFCOUNTER0_SELECT1[0]), 0, 0 }, + { "mmSX_PERFCOUNTER1_SELECT1", REG_MMIO, 0x3a45, 1, &mmSX_PERFCOUNTER1_SELECT1[0], sizeof(mmSX_PERFCOUNTER1_SELECT1)/sizeof(mmSX_PERFCOUNTER1_SELECT1[0]), 0, 0 }, + { "mmGDS_PERFCOUNTER0_SELECT", REG_MMIO, 0x3a80, 1, &mmGDS_PERFCOUNTER0_SELECT[0], sizeof(mmGDS_PERFCOUNTER0_SELECT)/sizeof(mmGDS_PERFCOUNTER0_SELECT[0]), 0, 0 }, + { "mmGDS_PERFCOUNTER1_SELECT", REG_MMIO, 0x3a81, 1, &mmGDS_PERFCOUNTER1_SELECT[0], sizeof(mmGDS_PERFCOUNTER1_SELECT)/sizeof(mmGDS_PERFCOUNTER1_SELECT[0]), 0, 0 }, + { "mmGDS_PERFCOUNTER2_SELECT", REG_MMIO, 0x3a82, 1, &mmGDS_PERFCOUNTER2_SELECT[0], sizeof(mmGDS_PERFCOUNTER2_SELECT)/sizeof(mmGDS_PERFCOUNTER2_SELECT[0]), 0, 0 }, + { "mmGDS_PERFCOUNTER3_SELECT", REG_MMIO, 0x3a83, 1, &mmGDS_PERFCOUNTER3_SELECT[0], sizeof(mmGDS_PERFCOUNTER3_SELECT)/sizeof(mmGDS_PERFCOUNTER3_SELECT[0]), 0, 0 }, + { "mmGDS_PERFCOUNTER0_SELECT1", REG_MMIO, 0x3a84, 1, &mmGDS_PERFCOUNTER0_SELECT1[0], sizeof(mmGDS_PERFCOUNTER0_SELECT1)/sizeof(mmGDS_PERFCOUNTER0_SELECT1[0]), 0, 0 }, + { "mmTA_PERFCOUNTER0_SELECT", REG_MMIO, 0x3ac0, 1, &mmTA_PERFCOUNTER0_SELECT[0], sizeof(mmTA_PERFCOUNTER0_SELECT)/sizeof(mmTA_PERFCOUNTER0_SELECT[0]), 0, 0 }, + { "mmTA_PERFCOUNTER0_SELECT1", REG_MMIO, 0x3ac1, 1, &mmTA_PERFCOUNTER0_SELECT1[0], sizeof(mmTA_PERFCOUNTER0_SELECT1)/sizeof(mmTA_PERFCOUNTER0_SELECT1[0]), 0, 0 }, + { "mmTA_PERFCOUNTER1_SELECT", REG_MMIO, 0x3ac2, 1, &mmTA_PERFCOUNTER1_SELECT[0], sizeof(mmTA_PERFCOUNTER1_SELECT)/sizeof(mmTA_PERFCOUNTER1_SELECT[0]), 0, 0 }, + { "mmTD_PERFCOUNTER0_SELECT", REG_MMIO, 0x3b00, 1, &mmTD_PERFCOUNTER0_SELECT[0], sizeof(mmTD_PERFCOUNTER0_SELECT)/sizeof(mmTD_PERFCOUNTER0_SELECT[0]), 0, 0 }, + { "mmTD_PERFCOUNTER0_SELECT1", REG_MMIO, 0x3b01, 1, &mmTD_PERFCOUNTER0_SELECT1[0], sizeof(mmTD_PERFCOUNTER0_SELECT1)/sizeof(mmTD_PERFCOUNTER0_SELECT1[0]), 0, 0 }, + { "mmTD_PERFCOUNTER1_SELECT", REG_MMIO, 0x3b02, 1, &mmTD_PERFCOUNTER1_SELECT[0], sizeof(mmTD_PERFCOUNTER1_SELECT)/sizeof(mmTD_PERFCOUNTER1_SELECT[0]), 0, 0 }, + { "mmTCP_PERFCOUNTER0_SELECT", REG_MMIO, 0x3b40, 1, &mmTCP_PERFCOUNTER0_SELECT[0], sizeof(mmTCP_PERFCOUNTER0_SELECT)/sizeof(mmTCP_PERFCOUNTER0_SELECT[0]), 0, 0 }, + { "mmTCP_PERFCOUNTER0_SELECT1", REG_MMIO, 0x3b41, 1, &mmTCP_PERFCOUNTER0_SELECT1[0], sizeof(mmTCP_PERFCOUNTER0_SELECT1)/sizeof(mmTCP_PERFCOUNTER0_SELECT1[0]), 0, 0 }, + { "mmTCP_PERFCOUNTER1_SELECT", REG_MMIO, 0x3b42, 1, &mmTCP_PERFCOUNTER1_SELECT[0], sizeof(mmTCP_PERFCOUNTER1_SELECT)/sizeof(mmTCP_PERFCOUNTER1_SELECT[0]), 0, 0 }, + { "mmTCP_PERFCOUNTER1_SELECT1", REG_MMIO, 0x3b43, 1, &mmTCP_PERFCOUNTER1_SELECT1[0], sizeof(mmTCP_PERFCOUNTER1_SELECT1)/sizeof(mmTCP_PERFCOUNTER1_SELECT1[0]), 0, 0 }, + { "mmTCP_PERFCOUNTER2_SELECT", REG_MMIO, 0x3b44, 1, &mmTCP_PERFCOUNTER2_SELECT[0], sizeof(mmTCP_PERFCOUNTER2_SELECT)/sizeof(mmTCP_PERFCOUNTER2_SELECT[0]), 0, 0 }, + { "mmTCP_PERFCOUNTER3_SELECT", REG_MMIO, 0x3b45, 1, &mmTCP_PERFCOUNTER3_SELECT[0], sizeof(mmTCP_PERFCOUNTER3_SELECT)/sizeof(mmTCP_PERFCOUNTER3_SELECT[0]), 0, 0 }, + { "mmTCC_PERFCOUNTER0_SELECT", REG_MMIO, 0x3b80, 1, &mmTCC_PERFCOUNTER0_SELECT[0], sizeof(mmTCC_PERFCOUNTER0_SELECT)/sizeof(mmTCC_PERFCOUNTER0_SELECT[0]), 0, 0 }, + { "mmTCC_PERFCOUNTER0_SELECT1", REG_MMIO, 0x3b81, 1, &mmTCC_PERFCOUNTER0_SELECT1[0], sizeof(mmTCC_PERFCOUNTER0_SELECT1)/sizeof(mmTCC_PERFCOUNTER0_SELECT1[0]), 0, 0 }, + { "mmTCC_PERFCOUNTER1_SELECT", REG_MMIO, 0x3b82, 1, &mmTCC_PERFCOUNTER1_SELECT[0], sizeof(mmTCC_PERFCOUNTER1_SELECT)/sizeof(mmTCC_PERFCOUNTER1_SELECT[0]), 0, 0 }, + { "mmTCC_PERFCOUNTER1_SELECT1", REG_MMIO, 0x3b83, 1, &mmTCC_PERFCOUNTER1_SELECT1[0], sizeof(mmTCC_PERFCOUNTER1_SELECT1)/sizeof(mmTCC_PERFCOUNTER1_SELECT1[0]), 0, 0 }, + { "mmTCC_PERFCOUNTER2_SELECT", REG_MMIO, 0x3b84, 1, &mmTCC_PERFCOUNTER2_SELECT[0], sizeof(mmTCC_PERFCOUNTER2_SELECT)/sizeof(mmTCC_PERFCOUNTER2_SELECT[0]), 0, 0 }, + { "mmTCC_PERFCOUNTER3_SELECT", REG_MMIO, 0x3b85, 1, &mmTCC_PERFCOUNTER3_SELECT[0], sizeof(mmTCC_PERFCOUNTER3_SELECT)/sizeof(mmTCC_PERFCOUNTER3_SELECT[0]), 0, 0 }, + { "mmTCA_PERFCOUNTER0_SELECT", REG_MMIO, 0x3b90, 1, &mmTCA_PERFCOUNTER0_SELECT[0], sizeof(mmTCA_PERFCOUNTER0_SELECT)/sizeof(mmTCA_PERFCOUNTER0_SELECT[0]), 0, 0 }, + { "mmTCA_PERFCOUNTER0_SELECT1", REG_MMIO, 0x3b91, 1, &mmTCA_PERFCOUNTER0_SELECT1[0], sizeof(mmTCA_PERFCOUNTER0_SELECT1)/sizeof(mmTCA_PERFCOUNTER0_SELECT1[0]), 0, 0 }, + { "mmTCA_PERFCOUNTER1_SELECT", REG_MMIO, 0x3b92, 1, &mmTCA_PERFCOUNTER1_SELECT[0], sizeof(mmTCA_PERFCOUNTER1_SELECT)/sizeof(mmTCA_PERFCOUNTER1_SELECT[0]), 0, 0 }, + { "mmTCA_PERFCOUNTER1_SELECT1", REG_MMIO, 0x3b93, 1, &mmTCA_PERFCOUNTER1_SELECT1[0], sizeof(mmTCA_PERFCOUNTER1_SELECT1)/sizeof(mmTCA_PERFCOUNTER1_SELECT1[0]), 0, 0 }, + { "mmTCA_PERFCOUNTER2_SELECT", REG_MMIO, 0x3b94, 1, &mmTCA_PERFCOUNTER2_SELECT[0], sizeof(mmTCA_PERFCOUNTER2_SELECT)/sizeof(mmTCA_PERFCOUNTER2_SELECT[0]), 0, 0 }, + { "mmTCA_PERFCOUNTER3_SELECT", REG_MMIO, 0x3b95, 1, &mmTCA_PERFCOUNTER3_SELECT[0], sizeof(mmTCA_PERFCOUNTER3_SELECT)/sizeof(mmTCA_PERFCOUNTER3_SELECT[0]), 0, 0 }, + { "mmCB_PERFCOUNTER_FILTER", REG_MMIO, 0x3c00, 1, &mmCB_PERFCOUNTER_FILTER[0], sizeof(mmCB_PERFCOUNTER_FILTER)/sizeof(mmCB_PERFCOUNTER_FILTER[0]), 0, 0 }, + { "mmCB_PERFCOUNTER0_SELECT", REG_MMIO, 0x3c01, 1, &mmCB_PERFCOUNTER0_SELECT[0], sizeof(mmCB_PERFCOUNTER0_SELECT)/sizeof(mmCB_PERFCOUNTER0_SELECT[0]), 0, 0 }, + { "mmCB_PERFCOUNTER0_SELECT1", REG_MMIO, 0x3c02, 1, &mmCB_PERFCOUNTER0_SELECT1[0], sizeof(mmCB_PERFCOUNTER0_SELECT1)/sizeof(mmCB_PERFCOUNTER0_SELECT1[0]), 0, 0 }, + { "mmCB_PERFCOUNTER1_SELECT", REG_MMIO, 0x3c03, 1, &mmCB_PERFCOUNTER1_SELECT[0], sizeof(mmCB_PERFCOUNTER1_SELECT)/sizeof(mmCB_PERFCOUNTER1_SELECT[0]), 0, 0 }, + { "mmCB_PERFCOUNTER2_SELECT", REG_MMIO, 0x3c04, 1, &mmCB_PERFCOUNTER2_SELECT[0], sizeof(mmCB_PERFCOUNTER2_SELECT)/sizeof(mmCB_PERFCOUNTER2_SELECT[0]), 0, 0 }, + { "mmCB_PERFCOUNTER3_SELECT", REG_MMIO, 0x3c05, 1, &mmCB_PERFCOUNTER3_SELECT[0], sizeof(mmCB_PERFCOUNTER3_SELECT)/sizeof(mmCB_PERFCOUNTER3_SELECT[0]), 0, 0 }, + { "mmDB_PERFCOUNTER0_SELECT", REG_MMIO, 0x3c40, 1, &mmDB_PERFCOUNTER0_SELECT[0], sizeof(mmDB_PERFCOUNTER0_SELECT)/sizeof(mmDB_PERFCOUNTER0_SELECT[0]), 0, 0 }, + { "mmDB_PERFCOUNTER0_SELECT1", REG_MMIO, 0x3c41, 1, &mmDB_PERFCOUNTER0_SELECT1[0], sizeof(mmDB_PERFCOUNTER0_SELECT1)/sizeof(mmDB_PERFCOUNTER0_SELECT1[0]), 0, 0 }, + { "mmDB_PERFCOUNTER1_SELECT", REG_MMIO, 0x3c42, 1, &mmDB_PERFCOUNTER1_SELECT[0], sizeof(mmDB_PERFCOUNTER1_SELECT)/sizeof(mmDB_PERFCOUNTER1_SELECT[0]), 0, 0 }, + { "mmDB_PERFCOUNTER1_SELECT1", REG_MMIO, 0x3c43, 1, &mmDB_PERFCOUNTER1_SELECT1[0], sizeof(mmDB_PERFCOUNTER1_SELECT1)/sizeof(mmDB_PERFCOUNTER1_SELECT1[0]), 0, 0 }, + { "mmDB_PERFCOUNTER2_SELECT", REG_MMIO, 0x3c44, 1, &mmDB_PERFCOUNTER2_SELECT[0], sizeof(mmDB_PERFCOUNTER2_SELECT)/sizeof(mmDB_PERFCOUNTER2_SELECT[0]), 0, 0 }, + { "mmDB_PERFCOUNTER3_SELECT", REG_MMIO, 0x3c46, 1, &mmDB_PERFCOUNTER3_SELECT[0], sizeof(mmDB_PERFCOUNTER3_SELECT)/sizeof(mmDB_PERFCOUNTER3_SELECT[0]), 0, 0 }, + { "mmRLC_SPM_PERFMON_CNTL", REG_MMIO, 0x3c80, 1, &mmRLC_SPM_PERFMON_CNTL[0], sizeof(mmRLC_SPM_PERFMON_CNTL)/sizeof(mmRLC_SPM_PERFMON_CNTL[0]), 0, 0 }, + { "mmRLC_SPM_PERFMON_RING_BASE_LO", REG_MMIO, 0x3c81, 1, &mmRLC_SPM_PERFMON_RING_BASE_LO[0], sizeof(mmRLC_SPM_PERFMON_RING_BASE_LO)/sizeof(mmRLC_SPM_PERFMON_RING_BASE_LO[0]), 0, 0 }, + { "mmRLC_SPM_PERFMON_RING_BASE_HI", REG_MMIO, 0x3c82, 1, &mmRLC_SPM_PERFMON_RING_BASE_HI[0], sizeof(mmRLC_SPM_PERFMON_RING_BASE_HI)/sizeof(mmRLC_SPM_PERFMON_RING_BASE_HI[0]), 0, 0 }, + { "mmRLC_SPM_PERFMON_RING_SIZE", REG_MMIO, 0x3c83, 1, &mmRLC_SPM_PERFMON_RING_SIZE[0], sizeof(mmRLC_SPM_PERFMON_RING_SIZE)/sizeof(mmRLC_SPM_PERFMON_RING_SIZE[0]), 0, 0 }, + { "mmRLC_SPM_PERFMON_SEGMENT_SIZE", REG_MMIO, 0x3c84, 1, &mmRLC_SPM_PERFMON_SEGMENT_SIZE[0], sizeof(mmRLC_SPM_PERFMON_SEGMENT_SIZE)/sizeof(mmRLC_SPM_PERFMON_SEGMENT_SIZE[0]), 0, 0 }, + { "mmRLC_SPM_SE_MUXSEL_ADDR", REG_MMIO, 0x3c85, 1, &mmRLC_SPM_SE_MUXSEL_ADDR[0], sizeof(mmRLC_SPM_SE_MUXSEL_ADDR)/sizeof(mmRLC_SPM_SE_MUXSEL_ADDR[0]), 0, 0 }, + { "mmRLC_SPM_SE_MUXSEL_DATA", REG_MMIO, 0x3c86, 1, &mmRLC_SPM_SE_MUXSEL_DATA[0], sizeof(mmRLC_SPM_SE_MUXSEL_DATA)/sizeof(mmRLC_SPM_SE_MUXSEL_DATA[0]), 0, 0 }, + { "mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY", REG_MMIO, 0x3c87, 1, &mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY[0]), 0, 0 }, + { "mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY", REG_MMIO, 0x3c88, 1, &mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY[0]), 0, 0 }, + { "mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY", REG_MMIO, 0x3c89, 1, &mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY[0]), 0, 0 }, + { "mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY", REG_MMIO, 0x3c8a, 1, &mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY[0]), 0, 0 }, + { "mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY", REG_MMIO, 0x3c8b, 1, &mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY[0]), 0, 0 }, + { "mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY", REG_MMIO, 0x3c8c, 1, &mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY[0]), 0, 0 }, + { "mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY", REG_MMIO, 0x3c8d, 1, &mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY[0]), 0, 0 }, + { "mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY", REG_MMIO, 0x3c8e, 1, &mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY[0]), 0, 0 }, + { "mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY", REG_MMIO, 0x3c90, 1, &mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY[0]), 0, 0 }, + { "mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY", REG_MMIO, 0x3c91, 1, &mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY[0]), 0, 0 }, + { "mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY", REG_MMIO, 0x3c92, 1, &mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY[0]), 0, 0 }, + { "mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY", REG_MMIO, 0x3c93, 1, &mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY[0]), 0, 0 }, + { "mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY", REG_MMIO, 0x3c94, 1, &mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY[0]), 0, 0 }, + { "mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY", REG_MMIO, 0x3c95, 1, &mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY[0]), 0, 0 }, + { "mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY", REG_MMIO, 0x3c96, 1, &mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY[0]), 0, 0 }, + { "mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY", REG_MMIO, 0x3c97, 1, &mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY[0]), 0, 0 }, + { "mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY", REG_MMIO, 0x3c98, 1, &mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY[0]), 0, 0 }, + { "mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY", REG_MMIO, 0x3c9a, 1, &mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY[0]), 0, 0 }, + { "mmRLC_SPM_GLOBAL_MUXSEL_ADDR", REG_MMIO, 0x3c9b, 1, &mmRLC_SPM_GLOBAL_MUXSEL_ADDR[0], sizeof(mmRLC_SPM_GLOBAL_MUXSEL_ADDR)/sizeof(mmRLC_SPM_GLOBAL_MUXSEL_ADDR[0]), 0, 0 }, + { "mmRLC_SPM_GLOBAL_MUXSEL_DATA", REG_MMIO, 0x3c9c, 1, &mmRLC_SPM_GLOBAL_MUXSEL_DATA[0], sizeof(mmRLC_SPM_GLOBAL_MUXSEL_DATA)/sizeof(mmRLC_SPM_GLOBAL_MUXSEL_DATA[0]), 0, 0 }, + { "mmRLC_SPM_RING_RDPTR", REG_MMIO, 0x3c9d, 1, &mmRLC_SPM_RING_RDPTR[0], sizeof(mmRLC_SPM_RING_RDPTR)/sizeof(mmRLC_SPM_RING_RDPTR[0]), 0, 0 }, + { "mmRLC_SPM_SEGMENT_THRESHOLD", REG_MMIO, 0x3c9e, 1, &mmRLC_SPM_SEGMENT_THRESHOLD[0], sizeof(mmRLC_SPM_SEGMENT_THRESHOLD)/sizeof(mmRLC_SPM_SEGMENT_THRESHOLD[0]), 0, 0 }, + { "mmRLC_SPM_RMI_PERFMON_SAMPLE_DELAY", REG_MMIO, 0x3ca3, 1, &mmRLC_SPM_RMI_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_RMI_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_RMI_PERFMON_SAMPLE_DELAY[0]), 0, 0 }, + { "mmRLC_PERFMON_CLK_CNTL", REG_MMIO, 0x3cbf, 1, &mmRLC_PERFMON_CLK_CNTL[0], sizeof(mmRLC_PERFMON_CLK_CNTL)/sizeof(mmRLC_PERFMON_CLK_CNTL[0]), 0, 0 }, + { "mmRLC_PERFMON_CNTL", REG_MMIO, 0x3cc0, 1, &mmRLC_PERFMON_CNTL[0], sizeof(mmRLC_PERFMON_CNTL)/sizeof(mmRLC_PERFMON_CNTL[0]), 0, 0 }, + { "mmRLC_PERFCOUNTER0_SELECT", REG_MMIO, 0x3cc1, 1, &mmRLC_PERFCOUNTER0_SELECT[0], sizeof(mmRLC_PERFCOUNTER0_SELECT)/sizeof(mmRLC_PERFCOUNTER0_SELECT[0]), 0, 0 }, + { "mmRLC_PERFCOUNTER1_SELECT", REG_MMIO, 0x3cc2, 1, &mmRLC_PERFCOUNTER1_SELECT[0], sizeof(mmRLC_PERFCOUNTER1_SELECT)/sizeof(mmRLC_PERFCOUNTER1_SELECT[0]), 0, 0 }, + { "mmRLC_GPU_IOV_PERF_CNT_CNTL", REG_MMIO, 0x3cc3, 1, &mmRLC_GPU_IOV_PERF_CNT_CNTL[0], sizeof(mmRLC_GPU_IOV_PERF_CNT_CNTL)/sizeof(mmRLC_GPU_IOV_PERF_CNT_CNTL[0]), 0, 0 }, + { "mmRLC_GPU_IOV_PERF_CNT_WR_ADDR", REG_MMIO, 0x3cc4, 1, &mmRLC_GPU_IOV_PERF_CNT_WR_ADDR[0], sizeof(mmRLC_GPU_IOV_PERF_CNT_WR_ADDR)/sizeof(mmRLC_GPU_IOV_PERF_CNT_WR_ADDR[0]), 0, 0 }, + { "mmRLC_GPU_IOV_PERF_CNT_WR_DATA", REG_MMIO, 0x3cc5, 1, &mmRLC_GPU_IOV_PERF_CNT_WR_DATA[0], sizeof(mmRLC_GPU_IOV_PERF_CNT_WR_DATA)/sizeof(mmRLC_GPU_IOV_PERF_CNT_WR_DATA[0]), 0, 0 }, + { "mmRLC_GPU_IOV_PERF_CNT_RD_ADDR", REG_MMIO, 0x3cc6, 1, &mmRLC_GPU_IOV_PERF_CNT_RD_ADDR[0], sizeof(mmRLC_GPU_IOV_PERF_CNT_RD_ADDR)/sizeof(mmRLC_GPU_IOV_PERF_CNT_RD_ADDR[0]), 0, 0 }, + { "mmRLC_GPU_IOV_PERF_CNT_RD_DATA", REG_MMIO, 0x3cc7, 1, &mmRLC_GPU_IOV_PERF_CNT_RD_DATA[0], sizeof(mmRLC_GPU_IOV_PERF_CNT_RD_DATA)/sizeof(mmRLC_GPU_IOV_PERF_CNT_RD_DATA[0]), 0, 0 }, + { "mmRMI_PERFCOUNTER0_SELECT", REG_MMIO, 0x3d00, 1, &mmRMI_PERFCOUNTER0_SELECT[0], sizeof(mmRMI_PERFCOUNTER0_SELECT)/sizeof(mmRMI_PERFCOUNTER0_SELECT[0]), 0, 0 }, + { "mmRMI_PERFCOUNTER0_SELECT1", REG_MMIO, 0x3d01, 1, &mmRMI_PERFCOUNTER0_SELECT1[0], sizeof(mmRMI_PERFCOUNTER0_SELECT1)/sizeof(mmRMI_PERFCOUNTER0_SELECT1[0]), 0, 0 }, + { "mmRMI_PERFCOUNTER1_SELECT", REG_MMIO, 0x3d02, 1, &mmRMI_PERFCOUNTER1_SELECT[0], sizeof(mmRMI_PERFCOUNTER1_SELECT)/sizeof(mmRMI_PERFCOUNTER1_SELECT[0]), 0, 0 }, + { "mmRMI_PERFCOUNTER2_SELECT", REG_MMIO, 0x3d03, 1, &mmRMI_PERFCOUNTER2_SELECT[0], sizeof(mmRMI_PERFCOUNTER2_SELECT)/sizeof(mmRMI_PERFCOUNTER2_SELECT[0]), 0, 0 }, + { "mmRMI_PERFCOUNTER2_SELECT1", REG_MMIO, 0x3d04, 1, &mmRMI_PERFCOUNTER2_SELECT1[0], sizeof(mmRMI_PERFCOUNTER2_SELECT1)/sizeof(mmRMI_PERFCOUNTER2_SELECT1[0]), 0, 0 }, + { "mmRMI_PERFCOUNTER3_SELECT", REG_MMIO, 0x3d05, 1, &mmRMI_PERFCOUNTER3_SELECT[0], sizeof(mmRMI_PERFCOUNTER3_SELECT)/sizeof(mmRMI_PERFCOUNTER3_SELECT[0]), 0, 0 }, + { "mmRMI_PERF_COUNTER_CNTL", REG_MMIO, 0x3d06, 1, &mmRMI_PERF_COUNTER_CNTL[0], sizeof(mmRMI_PERF_COUNTER_CNTL)/sizeof(mmRMI_PERF_COUNTER_CNTL[0]), 0, 0 }, + { "mmATC_L2_PERFCOUNTER0_CFG", REG_MMIO, 0x3d40, 1, &mmATC_L2_PERFCOUNTER0_CFG[0], sizeof(mmATC_L2_PERFCOUNTER0_CFG)/sizeof(mmATC_L2_PERFCOUNTER0_CFG[0]), 0, 0 }, + { "mmATC_L2_PERFCOUNTER1_CFG", REG_MMIO, 0x3d41, 1, &mmATC_L2_PERFCOUNTER1_CFG[0], sizeof(mmATC_L2_PERFCOUNTER1_CFG)/sizeof(mmATC_L2_PERFCOUNTER1_CFG[0]), 0, 0 }, + { "mmATC_L2_PERFCOUNTER_RSLT_CNTL", REG_MMIO, 0x3d42, 1, &mmATC_L2_PERFCOUNTER_RSLT_CNTL[0], sizeof(mmATC_L2_PERFCOUNTER_RSLT_CNTL)/sizeof(mmATC_L2_PERFCOUNTER_RSLT_CNTL[0]), 0, 0 }, + { "mmMC_VM_L2_PERFCOUNTER0_CFG", REG_MMIO, 0x3d4c, 1, &mmMC_VM_L2_PERFCOUNTER0_CFG[0], sizeof(mmMC_VM_L2_PERFCOUNTER0_CFG)/sizeof(mmMC_VM_L2_PERFCOUNTER0_CFG[0]), 0, 0 }, + { "mmMC_VM_L2_PERFCOUNTER1_CFG", REG_MMIO, 0x3d4d, 1, &mmMC_VM_L2_PERFCOUNTER1_CFG[0], sizeof(mmMC_VM_L2_PERFCOUNTER1_CFG)/sizeof(mmMC_VM_L2_PERFCOUNTER1_CFG[0]), 0, 0 }, + { "mmMC_VM_L2_PERFCOUNTER2_CFG", REG_MMIO, 0x3d4e, 1, &mmMC_VM_L2_PERFCOUNTER2_CFG[0], sizeof(mmMC_VM_L2_PERFCOUNTER2_CFG)/sizeof(mmMC_VM_L2_PERFCOUNTER2_CFG[0]), 0, 0 }, + { "mmMC_VM_L2_PERFCOUNTER3_CFG", REG_MMIO, 0x3d4f, 1, &mmMC_VM_L2_PERFCOUNTER3_CFG[0], sizeof(mmMC_VM_L2_PERFCOUNTER3_CFG)/sizeof(mmMC_VM_L2_PERFCOUNTER3_CFG[0]), 0, 0 }, + { "mmMC_VM_L2_PERFCOUNTER4_CFG", REG_MMIO, 0x3d50, 1, &mmMC_VM_L2_PERFCOUNTER4_CFG[0], sizeof(mmMC_VM_L2_PERFCOUNTER4_CFG)/sizeof(mmMC_VM_L2_PERFCOUNTER4_CFG[0]), 0, 0 }, + { "mmMC_VM_L2_PERFCOUNTER5_CFG", REG_MMIO, 0x3d51, 1, &mmMC_VM_L2_PERFCOUNTER5_CFG[0], sizeof(mmMC_VM_L2_PERFCOUNTER5_CFG)/sizeof(mmMC_VM_L2_PERFCOUNTER5_CFG[0]), 0, 0 }, + { "mmMC_VM_L2_PERFCOUNTER6_CFG", REG_MMIO, 0x3d52, 1, &mmMC_VM_L2_PERFCOUNTER6_CFG[0], sizeof(mmMC_VM_L2_PERFCOUNTER6_CFG)/sizeof(mmMC_VM_L2_PERFCOUNTER6_CFG[0]), 0, 0 }, + { "mmMC_VM_L2_PERFCOUNTER7_CFG", REG_MMIO, 0x3d53, 1, &mmMC_VM_L2_PERFCOUNTER7_CFG[0], sizeof(mmMC_VM_L2_PERFCOUNTER7_CFG)/sizeof(mmMC_VM_L2_PERFCOUNTER7_CFG[0]), 0, 0 }, + { "mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL", REG_MMIO, 0x3d54, 1, &mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL[0], sizeof(mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL)/sizeof(mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL[0]), 0, 0 }, + { "mmRLC_CNTL", REG_MMIO, 0x4c00, 1, &mmRLC_CNTL[0], sizeof(mmRLC_CNTL)/sizeof(mmRLC_CNTL[0]), 0, 0 }, + { "mmRLC_STAT", REG_MMIO, 0x4c04, 1, &mmRLC_STAT[0], sizeof(mmRLC_STAT)/sizeof(mmRLC_STAT[0]), 0, 0 }, + { "mmRLC_SAFE_MODE", REG_MMIO, 0x4c05, 1, &mmRLC_SAFE_MODE[0], sizeof(mmRLC_SAFE_MODE)/sizeof(mmRLC_SAFE_MODE[0]), 0, 0 }, + { "mmRLC_MEM_SLP_CNTL", REG_MMIO, 0x4c06, 1, &mmRLC_MEM_SLP_CNTL[0], sizeof(mmRLC_MEM_SLP_CNTL)/sizeof(mmRLC_MEM_SLP_CNTL[0]), 0, 0 }, + { "mmSMU_RLC_RESPONSE", REG_MMIO, 0x4c07, 1, &mmSMU_RLC_RESPONSE[0], sizeof(mmSMU_RLC_RESPONSE)/sizeof(mmSMU_RLC_RESPONSE[0]), 0, 0 }, + { "mmRLC_RLCV_SAFE_MODE", REG_MMIO, 0x4c08, 1, &mmRLC_RLCV_SAFE_MODE[0], sizeof(mmRLC_RLCV_SAFE_MODE)/sizeof(mmRLC_RLCV_SAFE_MODE[0]), 0, 0 }, + { "mmRLC_SMU_SAFE_MODE", REG_MMIO, 0x4c09, 1, &mmRLC_SMU_SAFE_MODE[0], sizeof(mmRLC_SMU_SAFE_MODE)/sizeof(mmRLC_SMU_SAFE_MODE[0]), 0, 0 }, + { "mmRLC_RLCV_COMMAND", REG_MMIO, 0x4c0a, 1, &mmRLC_RLCV_COMMAND[0], sizeof(mmRLC_RLCV_COMMAND)/sizeof(mmRLC_RLCV_COMMAND[0]), 0, 0 }, + { "mmRLC_REFCLOCK_TIMESTAMP_LSB", REG_MMIO, 0x4c0c, 1, &mmRLC_REFCLOCK_TIMESTAMP_LSB[0], sizeof(mmRLC_REFCLOCK_TIMESTAMP_LSB)/sizeof(mmRLC_REFCLOCK_TIMESTAMP_LSB[0]), 0, 0 }, + { "mmRLC_REFCLOCK_TIMESTAMP_MSB", REG_MMIO, 0x4c0d, 1, &mmRLC_REFCLOCK_TIMESTAMP_MSB[0], sizeof(mmRLC_REFCLOCK_TIMESTAMP_MSB)/sizeof(mmRLC_REFCLOCK_TIMESTAMP_MSB[0]), 0, 0 }, + { "mmRLC_GPM_TIMER_INT_0", REG_MMIO, 0x4c0e, 1, &mmRLC_GPM_TIMER_INT_0[0], sizeof(mmRLC_GPM_TIMER_INT_0)/sizeof(mmRLC_GPM_TIMER_INT_0[0]), 0, 0 }, + { "mmRLC_GPM_TIMER_INT_1", REG_MMIO, 0x4c0f, 1, &mmRLC_GPM_TIMER_INT_1[0], sizeof(mmRLC_GPM_TIMER_INT_1)/sizeof(mmRLC_GPM_TIMER_INT_1[0]), 0, 0 }, + { "mmRLC_GPM_TIMER_INT_2", REG_MMIO, 0x4c10, 1, &mmRLC_GPM_TIMER_INT_2[0], sizeof(mmRLC_GPM_TIMER_INT_2)/sizeof(mmRLC_GPM_TIMER_INT_2[0]), 0, 0 }, + { "mmRLC_GPM_TIMER_CTRL", REG_MMIO, 0x4c11, 1, &mmRLC_GPM_TIMER_CTRL[0], sizeof(mmRLC_GPM_TIMER_CTRL)/sizeof(mmRLC_GPM_TIMER_CTRL[0]), 0, 0 }, + { "mmRLC_LB_CNTR_MAX", REG_MMIO, 0x4c12, 1, &mmRLC_LB_CNTR_MAX[0], sizeof(mmRLC_LB_CNTR_MAX)/sizeof(mmRLC_LB_CNTR_MAX[0]), 0, 0 }, + { "mmRLC_GPM_TIMER_STAT", REG_MMIO, 0x4c13, 1, &mmRLC_GPM_TIMER_STAT[0], sizeof(mmRLC_GPM_TIMER_STAT)/sizeof(mmRLC_GPM_TIMER_STAT[0]), 0, 0 }, + { "mmRLC_GPM_TIMER_INT_3", REG_MMIO, 0x4c15, 1, &mmRLC_GPM_TIMER_INT_3[0], sizeof(mmRLC_GPM_TIMER_INT_3)/sizeof(mmRLC_GPM_TIMER_INT_3[0]), 0, 0 }, + { "mmRLC_SERDES_WR_NONCU_MASTER_MASK_1", REG_MMIO, 0x4c16, 1, &mmRLC_SERDES_WR_NONCU_MASTER_MASK_1[0], sizeof(mmRLC_SERDES_WR_NONCU_MASTER_MASK_1)/sizeof(mmRLC_SERDES_WR_NONCU_MASTER_MASK_1[0]), 0, 0 }, + { "mmRLC_SERDES_NONCU_MASTER_BUSY_1", REG_MMIO, 0x4c17, 1, &mmRLC_SERDES_NONCU_MASTER_BUSY_1[0], sizeof(mmRLC_SERDES_NONCU_MASTER_BUSY_1)/sizeof(mmRLC_SERDES_NONCU_MASTER_BUSY_1[0]), 0, 0 }, + { "mmRLC_INT_STAT", REG_MMIO, 0x4c18, 1, &mmRLC_INT_STAT[0], sizeof(mmRLC_INT_STAT)/sizeof(mmRLC_INT_STAT[0]), 0, 0 }, + { "mmRLC_LB_CNTL", REG_MMIO, 0x4c19, 1, &mmRLC_LB_CNTL[0], sizeof(mmRLC_LB_CNTL)/sizeof(mmRLC_LB_CNTL[0]), 0, 0 }, + { "mmRLC_MGCG_CTRL", REG_MMIO, 0x4c1a, 1, &mmRLC_MGCG_CTRL[0], sizeof(mmRLC_MGCG_CTRL)/sizeof(mmRLC_MGCG_CTRL[0]), 0, 0 }, + { "mmRLC_LB_CNTR_INIT", REG_MMIO, 0x4c1b, 1, &mmRLC_LB_CNTR_INIT[0], sizeof(mmRLC_LB_CNTR_INIT)/sizeof(mmRLC_LB_CNTR_INIT[0]), 0, 0 }, + { "mmRLC_LOAD_BALANCE_CNTR", REG_MMIO, 0x4c1c, 1, &mmRLC_LOAD_BALANCE_CNTR[0], sizeof(mmRLC_LOAD_BALANCE_CNTR)/sizeof(mmRLC_LOAD_BALANCE_CNTR[0]), 0, 0 }, + { "mmRLC_JUMP_TABLE_RESTORE", REG_MMIO, 0x4c1e, 1, &mmRLC_JUMP_TABLE_RESTORE[0], sizeof(mmRLC_JUMP_TABLE_RESTORE)/sizeof(mmRLC_JUMP_TABLE_RESTORE[0]), 0, 0 }, + { "mmRLC_PG_DELAY_2", REG_MMIO, 0x4c1f, 1, &mmRLC_PG_DELAY_2[0], sizeof(mmRLC_PG_DELAY_2)/sizeof(mmRLC_PG_DELAY_2[0]), 0, 0 }, + { "mmRLC_GPU_CLOCK_COUNT_LSB", REG_MMIO, 0x4c24, 1, &mmRLC_GPU_CLOCK_COUNT_LSB[0], sizeof(mmRLC_GPU_CLOCK_COUNT_LSB)/sizeof(mmRLC_GPU_CLOCK_COUNT_LSB[0]), 0, 0 }, + { "mmRLC_GPU_CLOCK_COUNT_MSB", REG_MMIO, 0x4c25, 1, &mmRLC_GPU_CLOCK_COUNT_MSB[0], sizeof(mmRLC_GPU_CLOCK_COUNT_MSB)/sizeof(mmRLC_GPU_CLOCK_COUNT_MSB[0]), 0, 0 }, + { "mmRLC_CAPTURE_GPU_CLOCK_COUNT", REG_MMIO, 0x4c26, 1, &mmRLC_CAPTURE_GPU_CLOCK_COUNT[0], sizeof(mmRLC_CAPTURE_GPU_CLOCK_COUNT)/sizeof(mmRLC_CAPTURE_GPU_CLOCK_COUNT[0]), 0, 0 }, + { "mmRLC_UCODE_CNTL", REG_MMIO, 0x4c27, 1, &mmRLC_UCODE_CNTL[0], sizeof(mmRLC_UCODE_CNTL)/sizeof(mmRLC_UCODE_CNTL[0]), 0, 0 }, + { "mmRLC_GPM_THREAD_RESET", REG_MMIO, 0x4c28, 1, &mmRLC_GPM_THREAD_RESET[0], sizeof(mmRLC_GPM_THREAD_RESET)/sizeof(mmRLC_GPM_THREAD_RESET[0]), 0, 0 }, + { "mmRLC_GPM_CP_DMA_COMPLETE_T0", REG_MMIO, 0x4c29, 1, &mmRLC_GPM_CP_DMA_COMPLETE_T0[0], sizeof(mmRLC_GPM_CP_DMA_COMPLETE_T0)/sizeof(mmRLC_GPM_CP_DMA_COMPLETE_T0[0]), 0, 0 }, + { "mmRLC_GPM_CP_DMA_COMPLETE_T1", REG_MMIO, 0x4c2a, 1, &mmRLC_GPM_CP_DMA_COMPLETE_T1[0], sizeof(mmRLC_GPM_CP_DMA_COMPLETE_T1)/sizeof(mmRLC_GPM_CP_DMA_COMPLETE_T1[0]), 0, 0 }, + { "mmRLC_FIREWALL_VIOLATION", REG_MMIO, 0x4c2b, 1, &mmRLC_FIREWALL_VIOLATION[0], sizeof(mmRLC_FIREWALL_VIOLATION)/sizeof(mmRLC_FIREWALL_VIOLATION[0]), 0, 0 }, + { "mmRLC_GPM_STAT", REG_MMIO, 0x4c40, 1, &mmRLC_GPM_STAT[0], sizeof(mmRLC_GPM_STAT)/sizeof(mmRLC_GPM_STAT[0]), 0, 0 }, + { "mmRLC_GPU_CLOCK_32_RES_SEL", REG_MMIO, 0x4c41, 1, &mmRLC_GPU_CLOCK_32_RES_SEL[0], sizeof(mmRLC_GPU_CLOCK_32_RES_SEL)/sizeof(mmRLC_GPU_CLOCK_32_RES_SEL[0]), 0, 0 }, + { "mmRLC_GPU_CLOCK_32", REG_MMIO, 0x4c42, 1, &mmRLC_GPU_CLOCK_32[0], sizeof(mmRLC_GPU_CLOCK_32)/sizeof(mmRLC_GPU_CLOCK_32[0]), 0, 0 }, + { "mmRLC_PG_CNTL", REG_MMIO, 0x4c43, 1, &mmRLC_PG_CNTL[0], sizeof(mmRLC_PG_CNTL)/sizeof(mmRLC_PG_CNTL[0]), 0, 0 }, + { "mmRLC_GPM_THREAD_PRIORITY", REG_MMIO, 0x4c44, 1, &mmRLC_GPM_THREAD_PRIORITY[0], sizeof(mmRLC_GPM_THREAD_PRIORITY)/sizeof(mmRLC_GPM_THREAD_PRIORITY[0]), 0, 0 }, + { "mmRLC_GPM_THREAD_ENABLE", REG_MMIO, 0x4c45, 1, &mmRLC_GPM_THREAD_ENABLE[0], sizeof(mmRLC_GPM_THREAD_ENABLE)/sizeof(mmRLC_GPM_THREAD_ENABLE[0]), 0, 0 }, + { "mmRLC_CGTT_MGCG_OVERRIDE", REG_MMIO, 0x4c48, 1, &mmRLC_CGTT_MGCG_OVERRIDE[0], sizeof(mmRLC_CGTT_MGCG_OVERRIDE)/sizeof(mmRLC_CGTT_MGCG_OVERRIDE[0]), 0, 0 }, + { "mmRLC_CGCG_CGLS_CTRL", REG_MMIO, 0x4c49, 1, &mmRLC_CGCG_CGLS_CTRL[0], sizeof(mmRLC_CGCG_CGLS_CTRL)/sizeof(mmRLC_CGCG_CGLS_CTRL[0]), 0, 0 }, + { "mmRLC_CGCG_RAMP_CTRL", REG_MMIO, 0x4c4a, 1, &mmRLC_CGCG_RAMP_CTRL[0], sizeof(mmRLC_CGCG_RAMP_CTRL)/sizeof(mmRLC_CGCG_RAMP_CTRL[0]), 0, 0 }, + { "mmRLC_DYN_PG_STATUS", REG_MMIO, 0x4c4b, 1, &mmRLC_DYN_PG_STATUS[0], sizeof(mmRLC_DYN_PG_STATUS)/sizeof(mmRLC_DYN_PG_STATUS[0]), 0, 0 }, + { "mmRLC_DYN_PG_REQUEST", REG_MMIO, 0x4c4c, 1, &mmRLC_DYN_PG_REQUEST[0], sizeof(mmRLC_DYN_PG_REQUEST)/sizeof(mmRLC_DYN_PG_REQUEST[0]), 0, 0 }, + { "mmRLC_PG_DELAY", REG_MMIO, 0x4c4d, 1, &mmRLC_PG_DELAY[0], sizeof(mmRLC_PG_DELAY)/sizeof(mmRLC_PG_DELAY[0]), 0, 0 }, + { "mmRLC_CU_STATUS", REG_MMIO, 0x4c4e, 1, &mmRLC_CU_STATUS[0], sizeof(mmRLC_CU_STATUS)/sizeof(mmRLC_CU_STATUS[0]), 0, 0 }, + { "mmRLC_LB_INIT_CU_MASK", REG_MMIO, 0x4c4f, 1, &mmRLC_LB_INIT_CU_MASK[0], sizeof(mmRLC_LB_INIT_CU_MASK)/sizeof(mmRLC_LB_INIT_CU_MASK[0]), 0, 0 }, + { "mmRLC_LB_ALWAYS_ACTIVE_CU_MASK", REG_MMIO, 0x4c50, 1, &mmRLC_LB_ALWAYS_ACTIVE_CU_MASK[0], sizeof(mmRLC_LB_ALWAYS_ACTIVE_CU_MASK)/sizeof(mmRLC_LB_ALWAYS_ACTIVE_CU_MASK[0]), 0, 0 }, + { "mmRLC_LB_PARAMS", REG_MMIO, 0x4c51, 1, &mmRLC_LB_PARAMS[0], sizeof(mmRLC_LB_PARAMS)/sizeof(mmRLC_LB_PARAMS[0]), 0, 0 }, + { "mmRLC_THREAD1_DELAY", REG_MMIO, 0x4c52, 1, &mmRLC_THREAD1_DELAY[0], sizeof(mmRLC_THREAD1_DELAY)/sizeof(mmRLC_THREAD1_DELAY[0]), 0, 0 }, + { "mmRLC_PG_ALWAYS_ON_CU_MASK", REG_MMIO, 0x4c53, 1, &mmRLC_PG_ALWAYS_ON_CU_MASK[0], sizeof(mmRLC_PG_ALWAYS_ON_CU_MASK)/sizeof(mmRLC_PG_ALWAYS_ON_CU_MASK[0]), 0, 0 }, + { "mmRLC_MAX_PG_CU", REG_MMIO, 0x4c54, 1, &mmRLC_MAX_PG_CU[0], sizeof(mmRLC_MAX_PG_CU)/sizeof(mmRLC_MAX_PG_CU[0]), 0, 0 }, + { "mmRLC_AUTO_PG_CTRL", REG_MMIO, 0x4c55, 1, &mmRLC_AUTO_PG_CTRL[0], sizeof(mmRLC_AUTO_PG_CTRL)/sizeof(mmRLC_AUTO_PG_CTRL[0]), 0, 0 }, + { "mmRLC_SMU_GRBM_REG_SAVE_CTRL", REG_MMIO, 0x4c56, 1, &mmRLC_SMU_GRBM_REG_SAVE_CTRL[0], sizeof(mmRLC_SMU_GRBM_REG_SAVE_CTRL)/sizeof(mmRLC_SMU_GRBM_REG_SAVE_CTRL[0]), 0, 0 }, + { "mmRLC_SERDES_RD_MASTER_INDEX", REG_MMIO, 0x4c59, 1, &mmRLC_SERDES_RD_MASTER_INDEX[0], sizeof(mmRLC_SERDES_RD_MASTER_INDEX)/sizeof(mmRLC_SERDES_RD_MASTER_INDEX[0]), 0, 0 }, + { "mmRLC_SERDES_RD_DATA_0", REG_MMIO, 0x4c5a, 1, &mmRLC_SERDES_RD_DATA_0[0], sizeof(mmRLC_SERDES_RD_DATA_0)/sizeof(mmRLC_SERDES_RD_DATA_0[0]), 0, 0 }, + { "mmRLC_SERDES_RD_DATA_1", REG_MMIO, 0x4c5b, 1, &mmRLC_SERDES_RD_DATA_1[0], sizeof(mmRLC_SERDES_RD_DATA_1)/sizeof(mmRLC_SERDES_RD_DATA_1[0]), 0, 0 }, + { "mmRLC_SERDES_RD_DATA_2", REG_MMIO, 0x4c5c, 1, &mmRLC_SERDES_RD_DATA_2[0], sizeof(mmRLC_SERDES_RD_DATA_2)/sizeof(mmRLC_SERDES_RD_DATA_2[0]), 0, 0 }, + { "mmRLC_SERDES_WR_CU_MASTER_MASK", REG_MMIO, 0x4c5d, 1, &mmRLC_SERDES_WR_CU_MASTER_MASK[0], sizeof(mmRLC_SERDES_WR_CU_MASTER_MASK)/sizeof(mmRLC_SERDES_WR_CU_MASTER_MASK[0]), 0, 0 }, + { "mmRLC_SERDES_WR_NONCU_MASTER_MASK", REG_MMIO, 0x4c5e, 1, &mmRLC_SERDES_WR_NONCU_MASTER_MASK[0], sizeof(mmRLC_SERDES_WR_NONCU_MASTER_MASK)/sizeof(mmRLC_SERDES_WR_NONCU_MASTER_MASK[0]), 0, 0 }, + { "mmRLC_SERDES_WR_CTRL", REG_MMIO, 0x4c5f, 1, &mmRLC_SERDES_WR_CTRL[0], sizeof(mmRLC_SERDES_WR_CTRL)/sizeof(mmRLC_SERDES_WR_CTRL[0]), 0, 0 }, + { "mmRLC_SERDES_WR_DATA", REG_MMIO, 0x4c60, 1, &mmRLC_SERDES_WR_DATA[0], sizeof(mmRLC_SERDES_WR_DATA)/sizeof(mmRLC_SERDES_WR_DATA[0]), 0, 0 }, + { "mmRLC_SERDES_CU_MASTER_BUSY", REG_MMIO, 0x4c61, 1, &mmRLC_SERDES_CU_MASTER_BUSY[0], sizeof(mmRLC_SERDES_CU_MASTER_BUSY)/sizeof(mmRLC_SERDES_CU_MASTER_BUSY[0]), 0, 0 }, + { "mmRLC_SERDES_NONCU_MASTER_BUSY", REG_MMIO, 0x4c62, 1, &mmRLC_SERDES_NONCU_MASTER_BUSY[0], sizeof(mmRLC_SERDES_NONCU_MASTER_BUSY)/sizeof(mmRLC_SERDES_NONCU_MASTER_BUSY[0]), 0, 0 }, + { "mmRLC_GPM_GENERAL_0", REG_MMIO, 0x4c63, 1, &mmRLC_GPM_GENERAL_0[0], sizeof(mmRLC_GPM_GENERAL_0)/sizeof(mmRLC_GPM_GENERAL_0[0]), 0, 0 }, + { "mmRLC_GPM_GENERAL_1", REG_MMIO, 0x4c64, 1, &mmRLC_GPM_GENERAL_1[0], sizeof(mmRLC_GPM_GENERAL_1)/sizeof(mmRLC_GPM_GENERAL_1[0]), 0, 0 }, + { "mmRLC_GPM_GENERAL_2", REG_MMIO, 0x4c65, 1, &mmRLC_GPM_GENERAL_2[0], sizeof(mmRLC_GPM_GENERAL_2)/sizeof(mmRLC_GPM_GENERAL_2[0]), 0, 0 }, + { "mmRLC_GPM_GENERAL_3", REG_MMIO, 0x4c66, 1, &mmRLC_GPM_GENERAL_3[0], sizeof(mmRLC_GPM_GENERAL_3)/sizeof(mmRLC_GPM_GENERAL_3[0]), 0, 0 }, + { "mmRLC_GPM_GENERAL_4", REG_MMIO, 0x4c67, 1, &mmRLC_GPM_GENERAL_4[0], sizeof(mmRLC_GPM_GENERAL_4)/sizeof(mmRLC_GPM_GENERAL_4[0]), 0, 0 }, + { "mmRLC_GPM_GENERAL_5", REG_MMIO, 0x4c68, 1, &mmRLC_GPM_GENERAL_5[0], sizeof(mmRLC_GPM_GENERAL_5)/sizeof(mmRLC_GPM_GENERAL_5[0]), 0, 0 }, + { "mmRLC_GPM_GENERAL_6", REG_MMIO, 0x4c69, 1, &mmRLC_GPM_GENERAL_6[0], sizeof(mmRLC_GPM_GENERAL_6)/sizeof(mmRLC_GPM_GENERAL_6[0]), 0, 0 }, + { "mmRLC_GPM_GENERAL_7", REG_MMIO, 0x4c6a, 1, &mmRLC_GPM_GENERAL_7[0], sizeof(mmRLC_GPM_GENERAL_7)/sizeof(mmRLC_GPM_GENERAL_7[0]), 0, 0 }, + { "mmRLC_GPM_SCRATCH_ADDR", REG_MMIO, 0x4c6c, 1, &mmRLC_GPM_SCRATCH_ADDR[0], sizeof(mmRLC_GPM_SCRATCH_ADDR)/sizeof(mmRLC_GPM_SCRATCH_ADDR[0]), 0, 0 }, + { "mmRLC_GPM_SCRATCH_DATA", REG_MMIO, 0x4c6d, 1, &mmRLC_GPM_SCRATCH_DATA[0], sizeof(mmRLC_GPM_SCRATCH_DATA)/sizeof(mmRLC_GPM_SCRATCH_DATA[0]), 0, 0 }, + { "mmRLC_STATIC_PG_STATUS", REG_MMIO, 0x4c6e, 1, &mmRLC_STATIC_PG_STATUS[0], sizeof(mmRLC_STATIC_PG_STATUS)/sizeof(mmRLC_STATIC_PG_STATUS[0]), 0, 0 }, + { "mmRLC_SPM_MC_CNTL", REG_MMIO, 0x4c71, 1, &mmRLC_SPM_MC_CNTL[0], sizeof(mmRLC_SPM_MC_CNTL)/sizeof(mmRLC_SPM_MC_CNTL[0]), 0, 0 }, + { "mmRLC_SPM_INT_CNTL", REG_MMIO, 0x4c72, 1, &mmRLC_SPM_INT_CNTL[0], sizeof(mmRLC_SPM_INT_CNTL)/sizeof(mmRLC_SPM_INT_CNTL[0]), 0, 0 }, + { "mmRLC_SPM_INT_STATUS", REG_MMIO, 0x4c73, 1, &mmRLC_SPM_INT_STATUS[0], sizeof(mmRLC_SPM_INT_STATUS)/sizeof(mmRLC_SPM_INT_STATUS[0]), 0, 0 }, + { "mmRLC_SMU_MESSAGE", REG_MMIO, 0x4c76, 1, &mmRLC_SMU_MESSAGE[0], sizeof(mmRLC_SMU_MESSAGE)/sizeof(mmRLC_SMU_MESSAGE[0]), 0, 0 }, + { "mmRLC_GPM_LOG_SIZE", REG_MMIO, 0x4c77, 1, &mmRLC_GPM_LOG_SIZE[0], sizeof(mmRLC_GPM_LOG_SIZE)/sizeof(mmRLC_GPM_LOG_SIZE[0]), 0, 0 }, + { "mmRLC_PG_DELAY_3", REG_MMIO, 0x4c78, 1, &mmRLC_PG_DELAY_3[0], sizeof(mmRLC_PG_DELAY_3)/sizeof(mmRLC_PG_DELAY_3[0]), 0, 0 }, + { "mmRLC_GPR_REG1", REG_MMIO, 0x4c79, 1, &mmRLC_GPR_REG1[0], sizeof(mmRLC_GPR_REG1)/sizeof(mmRLC_GPR_REG1[0]), 0, 0 }, + { "mmRLC_GPR_REG2", REG_MMIO, 0x4c7a, 1, &mmRLC_GPR_REG2[0], sizeof(mmRLC_GPR_REG2)/sizeof(mmRLC_GPR_REG2[0]), 0, 0 }, + { "mmRLC_GPM_LOG_CONT", REG_MMIO, 0x4c7b, 1, &mmRLC_GPM_LOG_CONT[0], sizeof(mmRLC_GPM_LOG_CONT)/sizeof(mmRLC_GPM_LOG_CONT[0]), 0, 0 }, + { "mmRLC_GPM_INT_DISABLE_TH0", REG_MMIO, 0x4c7c, 1, &mmRLC_GPM_INT_DISABLE_TH0[0], sizeof(mmRLC_GPM_INT_DISABLE_TH0)/sizeof(mmRLC_GPM_INT_DISABLE_TH0[0]), 0, 0 }, + { "mmRLC_GPM_INT_DISABLE_TH1", REG_MMIO, 0x4c7d, 1, &mmRLC_GPM_INT_DISABLE_TH1[0], sizeof(mmRLC_GPM_INT_DISABLE_TH1)/sizeof(mmRLC_GPM_INT_DISABLE_TH1[0]), 0, 0 }, + { "mmRLC_GPM_INT_FORCE_TH0", REG_MMIO, 0x4c7e, 1, &mmRLC_GPM_INT_FORCE_TH0[0], sizeof(mmRLC_GPM_INT_FORCE_TH0)/sizeof(mmRLC_GPM_INT_FORCE_TH0[0]), 0, 0 }, + { "mmRLC_GPM_INT_FORCE_TH1", REG_MMIO, 0x4c7f, 1, &mmRLC_GPM_INT_FORCE_TH1[0], sizeof(mmRLC_GPM_INT_FORCE_TH1)/sizeof(mmRLC_GPM_INT_FORCE_TH1[0]), 0, 0 }, + { "mmRLC_SRM_CNTL", REG_MMIO, 0x4c80, 1, &mmRLC_SRM_CNTL[0], sizeof(mmRLC_SRM_CNTL)/sizeof(mmRLC_SRM_CNTL[0]), 0, 0 }, + { "mmRLC_SRM_ARAM_ADDR", REG_MMIO, 0x4c83, 1, &mmRLC_SRM_ARAM_ADDR[0], sizeof(mmRLC_SRM_ARAM_ADDR)/sizeof(mmRLC_SRM_ARAM_ADDR[0]), 0, 0 }, + { "mmRLC_SRM_ARAM_DATA", REG_MMIO, 0x4c84, 1, &mmRLC_SRM_ARAM_DATA[0], sizeof(mmRLC_SRM_ARAM_DATA)/sizeof(mmRLC_SRM_ARAM_DATA[0]), 0, 0 }, + { "mmRLC_SRM_DRAM_ADDR", REG_MMIO, 0x4c85, 1, &mmRLC_SRM_DRAM_ADDR[0], sizeof(mmRLC_SRM_DRAM_ADDR)/sizeof(mmRLC_SRM_DRAM_ADDR[0]), 0, 0 }, + { "mmRLC_SRM_DRAM_DATA", REG_MMIO, 0x4c86, 1, &mmRLC_SRM_DRAM_DATA[0], sizeof(mmRLC_SRM_DRAM_DATA)/sizeof(mmRLC_SRM_DRAM_DATA[0]), 0, 0 }, + { "mmRLC_SRM_GPM_COMMAND", REG_MMIO, 0x4c87, 1, &mmRLC_SRM_GPM_COMMAND[0], sizeof(mmRLC_SRM_GPM_COMMAND)/sizeof(mmRLC_SRM_GPM_COMMAND[0]), 0, 0 }, + { "mmRLC_SRM_GPM_COMMAND_STATUS", REG_MMIO, 0x4c88, 1, &mmRLC_SRM_GPM_COMMAND_STATUS[0], sizeof(mmRLC_SRM_GPM_COMMAND_STATUS)/sizeof(mmRLC_SRM_GPM_COMMAND_STATUS[0]), 0, 0 }, + { "mmRLC_SRM_RLCV_COMMAND", REG_MMIO, 0x4c89, 1, &mmRLC_SRM_RLCV_COMMAND[0], sizeof(mmRLC_SRM_RLCV_COMMAND)/sizeof(mmRLC_SRM_RLCV_COMMAND[0]), 0, 0 }, + { "mmRLC_SRM_RLCV_COMMAND_STATUS", REG_MMIO, 0x4c8a, 1, &mmRLC_SRM_RLCV_COMMAND_STATUS[0], sizeof(mmRLC_SRM_RLCV_COMMAND_STATUS)/sizeof(mmRLC_SRM_RLCV_COMMAND_STATUS[0]), 0, 0 }, + { "mmRLC_SRM_INDEX_CNTL_ADDR_0", REG_MMIO, 0x4c8b, 1, &mmRLC_SRM_INDEX_CNTL_ADDR_0[0], sizeof(mmRLC_SRM_INDEX_CNTL_ADDR_0)/sizeof(mmRLC_SRM_INDEX_CNTL_ADDR_0[0]), 0, 0 }, + { "mmRLC_SRM_INDEX_CNTL_ADDR_1", REG_MMIO, 0x4c8c, 1, &mmRLC_SRM_INDEX_CNTL_ADDR_1[0], sizeof(mmRLC_SRM_INDEX_CNTL_ADDR_1)/sizeof(mmRLC_SRM_INDEX_CNTL_ADDR_1[0]), 0, 0 }, + { "mmRLC_SRM_INDEX_CNTL_ADDR_2", REG_MMIO, 0x4c8d, 1, &mmRLC_SRM_INDEX_CNTL_ADDR_2[0], sizeof(mmRLC_SRM_INDEX_CNTL_ADDR_2)/sizeof(mmRLC_SRM_INDEX_CNTL_ADDR_2[0]), 0, 0 }, + { "mmRLC_SRM_INDEX_CNTL_ADDR_3", REG_MMIO, 0x4c8e, 1, &mmRLC_SRM_INDEX_CNTL_ADDR_3[0], sizeof(mmRLC_SRM_INDEX_CNTL_ADDR_3)/sizeof(mmRLC_SRM_INDEX_CNTL_ADDR_3[0]), 0, 0 }, + { "mmRLC_SRM_INDEX_CNTL_ADDR_4", REG_MMIO, 0x4c8f, 1, &mmRLC_SRM_INDEX_CNTL_ADDR_4[0], sizeof(mmRLC_SRM_INDEX_CNTL_ADDR_4)/sizeof(mmRLC_SRM_INDEX_CNTL_ADDR_4[0]), 0, 0 }, + { "mmRLC_SRM_INDEX_CNTL_ADDR_5", REG_MMIO, 0x4c90, 1, &mmRLC_SRM_INDEX_CNTL_ADDR_5[0], sizeof(mmRLC_SRM_INDEX_CNTL_ADDR_5)/sizeof(mmRLC_SRM_INDEX_CNTL_ADDR_5[0]), 0, 0 }, + { "mmRLC_SRM_INDEX_CNTL_ADDR_6", REG_MMIO, 0x4c91, 1, &mmRLC_SRM_INDEX_CNTL_ADDR_6[0], sizeof(mmRLC_SRM_INDEX_CNTL_ADDR_6)/sizeof(mmRLC_SRM_INDEX_CNTL_ADDR_6[0]), 0, 0 }, + { "mmRLC_SRM_INDEX_CNTL_ADDR_7", REG_MMIO, 0x4c92, 1, &mmRLC_SRM_INDEX_CNTL_ADDR_7[0], sizeof(mmRLC_SRM_INDEX_CNTL_ADDR_7)/sizeof(mmRLC_SRM_INDEX_CNTL_ADDR_7[0]), 0, 0 }, + { "mmRLC_SRM_INDEX_CNTL_DATA_0", REG_MMIO, 0x4c93, 1, &mmRLC_SRM_INDEX_CNTL_DATA_0[0], sizeof(mmRLC_SRM_INDEX_CNTL_DATA_0)/sizeof(mmRLC_SRM_INDEX_CNTL_DATA_0[0]), 0, 0 }, + { "mmRLC_SRM_INDEX_CNTL_DATA_1", REG_MMIO, 0x4c94, 1, &mmRLC_SRM_INDEX_CNTL_DATA_1[0], sizeof(mmRLC_SRM_INDEX_CNTL_DATA_1)/sizeof(mmRLC_SRM_INDEX_CNTL_DATA_1[0]), 0, 0 }, + { "mmRLC_SRM_INDEX_CNTL_DATA_2", REG_MMIO, 0x4c95, 1, &mmRLC_SRM_INDEX_CNTL_DATA_2[0], sizeof(mmRLC_SRM_INDEX_CNTL_DATA_2)/sizeof(mmRLC_SRM_INDEX_CNTL_DATA_2[0]), 0, 0 }, + { "mmRLC_SRM_INDEX_CNTL_DATA_3", REG_MMIO, 0x4c96, 1, &mmRLC_SRM_INDEX_CNTL_DATA_3[0], sizeof(mmRLC_SRM_INDEX_CNTL_DATA_3)/sizeof(mmRLC_SRM_INDEX_CNTL_DATA_3[0]), 0, 0 }, + { "mmRLC_SRM_INDEX_CNTL_DATA_4", REG_MMIO, 0x4c97, 1, &mmRLC_SRM_INDEX_CNTL_DATA_4[0], sizeof(mmRLC_SRM_INDEX_CNTL_DATA_4)/sizeof(mmRLC_SRM_INDEX_CNTL_DATA_4[0]), 0, 0 }, + { "mmRLC_SRM_INDEX_CNTL_DATA_5", REG_MMIO, 0x4c98, 1, &mmRLC_SRM_INDEX_CNTL_DATA_5[0], sizeof(mmRLC_SRM_INDEX_CNTL_DATA_5)/sizeof(mmRLC_SRM_INDEX_CNTL_DATA_5[0]), 0, 0 }, + { "mmRLC_SRM_INDEX_CNTL_DATA_6", REG_MMIO, 0x4c99, 1, &mmRLC_SRM_INDEX_CNTL_DATA_6[0], sizeof(mmRLC_SRM_INDEX_CNTL_DATA_6)/sizeof(mmRLC_SRM_INDEX_CNTL_DATA_6[0]), 0, 0 }, + { "mmRLC_SRM_INDEX_CNTL_DATA_7", REG_MMIO, 0x4c9a, 1, &mmRLC_SRM_INDEX_CNTL_DATA_7[0], sizeof(mmRLC_SRM_INDEX_CNTL_DATA_7)/sizeof(mmRLC_SRM_INDEX_CNTL_DATA_7[0]), 0, 0 }, + { "mmRLC_SRM_STAT", REG_MMIO, 0x4c9b, 1, &mmRLC_SRM_STAT[0], sizeof(mmRLC_SRM_STAT)/sizeof(mmRLC_SRM_STAT[0]), 0, 0 }, + { "mmRLC_SRM_GPM_ABORT", REG_MMIO, 0x4c9c, 1, &mmRLC_SRM_GPM_ABORT[0], sizeof(mmRLC_SRM_GPM_ABORT)/sizeof(mmRLC_SRM_GPM_ABORT[0]), 0, 0 }, + { "mmRLC_CSIB_ADDR_LO", REG_MMIO, 0x4ca2, 1, &mmRLC_CSIB_ADDR_LO[0], sizeof(mmRLC_CSIB_ADDR_LO)/sizeof(mmRLC_CSIB_ADDR_LO[0]), 0, 0 }, + { "mmRLC_CSIB_ADDR_HI", REG_MMIO, 0x4ca3, 1, &mmRLC_CSIB_ADDR_HI[0], sizeof(mmRLC_CSIB_ADDR_HI)/sizeof(mmRLC_CSIB_ADDR_HI[0]), 0, 0 }, + { "mmRLC_CSIB_LENGTH", REG_MMIO, 0x4ca4, 1, &mmRLC_CSIB_LENGTH[0], sizeof(mmRLC_CSIB_LENGTH)/sizeof(mmRLC_CSIB_LENGTH[0]), 0, 0 }, + { "mmRLC_SMU_COMMAND", REG_MMIO, 0x4ca9, 1, &mmRLC_SMU_COMMAND[0], sizeof(mmRLC_SMU_COMMAND)/sizeof(mmRLC_SMU_COMMAND[0]), 0, 0 }, + { "mmRLC_CP_SCHEDULERS", REG_MMIO, 0x4caa, 1, &mmRLC_CP_SCHEDULERS[0], sizeof(mmRLC_CP_SCHEDULERS)/sizeof(mmRLC_CP_SCHEDULERS[0]), 0, 0 }, + { "mmRLC_SMU_ARGUMENT_1", REG_MMIO, 0x4cab, 1, &mmRLC_SMU_ARGUMENT_1[0], sizeof(mmRLC_SMU_ARGUMENT_1)/sizeof(mmRLC_SMU_ARGUMENT_1[0]), 0, 0 }, + { "mmRLC_SMU_ARGUMENT_2", REG_MMIO, 0x4cac, 1, &mmRLC_SMU_ARGUMENT_2[0], sizeof(mmRLC_SMU_ARGUMENT_2)/sizeof(mmRLC_SMU_ARGUMENT_2[0]), 0, 0 }, + { "mmRLC_GPM_GENERAL_8", REG_MMIO, 0x4cad, 1, &mmRLC_GPM_GENERAL_8[0], sizeof(mmRLC_GPM_GENERAL_8)/sizeof(mmRLC_GPM_GENERAL_8[0]), 0, 0 }, + { "mmRLC_GPM_GENERAL_9", REG_MMIO, 0x4cae, 1, &mmRLC_GPM_GENERAL_9[0], sizeof(mmRLC_GPM_GENERAL_9)/sizeof(mmRLC_GPM_GENERAL_9[0]), 0, 0 }, + { "mmRLC_GPM_GENERAL_10", REG_MMIO, 0x4caf, 1, &mmRLC_GPM_GENERAL_10[0], sizeof(mmRLC_GPM_GENERAL_10)/sizeof(mmRLC_GPM_GENERAL_10[0]), 0, 0 }, + { "mmRLC_GPM_GENERAL_11", REG_MMIO, 0x4cb0, 1, &mmRLC_GPM_GENERAL_11[0], sizeof(mmRLC_GPM_GENERAL_11)/sizeof(mmRLC_GPM_GENERAL_11[0]), 0, 0 }, + { "mmRLC_GPM_GENERAL_12", REG_MMIO, 0x4cb1, 1, &mmRLC_GPM_GENERAL_12[0], sizeof(mmRLC_GPM_GENERAL_12)/sizeof(mmRLC_GPM_GENERAL_12[0]), 0, 0 }, + { "mmRLC_GPM_UTCL1_CNTL_0", REG_MMIO, 0x4cb2, 1, &mmRLC_GPM_UTCL1_CNTL_0[0], sizeof(mmRLC_GPM_UTCL1_CNTL_0)/sizeof(mmRLC_GPM_UTCL1_CNTL_0[0]), 0, 0 }, + { "mmRLC_GPM_UTCL1_CNTL_1", REG_MMIO, 0x4cb3, 1, &mmRLC_GPM_UTCL1_CNTL_1[0], sizeof(mmRLC_GPM_UTCL1_CNTL_1)/sizeof(mmRLC_GPM_UTCL1_CNTL_1[0]), 0, 0 }, + { "mmRLC_GPM_UTCL1_CNTL_2", REG_MMIO, 0x4cb4, 1, &mmRLC_GPM_UTCL1_CNTL_2[0], sizeof(mmRLC_GPM_UTCL1_CNTL_2)/sizeof(mmRLC_GPM_UTCL1_CNTL_2[0]), 0, 0 }, + { "mmRLC_SPM_UTCL1_CNTL", REG_MMIO, 0x4cb5, 1, &mmRLC_SPM_UTCL1_CNTL[0], sizeof(mmRLC_SPM_UTCL1_CNTL)/sizeof(mmRLC_SPM_UTCL1_CNTL[0]), 0, 0 }, + { "mmRLC_UTCL1_STATUS_2", REG_MMIO, 0x4cb6, 1, &mmRLC_UTCL1_STATUS_2[0], sizeof(mmRLC_UTCL1_STATUS_2)/sizeof(mmRLC_UTCL1_STATUS_2[0]), 0, 0 }, + { "mmRLC_LB_THR_CONFIG_2", REG_MMIO, 0x4cb8, 1, &mmRLC_LB_THR_CONFIG_2[0], sizeof(mmRLC_LB_THR_CONFIG_2)/sizeof(mmRLC_LB_THR_CONFIG_2[0]), 0, 0 }, + { "mmRLC_LB_THR_CONFIG_3", REG_MMIO, 0x4cb9, 1, &mmRLC_LB_THR_CONFIG_3[0], sizeof(mmRLC_LB_THR_CONFIG_3)/sizeof(mmRLC_LB_THR_CONFIG_3[0]), 0, 0 }, + { "mmRLC_LB_THR_CONFIG_4", REG_MMIO, 0x4cba, 1, &mmRLC_LB_THR_CONFIG_4[0], sizeof(mmRLC_LB_THR_CONFIG_4)/sizeof(mmRLC_LB_THR_CONFIG_4[0]), 0, 0 }, + { "mmRLC_SPM_UTCL1_ERROR_1", REG_MMIO, 0x4cbc, 1, &mmRLC_SPM_UTCL1_ERROR_1[0], sizeof(mmRLC_SPM_UTCL1_ERROR_1)/sizeof(mmRLC_SPM_UTCL1_ERROR_1[0]), 0, 0 }, + { "mmRLC_SPM_UTCL1_ERROR_2", REG_MMIO, 0x4cbd, 1, &mmRLC_SPM_UTCL1_ERROR_2[0], sizeof(mmRLC_SPM_UTCL1_ERROR_2)/sizeof(mmRLC_SPM_UTCL1_ERROR_2[0]), 0, 0 }, + { "mmRLC_GPM_UTCL1_TH0_ERROR_1", REG_MMIO, 0x4cbe, 1, &mmRLC_GPM_UTCL1_TH0_ERROR_1[0], sizeof(mmRLC_GPM_UTCL1_TH0_ERROR_1)/sizeof(mmRLC_GPM_UTCL1_TH0_ERROR_1[0]), 0, 0 }, + { "mmRLC_LB_THR_CONFIG_1", REG_MMIO, 0x4cbf, 1, &mmRLC_LB_THR_CONFIG_1[0], sizeof(mmRLC_LB_THR_CONFIG_1)/sizeof(mmRLC_LB_THR_CONFIG_1[0]), 0, 0 }, + { "mmRLC_GPM_UTCL1_TH0_ERROR_2", REG_MMIO, 0x4cc0, 1, &mmRLC_GPM_UTCL1_TH0_ERROR_2[0], sizeof(mmRLC_GPM_UTCL1_TH0_ERROR_2)/sizeof(mmRLC_GPM_UTCL1_TH0_ERROR_2[0]), 0, 0 }, + { "mmRLC_GPM_UTCL1_TH1_ERROR_1", REG_MMIO, 0x4cc1, 1, &mmRLC_GPM_UTCL1_TH1_ERROR_1[0], sizeof(mmRLC_GPM_UTCL1_TH1_ERROR_1)/sizeof(mmRLC_GPM_UTCL1_TH1_ERROR_1[0]), 0, 0 }, + { "mmRLC_GPM_UTCL1_TH1_ERROR_2", REG_MMIO, 0x4cc2, 1, &mmRLC_GPM_UTCL1_TH1_ERROR_2[0], sizeof(mmRLC_GPM_UTCL1_TH1_ERROR_2)/sizeof(mmRLC_GPM_UTCL1_TH1_ERROR_2[0]), 0, 0 }, + { "mmRLC_GPM_UTCL1_TH2_ERROR_1", REG_MMIO, 0x4cc3, 1, &mmRLC_GPM_UTCL1_TH2_ERROR_1[0], sizeof(mmRLC_GPM_UTCL1_TH2_ERROR_1)/sizeof(mmRLC_GPM_UTCL1_TH2_ERROR_1[0]), 0, 0 }, + { "mmRLC_GPM_UTCL1_TH2_ERROR_2", REG_MMIO, 0x4cc4, 1, &mmRLC_GPM_UTCL1_TH2_ERROR_2[0], sizeof(mmRLC_GPM_UTCL1_TH2_ERROR_2)/sizeof(mmRLC_GPM_UTCL1_TH2_ERROR_2[0]), 0, 0 }, + { "mmRLC_CGCG_CGLS_CTRL_3D", REG_MMIO, 0x4cc5, 1, &mmRLC_CGCG_CGLS_CTRL_3D[0], sizeof(mmRLC_CGCG_CGLS_CTRL_3D)/sizeof(mmRLC_CGCG_CGLS_CTRL_3D[0]), 0, 0 }, + { "mmRLC_CGCG_RAMP_CTRL_3D", REG_MMIO, 0x4cc6, 1, &mmRLC_CGCG_RAMP_CTRL_3D[0], sizeof(mmRLC_CGCG_RAMP_CTRL_3D)/sizeof(mmRLC_CGCG_RAMP_CTRL_3D[0]), 0, 0 }, + { "mmRLC_SEMAPHORE_0", REG_MMIO, 0x4cc7, 1, &mmRLC_SEMAPHORE_0[0], sizeof(mmRLC_SEMAPHORE_0)/sizeof(mmRLC_SEMAPHORE_0[0]), 0, 0 }, + { "mmRLC_SEMAPHORE_1", REG_MMIO, 0x4cc8, 1, &mmRLC_SEMAPHORE_1[0], sizeof(mmRLC_SEMAPHORE_1)/sizeof(mmRLC_SEMAPHORE_1[0]), 0, 0 }, + { "mmRLC_CP_EOF_INT", REG_MMIO, 0x4cca, 1, &mmRLC_CP_EOF_INT[0], sizeof(mmRLC_CP_EOF_INT)/sizeof(mmRLC_CP_EOF_INT[0]), 0, 0 }, + { "mmRLC_CP_EOF_INT_CNT", REG_MMIO, 0x4ccb, 1, &mmRLC_CP_EOF_INT_CNT[0], sizeof(mmRLC_CP_EOF_INT_CNT)/sizeof(mmRLC_CP_EOF_INT_CNT[0]), 0, 0 }, + { "mmRLC_SPARE_INT", REG_MMIO, 0x4ccc, 1, &mmRLC_SPARE_INT[0], sizeof(mmRLC_SPARE_INT)/sizeof(mmRLC_SPARE_INT[0]), 0, 0 }, + { "mmRLC_PREWALKER_UTCL1_CNTL", REG_MMIO, 0x4ccd, 1, &mmRLC_PREWALKER_UTCL1_CNTL[0], sizeof(mmRLC_PREWALKER_UTCL1_CNTL)/sizeof(mmRLC_PREWALKER_UTCL1_CNTL[0]), 0, 0 }, + { "mmRLC_PREWALKER_UTCL1_TRIG", REG_MMIO, 0x4cce, 1, &mmRLC_PREWALKER_UTCL1_TRIG[0], sizeof(mmRLC_PREWALKER_UTCL1_TRIG)/sizeof(mmRLC_PREWALKER_UTCL1_TRIG[0]), 0, 0 }, + { "mmRLC_PREWALKER_UTCL1_ADDR_LSB", REG_MMIO, 0x4ccf, 1, &mmRLC_PREWALKER_UTCL1_ADDR_LSB[0], sizeof(mmRLC_PREWALKER_UTCL1_ADDR_LSB)/sizeof(mmRLC_PREWALKER_UTCL1_ADDR_LSB[0]), 0, 0 }, + { "mmRLC_PREWALKER_UTCL1_ADDR_MSB", REG_MMIO, 0x4cd0, 1, &mmRLC_PREWALKER_UTCL1_ADDR_MSB[0], sizeof(mmRLC_PREWALKER_UTCL1_ADDR_MSB)/sizeof(mmRLC_PREWALKER_UTCL1_ADDR_MSB[0]), 0, 0 }, + { "mmRLC_PREWALKER_UTCL1_SIZE_LSB", REG_MMIO, 0x4cd1, 1, &mmRLC_PREWALKER_UTCL1_SIZE_LSB[0], sizeof(mmRLC_PREWALKER_UTCL1_SIZE_LSB)/sizeof(mmRLC_PREWALKER_UTCL1_SIZE_LSB[0]), 0, 0 }, + { "mmRLC_PREWALKER_UTCL1_SIZE_MSB", REG_MMIO, 0x4cd2, 1, &mmRLC_PREWALKER_UTCL1_SIZE_MSB[0], sizeof(mmRLC_PREWALKER_UTCL1_SIZE_MSB)/sizeof(mmRLC_PREWALKER_UTCL1_SIZE_MSB[0]), 0, 0 }, + { "mmRLC_DSM_TRIG", REG_MMIO, 0x4cd3, 1, NULL, 0, 0, 0 }, + { "mmRLC_UTCL1_STATUS", REG_MMIO, 0x4cd4, 1, &mmRLC_UTCL1_STATUS[0], sizeof(mmRLC_UTCL1_STATUS)/sizeof(mmRLC_UTCL1_STATUS[0]), 0, 0 }, + { "mmRLC_R2I_CNTL_0", REG_MMIO, 0x4cd5, 1, &mmRLC_R2I_CNTL_0[0], sizeof(mmRLC_R2I_CNTL_0)/sizeof(mmRLC_R2I_CNTL_0[0]), 0, 0 }, + { "mmRLC_R2I_CNTL_1", REG_MMIO, 0x4cd6, 1, &mmRLC_R2I_CNTL_1[0], sizeof(mmRLC_R2I_CNTL_1)/sizeof(mmRLC_R2I_CNTL_1[0]), 0, 0 }, + { "mmRLC_R2I_CNTL_2", REG_MMIO, 0x4cd7, 1, &mmRLC_R2I_CNTL_2[0], sizeof(mmRLC_R2I_CNTL_2)/sizeof(mmRLC_R2I_CNTL_2[0]), 0, 0 }, + { "mmRLC_R2I_CNTL_3", REG_MMIO, 0x4cd8, 1, &mmRLC_R2I_CNTL_3[0], sizeof(mmRLC_R2I_CNTL_3)/sizeof(mmRLC_R2I_CNTL_3[0]), 0, 0 }, + { "mmRLC_UTCL2_CNTL", REG_MMIO, 0x4cd9, 1, &mmRLC_UTCL2_CNTL[0], sizeof(mmRLC_UTCL2_CNTL)/sizeof(mmRLC_UTCL2_CNTL[0]), 0, 0 }, + { "mmRLC_LBPW_CU_STAT", REG_MMIO, 0x4cda, 1, &mmRLC_LBPW_CU_STAT[0], sizeof(mmRLC_LBPW_CU_STAT)/sizeof(mmRLC_LBPW_CU_STAT[0]), 0, 0 }, + { "mmRLC_DS_CNTL", REG_MMIO, 0x4cdb, 1, &mmRLC_DS_CNTL[0], sizeof(mmRLC_DS_CNTL)/sizeof(mmRLC_DS_CNTL[0]), 0, 0 }, + { "mmRLC_RLCV_SPARE_INT", REG_MMIO, 0x4f30, 1, &mmRLC_RLCV_SPARE_INT[0], sizeof(mmRLC_RLCV_SPARE_INT)/sizeof(mmRLC_RLCV_SPARE_INT[0]), 0, 0 }, + { "mmCGTS_SM_CTRL_REG", REG_MMIO, 0x5000, 1, &mmCGTS_SM_CTRL_REG[0], sizeof(mmCGTS_SM_CTRL_REG)/sizeof(mmCGTS_SM_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_RD_CTRL_REG", REG_MMIO, 0x5001, 1, &mmCGTS_RD_CTRL_REG[0], sizeof(mmCGTS_RD_CTRL_REG)/sizeof(mmCGTS_RD_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_RD_REG", REG_MMIO, 0x5002, 1, &mmCGTS_RD_REG[0], sizeof(mmCGTS_RD_REG)/sizeof(mmCGTS_RD_REG[0]), 0, 0 }, + { "mmCGTS_TCC_DISABLE", REG_MMIO, 0x5003, 1, &mmCGTS_TCC_DISABLE[0], sizeof(mmCGTS_TCC_DISABLE)/sizeof(mmCGTS_TCC_DISABLE[0]), 0, 0 }, + { "mmCGTS_USER_TCC_DISABLE", REG_MMIO, 0x5004, 1, &mmCGTS_USER_TCC_DISABLE[0], sizeof(mmCGTS_USER_TCC_DISABLE)/sizeof(mmCGTS_USER_TCC_DISABLE[0]), 0, 0 }, + { "mmCGTS_CU0_SP0_CTRL_REG", REG_MMIO, 0x5008, 1, &mmCGTS_CU0_SP0_CTRL_REG[0], sizeof(mmCGTS_CU0_SP0_CTRL_REG)/sizeof(mmCGTS_CU0_SP0_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU0_LDS_SQ_CTRL_REG", REG_MMIO, 0x5009, 1, &mmCGTS_CU0_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU0_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU0_LDS_SQ_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU0_TA_SQC_CTRL_REG", REG_MMIO, 0x500a, 1, &mmCGTS_CU0_TA_SQC_CTRL_REG[0], sizeof(mmCGTS_CU0_TA_SQC_CTRL_REG)/sizeof(mmCGTS_CU0_TA_SQC_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU0_SP1_CTRL_REG", REG_MMIO, 0x500b, 1, &mmCGTS_CU0_SP1_CTRL_REG[0], sizeof(mmCGTS_CU0_SP1_CTRL_REG)/sizeof(mmCGTS_CU0_SP1_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU0_TD_TCP_CTRL_REG", REG_MMIO, 0x500c, 1, &mmCGTS_CU0_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU0_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU0_TD_TCP_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU1_SP0_CTRL_REG", REG_MMIO, 0x500d, 1, &mmCGTS_CU1_SP0_CTRL_REG[0], sizeof(mmCGTS_CU1_SP0_CTRL_REG)/sizeof(mmCGTS_CU1_SP0_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU1_LDS_SQ_CTRL_REG", REG_MMIO, 0x500e, 1, &mmCGTS_CU1_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU1_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU1_LDS_SQ_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU1_TA_SQC_CTRL_REG", REG_MMIO, 0x500f, 1, &mmCGTS_CU1_TA_SQC_CTRL_REG[0], sizeof(mmCGTS_CU1_TA_SQC_CTRL_REG)/sizeof(mmCGTS_CU1_TA_SQC_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU1_SP1_CTRL_REG", REG_MMIO, 0x5010, 1, &mmCGTS_CU1_SP1_CTRL_REG[0], sizeof(mmCGTS_CU1_SP1_CTRL_REG)/sizeof(mmCGTS_CU1_SP1_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU1_TD_TCP_CTRL_REG", REG_MMIO, 0x5011, 1, &mmCGTS_CU1_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU1_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU1_TD_TCP_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU2_SP0_CTRL_REG", REG_MMIO, 0x5012, 1, &mmCGTS_CU2_SP0_CTRL_REG[0], sizeof(mmCGTS_CU2_SP0_CTRL_REG)/sizeof(mmCGTS_CU2_SP0_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU2_LDS_SQ_CTRL_REG", REG_MMIO, 0x5013, 1, &mmCGTS_CU2_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU2_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU2_LDS_SQ_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU2_TA_SQC_CTRL_REG", REG_MMIO, 0x5014, 1, &mmCGTS_CU2_TA_SQC_CTRL_REG[0], sizeof(mmCGTS_CU2_TA_SQC_CTRL_REG)/sizeof(mmCGTS_CU2_TA_SQC_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU2_SP1_CTRL_REG", REG_MMIO, 0x5015, 1, &mmCGTS_CU2_SP1_CTRL_REG[0], sizeof(mmCGTS_CU2_SP1_CTRL_REG)/sizeof(mmCGTS_CU2_SP1_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU2_TD_TCP_CTRL_REG", REG_MMIO, 0x5016, 1, &mmCGTS_CU2_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU2_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU2_TD_TCP_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU3_SP0_CTRL_REG", REG_MMIO, 0x5017, 1, &mmCGTS_CU3_SP0_CTRL_REG[0], sizeof(mmCGTS_CU3_SP0_CTRL_REG)/sizeof(mmCGTS_CU3_SP0_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU3_LDS_SQ_CTRL_REG", REG_MMIO, 0x5018, 1, &mmCGTS_CU3_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU3_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU3_LDS_SQ_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU3_TA_SQC_CTRL_REG", REG_MMIO, 0x5019, 1, &mmCGTS_CU3_TA_SQC_CTRL_REG[0], sizeof(mmCGTS_CU3_TA_SQC_CTRL_REG)/sizeof(mmCGTS_CU3_TA_SQC_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU3_SP1_CTRL_REG", REG_MMIO, 0x501a, 1, &mmCGTS_CU3_SP1_CTRL_REG[0], sizeof(mmCGTS_CU3_SP1_CTRL_REG)/sizeof(mmCGTS_CU3_SP1_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU3_TD_TCP_CTRL_REG", REG_MMIO, 0x501b, 1, &mmCGTS_CU3_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU3_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU3_TD_TCP_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU4_SP0_CTRL_REG", REG_MMIO, 0x501c, 1, &mmCGTS_CU4_SP0_CTRL_REG[0], sizeof(mmCGTS_CU4_SP0_CTRL_REG)/sizeof(mmCGTS_CU4_SP0_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU4_LDS_SQ_CTRL_REG", REG_MMIO, 0x501d, 1, &mmCGTS_CU4_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU4_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU4_LDS_SQ_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU4_TA_SQC_CTRL_REG", REG_MMIO, 0x501e, 1, &mmCGTS_CU4_TA_SQC_CTRL_REG[0], sizeof(mmCGTS_CU4_TA_SQC_CTRL_REG)/sizeof(mmCGTS_CU4_TA_SQC_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU4_SP1_CTRL_REG", REG_MMIO, 0x501f, 1, &mmCGTS_CU4_SP1_CTRL_REG[0], sizeof(mmCGTS_CU4_SP1_CTRL_REG)/sizeof(mmCGTS_CU4_SP1_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU4_TD_TCP_CTRL_REG", REG_MMIO, 0x5020, 1, &mmCGTS_CU4_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU4_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU4_TD_TCP_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU5_SP0_CTRL_REG", REG_MMIO, 0x5021, 1, &mmCGTS_CU5_SP0_CTRL_REG[0], sizeof(mmCGTS_CU5_SP0_CTRL_REG)/sizeof(mmCGTS_CU5_SP0_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU5_LDS_SQ_CTRL_REG", REG_MMIO, 0x5022, 1, &mmCGTS_CU5_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU5_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU5_LDS_SQ_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU5_TA_SQC_CTRL_REG", REG_MMIO, 0x5023, 1, &mmCGTS_CU5_TA_SQC_CTRL_REG[0], sizeof(mmCGTS_CU5_TA_SQC_CTRL_REG)/sizeof(mmCGTS_CU5_TA_SQC_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU5_SP1_CTRL_REG", REG_MMIO, 0x5024, 1, &mmCGTS_CU5_SP1_CTRL_REG[0], sizeof(mmCGTS_CU5_SP1_CTRL_REG)/sizeof(mmCGTS_CU5_SP1_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU5_TD_TCP_CTRL_REG", REG_MMIO, 0x5025, 1, &mmCGTS_CU5_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU5_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU5_TD_TCP_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU6_SP0_CTRL_REG", REG_MMIO, 0x5026, 1, &mmCGTS_CU6_SP0_CTRL_REG[0], sizeof(mmCGTS_CU6_SP0_CTRL_REG)/sizeof(mmCGTS_CU6_SP0_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU6_LDS_SQ_CTRL_REG", REG_MMIO, 0x5027, 1, &mmCGTS_CU6_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU6_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU6_LDS_SQ_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU6_TA_SQC_CTRL_REG", REG_MMIO, 0x5028, 1, &mmCGTS_CU6_TA_SQC_CTRL_REG[0], sizeof(mmCGTS_CU6_TA_SQC_CTRL_REG)/sizeof(mmCGTS_CU6_TA_SQC_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU6_SP1_CTRL_REG", REG_MMIO, 0x5029, 1, &mmCGTS_CU6_SP1_CTRL_REG[0], sizeof(mmCGTS_CU6_SP1_CTRL_REG)/sizeof(mmCGTS_CU6_SP1_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU6_TD_TCP_CTRL_REG", REG_MMIO, 0x502a, 1, &mmCGTS_CU6_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU6_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU6_TD_TCP_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU7_SP0_CTRL_REG", REG_MMIO, 0x502b, 1, &mmCGTS_CU7_SP0_CTRL_REG[0], sizeof(mmCGTS_CU7_SP0_CTRL_REG)/sizeof(mmCGTS_CU7_SP0_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU7_LDS_SQ_CTRL_REG", REG_MMIO, 0x502c, 1, &mmCGTS_CU7_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU7_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU7_LDS_SQ_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU7_TA_SQC_CTRL_REG", REG_MMIO, 0x502d, 1, &mmCGTS_CU7_TA_SQC_CTRL_REG[0], sizeof(mmCGTS_CU7_TA_SQC_CTRL_REG)/sizeof(mmCGTS_CU7_TA_SQC_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU7_SP1_CTRL_REG", REG_MMIO, 0x502e, 1, &mmCGTS_CU7_SP1_CTRL_REG[0], sizeof(mmCGTS_CU7_SP1_CTRL_REG)/sizeof(mmCGTS_CU7_SP1_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU7_TD_TCP_CTRL_REG", REG_MMIO, 0x502f, 1, &mmCGTS_CU7_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU7_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU7_TD_TCP_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU8_SP0_CTRL_REG", REG_MMIO, 0x5030, 1, &mmCGTS_CU8_SP0_CTRL_REG[0], sizeof(mmCGTS_CU8_SP0_CTRL_REG)/sizeof(mmCGTS_CU8_SP0_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU8_LDS_SQ_CTRL_REG", REG_MMIO, 0x5031, 1, &mmCGTS_CU8_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU8_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU8_LDS_SQ_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU8_TA_SQC_CTRL_REG", REG_MMIO, 0x5032, 1, &mmCGTS_CU8_TA_SQC_CTRL_REG[0], sizeof(mmCGTS_CU8_TA_SQC_CTRL_REG)/sizeof(mmCGTS_CU8_TA_SQC_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU8_SP1_CTRL_REG", REG_MMIO, 0x5033, 1, &mmCGTS_CU8_SP1_CTRL_REG[0], sizeof(mmCGTS_CU8_SP1_CTRL_REG)/sizeof(mmCGTS_CU8_SP1_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU8_TD_TCP_CTRL_REG", REG_MMIO, 0x5034, 1, &mmCGTS_CU8_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU8_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU8_TD_TCP_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU9_SP0_CTRL_REG", REG_MMIO, 0x5035, 1, &mmCGTS_CU9_SP0_CTRL_REG[0], sizeof(mmCGTS_CU9_SP0_CTRL_REG)/sizeof(mmCGTS_CU9_SP0_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU9_LDS_SQ_CTRL_REG", REG_MMIO, 0x5036, 1, &mmCGTS_CU9_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU9_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU9_LDS_SQ_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU9_TA_SQC_CTRL_REG", REG_MMIO, 0x5037, 1, &mmCGTS_CU9_TA_SQC_CTRL_REG[0], sizeof(mmCGTS_CU9_TA_SQC_CTRL_REG)/sizeof(mmCGTS_CU9_TA_SQC_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU9_SP1_CTRL_REG", REG_MMIO, 0x5038, 1, &mmCGTS_CU9_SP1_CTRL_REG[0], sizeof(mmCGTS_CU9_SP1_CTRL_REG)/sizeof(mmCGTS_CU9_SP1_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU9_TD_TCP_CTRL_REG", REG_MMIO, 0x5039, 1, &mmCGTS_CU9_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU9_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU9_TD_TCP_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU10_SP0_CTRL_REG", REG_MMIO, 0x503a, 1, &mmCGTS_CU10_SP0_CTRL_REG[0], sizeof(mmCGTS_CU10_SP0_CTRL_REG)/sizeof(mmCGTS_CU10_SP0_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU10_LDS_SQ_CTRL_REG", REG_MMIO, 0x503b, 1, &mmCGTS_CU10_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU10_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU10_LDS_SQ_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU10_TA_SQC_CTRL_REG", REG_MMIO, 0x503c, 1, &mmCGTS_CU10_TA_SQC_CTRL_REG[0], sizeof(mmCGTS_CU10_TA_SQC_CTRL_REG)/sizeof(mmCGTS_CU10_TA_SQC_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU10_SP1_CTRL_REG", REG_MMIO, 0x503d, 1, &mmCGTS_CU10_SP1_CTRL_REG[0], sizeof(mmCGTS_CU10_SP1_CTRL_REG)/sizeof(mmCGTS_CU10_SP1_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU10_TD_TCP_CTRL_REG", REG_MMIO, 0x503e, 1, &mmCGTS_CU10_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU10_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU10_TD_TCP_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU11_SP0_CTRL_REG", REG_MMIO, 0x503f, 1, &mmCGTS_CU11_SP0_CTRL_REG[0], sizeof(mmCGTS_CU11_SP0_CTRL_REG)/sizeof(mmCGTS_CU11_SP0_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU11_LDS_SQ_CTRL_REG", REG_MMIO, 0x5040, 1, &mmCGTS_CU11_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU11_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU11_LDS_SQ_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU11_TA_SQC_CTRL_REG", REG_MMIO, 0x5041, 1, &mmCGTS_CU11_TA_SQC_CTRL_REG[0], sizeof(mmCGTS_CU11_TA_SQC_CTRL_REG)/sizeof(mmCGTS_CU11_TA_SQC_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU11_SP1_CTRL_REG", REG_MMIO, 0x5042, 1, &mmCGTS_CU11_SP1_CTRL_REG[0], sizeof(mmCGTS_CU11_SP1_CTRL_REG)/sizeof(mmCGTS_CU11_SP1_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU11_TD_TCP_CTRL_REG", REG_MMIO, 0x5043, 1, &mmCGTS_CU11_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU11_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU11_TD_TCP_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU12_SP0_CTRL_REG", REG_MMIO, 0x5044, 1, &mmCGTS_CU12_SP0_CTRL_REG[0], sizeof(mmCGTS_CU12_SP0_CTRL_REG)/sizeof(mmCGTS_CU12_SP0_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU12_LDS_SQ_CTRL_REG", REG_MMIO, 0x5045, 1, &mmCGTS_CU12_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU12_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU12_LDS_SQ_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU12_TA_SQC_CTRL_REG", REG_MMIO, 0x5046, 1, &mmCGTS_CU12_TA_SQC_CTRL_REG[0], sizeof(mmCGTS_CU12_TA_SQC_CTRL_REG)/sizeof(mmCGTS_CU12_TA_SQC_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU12_SP1_CTRL_REG", REG_MMIO, 0x5047, 1, &mmCGTS_CU12_SP1_CTRL_REG[0], sizeof(mmCGTS_CU12_SP1_CTRL_REG)/sizeof(mmCGTS_CU12_SP1_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU12_TD_TCP_CTRL_REG", REG_MMIO, 0x5048, 1, &mmCGTS_CU12_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU12_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU12_TD_TCP_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU13_SP0_CTRL_REG", REG_MMIO, 0x5049, 1, &mmCGTS_CU13_SP0_CTRL_REG[0], sizeof(mmCGTS_CU13_SP0_CTRL_REG)/sizeof(mmCGTS_CU13_SP0_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU13_LDS_SQ_CTRL_REG", REG_MMIO, 0x504a, 1, &mmCGTS_CU13_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU13_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU13_LDS_SQ_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU13_TA_SQC_CTRL_REG", REG_MMIO, 0x504b, 1, &mmCGTS_CU13_TA_SQC_CTRL_REG[0], sizeof(mmCGTS_CU13_TA_SQC_CTRL_REG)/sizeof(mmCGTS_CU13_TA_SQC_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU13_SP1_CTRL_REG", REG_MMIO, 0x504c, 1, &mmCGTS_CU13_SP1_CTRL_REG[0], sizeof(mmCGTS_CU13_SP1_CTRL_REG)/sizeof(mmCGTS_CU13_SP1_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU13_TD_TCP_CTRL_REG", REG_MMIO, 0x504d, 1, &mmCGTS_CU13_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU13_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU13_TD_TCP_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU14_SP0_CTRL_REG", REG_MMIO, 0x504e, 1, &mmCGTS_CU14_SP0_CTRL_REG[0], sizeof(mmCGTS_CU14_SP0_CTRL_REG)/sizeof(mmCGTS_CU14_SP0_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU14_LDS_SQ_CTRL_REG", REG_MMIO, 0x504f, 1, &mmCGTS_CU14_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU14_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU14_LDS_SQ_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU14_TA_SQC_CTRL_REG", REG_MMIO, 0x5050, 1, &mmCGTS_CU14_TA_SQC_CTRL_REG[0], sizeof(mmCGTS_CU14_TA_SQC_CTRL_REG)/sizeof(mmCGTS_CU14_TA_SQC_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU14_SP1_CTRL_REG", REG_MMIO, 0x5051, 1, &mmCGTS_CU14_SP1_CTRL_REG[0], sizeof(mmCGTS_CU14_SP1_CTRL_REG)/sizeof(mmCGTS_CU14_SP1_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU14_TD_TCP_CTRL_REG", REG_MMIO, 0x5052, 1, &mmCGTS_CU14_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU14_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU14_TD_TCP_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU15_SP0_CTRL_REG", REG_MMIO, 0x5053, 1, &mmCGTS_CU15_SP0_CTRL_REG[0], sizeof(mmCGTS_CU15_SP0_CTRL_REG)/sizeof(mmCGTS_CU15_SP0_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU15_LDS_SQ_CTRL_REG", REG_MMIO, 0x5054, 1, &mmCGTS_CU15_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU15_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU15_LDS_SQ_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU15_TA_SQC_CTRL_REG", REG_MMIO, 0x5055, 1, &mmCGTS_CU15_TA_SQC_CTRL_REG[0], sizeof(mmCGTS_CU15_TA_SQC_CTRL_REG)/sizeof(mmCGTS_CU15_TA_SQC_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU15_SP1_CTRL_REG", REG_MMIO, 0x5056, 1, &mmCGTS_CU15_SP1_CTRL_REG[0], sizeof(mmCGTS_CU15_SP1_CTRL_REG)/sizeof(mmCGTS_CU15_SP1_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU15_TD_TCP_CTRL_REG", REG_MMIO, 0x5057, 1, &mmCGTS_CU15_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU15_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU15_TD_TCP_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU0_TCPI_CTRL_REG", REG_MMIO, 0x5058, 1, &mmCGTS_CU0_TCPI_CTRL_REG[0], sizeof(mmCGTS_CU0_TCPI_CTRL_REG)/sizeof(mmCGTS_CU0_TCPI_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU1_TCPI_CTRL_REG", REG_MMIO, 0x5059, 1, &mmCGTS_CU1_TCPI_CTRL_REG[0], sizeof(mmCGTS_CU1_TCPI_CTRL_REG)/sizeof(mmCGTS_CU1_TCPI_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU2_TCPI_CTRL_REG", REG_MMIO, 0x505a, 1, &mmCGTS_CU2_TCPI_CTRL_REG[0], sizeof(mmCGTS_CU2_TCPI_CTRL_REG)/sizeof(mmCGTS_CU2_TCPI_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU3_TCPI_CTRL_REG", REG_MMIO, 0x505b, 1, &mmCGTS_CU3_TCPI_CTRL_REG[0], sizeof(mmCGTS_CU3_TCPI_CTRL_REG)/sizeof(mmCGTS_CU3_TCPI_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU4_TCPI_CTRL_REG", REG_MMIO, 0x505c, 1, &mmCGTS_CU4_TCPI_CTRL_REG[0], sizeof(mmCGTS_CU4_TCPI_CTRL_REG)/sizeof(mmCGTS_CU4_TCPI_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU5_TCPI_CTRL_REG", REG_MMIO, 0x505d, 1, &mmCGTS_CU5_TCPI_CTRL_REG[0], sizeof(mmCGTS_CU5_TCPI_CTRL_REG)/sizeof(mmCGTS_CU5_TCPI_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU6_TCPI_CTRL_REG", REG_MMIO, 0x505e, 1, &mmCGTS_CU6_TCPI_CTRL_REG[0], sizeof(mmCGTS_CU6_TCPI_CTRL_REG)/sizeof(mmCGTS_CU6_TCPI_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU7_TCPI_CTRL_REG", REG_MMIO, 0x505f, 1, &mmCGTS_CU7_TCPI_CTRL_REG[0], sizeof(mmCGTS_CU7_TCPI_CTRL_REG)/sizeof(mmCGTS_CU7_TCPI_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU8_TCPI_CTRL_REG", REG_MMIO, 0x5060, 1, &mmCGTS_CU8_TCPI_CTRL_REG[0], sizeof(mmCGTS_CU8_TCPI_CTRL_REG)/sizeof(mmCGTS_CU8_TCPI_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU9_TCPI_CTRL_REG", REG_MMIO, 0x5061, 1, &mmCGTS_CU9_TCPI_CTRL_REG[0], sizeof(mmCGTS_CU9_TCPI_CTRL_REG)/sizeof(mmCGTS_CU9_TCPI_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU10_TCPI_CTRL_REG", REG_MMIO, 0x5062, 1, &mmCGTS_CU10_TCPI_CTRL_REG[0], sizeof(mmCGTS_CU10_TCPI_CTRL_REG)/sizeof(mmCGTS_CU10_TCPI_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU11_TCPI_CTRL_REG", REG_MMIO, 0x5063, 1, &mmCGTS_CU11_TCPI_CTRL_REG[0], sizeof(mmCGTS_CU11_TCPI_CTRL_REG)/sizeof(mmCGTS_CU11_TCPI_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU12_TCPI_CTRL_REG", REG_MMIO, 0x5064, 1, &mmCGTS_CU12_TCPI_CTRL_REG[0], sizeof(mmCGTS_CU12_TCPI_CTRL_REG)/sizeof(mmCGTS_CU12_TCPI_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU13_TCPI_CTRL_REG", REG_MMIO, 0x5065, 1, &mmCGTS_CU13_TCPI_CTRL_REG[0], sizeof(mmCGTS_CU13_TCPI_CTRL_REG)/sizeof(mmCGTS_CU13_TCPI_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU14_TCPI_CTRL_REG", REG_MMIO, 0x5066, 1, &mmCGTS_CU14_TCPI_CTRL_REG[0], sizeof(mmCGTS_CU14_TCPI_CTRL_REG)/sizeof(mmCGTS_CU14_TCPI_CTRL_REG[0]), 0, 0 }, + { "mmCGTS_CU15_TCPI_CTRL_REG", REG_MMIO, 0x5067, 1, &mmCGTS_CU15_TCPI_CTRL_REG[0], sizeof(mmCGTS_CU15_TCPI_CTRL_REG)/sizeof(mmCGTS_CU15_TCPI_CTRL_REG[0]), 0, 0 }, + { "mmCGTT_SPI_CLK_CTRL", REG_MMIO, 0x5080, 1, &mmCGTT_SPI_CLK_CTRL[0], sizeof(mmCGTT_SPI_CLK_CTRL)/sizeof(mmCGTT_SPI_CLK_CTRL[0]), 0, 0 }, + { "mmCGTT_PC_CLK_CTRL", REG_MMIO, 0x5081, 1, &mmCGTT_PC_CLK_CTRL[0], sizeof(mmCGTT_PC_CLK_CTRL)/sizeof(mmCGTT_PC_CLK_CTRL[0]), 0, 0 }, + { "mmCGTT_BCI_CLK_CTRL", REG_MMIO, 0x5082, 1, &mmCGTT_BCI_CLK_CTRL[0], sizeof(mmCGTT_BCI_CLK_CTRL)/sizeof(mmCGTT_BCI_CLK_CTRL[0]), 0, 0 }, + { "mmCGTT_VGT_CLK_CTRL", REG_MMIO, 0x5084, 1, &mmCGTT_VGT_CLK_CTRL[0], sizeof(mmCGTT_VGT_CLK_CTRL)/sizeof(mmCGTT_VGT_CLK_CTRL[0]), 0, 0 }, + { "mmCGTT_IA_CLK_CTRL", REG_MMIO, 0x5085, 1, &mmCGTT_IA_CLK_CTRL[0], sizeof(mmCGTT_IA_CLK_CTRL)/sizeof(mmCGTT_IA_CLK_CTRL[0]), 0, 0 }, + { "mmCGTT_WD_CLK_CTRL", REG_MMIO, 0x5086, 1, &mmCGTT_WD_CLK_CTRL[0], sizeof(mmCGTT_WD_CLK_CTRL)/sizeof(mmCGTT_WD_CLK_CTRL[0]), 0, 0 }, + { "mmCGTT_PA_CLK_CTRL", REG_MMIO, 0x5088, 1, &mmCGTT_PA_CLK_CTRL[0], sizeof(mmCGTT_PA_CLK_CTRL)/sizeof(mmCGTT_PA_CLK_CTRL[0]), 0, 0 }, + { "mmCGTT_SC_CLK_CTRL0", REG_MMIO, 0x5089, 1, &mmCGTT_SC_CLK_CTRL0[0], sizeof(mmCGTT_SC_CLK_CTRL0)/sizeof(mmCGTT_SC_CLK_CTRL0[0]), 0, 0 }, + { "mmCGTT_SC_CLK_CTRL1", REG_MMIO, 0x508a, 1, &mmCGTT_SC_CLK_CTRL1[0], sizeof(mmCGTT_SC_CLK_CTRL1)/sizeof(mmCGTT_SC_CLK_CTRL1[0]), 0, 0 }, + { "mmCGTT_SQ_CLK_CTRL", REG_MMIO, 0x508c, 1, &mmCGTT_SQ_CLK_CTRL[0], sizeof(mmCGTT_SQ_CLK_CTRL)/sizeof(mmCGTT_SQ_CLK_CTRL[0]), 0, 0 }, + { "mmCGTT_SQG_CLK_CTRL", REG_MMIO, 0x508d, 1, &mmCGTT_SQG_CLK_CTRL[0], sizeof(mmCGTT_SQG_CLK_CTRL)/sizeof(mmCGTT_SQG_CLK_CTRL[0]), 0, 0 }, + { "mmSQ_ALU_CLK_CTRL", REG_MMIO, 0x508e, 1, &mmSQ_ALU_CLK_CTRL[0], sizeof(mmSQ_ALU_CLK_CTRL)/sizeof(mmSQ_ALU_CLK_CTRL[0]), 0, 0 }, + { "mmSQ_TEX_CLK_CTRL", REG_MMIO, 0x508f, 1, &mmSQ_TEX_CLK_CTRL[0], sizeof(mmSQ_TEX_CLK_CTRL)/sizeof(mmSQ_TEX_CLK_CTRL[0]), 0, 0 }, + { "mmSQ_LDS_CLK_CTRL", REG_MMIO, 0x5090, 1, &mmSQ_LDS_CLK_CTRL[0], sizeof(mmSQ_LDS_CLK_CTRL)/sizeof(mmSQ_LDS_CLK_CTRL[0]), 0, 0 }, + { "mmSQ_POWER_THROTTLE", REG_MMIO, 0x5091, 1, &mmSQ_POWER_THROTTLE[0], sizeof(mmSQ_POWER_THROTTLE)/sizeof(mmSQ_POWER_THROTTLE[0]), 0, 0 }, + { "mmSQ_POWER_THROTTLE2", REG_MMIO, 0x5092, 1, &mmSQ_POWER_THROTTLE2[0], sizeof(mmSQ_POWER_THROTTLE2)/sizeof(mmSQ_POWER_THROTTLE2[0]), 0, 0 }, + { "mmCGTT_SX_CLK_CTRL0", REG_MMIO, 0x5094, 1, &mmCGTT_SX_CLK_CTRL0[0], sizeof(mmCGTT_SX_CLK_CTRL0)/sizeof(mmCGTT_SX_CLK_CTRL0[0]), 0, 0 }, + { "mmCGTT_SX_CLK_CTRL1", REG_MMIO, 0x5095, 1, &mmCGTT_SX_CLK_CTRL1[0], sizeof(mmCGTT_SX_CLK_CTRL1)/sizeof(mmCGTT_SX_CLK_CTRL1[0]), 0, 0 }, + { "mmCGTT_SX_CLK_CTRL2", REG_MMIO, 0x5096, 1, &mmCGTT_SX_CLK_CTRL2[0], sizeof(mmCGTT_SX_CLK_CTRL2)/sizeof(mmCGTT_SX_CLK_CTRL2[0]), 0, 0 }, + { "mmCGTT_SX_CLK_CTRL3", REG_MMIO, 0x5097, 1, &mmCGTT_SX_CLK_CTRL3[0], sizeof(mmCGTT_SX_CLK_CTRL3)/sizeof(mmCGTT_SX_CLK_CTRL3[0]), 0, 0 }, + { "mmCGTT_SX_CLK_CTRL4", REG_MMIO, 0x5098, 1, &mmCGTT_SX_CLK_CTRL4[0], sizeof(mmCGTT_SX_CLK_CTRL4)/sizeof(mmCGTT_SX_CLK_CTRL4[0]), 0, 0 }, + { "mmTD_CGTT_CTRL", REG_MMIO, 0x509c, 1, &mmTD_CGTT_CTRL[0], sizeof(mmTD_CGTT_CTRL)/sizeof(mmTD_CGTT_CTRL[0]), 0, 0 }, + { "mmTA_CGTT_CTRL", REG_MMIO, 0x509d, 1, &mmTA_CGTT_CTRL[0], sizeof(mmTA_CGTT_CTRL)/sizeof(mmTA_CGTT_CTRL[0]), 0, 0 }, + { "mmCGTT_TCPI_CLK_CTRL", REG_MMIO, 0x509e, 1, &mmCGTT_TCPI_CLK_CTRL[0], sizeof(mmCGTT_TCPI_CLK_CTRL)/sizeof(mmCGTT_TCPI_CLK_CTRL[0]), 0, 0 }, + { "mmCGTT_TCI_CLK_CTRL", REG_MMIO, 0x509f, 1, &mmCGTT_TCI_CLK_CTRL[0], sizeof(mmCGTT_TCI_CLK_CTRL)/sizeof(mmCGTT_TCI_CLK_CTRL[0]), 0, 0 }, + { "mmCGTT_GDS_CLK_CTRL", REG_MMIO, 0x50a0, 1, &mmCGTT_GDS_CLK_CTRL[0], sizeof(mmCGTT_GDS_CLK_CTRL)/sizeof(mmCGTT_GDS_CLK_CTRL[0]), 0, 0 }, + { "mmDB_CGTT_CLK_CTRL_0", REG_MMIO, 0x50a4, 1, &mmDB_CGTT_CLK_CTRL_0[0], sizeof(mmDB_CGTT_CLK_CTRL_0)/sizeof(mmDB_CGTT_CLK_CTRL_0[0]), 0, 0 }, + { "mmCB_CGTT_SCLK_CTRL", REG_MMIO, 0x50a8, 1, &mmCB_CGTT_SCLK_CTRL[0], sizeof(mmCB_CGTT_SCLK_CTRL)/sizeof(mmCB_CGTT_SCLK_CTRL[0]), 0, 0 }, + { "mmTCC_CGTT_SCLK_CTRL", REG_MMIO, 0x50ac, 1, &mmTCC_CGTT_SCLK_CTRL[0], sizeof(mmTCC_CGTT_SCLK_CTRL)/sizeof(mmTCC_CGTT_SCLK_CTRL[0]), 0, 0 }, + { "mmTCA_CGTT_SCLK_CTRL", REG_MMIO, 0x50ad, 1, &mmTCA_CGTT_SCLK_CTRL[0], sizeof(mmTCA_CGTT_SCLK_CTRL)/sizeof(mmTCA_CGTT_SCLK_CTRL[0]), 0, 0 }, + { "mmCGTT_CP_CLK_CTRL", REG_MMIO, 0x50b0, 1, &mmCGTT_CP_CLK_CTRL[0], sizeof(mmCGTT_CP_CLK_CTRL)/sizeof(mmCGTT_CP_CLK_CTRL[0]), 0, 0 }, + { "mmCGTT_CPF_CLK_CTRL", REG_MMIO, 0x50b1, 1, &mmCGTT_CPF_CLK_CTRL[0], sizeof(mmCGTT_CPF_CLK_CTRL)/sizeof(mmCGTT_CPF_CLK_CTRL[0]), 0, 0 }, + { "mmCGTT_CPC_CLK_CTRL", REG_MMIO, 0x50b2, 1, &mmCGTT_CPC_CLK_CTRL[0], sizeof(mmCGTT_CPC_CLK_CTRL)/sizeof(mmCGTT_CPC_CLK_CTRL[0]), 0, 0 }, + { "mmRLC_PWR_CTRL", REG_MMIO, 0x50b4, 1, &mmRLC_PWR_CTRL[0], sizeof(mmRLC_PWR_CTRL)/sizeof(mmRLC_PWR_CTRL[0]), 0, 0 }, + { "mmCGTT_RLC_CLK_CTRL", REG_MMIO, 0x50b5, 1, &mmCGTT_RLC_CLK_CTRL[0], sizeof(mmCGTT_RLC_CLK_CTRL)/sizeof(mmCGTT_RLC_CLK_CTRL[0]), 0, 0 }, + { "mmRLC_GFX_RM_CNTL", REG_MMIO, 0x50b6, 1, &mmRLC_GFX_RM_CNTL[0], sizeof(mmRLC_GFX_RM_CNTL)/sizeof(mmRLC_GFX_RM_CNTL[0]), 0, 0 }, + { "mmRMI_CGTT_SCLK_CTRL", REG_MMIO, 0x50c0, 1, &mmRMI_CGTT_SCLK_CTRL[0], sizeof(mmRMI_CGTT_SCLK_CTRL)/sizeof(mmRMI_CGTT_SCLK_CTRL[0]), 0, 0 }, + { "mmCGTT_TCPF_CLK_CTRL", REG_MMIO, 0x50c1, 1, &mmCGTT_TCPF_CLK_CTRL[0], sizeof(mmCGTT_TCPF_CLK_CTRL)/sizeof(mmCGTT_TCPF_CLK_CTRL[0]), 0, 0 }, + { "mmGCEA_CGTT_CLK_CTRL", REG_MMIO, 0x50c4, 1, &mmGCEA_CGTT_CLK_CTRL[0], sizeof(mmGCEA_CGTT_CLK_CTRL)/sizeof(mmGCEA_CGTT_CLK_CTRL[0]), 0, 0 }, + { "mmMC_VM_FB_SIZE_OFFSET_VF0", REG_MMIO, 0x5a80, 1, &mmMC_VM_FB_SIZE_OFFSET_VF0[0], sizeof(mmMC_VM_FB_SIZE_OFFSET_VF0)/sizeof(mmMC_VM_FB_SIZE_OFFSET_VF0[0]), 0, 0 }, + { "mmMC_VM_FB_SIZE_OFFSET_VF1", REG_MMIO, 0x5a81, 1, &mmMC_VM_FB_SIZE_OFFSET_VF1[0], sizeof(mmMC_VM_FB_SIZE_OFFSET_VF1)/sizeof(mmMC_VM_FB_SIZE_OFFSET_VF1[0]), 0, 0 }, + { "mmMC_VM_FB_SIZE_OFFSET_VF2", REG_MMIO, 0x5a82, 1, &mmMC_VM_FB_SIZE_OFFSET_VF2[0], sizeof(mmMC_VM_FB_SIZE_OFFSET_VF2)/sizeof(mmMC_VM_FB_SIZE_OFFSET_VF2[0]), 0, 0 }, + { "mmMC_VM_FB_SIZE_OFFSET_VF3", REG_MMIO, 0x5a83, 1, &mmMC_VM_FB_SIZE_OFFSET_VF3[0], sizeof(mmMC_VM_FB_SIZE_OFFSET_VF3)/sizeof(mmMC_VM_FB_SIZE_OFFSET_VF3[0]), 0, 0 }, + { "mmMC_VM_FB_SIZE_OFFSET_VF4", REG_MMIO, 0x5a84, 1, &mmMC_VM_FB_SIZE_OFFSET_VF4[0], sizeof(mmMC_VM_FB_SIZE_OFFSET_VF4)/sizeof(mmMC_VM_FB_SIZE_OFFSET_VF4[0]), 0, 0 }, + { "mmMC_VM_FB_SIZE_OFFSET_VF5", REG_MMIO, 0x5a85, 1, &mmMC_VM_FB_SIZE_OFFSET_VF5[0], sizeof(mmMC_VM_FB_SIZE_OFFSET_VF5)/sizeof(mmMC_VM_FB_SIZE_OFFSET_VF5[0]), 0, 0 }, + { "mmMC_VM_FB_SIZE_OFFSET_VF6", REG_MMIO, 0x5a86, 1, &mmMC_VM_FB_SIZE_OFFSET_VF6[0], sizeof(mmMC_VM_FB_SIZE_OFFSET_VF6)/sizeof(mmMC_VM_FB_SIZE_OFFSET_VF6[0]), 0, 0 }, + { "mmMC_VM_FB_SIZE_OFFSET_VF7", REG_MMIO, 0x5a87, 1, &mmMC_VM_FB_SIZE_OFFSET_VF7[0], sizeof(mmMC_VM_FB_SIZE_OFFSET_VF7)/sizeof(mmMC_VM_FB_SIZE_OFFSET_VF7[0]), 0, 0 }, + { "mmMC_VM_FB_SIZE_OFFSET_VF8", REG_MMIO, 0x5a88, 1, &mmMC_VM_FB_SIZE_OFFSET_VF8[0], sizeof(mmMC_VM_FB_SIZE_OFFSET_VF8)/sizeof(mmMC_VM_FB_SIZE_OFFSET_VF8[0]), 0, 0 }, + { "mmMC_VM_FB_SIZE_OFFSET_VF9", REG_MMIO, 0x5a89, 1, &mmMC_VM_FB_SIZE_OFFSET_VF9[0], sizeof(mmMC_VM_FB_SIZE_OFFSET_VF9)/sizeof(mmMC_VM_FB_SIZE_OFFSET_VF9[0]), 0, 0 }, + { "mmMC_VM_FB_SIZE_OFFSET_VF10", REG_MMIO, 0x5a8a, 1, &mmMC_VM_FB_SIZE_OFFSET_VF10[0], sizeof(mmMC_VM_FB_SIZE_OFFSET_VF10)/sizeof(mmMC_VM_FB_SIZE_OFFSET_VF10[0]), 0, 0 }, + { "mmMC_VM_FB_SIZE_OFFSET_VF11", REG_MMIO, 0x5a8b, 1, &mmMC_VM_FB_SIZE_OFFSET_VF11[0], sizeof(mmMC_VM_FB_SIZE_OFFSET_VF11)/sizeof(mmMC_VM_FB_SIZE_OFFSET_VF11[0]), 0, 0 }, + { "mmMC_VM_FB_SIZE_OFFSET_VF12", REG_MMIO, 0x5a8c, 1, &mmMC_VM_FB_SIZE_OFFSET_VF12[0], sizeof(mmMC_VM_FB_SIZE_OFFSET_VF12)/sizeof(mmMC_VM_FB_SIZE_OFFSET_VF12[0]), 0, 0 }, + { "mmMC_VM_FB_SIZE_OFFSET_VF13", REG_MMIO, 0x5a8d, 1, &mmMC_VM_FB_SIZE_OFFSET_VF13[0], sizeof(mmMC_VM_FB_SIZE_OFFSET_VF13)/sizeof(mmMC_VM_FB_SIZE_OFFSET_VF13[0]), 0, 0 }, + { "mmMC_VM_FB_SIZE_OFFSET_VF14", REG_MMIO, 0x5a8e, 1, &mmMC_VM_FB_SIZE_OFFSET_VF14[0], sizeof(mmMC_VM_FB_SIZE_OFFSET_VF14)/sizeof(mmMC_VM_FB_SIZE_OFFSET_VF14[0]), 0, 0 }, + { "mmMC_VM_FB_SIZE_OFFSET_VF15", REG_MMIO, 0x5a8f, 1, &mmMC_VM_FB_SIZE_OFFSET_VF15[0], sizeof(mmMC_VM_FB_SIZE_OFFSET_VF15)/sizeof(mmMC_VM_FB_SIZE_OFFSET_VF15[0]), 0, 0 }, + { "mmVM_IOMMU_MMIO_CNTRL_1", REG_MMIO, 0x5a90, 1, &mmVM_IOMMU_MMIO_CNTRL_1[0], sizeof(mmVM_IOMMU_MMIO_CNTRL_1)/sizeof(mmVM_IOMMU_MMIO_CNTRL_1[0]), 0, 0 }, + { "mmMC_VM_MARC_BASE_LO_0", REG_MMIO, 0x5a91, 1, &mmMC_VM_MARC_BASE_LO_0[0], sizeof(mmMC_VM_MARC_BASE_LO_0)/sizeof(mmMC_VM_MARC_BASE_LO_0[0]), 0, 0 }, + { "mmMC_VM_MARC_BASE_LO_1", REG_MMIO, 0x5a92, 1, &mmMC_VM_MARC_BASE_LO_1[0], sizeof(mmMC_VM_MARC_BASE_LO_1)/sizeof(mmMC_VM_MARC_BASE_LO_1[0]), 0, 0 }, + { "mmMC_VM_MARC_BASE_LO_2", REG_MMIO, 0x5a93, 1, &mmMC_VM_MARC_BASE_LO_2[0], sizeof(mmMC_VM_MARC_BASE_LO_2)/sizeof(mmMC_VM_MARC_BASE_LO_2[0]), 0, 0 }, + { "mmMC_VM_MARC_BASE_LO_3", REG_MMIO, 0x5a94, 1, &mmMC_VM_MARC_BASE_LO_3[0], sizeof(mmMC_VM_MARC_BASE_LO_3)/sizeof(mmMC_VM_MARC_BASE_LO_3[0]), 0, 0 }, + { "mmMC_VM_MARC_BASE_HI_0", REG_MMIO, 0x5a95, 1, &mmMC_VM_MARC_BASE_HI_0[0], sizeof(mmMC_VM_MARC_BASE_HI_0)/sizeof(mmMC_VM_MARC_BASE_HI_0[0]), 0, 0 }, + { "mmMC_VM_MARC_BASE_HI_1", REG_MMIO, 0x5a96, 1, &mmMC_VM_MARC_BASE_HI_1[0], sizeof(mmMC_VM_MARC_BASE_HI_1)/sizeof(mmMC_VM_MARC_BASE_HI_1[0]), 0, 0 }, + { "mmMC_VM_MARC_BASE_HI_2", REG_MMIO, 0x5a97, 1, &mmMC_VM_MARC_BASE_HI_2[0], sizeof(mmMC_VM_MARC_BASE_HI_2)/sizeof(mmMC_VM_MARC_BASE_HI_2[0]), 0, 0 }, + { "mmMC_VM_MARC_BASE_HI_3", REG_MMIO, 0x5a98, 1, &mmMC_VM_MARC_BASE_HI_3[0], sizeof(mmMC_VM_MARC_BASE_HI_3)/sizeof(mmMC_VM_MARC_BASE_HI_3[0]), 0, 0 }, + { "mmMC_VM_MARC_RELOC_LO_0", REG_MMIO, 0x5a99, 1, &mmMC_VM_MARC_RELOC_LO_0[0], sizeof(mmMC_VM_MARC_RELOC_LO_0)/sizeof(mmMC_VM_MARC_RELOC_LO_0[0]), 0, 0 }, + { "mmMC_VM_MARC_RELOC_LO_1", REG_MMIO, 0x5a9a, 1, &mmMC_VM_MARC_RELOC_LO_1[0], sizeof(mmMC_VM_MARC_RELOC_LO_1)/sizeof(mmMC_VM_MARC_RELOC_LO_1[0]), 0, 0 }, + { "mmMC_VM_MARC_RELOC_LO_2", REG_MMIO, 0x5a9b, 1, &mmMC_VM_MARC_RELOC_LO_2[0], sizeof(mmMC_VM_MARC_RELOC_LO_2)/sizeof(mmMC_VM_MARC_RELOC_LO_2[0]), 0, 0 }, + { "mmMC_VM_MARC_RELOC_LO_3", REG_MMIO, 0x5a9c, 1, &mmMC_VM_MARC_RELOC_LO_3[0], sizeof(mmMC_VM_MARC_RELOC_LO_3)/sizeof(mmMC_VM_MARC_RELOC_LO_3[0]), 0, 0 }, + { "mmMC_VM_MARC_RELOC_HI_0", REG_MMIO, 0x5a9d, 1, &mmMC_VM_MARC_RELOC_HI_0[0], sizeof(mmMC_VM_MARC_RELOC_HI_0)/sizeof(mmMC_VM_MARC_RELOC_HI_0[0]), 0, 0 }, + { "mmMC_VM_MARC_RELOC_HI_1", REG_MMIO, 0x5a9e, 1, &mmMC_VM_MARC_RELOC_HI_1[0], sizeof(mmMC_VM_MARC_RELOC_HI_1)/sizeof(mmMC_VM_MARC_RELOC_HI_1[0]), 0, 0 }, + { "mmMC_VM_MARC_RELOC_HI_2", REG_MMIO, 0x5a9f, 1, &mmMC_VM_MARC_RELOC_HI_2[0], sizeof(mmMC_VM_MARC_RELOC_HI_2)/sizeof(mmMC_VM_MARC_RELOC_HI_2[0]), 0, 0 }, + { "mmMC_VM_MARC_RELOC_HI_3", REG_MMIO, 0x5aa0, 1, &mmMC_VM_MARC_RELOC_HI_3[0], sizeof(mmMC_VM_MARC_RELOC_HI_3)/sizeof(mmMC_VM_MARC_RELOC_HI_3[0]), 0, 0 }, + { "mmMC_VM_MARC_LEN_LO_0", REG_MMIO, 0x5aa1, 1, &mmMC_VM_MARC_LEN_LO_0[0], sizeof(mmMC_VM_MARC_LEN_LO_0)/sizeof(mmMC_VM_MARC_LEN_LO_0[0]), 0, 0 }, + { "mmMC_VM_MARC_LEN_LO_1", REG_MMIO, 0x5aa2, 1, &mmMC_VM_MARC_LEN_LO_1[0], sizeof(mmMC_VM_MARC_LEN_LO_1)/sizeof(mmMC_VM_MARC_LEN_LO_1[0]), 0, 0 }, + { "mmMC_VM_MARC_LEN_LO_2", REG_MMIO, 0x5aa3, 1, &mmMC_VM_MARC_LEN_LO_2[0], sizeof(mmMC_VM_MARC_LEN_LO_2)/sizeof(mmMC_VM_MARC_LEN_LO_2[0]), 0, 0 }, + { "mmMC_VM_MARC_LEN_LO_3", REG_MMIO, 0x5aa4, 1, &mmMC_VM_MARC_LEN_LO_3[0], sizeof(mmMC_VM_MARC_LEN_LO_3)/sizeof(mmMC_VM_MARC_LEN_LO_3[0]), 0, 0 }, + { "mmMC_VM_MARC_LEN_HI_0", REG_MMIO, 0x5aa5, 1, &mmMC_VM_MARC_LEN_HI_0[0], sizeof(mmMC_VM_MARC_LEN_HI_0)/sizeof(mmMC_VM_MARC_LEN_HI_0[0]), 0, 0 }, + { "mmMC_VM_MARC_LEN_HI_1", REG_MMIO, 0x5aa6, 1, &mmMC_VM_MARC_LEN_HI_1[0], sizeof(mmMC_VM_MARC_LEN_HI_1)/sizeof(mmMC_VM_MARC_LEN_HI_1[0]), 0, 0 }, + { "mmMC_VM_MARC_LEN_HI_2", REG_MMIO, 0x5aa7, 1, &mmMC_VM_MARC_LEN_HI_2[0], sizeof(mmMC_VM_MARC_LEN_HI_2)/sizeof(mmMC_VM_MARC_LEN_HI_2[0]), 0, 0 }, + { "mmMC_VM_MARC_LEN_HI_3", REG_MMIO, 0x5aa8, 1, &mmMC_VM_MARC_LEN_HI_3[0], sizeof(mmMC_VM_MARC_LEN_HI_3)/sizeof(mmMC_VM_MARC_LEN_HI_3[0]), 0, 0 }, + { "mmVM_IOMMU_CONTROL_REGISTER", REG_MMIO, 0x5aa9, 1, &mmVM_IOMMU_CONTROL_REGISTER[0], sizeof(mmVM_IOMMU_CONTROL_REGISTER)/sizeof(mmVM_IOMMU_CONTROL_REGISTER[0]), 0, 0 }, + { "mmVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER", REG_MMIO, 0x5aaa, 1, &mmVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER[0], sizeof(mmVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER)/sizeof(mmVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER[0]), 0, 0 }, + { "mmVM_PCIE_ATS_CNTL", REG_MMIO, 0x5aab, 1, &mmVM_PCIE_ATS_CNTL[0], sizeof(mmVM_PCIE_ATS_CNTL)/sizeof(mmVM_PCIE_ATS_CNTL[0]), 0, 0 }, + { "mmVM_PCIE_ATS_CNTL_VF_0", REG_MMIO, 0x5aac, 1, &mmVM_PCIE_ATS_CNTL_VF_0[0], sizeof(mmVM_PCIE_ATS_CNTL_VF_0)/sizeof(mmVM_PCIE_ATS_CNTL_VF_0[0]), 0, 0 }, + { "mmVM_PCIE_ATS_CNTL_VF_1", REG_MMIO, 0x5aad, 1, &mmVM_PCIE_ATS_CNTL_VF_1[0], sizeof(mmVM_PCIE_ATS_CNTL_VF_1)/sizeof(mmVM_PCIE_ATS_CNTL_VF_1[0]), 0, 0 }, + { "mmVM_PCIE_ATS_CNTL_VF_2", REG_MMIO, 0x5aae, 1, &mmVM_PCIE_ATS_CNTL_VF_2[0], sizeof(mmVM_PCIE_ATS_CNTL_VF_2)/sizeof(mmVM_PCIE_ATS_CNTL_VF_2[0]), 0, 0 }, + { "mmVM_PCIE_ATS_CNTL_VF_3", REG_MMIO, 0x5aaf, 1, &mmVM_PCIE_ATS_CNTL_VF_3[0], sizeof(mmVM_PCIE_ATS_CNTL_VF_3)/sizeof(mmVM_PCIE_ATS_CNTL_VF_3[0]), 0, 0 }, + { "mmVM_PCIE_ATS_CNTL_VF_4", REG_MMIO, 0x5ab0, 1, &mmVM_PCIE_ATS_CNTL_VF_4[0], sizeof(mmVM_PCIE_ATS_CNTL_VF_4)/sizeof(mmVM_PCIE_ATS_CNTL_VF_4[0]), 0, 0 }, + { "mmVM_PCIE_ATS_CNTL_VF_5", REG_MMIO, 0x5ab1, 1, &mmVM_PCIE_ATS_CNTL_VF_5[0], sizeof(mmVM_PCIE_ATS_CNTL_VF_5)/sizeof(mmVM_PCIE_ATS_CNTL_VF_5[0]), 0, 0 }, + { "mmVM_PCIE_ATS_CNTL_VF_6", REG_MMIO, 0x5ab2, 1, &mmVM_PCIE_ATS_CNTL_VF_6[0], sizeof(mmVM_PCIE_ATS_CNTL_VF_6)/sizeof(mmVM_PCIE_ATS_CNTL_VF_6[0]), 0, 0 }, + { "mmVM_PCIE_ATS_CNTL_VF_7", REG_MMIO, 0x5ab3, 1, &mmVM_PCIE_ATS_CNTL_VF_7[0], sizeof(mmVM_PCIE_ATS_CNTL_VF_7)/sizeof(mmVM_PCIE_ATS_CNTL_VF_7[0]), 0, 0 }, + { "mmVM_PCIE_ATS_CNTL_VF_8", REG_MMIO, 0x5ab4, 1, &mmVM_PCIE_ATS_CNTL_VF_8[0], sizeof(mmVM_PCIE_ATS_CNTL_VF_8)/sizeof(mmVM_PCIE_ATS_CNTL_VF_8[0]), 0, 0 }, + { "mmVM_PCIE_ATS_CNTL_VF_9", REG_MMIO, 0x5ab5, 1, &mmVM_PCIE_ATS_CNTL_VF_9[0], sizeof(mmVM_PCIE_ATS_CNTL_VF_9)/sizeof(mmVM_PCIE_ATS_CNTL_VF_9[0]), 0, 0 }, + { "mmVM_PCIE_ATS_CNTL_VF_10", REG_MMIO, 0x5ab6, 1, &mmVM_PCIE_ATS_CNTL_VF_10[0], sizeof(mmVM_PCIE_ATS_CNTL_VF_10)/sizeof(mmVM_PCIE_ATS_CNTL_VF_10[0]), 0, 0 }, + { "mmVM_PCIE_ATS_CNTL_VF_11", REG_MMIO, 0x5ab7, 1, &mmVM_PCIE_ATS_CNTL_VF_11[0], sizeof(mmVM_PCIE_ATS_CNTL_VF_11)/sizeof(mmVM_PCIE_ATS_CNTL_VF_11[0]), 0, 0 }, + { "mmVM_PCIE_ATS_CNTL_VF_12", REG_MMIO, 0x5ab8, 1, &mmVM_PCIE_ATS_CNTL_VF_12[0], sizeof(mmVM_PCIE_ATS_CNTL_VF_12)/sizeof(mmVM_PCIE_ATS_CNTL_VF_12[0]), 0, 0 }, + { "mmVM_PCIE_ATS_CNTL_VF_13", REG_MMIO, 0x5ab9, 1, &mmVM_PCIE_ATS_CNTL_VF_13[0], sizeof(mmVM_PCIE_ATS_CNTL_VF_13)/sizeof(mmVM_PCIE_ATS_CNTL_VF_13[0]), 0, 0 }, + { "mmVM_PCIE_ATS_CNTL_VF_14", REG_MMIO, 0x5aba, 1, &mmVM_PCIE_ATS_CNTL_VF_14[0], sizeof(mmVM_PCIE_ATS_CNTL_VF_14)/sizeof(mmVM_PCIE_ATS_CNTL_VF_14[0]), 0, 0 }, + { "mmVM_PCIE_ATS_CNTL_VF_15", REG_MMIO, 0x5abb, 1, &mmVM_PCIE_ATS_CNTL_VF_15[0], sizeof(mmVM_PCIE_ATS_CNTL_VF_15)/sizeof(mmVM_PCIE_ATS_CNTL_VF_15[0]), 0, 0 }, + { "mmUTCL2_CGTT_CLK_CTRL", REG_MMIO, 0x5abc, 1, &mmUTCL2_CGTT_CLK_CTRL[0], sizeof(mmUTCL2_CGTT_CLK_CTRL)/sizeof(mmUTCL2_CGTT_CLK_CTRL[0]), 0, 0 }, + { "mmCP_HYP_PFP_UCODE_ADDR", REG_MMIO, 0x5814, 1, &mmCP_HYP_PFP_UCODE_ADDR[0], sizeof(mmCP_HYP_PFP_UCODE_ADDR)/sizeof(mmCP_HYP_PFP_UCODE_ADDR[0]), 0, 0 }, + { "mmCP_PFP_UCODE_ADDR", REG_MMIO, 0x5814, 1, &mmCP_PFP_UCODE_ADDR[0], sizeof(mmCP_PFP_UCODE_ADDR)/sizeof(mmCP_PFP_UCODE_ADDR[0]), 0, 0 }, + { "mmCP_HYP_PFP_UCODE_DATA", REG_MMIO, 0x5815, 1, &mmCP_HYP_PFP_UCODE_DATA[0], sizeof(mmCP_HYP_PFP_UCODE_DATA)/sizeof(mmCP_HYP_PFP_UCODE_DATA[0]), 0, 0 }, + { "mmCP_PFP_UCODE_DATA", REG_MMIO, 0x5815, 1, &mmCP_PFP_UCODE_DATA[0], sizeof(mmCP_PFP_UCODE_DATA)/sizeof(mmCP_PFP_UCODE_DATA[0]), 0, 0 }, + { "mmCP_HYP_ME_UCODE_ADDR", REG_MMIO, 0x5816, 1, &mmCP_HYP_ME_UCODE_ADDR[0], sizeof(mmCP_HYP_ME_UCODE_ADDR)/sizeof(mmCP_HYP_ME_UCODE_ADDR[0]), 0, 0 }, + { "mmCP_ME_RAM_RADDR", REG_MMIO, 0x5816, 1, &mmCP_ME_RAM_RADDR[0], sizeof(mmCP_ME_RAM_RADDR)/sizeof(mmCP_ME_RAM_RADDR[0]), 0, 0 }, + { "mmCP_ME_RAM_WADDR", REG_MMIO, 0x5816, 1, &mmCP_ME_RAM_WADDR[0], sizeof(mmCP_ME_RAM_WADDR)/sizeof(mmCP_ME_RAM_WADDR[0]), 0, 0 }, + { "mmCP_HYP_ME_UCODE_DATA", REG_MMIO, 0x5817, 1, &mmCP_HYP_ME_UCODE_DATA[0], sizeof(mmCP_HYP_ME_UCODE_DATA)/sizeof(mmCP_HYP_ME_UCODE_DATA[0]), 0, 0 }, + { "mmCP_ME_RAM_DATA", REG_MMIO, 0x5817, 1, &mmCP_ME_RAM_DATA[0], sizeof(mmCP_ME_RAM_DATA)/sizeof(mmCP_ME_RAM_DATA[0]), 0, 0 }, + { "mmCP_CE_UCODE_ADDR", REG_MMIO, 0x5818, 1, &mmCP_CE_UCODE_ADDR[0], sizeof(mmCP_CE_UCODE_ADDR)/sizeof(mmCP_CE_UCODE_ADDR[0]), 0, 0 }, + { "mmCP_HYP_CE_UCODE_ADDR", REG_MMIO, 0x5818, 1, &mmCP_HYP_CE_UCODE_ADDR[0], sizeof(mmCP_HYP_CE_UCODE_ADDR)/sizeof(mmCP_HYP_CE_UCODE_ADDR[0]), 0, 0 }, + { "mmCP_CE_UCODE_DATA", REG_MMIO, 0x5819, 1, &mmCP_CE_UCODE_DATA[0], sizeof(mmCP_CE_UCODE_DATA)/sizeof(mmCP_CE_UCODE_DATA[0]), 0, 0 }, + { "mmCP_HYP_CE_UCODE_DATA", REG_MMIO, 0x5819, 1, &mmCP_HYP_CE_UCODE_DATA[0], sizeof(mmCP_HYP_CE_UCODE_DATA)/sizeof(mmCP_HYP_CE_UCODE_DATA[0]), 0, 0 }, + { "mmCP_HYP_MEC1_UCODE_ADDR", REG_MMIO, 0x581a, 1, &mmCP_HYP_MEC1_UCODE_ADDR[0], sizeof(mmCP_HYP_MEC1_UCODE_ADDR)/sizeof(mmCP_HYP_MEC1_UCODE_ADDR[0]), 0, 0 }, + { "mmCP_MEC_ME1_UCODE_ADDR", REG_MMIO, 0x581a, 1, &mmCP_MEC_ME1_UCODE_ADDR[0], sizeof(mmCP_MEC_ME1_UCODE_ADDR)/sizeof(mmCP_MEC_ME1_UCODE_ADDR[0]), 0, 0 }, + { "mmCP_HYP_MEC1_UCODE_DATA", REG_MMIO, 0x581b, 1, &mmCP_HYP_MEC1_UCODE_DATA[0], sizeof(mmCP_HYP_MEC1_UCODE_DATA)/sizeof(mmCP_HYP_MEC1_UCODE_DATA[0]), 0, 0 }, + { "mmCP_MEC_ME1_UCODE_DATA", REG_MMIO, 0x581b, 1, &mmCP_MEC_ME1_UCODE_DATA[0], sizeof(mmCP_MEC_ME1_UCODE_DATA)/sizeof(mmCP_MEC_ME1_UCODE_DATA[0]), 0, 0 }, + { "mmCP_HYP_MEC2_UCODE_ADDR", REG_MMIO, 0x581c, 1, &mmCP_HYP_MEC2_UCODE_ADDR[0], sizeof(mmCP_HYP_MEC2_UCODE_ADDR)/sizeof(mmCP_HYP_MEC2_UCODE_ADDR[0]), 0, 0 }, + { "mmCP_MEC_ME2_UCODE_ADDR", REG_MMIO, 0x581c, 1, &mmCP_MEC_ME2_UCODE_ADDR[0], sizeof(mmCP_MEC_ME2_UCODE_ADDR)/sizeof(mmCP_MEC_ME2_UCODE_ADDR[0]), 0, 0 }, + { "mmCP_HYP_MEC2_UCODE_DATA", REG_MMIO, 0x581d, 1, &mmCP_HYP_MEC2_UCODE_DATA[0], sizeof(mmCP_HYP_MEC2_UCODE_DATA)/sizeof(mmCP_HYP_MEC2_UCODE_DATA[0]), 0, 0 }, + { "mmCP_MEC_ME2_UCODE_DATA", REG_MMIO, 0x581d, 1, &mmCP_MEC_ME2_UCODE_DATA[0], sizeof(mmCP_MEC_ME2_UCODE_DATA)/sizeof(mmCP_MEC_ME2_UCODE_DATA[0]), 0, 0 }, + { "mmRLC_GPM_UCODE_ADDR", REG_MMIO, 0x583c, 1, &mmRLC_GPM_UCODE_ADDR[0], sizeof(mmRLC_GPM_UCODE_ADDR)/sizeof(mmRLC_GPM_UCODE_ADDR[0]), 0, 0 }, + { "mmRLC_GPM_UCODE_DATA", REG_MMIO, 0x583d, 1, &mmRLC_GPM_UCODE_DATA[0], sizeof(mmRLC_GPM_UCODE_DATA)/sizeof(mmRLC_GPM_UCODE_DATA[0]), 0, 0 }, + { "mmGRBM_GFX_INDEX_SR_SELECT", REG_MMIO, 0x5a00, 1, &mmGRBM_GFX_INDEX_SR_SELECT[0], sizeof(mmGRBM_GFX_INDEX_SR_SELECT)/sizeof(mmGRBM_GFX_INDEX_SR_SELECT[0]), 0, 0 }, + { "mmGRBM_GFX_INDEX_SR_DATA", REG_MMIO, 0x5a01, 1, &mmGRBM_GFX_INDEX_SR_DATA[0], sizeof(mmGRBM_GFX_INDEX_SR_DATA)/sizeof(mmGRBM_GFX_INDEX_SR_DATA[0]), 0, 0 }, + { "mmGRBM_GFX_CNTL_SR_SELECT", REG_MMIO, 0x5a02, 1, &mmGRBM_GFX_CNTL_SR_SELECT[0], sizeof(mmGRBM_GFX_CNTL_SR_SELECT)/sizeof(mmGRBM_GFX_CNTL_SR_SELECT[0]), 0, 0 }, + { "mmGRBM_GFX_CNTL_SR_DATA", REG_MMIO, 0x5a03, 1, &mmGRBM_GFX_CNTL_SR_DATA[0], sizeof(mmGRBM_GFX_CNTL_SR_DATA)/sizeof(mmGRBM_GFX_CNTL_SR_DATA[0]), 0, 0 }, + { "mmGRBM_CAM_INDEX", REG_MMIO, 0x5a04, 1, &mmGRBM_CAM_INDEX[0], sizeof(mmGRBM_CAM_INDEX)/sizeof(mmGRBM_CAM_INDEX[0]), 0, 0 }, + { "mmGRBM_HYP_CAM_INDEX", REG_MMIO, 0x5a04, 1, &mmGRBM_HYP_CAM_INDEX[0], sizeof(mmGRBM_HYP_CAM_INDEX)/sizeof(mmGRBM_HYP_CAM_INDEX[0]), 0, 0 }, + { "mmGRBM_CAM_DATA", REG_MMIO, 0x5a05, 1, &mmGRBM_CAM_DATA[0], sizeof(mmGRBM_CAM_DATA)/sizeof(mmGRBM_CAM_DATA[0]), 0, 0 }, + { "mmGRBM_HYP_CAM_DATA", REG_MMIO, 0x5a05, 1, &mmGRBM_HYP_CAM_DATA[0], sizeof(mmGRBM_HYP_CAM_DATA)/sizeof(mmGRBM_HYP_CAM_DATA[0]), 0, 0 }, + { "mmRLC_GPU_IOV_VF_ENABLE", REG_MMIO, 0x5b00, 1, &mmRLC_GPU_IOV_VF_ENABLE[0], sizeof(mmRLC_GPU_IOV_VF_ENABLE)/sizeof(mmRLC_GPU_IOV_VF_ENABLE[0]), 0, 0 }, + { "mmRLC_GFX_RM_CNTL_ADJ", REG_MMIO, 0x5b01, 1, &mmRLC_GFX_RM_CNTL_ADJ[0], sizeof(mmRLC_GFX_RM_CNTL_ADJ)/sizeof(mmRLC_GFX_RM_CNTL_ADJ[0]), 0, 0 }, + { "mmRLC_GPU_IOV_CFG_REG6", REG_MMIO, 0x5b06, 1, &mmRLC_GPU_IOV_CFG_REG6[0], sizeof(mmRLC_GPU_IOV_CFG_REG6)/sizeof(mmRLC_GPU_IOV_CFG_REG6[0]), 0, 0 }, + { "mmRLC_GPU_IOV_CFG_REG8", REG_MMIO, 0x5b20, 1, &mmRLC_GPU_IOV_CFG_REG8[0], sizeof(mmRLC_GPU_IOV_CFG_REG8)/sizeof(mmRLC_GPU_IOV_CFG_REG8[0]), 0, 0 }, + { "mmRLC_RLCV_TIMER_INT_0", REG_MMIO, 0x5b25, 1, &mmRLC_RLCV_TIMER_INT_0[0], sizeof(mmRLC_RLCV_TIMER_INT_0)/sizeof(mmRLC_RLCV_TIMER_INT_0[0]), 0, 0 }, + { "mmRLC_RLCV_TIMER_CTRL", REG_MMIO, 0x5b26, 1, &mmRLC_RLCV_TIMER_CTRL[0], sizeof(mmRLC_RLCV_TIMER_CTRL)/sizeof(mmRLC_RLCV_TIMER_CTRL[0]), 0, 0 }, + { "mmRLC_RLCV_TIMER_STAT", REG_MMIO, 0x5b27, 1, &mmRLC_RLCV_TIMER_STAT[0], sizeof(mmRLC_RLCV_TIMER_STAT)/sizeof(mmRLC_RLCV_TIMER_STAT[0]), 0, 0 }, + { "mmRLC_GPU_IOV_VF_DOORBELL_STATUS", REG_MMIO, 0x5b2a, 1, &mmRLC_GPU_IOV_VF_DOORBELL_STATUS[0], sizeof(mmRLC_GPU_IOV_VF_DOORBELL_STATUS)/sizeof(mmRLC_GPU_IOV_VF_DOORBELL_STATUS[0]), 0, 0 }, + { "mmRLC_GPU_IOV_VF_DOORBELL_STATUS_SET", REG_MMIO, 0x5b2b, 1, &mmRLC_GPU_IOV_VF_DOORBELL_STATUS_SET[0], sizeof(mmRLC_GPU_IOV_VF_DOORBELL_STATUS_SET)/sizeof(mmRLC_GPU_IOV_VF_DOORBELL_STATUS_SET[0]), 0, 0 }, + { "mmRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR", REG_MMIO, 0x5b2c, 1, &mmRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR[0], sizeof(mmRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR)/sizeof(mmRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR[0]), 0, 0 }, + { "mmRLC_GPU_IOV_VF_MASK", REG_MMIO, 0x5b2d, 1, &mmRLC_GPU_IOV_VF_MASK[0], sizeof(mmRLC_GPU_IOV_VF_MASK)/sizeof(mmRLC_GPU_IOV_VF_MASK[0]), 0, 0 }, + { "mmRLC_HYP_SEMAPHORE_2", REG_MMIO, 0x5b2e, 1, &mmRLC_HYP_SEMAPHORE_2[0], sizeof(mmRLC_HYP_SEMAPHORE_2)/sizeof(mmRLC_HYP_SEMAPHORE_2[0]), 0, 0 }, + { "mmRLC_HYP_SEMAPHORE_3", REG_MMIO, 0x5b2f, 1, &mmRLC_HYP_SEMAPHORE_3[0], sizeof(mmRLC_HYP_SEMAPHORE_3)/sizeof(mmRLC_HYP_SEMAPHORE_3[0]), 0, 0 }, + { "mmRLC_CLK_CNTL", REG_MMIO, 0x5b31, 1, &mmRLC_CLK_CNTL[0], sizeof(mmRLC_CLK_CNTL)/sizeof(mmRLC_CLK_CNTL[0]), 0, 0 }, + { "mmRLC_GPU_IOV_SCH_BLOCK", REG_MMIO, 0x5b34, 1, &mmRLC_GPU_IOV_SCH_BLOCK[0], sizeof(mmRLC_GPU_IOV_SCH_BLOCK)/sizeof(mmRLC_GPU_IOV_SCH_BLOCK[0]), 0, 0 }, + { "mmRLC_GPU_IOV_CFG_REG1", REG_MMIO, 0x5b35, 1, &mmRLC_GPU_IOV_CFG_REG1[0], sizeof(mmRLC_GPU_IOV_CFG_REG1)/sizeof(mmRLC_GPU_IOV_CFG_REG1[0]), 0, 0 }, + { "mmRLC_GPU_IOV_CFG_REG2", REG_MMIO, 0x5b36, 1, &mmRLC_GPU_IOV_CFG_REG2[0], sizeof(mmRLC_GPU_IOV_CFG_REG2)/sizeof(mmRLC_GPU_IOV_CFG_REG2[0]), 0, 0 }, + { "mmRLC_GPU_IOV_VM_BUSY_STATUS", REG_MMIO, 0x5b37, 1, &mmRLC_GPU_IOV_VM_BUSY_STATUS[0], sizeof(mmRLC_GPU_IOV_VM_BUSY_STATUS)/sizeof(mmRLC_GPU_IOV_VM_BUSY_STATUS[0]), 0, 0 }, + { "mmRLC_GPU_IOV_SCH_0", REG_MMIO, 0x5b38, 1, &mmRLC_GPU_IOV_SCH_0[0], sizeof(mmRLC_GPU_IOV_SCH_0)/sizeof(mmRLC_GPU_IOV_SCH_0[0]), 0, 0 }, + { "mmRLC_GPU_IOV_ACTIVE_FCN_ID", REG_MMIO, 0x5b39, 1, &mmRLC_GPU_IOV_ACTIVE_FCN_ID[0], sizeof(mmRLC_GPU_IOV_ACTIVE_FCN_ID)/sizeof(mmRLC_GPU_IOV_ACTIVE_FCN_ID[0]), 0, 0 }, + { "mmRLC_GPU_IOV_SCH_3", REG_MMIO, 0x5b3a, 1, &mmRLC_GPU_IOV_SCH_3[0], sizeof(mmRLC_GPU_IOV_SCH_3)/sizeof(mmRLC_GPU_IOV_SCH_3[0]), 0, 0 }, + { "mmRLC_GPU_IOV_SCH_1", REG_MMIO, 0x5b3b, 1, &mmRLC_GPU_IOV_SCH_1[0], sizeof(mmRLC_GPU_IOV_SCH_1)/sizeof(mmRLC_GPU_IOV_SCH_1[0]), 0, 0 }, + { "mmRLC_GPU_IOV_SCH_2", REG_MMIO, 0x5b3c, 1, &mmRLC_GPU_IOV_SCH_2[0], sizeof(mmRLC_GPU_IOV_SCH_2)/sizeof(mmRLC_GPU_IOV_SCH_2[0]), 0, 0 }, + { "mmRLC_GPU_IOV_UCODE_ADDR", REG_MMIO, 0x5b42, 1, &mmRLC_GPU_IOV_UCODE_ADDR[0], sizeof(mmRLC_GPU_IOV_UCODE_ADDR)/sizeof(mmRLC_GPU_IOV_UCODE_ADDR[0]), 0, 0 }, + { "mmRLC_GPU_IOV_UCODE_DATA", REG_MMIO, 0x5b43, 1, &mmRLC_GPU_IOV_UCODE_DATA[0], sizeof(mmRLC_GPU_IOV_UCODE_DATA)/sizeof(mmRLC_GPU_IOV_UCODE_DATA[0]), 0, 0 }, + { "mmRLC_GPU_IOV_SCRATCH_ADDR", REG_MMIO, 0x5b44, 1, &mmRLC_GPU_IOV_SCRATCH_ADDR[0], sizeof(mmRLC_GPU_IOV_SCRATCH_ADDR)/sizeof(mmRLC_GPU_IOV_SCRATCH_ADDR[0]), 0, 0 }, + { "mmRLC_GPU_IOV_SCRATCH_DATA", REG_MMIO, 0x5b45, 1, &mmRLC_GPU_IOV_SCRATCH_DATA[0], sizeof(mmRLC_GPU_IOV_SCRATCH_DATA)/sizeof(mmRLC_GPU_IOV_SCRATCH_DATA[0]), 0, 0 }, + { "mmRLC_GPU_IOV_F32_CNTL", REG_MMIO, 0x5b46, 1, &mmRLC_GPU_IOV_F32_CNTL[0], sizeof(mmRLC_GPU_IOV_F32_CNTL)/sizeof(mmRLC_GPU_IOV_F32_CNTL[0]), 0, 0 }, + { "mmRLC_GPU_IOV_F32_RESET", REG_MMIO, 0x5b47, 1, &mmRLC_GPU_IOV_F32_RESET[0], sizeof(mmRLC_GPU_IOV_F32_RESET)/sizeof(mmRLC_GPU_IOV_F32_RESET[0]), 0, 0 }, + { "mmRLC_GPU_IOV_SDMA0_STATUS", REG_MMIO, 0x5b48, 1, &mmRLC_GPU_IOV_SDMA0_STATUS[0], sizeof(mmRLC_GPU_IOV_SDMA0_STATUS)/sizeof(mmRLC_GPU_IOV_SDMA0_STATUS[0]), 0, 0 }, + { "mmRLC_GPU_IOV_SDMA1_STATUS", REG_MMIO, 0x5b49, 1, &mmRLC_GPU_IOV_SDMA1_STATUS[0], sizeof(mmRLC_GPU_IOV_SDMA1_STATUS)/sizeof(mmRLC_GPU_IOV_SDMA1_STATUS[0]), 0, 0 }, + { "mmRLC_GPU_IOV_SMU_RESPONSE", REG_MMIO, 0x5b4a, 1, &mmRLC_GPU_IOV_SMU_RESPONSE[0], sizeof(mmRLC_GPU_IOV_SMU_RESPONSE)/sizeof(mmRLC_GPU_IOV_SMU_RESPONSE[0]), 0, 0 }, + { "mmRLC_GPU_IOV_VIRT_RESET_REQ", REG_MMIO, 0x5b4c, 1, &mmRLC_GPU_IOV_VIRT_RESET_REQ[0], sizeof(mmRLC_GPU_IOV_VIRT_RESET_REQ)/sizeof(mmRLC_GPU_IOV_VIRT_RESET_REQ[0]), 0, 0 }, + { "mmRLC_GPU_IOV_RLC_RESPONSE", REG_MMIO, 0x5b4d, 1, &mmRLC_GPU_IOV_RLC_RESPONSE[0], sizeof(mmRLC_GPU_IOV_RLC_RESPONSE)/sizeof(mmRLC_GPU_IOV_RLC_RESPONSE[0]), 0, 0 }, + { "mmRLC_GPU_IOV_INT_DISABLE", REG_MMIO, 0x5b4e, 1, &mmRLC_GPU_IOV_INT_DISABLE[0], sizeof(mmRLC_GPU_IOV_INT_DISABLE)/sizeof(mmRLC_GPU_IOV_INT_DISABLE[0]), 0, 0 }, + { "mmRLC_GPU_IOV_INT_FORCE", REG_MMIO, 0x5b4f, 1, &mmRLC_GPU_IOV_INT_FORCE[0], sizeof(mmRLC_GPU_IOV_INT_FORCE)/sizeof(mmRLC_GPU_IOV_INT_FORCE[0]), 0, 0 }, + { "mmRLC_GPU_IOV_SDMA0_BUSY_STATUS", REG_MMIO, 0x5b50, 1, &mmRLC_GPU_IOV_SDMA0_BUSY_STATUS[0], sizeof(mmRLC_GPU_IOV_SDMA0_BUSY_STATUS)/sizeof(mmRLC_GPU_IOV_SDMA0_BUSY_STATUS[0]), 0, 0 }, + { "mmRLC_GPU_IOV_SDMA1_BUSY_STATUS", REG_MMIO, 0x5b51, 1, &mmRLC_GPU_IOV_SDMA1_BUSY_STATUS[0], sizeof(mmRLC_GPU_IOV_SDMA1_BUSY_STATUS)/sizeof(mmRLC_GPU_IOV_SDMA1_BUSY_STATUS[0]), 0, 0 }, + { "ixGC_CAC_CNTL", REG_SMC, 0x0000, 0, &ixGC_CAC_CNTL[0], sizeof(ixGC_CAC_CNTL)/sizeof(ixGC_CAC_CNTL[0]), 0, 0 }, + { "ixGC_CAC_OVR_SEL", REG_SMC, 0x0001, 0, &ixGC_CAC_OVR_SEL[0], sizeof(ixGC_CAC_OVR_SEL)/sizeof(ixGC_CAC_OVR_SEL[0]), 0, 0 }, + { "ixGC_CAC_OVR_VAL", REG_SMC, 0x0002, 0, &ixGC_CAC_OVR_VAL[0], sizeof(ixGC_CAC_OVR_VAL)/sizeof(ixGC_CAC_OVR_VAL[0]), 0, 0 }, + { "ixGC_CAC_WEIGHT_BCI_0", REG_SMC, 0x0003, 0, &ixGC_CAC_WEIGHT_BCI_0[0], sizeof(ixGC_CAC_WEIGHT_BCI_0)/sizeof(ixGC_CAC_WEIGHT_BCI_0[0]), 0, 0 }, + { "ixGC_CAC_WEIGHT_CB_0", REG_SMC, 0x0004, 0, &ixGC_CAC_WEIGHT_CB_0[0], sizeof(ixGC_CAC_WEIGHT_CB_0)/sizeof(ixGC_CAC_WEIGHT_CB_0[0]), 0, 0 }, + { "ixGC_CAC_WEIGHT_CB_1", REG_SMC, 0x0005, 0, &ixGC_CAC_WEIGHT_CB_1[0], sizeof(ixGC_CAC_WEIGHT_CB_1)/sizeof(ixGC_CAC_WEIGHT_CB_1[0]), 0, 0 }, + { "ixGC_CAC_WEIGHT_CP_0", REG_SMC, 0x0008, 0, &ixGC_CAC_WEIGHT_CP_0[0], sizeof(ixGC_CAC_WEIGHT_CP_0)/sizeof(ixGC_CAC_WEIGHT_CP_0[0]), 0, 0 }, + { "ixGC_CAC_WEIGHT_CP_1", REG_SMC, 0x0009, 0, &ixGC_CAC_WEIGHT_CP_1[0], sizeof(ixGC_CAC_WEIGHT_CP_1)/sizeof(ixGC_CAC_WEIGHT_CP_1[0]), 0, 0 }, + { "ixGC_CAC_WEIGHT_DB_0", REG_SMC, 0x000a, 0, &ixGC_CAC_WEIGHT_DB_0[0], sizeof(ixGC_CAC_WEIGHT_DB_0)/sizeof(ixGC_CAC_WEIGHT_DB_0[0]), 0, 0 }, + { "ixGC_CAC_WEIGHT_DB_1", REG_SMC, 0x000b, 0, &ixGC_CAC_WEIGHT_DB_1[0], sizeof(ixGC_CAC_WEIGHT_DB_1)/sizeof(ixGC_CAC_WEIGHT_DB_1[0]), 0, 0 }, + { "ixGC_CAC_WEIGHT_GDS_0", REG_SMC, 0x000e, 0, &ixGC_CAC_WEIGHT_GDS_0[0], sizeof(ixGC_CAC_WEIGHT_GDS_0)/sizeof(ixGC_CAC_WEIGHT_GDS_0[0]), 0, 0 }, + { "ixGC_CAC_WEIGHT_GDS_1", REG_SMC, 0x000f, 0, &ixGC_CAC_WEIGHT_GDS_1[0], sizeof(ixGC_CAC_WEIGHT_GDS_1)/sizeof(ixGC_CAC_WEIGHT_GDS_1[0]), 0, 0 }, + { "ixGC_CAC_WEIGHT_IA_0", REG_SMC, 0x0010, 0, &ixGC_CAC_WEIGHT_IA_0[0], sizeof(ixGC_CAC_WEIGHT_IA_0)/sizeof(ixGC_CAC_WEIGHT_IA_0[0]), 0, 0 }, + { "ixGC_CAC_WEIGHT_LDS_0", REG_SMC, 0x0011, 0, &ixGC_CAC_WEIGHT_LDS_0[0], sizeof(ixGC_CAC_WEIGHT_LDS_0)/sizeof(ixGC_CAC_WEIGHT_LDS_0[0]), 0, 0 }, + { "ixGC_CAC_WEIGHT_LDS_1", REG_SMC, 0x0012, 0, &ixGC_CAC_WEIGHT_LDS_1[0], sizeof(ixGC_CAC_WEIGHT_LDS_1)/sizeof(ixGC_CAC_WEIGHT_LDS_1[0]), 0, 0 }, + { "ixGC_CAC_WEIGHT_PA_0", REG_SMC, 0x0013, 0, &ixGC_CAC_WEIGHT_PA_0[0], sizeof(ixGC_CAC_WEIGHT_PA_0)/sizeof(ixGC_CAC_WEIGHT_PA_0[0]), 0, 0 }, + { "ixGC_CAC_WEIGHT_PC_0", REG_SMC, 0x0014, 0, &ixGC_CAC_WEIGHT_PC_0[0], sizeof(ixGC_CAC_WEIGHT_PC_0)/sizeof(ixGC_CAC_WEIGHT_PC_0[0]), 0, 0 }, + { "ixGC_CAC_WEIGHT_SC_0", REG_SMC, 0x0015, 0, &ixGC_CAC_WEIGHT_SC_0[0], sizeof(ixGC_CAC_WEIGHT_SC_0)/sizeof(ixGC_CAC_WEIGHT_SC_0[0]), 0, 0 }, + { "ixGC_CAC_WEIGHT_SPI_0", REG_SMC, 0x0016, 0, &ixGC_CAC_WEIGHT_SPI_0[0], sizeof(ixGC_CAC_WEIGHT_SPI_0)/sizeof(ixGC_CAC_WEIGHT_SPI_0[0]), 0, 0 }, + { "ixGC_CAC_WEIGHT_SPI_1", REG_SMC, 0x0017, 0, &ixGC_CAC_WEIGHT_SPI_1[0], sizeof(ixGC_CAC_WEIGHT_SPI_1)/sizeof(ixGC_CAC_WEIGHT_SPI_1[0]), 0, 0 }, + { "ixGC_CAC_WEIGHT_SPI_2", REG_SMC, 0x0018, 0, &ixGC_CAC_WEIGHT_SPI_2[0], sizeof(ixGC_CAC_WEIGHT_SPI_2)/sizeof(ixGC_CAC_WEIGHT_SPI_2[0]), 0, 0 }, + { "ixGC_CAC_WEIGHT_SQ_0", REG_SMC, 0x001a, 0, &ixGC_CAC_WEIGHT_SQ_0[0], sizeof(ixGC_CAC_WEIGHT_SQ_0)/sizeof(ixGC_CAC_WEIGHT_SQ_0[0]), 0, 0 }, + { "ixGC_CAC_WEIGHT_SQ_1", REG_SMC, 0x001b, 0, &ixGC_CAC_WEIGHT_SQ_1[0], sizeof(ixGC_CAC_WEIGHT_SQ_1)/sizeof(ixGC_CAC_WEIGHT_SQ_1[0]), 0, 0 }, + { "ixGC_CAC_WEIGHT_SQ_2", REG_SMC, 0x001c, 0, &ixGC_CAC_WEIGHT_SQ_2[0], sizeof(ixGC_CAC_WEIGHT_SQ_2)/sizeof(ixGC_CAC_WEIGHT_SQ_2[0]), 0, 0 }, + { "ixGC_CAC_WEIGHT_SQ_3", REG_SMC, 0x001d, 0, &ixGC_CAC_WEIGHT_SQ_3[0], sizeof(ixGC_CAC_WEIGHT_SQ_3)/sizeof(ixGC_CAC_WEIGHT_SQ_3[0]), 0, 0 }, + { "ixGC_CAC_WEIGHT_SQ_4", REG_SMC, 0x001e, 0, &ixGC_CAC_WEIGHT_SQ_4[0], sizeof(ixGC_CAC_WEIGHT_SQ_4)/sizeof(ixGC_CAC_WEIGHT_SQ_4[0]), 0, 0 }, + { "ixGC_CAC_WEIGHT_SX_0", REG_SMC, 0x001f, 0, &ixGC_CAC_WEIGHT_SX_0[0], sizeof(ixGC_CAC_WEIGHT_SX_0)/sizeof(ixGC_CAC_WEIGHT_SX_0[0]), 0, 0 }, + { "ixGC_CAC_WEIGHT_SXRB_0", REG_SMC, 0x0020, 0, &ixGC_CAC_WEIGHT_SXRB_0[0], sizeof(ixGC_CAC_WEIGHT_SXRB_0)/sizeof(ixGC_CAC_WEIGHT_SXRB_0[0]), 0, 0 }, + { "ixGC_CAC_WEIGHT_TA_0", REG_SMC, 0x0021, 0, &ixGC_CAC_WEIGHT_TA_0[0], sizeof(ixGC_CAC_WEIGHT_TA_0)/sizeof(ixGC_CAC_WEIGHT_TA_0[0]), 0, 0 }, + { "ixGC_CAC_WEIGHT_TCC_0", REG_SMC, 0x0022, 0, &ixGC_CAC_WEIGHT_TCC_0[0], sizeof(ixGC_CAC_WEIGHT_TCC_0)/sizeof(ixGC_CAC_WEIGHT_TCC_0[0]), 0, 0 }, + { "ixGC_CAC_WEIGHT_TCC_1", REG_SMC, 0x0023, 0, &ixGC_CAC_WEIGHT_TCC_1[0], sizeof(ixGC_CAC_WEIGHT_TCC_1)/sizeof(ixGC_CAC_WEIGHT_TCC_1[0]), 0, 0 }, + { "ixGC_CAC_WEIGHT_TCC_2", REG_SMC, 0x0024, 0, &ixGC_CAC_WEIGHT_TCC_2[0], sizeof(ixGC_CAC_WEIGHT_TCC_2)/sizeof(ixGC_CAC_WEIGHT_TCC_2[0]), 0, 0 }, + { "ixGC_CAC_WEIGHT_TCP_0", REG_SMC, 0x0025, 0, &ixGC_CAC_WEIGHT_TCP_0[0], sizeof(ixGC_CAC_WEIGHT_TCP_0)/sizeof(ixGC_CAC_WEIGHT_TCP_0[0]), 0, 0 }, + { "ixGC_CAC_WEIGHT_TCP_1", REG_SMC, 0x0026, 0, &ixGC_CAC_WEIGHT_TCP_1[0], sizeof(ixGC_CAC_WEIGHT_TCP_1)/sizeof(ixGC_CAC_WEIGHT_TCP_1[0]), 0, 0 }, + { "ixGC_CAC_WEIGHT_TCP_2", REG_SMC, 0x0027, 0, &ixGC_CAC_WEIGHT_TCP_2[0], sizeof(ixGC_CAC_WEIGHT_TCP_2)/sizeof(ixGC_CAC_WEIGHT_TCP_2[0]), 0, 0 }, + { "ixGC_CAC_WEIGHT_TD_0", REG_SMC, 0x0028, 0, &ixGC_CAC_WEIGHT_TD_0[0], sizeof(ixGC_CAC_WEIGHT_TD_0)/sizeof(ixGC_CAC_WEIGHT_TD_0[0]), 0, 0 }, + { "ixGC_CAC_WEIGHT_TD_1", REG_SMC, 0x0029, 0, &ixGC_CAC_WEIGHT_TD_1[0], sizeof(ixGC_CAC_WEIGHT_TD_1)/sizeof(ixGC_CAC_WEIGHT_TD_1[0]), 0, 0 }, + { "ixGC_CAC_WEIGHT_TD_2", REG_SMC, 0x002a, 0, &ixGC_CAC_WEIGHT_TD_2[0], sizeof(ixGC_CAC_WEIGHT_TD_2)/sizeof(ixGC_CAC_WEIGHT_TD_2[0]), 0, 0 }, + { "ixGC_CAC_WEIGHT_VGT_0", REG_SMC, 0x002b, 0, &ixGC_CAC_WEIGHT_VGT_0[0], sizeof(ixGC_CAC_WEIGHT_VGT_0)/sizeof(ixGC_CAC_WEIGHT_VGT_0[0]), 0, 0 }, + { "ixGC_CAC_WEIGHT_VGT_1", REG_SMC, 0x002c, 0, &ixGC_CAC_WEIGHT_VGT_1[0], sizeof(ixGC_CAC_WEIGHT_VGT_1)/sizeof(ixGC_CAC_WEIGHT_VGT_1[0]), 0, 0 }, + { "ixGC_CAC_WEIGHT_WD_0", REG_SMC, 0x002d, 0, &ixGC_CAC_WEIGHT_WD_0[0], sizeof(ixGC_CAC_WEIGHT_WD_0)/sizeof(ixGC_CAC_WEIGHT_WD_0[0]), 0, 0 }, + { "ixGC_CAC_WEIGHT_CU_0", REG_SMC, 0x0032, 0, &ixGC_CAC_WEIGHT_CU_0[0], sizeof(ixGC_CAC_WEIGHT_CU_0)/sizeof(ixGC_CAC_WEIGHT_CU_0[0]), 0, 0 }, + { "ixGC_CAC_WEIGHT_CU_1", REG_SMC, 0x0033, 0, &ixGC_CAC_WEIGHT_CU_1[0], sizeof(ixGC_CAC_WEIGHT_CU_1)/sizeof(ixGC_CAC_WEIGHT_CU_1[0]), 0, 0 }, + { "ixGC_CAC_WEIGHT_CU_2", REG_SMC, 0x0034, 0, &ixGC_CAC_WEIGHT_CU_2[0], sizeof(ixGC_CAC_WEIGHT_CU_2)/sizeof(ixGC_CAC_WEIGHT_CU_2[0]), 0, 0 }, + { "ixGC_CAC_WEIGHT_CU_3", REG_SMC, 0x0035, 0, &ixGC_CAC_WEIGHT_CU_3[0], sizeof(ixGC_CAC_WEIGHT_CU_3)/sizeof(ixGC_CAC_WEIGHT_CU_3[0]), 0, 0 }, + { "ixGC_CAC_WEIGHT_CU_4", REG_SMC, 0x0036, 0, &ixGC_CAC_WEIGHT_CU_4[0], sizeof(ixGC_CAC_WEIGHT_CU_4)/sizeof(ixGC_CAC_WEIGHT_CU_4[0]), 0, 0 }, + { "ixGC_CAC_WEIGHT_CU_5", REG_SMC, 0x0037, 0, &ixGC_CAC_WEIGHT_CU_5[0], sizeof(ixGC_CAC_WEIGHT_CU_5)/sizeof(ixGC_CAC_WEIGHT_CU_5[0]), 0, 0 }, + { "ixGC_CAC_ACC_BCI0", REG_SMC, 0x0042, 0, &ixGC_CAC_ACC_BCI0[0], sizeof(ixGC_CAC_ACC_BCI0)/sizeof(ixGC_CAC_ACC_BCI0[0]), 0, 0 }, + { "ixGC_CAC_ACC_CB0", REG_SMC, 0x0043, 0, &ixGC_CAC_ACC_CB0[0], sizeof(ixGC_CAC_ACC_CB0)/sizeof(ixGC_CAC_ACC_CB0[0]), 0, 0 }, + { "ixGC_CAC_ACC_CB1", REG_SMC, 0x0044, 0, &ixGC_CAC_ACC_CB1[0], sizeof(ixGC_CAC_ACC_CB1)/sizeof(ixGC_CAC_ACC_CB1[0]), 0, 0 }, + { "ixGC_CAC_ACC_CB2", REG_SMC, 0x0045, 0, &ixGC_CAC_ACC_CB2[0], sizeof(ixGC_CAC_ACC_CB2)/sizeof(ixGC_CAC_ACC_CB2[0]), 0, 0 }, + { "ixGC_CAC_ACC_CB3", REG_SMC, 0x0046, 0, &ixGC_CAC_ACC_CB3[0], sizeof(ixGC_CAC_ACC_CB3)/sizeof(ixGC_CAC_ACC_CB3[0]), 0, 0 }, + { "ixGC_CAC_ACC_CP0", REG_SMC, 0x004b, 0, &ixGC_CAC_ACC_CP0[0], sizeof(ixGC_CAC_ACC_CP0)/sizeof(ixGC_CAC_ACC_CP0[0]), 0, 0 }, + { "ixGC_CAC_ACC_CP1", REG_SMC, 0x004c, 0, &ixGC_CAC_ACC_CP1[0], sizeof(ixGC_CAC_ACC_CP1)/sizeof(ixGC_CAC_ACC_CP1[0]), 0, 0 }, + { "ixGC_CAC_ACC_CP2", REG_SMC, 0x004d, 0, &ixGC_CAC_ACC_CP2[0], sizeof(ixGC_CAC_ACC_CP2)/sizeof(ixGC_CAC_ACC_CP2[0]), 0, 0 }, + { "ixGC_CAC_ACC_DB0", REG_SMC, 0x004e, 0, &ixGC_CAC_ACC_DB0[0], sizeof(ixGC_CAC_ACC_DB0)/sizeof(ixGC_CAC_ACC_DB0[0]), 0, 0 }, + { "ixGC_CAC_ACC_DB1", REG_SMC, 0x004f, 0, &ixGC_CAC_ACC_DB1[0], sizeof(ixGC_CAC_ACC_DB1)/sizeof(ixGC_CAC_ACC_DB1[0]), 0, 0 }, + { "ixGC_CAC_ACC_DB2", REG_SMC, 0x0050, 0, &ixGC_CAC_ACC_DB2[0], sizeof(ixGC_CAC_ACC_DB2)/sizeof(ixGC_CAC_ACC_DB2[0]), 0, 0 }, + { "ixGC_CAC_ACC_DB3", REG_SMC, 0x0051, 0, &ixGC_CAC_ACC_DB3[0], sizeof(ixGC_CAC_ACC_DB3)/sizeof(ixGC_CAC_ACC_DB3[0]), 0, 0 }, + { "ixGC_CAC_ACC_GDS0", REG_SMC, 0x0056, 0, &ixGC_CAC_ACC_GDS0[0], sizeof(ixGC_CAC_ACC_GDS0)/sizeof(ixGC_CAC_ACC_GDS0[0]), 0, 0 }, + { "ixGC_CAC_ACC_GDS1", REG_SMC, 0x0057, 0, &ixGC_CAC_ACC_GDS1[0], sizeof(ixGC_CAC_ACC_GDS1)/sizeof(ixGC_CAC_ACC_GDS1[0]), 0, 0 }, + { "ixGC_CAC_ACC_GDS2", REG_SMC, 0x0058, 0, &ixGC_CAC_ACC_GDS2[0], sizeof(ixGC_CAC_ACC_GDS2)/sizeof(ixGC_CAC_ACC_GDS2[0]), 0, 0 }, + { "ixGC_CAC_ACC_GDS3", REG_SMC, 0x0059, 0, &ixGC_CAC_ACC_GDS3[0], sizeof(ixGC_CAC_ACC_GDS3)/sizeof(ixGC_CAC_ACC_GDS3[0]), 0, 0 }, + { "ixGC_CAC_ACC_IA0", REG_SMC, 0x005a, 0, &ixGC_CAC_ACC_IA0[0], sizeof(ixGC_CAC_ACC_IA0)/sizeof(ixGC_CAC_ACC_IA0[0]), 0, 0 }, + { "ixGC_CAC_ACC_LDS0", REG_SMC, 0x005b, 0, &ixGC_CAC_ACC_LDS0[0], sizeof(ixGC_CAC_ACC_LDS0)/sizeof(ixGC_CAC_ACC_LDS0[0]), 0, 0 }, + { "ixGC_CAC_ACC_LDS1", REG_SMC, 0x005c, 0, &ixGC_CAC_ACC_LDS1[0], sizeof(ixGC_CAC_ACC_LDS1)/sizeof(ixGC_CAC_ACC_LDS1[0]), 0, 0 }, + { "ixGC_CAC_ACC_LDS2", REG_SMC, 0x005d, 0, &ixGC_CAC_ACC_LDS2[0], sizeof(ixGC_CAC_ACC_LDS2)/sizeof(ixGC_CAC_ACC_LDS2[0]), 0, 0 }, + { "ixGC_CAC_ACC_LDS3", REG_SMC, 0x005e, 0, &ixGC_CAC_ACC_LDS3[0], sizeof(ixGC_CAC_ACC_LDS3)/sizeof(ixGC_CAC_ACC_LDS3[0]), 0, 0 }, + { "ixGC_CAC_ACC_PA0", REG_SMC, 0x005f, 0, &ixGC_CAC_ACC_PA0[0], sizeof(ixGC_CAC_ACC_PA0)/sizeof(ixGC_CAC_ACC_PA0[0]), 0, 0 }, + { "ixGC_CAC_ACC_PA1", REG_SMC, 0x0060, 0, &ixGC_CAC_ACC_PA1[0], sizeof(ixGC_CAC_ACC_PA1)/sizeof(ixGC_CAC_ACC_PA1[0]), 0, 0 }, + { "ixGC_CAC_ACC_PC0", REG_SMC, 0x0061, 0, &ixGC_CAC_ACC_PC0[0], sizeof(ixGC_CAC_ACC_PC0)/sizeof(ixGC_CAC_ACC_PC0[0]), 0, 0 }, + { "ixGC_CAC_ACC_SC0", REG_SMC, 0x0062, 0, &ixGC_CAC_ACC_SC0[0], sizeof(ixGC_CAC_ACC_SC0)/sizeof(ixGC_CAC_ACC_SC0[0]), 0, 0 }, + { "ixGC_CAC_ACC_SPI0", REG_SMC, 0x0063, 0, &ixGC_CAC_ACC_SPI0[0], sizeof(ixGC_CAC_ACC_SPI0)/sizeof(ixGC_CAC_ACC_SPI0[0]), 0, 0 }, + { "ixGC_CAC_ACC_SPI1", REG_SMC, 0x0064, 0, &ixGC_CAC_ACC_SPI1[0], sizeof(ixGC_CAC_ACC_SPI1)/sizeof(ixGC_CAC_ACC_SPI1[0]), 0, 0 }, + { "ixGC_CAC_ACC_SPI2", REG_SMC, 0x0065, 0, &ixGC_CAC_ACC_SPI2[0], sizeof(ixGC_CAC_ACC_SPI2)/sizeof(ixGC_CAC_ACC_SPI2[0]), 0, 0 }, + { "ixGC_CAC_ACC_SPI3", REG_SMC, 0x0066, 0, &ixGC_CAC_ACC_SPI3[0], sizeof(ixGC_CAC_ACC_SPI3)/sizeof(ixGC_CAC_ACC_SPI3[0]), 0, 0 }, + { "ixGC_CAC_ACC_SPI4", REG_SMC, 0x0067, 0, &ixGC_CAC_ACC_SPI4[0], sizeof(ixGC_CAC_ACC_SPI4)/sizeof(ixGC_CAC_ACC_SPI4[0]), 0, 0 }, + { "ixGC_CAC_ACC_SPI5", REG_SMC, 0x0068, 0, &ixGC_CAC_ACC_SPI5[0], sizeof(ixGC_CAC_ACC_SPI5)/sizeof(ixGC_CAC_ACC_SPI5[0]), 0, 0 }, + { "ixGC_CAC_WEIGHT_PG_0", REG_SMC, 0x0069, 0, &ixGC_CAC_WEIGHT_PG_0[0], sizeof(ixGC_CAC_WEIGHT_PG_0)/sizeof(ixGC_CAC_WEIGHT_PG_0[0]), 0, 0 }, + { "ixGC_CAC_ACC_PG0", REG_SMC, 0x006a, 0, &ixGC_CAC_ACC_PG0[0], sizeof(ixGC_CAC_ACC_PG0)/sizeof(ixGC_CAC_ACC_PG0[0]), 0, 0 }, + { "ixGC_CAC_OVRD_PG", REG_SMC, 0x006b, 0, &ixGC_CAC_OVRD_PG[0], sizeof(ixGC_CAC_OVRD_PG)/sizeof(ixGC_CAC_OVRD_PG[0]), 0, 0 }, + { "ixGC_CAC_WEIGHT_UTCL2_ATCL2_0", REG_SMC, 0x006f, 0, &ixGC_CAC_WEIGHT_UTCL2_ATCL2_0[0], sizeof(ixGC_CAC_WEIGHT_UTCL2_ATCL2_0)/sizeof(ixGC_CAC_WEIGHT_UTCL2_ATCL2_0[0]), 0, 0 }, + { "ixGC_CAC_ACC_EA0", REG_SMC, 0x0070, 0, &ixGC_CAC_ACC_EA0[0], sizeof(ixGC_CAC_ACC_EA0)/sizeof(ixGC_CAC_ACC_EA0[0]), 0, 0 }, + { "ixGC_CAC_ACC_EA1", REG_SMC, 0x0071, 0, &ixGC_CAC_ACC_EA1[0], sizeof(ixGC_CAC_ACC_EA1)/sizeof(ixGC_CAC_ACC_EA1[0]), 0, 0 }, + { "ixGC_CAC_ACC_EA2", REG_SMC, 0x0072, 0, &ixGC_CAC_ACC_EA2[0], sizeof(ixGC_CAC_ACC_EA2)/sizeof(ixGC_CAC_ACC_EA2[0]), 0, 0 }, + { "ixGC_CAC_ACC_EA3", REG_SMC, 0x0073, 0, &ixGC_CAC_ACC_EA3[0], sizeof(ixGC_CAC_ACC_EA3)/sizeof(ixGC_CAC_ACC_EA3[0]), 0, 0 }, + { "ixGC_CAC_ACC_UTCL2_ATCL20", REG_SMC, 0x0074, 0, &ixGC_CAC_ACC_UTCL2_ATCL20[0], sizeof(ixGC_CAC_ACC_UTCL2_ATCL20)/sizeof(ixGC_CAC_ACC_UTCL2_ATCL20[0]), 0, 0 }, + { "ixGC_CAC_OVRD_EA", REG_SMC, 0x0075, 0, &ixGC_CAC_OVRD_EA[0], sizeof(ixGC_CAC_OVRD_EA)/sizeof(ixGC_CAC_OVRD_EA[0]), 0, 0 }, + { "ixGC_CAC_OVRD_UTCL2_ATCL2", REG_SMC, 0x0076, 0, &ixGC_CAC_OVRD_UTCL2_ATCL2[0], sizeof(ixGC_CAC_OVRD_UTCL2_ATCL2)/sizeof(ixGC_CAC_OVRD_UTCL2_ATCL2[0]), 0, 0 }, + { "ixGC_CAC_WEIGHT_EA_0", REG_SMC, 0x0077, 0, &ixGC_CAC_WEIGHT_EA_0[0], sizeof(ixGC_CAC_WEIGHT_EA_0)/sizeof(ixGC_CAC_WEIGHT_EA_0[0]), 0, 0 }, + { "ixGC_CAC_WEIGHT_EA_1", REG_SMC, 0x0078, 0, &ixGC_CAC_WEIGHT_EA_1[0], sizeof(ixGC_CAC_WEIGHT_EA_1)/sizeof(ixGC_CAC_WEIGHT_EA_1[0]), 0, 0 }, + { "ixGC_CAC_WEIGHT_RMI_0", REG_SMC, 0x0079, 0, &ixGC_CAC_WEIGHT_RMI_0[0], sizeof(ixGC_CAC_WEIGHT_RMI_0)/sizeof(ixGC_CAC_WEIGHT_RMI_0[0]), 0, 0 }, + { "ixGC_CAC_ACC_RMI0", REG_SMC, 0x007a, 0, &ixGC_CAC_ACC_RMI0[0], sizeof(ixGC_CAC_ACC_RMI0)/sizeof(ixGC_CAC_ACC_RMI0[0]), 0, 0 }, + { "ixGC_CAC_OVRD_RMI", REG_SMC, 0x007b, 0, &ixGC_CAC_OVRD_RMI[0], sizeof(ixGC_CAC_OVRD_RMI)/sizeof(ixGC_CAC_OVRD_RMI[0]), 0, 0 }, + { "ixGC_CAC_WEIGHT_UTCL2_ATCL2_1", REG_SMC, 0x007c, 0, &ixGC_CAC_WEIGHT_UTCL2_ATCL2_1[0], sizeof(ixGC_CAC_WEIGHT_UTCL2_ATCL2_1)/sizeof(ixGC_CAC_WEIGHT_UTCL2_ATCL2_1[0]), 0, 0 }, + { "ixGC_CAC_ACC_UTCL2_ATCL21", REG_SMC, 0x007d, 0, &ixGC_CAC_ACC_UTCL2_ATCL21[0], sizeof(ixGC_CAC_ACC_UTCL2_ATCL21)/sizeof(ixGC_CAC_ACC_UTCL2_ATCL21[0]), 0, 0 }, + { "ixGC_CAC_ACC_UTCL2_ATCL22", REG_SMC, 0x007e, 0, &ixGC_CAC_ACC_UTCL2_ATCL22[0], sizeof(ixGC_CAC_ACC_UTCL2_ATCL22)/sizeof(ixGC_CAC_ACC_UTCL2_ATCL22[0]), 0, 0 }, + { "ixGC_CAC_ACC_UTCL2_ATCL23", REG_SMC, 0x007f, 0, &ixGC_CAC_ACC_UTCL2_ATCL23[0], sizeof(ixGC_CAC_ACC_UTCL2_ATCL23)/sizeof(ixGC_CAC_ACC_UTCL2_ATCL23[0]), 0, 0 }, + { "ixGC_CAC_ACC_EA4", REG_SMC, 0x0080, 0, &ixGC_CAC_ACC_EA4[0], sizeof(ixGC_CAC_ACC_EA4)/sizeof(ixGC_CAC_ACC_EA4[0]), 0, 0 }, + { "ixGC_CAC_ACC_EA5", REG_SMC, 0x0081, 0, &ixGC_CAC_ACC_EA5[0], sizeof(ixGC_CAC_ACC_EA5)/sizeof(ixGC_CAC_ACC_EA5[0]), 0, 0 }, + { "ixGC_CAC_WEIGHT_EA_2", REG_SMC, 0x0082, 0, &ixGC_CAC_WEIGHT_EA_2[0], sizeof(ixGC_CAC_WEIGHT_EA_2)/sizeof(ixGC_CAC_WEIGHT_EA_2[0]), 0, 0 }, + { "ixGC_CAC_ACC_SQ0_LOWER", REG_SMC, 0x0089, 0, &ixGC_CAC_ACC_SQ0_LOWER[0], sizeof(ixGC_CAC_ACC_SQ0_LOWER)/sizeof(ixGC_CAC_ACC_SQ0_LOWER[0]), 0, 0 }, + { "ixGC_CAC_ACC_SQ0_UPPER", REG_SMC, 0x008a, 0, &ixGC_CAC_ACC_SQ0_UPPER[0], sizeof(ixGC_CAC_ACC_SQ0_UPPER)/sizeof(ixGC_CAC_ACC_SQ0_UPPER[0]), 0, 0 }, + { "ixGC_CAC_ACC_SQ1_LOWER", REG_SMC, 0x008b, 0, &ixGC_CAC_ACC_SQ1_LOWER[0], sizeof(ixGC_CAC_ACC_SQ1_LOWER)/sizeof(ixGC_CAC_ACC_SQ1_LOWER[0]), 0, 0 }, + { "ixGC_CAC_ACC_SQ1_UPPER", REG_SMC, 0x008c, 0, &ixGC_CAC_ACC_SQ1_UPPER[0], sizeof(ixGC_CAC_ACC_SQ1_UPPER)/sizeof(ixGC_CAC_ACC_SQ1_UPPER[0]), 0, 0 }, + { "ixGC_CAC_ACC_SQ2_LOWER", REG_SMC, 0x008d, 0, &ixGC_CAC_ACC_SQ2_LOWER[0], sizeof(ixGC_CAC_ACC_SQ2_LOWER)/sizeof(ixGC_CAC_ACC_SQ2_LOWER[0]), 0, 0 }, + { "ixGC_CAC_ACC_SQ2_UPPER", REG_SMC, 0x008e, 0, &ixGC_CAC_ACC_SQ2_UPPER[0], sizeof(ixGC_CAC_ACC_SQ2_UPPER)/sizeof(ixGC_CAC_ACC_SQ2_UPPER[0]), 0, 0 }, + { "ixGC_CAC_ACC_SQ3_LOWER", REG_SMC, 0x008f, 0, &ixGC_CAC_ACC_SQ3_LOWER[0], sizeof(ixGC_CAC_ACC_SQ3_LOWER)/sizeof(ixGC_CAC_ACC_SQ3_LOWER[0]), 0, 0 }, + { "ixGC_CAC_ACC_SQ3_UPPER", REG_SMC, 0x0090, 0, &ixGC_CAC_ACC_SQ3_UPPER[0], sizeof(ixGC_CAC_ACC_SQ3_UPPER)/sizeof(ixGC_CAC_ACC_SQ3_UPPER[0]), 0, 0 }, + { "ixGC_CAC_ACC_SQ4_LOWER", REG_SMC, 0x0091, 0, &ixGC_CAC_ACC_SQ4_LOWER[0], sizeof(ixGC_CAC_ACC_SQ4_LOWER)/sizeof(ixGC_CAC_ACC_SQ4_LOWER[0]), 0, 0 }, + { "ixGC_CAC_ACC_SQ4_UPPER", REG_SMC, 0x0092, 0, &ixGC_CAC_ACC_SQ4_UPPER[0], sizeof(ixGC_CAC_ACC_SQ4_UPPER)/sizeof(ixGC_CAC_ACC_SQ4_UPPER[0]), 0, 0 }, + { "ixGC_CAC_ACC_SQ5_LOWER", REG_SMC, 0x0093, 0, &ixGC_CAC_ACC_SQ5_LOWER[0], sizeof(ixGC_CAC_ACC_SQ5_LOWER)/sizeof(ixGC_CAC_ACC_SQ5_LOWER[0]), 0, 0 }, + { "ixGC_CAC_ACC_SQ5_UPPER", REG_SMC, 0x0094, 0, &ixGC_CAC_ACC_SQ5_UPPER[0], sizeof(ixGC_CAC_ACC_SQ5_UPPER)/sizeof(ixGC_CAC_ACC_SQ5_UPPER[0]), 0, 0 }, + { "ixGC_CAC_ACC_SQ6_LOWER", REG_SMC, 0x0095, 0, &ixGC_CAC_ACC_SQ6_LOWER[0], sizeof(ixGC_CAC_ACC_SQ6_LOWER)/sizeof(ixGC_CAC_ACC_SQ6_LOWER[0]), 0, 0 }, + { "ixGC_CAC_ACC_SQ6_UPPER", REG_SMC, 0x0096, 0, &ixGC_CAC_ACC_SQ6_UPPER[0], sizeof(ixGC_CAC_ACC_SQ6_UPPER)/sizeof(ixGC_CAC_ACC_SQ6_UPPER[0]), 0, 0 }, + { "ixGC_CAC_ACC_SQ7_LOWER", REG_SMC, 0x0097, 0, &ixGC_CAC_ACC_SQ7_LOWER[0], sizeof(ixGC_CAC_ACC_SQ7_LOWER)/sizeof(ixGC_CAC_ACC_SQ7_LOWER[0]), 0, 0 }, + { "ixGC_CAC_ACC_SQ7_UPPER", REG_SMC, 0x0098, 0, &ixGC_CAC_ACC_SQ7_UPPER[0], sizeof(ixGC_CAC_ACC_SQ7_UPPER)/sizeof(ixGC_CAC_ACC_SQ7_UPPER[0]), 0, 0 }, + { "ixGC_CAC_ACC_SQ8_LOWER", REG_SMC, 0x0099, 0, &ixGC_CAC_ACC_SQ8_LOWER[0], sizeof(ixGC_CAC_ACC_SQ8_LOWER)/sizeof(ixGC_CAC_ACC_SQ8_LOWER[0]), 0, 0 }, + { "ixGC_CAC_ACC_SQ8_UPPER", REG_SMC, 0x009a, 0, &ixGC_CAC_ACC_SQ8_UPPER[0], sizeof(ixGC_CAC_ACC_SQ8_UPPER)/sizeof(ixGC_CAC_ACC_SQ8_UPPER[0]), 0, 0 }, + { "ixGC_CAC_ACC_SX0", REG_SMC, 0x009b, 0, &ixGC_CAC_ACC_SX0[0], sizeof(ixGC_CAC_ACC_SX0)/sizeof(ixGC_CAC_ACC_SX0[0]), 0, 0 }, + { "ixGC_CAC_ACC_SXRB0", REG_SMC, 0x009c, 0, &ixGC_CAC_ACC_SXRB0[0], sizeof(ixGC_CAC_ACC_SXRB0)/sizeof(ixGC_CAC_ACC_SXRB0[0]), 0, 0 }, + { "ixGC_CAC_ACC_SXRB1", REG_SMC, 0x009d, 0, &ixGC_CAC_ACC_SXRB1[0], sizeof(ixGC_CAC_ACC_SXRB1)/sizeof(ixGC_CAC_ACC_SXRB1[0]), 0, 0 }, + { "ixGC_CAC_ACC_TA0", REG_SMC, 0x009e, 0, &ixGC_CAC_ACC_TA0[0], sizeof(ixGC_CAC_ACC_TA0)/sizeof(ixGC_CAC_ACC_TA0[0]), 0, 0 }, + { "ixGC_CAC_ACC_TCC0", REG_SMC, 0x009f, 0, &ixGC_CAC_ACC_TCC0[0], sizeof(ixGC_CAC_ACC_TCC0)/sizeof(ixGC_CAC_ACC_TCC0[0]), 0, 0 }, + { "ixGC_CAC_ACC_TCC1", REG_SMC, 0x00a0, 0, &ixGC_CAC_ACC_TCC1[0], sizeof(ixGC_CAC_ACC_TCC1)/sizeof(ixGC_CAC_ACC_TCC1[0]), 0, 0 }, + { "ixGC_CAC_ACC_TCC2", REG_SMC, 0x00a1, 0, &ixGC_CAC_ACC_TCC2[0], sizeof(ixGC_CAC_ACC_TCC2)/sizeof(ixGC_CAC_ACC_TCC2[0]), 0, 0 }, + { "ixGC_CAC_ACC_TCC3", REG_SMC, 0x00a2, 0, &ixGC_CAC_ACC_TCC3[0], sizeof(ixGC_CAC_ACC_TCC3)/sizeof(ixGC_CAC_ACC_TCC3[0]), 0, 0 }, + { "ixGC_CAC_ACC_TCC4", REG_SMC, 0x00a3, 0, &ixGC_CAC_ACC_TCC4[0], sizeof(ixGC_CAC_ACC_TCC4)/sizeof(ixGC_CAC_ACC_TCC4[0]), 0, 0 }, + { "ixGC_CAC_ACC_TCP0", REG_SMC, 0x00a4, 0, &ixGC_CAC_ACC_TCP0[0], sizeof(ixGC_CAC_ACC_TCP0)/sizeof(ixGC_CAC_ACC_TCP0[0]), 0, 0 }, + { "ixGC_CAC_ACC_TCP1", REG_SMC, 0x00a5, 0, &ixGC_CAC_ACC_TCP1[0], sizeof(ixGC_CAC_ACC_TCP1)/sizeof(ixGC_CAC_ACC_TCP1[0]), 0, 0 }, + { "ixGC_CAC_ACC_TCP2", REG_SMC, 0x00a6, 0, &ixGC_CAC_ACC_TCP2[0], sizeof(ixGC_CAC_ACC_TCP2)/sizeof(ixGC_CAC_ACC_TCP2[0]), 0, 0 }, + { "ixGC_CAC_ACC_TCP3", REG_SMC, 0x00a7, 0, &ixGC_CAC_ACC_TCP3[0], sizeof(ixGC_CAC_ACC_TCP3)/sizeof(ixGC_CAC_ACC_TCP3[0]), 0, 0 }, + { "ixGC_CAC_ACC_TCP4", REG_SMC, 0x00a8, 0, &ixGC_CAC_ACC_TCP4[0], sizeof(ixGC_CAC_ACC_TCP4)/sizeof(ixGC_CAC_ACC_TCP4[0]), 0, 0 }, + { "ixGC_CAC_ACC_TD0", REG_SMC, 0x00a9, 0, &ixGC_CAC_ACC_TD0[0], sizeof(ixGC_CAC_ACC_TD0)/sizeof(ixGC_CAC_ACC_TD0[0]), 0, 0 }, + { "ixGC_CAC_ACC_TD1", REG_SMC, 0x00aa, 0, &ixGC_CAC_ACC_TD1[0], sizeof(ixGC_CAC_ACC_TD1)/sizeof(ixGC_CAC_ACC_TD1[0]), 0, 0 }, + { "ixGC_CAC_ACC_TD2", REG_SMC, 0x00ab, 0, &ixGC_CAC_ACC_TD2[0], sizeof(ixGC_CAC_ACC_TD2)/sizeof(ixGC_CAC_ACC_TD2[0]), 0, 0 }, + { "ixGC_CAC_ACC_TD3", REG_SMC, 0x00ac, 0, &ixGC_CAC_ACC_TD3[0], sizeof(ixGC_CAC_ACC_TD3)/sizeof(ixGC_CAC_ACC_TD3[0]), 0, 0 }, + { "ixGC_CAC_ACC_TD4", REG_SMC, 0x00ad, 0, &ixGC_CAC_ACC_TD4[0], sizeof(ixGC_CAC_ACC_TD4)/sizeof(ixGC_CAC_ACC_TD4[0]), 0, 0 }, + { "ixGC_CAC_ACC_TD5", REG_SMC, 0x00ae, 0, &ixGC_CAC_ACC_TD5[0], sizeof(ixGC_CAC_ACC_TD5)/sizeof(ixGC_CAC_ACC_TD5[0]), 0, 0 }, + { "ixGC_CAC_ACC_VGT0", REG_SMC, 0x00af, 0, &ixGC_CAC_ACC_VGT0[0], sizeof(ixGC_CAC_ACC_VGT0)/sizeof(ixGC_CAC_ACC_VGT0[0]), 0, 0 }, + { "ixGC_CAC_ACC_VGT1", REG_SMC, 0x00b0, 0, &ixGC_CAC_ACC_VGT1[0], sizeof(ixGC_CAC_ACC_VGT1)/sizeof(ixGC_CAC_ACC_VGT1[0]), 0, 0 }, + { "ixGC_CAC_ACC_VGT2", REG_SMC, 0x00b1, 0, &ixGC_CAC_ACC_VGT2[0], sizeof(ixGC_CAC_ACC_VGT2)/sizeof(ixGC_CAC_ACC_VGT2[0]), 0, 0 }, + { "ixGC_CAC_ACC_WD0", REG_SMC, 0x00b2, 0, &ixGC_CAC_ACC_WD0[0], sizeof(ixGC_CAC_ACC_WD0)/sizeof(ixGC_CAC_ACC_WD0[0]), 0, 0 }, + { "ixGC_CAC_ACC_CU0", REG_SMC, 0x00ba, 0, &ixGC_CAC_ACC_CU0[0], sizeof(ixGC_CAC_ACC_CU0)/sizeof(ixGC_CAC_ACC_CU0[0]), 0, 0 }, + { "ixGC_CAC_ACC_CU1", REG_SMC, 0x00bb, 0, &ixGC_CAC_ACC_CU1[0], sizeof(ixGC_CAC_ACC_CU1)/sizeof(ixGC_CAC_ACC_CU1[0]), 0, 0 }, + { "ixGC_CAC_ACC_CU2", REG_SMC, 0x00bc, 0, &ixGC_CAC_ACC_CU2[0], sizeof(ixGC_CAC_ACC_CU2)/sizeof(ixGC_CAC_ACC_CU2[0]), 0, 0 }, + { "ixGC_CAC_ACC_CU3", REG_SMC, 0x00bd, 0, &ixGC_CAC_ACC_CU3[0], sizeof(ixGC_CAC_ACC_CU3)/sizeof(ixGC_CAC_ACC_CU3[0]), 0, 0 }, + { "ixGC_CAC_ACC_CU4", REG_SMC, 0x00be, 0, &ixGC_CAC_ACC_CU4[0], sizeof(ixGC_CAC_ACC_CU4)/sizeof(ixGC_CAC_ACC_CU4[0]), 0, 0 }, + { "ixGC_CAC_ACC_CU5", REG_SMC, 0x00bf, 0, &ixGC_CAC_ACC_CU5[0], sizeof(ixGC_CAC_ACC_CU5)/sizeof(ixGC_CAC_ACC_CU5[0]), 0, 0 }, + { "ixGC_CAC_ACC_CU6", REG_SMC, 0x00c0, 0, &ixGC_CAC_ACC_CU6[0], sizeof(ixGC_CAC_ACC_CU6)/sizeof(ixGC_CAC_ACC_CU6[0]), 0, 0 }, + { "ixGC_CAC_ACC_CU7", REG_SMC, 0x00c1, 0, &ixGC_CAC_ACC_CU7[0], sizeof(ixGC_CAC_ACC_CU7)/sizeof(ixGC_CAC_ACC_CU7[0]), 0, 0 }, + { "ixGC_CAC_ACC_CU8", REG_SMC, 0x00c2, 0, &ixGC_CAC_ACC_CU8[0], sizeof(ixGC_CAC_ACC_CU8)/sizeof(ixGC_CAC_ACC_CU8[0]), 0, 0 }, + { "ixGC_CAC_ACC_CU9", REG_SMC, 0x00c3, 0, &ixGC_CAC_ACC_CU9[0], sizeof(ixGC_CAC_ACC_CU9)/sizeof(ixGC_CAC_ACC_CU9[0]), 0, 0 }, + { "ixGC_CAC_ACC_CU10", REG_SMC, 0x00c4, 0, &ixGC_CAC_ACC_CU10[0], sizeof(ixGC_CAC_ACC_CU10)/sizeof(ixGC_CAC_ACC_CU10[0]), 0, 0 }, + { "ixGC_CAC_OVRD_BCI", REG_SMC, 0x00da, 0, &ixGC_CAC_OVRD_BCI[0], sizeof(ixGC_CAC_OVRD_BCI)/sizeof(ixGC_CAC_OVRD_BCI[0]), 0, 0 }, + { "ixGC_CAC_OVRD_CB", REG_SMC, 0x00db, 0, &ixGC_CAC_OVRD_CB[0], sizeof(ixGC_CAC_OVRD_CB)/sizeof(ixGC_CAC_OVRD_CB[0]), 0, 0 }, + { "ixGC_CAC_OVRD_CP", REG_SMC, 0x00dd, 0, &ixGC_CAC_OVRD_CP[0], sizeof(ixGC_CAC_OVRD_CP)/sizeof(ixGC_CAC_OVRD_CP[0]), 0, 0 }, + { "ixGC_CAC_OVRD_DB", REG_SMC, 0x00de, 0, &ixGC_CAC_OVRD_DB[0], sizeof(ixGC_CAC_OVRD_DB)/sizeof(ixGC_CAC_OVRD_DB[0]), 0, 0 }, + { "ixGC_CAC_OVRD_GDS", REG_SMC, 0x00e0, 0, &ixGC_CAC_OVRD_GDS[0], sizeof(ixGC_CAC_OVRD_GDS)/sizeof(ixGC_CAC_OVRD_GDS[0]), 0, 0 }, + { "ixGC_CAC_OVRD_IA", REG_SMC, 0x00e1, 0, &ixGC_CAC_OVRD_IA[0], sizeof(ixGC_CAC_OVRD_IA)/sizeof(ixGC_CAC_OVRD_IA[0]), 0, 0 }, + { "ixGC_CAC_OVRD_LDS", REG_SMC, 0x00e2, 0, &ixGC_CAC_OVRD_LDS[0], sizeof(ixGC_CAC_OVRD_LDS)/sizeof(ixGC_CAC_OVRD_LDS[0]), 0, 0 }, + { "ixGC_CAC_OVRD_PA", REG_SMC, 0x00e3, 0, &ixGC_CAC_OVRD_PA[0], sizeof(ixGC_CAC_OVRD_PA)/sizeof(ixGC_CAC_OVRD_PA[0]), 0, 0 }, + { "ixGC_CAC_OVRD_PC", REG_SMC, 0x00e4, 0, &ixGC_CAC_OVRD_PC[0], sizeof(ixGC_CAC_OVRD_PC)/sizeof(ixGC_CAC_OVRD_PC[0]), 0, 0 }, + { "ixGC_CAC_OVRD_SC", REG_SMC, 0x00e5, 0, &ixGC_CAC_OVRD_SC[0], sizeof(ixGC_CAC_OVRD_SC)/sizeof(ixGC_CAC_OVRD_SC[0]), 0, 0 }, + { "ixGC_CAC_OVRD_SPI", REG_SMC, 0x00e6, 0, &ixGC_CAC_OVRD_SPI[0], sizeof(ixGC_CAC_OVRD_SPI)/sizeof(ixGC_CAC_OVRD_SPI[0]), 0, 0 }, + { "ixGC_CAC_OVRD_CU", REG_SMC, 0x00e7, 0, &ixGC_CAC_OVRD_CU[0], sizeof(ixGC_CAC_OVRD_CU)/sizeof(ixGC_CAC_OVRD_CU[0]), 0, 0 }, + { "ixGC_CAC_OVRD_SQ", REG_SMC, 0x00e8, 0, &ixGC_CAC_OVRD_SQ[0], sizeof(ixGC_CAC_OVRD_SQ)/sizeof(ixGC_CAC_OVRD_SQ[0]), 0, 0 }, + { "ixGC_CAC_OVRD_SX", REG_SMC, 0x00e9, 0, &ixGC_CAC_OVRD_SX[0], sizeof(ixGC_CAC_OVRD_SX)/sizeof(ixGC_CAC_OVRD_SX[0]), 0, 0 }, + { "ixGC_CAC_OVRD_SXRB", REG_SMC, 0x00ea, 0, &ixGC_CAC_OVRD_SXRB[0], sizeof(ixGC_CAC_OVRD_SXRB)/sizeof(ixGC_CAC_OVRD_SXRB[0]), 0, 0 }, + { "ixGC_CAC_OVRD_TA", REG_SMC, 0x00eb, 0, &ixGC_CAC_OVRD_TA[0], sizeof(ixGC_CAC_OVRD_TA)/sizeof(ixGC_CAC_OVRD_TA[0]), 0, 0 }, + { "ixGC_CAC_OVRD_TCC", REG_SMC, 0x00ec, 0, &ixGC_CAC_OVRD_TCC[0], sizeof(ixGC_CAC_OVRD_TCC)/sizeof(ixGC_CAC_OVRD_TCC[0]), 0, 0 }, + { "ixGC_CAC_OVRD_TCP", REG_SMC, 0x00ed, 0, &ixGC_CAC_OVRD_TCP[0], sizeof(ixGC_CAC_OVRD_TCP)/sizeof(ixGC_CAC_OVRD_TCP[0]), 0, 0 }, + { "ixGC_CAC_OVRD_TD", REG_SMC, 0x00ee, 0, &ixGC_CAC_OVRD_TD[0], sizeof(ixGC_CAC_OVRD_TD)/sizeof(ixGC_CAC_OVRD_TD[0]), 0, 0 }, + { "ixGC_CAC_OVRD_VGT", REG_SMC, 0x00ef, 0, &ixGC_CAC_OVRD_VGT[0], sizeof(ixGC_CAC_OVRD_VGT)/sizeof(ixGC_CAC_OVRD_VGT[0]), 0, 0 }, + { "ixGC_CAC_OVRD_WD", REG_SMC, 0x00f0, 0, &ixGC_CAC_OVRD_WD[0], sizeof(ixGC_CAC_OVRD_WD)/sizeof(ixGC_CAC_OVRD_WD[0]), 0, 0 }, + { "ixGC_CAC_ACC_BCI1", REG_SMC, 0x00ff, 0, &ixGC_CAC_ACC_BCI1[0], sizeof(ixGC_CAC_ACC_BCI1)/sizeof(ixGC_CAC_ACC_BCI1[0]), 0, 0 }, + { "ixGC_CAC_WEIGHT_UTCL2_ATCL2_2", REG_SMC, 0x0100, 0, &ixGC_CAC_WEIGHT_UTCL2_ATCL2_2[0], sizeof(ixGC_CAC_WEIGHT_UTCL2_ATCL2_2)/sizeof(ixGC_CAC_WEIGHT_UTCL2_ATCL2_2[0]), 0, 0 }, + { "ixGC_CAC_WEIGHT_UTCL2_ROUTER_0", REG_SMC, 0x0101, 0, &ixGC_CAC_WEIGHT_UTCL2_ROUTER_0[0], sizeof(ixGC_CAC_WEIGHT_UTCL2_ROUTER_0)/sizeof(ixGC_CAC_WEIGHT_UTCL2_ROUTER_0[0]), 0, 0 }, + { "ixGC_CAC_WEIGHT_UTCL2_ROUTER_1", REG_SMC, 0x0102, 0, &ixGC_CAC_WEIGHT_UTCL2_ROUTER_1[0], sizeof(ixGC_CAC_WEIGHT_UTCL2_ROUTER_1)/sizeof(ixGC_CAC_WEIGHT_UTCL2_ROUTER_1[0]), 0, 0 }, + { "ixGC_CAC_WEIGHT_UTCL2_ROUTER_2", REG_SMC, 0x0103, 0, &ixGC_CAC_WEIGHT_UTCL2_ROUTER_2[0], sizeof(ixGC_CAC_WEIGHT_UTCL2_ROUTER_2)/sizeof(ixGC_CAC_WEIGHT_UTCL2_ROUTER_2[0]), 0, 0 }, + { "ixGC_CAC_WEIGHT_UTCL2_ROUTER_3", REG_SMC, 0x0104, 0, &ixGC_CAC_WEIGHT_UTCL2_ROUTER_3[0], sizeof(ixGC_CAC_WEIGHT_UTCL2_ROUTER_3)/sizeof(ixGC_CAC_WEIGHT_UTCL2_ROUTER_3[0]), 0, 0 }, + { "ixGC_CAC_WEIGHT_UTCL2_ROUTER_4", REG_SMC, 0x0105, 0, &ixGC_CAC_WEIGHT_UTCL2_ROUTER_4[0], sizeof(ixGC_CAC_WEIGHT_UTCL2_ROUTER_4)/sizeof(ixGC_CAC_WEIGHT_UTCL2_ROUTER_4[0]), 0, 0 }, + { "ixGC_CAC_WEIGHT_UTCL2_VML2_0", REG_SMC, 0x0106, 0, &ixGC_CAC_WEIGHT_UTCL2_VML2_0[0], sizeof(ixGC_CAC_WEIGHT_UTCL2_VML2_0)/sizeof(ixGC_CAC_WEIGHT_UTCL2_VML2_0[0]), 0, 0 }, + { "ixGC_CAC_WEIGHT_UTCL2_VML2_1", REG_SMC, 0x0107, 0, &ixGC_CAC_WEIGHT_UTCL2_VML2_1[0], sizeof(ixGC_CAC_WEIGHT_UTCL2_VML2_1)/sizeof(ixGC_CAC_WEIGHT_UTCL2_VML2_1[0]), 0, 0 }, + { "ixGC_CAC_WEIGHT_UTCL2_VML2_2", REG_SMC, 0x0108, 0, &ixGC_CAC_WEIGHT_UTCL2_VML2_2[0], sizeof(ixGC_CAC_WEIGHT_UTCL2_VML2_2)/sizeof(ixGC_CAC_WEIGHT_UTCL2_VML2_2[0]), 0, 0 }, + { "ixGC_CAC_ACC_UTCL2_ATCL24", REG_SMC, 0x0109, 0, &ixGC_CAC_ACC_UTCL2_ATCL24[0], sizeof(ixGC_CAC_ACC_UTCL2_ATCL24)/sizeof(ixGC_CAC_ACC_UTCL2_ATCL24[0]), 0, 0 }, + { "ixGC_CAC_ACC_UTCL2_ROUTER0", REG_SMC, 0x010a, 0, &ixGC_CAC_ACC_UTCL2_ROUTER0[0], sizeof(ixGC_CAC_ACC_UTCL2_ROUTER0)/sizeof(ixGC_CAC_ACC_UTCL2_ROUTER0[0]), 0, 0 }, + { "ixGC_CAC_ACC_UTCL2_ROUTER1", REG_SMC, 0x010b, 0, &ixGC_CAC_ACC_UTCL2_ROUTER1[0], sizeof(ixGC_CAC_ACC_UTCL2_ROUTER1)/sizeof(ixGC_CAC_ACC_UTCL2_ROUTER1[0]), 0, 0 }, + { "ixGC_CAC_ACC_UTCL2_ROUTER2", REG_SMC, 0x010c, 0, &ixGC_CAC_ACC_UTCL2_ROUTER2[0], sizeof(ixGC_CAC_ACC_UTCL2_ROUTER2)/sizeof(ixGC_CAC_ACC_UTCL2_ROUTER2[0]), 0, 0 }, + { "ixGC_CAC_ACC_UTCL2_ROUTER3", REG_SMC, 0x010d, 0, &ixGC_CAC_ACC_UTCL2_ROUTER3[0], sizeof(ixGC_CAC_ACC_UTCL2_ROUTER3)/sizeof(ixGC_CAC_ACC_UTCL2_ROUTER3[0]), 0, 0 }, + { "ixGC_CAC_ACC_UTCL2_ROUTER4", REG_SMC, 0x010e, 0, &ixGC_CAC_ACC_UTCL2_ROUTER4[0], sizeof(ixGC_CAC_ACC_UTCL2_ROUTER4)/sizeof(ixGC_CAC_ACC_UTCL2_ROUTER4[0]), 0, 0 }, + { "ixGC_CAC_ACC_UTCL2_ROUTER5", REG_SMC, 0x010f, 0, &ixGC_CAC_ACC_UTCL2_ROUTER5[0], sizeof(ixGC_CAC_ACC_UTCL2_ROUTER5)/sizeof(ixGC_CAC_ACC_UTCL2_ROUTER5[0]), 0, 0 }, + { "ixGC_CAC_ACC_UTCL2_ROUTER6", REG_SMC, 0x0110, 0, &ixGC_CAC_ACC_UTCL2_ROUTER6[0], sizeof(ixGC_CAC_ACC_UTCL2_ROUTER6)/sizeof(ixGC_CAC_ACC_UTCL2_ROUTER6[0]), 0, 0 }, + { "ixGC_CAC_ACC_UTCL2_ROUTER7", REG_SMC, 0x0111, 0, &ixGC_CAC_ACC_UTCL2_ROUTER7[0], sizeof(ixGC_CAC_ACC_UTCL2_ROUTER7)/sizeof(ixGC_CAC_ACC_UTCL2_ROUTER7[0]), 0, 0 }, + { "ixGC_CAC_ACC_UTCL2_ROUTER8", REG_SMC, 0x0112, 0, &ixGC_CAC_ACC_UTCL2_ROUTER8[0], sizeof(ixGC_CAC_ACC_UTCL2_ROUTER8)/sizeof(ixGC_CAC_ACC_UTCL2_ROUTER8[0]), 0, 0 }, + { "ixGC_CAC_ACC_UTCL2_ROUTER9", REG_SMC, 0x0113, 0, &ixGC_CAC_ACC_UTCL2_ROUTER9[0], sizeof(ixGC_CAC_ACC_UTCL2_ROUTER9)/sizeof(ixGC_CAC_ACC_UTCL2_ROUTER9[0]), 0, 0 }, + { "ixGC_CAC_ACC_UTCL2_VML20", REG_SMC, 0x0114, 0, &ixGC_CAC_ACC_UTCL2_VML20[0], sizeof(ixGC_CAC_ACC_UTCL2_VML20)/sizeof(ixGC_CAC_ACC_UTCL2_VML20[0]), 0, 0 }, + { "ixGC_CAC_ACC_UTCL2_VML21", REG_SMC, 0x0115, 0, &ixGC_CAC_ACC_UTCL2_VML21[0], sizeof(ixGC_CAC_ACC_UTCL2_VML21)/sizeof(ixGC_CAC_ACC_UTCL2_VML21[0]), 0, 0 }, + { "ixGC_CAC_ACC_UTCL2_VML22", REG_SMC, 0x0116, 0, &ixGC_CAC_ACC_UTCL2_VML22[0], sizeof(ixGC_CAC_ACC_UTCL2_VML22)/sizeof(ixGC_CAC_ACC_UTCL2_VML22[0]), 0, 0 }, + { "ixGC_CAC_ACC_UTCL2_VML23", REG_SMC, 0x0117, 0, &ixGC_CAC_ACC_UTCL2_VML23[0], sizeof(ixGC_CAC_ACC_UTCL2_VML23)/sizeof(ixGC_CAC_ACC_UTCL2_VML23[0]), 0, 0 }, + { "ixGC_CAC_ACC_UTCL2_VML24", REG_SMC, 0x0118, 0, &ixGC_CAC_ACC_UTCL2_VML24[0], sizeof(ixGC_CAC_ACC_UTCL2_VML24)/sizeof(ixGC_CAC_ACC_UTCL2_VML24[0]), 0, 0 }, + { "ixGC_CAC_OVRD_UTCL2_ROUTER", REG_SMC, 0x0119, 0, &ixGC_CAC_OVRD_UTCL2_ROUTER[0], sizeof(ixGC_CAC_OVRD_UTCL2_ROUTER)/sizeof(ixGC_CAC_OVRD_UTCL2_ROUTER[0]), 0, 0 }, + { "ixGC_CAC_OVRD_UTCL2_VML2", REG_SMC, 0x011a, 0, &ixGC_CAC_OVRD_UTCL2_VML2[0], sizeof(ixGC_CAC_OVRD_UTCL2_VML2)/sizeof(ixGC_CAC_OVRD_UTCL2_VML2[0]), 0, 0 }, + { "ixGC_CAC_WEIGHT_UTCL2_WALKER_0", REG_SMC, 0x011b, 0, &ixGC_CAC_WEIGHT_UTCL2_WALKER_0[0], sizeof(ixGC_CAC_WEIGHT_UTCL2_WALKER_0)/sizeof(ixGC_CAC_WEIGHT_UTCL2_WALKER_0[0]), 0, 0 }, + { "ixGC_CAC_WEIGHT_UTCL2_WALKER_1", REG_SMC, 0x011c, 0, &ixGC_CAC_WEIGHT_UTCL2_WALKER_1[0], sizeof(ixGC_CAC_WEIGHT_UTCL2_WALKER_1)/sizeof(ixGC_CAC_WEIGHT_UTCL2_WALKER_1[0]), 0, 0 }, + { "ixGC_CAC_WEIGHT_UTCL2_WALKER_2", REG_SMC, 0x011d, 0, &ixGC_CAC_WEIGHT_UTCL2_WALKER_2[0], sizeof(ixGC_CAC_WEIGHT_UTCL2_WALKER_2)/sizeof(ixGC_CAC_WEIGHT_UTCL2_WALKER_2[0]), 0, 0 }, + { "ixGC_CAC_ACC_UTCL2_WALKER0", REG_SMC, 0x011e, 0, &ixGC_CAC_ACC_UTCL2_WALKER0[0], sizeof(ixGC_CAC_ACC_UTCL2_WALKER0)/sizeof(ixGC_CAC_ACC_UTCL2_WALKER0[0]), 0, 0 }, + { "ixGC_CAC_ACC_UTCL2_WALKER1", REG_SMC, 0x011f, 0, &ixGC_CAC_ACC_UTCL2_WALKER1[0], sizeof(ixGC_CAC_ACC_UTCL2_WALKER1)/sizeof(ixGC_CAC_ACC_UTCL2_WALKER1[0]), 0, 0 }, + { "ixGC_CAC_ACC_UTCL2_WALKER2", REG_SMC, 0x0120, 0, &ixGC_CAC_ACC_UTCL2_WALKER2[0], sizeof(ixGC_CAC_ACC_UTCL2_WALKER2)/sizeof(ixGC_CAC_ACC_UTCL2_WALKER2[0]), 0, 0 }, + { "ixGC_CAC_ACC_UTCL2_WALKER3", REG_SMC, 0x0121, 0, &ixGC_CAC_ACC_UTCL2_WALKER3[0], sizeof(ixGC_CAC_ACC_UTCL2_WALKER3)/sizeof(ixGC_CAC_ACC_UTCL2_WALKER3[0]), 0, 0 }, + { "ixGC_CAC_ACC_UTCL2_WALKER4", REG_SMC, 0x0122, 0, &ixGC_CAC_ACC_UTCL2_WALKER4[0], sizeof(ixGC_CAC_ACC_UTCL2_WALKER4)/sizeof(ixGC_CAC_ACC_UTCL2_WALKER4[0]), 0, 0 }, + { "ixGC_CAC_OVRD_UTCL2_WALKER", REG_SMC, 0x0123, 0, &ixGC_CAC_OVRD_UTCL2_WALKER[0], sizeof(ixGC_CAC_OVRD_UTCL2_WALKER)/sizeof(ixGC_CAC_OVRD_UTCL2_WALKER[0]), 0, 0 }, + { "ixSE_CAC_CNTL", REG_SMC, 0x0000, 0, &ixSE_CAC_CNTL[0], sizeof(ixSE_CAC_CNTL)/sizeof(ixSE_CAC_CNTL[0]), 0, 0 }, + { "ixSE_CAC_OVR_SEL", REG_SMC, 0x0001, 0, &ixSE_CAC_OVR_SEL[0], sizeof(ixSE_CAC_OVR_SEL)/sizeof(ixSE_CAC_OVR_SEL[0]), 0, 0 }, + { "ixSE_CAC_OVR_VAL", REG_SMC, 0x0002, 0, &ixSE_CAC_OVR_VAL[0], sizeof(ixSE_CAC_OVR_VAL)/sizeof(ixSE_CAC_OVR_VAL[0]), 0, 0 }, + { "ixSQ_WAVE_MODE", REG_SMC, 0x0011, 0, &ixSQ_WAVE_MODE[0], sizeof(ixSQ_WAVE_MODE)/sizeof(ixSQ_WAVE_MODE[0]), 0, 0 }, + { "ixSQ_WAVE_STATUS", REG_SMC, 0x0012, 0, &ixSQ_WAVE_STATUS[0], sizeof(ixSQ_WAVE_STATUS)/sizeof(ixSQ_WAVE_STATUS[0]), 0, 0 }, + { "ixSQ_WAVE_TRAPSTS", REG_SMC, 0x0013, 0, &ixSQ_WAVE_TRAPSTS[0], sizeof(ixSQ_WAVE_TRAPSTS)/sizeof(ixSQ_WAVE_TRAPSTS[0]), 0, 0 }, + { "ixSQ_WAVE_HW_ID", REG_SMC, 0x0014, 0, &ixSQ_WAVE_HW_ID[0], sizeof(ixSQ_WAVE_HW_ID)/sizeof(ixSQ_WAVE_HW_ID[0]), 0, 0 }, + { "ixSQ_WAVE_GPR_ALLOC", REG_SMC, 0x0015, 0, &ixSQ_WAVE_GPR_ALLOC[0], sizeof(ixSQ_WAVE_GPR_ALLOC)/sizeof(ixSQ_WAVE_GPR_ALLOC[0]), 0, 0 }, + { "ixSQ_WAVE_LDS_ALLOC", REG_SMC, 0x0016, 0, &ixSQ_WAVE_LDS_ALLOC[0], sizeof(ixSQ_WAVE_LDS_ALLOC)/sizeof(ixSQ_WAVE_LDS_ALLOC[0]), 0, 0 }, + { "ixSQ_WAVE_IB_STS", REG_SMC, 0x0017, 0, &ixSQ_WAVE_IB_STS[0], sizeof(ixSQ_WAVE_IB_STS)/sizeof(ixSQ_WAVE_IB_STS[0]), 0, 0 }, + { "ixSQ_WAVE_PC_LO", REG_SMC, 0x0018, 0, &ixSQ_WAVE_PC_LO[0], sizeof(ixSQ_WAVE_PC_LO)/sizeof(ixSQ_WAVE_PC_LO[0]), 0, 0 }, + { "ixSQ_WAVE_PC_HI", REG_SMC, 0x0019, 0, &ixSQ_WAVE_PC_HI[0], sizeof(ixSQ_WAVE_PC_HI)/sizeof(ixSQ_WAVE_PC_HI[0]), 0, 0 }, + { "ixSQ_WAVE_INST_DW0", REG_SMC, 0x001a, 0, &ixSQ_WAVE_INST_DW0[0], sizeof(ixSQ_WAVE_INST_DW0)/sizeof(ixSQ_WAVE_INST_DW0[0]), 0, 0 }, + { "ixSQ_WAVE_INST_DW1", REG_SMC, 0x001b, 0, &ixSQ_WAVE_INST_DW1[0], sizeof(ixSQ_WAVE_INST_DW1)/sizeof(ixSQ_WAVE_INST_DW1[0]), 0, 0 }, + { "ixSQ_WAVE_IB_DBG0", REG_SMC, 0x001c, 0, &ixSQ_WAVE_IB_DBG0[0], sizeof(ixSQ_WAVE_IB_DBG0)/sizeof(ixSQ_WAVE_IB_DBG0[0]), 0, 0 }, + { "ixSQ_WAVE_IB_DBG1", REG_SMC, 0x001d, 0, &ixSQ_WAVE_IB_DBG1[0], sizeof(ixSQ_WAVE_IB_DBG1)/sizeof(ixSQ_WAVE_IB_DBG1[0]), 0, 0 }, + { "ixSQ_WAVE_FLUSH_IB", REG_SMC, 0x001e, 0, &ixSQ_WAVE_FLUSH_IB[0], sizeof(ixSQ_WAVE_FLUSH_IB)/sizeof(ixSQ_WAVE_FLUSH_IB[0]), 0, 0 }, + { "ixSQ_WAVE_TTMP0", REG_SMC, 0x026c, 0, &ixSQ_WAVE_TTMP0[0], sizeof(ixSQ_WAVE_TTMP0)/sizeof(ixSQ_WAVE_TTMP0[0]), 0, 0 }, + { "ixSQ_WAVE_TTMP1", REG_SMC, 0x026d, 0, &ixSQ_WAVE_TTMP1[0], sizeof(ixSQ_WAVE_TTMP1)/sizeof(ixSQ_WAVE_TTMP1[0]), 0, 0 }, + { "ixSQ_WAVE_TTMP2", REG_SMC, 0x026e, 0, &ixSQ_WAVE_TTMP2[0], sizeof(ixSQ_WAVE_TTMP2)/sizeof(ixSQ_WAVE_TTMP2[0]), 0, 0 }, + { "ixSQ_WAVE_TTMP3", REG_SMC, 0x026f, 0, &ixSQ_WAVE_TTMP3[0], sizeof(ixSQ_WAVE_TTMP3)/sizeof(ixSQ_WAVE_TTMP3[0]), 0, 0 }, + { "ixSQ_WAVE_TTMP4", REG_SMC, 0x0270, 0, &ixSQ_WAVE_TTMP4[0], sizeof(ixSQ_WAVE_TTMP4)/sizeof(ixSQ_WAVE_TTMP4[0]), 0, 0 }, + { "ixSQ_WAVE_TTMP5", REG_SMC, 0x0271, 0, &ixSQ_WAVE_TTMP5[0], sizeof(ixSQ_WAVE_TTMP5)/sizeof(ixSQ_WAVE_TTMP5[0]), 0, 0 }, + { "ixSQ_WAVE_TTMP6", REG_SMC, 0x0272, 0, &ixSQ_WAVE_TTMP6[0], sizeof(ixSQ_WAVE_TTMP6)/sizeof(ixSQ_WAVE_TTMP6[0]), 0, 0 }, + { "ixSQ_WAVE_TTMP7", REG_SMC, 0x0273, 0, &ixSQ_WAVE_TTMP7[0], sizeof(ixSQ_WAVE_TTMP7)/sizeof(ixSQ_WAVE_TTMP7[0]), 0, 0 }, + { "ixSQ_WAVE_TTMP8", REG_SMC, 0x0274, 0, &ixSQ_WAVE_TTMP8[0], sizeof(ixSQ_WAVE_TTMP8)/sizeof(ixSQ_WAVE_TTMP8[0]), 0, 0 }, + { "ixSQ_WAVE_TTMP9", REG_SMC, 0x0275, 0, &ixSQ_WAVE_TTMP9[0], sizeof(ixSQ_WAVE_TTMP9)/sizeof(ixSQ_WAVE_TTMP9[0]), 0, 0 }, + { "ixSQ_WAVE_TTMP10", REG_SMC, 0x0276, 0, &ixSQ_WAVE_TTMP10[0], sizeof(ixSQ_WAVE_TTMP10)/sizeof(ixSQ_WAVE_TTMP10[0]), 0, 0 }, + { "ixSQ_WAVE_TTMP11", REG_SMC, 0x0277, 0, &ixSQ_WAVE_TTMP11[0], sizeof(ixSQ_WAVE_TTMP11)/sizeof(ixSQ_WAVE_TTMP11[0]), 0, 0 }, + { "ixSQ_WAVE_TTMP12", REG_SMC, 0x0278, 0, &ixSQ_WAVE_TTMP12[0], sizeof(ixSQ_WAVE_TTMP12)/sizeof(ixSQ_WAVE_TTMP12[0]), 0, 0 }, + { "ixSQ_WAVE_TTMP13", REG_SMC, 0x0279, 0, &ixSQ_WAVE_TTMP13[0], sizeof(ixSQ_WAVE_TTMP13)/sizeof(ixSQ_WAVE_TTMP13[0]), 0, 0 }, + { "ixSQ_WAVE_TTMP14", REG_SMC, 0x027a, 0, &ixSQ_WAVE_TTMP14[0], sizeof(ixSQ_WAVE_TTMP14)/sizeof(ixSQ_WAVE_TTMP14[0]), 0, 0 }, + { "ixSQ_WAVE_TTMP15", REG_SMC, 0x027b, 0, &ixSQ_WAVE_TTMP15[0], sizeof(ixSQ_WAVE_TTMP15)/sizeof(ixSQ_WAVE_TTMP15[0]), 0, 0 }, + { "ixSQ_WAVE_M0", REG_SMC, 0x027c, 0, &ixSQ_WAVE_M0[0], sizeof(ixSQ_WAVE_M0)/sizeof(ixSQ_WAVE_M0[0]), 0, 0 }, + { "ixSQ_WAVE_EXEC_LO", REG_SMC, 0x027e, 0, &ixSQ_WAVE_EXEC_LO[0], sizeof(ixSQ_WAVE_EXEC_LO)/sizeof(ixSQ_WAVE_EXEC_LO[0]), 0, 0 }, + { "ixSQ_WAVE_EXEC_HI", REG_SMC, 0x027f, 0, &ixSQ_WAVE_EXEC_HI[0], sizeof(ixSQ_WAVE_EXEC_HI)/sizeof(ixSQ_WAVE_EXEC_HI[0]), 0, 0 }, + { "ixSQ_INTERRUPT_WORD_AUTO_CTXID", REG_SMC, 0x20c0, 0, &ixSQ_INTERRUPT_WORD_AUTO_CTXID[0], sizeof(ixSQ_INTERRUPT_WORD_AUTO_CTXID)/sizeof(ixSQ_INTERRUPT_WORD_AUTO_CTXID[0]), 0, 0 }, + { "ixSQ_INTERRUPT_WORD_AUTO_HI", REG_SMC, 0x20c0, 0, &ixSQ_INTERRUPT_WORD_AUTO_HI[0], sizeof(ixSQ_INTERRUPT_WORD_AUTO_HI)/sizeof(ixSQ_INTERRUPT_WORD_AUTO_HI[0]), 0, 0 }, + { "ixSQ_INTERRUPT_WORD_AUTO_LO", REG_SMC, 0x20c0, 0, &ixSQ_INTERRUPT_WORD_AUTO_LO[0], sizeof(ixSQ_INTERRUPT_WORD_AUTO_LO)/sizeof(ixSQ_INTERRUPT_WORD_AUTO_LO[0]), 0, 0 }, + { "ixSQ_INTERRUPT_WORD_CMN_CTXID", REG_SMC, 0x20c0, 0, &ixSQ_INTERRUPT_WORD_CMN_CTXID[0], sizeof(ixSQ_INTERRUPT_WORD_CMN_CTXID)/sizeof(ixSQ_INTERRUPT_WORD_CMN_CTXID[0]), 0, 0 }, + { "ixSQ_INTERRUPT_WORD_CMN_HI", REG_SMC, 0x20c0, 0, &ixSQ_INTERRUPT_WORD_CMN_HI[0], sizeof(ixSQ_INTERRUPT_WORD_CMN_HI)/sizeof(ixSQ_INTERRUPT_WORD_CMN_HI[0]), 0, 0 }, + { "ixSQ_INTERRUPT_WORD_WAVE_CTXID", REG_SMC, 0x20c0, 0, &ixSQ_INTERRUPT_WORD_WAVE_CTXID[0], sizeof(ixSQ_INTERRUPT_WORD_WAVE_CTXID)/sizeof(ixSQ_INTERRUPT_WORD_WAVE_CTXID[0]), 0, 0 }, + { "ixSQ_INTERRUPT_WORD_WAVE_HI", REG_SMC, 0x20c0, 0, &ixSQ_INTERRUPT_WORD_WAVE_HI[0], sizeof(ixSQ_INTERRUPT_WORD_WAVE_HI)/sizeof(ixSQ_INTERRUPT_WORD_WAVE_HI[0]), 0, 0 }, + { "ixSQ_INTERRUPT_WORD_WAVE_LO", REG_SMC, 0x20c0, 0, &ixSQ_INTERRUPT_WORD_WAVE_LO[0], sizeof(ixSQ_INTERRUPT_WORD_WAVE_LO)/sizeof(ixSQ_INTERRUPT_WORD_WAVE_LO[0]), 0, 0 }, + { "ixDIDT_SQ_CTRL0", REG_SMC, 0x0000, 0, &ixDIDT_SQ_CTRL0[0], sizeof(ixDIDT_SQ_CTRL0)/sizeof(ixDIDT_SQ_CTRL0[0]), 0, 0 }, + { "ixDIDT_SQ_CTRL1", REG_SMC, 0x0001, 0, &ixDIDT_SQ_CTRL1[0], sizeof(ixDIDT_SQ_CTRL1)/sizeof(ixDIDT_SQ_CTRL1[0]), 0, 0 }, + { "ixDIDT_SQ_CTRL2", REG_SMC, 0x0002, 0, &ixDIDT_SQ_CTRL2[0], sizeof(ixDIDT_SQ_CTRL2)/sizeof(ixDIDT_SQ_CTRL2[0]), 0, 0 }, + { "ixDIDT_SQ_STALL_CTRL", REG_SMC, 0x0004, 0, &ixDIDT_SQ_STALL_CTRL[0], sizeof(ixDIDT_SQ_STALL_CTRL)/sizeof(ixDIDT_SQ_STALL_CTRL[0]), 0, 0 }, + { "ixDIDT_SQ_TUNING_CTRL", REG_SMC, 0x0005, 0, &ixDIDT_SQ_TUNING_CTRL[0], sizeof(ixDIDT_SQ_TUNING_CTRL)/sizeof(ixDIDT_SQ_TUNING_CTRL[0]), 0, 0 }, + { "ixDIDT_SQ_STALL_AUTO_RELEASE_CTRL", REG_SMC, 0x0006, 0, &ixDIDT_SQ_STALL_AUTO_RELEASE_CTRL[0], sizeof(ixDIDT_SQ_STALL_AUTO_RELEASE_CTRL)/sizeof(ixDIDT_SQ_STALL_AUTO_RELEASE_CTRL[0]), 0, 0 }, + { "ixDIDT_SQ_CTRL3", REG_SMC, 0x0007, 0, &ixDIDT_SQ_CTRL3[0], sizeof(ixDIDT_SQ_CTRL3)/sizeof(ixDIDT_SQ_CTRL3[0]), 0, 0 }, + { "ixDIDT_SQ_STALL_PATTERN_1_2", REG_SMC, 0x0008, 0, &ixDIDT_SQ_STALL_PATTERN_1_2[0], sizeof(ixDIDT_SQ_STALL_PATTERN_1_2)/sizeof(ixDIDT_SQ_STALL_PATTERN_1_2[0]), 0, 0 }, + { "ixDIDT_SQ_STALL_PATTERN_3_4", REG_SMC, 0x0009, 0, &ixDIDT_SQ_STALL_PATTERN_3_4[0], sizeof(ixDIDT_SQ_STALL_PATTERN_3_4)/sizeof(ixDIDT_SQ_STALL_PATTERN_3_4[0]), 0, 0 }, + { "ixDIDT_SQ_STALL_PATTERN_5_6", REG_SMC, 0x000a, 0, &ixDIDT_SQ_STALL_PATTERN_5_6[0], sizeof(ixDIDT_SQ_STALL_PATTERN_5_6)/sizeof(ixDIDT_SQ_STALL_PATTERN_5_6[0]), 0, 0 }, + { "ixDIDT_SQ_STALL_PATTERN_7", REG_SMC, 0x000b, 0, &ixDIDT_SQ_STALL_PATTERN_7[0], sizeof(ixDIDT_SQ_STALL_PATTERN_7)/sizeof(ixDIDT_SQ_STALL_PATTERN_7[0]), 0, 0 }, + { "ixDIDT_SQ_WEIGHT0_3", REG_SMC, 0x0010, 0, &ixDIDT_SQ_WEIGHT0_3[0], sizeof(ixDIDT_SQ_WEIGHT0_3)/sizeof(ixDIDT_SQ_WEIGHT0_3[0]), 0, 0 }, + { "ixDIDT_SQ_WEIGHT4_7", REG_SMC, 0x0011, 0, &ixDIDT_SQ_WEIGHT4_7[0], sizeof(ixDIDT_SQ_WEIGHT4_7)/sizeof(ixDIDT_SQ_WEIGHT4_7[0]), 0, 0 }, + { "ixDIDT_SQ_WEIGHT8_11", REG_SMC, 0x0012, 0, &ixDIDT_SQ_WEIGHT8_11[0], sizeof(ixDIDT_SQ_WEIGHT8_11)/sizeof(ixDIDT_SQ_WEIGHT8_11[0]), 0, 0 }, + { "ixDIDT_SQ_EDC_CTRL", REG_SMC, 0x0013, 0, &ixDIDT_SQ_EDC_CTRL[0], sizeof(ixDIDT_SQ_EDC_CTRL)/sizeof(ixDIDT_SQ_EDC_CTRL[0]), 0, 0 }, + { "ixDIDT_SQ_EDC_THRESHOLD", REG_SMC, 0x0014, 0, &ixDIDT_SQ_EDC_THRESHOLD[0], sizeof(ixDIDT_SQ_EDC_THRESHOLD)/sizeof(ixDIDT_SQ_EDC_THRESHOLD[0]), 0, 0 }, + { "ixDIDT_SQ_EDC_STALL_PATTERN_1_2", REG_SMC, 0x0015, 0, &ixDIDT_SQ_EDC_STALL_PATTERN_1_2[0], sizeof(ixDIDT_SQ_EDC_STALL_PATTERN_1_2)/sizeof(ixDIDT_SQ_EDC_STALL_PATTERN_1_2[0]), 0, 0 }, + { "ixDIDT_SQ_EDC_STALL_PATTERN_3_4", REG_SMC, 0x0016, 0, &ixDIDT_SQ_EDC_STALL_PATTERN_3_4[0], sizeof(ixDIDT_SQ_EDC_STALL_PATTERN_3_4)/sizeof(ixDIDT_SQ_EDC_STALL_PATTERN_3_4[0]), 0, 0 }, + { "ixDIDT_SQ_EDC_STALL_PATTERN_5_6", REG_SMC, 0x0017, 0, &ixDIDT_SQ_EDC_STALL_PATTERN_5_6[0], sizeof(ixDIDT_SQ_EDC_STALL_PATTERN_5_6)/sizeof(ixDIDT_SQ_EDC_STALL_PATTERN_5_6[0]), 0, 0 }, + { "ixDIDT_SQ_EDC_STALL_PATTERN_7", REG_SMC, 0x0018, 0, &ixDIDT_SQ_EDC_STALL_PATTERN_7[0], sizeof(ixDIDT_SQ_EDC_STALL_PATTERN_7)/sizeof(ixDIDT_SQ_EDC_STALL_PATTERN_7[0]), 0, 0 }, + { "ixDIDT_SQ_EDC_STATUS", REG_SMC, 0x0019, 0, &ixDIDT_SQ_EDC_STATUS[0], sizeof(ixDIDT_SQ_EDC_STATUS)/sizeof(ixDIDT_SQ_EDC_STATUS[0]), 0, 0 }, + { "ixDIDT_SQ_EDC_STALL_DELAY_1", REG_SMC, 0x001a, 0, &ixDIDT_SQ_EDC_STALL_DELAY_1[0], sizeof(ixDIDT_SQ_EDC_STALL_DELAY_1)/sizeof(ixDIDT_SQ_EDC_STALL_DELAY_1[0]), 0, 0 }, + { "ixDIDT_SQ_EDC_STALL_DELAY_2", REG_SMC, 0x001b, 0, &ixDIDT_SQ_EDC_STALL_DELAY_2[0], sizeof(ixDIDT_SQ_EDC_STALL_DELAY_2)/sizeof(ixDIDT_SQ_EDC_STALL_DELAY_2[0]), 0, 0 }, + { "ixDIDT_SQ_EDC_STALL_DELAY_3", REG_SMC, 0x001c, 0, &ixDIDT_SQ_EDC_STALL_DELAY_3[0], sizeof(ixDIDT_SQ_EDC_STALL_DELAY_3)/sizeof(ixDIDT_SQ_EDC_STALL_DELAY_3[0]), 0, 0 }, + { "ixDIDT_SQ_EDC_OVERFLOW", REG_SMC, 0x001e, 0, &ixDIDT_SQ_EDC_OVERFLOW[0], sizeof(ixDIDT_SQ_EDC_OVERFLOW)/sizeof(ixDIDT_SQ_EDC_OVERFLOW[0]), 0, 0 }, + { "ixDIDT_SQ_EDC_ROLLING_POWER_DELTA", REG_SMC, 0x001f, 0, &ixDIDT_SQ_EDC_ROLLING_POWER_DELTA[0], sizeof(ixDIDT_SQ_EDC_ROLLING_POWER_DELTA)/sizeof(ixDIDT_SQ_EDC_ROLLING_POWER_DELTA[0]), 0, 0 }, + { "ixDIDT_DB_CTRL0", REG_SMC, 0x0020, 0, &ixDIDT_DB_CTRL0[0], sizeof(ixDIDT_DB_CTRL0)/sizeof(ixDIDT_DB_CTRL0[0]), 0, 0 }, + { "ixDIDT_DB_CTRL1", REG_SMC, 0x0021, 0, &ixDIDT_DB_CTRL1[0], sizeof(ixDIDT_DB_CTRL1)/sizeof(ixDIDT_DB_CTRL1[0]), 0, 0 }, + { "ixDIDT_DB_CTRL2", REG_SMC, 0x0022, 0, &ixDIDT_DB_CTRL2[0], sizeof(ixDIDT_DB_CTRL2)/sizeof(ixDIDT_DB_CTRL2[0]), 0, 0 }, + { "ixDIDT_DB_STALL_CTRL", REG_SMC, 0x0024, 0, &ixDIDT_DB_STALL_CTRL[0], sizeof(ixDIDT_DB_STALL_CTRL)/sizeof(ixDIDT_DB_STALL_CTRL[0]), 0, 0 }, + { "ixDIDT_DB_TUNING_CTRL", REG_SMC, 0x0025, 0, &ixDIDT_DB_TUNING_CTRL[0], sizeof(ixDIDT_DB_TUNING_CTRL)/sizeof(ixDIDT_DB_TUNING_CTRL[0]), 0, 0 }, + { "ixDIDT_DB_STALL_AUTO_RELEASE_CTRL", REG_SMC, 0x0026, 0, &ixDIDT_DB_STALL_AUTO_RELEASE_CTRL[0], sizeof(ixDIDT_DB_STALL_AUTO_RELEASE_CTRL)/sizeof(ixDIDT_DB_STALL_AUTO_RELEASE_CTRL[0]), 0, 0 }, + { "ixDIDT_DB_CTRL3", REG_SMC, 0x0027, 0, &ixDIDT_DB_CTRL3[0], sizeof(ixDIDT_DB_CTRL3)/sizeof(ixDIDT_DB_CTRL3[0]), 0, 0 }, + { "ixDIDT_DB_STALL_PATTERN_1_2", REG_SMC, 0x0028, 0, &ixDIDT_DB_STALL_PATTERN_1_2[0], sizeof(ixDIDT_DB_STALL_PATTERN_1_2)/sizeof(ixDIDT_DB_STALL_PATTERN_1_2[0]), 0, 0 }, + { "ixDIDT_DB_STALL_PATTERN_3_4", REG_SMC, 0x0029, 0, &ixDIDT_DB_STALL_PATTERN_3_4[0], sizeof(ixDIDT_DB_STALL_PATTERN_3_4)/sizeof(ixDIDT_DB_STALL_PATTERN_3_4[0]), 0, 0 }, + { "ixDIDT_DB_STALL_PATTERN_5_6", REG_SMC, 0x002a, 0, &ixDIDT_DB_STALL_PATTERN_5_6[0], sizeof(ixDIDT_DB_STALL_PATTERN_5_6)/sizeof(ixDIDT_DB_STALL_PATTERN_5_6[0]), 0, 0 }, + { "ixDIDT_DB_STALL_PATTERN_7", REG_SMC, 0x002b, 0, &ixDIDT_DB_STALL_PATTERN_7[0], sizeof(ixDIDT_DB_STALL_PATTERN_7)/sizeof(ixDIDT_DB_STALL_PATTERN_7[0]), 0, 0 }, + { "ixDIDT_DB_WEIGHT0_3", REG_SMC, 0x0030, 0, &ixDIDT_DB_WEIGHT0_3[0], sizeof(ixDIDT_DB_WEIGHT0_3)/sizeof(ixDIDT_DB_WEIGHT0_3[0]), 0, 0 }, + { "ixDIDT_DB_WEIGHT4_7", REG_SMC, 0x0031, 0, &ixDIDT_DB_WEIGHT4_7[0], sizeof(ixDIDT_DB_WEIGHT4_7)/sizeof(ixDIDT_DB_WEIGHT4_7[0]), 0, 0 }, + { "ixDIDT_DB_WEIGHT8_11", REG_SMC, 0x0032, 0, &ixDIDT_DB_WEIGHT8_11[0], sizeof(ixDIDT_DB_WEIGHT8_11)/sizeof(ixDIDT_DB_WEIGHT8_11[0]), 0, 0 }, + { "ixDIDT_DB_EDC_CTRL", REG_SMC, 0x0033, 0, &ixDIDT_DB_EDC_CTRL[0], sizeof(ixDIDT_DB_EDC_CTRL)/sizeof(ixDIDT_DB_EDC_CTRL[0]), 0, 0 }, + { "ixDIDT_DB_EDC_THRESHOLD", REG_SMC, 0x0034, 0, &ixDIDT_DB_EDC_THRESHOLD[0], sizeof(ixDIDT_DB_EDC_THRESHOLD)/sizeof(ixDIDT_DB_EDC_THRESHOLD[0]), 0, 0 }, + { "ixDIDT_DB_EDC_STALL_PATTERN_1_2", REG_SMC, 0x0035, 0, &ixDIDT_DB_EDC_STALL_PATTERN_1_2[0], sizeof(ixDIDT_DB_EDC_STALL_PATTERN_1_2)/sizeof(ixDIDT_DB_EDC_STALL_PATTERN_1_2[0]), 0, 0 }, + { "ixDIDT_DB_EDC_STALL_PATTERN_3_4", REG_SMC, 0x0036, 0, &ixDIDT_DB_EDC_STALL_PATTERN_3_4[0], sizeof(ixDIDT_DB_EDC_STALL_PATTERN_3_4)/sizeof(ixDIDT_DB_EDC_STALL_PATTERN_3_4[0]), 0, 0 }, + { "ixDIDT_DB_EDC_STALL_PATTERN_5_6", REG_SMC, 0x0037, 0, &ixDIDT_DB_EDC_STALL_PATTERN_5_6[0], sizeof(ixDIDT_DB_EDC_STALL_PATTERN_5_6)/sizeof(ixDIDT_DB_EDC_STALL_PATTERN_5_6[0]), 0, 0 }, + { "ixDIDT_DB_EDC_STALL_PATTERN_7", REG_SMC, 0x0038, 0, &ixDIDT_DB_EDC_STALL_PATTERN_7[0], sizeof(ixDIDT_DB_EDC_STALL_PATTERN_7)/sizeof(ixDIDT_DB_EDC_STALL_PATTERN_7[0]), 0, 0 }, + { "ixDIDT_DB_EDC_STATUS", REG_SMC, 0x0039, 0, &ixDIDT_DB_EDC_STATUS[0], sizeof(ixDIDT_DB_EDC_STATUS)/sizeof(ixDIDT_DB_EDC_STATUS[0]), 0, 0 }, + { "ixDIDT_DB_EDC_STALL_DELAY_1", REG_SMC, 0x003a, 0, &ixDIDT_DB_EDC_STALL_DELAY_1[0], sizeof(ixDIDT_DB_EDC_STALL_DELAY_1)/sizeof(ixDIDT_DB_EDC_STALL_DELAY_1[0]), 0, 0 }, + { "ixDIDT_DB_EDC_OVERFLOW", REG_SMC, 0x003e, 0, &ixDIDT_DB_EDC_OVERFLOW[0], sizeof(ixDIDT_DB_EDC_OVERFLOW)/sizeof(ixDIDT_DB_EDC_OVERFLOW[0]), 0, 0 }, + { "ixDIDT_DB_EDC_ROLLING_POWER_DELTA", REG_SMC, 0x003f, 0, &ixDIDT_DB_EDC_ROLLING_POWER_DELTA[0], sizeof(ixDIDT_DB_EDC_ROLLING_POWER_DELTA)/sizeof(ixDIDT_DB_EDC_ROLLING_POWER_DELTA[0]), 0, 0 }, + { "ixDIDT_TD_CTRL0", REG_SMC, 0x0040, 0, &ixDIDT_TD_CTRL0[0], sizeof(ixDIDT_TD_CTRL0)/sizeof(ixDIDT_TD_CTRL0[0]), 0, 0 }, + { "ixDIDT_TD_CTRL1", REG_SMC, 0x0041, 0, &ixDIDT_TD_CTRL1[0], sizeof(ixDIDT_TD_CTRL1)/sizeof(ixDIDT_TD_CTRL1[0]), 0, 0 }, + { "ixDIDT_TD_CTRL2", REG_SMC, 0x0042, 0, &ixDIDT_TD_CTRL2[0], sizeof(ixDIDT_TD_CTRL2)/sizeof(ixDIDT_TD_CTRL2[0]), 0, 0 }, + { "ixDIDT_TD_STALL_CTRL", REG_SMC, 0x0044, 0, &ixDIDT_TD_STALL_CTRL[0], sizeof(ixDIDT_TD_STALL_CTRL)/sizeof(ixDIDT_TD_STALL_CTRL[0]), 0, 0 }, + { "ixDIDT_TD_TUNING_CTRL", REG_SMC, 0x0045, 0, &ixDIDT_TD_TUNING_CTRL[0], sizeof(ixDIDT_TD_TUNING_CTRL)/sizeof(ixDIDT_TD_TUNING_CTRL[0]), 0, 0 }, + { "ixDIDT_TD_STALL_AUTO_RELEASE_CTRL", REG_SMC, 0x0046, 0, &ixDIDT_TD_STALL_AUTO_RELEASE_CTRL[0], sizeof(ixDIDT_TD_STALL_AUTO_RELEASE_CTRL)/sizeof(ixDIDT_TD_STALL_AUTO_RELEASE_CTRL[0]), 0, 0 }, + { "ixDIDT_TD_CTRL3", REG_SMC, 0x0047, 0, &ixDIDT_TD_CTRL3[0], sizeof(ixDIDT_TD_CTRL3)/sizeof(ixDIDT_TD_CTRL3[0]), 0, 0 }, + { "ixDIDT_TD_STALL_PATTERN_1_2", REG_SMC, 0x0048, 0, &ixDIDT_TD_STALL_PATTERN_1_2[0], sizeof(ixDIDT_TD_STALL_PATTERN_1_2)/sizeof(ixDIDT_TD_STALL_PATTERN_1_2[0]), 0, 0 }, + { "ixDIDT_TD_STALL_PATTERN_3_4", REG_SMC, 0x0049, 0, &ixDIDT_TD_STALL_PATTERN_3_4[0], sizeof(ixDIDT_TD_STALL_PATTERN_3_4)/sizeof(ixDIDT_TD_STALL_PATTERN_3_4[0]), 0, 0 }, + { "ixDIDT_TD_STALL_PATTERN_5_6", REG_SMC, 0x004a, 0, &ixDIDT_TD_STALL_PATTERN_5_6[0], sizeof(ixDIDT_TD_STALL_PATTERN_5_6)/sizeof(ixDIDT_TD_STALL_PATTERN_5_6[0]), 0, 0 }, + { "ixDIDT_TD_STALL_PATTERN_7", REG_SMC, 0x004b, 0, &ixDIDT_TD_STALL_PATTERN_7[0], sizeof(ixDIDT_TD_STALL_PATTERN_7)/sizeof(ixDIDT_TD_STALL_PATTERN_7[0]), 0, 0 }, + { "ixDIDT_TD_WEIGHT0_3", REG_SMC, 0x0050, 0, &ixDIDT_TD_WEIGHT0_3[0], sizeof(ixDIDT_TD_WEIGHT0_3)/sizeof(ixDIDT_TD_WEIGHT0_3[0]), 0, 0 }, + { "ixDIDT_TD_WEIGHT4_7", REG_SMC, 0x0051, 0, &ixDIDT_TD_WEIGHT4_7[0], sizeof(ixDIDT_TD_WEIGHT4_7)/sizeof(ixDIDT_TD_WEIGHT4_7[0]), 0, 0 }, + { "ixDIDT_TD_WEIGHT8_11", REG_SMC, 0x0052, 0, &ixDIDT_TD_WEIGHT8_11[0], sizeof(ixDIDT_TD_WEIGHT8_11)/sizeof(ixDIDT_TD_WEIGHT8_11[0]), 0, 0 }, + { "ixDIDT_TD_EDC_CTRL", REG_SMC, 0x0053, 0, &ixDIDT_TD_EDC_CTRL[0], sizeof(ixDIDT_TD_EDC_CTRL)/sizeof(ixDIDT_TD_EDC_CTRL[0]), 0, 0 }, + { "ixDIDT_TD_EDC_THRESHOLD", REG_SMC, 0x0054, 0, &ixDIDT_TD_EDC_THRESHOLD[0], sizeof(ixDIDT_TD_EDC_THRESHOLD)/sizeof(ixDIDT_TD_EDC_THRESHOLD[0]), 0, 0 }, + { "ixDIDT_TD_EDC_STALL_PATTERN_1_2", REG_SMC, 0x0055, 0, &ixDIDT_TD_EDC_STALL_PATTERN_1_2[0], sizeof(ixDIDT_TD_EDC_STALL_PATTERN_1_2)/sizeof(ixDIDT_TD_EDC_STALL_PATTERN_1_2[0]), 0, 0 }, + { "ixDIDT_TD_EDC_STALL_PATTERN_3_4", REG_SMC, 0x0056, 0, &ixDIDT_TD_EDC_STALL_PATTERN_3_4[0], sizeof(ixDIDT_TD_EDC_STALL_PATTERN_3_4)/sizeof(ixDIDT_TD_EDC_STALL_PATTERN_3_4[0]), 0, 0 }, + { "ixDIDT_TD_EDC_STALL_PATTERN_5_6", REG_SMC, 0x0057, 0, &ixDIDT_TD_EDC_STALL_PATTERN_5_6[0], sizeof(ixDIDT_TD_EDC_STALL_PATTERN_5_6)/sizeof(ixDIDT_TD_EDC_STALL_PATTERN_5_6[0]), 0, 0 }, + { "ixDIDT_TD_EDC_STALL_PATTERN_7", REG_SMC, 0x0058, 0, &ixDIDT_TD_EDC_STALL_PATTERN_7[0], sizeof(ixDIDT_TD_EDC_STALL_PATTERN_7)/sizeof(ixDIDT_TD_EDC_STALL_PATTERN_7[0]), 0, 0 }, + { "ixDIDT_TD_EDC_STATUS", REG_SMC, 0x0059, 0, &ixDIDT_TD_EDC_STATUS[0], sizeof(ixDIDT_TD_EDC_STATUS)/sizeof(ixDIDT_TD_EDC_STATUS[0]), 0, 0 }, + { "ixDIDT_TD_EDC_STALL_DELAY_1", REG_SMC, 0x005a, 0, &ixDIDT_TD_EDC_STALL_DELAY_1[0], sizeof(ixDIDT_TD_EDC_STALL_DELAY_1)/sizeof(ixDIDT_TD_EDC_STALL_DELAY_1[0]), 0, 0 }, + { "ixDIDT_TD_EDC_STALL_DELAY_2", REG_SMC, 0x005b, 0, &ixDIDT_TD_EDC_STALL_DELAY_2[0], sizeof(ixDIDT_TD_EDC_STALL_DELAY_2)/sizeof(ixDIDT_TD_EDC_STALL_DELAY_2[0]), 0, 0 }, + { "ixDIDT_TD_EDC_STALL_DELAY_3", REG_SMC, 0x005c, 0, &ixDIDT_TD_EDC_STALL_DELAY_3[0], sizeof(ixDIDT_TD_EDC_STALL_DELAY_3)/sizeof(ixDIDT_TD_EDC_STALL_DELAY_3[0]), 0, 0 }, + { "ixDIDT_TD_EDC_OVERFLOW", REG_SMC, 0x005e, 0, &ixDIDT_TD_EDC_OVERFLOW[0], sizeof(ixDIDT_TD_EDC_OVERFLOW)/sizeof(ixDIDT_TD_EDC_OVERFLOW[0]), 0, 0 }, + { "ixDIDT_TD_EDC_ROLLING_POWER_DELTA", REG_SMC, 0x005f, 0, &ixDIDT_TD_EDC_ROLLING_POWER_DELTA[0], sizeof(ixDIDT_TD_EDC_ROLLING_POWER_DELTA)/sizeof(ixDIDT_TD_EDC_ROLLING_POWER_DELTA[0]), 0, 0 }, + { "ixDIDT_TCP_CTRL0", REG_SMC, 0x0060, 0, &ixDIDT_TCP_CTRL0[0], sizeof(ixDIDT_TCP_CTRL0)/sizeof(ixDIDT_TCP_CTRL0[0]), 0, 0 }, + { "ixDIDT_TCP_CTRL1", REG_SMC, 0x0061, 0, &ixDIDT_TCP_CTRL1[0], sizeof(ixDIDT_TCP_CTRL1)/sizeof(ixDIDT_TCP_CTRL1[0]), 0, 0 }, + { "ixDIDT_TCP_CTRL2", REG_SMC, 0x0062, 0, &ixDIDT_TCP_CTRL2[0], sizeof(ixDIDT_TCP_CTRL2)/sizeof(ixDIDT_TCP_CTRL2[0]), 0, 0 }, + { "ixDIDT_TCP_STALL_CTRL", REG_SMC, 0x0064, 0, &ixDIDT_TCP_STALL_CTRL[0], sizeof(ixDIDT_TCP_STALL_CTRL)/sizeof(ixDIDT_TCP_STALL_CTRL[0]), 0, 0 }, + { "ixDIDT_TCP_TUNING_CTRL", REG_SMC, 0x0065, 0, &ixDIDT_TCP_TUNING_CTRL[0], sizeof(ixDIDT_TCP_TUNING_CTRL)/sizeof(ixDIDT_TCP_TUNING_CTRL[0]), 0, 0 }, + { "ixDIDT_TCP_STALL_AUTO_RELEASE_CTRL", REG_SMC, 0x0066, 0, &ixDIDT_TCP_STALL_AUTO_RELEASE_CTRL[0], sizeof(ixDIDT_TCP_STALL_AUTO_RELEASE_CTRL)/sizeof(ixDIDT_TCP_STALL_AUTO_RELEASE_CTRL[0]), 0, 0 }, + { "ixDIDT_TCP_CTRL3", REG_SMC, 0x0067, 0, &ixDIDT_TCP_CTRL3[0], sizeof(ixDIDT_TCP_CTRL3)/sizeof(ixDIDT_TCP_CTRL3[0]), 0, 0 }, + { "ixDIDT_TCP_STALL_PATTERN_1_2", REG_SMC, 0x0068, 0, &ixDIDT_TCP_STALL_PATTERN_1_2[0], sizeof(ixDIDT_TCP_STALL_PATTERN_1_2)/sizeof(ixDIDT_TCP_STALL_PATTERN_1_2[0]), 0, 0 }, + { "ixDIDT_TCP_STALL_PATTERN_3_4", REG_SMC, 0x0069, 0, &ixDIDT_TCP_STALL_PATTERN_3_4[0], sizeof(ixDIDT_TCP_STALL_PATTERN_3_4)/sizeof(ixDIDT_TCP_STALL_PATTERN_3_4[0]), 0, 0 }, + { "ixDIDT_TCP_STALL_PATTERN_5_6", REG_SMC, 0x006a, 0, &ixDIDT_TCP_STALL_PATTERN_5_6[0], sizeof(ixDIDT_TCP_STALL_PATTERN_5_6)/sizeof(ixDIDT_TCP_STALL_PATTERN_5_6[0]), 0, 0 }, + { "ixDIDT_TCP_STALL_PATTERN_7", REG_SMC, 0x006b, 0, &ixDIDT_TCP_STALL_PATTERN_7[0], sizeof(ixDIDT_TCP_STALL_PATTERN_7)/sizeof(ixDIDT_TCP_STALL_PATTERN_7[0]), 0, 0 }, + { "ixDIDT_TCP_WEIGHT0_3", REG_SMC, 0x0070, 0, &ixDIDT_TCP_WEIGHT0_3[0], sizeof(ixDIDT_TCP_WEIGHT0_3)/sizeof(ixDIDT_TCP_WEIGHT0_3[0]), 0, 0 }, + { "ixDIDT_TCP_WEIGHT4_7", REG_SMC, 0x0071, 0, &ixDIDT_TCP_WEIGHT4_7[0], sizeof(ixDIDT_TCP_WEIGHT4_7)/sizeof(ixDIDT_TCP_WEIGHT4_7[0]), 0, 0 }, + { "ixDIDT_TCP_WEIGHT8_11", REG_SMC, 0x0072, 0, &ixDIDT_TCP_WEIGHT8_11[0], sizeof(ixDIDT_TCP_WEIGHT8_11)/sizeof(ixDIDT_TCP_WEIGHT8_11[0]), 0, 0 }, + { "ixDIDT_TCP_EDC_CTRL", REG_SMC, 0x0073, 0, &ixDIDT_TCP_EDC_CTRL[0], sizeof(ixDIDT_TCP_EDC_CTRL)/sizeof(ixDIDT_TCP_EDC_CTRL[0]), 0, 0 }, + { "ixDIDT_TCP_EDC_THRESHOLD", REG_SMC, 0x0074, 0, &ixDIDT_TCP_EDC_THRESHOLD[0], sizeof(ixDIDT_TCP_EDC_THRESHOLD)/sizeof(ixDIDT_TCP_EDC_THRESHOLD[0]), 0, 0 }, + { "ixDIDT_TCP_EDC_STALL_PATTERN_1_2", REG_SMC, 0x0075, 0, &ixDIDT_TCP_EDC_STALL_PATTERN_1_2[0], sizeof(ixDIDT_TCP_EDC_STALL_PATTERN_1_2)/sizeof(ixDIDT_TCP_EDC_STALL_PATTERN_1_2[0]), 0, 0 }, + { "ixDIDT_TCP_EDC_STALL_PATTERN_3_4", REG_SMC, 0x0076, 0, &ixDIDT_TCP_EDC_STALL_PATTERN_3_4[0], sizeof(ixDIDT_TCP_EDC_STALL_PATTERN_3_4)/sizeof(ixDIDT_TCP_EDC_STALL_PATTERN_3_4[0]), 0, 0 }, + { "ixDIDT_TCP_EDC_STALL_PATTERN_5_6", REG_SMC, 0x0077, 0, &ixDIDT_TCP_EDC_STALL_PATTERN_5_6[0], sizeof(ixDIDT_TCP_EDC_STALL_PATTERN_5_6)/sizeof(ixDIDT_TCP_EDC_STALL_PATTERN_5_6[0]), 0, 0 }, + { "ixDIDT_TCP_EDC_STALL_PATTERN_7", REG_SMC, 0x0078, 0, &ixDIDT_TCP_EDC_STALL_PATTERN_7[0], sizeof(ixDIDT_TCP_EDC_STALL_PATTERN_7)/sizeof(ixDIDT_TCP_EDC_STALL_PATTERN_7[0]), 0, 0 }, + { "ixDIDT_TCP_EDC_STATUS", REG_SMC, 0x0079, 0, &ixDIDT_TCP_EDC_STATUS[0], sizeof(ixDIDT_TCP_EDC_STATUS)/sizeof(ixDIDT_TCP_EDC_STATUS[0]), 0, 0 }, + { "ixDIDT_TCP_EDC_STALL_DELAY_1", REG_SMC, 0x007a, 0, &ixDIDT_TCP_EDC_STALL_DELAY_1[0], sizeof(ixDIDT_TCP_EDC_STALL_DELAY_1)/sizeof(ixDIDT_TCP_EDC_STALL_DELAY_1[0]), 0, 0 }, + { "ixDIDT_TCP_EDC_STALL_DELAY_2", REG_SMC, 0x007b, 0, &ixDIDT_TCP_EDC_STALL_DELAY_2[0], sizeof(ixDIDT_TCP_EDC_STALL_DELAY_2)/sizeof(ixDIDT_TCP_EDC_STALL_DELAY_2[0]), 0, 0 }, + { "ixDIDT_TCP_EDC_STALL_DELAY_3", REG_SMC, 0x007c, 0, &ixDIDT_TCP_EDC_STALL_DELAY_3[0], sizeof(ixDIDT_TCP_EDC_STALL_DELAY_3)/sizeof(ixDIDT_TCP_EDC_STALL_DELAY_3[0]), 0, 0 }, + { "ixDIDT_TCP_EDC_OVERFLOW", REG_SMC, 0x007e, 0, &ixDIDT_TCP_EDC_OVERFLOW[0], sizeof(ixDIDT_TCP_EDC_OVERFLOW)/sizeof(ixDIDT_TCP_EDC_OVERFLOW[0]), 0, 0 }, + { "ixDIDT_TCP_EDC_ROLLING_POWER_DELTA", REG_SMC, 0x007f, 0, &ixDIDT_TCP_EDC_ROLLING_POWER_DELTA[0], sizeof(ixDIDT_TCP_EDC_ROLLING_POWER_DELTA)/sizeof(ixDIDT_TCP_EDC_ROLLING_POWER_DELTA[0]), 0, 0 }, + { "ixDIDT_DBR_CTRL0", REG_SMC, 0x0080, 0, &ixDIDT_DBR_CTRL0[0], sizeof(ixDIDT_DBR_CTRL0)/sizeof(ixDIDT_DBR_CTRL0[0]), 0, 0 }, + { "ixDIDT_DBR_CTRL1", REG_SMC, 0x0081, 0, &ixDIDT_DBR_CTRL1[0], sizeof(ixDIDT_DBR_CTRL1)/sizeof(ixDIDT_DBR_CTRL1[0]), 0, 0 }, + { "ixDIDT_DBR_CTRL2", REG_SMC, 0x0082, 0, &ixDIDT_DBR_CTRL2[0], sizeof(ixDIDT_DBR_CTRL2)/sizeof(ixDIDT_DBR_CTRL2[0]), 0, 0 }, + { "ixDIDT_DBR_STALL_CTRL", REG_SMC, 0x0084, 0, &ixDIDT_DBR_STALL_CTRL[0], sizeof(ixDIDT_DBR_STALL_CTRL)/sizeof(ixDIDT_DBR_STALL_CTRL[0]), 0, 0 }, + { "ixDIDT_DBR_TUNING_CTRL", REG_SMC, 0x0085, 0, &ixDIDT_DBR_TUNING_CTRL[0], sizeof(ixDIDT_DBR_TUNING_CTRL)/sizeof(ixDIDT_DBR_TUNING_CTRL[0]), 0, 0 }, + { "ixDIDT_DBR_STALL_AUTO_RELEASE_CTRL", REG_SMC, 0x0086, 0, &ixDIDT_DBR_STALL_AUTO_RELEASE_CTRL[0], sizeof(ixDIDT_DBR_STALL_AUTO_RELEASE_CTRL)/sizeof(ixDIDT_DBR_STALL_AUTO_RELEASE_CTRL[0]), 0, 0 }, + { "ixDIDT_DBR_CTRL3", REG_SMC, 0x0087, 0, &ixDIDT_DBR_CTRL3[0], sizeof(ixDIDT_DBR_CTRL3)/sizeof(ixDIDT_DBR_CTRL3[0]), 0, 0 }, + { "ixDIDT_DBR_STALL_PATTERN_1_2", REG_SMC, 0x0088, 0, &ixDIDT_DBR_STALL_PATTERN_1_2[0], sizeof(ixDIDT_DBR_STALL_PATTERN_1_2)/sizeof(ixDIDT_DBR_STALL_PATTERN_1_2[0]), 0, 0 }, + { "ixDIDT_DBR_STALL_PATTERN_3_4", REG_SMC, 0x0089, 0, &ixDIDT_DBR_STALL_PATTERN_3_4[0], sizeof(ixDIDT_DBR_STALL_PATTERN_3_4)/sizeof(ixDIDT_DBR_STALL_PATTERN_3_4[0]), 0, 0 }, + { "ixDIDT_DBR_STALL_PATTERN_5_6", REG_SMC, 0x008a, 0, &ixDIDT_DBR_STALL_PATTERN_5_6[0], sizeof(ixDIDT_DBR_STALL_PATTERN_5_6)/sizeof(ixDIDT_DBR_STALL_PATTERN_5_6[0]), 0, 0 }, + { "ixDIDT_DBR_STALL_PATTERN_7", REG_SMC, 0x008b, 0, &ixDIDT_DBR_STALL_PATTERN_7[0], sizeof(ixDIDT_DBR_STALL_PATTERN_7)/sizeof(ixDIDT_DBR_STALL_PATTERN_7[0]), 0, 0 }, + { "ixDIDT_DBR_WEIGHT0_3", REG_SMC, 0x0090, 0, &ixDIDT_DBR_WEIGHT0_3[0], sizeof(ixDIDT_DBR_WEIGHT0_3)/sizeof(ixDIDT_DBR_WEIGHT0_3[0]), 0, 0 }, + { "ixDIDT_DBR_WEIGHT4_7", REG_SMC, 0x0091, 0, &ixDIDT_DBR_WEIGHT4_7[0], sizeof(ixDIDT_DBR_WEIGHT4_7)/sizeof(ixDIDT_DBR_WEIGHT4_7[0]), 0, 0 }, + { "ixDIDT_DBR_WEIGHT8_11", REG_SMC, 0x0092, 0, &ixDIDT_DBR_WEIGHT8_11[0], sizeof(ixDIDT_DBR_WEIGHT8_11)/sizeof(ixDIDT_DBR_WEIGHT8_11[0]), 0, 0 }, + { "ixDIDT_DBR_EDC_CTRL", REG_SMC, 0x0093, 0, &ixDIDT_DBR_EDC_CTRL[0], sizeof(ixDIDT_DBR_EDC_CTRL)/sizeof(ixDIDT_DBR_EDC_CTRL[0]), 0, 0 }, + { "ixDIDT_DBR_EDC_THRESHOLD", REG_SMC, 0x0094, 0, &ixDIDT_DBR_EDC_THRESHOLD[0], sizeof(ixDIDT_DBR_EDC_THRESHOLD)/sizeof(ixDIDT_DBR_EDC_THRESHOLD[0]), 0, 0 }, + { "ixDIDT_DBR_EDC_STALL_PATTERN_1_2", REG_SMC, 0x0095, 0, &ixDIDT_DBR_EDC_STALL_PATTERN_1_2[0], sizeof(ixDIDT_DBR_EDC_STALL_PATTERN_1_2)/sizeof(ixDIDT_DBR_EDC_STALL_PATTERN_1_2[0]), 0, 0 }, + { "ixDIDT_DBR_EDC_STALL_PATTERN_3_4", REG_SMC, 0x0096, 0, &ixDIDT_DBR_EDC_STALL_PATTERN_3_4[0], sizeof(ixDIDT_DBR_EDC_STALL_PATTERN_3_4)/sizeof(ixDIDT_DBR_EDC_STALL_PATTERN_3_4[0]), 0, 0 }, + { "ixDIDT_DBR_EDC_STALL_PATTERN_5_6", REG_SMC, 0x0097, 0, &ixDIDT_DBR_EDC_STALL_PATTERN_5_6[0], sizeof(ixDIDT_DBR_EDC_STALL_PATTERN_5_6)/sizeof(ixDIDT_DBR_EDC_STALL_PATTERN_5_6[0]), 0, 0 }, + { "ixDIDT_DBR_EDC_STALL_PATTERN_7", REG_SMC, 0x0098, 0, &ixDIDT_DBR_EDC_STALL_PATTERN_7[0], sizeof(ixDIDT_DBR_EDC_STALL_PATTERN_7)/sizeof(ixDIDT_DBR_EDC_STALL_PATTERN_7[0]), 0, 0 }, + { "ixDIDT_DBR_EDC_STATUS", REG_SMC, 0x0099, 0, &ixDIDT_DBR_EDC_STATUS[0], sizeof(ixDIDT_DBR_EDC_STATUS)/sizeof(ixDIDT_DBR_EDC_STATUS[0]), 0, 0 }, + { "ixDIDT_DBR_EDC_STALL_DELAY_1", REG_SMC, 0x009a, 0, &ixDIDT_DBR_EDC_STALL_DELAY_1[0], sizeof(ixDIDT_DBR_EDC_STALL_DELAY_1)/sizeof(ixDIDT_DBR_EDC_STALL_DELAY_1[0]), 0, 0 }, + { "ixDIDT_DBR_EDC_OVERFLOW", REG_SMC, 0x009e, 0, &ixDIDT_DBR_EDC_OVERFLOW[0], sizeof(ixDIDT_DBR_EDC_OVERFLOW)/sizeof(ixDIDT_DBR_EDC_OVERFLOW[0]), 0, 0 }, + { "ixDIDT_DBR_EDC_ROLLING_POWER_DELTA", REG_SMC, 0x009f, 0, &ixDIDT_DBR_EDC_ROLLING_POWER_DELTA[0], sizeof(ixDIDT_DBR_EDC_ROLLING_POWER_DELTA)/sizeof(ixDIDT_DBR_EDC_ROLLING_POWER_DELTA[0]), 0, 0 }, + { "ixDIDT_SQ_STALL_EVENT_COUNTER", REG_SMC, 0x00a0, 0, &ixDIDT_SQ_STALL_EVENT_COUNTER[0], sizeof(ixDIDT_SQ_STALL_EVENT_COUNTER)/sizeof(ixDIDT_SQ_STALL_EVENT_COUNTER[0]), 0, 0 }, + { "ixDIDT_DB_STALL_EVENT_COUNTER", REG_SMC, 0x00a1, 0, &ixDIDT_DB_STALL_EVENT_COUNTER[0], sizeof(ixDIDT_DB_STALL_EVENT_COUNTER)/sizeof(ixDIDT_DB_STALL_EVENT_COUNTER[0]), 0, 0 }, + { "ixDIDT_TD_STALL_EVENT_COUNTER", REG_SMC, 0x00a2, 0, &ixDIDT_TD_STALL_EVENT_COUNTER[0], sizeof(ixDIDT_TD_STALL_EVENT_COUNTER)/sizeof(ixDIDT_TD_STALL_EVENT_COUNTER[0]), 0, 0 }, + { "ixDIDT_TCP_STALL_EVENT_COUNTER", REG_SMC, 0x00a3, 0, &ixDIDT_TCP_STALL_EVENT_COUNTER[0], sizeof(ixDIDT_TCP_STALL_EVENT_COUNTER)/sizeof(ixDIDT_TCP_STALL_EVENT_COUNTER[0]), 0, 0 }, + { "ixDIDT_DBR_STALL_EVENT_COUNTER", REG_SMC, 0x00a4, 0, &ixDIDT_DBR_STALL_EVENT_COUNTER[0], sizeof(ixDIDT_DBR_STALL_EVENT_COUNTER)/sizeof(ixDIDT_DBR_STALL_EVENT_COUNTER[0]), 0, 0 }, diff --git a/src/lib/ip/mmhub91.c b/src/lib/ip/mmhub91.c new file mode 100644 index 0000000..5274a4f --- /dev/null +++ b/src/lib/ip/mmhub91.c @@ -0,0 +1,68 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Tom St Denis <tom.stdenis@amd.com> + * + */ +#include "umr.h" + +#include "mmhub91_bits.i" + +static const struct umr_reg_soc15 mmhub91_registers[] = { +#include "mmhub91_regs.i" +}; + +static int grant(struct umr_asic *asic) +{ + (void)asic; + return 0; +} + +static int deny(struct umr_asic *asic) +{ + (void)asic; + return -1; +} + +struct umr_ip_block *umr_create_mmhub91(struct umr_ip_offsets_soc15 *soc15_offsets, struct umr_options *options) +{ + struct umr_ip_block *ip; + + ip = calloc(1, sizeof *ip); + if (!ip) + return NULL; + + ip->ipname = "mmhub91"; + ip->no_regs = sizeof(mmhub91_registers)/sizeof(mmhub91_registers[0]); + ip->regs = calloc(ip->no_regs, sizeof(ip->regs[0])); + if (!ip->regs) { + free(ip); + return NULL; + } + ip->grant = (options->risky >= 1) ? grant : deny; + + if (umr_transfer_soc15_to_reg(options, soc15_offsets, "MMHUB", mmhub91_registers, ip)) { + free(ip); + return NULL; + } + + return ip; +} diff --git a/src/lib/ip/mmhub91_bits.i b/src/lib/ip/mmhub91_bits.i new file mode 100644 index 0000000..e63fc77 --- /dev/null +++ b/src/lib/ip/mmhub91_bits.i @@ -0,0 +1,6279 @@ +static struct umr_bitfield mmDAGB0_RDCLI0[] = { + { "VIRT_CHAN", 0, 2, &umr_bitfield_default }, + { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default }, + { "URG_HIGH", 4, 7, &umr_bitfield_default }, + { "URG_LOW", 8, 11, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default }, + { "MAX_BW", 13, 20, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default }, + { "MIN_BW", 22, 24, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default }, + { "MAX_OSD", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RDCLI1[] = { + { "VIRT_CHAN", 0, 2, &umr_bitfield_default }, + { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default }, + { "URG_HIGH", 4, 7, &umr_bitfield_default }, + { "URG_LOW", 8, 11, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default }, + { "MAX_BW", 13, 20, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default }, + { "MIN_BW", 22, 24, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default }, + { "MAX_OSD", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RDCLI2[] = { + { "VIRT_CHAN", 0, 2, &umr_bitfield_default }, + { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default }, + { "URG_HIGH", 4, 7, &umr_bitfield_default }, + { "URG_LOW", 8, 11, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default }, + { "MAX_BW", 13, 20, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default }, + { "MIN_BW", 22, 24, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default }, + { "MAX_OSD", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RDCLI3[] = { + { "VIRT_CHAN", 0, 2, &umr_bitfield_default }, + { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default }, + { "URG_HIGH", 4, 7, &umr_bitfield_default }, + { "URG_LOW", 8, 11, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default }, + { "MAX_BW", 13, 20, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default }, + { "MIN_BW", 22, 24, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default }, + { "MAX_OSD", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RDCLI4[] = { + { "VIRT_CHAN", 0, 2, &umr_bitfield_default }, + { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default }, + { "URG_HIGH", 4, 7, &umr_bitfield_default }, + { "URG_LOW", 8, 11, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default }, + { "MAX_BW", 13, 20, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default }, + { "MIN_BW", 22, 24, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default }, + { "MAX_OSD", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RDCLI5[] = { + { "VIRT_CHAN", 0, 2, &umr_bitfield_default }, + { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default }, + { "URG_HIGH", 4, 7, &umr_bitfield_default }, + { "URG_LOW", 8, 11, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default }, + { "MAX_BW", 13, 20, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default }, + { "MIN_BW", 22, 24, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default }, + { "MAX_OSD", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RDCLI6[] = { + { "VIRT_CHAN", 0, 2, &umr_bitfield_default }, + { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default }, + { "URG_HIGH", 4, 7, &umr_bitfield_default }, + { "URG_LOW", 8, 11, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default }, + { "MAX_BW", 13, 20, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default }, + { "MIN_BW", 22, 24, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default }, + { "MAX_OSD", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RDCLI7[] = { + { "VIRT_CHAN", 0, 2, &umr_bitfield_default }, + { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default }, + { "URG_HIGH", 4, 7, &umr_bitfield_default }, + { "URG_LOW", 8, 11, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default }, + { "MAX_BW", 13, 20, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default }, + { "MIN_BW", 22, 24, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default }, + { "MAX_OSD", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RDCLI8[] = { + { "VIRT_CHAN", 0, 2, &umr_bitfield_default }, + { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default }, + { "URG_HIGH", 4, 7, &umr_bitfield_default }, + { "URG_LOW", 8, 11, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default }, + { "MAX_BW", 13, 20, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default }, + { "MIN_BW", 22, 24, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default }, + { "MAX_OSD", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RDCLI9[] = { + { "VIRT_CHAN", 0, 2, &umr_bitfield_default }, + { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default }, + { "URG_HIGH", 4, 7, &umr_bitfield_default }, + { "URG_LOW", 8, 11, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default }, + { "MAX_BW", 13, 20, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default }, + { "MIN_BW", 22, 24, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default }, + { "MAX_OSD", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RDCLI10[] = { + { "VIRT_CHAN", 0, 2, &umr_bitfield_default }, + { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default }, + { "URG_HIGH", 4, 7, &umr_bitfield_default }, + { "URG_LOW", 8, 11, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default }, + { "MAX_BW", 13, 20, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default }, + { "MIN_BW", 22, 24, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default }, + { "MAX_OSD", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RDCLI11[] = { + { "VIRT_CHAN", 0, 2, &umr_bitfield_default }, + { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default }, + { "URG_HIGH", 4, 7, &umr_bitfield_default }, + { "URG_LOW", 8, 11, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default }, + { "MAX_BW", 13, 20, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default }, + { "MIN_BW", 22, 24, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default }, + { "MAX_OSD", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RDCLI12[] = { + { "VIRT_CHAN", 0, 2, &umr_bitfield_default }, + { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default }, + { "URG_HIGH", 4, 7, &umr_bitfield_default }, + { "URG_LOW", 8, 11, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default }, + { "MAX_BW", 13, 20, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default }, + { "MIN_BW", 22, 24, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default }, + { "MAX_OSD", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RDCLI13[] = { + { "VIRT_CHAN", 0, 2, &umr_bitfield_default }, + { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default }, + { "URG_HIGH", 4, 7, &umr_bitfield_default }, + { "URG_LOW", 8, 11, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default }, + { "MAX_BW", 13, 20, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default }, + { "MIN_BW", 22, 24, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default }, + { "MAX_OSD", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RDCLI14[] = { + { "VIRT_CHAN", 0, 2, &umr_bitfield_default }, + { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default }, + { "URG_HIGH", 4, 7, &umr_bitfield_default }, + { "URG_LOW", 8, 11, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default }, + { "MAX_BW", 13, 20, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default }, + { "MIN_BW", 22, 24, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default }, + { "MAX_OSD", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RDCLI15[] = { + { "VIRT_CHAN", 0, 2, &umr_bitfield_default }, + { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default }, + { "URG_HIGH", 4, 7, &umr_bitfield_default }, + { "URG_LOW", 8, 11, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default }, + { "MAX_BW", 13, 20, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default }, + { "MIN_BW", 22, 24, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default }, + { "MAX_OSD", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RDCLI16[] = { + { "VIRT_CHAN", 0, 2, &umr_bitfield_default }, + { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default }, + { "URG_HIGH", 4, 7, &umr_bitfield_default }, + { "URG_LOW", 8, 11, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default }, + { "MAX_BW", 13, 20, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default }, + { "MIN_BW", 22, 24, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default }, + { "MAX_OSD", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RDCLI17[] = { + { "VIRT_CHAN", 0, 2, &umr_bitfield_default }, + { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default }, + { "URG_HIGH", 4, 7, &umr_bitfield_default }, + { "URG_LOW", 8, 11, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default }, + { "MAX_BW", 13, 20, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default }, + { "MIN_BW", 22, 24, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default }, + { "MAX_OSD", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RDCLI18[] = { + { "VIRT_CHAN", 0, 2, &umr_bitfield_default }, + { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default }, + { "URG_HIGH", 4, 7, &umr_bitfield_default }, + { "URG_LOW", 8, 11, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default }, + { "MAX_BW", 13, 20, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default }, + { "MIN_BW", 22, 24, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default }, + { "MAX_OSD", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RDCLI19[] = { + { "VIRT_CHAN", 0, 2, &umr_bitfield_default }, + { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default }, + { "URG_HIGH", 4, 7, &umr_bitfield_default }, + { "URG_LOW", 8, 11, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default }, + { "MAX_BW", 13, 20, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default }, + { "MIN_BW", 22, 24, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default }, + { "MAX_OSD", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RDCLI20[] = { + { "VIRT_CHAN", 0, 2, &umr_bitfield_default }, + { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default }, + { "URG_HIGH", 4, 7, &umr_bitfield_default }, + { "URG_LOW", 8, 11, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default }, + { "MAX_BW", 13, 20, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default }, + { "MIN_BW", 22, 24, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default }, + { "MAX_OSD", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RDCLI21[] = { + { "VIRT_CHAN", 0, 2, &umr_bitfield_default }, + { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default }, + { "URG_HIGH", 4, 7, &umr_bitfield_default }, + { "URG_LOW", 8, 11, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default }, + { "MAX_BW", 13, 20, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default }, + { "MIN_BW", 22, 24, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default }, + { "MAX_OSD", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RDCLI22[] = { + { "VIRT_CHAN", 0, 2, &umr_bitfield_default }, + { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default }, + { "URG_HIGH", 4, 7, &umr_bitfield_default }, + { "URG_LOW", 8, 11, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default }, + { "MAX_BW", 13, 20, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default }, + { "MIN_BW", 22, 24, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default }, + { "MAX_OSD", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RDCLI23[] = { + { "VIRT_CHAN", 0, 2, &umr_bitfield_default }, + { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default }, + { "URG_HIGH", 4, 7, &umr_bitfield_default }, + { "URG_LOW", 8, 11, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default }, + { "MAX_BW", 13, 20, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default }, + { "MIN_BW", 22, 24, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default }, + { "MAX_OSD", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RDCLI24[] = { + { "VIRT_CHAN", 0, 2, &umr_bitfield_default }, + { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default }, + { "URG_HIGH", 4, 7, &umr_bitfield_default }, + { "URG_LOW", 8, 11, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default }, + { "MAX_BW", 13, 20, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default }, + { "MIN_BW", 22, 24, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default }, + { "MAX_OSD", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RDCLI25[] = { + { "VIRT_CHAN", 0, 2, &umr_bitfield_default }, + { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default }, + { "URG_HIGH", 4, 7, &umr_bitfield_default }, + { "URG_LOW", 8, 11, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default }, + { "MAX_BW", 13, 20, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default }, + { "MIN_BW", 22, 24, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default }, + { "MAX_OSD", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RDCLI26[] = { + { "VIRT_CHAN", 0, 2, &umr_bitfield_default }, + { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default }, + { "URG_HIGH", 4, 7, &umr_bitfield_default }, + { "URG_LOW", 8, 11, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default }, + { "MAX_BW", 13, 20, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default }, + { "MIN_BW", 22, 24, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default }, + { "MAX_OSD", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RDCLI27[] = { + { "VIRT_CHAN", 0, 2, &umr_bitfield_default }, + { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default }, + { "URG_HIGH", 4, 7, &umr_bitfield_default }, + { "URG_LOW", 8, 11, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default }, + { "MAX_BW", 13, 20, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default }, + { "MIN_BW", 22, 24, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default }, + { "MAX_OSD", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RDCLI28[] = { + { "VIRT_CHAN", 0, 2, &umr_bitfield_default }, + { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default }, + { "URG_HIGH", 4, 7, &umr_bitfield_default }, + { "URG_LOW", 8, 11, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default }, + { "MAX_BW", 13, 20, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default }, + { "MIN_BW", 22, 24, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default }, + { "MAX_OSD", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RDCLI29[] = { + { "VIRT_CHAN", 0, 2, &umr_bitfield_default }, + { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default }, + { "URG_HIGH", 4, 7, &umr_bitfield_default }, + { "URG_LOW", 8, 11, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default }, + { "MAX_BW", 13, 20, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default }, + { "MIN_BW", 22, 24, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default }, + { "MAX_OSD", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RDCLI30[] = { + { "VIRT_CHAN", 0, 2, &umr_bitfield_default }, + { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default }, + { "URG_HIGH", 4, 7, &umr_bitfield_default }, + { "URG_LOW", 8, 11, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default }, + { "MAX_BW", 13, 20, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default }, + { "MIN_BW", 22, 24, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default }, + { "MAX_OSD", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RDCLI31[] = { + { "VIRT_CHAN", 0, 2, &umr_bitfield_default }, + { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default }, + { "URG_HIGH", 4, 7, &umr_bitfield_default }, + { "URG_LOW", 8, 11, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default }, + { "MAX_BW", 13, 20, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default }, + { "MIN_BW", 22, 24, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default }, + { "MAX_OSD", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RD_CNTL[] = { + { "SCLK_FREQ", 0, 3, &umr_bitfield_default }, + { "CLI_MAX_BW_WINDOW", 4, 9, &umr_bitfield_default }, + { "VC_MAX_BW_WINDOW", 10, 15, &umr_bitfield_default }, + { "IO_LEVEL_OVERRIDE_ENABLE", 16, 16, &umr_bitfield_default }, + { "IO_LEVEL", 17, 19, &umr_bitfield_default }, + { "IO_LEVEL_COMPLY_VC", 20, 22, &umr_bitfield_default }, + { "SHARE_VC_NUM", 23, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RD_GMI_CNTL[] = { + { "EA_CREDIT", 0, 5, &umr_bitfield_default }, + { "LEVEL", 6, 8, &umr_bitfield_default }, + { "MAX_BURST", 9, 12, &umr_bitfield_default }, + { "LAZY_TIMER", 13, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RD_ADDR_DAGB[] = { + { "DAGB_ENABLE", 0, 2, &umr_bitfield_default }, + { "ENABLE_JUMP_AHEAD", 3, 5, &umr_bitfield_default }, + { "DISABLE_SELF_INIT", 6, 6, &umr_bitfield_default }, + { "WHOAMI", 7, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST[] = { + { "VC0", 0, 3, &umr_bitfield_default }, + { "VC1", 4, 7, &umr_bitfield_default }, + { "VC2", 8, 11, &umr_bitfield_default }, + { "VC3", 12, 15, &umr_bitfield_default }, + { "VC4", 16, 19, &umr_bitfield_default }, + { "VC5", 20, 23, &umr_bitfield_default }, + { "VC6", 24, 27, &umr_bitfield_default }, + { "VC7", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER[] = { + { "VC0", 0, 3, &umr_bitfield_default }, + { "VC1", 4, 7, &umr_bitfield_default }, + { "VC2", 8, 11, &umr_bitfield_default }, + { "VC3", 12, 15, &umr_bitfield_default }, + { "VC4", 16, 19, &umr_bitfield_default }, + { "VC5", 20, 23, &umr_bitfield_default }, + { "VC6", 24, 27, &umr_bitfield_default }, + { "VC7", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RD_CGTT_CLK_CTRL[] = { + { "ON_DELAY", 0, 3, &umr_bitfield_default }, + { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE", 22, 22, &umr_bitfield_default }, + { "LS_OVERRIDE", 27, 27, &umr_bitfield_default }, + { "LS_OVERRIDE_WRITE", 28, 28, &umr_bitfield_default }, + { "LS_OVERRIDE_READ", 29, 29, &umr_bitfield_default }, + { "LS_OVERRIDE_RETURN", 30, 30, &umr_bitfield_default }, + { "LS_OVERRIDE_REGISTER", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL[] = { + { "ON_DELAY", 0, 3, &umr_bitfield_default }, + { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE", 22, 22, &umr_bitfield_default }, + { "LS_OVERRIDE", 27, 27, &umr_bitfield_default }, + { "LS_OVERRIDE_WRITE", 28, 28, &umr_bitfield_default }, + { "LS_OVERRIDE_READ", 29, 29, &umr_bitfield_default }, + { "LS_OVERRIDE_RETURN", 30, 30, &umr_bitfield_default }, + { "LS_OVERRIDE_REGISTER", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL[] = { + { "ON_DELAY", 0, 3, &umr_bitfield_default }, + { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE", 22, 22, &umr_bitfield_default }, + { "LS_OVERRIDE", 27, 27, &umr_bitfield_default }, + { "LS_OVERRIDE_WRITE", 28, 28, &umr_bitfield_default }, + { "LS_OVERRIDE_READ", 29, 29, &umr_bitfield_default }, + { "LS_OVERRIDE_RETURN", 30, 30, &umr_bitfield_default }, + { "LS_OVERRIDE_REGISTER", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RD_ADDR_DAGB_MAX_BURST0[] = { + { "CLIENT0", 0, 3, &umr_bitfield_default }, + { "CLIENT1", 4, 7, &umr_bitfield_default }, + { "CLIENT2", 8, 11, &umr_bitfield_default }, + { "CLIENT3", 12, 15, &umr_bitfield_default }, + { "CLIENT4", 16, 19, &umr_bitfield_default }, + { "CLIENT5", 20, 23, &umr_bitfield_default }, + { "CLIENT6", 24, 27, &umr_bitfield_default }, + { "CLIENT7", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0[] = { + { "CLIENT0", 0, 3, &umr_bitfield_default }, + { "CLIENT1", 4, 7, &umr_bitfield_default }, + { "CLIENT2", 8, 11, &umr_bitfield_default }, + { "CLIENT3", 12, 15, &umr_bitfield_default }, + { "CLIENT4", 16, 19, &umr_bitfield_default }, + { "CLIENT5", 20, 23, &umr_bitfield_default }, + { "CLIENT6", 24, 27, &umr_bitfield_default }, + { "CLIENT7", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RD_ADDR_DAGB_MAX_BURST1[] = { + { "CLIENT8", 0, 3, &umr_bitfield_default }, + { "CLIENT9", 4, 7, &umr_bitfield_default }, + { "CLIENT10", 8, 11, &umr_bitfield_default }, + { "CLIENT11", 12, 15, &umr_bitfield_default }, + { "CLIENT12", 16, 19, &umr_bitfield_default }, + { "CLIENT13", 20, 23, &umr_bitfield_default }, + { "CLIENT14", 24, 27, &umr_bitfield_default }, + { "CLIENT15", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1[] = { + { "CLIENT8", 0, 3, &umr_bitfield_default }, + { "CLIENT9", 4, 7, &umr_bitfield_default }, + { "CLIENT10", 8, 11, &umr_bitfield_default }, + { "CLIENT11", 12, 15, &umr_bitfield_default }, + { "CLIENT12", 16, 19, &umr_bitfield_default }, + { "CLIENT13", 20, 23, &umr_bitfield_default }, + { "CLIENT14", 24, 27, &umr_bitfield_default }, + { "CLIENT15", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RD_ADDR_DAGB_MAX_BURST2[] = { + { "CLIENT16", 0, 3, &umr_bitfield_default }, + { "CLIENT17", 4, 7, &umr_bitfield_default }, + { "CLIENT18", 8, 11, &umr_bitfield_default }, + { "CLIENT19", 12, 15, &umr_bitfield_default }, + { "CLIENT20", 16, 19, &umr_bitfield_default }, + { "CLIENT21", 20, 23, &umr_bitfield_default }, + { "CLIENT22", 24, 27, &umr_bitfield_default }, + { "CLIENT23", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER2[] = { + { "CLIENT16", 0, 3, &umr_bitfield_default }, + { "CLIENT17", 4, 7, &umr_bitfield_default }, + { "CLIENT18", 8, 11, &umr_bitfield_default }, + { "CLIENT19", 12, 15, &umr_bitfield_default }, + { "CLIENT20", 16, 19, &umr_bitfield_default }, + { "CLIENT21", 20, 23, &umr_bitfield_default }, + { "CLIENT22", 24, 27, &umr_bitfield_default }, + { "CLIENT23", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RD_ADDR_DAGB_MAX_BURST3[] = { + { "CLIENT24", 0, 3, &umr_bitfield_default }, + { "CLIENT25", 4, 7, &umr_bitfield_default }, + { "CLIENT26", 8, 11, &umr_bitfield_default }, + { "CLIENT27", 12, 15, &umr_bitfield_default }, + { "CLIENT28", 16, 19, &umr_bitfield_default }, + { "CLIENT29", 20, 23, &umr_bitfield_default }, + { "CLIENT30", 24, 27, &umr_bitfield_default }, + { "CLIENT31", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER3[] = { + { "CLIENT24", 0, 3, &umr_bitfield_default }, + { "CLIENT25", 4, 7, &umr_bitfield_default }, + { "CLIENT26", 8, 11, &umr_bitfield_default }, + { "CLIENT27", 12, 15, &umr_bitfield_default }, + { "CLIENT28", 16, 19, &umr_bitfield_default }, + { "CLIENT29", 20, 23, &umr_bitfield_default }, + { "CLIENT30", 24, 27, &umr_bitfield_default }, + { "CLIENT31", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RD_VC0_CNTL[] = { + { "STOR_CREDIT", 0, 4, &umr_bitfield_default }, + { "EA_CREDIT", 5, 10, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 11, 11, &umr_bitfield_default }, + { "MAX_BW", 12, 19, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 20, 20, &umr_bitfield_default }, + { "MIN_BW", 21, 23, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 24, 24, &umr_bitfield_default }, + { "MAX_OSD", 25, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RD_VC1_CNTL[] = { + { "STOR_CREDIT", 0, 4, &umr_bitfield_default }, + { "EA_CREDIT", 5, 10, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 11, 11, &umr_bitfield_default }, + { "MAX_BW", 12, 19, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 20, 20, &umr_bitfield_default }, + { "MIN_BW", 21, 23, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 24, 24, &umr_bitfield_default }, + { "MAX_OSD", 25, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RD_VC2_CNTL[] = { + { "STOR_CREDIT", 0, 4, &umr_bitfield_default }, + { "EA_CREDIT", 5, 10, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 11, 11, &umr_bitfield_default }, + { "MAX_BW", 12, 19, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 20, 20, &umr_bitfield_default }, + { "MIN_BW", 21, 23, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 24, 24, &umr_bitfield_default }, + { "MAX_OSD", 25, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RD_VC3_CNTL[] = { + { "STOR_CREDIT", 0, 4, &umr_bitfield_default }, + { "EA_CREDIT", 5, 10, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 11, 11, &umr_bitfield_default }, + { "MAX_BW", 12, 19, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 20, 20, &umr_bitfield_default }, + { "MIN_BW", 21, 23, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 24, 24, &umr_bitfield_default }, + { "MAX_OSD", 25, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RD_VC4_CNTL[] = { + { "STOR_CREDIT", 0, 4, &umr_bitfield_default }, + { "EA_CREDIT", 5, 10, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 11, 11, &umr_bitfield_default }, + { "MAX_BW", 12, 19, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 20, 20, &umr_bitfield_default }, + { "MIN_BW", 21, 23, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 24, 24, &umr_bitfield_default }, + { "MAX_OSD", 25, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RD_VC5_CNTL[] = { + { "STOR_CREDIT", 0, 4, &umr_bitfield_default }, + { "EA_CREDIT", 5, 10, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 11, 11, &umr_bitfield_default }, + { "MAX_BW", 12, 19, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 20, 20, &umr_bitfield_default }, + { "MIN_BW", 21, 23, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 24, 24, &umr_bitfield_default }, + { "MAX_OSD", 25, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RD_VC6_CNTL[] = { + { "STOR_CREDIT", 0, 4, &umr_bitfield_default }, + { "EA_CREDIT", 5, 10, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 11, 11, &umr_bitfield_default }, + { "MAX_BW", 12, 19, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 20, 20, &umr_bitfield_default }, + { "MIN_BW", 21, 23, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 24, 24, &umr_bitfield_default }, + { "MAX_OSD", 25, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RD_VC7_CNTL[] = { + { "STOR_CREDIT", 0, 4, &umr_bitfield_default }, + { "EA_CREDIT", 5, 10, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 11, 11, &umr_bitfield_default }, + { "MAX_BW", 12, 19, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 20, 20, &umr_bitfield_default }, + { "MIN_BW", 21, 23, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 24, 24, &umr_bitfield_default }, + { "MAX_OSD", 25, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RD_CNTL_MISC[] = { + { "STOR_POOL_CREDIT", 0, 5, &umr_bitfield_default }, + { "EA_POOL_CREDIT", 6, 12, &umr_bitfield_default }, + { "IO_EA_CREDIT", 13, 18, &umr_bitfield_default }, + { "STOR_CC_LEGACY_MODE", 19, 19, &umr_bitfield_default }, + { "EA_CC_LEGACY_MODE", 20, 20, &umr_bitfield_default }, + { "UTCL2_CID", 21, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RD_TLB_CREDIT[] = { + { "TLB0", 0, 4, &umr_bitfield_default }, + { "TLB1", 5, 9, &umr_bitfield_default }, + { "TLB2", 10, 14, &umr_bitfield_default }, + { "TLB3", 15, 19, &umr_bitfield_default }, + { "TLB4", 20, 24, &umr_bitfield_default }, + { "TLB5", 25, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RDCLI_ASK_PENDING[] = { + { "BUSY", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RDCLI_GO_PENDING[] = { + { "BUSY", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RDCLI_GBLSEND_PENDING[] = { + { "BUSY", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RDCLI_TLB_PENDING[] = { + { "BUSY", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RDCLI_OARB_PENDING[] = { + { "BUSY", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RDCLI_OSD_PENDING[] = { + { "BUSY", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WRCLI0[] = { + { "VIRT_CHAN", 0, 2, &umr_bitfield_default }, + { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default }, + { "URG_HIGH", 4, 7, &umr_bitfield_default }, + { "URG_LOW", 8, 11, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default }, + { "MAX_BW", 13, 20, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default }, + { "MIN_BW", 22, 24, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default }, + { "MAX_OSD", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WRCLI1[] = { + { "VIRT_CHAN", 0, 2, &umr_bitfield_default }, + { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default }, + { "URG_HIGH", 4, 7, &umr_bitfield_default }, + { "URG_LOW", 8, 11, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default }, + { "MAX_BW", 13, 20, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default }, + { "MIN_BW", 22, 24, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default }, + { "MAX_OSD", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WRCLI2[] = { + { "VIRT_CHAN", 0, 2, &umr_bitfield_default }, + { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default }, + { "URG_HIGH", 4, 7, &umr_bitfield_default }, + { "URG_LOW", 8, 11, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default }, + { "MAX_BW", 13, 20, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default }, + { "MIN_BW", 22, 24, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default }, + { "MAX_OSD", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WRCLI3[] = { + { "VIRT_CHAN", 0, 2, &umr_bitfield_default }, + { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default }, + { "URG_HIGH", 4, 7, &umr_bitfield_default }, + { "URG_LOW", 8, 11, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default }, + { "MAX_BW", 13, 20, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default }, + { "MIN_BW", 22, 24, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default }, + { "MAX_OSD", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WRCLI4[] = { + { "VIRT_CHAN", 0, 2, &umr_bitfield_default }, + { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default }, + { "URG_HIGH", 4, 7, &umr_bitfield_default }, + { "URG_LOW", 8, 11, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default }, + { "MAX_BW", 13, 20, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default }, + { "MIN_BW", 22, 24, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default }, + { "MAX_OSD", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WRCLI5[] = { + { "VIRT_CHAN", 0, 2, &umr_bitfield_default }, + { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default }, + { "URG_HIGH", 4, 7, &umr_bitfield_default }, + { "URG_LOW", 8, 11, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default }, + { "MAX_BW", 13, 20, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default }, + { "MIN_BW", 22, 24, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default }, + { "MAX_OSD", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WRCLI6[] = { + { "VIRT_CHAN", 0, 2, &umr_bitfield_default }, + { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default }, + { "URG_HIGH", 4, 7, &umr_bitfield_default }, + { "URG_LOW", 8, 11, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default }, + { "MAX_BW", 13, 20, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default }, + { "MIN_BW", 22, 24, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default }, + { "MAX_OSD", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WRCLI7[] = { + { "VIRT_CHAN", 0, 2, &umr_bitfield_default }, + { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default }, + { "URG_HIGH", 4, 7, &umr_bitfield_default }, + { "URG_LOW", 8, 11, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default }, + { "MAX_BW", 13, 20, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default }, + { "MIN_BW", 22, 24, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default }, + { "MAX_OSD", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WRCLI8[] = { + { "VIRT_CHAN", 0, 2, &umr_bitfield_default }, + { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default }, + { "URG_HIGH", 4, 7, &umr_bitfield_default }, + { "URG_LOW", 8, 11, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default }, + { "MAX_BW", 13, 20, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default }, + { "MIN_BW", 22, 24, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default }, + { "MAX_OSD", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WRCLI9[] = { + { "VIRT_CHAN", 0, 2, &umr_bitfield_default }, + { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default }, + { "URG_HIGH", 4, 7, &umr_bitfield_default }, + { "URG_LOW", 8, 11, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default }, + { "MAX_BW", 13, 20, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default }, + { "MIN_BW", 22, 24, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default }, + { "MAX_OSD", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WRCLI10[] = { + { "VIRT_CHAN", 0, 2, &umr_bitfield_default }, + { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default }, + { "URG_HIGH", 4, 7, &umr_bitfield_default }, + { "URG_LOW", 8, 11, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default }, + { "MAX_BW", 13, 20, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default }, + { "MIN_BW", 22, 24, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default }, + { "MAX_OSD", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WRCLI11[] = { + { "VIRT_CHAN", 0, 2, &umr_bitfield_default }, + { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default }, + { "URG_HIGH", 4, 7, &umr_bitfield_default }, + { "URG_LOW", 8, 11, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default }, + { "MAX_BW", 13, 20, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default }, + { "MIN_BW", 22, 24, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default }, + { "MAX_OSD", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WRCLI12[] = { + { "VIRT_CHAN", 0, 2, &umr_bitfield_default }, + { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default }, + { "URG_HIGH", 4, 7, &umr_bitfield_default }, + { "URG_LOW", 8, 11, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default }, + { "MAX_BW", 13, 20, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default }, + { "MIN_BW", 22, 24, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default }, + { "MAX_OSD", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WRCLI13[] = { + { "VIRT_CHAN", 0, 2, &umr_bitfield_default }, + { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default }, + { "URG_HIGH", 4, 7, &umr_bitfield_default }, + { "URG_LOW", 8, 11, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default }, + { "MAX_BW", 13, 20, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default }, + { "MIN_BW", 22, 24, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default }, + { "MAX_OSD", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WRCLI14[] = { + { "VIRT_CHAN", 0, 2, &umr_bitfield_default }, + { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default }, + { "URG_HIGH", 4, 7, &umr_bitfield_default }, + { "URG_LOW", 8, 11, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default }, + { "MAX_BW", 13, 20, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default }, + { "MIN_BW", 22, 24, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default }, + { "MAX_OSD", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WRCLI15[] = { + { "VIRT_CHAN", 0, 2, &umr_bitfield_default }, + { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default }, + { "URG_HIGH", 4, 7, &umr_bitfield_default }, + { "URG_LOW", 8, 11, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default }, + { "MAX_BW", 13, 20, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default }, + { "MIN_BW", 22, 24, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default }, + { "MAX_OSD", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WRCLI16[] = { + { "VIRT_CHAN", 0, 2, &umr_bitfield_default }, + { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default }, + { "URG_HIGH", 4, 7, &umr_bitfield_default }, + { "URG_LOW", 8, 11, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default }, + { "MAX_BW", 13, 20, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default }, + { "MIN_BW", 22, 24, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default }, + { "MAX_OSD", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WRCLI17[] = { + { "VIRT_CHAN", 0, 2, &umr_bitfield_default }, + { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default }, + { "URG_HIGH", 4, 7, &umr_bitfield_default }, + { "URG_LOW", 8, 11, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default }, + { "MAX_BW", 13, 20, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default }, + { "MIN_BW", 22, 24, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default }, + { "MAX_OSD", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WRCLI18[] = { + { "VIRT_CHAN", 0, 2, &umr_bitfield_default }, + { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default }, + { "URG_HIGH", 4, 7, &umr_bitfield_default }, + { "URG_LOW", 8, 11, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default }, + { "MAX_BW", 13, 20, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default }, + { "MIN_BW", 22, 24, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default }, + { "MAX_OSD", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WRCLI19[] = { + { "VIRT_CHAN", 0, 2, &umr_bitfield_default }, + { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default }, + { "URG_HIGH", 4, 7, &umr_bitfield_default }, + { "URG_LOW", 8, 11, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default }, + { "MAX_BW", 13, 20, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default }, + { "MIN_BW", 22, 24, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default }, + { "MAX_OSD", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WRCLI20[] = { + { "VIRT_CHAN", 0, 2, &umr_bitfield_default }, + { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default }, + { "URG_HIGH", 4, 7, &umr_bitfield_default }, + { "URG_LOW", 8, 11, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default }, + { "MAX_BW", 13, 20, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default }, + { "MIN_BW", 22, 24, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default }, + { "MAX_OSD", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WRCLI21[] = { + { "VIRT_CHAN", 0, 2, &umr_bitfield_default }, + { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default }, + { "URG_HIGH", 4, 7, &umr_bitfield_default }, + { "URG_LOW", 8, 11, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default }, + { "MAX_BW", 13, 20, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default }, + { "MIN_BW", 22, 24, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default }, + { "MAX_OSD", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WRCLI22[] = { + { "VIRT_CHAN", 0, 2, &umr_bitfield_default }, + { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default }, + { "URG_HIGH", 4, 7, &umr_bitfield_default }, + { "URG_LOW", 8, 11, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default }, + { "MAX_BW", 13, 20, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default }, + { "MIN_BW", 22, 24, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default }, + { "MAX_OSD", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WRCLI23[] = { + { "VIRT_CHAN", 0, 2, &umr_bitfield_default }, + { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default }, + { "URG_HIGH", 4, 7, &umr_bitfield_default }, + { "URG_LOW", 8, 11, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default }, + { "MAX_BW", 13, 20, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default }, + { "MIN_BW", 22, 24, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default }, + { "MAX_OSD", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WRCLI24[] = { + { "VIRT_CHAN", 0, 2, &umr_bitfield_default }, + { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default }, + { "URG_HIGH", 4, 7, &umr_bitfield_default }, + { "URG_LOW", 8, 11, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default }, + { "MAX_BW", 13, 20, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default }, + { "MIN_BW", 22, 24, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default }, + { "MAX_OSD", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WRCLI25[] = { + { "VIRT_CHAN", 0, 2, &umr_bitfield_default }, + { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default }, + { "URG_HIGH", 4, 7, &umr_bitfield_default }, + { "URG_LOW", 8, 11, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default }, + { "MAX_BW", 13, 20, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default }, + { "MIN_BW", 22, 24, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default }, + { "MAX_OSD", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WRCLI26[] = { + { "VIRT_CHAN", 0, 2, &umr_bitfield_default }, + { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default }, + { "URG_HIGH", 4, 7, &umr_bitfield_default }, + { "URG_LOW", 8, 11, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default }, + { "MAX_BW", 13, 20, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default }, + { "MIN_BW", 22, 24, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default }, + { "MAX_OSD", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WRCLI27[] = { + { "VIRT_CHAN", 0, 2, &umr_bitfield_default }, + { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default }, + { "URG_HIGH", 4, 7, &umr_bitfield_default }, + { "URG_LOW", 8, 11, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default }, + { "MAX_BW", 13, 20, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default }, + { "MIN_BW", 22, 24, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default }, + { "MAX_OSD", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WRCLI28[] = { + { "VIRT_CHAN", 0, 2, &umr_bitfield_default }, + { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default }, + { "URG_HIGH", 4, 7, &umr_bitfield_default }, + { "URG_LOW", 8, 11, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default }, + { "MAX_BW", 13, 20, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default }, + { "MIN_BW", 22, 24, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default }, + { "MAX_OSD", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WRCLI29[] = { + { "VIRT_CHAN", 0, 2, &umr_bitfield_default }, + { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default }, + { "URG_HIGH", 4, 7, &umr_bitfield_default }, + { "URG_LOW", 8, 11, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default }, + { "MAX_BW", 13, 20, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default }, + { "MIN_BW", 22, 24, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default }, + { "MAX_OSD", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WRCLI30[] = { + { "VIRT_CHAN", 0, 2, &umr_bitfield_default }, + { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default }, + { "URG_HIGH", 4, 7, &umr_bitfield_default }, + { "URG_LOW", 8, 11, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default }, + { "MAX_BW", 13, 20, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default }, + { "MIN_BW", 22, 24, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default }, + { "MAX_OSD", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WRCLI31[] = { + { "VIRT_CHAN", 0, 2, &umr_bitfield_default }, + { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default }, + { "URG_HIGH", 4, 7, &umr_bitfield_default }, + { "URG_LOW", 8, 11, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default }, + { "MAX_BW", 13, 20, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default }, + { "MIN_BW", 22, 24, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default }, + { "MAX_OSD", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WR_CNTL[] = { + { "SCLK_FREQ", 0, 3, &umr_bitfield_default }, + { "CLI_MAX_BW_WINDOW", 4, 9, &umr_bitfield_default }, + { "VC_MAX_BW_WINDOW", 10, 15, &umr_bitfield_default }, + { "IO_LEVEL_OVERRIDE_ENABLE", 16, 16, &umr_bitfield_default }, + { "IO_LEVEL", 17, 19, &umr_bitfield_default }, + { "IO_LEVEL_COMPLY_VC", 20, 22, &umr_bitfield_default }, + { "SHARE_VC_NUM", 23, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WR_GMI_CNTL[] = { + { "EA_CREDIT", 0, 5, &umr_bitfield_default }, + { "LEVEL", 6, 8, &umr_bitfield_default }, + { "MAX_BURST", 9, 12, &umr_bitfield_default }, + { "LAZY_TIMER", 13, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WR_ADDR_DAGB[] = { + { "DAGB_ENABLE", 0, 2, &umr_bitfield_default }, + { "ENABLE_JUMP_AHEAD", 3, 5, &umr_bitfield_default }, + { "DISABLE_SELF_INIT", 6, 6, &umr_bitfield_default }, + { "WHOAMI", 7, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST[] = { + { "VC0", 0, 3, &umr_bitfield_default }, + { "VC1", 4, 7, &umr_bitfield_default }, + { "VC2", 8, 11, &umr_bitfield_default }, + { "VC3", 12, 15, &umr_bitfield_default }, + { "VC4", 16, 19, &umr_bitfield_default }, + { "VC5", 20, 23, &umr_bitfield_default }, + { "VC6", 24, 27, &umr_bitfield_default }, + { "VC7", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER[] = { + { "VC0", 0, 3, &umr_bitfield_default }, + { "VC1", 4, 7, &umr_bitfield_default }, + { "VC2", 8, 11, &umr_bitfield_default }, + { "VC3", 12, 15, &umr_bitfield_default }, + { "VC4", 16, 19, &umr_bitfield_default }, + { "VC5", 20, 23, &umr_bitfield_default }, + { "VC6", 24, 27, &umr_bitfield_default }, + { "VC7", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WR_CGTT_CLK_CTRL[] = { + { "ON_DELAY", 0, 3, &umr_bitfield_default }, + { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE", 22, 22, &umr_bitfield_default }, + { "LS_OVERRIDE", 27, 27, &umr_bitfield_default }, + { "LS_OVERRIDE_WRITE", 28, 28, &umr_bitfield_default }, + { "LS_OVERRIDE_READ", 29, 29, &umr_bitfield_default }, + { "LS_OVERRIDE_RETURN", 30, 30, &umr_bitfield_default }, + { "LS_OVERRIDE_REGISTER", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL[] = { + { "ON_DELAY", 0, 3, &umr_bitfield_default }, + { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE", 22, 22, &umr_bitfield_default }, + { "LS_OVERRIDE", 27, 27, &umr_bitfield_default }, + { "LS_OVERRIDE_WRITE", 28, 28, &umr_bitfield_default }, + { "LS_OVERRIDE_READ", 29, 29, &umr_bitfield_default }, + { "LS_OVERRIDE_RETURN", 30, 30, &umr_bitfield_default }, + { "LS_OVERRIDE_REGISTER", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL[] = { + { "ON_DELAY", 0, 3, &umr_bitfield_default }, + { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE", 22, 22, &umr_bitfield_default }, + { "LS_OVERRIDE", 27, 27, &umr_bitfield_default }, + { "LS_OVERRIDE_WRITE", 28, 28, &umr_bitfield_default }, + { "LS_OVERRIDE_READ", 29, 29, &umr_bitfield_default }, + { "LS_OVERRIDE_RETURN", 30, 30, &umr_bitfield_default }, + { "LS_OVERRIDE_REGISTER", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WR_ADDR_DAGB_MAX_BURST0[] = { + { "CLIENT0", 0, 3, &umr_bitfield_default }, + { "CLIENT1", 4, 7, &umr_bitfield_default }, + { "CLIENT2", 8, 11, &umr_bitfield_default }, + { "CLIENT3", 12, 15, &umr_bitfield_default }, + { "CLIENT4", 16, 19, &umr_bitfield_default }, + { "CLIENT5", 20, 23, &umr_bitfield_default }, + { "CLIENT6", 24, 27, &umr_bitfield_default }, + { "CLIENT7", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0[] = { + { "CLIENT0", 0, 3, &umr_bitfield_default }, + { "CLIENT1", 4, 7, &umr_bitfield_default }, + { "CLIENT2", 8, 11, &umr_bitfield_default }, + { "CLIENT3", 12, 15, &umr_bitfield_default }, + { "CLIENT4", 16, 19, &umr_bitfield_default }, + { "CLIENT5", 20, 23, &umr_bitfield_default }, + { "CLIENT6", 24, 27, &umr_bitfield_default }, + { "CLIENT7", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WR_ADDR_DAGB_MAX_BURST1[] = { + { "CLIENT8", 0, 3, &umr_bitfield_default }, + { "CLIENT9", 4, 7, &umr_bitfield_default }, + { "CLIENT10", 8, 11, &umr_bitfield_default }, + { "CLIENT11", 12, 15, &umr_bitfield_default }, + { "CLIENT12", 16, 19, &umr_bitfield_default }, + { "CLIENT13", 20, 23, &umr_bitfield_default }, + { "CLIENT14", 24, 27, &umr_bitfield_default }, + { "CLIENT15", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1[] = { + { "CLIENT8", 0, 3, &umr_bitfield_default }, + { "CLIENT9", 4, 7, &umr_bitfield_default }, + { "CLIENT10", 8, 11, &umr_bitfield_default }, + { "CLIENT11", 12, 15, &umr_bitfield_default }, + { "CLIENT12", 16, 19, &umr_bitfield_default }, + { "CLIENT13", 20, 23, &umr_bitfield_default }, + { "CLIENT14", 24, 27, &umr_bitfield_default }, + { "CLIENT15", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WR_ADDR_DAGB_MAX_BURST2[] = { + { "CLIENT16", 0, 3, &umr_bitfield_default }, + { "CLIENT17", 4, 7, &umr_bitfield_default }, + { "CLIENT18", 8, 11, &umr_bitfield_default }, + { "CLIENT19", 12, 15, &umr_bitfield_default }, + { "CLIENT20", 16, 19, &umr_bitfield_default }, + { "CLIENT21", 20, 23, &umr_bitfield_default }, + { "CLIENT22", 24, 27, &umr_bitfield_default }, + { "CLIENT23", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER2[] = { + { "CLIENT16", 0, 3, &umr_bitfield_default }, + { "CLIENT17", 4, 7, &umr_bitfield_default }, + { "CLIENT18", 8, 11, &umr_bitfield_default }, + { "CLIENT19", 12, 15, &umr_bitfield_default }, + { "CLIENT20", 16, 19, &umr_bitfield_default }, + { "CLIENT21", 20, 23, &umr_bitfield_default }, + { "CLIENT22", 24, 27, &umr_bitfield_default }, + { "CLIENT23", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WR_ADDR_DAGB_MAX_BURST3[] = { + { "CLIENT24", 0, 3, &umr_bitfield_default }, + { "CLIENT25", 4, 7, &umr_bitfield_default }, + { "CLIENT26", 8, 11, &umr_bitfield_default }, + { "CLIENT27", 12, 15, &umr_bitfield_default }, + { "CLIENT28", 16, 19, &umr_bitfield_default }, + { "CLIENT29", 20, 23, &umr_bitfield_default }, + { "CLIENT30", 24, 27, &umr_bitfield_default }, + { "CLIENT31", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER3[] = { + { "CLIENT24", 0, 3, &umr_bitfield_default }, + { "CLIENT25", 4, 7, &umr_bitfield_default }, + { "CLIENT26", 8, 11, &umr_bitfield_default }, + { "CLIENT27", 12, 15, &umr_bitfield_default }, + { "CLIENT28", 16, 19, &umr_bitfield_default }, + { "CLIENT29", 20, 23, &umr_bitfield_default }, + { "CLIENT30", 24, 27, &umr_bitfield_default }, + { "CLIENT31", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WR_DATA_DAGB[] = { + { "DAGB_ENABLE", 0, 2, &umr_bitfield_default }, + { "ENABLE_JUMP_AHEAD", 3, 5, &umr_bitfield_default }, + { "DISABLE_SELF_INIT", 6, 6, &umr_bitfield_default }, + { "WHOAMI", 7, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WR_DATA_DAGB_MAX_BURST0[] = { + { "CLIENT0", 0, 3, &umr_bitfield_default }, + { "CLIENT1", 4, 7, &umr_bitfield_default }, + { "CLIENT2", 8, 11, &umr_bitfield_default }, + { "CLIENT3", 12, 15, &umr_bitfield_default }, + { "CLIENT4", 16, 19, &umr_bitfield_default }, + { "CLIENT5", 20, 23, &umr_bitfield_default }, + { "CLIENT6", 24, 27, &umr_bitfield_default }, + { "CLIENT7", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0[] = { + { "CLIENT0", 0, 3, &umr_bitfield_default }, + { "CLIENT1", 4, 7, &umr_bitfield_default }, + { "CLIENT2", 8, 11, &umr_bitfield_default }, + { "CLIENT3", 12, 15, &umr_bitfield_default }, + { "CLIENT4", 16, 19, &umr_bitfield_default }, + { "CLIENT5", 20, 23, &umr_bitfield_default }, + { "CLIENT6", 24, 27, &umr_bitfield_default }, + { "CLIENT7", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WR_DATA_DAGB_MAX_BURST1[] = { + { "CLIENT8", 0, 3, &umr_bitfield_default }, + { "CLIENT9", 4, 7, &umr_bitfield_default }, + { "CLIENT10", 8, 11, &umr_bitfield_default }, + { "CLIENT11", 12, 15, &umr_bitfield_default }, + { "CLIENT12", 16, 19, &umr_bitfield_default }, + { "CLIENT13", 20, 23, &umr_bitfield_default }, + { "CLIENT14", 24, 27, &umr_bitfield_default }, + { "CLIENT15", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1[] = { + { "CLIENT8", 0, 3, &umr_bitfield_default }, + { "CLIENT9", 4, 7, &umr_bitfield_default }, + { "CLIENT10", 8, 11, &umr_bitfield_default }, + { "CLIENT11", 12, 15, &umr_bitfield_default }, + { "CLIENT12", 16, 19, &umr_bitfield_default }, + { "CLIENT13", 20, 23, &umr_bitfield_default }, + { "CLIENT14", 24, 27, &umr_bitfield_default }, + { "CLIENT15", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WR_DATA_DAGB_MAX_BURST2[] = { + { "CLIENT16", 0, 3, &umr_bitfield_default }, + { "CLIENT17", 4, 7, &umr_bitfield_default }, + { "CLIENT18", 8, 11, &umr_bitfield_default }, + { "CLIENT19", 12, 15, &umr_bitfield_default }, + { "CLIENT20", 16, 19, &umr_bitfield_default }, + { "CLIENT21", 20, 23, &umr_bitfield_default }, + { "CLIENT22", 24, 27, &umr_bitfield_default }, + { "CLIENT23", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WR_DATA_DAGB_LAZY_TIMER2[] = { + { "CLIENT16", 0, 3, &umr_bitfield_default }, + { "CLIENT17", 4, 7, &umr_bitfield_default }, + { "CLIENT18", 8, 11, &umr_bitfield_default }, + { "CLIENT19", 12, 15, &umr_bitfield_default }, + { "CLIENT20", 16, 19, &umr_bitfield_default }, + { "CLIENT21", 20, 23, &umr_bitfield_default }, + { "CLIENT22", 24, 27, &umr_bitfield_default }, + { "CLIENT23", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WR_DATA_DAGB_MAX_BURST3[] = { + { "CLIENT24", 0, 3, &umr_bitfield_default }, + { "CLIENT25", 4, 7, &umr_bitfield_default }, + { "CLIENT26", 8, 11, &umr_bitfield_default }, + { "CLIENT27", 12, 15, &umr_bitfield_default }, + { "CLIENT28", 16, 19, &umr_bitfield_default }, + { "CLIENT29", 20, 23, &umr_bitfield_default }, + { "CLIENT30", 24, 27, &umr_bitfield_default }, + { "CLIENT31", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WR_DATA_DAGB_LAZY_TIMER3[] = { + { "CLIENT24", 0, 3, &umr_bitfield_default }, + { "CLIENT25", 4, 7, &umr_bitfield_default }, + { "CLIENT26", 8, 11, &umr_bitfield_default }, + { "CLIENT27", 12, 15, &umr_bitfield_default }, + { "CLIENT28", 16, 19, &umr_bitfield_default }, + { "CLIENT29", 20, 23, &umr_bitfield_default }, + { "CLIENT30", 24, 27, &umr_bitfield_default }, + { "CLIENT31", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WR_VC0_CNTL[] = { + { "STOR_CREDIT", 0, 4, &umr_bitfield_default }, + { "EA_CREDIT", 5, 10, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 11, 11, &umr_bitfield_default }, + { "MAX_BW", 12, 19, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 20, 20, &umr_bitfield_default }, + { "MIN_BW", 21, 23, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 24, 24, &umr_bitfield_default }, + { "MAX_OSD", 25, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WR_VC1_CNTL[] = { + { "STOR_CREDIT", 0, 4, &umr_bitfield_default }, + { "EA_CREDIT", 5, 10, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 11, 11, &umr_bitfield_default }, + { "MAX_BW", 12, 19, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 20, 20, &umr_bitfield_default }, + { "MIN_BW", 21, 23, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 24, 24, &umr_bitfield_default }, + { "MAX_OSD", 25, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WR_VC2_CNTL[] = { + { "STOR_CREDIT", 0, 4, &umr_bitfield_default }, + { "EA_CREDIT", 5, 10, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 11, 11, &umr_bitfield_default }, + { "MAX_BW", 12, 19, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 20, 20, &umr_bitfield_default }, + { "MIN_BW", 21, 23, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 24, 24, &umr_bitfield_default }, + { "MAX_OSD", 25, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WR_VC3_CNTL[] = { + { "STOR_CREDIT", 0, 4, &umr_bitfield_default }, + { "EA_CREDIT", 5, 10, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 11, 11, &umr_bitfield_default }, + { "MAX_BW", 12, 19, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 20, 20, &umr_bitfield_default }, + { "MIN_BW", 21, 23, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 24, 24, &umr_bitfield_default }, + { "MAX_OSD", 25, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WR_VC4_CNTL[] = { + { "STOR_CREDIT", 0, 4, &umr_bitfield_default }, + { "EA_CREDIT", 5, 10, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 11, 11, &umr_bitfield_default }, + { "MAX_BW", 12, 19, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 20, 20, &umr_bitfield_default }, + { "MIN_BW", 21, 23, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 24, 24, &umr_bitfield_default }, + { "MAX_OSD", 25, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WR_VC5_CNTL[] = { + { "STOR_CREDIT", 0, 4, &umr_bitfield_default }, + { "EA_CREDIT", 5, 10, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 11, 11, &umr_bitfield_default }, + { "MAX_BW", 12, 19, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 20, 20, &umr_bitfield_default }, + { "MIN_BW", 21, 23, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 24, 24, &umr_bitfield_default }, + { "MAX_OSD", 25, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WR_VC6_CNTL[] = { + { "STOR_CREDIT", 0, 4, &umr_bitfield_default }, + { "EA_CREDIT", 5, 10, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 11, 11, &umr_bitfield_default }, + { "MAX_BW", 12, 19, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 20, 20, &umr_bitfield_default }, + { "MIN_BW", 21, 23, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 24, 24, &umr_bitfield_default }, + { "MAX_OSD", 25, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WR_VC7_CNTL[] = { + { "STOR_CREDIT", 0, 4, &umr_bitfield_default }, + { "EA_CREDIT", 5, 10, &umr_bitfield_default }, + { "MAX_BW_ENABLE", 11, 11, &umr_bitfield_default }, + { "MAX_BW", 12, 19, &umr_bitfield_default }, + { "MIN_BW_ENABLE", 20, 20, &umr_bitfield_default }, + { "MIN_BW", 21, 23, &umr_bitfield_default }, + { "OSD_LIMITER_ENABLE", 24, 24, &umr_bitfield_default }, + { "MAX_OSD", 25, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WR_CNTL_MISC[] = { + { "STOR_POOL_CREDIT", 0, 5, &umr_bitfield_default }, + { "EA_POOL_CREDIT", 6, 12, &umr_bitfield_default }, + { "IO_EA_CREDIT", 13, 18, &umr_bitfield_default }, + { "STOR_CC_LEGACY_MODE", 19, 19, &umr_bitfield_default }, + { "EA_CC_LEGACY_MODE", 20, 20, &umr_bitfield_default }, + { "UTCL2_CID", 21, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WR_TLB_CREDIT[] = { + { "TLB0", 0, 4, &umr_bitfield_default }, + { "TLB1", 5, 9, &umr_bitfield_default }, + { "TLB2", 10, 14, &umr_bitfield_default }, + { "TLB3", 15, 19, &umr_bitfield_default }, + { "TLB4", 20, 24, &umr_bitfield_default }, + { "TLB5", 25, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WR_DATA_CREDIT[] = { + { "DLOCK_VC_CREDITS", 0, 7, &umr_bitfield_default }, + { "LARGE_BURST_CREDITS", 8, 15, &umr_bitfield_default }, + { "MIDDLE_BURST_CREDITS", 16, 23, &umr_bitfield_default }, + { "SMALL_BURST_CREDITS", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WR_MISC_CREDIT[] = { + { "ATOMIC_CREDIT", 0, 5, &umr_bitfield_default }, + { "DLOCK_VC_NUM", 6, 8, &umr_bitfield_default }, + { "OSD_CREDIT", 9, 15, &umr_bitfield_default }, + { "OSD_DLOCK_CREDIT", 16, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WRCLI_ASK_PENDING[] = { + { "BUSY", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WRCLI_GO_PENDING[] = { + { "BUSY", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WRCLI_GBLSEND_PENDING[] = { + { "BUSY", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WRCLI_TLB_PENDING[] = { + { "BUSY", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WRCLI_OARB_PENDING[] = { + { "BUSY", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WRCLI_OSD_PENDING[] = { + { "BUSY", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WRCLI_DBUS_ASK_PENDING[] = { + { "BUSY", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WRCLI_DBUS_GO_PENDING[] = { + { "BUSY", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_DAGB_DLY[] = { + { "DLY", 0, 7, &umr_bitfield_default }, + { "CLI", 8, 15, &umr_bitfield_default }, + { "POS", 16, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_CNTL_MISC[] = { + { "EA_VC0_REMAP", 0, 2, &umr_bitfield_default }, + { "EA_VC1_REMAP", 3, 5, &umr_bitfield_default }, + { "EA_VC2_REMAP", 6, 8, &umr_bitfield_default }, + { "EA_VC3_REMAP", 9, 11, &umr_bitfield_default }, + { "EA_VC4_REMAP", 12, 14, &umr_bitfield_default }, + { "EA_VC5_REMAP", 15, 17, &umr_bitfield_default }, + { "EA_VC6_REMAP", 18, 20, &umr_bitfield_default }, + { "EA_VC7_REMAP", 21, 23, &umr_bitfield_default }, + { "BW_INIT_CYCLE", 24, 29, &umr_bitfield_default }, + { "BW_RW_GAP_CYCLE", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_CNTL_MISC2[] = { + { "URG_BOOST_ENABLE", 0, 0, &umr_bitfield_default }, + { "URG_HALT_ENABLE", 1, 1, &umr_bitfield_default }, + { "DISABLE_WRREQ_CG", 2, 2, &umr_bitfield_default }, + { "DISABLE_WRRET_CG", 3, 3, &umr_bitfield_default }, + { "DISABLE_RDREQ_CG", 4, 4, &umr_bitfield_default }, + { "DISABLE_RDRET_CG", 5, 5, &umr_bitfield_default }, + { "DISABLE_TLBWR_CG", 6, 6, &umr_bitfield_default }, + { "DISABLE_TLBRD_CG", 7, 7, &umr_bitfield_default }, + { "DISABLE_EAWRREQ_BUSY", 8, 8, &umr_bitfield_default }, + { "DISABLE_EARDREQ_BUSY", 9, 9, &umr_bitfield_default }, + { "SWAP_CTL", 10, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_FIFO_EMPTY[] = { + { "EMPTY", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_FIFO_FULL[] = { + { "FULL", 0, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_WR_CREDITS_FULL[] = { + { "FULL", 0, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RD_CREDITS_FULL[] = { + { "FULL", 0, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_PERFCOUNTER_LO[] = { + { "COUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_PERFCOUNTER_HI[] = { + { "COUNTER_HI", 0, 15, &umr_bitfield_default }, + { "COMPARE_VALUE", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_PERFCOUNTER0_CFG[] = { + { "PERF_SEL", 0, 7, &umr_bitfield_default }, + { "PERF_SEL_END", 8, 15, &umr_bitfield_default }, + { "PERF_MODE", 24, 27, &umr_bitfield_default }, + { "ENABLE", 28, 28, &umr_bitfield_default }, + { "CLEAR", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_PERFCOUNTER1_CFG[] = { + { "PERF_SEL", 0, 7, &umr_bitfield_default }, + { "PERF_SEL_END", 8, 15, &umr_bitfield_default }, + { "PERF_MODE", 24, 27, &umr_bitfield_default }, + { "ENABLE", 28, 28, &umr_bitfield_default }, + { "CLEAR", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_PERFCOUNTER2_CFG[] = { + { "PERF_SEL", 0, 7, &umr_bitfield_default }, + { "PERF_SEL_END", 8, 15, &umr_bitfield_default }, + { "PERF_MODE", 24, 27, &umr_bitfield_default }, + { "ENABLE", 28, 28, &umr_bitfield_default }, + { "CLEAR", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_PERFCOUNTER_RSLT_CNTL[] = { + { "PERF_COUNTER_SELECT", 0, 3, &umr_bitfield_default }, + { "START_TRIGGER", 8, 15, &umr_bitfield_default }, + { "STOP_TRIGGER", 16, 23, &umr_bitfield_default }, + { "ENABLE_ANY", 24, 24, &umr_bitfield_default }, + { "CLEAR_ALL", 25, 25, &umr_bitfield_default }, + { "STOP_ALL_ON_SATURATE", 26, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE0[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE1[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE2[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE3[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE4[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE5[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE6[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE7[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE8[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE9[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE10[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE11[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE12[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE13[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE14[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE15[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE16[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE17[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE18[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE19[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE20[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE21[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE22[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE23[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE24[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE25[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE26[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE27[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE28[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE29[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE30[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE31[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE32[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE33[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE34[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE35[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE36[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE37[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE38[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE39[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE40[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE41[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE42[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE43[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE44[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE45[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE46[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE47[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE48[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE49[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE50[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE51[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE52[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE53[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE54[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE55[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE56[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE57[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE58[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE59[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE60[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE61[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE62[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE63[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE64[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE65[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE66[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE67[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE68[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE69[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE70[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE71[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE72[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE73[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE74[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE75[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE76[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE77[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE78[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE79[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE80[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE81[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE82[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE83[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE84[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE85[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE86[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE87[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE88[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE89[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE90[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE91[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE92[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE93[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE94[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE95[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE96[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE97[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE98[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE99[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE100[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDAGB0_RESERVE101[] = { + { "RESERVE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_DRAM_RD_CLI2GRP_MAP0[] = { + { "CID0_GROUP", 0, 1, &umr_bitfield_default }, + { "CID1_GROUP", 2, 3, &umr_bitfield_default }, + { "CID2_GROUP", 4, 5, &umr_bitfield_default }, + { "CID3_GROUP", 6, 7, &umr_bitfield_default }, + { "CID4_GROUP", 8, 9, &umr_bitfield_default }, + { "CID5_GROUP", 10, 11, &umr_bitfield_default }, + { "CID6_GROUP", 12, 13, &umr_bitfield_default }, + { "CID7_GROUP", 14, 15, &umr_bitfield_default }, + { "CID8_GROUP", 16, 17, &umr_bitfield_default }, + { "CID9_GROUP", 18, 19, &umr_bitfield_default }, + { "CID10_GROUP", 20, 21, &umr_bitfield_default }, + { "CID11_GROUP", 22, 23, &umr_bitfield_default }, + { "CID12_GROUP", 24, 25, &umr_bitfield_default }, + { "CID13_GROUP", 26, 27, &umr_bitfield_default }, + { "CID14_GROUP", 28, 29, &umr_bitfield_default }, + { "CID15_GROUP", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_DRAM_RD_CLI2GRP_MAP1[] = { + { "CID16_GROUP", 0, 1, &umr_bitfield_default }, + { "CID17_GROUP", 2, 3, &umr_bitfield_default }, + { "CID18_GROUP", 4, 5, &umr_bitfield_default }, + { "CID19_GROUP", 6, 7, &umr_bitfield_default }, + { "CID20_GROUP", 8, 9, &umr_bitfield_default }, + { "CID21_GROUP", 10, 11, &umr_bitfield_default }, + { "CID22_GROUP", 12, 13, &umr_bitfield_default }, + { "CID23_GROUP", 14, 15, &umr_bitfield_default }, + { "CID24_GROUP", 16, 17, &umr_bitfield_default }, + { "CID25_GROUP", 18, 19, &umr_bitfield_default }, + { "CID26_GROUP", 20, 21, &umr_bitfield_default }, + { "CID27_GROUP", 22, 23, &umr_bitfield_default }, + { "CID28_GROUP", 24, 25, &umr_bitfield_default }, + { "CID29_GROUP", 26, 27, &umr_bitfield_default }, + { "CID30_GROUP", 28, 29, &umr_bitfield_default }, + { "CID31_GROUP", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_DRAM_WR_CLI2GRP_MAP0[] = { + { "CID0_GROUP", 0, 1, &umr_bitfield_default }, + { "CID1_GROUP", 2, 3, &umr_bitfield_default }, + { "CID2_GROUP", 4, 5, &umr_bitfield_default }, + { "CID3_GROUP", 6, 7, &umr_bitfield_default }, + { "CID4_GROUP", 8, 9, &umr_bitfield_default }, + { "CID5_GROUP", 10, 11, &umr_bitfield_default }, + { "CID6_GROUP", 12, 13, &umr_bitfield_default }, + { "CID7_GROUP", 14, 15, &umr_bitfield_default }, + { "CID8_GROUP", 16, 17, &umr_bitfield_default }, + { "CID9_GROUP", 18, 19, &umr_bitfield_default }, + { "CID10_GROUP", 20, 21, &umr_bitfield_default }, + { "CID11_GROUP", 22, 23, &umr_bitfield_default }, + { "CID12_GROUP", 24, 25, &umr_bitfield_default }, + { "CID13_GROUP", 26, 27, &umr_bitfield_default }, + { "CID14_GROUP", 28, 29, &umr_bitfield_default }, + { "CID15_GROUP", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_DRAM_WR_CLI2GRP_MAP1[] = { + { "CID16_GROUP", 0, 1, &umr_bitfield_default }, + { "CID17_GROUP", 2, 3, &umr_bitfield_default }, + { "CID18_GROUP", 4, 5, &umr_bitfield_default }, + { "CID19_GROUP", 6, 7, &umr_bitfield_default }, + { "CID20_GROUP", 8, 9, &umr_bitfield_default }, + { "CID21_GROUP", 10, 11, &umr_bitfield_default }, + { "CID22_GROUP", 12, 13, &umr_bitfield_default }, + { "CID23_GROUP", 14, 15, &umr_bitfield_default }, + { "CID24_GROUP", 16, 17, &umr_bitfield_default }, + { "CID25_GROUP", 18, 19, &umr_bitfield_default }, + { "CID26_GROUP", 20, 21, &umr_bitfield_default }, + { "CID27_GROUP", 22, 23, &umr_bitfield_default }, + { "CID28_GROUP", 24, 25, &umr_bitfield_default }, + { "CID29_GROUP", 26, 27, &umr_bitfield_default }, + { "CID30_GROUP", 28, 29, &umr_bitfield_default }, + { "CID31_GROUP", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_DRAM_RD_GRP2VC_MAP[] = { + { "GROUP0_VC", 0, 2, &umr_bitfield_default }, + { "GROUP1_VC", 3, 5, &umr_bitfield_default }, + { "GROUP2_VC", 6, 8, &umr_bitfield_default }, + { "GROUP3_VC", 9, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_DRAM_WR_GRP2VC_MAP[] = { + { "GROUP0_VC", 0, 2, &umr_bitfield_default }, + { "GROUP1_VC", 3, 5, &umr_bitfield_default }, + { "GROUP2_VC", 6, 8, &umr_bitfield_default }, + { "GROUP3_VC", 9, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_DRAM_RD_LAZY[] = { + { "GROUP0_DELAY", 0, 2, &umr_bitfield_default }, + { "GROUP1_DELAY", 3, 5, &umr_bitfield_default }, + { "GROUP2_DELAY", 6, 8, &umr_bitfield_default }, + { "GROUP3_DELAY", 9, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_DRAM_WR_LAZY[] = { + { "GROUP0_DELAY", 0, 2, &umr_bitfield_default }, + { "GROUP1_DELAY", 3, 5, &umr_bitfield_default }, + { "GROUP2_DELAY", 6, 8, &umr_bitfield_default }, + { "GROUP3_DELAY", 9, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_DRAM_RD_CAM_CNTL[] = { + { "DEPTH_GROUP0", 0, 3, &umr_bitfield_default }, + { "DEPTH_GROUP1", 4, 7, &umr_bitfield_default }, + { "DEPTH_GROUP2", 8, 11, &umr_bitfield_default }, + { "DEPTH_GROUP3", 12, 15, &umr_bitfield_default }, + { "REORDER_LIMIT_GROUP0", 16, 18, &umr_bitfield_default }, + { "REORDER_LIMIT_GROUP1", 19, 21, &umr_bitfield_default }, + { "REORDER_LIMIT_GROUP2", 22, 24, &umr_bitfield_default }, + { "REORDER_LIMIT_GROUP3", 25, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_DRAM_WR_CAM_CNTL[] = { + { "DEPTH_GROUP0", 0, 3, &umr_bitfield_default }, + { "DEPTH_GROUP1", 4, 7, &umr_bitfield_default }, + { "DEPTH_GROUP2", 8, 11, &umr_bitfield_default }, + { "DEPTH_GROUP3", 12, 15, &umr_bitfield_default }, + { "REORDER_LIMIT_GROUP0", 16, 18, &umr_bitfield_default }, + { "REORDER_LIMIT_GROUP1", 19, 21, &umr_bitfield_default }, + { "REORDER_LIMIT_GROUP2", 22, 24, &umr_bitfield_default }, + { "REORDER_LIMIT_GROUP3", 25, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_DRAM_PAGE_BURST[] = { + { "RD_LIMIT_LO", 0, 7, &umr_bitfield_default }, + { "RD_LIMIT_HI", 8, 15, &umr_bitfield_default }, + { "WR_LIMIT_LO", 16, 23, &umr_bitfield_default }, + { "WR_LIMIT_HI", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_DRAM_RD_PRI_AGE[] = { + { "GROUP0_AGING_RATE", 0, 2, &umr_bitfield_default }, + { "GROUP1_AGING_RATE", 3, 5, &umr_bitfield_default }, + { "GROUP2_AGING_RATE", 6, 8, &umr_bitfield_default }, + { "GROUP3_AGING_RATE", 9, 11, &umr_bitfield_default }, + { "GROUP0_AGE_COEFFICIENT", 12, 14, &umr_bitfield_default }, + { "GROUP1_AGE_COEFFICIENT", 15, 17, &umr_bitfield_default }, + { "GROUP2_AGE_COEFFICIENT", 18, 20, &umr_bitfield_default }, + { "GROUP3_AGE_COEFFICIENT", 21, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_DRAM_WR_PRI_AGE[] = { + { "GROUP0_AGING_RATE", 0, 2, &umr_bitfield_default }, + { "GROUP1_AGING_RATE", 3, 5, &umr_bitfield_default }, + { "GROUP2_AGING_RATE", 6, 8, &umr_bitfield_default }, + { "GROUP3_AGING_RATE", 9, 11, &umr_bitfield_default }, + { "GROUP0_AGE_COEFFICIENT", 12, 14, &umr_bitfield_default }, + { "GROUP1_AGE_COEFFICIENT", 15, 17, &umr_bitfield_default }, + { "GROUP2_AGE_COEFFICIENT", 18, 20, &umr_bitfield_default }, + { "GROUP3_AGE_COEFFICIENT", 21, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_DRAM_RD_PRI_QUEUING[] = { + { "GROUP0_QUEUING_COEFFICIENT", 0, 2, &umr_bitfield_default }, + { "GROUP1_QUEUING_COEFFICIENT", 3, 5, &umr_bitfield_default }, + { "GROUP2_QUEUING_COEFFICIENT", 6, 8, &umr_bitfield_default }, + { "GROUP3_QUEUING_COEFFICIENT", 9, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_DRAM_WR_PRI_QUEUING[] = { + { "GROUP0_QUEUING_COEFFICIENT", 0, 2, &umr_bitfield_default }, + { "GROUP1_QUEUING_COEFFICIENT", 3, 5, &umr_bitfield_default }, + { "GROUP2_QUEUING_COEFFICIENT", 6, 8, &umr_bitfield_default }, + { "GROUP3_QUEUING_COEFFICIENT", 9, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_DRAM_RD_PRI_FIXED[] = { + { "GROUP0_FIXED_COEFFICIENT", 0, 2, &umr_bitfield_default }, + { "GROUP1_FIXED_COEFFICIENT", 3, 5, &umr_bitfield_default }, + { "GROUP2_FIXED_COEFFICIENT", 6, 8, &umr_bitfield_default }, + { "GROUP3_FIXED_COEFFICIENT", 9, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_DRAM_WR_PRI_FIXED[] = { + { "GROUP0_FIXED_COEFFICIENT", 0, 2, &umr_bitfield_default }, + { "GROUP1_FIXED_COEFFICIENT", 3, 5, &umr_bitfield_default }, + { "GROUP2_FIXED_COEFFICIENT", 6, 8, &umr_bitfield_default }, + { "GROUP3_FIXED_COEFFICIENT", 9, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_DRAM_RD_PRI_URGENCY[] = { + { "GROUP0_URGENCY_COEFFICIENT", 0, 2, &umr_bitfield_default }, + { "GROUP1_URGENCY_COEFFICIENT", 3, 5, &umr_bitfield_default }, + { "GROUP2_URGENCY_COEFFICIENT", 6, 8, &umr_bitfield_default }, + { "GROUP3_URGENCY_COEFFICIENT", 9, 11, &umr_bitfield_default }, + { "GROUP0_URGENCY_MODE", 12, 12, &umr_bitfield_default }, + { "GROUP1_URGENCY_MODE", 13, 13, &umr_bitfield_default }, + { "GROUP2_URGENCY_MODE", 14, 14, &umr_bitfield_default }, + { "GROUP3_URGENCY_MODE", 15, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_DRAM_WR_PRI_URGENCY[] = { + { "GROUP0_URGENCY_COEFFICIENT", 0, 2, &umr_bitfield_default }, + { "GROUP1_URGENCY_COEFFICIENT", 3, 5, &umr_bitfield_default }, + { "GROUP2_URGENCY_COEFFICIENT", 6, 8, &umr_bitfield_default }, + { "GROUP3_URGENCY_COEFFICIENT", 9, 11, &umr_bitfield_default }, + { "GROUP0_URGENCY_MODE", 12, 12, &umr_bitfield_default }, + { "GROUP1_URGENCY_MODE", 13, 13, &umr_bitfield_default }, + { "GROUP2_URGENCY_MODE", 14, 14, &umr_bitfield_default }, + { "GROUP3_URGENCY_MODE", 15, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_DRAM_RD_PRI_QUANT_PRI1[] = { + { "GROUP0_THRESHOLD", 0, 7, &umr_bitfield_default }, + { "GROUP1_THRESHOLD", 8, 15, &umr_bitfield_default }, + { "GROUP2_THRESHOLD", 16, 23, &umr_bitfield_default }, + { "GROUP3_THRESHOLD", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_DRAM_RD_PRI_QUANT_PRI2[] = { + { "GROUP0_THRESHOLD", 0, 7, &umr_bitfield_default }, + { "GROUP1_THRESHOLD", 8, 15, &umr_bitfield_default }, + { "GROUP2_THRESHOLD", 16, 23, &umr_bitfield_default }, + { "GROUP3_THRESHOLD", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_DRAM_RD_PRI_QUANT_PRI3[] = { + { "GROUP0_THRESHOLD", 0, 7, &umr_bitfield_default }, + { "GROUP1_THRESHOLD", 8, 15, &umr_bitfield_default }, + { "GROUP2_THRESHOLD", 16, 23, &umr_bitfield_default }, + { "GROUP3_THRESHOLD", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_DRAM_WR_PRI_QUANT_PRI1[] = { + { "GROUP0_THRESHOLD", 0, 7, &umr_bitfield_default }, + { "GROUP1_THRESHOLD", 8, 15, &umr_bitfield_default }, + { "GROUP2_THRESHOLD", 16, 23, &umr_bitfield_default }, + { "GROUP3_THRESHOLD", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_DRAM_WR_PRI_QUANT_PRI2[] = { + { "GROUP0_THRESHOLD", 0, 7, &umr_bitfield_default }, + { "GROUP1_THRESHOLD", 8, 15, &umr_bitfield_default }, + { "GROUP2_THRESHOLD", 16, 23, &umr_bitfield_default }, + { "GROUP3_THRESHOLD", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_DRAM_WR_PRI_QUANT_PRI3[] = { + { "GROUP0_THRESHOLD", 0, 7, &umr_bitfield_default }, + { "GROUP1_THRESHOLD", 8, 15, &umr_bitfield_default }, + { "GROUP2_THRESHOLD", 16, 23, &umr_bitfield_default }, + { "GROUP3_THRESHOLD", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_ADDRNORM_BASE_ADDR0[] = { + { "ADDR_RNG_VAL", 0, 0, &umr_bitfield_default }, + { "LGCY_MMIO_HOLE_EN", 1, 1, &umr_bitfield_default }, + { "INTLV_NUM_CHAN", 4, 7, &umr_bitfield_default }, + { "INTLV_ADDR_SEL", 8, 10, &umr_bitfield_default }, + { "BASE_ADDR", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_ADDRNORM_LIMIT_ADDR0[] = { + { "DST_FABRIC_ID", 0, 3, &umr_bitfield_default }, + { "INTLV_NUM_SOCKETS", 8, 8, &umr_bitfield_default }, + { "INTLV_NUM_DIES", 10, 11, &umr_bitfield_default }, + { "LIMIT_ADDR", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_ADDRNORM_BASE_ADDR1[] = { + { "ADDR_RNG_VAL", 0, 0, &umr_bitfield_default }, + { "LGCY_MMIO_HOLE_EN", 1, 1, &umr_bitfield_default }, + { "INTLV_NUM_CHAN", 4, 7, &umr_bitfield_default }, + { "INTLV_ADDR_SEL", 8, 10, &umr_bitfield_default }, + { "BASE_ADDR", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_ADDRNORM_LIMIT_ADDR1[] = { + { "DST_FABRIC_ID", 0, 3, &umr_bitfield_default }, + { "INTLV_NUM_SOCKETS", 8, 8, &umr_bitfield_default }, + { "INTLV_NUM_DIES", 10, 11, &umr_bitfield_default }, + { "LIMIT_ADDR", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_ADDRNORM_OFFSET_ADDR1[] = { + { "HI_ADDR_OFFSET_EN", 0, 0, &umr_bitfield_default }, + { "HI_ADDR_OFFSET", 20, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_ADDRNORM_HOLE_CNTL[] = { + { "DRAM_HOLE_VALID", 0, 0, &umr_bitfield_default }, + { "DRAM_HOLE_OFFSET", 7, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_ADDRDEC_BANK_CFG[] = { + { "BANK_MASK_DRAM", 0, 4, &umr_bitfield_default }, + { "BANK_MASK_GMI", 5, 9, &umr_bitfield_default }, + { "BANKGROUP_SEL_DRAM", 10, 12, &umr_bitfield_default }, + { "BANKGROUP_SEL_GMI", 13, 15, &umr_bitfield_default }, + { "BANKGROUP_INTERLEAVE_DRAM", 16, 16, &umr_bitfield_default }, + { "BANKGROUP_INTERLEAVE_GMI", 17, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_ADDRDEC_MISC_CFG[] = { + { "VCM_EN0", 0, 0, &umr_bitfield_default }, + { "VCM_EN1", 1, 1, &umr_bitfield_default }, + { "VCM_EN2", 2, 2, &umr_bitfield_default }, + { "VCM_EN3", 3, 3, &umr_bitfield_default }, + { "VCM_EN4", 4, 4, &umr_bitfield_default }, + { "PCH_MASK_DRAM", 8, 8, &umr_bitfield_default }, + { "PCH_MASK_GMI", 9, 9, &umr_bitfield_default }, + { "CH_MASK_DRAM", 12, 15, &umr_bitfield_default }, + { "CH_MASK_GMI", 16, 19, &umr_bitfield_default }, + { "CS_MASK_DRAM", 20, 21, &umr_bitfield_default }, + { "CS_MASK_GMI", 22, 23, &umr_bitfield_default }, + { "RM_MASK_DRAM", 24, 26, &umr_bitfield_default }, + { "RM_MASK_GMI", 27, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0[] = { + { "XOR_ENABLE", 0, 0, &umr_bitfield_default }, + { "COL_XOR", 1, 13, &umr_bitfield_default }, + { "ROW_XOR", 14, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1[] = { + { "XOR_ENABLE", 0, 0, &umr_bitfield_default }, + { "COL_XOR", 1, 13, &umr_bitfield_default }, + { "ROW_XOR", 14, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2[] = { + { "XOR_ENABLE", 0, 0, &umr_bitfield_default }, + { "COL_XOR", 1, 13, &umr_bitfield_default }, + { "ROW_XOR", 14, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3[] = { + { "XOR_ENABLE", 0, 0, &umr_bitfield_default }, + { "COL_XOR", 1, 13, &umr_bitfield_default }, + { "ROW_XOR", 14, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4[] = { + { "XOR_ENABLE", 0, 0, &umr_bitfield_default }, + { "COL_XOR", 1, 13, &umr_bitfield_default }, + { "ROW_XOR", 14, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC[] = { + { "XOR_ENABLE", 0, 0, &umr_bitfield_default }, + { "COL_XOR", 1, 13, &umr_bitfield_default }, + { "ROW_XOR", 14, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2[] = { + { "BANK_XOR", 0, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0[] = { + { "XOR_ENABLE", 0, 0, &umr_bitfield_default }, + { "NA_XOR", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1[] = { + { "XOR_ENABLE", 0, 0, &umr_bitfield_default }, + { "NA_XOR", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE[] = { + { "FORCE_B3_EN", 0, 0, &umr_bitfield_default }, + { "FORCE_B3_VAL", 1, 1, &umr_bitfield_default }, + { "FORCE_B4_EN", 2, 2, &umr_bitfield_default }, + { "FORCE_B4_VAL", 3, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_ADDRDEC0_BASE_ADDR_CS0[] = { + { "CS_ENABLE", 0, 0, &umr_bitfield_default }, + { "BASE_ADDR", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_ADDRDEC0_BASE_ADDR_CS1[] = { + { "CS_ENABLE", 0, 0, &umr_bitfield_default }, + { "BASE_ADDR", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_ADDRDEC0_BASE_ADDR_CS2[] = { + { "CS_ENABLE", 0, 0, &umr_bitfield_default }, + { "BASE_ADDR", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_ADDRDEC0_BASE_ADDR_CS3[] = { + { "CS_ENABLE", 0, 0, &umr_bitfield_default }, + { "BASE_ADDR", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0[] = { + { "CS_ENABLE", 0, 0, &umr_bitfield_default }, + { "BASE_ADDR", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1[] = { + { "CS_ENABLE", 0, 0, &umr_bitfield_default }, + { "BASE_ADDR", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2[] = { + { "CS_ENABLE", 0, 0, &umr_bitfield_default }, + { "BASE_ADDR", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3[] = { + { "CS_ENABLE", 0, 0, &umr_bitfield_default }, + { "BASE_ADDR", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_ADDRDEC0_ADDR_MASK_CS01[] = { + { "ADDR_MASK", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_ADDRDEC0_ADDR_MASK_CS23[] = { + { "ADDR_MASK", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01[] = { + { "ADDR_MASK", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23[] = { + { "ADDR_MASK", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_ADDRDEC0_ADDR_CFG_CS01[] = { + { "NUM_BANK_GROUPS", 2, 3, &umr_bitfield_default }, + { "NUM_RM", 4, 5, &umr_bitfield_default }, + { "NUM_ROW_LO", 8, 11, &umr_bitfield_default }, + { "NUM_ROW_HI", 12, 15, &umr_bitfield_default }, + { "NUM_COL", 16, 19, &umr_bitfield_default }, + { "NUM_BANKS", 20, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_ADDRDEC0_ADDR_CFG_CS23[] = { + { "NUM_BANK_GROUPS", 2, 3, &umr_bitfield_default }, + { "NUM_RM", 4, 5, &umr_bitfield_default }, + { "NUM_ROW_LO", 8, 11, &umr_bitfield_default }, + { "NUM_ROW_HI", 12, 15, &umr_bitfield_default }, + { "NUM_COL", 16, 19, &umr_bitfield_default }, + { "NUM_BANKS", 20, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_ADDRDEC0_ADDR_SEL_CS01[] = { + { "BANK0", 0, 3, &umr_bitfield_default }, + { "BANK1", 4, 7, &umr_bitfield_default }, + { "BANK2", 8, 11, &umr_bitfield_default }, + { "BANK3", 12, 15, &umr_bitfield_default }, + { "BANK4", 16, 19, &umr_bitfield_default }, + { "ROW_LO", 24, 27, &umr_bitfield_default }, + { "ROW_HI", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_ADDRDEC0_ADDR_SEL_CS23[] = { + { "BANK0", 0, 3, &umr_bitfield_default }, + { "BANK1", 4, 7, &umr_bitfield_default }, + { "BANK2", 8, 11, &umr_bitfield_default }, + { "BANK3", 12, 15, &umr_bitfield_default }, + { "BANK4", 16, 19, &umr_bitfield_default }, + { "ROW_LO", 24, 27, &umr_bitfield_default }, + { "ROW_HI", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01[] = { + { "COL0", 0, 3, &umr_bitfield_default }, + { "COL1", 4, 7, &umr_bitfield_default }, + { "COL2", 8, 11, &umr_bitfield_default }, + { "COL3", 12, 15, &umr_bitfield_default }, + { "COL4", 16, 19, &umr_bitfield_default }, + { "COL5", 20, 23, &umr_bitfield_default }, + { "COL6", 24, 27, &umr_bitfield_default }, + { "COL7", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23[] = { + { "COL0", 0, 3, &umr_bitfield_default }, + { "COL1", 4, 7, &umr_bitfield_default }, + { "COL2", 8, 11, &umr_bitfield_default }, + { "COL3", 12, 15, &umr_bitfield_default }, + { "COL4", 16, 19, &umr_bitfield_default }, + { "COL5", 20, 23, &umr_bitfield_default }, + { "COL6", 24, 27, &umr_bitfield_default }, + { "COL7", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01[] = { + { "COL8", 0, 3, &umr_bitfield_default }, + { "COL9", 4, 7, &umr_bitfield_default }, + { "COL10", 8, 11, &umr_bitfield_default }, + { "COL11", 12, 15, &umr_bitfield_default }, + { "COL12", 16, 19, &umr_bitfield_default }, + { "COL13", 20, 23, &umr_bitfield_default }, + { "COL14", 24, 27, &umr_bitfield_default }, + { "COL15", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23[] = { + { "COL8", 0, 3, &umr_bitfield_default }, + { "COL9", 4, 7, &umr_bitfield_default }, + { "COL10", 8, 11, &umr_bitfield_default }, + { "COL11", 12, 15, &umr_bitfield_default }, + { "COL12", 16, 19, &umr_bitfield_default }, + { "COL13", 20, 23, &umr_bitfield_default }, + { "COL14", 24, 27, &umr_bitfield_default }, + { "COL15", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_ADDRDEC0_RM_SEL_CS01[] = { + { "RM0", 0, 3, &umr_bitfield_default }, + { "RM1", 4, 7, &umr_bitfield_default }, + { "RM2", 8, 11, &umr_bitfield_default }, + { "CHAN_BIT", 12, 15, &umr_bitfield_default }, + { "INVERT_ROW_MSBS_EVEN", 16, 17, &umr_bitfield_default }, + { "INVERT_ROW_MSBS_ODD", 18, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_ADDRDEC0_RM_SEL_CS23[] = { + { "RM0", 0, 3, &umr_bitfield_default }, + { "RM1", 4, 7, &umr_bitfield_default }, + { "RM2", 8, 11, &umr_bitfield_default }, + { "CHAN_BIT", 12, 15, &umr_bitfield_default }, + { "INVERT_ROW_MSBS_EVEN", 16, 17, &umr_bitfield_default }, + { "INVERT_ROW_MSBS_ODD", 18, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_ADDRDEC0_RM_SEL_SECCS01[] = { + { "RM0", 0, 3, &umr_bitfield_default }, + { "RM1", 4, 7, &umr_bitfield_default }, + { "RM2", 8, 11, &umr_bitfield_default }, + { "CHAN_BIT", 12, 15, &umr_bitfield_default }, + { "INVERT_ROW_MSBS_EVEN", 16, 17, &umr_bitfield_default }, + { "INVERT_ROW_MSBS_ODD", 18, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_ADDRDEC0_RM_SEL_SECCS23[] = { + { "RM0", 0, 3, &umr_bitfield_default }, + { "RM1", 4, 7, &umr_bitfield_default }, + { "RM2", 8, 11, &umr_bitfield_default }, + { "CHAN_BIT", 12, 15, &umr_bitfield_default }, + { "INVERT_ROW_MSBS_EVEN", 16, 17, &umr_bitfield_default }, + { "INVERT_ROW_MSBS_ODD", 18, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_ADDRDEC1_BASE_ADDR_CS0[] = { + { "CS_ENABLE", 0, 0, &umr_bitfield_default }, + { "BASE_ADDR", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_ADDRDEC1_BASE_ADDR_CS1[] = { + { "CS_ENABLE", 0, 0, &umr_bitfield_default }, + { "BASE_ADDR", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_ADDRDEC1_BASE_ADDR_CS2[] = { + { "CS_ENABLE", 0, 0, &umr_bitfield_default }, + { "BASE_ADDR", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_ADDRDEC1_BASE_ADDR_CS3[] = { + { "CS_ENABLE", 0, 0, &umr_bitfield_default }, + { "BASE_ADDR", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0[] = { + { "CS_ENABLE", 0, 0, &umr_bitfield_default }, + { "BASE_ADDR", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1[] = { + { "CS_ENABLE", 0, 0, &umr_bitfield_default }, + { "BASE_ADDR", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2[] = { + { "CS_ENABLE", 0, 0, &umr_bitfield_default }, + { "BASE_ADDR", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3[] = { + { "CS_ENABLE", 0, 0, &umr_bitfield_default }, + { "BASE_ADDR", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_ADDRDEC1_ADDR_MASK_CS01[] = { + { "ADDR_MASK", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_ADDRDEC1_ADDR_MASK_CS23[] = { + { "ADDR_MASK", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01[] = { + { "ADDR_MASK", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23[] = { + { "ADDR_MASK", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_ADDRDEC1_ADDR_CFG_CS01[] = { + { "NUM_BANK_GROUPS", 2, 3, &umr_bitfield_default }, + { "NUM_RM", 4, 5, &umr_bitfield_default }, + { "NUM_ROW_LO", 8, 11, &umr_bitfield_default }, + { "NUM_ROW_HI", 12, 15, &umr_bitfield_default }, + { "NUM_COL", 16, 19, &umr_bitfield_default }, + { "NUM_BANKS", 20, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_ADDRDEC1_ADDR_CFG_CS23[] = { + { "NUM_BANK_GROUPS", 2, 3, &umr_bitfield_default }, + { "NUM_RM", 4, 5, &umr_bitfield_default }, + { "NUM_ROW_LO", 8, 11, &umr_bitfield_default }, + { "NUM_ROW_HI", 12, 15, &umr_bitfield_default }, + { "NUM_COL", 16, 19, &umr_bitfield_default }, + { "NUM_BANKS", 20, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_ADDRDEC1_ADDR_SEL_CS01[] = { + { "BANK0", 0, 3, &umr_bitfield_default }, + { "BANK1", 4, 7, &umr_bitfield_default }, + { "BANK2", 8, 11, &umr_bitfield_default }, + { "BANK3", 12, 15, &umr_bitfield_default }, + { "BANK4", 16, 19, &umr_bitfield_default }, + { "ROW_LO", 24, 27, &umr_bitfield_default }, + { "ROW_HI", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_ADDRDEC1_ADDR_SEL_CS23[] = { + { "BANK0", 0, 3, &umr_bitfield_default }, + { "BANK1", 4, 7, &umr_bitfield_default }, + { "BANK2", 8, 11, &umr_bitfield_default }, + { "BANK3", 12, 15, &umr_bitfield_default }, + { "BANK4", 16, 19, &umr_bitfield_default }, + { "ROW_LO", 24, 27, &umr_bitfield_default }, + { "ROW_HI", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01[] = { + { "COL0", 0, 3, &umr_bitfield_default }, + { "COL1", 4, 7, &umr_bitfield_default }, + { "COL2", 8, 11, &umr_bitfield_default }, + { "COL3", 12, 15, &umr_bitfield_default }, + { "COL4", 16, 19, &umr_bitfield_default }, + { "COL5", 20, 23, &umr_bitfield_default }, + { "COL6", 24, 27, &umr_bitfield_default }, + { "COL7", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23[] = { + { "COL0", 0, 3, &umr_bitfield_default }, + { "COL1", 4, 7, &umr_bitfield_default }, + { "COL2", 8, 11, &umr_bitfield_default }, + { "COL3", 12, 15, &umr_bitfield_default }, + { "COL4", 16, 19, &umr_bitfield_default }, + { "COL5", 20, 23, &umr_bitfield_default }, + { "COL6", 24, 27, &umr_bitfield_default }, + { "COL7", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01[] = { + { "COL8", 0, 3, &umr_bitfield_default }, + { "COL9", 4, 7, &umr_bitfield_default }, + { "COL10", 8, 11, &umr_bitfield_default }, + { "COL11", 12, 15, &umr_bitfield_default }, + { "COL12", 16, 19, &umr_bitfield_default }, + { "COL13", 20, 23, &umr_bitfield_default }, + { "COL14", 24, 27, &umr_bitfield_default }, + { "COL15", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23[] = { + { "COL8", 0, 3, &umr_bitfield_default }, + { "COL9", 4, 7, &umr_bitfield_default }, + { "COL10", 8, 11, &umr_bitfield_default }, + { "COL11", 12, 15, &umr_bitfield_default }, + { "COL12", 16, 19, &umr_bitfield_default }, + { "COL13", 20, 23, &umr_bitfield_default }, + { "COL14", 24, 27, &umr_bitfield_default }, + { "COL15", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_ADDRDEC1_RM_SEL_CS01[] = { + { "RM0", 0, 3, &umr_bitfield_default }, + { "RM1", 4, 7, &umr_bitfield_default }, + { "RM2", 8, 11, &umr_bitfield_default }, + { "CHAN_BIT", 12, 15, &umr_bitfield_default }, + { "INVERT_ROW_MSBS_EVEN", 16, 17, &umr_bitfield_default }, + { "INVERT_ROW_MSBS_ODD", 18, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_ADDRDEC1_RM_SEL_CS23[] = { + { "RM0", 0, 3, &umr_bitfield_default }, + { "RM1", 4, 7, &umr_bitfield_default }, + { "RM2", 8, 11, &umr_bitfield_default }, + { "CHAN_BIT", 12, 15, &umr_bitfield_default }, + { "INVERT_ROW_MSBS_EVEN", 16, 17, &umr_bitfield_default }, + { "INVERT_ROW_MSBS_ODD", 18, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_ADDRDEC1_RM_SEL_SECCS01[] = { + { "RM0", 0, 3, &umr_bitfield_default }, + { "RM1", 4, 7, &umr_bitfield_default }, + { "RM2", 8, 11, &umr_bitfield_default }, + { "CHAN_BIT", 12, 15, &umr_bitfield_default }, + { "INVERT_ROW_MSBS_EVEN", 16, 17, &umr_bitfield_default }, + { "INVERT_ROW_MSBS_ODD", 18, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_ADDRDEC1_RM_SEL_SECCS23[] = { + { "RM0", 0, 3, &umr_bitfield_default }, + { "RM1", 4, 7, &umr_bitfield_default }, + { "RM2", 8, 11, &umr_bitfield_default }, + { "CHAN_BIT", 12, 15, &umr_bitfield_default }, + { "INVERT_ROW_MSBS_EVEN", 16, 17, &umr_bitfield_default }, + { "INVERT_ROW_MSBS_ODD", 18, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_IO_RD_CLI2GRP_MAP0[] = { + { "CID0_GROUP", 0, 1, &umr_bitfield_default }, + { "CID1_GROUP", 2, 3, &umr_bitfield_default }, + { "CID2_GROUP", 4, 5, &umr_bitfield_default }, + { "CID3_GROUP", 6, 7, &umr_bitfield_default }, + { "CID4_GROUP", 8, 9, &umr_bitfield_default }, + { "CID5_GROUP", 10, 11, &umr_bitfield_default }, + { "CID6_GROUP", 12, 13, &umr_bitfield_default }, + { "CID7_GROUP", 14, 15, &umr_bitfield_default }, + { "CID8_GROUP", 16, 17, &umr_bitfield_default }, + { "CID9_GROUP", 18, 19, &umr_bitfield_default }, + { "CID10_GROUP", 20, 21, &umr_bitfield_default }, + { "CID11_GROUP", 22, 23, &umr_bitfield_default }, + { "CID12_GROUP", 24, 25, &umr_bitfield_default }, + { "CID13_GROUP", 26, 27, &umr_bitfield_default }, + { "CID14_GROUP", 28, 29, &umr_bitfield_default }, + { "CID15_GROUP", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_IO_RD_CLI2GRP_MAP1[] = { + { "CID16_GROUP", 0, 1, &umr_bitfield_default }, + { "CID17_GROUP", 2, 3, &umr_bitfield_default }, + { "CID18_GROUP", 4, 5, &umr_bitfield_default }, + { "CID19_GROUP", 6, 7, &umr_bitfield_default }, + { "CID20_GROUP", 8, 9, &umr_bitfield_default }, + { "CID21_GROUP", 10, 11, &umr_bitfield_default }, + { "CID22_GROUP", 12, 13, &umr_bitfield_default }, + { "CID23_GROUP", 14, 15, &umr_bitfield_default }, + { "CID24_GROUP", 16, 17, &umr_bitfield_default }, + { "CID25_GROUP", 18, 19, &umr_bitfield_default }, + { "CID26_GROUP", 20, 21, &umr_bitfield_default }, + { "CID27_GROUP", 22, 23, &umr_bitfield_default }, + { "CID28_GROUP", 24, 25, &umr_bitfield_default }, + { "CID29_GROUP", 26, 27, &umr_bitfield_default }, + { "CID30_GROUP", 28, 29, &umr_bitfield_default }, + { "CID31_GROUP", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_IO_WR_CLI2GRP_MAP0[] = { + { "CID0_GROUP", 0, 1, &umr_bitfield_default }, + { "CID1_GROUP", 2, 3, &umr_bitfield_default }, + { "CID2_GROUP", 4, 5, &umr_bitfield_default }, + { "CID3_GROUP", 6, 7, &umr_bitfield_default }, + { "CID4_GROUP", 8, 9, &umr_bitfield_default }, + { "CID5_GROUP", 10, 11, &umr_bitfield_default }, + { "CID6_GROUP", 12, 13, &umr_bitfield_default }, + { "CID7_GROUP", 14, 15, &umr_bitfield_default }, + { "CID8_GROUP", 16, 17, &umr_bitfield_default }, + { "CID9_GROUP", 18, 19, &umr_bitfield_default }, + { "CID10_GROUP", 20, 21, &umr_bitfield_default }, + { "CID11_GROUP", 22, 23, &umr_bitfield_default }, + { "CID12_GROUP", 24, 25, &umr_bitfield_default }, + { "CID13_GROUP", 26, 27, &umr_bitfield_default }, + { "CID14_GROUP", 28, 29, &umr_bitfield_default }, + { "CID15_GROUP", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_IO_WR_CLI2GRP_MAP1[] = { + { "CID16_GROUP", 0, 1, &umr_bitfield_default }, + { "CID17_GROUP", 2, 3, &umr_bitfield_default }, + { "CID18_GROUP", 4, 5, &umr_bitfield_default }, + { "CID19_GROUP", 6, 7, &umr_bitfield_default }, + { "CID20_GROUP", 8, 9, &umr_bitfield_default }, + { "CID21_GROUP", 10, 11, &umr_bitfield_default }, + { "CID22_GROUP", 12, 13, &umr_bitfield_default }, + { "CID23_GROUP", 14, 15, &umr_bitfield_default }, + { "CID24_GROUP", 16, 17, &umr_bitfield_default }, + { "CID25_GROUP", 18, 19, &umr_bitfield_default }, + { "CID26_GROUP", 20, 21, &umr_bitfield_default }, + { "CID27_GROUP", 22, 23, &umr_bitfield_default }, + { "CID28_GROUP", 24, 25, &umr_bitfield_default }, + { "CID29_GROUP", 26, 27, &umr_bitfield_default }, + { "CID30_GROUP", 28, 29, &umr_bitfield_default }, + { "CID31_GROUP", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_IO_RD_COMBINE_FLUSH[] = { + { "GROUP0_TIMER", 0, 3, &umr_bitfield_default }, + { "GROUP1_TIMER", 4, 7, &umr_bitfield_default }, + { "GROUP2_TIMER", 8, 11, &umr_bitfield_default }, + { "GROUP3_TIMER", 12, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_IO_WR_COMBINE_FLUSH[] = { + { "GROUP0_TIMER", 0, 3, &umr_bitfield_default }, + { "GROUP1_TIMER", 4, 7, &umr_bitfield_default }, + { "GROUP2_TIMER", 8, 11, &umr_bitfield_default }, + { "GROUP3_TIMER", 12, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_IO_GROUP_BURST[] = { + { "RD_LIMIT_LO", 0, 7, &umr_bitfield_default }, + { "RD_LIMIT_HI", 8, 15, &umr_bitfield_default }, + { "WR_LIMIT_LO", 16, 23, &umr_bitfield_default }, + { "WR_LIMIT_HI", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_IO_RD_PRI_AGE[] = { + { "GROUP0_AGING_RATE", 0, 2, &umr_bitfield_default }, + { "GROUP1_AGING_RATE", 3, 5, &umr_bitfield_default }, + { "GROUP2_AGING_RATE", 6, 8, &umr_bitfield_default }, + { "GROUP3_AGING_RATE", 9, 11, &umr_bitfield_default }, + { "GROUP0_AGE_COEFFICIENT", 12, 14, &umr_bitfield_default }, + { "GROUP1_AGE_COEFFICIENT", 15, 17, &umr_bitfield_default }, + { "GROUP2_AGE_COEFFICIENT", 18, 20, &umr_bitfield_default }, + { "GROUP3_AGE_COEFFICIENT", 21, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_IO_WR_PRI_AGE[] = { + { "GROUP0_AGING_RATE", 0, 2, &umr_bitfield_default }, + { "GROUP1_AGING_RATE", 3, 5, &umr_bitfield_default }, + { "GROUP2_AGING_RATE", 6, 8, &umr_bitfield_default }, + { "GROUP3_AGING_RATE", 9, 11, &umr_bitfield_default }, + { "GROUP0_AGE_COEFFICIENT", 12, 14, &umr_bitfield_default }, + { "GROUP1_AGE_COEFFICIENT", 15, 17, &umr_bitfield_default }, + { "GROUP2_AGE_COEFFICIENT", 18, 20, &umr_bitfield_default }, + { "GROUP3_AGE_COEFFICIENT", 21, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_IO_RD_PRI_QUEUING[] = { + { "GROUP0_QUEUING_COEFFICIENT", 0, 2, &umr_bitfield_default }, + { "GROUP1_QUEUING_COEFFICIENT", 3, 5, &umr_bitfield_default }, + { "GROUP2_QUEUING_COEFFICIENT", 6, 8, &umr_bitfield_default }, + { "GROUP3_QUEUING_COEFFICIENT", 9, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_IO_WR_PRI_QUEUING[] = { + { "GROUP0_QUEUING_COEFFICIENT", 0, 2, &umr_bitfield_default }, + { "GROUP1_QUEUING_COEFFICIENT", 3, 5, &umr_bitfield_default }, + { "GROUP2_QUEUING_COEFFICIENT", 6, 8, &umr_bitfield_default }, + { "GROUP3_QUEUING_COEFFICIENT", 9, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_IO_RD_PRI_FIXED[] = { + { "GROUP0_FIXED_COEFFICIENT", 0, 2, &umr_bitfield_default }, + { "GROUP1_FIXED_COEFFICIENT", 3, 5, &umr_bitfield_default }, + { "GROUP2_FIXED_COEFFICIENT", 6, 8, &umr_bitfield_default }, + { "GROUP3_FIXED_COEFFICIENT", 9, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_IO_WR_PRI_FIXED[] = { + { "GROUP0_FIXED_COEFFICIENT", 0, 2, &umr_bitfield_default }, + { "GROUP1_FIXED_COEFFICIENT", 3, 5, &umr_bitfield_default }, + { "GROUP2_FIXED_COEFFICIENT", 6, 8, &umr_bitfield_default }, + { "GROUP3_FIXED_COEFFICIENT", 9, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_IO_RD_PRI_URGENCY[] = { + { "GROUP0_URGENCY_COEFFICIENT", 0, 2, &umr_bitfield_default }, + { "GROUP1_URGENCY_COEFFICIENT", 3, 5, &umr_bitfield_default }, + { "GROUP2_URGENCY_COEFFICIENT", 6, 8, &umr_bitfield_default }, + { "GROUP3_URGENCY_COEFFICIENT", 9, 11, &umr_bitfield_default }, + { "GROUP0_URGENCY_MODE", 12, 12, &umr_bitfield_default }, + { "GROUP1_URGENCY_MODE", 13, 13, &umr_bitfield_default }, + { "GROUP2_URGENCY_MODE", 14, 14, &umr_bitfield_default }, + { "GROUP3_URGENCY_MODE", 15, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_IO_WR_PRI_URGENCY[] = { + { "GROUP0_URGENCY_COEFFICIENT", 0, 2, &umr_bitfield_default }, + { "GROUP1_URGENCY_COEFFICIENT", 3, 5, &umr_bitfield_default }, + { "GROUP2_URGENCY_COEFFICIENT", 6, 8, &umr_bitfield_default }, + { "GROUP3_URGENCY_COEFFICIENT", 9, 11, &umr_bitfield_default }, + { "GROUP0_URGENCY_MODE", 12, 12, &umr_bitfield_default }, + { "GROUP1_URGENCY_MODE", 13, 13, &umr_bitfield_default }, + { "GROUP2_URGENCY_MODE", 14, 14, &umr_bitfield_default }, + { "GROUP3_URGENCY_MODE", 15, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_IO_RD_PRI_URGENCY_MASK[] = { + { "CID0_MASK", 0, 0, &umr_bitfield_default }, + { "CID1_MASK", 1, 1, &umr_bitfield_default }, + { "CID2_MASK", 2, 2, &umr_bitfield_default }, + { "CID3_MASK", 3, 3, &umr_bitfield_default }, + { "CID4_MASK", 4, 4, &umr_bitfield_default }, + { "CID5_MASK", 5, 5, &umr_bitfield_default }, + { "CID6_MASK", 6, 6, &umr_bitfield_default }, + { "CID7_MASK", 7, 7, &umr_bitfield_default }, + { "CID8_MASK", 8, 8, &umr_bitfield_default }, + { "CID9_MASK", 9, 9, &umr_bitfield_default }, + { "CID10_MASK", 10, 10, &umr_bitfield_default }, + { "CID11_MASK", 11, 11, &umr_bitfield_default }, + { "CID12_MASK", 12, 12, &umr_bitfield_default }, + { "CID13_MASK", 13, 13, &umr_bitfield_default }, + { "CID14_MASK", 14, 14, &umr_bitfield_default }, + { "CID15_MASK", 15, 15, &umr_bitfield_default }, + { "CID16_MASK", 16, 16, &umr_bitfield_default }, + { "CID17_MASK", 17, 17, &umr_bitfield_default }, + { "CID18_MASK", 18, 18, &umr_bitfield_default }, + { "CID19_MASK", 19, 19, &umr_bitfield_default }, + { "CID20_MASK", 20, 20, &umr_bitfield_default }, + { "CID21_MASK", 21, 21, &umr_bitfield_default }, + { "CID22_MASK", 22, 22, &umr_bitfield_default }, + { "CID23_MASK", 23, 23, &umr_bitfield_default }, + { "CID24_MASK", 24, 24, &umr_bitfield_default }, + { "CID25_MASK", 25, 25, &umr_bitfield_default }, + { "CID26_MASK", 26, 26, &umr_bitfield_default }, + { "CID27_MASK", 27, 27, &umr_bitfield_default }, + { "CID28_MASK", 28, 28, &umr_bitfield_default }, + { "CID29_MASK", 29, 29, &umr_bitfield_default }, + { "CID30_MASK", 30, 30, &umr_bitfield_default }, + { "CID31_MASK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_IO_WR_PRI_URGENCY_MASK[] = { + { "CID0_MASK", 0, 0, &umr_bitfield_default }, + { "CID1_MASK", 1, 1, &umr_bitfield_default }, + { "CID2_MASK", 2, 2, &umr_bitfield_default }, + { "CID3_MASK", 3, 3, &umr_bitfield_default }, + { "CID4_MASK", 4, 4, &umr_bitfield_default }, + { "CID5_MASK", 5, 5, &umr_bitfield_default }, + { "CID6_MASK", 6, 6, &umr_bitfield_default }, + { "CID7_MASK", 7, 7, &umr_bitfield_default }, + { "CID8_MASK", 8, 8, &umr_bitfield_default }, + { "CID9_MASK", 9, 9, &umr_bitfield_default }, + { "CID10_MASK", 10, 10, &umr_bitfield_default }, + { "CID11_MASK", 11, 11, &umr_bitfield_default }, + { "CID12_MASK", 12, 12, &umr_bitfield_default }, + { "CID13_MASK", 13, 13, &umr_bitfield_default }, + { "CID14_MASK", 14, 14, &umr_bitfield_default }, + { "CID15_MASK", 15, 15, &umr_bitfield_default }, + { "CID16_MASK", 16, 16, &umr_bitfield_default }, + { "CID17_MASK", 17, 17, &umr_bitfield_default }, + { "CID18_MASK", 18, 18, &umr_bitfield_default }, + { "CID19_MASK", 19, 19, &umr_bitfield_default }, + { "CID20_MASK", 20, 20, &umr_bitfield_default }, + { "CID21_MASK", 21, 21, &umr_bitfield_default }, + { "CID22_MASK", 22, 22, &umr_bitfield_default }, + { "CID23_MASK", 23, 23, &umr_bitfield_default }, + { "CID24_MASK", 24, 24, &umr_bitfield_default }, + { "CID25_MASK", 25, 25, &umr_bitfield_default }, + { "CID26_MASK", 26, 26, &umr_bitfield_default }, + { "CID27_MASK", 27, 27, &umr_bitfield_default }, + { "CID28_MASK", 28, 28, &umr_bitfield_default }, + { "CID29_MASK", 29, 29, &umr_bitfield_default }, + { "CID30_MASK", 30, 30, &umr_bitfield_default }, + { "CID31_MASK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_IO_RD_PRI_QUANT_PRI1[] = { + { "GROUP0_THRESHOLD", 0, 7, &umr_bitfield_default }, + { "GROUP1_THRESHOLD", 8, 15, &umr_bitfield_default }, + { "GROUP2_THRESHOLD", 16, 23, &umr_bitfield_default }, + { "GROUP3_THRESHOLD", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_IO_RD_PRI_QUANT_PRI2[] = { + { "GROUP0_THRESHOLD", 0, 7, &umr_bitfield_default }, + { "GROUP1_THRESHOLD", 8, 15, &umr_bitfield_default }, + { "GROUP2_THRESHOLD", 16, 23, &umr_bitfield_default }, + { "GROUP3_THRESHOLD", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_IO_RD_PRI_QUANT_PRI3[] = { + { "GROUP0_THRESHOLD", 0, 7, &umr_bitfield_default }, + { "GROUP1_THRESHOLD", 8, 15, &umr_bitfield_default }, + { "GROUP2_THRESHOLD", 16, 23, &umr_bitfield_default }, + { "GROUP3_THRESHOLD", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_IO_WR_PRI_QUANT_PRI1[] = { + { "GROUP0_THRESHOLD", 0, 7, &umr_bitfield_default }, + { "GROUP1_THRESHOLD", 8, 15, &umr_bitfield_default }, + { "GROUP2_THRESHOLD", 16, 23, &umr_bitfield_default }, + { "GROUP3_THRESHOLD", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_IO_WR_PRI_QUANT_PRI2[] = { + { "GROUP0_THRESHOLD", 0, 7, &umr_bitfield_default }, + { "GROUP1_THRESHOLD", 8, 15, &umr_bitfield_default }, + { "GROUP2_THRESHOLD", 16, 23, &umr_bitfield_default }, + { "GROUP3_THRESHOLD", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_IO_WR_PRI_QUANT_PRI3[] = { + { "GROUP0_THRESHOLD", 0, 7, &umr_bitfield_default }, + { "GROUP1_THRESHOLD", 8, 15, &umr_bitfield_default }, + { "GROUP2_THRESHOLD", 16, 23, &umr_bitfield_default }, + { "GROUP3_THRESHOLD", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_SDP_ARB_DRAM[] = { + { "RDWR_BURST_LIMIT_CYCL", 0, 6, &umr_bitfield_default }, + { "RDWR_BURST_LIMIT_DATA", 8, 14, &umr_bitfield_default }, + { "EARLY_SW2RD_ON_PRI", 16, 16, &umr_bitfield_default }, + { "EARLY_SW2WR_ON_PRI", 17, 17, &umr_bitfield_default }, + { "EARLY_SW2RD_ON_RES", 18, 18, &umr_bitfield_default }, + { "EARLY_SW2WR_ON_RES", 19, 19, &umr_bitfield_default }, + { "EOB_ON_EXPIRE", 20, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_SDP_ARB_FINAL[] = { + { "DRAM_BURST_LIMIT", 0, 4, &umr_bitfield_default }, + { "GMI_BURST_LIMIT", 5, 9, &umr_bitfield_default }, + { "IO_BURST_LIMIT", 10, 14, &umr_bitfield_default }, + { "BURST_LIMIT_MULTIPLIER", 15, 16, &umr_bitfield_default }, + { "RDONLY_VC0", 17, 17, &umr_bitfield_default }, + { "RDONLY_VC1", 18, 18, &umr_bitfield_default }, + { "RDONLY_VC2", 19, 19, &umr_bitfield_default }, + { "RDONLY_VC3", 20, 20, &umr_bitfield_default }, + { "RDONLY_VC4", 21, 21, &umr_bitfield_default }, + { "RDONLY_VC5", 22, 22, &umr_bitfield_default }, + { "RDONLY_VC6", 23, 23, &umr_bitfield_default }, + { "RDONLY_VC7", 24, 24, &umr_bitfield_default }, + { "ERREVENT_ON_ERROR", 25, 25, &umr_bitfield_default }, + { "HALTREQ_ON_ERROR", 26, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_SDP_DRAM_PRIORITY[] = { + { "RD_GROUP0_PRIORITY", 0, 3, &umr_bitfield_default }, + { "RD_GROUP1_PRIORITY", 4, 7, &umr_bitfield_default }, + { "RD_GROUP2_PRIORITY", 8, 11, &umr_bitfield_default }, + { "RD_GROUP3_PRIORITY", 12, 15, &umr_bitfield_default }, + { "WR_GROUP0_PRIORITY", 16, 19, &umr_bitfield_default }, + { "WR_GROUP1_PRIORITY", 20, 23, &umr_bitfield_default }, + { "WR_GROUP2_PRIORITY", 24, 27, &umr_bitfield_default }, + { "WR_GROUP3_PRIORITY", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_SDP_IO_PRIORITY[] = { + { "RD_GROUP0_PRIORITY", 0, 3, &umr_bitfield_default }, + { "RD_GROUP1_PRIORITY", 4, 7, &umr_bitfield_default }, + { "RD_GROUP2_PRIORITY", 8, 11, &umr_bitfield_default }, + { "RD_GROUP3_PRIORITY", 12, 15, &umr_bitfield_default }, + { "WR_GROUP0_PRIORITY", 16, 19, &umr_bitfield_default }, + { "WR_GROUP1_PRIORITY", 20, 23, &umr_bitfield_default }, + { "WR_GROUP2_PRIORITY", 24, 27, &umr_bitfield_default }, + { "WR_GROUP3_PRIORITY", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_SDP_CREDITS[] = { + { "TAG_LIMIT", 0, 7, &umr_bitfield_default }, + { "WR_RESP_CREDITS", 8, 14, &umr_bitfield_default }, + { "RD_RESP_CREDITS", 16, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_SDP_TAG_RESERVE0[] = { + { "VC0", 0, 7, &umr_bitfield_default }, + { "VC1", 8, 15, &umr_bitfield_default }, + { "VC2", 16, 23, &umr_bitfield_default }, + { "VC3", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_SDP_TAG_RESERVE1[] = { + { "VC4", 0, 7, &umr_bitfield_default }, + { "VC5", 8, 15, &umr_bitfield_default }, + { "VC6", 16, 23, &umr_bitfield_default }, + { "VC7", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_SDP_VCC_RESERVE0[] = { + { "VC0_CREDITS", 0, 5, &umr_bitfield_default }, + { "VC1_CREDITS", 6, 11, &umr_bitfield_default }, + { "VC2_CREDITS", 12, 17, &umr_bitfield_default }, + { "VC3_CREDITS", 18, 23, &umr_bitfield_default }, + { "VC4_CREDITS", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_SDP_VCC_RESERVE1[] = { + { "VC5_CREDITS", 0, 5, &umr_bitfield_default }, + { "VC6_CREDITS", 6, 11, &umr_bitfield_default }, + { "VC7_CREDITS", 12, 17, &umr_bitfield_default }, + { "DISTRIBUTE_POOL", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_SDP_VCD_RESERVE0[] = { + { "VC0_CREDITS", 0, 5, &umr_bitfield_default }, + { "VC1_CREDITS", 6, 11, &umr_bitfield_default }, + { "VC2_CREDITS", 12, 17, &umr_bitfield_default }, + { "VC3_CREDITS", 18, 23, &umr_bitfield_default }, + { "VC4_CREDITS", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_SDP_VCD_RESERVE1[] = { + { "VC5_CREDITS", 0, 5, &umr_bitfield_default }, + { "VC6_CREDITS", 6, 11, &umr_bitfield_default }, + { "VC7_CREDITS", 12, 17, &umr_bitfield_default }, + { "DISTRIBUTE_POOL", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_SDP_REQ_CNTL[] = { + { "REQ_PASS_PW_OVERRIDE_READ", 0, 0, &umr_bitfield_default }, + { "REQ_PASS_PW_OVERRIDE_WRITE", 1, 1, &umr_bitfield_default }, + { "REQ_PASS_PW_OVERRIDE_ATOMIC", 2, 2, &umr_bitfield_default }, + { "REQ_CHAIN_OVERRIDE_DRAM", 3, 3, &umr_bitfield_default }, + { "INNER_DOMAIN_MODE", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_MISC[] = { + { "RELATIVE_PRI_IN_DRAM_RD_ARB", 0, 0, &umr_bitfield_default }, + { "RELATIVE_PRI_IN_DRAM_WR_ARB", 1, 1, &umr_bitfield_default }, + { "RELATIVE_PRI_IN_GMI_RD_ARB", 2, 2, &umr_bitfield_default }, + { "RELATIVE_PRI_IN_GMI_WR_ARB", 3, 3, &umr_bitfield_default }, + { "RELATIVE_PRI_IN_IO_RD_ARB", 4, 4, &umr_bitfield_default }, + { "RELATIVE_PRI_IN_IO_WR_ARB", 5, 5, &umr_bitfield_default }, + { "RRET_SWAP_MODE", 6, 6, &umr_bitfield_default }, + { "EARLY_SDP_ORIGDATA", 7, 7, &umr_bitfield_default }, + { "LINKMGR_DYNAMIC_MODE", 8, 9, &umr_bitfield_default }, + { "LINKMGR_HALT_THRESHOLD", 10, 11, &umr_bitfield_default }, + { "LINKMGR_RECONNECT_DELAY", 12, 13, &umr_bitfield_default }, + { "LINKMGR_IDLE_THRESHOLD", 14, 18, &umr_bitfield_default }, + { "FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB", 19, 19, &umr_bitfield_default }, + { "FAVOUR_MIDCHAIN_CS_IN_GMI_ARB", 20, 20, &umr_bitfield_default }, + { "FAVOUR_LAST_CS_IN_DRAM_ARB", 21, 21, &umr_bitfield_default }, + { "FAVOUR_LAST_CS_IN_GMI_ARB", 22, 22, &umr_bitfield_default }, + { "SWITCH_CS_ON_W2R_IN_DRAM_ARB", 23, 23, &umr_bitfield_default }, + { "SWITCH_CS_ON_W2R_IN_GMI_ARB", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_LATENCY_SAMPLING[] = { + { "SAMPLER0_DRAM", 0, 0, &umr_bitfield_default }, + { "SAMPLER1_DRAM", 1, 1, &umr_bitfield_default }, + { "SAMPLER0_GMI", 2, 2, &umr_bitfield_default }, + { "SAMPLER1_GMI", 3, 3, &umr_bitfield_default }, + { "SAMPLER0_IO", 4, 4, &umr_bitfield_default }, + { "SAMPLER1_IO", 5, 5, &umr_bitfield_default }, + { "SAMPLER0_READ", 6, 6, &umr_bitfield_default }, + { "SAMPLER1_READ", 7, 7, &umr_bitfield_default }, + { "SAMPLER0_WRITE", 8, 8, &umr_bitfield_default }, + { "SAMPLER1_WRITE", 9, 9, &umr_bitfield_default }, + { "SAMPLER0_ATOMIC_RET", 10, 10, &umr_bitfield_default }, + { "SAMPLER1_ATOMIC_RET", 11, 11, &umr_bitfield_default }, + { "SAMPLER0_ATOMIC_NORET", 12, 12, &umr_bitfield_default }, + { "SAMPLER1_ATOMIC_NORET", 13, 13, &umr_bitfield_default }, + { "SAMPLER0_VC", 14, 21, &umr_bitfield_default }, + { "SAMPLER1_VC", 22, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_PERFCOUNTER_LO[] = { + { "COUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_PERFCOUNTER_HI[] = { + { "COUNTER_HI", 0, 15, &umr_bitfield_default }, + { "COMPARE_VALUE", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_PERFCOUNTER0_CFG[] = { + { "PERF_SEL", 0, 7, &umr_bitfield_default }, + { "PERF_SEL_END", 8, 15, &umr_bitfield_default }, + { "PERF_MODE", 24, 27, &umr_bitfield_default }, + { "ENABLE", 28, 28, &umr_bitfield_default }, + { "CLEAR", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_PERFCOUNTER1_CFG[] = { + { "PERF_SEL", 0, 7, &umr_bitfield_default }, + { "PERF_SEL_END", 8, 15, &umr_bitfield_default }, + { "PERF_MODE", 24, 27, &umr_bitfield_default }, + { "ENABLE", 28, 28, &umr_bitfield_default }, + { "CLEAR", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_PERFCOUNTER_RSLT_CNTL[] = { + { "PERF_COUNTER_SELECT", 0, 3, &umr_bitfield_default }, + { "START_TRIGGER", 8, 15, &umr_bitfield_default }, + { "STOP_TRIGGER", 16, 23, &umr_bitfield_default }, + { "ENABLE_ANY", 24, 24, &umr_bitfield_default }, + { "CLEAR_ALL", 25, 25, &umr_bitfield_default }, + { "STOP_ALL_ON_SATURATE", 26, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_EDC_CNT[] = { + { "DRAMRD_CMDMEM_SEC_COUNT", 0, 1, &umr_bitfield_default }, + { "DRAMRD_CMDMEM_DED_COUNT", 2, 3, &umr_bitfield_default }, + { "DRAMWR_CMDMEM_SEC_COUNT", 4, 5, &umr_bitfield_default }, + { "DRAMWR_CMDMEM_DED_COUNT", 6, 7, &umr_bitfield_default }, + { "DRAMWR_DATAMEM_SEC_COUNT", 8, 9, &umr_bitfield_default }, + { "DRAMWR_DATAMEM_DED_COUNT", 10, 11, &umr_bitfield_default }, + { "RRET_TAGMEM_SEC_COUNT", 12, 13, &umr_bitfield_default }, + { "RRET_TAGMEM_DED_COUNT", 14, 15, &umr_bitfield_default }, + { "WRET_TAGMEM_SEC_COUNT", 16, 17, &umr_bitfield_default }, + { "WRET_TAGMEM_DED_COUNT", 18, 19, &umr_bitfield_default }, + { "DRAMRD_PAGEMEM_SED_COUNT", 20, 21, &umr_bitfield_default }, + { "DRAMWR_PAGEMEM_SED_COUNT", 22, 23, &umr_bitfield_default }, + { "IORD_CMDMEM_SED_COUNT", 24, 25, &umr_bitfield_default }, + { "IOWR_CMDMEM_SED_COUNT", 26, 27, &umr_bitfield_default }, + { "IOWR_DATAMEM_SED_COUNT", 28, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_EDC_CNT2[] = { + { "GMIRD_CMDMEM_SEC_COUNT", 0, 1, &umr_bitfield_default }, + { "GMIRD_CMDMEM_DED_COUNT", 2, 3, &umr_bitfield_default }, + { "GMIWR_CMDMEM_SEC_COUNT", 4, 5, &umr_bitfield_default }, + { "GMIWR_CMDMEM_DED_COUNT", 6, 7, &umr_bitfield_default }, + { "GMIWR_DATAMEM_SEC_COUNT", 8, 9, &umr_bitfield_default }, + { "GMIWR_DATAMEM_DED_COUNT", 10, 11, &umr_bitfield_default }, + { "GMIRD_PAGEMEM_SED_COUNT", 12, 13, &umr_bitfield_default }, + { "GMIWR_PAGEMEM_SED_COUNT", 14, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_DSM_CNTL[] = { + { "DRAMRD_CMDMEM_DSM_IRRITATOR_DATA", 0, 1, &umr_bitfield_default }, + { "DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE", 2, 2, &umr_bitfield_default }, + { "DRAMWR_CMDMEM_DSM_IRRITATOR_DATA", 3, 4, &umr_bitfield_default }, + { "DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE", 5, 5, &umr_bitfield_default }, + { "DRAMWR_DATAMEM_DSM_IRRITATOR_DATA", 6, 7, &umr_bitfield_default }, + { "DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE", 8, 8, &umr_bitfield_default }, + { "RRET_TAGMEM_DSM_IRRITATOR_DATA", 9, 10, &umr_bitfield_default }, + { "RRET_TAGMEM_ENABLE_SINGLE_WRITE", 11, 11, &umr_bitfield_default }, + { "WRET_TAGMEM_DSM_IRRITATOR_DATA", 12, 13, &umr_bitfield_default }, + { "WRET_TAGMEM_ENABLE_SINGLE_WRITE", 14, 14, &umr_bitfield_default }, + { "GMIRD_CMDMEM_DSM_IRRITATOR_DATA", 15, 16, &umr_bitfield_default }, + { "GMIRD_CMDMEM_ENABLE_SINGLE_WRITE", 17, 17, &umr_bitfield_default }, + { "GMIWR_CMDMEM_DSM_IRRITATOR_DATA", 18, 19, &umr_bitfield_default }, + { "GMIWR_CMDMEM_ENABLE_SINGLE_WRITE", 20, 20, &umr_bitfield_default }, + { "GMIWR_DATAMEM_DSM_IRRITATOR_DATA", 21, 22, &umr_bitfield_default }, + { "GMIWR_DATAMEM_ENABLE_SINGLE_WRITE", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_DSM_CNTLA[] = { + { "DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA", 0, 1, &umr_bitfield_default }, + { "DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE", 2, 2, &umr_bitfield_default }, + { "DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA", 3, 4, &umr_bitfield_default }, + { "DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE", 5, 5, &umr_bitfield_default }, + { "IORD_CMDMEM_DSM_IRRITATOR_DATA", 6, 7, &umr_bitfield_default }, + { "IORD_CMDMEM_ENABLE_SINGLE_WRITE", 8, 8, &umr_bitfield_default }, + { "IOWR_CMDMEM_DSM_IRRITATOR_DATA", 9, 10, &umr_bitfield_default }, + { "IOWR_CMDMEM_ENABLE_SINGLE_WRITE", 11, 11, &umr_bitfield_default }, + { "IOWR_DATAMEM_DSM_IRRITATOR_DATA", 12, 13, &umr_bitfield_default }, + { "IOWR_DATAMEM_ENABLE_SINGLE_WRITE", 14, 14, &umr_bitfield_default }, + { "GMIRD_PAGEMEM_DSM_IRRITATOR_DATA", 15, 16, &umr_bitfield_default }, + { "GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE", 17, 17, &umr_bitfield_default }, + { "GMIWR_PAGEMEM_DSM_IRRITATOR_DATA", 18, 19, &umr_bitfield_default }, + { "GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE", 20, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_DSM_CNTL2[] = { + { "DRAMRD_CMDMEM_ENABLE_ERROR_INJECT", 0, 1, &umr_bitfield_default }, + { "DRAMRD_CMDMEM_SELECT_INJECT_DELAY", 2, 2, &umr_bitfield_default }, + { "DRAMWR_CMDMEM_ENABLE_ERROR_INJECT", 3, 4, &umr_bitfield_default }, + { "DRAMWR_CMDMEM_SELECT_INJECT_DELAY", 5, 5, &umr_bitfield_default }, + { "DRAMWR_DATAMEM_ENABLE_ERROR_INJECT", 6, 7, &umr_bitfield_default }, + { "DRAMWR_DATAMEM_SELECT_INJECT_DELAY", 8, 8, &umr_bitfield_default }, + { "RRET_TAGMEM_ENABLE_ERROR_INJECT", 9, 10, &umr_bitfield_default }, + { "RRET_TAGMEM_SELECT_INJECT_DELAY", 11, 11, &umr_bitfield_default }, + { "WRET_TAGMEM_ENABLE_ERROR_INJECT", 12, 13, &umr_bitfield_default }, + { "WRET_TAGMEM_SELECT_INJECT_DELAY", 14, 14, &umr_bitfield_default }, + { "GMIRD_CMDMEM_ENABLE_ERROR_INJECT", 15, 16, &umr_bitfield_default }, + { "GMIRD_CMDMEM_SELECT_INJECT_DELAY", 17, 17, &umr_bitfield_default }, + { "GMIWR_CMDMEM_ENABLE_ERROR_INJECT", 18, 19, &umr_bitfield_default }, + { "GMIWR_CMDMEM_SELECT_INJECT_DELAY", 20, 20, &umr_bitfield_default }, + { "GMIWR_DATAMEM_ENABLE_ERROR_INJECT", 21, 22, &umr_bitfield_default }, + { "GMIWR_DATAMEM_SELECT_INJECT_DELAY", 23, 23, &umr_bitfield_default }, + { "INJECT_DELAY", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_DSM_CNTL2A[] = { + { "DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT", 0, 1, &umr_bitfield_default }, + { "DRAMRD_PAGEMEM_SELECT_INJECT_DELAY", 2, 2, &umr_bitfield_default }, + { "DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT", 3, 4, &umr_bitfield_default }, + { "DRAMWR_PAGEMEM_SELECT_INJECT_DELAY", 5, 5, &umr_bitfield_default }, + { "IORD_CMDMEM_ENABLE_ERROR_INJECT", 6, 7, &umr_bitfield_default }, + { "IORD_CMDMEM_SELECT_INJECT_DELAY", 8, 8, &umr_bitfield_default }, + { "IOWR_CMDMEM_ENABLE_ERROR_INJECT", 9, 10, &umr_bitfield_default }, + { "IOWR_CMDMEM_SELECT_INJECT_DELAY", 11, 11, &umr_bitfield_default }, + { "IOWR_DATAMEM_ENABLE_ERROR_INJECT", 12, 13, &umr_bitfield_default }, + { "IOWR_DATAMEM_SELECT_INJECT_DELAY", 14, 14, &umr_bitfield_default }, + { "GMIRD_PAGEMEM_ENABLE_ERROR_INJECT", 15, 16, &umr_bitfield_default }, + { "GMIRD_PAGEMEM_SELECT_INJECT_DELAY", 17, 17, &umr_bitfield_default }, + { "GMIWR_PAGEMEM_ENABLE_ERROR_INJECT", 18, 19, &umr_bitfield_default }, + { "GMIWR_PAGEMEM_SELECT_INJECT_DELAY", 20, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_CGTT_CLK_CTRL[] = { + { "ON_DELAY", 0, 3, &umr_bitfield_default }, + { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE", 22, 22, &umr_bitfield_default }, + { "LS_OVERRIDE", 27, 27, &umr_bitfield_default }, + { "SOFT_OVERRIDE_WRITE", 28, 28, &umr_bitfield_default }, + { "SOFT_OVERRIDE_READ", 29, 29, &umr_bitfield_default }, + { "SOFT_OVERRIDE_RETURN", 30, 30, &umr_bitfield_default }, + { "SOFT_OVERRIDE_REGISTER", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_EDC_MODE[] = { + { "COUNT_FED_OUT", 16, 16, &umr_bitfield_default }, + { "GATE_FUE", 17, 17, &umr_bitfield_default }, + { "DED_MODE", 20, 21, &umr_bitfield_default }, + { "PROP_FED", 29, 29, &umr_bitfield_default }, + { "BYPASS", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_ERR_STATUS[] = { + { "SDP_RDRSP_STATUS", 0, 3, &umr_bitfield_default }, + { "SDP_WRRSP_STATUS", 4, 7, &umr_bitfield_default }, + { "SDP_RDRSP_DATAPARITY_ERROR", 8, 8, &umr_bitfield_default }, + { "CLEAR_ERROR_STATUS", 9, 9, &umr_bitfield_default }, + { "BUSY_ON_ERROR", 10, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA0_MISC2[] = { + { "CSGROUP_SWAP_IN_DRAM_ARB", 0, 0, &umr_bitfield_default }, + { "CSGROUP_SWAP_IN_GMI_ARB", 1, 1, &umr_bitfield_default }, + { "CSGRP_BURST_LIMIT_DATA_DRAM", 2, 6, &umr_bitfield_default }, + { "CSGRP_BURST_LIMIT_DATA_GMI", 7, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_DRAM_RD_CLI2GRP_MAP0[] = { + { "CID0_GROUP", 0, 1, &umr_bitfield_default }, + { "CID1_GROUP", 2, 3, &umr_bitfield_default }, + { "CID2_GROUP", 4, 5, &umr_bitfield_default }, + { "CID3_GROUP", 6, 7, &umr_bitfield_default }, + { "CID4_GROUP", 8, 9, &umr_bitfield_default }, + { "CID5_GROUP", 10, 11, &umr_bitfield_default }, + { "CID6_GROUP", 12, 13, &umr_bitfield_default }, + { "CID7_GROUP", 14, 15, &umr_bitfield_default }, + { "CID8_GROUP", 16, 17, &umr_bitfield_default }, + { "CID9_GROUP", 18, 19, &umr_bitfield_default }, + { "CID10_GROUP", 20, 21, &umr_bitfield_default }, + { "CID11_GROUP", 22, 23, &umr_bitfield_default }, + { "CID12_GROUP", 24, 25, &umr_bitfield_default }, + { "CID13_GROUP", 26, 27, &umr_bitfield_default }, + { "CID14_GROUP", 28, 29, &umr_bitfield_default }, + { "CID15_GROUP", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_DRAM_RD_CLI2GRP_MAP1[] = { + { "CID16_GROUP", 0, 1, &umr_bitfield_default }, + { "CID17_GROUP", 2, 3, &umr_bitfield_default }, + { "CID18_GROUP", 4, 5, &umr_bitfield_default }, + { "CID19_GROUP", 6, 7, &umr_bitfield_default }, + { "CID20_GROUP", 8, 9, &umr_bitfield_default }, + { "CID21_GROUP", 10, 11, &umr_bitfield_default }, + { "CID22_GROUP", 12, 13, &umr_bitfield_default }, + { "CID23_GROUP", 14, 15, &umr_bitfield_default }, + { "CID24_GROUP", 16, 17, &umr_bitfield_default }, + { "CID25_GROUP", 18, 19, &umr_bitfield_default }, + { "CID26_GROUP", 20, 21, &umr_bitfield_default }, + { "CID27_GROUP", 22, 23, &umr_bitfield_default }, + { "CID28_GROUP", 24, 25, &umr_bitfield_default }, + { "CID29_GROUP", 26, 27, &umr_bitfield_default }, + { "CID30_GROUP", 28, 29, &umr_bitfield_default }, + { "CID31_GROUP", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_DRAM_WR_CLI2GRP_MAP0[] = { + { "CID0_GROUP", 0, 1, &umr_bitfield_default }, + { "CID1_GROUP", 2, 3, &umr_bitfield_default }, + { "CID2_GROUP", 4, 5, &umr_bitfield_default }, + { "CID3_GROUP", 6, 7, &umr_bitfield_default }, + { "CID4_GROUP", 8, 9, &umr_bitfield_default }, + { "CID5_GROUP", 10, 11, &umr_bitfield_default }, + { "CID6_GROUP", 12, 13, &umr_bitfield_default }, + { "CID7_GROUP", 14, 15, &umr_bitfield_default }, + { "CID8_GROUP", 16, 17, &umr_bitfield_default }, + { "CID9_GROUP", 18, 19, &umr_bitfield_default }, + { "CID10_GROUP", 20, 21, &umr_bitfield_default }, + { "CID11_GROUP", 22, 23, &umr_bitfield_default }, + { "CID12_GROUP", 24, 25, &umr_bitfield_default }, + { "CID13_GROUP", 26, 27, &umr_bitfield_default }, + { "CID14_GROUP", 28, 29, &umr_bitfield_default }, + { "CID15_GROUP", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_DRAM_WR_CLI2GRP_MAP1[] = { + { "CID16_GROUP", 0, 1, &umr_bitfield_default }, + { "CID17_GROUP", 2, 3, &umr_bitfield_default }, + { "CID18_GROUP", 4, 5, &umr_bitfield_default }, + { "CID19_GROUP", 6, 7, &umr_bitfield_default }, + { "CID20_GROUP", 8, 9, &umr_bitfield_default }, + { "CID21_GROUP", 10, 11, &umr_bitfield_default }, + { "CID22_GROUP", 12, 13, &umr_bitfield_default }, + { "CID23_GROUP", 14, 15, &umr_bitfield_default }, + { "CID24_GROUP", 16, 17, &umr_bitfield_default }, + { "CID25_GROUP", 18, 19, &umr_bitfield_default }, + { "CID26_GROUP", 20, 21, &umr_bitfield_default }, + { "CID27_GROUP", 22, 23, &umr_bitfield_default }, + { "CID28_GROUP", 24, 25, &umr_bitfield_default }, + { "CID29_GROUP", 26, 27, &umr_bitfield_default }, + { "CID30_GROUP", 28, 29, &umr_bitfield_default }, + { "CID31_GROUP", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_DRAM_RD_GRP2VC_MAP[] = { + { "GROUP0_VC", 0, 2, &umr_bitfield_default }, + { "GROUP1_VC", 3, 5, &umr_bitfield_default }, + { "GROUP2_VC", 6, 8, &umr_bitfield_default }, + { "GROUP3_VC", 9, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_DRAM_WR_GRP2VC_MAP[] = { + { "GROUP0_VC", 0, 2, &umr_bitfield_default }, + { "GROUP1_VC", 3, 5, &umr_bitfield_default }, + { "GROUP2_VC", 6, 8, &umr_bitfield_default }, + { "GROUP3_VC", 9, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_DRAM_RD_LAZY[] = { + { "GROUP0_DELAY", 0, 2, &umr_bitfield_default }, + { "GROUP1_DELAY", 3, 5, &umr_bitfield_default }, + { "GROUP2_DELAY", 6, 8, &umr_bitfield_default }, + { "GROUP3_DELAY", 9, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_DRAM_WR_LAZY[] = { + { "GROUP0_DELAY", 0, 2, &umr_bitfield_default }, + { "GROUP1_DELAY", 3, 5, &umr_bitfield_default }, + { "GROUP2_DELAY", 6, 8, &umr_bitfield_default }, + { "GROUP3_DELAY", 9, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_DRAM_RD_CAM_CNTL[] = { + { "DEPTH_GROUP0", 0, 3, &umr_bitfield_default }, + { "DEPTH_GROUP1", 4, 7, &umr_bitfield_default }, + { "DEPTH_GROUP2", 8, 11, &umr_bitfield_default }, + { "DEPTH_GROUP3", 12, 15, &umr_bitfield_default }, + { "REORDER_LIMIT_GROUP0", 16, 18, &umr_bitfield_default }, + { "REORDER_LIMIT_GROUP1", 19, 21, &umr_bitfield_default }, + { "REORDER_LIMIT_GROUP2", 22, 24, &umr_bitfield_default }, + { "REORDER_LIMIT_GROUP3", 25, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_DRAM_WR_CAM_CNTL[] = { + { "DEPTH_GROUP0", 0, 3, &umr_bitfield_default }, + { "DEPTH_GROUP1", 4, 7, &umr_bitfield_default }, + { "DEPTH_GROUP2", 8, 11, &umr_bitfield_default }, + { "DEPTH_GROUP3", 12, 15, &umr_bitfield_default }, + { "REORDER_LIMIT_GROUP0", 16, 18, &umr_bitfield_default }, + { "REORDER_LIMIT_GROUP1", 19, 21, &umr_bitfield_default }, + { "REORDER_LIMIT_GROUP2", 22, 24, &umr_bitfield_default }, + { "REORDER_LIMIT_GROUP3", 25, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_DRAM_PAGE_BURST[] = { + { "RD_LIMIT_LO", 0, 7, &umr_bitfield_default }, + { "RD_LIMIT_HI", 8, 15, &umr_bitfield_default }, + { "WR_LIMIT_LO", 16, 23, &umr_bitfield_default }, + { "WR_LIMIT_HI", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_DRAM_RD_PRI_AGE[] = { + { "GROUP0_AGING_RATE", 0, 2, &umr_bitfield_default }, + { "GROUP1_AGING_RATE", 3, 5, &umr_bitfield_default }, + { "GROUP2_AGING_RATE", 6, 8, &umr_bitfield_default }, + { "GROUP3_AGING_RATE", 9, 11, &umr_bitfield_default }, + { "GROUP0_AGE_COEFFICIENT", 12, 14, &umr_bitfield_default }, + { "GROUP1_AGE_COEFFICIENT", 15, 17, &umr_bitfield_default }, + { "GROUP2_AGE_COEFFICIENT", 18, 20, &umr_bitfield_default }, + { "GROUP3_AGE_COEFFICIENT", 21, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_DRAM_WR_PRI_AGE[] = { + { "GROUP0_AGING_RATE", 0, 2, &umr_bitfield_default }, + { "GROUP1_AGING_RATE", 3, 5, &umr_bitfield_default }, + { "GROUP2_AGING_RATE", 6, 8, &umr_bitfield_default }, + { "GROUP3_AGING_RATE", 9, 11, &umr_bitfield_default }, + { "GROUP0_AGE_COEFFICIENT", 12, 14, &umr_bitfield_default }, + { "GROUP1_AGE_COEFFICIENT", 15, 17, &umr_bitfield_default }, + { "GROUP2_AGE_COEFFICIENT", 18, 20, &umr_bitfield_default }, + { "GROUP3_AGE_COEFFICIENT", 21, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_DRAM_RD_PRI_QUEUING[] = { + { "GROUP0_QUEUING_COEFFICIENT", 0, 2, &umr_bitfield_default }, + { "GROUP1_QUEUING_COEFFICIENT", 3, 5, &umr_bitfield_default }, + { "GROUP2_QUEUING_COEFFICIENT", 6, 8, &umr_bitfield_default }, + { "GROUP3_QUEUING_COEFFICIENT", 9, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_DRAM_WR_PRI_QUEUING[] = { + { "GROUP0_QUEUING_COEFFICIENT", 0, 2, &umr_bitfield_default }, + { "GROUP1_QUEUING_COEFFICIENT", 3, 5, &umr_bitfield_default }, + { "GROUP2_QUEUING_COEFFICIENT", 6, 8, &umr_bitfield_default }, + { "GROUP3_QUEUING_COEFFICIENT", 9, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_DRAM_RD_PRI_FIXED[] = { + { "GROUP0_FIXED_COEFFICIENT", 0, 2, &umr_bitfield_default }, + { "GROUP1_FIXED_COEFFICIENT", 3, 5, &umr_bitfield_default }, + { "GROUP2_FIXED_COEFFICIENT", 6, 8, &umr_bitfield_default }, + { "GROUP3_FIXED_COEFFICIENT", 9, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_DRAM_WR_PRI_FIXED[] = { + { "GROUP0_FIXED_COEFFICIENT", 0, 2, &umr_bitfield_default }, + { "GROUP1_FIXED_COEFFICIENT", 3, 5, &umr_bitfield_default }, + { "GROUP2_FIXED_COEFFICIENT", 6, 8, &umr_bitfield_default }, + { "GROUP3_FIXED_COEFFICIENT", 9, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_DRAM_RD_PRI_URGENCY[] = { + { "GROUP0_URGENCY_COEFFICIENT", 0, 2, &umr_bitfield_default }, + { "GROUP1_URGENCY_COEFFICIENT", 3, 5, &umr_bitfield_default }, + { "GROUP2_URGENCY_COEFFICIENT", 6, 8, &umr_bitfield_default }, + { "GROUP3_URGENCY_COEFFICIENT", 9, 11, &umr_bitfield_default }, + { "GROUP0_URGENCY_MODE", 12, 12, &umr_bitfield_default }, + { "GROUP1_URGENCY_MODE", 13, 13, &umr_bitfield_default }, + { "GROUP2_URGENCY_MODE", 14, 14, &umr_bitfield_default }, + { "GROUP3_URGENCY_MODE", 15, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_DRAM_WR_PRI_URGENCY[] = { + { "GROUP0_URGENCY_COEFFICIENT", 0, 2, &umr_bitfield_default }, + { "GROUP1_URGENCY_COEFFICIENT", 3, 5, &umr_bitfield_default }, + { "GROUP2_URGENCY_COEFFICIENT", 6, 8, &umr_bitfield_default }, + { "GROUP3_URGENCY_COEFFICIENT", 9, 11, &umr_bitfield_default }, + { "GROUP0_URGENCY_MODE", 12, 12, &umr_bitfield_default }, + { "GROUP1_URGENCY_MODE", 13, 13, &umr_bitfield_default }, + { "GROUP2_URGENCY_MODE", 14, 14, &umr_bitfield_default }, + { "GROUP3_URGENCY_MODE", 15, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_DRAM_RD_PRI_QUANT_PRI1[] = { + { "GROUP0_THRESHOLD", 0, 7, &umr_bitfield_default }, + { "GROUP1_THRESHOLD", 8, 15, &umr_bitfield_default }, + { "GROUP2_THRESHOLD", 16, 23, &umr_bitfield_default }, + { "GROUP3_THRESHOLD", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_DRAM_RD_PRI_QUANT_PRI2[] = { + { "GROUP0_THRESHOLD", 0, 7, &umr_bitfield_default }, + { "GROUP1_THRESHOLD", 8, 15, &umr_bitfield_default }, + { "GROUP2_THRESHOLD", 16, 23, &umr_bitfield_default }, + { "GROUP3_THRESHOLD", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_DRAM_RD_PRI_QUANT_PRI3[] = { + { "GROUP0_THRESHOLD", 0, 7, &umr_bitfield_default }, + { "GROUP1_THRESHOLD", 8, 15, &umr_bitfield_default }, + { "GROUP2_THRESHOLD", 16, 23, &umr_bitfield_default }, + { "GROUP3_THRESHOLD", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_DRAM_WR_PRI_QUANT_PRI1[] = { + { "GROUP0_THRESHOLD", 0, 7, &umr_bitfield_default }, + { "GROUP1_THRESHOLD", 8, 15, &umr_bitfield_default }, + { "GROUP2_THRESHOLD", 16, 23, &umr_bitfield_default }, + { "GROUP3_THRESHOLD", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_DRAM_WR_PRI_QUANT_PRI2[] = { + { "GROUP0_THRESHOLD", 0, 7, &umr_bitfield_default }, + { "GROUP1_THRESHOLD", 8, 15, &umr_bitfield_default }, + { "GROUP2_THRESHOLD", 16, 23, &umr_bitfield_default }, + { "GROUP3_THRESHOLD", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_DRAM_WR_PRI_QUANT_PRI3[] = { + { "GROUP0_THRESHOLD", 0, 7, &umr_bitfield_default }, + { "GROUP1_THRESHOLD", 8, 15, &umr_bitfield_default }, + { "GROUP2_THRESHOLD", 16, 23, &umr_bitfield_default }, + { "GROUP3_THRESHOLD", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_ADDRNORM_BASE_ADDR0[] = { + { "ADDR_RNG_VAL", 0, 0, &umr_bitfield_default }, + { "LGCY_MMIO_HOLE_EN", 1, 1, &umr_bitfield_default }, + { "INTLV_NUM_CHAN", 4, 7, &umr_bitfield_default }, + { "INTLV_ADDR_SEL", 8, 10, &umr_bitfield_default }, + { "BASE_ADDR", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_ADDRNORM_LIMIT_ADDR0[] = { + { "DST_FABRIC_ID", 0, 3, &umr_bitfield_default }, + { "INTLV_NUM_SOCKETS", 8, 8, &umr_bitfield_default }, + { "INTLV_NUM_DIES", 10, 11, &umr_bitfield_default }, + { "LIMIT_ADDR", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_ADDRNORM_BASE_ADDR1[] = { + { "ADDR_RNG_VAL", 0, 0, &umr_bitfield_default }, + { "LGCY_MMIO_HOLE_EN", 1, 1, &umr_bitfield_default }, + { "INTLV_NUM_CHAN", 4, 7, &umr_bitfield_default }, + { "INTLV_ADDR_SEL", 8, 10, &umr_bitfield_default }, + { "BASE_ADDR", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_ADDRNORM_LIMIT_ADDR1[] = { + { "DST_FABRIC_ID", 0, 3, &umr_bitfield_default }, + { "INTLV_NUM_SOCKETS", 8, 8, &umr_bitfield_default }, + { "INTLV_NUM_DIES", 10, 11, &umr_bitfield_default }, + { "LIMIT_ADDR", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_ADDRNORM_OFFSET_ADDR1[] = { + { "HI_ADDR_OFFSET_EN", 0, 0, &umr_bitfield_default }, + { "HI_ADDR_OFFSET", 20, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_ADDRNORM_HOLE_CNTL[] = { + { "DRAM_HOLE_VALID", 0, 0, &umr_bitfield_default }, + { "DRAM_HOLE_OFFSET", 7, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_ADDRDEC_BANK_CFG[] = { + { "BANK_MASK_DRAM", 0, 4, &umr_bitfield_default }, + { "BANK_MASK_GMI", 5, 9, &umr_bitfield_default }, + { "BANKGROUP_SEL_DRAM", 10, 12, &umr_bitfield_default }, + { "BANKGROUP_SEL_GMI", 13, 15, &umr_bitfield_default }, + { "BANKGROUP_INTERLEAVE_DRAM", 16, 16, &umr_bitfield_default }, + { "BANKGROUP_INTERLEAVE_GMI", 17, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_ADDRDEC_MISC_CFG[] = { + { "VCM_EN0", 0, 0, &umr_bitfield_default }, + { "VCM_EN1", 1, 1, &umr_bitfield_default }, + { "VCM_EN2", 2, 2, &umr_bitfield_default }, + { "VCM_EN3", 3, 3, &umr_bitfield_default }, + { "VCM_EN4", 4, 4, &umr_bitfield_default }, + { "PCH_MASK_DRAM", 8, 8, &umr_bitfield_default }, + { "PCH_MASK_GMI", 9, 9, &umr_bitfield_default }, + { "CH_MASK_DRAM", 12, 15, &umr_bitfield_default }, + { "CH_MASK_GMI", 16, 19, &umr_bitfield_default }, + { "CS_MASK_DRAM", 20, 21, &umr_bitfield_default }, + { "CS_MASK_GMI", 22, 23, &umr_bitfield_default }, + { "RM_MASK_DRAM", 24, 26, &umr_bitfield_default }, + { "RM_MASK_GMI", 27, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK0[] = { + { "XOR_ENABLE", 0, 0, &umr_bitfield_default }, + { "COL_XOR", 1, 13, &umr_bitfield_default }, + { "ROW_XOR", 14, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK1[] = { + { "XOR_ENABLE", 0, 0, &umr_bitfield_default }, + { "COL_XOR", 1, 13, &umr_bitfield_default }, + { "ROW_XOR", 14, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK2[] = { + { "XOR_ENABLE", 0, 0, &umr_bitfield_default }, + { "COL_XOR", 1, 13, &umr_bitfield_default }, + { "ROW_XOR", 14, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK3[] = { + { "XOR_ENABLE", 0, 0, &umr_bitfield_default }, + { "COL_XOR", 1, 13, &umr_bitfield_default }, + { "ROW_XOR", 14, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK4[] = { + { "XOR_ENABLE", 0, 0, &umr_bitfield_default }, + { "COL_XOR", 1, 13, &umr_bitfield_default }, + { "ROW_XOR", 14, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC[] = { + { "XOR_ENABLE", 0, 0, &umr_bitfield_default }, + { "COL_XOR", 1, 13, &umr_bitfield_default }, + { "ROW_XOR", 14, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC2[] = { + { "BANK_XOR", 0, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS0[] = { + { "XOR_ENABLE", 0, 0, &umr_bitfield_default }, + { "NA_XOR", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS1[] = { + { "XOR_ENABLE", 0, 0, &umr_bitfield_default }, + { "NA_XOR", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_ADDRDECDRAM_HARVEST_ENABLE[] = { + { "FORCE_B3_EN", 0, 0, &umr_bitfield_default }, + { "FORCE_B3_VAL", 1, 1, &umr_bitfield_default }, + { "FORCE_B4_EN", 2, 2, &umr_bitfield_default }, + { "FORCE_B4_VAL", 3, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_ADDRDEC0_BASE_ADDR_CS0[] = { + { "CS_ENABLE", 0, 0, &umr_bitfield_default }, + { "BASE_ADDR", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_ADDRDEC0_BASE_ADDR_CS1[] = { + { "CS_ENABLE", 0, 0, &umr_bitfield_default }, + { "BASE_ADDR", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_ADDRDEC0_BASE_ADDR_CS2[] = { + { "CS_ENABLE", 0, 0, &umr_bitfield_default }, + { "BASE_ADDR", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_ADDRDEC0_BASE_ADDR_CS3[] = { + { "CS_ENABLE", 0, 0, &umr_bitfield_default }, + { "BASE_ADDR", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS0[] = { + { "CS_ENABLE", 0, 0, &umr_bitfield_default }, + { "BASE_ADDR", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS1[] = { + { "CS_ENABLE", 0, 0, &umr_bitfield_default }, + { "BASE_ADDR", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS2[] = { + { "CS_ENABLE", 0, 0, &umr_bitfield_default }, + { "BASE_ADDR", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS3[] = { + { "CS_ENABLE", 0, 0, &umr_bitfield_default }, + { "BASE_ADDR", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_ADDRDEC0_ADDR_MASK_CS01[] = { + { "ADDR_MASK", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_ADDRDEC0_ADDR_MASK_CS23[] = { + { "ADDR_MASK", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS01[] = { + { "ADDR_MASK", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS23[] = { + { "ADDR_MASK", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_ADDRDEC0_ADDR_CFG_CS01[] = { + { "NUM_BANK_GROUPS", 2, 3, &umr_bitfield_default }, + { "NUM_RM", 4, 5, &umr_bitfield_default }, + { "NUM_ROW_LO", 8, 11, &umr_bitfield_default }, + { "NUM_ROW_HI", 12, 15, &umr_bitfield_default }, + { "NUM_COL", 16, 19, &umr_bitfield_default }, + { "NUM_BANKS", 20, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_ADDRDEC0_ADDR_CFG_CS23[] = { + { "NUM_BANK_GROUPS", 2, 3, &umr_bitfield_default }, + { "NUM_RM", 4, 5, &umr_bitfield_default }, + { "NUM_ROW_LO", 8, 11, &umr_bitfield_default }, + { "NUM_ROW_HI", 12, 15, &umr_bitfield_default }, + { "NUM_COL", 16, 19, &umr_bitfield_default }, + { "NUM_BANKS", 20, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_ADDRDEC0_ADDR_SEL_CS01[] = { + { "BANK0", 0, 3, &umr_bitfield_default }, + { "BANK1", 4, 7, &umr_bitfield_default }, + { "BANK2", 8, 11, &umr_bitfield_default }, + { "BANK3", 12, 15, &umr_bitfield_default }, + { "BANK4", 16, 19, &umr_bitfield_default }, + { "ROW_LO", 24, 27, &umr_bitfield_default }, + { "ROW_HI", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_ADDRDEC0_ADDR_SEL_CS23[] = { + { "BANK0", 0, 3, &umr_bitfield_default }, + { "BANK1", 4, 7, &umr_bitfield_default }, + { "BANK2", 8, 11, &umr_bitfield_default }, + { "BANK3", 12, 15, &umr_bitfield_default }, + { "BANK4", 16, 19, &umr_bitfield_default }, + { "ROW_LO", 24, 27, &umr_bitfield_default }, + { "ROW_HI", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_ADDRDEC0_COL_SEL_LO_CS01[] = { + { "COL0", 0, 3, &umr_bitfield_default }, + { "COL1", 4, 7, &umr_bitfield_default }, + { "COL2", 8, 11, &umr_bitfield_default }, + { "COL3", 12, 15, &umr_bitfield_default }, + { "COL4", 16, 19, &umr_bitfield_default }, + { "COL5", 20, 23, &umr_bitfield_default }, + { "COL6", 24, 27, &umr_bitfield_default }, + { "COL7", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_ADDRDEC0_COL_SEL_LO_CS23[] = { + { "COL0", 0, 3, &umr_bitfield_default }, + { "COL1", 4, 7, &umr_bitfield_default }, + { "COL2", 8, 11, &umr_bitfield_default }, + { "COL3", 12, 15, &umr_bitfield_default }, + { "COL4", 16, 19, &umr_bitfield_default }, + { "COL5", 20, 23, &umr_bitfield_default }, + { "COL6", 24, 27, &umr_bitfield_default }, + { "COL7", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_ADDRDEC0_COL_SEL_HI_CS01[] = { + { "COL8", 0, 3, &umr_bitfield_default }, + { "COL9", 4, 7, &umr_bitfield_default }, + { "COL10", 8, 11, &umr_bitfield_default }, + { "COL11", 12, 15, &umr_bitfield_default }, + { "COL12", 16, 19, &umr_bitfield_default }, + { "COL13", 20, 23, &umr_bitfield_default }, + { "COL14", 24, 27, &umr_bitfield_default }, + { "COL15", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_ADDRDEC0_COL_SEL_HI_CS23[] = { + { "COL8", 0, 3, &umr_bitfield_default }, + { "COL9", 4, 7, &umr_bitfield_default }, + { "COL10", 8, 11, &umr_bitfield_default }, + { "COL11", 12, 15, &umr_bitfield_default }, + { "COL12", 16, 19, &umr_bitfield_default }, + { "COL13", 20, 23, &umr_bitfield_default }, + { "COL14", 24, 27, &umr_bitfield_default }, + { "COL15", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_ADDRDEC0_RM_SEL_CS01[] = { + { "RM0", 0, 3, &umr_bitfield_default }, + { "RM1", 4, 7, &umr_bitfield_default }, + { "RM2", 8, 11, &umr_bitfield_default }, + { "CHAN_BIT", 12, 15, &umr_bitfield_default }, + { "INVERT_ROW_MSBS_EVEN", 16, 17, &umr_bitfield_default }, + { "INVERT_ROW_MSBS_ODD", 18, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_ADDRDEC0_RM_SEL_CS23[] = { + { "RM0", 0, 3, &umr_bitfield_default }, + { "RM1", 4, 7, &umr_bitfield_default }, + { "RM2", 8, 11, &umr_bitfield_default }, + { "CHAN_BIT", 12, 15, &umr_bitfield_default }, + { "INVERT_ROW_MSBS_EVEN", 16, 17, &umr_bitfield_default }, + { "INVERT_ROW_MSBS_ODD", 18, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_ADDRDEC0_RM_SEL_SECCS01[] = { + { "RM0", 0, 3, &umr_bitfield_default }, + { "RM1", 4, 7, &umr_bitfield_default }, + { "RM2", 8, 11, &umr_bitfield_default }, + { "CHAN_BIT", 12, 15, &umr_bitfield_default }, + { "INVERT_ROW_MSBS_EVEN", 16, 17, &umr_bitfield_default }, + { "INVERT_ROW_MSBS_ODD", 18, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_ADDRDEC0_RM_SEL_SECCS23[] = { + { "RM0", 0, 3, &umr_bitfield_default }, + { "RM1", 4, 7, &umr_bitfield_default }, + { "RM2", 8, 11, &umr_bitfield_default }, + { "CHAN_BIT", 12, 15, &umr_bitfield_default }, + { "INVERT_ROW_MSBS_EVEN", 16, 17, &umr_bitfield_default }, + { "INVERT_ROW_MSBS_ODD", 18, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_ADDRDEC1_BASE_ADDR_CS0[] = { + { "CS_ENABLE", 0, 0, &umr_bitfield_default }, + { "BASE_ADDR", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_ADDRDEC1_BASE_ADDR_CS1[] = { + { "CS_ENABLE", 0, 0, &umr_bitfield_default }, + { "BASE_ADDR", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_ADDRDEC1_BASE_ADDR_CS2[] = { + { "CS_ENABLE", 0, 0, &umr_bitfield_default }, + { "BASE_ADDR", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_ADDRDEC1_BASE_ADDR_CS3[] = { + { "CS_ENABLE", 0, 0, &umr_bitfield_default }, + { "BASE_ADDR", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS0[] = { + { "CS_ENABLE", 0, 0, &umr_bitfield_default }, + { "BASE_ADDR", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS1[] = { + { "CS_ENABLE", 0, 0, &umr_bitfield_default }, + { "BASE_ADDR", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS2[] = { + { "CS_ENABLE", 0, 0, &umr_bitfield_default }, + { "BASE_ADDR", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS3[] = { + { "CS_ENABLE", 0, 0, &umr_bitfield_default }, + { "BASE_ADDR", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_ADDRDEC1_ADDR_MASK_CS01[] = { + { "ADDR_MASK", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_ADDRDEC1_ADDR_MASK_CS23[] = { + { "ADDR_MASK", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS01[] = { + { "ADDR_MASK", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS23[] = { + { "ADDR_MASK", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_ADDRDEC1_ADDR_CFG_CS01[] = { + { "NUM_BANK_GROUPS", 2, 3, &umr_bitfield_default }, + { "NUM_RM", 4, 5, &umr_bitfield_default }, + { "NUM_ROW_LO", 8, 11, &umr_bitfield_default }, + { "NUM_ROW_HI", 12, 15, &umr_bitfield_default }, + { "NUM_COL", 16, 19, &umr_bitfield_default }, + { "NUM_BANKS", 20, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_ADDRDEC1_ADDR_CFG_CS23[] = { + { "NUM_BANK_GROUPS", 2, 3, &umr_bitfield_default }, + { "NUM_RM", 4, 5, &umr_bitfield_default }, + { "NUM_ROW_LO", 8, 11, &umr_bitfield_default }, + { "NUM_ROW_HI", 12, 15, &umr_bitfield_default }, + { "NUM_COL", 16, 19, &umr_bitfield_default }, + { "NUM_BANKS", 20, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_ADDRDEC1_ADDR_SEL_CS01[] = { + { "BANK0", 0, 3, &umr_bitfield_default }, + { "BANK1", 4, 7, &umr_bitfield_default }, + { "BANK2", 8, 11, &umr_bitfield_default }, + { "BANK3", 12, 15, &umr_bitfield_default }, + { "BANK4", 16, 19, &umr_bitfield_default }, + { "ROW_LO", 24, 27, &umr_bitfield_default }, + { "ROW_HI", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_ADDRDEC1_ADDR_SEL_CS23[] = { + { "BANK0", 0, 3, &umr_bitfield_default }, + { "BANK1", 4, 7, &umr_bitfield_default }, + { "BANK2", 8, 11, &umr_bitfield_default }, + { "BANK3", 12, 15, &umr_bitfield_default }, + { "BANK4", 16, 19, &umr_bitfield_default }, + { "ROW_LO", 24, 27, &umr_bitfield_default }, + { "ROW_HI", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_ADDRDEC1_COL_SEL_LO_CS01[] = { + { "COL0", 0, 3, &umr_bitfield_default }, + { "COL1", 4, 7, &umr_bitfield_default }, + { "COL2", 8, 11, &umr_bitfield_default }, + { "COL3", 12, 15, &umr_bitfield_default }, + { "COL4", 16, 19, &umr_bitfield_default }, + { "COL5", 20, 23, &umr_bitfield_default }, + { "COL6", 24, 27, &umr_bitfield_default }, + { "COL7", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_ADDRDEC1_COL_SEL_LO_CS23[] = { + { "COL0", 0, 3, &umr_bitfield_default }, + { "COL1", 4, 7, &umr_bitfield_default }, + { "COL2", 8, 11, &umr_bitfield_default }, + { "COL3", 12, 15, &umr_bitfield_default }, + { "COL4", 16, 19, &umr_bitfield_default }, + { "COL5", 20, 23, &umr_bitfield_default }, + { "COL6", 24, 27, &umr_bitfield_default }, + { "COL7", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_ADDRDEC1_COL_SEL_HI_CS01[] = { + { "COL8", 0, 3, &umr_bitfield_default }, + { "COL9", 4, 7, &umr_bitfield_default }, + { "COL10", 8, 11, &umr_bitfield_default }, + { "COL11", 12, 15, &umr_bitfield_default }, + { "COL12", 16, 19, &umr_bitfield_default }, + { "COL13", 20, 23, &umr_bitfield_default }, + { "COL14", 24, 27, &umr_bitfield_default }, + { "COL15", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_ADDRDEC1_COL_SEL_HI_CS23[] = { + { "COL8", 0, 3, &umr_bitfield_default }, + { "COL9", 4, 7, &umr_bitfield_default }, + { "COL10", 8, 11, &umr_bitfield_default }, + { "COL11", 12, 15, &umr_bitfield_default }, + { "COL12", 16, 19, &umr_bitfield_default }, + { "COL13", 20, 23, &umr_bitfield_default }, + { "COL14", 24, 27, &umr_bitfield_default }, + { "COL15", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_ADDRDEC1_RM_SEL_CS01[] = { + { "RM0", 0, 3, &umr_bitfield_default }, + { "RM1", 4, 7, &umr_bitfield_default }, + { "RM2", 8, 11, &umr_bitfield_default }, + { "CHAN_BIT", 12, 15, &umr_bitfield_default }, + { "INVERT_ROW_MSBS_EVEN", 16, 17, &umr_bitfield_default }, + { "INVERT_ROW_MSBS_ODD", 18, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_ADDRDEC1_RM_SEL_CS23[] = { + { "RM0", 0, 3, &umr_bitfield_default }, + { "RM1", 4, 7, &umr_bitfield_default }, + { "RM2", 8, 11, &umr_bitfield_default }, + { "CHAN_BIT", 12, 15, &umr_bitfield_default }, + { "INVERT_ROW_MSBS_EVEN", 16, 17, &umr_bitfield_default }, + { "INVERT_ROW_MSBS_ODD", 18, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_ADDRDEC1_RM_SEL_SECCS01[] = { + { "RM0", 0, 3, &umr_bitfield_default }, + { "RM1", 4, 7, &umr_bitfield_default }, + { "RM2", 8, 11, &umr_bitfield_default }, + { "CHAN_BIT", 12, 15, &umr_bitfield_default }, + { "INVERT_ROW_MSBS_EVEN", 16, 17, &umr_bitfield_default }, + { "INVERT_ROW_MSBS_ODD", 18, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_ADDRDEC1_RM_SEL_SECCS23[] = { + { "RM0", 0, 3, &umr_bitfield_default }, + { "RM1", 4, 7, &umr_bitfield_default }, + { "RM2", 8, 11, &umr_bitfield_default }, + { "CHAN_BIT", 12, 15, &umr_bitfield_default }, + { "INVERT_ROW_MSBS_EVEN", 16, 17, &umr_bitfield_default }, + { "INVERT_ROW_MSBS_ODD", 18, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_IO_RD_CLI2GRP_MAP0[] = { + { "CID0_GROUP", 0, 1, &umr_bitfield_default }, + { "CID1_GROUP", 2, 3, &umr_bitfield_default }, + { "CID2_GROUP", 4, 5, &umr_bitfield_default }, + { "CID3_GROUP", 6, 7, &umr_bitfield_default }, + { "CID4_GROUP", 8, 9, &umr_bitfield_default }, + { "CID5_GROUP", 10, 11, &umr_bitfield_default }, + { "CID6_GROUP", 12, 13, &umr_bitfield_default }, + { "CID7_GROUP", 14, 15, &umr_bitfield_default }, + { "CID8_GROUP", 16, 17, &umr_bitfield_default }, + { "CID9_GROUP", 18, 19, &umr_bitfield_default }, + { "CID10_GROUP", 20, 21, &umr_bitfield_default }, + { "CID11_GROUP", 22, 23, &umr_bitfield_default }, + { "CID12_GROUP", 24, 25, &umr_bitfield_default }, + { "CID13_GROUP", 26, 27, &umr_bitfield_default }, + { "CID14_GROUP", 28, 29, &umr_bitfield_default }, + { "CID15_GROUP", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_IO_RD_CLI2GRP_MAP1[] = { + { "CID16_GROUP", 0, 1, &umr_bitfield_default }, + { "CID17_GROUP", 2, 3, &umr_bitfield_default }, + { "CID18_GROUP", 4, 5, &umr_bitfield_default }, + { "CID19_GROUP", 6, 7, &umr_bitfield_default }, + { "CID20_GROUP", 8, 9, &umr_bitfield_default }, + { "CID21_GROUP", 10, 11, &umr_bitfield_default }, + { "CID22_GROUP", 12, 13, &umr_bitfield_default }, + { "CID23_GROUP", 14, 15, &umr_bitfield_default }, + { "CID24_GROUP", 16, 17, &umr_bitfield_default }, + { "CID25_GROUP", 18, 19, &umr_bitfield_default }, + { "CID26_GROUP", 20, 21, &umr_bitfield_default }, + { "CID27_GROUP", 22, 23, &umr_bitfield_default }, + { "CID28_GROUP", 24, 25, &umr_bitfield_default }, + { "CID29_GROUP", 26, 27, &umr_bitfield_default }, + { "CID30_GROUP", 28, 29, &umr_bitfield_default }, + { "CID31_GROUP", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_IO_WR_CLI2GRP_MAP0[] = { + { "CID0_GROUP", 0, 1, &umr_bitfield_default }, + { "CID1_GROUP", 2, 3, &umr_bitfield_default }, + { "CID2_GROUP", 4, 5, &umr_bitfield_default }, + { "CID3_GROUP", 6, 7, &umr_bitfield_default }, + { "CID4_GROUP", 8, 9, &umr_bitfield_default }, + { "CID5_GROUP", 10, 11, &umr_bitfield_default }, + { "CID6_GROUP", 12, 13, &umr_bitfield_default }, + { "CID7_GROUP", 14, 15, &umr_bitfield_default }, + { "CID8_GROUP", 16, 17, &umr_bitfield_default }, + { "CID9_GROUP", 18, 19, &umr_bitfield_default }, + { "CID10_GROUP", 20, 21, &umr_bitfield_default }, + { "CID11_GROUP", 22, 23, &umr_bitfield_default }, + { "CID12_GROUP", 24, 25, &umr_bitfield_default }, + { "CID13_GROUP", 26, 27, &umr_bitfield_default }, + { "CID14_GROUP", 28, 29, &umr_bitfield_default }, + { "CID15_GROUP", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_IO_WR_CLI2GRP_MAP1[] = { + { "CID16_GROUP", 0, 1, &umr_bitfield_default }, + { "CID17_GROUP", 2, 3, &umr_bitfield_default }, + { "CID18_GROUP", 4, 5, &umr_bitfield_default }, + { "CID19_GROUP", 6, 7, &umr_bitfield_default }, + { "CID20_GROUP", 8, 9, &umr_bitfield_default }, + { "CID21_GROUP", 10, 11, &umr_bitfield_default }, + { "CID22_GROUP", 12, 13, &umr_bitfield_default }, + { "CID23_GROUP", 14, 15, &umr_bitfield_default }, + { "CID24_GROUP", 16, 17, &umr_bitfield_default }, + { "CID25_GROUP", 18, 19, &umr_bitfield_default }, + { "CID26_GROUP", 20, 21, &umr_bitfield_default }, + { "CID27_GROUP", 22, 23, &umr_bitfield_default }, + { "CID28_GROUP", 24, 25, &umr_bitfield_default }, + { "CID29_GROUP", 26, 27, &umr_bitfield_default }, + { "CID30_GROUP", 28, 29, &umr_bitfield_default }, + { "CID31_GROUP", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_IO_RD_COMBINE_FLUSH[] = { + { "GROUP0_TIMER", 0, 3, &umr_bitfield_default }, + { "GROUP1_TIMER", 4, 7, &umr_bitfield_default }, + { "GROUP2_TIMER", 8, 11, &umr_bitfield_default }, + { "GROUP3_TIMER", 12, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_IO_WR_COMBINE_FLUSH[] = { + { "GROUP0_TIMER", 0, 3, &umr_bitfield_default }, + { "GROUP1_TIMER", 4, 7, &umr_bitfield_default }, + { "GROUP2_TIMER", 8, 11, &umr_bitfield_default }, + { "GROUP3_TIMER", 12, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_IO_GROUP_BURST[] = { + { "RD_LIMIT_LO", 0, 7, &umr_bitfield_default }, + { "RD_LIMIT_HI", 8, 15, &umr_bitfield_default }, + { "WR_LIMIT_LO", 16, 23, &umr_bitfield_default }, + { "WR_LIMIT_HI", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_IO_RD_PRI_AGE[] = { + { "GROUP0_AGING_RATE", 0, 2, &umr_bitfield_default }, + { "GROUP1_AGING_RATE", 3, 5, &umr_bitfield_default }, + { "GROUP2_AGING_RATE", 6, 8, &umr_bitfield_default }, + { "GROUP3_AGING_RATE", 9, 11, &umr_bitfield_default }, + { "GROUP0_AGE_COEFFICIENT", 12, 14, &umr_bitfield_default }, + { "GROUP1_AGE_COEFFICIENT", 15, 17, &umr_bitfield_default }, + { "GROUP2_AGE_COEFFICIENT", 18, 20, &umr_bitfield_default }, + { "GROUP3_AGE_COEFFICIENT", 21, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_IO_WR_PRI_AGE[] = { + { "GROUP0_AGING_RATE", 0, 2, &umr_bitfield_default }, + { "GROUP1_AGING_RATE", 3, 5, &umr_bitfield_default }, + { "GROUP2_AGING_RATE", 6, 8, &umr_bitfield_default }, + { "GROUP3_AGING_RATE", 9, 11, &umr_bitfield_default }, + { "GROUP0_AGE_COEFFICIENT", 12, 14, &umr_bitfield_default }, + { "GROUP1_AGE_COEFFICIENT", 15, 17, &umr_bitfield_default }, + { "GROUP2_AGE_COEFFICIENT", 18, 20, &umr_bitfield_default }, + { "GROUP3_AGE_COEFFICIENT", 21, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_IO_RD_PRI_QUEUING[] = { + { "GROUP0_QUEUING_COEFFICIENT", 0, 2, &umr_bitfield_default }, + { "GROUP1_QUEUING_COEFFICIENT", 3, 5, &umr_bitfield_default }, + { "GROUP2_QUEUING_COEFFICIENT", 6, 8, &umr_bitfield_default }, + { "GROUP3_QUEUING_COEFFICIENT", 9, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_IO_WR_PRI_QUEUING[] = { + { "GROUP0_QUEUING_COEFFICIENT", 0, 2, &umr_bitfield_default }, + { "GROUP1_QUEUING_COEFFICIENT", 3, 5, &umr_bitfield_default }, + { "GROUP2_QUEUING_COEFFICIENT", 6, 8, &umr_bitfield_default }, + { "GROUP3_QUEUING_COEFFICIENT", 9, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_IO_RD_PRI_FIXED[] = { + { "GROUP0_FIXED_COEFFICIENT", 0, 2, &umr_bitfield_default }, + { "GROUP1_FIXED_COEFFICIENT", 3, 5, &umr_bitfield_default }, + { "GROUP2_FIXED_COEFFICIENT", 6, 8, &umr_bitfield_default }, + { "GROUP3_FIXED_COEFFICIENT", 9, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_IO_WR_PRI_FIXED[] = { + { "GROUP0_FIXED_COEFFICIENT", 0, 2, &umr_bitfield_default }, + { "GROUP1_FIXED_COEFFICIENT", 3, 5, &umr_bitfield_default }, + { "GROUP2_FIXED_COEFFICIENT", 6, 8, &umr_bitfield_default }, + { "GROUP3_FIXED_COEFFICIENT", 9, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_IO_RD_PRI_URGENCY[] = { + { "GROUP0_URGENCY_COEFFICIENT", 0, 2, &umr_bitfield_default }, + { "GROUP1_URGENCY_COEFFICIENT", 3, 5, &umr_bitfield_default }, + { "GROUP2_URGENCY_COEFFICIENT", 6, 8, &umr_bitfield_default }, + { "GROUP3_URGENCY_COEFFICIENT", 9, 11, &umr_bitfield_default }, + { "GROUP0_URGENCY_MODE", 12, 12, &umr_bitfield_default }, + { "GROUP1_URGENCY_MODE", 13, 13, &umr_bitfield_default }, + { "GROUP2_URGENCY_MODE", 14, 14, &umr_bitfield_default }, + { "GROUP3_URGENCY_MODE", 15, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_IO_WR_PRI_URGENCY[] = { + { "GROUP0_URGENCY_COEFFICIENT", 0, 2, &umr_bitfield_default }, + { "GROUP1_URGENCY_COEFFICIENT", 3, 5, &umr_bitfield_default }, + { "GROUP2_URGENCY_COEFFICIENT", 6, 8, &umr_bitfield_default }, + { "GROUP3_URGENCY_COEFFICIENT", 9, 11, &umr_bitfield_default }, + { "GROUP0_URGENCY_MODE", 12, 12, &umr_bitfield_default }, + { "GROUP1_URGENCY_MODE", 13, 13, &umr_bitfield_default }, + { "GROUP2_URGENCY_MODE", 14, 14, &umr_bitfield_default }, + { "GROUP3_URGENCY_MODE", 15, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_IO_RD_PRI_URGENCY_MASK[] = { + { "CID0_MASK", 0, 0, &umr_bitfield_default }, + { "CID1_MASK", 1, 1, &umr_bitfield_default }, + { "CID2_MASK", 2, 2, &umr_bitfield_default }, + { "CID3_MASK", 3, 3, &umr_bitfield_default }, + { "CID4_MASK", 4, 4, &umr_bitfield_default }, + { "CID5_MASK", 5, 5, &umr_bitfield_default }, + { "CID6_MASK", 6, 6, &umr_bitfield_default }, + { "CID7_MASK", 7, 7, &umr_bitfield_default }, + { "CID8_MASK", 8, 8, &umr_bitfield_default }, + { "CID9_MASK", 9, 9, &umr_bitfield_default }, + { "CID10_MASK", 10, 10, &umr_bitfield_default }, + { "CID11_MASK", 11, 11, &umr_bitfield_default }, + { "CID12_MASK", 12, 12, &umr_bitfield_default }, + { "CID13_MASK", 13, 13, &umr_bitfield_default }, + { "CID14_MASK", 14, 14, &umr_bitfield_default }, + { "CID15_MASK", 15, 15, &umr_bitfield_default }, + { "CID16_MASK", 16, 16, &umr_bitfield_default }, + { "CID17_MASK", 17, 17, &umr_bitfield_default }, + { "CID18_MASK", 18, 18, &umr_bitfield_default }, + { "CID19_MASK", 19, 19, &umr_bitfield_default }, + { "CID20_MASK", 20, 20, &umr_bitfield_default }, + { "CID21_MASK", 21, 21, &umr_bitfield_default }, + { "CID22_MASK", 22, 22, &umr_bitfield_default }, + { "CID23_MASK", 23, 23, &umr_bitfield_default }, + { "CID24_MASK", 24, 24, &umr_bitfield_default }, + { "CID25_MASK", 25, 25, &umr_bitfield_default }, + { "CID26_MASK", 26, 26, &umr_bitfield_default }, + { "CID27_MASK", 27, 27, &umr_bitfield_default }, + { "CID28_MASK", 28, 28, &umr_bitfield_default }, + { "CID29_MASK", 29, 29, &umr_bitfield_default }, + { "CID30_MASK", 30, 30, &umr_bitfield_default }, + { "CID31_MASK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_IO_WR_PRI_URGENCY_MASK[] = { + { "CID0_MASK", 0, 0, &umr_bitfield_default }, + { "CID1_MASK", 1, 1, &umr_bitfield_default }, + { "CID2_MASK", 2, 2, &umr_bitfield_default }, + { "CID3_MASK", 3, 3, &umr_bitfield_default }, + { "CID4_MASK", 4, 4, &umr_bitfield_default }, + { "CID5_MASK", 5, 5, &umr_bitfield_default }, + { "CID6_MASK", 6, 6, &umr_bitfield_default }, + { "CID7_MASK", 7, 7, &umr_bitfield_default }, + { "CID8_MASK", 8, 8, &umr_bitfield_default }, + { "CID9_MASK", 9, 9, &umr_bitfield_default }, + { "CID10_MASK", 10, 10, &umr_bitfield_default }, + { "CID11_MASK", 11, 11, &umr_bitfield_default }, + { "CID12_MASK", 12, 12, &umr_bitfield_default }, + { "CID13_MASK", 13, 13, &umr_bitfield_default }, + { "CID14_MASK", 14, 14, &umr_bitfield_default }, + { "CID15_MASK", 15, 15, &umr_bitfield_default }, + { "CID16_MASK", 16, 16, &umr_bitfield_default }, + { "CID17_MASK", 17, 17, &umr_bitfield_default }, + { "CID18_MASK", 18, 18, &umr_bitfield_default }, + { "CID19_MASK", 19, 19, &umr_bitfield_default }, + { "CID20_MASK", 20, 20, &umr_bitfield_default }, + { "CID21_MASK", 21, 21, &umr_bitfield_default }, + { "CID22_MASK", 22, 22, &umr_bitfield_default }, + { "CID23_MASK", 23, 23, &umr_bitfield_default }, + { "CID24_MASK", 24, 24, &umr_bitfield_default }, + { "CID25_MASK", 25, 25, &umr_bitfield_default }, + { "CID26_MASK", 26, 26, &umr_bitfield_default }, + { "CID27_MASK", 27, 27, &umr_bitfield_default }, + { "CID28_MASK", 28, 28, &umr_bitfield_default }, + { "CID29_MASK", 29, 29, &umr_bitfield_default }, + { "CID30_MASK", 30, 30, &umr_bitfield_default }, + { "CID31_MASK", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_IO_RD_PRI_QUANT_PRI1[] = { + { "GROUP0_THRESHOLD", 0, 7, &umr_bitfield_default }, + { "GROUP1_THRESHOLD", 8, 15, &umr_bitfield_default }, + { "GROUP2_THRESHOLD", 16, 23, &umr_bitfield_default }, + { "GROUP3_THRESHOLD", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_IO_RD_PRI_QUANT_PRI2[] = { + { "GROUP0_THRESHOLD", 0, 7, &umr_bitfield_default }, + { "GROUP1_THRESHOLD", 8, 15, &umr_bitfield_default }, + { "GROUP2_THRESHOLD", 16, 23, &umr_bitfield_default }, + { "GROUP3_THRESHOLD", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_IO_RD_PRI_QUANT_PRI3[] = { + { "GROUP0_THRESHOLD", 0, 7, &umr_bitfield_default }, + { "GROUP1_THRESHOLD", 8, 15, &umr_bitfield_default }, + { "GROUP2_THRESHOLD", 16, 23, &umr_bitfield_default }, + { "GROUP3_THRESHOLD", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_IO_WR_PRI_QUANT_PRI1[] = { + { "GROUP0_THRESHOLD", 0, 7, &umr_bitfield_default }, + { "GROUP1_THRESHOLD", 8, 15, &umr_bitfield_default }, + { "GROUP2_THRESHOLD", 16, 23, &umr_bitfield_default }, + { "GROUP3_THRESHOLD", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_IO_WR_PRI_QUANT_PRI2[] = { + { "GROUP0_THRESHOLD", 0, 7, &umr_bitfield_default }, + { "GROUP1_THRESHOLD", 8, 15, &umr_bitfield_default }, + { "GROUP2_THRESHOLD", 16, 23, &umr_bitfield_default }, + { "GROUP3_THRESHOLD", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_IO_WR_PRI_QUANT_PRI3[] = { + { "GROUP0_THRESHOLD", 0, 7, &umr_bitfield_default }, + { "GROUP1_THRESHOLD", 8, 15, &umr_bitfield_default }, + { "GROUP2_THRESHOLD", 16, 23, &umr_bitfield_default }, + { "GROUP3_THRESHOLD", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_SDP_ARB_DRAM[] = { + { "RDWR_BURST_LIMIT_CYCL", 0, 6, &umr_bitfield_default }, + { "RDWR_BURST_LIMIT_DATA", 8, 14, &umr_bitfield_default }, + { "EARLY_SW2RD_ON_PRI", 16, 16, &umr_bitfield_default }, + { "EARLY_SW2WR_ON_PRI", 17, 17, &umr_bitfield_default }, + { "EARLY_SW2RD_ON_RES", 18, 18, &umr_bitfield_default }, + { "EARLY_SW2WR_ON_RES", 19, 19, &umr_bitfield_default }, + { "EOB_ON_EXPIRE", 20, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_SDP_ARB_FINAL[] = { + { "DRAM_BURST_LIMIT", 0, 4, &umr_bitfield_default }, + { "GMI_BURST_LIMIT", 5, 9, &umr_bitfield_default }, + { "IO_BURST_LIMIT", 10, 14, &umr_bitfield_default }, + { "BURST_LIMIT_MULTIPLIER", 15, 16, &umr_bitfield_default }, + { "RDONLY_VC0", 17, 17, &umr_bitfield_default }, + { "RDONLY_VC1", 18, 18, &umr_bitfield_default }, + { "RDONLY_VC2", 19, 19, &umr_bitfield_default }, + { "RDONLY_VC3", 20, 20, &umr_bitfield_default }, + { "RDONLY_VC4", 21, 21, &umr_bitfield_default }, + { "RDONLY_VC5", 22, 22, &umr_bitfield_default }, + { "RDONLY_VC6", 23, 23, &umr_bitfield_default }, + { "RDONLY_VC7", 24, 24, &umr_bitfield_default }, + { "ERREVENT_ON_ERROR", 25, 25, &umr_bitfield_default }, + { "HALTREQ_ON_ERROR", 26, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_SDP_DRAM_PRIORITY[] = { + { "RD_GROUP0_PRIORITY", 0, 3, &umr_bitfield_default }, + { "RD_GROUP1_PRIORITY", 4, 7, &umr_bitfield_default }, + { "RD_GROUP2_PRIORITY", 8, 11, &umr_bitfield_default }, + { "RD_GROUP3_PRIORITY", 12, 15, &umr_bitfield_default }, + { "WR_GROUP0_PRIORITY", 16, 19, &umr_bitfield_default }, + { "WR_GROUP1_PRIORITY", 20, 23, &umr_bitfield_default }, + { "WR_GROUP2_PRIORITY", 24, 27, &umr_bitfield_default }, + { "WR_GROUP3_PRIORITY", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_SDP_IO_PRIORITY[] = { + { "RD_GROUP0_PRIORITY", 0, 3, &umr_bitfield_default }, + { "RD_GROUP1_PRIORITY", 4, 7, &umr_bitfield_default }, + { "RD_GROUP2_PRIORITY", 8, 11, &umr_bitfield_default }, + { "RD_GROUP3_PRIORITY", 12, 15, &umr_bitfield_default }, + { "WR_GROUP0_PRIORITY", 16, 19, &umr_bitfield_default }, + { "WR_GROUP1_PRIORITY", 20, 23, &umr_bitfield_default }, + { "WR_GROUP2_PRIORITY", 24, 27, &umr_bitfield_default }, + { "WR_GROUP3_PRIORITY", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_SDP_CREDITS[] = { + { "TAG_LIMIT", 0, 7, &umr_bitfield_default }, + { "WR_RESP_CREDITS", 8, 14, &umr_bitfield_default }, + { "RD_RESP_CREDITS", 16, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_SDP_TAG_RESERVE0[] = { + { "VC0", 0, 7, &umr_bitfield_default }, + { "VC1", 8, 15, &umr_bitfield_default }, + { "VC2", 16, 23, &umr_bitfield_default }, + { "VC3", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_SDP_TAG_RESERVE1[] = { + { "VC4", 0, 7, &umr_bitfield_default }, + { "VC5", 8, 15, &umr_bitfield_default }, + { "VC6", 16, 23, &umr_bitfield_default }, + { "VC7", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_SDP_VCC_RESERVE0[] = { + { "VC0_CREDITS", 0, 5, &umr_bitfield_default }, + { "VC1_CREDITS", 6, 11, &umr_bitfield_default }, + { "VC2_CREDITS", 12, 17, &umr_bitfield_default }, + { "VC3_CREDITS", 18, 23, &umr_bitfield_default }, + { "VC4_CREDITS", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_SDP_VCC_RESERVE1[] = { + { "VC5_CREDITS", 0, 5, &umr_bitfield_default }, + { "VC6_CREDITS", 6, 11, &umr_bitfield_default }, + { "VC7_CREDITS", 12, 17, &umr_bitfield_default }, + { "DISTRIBUTE_POOL", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_SDP_VCD_RESERVE0[] = { + { "VC0_CREDITS", 0, 5, &umr_bitfield_default }, + { "VC1_CREDITS", 6, 11, &umr_bitfield_default }, + { "VC2_CREDITS", 12, 17, &umr_bitfield_default }, + { "VC3_CREDITS", 18, 23, &umr_bitfield_default }, + { "VC4_CREDITS", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_SDP_VCD_RESERVE1[] = { + { "VC5_CREDITS", 0, 5, &umr_bitfield_default }, + { "VC6_CREDITS", 6, 11, &umr_bitfield_default }, + { "VC7_CREDITS", 12, 17, &umr_bitfield_default }, + { "DISTRIBUTE_POOL", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_SDP_REQ_CNTL[] = { + { "REQ_PASS_PW_OVERRIDE_READ", 0, 0, &umr_bitfield_default }, + { "REQ_PASS_PW_OVERRIDE_WRITE", 1, 1, &umr_bitfield_default }, + { "REQ_PASS_PW_OVERRIDE_ATOMIC", 2, 2, &umr_bitfield_default }, + { "REQ_CHAIN_OVERRIDE_DRAM", 3, 3, &umr_bitfield_default }, + { "INNER_DOMAIN_MODE", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_MISC[] = { + { "RELATIVE_PRI_IN_DRAM_RD_ARB", 0, 0, &umr_bitfield_default }, + { "RELATIVE_PRI_IN_DRAM_WR_ARB", 1, 1, &umr_bitfield_default }, + { "RELATIVE_PRI_IN_GMI_RD_ARB", 2, 2, &umr_bitfield_default }, + { "RELATIVE_PRI_IN_GMI_WR_ARB", 3, 3, &umr_bitfield_default }, + { "RELATIVE_PRI_IN_IO_RD_ARB", 4, 4, &umr_bitfield_default }, + { "RELATIVE_PRI_IN_IO_WR_ARB", 5, 5, &umr_bitfield_default }, + { "RRET_SWAP_MODE", 6, 6, &umr_bitfield_default }, + { "EARLY_SDP_ORIGDATA", 7, 7, &umr_bitfield_default }, + { "LINKMGR_DYNAMIC_MODE", 8, 9, &umr_bitfield_default }, + { "LINKMGR_HALT_THRESHOLD", 10, 11, &umr_bitfield_default }, + { "LINKMGR_RECONNECT_DELAY", 12, 13, &umr_bitfield_default }, + { "LINKMGR_IDLE_THRESHOLD", 14, 18, &umr_bitfield_default }, + { "FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB", 19, 19, &umr_bitfield_default }, + { "FAVOUR_MIDCHAIN_CS_IN_GMI_ARB", 20, 20, &umr_bitfield_default }, + { "FAVOUR_LAST_CS_IN_DRAM_ARB", 21, 21, &umr_bitfield_default }, + { "FAVOUR_LAST_CS_IN_GMI_ARB", 22, 22, &umr_bitfield_default }, + { "SWITCH_CS_ON_W2R_IN_DRAM_ARB", 23, 23, &umr_bitfield_default }, + { "SWITCH_CS_ON_W2R_IN_GMI_ARB", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_LATENCY_SAMPLING[] = { + { "SAMPLER0_DRAM", 0, 0, &umr_bitfield_default }, + { "SAMPLER1_DRAM", 1, 1, &umr_bitfield_default }, + { "SAMPLER0_GMI", 2, 2, &umr_bitfield_default }, + { "SAMPLER1_GMI", 3, 3, &umr_bitfield_default }, + { "SAMPLER0_IO", 4, 4, &umr_bitfield_default }, + { "SAMPLER1_IO", 5, 5, &umr_bitfield_default }, + { "SAMPLER0_READ", 6, 6, &umr_bitfield_default }, + { "SAMPLER1_READ", 7, 7, &umr_bitfield_default }, + { "SAMPLER0_WRITE", 8, 8, &umr_bitfield_default }, + { "SAMPLER1_WRITE", 9, 9, &umr_bitfield_default }, + { "SAMPLER0_ATOMIC_RET", 10, 10, &umr_bitfield_default }, + { "SAMPLER1_ATOMIC_RET", 11, 11, &umr_bitfield_default }, + { "SAMPLER0_ATOMIC_NORET", 12, 12, &umr_bitfield_default }, + { "SAMPLER1_ATOMIC_NORET", 13, 13, &umr_bitfield_default }, + { "SAMPLER0_VC", 14, 21, &umr_bitfield_default }, + { "SAMPLER1_VC", 22, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_PERFCOUNTER_LO[] = { + { "COUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_PERFCOUNTER_HI[] = { + { "COUNTER_HI", 0, 15, &umr_bitfield_default }, + { "COMPARE_VALUE", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_PERFCOUNTER0_CFG[] = { + { "PERF_SEL", 0, 7, &umr_bitfield_default }, + { "PERF_SEL_END", 8, 15, &umr_bitfield_default }, + { "PERF_MODE", 24, 27, &umr_bitfield_default }, + { "ENABLE", 28, 28, &umr_bitfield_default }, + { "CLEAR", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_PERFCOUNTER1_CFG[] = { + { "PERF_SEL", 0, 7, &umr_bitfield_default }, + { "PERF_SEL_END", 8, 15, &umr_bitfield_default }, + { "PERF_MODE", 24, 27, &umr_bitfield_default }, + { "ENABLE", 28, 28, &umr_bitfield_default }, + { "CLEAR", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_PERFCOUNTER_RSLT_CNTL[] = { + { "PERF_COUNTER_SELECT", 0, 3, &umr_bitfield_default }, + { "START_TRIGGER", 8, 15, &umr_bitfield_default }, + { "STOP_TRIGGER", 16, 23, &umr_bitfield_default }, + { "ENABLE_ANY", 24, 24, &umr_bitfield_default }, + { "CLEAR_ALL", 25, 25, &umr_bitfield_default }, + { "STOP_ALL_ON_SATURATE", 26, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_EDC_CNT[] = { + { "DRAMRD_CMDMEM_SEC_COUNT", 0, 1, &umr_bitfield_default }, + { "DRAMRD_CMDMEM_DED_COUNT", 2, 3, &umr_bitfield_default }, + { "DRAMWR_CMDMEM_SEC_COUNT", 4, 5, &umr_bitfield_default }, + { "DRAMWR_CMDMEM_DED_COUNT", 6, 7, &umr_bitfield_default }, + { "DRAMWR_DATAMEM_SEC_COUNT", 8, 9, &umr_bitfield_default }, + { "DRAMWR_DATAMEM_DED_COUNT", 10, 11, &umr_bitfield_default }, + { "RRET_TAGMEM_SEC_COUNT", 12, 13, &umr_bitfield_default }, + { "RRET_TAGMEM_DED_COUNT", 14, 15, &umr_bitfield_default }, + { "WRET_TAGMEM_SEC_COUNT", 16, 17, &umr_bitfield_default }, + { "WRET_TAGMEM_DED_COUNT", 18, 19, &umr_bitfield_default }, + { "DRAMRD_PAGEMEM_SED_COUNT", 20, 21, &umr_bitfield_default }, + { "DRAMWR_PAGEMEM_SED_COUNT", 22, 23, &umr_bitfield_default }, + { "IORD_CMDMEM_SED_COUNT", 24, 25, &umr_bitfield_default }, + { "IOWR_CMDMEM_SED_COUNT", 26, 27, &umr_bitfield_default }, + { "IOWR_DATAMEM_SED_COUNT", 28, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_EDC_CNT2[] = { + { "GMIRD_CMDMEM_SEC_COUNT", 0, 1, &umr_bitfield_default }, + { "GMIRD_CMDMEM_DED_COUNT", 2, 3, &umr_bitfield_default }, + { "GMIWR_CMDMEM_SEC_COUNT", 4, 5, &umr_bitfield_default }, + { "GMIWR_CMDMEM_DED_COUNT", 6, 7, &umr_bitfield_default }, + { "GMIWR_DATAMEM_SEC_COUNT", 8, 9, &umr_bitfield_default }, + { "GMIWR_DATAMEM_DED_COUNT", 10, 11, &umr_bitfield_default }, + { "GMIRD_PAGEMEM_SED_COUNT", 12, 13, &umr_bitfield_default }, + { "GMIWR_PAGEMEM_SED_COUNT", 14, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_DSM_CNTL[] = { + { "DRAMRD_CMDMEM_DSM_IRRITATOR_DATA", 0, 1, &umr_bitfield_default }, + { "DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE", 2, 2, &umr_bitfield_default }, + { "DRAMWR_CMDMEM_DSM_IRRITATOR_DATA", 3, 4, &umr_bitfield_default }, + { "DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE", 5, 5, &umr_bitfield_default }, + { "DRAMWR_DATAMEM_DSM_IRRITATOR_DATA", 6, 7, &umr_bitfield_default }, + { "DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE", 8, 8, &umr_bitfield_default }, + { "RRET_TAGMEM_DSM_IRRITATOR_DATA", 9, 10, &umr_bitfield_default }, + { "RRET_TAGMEM_ENABLE_SINGLE_WRITE", 11, 11, &umr_bitfield_default }, + { "WRET_TAGMEM_DSM_IRRITATOR_DATA", 12, 13, &umr_bitfield_default }, + { "WRET_TAGMEM_ENABLE_SINGLE_WRITE", 14, 14, &umr_bitfield_default }, + { "GMIRD_CMDMEM_DSM_IRRITATOR_DATA", 15, 16, &umr_bitfield_default }, + { "GMIRD_CMDMEM_ENABLE_SINGLE_WRITE", 17, 17, &umr_bitfield_default }, + { "GMIWR_CMDMEM_DSM_IRRITATOR_DATA", 18, 19, &umr_bitfield_default }, + { "GMIWR_CMDMEM_ENABLE_SINGLE_WRITE", 20, 20, &umr_bitfield_default }, + { "GMIWR_DATAMEM_DSM_IRRITATOR_DATA", 21, 22, &umr_bitfield_default }, + { "GMIWR_DATAMEM_ENABLE_SINGLE_WRITE", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_DSM_CNTLA[] = { + { "DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA", 0, 1, &umr_bitfield_default }, + { "DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE", 2, 2, &umr_bitfield_default }, + { "DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA", 3, 4, &umr_bitfield_default }, + { "DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE", 5, 5, &umr_bitfield_default }, + { "IORD_CMDMEM_DSM_IRRITATOR_DATA", 6, 7, &umr_bitfield_default }, + { "IORD_CMDMEM_ENABLE_SINGLE_WRITE", 8, 8, &umr_bitfield_default }, + { "IOWR_CMDMEM_DSM_IRRITATOR_DATA", 9, 10, &umr_bitfield_default }, + { "IOWR_CMDMEM_ENABLE_SINGLE_WRITE", 11, 11, &umr_bitfield_default }, + { "IOWR_DATAMEM_DSM_IRRITATOR_DATA", 12, 13, &umr_bitfield_default }, + { "IOWR_DATAMEM_ENABLE_SINGLE_WRITE", 14, 14, &umr_bitfield_default }, + { "GMIRD_PAGEMEM_DSM_IRRITATOR_DATA", 15, 16, &umr_bitfield_default }, + { "GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE", 17, 17, &umr_bitfield_default }, + { "GMIWR_PAGEMEM_DSM_IRRITATOR_DATA", 18, 19, &umr_bitfield_default }, + { "GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE", 20, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_DSM_CNTL2[] = { + { "DRAMRD_CMDMEM_ENABLE_ERROR_INJECT", 0, 1, &umr_bitfield_default }, + { "DRAMRD_CMDMEM_SELECT_INJECT_DELAY", 2, 2, &umr_bitfield_default }, + { "DRAMWR_CMDMEM_ENABLE_ERROR_INJECT", 3, 4, &umr_bitfield_default }, + { "DRAMWR_CMDMEM_SELECT_INJECT_DELAY", 5, 5, &umr_bitfield_default }, + { "DRAMWR_DATAMEM_ENABLE_ERROR_INJECT", 6, 7, &umr_bitfield_default }, + { "DRAMWR_DATAMEM_SELECT_INJECT_DELAY", 8, 8, &umr_bitfield_default }, + { "RRET_TAGMEM_ENABLE_ERROR_INJECT", 9, 10, &umr_bitfield_default }, + { "RRET_TAGMEM_SELECT_INJECT_DELAY", 11, 11, &umr_bitfield_default }, + { "WRET_TAGMEM_ENABLE_ERROR_INJECT", 12, 13, &umr_bitfield_default }, + { "WRET_TAGMEM_SELECT_INJECT_DELAY", 14, 14, &umr_bitfield_default }, + { "GMIRD_CMDMEM_ENABLE_ERROR_INJECT", 15, 16, &umr_bitfield_default }, + { "GMIRD_CMDMEM_SELECT_INJECT_DELAY", 17, 17, &umr_bitfield_default }, + { "GMIWR_CMDMEM_ENABLE_ERROR_INJECT", 18, 19, &umr_bitfield_default }, + { "GMIWR_CMDMEM_SELECT_INJECT_DELAY", 20, 20, &umr_bitfield_default }, + { "GMIWR_DATAMEM_ENABLE_ERROR_INJECT", 21, 22, &umr_bitfield_default }, + { "GMIWR_DATAMEM_SELECT_INJECT_DELAY", 23, 23, &umr_bitfield_default }, + { "INJECT_DELAY", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_DSM_CNTL2A[] = { + { "DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT", 0, 1, &umr_bitfield_default }, + { "DRAMRD_PAGEMEM_SELECT_INJECT_DELAY", 2, 2, &umr_bitfield_default }, + { "DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT", 3, 4, &umr_bitfield_default }, + { "DRAMWR_PAGEMEM_SELECT_INJECT_DELAY", 5, 5, &umr_bitfield_default }, + { "IORD_CMDMEM_ENABLE_ERROR_INJECT", 6, 7, &umr_bitfield_default }, + { "IORD_CMDMEM_SELECT_INJECT_DELAY", 8, 8, &umr_bitfield_default }, + { "IOWR_CMDMEM_ENABLE_ERROR_INJECT", 9, 10, &umr_bitfield_default }, + { "IOWR_CMDMEM_SELECT_INJECT_DELAY", 11, 11, &umr_bitfield_default }, + { "IOWR_DATAMEM_ENABLE_ERROR_INJECT", 12, 13, &umr_bitfield_default }, + { "IOWR_DATAMEM_SELECT_INJECT_DELAY", 14, 14, &umr_bitfield_default }, + { "GMIRD_PAGEMEM_ENABLE_ERROR_INJECT", 15, 16, &umr_bitfield_default }, + { "GMIRD_PAGEMEM_SELECT_INJECT_DELAY", 17, 17, &umr_bitfield_default }, + { "GMIWR_PAGEMEM_ENABLE_ERROR_INJECT", 18, 19, &umr_bitfield_default }, + { "GMIWR_PAGEMEM_SELECT_INJECT_DELAY", 20, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_CGTT_CLK_CTRL[] = { + { "ON_DELAY", 0, 3, &umr_bitfield_default }, + { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE", 22, 22, &umr_bitfield_default }, + { "LS_OVERRIDE", 27, 27, &umr_bitfield_default }, + { "SOFT_OVERRIDE_WRITE", 28, 28, &umr_bitfield_default }, + { "SOFT_OVERRIDE_READ", 29, 29, &umr_bitfield_default }, + { "SOFT_OVERRIDE_RETURN", 30, 30, &umr_bitfield_default }, + { "SOFT_OVERRIDE_REGISTER", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_EDC_MODE[] = { + { "COUNT_FED_OUT", 16, 16, &umr_bitfield_default }, + { "GATE_FUE", 17, 17, &umr_bitfield_default }, + { "DED_MODE", 20, 21, &umr_bitfield_default }, + { "PROP_FED", 29, 29, &umr_bitfield_default }, + { "BYPASS", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_ERR_STATUS[] = { + { "SDP_RDRSP_STATUS", 0, 3, &umr_bitfield_default }, + { "SDP_WRRSP_STATUS", 4, 7, &umr_bitfield_default }, + { "SDP_RDRSP_DATAPARITY_ERROR", 8, 8, &umr_bitfield_default }, + { "CLEAR_ERROR_STATUS", 9, 9, &umr_bitfield_default }, + { "BUSY_ON_ERROR", 10, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMMEA1_MISC2[] = { + { "CSGROUP_SWAP_IN_DRAM_ARB", 0, 0, &umr_bitfield_default }, + { "CSGROUP_SWAP_IN_GMI_ARB", 1, 1, &umr_bitfield_default }, + { "CSGRP_BURST_LIMIT_DATA_DRAM", 2, 6, &umr_bitfield_default }, + { "CSGRP_BURST_LIMIT_DATA_GMI", 7, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPCTL_MISC[] = { + { "ALLOW_DEEP_SLEEP_MODE", 0, 2, &umr_bitfield_default }, + { "STCTRL_RSMU_IDLE_THRESHOLD", 3, 5, &umr_bitfield_default }, + { "STCTRL_DAGB_IDLE_THRESHOLD", 6, 10, &umr_bitfield_default }, + { "STCTRL_IGNORE_PROTECTION_FAULT", 11, 11, &umr_bitfield_default }, + { "IGNORE_EA0_SDP_ACK", 12, 12, &umr_bitfield_default }, + { "IGNORE_EA1_SDP_ACK", 13, 13, &umr_bitfield_default }, + { "PGFSM_CMD_STATUS", 14, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPCTL_MMHUB_DEEPSLEEP[] = { + { "DS0", 0, 0, &umr_bitfield_default }, + { "DS1", 1, 1, &umr_bitfield_default }, + { "DS2", 2, 2, &umr_bitfield_default }, + { "DS3", 3, 3, &umr_bitfield_default }, + { "DS4", 4, 4, &umr_bitfield_default }, + { "DS5", 5, 5, &umr_bitfield_default }, + { "DS6", 6, 6, &umr_bitfield_default }, + { "DS7", 7, 7, &umr_bitfield_default }, + { "DS8", 8, 8, &umr_bitfield_default }, + { "DS9", 9, 9, &umr_bitfield_default }, + { "DS10", 10, 10, &umr_bitfield_default }, + { "DS11", 11, 11, &umr_bitfield_default }, + { "DS12", 12, 12, &umr_bitfield_default }, + { "DS13", 13, 13, &umr_bitfield_default }, + { "DS14", 14, 14, &umr_bitfield_default }, + { "DS15", 15, 15, &umr_bitfield_default }, + { "DS16", 16, 16, &umr_bitfield_default }, + { "SETCLEAR", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPCTL_MMHUB_DEEPSLEEP_OVERRIDE[] = { + { "DS0", 0, 0, &umr_bitfield_default }, + { "DS1", 1, 1, &umr_bitfield_default }, + { "DS2", 2, 2, &umr_bitfield_default }, + { "DS3", 3, 3, &umr_bitfield_default }, + { "DS4", 4, 4, &umr_bitfield_default }, + { "DS5", 5, 5, &umr_bitfield_default }, + { "DS6", 6, 6, &umr_bitfield_default }, + { "DS7", 7, 7, &umr_bitfield_default }, + { "DS8", 8, 8, &umr_bitfield_default }, + { "DS9", 9, 9, &umr_bitfield_default }, + { "DS10", 10, 10, &umr_bitfield_default }, + { "DS11", 11, 11, &umr_bitfield_default }, + { "DS12", 12, 12, &umr_bitfield_default }, + { "DS13", 13, 13, &umr_bitfield_default }, + { "DS14", 14, 14, &umr_bitfield_default }, + { "DS15", 15, 15, &umr_bitfield_default }, + { "DS16", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPCTL_PG_IGNORE_DEEPSLEEP[] = { + { "ALLIPS", 0, 0, &umr_bitfield_default }, + { "DS0", 1, 1, &umr_bitfield_default }, + { "DS1", 2, 2, &umr_bitfield_default }, + { "DS2", 3, 3, &umr_bitfield_default }, + { "DS3", 4, 4, &umr_bitfield_default }, + { "DS4", 5, 5, &umr_bitfield_default }, + { "DS5", 6, 6, &umr_bitfield_default }, + { "DS6", 7, 7, &umr_bitfield_default }, + { "DS7", 8, 8, &umr_bitfield_default }, + { "DS8", 9, 9, &umr_bitfield_default }, + { "DS9", 10, 10, &umr_bitfield_default }, + { "DS10", 11, 11, &umr_bitfield_default }, + { "DS11", 12, 12, &umr_bitfield_default }, + { "DS12", 13, 13, &umr_bitfield_default }, + { "DS13", 14, 14, &umr_bitfield_default }, + { "DS14", 15, 15, &umr_bitfield_default }, + { "DS15", 16, 16, &umr_bitfield_default }, + { "DS16", 17, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPCTL_PG_DAGB[] = { + { "DS0", 0, 0, &umr_bitfield_default }, + { "DS1", 1, 1, &umr_bitfield_default }, + { "DS2", 2, 2, &umr_bitfield_default }, + { "DS3", 3, 3, &umr_bitfield_default }, + { "DS4", 4, 4, &umr_bitfield_default }, + { "DS5", 5, 5, &umr_bitfield_default }, + { "DS6", 6, 6, &umr_bitfield_default }, + { "DS7", 7, 7, &umr_bitfield_default }, + { "DS8", 8, 8, &umr_bitfield_default }, + { "DS9", 9, 9, &umr_bitfield_default }, + { "DS10", 10, 10, &umr_bitfield_default }, + { "DS11", 11, 11, &umr_bitfield_default }, + { "DS12", 12, 12, &umr_bitfield_default }, + { "DS13", 13, 13, &umr_bitfield_default }, + { "DS14", 14, 14, &umr_bitfield_default }, + { "DS15", 15, 15, &umr_bitfield_default }, + { "DS16", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPCTL0_RENG_RAM_INDEX[] = { + { "RENG_RAM_INDEX", 0, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPCTL0_RENG_RAM_DATA[] = { + { "RENG_RAM_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPCTL0_RENG_EXECUTE[] = { + { "RENG_EXECUTE_ON_PWR_UP", 0, 0, &umr_bitfield_default }, + { "RENG_EXECUTE_NOW", 1, 1, &umr_bitfield_default }, + { "RENG_EXECUTE_NOW_MODE", 2, 2, &umr_bitfield_default }, + { "RENG_EXECUTE_NOW_START_PTR", 3, 13, &umr_bitfield_default }, + { "RENG_EXECUTE_END_PTR", 14, 24, &umr_bitfield_default }, + { "RENG_EXECUTE_ON_REG_UPDATE", 25, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPCTL0_MISC[] = { + { "CRITICAL_REGS_LOCK", 11, 11, &umr_bitfield_default }, + { "TILE_IDLE_THRESHOLD", 12, 14, &umr_bitfield_default }, + { "RENG_MEM_LS_ENABLE", 15, 15, &umr_bitfield_default }, + { "STCTRL_FORCE_PGFSM_CMD_DONE", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPCTL0_STCTRL_REGISTER_SAVE_RANGE0[] = { + { "STCTRL_REGISTER_SAVE_BASE", 0, 15, &umr_bitfield_default }, + { "STCTRL_REGISTER_SAVE_LIMIT", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPCTL0_STCTRL_REGISTER_SAVE_RANGE1[] = { + { "STCTRL_REGISTER_SAVE_BASE", 0, 15, &umr_bitfield_default }, + { "STCTRL_REGISTER_SAVE_LIMIT", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPCTL0_STCTRL_REGISTER_SAVE_RANGE2[] = { + { "STCTRL_REGISTER_SAVE_BASE", 0, 15, &umr_bitfield_default }, + { "STCTRL_REGISTER_SAVE_LIMIT", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET[] = { + { "STCTRL_REGISTER_SAVE_EXCL0", 0, 15, &umr_bitfield_default }, + { "STCTRL_REGISTER_SAVE_EXCL1", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1[] = { + { "STCTRL_REGISTER_SAVE_EXCL2", 0, 15, &umr_bitfield_default }, + { "STCTRL_REGISTER_SAVE_EXCL3", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPCTL1_RENG_RAM_INDEX[] = { + { "RENG_RAM_INDEX", 0, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPCTL1_RENG_RAM_DATA[] = { + { "RENG_RAM_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPCTL1_RENG_EXECUTE[] = { + { "RENG_EXECUTE_ON_PWR_UP", 0, 0, &umr_bitfield_default }, + { "RENG_EXECUTE_NOW", 1, 1, &umr_bitfield_default }, + { "RENG_EXECUTE_NOW_MODE", 2, 2, &umr_bitfield_default }, + { "RENG_EXECUTE_NOW_START_PTR", 3, 12, &umr_bitfield_default }, + { "RENG_EXECUTE_END_PTR", 13, 22, &umr_bitfield_default }, + { "RENG_EXECUTE_ON_REG_UPDATE", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPCTL1_MISC[] = { + { "CRITICAL_REGS_LOCK", 10, 10, &umr_bitfield_default }, + { "TILE_IDLE_THRESHOLD", 11, 13, &umr_bitfield_default }, + { "RENG_MEM_LS_ENABLE", 14, 14, &umr_bitfield_default }, + { "STCTRL_FORCE_PGFSM_CMD_DONE", 15, 15, &umr_bitfield_default }, + { "DEEPSLEEP_DISCSDP", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPCTL1_STCTRL_REGISTER_SAVE_RANGE0[] = { + { "STCTRL_REGISTER_SAVE_BASE", 0, 15, &umr_bitfield_default }, + { "STCTRL_REGISTER_SAVE_LIMIT", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPCTL1_STCTRL_REGISTER_SAVE_RANGE1[] = { + { "STCTRL_REGISTER_SAVE_BASE", 0, 15, &umr_bitfield_default }, + { "STCTRL_REGISTER_SAVE_LIMIT", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPCTL1_STCTRL_REGISTER_SAVE_RANGE2[] = { + { "STCTRL_REGISTER_SAVE_BASE", 0, 15, &umr_bitfield_default }, + { "STCTRL_REGISTER_SAVE_LIMIT", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET[] = { + { "STCTRL_REGISTER_SAVE_EXCL0", 0, 15, &umr_bitfield_default }, + { "STCTRL_REGISTER_SAVE_EXCL1", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1[] = { + { "STCTRL_REGISTER_SAVE_EXCL2", 0, 15, &umr_bitfield_default }, + { "STCTRL_REGISTER_SAVE_EXCL3", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPCTL2_RENG_RAM_INDEX[] = { + { "RENG_RAM_INDEX", 0, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPCTL2_RENG_RAM_DATA[] = { + { "RENG_RAM_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPCTL2_RENG_EXECUTE[] = { + { "RENG_EXECUTE_ON_PWR_UP", 0, 0, &umr_bitfield_default }, + { "RENG_EXECUTE_NOW", 1, 1, &umr_bitfield_default }, + { "RENG_EXECUTE_NOW_MODE", 2, 2, &umr_bitfield_default }, + { "RENG_EXECUTE_NOW_START_PTR", 3, 12, &umr_bitfield_default }, + { "RENG_EXECUTE_END_PTR", 13, 22, &umr_bitfield_default }, + { "RENG_EXECUTE_ON_REG_UPDATE", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPCTL2_MISC[] = { + { "CRITICAL_REGS_LOCK", 10, 10, &umr_bitfield_default }, + { "TILE_IDLE_THRESHOLD", 11, 13, &umr_bitfield_default }, + { "RENG_MEM_LS_ENABLE", 14, 14, &umr_bitfield_default }, + { "STCTRL_FORCE_PGFSM_CMD_DONE", 15, 15, &umr_bitfield_default }, + { "DEEPSLEEP_DISCSDP", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPCTL2_STCTRL_REGISTER_SAVE_RANGE0[] = { + { "STCTRL_REGISTER_SAVE_BASE", 0, 15, &umr_bitfield_default }, + { "STCTRL_REGISTER_SAVE_LIMIT", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPCTL2_STCTRL_REGISTER_SAVE_RANGE1[] = { + { "STCTRL_REGISTER_SAVE_BASE", 0, 15, &umr_bitfield_default }, + { "STCTRL_REGISTER_SAVE_LIMIT", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPCTL2_STCTRL_REGISTER_SAVE_RANGE2[] = { + { "STCTRL_REGISTER_SAVE_BASE", 0, 15, &umr_bitfield_default }, + { "STCTRL_REGISTER_SAVE_LIMIT", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET[] = { + { "STCTRL_REGISTER_SAVE_EXCL0", 0, 15, &umr_bitfield_default }, + { "STCTRL_REGISTER_SAVE_EXCL1", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1[] = { + { "STCTRL_REGISTER_SAVE_EXCL2", 0, 15, &umr_bitfield_default }, + { "STCTRL_REGISTER_SAVE_EXCL3", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_MX_L1_TLB0_STATUS[] = { + { "BUSY", 0, 0, &umr_bitfield_default }, + { "FOUND_PARITY_ERRORS", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_MX_L1_TLB1_STATUS[] = { + { "BUSY", 0, 0, &umr_bitfield_default }, + { "FOUND_PARITY_ERRORS", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_MX_L1_TLB2_STATUS[] = { + { "BUSY", 0, 0, &umr_bitfield_default }, + { "FOUND_PARITY_ERRORS", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_MX_L1_TLB3_STATUS[] = { + { "BUSY", 0, 0, &umr_bitfield_default }, + { "FOUND_PARITY_ERRORS", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_MX_L1_TLB4_STATUS[] = { + { "BUSY", 0, 0, &umr_bitfield_default }, + { "FOUND_PARITY_ERRORS", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_MX_L1_TLB5_STATUS[] = { + { "BUSY", 0, 0, &umr_bitfield_default }, + { "FOUND_PARITY_ERRORS", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_MX_L1_TLB6_STATUS[] = { + { "BUSY", 0, 0, &umr_bitfield_default }, + { "FOUND_PARITY_ERRORS", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_MX_L1_TLB7_STATUS[] = { + { "BUSY", 0, 0, &umr_bitfield_default }, + { "FOUND_PARITY_ERRORS", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_MX_L1_PERFCOUNTER0_CFG[] = { + { "PERF_SEL", 0, 7, &umr_bitfield_default }, + { "PERF_SEL_END", 8, 15, &umr_bitfield_default }, + { "PERF_MODE", 24, 27, &umr_bitfield_default }, + { "ENABLE", 28, 28, &umr_bitfield_default }, + { "CLEAR", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_MX_L1_PERFCOUNTER1_CFG[] = { + { "PERF_SEL", 0, 7, &umr_bitfield_default }, + { "PERF_SEL_END", 8, 15, &umr_bitfield_default }, + { "PERF_MODE", 24, 27, &umr_bitfield_default }, + { "ENABLE", 28, 28, &umr_bitfield_default }, + { "CLEAR", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_MX_L1_PERFCOUNTER2_CFG[] = { + { "PERF_SEL", 0, 7, &umr_bitfield_default }, + { "PERF_SEL_END", 8, 15, &umr_bitfield_default }, + { "PERF_MODE", 24, 27, &umr_bitfield_default }, + { "ENABLE", 28, 28, &umr_bitfield_default }, + { "CLEAR", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_MX_L1_PERFCOUNTER3_CFG[] = { + { "PERF_SEL", 0, 7, &umr_bitfield_default }, + { "PERF_SEL_END", 8, 15, &umr_bitfield_default }, + { "PERF_MODE", 24, 27, &umr_bitfield_default }, + { "ENABLE", 28, 28, &umr_bitfield_default }, + { "CLEAR", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL[] = { + { "PERF_COUNTER_SELECT", 0, 3, &umr_bitfield_default }, + { "START_TRIGGER", 8, 15, &umr_bitfield_default }, + { "STOP_TRIGGER", 16, 23, &umr_bitfield_default }, + { "ENABLE_ANY", 24, 24, &umr_bitfield_default }, + { "CLEAR_ALL", 25, 25, &umr_bitfield_default }, + { "STOP_ALL_ON_SATURATE", 26, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_MX_L1_PERFCOUNTER_LO[] = { + { "COUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_MX_L1_PERFCOUNTER_HI[] = { + { "COUNTER_HI", 0, 15, &umr_bitfield_default }, + { "COMPARE_VALUE", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_L2_SAW_CNTL[] = { + { "ENABLE_L2_CACHE", 0, 0, &umr_bitfield_default }, + { "ENABLE_L2_FRAGMENT_PROCESSING", 1, 1, &umr_bitfield_default }, + { "L2_CACHE_PTE_ENDIAN_SWAP_MODE", 2, 3, &umr_bitfield_default }, + { "L2_CACHE_PDE_ENDIAN_SWAP_MODE", 4, 5, &umr_bitfield_default }, + { "L2_PDE0_CACHE_TAG_GENERATION_MODE", 8, 8, &umr_bitfield_default }, + { "ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE", 9, 9, &umr_bitfield_default }, + { "ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE", 10, 10, &umr_bitfield_default }, + { "ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY", 11, 11, &umr_bitfield_default }, + { "L2_PDE0_CACHE_SPLIT_MODE", 12, 14, &umr_bitfield_default }, + { "EFFECTIVE_L2_QUEUE_SIZE", 15, 17, &umr_bitfield_default }, + { "PDE_FAULT_CLASSIFICATION", 18, 18, &umr_bitfield_default }, + { "CONTEXT1_IDENTITY_ACCESS_MODE", 19, 20, &umr_bitfield_default }, + { "IDENTITY_MODE_FRAGMENT_SIZE", 21, 25, &umr_bitfield_default }, + { "L2_CACHE_4K_SWAP_TAG_INDEX_LSBS", 26, 27, &umr_bitfield_default }, + { "L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_L2_SAW_CNTL2[] = { + { "INVALIDATE_ALL_L1_TLBS", 0, 0, &umr_bitfield_default }, + { "INVALIDATE_L2_CACHE", 1, 1, &umr_bitfield_default }, + { "DISABLE_INVALIDATE_PER_DOMAIN", 21, 21, &umr_bitfield_default }, + { "DISABLE_BIGK_CACHE_OPTIMIZATION", 22, 22, &umr_bitfield_default }, + { "L2_CACHE_BIGK_VMID_MODE", 23, 25, &umr_bitfield_default }, + { "INVALIDATE_CACHE_MODE", 26, 27, &umr_bitfield_default }, + { "PDE_CACHE_EFFECTIVE_SIZE", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_L2_SAW_CNTL3[] = { + { "BANK_SELECT", 0, 5, &umr_bitfield_default }, + { "L2_CACHE_UPDATE_MODE", 6, 7, &umr_bitfield_default }, + { "L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE", 8, 12, &umr_bitfield_default }, + { "L2_CACHE_BIGK_FRAGMENT_SIZE", 15, 19, &umr_bitfield_default }, + { "L2_CACHE_BIGK_ASSOCIATIVITY", 20, 20, &umr_bitfield_default }, + { "L2_CACHE_4K_EFFECTIVE_SIZE", 21, 23, &umr_bitfield_default }, + { "L2_CACHE_BIGK_EFFECTIVE_SIZE", 24, 27, &umr_bitfield_default }, + { "L2_CACHE_4K_FORCE_MISS", 28, 28, &umr_bitfield_default }, + { "L2_CACHE_BIGK_FORCE_MISS", 29, 29, &umr_bitfield_default }, + { "PDE_CACHE_FORCE_MISS", 30, 30, &umr_bitfield_default }, + { "L2_CACHE_4K_ASSOCIATIVITY", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_L2_SAW_CNTL4[] = { + { "L2_CACHE_4K_PARTITION_COUNT", 0, 5, &umr_bitfield_default }, + { "VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL", 6, 6, &umr_bitfield_default }, + { "VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED", 7, 7, &umr_bitfield_default }, + { "VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP", 8, 8, &umr_bitfield_default }, + { "VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL", 9, 9, &umr_bitfield_default }, + { "VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED", 10, 10, &umr_bitfield_default }, + { "VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP", 11, 11, &umr_bitfield_default }, + { "VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL", 12, 12, &umr_bitfield_default }, + { "VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED", 13, 13, &umr_bitfield_default }, + { "VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP", 14, 14, &umr_bitfield_default }, + { "VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL", 15, 15, &umr_bitfield_default }, + { "VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED", 16, 16, &umr_bitfield_default }, + { "VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP", 17, 17, &umr_bitfield_default }, + { "L2_CACHE_4K_LRU_ADDR_MATCHING", 18, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_L2_SAW_CONTEXT0_CNTL[] = { + { "ENABLE_CONTEXT", 0, 0, &umr_bitfield_default }, + { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 3, 3, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 4, 4, &umr_bitfield_default }, + { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 6, 6, &umr_bitfield_default }, + { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT", 7, 7, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT", 9, 9, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_DEFAULT", 10, 10, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_SAVE", 11, 11, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 12, 12, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 13, 13, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_SAVE", 14, 14, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_SAVE", 17, 17, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT", 18, 18, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_DEFAULT", 19, 19, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_SAVE", 20, 20, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT", 21, 21, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT", 22, 22, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_SAVE", 23, 23, &umr_bitfield_default }, + { "PAGE_TABLE_BLOCK_SIZE", 24, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_L2_SAW_CONTEXT0_CNTL2[] = { + { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 0, 0, &umr_bitfield_default }, + { "ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT", 1, 1, &umr_bitfield_default }, + { "ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT", 2, 2, &umr_bitfield_default }, + { "ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES", 3, 3, &umr_bitfield_default }, + { "WAIT_FOR_IDLE_WHEN_INVALIDATE", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32[] = { + { "PHYSICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32[] = { + { "PHYSICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_L2_SAW_CONTEXTS_DISABLE[] = { + { "DISABLE_CONTEXT_0", 0, 0, &umr_bitfield_default }, + { "DISABLE_CONTEXT_1", 1, 1, &umr_bitfield_default }, + { "DISABLE_CONTEXT_2", 2, 2, &umr_bitfield_default }, + { "DISABLE_CONTEXT_3", 3, 3, &umr_bitfield_default }, + { "DISABLE_CONTEXT_4", 4, 4, &umr_bitfield_default }, + { "DISABLE_CONTEXT_5", 5, 5, &umr_bitfield_default }, + { "DISABLE_CONTEXT_6", 6, 6, &umr_bitfield_default }, + { "DISABLE_CONTEXT_7", 7, 7, &umr_bitfield_default }, + { "DISABLE_CONTEXT_8", 8, 8, &umr_bitfield_default }, + { "DISABLE_CONTEXT_9", 9, 9, &umr_bitfield_default }, + { "DISABLE_CONTEXT_10", 10, 10, &umr_bitfield_default }, + { "DISABLE_CONTEXT_11", 11, 11, &umr_bitfield_default }, + { "DISABLE_CONTEXT_12", 12, 12, &umr_bitfield_default }, + { "DISABLE_CONTEXT_13", 13, 13, &umr_bitfield_default }, + { "DISABLE_CONTEXT_14", 14, 14, &umr_bitfield_default }, + { "DISABLE_CONTEXT_15", 15, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_L2_SAW_PIPES_BUSY[] = { + { "PIPES_BUSY", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmATC_L2_CNTL[] = { + { "NUMBER_OF_TRANSLATION_READ_REQUESTS", 0, 1, &umr_bitfield_default }, + { "NUMBER_OF_TRANSLATION_WRITE_REQUESTS", 3, 4, &umr_bitfield_default }, + { "NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD", 6, 6, &umr_bitfield_default }, + { "NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD", 7, 7, &umr_bitfield_default }, + { "CACHE_INVALIDATE_MODE", 8, 10, &umr_bitfield_default }, + { "ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY", 11, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmATC_L2_CNTL2[] = { + { "BANK_SELECT", 0, 5, &umr_bitfield_default }, + { "L2_CACHE_UPDATE_MODE", 6, 7, &umr_bitfield_default }, + { "ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE", 8, 8, &umr_bitfield_default }, + { "L2_CACHE_SWAP_TAG_INDEX_LSBS", 9, 11, &umr_bitfield_default }, + { "L2_CACHE_VMID_MODE", 12, 14, &umr_bitfield_default }, + { "L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE", 15, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmATC_L2_CACHE_DATA0[] = { + { "DATA_REGISTER_VALID", 0, 0, &umr_bitfield_default }, + { "CACHE_ENTRY_VALID", 1, 1, &umr_bitfield_default }, + { "CACHED_ATTRIBUTES", 2, 22, &umr_bitfield_default }, + { "VIRTUAL_PAGE_ADDRESS_HIGH", 23, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmATC_L2_CACHE_DATA1[] = { + { "VIRTUAL_PAGE_ADDRESS_LOW", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmATC_L2_CACHE_DATA2[] = { + { "PHYSICAL_PAGE_ADDRESS", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmATC_L2_CNTL3[] = { + { "DELAY_SEND_INVALIDATION_REQUEST", 0, 2, &umr_bitfield_default }, + { "ATS_REQUEST_CREDIT_MINUS1", 3, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmATC_L2_STATUS[] = { + { "BUSY", 0, 0, &umr_bitfield_default }, + { "PARITY_ERROR_INFO", 1, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmATC_L2_STATUS2[] = { + { "IFIFO_NON_FATAL_PARITY_ERROR_INFO", 0, 7, &umr_bitfield_default }, + { "IFIFO_FATAL_PARITY_ERROR_INFO", 8, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmATC_L2_MISC_CG[] = { + { "OFFDLY", 6, 11, &umr_bitfield_default }, + { "ENABLE", 18, 18, &umr_bitfield_default }, + { "MEM_LS_ENABLE", 19, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmATC_L2_MEM_POWER_LS[] = { + { "LS_SETUP", 0, 5, &umr_bitfield_default }, + { "LS_HOLD", 6, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmATC_L2_CGTT_CLK_CTRL[] = { + { "ON_DELAY", 0, 3, &umr_bitfield_default }, + { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default }, + { "MGLS_OVERRIDE", 15, 15, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE", 16, 23, &umr_bitfield_default }, + { "SOFT_OVERRIDE", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_L2_CNTL[] = { + { "ENABLE_L2_CACHE", 0, 0, &umr_bitfield_default }, + { "ENABLE_L2_FRAGMENT_PROCESSING", 1, 1, &umr_bitfield_default }, + { "L2_CACHE_PTE_ENDIAN_SWAP_MODE", 2, 3, &umr_bitfield_default }, + { "L2_CACHE_PDE_ENDIAN_SWAP_MODE", 4, 5, &umr_bitfield_default }, + { "L2_PDE0_CACHE_TAG_GENERATION_MODE", 8, 8, &umr_bitfield_default }, + { "ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE", 9, 9, &umr_bitfield_default }, + { "ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE", 10, 10, &umr_bitfield_default }, + { "ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY", 11, 11, &umr_bitfield_default }, + { "L2_PDE0_CACHE_SPLIT_MODE", 12, 14, &umr_bitfield_default }, + { "EFFECTIVE_L2_QUEUE_SIZE", 15, 17, &umr_bitfield_default }, + { "PDE_FAULT_CLASSIFICATION", 18, 18, &umr_bitfield_default }, + { "CONTEXT1_IDENTITY_ACCESS_MODE", 19, 20, &umr_bitfield_default }, + { "IDENTITY_MODE_FRAGMENT_SIZE", 21, 25, &umr_bitfield_default }, + { "L2_PTE_CACHE_ADDR_MODE", 26, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_L2_CNTL2[] = { + { "INVALIDATE_ALL_L1_TLBS", 0, 0, &umr_bitfield_default }, + { "INVALIDATE_L2_CACHE", 1, 1, &umr_bitfield_default }, + { "DISABLE_INVALIDATE_PER_DOMAIN", 21, 21, &umr_bitfield_default }, + { "DISABLE_BIGK_CACHE_OPTIMIZATION", 22, 22, &umr_bitfield_default }, + { "L2_PTE_CACHE_VMID_MODE", 23, 25, &umr_bitfield_default }, + { "INVALIDATE_CACHE_MODE", 26, 27, &umr_bitfield_default }, + { "PDE_CACHE_EFFECTIVE_SIZE", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_L2_CNTL3[] = { + { "BANK_SELECT", 0, 5, &umr_bitfield_default }, + { "L2_CACHE_UPDATE_MODE", 6, 7, &umr_bitfield_default }, + { "L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE", 8, 12, &umr_bitfield_default }, + { "L2_CACHE_BIGK_FRAGMENT_SIZE", 15, 19, &umr_bitfield_default }, + { "L2_CACHE_BIGK_ASSOCIATIVITY", 20, 20, &umr_bitfield_default }, + { "L2_CACHE_4K_EFFECTIVE_SIZE", 21, 23, &umr_bitfield_default }, + { "L2_CACHE_BIGK_EFFECTIVE_SIZE", 24, 27, &umr_bitfield_default }, + { "L2_CACHE_4K_FORCE_MISS", 28, 28, &umr_bitfield_default }, + { "L2_CACHE_BIGK_FORCE_MISS", 29, 29, &umr_bitfield_default }, + { "PDE_CACHE_FORCE_MISS", 30, 30, &umr_bitfield_default }, + { "L2_CACHE_4K_ASSOCIATIVITY", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_L2_STATUS[] = { + { "L2_BUSY", 0, 0, &umr_bitfield_default }, + { "CONTEXT_DOMAIN_BUSY", 1, 16, &umr_bitfield_default }, + { "FOUND_4K_PTE_CACHE_PARITY_ERRORS", 17, 17, &umr_bitfield_default }, + { "FOUND_BIGK_PTE_CACHE_PARITY_ERRORS", 18, 18, &umr_bitfield_default }, + { "FOUND_PDE0_CACHE_PARITY_ERRORS", 19, 19, &umr_bitfield_default }, + { "FOUND_PDE1_CACHE_PARITY_ERRORS", 20, 20, &umr_bitfield_default }, + { "FOUND_PDE2_CACHE_PARITY_ERRORS", 21, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_DUMMY_PAGE_FAULT_CNTL[] = { + { "DUMMY_PAGE_FAULT_ENABLE", 0, 0, &umr_bitfield_default }, + { "DUMMY_PAGE_ADDRESS_LOGICAL", 1, 1, &umr_bitfield_default }, + { "DUMMY_PAGE_COMPARE_MSBS", 2, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_DUMMY_PAGE_FAULT_ADDR_LO32[] = { + { "DUMMY_PAGE_ADDR_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_DUMMY_PAGE_FAULT_ADDR_HI32[] = { + { "DUMMY_PAGE_ADDR_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_L2_PROTECTION_FAULT_CNTL[] = { + { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 0, 0, &umr_bitfield_default }, + { "ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES", 1, 1, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 2, 2, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_DEFAULT", 3, 3, &umr_bitfield_default }, + { "PDE1_PROTECTION_FAULT_ENABLE_DEFAULT", 4, 4, &umr_bitfield_default }, + { "PDE2_PROTECTION_FAULT_ENABLE_DEFAULT", 5, 5, &umr_bitfield_default }, + { "TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT", 6, 6, &umr_bitfield_default }, + { "NACK_PROTECTION_FAULT_ENABLE_DEFAULT", 7, 7, &umr_bitfield_default }, + { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT", 8, 8, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 9, 9, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 10, 10, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_DEFAULT", 11, 11, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT", 12, 12, &umr_bitfield_default }, + { "CLIENT_ID_NO_RETRY_FAULT_INTERRUPT", 13, 28, &umr_bitfield_default }, + { "OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT", 29, 29, &umr_bitfield_default }, + { "CRASH_ON_NO_RETRY_FAULT", 30, 30, &umr_bitfield_default }, + { "CRASH_ON_RETRY_FAULT", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_L2_PROTECTION_FAULT_CNTL2[] = { + { "CLIENT_ID_PRT_FAULT_INTERRUPT", 0, 15, &umr_bitfield_default }, + { "OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT", 16, 16, &umr_bitfield_default }, + { "ACTIVE_PAGE_MIGRATION_PTE", 17, 17, &umr_bitfield_default }, + { "ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY", 18, 18, &umr_bitfield_default }, + { "ENABLE_RETRY_FAULT_INTERRUPT", 19, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_L2_PROTECTION_FAULT_MM_CNTL3[] = { + { "VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_L2_PROTECTION_FAULT_MM_CNTL4[] = { + { "VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_L2_PROTECTION_FAULT_STATUS[] = { + { "MORE_FAULTS", 0, 0, &umr_bitfield_default }, + { "WALKER_ERROR", 1, 3, &umr_bitfield_default }, + { "PERMISSION_FAULTS", 4, 7, &umr_bitfield_default }, + { "MAPPING_ERROR", 8, 8, &umr_bitfield_default }, + { "CID", 9, 17, &umr_bitfield_default }, + { "RW", 18, 18, &umr_bitfield_default }, + { "ATOMIC", 19, 19, &umr_bitfield_default }, + { "VMID", 20, 23, &umr_bitfield_default }, + { "VF", 24, 24, &umr_bitfield_default }, + { "VFID", 25, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_L2_PROTECTION_FAULT_ADDR_LO32[] = { + { "LOGICAL_PAGE_ADDR_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_L2_PROTECTION_FAULT_ADDR_HI32[] = { + { "LOGICAL_PAGE_ADDR_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32[] = { + { "PHYSICAL_PAGE_ADDR_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32[] = { + { "PHYSICAL_PAGE_ADDR_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32[] = { + { "PHYSICAL_PAGE_OFFSET_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32[] = { + { "PHYSICAL_PAGE_OFFSET_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_L2_CNTL4[] = { + { "L2_CACHE_4K_PARTITION_COUNT", 0, 5, &umr_bitfield_default }, + { "VMC_TAP_PDE_REQUEST_PHYSICAL", 6, 6, &umr_bitfield_default }, + { "VMC_TAP_PTE_REQUEST_PHYSICAL", 7, 7, &umr_bitfield_default }, + { "MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT", 8, 17, &umr_bitfield_default }, + { "MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT", 18, 27, &umr_bitfield_default }, + { "BPM_CGCGLS_OVERRIDE", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_L2_MM_GROUP_RT_CLASSES[] = { + { "GROUP_0_RT_CLASS", 0, 0, &umr_bitfield_default }, + { "GROUP_1_RT_CLASS", 1, 1, &umr_bitfield_default }, + { "GROUP_2_RT_CLASS", 2, 2, &umr_bitfield_default }, + { "GROUP_3_RT_CLASS", 3, 3, &umr_bitfield_default }, + { "GROUP_4_RT_CLASS", 4, 4, &umr_bitfield_default }, + { "GROUP_5_RT_CLASS", 5, 5, &umr_bitfield_default }, + { "GROUP_6_RT_CLASS", 6, 6, &umr_bitfield_default }, + { "GROUP_7_RT_CLASS", 7, 7, &umr_bitfield_default }, + { "GROUP_8_RT_CLASS", 8, 8, &umr_bitfield_default }, + { "GROUP_9_RT_CLASS", 9, 9, &umr_bitfield_default }, + { "GROUP_10_RT_CLASS", 10, 10, &umr_bitfield_default }, + { "GROUP_11_RT_CLASS", 11, 11, &umr_bitfield_default }, + { "GROUP_12_RT_CLASS", 12, 12, &umr_bitfield_default }, + { "GROUP_13_RT_CLASS", 13, 13, &umr_bitfield_default }, + { "GROUP_14_RT_CLASS", 14, 14, &umr_bitfield_default }, + { "GROUP_15_RT_CLASS", 15, 15, &umr_bitfield_default }, + { "GROUP_16_RT_CLASS", 16, 16, &umr_bitfield_default }, + { "GROUP_17_RT_CLASS", 17, 17, &umr_bitfield_default }, + { "GROUP_18_RT_CLASS", 18, 18, &umr_bitfield_default }, + { "GROUP_19_RT_CLASS", 19, 19, &umr_bitfield_default }, + { "GROUP_20_RT_CLASS", 20, 20, &umr_bitfield_default }, + { "GROUP_21_RT_CLASS", 21, 21, &umr_bitfield_default }, + { "GROUP_22_RT_CLASS", 22, 22, &umr_bitfield_default }, + { "GROUP_23_RT_CLASS", 23, 23, &umr_bitfield_default }, + { "GROUP_24_RT_CLASS", 24, 24, &umr_bitfield_default }, + { "GROUP_25_RT_CLASS", 25, 25, &umr_bitfield_default }, + { "GROUP_26_RT_CLASS", 26, 26, &umr_bitfield_default }, + { "GROUP_27_RT_CLASS", 27, 27, &umr_bitfield_default }, + { "GROUP_28_RT_CLASS", 28, 28, &umr_bitfield_default }, + { "GROUP_29_RT_CLASS", 29, 29, &umr_bitfield_default }, + { "GROUP_30_RT_CLASS", 30, 30, &umr_bitfield_default }, + { "GROUP_31_RT_CLASS", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_L2_BANK_SELECT_RESERVED_CID[] = { + { "RESERVED_READ_CLIENT_ID", 0, 8, &umr_bitfield_default }, + { "RESERVED_WRITE_CLIENT_ID", 10, 18, &umr_bitfield_default }, + { "ENABLE", 20, 20, &umr_bitfield_default }, + { "RESERVED_CACHE_INVALIDATION_MODE", 24, 24, &umr_bitfield_default }, + { "RESERVED_CACHE_PRIVATE_INVALIDATION", 25, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_L2_BANK_SELECT_RESERVED_CID2[] = { + { "RESERVED_READ_CLIENT_ID", 0, 8, &umr_bitfield_default }, + { "RESERVED_WRITE_CLIENT_ID", 10, 18, &umr_bitfield_default }, + { "ENABLE", 20, 20, &umr_bitfield_default }, + { "RESERVED_CACHE_INVALIDATION_MODE", 24, 24, &umr_bitfield_default }, + { "RESERVED_CACHE_PRIVATE_INVALIDATION", 25, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_L2_CACHE_PARITY_CNTL[] = { + { "ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES", 0, 0, &umr_bitfield_default }, + { "ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES", 1, 1, &umr_bitfield_default }, + { "ENABLE_PARITY_CHECKS_IN_PDE_CACHES", 2, 2, &umr_bitfield_default }, + { "FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE", 3, 3, &umr_bitfield_default }, + { "FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE", 4, 4, &umr_bitfield_default }, + { "FORCE_PARITY_MISMATCH_IN_PDE_CACHE", 5, 5, &umr_bitfield_default }, + { "FORCE_CACHE_BANK", 6, 8, &umr_bitfield_default }, + { "FORCE_CACHE_NUMBER", 9, 11, &umr_bitfield_default }, + { "FORCE_CACHE_ASSOC", 12, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_L2_CGTT_CLK_CTRL[] = { + { "ON_DELAY", 0, 3, &umr_bitfield_default }, + { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default }, + { "MGLS_OVERRIDE", 15, 15, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE", 16, 23, &umr_bitfield_default }, + { "SOFT_OVERRIDE", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT0_CNTL[] = { + { "ENABLE_CONTEXT", 0, 0, &umr_bitfield_default }, + { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default }, + { "PAGE_TABLE_BLOCK_SIZE", 3, 6, &umr_bitfield_default }, + { "RETRY_PERMISSION_OR_INVALID_PAGE_FAULT", 7, 7, &umr_bitfield_default }, + { "RETRY_OTHER_FAULT", 8, 8, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 9, 9, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 10, 10, &umr_bitfield_default }, + { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 11, 11, &umr_bitfield_default }, + { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT", 12, 12, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT", 13, 13, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_DEFAULT", 14, 14, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 17, 17, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 18, 18, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT", 19, 19, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_DEFAULT", 20, 20, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT", 21, 21, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT", 22, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT1_CNTL[] = { + { "ENABLE_CONTEXT", 0, 0, &umr_bitfield_default }, + { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default }, + { "PAGE_TABLE_BLOCK_SIZE", 3, 6, &umr_bitfield_default }, + { "RETRY_PERMISSION_OR_INVALID_PAGE_FAULT", 7, 7, &umr_bitfield_default }, + { "RETRY_OTHER_FAULT", 8, 8, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 9, 9, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 10, 10, &umr_bitfield_default }, + { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 11, 11, &umr_bitfield_default }, + { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT", 12, 12, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT", 13, 13, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_DEFAULT", 14, 14, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 17, 17, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 18, 18, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT", 19, 19, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_DEFAULT", 20, 20, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT", 21, 21, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT", 22, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT2_CNTL[] = { + { "ENABLE_CONTEXT", 0, 0, &umr_bitfield_default }, + { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default }, + { "PAGE_TABLE_BLOCK_SIZE", 3, 6, &umr_bitfield_default }, + { "RETRY_PERMISSION_OR_INVALID_PAGE_FAULT", 7, 7, &umr_bitfield_default }, + { "RETRY_OTHER_FAULT", 8, 8, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 9, 9, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 10, 10, &umr_bitfield_default }, + { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 11, 11, &umr_bitfield_default }, + { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT", 12, 12, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT", 13, 13, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_DEFAULT", 14, 14, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 17, 17, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 18, 18, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT", 19, 19, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_DEFAULT", 20, 20, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT", 21, 21, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT", 22, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT3_CNTL[] = { + { "ENABLE_CONTEXT", 0, 0, &umr_bitfield_default }, + { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default }, + { "PAGE_TABLE_BLOCK_SIZE", 3, 6, &umr_bitfield_default }, + { "RETRY_PERMISSION_OR_INVALID_PAGE_FAULT", 7, 7, &umr_bitfield_default }, + { "RETRY_OTHER_FAULT", 8, 8, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 9, 9, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 10, 10, &umr_bitfield_default }, + { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 11, 11, &umr_bitfield_default }, + { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT", 12, 12, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT", 13, 13, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_DEFAULT", 14, 14, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 17, 17, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 18, 18, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT", 19, 19, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_DEFAULT", 20, 20, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT", 21, 21, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT", 22, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT4_CNTL[] = { + { "ENABLE_CONTEXT", 0, 0, &umr_bitfield_default }, + { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default }, + { "PAGE_TABLE_BLOCK_SIZE", 3, 6, &umr_bitfield_default }, + { "RETRY_PERMISSION_OR_INVALID_PAGE_FAULT", 7, 7, &umr_bitfield_default }, + { "RETRY_OTHER_FAULT", 8, 8, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 9, 9, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 10, 10, &umr_bitfield_default }, + { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 11, 11, &umr_bitfield_default }, + { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT", 12, 12, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT", 13, 13, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_DEFAULT", 14, 14, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 17, 17, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 18, 18, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT", 19, 19, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_DEFAULT", 20, 20, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT", 21, 21, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT", 22, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT5_CNTL[] = { + { "ENABLE_CONTEXT", 0, 0, &umr_bitfield_default }, + { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default }, + { "PAGE_TABLE_BLOCK_SIZE", 3, 6, &umr_bitfield_default }, + { "RETRY_PERMISSION_OR_INVALID_PAGE_FAULT", 7, 7, &umr_bitfield_default }, + { "RETRY_OTHER_FAULT", 8, 8, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 9, 9, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 10, 10, &umr_bitfield_default }, + { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 11, 11, &umr_bitfield_default }, + { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT", 12, 12, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT", 13, 13, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_DEFAULT", 14, 14, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 17, 17, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 18, 18, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT", 19, 19, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_DEFAULT", 20, 20, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT", 21, 21, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT", 22, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT6_CNTL[] = { + { "ENABLE_CONTEXT", 0, 0, &umr_bitfield_default }, + { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default }, + { "PAGE_TABLE_BLOCK_SIZE", 3, 6, &umr_bitfield_default }, + { "RETRY_PERMISSION_OR_INVALID_PAGE_FAULT", 7, 7, &umr_bitfield_default }, + { "RETRY_OTHER_FAULT", 8, 8, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 9, 9, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 10, 10, &umr_bitfield_default }, + { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 11, 11, &umr_bitfield_default }, + { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT", 12, 12, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT", 13, 13, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_DEFAULT", 14, 14, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 17, 17, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 18, 18, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT", 19, 19, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_DEFAULT", 20, 20, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT", 21, 21, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT", 22, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT7_CNTL[] = { + { "ENABLE_CONTEXT", 0, 0, &umr_bitfield_default }, + { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default }, + { "PAGE_TABLE_BLOCK_SIZE", 3, 6, &umr_bitfield_default }, + { "RETRY_PERMISSION_OR_INVALID_PAGE_FAULT", 7, 7, &umr_bitfield_default }, + { "RETRY_OTHER_FAULT", 8, 8, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 9, 9, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 10, 10, &umr_bitfield_default }, + { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 11, 11, &umr_bitfield_default }, + { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT", 12, 12, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT", 13, 13, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_DEFAULT", 14, 14, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 17, 17, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 18, 18, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT", 19, 19, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_DEFAULT", 20, 20, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT", 21, 21, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT", 22, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT8_CNTL[] = { + { "ENABLE_CONTEXT", 0, 0, &umr_bitfield_default }, + { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default }, + { "PAGE_TABLE_BLOCK_SIZE", 3, 6, &umr_bitfield_default }, + { "RETRY_PERMISSION_OR_INVALID_PAGE_FAULT", 7, 7, &umr_bitfield_default }, + { "RETRY_OTHER_FAULT", 8, 8, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 9, 9, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 10, 10, &umr_bitfield_default }, + { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 11, 11, &umr_bitfield_default }, + { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT", 12, 12, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT", 13, 13, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_DEFAULT", 14, 14, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 17, 17, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 18, 18, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT", 19, 19, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_DEFAULT", 20, 20, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT", 21, 21, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT", 22, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT9_CNTL[] = { + { "ENABLE_CONTEXT", 0, 0, &umr_bitfield_default }, + { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default }, + { "PAGE_TABLE_BLOCK_SIZE", 3, 6, &umr_bitfield_default }, + { "RETRY_PERMISSION_OR_INVALID_PAGE_FAULT", 7, 7, &umr_bitfield_default }, + { "RETRY_OTHER_FAULT", 8, 8, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 9, 9, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 10, 10, &umr_bitfield_default }, + { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 11, 11, &umr_bitfield_default }, + { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT", 12, 12, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT", 13, 13, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_DEFAULT", 14, 14, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 17, 17, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 18, 18, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT", 19, 19, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_DEFAULT", 20, 20, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT", 21, 21, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT", 22, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT10_CNTL[] = { + { "ENABLE_CONTEXT", 0, 0, &umr_bitfield_default }, + { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default }, + { "PAGE_TABLE_BLOCK_SIZE", 3, 6, &umr_bitfield_default }, + { "RETRY_PERMISSION_OR_INVALID_PAGE_FAULT", 7, 7, &umr_bitfield_default }, + { "RETRY_OTHER_FAULT", 8, 8, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 9, 9, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 10, 10, &umr_bitfield_default }, + { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 11, 11, &umr_bitfield_default }, + { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT", 12, 12, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT", 13, 13, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_DEFAULT", 14, 14, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 17, 17, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 18, 18, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT", 19, 19, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_DEFAULT", 20, 20, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT", 21, 21, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT", 22, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT11_CNTL[] = { + { "ENABLE_CONTEXT", 0, 0, &umr_bitfield_default }, + { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default }, + { "PAGE_TABLE_BLOCK_SIZE", 3, 6, &umr_bitfield_default }, + { "RETRY_PERMISSION_OR_INVALID_PAGE_FAULT", 7, 7, &umr_bitfield_default }, + { "RETRY_OTHER_FAULT", 8, 8, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 9, 9, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 10, 10, &umr_bitfield_default }, + { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 11, 11, &umr_bitfield_default }, + { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT", 12, 12, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT", 13, 13, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_DEFAULT", 14, 14, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 17, 17, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 18, 18, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT", 19, 19, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_DEFAULT", 20, 20, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT", 21, 21, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT", 22, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT12_CNTL[] = { + { "ENABLE_CONTEXT", 0, 0, &umr_bitfield_default }, + { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default }, + { "PAGE_TABLE_BLOCK_SIZE", 3, 6, &umr_bitfield_default }, + { "RETRY_PERMISSION_OR_INVALID_PAGE_FAULT", 7, 7, &umr_bitfield_default }, + { "RETRY_OTHER_FAULT", 8, 8, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 9, 9, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 10, 10, &umr_bitfield_default }, + { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 11, 11, &umr_bitfield_default }, + { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT", 12, 12, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT", 13, 13, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_DEFAULT", 14, 14, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 17, 17, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 18, 18, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT", 19, 19, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_DEFAULT", 20, 20, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT", 21, 21, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT", 22, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT13_CNTL[] = { + { "ENABLE_CONTEXT", 0, 0, &umr_bitfield_default }, + { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default }, + { "PAGE_TABLE_BLOCK_SIZE", 3, 6, &umr_bitfield_default }, + { "RETRY_PERMISSION_OR_INVALID_PAGE_FAULT", 7, 7, &umr_bitfield_default }, + { "RETRY_OTHER_FAULT", 8, 8, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 9, 9, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 10, 10, &umr_bitfield_default }, + { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 11, 11, &umr_bitfield_default }, + { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT", 12, 12, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT", 13, 13, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_DEFAULT", 14, 14, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 17, 17, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 18, 18, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT", 19, 19, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_DEFAULT", 20, 20, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT", 21, 21, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT", 22, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT14_CNTL[] = { + { "ENABLE_CONTEXT", 0, 0, &umr_bitfield_default }, + { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default }, + { "PAGE_TABLE_BLOCK_SIZE", 3, 6, &umr_bitfield_default }, + { "RETRY_PERMISSION_OR_INVALID_PAGE_FAULT", 7, 7, &umr_bitfield_default }, + { "RETRY_OTHER_FAULT", 8, 8, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 9, 9, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 10, 10, &umr_bitfield_default }, + { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 11, 11, &umr_bitfield_default }, + { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT", 12, 12, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT", 13, 13, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_DEFAULT", 14, 14, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 17, 17, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 18, 18, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT", 19, 19, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_DEFAULT", 20, 20, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT", 21, 21, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT", 22, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT15_CNTL[] = { + { "ENABLE_CONTEXT", 0, 0, &umr_bitfield_default }, + { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default }, + { "PAGE_TABLE_BLOCK_SIZE", 3, 6, &umr_bitfield_default }, + { "RETRY_PERMISSION_OR_INVALID_PAGE_FAULT", 7, 7, &umr_bitfield_default }, + { "RETRY_OTHER_FAULT", 8, 8, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 9, 9, &umr_bitfield_default }, + { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 10, 10, &umr_bitfield_default }, + { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 11, 11, &umr_bitfield_default }, + { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT", 12, 12, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT", 13, 13, &umr_bitfield_default }, + { "PDE0_PROTECTION_FAULT_ENABLE_DEFAULT", 14, 14, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default }, + { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 17, 17, &umr_bitfield_default }, + { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 18, 18, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT", 19, 19, &umr_bitfield_default }, + { "WRITE_PROTECTION_FAULT_ENABLE_DEFAULT", 20, 20, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT", 21, 21, &umr_bitfield_default }, + { "EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT", 22, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXTS_DISABLE[] = { + { "DISABLE_CONTEXT_0", 0, 0, &umr_bitfield_default }, + { "DISABLE_CONTEXT_1", 1, 1, &umr_bitfield_default }, + { "DISABLE_CONTEXT_2", 2, 2, &umr_bitfield_default }, + { "DISABLE_CONTEXT_3", 3, 3, &umr_bitfield_default }, + { "DISABLE_CONTEXT_4", 4, 4, &umr_bitfield_default }, + { "DISABLE_CONTEXT_5", 5, 5, &umr_bitfield_default }, + { "DISABLE_CONTEXT_6", 6, 6, &umr_bitfield_default }, + { "DISABLE_CONTEXT_7", 7, 7, &umr_bitfield_default }, + { "DISABLE_CONTEXT_8", 8, 8, &umr_bitfield_default }, + { "DISABLE_CONTEXT_9", 9, 9, &umr_bitfield_default }, + { "DISABLE_CONTEXT_10", 10, 10, &umr_bitfield_default }, + { "DISABLE_CONTEXT_11", 11, 11, &umr_bitfield_default }, + { "DISABLE_CONTEXT_12", 12, 12, &umr_bitfield_default }, + { "DISABLE_CONTEXT_13", 13, 13, &umr_bitfield_default }, + { "DISABLE_CONTEXT_14", 14, 14, &umr_bitfield_default }, + { "DISABLE_CONTEXT_15", 15, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG0_SEM[] = { + { "SEMAPHORE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG1_SEM[] = { + { "SEMAPHORE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG2_SEM[] = { + { "SEMAPHORE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG3_SEM[] = { + { "SEMAPHORE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG4_SEM[] = { + { "SEMAPHORE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG5_SEM[] = { + { "SEMAPHORE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG6_SEM[] = { + { "SEMAPHORE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG7_SEM[] = { + { "SEMAPHORE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG8_SEM[] = { + { "SEMAPHORE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG9_SEM[] = { + { "SEMAPHORE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG10_SEM[] = { + { "SEMAPHORE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG11_SEM[] = { + { "SEMAPHORE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG12_SEM[] = { + { "SEMAPHORE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG13_SEM[] = { + { "SEMAPHORE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG14_SEM[] = { + { "SEMAPHORE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG15_SEM[] = { + { "SEMAPHORE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG16_SEM[] = { + { "SEMAPHORE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG17_SEM[] = { + { "SEMAPHORE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG0_REQ[] = { + { "PER_VMID_INVALIDATE_REQ", 0, 15, &umr_bitfield_default }, + { "FLUSH_TYPE", 16, 17, &umr_bitfield_default }, + { "INVALIDATE_L2_PTES", 18, 18, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE0", 19, 19, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE1", 20, 20, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE2", 21, 21, &umr_bitfield_default }, + { "INVALIDATE_L1_PTES", 22, 22, &umr_bitfield_default }, + { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG1_REQ[] = { + { "PER_VMID_INVALIDATE_REQ", 0, 15, &umr_bitfield_default }, + { "FLUSH_TYPE", 16, 17, &umr_bitfield_default }, + { "INVALIDATE_L2_PTES", 18, 18, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE0", 19, 19, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE1", 20, 20, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE2", 21, 21, &umr_bitfield_default }, + { "INVALIDATE_L1_PTES", 22, 22, &umr_bitfield_default }, + { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG2_REQ[] = { + { "PER_VMID_INVALIDATE_REQ", 0, 15, &umr_bitfield_default }, + { "FLUSH_TYPE", 16, 17, &umr_bitfield_default }, + { "INVALIDATE_L2_PTES", 18, 18, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE0", 19, 19, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE1", 20, 20, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE2", 21, 21, &umr_bitfield_default }, + { "INVALIDATE_L1_PTES", 22, 22, &umr_bitfield_default }, + { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG3_REQ[] = { + { "PER_VMID_INVALIDATE_REQ", 0, 15, &umr_bitfield_default }, + { "FLUSH_TYPE", 16, 17, &umr_bitfield_default }, + { "INVALIDATE_L2_PTES", 18, 18, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE0", 19, 19, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE1", 20, 20, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE2", 21, 21, &umr_bitfield_default }, + { "INVALIDATE_L1_PTES", 22, 22, &umr_bitfield_default }, + { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG4_REQ[] = { + { "PER_VMID_INVALIDATE_REQ", 0, 15, &umr_bitfield_default }, + { "FLUSH_TYPE", 16, 17, &umr_bitfield_default }, + { "INVALIDATE_L2_PTES", 18, 18, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE0", 19, 19, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE1", 20, 20, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE2", 21, 21, &umr_bitfield_default }, + { "INVALIDATE_L1_PTES", 22, 22, &umr_bitfield_default }, + { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG5_REQ[] = { + { "PER_VMID_INVALIDATE_REQ", 0, 15, &umr_bitfield_default }, + { "FLUSH_TYPE", 16, 17, &umr_bitfield_default }, + { "INVALIDATE_L2_PTES", 18, 18, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE0", 19, 19, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE1", 20, 20, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE2", 21, 21, &umr_bitfield_default }, + { "INVALIDATE_L1_PTES", 22, 22, &umr_bitfield_default }, + { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG6_REQ[] = { + { "PER_VMID_INVALIDATE_REQ", 0, 15, &umr_bitfield_default }, + { "FLUSH_TYPE", 16, 17, &umr_bitfield_default }, + { "INVALIDATE_L2_PTES", 18, 18, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE0", 19, 19, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE1", 20, 20, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE2", 21, 21, &umr_bitfield_default }, + { "INVALIDATE_L1_PTES", 22, 22, &umr_bitfield_default }, + { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG7_REQ[] = { + { "PER_VMID_INVALIDATE_REQ", 0, 15, &umr_bitfield_default }, + { "FLUSH_TYPE", 16, 17, &umr_bitfield_default }, + { "INVALIDATE_L2_PTES", 18, 18, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE0", 19, 19, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE1", 20, 20, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE2", 21, 21, &umr_bitfield_default }, + { "INVALIDATE_L1_PTES", 22, 22, &umr_bitfield_default }, + { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG8_REQ[] = { + { "PER_VMID_INVALIDATE_REQ", 0, 15, &umr_bitfield_default }, + { "FLUSH_TYPE", 16, 17, &umr_bitfield_default }, + { "INVALIDATE_L2_PTES", 18, 18, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE0", 19, 19, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE1", 20, 20, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE2", 21, 21, &umr_bitfield_default }, + { "INVALIDATE_L1_PTES", 22, 22, &umr_bitfield_default }, + { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG9_REQ[] = { + { "PER_VMID_INVALIDATE_REQ", 0, 15, &umr_bitfield_default }, + { "FLUSH_TYPE", 16, 17, &umr_bitfield_default }, + { "INVALIDATE_L2_PTES", 18, 18, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE0", 19, 19, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE1", 20, 20, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE2", 21, 21, &umr_bitfield_default }, + { "INVALIDATE_L1_PTES", 22, 22, &umr_bitfield_default }, + { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG10_REQ[] = { + { "PER_VMID_INVALIDATE_REQ", 0, 15, &umr_bitfield_default }, + { "FLUSH_TYPE", 16, 17, &umr_bitfield_default }, + { "INVALIDATE_L2_PTES", 18, 18, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE0", 19, 19, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE1", 20, 20, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE2", 21, 21, &umr_bitfield_default }, + { "INVALIDATE_L1_PTES", 22, 22, &umr_bitfield_default }, + { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG11_REQ[] = { + { "PER_VMID_INVALIDATE_REQ", 0, 15, &umr_bitfield_default }, + { "FLUSH_TYPE", 16, 17, &umr_bitfield_default }, + { "INVALIDATE_L2_PTES", 18, 18, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE0", 19, 19, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE1", 20, 20, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE2", 21, 21, &umr_bitfield_default }, + { "INVALIDATE_L1_PTES", 22, 22, &umr_bitfield_default }, + { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG12_REQ[] = { + { "PER_VMID_INVALIDATE_REQ", 0, 15, &umr_bitfield_default }, + { "FLUSH_TYPE", 16, 17, &umr_bitfield_default }, + { "INVALIDATE_L2_PTES", 18, 18, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE0", 19, 19, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE1", 20, 20, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE2", 21, 21, &umr_bitfield_default }, + { "INVALIDATE_L1_PTES", 22, 22, &umr_bitfield_default }, + { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG13_REQ[] = { + { "PER_VMID_INVALIDATE_REQ", 0, 15, &umr_bitfield_default }, + { "FLUSH_TYPE", 16, 17, &umr_bitfield_default }, + { "INVALIDATE_L2_PTES", 18, 18, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE0", 19, 19, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE1", 20, 20, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE2", 21, 21, &umr_bitfield_default }, + { "INVALIDATE_L1_PTES", 22, 22, &umr_bitfield_default }, + { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG14_REQ[] = { + { "PER_VMID_INVALIDATE_REQ", 0, 15, &umr_bitfield_default }, + { "FLUSH_TYPE", 16, 17, &umr_bitfield_default }, + { "INVALIDATE_L2_PTES", 18, 18, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE0", 19, 19, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE1", 20, 20, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE2", 21, 21, &umr_bitfield_default }, + { "INVALIDATE_L1_PTES", 22, 22, &umr_bitfield_default }, + { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG15_REQ[] = { + { "PER_VMID_INVALIDATE_REQ", 0, 15, &umr_bitfield_default }, + { "FLUSH_TYPE", 16, 17, &umr_bitfield_default }, + { "INVALIDATE_L2_PTES", 18, 18, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE0", 19, 19, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE1", 20, 20, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE2", 21, 21, &umr_bitfield_default }, + { "INVALIDATE_L1_PTES", 22, 22, &umr_bitfield_default }, + { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG16_REQ[] = { + { "PER_VMID_INVALIDATE_REQ", 0, 15, &umr_bitfield_default }, + { "FLUSH_TYPE", 16, 17, &umr_bitfield_default }, + { "INVALIDATE_L2_PTES", 18, 18, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE0", 19, 19, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE1", 20, 20, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE2", 21, 21, &umr_bitfield_default }, + { "INVALIDATE_L1_PTES", 22, 22, &umr_bitfield_default }, + { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG17_REQ[] = { + { "PER_VMID_INVALIDATE_REQ", 0, 15, &umr_bitfield_default }, + { "FLUSH_TYPE", 16, 17, &umr_bitfield_default }, + { "INVALIDATE_L2_PTES", 18, 18, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE0", 19, 19, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE1", 20, 20, &umr_bitfield_default }, + { "INVALIDATE_L2_PDE2", 21, 21, &umr_bitfield_default }, + { "INVALIDATE_L1_PTES", 22, 22, &umr_bitfield_default }, + { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG0_ACK[] = { + { "PER_VMID_INVALIDATE_ACK", 0, 15, &umr_bitfield_default }, + { "SEMAPHORE", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG1_ACK[] = { + { "PER_VMID_INVALIDATE_ACK", 0, 15, &umr_bitfield_default }, + { "SEMAPHORE", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG2_ACK[] = { + { "PER_VMID_INVALIDATE_ACK", 0, 15, &umr_bitfield_default }, + { "SEMAPHORE", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG3_ACK[] = { + { "PER_VMID_INVALIDATE_ACK", 0, 15, &umr_bitfield_default }, + { "SEMAPHORE", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG4_ACK[] = { + { "PER_VMID_INVALIDATE_ACK", 0, 15, &umr_bitfield_default }, + { "SEMAPHORE", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG5_ACK[] = { + { "PER_VMID_INVALIDATE_ACK", 0, 15, &umr_bitfield_default }, + { "SEMAPHORE", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG6_ACK[] = { + { "PER_VMID_INVALIDATE_ACK", 0, 15, &umr_bitfield_default }, + { "SEMAPHORE", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG7_ACK[] = { + { "PER_VMID_INVALIDATE_ACK", 0, 15, &umr_bitfield_default }, + { "SEMAPHORE", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG8_ACK[] = { + { "PER_VMID_INVALIDATE_ACK", 0, 15, &umr_bitfield_default }, + { "SEMAPHORE", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG9_ACK[] = { + { "PER_VMID_INVALIDATE_ACK", 0, 15, &umr_bitfield_default }, + { "SEMAPHORE", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG10_ACK[] = { + { "PER_VMID_INVALIDATE_ACK", 0, 15, &umr_bitfield_default }, + { "SEMAPHORE", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG11_ACK[] = { + { "PER_VMID_INVALIDATE_ACK", 0, 15, &umr_bitfield_default }, + { "SEMAPHORE", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG12_ACK[] = { + { "PER_VMID_INVALIDATE_ACK", 0, 15, &umr_bitfield_default }, + { "SEMAPHORE", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG13_ACK[] = { + { "PER_VMID_INVALIDATE_ACK", 0, 15, &umr_bitfield_default }, + { "SEMAPHORE", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG14_ACK[] = { + { "PER_VMID_INVALIDATE_ACK", 0, 15, &umr_bitfield_default }, + { "SEMAPHORE", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG15_ACK[] = { + { "PER_VMID_INVALIDATE_ACK", 0, 15, &umr_bitfield_default }, + { "SEMAPHORE", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG16_ACK[] = { + { "PER_VMID_INVALIDATE_ACK", 0, 15, &umr_bitfield_default }, + { "SEMAPHORE", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG17_ACK[] = { + { "PER_VMID_INVALIDATE_ACK", 0, 15, &umr_bitfield_default }, + { "SEMAPHORE", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32[] = { + { "S_BIT", 0, 0, &umr_bitfield_default }, + { "LOGI_PAGE_ADDR_RANGE_LO31", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32[] = { + { "LOGI_PAGE_ADDR_RANGE_HI5", 0, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32[] = { + { "S_BIT", 0, 0, &umr_bitfield_default }, + { "LOGI_PAGE_ADDR_RANGE_LO31", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG1_ADDR_RANGE_HI32[] = { + { "LOGI_PAGE_ADDR_RANGE_HI5", 0, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG2_ADDR_RANGE_LO32[] = { + { "S_BIT", 0, 0, &umr_bitfield_default }, + { "LOGI_PAGE_ADDR_RANGE_LO31", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG2_ADDR_RANGE_HI32[] = { + { "LOGI_PAGE_ADDR_RANGE_HI5", 0, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG3_ADDR_RANGE_LO32[] = { + { "S_BIT", 0, 0, &umr_bitfield_default }, + { "LOGI_PAGE_ADDR_RANGE_LO31", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG3_ADDR_RANGE_HI32[] = { + { "LOGI_PAGE_ADDR_RANGE_HI5", 0, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG4_ADDR_RANGE_LO32[] = { + { "S_BIT", 0, 0, &umr_bitfield_default }, + { "LOGI_PAGE_ADDR_RANGE_LO31", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG4_ADDR_RANGE_HI32[] = { + { "LOGI_PAGE_ADDR_RANGE_HI5", 0, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG5_ADDR_RANGE_LO32[] = { + { "S_BIT", 0, 0, &umr_bitfield_default }, + { "LOGI_PAGE_ADDR_RANGE_LO31", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG5_ADDR_RANGE_HI32[] = { + { "LOGI_PAGE_ADDR_RANGE_HI5", 0, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG6_ADDR_RANGE_LO32[] = { + { "S_BIT", 0, 0, &umr_bitfield_default }, + { "LOGI_PAGE_ADDR_RANGE_LO31", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG6_ADDR_RANGE_HI32[] = { + { "LOGI_PAGE_ADDR_RANGE_HI5", 0, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG7_ADDR_RANGE_LO32[] = { + { "S_BIT", 0, 0, &umr_bitfield_default }, + { "LOGI_PAGE_ADDR_RANGE_LO31", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG7_ADDR_RANGE_HI32[] = { + { "LOGI_PAGE_ADDR_RANGE_HI5", 0, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG8_ADDR_RANGE_LO32[] = { + { "S_BIT", 0, 0, &umr_bitfield_default }, + { "LOGI_PAGE_ADDR_RANGE_LO31", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG8_ADDR_RANGE_HI32[] = { + { "LOGI_PAGE_ADDR_RANGE_HI5", 0, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG9_ADDR_RANGE_LO32[] = { + { "S_BIT", 0, 0, &umr_bitfield_default }, + { "LOGI_PAGE_ADDR_RANGE_LO31", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG9_ADDR_RANGE_HI32[] = { + { "LOGI_PAGE_ADDR_RANGE_HI5", 0, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG10_ADDR_RANGE_LO32[] = { + { "S_BIT", 0, 0, &umr_bitfield_default }, + { "LOGI_PAGE_ADDR_RANGE_LO31", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG10_ADDR_RANGE_HI32[] = { + { "LOGI_PAGE_ADDR_RANGE_HI5", 0, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG11_ADDR_RANGE_LO32[] = { + { "S_BIT", 0, 0, &umr_bitfield_default }, + { "LOGI_PAGE_ADDR_RANGE_LO31", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG11_ADDR_RANGE_HI32[] = { + { "LOGI_PAGE_ADDR_RANGE_HI5", 0, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG12_ADDR_RANGE_LO32[] = { + { "S_BIT", 0, 0, &umr_bitfield_default }, + { "LOGI_PAGE_ADDR_RANGE_LO31", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG12_ADDR_RANGE_HI32[] = { + { "LOGI_PAGE_ADDR_RANGE_HI5", 0, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG13_ADDR_RANGE_LO32[] = { + { "S_BIT", 0, 0, &umr_bitfield_default }, + { "LOGI_PAGE_ADDR_RANGE_LO31", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG13_ADDR_RANGE_HI32[] = { + { "LOGI_PAGE_ADDR_RANGE_HI5", 0, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG14_ADDR_RANGE_LO32[] = { + { "S_BIT", 0, 0, &umr_bitfield_default }, + { "LOGI_PAGE_ADDR_RANGE_LO31", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG14_ADDR_RANGE_HI32[] = { + { "LOGI_PAGE_ADDR_RANGE_HI5", 0, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG15_ADDR_RANGE_LO32[] = { + { "S_BIT", 0, 0, &umr_bitfield_default }, + { "LOGI_PAGE_ADDR_RANGE_LO31", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG15_ADDR_RANGE_HI32[] = { + { "LOGI_PAGE_ADDR_RANGE_HI5", 0, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG16_ADDR_RANGE_LO32[] = { + { "S_BIT", 0, 0, &umr_bitfield_default }, + { "LOGI_PAGE_ADDR_RANGE_LO31", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG16_ADDR_RANGE_HI32[] = { + { "LOGI_PAGE_ADDR_RANGE_HI5", 0, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG17_ADDR_RANGE_LO32[] = { + { "S_BIT", 0, 0, &umr_bitfield_default }, + { "LOGI_PAGE_ADDR_RANGE_LO31", 1, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_INVALIDATE_ENG17_ADDR_RANGE_HI32[] = { + { "LOGI_PAGE_ADDR_RANGE_HI5", 0, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32[] = { + { "PAGE_DIRECTORY_ENTRY_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32[] = { + { "PAGE_DIRECTORY_ENTRY_HI32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32[] = { + { "PAGE_DIRECTORY_ENTRY_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32[] = { + { "PAGE_DIRECTORY_ENTRY_HI32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32[] = { + { "PAGE_DIRECTORY_ENTRY_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32[] = { + { "PAGE_DIRECTORY_ENTRY_HI32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32[] = { + { "PAGE_DIRECTORY_ENTRY_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32[] = { + { "PAGE_DIRECTORY_ENTRY_HI32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32[] = { + { "PAGE_DIRECTORY_ENTRY_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32[] = { + { "PAGE_DIRECTORY_ENTRY_HI32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32[] = { + { "PAGE_DIRECTORY_ENTRY_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32[] = { + { "PAGE_DIRECTORY_ENTRY_HI32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32[] = { + { "PAGE_DIRECTORY_ENTRY_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32[] = { + { "PAGE_DIRECTORY_ENTRY_HI32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32[] = { + { "PAGE_DIRECTORY_ENTRY_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32[] = { + { "PAGE_DIRECTORY_ENTRY_HI32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32[] = { + { "PAGE_DIRECTORY_ENTRY_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32[] = { + { "PAGE_DIRECTORY_ENTRY_HI32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32[] = { + { "PAGE_DIRECTORY_ENTRY_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32[] = { + { "PAGE_DIRECTORY_ENTRY_HI32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32[] = { + { "PAGE_DIRECTORY_ENTRY_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32[] = { + { "PAGE_DIRECTORY_ENTRY_HI32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32[] = { + { "PAGE_DIRECTORY_ENTRY_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32[] = { + { "PAGE_DIRECTORY_ENTRY_HI32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32[] = { + { "PAGE_DIRECTORY_ENTRY_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32[] = { + { "PAGE_DIRECTORY_ENTRY_HI32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32[] = { + { "PAGE_DIRECTORY_ENTRY_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32[] = { + { "PAGE_DIRECTORY_ENTRY_HI32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32[] = { + { "PAGE_DIRECTORY_ENTRY_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32[] = { + { "PAGE_DIRECTORY_ENTRY_HI32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32[] = { + { "PAGE_DIRECTORY_ENTRY_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32[] = { + { "PAGE_DIRECTORY_ENTRY_HI32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32[] = { + { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32[] = { + { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_L2_PERFCOUNTER0_CFG[] = { + { "PERF_SEL", 0, 7, &umr_bitfield_default }, + { "PERF_SEL_END", 8, 15, &umr_bitfield_default }, + { "PERF_MODE", 24, 27, &umr_bitfield_default }, + { "ENABLE", 28, 28, &umr_bitfield_default }, + { "CLEAR", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_L2_PERFCOUNTER1_CFG[] = { + { "PERF_SEL", 0, 7, &umr_bitfield_default }, + { "PERF_SEL_END", 8, 15, &umr_bitfield_default }, + { "PERF_MODE", 24, 27, &umr_bitfield_default }, + { "ENABLE", 28, 28, &umr_bitfield_default }, + { "CLEAR", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_L2_PERFCOUNTER2_CFG[] = { + { "PERF_SEL", 0, 7, &umr_bitfield_default }, + { "PERF_SEL_END", 8, 15, &umr_bitfield_default }, + { "PERF_MODE", 24, 27, &umr_bitfield_default }, + { "ENABLE", 28, 28, &umr_bitfield_default }, + { "CLEAR", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_L2_PERFCOUNTER3_CFG[] = { + { "PERF_SEL", 0, 7, &umr_bitfield_default }, + { "PERF_SEL_END", 8, 15, &umr_bitfield_default }, + { "PERF_MODE", 24, 27, &umr_bitfield_default }, + { "ENABLE", 28, 28, &umr_bitfield_default }, + { "CLEAR", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_L2_PERFCOUNTER4_CFG[] = { + { "PERF_SEL", 0, 7, &umr_bitfield_default }, + { "PERF_SEL_END", 8, 15, &umr_bitfield_default }, + { "PERF_MODE", 24, 27, &umr_bitfield_default }, + { "ENABLE", 28, 28, &umr_bitfield_default }, + { "CLEAR", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_L2_PERFCOUNTER5_CFG[] = { + { "PERF_SEL", 0, 7, &umr_bitfield_default }, + { "PERF_SEL_END", 8, 15, &umr_bitfield_default }, + { "PERF_MODE", 24, 27, &umr_bitfield_default }, + { "ENABLE", 28, 28, &umr_bitfield_default }, + { "CLEAR", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_L2_PERFCOUNTER6_CFG[] = { + { "PERF_SEL", 0, 7, &umr_bitfield_default }, + { "PERF_SEL_END", 8, 15, &umr_bitfield_default }, + { "PERF_MODE", 24, 27, &umr_bitfield_default }, + { "ENABLE", 28, 28, &umr_bitfield_default }, + { "CLEAR", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_L2_PERFCOUNTER7_CFG[] = { + { "PERF_SEL", 0, 7, &umr_bitfield_default }, + { "PERF_SEL_END", 8, 15, &umr_bitfield_default }, + { "PERF_MODE", 24, 27, &umr_bitfield_default }, + { "ENABLE", 28, 28, &umr_bitfield_default }, + { "CLEAR", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL[] = { + { "PERF_COUNTER_SELECT", 0, 3, &umr_bitfield_default }, + { "START_TRIGGER", 8, 15, &umr_bitfield_default }, + { "STOP_TRIGGER", 16, 23, &umr_bitfield_default }, + { "ENABLE_ANY", 24, 24, &umr_bitfield_default }, + { "CLEAR_ALL", 25, 25, &umr_bitfield_default }, + { "STOP_ALL_ON_SATURATE", 26, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_L2_PERFCOUNTER_LO[] = { + { "COUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_L2_PERFCOUNTER_HI[] = { + { "COUNTER_HI", 0, 15, &umr_bitfield_default }, + { "COMPARE_VALUE", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF0[] = { + { "VF_FB_SIZE", 0, 15, &umr_bitfield_default }, + { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF1[] = { + { "VF_FB_SIZE", 0, 15, &umr_bitfield_default }, + { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF2[] = { + { "VF_FB_SIZE", 0, 15, &umr_bitfield_default }, + { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF3[] = { + { "VF_FB_SIZE", 0, 15, &umr_bitfield_default }, + { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF4[] = { + { "VF_FB_SIZE", 0, 15, &umr_bitfield_default }, + { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF5[] = { + { "VF_FB_SIZE", 0, 15, &umr_bitfield_default }, + { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF6[] = { + { "VF_FB_SIZE", 0, 15, &umr_bitfield_default }, + { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF7[] = { + { "VF_FB_SIZE", 0, 15, &umr_bitfield_default }, + { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF8[] = { + { "VF_FB_SIZE", 0, 15, &umr_bitfield_default }, + { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF9[] = { + { "VF_FB_SIZE", 0, 15, &umr_bitfield_default }, + { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF10[] = { + { "VF_FB_SIZE", 0, 15, &umr_bitfield_default }, + { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF11[] = { + { "VF_FB_SIZE", 0, 15, &umr_bitfield_default }, + { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF12[] = { + { "VF_FB_SIZE", 0, 15, &umr_bitfield_default }, + { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF13[] = { + { "VF_FB_SIZE", 0, 15, &umr_bitfield_default }, + { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF14[] = { + { "VF_FB_SIZE", 0, 15, &umr_bitfield_default }, + { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF15[] = { + { "VF_FB_SIZE", 0, 15, &umr_bitfield_default }, + { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_IOMMU_MMIO_CNTRL_1[] = { + { "MARC_EN", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_MARC_BASE_LO_0[] = { + { "MARC_BASE_LO_0", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_MARC_BASE_LO_1[] = { + { "MARC_BASE_LO_1", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_MARC_BASE_LO_2[] = { + { "MARC_BASE_LO_2", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_MARC_BASE_LO_3[] = { + { "MARC_BASE_LO_3", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_MARC_BASE_HI_0[] = { + { "MARC_BASE_HI_0", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_MARC_BASE_HI_1[] = { + { "MARC_BASE_HI_1", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_MARC_BASE_HI_2[] = { + { "MARC_BASE_HI_2", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_MARC_BASE_HI_3[] = { + { "MARC_BASE_HI_3", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_MARC_RELOC_LO_0[] = { + { "MARC_ENABLE_0", 0, 0, &umr_bitfield_default }, + { "MARC_READONLY_0", 1, 1, &umr_bitfield_default }, + { "MARC_RELOC_LO_0", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_MARC_RELOC_LO_1[] = { + { "MARC_ENABLE_1", 0, 0, &umr_bitfield_default }, + { "MARC_READONLY_1", 1, 1, &umr_bitfield_default }, + { "MARC_RELOC_LO_1", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_MARC_RELOC_LO_2[] = { + { "MARC_ENABLE_2", 0, 0, &umr_bitfield_default }, + { "MARC_READONLY_2", 1, 1, &umr_bitfield_default }, + { "MARC_RELOC_LO_2", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_MARC_RELOC_LO_3[] = { + { "MARC_ENABLE_3", 0, 0, &umr_bitfield_default }, + { "MARC_READONLY_3", 1, 1, &umr_bitfield_default }, + { "MARC_RELOC_LO_3", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_MARC_RELOC_HI_0[] = { + { "MARC_RELOC_HI_0", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_MARC_RELOC_HI_1[] = { + { "MARC_RELOC_HI_1", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_MARC_RELOC_HI_2[] = { + { "MARC_RELOC_HI_2", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_MARC_RELOC_HI_3[] = { + { "MARC_RELOC_HI_3", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_MARC_LEN_LO_0[] = { + { "MARC_LEN_LO_0", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_MARC_LEN_LO_1[] = { + { "MARC_LEN_LO_1", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_MARC_LEN_LO_2[] = { + { "MARC_LEN_LO_2", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_MARC_LEN_LO_3[] = { + { "MARC_LEN_LO_3", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_MARC_LEN_HI_0[] = { + { "MARC_LEN_HI_0", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_MARC_LEN_HI_1[] = { + { "MARC_LEN_HI_1", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_MARC_LEN_HI_2[] = { + { "MARC_LEN_HI_2", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_MARC_LEN_HI_3[] = { + { "MARC_LEN_HI_3", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_IOMMU_CONTROL_REGISTER[] = { + { "IOMMUEN", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER[] = { + { "PERFOPTEN", 13, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_PCIE_ATS_CNTL[] = { + { "STU", 16, 20, &umr_bitfield_default }, + { "ATC_ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_PCIE_ATS_CNTL_VF_0[] = { + { "ATC_ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_PCIE_ATS_CNTL_VF_1[] = { + { "ATC_ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_PCIE_ATS_CNTL_VF_2[] = { + { "ATC_ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_PCIE_ATS_CNTL_VF_3[] = { + { "ATC_ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_PCIE_ATS_CNTL_VF_4[] = { + { "ATC_ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_PCIE_ATS_CNTL_VF_5[] = { + { "ATC_ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_PCIE_ATS_CNTL_VF_6[] = { + { "ATC_ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_PCIE_ATS_CNTL_VF_7[] = { + { "ATC_ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_PCIE_ATS_CNTL_VF_8[] = { + { "ATC_ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_PCIE_ATS_CNTL_VF_9[] = { + { "ATC_ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_PCIE_ATS_CNTL_VF_10[] = { + { "ATC_ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_PCIE_ATS_CNTL_VF_11[] = { + { "ATC_ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_PCIE_ATS_CNTL_VF_12[] = { + { "ATC_ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_PCIE_ATS_CNTL_VF_13[] = { + { "ATC_ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_PCIE_ATS_CNTL_VF_14[] = { + { "ATC_ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmVM_PCIE_ATS_CNTL_VF_15[] = { + { "ATC_ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUTCL2_CGTT_CLK_CTRL[] = { + { "ON_DELAY", 0, 3, &umr_bitfield_default }, + { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default }, + { "SOFT_OVERRIDE_EXTRA", 12, 14, &umr_bitfield_default }, + { "MGLS_OVERRIDE", 15, 15, &umr_bitfield_default }, + { "SOFT_STALL_OVERRIDE", 16, 23, &umr_bitfield_default }, + { "SOFT_OVERRIDE", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_NB_MMIOBASE[] = { + { "MMIOBASE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_NB_MMIOLIMIT[] = { + { "MMIOLIMIT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_NB_PCI_CTRL[] = { + { "MMIOENABLE", 23, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_NB_PCI_ARB[] = { + { "VGA_HOLE", 3, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_NB_TOP_OF_DRAM_SLOT1[] = { + { "TOP_OF_DRAM", 23, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_NB_LOWER_TOP_OF_DRAM2[] = { + { "ENABLE", 0, 0, &umr_bitfield_default }, + { "LOWER_TOM2", 23, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_NB_UPPER_TOP_OF_DRAM2[] = { + { "UPPER_TOM2", 0, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_FB_OFFSET[] = { + { "FB_OFFSET", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB[] = { + { "PHYSICAL_PAGE_NUMBER_LSB", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB[] = { + { "PHYSICAL_PAGE_NUMBER_MSB", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_STEERING[] = { + { "DEFAULT_STEERING", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_SHARED_VIRT_RESET_REQ[] = { + { "VF", 0, 15, &umr_bitfield_default }, + { "PF", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_MEM_POWER_LS[] = { + { "LS_SETUP", 0, 5, &umr_bitfield_default }, + { "LS_HOLD", 6, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_CACHEABLE_DRAM_ADDRESS_START[] = { + { "ADDRESS", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_CACHEABLE_DRAM_ADDRESS_END[] = { + { "ADDRESS", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_APT_CNTL[] = { + { "FORCE_MTYPE_UC", 0, 0, &umr_bitfield_default }, + { "DIRECT_SYSTEM_EN", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_LOCAL_HBM_ADDRESS_START[] = { + { "ADDRESS", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_LOCAL_HBM_ADDRESS_END[] = { + { "ADDRESS", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL[] = { + { "LOCK", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_FB_LOCATION_BASE[] = { + { "FB_BASE", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_FB_LOCATION_TOP[] = { + { "FB_TOP", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_AGP_TOP[] = { + { "AGP_TOP", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_AGP_BOT[] = { + { "AGP_BOT", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_AGP_BASE[] = { + { "AGP_BASE", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_SYSTEM_APERTURE_LOW_ADDR[] = { + { "LOGICAL_ADDR", 0, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR[] = { + { "LOGICAL_ADDR", 0, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMC_VM_MX_L1_TLB_CNTL[] = { + { "ENABLE_L1_TLB", 0, 0, &umr_bitfield_default }, + { "SYSTEM_ACCESS_MODE", 3, 4, &umr_bitfield_default }, + { "SYSTEM_APERTURE_UNMAPPED_ACCESS", 5, 5, &umr_bitfield_default }, + { "ENABLE_ADVANCED_DRIVER_MODEL", 6, 6, &umr_bitfield_default }, + { "ECO_BITS", 7, 10, &umr_bitfield_default }, + { "MTYPE", 11, 12, &umr_bitfield_default }, + { "ATC_EN", 13, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmATC_L2_PERFCOUNTER_LO[] = { + { "COUNTER_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmATC_L2_PERFCOUNTER_HI[] = { + { "COUNTER_HI", 0, 15, &umr_bitfield_default }, + { "COMPARE_VALUE", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmATC_L2_PERFCOUNTER0_CFG[] = { + { "PERF_SEL", 0, 7, &umr_bitfield_default }, + { "PERF_SEL_END", 8, 15, &umr_bitfield_default }, + { "PERF_MODE", 24, 27, &umr_bitfield_default }, + { "ENABLE", 28, 28, &umr_bitfield_default }, + { "CLEAR", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmATC_L2_PERFCOUNTER1_CFG[] = { + { "PERF_SEL", 0, 7, &umr_bitfield_default }, + { "PERF_SEL_END", 8, 15, &umr_bitfield_default }, + { "PERF_MODE", 24, 27, &umr_bitfield_default }, + { "ENABLE", 28, 28, &umr_bitfield_default }, + { "CLEAR", 29, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmATC_L2_PERFCOUNTER_RSLT_CNTL[] = { + { "PERF_COUNTER_SELECT", 0, 3, &umr_bitfield_default }, + { "START_TRIGGER", 8, 15, &umr_bitfield_default }, + { "STOP_TRIGGER", 16, 23, &umr_bitfield_default }, + { "ENABLE_ANY", 24, 24, &umr_bitfield_default }, + { "CLEAR_ALL", 25, 25, &umr_bitfield_default }, + { "STOP_ALL_ON_SATURATE", 26, 26, &umr_bitfield_default }, +}; diff --git a/src/lib/ip/mmhub91_regs.i b/src/lib/ip/mmhub91_regs.i new file mode 100644 index 0000000..cf2a79e --- /dev/null +++ b/src/lib/ip/mmhub91_regs.i @@ -0,0 +1,953 @@ + { "mmDAGB0_RDCLI0", REG_MMIO, 0x0000, 0, &mmDAGB0_RDCLI0[0], sizeof(mmDAGB0_RDCLI0)/sizeof(mmDAGB0_RDCLI0[0]), 0, 0 }, + { "mmDAGB0_RDCLI1", REG_MMIO, 0x0001, 0, &mmDAGB0_RDCLI1[0], sizeof(mmDAGB0_RDCLI1)/sizeof(mmDAGB0_RDCLI1[0]), 0, 0 }, + { "mmDAGB0_RDCLI2", REG_MMIO, 0x0002, 0, &mmDAGB0_RDCLI2[0], sizeof(mmDAGB0_RDCLI2)/sizeof(mmDAGB0_RDCLI2[0]), 0, 0 }, + { "mmDAGB0_RDCLI3", REG_MMIO, 0x0003, 0, &mmDAGB0_RDCLI3[0], sizeof(mmDAGB0_RDCLI3)/sizeof(mmDAGB0_RDCLI3[0]), 0, 0 }, + { "mmDAGB0_RDCLI4", REG_MMIO, 0x0004, 0, &mmDAGB0_RDCLI4[0], sizeof(mmDAGB0_RDCLI4)/sizeof(mmDAGB0_RDCLI4[0]), 0, 0 }, + { "mmDAGB0_RDCLI5", REG_MMIO, 0x0005, 0, &mmDAGB0_RDCLI5[0], sizeof(mmDAGB0_RDCLI5)/sizeof(mmDAGB0_RDCLI5[0]), 0, 0 }, + { "mmDAGB0_RDCLI6", REG_MMIO, 0x0006, 0, &mmDAGB0_RDCLI6[0], sizeof(mmDAGB0_RDCLI6)/sizeof(mmDAGB0_RDCLI6[0]), 0, 0 }, + { "mmDAGB0_RDCLI7", REG_MMIO, 0x0007, 0, &mmDAGB0_RDCLI7[0], sizeof(mmDAGB0_RDCLI7)/sizeof(mmDAGB0_RDCLI7[0]), 0, 0 }, + { "mmDAGB0_RDCLI8", REG_MMIO, 0x0008, 0, &mmDAGB0_RDCLI8[0], sizeof(mmDAGB0_RDCLI8)/sizeof(mmDAGB0_RDCLI8[0]), 0, 0 }, + { "mmDAGB0_RDCLI9", REG_MMIO, 0x0009, 0, &mmDAGB0_RDCLI9[0], sizeof(mmDAGB0_RDCLI9)/sizeof(mmDAGB0_RDCLI9[0]), 0, 0 }, + { "mmDAGB0_RDCLI10", REG_MMIO, 0x000a, 0, &mmDAGB0_RDCLI10[0], sizeof(mmDAGB0_RDCLI10)/sizeof(mmDAGB0_RDCLI10[0]), 0, 0 }, + { "mmDAGB0_RDCLI11", REG_MMIO, 0x000b, 0, &mmDAGB0_RDCLI11[0], sizeof(mmDAGB0_RDCLI11)/sizeof(mmDAGB0_RDCLI11[0]), 0, 0 }, + { "mmDAGB0_RDCLI12", REG_MMIO, 0x000c, 0, &mmDAGB0_RDCLI12[0], sizeof(mmDAGB0_RDCLI12)/sizeof(mmDAGB0_RDCLI12[0]), 0, 0 }, + { "mmDAGB0_RDCLI13", REG_MMIO, 0x000d, 0, &mmDAGB0_RDCLI13[0], sizeof(mmDAGB0_RDCLI13)/sizeof(mmDAGB0_RDCLI13[0]), 0, 0 }, + { "mmDAGB0_RDCLI14", REG_MMIO, 0x000e, 0, &mmDAGB0_RDCLI14[0], sizeof(mmDAGB0_RDCLI14)/sizeof(mmDAGB0_RDCLI14[0]), 0, 0 }, + { "mmDAGB0_RDCLI15", REG_MMIO, 0x000f, 0, &mmDAGB0_RDCLI15[0], sizeof(mmDAGB0_RDCLI15)/sizeof(mmDAGB0_RDCLI15[0]), 0, 0 }, + { "mmDAGB0_RDCLI16", REG_MMIO, 0x0010, 0, &mmDAGB0_RDCLI16[0], sizeof(mmDAGB0_RDCLI16)/sizeof(mmDAGB0_RDCLI16[0]), 0, 0 }, + { "mmDAGB0_RDCLI17", REG_MMIO, 0x0011, 0, &mmDAGB0_RDCLI17[0], sizeof(mmDAGB0_RDCLI17)/sizeof(mmDAGB0_RDCLI17[0]), 0, 0 }, + { "mmDAGB0_RDCLI18", REG_MMIO, 0x0012, 0, &mmDAGB0_RDCLI18[0], sizeof(mmDAGB0_RDCLI18)/sizeof(mmDAGB0_RDCLI18[0]), 0, 0 }, + { "mmDAGB0_RDCLI19", REG_MMIO, 0x0013, 0, &mmDAGB0_RDCLI19[0], sizeof(mmDAGB0_RDCLI19)/sizeof(mmDAGB0_RDCLI19[0]), 0, 0 }, + { "mmDAGB0_RDCLI20", REG_MMIO, 0x0014, 0, &mmDAGB0_RDCLI20[0], sizeof(mmDAGB0_RDCLI20)/sizeof(mmDAGB0_RDCLI20[0]), 0, 0 }, + { "mmDAGB0_RDCLI21", REG_MMIO, 0x0015, 0, &mmDAGB0_RDCLI21[0], sizeof(mmDAGB0_RDCLI21)/sizeof(mmDAGB0_RDCLI21[0]), 0, 0 }, + { "mmDAGB0_RDCLI22", REG_MMIO, 0x0016, 0, &mmDAGB0_RDCLI22[0], sizeof(mmDAGB0_RDCLI22)/sizeof(mmDAGB0_RDCLI22[0]), 0, 0 }, + { "mmDAGB0_RDCLI23", REG_MMIO, 0x0017, 0, &mmDAGB0_RDCLI23[0], sizeof(mmDAGB0_RDCLI23)/sizeof(mmDAGB0_RDCLI23[0]), 0, 0 }, + { "mmDAGB0_RDCLI24", REG_MMIO, 0x0018, 0, &mmDAGB0_RDCLI24[0], sizeof(mmDAGB0_RDCLI24)/sizeof(mmDAGB0_RDCLI24[0]), 0, 0 }, + { "mmDAGB0_RDCLI25", REG_MMIO, 0x0019, 0, &mmDAGB0_RDCLI25[0], sizeof(mmDAGB0_RDCLI25)/sizeof(mmDAGB0_RDCLI25[0]), 0, 0 }, + { "mmDAGB0_RDCLI26", REG_MMIO, 0x001a, 0, &mmDAGB0_RDCLI26[0], sizeof(mmDAGB0_RDCLI26)/sizeof(mmDAGB0_RDCLI26[0]), 0, 0 }, + { "mmDAGB0_RDCLI27", REG_MMIO, 0x001b, 0, &mmDAGB0_RDCLI27[0], sizeof(mmDAGB0_RDCLI27)/sizeof(mmDAGB0_RDCLI27[0]), 0, 0 }, + { "mmDAGB0_RDCLI28", REG_MMIO, 0x001c, 0, &mmDAGB0_RDCLI28[0], sizeof(mmDAGB0_RDCLI28)/sizeof(mmDAGB0_RDCLI28[0]), 0, 0 }, + { "mmDAGB0_RDCLI29", REG_MMIO, 0x001d, 0, &mmDAGB0_RDCLI29[0], sizeof(mmDAGB0_RDCLI29)/sizeof(mmDAGB0_RDCLI29[0]), 0, 0 }, + { "mmDAGB0_RDCLI30", REG_MMIO, 0x001e, 0, &mmDAGB0_RDCLI30[0], sizeof(mmDAGB0_RDCLI30)/sizeof(mmDAGB0_RDCLI30[0]), 0, 0 }, + { "mmDAGB0_RDCLI31", REG_MMIO, 0x001f, 0, &mmDAGB0_RDCLI31[0], sizeof(mmDAGB0_RDCLI31)/sizeof(mmDAGB0_RDCLI31[0]), 0, 0 }, + { "mmDAGB0_RD_CNTL", REG_MMIO, 0x0020, 0, &mmDAGB0_RD_CNTL[0], sizeof(mmDAGB0_RD_CNTL)/sizeof(mmDAGB0_RD_CNTL[0]), 0, 0 }, + { "mmDAGB0_RD_GMI_CNTL", REG_MMIO, 0x0021, 0, &mmDAGB0_RD_GMI_CNTL[0], sizeof(mmDAGB0_RD_GMI_CNTL)/sizeof(mmDAGB0_RD_GMI_CNTL[0]), 0, 0 }, + { "mmDAGB0_RD_ADDR_DAGB", REG_MMIO, 0x0022, 0, &mmDAGB0_RD_ADDR_DAGB[0], sizeof(mmDAGB0_RD_ADDR_DAGB)/sizeof(mmDAGB0_RD_ADDR_DAGB[0]), 0, 0 }, + { "mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST", REG_MMIO, 0x0023, 0, &mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST[0], sizeof(mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST)/sizeof(mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST[0]), 0, 0 }, + { "mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER", REG_MMIO, 0x0024, 0, &mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER[0], sizeof(mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER)/sizeof(mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER[0]), 0, 0 }, + { "mmDAGB0_RD_CGTT_CLK_CTRL", REG_MMIO, 0x0025, 0, &mmDAGB0_RD_CGTT_CLK_CTRL[0], sizeof(mmDAGB0_RD_CGTT_CLK_CTRL)/sizeof(mmDAGB0_RD_CGTT_CLK_CTRL[0]), 0, 0 }, + { "mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL", REG_MMIO, 0x0026, 0, &mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL[0], sizeof(mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL)/sizeof(mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL[0]), 0, 0 }, + { "mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL", REG_MMIO, 0x0027, 0, &mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL[0], sizeof(mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL)/sizeof(mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL[0]), 0, 0 }, + { "mmDAGB0_RD_ADDR_DAGB_MAX_BURST0", REG_MMIO, 0x0028, 0, &mmDAGB0_RD_ADDR_DAGB_MAX_BURST0[0], sizeof(mmDAGB0_RD_ADDR_DAGB_MAX_BURST0)/sizeof(mmDAGB0_RD_ADDR_DAGB_MAX_BURST0[0]), 0, 0 }, + { "mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0", REG_MMIO, 0x0029, 0, &mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0[0], sizeof(mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0)/sizeof(mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0[0]), 0, 0 }, + { "mmDAGB0_RD_ADDR_DAGB_MAX_BURST1", REG_MMIO, 0x002a, 0, &mmDAGB0_RD_ADDR_DAGB_MAX_BURST1[0], sizeof(mmDAGB0_RD_ADDR_DAGB_MAX_BURST1)/sizeof(mmDAGB0_RD_ADDR_DAGB_MAX_BURST1[0]), 0, 0 }, + { "mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1", REG_MMIO, 0x002b, 0, &mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1[0], sizeof(mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1)/sizeof(mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1[0]), 0, 0 }, + { "mmDAGB0_RD_ADDR_DAGB_MAX_BURST2", REG_MMIO, 0x002c, 0, &mmDAGB0_RD_ADDR_DAGB_MAX_BURST2[0], sizeof(mmDAGB0_RD_ADDR_DAGB_MAX_BURST2)/sizeof(mmDAGB0_RD_ADDR_DAGB_MAX_BURST2[0]), 0, 0 }, + { "mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER2", REG_MMIO, 0x002d, 0, &mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER2[0], sizeof(mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER2)/sizeof(mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER2[0]), 0, 0 }, + { "mmDAGB0_RD_ADDR_DAGB_MAX_BURST3", REG_MMIO, 0x002e, 0, &mmDAGB0_RD_ADDR_DAGB_MAX_BURST3[0], sizeof(mmDAGB0_RD_ADDR_DAGB_MAX_BURST3)/sizeof(mmDAGB0_RD_ADDR_DAGB_MAX_BURST3[0]), 0, 0 }, + { "mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER3", REG_MMIO, 0x002f, 0, &mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER3[0], sizeof(mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER3)/sizeof(mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER3[0]), 0, 0 }, + { "mmDAGB0_RD_VC0_CNTL", REG_MMIO, 0x0030, 0, &mmDAGB0_RD_VC0_CNTL[0], sizeof(mmDAGB0_RD_VC0_CNTL)/sizeof(mmDAGB0_RD_VC0_CNTL[0]), 0, 0 }, + { "mmDAGB0_RD_VC1_CNTL", REG_MMIO, 0x0031, 0, &mmDAGB0_RD_VC1_CNTL[0], sizeof(mmDAGB0_RD_VC1_CNTL)/sizeof(mmDAGB0_RD_VC1_CNTL[0]), 0, 0 }, + { "mmDAGB0_RD_VC2_CNTL", REG_MMIO, 0x0032, 0, &mmDAGB0_RD_VC2_CNTL[0], sizeof(mmDAGB0_RD_VC2_CNTL)/sizeof(mmDAGB0_RD_VC2_CNTL[0]), 0, 0 }, + { "mmDAGB0_RD_VC3_CNTL", REG_MMIO, 0x0033, 0, &mmDAGB0_RD_VC3_CNTL[0], sizeof(mmDAGB0_RD_VC3_CNTL)/sizeof(mmDAGB0_RD_VC3_CNTL[0]), 0, 0 }, + { "mmDAGB0_RD_VC4_CNTL", REG_MMIO, 0x0034, 0, &mmDAGB0_RD_VC4_CNTL[0], sizeof(mmDAGB0_RD_VC4_CNTL)/sizeof(mmDAGB0_RD_VC4_CNTL[0]), 0, 0 }, + { "mmDAGB0_RD_VC5_CNTL", REG_MMIO, 0x0035, 0, &mmDAGB0_RD_VC5_CNTL[0], sizeof(mmDAGB0_RD_VC5_CNTL)/sizeof(mmDAGB0_RD_VC5_CNTL[0]), 0, 0 }, + { "mmDAGB0_RD_VC6_CNTL", REG_MMIO, 0x0036, 0, &mmDAGB0_RD_VC6_CNTL[0], sizeof(mmDAGB0_RD_VC6_CNTL)/sizeof(mmDAGB0_RD_VC6_CNTL[0]), 0, 0 }, + { "mmDAGB0_RD_VC7_CNTL", REG_MMIO, 0x0037, 0, &mmDAGB0_RD_VC7_CNTL[0], sizeof(mmDAGB0_RD_VC7_CNTL)/sizeof(mmDAGB0_RD_VC7_CNTL[0]), 0, 0 }, + { "mmDAGB0_RD_CNTL_MISC", REG_MMIO, 0x0038, 0, &mmDAGB0_RD_CNTL_MISC[0], sizeof(mmDAGB0_RD_CNTL_MISC)/sizeof(mmDAGB0_RD_CNTL_MISC[0]), 0, 0 }, + { "mmDAGB0_RD_TLB_CREDIT", REG_MMIO, 0x0039, 0, &mmDAGB0_RD_TLB_CREDIT[0], sizeof(mmDAGB0_RD_TLB_CREDIT)/sizeof(mmDAGB0_RD_TLB_CREDIT[0]), 0, 0 }, + { "mmDAGB0_RDCLI_ASK_PENDING", REG_MMIO, 0x003a, 0, &mmDAGB0_RDCLI_ASK_PENDING[0], sizeof(mmDAGB0_RDCLI_ASK_PENDING)/sizeof(mmDAGB0_RDCLI_ASK_PENDING[0]), 0, 0 }, + { "mmDAGB0_RDCLI_GO_PENDING", REG_MMIO, 0x003b, 0, &mmDAGB0_RDCLI_GO_PENDING[0], sizeof(mmDAGB0_RDCLI_GO_PENDING)/sizeof(mmDAGB0_RDCLI_GO_PENDING[0]), 0, 0 }, + { "mmDAGB0_RDCLI_GBLSEND_PENDING", REG_MMIO, 0x003c, 0, &mmDAGB0_RDCLI_GBLSEND_PENDING[0], sizeof(mmDAGB0_RDCLI_GBLSEND_PENDING)/sizeof(mmDAGB0_RDCLI_GBLSEND_PENDING[0]), 0, 0 }, + { "mmDAGB0_RDCLI_TLB_PENDING", REG_MMIO, 0x003d, 0, &mmDAGB0_RDCLI_TLB_PENDING[0], sizeof(mmDAGB0_RDCLI_TLB_PENDING)/sizeof(mmDAGB0_RDCLI_TLB_PENDING[0]), 0, 0 }, + { "mmDAGB0_RDCLI_OARB_PENDING", REG_MMIO, 0x003e, 0, &mmDAGB0_RDCLI_OARB_PENDING[0], sizeof(mmDAGB0_RDCLI_OARB_PENDING)/sizeof(mmDAGB0_RDCLI_OARB_PENDING[0]), 0, 0 }, + { "mmDAGB0_RDCLI_OSD_PENDING", REG_MMIO, 0x003f, 0, &mmDAGB0_RDCLI_OSD_PENDING[0], sizeof(mmDAGB0_RDCLI_OSD_PENDING)/sizeof(mmDAGB0_RDCLI_OSD_PENDING[0]), 0, 0 }, + { "mmDAGB0_WRCLI0", REG_MMIO, 0x0040, 0, &mmDAGB0_WRCLI0[0], sizeof(mmDAGB0_WRCLI0)/sizeof(mmDAGB0_WRCLI0[0]), 0, 0 }, + { "mmDAGB0_WRCLI1", REG_MMIO, 0x0041, 0, &mmDAGB0_WRCLI1[0], sizeof(mmDAGB0_WRCLI1)/sizeof(mmDAGB0_WRCLI1[0]), 0, 0 }, + { "mmDAGB0_WRCLI2", REG_MMIO, 0x0042, 0, &mmDAGB0_WRCLI2[0], sizeof(mmDAGB0_WRCLI2)/sizeof(mmDAGB0_WRCLI2[0]), 0, 0 }, + { "mmDAGB0_WRCLI3", REG_MMIO, 0x0043, 0, &mmDAGB0_WRCLI3[0], sizeof(mmDAGB0_WRCLI3)/sizeof(mmDAGB0_WRCLI3[0]), 0, 0 }, + { "mmDAGB0_WRCLI4", REG_MMIO, 0x0044, 0, &mmDAGB0_WRCLI4[0], sizeof(mmDAGB0_WRCLI4)/sizeof(mmDAGB0_WRCLI4[0]), 0, 0 }, + { "mmDAGB0_WRCLI5", REG_MMIO, 0x0045, 0, &mmDAGB0_WRCLI5[0], sizeof(mmDAGB0_WRCLI5)/sizeof(mmDAGB0_WRCLI5[0]), 0, 0 }, + { "mmDAGB0_WRCLI6", REG_MMIO, 0x0046, 0, &mmDAGB0_WRCLI6[0], sizeof(mmDAGB0_WRCLI6)/sizeof(mmDAGB0_WRCLI6[0]), 0, 0 }, + { "mmDAGB0_WRCLI7", REG_MMIO, 0x0047, 0, &mmDAGB0_WRCLI7[0], sizeof(mmDAGB0_WRCLI7)/sizeof(mmDAGB0_WRCLI7[0]), 0, 0 }, + { "mmDAGB0_WRCLI8", REG_MMIO, 0x0048, 0, &mmDAGB0_WRCLI8[0], sizeof(mmDAGB0_WRCLI8)/sizeof(mmDAGB0_WRCLI8[0]), 0, 0 }, + { "mmDAGB0_WRCLI9", REG_MMIO, 0x0049, 0, &mmDAGB0_WRCLI9[0], sizeof(mmDAGB0_WRCLI9)/sizeof(mmDAGB0_WRCLI9[0]), 0, 0 }, + { "mmDAGB0_WRCLI10", REG_MMIO, 0x004a, 0, &mmDAGB0_WRCLI10[0], sizeof(mmDAGB0_WRCLI10)/sizeof(mmDAGB0_WRCLI10[0]), 0, 0 }, + { "mmDAGB0_WRCLI11", REG_MMIO, 0x004b, 0, &mmDAGB0_WRCLI11[0], sizeof(mmDAGB0_WRCLI11)/sizeof(mmDAGB0_WRCLI11[0]), 0, 0 }, + { "mmDAGB0_WRCLI12", REG_MMIO, 0x004c, 0, &mmDAGB0_WRCLI12[0], sizeof(mmDAGB0_WRCLI12)/sizeof(mmDAGB0_WRCLI12[0]), 0, 0 }, + { "mmDAGB0_WRCLI13", REG_MMIO, 0x004d, 0, &mmDAGB0_WRCLI13[0], sizeof(mmDAGB0_WRCLI13)/sizeof(mmDAGB0_WRCLI13[0]), 0, 0 }, + { "mmDAGB0_WRCLI14", REG_MMIO, 0x004e, 0, &mmDAGB0_WRCLI14[0], sizeof(mmDAGB0_WRCLI14)/sizeof(mmDAGB0_WRCLI14[0]), 0, 0 }, + { "mmDAGB0_WRCLI15", REG_MMIO, 0x004f, 0, &mmDAGB0_WRCLI15[0], sizeof(mmDAGB0_WRCLI15)/sizeof(mmDAGB0_WRCLI15[0]), 0, 0 }, + { "mmDAGB0_WRCLI16", REG_MMIO, 0x0050, 0, &mmDAGB0_WRCLI16[0], sizeof(mmDAGB0_WRCLI16)/sizeof(mmDAGB0_WRCLI16[0]), 0, 0 }, + { "mmDAGB0_WRCLI17", REG_MMIO, 0x0051, 0, &mmDAGB0_WRCLI17[0], sizeof(mmDAGB0_WRCLI17)/sizeof(mmDAGB0_WRCLI17[0]), 0, 0 }, + { "mmDAGB0_WRCLI18", REG_MMIO, 0x0052, 0, &mmDAGB0_WRCLI18[0], sizeof(mmDAGB0_WRCLI18)/sizeof(mmDAGB0_WRCLI18[0]), 0, 0 }, + { "mmDAGB0_WRCLI19", REG_MMIO, 0x0053, 0, &mmDAGB0_WRCLI19[0], sizeof(mmDAGB0_WRCLI19)/sizeof(mmDAGB0_WRCLI19[0]), 0, 0 }, + { "mmDAGB0_WRCLI20", REG_MMIO, 0x0054, 0, &mmDAGB0_WRCLI20[0], sizeof(mmDAGB0_WRCLI20)/sizeof(mmDAGB0_WRCLI20[0]), 0, 0 }, + { "mmDAGB0_WRCLI21", REG_MMIO, 0x0055, 0, &mmDAGB0_WRCLI21[0], sizeof(mmDAGB0_WRCLI21)/sizeof(mmDAGB0_WRCLI21[0]), 0, 0 }, + { "mmDAGB0_WRCLI22", REG_MMIO, 0x0056, 0, &mmDAGB0_WRCLI22[0], sizeof(mmDAGB0_WRCLI22)/sizeof(mmDAGB0_WRCLI22[0]), 0, 0 }, + { "mmDAGB0_WRCLI23", REG_MMIO, 0x0057, 0, &mmDAGB0_WRCLI23[0], sizeof(mmDAGB0_WRCLI23)/sizeof(mmDAGB0_WRCLI23[0]), 0, 0 }, + { "mmDAGB0_WRCLI24", REG_MMIO, 0x0058, 0, &mmDAGB0_WRCLI24[0], sizeof(mmDAGB0_WRCLI24)/sizeof(mmDAGB0_WRCLI24[0]), 0, 0 }, + { "mmDAGB0_WRCLI25", REG_MMIO, 0x0059, 0, &mmDAGB0_WRCLI25[0], sizeof(mmDAGB0_WRCLI25)/sizeof(mmDAGB0_WRCLI25[0]), 0, 0 }, + { "mmDAGB0_WRCLI26", REG_MMIO, 0x005a, 0, &mmDAGB0_WRCLI26[0], sizeof(mmDAGB0_WRCLI26)/sizeof(mmDAGB0_WRCLI26[0]), 0, 0 }, + { "mmDAGB0_WRCLI27", REG_MMIO, 0x005b, 0, &mmDAGB0_WRCLI27[0], sizeof(mmDAGB0_WRCLI27)/sizeof(mmDAGB0_WRCLI27[0]), 0, 0 }, + { "mmDAGB0_WRCLI28", REG_MMIO, 0x005c, 0, &mmDAGB0_WRCLI28[0], sizeof(mmDAGB0_WRCLI28)/sizeof(mmDAGB0_WRCLI28[0]), 0, 0 }, + { "mmDAGB0_WRCLI29", REG_MMIO, 0x005d, 0, &mmDAGB0_WRCLI29[0], sizeof(mmDAGB0_WRCLI29)/sizeof(mmDAGB0_WRCLI29[0]), 0, 0 }, + { "mmDAGB0_WRCLI30", REG_MMIO, 0x005e, 0, &mmDAGB0_WRCLI30[0], sizeof(mmDAGB0_WRCLI30)/sizeof(mmDAGB0_WRCLI30[0]), 0, 0 }, + { "mmDAGB0_WRCLI31", REG_MMIO, 0x005f, 0, &mmDAGB0_WRCLI31[0], sizeof(mmDAGB0_WRCLI31)/sizeof(mmDAGB0_WRCLI31[0]), 0, 0 }, + { "mmDAGB0_WR_CNTL", REG_MMIO, 0x0060, 0, &mmDAGB0_WR_CNTL[0], sizeof(mmDAGB0_WR_CNTL)/sizeof(mmDAGB0_WR_CNTL[0]), 0, 0 }, + { "mmDAGB0_WR_GMI_CNTL", REG_MMIO, 0x0061, 0, &mmDAGB0_WR_GMI_CNTL[0], sizeof(mmDAGB0_WR_GMI_CNTL)/sizeof(mmDAGB0_WR_GMI_CNTL[0]), 0, 0 }, + { "mmDAGB0_WR_ADDR_DAGB", REG_MMIO, 0x0062, 0, &mmDAGB0_WR_ADDR_DAGB[0], sizeof(mmDAGB0_WR_ADDR_DAGB)/sizeof(mmDAGB0_WR_ADDR_DAGB[0]), 0, 0 }, + { "mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST", REG_MMIO, 0x0063, 0, &mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST[0], sizeof(mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST)/sizeof(mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST[0]), 0, 0 }, + { "mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER", REG_MMIO, 0x0064, 0, &mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER[0], sizeof(mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER)/sizeof(mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER[0]), 0, 0 }, + { "mmDAGB0_WR_CGTT_CLK_CTRL", REG_MMIO, 0x0065, 0, &mmDAGB0_WR_CGTT_CLK_CTRL[0], sizeof(mmDAGB0_WR_CGTT_CLK_CTRL)/sizeof(mmDAGB0_WR_CGTT_CLK_CTRL[0]), 0, 0 }, + { "mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL", REG_MMIO, 0x0066, 0, &mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL[0], sizeof(mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL)/sizeof(mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL[0]), 0, 0 }, + { "mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL", REG_MMIO, 0x0067, 0, &mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL[0], sizeof(mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL)/sizeof(mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL[0]), 0, 0 }, + { "mmDAGB0_WR_ADDR_DAGB_MAX_BURST0", REG_MMIO, 0x0068, 0, &mmDAGB0_WR_ADDR_DAGB_MAX_BURST0[0], sizeof(mmDAGB0_WR_ADDR_DAGB_MAX_BURST0)/sizeof(mmDAGB0_WR_ADDR_DAGB_MAX_BURST0[0]), 0, 0 }, + { "mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0", REG_MMIO, 0x0069, 0, &mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0[0], sizeof(mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0)/sizeof(mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0[0]), 0, 0 }, + { "mmDAGB0_WR_ADDR_DAGB_MAX_BURST1", REG_MMIO, 0x006a, 0, &mmDAGB0_WR_ADDR_DAGB_MAX_BURST1[0], sizeof(mmDAGB0_WR_ADDR_DAGB_MAX_BURST1)/sizeof(mmDAGB0_WR_ADDR_DAGB_MAX_BURST1[0]), 0, 0 }, + { "mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1", REG_MMIO, 0x006b, 0, &mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1[0], sizeof(mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1)/sizeof(mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1[0]), 0, 0 }, + { "mmDAGB0_WR_ADDR_DAGB_MAX_BURST2", REG_MMIO, 0x006c, 0, &mmDAGB0_WR_ADDR_DAGB_MAX_BURST2[0], sizeof(mmDAGB0_WR_ADDR_DAGB_MAX_BURST2)/sizeof(mmDAGB0_WR_ADDR_DAGB_MAX_BURST2[0]), 0, 0 }, + { "mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER2", REG_MMIO, 0x006d, 0, &mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER2[0], sizeof(mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER2)/sizeof(mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER2[0]), 0, 0 }, + { "mmDAGB0_WR_ADDR_DAGB_MAX_BURST3", REG_MMIO, 0x006e, 0, &mmDAGB0_WR_ADDR_DAGB_MAX_BURST3[0], sizeof(mmDAGB0_WR_ADDR_DAGB_MAX_BURST3)/sizeof(mmDAGB0_WR_ADDR_DAGB_MAX_BURST3[0]), 0, 0 }, + { "mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER3", REG_MMIO, 0x006f, 0, &mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER3[0], sizeof(mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER3)/sizeof(mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER3[0]), 0, 0 }, + { "mmDAGB0_WR_DATA_DAGB", REG_MMIO, 0x0070, 0, &mmDAGB0_WR_DATA_DAGB[0], sizeof(mmDAGB0_WR_DATA_DAGB)/sizeof(mmDAGB0_WR_DATA_DAGB[0]), 0, 0 }, + { "mmDAGB0_WR_DATA_DAGB_MAX_BURST0", REG_MMIO, 0x0071, 0, &mmDAGB0_WR_DATA_DAGB_MAX_BURST0[0], sizeof(mmDAGB0_WR_DATA_DAGB_MAX_BURST0)/sizeof(mmDAGB0_WR_DATA_DAGB_MAX_BURST0[0]), 0, 0 }, + { "mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0", REG_MMIO, 0x0072, 0, &mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0[0], sizeof(mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0)/sizeof(mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0[0]), 0, 0 }, + { "mmDAGB0_WR_DATA_DAGB_MAX_BURST1", REG_MMIO, 0x0073, 0, &mmDAGB0_WR_DATA_DAGB_MAX_BURST1[0], sizeof(mmDAGB0_WR_DATA_DAGB_MAX_BURST1)/sizeof(mmDAGB0_WR_DATA_DAGB_MAX_BURST1[0]), 0, 0 }, + { "mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1", REG_MMIO, 0x0074, 0, &mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1[0], sizeof(mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1)/sizeof(mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1[0]), 0, 0 }, + { "mmDAGB0_WR_DATA_DAGB_MAX_BURST2", REG_MMIO, 0x0075, 0, &mmDAGB0_WR_DATA_DAGB_MAX_BURST2[0], sizeof(mmDAGB0_WR_DATA_DAGB_MAX_BURST2)/sizeof(mmDAGB0_WR_DATA_DAGB_MAX_BURST2[0]), 0, 0 }, + { "mmDAGB0_WR_DATA_DAGB_LAZY_TIMER2", REG_MMIO, 0x0076, 0, &mmDAGB0_WR_DATA_DAGB_LAZY_TIMER2[0], sizeof(mmDAGB0_WR_DATA_DAGB_LAZY_TIMER2)/sizeof(mmDAGB0_WR_DATA_DAGB_LAZY_TIMER2[0]), 0, 0 }, + { "mmDAGB0_WR_DATA_DAGB_MAX_BURST3", REG_MMIO, 0x0077, 0, &mmDAGB0_WR_DATA_DAGB_MAX_BURST3[0], sizeof(mmDAGB0_WR_DATA_DAGB_MAX_BURST3)/sizeof(mmDAGB0_WR_DATA_DAGB_MAX_BURST3[0]), 0, 0 }, + { "mmDAGB0_WR_DATA_DAGB_LAZY_TIMER3", REG_MMIO, 0x0078, 0, &mmDAGB0_WR_DATA_DAGB_LAZY_TIMER3[0], sizeof(mmDAGB0_WR_DATA_DAGB_LAZY_TIMER3)/sizeof(mmDAGB0_WR_DATA_DAGB_LAZY_TIMER3[0]), 0, 0 }, + { "mmDAGB0_WR_VC0_CNTL", REG_MMIO, 0x0079, 0, &mmDAGB0_WR_VC0_CNTL[0], sizeof(mmDAGB0_WR_VC0_CNTL)/sizeof(mmDAGB0_WR_VC0_CNTL[0]), 0, 0 }, + { "mmDAGB0_WR_VC1_CNTL", REG_MMIO, 0x007a, 0, &mmDAGB0_WR_VC1_CNTL[0], sizeof(mmDAGB0_WR_VC1_CNTL)/sizeof(mmDAGB0_WR_VC1_CNTL[0]), 0, 0 }, + { "mmDAGB0_WR_VC2_CNTL", REG_MMIO, 0x007b, 0, &mmDAGB0_WR_VC2_CNTL[0], sizeof(mmDAGB0_WR_VC2_CNTL)/sizeof(mmDAGB0_WR_VC2_CNTL[0]), 0, 0 }, + { "mmDAGB0_WR_VC3_CNTL", REG_MMIO, 0x007c, 0, &mmDAGB0_WR_VC3_CNTL[0], sizeof(mmDAGB0_WR_VC3_CNTL)/sizeof(mmDAGB0_WR_VC3_CNTL[0]), 0, 0 }, + { "mmDAGB0_WR_VC4_CNTL", REG_MMIO, 0x007d, 0, &mmDAGB0_WR_VC4_CNTL[0], sizeof(mmDAGB0_WR_VC4_CNTL)/sizeof(mmDAGB0_WR_VC4_CNTL[0]), 0, 0 }, + { "mmDAGB0_WR_VC5_CNTL", REG_MMIO, 0x007e, 0, &mmDAGB0_WR_VC5_CNTL[0], sizeof(mmDAGB0_WR_VC5_CNTL)/sizeof(mmDAGB0_WR_VC5_CNTL[0]), 0, 0 }, + { "mmDAGB0_WR_VC6_CNTL", REG_MMIO, 0x007f, 0, &mmDAGB0_WR_VC6_CNTL[0], sizeof(mmDAGB0_WR_VC6_CNTL)/sizeof(mmDAGB0_WR_VC6_CNTL[0]), 0, 0 }, + { "mmDAGB0_WR_VC7_CNTL", REG_MMIO, 0x0080, 0, &mmDAGB0_WR_VC7_CNTL[0], sizeof(mmDAGB0_WR_VC7_CNTL)/sizeof(mmDAGB0_WR_VC7_CNTL[0]), 0, 0 }, + { "mmDAGB0_WR_CNTL_MISC", REG_MMIO, 0x0081, 0, &mmDAGB0_WR_CNTL_MISC[0], sizeof(mmDAGB0_WR_CNTL_MISC)/sizeof(mmDAGB0_WR_CNTL_MISC[0]), 0, 0 }, + { "mmDAGB0_WR_TLB_CREDIT", REG_MMIO, 0x0082, 0, &mmDAGB0_WR_TLB_CREDIT[0], sizeof(mmDAGB0_WR_TLB_CREDIT)/sizeof(mmDAGB0_WR_TLB_CREDIT[0]), 0, 0 }, + { "mmDAGB0_WR_DATA_CREDIT", REG_MMIO, 0x0083, 0, &mmDAGB0_WR_DATA_CREDIT[0], sizeof(mmDAGB0_WR_DATA_CREDIT)/sizeof(mmDAGB0_WR_DATA_CREDIT[0]), 0, 0 }, + { "mmDAGB0_WR_MISC_CREDIT", REG_MMIO, 0x0084, 0, &mmDAGB0_WR_MISC_CREDIT[0], sizeof(mmDAGB0_WR_MISC_CREDIT)/sizeof(mmDAGB0_WR_MISC_CREDIT[0]), 0, 0 }, + { "mmDAGB0_WRCLI_ASK_PENDING", REG_MMIO, 0x0085, 0, &mmDAGB0_WRCLI_ASK_PENDING[0], sizeof(mmDAGB0_WRCLI_ASK_PENDING)/sizeof(mmDAGB0_WRCLI_ASK_PENDING[0]), 0, 0 }, + { "mmDAGB0_WRCLI_GO_PENDING", REG_MMIO, 0x0086, 0, &mmDAGB0_WRCLI_GO_PENDING[0], sizeof(mmDAGB0_WRCLI_GO_PENDING)/sizeof(mmDAGB0_WRCLI_GO_PENDING[0]), 0, 0 }, + { "mmDAGB0_WRCLI_GBLSEND_PENDING", REG_MMIO, 0x0087, 0, &mmDAGB0_WRCLI_GBLSEND_PENDING[0], sizeof(mmDAGB0_WRCLI_GBLSEND_PENDING)/sizeof(mmDAGB0_WRCLI_GBLSEND_PENDING[0]), 0, 0 }, + { "mmDAGB0_WRCLI_TLB_PENDING", REG_MMIO, 0x0088, 0, &mmDAGB0_WRCLI_TLB_PENDING[0], sizeof(mmDAGB0_WRCLI_TLB_PENDING)/sizeof(mmDAGB0_WRCLI_TLB_PENDING[0]), 0, 0 }, + { "mmDAGB0_WRCLI_OARB_PENDING", REG_MMIO, 0x0089, 0, &mmDAGB0_WRCLI_OARB_PENDING[0], sizeof(mmDAGB0_WRCLI_OARB_PENDING)/sizeof(mmDAGB0_WRCLI_OARB_PENDING[0]), 0, 0 }, + { "mmDAGB0_WRCLI_OSD_PENDING", REG_MMIO, 0x008a, 0, &mmDAGB0_WRCLI_OSD_PENDING[0], sizeof(mmDAGB0_WRCLI_OSD_PENDING)/sizeof(mmDAGB0_WRCLI_OSD_PENDING[0]), 0, 0 }, + { "mmDAGB0_WRCLI_DBUS_ASK_PENDING", REG_MMIO, 0x008b, 0, &mmDAGB0_WRCLI_DBUS_ASK_PENDING[0], sizeof(mmDAGB0_WRCLI_DBUS_ASK_PENDING)/sizeof(mmDAGB0_WRCLI_DBUS_ASK_PENDING[0]), 0, 0 }, + { "mmDAGB0_WRCLI_DBUS_GO_PENDING", REG_MMIO, 0x008c, 0, &mmDAGB0_WRCLI_DBUS_GO_PENDING[0], sizeof(mmDAGB0_WRCLI_DBUS_GO_PENDING)/sizeof(mmDAGB0_WRCLI_DBUS_GO_PENDING[0]), 0, 0 }, + { "mmDAGB0_DAGB_DLY", REG_MMIO, 0x008d, 0, &mmDAGB0_DAGB_DLY[0], sizeof(mmDAGB0_DAGB_DLY)/sizeof(mmDAGB0_DAGB_DLY[0]), 0, 0 }, + { "mmDAGB0_CNTL_MISC", REG_MMIO, 0x008e, 0, &mmDAGB0_CNTL_MISC[0], sizeof(mmDAGB0_CNTL_MISC)/sizeof(mmDAGB0_CNTL_MISC[0]), 0, 0 }, + { "mmDAGB0_CNTL_MISC2", REG_MMIO, 0x008f, 0, &mmDAGB0_CNTL_MISC2[0], sizeof(mmDAGB0_CNTL_MISC2)/sizeof(mmDAGB0_CNTL_MISC2[0]), 0, 0 }, + { "mmDAGB0_FIFO_EMPTY", REG_MMIO, 0x0090, 0, &mmDAGB0_FIFO_EMPTY[0], sizeof(mmDAGB0_FIFO_EMPTY)/sizeof(mmDAGB0_FIFO_EMPTY[0]), 0, 0 }, + { "mmDAGB0_FIFO_FULL", REG_MMIO, 0x0091, 0, &mmDAGB0_FIFO_FULL[0], sizeof(mmDAGB0_FIFO_FULL)/sizeof(mmDAGB0_FIFO_FULL[0]), 0, 0 }, + { "mmDAGB0_WR_CREDITS_FULL", REG_MMIO, 0x0092, 0, &mmDAGB0_WR_CREDITS_FULL[0], sizeof(mmDAGB0_WR_CREDITS_FULL)/sizeof(mmDAGB0_WR_CREDITS_FULL[0]), 0, 0 }, + { "mmDAGB0_RD_CREDITS_FULL", REG_MMIO, 0x0093, 0, &mmDAGB0_RD_CREDITS_FULL[0], sizeof(mmDAGB0_RD_CREDITS_FULL)/sizeof(mmDAGB0_RD_CREDITS_FULL[0]), 0, 0 }, + { "mmDAGB0_PERFCOUNTER_LO", REG_MMIO, 0x0094, 0, &mmDAGB0_PERFCOUNTER_LO[0], sizeof(mmDAGB0_PERFCOUNTER_LO)/sizeof(mmDAGB0_PERFCOUNTER_LO[0]), 0, 0 }, + { "mmDAGB0_PERFCOUNTER_HI", REG_MMIO, 0x0095, 0, &mmDAGB0_PERFCOUNTER_HI[0], sizeof(mmDAGB0_PERFCOUNTER_HI)/sizeof(mmDAGB0_PERFCOUNTER_HI[0]), 0, 0 }, + { "mmDAGB0_PERFCOUNTER0_CFG", REG_MMIO, 0x0096, 0, &mmDAGB0_PERFCOUNTER0_CFG[0], sizeof(mmDAGB0_PERFCOUNTER0_CFG)/sizeof(mmDAGB0_PERFCOUNTER0_CFG[0]), 0, 0 }, + { "mmDAGB0_PERFCOUNTER1_CFG", REG_MMIO, 0x0097, 0, &mmDAGB0_PERFCOUNTER1_CFG[0], sizeof(mmDAGB0_PERFCOUNTER1_CFG)/sizeof(mmDAGB0_PERFCOUNTER1_CFG[0]), 0, 0 }, + { "mmDAGB0_PERFCOUNTER2_CFG", REG_MMIO, 0x0098, 0, &mmDAGB0_PERFCOUNTER2_CFG[0], sizeof(mmDAGB0_PERFCOUNTER2_CFG)/sizeof(mmDAGB0_PERFCOUNTER2_CFG[0]), 0, 0 }, + { "mmDAGB0_PERFCOUNTER_RSLT_CNTL", REG_MMIO, 0x0099, 0, &mmDAGB0_PERFCOUNTER_RSLT_CNTL[0], sizeof(mmDAGB0_PERFCOUNTER_RSLT_CNTL)/sizeof(mmDAGB0_PERFCOUNTER_RSLT_CNTL[0]), 0, 0 }, + { "mmDAGB0_RESERVE0", REG_MMIO, 0x009a, 0, &mmDAGB0_RESERVE0[0], sizeof(mmDAGB0_RESERVE0)/sizeof(mmDAGB0_RESERVE0[0]), 0, 0 }, + { "mmDAGB0_RESERVE1", REG_MMIO, 0x009b, 0, &mmDAGB0_RESERVE1[0], sizeof(mmDAGB0_RESERVE1)/sizeof(mmDAGB0_RESERVE1[0]), 0, 0 }, + { "mmDAGB0_RESERVE2", REG_MMIO, 0x009c, 0, &mmDAGB0_RESERVE2[0], sizeof(mmDAGB0_RESERVE2)/sizeof(mmDAGB0_RESERVE2[0]), 0, 0 }, + { "mmDAGB0_RESERVE3", REG_MMIO, 0x009d, 0, &mmDAGB0_RESERVE3[0], sizeof(mmDAGB0_RESERVE3)/sizeof(mmDAGB0_RESERVE3[0]), 0, 0 }, + { "mmDAGB0_RESERVE4", REG_MMIO, 0x009e, 0, &mmDAGB0_RESERVE4[0], sizeof(mmDAGB0_RESERVE4)/sizeof(mmDAGB0_RESERVE4[0]), 0, 0 }, + { "mmDAGB0_RESERVE5", REG_MMIO, 0x009f, 0, &mmDAGB0_RESERVE5[0], sizeof(mmDAGB0_RESERVE5)/sizeof(mmDAGB0_RESERVE5[0]), 0, 0 }, + { "mmDAGB0_RESERVE6", REG_MMIO, 0x00a0, 0, &mmDAGB0_RESERVE6[0], sizeof(mmDAGB0_RESERVE6)/sizeof(mmDAGB0_RESERVE6[0]), 0, 0 }, + { "mmDAGB0_RESERVE7", REG_MMIO, 0x00a1, 0, &mmDAGB0_RESERVE7[0], sizeof(mmDAGB0_RESERVE7)/sizeof(mmDAGB0_RESERVE7[0]), 0, 0 }, + { "mmDAGB0_RESERVE8", REG_MMIO, 0x00a2, 0, &mmDAGB0_RESERVE8[0], sizeof(mmDAGB0_RESERVE8)/sizeof(mmDAGB0_RESERVE8[0]), 0, 0 }, + { "mmDAGB0_RESERVE9", REG_MMIO, 0x00a3, 0, &mmDAGB0_RESERVE9[0], sizeof(mmDAGB0_RESERVE9)/sizeof(mmDAGB0_RESERVE9[0]), 0, 0 }, + { "mmDAGB0_RESERVE10", REG_MMIO, 0x00a4, 0, &mmDAGB0_RESERVE10[0], sizeof(mmDAGB0_RESERVE10)/sizeof(mmDAGB0_RESERVE10[0]), 0, 0 }, + { "mmDAGB0_RESERVE11", REG_MMIO, 0x00a5, 0, &mmDAGB0_RESERVE11[0], sizeof(mmDAGB0_RESERVE11)/sizeof(mmDAGB0_RESERVE11[0]), 0, 0 }, + { "mmDAGB0_RESERVE12", REG_MMIO, 0x00a6, 0, &mmDAGB0_RESERVE12[0], sizeof(mmDAGB0_RESERVE12)/sizeof(mmDAGB0_RESERVE12[0]), 0, 0 }, + { "mmDAGB0_RESERVE13", REG_MMIO, 0x00a7, 0, &mmDAGB0_RESERVE13[0], sizeof(mmDAGB0_RESERVE13)/sizeof(mmDAGB0_RESERVE13[0]), 0, 0 }, + { "mmDAGB0_RESERVE14", REG_MMIO, 0x00a8, 0, &mmDAGB0_RESERVE14[0], sizeof(mmDAGB0_RESERVE14)/sizeof(mmDAGB0_RESERVE14[0]), 0, 0 }, + { "mmDAGB0_RESERVE15", REG_MMIO, 0x00a9, 0, &mmDAGB0_RESERVE15[0], sizeof(mmDAGB0_RESERVE15)/sizeof(mmDAGB0_RESERVE15[0]), 0, 0 }, + { "mmDAGB0_RESERVE16", REG_MMIO, 0x00aa, 0, &mmDAGB0_RESERVE16[0], sizeof(mmDAGB0_RESERVE16)/sizeof(mmDAGB0_RESERVE16[0]), 0, 0 }, + { "mmDAGB0_RESERVE17", REG_MMIO, 0x00ab, 0, &mmDAGB0_RESERVE17[0], sizeof(mmDAGB0_RESERVE17)/sizeof(mmDAGB0_RESERVE17[0]), 0, 0 }, + { "mmDAGB0_RESERVE18", REG_MMIO, 0x00ac, 0, &mmDAGB0_RESERVE18[0], sizeof(mmDAGB0_RESERVE18)/sizeof(mmDAGB0_RESERVE18[0]), 0, 0 }, + { "mmDAGB0_RESERVE19", REG_MMIO, 0x00ad, 0, &mmDAGB0_RESERVE19[0], sizeof(mmDAGB0_RESERVE19)/sizeof(mmDAGB0_RESERVE19[0]), 0, 0 }, + { "mmDAGB0_RESERVE20", REG_MMIO, 0x00ae, 0, &mmDAGB0_RESERVE20[0], sizeof(mmDAGB0_RESERVE20)/sizeof(mmDAGB0_RESERVE20[0]), 0, 0 }, + { "mmDAGB0_RESERVE21", REG_MMIO, 0x00af, 0, &mmDAGB0_RESERVE21[0], sizeof(mmDAGB0_RESERVE21)/sizeof(mmDAGB0_RESERVE21[0]), 0, 0 }, + { "mmDAGB0_RESERVE22", REG_MMIO, 0x00b0, 0, &mmDAGB0_RESERVE22[0], sizeof(mmDAGB0_RESERVE22)/sizeof(mmDAGB0_RESERVE22[0]), 0, 0 }, + { "mmDAGB0_RESERVE23", REG_MMIO, 0x00b1, 0, &mmDAGB0_RESERVE23[0], sizeof(mmDAGB0_RESERVE23)/sizeof(mmDAGB0_RESERVE23[0]), 0, 0 }, + { "mmDAGB0_RESERVE24", REG_MMIO, 0x00b2, 0, &mmDAGB0_RESERVE24[0], sizeof(mmDAGB0_RESERVE24)/sizeof(mmDAGB0_RESERVE24[0]), 0, 0 }, + { "mmDAGB0_RESERVE25", REG_MMIO, 0x00b3, 0, &mmDAGB0_RESERVE25[0], sizeof(mmDAGB0_RESERVE25)/sizeof(mmDAGB0_RESERVE25[0]), 0, 0 }, + { "mmDAGB0_RESERVE26", REG_MMIO, 0x00b4, 0, &mmDAGB0_RESERVE26[0], sizeof(mmDAGB0_RESERVE26)/sizeof(mmDAGB0_RESERVE26[0]), 0, 0 }, + { "mmDAGB0_RESERVE27", REG_MMIO, 0x00b5, 0, &mmDAGB0_RESERVE27[0], sizeof(mmDAGB0_RESERVE27)/sizeof(mmDAGB0_RESERVE27[0]), 0, 0 }, + { "mmDAGB0_RESERVE28", REG_MMIO, 0x00b6, 0, &mmDAGB0_RESERVE28[0], sizeof(mmDAGB0_RESERVE28)/sizeof(mmDAGB0_RESERVE28[0]), 0, 0 }, + { "mmDAGB0_RESERVE29", REG_MMIO, 0x00b7, 0, &mmDAGB0_RESERVE29[0], sizeof(mmDAGB0_RESERVE29)/sizeof(mmDAGB0_RESERVE29[0]), 0, 0 }, + { "mmDAGB0_RESERVE30", REG_MMIO, 0x00b8, 0, &mmDAGB0_RESERVE30[0], sizeof(mmDAGB0_RESERVE30)/sizeof(mmDAGB0_RESERVE30[0]), 0, 0 }, + { "mmDAGB0_RESERVE31", REG_MMIO, 0x00b9, 0, &mmDAGB0_RESERVE31[0], sizeof(mmDAGB0_RESERVE31)/sizeof(mmDAGB0_RESERVE31[0]), 0, 0 }, + { "mmDAGB0_RESERVE32", REG_MMIO, 0x00ba, 0, &mmDAGB0_RESERVE32[0], sizeof(mmDAGB0_RESERVE32)/sizeof(mmDAGB0_RESERVE32[0]), 0, 0 }, + { "mmDAGB0_RESERVE33", REG_MMIO, 0x00bb, 0, &mmDAGB0_RESERVE33[0], sizeof(mmDAGB0_RESERVE33)/sizeof(mmDAGB0_RESERVE33[0]), 0, 0 }, + { "mmDAGB0_RESERVE34", REG_MMIO, 0x00bc, 0, &mmDAGB0_RESERVE34[0], sizeof(mmDAGB0_RESERVE34)/sizeof(mmDAGB0_RESERVE34[0]), 0, 0 }, + { "mmDAGB0_RESERVE35", REG_MMIO, 0x00bd, 0, &mmDAGB0_RESERVE35[0], sizeof(mmDAGB0_RESERVE35)/sizeof(mmDAGB0_RESERVE35[0]), 0, 0 }, + { "mmDAGB0_RESERVE36", REG_MMIO, 0x00be, 0, &mmDAGB0_RESERVE36[0], sizeof(mmDAGB0_RESERVE36)/sizeof(mmDAGB0_RESERVE36[0]), 0, 0 }, + { "mmDAGB0_RESERVE37", REG_MMIO, 0x00bf, 0, &mmDAGB0_RESERVE37[0], sizeof(mmDAGB0_RESERVE37)/sizeof(mmDAGB0_RESERVE37[0]), 0, 0 }, + { "mmDAGB0_RESERVE38", REG_MMIO, 0x00c0, 0, &mmDAGB0_RESERVE38[0], sizeof(mmDAGB0_RESERVE38)/sizeof(mmDAGB0_RESERVE38[0]), 0, 0 }, + { "mmDAGB0_RESERVE39", REG_MMIO, 0x00c1, 0, &mmDAGB0_RESERVE39[0], sizeof(mmDAGB0_RESERVE39)/sizeof(mmDAGB0_RESERVE39[0]), 0, 0 }, + { "mmDAGB0_RESERVE40", REG_MMIO, 0x00c2, 0, &mmDAGB0_RESERVE40[0], sizeof(mmDAGB0_RESERVE40)/sizeof(mmDAGB0_RESERVE40[0]), 0, 0 }, + { "mmDAGB0_RESERVE41", REG_MMIO, 0x00c3, 0, &mmDAGB0_RESERVE41[0], sizeof(mmDAGB0_RESERVE41)/sizeof(mmDAGB0_RESERVE41[0]), 0, 0 }, + { "mmDAGB0_RESERVE42", REG_MMIO, 0x00c4, 0, &mmDAGB0_RESERVE42[0], sizeof(mmDAGB0_RESERVE42)/sizeof(mmDAGB0_RESERVE42[0]), 0, 0 }, + { "mmDAGB0_RESERVE43", REG_MMIO, 0x00c5, 0, &mmDAGB0_RESERVE43[0], sizeof(mmDAGB0_RESERVE43)/sizeof(mmDAGB0_RESERVE43[0]), 0, 0 }, + { "mmDAGB0_RESERVE44", REG_MMIO, 0x00c6, 0, &mmDAGB0_RESERVE44[0], sizeof(mmDAGB0_RESERVE44)/sizeof(mmDAGB0_RESERVE44[0]), 0, 0 }, + { "mmDAGB0_RESERVE45", REG_MMIO, 0x00c7, 0, &mmDAGB0_RESERVE45[0], sizeof(mmDAGB0_RESERVE45)/sizeof(mmDAGB0_RESERVE45[0]), 0, 0 }, + { "mmDAGB0_RESERVE46", REG_MMIO, 0x00c8, 0, &mmDAGB0_RESERVE46[0], sizeof(mmDAGB0_RESERVE46)/sizeof(mmDAGB0_RESERVE46[0]), 0, 0 }, + { "mmDAGB0_RESERVE47", REG_MMIO, 0x00c9, 0, &mmDAGB0_RESERVE47[0], sizeof(mmDAGB0_RESERVE47)/sizeof(mmDAGB0_RESERVE47[0]), 0, 0 }, + { "mmDAGB0_RESERVE48", REG_MMIO, 0x00ca, 0, &mmDAGB0_RESERVE48[0], sizeof(mmDAGB0_RESERVE48)/sizeof(mmDAGB0_RESERVE48[0]), 0, 0 }, + { "mmDAGB0_RESERVE49", REG_MMIO, 0x00cb, 0, &mmDAGB0_RESERVE49[0], sizeof(mmDAGB0_RESERVE49)/sizeof(mmDAGB0_RESERVE49[0]), 0, 0 }, + { "mmDAGB0_RESERVE50", REG_MMIO, 0x00cc, 0, &mmDAGB0_RESERVE50[0], sizeof(mmDAGB0_RESERVE50)/sizeof(mmDAGB0_RESERVE50[0]), 0, 0 }, + { "mmDAGB0_RESERVE51", REG_MMIO, 0x00cd, 0, &mmDAGB0_RESERVE51[0], sizeof(mmDAGB0_RESERVE51)/sizeof(mmDAGB0_RESERVE51[0]), 0, 0 }, + { "mmDAGB0_RESERVE52", REG_MMIO, 0x00ce, 0, &mmDAGB0_RESERVE52[0], sizeof(mmDAGB0_RESERVE52)/sizeof(mmDAGB0_RESERVE52[0]), 0, 0 }, + { "mmDAGB0_RESERVE53", REG_MMIO, 0x00cf, 0, &mmDAGB0_RESERVE53[0], sizeof(mmDAGB0_RESERVE53)/sizeof(mmDAGB0_RESERVE53[0]), 0, 0 }, + { "mmDAGB0_RESERVE54", REG_MMIO, 0x00d0, 0, &mmDAGB0_RESERVE54[0], sizeof(mmDAGB0_RESERVE54)/sizeof(mmDAGB0_RESERVE54[0]), 0, 0 }, + { "mmDAGB0_RESERVE55", REG_MMIO, 0x00d1, 0, &mmDAGB0_RESERVE55[0], sizeof(mmDAGB0_RESERVE55)/sizeof(mmDAGB0_RESERVE55[0]), 0, 0 }, + { "mmDAGB0_RESERVE56", REG_MMIO, 0x00d2, 0, &mmDAGB0_RESERVE56[0], sizeof(mmDAGB0_RESERVE56)/sizeof(mmDAGB0_RESERVE56[0]), 0, 0 }, + { "mmDAGB0_RESERVE57", REG_MMIO, 0x00d3, 0, &mmDAGB0_RESERVE57[0], sizeof(mmDAGB0_RESERVE57)/sizeof(mmDAGB0_RESERVE57[0]), 0, 0 }, + { "mmDAGB0_RESERVE58", REG_MMIO, 0x00d4, 0, &mmDAGB0_RESERVE58[0], sizeof(mmDAGB0_RESERVE58)/sizeof(mmDAGB0_RESERVE58[0]), 0, 0 }, + { "mmDAGB0_RESERVE59", REG_MMIO, 0x00d5, 0, &mmDAGB0_RESERVE59[0], sizeof(mmDAGB0_RESERVE59)/sizeof(mmDAGB0_RESERVE59[0]), 0, 0 }, + { "mmDAGB0_RESERVE60", REG_MMIO, 0x00d6, 0, &mmDAGB0_RESERVE60[0], sizeof(mmDAGB0_RESERVE60)/sizeof(mmDAGB0_RESERVE60[0]), 0, 0 }, + { "mmDAGB0_RESERVE61", REG_MMIO, 0x00d7, 0, &mmDAGB0_RESERVE61[0], sizeof(mmDAGB0_RESERVE61)/sizeof(mmDAGB0_RESERVE61[0]), 0, 0 }, + { "mmDAGB0_RESERVE62", REG_MMIO, 0x00d8, 0, &mmDAGB0_RESERVE62[0], sizeof(mmDAGB0_RESERVE62)/sizeof(mmDAGB0_RESERVE62[0]), 0, 0 }, + { "mmDAGB0_RESERVE63", REG_MMIO, 0x00d9, 0, &mmDAGB0_RESERVE63[0], sizeof(mmDAGB0_RESERVE63)/sizeof(mmDAGB0_RESERVE63[0]), 0, 0 }, + { "mmDAGB0_RESERVE64", REG_MMIO, 0x00da, 0, &mmDAGB0_RESERVE64[0], sizeof(mmDAGB0_RESERVE64)/sizeof(mmDAGB0_RESERVE64[0]), 0, 0 }, + { "mmDAGB0_RESERVE65", REG_MMIO, 0x00db, 0, &mmDAGB0_RESERVE65[0], sizeof(mmDAGB0_RESERVE65)/sizeof(mmDAGB0_RESERVE65[0]), 0, 0 }, + { "mmDAGB0_RESERVE66", REG_MMIO, 0x00dc, 0, &mmDAGB0_RESERVE66[0], sizeof(mmDAGB0_RESERVE66)/sizeof(mmDAGB0_RESERVE66[0]), 0, 0 }, + { "mmDAGB0_RESERVE67", REG_MMIO, 0x00dd, 0, &mmDAGB0_RESERVE67[0], sizeof(mmDAGB0_RESERVE67)/sizeof(mmDAGB0_RESERVE67[0]), 0, 0 }, + { "mmDAGB0_RESERVE68", REG_MMIO, 0x00de, 0, &mmDAGB0_RESERVE68[0], sizeof(mmDAGB0_RESERVE68)/sizeof(mmDAGB0_RESERVE68[0]), 0, 0 }, + { "mmDAGB0_RESERVE69", REG_MMIO, 0x00df, 0, &mmDAGB0_RESERVE69[0], sizeof(mmDAGB0_RESERVE69)/sizeof(mmDAGB0_RESERVE69[0]), 0, 0 }, + { "mmDAGB0_RESERVE70", REG_MMIO, 0x00e0, 0, &mmDAGB0_RESERVE70[0], sizeof(mmDAGB0_RESERVE70)/sizeof(mmDAGB0_RESERVE70[0]), 0, 0 }, + { "mmDAGB0_RESERVE71", REG_MMIO, 0x00e1, 0, &mmDAGB0_RESERVE71[0], sizeof(mmDAGB0_RESERVE71)/sizeof(mmDAGB0_RESERVE71[0]), 0, 0 }, + { "mmDAGB0_RESERVE72", REG_MMIO, 0x00e2, 0, &mmDAGB0_RESERVE72[0], sizeof(mmDAGB0_RESERVE72)/sizeof(mmDAGB0_RESERVE72[0]), 0, 0 }, + { "mmDAGB0_RESERVE73", REG_MMIO, 0x00e3, 0, &mmDAGB0_RESERVE73[0], sizeof(mmDAGB0_RESERVE73)/sizeof(mmDAGB0_RESERVE73[0]), 0, 0 }, + { "mmDAGB0_RESERVE74", REG_MMIO, 0x00e4, 0, &mmDAGB0_RESERVE74[0], sizeof(mmDAGB0_RESERVE74)/sizeof(mmDAGB0_RESERVE74[0]), 0, 0 }, + { "mmDAGB0_RESERVE75", REG_MMIO, 0x00e5, 0, &mmDAGB0_RESERVE75[0], sizeof(mmDAGB0_RESERVE75)/sizeof(mmDAGB0_RESERVE75[0]), 0, 0 }, + { "mmDAGB0_RESERVE76", REG_MMIO, 0x00e6, 0, &mmDAGB0_RESERVE76[0], sizeof(mmDAGB0_RESERVE76)/sizeof(mmDAGB0_RESERVE76[0]), 0, 0 }, + { "mmDAGB0_RESERVE77", REG_MMIO, 0x00e7, 0, &mmDAGB0_RESERVE77[0], sizeof(mmDAGB0_RESERVE77)/sizeof(mmDAGB0_RESERVE77[0]), 0, 0 }, + { "mmDAGB0_RESERVE78", REG_MMIO, 0x00e8, 0, &mmDAGB0_RESERVE78[0], sizeof(mmDAGB0_RESERVE78)/sizeof(mmDAGB0_RESERVE78[0]), 0, 0 }, + { "mmDAGB0_RESERVE79", REG_MMIO, 0x00e9, 0, &mmDAGB0_RESERVE79[0], sizeof(mmDAGB0_RESERVE79)/sizeof(mmDAGB0_RESERVE79[0]), 0, 0 }, + { "mmDAGB0_RESERVE80", REG_MMIO, 0x00ea, 0, &mmDAGB0_RESERVE80[0], sizeof(mmDAGB0_RESERVE80)/sizeof(mmDAGB0_RESERVE80[0]), 0, 0 }, + { "mmDAGB0_RESERVE81", REG_MMIO, 0x00eb, 0, &mmDAGB0_RESERVE81[0], sizeof(mmDAGB0_RESERVE81)/sizeof(mmDAGB0_RESERVE81[0]), 0, 0 }, + { "mmDAGB0_RESERVE82", REG_MMIO, 0x00ec, 0, &mmDAGB0_RESERVE82[0], sizeof(mmDAGB0_RESERVE82)/sizeof(mmDAGB0_RESERVE82[0]), 0, 0 }, + { "mmDAGB0_RESERVE83", REG_MMIO, 0x00ed, 0, &mmDAGB0_RESERVE83[0], sizeof(mmDAGB0_RESERVE83)/sizeof(mmDAGB0_RESERVE83[0]), 0, 0 }, + { "mmDAGB0_RESERVE84", REG_MMIO, 0x00ee, 0, &mmDAGB0_RESERVE84[0], sizeof(mmDAGB0_RESERVE84)/sizeof(mmDAGB0_RESERVE84[0]), 0, 0 }, + { "mmDAGB0_RESERVE85", REG_MMIO, 0x00ef, 0, &mmDAGB0_RESERVE85[0], sizeof(mmDAGB0_RESERVE85)/sizeof(mmDAGB0_RESERVE85[0]), 0, 0 }, + { "mmDAGB0_RESERVE86", REG_MMIO, 0x00f0, 0, &mmDAGB0_RESERVE86[0], sizeof(mmDAGB0_RESERVE86)/sizeof(mmDAGB0_RESERVE86[0]), 0, 0 }, + { "mmDAGB0_RESERVE87", REG_MMIO, 0x00f1, 0, &mmDAGB0_RESERVE87[0], sizeof(mmDAGB0_RESERVE87)/sizeof(mmDAGB0_RESERVE87[0]), 0, 0 }, + { "mmDAGB0_RESERVE88", REG_MMIO, 0x00f2, 0, &mmDAGB0_RESERVE88[0], sizeof(mmDAGB0_RESERVE88)/sizeof(mmDAGB0_RESERVE88[0]), 0, 0 }, + { "mmDAGB0_RESERVE89", REG_MMIO, 0x00f3, 0, &mmDAGB0_RESERVE89[0], sizeof(mmDAGB0_RESERVE89)/sizeof(mmDAGB0_RESERVE89[0]), 0, 0 }, + { "mmDAGB0_RESERVE90", REG_MMIO, 0x00f4, 0, &mmDAGB0_RESERVE90[0], sizeof(mmDAGB0_RESERVE90)/sizeof(mmDAGB0_RESERVE90[0]), 0, 0 }, + { "mmDAGB0_RESERVE91", REG_MMIO, 0x00f5, 0, &mmDAGB0_RESERVE91[0], sizeof(mmDAGB0_RESERVE91)/sizeof(mmDAGB0_RESERVE91[0]), 0, 0 }, + { "mmDAGB0_RESERVE92", REG_MMIO, 0x00f6, 0, &mmDAGB0_RESERVE92[0], sizeof(mmDAGB0_RESERVE92)/sizeof(mmDAGB0_RESERVE92[0]), 0, 0 }, + { "mmDAGB0_RESERVE93", REG_MMIO, 0x00f7, 0, &mmDAGB0_RESERVE93[0], sizeof(mmDAGB0_RESERVE93)/sizeof(mmDAGB0_RESERVE93[0]), 0, 0 }, + { "mmDAGB0_RESERVE94", REG_MMIO, 0x00f8, 0, &mmDAGB0_RESERVE94[0], sizeof(mmDAGB0_RESERVE94)/sizeof(mmDAGB0_RESERVE94[0]), 0, 0 }, + { "mmDAGB0_RESERVE95", REG_MMIO, 0x00f9, 0, &mmDAGB0_RESERVE95[0], sizeof(mmDAGB0_RESERVE95)/sizeof(mmDAGB0_RESERVE95[0]), 0, 0 }, + { "mmDAGB0_RESERVE96", REG_MMIO, 0x00fa, 0, &mmDAGB0_RESERVE96[0], sizeof(mmDAGB0_RESERVE96)/sizeof(mmDAGB0_RESERVE96[0]), 0, 0 }, + { "mmDAGB0_RESERVE97", REG_MMIO, 0x00fb, 0, &mmDAGB0_RESERVE97[0], sizeof(mmDAGB0_RESERVE97)/sizeof(mmDAGB0_RESERVE97[0]), 0, 0 }, + { "mmDAGB0_RESERVE98", REG_MMIO, 0x00fc, 0, &mmDAGB0_RESERVE98[0], sizeof(mmDAGB0_RESERVE98)/sizeof(mmDAGB0_RESERVE98[0]), 0, 0 }, + { "mmDAGB0_RESERVE99", REG_MMIO, 0x00fd, 0, &mmDAGB0_RESERVE99[0], sizeof(mmDAGB0_RESERVE99)/sizeof(mmDAGB0_RESERVE99[0]), 0, 0 }, + { "mmDAGB0_RESERVE100", REG_MMIO, 0x00fe, 0, &mmDAGB0_RESERVE100[0], sizeof(mmDAGB0_RESERVE100)/sizeof(mmDAGB0_RESERVE100[0]), 0, 0 }, + { "mmDAGB0_RESERVE101", REG_MMIO, 0x00ff, 0, &mmDAGB0_RESERVE101[0], sizeof(mmDAGB0_RESERVE101)/sizeof(mmDAGB0_RESERVE101[0]), 0, 0 }, + { "mmMMEA0_DRAM_RD_CLI2GRP_MAP0", REG_MMIO, 0x0100, 0, &mmMMEA0_DRAM_RD_CLI2GRP_MAP0[0], sizeof(mmMMEA0_DRAM_RD_CLI2GRP_MAP0)/sizeof(mmMMEA0_DRAM_RD_CLI2GRP_MAP0[0]), 0, 0 }, + { "mmMMEA0_DRAM_RD_CLI2GRP_MAP1", REG_MMIO, 0x0101, 0, &mmMMEA0_DRAM_RD_CLI2GRP_MAP1[0], sizeof(mmMMEA0_DRAM_RD_CLI2GRP_MAP1)/sizeof(mmMMEA0_DRAM_RD_CLI2GRP_MAP1[0]), 0, 0 }, + { "mmMMEA0_DRAM_WR_CLI2GRP_MAP0", REG_MMIO, 0x0102, 0, &mmMMEA0_DRAM_WR_CLI2GRP_MAP0[0], sizeof(mmMMEA0_DRAM_WR_CLI2GRP_MAP0)/sizeof(mmMMEA0_DRAM_WR_CLI2GRP_MAP0[0]), 0, 0 }, + { "mmMMEA0_DRAM_WR_CLI2GRP_MAP1", REG_MMIO, 0x0103, 0, &mmMMEA0_DRAM_WR_CLI2GRP_MAP1[0], sizeof(mmMMEA0_DRAM_WR_CLI2GRP_MAP1)/sizeof(mmMMEA0_DRAM_WR_CLI2GRP_MAP1[0]), 0, 0 }, + { "mmMMEA0_DRAM_RD_GRP2VC_MAP", REG_MMIO, 0x0104, 0, &mmMMEA0_DRAM_RD_GRP2VC_MAP[0], sizeof(mmMMEA0_DRAM_RD_GRP2VC_MAP)/sizeof(mmMMEA0_DRAM_RD_GRP2VC_MAP[0]), 0, 0 }, + { "mmMMEA0_DRAM_WR_GRP2VC_MAP", REG_MMIO, 0x0105, 0, &mmMMEA0_DRAM_WR_GRP2VC_MAP[0], sizeof(mmMMEA0_DRAM_WR_GRP2VC_MAP)/sizeof(mmMMEA0_DRAM_WR_GRP2VC_MAP[0]), 0, 0 }, + { "mmMMEA0_DRAM_RD_LAZY", REG_MMIO, 0x0106, 0, &mmMMEA0_DRAM_RD_LAZY[0], sizeof(mmMMEA0_DRAM_RD_LAZY)/sizeof(mmMMEA0_DRAM_RD_LAZY[0]), 0, 0 }, + { "mmMMEA0_DRAM_WR_LAZY", REG_MMIO, 0x0107, 0, &mmMMEA0_DRAM_WR_LAZY[0], sizeof(mmMMEA0_DRAM_WR_LAZY)/sizeof(mmMMEA0_DRAM_WR_LAZY[0]), 0, 0 }, + { "mmMMEA0_DRAM_RD_CAM_CNTL", REG_MMIO, 0x0108, 0, &mmMMEA0_DRAM_RD_CAM_CNTL[0], sizeof(mmMMEA0_DRAM_RD_CAM_CNTL)/sizeof(mmMMEA0_DRAM_RD_CAM_CNTL[0]), 0, 0 }, + { "mmMMEA0_DRAM_WR_CAM_CNTL", REG_MMIO, 0x0109, 0, &mmMMEA0_DRAM_WR_CAM_CNTL[0], sizeof(mmMMEA0_DRAM_WR_CAM_CNTL)/sizeof(mmMMEA0_DRAM_WR_CAM_CNTL[0]), 0, 0 }, + { "mmMMEA0_DRAM_PAGE_BURST", REG_MMIO, 0x010a, 0, &mmMMEA0_DRAM_PAGE_BURST[0], sizeof(mmMMEA0_DRAM_PAGE_BURST)/sizeof(mmMMEA0_DRAM_PAGE_BURST[0]), 0, 0 }, + { "mmMMEA0_DRAM_RD_PRI_AGE", REG_MMIO, 0x010b, 0, &mmMMEA0_DRAM_RD_PRI_AGE[0], sizeof(mmMMEA0_DRAM_RD_PRI_AGE)/sizeof(mmMMEA0_DRAM_RD_PRI_AGE[0]), 0, 0 }, + { "mmMMEA0_DRAM_WR_PRI_AGE", REG_MMIO, 0x010c, 0, &mmMMEA0_DRAM_WR_PRI_AGE[0], sizeof(mmMMEA0_DRAM_WR_PRI_AGE)/sizeof(mmMMEA0_DRAM_WR_PRI_AGE[0]), 0, 0 }, + { "mmMMEA0_DRAM_RD_PRI_QUEUING", REG_MMIO, 0x010d, 0, &mmMMEA0_DRAM_RD_PRI_QUEUING[0], sizeof(mmMMEA0_DRAM_RD_PRI_QUEUING)/sizeof(mmMMEA0_DRAM_RD_PRI_QUEUING[0]), 0, 0 }, + { "mmMMEA0_DRAM_WR_PRI_QUEUING", REG_MMIO, 0x010e, 0, &mmMMEA0_DRAM_WR_PRI_QUEUING[0], sizeof(mmMMEA0_DRAM_WR_PRI_QUEUING)/sizeof(mmMMEA0_DRAM_WR_PRI_QUEUING[0]), 0, 0 }, + { "mmMMEA0_DRAM_RD_PRI_FIXED", REG_MMIO, 0x010f, 0, &mmMMEA0_DRAM_RD_PRI_FIXED[0], sizeof(mmMMEA0_DRAM_RD_PRI_FIXED)/sizeof(mmMMEA0_DRAM_RD_PRI_FIXED[0]), 0, 0 }, + { "mmMMEA0_DRAM_WR_PRI_FIXED", REG_MMIO, 0x0110, 0, &mmMMEA0_DRAM_WR_PRI_FIXED[0], sizeof(mmMMEA0_DRAM_WR_PRI_FIXED)/sizeof(mmMMEA0_DRAM_WR_PRI_FIXED[0]), 0, 0 }, + { "mmMMEA0_DRAM_RD_PRI_URGENCY", REG_MMIO, 0x0111, 0, &mmMMEA0_DRAM_RD_PRI_URGENCY[0], sizeof(mmMMEA0_DRAM_RD_PRI_URGENCY)/sizeof(mmMMEA0_DRAM_RD_PRI_URGENCY[0]), 0, 0 }, + { "mmMMEA0_DRAM_WR_PRI_URGENCY", REG_MMIO, 0x0112, 0, &mmMMEA0_DRAM_WR_PRI_URGENCY[0], sizeof(mmMMEA0_DRAM_WR_PRI_URGENCY)/sizeof(mmMMEA0_DRAM_WR_PRI_URGENCY[0]), 0, 0 }, + { "mmMMEA0_DRAM_RD_PRI_QUANT_PRI1", REG_MMIO, 0x0113, 0, &mmMMEA0_DRAM_RD_PRI_QUANT_PRI1[0], sizeof(mmMMEA0_DRAM_RD_PRI_QUANT_PRI1)/sizeof(mmMMEA0_DRAM_RD_PRI_QUANT_PRI1[0]), 0, 0 }, + { "mmMMEA0_DRAM_RD_PRI_QUANT_PRI2", REG_MMIO, 0x0114, 0, &mmMMEA0_DRAM_RD_PRI_QUANT_PRI2[0], sizeof(mmMMEA0_DRAM_RD_PRI_QUANT_PRI2)/sizeof(mmMMEA0_DRAM_RD_PRI_QUANT_PRI2[0]), 0, 0 }, + { "mmMMEA0_DRAM_RD_PRI_QUANT_PRI3", REG_MMIO, 0x0115, 0, &mmMMEA0_DRAM_RD_PRI_QUANT_PRI3[0], sizeof(mmMMEA0_DRAM_RD_PRI_QUANT_PRI3)/sizeof(mmMMEA0_DRAM_RD_PRI_QUANT_PRI3[0]), 0, 0 }, + { "mmMMEA0_DRAM_WR_PRI_QUANT_PRI1", REG_MMIO, 0x0116, 0, &mmMMEA0_DRAM_WR_PRI_QUANT_PRI1[0], sizeof(mmMMEA0_DRAM_WR_PRI_QUANT_PRI1)/sizeof(mmMMEA0_DRAM_WR_PRI_QUANT_PRI1[0]), 0, 0 }, + { "mmMMEA0_DRAM_WR_PRI_QUANT_PRI2", REG_MMIO, 0x0117, 0, &mmMMEA0_DRAM_WR_PRI_QUANT_PRI2[0], sizeof(mmMMEA0_DRAM_WR_PRI_QUANT_PRI2)/sizeof(mmMMEA0_DRAM_WR_PRI_QUANT_PRI2[0]), 0, 0 }, + { "mmMMEA0_DRAM_WR_PRI_QUANT_PRI3", REG_MMIO, 0x0118, 0, &mmMMEA0_DRAM_WR_PRI_QUANT_PRI3[0], sizeof(mmMMEA0_DRAM_WR_PRI_QUANT_PRI3)/sizeof(mmMMEA0_DRAM_WR_PRI_QUANT_PRI3[0]), 0, 0 }, + { "mmMMEA0_ADDRNORM_BASE_ADDR0", REG_MMIO, 0x0132, 0, &mmMMEA0_ADDRNORM_BASE_ADDR0[0], sizeof(mmMMEA0_ADDRNORM_BASE_ADDR0)/sizeof(mmMMEA0_ADDRNORM_BASE_ADDR0[0]), 0, 0 }, + { "mmMMEA0_ADDRNORM_LIMIT_ADDR0", REG_MMIO, 0x0133, 0, &mmMMEA0_ADDRNORM_LIMIT_ADDR0[0], sizeof(mmMMEA0_ADDRNORM_LIMIT_ADDR0)/sizeof(mmMMEA0_ADDRNORM_LIMIT_ADDR0[0]), 0, 0 }, + { "mmMMEA0_ADDRNORM_BASE_ADDR1", REG_MMIO, 0x0134, 0, &mmMMEA0_ADDRNORM_BASE_ADDR1[0], sizeof(mmMMEA0_ADDRNORM_BASE_ADDR1)/sizeof(mmMMEA0_ADDRNORM_BASE_ADDR1[0]), 0, 0 }, + { "mmMMEA0_ADDRNORM_LIMIT_ADDR1", REG_MMIO, 0x0135, 0, &mmMMEA0_ADDRNORM_LIMIT_ADDR1[0], sizeof(mmMMEA0_ADDRNORM_LIMIT_ADDR1)/sizeof(mmMMEA0_ADDRNORM_LIMIT_ADDR1[0]), 0, 0 }, + { "mmMMEA0_ADDRNORM_OFFSET_ADDR1", REG_MMIO, 0x0136, 0, &mmMMEA0_ADDRNORM_OFFSET_ADDR1[0], sizeof(mmMMEA0_ADDRNORM_OFFSET_ADDR1)/sizeof(mmMMEA0_ADDRNORM_OFFSET_ADDR1[0]), 0, 0 }, + { "mmMMEA0_ADDRNORM_HOLE_CNTL", REG_MMIO, 0x0141, 0, &mmMMEA0_ADDRNORM_HOLE_CNTL[0], sizeof(mmMMEA0_ADDRNORM_HOLE_CNTL)/sizeof(mmMMEA0_ADDRNORM_HOLE_CNTL[0]), 0, 0 }, + { "mmMMEA0_ADDRDEC_BANK_CFG", REG_MMIO, 0x0142, 0, &mmMMEA0_ADDRDEC_BANK_CFG[0], sizeof(mmMMEA0_ADDRDEC_BANK_CFG)/sizeof(mmMMEA0_ADDRDEC_BANK_CFG[0]), 0, 0 }, + { "mmMMEA0_ADDRDEC_MISC_CFG", REG_MMIO, 0x0143, 0, &mmMMEA0_ADDRDEC_MISC_CFG[0], sizeof(mmMMEA0_ADDRDEC_MISC_CFG)/sizeof(mmMMEA0_ADDRDEC_MISC_CFG[0]), 0, 0 }, + { "mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0", REG_MMIO, 0x0144, 0, &mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0[0], sizeof(mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0)/sizeof(mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0[0]), 0, 0 }, + { "mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1", REG_MMIO, 0x0145, 0, &mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1[0], sizeof(mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1)/sizeof(mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1[0]), 0, 0 }, + { "mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2", REG_MMIO, 0x0146, 0, &mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2[0], sizeof(mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2)/sizeof(mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2[0]), 0, 0 }, + { "mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3", REG_MMIO, 0x0147, 0, &mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3[0], sizeof(mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3)/sizeof(mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3[0]), 0, 0 }, + { "mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4", REG_MMIO, 0x0148, 0, &mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4[0], sizeof(mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4)/sizeof(mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4[0]), 0, 0 }, + { "mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC", REG_MMIO, 0x0149, 0, &mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC[0], sizeof(mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC)/sizeof(mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC[0]), 0, 0 }, + { "mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2", REG_MMIO, 0x014a, 0, &mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2[0], sizeof(mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2)/sizeof(mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2[0]), 0, 0 }, + { "mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0", REG_MMIO, 0x014b, 0, &mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0[0], sizeof(mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0)/sizeof(mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0[0]), 0, 0 }, + { "mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1", REG_MMIO, 0x014c, 0, &mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1[0], sizeof(mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1)/sizeof(mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1[0]), 0, 0 }, + { "mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE", REG_MMIO, 0x014d, 0, &mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE[0], sizeof(mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE)/sizeof(mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE[0]), 0, 0 }, + { "mmMMEA0_ADDRDEC0_BASE_ADDR_CS0", REG_MMIO, 0x0158, 0, &mmMMEA0_ADDRDEC0_BASE_ADDR_CS0[0], sizeof(mmMMEA0_ADDRDEC0_BASE_ADDR_CS0)/sizeof(mmMMEA0_ADDRDEC0_BASE_ADDR_CS0[0]), 0, 0 }, + { "mmMMEA0_ADDRDEC0_BASE_ADDR_CS1", REG_MMIO, 0x0159, 0, &mmMMEA0_ADDRDEC0_BASE_ADDR_CS1[0], sizeof(mmMMEA0_ADDRDEC0_BASE_ADDR_CS1)/sizeof(mmMMEA0_ADDRDEC0_BASE_ADDR_CS1[0]), 0, 0 }, + { "mmMMEA0_ADDRDEC0_BASE_ADDR_CS2", REG_MMIO, 0x015a, 0, &mmMMEA0_ADDRDEC0_BASE_ADDR_CS2[0], sizeof(mmMMEA0_ADDRDEC0_BASE_ADDR_CS2)/sizeof(mmMMEA0_ADDRDEC0_BASE_ADDR_CS2[0]), 0, 0 }, + { "mmMMEA0_ADDRDEC0_BASE_ADDR_CS3", REG_MMIO, 0x015b, 0, &mmMMEA0_ADDRDEC0_BASE_ADDR_CS3[0], sizeof(mmMMEA0_ADDRDEC0_BASE_ADDR_CS3)/sizeof(mmMMEA0_ADDRDEC0_BASE_ADDR_CS3[0]), 0, 0 }, + { "mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0", REG_MMIO, 0x015c, 0, &mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0[0], sizeof(mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0)/sizeof(mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0[0]), 0, 0 }, + { "mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1", REG_MMIO, 0x015d, 0, &mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1[0], sizeof(mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1)/sizeof(mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1[0]), 0, 0 }, + { "mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2", REG_MMIO, 0x015e, 0, &mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2[0], sizeof(mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2)/sizeof(mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2[0]), 0, 0 }, + { "mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3", REG_MMIO, 0x015f, 0, &mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3[0], sizeof(mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3)/sizeof(mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3[0]), 0, 0 }, + { "mmMMEA0_ADDRDEC0_ADDR_MASK_CS01", REG_MMIO, 0x0160, 0, &mmMMEA0_ADDRDEC0_ADDR_MASK_CS01[0], sizeof(mmMMEA0_ADDRDEC0_ADDR_MASK_CS01)/sizeof(mmMMEA0_ADDRDEC0_ADDR_MASK_CS01[0]), 0, 0 }, + { "mmMMEA0_ADDRDEC0_ADDR_MASK_CS23", REG_MMIO, 0x0161, 0, &mmMMEA0_ADDRDEC0_ADDR_MASK_CS23[0], sizeof(mmMMEA0_ADDRDEC0_ADDR_MASK_CS23)/sizeof(mmMMEA0_ADDRDEC0_ADDR_MASK_CS23[0]), 0, 0 }, + { "mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01", REG_MMIO, 0x0162, 0, &mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01[0], sizeof(mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01)/sizeof(mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01[0]), 0, 0 }, + { "mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23", REG_MMIO, 0x0163, 0, &mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23[0], sizeof(mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23)/sizeof(mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23[0]), 0, 0 }, + { "mmMMEA0_ADDRDEC0_ADDR_CFG_CS01", REG_MMIO, 0x0164, 0, &mmMMEA0_ADDRDEC0_ADDR_CFG_CS01[0], sizeof(mmMMEA0_ADDRDEC0_ADDR_CFG_CS01)/sizeof(mmMMEA0_ADDRDEC0_ADDR_CFG_CS01[0]), 0, 0 }, + { "mmMMEA0_ADDRDEC0_ADDR_CFG_CS23", REG_MMIO, 0x0165, 0, &mmMMEA0_ADDRDEC0_ADDR_CFG_CS23[0], sizeof(mmMMEA0_ADDRDEC0_ADDR_CFG_CS23)/sizeof(mmMMEA0_ADDRDEC0_ADDR_CFG_CS23[0]), 0, 0 }, + { "mmMMEA0_ADDRDEC0_ADDR_SEL_CS01", REG_MMIO, 0x0166, 0, &mmMMEA0_ADDRDEC0_ADDR_SEL_CS01[0], sizeof(mmMMEA0_ADDRDEC0_ADDR_SEL_CS01)/sizeof(mmMMEA0_ADDRDEC0_ADDR_SEL_CS01[0]), 0, 0 }, + { "mmMMEA0_ADDRDEC0_ADDR_SEL_CS23", REG_MMIO, 0x0167, 0, &mmMMEA0_ADDRDEC0_ADDR_SEL_CS23[0], sizeof(mmMMEA0_ADDRDEC0_ADDR_SEL_CS23)/sizeof(mmMMEA0_ADDRDEC0_ADDR_SEL_CS23[0]), 0, 0 }, + { "mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01", REG_MMIO, 0x0168, 0, &mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01[0], sizeof(mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01)/sizeof(mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01[0]), 0, 0 }, + { "mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23", REG_MMIO, 0x0169, 0, &mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23[0], sizeof(mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23)/sizeof(mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23[0]), 0, 0 }, + { "mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01", REG_MMIO, 0x016a, 0, &mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01[0], sizeof(mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01)/sizeof(mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01[0]), 0, 0 }, + { "mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23", REG_MMIO, 0x016b, 0, &mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23[0], sizeof(mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23)/sizeof(mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23[0]), 0, 0 }, + { "mmMMEA0_ADDRDEC0_RM_SEL_CS01", REG_MMIO, 0x016c, 0, &mmMMEA0_ADDRDEC0_RM_SEL_CS01[0], sizeof(mmMMEA0_ADDRDEC0_RM_SEL_CS01)/sizeof(mmMMEA0_ADDRDEC0_RM_SEL_CS01[0]), 0, 0 }, + { "mmMMEA0_ADDRDEC0_RM_SEL_CS23", REG_MMIO, 0x016d, 0, &mmMMEA0_ADDRDEC0_RM_SEL_CS23[0], sizeof(mmMMEA0_ADDRDEC0_RM_SEL_CS23)/sizeof(mmMMEA0_ADDRDEC0_RM_SEL_CS23[0]), 0, 0 }, + { "mmMMEA0_ADDRDEC0_RM_SEL_SECCS01", REG_MMIO, 0x016e, 0, &mmMMEA0_ADDRDEC0_RM_SEL_SECCS01[0], sizeof(mmMMEA0_ADDRDEC0_RM_SEL_SECCS01)/sizeof(mmMMEA0_ADDRDEC0_RM_SEL_SECCS01[0]), 0, 0 }, + { "mmMMEA0_ADDRDEC0_RM_SEL_SECCS23", REG_MMIO, 0x016f, 0, &mmMMEA0_ADDRDEC0_RM_SEL_SECCS23[0], sizeof(mmMMEA0_ADDRDEC0_RM_SEL_SECCS23)/sizeof(mmMMEA0_ADDRDEC0_RM_SEL_SECCS23[0]), 0, 0 }, + { "mmMMEA0_ADDRDEC1_BASE_ADDR_CS0", REG_MMIO, 0x0170, 0, &mmMMEA0_ADDRDEC1_BASE_ADDR_CS0[0], sizeof(mmMMEA0_ADDRDEC1_BASE_ADDR_CS0)/sizeof(mmMMEA0_ADDRDEC1_BASE_ADDR_CS0[0]), 0, 0 }, + { "mmMMEA0_ADDRDEC1_BASE_ADDR_CS1", REG_MMIO, 0x0171, 0, &mmMMEA0_ADDRDEC1_BASE_ADDR_CS1[0], sizeof(mmMMEA0_ADDRDEC1_BASE_ADDR_CS1)/sizeof(mmMMEA0_ADDRDEC1_BASE_ADDR_CS1[0]), 0, 0 }, + { "mmMMEA0_ADDRDEC1_BASE_ADDR_CS2", REG_MMIO, 0x0172, 0, &mmMMEA0_ADDRDEC1_BASE_ADDR_CS2[0], sizeof(mmMMEA0_ADDRDEC1_BASE_ADDR_CS2)/sizeof(mmMMEA0_ADDRDEC1_BASE_ADDR_CS2[0]), 0, 0 }, + { "mmMMEA0_ADDRDEC1_BASE_ADDR_CS3", REG_MMIO, 0x0173, 0, &mmMMEA0_ADDRDEC1_BASE_ADDR_CS3[0], sizeof(mmMMEA0_ADDRDEC1_BASE_ADDR_CS3)/sizeof(mmMMEA0_ADDRDEC1_BASE_ADDR_CS3[0]), 0, 0 }, + { "mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0", REG_MMIO, 0x0174, 0, &mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0[0], sizeof(mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0)/sizeof(mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0[0]), 0, 0 }, + { "mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1", REG_MMIO, 0x0175, 0, &mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1[0], sizeof(mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1)/sizeof(mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1[0]), 0, 0 }, + { "mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2", REG_MMIO, 0x0176, 0, &mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2[0], sizeof(mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2)/sizeof(mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2[0]), 0, 0 }, + { "mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3", REG_MMIO, 0x0177, 0, &mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3[0], sizeof(mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3)/sizeof(mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3[0]), 0, 0 }, + { "mmMMEA0_ADDRDEC1_ADDR_MASK_CS01", REG_MMIO, 0x0178, 0, &mmMMEA0_ADDRDEC1_ADDR_MASK_CS01[0], sizeof(mmMMEA0_ADDRDEC1_ADDR_MASK_CS01)/sizeof(mmMMEA0_ADDRDEC1_ADDR_MASK_CS01[0]), 0, 0 }, + { "mmMMEA0_ADDRDEC1_ADDR_MASK_CS23", REG_MMIO, 0x0179, 0, &mmMMEA0_ADDRDEC1_ADDR_MASK_CS23[0], sizeof(mmMMEA0_ADDRDEC1_ADDR_MASK_CS23)/sizeof(mmMMEA0_ADDRDEC1_ADDR_MASK_CS23[0]), 0, 0 }, + { "mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01", REG_MMIO, 0x017a, 0, &mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01[0], sizeof(mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01)/sizeof(mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01[0]), 0, 0 }, + { "mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23", REG_MMIO, 0x017b, 0, &mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23[0], sizeof(mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23)/sizeof(mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23[0]), 0, 0 }, + { "mmMMEA0_ADDRDEC1_ADDR_CFG_CS01", REG_MMIO, 0x017c, 0, &mmMMEA0_ADDRDEC1_ADDR_CFG_CS01[0], sizeof(mmMMEA0_ADDRDEC1_ADDR_CFG_CS01)/sizeof(mmMMEA0_ADDRDEC1_ADDR_CFG_CS01[0]), 0, 0 }, + { "mmMMEA0_ADDRDEC1_ADDR_CFG_CS23", REG_MMIO, 0x017d, 0, &mmMMEA0_ADDRDEC1_ADDR_CFG_CS23[0], sizeof(mmMMEA0_ADDRDEC1_ADDR_CFG_CS23)/sizeof(mmMMEA0_ADDRDEC1_ADDR_CFG_CS23[0]), 0, 0 }, + { "mmMMEA0_ADDRDEC1_ADDR_SEL_CS01", REG_MMIO, 0x017e, 0, &mmMMEA0_ADDRDEC1_ADDR_SEL_CS01[0], sizeof(mmMMEA0_ADDRDEC1_ADDR_SEL_CS01)/sizeof(mmMMEA0_ADDRDEC1_ADDR_SEL_CS01[0]), 0, 0 }, + { "mmMMEA0_ADDRDEC1_ADDR_SEL_CS23", REG_MMIO, 0x017f, 0, &mmMMEA0_ADDRDEC1_ADDR_SEL_CS23[0], sizeof(mmMMEA0_ADDRDEC1_ADDR_SEL_CS23)/sizeof(mmMMEA0_ADDRDEC1_ADDR_SEL_CS23[0]), 0, 0 }, + { "mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01", REG_MMIO, 0x0180, 0, &mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01[0], sizeof(mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01)/sizeof(mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01[0]), 0, 0 }, + { "mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23", REG_MMIO, 0x0181, 0, &mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23[0], sizeof(mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23)/sizeof(mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23[0]), 0, 0 }, + { "mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01", REG_MMIO, 0x0182, 0, &mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01[0], sizeof(mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01)/sizeof(mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01[0]), 0, 0 }, + { "mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23", REG_MMIO, 0x0183, 0, &mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23[0], sizeof(mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23)/sizeof(mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23[0]), 0, 0 }, + { "mmMMEA0_ADDRDEC1_RM_SEL_CS01", REG_MMIO, 0x0184, 0, &mmMMEA0_ADDRDEC1_RM_SEL_CS01[0], sizeof(mmMMEA0_ADDRDEC1_RM_SEL_CS01)/sizeof(mmMMEA0_ADDRDEC1_RM_SEL_CS01[0]), 0, 0 }, + { "mmMMEA0_ADDRDEC1_RM_SEL_CS23", REG_MMIO, 0x0185, 0, &mmMMEA0_ADDRDEC1_RM_SEL_CS23[0], sizeof(mmMMEA0_ADDRDEC1_RM_SEL_CS23)/sizeof(mmMMEA0_ADDRDEC1_RM_SEL_CS23[0]), 0, 0 }, + { "mmMMEA0_ADDRDEC1_RM_SEL_SECCS01", REG_MMIO, 0x0186, 0, &mmMMEA0_ADDRDEC1_RM_SEL_SECCS01[0], sizeof(mmMMEA0_ADDRDEC1_RM_SEL_SECCS01)/sizeof(mmMMEA0_ADDRDEC1_RM_SEL_SECCS01[0]), 0, 0 }, + { "mmMMEA0_ADDRDEC1_RM_SEL_SECCS23", REG_MMIO, 0x0187, 0, &mmMMEA0_ADDRDEC1_RM_SEL_SECCS23[0], sizeof(mmMMEA0_ADDRDEC1_RM_SEL_SECCS23)/sizeof(mmMMEA0_ADDRDEC1_RM_SEL_SECCS23[0]), 0, 0 }, + { "mmMMEA0_IO_RD_CLI2GRP_MAP0", REG_MMIO, 0x01d0, 0, &mmMMEA0_IO_RD_CLI2GRP_MAP0[0], sizeof(mmMMEA0_IO_RD_CLI2GRP_MAP0)/sizeof(mmMMEA0_IO_RD_CLI2GRP_MAP0[0]), 0, 0 }, + { "mmMMEA0_IO_RD_CLI2GRP_MAP1", REG_MMIO, 0x01d1, 0, &mmMMEA0_IO_RD_CLI2GRP_MAP1[0], sizeof(mmMMEA0_IO_RD_CLI2GRP_MAP1)/sizeof(mmMMEA0_IO_RD_CLI2GRP_MAP1[0]), 0, 0 }, + { "mmMMEA0_IO_WR_CLI2GRP_MAP0", REG_MMIO, 0x01d2, 0, &mmMMEA0_IO_WR_CLI2GRP_MAP0[0], sizeof(mmMMEA0_IO_WR_CLI2GRP_MAP0)/sizeof(mmMMEA0_IO_WR_CLI2GRP_MAP0[0]), 0, 0 }, + { "mmMMEA0_IO_WR_CLI2GRP_MAP1", REG_MMIO, 0x01d3, 0, &mmMMEA0_IO_WR_CLI2GRP_MAP1[0], sizeof(mmMMEA0_IO_WR_CLI2GRP_MAP1)/sizeof(mmMMEA0_IO_WR_CLI2GRP_MAP1[0]), 0, 0 }, + { "mmMMEA0_IO_RD_COMBINE_FLUSH", REG_MMIO, 0x01d4, 0, &mmMMEA0_IO_RD_COMBINE_FLUSH[0], sizeof(mmMMEA0_IO_RD_COMBINE_FLUSH)/sizeof(mmMMEA0_IO_RD_COMBINE_FLUSH[0]), 0, 0 }, + { "mmMMEA0_IO_WR_COMBINE_FLUSH", REG_MMIO, 0x01d5, 0, &mmMMEA0_IO_WR_COMBINE_FLUSH[0], sizeof(mmMMEA0_IO_WR_COMBINE_FLUSH)/sizeof(mmMMEA0_IO_WR_COMBINE_FLUSH[0]), 0, 0 }, + { "mmMMEA0_IO_GROUP_BURST", REG_MMIO, 0x01d6, 0, &mmMMEA0_IO_GROUP_BURST[0], sizeof(mmMMEA0_IO_GROUP_BURST)/sizeof(mmMMEA0_IO_GROUP_BURST[0]), 0, 0 }, + { "mmMMEA0_IO_RD_PRI_AGE", REG_MMIO, 0x01d7, 0, &mmMMEA0_IO_RD_PRI_AGE[0], sizeof(mmMMEA0_IO_RD_PRI_AGE)/sizeof(mmMMEA0_IO_RD_PRI_AGE[0]), 0, 0 }, + { "mmMMEA0_IO_WR_PRI_AGE", REG_MMIO, 0x01d8, 0, &mmMMEA0_IO_WR_PRI_AGE[0], sizeof(mmMMEA0_IO_WR_PRI_AGE)/sizeof(mmMMEA0_IO_WR_PRI_AGE[0]), 0, 0 }, + { "mmMMEA0_IO_RD_PRI_QUEUING", REG_MMIO, 0x01d9, 0, &mmMMEA0_IO_RD_PRI_QUEUING[0], sizeof(mmMMEA0_IO_RD_PRI_QUEUING)/sizeof(mmMMEA0_IO_RD_PRI_QUEUING[0]), 0, 0 }, + { "mmMMEA0_IO_WR_PRI_QUEUING", REG_MMIO, 0x01da, 0, &mmMMEA0_IO_WR_PRI_QUEUING[0], sizeof(mmMMEA0_IO_WR_PRI_QUEUING)/sizeof(mmMMEA0_IO_WR_PRI_QUEUING[0]), 0, 0 }, + { "mmMMEA0_IO_RD_PRI_FIXED", REG_MMIO, 0x01db, 0, &mmMMEA0_IO_RD_PRI_FIXED[0], sizeof(mmMMEA0_IO_RD_PRI_FIXED)/sizeof(mmMMEA0_IO_RD_PRI_FIXED[0]), 0, 0 }, + { "mmMMEA0_IO_WR_PRI_FIXED", REG_MMIO, 0x01dc, 0, &mmMMEA0_IO_WR_PRI_FIXED[0], sizeof(mmMMEA0_IO_WR_PRI_FIXED)/sizeof(mmMMEA0_IO_WR_PRI_FIXED[0]), 0, 0 }, + { "mmMMEA0_IO_RD_PRI_URGENCY", REG_MMIO, 0x01dd, 0, &mmMMEA0_IO_RD_PRI_URGENCY[0], sizeof(mmMMEA0_IO_RD_PRI_URGENCY)/sizeof(mmMMEA0_IO_RD_PRI_URGENCY[0]), 0, 0 }, + { "mmMMEA0_IO_WR_PRI_URGENCY", REG_MMIO, 0x01de, 0, &mmMMEA0_IO_WR_PRI_URGENCY[0], sizeof(mmMMEA0_IO_WR_PRI_URGENCY)/sizeof(mmMMEA0_IO_WR_PRI_URGENCY[0]), 0, 0 }, + { "mmMMEA0_IO_RD_PRI_URGENCY_MASK", REG_MMIO, 0x01df, 0, &mmMMEA0_IO_RD_PRI_URGENCY_MASK[0], sizeof(mmMMEA0_IO_RD_PRI_URGENCY_MASK)/sizeof(mmMMEA0_IO_RD_PRI_URGENCY_MASK[0]), 0, 0 }, + { "mmMMEA0_IO_WR_PRI_URGENCY_MASK", REG_MMIO, 0x01e0, 0, &mmMMEA0_IO_WR_PRI_URGENCY_MASK[0], sizeof(mmMMEA0_IO_WR_PRI_URGENCY_MASK)/sizeof(mmMMEA0_IO_WR_PRI_URGENCY_MASK[0]), 0, 0 }, + { "mmMMEA0_IO_RD_PRI_QUANT_PRI1", REG_MMIO, 0x01e1, 0, &mmMMEA0_IO_RD_PRI_QUANT_PRI1[0], sizeof(mmMMEA0_IO_RD_PRI_QUANT_PRI1)/sizeof(mmMMEA0_IO_RD_PRI_QUANT_PRI1[0]), 0, 0 }, + { "mmMMEA0_IO_RD_PRI_QUANT_PRI2", REG_MMIO, 0x01e2, 0, &mmMMEA0_IO_RD_PRI_QUANT_PRI2[0], sizeof(mmMMEA0_IO_RD_PRI_QUANT_PRI2)/sizeof(mmMMEA0_IO_RD_PRI_QUANT_PRI2[0]), 0, 0 }, + { "mmMMEA0_IO_RD_PRI_QUANT_PRI3", REG_MMIO, 0x01e3, 0, &mmMMEA0_IO_RD_PRI_QUANT_PRI3[0], sizeof(mmMMEA0_IO_RD_PRI_QUANT_PRI3)/sizeof(mmMMEA0_IO_RD_PRI_QUANT_PRI3[0]), 0, 0 }, + { "mmMMEA0_IO_WR_PRI_QUANT_PRI1", REG_MMIO, 0x01e4, 0, &mmMMEA0_IO_WR_PRI_QUANT_PRI1[0], sizeof(mmMMEA0_IO_WR_PRI_QUANT_PRI1)/sizeof(mmMMEA0_IO_WR_PRI_QUANT_PRI1[0]), 0, 0 }, + { "mmMMEA0_IO_WR_PRI_QUANT_PRI2", REG_MMIO, 0x01e5, 0, &mmMMEA0_IO_WR_PRI_QUANT_PRI2[0], sizeof(mmMMEA0_IO_WR_PRI_QUANT_PRI2)/sizeof(mmMMEA0_IO_WR_PRI_QUANT_PRI2[0]), 0, 0 }, + { "mmMMEA0_IO_WR_PRI_QUANT_PRI3", REG_MMIO, 0x01e6, 0, &mmMMEA0_IO_WR_PRI_QUANT_PRI3[0], sizeof(mmMMEA0_IO_WR_PRI_QUANT_PRI3)/sizeof(mmMMEA0_IO_WR_PRI_QUANT_PRI3[0]), 0, 0 }, + { "mmMMEA0_SDP_ARB_DRAM", REG_MMIO, 0x01e7, 0, &mmMMEA0_SDP_ARB_DRAM[0], sizeof(mmMMEA0_SDP_ARB_DRAM)/sizeof(mmMMEA0_SDP_ARB_DRAM[0]), 0, 0 }, + { "mmMMEA0_SDP_ARB_FINAL", REG_MMIO, 0x01e9, 0, &mmMMEA0_SDP_ARB_FINAL[0], sizeof(mmMMEA0_SDP_ARB_FINAL)/sizeof(mmMMEA0_SDP_ARB_FINAL[0]), 0, 0 }, + { "mmMMEA0_SDP_DRAM_PRIORITY", REG_MMIO, 0x01ea, 0, &mmMMEA0_SDP_DRAM_PRIORITY[0], sizeof(mmMMEA0_SDP_DRAM_PRIORITY)/sizeof(mmMMEA0_SDP_DRAM_PRIORITY[0]), 0, 0 }, + { "mmMMEA0_SDP_IO_PRIORITY", REG_MMIO, 0x01ec, 0, &mmMMEA0_SDP_IO_PRIORITY[0], sizeof(mmMMEA0_SDP_IO_PRIORITY)/sizeof(mmMMEA0_SDP_IO_PRIORITY[0]), 0, 0 }, + { "mmMMEA0_SDP_CREDITS", REG_MMIO, 0x01ed, 0, &mmMMEA0_SDP_CREDITS[0], sizeof(mmMMEA0_SDP_CREDITS)/sizeof(mmMMEA0_SDP_CREDITS[0]), 0, 0 }, + { "mmMMEA0_SDP_TAG_RESERVE0", REG_MMIO, 0x01ee, 0, &mmMMEA0_SDP_TAG_RESERVE0[0], sizeof(mmMMEA0_SDP_TAG_RESERVE0)/sizeof(mmMMEA0_SDP_TAG_RESERVE0[0]), 0, 0 }, + { "mmMMEA0_SDP_TAG_RESERVE1", REG_MMIO, 0x01ef, 0, &mmMMEA0_SDP_TAG_RESERVE1[0], sizeof(mmMMEA0_SDP_TAG_RESERVE1)/sizeof(mmMMEA0_SDP_TAG_RESERVE1[0]), 0, 0 }, + { "mmMMEA0_SDP_VCC_RESERVE0", REG_MMIO, 0x01f0, 0, &mmMMEA0_SDP_VCC_RESERVE0[0], sizeof(mmMMEA0_SDP_VCC_RESERVE0)/sizeof(mmMMEA0_SDP_VCC_RESERVE0[0]), 0, 0 }, + { "mmMMEA0_SDP_VCC_RESERVE1", REG_MMIO, 0x01f1, 0, &mmMMEA0_SDP_VCC_RESERVE1[0], sizeof(mmMMEA0_SDP_VCC_RESERVE1)/sizeof(mmMMEA0_SDP_VCC_RESERVE1[0]), 0, 0 }, + { "mmMMEA0_SDP_VCD_RESERVE0", REG_MMIO, 0x01f2, 0, &mmMMEA0_SDP_VCD_RESERVE0[0], sizeof(mmMMEA0_SDP_VCD_RESERVE0)/sizeof(mmMMEA0_SDP_VCD_RESERVE0[0]), 0, 0 }, + { "mmMMEA0_SDP_VCD_RESERVE1", REG_MMIO, 0x01f3, 0, &mmMMEA0_SDP_VCD_RESERVE1[0], sizeof(mmMMEA0_SDP_VCD_RESERVE1)/sizeof(mmMMEA0_SDP_VCD_RESERVE1[0]), 0, 0 }, + { "mmMMEA0_SDP_REQ_CNTL", REG_MMIO, 0x01f4, 0, &mmMMEA0_SDP_REQ_CNTL[0], sizeof(mmMMEA0_SDP_REQ_CNTL)/sizeof(mmMMEA0_SDP_REQ_CNTL[0]), 0, 0 }, + { "mmMMEA0_MISC", REG_MMIO, 0x01f5, 0, &mmMMEA0_MISC[0], sizeof(mmMMEA0_MISC)/sizeof(mmMMEA0_MISC[0]), 0, 0 }, + { "mmMMEA0_LATENCY_SAMPLING", REG_MMIO, 0x01f6, 0, &mmMMEA0_LATENCY_SAMPLING[0], sizeof(mmMMEA0_LATENCY_SAMPLING)/sizeof(mmMMEA0_LATENCY_SAMPLING[0]), 0, 0 }, + { "mmMMEA0_PERFCOUNTER_LO", REG_MMIO, 0x01f7, 0, &mmMMEA0_PERFCOUNTER_LO[0], sizeof(mmMMEA0_PERFCOUNTER_LO)/sizeof(mmMMEA0_PERFCOUNTER_LO[0]), 0, 0 }, + { "mmMMEA0_PERFCOUNTER_HI", REG_MMIO, 0x01f8, 0, &mmMMEA0_PERFCOUNTER_HI[0], sizeof(mmMMEA0_PERFCOUNTER_HI)/sizeof(mmMMEA0_PERFCOUNTER_HI[0]), 0, 0 }, + { "mmMMEA0_PERFCOUNTER0_CFG", REG_MMIO, 0x01f9, 0, &mmMMEA0_PERFCOUNTER0_CFG[0], sizeof(mmMMEA0_PERFCOUNTER0_CFG)/sizeof(mmMMEA0_PERFCOUNTER0_CFG[0]), 0, 0 }, + { "mmMMEA0_PERFCOUNTER1_CFG", REG_MMIO, 0x01fa, 0, &mmMMEA0_PERFCOUNTER1_CFG[0], sizeof(mmMMEA0_PERFCOUNTER1_CFG)/sizeof(mmMMEA0_PERFCOUNTER1_CFG[0]), 0, 0 }, + { "mmMMEA0_PERFCOUNTER_RSLT_CNTL", REG_MMIO, 0x01fb, 0, &mmMMEA0_PERFCOUNTER_RSLT_CNTL[0], sizeof(mmMMEA0_PERFCOUNTER_RSLT_CNTL)/sizeof(mmMMEA0_PERFCOUNTER_RSLT_CNTL[0]), 0, 0 }, + { "mmMMEA0_EDC_CNT", REG_MMIO, 0x0201, 0, &mmMMEA0_EDC_CNT[0], sizeof(mmMMEA0_EDC_CNT)/sizeof(mmMMEA0_EDC_CNT[0]), 0, 0 }, + { "mmMMEA0_EDC_CNT2", REG_MMIO, 0x0202, 0, &mmMMEA0_EDC_CNT2[0], sizeof(mmMMEA0_EDC_CNT2)/sizeof(mmMMEA0_EDC_CNT2[0]), 0, 0 }, + { "mmMMEA0_DSM_CNTL", REG_MMIO, 0x0203, 0, &mmMMEA0_DSM_CNTL[0], sizeof(mmMMEA0_DSM_CNTL)/sizeof(mmMMEA0_DSM_CNTL[0]), 0, 0 }, + { "mmMMEA0_DSM_CNTLA", REG_MMIO, 0x0204, 0, &mmMMEA0_DSM_CNTLA[0], sizeof(mmMMEA0_DSM_CNTLA)/sizeof(mmMMEA0_DSM_CNTLA[0]), 0, 0 }, + { "mmMMEA0_DSM_CNTLB", REG_MMIO, 0x0205, 0, NULL, 0, 0, 0 }, + { "mmMMEA0_DSM_CNTL2", REG_MMIO, 0x0206, 0, &mmMMEA0_DSM_CNTL2[0], sizeof(mmMMEA0_DSM_CNTL2)/sizeof(mmMMEA0_DSM_CNTL2[0]), 0, 0 }, + { "mmMMEA0_DSM_CNTL2A", REG_MMIO, 0x0207, 0, &mmMMEA0_DSM_CNTL2A[0], sizeof(mmMMEA0_DSM_CNTL2A)/sizeof(mmMMEA0_DSM_CNTL2A[0]), 0, 0 }, + { "mmMMEA0_DSM_CNTL2B", REG_MMIO, 0x0208, 0, NULL, 0, 0, 0 }, + { "mmMMEA0_CGTT_CLK_CTRL", REG_MMIO, 0x020a, 0, &mmMMEA0_CGTT_CLK_CTRL[0], sizeof(mmMMEA0_CGTT_CLK_CTRL)/sizeof(mmMMEA0_CGTT_CLK_CTRL[0]), 0, 0 }, + { "mmMMEA0_EDC_MODE", REG_MMIO, 0x020b, 0, &mmMMEA0_EDC_MODE[0], sizeof(mmMMEA0_EDC_MODE)/sizeof(mmMMEA0_EDC_MODE[0]), 0, 0 }, + { "mmMMEA0_ERR_STATUS", REG_MMIO, 0x020c, 0, &mmMMEA0_ERR_STATUS[0], sizeof(mmMMEA0_ERR_STATUS)/sizeof(mmMMEA0_ERR_STATUS[0]), 0, 0 }, + { "mmMMEA0_MISC2", REG_MMIO, 0x020d, 0, &mmMMEA0_MISC2[0], sizeof(mmMMEA0_MISC2)/sizeof(mmMMEA0_MISC2[0]), 0, 0 }, + { "mmMMEA1_DRAM_RD_CLI2GRP_MAP0", REG_MMIO, 0x0240, 0, &mmMMEA1_DRAM_RD_CLI2GRP_MAP0[0], sizeof(mmMMEA1_DRAM_RD_CLI2GRP_MAP0)/sizeof(mmMMEA1_DRAM_RD_CLI2GRP_MAP0[0]), 0, 0 }, + { "mmMMEA1_DRAM_RD_CLI2GRP_MAP1", REG_MMIO, 0x0241, 0, &mmMMEA1_DRAM_RD_CLI2GRP_MAP1[0], sizeof(mmMMEA1_DRAM_RD_CLI2GRP_MAP1)/sizeof(mmMMEA1_DRAM_RD_CLI2GRP_MAP1[0]), 0, 0 }, + { "mmMMEA1_DRAM_WR_CLI2GRP_MAP0", REG_MMIO, 0x0242, 0, &mmMMEA1_DRAM_WR_CLI2GRP_MAP0[0], sizeof(mmMMEA1_DRAM_WR_CLI2GRP_MAP0)/sizeof(mmMMEA1_DRAM_WR_CLI2GRP_MAP0[0]), 0, 0 }, + { "mmMMEA1_DRAM_WR_CLI2GRP_MAP1", REG_MMIO, 0x0243, 0, &mmMMEA1_DRAM_WR_CLI2GRP_MAP1[0], sizeof(mmMMEA1_DRAM_WR_CLI2GRP_MAP1)/sizeof(mmMMEA1_DRAM_WR_CLI2GRP_MAP1[0]), 0, 0 }, + { "mmMMEA1_DRAM_RD_GRP2VC_MAP", REG_MMIO, 0x0244, 0, &mmMMEA1_DRAM_RD_GRP2VC_MAP[0], sizeof(mmMMEA1_DRAM_RD_GRP2VC_MAP)/sizeof(mmMMEA1_DRAM_RD_GRP2VC_MAP[0]), 0, 0 }, + { "mmMMEA1_DRAM_WR_GRP2VC_MAP", REG_MMIO, 0x0245, 0, &mmMMEA1_DRAM_WR_GRP2VC_MAP[0], sizeof(mmMMEA1_DRAM_WR_GRP2VC_MAP)/sizeof(mmMMEA1_DRAM_WR_GRP2VC_MAP[0]), 0, 0 }, + { "mmMMEA1_DRAM_RD_LAZY", REG_MMIO, 0x0246, 0, &mmMMEA1_DRAM_RD_LAZY[0], sizeof(mmMMEA1_DRAM_RD_LAZY)/sizeof(mmMMEA1_DRAM_RD_LAZY[0]), 0, 0 }, + { "mmMMEA1_DRAM_WR_LAZY", REG_MMIO, 0x0247, 0, &mmMMEA1_DRAM_WR_LAZY[0], sizeof(mmMMEA1_DRAM_WR_LAZY)/sizeof(mmMMEA1_DRAM_WR_LAZY[0]), 0, 0 }, + { "mmMMEA1_DRAM_RD_CAM_CNTL", REG_MMIO, 0x0248, 0, &mmMMEA1_DRAM_RD_CAM_CNTL[0], sizeof(mmMMEA1_DRAM_RD_CAM_CNTL)/sizeof(mmMMEA1_DRAM_RD_CAM_CNTL[0]), 0, 0 }, + { "mmMMEA1_DRAM_WR_CAM_CNTL", REG_MMIO, 0x0249, 0, &mmMMEA1_DRAM_WR_CAM_CNTL[0], sizeof(mmMMEA1_DRAM_WR_CAM_CNTL)/sizeof(mmMMEA1_DRAM_WR_CAM_CNTL[0]), 0, 0 }, + { "mmMMEA1_DRAM_PAGE_BURST", REG_MMIO, 0x024a, 0, &mmMMEA1_DRAM_PAGE_BURST[0], sizeof(mmMMEA1_DRAM_PAGE_BURST)/sizeof(mmMMEA1_DRAM_PAGE_BURST[0]), 0, 0 }, + { "mmMMEA1_DRAM_RD_PRI_AGE", REG_MMIO, 0x024b, 0, &mmMMEA1_DRAM_RD_PRI_AGE[0], sizeof(mmMMEA1_DRAM_RD_PRI_AGE)/sizeof(mmMMEA1_DRAM_RD_PRI_AGE[0]), 0, 0 }, + { "mmMMEA1_DRAM_WR_PRI_AGE", REG_MMIO, 0x024c, 0, &mmMMEA1_DRAM_WR_PRI_AGE[0], sizeof(mmMMEA1_DRAM_WR_PRI_AGE)/sizeof(mmMMEA1_DRAM_WR_PRI_AGE[0]), 0, 0 }, + { "mmMMEA1_DRAM_RD_PRI_QUEUING", REG_MMIO, 0x024d, 0, &mmMMEA1_DRAM_RD_PRI_QUEUING[0], sizeof(mmMMEA1_DRAM_RD_PRI_QUEUING)/sizeof(mmMMEA1_DRAM_RD_PRI_QUEUING[0]), 0, 0 }, + { "mmMMEA1_DRAM_WR_PRI_QUEUING", REG_MMIO, 0x024e, 0, &mmMMEA1_DRAM_WR_PRI_QUEUING[0], sizeof(mmMMEA1_DRAM_WR_PRI_QUEUING)/sizeof(mmMMEA1_DRAM_WR_PRI_QUEUING[0]), 0, 0 }, + { "mmMMEA1_DRAM_RD_PRI_FIXED", REG_MMIO, 0x024f, 0, &mmMMEA1_DRAM_RD_PRI_FIXED[0], sizeof(mmMMEA1_DRAM_RD_PRI_FIXED)/sizeof(mmMMEA1_DRAM_RD_PRI_FIXED[0]), 0, 0 }, + { "mmMMEA1_DRAM_WR_PRI_FIXED", REG_MMIO, 0x0250, 0, &mmMMEA1_DRAM_WR_PRI_FIXED[0], sizeof(mmMMEA1_DRAM_WR_PRI_FIXED)/sizeof(mmMMEA1_DRAM_WR_PRI_FIXED[0]), 0, 0 }, + { "mmMMEA1_DRAM_RD_PRI_URGENCY", REG_MMIO, 0x0251, 0, &mmMMEA1_DRAM_RD_PRI_URGENCY[0], sizeof(mmMMEA1_DRAM_RD_PRI_URGENCY)/sizeof(mmMMEA1_DRAM_RD_PRI_URGENCY[0]), 0, 0 }, + { "mmMMEA1_DRAM_WR_PRI_URGENCY", REG_MMIO, 0x0252, 0, &mmMMEA1_DRAM_WR_PRI_URGENCY[0], sizeof(mmMMEA1_DRAM_WR_PRI_URGENCY)/sizeof(mmMMEA1_DRAM_WR_PRI_URGENCY[0]), 0, 0 }, + { "mmMMEA1_DRAM_RD_PRI_QUANT_PRI1", REG_MMIO, 0x0253, 0, &mmMMEA1_DRAM_RD_PRI_QUANT_PRI1[0], sizeof(mmMMEA1_DRAM_RD_PRI_QUANT_PRI1)/sizeof(mmMMEA1_DRAM_RD_PRI_QUANT_PRI1[0]), 0, 0 }, + { "mmMMEA1_DRAM_RD_PRI_QUANT_PRI2", REG_MMIO, 0x0254, 0, &mmMMEA1_DRAM_RD_PRI_QUANT_PRI2[0], sizeof(mmMMEA1_DRAM_RD_PRI_QUANT_PRI2)/sizeof(mmMMEA1_DRAM_RD_PRI_QUANT_PRI2[0]), 0, 0 }, + { "mmMMEA1_DRAM_RD_PRI_QUANT_PRI3", REG_MMIO, 0x0255, 0, &mmMMEA1_DRAM_RD_PRI_QUANT_PRI3[0], sizeof(mmMMEA1_DRAM_RD_PRI_QUANT_PRI3)/sizeof(mmMMEA1_DRAM_RD_PRI_QUANT_PRI3[0]), 0, 0 }, + { "mmMMEA1_DRAM_WR_PRI_QUANT_PRI1", REG_MMIO, 0x0256, 0, &mmMMEA1_DRAM_WR_PRI_QUANT_PRI1[0], sizeof(mmMMEA1_DRAM_WR_PRI_QUANT_PRI1)/sizeof(mmMMEA1_DRAM_WR_PRI_QUANT_PRI1[0]), 0, 0 }, + { "mmMMEA1_DRAM_WR_PRI_QUANT_PRI2", REG_MMIO, 0x0257, 0, &mmMMEA1_DRAM_WR_PRI_QUANT_PRI2[0], sizeof(mmMMEA1_DRAM_WR_PRI_QUANT_PRI2)/sizeof(mmMMEA1_DRAM_WR_PRI_QUANT_PRI2[0]), 0, 0 }, + { "mmMMEA1_DRAM_WR_PRI_QUANT_PRI3", REG_MMIO, 0x0258, 0, &mmMMEA1_DRAM_WR_PRI_QUANT_PRI3[0], sizeof(mmMMEA1_DRAM_WR_PRI_QUANT_PRI3)/sizeof(mmMMEA1_DRAM_WR_PRI_QUANT_PRI3[0]), 0, 0 }, + { "mmMMEA1_ADDRNORM_BASE_ADDR0", REG_MMIO, 0x0272, 0, &mmMMEA1_ADDRNORM_BASE_ADDR0[0], sizeof(mmMMEA1_ADDRNORM_BASE_ADDR0)/sizeof(mmMMEA1_ADDRNORM_BASE_ADDR0[0]), 0, 0 }, + { "mmMMEA1_ADDRNORM_LIMIT_ADDR0", REG_MMIO, 0x0273, 0, &mmMMEA1_ADDRNORM_LIMIT_ADDR0[0], sizeof(mmMMEA1_ADDRNORM_LIMIT_ADDR0)/sizeof(mmMMEA1_ADDRNORM_LIMIT_ADDR0[0]), 0, 0 }, + { "mmMMEA1_ADDRNORM_BASE_ADDR1", REG_MMIO, 0x0274, 0, &mmMMEA1_ADDRNORM_BASE_ADDR1[0], sizeof(mmMMEA1_ADDRNORM_BASE_ADDR1)/sizeof(mmMMEA1_ADDRNORM_BASE_ADDR1[0]), 0, 0 }, + { "mmMMEA1_ADDRNORM_LIMIT_ADDR1", REG_MMIO, 0x0275, 0, &mmMMEA1_ADDRNORM_LIMIT_ADDR1[0], sizeof(mmMMEA1_ADDRNORM_LIMIT_ADDR1)/sizeof(mmMMEA1_ADDRNORM_LIMIT_ADDR1[0]), 0, 0 }, + { "mmMMEA1_ADDRNORM_OFFSET_ADDR1", REG_MMIO, 0x0276, 0, &mmMMEA1_ADDRNORM_OFFSET_ADDR1[0], sizeof(mmMMEA1_ADDRNORM_OFFSET_ADDR1)/sizeof(mmMMEA1_ADDRNORM_OFFSET_ADDR1[0]), 0, 0 }, + { "mmMMEA1_ADDRNORM_HOLE_CNTL", REG_MMIO, 0x0281, 0, &mmMMEA1_ADDRNORM_HOLE_CNTL[0], sizeof(mmMMEA1_ADDRNORM_HOLE_CNTL)/sizeof(mmMMEA1_ADDRNORM_HOLE_CNTL[0]), 0, 0 }, + { "mmMMEA1_ADDRDEC_BANK_CFG", REG_MMIO, 0x0282, 0, &mmMMEA1_ADDRDEC_BANK_CFG[0], sizeof(mmMMEA1_ADDRDEC_BANK_CFG)/sizeof(mmMMEA1_ADDRDEC_BANK_CFG[0]), 0, 0 }, + { "mmMMEA1_ADDRDEC_MISC_CFG", REG_MMIO, 0x0283, 0, &mmMMEA1_ADDRDEC_MISC_CFG[0], sizeof(mmMMEA1_ADDRDEC_MISC_CFG)/sizeof(mmMMEA1_ADDRDEC_MISC_CFG[0]), 0, 0 }, + { "mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK0", REG_MMIO, 0x0284, 0, &mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK0[0], sizeof(mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK0)/sizeof(mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK0[0]), 0, 0 }, + { "mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK1", REG_MMIO, 0x0285, 0, &mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK1[0], sizeof(mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK1)/sizeof(mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK1[0]), 0, 0 }, + { "mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK2", REG_MMIO, 0x0286, 0, &mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK2[0], sizeof(mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK2)/sizeof(mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK2[0]), 0, 0 }, + { "mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK3", REG_MMIO, 0x0287, 0, &mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK3[0], sizeof(mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK3)/sizeof(mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK3[0]), 0, 0 }, + { "mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK4", REG_MMIO, 0x0288, 0, &mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK4[0], sizeof(mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK4)/sizeof(mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK4[0]), 0, 0 }, + { "mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC", REG_MMIO, 0x0289, 0, &mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC[0], sizeof(mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC)/sizeof(mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC[0]), 0, 0 }, + { "mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC2", REG_MMIO, 0x028a, 0, &mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC2[0], sizeof(mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC2)/sizeof(mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC2[0]), 0, 0 }, + { "mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS0", REG_MMIO, 0x028b, 0, &mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS0[0], sizeof(mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS0)/sizeof(mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS0[0]), 0, 0 }, + { "mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS1", REG_MMIO, 0x028c, 0, &mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS1[0], sizeof(mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS1)/sizeof(mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS1[0]), 0, 0 }, + { "mmMMEA1_ADDRDECDRAM_HARVEST_ENABLE", REG_MMIO, 0x028d, 0, &mmMMEA1_ADDRDECDRAM_HARVEST_ENABLE[0], sizeof(mmMMEA1_ADDRDECDRAM_HARVEST_ENABLE)/sizeof(mmMMEA1_ADDRDECDRAM_HARVEST_ENABLE[0]), 0, 0 }, + { "mmMMEA1_ADDRDEC0_BASE_ADDR_CS0", REG_MMIO, 0x0298, 0, &mmMMEA1_ADDRDEC0_BASE_ADDR_CS0[0], sizeof(mmMMEA1_ADDRDEC0_BASE_ADDR_CS0)/sizeof(mmMMEA1_ADDRDEC0_BASE_ADDR_CS0[0]), 0, 0 }, + { "mmMMEA1_ADDRDEC0_BASE_ADDR_CS1", REG_MMIO, 0x0299, 0, &mmMMEA1_ADDRDEC0_BASE_ADDR_CS1[0], sizeof(mmMMEA1_ADDRDEC0_BASE_ADDR_CS1)/sizeof(mmMMEA1_ADDRDEC0_BASE_ADDR_CS1[0]), 0, 0 }, + { "mmMMEA1_ADDRDEC0_BASE_ADDR_CS2", REG_MMIO, 0x029a, 0, &mmMMEA1_ADDRDEC0_BASE_ADDR_CS2[0], sizeof(mmMMEA1_ADDRDEC0_BASE_ADDR_CS2)/sizeof(mmMMEA1_ADDRDEC0_BASE_ADDR_CS2[0]), 0, 0 }, + { "mmMMEA1_ADDRDEC0_BASE_ADDR_CS3", REG_MMIO, 0x029b, 0, &mmMMEA1_ADDRDEC0_BASE_ADDR_CS3[0], sizeof(mmMMEA1_ADDRDEC0_BASE_ADDR_CS3)/sizeof(mmMMEA1_ADDRDEC0_BASE_ADDR_CS3[0]), 0, 0 }, + { "mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS0", REG_MMIO, 0x029c, 0, &mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS0[0], sizeof(mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS0)/sizeof(mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS0[0]), 0, 0 }, + { "mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS1", REG_MMIO, 0x029d, 0, &mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS1[0], sizeof(mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS1)/sizeof(mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS1[0]), 0, 0 }, + { "mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS2", REG_MMIO, 0x029e, 0, &mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS2[0], sizeof(mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS2)/sizeof(mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS2[0]), 0, 0 }, + { "mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS3", REG_MMIO, 0x029f, 0, &mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS3[0], sizeof(mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS3)/sizeof(mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS3[0]), 0, 0 }, + { "mmMMEA1_ADDRDEC0_ADDR_MASK_CS01", REG_MMIO, 0x02a0, 0, &mmMMEA1_ADDRDEC0_ADDR_MASK_CS01[0], sizeof(mmMMEA1_ADDRDEC0_ADDR_MASK_CS01)/sizeof(mmMMEA1_ADDRDEC0_ADDR_MASK_CS01[0]), 0, 0 }, + { "mmMMEA1_ADDRDEC0_ADDR_MASK_CS23", REG_MMIO, 0x02a1, 0, &mmMMEA1_ADDRDEC0_ADDR_MASK_CS23[0], sizeof(mmMMEA1_ADDRDEC0_ADDR_MASK_CS23)/sizeof(mmMMEA1_ADDRDEC0_ADDR_MASK_CS23[0]), 0, 0 }, + { "mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS01", REG_MMIO, 0x02a2, 0, &mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS01[0], sizeof(mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS01)/sizeof(mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS01[0]), 0, 0 }, + { "mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS23", REG_MMIO, 0x02a3, 0, &mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS23[0], sizeof(mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS23)/sizeof(mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS23[0]), 0, 0 }, + { "mmMMEA1_ADDRDEC0_ADDR_CFG_CS01", REG_MMIO, 0x02a4, 0, &mmMMEA1_ADDRDEC0_ADDR_CFG_CS01[0], sizeof(mmMMEA1_ADDRDEC0_ADDR_CFG_CS01)/sizeof(mmMMEA1_ADDRDEC0_ADDR_CFG_CS01[0]), 0, 0 }, + { "mmMMEA1_ADDRDEC0_ADDR_CFG_CS23", REG_MMIO, 0x02a5, 0, &mmMMEA1_ADDRDEC0_ADDR_CFG_CS23[0], sizeof(mmMMEA1_ADDRDEC0_ADDR_CFG_CS23)/sizeof(mmMMEA1_ADDRDEC0_ADDR_CFG_CS23[0]), 0, 0 }, + { "mmMMEA1_ADDRDEC0_ADDR_SEL_CS01", REG_MMIO, 0x02a6, 0, &mmMMEA1_ADDRDEC0_ADDR_SEL_CS01[0], sizeof(mmMMEA1_ADDRDEC0_ADDR_SEL_CS01)/sizeof(mmMMEA1_ADDRDEC0_ADDR_SEL_CS01[0]), 0, 0 }, + { "mmMMEA1_ADDRDEC0_ADDR_SEL_CS23", REG_MMIO, 0x02a7, 0, &mmMMEA1_ADDRDEC0_ADDR_SEL_CS23[0], sizeof(mmMMEA1_ADDRDEC0_ADDR_SEL_CS23)/sizeof(mmMMEA1_ADDRDEC0_ADDR_SEL_CS23[0]), 0, 0 }, + { "mmMMEA1_ADDRDEC0_COL_SEL_LO_CS01", REG_MMIO, 0x02a8, 0, &mmMMEA1_ADDRDEC0_COL_SEL_LO_CS01[0], sizeof(mmMMEA1_ADDRDEC0_COL_SEL_LO_CS01)/sizeof(mmMMEA1_ADDRDEC0_COL_SEL_LO_CS01[0]), 0, 0 }, + { "mmMMEA1_ADDRDEC0_COL_SEL_LO_CS23", REG_MMIO, 0x02a9, 0, &mmMMEA1_ADDRDEC0_COL_SEL_LO_CS23[0], sizeof(mmMMEA1_ADDRDEC0_COL_SEL_LO_CS23)/sizeof(mmMMEA1_ADDRDEC0_COL_SEL_LO_CS23[0]), 0, 0 }, + { "mmMMEA1_ADDRDEC0_COL_SEL_HI_CS01", REG_MMIO, 0x02aa, 0, &mmMMEA1_ADDRDEC0_COL_SEL_HI_CS01[0], sizeof(mmMMEA1_ADDRDEC0_COL_SEL_HI_CS01)/sizeof(mmMMEA1_ADDRDEC0_COL_SEL_HI_CS01[0]), 0, 0 }, + { "mmMMEA1_ADDRDEC0_COL_SEL_HI_CS23", REG_MMIO, 0x02ab, 0, &mmMMEA1_ADDRDEC0_COL_SEL_HI_CS23[0], sizeof(mmMMEA1_ADDRDEC0_COL_SEL_HI_CS23)/sizeof(mmMMEA1_ADDRDEC0_COL_SEL_HI_CS23[0]), 0, 0 }, + { "mmMMEA1_ADDRDEC0_RM_SEL_CS01", REG_MMIO, 0x02ac, 0, &mmMMEA1_ADDRDEC0_RM_SEL_CS01[0], sizeof(mmMMEA1_ADDRDEC0_RM_SEL_CS01)/sizeof(mmMMEA1_ADDRDEC0_RM_SEL_CS01[0]), 0, 0 }, + { "mmMMEA1_ADDRDEC0_RM_SEL_CS23", REG_MMIO, 0x02ad, 0, &mmMMEA1_ADDRDEC0_RM_SEL_CS23[0], sizeof(mmMMEA1_ADDRDEC0_RM_SEL_CS23)/sizeof(mmMMEA1_ADDRDEC0_RM_SEL_CS23[0]), 0, 0 }, + { "mmMMEA1_ADDRDEC0_RM_SEL_SECCS01", REG_MMIO, 0x02ae, 0, &mmMMEA1_ADDRDEC0_RM_SEL_SECCS01[0], sizeof(mmMMEA1_ADDRDEC0_RM_SEL_SECCS01)/sizeof(mmMMEA1_ADDRDEC0_RM_SEL_SECCS01[0]), 0, 0 }, + { "mmMMEA1_ADDRDEC0_RM_SEL_SECCS23", REG_MMIO, 0x02af, 0, &mmMMEA1_ADDRDEC0_RM_SEL_SECCS23[0], sizeof(mmMMEA1_ADDRDEC0_RM_SEL_SECCS23)/sizeof(mmMMEA1_ADDRDEC0_RM_SEL_SECCS23[0]), 0, 0 }, + { "mmMMEA1_ADDRDEC1_BASE_ADDR_CS0", REG_MMIO, 0x02b0, 0, &mmMMEA1_ADDRDEC1_BASE_ADDR_CS0[0], sizeof(mmMMEA1_ADDRDEC1_BASE_ADDR_CS0)/sizeof(mmMMEA1_ADDRDEC1_BASE_ADDR_CS0[0]), 0, 0 }, + { "mmMMEA1_ADDRDEC1_BASE_ADDR_CS1", REG_MMIO, 0x02b1, 0, &mmMMEA1_ADDRDEC1_BASE_ADDR_CS1[0], sizeof(mmMMEA1_ADDRDEC1_BASE_ADDR_CS1)/sizeof(mmMMEA1_ADDRDEC1_BASE_ADDR_CS1[0]), 0, 0 }, + { "mmMMEA1_ADDRDEC1_BASE_ADDR_CS2", REG_MMIO, 0x02b2, 0, &mmMMEA1_ADDRDEC1_BASE_ADDR_CS2[0], sizeof(mmMMEA1_ADDRDEC1_BASE_ADDR_CS2)/sizeof(mmMMEA1_ADDRDEC1_BASE_ADDR_CS2[0]), 0, 0 }, + { "mmMMEA1_ADDRDEC1_BASE_ADDR_CS3", REG_MMIO, 0x02b3, 0, &mmMMEA1_ADDRDEC1_BASE_ADDR_CS3[0], sizeof(mmMMEA1_ADDRDEC1_BASE_ADDR_CS3)/sizeof(mmMMEA1_ADDRDEC1_BASE_ADDR_CS3[0]), 0, 0 }, + { "mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS0", REG_MMIO, 0x02b4, 0, &mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS0[0], sizeof(mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS0)/sizeof(mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS0[0]), 0, 0 }, + { "mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS1", REG_MMIO, 0x02b5, 0, &mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS1[0], sizeof(mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS1)/sizeof(mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS1[0]), 0, 0 }, + { "mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS2", REG_MMIO, 0x02b6, 0, &mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS2[0], sizeof(mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS2)/sizeof(mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS2[0]), 0, 0 }, + { "mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS3", REG_MMIO, 0x02b7, 0, &mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS3[0], sizeof(mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS3)/sizeof(mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS3[0]), 0, 0 }, + { "mmMMEA1_ADDRDEC1_ADDR_MASK_CS01", REG_MMIO, 0x02b8, 0, &mmMMEA1_ADDRDEC1_ADDR_MASK_CS01[0], sizeof(mmMMEA1_ADDRDEC1_ADDR_MASK_CS01)/sizeof(mmMMEA1_ADDRDEC1_ADDR_MASK_CS01[0]), 0, 0 }, + { "mmMMEA1_ADDRDEC1_ADDR_MASK_CS23", REG_MMIO, 0x02b9, 0, &mmMMEA1_ADDRDEC1_ADDR_MASK_CS23[0], sizeof(mmMMEA1_ADDRDEC1_ADDR_MASK_CS23)/sizeof(mmMMEA1_ADDRDEC1_ADDR_MASK_CS23[0]), 0, 0 }, + { "mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS01", REG_MMIO, 0x02ba, 0, &mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS01[0], sizeof(mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS01)/sizeof(mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS01[0]), 0, 0 }, + { "mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS23", REG_MMIO, 0x02bb, 0, &mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS23[0], sizeof(mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS23)/sizeof(mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS23[0]), 0, 0 }, + { "mmMMEA1_ADDRDEC1_ADDR_CFG_CS01", REG_MMIO, 0x02bc, 0, &mmMMEA1_ADDRDEC1_ADDR_CFG_CS01[0], sizeof(mmMMEA1_ADDRDEC1_ADDR_CFG_CS01)/sizeof(mmMMEA1_ADDRDEC1_ADDR_CFG_CS01[0]), 0, 0 }, + { "mmMMEA1_ADDRDEC1_ADDR_CFG_CS23", REG_MMIO, 0x02bd, 0, &mmMMEA1_ADDRDEC1_ADDR_CFG_CS23[0], sizeof(mmMMEA1_ADDRDEC1_ADDR_CFG_CS23)/sizeof(mmMMEA1_ADDRDEC1_ADDR_CFG_CS23[0]), 0, 0 }, + { "mmMMEA1_ADDRDEC1_ADDR_SEL_CS01", REG_MMIO, 0x02be, 0, &mmMMEA1_ADDRDEC1_ADDR_SEL_CS01[0], sizeof(mmMMEA1_ADDRDEC1_ADDR_SEL_CS01)/sizeof(mmMMEA1_ADDRDEC1_ADDR_SEL_CS01[0]), 0, 0 }, + { "mmMMEA1_ADDRDEC1_ADDR_SEL_CS23", REG_MMIO, 0x02bf, 0, &mmMMEA1_ADDRDEC1_ADDR_SEL_CS23[0], sizeof(mmMMEA1_ADDRDEC1_ADDR_SEL_CS23)/sizeof(mmMMEA1_ADDRDEC1_ADDR_SEL_CS23[0]), 0, 0 }, + { "mmMMEA1_ADDRDEC1_COL_SEL_LO_CS01", REG_MMIO, 0x02c0, 0, &mmMMEA1_ADDRDEC1_COL_SEL_LO_CS01[0], sizeof(mmMMEA1_ADDRDEC1_COL_SEL_LO_CS01)/sizeof(mmMMEA1_ADDRDEC1_COL_SEL_LO_CS01[0]), 0, 0 }, + { "mmMMEA1_ADDRDEC1_COL_SEL_LO_CS23", REG_MMIO, 0x02c1, 0, &mmMMEA1_ADDRDEC1_COL_SEL_LO_CS23[0], sizeof(mmMMEA1_ADDRDEC1_COL_SEL_LO_CS23)/sizeof(mmMMEA1_ADDRDEC1_COL_SEL_LO_CS23[0]), 0, 0 }, + { "mmMMEA1_ADDRDEC1_COL_SEL_HI_CS01", REG_MMIO, 0x02c2, 0, &mmMMEA1_ADDRDEC1_COL_SEL_HI_CS01[0], sizeof(mmMMEA1_ADDRDEC1_COL_SEL_HI_CS01)/sizeof(mmMMEA1_ADDRDEC1_COL_SEL_HI_CS01[0]), 0, 0 }, + { "mmMMEA1_ADDRDEC1_COL_SEL_HI_CS23", REG_MMIO, 0x02c3, 0, &mmMMEA1_ADDRDEC1_COL_SEL_HI_CS23[0], sizeof(mmMMEA1_ADDRDEC1_COL_SEL_HI_CS23)/sizeof(mmMMEA1_ADDRDEC1_COL_SEL_HI_CS23[0]), 0, 0 }, + { "mmMMEA1_ADDRDEC1_RM_SEL_CS01", REG_MMIO, 0x02c4, 0, &mmMMEA1_ADDRDEC1_RM_SEL_CS01[0], sizeof(mmMMEA1_ADDRDEC1_RM_SEL_CS01)/sizeof(mmMMEA1_ADDRDEC1_RM_SEL_CS01[0]), 0, 0 }, + { "mmMMEA1_ADDRDEC1_RM_SEL_CS23", REG_MMIO, 0x02c5, 0, &mmMMEA1_ADDRDEC1_RM_SEL_CS23[0], sizeof(mmMMEA1_ADDRDEC1_RM_SEL_CS23)/sizeof(mmMMEA1_ADDRDEC1_RM_SEL_CS23[0]), 0, 0 }, + { "mmMMEA1_ADDRDEC1_RM_SEL_SECCS01", REG_MMIO, 0x02c6, 0, &mmMMEA1_ADDRDEC1_RM_SEL_SECCS01[0], sizeof(mmMMEA1_ADDRDEC1_RM_SEL_SECCS01)/sizeof(mmMMEA1_ADDRDEC1_RM_SEL_SECCS01[0]), 0, 0 }, + { "mmMMEA1_ADDRDEC1_RM_SEL_SECCS23", REG_MMIO, 0x02c7, 0, &mmMMEA1_ADDRDEC1_RM_SEL_SECCS23[0], sizeof(mmMMEA1_ADDRDEC1_RM_SEL_SECCS23)/sizeof(mmMMEA1_ADDRDEC1_RM_SEL_SECCS23[0]), 0, 0 }, + { "mmMMEA1_IO_RD_CLI2GRP_MAP0", REG_MMIO, 0x0310, 0, &mmMMEA1_IO_RD_CLI2GRP_MAP0[0], sizeof(mmMMEA1_IO_RD_CLI2GRP_MAP0)/sizeof(mmMMEA1_IO_RD_CLI2GRP_MAP0[0]), 0, 0 }, + { "mmMMEA1_IO_RD_CLI2GRP_MAP1", REG_MMIO, 0x0311, 0, &mmMMEA1_IO_RD_CLI2GRP_MAP1[0], sizeof(mmMMEA1_IO_RD_CLI2GRP_MAP1)/sizeof(mmMMEA1_IO_RD_CLI2GRP_MAP1[0]), 0, 0 }, + { "mmMMEA1_IO_WR_CLI2GRP_MAP0", REG_MMIO, 0x0312, 0, &mmMMEA1_IO_WR_CLI2GRP_MAP0[0], sizeof(mmMMEA1_IO_WR_CLI2GRP_MAP0)/sizeof(mmMMEA1_IO_WR_CLI2GRP_MAP0[0]), 0, 0 }, + { "mmMMEA1_IO_WR_CLI2GRP_MAP1", REG_MMIO, 0x0313, 0, &mmMMEA1_IO_WR_CLI2GRP_MAP1[0], sizeof(mmMMEA1_IO_WR_CLI2GRP_MAP1)/sizeof(mmMMEA1_IO_WR_CLI2GRP_MAP1[0]), 0, 0 }, + { "mmMMEA1_IO_RD_COMBINE_FLUSH", REG_MMIO, 0x0314, 0, &mmMMEA1_IO_RD_COMBINE_FLUSH[0], sizeof(mmMMEA1_IO_RD_COMBINE_FLUSH)/sizeof(mmMMEA1_IO_RD_COMBINE_FLUSH[0]), 0, 0 }, + { "mmMMEA1_IO_WR_COMBINE_FLUSH", REG_MMIO, 0x0315, 0, &mmMMEA1_IO_WR_COMBINE_FLUSH[0], sizeof(mmMMEA1_IO_WR_COMBINE_FLUSH)/sizeof(mmMMEA1_IO_WR_COMBINE_FLUSH[0]), 0, 0 }, + { "mmMMEA1_IO_GROUP_BURST", REG_MMIO, 0x0316, 0, &mmMMEA1_IO_GROUP_BURST[0], sizeof(mmMMEA1_IO_GROUP_BURST)/sizeof(mmMMEA1_IO_GROUP_BURST[0]), 0, 0 }, + { "mmMMEA1_IO_RD_PRI_AGE", REG_MMIO, 0x0317, 0, &mmMMEA1_IO_RD_PRI_AGE[0], sizeof(mmMMEA1_IO_RD_PRI_AGE)/sizeof(mmMMEA1_IO_RD_PRI_AGE[0]), 0, 0 }, + { "mmMMEA1_IO_WR_PRI_AGE", REG_MMIO, 0x0318, 0, &mmMMEA1_IO_WR_PRI_AGE[0], sizeof(mmMMEA1_IO_WR_PRI_AGE)/sizeof(mmMMEA1_IO_WR_PRI_AGE[0]), 0, 0 }, + { "mmMMEA1_IO_RD_PRI_QUEUING", REG_MMIO, 0x0319, 0, &mmMMEA1_IO_RD_PRI_QUEUING[0], sizeof(mmMMEA1_IO_RD_PRI_QUEUING)/sizeof(mmMMEA1_IO_RD_PRI_QUEUING[0]), 0, 0 }, + { "mmMMEA1_IO_WR_PRI_QUEUING", REG_MMIO, 0x031a, 0, &mmMMEA1_IO_WR_PRI_QUEUING[0], sizeof(mmMMEA1_IO_WR_PRI_QUEUING)/sizeof(mmMMEA1_IO_WR_PRI_QUEUING[0]), 0, 0 }, + { "mmMMEA1_IO_RD_PRI_FIXED", REG_MMIO, 0x031b, 0, &mmMMEA1_IO_RD_PRI_FIXED[0], sizeof(mmMMEA1_IO_RD_PRI_FIXED)/sizeof(mmMMEA1_IO_RD_PRI_FIXED[0]), 0, 0 }, + { "mmMMEA1_IO_WR_PRI_FIXED", REG_MMIO, 0x031c, 0, &mmMMEA1_IO_WR_PRI_FIXED[0], sizeof(mmMMEA1_IO_WR_PRI_FIXED)/sizeof(mmMMEA1_IO_WR_PRI_FIXED[0]), 0, 0 }, + { "mmMMEA1_IO_RD_PRI_URGENCY", REG_MMIO, 0x031d, 0, &mmMMEA1_IO_RD_PRI_URGENCY[0], sizeof(mmMMEA1_IO_RD_PRI_URGENCY)/sizeof(mmMMEA1_IO_RD_PRI_URGENCY[0]), 0, 0 }, + { "mmMMEA1_IO_WR_PRI_URGENCY", REG_MMIO, 0x031e, 0, &mmMMEA1_IO_WR_PRI_URGENCY[0], sizeof(mmMMEA1_IO_WR_PRI_URGENCY)/sizeof(mmMMEA1_IO_WR_PRI_URGENCY[0]), 0, 0 }, + { "mmMMEA1_IO_RD_PRI_URGENCY_MASK", REG_MMIO, 0x031f, 0, &mmMMEA1_IO_RD_PRI_URGENCY_MASK[0], sizeof(mmMMEA1_IO_RD_PRI_URGENCY_MASK)/sizeof(mmMMEA1_IO_RD_PRI_URGENCY_MASK[0]), 0, 0 }, + { "mmMMEA1_IO_WR_PRI_URGENCY_MASK", REG_MMIO, 0x0320, 0, &mmMMEA1_IO_WR_PRI_URGENCY_MASK[0], sizeof(mmMMEA1_IO_WR_PRI_URGENCY_MASK)/sizeof(mmMMEA1_IO_WR_PRI_URGENCY_MASK[0]), 0, 0 }, + { "mmMMEA1_IO_RD_PRI_QUANT_PRI1", REG_MMIO, 0x0321, 0, &mmMMEA1_IO_RD_PRI_QUANT_PRI1[0], sizeof(mmMMEA1_IO_RD_PRI_QUANT_PRI1)/sizeof(mmMMEA1_IO_RD_PRI_QUANT_PRI1[0]), 0, 0 }, + { "mmMMEA1_IO_RD_PRI_QUANT_PRI2", REG_MMIO, 0x0322, 0, &mmMMEA1_IO_RD_PRI_QUANT_PRI2[0], sizeof(mmMMEA1_IO_RD_PRI_QUANT_PRI2)/sizeof(mmMMEA1_IO_RD_PRI_QUANT_PRI2[0]), 0, 0 }, + { "mmMMEA1_IO_RD_PRI_QUANT_PRI3", REG_MMIO, 0x0323, 0, &mmMMEA1_IO_RD_PRI_QUANT_PRI3[0], sizeof(mmMMEA1_IO_RD_PRI_QUANT_PRI3)/sizeof(mmMMEA1_IO_RD_PRI_QUANT_PRI3[0]), 0, 0 }, + { "mmMMEA1_IO_WR_PRI_QUANT_PRI1", REG_MMIO, 0x0324, 0, &mmMMEA1_IO_WR_PRI_QUANT_PRI1[0], sizeof(mmMMEA1_IO_WR_PRI_QUANT_PRI1)/sizeof(mmMMEA1_IO_WR_PRI_QUANT_PRI1[0]), 0, 0 }, + { "mmMMEA1_IO_WR_PRI_QUANT_PRI2", REG_MMIO, 0x0325, 0, &mmMMEA1_IO_WR_PRI_QUANT_PRI2[0], sizeof(mmMMEA1_IO_WR_PRI_QUANT_PRI2)/sizeof(mmMMEA1_IO_WR_PRI_QUANT_PRI2[0]), 0, 0 }, + { "mmMMEA1_IO_WR_PRI_QUANT_PRI3", REG_MMIO, 0x0326, 0, &mmMMEA1_IO_WR_PRI_QUANT_PRI3[0], sizeof(mmMMEA1_IO_WR_PRI_QUANT_PRI3)/sizeof(mmMMEA1_IO_WR_PRI_QUANT_PRI3[0]), 0, 0 }, + { "mmMMEA1_SDP_ARB_DRAM", REG_MMIO, 0x0327, 0, &mmMMEA1_SDP_ARB_DRAM[0], sizeof(mmMMEA1_SDP_ARB_DRAM)/sizeof(mmMMEA1_SDP_ARB_DRAM[0]), 0, 0 }, + { "mmMMEA1_SDP_ARB_FINAL", REG_MMIO, 0x0329, 0, &mmMMEA1_SDP_ARB_FINAL[0], sizeof(mmMMEA1_SDP_ARB_FINAL)/sizeof(mmMMEA1_SDP_ARB_FINAL[0]), 0, 0 }, + { "mmMMEA1_SDP_DRAM_PRIORITY", REG_MMIO, 0x032a, 0, &mmMMEA1_SDP_DRAM_PRIORITY[0], sizeof(mmMMEA1_SDP_DRAM_PRIORITY)/sizeof(mmMMEA1_SDP_DRAM_PRIORITY[0]), 0, 0 }, + { "mmMMEA1_SDP_IO_PRIORITY", REG_MMIO, 0x032c, 0, &mmMMEA1_SDP_IO_PRIORITY[0], sizeof(mmMMEA1_SDP_IO_PRIORITY)/sizeof(mmMMEA1_SDP_IO_PRIORITY[0]), 0, 0 }, + { "mmMMEA1_SDP_CREDITS", REG_MMIO, 0x032d, 0, &mmMMEA1_SDP_CREDITS[0], sizeof(mmMMEA1_SDP_CREDITS)/sizeof(mmMMEA1_SDP_CREDITS[0]), 0, 0 }, + { "mmMMEA1_SDP_TAG_RESERVE0", REG_MMIO, 0x032e, 0, &mmMMEA1_SDP_TAG_RESERVE0[0], sizeof(mmMMEA1_SDP_TAG_RESERVE0)/sizeof(mmMMEA1_SDP_TAG_RESERVE0[0]), 0, 0 }, + { "mmMMEA1_SDP_TAG_RESERVE1", REG_MMIO, 0x032f, 0, &mmMMEA1_SDP_TAG_RESERVE1[0], sizeof(mmMMEA1_SDP_TAG_RESERVE1)/sizeof(mmMMEA1_SDP_TAG_RESERVE1[0]), 0, 0 }, + { "mmMMEA1_SDP_VCC_RESERVE0", REG_MMIO, 0x0330, 0, &mmMMEA1_SDP_VCC_RESERVE0[0], sizeof(mmMMEA1_SDP_VCC_RESERVE0)/sizeof(mmMMEA1_SDP_VCC_RESERVE0[0]), 0, 0 }, + { "mmMMEA1_SDP_VCC_RESERVE1", REG_MMIO, 0x0331, 0, &mmMMEA1_SDP_VCC_RESERVE1[0], sizeof(mmMMEA1_SDP_VCC_RESERVE1)/sizeof(mmMMEA1_SDP_VCC_RESERVE1[0]), 0, 0 }, + { "mmMMEA1_SDP_VCD_RESERVE0", REG_MMIO, 0x0332, 0, &mmMMEA1_SDP_VCD_RESERVE0[0], sizeof(mmMMEA1_SDP_VCD_RESERVE0)/sizeof(mmMMEA1_SDP_VCD_RESERVE0[0]), 0, 0 }, + { "mmMMEA1_SDP_VCD_RESERVE1", REG_MMIO, 0x0333, 0, &mmMMEA1_SDP_VCD_RESERVE1[0], sizeof(mmMMEA1_SDP_VCD_RESERVE1)/sizeof(mmMMEA1_SDP_VCD_RESERVE1[0]), 0, 0 }, + { "mmMMEA1_SDP_REQ_CNTL", REG_MMIO, 0x0334, 0, &mmMMEA1_SDP_REQ_CNTL[0], sizeof(mmMMEA1_SDP_REQ_CNTL)/sizeof(mmMMEA1_SDP_REQ_CNTL[0]), 0, 0 }, + { "mmMMEA1_MISC", REG_MMIO, 0x0335, 0, &mmMMEA1_MISC[0], sizeof(mmMMEA1_MISC)/sizeof(mmMMEA1_MISC[0]), 0, 0 }, + { "mmMMEA1_LATENCY_SAMPLING", REG_MMIO, 0x0336, 0, &mmMMEA1_LATENCY_SAMPLING[0], sizeof(mmMMEA1_LATENCY_SAMPLING)/sizeof(mmMMEA1_LATENCY_SAMPLING[0]), 0, 0 }, + { "mmMMEA1_PERFCOUNTER_LO", REG_MMIO, 0x0337, 0, &mmMMEA1_PERFCOUNTER_LO[0], sizeof(mmMMEA1_PERFCOUNTER_LO)/sizeof(mmMMEA1_PERFCOUNTER_LO[0]), 0, 0 }, + { "mmMMEA1_PERFCOUNTER_HI", REG_MMIO, 0x0338, 0, &mmMMEA1_PERFCOUNTER_HI[0], sizeof(mmMMEA1_PERFCOUNTER_HI)/sizeof(mmMMEA1_PERFCOUNTER_HI[0]), 0, 0 }, + { "mmMMEA1_PERFCOUNTER0_CFG", REG_MMIO, 0x0339, 0, &mmMMEA1_PERFCOUNTER0_CFG[0], sizeof(mmMMEA1_PERFCOUNTER0_CFG)/sizeof(mmMMEA1_PERFCOUNTER0_CFG[0]), 0, 0 }, + { "mmMMEA1_PERFCOUNTER1_CFG", REG_MMIO, 0x033a, 0, &mmMMEA1_PERFCOUNTER1_CFG[0], sizeof(mmMMEA1_PERFCOUNTER1_CFG)/sizeof(mmMMEA1_PERFCOUNTER1_CFG[0]), 0, 0 }, + { "mmMMEA1_PERFCOUNTER_RSLT_CNTL", REG_MMIO, 0x033b, 0, &mmMMEA1_PERFCOUNTER_RSLT_CNTL[0], sizeof(mmMMEA1_PERFCOUNTER_RSLT_CNTL)/sizeof(mmMMEA1_PERFCOUNTER_RSLT_CNTL[0]), 0, 0 }, + { "mmMMEA1_EDC_CNT", REG_MMIO, 0x0341, 0, &mmMMEA1_EDC_CNT[0], sizeof(mmMMEA1_EDC_CNT)/sizeof(mmMMEA1_EDC_CNT[0]), 0, 0 }, + { "mmMMEA1_EDC_CNT2", REG_MMIO, 0x0342, 0, &mmMMEA1_EDC_CNT2[0], sizeof(mmMMEA1_EDC_CNT2)/sizeof(mmMMEA1_EDC_CNT2[0]), 0, 0 }, + { "mmMMEA1_DSM_CNTL", REG_MMIO, 0x0343, 0, &mmMMEA1_DSM_CNTL[0], sizeof(mmMMEA1_DSM_CNTL)/sizeof(mmMMEA1_DSM_CNTL[0]), 0, 0 }, + { "mmMMEA1_DSM_CNTLA", REG_MMIO, 0x0344, 0, &mmMMEA1_DSM_CNTLA[0], sizeof(mmMMEA1_DSM_CNTLA)/sizeof(mmMMEA1_DSM_CNTLA[0]), 0, 0 }, + { "mmMMEA1_DSM_CNTLB", REG_MMIO, 0x0345, 0, NULL, 0, 0, 0 }, + { "mmMMEA1_DSM_CNTL2", REG_MMIO, 0x0346, 0, &mmMMEA1_DSM_CNTL2[0], sizeof(mmMMEA1_DSM_CNTL2)/sizeof(mmMMEA1_DSM_CNTL2[0]), 0, 0 }, + { "mmMMEA1_DSM_CNTL2A", REG_MMIO, 0x0347, 0, &mmMMEA1_DSM_CNTL2A[0], sizeof(mmMMEA1_DSM_CNTL2A)/sizeof(mmMMEA1_DSM_CNTL2A[0]), 0, 0 }, + { "mmMMEA1_DSM_CNTL2B", REG_MMIO, 0x0348, 0, NULL, 0, 0, 0 }, + { "mmMMEA1_CGTT_CLK_CTRL", REG_MMIO, 0x034a, 0, &mmMMEA1_CGTT_CLK_CTRL[0], sizeof(mmMMEA1_CGTT_CLK_CTRL)/sizeof(mmMMEA1_CGTT_CLK_CTRL[0]), 0, 0 }, + { "mmMMEA1_EDC_MODE", REG_MMIO, 0x034b, 0, &mmMMEA1_EDC_MODE[0], sizeof(mmMMEA1_EDC_MODE)/sizeof(mmMMEA1_EDC_MODE[0]), 0, 0 }, + { "mmMMEA1_ERR_STATUS", REG_MMIO, 0x034c, 0, &mmMMEA1_ERR_STATUS[0], sizeof(mmMMEA1_ERR_STATUS)/sizeof(mmMMEA1_ERR_STATUS[0]), 0, 0 }, + { "mmMMEA1_MISC2", REG_MMIO, 0x034d, 0, &mmMMEA1_MISC2[0], sizeof(mmMMEA1_MISC2)/sizeof(mmMMEA1_MISC2[0]), 0, 0 }, + { "mmPCTL_MISC", REG_MMIO, 0x0380, 0, &mmPCTL_MISC[0], sizeof(mmPCTL_MISC)/sizeof(mmPCTL_MISC[0]), 0, 0 }, + { "mmPCTL_MMHUB_DEEPSLEEP", REG_MMIO, 0x0381, 0, &mmPCTL_MMHUB_DEEPSLEEP[0], sizeof(mmPCTL_MMHUB_DEEPSLEEP)/sizeof(mmPCTL_MMHUB_DEEPSLEEP[0]), 0, 0 }, + { "mmPCTL_MMHUB_DEEPSLEEP_OVERRIDE", REG_MMIO, 0x0382, 0, &mmPCTL_MMHUB_DEEPSLEEP_OVERRIDE[0], sizeof(mmPCTL_MMHUB_DEEPSLEEP_OVERRIDE)/sizeof(mmPCTL_MMHUB_DEEPSLEEP_OVERRIDE[0]), 0, 0 }, + { "mmPCTL_PG_IGNORE_DEEPSLEEP", REG_MMIO, 0x0383, 0, &mmPCTL_PG_IGNORE_DEEPSLEEP[0], sizeof(mmPCTL_PG_IGNORE_DEEPSLEEP)/sizeof(mmPCTL_PG_IGNORE_DEEPSLEEP[0]), 0, 0 }, + { "mmPCTL_PG_DAGB", REG_MMIO, 0x0384, 0, &mmPCTL_PG_DAGB[0], sizeof(mmPCTL_PG_DAGB)/sizeof(mmPCTL_PG_DAGB[0]), 0, 0 }, + { "mmPCTL0_RENG_RAM_INDEX", REG_MMIO, 0x0385, 0, &mmPCTL0_RENG_RAM_INDEX[0], sizeof(mmPCTL0_RENG_RAM_INDEX)/sizeof(mmPCTL0_RENG_RAM_INDEX[0]), 0, 0 }, + { "mmPCTL0_RENG_RAM_DATA", REG_MMIO, 0x0386, 0, &mmPCTL0_RENG_RAM_DATA[0], sizeof(mmPCTL0_RENG_RAM_DATA)/sizeof(mmPCTL0_RENG_RAM_DATA[0]), 0, 0 }, + { "mmPCTL0_RENG_EXECUTE", REG_MMIO, 0x0387, 0, &mmPCTL0_RENG_EXECUTE[0], sizeof(mmPCTL0_RENG_EXECUTE)/sizeof(mmPCTL0_RENG_EXECUTE[0]), 0, 0 }, + { "mmPCTL0_MISC", REG_MMIO, 0x0388, 0, &mmPCTL0_MISC[0], sizeof(mmPCTL0_MISC)/sizeof(mmPCTL0_MISC[0]), 0, 0 }, + { "mmPCTL0_STCTRL_REGISTER_SAVE_RANGE0", REG_MMIO, 0x0389, 0, &mmPCTL0_STCTRL_REGISTER_SAVE_RANGE0[0], sizeof(mmPCTL0_STCTRL_REGISTER_SAVE_RANGE0)/sizeof(mmPCTL0_STCTRL_REGISTER_SAVE_RANGE0[0]), 0, 0 }, + { "mmPCTL0_STCTRL_REGISTER_SAVE_RANGE1", REG_MMIO, 0x038a, 0, &mmPCTL0_STCTRL_REGISTER_SAVE_RANGE1[0], sizeof(mmPCTL0_STCTRL_REGISTER_SAVE_RANGE1)/sizeof(mmPCTL0_STCTRL_REGISTER_SAVE_RANGE1[0]), 0, 0 }, + { "mmPCTL0_STCTRL_REGISTER_SAVE_RANGE2", REG_MMIO, 0x038b, 0, &mmPCTL0_STCTRL_REGISTER_SAVE_RANGE2[0], sizeof(mmPCTL0_STCTRL_REGISTER_SAVE_RANGE2)/sizeof(mmPCTL0_STCTRL_REGISTER_SAVE_RANGE2[0]), 0, 0 }, + { "mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET", REG_MMIO, 0x038c, 0, &mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET[0], sizeof(mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET)/sizeof(mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET[0]), 0, 0 }, + { "mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1", REG_MMIO, 0x038d, 0, &mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1[0], sizeof(mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1)/sizeof(mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1[0]), 0, 0 }, + { "mmPCTL1_RENG_RAM_INDEX", REG_MMIO, 0x038e, 0, &mmPCTL1_RENG_RAM_INDEX[0], sizeof(mmPCTL1_RENG_RAM_INDEX)/sizeof(mmPCTL1_RENG_RAM_INDEX[0]), 0, 0 }, + { "mmPCTL1_RENG_RAM_DATA", REG_MMIO, 0x038f, 0, &mmPCTL1_RENG_RAM_DATA[0], sizeof(mmPCTL1_RENG_RAM_DATA)/sizeof(mmPCTL1_RENG_RAM_DATA[0]), 0, 0 }, + { "mmPCTL1_RENG_EXECUTE", REG_MMIO, 0x0390, 0, &mmPCTL1_RENG_EXECUTE[0], sizeof(mmPCTL1_RENG_EXECUTE)/sizeof(mmPCTL1_RENG_EXECUTE[0]), 0, 0 }, + { "mmPCTL1_MISC", REG_MMIO, 0x0391, 0, &mmPCTL1_MISC[0], sizeof(mmPCTL1_MISC)/sizeof(mmPCTL1_MISC[0]), 0, 0 }, + { "mmPCTL1_STCTRL_REGISTER_SAVE_RANGE0", REG_MMIO, 0x0392, 0, &mmPCTL1_STCTRL_REGISTER_SAVE_RANGE0[0], sizeof(mmPCTL1_STCTRL_REGISTER_SAVE_RANGE0)/sizeof(mmPCTL1_STCTRL_REGISTER_SAVE_RANGE0[0]), 0, 0 }, + { "mmPCTL1_STCTRL_REGISTER_SAVE_RANGE1", REG_MMIO, 0x0393, 0, &mmPCTL1_STCTRL_REGISTER_SAVE_RANGE1[0], sizeof(mmPCTL1_STCTRL_REGISTER_SAVE_RANGE1)/sizeof(mmPCTL1_STCTRL_REGISTER_SAVE_RANGE1[0]), 0, 0 }, + { "mmPCTL1_STCTRL_REGISTER_SAVE_RANGE2", REG_MMIO, 0x0394, 0, &mmPCTL1_STCTRL_REGISTER_SAVE_RANGE2[0], sizeof(mmPCTL1_STCTRL_REGISTER_SAVE_RANGE2)/sizeof(mmPCTL1_STCTRL_REGISTER_SAVE_RANGE2[0]), 0, 0 }, + { "mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET", REG_MMIO, 0x0395, 0, &mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET[0], sizeof(mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET)/sizeof(mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET[0]), 0, 0 }, + { "mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1", REG_MMIO, 0x0396, 0, &mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1[0], sizeof(mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1)/sizeof(mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1[0]), 0, 0 }, + { "mmPCTL2_RENG_RAM_INDEX", REG_MMIO, 0x0397, 0, &mmPCTL2_RENG_RAM_INDEX[0], sizeof(mmPCTL2_RENG_RAM_INDEX)/sizeof(mmPCTL2_RENG_RAM_INDEX[0]), 0, 0 }, + { "mmPCTL2_RENG_RAM_DATA", REG_MMIO, 0x0398, 0, &mmPCTL2_RENG_RAM_DATA[0], sizeof(mmPCTL2_RENG_RAM_DATA)/sizeof(mmPCTL2_RENG_RAM_DATA[0]), 0, 0 }, + { "mmPCTL2_RENG_EXECUTE", REG_MMIO, 0x0399, 0, &mmPCTL2_RENG_EXECUTE[0], sizeof(mmPCTL2_RENG_EXECUTE)/sizeof(mmPCTL2_RENG_EXECUTE[0]), 0, 0 }, + { "mmPCTL2_MISC", REG_MMIO, 0x039a, 0, &mmPCTL2_MISC[0], sizeof(mmPCTL2_MISC)/sizeof(mmPCTL2_MISC[0]), 0, 0 }, + { "mmPCTL2_STCTRL_REGISTER_SAVE_RANGE0", REG_MMIO, 0x039b, 0, &mmPCTL2_STCTRL_REGISTER_SAVE_RANGE0[0], sizeof(mmPCTL2_STCTRL_REGISTER_SAVE_RANGE0)/sizeof(mmPCTL2_STCTRL_REGISTER_SAVE_RANGE0[0]), 0, 0 }, + { "mmPCTL2_STCTRL_REGISTER_SAVE_RANGE1", REG_MMIO, 0x039c, 0, &mmPCTL2_STCTRL_REGISTER_SAVE_RANGE1[0], sizeof(mmPCTL2_STCTRL_REGISTER_SAVE_RANGE1)/sizeof(mmPCTL2_STCTRL_REGISTER_SAVE_RANGE1[0]), 0, 0 }, + { "mmPCTL2_STCTRL_REGISTER_SAVE_RANGE2", REG_MMIO, 0x039d, 0, &mmPCTL2_STCTRL_REGISTER_SAVE_RANGE2[0], sizeof(mmPCTL2_STCTRL_REGISTER_SAVE_RANGE2)/sizeof(mmPCTL2_STCTRL_REGISTER_SAVE_RANGE2[0]), 0, 0 }, + { "mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET", REG_MMIO, 0x039e, 0, &mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET[0], sizeof(mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET)/sizeof(mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET[0]), 0, 0 }, + { "mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1", REG_MMIO, 0x039f, 0, &mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1[0], sizeof(mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1)/sizeof(mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1[0]), 0, 0 }, + { "mmMC_VM_MX_L1_TLB0_STATUS", REG_MMIO, 0x0588, 0, &mmMC_VM_MX_L1_TLB0_STATUS[0], sizeof(mmMC_VM_MX_L1_TLB0_STATUS)/sizeof(mmMC_VM_MX_L1_TLB0_STATUS[0]), 0, 0 }, + { "mmMC_VM_MX_L1_TLB1_STATUS", REG_MMIO, 0x0589, 0, &mmMC_VM_MX_L1_TLB1_STATUS[0], sizeof(mmMC_VM_MX_L1_TLB1_STATUS)/sizeof(mmMC_VM_MX_L1_TLB1_STATUS[0]), 0, 0 }, + { "mmMC_VM_MX_L1_TLB2_STATUS", REG_MMIO, 0x058a, 0, &mmMC_VM_MX_L1_TLB2_STATUS[0], sizeof(mmMC_VM_MX_L1_TLB2_STATUS)/sizeof(mmMC_VM_MX_L1_TLB2_STATUS[0]), 0, 0 }, + { "mmMC_VM_MX_L1_TLB3_STATUS", REG_MMIO, 0x058b, 0, &mmMC_VM_MX_L1_TLB3_STATUS[0], sizeof(mmMC_VM_MX_L1_TLB3_STATUS)/sizeof(mmMC_VM_MX_L1_TLB3_STATUS[0]), 0, 0 }, + { "mmMC_VM_MX_L1_TLB4_STATUS", REG_MMIO, 0x058c, 0, &mmMC_VM_MX_L1_TLB4_STATUS[0], sizeof(mmMC_VM_MX_L1_TLB4_STATUS)/sizeof(mmMC_VM_MX_L1_TLB4_STATUS[0]), 0, 0 }, + { "mmMC_VM_MX_L1_TLB5_STATUS", REG_MMIO, 0x058d, 0, &mmMC_VM_MX_L1_TLB5_STATUS[0], sizeof(mmMC_VM_MX_L1_TLB5_STATUS)/sizeof(mmMC_VM_MX_L1_TLB5_STATUS[0]), 0, 0 }, + { "mmMC_VM_MX_L1_TLB6_STATUS", REG_MMIO, 0x058e, 0, &mmMC_VM_MX_L1_TLB6_STATUS[0], sizeof(mmMC_VM_MX_L1_TLB6_STATUS)/sizeof(mmMC_VM_MX_L1_TLB6_STATUS[0]), 0, 0 }, + { "mmMC_VM_MX_L1_TLB7_STATUS", REG_MMIO, 0x058f, 0, &mmMC_VM_MX_L1_TLB7_STATUS[0], sizeof(mmMC_VM_MX_L1_TLB7_STATUS)/sizeof(mmMC_VM_MX_L1_TLB7_STATUS[0]), 0, 0 }, + { "mmMC_VM_MX_L1_PERFCOUNTER0_CFG", REG_MMIO, 0x0594, 0, &mmMC_VM_MX_L1_PERFCOUNTER0_CFG[0], sizeof(mmMC_VM_MX_L1_PERFCOUNTER0_CFG)/sizeof(mmMC_VM_MX_L1_PERFCOUNTER0_CFG[0]), 0, 0 }, + { "mmMC_VM_MX_L1_PERFCOUNTER1_CFG", REG_MMIO, 0x0595, 0, &mmMC_VM_MX_L1_PERFCOUNTER1_CFG[0], sizeof(mmMC_VM_MX_L1_PERFCOUNTER1_CFG)/sizeof(mmMC_VM_MX_L1_PERFCOUNTER1_CFG[0]), 0, 0 }, + { "mmMC_VM_MX_L1_PERFCOUNTER2_CFG", REG_MMIO, 0x0596, 0, &mmMC_VM_MX_L1_PERFCOUNTER2_CFG[0], sizeof(mmMC_VM_MX_L1_PERFCOUNTER2_CFG)/sizeof(mmMC_VM_MX_L1_PERFCOUNTER2_CFG[0]), 0, 0 }, + { "mmMC_VM_MX_L1_PERFCOUNTER3_CFG", REG_MMIO, 0x0597, 0, &mmMC_VM_MX_L1_PERFCOUNTER3_CFG[0], sizeof(mmMC_VM_MX_L1_PERFCOUNTER3_CFG)/sizeof(mmMC_VM_MX_L1_PERFCOUNTER3_CFG[0]), 0, 0 }, + { "mmMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL", REG_MMIO, 0x0598, 0, &mmMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL[0], sizeof(mmMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL)/sizeof(mmMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL[0]), 0, 0 }, + { "mmMC_VM_MX_L1_PERFCOUNTER_LO", REG_MMIO, 0x059c, 0, &mmMC_VM_MX_L1_PERFCOUNTER_LO[0], sizeof(mmMC_VM_MX_L1_PERFCOUNTER_LO)/sizeof(mmMC_VM_MX_L1_PERFCOUNTER_LO[0]), 0, 0 }, + { "mmMC_VM_MX_L1_PERFCOUNTER_HI", REG_MMIO, 0x059d, 0, &mmMC_VM_MX_L1_PERFCOUNTER_HI[0], sizeof(mmMC_VM_MX_L1_PERFCOUNTER_HI)/sizeof(mmMC_VM_MX_L1_PERFCOUNTER_HI[0]), 0, 0 }, + { "mmVM_L2_SAW_CNTL", REG_MMIO, 0x0600, 0, &mmVM_L2_SAW_CNTL[0], sizeof(mmVM_L2_SAW_CNTL)/sizeof(mmVM_L2_SAW_CNTL[0]), 0, 0 }, + { "mmVM_L2_SAW_CNTL2", REG_MMIO, 0x0601, 0, &mmVM_L2_SAW_CNTL2[0], sizeof(mmVM_L2_SAW_CNTL2)/sizeof(mmVM_L2_SAW_CNTL2[0]), 0, 0 }, + { "mmVM_L2_SAW_CNTL3", REG_MMIO, 0x0602, 0, &mmVM_L2_SAW_CNTL3[0], sizeof(mmVM_L2_SAW_CNTL3)/sizeof(mmVM_L2_SAW_CNTL3[0]), 0, 0 }, + { "mmVM_L2_SAW_CNTL4", REG_MMIO, 0x0603, 0, &mmVM_L2_SAW_CNTL4[0], sizeof(mmVM_L2_SAW_CNTL4)/sizeof(mmVM_L2_SAW_CNTL4[0]), 0, 0 }, + { "mmVM_L2_SAW_CONTEXT0_CNTL", REG_MMIO, 0x0604, 0, &mmVM_L2_SAW_CONTEXT0_CNTL[0], sizeof(mmVM_L2_SAW_CONTEXT0_CNTL)/sizeof(mmVM_L2_SAW_CONTEXT0_CNTL[0]), 0, 0 }, + { "mmVM_L2_SAW_CONTEXT0_CNTL2", REG_MMIO, 0x0605, 0, &mmVM_L2_SAW_CONTEXT0_CNTL2[0], sizeof(mmVM_L2_SAW_CONTEXT0_CNTL2)/sizeof(mmVM_L2_SAW_CONTEXT0_CNTL2[0]), 0, 0 }, + { "mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32", REG_MMIO, 0x0606, 0, &mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32[0], sizeof(mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32)/sizeof(mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32[0]), 0, 0 }, + { "mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32", REG_MMIO, 0x0607, 0, &mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32[0], sizeof(mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32)/sizeof(mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32[0]), 0, 0 }, + { "mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32", REG_MMIO, 0x0608, 0, &mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32[0], sizeof(mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32)/sizeof(mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32[0]), 0, 0 }, + { "mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32", REG_MMIO, 0x0609, 0, &mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32[0], sizeof(mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32)/sizeof(mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32[0]), 0, 0 }, + { "mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32", REG_MMIO, 0x060a, 0, &mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32[0], sizeof(mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32)/sizeof(mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32[0]), 0, 0 }, + { "mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32", REG_MMIO, 0x060b, 0, &mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32[0], sizeof(mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32)/sizeof(mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32[0]), 0, 0 }, + { "mmVM_L2_SAW_CONTEXTS_DISABLE", REG_MMIO, 0x060c, 0, &mmVM_L2_SAW_CONTEXTS_DISABLE[0], sizeof(mmVM_L2_SAW_CONTEXTS_DISABLE)/sizeof(mmVM_L2_SAW_CONTEXTS_DISABLE[0]), 0, 0 }, + { "mmVM_L2_SAW_PIPES_BUSY", REG_MMIO, 0x060d, 0, &mmVM_L2_SAW_PIPES_BUSY[0], sizeof(mmVM_L2_SAW_PIPES_BUSY)/sizeof(mmVM_L2_SAW_PIPES_BUSY[0]), 0, 0 }, + { "mmATC_L2_CNTL", REG_MMIO, 0x0640, 0, &mmATC_L2_CNTL[0], sizeof(mmATC_L2_CNTL)/sizeof(mmATC_L2_CNTL[0]), 0, 0 }, + { "mmATC_L2_CNTL2", REG_MMIO, 0x0641, 0, &mmATC_L2_CNTL2[0], sizeof(mmATC_L2_CNTL2)/sizeof(mmATC_L2_CNTL2[0]), 0, 0 }, + { "mmATC_L2_CACHE_DATA0", REG_MMIO, 0x0644, 0, &mmATC_L2_CACHE_DATA0[0], sizeof(mmATC_L2_CACHE_DATA0)/sizeof(mmATC_L2_CACHE_DATA0[0]), 0, 0 }, + { "mmATC_L2_CACHE_DATA1", REG_MMIO, 0x0645, 0, &mmATC_L2_CACHE_DATA1[0], sizeof(mmATC_L2_CACHE_DATA1)/sizeof(mmATC_L2_CACHE_DATA1[0]), 0, 0 }, + { "mmATC_L2_CACHE_DATA2", REG_MMIO, 0x0646, 0, &mmATC_L2_CACHE_DATA2[0], sizeof(mmATC_L2_CACHE_DATA2)/sizeof(mmATC_L2_CACHE_DATA2[0]), 0, 0 }, + { "mmATC_L2_CNTL3", REG_MMIO, 0x0647, 0, &mmATC_L2_CNTL3[0], sizeof(mmATC_L2_CNTL3)/sizeof(mmATC_L2_CNTL3[0]), 0, 0 }, + { "mmATC_L2_STATUS", REG_MMIO, 0x0648, 0, &mmATC_L2_STATUS[0], sizeof(mmATC_L2_STATUS)/sizeof(mmATC_L2_STATUS[0]), 0, 0 }, + { "mmATC_L2_STATUS2", REG_MMIO, 0x0649, 0, &mmATC_L2_STATUS2[0], sizeof(mmATC_L2_STATUS2)/sizeof(mmATC_L2_STATUS2[0]), 0, 0 }, + { "mmATC_L2_MISC_CG", REG_MMIO, 0x064a, 0, &mmATC_L2_MISC_CG[0], sizeof(mmATC_L2_MISC_CG)/sizeof(mmATC_L2_MISC_CG[0]), 0, 0 }, + { "mmATC_L2_MEM_POWER_LS", REG_MMIO, 0x064b, 0, &mmATC_L2_MEM_POWER_LS[0], sizeof(mmATC_L2_MEM_POWER_LS)/sizeof(mmATC_L2_MEM_POWER_LS[0]), 0, 0 }, + { "mmATC_L2_CGTT_CLK_CTRL", REG_MMIO, 0x064c, 0, &mmATC_L2_CGTT_CLK_CTRL[0], sizeof(mmATC_L2_CGTT_CLK_CTRL)/sizeof(mmATC_L2_CGTT_CLK_CTRL[0]), 0, 0 }, + { "mmVM_L2_CNTL", REG_MMIO, 0x0680, 0, &mmVM_L2_CNTL[0], sizeof(mmVM_L2_CNTL)/sizeof(mmVM_L2_CNTL[0]), 0, 0 }, + { "mmVM_L2_CNTL2", REG_MMIO, 0x0681, 0, &mmVM_L2_CNTL2[0], sizeof(mmVM_L2_CNTL2)/sizeof(mmVM_L2_CNTL2[0]), 0, 0 }, + { "mmVM_L2_CNTL3", REG_MMIO, 0x0682, 0, &mmVM_L2_CNTL3[0], sizeof(mmVM_L2_CNTL3)/sizeof(mmVM_L2_CNTL3[0]), 0, 0 }, + { "mmVM_L2_STATUS", REG_MMIO, 0x0683, 0, &mmVM_L2_STATUS[0], sizeof(mmVM_L2_STATUS)/sizeof(mmVM_L2_STATUS[0]), 0, 0 }, + { "mmVM_DUMMY_PAGE_FAULT_CNTL", REG_MMIO, 0x0684, 0, &mmVM_DUMMY_PAGE_FAULT_CNTL[0], sizeof(mmVM_DUMMY_PAGE_FAULT_CNTL)/sizeof(mmVM_DUMMY_PAGE_FAULT_CNTL[0]), 0, 0 }, + { "mmVM_DUMMY_PAGE_FAULT_ADDR_LO32", REG_MMIO, 0x0685, 0, &mmVM_DUMMY_PAGE_FAULT_ADDR_LO32[0], sizeof(mmVM_DUMMY_PAGE_FAULT_ADDR_LO32)/sizeof(mmVM_DUMMY_PAGE_FAULT_ADDR_LO32[0]), 0, 0 }, + { "mmVM_DUMMY_PAGE_FAULT_ADDR_HI32", REG_MMIO, 0x0686, 0, &mmVM_DUMMY_PAGE_FAULT_ADDR_HI32[0], sizeof(mmVM_DUMMY_PAGE_FAULT_ADDR_HI32)/sizeof(mmVM_DUMMY_PAGE_FAULT_ADDR_HI32[0]), 0, 0 }, + { "mmVM_L2_PROTECTION_FAULT_CNTL", REG_MMIO, 0x0687, 0, &mmVM_L2_PROTECTION_FAULT_CNTL[0], sizeof(mmVM_L2_PROTECTION_FAULT_CNTL)/sizeof(mmVM_L2_PROTECTION_FAULT_CNTL[0]), 0, 0 }, + { "mmVM_L2_PROTECTION_FAULT_CNTL2", REG_MMIO, 0x0688, 0, &mmVM_L2_PROTECTION_FAULT_CNTL2[0], sizeof(mmVM_L2_PROTECTION_FAULT_CNTL2)/sizeof(mmVM_L2_PROTECTION_FAULT_CNTL2[0]), 0, 0 }, + { "mmVM_L2_PROTECTION_FAULT_MM_CNTL3", REG_MMIO, 0x0689, 0, &mmVM_L2_PROTECTION_FAULT_MM_CNTL3[0], sizeof(mmVM_L2_PROTECTION_FAULT_MM_CNTL3)/sizeof(mmVM_L2_PROTECTION_FAULT_MM_CNTL3[0]), 0, 0 }, + { "mmVM_L2_PROTECTION_FAULT_MM_CNTL4", REG_MMIO, 0x068a, 0, &mmVM_L2_PROTECTION_FAULT_MM_CNTL4[0], sizeof(mmVM_L2_PROTECTION_FAULT_MM_CNTL4)/sizeof(mmVM_L2_PROTECTION_FAULT_MM_CNTL4[0]), 0, 0 }, + { "mmVM_L2_PROTECTION_FAULT_STATUS", REG_MMIO, 0x068b, 0, &mmVM_L2_PROTECTION_FAULT_STATUS[0], sizeof(mmVM_L2_PROTECTION_FAULT_STATUS)/sizeof(mmVM_L2_PROTECTION_FAULT_STATUS[0]), 0, 0 }, + { "mmVM_L2_PROTECTION_FAULT_ADDR_LO32", REG_MMIO, 0x068c, 0, &mmVM_L2_PROTECTION_FAULT_ADDR_LO32[0], sizeof(mmVM_L2_PROTECTION_FAULT_ADDR_LO32)/sizeof(mmVM_L2_PROTECTION_FAULT_ADDR_LO32[0]), 0, 0 }, + { "mmVM_L2_PROTECTION_FAULT_ADDR_HI32", REG_MMIO, 0x068d, 0, &mmVM_L2_PROTECTION_FAULT_ADDR_HI32[0], sizeof(mmVM_L2_PROTECTION_FAULT_ADDR_HI32)/sizeof(mmVM_L2_PROTECTION_FAULT_ADDR_HI32[0]), 0, 0 }, + { "mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32", REG_MMIO, 0x068e, 0, &mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32[0], sizeof(mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32)/sizeof(mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32[0]), 0, 0 }, + { "mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32", REG_MMIO, 0x068f, 0, &mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32[0], sizeof(mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32)/sizeof(mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32[0]), 0, 0 }, + { "mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32", REG_MMIO, 0x0691, 0, &mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32[0], sizeof(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32)/sizeof(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32[0]), 0, 0 }, + { "mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32", REG_MMIO, 0x0692, 0, &mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32[0], sizeof(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32)/sizeof(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32[0]), 0, 0 }, + { "mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32", REG_MMIO, 0x0693, 0, &mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32[0], sizeof(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32)/sizeof(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32[0]), 0, 0 }, + { "mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32", REG_MMIO, 0x0694, 0, &mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32[0], sizeof(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32)/sizeof(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32[0]), 0, 0 }, + { "mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32", REG_MMIO, 0x0695, 0, &mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32[0], sizeof(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32)/sizeof(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32[0]), 0, 0 }, + { "mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32", REG_MMIO, 0x0696, 0, &mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32[0], sizeof(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32)/sizeof(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32[0]), 0, 0 }, + { "mmVM_L2_CNTL4", REG_MMIO, 0x0697, 0, &mmVM_L2_CNTL4[0], sizeof(mmVM_L2_CNTL4)/sizeof(mmVM_L2_CNTL4[0]), 0, 0 }, + { "mmVM_L2_MM_GROUP_RT_CLASSES", REG_MMIO, 0x0698, 0, &mmVM_L2_MM_GROUP_RT_CLASSES[0], sizeof(mmVM_L2_MM_GROUP_RT_CLASSES)/sizeof(mmVM_L2_MM_GROUP_RT_CLASSES[0]), 0, 0 }, + { "mmVM_L2_BANK_SELECT_RESERVED_CID", REG_MMIO, 0x0699, 0, &mmVM_L2_BANK_SELECT_RESERVED_CID[0], sizeof(mmVM_L2_BANK_SELECT_RESERVED_CID)/sizeof(mmVM_L2_BANK_SELECT_RESERVED_CID[0]), 0, 0 }, + { "mmVM_L2_BANK_SELECT_RESERVED_CID2", REG_MMIO, 0x069a, 0, &mmVM_L2_BANK_SELECT_RESERVED_CID2[0], sizeof(mmVM_L2_BANK_SELECT_RESERVED_CID2)/sizeof(mmVM_L2_BANK_SELECT_RESERVED_CID2[0]), 0, 0 }, + { "mmVM_L2_CACHE_PARITY_CNTL", REG_MMIO, 0x069b, 0, &mmVM_L2_CACHE_PARITY_CNTL[0], sizeof(mmVM_L2_CACHE_PARITY_CNTL)/sizeof(mmVM_L2_CACHE_PARITY_CNTL[0]), 0, 0 }, + { "mmVM_L2_CGTT_CLK_CTRL", REG_MMIO, 0x069e, 0, &mmVM_L2_CGTT_CLK_CTRL[0], sizeof(mmVM_L2_CGTT_CLK_CTRL)/sizeof(mmVM_L2_CGTT_CLK_CTRL[0]), 0, 0 }, + { "mmVM_CONTEXT0_CNTL", REG_MMIO, 0x06c0, 0, &mmVM_CONTEXT0_CNTL[0], sizeof(mmVM_CONTEXT0_CNTL)/sizeof(mmVM_CONTEXT0_CNTL[0]), 0, 0 }, + { "mmVM_CONTEXT1_CNTL", REG_MMIO, 0x06c1, 0, &mmVM_CONTEXT1_CNTL[0], sizeof(mmVM_CONTEXT1_CNTL)/sizeof(mmVM_CONTEXT1_CNTL[0]), 0, 0 }, + { "mmVM_CONTEXT2_CNTL", REG_MMIO, 0x06c2, 0, &mmVM_CONTEXT2_CNTL[0], sizeof(mmVM_CONTEXT2_CNTL)/sizeof(mmVM_CONTEXT2_CNTL[0]), 0, 0 }, + { "mmVM_CONTEXT3_CNTL", REG_MMIO, 0x06c3, 0, &mmVM_CONTEXT3_CNTL[0], sizeof(mmVM_CONTEXT3_CNTL)/sizeof(mmVM_CONTEXT3_CNTL[0]), 0, 0 }, + { "mmVM_CONTEXT4_CNTL", REG_MMIO, 0x06c4, 0, &mmVM_CONTEXT4_CNTL[0], sizeof(mmVM_CONTEXT4_CNTL)/sizeof(mmVM_CONTEXT4_CNTL[0]), 0, 0 }, + { "mmVM_CONTEXT5_CNTL", REG_MMIO, 0x06c5, 0, &mmVM_CONTEXT5_CNTL[0], sizeof(mmVM_CONTEXT5_CNTL)/sizeof(mmVM_CONTEXT5_CNTL[0]), 0, 0 }, + { "mmVM_CONTEXT6_CNTL", REG_MMIO, 0x06c6, 0, &mmVM_CONTEXT6_CNTL[0], sizeof(mmVM_CONTEXT6_CNTL)/sizeof(mmVM_CONTEXT6_CNTL[0]), 0, 0 }, + { "mmVM_CONTEXT7_CNTL", REG_MMIO, 0x06c7, 0, &mmVM_CONTEXT7_CNTL[0], sizeof(mmVM_CONTEXT7_CNTL)/sizeof(mmVM_CONTEXT7_CNTL[0]), 0, 0 }, + { "mmVM_CONTEXT8_CNTL", REG_MMIO, 0x06c8, 0, &mmVM_CONTEXT8_CNTL[0], sizeof(mmVM_CONTEXT8_CNTL)/sizeof(mmVM_CONTEXT8_CNTL[0]), 0, 0 }, + { "mmVM_CONTEXT9_CNTL", REG_MMIO, 0x06c9, 0, &mmVM_CONTEXT9_CNTL[0], sizeof(mmVM_CONTEXT9_CNTL)/sizeof(mmVM_CONTEXT9_CNTL[0]), 0, 0 }, + { "mmVM_CONTEXT10_CNTL", REG_MMIO, 0x06ca, 0, &mmVM_CONTEXT10_CNTL[0], sizeof(mmVM_CONTEXT10_CNTL)/sizeof(mmVM_CONTEXT10_CNTL[0]), 0, 0 }, + { "mmVM_CONTEXT11_CNTL", REG_MMIO, 0x06cb, 0, &mmVM_CONTEXT11_CNTL[0], sizeof(mmVM_CONTEXT11_CNTL)/sizeof(mmVM_CONTEXT11_CNTL[0]), 0, 0 }, + { "mmVM_CONTEXT12_CNTL", REG_MMIO, 0x06cc, 0, &mmVM_CONTEXT12_CNTL[0], sizeof(mmVM_CONTEXT12_CNTL)/sizeof(mmVM_CONTEXT12_CNTL[0]), 0, 0 }, + { "mmVM_CONTEXT13_CNTL", REG_MMIO, 0x06cd, 0, &mmVM_CONTEXT13_CNTL[0], sizeof(mmVM_CONTEXT13_CNTL)/sizeof(mmVM_CONTEXT13_CNTL[0]), 0, 0 }, + { "mmVM_CONTEXT14_CNTL", REG_MMIO, 0x06ce, 0, &mmVM_CONTEXT14_CNTL[0], sizeof(mmVM_CONTEXT14_CNTL)/sizeof(mmVM_CONTEXT14_CNTL[0]), 0, 0 }, + { "mmVM_CONTEXT15_CNTL", REG_MMIO, 0x06cf, 0, &mmVM_CONTEXT15_CNTL[0], sizeof(mmVM_CONTEXT15_CNTL)/sizeof(mmVM_CONTEXT15_CNTL[0]), 0, 0 }, + { "mmVM_CONTEXTS_DISABLE", REG_MMIO, 0x06d0, 0, &mmVM_CONTEXTS_DISABLE[0], sizeof(mmVM_CONTEXTS_DISABLE)/sizeof(mmVM_CONTEXTS_DISABLE[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG0_SEM", REG_MMIO, 0x06d1, 0, &mmVM_INVALIDATE_ENG0_SEM[0], sizeof(mmVM_INVALIDATE_ENG0_SEM)/sizeof(mmVM_INVALIDATE_ENG0_SEM[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG1_SEM", REG_MMIO, 0x06d2, 0, &mmVM_INVALIDATE_ENG1_SEM[0], sizeof(mmVM_INVALIDATE_ENG1_SEM)/sizeof(mmVM_INVALIDATE_ENG1_SEM[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG2_SEM", REG_MMIO, 0x06d3, 0, &mmVM_INVALIDATE_ENG2_SEM[0], sizeof(mmVM_INVALIDATE_ENG2_SEM)/sizeof(mmVM_INVALIDATE_ENG2_SEM[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG3_SEM", REG_MMIO, 0x06d4, 0, &mmVM_INVALIDATE_ENG3_SEM[0], sizeof(mmVM_INVALIDATE_ENG3_SEM)/sizeof(mmVM_INVALIDATE_ENG3_SEM[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG4_SEM", REG_MMIO, 0x06d5, 0, &mmVM_INVALIDATE_ENG4_SEM[0], sizeof(mmVM_INVALIDATE_ENG4_SEM)/sizeof(mmVM_INVALIDATE_ENG4_SEM[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG5_SEM", REG_MMIO, 0x06d6, 0, &mmVM_INVALIDATE_ENG5_SEM[0], sizeof(mmVM_INVALIDATE_ENG5_SEM)/sizeof(mmVM_INVALIDATE_ENG5_SEM[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG6_SEM", REG_MMIO, 0x06d7, 0, &mmVM_INVALIDATE_ENG6_SEM[0], sizeof(mmVM_INVALIDATE_ENG6_SEM)/sizeof(mmVM_INVALIDATE_ENG6_SEM[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG7_SEM", REG_MMIO, 0x06d8, 0, &mmVM_INVALIDATE_ENG7_SEM[0], sizeof(mmVM_INVALIDATE_ENG7_SEM)/sizeof(mmVM_INVALIDATE_ENG7_SEM[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG8_SEM", REG_MMIO, 0x06d9, 0, &mmVM_INVALIDATE_ENG8_SEM[0], sizeof(mmVM_INVALIDATE_ENG8_SEM)/sizeof(mmVM_INVALIDATE_ENG8_SEM[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG9_SEM", REG_MMIO, 0x06da, 0, &mmVM_INVALIDATE_ENG9_SEM[0], sizeof(mmVM_INVALIDATE_ENG9_SEM)/sizeof(mmVM_INVALIDATE_ENG9_SEM[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG10_SEM", REG_MMIO, 0x06db, 0, &mmVM_INVALIDATE_ENG10_SEM[0], sizeof(mmVM_INVALIDATE_ENG10_SEM)/sizeof(mmVM_INVALIDATE_ENG10_SEM[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG11_SEM", REG_MMIO, 0x06dc, 0, &mmVM_INVALIDATE_ENG11_SEM[0], sizeof(mmVM_INVALIDATE_ENG11_SEM)/sizeof(mmVM_INVALIDATE_ENG11_SEM[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG12_SEM", REG_MMIO, 0x06dd, 0, &mmVM_INVALIDATE_ENG12_SEM[0], sizeof(mmVM_INVALIDATE_ENG12_SEM)/sizeof(mmVM_INVALIDATE_ENG12_SEM[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG13_SEM", REG_MMIO, 0x06de, 0, &mmVM_INVALIDATE_ENG13_SEM[0], sizeof(mmVM_INVALIDATE_ENG13_SEM)/sizeof(mmVM_INVALIDATE_ENG13_SEM[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG14_SEM", REG_MMIO, 0x06df, 0, &mmVM_INVALIDATE_ENG14_SEM[0], sizeof(mmVM_INVALIDATE_ENG14_SEM)/sizeof(mmVM_INVALIDATE_ENG14_SEM[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG15_SEM", REG_MMIO, 0x06e0, 0, &mmVM_INVALIDATE_ENG15_SEM[0], sizeof(mmVM_INVALIDATE_ENG15_SEM)/sizeof(mmVM_INVALIDATE_ENG15_SEM[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG16_SEM", REG_MMIO, 0x06e1, 0, &mmVM_INVALIDATE_ENG16_SEM[0], sizeof(mmVM_INVALIDATE_ENG16_SEM)/sizeof(mmVM_INVALIDATE_ENG16_SEM[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG17_SEM", REG_MMIO, 0x06e2, 0, &mmVM_INVALIDATE_ENG17_SEM[0], sizeof(mmVM_INVALIDATE_ENG17_SEM)/sizeof(mmVM_INVALIDATE_ENG17_SEM[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG0_REQ", REG_MMIO, 0x06e3, 0, &mmVM_INVALIDATE_ENG0_REQ[0], sizeof(mmVM_INVALIDATE_ENG0_REQ)/sizeof(mmVM_INVALIDATE_ENG0_REQ[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG1_REQ", REG_MMIO, 0x06e4, 0, &mmVM_INVALIDATE_ENG1_REQ[0], sizeof(mmVM_INVALIDATE_ENG1_REQ)/sizeof(mmVM_INVALIDATE_ENG1_REQ[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG2_REQ", REG_MMIO, 0x06e5, 0, &mmVM_INVALIDATE_ENG2_REQ[0], sizeof(mmVM_INVALIDATE_ENG2_REQ)/sizeof(mmVM_INVALIDATE_ENG2_REQ[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG3_REQ", REG_MMIO, 0x06e6, 0, &mmVM_INVALIDATE_ENG3_REQ[0], sizeof(mmVM_INVALIDATE_ENG3_REQ)/sizeof(mmVM_INVALIDATE_ENG3_REQ[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG4_REQ", REG_MMIO, 0x06e7, 0, &mmVM_INVALIDATE_ENG4_REQ[0], sizeof(mmVM_INVALIDATE_ENG4_REQ)/sizeof(mmVM_INVALIDATE_ENG4_REQ[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG5_REQ", REG_MMIO, 0x06e8, 0, &mmVM_INVALIDATE_ENG5_REQ[0], sizeof(mmVM_INVALIDATE_ENG5_REQ)/sizeof(mmVM_INVALIDATE_ENG5_REQ[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG6_REQ", REG_MMIO, 0x06e9, 0, &mmVM_INVALIDATE_ENG6_REQ[0], sizeof(mmVM_INVALIDATE_ENG6_REQ)/sizeof(mmVM_INVALIDATE_ENG6_REQ[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG7_REQ", REG_MMIO, 0x06ea, 0, &mmVM_INVALIDATE_ENG7_REQ[0], sizeof(mmVM_INVALIDATE_ENG7_REQ)/sizeof(mmVM_INVALIDATE_ENG7_REQ[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG8_REQ", REG_MMIO, 0x06eb, 0, &mmVM_INVALIDATE_ENG8_REQ[0], sizeof(mmVM_INVALIDATE_ENG8_REQ)/sizeof(mmVM_INVALIDATE_ENG8_REQ[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG9_REQ", REG_MMIO, 0x06ec, 0, &mmVM_INVALIDATE_ENG9_REQ[0], sizeof(mmVM_INVALIDATE_ENG9_REQ)/sizeof(mmVM_INVALIDATE_ENG9_REQ[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG10_REQ", REG_MMIO, 0x06ed, 0, &mmVM_INVALIDATE_ENG10_REQ[0], sizeof(mmVM_INVALIDATE_ENG10_REQ)/sizeof(mmVM_INVALIDATE_ENG10_REQ[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG11_REQ", REG_MMIO, 0x06ee, 0, &mmVM_INVALIDATE_ENG11_REQ[0], sizeof(mmVM_INVALIDATE_ENG11_REQ)/sizeof(mmVM_INVALIDATE_ENG11_REQ[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG12_REQ", REG_MMIO, 0x06ef, 0, &mmVM_INVALIDATE_ENG12_REQ[0], sizeof(mmVM_INVALIDATE_ENG12_REQ)/sizeof(mmVM_INVALIDATE_ENG12_REQ[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG13_REQ", REG_MMIO, 0x06f0, 0, &mmVM_INVALIDATE_ENG13_REQ[0], sizeof(mmVM_INVALIDATE_ENG13_REQ)/sizeof(mmVM_INVALIDATE_ENG13_REQ[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG14_REQ", REG_MMIO, 0x06f1, 0, &mmVM_INVALIDATE_ENG14_REQ[0], sizeof(mmVM_INVALIDATE_ENG14_REQ)/sizeof(mmVM_INVALIDATE_ENG14_REQ[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG15_REQ", REG_MMIO, 0x06f2, 0, &mmVM_INVALIDATE_ENG15_REQ[0], sizeof(mmVM_INVALIDATE_ENG15_REQ)/sizeof(mmVM_INVALIDATE_ENG15_REQ[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG16_REQ", REG_MMIO, 0x06f3, 0, &mmVM_INVALIDATE_ENG16_REQ[0], sizeof(mmVM_INVALIDATE_ENG16_REQ)/sizeof(mmVM_INVALIDATE_ENG16_REQ[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG17_REQ", REG_MMIO, 0x06f4, 0, &mmVM_INVALIDATE_ENG17_REQ[0], sizeof(mmVM_INVALIDATE_ENG17_REQ)/sizeof(mmVM_INVALIDATE_ENG17_REQ[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG0_ACK", REG_MMIO, 0x06f5, 0, &mmVM_INVALIDATE_ENG0_ACK[0], sizeof(mmVM_INVALIDATE_ENG0_ACK)/sizeof(mmVM_INVALIDATE_ENG0_ACK[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG1_ACK", REG_MMIO, 0x06f6, 0, &mmVM_INVALIDATE_ENG1_ACK[0], sizeof(mmVM_INVALIDATE_ENG1_ACK)/sizeof(mmVM_INVALIDATE_ENG1_ACK[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG2_ACK", REG_MMIO, 0x06f7, 0, &mmVM_INVALIDATE_ENG2_ACK[0], sizeof(mmVM_INVALIDATE_ENG2_ACK)/sizeof(mmVM_INVALIDATE_ENG2_ACK[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG3_ACK", REG_MMIO, 0x06f8, 0, &mmVM_INVALIDATE_ENG3_ACK[0], sizeof(mmVM_INVALIDATE_ENG3_ACK)/sizeof(mmVM_INVALIDATE_ENG3_ACK[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG4_ACK", REG_MMIO, 0x06f9, 0, &mmVM_INVALIDATE_ENG4_ACK[0], sizeof(mmVM_INVALIDATE_ENG4_ACK)/sizeof(mmVM_INVALIDATE_ENG4_ACK[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG5_ACK", REG_MMIO, 0x06fa, 0, &mmVM_INVALIDATE_ENG5_ACK[0], sizeof(mmVM_INVALIDATE_ENG5_ACK)/sizeof(mmVM_INVALIDATE_ENG5_ACK[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG6_ACK", REG_MMIO, 0x06fb, 0, &mmVM_INVALIDATE_ENG6_ACK[0], sizeof(mmVM_INVALIDATE_ENG6_ACK)/sizeof(mmVM_INVALIDATE_ENG6_ACK[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG7_ACK", REG_MMIO, 0x06fc, 0, &mmVM_INVALIDATE_ENG7_ACK[0], sizeof(mmVM_INVALIDATE_ENG7_ACK)/sizeof(mmVM_INVALIDATE_ENG7_ACK[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG8_ACK", REG_MMIO, 0x06fd, 0, &mmVM_INVALIDATE_ENG8_ACK[0], sizeof(mmVM_INVALIDATE_ENG8_ACK)/sizeof(mmVM_INVALIDATE_ENG8_ACK[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG9_ACK", REG_MMIO, 0x06fe, 0, &mmVM_INVALIDATE_ENG9_ACK[0], sizeof(mmVM_INVALIDATE_ENG9_ACK)/sizeof(mmVM_INVALIDATE_ENG9_ACK[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG10_ACK", REG_MMIO, 0x06ff, 0, &mmVM_INVALIDATE_ENG10_ACK[0], sizeof(mmVM_INVALIDATE_ENG10_ACK)/sizeof(mmVM_INVALIDATE_ENG10_ACK[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG11_ACK", REG_MMIO, 0x0700, 0, &mmVM_INVALIDATE_ENG11_ACK[0], sizeof(mmVM_INVALIDATE_ENG11_ACK)/sizeof(mmVM_INVALIDATE_ENG11_ACK[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG12_ACK", REG_MMIO, 0x0701, 0, &mmVM_INVALIDATE_ENG12_ACK[0], sizeof(mmVM_INVALIDATE_ENG12_ACK)/sizeof(mmVM_INVALIDATE_ENG12_ACK[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG13_ACK", REG_MMIO, 0x0702, 0, &mmVM_INVALIDATE_ENG13_ACK[0], sizeof(mmVM_INVALIDATE_ENG13_ACK)/sizeof(mmVM_INVALIDATE_ENG13_ACK[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG14_ACK", REG_MMIO, 0x0703, 0, &mmVM_INVALIDATE_ENG14_ACK[0], sizeof(mmVM_INVALIDATE_ENG14_ACK)/sizeof(mmVM_INVALIDATE_ENG14_ACK[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG15_ACK", REG_MMIO, 0x0704, 0, &mmVM_INVALIDATE_ENG15_ACK[0], sizeof(mmVM_INVALIDATE_ENG15_ACK)/sizeof(mmVM_INVALIDATE_ENG15_ACK[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG16_ACK", REG_MMIO, 0x0705, 0, &mmVM_INVALIDATE_ENG16_ACK[0], sizeof(mmVM_INVALIDATE_ENG16_ACK)/sizeof(mmVM_INVALIDATE_ENG16_ACK[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG17_ACK", REG_MMIO, 0x0706, 0, &mmVM_INVALIDATE_ENG17_ACK[0], sizeof(mmVM_INVALIDATE_ENG17_ACK)/sizeof(mmVM_INVALIDATE_ENG17_ACK[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32", REG_MMIO, 0x0707, 0, &mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32[0], sizeof(mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32)/sizeof(mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32", REG_MMIO, 0x0708, 0, &mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32[0], sizeof(mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32)/sizeof(mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32", REG_MMIO, 0x0709, 0, &mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32[0], sizeof(mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32)/sizeof(mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG1_ADDR_RANGE_HI32", REG_MMIO, 0x070a, 0, &mmVM_INVALIDATE_ENG1_ADDR_RANGE_HI32[0], sizeof(mmVM_INVALIDATE_ENG1_ADDR_RANGE_HI32)/sizeof(mmVM_INVALIDATE_ENG1_ADDR_RANGE_HI32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG2_ADDR_RANGE_LO32", REG_MMIO, 0x070b, 0, &mmVM_INVALIDATE_ENG2_ADDR_RANGE_LO32[0], sizeof(mmVM_INVALIDATE_ENG2_ADDR_RANGE_LO32)/sizeof(mmVM_INVALIDATE_ENG2_ADDR_RANGE_LO32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG2_ADDR_RANGE_HI32", REG_MMIO, 0x070c, 0, &mmVM_INVALIDATE_ENG2_ADDR_RANGE_HI32[0], sizeof(mmVM_INVALIDATE_ENG2_ADDR_RANGE_HI32)/sizeof(mmVM_INVALIDATE_ENG2_ADDR_RANGE_HI32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG3_ADDR_RANGE_LO32", REG_MMIO, 0x070d, 0, &mmVM_INVALIDATE_ENG3_ADDR_RANGE_LO32[0], sizeof(mmVM_INVALIDATE_ENG3_ADDR_RANGE_LO32)/sizeof(mmVM_INVALIDATE_ENG3_ADDR_RANGE_LO32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG3_ADDR_RANGE_HI32", REG_MMIO, 0x070e, 0, &mmVM_INVALIDATE_ENG3_ADDR_RANGE_HI32[0], sizeof(mmVM_INVALIDATE_ENG3_ADDR_RANGE_HI32)/sizeof(mmVM_INVALIDATE_ENG3_ADDR_RANGE_HI32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG4_ADDR_RANGE_LO32", REG_MMIO, 0x070f, 0, &mmVM_INVALIDATE_ENG4_ADDR_RANGE_LO32[0], sizeof(mmVM_INVALIDATE_ENG4_ADDR_RANGE_LO32)/sizeof(mmVM_INVALIDATE_ENG4_ADDR_RANGE_LO32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG4_ADDR_RANGE_HI32", REG_MMIO, 0x0710, 0, &mmVM_INVALIDATE_ENG4_ADDR_RANGE_HI32[0], sizeof(mmVM_INVALIDATE_ENG4_ADDR_RANGE_HI32)/sizeof(mmVM_INVALIDATE_ENG4_ADDR_RANGE_HI32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG5_ADDR_RANGE_LO32", REG_MMIO, 0x0711, 0, &mmVM_INVALIDATE_ENG5_ADDR_RANGE_LO32[0], sizeof(mmVM_INVALIDATE_ENG5_ADDR_RANGE_LO32)/sizeof(mmVM_INVALIDATE_ENG5_ADDR_RANGE_LO32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG5_ADDR_RANGE_HI32", REG_MMIO, 0x0712, 0, &mmVM_INVALIDATE_ENG5_ADDR_RANGE_HI32[0], sizeof(mmVM_INVALIDATE_ENG5_ADDR_RANGE_HI32)/sizeof(mmVM_INVALIDATE_ENG5_ADDR_RANGE_HI32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG6_ADDR_RANGE_LO32", REG_MMIO, 0x0713, 0, &mmVM_INVALIDATE_ENG6_ADDR_RANGE_LO32[0], sizeof(mmVM_INVALIDATE_ENG6_ADDR_RANGE_LO32)/sizeof(mmVM_INVALIDATE_ENG6_ADDR_RANGE_LO32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG6_ADDR_RANGE_HI32", REG_MMIO, 0x0714, 0, &mmVM_INVALIDATE_ENG6_ADDR_RANGE_HI32[0], sizeof(mmVM_INVALIDATE_ENG6_ADDR_RANGE_HI32)/sizeof(mmVM_INVALIDATE_ENG6_ADDR_RANGE_HI32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG7_ADDR_RANGE_LO32", REG_MMIO, 0x0715, 0, &mmVM_INVALIDATE_ENG7_ADDR_RANGE_LO32[0], sizeof(mmVM_INVALIDATE_ENG7_ADDR_RANGE_LO32)/sizeof(mmVM_INVALIDATE_ENG7_ADDR_RANGE_LO32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG7_ADDR_RANGE_HI32", REG_MMIO, 0x0716, 0, &mmVM_INVALIDATE_ENG7_ADDR_RANGE_HI32[0], sizeof(mmVM_INVALIDATE_ENG7_ADDR_RANGE_HI32)/sizeof(mmVM_INVALIDATE_ENG7_ADDR_RANGE_HI32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG8_ADDR_RANGE_LO32", REG_MMIO, 0x0717, 0, &mmVM_INVALIDATE_ENG8_ADDR_RANGE_LO32[0], sizeof(mmVM_INVALIDATE_ENG8_ADDR_RANGE_LO32)/sizeof(mmVM_INVALIDATE_ENG8_ADDR_RANGE_LO32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG8_ADDR_RANGE_HI32", REG_MMIO, 0x0718, 0, &mmVM_INVALIDATE_ENG8_ADDR_RANGE_HI32[0], sizeof(mmVM_INVALIDATE_ENG8_ADDR_RANGE_HI32)/sizeof(mmVM_INVALIDATE_ENG8_ADDR_RANGE_HI32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG9_ADDR_RANGE_LO32", REG_MMIO, 0x0719, 0, &mmVM_INVALIDATE_ENG9_ADDR_RANGE_LO32[0], sizeof(mmVM_INVALIDATE_ENG9_ADDR_RANGE_LO32)/sizeof(mmVM_INVALIDATE_ENG9_ADDR_RANGE_LO32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG9_ADDR_RANGE_HI32", REG_MMIO, 0x071a, 0, &mmVM_INVALIDATE_ENG9_ADDR_RANGE_HI32[0], sizeof(mmVM_INVALIDATE_ENG9_ADDR_RANGE_HI32)/sizeof(mmVM_INVALIDATE_ENG9_ADDR_RANGE_HI32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG10_ADDR_RANGE_LO32", REG_MMIO, 0x071b, 0, &mmVM_INVALIDATE_ENG10_ADDR_RANGE_LO32[0], sizeof(mmVM_INVALIDATE_ENG10_ADDR_RANGE_LO32)/sizeof(mmVM_INVALIDATE_ENG10_ADDR_RANGE_LO32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG10_ADDR_RANGE_HI32", REG_MMIO, 0x071c, 0, &mmVM_INVALIDATE_ENG10_ADDR_RANGE_HI32[0], sizeof(mmVM_INVALIDATE_ENG10_ADDR_RANGE_HI32)/sizeof(mmVM_INVALIDATE_ENG10_ADDR_RANGE_HI32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG11_ADDR_RANGE_LO32", REG_MMIO, 0x071d, 0, &mmVM_INVALIDATE_ENG11_ADDR_RANGE_LO32[0], sizeof(mmVM_INVALIDATE_ENG11_ADDR_RANGE_LO32)/sizeof(mmVM_INVALIDATE_ENG11_ADDR_RANGE_LO32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG11_ADDR_RANGE_HI32", REG_MMIO, 0x071e, 0, &mmVM_INVALIDATE_ENG11_ADDR_RANGE_HI32[0], sizeof(mmVM_INVALIDATE_ENG11_ADDR_RANGE_HI32)/sizeof(mmVM_INVALIDATE_ENG11_ADDR_RANGE_HI32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG12_ADDR_RANGE_LO32", REG_MMIO, 0x071f, 0, &mmVM_INVALIDATE_ENG12_ADDR_RANGE_LO32[0], sizeof(mmVM_INVALIDATE_ENG12_ADDR_RANGE_LO32)/sizeof(mmVM_INVALIDATE_ENG12_ADDR_RANGE_LO32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG12_ADDR_RANGE_HI32", REG_MMIO, 0x0720, 0, &mmVM_INVALIDATE_ENG12_ADDR_RANGE_HI32[0], sizeof(mmVM_INVALIDATE_ENG12_ADDR_RANGE_HI32)/sizeof(mmVM_INVALIDATE_ENG12_ADDR_RANGE_HI32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG13_ADDR_RANGE_LO32", REG_MMIO, 0x0721, 0, &mmVM_INVALIDATE_ENG13_ADDR_RANGE_LO32[0], sizeof(mmVM_INVALIDATE_ENG13_ADDR_RANGE_LO32)/sizeof(mmVM_INVALIDATE_ENG13_ADDR_RANGE_LO32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG13_ADDR_RANGE_HI32", REG_MMIO, 0x0722, 0, &mmVM_INVALIDATE_ENG13_ADDR_RANGE_HI32[0], sizeof(mmVM_INVALIDATE_ENG13_ADDR_RANGE_HI32)/sizeof(mmVM_INVALIDATE_ENG13_ADDR_RANGE_HI32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG14_ADDR_RANGE_LO32", REG_MMIO, 0x0723, 0, &mmVM_INVALIDATE_ENG14_ADDR_RANGE_LO32[0], sizeof(mmVM_INVALIDATE_ENG14_ADDR_RANGE_LO32)/sizeof(mmVM_INVALIDATE_ENG14_ADDR_RANGE_LO32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG14_ADDR_RANGE_HI32", REG_MMIO, 0x0724, 0, &mmVM_INVALIDATE_ENG14_ADDR_RANGE_HI32[0], sizeof(mmVM_INVALIDATE_ENG14_ADDR_RANGE_HI32)/sizeof(mmVM_INVALIDATE_ENG14_ADDR_RANGE_HI32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG15_ADDR_RANGE_LO32", REG_MMIO, 0x0725, 0, &mmVM_INVALIDATE_ENG15_ADDR_RANGE_LO32[0], sizeof(mmVM_INVALIDATE_ENG15_ADDR_RANGE_LO32)/sizeof(mmVM_INVALIDATE_ENG15_ADDR_RANGE_LO32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG15_ADDR_RANGE_HI32", REG_MMIO, 0x0726, 0, &mmVM_INVALIDATE_ENG15_ADDR_RANGE_HI32[0], sizeof(mmVM_INVALIDATE_ENG15_ADDR_RANGE_HI32)/sizeof(mmVM_INVALIDATE_ENG15_ADDR_RANGE_HI32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG16_ADDR_RANGE_LO32", REG_MMIO, 0x0727, 0, &mmVM_INVALIDATE_ENG16_ADDR_RANGE_LO32[0], sizeof(mmVM_INVALIDATE_ENG16_ADDR_RANGE_LO32)/sizeof(mmVM_INVALIDATE_ENG16_ADDR_RANGE_LO32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG16_ADDR_RANGE_HI32", REG_MMIO, 0x0728, 0, &mmVM_INVALIDATE_ENG16_ADDR_RANGE_HI32[0], sizeof(mmVM_INVALIDATE_ENG16_ADDR_RANGE_HI32)/sizeof(mmVM_INVALIDATE_ENG16_ADDR_RANGE_HI32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG17_ADDR_RANGE_LO32", REG_MMIO, 0x0729, 0, &mmVM_INVALIDATE_ENG17_ADDR_RANGE_LO32[0], sizeof(mmVM_INVALIDATE_ENG17_ADDR_RANGE_LO32)/sizeof(mmVM_INVALIDATE_ENG17_ADDR_RANGE_LO32[0]), 0, 0 }, + { "mmVM_INVALIDATE_ENG17_ADDR_RANGE_HI32", REG_MMIO, 0x072a, 0, &mmVM_INVALIDATE_ENG17_ADDR_RANGE_HI32[0], sizeof(mmVM_INVALIDATE_ENG17_ADDR_RANGE_HI32)/sizeof(mmVM_INVALIDATE_ENG17_ADDR_RANGE_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32", REG_MMIO, 0x072b, 0, &mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32[0], sizeof(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32)/sizeof(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32", REG_MMIO, 0x072c, 0, &mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32[0], sizeof(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32)/sizeof(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32", REG_MMIO, 0x072d, 0, &mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32[0], sizeof(mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32)/sizeof(mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32", REG_MMIO, 0x072e, 0, &mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32[0], sizeof(mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32)/sizeof(mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32", REG_MMIO, 0x072f, 0, &mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32[0], sizeof(mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32)/sizeof(mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32", REG_MMIO, 0x0730, 0, &mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32[0], sizeof(mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32)/sizeof(mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32", REG_MMIO, 0x0731, 0, &mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32[0], sizeof(mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32)/sizeof(mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32", REG_MMIO, 0x0732, 0, &mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32[0], sizeof(mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32)/sizeof(mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32", REG_MMIO, 0x0733, 0, &mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32[0], sizeof(mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32)/sizeof(mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32", REG_MMIO, 0x0734, 0, &mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32[0], sizeof(mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32)/sizeof(mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32", REG_MMIO, 0x0735, 0, &mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32[0], sizeof(mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32)/sizeof(mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32", REG_MMIO, 0x0736, 0, &mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32[0], sizeof(mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32)/sizeof(mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32", REG_MMIO, 0x0737, 0, &mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32[0], sizeof(mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32)/sizeof(mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32", REG_MMIO, 0x0738, 0, &mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32[0], sizeof(mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32)/sizeof(mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32", REG_MMIO, 0x0739, 0, &mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32[0], sizeof(mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32)/sizeof(mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32", REG_MMIO, 0x073a, 0, &mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32[0], sizeof(mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32)/sizeof(mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32", REG_MMIO, 0x073b, 0, &mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32[0], sizeof(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32)/sizeof(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32", REG_MMIO, 0x073c, 0, &mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32[0], sizeof(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32)/sizeof(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32", REG_MMIO, 0x073d, 0, &mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32[0], sizeof(mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32)/sizeof(mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32", REG_MMIO, 0x073e, 0, &mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32[0], sizeof(mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32)/sizeof(mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32", REG_MMIO, 0x073f, 0, &mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32[0], sizeof(mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32)/sizeof(mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32", REG_MMIO, 0x0740, 0, &mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32[0], sizeof(mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32)/sizeof(mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32", REG_MMIO, 0x0741, 0, &mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32[0], sizeof(mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32)/sizeof(mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32", REG_MMIO, 0x0742, 0, &mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32[0], sizeof(mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32)/sizeof(mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32", REG_MMIO, 0x0743, 0, &mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32[0], sizeof(mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32)/sizeof(mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32", REG_MMIO, 0x0744, 0, &mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32[0], sizeof(mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32)/sizeof(mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32", REG_MMIO, 0x0745, 0, &mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32[0], sizeof(mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32)/sizeof(mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32", REG_MMIO, 0x0746, 0, &mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32[0], sizeof(mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32)/sizeof(mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32", REG_MMIO, 0x0747, 0, &mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32[0], sizeof(mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32)/sizeof(mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32", REG_MMIO, 0x0748, 0, &mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32[0], sizeof(mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32)/sizeof(mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32", REG_MMIO, 0x0749, 0, &mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32[0], sizeof(mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32)/sizeof(mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32", REG_MMIO, 0x074a, 0, &mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32[0], sizeof(mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32)/sizeof(mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32", REG_MMIO, 0x074b, 0, &mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32[0], sizeof(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32)/sizeof(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32", REG_MMIO, 0x074c, 0, &mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32[0], sizeof(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32)/sizeof(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32", REG_MMIO, 0x074d, 0, &mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32[0], sizeof(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32)/sizeof(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32", REG_MMIO, 0x074e, 0, &mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32[0], sizeof(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32)/sizeof(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32", REG_MMIO, 0x074f, 0, &mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32[0], sizeof(mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32)/sizeof(mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32", REG_MMIO, 0x0750, 0, &mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32[0], sizeof(mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32)/sizeof(mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32", REG_MMIO, 0x0751, 0, &mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32[0], sizeof(mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32)/sizeof(mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32", REG_MMIO, 0x0752, 0, &mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32[0], sizeof(mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32)/sizeof(mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32", REG_MMIO, 0x0753, 0, &mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32[0], sizeof(mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32)/sizeof(mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32", REG_MMIO, 0x0754, 0, &mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32[0], sizeof(mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32)/sizeof(mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32", REG_MMIO, 0x0755, 0, &mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32[0], sizeof(mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32)/sizeof(mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32", REG_MMIO, 0x0756, 0, &mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32[0], sizeof(mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32)/sizeof(mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32", REG_MMIO, 0x0757, 0, &mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32[0], sizeof(mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32)/sizeof(mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32", REG_MMIO, 0x0758, 0, &mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32[0], sizeof(mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32)/sizeof(mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32", REG_MMIO, 0x0759, 0, &mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32[0], sizeof(mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32)/sizeof(mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32", REG_MMIO, 0x075a, 0, &mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32[0], sizeof(mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32)/sizeof(mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32", REG_MMIO, 0x075b, 0, &mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32[0], sizeof(mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32)/sizeof(mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32", REG_MMIO, 0x075c, 0, &mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32[0], sizeof(mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32)/sizeof(mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32", REG_MMIO, 0x075d, 0, &mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32[0], sizeof(mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32)/sizeof(mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32", REG_MMIO, 0x075e, 0, &mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32[0], sizeof(mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32)/sizeof(mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32", REG_MMIO, 0x075f, 0, &mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32[0], sizeof(mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32)/sizeof(mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32", REG_MMIO, 0x0760, 0, &mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32[0], sizeof(mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32)/sizeof(mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32", REG_MMIO, 0x0761, 0, &mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32[0], sizeof(mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32)/sizeof(mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32", REG_MMIO, 0x0762, 0, &mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32[0], sizeof(mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32)/sizeof(mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32", REG_MMIO, 0x0763, 0, &mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32[0], sizeof(mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32)/sizeof(mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32", REG_MMIO, 0x0764, 0, &mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32[0], sizeof(mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32)/sizeof(mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32", REG_MMIO, 0x0765, 0, &mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32[0], sizeof(mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32)/sizeof(mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32", REG_MMIO, 0x0766, 0, &mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32[0], sizeof(mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32)/sizeof(mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32", REG_MMIO, 0x0767, 0, &mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32[0], sizeof(mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32)/sizeof(mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32", REG_MMIO, 0x0768, 0, &mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32[0], sizeof(mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32)/sizeof(mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32", REG_MMIO, 0x0769, 0, &mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32[0], sizeof(mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32)/sizeof(mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32", REG_MMIO, 0x076a, 0, &mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32[0], sizeof(mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32)/sizeof(mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32", REG_MMIO, 0x076b, 0, &mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32[0], sizeof(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32)/sizeof(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32", REG_MMIO, 0x076c, 0, &mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32[0], sizeof(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32)/sizeof(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32", REG_MMIO, 0x076d, 0, &mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32[0], sizeof(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32)/sizeof(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32", REG_MMIO, 0x076e, 0, &mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32[0], sizeof(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32)/sizeof(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32", REG_MMIO, 0x076f, 0, &mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32[0], sizeof(mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32)/sizeof(mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32", REG_MMIO, 0x0770, 0, &mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32[0], sizeof(mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32)/sizeof(mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32", REG_MMIO, 0x0771, 0, &mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32[0], sizeof(mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32)/sizeof(mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32", REG_MMIO, 0x0772, 0, &mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32[0], sizeof(mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32)/sizeof(mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32", REG_MMIO, 0x0773, 0, &mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32[0], sizeof(mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32)/sizeof(mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32", REG_MMIO, 0x0774, 0, &mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32[0], sizeof(mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32)/sizeof(mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32", REG_MMIO, 0x0775, 0, &mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32[0], sizeof(mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32)/sizeof(mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32", REG_MMIO, 0x0776, 0, &mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32[0], sizeof(mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32)/sizeof(mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32", REG_MMIO, 0x0777, 0, &mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32[0], sizeof(mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32)/sizeof(mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32", REG_MMIO, 0x0778, 0, &mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32[0], sizeof(mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32)/sizeof(mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32", REG_MMIO, 0x0779, 0, &mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32[0], sizeof(mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32)/sizeof(mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32", REG_MMIO, 0x077a, 0, &mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32[0], sizeof(mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32)/sizeof(mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32", REG_MMIO, 0x077b, 0, &mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32[0], sizeof(mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32)/sizeof(mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32", REG_MMIO, 0x077c, 0, &mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32[0], sizeof(mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32)/sizeof(mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32", REG_MMIO, 0x077d, 0, &mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32[0], sizeof(mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32)/sizeof(mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32", REG_MMIO, 0x077e, 0, &mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32[0], sizeof(mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32)/sizeof(mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32", REG_MMIO, 0x077f, 0, &mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32[0], sizeof(mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32)/sizeof(mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32", REG_MMIO, 0x0780, 0, &mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32[0], sizeof(mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32)/sizeof(mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32", REG_MMIO, 0x0781, 0, &mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32[0], sizeof(mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32)/sizeof(mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32", REG_MMIO, 0x0782, 0, &mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32[0], sizeof(mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32)/sizeof(mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32", REG_MMIO, 0x0783, 0, &mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32[0], sizeof(mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32)/sizeof(mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32", REG_MMIO, 0x0784, 0, &mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32[0], sizeof(mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32)/sizeof(mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32", REG_MMIO, 0x0785, 0, &mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32[0], sizeof(mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32)/sizeof(mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32", REG_MMIO, 0x0786, 0, &mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32[0], sizeof(mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32)/sizeof(mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32", REG_MMIO, 0x0787, 0, &mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32[0], sizeof(mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32)/sizeof(mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32", REG_MMIO, 0x0788, 0, &mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32[0], sizeof(mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32)/sizeof(mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32[0]), 0, 0 }, + { "mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32", REG_MMIO, 0x0789, 0, &mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32[0], sizeof(mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32)/sizeof(mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32[0]), 0, 0 }, + { "mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32", REG_MMIO, 0x078a, 0, &mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32[0], sizeof(mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32)/sizeof(mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32[0]), 0, 0 }, + { "mmMC_VM_L2_PERFCOUNTER0_CFG", REG_MMIO, 0x07a4, 0, &mmMC_VM_L2_PERFCOUNTER0_CFG[0], sizeof(mmMC_VM_L2_PERFCOUNTER0_CFG)/sizeof(mmMC_VM_L2_PERFCOUNTER0_CFG[0]), 0, 0 }, + { "mmMC_VM_L2_PERFCOUNTER1_CFG", REG_MMIO, 0x07a5, 0, &mmMC_VM_L2_PERFCOUNTER1_CFG[0], sizeof(mmMC_VM_L2_PERFCOUNTER1_CFG)/sizeof(mmMC_VM_L2_PERFCOUNTER1_CFG[0]), 0, 0 }, + { "mmMC_VM_L2_PERFCOUNTER2_CFG", REG_MMIO, 0x07a6, 0, &mmMC_VM_L2_PERFCOUNTER2_CFG[0], sizeof(mmMC_VM_L2_PERFCOUNTER2_CFG)/sizeof(mmMC_VM_L2_PERFCOUNTER2_CFG[0]), 0, 0 }, + { "mmMC_VM_L2_PERFCOUNTER3_CFG", REG_MMIO, 0x07a7, 0, &mmMC_VM_L2_PERFCOUNTER3_CFG[0], sizeof(mmMC_VM_L2_PERFCOUNTER3_CFG)/sizeof(mmMC_VM_L2_PERFCOUNTER3_CFG[0]), 0, 0 }, + { "mmMC_VM_L2_PERFCOUNTER4_CFG", REG_MMIO, 0x07a8, 0, &mmMC_VM_L2_PERFCOUNTER4_CFG[0], sizeof(mmMC_VM_L2_PERFCOUNTER4_CFG)/sizeof(mmMC_VM_L2_PERFCOUNTER4_CFG[0]), 0, 0 }, + { "mmMC_VM_L2_PERFCOUNTER5_CFG", REG_MMIO, 0x07a9, 0, &mmMC_VM_L2_PERFCOUNTER5_CFG[0], sizeof(mmMC_VM_L2_PERFCOUNTER5_CFG)/sizeof(mmMC_VM_L2_PERFCOUNTER5_CFG[0]), 0, 0 }, + { "mmMC_VM_L2_PERFCOUNTER6_CFG", REG_MMIO, 0x07aa, 0, &mmMC_VM_L2_PERFCOUNTER6_CFG[0], sizeof(mmMC_VM_L2_PERFCOUNTER6_CFG)/sizeof(mmMC_VM_L2_PERFCOUNTER6_CFG[0]), 0, 0 }, + { "mmMC_VM_L2_PERFCOUNTER7_CFG", REG_MMIO, 0x07ab, 0, &mmMC_VM_L2_PERFCOUNTER7_CFG[0], sizeof(mmMC_VM_L2_PERFCOUNTER7_CFG)/sizeof(mmMC_VM_L2_PERFCOUNTER7_CFG[0]), 0, 0 }, + { "mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL", REG_MMIO, 0x07ac, 0, &mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL[0], sizeof(mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL)/sizeof(mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL[0]), 0, 0 }, + { "mmMC_VM_L2_PERFCOUNTER_LO", REG_MMIO, 0x07b8, 0, &mmMC_VM_L2_PERFCOUNTER_LO[0], sizeof(mmMC_VM_L2_PERFCOUNTER_LO)/sizeof(mmMC_VM_L2_PERFCOUNTER_LO[0]), 0, 0 }, + { "mmMC_VM_L2_PERFCOUNTER_HI", REG_MMIO, 0x07b9, 0, &mmMC_VM_L2_PERFCOUNTER_HI[0], sizeof(mmMC_VM_L2_PERFCOUNTER_HI)/sizeof(mmMC_VM_L2_PERFCOUNTER_HI[0]), 0, 0 }, + { "mmMC_VM_FB_SIZE_OFFSET_VF0", REG_MMIO, 0x07cc, 0, &mmMC_VM_FB_SIZE_OFFSET_VF0[0], sizeof(mmMC_VM_FB_SIZE_OFFSET_VF0)/sizeof(mmMC_VM_FB_SIZE_OFFSET_VF0[0]), 0, 0 }, + { "mmMC_VM_FB_SIZE_OFFSET_VF1", REG_MMIO, 0x07cd, 0, &mmMC_VM_FB_SIZE_OFFSET_VF1[0], sizeof(mmMC_VM_FB_SIZE_OFFSET_VF1)/sizeof(mmMC_VM_FB_SIZE_OFFSET_VF1[0]), 0, 0 }, + { "mmMC_VM_FB_SIZE_OFFSET_VF2", REG_MMIO, 0x07ce, 0, &mmMC_VM_FB_SIZE_OFFSET_VF2[0], sizeof(mmMC_VM_FB_SIZE_OFFSET_VF2)/sizeof(mmMC_VM_FB_SIZE_OFFSET_VF2[0]), 0, 0 }, + { "mmMC_VM_FB_SIZE_OFFSET_VF3", REG_MMIO, 0x07cf, 0, &mmMC_VM_FB_SIZE_OFFSET_VF3[0], sizeof(mmMC_VM_FB_SIZE_OFFSET_VF3)/sizeof(mmMC_VM_FB_SIZE_OFFSET_VF3[0]), 0, 0 }, + { "mmMC_VM_FB_SIZE_OFFSET_VF4", REG_MMIO, 0x07d0, 0, &mmMC_VM_FB_SIZE_OFFSET_VF4[0], sizeof(mmMC_VM_FB_SIZE_OFFSET_VF4)/sizeof(mmMC_VM_FB_SIZE_OFFSET_VF4[0]), 0, 0 }, + { "mmMC_VM_FB_SIZE_OFFSET_VF5", REG_MMIO, 0x07d1, 0, &mmMC_VM_FB_SIZE_OFFSET_VF5[0], sizeof(mmMC_VM_FB_SIZE_OFFSET_VF5)/sizeof(mmMC_VM_FB_SIZE_OFFSET_VF5[0]), 0, 0 }, + { "mmMC_VM_FB_SIZE_OFFSET_VF6", REG_MMIO, 0x07d2, 0, &mmMC_VM_FB_SIZE_OFFSET_VF6[0], sizeof(mmMC_VM_FB_SIZE_OFFSET_VF6)/sizeof(mmMC_VM_FB_SIZE_OFFSET_VF6[0]), 0, 0 }, + { "mmMC_VM_FB_SIZE_OFFSET_VF7", REG_MMIO, 0x07d3, 0, &mmMC_VM_FB_SIZE_OFFSET_VF7[0], sizeof(mmMC_VM_FB_SIZE_OFFSET_VF7)/sizeof(mmMC_VM_FB_SIZE_OFFSET_VF7[0]), 0, 0 }, + { "mmMC_VM_FB_SIZE_OFFSET_VF8", REG_MMIO, 0x07d4, 0, &mmMC_VM_FB_SIZE_OFFSET_VF8[0], sizeof(mmMC_VM_FB_SIZE_OFFSET_VF8)/sizeof(mmMC_VM_FB_SIZE_OFFSET_VF8[0]), 0, 0 }, + { "mmMC_VM_FB_SIZE_OFFSET_VF9", REG_MMIO, 0x07d5, 0, &mmMC_VM_FB_SIZE_OFFSET_VF9[0], sizeof(mmMC_VM_FB_SIZE_OFFSET_VF9)/sizeof(mmMC_VM_FB_SIZE_OFFSET_VF9[0]), 0, 0 }, + { "mmMC_VM_FB_SIZE_OFFSET_VF10", REG_MMIO, 0x07d6, 0, &mmMC_VM_FB_SIZE_OFFSET_VF10[0], sizeof(mmMC_VM_FB_SIZE_OFFSET_VF10)/sizeof(mmMC_VM_FB_SIZE_OFFSET_VF10[0]), 0, 0 }, + { "mmMC_VM_FB_SIZE_OFFSET_VF11", REG_MMIO, 0x07d7, 0, &mmMC_VM_FB_SIZE_OFFSET_VF11[0], sizeof(mmMC_VM_FB_SIZE_OFFSET_VF11)/sizeof(mmMC_VM_FB_SIZE_OFFSET_VF11[0]), 0, 0 }, + { "mmMC_VM_FB_SIZE_OFFSET_VF12", REG_MMIO, 0x07d8, 0, &mmMC_VM_FB_SIZE_OFFSET_VF12[0], sizeof(mmMC_VM_FB_SIZE_OFFSET_VF12)/sizeof(mmMC_VM_FB_SIZE_OFFSET_VF12[0]), 0, 0 }, + { "mmMC_VM_FB_SIZE_OFFSET_VF13", REG_MMIO, 0x07d9, 0, &mmMC_VM_FB_SIZE_OFFSET_VF13[0], sizeof(mmMC_VM_FB_SIZE_OFFSET_VF13)/sizeof(mmMC_VM_FB_SIZE_OFFSET_VF13[0]), 0, 0 }, + { "mmMC_VM_FB_SIZE_OFFSET_VF14", REG_MMIO, 0x07da, 0, &mmMC_VM_FB_SIZE_OFFSET_VF14[0], sizeof(mmMC_VM_FB_SIZE_OFFSET_VF14)/sizeof(mmMC_VM_FB_SIZE_OFFSET_VF14[0]), 0, 0 }, + { "mmMC_VM_FB_SIZE_OFFSET_VF15", REG_MMIO, 0x07db, 0, &mmMC_VM_FB_SIZE_OFFSET_VF15[0], sizeof(mmMC_VM_FB_SIZE_OFFSET_VF15)/sizeof(mmMC_VM_FB_SIZE_OFFSET_VF15[0]), 0, 0 }, + { "mmVM_IOMMU_MMIO_CNTRL_1", REG_MMIO, 0x07dc, 0, &mmVM_IOMMU_MMIO_CNTRL_1[0], sizeof(mmVM_IOMMU_MMIO_CNTRL_1)/sizeof(mmVM_IOMMU_MMIO_CNTRL_1[0]), 0, 0 }, + { "mmMC_VM_MARC_BASE_LO_0", REG_MMIO, 0x07dd, 0, &mmMC_VM_MARC_BASE_LO_0[0], sizeof(mmMC_VM_MARC_BASE_LO_0)/sizeof(mmMC_VM_MARC_BASE_LO_0[0]), 0, 0 }, + { "mmMC_VM_MARC_BASE_LO_1", REG_MMIO, 0x07de, 0, &mmMC_VM_MARC_BASE_LO_1[0], sizeof(mmMC_VM_MARC_BASE_LO_1)/sizeof(mmMC_VM_MARC_BASE_LO_1[0]), 0, 0 }, + { "mmMC_VM_MARC_BASE_LO_2", REG_MMIO, 0x07df, 0, &mmMC_VM_MARC_BASE_LO_2[0], sizeof(mmMC_VM_MARC_BASE_LO_2)/sizeof(mmMC_VM_MARC_BASE_LO_2[0]), 0, 0 }, + { "mmMC_VM_MARC_BASE_LO_3", REG_MMIO, 0x07e0, 0, &mmMC_VM_MARC_BASE_LO_3[0], sizeof(mmMC_VM_MARC_BASE_LO_3)/sizeof(mmMC_VM_MARC_BASE_LO_3[0]), 0, 0 }, + { "mmMC_VM_MARC_BASE_HI_0", REG_MMIO, 0x07e1, 0, &mmMC_VM_MARC_BASE_HI_0[0], sizeof(mmMC_VM_MARC_BASE_HI_0)/sizeof(mmMC_VM_MARC_BASE_HI_0[0]), 0, 0 }, + { "mmMC_VM_MARC_BASE_HI_1", REG_MMIO, 0x07e2, 0, &mmMC_VM_MARC_BASE_HI_1[0], sizeof(mmMC_VM_MARC_BASE_HI_1)/sizeof(mmMC_VM_MARC_BASE_HI_1[0]), 0, 0 }, + { "mmMC_VM_MARC_BASE_HI_2", REG_MMIO, 0x07e3, 0, &mmMC_VM_MARC_BASE_HI_2[0], sizeof(mmMC_VM_MARC_BASE_HI_2)/sizeof(mmMC_VM_MARC_BASE_HI_2[0]), 0, 0 }, + { "mmMC_VM_MARC_BASE_HI_3", REG_MMIO, 0x07e4, 0, &mmMC_VM_MARC_BASE_HI_3[0], sizeof(mmMC_VM_MARC_BASE_HI_3)/sizeof(mmMC_VM_MARC_BASE_HI_3[0]), 0, 0 }, + { "mmMC_VM_MARC_RELOC_LO_0", REG_MMIO, 0x07e5, 0, &mmMC_VM_MARC_RELOC_LO_0[0], sizeof(mmMC_VM_MARC_RELOC_LO_0)/sizeof(mmMC_VM_MARC_RELOC_LO_0[0]), 0, 0 }, + { "mmMC_VM_MARC_RELOC_LO_1", REG_MMIO, 0x07e6, 0, &mmMC_VM_MARC_RELOC_LO_1[0], sizeof(mmMC_VM_MARC_RELOC_LO_1)/sizeof(mmMC_VM_MARC_RELOC_LO_1[0]), 0, 0 }, + { "mmMC_VM_MARC_RELOC_LO_2", REG_MMIO, 0x07e7, 0, &mmMC_VM_MARC_RELOC_LO_2[0], sizeof(mmMC_VM_MARC_RELOC_LO_2)/sizeof(mmMC_VM_MARC_RELOC_LO_2[0]), 0, 0 }, + { "mmMC_VM_MARC_RELOC_LO_3", REG_MMIO, 0x07e8, 0, &mmMC_VM_MARC_RELOC_LO_3[0], sizeof(mmMC_VM_MARC_RELOC_LO_3)/sizeof(mmMC_VM_MARC_RELOC_LO_3[0]), 0, 0 }, + { "mmMC_VM_MARC_RELOC_HI_0", REG_MMIO, 0x07e9, 0, &mmMC_VM_MARC_RELOC_HI_0[0], sizeof(mmMC_VM_MARC_RELOC_HI_0)/sizeof(mmMC_VM_MARC_RELOC_HI_0[0]), 0, 0 }, + { "mmMC_VM_MARC_RELOC_HI_1", REG_MMIO, 0x07ea, 0, &mmMC_VM_MARC_RELOC_HI_1[0], sizeof(mmMC_VM_MARC_RELOC_HI_1)/sizeof(mmMC_VM_MARC_RELOC_HI_1[0]), 0, 0 }, + { "mmMC_VM_MARC_RELOC_HI_2", REG_MMIO, 0x07eb, 0, &mmMC_VM_MARC_RELOC_HI_2[0], sizeof(mmMC_VM_MARC_RELOC_HI_2)/sizeof(mmMC_VM_MARC_RELOC_HI_2[0]), 0, 0 }, + { "mmMC_VM_MARC_RELOC_HI_3", REG_MMIO, 0x07ec, 0, &mmMC_VM_MARC_RELOC_HI_3[0], sizeof(mmMC_VM_MARC_RELOC_HI_3)/sizeof(mmMC_VM_MARC_RELOC_HI_3[0]), 0, 0 }, + { "mmMC_VM_MARC_LEN_LO_0", REG_MMIO, 0x07ed, 0, &mmMC_VM_MARC_LEN_LO_0[0], sizeof(mmMC_VM_MARC_LEN_LO_0)/sizeof(mmMC_VM_MARC_LEN_LO_0[0]), 0, 0 }, + { "mmMC_VM_MARC_LEN_LO_1", REG_MMIO, 0x07ee, 0, &mmMC_VM_MARC_LEN_LO_1[0], sizeof(mmMC_VM_MARC_LEN_LO_1)/sizeof(mmMC_VM_MARC_LEN_LO_1[0]), 0, 0 }, + { "mmMC_VM_MARC_LEN_LO_2", REG_MMIO, 0x07ef, 0, &mmMC_VM_MARC_LEN_LO_2[0], sizeof(mmMC_VM_MARC_LEN_LO_2)/sizeof(mmMC_VM_MARC_LEN_LO_2[0]), 0, 0 }, + { "mmMC_VM_MARC_LEN_LO_3", REG_MMIO, 0x07f0, 0, &mmMC_VM_MARC_LEN_LO_3[0], sizeof(mmMC_VM_MARC_LEN_LO_3)/sizeof(mmMC_VM_MARC_LEN_LO_3[0]), 0, 0 }, + { "mmMC_VM_MARC_LEN_HI_0", REG_MMIO, 0x07f1, 0, &mmMC_VM_MARC_LEN_HI_0[0], sizeof(mmMC_VM_MARC_LEN_HI_0)/sizeof(mmMC_VM_MARC_LEN_HI_0[0]), 0, 0 }, + { "mmMC_VM_MARC_LEN_HI_1", REG_MMIO, 0x07f2, 0, &mmMC_VM_MARC_LEN_HI_1[0], sizeof(mmMC_VM_MARC_LEN_HI_1)/sizeof(mmMC_VM_MARC_LEN_HI_1[0]), 0, 0 }, + { "mmMC_VM_MARC_LEN_HI_2", REG_MMIO, 0x07f3, 0, &mmMC_VM_MARC_LEN_HI_2[0], sizeof(mmMC_VM_MARC_LEN_HI_2)/sizeof(mmMC_VM_MARC_LEN_HI_2[0]), 0, 0 }, + { "mmMC_VM_MARC_LEN_HI_3", REG_MMIO, 0x07f4, 0, &mmMC_VM_MARC_LEN_HI_3[0], sizeof(mmMC_VM_MARC_LEN_HI_3)/sizeof(mmMC_VM_MARC_LEN_HI_3[0]), 0, 0 }, + { "mmVM_IOMMU_CONTROL_REGISTER", REG_MMIO, 0x07f5, 0, &mmVM_IOMMU_CONTROL_REGISTER[0], sizeof(mmVM_IOMMU_CONTROL_REGISTER)/sizeof(mmVM_IOMMU_CONTROL_REGISTER[0]), 0, 0 }, + { "mmVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER", REG_MMIO, 0x07f6, 0, &mmVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER[0], sizeof(mmVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER)/sizeof(mmVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER[0]), 0, 0 }, + { "mmVM_PCIE_ATS_CNTL", REG_MMIO, 0x07f7, 0, &mmVM_PCIE_ATS_CNTL[0], sizeof(mmVM_PCIE_ATS_CNTL)/sizeof(mmVM_PCIE_ATS_CNTL[0]), 0, 0 }, + { "mmVM_PCIE_ATS_CNTL_VF_0", REG_MMIO, 0x07f8, 0, &mmVM_PCIE_ATS_CNTL_VF_0[0], sizeof(mmVM_PCIE_ATS_CNTL_VF_0)/sizeof(mmVM_PCIE_ATS_CNTL_VF_0[0]), 0, 0 }, + { "mmVM_PCIE_ATS_CNTL_VF_1", REG_MMIO, 0x07f9, 0, &mmVM_PCIE_ATS_CNTL_VF_1[0], sizeof(mmVM_PCIE_ATS_CNTL_VF_1)/sizeof(mmVM_PCIE_ATS_CNTL_VF_1[0]), 0, 0 }, + { "mmVM_PCIE_ATS_CNTL_VF_2", REG_MMIO, 0x07fa, 0, &mmVM_PCIE_ATS_CNTL_VF_2[0], sizeof(mmVM_PCIE_ATS_CNTL_VF_2)/sizeof(mmVM_PCIE_ATS_CNTL_VF_2[0]), 0, 0 }, + { "mmVM_PCIE_ATS_CNTL_VF_3", REG_MMIO, 0x07fb, 0, &mmVM_PCIE_ATS_CNTL_VF_3[0], sizeof(mmVM_PCIE_ATS_CNTL_VF_3)/sizeof(mmVM_PCIE_ATS_CNTL_VF_3[0]), 0, 0 }, + { "mmVM_PCIE_ATS_CNTL_VF_4", REG_MMIO, 0x07fc, 0, &mmVM_PCIE_ATS_CNTL_VF_4[0], sizeof(mmVM_PCIE_ATS_CNTL_VF_4)/sizeof(mmVM_PCIE_ATS_CNTL_VF_4[0]), 0, 0 }, + { "mmVM_PCIE_ATS_CNTL_VF_5", REG_MMIO, 0x07fd, 0, &mmVM_PCIE_ATS_CNTL_VF_5[0], sizeof(mmVM_PCIE_ATS_CNTL_VF_5)/sizeof(mmVM_PCIE_ATS_CNTL_VF_5[0]), 0, 0 }, + { "mmVM_PCIE_ATS_CNTL_VF_6", REG_MMIO, 0x07fe, 0, &mmVM_PCIE_ATS_CNTL_VF_6[0], sizeof(mmVM_PCIE_ATS_CNTL_VF_6)/sizeof(mmVM_PCIE_ATS_CNTL_VF_6[0]), 0, 0 }, + { "mmVM_PCIE_ATS_CNTL_VF_7", REG_MMIO, 0x07ff, 0, &mmVM_PCIE_ATS_CNTL_VF_7[0], sizeof(mmVM_PCIE_ATS_CNTL_VF_7)/sizeof(mmVM_PCIE_ATS_CNTL_VF_7[0]), 0, 0 }, + { "mmVM_PCIE_ATS_CNTL_VF_8", REG_MMIO, 0x0800, 0, &mmVM_PCIE_ATS_CNTL_VF_8[0], sizeof(mmVM_PCIE_ATS_CNTL_VF_8)/sizeof(mmVM_PCIE_ATS_CNTL_VF_8[0]), 0, 0 }, + { "mmVM_PCIE_ATS_CNTL_VF_9", REG_MMIO, 0x0801, 0, &mmVM_PCIE_ATS_CNTL_VF_9[0], sizeof(mmVM_PCIE_ATS_CNTL_VF_9)/sizeof(mmVM_PCIE_ATS_CNTL_VF_9[0]), 0, 0 }, + { "mmVM_PCIE_ATS_CNTL_VF_10", REG_MMIO, 0x0802, 0, &mmVM_PCIE_ATS_CNTL_VF_10[0], sizeof(mmVM_PCIE_ATS_CNTL_VF_10)/sizeof(mmVM_PCIE_ATS_CNTL_VF_10[0]), 0, 0 }, + { "mmVM_PCIE_ATS_CNTL_VF_11", REG_MMIO, 0x0803, 0, &mmVM_PCIE_ATS_CNTL_VF_11[0], sizeof(mmVM_PCIE_ATS_CNTL_VF_11)/sizeof(mmVM_PCIE_ATS_CNTL_VF_11[0]), 0, 0 }, + { "mmVM_PCIE_ATS_CNTL_VF_12", REG_MMIO, 0x0804, 0, &mmVM_PCIE_ATS_CNTL_VF_12[0], sizeof(mmVM_PCIE_ATS_CNTL_VF_12)/sizeof(mmVM_PCIE_ATS_CNTL_VF_12[0]), 0, 0 }, + { "mmVM_PCIE_ATS_CNTL_VF_13", REG_MMIO, 0x0805, 0, &mmVM_PCIE_ATS_CNTL_VF_13[0], sizeof(mmVM_PCIE_ATS_CNTL_VF_13)/sizeof(mmVM_PCIE_ATS_CNTL_VF_13[0]), 0, 0 }, + { "mmVM_PCIE_ATS_CNTL_VF_14", REG_MMIO, 0x0806, 0, &mmVM_PCIE_ATS_CNTL_VF_14[0], sizeof(mmVM_PCIE_ATS_CNTL_VF_14)/sizeof(mmVM_PCIE_ATS_CNTL_VF_14[0]), 0, 0 }, + { "mmVM_PCIE_ATS_CNTL_VF_15", REG_MMIO, 0x0807, 0, &mmVM_PCIE_ATS_CNTL_VF_15[0], sizeof(mmVM_PCIE_ATS_CNTL_VF_15)/sizeof(mmVM_PCIE_ATS_CNTL_VF_15[0]), 0, 0 }, + { "mmUTCL2_CGTT_CLK_CTRL", REG_MMIO, 0x0808, 0, &mmUTCL2_CGTT_CLK_CTRL[0], sizeof(mmUTCL2_CGTT_CLK_CTRL)/sizeof(mmUTCL2_CGTT_CLK_CTRL[0]), 0, 0 }, + { "mmMC_VM_NB_MMIOBASE", REG_MMIO, 0x0810, 0, &mmMC_VM_NB_MMIOBASE[0], sizeof(mmMC_VM_NB_MMIOBASE)/sizeof(mmMC_VM_NB_MMIOBASE[0]), 0, 0 }, + { "mmMC_VM_NB_MMIOLIMIT", REG_MMIO, 0x0811, 0, &mmMC_VM_NB_MMIOLIMIT[0], sizeof(mmMC_VM_NB_MMIOLIMIT)/sizeof(mmMC_VM_NB_MMIOLIMIT[0]), 0, 0 }, + { "mmMC_VM_NB_PCI_CTRL", REG_MMIO, 0x0812, 0, &mmMC_VM_NB_PCI_CTRL[0], sizeof(mmMC_VM_NB_PCI_CTRL)/sizeof(mmMC_VM_NB_PCI_CTRL[0]), 0, 0 }, + { "mmMC_VM_NB_PCI_ARB", REG_MMIO, 0x0813, 0, &mmMC_VM_NB_PCI_ARB[0], sizeof(mmMC_VM_NB_PCI_ARB)/sizeof(mmMC_VM_NB_PCI_ARB[0]), 0, 0 }, + { "mmMC_VM_NB_TOP_OF_DRAM_SLOT1", REG_MMIO, 0x0814, 0, &mmMC_VM_NB_TOP_OF_DRAM_SLOT1[0], sizeof(mmMC_VM_NB_TOP_OF_DRAM_SLOT1)/sizeof(mmMC_VM_NB_TOP_OF_DRAM_SLOT1[0]), 0, 0 }, + { "mmMC_VM_NB_LOWER_TOP_OF_DRAM2", REG_MMIO, 0x0815, 0, &mmMC_VM_NB_LOWER_TOP_OF_DRAM2[0], sizeof(mmMC_VM_NB_LOWER_TOP_OF_DRAM2)/sizeof(mmMC_VM_NB_LOWER_TOP_OF_DRAM2[0]), 0, 0 }, + { "mmMC_VM_NB_UPPER_TOP_OF_DRAM2", REG_MMIO, 0x0816, 0, &mmMC_VM_NB_UPPER_TOP_OF_DRAM2[0], sizeof(mmMC_VM_NB_UPPER_TOP_OF_DRAM2)/sizeof(mmMC_VM_NB_UPPER_TOP_OF_DRAM2[0]), 0, 0 }, + { "mmMC_VM_FB_OFFSET", REG_MMIO, 0x0817, 0, &mmMC_VM_FB_OFFSET[0], sizeof(mmMC_VM_FB_OFFSET)/sizeof(mmMC_VM_FB_OFFSET[0]), 0, 0 }, + { "mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB", REG_MMIO, 0x0818, 0, &mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB[0], sizeof(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB)/sizeof(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB[0]), 0, 0 }, + { "mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB", REG_MMIO, 0x0819, 0, &mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB[0], sizeof(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB)/sizeof(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB[0]), 0, 0 }, + { "mmMC_VM_STEERING", REG_MMIO, 0x081a, 0, &mmMC_VM_STEERING[0], sizeof(mmMC_VM_STEERING)/sizeof(mmMC_VM_STEERING[0]), 0, 0 }, + { "mmMC_SHARED_VIRT_RESET_REQ", REG_MMIO, 0x081b, 0, &mmMC_SHARED_VIRT_RESET_REQ[0], sizeof(mmMC_SHARED_VIRT_RESET_REQ)/sizeof(mmMC_SHARED_VIRT_RESET_REQ[0]), 0, 0 }, + { "mmMC_MEM_POWER_LS", REG_MMIO, 0x081c, 0, &mmMC_MEM_POWER_LS[0], sizeof(mmMC_MEM_POWER_LS)/sizeof(mmMC_MEM_POWER_LS[0]), 0, 0 }, + { "mmMC_VM_CACHEABLE_DRAM_ADDRESS_START", REG_MMIO, 0x081d, 0, &mmMC_VM_CACHEABLE_DRAM_ADDRESS_START[0], sizeof(mmMC_VM_CACHEABLE_DRAM_ADDRESS_START)/sizeof(mmMC_VM_CACHEABLE_DRAM_ADDRESS_START[0]), 0, 0 }, + { "mmMC_VM_CACHEABLE_DRAM_ADDRESS_END", REG_MMIO, 0x081e, 0, &mmMC_VM_CACHEABLE_DRAM_ADDRESS_END[0], sizeof(mmMC_VM_CACHEABLE_DRAM_ADDRESS_END)/sizeof(mmMC_VM_CACHEABLE_DRAM_ADDRESS_END[0]), 0, 0 }, + { "mmMC_VM_APT_CNTL", REG_MMIO, 0x081f, 0, &mmMC_VM_APT_CNTL[0], sizeof(mmMC_VM_APT_CNTL)/sizeof(mmMC_VM_APT_CNTL[0]), 0, 0 }, + { "mmMC_VM_LOCAL_HBM_ADDRESS_START", REG_MMIO, 0x0820, 0, &mmMC_VM_LOCAL_HBM_ADDRESS_START[0], sizeof(mmMC_VM_LOCAL_HBM_ADDRESS_START)/sizeof(mmMC_VM_LOCAL_HBM_ADDRESS_START[0]), 0, 0 }, + { "mmMC_VM_LOCAL_HBM_ADDRESS_END", REG_MMIO, 0x0821, 0, &mmMC_VM_LOCAL_HBM_ADDRESS_END[0], sizeof(mmMC_VM_LOCAL_HBM_ADDRESS_END)/sizeof(mmMC_VM_LOCAL_HBM_ADDRESS_END[0]), 0, 0 }, + { "mmMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL", REG_MMIO, 0x0822, 0, &mmMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL[0], sizeof(mmMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL)/sizeof(mmMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL[0]), 0, 0 }, + { "mmMC_VM_FB_LOCATION_BASE", REG_MMIO, 0x082c, 0, &mmMC_VM_FB_LOCATION_BASE[0], sizeof(mmMC_VM_FB_LOCATION_BASE)/sizeof(mmMC_VM_FB_LOCATION_BASE[0]), 0, 0 }, + { "mmMC_VM_FB_LOCATION_TOP", REG_MMIO, 0x082d, 0, &mmMC_VM_FB_LOCATION_TOP[0], sizeof(mmMC_VM_FB_LOCATION_TOP)/sizeof(mmMC_VM_FB_LOCATION_TOP[0]), 0, 0 }, + { "mmMC_VM_AGP_TOP", REG_MMIO, 0x082e, 0, &mmMC_VM_AGP_TOP[0], sizeof(mmMC_VM_AGP_TOP)/sizeof(mmMC_VM_AGP_TOP[0]), 0, 0 }, + { "mmMC_VM_AGP_BOT", REG_MMIO, 0x082f, 0, &mmMC_VM_AGP_BOT[0], sizeof(mmMC_VM_AGP_BOT)/sizeof(mmMC_VM_AGP_BOT[0]), 0, 0 }, + { "mmMC_VM_AGP_BASE", REG_MMIO, 0x0830, 0, &mmMC_VM_AGP_BASE[0], sizeof(mmMC_VM_AGP_BASE)/sizeof(mmMC_VM_AGP_BASE[0]), 0, 0 }, + { "mmMC_VM_SYSTEM_APERTURE_LOW_ADDR", REG_MMIO, 0x0831, 0, &mmMC_VM_SYSTEM_APERTURE_LOW_ADDR[0], sizeof(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR)/sizeof(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR[0]), 0, 0 }, + { "mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR", REG_MMIO, 0x0832, 0, &mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR[0], sizeof(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR)/sizeof(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR[0]), 0, 0 }, + { "mmMC_VM_MX_L1_TLB_CNTL", REG_MMIO, 0x0833, 0, &mmMC_VM_MX_L1_TLB_CNTL[0], sizeof(mmMC_VM_MX_L1_TLB_CNTL)/sizeof(mmMC_VM_MX_L1_TLB_CNTL[0]), 0, 0 }, + { "mmATC_L2_PERFCOUNTER_LO", REG_MMIO, 0x0840, 0, &mmATC_L2_PERFCOUNTER_LO[0], sizeof(mmATC_L2_PERFCOUNTER_LO)/sizeof(mmATC_L2_PERFCOUNTER_LO[0]), 0, 0 }, + { "mmATC_L2_PERFCOUNTER_HI", REG_MMIO, 0x0841, 0, &mmATC_L2_PERFCOUNTER_HI[0], sizeof(mmATC_L2_PERFCOUNTER_HI)/sizeof(mmATC_L2_PERFCOUNTER_HI[0]), 0, 0 }, + { "mmATC_L2_PERFCOUNTER0_CFG", REG_MMIO, 0x0848, 0, &mmATC_L2_PERFCOUNTER0_CFG[0], sizeof(mmATC_L2_PERFCOUNTER0_CFG)/sizeof(mmATC_L2_PERFCOUNTER0_CFG[0]), 0, 0 }, + { "mmATC_L2_PERFCOUNTER1_CFG", REG_MMIO, 0x0849, 0, &mmATC_L2_PERFCOUNTER1_CFG[0], sizeof(mmATC_L2_PERFCOUNTER1_CFG)/sizeof(mmATC_L2_PERFCOUNTER1_CFG[0]), 0, 0 }, + { "mmATC_L2_PERFCOUNTER_RSLT_CNTL", REG_MMIO, 0x084a, 0, &mmATC_L2_PERFCOUNTER_RSLT_CNTL[0], sizeof(mmATC_L2_PERFCOUNTER_RSLT_CNTL)/sizeof(mmATC_L2_PERFCOUNTER_RSLT_CNTL[0]), 0, 0 }, diff --git a/src/lib/ip/mp100.c b/src/lib/ip/mp100.c new file mode 100644 index 0000000..575511a --- /dev/null +++ b/src/lib/ip/mp100.c @@ -0,0 +1,68 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Tom St Denis <tom.stdenis@amd.com> + * + */ +#include "umr.h" + +#include "mp100_bits.i" + +static const struct umr_reg_soc15 mp100_registers[] = { +#include "mp100_regs.i" +}; + +static int grant(struct umr_asic *asic) +{ + (void)asic; + return 0; +} + +static int deny(struct umr_asic *asic) +{ + (void)asic; + return -1; +} + +struct umr_ip_block *umr_create_mp100(struct umr_ip_offsets_soc15 *soc15_offsets, struct umr_options *options) +{ + struct umr_ip_block *ip; + + ip = calloc(1, sizeof *ip); + if (!ip) + return NULL; + + ip->ipname = "mp100"; + ip->no_regs = sizeof(mp100_registers)/sizeof(mp100_registers[0]); + ip->regs = calloc(ip->no_regs, sizeof(ip->regs[0])); + if (!ip->regs) { + free(ip); + return NULL; + } + ip->grant = (options->risky >= 1) ? grant : deny; + + if (umr_transfer_soc15_to_reg(options, soc15_offsets, "MP0", mp100_registers, ip)) { // this might be broken because there is MP1/2 as well + free(ip); + return NULL; + } + + return ip; +} diff --git a/src/lib/ip/mp100_bits.i b/src/lib/ip/mp100_bits.i new file mode 100644 index 0000000..0333037 --- /dev/null +++ b/src/lib/ip/mp100_bits.i @@ -0,0 +1,459 @@ +static struct umr_bitfield mmMP0_SMN_C2PMSG_32[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_33[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_34[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_35[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_36[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_37[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_38[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_39[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_40[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_41[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_42[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_43[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_44[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_45[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_46[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_47[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_48[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_49[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_50[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_51[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_52[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_53[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_54[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_55[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_56[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_57[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_58[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_59[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_60[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_61[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_62[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_63[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_64[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_65[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_66[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_67[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_68[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_69[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_70[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_71[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_72[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_73[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_74[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_75[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_76[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_77[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_78[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_79[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_80[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_81[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_82[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_83[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_84[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_85[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_86[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_87[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_88[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_89[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_90[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_91[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_92[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_93[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_94[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_95[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_96[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_97[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_98[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_99[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_100[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_101[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_102[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_C2PMSG_103[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_IH_CREDIT[] = { + { "CREDIT_VALUE", 0, 1, &umr_bitfield_default }, + { "CLIENT_ID", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_IH_SW_INT[] = { + { "VALID", 0, 0, &umr_bitfield_default }, + { "ID", 1, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP0_SMN_IH_SW_INT_CTRL[] = { + { "SW_TRIG_MASK", 0, 0, &umr_bitfield_default }, + { "SW_INT_ACK", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_32[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_33[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_34[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_35[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_36[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_37[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_38[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_39[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_40[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_41[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_42[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_43[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_44[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_45[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_46[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_47[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_48[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_49[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_50[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_51[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_52[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_53[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_54[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_55[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_56[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_57[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_58[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_59[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_60[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_61[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_62[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_63[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_64[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_65[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_66[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_67[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_68[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_69[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_70[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_71[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_72[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_73[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_74[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_75[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_76[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_77[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_78[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_79[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_80[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_81[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_82[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_83[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_84[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_85[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_86[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_87[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_88[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_89[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_90[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_91[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_92[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_93[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_94[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_95[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_96[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_97[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_98[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_99[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_100[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_101[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_102[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_C2PMSG_103[] = { + { "CONTENT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_IH_CREDIT[] = { + { "CREDIT_VALUE", 0, 1, &umr_bitfield_default }, + { "CLIENT_ID", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_IH_SW_INT[] = { + { "VALID", 0, 0, &umr_bitfield_default }, + { "ID", 1, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_IH_SW_INT_CTRL[] = { + { "SW_TRIG_MASK", 0, 0, &umr_bitfield_default }, + { "SW_INT_ACK", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMP1_SMN_FPS_CNT[] = { + { "COUNT", 0, 31, &umr_bitfield_default }, +}; diff --git a/src/lib/ip/mp100_regs.i b/src/lib/ip/mp100_regs.i new file mode 100644 index 0000000..b3c0732 --- /dev/null +++ b/src/lib/ip/mp100_regs.i @@ -0,0 +1,151 @@ + { "mmMP0_SMN_C2PMSG_32", REG_MMIO, 0x0060, 0, &mmMP0_SMN_C2PMSG_32[0], sizeof(mmMP0_SMN_C2PMSG_32)/sizeof(mmMP0_SMN_C2PMSG_32[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_33", REG_MMIO, 0x0061, 0, &mmMP0_SMN_C2PMSG_33[0], sizeof(mmMP0_SMN_C2PMSG_33)/sizeof(mmMP0_SMN_C2PMSG_33[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_34", REG_MMIO, 0x0062, 0, &mmMP0_SMN_C2PMSG_34[0], sizeof(mmMP0_SMN_C2PMSG_34)/sizeof(mmMP0_SMN_C2PMSG_34[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_35", REG_MMIO, 0x0063, 0, &mmMP0_SMN_C2PMSG_35[0], sizeof(mmMP0_SMN_C2PMSG_35)/sizeof(mmMP0_SMN_C2PMSG_35[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_36", REG_MMIO, 0x0064, 0, &mmMP0_SMN_C2PMSG_36[0], sizeof(mmMP0_SMN_C2PMSG_36)/sizeof(mmMP0_SMN_C2PMSG_36[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_37", REG_MMIO, 0x0065, 0, &mmMP0_SMN_C2PMSG_37[0], sizeof(mmMP0_SMN_C2PMSG_37)/sizeof(mmMP0_SMN_C2PMSG_37[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_38", REG_MMIO, 0x0066, 0, &mmMP0_SMN_C2PMSG_38[0], sizeof(mmMP0_SMN_C2PMSG_38)/sizeof(mmMP0_SMN_C2PMSG_38[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_39", REG_MMIO, 0x0067, 0, &mmMP0_SMN_C2PMSG_39[0], sizeof(mmMP0_SMN_C2PMSG_39)/sizeof(mmMP0_SMN_C2PMSG_39[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_40", REG_MMIO, 0x0068, 0, &mmMP0_SMN_C2PMSG_40[0], sizeof(mmMP0_SMN_C2PMSG_40)/sizeof(mmMP0_SMN_C2PMSG_40[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_41", REG_MMIO, 0x0069, 0, &mmMP0_SMN_C2PMSG_41[0], sizeof(mmMP0_SMN_C2PMSG_41)/sizeof(mmMP0_SMN_C2PMSG_41[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_42", REG_MMIO, 0x006a, 0, &mmMP0_SMN_C2PMSG_42[0], sizeof(mmMP0_SMN_C2PMSG_42)/sizeof(mmMP0_SMN_C2PMSG_42[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_43", REG_MMIO, 0x006b, 0, &mmMP0_SMN_C2PMSG_43[0], sizeof(mmMP0_SMN_C2PMSG_43)/sizeof(mmMP0_SMN_C2PMSG_43[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_44", REG_MMIO, 0x006c, 0, &mmMP0_SMN_C2PMSG_44[0], sizeof(mmMP0_SMN_C2PMSG_44)/sizeof(mmMP0_SMN_C2PMSG_44[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_45", REG_MMIO, 0x006d, 0, &mmMP0_SMN_C2PMSG_45[0], sizeof(mmMP0_SMN_C2PMSG_45)/sizeof(mmMP0_SMN_C2PMSG_45[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_46", REG_MMIO, 0x006e, 0, &mmMP0_SMN_C2PMSG_46[0], sizeof(mmMP0_SMN_C2PMSG_46)/sizeof(mmMP0_SMN_C2PMSG_46[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_47", REG_MMIO, 0x006f, 0, &mmMP0_SMN_C2PMSG_47[0], sizeof(mmMP0_SMN_C2PMSG_47)/sizeof(mmMP0_SMN_C2PMSG_47[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_48", REG_MMIO, 0x0070, 0, &mmMP0_SMN_C2PMSG_48[0], sizeof(mmMP0_SMN_C2PMSG_48)/sizeof(mmMP0_SMN_C2PMSG_48[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_49", REG_MMIO, 0x0071, 0, &mmMP0_SMN_C2PMSG_49[0], sizeof(mmMP0_SMN_C2PMSG_49)/sizeof(mmMP0_SMN_C2PMSG_49[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_50", REG_MMIO, 0x0072, 0, &mmMP0_SMN_C2PMSG_50[0], sizeof(mmMP0_SMN_C2PMSG_50)/sizeof(mmMP0_SMN_C2PMSG_50[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_51", REG_MMIO, 0x0073, 0, &mmMP0_SMN_C2PMSG_51[0], sizeof(mmMP0_SMN_C2PMSG_51)/sizeof(mmMP0_SMN_C2PMSG_51[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_52", REG_MMIO, 0x0074, 0, &mmMP0_SMN_C2PMSG_52[0], sizeof(mmMP0_SMN_C2PMSG_52)/sizeof(mmMP0_SMN_C2PMSG_52[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_53", REG_MMIO, 0x0075, 0, &mmMP0_SMN_C2PMSG_53[0], sizeof(mmMP0_SMN_C2PMSG_53)/sizeof(mmMP0_SMN_C2PMSG_53[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_54", REG_MMIO, 0x0076, 0, &mmMP0_SMN_C2PMSG_54[0], sizeof(mmMP0_SMN_C2PMSG_54)/sizeof(mmMP0_SMN_C2PMSG_54[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_55", REG_MMIO, 0x0077, 0, &mmMP0_SMN_C2PMSG_55[0], sizeof(mmMP0_SMN_C2PMSG_55)/sizeof(mmMP0_SMN_C2PMSG_55[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_56", REG_MMIO, 0x0078, 0, &mmMP0_SMN_C2PMSG_56[0], sizeof(mmMP0_SMN_C2PMSG_56)/sizeof(mmMP0_SMN_C2PMSG_56[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_57", REG_MMIO, 0x0079, 0, &mmMP0_SMN_C2PMSG_57[0], sizeof(mmMP0_SMN_C2PMSG_57)/sizeof(mmMP0_SMN_C2PMSG_57[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_58", REG_MMIO, 0x007a, 0, &mmMP0_SMN_C2PMSG_58[0], sizeof(mmMP0_SMN_C2PMSG_58)/sizeof(mmMP0_SMN_C2PMSG_58[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_59", REG_MMIO, 0x007b, 0, &mmMP0_SMN_C2PMSG_59[0], sizeof(mmMP0_SMN_C2PMSG_59)/sizeof(mmMP0_SMN_C2PMSG_59[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_60", REG_MMIO, 0x007c, 0, &mmMP0_SMN_C2PMSG_60[0], sizeof(mmMP0_SMN_C2PMSG_60)/sizeof(mmMP0_SMN_C2PMSG_60[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_61", REG_MMIO, 0x007d, 0, &mmMP0_SMN_C2PMSG_61[0], sizeof(mmMP0_SMN_C2PMSG_61)/sizeof(mmMP0_SMN_C2PMSG_61[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_62", REG_MMIO, 0x007e, 0, &mmMP0_SMN_C2PMSG_62[0], sizeof(mmMP0_SMN_C2PMSG_62)/sizeof(mmMP0_SMN_C2PMSG_62[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_63", REG_MMIO, 0x007f, 0, &mmMP0_SMN_C2PMSG_63[0], sizeof(mmMP0_SMN_C2PMSG_63)/sizeof(mmMP0_SMN_C2PMSG_63[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_64", REG_MMIO, 0x0080, 0, &mmMP0_SMN_C2PMSG_64[0], sizeof(mmMP0_SMN_C2PMSG_64)/sizeof(mmMP0_SMN_C2PMSG_64[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_65", REG_MMIO, 0x0081, 0, &mmMP0_SMN_C2PMSG_65[0], sizeof(mmMP0_SMN_C2PMSG_65)/sizeof(mmMP0_SMN_C2PMSG_65[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_66", REG_MMIO, 0x0082, 0, &mmMP0_SMN_C2PMSG_66[0], sizeof(mmMP0_SMN_C2PMSG_66)/sizeof(mmMP0_SMN_C2PMSG_66[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_67", REG_MMIO, 0x0083, 0, &mmMP0_SMN_C2PMSG_67[0], sizeof(mmMP0_SMN_C2PMSG_67)/sizeof(mmMP0_SMN_C2PMSG_67[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_68", REG_MMIO, 0x0084, 0, &mmMP0_SMN_C2PMSG_68[0], sizeof(mmMP0_SMN_C2PMSG_68)/sizeof(mmMP0_SMN_C2PMSG_68[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_69", REG_MMIO, 0x0085, 0, &mmMP0_SMN_C2PMSG_69[0], sizeof(mmMP0_SMN_C2PMSG_69)/sizeof(mmMP0_SMN_C2PMSG_69[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_70", REG_MMIO, 0x0086, 0, &mmMP0_SMN_C2PMSG_70[0], sizeof(mmMP0_SMN_C2PMSG_70)/sizeof(mmMP0_SMN_C2PMSG_70[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_71", REG_MMIO, 0x0087, 0, &mmMP0_SMN_C2PMSG_71[0], sizeof(mmMP0_SMN_C2PMSG_71)/sizeof(mmMP0_SMN_C2PMSG_71[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_72", REG_MMIO, 0x0088, 0, &mmMP0_SMN_C2PMSG_72[0], sizeof(mmMP0_SMN_C2PMSG_72)/sizeof(mmMP0_SMN_C2PMSG_72[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_73", REG_MMIO, 0x0089, 0, &mmMP0_SMN_C2PMSG_73[0], sizeof(mmMP0_SMN_C2PMSG_73)/sizeof(mmMP0_SMN_C2PMSG_73[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_74", REG_MMIO, 0x008a, 0, &mmMP0_SMN_C2PMSG_74[0], sizeof(mmMP0_SMN_C2PMSG_74)/sizeof(mmMP0_SMN_C2PMSG_74[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_75", REG_MMIO, 0x008b, 0, &mmMP0_SMN_C2PMSG_75[0], sizeof(mmMP0_SMN_C2PMSG_75)/sizeof(mmMP0_SMN_C2PMSG_75[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_76", REG_MMIO, 0x008c, 0, &mmMP0_SMN_C2PMSG_76[0], sizeof(mmMP0_SMN_C2PMSG_76)/sizeof(mmMP0_SMN_C2PMSG_76[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_77", REG_MMIO, 0x008d, 0, &mmMP0_SMN_C2PMSG_77[0], sizeof(mmMP0_SMN_C2PMSG_77)/sizeof(mmMP0_SMN_C2PMSG_77[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_78", REG_MMIO, 0x008e, 0, &mmMP0_SMN_C2PMSG_78[0], sizeof(mmMP0_SMN_C2PMSG_78)/sizeof(mmMP0_SMN_C2PMSG_78[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_79", REG_MMIO, 0x008f, 0, &mmMP0_SMN_C2PMSG_79[0], sizeof(mmMP0_SMN_C2PMSG_79)/sizeof(mmMP0_SMN_C2PMSG_79[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_80", REG_MMIO, 0x0090, 0, &mmMP0_SMN_C2PMSG_80[0], sizeof(mmMP0_SMN_C2PMSG_80)/sizeof(mmMP0_SMN_C2PMSG_80[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_81", REG_MMIO, 0x0091, 0, &mmMP0_SMN_C2PMSG_81[0], sizeof(mmMP0_SMN_C2PMSG_81)/sizeof(mmMP0_SMN_C2PMSG_81[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_82", REG_MMIO, 0x0092, 0, &mmMP0_SMN_C2PMSG_82[0], sizeof(mmMP0_SMN_C2PMSG_82)/sizeof(mmMP0_SMN_C2PMSG_82[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_83", REG_MMIO, 0x0093, 0, &mmMP0_SMN_C2PMSG_83[0], sizeof(mmMP0_SMN_C2PMSG_83)/sizeof(mmMP0_SMN_C2PMSG_83[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_84", REG_MMIO, 0x0094, 0, &mmMP0_SMN_C2PMSG_84[0], sizeof(mmMP0_SMN_C2PMSG_84)/sizeof(mmMP0_SMN_C2PMSG_84[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_85", REG_MMIO, 0x0095, 0, &mmMP0_SMN_C2PMSG_85[0], sizeof(mmMP0_SMN_C2PMSG_85)/sizeof(mmMP0_SMN_C2PMSG_85[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_86", REG_MMIO, 0x0096, 0, &mmMP0_SMN_C2PMSG_86[0], sizeof(mmMP0_SMN_C2PMSG_86)/sizeof(mmMP0_SMN_C2PMSG_86[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_87", REG_MMIO, 0x0097, 0, &mmMP0_SMN_C2PMSG_87[0], sizeof(mmMP0_SMN_C2PMSG_87)/sizeof(mmMP0_SMN_C2PMSG_87[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_88", REG_MMIO, 0x0098, 0, &mmMP0_SMN_C2PMSG_88[0], sizeof(mmMP0_SMN_C2PMSG_88)/sizeof(mmMP0_SMN_C2PMSG_88[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_89", REG_MMIO, 0x0099, 0, &mmMP0_SMN_C2PMSG_89[0], sizeof(mmMP0_SMN_C2PMSG_89)/sizeof(mmMP0_SMN_C2PMSG_89[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_90", REG_MMIO, 0x009a, 0, &mmMP0_SMN_C2PMSG_90[0], sizeof(mmMP0_SMN_C2PMSG_90)/sizeof(mmMP0_SMN_C2PMSG_90[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_91", REG_MMIO, 0x009b, 0, &mmMP0_SMN_C2PMSG_91[0], sizeof(mmMP0_SMN_C2PMSG_91)/sizeof(mmMP0_SMN_C2PMSG_91[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_92", REG_MMIO, 0x009c, 0, &mmMP0_SMN_C2PMSG_92[0], sizeof(mmMP0_SMN_C2PMSG_92)/sizeof(mmMP0_SMN_C2PMSG_92[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_93", REG_MMIO, 0x009d, 0, &mmMP0_SMN_C2PMSG_93[0], sizeof(mmMP0_SMN_C2PMSG_93)/sizeof(mmMP0_SMN_C2PMSG_93[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_94", REG_MMIO, 0x009e, 0, &mmMP0_SMN_C2PMSG_94[0], sizeof(mmMP0_SMN_C2PMSG_94)/sizeof(mmMP0_SMN_C2PMSG_94[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_95", REG_MMIO, 0x009f, 0, &mmMP0_SMN_C2PMSG_95[0], sizeof(mmMP0_SMN_C2PMSG_95)/sizeof(mmMP0_SMN_C2PMSG_95[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_96", REG_MMIO, 0x00a0, 0, &mmMP0_SMN_C2PMSG_96[0], sizeof(mmMP0_SMN_C2PMSG_96)/sizeof(mmMP0_SMN_C2PMSG_96[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_97", REG_MMIO, 0x00a1, 0, &mmMP0_SMN_C2PMSG_97[0], sizeof(mmMP0_SMN_C2PMSG_97)/sizeof(mmMP0_SMN_C2PMSG_97[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_98", REG_MMIO, 0x00a2, 0, &mmMP0_SMN_C2PMSG_98[0], sizeof(mmMP0_SMN_C2PMSG_98)/sizeof(mmMP0_SMN_C2PMSG_98[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_99", REG_MMIO, 0x00a3, 0, &mmMP0_SMN_C2PMSG_99[0], sizeof(mmMP0_SMN_C2PMSG_99)/sizeof(mmMP0_SMN_C2PMSG_99[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_100", REG_MMIO, 0x00a4, 0, &mmMP0_SMN_C2PMSG_100[0], sizeof(mmMP0_SMN_C2PMSG_100)/sizeof(mmMP0_SMN_C2PMSG_100[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_101", REG_MMIO, 0x00a5, 0, &mmMP0_SMN_C2PMSG_101[0], sizeof(mmMP0_SMN_C2PMSG_101)/sizeof(mmMP0_SMN_C2PMSG_101[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_102", REG_MMIO, 0x00a6, 0, &mmMP0_SMN_C2PMSG_102[0], sizeof(mmMP0_SMN_C2PMSG_102)/sizeof(mmMP0_SMN_C2PMSG_102[0]), 0, 0 }, + { "mmMP0_SMN_C2PMSG_103", REG_MMIO, 0x00a7, 0, &mmMP0_SMN_C2PMSG_103[0], sizeof(mmMP0_SMN_C2PMSG_103)/sizeof(mmMP0_SMN_C2PMSG_103[0]), 0, 0 }, + { "mmMP0_SMN_IH_CREDIT", REG_MMIO, 0x00c1, 0, &mmMP0_SMN_IH_CREDIT[0], sizeof(mmMP0_SMN_IH_CREDIT)/sizeof(mmMP0_SMN_IH_CREDIT[0]), 0, 0 }, + { "mmMP0_SMN_IH_SW_INT", REG_MMIO, 0x00c2, 0, &mmMP0_SMN_IH_SW_INT[0], sizeof(mmMP0_SMN_IH_SW_INT)/sizeof(mmMP0_SMN_IH_SW_INT[0]), 0, 0 }, + { "mmMP0_SMN_IH_SW_INT_CTRL", REG_MMIO, 0x00c3, 0, &mmMP0_SMN_IH_SW_INT_CTRL[0], sizeof(mmMP0_SMN_IH_SW_INT_CTRL)/sizeof(mmMP0_SMN_IH_SW_INT_CTRL[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_32", REG_MMIO, 0x0260, 0, &mmMP1_SMN_C2PMSG_32[0], sizeof(mmMP1_SMN_C2PMSG_32)/sizeof(mmMP1_SMN_C2PMSG_32[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_33", REG_MMIO, 0x0261, 0, &mmMP1_SMN_C2PMSG_33[0], sizeof(mmMP1_SMN_C2PMSG_33)/sizeof(mmMP1_SMN_C2PMSG_33[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_34", REG_MMIO, 0x0262, 0, &mmMP1_SMN_C2PMSG_34[0], sizeof(mmMP1_SMN_C2PMSG_34)/sizeof(mmMP1_SMN_C2PMSG_34[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_35", REG_MMIO, 0x0263, 0, &mmMP1_SMN_C2PMSG_35[0], sizeof(mmMP1_SMN_C2PMSG_35)/sizeof(mmMP1_SMN_C2PMSG_35[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_36", REG_MMIO, 0x0264, 0, &mmMP1_SMN_C2PMSG_36[0], sizeof(mmMP1_SMN_C2PMSG_36)/sizeof(mmMP1_SMN_C2PMSG_36[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_37", REG_MMIO, 0x0265, 0, &mmMP1_SMN_C2PMSG_37[0], sizeof(mmMP1_SMN_C2PMSG_37)/sizeof(mmMP1_SMN_C2PMSG_37[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_38", REG_MMIO, 0x0266, 0, &mmMP1_SMN_C2PMSG_38[0], sizeof(mmMP1_SMN_C2PMSG_38)/sizeof(mmMP1_SMN_C2PMSG_38[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_39", REG_MMIO, 0x0267, 0, &mmMP1_SMN_C2PMSG_39[0], sizeof(mmMP1_SMN_C2PMSG_39)/sizeof(mmMP1_SMN_C2PMSG_39[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_40", REG_MMIO, 0x0268, 0, &mmMP1_SMN_C2PMSG_40[0], sizeof(mmMP1_SMN_C2PMSG_40)/sizeof(mmMP1_SMN_C2PMSG_40[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_41", REG_MMIO, 0x0269, 0, &mmMP1_SMN_C2PMSG_41[0], sizeof(mmMP1_SMN_C2PMSG_41)/sizeof(mmMP1_SMN_C2PMSG_41[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_42", REG_MMIO, 0x026a, 0, &mmMP1_SMN_C2PMSG_42[0], sizeof(mmMP1_SMN_C2PMSG_42)/sizeof(mmMP1_SMN_C2PMSG_42[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_43", REG_MMIO, 0x026b, 0, &mmMP1_SMN_C2PMSG_43[0], sizeof(mmMP1_SMN_C2PMSG_43)/sizeof(mmMP1_SMN_C2PMSG_43[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_44", REG_MMIO, 0x026c, 0, &mmMP1_SMN_C2PMSG_44[0], sizeof(mmMP1_SMN_C2PMSG_44)/sizeof(mmMP1_SMN_C2PMSG_44[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_45", REG_MMIO, 0x026d, 0, &mmMP1_SMN_C2PMSG_45[0], sizeof(mmMP1_SMN_C2PMSG_45)/sizeof(mmMP1_SMN_C2PMSG_45[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_46", REG_MMIO, 0x026e, 0, &mmMP1_SMN_C2PMSG_46[0], sizeof(mmMP1_SMN_C2PMSG_46)/sizeof(mmMP1_SMN_C2PMSG_46[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_47", REG_MMIO, 0x026f, 0, &mmMP1_SMN_C2PMSG_47[0], sizeof(mmMP1_SMN_C2PMSG_47)/sizeof(mmMP1_SMN_C2PMSG_47[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_48", REG_MMIO, 0x0270, 0, &mmMP1_SMN_C2PMSG_48[0], sizeof(mmMP1_SMN_C2PMSG_48)/sizeof(mmMP1_SMN_C2PMSG_48[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_49", REG_MMIO, 0x0271, 0, &mmMP1_SMN_C2PMSG_49[0], sizeof(mmMP1_SMN_C2PMSG_49)/sizeof(mmMP1_SMN_C2PMSG_49[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_50", REG_MMIO, 0x0272, 0, &mmMP1_SMN_C2PMSG_50[0], sizeof(mmMP1_SMN_C2PMSG_50)/sizeof(mmMP1_SMN_C2PMSG_50[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_51", REG_MMIO, 0x0273, 0, &mmMP1_SMN_C2PMSG_51[0], sizeof(mmMP1_SMN_C2PMSG_51)/sizeof(mmMP1_SMN_C2PMSG_51[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_52", REG_MMIO, 0x0274, 0, &mmMP1_SMN_C2PMSG_52[0], sizeof(mmMP1_SMN_C2PMSG_52)/sizeof(mmMP1_SMN_C2PMSG_52[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_53", REG_MMIO, 0x0275, 0, &mmMP1_SMN_C2PMSG_53[0], sizeof(mmMP1_SMN_C2PMSG_53)/sizeof(mmMP1_SMN_C2PMSG_53[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_54", REG_MMIO, 0x0276, 0, &mmMP1_SMN_C2PMSG_54[0], sizeof(mmMP1_SMN_C2PMSG_54)/sizeof(mmMP1_SMN_C2PMSG_54[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_55", REG_MMIO, 0x0277, 0, &mmMP1_SMN_C2PMSG_55[0], sizeof(mmMP1_SMN_C2PMSG_55)/sizeof(mmMP1_SMN_C2PMSG_55[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_56", REG_MMIO, 0x0278, 0, &mmMP1_SMN_C2PMSG_56[0], sizeof(mmMP1_SMN_C2PMSG_56)/sizeof(mmMP1_SMN_C2PMSG_56[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_57", REG_MMIO, 0x0279, 0, &mmMP1_SMN_C2PMSG_57[0], sizeof(mmMP1_SMN_C2PMSG_57)/sizeof(mmMP1_SMN_C2PMSG_57[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_58", REG_MMIO, 0x027a, 0, &mmMP1_SMN_C2PMSG_58[0], sizeof(mmMP1_SMN_C2PMSG_58)/sizeof(mmMP1_SMN_C2PMSG_58[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_59", REG_MMIO, 0x027b, 0, &mmMP1_SMN_C2PMSG_59[0], sizeof(mmMP1_SMN_C2PMSG_59)/sizeof(mmMP1_SMN_C2PMSG_59[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_60", REG_MMIO, 0x027c, 0, &mmMP1_SMN_C2PMSG_60[0], sizeof(mmMP1_SMN_C2PMSG_60)/sizeof(mmMP1_SMN_C2PMSG_60[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_61", REG_MMIO, 0x027d, 0, &mmMP1_SMN_C2PMSG_61[0], sizeof(mmMP1_SMN_C2PMSG_61)/sizeof(mmMP1_SMN_C2PMSG_61[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_62", REG_MMIO, 0x027e, 0, &mmMP1_SMN_C2PMSG_62[0], sizeof(mmMP1_SMN_C2PMSG_62)/sizeof(mmMP1_SMN_C2PMSG_62[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_63", REG_MMIO, 0x027f, 0, &mmMP1_SMN_C2PMSG_63[0], sizeof(mmMP1_SMN_C2PMSG_63)/sizeof(mmMP1_SMN_C2PMSG_63[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_64", REG_MMIO, 0x0280, 0, &mmMP1_SMN_C2PMSG_64[0], sizeof(mmMP1_SMN_C2PMSG_64)/sizeof(mmMP1_SMN_C2PMSG_64[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_65", REG_MMIO, 0x0281, 0, &mmMP1_SMN_C2PMSG_65[0], sizeof(mmMP1_SMN_C2PMSG_65)/sizeof(mmMP1_SMN_C2PMSG_65[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_66", REG_MMIO, 0x0282, 0, &mmMP1_SMN_C2PMSG_66[0], sizeof(mmMP1_SMN_C2PMSG_66)/sizeof(mmMP1_SMN_C2PMSG_66[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_67", REG_MMIO, 0x0283, 0, &mmMP1_SMN_C2PMSG_67[0], sizeof(mmMP1_SMN_C2PMSG_67)/sizeof(mmMP1_SMN_C2PMSG_67[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_68", REG_MMIO, 0x0284, 0, &mmMP1_SMN_C2PMSG_68[0], sizeof(mmMP1_SMN_C2PMSG_68)/sizeof(mmMP1_SMN_C2PMSG_68[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_69", REG_MMIO, 0x0285, 0, &mmMP1_SMN_C2PMSG_69[0], sizeof(mmMP1_SMN_C2PMSG_69)/sizeof(mmMP1_SMN_C2PMSG_69[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_70", REG_MMIO, 0x0286, 0, &mmMP1_SMN_C2PMSG_70[0], sizeof(mmMP1_SMN_C2PMSG_70)/sizeof(mmMP1_SMN_C2PMSG_70[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_71", REG_MMIO, 0x0287, 0, &mmMP1_SMN_C2PMSG_71[0], sizeof(mmMP1_SMN_C2PMSG_71)/sizeof(mmMP1_SMN_C2PMSG_71[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_72", REG_MMIO, 0x0288, 0, &mmMP1_SMN_C2PMSG_72[0], sizeof(mmMP1_SMN_C2PMSG_72)/sizeof(mmMP1_SMN_C2PMSG_72[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_73", REG_MMIO, 0x0289, 0, &mmMP1_SMN_C2PMSG_73[0], sizeof(mmMP1_SMN_C2PMSG_73)/sizeof(mmMP1_SMN_C2PMSG_73[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_74", REG_MMIO, 0x028a, 0, &mmMP1_SMN_C2PMSG_74[0], sizeof(mmMP1_SMN_C2PMSG_74)/sizeof(mmMP1_SMN_C2PMSG_74[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_75", REG_MMIO, 0x028b, 0, &mmMP1_SMN_C2PMSG_75[0], sizeof(mmMP1_SMN_C2PMSG_75)/sizeof(mmMP1_SMN_C2PMSG_75[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_76", REG_MMIO, 0x028c, 0, &mmMP1_SMN_C2PMSG_76[0], sizeof(mmMP1_SMN_C2PMSG_76)/sizeof(mmMP1_SMN_C2PMSG_76[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_77", REG_MMIO, 0x028d, 0, &mmMP1_SMN_C2PMSG_77[0], sizeof(mmMP1_SMN_C2PMSG_77)/sizeof(mmMP1_SMN_C2PMSG_77[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_78", REG_MMIO, 0x028e, 0, &mmMP1_SMN_C2PMSG_78[0], sizeof(mmMP1_SMN_C2PMSG_78)/sizeof(mmMP1_SMN_C2PMSG_78[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_79", REG_MMIO, 0x028f, 0, &mmMP1_SMN_C2PMSG_79[0], sizeof(mmMP1_SMN_C2PMSG_79)/sizeof(mmMP1_SMN_C2PMSG_79[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_80", REG_MMIO, 0x0290, 0, &mmMP1_SMN_C2PMSG_80[0], sizeof(mmMP1_SMN_C2PMSG_80)/sizeof(mmMP1_SMN_C2PMSG_80[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_81", REG_MMIO, 0x0291, 0, &mmMP1_SMN_C2PMSG_81[0], sizeof(mmMP1_SMN_C2PMSG_81)/sizeof(mmMP1_SMN_C2PMSG_81[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_82", REG_MMIO, 0x0292, 0, &mmMP1_SMN_C2PMSG_82[0], sizeof(mmMP1_SMN_C2PMSG_82)/sizeof(mmMP1_SMN_C2PMSG_82[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_83", REG_MMIO, 0x0293, 0, &mmMP1_SMN_C2PMSG_83[0], sizeof(mmMP1_SMN_C2PMSG_83)/sizeof(mmMP1_SMN_C2PMSG_83[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_84", REG_MMIO, 0x0294, 0, &mmMP1_SMN_C2PMSG_84[0], sizeof(mmMP1_SMN_C2PMSG_84)/sizeof(mmMP1_SMN_C2PMSG_84[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_85", REG_MMIO, 0x0295, 0, &mmMP1_SMN_C2PMSG_85[0], sizeof(mmMP1_SMN_C2PMSG_85)/sizeof(mmMP1_SMN_C2PMSG_85[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_86", REG_MMIO, 0x0296, 0, &mmMP1_SMN_C2PMSG_86[0], sizeof(mmMP1_SMN_C2PMSG_86)/sizeof(mmMP1_SMN_C2PMSG_86[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_87", REG_MMIO, 0x0297, 0, &mmMP1_SMN_C2PMSG_87[0], sizeof(mmMP1_SMN_C2PMSG_87)/sizeof(mmMP1_SMN_C2PMSG_87[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_88", REG_MMIO, 0x0298, 0, &mmMP1_SMN_C2PMSG_88[0], sizeof(mmMP1_SMN_C2PMSG_88)/sizeof(mmMP1_SMN_C2PMSG_88[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_89", REG_MMIO, 0x0299, 0, &mmMP1_SMN_C2PMSG_89[0], sizeof(mmMP1_SMN_C2PMSG_89)/sizeof(mmMP1_SMN_C2PMSG_89[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_90", REG_MMIO, 0x029a, 0, &mmMP1_SMN_C2PMSG_90[0], sizeof(mmMP1_SMN_C2PMSG_90)/sizeof(mmMP1_SMN_C2PMSG_90[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_91", REG_MMIO, 0x029b, 0, &mmMP1_SMN_C2PMSG_91[0], sizeof(mmMP1_SMN_C2PMSG_91)/sizeof(mmMP1_SMN_C2PMSG_91[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_92", REG_MMIO, 0x029c, 0, &mmMP1_SMN_C2PMSG_92[0], sizeof(mmMP1_SMN_C2PMSG_92)/sizeof(mmMP1_SMN_C2PMSG_92[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_93", REG_MMIO, 0x029d, 0, &mmMP1_SMN_C2PMSG_93[0], sizeof(mmMP1_SMN_C2PMSG_93)/sizeof(mmMP1_SMN_C2PMSG_93[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_94", REG_MMIO, 0x029e, 0, &mmMP1_SMN_C2PMSG_94[0], sizeof(mmMP1_SMN_C2PMSG_94)/sizeof(mmMP1_SMN_C2PMSG_94[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_95", REG_MMIO, 0x029f, 0, &mmMP1_SMN_C2PMSG_95[0], sizeof(mmMP1_SMN_C2PMSG_95)/sizeof(mmMP1_SMN_C2PMSG_95[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_96", REG_MMIO, 0x02a0, 0, &mmMP1_SMN_C2PMSG_96[0], sizeof(mmMP1_SMN_C2PMSG_96)/sizeof(mmMP1_SMN_C2PMSG_96[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_97", REG_MMIO, 0x02a1, 0, &mmMP1_SMN_C2PMSG_97[0], sizeof(mmMP1_SMN_C2PMSG_97)/sizeof(mmMP1_SMN_C2PMSG_97[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_98", REG_MMIO, 0x02a2, 0, &mmMP1_SMN_C2PMSG_98[0], sizeof(mmMP1_SMN_C2PMSG_98)/sizeof(mmMP1_SMN_C2PMSG_98[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_99", REG_MMIO, 0x02a3, 0, &mmMP1_SMN_C2PMSG_99[0], sizeof(mmMP1_SMN_C2PMSG_99)/sizeof(mmMP1_SMN_C2PMSG_99[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_100", REG_MMIO, 0x02a4, 0, &mmMP1_SMN_C2PMSG_100[0], sizeof(mmMP1_SMN_C2PMSG_100)/sizeof(mmMP1_SMN_C2PMSG_100[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_101", REG_MMIO, 0x02a5, 0, &mmMP1_SMN_C2PMSG_101[0], sizeof(mmMP1_SMN_C2PMSG_101)/sizeof(mmMP1_SMN_C2PMSG_101[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_102", REG_MMIO, 0x02a6, 0, &mmMP1_SMN_C2PMSG_102[0], sizeof(mmMP1_SMN_C2PMSG_102)/sizeof(mmMP1_SMN_C2PMSG_102[0]), 0, 0 }, + { "mmMP1_SMN_C2PMSG_103", REG_MMIO, 0x02a7, 0, &mmMP1_SMN_C2PMSG_103[0], sizeof(mmMP1_SMN_C2PMSG_103)/sizeof(mmMP1_SMN_C2PMSG_103[0]), 0, 0 }, + { "mmMP1_SMN_IH_CREDIT", REG_MMIO, 0x02c1, 0, &mmMP1_SMN_IH_CREDIT[0], sizeof(mmMP1_SMN_IH_CREDIT)/sizeof(mmMP1_SMN_IH_CREDIT[0]), 0, 0 }, + { "mmMP1_SMN_IH_SW_INT", REG_MMIO, 0x02c2, 0, &mmMP1_SMN_IH_SW_INT[0], sizeof(mmMP1_SMN_IH_SW_INT)/sizeof(mmMP1_SMN_IH_SW_INT[0]), 0, 0 }, + { "mmMP1_SMN_IH_SW_INT_CTRL", REG_MMIO, 0x02c3, 0, &mmMP1_SMN_IH_SW_INT_CTRL[0], sizeof(mmMP1_SMN_IH_SW_INT_CTRL)/sizeof(mmMP1_SMN_IH_SW_INT_CTRL[0]), 0, 0 }, + { "mmMP1_SMN_FPS_CNT", REG_MMIO, 0x02c4, 0, &mmMP1_SMN_FPS_CNT[0], sizeof(mmMP1_SMN_FPS_CNT)/sizeof(mmMP1_SMN_FPS_CNT[0]), 0, 0 }, diff --git a/src/lib/ip/nbif61_bits.i b/src/lib/ip/nbif61_bits.i deleted file mode 100644 index bdb733a..0000000 --- a/src/lib/ip/nbif61_bits.i +++ /dev/null @@ -1,4904 +0,0 @@ -static struct umr_bitfield mmSUB_BUS_NUMBER_LATENCY[] = { - { "PRIMARY_BUS_", 0, 7, &umr_bitfield_default }, - { "SECONDARY_BUS_", 8, 15, &umr_bitfield_default }, - { "SUB_BUS_NUM_", 16, 23, &umr_bitfield_default }, - { "SECONDARY_LATENCY_TIMER_", 24, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmIO_BASE_LIMIT[] = { - { "IO_BASE_TYPE_", 0, 3, &umr_bitfield_default }, - { "IO_BASE_", 4, 7, &umr_bitfield_default }, - { "IO_LIMIT_TYPE_", 8, 11, &umr_bitfield_default }, - { "IO_LIMIT_", 12, 15, &umr_bitfield_default }, -}; -static struct umr_bitfield mmSECONDARY_STATUS[] = { - { "CAP_LIST_", 4, 4, &umr_bitfield_default }, - { "PCI_66_EN_", 5, 5, &umr_bitfield_default }, - { "FAST_BACK_CAPABLE_", 7, 7, &umr_bitfield_default }, - { "MASTER_DATA_PARITY_ERROR_", 8, 8, &umr_bitfield_default }, - { "DEVSEL_TIMING_", 9, 10, &umr_bitfield_default }, - { "SIGNAL_TARGET_ABORT_", 11, 11, &umr_bitfield_default }, - { "RECEIVED_TARGET_ABORT_", 12, 12, &umr_bitfield_default }, - { "RECEIVED_MASTER_ABORT_", 13, 13, &umr_bitfield_default }, - { "RECEIVED_SYSTEM_ERROR_", 14, 14, &umr_bitfield_default }, - { "PARITY_ERROR_DETECTED_", 15, 15, &umr_bitfield_default }, -}; -static struct umr_bitfield mmMEM_BASE_LIMIT[] = { - { "MEM_BASE_TYPE_", 0, 3, &umr_bitfield_default }, - { "MEM_BASE_31_20_", 4, 15, &umr_bitfield_default }, - { "MEM_LIMIT_TYPE_", 16, 19, &umr_bitfield_default }, - { "MEM_LIMIT_31_20_", 20, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmPREF_BASE_LIMIT[] = { - { "PREF_MEM_BASE_TYPE_", 0, 3, &umr_bitfield_default }, - { "PREF_MEM_BASE_31_20_", 4, 15, &umr_bitfield_default }, - { "PREF_MEM_LIMIT_TYPE_", 16, 19, &umr_bitfield_default }, - { "PREF_MEM_LIMIT_31_20_", 20, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmPREF_BASE_UPPER[] = { - { "PREF_BASE_UPPER_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmPREF_LIMIT_UPPER[] = { - { "PREF_LIMIT_UPPER_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmIO_BASE_LIMIT_HI[] = { - { "IO_BASE_31_16_", 0, 15, &umr_bitfield_default }, - { "IO_LIMIT_31_16_", 16, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmIRQ_BRIDGE_CNTL[] = { - { "PARITY_RESPONSE_EN_", 0, 0, &umr_bitfield_default }, - { "SERR_EN_", 1, 1, &umr_bitfield_default }, - { "ISA_EN_", 2, 2, &umr_bitfield_default }, - { "VGA_EN_", 3, 3, &umr_bitfield_default }, - { "VGA_DEC_", 4, 4, &umr_bitfield_default }, - { "MASTER_ABORT_MODE_", 5, 5, &umr_bitfield_default }, - { "SECONDARY_BUS_RESET_", 6, 6, &umr_bitfield_default }, - { "FAST_B2B_EN_", 7, 7, &umr_bitfield_default }, -}; -static struct umr_bitfield mmSLOT_CAP[] = { - { "ATTN_BUTTON_PRESENT_", 0, 0, &umr_bitfield_default }, - { "PWR_CONTROLLER_PRESENT_", 1, 1, &umr_bitfield_default }, - { "MRL_SENSOR_PRESENT_", 2, 2, &umr_bitfield_default }, - { "ATTN_INDICATOR_PRESENT_", 3, 3, &umr_bitfield_default }, - { "PWR_INDICATOR_PRESENT_", 4, 4, &umr_bitfield_default }, - { "HOTPLUG_SURPRISE_", 5, 5, &umr_bitfield_default }, - { "HOTPLUG_CAPABLE_", 6, 6, &umr_bitfield_default }, - { "SLOT_PWR_LIMIT_VALUE_", 7, 14, &umr_bitfield_default }, - { "SLOT_PWR_LIMIT_SCALE_", 15, 16, &umr_bitfield_default }, - { "ELECTROMECH_INTERLOCK_PRESENT_", 17, 17, &umr_bitfield_default }, - { "NO_COMMAND_COMPLETED_SUPPORTED_", 18, 18, &umr_bitfield_default }, - { "PHYSICAL_SLOT_NUM_", 19, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmSLOT_CNTL[] = { - { "ATTN_BUTTON_PRESSED_EN_", 0, 0, &umr_bitfield_default }, - { "PWR_FAULT_DETECTED_EN_", 1, 1, &umr_bitfield_default }, - { "MRL_SENSOR_CHANGED_EN_", 2, 2, &umr_bitfield_default }, - { "PRESENCE_DETECT_CHANGED_EN_", 3, 3, &umr_bitfield_default }, - { "COMMAND_COMPLETED_INTR_EN_", 4, 4, &umr_bitfield_default }, - { "HOTPLUG_INTR_EN_", 5, 5, &umr_bitfield_default }, - { "ATTN_INDICATOR_CNTL_", 6, 7, &umr_bitfield_default }, - { "PWR_INDICATOR_CNTL_", 8, 9, &umr_bitfield_default }, - { "PWR_CONTROLLER_CNTL_", 10, 10, &umr_bitfield_default }, - { "ELECTROMECH_INTERLOCK_CNTL_", 11, 11, &umr_bitfield_default }, - { "DL_STATE_CHANGED_EN_", 12, 12, &umr_bitfield_default }, -}; -static struct umr_bitfield mmSLOT_STATUS[] = { - { "ATTN_BUTTON_PRESSED_", 0, 0, &umr_bitfield_default }, - { "PWR_FAULT_DETECTED_", 1, 1, &umr_bitfield_default }, - { "MRL_SENSOR_CHANGED_", 2, 2, &umr_bitfield_default }, - { "PRESENCE_DETECT_CHANGED_", 3, 3, &umr_bitfield_default }, - { "COMMAND_COMPLETED_", 4, 4, &umr_bitfield_default }, - { "MRL_SENSOR_STATE_", 5, 5, &umr_bitfield_default }, - { "PRESENCE_DETECT_STATE_", 6, 6, &umr_bitfield_default }, - { "ELECTROMECH_INTERLOCK_STATUS_", 7, 7, &umr_bitfield_default }, - { "DL_STATE_CHANGED_", 8, 8, &umr_bitfield_default }, -}; -static struct umr_bitfield mmSSID_CAP_LIST[] = { - { "CAP_ID_", 0, 7, &umr_bitfield_default }, - { "NEXT_PTR_", 8, 15, &umr_bitfield_default }, -}; -static struct umr_bitfield mmSSID_CAP[] = { - { "SUBSYSTEM_VENDOR_ID_", 0, 15, &umr_bitfield_default }, - { "SUBSYSTEM_ID_", 16, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSHADOW_COMMAND[] = { - { "IOEN_UP_", 0, 0, &umr_bitfield_default }, - { "MEMEN_UP_", 1, 1, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSHADOW_BASE_ADDR_1[] = { - { "BAR1_UP_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSHADOW_BASE_ADDR_2[] = { - { "BAR2_UP_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSHADOW_SUB_BUS_NUMBER_LATENCY[] = { - { "SECONDARY_BUS_UP_", 8, 15, &umr_bitfield_default }, - { "SUB_BUS_NUM_UP_", 16, 23, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSHADOW_IO_BASE_LIMIT[] = { - { "IO_BASE_UP_", 4, 7, &umr_bitfield_default }, - { "IO_LIMIT_UP_", 12, 15, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSHADOW_MEM_BASE_LIMIT[] = { - { "MEM_BASE_TYPE_", 0, 3, &umr_bitfield_default }, - { "MEM_BASE_31_20_UP_", 4, 15, &umr_bitfield_default }, - { "MEM_LIMIT_TYPE_", 16, 19, &umr_bitfield_default }, - { "MEM_LIMIT_31_20_UP_", 20, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSHADOW_PREF_BASE_LIMIT[] = { - { "PREF_MEM_BASE_TYPE_", 0, 3, &umr_bitfield_default }, - { "PREF_MEM_BASE_31_20_UP_", 4, 15, &umr_bitfield_default }, - { "PREF_MEM_LIMIT_TYPE_", 16, 19, &umr_bitfield_default }, - { "PREF_MEM_LIMIT_31_20_UP_", 20, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSHADOW_PREF_BASE_UPPER[] = { - { "PREF_BASE_UPPER_UP_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSHADOW_PREF_LIMIT_UPPER[] = { - { "PREF_LIMIT_UPPER_UP_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSHADOW_IO_BASE_LIMIT_HI[] = { - { "IO_BASE_31_16_UP_", 0, 15, &umr_bitfield_default }, - { "IO_LIMIT_31_16_UP_", 16, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSHADOW_IRQ_BRIDGE_CNTL[] = { - { "ISA_EN_UP_", 2, 2, &umr_bitfield_default }, - { "VGA_EN_UP_", 3, 3, &umr_bitfield_default }, - { "VGA_DEC_UP_", 4, 4, &umr_bitfield_default }, - { "SECONDARY_BUS_RESET_UP_", 6, 6, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSUC_INDEX[] = { - { "SUC_INDEX_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSUC_DATA[] = { - { "SUC_DATA_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSUM_INDEX[] = { - { "SUM_INDEX_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSUM_DATA[] = { - { "SUM_DATA_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmA2S_CNTL_CL0[] = { - { "NSNOOP_MAP_", 0, 1, &umr_bitfield_default }, - { "REQPASSPW_VC0_MAP_", 2, 3, &umr_bitfield_default }, - { "REQPASSPW_NVC0_MAP_", 4, 5, &umr_bitfield_default }, - { "REQRSPPASSPW_VC0_MAP_", 6, 7, &umr_bitfield_default }, - { "REQRSPPASSPW_NVC0_MAP_", 8, 9, &umr_bitfield_default }, - { "BLKLVL_MAP_", 10, 11, &umr_bitfield_default }, - { "DATERR_MAP_", 12, 13, &umr_bitfield_default }, - { "EXOKAY_WR_MAP_", 14, 15, &umr_bitfield_default }, - { "EXOKAY_RD_MAP_", 16, 17, &umr_bitfield_default }, - { "RESP_WR_MAP_", 18, 19, &umr_bitfield_default }, - { "RESP_RD_MAP_", 20, 21, &umr_bitfield_default }, -}; -static struct umr_bitfield mmA2S_CNTL_CL1[] = { - { "NSNOOP_MAP_", 0, 1, &umr_bitfield_default }, - { "REQPASSPW_VC0_MAP_", 2, 3, &umr_bitfield_default }, - { "REQPASSPW_NVC0_MAP_", 4, 5, &umr_bitfield_default }, - { "REQRSPPASSPW_VC0_MAP_", 6, 7, &umr_bitfield_default }, - { "REQRSPPASSPW_NVC0_MAP_", 8, 9, &umr_bitfield_default }, - { "BLKLVL_MAP_", 10, 11, &umr_bitfield_default }, - { "DATERR_MAP_", 12, 13, &umr_bitfield_default }, - { "EXOKAY_WR_MAP_", 14, 15, &umr_bitfield_default }, - { "EXOKAY_RD_MAP_", 16, 17, &umr_bitfield_default }, - { "RESP_WR_MAP_", 18, 19, &umr_bitfield_default }, - { "RESP_RD_MAP_", 20, 21, &umr_bitfield_default }, -}; -static struct umr_bitfield mmA2S_CNTL_CL2[] = { - { "NSNOOP_MAP_", 0, 1, &umr_bitfield_default }, - { "REQPASSPW_VC0_MAP_", 2, 3, &umr_bitfield_default }, - { "REQPASSPW_NVC0_MAP_", 4, 5, &umr_bitfield_default }, - { "REQRSPPASSPW_VC0_MAP_", 6, 7, &umr_bitfield_default }, - { "REQRSPPASSPW_NVC0_MAP_", 8, 9, &umr_bitfield_default }, - { "BLKLVL_MAP_", 10, 11, &umr_bitfield_default }, - { "DATERR_MAP_", 12, 13, &umr_bitfield_default }, - { "EXOKAY_WR_MAP_", 14, 15, &umr_bitfield_default }, - { "EXOKAY_RD_MAP_", 16, 17, &umr_bitfield_default }, - { "RESP_WR_MAP_", 18, 19, &umr_bitfield_default }, - { "RESP_RD_MAP_", 20, 21, &umr_bitfield_default }, -}; -static struct umr_bitfield mmA2S_CNTL_CL3[] = { - { "NSNOOP_MAP_", 0, 1, &umr_bitfield_default }, - { "REQPASSPW_VC0_MAP_", 2, 3, &umr_bitfield_default }, - { "REQPASSPW_NVC0_MAP_", 4, 5, &umr_bitfield_default }, - { "REQRSPPASSPW_VC0_MAP_", 6, 7, &umr_bitfield_default }, - { "REQRSPPASSPW_NVC0_MAP_", 8, 9, &umr_bitfield_default }, - { "BLKLVL_MAP_", 10, 11, &umr_bitfield_default }, - { "DATERR_MAP_", 12, 13, &umr_bitfield_default }, - { "EXOKAY_WR_MAP_", 14, 15, &umr_bitfield_default }, - { "EXOKAY_RD_MAP_", 16, 17, &umr_bitfield_default }, - { "RESP_WR_MAP_", 18, 19, &umr_bitfield_default }, - { "RESP_RD_MAP_", 20, 21, &umr_bitfield_default }, -}; -static struct umr_bitfield mmA2S_CNTL_CL4[] = { - { "NSNOOP_MAP_", 0, 1, &umr_bitfield_default }, - { "REQPASSPW_VC0_MAP_", 2, 3, &umr_bitfield_default }, - { "REQPASSPW_NVC0_MAP_", 4, 5, &umr_bitfield_default }, - { "REQRSPPASSPW_VC0_MAP_", 6, 7, &umr_bitfield_default }, - { "REQRSPPASSPW_NVC0_MAP_", 8, 9, &umr_bitfield_default }, - { "BLKLVL_MAP_", 10, 11, &umr_bitfield_default }, - { "DATERR_MAP_", 12, 13, &umr_bitfield_default }, - { "EXOKAY_WR_MAP_", 14, 15, &umr_bitfield_default }, - { "EXOKAY_RD_MAP_", 16, 17, &umr_bitfield_default }, - { "RESP_WR_MAP_", 18, 19, &umr_bitfield_default }, - { "RESP_RD_MAP_", 20, 21, &umr_bitfield_default }, -}; -static struct umr_bitfield mmA2S_CNTL_SW0[] = { - { "WR_TAG_SET_MIN_", 0, 2, &umr_bitfield_default }, - { "RD_TAG_SET_MIN_", 3, 5, &umr_bitfield_default }, - { "FORCE_RSP_REORDER_EN_", 6, 6, &umr_bitfield_default }, - { "RSP_REORDER_DIS_", 7, 7, &umr_bitfield_default }, - { "WRRSP_ACCUM_SEL_", 8, 8, &umr_bitfield_default }, - { "SDP_WR_CHAIN_DIS_", 9, 9, &umr_bitfield_default }, - { "WRRSP_TAGFIFO_CONT_RD_DIS_", 10, 10, &umr_bitfield_default }, - { "RDRSP_TAGFIFO_CONT_RD_DIS_", 11, 11, &umr_bitfield_default }, - { "RDRSP_STS_DATSTS_PRIORITY_", 12, 12, &umr_bitfield_default }, - { "WRR_RD_WEIGHT_", 16, 23, &umr_bitfield_default }, - { "WRR_WR_WEIGHT_", 24, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmA2S_CNTL_SW1[] = { - { "WR_TAG_SET_MIN_", 0, 2, &umr_bitfield_default }, - { "RD_TAG_SET_MIN_", 3, 5, &umr_bitfield_default }, - { "FORCE_RSP_REORDER_EN_", 6, 6, &umr_bitfield_default }, - { "RSP_REORDER_DIS_", 7, 7, &umr_bitfield_default }, - { "WRRSP_ACCUM_SEL_", 8, 8, &umr_bitfield_default }, - { "SDP_WR_CHAIN_DIS_", 9, 9, &umr_bitfield_default }, - { "WRRSP_TAGFIFO_CONT_RD_DIS_", 10, 10, &umr_bitfield_default }, - { "RDRSP_TAGFIFO_CONT_RD_DIS_", 11, 11, &umr_bitfield_default }, - { "RDRSP_STS_DATSTS_PRIORITY_", 12, 12, &umr_bitfield_default }, - { "WRR_RD_WEIGHT_", 16, 23, &umr_bitfield_default }, - { "WRR_WR_WEIGHT_", 24, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmA2S_CNTL_SW2[] = { - { "WR_TAG_SET_MIN_", 0, 2, &umr_bitfield_default }, - { "RD_TAG_SET_MIN_", 3, 5, &umr_bitfield_default }, - { "FORCE_RSP_REORDER_EN_", 6, 6, &umr_bitfield_default }, - { "RSP_REORDER_DIS_", 7, 7, &umr_bitfield_default }, - { "WRRSP_ACCUM_SEL_", 8, 8, &umr_bitfield_default }, - { "SDP_WR_CHAIN_DIS_", 9, 9, &umr_bitfield_default }, - { "WRRSP_TAGFIFO_CONT_RD_DIS_", 10, 10, &umr_bitfield_default }, - { "RDRSP_TAGFIFO_CONT_RD_DIS_", 11, 11, &umr_bitfield_default }, - { "RDRSP_STS_DATSTS_PRIORITY_", 12, 12, &umr_bitfield_default }, - { "WRR_RD_WEIGHT_", 16, 23, &umr_bitfield_default }, - { "WRR_WR_WEIGHT_", 24, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmNGDC_MGCG_CTRL[] = { - { "NGDC_MGCG_EN_", 0, 0, &umr_bitfield_default }, - { "NGDC_MGCG_MODE_", 1, 1, &umr_bitfield_default }, - { "NGDC_MGCG_HYSTERESIS_", 2, 9, &umr_bitfield_default }, -}; -static struct umr_bitfield mmA2S_MISC_CNTL[] = { - { "BLKLVL_FOR_MSG_", 0, 1, &umr_bitfield_default }, - { "RESERVE_2_CRED_FOR_NPWR_REQ_DIS_", 2, 2, &umr_bitfield_default }, -}; -static struct umr_bitfield mmNGDC_SDP_PORT_CTRL[] = { - { "SDP_DISCON_HYSTERESIS_", 0, 5, &umr_bitfield_default }, -}; -static struct umr_bitfield mmNGDC_RESERVED_0[] = { - { "RESERVED_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmNGDC_RESERVED_1[] = { - { "RESERVED_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_SDMA0_DOORBELL_RANGE[] = { - { "OFFSET_", 2, 11, &umr_bitfield_default }, - { "SIZE_", 16, 20, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_SDMA1_DOORBELL_RANGE[] = { - { "OFFSET_", 2, 11, &umr_bitfield_default }, - { "SIZE_", 16, 20, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_IH_DOORBELL_RANGE[] = { - { "OFFSET_", 2, 11, &umr_bitfield_default }, - { "SIZE_", 16, 20, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_MMSCH0_DOORBELL_RANGE[] = { - { "OFFSET_", 2, 11, &umr_bitfield_default }, - { "SIZE_", 16, 20, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_DOORBELL_FENCE_CNTL[] = { - { "DOORBELL_FENCE_ENABLE_", 0, 0, &umr_bitfield_default }, -}; -static struct umr_bitfield mmS2A_MISC_CNTL[] = { - { "DOORBELL_64BIT_SUPPORT_SDMA0_DIS_", 0, 0, &umr_bitfield_default }, - { "DOORBELL_64BIT_SUPPORT_SDMA1_DIS_", 1, 1, &umr_bitfield_default }, - { "DOORBELL_64BIT_SUPPORT_CP_DIS_", 2, 2, &umr_bitfield_default }, -}; -static struct umr_bitfield mmA2S_CNTL2_SEC_CL0[] = { - { "SECLVL_MAP_", 0, 2, &umr_bitfield_default }, -}; -static struct umr_bitfield mmA2S_CNTL2_SEC_CL1[] = { - { "SECLVL_MAP_", 0, 2, &umr_bitfield_default }, -}; -static struct umr_bitfield mmA2S_CNTL2_SEC_CL2[] = { - { "SECLVL_MAP_", 0, 2, &umr_bitfield_default }, -}; -static struct umr_bitfield mmA2S_CNTL2_SEC_CL3[] = { - { "SECLVL_MAP_", 0, 2, &umr_bitfield_default }, -}; -static struct umr_bitfield mmA2S_CNTL2_SEC_CL4[] = { - { "SECLVL_MAP_", 0, 2, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL0_RdRsp_BurstTarget_REG0[] = { - { "RdRsp_BurstTarget_31_0_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL0_RdRsp_BurstTarget_REG1[] = { - { "RdRsp_BurstTarget_63_32_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL0_RdRsp_TimeSlot_REG0[] = { - { "RdRsp_TimeSlot_31_0_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL0_RdRsp_TimeSlot_REG1[] = { - { "RdRsp_TimeSlot_63_32_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL0_WrRsp_BurstTarget_REG0[] = { - { "WrRsp_BurstTarget_31_0_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL0_WrRsp_BurstTarget_REG1[] = { - { "WrRsp_BurstTarget_63_32_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL0_WrRsp_TimeSlot_REG0[] = { - { "WrRsp_TimeSlot_31_0_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL0_WrRsp_TimeSlot_REG1[] = { - { "WrRsp_TimeSlot_63_32_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL0_Req_BurstTarget_REG0[] = { - { "Req_BurstTarget_31_0_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL0_Req_BurstTarget_REG1[] = { - { "Req_BurstTarget_63_32_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL0_Req_TimeSlot_REG0[] = { - { "Req_TimeSlot_31_0_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL0_Req_TimeSlot_REG1[] = { - { "Req_TimeSlot_63_32_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL0_ReqPoolCredit_Alloc_REG0[] = { - { "ReqPoolCredit_Alloc_31_0_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL0_ReqPoolCredit_Alloc_REG1[] = { - { "ReqPoolCredit_Alloc_63_32_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL0_DataPoolCredit_Alloc_REG0[] = { - { "DataPoolCredit_Alloc_31_0_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL0_DataPoolCredit_Alloc_REG1[] = { - { "DataPoolCredit_Alloc_63_32_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL0_RdRspPoolCredit_Alloc_REG0[] = { - { "RdRspPoolCredit_Alloc_31_0_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL0_RdRspPoolCredit_Alloc_REG1[] = { - { "RdRspPoolCredit_Alloc_63_32_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL0_WrRspPoolCredit_Alloc_REG0[] = { - { "WrRspPoolCredit_Alloc_31_0_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL0_WrRspPoolCredit_Alloc_REG1[] = { - { "WrRspPoolCredit_Alloc_63_32_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL1_RdRsp_BurstTarget_REG0[] = { - { "RdRsp_BurstTarget_31_0_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL1_RdRsp_BurstTarget_REG1[] = { - { "RdRsp_BurstTarget_63_32_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL1_RdRsp_TimeSlot_REG0[] = { - { "RdRsp_TimeSlot_31_0_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL1_RdRsp_TimeSlot_REG1[] = { - { "RdRsp_TimeSlot_63_32_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL1_WrRsp_BurstTarget_REG0[] = { - { "WrRsp_BurstTarget_31_0_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL1_WrRsp_BurstTarget_REG1[] = { - { "WrRsp_BurstTarget_63_32_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL1_WrRsp_TimeSlot_REG0[] = { - { "WrRsp_TimeSlot_31_0_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL1_WrRsp_TimeSlot_REG1[] = { - { "WrRsp_TimeSlot_63_32_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL1_Req_BurstTarget_REG0[] = { - { "Req_BurstTarget_31_0_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL1_Req_BurstTarget_REG1[] = { - { "Req_BurstTarget_63_32_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL1_Req_TimeSlot_REG0[] = { - { "Req_TimeSlot_31_0_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL1_Req_TimeSlot_REG1[] = { - { "Req_TimeSlot_63_32_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL1_ReqPoolCredit_Alloc_REG0[] = { - { "ReqPoolCredit_Alloc_31_0_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL1_ReqPoolCredit_Alloc_REG1[] = { - { "ReqPoolCredit_Alloc_63_32_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL1_DataPoolCredit_Alloc_REG0[] = { - { "DataPoolCredit_Alloc_31_0_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL1_DataPoolCredit_Alloc_REG1[] = { - { "DataPoolCredit_Alloc_63_32_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL1_RdRspPoolCredit_Alloc_REG0[] = { - { "RdRspPoolCredit_Alloc_31_0_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL1_RdRspPoolCredit_Alloc_REG1[] = { - { "RdRspPoolCredit_Alloc_63_32_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL1_WrRspPoolCredit_Alloc_REG0[] = { - { "WrRspPoolCredit_Alloc_31_0_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL1_WrRspPoolCredit_Alloc_REG1[] = { - { "WrRspPoolCredit_Alloc_63_32_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL2_RdRsp_BurstTarget_REG0[] = { - { "RdRsp_BurstTarget_31_0_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL2_RdRsp_BurstTarget_REG1[] = { - { "RdRsp_BurstTarget_63_32_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL2_RdRsp_TimeSlot_REG0[] = { - { "RdRsp_TimeSlot_31_0_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL2_RdRsp_TimeSlot_REG1[] = { - { "RdRsp_TimeSlot_63_32_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL2_WrRsp_BurstTarget_REG0[] = { - { "WrRsp_BurstTarget_31_0_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL2_WrRsp_BurstTarget_REG1[] = { - { "WrRsp_BurstTarget_63_32_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL2_WrRsp_TimeSlot_REG0[] = { - { "WrRsp_TimeSlot_31_0_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL2_WrRsp_TimeSlot_REG1[] = { - { "WrRsp_TimeSlot_63_32_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL2_Req_BurstTarget_REG0[] = { - { "Req_BurstTarget_31_0_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL2_Req_BurstTarget_REG1[] = { - { "Req_BurstTarget_63_32_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL2_Req_TimeSlot_REG0[] = { - { "Req_TimeSlot_31_0_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL2_Req_TimeSlot_REG1[] = { - { "Req_TimeSlot_63_32_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL2_ReqPoolCredit_Alloc_REG0[] = { - { "ReqPoolCredit_Alloc_31_0_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL2_ReqPoolCredit_Alloc_REG1[] = { - { "ReqPoolCredit_Alloc_63_32_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL2_DataPoolCredit_Alloc_REG0[] = { - { "DataPoolCredit_Alloc_31_0_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL2_DataPoolCredit_Alloc_REG1[] = { - { "DataPoolCredit_Alloc_63_32_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL2_RdRspPoolCredit_Alloc_REG0[] = { - { "RdRspPoolCredit_Alloc_31_0_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL2_RdRspPoolCredit_Alloc_REG1[] = { - { "RdRspPoolCredit_Alloc_63_32_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL2_WrRspPoolCredit_Alloc_REG0[] = { - { "WrRspPoolCredit_Alloc_31_0_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL2_WrRspPoolCredit_Alloc_REG1[] = { - { "WrRspPoolCredit_Alloc_63_32_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL3_RdRsp_BurstTarget_REG0[] = { - { "RdRsp_BurstTarget_31_0_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL3_RdRsp_BurstTarget_REG1[] = { - { "RdRsp_BurstTarget_63_32_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL3_RdRsp_TimeSlot_REG0[] = { - { "RdRsp_TimeSlot_31_0_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL3_RdRsp_TimeSlot_REG1[] = { - { "RdRsp_TimeSlot_63_32_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL3_WrRsp_BurstTarget_REG0[] = { - { "WrRsp_BurstTarget_31_0_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL3_WrRsp_BurstTarget_REG1[] = { - { "WrRsp_BurstTarget_63_32_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL3_WrRsp_TimeSlot_REG0[] = { - { "WrRsp_TimeSlot_31_0_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL3_WrRsp_TimeSlot_REG1[] = { - { "WrRsp_TimeSlot_63_32_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL3_Req_BurstTarget_REG0[] = { - { "Req_BurstTarget_31_0_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL3_Req_BurstTarget_REG1[] = { - { "Req_BurstTarget_63_32_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL3_Req_TimeSlot_REG0[] = { - { "Req_TimeSlot_31_0_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL3_Req_TimeSlot_REG1[] = { - { "Req_TimeSlot_63_32_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL3_ReqPoolCredit_Alloc_REG0[] = { - { "ReqPoolCredit_Alloc_31_0_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL3_ReqPoolCredit_Alloc_REG1[] = { - { "ReqPoolCredit_Alloc_63_32_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL3_DataPoolCredit_Alloc_REG0[] = { - { "DataPoolCredit_Alloc_31_0_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL3_DataPoolCredit_Alloc_REG1[] = { - { "DataPoolCredit_Alloc_63_32_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL3_RdRspPoolCredit_Alloc_REG0[] = { - { "RdRspPoolCredit_Alloc_31_0_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL3_RdRspPoolCredit_Alloc_REG1[] = { - { "RdRspPoolCredit_Alloc_63_32_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL3_WrRspPoolCredit_Alloc_REG0[] = { - { "WrRspPoolCredit_Alloc_31_0_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL3_WrRspPoolCredit_Alloc_REG1[] = { - { "WrRspPoolCredit_Alloc_63_32_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL4_RdRsp_BurstTarget_REG0[] = { - { "RdRsp_BurstTarget_31_0_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL4_RdRsp_BurstTarget_REG1[] = { - { "RdRsp_BurstTarget_63_32_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL4_RdRsp_TimeSlot_REG0[] = { - { "RdRsp_TimeSlot_31_0_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL4_RdRsp_TimeSlot_REG1[] = { - { "RdRsp_TimeSlot_63_32_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL4_WrRsp_BurstTarget_REG0[] = { - { "WrRsp_BurstTarget_31_0_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL4_WrRsp_BurstTarget_REG1[] = { - { "WrRsp_BurstTarget_63_32_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL4_WrRsp_TimeSlot_REG0[] = { - { "WrRsp_TimeSlot_31_0_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL4_WrRsp_TimeSlot_REG1[] = { - { "WrRsp_TimeSlot_63_32_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL4_Req_BurstTarget_REG0[] = { - { "Req_BurstTarget_31_0_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL4_Req_BurstTarget_REG1[] = { - { "Req_BurstTarget_63_32_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL4_Req_TimeSlot_REG0[] = { - { "Req_TimeSlot_31_0_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL4_Req_TimeSlot_REG1[] = { - { "Req_TimeSlot_63_32_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL4_ReqPoolCredit_Alloc_REG0[] = { - { "ReqPoolCredit_Alloc_31_0_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL4_ReqPoolCredit_Alloc_REG1[] = { - { "ReqPoolCredit_Alloc_63_32_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL4_DataPoolCredit_Alloc_REG0[] = { - { "DataPoolCredit_Alloc_31_0_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL4_DataPoolCredit_Alloc_REG1[] = { - { "DataPoolCredit_Alloc_63_32_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL4_RdRspPoolCredit_Alloc_REG0[] = { - { "RdRspPoolCredit_Alloc_31_0_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL4_RdRspPoolCredit_Alloc_REG1[] = { - { "RdRspPoolCredit_Alloc_63_32_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL4_WrRspPoolCredit_Alloc_REG0[] = { - { "WrRspPoolCredit_Alloc_31_0_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL4_WrRspPoolCredit_Alloc_REG1[] = { - { "WrRspPoolCredit_Alloc_63_32_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL5_RdRsp_BurstTarget_REG0[] = { - { "RdRsp_BurstTarget_31_0_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL5_RdRsp_BurstTarget_REG1[] = { - { "RdRsp_BurstTarget_63_32_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL5_RdRsp_TimeSlot_REG0[] = { - { "RdRsp_TimeSlot_31_0_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL5_RdRsp_TimeSlot_REG1[] = { - { "RdRsp_TimeSlot_63_32_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL5_WrRsp_BurstTarget_REG0[] = { - { "WrRsp_BurstTarget_31_0_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL5_WrRsp_BurstTarget_REG1[] = { - { "WrRsp_BurstTarget_63_32_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL5_WrRsp_TimeSlot_REG0[] = { - { "WrRsp_TimeSlot_31_0_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL5_WrRsp_TimeSlot_REG1[] = { - { "WrRsp_TimeSlot_63_32_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL5_Req_BurstTarget_REG0[] = { - { "Req_BurstTarget_31_0_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL5_Req_BurstTarget_REG1[] = { - { "Req_BurstTarget_63_32_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL5_Req_TimeSlot_REG0[] = { - { "Req_TimeSlot_31_0_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL5_Req_TimeSlot_REG1[] = { - { "Req_TimeSlot_63_32_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL5_ReqPoolCredit_Alloc_REG0[] = { - { "ReqPoolCredit_Alloc_31_0_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL5_ReqPoolCredit_Alloc_REG1[] = { - { "ReqPoolCredit_Alloc_63_32_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL5_DataPoolCredit_Alloc_REG0[] = { - { "DataPoolCredit_Alloc_31_0_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL5_DataPoolCredit_Alloc_REG1[] = { - { "DataPoolCredit_Alloc_63_32_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL5_RdRspPoolCredit_Alloc_REG0[] = { - { "RdRspPoolCredit_Alloc_31_0_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL5_RdRspPoolCredit_Alloc_REG1[] = { - { "RdRspPoolCredit_Alloc_63_32_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL5_WrRspPoolCredit_Alloc_REG0[] = { - { "WrRspPoolCredit_Alloc_31_0_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CL5_WrRspPoolCredit_Alloc_REG1[] = { - { "WrRspPoolCredit_Alloc_63_32_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CNTL_REG0[] = { - { "NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0_", 0, 0, &umr_bitfield_default }, - { "NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1_", 1, 1, &umr_bitfield_default }, - { "NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2_", 2, 2, &umr_bitfield_default }, - { "NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3_", 3, 3, &umr_bitfield_default }, - { "NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4_", 4, 4, &umr_bitfield_default }, - { "NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5_", 5, 5, &umr_bitfield_default }, - { "NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6_", 6, 6, &umr_bitfield_default }, - { "NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7_", 7, 7, &umr_bitfield_default }, - { "NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8_", 8, 8, &umr_bitfield_default }, - { "NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9_", 9, 9, &umr_bitfield_default }, - { "NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK0_", 10, 10, &umr_bitfield_default }, - { "NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK1_", 11, 11, &umr_bitfield_default }, - { "NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK2_", 12, 12, &umr_bitfield_default }, - { "NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK3_", 13, 13, &umr_bitfield_default }, - { "NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK4_", 14, 14, &umr_bitfield_default }, - { "NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK5_", 15, 15, &umr_bitfield_default }, - { "NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK6_", 16, 16, &umr_bitfield_default }, - { "NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK7_", 17, 17, &umr_bitfield_default }, - { "NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK8_", 18, 18, &umr_bitfield_default }, - { "NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK9_", 19, 19, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSION_CNTL_REG1[] = { - { "LIVELOCK_WATCHDOG_THRESHOLD_", 0, 7, &umr_bitfield_default }, - { "CG_OFF_HYSTERESIS_", 8, 15, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSYSHUB_DS_CTRL_SOCCLK[] = { - { "HST_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_", 0, 0, &umr_bitfield_default }, - { "HST_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_", 1, 1, &umr_bitfield_default }, - { "HST_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_", 2, 2, &umr_bitfield_default }, - { "HST_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_", 3, 3, &umr_bitfield_default }, - { "HST_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_", 4, 4, &umr_bitfield_default }, - { "HST_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_", 5, 5, &umr_bitfield_default }, - { "HST_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_", 6, 6, &umr_bitfield_default }, - { "HST_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_", 7, 7, &umr_bitfield_default }, - { "DMA_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_", 16, 16, &umr_bitfield_default }, - { "DMA_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_", 17, 17, &umr_bitfield_default }, - { "DMA_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_", 18, 18, &umr_bitfield_default }, - { "DMA_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_", 19, 19, &umr_bitfield_default }, - { "DMA_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_", 20, 20, &umr_bitfield_default }, - { "DMA_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_", 21, 21, &umr_bitfield_default }, - { "DMA_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_", 22, 22, &umr_bitfield_default }, - { "DMA_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_", 23, 23, &umr_bitfield_default }, - { "SYSHUB_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_", 28, 28, &umr_bitfield_default }, - { "SYSHUB_SOCCLK_DS_EN_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSYSHUB_DS_CTRL2_SOCCLK[] = { - { "SYSHUB_SOCCLK_DS_TIMER_", 0, 15, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK[] = { - { "SYSHUB_bgen_socclk_HST_SW0_bypass_en_", 0, 0, &umr_bitfield_default }, - { "SYSHUB_bgen_socclk_HST_SW1_bypass_en_", 1, 1, &umr_bitfield_default }, - { "SYSHUB_bgen_socclk_DMA_SW0_bypass_en_", 15, 15, &umr_bitfield_default }, - { "SYSHUB_bgen_socclk_DMA_SW1_bypass_en_", 16, 16, &umr_bitfield_default }, - { "SYSHUB_bgen_socclk_DMA_SW2_bypass_en_", 17, 17, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK[] = { - { "SYSHUB_bgen_socclk_HST_SW0_imm_en_", 0, 0, &umr_bitfield_default }, - { "SYSHUB_bgen_socclk_HST_SW1_imm_en_", 1, 1, &umr_bitfield_default }, - { "SYSHUB_bgen_socclk_DMA_SW0_imm_en_", 15, 15, &umr_bitfield_default }, - { "SYSHUB_bgen_socclk_DMA_SW1_imm_en_", 16, 16, &umr_bitfield_default }, - { "SYSHUB_bgen_socclk_DMA_SW2_imm_en_", 17, 17, &umr_bitfield_default }, -}; -static struct umr_bitfield ixDMA_CLK0_SW0_SYSHUB_QOS_CNTL[] = { - { "QOS_CNTL_MODE_", 0, 0, &umr_bitfield_default }, - { "QOS_MAX_VALUE_", 1, 4, &umr_bitfield_default }, - { "QOS_MIN_VALUE_", 5, 8, &umr_bitfield_default }, -}; -static struct umr_bitfield ixDMA_CLK0_SW1_SYSHUB_QOS_CNTL[] = { - { "QOS_CNTL_MODE_", 0, 0, &umr_bitfield_default }, - { "QOS_MAX_VALUE_", 1, 4, &umr_bitfield_default }, - { "QOS_MIN_VALUE_", 5, 8, &umr_bitfield_default }, -}; -static struct umr_bitfield ixDMA_CLK0_SW0_CL0_CNTL[] = { - { "FLR_ON_RS_RESET_EN_", 0, 0, &umr_bitfield_default }, - { "LKRST_ON_RS_RESET_EN_", 1, 1, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_EN_", 8, 8, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_VALUE_", 9, 12, &umr_bitfield_default }, - { "READ_WRR_WEIGHT_", 16, 23, &umr_bitfield_default }, - { "WRITE_WRR_WEIGHT_", 24, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixDMA_CLK0_SW0_CL1_CNTL[] = { - { "FLR_ON_RS_RESET_EN_", 0, 0, &umr_bitfield_default }, - { "LKRST_ON_RS_RESET_EN_", 1, 1, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_EN_", 8, 8, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_VALUE_", 9, 12, &umr_bitfield_default }, - { "READ_WRR_WEIGHT_", 16, 23, &umr_bitfield_default }, - { "WRITE_WRR_WEIGHT_", 24, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixDMA_CLK0_SW0_CL2_CNTL[] = { - { "FLR_ON_RS_RESET_EN_", 0, 0, &umr_bitfield_default }, - { "LKRST_ON_RS_RESET_EN_", 1, 1, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_EN_", 8, 8, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_VALUE_", 9, 12, &umr_bitfield_default }, - { "READ_WRR_WEIGHT_", 16, 23, &umr_bitfield_default }, - { "WRITE_WRR_WEIGHT_", 24, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixDMA_CLK0_SW0_CL3_CNTL[] = { - { "FLR_ON_RS_RESET_EN_", 0, 0, &umr_bitfield_default }, - { "LKRST_ON_RS_RESET_EN_", 1, 1, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_EN_", 8, 8, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_VALUE_", 9, 12, &umr_bitfield_default }, - { "READ_WRR_WEIGHT_", 16, 23, &umr_bitfield_default }, - { "WRITE_WRR_WEIGHT_", 24, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixDMA_CLK0_SW0_CL4_CNTL[] = { - { "FLR_ON_RS_RESET_EN_", 0, 0, &umr_bitfield_default }, - { "LKRST_ON_RS_RESET_EN_", 1, 1, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_EN_", 8, 8, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_VALUE_", 9, 12, &umr_bitfield_default }, - { "READ_WRR_WEIGHT_", 16, 23, &umr_bitfield_default }, - { "WRITE_WRR_WEIGHT_", 24, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixDMA_CLK0_SW0_CL5_CNTL[] = { - { "FLR_ON_RS_RESET_EN_", 0, 0, &umr_bitfield_default }, - { "LKRST_ON_RS_RESET_EN_", 1, 1, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_EN_", 8, 8, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_VALUE_", 9, 12, &umr_bitfield_default }, - { "READ_WRR_WEIGHT_", 16, 23, &umr_bitfield_default }, - { "WRITE_WRR_WEIGHT_", 24, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixDMA_CLK0_SW1_CL0_CNTL[] = { - { "FLR_ON_RS_RESET_EN_", 0, 0, &umr_bitfield_default }, - { "LKRST_ON_RS_RESET_EN_", 1, 1, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_EN_", 8, 8, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_VALUE_", 9, 12, &umr_bitfield_default }, - { "READ_WRR_WEIGHT_", 16, 23, &umr_bitfield_default }, - { "WRITE_WRR_WEIGHT_", 24, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixDMA_CLK0_SW2_CL0_CNTL[] = { - { "FLR_ON_RS_RESET_EN_", 0, 0, &umr_bitfield_default }, - { "LKRST_ON_RS_RESET_EN_", 1, 1, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_EN_", 8, 8, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_VALUE_", 9, 12, &umr_bitfield_default }, - { "READ_WRR_WEIGHT_", 16, 23, &umr_bitfield_default }, - { "WRITE_WRR_WEIGHT_", 24, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSYSHUB_CG_CNTL[] = { - { "SYSHUB_CG_EN_", 0, 0, &umr_bitfield_default }, - { "SYSHUB_CG_IDLE_TIMER_", 8, 15, &umr_bitfield_default }, - { "SYSHUB_CG_WAKEUP_TIMER_", 16, 23, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSYSHUB_TRANS_IDLE[] = { - { "SYSHUB_TRANS_IDLE_VF0_", 0, 0, &umr_bitfield_default }, - { "SYSHUB_TRANS_IDLE_VF1_", 1, 1, &umr_bitfield_default }, - { "SYSHUB_TRANS_IDLE_VF2_", 2, 2, &umr_bitfield_default }, - { "SYSHUB_TRANS_IDLE_VF3_", 3, 3, &umr_bitfield_default }, - { "SYSHUB_TRANS_IDLE_VF4_", 4, 4, &umr_bitfield_default }, - { "SYSHUB_TRANS_IDLE_VF5_", 5, 5, &umr_bitfield_default }, - { "SYSHUB_TRANS_IDLE_VF6_", 6, 6, &umr_bitfield_default }, - { "SYSHUB_TRANS_IDLE_VF7_", 7, 7, &umr_bitfield_default }, - { "SYSHUB_TRANS_IDLE_VF8_", 8, 8, &umr_bitfield_default }, - { "SYSHUB_TRANS_IDLE_VF9_", 9, 9, &umr_bitfield_default }, - { "SYSHUB_TRANS_IDLE_VF10_", 10, 10, &umr_bitfield_default }, - { "SYSHUB_TRANS_IDLE_VF11_", 11, 11, &umr_bitfield_default }, - { "SYSHUB_TRANS_IDLE_VF12_", 12, 12, &umr_bitfield_default }, - { "SYSHUB_TRANS_IDLE_VF13_", 13, 13, &umr_bitfield_default }, - { "SYSHUB_TRANS_IDLE_VF14_", 14, 14, &umr_bitfield_default }, - { "SYSHUB_TRANS_IDLE_VF15_", 15, 15, &umr_bitfield_default }, - { "SYSHUB_TRANS_IDLE_PF_", 16, 16, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSYSHUB_HP_TIMER[] = { - { "SYSHUB_HP_TIMER_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSYSHUB_SCRATCH[] = { - { "SCRATCH_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSYSHUB_DS_CTRL_SHUBCLK[] = { - { "HST_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_", 0, 0, &umr_bitfield_default }, - { "HST_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_", 1, 1, &umr_bitfield_default }, - { "HST_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_", 2, 2, &umr_bitfield_default }, - { "HST_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_", 3, 3, &umr_bitfield_default }, - { "HST_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_", 4, 4, &umr_bitfield_default }, - { "HST_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_", 5, 5, &umr_bitfield_default }, - { "HST_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_", 6, 6, &umr_bitfield_default }, - { "HST_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_", 7, 7, &umr_bitfield_default }, - { "DMA_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_", 16, 16, &umr_bitfield_default }, - { "DMA_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_", 17, 17, &umr_bitfield_default }, - { "DMA_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_", 18, 18, &umr_bitfield_default }, - { "DMA_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_", 19, 19, &umr_bitfield_default }, - { "DMA_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_", 20, 20, &umr_bitfield_default }, - { "DMA_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_", 21, 21, &umr_bitfield_default }, - { "DMA_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_", 22, 22, &umr_bitfield_default }, - { "DMA_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_", 23, 23, &umr_bitfield_default }, - { "SYSHUB_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_", 28, 28, &umr_bitfield_default }, - { "SYSHUB_SHUBCLK_DS_EN_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSYSHUB_DS_CTRL2_SHUBCLK[] = { - { "SYSHUB_SHUBCLK_DS_TIMER_", 0, 15, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK[] = { - { "SYSHUB_bgen_shubclk_DMA_SW0_bypass_en_", 15, 15, &umr_bitfield_default }, - { "SYSHUB_bgen_shubclk_DMA_SW1_bypass_en_", 16, 16, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK[] = { - { "SYSHUB_bgen_shubclk_DMA_SW0_imm_en_", 15, 15, &umr_bitfield_default }, - { "SYSHUB_bgen_shubclk_DMA_SW1_imm_en_", 16, 16, &umr_bitfield_default }, -}; -static struct umr_bitfield ixDMA_CLK1_SW0_SYSHUB_QOS_CNTL[] = { - { "QOS_CNTL_MODE_", 0, 0, &umr_bitfield_default }, - { "QOS_MAX_VALUE_", 1, 4, &umr_bitfield_default }, - { "QOS_MIN_VALUE_", 5, 8, &umr_bitfield_default }, -}; -static struct umr_bitfield ixDMA_CLK1_SW1_SYSHUB_QOS_CNTL[] = { - { "QOS_CNTL_MODE_", 0, 0, &umr_bitfield_default }, - { "QOS_MAX_VALUE_", 1, 4, &umr_bitfield_default }, - { "QOS_MIN_VALUE_", 5, 8, &umr_bitfield_default }, -}; -static struct umr_bitfield ixDMA_CLK1_SW0_CL0_CNTL[] = { - { "FLR_ON_RS_RESET_EN_", 0, 0, &umr_bitfield_default }, - { "LKRST_ON_RS_RESET_EN_", 1, 1, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_EN_", 8, 8, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_VALUE_", 9, 12, &umr_bitfield_default }, - { "READ_WRR_WEIGHT_", 16, 23, &umr_bitfield_default }, - { "WRITE_WRR_WEIGHT_", 24, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixDMA_CLK1_SW0_CL1_CNTL[] = { - { "FLR_ON_RS_RESET_EN_", 0, 0, &umr_bitfield_default }, - { "LKRST_ON_RS_RESET_EN_", 1, 1, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_EN_", 8, 8, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_VALUE_", 9, 12, &umr_bitfield_default }, - { "READ_WRR_WEIGHT_", 16, 23, &umr_bitfield_default }, - { "WRITE_WRR_WEIGHT_", 24, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixDMA_CLK1_SW0_CL2_CNTL[] = { - { "FLR_ON_RS_RESET_EN_", 0, 0, &umr_bitfield_default }, - { "LKRST_ON_RS_RESET_EN_", 1, 1, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_EN_", 8, 8, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_VALUE_", 9, 12, &umr_bitfield_default }, - { "READ_WRR_WEIGHT_", 16, 23, &umr_bitfield_default }, - { "WRITE_WRR_WEIGHT_", 24, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixDMA_CLK1_SW0_CL3_CNTL[] = { - { "FLR_ON_RS_RESET_EN_", 0, 0, &umr_bitfield_default }, - { "LKRST_ON_RS_RESET_EN_", 1, 1, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_EN_", 8, 8, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_VALUE_", 9, 12, &umr_bitfield_default }, - { "READ_WRR_WEIGHT_", 16, 23, &umr_bitfield_default }, - { "WRITE_WRR_WEIGHT_", 24, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixDMA_CLK1_SW0_CL4_CNTL[] = { - { "FLR_ON_RS_RESET_EN_", 0, 0, &umr_bitfield_default }, - { "LKRST_ON_RS_RESET_EN_", 1, 1, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_EN_", 8, 8, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_VALUE_", 9, 12, &umr_bitfield_default }, - { "READ_WRR_WEIGHT_", 16, 23, &umr_bitfield_default }, - { "WRITE_WRR_WEIGHT_", 24, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixDMA_CLK1_SW1_CL0_CNTL[] = { - { "FLR_ON_RS_RESET_EN_", 0, 0, &umr_bitfield_default }, - { "LKRST_ON_RS_RESET_EN_", 1, 1, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_EN_", 8, 8, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_VALUE_", 9, 12, &umr_bitfield_default }, - { "READ_WRR_WEIGHT_", 16, 23, &umr_bitfield_default }, - { "WRITE_WRR_WEIGHT_", 24, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixDMA_CLK1_SW1_CL1_CNTL[] = { - { "FLR_ON_RS_RESET_EN_", 0, 0, &umr_bitfield_default }, - { "LKRST_ON_RS_RESET_EN_", 1, 1, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_EN_", 8, 8, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_VALUE_", 9, 12, &umr_bitfield_default }, - { "READ_WRR_WEIGHT_", 16, 23, &umr_bitfield_default }, - { "WRITE_WRR_WEIGHT_", 24, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixDMA_CLK1_SW1_CL2_CNTL[] = { - { "FLR_ON_RS_RESET_EN_", 0, 0, &umr_bitfield_default }, - { "LKRST_ON_RS_RESET_EN_", 1, 1, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_EN_", 8, 8, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_VALUE_", 9, 12, &umr_bitfield_default }, - { "READ_WRR_WEIGHT_", 16, 23, &umr_bitfield_default }, - { "WRITE_WRR_WEIGHT_", 24, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixDMA_CLK1_SW1_CL3_CNTL[] = { - { "FLR_ON_RS_RESET_EN_", 0, 0, &umr_bitfield_default }, - { "LKRST_ON_RS_RESET_EN_", 1, 1, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_EN_", 8, 8, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_VALUE_", 9, 12, &umr_bitfield_default }, - { "READ_WRR_WEIGHT_", 16, 23, &umr_bitfield_default }, - { "WRITE_WRR_WEIGHT_", 24, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixDMA_CLK1_SW1_CL4_CNTL[] = { - { "FLR_ON_RS_RESET_EN_", 0, 0, &umr_bitfield_default }, - { "LKRST_ON_RS_RESET_EN_", 1, 1, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_EN_", 8, 8, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_VALUE_", 9, 12, &umr_bitfield_default }, - { "READ_WRR_WEIGHT_", 16, 23, &umr_bitfield_default }, - { "WRITE_WRR_WEIGHT_", 24, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixGDC_RAS_LEAF0_CTRL[] = { - { "POISON_DET_EN_", 0, 0, &umr_bitfield_default }, - { "POISON_ERREVENT_EN_", 1, 1, &umr_bitfield_default }, - { "POISON_STALL_EN_", 2, 2, &umr_bitfield_default }, - { "PARITY_DET_EN_", 4, 4, &umr_bitfield_default }, - { "PARITY_ERREVENT_EN_", 5, 5, &umr_bitfield_default }, - { "PARITY_STALL_EN_", 6, 6, &umr_bitfield_default }, - { "ERR_EVENT_RECV_", 16, 16, &umr_bitfield_default }, - { "LINK_DIS_RECV_", 17, 17, &umr_bitfield_default }, - { "POISON_ERR_DET_", 18, 18, &umr_bitfield_default }, - { "PARITY_ERR_DET_", 19, 19, &umr_bitfield_default }, - { "ERR_EVENT_SENT_", 20, 20, &umr_bitfield_default }, - { "EGRESS_STALLED_", 21, 21, &umr_bitfield_default }, -}; -static struct umr_bitfield ixGDC_RAS_LEAF1_CTRL[] = { - { "POISON_DET_EN_", 0, 0, &umr_bitfield_default }, - { "POISON_ERREVENT_EN_", 1, 1, &umr_bitfield_default }, - { "POISON_STALL_EN_", 2, 2, &umr_bitfield_default }, - { "PARITY_DET_EN_", 4, 4, &umr_bitfield_default }, - { "PARITY_ERREVENT_EN_", 5, 5, &umr_bitfield_default }, - { "PARITY_STALL_EN_", 6, 6, &umr_bitfield_default }, - { "ERR_EVENT_RECV_", 16, 16, &umr_bitfield_default }, - { "LINK_DIS_RECV_", 17, 17, &umr_bitfield_default }, - { "POISON_ERR_DET_", 18, 18, &umr_bitfield_default }, - { "PARITY_ERR_DET_", 19, 19, &umr_bitfield_default }, - { "ERR_EVENT_SENT_", 20, 20, &umr_bitfield_default }, - { "EGRESS_STALLED_", 21, 21, &umr_bitfield_default }, -}; -static struct umr_bitfield ixGDC_RAS_LEAF2_CTRL[] = { - { "POISON_DET_EN_", 0, 0, &umr_bitfield_default }, - { "POISON_ERREVENT_EN_", 1, 1, &umr_bitfield_default }, - { "POISON_STALL_EN_", 2, 2, &umr_bitfield_default }, - { "PARITY_DET_EN_", 4, 4, &umr_bitfield_default }, - { "PARITY_ERREVENT_EN_", 5, 5, &umr_bitfield_default }, - { "PARITY_STALL_EN_", 6, 6, &umr_bitfield_default }, - { "ERR_EVENT_RECV_", 16, 16, &umr_bitfield_default }, - { "LINK_DIS_RECV_", 17, 17, &umr_bitfield_default }, - { "POISON_ERR_DET_", 18, 18, &umr_bitfield_default }, - { "PARITY_ERR_DET_", 19, 19, &umr_bitfield_default }, - { "ERR_EVENT_SENT_", 20, 20, &umr_bitfield_default }, - { "EGRESS_STALLED_", 21, 21, &umr_bitfield_default }, -}; -static struct umr_bitfield ixGDC_RAS_LEAF3_CTRL[] = { - { "POISON_DET_EN_", 0, 0, &umr_bitfield_default }, - { "POISON_ERREVENT_EN_", 1, 1, &umr_bitfield_default }, - { "POISON_STALL_EN_", 2, 2, &umr_bitfield_default }, - { "PARITY_DET_EN_", 4, 4, &umr_bitfield_default }, - { "PARITY_ERREVENT_EN_", 5, 5, &umr_bitfield_default }, - { "PARITY_STALL_EN_", 6, 6, &umr_bitfield_default }, - { "ERR_EVENT_RECV_", 16, 16, &umr_bitfield_default }, - { "LINK_DIS_RECV_", 17, 17, &umr_bitfield_default }, - { "POISON_ERR_DET_", 18, 18, &umr_bitfield_default }, - { "PARITY_ERR_DET_", 19, 19, &umr_bitfield_default }, - { "ERR_EVENT_SENT_", 20, 20, &umr_bitfield_default }, - { "EGRESS_STALLED_", 21, 21, &umr_bitfield_default }, -}; -static struct umr_bitfield ixGDC_RAS_LEAF4_CTRL[] = { - { "POISON_DET_EN_", 0, 0, &umr_bitfield_default }, - { "POISON_ERREVENT_EN_", 1, 1, &umr_bitfield_default }, - { "POISON_STALL_EN_", 2, 2, &umr_bitfield_default }, - { "PARITY_DET_EN_", 4, 4, &umr_bitfield_default }, - { "PARITY_ERREVENT_EN_", 5, 5, &umr_bitfield_default }, - { "PARITY_STALL_EN_", 6, 6, &umr_bitfield_default }, - { "ERR_EVENT_RECV_", 16, 16, &umr_bitfield_default }, - { "LINK_DIS_RECV_", 17, 17, &umr_bitfield_default }, - { "POISON_ERR_DET_", 18, 18, &umr_bitfield_default }, - { "PARITY_ERR_DET_", 19, 19, &umr_bitfield_default }, - { "ERR_EVENT_SENT_", 20, 20, &umr_bitfield_default }, - { "EGRESS_STALLED_", 21, 21, &umr_bitfield_default }, -}; -static struct umr_bitfield ixGDC_RAS_LEAF5_CTRL[] = { - { "POISON_DET_EN_", 0, 0, &umr_bitfield_default }, - { "POISON_ERREVENT_EN_", 1, 1, &umr_bitfield_default }, - { "POISON_STALL_EN_", 2, 2, &umr_bitfield_default }, - { "PARITY_DET_EN_", 4, 4, &umr_bitfield_default }, - { "PARITY_ERREVENT_EN_", 5, 5, &umr_bitfield_default }, - { "PARITY_STALL_EN_", 6, 6, &umr_bitfield_default }, - { "ERR_EVENT_RECV_", 16, 16, &umr_bitfield_default }, - { "LINK_DIS_RECV_", 17, 17, &umr_bitfield_default }, - { "POISON_ERR_DET_", 18, 18, &umr_bitfield_default }, - { "PARITY_ERR_DET_", 19, 19, &umr_bitfield_default }, - { "ERR_EVENT_SENT_", 20, 20, &umr_bitfield_default }, - { "EGRESS_STALLED_", 21, 21, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSHUB_PF_FLR_RST[] = { - { "PF0_FLR_RST_", 0, 0, &umr_bitfield_default }, - { "PF1_FLR_RST_", 1, 1, &umr_bitfield_default }, - { "PF2_FLR_RST_", 2, 2, &umr_bitfield_default }, - { "PF3_FLR_RST_", 3, 3, &umr_bitfield_default }, - { "PF4_FLR_RST_", 4, 4, &umr_bitfield_default }, - { "PF5_FLR_RST_", 5, 5, &umr_bitfield_default }, - { "PF6_FLR_RST_", 6, 6, &umr_bitfield_default }, - { "PF7_FLR_RST_", 7, 7, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSHUB_GFX_DRV_MODE1_RST[] = { - { "GFX_DRV_MODE1_RST_", 0, 0, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSHUB_LINK_RESET[] = { - { "LINK_RESET_", 0, 0, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSHUB_PF0_VF_FLR_RST[] = { - { "PF0_VF0_FLR_RST_", 0, 0, &umr_bitfield_default }, - { "PF0_VF1_FLR_RST_", 1, 1, &umr_bitfield_default }, - { "PF0_VF2_FLR_RST_", 2, 2, &umr_bitfield_default }, - { "PF0_VF3_FLR_RST_", 3, 3, &umr_bitfield_default }, - { "PF0_VF4_FLR_RST_", 4, 4, &umr_bitfield_default }, - { "PF0_VF5_FLR_RST_", 5, 5, &umr_bitfield_default }, - { "PF0_VF6_FLR_RST_", 6, 6, &umr_bitfield_default }, - { "PF0_VF7_FLR_RST_", 7, 7, &umr_bitfield_default }, - { "PF0_VF8_FLR_RST_", 8, 8, &umr_bitfield_default }, - { "PF0_VF9_FLR_RST_", 9, 9, &umr_bitfield_default }, - { "PF0_VF10_FLR_RST_", 10, 10, &umr_bitfield_default }, - { "PF0_VF11_FLR_RST_", 11, 11, &umr_bitfield_default }, - { "PF0_VF12_FLR_RST_", 12, 12, &umr_bitfield_default }, - { "PF0_VF13_FLR_RST_", 13, 13, &umr_bitfield_default }, - { "PF0_VF14_FLR_RST_", 14, 14, &umr_bitfield_default }, - { "PF0_VF15_FLR_RST_", 15, 15, &umr_bitfield_default }, - { "PF0_SOFTPF_FLR_RST_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSHUB_HARD_RST_CTRL[] = { - { "COR_RESET_EN_", 0, 0, &umr_bitfield_default }, - { "REG_RESET_EN_", 1, 1, &umr_bitfield_default }, - { "STY_RESET_EN_", 2, 2, &umr_bitfield_default }, - { "NIC400_RESET_EN_", 3, 3, &umr_bitfield_default }, - { "SDP_PORT_RESET_EN_", 4, 4, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSHUB_SOFT_RST_CTRL[] = { - { "COR_RESET_EN_", 0, 0, &umr_bitfield_default }, - { "REG_RESET_EN_", 1, 1, &umr_bitfield_default }, - { "STY_RESET_EN_", 2, 2, &umr_bitfield_default }, - { "NIC400_RESET_EN_", 3, 3, &umr_bitfield_default }, - { "SDP_PORT_RESET_EN_", 4, 4, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSHUB_SDP_PORT_RST[] = { - { "SDP_PORT_RST_", 0, 0, &umr_bitfield_default }, -}; -static struct umr_bitfield mmSBIOS_SCRATCH_0[] = { - { "SBIOS_SCRATCH_DW_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmSBIOS_SCRATCH_1[] = { - { "SBIOS_SCRATCH_DW_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmSBIOS_SCRATCH_2[] = { - { "SBIOS_SCRATCH_DW_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmSBIOS_SCRATCH_3[] = { - { "SBIOS_SCRATCH_DW_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIOS_SCRATCH_0[] = { - { "BIOS_SCRATCH_0_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIOS_SCRATCH_1[] = { - { "BIOS_SCRATCH_1_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIOS_SCRATCH_2[] = { - { "BIOS_SCRATCH_2_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIOS_SCRATCH_3[] = { - { "BIOS_SCRATCH_3_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIOS_SCRATCH_4[] = { - { "BIOS_SCRATCH_4_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIOS_SCRATCH_5[] = { - { "BIOS_SCRATCH_5_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIOS_SCRATCH_6[] = { - { "BIOS_SCRATCH_6_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIOS_SCRATCH_7[] = { - { "BIOS_SCRATCH_7_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIOS_SCRATCH_8[] = { - { "BIOS_SCRATCH_8_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIOS_SCRATCH_9[] = { - { "BIOS_SCRATCH_9_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIOS_SCRATCH_10[] = { - { "BIOS_SCRATCH_10_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIOS_SCRATCH_11[] = { - { "BIOS_SCRATCH_11_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIOS_SCRATCH_12[] = { - { "BIOS_SCRATCH_12_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIOS_SCRATCH_13[] = { - { "BIOS_SCRATCH_13_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIOS_SCRATCH_14[] = { - { "BIOS_SCRATCH_14_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIOS_SCRATCH_15[] = { - { "BIOS_SCRATCH_15_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_RLC_INTR_CNTL[] = { - { "RLC_CMD_COMPLETE_", 0, 0, &umr_bitfield_default }, - { "RLC_HANG_SELF_RECOVERED_", 1, 1, &umr_bitfield_default }, - { "RLC_HANG_NEED_FLR_", 2, 2, &umr_bitfield_default }, - { "RLC_VM_BUSY_TRANSITION_", 3, 3, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_VCE_INTR_CNTL[] = { - { "VCE_CMD_COMPLETE_", 0, 0, &umr_bitfield_default }, - { "VCE_HANG_SELF_RECOVERED_", 1, 1, &umr_bitfield_default }, - { "VCE_HANG_NEED_FLR_", 2, 2, &umr_bitfield_default }, - { "VCE_VM_BUSY_TRANSITION_", 3, 3, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_UVD_INTR_CNTL[] = { - { "UVD_CMD_COMPLETE_", 0, 0, &umr_bitfield_default }, - { "UVD_HANG_SELF_RECOVERED_", 1, 1, &umr_bitfield_default }, - { "UVD_HANG_NEED_FLR_", 2, 2, &umr_bitfield_default }, - { "UVD_VM_BUSY_TRANSITION_", 3, 3, &umr_bitfield_default }, -}; -static struct umr_bitfield mmGFX_MMIOREG_CAM_ADDR0[] = { - { "CAM_ADDR0_", 0, 19, &umr_bitfield_default }, -}; -static struct umr_bitfield mmGFX_MMIOREG_CAM_REMAP_ADDR0[] = { - { "CAM_REMAP_ADDR0_", 0, 19, &umr_bitfield_default }, -}; -static struct umr_bitfield mmGFX_MMIOREG_CAM_ADDR1[] = { - { "CAM_ADDR1_", 0, 19, &umr_bitfield_default }, -}; -static struct umr_bitfield mmGFX_MMIOREG_CAM_REMAP_ADDR1[] = { - { "CAM_REMAP_ADDR1_", 0, 19, &umr_bitfield_default }, -}; -static struct umr_bitfield mmGFX_MMIOREG_CAM_ADDR2[] = { - { "CAM_ADDR2_", 0, 19, &umr_bitfield_default }, -}; -static struct umr_bitfield mmGFX_MMIOREG_CAM_REMAP_ADDR2[] = { - { "CAM_REMAP_ADDR2_", 0, 19, &umr_bitfield_default }, -}; -static struct umr_bitfield mmGFX_MMIOREG_CAM_ADDR3[] = { - { "CAM_ADDR3_", 0, 19, &umr_bitfield_default }, -}; -static struct umr_bitfield mmGFX_MMIOREG_CAM_REMAP_ADDR3[] = { - { "CAM_REMAP_ADDR3_", 0, 19, &umr_bitfield_default }, -}; -static struct umr_bitfield mmGFX_MMIOREG_CAM_ADDR4[] = { - { "CAM_ADDR4_", 0, 19, &umr_bitfield_default }, -}; -static struct umr_bitfield mmGFX_MMIOREG_CAM_REMAP_ADDR4[] = { - { "CAM_REMAP_ADDR4_", 0, 19, &umr_bitfield_default }, -}; -static struct umr_bitfield mmGFX_MMIOREG_CAM_ADDR5[] = { - { "CAM_ADDR5_", 0, 19, &umr_bitfield_default }, -}; -static struct umr_bitfield mmGFX_MMIOREG_CAM_REMAP_ADDR5[] = { - { "CAM_REMAP_ADDR5_", 0, 19, &umr_bitfield_default }, -}; -static struct umr_bitfield mmGFX_MMIOREG_CAM_ADDR6[] = { - { "CAM_ADDR6_", 0, 19, &umr_bitfield_default }, -}; -static struct umr_bitfield mmGFX_MMIOREG_CAM_REMAP_ADDR6[] = { - { "CAM_REMAP_ADDR6_", 0, 19, &umr_bitfield_default }, -}; -static struct umr_bitfield mmGFX_MMIOREG_CAM_ADDR7[] = { - { "CAM_ADDR7_", 0, 19, &umr_bitfield_default }, -}; -static struct umr_bitfield mmGFX_MMIOREG_CAM_REMAP_ADDR7[] = { - { "CAM_REMAP_ADDR7_", 0, 19, &umr_bitfield_default }, -}; -static struct umr_bitfield mmGFX_MMIOREG_CAM_CNTL[] = { - { "CAM_ENABLE_", 0, 7, &umr_bitfield_default }, -}; -static struct umr_bitfield mmGFX_MMIOREG_CAM_ZERO_CPL[] = { - { "CAM_ZERO_CPL_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmGFX_MMIOREG_CAM_ONE_CPL[] = { - { "CAM_ONE_CPL_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL[] = { - { "CAM_PROGRAMMABLE_CPL_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmMM_INDEX[] = { - { "MM_OFFSET_", 0, 30, &umr_bitfield_default }, - { "MM_APER_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmMM_DATA[] = { - { "MM_DATA_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmMM_INDEX_HI[] = { - { "MM_OFFSET_HI_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmSYSHUB_INDEX_OVLP[] = { - { "SYSHUB_OFFSET_", 0, 21, &umr_bitfield_default }, -}; -static struct umr_bitfield mmSYSHUB_DATA_OVLP[] = { - { "SYSHUB_DATA_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmPCIE_INDEX[] = { - { "PCIE_INDEX_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmPCIE_DATA[] = { - { "PCIE_DATA_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmPCIE_INDEX2[] = { - { "PCIE_INDEX2_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmPCIE_DATA2[] = { - { "PCIE_DATA2_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmDN_PCIE_RESERVED[] = { - { "PCIE_RESERVED_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmDN_PCIE_SCRATCH[] = { - { "PCIE_SCRATCH_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmDN_PCIE_CNTL[] = { - { "HWINIT_WR_LOCK_", 0, 0, &umr_bitfield_default }, - { "UR_ERR_REPORT_DIS_DN_", 7, 7, &umr_bitfield_default }, - { "RX_IGNORE_LTR_MSG_UR_", 30, 30, &umr_bitfield_default }, -}; -static struct umr_bitfield mmDN_PCIE_CONFIG_CNTL[] = { - { "CI_EXTENDED_TAG_EN_OVERRIDE_", 25, 26, &umr_bitfield_default }, -}; -static struct umr_bitfield mmDN_PCIE_RX_CNTL2[] = { - { "FLR_EXTEND_MODE_", 28, 30, &umr_bitfield_default }, -}; -static struct umr_bitfield mmDN_PCIE_BUS_CNTL[] = { - { "IMMEDIATE_PMI_DIS_", 7, 7, &umr_bitfield_default }, - { "AER_CPL_TIMEOUT_RO_DIS_SWDN_", 8, 8, &umr_bitfield_default }, -}; -static struct umr_bitfield mmDN_PCIE_CFG_CNTL[] = { - { "CFG_EN_DEC_TO_HIDDEN_REG_", 0, 0, &umr_bitfield_default }, - { "CFG_EN_DEC_TO_GEN2_HIDDEN_REG_", 1, 1, &umr_bitfield_default }, - { "CFG_EN_DEC_TO_GEN3_HIDDEN_REG_", 2, 2, &umr_bitfield_default }, -}; -static struct umr_bitfield mmDN_PCIE_STRAP_F0[] = { - { "STRAP_F0_EN_", 0, 0, &umr_bitfield_default }, - { "STRAP_F0_MC_EN_", 17, 17, &umr_bitfield_default }, - { "STRAP_F0_MSI_MULTI_CAP_", 21, 23, &umr_bitfield_default }, -}; -static struct umr_bitfield mmDN_PCIE_STRAP_MISC[] = { - { "STRAP_CLK_PM_EN_", 24, 24, &umr_bitfield_default }, - { "STRAP_MST_ADR64_EN_", 29, 29, &umr_bitfield_default }, -}; -static struct umr_bitfield mmDN_PCIE_STRAP_MISC2[] = { - { "STRAP_MSTCPL_TIMEOUT_EN_", 2, 2, &umr_bitfield_default }, -}; -static struct umr_bitfield mmPCIEP_RESERVED[] = { - { "PCIEP_RESERVED_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmPCIEP_SCRATCH[] = { - { "PCIEP_SCRATCH_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmPCIE_ERR_CNTL[] = { - { "ERR_REPORTING_DIS_", 0, 0, &umr_bitfield_default }, - { "AER_HDR_LOG_TIMEOUT_", 8, 10, &umr_bitfield_default }, - { "AER_HDR_LOG_F0_TIMER_EXPIRED_", 11, 11, &umr_bitfield_default }, - { "SEND_ERR_MSG_IMMEDIATELY_", 17, 17, &umr_bitfield_default }, -}; -static struct umr_bitfield mmPCIE_RX_CNTL[] = { - { "RX_IGNORE_MAX_PAYLOAD_ERR_", 8, 8, &umr_bitfield_default }, - { "RX_IGNORE_TC_ERR_DN_", 9, 9, &umr_bitfield_default }, - { "RX_PCIE_CPL_TIMEOUT_DIS_", 20, 20, &umr_bitfield_default }, - { "RX_IGNORE_SHORTPREFIX_ERR_DN_", 21, 21, &umr_bitfield_default }, - { "RX_RCB_FLR_TIMEOUT_DIS_", 27, 27, &umr_bitfield_default }, -}; -static struct umr_bitfield mmPCIE_LC_SPEED_CNTL[] = { - { "LC_GEN2_EN_STRAP_", 0, 0, &umr_bitfield_default }, - { "LC_GEN3_EN_STRAP_", 1, 1, &umr_bitfield_default }, -}; -static struct umr_bitfield mmPCIE_LC_CNTL2[] = { - { "LC_LINK_BW_NOTIFICATION_DIS_", 27, 27, &umr_bitfield_default }, -}; -static struct umr_bitfield mmPCIEP_STRAP_MISC[] = { - { "STRAP_MULTI_FUNC_EN_", 10, 10, &umr_bitfield_default }, -}; -static struct umr_bitfield mmLTR_MSG_INFO_FROM_EP[] = { - { "LTR_MSG_INFO_FROM_EP_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmEP_PCIE_SCRATCH[] = { - { "PCIE_SCRATCH_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmEP_PCIE_CNTL[] = { - { "UR_ERR_REPORT_DIS_", 7, 7, &umr_bitfield_default }, - { "PCIE_MALFORM_ATOMIC_OPS_", 8, 8, &umr_bitfield_default }, - { "RX_IGNORE_LTR_MSG_UR_", 30, 30, &umr_bitfield_default }, -}; -static struct umr_bitfield mmEP_PCIE_INT_CNTL[] = { - { "CORR_ERR_INT_EN_", 0, 0, &umr_bitfield_default }, - { "NON_FATAL_ERR_INT_EN_", 1, 1, &umr_bitfield_default }, - { "FATAL_ERR_INT_EN_", 2, 2, &umr_bitfield_default }, - { "USR_DETECTED_INT_EN_", 3, 3, &umr_bitfield_default }, - { "MISC_ERR_INT_EN_", 4, 4, &umr_bitfield_default }, - { "POWER_STATE_CHG_INT_EN_", 6, 6, &umr_bitfield_default }, -}; -static struct umr_bitfield mmEP_PCIE_INT_STATUS[] = { - { "CORR_ERR_INT_STATUS_", 0, 0, &umr_bitfield_default }, - { "NON_FATAL_ERR_INT_STATUS_", 1, 1, &umr_bitfield_default }, - { "FATAL_ERR_INT_STATUS_", 2, 2, &umr_bitfield_default }, - { "USR_DETECTED_INT_STATUS_", 3, 3, &umr_bitfield_default }, - { "MISC_ERR_INT_STATUS_", 4, 4, &umr_bitfield_default }, - { "POWER_STATE_CHG_INT_STATUS_", 6, 6, &umr_bitfield_default }, -}; -static struct umr_bitfield mmEP_PCIE_RX_CNTL2[] = { - { "RX_IGNORE_EP_INVALIDPASID_UR_", 0, 0, &umr_bitfield_default }, -}; -static struct umr_bitfield mmEP_PCIE_BUS_CNTL[] = { - { "IMMEDIATE_PMI_DIS_", 7, 7, &umr_bitfield_default }, -}; -static struct umr_bitfield mmEP_PCIE_CFG_CNTL[] = { - { "CFG_EN_DEC_TO_HIDDEN_REG_", 0, 0, &umr_bitfield_default }, - { "CFG_EN_DEC_TO_GEN2_HIDDEN_REG_", 1, 1, &umr_bitfield_default }, - { "CFG_EN_DEC_TO_GEN3_HIDDEN_REG_", 2, 2, &umr_bitfield_default }, -}; -static struct umr_bitfield mmEP_PCIE_OBFF_CNTL[] = { - { "TX_OBFF_PRIV_DISABLE_", 0, 0, &umr_bitfield_default }, - { "TX_OBFF_WAKE_SIMPLE_MODE_EN_", 1, 1, &umr_bitfield_default }, - { "TX_OBFF_HOSTMEM_TO_ACTIVE_", 2, 2, &umr_bitfield_default }, - { "TX_OBFF_SLVCPL_TO_ACTIVE_", 3, 3, &umr_bitfield_default }, - { "TX_OBFF_WAKE_MAX_PULSE_WIDTH_", 4, 7, &umr_bitfield_default }, - { "TX_OBFF_WAKE_MAX_TWO_FALLING_WIDTH_", 8, 11, &umr_bitfield_default }, - { "TX_OBFF_WAKE_SAMPLING_PERIOD_", 12, 15, &umr_bitfield_default }, - { "TX_OBFF_INTR_TO_ACTIVE_", 16, 16, &umr_bitfield_default }, - { "TX_OBFF_ERR_TO_ACTIVE_", 17, 17, &umr_bitfield_default }, - { "TX_OBFF_ANY_MSG_TO_ACTIVE_", 18, 18, &umr_bitfield_default }, - { "TX_OBFF_ACCEPT_IN_NOND0_", 19, 19, &umr_bitfield_default }, - { "TX_OBFF_PENDING_REQ_TO_ACTIVE_", 20, 23, &umr_bitfield_default }, -}; -static struct umr_bitfield mmEP_PCIE_TX_LTR_CNTL[] = { - { "LTR_PRIV_S_SHORT_VALUE_", 0, 2, &umr_bitfield_default }, - { "LTR_PRIV_S_LONG_VALUE_", 3, 5, &umr_bitfield_default }, - { "LTR_PRIV_S_REQUIREMENT_", 6, 6, &umr_bitfield_default }, - { "LTR_PRIV_NS_SHORT_VALUE_", 7, 9, &umr_bitfield_default }, - { "LTR_PRIV_NS_LONG_VALUE_", 10, 12, &umr_bitfield_default }, - { "LTR_PRIV_NS_REQUIREMENT_", 13, 13, &umr_bitfield_default }, - { "LTR_PRIV_MSG_DIS_IN_PM_NON_D0_", 14, 14, &umr_bitfield_default }, - { "LTR_PRIV_RST_LTR_IN_DL_DOWN_", 15, 15, &umr_bitfield_default }, - { "TX_CHK_FC_FOR_L1_", 16, 16, &umr_bitfield_default }, -}; -static struct umr_bitfield mmEP_PCIE_STRAP_MISC[] = { - { "STRAP_MST_ADR64_EN_", 29, 29, &umr_bitfield_default }, -}; -static struct umr_bitfield mmEP_PCIE_STRAP_MISC2[] = { - { "STRAP_TPH_SUPPORTED_", 4, 4, &umr_bitfield_default }, -}; -static struct umr_bitfield mmEP_PCIE_F0_DPA_CAP[] = { - { "TRANS_LAT_UNIT_", 8, 9, &umr_bitfield_default }, - { "PWR_ALLOC_SCALE_", 12, 13, &umr_bitfield_default }, - { "TRANS_LAT_VAL_0_", 16, 23, &umr_bitfield_default }, - { "TRANS_LAT_VAL_1_", 24, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmEP_PCIE_F0_DPA_LATENCY_INDICATOR[] = { - { "TRANS_LAT_INDICATOR_BITS_", 0, 7, &umr_bitfield_default }, -}; -static struct umr_bitfield mmEP_PCIE_F0_DPA_CNTL[] = { - { "SUBSTATE_STATUS_", 0, 4, &umr_bitfield_default }, - { "DPA_COMPLIANCE_MODE_", 8, 8, &umr_bitfield_default }, -}; -static struct umr_bitfield mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0[] = { - { "SUBSTATE_PWR_ALLOC_", 0, 7, &umr_bitfield_default }, -}; -static struct umr_bitfield mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1[] = { - { "SUBSTATE_PWR_ALLOC_", 0, 7, &umr_bitfield_default }, -}; -static struct umr_bitfield mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2[] = { - { "SUBSTATE_PWR_ALLOC_", 0, 7, &umr_bitfield_default }, -}; -static struct umr_bitfield mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3[] = { - { "SUBSTATE_PWR_ALLOC_", 0, 7, &umr_bitfield_default }, -}; -static struct umr_bitfield mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4[] = { - { "SUBSTATE_PWR_ALLOC_", 0, 7, &umr_bitfield_default }, -}; -static struct umr_bitfield mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5[] = { - { "SUBSTATE_PWR_ALLOC_", 0, 7, &umr_bitfield_default }, -}; -static struct umr_bitfield mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6[] = { - { "SUBSTATE_PWR_ALLOC_", 0, 7, &umr_bitfield_default }, -}; -static struct umr_bitfield mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7[] = { - { "SUBSTATE_PWR_ALLOC_", 0, 7, &umr_bitfield_default }, -}; -static struct umr_bitfield mmEP_PCIE_PME_CONTROL[] = { - { "PME_SERVICE_TIMER_", 0, 4, &umr_bitfield_default }, -}; -static struct umr_bitfield mmEP_PCIEP_RESERVED[] = { - { "PCIEP_RESERVED_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmEP_PCIE_TX_CNTL[] = { - { "TX_SNR_OVERRIDE_", 10, 11, &umr_bitfield_default }, - { "TX_RO_OVERRIDE_", 12, 13, &umr_bitfield_default }, - { "TX_F0_TPH_DIS_", 24, 24, &umr_bitfield_default }, - { "TX_F1_TPH_DIS_", 25, 25, &umr_bitfield_default }, - { "TX_F2_TPH_DIS_", 26, 26, &umr_bitfield_default }, -}; -static struct umr_bitfield mmEP_PCIE_TX_REQUESTER_ID[] = { - { "TX_REQUESTER_ID_FUNCTION_", 0, 2, &umr_bitfield_default }, - { "TX_REQUESTER_ID_DEVICE_", 3, 7, &umr_bitfield_default }, - { "TX_REQUESTER_ID_BUS_", 8, 15, &umr_bitfield_default }, -}; -static struct umr_bitfield mmEP_PCIE_ERR_CNTL[] = { - { "ERR_REPORTING_DIS_", 0, 0, &umr_bitfield_default }, - { "AER_HDR_LOG_TIMEOUT_", 8, 10, &umr_bitfield_default }, - { "SEND_ERR_MSG_IMMEDIATELY_", 17, 17, &umr_bitfield_default }, - { "STRAP_POISONED_ADVISORY_NONFATAL_", 18, 18, &umr_bitfield_default }, - { "AER_HDR_LOG_F0_TIMER_EXPIRED_", 24, 24, &umr_bitfield_default }, - { "AER_HDR_LOG_F1_TIMER_EXPIRED_", 25, 25, &umr_bitfield_default }, - { "AER_HDR_LOG_F2_TIMER_EXPIRED_", 26, 26, &umr_bitfield_default }, - { "AER_HDR_LOG_F3_TIMER_EXPIRED_", 27, 27, &umr_bitfield_default }, - { "AER_HDR_LOG_F4_TIMER_EXPIRED_", 28, 28, &umr_bitfield_default }, - { "AER_HDR_LOG_F5_TIMER_EXPIRED_", 29, 29, &umr_bitfield_default }, - { "AER_HDR_LOG_F6_TIMER_EXPIRED_", 30, 30, &umr_bitfield_default }, - { "AER_HDR_LOG_F7_TIMER_EXPIRED_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmEP_PCIE_RX_CNTL[] = { - { "RX_IGNORE_MAX_PAYLOAD_ERR_", 8, 8, &umr_bitfield_default }, - { "RX_IGNORE_TC_ERR_", 9, 9, &umr_bitfield_default }, - { "RX_PCIE_CPL_TIMEOUT_DIS_", 20, 20, &umr_bitfield_default }, - { "RX_IGNORE_SHORTPREFIX_ERR_", 21, 21, &umr_bitfield_default }, - { "RX_IGNORE_MAXPREFIX_ERR_", 22, 22, &umr_bitfield_default }, - { "RX_IGNORE_INVALIDPASID_ERR_", 24, 24, &umr_bitfield_default }, - { "RX_IGNORE_NOT_PASID_UR_", 25, 25, &umr_bitfield_default }, - { "RX_TPH_DIS_", 26, 26, &umr_bitfield_default }, -}; -static struct umr_bitfield mmEP_PCIE_LC_SPEED_CNTL[] = { - { "LC_GEN2_EN_STRAP_", 0, 0, &umr_bitfield_default }, - { "LC_GEN3_EN_STRAP_", 1, 1, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_MM_INDACCESS_CNTL[] = { - { "MM_INDACCESS_DIS_", 1, 1, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBUS_CNTL[] = { - { "PMI_INT_DIS_EP_", 3, 3, &umr_bitfield_default }, - { "PMI_INT_DIS_DN_", 4, 4, &umr_bitfield_default }, - { "PMI_INT_DIS_SWUS_", 5, 5, &umr_bitfield_default }, - { "VGA_REG_COHERENCY_DIS_", 6, 6, &umr_bitfield_default }, - { "VGA_MEM_COHERENCY_DIS_", 7, 7, &umr_bitfield_default }, - { "SET_AZ_TC_", 10, 12, &umr_bitfield_default }, - { "SET_MC_TC_", 13, 15, &umr_bitfield_default }, - { "ZERO_BE_WR_EN_", 16, 16, &umr_bitfield_default }, - { "ZERO_BE_RD_EN_", 17, 17, &umr_bitfield_default }, - { "RD_STALL_IO_WR_", 18, 18, &umr_bitfield_default }, - { "DEASRT_INTX_DSTATE_CHK_DIS_EP_", 19, 19, &umr_bitfield_default }, - { "DEASRT_INTX_DSTATE_CHK_DIS_DN_", 20, 20, &umr_bitfield_default }, - { "DEASRT_INTX_DSTATE_CHK_DIS_SWUS_", 21, 21, &umr_bitfield_default }, - { "DEASRT_INTX_IN_NOND0_EN_EP_", 22, 22, &umr_bitfield_default }, - { "DEASRT_INTX_IN_NOND0_EN_DN_", 23, 23, &umr_bitfield_default }, - { "UR_OVRD_FOR_ECRC_EN_", 24, 24, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_SCRATCH0[] = { - { "BIF_SCRATCH0_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_SCRATCH1[] = { - { "BIF_SCRATCH1_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBX_RESET_EN[] = { - { "COR_RESET_EN_", 0, 0, &umr_bitfield_default }, - { "REG_RESET_EN_", 1, 1, &umr_bitfield_default }, - { "STY_RESET_EN_", 2, 2, &umr_bitfield_default }, - { "FLR_TWICE_EN_", 8, 8, &umr_bitfield_default }, - { "RESET_ON_VFENABLE_LOW_EN_", 16, 16, &umr_bitfield_default }, -}; -static struct umr_bitfield mmMM_CFGREGS_CNTL[] = { - { "MM_CFG_FUNC_SEL_", 0, 2, &umr_bitfield_default }, - { "MM_CFG_DEV_SEL_", 6, 7, &umr_bitfield_default }, - { "MM_WR_TO_CFG_EN_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBX_RESET_CNTL[] = { - { "LINK_TRAIN_EN_", 0, 0, &umr_bitfield_default }, -}; -static struct umr_bitfield mmINTERRUPT_CNTL[] = { - { "IH_DUMMY_RD_OVERRIDE_", 0, 0, &umr_bitfield_default }, - { "IH_DUMMY_RD_EN_", 1, 1, &umr_bitfield_default }, - { "IH_REQ_NONSNOOP_EN_", 3, 3, &umr_bitfield_default }, - { "IH_INTR_DLY_CNTR_", 4, 7, &umr_bitfield_default }, - { "GEN_IH_INT_EN_", 8, 8, &umr_bitfield_default }, - { "BIF_RB_REQ_NONSNOOP_EN_", 15, 15, &umr_bitfield_default }, -}; -static struct umr_bitfield mmINTERRUPT_CNTL2[] = { - { "IH_DUMMY_RD_ADDR_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmCLKREQB_PAD_CNTL[] = { - { "CLKREQB_PAD_A_", 0, 0, &umr_bitfield_default }, - { "CLKREQB_PAD_SEL_", 1, 1, &umr_bitfield_default }, - { "CLKREQB_PAD_MODE_", 2, 2, &umr_bitfield_default }, - { "CLKREQB_PAD_SPARE_", 3, 4, &umr_bitfield_default }, - { "CLKREQB_PAD_SN0_", 5, 5, &umr_bitfield_default }, - { "CLKREQB_PAD_SN1_", 6, 6, &umr_bitfield_default }, - { "CLKREQB_PAD_SN2_", 7, 7, &umr_bitfield_default }, - { "CLKREQB_PAD_SN3_", 8, 8, &umr_bitfield_default }, - { "CLKREQB_PAD_SLEWN_", 9, 9, &umr_bitfield_default }, - { "CLKREQB_PAD_WAKE_", 10, 10, &umr_bitfield_default }, - { "CLKREQB_PAD_SCHMEN_", 11, 11, &umr_bitfield_default }, - { "CLKREQB_PAD_CNTL_EN_", 12, 12, &umr_bitfield_default }, - { "CLKREQB_PAD_Y_", 13, 13, &umr_bitfield_default }, - { "CLKREQB_PERF_COUNTER_UPPER_", 24, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmCLKREQB_PERF_COUNTER[] = { - { "CLKREQB_PERF_COUNTER_LOWER_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_CLK_CTRL[] = { - { "BIF_XSTCLK_READY_", 0, 0, &umr_bitfield_default }, - { "BACO_XSTCLK_SWITCH_BYPASS_", 1, 1, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_FEATURES_CONTROL_MISC[] = { - { "MST_BIF_REQ_EP_DIS_", 0, 0, &umr_bitfield_default }, - { "SLV_BIF_CPL_EP_DIS_", 1, 1, &umr_bitfield_default }, - { "BIF_SLV_REQ_EP_DIS_", 2, 2, &umr_bitfield_default }, - { "BIF_MST_CPL_EP_DIS_", 3, 3, &umr_bitfield_default }, - { "MC_BIF_REQ_ID_ROUTING_DIS_", 9, 9, &umr_bitfield_default }, - { "AZ_BIF_REQ_ID_ROUTING_DIS_", 10, 10, &umr_bitfield_default }, - { "ATC_PRG_RESP_PASID_UR_EN_", 11, 11, &umr_bitfield_default }, - { "BIF_RB_SET_OVERFLOW_EN_", 12, 12, &umr_bitfield_default }, - { "ATOMIC_ERR_INT_DIS_", 13, 13, &umr_bitfield_default }, - { "BME_HDL_NONVIR_EN_", 15, 15, &umr_bitfield_default }, - { "FLR_MST_PEND_CHK_DIS_", 17, 17, &umr_bitfield_default }, - { "FLR_SLV_PEND_CHK_DIS_", 18, 18, &umr_bitfield_default }, - { "DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR_", 24, 24, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_DOORBELL_CNTL[] = { - { "SELF_RING_DIS_", 0, 0, &umr_bitfield_default }, - { "TRANS_CHECK_DIS_", 1, 1, &umr_bitfield_default }, - { "UNTRANS_LBACK_EN_", 2, 2, &umr_bitfield_default }, - { "NON_CONSECUTIVE_BE_ZERO_DIS_", 3, 3, &umr_bitfield_default }, - { "DOORBELL_MONITOR_EN_", 4, 4, &umr_bitfield_default }, - { "DB_MNTR_INTGEN_DIS_", 24, 24, &umr_bitfield_default }, - { "DB_MNTR_INTGEN_MODE_0_", 25, 25, &umr_bitfield_default }, - { "DB_MNTR_INTGEN_MODE_1_", 26, 26, &umr_bitfield_default }, - { "DB_MNTR_INTGEN_MODE_2_", 27, 27, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_DOORBELL_INT_CNTL[] = { - { "DOORBELL_INTERRUPT_STATUS_", 0, 0, &umr_bitfield_default }, - { "IOHC_RAS_INTERRUPT_STATUS_", 1, 1, &umr_bitfield_default }, - { "DOORBELL_INTERRUPT_CLEAR_", 16, 16, &umr_bitfield_default }, - { "IOHC_RAS_INTERRUPT_CLEAR_", 17, 17, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_SLVARB_MODE[] = { - { "SLVARB_MODE_", 0, 1, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_FB_EN[] = { - { "FB_READ_EN_", 0, 0, &umr_bitfield_default }, - { "FB_WRITE_EN_", 1, 1, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_BUSY_DELAY_CNTR[] = { - { "DELAY_CNT_", 0, 5, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_PERFMON_CNTL[] = { - { "PERFCOUNTER_EN_", 0, 0, &umr_bitfield_default }, - { "PERFCOUNTER_RESET0_", 1, 1, &umr_bitfield_default }, - { "PERFCOUNTER_RESET1_", 2, 2, &umr_bitfield_default }, - { "PERF_SEL0_", 8, 12, &umr_bitfield_default }, - { "PERF_SEL1_", 13, 17, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_PERFCOUNTER0_RESULT[] = { - { "PERFCOUNTER_RESULT_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_PERFCOUNTER1_RESULT[] = { - { "PERFCOUNTER_RESULT_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_MST_TRANS_PENDING_VF[] = { - { "BIF_MST_TRANS_PENDING_", 0, 15, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_SLV_TRANS_PENDING_VF[] = { - { "BIF_SLV_TRANS_PENDING_", 0, 15, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBACO_CNTL[] = { - { "BACO_EN_", 0, 0, &umr_bitfield_default }, - { "BACO_BIF_LCLK_SWITCH_", 1, 1, &umr_bitfield_default }, - { "BACO_DUMMY_EN_", 2, 2, &umr_bitfield_default }, - { "BACO_POWER_OFF_", 3, 3, &umr_bitfield_default }, - { "BACO_DSTATE_BYPASS_", 5, 5, &umr_bitfield_default }, - { "BACO_RST_INTR_MASK_", 6, 6, &umr_bitfield_default }, - { "BACO_MODE_", 8, 8, &umr_bitfield_default }, - { "RCU_BIF_CONFIG_DONE_", 9, 9, &umr_bitfield_default }, - { "BACO_AUTO_EXIT_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_BACO_EXIT_TIME0[] = { - { "BACO_EXIT_PXEN_CLR_TIMER_", 0, 19, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_BACO_EXIT_TIMER1[] = { - { "BACO_EXIT_SIDEBAND_TIMER_", 0, 19, &umr_bitfield_default }, - { "BACO_HW_EXIT_DIS_", 26, 26, &umr_bitfield_default }, - { "PX_EN_OE_IN_PX_EN_HIGH_", 27, 27, &umr_bitfield_default }, - { "PX_EN_OE_IN_PX_EN_LOW_", 28, 28, &umr_bitfield_default }, - { "BACO_MODE_SEL_", 29, 30, &umr_bitfield_default }, - { "AUTO_BACO_EXIT_CLR_BY_HW_DIS_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_BACO_EXIT_TIMER2[] = { - { "BACO_EXIT_LCLK_BAK_TIMER_", 0, 19, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_BACO_EXIT_TIMER3[] = { - { "BACO_EXIT_DUMMY_EN_CLR_TIMER_", 0, 19, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_BACO_EXIT_TIMER4[] = { - { "BACO_EXIT_BACO_EN_CLR_TIMER_", 0, 19, &umr_bitfield_default }, -}; -static struct umr_bitfield mmMEM_TYPE_CNTL[] = { - { "BF_MEM_PHY_G5_G3_", 0, 0, &umr_bitfield_default }, -}; -static struct umr_bitfield mmSMU_BIF_VDDGFX_PWR_STATUS[] = { - { "VDDGFX_GFX_PWR_OFF_", 0, 0, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_VDDGFX_GFX0_LOWER[] = { - { "VDDGFX_GFX0_REG_LOWER_", 2, 17, &umr_bitfield_default }, - { "VDDGFX_GFX0_REG_CMP_EN_", 30, 30, &umr_bitfield_default }, - { "VDDGFX_GFX0_REG_STALL_EN_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_VDDGFX_GFX0_UPPER[] = { - { "VDDGFX_GFX0_REG_UPPER_", 2, 17, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_VDDGFX_GFX1_LOWER[] = { - { "VDDGFX_GFX1_REG_LOWER_", 2, 17, &umr_bitfield_default }, - { "VDDGFX_GFX1_REG_CMP_EN_", 30, 30, &umr_bitfield_default }, - { "VDDGFX_GFX1_REG_STALL_EN_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_VDDGFX_GFX1_UPPER[] = { - { "VDDGFX_GFX1_REG_UPPER_", 2, 17, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_VDDGFX_GFX2_LOWER[] = { - { "VDDGFX_GFX2_REG_LOWER_", 2, 17, &umr_bitfield_default }, - { "VDDGFX_GFX2_REG_CMP_EN_", 30, 30, &umr_bitfield_default }, - { "VDDGFX_GFX2_REG_STALL_EN_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_VDDGFX_GFX2_UPPER[] = { - { "VDDGFX_GFX2_REG_UPPER_", 2, 17, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_VDDGFX_GFX3_LOWER[] = { - { "VDDGFX_GFX3_REG_LOWER_", 2, 17, &umr_bitfield_default }, - { "VDDGFX_GFX3_REG_CMP_EN_", 30, 30, &umr_bitfield_default }, - { "VDDGFX_GFX3_REG_STALL_EN_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_VDDGFX_GFX3_UPPER[] = { - { "VDDGFX_GFX3_REG_UPPER_", 2, 17, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_VDDGFX_GFX4_LOWER[] = { - { "VDDGFX_GFX4_REG_LOWER_", 2, 17, &umr_bitfield_default }, - { "VDDGFX_GFX4_REG_CMP_EN_", 30, 30, &umr_bitfield_default }, - { "VDDGFX_GFX4_REG_STALL_EN_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_VDDGFX_GFX4_UPPER[] = { - { "VDDGFX_GFX4_REG_UPPER_", 2, 17, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_VDDGFX_GFX5_LOWER[] = { - { "VDDGFX_GFX5_REG_LOWER_", 2, 17, &umr_bitfield_default }, - { "VDDGFX_GFX5_REG_CMP_EN_", 30, 30, &umr_bitfield_default }, - { "VDDGFX_GFX5_REG_STALL_EN_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_VDDGFX_GFX5_UPPER[] = { - { "VDDGFX_GFX5_REG_UPPER_", 2, 17, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_VDDGFX_RSV1_LOWER[] = { - { "VDDGFX_RSV1_REG_LOWER_", 2, 17, &umr_bitfield_default }, - { "VDDGFX_RSV1_REG_CMP_EN_", 30, 30, &umr_bitfield_default }, - { "VDDGFX_RSV1_REG_STALL_EN_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_VDDGFX_RSV1_UPPER[] = { - { "VDDGFX_RSV1_REG_UPPER_", 2, 17, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_VDDGFX_RSV2_LOWER[] = { - { "VDDGFX_RSV2_REG_LOWER_", 2, 17, &umr_bitfield_default }, - { "VDDGFX_RSV2_REG_CMP_EN_", 30, 30, &umr_bitfield_default }, - { "VDDGFX_RSV2_REG_STALL_EN_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_VDDGFX_RSV2_UPPER[] = { - { "VDDGFX_RSV2_REG_UPPER_", 2, 17, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_VDDGFX_RSV3_LOWER[] = { - { "VDDGFX_RSV3_REG_LOWER_", 2, 17, &umr_bitfield_default }, - { "VDDGFX_RSV3_REG_CMP_EN_", 30, 30, &umr_bitfield_default }, - { "VDDGFX_RSV3_REG_STALL_EN_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_VDDGFX_RSV3_UPPER[] = { - { "VDDGFX_RSV3_REG_UPPER_", 2, 17, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_VDDGFX_RSV4_LOWER[] = { - { "VDDGFX_RSV4_REG_LOWER_", 2, 17, &umr_bitfield_default }, - { "VDDGFX_RSV4_REG_CMP_EN_", 30, 30, &umr_bitfield_default }, - { "VDDGFX_RSV4_REG_STALL_EN_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_VDDGFX_RSV4_UPPER[] = { - { "VDDGFX_RSV4_REG_UPPER_", 2, 17, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_VDDGFX_FB_CMP[] = { - { "VDDGFX_FB_HDP_CMP_EN_", 0, 0, &umr_bitfield_default }, - { "VDDGFX_FB_HDP_STALL_EN_", 1, 1, &umr_bitfield_default }, - { "VDDGFX_FB_XDMA_CMP_EN_", 2, 2, &umr_bitfield_default }, - { "VDDGFX_FB_XDMA_STALL_EN_", 3, 3, &umr_bitfield_default }, - { "VDDGFX_FB_VGA_CMP_EN_", 4, 4, &umr_bitfield_default }, - { "VDDGFX_FB_VGA_STALL_EN_", 5, 5, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_DOORBELL_GBLAPER1_LOWER[] = { - { "DOORBELL_GBLAPER1_LOWER_", 2, 11, &umr_bitfield_default }, - { "DOORBELL_GBLAPER1_EN_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_DOORBELL_GBLAPER1_UPPER[] = { - { "DOORBELL_GBLAPER1_UPPER_", 2, 11, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_DOORBELL_GBLAPER2_LOWER[] = { - { "DOORBELL_GBLAPER2_LOWER_", 2, 11, &umr_bitfield_default }, - { "DOORBELL_GBLAPER2_EN_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_DOORBELL_GBLAPER2_UPPER[] = { - { "DOORBELL_GBLAPER2_UPPER_", 2, 11, &umr_bitfield_default }, -}; -static struct umr_bitfield mmREMAP_HDP_MEM_FLUSH_CNTL[] = { - { "ADDRESS_", 2, 18, &umr_bitfield_default }, -}; -static struct umr_bitfield mmREMAP_HDP_REG_FLUSH_CNTL[] = { - { "ADDRESS_", 2, 18, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_RB_CNTL[] = { - { "RB_ENABLE_", 0, 0, &umr_bitfield_default }, - { "RB_SIZE_", 1, 5, &umr_bitfield_default }, - { "WPTR_WRITEBACK_ENABLE_", 8, 8, &umr_bitfield_default }, - { "WPTR_WRITEBACK_TIMER_", 9, 13, &umr_bitfield_default }, - { "BIF_RB_TRAN_", 17, 17, &umr_bitfield_default }, - { "WPTR_OVERFLOW_CLEAR_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_RB_BASE[] = { - { "ADDR_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_RB_RPTR[] = { - { "OFFSET_", 2, 17, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_RB_WPTR[] = { - { "BIF_RB_OVERFLOW_", 0, 0, &umr_bitfield_default }, - { "OFFSET_", 2, 17, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_RB_WPTR_ADDR_HI[] = { - { "ADDR_", 0, 7, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_RB_WPTR_ADDR_LO[] = { - { "ADDR_", 2, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmMAILBOX_INDEX[] = { - { "MAILBOX_INDEX_", 0, 4, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_GPUIOV_RESET_NOTIFICATION[] = { - { "RESET_NOTIFICATION_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_UVD_GPUIOV_CFG_SIZE[] = { - { "UVD_GPUIOV_CFG_SIZE_", 0, 3, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_VCE_GPUIOV_CFG_SIZE[] = { - { "VCE_GPUIOV_CFG_SIZE_", 0, 3, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_GFX_SDMA_GPUIOV_CFG_SIZE[] = { - { "GFX_SDMA_GPUIOV_CFG_SIZE_", 0, 3, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_GMI_WRR_WEIGHT[] = { - { "GMI_REQ_REALTIME_WEIGHT_", 0, 7, &umr_bitfield_default }, - { "GMI_REQ_NORM_P_WEIGHT_", 8, 15, &umr_bitfield_default }, - { "GMI_REQ_NORM_NP_WEIGHT_", 16, 23, &umr_bitfield_default }, -}; -static struct umr_bitfield mmNBIF_STRAP_WRITE_CTRL[] = { - { "NBIF_STRAP_WRITE_ONCE_ENABLE_", 0, 0, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_PERSTB_PAD_CNTL[] = { - { "PERSTB_PAD_CNTL_", 0, 15, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_PX_EN_PAD_CNTL[] = { - { "PX_EN_PAD_CNTL_", 0, 7, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_REFPADKIN_PAD_CNTL[] = { - { "REFPADKIN_PAD_CNTL_", 0, 7, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_CLKREQB_PAD_CNTL[] = { - { "CLKREQB_PAD_CNTL_", 0, 23, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_BACO_CNTL_MISC[] = { - { "BIF_ROM_REQ_DIS_", 0, 0, &umr_bitfield_default }, - { "BIF_AZ_REQ_DIS_", 1, 1, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_RESET_EN[] = { - { "DB_APER_RESET_EN_", 15, 15, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_VDM_SUPPORT[] = { - { "MCTP_SUPPORT_", 0, 0, &umr_bitfield_default }, - { "AMPTP_SUPPORT_", 1, 1, &umr_bitfield_default }, - { "OTHER_VDM_SUPPORT_", 2, 2, &umr_bitfield_default }, - { "ROUTE_TO_RC_CHECK_IN_RCMODE_", 3, 3, &umr_bitfield_default }, - { "ROUTE_BROADCAST_CHECK_IN_RCMODE_", 4, 4, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_PEER_REG_RANGE0[] = { - { "START_ADDR_", 0, 15, &umr_bitfield_default }, - { "END_ADDR_", 16, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_PEER_REG_RANGE1[] = { - { "START_ADDR_", 0, 15, &umr_bitfield_default }, - { "END_ADDR_", 16, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_BUS_CNTL[] = { - { "PMI_IO_DIS_", 2, 2, &umr_bitfield_default }, - { "PMI_MEM_DIS_", 3, 3, &umr_bitfield_default }, - { "PMI_BM_DIS_", 4, 4, &umr_bitfield_default }, - { "PMI_IO_DIS_DN_", 5, 5, &umr_bitfield_default }, - { "PMI_MEM_DIS_DN_", 6, 6, &umr_bitfield_default }, - { "PMI_IO_DIS_UP_", 7, 7, &umr_bitfield_default }, - { "PMI_MEM_DIS_UP_", 8, 8, &umr_bitfield_default }, - { "ROOT_ERR_LOG_ON_EVENT_", 12, 12, &umr_bitfield_default }, - { "HOST_CPL_POISONED_LOG_IN_RC_", 13, 13, &umr_bitfield_default }, - { "DN_SEC_SIG_CPLCA_WITH_EP_ERR_", 16, 16, &umr_bitfield_default }, - { "DN_SEC_RCV_CPLCA_WITH_EP_ERR_", 17, 17, &umr_bitfield_default }, - { "DN_SEC_RCV_CPLUR_WITH_EP_ERR_", 18, 18, &umr_bitfield_default }, - { "DN_PRI_SIG_CPLCA_WITH_EP_ERR_", 19, 19, &umr_bitfield_default }, - { "DN_PRI_RCV_CPLCA_WITH_EP_ERR_", 20, 20, &umr_bitfield_default }, - { "DN_PRI_RCV_CPLUR_WITH_EP_ERR_", 21, 21, &umr_bitfield_default }, - { "MAX_PAYLOAD_SIZE_MODE_", 24, 24, &umr_bitfield_default }, - { "PRIV_MAX_PAYLOAD_SIZE_", 25, 27, &umr_bitfield_default }, - { "MAX_READ_REQUEST_SIZE_MODE_", 28, 28, &umr_bitfield_default }, - { "PRIV_MAX_READ_REQUEST_SIZE_", 29, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_CONFIG_CNTL[] = { - { "CFG_VGA_RAM_EN_", 0, 0, &umr_bitfield_default }, - { "GENMO_MONO_ADDRESS_B_", 2, 2, &umr_bitfield_default }, - { "GRPH_ADRSEL_", 3, 4, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_CONFIG_F0_BASE[] = { - { "F0_BASE_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_CONFIG_APER_SIZE[] = { - { "APER_SIZE_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_CONFIG_REG_APER_SIZE[] = { - { "REG_APER_SIZE_", 0, 19, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_XDMA_LO[] = { - { "BIF_XDMA_LOWER_BOUND_", 0, 28, &umr_bitfield_default }, - { "BIF_XDMA_APER_EN_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_XDMA_HI[] = { - { "BIF_XDMA_UPPER_BOUND_", 0, 28, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_FEATURES_CONTROL_MISC[] = { - { "UR_PSN_PKT_REPORT_POISON_DIS_", 4, 4, &umr_bitfield_default }, - { "POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS_", 5, 5, &umr_bitfield_default }, - { "POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS_", 6, 6, &umr_bitfield_default }, - { "ATC_PRG_RESP_PASID_UR_EN_", 8, 8, &umr_bitfield_default }, - { "RX_IGNORE_TRANSMRD_UR_", 9, 9, &umr_bitfield_default }, - { "RX_IGNORE_TRANSMWR_UR_", 10, 10, &umr_bitfield_default }, - { "RX_IGNORE_ATSTRANSREQ_UR_", 11, 11, &umr_bitfield_default }, - { "RX_IGNORE_PAGEREQMSG_UR_", 12, 12, &umr_bitfield_default }, - { "RX_IGNORE_INVCPL_UR_", 13, 13, &umr_bitfield_default }, - { "CLR_MSI_X_PENDING_WHEN_DISABLED_DIS_", 14, 14, &umr_bitfield_default }, - { "CHECK_BME_ON_PENDING_PKT_GEN_DIS_", 15, 15, &umr_bitfield_default }, - { "PSN_CHECK_ON_PAYLOAD_DIS_", 16, 16, &umr_bitfield_default }, - { "CLR_MSI_PENDING_ON_MULTIEN_DIS_", 17, 17, &umr_bitfield_default }, - { "SET_DEVICE_ERR_FOR_ECRC_EN_", 18, 18, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_BUSNUM_CNTL1[] = { - { "ID_MASK_", 0, 7, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_BUSNUM_LIST0[] = { - { "ID0_", 0, 7, &umr_bitfield_default }, - { "ID1_", 8, 15, &umr_bitfield_default }, - { "ID2_", 16, 23, &umr_bitfield_default }, - { "ID3_", 24, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_BUSNUM_LIST1[] = { - { "ID4_", 0, 7, &umr_bitfield_default }, - { "ID5_", 8, 15, &umr_bitfield_default }, - { "ID6_", 16, 23, &umr_bitfield_default }, - { "ID7_", 24, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_BUSNUM_CNTL2[] = { - { "AUTOUPDATE_SEL_", 0, 7, &umr_bitfield_default }, - { "AUTOUPDATE_EN_", 8, 8, &umr_bitfield_default }, - { "HDPREG_CNTL_", 16, 16, &umr_bitfield_default }, - { "ERROR_MULTIPLE_ID_MATCH_", 17, 17, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_CAPTURE_HOST_BUSNUM[] = { - { "CHECK_EN_", 0, 0, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_HOST_BUSNUM[] = { - { "HOST_ID_", 0, 15, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_PEER0_FB_OFFSET_HI[] = { - { "PEER0_FB_OFFSET_HI_", 0, 19, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_PEER0_FB_OFFSET_LO[] = { - { "PEER0_FB_OFFSET_LO_", 0, 19, &umr_bitfield_default }, - { "PEER0_FB_EN_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_PEER1_FB_OFFSET_HI[] = { - { "PEER1_FB_OFFSET_HI_", 0, 19, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_PEER1_FB_OFFSET_LO[] = { - { "PEER1_FB_OFFSET_LO_", 0, 19, &umr_bitfield_default }, - { "PEER1_FB_EN_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_PEER2_FB_OFFSET_HI[] = { - { "PEER2_FB_OFFSET_HI_", 0, 19, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_PEER2_FB_OFFSET_LO[] = { - { "PEER2_FB_OFFSET_LO_", 0, 19, &umr_bitfield_default }, - { "PEER2_FB_EN_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_PEER3_FB_OFFSET_HI[] = { - { "PEER3_FB_OFFSET_HI_", 0, 19, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_PEER3_FB_OFFSET_LO[] = { - { "PEER3_FB_OFFSET_LO_", 0, 19, &umr_bitfield_default }, - { "PEER3_FB_EN_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEVFUNCNUM_LIST0[] = { - { "DEVFUNC_ID0_", 0, 7, &umr_bitfield_default }, - { "DEVFUNC_ID1_", 8, 15, &umr_bitfield_default }, - { "DEVFUNC_ID2_", 16, 23, &umr_bitfield_default }, - { "DEVFUNC_ID3_", 24, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEVFUNCNUM_LIST1[] = { - { "DEVFUNC_ID4_", 0, 7, &umr_bitfield_default }, - { "DEVFUNC_ID5_", 8, 15, &umr_bitfield_default }, - { "DEVFUNC_ID6_", 16, 23, &umr_bitfield_default }, - { "DEVFUNC_ID7_", 24, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_LINK_CNTL[] = { - { "LINK_DOWN_EXIT_", 0, 0, &umr_bitfield_default }, - { "LINK_DOWN_ENTRY_", 8, 8, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_CMN_LINK_CNTL[] = { - { "BLOCK_PME_ON_L0S_DIS_", 0, 0, &umr_bitfield_default }, - { "BLOCK_PME_ON_L1_DIS_", 1, 1, &umr_bitfield_default }, - { "BLOCK_PME_ON_LDN_DIS_", 2, 2, &umr_bitfield_default }, - { "PM_L1_IDLE_CHECK_DMA_EN_", 3, 3, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_EP_REQUESTERID_RESTORE[] = { - { "EP_REQID_BUS_", 0, 7, &umr_bitfield_default }, - { "EP_REQID_DEV_", 8, 12, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_LTR_LSWITCH_CNTL[] = { - { "LSWITCH_LATENCY_VALUE_", 0, 9, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_MH_ARB_CNTL[] = { - { "MH_ARB_MODE_", 0, 0, &umr_bitfield_default }, - { "MH_ARB_FIX_PRIORITY_", 1, 14, &umr_bitfield_default }, -}; -static struct umr_bitfield mmGFXMSIX_VECT0_ADDR_LO[] = { - { "MSG_ADDR_LO_", 2, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmGFXMSIX_VECT0_ADDR_HI[] = { - { "MSG_ADDR_HI_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmGFXMSIX_VECT0_MSG_DATA[] = { - { "MSG_DATA_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmGFXMSIX_VECT0_CONTROL[] = { - { "MASK_BIT_", 0, 0, &umr_bitfield_default }, -}; -static struct umr_bitfield mmGFXMSIX_VECT1_ADDR_LO[] = { - { "MSG_ADDR_LO_", 2, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmGFXMSIX_VECT1_ADDR_HI[] = { - { "MSG_ADDR_HI_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmGFXMSIX_VECT1_MSG_DATA[] = { - { "MSG_DATA_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmGFXMSIX_VECT1_CONTROL[] = { - { "MASK_BIT_", 0, 0, &umr_bitfield_default }, -}; -static struct umr_bitfield mmGFXMSIX_VECT2_ADDR_LO[] = { - { "MSG_ADDR_LO_", 2, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmGFXMSIX_VECT2_ADDR_HI[] = { - { "MSG_ADDR_HI_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmGFXMSIX_VECT2_MSG_DATA[] = { - { "MSG_DATA_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmGFXMSIX_VECT2_CONTROL[] = { - { "MASK_BIT_", 0, 0, &umr_bitfield_default }, -}; -static struct umr_bitfield mmGFXMSIX_PBA[] = { - { "MSIX_PENDING_BITS_0_", 0, 0, &umr_bitfield_default }, - { "MSIX_PENDING_BITS_1_", 1, 1, &umr_bitfield_default }, - { "MSIX_PENDING_BITS_2_", 2, 2, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_PORT_STRAP0[] = { - { "STRAP_ARI_EN_DN_DEV0_", 1, 1, &umr_bitfield_default }, - { "STRAP_ACS_EN_DN_DEV0_", 2, 2, &umr_bitfield_default }, - { "STRAP_AER_EN_DN_DEV0_", 3, 3, &umr_bitfield_default }, - { "STRAP_CPL_ABORT_ERR_EN_DN_DEV0_", 4, 4, &umr_bitfield_default }, - { "STRAP_DEVICE_ID_DN_DEV0_", 5, 20, &umr_bitfield_default }, - { "STRAP_INTERRUPT_PIN_DN_DEV0_", 21, 23, &umr_bitfield_default }, - { "STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0_", 24, 24, &umr_bitfield_default }, - { "STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0_", 25, 27, &umr_bitfield_default }, - { "STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0_", 28, 30, &umr_bitfield_default }, - { "STRAP_EPF0_DUMMY_EN_DEV0_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_PORT_STRAP1[] = { - { "STRAP_SUBSYS_ID_DN_DEV0_", 0, 15, &umr_bitfield_default }, - { "STRAP_SUBSYS_VEN_ID_DN_DEV0_", 16, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_PORT_STRAP2[] = { - { "STRAP_DE_EMPHASIS_SEL_DN_DEV0_", 0, 0, &umr_bitfield_default }, - { "STRAP_DSN_EN_DN_DEV0_", 1, 1, &umr_bitfield_default }, - { "STRAP_E2E_PREFIX_EN_DEV0_", 2, 2, &umr_bitfield_default }, - { "STRAP_ECN1P1_EN_DEV0_", 3, 3, &umr_bitfield_default }, - { "STRAP_ECRC_CHECK_EN_DEV0_", 4, 4, &umr_bitfield_default }, - { "STRAP_ECRC_GEN_EN_DEV0_", 5, 5, &umr_bitfield_default }, - { "STRAP_ERR_REPORTING_DIS_DEV0_", 6, 6, &umr_bitfield_default }, - { "STRAP_EXTENDED_FMT_SUPPORTED_DEV0_", 7, 7, &umr_bitfield_default }, - { "STRAP_EXTENDED_TAG_ECN_EN_DEV0_", 8, 8, &umr_bitfield_default }, - { "STRAP_EXT_VC_COUNT_DN_DEV0_", 9, 11, &umr_bitfield_default }, - { "STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0_", 12, 12, &umr_bitfield_default }, - { "STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0_", 13, 13, &umr_bitfield_default }, - { "STRAP_GEN2_COMPLIANCE_DEV0_", 14, 14, &umr_bitfield_default }, - { "STRAP_GEN2_EN_DEV0_", 15, 15, &umr_bitfield_default }, - { "STRAP_GEN3_COMPLIANCE_DEV0_", 16, 16, &umr_bitfield_default }, - { "STRAP_TARGET_LINK_SPEED_DEV0_", 17, 18, &umr_bitfield_default }, - { "STRAP_INTERNAL_ERR_EN_DEV0_", 19, 19, &umr_bitfield_default }, - { "STRAP_L0S_ACCEPTABLE_LATENCY_DEV0_", 20, 22, &umr_bitfield_default }, - { "STRAP_L0S_EXIT_LATENCY_DEV0_", 23, 25, &umr_bitfield_default }, - { "STRAP_L1_ACCEPTABLE_LATENCY_DEV0_", 26, 28, &umr_bitfield_default }, - { "STRAP_L1_EXIT_LATENCY_DEV0_", 29, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_PORT_STRAP3[] = { - { "STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0_", 0, 0, &umr_bitfield_default }, - { "STRAP_LTR_EN_DEV0_", 1, 1, &umr_bitfield_default }, - { "STRAP_LTR_EN_DN_DEV0_", 2, 2, &umr_bitfield_default }, - { "STRAP_MAX_PAYLOAD_SUPPORT_DEV0_", 3, 5, &umr_bitfield_default }, - { "STRAP_MSI_EN_DN_DEV0_", 6, 6, &umr_bitfield_default }, - { "STRAP_MSTCPL_TIMEOUT_EN_DEV0_", 7, 7, &umr_bitfield_default }, - { "STRAP_NO_SOFT_RESET_DN_DEV0_", 8, 8, &umr_bitfield_default }, - { "STRAP_OBFF_SUPPORTED_DEV0_", 9, 10, &umr_bitfield_default }, - { "STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0_", 11, 13, &umr_bitfield_default }, - { "STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0_", 14, 17, &umr_bitfield_default }, - { "STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0_", 18, 20, &umr_bitfield_default }, - { "STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0_", 21, 24, &umr_bitfield_default }, - { "STRAP_PM_SUPPORT_DEV0_", 25, 26, &umr_bitfield_default }, - { "STRAP_PM_SUPPORT_DN_DEV0_", 27, 28, &umr_bitfield_default }, - { "STRAP_ATOMIC_EN_DN_DEV0_", 29, 29, &umr_bitfield_default }, - { "STRAP_VENDOR_ID_BIT_DN_DEV0_", 30, 30, &umr_bitfield_default }, - { "STRAP_PMC_DSI_DN_DEV0_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_PORT_STRAP4[] = { - { "STRAP_PWR_BUDGET_DATA_8T0_0_DEV0_", 0, 7, &umr_bitfield_default }, - { "STRAP_PWR_BUDGET_DATA_8T0_1_DEV0_", 8, 15, &umr_bitfield_default }, - { "STRAP_PWR_BUDGET_DATA_8T0_2_DEV0_", 16, 23, &umr_bitfield_default }, - { "STRAP_PWR_BUDGET_DATA_8T0_3_DEV0_", 24, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_PORT_STRAP5[] = { - { "STRAP_PWR_BUDGET_DATA_8T0_4_DEV0_", 0, 7, &umr_bitfield_default }, - { "STRAP_PWR_BUDGET_DATA_8T0_5_DEV0_", 8, 15, &umr_bitfield_default }, - { "STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0_", 16, 16, &umr_bitfield_default }, - { "STRAP_ATOMIC_64BIT_EN_DN_DEV0_", 17, 17, &umr_bitfield_default }, - { "STRAP_ATOMIC_ROUTING_EN_DEV0_", 18, 18, &umr_bitfield_default }, - { "STRAP_VC_EN_DN_DEV0_", 19, 19, &umr_bitfield_default }, - { "STRAP_TwoVC_EN_DEV0_", 20, 20, &umr_bitfield_default }, - { "STRAP_TwoVC_EN_DN_DEV0_", 21, 21, &umr_bitfield_default }, - { "STRAP_ACS_SOURCE_VALIDATION_DN_DEV0_", 23, 23, &umr_bitfield_default }, - { "STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0_", 24, 24, &umr_bitfield_default }, - { "STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0_", 25, 25, &umr_bitfield_default }, - { "STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0_", 26, 26, &umr_bitfield_default }, - { "STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0_", 27, 27, &umr_bitfield_default }, - { "STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0_", 28, 28, &umr_bitfield_default }, - { "STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0_", 29, 29, &umr_bitfield_default }, - { "STRAP_MSI_MAP_EN_DEV0_", 30, 30, &umr_bitfield_default }, - { "STRAP_SSID_EN_DEV0_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_PORT_STRAP6[] = { - { "STRAP_CFG_CRS_EN_DEV0_", 0, 0, &umr_bitfield_default }, - { "STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0_", 1, 1, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_PORT_STRAP7[] = { - { "STRAP_PORT_NUMBER_DEV0_", 0, 7, &umr_bitfield_default }, - { "STRAP_MAJOR_REV_ID_DN_DEV0_", 8, 11, &umr_bitfield_default }, - { "STRAP_MINOR_REV_ID_DN_DEV0_", 12, 15, &umr_bitfield_default }, - { "STRAP_RP_BUSNUM_DEV0_", 16, 23, &umr_bitfield_default }, - { "STRAP_DN_DEVNUM_DEV0_", 24, 28, &umr_bitfield_default }, - { "STRAP_DN_FUNCID_DEV0_", 29, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_EPF0_STRAP0[] = { - { "STRAP_DEVICE_ID_DEV0_F0_", 0, 15, &umr_bitfield_default }, - { "STRAP_MAJOR_REV_ID_DEV0_F0_", 16, 19, &umr_bitfield_default }, - { "STRAP_MINOR_REV_ID_DEV0_F0_", 20, 23, &umr_bitfield_default }, - { "STRAP_ATI_REV_ID_DEV0_F0_", 24, 27, &umr_bitfield_default }, - { "STRAP_FUNC_EN_DEV0_F0_", 28, 28, &umr_bitfield_default }, - { "STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_", 29, 29, &umr_bitfield_default }, - { "STRAP_D1_SUPPORT_DEV0_F0_", 30, 30, &umr_bitfield_default }, - { "STRAP_D2_SUPPORT_DEV0_F0_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_EPF0_STRAP1[] = { - { "STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0_", 0, 15, &umr_bitfield_default }, - { "STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0_", 16, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_EPF0_STRAP13[] = { - { "STRAP_CLASS_CODE_PIF_DEV0_F0_", 0, 7, &umr_bitfield_default }, - { "STRAP_CLASS_CODE_SUB_DEV0_F0_", 8, 15, &umr_bitfield_default }, - { "STRAP_CLASS_CODE_BASE_DEV0_F0_", 16, 23, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_EPF0_STRAP2[] = { - { "STRAP_SRIOV_EN_DEV0_F0_", 0, 0, &umr_bitfield_default }, - { "STRAP_SRIOV_TOTAL_VFS_DEV0_F0_", 1, 5, &umr_bitfield_default }, - { "STRAP_64BAR_DIS_DEV0_F0_", 6, 6, &umr_bitfield_default }, - { "STRAP_NO_SOFT_RESET_DEV0_F0_", 7, 7, &umr_bitfield_default }, - { "STRAP_RESIZE_BAR_EN_DEV0_F0_", 8, 8, &umr_bitfield_default }, - { "STRAP_MAX_PASID_WIDTH_DEV0_F0_", 9, 13, &umr_bitfield_default }, - { "STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0_", 14, 14, &umr_bitfield_default }, - { "STRAP_ARI_EN_DEV0_F0_", 15, 15, &umr_bitfield_default }, - { "STRAP_AER_EN_DEV0_F0_", 16, 16, &umr_bitfield_default }, - { "STRAP_ACS_EN_DEV0_F0_", 17, 17, &umr_bitfield_default }, - { "STRAP_ATS_EN_DEV0_F0_", 18, 18, &umr_bitfield_default }, - { "STRAP_CPL_ABORT_ERR_EN_DEV0_F0_", 20, 20, &umr_bitfield_default }, - { "STRAP_DPA_EN_DEV0_F0_", 21, 21, &umr_bitfield_default }, - { "STRAP_DSN_EN_DEV0_F0_", 22, 22, &umr_bitfield_default }, - { "STRAP_VC_EN_DEV0_F0_", 23, 23, &umr_bitfield_default }, - { "STRAP_MSI_MULTI_CAP_DEV0_F0_", 24, 26, &umr_bitfield_default }, - { "STRAP_PAGE_REQ_EN_DEV0_F0_", 27, 27, &umr_bitfield_default }, - { "STRAP_PASID_EN_DEV0_F0_", 28, 28, &umr_bitfield_default }, - { "STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0_", 29, 29, &umr_bitfield_default }, - { "STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0_", 30, 30, &umr_bitfield_default }, - { "STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_EPF0_STRAP3[] = { - { "STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0_", 0, 0, &umr_bitfield_default }, - { "STRAP_PWR_EN_DEV0_F0_", 1, 1, &umr_bitfield_default }, - { "STRAP_SUBSYS_ID_DEV0_F0_", 2, 17, &umr_bitfield_default }, - { "STRAP_MSI_EN_DEV0_F0_", 18, 18, &umr_bitfield_default }, - { "STRAP_MSI_CLR_PENDING_EN_DEV0_F0_", 19, 19, &umr_bitfield_default }, - { "STRAP_MSIX_EN_DEV0_F0_", 20, 20, &umr_bitfield_default }, - { "STRAP_MSIX_TABLE_BIR_DEV0_F0_", 21, 23, &umr_bitfield_default }, - { "STRAP_PMC_DSI_DEV0_F0_", 24, 24, &umr_bitfield_default }, - { "STRAP_VENDOR_ID_BIT_DEV0_F0_", 25, 25, &umr_bitfield_default }, - { "STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0_", 26, 26, &umr_bitfield_default }, - { "STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0_", 27, 27, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_EPF0_STRAP4[] = { - { "STRAP_MSIX_TABLE_OFFSET_DEV0_F0_", 0, 19, &umr_bitfield_default }, - { "STRAP_ATOMIC_64BIT_EN_DEV0_F0_", 20, 20, &umr_bitfield_default }, - { "STRAP_ATOMIC_EN_DEV0_F0_", 21, 21, &umr_bitfield_default }, - { "STRAP_FLR_EN_DEV0_F0_", 22, 22, &umr_bitfield_default }, - { "STRAP_PME_SUPPORT_DEV0_F0_", 23, 27, &umr_bitfield_default }, - { "STRAP_INTERRUPT_PIN_DEV0_F0_", 28, 30, &umr_bitfield_default }, - { "STRAP_AUXPWR_SUPPORT_DEV0_F0_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_EPF0_STRAP5[] = { - { "STRAP_SUBSYS_VEN_ID_DEV0_F0_", 0, 15, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_EPF0_STRAP8[] = { - { "STRAP_BAR_COMPLIANCE_EN_DEV0_F0_", 0, 0, &umr_bitfield_default }, - { "STRAP_DOORBELL_APER_SIZE_DEV0_F0_", 1, 2, &umr_bitfield_default }, - { "STRAP_DOORBELL_BAR_DIS_DEV0_F0_", 3, 3, &umr_bitfield_default }, - { "STRAP_FB_ALWAYS_ON_DEV0_F0_", 4, 4, &umr_bitfield_default }, - { "STRAP_FB_CPL_TYPE_SEL_DEV0_F0_", 5, 6, &umr_bitfield_default }, - { "STRAP_IO_BAR_DIS_DEV0_F0_", 7, 7, &umr_bitfield_default }, - { "STRAP_LFB_ERRMSG_EN_DEV0_F0_", 8, 8, &umr_bitfield_default }, - { "STRAP_MEM_AP_SIZE_DEV0_F0_", 9, 11, &umr_bitfield_default }, - { "STRAP_REG_AP_SIZE_DEV0_F0_", 12, 13, &umr_bitfield_default }, - { "STRAP_ROM_AP_SIZE_DEV0_F0_", 14, 15, &umr_bitfield_default }, - { "STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0_", 16, 18, &umr_bitfield_default }, - { "STRAP_VF_MEM_AP_SIZE_DEV0_F0_", 19, 21, &umr_bitfield_default }, - { "STRAP_VF_REG_AP_SIZE_DEV0_F0_", 22, 23, &umr_bitfield_default }, - { "STRAP_VGA_DIS_DEV0_F0_", 24, 24, &umr_bitfield_default }, - { "STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0_", 25, 25, &umr_bitfield_default }, - { "STRAP_VF_REG_PROT_DIS_DEV0_F0_", 26, 26, &umr_bitfield_default }, - { "STRAP_VF_MSI_MULTI_CAP_DEV0_F0_", 27, 29, &umr_bitfield_default }, - { "STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0_", 30, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_EPF1_STRAP0[] = { - { "STRAP_DEVICE_ID_DEV0_F1_", 0, 15, &umr_bitfield_default }, - { "STRAP_MAJOR_REV_ID_DEV0_F1_", 16, 19, &umr_bitfield_default }, - { "STRAP_MINOR_REV_ID_DEV0_F1_", 20, 23, &umr_bitfield_default }, - { "STRAP_FUNC_EN_DEV0_F1_", 28, 28, &umr_bitfield_default }, - { "STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1_", 29, 29, &umr_bitfield_default }, - { "STRAP_D1_SUPPORT_DEV0_F1_", 30, 30, &umr_bitfield_default }, - { "STRAP_D2_SUPPORT_DEV0_F1_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_EPF1_STRAP10[] = { - { "STRAP_APER1_RESIZE_EN_DEV0_F1_", 0, 0, &umr_bitfield_default }, - { "STRAP_APER1_RESIZE_SUPPORT_DEV0_F1_", 1, 20, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_EPF1_STRAP11[] = { - { "STRAP_APER2_RESIZE_EN_DEV0_F1_", 0, 0, &umr_bitfield_default }, - { "STRAP_APER2_RESIZE_SUPPORT_DEV0_F1_", 1, 20, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_EPF1_STRAP12[] = { - { "STRAP_APER3_RESIZE_EN_DEV0_F1_", 0, 0, &umr_bitfield_default }, - { "STRAP_APER3_RESIZE_SUPPORT_DEV0_F1_", 1, 20, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_EPF1_STRAP13[] = { - { "STRAP_CLASS_CODE_PIF_DEV0_F1_", 0, 7, &umr_bitfield_default }, - { "STRAP_CLASS_CODE_SUB_DEV0_F1_", 8, 15, &umr_bitfield_default }, - { "STRAP_CLASS_CODE_BASE_DEV0_F1_", 16, 23, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_EPF1_STRAP2[] = { - { "STRAP_NO_SOFT_RESET_DEV0_F1_", 7, 7, &umr_bitfield_default }, - { "STRAP_RESIZE_BAR_EN_DEV0_F1_", 8, 8, &umr_bitfield_default }, - { "STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1_", 14, 14, &umr_bitfield_default }, - { "STRAP_AER_EN_DEV0_F1_", 16, 16, &umr_bitfield_default }, - { "STRAP_ACS_EN_DEV0_F1_", 17, 17, &umr_bitfield_default }, - { "STRAP_ATS_EN_DEV0_F1_", 18, 18, &umr_bitfield_default }, - { "STRAP_CPL_ABORT_ERR_EN_DEV0_F1_", 20, 20, &umr_bitfield_default }, - { "STRAP_DPA_EN_DEV0_F1_", 21, 21, &umr_bitfield_default }, - { "STRAP_DSN_EN_DEV0_F1_", 22, 22, &umr_bitfield_default }, - { "STRAP_VC_EN_DEV0_F1_", 23, 23, &umr_bitfield_default }, - { "STRAP_MSI_MULTI_CAP_DEV0_F1_", 24, 26, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_EPF1_STRAP3[] = { - { "STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1_", 0, 0, &umr_bitfield_default }, - { "STRAP_PWR_EN_DEV0_F1_", 1, 1, &umr_bitfield_default }, - { "STRAP_SUBSYS_ID_DEV0_F1_", 2, 17, &umr_bitfield_default }, - { "STRAP_MSI_EN_DEV0_F1_", 18, 18, &umr_bitfield_default }, - { "STRAP_MSI_CLR_PENDING_EN_DEV0_F1_", 19, 19, &umr_bitfield_default }, - { "STRAP_MSIX_EN_DEV0_F1_", 20, 20, &umr_bitfield_default }, - { "STRAP_PMC_DSI_DEV0_F1_", 24, 24, &umr_bitfield_default }, - { "STRAP_VENDOR_ID_BIT_DEV0_F1_", 25, 25, &umr_bitfield_default }, - { "STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1_", 26, 26, &umr_bitfield_default }, - { "STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1_", 27, 27, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_EPF1_STRAP4[] = { - { "STRAP_ATOMIC_64BIT_EN_DEV0_F1_", 20, 20, &umr_bitfield_default }, - { "STRAP_ATOMIC_EN_DEV0_F1_", 21, 21, &umr_bitfield_default }, - { "STRAP_FLR_EN_DEV0_F1_", 22, 22, &umr_bitfield_default }, - { "STRAP_PME_SUPPORT_DEV0_F1_", 23, 27, &umr_bitfield_default }, - { "STRAP_INTERRUPT_PIN_DEV0_F1_", 28, 30, &umr_bitfield_default }, - { "STRAP_AUXPWR_SUPPORT_DEV0_F1_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_EPF1_STRAP5[] = { - { "STRAP_SUBSYS_VEN_ID_DEV0_F1_", 0, 15, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_EPF1_STRAP6[] = { - { "STRAP_APER0_EN_DEV0_F1_", 0, 0, &umr_bitfield_default }, - { "STRAP_APER0_PREFETCHABLE_EN_DEV0_F1_", 1, 1, &umr_bitfield_default }, - { "STRAP_APER0_64BAR_EN_DEV0_F1_", 2, 2, &umr_bitfield_default }, - { "STRAP_APER0_AP_SIZE_DEV0_F1_", 4, 6, &umr_bitfield_default }, - { "STRAP_APER1_EN_DEV0_F1_", 8, 8, &umr_bitfield_default }, - { "STRAP_APER1_PREFETCHABLE_EN_DEV0_F1_", 9, 9, &umr_bitfield_default }, - { "STRAP_APER2_EN_DEV0_F1_", 16, 16, &umr_bitfield_default }, - { "STRAP_APER2_PREFETCHABLE_EN_DEV0_F1_", 17, 17, &umr_bitfield_default }, - { "STRAP_APER3_EN_DEV0_F1_", 24, 24, &umr_bitfield_default }, - { "STRAP_APER3_PREFETCHABLE_EN_DEV0_F1_", 25, 25, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_EPF1_STRAP7[] = { - { "STRAP_ROM_APER_EN_DEV0_F1_", 0, 0, &umr_bitfield_default }, - { "STRAP_ROM_APER_SIZE_DEV0_F1_", 1, 4, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_BME_STATUS[] = { - { "DMA_ON_BME_LOW_", 0, 0, &umr_bitfield_default }, - { "CLEAR_DMA_ON_BME_LOW_", 16, 16, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_ATOMIC_ERR_LOG[] = { - { "UR_ATOMIC_OPCODE_", 0, 0, &umr_bitfield_default }, - { "UR_ATOMIC_REQEN_LOW_", 1, 1, &umr_bitfield_default }, - { "CLEAR_UR_ATOMIC_OPCODE_", 16, 16, &umr_bitfield_default }, - { "CLEAR_UR_ATOMIC_REQEN_LOW_", 17, 17, &umr_bitfield_default }, -}; -static struct umr_bitfield mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH[] = { - { "DOORBELL_SELFRING_GPA_APER_BASE_HIGH_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmDOORBELL_SELFRING_GPA_APER_BASE_LOW[] = { - { "DOORBELL_SELFRING_GPA_APER_BASE_LOW_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmDOORBELL_SELFRING_GPA_APER_CNTL[] = { - { "DOORBELL_SELFRING_GPA_APER_EN_", 0, 0, &umr_bitfield_default }, - { "DOORBELL_SELFRING_GPA_APER_SIZE_", 8, 15, &umr_bitfield_default }, -}; -static struct umr_bitfield mmHDP_REG_COHERENCY_FLUSH_CNTL[] = { - { "HDP_REG_FLUSH_ADDR_", 0, 0, &umr_bitfield_default }, -}; -static struct umr_bitfield mmHDP_MEM_COHERENCY_FLUSH_CNTL[] = { - { "HDP_MEM_FLUSH_ADDR_", 0, 0, &umr_bitfield_default }, -}; -static struct umr_bitfield mmGPU_HDP_FLUSH_REQ[] = { - { "CP0_", 0, 0, &umr_bitfield_default }, - { "CP1_", 1, 1, &umr_bitfield_default }, - { "CP2_", 2, 2, &umr_bitfield_default }, - { "CP3_", 3, 3, &umr_bitfield_default }, - { "CP4_", 4, 4, &umr_bitfield_default }, - { "CP5_", 5, 5, &umr_bitfield_default }, - { "CP6_", 6, 6, &umr_bitfield_default }, - { "CP7_", 7, 7, &umr_bitfield_default }, - { "CP8_", 8, 8, &umr_bitfield_default }, - { "CP9_", 9, 9, &umr_bitfield_default }, - { "SDMA0_", 10, 10, &umr_bitfield_default }, - { "SDMA1_", 11, 11, &umr_bitfield_default }, -}; -static struct umr_bitfield mmGPU_HDP_FLUSH_DONE[] = { - { "CP0_", 0, 0, &umr_bitfield_default }, - { "CP1_", 1, 1, &umr_bitfield_default }, - { "CP2_", 2, 2, &umr_bitfield_default }, - { "CP3_", 3, 3, &umr_bitfield_default }, - { "CP4_", 4, 4, &umr_bitfield_default }, - { "CP5_", 5, 5, &umr_bitfield_default }, - { "CP6_", 6, 6, &umr_bitfield_default }, - { "CP7_", 7, 7, &umr_bitfield_default }, - { "CP8_", 8, 8, &umr_bitfield_default }, - { "CP9_", 9, 9, &umr_bitfield_default }, - { "SDMA0_", 10, 10, &umr_bitfield_default }, - { "SDMA1_", 11, 11, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_TRANS_PENDING[] = { - { "BIF_MST_TRANS_PENDING_", 0, 0, &umr_bitfield_default }, - { "BIF_SLV_TRANS_PENDING_", 1, 1, &umr_bitfield_default }, -}; -static struct umr_bitfield mmMAILBOX_MSGBUF_TRN_DW0[] = { - { "MSGBUF_DATA_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmMAILBOX_MSGBUF_TRN_DW1[] = { - { "MSGBUF_DATA_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmMAILBOX_MSGBUF_TRN_DW2[] = { - { "MSGBUF_DATA_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmMAILBOX_MSGBUF_TRN_DW3[] = { - { "MSGBUF_DATA_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmMAILBOX_MSGBUF_RCV_DW0[] = { - { "MSGBUF_DATA_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmMAILBOX_MSGBUF_RCV_DW1[] = { - { "MSGBUF_DATA_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmMAILBOX_MSGBUF_RCV_DW2[] = { - { "MSGBUF_DATA_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmMAILBOX_MSGBUF_RCV_DW3[] = { - { "MSGBUF_DATA_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmMAILBOX_CONTROL[] = { - { "TRN_MSG_VALID_", 0, 0, &umr_bitfield_default }, - { "TRN_MSG_ACK_", 1, 1, &umr_bitfield_default }, - { "RCV_MSG_VALID_", 8, 8, &umr_bitfield_default }, - { "RCV_MSG_ACK_", 9, 9, &umr_bitfield_default }, -}; -static struct umr_bitfield mmMAILBOX_INT_CNTL[] = { - { "VALID_INT_EN_", 0, 0, &umr_bitfield_default }, - { "ACK_INT_EN_", 1, 1, &umr_bitfield_default }, -}; -static struct umr_bitfield mmBIF_VMHV_MAILBOX[] = { - { "VMHV_MAILBOX_TRN_ACK_INTR_EN_", 0, 0, &umr_bitfield_default }, - { "VMHV_MAILBOX_RCV_VALID_INTR_EN_", 1, 1, &umr_bitfield_default }, - { "VMHV_MAILBOX_TRN_MSG_DATA_", 8, 11, &umr_bitfield_default }, - { "VMHV_MAILBOX_TRN_MSG_VALID_", 15, 15, &umr_bitfield_default }, - { "VMHV_MAILBOX_RCV_MSG_DATA_", 16, 19, &umr_bitfield_default }, - { "VMHV_MAILBOX_RCV_MSG_VALID_", 23, 23, &umr_bitfield_default }, - { "VMHV_MAILBOX_TRN_MSG_ACK_", 24, 24, &umr_bitfield_default }, - { "VMHV_MAILBOX_RCV_MSG_ACK_", 25, 25, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DOORBELL_APER_EN[] = { - { "BIF_DOORBELL_APER_EN_", 0, 0, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_CONFIG_MEMSIZE[] = { - { "CONFIG_MEMSIZE_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_CONFIG_RESERVED[] = { - { "CONFIG_RESERVED_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_IOV_FUNC_IDENTIFIER[] = { - { "FUNC_IDENTIFIER_", 0, 0, &umr_bitfield_default }, - { "IOV_ENABLE_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmSYSHUB_INDEX[] = { - { "INDEX_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmSYSHUB_DATA[] = { - { "DATA_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0[] = { - { "STRAP_ARI_EN_DN_DEV0_", 1, 1, &umr_bitfield_default }, - { "STRAP_ACS_EN_DN_DEV0_", 2, 2, &umr_bitfield_default }, - { "STRAP_AER_EN_DN_DEV0_", 3, 3, &umr_bitfield_default }, - { "STRAP_CPL_ABORT_ERR_EN_DN_DEV0_", 4, 4, &umr_bitfield_default }, - { "STRAP_DEVICE_ID_DN_DEV0_", 5, 20, &umr_bitfield_default }, - { "STRAP_INTERRUPT_PIN_DN_DEV0_", 21, 23, &umr_bitfield_default }, - { "STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0_", 24, 24, &umr_bitfield_default }, - { "STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0_", 25, 27, &umr_bitfield_default }, - { "STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0_", 28, 30, &umr_bitfield_default }, - { "STRAP_EPF0_DUMMY_EN_DEV0_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP1[] = { - { "STRAP_SUBSYS_ID_DN_DEV0_", 0, 15, &umr_bitfield_default }, - { "STRAP_SUBSYS_VEN_ID_DN_DEV0_", 16, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2[] = { - { "STRAP_DE_EMPHASIS_SEL_DN_DEV0_", 0, 0, &umr_bitfield_default }, - { "STRAP_DSN_EN_DN_DEV0_", 1, 1, &umr_bitfield_default }, - { "STRAP_E2E_PREFIX_EN_DEV0_", 2, 2, &umr_bitfield_default }, - { "STRAP_ECN1P1_EN_DEV0_", 3, 3, &umr_bitfield_default }, - { "STRAP_ECRC_CHECK_EN_DEV0_", 4, 4, &umr_bitfield_default }, - { "STRAP_ECRC_GEN_EN_DEV0_", 5, 5, &umr_bitfield_default }, - { "STRAP_ERR_REPORTING_DIS_DEV0_", 6, 6, &umr_bitfield_default }, - { "STRAP_EXTENDED_FMT_SUPPORTED_DEV0_", 7, 7, &umr_bitfield_default }, - { "STRAP_EXTENDED_TAG_ECN_EN_DEV0_", 8, 8, &umr_bitfield_default }, - { "STRAP_EXT_VC_COUNT_DN_DEV0_", 9, 11, &umr_bitfield_default }, - { "STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0_", 12, 12, &umr_bitfield_default }, - { "STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0_", 13, 13, &umr_bitfield_default }, - { "STRAP_GEN2_COMPLIANCE_DEV0_", 14, 14, &umr_bitfield_default }, - { "STRAP_GEN2_EN_DEV0_", 15, 15, &umr_bitfield_default }, - { "STRAP_GEN3_COMPLIANCE_DEV0_", 16, 16, &umr_bitfield_default }, - { "STRAP_TARGET_LINK_SPEED_DEV0_", 17, 18, &umr_bitfield_default }, - { "STRAP_INTERNAL_ERR_EN_DEV0_", 19, 19, &umr_bitfield_default }, - { "STRAP_L0S_ACCEPTABLE_LATENCY_DEV0_", 20, 22, &umr_bitfield_default }, - { "STRAP_L0S_EXIT_LATENCY_DEV0_", 23, 25, &umr_bitfield_default }, - { "STRAP_L1_ACCEPTABLE_LATENCY_DEV0_", 26, 28, &umr_bitfield_default }, - { "STRAP_L1_EXIT_LATENCY_DEV0_", 29, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3[] = { - { "STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0_", 0, 0, &umr_bitfield_default }, - { "STRAP_LTR_EN_DEV0_", 1, 1, &umr_bitfield_default }, - { "STRAP_LTR_EN_DN_DEV0_", 2, 2, &umr_bitfield_default }, - { "STRAP_MAX_PAYLOAD_SUPPORT_DEV0_", 3, 5, &umr_bitfield_default }, - { "STRAP_MSI_EN_DN_DEV0_", 6, 6, &umr_bitfield_default }, - { "STRAP_MSTCPL_TIMEOUT_EN_DEV0_", 7, 7, &umr_bitfield_default }, - { "STRAP_NO_SOFT_RESET_DN_DEV0_", 8, 8, &umr_bitfield_default }, - { "STRAP_OBFF_SUPPORTED_DEV0_", 9, 10, &umr_bitfield_default }, - { "STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0_", 11, 13, &umr_bitfield_default }, - { "STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0_", 14, 17, &umr_bitfield_default }, - { "STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0_", 18, 20, &umr_bitfield_default }, - { "STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0_", 21, 24, &umr_bitfield_default }, - { "STRAP_PM_SUPPORT_DEV0_", 25, 26, &umr_bitfield_default }, - { "STRAP_PM_SUPPORT_DN_DEV0_", 27, 28, &umr_bitfield_default }, - { "STRAP_ATOMIC_EN_DN_DEV0_", 29, 29, &umr_bitfield_default }, - { "STRAP_VENDOR_ID_BIT_DN_DEV0_", 30, 30, &umr_bitfield_default }, - { "STRAP_PMC_DSI_DN_DEV0_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4[] = { - { "STRAP_PWR_BUDGET_DATA_8T0_0_DEV0_", 0, 7, &umr_bitfield_default }, - { "STRAP_PWR_BUDGET_DATA_8T0_1_DEV0_", 8, 15, &umr_bitfield_default }, - { "STRAP_PWR_BUDGET_DATA_8T0_2_DEV0_", 16, 23, &umr_bitfield_default }, - { "STRAP_PWR_BUDGET_DATA_8T0_3_DEV0_", 24, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5[] = { - { "STRAP_PWR_BUDGET_DATA_8T0_4_DEV0_", 0, 7, &umr_bitfield_default }, - { "STRAP_PWR_BUDGET_DATA_8T0_5_DEV0_", 8, 15, &umr_bitfield_default }, - { "STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0_", 16, 16, &umr_bitfield_default }, - { "STRAP_ATOMIC_64BIT_EN_DN_DEV0_", 17, 17, &umr_bitfield_default }, - { "STRAP_ATOMIC_ROUTING_EN_DEV0_", 18, 18, &umr_bitfield_default }, - { "STRAP_VC_EN_DN_DEV0_", 19, 19, &umr_bitfield_default }, - { "STRAP_TwoVC_EN_DEV0_", 20, 20, &umr_bitfield_default }, - { "STRAP_TwoVC_EN_DN_DEV0_", 21, 21, &umr_bitfield_default }, - { "STRAP_ACS_SOURCE_VALIDATION_DN_DEV0_", 23, 23, &umr_bitfield_default }, - { "STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0_", 24, 24, &umr_bitfield_default }, - { "STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0_", 25, 25, &umr_bitfield_default }, - { "STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0_", 26, 26, &umr_bitfield_default }, - { "STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0_", 27, 27, &umr_bitfield_default }, - { "STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0_", 28, 28, &umr_bitfield_default }, - { "STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0_", 29, 29, &umr_bitfield_default }, - { "STRAP_MSI_MAP_EN_DEV0_", 30, 30, &umr_bitfield_default }, - { "STRAP_SSID_EN_DEV0_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP6[] = { - { "STRAP_CFG_CRS_EN_DEV0_", 0, 0, &umr_bitfield_default }, - { "STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0_", 1, 1, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7[] = { - { "STRAP_PORT_NUMBER_DEV0_", 0, 7, &umr_bitfield_default }, - { "STRAP_MAJOR_REV_ID_DN_DEV0_", 8, 11, &umr_bitfield_default }, - { "STRAP_MINOR_REV_ID_DN_DEV0_", 12, 15, &umr_bitfield_default }, - { "STRAP_RP_BUSNUM_DEV0_", 16, 23, &umr_bitfield_default }, - { "STRAP_DN_DEVNUM_DEV0_", 24, 28, &umr_bitfield_default }, - { "STRAP_DN_FUNCID_DEV0_", 29, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV1_PORT_STRAP0[] = { - { "STRAP_ARI_EN_DN_DEV1_", 1, 1, &umr_bitfield_default }, - { "STRAP_ACS_EN_DN_DEV1_", 2, 2, &umr_bitfield_default }, - { "STRAP_AER_EN_DN_DEV1_", 3, 3, &umr_bitfield_default }, - { "STRAP_CPL_ABORT_ERR_EN_DN_DEV1_", 4, 4, &umr_bitfield_default }, - { "STRAP_DEVICE_ID_DN_DEV1_", 5, 20, &umr_bitfield_default }, - { "STRAP_INTERRUPT_PIN_DN_DEV1_", 21, 23, &umr_bitfield_default }, - { "STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV1_", 24, 24, &umr_bitfield_default }, - { "STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV1_", 25, 27, &umr_bitfield_default }, - { "STRAP_MAX_LINK_WIDTH_SUPPORT_DEV1_", 28, 30, &umr_bitfield_default }, - { "STRAP_EPF0_DUMMY_EN_DEV1_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV1_PORT_STRAP1[] = { - { "STRAP_SUBSYS_ID_DN_DEV1_", 0, 15, &umr_bitfield_default }, - { "STRAP_SUBSYS_VEN_ID_DN_DEV1_", 16, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV1_PORT_STRAP2[] = { - { "STRAP_DE_EMPHASIS_SEL_DN_DEV1_", 0, 0, &umr_bitfield_default }, - { "STRAP_DSN_EN_DN_DEV1_", 1, 1, &umr_bitfield_default }, - { "STRAP_E2E_PREFIX_EN_DEV1_", 2, 2, &umr_bitfield_default }, - { "STRAP_ECN1P1_EN_DEV1_", 3, 3, &umr_bitfield_default }, - { "STRAP_ECRC_CHECK_EN_DEV1_", 4, 4, &umr_bitfield_default }, - { "STRAP_ECRC_GEN_EN_DEV1_", 5, 5, &umr_bitfield_default }, - { "STRAP_ERR_REPORTING_DIS_DEV1_", 6, 6, &umr_bitfield_default }, - { "STRAP_EXTENDED_FMT_SUPPORTED_DEV1_", 7, 7, &umr_bitfield_default }, - { "STRAP_EXTENDED_TAG_ECN_EN_DEV1_", 8, 8, &umr_bitfield_default }, - { "STRAP_EXT_VC_COUNT_DN_DEV1_", 9, 11, &umr_bitfield_default }, - { "STRAP_FIRST_RCVD_ERR_LOG_DN_DEV1_", 12, 12, &umr_bitfield_default }, - { "STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV1_", 13, 13, &umr_bitfield_default }, - { "STRAP_GEN2_COMPLIANCE_DEV1_", 14, 14, &umr_bitfield_default }, - { "STRAP_GEN2_EN_DEV1_", 15, 15, &umr_bitfield_default }, - { "STRAP_GEN3_COMPLIANCE_DEV1_", 16, 16, &umr_bitfield_default }, - { "STRAP_TARGET_LINK_SPEED_DEV1_", 17, 18, &umr_bitfield_default }, - { "STRAP_INTERNAL_ERR_EN_DEV1_", 19, 19, &umr_bitfield_default }, - { "STRAP_L0S_ACCEPTABLE_LATENCY_DEV1_", 20, 22, &umr_bitfield_default }, - { "STRAP_L0S_EXIT_LATENCY_DEV1_", 23, 25, &umr_bitfield_default }, - { "STRAP_L1_ACCEPTABLE_LATENCY_DEV1_", 26, 28, &umr_bitfield_default }, - { "STRAP_L1_EXIT_LATENCY_DEV1_", 29, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV1_PORT_STRAP3[] = { - { "STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV1_", 0, 0, &umr_bitfield_default }, - { "STRAP_LTR_EN_DEV1_", 1, 1, &umr_bitfield_default }, - { "STRAP_LTR_EN_DN_DEV1_", 2, 2, &umr_bitfield_default }, - { "STRAP_MAX_PAYLOAD_SUPPORT_DEV1_", 3, 5, &umr_bitfield_default }, - { "STRAP_MSI_EN_DN_DEV1_", 6, 6, &umr_bitfield_default }, - { "STRAP_MSTCPL_TIMEOUT_EN_DEV1_", 7, 7, &umr_bitfield_default }, - { "STRAP_NO_SOFT_RESET_DN_DEV1_", 8, 8, &umr_bitfield_default }, - { "STRAP_OBFF_SUPPORTED_DEV1_", 9, 10, &umr_bitfield_default }, - { "STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV1_", 11, 13, &umr_bitfield_default }, - { "STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV1_", 14, 17, &umr_bitfield_default }, - { "STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV1_", 18, 20, &umr_bitfield_default }, - { "STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV1_", 21, 24, &umr_bitfield_default }, - { "STRAP_PM_SUPPORT_DEV1_", 25, 26, &umr_bitfield_default }, - { "STRAP_PM_SUPPORT_DN_DEV1_", 27, 28, &umr_bitfield_default }, - { "STRAP_ATOMIC_EN_DN_DEV1_", 29, 29, &umr_bitfield_default }, - { "STRAP_VENDOR_ID_BIT_DN_DEV1_", 30, 30, &umr_bitfield_default }, - { "STRAP_PMC_DSI_DN_DEV1_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV1_PORT_STRAP4[] = { - { "STRAP_PWR_BUDGET_DATA_8T0_0_DEV1_", 0, 7, &umr_bitfield_default }, - { "STRAP_PWR_BUDGET_DATA_8T0_1_DEV1_", 8, 15, &umr_bitfield_default }, - { "STRAP_PWR_BUDGET_DATA_8T0_2_DEV1_", 16, 23, &umr_bitfield_default }, - { "STRAP_PWR_BUDGET_DATA_8T0_3_DEV1_", 24, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV1_PORT_STRAP5[] = { - { "STRAP_PWR_BUDGET_DATA_8T0_4_DEV1_", 0, 7, &umr_bitfield_default }, - { "STRAP_PWR_BUDGET_DATA_8T0_5_DEV1_", 8, 15, &umr_bitfield_default }, - { "STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV1_", 16, 16, &umr_bitfield_default }, - { "STRAP_ATOMIC_64BIT_EN_DN_DEV1_", 17, 17, &umr_bitfield_default }, - { "STRAP_ATOMIC_ROUTING_EN_DEV1_", 18, 18, &umr_bitfield_default }, - { "STRAP_VC_EN_DN_DEV1_", 19, 19, &umr_bitfield_default }, - { "STRAP_TwoVC_EN_DEV1_", 20, 20, &umr_bitfield_default }, - { "STRAP_TwoVC_EN_DN_DEV1_", 21, 21, &umr_bitfield_default }, - { "STRAP_ACS_SOURCE_VALIDATION_DN_DEV1_", 23, 23, &umr_bitfield_default }, - { "STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV1_", 24, 24, &umr_bitfield_default }, - { "STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV1_", 25, 25, &umr_bitfield_default }, - { "STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV1_", 26, 26, &umr_bitfield_default }, - { "STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV1_", 27, 27, &umr_bitfield_default }, - { "STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV1_", 28, 28, &umr_bitfield_default }, - { "STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV1_", 29, 29, &umr_bitfield_default }, - { "STRAP_MSI_MAP_EN_DEV1_", 30, 30, &umr_bitfield_default }, - { "STRAP_SSID_EN_DEV1_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV1_PORT_STRAP6[] = { - { "STRAP_CFG_CRS_EN_DEV1_", 0, 0, &umr_bitfield_default }, - { "STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV1_", 1, 1, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV1_PORT_STRAP7[] = { - { "STRAP_PORT_NUMBER_DEV1_", 0, 7, &umr_bitfield_default }, - { "STRAP_MAJOR_REV_ID_DN_DEV1_", 8, 11, &umr_bitfield_default }, - { "STRAP_MINOR_REV_ID_DN_DEV1_", 12, 15, &umr_bitfield_default }, - { "STRAP_RP_BUSNUM_DEV1_", 16, 23, &umr_bitfield_default }, - { "STRAP_DN_DEVNUM_DEV1_", 24, 28, &umr_bitfield_default }, - { "STRAP_DN_FUNCID_DEV1_", 29, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0[] = { - { "STRAP_DEVICE_ID_DEV0_F0_", 0, 15, &umr_bitfield_default }, - { "STRAP_MAJOR_REV_ID_DEV0_F0_", 16, 19, &umr_bitfield_default }, - { "STRAP_MINOR_REV_ID_DEV0_F0_", 20, 23, &umr_bitfield_default }, - { "STRAP_ATI_REV_ID_DEV0_F0_", 24, 27, &umr_bitfield_default }, - { "STRAP_FUNC_EN_DEV0_F0_", 28, 28, &umr_bitfield_default }, - { "STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_", 29, 29, &umr_bitfield_default }, - { "STRAP_D1_SUPPORT_DEV0_F0_", 30, 30, &umr_bitfield_default }, - { "STRAP_D2_SUPPORT_DEV0_F0_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP1[] = { - { "STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0_", 0, 15, &umr_bitfield_default }, - { "STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0_", 16, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2[] = { - { "STRAP_SRIOV_EN_DEV0_F0_", 0, 0, &umr_bitfield_default }, - { "STRAP_SRIOV_TOTAL_VFS_DEV0_F0_", 1, 5, &umr_bitfield_default }, - { "STRAP_64BAR_DIS_DEV0_F0_", 6, 6, &umr_bitfield_default }, - { "STRAP_NO_SOFT_RESET_DEV0_F0_", 7, 7, &umr_bitfield_default }, - { "STRAP_RESIZE_BAR_EN_DEV0_F0_", 8, 8, &umr_bitfield_default }, - { "STRAP_MAX_PASID_WIDTH_DEV0_F0_", 9, 13, &umr_bitfield_default }, - { "STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0_", 14, 14, &umr_bitfield_default }, - { "STRAP_ARI_EN_DEV0_F0_", 15, 15, &umr_bitfield_default }, - { "STRAP_AER_EN_DEV0_F0_", 16, 16, &umr_bitfield_default }, - { "STRAP_ACS_EN_DEV0_F0_", 17, 17, &umr_bitfield_default }, - { "STRAP_ATS_EN_DEV0_F0_", 18, 18, &umr_bitfield_default }, - { "STRAP_CPL_ABORT_ERR_EN_DEV0_F0_", 20, 20, &umr_bitfield_default }, - { "STRAP_DPA_EN_DEV0_F0_", 21, 21, &umr_bitfield_default }, - { "STRAP_DSN_EN_DEV0_F0_", 22, 22, &umr_bitfield_default }, - { "STRAP_VC_EN_DEV0_F0_", 23, 23, &umr_bitfield_default }, - { "STRAP_MSI_MULTI_CAP_DEV0_F0_", 24, 26, &umr_bitfield_default }, - { "STRAP_PAGE_REQ_EN_DEV0_F0_", 27, 27, &umr_bitfield_default }, - { "STRAP_PASID_EN_DEV0_F0_", 28, 28, &umr_bitfield_default }, - { "STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0_", 29, 29, &umr_bitfield_default }, - { "STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0_", 30, 30, &umr_bitfield_default }, - { "STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3[] = { - { "STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0_", 0, 0, &umr_bitfield_default }, - { "STRAP_PWR_EN_DEV0_F0_", 1, 1, &umr_bitfield_default }, - { "STRAP_SUBSYS_ID_DEV0_F0_", 2, 17, &umr_bitfield_default }, - { "STRAP_MSI_EN_DEV0_F0_", 18, 18, &umr_bitfield_default }, - { "STRAP_MSI_CLR_PENDING_EN_DEV0_F0_", 19, 19, &umr_bitfield_default }, - { "STRAP_MSIX_EN_DEV0_F0_", 20, 20, &umr_bitfield_default }, - { "STRAP_MSIX_TABLE_BIR_DEV0_F0_", 21, 23, &umr_bitfield_default }, - { "STRAP_PMC_DSI_DEV0_F0_", 24, 24, &umr_bitfield_default }, - { "STRAP_VENDOR_ID_BIT_DEV0_F0_", 25, 25, &umr_bitfield_default }, - { "STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0_", 26, 26, &umr_bitfield_default }, - { "STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0_", 27, 27, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4[] = { - { "STRAP_MSIX_TABLE_OFFSET_DEV0_F0_", 0, 19, &umr_bitfield_default }, - { "STRAP_ATOMIC_64BIT_EN_DEV0_F0_", 20, 20, &umr_bitfield_default }, - { "STRAP_ATOMIC_EN_DEV0_F0_", 21, 21, &umr_bitfield_default }, - { "STRAP_FLR_EN_DEV0_F0_", 22, 22, &umr_bitfield_default }, - { "STRAP_PME_SUPPORT_DEV0_F0_", 23, 27, &umr_bitfield_default }, - { "STRAP_INTERRUPT_PIN_DEV0_F0_", 28, 30, &umr_bitfield_default }, - { "STRAP_AUXPWR_SUPPORT_DEV0_F0_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP5[] = { - { "STRAP_SUBSYS_VEN_ID_DEV0_F0_", 0, 15, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8[] = { - { "STRAP_BAR_COMPLIANCE_EN_DEV0_F0_", 0, 0, &umr_bitfield_default }, - { "STRAP_DOORBELL_APER_SIZE_DEV0_F0_", 1, 2, &umr_bitfield_default }, - { "STRAP_DOORBELL_BAR_DIS_DEV0_F0_", 3, 3, &umr_bitfield_default }, - { "STRAP_FB_ALWAYS_ON_DEV0_F0_", 4, 4, &umr_bitfield_default }, - { "STRAP_FB_CPL_TYPE_SEL_DEV0_F0_", 5, 6, &umr_bitfield_default }, - { "STRAP_IO_BAR_DIS_DEV0_F0_", 7, 7, &umr_bitfield_default }, - { "STRAP_LFB_ERRMSG_EN_DEV0_F0_", 8, 8, &umr_bitfield_default }, - { "STRAP_MEM_AP_SIZE_DEV0_F0_", 9, 11, &umr_bitfield_default }, - { "STRAP_REG_AP_SIZE_DEV0_F0_", 12, 13, &umr_bitfield_default }, - { "STRAP_ROM_AP_SIZE_DEV0_F0_", 14, 15, &umr_bitfield_default }, - { "STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0_", 16, 18, &umr_bitfield_default }, - { "STRAP_VF_MEM_AP_SIZE_DEV0_F0_", 19, 21, &umr_bitfield_default }, - { "STRAP_VF_REG_AP_SIZE_DEV0_F0_", 22, 23, &umr_bitfield_default }, - { "STRAP_VGA_DIS_DEV0_F0_", 24, 24, &umr_bitfield_default }, - { "STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0_", 25, 25, &umr_bitfield_default }, - { "STRAP_VF_REG_PROT_DIS_DEV0_F0_", 26, 26, &umr_bitfield_default }, - { "STRAP_VF_MSI_MULTI_CAP_DEV0_F0_", 27, 29, &umr_bitfield_default }, - { "STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0_", 30, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13[] = { - { "STRAP_CLASS_CODE_PIF_DEV0_F0_", 0, 7, &umr_bitfield_default }, - { "STRAP_CLASS_CODE_SUB_DEV0_F0_", 8, 15, &umr_bitfield_default }, - { "STRAP_CLASS_CODE_BASE_DEV0_F0_", 16, 23, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0[] = { - { "STRAP_DEVICE_ID_DEV0_F1_", 0, 15, &umr_bitfield_default }, - { "STRAP_MAJOR_REV_ID_DEV0_F1_", 16, 19, &umr_bitfield_default }, - { "STRAP_MINOR_REV_ID_DEV0_F1_", 20, 23, &umr_bitfield_default }, - { "STRAP_FUNC_EN_DEV0_F1_", 28, 28, &umr_bitfield_default }, - { "STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1_", 29, 29, &umr_bitfield_default }, - { "STRAP_D1_SUPPORT_DEV0_F1_", 30, 30, &umr_bitfield_default }, - { "STRAP_D2_SUPPORT_DEV0_F1_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2[] = { - { "STRAP_NO_SOFT_RESET_DEV0_F1_", 7, 7, &umr_bitfield_default }, - { "STRAP_RESIZE_BAR_EN_DEV0_F1_", 8, 8, &umr_bitfield_default }, - { "STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1_", 14, 14, &umr_bitfield_default }, - { "STRAP_AER_EN_DEV0_F1_", 16, 16, &umr_bitfield_default }, - { "STRAP_ACS_EN_DEV0_F1_", 17, 17, &umr_bitfield_default }, - { "STRAP_ATS_EN_DEV0_F1_", 18, 18, &umr_bitfield_default }, - { "STRAP_CPL_ABORT_ERR_EN_DEV0_F1_", 20, 20, &umr_bitfield_default }, - { "STRAP_DPA_EN_DEV0_F1_", 21, 21, &umr_bitfield_default }, - { "STRAP_DSN_EN_DEV0_F1_", 22, 22, &umr_bitfield_default }, - { "STRAP_VC_EN_DEV0_F1_", 23, 23, &umr_bitfield_default }, - { "STRAP_MSI_MULTI_CAP_DEV0_F1_", 24, 26, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3[] = { - { "STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1_", 0, 0, &umr_bitfield_default }, - { "STRAP_PWR_EN_DEV0_F1_", 1, 1, &umr_bitfield_default }, - { "STRAP_SUBSYS_ID_DEV0_F1_", 2, 17, &umr_bitfield_default }, - { "STRAP_MSI_EN_DEV0_F1_", 18, 18, &umr_bitfield_default }, - { "STRAP_MSI_CLR_PENDING_EN_DEV0_F1_", 19, 19, &umr_bitfield_default }, - { "STRAP_MSIX_EN_DEV0_F1_", 20, 20, &umr_bitfield_default }, - { "STRAP_PMC_DSI_DEV0_F1_", 24, 24, &umr_bitfield_default }, - { "STRAP_VENDOR_ID_BIT_DEV0_F1_", 25, 25, &umr_bitfield_default }, - { "STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1_", 26, 26, &umr_bitfield_default }, - { "STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1_", 27, 27, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4[] = { - { "STRAP_ATOMIC_64BIT_EN_DEV0_F1_", 20, 20, &umr_bitfield_default }, - { "STRAP_ATOMIC_EN_DEV0_F1_", 21, 21, &umr_bitfield_default }, - { "STRAP_FLR_EN_DEV0_F1_", 22, 22, &umr_bitfield_default }, - { "STRAP_PME_SUPPORT_DEV0_F1_", 23, 27, &umr_bitfield_default }, - { "STRAP_INTERRUPT_PIN_DEV0_F1_", 28, 30, &umr_bitfield_default }, - { "STRAP_AUXPWR_SUPPORT_DEV0_F1_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP5[] = { - { "STRAP_SUBSYS_VEN_ID_DEV0_F1_", 0, 15, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6[] = { - { "STRAP_APER0_EN_DEV0_F1_", 0, 0, &umr_bitfield_default }, - { "STRAP_APER0_PREFETCHABLE_EN_DEV0_F1_", 1, 1, &umr_bitfield_default }, - { "STRAP_APER0_64BAR_EN_DEV0_F1_", 2, 2, &umr_bitfield_default }, - { "STRAP_APER0_AP_SIZE_DEV0_F1_", 4, 6, &umr_bitfield_default }, - { "STRAP_APER1_EN_DEV0_F1_", 8, 8, &umr_bitfield_default }, - { "STRAP_APER1_PREFETCHABLE_EN_DEV0_F1_", 9, 9, &umr_bitfield_default }, - { "STRAP_APER2_EN_DEV0_F1_", 16, 16, &umr_bitfield_default }, - { "STRAP_APER2_PREFETCHABLE_EN_DEV0_F1_", 17, 17, &umr_bitfield_default }, - { "STRAP_APER3_EN_DEV0_F1_", 24, 24, &umr_bitfield_default }, - { "STRAP_APER3_PREFETCHABLE_EN_DEV0_F1_", 25, 25, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP7[] = { - { "STRAP_ROM_APER_EN_DEV0_F1_", 0, 0, &umr_bitfield_default }, - { "STRAP_ROM_APER_SIZE_DEV0_F1_", 1, 4, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP10[] = { - { "STRAP_APER1_RESIZE_EN_DEV0_F1_", 0, 0, &umr_bitfield_default }, - { "STRAP_APER1_RESIZE_SUPPORT_DEV0_F1_", 1, 20, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP11[] = { - { "STRAP_APER2_RESIZE_EN_DEV0_F1_", 0, 0, &umr_bitfield_default }, - { "STRAP_APER2_RESIZE_SUPPORT_DEV0_F1_", 1, 20, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP12[] = { - { "STRAP_APER3_RESIZE_EN_DEV0_F1_", 0, 0, &umr_bitfield_default }, - { "STRAP_APER3_RESIZE_SUPPORT_DEV0_F1_", 1, 20, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13[] = { - { "STRAP_CLASS_CODE_PIF_DEV0_F1_", 0, 7, &umr_bitfield_default }, - { "STRAP_CLASS_CODE_SUB_DEV0_F1_", 8, 15, &umr_bitfield_default }, - { "STRAP_CLASS_CODE_BASE_DEV0_F1_", 16, 23, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_EPF2_STRAP0[] = { - { "STRAP_DEVICE_ID_DEV0_F2_", 0, 15, &umr_bitfield_default }, - { "STRAP_MAJOR_REV_ID_DEV0_F2_", 16, 19, &umr_bitfield_default }, - { "STRAP_MINOR_REV_ID_DEV0_F2_", 20, 23, &umr_bitfield_default }, - { "STRAP_FUNC_EN_DEV0_F2_", 28, 28, &umr_bitfield_default }, - { "STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F2_", 29, 29, &umr_bitfield_default }, - { "STRAP_D1_SUPPORT_DEV0_F2_", 30, 30, &umr_bitfield_default }, - { "STRAP_D2_SUPPORT_DEV0_F2_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_EPF2_STRAP2[] = { - { "STRAP_NO_SOFT_RESET_DEV0_F2_", 7, 7, &umr_bitfield_default }, - { "STRAP_RESIZE_BAR_EN_DEV0_F2_", 8, 8, &umr_bitfield_default }, - { "STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F2_", 14, 14, &umr_bitfield_default }, - { "STRAP_AER_EN_DEV0_F2_", 16, 16, &umr_bitfield_default }, - { "STRAP_ACS_EN_DEV0_F2_", 17, 17, &umr_bitfield_default }, - { "STRAP_CPL_ABORT_ERR_EN_DEV0_F2_", 20, 20, &umr_bitfield_default }, - { "STRAP_DPA_EN_DEV0_F2_", 21, 21, &umr_bitfield_default }, - { "STRAP_VC_EN_DEV0_F2_", 23, 23, &umr_bitfield_default }, - { "STRAP_MSI_MULTI_CAP_DEV0_F2_", 24, 26, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_EPF2_STRAP3[] = { - { "STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F2_", 0, 0, &umr_bitfield_default }, - { "STRAP_PWR_EN_DEV0_F2_", 1, 1, &umr_bitfield_default }, - { "STRAP_SUBSYS_ID_DEV0_F2_", 2, 17, &umr_bitfield_default }, - { "STRAP_MSI_EN_DEV0_F2_", 18, 18, &umr_bitfield_default }, - { "STRAP_MSI_CLR_PENDING_EN_DEV0_F2_", 19, 19, &umr_bitfield_default }, - { "STRAP_MSIX_EN_DEV0_F2_", 20, 20, &umr_bitfield_default }, - { "STRAP_PMC_DSI_DEV0_F2_", 24, 24, &umr_bitfield_default }, - { "STRAP_VENDOR_ID_BIT_DEV0_F2_", 25, 25, &umr_bitfield_default }, - { "STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F2_", 26, 26, &umr_bitfield_default }, - { "STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F2_", 27, 27, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_EPF2_STRAP4[] = { - { "STRAP_ATOMIC_64BIT_EN_DEV0_F2_", 20, 20, &umr_bitfield_default }, - { "STRAP_ATOMIC_EN_DEV0_F2_", 21, 21, &umr_bitfield_default }, - { "STRAP_FLR_EN_DEV0_F2_", 22, 22, &umr_bitfield_default }, - { "STRAP_PME_SUPPORT_DEV0_F2_", 23, 27, &umr_bitfield_default }, - { "STRAP_INTERRUPT_PIN_DEV0_F2_", 28, 30, &umr_bitfield_default }, - { "STRAP_AUXPWR_SUPPORT_DEV0_F2_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_EPF2_STRAP5[] = { - { "STRAP_SUBSYS_VEN_ID_DEV0_F2_", 0, 15, &umr_bitfield_default }, - { "STRAP_SATAIDP_EN_DEV0_F2_", 24, 24, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_EPF2_STRAP6[] = { - { "STRAP_APER0_EN_DEV0_F2_", 0, 0, &umr_bitfield_default }, - { "STRAP_APER0_PREFETCHABLE_EN_DEV0_F2_", 1, 1, &umr_bitfield_default }, - { "STRAP_APER0_AP_SIZE_DEV0_F2_", 4, 6, &umr_bitfield_default }, - { "STRAP_APER1_EN_DEV0_F2_", 8, 8, &umr_bitfield_default }, - { "STRAP_APER1_PREFETCHABLE_EN_DEV0_F2_", 9, 9, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_EPF2_STRAP13[] = { - { "STRAP_CLASS_CODE_PIF_DEV0_F2_", 0, 7, &umr_bitfield_default }, - { "STRAP_CLASS_CODE_SUB_DEV0_F2_", 8, 15, &umr_bitfield_default }, - { "STRAP_CLASS_CODE_BASE_DEV0_F2_", 16, 23, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_EPF3_STRAP0[] = { - { "STRAP_DEVICE_ID_DEV0_F3_", 0, 15, &umr_bitfield_default }, - { "STRAP_MAJOR_REV_ID_DEV0_F3_", 16, 19, &umr_bitfield_default }, - { "STRAP_MINOR_REV_ID_DEV0_F3_", 20, 23, &umr_bitfield_default }, - { "STRAP_FUNC_EN_DEV0_F3_", 28, 28, &umr_bitfield_default }, - { "STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F3_", 29, 29, &umr_bitfield_default }, - { "STRAP_D1_SUPPORT_DEV0_F3_", 30, 30, &umr_bitfield_default }, - { "STRAP_D2_SUPPORT_DEV0_F3_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_EPF3_STRAP2[] = { - { "STRAP_NO_SOFT_RESET_DEV0_F3_", 7, 7, &umr_bitfield_default }, - { "STRAP_RESIZE_BAR_EN_DEV0_F3_", 8, 8, &umr_bitfield_default }, - { "STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F3_", 14, 14, &umr_bitfield_default }, - { "STRAP_AER_EN_DEV0_F3_", 16, 16, &umr_bitfield_default }, - { "STRAP_ACS_EN_DEV0_F3_", 17, 17, &umr_bitfield_default }, - { "STRAP_CPL_ABORT_ERR_EN_DEV0_F3_", 20, 20, &umr_bitfield_default }, - { "STRAP_DPA_EN_DEV0_F3_", 21, 21, &umr_bitfield_default }, - { "STRAP_VC_EN_DEV0_F3_", 23, 23, &umr_bitfield_default }, - { "STRAP_MSI_MULTI_CAP_DEV0_F3_", 24, 26, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_EPF3_STRAP3[] = { - { "STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F3_", 0, 0, &umr_bitfield_default }, - { "STRAP_PWR_EN_DEV0_F3_", 1, 1, &umr_bitfield_default }, - { "STRAP_SUBSYS_ID_DEV0_F3_", 2, 17, &umr_bitfield_default }, - { "STRAP_MSI_EN_DEV0_F3_", 18, 18, &umr_bitfield_default }, - { "STRAP_MSI_CLR_PENDING_EN_DEV0_F3_", 19, 19, &umr_bitfield_default }, - { "STRAP_MSIX_EN_DEV0_F3_", 20, 20, &umr_bitfield_default }, - { "STRAP_PMC_DSI_DEV0_F3_", 24, 24, &umr_bitfield_default }, - { "STRAP_VENDOR_ID_BIT_DEV0_F3_", 25, 25, &umr_bitfield_default }, - { "STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F3_", 26, 26, &umr_bitfield_default }, - { "STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F3_", 27, 27, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_EPF3_STRAP4[] = { - { "STRAP_ATOMIC_64BIT_EN_DEV0_F3_", 20, 20, &umr_bitfield_default }, - { "STRAP_ATOMIC_EN_DEV0_F3_", 21, 21, &umr_bitfield_default }, - { "STRAP_FLR_EN_DEV0_F3_", 22, 22, &umr_bitfield_default }, - { "STRAP_PME_SUPPORT_DEV0_F3_", 23, 27, &umr_bitfield_default }, - { "STRAP_INTERRUPT_PIN_DEV0_F3_", 28, 30, &umr_bitfield_default }, - { "STRAP_AUXPWR_SUPPORT_DEV0_F3_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_EPF3_STRAP5[] = { - { "STRAP_SUBSYS_VEN_ID_DEV0_F3_", 0, 15, &umr_bitfield_default }, - { "STRAP_USB_DBESEL_DEV0_F3_", 16, 19, &umr_bitfield_default }, - { "STRAP_USB_DBESELD_DEV0_F3_", 20, 23, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_EPF3_STRAP6[] = { - { "STRAP_APER0_EN_DEV0_F3_", 0, 0, &umr_bitfield_default }, - { "STRAP_APER0_PREFETCHABLE_EN_DEV0_F3_", 1, 1, &umr_bitfield_default }, - { "STRAP_APER0_AP_SIZE_DEV0_F3_", 4, 6, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_EPF3_STRAP13[] = { - { "STRAP_CLASS_CODE_PIF_DEV0_F3_", 0, 7, &umr_bitfield_default }, - { "STRAP_CLASS_CODE_SUB_DEV0_F3_", 8, 15, &umr_bitfield_default }, - { "STRAP_CLASS_CODE_BASE_DEV0_F3_", 16, 23, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_EPF4_STRAP0[] = { - { "STRAP_DEVICE_ID_DEV0_F4_", 0, 15, &umr_bitfield_default }, - { "STRAP_MAJOR_REV_ID_DEV0_F4_", 16, 19, &umr_bitfield_default }, - { "STRAP_MINOR_REV_ID_DEV0_F4_", 20, 23, &umr_bitfield_default }, - { "STRAP_FUNC_EN_DEV0_F4_", 28, 28, &umr_bitfield_default }, - { "STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F4_", 29, 29, &umr_bitfield_default }, - { "STRAP_D1_SUPPORT_DEV0_F4_", 30, 30, &umr_bitfield_default }, - { "STRAP_D2_SUPPORT_DEV0_F4_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_EPF4_STRAP2[] = { - { "STRAP_NO_SOFT_RESET_DEV0_F4_", 7, 7, &umr_bitfield_default }, - { "STRAP_RESIZE_BAR_EN_DEV0_F4_", 8, 8, &umr_bitfield_default }, - { "STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F4_", 14, 14, &umr_bitfield_default }, - { "STRAP_AER_EN_DEV0_F4_", 16, 16, &umr_bitfield_default }, - { "STRAP_ACS_EN_DEV0_F4_", 17, 17, &umr_bitfield_default }, - { "STRAP_CPL_ABORT_ERR_EN_DEV0_F4_", 20, 20, &umr_bitfield_default }, - { "STRAP_DPA_EN_DEV0_F4_", 21, 21, &umr_bitfield_default }, - { "STRAP_VC_EN_DEV0_F4_", 23, 23, &umr_bitfield_default }, - { "STRAP_MSI_MULTI_CAP_DEV0_F4_", 24, 26, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_EPF4_STRAP3[] = { - { "STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F4_", 0, 0, &umr_bitfield_default }, - { "STRAP_PWR_EN_DEV0_F4_", 1, 1, &umr_bitfield_default }, - { "STRAP_SUBSYS_ID_DEV0_F4_", 2, 17, &umr_bitfield_default }, - { "STRAP_MSI_EN_DEV0_F4_", 18, 18, &umr_bitfield_default }, - { "STRAP_MSI_CLR_PENDING_EN_DEV0_F4_", 19, 19, &umr_bitfield_default }, - { "STRAP_MSIX_EN_DEV0_F4_", 20, 20, &umr_bitfield_default }, - { "STRAP_PMC_DSI_DEV0_F4_", 24, 24, &umr_bitfield_default }, - { "STRAP_VENDOR_ID_BIT_DEV0_F4_", 25, 25, &umr_bitfield_default }, - { "STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F4_", 26, 26, &umr_bitfield_default }, - { "STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F4_", 27, 27, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_EPF4_STRAP4[] = { - { "STRAP_ATOMIC_64BIT_EN_DEV0_F4_", 20, 20, &umr_bitfield_default }, - { "STRAP_ATOMIC_EN_DEV0_F4_", 21, 21, &umr_bitfield_default }, - { "STRAP_FLR_EN_DEV0_F4_", 22, 22, &umr_bitfield_default }, - { "STRAP_PME_SUPPORT_DEV0_F4_", 23, 27, &umr_bitfield_default }, - { "STRAP_INTERRUPT_PIN_DEV0_F4_", 28, 30, &umr_bitfield_default }, - { "STRAP_AUXPWR_SUPPORT_DEV0_F4_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_EPF4_STRAP5[] = { - { "STRAP_SUBSYS_VEN_ID_DEV0_F4_", 0, 15, &umr_bitfield_default }, - { "STRAP_USB_DBESEL_DEV0_F4_", 16, 19, &umr_bitfield_default }, - { "STRAP_USB_DBESELD_DEV0_F4_", 20, 23, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_EPF4_STRAP6[] = { - { "STRAP_APER0_EN_DEV0_F4_", 0, 0, &umr_bitfield_default }, - { "STRAP_APER0_PREFETCHABLE_EN_DEV0_F4_", 1, 1, &umr_bitfield_default }, - { "STRAP_APER0_AP_SIZE_DEV0_F4_", 4, 6, &umr_bitfield_default }, - { "STRAP_APER1_EN_DEV0_F4_", 8, 8, &umr_bitfield_default }, - { "STRAP_APER1_PREFETCHABLE_EN_DEV0_F4_", 9, 9, &umr_bitfield_default }, - { "STRAP_APER2_EN_DEV0_F4_", 16, 16, &umr_bitfield_default }, - { "STRAP_APER2_PREFETCHABLE_EN_DEV0_F4_", 17, 17, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_EPF4_STRAP13[] = { - { "STRAP_CLASS_CODE_PIF_DEV0_F4_", 0, 7, &umr_bitfield_default }, - { "STRAP_CLASS_CODE_SUB_DEV0_F4_", 8, 15, &umr_bitfield_default }, - { "STRAP_CLASS_CODE_BASE_DEV0_F4_", 16, 23, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_EPF5_STRAP0[] = { - { "STRAP_DEVICE_ID_DEV0_F5_", 0, 15, &umr_bitfield_default }, - { "STRAP_MAJOR_REV_ID_DEV0_F5_", 16, 19, &umr_bitfield_default }, - { "STRAP_MINOR_REV_ID_DEV0_F5_", 20, 23, &umr_bitfield_default }, - { "STRAP_FUNC_EN_DEV0_F5_", 28, 28, &umr_bitfield_default }, - { "STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F5_", 29, 29, &umr_bitfield_default }, - { "STRAP_D1_SUPPORT_DEV0_F5_", 30, 30, &umr_bitfield_default }, - { "STRAP_D2_SUPPORT_DEV0_F5_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_EPF5_STRAP2[] = { - { "STRAP_NO_SOFT_RESET_DEV0_F5_", 7, 7, &umr_bitfield_default }, - { "STRAP_RESIZE_BAR_EN_DEV0_F5_", 8, 8, &umr_bitfield_default }, - { "STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F5_", 14, 14, &umr_bitfield_default }, - { "STRAP_AER_EN_DEV0_F5_", 16, 16, &umr_bitfield_default }, - { "STRAP_ACS_EN_DEV0_F5_", 17, 17, &umr_bitfield_default }, - { "STRAP_CPL_ABORT_ERR_EN_DEV0_F5_", 20, 20, &umr_bitfield_default }, - { "STRAP_DPA_EN_DEV0_F5_", 21, 21, &umr_bitfield_default }, - { "STRAP_VC_EN_DEV0_F5_", 23, 23, &umr_bitfield_default }, - { "STRAP_MSI_MULTI_CAP_DEV0_F5_", 24, 26, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_EPF5_STRAP3[] = { - { "STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F5_", 0, 0, &umr_bitfield_default }, - { "STRAP_PWR_EN_DEV0_F5_", 1, 1, &umr_bitfield_default }, - { "STRAP_SUBSYS_ID_DEV0_F5_", 2, 17, &umr_bitfield_default }, - { "STRAP_MSI_EN_DEV0_F5_", 18, 18, &umr_bitfield_default }, - { "STRAP_MSI_CLR_PENDING_EN_DEV0_F5_", 19, 19, &umr_bitfield_default }, - { "STRAP_MSIX_EN_DEV0_F5_", 20, 20, &umr_bitfield_default }, - { "STRAP_PMC_DSI_DEV0_F5_", 24, 24, &umr_bitfield_default }, - { "STRAP_VENDOR_ID_BIT_DEV0_F5_", 25, 25, &umr_bitfield_default }, - { "STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F5_", 26, 26, &umr_bitfield_default }, - { "STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F5_", 27, 27, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_EPF5_STRAP4[] = { - { "STRAP_ATOMIC_64BIT_EN_DEV0_F5_", 20, 20, &umr_bitfield_default }, - { "STRAP_ATOMIC_EN_DEV0_F5_", 21, 21, &umr_bitfield_default }, - { "STRAP_FLR_EN_DEV0_F5_", 22, 22, &umr_bitfield_default }, - { "STRAP_PME_SUPPORT_DEV0_F5_", 23, 27, &umr_bitfield_default }, - { "STRAP_INTERRUPT_PIN_DEV0_F5_", 28, 30, &umr_bitfield_default }, - { "STRAP_AUXPWR_SUPPORT_DEV0_F5_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_EPF5_STRAP5[] = { - { "STRAP_SUBSYS_VEN_ID_DEV0_F5_", 0, 15, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_EPF5_STRAP6[] = { - { "STRAP_APER0_EN_DEV0_F5_", 0, 0, &umr_bitfield_default }, - { "STRAP_APER0_PREFETCHABLE_EN_DEV0_F5_", 1, 1, &umr_bitfield_default }, - { "STRAP_APER0_AP_SIZE_DEV0_F5_", 4, 6, &umr_bitfield_default }, - { "STRAP_APER1_EN_DEV0_F5_", 8, 8, &umr_bitfield_default }, - { "STRAP_APER1_PREFETCHABLE_EN_DEV0_F5_", 9, 9, &umr_bitfield_default }, - { "STRAP_APER2_EN_DEV0_F5_", 16, 16, &umr_bitfield_default }, - { "STRAP_APER2_PREFETCHABLE_EN_DEV0_F5_", 17, 17, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_EPF5_STRAP13[] = { - { "STRAP_CLASS_CODE_PIF_DEV0_F5_", 0, 7, &umr_bitfield_default }, - { "STRAP_CLASS_CODE_SUB_DEV0_F5_", 8, 15, &umr_bitfield_default }, - { "STRAP_CLASS_CODE_BASE_DEV0_F5_", 16, 23, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_EPF6_STRAP0[] = { - { "STRAP_DEVICE_ID_DEV0_F6_", 0, 15, &umr_bitfield_default }, - { "STRAP_MAJOR_REV_ID_DEV0_F6_", 16, 19, &umr_bitfield_default }, - { "STRAP_MINOR_REV_ID_DEV0_F6_", 20, 23, &umr_bitfield_default }, - { "STRAP_FUNC_EN_DEV0_F6_", 28, 28, &umr_bitfield_default }, - { "STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F6_", 29, 29, &umr_bitfield_default }, - { "STRAP_D1_SUPPORT_DEV0_F6_", 30, 30, &umr_bitfield_default }, - { "STRAP_D2_SUPPORT_DEV0_F6_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_EPF6_STRAP2[] = { - { "STRAP_NO_SOFT_RESET_DEV0_F6_", 7, 7, &umr_bitfield_default }, - { "STRAP_RESIZE_BAR_EN_DEV0_F6_", 8, 8, &umr_bitfield_default }, - { "STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F6_", 14, 14, &umr_bitfield_default }, - { "STRAP_AER_EN_DEV0_F6_", 16, 16, &umr_bitfield_default }, - { "STRAP_ACS_EN_DEV0_F6_", 17, 17, &umr_bitfield_default }, - { "STRAP_CPL_ABORT_ERR_EN_DEV0_F6_", 20, 20, &umr_bitfield_default }, - { "STRAP_DPA_EN_DEV0_F6_", 21, 21, &umr_bitfield_default }, - { "STRAP_VC_EN_DEV0_F6_", 23, 23, &umr_bitfield_default }, - { "STRAP_MSI_MULTI_CAP_DEV0_F6_", 24, 26, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_EPF6_STRAP3[] = { - { "STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F6_", 0, 0, &umr_bitfield_default }, - { "STRAP_PWR_EN_DEV0_F6_", 1, 1, &umr_bitfield_default }, - { "STRAP_SUBSYS_ID_DEV0_F6_", 2, 17, &umr_bitfield_default }, - { "STRAP_MSI_EN_DEV0_F6_", 18, 18, &umr_bitfield_default }, - { "STRAP_MSI_CLR_PENDING_EN_DEV0_F6_", 19, 19, &umr_bitfield_default }, - { "STRAP_MSIX_EN_DEV0_F6_", 20, 20, &umr_bitfield_default }, - { "STRAP_PMC_DSI_DEV0_F6_", 24, 24, &umr_bitfield_default }, - { "STRAP_VENDOR_ID_BIT_DEV0_F6_", 25, 25, &umr_bitfield_default }, - { "STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F6_", 26, 26, &umr_bitfield_default }, - { "STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F6_", 27, 27, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_EPF6_STRAP4[] = { - { "STRAP_ATOMIC_64BIT_EN_DEV0_F6_", 20, 20, &umr_bitfield_default }, - { "STRAP_ATOMIC_EN_DEV0_F6_", 21, 21, &umr_bitfield_default }, - { "STRAP_FLR_EN_DEV0_F6_", 22, 22, &umr_bitfield_default }, - { "STRAP_PME_SUPPORT_DEV0_F6_", 23, 27, &umr_bitfield_default }, - { "STRAP_INTERRUPT_PIN_DEV0_F6_", 28, 30, &umr_bitfield_default }, - { "STRAP_AUXPWR_SUPPORT_DEV0_F6_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_EPF6_STRAP5[] = { - { "STRAP_SUBSYS_VEN_ID_DEV0_F6_", 0, 15, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_EPF6_STRAP6[] = { - { "STRAP_APER0_EN_DEV0_F6_", 0, 0, &umr_bitfield_default }, - { "STRAP_APER0_PREFETCHABLE_EN_DEV0_F6_", 1, 1, &umr_bitfield_default }, - { "STRAP_APER0_AP_SIZE_DEV0_F6_", 4, 6, &umr_bitfield_default }, - { "STRAP_APER1_EN_DEV0_F6_", 8, 8, &umr_bitfield_default }, - { "STRAP_APER1_PREFETCHABLE_EN_DEV0_F6_", 9, 9, &umr_bitfield_default }, - { "STRAP_APER2_EN_DEV0_F6_", 16, 16, &umr_bitfield_default }, - { "STRAP_APER2_PREFETCHABLE_EN_DEV0_F6_", 17, 17, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_EPF6_STRAP13[] = { - { "STRAP_CLASS_CODE_PIF_DEV0_F6_", 0, 7, &umr_bitfield_default }, - { "STRAP_CLASS_CODE_SUB_DEV0_F6_", 8, 15, &umr_bitfield_default }, - { "STRAP_CLASS_CODE_BASE_DEV0_F6_", 16, 23, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_EPF7_STRAP0[] = { - { "STRAP_DEVICE_ID_DEV0_F7_", 0, 15, &umr_bitfield_default }, - { "STRAP_MAJOR_REV_ID_DEV0_F7_", 16, 19, &umr_bitfield_default }, - { "STRAP_MINOR_REV_ID_DEV0_F7_", 20, 23, &umr_bitfield_default }, - { "STRAP_FUNC_EN_DEV0_F7_", 28, 28, &umr_bitfield_default }, - { "STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F7_", 29, 29, &umr_bitfield_default }, - { "STRAP_D1_SUPPORT_DEV0_F7_", 30, 30, &umr_bitfield_default }, - { "STRAP_D2_SUPPORT_DEV0_F7_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_EPF7_STRAP2[] = { - { "STRAP_NO_SOFT_RESET_DEV0_F7_", 7, 7, &umr_bitfield_default }, - { "STRAP_RESIZE_BAR_EN_DEV0_F7_", 8, 8, &umr_bitfield_default }, - { "STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F7_", 14, 14, &umr_bitfield_default }, - { "STRAP_AER_EN_DEV0_F7_", 16, 16, &umr_bitfield_default }, - { "STRAP_ACS_EN_DEV0_F7_", 17, 17, &umr_bitfield_default }, - { "STRAP_CPL_ABORT_ERR_EN_DEV0_F7_", 20, 20, &umr_bitfield_default }, - { "STRAP_DPA_EN_DEV0_F7_", 21, 21, &umr_bitfield_default }, - { "STRAP_VC_EN_DEV0_F7_", 23, 23, &umr_bitfield_default }, - { "STRAP_MSI_MULTI_CAP_DEV0_F7_", 24, 26, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_EPF7_STRAP3[] = { - { "STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F7_", 0, 0, &umr_bitfield_default }, - { "STRAP_PWR_EN_DEV0_F7_", 1, 1, &umr_bitfield_default }, - { "STRAP_SUBSYS_ID_DEV0_F7_", 2, 17, &umr_bitfield_default }, - { "STRAP_MSI_EN_DEV0_F7_", 18, 18, &umr_bitfield_default }, - { "STRAP_MSI_CLR_PENDING_EN_DEV0_F7_", 19, 19, &umr_bitfield_default }, - { "STRAP_MSIX_EN_DEV0_F7_", 20, 20, &umr_bitfield_default }, - { "STRAP_PMC_DSI_DEV0_F7_", 24, 24, &umr_bitfield_default }, - { "STRAP_VENDOR_ID_BIT_DEV0_F7_", 25, 25, &umr_bitfield_default }, - { "STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F7_", 26, 26, &umr_bitfield_default }, - { "STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F7_", 27, 27, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_EPF7_STRAP4[] = { - { "STRAP_ATOMIC_64BIT_EN_DEV0_F7_", 20, 20, &umr_bitfield_default }, - { "STRAP_ATOMIC_EN_DEV0_F7_", 21, 21, &umr_bitfield_default }, - { "STRAP_FLR_EN_DEV0_F7_", 22, 22, &umr_bitfield_default }, - { "STRAP_PME_SUPPORT_DEV0_F7_", 23, 27, &umr_bitfield_default }, - { "STRAP_INTERRUPT_PIN_DEV0_F7_", 28, 30, &umr_bitfield_default }, - { "STRAP_AUXPWR_SUPPORT_DEV0_F7_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_EPF7_STRAP5[] = { - { "STRAP_SUBSYS_VEN_ID_DEV0_F7_", 0, 15, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_EPF7_STRAP6[] = { - { "STRAP_APER0_EN_DEV0_F7_", 0, 0, &umr_bitfield_default }, - { "STRAP_APER0_PREFETCHABLE_EN_DEV0_F7_", 1, 1, &umr_bitfield_default }, - { "STRAP_APER0_AP_SIZE_DEV0_F7_", 4, 6, &umr_bitfield_default }, - { "STRAP_APER1_EN_DEV0_F7_", 8, 8, &umr_bitfield_default }, - { "STRAP_APER1_PREFETCHABLE_EN_DEV0_F7_", 9, 9, &umr_bitfield_default }, - { "STRAP_APER2_EN_DEV0_F7_", 16, 16, &umr_bitfield_default }, - { "STRAP_APER2_PREFETCHABLE_EN_DEV0_F7_", 17, 17, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV0_EPF7_STRAP13[] = { - { "STRAP_CLASS_CODE_PIF_DEV0_F7_", 0, 7, &umr_bitfield_default }, - { "STRAP_CLASS_CODE_SUB_DEV0_F7_", 8, 15, &umr_bitfield_default }, - { "STRAP_CLASS_CODE_BASE_DEV0_F7_", 16, 23, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV1_EPF0_STRAP0[] = { - { "STRAP_DEVICE_ID_DEV1_F0_", 0, 15, &umr_bitfield_default }, - { "STRAP_MAJOR_REV_ID_DEV1_F0_", 16, 19, &umr_bitfield_default }, - { "STRAP_MINOR_REV_ID_DEV1_F0_", 20, 23, &umr_bitfield_default }, - { "STRAP_FUNC_EN_DEV1_F0_", 28, 28, &umr_bitfield_default }, - { "STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F0_", 29, 29, &umr_bitfield_default }, - { "STRAP_D1_SUPPORT_DEV1_F0_", 30, 30, &umr_bitfield_default }, - { "STRAP_D2_SUPPORT_DEV1_F0_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV1_EPF0_STRAP2[] = { - { "STRAP_NO_SOFT_RESET_DEV1_F0_", 7, 7, &umr_bitfield_default }, - { "STRAP_RESIZE_BAR_EN_DEV1_F0_", 8, 8, &umr_bitfield_default }, - { "STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F0_", 14, 14, &umr_bitfield_default }, - { "STRAP_ARI_EN_DEV1_F0_", 15, 15, &umr_bitfield_default }, - { "STRAP_AER_EN_DEV1_F0_", 16, 16, &umr_bitfield_default }, - { "STRAP_ACS_EN_DEV1_F0_", 17, 17, &umr_bitfield_default }, - { "STRAP_CPL_ABORT_ERR_EN_DEV1_F0_", 20, 20, &umr_bitfield_default }, - { "STRAP_DPA_EN_DEV1_F0_", 21, 21, &umr_bitfield_default }, - { "STRAP_VC_EN_DEV1_F0_", 23, 23, &umr_bitfield_default }, - { "STRAP_MSI_MULTI_CAP_DEV1_F0_", 24, 26, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV1_EPF0_STRAP3[] = { - { "STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F0_", 0, 0, &umr_bitfield_default }, - { "STRAP_PWR_EN_DEV1_F0_", 1, 1, &umr_bitfield_default }, - { "STRAP_SUBSYS_ID_DEV1_F0_", 2, 17, &umr_bitfield_default }, - { "STRAP_MSI_EN_DEV1_F0_", 18, 18, &umr_bitfield_default }, - { "STRAP_MSI_CLR_PENDING_EN_DEV1_F0_", 19, 19, &umr_bitfield_default }, - { "STRAP_MSIX_EN_DEV1_F0_", 20, 20, &umr_bitfield_default }, - { "STRAP_PMC_DSI_DEV1_F0_", 24, 24, &umr_bitfield_default }, - { "STRAP_VENDOR_ID_BIT_DEV1_F0_", 25, 25, &umr_bitfield_default }, - { "STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F0_", 26, 26, &umr_bitfield_default }, - { "STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F0_", 27, 27, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV1_EPF0_STRAP4[] = { - { "STRAP_ATOMIC_64BIT_EN_DEV1_F0_", 20, 20, &umr_bitfield_default }, - { "STRAP_ATOMIC_EN_DEV1_F0_", 21, 21, &umr_bitfield_default }, - { "STRAP_FLR_EN_DEV1_F0_", 22, 22, &umr_bitfield_default }, - { "STRAP_PME_SUPPORT_DEV1_F0_", 23, 27, &umr_bitfield_default }, - { "STRAP_INTERRUPT_PIN_DEV1_F0_", 28, 30, &umr_bitfield_default }, - { "STRAP_AUXPWR_SUPPORT_DEV1_F0_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV1_EPF0_STRAP5[] = { - { "STRAP_SUBSYS_VEN_ID_DEV1_F0_", 0, 15, &umr_bitfield_default }, - { "STRAP_SATAIDP_EN_DEV1_F0_", 24, 24, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV1_EPF0_STRAP6[] = { - { "STRAP_APER0_EN_DEV1_F0_", 0, 0, &umr_bitfield_default }, - { "STRAP_APER0_PREFETCHABLE_EN_DEV1_F0_", 1, 1, &umr_bitfield_default }, - { "STRAP_APER0_AP_SIZE_DEV1_F0_", 4, 6, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV1_EPF0_STRAP13[] = { - { "STRAP_CLASS_CODE_PIF_DEV1_F0_", 0, 7, &umr_bitfield_default }, - { "STRAP_CLASS_CODE_SUB_DEV1_F0_", 8, 15, &umr_bitfield_default }, - { "STRAP_CLASS_CODE_BASE_DEV1_F0_", 16, 23, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV1_EPF1_STRAP0[] = { - { "STRAP_DEVICE_ID_DEV1_F1_", 0, 15, &umr_bitfield_default }, - { "STRAP_MAJOR_REV_ID_DEV1_F1_", 16, 19, &umr_bitfield_default }, - { "STRAP_MINOR_REV_ID_DEV1_F1_", 20, 23, &umr_bitfield_default }, - { "STRAP_FUNC_EN_DEV1_F1_", 28, 28, &umr_bitfield_default }, - { "STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F1_", 29, 29, &umr_bitfield_default }, - { "STRAP_D1_SUPPORT_DEV1_F1_", 30, 30, &umr_bitfield_default }, - { "STRAP_D2_SUPPORT_DEV1_F1_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV1_EPF1_STRAP2[] = { - { "STRAP_NO_SOFT_RESET_DEV1_F1_", 7, 7, &umr_bitfield_default }, - { "STRAP_RESIZE_BAR_EN_DEV1_F1_", 8, 8, &umr_bitfield_default }, - { "STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F1_", 14, 14, &umr_bitfield_default }, - { "STRAP_AER_EN_DEV1_F1_", 16, 16, &umr_bitfield_default }, - { "STRAP_ACS_EN_DEV1_F1_", 17, 17, &umr_bitfield_default }, - { "STRAP_CPL_ABORT_ERR_EN_DEV1_F1_", 20, 20, &umr_bitfield_default }, - { "STRAP_DPA_EN_DEV1_F1_", 21, 21, &umr_bitfield_default }, - { "STRAP_VC_EN_DEV1_F1_", 23, 23, &umr_bitfield_default }, - { "STRAP_MSI_MULTI_CAP_DEV1_F1_", 24, 26, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV1_EPF1_STRAP3[] = { - { "STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F1_", 0, 0, &umr_bitfield_default }, - { "STRAP_PWR_EN_DEV1_F1_", 1, 1, &umr_bitfield_default }, - { "STRAP_SUBSYS_ID_DEV1_F1_", 2, 17, &umr_bitfield_default }, - { "STRAP_MSI_EN_DEV1_F1_", 18, 18, &umr_bitfield_default }, - { "STRAP_MSI_CLR_PENDING_EN_DEV1_F1_", 19, 19, &umr_bitfield_default }, - { "STRAP_MSIX_EN_DEV1_F1_", 20, 20, &umr_bitfield_default }, - { "STRAP_PMC_DSI_DEV1_F1_", 24, 24, &umr_bitfield_default }, - { "STRAP_VENDOR_ID_BIT_DEV1_F1_", 25, 25, &umr_bitfield_default }, - { "STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F1_", 26, 26, &umr_bitfield_default }, - { "STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F1_", 27, 27, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV1_EPF1_STRAP4[] = { - { "STRAP_ATOMIC_64BIT_EN_DEV1_F1_", 20, 20, &umr_bitfield_default }, - { "STRAP_ATOMIC_EN_DEV1_F1_", 21, 21, &umr_bitfield_default }, - { "STRAP_FLR_EN_DEV1_F1_", 22, 22, &umr_bitfield_default }, - { "STRAP_PME_SUPPORT_DEV1_F1_", 23, 27, &umr_bitfield_default }, - { "STRAP_INTERRUPT_PIN_DEV1_F1_", 28, 30, &umr_bitfield_default }, - { "STRAP_AUXPWR_SUPPORT_DEV1_F1_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV1_EPF1_STRAP5[] = { - { "STRAP_SUBSYS_VEN_ID_DEV1_F1_", 0, 15, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV1_EPF1_STRAP6[] = { - { "STRAP_APER0_EN_DEV1_F1_", 0, 0, &umr_bitfield_default }, - { "STRAP_APER0_PREFETCHABLE_EN_DEV1_F1_", 1, 1, &umr_bitfield_default }, - { "STRAP_APER0_AP_SIZE_DEV1_F1_", 4, 6, &umr_bitfield_default }, - { "STRAP_APER1_EN_DEV1_F1_", 8, 8, &umr_bitfield_default }, - { "STRAP_APER1_PREFETCHABLE_EN_DEV1_F1_", 9, 9, &umr_bitfield_default }, - { "STRAP_APER2_EN_DEV1_F1_", 16, 16, &umr_bitfield_default }, - { "STRAP_APER2_PREFETCHABLE_EN_DEV1_F1_", 17, 17, &umr_bitfield_default }, - { "STRAP_APER3_EN_DEV1_F1_", 24, 24, &umr_bitfield_default }, - { "STRAP_APER3_PREFETCHABLE_EN_DEV1_F1_", 25, 25, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV1_EPF1_STRAP13[] = { - { "STRAP_CLASS_CODE_PIF_DEV1_F1_", 0, 7, &umr_bitfield_default }, - { "STRAP_CLASS_CODE_SUB_DEV1_F1_", 8, 15, &umr_bitfield_default }, - { "STRAP_CLASS_CODE_BASE_DEV1_F1_", 16, 23, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV1_EPF2_STRAP0[] = { - { "STRAP_DEVICE_ID_DEV1_F2_", 0, 15, &umr_bitfield_default }, - { "STRAP_MAJOR_REV_ID_DEV1_F2_", 16, 19, &umr_bitfield_default }, - { "STRAP_MINOR_REV_ID_DEV1_F2_", 20, 23, &umr_bitfield_default }, - { "STRAP_FUNC_EN_DEV1_F2_", 28, 28, &umr_bitfield_default }, - { "STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F2_", 29, 29, &umr_bitfield_default }, - { "STRAP_D1_SUPPORT_DEV1_F2_", 30, 30, &umr_bitfield_default }, - { "STRAP_D2_SUPPORT_DEV1_F2_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV1_EPF2_STRAP2[] = { - { "STRAP_NO_SOFT_RESET_DEV1_F2_", 7, 7, &umr_bitfield_default }, - { "STRAP_RESIZE_BAR_EN_DEV1_F2_", 8, 8, &umr_bitfield_default }, - { "STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F2_", 14, 14, &umr_bitfield_default }, - { "STRAP_AER_EN_DEV1_F2_", 16, 16, &umr_bitfield_default }, - { "STRAP_ACS_EN_DEV1_F2_", 17, 17, &umr_bitfield_default }, - { "STRAP_CPL_ABORT_ERR_EN_DEV1_F2_", 20, 20, &umr_bitfield_default }, - { "STRAP_DPA_EN_DEV1_F2_", 21, 21, &umr_bitfield_default }, - { "STRAP_VC_EN_DEV1_F2_", 23, 23, &umr_bitfield_default }, - { "STRAP_MSI_MULTI_CAP_DEV1_F2_", 24, 26, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV1_EPF2_STRAP3[] = { - { "STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F2_", 0, 0, &umr_bitfield_default }, - { "STRAP_PWR_EN_DEV1_F2_", 1, 1, &umr_bitfield_default }, - { "STRAP_SUBSYS_ID_DEV1_F2_", 2, 17, &umr_bitfield_default }, - { "STRAP_MSI_EN_DEV1_F2_", 18, 18, &umr_bitfield_default }, - { "STRAP_MSI_CLR_PENDING_EN_DEV1_F2_", 19, 19, &umr_bitfield_default }, - { "STRAP_MSIX_EN_DEV1_F2_", 20, 20, &umr_bitfield_default }, - { "STRAP_PMC_DSI_DEV1_F2_", 24, 24, &umr_bitfield_default }, - { "STRAP_VENDOR_ID_BIT_DEV1_F2_", 25, 25, &umr_bitfield_default }, - { "STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F2_", 26, 26, &umr_bitfield_default }, - { "STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F2_", 27, 27, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV1_EPF2_STRAP4[] = { - { "STRAP_ATOMIC_64BIT_EN_DEV1_F2_", 20, 20, &umr_bitfield_default }, - { "STRAP_ATOMIC_EN_DEV1_F2_", 21, 21, &umr_bitfield_default }, - { "STRAP_FLR_EN_DEV1_F2_", 22, 22, &umr_bitfield_default }, - { "STRAP_PME_SUPPORT_DEV1_F2_", 23, 27, &umr_bitfield_default }, - { "STRAP_INTERRUPT_PIN_DEV1_F2_", 28, 30, &umr_bitfield_default }, - { "STRAP_AUXPWR_SUPPORT_DEV1_F2_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV1_EPF2_STRAP5[] = { - { "STRAP_SUBSYS_VEN_ID_DEV1_F2_", 0, 15, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV1_EPF2_STRAP6[] = { - { "STRAP_APER0_EN_DEV1_F2_", 0, 0, &umr_bitfield_default }, - { "STRAP_APER0_PREFETCHABLE_EN_DEV1_F2_", 1, 1, &umr_bitfield_default }, - { "STRAP_APER0_AP_SIZE_DEV1_F2_", 4, 6, &umr_bitfield_default }, - { "STRAP_APER1_EN_DEV1_F2_", 8, 8, &umr_bitfield_default }, - { "STRAP_APER1_PREFETCHABLE_EN_DEV1_F2_", 9, 9, &umr_bitfield_default }, - { "STRAP_APER2_EN_DEV1_F2_", 16, 16, &umr_bitfield_default }, - { "STRAP_APER2_PREFETCHABLE_EN_DEV1_F2_", 17, 17, &umr_bitfield_default }, - { "STRAP_APER3_EN_DEV1_F2_", 24, 24, &umr_bitfield_default }, - { "STRAP_APER3_PREFETCHABLE_EN_DEV1_F2_", 25, 25, &umr_bitfield_default }, -}; -static struct umr_bitfield mmRCC_DEV1_EPF2_STRAP13[] = { - { "STRAP_CLASS_CODE_PIF_DEV1_F2_", 0, 7, &umr_bitfield_default }, - { "STRAP_CLASS_CODE_SUB_DEV1_F2_", 8, 15, &umr_bitfield_default }, - { "STRAP_CLASS_CODE_BASE_DEV1_F2_", 16, 23, &umr_bitfield_default }, -}; -static struct umr_bitfield ixHARD_RST_CTRL[] = { - { "DSPT_CFG_RST_EN_", 0, 0, &umr_bitfield_default }, - { "DSPT_CFG_STICKY_RST_EN_", 1, 1, &umr_bitfield_default }, - { "DSPT_PRV_RST_EN_", 2, 2, &umr_bitfield_default }, - { "DSPT_PRV_STICKY_RST_EN_", 3, 3, &umr_bitfield_default }, - { "EP_CFG_RST_EN_", 4, 4, &umr_bitfield_default }, - { "EP_CFG_STICKY_RST_EN_", 5, 5, &umr_bitfield_default }, - { "EP_PRV_RST_EN_", 6, 6, &umr_bitfield_default }, - { "EP_PRV_STICKY_RST_EN_", 7, 7, &umr_bitfield_default }, - { "SWUS_SHADOW_RST_EN_", 28, 28, &umr_bitfield_default }, - { "CORE_STICKY_RST_EN_", 29, 29, &umr_bitfield_default }, - { "RELOAD_STRAP_EN_", 30, 30, &umr_bitfield_default }, - { "CORE_RST_EN_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixRSMU_SOFT_RST_CTRL[] = { - { "DSPT_CFG_RST_EN_", 0, 0, &umr_bitfield_default }, - { "DSPT_CFG_STICKY_RST_EN_", 1, 1, &umr_bitfield_default }, - { "DSPT_PRV_RST_EN_", 2, 2, &umr_bitfield_default }, - { "DSPT_PRV_STICKY_RST_EN_", 3, 3, &umr_bitfield_default }, - { "EP_CFG_RST_EN_", 4, 4, &umr_bitfield_default }, - { "EP_CFG_STICKY_RST_EN_", 5, 5, &umr_bitfield_default }, - { "EP_PRV_RST_EN_", 6, 6, &umr_bitfield_default }, - { "EP_PRV_STICKY_RST_EN_", 7, 7, &umr_bitfield_default }, - { "SWUS_SHADOW_RST_EN_", 28, 28, &umr_bitfield_default }, - { "CORE_STICKY_RST_EN_", 29, 29, &umr_bitfield_default }, - { "RELOAD_STRAP_EN_", 30, 30, &umr_bitfield_default }, - { "CORE_RST_EN_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSELF_SOFT_RST[] = { - { "DSPT0_CFG_RST_", 0, 0, &umr_bitfield_default }, - { "DSPT0_CFG_STICKY_RST_", 1, 1, &umr_bitfield_default }, - { "DSPT0_PRV_RST_", 2, 2, &umr_bitfield_default }, - { "DSPT0_PRV_STICKY_RST_", 3, 3, &umr_bitfield_default }, - { "EP0_CFG_RST_", 4, 4, &umr_bitfield_default }, - { "EP0_CFG_STICKY_RST_", 5, 5, &umr_bitfield_default }, - { "EP0_PRV_RST_", 6, 6, &umr_bitfield_default }, - { "EP0_PRV_STICKY_RST_", 7, 7, &umr_bitfield_default }, - { "SDP_PORT_RST_", 27, 27, &umr_bitfield_default }, - { "SWUS_SHADOW_RST_", 28, 28, &umr_bitfield_default }, - { "CORE_STICKY_RST_", 29, 29, &umr_bitfield_default }, - { "RELOAD_STRAP_", 30, 30, &umr_bitfield_default }, - { "CORE_RST_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixGFX_DRV_MODE1_RST_CTRL[] = { - { "DRV_MODE1_PF_CFG_RST_", 0, 0, &umr_bitfield_default }, - { "DRV_MODE1_PF_CFG_FLR_EXC_RST_", 1, 1, &umr_bitfield_default }, - { "DRV_MODE1_PF_CFG_STICKY_RST_", 2, 2, &umr_bitfield_default }, - { "DRV_MODE1_PF_PRV_RST_", 3, 3, &umr_bitfield_default }, - { "DRV_MODE1_PF_PRV_STICKY_RST_", 4, 4, &umr_bitfield_default }, - { "DRV_MODE1_VF_CFG_RST_", 5, 5, &umr_bitfield_default }, - { "DRV_MODE1_VF_CFG_STICKY_RST_", 6, 6, &umr_bitfield_default }, - { "DRV_MODE1_VF_PRV_RST_", 7, 7, &umr_bitfield_default }, -}; -static struct umr_bitfield ixBIF_RST_MISC_CTRL[] = { - { "ERRSTATUS_KEPT_IN_PERSTB_", 0, 0, &umr_bitfield_default }, - { "DRV_RST_MODE_", 2, 3, &umr_bitfield_default }, - { "DRV_RST_CFG_MASK_", 4, 4, &umr_bitfield_default }, - { "DRV_RST_BITS_AUTO_CLEAR_", 5, 5, &umr_bitfield_default }, - { "FLR_RST_BIT_AUTO_CLEAR_", 6, 6, &umr_bitfield_default }, - { "STRAP_EP_LNK_RST_IOV_EN_", 8, 8, &umr_bitfield_default }, - { "LNK_RST_GRACE_MODE_", 9, 9, &umr_bitfield_default }, - { "LNK_RST_GRACE_TIMEOUT_", 10, 12, &umr_bitfield_default }, - { "LNK_RST_TIMER_SEL_", 13, 14, &umr_bitfield_default }, - { "LNK_RST_TIMER2_SEL_", 15, 16, &umr_bitfield_default }, - { "SRIOV_SAVE_VFS_ON_VFENABLE_CLR_", 17, 18, &umr_bitfield_default }, - { "LNK_RST_DMA_DUMMY_DIS_", 23, 23, &umr_bitfield_default }, - { "LNK_RST_DMA_DUMMY_RSPSTS_", 24, 25, &umr_bitfield_default }, -}; -static struct umr_bitfield ixBIF_RST_MISC_CTRL2[] = { - { "SWUS_LNK_RST_TRANS_IDLE_", 16, 16, &umr_bitfield_default }, - { "SWDS_LNK_RST_TRANS_IDLE_", 17, 17, &umr_bitfield_default }, - { "ENDP0_LNK_RST_TRANS_IDLE_", 18, 18, &umr_bitfield_default }, - { "ALL_RST_TRANS_IDLE_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixBIF_RST_MISC_CTRL3[] = { - { "TIMER_SCALE_", 0, 3, &umr_bitfield_default }, - { "PME_TURNOFF_TIMEOUT_", 4, 5, &umr_bitfield_default }, - { "PME_TURNOFF_MODE_", 6, 6, &umr_bitfield_default }, - { "RELOAD_STRAP_DELAY_HARD_", 7, 9, &umr_bitfield_default }, - { "RELOAD_STRAP_DELAY_SOFT_", 10, 12, &umr_bitfield_default }, - { "RELOAD_STRAP_DELAY_SELF_", 13, 15, &umr_bitfield_default }, -}; -static struct umr_bitfield ixBIF_RST_GFXVF_FLR_IDLE[] = { - { "VF0_TRANS_IDLE_", 0, 0, &umr_bitfield_default }, - { "VF1_TRANS_IDLE_", 1, 1, &umr_bitfield_default }, - { "VF2_TRANS_IDLE_", 2, 2, &umr_bitfield_default }, - { "VF3_TRANS_IDLE_", 3, 3, &umr_bitfield_default }, - { "VF4_TRANS_IDLE_", 4, 4, &umr_bitfield_default }, - { "VF5_TRANS_IDLE_", 5, 5, &umr_bitfield_default }, - { "VF6_TRANS_IDLE_", 6, 6, &umr_bitfield_default }, - { "VF7_TRANS_IDLE_", 7, 7, &umr_bitfield_default }, - { "VF8_TRANS_IDLE_", 8, 8, &umr_bitfield_default }, - { "VF9_TRANS_IDLE_", 9, 9, &umr_bitfield_default }, - { "VF10_TRANS_IDLE_", 10, 10, &umr_bitfield_default }, - { "VF11_TRANS_IDLE_", 11, 11, &umr_bitfield_default }, - { "VF12_TRANS_IDLE_", 12, 12, &umr_bitfield_default }, - { "VF13_TRANS_IDLE_", 13, 13, &umr_bitfield_default }, - { "VF14_TRANS_IDLE_", 14, 14, &umr_bitfield_default }, - { "VF15_TRANS_IDLE_", 15, 15, &umr_bitfield_default }, - { "SOFTPF_TRANS_IDLE_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixDEV0_PF0_FLR_RST_CTRL[] = { - { "PF_CFG_EN_", 0, 0, &umr_bitfield_default }, - { "PF_CFG_FLR_EXC_EN_", 1, 1, &umr_bitfield_default }, - { "PF_CFG_STICKY_EN_", 2, 2, &umr_bitfield_default }, - { "PF_PRV_EN_", 3, 3, &umr_bitfield_default }, - { "PF_PRV_STICKY_EN_", 4, 4, &umr_bitfield_default }, - { "VF_CFG_EN_", 5, 5, &umr_bitfield_default }, - { "VF_CFG_STICKY_EN_", 6, 6, &umr_bitfield_default }, - { "VF_PRV_EN_", 7, 7, &umr_bitfield_default }, - { "SOFT_PF_CFG_EN_", 8, 8, &umr_bitfield_default }, - { "SOFT_PF_CFG_FLR_EXC_EN_", 9, 9, &umr_bitfield_default }, - { "SOFT_PF_CFG_STICKY_EN_", 10, 10, &umr_bitfield_default }, - { "SOFT_PF_PRV_EN_", 11, 11, &umr_bitfield_default }, - { "SOFT_PF_PRV_STICKY_EN_", 12, 12, &umr_bitfield_default }, - { "VF_VF_CFG_EN_", 13, 13, &umr_bitfield_default }, - { "VF_VF_CFG_STICKY_EN_", 14, 14, &umr_bitfield_default }, - { "VF_VF_PRV_EN_", 15, 15, &umr_bitfield_default }, - { "FLR_TWICE_EN_", 16, 16, &umr_bitfield_default }, - { "FLR_GRACE_MODE_", 17, 17, &umr_bitfield_default }, - { "FLR_GRACE_TIMEOUT_", 18, 20, &umr_bitfield_default }, - { "FLR_DMA_DUMMY_RSPSTS_", 23, 24, &umr_bitfield_default }, - { "FLR_HST_DUMMY_RSPSTS_", 25, 26, &umr_bitfield_default }, -}; -static struct umr_bitfield ixDEV0_PF1_FLR_RST_CTRL[] = { - { "PF_CFG_EN_", 0, 0, &umr_bitfield_default }, - { "PF_CFG_FLR_EXC_EN_", 1, 1, &umr_bitfield_default }, - { "PF_CFG_STICKY_EN_", 2, 2, &umr_bitfield_default }, - { "PF_PRV_EN_", 3, 3, &umr_bitfield_default }, - { "PF_PRV_STICKY_EN_", 4, 4, &umr_bitfield_default }, - { "FLR_GRACE_MODE_", 17, 17, &umr_bitfield_default }, - { "FLR_GRACE_TIMEOUT_", 18, 20, &umr_bitfield_default }, - { "FLR_DMA_DUMMY_RSPSTS_", 23, 24, &umr_bitfield_default }, - { "FLR_HST_DUMMY_RSPSTS_", 25, 26, &umr_bitfield_default }, -}; -static struct umr_bitfield ixDEV0_PF2_FLR_RST_CTRL[] = { - { "PF_CFG_EN_", 0, 0, &umr_bitfield_default }, - { "PF_CFG_FLR_EXC_EN_", 1, 1, &umr_bitfield_default }, - { "PF_CFG_STICKY_EN_", 2, 2, &umr_bitfield_default }, - { "PF_PRV_EN_", 3, 3, &umr_bitfield_default }, - { "PF_PRV_STICKY_EN_", 4, 4, &umr_bitfield_default }, - { "FLR_GRACE_MODE_", 17, 17, &umr_bitfield_default }, - { "FLR_GRACE_TIMEOUT_", 18, 20, &umr_bitfield_default }, - { "FLR_DMA_DUMMY_RSPSTS_", 23, 24, &umr_bitfield_default }, - { "FLR_HST_DUMMY_RSPSTS_", 25, 26, &umr_bitfield_default }, -}; -static struct umr_bitfield ixDEV0_PF3_FLR_RST_CTRL[] = { - { "PF_CFG_EN_", 0, 0, &umr_bitfield_default }, - { "PF_CFG_FLR_EXC_EN_", 1, 1, &umr_bitfield_default }, - { "PF_CFG_STICKY_EN_", 2, 2, &umr_bitfield_default }, - { "PF_PRV_EN_", 3, 3, &umr_bitfield_default }, - { "PF_PRV_STICKY_EN_", 4, 4, &umr_bitfield_default }, - { "FLR_GRACE_MODE_", 17, 17, &umr_bitfield_default }, - { "FLR_GRACE_TIMEOUT_", 18, 20, &umr_bitfield_default }, - { "FLR_DMA_DUMMY_RSPSTS_", 23, 24, &umr_bitfield_default }, - { "FLR_HST_DUMMY_RSPSTS_", 25, 26, &umr_bitfield_default }, -}; -static struct umr_bitfield ixDEV0_PF4_FLR_RST_CTRL[] = { - { "PF_CFG_EN_", 0, 0, &umr_bitfield_default }, - { "PF_CFG_FLR_EXC_EN_", 1, 1, &umr_bitfield_default }, - { "PF_CFG_STICKY_EN_", 2, 2, &umr_bitfield_default }, - { "PF_PRV_EN_", 3, 3, &umr_bitfield_default }, - { "PF_PRV_STICKY_EN_", 4, 4, &umr_bitfield_default }, - { "FLR_GRACE_MODE_", 17, 17, &umr_bitfield_default }, - { "FLR_GRACE_TIMEOUT_", 18, 20, &umr_bitfield_default }, - { "FLR_DMA_DUMMY_RSPSTS_", 23, 24, &umr_bitfield_default }, - { "FLR_HST_DUMMY_RSPSTS_", 25, 26, &umr_bitfield_default }, -}; -static struct umr_bitfield ixDEV0_PF5_FLR_RST_CTRL[] = { - { "PF_CFG_EN_", 0, 0, &umr_bitfield_default }, - { "PF_CFG_FLR_EXC_EN_", 1, 1, &umr_bitfield_default }, - { "PF_CFG_STICKY_EN_", 2, 2, &umr_bitfield_default }, - { "PF_PRV_EN_", 3, 3, &umr_bitfield_default }, - { "PF_PRV_STICKY_EN_", 4, 4, &umr_bitfield_default }, - { "FLR_GRACE_MODE_", 17, 17, &umr_bitfield_default }, - { "FLR_GRACE_TIMEOUT_", 18, 20, &umr_bitfield_default }, - { "FLR_DMA_DUMMY_RSPSTS_", 23, 24, &umr_bitfield_default }, - { "FLR_HST_DUMMY_RSPSTS_", 25, 26, &umr_bitfield_default }, -}; -static struct umr_bitfield ixDEV0_PF6_FLR_RST_CTRL[] = { - { "PF_CFG_EN_", 0, 0, &umr_bitfield_default }, - { "PF_CFG_FLR_EXC_EN_", 1, 1, &umr_bitfield_default }, - { "PF_CFG_STICKY_EN_", 2, 2, &umr_bitfield_default }, - { "PF_PRV_EN_", 3, 3, &umr_bitfield_default }, - { "PF_PRV_STICKY_EN_", 4, 4, &umr_bitfield_default }, - { "FLR_GRACE_MODE_", 17, 17, &umr_bitfield_default }, - { "FLR_GRACE_TIMEOUT_", 18, 20, &umr_bitfield_default }, - { "FLR_DMA_DUMMY_RSPSTS_", 23, 24, &umr_bitfield_default }, - { "FLR_HST_DUMMY_RSPSTS_", 25, 26, &umr_bitfield_default }, -}; -static struct umr_bitfield ixDEV0_PF7_FLR_RST_CTRL[] = { - { "PF_CFG_EN_", 0, 0, &umr_bitfield_default }, - { "PF_CFG_FLR_EXC_EN_", 1, 1, &umr_bitfield_default }, - { "PF_CFG_STICKY_EN_", 2, 2, &umr_bitfield_default }, - { "PF_PRV_EN_", 3, 3, &umr_bitfield_default }, - { "PF_PRV_STICKY_EN_", 4, 4, &umr_bitfield_default }, - { "FLR_GRACE_MODE_", 17, 17, &umr_bitfield_default }, - { "FLR_GRACE_TIMEOUT_", 18, 20, &umr_bitfield_default }, - { "FLR_DMA_DUMMY_RSPSTS_", 23, 24, &umr_bitfield_default }, - { "FLR_HST_DUMMY_RSPSTS_", 25, 26, &umr_bitfield_default }, -}; -static struct umr_bitfield ixBIF_INST_RESET_INTR_STS[] = { - { "EP0_LINK_RESET_INTR_STS_", 0, 0, &umr_bitfield_default }, - { "EP0_LINK_RESET_CFG_ONLY_INTR_STS_", 1, 1, &umr_bitfield_default }, - { "DRV_RESET_M0_INTR_STS_", 2, 2, &umr_bitfield_default }, - { "DRV_RESET_M1_INTR_STS_", 3, 3, &umr_bitfield_default }, - { "DRV_RESET_M2_INTR_STS_", 4, 4, &umr_bitfield_default }, -}; -static struct umr_bitfield ixBIF_PF_FLR_INTR_STS[] = { - { "DEV0_PF0_FLR_INTR_STS_", 0, 0, &umr_bitfield_default }, - { "DEV0_PF1_FLR_INTR_STS_", 1, 1, &umr_bitfield_default }, - { "DEV0_PF2_FLR_INTR_STS_", 2, 2, &umr_bitfield_default }, - { "DEV0_PF3_FLR_INTR_STS_", 3, 3, &umr_bitfield_default }, - { "DEV0_PF4_FLR_INTR_STS_", 4, 4, &umr_bitfield_default }, - { "DEV0_PF5_FLR_INTR_STS_", 5, 5, &umr_bitfield_default }, - { "DEV0_PF6_FLR_INTR_STS_", 6, 6, &umr_bitfield_default }, - { "DEV0_PF7_FLR_INTR_STS_", 7, 7, &umr_bitfield_default }, -}; -static struct umr_bitfield ixBIF_D3HOTD0_INTR_STS[] = { - { "DEV0_PF0_D3HOTD0_INTR_STS_", 0, 0, &umr_bitfield_default }, - { "DEV0_PF1_D3HOTD0_INTR_STS_", 1, 1, &umr_bitfield_default }, - { "DEV0_PF2_D3HOTD0_INTR_STS_", 2, 2, &umr_bitfield_default }, - { "DEV0_PF3_D3HOTD0_INTR_STS_", 3, 3, &umr_bitfield_default }, - { "DEV0_PF4_D3HOTD0_INTR_STS_", 4, 4, &umr_bitfield_default }, - { "DEV0_PF5_D3HOTD0_INTR_STS_", 5, 5, &umr_bitfield_default }, - { "DEV0_PF6_D3HOTD0_INTR_STS_", 6, 6, &umr_bitfield_default }, - { "DEV0_PF7_D3HOTD0_INTR_STS_", 7, 7, &umr_bitfield_default }, -}; -static struct umr_bitfield ixBIF_POWER_INTR_STS[] = { - { "DEV0_PME_TURN_OFF_INTR_STS_", 0, 0, &umr_bitfield_default }, - { "PORT0_DSTATE_INTR_STS_", 16, 16, &umr_bitfield_default }, -}; -static struct umr_bitfield ixBIF_PF_DSTATE_INTR_STS[] = { - { "DEV0_PF0_DSTATE_INTR_STS_", 0, 0, &umr_bitfield_default }, - { "DEV0_PF1_DSTATE_INTR_STS_", 1, 1, &umr_bitfield_default }, - { "DEV0_PF2_DSTATE_INTR_STS_", 2, 2, &umr_bitfield_default }, - { "DEV0_PF3_DSTATE_INTR_STS_", 3, 3, &umr_bitfield_default }, - { "DEV0_PF4_DSTATE_INTR_STS_", 4, 4, &umr_bitfield_default }, - { "DEV0_PF5_DSTATE_INTR_STS_", 5, 5, &umr_bitfield_default }, - { "DEV0_PF6_DSTATE_INTR_STS_", 6, 6, &umr_bitfield_default }, - { "DEV0_PF7_DSTATE_INTR_STS_", 7, 7, &umr_bitfield_default }, -}; -static struct umr_bitfield ixBIF_PF0_VF_FLR_INTR_STS[] = { - { "PF0_VF0_FLR_INTR_STS_", 0, 0, &umr_bitfield_default }, - { "PF0_VF1_FLR_INTR_STS_", 1, 1, &umr_bitfield_default }, - { "PF0_VF2_FLR_INTR_STS_", 2, 2, &umr_bitfield_default }, - { "PF0_VF3_FLR_INTR_STS_", 3, 3, &umr_bitfield_default }, - { "PF0_VF4_FLR_INTR_STS_", 4, 4, &umr_bitfield_default }, - { "PF0_VF5_FLR_INTR_STS_", 5, 5, &umr_bitfield_default }, - { "PF0_VF6_FLR_INTR_STS_", 6, 6, &umr_bitfield_default }, - { "PF0_VF7_FLR_INTR_STS_", 7, 7, &umr_bitfield_default }, - { "PF0_VF8_FLR_INTR_STS_", 8, 8, &umr_bitfield_default }, - { "PF0_VF9_FLR_INTR_STS_", 9, 9, &umr_bitfield_default }, - { "PF0_VF10_FLR_INTR_STS_", 10, 10, &umr_bitfield_default }, - { "PF0_VF11_FLR_INTR_STS_", 11, 11, &umr_bitfield_default }, - { "PF0_VF12_FLR_INTR_STS_", 12, 12, &umr_bitfield_default }, - { "PF0_VF13_FLR_INTR_STS_", 13, 13, &umr_bitfield_default }, - { "PF0_VF14_FLR_INTR_STS_", 14, 14, &umr_bitfield_default }, - { "PF0_VF15_FLR_INTR_STS_", 15, 15, &umr_bitfield_default }, - { "PF0_SOFTPF_FLR_INTR_STS_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixBIF_INST_RESET_INTR_MASK[] = { - { "EP0_LINK_RESET_INTR_MASK_", 0, 0, &umr_bitfield_default }, - { "EP0_LINK_RESET_CFG_ONLY_INTR_MASK_", 1, 1, &umr_bitfield_default }, - { "DRV_RESET_M0_INTR_MASK_", 2, 2, &umr_bitfield_default }, - { "DRV_RESET_M1_INTR_MASK_", 3, 3, &umr_bitfield_default }, - { "DRV_RESET_M2_INTR_MASK_", 4, 4, &umr_bitfield_default }, -}; -static struct umr_bitfield ixBIF_PF_FLR_INTR_MASK[] = { - { "DEV0_PF0_FLR_INTR_MASK_", 0, 0, &umr_bitfield_default }, - { "DEV0_PF1_FLR_INTR_MASK_", 1, 1, &umr_bitfield_default }, - { "DEV0_PF2_FLR_INTR_MASK_", 2, 2, &umr_bitfield_default }, - { "DEV0_PF3_FLR_INTR_MASK_", 3, 3, &umr_bitfield_default }, - { "DEV0_PF4_FLR_INTR_MASK_", 4, 4, &umr_bitfield_default }, - { "DEV0_PF5_FLR_INTR_MASK_", 5, 5, &umr_bitfield_default }, - { "DEV0_PF6_FLR_INTR_MASK_", 6, 6, &umr_bitfield_default }, - { "DEV0_PF7_FLR_INTR_MASK_", 7, 7, &umr_bitfield_default }, -}; -static struct umr_bitfield ixBIF_D3HOTD0_INTR_MASK[] = { - { "DEV0_PF0_D3HOTD0_INTR_MASK_", 0, 0, &umr_bitfield_default }, - { "DEV0_PF1_D3HOTD0_INTR_MASK_", 1, 1, &umr_bitfield_default }, - { "DEV0_PF2_D3HOTD0_INTR_MASK_", 2, 2, &umr_bitfield_default }, - { "DEV0_PF3_D3HOTD0_INTR_MASK_", 3, 3, &umr_bitfield_default }, - { "DEV0_PF4_D3HOTD0_INTR_MASK_", 4, 4, &umr_bitfield_default }, - { "DEV0_PF5_D3HOTD0_INTR_MASK_", 5, 5, &umr_bitfield_default }, - { "DEV0_PF6_D3HOTD0_INTR_MASK_", 6, 6, &umr_bitfield_default }, - { "DEV0_PF7_D3HOTD0_INTR_MASK_", 7, 7, &umr_bitfield_default }, -}; -static struct umr_bitfield ixBIF_POWER_INTR_MASK[] = { - { "DEV0_PME_TURN_OFF_INTR_MASK_", 0, 0, &umr_bitfield_default }, - { "PORT0_DSTATE_INTR_MASK_", 16, 16, &umr_bitfield_default }, -}; -static struct umr_bitfield ixBIF_PF_DSTATE_INTR_MASK[] = { - { "DEV0_PF0_DSTATE_INTR_MASK_", 0, 0, &umr_bitfield_default }, - { "DEV0_PF1_DSTATE_INTR_MASK_", 1, 1, &umr_bitfield_default }, - { "DEV0_PF2_DSTATE_INTR_MASK_", 2, 2, &umr_bitfield_default }, - { "DEV0_PF3_DSTATE_INTR_MASK_", 3, 3, &umr_bitfield_default }, - { "DEV0_PF4_DSTATE_INTR_MASK_", 4, 4, &umr_bitfield_default }, - { "DEV0_PF5_DSTATE_INTR_MASK_", 5, 5, &umr_bitfield_default }, - { "DEV0_PF6_DSTATE_INTR_MASK_", 6, 6, &umr_bitfield_default }, - { "DEV0_PF7_DSTATE_INTR_MASK_", 7, 7, &umr_bitfield_default }, -}; -static struct umr_bitfield ixBIF_PF0_VF_FLR_INTR_MASK[] = { - { "PF0_VF0_FLR_INTR_MASK_", 0, 0, &umr_bitfield_default }, - { "PF0_VF1_FLR_INTR_MASK_", 1, 1, &umr_bitfield_default }, - { "PF0_VF2_FLR_INTR_MASK_", 2, 2, &umr_bitfield_default }, - { "PF0_VF3_FLR_INTR_MASK_", 3, 3, &umr_bitfield_default }, - { "PF0_VF4_FLR_INTR_MASK_", 4, 4, &umr_bitfield_default }, - { "PF0_VF5_FLR_INTR_MASK_", 5, 5, &umr_bitfield_default }, - { "PF0_VF6_FLR_INTR_MASK_", 6, 6, &umr_bitfield_default }, - { "PF0_VF7_FLR_INTR_MASK_", 7, 7, &umr_bitfield_default }, - { "PF0_VF8_FLR_INTR_MASK_", 8, 8, &umr_bitfield_default }, - { "PF0_VF9_FLR_INTR_MASK_", 9, 9, &umr_bitfield_default }, - { "PF0_VF10_FLR_INTR_MASK_", 10, 10, &umr_bitfield_default }, - { "PF0_VF11_FLR_INTR_MASK_", 11, 11, &umr_bitfield_default }, - { "PF0_VF12_FLR_INTR_MASK_", 12, 12, &umr_bitfield_default }, - { "PF0_VF13_FLR_INTR_MASK_", 13, 13, &umr_bitfield_default }, - { "PF0_VF14_FLR_INTR_MASK_", 14, 14, &umr_bitfield_default }, - { "PF0_VF15_FLR_INTR_MASK_", 15, 15, &umr_bitfield_default }, - { "PF0_SOFTPF_FLR_INTR_MASK_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixBIF_PF_FLR_RST[] = { - { "DEV0_PF0_FLR_RST_", 0, 0, &umr_bitfield_default }, - { "DEV0_PF1_FLR_RST_", 1, 1, &umr_bitfield_default }, - { "DEV0_PF2_FLR_RST_", 2, 2, &umr_bitfield_default }, - { "DEV0_PF3_FLR_RST_", 3, 3, &umr_bitfield_default }, - { "DEV0_PF4_FLR_RST_", 4, 4, &umr_bitfield_default }, - { "DEV0_PF5_FLR_RST_", 5, 5, &umr_bitfield_default }, - { "DEV0_PF6_FLR_RST_", 6, 6, &umr_bitfield_default }, - { "DEV0_PF7_FLR_RST_", 7, 7, &umr_bitfield_default }, -}; -static struct umr_bitfield ixBIF_PF0_VF_FLR_RST[] = { - { "PF0_VF0_FLR_RST_", 0, 0, &umr_bitfield_default }, - { "PF0_VF1_FLR_RST_", 1, 1, &umr_bitfield_default }, - { "PF0_VF2_FLR_RST_", 2, 2, &umr_bitfield_default }, - { "PF0_VF3_FLR_RST_", 3, 3, &umr_bitfield_default }, - { "PF0_VF4_FLR_RST_", 4, 4, &umr_bitfield_default }, - { "PF0_VF5_FLR_RST_", 5, 5, &umr_bitfield_default }, - { "PF0_VF6_FLR_RST_", 6, 6, &umr_bitfield_default }, - { "PF0_VF7_FLR_RST_", 7, 7, &umr_bitfield_default }, - { "PF0_VF8_FLR_RST_", 8, 8, &umr_bitfield_default }, - { "PF0_VF9_FLR_RST_", 9, 9, &umr_bitfield_default }, - { "PF0_VF10_FLR_RST_", 10, 10, &umr_bitfield_default }, - { "PF0_VF11_FLR_RST_", 11, 11, &umr_bitfield_default }, - { "PF0_VF12_FLR_RST_", 12, 12, &umr_bitfield_default }, - { "PF0_VF13_FLR_RST_", 13, 13, &umr_bitfield_default }, - { "PF0_VF14_FLR_RST_", 14, 14, &umr_bitfield_default }, - { "PF0_VF15_FLR_RST_", 15, 15, &umr_bitfield_default }, - { "PF0_SOFTPF_FLR_RST_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixBIF_DEV0_PF0_DSTATE_VALUE[] = { - { "DEV0_PF0_DSTATE_TGT_VALUE_", 0, 1, &umr_bitfield_default }, - { "DEV0_PF0_DSTATE_NEED_D3TOD0_RESET_", 2, 2, &umr_bitfield_default }, - { "DEV0_PF0_DSTATE_ACK_VALUE_", 16, 17, &umr_bitfield_default }, -}; -static struct umr_bitfield ixBIF_DEV0_PF1_DSTATE_VALUE[] = { - { "DEV0_PF1_DSTATE_TGT_VALUE_", 0, 1, &umr_bitfield_default }, - { "DEV0_PF1_DSTATE_NEED_D3TOD0_RESET_", 2, 2, &umr_bitfield_default }, - { "DEV0_PF1_DSTATE_ACK_VALUE_", 16, 17, &umr_bitfield_default }, -}; -static struct umr_bitfield ixBIF_DEV0_PF2_DSTATE_VALUE[] = { - { "DEV0_PF2_DSTATE_TGT_VALUE_", 0, 1, &umr_bitfield_default }, - { "DEV0_PF2_DSTATE_NEED_D3TOD0_RESET_", 2, 2, &umr_bitfield_default }, - { "DEV0_PF2_DSTATE_ACK_VALUE_", 16, 17, &umr_bitfield_default }, -}; -static struct umr_bitfield ixBIF_DEV0_PF3_DSTATE_VALUE[] = { - { "DEV0_PF3_DSTATE_TGT_VALUE_", 0, 1, &umr_bitfield_default }, - { "DEV0_PF3_DSTATE_NEED_D3TOD0_RESET_", 2, 2, &umr_bitfield_default }, - { "DEV0_PF3_DSTATE_ACK_VALUE_", 16, 17, &umr_bitfield_default }, -}; -static struct umr_bitfield ixBIF_DEV0_PF4_DSTATE_VALUE[] = { - { "DEV0_PF4_DSTATE_TGT_VALUE_", 0, 1, &umr_bitfield_default }, - { "DEV0_PF4_DSTATE_NEED_D3TOD0_RESET_", 2, 2, &umr_bitfield_default }, - { "DEV0_PF4_DSTATE_ACK_VALUE_", 16, 17, &umr_bitfield_default }, -}; -static struct umr_bitfield ixBIF_DEV0_PF5_DSTATE_VALUE[] = { - { "DEV0_PF5_DSTATE_TGT_VALUE_", 0, 1, &umr_bitfield_default }, - { "DEV0_PF5_DSTATE_NEED_D3TOD0_RESET_", 2, 2, &umr_bitfield_default }, - { "DEV0_PF5_DSTATE_ACK_VALUE_", 16, 17, &umr_bitfield_default }, -}; -static struct umr_bitfield ixBIF_DEV0_PF6_DSTATE_VALUE[] = { - { "DEV0_PF6_DSTATE_TGT_VALUE_", 0, 1, &umr_bitfield_default }, - { "DEV0_PF6_DSTATE_NEED_D3TOD0_RESET_", 2, 2, &umr_bitfield_default }, - { "DEV0_PF6_DSTATE_ACK_VALUE_", 16, 17, &umr_bitfield_default }, -}; -static struct umr_bitfield ixBIF_DEV0_PF7_DSTATE_VALUE[] = { - { "DEV0_PF7_DSTATE_TGT_VALUE_", 0, 1, &umr_bitfield_default }, - { "DEV0_PF7_DSTATE_NEED_D3TOD0_RESET_", 2, 2, &umr_bitfield_default }, - { "DEV0_PF7_DSTATE_ACK_VALUE_", 16, 17, &umr_bitfield_default }, -}; -static struct umr_bitfield ixDEV0_PF0_D3HOTD0_RST_CTRL[] = { - { "PF_CFG_EN_", 0, 0, &umr_bitfield_default }, - { "PF_CFG_FLR_EXC_EN_", 1, 1, &umr_bitfield_default }, - { "PF_CFG_STICKY_EN_", 2, 2, &umr_bitfield_default }, - { "PF_PRV_EN_", 3, 3, &umr_bitfield_default }, - { "PF_PRV_STICKY_EN_", 4, 4, &umr_bitfield_default }, -}; -static struct umr_bitfield ixDEV0_PF1_D3HOTD0_RST_CTRL[] = { - { "PF_CFG_EN_", 0, 0, &umr_bitfield_default }, - { "PF_CFG_FLR_EXC_EN_", 1, 1, &umr_bitfield_default }, - { "PF_CFG_STICKY_EN_", 2, 2, &umr_bitfield_default }, - { "PF_PRV_EN_", 3, 3, &umr_bitfield_default }, - { "PF_PRV_STICKY_EN_", 4, 4, &umr_bitfield_default }, -}; -static struct umr_bitfield ixDEV0_PF2_D3HOTD0_RST_CTRL[] = { - { "PF_CFG_EN_", 0, 0, &umr_bitfield_default }, - { "PF_CFG_FLR_EXC_EN_", 1, 1, &umr_bitfield_default }, - { "PF_CFG_STICKY_EN_", 2, 2, &umr_bitfield_default }, - { "PF_PRV_EN_", 3, 3, &umr_bitfield_default }, - { "PF_PRV_STICKY_EN_", 4, 4, &umr_bitfield_default }, -}; -static struct umr_bitfield ixDEV0_PF3_D3HOTD0_RST_CTRL[] = { - { "PF_CFG_EN_", 0, 0, &umr_bitfield_default }, - { "PF_CFG_FLR_EXC_EN_", 1, 1, &umr_bitfield_default }, - { "PF_CFG_STICKY_EN_", 2, 2, &umr_bitfield_default }, - { "PF_PRV_EN_", 3, 3, &umr_bitfield_default }, - { "PF_PRV_STICKY_EN_", 4, 4, &umr_bitfield_default }, -}; -static struct umr_bitfield ixDEV0_PF4_D3HOTD0_RST_CTRL[] = { - { "PF_CFG_EN_", 0, 0, &umr_bitfield_default }, - { "PF_CFG_FLR_EXC_EN_", 1, 1, &umr_bitfield_default }, - { "PF_CFG_STICKY_EN_", 2, 2, &umr_bitfield_default }, - { "PF_PRV_EN_", 3, 3, &umr_bitfield_default }, - { "PF_PRV_STICKY_EN_", 4, 4, &umr_bitfield_default }, -}; -static struct umr_bitfield ixDEV0_PF5_D3HOTD0_RST_CTRL[] = { - { "PF_CFG_EN_", 0, 0, &umr_bitfield_default }, - { "PF_CFG_FLR_EXC_EN_", 1, 1, &umr_bitfield_default }, - { "PF_CFG_STICKY_EN_", 2, 2, &umr_bitfield_default }, - { "PF_PRV_EN_", 3, 3, &umr_bitfield_default }, - { "PF_PRV_STICKY_EN_", 4, 4, &umr_bitfield_default }, -}; -static struct umr_bitfield ixDEV0_PF6_D3HOTD0_RST_CTRL[] = { - { "PF_CFG_EN_", 0, 0, &umr_bitfield_default }, - { "PF_CFG_FLR_EXC_EN_", 1, 1, &umr_bitfield_default }, - { "PF_CFG_STICKY_EN_", 2, 2, &umr_bitfield_default }, - { "PF_PRV_EN_", 3, 3, &umr_bitfield_default }, - { "PF_PRV_STICKY_EN_", 4, 4, &umr_bitfield_default }, -}; -static struct umr_bitfield ixDEV0_PF7_D3HOTD0_RST_CTRL[] = { - { "PF_CFG_EN_", 0, 0, &umr_bitfield_default }, - { "PF_CFG_FLR_EXC_EN_", 1, 1, &umr_bitfield_default }, - { "PF_CFG_STICKY_EN_", 2, 2, &umr_bitfield_default }, - { "PF_PRV_EN_", 3, 3, &umr_bitfield_default }, - { "PF_PRV_STICKY_EN_", 4, 4, &umr_bitfield_default }, -}; -static struct umr_bitfield ixBIF_PORT0_DSTATE_VALUE[] = { - { "PORT0_DSTATE_TGT_VALUE_", 0, 1, &umr_bitfield_default }, - { "PORT0_DSTATE_ACK_VALUE_", 16, 17, &umr_bitfield_default }, -}; -static struct umr_bitfield ixMISC_SCRATCH[] = { - { "MISC_SCRATCH0_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixINTR_LINE_POLARITY[] = { - { "INTR_LINE_POLARITY_DEV0_", 0, 7, &umr_bitfield_default }, -}; -static struct umr_bitfield ixINTR_LINE_ENABLE[] = { - { "INTR_LINE_ENABLE_DEV0_", 0, 7, &umr_bitfield_default }, -}; -static struct umr_bitfield ixOUTSTANDING_VC_ALLOC[] = { - { "DMA_OUTSTANDING_VC0_ALLOC_", 0, 1, &umr_bitfield_default }, - { "DMA_OUTSTANDING_VC1_ALLOC_", 2, 3, &umr_bitfield_default }, - { "DMA_OUTSTANDING_VC2_ALLOC_", 4, 5, &umr_bitfield_default }, - { "DMA_OUTSTANDING_VC3_ALLOC_", 6, 7, &umr_bitfield_default }, - { "DMA_OUTSTANDING_VC4_ALLOC_", 8, 9, &umr_bitfield_default }, - { "DMA_OUTSTANDING_VC5_ALLOC_", 10, 11, &umr_bitfield_default }, - { "DMA_OUTSTANDING_VC6_ALLOC_", 12, 13, &umr_bitfield_default }, - { "DMA_OUTSTANDING_VC7_ALLOC_", 14, 15, &umr_bitfield_default }, - { "DMA_OUTSTANDING_THRD_", 16, 19, &umr_bitfield_default }, - { "HST_OUTSTANDING_VC0_ALLOC_", 24, 25, &umr_bitfield_default }, - { "HST_OUTSTANDING_VC1_ALLOC_", 26, 27, &umr_bitfield_default }, - { "HST_OUTSTANDING_THRD_", 28, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixBIFC_MISC_CTRL0[] = { - { "VWIRE_TARG_UNITID_CHECK_EN_", 0, 0, &umr_bitfield_default }, - { "VWIRE_SRC_UNITID_CHECK_EN_", 1, 2, &umr_bitfield_default }, - { "DMA_CHAIN_BREAK_IN_RCMODE_", 8, 8, &umr_bitfield_default }, - { "HST_ARB_CHAIN_LOCK_", 9, 9, &umr_bitfield_default }, - { "GSI_SST_ARB_CHAIN_LOCK_", 10, 10, &umr_bitfield_default }, - { "DMA_ATOMIC_LENGTH_CHK_DIS_", 16, 16, &umr_bitfield_default }, - { "DMA_ATOMIC_FAILED_STS_SEL_", 17, 17, &umr_bitfield_default }, - { "PCIE_CAPABILITY_PROT_DIS_", 24, 24, &umr_bitfield_default }, - { "VC7_DMA_IOCFG_DIS_", 25, 25, &umr_bitfield_default }, - { "DMA_2ND_REQ_DIS_", 26, 26, &umr_bitfield_default }, - { "PORT_DSTATE_BYPASS_MODE_", 27, 27, &umr_bitfield_default }, - { "PME_TURNOFF_MODE_", 28, 28, &umr_bitfield_default }, - { "PCIESWUS_SELECTION_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixBIFC_MISC_CTRL1[] = { - { "THT_HST_CPLD_POISON_REPORT_", 0, 0, &umr_bitfield_default }, - { "DMA_REQ_POISON_REPORT_", 1, 1, &umr_bitfield_default }, - { "DMA_REQ_ACSVIO_REPORT_", 2, 2, &umr_bitfield_default }, - { "DMA_RSP_POISON_CPLD_REPORT_", 3, 3, &umr_bitfield_default }, - { "GSI_SMN_WORST_ERR_STSTUS_", 4, 4, &umr_bitfield_default }, - { "GSI_SDP_RDRSP_DATA_FORCE1_FOR_ERROR_", 5, 5, &umr_bitfield_default }, - { "GSI_RDWR_BALANCE_DIS_", 6, 6, &umr_bitfield_default }, - { "GMI_MSG_BLOCKLVL_SEL_", 7, 7, &umr_bitfield_default }, - { "HST_UNSUPPORT_SDPCMD_STS_", 8, 9, &umr_bitfield_default }, - { "HST_UNSUPPORT_SDPCMD_DATASTS_", 10, 11, &umr_bitfield_default }, - { "DROP_OTHER_HT_ADDR_REQ_", 12, 12, &umr_bitfield_default }, - { "DMAWRREQ_HSTRDRSP_ORDER_FORCE_", 13, 13, &umr_bitfield_default }, - { "DMAWRREQ_HSTRDRSP_ORDER_FORCE_VALUE_", 14, 14, &umr_bitfield_default }, - { "UPS_SDP_RDY_TIE1_", 15, 15, &umr_bitfield_default }, - { "GMI_RCC_DN_BME_DROP_DIS_", 16, 16, &umr_bitfield_default }, - { "GMI_RCC_EP_BME_DROP_DIS_", 17, 17, &umr_bitfield_default }, - { "GMI_BIH_DN_BME_DROP_DIS_", 18, 18, &umr_bitfield_default }, - { "GMI_BIH_EP_BME_DROP_DIS_", 19, 19, &umr_bitfield_default }, -}; -static struct umr_bitfield ixBIFC_BME_ERR_LOG[] = { - { "DMA_ON_BME_LOW_DEV0_F0_", 0, 0, &umr_bitfield_default }, - { "DMA_ON_BME_LOW_DEV0_F1_", 1, 1, &umr_bitfield_default }, - { "DMA_ON_BME_LOW_DEV0_F2_", 2, 2, &umr_bitfield_default }, - { "DMA_ON_BME_LOW_DEV0_F3_", 3, 3, &umr_bitfield_default }, - { "DMA_ON_BME_LOW_DEV0_F4_", 4, 4, &umr_bitfield_default }, - { "DMA_ON_BME_LOW_DEV0_F5_", 5, 5, &umr_bitfield_default }, - { "DMA_ON_BME_LOW_DEV0_F6_", 6, 6, &umr_bitfield_default }, - { "DMA_ON_BME_LOW_DEV0_F7_", 7, 7, &umr_bitfield_default }, - { "CLEAR_DMA_ON_BME_LOW_DEV0_F0_", 16, 16, &umr_bitfield_default }, - { "CLEAR_DMA_ON_BME_LOW_DEV0_F1_", 17, 17, &umr_bitfield_default }, - { "CLEAR_DMA_ON_BME_LOW_DEV0_F2_", 18, 18, &umr_bitfield_default }, - { "CLEAR_DMA_ON_BME_LOW_DEV0_F3_", 19, 19, &umr_bitfield_default }, - { "CLEAR_DMA_ON_BME_LOW_DEV0_F4_", 20, 20, &umr_bitfield_default }, - { "CLEAR_DMA_ON_BME_LOW_DEV0_F5_", 21, 21, &umr_bitfield_default }, - { "CLEAR_DMA_ON_BME_LOW_DEV0_F6_", 22, 22, &umr_bitfield_default }, - { "CLEAR_DMA_ON_BME_LOW_DEV0_F7_", 23, 23, &umr_bitfield_default }, -}; -static struct umr_bitfield ixBIFC_RCCBIH_BME_ERR_LOG[] = { - { "RCCBIH_ON_BME_LOW_DEV0_F0_", 0, 0, &umr_bitfield_default }, - { "RCCBIH_ON_BME_LOW_DEV0_F1_", 1, 1, &umr_bitfield_default }, - { "RCCBIH_ON_BME_LOW_DEV0_F2_", 2, 2, &umr_bitfield_default }, - { "RCCBIH_ON_BME_LOW_DEV0_F3_", 3, 3, &umr_bitfield_default }, - { "RCCBIH_ON_BME_LOW_DEV0_F4_", 4, 4, &umr_bitfield_default }, - { "RCCBIH_ON_BME_LOW_DEV0_F5_", 5, 5, &umr_bitfield_default }, - { "RCCBIH_ON_BME_LOW_DEV0_F6_", 6, 6, &umr_bitfield_default }, - { "RCCBIH_ON_BME_LOW_DEV0_F7_", 7, 7, &umr_bitfield_default }, - { "CLEAR_RCCBIH_ON_BME_LOW_DEV0_F0_", 16, 16, &umr_bitfield_default }, - { "CLEAR_RCCBIH_ON_BME_LOW_DEV0_F1_", 17, 17, &umr_bitfield_default }, - { "CLEAR_RCCBIH_ON_BME_LOW_DEV0_F2_", 18, 18, &umr_bitfield_default }, - { "CLEAR_RCCBIH_ON_BME_LOW_DEV0_F3_", 19, 19, &umr_bitfield_default }, - { "CLEAR_RCCBIH_ON_BME_LOW_DEV0_F4_", 20, 20, &umr_bitfield_default }, - { "CLEAR_RCCBIH_ON_BME_LOW_DEV0_F5_", 21, 21, &umr_bitfield_default }, - { "CLEAR_RCCBIH_ON_BME_LOW_DEV0_F6_", 22, 22, &umr_bitfield_default }, - { "CLEAR_RCCBIH_ON_BME_LOW_DEV0_F7_", 23, 23, &umr_bitfield_default }, -}; -static struct umr_bitfield ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1[] = { - { "TX_IDO_OVERIDE_P_DEV0_F0_", 0, 1, &umr_bitfield_default }, - { "TX_IDO_OVERIDE_NP_DEV0_F0_", 2, 3, &umr_bitfield_default }, - { "TX_RO_OVERIDE_P_DEV0_F0_", 6, 7, &umr_bitfield_default }, - { "TX_RO_OVERIDE_NP_DEV0_F0_", 8, 9, &umr_bitfield_default }, - { "TX_SNR_OVERIDE_P_DEV0_F0_", 10, 11, &umr_bitfield_default }, - { "TX_SNR_OVERIDE_NP_DEV0_F0_", 12, 13, &umr_bitfield_default }, - { "TX_IDO_OVERIDE_P_DEV0_F1_", 16, 17, &umr_bitfield_default }, - { "TX_IDO_OVERIDE_NP_DEV0_F1_", 18, 19, &umr_bitfield_default }, - { "TX_RO_OVERIDE_P_DEV0_F1_", 22, 23, &umr_bitfield_default }, - { "TX_RO_OVERIDE_NP_DEV0_F1_", 24, 25, &umr_bitfield_default }, - { "TX_SNR_OVERIDE_P_DEV0_F1_", 26, 27, &umr_bitfield_default }, - { "TX_SNR_OVERIDE_NP_DEV0_F1_", 28, 29, &umr_bitfield_default }, -}; -static struct umr_bitfield ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3[] = { - { "TX_IDO_OVERIDE_P_DEV0_F2_", 0, 1, &umr_bitfield_default }, - { "TX_IDO_OVERIDE_NP_DEV0_F2_", 2, 3, &umr_bitfield_default }, - { "TX_RO_OVERIDE_P_DEV0_F2_", 6, 7, &umr_bitfield_default }, - { "TX_RO_OVERIDE_NP_DEV0_F2_", 8, 9, &umr_bitfield_default }, - { "TX_SNR_OVERIDE_P_DEV0_F2_", 10, 11, &umr_bitfield_default }, - { "TX_SNR_OVERIDE_NP_DEV0_F2_", 12, 13, &umr_bitfield_default }, - { "TX_IDO_OVERIDE_P_DEV0_F3_", 16, 17, &umr_bitfield_default }, - { "TX_IDO_OVERIDE_NP_DEV0_F3_", 18, 19, &umr_bitfield_default }, - { "TX_RO_OVERIDE_P_DEV0_F3_", 22, 23, &umr_bitfield_default }, - { "TX_RO_OVERIDE_NP_DEV0_F3_", 24, 25, &umr_bitfield_default }, - { "TX_SNR_OVERIDE_P_DEV0_F3_", 26, 27, &umr_bitfield_default }, - { "TX_SNR_OVERIDE_NP_DEV0_F3_", 28, 29, &umr_bitfield_default }, -}; -static struct umr_bitfield ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5[] = { - { "TX_IDO_OVERIDE_P_DEV0_F4_", 0, 1, &umr_bitfield_default }, - { "TX_IDO_OVERIDE_NP_DEV0_F4_", 2, 3, &umr_bitfield_default }, - { "TX_RO_OVERIDE_P_DEV0_F4_", 6, 7, &umr_bitfield_default }, - { "TX_RO_OVERIDE_NP_DEV0_F4_", 8, 9, &umr_bitfield_default }, - { "TX_SNR_OVERIDE_P_DEV0_F4_", 10, 11, &umr_bitfield_default }, - { "TX_SNR_OVERIDE_NP_DEV0_F4_", 12, 13, &umr_bitfield_default }, - { "TX_IDO_OVERIDE_P_DEV0_F5_", 16, 17, &umr_bitfield_default }, - { "TX_IDO_OVERIDE_NP_DEV0_F5_", 18, 19, &umr_bitfield_default }, - { "TX_RO_OVERIDE_P_DEV0_F5_", 22, 23, &umr_bitfield_default }, - { "TX_RO_OVERIDE_NP_DEV0_F5_", 24, 25, &umr_bitfield_default }, - { "TX_SNR_OVERIDE_P_DEV0_F5_", 26, 27, &umr_bitfield_default }, - { "TX_SNR_OVERIDE_NP_DEV0_F5_", 28, 29, &umr_bitfield_default }, -}; -static struct umr_bitfield ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7[] = { - { "TX_IDO_OVERIDE_P_DEV0_F6_", 0, 1, &umr_bitfield_default }, - { "TX_IDO_OVERIDE_NP_DEV0_F6_", 2, 3, &umr_bitfield_default }, - { "TX_RO_OVERIDE_P_DEV0_F6_", 6, 7, &umr_bitfield_default }, - { "TX_RO_OVERIDE_NP_DEV0_F6_", 8, 9, &umr_bitfield_default }, - { "TX_SNR_OVERIDE_P_DEV0_F6_", 10, 11, &umr_bitfield_default }, - { "TX_SNR_OVERIDE_NP_DEV0_F6_", 12, 13, &umr_bitfield_default }, - { "TX_IDO_OVERIDE_P_DEV0_F7_", 16, 17, &umr_bitfield_default }, - { "TX_IDO_OVERIDE_NP_DEV0_F7_", 18, 19, &umr_bitfield_default }, - { "TX_RO_OVERIDE_P_DEV0_F7_", 22, 23, &umr_bitfield_default }, - { "TX_RO_OVERIDE_NP_DEV0_F7_", 24, 25, &umr_bitfield_default }, - { "TX_SNR_OVERIDE_P_DEV0_F7_", 26, 27, &umr_bitfield_default }, - { "TX_SNR_OVERIDE_NP_DEV0_F7_", 28, 29, &umr_bitfield_default }, -}; -static struct umr_bitfield ixNBIF_VWIRE_CTRL[] = { - { "SMN_VWR_RESET_DELAY_CNT_", 4, 7, &umr_bitfield_default }, - { "SMN_VWR_POSTED_", 8, 8, &umr_bitfield_default }, - { "SDP_VWR_RESET_DELAY_CNT_", 20, 23, &umr_bitfield_default }, - { "SDP_VWR_BLOCKLVL_", 26, 27, &umr_bitfield_default }, -}; -static struct umr_bitfield ixNBIF_SMN_VWR_VCHG_DIS_CTRL[] = { - { "SMN_VWR_VCHG_SET0_DIS_", 0, 0, &umr_bitfield_default }, - { "SMN_VWR_VCHG_SET1_DIS_", 1, 1, &umr_bitfield_default }, - { "SMN_VWR_VCHG_SET2_DIS_", 2, 2, &umr_bitfield_default }, - { "SMN_VWR_VCHG_SET3_DIS_", 3, 3, &umr_bitfield_default }, - { "SMN_VWR_VCHG_SET4_DIS_", 4, 4, &umr_bitfield_default }, - { "SMN_VWR_VCHG_SET5_DIS_", 5, 5, &umr_bitfield_default }, - { "SMN_VWR_VCHG_SET6_DIS_", 6, 6, &umr_bitfield_default }, -}; -static struct umr_bitfield ixNBIF_SMN_VWR_VCHG_RST_CTRL0[] = { - { "SMN_VWR_VCHG_SET0_RST_DEF_REV_", 0, 0, &umr_bitfield_default }, - { "SMN_VWR_VCHG_SET1_RST_DEF_REV_", 1, 1, &umr_bitfield_default }, - { "SMN_VWR_VCHG_SET2_RST_DEF_REV_", 2, 2, &umr_bitfield_default }, - { "SMN_VWR_VCHG_SET3_RST_DEF_REV_", 3, 3, &umr_bitfield_default }, - { "SMN_VWR_VCHG_SET4_RST_DEF_REV_", 4, 4, &umr_bitfield_default }, - { "SMN_VWR_VCHG_SET5_RST_DEF_REV_", 5, 5, &umr_bitfield_default }, - { "SMN_VWR_VCHG_SET6_RST_DEF_REV_", 6, 6, &umr_bitfield_default }, -}; -static struct umr_bitfield ixNBIF_SMN_VWR_VCHG_TRIG[] = { - { "SMN_VWR_VCHG_SET0_TRIG_", 0, 0, &umr_bitfield_default }, - { "SMN_VWR_VCHG_SET1_TRIG_", 1, 1, &umr_bitfield_default }, - { "SMN_VWR_VCHG_SET2_TRIG_", 2, 2, &umr_bitfield_default }, - { "SMN_VWR_VCHG_SET3_TRIG_", 3, 3, &umr_bitfield_default }, - { "SMN_VWR_VCHG_SET4_TRIG_", 4, 4, &umr_bitfield_default }, - { "SMN_VWR_VCHG_SET5_TRIG_", 5, 5, &umr_bitfield_default }, - { "SMN_VWR_VCHG_SET6_TRIG_", 6, 6, &umr_bitfield_default }, -}; -static struct umr_bitfield ixNBIF_SMN_VWR_WTRIG_CNTL[] = { - { "SMN_VWR_WTRIG_SET0_DIS_", 0, 0, &umr_bitfield_default }, - { "SMN_VWR_WTRIG_SET1_DIS_", 1, 1, &umr_bitfield_default }, - { "SMN_VWR_WTRIG_SET2_DIS_", 2, 2, &umr_bitfield_default }, - { "SMN_VWR_WTRIG_SET3_DIS_", 3, 3, &umr_bitfield_default }, - { "SMN_VWR_WTRIG_SET4_DIS_", 4, 4, &umr_bitfield_default }, - { "SMN_VWR_WTRIG_SET5_DIS_", 5, 5, &umr_bitfield_default }, - { "SMN_VWR_WTRIG_SET6_DIS_", 6, 6, &umr_bitfield_default }, -}; -static struct umr_bitfield ixNBIF_SMN_VWR_VCHG_DIS_CTRL_1[] = { - { "SMN_VWR_VCHG_SET0_DIFFDET_DEF_REV_", 0, 0, &umr_bitfield_default }, - { "SMN_VWR_VCHG_SET1_DIFFDET_DEF_REV_", 1, 1, &umr_bitfield_default }, - { "SMN_VWR_VCHG_SET2_DIFFDET_DEF_REV_", 2, 2, &umr_bitfield_default }, - { "SMN_VWR_VCHG_SET3_DIFFDET_DEF_REV_", 3, 3, &umr_bitfield_default }, - { "SMN_VWR_VCHG_SET4_DIFFDET_DEF_REV_", 4, 4, &umr_bitfield_default }, - { "SMN_VWR_VCHG_SET5_DIFFDET_DEF_REV_", 5, 5, &umr_bitfield_default }, - { "SMN_VWR_VCHG_SET6_DIFFDET_DEF_REV_", 6, 6, &umr_bitfield_default }, -}; -static struct umr_bitfield ixNBIF_MGCG_CTRL[] = { - { "NBIF_MGCG_EN_", 0, 0, &umr_bitfield_default }, - { "NBIF_MGCG_MODE_", 1, 1, &umr_bitfield_default }, - { "NBIF_MGCG_HYSTERESIS_", 2, 9, &umr_bitfield_default }, -}; -static struct umr_bitfield ixNBIF_DS_CTRL_LCLK[] = { - { "NBIF_LCLK_DS_EN_", 0, 0, &umr_bitfield_default }, - { "NBIF_LCLK_DS_TIMER_", 16, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSMN_MST_CNTL0[] = { - { "SMN_ARB_MODE_", 0, 1, &umr_bitfield_default }, - { "SMN_ZERO_BE_WR_EN_UPS_", 8, 8, &umr_bitfield_default }, - { "SMN_ZERO_BE_RD_EN_UPS_", 9, 9, &umr_bitfield_default }, - { "SMN_POST_MASK_EN_UPS_", 10, 10, &umr_bitfield_default }, - { "MULTI_SMN_TRANS_ID_DIS_UPS_", 11, 11, &umr_bitfield_default }, - { "SMN_ZERO_BE_WR_EN_DNS_DEV0_", 16, 16, &umr_bitfield_default }, - { "SMN_ZERO_BE_RD_EN_DNS_DEV0_", 20, 20, &umr_bitfield_default }, - { "SMN_POST_MASK_EN_DNS_DEV0_", 24, 24, &umr_bitfield_default }, - { "MULTI_SMN_TRANS_ID_DIS_DNS_DEV0_", 28, 28, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSMN_MST_EP_CNTL1[] = { - { "SMN_POST_MASK_EN_EP_DEV0_PF0_", 0, 0, &umr_bitfield_default }, - { "SMN_POST_MASK_EN_EP_DEV0_PF1_", 1, 1, &umr_bitfield_default }, - { "SMN_POST_MASK_EN_EP_DEV0_PF2_", 2, 2, &umr_bitfield_default }, - { "SMN_POST_MASK_EN_EP_DEV0_PF3_", 3, 3, &umr_bitfield_default }, - { "SMN_POST_MASK_EN_EP_DEV0_PF4_", 4, 4, &umr_bitfield_default }, - { "SMN_POST_MASK_EN_EP_DEV0_PF5_", 5, 5, &umr_bitfield_default }, - { "SMN_POST_MASK_EN_EP_DEV0_PF6_", 6, 6, &umr_bitfield_default }, - { "SMN_POST_MASK_EN_EP_DEV0_PF7_", 7, 7, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSMN_MST_EP_CNTL2[] = { - { "MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF0_", 0, 0, &umr_bitfield_default }, - { "MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF1_", 1, 1, &umr_bitfield_default }, - { "MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF2_", 2, 2, &umr_bitfield_default }, - { "MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF3_", 3, 3, &umr_bitfield_default }, - { "MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF4_", 4, 4, &umr_bitfield_default }, - { "MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF5_", 5, 5, &umr_bitfield_default }, - { "MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF6_", 6, 6, &umr_bitfield_default }, - { "MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF7_", 7, 7, &umr_bitfield_default }, -}; -static struct umr_bitfield ixNBIF_SDP_VWR_VCHG_DIS_CTRL[] = { - { "SDP_VWR_VCHG_ENDP_F0_DIS_", 0, 0, &umr_bitfield_default }, - { "SDP_VWR_VCHG_ENDP_F1_DIS_", 1, 1, &umr_bitfield_default }, - { "SDP_VWR_VCHG_ENDP_F2_DIS_", 2, 2, &umr_bitfield_default }, - { "SDP_VWR_VCHG_ENDP_F3_DIS_", 3, 3, &umr_bitfield_default }, - { "SDP_VWR_VCHG_ENDP_F4_DIS_", 4, 4, &umr_bitfield_default }, - { "SDP_VWR_VCHG_ENDP_F5_DIS_", 5, 5, &umr_bitfield_default }, - { "SDP_VWR_VCHG_ENDP_F6_DIS_", 6, 6, &umr_bitfield_default }, - { "SDP_VWR_VCHG_ENDP_F7_DIS_", 7, 7, &umr_bitfield_default }, - { "SDP_VWR_VCHG_SWDS_P0_DIS_", 24, 24, &umr_bitfield_default }, -}; -static struct umr_bitfield ixNBIF_SDP_VWR_VCHG_RST_CTRL0[] = { - { "SDP_VWR_VCHG_ENDP_F0_RST_OVRD_EN_", 0, 0, &umr_bitfield_default }, - { "SDP_VWR_VCHG_ENDP_F1_RST_OVRD_EN_", 1, 1, &umr_bitfield_default }, - { "SDP_VWR_VCHG_ENDP_F2_RST_OVRD_EN_", 2, 2, &umr_bitfield_default }, - { "SDP_VWR_VCHG_ENDP_F3_RST_OVRD_EN_", 3, 3, &umr_bitfield_default }, - { "SDP_VWR_VCHG_ENDP_F4_RST_OVRD_EN_", 4, 4, &umr_bitfield_default }, - { "SDP_VWR_VCHG_ENDP_F5_RST_OVRD_EN_", 5, 5, &umr_bitfield_default }, - { "SDP_VWR_VCHG_ENDP_F6_RST_OVRD_EN_", 6, 6, &umr_bitfield_default }, - { "SDP_VWR_VCHG_ENDP_F7_RST_OVRD_EN_", 7, 7, &umr_bitfield_default }, - { "SDP_VWR_VCHG_SWDS_P0_RST_OVRD_EN_", 24, 24, &umr_bitfield_default }, -}; -static struct umr_bitfield ixNBIF_SDP_VWR_VCHG_RST_CTRL1[] = { - { "SDP_VWR_VCHG_ENDP_F0_RST_OVRD_VAL_", 0, 0, &umr_bitfield_default }, - { "SDP_VWR_VCHG_ENDP_F1_RST_OVRD_VAL_", 1, 1, &umr_bitfield_default }, - { "SDP_VWR_VCHG_ENDP_F2_RST_OVRD_VAL_", 2, 2, &umr_bitfield_default }, - { "SDP_VWR_VCHG_ENDP_F3_RST_OVRD_VAL_", 3, 3, &umr_bitfield_default }, - { "SDP_VWR_VCHG_ENDP_F4_RST_OVRD_VAL_", 4, 4, &umr_bitfield_default }, - { "SDP_VWR_VCHG_ENDP_F5_RST_OVRD_VAL_", 5, 5, &umr_bitfield_default }, - { "SDP_VWR_VCHG_ENDP_F6_RST_OVRD_VAL_", 6, 6, &umr_bitfield_default }, - { "SDP_VWR_VCHG_ENDP_F7_RST_OVRD_VAL_", 7, 7, &umr_bitfield_default }, - { "SDP_VWR_VCHG_SWDS_P0_RST_OVRD_VAL_", 24, 24, &umr_bitfield_default }, -}; -static struct umr_bitfield ixNBIF_SDP_VWR_VCHG_TRIG[] = { - { "SDP_VWR_VCHG_ENDP_F0_TRIG_", 0, 0, &umr_bitfield_default }, - { "SDP_VWR_VCHG_ENDP_F1_TRIG_", 1, 1, &umr_bitfield_default }, - { "SDP_VWR_VCHG_ENDP_F2_TRIG_", 2, 2, &umr_bitfield_default }, - { "SDP_VWR_VCHG_ENDP_F3_TRIG_", 3, 3, &umr_bitfield_default }, - { "SDP_VWR_VCHG_ENDP_F4_TRIG_", 4, 4, &umr_bitfield_default }, - { "SDP_VWR_VCHG_ENDP_F5_TRIG_", 5, 5, &umr_bitfield_default }, - { "SDP_VWR_VCHG_ENDP_F6_TRIG_", 6, 6, &umr_bitfield_default }, - { "SDP_VWR_VCHG_ENDP_F7_TRIG_", 7, 7, &umr_bitfield_default }, - { "SDP_VWR_VCHG_SWDS_P0_TRIG_", 24, 24, &umr_bitfield_default }, -}; -static struct umr_bitfield ixBME_DUMMY_CNTL_0[] = { - { "BME_DUMMY_RSPSTS_DEV0_F0_", 0, 1, &umr_bitfield_default }, - { "BME_DUMMY_RSPSTS_DEV0_F1_", 2, 3, &umr_bitfield_default }, - { "BME_DUMMY_RSPSTS_DEV0_F2_", 4, 5, &umr_bitfield_default }, - { "BME_DUMMY_RSPSTS_DEV0_F3_", 6, 7, &umr_bitfield_default }, - { "BME_DUMMY_RSPSTS_DEV0_F4_", 8, 9, &umr_bitfield_default }, - { "BME_DUMMY_RSPSTS_DEV0_F5_", 10, 11, &umr_bitfield_default }, - { "BME_DUMMY_RSPSTS_DEV0_F6_", 12, 13, &umr_bitfield_default }, - { "BME_DUMMY_RSPSTS_DEV0_F7_", 14, 15, &umr_bitfield_default }, -}; -static struct umr_bitfield ixBIFC_THT_CNTL[] = { - { "CREDIT_ALLOC_THT_RD_VC0_", 0, 3, &umr_bitfield_default }, - { "CREDIT_ALLOC_THT_WR_VC0_", 4, 7, &umr_bitfield_default }, - { "CREDIT_ALLOC_THT_WR_VC1_", 8, 11, &umr_bitfield_default }, -}; -static struct umr_bitfield ixBIFC_HSTARB_CNTL[] = { - { "SLVARB_MODE_", 0, 1, &umr_bitfield_default }, -}; -static struct umr_bitfield ixBIFC_GSI_CNTL[] = { - { "GSI_SDP_RSP_ARB_MODE_", 0, 1, &umr_bitfield_default }, - { "GSI_CPL_RSP_ARB_MODE_", 2, 4, &umr_bitfield_default }, - { "GSI_CPL_INTERLEAVING_EN_", 5, 5, &umr_bitfield_default }, - { "GSI_CPL_PCR_EP_CAUSE_UR_EN_", 6, 6, &umr_bitfield_default }, - { "GSI_CPL_SMN_P_EP_CAUSE_UR_EN_", 7, 7, &umr_bitfield_default }, - { "GSI_CPL_SMN_NP_EP_CAUSE_UR_EN_", 8, 8, &umr_bitfield_default }, - { "GSI_CPL_SST_EP_CAUSE_UR_EN_", 9, 9, &umr_bitfield_default }, - { "GSI_SDP_REQ_ARB_MODE_", 10, 11, &umr_bitfield_default }, - { "GSI_SMN_REQ_ARB_MODE_", 12, 13, &umr_bitfield_default }, -}; -static struct umr_bitfield ixBIFC_PCIEFUNC_CNTL[] = { - { "DMA_NON_PCIEFUNC_BUSDEVFUNC_", 0, 15, &umr_bitfield_default }, - { "MP1SYSHUBDATA_DRAM_IS_PCIEFUNC_", 16, 16, &umr_bitfield_default }, -}; -static struct umr_bitfield ixBIFC_SDP_CNTL_0[] = { - { "HRP_SDP_DISCON_HYSTERESIS_", 0, 5, &umr_bitfield_default }, - { "GSI_SDP_DISCON_HYSTERESIS_", 6, 11, &umr_bitfield_default }, - { "GMI_DNS_SDP_DISCON_HYSTERESIS_", 12, 17, &umr_bitfield_default }, - { "GMI_UPS_SDP_DISCON_HYSTERESIS_", 18, 23, &umr_bitfield_default }, -}; -static struct umr_bitfield ixBIFC_PERF_CNTL_0[] = { - { "PERF_CNT_MMIO_RD_EN_", 0, 0, &umr_bitfield_default }, - { "PERF_CNT_MMIO_WR_EN_", 1, 1, &umr_bitfield_default }, - { "PERF_CNT_MMIO_RD_RESET_", 8, 8, &umr_bitfield_default }, - { "PERF_CNT_MMIO_WR_RESET_", 9, 9, &umr_bitfield_default }, - { "PERF_CNT_MMIO_RD_SEL_", 16, 20, &umr_bitfield_default }, - { "PERF_CNT_MMIO_WR_SEL_", 24, 28, &umr_bitfield_default }, -}; -static struct umr_bitfield ixBIFC_PERF_CNTL_1[] = { - { "PERF_CNT_DMA_RD_EN_", 0, 0, &umr_bitfield_default }, - { "PERF_CNT_DMA_WR_EN_", 1, 1, &umr_bitfield_default }, - { "PERF_CNT_DMA_RD_RESET_", 8, 8, &umr_bitfield_default }, - { "PERF_CNT_DMA_WR_RESET_", 9, 9, &umr_bitfield_default }, - { "PERF_CNT_DMA_RD_SEL_", 16, 21, &umr_bitfield_default }, - { "PERF_CNT_DMA_WR_SEL_", 24, 30, &umr_bitfield_default }, -}; -static struct umr_bitfield ixBIFC_PERF_CNT_MMIO_RD[] = { - { "PERF_CNT_MMIO_RD_VALUE_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixBIFC_PERF_CNT_MMIO_WR[] = { - { "PERF_CNT_MMIO_WR_VALUE_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixBIFC_PERF_CNT_DMA_RD[] = { - { "PERF_CNT_DMA_RD_VALUE_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixBIFC_PERF_CNT_DMA_WR[] = { - { "PERF_CNT_DMA_WR_VALUE_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixNBIF_REGIF_ERRSET_CTRL[] = { - { "DROP_NONPF_MMREGREQ_SETERR_DIS_", 0, 0, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSMN_MST_EP_CNTL3[] = { - { "SMN_ZERO_BE_WR_EN_EP_DEV0_PF0_", 0, 0, &umr_bitfield_default }, - { "SMN_ZERO_BE_WR_EN_EP_DEV0_PF1_", 1, 1, &umr_bitfield_default }, - { "SMN_ZERO_BE_WR_EN_EP_DEV0_PF2_", 2, 2, &umr_bitfield_default }, - { "SMN_ZERO_BE_WR_EN_EP_DEV0_PF3_", 3, 3, &umr_bitfield_default }, - { "SMN_ZERO_BE_WR_EN_EP_DEV0_PF4_", 4, 4, &umr_bitfield_default }, - { "SMN_ZERO_BE_WR_EN_EP_DEV0_PF5_", 5, 5, &umr_bitfield_default }, - { "SMN_ZERO_BE_WR_EN_EP_DEV0_PF6_", 6, 6, &umr_bitfield_default }, - { "SMN_ZERO_BE_WR_EN_EP_DEV0_PF7_", 7, 7, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSMN_MST_EP_CNTL4[] = { - { "SMN_ZERO_BE_RD_EN_EP_DEV0_PF0_", 0, 0, &umr_bitfield_default }, - { "SMN_ZERO_BE_RD_EN_EP_DEV0_PF1_", 1, 1, &umr_bitfield_default }, - { "SMN_ZERO_BE_RD_EN_EP_DEV0_PF2_", 2, 2, &umr_bitfield_default }, - { "SMN_ZERO_BE_RD_EN_EP_DEV0_PF3_", 3, 3, &umr_bitfield_default }, - { "SMN_ZERO_BE_RD_EN_EP_DEV0_PF4_", 4, 4, &umr_bitfield_default }, - { "SMN_ZERO_BE_RD_EN_EP_DEV0_PF5_", 5, 5, &umr_bitfield_default }, - { "SMN_ZERO_BE_RD_EN_EP_DEV0_PF6_", 6, 6, &umr_bitfield_default }, - { "SMN_ZERO_BE_RD_EN_EP_DEV0_PF7_", 7, 7, &umr_bitfield_default }, -}; -static struct umr_bitfield ixBIF_SELFRING_BUFFER_VID[] = { - { "DOORBELL_MONITOR_CID_", 0, 7, &umr_bitfield_default }, - { "IOHUB_RAS_INTR_CID_", 8, 15, &umr_bitfield_default }, -}; -static struct umr_bitfield ixBIF_SELFRING_VECTOR_CNTL[] = { - { "MISC_DB_MNTR_INTR_DIS_", 0, 0, &umr_bitfield_default }, -}; -static struct umr_bitfield ixBIF_RAS_LEAF0_CTRL[] = { - { "POISON_DET_EN_", 0, 0, &umr_bitfield_default }, - { "POISON_ERREVENT_EN_", 1, 1, &umr_bitfield_default }, - { "POISON_STALL_EN_", 2, 2, &umr_bitfield_default }, - { "PARITY_DET_EN_", 4, 4, &umr_bitfield_default }, - { "PARITY_ERREVENT_EN_", 5, 5, &umr_bitfield_default }, - { "PARITY_STALL_EN_", 6, 6, &umr_bitfield_default }, - { "ERR_EVENT_RECV_", 16, 16, &umr_bitfield_default }, - { "LINK_DIS_RECV_", 17, 17, &umr_bitfield_default }, - { "POISON_ERR_DET_", 18, 18, &umr_bitfield_default }, - { "PARITY_ERR_DET_", 19, 19, &umr_bitfield_default }, - { "ERR_EVENT_SENT_", 20, 20, &umr_bitfield_default }, - { "EGRESS_STALLED_", 21, 21, &umr_bitfield_default }, -}; -static struct umr_bitfield ixBIF_RAS_LEAF1_CTRL[] = { - { "POISON_DET_EN_", 0, 0, &umr_bitfield_default }, - { "POISON_ERREVENT_EN_", 1, 1, &umr_bitfield_default }, - { "POISON_STALL_EN_", 2, 2, &umr_bitfield_default }, - { "PARITY_DET_EN_", 4, 4, &umr_bitfield_default }, - { "PARITY_ERREVENT_EN_", 5, 5, &umr_bitfield_default }, - { "PARITY_STALL_EN_", 6, 6, &umr_bitfield_default }, - { "ERR_EVENT_RECV_", 16, 16, &umr_bitfield_default }, - { "LINK_DIS_RECV_", 17, 17, &umr_bitfield_default }, - { "POISON_ERR_DET_", 18, 18, &umr_bitfield_default }, - { "PARITY_ERR_DET_", 19, 19, &umr_bitfield_default }, - { "ERR_EVENT_SENT_", 20, 20, &umr_bitfield_default }, - { "EGRESS_STALLED_", 21, 21, &umr_bitfield_default }, -}; -static struct umr_bitfield ixBIF_RAS_LEAF2_CTRL[] = { - { "POISON_DET_EN_", 0, 0, &umr_bitfield_default }, - { "POISON_ERREVENT_EN_", 1, 1, &umr_bitfield_default }, - { "POISON_STALL_EN_", 2, 2, &umr_bitfield_default }, - { "PARITY_DET_EN_", 4, 4, &umr_bitfield_default }, - { "PARITY_ERREVENT_EN_", 5, 5, &umr_bitfield_default }, - { "PARITY_STALL_EN_", 6, 6, &umr_bitfield_default }, - { "ERR_EVENT_RECV_", 16, 16, &umr_bitfield_default }, - { "LINK_DIS_RECV_", 17, 17, &umr_bitfield_default }, - { "POISON_ERR_DET_", 18, 18, &umr_bitfield_default }, - { "PARITY_ERR_DET_", 19, 19, &umr_bitfield_default }, - { "ERR_EVENT_SENT_", 20, 20, &umr_bitfield_default }, - { "EGRESS_STALLED_", 21, 21, &umr_bitfield_default }, -}; -static struct umr_bitfield ixBIF_RAS_MISC_CTRL[] = { - { "LINKDIS_TRIG_ERREVENT_EN_", 0, 0, &umr_bitfield_default }, -}; -static struct umr_bitfield ixBIF_IOHUB_RAS_IH_CNTL[] = { - { "RAS_IH_INTR_EN_", 0, 0, &umr_bitfield_default }, -}; -static struct umr_bitfield ixBIF_RAS_VWR_FROM_IOHUB[] = { - { "RAS_IH_INTR_TRIG_", 0, 0, &umr_bitfield_default }, -}; -static struct umr_bitfield ixRCC_PFC_LTR_CNTL[] = { - { "SNOOP_LATENCY_VALUE_", 0, 9, &umr_bitfield_default }, - { "SNOOP_LATENCY_SCALE_", 10, 12, &umr_bitfield_default }, - { "SNOOP_REQUIREMENT_", 15, 15, &umr_bitfield_default }, - { "NONSNOOP_LATENCY_VALUE_", 16, 25, &umr_bitfield_default }, - { "NONSNOOP_LATENCY_SCALE_", 26, 28, &umr_bitfield_default }, - { "NONSNOOP_REQUIREMENT_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixRCC_PFC_PME_RESTORE[] = { - { "PME_RESTORE_PME_EN_", 0, 0, &umr_bitfield_default }, - { "PME_RESTORE_PME_STATUS_", 8, 8, &umr_bitfield_default }, -}; -static struct umr_bitfield ixRCC_PFC_STICKY_RESTORE_0[] = { - { "RESTORE_PSN_ERR_STATUS_", 0, 0, &umr_bitfield_default }, - { "RESTORE_CPL_TIMEOUT_STATUS_", 1, 1, &umr_bitfield_default }, - { "RESTORE_CPL_ABORT_ERR_STATUS_", 2, 2, &umr_bitfield_default }, - { "RESTORE_UNEXP_CPL_STATUS_", 3, 3, &umr_bitfield_default }, - { "RESTORE_MAL_TLP_STATUS_", 4, 4, &umr_bitfield_default }, - { "RESTORE_ECRC_ERR_STATUS_", 5, 5, &umr_bitfield_default }, - { "RESTORE_UNSUPP_REQ_ERR_STATUS_", 6, 6, &umr_bitfield_default }, - { "RESTORE_ADVISORY_NONFATAL_ERR_STATUS_", 7, 7, &umr_bitfield_default }, -}; -static struct umr_bitfield ixRCC_PFC_STICKY_RESTORE_1[] = { - { "RESTORE_TLP_HDR_0_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixRCC_PFC_STICKY_RESTORE_2[] = { - { "RESTORE_TLP_HDR_1_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixRCC_PFC_STICKY_RESTORE_3[] = { - { "RESTORE_TLP_HDR_2_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixRCC_PFC_STICKY_RESTORE_4[] = { - { "RESTORE_TLP_HDR_3_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixRCC_PFC_STICKY_RESTORE_5[] = { - { "RESTORE_TLP_PREFIX_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixRCC_PFC_AUXPWR_CNTL[] = { - { "AUX_CURRENT_OVERRIDE_", 0, 2, &umr_bitfield_default }, - { "AUX_POWER_DETECTED_OVERRIDE_", 3, 3, &umr_bitfield_default }, -}; -static struct umr_bitfield ixRCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL[] = { - { "SNOOP_LATENCY_VALUE_", 0, 9, &umr_bitfield_default }, - { "SNOOP_LATENCY_SCALE_", 10, 12, &umr_bitfield_default }, - { "SNOOP_REQUIREMENT_", 15, 15, &umr_bitfield_default }, - { "NONSNOOP_LATENCY_VALUE_", 16, 25, &umr_bitfield_default }, - { "NONSNOOP_LATENCY_SCALE_", 26, 28, &umr_bitfield_default }, - { "NONSNOOP_REQUIREMENT_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixRCCPFCAMDGFXAZ_RCC_PFC_PME_RESTORE[] = { - { "PME_RESTORE_PME_EN_", 0, 0, &umr_bitfield_default }, - { "PME_RESTORE_PME_STATUS_", 8, 8, &umr_bitfield_default }, -}; -static struct umr_bitfield ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0[] = { - { "RESTORE_PSN_ERR_STATUS_", 0, 0, &umr_bitfield_default }, - { "RESTORE_CPL_TIMEOUT_STATUS_", 1, 1, &umr_bitfield_default }, - { "RESTORE_CPL_ABORT_ERR_STATUS_", 2, 2, &umr_bitfield_default }, - { "RESTORE_UNEXP_CPL_STATUS_", 3, 3, &umr_bitfield_default }, - { "RESTORE_MAL_TLP_STATUS_", 4, 4, &umr_bitfield_default }, - { "RESTORE_ECRC_ERR_STATUS_", 5, 5, &umr_bitfield_default }, - { "RESTORE_UNSUPP_REQ_ERR_STATUS_", 6, 6, &umr_bitfield_default }, - { "RESTORE_ADVISORY_NONFATAL_ERR_STATUS_", 7, 7, &umr_bitfield_default }, -}; -static struct umr_bitfield ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_1[] = { - { "RESTORE_TLP_HDR_0_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_2[] = { - { "RESTORE_TLP_HDR_1_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_3[] = { - { "RESTORE_TLP_HDR_2_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_4[] = { - { "RESTORE_TLP_HDR_3_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_5[] = { - { "RESTORE_TLP_PREFIX_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixRCCPFCAMDGFXAZ_RCC_PFC_AUXPWR_CNTL[] = { - { "AUX_CURRENT_OVERRIDE_", 0, 2, &umr_bitfield_default }, - { "AUX_POWER_DETECTED_OVERRIDE_", 3, 3, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT0_ADDR_LO[] = { - { "MSG_ADDR_LO_", 2, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT0_ADDR_HI[] = { - { "MSG_ADDR_HI_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT0_MSG_DATA[] = { - { "MSG_DATA_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT0_CONTROL[] = { - { "MASK_BIT_", 0, 0, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT1_ADDR_LO[] = { - { "MSG_ADDR_LO_", 2, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT1_ADDR_HI[] = { - { "MSG_ADDR_HI_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT1_MSG_DATA[] = { - { "MSG_DATA_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT1_CONTROL[] = { - { "MASK_BIT_", 0, 0, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT2_ADDR_LO[] = { - { "MSG_ADDR_LO_", 2, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT2_ADDR_HI[] = { - { "MSG_ADDR_HI_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT2_MSG_DATA[] = { - { "MSG_DATA_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT2_CONTROL[] = { - { "MASK_BIT_", 0, 0, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT3_ADDR_LO[] = { - { "MSG_ADDR_LO_", 2, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT3_ADDR_HI[] = { - { "MSG_ADDR_HI_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT3_MSG_DATA[] = { - { "MSG_DATA_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT3_CONTROL[] = { - { "MASK_BIT_", 0, 0, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT4_ADDR_LO[] = { - { "MSG_ADDR_LO_", 2, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT4_ADDR_HI[] = { - { "MSG_ADDR_HI_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT4_MSG_DATA[] = { - { "MSG_DATA_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT4_CONTROL[] = { - { "MASK_BIT_", 0, 0, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT5_ADDR_LO[] = { - { "MSG_ADDR_LO_", 2, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT5_ADDR_HI[] = { - { "MSG_ADDR_HI_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT5_MSG_DATA[] = { - { "MSG_DATA_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT5_CONTROL[] = { - { "MASK_BIT_", 0, 0, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT6_ADDR_LO[] = { - { "MSG_ADDR_LO_", 2, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT6_ADDR_HI[] = { - { "MSG_ADDR_HI_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT6_MSG_DATA[] = { - { "MSG_DATA_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT6_CONTROL[] = { - { "MASK_BIT_", 0, 0, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT7_ADDR_LO[] = { - { "MSG_ADDR_LO_", 2, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT7_ADDR_HI[] = { - { "MSG_ADDR_HI_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT7_MSG_DATA[] = { - { "MSG_DATA_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT7_CONTROL[] = { - { "MASK_BIT_", 0, 0, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT8_ADDR_LO[] = { - { "MSG_ADDR_LO_", 2, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT8_ADDR_HI[] = { - { "MSG_ADDR_HI_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT8_MSG_DATA[] = { - { "MSG_DATA_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT8_CONTROL[] = { - { "MASK_BIT_", 0, 0, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT9_ADDR_LO[] = { - { "MSG_ADDR_LO_", 2, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT9_ADDR_HI[] = { - { "MSG_ADDR_HI_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT9_MSG_DATA[] = { - { "MSG_DATA_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT9_CONTROL[] = { - { "MASK_BIT_", 0, 0, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT10_ADDR_LO[] = { - { "MSG_ADDR_LO_", 2, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT10_ADDR_HI[] = { - { "MSG_ADDR_HI_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT10_MSG_DATA[] = { - { "MSG_DATA_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT10_CONTROL[] = { - { "MASK_BIT_", 0, 0, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT11_ADDR_LO[] = { - { "MSG_ADDR_LO_", 2, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT11_ADDR_HI[] = { - { "MSG_ADDR_HI_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT11_MSG_DATA[] = { - { "MSG_DATA_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT11_CONTROL[] = { - { "MASK_BIT_", 0, 0, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT12_ADDR_LO[] = { - { "MSG_ADDR_LO_", 2, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT12_ADDR_HI[] = { - { "MSG_ADDR_HI_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT12_MSG_DATA[] = { - { "MSG_DATA_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT12_CONTROL[] = { - { "MASK_BIT_", 0, 0, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT13_ADDR_LO[] = { - { "MSG_ADDR_LO_", 2, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT13_ADDR_HI[] = { - { "MSG_ADDR_HI_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT13_MSG_DATA[] = { - { "MSG_DATA_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT13_CONTROL[] = { - { "MASK_BIT_", 0, 0, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT14_ADDR_LO[] = { - { "MSG_ADDR_LO_", 2, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT14_ADDR_HI[] = { - { "MSG_ADDR_HI_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT14_MSG_DATA[] = { - { "MSG_DATA_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT14_CONTROL[] = { - { "MASK_BIT_", 0, 0, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT15_ADDR_LO[] = { - { "MSG_ADDR_LO_", 2, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT15_ADDR_HI[] = { - { "MSG_ADDR_HI_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT15_MSG_DATA[] = { - { "MSG_DATA_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT15_CONTROL[] = { - { "MASK_BIT_", 0, 0, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT16_ADDR_LO[] = { - { "MSG_ADDR_LO_", 2, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT16_ADDR_HI[] = { - { "MSG_ADDR_HI_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT16_MSG_DATA[] = { - { "MSG_DATA_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT16_CONTROL[] = { - { "MASK_BIT_", 0, 0, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT17_ADDR_LO[] = { - { "MSG_ADDR_LO_", 2, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT17_ADDR_HI[] = { - { "MSG_ADDR_HI_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT17_MSG_DATA[] = { - { "MSG_DATA_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT17_CONTROL[] = { - { "MASK_BIT_", 0, 0, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT18_ADDR_LO[] = { - { "MSG_ADDR_LO_", 2, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT18_ADDR_HI[] = { - { "MSG_ADDR_HI_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT18_MSG_DATA[] = { - { "MSG_DATA_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT18_CONTROL[] = { - { "MASK_BIT_", 0, 0, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT19_ADDR_LO[] = { - { "MSG_ADDR_LO_", 2, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT19_ADDR_HI[] = { - { "MSG_ADDR_HI_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT19_MSG_DATA[] = { - { "MSG_DATA_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT19_CONTROL[] = { - { "MASK_BIT_", 0, 0, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT20_ADDR_LO[] = { - { "MSG_ADDR_LO_", 2, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT20_ADDR_HI[] = { - { "MSG_ADDR_HI_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT20_MSG_DATA[] = { - { "MSG_DATA_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT20_CONTROL[] = { - { "MASK_BIT_", 0, 0, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT21_ADDR_LO[] = { - { "MSG_ADDR_LO_", 2, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT21_ADDR_HI[] = { - { "MSG_ADDR_HI_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT21_MSG_DATA[] = { - { "MSG_DATA_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT21_CONTROL[] = { - { "MASK_BIT_", 0, 0, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT22_ADDR_LO[] = { - { "MSG_ADDR_LO_", 2, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT22_ADDR_HI[] = { - { "MSG_ADDR_HI_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT22_MSG_DATA[] = { - { "MSG_DATA_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT22_CONTROL[] = { - { "MASK_BIT_", 0, 0, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT23_ADDR_LO[] = { - { "MSG_ADDR_LO_", 2, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT23_ADDR_HI[] = { - { "MSG_ADDR_HI_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT23_MSG_DATA[] = { - { "MSG_DATA_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT23_CONTROL[] = { - { "MASK_BIT_", 0, 0, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT24_ADDR_LO[] = { - { "MSG_ADDR_LO_", 2, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT24_ADDR_HI[] = { - { "MSG_ADDR_HI_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT24_MSG_DATA[] = { - { "MSG_DATA_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT24_CONTROL[] = { - { "MASK_BIT_", 0, 0, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT25_ADDR_LO[] = { - { "MSG_ADDR_LO_", 2, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT25_ADDR_HI[] = { - { "MSG_ADDR_HI_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT25_MSG_DATA[] = { - { "MSG_DATA_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT25_CONTROL[] = { - { "MASK_BIT_", 0, 0, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT26_ADDR_LO[] = { - { "MSG_ADDR_LO_", 2, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT26_ADDR_HI[] = { - { "MSG_ADDR_HI_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT26_MSG_DATA[] = { - { "MSG_DATA_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT26_CONTROL[] = { - { "MASK_BIT_", 0, 0, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT27_ADDR_LO[] = { - { "MSG_ADDR_LO_", 2, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT27_ADDR_HI[] = { - { "MSG_ADDR_HI_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT27_MSG_DATA[] = { - { "MSG_DATA_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT27_CONTROL[] = { - { "MASK_BIT_", 0, 0, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT28_ADDR_LO[] = { - { "MSG_ADDR_LO_", 2, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT28_ADDR_HI[] = { - { "MSG_ADDR_HI_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT28_MSG_DATA[] = { - { "MSG_DATA_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT28_CONTROL[] = { - { "MASK_BIT_", 0, 0, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT29_ADDR_LO[] = { - { "MSG_ADDR_LO_", 2, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT29_ADDR_HI[] = { - { "MSG_ADDR_HI_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT29_MSG_DATA[] = { - { "MSG_DATA_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT29_CONTROL[] = { - { "MASK_BIT_", 0, 0, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT30_ADDR_LO[] = { - { "MSG_ADDR_LO_", 2, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT30_ADDR_HI[] = { - { "MSG_ADDR_HI_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT30_MSG_DATA[] = { - { "MSG_DATA_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT30_CONTROL[] = { - { "MASK_BIT_", 0, 0, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT31_ADDR_LO[] = { - { "MSG_ADDR_LO_", 2, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT31_ADDR_HI[] = { - { "MSG_ADDR_HI_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT31_MSG_DATA[] = { - { "MSG_DATA_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_VECT31_CONTROL[] = { - { "MASK_BIT_", 0, 0, &umr_bitfield_default }, -}; -static struct umr_bitfield ixPCIEMSIX_PBA[] = { - { "MSIX_PENDING_BITS_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK[] = { - { "HST_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_", 0, 0, &umr_bitfield_default }, - { "HST_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_", 1, 1, &umr_bitfield_default }, - { "HST_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_", 2, 2, &umr_bitfield_default }, - { "HST_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_", 3, 3, &umr_bitfield_default }, - { "HST_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_", 4, 4, &umr_bitfield_default }, - { "HST_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_", 5, 5, &umr_bitfield_default }, - { "HST_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_", 6, 6, &umr_bitfield_default }, - { "HST_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_", 7, 7, &umr_bitfield_default }, - { "DMA_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_", 16, 16, &umr_bitfield_default }, - { "DMA_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_", 17, 17, &umr_bitfield_default }, - { "DMA_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_", 18, 18, &umr_bitfield_default }, - { "DMA_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_", 19, 19, &umr_bitfield_default }, - { "DMA_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_", 20, 20, &umr_bitfield_default }, - { "DMA_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_", 21, 21, &umr_bitfield_default }, - { "DMA_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_", 22, 22, &umr_bitfield_default }, - { "DMA_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_", 23, 23, &umr_bitfield_default }, - { "SYSHUB_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_", 28, 28, &umr_bitfield_default }, - { "SYSHUB_SOCCLK_DS_EN_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSYSHUBMMREGIND_SYSHUB_DS_CTRL2_SOCCLK[] = { - { "SYSHUB_SOCCLK_DS_TIMER_", 0, 15, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK[] = { - { "SYSHUB_bgen_socclk_HST_SW0_bypass_en_", 0, 0, &umr_bitfield_default }, - { "SYSHUB_bgen_socclk_HST_SW1_bypass_en_", 1, 1, &umr_bitfield_default }, - { "SYSHUB_bgen_socclk_DMA_SW0_bypass_en_", 15, 15, &umr_bitfield_default }, - { "SYSHUB_bgen_socclk_DMA_SW1_bypass_en_", 16, 16, &umr_bitfield_default }, - { "SYSHUB_bgen_socclk_DMA_SW2_bypass_en_", 17, 17, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK[] = { - { "SYSHUB_bgen_socclk_HST_SW0_imm_en_", 0, 0, &umr_bitfield_default }, - { "SYSHUB_bgen_socclk_HST_SW1_imm_en_", 1, 1, &umr_bitfield_default }, - { "SYSHUB_bgen_socclk_DMA_SW0_imm_en_", 15, 15, &umr_bitfield_default }, - { "SYSHUB_bgen_socclk_DMA_SW1_imm_en_", 16, 16, &umr_bitfield_default }, - { "SYSHUB_bgen_socclk_DMA_SW2_imm_en_", 17, 17, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSYSHUBMMREGIND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL[] = { - { "QOS_CNTL_MODE_", 0, 0, &umr_bitfield_default }, - { "QOS_MAX_VALUE_", 1, 4, &umr_bitfield_default }, - { "QOS_MIN_VALUE_", 5, 8, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSYSHUBMMREGIND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL[] = { - { "QOS_CNTL_MODE_", 0, 0, &umr_bitfield_default }, - { "QOS_MAX_VALUE_", 1, 4, &umr_bitfield_default }, - { "QOS_MIN_VALUE_", 5, 8, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL[] = { - { "FLR_ON_RS_RESET_EN_", 0, 0, &umr_bitfield_default }, - { "LKRST_ON_RS_RESET_EN_", 1, 1, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_EN_", 8, 8, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_VALUE_", 9, 12, &umr_bitfield_default }, - { "READ_WRR_WEIGHT_", 16, 23, &umr_bitfield_default }, - { "WRITE_WRR_WEIGHT_", 24, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL[] = { - { "FLR_ON_RS_RESET_EN_", 0, 0, &umr_bitfield_default }, - { "LKRST_ON_RS_RESET_EN_", 1, 1, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_EN_", 8, 8, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_VALUE_", 9, 12, &umr_bitfield_default }, - { "READ_WRR_WEIGHT_", 16, 23, &umr_bitfield_default }, - { "WRITE_WRR_WEIGHT_", 24, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL[] = { - { "FLR_ON_RS_RESET_EN_", 0, 0, &umr_bitfield_default }, - { "LKRST_ON_RS_RESET_EN_", 1, 1, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_EN_", 8, 8, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_VALUE_", 9, 12, &umr_bitfield_default }, - { "READ_WRR_WEIGHT_", 16, 23, &umr_bitfield_default }, - { "WRITE_WRR_WEIGHT_", 24, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL[] = { - { "FLR_ON_RS_RESET_EN_", 0, 0, &umr_bitfield_default }, - { "LKRST_ON_RS_RESET_EN_", 1, 1, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_EN_", 8, 8, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_VALUE_", 9, 12, &umr_bitfield_default }, - { "READ_WRR_WEIGHT_", 16, 23, &umr_bitfield_default }, - { "WRITE_WRR_WEIGHT_", 24, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL[] = { - { "FLR_ON_RS_RESET_EN_", 0, 0, &umr_bitfield_default }, - { "LKRST_ON_RS_RESET_EN_", 1, 1, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_EN_", 8, 8, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_VALUE_", 9, 12, &umr_bitfield_default }, - { "READ_WRR_WEIGHT_", 16, 23, &umr_bitfield_default }, - { "WRITE_WRR_WEIGHT_", 24, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL[] = { - { "FLR_ON_RS_RESET_EN_", 0, 0, &umr_bitfield_default }, - { "LKRST_ON_RS_RESET_EN_", 1, 1, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_EN_", 8, 8, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_VALUE_", 9, 12, &umr_bitfield_default }, - { "READ_WRR_WEIGHT_", 16, 23, &umr_bitfield_default }, - { "WRITE_WRR_WEIGHT_", 24, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL[] = { - { "FLR_ON_RS_RESET_EN_", 0, 0, &umr_bitfield_default }, - { "LKRST_ON_RS_RESET_EN_", 1, 1, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_EN_", 8, 8, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_VALUE_", 9, 12, &umr_bitfield_default }, - { "READ_WRR_WEIGHT_", 16, 23, &umr_bitfield_default }, - { "WRITE_WRR_WEIGHT_", 24, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL[] = { - { "FLR_ON_RS_RESET_EN_", 0, 0, &umr_bitfield_default }, - { "LKRST_ON_RS_RESET_EN_", 1, 1, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_EN_", 8, 8, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_VALUE_", 9, 12, &umr_bitfield_default }, - { "READ_WRR_WEIGHT_", 16, 23, &umr_bitfield_default }, - { "WRITE_WRR_WEIGHT_", 24, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSYSHUBMMREGIND_SYSHUB_CG_CNTL[] = { - { "SYSHUB_CG_EN_", 0, 0, &umr_bitfield_default }, - { "SYSHUB_CG_IDLE_TIMER_", 8, 15, &umr_bitfield_default }, - { "SYSHUB_CG_WAKEUP_TIMER_", 16, 23, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSYSHUBMMREGIND_SYSHUB_TRANS_IDLE[] = { - { "SYSHUB_TRANS_IDLE_VF0_", 0, 0, &umr_bitfield_default }, - { "SYSHUB_TRANS_IDLE_VF1_", 1, 1, &umr_bitfield_default }, - { "SYSHUB_TRANS_IDLE_VF2_", 2, 2, &umr_bitfield_default }, - { "SYSHUB_TRANS_IDLE_VF3_", 3, 3, &umr_bitfield_default }, - { "SYSHUB_TRANS_IDLE_VF4_", 4, 4, &umr_bitfield_default }, - { "SYSHUB_TRANS_IDLE_VF5_", 5, 5, &umr_bitfield_default }, - { "SYSHUB_TRANS_IDLE_VF6_", 6, 6, &umr_bitfield_default }, - { "SYSHUB_TRANS_IDLE_VF7_", 7, 7, &umr_bitfield_default }, - { "SYSHUB_TRANS_IDLE_VF8_", 8, 8, &umr_bitfield_default }, - { "SYSHUB_TRANS_IDLE_VF9_", 9, 9, &umr_bitfield_default }, - { "SYSHUB_TRANS_IDLE_VF10_", 10, 10, &umr_bitfield_default }, - { "SYSHUB_TRANS_IDLE_VF11_", 11, 11, &umr_bitfield_default }, - { "SYSHUB_TRANS_IDLE_VF12_", 12, 12, &umr_bitfield_default }, - { "SYSHUB_TRANS_IDLE_VF13_", 13, 13, &umr_bitfield_default }, - { "SYSHUB_TRANS_IDLE_VF14_", 14, 14, &umr_bitfield_default }, - { "SYSHUB_TRANS_IDLE_VF15_", 15, 15, &umr_bitfield_default }, - { "SYSHUB_TRANS_IDLE_PF_", 16, 16, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSYSHUBMMREGIND_SYSHUB_HP_TIMER[] = { - { "SYSHUB_HP_TIMER_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSYSHUBMMREGIND_SYSHUB_SCRATCH[] = { - { "SCRATCH_", 0, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK[] = { - { "HST_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_", 0, 0, &umr_bitfield_default }, - { "HST_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_", 1, 1, &umr_bitfield_default }, - { "HST_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_", 2, 2, &umr_bitfield_default }, - { "HST_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_", 3, 3, &umr_bitfield_default }, - { "HST_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_", 4, 4, &umr_bitfield_default }, - { "HST_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_", 5, 5, &umr_bitfield_default }, - { "HST_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_", 6, 6, &umr_bitfield_default }, - { "HST_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_", 7, 7, &umr_bitfield_default }, - { "DMA_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_", 16, 16, &umr_bitfield_default }, - { "DMA_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_", 17, 17, &umr_bitfield_default }, - { "DMA_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_", 18, 18, &umr_bitfield_default }, - { "DMA_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_", 19, 19, &umr_bitfield_default }, - { "DMA_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_", 20, 20, &umr_bitfield_default }, - { "DMA_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_", 21, 21, &umr_bitfield_default }, - { "DMA_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_", 22, 22, &umr_bitfield_default }, - { "DMA_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_", 23, 23, &umr_bitfield_default }, - { "SYSHUB_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_", 28, 28, &umr_bitfield_default }, - { "SYSHUB_SHUBCLK_DS_EN_", 31, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSYSHUBMMREGIND_SYSHUB_DS_CTRL2_SHUBCLK[] = { - { "SYSHUB_SHUBCLK_DS_TIMER_", 0, 15, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK[] = { - { "SYSHUB_bgen_shubclk_DMA_SW0_bypass_en_", 15, 15, &umr_bitfield_default }, - { "SYSHUB_bgen_shubclk_DMA_SW1_bypass_en_", 16, 16, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK[] = { - { "SYSHUB_bgen_shubclk_DMA_SW0_imm_en_", 15, 15, &umr_bitfield_default }, - { "SYSHUB_bgen_shubclk_DMA_SW1_imm_en_", 16, 16, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSYSHUBMMREGIND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL[] = { - { "QOS_CNTL_MODE_", 0, 0, &umr_bitfield_default }, - { "QOS_MAX_VALUE_", 1, 4, &umr_bitfield_default }, - { "QOS_MIN_VALUE_", 5, 8, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSYSHUBMMREGIND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL[] = { - { "QOS_CNTL_MODE_", 0, 0, &umr_bitfield_default }, - { "QOS_MAX_VALUE_", 1, 4, &umr_bitfield_default }, - { "QOS_MIN_VALUE_", 5, 8, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL[] = { - { "FLR_ON_RS_RESET_EN_", 0, 0, &umr_bitfield_default }, - { "LKRST_ON_RS_RESET_EN_", 1, 1, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_EN_", 8, 8, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_VALUE_", 9, 12, &umr_bitfield_default }, - { "READ_WRR_WEIGHT_", 16, 23, &umr_bitfield_default }, - { "WRITE_WRR_WEIGHT_", 24, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL[] = { - { "FLR_ON_RS_RESET_EN_", 0, 0, &umr_bitfield_default }, - { "LKRST_ON_RS_RESET_EN_", 1, 1, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_EN_", 8, 8, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_VALUE_", 9, 12, &umr_bitfield_default }, - { "READ_WRR_WEIGHT_", 16, 23, &umr_bitfield_default }, - { "WRITE_WRR_WEIGHT_", 24, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL[] = { - { "FLR_ON_RS_RESET_EN_", 0, 0, &umr_bitfield_default }, - { "LKRST_ON_RS_RESET_EN_", 1, 1, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_EN_", 8, 8, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_VALUE_", 9, 12, &umr_bitfield_default }, - { "READ_WRR_WEIGHT_", 16, 23, &umr_bitfield_default }, - { "WRITE_WRR_WEIGHT_", 24, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL[] = { - { "FLR_ON_RS_RESET_EN_", 0, 0, &umr_bitfield_default }, - { "LKRST_ON_RS_RESET_EN_", 1, 1, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_EN_", 8, 8, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_VALUE_", 9, 12, &umr_bitfield_default }, - { "READ_WRR_WEIGHT_", 16, 23, &umr_bitfield_default }, - { "WRITE_WRR_WEIGHT_", 24, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL[] = { - { "FLR_ON_RS_RESET_EN_", 0, 0, &umr_bitfield_default }, - { "LKRST_ON_RS_RESET_EN_", 1, 1, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_EN_", 8, 8, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_VALUE_", 9, 12, &umr_bitfield_default }, - { "READ_WRR_WEIGHT_", 16, 23, &umr_bitfield_default }, - { "WRITE_WRR_WEIGHT_", 24, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL[] = { - { "FLR_ON_RS_RESET_EN_", 0, 0, &umr_bitfield_default }, - { "LKRST_ON_RS_RESET_EN_", 1, 1, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_EN_", 8, 8, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_VALUE_", 9, 12, &umr_bitfield_default }, - { "READ_WRR_WEIGHT_", 16, 23, &umr_bitfield_default }, - { "WRITE_WRR_WEIGHT_", 24, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL[] = { - { "FLR_ON_RS_RESET_EN_", 0, 0, &umr_bitfield_default }, - { "LKRST_ON_RS_RESET_EN_", 1, 1, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_EN_", 8, 8, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_VALUE_", 9, 12, &umr_bitfield_default }, - { "READ_WRR_WEIGHT_", 16, 23, &umr_bitfield_default }, - { "WRITE_WRR_WEIGHT_", 24, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL[] = { - { "FLR_ON_RS_RESET_EN_", 0, 0, &umr_bitfield_default }, - { "LKRST_ON_RS_RESET_EN_", 1, 1, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_EN_", 8, 8, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_VALUE_", 9, 12, &umr_bitfield_default }, - { "READ_WRR_WEIGHT_", 16, 23, &umr_bitfield_default }, - { "WRITE_WRR_WEIGHT_", 24, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL[] = { - { "FLR_ON_RS_RESET_EN_", 0, 0, &umr_bitfield_default }, - { "LKRST_ON_RS_RESET_EN_", 1, 1, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_EN_", 8, 8, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_VALUE_", 9, 12, &umr_bitfield_default }, - { "READ_WRR_WEIGHT_", 16, 23, &umr_bitfield_default }, - { "WRITE_WRR_WEIGHT_", 24, 31, &umr_bitfield_default }, -}; -static struct umr_bitfield ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL[] = { - { "FLR_ON_RS_RESET_EN_", 0, 0, &umr_bitfield_default }, - { "LKRST_ON_RS_RESET_EN_", 1, 1, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_EN_", 8, 8, &umr_bitfield_default }, - { "QOS_STATIC_OVERRIDE_VALUE_", 9, 12, &umr_bitfield_default }, - { "READ_WRR_WEIGHT_", 16, 23, &umr_bitfield_default }, - { "WRITE_WRR_WEIGHT_", 24, 31, &umr_bitfield_default }, -}; diff --git a/src/lib/ip/nbif61_regs.i b/src/lib/ip/nbif61_regs.i deleted file mode 100644 index c2e7aa5..0000000 --- a/src/lib/ip/nbif61_regs.i +++ /dev/null @@ -1,876 +0,0 @@ - { "mmSUB_BUS_NUMBER_LATENCY", REG_MMIO, 0x0006, 0, &mmSUB_BUS_NUMBER_LATENCY[0], sizeof(mmSUB_BUS_NUMBER_LATENCY)/sizeof(mmSUB_BUS_NUMBER_LATENCY[0]), 0, 0 }, - { "mmIO_BASE_LIMIT", REG_MMIO, 0x0007, 0, &mmIO_BASE_LIMIT[0], sizeof(mmIO_BASE_LIMIT)/sizeof(mmIO_BASE_LIMIT[0]), 0, 0 }, - { "mmSECONDARY_STATUS", REG_MMIO, 0x0007, 0, &mmSECONDARY_STATUS[0], sizeof(mmSECONDARY_STATUS)/sizeof(mmSECONDARY_STATUS[0]), 0, 0 }, - { "mmMEM_BASE_LIMIT", REG_MMIO, 0x0008, 0, &mmMEM_BASE_LIMIT[0], sizeof(mmMEM_BASE_LIMIT)/sizeof(mmMEM_BASE_LIMIT[0]), 0, 0 }, - { "mmPREF_BASE_LIMIT", REG_MMIO, 0x0009, 0, &mmPREF_BASE_LIMIT[0], sizeof(mmPREF_BASE_LIMIT)/sizeof(mmPREF_BASE_LIMIT[0]), 0, 0 }, - { "mmPREF_BASE_UPPER", REG_MMIO, 0x000a, 0, &mmPREF_BASE_UPPER[0], sizeof(mmPREF_BASE_UPPER)/sizeof(mmPREF_BASE_UPPER[0]), 0, 0 }, - { "mmPREF_LIMIT_UPPER", REG_MMIO, 0x000b, 0, &mmPREF_LIMIT_UPPER[0], sizeof(mmPREF_LIMIT_UPPER)/sizeof(mmPREF_LIMIT_UPPER[0]), 0, 0 }, - { "mmIO_BASE_LIMIT_HI", REG_MMIO, 0x000c, 0, &mmIO_BASE_LIMIT_HI[0], sizeof(mmIO_BASE_LIMIT_HI)/sizeof(mmIO_BASE_LIMIT_HI[0]), 0, 0 }, - { "mmIRQ_BRIDGE_CNTL", REG_MMIO, 0x000f, 0, &mmIRQ_BRIDGE_CNTL[0], sizeof(mmIRQ_BRIDGE_CNTL)/sizeof(mmIRQ_BRIDGE_CNTL[0]), 0, 0 }, - { "mmSLOT_CAP", REG_MMIO, 0x001b, 0, &mmSLOT_CAP[0], sizeof(mmSLOT_CAP)/sizeof(mmSLOT_CAP[0]), 0, 0 }, - { "mmSLOT_CNTL", REG_MMIO, 0x001c, 0, &mmSLOT_CNTL[0], sizeof(mmSLOT_CNTL)/sizeof(mmSLOT_CNTL[0]), 0, 0 }, - { "mmSLOT_STATUS", REG_MMIO, 0x001c, 0, &mmSLOT_STATUS[0], sizeof(mmSLOT_STATUS)/sizeof(mmSLOT_STATUS[0]), 0, 0 }, - { "mmSSID_CAP_LIST", REG_MMIO, 0x0030, 0, &mmSSID_CAP_LIST[0], sizeof(mmSSID_CAP_LIST)/sizeof(mmSSID_CAP_LIST[0]), 0, 0 }, - { "mmSSID_CAP", REG_MMIO, 0x0031, 0, &mmSSID_CAP[0], sizeof(mmSSID_CAP)/sizeof(mmSSID_CAP[0]), 0, 0 }, - { "ixSHADOW_COMMAND", REG_SMC, 0x0004, 0, &ixSHADOW_COMMAND[0], sizeof(ixSHADOW_COMMAND)/sizeof(ixSHADOW_COMMAND[0]), 0, 0 }, - { "ixSHADOW_BASE_ADDR_1", REG_SMC, 0x0010, 0, &ixSHADOW_BASE_ADDR_1[0], sizeof(ixSHADOW_BASE_ADDR_1)/sizeof(ixSHADOW_BASE_ADDR_1[0]), 0, 0 }, - { "ixSHADOW_BASE_ADDR_2", REG_SMC, 0x0014, 0, &ixSHADOW_BASE_ADDR_2[0], sizeof(ixSHADOW_BASE_ADDR_2)/sizeof(ixSHADOW_BASE_ADDR_2[0]), 0, 0 }, - { "ixSHADOW_SUB_BUS_NUMBER_LATENCY", REG_SMC, 0x0018, 0, &ixSHADOW_SUB_BUS_NUMBER_LATENCY[0], sizeof(ixSHADOW_SUB_BUS_NUMBER_LATENCY)/sizeof(ixSHADOW_SUB_BUS_NUMBER_LATENCY[0]), 0, 0 }, - { "ixSHADOW_IO_BASE_LIMIT", REG_SMC, 0x001c, 0, &ixSHADOW_IO_BASE_LIMIT[0], sizeof(ixSHADOW_IO_BASE_LIMIT)/sizeof(ixSHADOW_IO_BASE_LIMIT[0]), 0, 0 }, - { "ixSHADOW_MEM_BASE_LIMIT", REG_SMC, 0x0020, 0, &ixSHADOW_MEM_BASE_LIMIT[0], sizeof(ixSHADOW_MEM_BASE_LIMIT)/sizeof(ixSHADOW_MEM_BASE_LIMIT[0]), 0, 0 }, - { "ixSHADOW_PREF_BASE_LIMIT", REG_SMC, 0x0024, 0, &ixSHADOW_PREF_BASE_LIMIT[0], sizeof(ixSHADOW_PREF_BASE_LIMIT)/sizeof(ixSHADOW_PREF_BASE_LIMIT[0]), 0, 0 }, - { "ixSHADOW_PREF_BASE_UPPER", REG_SMC, 0x0028, 0, &ixSHADOW_PREF_BASE_UPPER[0], sizeof(ixSHADOW_PREF_BASE_UPPER)/sizeof(ixSHADOW_PREF_BASE_UPPER[0]), 0, 0 }, - { "ixSHADOW_PREF_LIMIT_UPPER", REG_SMC, 0x002c, 0, &ixSHADOW_PREF_LIMIT_UPPER[0], sizeof(ixSHADOW_PREF_LIMIT_UPPER)/sizeof(ixSHADOW_PREF_LIMIT_UPPER[0]), 0, 0 }, - { "ixSHADOW_IO_BASE_LIMIT_HI", REG_SMC, 0x0030, 0, &ixSHADOW_IO_BASE_LIMIT_HI[0], sizeof(ixSHADOW_IO_BASE_LIMIT_HI)/sizeof(ixSHADOW_IO_BASE_LIMIT_HI[0]), 0, 0 }, - { "ixSHADOW_IRQ_BRIDGE_CNTL", REG_SMC, 0x003e, 0, &ixSHADOW_IRQ_BRIDGE_CNTL[0], sizeof(ixSHADOW_IRQ_BRIDGE_CNTL)/sizeof(ixSHADOW_IRQ_BRIDGE_CNTL[0]), 0, 0 }, - { "ixSUC_INDEX", REG_SMC, 0x00e0, 0, &ixSUC_INDEX[0], sizeof(ixSUC_INDEX)/sizeof(ixSUC_INDEX[0]), 0, 0 }, - { "ixSUC_DATA", REG_SMC, 0x00e4, 0, &ixSUC_DATA[0], sizeof(ixSUC_DATA)/sizeof(ixSUC_DATA[0]), 0, 0 }, - { "ixSUM_INDEX", REG_SMC, 0x00e0, 0, &ixSUM_INDEX[0], sizeof(ixSUM_INDEX)/sizeof(ixSUM_INDEX[0]), 0, 0 }, - { "ixSUM_DATA", REG_SMC, 0x00e4, 0, &ixSUM_DATA[0], sizeof(ixSUM_DATA)/sizeof(ixSUM_DATA[0]), 0, 0 }, - { "mmA2S_CNTL_CL0", REG_MMIO, 0x4f0ab0, 3, &mmA2S_CNTL_CL0[0], sizeof(mmA2S_CNTL_CL0)/sizeof(mmA2S_CNTL_CL0[0]), 0, 0 }, - { "mmA2S_CNTL_CL1", REG_MMIO, 0x4f0ab1, 3, &mmA2S_CNTL_CL1[0], sizeof(mmA2S_CNTL_CL1)/sizeof(mmA2S_CNTL_CL1[0]), 0, 0 }, - { "mmA2S_CNTL_CL2", REG_MMIO, 0x4f0ab2, 3, &mmA2S_CNTL_CL2[0], sizeof(mmA2S_CNTL_CL2)/sizeof(mmA2S_CNTL_CL2[0]), 0, 0 }, - { "mmA2S_CNTL_CL3", REG_MMIO, 0x4f0ab3, 3, &mmA2S_CNTL_CL3[0], sizeof(mmA2S_CNTL_CL3)/sizeof(mmA2S_CNTL_CL3[0]), 0, 0 }, - { "mmA2S_CNTL_CL4", REG_MMIO, 0x4f0ab4, 3, &mmA2S_CNTL_CL4[0], sizeof(mmA2S_CNTL_CL4)/sizeof(mmA2S_CNTL_CL4[0]), 0, 0 }, - { "mmA2S_CNTL_SW0", REG_MMIO, 0x4f0ad0, 3, &mmA2S_CNTL_SW0[0], sizeof(mmA2S_CNTL_SW0)/sizeof(mmA2S_CNTL_SW0[0]), 0, 0 }, - { "mmA2S_CNTL_SW1", REG_MMIO, 0x4f0ad1, 3, &mmA2S_CNTL_SW1[0], sizeof(mmA2S_CNTL_SW1)/sizeof(mmA2S_CNTL_SW1[0]), 0, 0 }, - { "mmA2S_CNTL_SW2", REG_MMIO, 0x4f0ad2, 3, &mmA2S_CNTL_SW2[0], sizeof(mmA2S_CNTL_SW2)/sizeof(mmA2S_CNTL_SW2[0]), 0, 0 }, - { "mmNGDC_MGCG_CTRL", REG_MMIO, 0x4f0ae0, 3, &mmNGDC_MGCG_CTRL[0], sizeof(mmNGDC_MGCG_CTRL)/sizeof(mmNGDC_MGCG_CTRL[0]), 0, 0 }, - { "mmA2S_MISC_CNTL", REG_MMIO, 0x4f0ae1, 3, &mmA2S_MISC_CNTL[0], sizeof(mmA2S_MISC_CNTL)/sizeof(mmA2S_MISC_CNTL[0]), 0, 0 }, - { "mmNGDC_SDP_PORT_CTRL", REG_MMIO, 0x4f0ae2, 3, &mmNGDC_SDP_PORT_CTRL[0], sizeof(mmNGDC_SDP_PORT_CTRL)/sizeof(mmNGDC_SDP_PORT_CTRL[0]), 0, 0 }, - { "mmNGDC_RESERVED_0", REG_MMIO, 0x4f0aeb, 3, &mmNGDC_RESERVED_0[0], sizeof(mmNGDC_RESERVED_0)/sizeof(mmNGDC_RESERVED_0[0]), 0, 0 }, - { "mmNGDC_RESERVED_1", REG_MMIO, 0x4f0aec, 3, &mmNGDC_RESERVED_1[0], sizeof(mmNGDC_RESERVED_1)/sizeof(mmNGDC_RESERVED_1[0]), 0, 0 }, - { "mmBIF_SDMA0_DOORBELL_RANGE", REG_MMIO, 0x4f0af0, 3, &mmBIF_SDMA0_DOORBELL_RANGE[0], sizeof(mmBIF_SDMA0_DOORBELL_RANGE)/sizeof(mmBIF_SDMA0_DOORBELL_RANGE[0]), 0, 0 }, - { "mmBIF_SDMA1_DOORBELL_RANGE", REG_MMIO, 0x4f0af1, 3, &mmBIF_SDMA1_DOORBELL_RANGE[0], sizeof(mmBIF_SDMA1_DOORBELL_RANGE)/sizeof(mmBIF_SDMA1_DOORBELL_RANGE[0]), 0, 0 }, - { "mmBIF_IH_DOORBELL_RANGE", REG_MMIO, 0x4f0af2, 3, &mmBIF_IH_DOORBELL_RANGE[0], sizeof(mmBIF_IH_DOORBELL_RANGE)/sizeof(mmBIF_IH_DOORBELL_RANGE[0]), 0, 0 }, - { "mmBIF_MMSCH0_DOORBELL_RANGE", REG_MMIO, 0x4f0af3, 3, &mmBIF_MMSCH0_DOORBELL_RANGE[0], sizeof(mmBIF_MMSCH0_DOORBELL_RANGE)/sizeof(mmBIF_MMSCH0_DOORBELL_RANGE[0]), 0, 0 }, - { "mmBIF_DOORBELL_FENCE_CNTL", REG_MMIO, 0x4f0afe, 3, &mmBIF_DOORBELL_FENCE_CNTL[0], sizeof(mmBIF_DOORBELL_FENCE_CNTL)/sizeof(mmBIF_DOORBELL_FENCE_CNTL[0]), 0, 0 }, - { "mmS2A_MISC_CNTL", REG_MMIO, 0x4f0aff, 3, &mmS2A_MISC_CNTL[0], sizeof(mmS2A_MISC_CNTL)/sizeof(mmS2A_MISC_CNTL[0]), 0, 0 }, - { "mmA2S_CNTL2_SEC_CL0", REG_MMIO, 0x4f0b00, 3, &mmA2S_CNTL2_SEC_CL0[0], sizeof(mmA2S_CNTL2_SEC_CL0)/sizeof(mmA2S_CNTL2_SEC_CL0[0]), 0, 0 }, - { "mmA2S_CNTL2_SEC_CL1", REG_MMIO, 0x4f0b01, 3, &mmA2S_CNTL2_SEC_CL1[0], sizeof(mmA2S_CNTL2_SEC_CL1)/sizeof(mmA2S_CNTL2_SEC_CL1[0]), 0, 0 }, - { "mmA2S_CNTL2_SEC_CL2", REG_MMIO, 0x4f0b02, 3, &mmA2S_CNTL2_SEC_CL2[0], sizeof(mmA2S_CNTL2_SEC_CL2)/sizeof(mmA2S_CNTL2_SEC_CL2[0]), 0, 0 }, - { "mmA2S_CNTL2_SEC_CL3", REG_MMIO, 0x4f0b03, 3, &mmA2S_CNTL2_SEC_CL3[0], sizeof(mmA2S_CNTL2_SEC_CL3)/sizeof(mmA2S_CNTL2_SEC_CL3[0]), 0, 0 }, - { "mmA2S_CNTL2_SEC_CL4", REG_MMIO, 0x4f0b04, 3, &mmA2S_CNTL2_SEC_CL4[0], sizeof(mmA2S_CNTL2_SEC_CL4)/sizeof(mmA2S_CNTL2_SEC_CL4[0]), 0, 0 }, - { "ixSION_CL0_RdRsp_BurstTarget_REG0", REG_SMC, 0x1e000, 0, &ixSION_CL0_RdRsp_BurstTarget_REG0[0], sizeof(ixSION_CL0_RdRsp_BurstTarget_REG0)/sizeof(ixSION_CL0_RdRsp_BurstTarget_REG0[0]), 0, 0 }, - { "ixSION_CL0_RdRsp_BurstTarget_REG1", REG_SMC, 0x1e004, 0, &ixSION_CL0_RdRsp_BurstTarget_REG1[0], sizeof(ixSION_CL0_RdRsp_BurstTarget_REG1)/sizeof(ixSION_CL0_RdRsp_BurstTarget_REG1[0]), 0, 0 }, - { "ixSION_CL0_RdRsp_TimeSlot_REG0", REG_SMC, 0x1e008, 0, &ixSION_CL0_RdRsp_TimeSlot_REG0[0], sizeof(ixSION_CL0_RdRsp_TimeSlot_REG0)/sizeof(ixSION_CL0_RdRsp_TimeSlot_REG0[0]), 0, 0 }, - { "ixSION_CL0_RdRsp_TimeSlot_REG1", REG_SMC, 0x1e00c, 0, &ixSION_CL0_RdRsp_TimeSlot_REG1[0], sizeof(ixSION_CL0_RdRsp_TimeSlot_REG1)/sizeof(ixSION_CL0_RdRsp_TimeSlot_REG1[0]), 0, 0 }, - { "ixSION_CL0_WrRsp_BurstTarget_REG0", REG_SMC, 0x1e010, 0, &ixSION_CL0_WrRsp_BurstTarget_REG0[0], sizeof(ixSION_CL0_WrRsp_BurstTarget_REG0)/sizeof(ixSION_CL0_WrRsp_BurstTarget_REG0[0]), 0, 0 }, - { "ixSION_CL0_WrRsp_BurstTarget_REG1", REG_SMC, 0x1e014, 0, &ixSION_CL0_WrRsp_BurstTarget_REG1[0], sizeof(ixSION_CL0_WrRsp_BurstTarget_REG1)/sizeof(ixSION_CL0_WrRsp_BurstTarget_REG1[0]), 0, 0 }, - { "ixSION_CL0_WrRsp_TimeSlot_REG0", REG_SMC, 0x1e018, 0, &ixSION_CL0_WrRsp_TimeSlot_REG0[0], sizeof(ixSION_CL0_WrRsp_TimeSlot_REG0)/sizeof(ixSION_CL0_WrRsp_TimeSlot_REG0[0]), 0, 0 }, - { "ixSION_CL0_WrRsp_TimeSlot_REG1", REG_SMC, 0x1e01c, 0, &ixSION_CL0_WrRsp_TimeSlot_REG1[0], sizeof(ixSION_CL0_WrRsp_TimeSlot_REG1)/sizeof(ixSION_CL0_WrRsp_TimeSlot_REG1[0]), 0, 0 }, - { "ixSION_CL0_Req_BurstTarget_REG0", REG_SMC, 0x1e020, 0, &ixSION_CL0_Req_BurstTarget_REG0[0], sizeof(ixSION_CL0_Req_BurstTarget_REG0)/sizeof(ixSION_CL0_Req_BurstTarget_REG0[0]), 0, 0 }, - { "ixSION_CL0_Req_BurstTarget_REG1", REG_SMC, 0x1e024, 0, &ixSION_CL0_Req_BurstTarget_REG1[0], sizeof(ixSION_CL0_Req_BurstTarget_REG1)/sizeof(ixSION_CL0_Req_BurstTarget_REG1[0]), 0, 0 }, - { "ixSION_CL0_Req_TimeSlot_REG0", REG_SMC, 0x1e028, 0, &ixSION_CL0_Req_TimeSlot_REG0[0], sizeof(ixSION_CL0_Req_TimeSlot_REG0)/sizeof(ixSION_CL0_Req_TimeSlot_REG0[0]), 0, 0 }, - { "ixSION_CL0_Req_TimeSlot_REG1", REG_SMC, 0x1e02c, 0, &ixSION_CL0_Req_TimeSlot_REG1[0], sizeof(ixSION_CL0_Req_TimeSlot_REG1)/sizeof(ixSION_CL0_Req_TimeSlot_REG1[0]), 0, 0 }, - { "ixSION_CL0_ReqPoolCredit_Alloc_REG0", REG_SMC, 0x1e030, 0, &ixSION_CL0_ReqPoolCredit_Alloc_REG0[0], sizeof(ixSION_CL0_ReqPoolCredit_Alloc_REG0)/sizeof(ixSION_CL0_ReqPoolCredit_Alloc_REG0[0]), 0, 0 }, - { "ixSION_CL0_ReqPoolCredit_Alloc_REG1", REG_SMC, 0x1e034, 0, &ixSION_CL0_ReqPoolCredit_Alloc_REG1[0], sizeof(ixSION_CL0_ReqPoolCredit_Alloc_REG1)/sizeof(ixSION_CL0_ReqPoolCredit_Alloc_REG1[0]), 0, 0 }, - { "ixSION_CL0_DataPoolCredit_Alloc_REG0", REG_SMC, 0x1e038, 0, &ixSION_CL0_DataPoolCredit_Alloc_REG0[0], sizeof(ixSION_CL0_DataPoolCredit_Alloc_REG0)/sizeof(ixSION_CL0_DataPoolCredit_Alloc_REG0[0]), 0, 0 }, - { "ixSION_CL0_DataPoolCredit_Alloc_REG1", REG_SMC, 0x1e03c, 0, &ixSION_CL0_DataPoolCredit_Alloc_REG1[0], sizeof(ixSION_CL0_DataPoolCredit_Alloc_REG1)/sizeof(ixSION_CL0_DataPoolCredit_Alloc_REG1[0]), 0, 0 }, - { "ixSION_CL0_RdRspPoolCredit_Alloc_REG0", REG_SMC, 0x1e040, 0, &ixSION_CL0_RdRspPoolCredit_Alloc_REG0[0], sizeof(ixSION_CL0_RdRspPoolCredit_Alloc_REG0)/sizeof(ixSION_CL0_RdRspPoolCredit_Alloc_REG0[0]), 0, 0 }, - { "ixSION_CL0_RdRspPoolCredit_Alloc_REG1", REG_SMC, 0x1e044, 0, &ixSION_CL0_RdRspPoolCredit_Alloc_REG1[0], sizeof(ixSION_CL0_RdRspPoolCredit_Alloc_REG1)/sizeof(ixSION_CL0_RdRspPoolCredit_Alloc_REG1[0]), 0, 0 }, - { "ixSION_CL0_WrRspPoolCredit_Alloc_REG0", REG_SMC, 0x1e048, 0, &ixSION_CL0_WrRspPoolCredit_Alloc_REG0[0], sizeof(ixSION_CL0_WrRspPoolCredit_Alloc_REG0)/sizeof(ixSION_CL0_WrRspPoolCredit_Alloc_REG0[0]), 0, 0 }, - { "ixSION_CL0_WrRspPoolCredit_Alloc_REG1", REG_SMC, 0x1e04c, 0, &ixSION_CL0_WrRspPoolCredit_Alloc_REG1[0], sizeof(ixSION_CL0_WrRspPoolCredit_Alloc_REG1)/sizeof(ixSION_CL0_WrRspPoolCredit_Alloc_REG1[0]), 0, 0 }, - { "ixSION_CL1_RdRsp_BurstTarget_REG0", REG_SMC, 0x1e050, 0, &ixSION_CL1_RdRsp_BurstTarget_REG0[0], sizeof(ixSION_CL1_RdRsp_BurstTarget_REG0)/sizeof(ixSION_CL1_RdRsp_BurstTarget_REG0[0]), 0, 0 }, - { "ixSION_CL1_RdRsp_BurstTarget_REG1", REG_SMC, 0x1e054, 0, &ixSION_CL1_RdRsp_BurstTarget_REG1[0], sizeof(ixSION_CL1_RdRsp_BurstTarget_REG1)/sizeof(ixSION_CL1_RdRsp_BurstTarget_REG1[0]), 0, 0 }, - { "ixSION_CL1_RdRsp_TimeSlot_REG0", REG_SMC, 0x1e058, 0, &ixSION_CL1_RdRsp_TimeSlot_REG0[0], sizeof(ixSION_CL1_RdRsp_TimeSlot_REG0)/sizeof(ixSION_CL1_RdRsp_TimeSlot_REG0[0]), 0, 0 }, - { "ixSION_CL1_RdRsp_TimeSlot_REG1", REG_SMC, 0x1e05c, 0, &ixSION_CL1_RdRsp_TimeSlot_REG1[0], sizeof(ixSION_CL1_RdRsp_TimeSlot_REG1)/sizeof(ixSION_CL1_RdRsp_TimeSlot_REG1[0]), 0, 0 }, - { "ixSION_CL1_WrRsp_BurstTarget_REG0", REG_SMC, 0x1e060, 0, &ixSION_CL1_WrRsp_BurstTarget_REG0[0], sizeof(ixSION_CL1_WrRsp_BurstTarget_REG0)/sizeof(ixSION_CL1_WrRsp_BurstTarget_REG0[0]), 0, 0 }, - { "ixSION_CL1_WrRsp_BurstTarget_REG1", REG_SMC, 0x1e064, 0, &ixSION_CL1_WrRsp_BurstTarget_REG1[0], sizeof(ixSION_CL1_WrRsp_BurstTarget_REG1)/sizeof(ixSION_CL1_WrRsp_BurstTarget_REG1[0]), 0, 0 }, - { "ixSION_CL1_WrRsp_TimeSlot_REG0", REG_SMC, 0x1e068, 0, &ixSION_CL1_WrRsp_TimeSlot_REG0[0], sizeof(ixSION_CL1_WrRsp_TimeSlot_REG0)/sizeof(ixSION_CL1_WrRsp_TimeSlot_REG0[0]), 0, 0 }, - { "ixSION_CL1_WrRsp_TimeSlot_REG1", REG_SMC, 0x1e06c, 0, &ixSION_CL1_WrRsp_TimeSlot_REG1[0], sizeof(ixSION_CL1_WrRsp_TimeSlot_REG1)/sizeof(ixSION_CL1_WrRsp_TimeSlot_REG1[0]), 0, 0 }, - { "ixSION_CL1_Req_BurstTarget_REG0", REG_SMC, 0x1e070, 0, &ixSION_CL1_Req_BurstTarget_REG0[0], sizeof(ixSION_CL1_Req_BurstTarget_REG0)/sizeof(ixSION_CL1_Req_BurstTarget_REG0[0]), 0, 0 }, - { "ixSION_CL1_Req_BurstTarget_REG1", REG_SMC, 0x1e074, 0, &ixSION_CL1_Req_BurstTarget_REG1[0], sizeof(ixSION_CL1_Req_BurstTarget_REG1)/sizeof(ixSION_CL1_Req_BurstTarget_REG1[0]), 0, 0 }, - { "ixSION_CL1_Req_TimeSlot_REG0", REG_SMC, 0x1e078, 0, &ixSION_CL1_Req_TimeSlot_REG0[0], sizeof(ixSION_CL1_Req_TimeSlot_REG0)/sizeof(ixSION_CL1_Req_TimeSlot_REG0[0]), 0, 0 }, - { "ixSION_CL1_Req_TimeSlot_REG1", REG_SMC, 0x1e07c, 0, &ixSION_CL1_Req_TimeSlot_REG1[0], sizeof(ixSION_CL1_Req_TimeSlot_REG1)/sizeof(ixSION_CL1_Req_TimeSlot_REG1[0]), 0, 0 }, - { "ixSION_CL1_ReqPoolCredit_Alloc_REG0", REG_SMC, 0x1e080, 0, &ixSION_CL1_ReqPoolCredit_Alloc_REG0[0], sizeof(ixSION_CL1_ReqPoolCredit_Alloc_REG0)/sizeof(ixSION_CL1_ReqPoolCredit_Alloc_REG0[0]), 0, 0 }, - { "ixSION_CL1_ReqPoolCredit_Alloc_REG1", REG_SMC, 0x1e084, 0, &ixSION_CL1_ReqPoolCredit_Alloc_REG1[0], sizeof(ixSION_CL1_ReqPoolCredit_Alloc_REG1)/sizeof(ixSION_CL1_ReqPoolCredit_Alloc_REG1[0]), 0, 0 }, - { "ixSION_CL1_DataPoolCredit_Alloc_REG0", REG_SMC, 0x1e088, 0, &ixSION_CL1_DataPoolCredit_Alloc_REG0[0], sizeof(ixSION_CL1_DataPoolCredit_Alloc_REG0)/sizeof(ixSION_CL1_DataPoolCredit_Alloc_REG0[0]), 0, 0 }, - { "ixSION_CL1_DataPoolCredit_Alloc_REG1", REG_SMC, 0x1e08c, 0, &ixSION_CL1_DataPoolCredit_Alloc_REG1[0], sizeof(ixSION_CL1_DataPoolCredit_Alloc_REG1)/sizeof(ixSION_CL1_DataPoolCredit_Alloc_REG1[0]), 0, 0 }, - { "ixSION_CL1_RdRspPoolCredit_Alloc_REG0", REG_SMC, 0x1e090, 0, &ixSION_CL1_RdRspPoolCredit_Alloc_REG0[0], sizeof(ixSION_CL1_RdRspPoolCredit_Alloc_REG0)/sizeof(ixSION_CL1_RdRspPoolCredit_Alloc_REG0[0]), 0, 0 }, - { "ixSION_CL1_RdRspPoolCredit_Alloc_REG1", REG_SMC, 0x1e094, 0, &ixSION_CL1_RdRspPoolCredit_Alloc_REG1[0], sizeof(ixSION_CL1_RdRspPoolCredit_Alloc_REG1)/sizeof(ixSION_CL1_RdRspPoolCredit_Alloc_REG1[0]), 0, 0 }, - { "ixSION_CL1_WrRspPoolCredit_Alloc_REG0", REG_SMC, 0x1e098, 0, &ixSION_CL1_WrRspPoolCredit_Alloc_REG0[0], sizeof(ixSION_CL1_WrRspPoolCredit_Alloc_REG0)/sizeof(ixSION_CL1_WrRspPoolCredit_Alloc_REG0[0]), 0, 0 }, - { "ixSION_CL1_WrRspPoolCredit_Alloc_REG1", REG_SMC, 0x1e09c, 0, &ixSION_CL1_WrRspPoolCredit_Alloc_REG1[0], sizeof(ixSION_CL1_WrRspPoolCredit_Alloc_REG1)/sizeof(ixSION_CL1_WrRspPoolCredit_Alloc_REG1[0]), 0, 0 }, - { "ixSION_CL2_RdRsp_BurstTarget_REG0", REG_SMC, 0x1e0a0, 0, &ixSION_CL2_RdRsp_BurstTarget_REG0[0], sizeof(ixSION_CL2_RdRsp_BurstTarget_REG0)/sizeof(ixSION_CL2_RdRsp_BurstTarget_REG0[0]), 0, 0 }, - { "ixSION_CL2_RdRsp_BurstTarget_REG1", REG_SMC, 0x1e0a4, 0, &ixSION_CL2_RdRsp_BurstTarget_REG1[0], sizeof(ixSION_CL2_RdRsp_BurstTarget_REG1)/sizeof(ixSION_CL2_RdRsp_BurstTarget_REG1[0]), 0, 0 }, - { "ixSION_CL2_RdRsp_TimeSlot_REG0", REG_SMC, 0x1e0a8, 0, &ixSION_CL2_RdRsp_TimeSlot_REG0[0], sizeof(ixSION_CL2_RdRsp_TimeSlot_REG0)/sizeof(ixSION_CL2_RdRsp_TimeSlot_REG0[0]), 0, 0 }, - { "ixSION_CL2_RdRsp_TimeSlot_REG1", REG_SMC, 0x1e0ac, 0, &ixSION_CL2_RdRsp_TimeSlot_REG1[0], sizeof(ixSION_CL2_RdRsp_TimeSlot_REG1)/sizeof(ixSION_CL2_RdRsp_TimeSlot_REG1[0]), 0, 0 }, - { "ixSION_CL2_WrRsp_BurstTarget_REG0", REG_SMC, 0x1e0b0, 0, &ixSION_CL2_WrRsp_BurstTarget_REG0[0], sizeof(ixSION_CL2_WrRsp_BurstTarget_REG0)/sizeof(ixSION_CL2_WrRsp_BurstTarget_REG0[0]), 0, 0 }, - { "ixSION_CL2_WrRsp_BurstTarget_REG1", REG_SMC, 0x1e0b4, 0, &ixSION_CL2_WrRsp_BurstTarget_REG1[0], sizeof(ixSION_CL2_WrRsp_BurstTarget_REG1)/sizeof(ixSION_CL2_WrRsp_BurstTarget_REG1[0]), 0, 0 }, - { "ixSION_CL2_WrRsp_TimeSlot_REG0", REG_SMC, 0x1e0b8, 0, &ixSION_CL2_WrRsp_TimeSlot_REG0[0], sizeof(ixSION_CL2_WrRsp_TimeSlot_REG0)/sizeof(ixSION_CL2_WrRsp_TimeSlot_REG0[0]), 0, 0 }, - { "ixSION_CL2_WrRsp_TimeSlot_REG1", REG_SMC, 0x1e0bc, 0, &ixSION_CL2_WrRsp_TimeSlot_REG1[0], sizeof(ixSION_CL2_WrRsp_TimeSlot_REG1)/sizeof(ixSION_CL2_WrRsp_TimeSlot_REG1[0]), 0, 0 }, - { "ixSION_CL2_Req_BurstTarget_REG0", REG_SMC, 0x1e0c0, 0, &ixSION_CL2_Req_BurstTarget_REG0[0], sizeof(ixSION_CL2_Req_BurstTarget_REG0)/sizeof(ixSION_CL2_Req_BurstTarget_REG0[0]), 0, 0 }, - { "ixSION_CL2_Req_BurstTarget_REG1", REG_SMC, 0x1e0c4, 0, &ixSION_CL2_Req_BurstTarget_REG1[0], sizeof(ixSION_CL2_Req_BurstTarget_REG1)/sizeof(ixSION_CL2_Req_BurstTarget_REG1[0]), 0, 0 }, - { "ixSION_CL2_Req_TimeSlot_REG0", REG_SMC, 0x1e0c8, 0, &ixSION_CL2_Req_TimeSlot_REG0[0], sizeof(ixSION_CL2_Req_TimeSlot_REG0)/sizeof(ixSION_CL2_Req_TimeSlot_REG0[0]), 0, 0 }, - { "ixSION_CL2_Req_TimeSlot_REG1", REG_SMC, 0x1e0cc, 0, &ixSION_CL2_Req_TimeSlot_REG1[0], sizeof(ixSION_CL2_Req_TimeSlot_REG1)/sizeof(ixSION_CL2_Req_TimeSlot_REG1[0]), 0, 0 }, - { "ixSION_CL2_ReqPoolCredit_Alloc_REG0", REG_SMC, 0x1e0d0, 0, &ixSION_CL2_ReqPoolCredit_Alloc_REG0[0], sizeof(ixSION_CL2_ReqPoolCredit_Alloc_REG0)/sizeof(ixSION_CL2_ReqPoolCredit_Alloc_REG0[0]), 0, 0 }, - { "ixSION_CL2_ReqPoolCredit_Alloc_REG1", REG_SMC, 0x1e0d4, 0, &ixSION_CL2_ReqPoolCredit_Alloc_REG1[0], sizeof(ixSION_CL2_ReqPoolCredit_Alloc_REG1)/sizeof(ixSION_CL2_ReqPoolCredit_Alloc_REG1[0]), 0, 0 }, - { "ixSION_CL2_DataPoolCredit_Alloc_REG0", REG_SMC, 0x1e0d8, 0, &ixSION_CL2_DataPoolCredit_Alloc_REG0[0], sizeof(ixSION_CL2_DataPoolCredit_Alloc_REG0)/sizeof(ixSION_CL2_DataPoolCredit_Alloc_REG0[0]), 0, 0 }, - { "ixSION_CL2_DataPoolCredit_Alloc_REG1", REG_SMC, 0x1e0dc, 0, &ixSION_CL2_DataPoolCredit_Alloc_REG1[0], sizeof(ixSION_CL2_DataPoolCredit_Alloc_REG1)/sizeof(ixSION_CL2_DataPoolCredit_Alloc_REG1[0]), 0, 0 }, - { "ixSION_CL2_RdRspPoolCredit_Alloc_REG0", REG_SMC, 0x1e0e0, 0, &ixSION_CL2_RdRspPoolCredit_Alloc_REG0[0], sizeof(ixSION_CL2_RdRspPoolCredit_Alloc_REG0)/sizeof(ixSION_CL2_RdRspPoolCredit_Alloc_REG0[0]), 0, 0 }, - { "ixSION_CL2_RdRspPoolCredit_Alloc_REG1", REG_SMC, 0x1e0e4, 0, &ixSION_CL2_RdRspPoolCredit_Alloc_REG1[0], sizeof(ixSION_CL2_RdRspPoolCredit_Alloc_REG1)/sizeof(ixSION_CL2_RdRspPoolCredit_Alloc_REG1[0]), 0, 0 }, - { "ixSION_CL2_WrRspPoolCredit_Alloc_REG0", REG_SMC, 0x1e0e8, 0, &ixSION_CL2_WrRspPoolCredit_Alloc_REG0[0], sizeof(ixSION_CL2_WrRspPoolCredit_Alloc_REG0)/sizeof(ixSION_CL2_WrRspPoolCredit_Alloc_REG0[0]), 0, 0 }, - { "ixSION_CL2_WrRspPoolCredit_Alloc_REG1", REG_SMC, 0x1e0ec, 0, &ixSION_CL2_WrRspPoolCredit_Alloc_REG1[0], sizeof(ixSION_CL2_WrRspPoolCredit_Alloc_REG1)/sizeof(ixSION_CL2_WrRspPoolCredit_Alloc_REG1[0]), 0, 0 }, - { "ixSION_CL3_RdRsp_BurstTarget_REG0", REG_SMC, 0x1e0f0, 0, &ixSION_CL3_RdRsp_BurstTarget_REG0[0], sizeof(ixSION_CL3_RdRsp_BurstTarget_REG0)/sizeof(ixSION_CL3_RdRsp_BurstTarget_REG0[0]), 0, 0 }, - { "ixSION_CL3_RdRsp_BurstTarget_REG1", REG_SMC, 0x1e0f4, 0, &ixSION_CL3_RdRsp_BurstTarget_REG1[0], sizeof(ixSION_CL3_RdRsp_BurstTarget_REG1)/sizeof(ixSION_CL3_RdRsp_BurstTarget_REG1[0]), 0, 0 }, - { "ixSION_CL3_RdRsp_TimeSlot_REG0", REG_SMC, 0x1e0f8, 0, &ixSION_CL3_RdRsp_TimeSlot_REG0[0], sizeof(ixSION_CL3_RdRsp_TimeSlot_REG0)/sizeof(ixSION_CL3_RdRsp_TimeSlot_REG0[0]), 0, 0 }, - { "ixSION_CL3_RdRsp_TimeSlot_REG1", REG_SMC, 0x1e0fc, 0, &ixSION_CL3_RdRsp_TimeSlot_REG1[0], sizeof(ixSION_CL3_RdRsp_TimeSlot_REG1)/sizeof(ixSION_CL3_RdRsp_TimeSlot_REG1[0]), 0, 0 }, - { "ixSION_CL3_WrRsp_BurstTarget_REG0", REG_SMC, 0x1e100, 0, &ixSION_CL3_WrRsp_BurstTarget_REG0[0], sizeof(ixSION_CL3_WrRsp_BurstTarget_REG0)/sizeof(ixSION_CL3_WrRsp_BurstTarget_REG0[0]), 0, 0 }, - { "ixSION_CL3_WrRsp_BurstTarget_REG1", REG_SMC, 0x1e104, 0, &ixSION_CL3_WrRsp_BurstTarget_REG1[0], sizeof(ixSION_CL3_WrRsp_BurstTarget_REG1)/sizeof(ixSION_CL3_WrRsp_BurstTarget_REG1[0]), 0, 0 }, - { "ixSION_CL3_WrRsp_TimeSlot_REG0", REG_SMC, 0x1e108, 0, &ixSION_CL3_WrRsp_TimeSlot_REG0[0], sizeof(ixSION_CL3_WrRsp_TimeSlot_REG0)/sizeof(ixSION_CL3_WrRsp_TimeSlot_REG0[0]), 0, 0 }, - { "ixSION_CL3_WrRsp_TimeSlot_REG1", REG_SMC, 0x1e10c, 0, &ixSION_CL3_WrRsp_TimeSlot_REG1[0], sizeof(ixSION_CL3_WrRsp_TimeSlot_REG1)/sizeof(ixSION_CL3_WrRsp_TimeSlot_REG1[0]), 0, 0 }, - { "ixSION_CL3_Req_BurstTarget_REG0", REG_SMC, 0x1e110, 0, &ixSION_CL3_Req_BurstTarget_REG0[0], sizeof(ixSION_CL3_Req_BurstTarget_REG0)/sizeof(ixSION_CL3_Req_BurstTarget_REG0[0]), 0, 0 }, - { "ixSION_CL3_Req_BurstTarget_REG1", REG_SMC, 0x1e114, 0, &ixSION_CL3_Req_BurstTarget_REG1[0], sizeof(ixSION_CL3_Req_BurstTarget_REG1)/sizeof(ixSION_CL3_Req_BurstTarget_REG1[0]), 0, 0 }, - { "ixSION_CL3_Req_TimeSlot_REG0", REG_SMC, 0x1e118, 0, &ixSION_CL3_Req_TimeSlot_REG0[0], sizeof(ixSION_CL3_Req_TimeSlot_REG0)/sizeof(ixSION_CL3_Req_TimeSlot_REG0[0]), 0, 0 }, - { "ixSION_CL3_Req_TimeSlot_REG1", REG_SMC, 0x1e11c, 0, &ixSION_CL3_Req_TimeSlot_REG1[0], sizeof(ixSION_CL3_Req_TimeSlot_REG1)/sizeof(ixSION_CL3_Req_TimeSlot_REG1[0]), 0, 0 }, - { "ixSION_CL3_ReqPoolCredit_Alloc_REG0", REG_SMC, 0x1e120, 0, &ixSION_CL3_ReqPoolCredit_Alloc_REG0[0], sizeof(ixSION_CL3_ReqPoolCredit_Alloc_REG0)/sizeof(ixSION_CL3_ReqPoolCredit_Alloc_REG0[0]), 0, 0 }, - { "ixSION_CL3_ReqPoolCredit_Alloc_REG1", REG_SMC, 0x1e124, 0, &ixSION_CL3_ReqPoolCredit_Alloc_REG1[0], sizeof(ixSION_CL3_ReqPoolCredit_Alloc_REG1)/sizeof(ixSION_CL3_ReqPoolCredit_Alloc_REG1[0]), 0, 0 }, - { "ixSION_CL3_DataPoolCredit_Alloc_REG0", REG_SMC, 0x1e128, 0, &ixSION_CL3_DataPoolCredit_Alloc_REG0[0], sizeof(ixSION_CL3_DataPoolCredit_Alloc_REG0)/sizeof(ixSION_CL3_DataPoolCredit_Alloc_REG0[0]), 0, 0 }, - { "ixSION_CL3_DataPoolCredit_Alloc_REG1", REG_SMC, 0x1e12c, 0, &ixSION_CL3_DataPoolCredit_Alloc_REG1[0], sizeof(ixSION_CL3_DataPoolCredit_Alloc_REG1)/sizeof(ixSION_CL3_DataPoolCredit_Alloc_REG1[0]), 0, 0 }, - { "ixSION_CL3_RdRspPoolCredit_Alloc_REG0", REG_SMC, 0x1e130, 0, &ixSION_CL3_RdRspPoolCredit_Alloc_REG0[0], sizeof(ixSION_CL3_RdRspPoolCredit_Alloc_REG0)/sizeof(ixSION_CL3_RdRspPoolCredit_Alloc_REG0[0]), 0, 0 }, - { "ixSION_CL3_RdRspPoolCredit_Alloc_REG1", REG_SMC, 0x1e134, 0, &ixSION_CL3_RdRspPoolCredit_Alloc_REG1[0], sizeof(ixSION_CL3_RdRspPoolCredit_Alloc_REG1)/sizeof(ixSION_CL3_RdRspPoolCredit_Alloc_REG1[0]), 0, 0 }, - { "ixSION_CL3_WrRspPoolCredit_Alloc_REG0", REG_SMC, 0x1e138, 0, &ixSION_CL3_WrRspPoolCredit_Alloc_REG0[0], sizeof(ixSION_CL3_WrRspPoolCredit_Alloc_REG0)/sizeof(ixSION_CL3_WrRspPoolCredit_Alloc_REG0[0]), 0, 0 }, - { "ixSION_CL3_WrRspPoolCredit_Alloc_REG1", REG_SMC, 0x1e13c, 0, &ixSION_CL3_WrRspPoolCredit_Alloc_REG1[0], sizeof(ixSION_CL3_WrRspPoolCredit_Alloc_REG1)/sizeof(ixSION_CL3_WrRspPoolCredit_Alloc_REG1[0]), 0, 0 }, - { "ixSION_CL4_RdRsp_BurstTarget_REG0", REG_SMC, 0x1e140, 0, &ixSION_CL4_RdRsp_BurstTarget_REG0[0], sizeof(ixSION_CL4_RdRsp_BurstTarget_REG0)/sizeof(ixSION_CL4_RdRsp_BurstTarget_REG0[0]), 0, 0 }, - { "ixSION_CL4_RdRsp_BurstTarget_REG1", REG_SMC, 0x1e144, 0, &ixSION_CL4_RdRsp_BurstTarget_REG1[0], sizeof(ixSION_CL4_RdRsp_BurstTarget_REG1)/sizeof(ixSION_CL4_RdRsp_BurstTarget_REG1[0]), 0, 0 }, - { "ixSION_CL4_RdRsp_TimeSlot_REG0", REG_SMC, 0x1e148, 0, &ixSION_CL4_RdRsp_TimeSlot_REG0[0], sizeof(ixSION_CL4_RdRsp_TimeSlot_REG0)/sizeof(ixSION_CL4_RdRsp_TimeSlot_REG0[0]), 0, 0 }, - { "ixSION_CL4_RdRsp_TimeSlot_REG1", REG_SMC, 0x1e14c, 0, &ixSION_CL4_RdRsp_TimeSlot_REG1[0], sizeof(ixSION_CL4_RdRsp_TimeSlot_REG1)/sizeof(ixSION_CL4_RdRsp_TimeSlot_REG1[0]), 0, 0 }, - { "ixSION_CL4_WrRsp_BurstTarget_REG0", REG_SMC, 0x1e150, 0, &ixSION_CL4_WrRsp_BurstTarget_REG0[0], sizeof(ixSION_CL4_WrRsp_BurstTarget_REG0)/sizeof(ixSION_CL4_WrRsp_BurstTarget_REG0[0]), 0, 0 }, - { "ixSION_CL4_WrRsp_BurstTarget_REG1", REG_SMC, 0x1e154, 0, &ixSION_CL4_WrRsp_BurstTarget_REG1[0], sizeof(ixSION_CL4_WrRsp_BurstTarget_REG1)/sizeof(ixSION_CL4_WrRsp_BurstTarget_REG1[0]), 0, 0 }, - { "ixSION_CL4_WrRsp_TimeSlot_REG0", REG_SMC, 0x1e158, 0, &ixSION_CL4_WrRsp_TimeSlot_REG0[0], sizeof(ixSION_CL4_WrRsp_TimeSlot_REG0)/sizeof(ixSION_CL4_WrRsp_TimeSlot_REG0[0]), 0, 0 }, - { "ixSION_CL4_WrRsp_TimeSlot_REG1", REG_SMC, 0x1e15c, 0, &ixSION_CL4_WrRsp_TimeSlot_REG1[0], sizeof(ixSION_CL4_WrRsp_TimeSlot_REG1)/sizeof(ixSION_CL4_WrRsp_TimeSlot_REG1[0]), 0, 0 }, - { "ixSION_CL4_Req_BurstTarget_REG0", REG_SMC, 0x1e160, 0, &ixSION_CL4_Req_BurstTarget_REG0[0], sizeof(ixSION_CL4_Req_BurstTarget_REG0)/sizeof(ixSION_CL4_Req_BurstTarget_REG0[0]), 0, 0 }, - { "ixSION_CL4_Req_BurstTarget_REG1", REG_SMC, 0x1e164, 0, &ixSION_CL4_Req_BurstTarget_REG1[0], sizeof(ixSION_CL4_Req_BurstTarget_REG1)/sizeof(ixSION_CL4_Req_BurstTarget_REG1[0]), 0, 0 }, - { "ixSION_CL4_Req_TimeSlot_REG0", REG_SMC, 0x1e168, 0, &ixSION_CL4_Req_TimeSlot_REG0[0], sizeof(ixSION_CL4_Req_TimeSlot_REG0)/sizeof(ixSION_CL4_Req_TimeSlot_REG0[0]), 0, 0 }, - { "ixSION_CL4_Req_TimeSlot_REG1", REG_SMC, 0x1e16c, 0, &ixSION_CL4_Req_TimeSlot_REG1[0], sizeof(ixSION_CL4_Req_TimeSlot_REG1)/sizeof(ixSION_CL4_Req_TimeSlot_REG1[0]), 0, 0 }, - { "ixSION_CL4_ReqPoolCredit_Alloc_REG0", REG_SMC, 0x1e170, 0, &ixSION_CL4_ReqPoolCredit_Alloc_REG0[0], sizeof(ixSION_CL4_ReqPoolCredit_Alloc_REG0)/sizeof(ixSION_CL4_ReqPoolCredit_Alloc_REG0[0]), 0, 0 }, - { "ixSION_CL4_ReqPoolCredit_Alloc_REG1", REG_SMC, 0x1e174, 0, &ixSION_CL4_ReqPoolCredit_Alloc_REG1[0], sizeof(ixSION_CL4_ReqPoolCredit_Alloc_REG1)/sizeof(ixSION_CL4_ReqPoolCredit_Alloc_REG1[0]), 0, 0 }, - { "ixSION_CL4_DataPoolCredit_Alloc_REG0", REG_SMC, 0x1e178, 0, &ixSION_CL4_DataPoolCredit_Alloc_REG0[0], sizeof(ixSION_CL4_DataPoolCredit_Alloc_REG0)/sizeof(ixSION_CL4_DataPoolCredit_Alloc_REG0[0]), 0, 0 }, - { "ixSION_CL4_DataPoolCredit_Alloc_REG1", REG_SMC, 0x1e17c, 0, &ixSION_CL4_DataPoolCredit_Alloc_REG1[0], sizeof(ixSION_CL4_DataPoolCredit_Alloc_REG1)/sizeof(ixSION_CL4_DataPoolCredit_Alloc_REG1[0]), 0, 0 }, - { "ixSION_CL4_RdRspPoolCredit_Alloc_REG0", REG_SMC, 0x1e180, 0, &ixSION_CL4_RdRspPoolCredit_Alloc_REG0[0], sizeof(ixSION_CL4_RdRspPoolCredit_Alloc_REG0)/sizeof(ixSION_CL4_RdRspPoolCredit_Alloc_REG0[0]), 0, 0 }, - { "ixSION_CL4_RdRspPoolCredit_Alloc_REG1", REG_SMC, 0x1e184, 0, &ixSION_CL4_RdRspPoolCredit_Alloc_REG1[0], sizeof(ixSION_CL4_RdRspPoolCredit_Alloc_REG1)/sizeof(ixSION_CL4_RdRspPoolCredit_Alloc_REG1[0]), 0, 0 }, - { "ixSION_CL4_WrRspPoolCredit_Alloc_REG0", REG_SMC, 0x1e188, 0, &ixSION_CL4_WrRspPoolCredit_Alloc_REG0[0], sizeof(ixSION_CL4_WrRspPoolCredit_Alloc_REG0)/sizeof(ixSION_CL4_WrRspPoolCredit_Alloc_REG0[0]), 0, 0 }, - { "ixSION_CL4_WrRspPoolCredit_Alloc_REG1", REG_SMC, 0x1e18c, 0, &ixSION_CL4_WrRspPoolCredit_Alloc_REG1[0], sizeof(ixSION_CL4_WrRspPoolCredit_Alloc_REG1)/sizeof(ixSION_CL4_WrRspPoolCredit_Alloc_REG1[0]), 0, 0 }, - { "ixSION_CL5_RdRsp_BurstTarget_REG0", REG_SMC, 0x1e190, 0, &ixSION_CL5_RdRsp_BurstTarget_REG0[0], sizeof(ixSION_CL5_RdRsp_BurstTarget_REG0)/sizeof(ixSION_CL5_RdRsp_BurstTarget_REG0[0]), 0, 0 }, - { "ixSION_CL5_RdRsp_BurstTarget_REG1", REG_SMC, 0x1e194, 0, &ixSION_CL5_RdRsp_BurstTarget_REG1[0], sizeof(ixSION_CL5_RdRsp_BurstTarget_REG1)/sizeof(ixSION_CL5_RdRsp_BurstTarget_REG1[0]), 0, 0 }, - { "ixSION_CL5_RdRsp_TimeSlot_REG0", REG_SMC, 0x1e198, 0, &ixSION_CL5_RdRsp_TimeSlot_REG0[0], sizeof(ixSION_CL5_RdRsp_TimeSlot_REG0)/sizeof(ixSION_CL5_RdRsp_TimeSlot_REG0[0]), 0, 0 }, - { "ixSION_CL5_RdRsp_TimeSlot_REG1", REG_SMC, 0x1e19c, 0, &ixSION_CL5_RdRsp_TimeSlot_REG1[0], sizeof(ixSION_CL5_RdRsp_TimeSlot_REG1)/sizeof(ixSION_CL5_RdRsp_TimeSlot_REG1[0]), 0, 0 }, - { "ixSION_CL5_WrRsp_BurstTarget_REG0", REG_SMC, 0x1e1a0, 0, &ixSION_CL5_WrRsp_BurstTarget_REG0[0], sizeof(ixSION_CL5_WrRsp_BurstTarget_REG0)/sizeof(ixSION_CL5_WrRsp_BurstTarget_REG0[0]), 0, 0 }, - { "ixSION_CL5_WrRsp_BurstTarget_REG1", REG_SMC, 0x1e1a4, 0, &ixSION_CL5_WrRsp_BurstTarget_REG1[0], sizeof(ixSION_CL5_WrRsp_BurstTarget_REG1)/sizeof(ixSION_CL5_WrRsp_BurstTarget_REG1[0]), 0, 0 }, - { "ixSION_CL5_WrRsp_TimeSlot_REG0", REG_SMC, 0x1e1a8, 0, &ixSION_CL5_WrRsp_TimeSlot_REG0[0], sizeof(ixSION_CL5_WrRsp_TimeSlot_REG0)/sizeof(ixSION_CL5_WrRsp_TimeSlot_REG0[0]), 0, 0 }, - { "ixSION_CL5_WrRsp_TimeSlot_REG1", REG_SMC, 0x1e1ac, 0, &ixSION_CL5_WrRsp_TimeSlot_REG1[0], sizeof(ixSION_CL5_WrRsp_TimeSlot_REG1)/sizeof(ixSION_CL5_WrRsp_TimeSlot_REG1[0]), 0, 0 }, - { "ixSION_CL5_Req_BurstTarget_REG0", REG_SMC, 0x1e1b0, 0, &ixSION_CL5_Req_BurstTarget_REG0[0], sizeof(ixSION_CL5_Req_BurstTarget_REG0)/sizeof(ixSION_CL5_Req_BurstTarget_REG0[0]), 0, 0 }, - { "ixSION_CL5_Req_BurstTarget_REG1", REG_SMC, 0x1e1b4, 0, &ixSION_CL5_Req_BurstTarget_REG1[0], sizeof(ixSION_CL5_Req_BurstTarget_REG1)/sizeof(ixSION_CL5_Req_BurstTarget_REG1[0]), 0, 0 }, - { "ixSION_CL5_Req_TimeSlot_REG0", REG_SMC, 0x1e1b8, 0, &ixSION_CL5_Req_TimeSlot_REG0[0], sizeof(ixSION_CL5_Req_TimeSlot_REG0)/sizeof(ixSION_CL5_Req_TimeSlot_REG0[0]), 0, 0 }, - { "ixSION_CL5_Req_TimeSlot_REG1", REG_SMC, 0x1e1bc, 0, &ixSION_CL5_Req_TimeSlot_REG1[0], sizeof(ixSION_CL5_Req_TimeSlot_REG1)/sizeof(ixSION_CL5_Req_TimeSlot_REG1[0]), 0, 0 }, - { "ixSION_CL5_ReqPoolCredit_Alloc_REG0", REG_SMC, 0x1e1c0, 0, &ixSION_CL5_ReqPoolCredit_Alloc_REG0[0], sizeof(ixSION_CL5_ReqPoolCredit_Alloc_REG0)/sizeof(ixSION_CL5_ReqPoolCredit_Alloc_REG0[0]), 0, 0 }, - { "ixSION_CL5_ReqPoolCredit_Alloc_REG1", REG_SMC, 0x1e1c4, 0, &ixSION_CL5_ReqPoolCredit_Alloc_REG1[0], sizeof(ixSION_CL5_ReqPoolCredit_Alloc_REG1)/sizeof(ixSION_CL5_ReqPoolCredit_Alloc_REG1[0]), 0, 0 }, - { "ixSION_CL5_DataPoolCredit_Alloc_REG0", REG_SMC, 0x1e1c8, 0, &ixSION_CL5_DataPoolCredit_Alloc_REG0[0], sizeof(ixSION_CL5_DataPoolCredit_Alloc_REG0)/sizeof(ixSION_CL5_DataPoolCredit_Alloc_REG0[0]), 0, 0 }, - { "ixSION_CL5_DataPoolCredit_Alloc_REG1", REG_SMC, 0x1e1cc, 0, &ixSION_CL5_DataPoolCredit_Alloc_REG1[0], sizeof(ixSION_CL5_DataPoolCredit_Alloc_REG1)/sizeof(ixSION_CL5_DataPoolCredit_Alloc_REG1[0]), 0, 0 }, - { "ixSION_CL5_RdRspPoolCredit_Alloc_REG0", REG_SMC, 0x1e1d0, 0, &ixSION_CL5_RdRspPoolCredit_Alloc_REG0[0], sizeof(ixSION_CL5_RdRspPoolCredit_Alloc_REG0)/sizeof(ixSION_CL5_RdRspPoolCredit_Alloc_REG0[0]), 0, 0 }, - { "ixSION_CL5_RdRspPoolCredit_Alloc_REG1", REG_SMC, 0x1e1d4, 0, &ixSION_CL5_RdRspPoolCredit_Alloc_REG1[0], sizeof(ixSION_CL5_RdRspPoolCredit_Alloc_REG1)/sizeof(ixSION_CL5_RdRspPoolCredit_Alloc_REG1[0]), 0, 0 }, - { "ixSION_CL5_WrRspPoolCredit_Alloc_REG0", REG_SMC, 0x1e1d8, 0, &ixSION_CL5_WrRspPoolCredit_Alloc_REG0[0], sizeof(ixSION_CL5_WrRspPoolCredit_Alloc_REG0)/sizeof(ixSION_CL5_WrRspPoolCredit_Alloc_REG0[0]), 0, 0 }, - { "ixSION_CL5_WrRspPoolCredit_Alloc_REG1", REG_SMC, 0x1e1dc, 0, &ixSION_CL5_WrRspPoolCredit_Alloc_REG1[0], sizeof(ixSION_CL5_WrRspPoolCredit_Alloc_REG1)/sizeof(ixSION_CL5_WrRspPoolCredit_Alloc_REG1[0]), 0, 0 }, - { "ixSION_CNTL_REG0", REG_SMC, 0x1e1e0, 0, &ixSION_CNTL_REG0[0], sizeof(ixSION_CNTL_REG0)/sizeof(ixSION_CNTL_REG0[0]), 0, 0 }, - { "ixSION_CNTL_REG1", REG_SMC, 0x1e1e4, 0, &ixSION_CNTL_REG1[0], sizeof(ixSION_CNTL_REG1)/sizeof(ixSION_CNTL_REG1[0]), 0, 0 }, - { "ixSYSHUB_DS_CTRL_SOCCLK", REG_SMC, 0x10000, 0, &ixSYSHUB_DS_CTRL_SOCCLK[0], sizeof(ixSYSHUB_DS_CTRL_SOCCLK)/sizeof(ixSYSHUB_DS_CTRL_SOCCLK[0]), 0, 0 }, - { "ixSYSHUB_DS_CTRL2_SOCCLK", REG_SMC, 0x10004, 0, &ixSYSHUB_DS_CTRL2_SOCCLK[0], sizeof(ixSYSHUB_DS_CTRL2_SOCCLK)/sizeof(ixSYSHUB_DS_CTRL2_SOCCLK[0]), 0, 0 }, - { "ixSYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK", REG_SMC, 0x10008, 0, &ixSYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK[0], sizeof(ixSYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK)/sizeof(ixSYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK[0]), 0, 0 }, - { "ixSYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK", REG_SMC, 0x1000c, 0, &ixSYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK[0], sizeof(ixSYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK)/sizeof(ixSYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK[0]), 0, 0 }, - { "ixDMA_CLK0_SW0_SYSHUB_QOS_CNTL", REG_SMC, 0x10010, 0, &ixDMA_CLK0_SW0_SYSHUB_QOS_CNTL[0], sizeof(ixDMA_CLK0_SW0_SYSHUB_QOS_CNTL)/sizeof(ixDMA_CLK0_SW0_SYSHUB_QOS_CNTL[0]), 0, 0 }, - { "ixDMA_CLK0_SW1_SYSHUB_QOS_CNTL", REG_SMC, 0x10014, 0, &ixDMA_CLK0_SW1_SYSHUB_QOS_CNTL[0], sizeof(ixDMA_CLK0_SW1_SYSHUB_QOS_CNTL)/sizeof(ixDMA_CLK0_SW1_SYSHUB_QOS_CNTL[0]), 0, 0 }, - { "ixDMA_CLK0_SW0_CL0_CNTL", REG_SMC, 0x10018, 0, &ixDMA_CLK0_SW0_CL0_CNTL[0], sizeof(ixDMA_CLK0_SW0_CL0_CNTL)/sizeof(ixDMA_CLK0_SW0_CL0_CNTL[0]), 0, 0 }, - { "ixDMA_CLK0_SW0_CL1_CNTL", REG_SMC, 0x1001c, 0, &ixDMA_CLK0_SW0_CL1_CNTL[0], sizeof(ixDMA_CLK0_SW0_CL1_CNTL)/sizeof(ixDMA_CLK0_SW0_CL1_CNTL[0]), 0, 0 }, - { "ixDMA_CLK0_SW0_CL2_CNTL", REG_SMC, 0x10020, 0, &ixDMA_CLK0_SW0_CL2_CNTL[0], sizeof(ixDMA_CLK0_SW0_CL2_CNTL)/sizeof(ixDMA_CLK0_SW0_CL2_CNTL[0]), 0, 0 }, - { "ixDMA_CLK0_SW0_CL3_CNTL", REG_SMC, 0x10024, 0, &ixDMA_CLK0_SW0_CL3_CNTL[0], sizeof(ixDMA_CLK0_SW0_CL3_CNTL)/sizeof(ixDMA_CLK0_SW0_CL3_CNTL[0]), 0, 0 }, - { "ixDMA_CLK0_SW0_CL4_CNTL", REG_SMC, 0x10028, 0, &ixDMA_CLK0_SW0_CL4_CNTL[0], sizeof(ixDMA_CLK0_SW0_CL4_CNTL)/sizeof(ixDMA_CLK0_SW0_CL4_CNTL[0]), 0, 0 }, - { "ixDMA_CLK0_SW0_CL5_CNTL", REG_SMC, 0x1002c, 0, &ixDMA_CLK0_SW0_CL5_CNTL[0], sizeof(ixDMA_CLK0_SW0_CL5_CNTL)/sizeof(ixDMA_CLK0_SW0_CL5_CNTL[0]), 0, 0 }, - { "ixDMA_CLK0_SW1_CL0_CNTL", REG_SMC, 0x10030, 0, &ixDMA_CLK0_SW1_CL0_CNTL[0], sizeof(ixDMA_CLK0_SW1_CL0_CNTL)/sizeof(ixDMA_CLK0_SW1_CL0_CNTL[0]), 0, 0 }, - { "ixDMA_CLK0_SW2_CL0_CNTL", REG_SMC, 0x10034, 0, &ixDMA_CLK0_SW2_CL0_CNTL[0], sizeof(ixDMA_CLK0_SW2_CL0_CNTL)/sizeof(ixDMA_CLK0_SW2_CL0_CNTL[0]), 0, 0 }, - { "ixSYSHUB_CG_CNTL", REG_SMC, 0x10300, 0, &ixSYSHUB_CG_CNTL[0], sizeof(ixSYSHUB_CG_CNTL)/sizeof(ixSYSHUB_CG_CNTL[0]), 0, 0 }, - { "ixSYSHUB_TRANS_IDLE", REG_SMC, 0x10308, 0, &ixSYSHUB_TRANS_IDLE[0], sizeof(ixSYSHUB_TRANS_IDLE)/sizeof(ixSYSHUB_TRANS_IDLE[0]), 0, 0 }, - { "ixSYSHUB_HP_TIMER", REG_SMC, 0x1030c, 0, &ixSYSHUB_HP_TIMER[0], sizeof(ixSYSHUB_HP_TIMER)/sizeof(ixSYSHUB_HP_TIMER[0]), 0, 0 }, - { "ixSYSHUB_SCRATCH", REG_SMC, 0x10f00, 0, &ixSYSHUB_SCRATCH[0], sizeof(ixSYSHUB_SCRATCH)/sizeof(ixSYSHUB_SCRATCH[0]), 0, 0 }, - { "ixSYSHUB_DS_CTRL_SHUBCLK", REG_SMC, 0x11000, 0, &ixSYSHUB_DS_CTRL_SHUBCLK[0], sizeof(ixSYSHUB_DS_CTRL_SHUBCLK)/sizeof(ixSYSHUB_DS_CTRL_SHUBCLK[0]), 0, 0 }, - { "ixSYSHUB_DS_CTRL2_SHUBCLK", REG_SMC, 0x11004, 0, &ixSYSHUB_DS_CTRL2_SHUBCLK[0], sizeof(ixSYSHUB_DS_CTRL2_SHUBCLK)/sizeof(ixSYSHUB_DS_CTRL2_SHUBCLK[0]), 0, 0 }, - { "ixSYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK", REG_SMC, 0x11008, 0, &ixSYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK[0], sizeof(ixSYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK)/sizeof(ixSYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK[0]), 0, 0 }, - { "ixSYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK", REG_SMC, 0x1100c, 0, &ixSYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK[0], sizeof(ixSYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK)/sizeof(ixSYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK[0]), 0, 0 }, - { "ixDMA_CLK1_SW0_SYSHUB_QOS_CNTL", REG_SMC, 0x11010, 0, &ixDMA_CLK1_SW0_SYSHUB_QOS_CNTL[0], sizeof(ixDMA_CLK1_SW0_SYSHUB_QOS_CNTL)/sizeof(ixDMA_CLK1_SW0_SYSHUB_QOS_CNTL[0]), 0, 0 }, - { "ixDMA_CLK1_SW1_SYSHUB_QOS_CNTL", REG_SMC, 0x11014, 0, &ixDMA_CLK1_SW1_SYSHUB_QOS_CNTL[0], sizeof(ixDMA_CLK1_SW1_SYSHUB_QOS_CNTL)/sizeof(ixDMA_CLK1_SW1_SYSHUB_QOS_CNTL[0]), 0, 0 }, - { "ixDMA_CLK1_SW0_CL0_CNTL", REG_SMC, 0x11018, 0, &ixDMA_CLK1_SW0_CL0_CNTL[0], sizeof(ixDMA_CLK1_SW0_CL0_CNTL)/sizeof(ixDMA_CLK1_SW0_CL0_CNTL[0]), 0, 0 }, - { "ixDMA_CLK1_SW0_CL1_CNTL", REG_SMC, 0x1101c, 0, &ixDMA_CLK1_SW0_CL1_CNTL[0], sizeof(ixDMA_CLK1_SW0_CL1_CNTL)/sizeof(ixDMA_CLK1_SW0_CL1_CNTL[0]), 0, 0 }, - { "ixDMA_CLK1_SW0_CL2_CNTL", REG_SMC, 0x11020, 0, &ixDMA_CLK1_SW0_CL2_CNTL[0], sizeof(ixDMA_CLK1_SW0_CL2_CNTL)/sizeof(ixDMA_CLK1_SW0_CL2_CNTL[0]), 0, 0 }, - { "ixDMA_CLK1_SW0_CL3_CNTL", REG_SMC, 0x11024, 0, &ixDMA_CLK1_SW0_CL3_CNTL[0], sizeof(ixDMA_CLK1_SW0_CL3_CNTL)/sizeof(ixDMA_CLK1_SW0_CL3_CNTL[0]), 0, 0 }, - { "ixDMA_CLK1_SW0_CL4_CNTL", REG_SMC, 0x11028, 0, &ixDMA_CLK1_SW0_CL4_CNTL[0], sizeof(ixDMA_CLK1_SW0_CL4_CNTL)/sizeof(ixDMA_CLK1_SW0_CL4_CNTL[0]), 0, 0 }, - { "ixDMA_CLK1_SW1_CL0_CNTL", REG_SMC, 0x1102c, 0, &ixDMA_CLK1_SW1_CL0_CNTL[0], sizeof(ixDMA_CLK1_SW1_CL0_CNTL)/sizeof(ixDMA_CLK1_SW1_CL0_CNTL[0]), 0, 0 }, - { "ixDMA_CLK1_SW1_CL1_CNTL", REG_SMC, 0x11030, 0, &ixDMA_CLK1_SW1_CL1_CNTL[0], sizeof(ixDMA_CLK1_SW1_CL1_CNTL)/sizeof(ixDMA_CLK1_SW1_CL1_CNTL[0]), 0, 0 }, - { "ixDMA_CLK1_SW1_CL2_CNTL", REG_SMC, 0x11034, 0, &ixDMA_CLK1_SW1_CL2_CNTL[0], sizeof(ixDMA_CLK1_SW1_CL2_CNTL)/sizeof(ixDMA_CLK1_SW1_CL2_CNTL[0]), 0, 0 }, - { "ixDMA_CLK1_SW1_CL3_CNTL", REG_SMC, 0x11038, 0, &ixDMA_CLK1_SW1_CL3_CNTL[0], sizeof(ixDMA_CLK1_SW1_CL3_CNTL)/sizeof(ixDMA_CLK1_SW1_CL3_CNTL[0]), 0, 0 }, - { "ixDMA_CLK1_SW1_CL4_CNTL", REG_SMC, 0x1103c, 0, &ixDMA_CLK1_SW1_CL4_CNTL[0], sizeof(ixDMA_CLK1_SW1_CL4_CNTL)/sizeof(ixDMA_CLK1_SW1_CL4_CNTL[0]), 0, 0 }, - { "ixGDC_RAS_LEAF0_CTRL", REG_SMC, 0x1f800, 0, &ixGDC_RAS_LEAF0_CTRL[0], sizeof(ixGDC_RAS_LEAF0_CTRL)/sizeof(ixGDC_RAS_LEAF0_CTRL[0]), 0, 0 }, - { "ixGDC_RAS_LEAF1_CTRL", REG_SMC, 0x1f804, 0, &ixGDC_RAS_LEAF1_CTRL[0], sizeof(ixGDC_RAS_LEAF1_CTRL)/sizeof(ixGDC_RAS_LEAF1_CTRL[0]), 0, 0 }, - { "ixGDC_RAS_LEAF2_CTRL", REG_SMC, 0x1f808, 0, &ixGDC_RAS_LEAF2_CTRL[0], sizeof(ixGDC_RAS_LEAF2_CTRL)/sizeof(ixGDC_RAS_LEAF2_CTRL[0]), 0, 0 }, - { "ixGDC_RAS_LEAF3_CTRL", REG_SMC, 0x1f80c, 0, &ixGDC_RAS_LEAF3_CTRL[0], sizeof(ixGDC_RAS_LEAF3_CTRL)/sizeof(ixGDC_RAS_LEAF3_CTRL[0]), 0, 0 }, - { "ixGDC_RAS_LEAF4_CTRL", REG_SMC, 0x1f810, 0, &ixGDC_RAS_LEAF4_CTRL[0], sizeof(ixGDC_RAS_LEAF4_CTRL)/sizeof(ixGDC_RAS_LEAF4_CTRL[0]), 0, 0 }, - { "ixGDC_RAS_LEAF5_CTRL", REG_SMC, 0x1f814, 0, &ixGDC_RAS_LEAF5_CTRL[0], sizeof(ixGDC_RAS_LEAF5_CTRL)/sizeof(ixGDC_RAS_LEAF5_CTRL[0]), 0, 0 }, - { "ixSHUB_PF_FLR_RST", REG_SMC, 0x1f000, 0, &ixSHUB_PF_FLR_RST[0], sizeof(ixSHUB_PF_FLR_RST)/sizeof(ixSHUB_PF_FLR_RST[0]), 0, 0 }, - { "ixSHUB_GFX_DRV_MODE1_RST", REG_SMC, 0x1f004, 0, &ixSHUB_GFX_DRV_MODE1_RST[0], sizeof(ixSHUB_GFX_DRV_MODE1_RST)/sizeof(ixSHUB_GFX_DRV_MODE1_RST[0]), 0, 0 }, - { "ixSHUB_LINK_RESET", REG_SMC, 0x1f008, 0, &ixSHUB_LINK_RESET[0], sizeof(ixSHUB_LINK_RESET)/sizeof(ixSHUB_LINK_RESET[0]), 0, 0 }, - { "ixSHUB_PF0_VF_FLR_RST", REG_SMC, 0x1f020, 0, &ixSHUB_PF0_VF_FLR_RST[0], sizeof(ixSHUB_PF0_VF_FLR_RST)/sizeof(ixSHUB_PF0_VF_FLR_RST[0]), 0, 0 }, - { "ixSHUB_HARD_RST_CTRL", REG_SMC, 0x1f040, 0, &ixSHUB_HARD_RST_CTRL[0], sizeof(ixSHUB_HARD_RST_CTRL)/sizeof(ixSHUB_HARD_RST_CTRL[0]), 0, 0 }, - { "ixSHUB_SOFT_RST_CTRL", REG_SMC, 0x1f044, 0, &ixSHUB_SOFT_RST_CTRL[0], sizeof(ixSHUB_SOFT_RST_CTRL)/sizeof(ixSHUB_SOFT_RST_CTRL[0]), 0, 0 }, - { "ixSHUB_SDP_PORT_RST", REG_SMC, 0x1f048, 0, &ixSHUB_SDP_PORT_RST[0], sizeof(ixSHUB_SDP_PORT_RST)/sizeof(ixSHUB_SDP_PORT_RST[0]), 0, 0 }, - { "mmSBIOS_SCRATCH_0", REG_MMIO, 0x0048, 0, &mmSBIOS_SCRATCH_0[0], sizeof(mmSBIOS_SCRATCH_0)/sizeof(mmSBIOS_SCRATCH_0[0]), 0, 0 }, - { "mmSBIOS_SCRATCH_1", REG_MMIO, 0x0049, 0, &mmSBIOS_SCRATCH_1[0], sizeof(mmSBIOS_SCRATCH_1)/sizeof(mmSBIOS_SCRATCH_1[0]), 0, 0 }, - { "mmSBIOS_SCRATCH_2", REG_MMIO, 0x004a, 0, &mmSBIOS_SCRATCH_2[0], sizeof(mmSBIOS_SCRATCH_2)/sizeof(mmSBIOS_SCRATCH_2[0]), 0, 0 }, - { "mmSBIOS_SCRATCH_3", REG_MMIO, 0x004b, 0, &mmSBIOS_SCRATCH_3[0], sizeof(mmSBIOS_SCRATCH_3)/sizeof(mmSBIOS_SCRATCH_3[0]), 0, 0 }, - { "mmBIOS_SCRATCH_0", REG_MMIO, 0x004c, 0, &mmBIOS_SCRATCH_0[0], sizeof(mmBIOS_SCRATCH_0)/sizeof(mmBIOS_SCRATCH_0[0]), 0, 0 }, - { "mmBIOS_SCRATCH_1", REG_MMIO, 0x004d, 0, &mmBIOS_SCRATCH_1[0], sizeof(mmBIOS_SCRATCH_1)/sizeof(mmBIOS_SCRATCH_1[0]), 0, 0 }, - { "mmBIOS_SCRATCH_2", REG_MMIO, 0x004e, 0, &mmBIOS_SCRATCH_2[0], sizeof(mmBIOS_SCRATCH_2)/sizeof(mmBIOS_SCRATCH_2[0]), 0, 0 }, - { "mmBIOS_SCRATCH_3", REG_MMIO, 0x004f, 0, &mmBIOS_SCRATCH_3[0], sizeof(mmBIOS_SCRATCH_3)/sizeof(mmBIOS_SCRATCH_3[0]), 0, 0 }, - { "mmBIOS_SCRATCH_4", REG_MMIO, 0x0050, 0, &mmBIOS_SCRATCH_4[0], sizeof(mmBIOS_SCRATCH_4)/sizeof(mmBIOS_SCRATCH_4[0]), 0, 0 }, - { "mmBIOS_SCRATCH_5", REG_MMIO, 0x0051, 0, &mmBIOS_SCRATCH_5[0], sizeof(mmBIOS_SCRATCH_5)/sizeof(mmBIOS_SCRATCH_5[0]), 0, 0 }, - { "mmBIOS_SCRATCH_6", REG_MMIO, 0x0052, 0, &mmBIOS_SCRATCH_6[0], sizeof(mmBIOS_SCRATCH_6)/sizeof(mmBIOS_SCRATCH_6[0]), 0, 0 }, - { "mmBIOS_SCRATCH_7", REG_MMIO, 0x0053, 0, &mmBIOS_SCRATCH_7[0], sizeof(mmBIOS_SCRATCH_7)/sizeof(mmBIOS_SCRATCH_7[0]), 0, 0 }, - { "mmBIOS_SCRATCH_8", REG_MMIO, 0x0054, 0, &mmBIOS_SCRATCH_8[0], sizeof(mmBIOS_SCRATCH_8)/sizeof(mmBIOS_SCRATCH_8[0]), 0, 0 }, - { "mmBIOS_SCRATCH_9", REG_MMIO, 0x0055, 0, &mmBIOS_SCRATCH_9[0], sizeof(mmBIOS_SCRATCH_9)/sizeof(mmBIOS_SCRATCH_9[0]), 0, 0 }, - { "mmBIOS_SCRATCH_10", REG_MMIO, 0x0056, 0, &mmBIOS_SCRATCH_10[0], sizeof(mmBIOS_SCRATCH_10)/sizeof(mmBIOS_SCRATCH_10[0]), 0, 0 }, - { "mmBIOS_SCRATCH_11", REG_MMIO, 0x0057, 0, &mmBIOS_SCRATCH_11[0], sizeof(mmBIOS_SCRATCH_11)/sizeof(mmBIOS_SCRATCH_11[0]), 0, 0 }, - { "mmBIOS_SCRATCH_12", REG_MMIO, 0x0058, 0, &mmBIOS_SCRATCH_12[0], sizeof(mmBIOS_SCRATCH_12)/sizeof(mmBIOS_SCRATCH_12[0]), 0, 0 }, - { "mmBIOS_SCRATCH_13", REG_MMIO, 0x0059, 0, &mmBIOS_SCRATCH_13[0], sizeof(mmBIOS_SCRATCH_13)/sizeof(mmBIOS_SCRATCH_13[0]), 0, 0 }, - { "mmBIOS_SCRATCH_14", REG_MMIO, 0x005a, 0, &mmBIOS_SCRATCH_14[0], sizeof(mmBIOS_SCRATCH_14)/sizeof(mmBIOS_SCRATCH_14[0]), 0, 0 }, - { "mmBIOS_SCRATCH_15", REG_MMIO, 0x005b, 0, &mmBIOS_SCRATCH_15[0], sizeof(mmBIOS_SCRATCH_15)/sizeof(mmBIOS_SCRATCH_15[0]), 0, 0 }, - { "mmBIF_RLC_INTR_CNTL", REG_MMIO, 0x0060, 0, &mmBIF_RLC_INTR_CNTL[0], sizeof(mmBIF_RLC_INTR_CNTL)/sizeof(mmBIF_RLC_INTR_CNTL[0]), 0, 0 }, - { "mmBIF_VCE_INTR_CNTL", REG_MMIO, 0x0061, 0, &mmBIF_VCE_INTR_CNTL[0], sizeof(mmBIF_VCE_INTR_CNTL)/sizeof(mmBIF_VCE_INTR_CNTL[0]), 0, 0 }, - { "mmBIF_UVD_INTR_CNTL", REG_MMIO, 0x0062, 0, &mmBIF_UVD_INTR_CNTL[0], sizeof(mmBIF_UVD_INTR_CNTL)/sizeof(mmBIF_UVD_INTR_CNTL[0]), 0, 0 }, - { "mmGFX_MMIOREG_CAM_ADDR0", REG_MMIO, 0x0080, 0, &mmGFX_MMIOREG_CAM_ADDR0[0], sizeof(mmGFX_MMIOREG_CAM_ADDR0)/sizeof(mmGFX_MMIOREG_CAM_ADDR0[0]), 0, 0 }, - { "mmGFX_MMIOREG_CAM_REMAP_ADDR0", REG_MMIO, 0x0081, 0, &mmGFX_MMIOREG_CAM_REMAP_ADDR0[0], sizeof(mmGFX_MMIOREG_CAM_REMAP_ADDR0)/sizeof(mmGFX_MMIOREG_CAM_REMAP_ADDR0[0]), 0, 0 }, - { "mmGFX_MMIOREG_CAM_ADDR1", REG_MMIO, 0x0082, 0, &mmGFX_MMIOREG_CAM_ADDR1[0], sizeof(mmGFX_MMIOREG_CAM_ADDR1)/sizeof(mmGFX_MMIOREG_CAM_ADDR1[0]), 0, 0 }, - { "mmGFX_MMIOREG_CAM_REMAP_ADDR1", REG_MMIO, 0x0083, 0, &mmGFX_MMIOREG_CAM_REMAP_ADDR1[0], sizeof(mmGFX_MMIOREG_CAM_REMAP_ADDR1)/sizeof(mmGFX_MMIOREG_CAM_REMAP_ADDR1[0]), 0, 0 }, - { "mmGFX_MMIOREG_CAM_ADDR2", REG_MMIO, 0x0084, 0, &mmGFX_MMIOREG_CAM_ADDR2[0], sizeof(mmGFX_MMIOREG_CAM_ADDR2)/sizeof(mmGFX_MMIOREG_CAM_ADDR2[0]), 0, 0 }, - { "mmGFX_MMIOREG_CAM_REMAP_ADDR2", REG_MMIO, 0x0085, 0, &mmGFX_MMIOREG_CAM_REMAP_ADDR2[0], sizeof(mmGFX_MMIOREG_CAM_REMAP_ADDR2)/sizeof(mmGFX_MMIOREG_CAM_REMAP_ADDR2[0]), 0, 0 }, - { "mmGFX_MMIOREG_CAM_ADDR3", REG_MMIO, 0x0086, 0, &mmGFX_MMIOREG_CAM_ADDR3[0], sizeof(mmGFX_MMIOREG_CAM_ADDR3)/sizeof(mmGFX_MMIOREG_CAM_ADDR3[0]), 0, 0 }, - { "mmGFX_MMIOREG_CAM_REMAP_ADDR3", REG_MMIO, 0x0087, 0, &mmGFX_MMIOREG_CAM_REMAP_ADDR3[0], sizeof(mmGFX_MMIOREG_CAM_REMAP_ADDR3)/sizeof(mmGFX_MMIOREG_CAM_REMAP_ADDR3[0]), 0, 0 }, - { "mmGFX_MMIOREG_CAM_ADDR4", REG_MMIO, 0x0088, 0, &mmGFX_MMIOREG_CAM_ADDR4[0], sizeof(mmGFX_MMIOREG_CAM_ADDR4)/sizeof(mmGFX_MMIOREG_CAM_ADDR4[0]), 0, 0 }, - { "mmGFX_MMIOREG_CAM_REMAP_ADDR4", REG_MMIO, 0x0089, 0, &mmGFX_MMIOREG_CAM_REMAP_ADDR4[0], sizeof(mmGFX_MMIOREG_CAM_REMAP_ADDR4)/sizeof(mmGFX_MMIOREG_CAM_REMAP_ADDR4[0]), 0, 0 }, - { "mmGFX_MMIOREG_CAM_ADDR5", REG_MMIO, 0x008a, 0, &mmGFX_MMIOREG_CAM_ADDR5[0], sizeof(mmGFX_MMIOREG_CAM_ADDR5)/sizeof(mmGFX_MMIOREG_CAM_ADDR5[0]), 0, 0 }, - { "mmGFX_MMIOREG_CAM_REMAP_ADDR5", REG_MMIO, 0x008b, 0, &mmGFX_MMIOREG_CAM_REMAP_ADDR5[0], sizeof(mmGFX_MMIOREG_CAM_REMAP_ADDR5)/sizeof(mmGFX_MMIOREG_CAM_REMAP_ADDR5[0]), 0, 0 }, - { "mmGFX_MMIOREG_CAM_ADDR6", REG_MMIO, 0x008c, 0, &mmGFX_MMIOREG_CAM_ADDR6[0], sizeof(mmGFX_MMIOREG_CAM_ADDR6)/sizeof(mmGFX_MMIOREG_CAM_ADDR6[0]), 0, 0 }, - { "mmGFX_MMIOREG_CAM_REMAP_ADDR6", REG_MMIO, 0x008d, 0, &mmGFX_MMIOREG_CAM_REMAP_ADDR6[0], sizeof(mmGFX_MMIOREG_CAM_REMAP_ADDR6)/sizeof(mmGFX_MMIOREG_CAM_REMAP_ADDR6[0]), 0, 0 }, - { "mmGFX_MMIOREG_CAM_ADDR7", REG_MMIO, 0x008e, 0, &mmGFX_MMIOREG_CAM_ADDR7[0], sizeof(mmGFX_MMIOREG_CAM_ADDR7)/sizeof(mmGFX_MMIOREG_CAM_ADDR7[0]), 0, 0 }, - { "mmGFX_MMIOREG_CAM_REMAP_ADDR7", REG_MMIO, 0x008f, 0, &mmGFX_MMIOREG_CAM_REMAP_ADDR7[0], sizeof(mmGFX_MMIOREG_CAM_REMAP_ADDR7)/sizeof(mmGFX_MMIOREG_CAM_REMAP_ADDR7[0]), 0, 0 }, - { "mmGFX_MMIOREG_CAM_CNTL", REG_MMIO, 0x0090, 0, &mmGFX_MMIOREG_CAM_CNTL[0], sizeof(mmGFX_MMIOREG_CAM_CNTL)/sizeof(mmGFX_MMIOREG_CAM_CNTL[0]), 0, 0 }, - { "mmGFX_MMIOREG_CAM_ZERO_CPL", REG_MMIO, 0x0091, 0, &mmGFX_MMIOREG_CAM_ZERO_CPL[0], sizeof(mmGFX_MMIOREG_CAM_ZERO_CPL)/sizeof(mmGFX_MMIOREG_CAM_ZERO_CPL[0]), 0, 0 }, - { "mmGFX_MMIOREG_CAM_ONE_CPL", REG_MMIO, 0x0092, 0, &mmGFX_MMIOREG_CAM_ONE_CPL[0], sizeof(mmGFX_MMIOREG_CAM_ONE_CPL)/sizeof(mmGFX_MMIOREG_CAM_ONE_CPL[0]), 0, 0 }, - { "mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL", REG_MMIO, 0x0093, 0, &mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL[0], sizeof(mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL)/sizeof(mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL[0]), 0, 0 }, - { "mmMM_INDEX", REG_MMIO, 0x0000, 0, &mmMM_INDEX[0], sizeof(mmMM_INDEX)/sizeof(mmMM_INDEX[0]), 0, 0 }, - { "mmMM_DATA", REG_MMIO, 0x0001, 0, &mmMM_DATA[0], sizeof(mmMM_DATA)/sizeof(mmMM_DATA[0]), 0, 0 }, - { "mmMM_INDEX_HI", REG_MMIO, 0x0006, 0, &mmMM_INDEX_HI[0], sizeof(mmMM_INDEX_HI)/sizeof(mmMM_INDEX_HI[0]), 0, 0 }, - { "mmSYSHUB_INDEX_OVLP", REG_MMIO, 0x0008, 0, &mmSYSHUB_INDEX_OVLP[0], sizeof(mmSYSHUB_INDEX_OVLP)/sizeof(mmSYSHUB_INDEX_OVLP[0]), 0, 0 }, - { "mmSYSHUB_DATA_OVLP", REG_MMIO, 0x0009, 0, &mmSYSHUB_DATA_OVLP[0], sizeof(mmSYSHUB_DATA_OVLP)/sizeof(mmSYSHUB_DATA_OVLP[0]), 0, 0 }, - { "mmPCIE_INDEX", REG_MMIO, 0x000c, 0, &mmPCIE_INDEX[0], sizeof(mmPCIE_INDEX)/sizeof(mmPCIE_INDEX[0]), 0, 0 }, - { "mmPCIE_DATA", REG_MMIO, 0x000d, 0, &mmPCIE_DATA[0], sizeof(mmPCIE_DATA)/sizeof(mmPCIE_DATA[0]), 0, 0 }, - { "mmPCIE_INDEX2", REG_MMIO, 0x000e, 0, &mmPCIE_INDEX2[0], sizeof(mmPCIE_INDEX2)/sizeof(mmPCIE_INDEX2[0]), 0, 0 }, - { "mmPCIE_DATA2", REG_MMIO, 0x000f, 0, &mmPCIE_DATA2[0], sizeof(mmPCIE_DATA2)/sizeof(mmPCIE_DATA2[0]), 0, 0 }, - { "mmDN_PCIE_RESERVED", REG_MMIO, 0x0d60, 0, &mmDN_PCIE_RESERVED[0], sizeof(mmDN_PCIE_RESERVED)/sizeof(mmDN_PCIE_RESERVED[0]), 0, 0 }, - { "mmDN_PCIE_SCRATCH", REG_MMIO, 0x0d61, 0, &mmDN_PCIE_SCRATCH[0], sizeof(mmDN_PCIE_SCRATCH)/sizeof(mmDN_PCIE_SCRATCH[0]), 0, 0 }, - { "mmDN_PCIE_CNTL", REG_MMIO, 0x0d63, 0, &mmDN_PCIE_CNTL[0], sizeof(mmDN_PCIE_CNTL)/sizeof(mmDN_PCIE_CNTL[0]), 0, 0 }, - { "mmDN_PCIE_CONFIG_CNTL", REG_MMIO, 0x0d64, 0, &mmDN_PCIE_CONFIG_CNTL[0], sizeof(mmDN_PCIE_CONFIG_CNTL)/sizeof(mmDN_PCIE_CONFIG_CNTL[0]), 0, 0 }, - { "mmDN_PCIE_RX_CNTL2", REG_MMIO, 0x0d65, 0, &mmDN_PCIE_RX_CNTL2[0], sizeof(mmDN_PCIE_RX_CNTL2)/sizeof(mmDN_PCIE_RX_CNTL2[0]), 0, 0 }, - { "mmDN_PCIE_BUS_CNTL", REG_MMIO, 0x0d66, 0, &mmDN_PCIE_BUS_CNTL[0], sizeof(mmDN_PCIE_BUS_CNTL)/sizeof(mmDN_PCIE_BUS_CNTL[0]), 0, 0 }, - { "mmDN_PCIE_CFG_CNTL", REG_MMIO, 0x0d67, 0, &mmDN_PCIE_CFG_CNTL[0], sizeof(mmDN_PCIE_CFG_CNTL)/sizeof(mmDN_PCIE_CFG_CNTL[0]), 0, 0 }, - { "mmDN_PCIE_STRAP_F0", REG_MMIO, 0x0d68, 0, &mmDN_PCIE_STRAP_F0[0], sizeof(mmDN_PCIE_STRAP_F0)/sizeof(mmDN_PCIE_STRAP_F0[0]), 0, 0 }, - { "mmDN_PCIE_STRAP_MISC", REG_MMIO, 0x0d69, 0, &mmDN_PCIE_STRAP_MISC[0], sizeof(mmDN_PCIE_STRAP_MISC)/sizeof(mmDN_PCIE_STRAP_MISC[0]), 0, 0 }, - { "mmDN_PCIE_STRAP_MISC2", REG_MMIO, 0x0d6a, 0, &mmDN_PCIE_STRAP_MISC2[0], sizeof(mmDN_PCIE_STRAP_MISC2)/sizeof(mmDN_PCIE_STRAP_MISC2[0]), 0, 0 }, - { "mmPCIEP_RESERVED", REG_MMIO, 0x0d6c, 0, &mmPCIEP_RESERVED[0], sizeof(mmPCIEP_RESERVED)/sizeof(mmPCIEP_RESERVED[0]), 0, 0 }, - { "mmPCIEP_SCRATCH", REG_MMIO, 0x0d6d, 0, &mmPCIEP_SCRATCH[0], sizeof(mmPCIEP_SCRATCH)/sizeof(mmPCIEP_SCRATCH[0]), 0, 0 }, - { "mmPCIE_ERR_CNTL", REG_MMIO, 0x0d6f, 0, &mmPCIE_ERR_CNTL[0], sizeof(mmPCIE_ERR_CNTL)/sizeof(mmPCIE_ERR_CNTL[0]), 0, 0 }, - { "mmPCIE_RX_CNTL", REG_MMIO, 0x0d70, 0, &mmPCIE_RX_CNTL[0], sizeof(mmPCIE_RX_CNTL)/sizeof(mmPCIE_RX_CNTL[0]), 0, 0 }, - { "mmPCIE_LC_SPEED_CNTL", REG_MMIO, 0x0d71, 0, &mmPCIE_LC_SPEED_CNTL[0], sizeof(mmPCIE_LC_SPEED_CNTL)/sizeof(mmPCIE_LC_SPEED_CNTL[0]), 0, 0 }, - { "mmPCIE_LC_CNTL2", REG_MMIO, 0x0d72, 0, &mmPCIE_LC_CNTL2[0], sizeof(mmPCIE_LC_CNTL2)/sizeof(mmPCIE_LC_CNTL2[0]), 0, 0 }, - { "mmPCIEP_STRAP_MISC", REG_MMIO, 0x0d73, 0, &mmPCIEP_STRAP_MISC[0], sizeof(mmPCIEP_STRAP_MISC)/sizeof(mmPCIEP_STRAP_MISC[0]), 0, 0 }, - { "mmLTR_MSG_INFO_FROM_EP", REG_MMIO, 0x0d74, 0, &mmLTR_MSG_INFO_FROM_EP[0], sizeof(mmLTR_MSG_INFO_FROM_EP)/sizeof(mmLTR_MSG_INFO_FROM_EP[0]), 0, 0 }, - { "mmEP_PCIE_SCRATCH", REG_MMIO, 0x0d43, 0, &mmEP_PCIE_SCRATCH[0], sizeof(mmEP_PCIE_SCRATCH)/sizeof(mmEP_PCIE_SCRATCH[0]), 0, 0 }, - { "mmEP_PCIE_CNTL", REG_MMIO, 0x0d45, 0, &mmEP_PCIE_CNTL[0], sizeof(mmEP_PCIE_CNTL)/sizeof(mmEP_PCIE_CNTL[0]), 0, 0 }, - { "mmEP_PCIE_INT_CNTL", REG_MMIO, 0x0d46, 0, &mmEP_PCIE_INT_CNTL[0], sizeof(mmEP_PCIE_INT_CNTL)/sizeof(mmEP_PCIE_INT_CNTL[0]), 0, 0 }, - { "mmEP_PCIE_INT_STATUS", REG_MMIO, 0x0d47, 0, &mmEP_PCIE_INT_STATUS[0], sizeof(mmEP_PCIE_INT_STATUS)/sizeof(mmEP_PCIE_INT_STATUS[0]), 0, 0 }, - { "mmEP_PCIE_RX_CNTL2", REG_MMIO, 0x0d48, 0, &mmEP_PCIE_RX_CNTL2[0], sizeof(mmEP_PCIE_RX_CNTL2)/sizeof(mmEP_PCIE_RX_CNTL2[0]), 0, 0 }, - { "mmEP_PCIE_BUS_CNTL", REG_MMIO, 0x0d49, 0, &mmEP_PCIE_BUS_CNTL[0], sizeof(mmEP_PCIE_BUS_CNTL)/sizeof(mmEP_PCIE_BUS_CNTL[0]), 0, 0 }, - { "mmEP_PCIE_CFG_CNTL", REG_MMIO, 0x0d4a, 0, &mmEP_PCIE_CFG_CNTL[0], sizeof(mmEP_PCIE_CFG_CNTL)/sizeof(mmEP_PCIE_CFG_CNTL[0]), 0, 0 }, - { "mmEP_PCIE_OBFF_CNTL", REG_MMIO, 0x0d4b, 0, &mmEP_PCIE_OBFF_CNTL[0], sizeof(mmEP_PCIE_OBFF_CNTL)/sizeof(mmEP_PCIE_OBFF_CNTL[0]), 0, 0 }, - { "mmEP_PCIE_TX_LTR_CNTL", REG_MMIO, 0x0d4c, 0, &mmEP_PCIE_TX_LTR_CNTL[0], sizeof(mmEP_PCIE_TX_LTR_CNTL)/sizeof(mmEP_PCIE_TX_LTR_CNTL[0]), 0, 0 }, - { "mmEP_PCIE_STRAP_MISC", REG_MMIO, 0x0d4f, 0, &mmEP_PCIE_STRAP_MISC[0], sizeof(mmEP_PCIE_STRAP_MISC)/sizeof(mmEP_PCIE_STRAP_MISC[0]), 0, 0 }, - { "mmEP_PCIE_STRAP_MISC2", REG_MMIO, 0x0d50, 0, &mmEP_PCIE_STRAP_MISC2[0], sizeof(mmEP_PCIE_STRAP_MISC2)/sizeof(mmEP_PCIE_STRAP_MISC2[0]), 0, 0 }, - { "mmEP_PCIE_STRAP_PI", REG_MMIO, 0x0d51, 0, NULL, 0, 0, 0 }, - { "mmEP_PCIE_F0_DPA_CAP", REG_MMIO, 0x0d52, 0, &mmEP_PCIE_F0_DPA_CAP[0], sizeof(mmEP_PCIE_F0_DPA_CAP)/sizeof(mmEP_PCIE_F0_DPA_CAP[0]), 0, 0 }, - { "mmEP_PCIE_F0_DPA_LATENCY_INDICATOR", REG_MMIO, 0x0d53, 0, &mmEP_PCIE_F0_DPA_LATENCY_INDICATOR[0], sizeof(mmEP_PCIE_F0_DPA_LATENCY_INDICATOR)/sizeof(mmEP_PCIE_F0_DPA_LATENCY_INDICATOR[0]), 0, 0 }, - { "mmEP_PCIE_F0_DPA_CNTL", REG_MMIO, 0x0d53, 0, &mmEP_PCIE_F0_DPA_CNTL[0], sizeof(mmEP_PCIE_F0_DPA_CNTL)/sizeof(mmEP_PCIE_F0_DPA_CNTL[0]), 0, 0 }, - { "mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0", REG_MMIO, 0x0d53, 0, &mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0[0], sizeof(mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0)/sizeof(mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0[0]), 0, 0 }, - { "mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1", REG_MMIO, 0x0d54, 0, &mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1[0], sizeof(mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1)/sizeof(mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1[0]), 0, 0 }, - { "mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2", REG_MMIO, 0x0d54, 0, &mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2[0], sizeof(mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2)/sizeof(mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2[0]), 0, 0 }, - { "mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3", REG_MMIO, 0x0d54, 0, &mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3[0], sizeof(mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3)/sizeof(mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3[0]), 0, 0 }, - { "mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4", REG_MMIO, 0x0d54, 0, &mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4[0], sizeof(mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4)/sizeof(mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4[0]), 0, 0 }, - { "mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5", REG_MMIO, 0x0d55, 0, &mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5[0], sizeof(mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5)/sizeof(mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5[0]), 0, 0 }, - { "mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6", REG_MMIO, 0x0d55, 0, &mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6[0], sizeof(mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6)/sizeof(mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6[0]), 0, 0 }, - { "mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7", REG_MMIO, 0x0d55, 0, &mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7[0], sizeof(mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7)/sizeof(mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7[0]), 0, 0 }, - { "mmEP_PCIE_PME_CONTROL", REG_MMIO, 0x0d55, 0, &mmEP_PCIE_PME_CONTROL[0], sizeof(mmEP_PCIE_PME_CONTROL)/sizeof(mmEP_PCIE_PME_CONTROL[0]), 0, 0 }, - { "mmEP_PCIEP_RESERVED", REG_MMIO, 0x0d56, 0, &mmEP_PCIEP_RESERVED[0], sizeof(mmEP_PCIEP_RESERVED)/sizeof(mmEP_PCIEP_RESERVED[0]), 0, 0 }, - { "mmEP_PCIE_TX_CNTL", REG_MMIO, 0x0d58, 0, &mmEP_PCIE_TX_CNTL[0], sizeof(mmEP_PCIE_TX_CNTL)/sizeof(mmEP_PCIE_TX_CNTL[0]), 0, 0 }, - { "mmEP_PCIE_TX_REQUESTER_ID", REG_MMIO, 0x0d59, 0, &mmEP_PCIE_TX_REQUESTER_ID[0], sizeof(mmEP_PCIE_TX_REQUESTER_ID)/sizeof(mmEP_PCIE_TX_REQUESTER_ID[0]), 0, 0 }, - { "mmEP_PCIE_ERR_CNTL", REG_MMIO, 0x0d5a, 0, &mmEP_PCIE_ERR_CNTL[0], sizeof(mmEP_PCIE_ERR_CNTL)/sizeof(mmEP_PCIE_ERR_CNTL[0]), 0, 0 }, - { "mmEP_PCIE_RX_CNTL", REG_MMIO, 0x0d5b, 0, &mmEP_PCIE_RX_CNTL[0], sizeof(mmEP_PCIE_RX_CNTL)/sizeof(mmEP_PCIE_RX_CNTL[0]), 0, 0 }, - { "mmEP_PCIE_LC_SPEED_CNTL", REG_MMIO, 0x0d5c, 0, &mmEP_PCIE_LC_SPEED_CNTL[0], sizeof(mmEP_PCIE_LC_SPEED_CNTL)/sizeof(mmEP_PCIE_LC_SPEED_CNTL[0]), 0, 0 }, - { "mmBIF_MM_INDACCESS_CNTL", REG_MMIO, 0x0e06, 0, &mmBIF_MM_INDACCESS_CNTL[0], sizeof(mmBIF_MM_INDACCESS_CNTL)/sizeof(mmBIF_MM_INDACCESS_CNTL[0]), 0, 0 }, - { "mmBUS_CNTL", REG_MMIO, 0x0e07, 0, &mmBUS_CNTL[0], sizeof(mmBUS_CNTL)/sizeof(mmBUS_CNTL[0]), 0, 0 }, - { "mmBIF_SCRATCH0", REG_MMIO, 0x0e08, 0, &mmBIF_SCRATCH0[0], sizeof(mmBIF_SCRATCH0)/sizeof(mmBIF_SCRATCH0[0]), 0, 0 }, - { "mmBIF_SCRATCH1", REG_MMIO, 0x0e09, 0, &mmBIF_SCRATCH1[0], sizeof(mmBIF_SCRATCH1)/sizeof(mmBIF_SCRATCH1[0]), 0, 0 }, - { "mmBX_RESET_EN", REG_MMIO, 0x0e0d, 0, &mmBX_RESET_EN[0], sizeof(mmBX_RESET_EN)/sizeof(mmBX_RESET_EN[0]), 0, 0 }, - { "mmMM_CFGREGS_CNTL", REG_MMIO, 0x0e0e, 0, &mmMM_CFGREGS_CNTL[0], sizeof(mmMM_CFGREGS_CNTL)/sizeof(mmMM_CFGREGS_CNTL[0]), 0, 0 }, - { "mmBX_RESET_CNTL", REG_MMIO, 0x0e10, 0, &mmBX_RESET_CNTL[0], sizeof(mmBX_RESET_CNTL)/sizeof(mmBX_RESET_CNTL[0]), 0, 0 }, - { "mmINTERRUPT_CNTL", REG_MMIO, 0x0e11, 0, &mmINTERRUPT_CNTL[0], sizeof(mmINTERRUPT_CNTL)/sizeof(mmINTERRUPT_CNTL[0]), 0, 0 }, - { "mmINTERRUPT_CNTL2", REG_MMIO, 0x0e12, 0, &mmINTERRUPT_CNTL2[0], sizeof(mmINTERRUPT_CNTL2)/sizeof(mmINTERRUPT_CNTL2[0]), 0, 0 }, - { "mmCLKREQB_PAD_CNTL", REG_MMIO, 0x0e18, 0, &mmCLKREQB_PAD_CNTL[0], sizeof(mmCLKREQB_PAD_CNTL)/sizeof(mmCLKREQB_PAD_CNTL[0]), 0, 0 }, - { "mmCLKREQB_PERF_COUNTER", REG_MMIO, 0x0e19, 0, &mmCLKREQB_PERF_COUNTER[0], sizeof(mmCLKREQB_PERF_COUNTER)/sizeof(mmCLKREQB_PERF_COUNTER[0]), 0, 0 }, - { "mmBIF_CLK_CTRL", REG_MMIO, 0x0e1a, 0, &mmBIF_CLK_CTRL[0], sizeof(mmBIF_CLK_CTRL)/sizeof(mmBIF_CLK_CTRL[0]), 0, 0 }, - { "mmBIF_FEATURES_CONTROL_MISC", REG_MMIO, 0x0e1b, 0, &mmBIF_FEATURES_CONTROL_MISC[0], sizeof(mmBIF_FEATURES_CONTROL_MISC)/sizeof(mmBIF_FEATURES_CONTROL_MISC[0]), 0, 0 }, - { "mmBIF_DOORBELL_CNTL", REG_MMIO, 0x0e1c, 0, &mmBIF_DOORBELL_CNTL[0], sizeof(mmBIF_DOORBELL_CNTL)/sizeof(mmBIF_DOORBELL_CNTL[0]), 0, 0 }, - { "mmBIF_DOORBELL_INT_CNTL", REG_MMIO, 0x0e1d, 0, &mmBIF_DOORBELL_INT_CNTL[0], sizeof(mmBIF_DOORBELL_INT_CNTL)/sizeof(mmBIF_DOORBELL_INT_CNTL[0]), 0, 0 }, - { "mmBIF_SLVARB_MODE", REG_MMIO, 0x0e1e, 0, &mmBIF_SLVARB_MODE[0], sizeof(mmBIF_SLVARB_MODE)/sizeof(mmBIF_SLVARB_MODE[0]), 0, 0 }, - { "mmBIF_FB_EN", REG_MMIO, 0x0e1f, 0, &mmBIF_FB_EN[0], sizeof(mmBIF_FB_EN)/sizeof(mmBIF_FB_EN[0]), 0, 0 }, - { "mmBIF_BUSY_DELAY_CNTR", REG_MMIO, 0x0e20, 0, &mmBIF_BUSY_DELAY_CNTR[0], sizeof(mmBIF_BUSY_DELAY_CNTR)/sizeof(mmBIF_BUSY_DELAY_CNTR[0]), 0, 0 }, - { "mmBIF_PERFMON_CNTL", REG_MMIO, 0x0e21, 0, &mmBIF_PERFMON_CNTL[0], sizeof(mmBIF_PERFMON_CNTL)/sizeof(mmBIF_PERFMON_CNTL[0]), 0, 0 }, - { "mmBIF_PERFCOUNTER0_RESULT", REG_MMIO, 0x0e22, 0, &mmBIF_PERFCOUNTER0_RESULT[0], sizeof(mmBIF_PERFCOUNTER0_RESULT)/sizeof(mmBIF_PERFCOUNTER0_RESULT[0]), 0, 0 }, - { "mmBIF_PERFCOUNTER1_RESULT", REG_MMIO, 0x0e23, 0, &mmBIF_PERFCOUNTER1_RESULT[0], sizeof(mmBIF_PERFCOUNTER1_RESULT)/sizeof(mmBIF_PERFCOUNTER1_RESULT[0]), 0, 0 }, - { "mmBIF_MST_TRANS_PENDING_VF", REG_MMIO, 0x0e29, 0, &mmBIF_MST_TRANS_PENDING_VF[0], sizeof(mmBIF_MST_TRANS_PENDING_VF)/sizeof(mmBIF_MST_TRANS_PENDING_VF[0]), 0, 0 }, - { "mmBIF_SLV_TRANS_PENDING_VF", REG_MMIO, 0x0e2a, 0, &mmBIF_SLV_TRANS_PENDING_VF[0], sizeof(mmBIF_SLV_TRANS_PENDING_VF)/sizeof(mmBIF_SLV_TRANS_PENDING_VF[0]), 0, 0 }, - { "mmBACO_CNTL", REG_MMIO, 0x0e2b, 0, &mmBACO_CNTL[0], sizeof(mmBACO_CNTL)/sizeof(mmBACO_CNTL[0]), 0, 0 }, - { "mmBIF_BACO_EXIT_TIME0", REG_MMIO, 0x0e2c, 0, &mmBIF_BACO_EXIT_TIME0[0], sizeof(mmBIF_BACO_EXIT_TIME0)/sizeof(mmBIF_BACO_EXIT_TIME0[0]), 0, 0 }, - { "mmBIF_BACO_EXIT_TIMER1", REG_MMIO, 0x0e2d, 0, &mmBIF_BACO_EXIT_TIMER1[0], sizeof(mmBIF_BACO_EXIT_TIMER1)/sizeof(mmBIF_BACO_EXIT_TIMER1[0]), 0, 0 }, - { "mmBIF_BACO_EXIT_TIMER2", REG_MMIO, 0x0e2e, 0, &mmBIF_BACO_EXIT_TIMER2[0], sizeof(mmBIF_BACO_EXIT_TIMER2)/sizeof(mmBIF_BACO_EXIT_TIMER2[0]), 0, 0 }, - { "mmBIF_BACO_EXIT_TIMER3", REG_MMIO, 0x0e2f, 0, &mmBIF_BACO_EXIT_TIMER3[0], sizeof(mmBIF_BACO_EXIT_TIMER3)/sizeof(mmBIF_BACO_EXIT_TIMER3[0]), 0, 0 }, - { "mmBIF_BACO_EXIT_TIMER4", REG_MMIO, 0x0e30, 0, &mmBIF_BACO_EXIT_TIMER4[0], sizeof(mmBIF_BACO_EXIT_TIMER4)/sizeof(mmBIF_BACO_EXIT_TIMER4[0]), 0, 0 }, - { "mmMEM_TYPE_CNTL", REG_MMIO, 0x0e31, 0, &mmMEM_TYPE_CNTL[0], sizeof(mmMEM_TYPE_CNTL)/sizeof(mmMEM_TYPE_CNTL[0]), 0, 0 }, - { "mmSMU_BIF_VDDGFX_PWR_STATUS", REG_MMIO, 0x0e33, 0, &mmSMU_BIF_VDDGFX_PWR_STATUS[0], sizeof(mmSMU_BIF_VDDGFX_PWR_STATUS)/sizeof(mmSMU_BIF_VDDGFX_PWR_STATUS[0]), 0, 0 }, - { "mmBIF_VDDGFX_GFX0_LOWER", REG_MMIO, 0x0e34, 0, &mmBIF_VDDGFX_GFX0_LOWER[0], sizeof(mmBIF_VDDGFX_GFX0_LOWER)/sizeof(mmBIF_VDDGFX_GFX0_LOWER[0]), 0, 0 }, - { "mmBIF_VDDGFX_GFX0_UPPER", REG_MMIO, 0x0e35, 0, &mmBIF_VDDGFX_GFX0_UPPER[0], sizeof(mmBIF_VDDGFX_GFX0_UPPER)/sizeof(mmBIF_VDDGFX_GFX0_UPPER[0]), 0, 0 }, - { "mmBIF_VDDGFX_GFX1_LOWER", REG_MMIO, 0x0e36, 0, &mmBIF_VDDGFX_GFX1_LOWER[0], sizeof(mmBIF_VDDGFX_GFX1_LOWER)/sizeof(mmBIF_VDDGFX_GFX1_LOWER[0]), 0, 0 }, - { "mmBIF_VDDGFX_GFX1_UPPER", REG_MMIO, 0x0e37, 0, &mmBIF_VDDGFX_GFX1_UPPER[0], sizeof(mmBIF_VDDGFX_GFX1_UPPER)/sizeof(mmBIF_VDDGFX_GFX1_UPPER[0]), 0, 0 }, - { "mmBIF_VDDGFX_GFX2_LOWER", REG_MMIO, 0x0e38, 0, &mmBIF_VDDGFX_GFX2_LOWER[0], sizeof(mmBIF_VDDGFX_GFX2_LOWER)/sizeof(mmBIF_VDDGFX_GFX2_LOWER[0]), 0, 0 }, - { "mmBIF_VDDGFX_GFX2_UPPER", REG_MMIO, 0x0e39, 0, &mmBIF_VDDGFX_GFX2_UPPER[0], sizeof(mmBIF_VDDGFX_GFX2_UPPER)/sizeof(mmBIF_VDDGFX_GFX2_UPPER[0]), 0, 0 }, - { "mmBIF_VDDGFX_GFX3_LOWER", REG_MMIO, 0x0e3a, 0, &mmBIF_VDDGFX_GFX3_LOWER[0], sizeof(mmBIF_VDDGFX_GFX3_LOWER)/sizeof(mmBIF_VDDGFX_GFX3_LOWER[0]), 0, 0 }, - { "mmBIF_VDDGFX_GFX3_UPPER", REG_MMIO, 0x0e3b, 0, &mmBIF_VDDGFX_GFX3_UPPER[0], sizeof(mmBIF_VDDGFX_GFX3_UPPER)/sizeof(mmBIF_VDDGFX_GFX3_UPPER[0]), 0, 0 }, - { "mmBIF_VDDGFX_GFX4_LOWER", REG_MMIO, 0x0e3c, 0, &mmBIF_VDDGFX_GFX4_LOWER[0], sizeof(mmBIF_VDDGFX_GFX4_LOWER)/sizeof(mmBIF_VDDGFX_GFX4_LOWER[0]), 0, 0 }, - { "mmBIF_VDDGFX_GFX4_UPPER", REG_MMIO, 0x0e3d, 0, &mmBIF_VDDGFX_GFX4_UPPER[0], sizeof(mmBIF_VDDGFX_GFX4_UPPER)/sizeof(mmBIF_VDDGFX_GFX4_UPPER[0]), 0, 0 }, - { "mmBIF_VDDGFX_GFX5_LOWER", REG_MMIO, 0x0e3e, 0, &mmBIF_VDDGFX_GFX5_LOWER[0], sizeof(mmBIF_VDDGFX_GFX5_LOWER)/sizeof(mmBIF_VDDGFX_GFX5_LOWER[0]), 0, 0 }, - { "mmBIF_VDDGFX_GFX5_UPPER", REG_MMIO, 0x0e3f, 0, &mmBIF_VDDGFX_GFX5_UPPER[0], sizeof(mmBIF_VDDGFX_GFX5_UPPER)/sizeof(mmBIF_VDDGFX_GFX5_UPPER[0]), 0, 0 }, - { "mmBIF_VDDGFX_RSV1_LOWER", REG_MMIO, 0x0e40, 0, &mmBIF_VDDGFX_RSV1_LOWER[0], sizeof(mmBIF_VDDGFX_RSV1_LOWER)/sizeof(mmBIF_VDDGFX_RSV1_LOWER[0]), 0, 0 }, - { "mmBIF_VDDGFX_RSV1_UPPER", REG_MMIO, 0x0e41, 0, &mmBIF_VDDGFX_RSV1_UPPER[0], sizeof(mmBIF_VDDGFX_RSV1_UPPER)/sizeof(mmBIF_VDDGFX_RSV1_UPPER[0]), 0, 0 }, - { "mmBIF_VDDGFX_RSV2_LOWER", REG_MMIO, 0x0e42, 0, &mmBIF_VDDGFX_RSV2_LOWER[0], sizeof(mmBIF_VDDGFX_RSV2_LOWER)/sizeof(mmBIF_VDDGFX_RSV2_LOWER[0]), 0, 0 }, - { "mmBIF_VDDGFX_RSV2_UPPER", REG_MMIO, 0x0e43, 0, &mmBIF_VDDGFX_RSV2_UPPER[0], sizeof(mmBIF_VDDGFX_RSV2_UPPER)/sizeof(mmBIF_VDDGFX_RSV2_UPPER[0]), 0, 0 }, - { "mmBIF_VDDGFX_RSV3_LOWER", REG_MMIO, 0x0e44, 0, &mmBIF_VDDGFX_RSV3_LOWER[0], sizeof(mmBIF_VDDGFX_RSV3_LOWER)/sizeof(mmBIF_VDDGFX_RSV3_LOWER[0]), 0, 0 }, - { "mmBIF_VDDGFX_RSV3_UPPER", REG_MMIO, 0x0e45, 0, &mmBIF_VDDGFX_RSV3_UPPER[0], sizeof(mmBIF_VDDGFX_RSV3_UPPER)/sizeof(mmBIF_VDDGFX_RSV3_UPPER[0]), 0, 0 }, - { "mmBIF_VDDGFX_RSV4_LOWER", REG_MMIO, 0x0e46, 0, &mmBIF_VDDGFX_RSV4_LOWER[0], sizeof(mmBIF_VDDGFX_RSV4_LOWER)/sizeof(mmBIF_VDDGFX_RSV4_LOWER[0]), 0, 0 }, - { "mmBIF_VDDGFX_RSV4_UPPER", REG_MMIO, 0x0e47, 0, &mmBIF_VDDGFX_RSV4_UPPER[0], sizeof(mmBIF_VDDGFX_RSV4_UPPER)/sizeof(mmBIF_VDDGFX_RSV4_UPPER[0]), 0, 0 }, - { "mmBIF_VDDGFX_FB_CMP", REG_MMIO, 0x0e48, 0, &mmBIF_VDDGFX_FB_CMP[0], sizeof(mmBIF_VDDGFX_FB_CMP)/sizeof(mmBIF_VDDGFX_FB_CMP[0]), 0, 0 }, - { "mmBIF_DOORBELL_GBLAPER1_LOWER", REG_MMIO, 0x0e49, 0, &mmBIF_DOORBELL_GBLAPER1_LOWER[0], sizeof(mmBIF_DOORBELL_GBLAPER1_LOWER)/sizeof(mmBIF_DOORBELL_GBLAPER1_LOWER[0]), 0, 0 }, - { "mmBIF_DOORBELL_GBLAPER1_UPPER", REG_MMIO, 0x0e4a, 0, &mmBIF_DOORBELL_GBLAPER1_UPPER[0], sizeof(mmBIF_DOORBELL_GBLAPER1_UPPER)/sizeof(mmBIF_DOORBELL_GBLAPER1_UPPER[0]), 0, 0 }, - { "mmBIF_DOORBELL_GBLAPER2_LOWER", REG_MMIO, 0x0e4b, 0, &mmBIF_DOORBELL_GBLAPER2_LOWER[0], sizeof(mmBIF_DOORBELL_GBLAPER2_LOWER)/sizeof(mmBIF_DOORBELL_GBLAPER2_LOWER[0]), 0, 0 }, - { "mmBIF_DOORBELL_GBLAPER2_UPPER", REG_MMIO, 0x0e4c, 0, &mmBIF_DOORBELL_GBLAPER2_UPPER[0], sizeof(mmBIF_DOORBELL_GBLAPER2_UPPER)/sizeof(mmBIF_DOORBELL_GBLAPER2_UPPER[0]), 0, 0 }, - { "mmREMAP_HDP_MEM_FLUSH_CNTL", REG_MMIO, 0x0e4d, 0, &mmREMAP_HDP_MEM_FLUSH_CNTL[0], sizeof(mmREMAP_HDP_MEM_FLUSH_CNTL)/sizeof(mmREMAP_HDP_MEM_FLUSH_CNTL[0]), 0, 0 }, - { "mmREMAP_HDP_REG_FLUSH_CNTL", REG_MMIO, 0x0e4e, 0, &mmREMAP_HDP_REG_FLUSH_CNTL[0], sizeof(mmREMAP_HDP_REG_FLUSH_CNTL)/sizeof(mmREMAP_HDP_REG_FLUSH_CNTL[0]), 0, 0 }, - { "mmBIF_RB_CNTL", REG_MMIO, 0x0e4f, 0, &mmBIF_RB_CNTL[0], sizeof(mmBIF_RB_CNTL)/sizeof(mmBIF_RB_CNTL[0]), 0, 0 }, - { "mmBIF_RB_BASE", REG_MMIO, 0x0e50, 0, &mmBIF_RB_BASE[0], sizeof(mmBIF_RB_BASE)/sizeof(mmBIF_RB_BASE[0]), 0, 0 }, - { "mmBIF_RB_RPTR", REG_MMIO, 0x0e51, 0, &mmBIF_RB_RPTR[0], sizeof(mmBIF_RB_RPTR)/sizeof(mmBIF_RB_RPTR[0]), 0, 0 }, - { "mmBIF_RB_WPTR", REG_MMIO, 0x0e52, 0, &mmBIF_RB_WPTR[0], sizeof(mmBIF_RB_WPTR)/sizeof(mmBIF_RB_WPTR[0]), 0, 0 }, - { "mmBIF_RB_WPTR_ADDR_HI", REG_MMIO, 0x0e53, 0, &mmBIF_RB_WPTR_ADDR_HI[0], sizeof(mmBIF_RB_WPTR_ADDR_HI)/sizeof(mmBIF_RB_WPTR_ADDR_HI[0]), 0, 0 }, - { "mmBIF_RB_WPTR_ADDR_LO", REG_MMIO, 0x0e54, 0, &mmBIF_RB_WPTR_ADDR_LO[0], sizeof(mmBIF_RB_WPTR_ADDR_LO)/sizeof(mmBIF_RB_WPTR_ADDR_LO[0]), 0, 0 }, - { "mmMAILBOX_INDEX", REG_MMIO, 0x0e55, 0, &mmMAILBOX_INDEX[0], sizeof(mmMAILBOX_INDEX)/sizeof(mmMAILBOX_INDEX[0]), 0, 0 }, - { "mmBIF_GPUIOV_RESET_NOTIFICATION", REG_MMIO, 0x0e62, 0, &mmBIF_GPUIOV_RESET_NOTIFICATION[0], sizeof(mmBIF_GPUIOV_RESET_NOTIFICATION)/sizeof(mmBIF_GPUIOV_RESET_NOTIFICATION[0]), 0, 0 }, - { "mmBIF_UVD_GPUIOV_CFG_SIZE", REG_MMIO, 0x0e63, 0, &mmBIF_UVD_GPUIOV_CFG_SIZE[0], sizeof(mmBIF_UVD_GPUIOV_CFG_SIZE)/sizeof(mmBIF_UVD_GPUIOV_CFG_SIZE[0]), 0, 0 }, - { "mmBIF_VCE_GPUIOV_CFG_SIZE", REG_MMIO, 0x0e64, 0, &mmBIF_VCE_GPUIOV_CFG_SIZE[0], sizeof(mmBIF_VCE_GPUIOV_CFG_SIZE)/sizeof(mmBIF_VCE_GPUIOV_CFG_SIZE[0]), 0, 0 }, - { "mmBIF_GFX_SDMA_GPUIOV_CFG_SIZE", REG_MMIO, 0x0e65, 0, &mmBIF_GFX_SDMA_GPUIOV_CFG_SIZE[0], sizeof(mmBIF_GFX_SDMA_GPUIOV_CFG_SIZE)/sizeof(mmBIF_GFX_SDMA_GPUIOV_CFG_SIZE[0]), 0, 0 }, - { "mmBIF_GMI_WRR_WEIGHT", REG_MMIO, 0x0e66, 0, &mmBIF_GMI_WRR_WEIGHT[0], sizeof(mmBIF_GMI_WRR_WEIGHT)/sizeof(mmBIF_GMI_WRR_WEIGHT[0]), 0, 0 }, - { "mmNBIF_STRAP_WRITE_CTRL", REG_MMIO, 0x0e67, 0, &mmNBIF_STRAP_WRITE_CTRL[0], sizeof(mmNBIF_STRAP_WRITE_CTRL)/sizeof(mmNBIF_STRAP_WRITE_CTRL[0]), 0, 0 }, - { "mmBIF_PERSTB_PAD_CNTL", REG_MMIO, 0x0e68, 0, &mmBIF_PERSTB_PAD_CNTL[0], sizeof(mmBIF_PERSTB_PAD_CNTL)/sizeof(mmBIF_PERSTB_PAD_CNTL[0]), 0, 0 }, - { "mmBIF_PX_EN_PAD_CNTL", REG_MMIO, 0x0e69, 0, &mmBIF_PX_EN_PAD_CNTL[0], sizeof(mmBIF_PX_EN_PAD_CNTL)/sizeof(mmBIF_PX_EN_PAD_CNTL[0]), 0, 0 }, - { "mmBIF_REFPADKIN_PAD_CNTL", REG_MMIO, 0x0e6a, 0, &mmBIF_REFPADKIN_PAD_CNTL[0], sizeof(mmBIF_REFPADKIN_PAD_CNTL)/sizeof(mmBIF_REFPADKIN_PAD_CNTL[0]), 0, 0 }, - { "mmBIF_CLKREQB_PAD_CNTL", REG_MMIO, 0x0e6b, 0, &mmBIF_CLKREQB_PAD_CNTL[0], sizeof(mmBIF_CLKREQB_PAD_CNTL)/sizeof(mmBIF_CLKREQB_PAD_CNTL[0]), 0, 0 }, - { "mmRCC_BACO_CNTL_MISC", REG_MMIO, 0x0da7, 0, &mmRCC_BACO_CNTL_MISC[0], sizeof(mmRCC_BACO_CNTL_MISC)/sizeof(mmRCC_BACO_CNTL_MISC[0]), 0, 0 }, - { "mmRCC_RESET_EN", REG_MMIO, 0x0da8, 0, &mmRCC_RESET_EN[0], sizeof(mmRCC_RESET_EN)/sizeof(mmRCC_RESET_EN[0]), 0, 0 }, - { "mmRCC_VDM_SUPPORT", REG_MMIO, 0x0da9, 0, &mmRCC_VDM_SUPPORT[0], sizeof(mmRCC_VDM_SUPPORT)/sizeof(mmRCC_VDM_SUPPORT[0]), 0, 0 }, - { "mmRCC_PEER_REG_RANGE0", REG_MMIO, 0x0dde, 0, &mmRCC_PEER_REG_RANGE0[0], sizeof(mmRCC_PEER_REG_RANGE0)/sizeof(mmRCC_PEER_REG_RANGE0[0]), 0, 0 }, - { "mmRCC_PEER_REG_RANGE1", REG_MMIO, 0x0ddf, 0, &mmRCC_PEER_REG_RANGE1[0], sizeof(mmRCC_PEER_REG_RANGE1)/sizeof(mmRCC_PEER_REG_RANGE1[0]), 0, 0 }, - { "mmRCC_BUS_CNTL", REG_MMIO, 0x0de1, 0, &mmRCC_BUS_CNTL[0], sizeof(mmRCC_BUS_CNTL)/sizeof(mmRCC_BUS_CNTL[0]), 0, 0 }, - { "mmRCC_CONFIG_CNTL", REG_MMIO, 0x0de2, 0, &mmRCC_CONFIG_CNTL[0], sizeof(mmRCC_CONFIG_CNTL)/sizeof(mmRCC_CONFIG_CNTL[0]), 0, 0 }, - { "mmRCC_CONFIG_F0_BASE", REG_MMIO, 0x0de6, 0, &mmRCC_CONFIG_F0_BASE[0], sizeof(mmRCC_CONFIG_F0_BASE)/sizeof(mmRCC_CONFIG_F0_BASE[0]), 0, 0 }, - { "mmRCC_CONFIG_APER_SIZE", REG_MMIO, 0x0de7, 0, &mmRCC_CONFIG_APER_SIZE[0], sizeof(mmRCC_CONFIG_APER_SIZE)/sizeof(mmRCC_CONFIG_APER_SIZE[0]), 0, 0 }, - { "mmRCC_CONFIG_REG_APER_SIZE", REG_MMIO, 0x0de8, 0, &mmRCC_CONFIG_REG_APER_SIZE[0], sizeof(mmRCC_CONFIG_REG_APER_SIZE)/sizeof(mmRCC_CONFIG_REG_APER_SIZE[0]), 0, 0 }, - { "mmRCC_XDMA_LO", REG_MMIO, 0x0de9, 0, &mmRCC_XDMA_LO[0], sizeof(mmRCC_XDMA_LO)/sizeof(mmRCC_XDMA_LO[0]), 0, 0 }, - { "mmRCC_XDMA_HI", REG_MMIO, 0x0dea, 0, &mmRCC_XDMA_HI[0], sizeof(mmRCC_XDMA_HI)/sizeof(mmRCC_XDMA_HI[0]), 0, 0 }, - { "mmRCC_FEATURES_CONTROL_MISC", REG_MMIO, 0x0deb, 0, &mmRCC_FEATURES_CONTROL_MISC[0], sizeof(mmRCC_FEATURES_CONTROL_MISC)/sizeof(mmRCC_FEATURES_CONTROL_MISC[0]), 0, 0 }, - { "mmRCC_BUSNUM_CNTL1", REG_MMIO, 0x0dec, 0, &mmRCC_BUSNUM_CNTL1[0], sizeof(mmRCC_BUSNUM_CNTL1)/sizeof(mmRCC_BUSNUM_CNTL1[0]), 0, 0 }, - { "mmRCC_BUSNUM_LIST0", REG_MMIO, 0x0ded, 0, &mmRCC_BUSNUM_LIST0[0], sizeof(mmRCC_BUSNUM_LIST0)/sizeof(mmRCC_BUSNUM_LIST0[0]), 0, 0 }, - { "mmRCC_BUSNUM_LIST1", REG_MMIO, 0x0dee, 0, &mmRCC_BUSNUM_LIST1[0], sizeof(mmRCC_BUSNUM_LIST1)/sizeof(mmRCC_BUSNUM_LIST1[0]), 0, 0 }, - { "mmRCC_BUSNUM_CNTL2", REG_MMIO, 0x0def, 0, &mmRCC_BUSNUM_CNTL2[0], sizeof(mmRCC_BUSNUM_CNTL2)/sizeof(mmRCC_BUSNUM_CNTL2[0]), 0, 0 }, - { "mmRCC_CAPTURE_HOST_BUSNUM", REG_MMIO, 0x0df0, 0, &mmRCC_CAPTURE_HOST_BUSNUM[0], sizeof(mmRCC_CAPTURE_HOST_BUSNUM)/sizeof(mmRCC_CAPTURE_HOST_BUSNUM[0]), 0, 0 }, - { "mmRCC_HOST_BUSNUM", REG_MMIO, 0x0df1, 0, &mmRCC_HOST_BUSNUM[0], sizeof(mmRCC_HOST_BUSNUM)/sizeof(mmRCC_HOST_BUSNUM[0]), 0, 0 }, - { "mmRCC_PEER0_FB_OFFSET_HI", REG_MMIO, 0x0df2, 0, &mmRCC_PEER0_FB_OFFSET_HI[0], sizeof(mmRCC_PEER0_FB_OFFSET_HI)/sizeof(mmRCC_PEER0_FB_OFFSET_HI[0]), 0, 0 }, - { "mmRCC_PEER0_FB_OFFSET_LO", REG_MMIO, 0x0df3, 0, &mmRCC_PEER0_FB_OFFSET_LO[0], sizeof(mmRCC_PEER0_FB_OFFSET_LO)/sizeof(mmRCC_PEER0_FB_OFFSET_LO[0]), 0, 0 }, - { "mmRCC_PEER1_FB_OFFSET_HI", REG_MMIO, 0x0df4, 0, &mmRCC_PEER1_FB_OFFSET_HI[0], sizeof(mmRCC_PEER1_FB_OFFSET_HI)/sizeof(mmRCC_PEER1_FB_OFFSET_HI[0]), 0, 0 }, - { "mmRCC_PEER1_FB_OFFSET_LO", REG_MMIO, 0x0df5, 0, &mmRCC_PEER1_FB_OFFSET_LO[0], sizeof(mmRCC_PEER1_FB_OFFSET_LO)/sizeof(mmRCC_PEER1_FB_OFFSET_LO[0]), 0, 0 }, - { "mmRCC_PEER2_FB_OFFSET_HI", REG_MMIO, 0x0df6, 0, &mmRCC_PEER2_FB_OFFSET_HI[0], sizeof(mmRCC_PEER2_FB_OFFSET_HI)/sizeof(mmRCC_PEER2_FB_OFFSET_HI[0]), 0, 0 }, - { "mmRCC_PEER2_FB_OFFSET_LO", REG_MMIO, 0x0df7, 0, &mmRCC_PEER2_FB_OFFSET_LO[0], sizeof(mmRCC_PEER2_FB_OFFSET_LO)/sizeof(mmRCC_PEER2_FB_OFFSET_LO[0]), 0, 0 }, - { "mmRCC_PEER3_FB_OFFSET_HI", REG_MMIO, 0x0df8, 0, &mmRCC_PEER3_FB_OFFSET_HI[0], sizeof(mmRCC_PEER3_FB_OFFSET_HI)/sizeof(mmRCC_PEER3_FB_OFFSET_HI[0]), 0, 0 }, - { "mmRCC_PEER3_FB_OFFSET_LO", REG_MMIO, 0x0df9, 0, &mmRCC_PEER3_FB_OFFSET_LO[0], sizeof(mmRCC_PEER3_FB_OFFSET_LO)/sizeof(mmRCC_PEER3_FB_OFFSET_LO[0]), 0, 0 }, - { "mmRCC_DEVFUNCNUM_LIST0", REG_MMIO, 0x0dfa, 0, &mmRCC_DEVFUNCNUM_LIST0[0], sizeof(mmRCC_DEVFUNCNUM_LIST0)/sizeof(mmRCC_DEVFUNCNUM_LIST0[0]), 0, 0 }, - { "mmRCC_DEVFUNCNUM_LIST1", REG_MMIO, 0x0dfb, 0, &mmRCC_DEVFUNCNUM_LIST1[0], sizeof(mmRCC_DEVFUNCNUM_LIST1)/sizeof(mmRCC_DEVFUNCNUM_LIST1[0]), 0, 0 }, - { "mmRCC_DEV0_LINK_CNTL", REG_MMIO, 0x0dfd, 0, &mmRCC_DEV0_LINK_CNTL[0], sizeof(mmRCC_DEV0_LINK_CNTL)/sizeof(mmRCC_DEV0_LINK_CNTL[0]), 0, 0 }, - { "mmRCC_CMN_LINK_CNTL", REG_MMIO, 0x0dfe, 0, &mmRCC_CMN_LINK_CNTL[0], sizeof(mmRCC_CMN_LINK_CNTL)/sizeof(mmRCC_CMN_LINK_CNTL[0]), 0, 0 }, - { "mmRCC_EP_REQUESTERID_RESTORE", REG_MMIO, 0x0dff, 0, &mmRCC_EP_REQUESTERID_RESTORE[0], sizeof(mmRCC_EP_REQUESTERID_RESTORE)/sizeof(mmRCC_EP_REQUESTERID_RESTORE[0]), 0, 0 }, - { "mmRCC_LTR_LSWITCH_CNTL", REG_MMIO, 0x0e00, 0, &mmRCC_LTR_LSWITCH_CNTL[0], sizeof(mmRCC_LTR_LSWITCH_CNTL)/sizeof(mmRCC_LTR_LSWITCH_CNTL[0]), 0, 0 }, - { "mmRCC_MH_ARB_CNTL", REG_MMIO, 0x0e01, 0, &mmRCC_MH_ARB_CNTL[0], sizeof(mmRCC_MH_ARB_CNTL)/sizeof(mmRCC_MH_ARB_CNTL[0]), 0, 0 }, - { "mmGFXMSIX_VECT0_ADDR_LO", REG_MMIO, 0x10800, 0, &mmGFXMSIX_VECT0_ADDR_LO[0], sizeof(mmGFXMSIX_VECT0_ADDR_LO)/sizeof(mmGFXMSIX_VECT0_ADDR_LO[0]), 0, 0 }, - { "mmGFXMSIX_VECT0_ADDR_HI", REG_MMIO, 0x10801, 0, &mmGFXMSIX_VECT0_ADDR_HI[0], sizeof(mmGFXMSIX_VECT0_ADDR_HI)/sizeof(mmGFXMSIX_VECT0_ADDR_HI[0]), 0, 0 }, - { "mmGFXMSIX_VECT0_MSG_DATA", REG_MMIO, 0x10802, 0, &mmGFXMSIX_VECT0_MSG_DATA[0], sizeof(mmGFXMSIX_VECT0_MSG_DATA)/sizeof(mmGFXMSIX_VECT0_MSG_DATA[0]), 0, 0 }, - { "mmGFXMSIX_VECT0_CONTROL", REG_MMIO, 0x10803, 0, &mmGFXMSIX_VECT0_CONTROL[0], sizeof(mmGFXMSIX_VECT0_CONTROL)/sizeof(mmGFXMSIX_VECT0_CONTROL[0]), 0, 0 }, - { "mmGFXMSIX_VECT1_ADDR_LO", REG_MMIO, 0x10804, 0, &mmGFXMSIX_VECT1_ADDR_LO[0], sizeof(mmGFXMSIX_VECT1_ADDR_LO)/sizeof(mmGFXMSIX_VECT1_ADDR_LO[0]), 0, 0 }, - { "mmGFXMSIX_VECT1_ADDR_HI", REG_MMIO, 0x10805, 0, &mmGFXMSIX_VECT1_ADDR_HI[0], sizeof(mmGFXMSIX_VECT1_ADDR_HI)/sizeof(mmGFXMSIX_VECT1_ADDR_HI[0]), 0, 0 }, - { "mmGFXMSIX_VECT1_MSG_DATA", REG_MMIO, 0x10806, 0, &mmGFXMSIX_VECT1_MSG_DATA[0], sizeof(mmGFXMSIX_VECT1_MSG_DATA)/sizeof(mmGFXMSIX_VECT1_MSG_DATA[0]), 0, 0 }, - { "mmGFXMSIX_VECT1_CONTROL", REG_MMIO, 0x10807, 0, &mmGFXMSIX_VECT1_CONTROL[0], sizeof(mmGFXMSIX_VECT1_CONTROL)/sizeof(mmGFXMSIX_VECT1_CONTROL[0]), 0, 0 }, - { "mmGFXMSIX_VECT2_ADDR_LO", REG_MMIO, 0x10808, 0, &mmGFXMSIX_VECT2_ADDR_LO[0], sizeof(mmGFXMSIX_VECT2_ADDR_LO)/sizeof(mmGFXMSIX_VECT2_ADDR_LO[0]), 0, 0 }, - { "mmGFXMSIX_VECT2_ADDR_HI", REG_MMIO, 0x10809, 0, &mmGFXMSIX_VECT2_ADDR_HI[0], sizeof(mmGFXMSIX_VECT2_ADDR_HI)/sizeof(mmGFXMSIX_VECT2_ADDR_HI[0]), 0, 0 }, - { "mmGFXMSIX_VECT2_MSG_DATA", REG_MMIO, 0x1080a, 0, &mmGFXMSIX_VECT2_MSG_DATA[0], sizeof(mmGFXMSIX_VECT2_MSG_DATA)/sizeof(mmGFXMSIX_VECT2_MSG_DATA[0]), 0, 0 }, - { "mmGFXMSIX_VECT2_CONTROL", REG_MMIO, 0x1080b, 0, &mmGFXMSIX_VECT2_CONTROL[0], sizeof(mmGFXMSIX_VECT2_CONTROL)/sizeof(mmGFXMSIX_VECT2_CONTROL[0]), 0, 0 }, - { "mmGFXMSIX_PBA", REG_MMIO, 0x10c00, 0, &mmGFXMSIX_PBA[0], sizeof(mmGFXMSIX_PBA)/sizeof(mmGFXMSIX_PBA[0]), 0, 0 }, - { "mmRCC_DEV0_PORT_STRAP0", REG_MMIO, 0x0d27, 0, &mmRCC_DEV0_PORT_STRAP0[0], sizeof(mmRCC_DEV0_PORT_STRAP0)/sizeof(mmRCC_DEV0_PORT_STRAP0[0]), 0, 0 }, - { "mmRCC_DEV0_PORT_STRAP1", REG_MMIO, 0x0d28, 0, &mmRCC_DEV0_PORT_STRAP1[0], sizeof(mmRCC_DEV0_PORT_STRAP1)/sizeof(mmRCC_DEV0_PORT_STRAP1[0]), 0, 0 }, - { "mmRCC_DEV0_PORT_STRAP2", REG_MMIO, 0x0d29, 0, &mmRCC_DEV0_PORT_STRAP2[0], sizeof(mmRCC_DEV0_PORT_STRAP2)/sizeof(mmRCC_DEV0_PORT_STRAP2[0]), 0, 0 }, - { "mmRCC_DEV0_PORT_STRAP3", REG_MMIO, 0x0d2a, 0, &mmRCC_DEV0_PORT_STRAP3[0], sizeof(mmRCC_DEV0_PORT_STRAP3)/sizeof(mmRCC_DEV0_PORT_STRAP3[0]), 0, 0 }, - { "mmRCC_DEV0_PORT_STRAP4", REG_MMIO, 0x0d2b, 0, &mmRCC_DEV0_PORT_STRAP4[0], sizeof(mmRCC_DEV0_PORT_STRAP4)/sizeof(mmRCC_DEV0_PORT_STRAP4[0]), 0, 0 }, - { "mmRCC_DEV0_PORT_STRAP5", REG_MMIO, 0x0d2c, 0, &mmRCC_DEV0_PORT_STRAP5[0], sizeof(mmRCC_DEV0_PORT_STRAP5)/sizeof(mmRCC_DEV0_PORT_STRAP5[0]), 0, 0 }, - { "mmRCC_DEV0_PORT_STRAP6", REG_MMIO, 0x0d2d, 0, &mmRCC_DEV0_PORT_STRAP6[0], sizeof(mmRCC_DEV0_PORT_STRAP6)/sizeof(mmRCC_DEV0_PORT_STRAP6[0]), 0, 0 }, - { "mmRCC_DEV0_PORT_STRAP7", REG_MMIO, 0x0d2e, 0, &mmRCC_DEV0_PORT_STRAP7[0], sizeof(mmRCC_DEV0_PORT_STRAP7)/sizeof(mmRCC_DEV0_PORT_STRAP7[0]), 0, 0 }, - { "mmRCC_DEV0_EPF0_STRAP0", REG_MMIO, 0x0d2f, 0, &mmRCC_DEV0_EPF0_STRAP0[0], sizeof(mmRCC_DEV0_EPF0_STRAP0)/sizeof(mmRCC_DEV0_EPF0_STRAP0[0]), 0, 0 }, - { "mmRCC_DEV0_EPF0_STRAP1", REG_MMIO, 0x0d30, 0, &mmRCC_DEV0_EPF0_STRAP1[0], sizeof(mmRCC_DEV0_EPF0_STRAP1)/sizeof(mmRCC_DEV0_EPF0_STRAP1[0]), 0, 0 }, - { "mmRCC_DEV0_EPF0_STRAP13", REG_MMIO, 0x0d31, 0, &mmRCC_DEV0_EPF0_STRAP13[0], sizeof(mmRCC_DEV0_EPF0_STRAP13)/sizeof(mmRCC_DEV0_EPF0_STRAP13[0]), 0, 0 }, - { "mmRCC_DEV0_EPF0_STRAP2", REG_MMIO, 0x0d32, 0, &mmRCC_DEV0_EPF0_STRAP2[0], sizeof(mmRCC_DEV0_EPF0_STRAP2)/sizeof(mmRCC_DEV0_EPF0_STRAP2[0]), 0, 0 }, - { "mmRCC_DEV0_EPF0_STRAP3", REG_MMIO, 0x0d33, 0, &mmRCC_DEV0_EPF0_STRAP3[0], sizeof(mmRCC_DEV0_EPF0_STRAP3)/sizeof(mmRCC_DEV0_EPF0_STRAP3[0]), 0, 0 }, - { "mmRCC_DEV0_EPF0_STRAP4", REG_MMIO, 0x0d34, 0, &mmRCC_DEV0_EPF0_STRAP4[0], sizeof(mmRCC_DEV0_EPF0_STRAP4)/sizeof(mmRCC_DEV0_EPF0_STRAP4[0]), 0, 0 }, - { "mmRCC_DEV0_EPF0_STRAP5", REG_MMIO, 0x0d35, 0, &mmRCC_DEV0_EPF0_STRAP5[0], sizeof(mmRCC_DEV0_EPF0_STRAP5)/sizeof(mmRCC_DEV0_EPF0_STRAP5[0]), 0, 0 }, - { "mmRCC_DEV0_EPF0_STRAP8", REG_MMIO, 0x0d36, 0, &mmRCC_DEV0_EPF0_STRAP8[0], sizeof(mmRCC_DEV0_EPF0_STRAP8)/sizeof(mmRCC_DEV0_EPF0_STRAP8[0]), 0, 0 }, - { "mmRCC_DEV0_EPF0_STRAP9", REG_MMIO, 0x0d37, 0, NULL, 0, 0, 0 }, - { "mmRCC_DEV0_EPF1_STRAP0", REG_MMIO, 0x0d38, 0, &mmRCC_DEV0_EPF1_STRAP0[0], sizeof(mmRCC_DEV0_EPF1_STRAP0)/sizeof(mmRCC_DEV0_EPF1_STRAP0[0]), 0, 0 }, - { "mmRCC_DEV0_EPF1_STRAP10", REG_MMIO, 0x0d39, 0, &mmRCC_DEV0_EPF1_STRAP10[0], sizeof(mmRCC_DEV0_EPF1_STRAP10)/sizeof(mmRCC_DEV0_EPF1_STRAP10[0]), 0, 0 }, - { "mmRCC_DEV0_EPF1_STRAP11", REG_MMIO, 0x0d3a, 0, &mmRCC_DEV0_EPF1_STRAP11[0], sizeof(mmRCC_DEV0_EPF1_STRAP11)/sizeof(mmRCC_DEV0_EPF1_STRAP11[0]), 0, 0 }, - { "mmRCC_DEV0_EPF1_STRAP12", REG_MMIO, 0x0d3b, 0, &mmRCC_DEV0_EPF1_STRAP12[0], sizeof(mmRCC_DEV0_EPF1_STRAP12)/sizeof(mmRCC_DEV0_EPF1_STRAP12[0]), 0, 0 }, - { "mmRCC_DEV0_EPF1_STRAP13", REG_MMIO, 0x0d3c, 0, &mmRCC_DEV0_EPF1_STRAP13[0], sizeof(mmRCC_DEV0_EPF1_STRAP13)/sizeof(mmRCC_DEV0_EPF1_STRAP13[0]), 0, 0 }, - { "mmRCC_DEV0_EPF1_STRAP2", REG_MMIO, 0x0d3d, 0, &mmRCC_DEV0_EPF1_STRAP2[0], sizeof(mmRCC_DEV0_EPF1_STRAP2)/sizeof(mmRCC_DEV0_EPF1_STRAP2[0]), 0, 0 }, - { "mmRCC_DEV0_EPF1_STRAP3", REG_MMIO, 0x0d3e, 0, &mmRCC_DEV0_EPF1_STRAP3[0], sizeof(mmRCC_DEV0_EPF1_STRAP3)/sizeof(mmRCC_DEV0_EPF1_STRAP3[0]), 0, 0 }, - { "mmRCC_DEV0_EPF1_STRAP4", REG_MMIO, 0x0d3f, 0, &mmRCC_DEV0_EPF1_STRAP4[0], sizeof(mmRCC_DEV0_EPF1_STRAP4)/sizeof(mmRCC_DEV0_EPF1_STRAP4[0]), 0, 0 }, - { "mmRCC_DEV0_EPF1_STRAP5", REG_MMIO, 0x0d40, 0, &mmRCC_DEV0_EPF1_STRAP5[0], sizeof(mmRCC_DEV0_EPF1_STRAP5)/sizeof(mmRCC_DEV0_EPF1_STRAP5[0]), 0, 0 }, - { "mmRCC_DEV0_EPF1_STRAP6", REG_MMIO, 0x0d41, 0, &mmRCC_DEV0_EPF1_STRAP6[0], sizeof(mmRCC_DEV0_EPF1_STRAP6)/sizeof(mmRCC_DEV0_EPF1_STRAP6[0]), 0, 0 }, - { "mmRCC_DEV0_EPF1_STRAP7", REG_MMIO, 0x0d42, 0, &mmRCC_DEV0_EPF1_STRAP7[0], sizeof(mmRCC_DEV0_EPF1_STRAP7)/sizeof(mmRCC_DEV0_EPF1_STRAP7[0]), 0, 0 }, - { "mmBIF_BME_STATUS", REG_MMIO, 0x0e0b, 0, &mmBIF_BME_STATUS[0], sizeof(mmBIF_BME_STATUS)/sizeof(mmBIF_BME_STATUS[0]), 0, 0 }, - { "mmBIF_ATOMIC_ERR_LOG", REG_MMIO, 0x0e0c, 0, &mmBIF_ATOMIC_ERR_LOG[0], sizeof(mmBIF_ATOMIC_ERR_LOG)/sizeof(mmBIF_ATOMIC_ERR_LOG[0]), 0, 0 }, - { "mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH", REG_MMIO, 0x0e13, 0, &mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH[0], sizeof(mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH)/sizeof(mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH[0]), 0, 0 }, - { "mmDOORBELL_SELFRING_GPA_APER_BASE_LOW", REG_MMIO, 0x0e14, 0, &mmDOORBELL_SELFRING_GPA_APER_BASE_LOW[0], sizeof(mmDOORBELL_SELFRING_GPA_APER_BASE_LOW)/sizeof(mmDOORBELL_SELFRING_GPA_APER_BASE_LOW[0]), 0, 0 }, - { "mmDOORBELL_SELFRING_GPA_APER_CNTL", REG_MMIO, 0x0e15, 0, &mmDOORBELL_SELFRING_GPA_APER_CNTL[0], sizeof(mmDOORBELL_SELFRING_GPA_APER_CNTL)/sizeof(mmDOORBELL_SELFRING_GPA_APER_CNTL[0]), 0, 0 }, - { "mmHDP_REG_COHERENCY_FLUSH_CNTL", REG_MMIO, 0x0e16, 0, &mmHDP_REG_COHERENCY_FLUSH_CNTL[0], sizeof(mmHDP_REG_COHERENCY_FLUSH_CNTL)/sizeof(mmHDP_REG_COHERENCY_FLUSH_CNTL[0]), 0, 0 }, - { "mmHDP_MEM_COHERENCY_FLUSH_CNTL", REG_MMIO, 0x0e17, 0, &mmHDP_MEM_COHERENCY_FLUSH_CNTL[0], sizeof(mmHDP_MEM_COHERENCY_FLUSH_CNTL)/sizeof(mmHDP_MEM_COHERENCY_FLUSH_CNTL[0]), 0, 0 }, - { "mmGPU_HDP_FLUSH_REQ", REG_MMIO, 0x0e26, 0, &mmGPU_HDP_FLUSH_REQ[0], sizeof(mmGPU_HDP_FLUSH_REQ)/sizeof(mmGPU_HDP_FLUSH_REQ[0]), 0, 0 }, - { "mmGPU_HDP_FLUSH_DONE", REG_MMIO, 0x0e27, 0, &mmGPU_HDP_FLUSH_DONE[0], sizeof(mmGPU_HDP_FLUSH_DONE)/sizeof(mmGPU_HDP_FLUSH_DONE[0]), 0, 0 }, - { "mmBIF_TRANS_PENDING", REG_MMIO, 0x0e28, 0, &mmBIF_TRANS_PENDING[0], sizeof(mmBIF_TRANS_PENDING)/sizeof(mmBIF_TRANS_PENDING[0]), 0, 0 }, - { "mmMAILBOX_MSGBUF_TRN_DW0", REG_MMIO, 0x0e56, 0, &mmMAILBOX_MSGBUF_TRN_DW0[0], sizeof(mmMAILBOX_MSGBUF_TRN_DW0)/sizeof(mmMAILBOX_MSGBUF_TRN_DW0[0]), 0, 0 }, - { "mmMAILBOX_MSGBUF_TRN_DW1", REG_MMIO, 0x0e57, 0, &mmMAILBOX_MSGBUF_TRN_DW1[0], sizeof(mmMAILBOX_MSGBUF_TRN_DW1)/sizeof(mmMAILBOX_MSGBUF_TRN_DW1[0]), 0, 0 }, - { "mmMAILBOX_MSGBUF_TRN_DW2", REG_MMIO, 0x0e58, 0, &mmMAILBOX_MSGBUF_TRN_DW2[0], sizeof(mmMAILBOX_MSGBUF_TRN_DW2)/sizeof(mmMAILBOX_MSGBUF_TRN_DW2[0]), 0, 0 }, - { "mmMAILBOX_MSGBUF_TRN_DW3", REG_MMIO, 0x0e59, 0, &mmMAILBOX_MSGBUF_TRN_DW3[0], sizeof(mmMAILBOX_MSGBUF_TRN_DW3)/sizeof(mmMAILBOX_MSGBUF_TRN_DW3[0]), 0, 0 }, - { "mmMAILBOX_MSGBUF_RCV_DW0", REG_MMIO, 0x0e5a, 0, &mmMAILBOX_MSGBUF_RCV_DW0[0], sizeof(mmMAILBOX_MSGBUF_RCV_DW0)/sizeof(mmMAILBOX_MSGBUF_RCV_DW0[0]), 0, 0 }, - { "mmMAILBOX_MSGBUF_RCV_DW1", REG_MMIO, 0x0e5b, 0, &mmMAILBOX_MSGBUF_RCV_DW1[0], sizeof(mmMAILBOX_MSGBUF_RCV_DW1)/sizeof(mmMAILBOX_MSGBUF_RCV_DW1[0]), 0, 0 }, - { "mmMAILBOX_MSGBUF_RCV_DW2", REG_MMIO, 0x0e5c, 0, &mmMAILBOX_MSGBUF_RCV_DW2[0], sizeof(mmMAILBOX_MSGBUF_RCV_DW2)/sizeof(mmMAILBOX_MSGBUF_RCV_DW2[0]), 0, 0 }, - { "mmMAILBOX_MSGBUF_RCV_DW3", REG_MMIO, 0x0e5d, 0, &mmMAILBOX_MSGBUF_RCV_DW3[0], sizeof(mmMAILBOX_MSGBUF_RCV_DW3)/sizeof(mmMAILBOX_MSGBUF_RCV_DW3[0]), 0, 0 }, - { "mmMAILBOX_CONTROL", REG_MMIO, 0x0e5e, 0, &mmMAILBOX_CONTROL[0], sizeof(mmMAILBOX_CONTROL)/sizeof(mmMAILBOX_CONTROL[0]), 0, 0 }, - { "mmMAILBOX_INT_CNTL", REG_MMIO, 0x0e5f, 0, &mmMAILBOX_INT_CNTL[0], sizeof(mmMAILBOX_INT_CNTL)/sizeof(mmMAILBOX_INT_CNTL[0]), 0, 0 }, - { "mmBIF_VMHV_MAILBOX", REG_MMIO, 0x0e60, 0, &mmBIF_VMHV_MAILBOX[0], sizeof(mmBIF_VMHV_MAILBOX)/sizeof(mmBIF_VMHV_MAILBOX[0]), 0, 0 }, - { "mmRCC_DOORBELL_APER_EN", REG_MMIO, 0x0de0, 0, &mmRCC_DOORBELL_APER_EN[0], sizeof(mmRCC_DOORBELL_APER_EN)/sizeof(mmRCC_DOORBELL_APER_EN[0]), 0, 0 }, - { "mmRCC_CONFIG_MEMSIZE", REG_MMIO, 0x0de3, 0, &mmRCC_CONFIG_MEMSIZE[0], sizeof(mmRCC_CONFIG_MEMSIZE)/sizeof(mmRCC_CONFIG_MEMSIZE[0]), 0, 0 }, - { "mmRCC_CONFIG_RESERVED", REG_MMIO, 0x0de4, 0, &mmRCC_CONFIG_RESERVED[0], sizeof(mmRCC_CONFIG_RESERVED)/sizeof(mmRCC_CONFIG_RESERVED[0]), 0, 0 }, - { "mmRCC_IOV_FUNC_IDENTIFIER", REG_MMIO, 0x0de5, 0, &mmRCC_IOV_FUNC_IDENTIFIER[0], sizeof(mmRCC_IOV_FUNC_IDENTIFIER)/sizeof(mmRCC_IOV_FUNC_IDENTIFIER[0]), 0, 0 }, - { "mmSYSHUB_INDEX", REG_MMIO, 0x0008, 0, &mmSYSHUB_INDEX[0], sizeof(mmSYSHUB_INDEX)/sizeof(mmSYSHUB_INDEX[0]), 0, 0 }, - { "mmSYSHUB_DATA", REG_MMIO, 0x0009, 0, &mmSYSHUB_DATA[0], sizeof(mmSYSHUB_DATA)/sizeof(mmSYSHUB_DATA[0]), 0, 0 }, - { "mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0", REG_MMIO, 0x403c000, 3, &mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0[0], sizeof(mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0)/sizeof(mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0[0]), 0, 0 }, - { "mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP1", REG_MMIO, 0x403c001, 3, &mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP1[0], sizeof(mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP1)/sizeof(mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP1[0]), 0, 0 }, - { "mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2", REG_MMIO, 0x403c002, 3, &mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2[0], sizeof(mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2)/sizeof(mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2[0]), 0, 0 }, - { "mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3", REG_MMIO, 0x403c003, 3, &mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3[0], sizeof(mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3)/sizeof(mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3[0]), 0, 0 }, - { "mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4", REG_MMIO, 0x403c004, 3, &mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4[0], sizeof(mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4)/sizeof(mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4[0]), 0, 0 }, - { "mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5", REG_MMIO, 0x403c005, 3, &mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5[0], sizeof(mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5)/sizeof(mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5[0]), 0, 0 }, - { "mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP6", REG_MMIO, 0x403c006, 3, &mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP6[0], sizeof(mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP6)/sizeof(mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP6[0]), 0, 0 }, - { "mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7", REG_MMIO, 0x403c007, 3, &mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7[0], sizeof(mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7)/sizeof(mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7[0]), 0, 0 }, - { "mmRCC_DEV1_PORT_STRAP0", REG_MMIO, 0x403c080, 3, &mmRCC_DEV1_PORT_STRAP0[0], sizeof(mmRCC_DEV1_PORT_STRAP0)/sizeof(mmRCC_DEV1_PORT_STRAP0[0]), 0, 0 }, - { "mmRCC_DEV1_PORT_STRAP1", REG_MMIO, 0x403c081, 3, &mmRCC_DEV1_PORT_STRAP1[0], sizeof(mmRCC_DEV1_PORT_STRAP1)/sizeof(mmRCC_DEV1_PORT_STRAP1[0]), 0, 0 }, - { "mmRCC_DEV1_PORT_STRAP2", REG_MMIO, 0x403c082, 3, &mmRCC_DEV1_PORT_STRAP2[0], sizeof(mmRCC_DEV1_PORT_STRAP2)/sizeof(mmRCC_DEV1_PORT_STRAP2[0]), 0, 0 }, - { "mmRCC_DEV1_PORT_STRAP3", REG_MMIO, 0x403c083, 3, &mmRCC_DEV1_PORT_STRAP3[0], sizeof(mmRCC_DEV1_PORT_STRAP3)/sizeof(mmRCC_DEV1_PORT_STRAP3[0]), 0, 0 }, - { "mmRCC_DEV1_PORT_STRAP4", REG_MMIO, 0x403c084, 3, &mmRCC_DEV1_PORT_STRAP4[0], sizeof(mmRCC_DEV1_PORT_STRAP4)/sizeof(mmRCC_DEV1_PORT_STRAP4[0]), 0, 0 }, - { "mmRCC_DEV1_PORT_STRAP5", REG_MMIO, 0x403c085, 3, &mmRCC_DEV1_PORT_STRAP5[0], sizeof(mmRCC_DEV1_PORT_STRAP5)/sizeof(mmRCC_DEV1_PORT_STRAP5[0]), 0, 0 }, - { "mmRCC_DEV1_PORT_STRAP6", REG_MMIO, 0x403c086, 3, &mmRCC_DEV1_PORT_STRAP6[0], sizeof(mmRCC_DEV1_PORT_STRAP6)/sizeof(mmRCC_DEV1_PORT_STRAP6[0]), 0, 0 }, - { "mmRCC_DEV1_PORT_STRAP7", REG_MMIO, 0x403c087, 3, &mmRCC_DEV1_PORT_STRAP7[0], sizeof(mmRCC_DEV1_PORT_STRAP7)/sizeof(mmRCC_DEV1_PORT_STRAP7[0]), 0, 0 }, - { "mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0", REG_MMIO, 0x403cc00, 3, &mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0[0], sizeof(mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0)/sizeof(mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0[0]), 0, 0 }, - { "mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP1", REG_MMIO, 0x403cc01, 3, &mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP1[0], sizeof(mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP1)/sizeof(mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP1[0]), 0, 0 }, - { "mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2", REG_MMIO, 0x403cc02, 3, &mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2[0], sizeof(mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2)/sizeof(mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2[0]), 0, 0 }, - { "mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3", REG_MMIO, 0x403cc03, 3, &mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3[0], sizeof(mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3)/sizeof(mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3[0]), 0, 0 }, - { "mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4", REG_MMIO, 0x403cc04, 3, &mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4[0], sizeof(mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4)/sizeof(mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4[0]), 0, 0 }, - { "mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP5", REG_MMIO, 0x403cc05, 3, &mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP5[0], sizeof(mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP5)/sizeof(mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP5[0]), 0, 0 }, - { "mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8", REG_MMIO, 0x403cc08, 3, &mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8[0], sizeof(mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8)/sizeof(mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8[0]), 0, 0 }, - { "mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP9", REG_MMIO, 0x403cc09, 3, NULL, 0, 0, 0 }, - { "mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13", REG_MMIO, 0x403cc0d, 3, &mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13[0], sizeof(mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13)/sizeof(mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13[0]), 0, 0 }, - { "mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0", REG_MMIO, 0x403cc80, 3, &mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0[0], sizeof(mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0)/sizeof(mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0[0]), 0, 0 }, - { "mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2", REG_MMIO, 0x403cc82, 3, &mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2[0], sizeof(mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2)/sizeof(mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2[0]), 0, 0 }, - { "mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3", REG_MMIO, 0x403cc83, 3, &mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3[0], sizeof(mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3)/sizeof(mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3[0]), 0, 0 }, - { "mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4", REG_MMIO, 0x403cc84, 3, &mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4[0], sizeof(mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4)/sizeof(mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4[0]), 0, 0 }, - { "mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP5", REG_MMIO, 0x403cc85, 3, &mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP5[0], sizeof(mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP5)/sizeof(mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP5[0]), 0, 0 }, - { "mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6", REG_MMIO, 0x403cc86, 3, &mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6[0], sizeof(mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6)/sizeof(mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6[0]), 0, 0 }, - { "mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP7", REG_MMIO, 0x403cc87, 3, &mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP7[0], sizeof(mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP7)/sizeof(mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP7[0]), 0, 0 }, - { "mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP10", REG_MMIO, 0x403cc8a, 3, &mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP10[0], sizeof(mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP10)/sizeof(mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP10[0]), 0, 0 }, - { "mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP11", REG_MMIO, 0x403cc8b, 3, &mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP11[0], sizeof(mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP11)/sizeof(mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP11[0]), 0, 0 }, - { "mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP12", REG_MMIO, 0x403cc8c, 3, &mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP12[0], sizeof(mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP12)/sizeof(mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP12[0]), 0, 0 }, - { "mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13", REG_MMIO, 0x403cc8d, 3, &mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13[0], sizeof(mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13)/sizeof(mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13[0]), 0, 0 }, - { "mmRCC_DEV0_EPF2_STRAP0", REG_MMIO, 0x403cd00, 3, &mmRCC_DEV0_EPF2_STRAP0[0], sizeof(mmRCC_DEV0_EPF2_STRAP0)/sizeof(mmRCC_DEV0_EPF2_STRAP0[0]), 0, 0 }, - { "mmRCC_DEV0_EPF2_STRAP2", REG_MMIO, 0x403cd02, 3, &mmRCC_DEV0_EPF2_STRAP2[0], sizeof(mmRCC_DEV0_EPF2_STRAP2)/sizeof(mmRCC_DEV0_EPF2_STRAP2[0]), 0, 0 }, - { "mmRCC_DEV0_EPF2_STRAP3", REG_MMIO, 0x403cd03, 3, &mmRCC_DEV0_EPF2_STRAP3[0], sizeof(mmRCC_DEV0_EPF2_STRAP3)/sizeof(mmRCC_DEV0_EPF2_STRAP3[0]), 0, 0 }, - { "mmRCC_DEV0_EPF2_STRAP4", REG_MMIO, 0x403cd04, 3, &mmRCC_DEV0_EPF2_STRAP4[0], sizeof(mmRCC_DEV0_EPF2_STRAP4)/sizeof(mmRCC_DEV0_EPF2_STRAP4[0]), 0, 0 }, - { "mmRCC_DEV0_EPF2_STRAP5", REG_MMIO, 0x403cd05, 3, &mmRCC_DEV0_EPF2_STRAP5[0], sizeof(mmRCC_DEV0_EPF2_STRAP5)/sizeof(mmRCC_DEV0_EPF2_STRAP5[0]), 0, 0 }, - { "mmRCC_DEV0_EPF2_STRAP6", REG_MMIO, 0x403cd06, 3, &mmRCC_DEV0_EPF2_STRAP6[0], sizeof(mmRCC_DEV0_EPF2_STRAP6)/sizeof(mmRCC_DEV0_EPF2_STRAP6[0]), 0, 0 }, - { "mmRCC_DEV0_EPF2_STRAP13", REG_MMIO, 0x403cd0d, 3, &mmRCC_DEV0_EPF2_STRAP13[0], sizeof(mmRCC_DEV0_EPF2_STRAP13)/sizeof(mmRCC_DEV0_EPF2_STRAP13[0]), 0, 0 }, - { "mmRCC_DEV0_EPF3_STRAP0", REG_MMIO, 0x403cd80, 3, &mmRCC_DEV0_EPF3_STRAP0[0], sizeof(mmRCC_DEV0_EPF3_STRAP0)/sizeof(mmRCC_DEV0_EPF3_STRAP0[0]), 0, 0 }, - { "mmRCC_DEV0_EPF3_STRAP2", REG_MMIO, 0x403cd82, 3, &mmRCC_DEV0_EPF3_STRAP2[0], sizeof(mmRCC_DEV0_EPF3_STRAP2)/sizeof(mmRCC_DEV0_EPF3_STRAP2[0]), 0, 0 }, - { "mmRCC_DEV0_EPF3_STRAP3", REG_MMIO, 0x403cd83, 3, &mmRCC_DEV0_EPF3_STRAP3[0], sizeof(mmRCC_DEV0_EPF3_STRAP3)/sizeof(mmRCC_DEV0_EPF3_STRAP3[0]), 0, 0 }, - { "mmRCC_DEV0_EPF3_STRAP4", REG_MMIO, 0x403cd84, 3, &mmRCC_DEV0_EPF3_STRAP4[0], sizeof(mmRCC_DEV0_EPF3_STRAP4)/sizeof(mmRCC_DEV0_EPF3_STRAP4[0]), 0, 0 }, - { "mmRCC_DEV0_EPF3_STRAP5", REG_MMIO, 0x403cd85, 3, &mmRCC_DEV0_EPF3_STRAP5[0], sizeof(mmRCC_DEV0_EPF3_STRAP5)/sizeof(mmRCC_DEV0_EPF3_STRAP5[0]), 0, 0 }, - { "mmRCC_DEV0_EPF3_STRAP6", REG_MMIO, 0x403cd86, 3, &mmRCC_DEV0_EPF3_STRAP6[0], sizeof(mmRCC_DEV0_EPF3_STRAP6)/sizeof(mmRCC_DEV0_EPF3_STRAP6[0]), 0, 0 }, - { "mmRCC_DEV0_EPF3_STRAP13", REG_MMIO, 0x403cd8d, 3, &mmRCC_DEV0_EPF3_STRAP13[0], sizeof(mmRCC_DEV0_EPF3_STRAP13)/sizeof(mmRCC_DEV0_EPF3_STRAP13[0]), 0, 0 }, - { "mmRCC_DEV0_EPF4_STRAP0", REG_MMIO, 0x403ce00, 3, &mmRCC_DEV0_EPF4_STRAP0[0], sizeof(mmRCC_DEV0_EPF4_STRAP0)/sizeof(mmRCC_DEV0_EPF4_STRAP0[0]), 0, 0 }, - { "mmRCC_DEV0_EPF4_STRAP2", REG_MMIO, 0x403ce02, 3, &mmRCC_DEV0_EPF4_STRAP2[0], sizeof(mmRCC_DEV0_EPF4_STRAP2)/sizeof(mmRCC_DEV0_EPF4_STRAP2[0]), 0, 0 }, - { "mmRCC_DEV0_EPF4_STRAP3", REG_MMIO, 0x403ce03, 3, &mmRCC_DEV0_EPF4_STRAP3[0], sizeof(mmRCC_DEV0_EPF4_STRAP3)/sizeof(mmRCC_DEV0_EPF4_STRAP3[0]), 0, 0 }, - { "mmRCC_DEV0_EPF4_STRAP4", REG_MMIO, 0x403ce04, 3, &mmRCC_DEV0_EPF4_STRAP4[0], sizeof(mmRCC_DEV0_EPF4_STRAP4)/sizeof(mmRCC_DEV0_EPF4_STRAP4[0]), 0, 0 }, - { "mmRCC_DEV0_EPF4_STRAP5", REG_MMIO, 0x403ce05, 3, &mmRCC_DEV0_EPF4_STRAP5[0], sizeof(mmRCC_DEV0_EPF4_STRAP5)/sizeof(mmRCC_DEV0_EPF4_STRAP5[0]), 0, 0 }, - { "mmRCC_DEV0_EPF4_STRAP6", REG_MMIO, 0x403ce06, 3, &mmRCC_DEV0_EPF4_STRAP6[0], sizeof(mmRCC_DEV0_EPF4_STRAP6)/sizeof(mmRCC_DEV0_EPF4_STRAP6[0]), 0, 0 }, - { "mmRCC_DEV0_EPF4_STRAP13", REG_MMIO, 0x403ce0d, 3, &mmRCC_DEV0_EPF4_STRAP13[0], sizeof(mmRCC_DEV0_EPF4_STRAP13)/sizeof(mmRCC_DEV0_EPF4_STRAP13[0]), 0, 0 }, - { "mmRCC_DEV0_EPF5_STRAP0", REG_MMIO, 0x403ce80, 3, &mmRCC_DEV0_EPF5_STRAP0[0], sizeof(mmRCC_DEV0_EPF5_STRAP0)/sizeof(mmRCC_DEV0_EPF5_STRAP0[0]), 0, 0 }, - { "mmRCC_DEV0_EPF5_STRAP2", REG_MMIO, 0x403ce82, 3, &mmRCC_DEV0_EPF5_STRAP2[0], sizeof(mmRCC_DEV0_EPF5_STRAP2)/sizeof(mmRCC_DEV0_EPF5_STRAP2[0]), 0, 0 }, - { "mmRCC_DEV0_EPF5_STRAP3", REG_MMIO, 0x403ce83, 3, &mmRCC_DEV0_EPF5_STRAP3[0], sizeof(mmRCC_DEV0_EPF5_STRAP3)/sizeof(mmRCC_DEV0_EPF5_STRAP3[0]), 0, 0 }, - { "mmRCC_DEV0_EPF5_STRAP4", REG_MMIO, 0x403ce84, 3, &mmRCC_DEV0_EPF5_STRAP4[0], sizeof(mmRCC_DEV0_EPF5_STRAP4)/sizeof(mmRCC_DEV0_EPF5_STRAP4[0]), 0, 0 }, - { "mmRCC_DEV0_EPF5_STRAP5", REG_MMIO, 0x403ce85, 3, &mmRCC_DEV0_EPF5_STRAP5[0], sizeof(mmRCC_DEV0_EPF5_STRAP5)/sizeof(mmRCC_DEV0_EPF5_STRAP5[0]), 0, 0 }, - { "mmRCC_DEV0_EPF5_STRAP6", REG_MMIO, 0x403ce86, 3, &mmRCC_DEV0_EPF5_STRAP6[0], sizeof(mmRCC_DEV0_EPF5_STRAP6)/sizeof(mmRCC_DEV0_EPF5_STRAP6[0]), 0, 0 }, - { "mmRCC_DEV0_EPF5_STRAP13", REG_MMIO, 0x403ce8d, 3, &mmRCC_DEV0_EPF5_STRAP13[0], sizeof(mmRCC_DEV0_EPF5_STRAP13)/sizeof(mmRCC_DEV0_EPF5_STRAP13[0]), 0, 0 }, - { "mmRCC_DEV0_EPF6_STRAP0", REG_MMIO, 0x403cf00, 3, &mmRCC_DEV0_EPF6_STRAP0[0], sizeof(mmRCC_DEV0_EPF6_STRAP0)/sizeof(mmRCC_DEV0_EPF6_STRAP0[0]), 0, 0 }, - { "mmRCC_DEV0_EPF6_STRAP2", REG_MMIO, 0x403cf02, 3, &mmRCC_DEV0_EPF6_STRAP2[0], sizeof(mmRCC_DEV0_EPF6_STRAP2)/sizeof(mmRCC_DEV0_EPF6_STRAP2[0]), 0, 0 }, - { "mmRCC_DEV0_EPF6_STRAP3", REG_MMIO, 0x403cf03, 3, &mmRCC_DEV0_EPF6_STRAP3[0], sizeof(mmRCC_DEV0_EPF6_STRAP3)/sizeof(mmRCC_DEV0_EPF6_STRAP3[0]), 0, 0 }, - { "mmRCC_DEV0_EPF6_STRAP4", REG_MMIO, 0x403cf04, 3, &mmRCC_DEV0_EPF6_STRAP4[0], sizeof(mmRCC_DEV0_EPF6_STRAP4)/sizeof(mmRCC_DEV0_EPF6_STRAP4[0]), 0, 0 }, - { "mmRCC_DEV0_EPF6_STRAP5", REG_MMIO, 0x403cf05, 3, &mmRCC_DEV0_EPF6_STRAP5[0], sizeof(mmRCC_DEV0_EPF6_STRAP5)/sizeof(mmRCC_DEV0_EPF6_STRAP5[0]), 0, 0 }, - { "mmRCC_DEV0_EPF6_STRAP6", REG_MMIO, 0x403cf06, 3, &mmRCC_DEV0_EPF6_STRAP6[0], sizeof(mmRCC_DEV0_EPF6_STRAP6)/sizeof(mmRCC_DEV0_EPF6_STRAP6[0]), 0, 0 }, - { "mmRCC_DEV0_EPF6_STRAP13", REG_MMIO, 0x403cf0d, 3, &mmRCC_DEV0_EPF6_STRAP13[0], sizeof(mmRCC_DEV0_EPF6_STRAP13)/sizeof(mmRCC_DEV0_EPF6_STRAP13[0]), 0, 0 }, - { "mmRCC_DEV0_EPF7_STRAP0", REG_MMIO, 0x403cf80, 3, &mmRCC_DEV0_EPF7_STRAP0[0], sizeof(mmRCC_DEV0_EPF7_STRAP0)/sizeof(mmRCC_DEV0_EPF7_STRAP0[0]), 0, 0 }, - { "mmRCC_DEV0_EPF7_STRAP2", REG_MMIO, 0x403cf82, 3, &mmRCC_DEV0_EPF7_STRAP2[0], sizeof(mmRCC_DEV0_EPF7_STRAP2)/sizeof(mmRCC_DEV0_EPF7_STRAP2[0]), 0, 0 }, - { "mmRCC_DEV0_EPF7_STRAP3", REG_MMIO, 0x403cf83, 3, &mmRCC_DEV0_EPF7_STRAP3[0], sizeof(mmRCC_DEV0_EPF7_STRAP3)/sizeof(mmRCC_DEV0_EPF7_STRAP3[0]), 0, 0 }, - { "mmRCC_DEV0_EPF7_STRAP4", REG_MMIO, 0x403cf84, 3, &mmRCC_DEV0_EPF7_STRAP4[0], sizeof(mmRCC_DEV0_EPF7_STRAP4)/sizeof(mmRCC_DEV0_EPF7_STRAP4[0]), 0, 0 }, - { "mmRCC_DEV0_EPF7_STRAP5", REG_MMIO, 0x403cf85, 3, &mmRCC_DEV0_EPF7_STRAP5[0], sizeof(mmRCC_DEV0_EPF7_STRAP5)/sizeof(mmRCC_DEV0_EPF7_STRAP5[0]), 0, 0 }, - { "mmRCC_DEV0_EPF7_STRAP6", REG_MMIO, 0x403cf86, 3, &mmRCC_DEV0_EPF7_STRAP6[0], sizeof(mmRCC_DEV0_EPF7_STRAP6)/sizeof(mmRCC_DEV0_EPF7_STRAP6[0]), 0, 0 }, - { "mmRCC_DEV0_EPF7_STRAP13", REG_MMIO, 0x403cf8d, 3, &mmRCC_DEV0_EPF7_STRAP13[0], sizeof(mmRCC_DEV0_EPF7_STRAP13)/sizeof(mmRCC_DEV0_EPF7_STRAP13[0]), 0, 0 }, - { "mmRCC_DEV1_EPF0_STRAP0", REG_MMIO, 0x403d000, 3, &mmRCC_DEV1_EPF0_STRAP0[0], sizeof(mmRCC_DEV1_EPF0_STRAP0)/sizeof(mmRCC_DEV1_EPF0_STRAP0[0]), 0, 0 }, - { "mmRCC_DEV1_EPF0_STRAP2", REG_MMIO, 0x403d002, 3, &mmRCC_DEV1_EPF0_STRAP2[0], sizeof(mmRCC_DEV1_EPF0_STRAP2)/sizeof(mmRCC_DEV1_EPF0_STRAP2[0]), 0, 0 }, - { "mmRCC_DEV1_EPF0_STRAP3", REG_MMIO, 0x403d003, 3, &mmRCC_DEV1_EPF0_STRAP3[0], sizeof(mmRCC_DEV1_EPF0_STRAP3)/sizeof(mmRCC_DEV1_EPF0_STRAP3[0]), 0, 0 }, - { "mmRCC_DEV1_EPF0_STRAP4", REG_MMIO, 0x403d004, 3, &mmRCC_DEV1_EPF0_STRAP4[0], sizeof(mmRCC_DEV1_EPF0_STRAP4)/sizeof(mmRCC_DEV1_EPF0_STRAP4[0]), 0, 0 }, - { "mmRCC_DEV1_EPF0_STRAP5", REG_MMIO, 0x403d005, 3, &mmRCC_DEV1_EPF0_STRAP5[0], sizeof(mmRCC_DEV1_EPF0_STRAP5)/sizeof(mmRCC_DEV1_EPF0_STRAP5[0]), 0, 0 }, - { "mmRCC_DEV1_EPF0_STRAP6", REG_MMIO, 0x403d006, 3, &mmRCC_DEV1_EPF0_STRAP6[0], sizeof(mmRCC_DEV1_EPF0_STRAP6)/sizeof(mmRCC_DEV1_EPF0_STRAP6[0]), 0, 0 }, - { "mmRCC_DEV1_EPF0_STRAP13", REG_MMIO, 0x403d00d, 3, &mmRCC_DEV1_EPF0_STRAP13[0], sizeof(mmRCC_DEV1_EPF0_STRAP13)/sizeof(mmRCC_DEV1_EPF0_STRAP13[0]), 0, 0 }, - { "mmRCC_DEV1_EPF1_STRAP0", REG_MMIO, 0x403d080, 3, &mmRCC_DEV1_EPF1_STRAP0[0], sizeof(mmRCC_DEV1_EPF1_STRAP0)/sizeof(mmRCC_DEV1_EPF1_STRAP0[0]), 0, 0 }, - { "mmRCC_DEV1_EPF1_STRAP2", REG_MMIO, 0x403d082, 3, &mmRCC_DEV1_EPF1_STRAP2[0], sizeof(mmRCC_DEV1_EPF1_STRAP2)/sizeof(mmRCC_DEV1_EPF1_STRAP2[0]), 0, 0 }, - { "mmRCC_DEV1_EPF1_STRAP3", REG_MMIO, 0x403d083, 3, &mmRCC_DEV1_EPF1_STRAP3[0], sizeof(mmRCC_DEV1_EPF1_STRAP3)/sizeof(mmRCC_DEV1_EPF1_STRAP3[0]), 0, 0 }, - { "mmRCC_DEV1_EPF1_STRAP4", REG_MMIO, 0x403d084, 3, &mmRCC_DEV1_EPF1_STRAP4[0], sizeof(mmRCC_DEV1_EPF1_STRAP4)/sizeof(mmRCC_DEV1_EPF1_STRAP4[0]), 0, 0 }, - { "mmRCC_DEV1_EPF1_STRAP5", REG_MMIO, 0x403d085, 3, &mmRCC_DEV1_EPF1_STRAP5[0], sizeof(mmRCC_DEV1_EPF1_STRAP5)/sizeof(mmRCC_DEV1_EPF1_STRAP5[0]), 0, 0 }, - { "mmRCC_DEV1_EPF1_STRAP6", REG_MMIO, 0x403d086, 3, &mmRCC_DEV1_EPF1_STRAP6[0], sizeof(mmRCC_DEV1_EPF1_STRAP6)/sizeof(mmRCC_DEV1_EPF1_STRAP6[0]), 0, 0 }, - { "mmRCC_DEV1_EPF1_STRAP13", REG_MMIO, 0x403d08d, 3, &mmRCC_DEV1_EPF1_STRAP13[0], sizeof(mmRCC_DEV1_EPF1_STRAP13)/sizeof(mmRCC_DEV1_EPF1_STRAP13[0]), 0, 0 }, - { "mmRCC_DEV1_EPF2_STRAP0", REG_MMIO, 0x403d100, 3, &mmRCC_DEV1_EPF2_STRAP0[0], sizeof(mmRCC_DEV1_EPF2_STRAP0)/sizeof(mmRCC_DEV1_EPF2_STRAP0[0]), 0, 0 }, - { "mmRCC_DEV1_EPF2_STRAP2", REG_MMIO, 0x403d102, 3, &mmRCC_DEV1_EPF2_STRAP2[0], sizeof(mmRCC_DEV1_EPF2_STRAP2)/sizeof(mmRCC_DEV1_EPF2_STRAP2[0]), 0, 0 }, - { "mmRCC_DEV1_EPF2_STRAP3", REG_MMIO, 0x403d103, 3, &mmRCC_DEV1_EPF2_STRAP3[0], sizeof(mmRCC_DEV1_EPF2_STRAP3)/sizeof(mmRCC_DEV1_EPF2_STRAP3[0]), 0, 0 }, - { "mmRCC_DEV1_EPF2_STRAP4", REG_MMIO, 0x403d104, 3, &mmRCC_DEV1_EPF2_STRAP4[0], sizeof(mmRCC_DEV1_EPF2_STRAP4)/sizeof(mmRCC_DEV1_EPF2_STRAP4[0]), 0, 0 }, - { "mmRCC_DEV1_EPF2_STRAP5", REG_MMIO, 0x403d105, 3, &mmRCC_DEV1_EPF2_STRAP5[0], sizeof(mmRCC_DEV1_EPF2_STRAP5)/sizeof(mmRCC_DEV1_EPF2_STRAP5[0]), 0, 0 }, - { "mmRCC_DEV1_EPF2_STRAP6", REG_MMIO, 0x403d106, 3, &mmRCC_DEV1_EPF2_STRAP6[0], sizeof(mmRCC_DEV1_EPF2_STRAP6)/sizeof(mmRCC_DEV1_EPF2_STRAP6[0]), 0, 0 }, - { "mmRCC_DEV1_EPF2_STRAP13", REG_MMIO, 0x403d10d, 3, &mmRCC_DEV1_EPF2_STRAP13[0], sizeof(mmRCC_DEV1_EPF2_STRAP13)/sizeof(mmRCC_DEV1_EPF2_STRAP13[0]), 0, 0 }, - { "ixHARD_RST_CTRL", REG_SMC, 0x38000, 0, &ixHARD_RST_CTRL[0], sizeof(ixHARD_RST_CTRL)/sizeof(ixHARD_RST_CTRL[0]), 0, 0 }, - { "ixRSMU_SOFT_RST_CTRL", REG_SMC, 0x38004, 0, &ixRSMU_SOFT_RST_CTRL[0], sizeof(ixRSMU_SOFT_RST_CTRL)/sizeof(ixRSMU_SOFT_RST_CTRL[0]), 0, 0 }, - { "ixSELF_SOFT_RST", REG_SMC, 0x38008, 0, &ixSELF_SOFT_RST[0], sizeof(ixSELF_SOFT_RST)/sizeof(ixSELF_SOFT_RST[0]), 0, 0 }, - { "ixGFX_DRV_MODE1_RST_CTRL", REG_SMC, 0x3800c, 0, &ixGFX_DRV_MODE1_RST_CTRL[0], sizeof(ixGFX_DRV_MODE1_RST_CTRL)/sizeof(ixGFX_DRV_MODE1_RST_CTRL[0]), 0, 0 }, - { "ixBIF_RST_MISC_CTRL", REG_SMC, 0x38010, 0, &ixBIF_RST_MISC_CTRL[0], sizeof(ixBIF_RST_MISC_CTRL)/sizeof(ixBIF_RST_MISC_CTRL[0]), 0, 0 }, - { "ixBIF_RST_MISC_CTRL2", REG_SMC, 0x38014, 0, &ixBIF_RST_MISC_CTRL2[0], sizeof(ixBIF_RST_MISC_CTRL2)/sizeof(ixBIF_RST_MISC_CTRL2[0]), 0, 0 }, - { "ixBIF_RST_MISC_CTRL3", REG_SMC, 0x38018, 0, &ixBIF_RST_MISC_CTRL3[0], sizeof(ixBIF_RST_MISC_CTRL3)/sizeof(ixBIF_RST_MISC_CTRL3[0]), 0, 0 }, - { "ixBIF_RST_GFXVF_FLR_IDLE", REG_SMC, 0x3801c, 0, &ixBIF_RST_GFXVF_FLR_IDLE[0], sizeof(ixBIF_RST_GFXVF_FLR_IDLE)/sizeof(ixBIF_RST_GFXVF_FLR_IDLE[0]), 0, 0 }, - { "ixDEV0_PF0_FLR_RST_CTRL", REG_SMC, 0x38020, 0, &ixDEV0_PF0_FLR_RST_CTRL[0], sizeof(ixDEV0_PF0_FLR_RST_CTRL)/sizeof(ixDEV0_PF0_FLR_RST_CTRL[0]), 0, 0 }, - { "ixDEV0_PF1_FLR_RST_CTRL", REG_SMC, 0x38024, 0, &ixDEV0_PF1_FLR_RST_CTRL[0], sizeof(ixDEV0_PF1_FLR_RST_CTRL)/sizeof(ixDEV0_PF1_FLR_RST_CTRL[0]), 0, 0 }, - { "ixDEV0_PF2_FLR_RST_CTRL", REG_SMC, 0x38028, 0, &ixDEV0_PF2_FLR_RST_CTRL[0], sizeof(ixDEV0_PF2_FLR_RST_CTRL)/sizeof(ixDEV0_PF2_FLR_RST_CTRL[0]), 0, 0 }, - { "ixDEV0_PF3_FLR_RST_CTRL", REG_SMC, 0x3802c, 0, &ixDEV0_PF3_FLR_RST_CTRL[0], sizeof(ixDEV0_PF3_FLR_RST_CTRL)/sizeof(ixDEV0_PF3_FLR_RST_CTRL[0]), 0, 0 }, - { "ixDEV0_PF4_FLR_RST_CTRL", REG_SMC, 0x38030, 0, &ixDEV0_PF4_FLR_RST_CTRL[0], sizeof(ixDEV0_PF4_FLR_RST_CTRL)/sizeof(ixDEV0_PF4_FLR_RST_CTRL[0]), 0, 0 }, - { "ixDEV0_PF5_FLR_RST_CTRL", REG_SMC, 0x38034, 0, &ixDEV0_PF5_FLR_RST_CTRL[0], sizeof(ixDEV0_PF5_FLR_RST_CTRL)/sizeof(ixDEV0_PF5_FLR_RST_CTRL[0]), 0, 0 }, - { "ixDEV0_PF6_FLR_RST_CTRL", REG_SMC, 0x38038, 0, &ixDEV0_PF6_FLR_RST_CTRL[0], sizeof(ixDEV0_PF6_FLR_RST_CTRL)/sizeof(ixDEV0_PF6_FLR_RST_CTRL[0]), 0, 0 }, - { "ixDEV0_PF7_FLR_RST_CTRL", REG_SMC, 0x3803c, 0, &ixDEV0_PF7_FLR_RST_CTRL[0], sizeof(ixDEV0_PF7_FLR_RST_CTRL)/sizeof(ixDEV0_PF7_FLR_RST_CTRL[0]), 0, 0 }, - { "ixBIF_INST_RESET_INTR_STS", REG_SMC, 0x38040, 0, &ixBIF_INST_RESET_INTR_STS[0], sizeof(ixBIF_INST_RESET_INTR_STS)/sizeof(ixBIF_INST_RESET_INTR_STS[0]), 0, 0 }, - { "ixBIF_PF_FLR_INTR_STS", REG_SMC, 0x38044, 0, &ixBIF_PF_FLR_INTR_STS[0], sizeof(ixBIF_PF_FLR_INTR_STS)/sizeof(ixBIF_PF_FLR_INTR_STS[0]), 0, 0 }, - { "ixBIF_D3HOTD0_INTR_STS", REG_SMC, 0x38048, 0, &ixBIF_D3HOTD0_INTR_STS[0], sizeof(ixBIF_D3HOTD0_INTR_STS)/sizeof(ixBIF_D3HOTD0_INTR_STS[0]), 0, 0 }, - { "ixBIF_POWER_INTR_STS", REG_SMC, 0x38050, 0, &ixBIF_POWER_INTR_STS[0], sizeof(ixBIF_POWER_INTR_STS)/sizeof(ixBIF_POWER_INTR_STS[0]), 0, 0 }, - { "ixBIF_PF_DSTATE_INTR_STS", REG_SMC, 0x38054, 0, &ixBIF_PF_DSTATE_INTR_STS[0], sizeof(ixBIF_PF_DSTATE_INTR_STS)/sizeof(ixBIF_PF_DSTATE_INTR_STS[0]), 0, 0 }, - { "ixBIF_PF0_VF_FLR_INTR_STS", REG_SMC, 0x38060, 0, &ixBIF_PF0_VF_FLR_INTR_STS[0], sizeof(ixBIF_PF0_VF_FLR_INTR_STS)/sizeof(ixBIF_PF0_VF_FLR_INTR_STS[0]), 0, 0 }, - { "ixBIF_INST_RESET_INTR_MASK", REG_SMC, 0x38080, 0, &ixBIF_INST_RESET_INTR_MASK[0], sizeof(ixBIF_INST_RESET_INTR_MASK)/sizeof(ixBIF_INST_RESET_INTR_MASK[0]), 0, 0 }, - { "ixBIF_PF_FLR_INTR_MASK", REG_SMC, 0x38084, 0, &ixBIF_PF_FLR_INTR_MASK[0], sizeof(ixBIF_PF_FLR_INTR_MASK)/sizeof(ixBIF_PF_FLR_INTR_MASK[0]), 0, 0 }, - { "ixBIF_D3HOTD0_INTR_MASK", REG_SMC, 0x38088, 0, &ixBIF_D3HOTD0_INTR_MASK[0], sizeof(ixBIF_D3HOTD0_INTR_MASK)/sizeof(ixBIF_D3HOTD0_INTR_MASK[0]), 0, 0 }, - { "ixBIF_POWER_INTR_MASK", REG_SMC, 0x38090, 0, &ixBIF_POWER_INTR_MASK[0], sizeof(ixBIF_POWER_INTR_MASK)/sizeof(ixBIF_POWER_INTR_MASK[0]), 0, 0 }, - { "ixBIF_PF_DSTATE_INTR_MASK", REG_SMC, 0x38094, 0, &ixBIF_PF_DSTATE_INTR_MASK[0], sizeof(ixBIF_PF_DSTATE_INTR_MASK)/sizeof(ixBIF_PF_DSTATE_INTR_MASK[0]), 0, 0 }, - { "ixBIF_PF0_VF_FLR_INTR_MASK", REG_SMC, 0x380a0, 0, &ixBIF_PF0_VF_FLR_INTR_MASK[0], sizeof(ixBIF_PF0_VF_FLR_INTR_MASK)/sizeof(ixBIF_PF0_VF_FLR_INTR_MASK[0]), 0, 0 }, - { "ixBIF_PF_FLR_RST", REG_SMC, 0x38100, 0, &ixBIF_PF_FLR_RST[0], sizeof(ixBIF_PF_FLR_RST)/sizeof(ixBIF_PF_FLR_RST[0]), 0, 0 }, - { "ixBIF_PF0_VF_FLR_RST", REG_SMC, 0x38120, 0, &ixBIF_PF0_VF_FLR_RST[0], sizeof(ixBIF_PF0_VF_FLR_RST)/sizeof(ixBIF_PF0_VF_FLR_RST[0]), 0, 0 }, - { "ixBIF_DEV0_PF0_DSTATE_VALUE", REG_SMC, 0x38140, 0, &ixBIF_DEV0_PF0_DSTATE_VALUE[0], sizeof(ixBIF_DEV0_PF0_DSTATE_VALUE)/sizeof(ixBIF_DEV0_PF0_DSTATE_VALUE[0]), 0, 0 }, - { "ixBIF_DEV0_PF1_DSTATE_VALUE", REG_SMC, 0x38144, 0, &ixBIF_DEV0_PF1_DSTATE_VALUE[0], sizeof(ixBIF_DEV0_PF1_DSTATE_VALUE)/sizeof(ixBIF_DEV0_PF1_DSTATE_VALUE[0]), 0, 0 }, - { "ixBIF_DEV0_PF2_DSTATE_VALUE", REG_SMC, 0x38148, 0, &ixBIF_DEV0_PF2_DSTATE_VALUE[0], sizeof(ixBIF_DEV0_PF2_DSTATE_VALUE)/sizeof(ixBIF_DEV0_PF2_DSTATE_VALUE[0]), 0, 0 }, - { "ixBIF_DEV0_PF3_DSTATE_VALUE", REG_SMC, 0x3814c, 0, &ixBIF_DEV0_PF3_DSTATE_VALUE[0], sizeof(ixBIF_DEV0_PF3_DSTATE_VALUE)/sizeof(ixBIF_DEV0_PF3_DSTATE_VALUE[0]), 0, 0 }, - { "ixBIF_DEV0_PF4_DSTATE_VALUE", REG_SMC, 0x38150, 0, &ixBIF_DEV0_PF4_DSTATE_VALUE[0], sizeof(ixBIF_DEV0_PF4_DSTATE_VALUE)/sizeof(ixBIF_DEV0_PF4_DSTATE_VALUE[0]), 0, 0 }, - { "ixBIF_DEV0_PF5_DSTATE_VALUE", REG_SMC, 0x38154, 0, &ixBIF_DEV0_PF5_DSTATE_VALUE[0], sizeof(ixBIF_DEV0_PF5_DSTATE_VALUE)/sizeof(ixBIF_DEV0_PF5_DSTATE_VALUE[0]), 0, 0 }, - { "ixBIF_DEV0_PF6_DSTATE_VALUE", REG_SMC, 0x38158, 0, &ixBIF_DEV0_PF6_DSTATE_VALUE[0], sizeof(ixBIF_DEV0_PF6_DSTATE_VALUE)/sizeof(ixBIF_DEV0_PF6_DSTATE_VALUE[0]), 0, 0 }, - { "ixBIF_DEV0_PF7_DSTATE_VALUE", REG_SMC, 0x3815c, 0, &ixBIF_DEV0_PF7_DSTATE_VALUE[0], sizeof(ixBIF_DEV0_PF7_DSTATE_VALUE)/sizeof(ixBIF_DEV0_PF7_DSTATE_VALUE[0]), 0, 0 }, - { "ixDEV0_PF0_D3HOTD0_RST_CTRL", REG_SMC, 0x381e0, 0, &ixDEV0_PF0_D3HOTD0_RST_CTRL[0], sizeof(ixDEV0_PF0_D3HOTD0_RST_CTRL)/sizeof(ixDEV0_PF0_D3HOTD0_RST_CTRL[0]), 0, 0 }, - { "ixDEV0_PF1_D3HOTD0_RST_CTRL", REG_SMC, 0x381e4, 0, &ixDEV0_PF1_D3HOTD0_RST_CTRL[0], sizeof(ixDEV0_PF1_D3HOTD0_RST_CTRL)/sizeof(ixDEV0_PF1_D3HOTD0_RST_CTRL[0]), 0, 0 }, - { "ixDEV0_PF2_D3HOTD0_RST_CTRL", REG_SMC, 0x381e8, 0, &ixDEV0_PF2_D3HOTD0_RST_CTRL[0], sizeof(ixDEV0_PF2_D3HOTD0_RST_CTRL)/sizeof(ixDEV0_PF2_D3HOTD0_RST_CTRL[0]), 0, 0 }, - { "ixDEV0_PF3_D3HOTD0_RST_CTRL", REG_SMC, 0x381ec, 0, &ixDEV0_PF3_D3HOTD0_RST_CTRL[0], sizeof(ixDEV0_PF3_D3HOTD0_RST_CTRL)/sizeof(ixDEV0_PF3_D3HOTD0_RST_CTRL[0]), 0, 0 }, - { "ixDEV0_PF4_D3HOTD0_RST_CTRL", REG_SMC, 0x381f0, 0, &ixDEV0_PF4_D3HOTD0_RST_CTRL[0], sizeof(ixDEV0_PF4_D3HOTD0_RST_CTRL)/sizeof(ixDEV0_PF4_D3HOTD0_RST_CTRL[0]), 0, 0 }, - { "ixDEV0_PF5_D3HOTD0_RST_CTRL", REG_SMC, 0x381f4, 0, &ixDEV0_PF5_D3HOTD0_RST_CTRL[0], sizeof(ixDEV0_PF5_D3HOTD0_RST_CTRL)/sizeof(ixDEV0_PF5_D3HOTD0_RST_CTRL[0]), 0, 0 }, - { "ixDEV0_PF6_D3HOTD0_RST_CTRL", REG_SMC, 0x381f8, 0, &ixDEV0_PF6_D3HOTD0_RST_CTRL[0], sizeof(ixDEV0_PF6_D3HOTD0_RST_CTRL)/sizeof(ixDEV0_PF6_D3HOTD0_RST_CTRL[0]), 0, 0 }, - { "ixDEV0_PF7_D3HOTD0_RST_CTRL", REG_SMC, 0x381fc, 0, &ixDEV0_PF7_D3HOTD0_RST_CTRL[0], sizeof(ixDEV0_PF7_D3HOTD0_RST_CTRL)/sizeof(ixDEV0_PF7_D3HOTD0_RST_CTRL[0]), 0, 0 }, - { "ixBIF_PORT0_DSTATE_VALUE", REG_SMC, 0x388c0, 0, &ixBIF_PORT0_DSTATE_VALUE[0], sizeof(ixBIF_PORT0_DSTATE_VALUE)/sizeof(ixBIF_PORT0_DSTATE_VALUE[0]), 0, 0 }, - { "ixMISC_SCRATCH", REG_SMC, 0x3a000, 0, &ixMISC_SCRATCH[0], sizeof(ixMISC_SCRATCH)/sizeof(ixMISC_SCRATCH[0]), 0, 0 }, - { "ixINTR_LINE_POLARITY", REG_SMC, 0x3a004, 0, &ixINTR_LINE_POLARITY[0], sizeof(ixINTR_LINE_POLARITY)/sizeof(ixINTR_LINE_POLARITY[0]), 0, 0 }, - { "ixINTR_LINE_ENABLE", REG_SMC, 0x3a008, 0, &ixINTR_LINE_ENABLE[0], sizeof(ixINTR_LINE_ENABLE)/sizeof(ixINTR_LINE_ENABLE[0]), 0, 0 }, - { "ixOUTSTANDING_VC_ALLOC", REG_SMC, 0x3a00c, 0, &ixOUTSTANDING_VC_ALLOC[0], sizeof(ixOUTSTANDING_VC_ALLOC)/sizeof(ixOUTSTANDING_VC_ALLOC[0]), 0, 0 }, - { "ixBIFC_MISC_CTRL0", REG_SMC, 0x3a010, 0, &ixBIFC_MISC_CTRL0[0], sizeof(ixBIFC_MISC_CTRL0)/sizeof(ixBIFC_MISC_CTRL0[0]), 0, 0 }, - { "ixBIFC_MISC_CTRL1", REG_SMC, 0x3a014, 0, &ixBIFC_MISC_CTRL1[0], sizeof(ixBIFC_MISC_CTRL1)/sizeof(ixBIFC_MISC_CTRL1[0]), 0, 0 }, - { "ixBIFC_BME_ERR_LOG", REG_SMC, 0x3a018, 0, &ixBIFC_BME_ERR_LOG[0], sizeof(ixBIFC_BME_ERR_LOG)/sizeof(ixBIFC_BME_ERR_LOG[0]), 0, 0 }, - { "ixBIFC_RCCBIH_BME_ERR_LOG", REG_SMC, 0x3a01c, 0, &ixBIFC_RCCBIH_BME_ERR_LOG[0], sizeof(ixBIFC_RCCBIH_BME_ERR_LOG)/sizeof(ixBIFC_RCCBIH_BME_ERR_LOG[0]), 0, 0 }, - { "ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1", REG_SMC, 0x3a020, 0, &ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1[0], sizeof(ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1)/sizeof(ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1[0]), 0, 0 }, - { "ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3", REG_SMC, 0x3a024, 0, &ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3[0], sizeof(ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3)/sizeof(ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3[0]), 0, 0 }, - { "ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5", REG_SMC, 0x3a028, 0, &ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5[0], sizeof(ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5)/sizeof(ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5[0]), 0, 0 }, - { "ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7", REG_SMC, 0x3a02c, 0, &ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7[0], sizeof(ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7)/sizeof(ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7[0]), 0, 0 }, - { "ixNBIF_VWIRE_CTRL", REG_SMC, 0x3a040, 0, &ixNBIF_VWIRE_CTRL[0], sizeof(ixNBIF_VWIRE_CTRL)/sizeof(ixNBIF_VWIRE_CTRL[0]), 0, 0 }, - { "ixNBIF_SMN_VWR_VCHG_DIS_CTRL", REG_SMC, 0x3a044, 0, &ixNBIF_SMN_VWR_VCHG_DIS_CTRL[0], sizeof(ixNBIF_SMN_VWR_VCHG_DIS_CTRL)/sizeof(ixNBIF_SMN_VWR_VCHG_DIS_CTRL[0]), 0, 0 }, - { "ixNBIF_SMN_VWR_VCHG_RST_CTRL0", REG_SMC, 0x3a048, 0, &ixNBIF_SMN_VWR_VCHG_RST_CTRL0[0], sizeof(ixNBIF_SMN_VWR_VCHG_RST_CTRL0)/sizeof(ixNBIF_SMN_VWR_VCHG_RST_CTRL0[0]), 0, 0 }, - { "ixNBIF_SMN_VWR_VCHG_TRIG", REG_SMC, 0x3a050, 0, &ixNBIF_SMN_VWR_VCHG_TRIG[0], sizeof(ixNBIF_SMN_VWR_VCHG_TRIG)/sizeof(ixNBIF_SMN_VWR_VCHG_TRIG[0]), 0, 0 }, - { "ixNBIF_SMN_VWR_WTRIG_CNTL", REG_SMC, 0x3a054, 0, &ixNBIF_SMN_VWR_WTRIG_CNTL[0], sizeof(ixNBIF_SMN_VWR_WTRIG_CNTL)/sizeof(ixNBIF_SMN_VWR_WTRIG_CNTL[0]), 0, 0 }, - { "ixNBIF_SMN_VWR_VCHG_DIS_CTRL_1", REG_SMC, 0x3a058, 0, &ixNBIF_SMN_VWR_VCHG_DIS_CTRL_1[0], sizeof(ixNBIF_SMN_VWR_VCHG_DIS_CTRL_1)/sizeof(ixNBIF_SMN_VWR_VCHG_DIS_CTRL_1[0]), 0, 0 }, - { "ixNBIF_MGCG_CTRL", REG_SMC, 0x3a05c, 0, &ixNBIF_MGCG_CTRL[0], sizeof(ixNBIF_MGCG_CTRL)/sizeof(ixNBIF_MGCG_CTRL[0]), 0, 0 }, - { "ixNBIF_DS_CTRL_LCLK", REG_SMC, 0x3a060, 0, &ixNBIF_DS_CTRL_LCLK[0], sizeof(ixNBIF_DS_CTRL_LCLK)/sizeof(ixNBIF_DS_CTRL_LCLK[0]), 0, 0 }, - { "ixSMN_MST_CNTL0", REG_SMC, 0x3a064, 0, &ixSMN_MST_CNTL0[0], sizeof(ixSMN_MST_CNTL0)/sizeof(ixSMN_MST_CNTL0[0]), 0, 0 }, - { "ixSMN_MST_EP_CNTL1", REG_SMC, 0x3a068, 0, &ixSMN_MST_EP_CNTL1[0], sizeof(ixSMN_MST_EP_CNTL1)/sizeof(ixSMN_MST_EP_CNTL1[0]), 0, 0 }, - { "ixSMN_MST_EP_CNTL2", REG_SMC, 0x3a06c, 0, &ixSMN_MST_EP_CNTL2[0], sizeof(ixSMN_MST_EP_CNTL2)/sizeof(ixSMN_MST_EP_CNTL2[0]), 0, 0 }, - { "ixNBIF_SDP_VWR_VCHG_DIS_CTRL", REG_SMC, 0x3a070, 0, &ixNBIF_SDP_VWR_VCHG_DIS_CTRL[0], sizeof(ixNBIF_SDP_VWR_VCHG_DIS_CTRL)/sizeof(ixNBIF_SDP_VWR_VCHG_DIS_CTRL[0]), 0, 0 }, - { "ixNBIF_SDP_VWR_VCHG_RST_CTRL0", REG_SMC, 0x3a074, 0, &ixNBIF_SDP_VWR_VCHG_RST_CTRL0[0], sizeof(ixNBIF_SDP_VWR_VCHG_RST_CTRL0)/sizeof(ixNBIF_SDP_VWR_VCHG_RST_CTRL0[0]), 0, 0 }, - { "ixNBIF_SDP_VWR_VCHG_RST_CTRL1", REG_SMC, 0x3a078, 0, &ixNBIF_SDP_VWR_VCHG_RST_CTRL1[0], sizeof(ixNBIF_SDP_VWR_VCHG_RST_CTRL1)/sizeof(ixNBIF_SDP_VWR_VCHG_RST_CTRL1[0]), 0, 0 }, - { "ixNBIF_SDP_VWR_VCHG_TRIG", REG_SMC, 0x3a07c, 0, &ixNBIF_SDP_VWR_VCHG_TRIG[0], sizeof(ixNBIF_SDP_VWR_VCHG_TRIG)/sizeof(ixNBIF_SDP_VWR_VCHG_TRIG[0]), 0, 0 }, - { "ixBME_DUMMY_CNTL_0", REG_SMC, 0x3a098, 0, &ixBME_DUMMY_CNTL_0[0], sizeof(ixBME_DUMMY_CNTL_0)/sizeof(ixBME_DUMMY_CNTL_0[0]), 0, 0 }, - { "ixBIFC_THT_CNTL", REG_SMC, 0x3a09c, 0, &ixBIFC_THT_CNTL[0], sizeof(ixBIFC_THT_CNTL)/sizeof(ixBIFC_THT_CNTL[0]), 0, 0 }, - { "ixBIFC_HSTARB_CNTL", REG_SMC, 0x3a0a0, 0, &ixBIFC_HSTARB_CNTL[0], sizeof(ixBIFC_HSTARB_CNTL)/sizeof(ixBIFC_HSTARB_CNTL[0]), 0, 0 }, - { "ixBIFC_GSI_CNTL", REG_SMC, 0x3a0a4, 0, &ixBIFC_GSI_CNTL[0], sizeof(ixBIFC_GSI_CNTL)/sizeof(ixBIFC_GSI_CNTL[0]), 0, 0 }, - { "ixBIFC_PCIEFUNC_CNTL", REG_SMC, 0x3a0a8, 0, &ixBIFC_PCIEFUNC_CNTL[0], sizeof(ixBIFC_PCIEFUNC_CNTL)/sizeof(ixBIFC_PCIEFUNC_CNTL[0]), 0, 0 }, - { "ixBIFC_SDP_CNTL_0", REG_SMC, 0x3a0b0, 0, &ixBIFC_SDP_CNTL_0[0], sizeof(ixBIFC_SDP_CNTL_0)/sizeof(ixBIFC_SDP_CNTL_0[0]), 0, 0 }, - { "ixBIFC_PERF_CNTL_0", REG_SMC, 0x3a0c0, 0, &ixBIFC_PERF_CNTL_0[0], sizeof(ixBIFC_PERF_CNTL_0)/sizeof(ixBIFC_PERF_CNTL_0[0]), 0, 0 }, - { "ixBIFC_PERF_CNTL_1", REG_SMC, 0x3a0c4, 0, &ixBIFC_PERF_CNTL_1[0], sizeof(ixBIFC_PERF_CNTL_1)/sizeof(ixBIFC_PERF_CNTL_1[0]), 0, 0 }, - { "ixBIFC_PERF_CNT_MMIO_RD", REG_SMC, 0x3a0c8, 0, &ixBIFC_PERF_CNT_MMIO_RD[0], sizeof(ixBIFC_PERF_CNT_MMIO_RD)/sizeof(ixBIFC_PERF_CNT_MMIO_RD[0]), 0, 0 }, - { "ixBIFC_PERF_CNT_MMIO_WR", REG_SMC, 0x3a0cc, 0, &ixBIFC_PERF_CNT_MMIO_WR[0], sizeof(ixBIFC_PERF_CNT_MMIO_WR)/sizeof(ixBIFC_PERF_CNT_MMIO_WR[0]), 0, 0 }, - { "ixBIFC_PERF_CNT_DMA_RD", REG_SMC, 0x3a0d0, 0, &ixBIFC_PERF_CNT_DMA_RD[0], sizeof(ixBIFC_PERF_CNT_DMA_RD)/sizeof(ixBIFC_PERF_CNT_DMA_RD[0]), 0, 0 }, - { "ixBIFC_PERF_CNT_DMA_WR", REG_SMC, 0x3a0d4, 0, &ixBIFC_PERF_CNT_DMA_WR[0], sizeof(ixBIFC_PERF_CNT_DMA_WR)/sizeof(ixBIFC_PERF_CNT_DMA_WR[0]), 0, 0 }, - { "ixNBIF_REGIF_ERRSET_CTRL", REG_SMC, 0x3a0d8, 0, &ixNBIF_REGIF_ERRSET_CTRL[0], sizeof(ixNBIF_REGIF_ERRSET_CTRL)/sizeof(ixNBIF_REGIF_ERRSET_CTRL[0]), 0, 0 }, - { "ixSMN_MST_EP_CNTL3", REG_SMC, 0x3a0f0, 0, &ixSMN_MST_EP_CNTL3[0], sizeof(ixSMN_MST_EP_CNTL3)/sizeof(ixSMN_MST_EP_CNTL3[0]), 0, 0 }, - { "ixSMN_MST_EP_CNTL4", REG_SMC, 0x3a0f4, 0, &ixSMN_MST_EP_CNTL4[0], sizeof(ixSMN_MST_EP_CNTL4)/sizeof(ixSMN_MST_EP_CNTL4[0]), 0, 0 }, - { "ixBIF_SELFRING_BUFFER_VID", REG_SMC, 0x3a100, 0, &ixBIF_SELFRING_BUFFER_VID[0], sizeof(ixBIF_SELFRING_BUFFER_VID)/sizeof(ixBIF_SELFRING_BUFFER_VID[0]), 0, 0 }, - { "ixBIF_SELFRING_VECTOR_CNTL", REG_SMC, 0x3a104, 0, &ixBIF_SELFRING_VECTOR_CNTL[0], sizeof(ixBIF_SELFRING_VECTOR_CNTL)/sizeof(ixBIF_SELFRING_VECTOR_CNTL[0]), 0, 0 }, - { "ixBIF_RAS_LEAF0_CTRL", REG_SMC, 0x39000, 0, &ixBIF_RAS_LEAF0_CTRL[0], sizeof(ixBIF_RAS_LEAF0_CTRL)/sizeof(ixBIF_RAS_LEAF0_CTRL[0]), 0, 0 }, - { "ixBIF_RAS_LEAF1_CTRL", REG_SMC, 0x39004, 0, &ixBIF_RAS_LEAF1_CTRL[0], sizeof(ixBIF_RAS_LEAF1_CTRL)/sizeof(ixBIF_RAS_LEAF1_CTRL[0]), 0, 0 }, - { "ixBIF_RAS_LEAF2_CTRL", REG_SMC, 0x39008, 0, &ixBIF_RAS_LEAF2_CTRL[0], sizeof(ixBIF_RAS_LEAF2_CTRL)/sizeof(ixBIF_RAS_LEAF2_CTRL[0]), 0, 0 }, - { "ixBIF_RAS_MISC_CTRL", REG_SMC, 0x39100, 0, &ixBIF_RAS_MISC_CTRL[0], sizeof(ixBIF_RAS_MISC_CTRL)/sizeof(ixBIF_RAS_MISC_CTRL[0]), 0, 0 }, - { "ixBIF_IOHUB_RAS_IH_CNTL", REG_SMC, 0x39ff8, 0, &ixBIF_IOHUB_RAS_IH_CNTL[0], sizeof(ixBIF_IOHUB_RAS_IH_CNTL)/sizeof(ixBIF_IOHUB_RAS_IH_CNTL[0]), 0, 0 }, - { "ixBIF_RAS_VWR_FROM_IOHUB", REG_SMC, 0x39ffc, 0, &ixBIF_RAS_VWR_FROM_IOHUB[0], sizeof(ixBIF_RAS_VWR_FROM_IOHUB)/sizeof(ixBIF_RAS_VWR_FROM_IOHUB[0]), 0, 0 }, - { "ixRCC_PFC_LTR_CNTL", REG_SMC, 0x0100, 0, &ixRCC_PFC_LTR_CNTL[0], sizeof(ixRCC_PFC_LTR_CNTL)/sizeof(ixRCC_PFC_LTR_CNTL[0]), 0, 0 }, - { "ixRCC_PFC_PME_RESTORE", REG_SMC, 0x0104, 0, &ixRCC_PFC_PME_RESTORE[0], sizeof(ixRCC_PFC_PME_RESTORE)/sizeof(ixRCC_PFC_PME_RESTORE[0]), 0, 0 }, - { "ixRCC_PFC_STICKY_RESTORE_0", REG_SMC, 0x0108, 0, &ixRCC_PFC_STICKY_RESTORE_0[0], sizeof(ixRCC_PFC_STICKY_RESTORE_0)/sizeof(ixRCC_PFC_STICKY_RESTORE_0[0]), 0, 0 }, - { "ixRCC_PFC_STICKY_RESTORE_1", REG_SMC, 0x010c, 0, &ixRCC_PFC_STICKY_RESTORE_1[0], sizeof(ixRCC_PFC_STICKY_RESTORE_1)/sizeof(ixRCC_PFC_STICKY_RESTORE_1[0]), 0, 0 }, - { "ixRCC_PFC_STICKY_RESTORE_2", REG_SMC, 0x0110, 0, &ixRCC_PFC_STICKY_RESTORE_2[0], sizeof(ixRCC_PFC_STICKY_RESTORE_2)/sizeof(ixRCC_PFC_STICKY_RESTORE_2[0]), 0, 0 }, - { "ixRCC_PFC_STICKY_RESTORE_3", REG_SMC, 0x0114, 0, &ixRCC_PFC_STICKY_RESTORE_3[0], sizeof(ixRCC_PFC_STICKY_RESTORE_3)/sizeof(ixRCC_PFC_STICKY_RESTORE_3[0]), 0, 0 }, - { "ixRCC_PFC_STICKY_RESTORE_4", REG_SMC, 0x0118, 0, &ixRCC_PFC_STICKY_RESTORE_4[0], sizeof(ixRCC_PFC_STICKY_RESTORE_4)/sizeof(ixRCC_PFC_STICKY_RESTORE_4[0]), 0, 0 }, - { "ixRCC_PFC_STICKY_RESTORE_5", REG_SMC, 0x011c, 0, &ixRCC_PFC_STICKY_RESTORE_5[0], sizeof(ixRCC_PFC_STICKY_RESTORE_5)/sizeof(ixRCC_PFC_STICKY_RESTORE_5[0]), 0, 0 }, - { "ixRCC_PFC_AUXPWR_CNTL", REG_SMC, 0x0120, 0, &ixRCC_PFC_AUXPWR_CNTL[0], sizeof(ixRCC_PFC_AUXPWR_CNTL)/sizeof(ixRCC_PFC_AUXPWR_CNTL[0]), 0, 0 }, - { "ixRCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL", REG_SMC, 0x0100, 0, &ixRCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL[0], sizeof(ixRCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL)/sizeof(ixRCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL[0]), 0, 0 }, - { "ixRCCPFCAMDGFXAZ_RCC_PFC_PME_RESTORE", REG_SMC, 0x0104, 0, &ixRCCPFCAMDGFXAZ_RCC_PFC_PME_RESTORE[0], sizeof(ixRCCPFCAMDGFXAZ_RCC_PFC_PME_RESTORE)/sizeof(ixRCCPFCAMDGFXAZ_RCC_PFC_PME_RESTORE[0]), 0, 0 }, - { "ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0", REG_SMC, 0x0108, 0, &ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0[0], sizeof(ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0)/sizeof(ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0[0]), 0, 0 }, - { "ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_1", REG_SMC, 0x010c, 0, &ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_1[0], sizeof(ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_1)/sizeof(ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_1[0]), 0, 0 }, - { "ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_2", REG_SMC, 0x0110, 0, &ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_2[0], sizeof(ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_2)/sizeof(ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_2[0]), 0, 0 }, - { "ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_3", REG_SMC, 0x0114, 0, &ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_3[0], sizeof(ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_3)/sizeof(ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_3[0]), 0, 0 }, - { "ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_4", REG_SMC, 0x0118, 0, &ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_4[0], sizeof(ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_4)/sizeof(ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_4[0]), 0, 0 }, - { "ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_5", REG_SMC, 0x011c, 0, &ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_5[0], sizeof(ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_5)/sizeof(ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_5[0]), 0, 0 }, - { "ixRCCPFCAMDGFXAZ_RCC_PFC_AUXPWR_CNTL", REG_SMC, 0x0120, 0, &ixRCCPFCAMDGFXAZ_RCC_PFC_AUXPWR_CNTL[0], sizeof(ixRCCPFCAMDGFXAZ_RCC_PFC_AUXPWR_CNTL)/sizeof(ixRCCPFCAMDGFXAZ_RCC_PFC_AUXPWR_CNTL[0]), 0, 0 }, - { "ixPCIEMSIX_VECT0_ADDR_LO", REG_SMC, 0x0000, 0, &ixPCIEMSIX_VECT0_ADDR_LO[0], sizeof(ixPCIEMSIX_VECT0_ADDR_LO)/sizeof(ixPCIEMSIX_VECT0_ADDR_LO[0]), 0, 0 }, - { "ixPCIEMSIX_VECT0_ADDR_HI", REG_SMC, 0x0004, 0, &ixPCIEMSIX_VECT0_ADDR_HI[0], sizeof(ixPCIEMSIX_VECT0_ADDR_HI)/sizeof(ixPCIEMSIX_VECT0_ADDR_HI[0]), 0, 0 }, - { "ixPCIEMSIX_VECT0_MSG_DATA", REG_SMC, 0x0008, 0, &ixPCIEMSIX_VECT0_MSG_DATA[0], sizeof(ixPCIEMSIX_VECT0_MSG_DATA)/sizeof(ixPCIEMSIX_VECT0_MSG_DATA[0]), 0, 0 }, - { "ixPCIEMSIX_VECT0_CONTROL", REG_SMC, 0x000c, 0, &ixPCIEMSIX_VECT0_CONTROL[0], sizeof(ixPCIEMSIX_VECT0_CONTROL)/sizeof(ixPCIEMSIX_VECT0_CONTROL[0]), 0, 0 }, - { "ixPCIEMSIX_VECT1_ADDR_LO", REG_SMC, 0x0010, 0, &ixPCIEMSIX_VECT1_ADDR_LO[0], sizeof(ixPCIEMSIX_VECT1_ADDR_LO)/sizeof(ixPCIEMSIX_VECT1_ADDR_LO[0]), 0, 0 }, - { "ixPCIEMSIX_VECT1_ADDR_HI", REG_SMC, 0x0014, 0, &ixPCIEMSIX_VECT1_ADDR_HI[0], sizeof(ixPCIEMSIX_VECT1_ADDR_HI)/sizeof(ixPCIEMSIX_VECT1_ADDR_HI[0]), 0, 0 }, - { "ixPCIEMSIX_VECT1_MSG_DATA", REG_SMC, 0x0018, 0, &ixPCIEMSIX_VECT1_MSG_DATA[0], sizeof(ixPCIEMSIX_VECT1_MSG_DATA)/sizeof(ixPCIEMSIX_VECT1_MSG_DATA[0]), 0, 0 }, - { "ixPCIEMSIX_VECT1_CONTROL", REG_SMC, 0x001c, 0, &ixPCIEMSIX_VECT1_CONTROL[0], sizeof(ixPCIEMSIX_VECT1_CONTROL)/sizeof(ixPCIEMSIX_VECT1_CONTROL[0]), 0, 0 }, - { "ixPCIEMSIX_VECT2_ADDR_LO", REG_SMC, 0x0020, 0, &ixPCIEMSIX_VECT2_ADDR_LO[0], sizeof(ixPCIEMSIX_VECT2_ADDR_LO)/sizeof(ixPCIEMSIX_VECT2_ADDR_LO[0]), 0, 0 }, - { "ixPCIEMSIX_VECT2_ADDR_HI", REG_SMC, 0x0024, 0, &ixPCIEMSIX_VECT2_ADDR_HI[0], sizeof(ixPCIEMSIX_VECT2_ADDR_HI)/sizeof(ixPCIEMSIX_VECT2_ADDR_HI[0]), 0, 0 }, - { "ixPCIEMSIX_VECT2_MSG_DATA", REG_SMC, 0x0028, 0, &ixPCIEMSIX_VECT2_MSG_DATA[0], sizeof(ixPCIEMSIX_VECT2_MSG_DATA)/sizeof(ixPCIEMSIX_VECT2_MSG_DATA[0]), 0, 0 }, - { "ixPCIEMSIX_VECT2_CONTROL", REG_SMC, 0x002c, 0, &ixPCIEMSIX_VECT2_CONTROL[0], sizeof(ixPCIEMSIX_VECT2_CONTROL)/sizeof(ixPCIEMSIX_VECT2_CONTROL[0]), 0, 0 }, - { "ixPCIEMSIX_VECT3_ADDR_LO", REG_SMC, 0x0030, 0, &ixPCIEMSIX_VECT3_ADDR_LO[0], sizeof(ixPCIEMSIX_VECT3_ADDR_LO)/sizeof(ixPCIEMSIX_VECT3_ADDR_LO[0]), 0, 0 }, - { "ixPCIEMSIX_VECT3_ADDR_HI", REG_SMC, 0x0034, 0, &ixPCIEMSIX_VECT3_ADDR_HI[0], sizeof(ixPCIEMSIX_VECT3_ADDR_HI)/sizeof(ixPCIEMSIX_VECT3_ADDR_HI[0]), 0, 0 }, - { "ixPCIEMSIX_VECT3_MSG_DATA", REG_SMC, 0x0038, 0, &ixPCIEMSIX_VECT3_MSG_DATA[0], sizeof(ixPCIEMSIX_VECT3_MSG_DATA)/sizeof(ixPCIEMSIX_VECT3_MSG_DATA[0]), 0, 0 }, - { "ixPCIEMSIX_VECT3_CONTROL", REG_SMC, 0x003c, 0, &ixPCIEMSIX_VECT3_CONTROL[0], sizeof(ixPCIEMSIX_VECT3_CONTROL)/sizeof(ixPCIEMSIX_VECT3_CONTROL[0]), 0, 0 }, - { "ixPCIEMSIX_VECT4_ADDR_LO", REG_SMC, 0x0040, 0, &ixPCIEMSIX_VECT4_ADDR_LO[0], sizeof(ixPCIEMSIX_VECT4_ADDR_LO)/sizeof(ixPCIEMSIX_VECT4_ADDR_LO[0]), 0, 0 }, - { "ixPCIEMSIX_VECT4_ADDR_HI", REG_SMC, 0x0044, 0, &ixPCIEMSIX_VECT4_ADDR_HI[0], sizeof(ixPCIEMSIX_VECT4_ADDR_HI)/sizeof(ixPCIEMSIX_VECT4_ADDR_HI[0]), 0, 0 }, - { "ixPCIEMSIX_VECT4_MSG_DATA", REG_SMC, 0x0048, 0, &ixPCIEMSIX_VECT4_MSG_DATA[0], sizeof(ixPCIEMSIX_VECT4_MSG_DATA)/sizeof(ixPCIEMSIX_VECT4_MSG_DATA[0]), 0, 0 }, - { "ixPCIEMSIX_VECT4_CONTROL", REG_SMC, 0x004c, 0, &ixPCIEMSIX_VECT4_CONTROL[0], sizeof(ixPCIEMSIX_VECT4_CONTROL)/sizeof(ixPCIEMSIX_VECT4_CONTROL[0]), 0, 0 }, - { "ixPCIEMSIX_VECT5_ADDR_LO", REG_SMC, 0x0050, 0, &ixPCIEMSIX_VECT5_ADDR_LO[0], sizeof(ixPCIEMSIX_VECT5_ADDR_LO)/sizeof(ixPCIEMSIX_VECT5_ADDR_LO[0]), 0, 0 }, - { "ixPCIEMSIX_VECT5_ADDR_HI", REG_SMC, 0x0054, 0, &ixPCIEMSIX_VECT5_ADDR_HI[0], sizeof(ixPCIEMSIX_VECT5_ADDR_HI)/sizeof(ixPCIEMSIX_VECT5_ADDR_HI[0]), 0, 0 }, - { "ixPCIEMSIX_VECT5_MSG_DATA", REG_SMC, 0x0058, 0, &ixPCIEMSIX_VECT5_MSG_DATA[0], sizeof(ixPCIEMSIX_VECT5_MSG_DATA)/sizeof(ixPCIEMSIX_VECT5_MSG_DATA[0]), 0, 0 }, - { "ixPCIEMSIX_VECT5_CONTROL", REG_SMC, 0x005c, 0, &ixPCIEMSIX_VECT5_CONTROL[0], sizeof(ixPCIEMSIX_VECT5_CONTROL)/sizeof(ixPCIEMSIX_VECT5_CONTROL[0]), 0, 0 }, - { "ixPCIEMSIX_VECT6_ADDR_LO", REG_SMC, 0x0060, 0, &ixPCIEMSIX_VECT6_ADDR_LO[0], sizeof(ixPCIEMSIX_VECT6_ADDR_LO)/sizeof(ixPCIEMSIX_VECT6_ADDR_LO[0]), 0, 0 }, - { "ixPCIEMSIX_VECT6_ADDR_HI", REG_SMC, 0x0064, 0, &ixPCIEMSIX_VECT6_ADDR_HI[0], sizeof(ixPCIEMSIX_VECT6_ADDR_HI)/sizeof(ixPCIEMSIX_VECT6_ADDR_HI[0]), 0, 0 }, - { "ixPCIEMSIX_VECT6_MSG_DATA", REG_SMC, 0x0068, 0, &ixPCIEMSIX_VECT6_MSG_DATA[0], sizeof(ixPCIEMSIX_VECT6_MSG_DATA)/sizeof(ixPCIEMSIX_VECT6_MSG_DATA[0]), 0, 0 }, - { "ixPCIEMSIX_VECT6_CONTROL", REG_SMC, 0x006c, 0, &ixPCIEMSIX_VECT6_CONTROL[0], sizeof(ixPCIEMSIX_VECT6_CONTROL)/sizeof(ixPCIEMSIX_VECT6_CONTROL[0]), 0, 0 }, - { "ixPCIEMSIX_VECT7_ADDR_LO", REG_SMC, 0x0070, 0, &ixPCIEMSIX_VECT7_ADDR_LO[0], sizeof(ixPCIEMSIX_VECT7_ADDR_LO)/sizeof(ixPCIEMSIX_VECT7_ADDR_LO[0]), 0, 0 }, - { "ixPCIEMSIX_VECT7_ADDR_HI", REG_SMC, 0x0074, 0, &ixPCIEMSIX_VECT7_ADDR_HI[0], sizeof(ixPCIEMSIX_VECT7_ADDR_HI)/sizeof(ixPCIEMSIX_VECT7_ADDR_HI[0]), 0, 0 }, - { "ixPCIEMSIX_VECT7_MSG_DATA", REG_SMC, 0x0078, 0, &ixPCIEMSIX_VECT7_MSG_DATA[0], sizeof(ixPCIEMSIX_VECT7_MSG_DATA)/sizeof(ixPCIEMSIX_VECT7_MSG_DATA[0]), 0, 0 }, - { "ixPCIEMSIX_VECT7_CONTROL", REG_SMC, 0x007c, 0, &ixPCIEMSIX_VECT7_CONTROL[0], sizeof(ixPCIEMSIX_VECT7_CONTROL)/sizeof(ixPCIEMSIX_VECT7_CONTROL[0]), 0, 0 }, - { "ixPCIEMSIX_VECT8_ADDR_LO", REG_SMC, 0x0080, 0, &ixPCIEMSIX_VECT8_ADDR_LO[0], sizeof(ixPCIEMSIX_VECT8_ADDR_LO)/sizeof(ixPCIEMSIX_VECT8_ADDR_LO[0]), 0, 0 }, - { "ixPCIEMSIX_VECT8_ADDR_HI", REG_SMC, 0x0084, 0, &ixPCIEMSIX_VECT8_ADDR_HI[0], sizeof(ixPCIEMSIX_VECT8_ADDR_HI)/sizeof(ixPCIEMSIX_VECT8_ADDR_HI[0]), 0, 0 }, - { "ixPCIEMSIX_VECT8_MSG_DATA", REG_SMC, 0x0088, 0, &ixPCIEMSIX_VECT8_MSG_DATA[0], sizeof(ixPCIEMSIX_VECT8_MSG_DATA)/sizeof(ixPCIEMSIX_VECT8_MSG_DATA[0]), 0, 0 }, - { "ixPCIEMSIX_VECT8_CONTROL", REG_SMC, 0x008c, 0, &ixPCIEMSIX_VECT8_CONTROL[0], sizeof(ixPCIEMSIX_VECT8_CONTROL)/sizeof(ixPCIEMSIX_VECT8_CONTROL[0]), 0, 0 }, - { "ixPCIEMSIX_VECT9_ADDR_LO", REG_SMC, 0x0090, 0, &ixPCIEMSIX_VECT9_ADDR_LO[0], sizeof(ixPCIEMSIX_VECT9_ADDR_LO)/sizeof(ixPCIEMSIX_VECT9_ADDR_LO[0]), 0, 0 }, - { "ixPCIEMSIX_VECT9_ADDR_HI", REG_SMC, 0x0094, 0, &ixPCIEMSIX_VECT9_ADDR_HI[0], sizeof(ixPCIEMSIX_VECT9_ADDR_HI)/sizeof(ixPCIEMSIX_VECT9_ADDR_HI[0]), 0, 0 }, - { "ixPCIEMSIX_VECT9_MSG_DATA", REG_SMC, 0x0098, 0, &ixPCIEMSIX_VECT9_MSG_DATA[0], sizeof(ixPCIEMSIX_VECT9_MSG_DATA)/sizeof(ixPCIEMSIX_VECT9_MSG_DATA[0]), 0, 0 }, - { "ixPCIEMSIX_VECT9_CONTROL", REG_SMC, 0x009c, 0, &ixPCIEMSIX_VECT9_CONTROL[0], sizeof(ixPCIEMSIX_VECT9_CONTROL)/sizeof(ixPCIEMSIX_VECT9_CONTROL[0]), 0, 0 }, - { "ixPCIEMSIX_VECT10_ADDR_LO", REG_SMC, 0x00a0, 0, &ixPCIEMSIX_VECT10_ADDR_LO[0], sizeof(ixPCIEMSIX_VECT10_ADDR_LO)/sizeof(ixPCIEMSIX_VECT10_ADDR_LO[0]), 0, 0 }, - { "ixPCIEMSIX_VECT10_ADDR_HI", REG_SMC, 0x00a4, 0, &ixPCIEMSIX_VECT10_ADDR_HI[0], sizeof(ixPCIEMSIX_VECT10_ADDR_HI)/sizeof(ixPCIEMSIX_VECT10_ADDR_HI[0]), 0, 0 }, - { "ixPCIEMSIX_VECT10_MSG_DATA", REG_SMC, 0x00a8, 0, &ixPCIEMSIX_VECT10_MSG_DATA[0], sizeof(ixPCIEMSIX_VECT10_MSG_DATA)/sizeof(ixPCIEMSIX_VECT10_MSG_DATA[0]), 0, 0 }, - { "ixPCIEMSIX_VECT10_CONTROL", REG_SMC, 0x00ac, 0, &ixPCIEMSIX_VECT10_CONTROL[0], sizeof(ixPCIEMSIX_VECT10_CONTROL)/sizeof(ixPCIEMSIX_VECT10_CONTROL[0]), 0, 0 }, - { "ixPCIEMSIX_VECT11_ADDR_LO", REG_SMC, 0x00b0, 0, &ixPCIEMSIX_VECT11_ADDR_LO[0], sizeof(ixPCIEMSIX_VECT11_ADDR_LO)/sizeof(ixPCIEMSIX_VECT11_ADDR_LO[0]), 0, 0 }, - { "ixPCIEMSIX_VECT11_ADDR_HI", REG_SMC, 0x00b4, 0, &ixPCIEMSIX_VECT11_ADDR_HI[0], sizeof(ixPCIEMSIX_VECT11_ADDR_HI)/sizeof(ixPCIEMSIX_VECT11_ADDR_HI[0]), 0, 0 }, - { "ixPCIEMSIX_VECT11_MSG_DATA", REG_SMC, 0x00b8, 0, &ixPCIEMSIX_VECT11_MSG_DATA[0], sizeof(ixPCIEMSIX_VECT11_MSG_DATA)/sizeof(ixPCIEMSIX_VECT11_MSG_DATA[0]), 0, 0 }, - { "ixPCIEMSIX_VECT11_CONTROL", REG_SMC, 0x00bc, 0, &ixPCIEMSIX_VECT11_CONTROL[0], sizeof(ixPCIEMSIX_VECT11_CONTROL)/sizeof(ixPCIEMSIX_VECT11_CONTROL[0]), 0, 0 }, - { "ixPCIEMSIX_VECT12_ADDR_LO", REG_SMC, 0x00c0, 0, &ixPCIEMSIX_VECT12_ADDR_LO[0], sizeof(ixPCIEMSIX_VECT12_ADDR_LO)/sizeof(ixPCIEMSIX_VECT12_ADDR_LO[0]), 0, 0 }, - { "ixPCIEMSIX_VECT12_ADDR_HI", REG_SMC, 0x00c4, 0, &ixPCIEMSIX_VECT12_ADDR_HI[0], sizeof(ixPCIEMSIX_VECT12_ADDR_HI)/sizeof(ixPCIEMSIX_VECT12_ADDR_HI[0]), 0, 0 }, - { "ixPCIEMSIX_VECT12_MSG_DATA", REG_SMC, 0x00c8, 0, &ixPCIEMSIX_VECT12_MSG_DATA[0], sizeof(ixPCIEMSIX_VECT12_MSG_DATA)/sizeof(ixPCIEMSIX_VECT12_MSG_DATA[0]), 0, 0 }, - { "ixPCIEMSIX_VECT12_CONTROL", REG_SMC, 0x00cc, 0, &ixPCIEMSIX_VECT12_CONTROL[0], sizeof(ixPCIEMSIX_VECT12_CONTROL)/sizeof(ixPCIEMSIX_VECT12_CONTROL[0]), 0, 0 }, - { "ixPCIEMSIX_VECT13_ADDR_LO", REG_SMC, 0x00d0, 0, &ixPCIEMSIX_VECT13_ADDR_LO[0], sizeof(ixPCIEMSIX_VECT13_ADDR_LO)/sizeof(ixPCIEMSIX_VECT13_ADDR_LO[0]), 0, 0 }, - { "ixPCIEMSIX_VECT13_ADDR_HI", REG_SMC, 0x00d4, 0, &ixPCIEMSIX_VECT13_ADDR_HI[0], sizeof(ixPCIEMSIX_VECT13_ADDR_HI)/sizeof(ixPCIEMSIX_VECT13_ADDR_HI[0]), 0, 0 }, - { "ixPCIEMSIX_VECT13_MSG_DATA", REG_SMC, 0x00d8, 0, &ixPCIEMSIX_VECT13_MSG_DATA[0], sizeof(ixPCIEMSIX_VECT13_MSG_DATA)/sizeof(ixPCIEMSIX_VECT13_MSG_DATA[0]), 0, 0 }, - { "ixPCIEMSIX_VECT13_CONTROL", REG_SMC, 0x00dc, 0, &ixPCIEMSIX_VECT13_CONTROL[0], sizeof(ixPCIEMSIX_VECT13_CONTROL)/sizeof(ixPCIEMSIX_VECT13_CONTROL[0]), 0, 0 }, - { "ixPCIEMSIX_VECT14_ADDR_LO", REG_SMC, 0x00e0, 0, &ixPCIEMSIX_VECT14_ADDR_LO[0], sizeof(ixPCIEMSIX_VECT14_ADDR_LO)/sizeof(ixPCIEMSIX_VECT14_ADDR_LO[0]), 0, 0 }, - { "ixPCIEMSIX_VECT14_ADDR_HI", REG_SMC, 0x00e4, 0, &ixPCIEMSIX_VECT14_ADDR_HI[0], sizeof(ixPCIEMSIX_VECT14_ADDR_HI)/sizeof(ixPCIEMSIX_VECT14_ADDR_HI[0]), 0, 0 }, - { "ixPCIEMSIX_VECT14_MSG_DATA", REG_SMC, 0x00e8, 0, &ixPCIEMSIX_VECT14_MSG_DATA[0], sizeof(ixPCIEMSIX_VECT14_MSG_DATA)/sizeof(ixPCIEMSIX_VECT14_MSG_DATA[0]), 0, 0 }, - { "ixPCIEMSIX_VECT14_CONTROL", REG_SMC, 0x00ec, 0, &ixPCIEMSIX_VECT14_CONTROL[0], sizeof(ixPCIEMSIX_VECT14_CONTROL)/sizeof(ixPCIEMSIX_VECT14_CONTROL[0]), 0, 0 }, - { "ixPCIEMSIX_VECT15_ADDR_LO", REG_SMC, 0x00f0, 0, &ixPCIEMSIX_VECT15_ADDR_LO[0], sizeof(ixPCIEMSIX_VECT15_ADDR_LO)/sizeof(ixPCIEMSIX_VECT15_ADDR_LO[0]), 0, 0 }, - { "ixPCIEMSIX_VECT15_ADDR_HI", REG_SMC, 0x00f4, 0, &ixPCIEMSIX_VECT15_ADDR_HI[0], sizeof(ixPCIEMSIX_VECT15_ADDR_HI)/sizeof(ixPCIEMSIX_VECT15_ADDR_HI[0]), 0, 0 }, - { "ixPCIEMSIX_VECT15_MSG_DATA", REG_SMC, 0x00f8, 0, &ixPCIEMSIX_VECT15_MSG_DATA[0], sizeof(ixPCIEMSIX_VECT15_MSG_DATA)/sizeof(ixPCIEMSIX_VECT15_MSG_DATA[0]), 0, 0 }, - { "ixPCIEMSIX_VECT15_CONTROL", REG_SMC, 0x00fc, 0, &ixPCIEMSIX_VECT15_CONTROL[0], sizeof(ixPCIEMSIX_VECT15_CONTROL)/sizeof(ixPCIEMSIX_VECT15_CONTROL[0]), 0, 0 }, - { "ixPCIEMSIX_VECT16_ADDR_LO", REG_SMC, 0x0100, 0, &ixPCIEMSIX_VECT16_ADDR_LO[0], sizeof(ixPCIEMSIX_VECT16_ADDR_LO)/sizeof(ixPCIEMSIX_VECT16_ADDR_LO[0]), 0, 0 }, - { "ixPCIEMSIX_VECT16_ADDR_HI", REG_SMC, 0x0104, 0, &ixPCIEMSIX_VECT16_ADDR_HI[0], sizeof(ixPCIEMSIX_VECT16_ADDR_HI)/sizeof(ixPCIEMSIX_VECT16_ADDR_HI[0]), 0, 0 }, - { "ixPCIEMSIX_VECT16_MSG_DATA", REG_SMC, 0x0108, 0, &ixPCIEMSIX_VECT16_MSG_DATA[0], sizeof(ixPCIEMSIX_VECT16_MSG_DATA)/sizeof(ixPCIEMSIX_VECT16_MSG_DATA[0]), 0, 0 }, - { "ixPCIEMSIX_VECT16_CONTROL", REG_SMC, 0x010c, 0, &ixPCIEMSIX_VECT16_CONTROL[0], sizeof(ixPCIEMSIX_VECT16_CONTROL)/sizeof(ixPCIEMSIX_VECT16_CONTROL[0]), 0, 0 }, - { "ixPCIEMSIX_VECT17_ADDR_LO", REG_SMC, 0x0110, 0, &ixPCIEMSIX_VECT17_ADDR_LO[0], sizeof(ixPCIEMSIX_VECT17_ADDR_LO)/sizeof(ixPCIEMSIX_VECT17_ADDR_LO[0]), 0, 0 }, - { "ixPCIEMSIX_VECT17_ADDR_HI", REG_SMC, 0x0114, 0, &ixPCIEMSIX_VECT17_ADDR_HI[0], sizeof(ixPCIEMSIX_VECT17_ADDR_HI)/sizeof(ixPCIEMSIX_VECT17_ADDR_HI[0]), 0, 0 }, - { "ixPCIEMSIX_VECT17_MSG_DATA", REG_SMC, 0x0118, 0, &ixPCIEMSIX_VECT17_MSG_DATA[0], sizeof(ixPCIEMSIX_VECT17_MSG_DATA)/sizeof(ixPCIEMSIX_VECT17_MSG_DATA[0]), 0, 0 }, - { "ixPCIEMSIX_VECT17_CONTROL", REG_SMC, 0x011c, 0, &ixPCIEMSIX_VECT17_CONTROL[0], sizeof(ixPCIEMSIX_VECT17_CONTROL)/sizeof(ixPCIEMSIX_VECT17_CONTROL[0]), 0, 0 }, - { "ixPCIEMSIX_VECT18_ADDR_LO", REG_SMC, 0x0120, 0, &ixPCIEMSIX_VECT18_ADDR_LO[0], sizeof(ixPCIEMSIX_VECT18_ADDR_LO)/sizeof(ixPCIEMSIX_VECT18_ADDR_LO[0]), 0, 0 }, - { "ixPCIEMSIX_VECT18_ADDR_HI", REG_SMC, 0x0124, 0, &ixPCIEMSIX_VECT18_ADDR_HI[0], sizeof(ixPCIEMSIX_VECT18_ADDR_HI)/sizeof(ixPCIEMSIX_VECT18_ADDR_HI[0]), 0, 0 }, - { "ixPCIEMSIX_VECT18_MSG_DATA", REG_SMC, 0x0128, 0, &ixPCIEMSIX_VECT18_MSG_DATA[0], sizeof(ixPCIEMSIX_VECT18_MSG_DATA)/sizeof(ixPCIEMSIX_VECT18_MSG_DATA[0]), 0, 0 }, - { "ixPCIEMSIX_VECT18_CONTROL", REG_SMC, 0x012c, 0, &ixPCIEMSIX_VECT18_CONTROL[0], sizeof(ixPCIEMSIX_VECT18_CONTROL)/sizeof(ixPCIEMSIX_VECT18_CONTROL[0]), 0, 0 }, - { "ixPCIEMSIX_VECT19_ADDR_LO", REG_SMC, 0x0130, 0, &ixPCIEMSIX_VECT19_ADDR_LO[0], sizeof(ixPCIEMSIX_VECT19_ADDR_LO)/sizeof(ixPCIEMSIX_VECT19_ADDR_LO[0]), 0, 0 }, - { "ixPCIEMSIX_VECT19_ADDR_HI", REG_SMC, 0x0134, 0, &ixPCIEMSIX_VECT19_ADDR_HI[0], sizeof(ixPCIEMSIX_VECT19_ADDR_HI)/sizeof(ixPCIEMSIX_VECT19_ADDR_HI[0]), 0, 0 }, - { "ixPCIEMSIX_VECT19_MSG_DATA", REG_SMC, 0x0138, 0, &ixPCIEMSIX_VECT19_MSG_DATA[0], sizeof(ixPCIEMSIX_VECT19_MSG_DATA)/sizeof(ixPCIEMSIX_VECT19_MSG_DATA[0]), 0, 0 }, - { "ixPCIEMSIX_VECT19_CONTROL", REG_SMC, 0x013c, 0, &ixPCIEMSIX_VECT19_CONTROL[0], sizeof(ixPCIEMSIX_VECT19_CONTROL)/sizeof(ixPCIEMSIX_VECT19_CONTROL[0]), 0, 0 }, - { "ixPCIEMSIX_VECT20_ADDR_LO", REG_SMC, 0x0140, 0, &ixPCIEMSIX_VECT20_ADDR_LO[0], sizeof(ixPCIEMSIX_VECT20_ADDR_LO)/sizeof(ixPCIEMSIX_VECT20_ADDR_LO[0]), 0, 0 }, - { "ixPCIEMSIX_VECT20_ADDR_HI", REG_SMC, 0x0144, 0, &ixPCIEMSIX_VECT20_ADDR_HI[0], sizeof(ixPCIEMSIX_VECT20_ADDR_HI)/sizeof(ixPCIEMSIX_VECT20_ADDR_HI[0]), 0, 0 }, - { "ixPCIEMSIX_VECT20_MSG_DATA", REG_SMC, 0x0148, 0, &ixPCIEMSIX_VECT20_MSG_DATA[0], sizeof(ixPCIEMSIX_VECT20_MSG_DATA)/sizeof(ixPCIEMSIX_VECT20_MSG_DATA[0]), 0, 0 }, - { "ixPCIEMSIX_VECT20_CONTROL", REG_SMC, 0x014c, 0, &ixPCIEMSIX_VECT20_CONTROL[0], sizeof(ixPCIEMSIX_VECT20_CONTROL)/sizeof(ixPCIEMSIX_VECT20_CONTROL[0]), 0, 0 }, - { "ixPCIEMSIX_VECT21_ADDR_LO", REG_SMC, 0x0150, 0, &ixPCIEMSIX_VECT21_ADDR_LO[0], sizeof(ixPCIEMSIX_VECT21_ADDR_LO)/sizeof(ixPCIEMSIX_VECT21_ADDR_LO[0]), 0, 0 }, - { "ixPCIEMSIX_VECT21_ADDR_HI", REG_SMC, 0x0154, 0, &ixPCIEMSIX_VECT21_ADDR_HI[0], sizeof(ixPCIEMSIX_VECT21_ADDR_HI)/sizeof(ixPCIEMSIX_VECT21_ADDR_HI[0]), 0, 0 }, - { "ixPCIEMSIX_VECT21_MSG_DATA", REG_SMC, 0x0158, 0, &ixPCIEMSIX_VECT21_MSG_DATA[0], sizeof(ixPCIEMSIX_VECT21_MSG_DATA)/sizeof(ixPCIEMSIX_VECT21_MSG_DATA[0]), 0, 0 }, - { "ixPCIEMSIX_VECT21_CONTROL", REG_SMC, 0x015c, 0, &ixPCIEMSIX_VECT21_CONTROL[0], sizeof(ixPCIEMSIX_VECT21_CONTROL)/sizeof(ixPCIEMSIX_VECT21_CONTROL[0]), 0, 0 }, - { "ixPCIEMSIX_VECT22_ADDR_LO", REG_SMC, 0x0160, 0, &ixPCIEMSIX_VECT22_ADDR_LO[0], sizeof(ixPCIEMSIX_VECT22_ADDR_LO)/sizeof(ixPCIEMSIX_VECT22_ADDR_LO[0]), 0, 0 }, - { "ixPCIEMSIX_VECT22_ADDR_HI", REG_SMC, 0x0164, 0, &ixPCIEMSIX_VECT22_ADDR_HI[0], sizeof(ixPCIEMSIX_VECT22_ADDR_HI)/sizeof(ixPCIEMSIX_VECT22_ADDR_HI[0]), 0, 0 }, - { "ixPCIEMSIX_VECT22_MSG_DATA", REG_SMC, 0x0168, 0, &ixPCIEMSIX_VECT22_MSG_DATA[0], sizeof(ixPCIEMSIX_VECT22_MSG_DATA)/sizeof(ixPCIEMSIX_VECT22_MSG_DATA[0]), 0, 0 }, - { "ixPCIEMSIX_VECT22_CONTROL", REG_SMC, 0x016c, 0, &ixPCIEMSIX_VECT22_CONTROL[0], sizeof(ixPCIEMSIX_VECT22_CONTROL)/sizeof(ixPCIEMSIX_VECT22_CONTROL[0]), 0, 0 }, - { "ixPCIEMSIX_VECT23_ADDR_LO", REG_SMC, 0x0170, 0, &ixPCIEMSIX_VECT23_ADDR_LO[0], sizeof(ixPCIEMSIX_VECT23_ADDR_LO)/sizeof(ixPCIEMSIX_VECT23_ADDR_LO[0]), 0, 0 }, - { "ixPCIEMSIX_VECT23_ADDR_HI", REG_SMC, 0x0174, 0, &ixPCIEMSIX_VECT23_ADDR_HI[0], sizeof(ixPCIEMSIX_VECT23_ADDR_HI)/sizeof(ixPCIEMSIX_VECT23_ADDR_HI[0]), 0, 0 }, - { "ixPCIEMSIX_VECT23_MSG_DATA", REG_SMC, 0x0178, 0, &ixPCIEMSIX_VECT23_MSG_DATA[0], sizeof(ixPCIEMSIX_VECT23_MSG_DATA)/sizeof(ixPCIEMSIX_VECT23_MSG_DATA[0]), 0, 0 }, - { "ixPCIEMSIX_VECT23_CONTROL", REG_SMC, 0x017c, 0, &ixPCIEMSIX_VECT23_CONTROL[0], sizeof(ixPCIEMSIX_VECT23_CONTROL)/sizeof(ixPCIEMSIX_VECT23_CONTROL[0]), 0, 0 }, - { "ixPCIEMSIX_VECT24_ADDR_LO", REG_SMC, 0x0180, 0, &ixPCIEMSIX_VECT24_ADDR_LO[0], sizeof(ixPCIEMSIX_VECT24_ADDR_LO)/sizeof(ixPCIEMSIX_VECT24_ADDR_LO[0]), 0, 0 }, - { "ixPCIEMSIX_VECT24_ADDR_HI", REG_SMC, 0x0184, 0, &ixPCIEMSIX_VECT24_ADDR_HI[0], sizeof(ixPCIEMSIX_VECT24_ADDR_HI)/sizeof(ixPCIEMSIX_VECT24_ADDR_HI[0]), 0, 0 }, - { "ixPCIEMSIX_VECT24_MSG_DATA", REG_SMC, 0x0188, 0, &ixPCIEMSIX_VECT24_MSG_DATA[0], sizeof(ixPCIEMSIX_VECT24_MSG_DATA)/sizeof(ixPCIEMSIX_VECT24_MSG_DATA[0]), 0, 0 }, - { "ixPCIEMSIX_VECT24_CONTROL", REG_SMC, 0x018c, 0, &ixPCIEMSIX_VECT24_CONTROL[0], sizeof(ixPCIEMSIX_VECT24_CONTROL)/sizeof(ixPCIEMSIX_VECT24_CONTROL[0]), 0, 0 }, - { "ixPCIEMSIX_VECT25_ADDR_LO", REG_SMC, 0x0190, 0, &ixPCIEMSIX_VECT25_ADDR_LO[0], sizeof(ixPCIEMSIX_VECT25_ADDR_LO)/sizeof(ixPCIEMSIX_VECT25_ADDR_LO[0]), 0, 0 }, - { "ixPCIEMSIX_VECT25_ADDR_HI", REG_SMC, 0x0194, 0, &ixPCIEMSIX_VECT25_ADDR_HI[0], sizeof(ixPCIEMSIX_VECT25_ADDR_HI)/sizeof(ixPCIEMSIX_VECT25_ADDR_HI[0]), 0, 0 }, - { "ixPCIEMSIX_VECT25_MSG_DATA", REG_SMC, 0x0198, 0, &ixPCIEMSIX_VECT25_MSG_DATA[0], sizeof(ixPCIEMSIX_VECT25_MSG_DATA)/sizeof(ixPCIEMSIX_VECT25_MSG_DATA[0]), 0, 0 }, - { "ixPCIEMSIX_VECT25_CONTROL", REG_SMC, 0x019c, 0, &ixPCIEMSIX_VECT25_CONTROL[0], sizeof(ixPCIEMSIX_VECT25_CONTROL)/sizeof(ixPCIEMSIX_VECT25_CONTROL[0]), 0, 0 }, - { "ixPCIEMSIX_VECT26_ADDR_LO", REG_SMC, 0x01a0, 0, &ixPCIEMSIX_VECT26_ADDR_LO[0], sizeof(ixPCIEMSIX_VECT26_ADDR_LO)/sizeof(ixPCIEMSIX_VECT26_ADDR_LO[0]), 0, 0 }, - { "ixPCIEMSIX_VECT26_ADDR_HI", REG_SMC, 0x01a4, 0, &ixPCIEMSIX_VECT26_ADDR_HI[0], sizeof(ixPCIEMSIX_VECT26_ADDR_HI)/sizeof(ixPCIEMSIX_VECT26_ADDR_HI[0]), 0, 0 }, - { "ixPCIEMSIX_VECT26_MSG_DATA", REG_SMC, 0x01a8, 0, &ixPCIEMSIX_VECT26_MSG_DATA[0], sizeof(ixPCIEMSIX_VECT26_MSG_DATA)/sizeof(ixPCIEMSIX_VECT26_MSG_DATA[0]), 0, 0 }, - { "ixPCIEMSIX_VECT26_CONTROL", REG_SMC, 0x01ac, 0, &ixPCIEMSIX_VECT26_CONTROL[0], sizeof(ixPCIEMSIX_VECT26_CONTROL)/sizeof(ixPCIEMSIX_VECT26_CONTROL[0]), 0, 0 }, - { "ixPCIEMSIX_VECT27_ADDR_LO", REG_SMC, 0x01b0, 0, &ixPCIEMSIX_VECT27_ADDR_LO[0], sizeof(ixPCIEMSIX_VECT27_ADDR_LO)/sizeof(ixPCIEMSIX_VECT27_ADDR_LO[0]), 0, 0 }, - { "ixPCIEMSIX_VECT27_ADDR_HI", REG_SMC, 0x01b4, 0, &ixPCIEMSIX_VECT27_ADDR_HI[0], sizeof(ixPCIEMSIX_VECT27_ADDR_HI)/sizeof(ixPCIEMSIX_VECT27_ADDR_HI[0]), 0, 0 }, - { "ixPCIEMSIX_VECT27_MSG_DATA", REG_SMC, 0x01b8, 0, &ixPCIEMSIX_VECT27_MSG_DATA[0], sizeof(ixPCIEMSIX_VECT27_MSG_DATA)/sizeof(ixPCIEMSIX_VECT27_MSG_DATA[0]), 0, 0 }, - { "ixPCIEMSIX_VECT27_CONTROL", REG_SMC, 0x01bc, 0, &ixPCIEMSIX_VECT27_CONTROL[0], sizeof(ixPCIEMSIX_VECT27_CONTROL)/sizeof(ixPCIEMSIX_VECT27_CONTROL[0]), 0, 0 }, - { "ixPCIEMSIX_VECT28_ADDR_LO", REG_SMC, 0x01c0, 0, &ixPCIEMSIX_VECT28_ADDR_LO[0], sizeof(ixPCIEMSIX_VECT28_ADDR_LO)/sizeof(ixPCIEMSIX_VECT28_ADDR_LO[0]), 0, 0 }, - { "ixPCIEMSIX_VECT28_ADDR_HI", REG_SMC, 0x01c4, 0, &ixPCIEMSIX_VECT28_ADDR_HI[0], sizeof(ixPCIEMSIX_VECT28_ADDR_HI)/sizeof(ixPCIEMSIX_VECT28_ADDR_HI[0]), 0, 0 }, - { "ixPCIEMSIX_VECT28_MSG_DATA", REG_SMC, 0x01c8, 0, &ixPCIEMSIX_VECT28_MSG_DATA[0], sizeof(ixPCIEMSIX_VECT28_MSG_DATA)/sizeof(ixPCIEMSIX_VECT28_MSG_DATA[0]), 0, 0 }, - { "ixPCIEMSIX_VECT28_CONTROL", REG_SMC, 0x01cc, 0, &ixPCIEMSIX_VECT28_CONTROL[0], sizeof(ixPCIEMSIX_VECT28_CONTROL)/sizeof(ixPCIEMSIX_VECT28_CONTROL[0]), 0, 0 }, - { "ixPCIEMSIX_VECT29_ADDR_LO", REG_SMC, 0x01d0, 0, &ixPCIEMSIX_VECT29_ADDR_LO[0], sizeof(ixPCIEMSIX_VECT29_ADDR_LO)/sizeof(ixPCIEMSIX_VECT29_ADDR_LO[0]), 0, 0 }, - { "ixPCIEMSIX_VECT29_ADDR_HI", REG_SMC, 0x01d4, 0, &ixPCIEMSIX_VECT29_ADDR_HI[0], sizeof(ixPCIEMSIX_VECT29_ADDR_HI)/sizeof(ixPCIEMSIX_VECT29_ADDR_HI[0]), 0, 0 }, - { "ixPCIEMSIX_VECT29_MSG_DATA", REG_SMC, 0x01d8, 0, &ixPCIEMSIX_VECT29_MSG_DATA[0], sizeof(ixPCIEMSIX_VECT29_MSG_DATA)/sizeof(ixPCIEMSIX_VECT29_MSG_DATA[0]), 0, 0 }, - { "ixPCIEMSIX_VECT29_CONTROL", REG_SMC, 0x01dc, 0, &ixPCIEMSIX_VECT29_CONTROL[0], sizeof(ixPCIEMSIX_VECT29_CONTROL)/sizeof(ixPCIEMSIX_VECT29_CONTROL[0]), 0, 0 }, - { "ixPCIEMSIX_VECT30_ADDR_LO", REG_SMC, 0x01e0, 0, &ixPCIEMSIX_VECT30_ADDR_LO[0], sizeof(ixPCIEMSIX_VECT30_ADDR_LO)/sizeof(ixPCIEMSIX_VECT30_ADDR_LO[0]), 0, 0 }, - { "ixPCIEMSIX_VECT30_ADDR_HI", REG_SMC, 0x01e4, 0, &ixPCIEMSIX_VECT30_ADDR_HI[0], sizeof(ixPCIEMSIX_VECT30_ADDR_HI)/sizeof(ixPCIEMSIX_VECT30_ADDR_HI[0]), 0, 0 }, - { "ixPCIEMSIX_VECT30_MSG_DATA", REG_SMC, 0x01e8, 0, &ixPCIEMSIX_VECT30_MSG_DATA[0], sizeof(ixPCIEMSIX_VECT30_MSG_DATA)/sizeof(ixPCIEMSIX_VECT30_MSG_DATA[0]), 0, 0 }, - { "ixPCIEMSIX_VECT30_CONTROL", REG_SMC, 0x01ec, 0, &ixPCIEMSIX_VECT30_CONTROL[0], sizeof(ixPCIEMSIX_VECT30_CONTROL)/sizeof(ixPCIEMSIX_VECT30_CONTROL[0]), 0, 0 }, - { "ixPCIEMSIX_VECT31_ADDR_LO", REG_SMC, 0x01f0, 0, &ixPCIEMSIX_VECT31_ADDR_LO[0], sizeof(ixPCIEMSIX_VECT31_ADDR_LO)/sizeof(ixPCIEMSIX_VECT31_ADDR_LO[0]), 0, 0 }, - { "ixPCIEMSIX_VECT31_ADDR_HI", REG_SMC, 0x01f4, 0, &ixPCIEMSIX_VECT31_ADDR_HI[0], sizeof(ixPCIEMSIX_VECT31_ADDR_HI)/sizeof(ixPCIEMSIX_VECT31_ADDR_HI[0]), 0, 0 }, - { "ixPCIEMSIX_VECT31_MSG_DATA", REG_SMC, 0x01f8, 0, &ixPCIEMSIX_VECT31_MSG_DATA[0], sizeof(ixPCIEMSIX_VECT31_MSG_DATA)/sizeof(ixPCIEMSIX_VECT31_MSG_DATA[0]), 0, 0 }, - { "ixPCIEMSIX_VECT31_CONTROL", REG_SMC, 0x01fc, 0, &ixPCIEMSIX_VECT31_CONTROL[0], sizeof(ixPCIEMSIX_VECT31_CONTROL)/sizeof(ixPCIEMSIX_VECT31_CONTROL[0]), 0, 0 }, - { "ixPCIEMSIX_PBA", REG_SMC, 0x0000, 0, &ixPCIEMSIX_PBA[0], sizeof(ixPCIEMSIX_PBA)/sizeof(ixPCIEMSIX_PBA[0]), 0, 0 }, - { "ixSYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK", REG_SMC, 0x10000, 0, &ixSYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK[0], sizeof(ixSYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK)/sizeof(ixSYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK[0]), 0, 0 }, - { "ixSYSHUBMMREGIND_SYSHUB_DS_CTRL2_SOCCLK", REG_SMC, 0x10004, 0, &ixSYSHUBMMREGIND_SYSHUB_DS_CTRL2_SOCCLK[0], sizeof(ixSYSHUBMMREGIND_SYSHUB_DS_CTRL2_SOCCLK)/sizeof(ixSYSHUBMMREGIND_SYSHUB_DS_CTRL2_SOCCLK[0]), 0, 0 }, - { "ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK", REG_SMC, 0x10008, 0, &ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK[0], sizeof(ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK)/sizeof(ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK[0]), 0, 0 }, - { "ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK", REG_SMC, 0x1000c, 0, &ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK[0], sizeof(ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK)/sizeof(ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK[0]), 0, 0 }, - { "ixSYSHUBMMREGIND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL", REG_SMC, 0x10010, 0, &ixSYSHUBMMREGIND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL[0], sizeof(ixSYSHUBMMREGIND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL)/sizeof(ixSYSHUBMMREGIND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL[0]), 0, 0 }, - { "ixSYSHUBMMREGIND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL", REG_SMC, 0x10014, 0, &ixSYSHUBMMREGIND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL[0], sizeof(ixSYSHUBMMREGIND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL)/sizeof(ixSYSHUBMMREGIND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL[0]), 0, 0 }, - { "ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL", REG_SMC, 0x10018, 0, &ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL[0], sizeof(ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL)/sizeof(ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL[0]), 0, 0 }, - { "ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL", REG_SMC, 0x1001c, 0, &ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL[0], sizeof(ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL)/sizeof(ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL[0]), 0, 0 }, - { "ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL", REG_SMC, 0x10020, 0, &ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL[0], sizeof(ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL)/sizeof(ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL[0]), 0, 0 }, - { "ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL", REG_SMC, 0x10024, 0, &ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL[0], sizeof(ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL)/sizeof(ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL[0]), 0, 0 }, - { "ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL", REG_SMC, 0x10028, 0, &ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL[0], sizeof(ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL)/sizeof(ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL[0]), 0, 0 }, - { "ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL", REG_SMC, 0x1002c, 0, &ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL[0], sizeof(ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL)/sizeof(ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL[0]), 0, 0 }, - { "ixSYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL", REG_SMC, 0x10030, 0, &ixSYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL[0], sizeof(ixSYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL)/sizeof(ixSYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL[0]), 0, 0 }, - { "ixSYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL", REG_SMC, 0x10034, 0, &ixSYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL[0], sizeof(ixSYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL)/sizeof(ixSYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL[0]), 0, 0 }, - { "ixSYSHUBMMREGIND_SYSHUB_CG_CNTL", REG_SMC, 0x10300, 0, &ixSYSHUBMMREGIND_SYSHUB_CG_CNTL[0], sizeof(ixSYSHUBMMREGIND_SYSHUB_CG_CNTL)/sizeof(ixSYSHUBMMREGIND_SYSHUB_CG_CNTL[0]), 0, 0 }, - { "ixSYSHUBMMREGIND_SYSHUB_TRANS_IDLE", REG_SMC, 0x10308, 0, &ixSYSHUBMMREGIND_SYSHUB_TRANS_IDLE[0], sizeof(ixSYSHUBMMREGIND_SYSHUB_TRANS_IDLE)/sizeof(ixSYSHUBMMREGIND_SYSHUB_TRANS_IDLE[0]), 0, 0 }, - { "ixSYSHUBMMREGIND_SYSHUB_HP_TIMER", REG_SMC, 0x1030c, 0, &ixSYSHUBMMREGIND_SYSHUB_HP_TIMER[0], sizeof(ixSYSHUBMMREGIND_SYSHUB_HP_TIMER)/sizeof(ixSYSHUBMMREGIND_SYSHUB_HP_TIMER[0]), 0, 0 }, - { "ixSYSHUBMMREGIND_SYSHUB_SCRATCH", REG_SMC, 0x10f00, 0, &ixSYSHUBMMREGIND_SYSHUB_SCRATCH[0], sizeof(ixSYSHUBMMREGIND_SYSHUB_SCRATCH)/sizeof(ixSYSHUBMMREGIND_SYSHUB_SCRATCH[0]), 0, 0 }, - { "ixSYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK", REG_SMC, 0x11000, 0, &ixSYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK[0], sizeof(ixSYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK)/sizeof(ixSYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK[0]), 0, 0 }, - { "ixSYSHUBMMREGIND_SYSHUB_DS_CTRL2_SHUBCLK", REG_SMC, 0x11004, 0, &ixSYSHUBMMREGIND_SYSHUB_DS_CTRL2_SHUBCLK[0], sizeof(ixSYSHUBMMREGIND_SYSHUB_DS_CTRL2_SHUBCLK)/sizeof(ixSYSHUBMMREGIND_SYSHUB_DS_CTRL2_SHUBCLK[0]), 0, 0 }, - { "ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK", REG_SMC, 0x11008, 0, &ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK[0], sizeof(ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK)/sizeof(ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK[0]), 0, 0 }, - { "ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK", REG_SMC, 0x1100c, 0, &ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK[0], sizeof(ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK)/sizeof(ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK[0]), 0, 0 }, - { "ixSYSHUBMMREGIND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL", REG_SMC, 0x11010, 0, &ixSYSHUBMMREGIND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL[0], sizeof(ixSYSHUBMMREGIND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL)/sizeof(ixSYSHUBMMREGIND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL[0]), 0, 0 }, - { "ixSYSHUBMMREGIND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL", REG_SMC, 0x11014, 0, &ixSYSHUBMMREGIND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL[0], sizeof(ixSYSHUBMMREGIND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL)/sizeof(ixSYSHUBMMREGIND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL[0]), 0, 0 }, - { "ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL", REG_SMC, 0x11018, 0, &ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL[0], sizeof(ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL)/sizeof(ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL[0]), 0, 0 }, - { "ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL", REG_SMC, 0x1101c, 0, &ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL[0], sizeof(ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL)/sizeof(ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL[0]), 0, 0 }, - { "ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL", REG_SMC, 0x11020, 0, &ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL[0], sizeof(ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL)/sizeof(ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL[0]), 0, 0 }, - { "ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL", REG_SMC, 0x11024, 0, &ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL[0], sizeof(ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL)/sizeof(ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL[0]), 0, 0 }, - { "ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL", REG_SMC, 0x11028, 0, &ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL[0], sizeof(ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL)/sizeof(ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL[0]), 0, 0 }, - { "ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL", REG_SMC, 0x1102c, 0, &ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL[0], sizeof(ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL)/sizeof(ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL[0]), 0, 0 }, - { "ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL", REG_SMC, 0x11030, 0, &ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL[0], sizeof(ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL)/sizeof(ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL[0]), 0, 0 }, - { "ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL", REG_SMC, 0x11034, 0, &ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL[0], sizeof(ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL)/sizeof(ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL[0]), 0, 0 }, - { "ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL", REG_SMC, 0x11038, 0, &ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL[0], sizeof(ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL)/sizeof(ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL[0]), 0, 0 }, - { "ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL", REG_SMC, 0x1103c, 0, &ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL[0], sizeof(ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL)/sizeof(ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL[0]), 0, 0 }, diff --git a/src/lib/ip/nbif61.c b/src/lib/ip/nbio70.c index abae80a..df712f8 100644 --- a/src/lib/ip/nbif61.c +++ b/src/lib/ip/nbio70.c @@ -24,13 +24,13 @@ */ #include "umr.h" -#include "nbif61_bits.i" +#include "nbio70_bits.i" -static const struct umr_reg_soc15 nbif61_registers[] = { -#include "nbif61_regs.i" +static const struct umr_reg_soc15 nbio70_registers[] = { +#include "nbio70_regs.i" }; -struct umr_ip_block *umr_create_nbif61(struct umr_ip_offsets_soc15 *soc15_offsets, struct umr_options *options) +struct umr_ip_block *umr_create_nbio70(struct umr_ip_offsets_soc15 *soc15_offsets, struct umr_options *options) { struct umr_ip_block *ip; @@ -38,15 +38,15 @@ struct umr_ip_block *umr_create_nbif61(struct umr_ip_offsets_soc15 *soc15_offset if (!ip) return NULL; - ip->ipname = "nbif61"; - ip->no_regs = sizeof(nbif61_registers)/sizeof(nbif61_registers[0]); + ip->ipname = "nbio70"; + ip->no_regs = sizeof(nbio70_registers)/sizeof(nbio70_registers[0]); ip->regs = calloc(ip->no_regs, sizeof(ip->regs[0])); if (!ip->regs) { free(ip); return NULL; } - if (umr_transfer_soc15_to_reg(options, soc15_offsets, "NBIF", nbif61_registers, ip)) { + if (umr_transfer_soc15_to_reg(options, soc15_offsets, "NBIO", nbio70_registers, ip)) { free(ip); return NULL; } diff --git a/src/lib/ip/nbio70_bits.i b/src/lib/ip/nbio70_bits.i new file mode 100644 index 0000000..2718498 --- /dev/null +++ b/src/lib/ip/nbio70_bits.i @@ -0,0 +1,2558 @@ +static struct umr_bitfield mmport_a_addr[] = { + { "Index", 0, 7, &umr_bitfield_default }, + { "Reserved", 8, 30, &umr_bitfield_default }, + { "ReadEnable", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmport_a_data_lo[] = { + { "Data", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmport_a_data_hi[] = { + { "Data", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmport_b_addr[] = { + { "Index", 0, 7, &umr_bitfield_default }, + { "Reserved", 8, 30, &umr_bitfield_default }, + { "ReadEnable", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmport_b_data_lo[] = { + { "Data", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmport_b_data_hi[] = { + { "Data", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmport_c_addr[] = { + { "Index", 0, 7, &umr_bitfield_default }, + { "Reserved", 8, 30, &umr_bitfield_default }, + { "ReadEnable", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmport_c_data_lo[] = { + { "Data", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmport_c_data_hi[] = { + { "Data", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmport_d_addr[] = { + { "Index", 0, 7, &umr_bitfield_default }, + { "Reserved", 8, 30, &umr_bitfield_default }, + { "ReadEnable", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmport_d_data_lo[] = { + { "Data", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmport_d_data_hi[] = { + { "Data", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_DEVTBL_BASE_0[] = { + { "DEV_TBL_SIZE", 0, 8, &umr_bitfield_default }, + { "Reserved1", 9, 11, &umr_bitfield_default }, + { "DEV_TBL_BASE_LO", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_DEVTBL_BASE_1[] = { + { "DEV_TBL_BASE_HI", 0, 19, &umr_bitfield_default }, + { "Reserved0", 20, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_CMD_BASE_0[] = { + { "Reserved1", 0, 11, &umr_bitfield_default }, + { "COM_BASE_LO", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_CMD_BASE_1[] = { + { "COM_BASE_HI", 0, 19, &umr_bitfield_default }, + { "Reserved1", 20, 23, &umr_bitfield_default }, + { "COM_LEN", 24, 27, &umr_bitfield_default }, + { "Reserved0", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_EVENT_BASE_0[] = { + { "Reserved1", 0, 11, &umr_bitfield_default }, + { "EVENT_BASE_LO", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_EVENT_BASE_1[] = { + { "EVENT_BASE_HI", 0, 19, &umr_bitfield_default }, + { "Reserved1", 20, 23, &umr_bitfield_default }, + { "EVENT_LEN", 24, 27, &umr_bitfield_default }, + { "Reserved0", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_CNTRL_0[] = { + { "IOMMU_EN", 0, 0, &umr_bitfield_default }, + { "HT_TUN_EN", 1, 1, &umr_bitfield_default }, + { "EVENT_LOG_EN", 2, 2, &umr_bitfield_default }, + { "EVENT_INT_EN", 3, 3, &umr_bitfield_default }, + { "COM_WAIT_INTEN", 4, 4, &umr_bitfield_default }, + { "INV_TIMEOUT", 5, 7, &umr_bitfield_default }, + { "PASS_PW", 8, 8, &umr_bitfield_default }, + { "RES_PASS_PW", 9, 9, &umr_bitfield_default }, + { "COHERENT", 10, 10, &umr_bitfield_default }, + { "ISOC", 11, 11, &umr_bitfield_default }, + { "CMD_BUF_EN", 12, 12, &umr_bitfield_default }, + { "PPR_LOG_EN", 13, 13, &umr_bitfield_default }, + { "PPR_INT_EN", 14, 14, &umr_bitfield_default }, + { "PPR_EN", 15, 15, &umr_bitfield_default }, + { "GT_EN", 16, 16, &umr_bitfield_default }, + { "GA_EN", 17, 17, &umr_bitfield_default }, + { "TLPT", 18, 21, &umr_bitfield_default }, + { "SMIF_EN", 22, 22, &umr_bitfield_default }, + { "SMIF_LOG_EN", 24, 24, &umr_bitfield_default }, + { "GAM_EN", 25, 27, &umr_bitfield_default }, + { "GA_LOG_EN", 28, 28, &umr_bitfield_default }, + { "GA_INT_EN", 29, 29, &umr_bitfield_default }, + { "PPRQ", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_CNTRL_1[] = { + { "EVENTQ", 0, 1, &umr_bitfield_default }, + { "DTE_SEG_EN", 2, 3, &umr_bitfield_default }, + { "Reserved1", 4, 4, &umr_bitfield_default }, + { "PRIV_ABORT_EN", 5, 6, &umr_bitfield_default }, + { "PPR_Auto_resp_en", 7, 7, &umr_bitfield_default }, + { "MARC_en", 8, 8, &umr_bitfield_default }, + { "Block_StopMark_En", 9, 9, &umr_bitfield_default }, + { "PPR_Auto_resp_AON", 10, 10, &umr_bitfield_default }, + { "DVM_DOMAIN_PNE", 11, 11, &umr_bitfield_default }, + { "DVM_ERR_EN", 12, 12, &umr_bitfield_default }, + { "EPH_EN", 13, 13, &umr_bitfield_default }, + { "HW_Prefetch_AD", 14, 15, &umr_bitfield_default }, + { "V2_HD_Dis", 16, 16, &umr_bitfield_default }, + { "Reserved0", 17, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_EXCL_BASE_0[] = { + { "EX_EN", 0, 0, &umr_bitfield_default }, + { "EX_ALLOW", 1, 1, &umr_bitfield_default }, + { "Reserved0", 2, 11, &umr_bitfield_default }, + { "EXCL_BASE_LO", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_EXCL_BASE_1[] = { + { "EXCL_BASE_HI", 0, 19, &umr_bitfield_default }, + { "Reserved0", 20, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_EXCL_LIM_0[] = { + { "Reserved0", 0, 11, &umr_bitfield_default }, + { "EXCL_LIMIT_LO", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_EXCL_LIM_1[] = { + { "EXCL_LIMIT_HI", 0, 19, &umr_bitfield_default }, + { "Reserved0", 20, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_EFR_0[] = { + { "PREF_SUP", 0, 0, &umr_bitfield_default }, + { "PPR_SUP", 1, 1, &umr_bitfield_default }, + { "XT_SUP", 2, 2, &umr_bitfield_default }, + { "NX_SUP", 3, 3, &umr_bitfield_default }, + { "GT_SUP", 4, 4, &umr_bitfield_default }, + { "Reserved", 5, 5, &umr_bitfield_default }, + { "IA_SUP", 6, 6, &umr_bitfield_default }, + { "GA_SUP", 7, 7, &umr_bitfield_default }, + { "HE_SUP", 8, 8, &umr_bitfield_default }, + { "PC_SUP", 9, 9, &umr_bitfield_default }, + { "HATS", 10, 11, &umr_bitfield_default }, + { "GATS", 12, 13, &umr_bitfield_default }, + { "GLX_SUP", 14, 15, &umr_bitfield_default }, + { "SMIF_SUP", 16, 17, &umr_bitfield_default }, + { "SMIF_RC", 18, 20, &umr_bitfield_default }, + { "GAM_SUP", 21, 23, &umr_bitfield_default }, + { "PPRF", 24, 25, &umr_bitfield_default }, + { "GAF", 26, 27, &umr_bitfield_default }, + { "EVENTF", 28, 29, &umr_bitfield_default }, + { "DVM_ERR_SUP", 30, 30, &umr_bitfield_default }, + { "Reserved1", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_EFR_1[] = { + { "PAS_MAX", 0, 3, &umr_bitfield_default }, + { "Reserved1", 4, 4, &umr_bitfield_default }, + { "US_SUP", 5, 5, &umr_bitfield_default }, + { "DTE_seg", 6, 7, &umr_bitfield_default }, + { "PPR_OVERFLOW_EARLY_SUP", 8, 8, &umr_bitfield_default }, + { "PPR_AUTORESP_SUP", 9, 9, &umr_bitfield_default }, + { "MARCnum", 10, 11, &umr_bitfield_default }, + { "BLOCK_STOPMARK_SUP", 12, 12, &umr_bitfield_default }, + { "GMC_IOMMU_BYPASS_SUP", 13, 13, &umr_bitfield_default }, + { "MMIO_MSI_CAP_SUP", 14, 14, &umr_bitfield_default }, + { "SNOOP_ATTRS_SUP", 15, 15, &umr_bitfield_default }, + { "GIo_SUP", 16, 16, &umr_bitfield_default }, + { "HA_SUP", 17, 17, &umr_bitfield_default }, + { "EPH_SUP", 18, 18, &umr_bitfield_default }, + { "ATTRFW_SUP", 19, 19, &umr_bitfield_default }, + { "HD_SUP", 20, 20, &umr_bitfield_default }, + { "V2_HD_DIS_SUP", 21, 21, &umr_bitfield_default }, + { "InvIotlbTypeSup", 22, 22, &umr_bitfield_default }, + { "Reserved0", 23, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_PPR_BASE_0[] = { + { "Reserved1", 0, 11, &umr_bitfield_default }, + { "PPR_BASE_LO", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_PPR_BASE_1[] = { + { "PPR_BASE_HI", 0, 19, &umr_bitfield_default }, + { "Reserved1", 20, 23, &umr_bitfield_default }, + { "PPR_LEN", 24, 27, &umr_bitfield_default }, + { "Reserved0", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_HW_ERR_UPPER_0[] = { + { "FIRST_EV_CODE_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_HW_ERR_UPPER_1[] = { + { "FIRST_EV_CODE_HI", 0, 27, &umr_bitfield_default }, + { "EV_CODE", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_HW_ERR_LOWER_0[] = { + { "SECOND_EV_CODE_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_HW_ERR_LOWER_1[] = { + { "SECOND_EV_CODE_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_HW_ERR_STATUS_0[] = { + { "HEV", 0, 0, &umr_bitfield_default }, + { "HEO", 1, 1, &umr_bitfield_default }, + { "Reserved", 2, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_HW_ERR_STATUS_1[] = { + { "Reserved", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSMI_FILTER_REGISTER_0_0[] = { + { "SmiDID_0", 0, 15, &umr_bitfield_default }, + { "SmiDV_0", 16, 16, &umr_bitfield_default }, + { "SmiFLock_0", 17, 17, &umr_bitfield_default }, + { "Reserved", 18, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSMI_FILTER_REGISTER_0_1[] = { + { "Reserved", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSMI_FILTER_REGISTER_1_0[] = { + { "SmiDID_1", 0, 15, &umr_bitfield_default }, + { "SmiDV_1", 16, 16, &umr_bitfield_default }, + { "SmiFLock_1", 17, 17, &umr_bitfield_default }, + { "Reserved", 18, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSMI_FILTER_REGISTER_1_1[] = { + { "Reserved", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSMI_FILTER_REGISTER_2_0[] = { + { "SmiDID_2", 0, 15, &umr_bitfield_default }, + { "SmiDV_2", 16, 16, &umr_bitfield_default }, + { "SmiFLock_2", 17, 17, &umr_bitfield_default }, + { "Reserved", 18, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSMI_FILTER_REGISTER_2_1[] = { + { "Reserved", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSMI_FILTER_REGISTER_3_0[] = { + { "SmiDID_3", 0, 15, &umr_bitfield_default }, + { "SmiDV_3", 16, 16, &umr_bitfield_default }, + { "SmiFLock_3", 17, 17, &umr_bitfield_default }, + { "Reserved", 18, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSMI_FILTER_REGISTER_3_1[] = { + { "Reserved", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_GA_LOG_BASE_0[] = { + { "GA_LOG_BASE_LO", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_GA_LOG_BASE_1[] = { + { "GA_LOG_BASE_HI", 0, 19, &umr_bitfield_default }, + { "GA_LOG_LEN", 24, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_GA_LOG_TAILPTR_ADDR_0[] = { + { "GA_LOG_TAILPTR_ADDR_LO", 3, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_GA_LOG_TAILPTR_ADDR_1[] = { + { "GA_LOG_TAILPTR_ADDR_HI", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_PPR_B_BASE_0[] = { + { "Reserved1", 0, 11, &umr_bitfield_default }, + { "PPR_B_BASE_LO", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_PPR_B_BASE_1[] = { + { "PPR_B_BASE_HI", 0, 19, &umr_bitfield_default }, + { "Reserved1", 20, 23, &umr_bitfield_default }, + { "PPR_B_LEN", 24, 27, &umr_bitfield_default }, + { "Reserved0", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_EVENT_B_BASE_0[] = { + { "Reserved1", 0, 11, &umr_bitfield_default }, + { "EVENT_B_BASE_LO", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_EVENT_B_BASE_1[] = { + { "EVENT_B_BASE_HI", 0, 19, &umr_bitfield_default }, + { "Reserved1", 20, 23, &umr_bitfield_default }, + { "EVENT_B_LEN", 24, 27, &umr_bitfield_default }, + { "Reserved0", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_DEVTBL_1_BASE_0[] = { + { "DEV_TBL_1_SIZE", 0, 8, &umr_bitfield_default }, + { "Reserved1", 9, 11, &umr_bitfield_default }, + { "DEV_TBL_1_BASE_LO", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_DEVTBL_1_BASE_1[] = { + { "DEV_TBL_1_BASE_HI", 0, 19, &umr_bitfield_default }, + { "Reserved0", 20, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_DEVTBL_2_BASE_0[] = { + { "DEV_TBL_2_SIZE", 0, 8, &umr_bitfield_default }, + { "Reserved1", 9, 11, &umr_bitfield_default }, + { "DEV_TBL_2_BASE_LO", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_DEVTBL_2_BASE_1[] = { + { "DEV_TBL_2_BASE_HI", 0, 19, &umr_bitfield_default }, + { "Reserved0", 20, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_DEVTBL_3_BASE_0[] = { + { "DEV_TBL_3_SIZE", 0, 8, &umr_bitfield_default }, + { "Reserved1", 9, 11, &umr_bitfield_default }, + { "DEV_TBL_3_BASE_LO", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_DEVTBL_3_BASE_1[] = { + { "DEV_TBL_3_BASE_HI", 0, 19, &umr_bitfield_default }, + { "Reserved0", 20, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_DEVTBL_4_BASE_0[] = { + { "DEV_TBL_4_SIZE", 0, 8, &umr_bitfield_default }, + { "Reserved1", 9, 11, &umr_bitfield_default }, + { "DEV_TBL_4_BASE_LO", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_DEVTBL_4_BASE_1[] = { + { "DEV_TBL_4_BASE_HI", 0, 19, &umr_bitfield_default }, + { "Reserved0", 20, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_DEVTBL_5_BASE_0[] = { + { "DEV_TBL_5_SIZE", 0, 8, &umr_bitfield_default }, + { "Reserved1", 9, 11, &umr_bitfield_default }, + { "DEV_TBL_5_BASE_LO", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_DEVTBL_5_BASE_1[] = { + { "DEV_TBL_5_BASE_HI", 0, 19, &umr_bitfield_default }, + { "Reserved0", 20, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_DEVTBL_6_BASE_0[] = { + { "DEV_TBL_6_SIZE", 0, 8, &umr_bitfield_default }, + { "Reserved1", 9, 11, &umr_bitfield_default }, + { "DEV_TBL_6_BASE_LO", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_DEVTBL_6_BASE_1[] = { + { "DEV_TBL_6_BASE_HI", 0, 19, &umr_bitfield_default }, + { "Reserved0", 20, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_DEVTBL_7_BASE_0[] = { + { "DEV_TBL_7_SIZE", 0, 8, &umr_bitfield_default }, + { "Reserved1", 9, 11, &umr_bitfield_default }, + { "DEV_TBL_7_BASE_LO", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_DEVTBL_7_BASE_1[] = { + { "DEV_TBL_7_BASE_HI", 0, 19, &umr_bitfield_default }, + { "Reserved0", 20, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_DSFX[] = { + { "DSFXSup", 0, 23, &umr_bitfield_default }, + { "REVISION_MINOR", 24, 27, &umr_bitfield_default }, + { "REVISION_MAJOR", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_DSCX[] = { + { "DSCX_CNTRL", 0, 23, &umr_bitfield_default }, + { "REVISION_MINOR", 24, 27, &umr_bitfield_default }, + { "REVISION_MAJOR", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_DSSX[] = { + { "DSSX_status", 0, 23, &umr_bitfield_default }, + { "REVISION_MINOR", 24, 27, &umr_bitfield_default }, + { "REVISION_MAJOR", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_CAP_MISC[] = { + { "IOMMU_MSI_NUM", 0, 4, &umr_bitfield_default }, + { "Reserved1", 5, 26, &umr_bitfield_default }, + { "IOMMU_MSI_NUM_PPR", 27, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_CAP_MISC_1[] = { + { "IOMMU_MSI_NUM_GA", 0, 4, &umr_bitfield_default }, + { "Reserved", 5, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_MSI_CAP[] = { + { "MSI_CAP_ID", 0, 7, &umr_bitfield_default }, + { "MSI_CAP_PTR", 8, 15, &umr_bitfield_default }, + { "MSI_EN", 16, 16, &umr_bitfield_default }, + { "MSI_MULT_MESS_CAP", 17, 19, &umr_bitfield_default }, + { "MSI_MULT_MESS_EN", 20, 22, &umr_bitfield_default }, + { "MSI_64_EN", 23, 23, &umr_bitfield_default }, + { "Reserved", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_MSI_ADDR_LO[] = { + { "Reserved", 0, 1, &umr_bitfield_default }, + { "MSI_ADDR_LO", 2, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_MSI_ADDR_HI[] = { + { "MSI_ADDR_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_MSI_DATA[] = { + { "MSI_DATA", 0, 15, &umr_bitfield_default }, + { "Reserved", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_MSI_MAPPING_CAP[] = { + { "MSI_MAP_CAP_ID", 0, 7, &umr_bitfield_default }, + { "MSI_MAP_CAP_PTR", 8, 15, &umr_bitfield_default }, + { "MSI_MAP_EN", 16, 16, &umr_bitfield_default }, + { "MSI_MAP_FIXD", 17, 17, &umr_bitfield_default }, + { "MSI_MAP_RSV", 18, 26, &umr_bitfield_default }, + { "MSI_MAP_CAP_TYPE", 27, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_CONTROL_W[] = { + { "Reserved0", 0, 12, &umr_bitfield_default }, + { "GMC_IOMMU_BYPASS", 13, 13, &umr_bitfield_default }, + { "Reserved1", 14, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MARC_BASE_LO_0[] = { + { "Reserved", 0, 11, &umr_bitfield_default }, + { "MARCBaseAddr_L_0", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MARC_BASE_HI_0[] = { + { "MARCBaseAddr_H_0", 0, 19, &umr_bitfield_default }, + { "Reserved", 20, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MARC_RELOC_LO_0[] = { + { "MARCEnable_0", 0, 0, &umr_bitfield_default }, + { "MARCReadOnly_0", 1, 1, &umr_bitfield_default }, + { "Reserved", 2, 11, &umr_bitfield_default }, + { "MARCRelocAddr_L_0", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MARC_RELOC_HI_0[] = { + { "MARCRelocAddr_H_0", 0, 19, &umr_bitfield_default }, + { "Reserved", 20, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MARC_LEN_LO_0[] = { + { "Reserved", 0, 11, &umr_bitfield_default }, + { "MARCLen_L_0", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MARC_LEN_HI_0[] = { + { "MARCLen_H_0", 0, 19, &umr_bitfield_default }, + { "Reserved", 20, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MARC_BASE_LO_1[] = { + { "Reserved", 0, 11, &umr_bitfield_default }, + { "MARCBaseAddr_L_1", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MARC_BASE_HI_1[] = { + { "MARCBaseAddr_H_1", 0, 19, &umr_bitfield_default }, + { "Reserved", 20, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MARC_RELOC_LO_1[] = { + { "MARCEnable_1", 0, 0, &umr_bitfield_default }, + { "MARCReadOnly_1", 1, 1, &umr_bitfield_default }, + { "Reserved", 2, 11, &umr_bitfield_default }, + { "MARCRelocAddr_L_1", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MARC_RELOC_HI_1[] = { + { "MARCRelocAddr_H_1", 0, 19, &umr_bitfield_default }, + { "Reserved", 20, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MARC_LEN_LO_1[] = { + { "Reserved", 0, 11, &umr_bitfield_default }, + { "MARCLen_L_1", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MARC_LEN_HI_1[] = { + { "MARCLen_H_1", 0, 19, &umr_bitfield_default }, + { "Reserved", 20, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MARC_BASE_LO_2[] = { + { "Reserved", 0, 11, &umr_bitfield_default }, + { "MARCBaseAddr_L_2", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MARC_BASE_HI_2[] = { + { "MARCBaseAddr_H_2", 0, 19, &umr_bitfield_default }, + { "Reserved", 20, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MARC_RELOC_LO_2[] = { + { "MARCEnable_2", 0, 0, &umr_bitfield_default }, + { "MARCReadOnly_2", 1, 1, &umr_bitfield_default }, + { "Reserved", 2, 11, &umr_bitfield_default }, + { "MARCRelocAddr_L_2", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MARC_RELOC_HI_2[] = { + { "MARCRelocAddr_H_2", 0, 19, &umr_bitfield_default }, + { "Reserved", 20, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MARC_LEN_LO_2[] = { + { "Reserved", 0, 11, &umr_bitfield_default }, + { "MARCLen_L_2", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MARC_LEN_HI_2[] = { + { "MARCLen_H_2", 0, 19, &umr_bitfield_default }, + { "Reserved", 20, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MARC_BASE_LO_3[] = { + { "Reserved", 0, 11, &umr_bitfield_default }, + { "MARCBaseAddr_L_3", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MARC_BASE_HI_3[] = { + { "MARCBaseAddr_H_3", 0, 19, &umr_bitfield_default }, + { "Reserved", 20, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MARC_RELOC_LO_3[] = { + { "MARCEnable_3", 0, 0, &umr_bitfield_default }, + { "MARCReadOnly_3", 1, 1, &umr_bitfield_default }, + { "Reserved", 2, 11, &umr_bitfield_default }, + { "MARCRelocAddr_L_3", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MARC_RELOC_HI_3[] = { + { "MARCRelocAddr_H_3", 0, 19, &umr_bitfield_default }, + { "Reserved", 20, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MARC_LEN_LO_3[] = { + { "Reserved", 0, 11, &umr_bitfield_default }, + { "MARCLen_L_3", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MARC_LEN_HI_3[] = { + { "MARCLen_H_3", 0, 19, &umr_bitfield_default }, + { "Reserved", 20, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_CMD_BUF_HDPTR_0[] = { + { "Reserved0", 0, 3, &umr_bitfield_default }, + { "CMD_HDPTR", 4, 18, &umr_bitfield_default }, + { "Reserved1", 19, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_CMD_BUF_HDPTR_1[] = { + { "Reserved0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_CMD_BUF_TAILPTR_0[] = { + { "Reserved0", 0, 3, &umr_bitfield_default }, + { "CMD_TAILPTR", 4, 18, &umr_bitfield_default }, + { "Reserved1", 19, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_CMD_BUF_TAILPTR_1[] = { + { "Reserved0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_EVENT_BUF_HDPTR_0[] = { + { "Reserved0", 0, 3, &umr_bitfield_default }, + { "EVENT_HDPTR", 4, 18, &umr_bitfield_default }, + { "Reserved1", 19, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_EVENT_BUF_HDPTR_1[] = { + { "Reserved0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_EVENT_BUF_TAILPTR_0[] = { + { "Reserved0", 0, 3, &umr_bitfield_default }, + { "EVENT_TAILPTR", 4, 18, &umr_bitfield_default }, + { "Reserved1", 19, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_EVENT_BUF_TAILPTR_1[] = { + { "Reserved0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_STATUS_0[] = { + { "EVENT_OVERFLOW", 0, 0, &umr_bitfield_default }, + { "EVENT_LOGINT", 1, 1, &umr_bitfield_default }, + { "COMWAIT_INT", 2, 2, &umr_bitfield_default }, + { "EVENT_LOGRUN", 3, 3, &umr_bitfield_default }, + { "CMD_BUFRUN", 4, 4, &umr_bitfield_default }, + { "PPR_OVERFLOW", 5, 5, &umr_bitfield_default }, + { "PPR_INT", 6, 6, &umr_bitfield_default }, + { "PPR_RUN", 7, 7, &umr_bitfield_default }, + { "GA_RUN", 8, 8, &umr_bitfield_default }, + { "GA_OVERFLOW", 9, 9, &umr_bitfield_default }, + { "GA_INT", 10, 10, &umr_bitfield_default }, + { "PPR_B_OVERFLOW", 11, 11, &umr_bitfield_default }, + { "PPR_BUF_ACTIVE", 12, 12, &umr_bitfield_default }, + { "Reserved0", 13, 14, &umr_bitfield_default }, + { "EVENT_B_OVERFLOW", 15, 15, &umr_bitfield_default }, + { "EVENT_BUF_ACTIVE", 16, 16, &umr_bitfield_default }, + { "PPR_B_OVERFLOW_EARLY", 17, 17, &umr_bitfield_default }, + { "PPR_OVERFLOW_EARLY", 18, 18, &umr_bitfield_default }, + { "Reserved1", 19, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_STATUS_1[] = { + { "Reserved0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_PPR_BUF_HDPTR_0[] = { + { "Reserved0", 0, 3, &umr_bitfield_default }, + { "PPR_HDPTR", 4, 18, &umr_bitfield_default }, + { "Reserved1", 19, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_PPR_BUF_HDPTR_1[] = { + { "Reserved0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_PPR_BUF_TAILPTR_0[] = { + { "Reserved0", 0, 3, &umr_bitfield_default }, + { "PPR_TAILPTR", 4, 18, &umr_bitfield_default }, + { "Reserved1", 19, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_PPR_BUF_TAILPTR_1[] = { + { "Reserved0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_GA_BUF_HDPTR_0[] = { + { "Reserved0", 0, 2, &umr_bitfield_default }, + { "GA_HDPTR", 3, 15, &umr_bitfield_default }, + { "Reserved1", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_GA_BUF_HDPTR_1[] = { + { "Reserved0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_GA_BUF_TAILPTR_0[] = { + { "Reserved0", 0, 2, &umr_bitfield_default }, + { "GA_TAILPTR", 3, 15, &umr_bitfield_default }, + { "Reserved1", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_GA_BUF_TAILPTR_1[] = { + { "Reserved0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_PPR_B_BUF_HDPTR_0[] = { + { "Reserved0", 0, 3, &umr_bitfield_default }, + { "PPR_B_HDPTR", 4, 18, &umr_bitfield_default }, + { "Reserved1", 19, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_PPR_B_BUF_HDPTR_1[] = { + { "Reserved0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_PPR_B_BUF_TAILPTR_0[] = { + { "Reserved0", 0, 3, &umr_bitfield_default }, + { "PPR_B_TAILPTR", 4, 18, &umr_bitfield_default }, + { "Reserved1", 19, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_PPR_B_BUF_TAILPTR_1[] = { + { "Reserved0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_EVENT_B_BUF_HDPTR_0[] = { + { "Reserved0", 0, 3, &umr_bitfield_default }, + { "EVENT_B_HDPTR", 4, 18, &umr_bitfield_default }, + { "Reserved1", 19, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_EVENT_B_BUF_HDPTR_1[] = { + { "Reserved0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_EVENT_B_BUF_TAILPTR_0[] = { + { "Reserved0", 0, 3, &umr_bitfield_default }, + { "EVENT_B_TAILPTR", 4, 18, &umr_bitfield_default }, + { "Reserved1", 19, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_EVENT_B_BUF_TAILPTR_1[] = { + { "Reserved0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_PPR_AUTORESP_0[] = { + { "PPR_Auto_resp_code", 0, 3, &umr_bitfield_default }, + { "PPR_Auto_resp_mask_gn", 4, 4, &umr_bitfield_default }, + { "Reserved0", 5, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_PPR_OVERFLOW_EARLY_0[] = { + { "PPR_Overflow_early_threshold", 0, 14, &umr_bitfield_default }, + { "Reserved0", 15, 29, &umr_bitfield_default }, + { "PPR_Overflow_early_int_en", 30, 30, &umr_bitfield_default }, + { "PPR_Overflow_early_en", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0[] = { + { "PPR_B_Overflow_early_threshold", 0, 14, &umr_bitfield_default }, + { "Reserved0", 15, 29, &umr_bitfield_default }, + { "PPR_B_Overflow_early_int_en", 30, 30, &umr_bitfield_default }, + { "PPR_B_Overflow_early_en", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_COUNTER_CONFIG_0[] = { + { "Reserved0", 0, 6, &umr_bitfield_default }, + { "N_COUNTER", 7, 10, &umr_bitfield_default }, + { "Reserved1", 11, 11, &umr_bitfield_default }, + { "N_COUNTER_BANKS", 12, 17, &umr_bitfield_default }, + { "Reserved2", 18, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_COUNTER_CONFIG_1[] = { + { "Reserved0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_COUNTER_PASID_BANK_LOCK_0[] = { + { "PASID_LOCK_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_COUNTER_PASID_BANK_LOCK_1[] = { + { "PASID_LOCK_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_0[] = { + { "DOMAIN_LOCK_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_1[] = { + { "DOMAIN_LOCK_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_0[] = { + { "DEVID_LOCK_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_1[] = { + { "DEVID_LOCK_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_COUNTER_BANK_0_CNT_0_0[] = { + { "ICOUNTER_0_0_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_COUNTER_BANK_0_CNT_0_1[] = { + { "ICOUNTER_0_0_HI", 0, 15, &umr_bitfield_default }, + { "Reserved", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0[] = { + { "CSOURCE_0_0", 0, 7, &umr_bitfield_default }, + { "Reserved1", 8, 29, &umr_bitfield_default }, + { "COUNT_UNITS_0_0", 30, 30, &umr_bitfield_default }, + { "CAC_0_0", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_1[] = { + { "Reserved0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0[] = { + { "PASID_MATCH_0_0", 0, 15, &umr_bitfield_default }, + { "Reserved1", 16, 30, &umr_bitfield_default }, + { "PASMEN_0_0", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1[] = { + { "PASID_MASK_0_0", 0, 15, &umr_bitfield_default }, + { "Reserved0", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0[] = { + { "DOMAIN_MATCH_0_0", 0, 15, &umr_bitfield_default }, + { "Reserved1", 16, 30, &umr_bitfield_default }, + { "DOMMEN_0_0", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1[] = { + { "DOMAIN_MASK_0_0", 0, 15, &umr_bitfield_default }, + { "Reserved0", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0[] = { + { "DEVICEID_MATCH_0_0", 0, 15, &umr_bitfield_default }, + { "Reserved1", 16, 30, &umr_bitfield_default }, + { "DIDMEN_0_0", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1[] = { + { "DEVICEID_MASK_0_0", 0, 15, &umr_bitfield_default }, + { "Reserved0", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_0[] = { + { "EVENT_NOTE_0_0_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1[] = { + { "EVENT_NOTE_0_0_HI", 0, 19, &umr_bitfield_default }, + { "Reserved0", 20, 30, &umr_bitfield_default }, + { "CERE_0_0", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_COUNTER_BANK_0_CNT_1_0[] = { + { "ICOUNTER_0_1_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_COUNTER_BANK_0_CNT_1_1[] = { + { "ICOUNTER_0_1_HI", 0, 15, &umr_bitfield_default }, + { "Reserved", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0[] = { + { "CSOURCE_0_1", 0, 7, &umr_bitfield_default }, + { "Reserved1", 8, 29, &umr_bitfield_default }, + { "COUNT_UNITS_0_1", 30, 30, &umr_bitfield_default }, + { "CAC_0_1", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_1[] = { + { "Reserved0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0[] = { + { "PASID_MATCH_0_1", 0, 15, &umr_bitfield_default }, + { "Reserved1", 16, 30, &umr_bitfield_default }, + { "PASMEN_0_1", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1[] = { + { "PASID_MASK_0_1", 0, 15, &umr_bitfield_default }, + { "Reserved0", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0[] = { + { "DOMAIN_MATCH_0_1", 0, 15, &umr_bitfield_default }, + { "Reserved1", 16, 30, &umr_bitfield_default }, + { "DOMMEN_0_1", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1[] = { + { "DOMAIN_MASK_0_1", 0, 15, &umr_bitfield_default }, + { "Reserved0", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0[] = { + { "DEVICEID_MATCH_0_1", 0, 15, &umr_bitfield_default }, + { "Reserved1", 16, 30, &umr_bitfield_default }, + { "DIDMEN_0_1", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1[] = { + { "DEVICEID_MASK_0_1", 0, 15, &umr_bitfield_default }, + { "Reserved0", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_0[] = { + { "EVENT_NOTE_0_1_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1[] = { + { "EVENT_NOTE_0_1_HI", 0, 19, &umr_bitfield_default }, + { "Reserved0", 20, 30, &umr_bitfield_default }, + { "CERE_0_1", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_COUNTER_BANK_0_CNT_2_0[] = { + { "ICOUNTER_0_2_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_COUNTER_BANK_0_CNT_2_1[] = { + { "ICOUNTER_0_2_HI", 0, 15, &umr_bitfield_default }, + { "Reserved", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0[] = { + { "CSOURCE_0_2", 0, 7, &umr_bitfield_default }, + { "Reserved1", 8, 29, &umr_bitfield_default }, + { "COUNT_UNITS_0_2", 30, 30, &umr_bitfield_default }, + { "CAC_0_2", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_1[] = { + { "Reserved0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0[] = { + { "PASID_MATCH_0_2", 0, 15, &umr_bitfield_default }, + { "Reserved1", 16, 30, &umr_bitfield_default }, + { "PASMEN_0_2", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1[] = { + { "PASID_MASK_0_2", 0, 15, &umr_bitfield_default }, + { "Reserved0", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0[] = { + { "DOMAIN_MATCH_0_2", 0, 15, &umr_bitfield_default }, + { "Reserved1", 16, 30, &umr_bitfield_default }, + { "DOMMEN_0_2", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1[] = { + { "DOMAIN_MASK_0_2", 0, 15, &umr_bitfield_default }, + { "Reserved0", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0[] = { + { "DEVICEID_MATCH_0_2", 0, 15, &umr_bitfield_default }, + { "Reserved1", 16, 30, &umr_bitfield_default }, + { "DIDMEN_0_2", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1[] = { + { "DEVICEID_MASK_0_2", 0, 15, &umr_bitfield_default }, + { "Reserved0", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_0[] = { + { "EVENT_NOTE_0_2_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1[] = { + { "EVENT_NOTE_0_2_HI", 0, 19, &umr_bitfield_default }, + { "Reserved0", 20, 30, &umr_bitfield_default }, + { "CERE_0_2", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_COUNTER_BANK_0_CNT_3_0[] = { + { "ICOUNTER_0_3_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_COUNTER_BANK_0_CNT_3_1[] = { + { "ICOUNTER_0_3_HI", 0, 15, &umr_bitfield_default }, + { "Reserved", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0[] = { + { "CSOURCE_0_3", 0, 7, &umr_bitfield_default }, + { "Reserved1", 8, 29, &umr_bitfield_default }, + { "COUNT_UNITS_0_3", 30, 30, &umr_bitfield_default }, + { "CAC_0_3", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_1[] = { + { "Reserved0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0[] = { + { "PASID_MATCH_0_3", 0, 15, &umr_bitfield_default }, + { "Reserved1", 16, 30, &umr_bitfield_default }, + { "PASMEN_0_3", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1[] = { + { "PASID_MASK_0_3", 0, 15, &umr_bitfield_default }, + { "Reserved0", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0[] = { + { "DOMAIN_MATCH_0_3", 0, 15, &umr_bitfield_default }, + { "Reserved1", 16, 30, &umr_bitfield_default }, + { "DOMMEN_0_3", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1[] = { + { "DOMAIN_MASK_0_3", 0, 15, &umr_bitfield_default }, + { "Reserved0", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0[] = { + { "DEVICEID_MATCH_0_3", 0, 15, &umr_bitfield_default }, + { "Reserved1", 16, 30, &umr_bitfield_default }, + { "DIDMEN_0_3", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1[] = { + { "DEVICEID_MASK_0_3", 0, 15, &umr_bitfield_default }, + { "Reserved0", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_0[] = { + { "EVENT_NOTE_0_3_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1[] = { + { "EVENT_NOTE_0_3_HI", 0, 19, &umr_bitfield_default }, + { "Reserved0", 20, 30, &umr_bitfield_default }, + { "CERE_0_3", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_COUNTER_BANK_1_CNT_0_0[] = { + { "ICOUNTER_1_0_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_COUNTER_BANK_1_CNT_0_1[] = { + { "ICOUNTER_1_0_HI", 0, 15, &umr_bitfield_default }, + { "Reserved", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0[] = { + { "CSOURCE_1_0", 0, 7, &umr_bitfield_default }, + { "Reserved1", 8, 29, &umr_bitfield_default }, + { "COUNT_UNITS_1_0", 30, 30, &umr_bitfield_default }, + { "CAC_1_0", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_1[] = { + { "Reserved0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0[] = { + { "PASID_MATCH_1_0", 0, 15, &umr_bitfield_default }, + { "Reserved1", 16, 30, &umr_bitfield_default }, + { "PASMEN_1_0", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1[] = { + { "PASID_MASK_1_0", 0, 15, &umr_bitfield_default }, + { "Reserved0", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0[] = { + { "DOMAIN_MATCH_1_0", 0, 15, &umr_bitfield_default }, + { "Reserved1", 16, 30, &umr_bitfield_default }, + { "DOMMEN_1_0", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1[] = { + { "DOMAIN_MASK_1_0", 0, 15, &umr_bitfield_default }, + { "Reserved0", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0[] = { + { "DEVICEID_MATCH_1_0", 0, 15, &umr_bitfield_default }, + { "Reserved1", 16, 30, &umr_bitfield_default }, + { "DIDMEN_1_0", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1[] = { + { "DEVICEID_MASK_1_0", 0, 15, &umr_bitfield_default }, + { "Reserved0", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_0[] = { + { "EVENT_NOTE_1_0_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1[] = { + { "EVENT_NOTE_1_0_HI", 0, 19, &umr_bitfield_default }, + { "Reserved0", 20, 30, &umr_bitfield_default }, + { "CERE_1_0", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_COUNTER_BANK_1_CNT_1_0[] = { + { "ICOUNTER_1_1_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_COUNTER_BANK_1_CNT_1_1[] = { + { "ICOUNTER_1_1_HI", 0, 15, &umr_bitfield_default }, + { "Reserved", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0[] = { + { "CSOURCE_1_1", 0, 7, &umr_bitfield_default }, + { "Reserved1", 8, 29, &umr_bitfield_default }, + { "COUNT_UNITS_1_1", 30, 30, &umr_bitfield_default }, + { "CAC_1_1", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_1[] = { + { "Reserved0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0[] = { + { "PASID_MATCH_1_1", 0, 15, &umr_bitfield_default }, + { "Reserved1", 16, 30, &umr_bitfield_default }, + { "PASMEN_1_1", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1[] = { + { "PASID_MASK_1_1", 0, 15, &umr_bitfield_default }, + { "Reserved0", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0[] = { + { "DOMAIN_MATCH_1_1", 0, 15, &umr_bitfield_default }, + { "Reserved1", 16, 30, &umr_bitfield_default }, + { "DOMMEN_1_1", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1[] = { + { "DOMAIN_MASK_1_1", 0, 15, &umr_bitfield_default }, + { "Reserved0", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0[] = { + { "DEVICEID_MATCH_1_1", 0, 15, &umr_bitfield_default }, + { "Reserved1", 16, 30, &umr_bitfield_default }, + { "DIDMEN_1_1", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1[] = { + { "DEVICEID_MASK_1_1", 0, 15, &umr_bitfield_default }, + { "Reserved0", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_0[] = { + { "EVENT_NOTE_1_1_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1[] = { + { "EVENT_NOTE_1_1_HI", 0, 19, &umr_bitfield_default }, + { "Reserved0", 20, 30, &umr_bitfield_default }, + { "CERE_1_1", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_COUNTER_BANK_1_CNT_2_0[] = { + { "ICOUNTER_1_2_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_COUNTER_BANK_1_CNT_2_1[] = { + { "ICOUNTER_1_2_HI", 0, 15, &umr_bitfield_default }, + { "Reserved", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0[] = { + { "CSOURCE_1_2", 0, 7, &umr_bitfield_default }, + { "Reserved1", 8, 29, &umr_bitfield_default }, + { "COUNT_UNITS_1_2", 30, 30, &umr_bitfield_default }, + { "CAC_1_2", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_1[] = { + { "Reserved0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0[] = { + { "PASID_MATCH_1_2", 0, 15, &umr_bitfield_default }, + { "Reserved1", 16, 30, &umr_bitfield_default }, + { "PASMEN_1_2", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1[] = { + { "PASID_MASK_1_2", 0, 15, &umr_bitfield_default }, + { "Reserved0", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0[] = { + { "DOMAIN_MATCH_1_2", 0, 15, &umr_bitfield_default }, + { "Reserved1", 16, 30, &umr_bitfield_default }, + { "DOMMEN_1_2", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1[] = { + { "DOMAIN_MASK_1_2", 0, 15, &umr_bitfield_default }, + { "Reserved0", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0[] = { + { "DEVICEID_MATCH_1_2", 0, 15, &umr_bitfield_default }, + { "Reserved1", 16, 30, &umr_bitfield_default }, + { "DIDMEN_1_2", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1[] = { + { "DEVICEID_MASK_1_2", 0, 15, &umr_bitfield_default }, + { "Reserved0", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_0[] = { + { "EVENT_NOTE_1_2_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1[] = { + { "EVENT_NOTE_1_2_HI", 0, 19, &umr_bitfield_default }, + { "Reserved0", 20, 30, &umr_bitfield_default }, + { "CERE_1_2", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_COUNTER_BANK_1_CNT_3_0[] = { + { "ICOUNTER_1_3_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_COUNTER_BANK_1_CNT_3_1[] = { + { "ICOUNTER_1_3_HI", 0, 15, &umr_bitfield_default }, + { "Reserved", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0[] = { + { "CSOURCE_1_3", 0, 7, &umr_bitfield_default }, + { "Reserved1", 8, 29, &umr_bitfield_default }, + { "COUNT_UNITS_1_3", 30, 30, &umr_bitfield_default }, + { "CAC_1_3", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_1[] = { + { "Reserved0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0[] = { + { "PASID_MATCH_1_3", 0, 15, &umr_bitfield_default }, + { "Reserved1", 16, 30, &umr_bitfield_default }, + { "PASMEN_1_3", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1[] = { + { "PASID_MASK_1_3", 0, 15, &umr_bitfield_default }, + { "Reserved0", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0[] = { + { "DOMAIN_MATCH_1_3", 0, 15, &umr_bitfield_default }, + { "Reserved1", 16, 30, &umr_bitfield_default }, + { "DOMMEN_1_3", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1[] = { + { "DOMAIN_MASK_1_3", 0, 15, &umr_bitfield_default }, + { "Reserved0", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0[] = { + { "DEVICEID_MATCH_1_3", 0, 15, &umr_bitfield_default }, + { "Reserved1", 16, 30, &umr_bitfield_default }, + { "DIDMEN_1_3", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1[] = { + { "DEVICEID_MASK_1_3", 0, 15, &umr_bitfield_default }, + { "Reserved0", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_0[] = { + { "EVENT_NOTE_1_3_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1[] = { + { "EVENT_NOTE_1_3_HI", 0, 19, &umr_bitfield_default }, + { "Reserved0", 20, 30, &umr_bitfield_default }, + { "CERE_1_3", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMM_INDEX[] = { + { "MM_OFFSET", 0, 30, &umr_bitfield_default }, + { "MM_APER", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMM_DATA[] = { + { "MM_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMM_INDEX_HI[] = { + { "MM_OFFSET_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSYSHUB_INDEX_OVLP[] = { + { "SYSHUB_OFFSET", 0, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSYSHUB_DATA_OVLP[] = { + { "SYSHUB_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPCIE_INDEX[] = { + { "PCIE_INDEX", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPCIE_DATA[] = { + { "PCIE_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPCIE_INDEX2[] = { + { "PCIE_INDEX2", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPCIE_DATA2[] = { + { "PCIE_DATA2", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSBIOS_SCRATCH_0[] = { + { "SBIOS_SCRATCH_DW", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSBIOS_SCRATCH_1[] = { + { "SBIOS_SCRATCH_DW", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSBIOS_SCRATCH_2[] = { + { "SBIOS_SCRATCH_DW", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSBIOS_SCRATCH_3[] = { + { "SBIOS_SCRATCH_DW", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIOS_SCRATCH_0[] = { + { "BIOS_SCRATCH_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIOS_SCRATCH_1[] = { + { "BIOS_SCRATCH_1", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIOS_SCRATCH_2[] = { + { "BIOS_SCRATCH_2", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIOS_SCRATCH_3[] = { + { "BIOS_SCRATCH_3", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIOS_SCRATCH_4[] = { + { "BIOS_SCRATCH_4", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIOS_SCRATCH_5[] = { + { "BIOS_SCRATCH_5", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIOS_SCRATCH_6[] = { + { "BIOS_SCRATCH_6", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIOS_SCRATCH_7[] = { + { "BIOS_SCRATCH_7", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIOS_SCRATCH_8[] = { + { "BIOS_SCRATCH_8", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIOS_SCRATCH_9[] = { + { "BIOS_SCRATCH_9", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIOS_SCRATCH_10[] = { + { "BIOS_SCRATCH_10", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIOS_SCRATCH_11[] = { + { "BIOS_SCRATCH_11", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIOS_SCRATCH_12[] = { + { "BIOS_SCRATCH_12", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIOS_SCRATCH_13[] = { + { "BIOS_SCRATCH_13", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIOS_SCRATCH_14[] = { + { "BIOS_SCRATCH_14", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIOS_SCRATCH_15[] = { + { "BIOS_SCRATCH_15", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIF_RLC_INTR_CNTL[] = { + { "RLC_CMD_COMPLETE", 0, 0, &umr_bitfield_default }, + { "RLC_HANG_SELF_RECOVERED", 1, 1, &umr_bitfield_default }, + { "RLC_HANG_NEED_FLR", 2, 2, &umr_bitfield_default }, + { "RLC_VM_BUSY_TRANSITION", 3, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIF_VCE_INTR_CNTL[] = { + { "VCE_CMD_COMPLETE", 0, 0, &umr_bitfield_default }, + { "VCE_HANG_SELF_RECOVERED", 1, 1, &umr_bitfield_default }, + { "VCE_HANG_NEED_FLR", 2, 2, &umr_bitfield_default }, + { "VCE_VM_BUSY_TRANSITION", 3, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIF_UVD_INTR_CNTL[] = { + { "UVD_CMD_COMPLETE", 0, 0, &umr_bitfield_default }, + { "UVD_HANG_SELF_RECOVERED", 1, 1, &umr_bitfield_default }, + { "UVD_HANG_NEED_FLR", 2, 2, &umr_bitfield_default }, + { "UVD_VM_BUSY_TRANSITION", 3, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGFX_MMIOREG_CAM_ADDR0[] = { + { "CAM_ADDR0", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGFX_MMIOREG_CAM_REMAP_ADDR0[] = { + { "CAM_REMAP_ADDR0", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGFX_MMIOREG_CAM_ADDR1[] = { + { "CAM_ADDR1", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGFX_MMIOREG_CAM_REMAP_ADDR1[] = { + { "CAM_REMAP_ADDR1", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGFX_MMIOREG_CAM_ADDR2[] = { + { "CAM_ADDR2", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGFX_MMIOREG_CAM_REMAP_ADDR2[] = { + { "CAM_REMAP_ADDR2", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGFX_MMIOREG_CAM_ADDR3[] = { + { "CAM_ADDR3", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGFX_MMIOREG_CAM_REMAP_ADDR3[] = { + { "CAM_REMAP_ADDR3", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGFX_MMIOREG_CAM_ADDR4[] = { + { "CAM_ADDR4", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGFX_MMIOREG_CAM_REMAP_ADDR4[] = { + { "CAM_REMAP_ADDR4", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGFX_MMIOREG_CAM_ADDR5[] = { + { "CAM_ADDR5", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGFX_MMIOREG_CAM_REMAP_ADDR5[] = { + { "CAM_REMAP_ADDR5", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGFX_MMIOREG_CAM_ADDR6[] = { + { "CAM_ADDR6", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGFX_MMIOREG_CAM_REMAP_ADDR6[] = { + { "CAM_REMAP_ADDR6", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGFX_MMIOREG_CAM_ADDR7[] = { + { "CAM_ADDR7", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGFX_MMIOREG_CAM_REMAP_ADDR7[] = { + { "CAM_REMAP_ADDR7", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGFX_MMIOREG_CAM_CNTL[] = { + { "CAM_ENABLE", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGFX_MMIOREG_CAM_ZERO_CPL[] = { + { "CAM_ZERO_CPL", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGFX_MMIOREG_CAM_ONE_CPL[] = { + { "CAM_ONE_CPL", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL[] = { + { "CAM_PROGRAMMABLE_CPL", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSYSHUB_INDEX[] = { + { "INDEX", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSYSHUB_DATA[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRCC_DEV0_EPF0_STRAP0[] = { + { "STRAP_DEVICE_ID_DEV0_F0", 0, 15, &umr_bitfield_default }, + { "STRAP_MAJOR_REV_ID_DEV0_F0", 16, 19, &umr_bitfield_default }, + { "STRAP_MINOR_REV_ID_DEV0_F0", 20, 23, &umr_bitfield_default }, + { "STRAP_ATI_REV_ID_DEV0_F0", 24, 27, &umr_bitfield_default }, + { "STRAP_FUNC_EN_DEV0_F0", 28, 28, &umr_bitfield_default }, + { "STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0", 29, 29, &umr_bitfield_default }, + { "STRAP_D1_SUPPORT_DEV0_F0", 30, 30, &umr_bitfield_default }, + { "STRAP_D2_SUPPORT_DEV0_F0", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmEP_PCIE_SCRATCH[] = { + { "PCIE_SCRATCH", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmEP_PCIE_CNTL[] = { + { "UR_ERR_REPORT_DIS", 7, 7, &umr_bitfield_default }, + { "PCIE_MALFORM_ATOMIC_OPS", 8, 8, &umr_bitfield_default }, + { "RX_IGNORE_LTR_MSG_UR", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmEP_PCIE_INT_CNTL[] = { + { "CORR_ERR_INT_EN", 0, 0, &umr_bitfield_default }, + { "NON_FATAL_ERR_INT_EN", 1, 1, &umr_bitfield_default }, + { "FATAL_ERR_INT_EN", 2, 2, &umr_bitfield_default }, + { "USR_DETECTED_INT_EN", 3, 3, &umr_bitfield_default }, + { "MISC_ERR_INT_EN", 4, 4, &umr_bitfield_default }, + { "POWER_STATE_CHG_INT_EN", 6, 6, &umr_bitfield_default }, +}; +static struct umr_bitfield mmEP_PCIE_INT_STATUS[] = { + { "CORR_ERR_INT_STATUS", 0, 0, &umr_bitfield_default }, + { "NON_FATAL_ERR_INT_STATUS", 1, 1, &umr_bitfield_default }, + { "FATAL_ERR_INT_STATUS", 2, 2, &umr_bitfield_default }, + { "USR_DETECTED_INT_STATUS", 3, 3, &umr_bitfield_default }, + { "MISC_ERR_INT_STATUS", 4, 4, &umr_bitfield_default }, + { "POWER_STATE_CHG_INT_STATUS", 6, 6, &umr_bitfield_default }, +}; +static struct umr_bitfield mmEP_PCIE_RX_CNTL2[] = { + { "RX_IGNORE_EP_INVALIDPASID_UR", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmEP_PCIE_BUS_CNTL[] = { + { "IMMEDIATE_PMI_DIS", 7, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmEP_PCIE_CFG_CNTL[] = { + { "CFG_EN_DEC_TO_HIDDEN_REG", 0, 0, &umr_bitfield_default }, + { "CFG_EN_DEC_TO_GEN2_HIDDEN_REG", 1, 1, &umr_bitfield_default }, + { "CFG_EN_DEC_TO_GEN3_HIDDEN_REG", 2, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmEP_PCIE_TX_LTR_CNTL[] = { + { "LTR_PRIV_S_SHORT_VALUE", 0, 2, &umr_bitfield_default }, + { "LTR_PRIV_S_LONG_VALUE", 3, 5, &umr_bitfield_default }, + { "LTR_PRIV_S_REQUIREMENT", 6, 6, &umr_bitfield_default }, + { "LTR_PRIV_NS_SHORT_VALUE", 7, 9, &umr_bitfield_default }, + { "LTR_PRIV_NS_LONG_VALUE", 10, 12, &umr_bitfield_default }, + { "LTR_PRIV_NS_REQUIREMENT", 13, 13, &umr_bitfield_default }, + { "LTR_PRIV_MSG_DIS_IN_PM_NON_D0", 14, 14, &umr_bitfield_default }, + { "LTR_PRIV_RST_LTR_IN_DL_DOWN", 15, 15, &umr_bitfield_default }, + { "TX_CHK_FC_FOR_L1", 16, 16, &umr_bitfield_default }, + { "LTR_DSTATE_USING_WDATA_EN", 17, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0[] = { + { "SUBSTATE_PWR_ALLOC", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1[] = { + { "SUBSTATE_PWR_ALLOC", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2[] = { + { "SUBSTATE_PWR_ALLOC", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3[] = { + { "SUBSTATE_PWR_ALLOC", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4[] = { + { "SUBSTATE_PWR_ALLOC", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5[] = { + { "SUBSTATE_PWR_ALLOC", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6[] = { + { "SUBSTATE_PWR_ALLOC", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7[] = { + { "SUBSTATE_PWR_ALLOC", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmEP_PCIE_F0_DPA_CAP[] = { + { "TRANS_LAT_UNIT", 8, 9, &umr_bitfield_default }, + { "PWR_ALLOC_SCALE", 12, 13, &umr_bitfield_default }, + { "TRANS_LAT_VAL_0", 16, 23, &umr_bitfield_default }, + { "TRANS_LAT_VAL_1", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmEP_PCIE_F0_DPA_LATENCY_INDICATOR[] = { + { "TRANS_LAT_INDICATOR_BITS", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmEP_PCIE_F0_DPA_CNTL[] = { + { "SUBSTATE_STATUS", 0, 4, &umr_bitfield_default }, + { "DPA_COMPLIANCE_MODE", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0[] = { + { "SUBSTATE_PWR_ALLOC", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1[] = { + { "SUBSTATE_PWR_ALLOC", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2[] = { + { "SUBSTATE_PWR_ALLOC", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3[] = { + { "SUBSTATE_PWR_ALLOC", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4[] = { + { "SUBSTATE_PWR_ALLOC", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5[] = { + { "SUBSTATE_PWR_ALLOC", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6[] = { + { "SUBSTATE_PWR_ALLOC", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7[] = { + { "SUBSTATE_PWR_ALLOC", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmEP_PCIE_PME_CONTROL[] = { + { "PME_SERVICE_TIMER", 0, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmEP_PCIEP_RESERVED[] = { + { "PCIEP_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmEP_PCIE_TX_CNTL[] = { + { "TX_SNR_OVERRIDE", 10, 11, &umr_bitfield_default }, + { "TX_RO_OVERRIDE", 12, 13, &umr_bitfield_default }, + { "TX_F0_TPH_DIS", 24, 24, &umr_bitfield_default }, + { "TX_F1_TPH_DIS", 25, 25, &umr_bitfield_default }, + { "TX_F2_TPH_DIS", 26, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmEP_PCIE_TX_REQUESTER_ID[] = { + { "TX_REQUESTER_ID_FUNCTION", 0, 2, &umr_bitfield_default }, + { "TX_REQUESTER_ID_DEVICE", 3, 7, &umr_bitfield_default }, + { "TX_REQUESTER_ID_BUS", 8, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmEP_PCIE_ERR_CNTL[] = { + { "ERR_REPORTING_DIS", 0, 0, &umr_bitfield_default }, + { "AER_HDR_LOG_TIMEOUT", 8, 10, &umr_bitfield_default }, + { "SEND_ERR_MSG_IMMEDIATELY", 17, 17, &umr_bitfield_default }, + { "STRAP_POISONED_ADVISORY_NONFATAL", 18, 18, &umr_bitfield_default }, + { "AER_HDR_LOG_F0_TIMER_EXPIRED", 24, 24, &umr_bitfield_default }, + { "AER_HDR_LOG_F1_TIMER_EXPIRED", 25, 25, &umr_bitfield_default }, + { "AER_HDR_LOG_F2_TIMER_EXPIRED", 26, 26, &umr_bitfield_default }, + { "AER_HDR_LOG_F3_TIMER_EXPIRED", 27, 27, &umr_bitfield_default }, + { "AER_HDR_LOG_F4_TIMER_EXPIRED", 28, 28, &umr_bitfield_default }, + { "AER_HDR_LOG_F5_TIMER_EXPIRED", 29, 29, &umr_bitfield_default }, + { "AER_HDR_LOG_F6_TIMER_EXPIRED", 30, 30, &umr_bitfield_default }, + { "AER_HDR_LOG_F7_TIMER_EXPIRED", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmEP_PCIE_RX_CNTL[] = { + { "RX_IGNORE_MAX_PAYLOAD_ERR", 8, 8, &umr_bitfield_default }, + { "RX_IGNORE_TC_ERR", 9, 9, &umr_bitfield_default }, + { "RX_PCIE_CPL_TIMEOUT_DIS", 20, 20, &umr_bitfield_default }, + { "RX_IGNORE_SHORTPREFIX_ERR", 21, 21, &umr_bitfield_default }, + { "RX_IGNORE_MAXPREFIX_ERR", 22, 22, &umr_bitfield_default }, + { "RX_IGNORE_INVALIDPASID_ERR", 24, 24, &umr_bitfield_default }, + { "RX_IGNORE_NOT_PASID_UR", 25, 25, &umr_bitfield_default }, + { "RX_TPH_DIS", 26, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmEP_PCIE_LC_SPEED_CNTL[] = { + { "LC_GEN2_EN_STRAP", 0, 0, &umr_bitfield_default }, + { "LC_GEN3_EN_STRAP", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDN_PCIE_RESERVED[] = { + { "PCIE_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDN_PCIE_SCRATCH[] = { + { "PCIE_SCRATCH", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDN_PCIE_CNTL[] = { + { "HWINIT_WR_LOCK", 0, 0, &umr_bitfield_default }, + { "UR_ERR_REPORT_DIS_DN", 7, 7, &umr_bitfield_default }, + { "RX_IGNORE_LTR_MSG_UR", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDN_PCIE_CONFIG_CNTL[] = { + { "CI_EXTENDED_TAG_EN_OVERRIDE", 25, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDN_PCIE_RX_CNTL2[] = { + { "FLR_EXTEND_MODE", 28, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDN_PCIE_BUS_CNTL[] = { + { "IMMEDIATE_PMI_DIS", 7, 7, &umr_bitfield_default }, + { "AER_CPL_TIMEOUT_RO_DIS_SWDN", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDN_PCIE_CFG_CNTL[] = { + { "CFG_EN_DEC_TO_HIDDEN_REG", 0, 0, &umr_bitfield_default }, + { "CFG_EN_DEC_TO_GEN2_HIDDEN_REG", 1, 1, &umr_bitfield_default }, + { "CFG_EN_DEC_TO_GEN3_HIDDEN_REG", 2, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPCIE_ERR_CNTL[] = { + { "ERR_REPORTING_DIS", 0, 0, &umr_bitfield_default }, + { "AER_HDR_LOG_TIMEOUT", 8, 10, &umr_bitfield_default }, + { "AER_HDR_LOG_F0_TIMER_EXPIRED", 11, 11, &umr_bitfield_default }, + { "SEND_ERR_MSG_IMMEDIATELY", 17, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPCIE_RX_CNTL[] = { + { "RX_IGNORE_MAX_PAYLOAD_ERR", 8, 8, &umr_bitfield_default }, + { "RX_IGNORE_TC_ERR_DN", 9, 9, &umr_bitfield_default }, + { "RX_PCIE_CPL_TIMEOUT_DIS", 20, 20, &umr_bitfield_default }, + { "RX_IGNORE_SHORTPREFIX_ERR_DN", 21, 21, &umr_bitfield_default }, + { "RX_RCB_FLR_TIMEOUT_DIS", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPCIE_LC_SPEED_CNTL[] = { + { "LC_GEN2_EN_STRAP", 0, 0, &umr_bitfield_default }, + { "LC_GEN3_EN_STRAP", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPCIE_LC_CNTL2[] = { + { "LC_LINK_BW_NOTIFICATION_DIS", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmPCIEP_STRAP_MISC[] = { + { "STRAP_MULTI_FUNC_EN", 10, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmLTR_MSG_INFO_FROM_EP[] = { + { "LTR_MSG_INFO_FROM_EP", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRCC_ERR_LOG[] = { + { "INVALID_REG_ACCESS_IN_SRIOV_STATUS", 0, 0, &umr_bitfield_default }, + { "DOORBELL_READ_ACCESS_STATUS", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRCC_DOORBELL_APER_EN[] = { + { "BIF_DOORBELL_APER_EN", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRCC_CONFIG_MEMSIZE[] = { + { "CONFIG_MEMSIZE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRCC_CONFIG_RESERVED[] = { + { "CONFIG_RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRCC_IOV_FUNC_IDENTIFIER[] = { + { "FUNC_IDENTIFIER", 0, 0, &umr_bitfield_default }, + { "IOV_ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRCC_ERR_INT_CNTL[] = { + { "INVALID_REG_ACCESS_IN_SRIOV_INT_EN", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRCC_BACO_CNTL_MISC[] = { + { "BIF_ROM_REQ_DIS", 0, 0, &umr_bitfield_default }, + { "BIF_AZ_REQ_DIS", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRCC_RESET_EN[] = { + { "DB_APER_RESET_EN", 15, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRCC_VDM_SUPPORT[] = { + { "MCTP_SUPPORT", 0, 0, &umr_bitfield_default }, + { "AMPTP_SUPPORT", 1, 1, &umr_bitfield_default }, + { "OTHER_VDM_SUPPORT", 2, 2, &umr_bitfield_default }, + { "ROUTE_TO_RC_CHECK_IN_RCMODE", 3, 3, &umr_bitfield_default }, + { "ROUTE_BROADCAST_CHECK_IN_RCMODE", 4, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRCC_PEER_REG_RANGE0[] = { + { "START_ADDR", 0, 15, &umr_bitfield_default }, + { "END_ADDR", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRCC_PEER_REG_RANGE1[] = { + { "START_ADDR", 0, 15, &umr_bitfield_default }, + { "END_ADDR", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRCC_BUS_CNTL[] = { + { "PMI_IO_DIS", 2, 2, &umr_bitfield_default }, + { "PMI_MEM_DIS", 3, 3, &umr_bitfield_default }, + { "PMI_BM_DIS", 4, 4, &umr_bitfield_default }, + { "PMI_IO_DIS_DN", 5, 5, &umr_bitfield_default }, + { "PMI_MEM_DIS_DN", 6, 6, &umr_bitfield_default }, + { "PMI_IO_DIS_UP", 7, 7, &umr_bitfield_default }, + { "PMI_MEM_DIS_UP", 8, 8, &umr_bitfield_default }, + { "ROOT_ERR_LOG_ON_EVENT", 12, 12, &umr_bitfield_default }, + { "HOST_CPL_POISONED_LOG_IN_RC", 13, 13, &umr_bitfield_default }, + { "DN_SEC_SIG_CPLCA_WITH_EP_ERR", 16, 16, &umr_bitfield_default }, + { "DN_SEC_RCV_CPLCA_WITH_EP_ERR", 17, 17, &umr_bitfield_default }, + { "DN_SEC_RCV_CPLUR_WITH_EP_ERR", 18, 18, &umr_bitfield_default }, + { "DN_PRI_SIG_CPLCA_WITH_EP_ERR", 19, 19, &umr_bitfield_default }, + { "DN_PRI_RCV_CPLCA_WITH_EP_ERR", 20, 20, &umr_bitfield_default }, + { "DN_PRI_RCV_CPLUR_WITH_EP_ERR", 21, 21, &umr_bitfield_default }, + { "MAX_PAYLOAD_SIZE_MODE", 24, 24, &umr_bitfield_default }, + { "PRIV_MAX_PAYLOAD_SIZE", 25, 27, &umr_bitfield_default }, + { "MAX_READ_REQUEST_SIZE_MODE", 28, 28, &umr_bitfield_default }, + { "PRIV_MAX_READ_REQUEST_SIZE", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRCC_CONFIG_CNTL[] = { + { "CFG_VGA_RAM_EN", 0, 0, &umr_bitfield_default }, + { "GENMO_MONO_ADDRESS_B", 2, 2, &umr_bitfield_default }, + { "GRPH_ADRSEL", 3, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRCC_CONFIG_F0_BASE[] = { + { "F0_BASE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRCC_CONFIG_APER_SIZE[] = { + { "APER_SIZE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRCC_CONFIG_REG_APER_SIZE[] = { + { "REG_APER_SIZE", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRCC_XDMA_LO[] = { + { "BIF_XDMA_LOWER_BOUND", 0, 30, &umr_bitfield_default }, + { "BIF_XDMA_APER_EN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRCC_XDMA_HI[] = { + { "BIF_XDMA_UPPER_BOUND", 0, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRCC_FEATURES_CONTROL_MISC[] = { + { "UR_PSN_PKT_REPORT_POISON_DIS", 4, 4, &umr_bitfield_default }, + { "POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS", 5, 5, &umr_bitfield_default }, + { "POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS", 6, 6, &umr_bitfield_default }, + { "INIT_PFFLR_CRS_RET_DIS", 7, 7, &umr_bitfield_default }, + { "ATC_PRG_RESP_PASID_UR_EN", 8, 8, &umr_bitfield_default }, + { "RX_IGNORE_TRANSMRD_UR", 9, 9, &umr_bitfield_default }, + { "RX_IGNORE_TRANSMWR_UR", 10, 10, &umr_bitfield_default }, + { "RX_IGNORE_ATSTRANSREQ_UR", 11, 11, &umr_bitfield_default }, + { "RX_IGNORE_PAGEREQMSG_UR", 12, 12, &umr_bitfield_default }, + { "RX_IGNORE_INVCPL_UR", 13, 13, &umr_bitfield_default }, + { "CLR_MSI_X_PENDING_WHEN_DISABLED_DIS", 14, 14, &umr_bitfield_default }, + { "CHECK_BME_ON_PENDING_PKT_GEN_DIS", 15, 15, &umr_bitfield_default }, + { "PSN_CHECK_ON_PAYLOAD_DIS", 16, 16, &umr_bitfield_default }, + { "CLR_MSI_PENDING_ON_MULTIEN_DIS", 17, 17, &umr_bitfield_default }, + { "SET_DEVICE_ERR_FOR_ECRC_EN", 18, 18, &umr_bitfield_default }, + { "HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS", 19, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRCC_BUSNUM_CNTL1[] = { + { "ID_MASK", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRCC_BUSNUM_LIST0[] = { + { "ID0", 0, 7, &umr_bitfield_default }, + { "ID1", 8, 15, &umr_bitfield_default }, + { "ID2", 16, 23, &umr_bitfield_default }, + { "ID3", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRCC_BUSNUM_LIST1[] = { + { "ID4", 0, 7, &umr_bitfield_default }, + { "ID5", 8, 15, &umr_bitfield_default }, + { "ID6", 16, 23, &umr_bitfield_default }, + { "ID7", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRCC_BUSNUM_CNTL2[] = { + { "AUTOUPDATE_SEL", 0, 7, &umr_bitfield_default }, + { "AUTOUPDATE_EN", 8, 8, &umr_bitfield_default }, + { "HDPREG_CNTL", 16, 16, &umr_bitfield_default }, + { "ERROR_MULTIPLE_ID_MATCH", 17, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRCC_CAPTURE_HOST_BUSNUM[] = { + { "CHECK_EN", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRCC_HOST_BUSNUM[] = { + { "HOST_ID", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRCC_PEER0_FB_OFFSET_HI[] = { + { "PEER0_FB_OFFSET_HI", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRCC_PEER0_FB_OFFSET_LO[] = { + { "PEER0_FB_OFFSET_LO", 0, 19, &umr_bitfield_default }, + { "PEER0_FB_EN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRCC_PEER1_FB_OFFSET_HI[] = { + { "PEER1_FB_OFFSET_HI", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRCC_PEER1_FB_OFFSET_LO[] = { + { "PEER1_FB_OFFSET_LO", 0, 19, &umr_bitfield_default }, + { "PEER1_FB_EN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRCC_PEER2_FB_OFFSET_HI[] = { + { "PEER2_FB_OFFSET_HI", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRCC_PEER2_FB_OFFSET_LO[] = { + { "PEER2_FB_OFFSET_LO", 0, 19, &umr_bitfield_default }, + { "PEER2_FB_EN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRCC_PEER3_FB_OFFSET_HI[] = { + { "PEER3_FB_OFFSET_HI", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRCC_PEER3_FB_OFFSET_LO[] = { + { "PEER3_FB_OFFSET_LO", 0, 19, &umr_bitfield_default }, + { "PEER3_FB_EN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRCC_CMN_LINK_CNTL[] = { + { "BLOCK_PME_ON_L0S_DIS", 0, 0, &umr_bitfield_default }, + { "BLOCK_PME_ON_L1_DIS", 1, 1, &umr_bitfield_default }, + { "BLOCK_PME_ON_LDN_DIS", 2, 2, &umr_bitfield_default }, + { "PM_L1_IDLE_CHECK_DMA_EN", 3, 3, &umr_bitfield_default }, + { "VLINK_IN_L1LTR_TIMER", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRCC_EP_REQUESTERID_RESTORE[] = { + { "EP_REQID_BUS", 0, 7, &umr_bitfield_default }, + { "EP_REQID_DEV", 8, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRCC_LTR_LSWITCH_CNTL[] = { + { "LSWITCH_LATENCY_VALUE", 0, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmRCC_MH_ARB_CNTL[] = { + { "MH_ARB_MODE", 0, 0, &umr_bitfield_default }, + { "MH_ARB_FIX_PRIORITY", 1, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIF_MM_INDACCESS_CNTL[] = { + { "MM_INDACCESS_DIS", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBUS_CNTL[] = { + { "PMI_INT_DIS_EP", 3, 3, &umr_bitfield_default }, + { "PMI_INT_DIS_DN", 4, 4, &umr_bitfield_default }, + { "PMI_INT_DIS_SWUS", 5, 5, &umr_bitfield_default }, + { "VGA_REG_COHERENCY_DIS", 6, 6, &umr_bitfield_default }, + { "VGA_MEM_COHERENCY_DIS", 7, 7, &umr_bitfield_default }, + { "SET_AZ_TC", 10, 12, &umr_bitfield_default }, + { "SET_MC_TC", 13, 15, &umr_bitfield_default }, + { "ZERO_BE_WR_EN", 16, 16, &umr_bitfield_default }, + { "ZERO_BE_RD_EN", 17, 17, &umr_bitfield_default }, + { "RD_STALL_IO_WR", 18, 18, &umr_bitfield_default }, + { "DEASRT_INTX_DSTATE_CHK_DIS_EP", 19, 19, &umr_bitfield_default }, + { "DEASRT_INTX_DSTATE_CHK_DIS_DN", 20, 20, &umr_bitfield_default }, + { "DEASRT_INTX_DSTATE_CHK_DIS_SWUS", 21, 21, &umr_bitfield_default }, + { "DEASRT_INTX_IN_NOND0_EN_EP", 22, 22, &umr_bitfield_default }, + { "DEASRT_INTX_IN_NOND0_EN_DN", 23, 23, &umr_bitfield_default }, + { "UR_OVRD_FOR_ECRC_EN", 24, 24, &umr_bitfield_default }, + { "PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS", 25, 25, &umr_bitfield_default }, + { "PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS", 26, 26, &umr_bitfield_default }, + { "GSI_RD_SPLIT_STALL_FLUSH_EN", 27, 27, &umr_bitfield_default }, + { "GSI_RD_SPLIT_STALL_NPWR_DIS", 28, 28, &umr_bitfield_default }, + { "HDP_REG_FLUSH_VF_MASK_EN", 29, 29, &umr_bitfield_default }, + { "VGAFB_ZERO_BE_WR_EN", 30, 30, &umr_bitfield_default }, + { "VGAFB_ZERO_BE_RD_EN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIF_SCRATCH0[] = { + { "BIF_SCRATCH0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIF_SCRATCH1[] = { + { "BIF_SCRATCH1", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBX_RESET_EN[] = { + { "COR_RESET_EN", 0, 0, &umr_bitfield_default }, + { "REG_RESET_EN", 1, 1, &umr_bitfield_default }, + { "STY_RESET_EN", 2, 2, &umr_bitfield_default }, + { "FLR_TWICE_EN", 8, 8, &umr_bitfield_default }, + { "RESET_ON_VFENABLE_LOW_EN", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMM_CFGREGS_CNTL[] = { + { "MM_CFG_FUNC_SEL", 0, 2, &umr_bitfield_default }, + { "MM_CFG_DEV_SEL", 6, 7, &umr_bitfield_default }, + { "MM_WR_TO_CFG_EN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBX_RESET_CNTL[] = { + { "LINK_TRAIN_EN", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmINTERRUPT_CNTL[] = { + { "IH_DUMMY_RD_OVERRIDE", 0, 0, &umr_bitfield_default }, + { "IH_DUMMY_RD_EN", 1, 1, &umr_bitfield_default }, + { "IH_REQ_NONSNOOP_EN", 3, 3, &umr_bitfield_default }, + { "IH_INTR_DLY_CNTR", 4, 7, &umr_bitfield_default }, + { "GEN_IH_INT_EN", 8, 8, &umr_bitfield_default }, + { "BIF_RB_REQ_NONSNOOP_EN", 15, 15, &umr_bitfield_default }, + { "DUMMYRD_BYPASS_IN_MSI_EN", 16, 16, &umr_bitfield_default }, + { "ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS", 17, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmINTERRUPT_CNTL2[] = { + { "IH_DUMMY_RD_ADDR", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCLKREQB_PAD_CNTL[] = { + { "CLKREQB_PAD_A", 0, 0, &umr_bitfield_default }, + { "CLKREQB_PAD_SEL", 1, 1, &umr_bitfield_default }, + { "CLKREQB_PAD_MODE", 2, 2, &umr_bitfield_default }, + { "CLKREQB_PAD_SPARE", 3, 4, &umr_bitfield_default }, + { "CLKREQB_PAD_SN0", 5, 5, &umr_bitfield_default }, + { "CLKREQB_PAD_SN1", 6, 6, &umr_bitfield_default }, + { "CLKREQB_PAD_SN2", 7, 7, &umr_bitfield_default }, + { "CLKREQB_PAD_SN3", 8, 8, &umr_bitfield_default }, + { "CLKREQB_PAD_SLEWN", 9, 9, &umr_bitfield_default }, + { "CLKREQB_PAD_WAKE", 10, 10, &umr_bitfield_default }, + { "CLKREQB_PAD_SCHMEN", 11, 11, &umr_bitfield_default }, + { "CLKREQB_PAD_CNTL_EN", 12, 12, &umr_bitfield_default }, + { "CLKREQB_PAD_Y", 13, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIF_FEATURES_CONTROL_MISC[] = { + { "MST_BIF_REQ_EP_DIS", 0, 0, &umr_bitfield_default }, + { "SLV_BIF_CPL_EP_DIS", 1, 1, &umr_bitfield_default }, + { "BIF_SLV_REQ_EP_DIS", 2, 2, &umr_bitfield_default }, + { "BIF_MST_CPL_EP_DIS", 3, 3, &umr_bitfield_default }, + { "BIF_RB_SET_OVERFLOW_EN", 12, 12, &umr_bitfield_default }, + { "ATOMIC_ERR_INT_DIS", 13, 13, &umr_bitfield_default }, + { "BME_HDL_NONVIR_EN", 15, 15, &umr_bitfield_default }, + { "FLR_MST_PEND_CHK_DIS", 17, 17, &umr_bitfield_default }, + { "FLR_SLV_PEND_CHK_DIS", 18, 18, &umr_bitfield_default }, + { "DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIF_DOORBELL_CNTL[] = { + { "SELF_RING_DIS", 0, 0, &umr_bitfield_default }, + { "TRANS_CHECK_DIS", 1, 1, &umr_bitfield_default }, + { "UNTRANS_LBACK_EN", 2, 2, &umr_bitfield_default }, + { "NON_CONSECUTIVE_BE_ZERO_DIS", 3, 3, &umr_bitfield_default }, + { "DOORBELL_MONITOR_EN", 4, 4, &umr_bitfield_default }, + { "DB_MNTR_INTGEN_DIS", 24, 24, &umr_bitfield_default }, + { "DB_MNTR_INTGEN_MODE_0", 25, 25, &umr_bitfield_default }, + { "DB_MNTR_INTGEN_MODE_1", 26, 26, &umr_bitfield_default }, + { "DB_MNTR_INTGEN_MODE_2", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIF_DOORBELL_INT_CNTL[] = { + { "DOORBELL_INTERRUPT_STATUS", 0, 0, &umr_bitfield_default }, + { "IOHC_RAS_INTERRUPT_STATUS", 1, 1, &umr_bitfield_default }, + { "DOORBELL_INTERRUPT_CLEAR", 16, 16, &umr_bitfield_default }, + { "IOHC_RAS_INTERRUPT_CLEAR", 17, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIF_FB_EN[] = { + { "FB_READ_EN", 0, 0, &umr_bitfield_default }, + { "FB_WRITE_EN", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIF_BUSY_DELAY_CNTR[] = { + { "DELAY_CNT", 0, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIF_MST_TRANS_PENDING_VF[] = { + { "BIF_MST_TRANS_PENDING", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIF_SLV_TRANS_PENDING_VF[] = { + { "BIF_SLV_TRANS_PENDING", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBACO_CNTL[] = { + { "BACO_EN", 0, 0, &umr_bitfield_default }, + { "BACO_BIF_LCLK_SWITCH", 1, 1, &umr_bitfield_default }, + { "BACO_DUMMY_EN", 2, 2, &umr_bitfield_default }, + { "BACO_POWER_OFF", 3, 3, &umr_bitfield_default }, + { "BACO_DSTATE_BYPASS", 5, 5, &umr_bitfield_default }, + { "BACO_RST_INTR_MASK", 6, 6, &umr_bitfield_default }, + { "BACO_MODE", 8, 8, &umr_bitfield_default }, + { "RCU_BIF_CONFIG_DONE", 9, 9, &umr_bitfield_default }, + { "BACO_AUTO_EXIT", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIF_BACO_EXIT_TIME0[] = { + { "BACO_EXIT_PXEN_CLR_TIMER", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIF_BACO_EXIT_TIMER1[] = { + { "BACO_EXIT_SIDEBAND_TIMER", 0, 19, &umr_bitfield_default }, + { "BACO_HW_AUTO_FLUSH_EN", 24, 24, &umr_bitfield_default }, + { "BACO_HW_EXIT_ENDING_AUTO_BY_RSMU_INTR_CLR", 25, 25, &umr_bitfield_default }, + { "BACO_HW_EXIT_DIS", 26, 26, &umr_bitfield_default }, + { "PX_EN_OE_IN_PX_EN_HIGH", 27, 27, &umr_bitfield_default }, + { "PX_EN_OE_IN_PX_EN_LOW", 28, 28, &umr_bitfield_default }, + { "BACO_MODE_SEL", 29, 30, &umr_bitfield_default }, + { "AUTO_BACO_EXIT_CLR_BY_HW_DIS", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIF_BACO_EXIT_TIMER2[] = { + { "BACO_EXIT_LCLK_BAK_TIMER", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIF_BACO_EXIT_TIMER3[] = { + { "BACO_EXIT_DUMMY_EN_CLR_TIMER", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIF_BACO_EXIT_TIMER4[] = { + { "BACO_EXIT_BACO_EN_CLR_TIMER", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMEM_TYPE_CNTL[] = { + { "BF_MEM_PHY_G5_G3", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSMU_BIF_VDDGFX_PWR_STATUS[] = { + { "VDDGFX_GFX_PWR_OFF", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIF_VDDGFX_GFX0_LOWER[] = { + { "VDDGFX_GFX0_REG_LOWER", 2, 17, &umr_bitfield_default }, + { "VDDGFX_GFX0_REG_CMP_EN", 30, 30, &umr_bitfield_default }, + { "VDDGFX_GFX0_REG_STALL_EN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIF_VDDGFX_GFX0_UPPER[] = { + { "VDDGFX_GFX0_REG_UPPER", 2, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIF_VDDGFX_GFX1_LOWER[] = { + { "VDDGFX_GFX1_REG_LOWER", 2, 17, &umr_bitfield_default }, + { "VDDGFX_GFX1_REG_CMP_EN", 30, 30, &umr_bitfield_default }, + { "VDDGFX_GFX1_REG_STALL_EN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIF_VDDGFX_GFX1_UPPER[] = { + { "VDDGFX_GFX1_REG_UPPER", 2, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIF_VDDGFX_GFX2_LOWER[] = { + { "VDDGFX_GFX2_REG_LOWER", 2, 17, &umr_bitfield_default }, + { "VDDGFX_GFX2_REG_CMP_EN", 30, 30, &umr_bitfield_default }, + { "VDDGFX_GFX2_REG_STALL_EN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIF_VDDGFX_GFX2_UPPER[] = { + { "VDDGFX_GFX2_REG_UPPER", 2, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIF_VDDGFX_GFX3_LOWER[] = { + { "VDDGFX_GFX3_REG_LOWER", 2, 17, &umr_bitfield_default }, + { "VDDGFX_GFX3_REG_CMP_EN", 30, 30, &umr_bitfield_default }, + { "VDDGFX_GFX3_REG_STALL_EN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIF_VDDGFX_GFX3_UPPER[] = { + { "VDDGFX_GFX3_REG_UPPER", 2, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIF_VDDGFX_GFX4_LOWER[] = { + { "VDDGFX_GFX4_REG_LOWER", 2, 17, &umr_bitfield_default }, + { "VDDGFX_GFX4_REG_CMP_EN", 30, 30, &umr_bitfield_default }, + { "VDDGFX_GFX4_REG_STALL_EN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIF_VDDGFX_GFX4_UPPER[] = { + { "VDDGFX_GFX4_REG_UPPER", 2, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIF_VDDGFX_GFX5_LOWER[] = { + { "VDDGFX_GFX5_REG_LOWER", 2, 17, &umr_bitfield_default }, + { "VDDGFX_GFX5_REG_CMP_EN", 30, 30, &umr_bitfield_default }, + { "VDDGFX_GFX5_REG_STALL_EN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIF_VDDGFX_GFX5_UPPER[] = { + { "VDDGFX_GFX5_REG_UPPER", 2, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIF_VDDGFX_RSV1_LOWER[] = { + { "VDDGFX_RSV1_REG_LOWER", 2, 17, &umr_bitfield_default }, + { "VDDGFX_RSV1_REG_CMP_EN", 30, 30, &umr_bitfield_default }, + { "VDDGFX_RSV1_REG_STALL_EN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIF_VDDGFX_RSV1_UPPER[] = { + { "VDDGFX_RSV1_REG_UPPER", 2, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIF_VDDGFX_RSV2_LOWER[] = { + { "VDDGFX_RSV2_REG_LOWER", 2, 17, &umr_bitfield_default }, + { "VDDGFX_RSV2_REG_CMP_EN", 30, 30, &umr_bitfield_default }, + { "VDDGFX_RSV2_REG_STALL_EN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIF_VDDGFX_RSV2_UPPER[] = { + { "VDDGFX_RSV2_REG_UPPER", 2, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIF_VDDGFX_RSV3_LOWER[] = { + { "VDDGFX_RSV3_REG_LOWER", 2, 17, &umr_bitfield_default }, + { "VDDGFX_RSV3_REG_CMP_EN", 30, 30, &umr_bitfield_default }, + { "VDDGFX_RSV3_REG_STALL_EN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIF_VDDGFX_RSV3_UPPER[] = { + { "VDDGFX_RSV3_REG_UPPER", 2, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIF_VDDGFX_RSV4_LOWER[] = { + { "VDDGFX_RSV4_REG_LOWER", 2, 17, &umr_bitfield_default }, + { "VDDGFX_RSV4_REG_CMP_EN", 30, 30, &umr_bitfield_default }, + { "VDDGFX_RSV4_REG_STALL_EN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIF_VDDGFX_RSV4_UPPER[] = { + { "VDDGFX_RSV4_REG_UPPER", 2, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIF_VDDGFX_FB_CMP[] = { + { "VDDGFX_FB_HDP_CMP_EN", 0, 0, &umr_bitfield_default }, + { "VDDGFX_FB_HDP_STALL_EN", 1, 1, &umr_bitfield_default }, + { "VDDGFX_FB_XDMA_CMP_EN", 2, 2, &umr_bitfield_default }, + { "VDDGFX_FB_XDMA_STALL_EN", 3, 3, &umr_bitfield_default }, + { "VDDGFX_FB_VGA_CMP_EN", 4, 4, &umr_bitfield_default }, + { "VDDGFX_FB_VGA_STALL_EN", 5, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIF_DOORBELL_GBLAPER1_LOWER[] = { + { "DOORBELL_GBLAPER1_LOWER", 2, 11, &umr_bitfield_default }, + { "DOORBELL_GBLAPER1_EN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIF_DOORBELL_GBLAPER1_UPPER[] = { + { "DOORBELL_GBLAPER1_UPPER", 2, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIF_DOORBELL_GBLAPER2_LOWER[] = { + { "DOORBELL_GBLAPER2_LOWER", 2, 11, &umr_bitfield_default }, + { "DOORBELL_GBLAPER2_EN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIF_DOORBELL_GBLAPER2_UPPER[] = { + { "DOORBELL_GBLAPER2_UPPER", 2, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmREMAP_HDP_MEM_FLUSH_CNTL[] = { + { "ADDRESS", 2, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmREMAP_HDP_REG_FLUSH_CNTL[] = { + { "ADDRESS", 2, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIF_RB_CNTL[] = { + { "RB_ENABLE", 0, 0, &umr_bitfield_default }, + { "RB_SIZE", 1, 5, &umr_bitfield_default }, + { "WPTR_WRITEBACK_ENABLE", 8, 8, &umr_bitfield_default }, + { "WPTR_WRITEBACK_TIMER", 9, 13, &umr_bitfield_default }, + { "BIF_RB_TRAN", 17, 17, &umr_bitfield_default }, + { "WPTR_OVERFLOW_CLEAR", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIF_RB_BASE[] = { + { "ADDR", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIF_RB_RPTR[] = { + { "OFFSET", 2, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIF_RB_WPTR[] = { + { "BIF_RB_OVERFLOW", 0, 0, &umr_bitfield_default }, + { "OFFSET", 2, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIF_RB_WPTR_ADDR_HI[] = { + { "ADDR", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIF_RB_WPTR_ADDR_LO[] = { + { "ADDR", 2, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMAILBOX_INDEX[] = { + { "MAILBOX_INDEX", 0, 4, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIF_UVD_GPUIOV_CFG_SIZE[] = { + { "UVD_GPUIOV_CFG_SIZE", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIF_VCE_GPUIOV_CFG_SIZE[] = { + { "VCE_GPUIOV_CFG_SIZE", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIF_GFX_SDMA_GPUIOV_CFG_SIZE[] = { + { "GFX_SDMA_GPUIOV_CFG_SIZE", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIF_PERSTB_PAD_CNTL[] = { + { "PERSTB_PAD_CNTL", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIF_PX_EN_PAD_CNTL[] = { + { "PX_EN_PAD_CNTL", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIF_REFPADKIN_PAD_CNTL[] = { + { "REFPADKIN_PAD_CNTL", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIF_CLKREQB_PAD_CNTL[] = { + { "CLKREQB_PAD_CNTL", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIF_BME_STATUS[] = { + { "DMA_ON_BME_LOW", 0, 0, &umr_bitfield_default }, + { "CLEAR_DMA_ON_BME_LOW", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIF_ATOMIC_ERR_LOG[] = { + { "UR_ATOMIC_OPCODE", 0, 0, &umr_bitfield_default }, + { "UR_ATOMIC_REQEN_LOW", 1, 1, &umr_bitfield_default }, + { "UR_ATOMIC_LENGTH", 2, 2, &umr_bitfield_default }, + { "UR_ATOMIC_NR", 3, 3, &umr_bitfield_default }, + { "CLEAR_UR_ATOMIC_OPCODE", 16, 16, &umr_bitfield_default }, + { "CLEAR_UR_ATOMIC_REQEN_LOW", 17, 17, &umr_bitfield_default }, + { "CLEAR_UR_ATOMIC_LENGTH", 18, 18, &umr_bitfield_default }, + { "CLEAR_UR_ATOMIC_NR", 19, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH[] = { + { "DOORBELL_SELFRING_GPA_APER_BASE_HIGH", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDOORBELL_SELFRING_GPA_APER_BASE_LOW[] = { + { "DOORBELL_SELFRING_GPA_APER_BASE_LOW", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmDOORBELL_SELFRING_GPA_APER_CNTL[] = { + { "DOORBELL_SELFRING_GPA_APER_EN", 0, 0, &umr_bitfield_default }, + { "DOORBELL_SELFRING_GPA_APER_MODE", 1, 1, &umr_bitfield_default }, + { "DOORBELL_SELFRING_GPA_APER_SIZE", 8, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHDP_REG_COHERENCY_FLUSH_CNTL[] = { + { "HDP_REG_FLUSH_ADDR", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmHDP_MEM_COHERENCY_FLUSH_CNTL[] = { + { "HDP_MEM_FLUSH_ADDR", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGPU_HDP_FLUSH_REQ[] = { + { "CP0", 0, 0, &umr_bitfield_default }, + { "CP1", 1, 1, &umr_bitfield_default }, + { "CP2", 2, 2, &umr_bitfield_default }, + { "CP3", 3, 3, &umr_bitfield_default }, + { "CP4", 4, 4, &umr_bitfield_default }, + { "CP5", 5, 5, &umr_bitfield_default }, + { "CP6", 6, 6, &umr_bitfield_default }, + { "CP7", 7, 7, &umr_bitfield_default }, + { "CP8", 8, 8, &umr_bitfield_default }, + { "CP9", 9, 9, &umr_bitfield_default }, + { "SDMA0", 10, 10, &umr_bitfield_default }, + { "SDMA1", 11, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGPU_HDP_FLUSH_DONE[] = { + { "CP0", 0, 0, &umr_bitfield_default }, + { "CP1", 1, 1, &umr_bitfield_default }, + { "CP2", 2, 2, &umr_bitfield_default }, + { "CP3", 3, 3, &umr_bitfield_default }, + { "CP4", 4, 4, &umr_bitfield_default }, + { "CP5", 5, 5, &umr_bitfield_default }, + { "CP6", 6, 6, &umr_bitfield_default }, + { "CP7", 7, 7, &umr_bitfield_default }, + { "CP8", 8, 8, &umr_bitfield_default }, + { "CP9", 9, 9, &umr_bitfield_default }, + { "SDMA0", 10, 10, &umr_bitfield_default }, + { "SDMA1", 11, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIF_TRANS_PENDING[] = { + { "BIF_MST_TRANS_PENDING", 0, 0, &umr_bitfield_default }, + { "BIF_SLV_TRANS_PENDING", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMAILBOX_MSGBUF_TRN_DW0[] = { + { "MSGBUF_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMAILBOX_MSGBUF_TRN_DW1[] = { + { "MSGBUF_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMAILBOX_MSGBUF_TRN_DW2[] = { + { "MSGBUF_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMAILBOX_MSGBUF_TRN_DW3[] = { + { "MSGBUF_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMAILBOX_MSGBUF_RCV_DW0[] = { + { "MSGBUF_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMAILBOX_MSGBUF_RCV_DW1[] = { + { "MSGBUF_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMAILBOX_MSGBUF_RCV_DW2[] = { + { "MSGBUF_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMAILBOX_MSGBUF_RCV_DW3[] = { + { "MSGBUF_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMAILBOX_CONTROL[] = { + { "TRN_MSG_VALID", 0, 0, &umr_bitfield_default }, + { "TRN_MSG_ACK", 1, 1, &umr_bitfield_default }, + { "RCV_MSG_VALID", 8, 8, &umr_bitfield_default }, + { "RCV_MSG_ACK", 9, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmMAILBOX_INT_CNTL[] = { + { "VALID_INT_EN", 0, 0, &umr_bitfield_default }, + { "ACK_INT_EN", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIF_VMHV_MAILBOX[] = { + { "VMHV_MAILBOX_TRN_ACK_INTR_EN", 0, 0, &umr_bitfield_default }, + { "VMHV_MAILBOX_RCV_VALID_INTR_EN", 1, 1, &umr_bitfield_default }, + { "VMHV_MAILBOX_TRN_MSG_DATA", 8, 11, &umr_bitfield_default }, + { "VMHV_MAILBOX_TRN_MSG_VALID", 15, 15, &umr_bitfield_default }, + { "VMHV_MAILBOX_RCV_MSG_DATA", 16, 19, &umr_bitfield_default }, + { "VMHV_MAILBOX_RCV_MSG_VALID", 23, 23, &umr_bitfield_default }, + { "VMHV_MAILBOX_TRN_MSG_ACK", 24, 24, &umr_bitfield_default }, + { "VMHV_MAILBOX_RCV_MSG_ACK", 25, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmNGDC_SDP_PORT_CTRL[] = { + { "SDP_DISCON_HYSTERESIS", 0, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSHUB_REGS_IF_CTL[] = { + { "SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmNGDC_RESERVED_0[] = { + { "RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmNGDC_RESERVED_1[] = { + { "RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmNGDC_SDP_PORT_CTRL_SOCCLK[] = { + { "SDP_DISCON_HYSTERESIS_SOCCLK", 0, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIF_SDMA0_DOORBELL_RANGE[] = { + { "OFFSET", 2, 11, &umr_bitfield_default }, + { "SIZE", 16, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIF_SDMA1_DOORBELL_RANGE[] = { + { "OFFSET", 2, 11, &umr_bitfield_default }, + { "SIZE", 16, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIF_IH_DOORBELL_RANGE[] = { + { "OFFSET", 2, 11, &umr_bitfield_default }, + { "SIZE", 16, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIF_MMSCH0_DOORBELL_RANGE[] = { + { "OFFSET", 2, 11, &umr_bitfield_default }, + { "SIZE", 16, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmATDMA_MISC_CNTL[] = { + { "WRR_ARB_MODE", 0, 0, &umr_bitfield_default }, + { "INSERT_RD_ON_2ND_WDAT_EN", 1, 1, &umr_bitfield_default }, + { "WRR_VC0_WEIGHT", 16, 23, &umr_bitfield_default }, + { "WRR_VC1_WEIGHT", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmBIF_DOORBELL_FENCE_CNTL[] = { + { "DOORBELL_FENCE_ENABLE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmS2A_MISC_CNTL[] = { + { "DOORBELL_64BIT_SUPPORT_SDMA0_DIS", 0, 0, &umr_bitfield_default }, + { "DOORBELL_64BIT_SUPPORT_SDMA1_DIS", 1, 1, &umr_bitfield_default }, + { "DOORBELL_64BIT_SUPPORT_CP_DIS", 2, 2, &umr_bitfield_default }, + { "AXI_HST_CPL_EP_DIS", 3, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGDC_PG_MISC_CNTL[] = { + { "GDC_PG_RESET_SELECT_COLD_RESET", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGFXMSIX_VECT0_ADDR_LO[] = { + { "MSG_ADDR_LO", 2, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGFXMSIX_VECT0_ADDR_HI[] = { + { "MSG_ADDR_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGFXMSIX_VECT0_MSG_DATA[] = { + { "MSG_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGFXMSIX_VECT0_CONTROL[] = { + { "MASK_BIT", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGFXMSIX_VECT1_ADDR_LO[] = { + { "MSG_ADDR_LO", 2, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGFXMSIX_VECT1_ADDR_HI[] = { + { "MSG_ADDR_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGFXMSIX_VECT1_MSG_DATA[] = { + { "MSG_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGFXMSIX_VECT1_CONTROL[] = { + { "MASK_BIT", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGFXMSIX_VECT2_ADDR_LO[] = { + { "MSG_ADDR_LO", 2, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGFXMSIX_VECT2_ADDR_HI[] = { + { "MSG_ADDR_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGFXMSIX_VECT2_MSG_DATA[] = { + { "MSG_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGFXMSIX_VECT2_CONTROL[] = { + { "MASK_BIT", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmGFXMSIX_PBA[] = { + { "MSIX_PENDING_BITS_0", 0, 0, &umr_bitfield_default }, + { "MSIX_PENDING_BITS_1", 1, 1, &umr_bitfield_default }, + { "MSIX_PENDING_BITS_2", 2, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK[] = { + { "HST_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE", 0, 0, &umr_bitfield_default }, + { "HST_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE", 1, 1, &umr_bitfield_default }, + { "HST_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE", 2, 2, &umr_bitfield_default }, + { "HST_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE", 3, 3, &umr_bitfield_default }, + { "HST_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE", 4, 4, &umr_bitfield_default }, + { "HST_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE", 5, 5, &umr_bitfield_default }, + { "HST_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE", 6, 6, &umr_bitfield_default }, + { "HST_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE", 7, 7, &umr_bitfield_default }, + { "DMA_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE", 16, 16, &umr_bitfield_default }, + { "DMA_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE", 17, 17, &umr_bitfield_default }, + { "DMA_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE", 18, 18, &umr_bitfield_default }, + { "DMA_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE", 19, 19, &umr_bitfield_default }, + { "DMA_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE", 20, 20, &umr_bitfield_default }, + { "DMA_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE", 21, 21, &umr_bitfield_default }, + { "DMA_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE", 22, 22, &umr_bitfield_default }, + { "DMA_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE", 23, 23, &umr_bitfield_default }, + { "SYSHUB_SOCCLK_DEEPSLEEP_ALLOW_ENABLE", 28, 28, &umr_bitfield_default }, + { "SYSHUB_SOCCLK_DS_EN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_SYSHUB_DS_CTRL2_SOCCLK[] = { + { "SYSHUB_SOCCLK_DS_TIMER", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK[] = { + { "SYSHUB_bgen_socclk_HST_SW0_bypass_en", 0, 0, &umr_bitfield_default }, + { "SYSHUB_bgen_socclk_HST_SW1_bypass_en", 1, 1, &umr_bitfield_default }, + { "SYSHUB_bgen_socclk_DMA_SW0_bypass_en", 15, 15, &umr_bitfield_default }, + { "SYSHUB_bgen_socclk_DMA_SW1_bypass_en", 16, 16, &umr_bitfield_default }, + { "SYSHUB_bgen_socclk_DMA_SW2_bypass_en", 17, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK[] = { + { "SYSHUB_bgen_socclk_HST_SW0_imm_en", 0, 0, &umr_bitfield_default }, + { "SYSHUB_bgen_socclk_HST_SW1_imm_en", 1, 1, &umr_bitfield_default }, + { "SYSHUB_bgen_socclk_DMA_SW0_imm_en", 15, 15, &umr_bitfield_default }, + { "SYSHUB_bgen_socclk_DMA_SW1_imm_en", 16, 16, &umr_bitfield_default }, + { "SYSHUB_bgen_socclk_DMA_SW2_imm_en", 17, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL[] = { + { "QOS_CNTL_MODE", 0, 0, &umr_bitfield_default }, + { "QOS_MAX_VALUE", 1, 4, &umr_bitfield_default }, + { "QOS_MIN_VALUE", 5, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL[] = { + { "QOS_CNTL_MODE", 0, 0, &umr_bitfield_default }, + { "QOS_MAX_VALUE", 1, 4, &umr_bitfield_default }, + { "QOS_MIN_VALUE", 5, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_DMA_CLK0_SW2_SYSHUB_QOS_CNTL[] = { + { "QOS_CNTL_MODE", 0, 0, &umr_bitfield_default }, + { "QOS_MAX_VALUE", 1, 4, &umr_bitfield_default }, + { "QOS_MIN_VALUE", 5, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL[] = { + { "FLR_ON_RS_RESET_EN", 0, 0, &umr_bitfield_default }, + { "LKRST_ON_RS_RESET_EN", 1, 1, &umr_bitfield_default }, + { "QOS_STATIC_OVERRIDE_EN", 8, 8, &umr_bitfield_default }, + { "QOS_STATIC_OVERRIDE_VALUE", 9, 12, &umr_bitfield_default }, + { "READ_WRR_WEIGHT", 16, 23, &umr_bitfield_default }, + { "WRITE_WRR_WEIGHT", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL[] = { + { "FLR_ON_RS_RESET_EN", 0, 0, &umr_bitfield_default }, + { "LKRST_ON_RS_RESET_EN", 1, 1, &umr_bitfield_default }, + { "QOS_STATIC_OVERRIDE_EN", 8, 8, &umr_bitfield_default }, + { "QOS_STATIC_OVERRIDE_VALUE", 9, 12, &umr_bitfield_default }, + { "READ_WRR_WEIGHT", 16, 23, &umr_bitfield_default }, + { "WRITE_WRR_WEIGHT", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL[] = { + { "FLR_ON_RS_RESET_EN", 0, 0, &umr_bitfield_default }, + { "LKRST_ON_RS_RESET_EN", 1, 1, &umr_bitfield_default }, + { "QOS_STATIC_OVERRIDE_EN", 8, 8, &umr_bitfield_default }, + { "QOS_STATIC_OVERRIDE_VALUE", 9, 12, &umr_bitfield_default }, + { "READ_WRR_WEIGHT", 16, 23, &umr_bitfield_default }, + { "WRITE_WRR_WEIGHT", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL[] = { + { "FLR_ON_RS_RESET_EN", 0, 0, &umr_bitfield_default }, + { "LKRST_ON_RS_RESET_EN", 1, 1, &umr_bitfield_default }, + { "QOS_STATIC_OVERRIDE_EN", 8, 8, &umr_bitfield_default }, + { "QOS_STATIC_OVERRIDE_VALUE", 9, 12, &umr_bitfield_default }, + { "READ_WRR_WEIGHT", 16, 23, &umr_bitfield_default }, + { "WRITE_WRR_WEIGHT", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL[] = { + { "FLR_ON_RS_RESET_EN", 0, 0, &umr_bitfield_default }, + { "LKRST_ON_RS_RESET_EN", 1, 1, &umr_bitfield_default }, + { "QOS_STATIC_OVERRIDE_EN", 8, 8, &umr_bitfield_default }, + { "QOS_STATIC_OVERRIDE_VALUE", 9, 12, &umr_bitfield_default }, + { "READ_WRR_WEIGHT", 16, 23, &umr_bitfield_default }, + { "WRITE_WRR_WEIGHT", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL[] = { + { "FLR_ON_RS_RESET_EN", 0, 0, &umr_bitfield_default }, + { "LKRST_ON_RS_RESET_EN", 1, 1, &umr_bitfield_default }, + { "QOS_STATIC_OVERRIDE_EN", 8, 8, &umr_bitfield_default }, + { "QOS_STATIC_OVERRIDE_VALUE", 9, 12, &umr_bitfield_default }, + { "READ_WRR_WEIGHT", 16, 23, &umr_bitfield_default }, + { "WRITE_WRR_WEIGHT", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL[] = { + { "FLR_ON_RS_RESET_EN", 0, 0, &umr_bitfield_default }, + { "LKRST_ON_RS_RESET_EN", 1, 1, &umr_bitfield_default }, + { "QOS_STATIC_OVERRIDE_EN", 8, 8, &umr_bitfield_default }, + { "QOS_STATIC_OVERRIDE_VALUE", 9, 12, &umr_bitfield_default }, + { "READ_WRR_WEIGHT", 16, 23, &umr_bitfield_default }, + { "WRITE_WRR_WEIGHT", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL[] = { + { "FLR_ON_RS_RESET_EN", 0, 0, &umr_bitfield_default }, + { "LKRST_ON_RS_RESET_EN", 1, 1, &umr_bitfield_default }, + { "QOS_STATIC_OVERRIDE_EN", 8, 8, &umr_bitfield_default }, + { "QOS_STATIC_OVERRIDE_VALUE", 9, 12, &umr_bitfield_default }, + { "READ_WRR_WEIGHT", 16, 23, &umr_bitfield_default }, + { "WRITE_WRR_WEIGHT", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_HST_CLK0_SW0_CL0_CNTL[] = { + { "FLR_ON_RS_RESET_EN", 0, 0, &umr_bitfield_default }, + { "LKRST_ON_RS_RESET_EN", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_HST_CLK0_SW0_CL1_CNTL[] = { + { "FLR_ON_RS_RESET_EN", 0, 0, &umr_bitfield_default }, + { "LKRST_ON_RS_RESET_EN", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_HST_CLK0_SW0_CL2_CNTL[] = { + { "FLR_ON_RS_RESET_EN", 0, 0, &umr_bitfield_default }, + { "LKRST_ON_RS_RESET_EN", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL0_CNTL[] = { + { "FLR_ON_RS_RESET_EN", 0, 0, &umr_bitfield_default }, + { "LKRST_ON_RS_RESET_EN", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL1_CNTL[] = { + { "FLR_ON_RS_RESET_EN", 0, 0, &umr_bitfield_default }, + { "LKRST_ON_RS_RESET_EN", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL2_CNTL[] = { + { "FLR_ON_RS_RESET_EN", 0, 0, &umr_bitfield_default }, + { "LKRST_ON_RS_RESET_EN", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL3_CNTL[] = { + { "FLR_ON_RS_RESET_EN", 0, 0, &umr_bitfield_default }, + { "LKRST_ON_RS_RESET_EN", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL4_CNTL[] = { + { "FLR_ON_RS_RESET_EN", 0, 0, &umr_bitfield_default }, + { "LKRST_ON_RS_RESET_EN", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_SYSHUB_CG_CNTL[] = { + { "SYSHUB_CG_EN", 0, 0, &umr_bitfield_default }, + { "SYSHUB_CG_IDLE_TIMER", 8, 15, &umr_bitfield_default }, + { "SYSHUB_CG_WAKEUP_TIMER", 16, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE[] = { + { "SYSHUB_TRANS_IDLE_VF0", 0, 0, &umr_bitfield_default }, + { "SYSHUB_TRANS_IDLE_VF1", 1, 1, &umr_bitfield_default }, + { "SYSHUB_TRANS_IDLE_VF2", 2, 2, &umr_bitfield_default }, + { "SYSHUB_TRANS_IDLE_VF3", 3, 3, &umr_bitfield_default }, + { "SYSHUB_TRANS_IDLE_VF4", 4, 4, &umr_bitfield_default }, + { "SYSHUB_TRANS_IDLE_VF5", 5, 5, &umr_bitfield_default }, + { "SYSHUB_TRANS_IDLE_VF6", 6, 6, &umr_bitfield_default }, + { "SYSHUB_TRANS_IDLE_VF7", 7, 7, &umr_bitfield_default }, + { "SYSHUB_TRANS_IDLE_VF8", 8, 8, &umr_bitfield_default }, + { "SYSHUB_TRANS_IDLE_VF9", 9, 9, &umr_bitfield_default }, + { "SYSHUB_TRANS_IDLE_VF10", 10, 10, &umr_bitfield_default }, + { "SYSHUB_TRANS_IDLE_VF11", 11, 11, &umr_bitfield_default }, + { "SYSHUB_TRANS_IDLE_VF12", 12, 12, &umr_bitfield_default }, + { "SYSHUB_TRANS_IDLE_VF13", 13, 13, &umr_bitfield_default }, + { "SYSHUB_TRANS_IDLE_VF14", 14, 14, &umr_bitfield_default }, + { "SYSHUB_TRANS_IDLE_VF15", 15, 15, &umr_bitfield_default }, + { "SYSHUB_TRANS_IDLE_PF", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_SYSHUB_HP_TIMER[] = { + { "SYSHUB_HP_TIMER", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK[] = { + { "SYSHUB_MGCG_EN_SOCCLK", 0, 0, &umr_bitfield_default }, + { "SYSHUB_MGCG_MODE_SOCCLK", 1, 1, &umr_bitfield_default }, + { "SYSHUB_MGCG_HYSTERESIS_SOCCLK", 2, 9, &umr_bitfield_default }, + { "SYSHUB_MGCG_HST_DIS_SOCCLK", 10, 10, &umr_bitfield_default }, + { "SYSHUB_MGCG_DMA_DIS_SOCCLK", 11, 11, &umr_bitfield_default }, + { "SYSHUB_MGCG_REGS_DIS_SOCCLK", 12, 12, &umr_bitfield_default }, + { "SYSHUB_MGCG_AER_DIS_SOCCLK", 13, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_SYSUB_CPF_DOORBELL_RS_RESET[] = { + { "SYSHUB_CPF_DOORBELL_RS_RESET", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_SYSHUB_SCRATCH[] = { + { "SCRATCH", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_SYSHUB_CL_MASK[] = { + { "MP1DRAM_MASK_DIS", 1, 1, &umr_bitfield_default }, + { "MP1_MASK_DIS", 2, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK[] = { + { "HST_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE", 0, 0, &umr_bitfield_default }, + { "HST_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE", 1, 1, &umr_bitfield_default }, + { "HST_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE", 2, 2, &umr_bitfield_default }, + { "HST_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE", 3, 3, &umr_bitfield_default }, + { "HST_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE", 4, 4, &umr_bitfield_default }, + { "HST_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE", 5, 5, &umr_bitfield_default }, + { "HST_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE", 6, 6, &umr_bitfield_default }, + { "HST_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE", 7, 7, &umr_bitfield_default }, + { "DMA_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE", 16, 16, &umr_bitfield_default }, + { "DMA_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE", 17, 17, &umr_bitfield_default }, + { "DMA_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE", 18, 18, &umr_bitfield_default }, + { "DMA_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE", 19, 19, &umr_bitfield_default }, + { "DMA_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE", 20, 20, &umr_bitfield_default }, + { "DMA_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE", 21, 21, &umr_bitfield_default }, + { "DMA_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE", 22, 22, &umr_bitfield_default }, + { "DMA_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE", 23, 23, &umr_bitfield_default }, + { "SYSHUB_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE", 28, 28, &umr_bitfield_default }, + { "SYSHUB_SHUBCLK_DS_EN", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_SYSHUB_DS_CTRL2_SHUBCLK[] = { + { "SYSHUB_SHUBCLK_DS_TIMER", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK[] = { + { "SYSHUB_bgen_shubclk_DMA_SW0_bypass_en", 15, 15, &umr_bitfield_default }, + { "SYSHUB_bgen_shubclk_DMA_SW1_bypass_en", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK[] = { + { "SYSHUB_bgen_shubclk_DMA_SW0_imm_en", 15, 15, &umr_bitfield_default }, + { "SYSHUB_bgen_shubclk_DMA_SW1_imm_en", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL[] = { + { "QOS_CNTL_MODE", 0, 0, &umr_bitfield_default }, + { "QOS_MAX_VALUE", 1, 4, &umr_bitfield_default }, + { "QOS_MIN_VALUE", 5, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL[] = { + { "QOS_CNTL_MODE", 0, 0, &umr_bitfield_default }, + { "QOS_MAX_VALUE", 1, 4, &umr_bitfield_default }, + { "QOS_MIN_VALUE", 5, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL[] = { + { "FLR_ON_RS_RESET_EN", 0, 0, &umr_bitfield_default }, + { "LKRST_ON_RS_RESET_EN", 1, 1, &umr_bitfield_default }, + { "QOS_STATIC_OVERRIDE_EN", 8, 8, &umr_bitfield_default }, + { "QOS_STATIC_OVERRIDE_VALUE", 9, 12, &umr_bitfield_default }, + { "READ_WRR_WEIGHT", 16, 23, &umr_bitfield_default }, + { "WRITE_WRR_WEIGHT", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL[] = { + { "FLR_ON_RS_RESET_EN", 0, 0, &umr_bitfield_default }, + { "LKRST_ON_RS_RESET_EN", 1, 1, &umr_bitfield_default }, + { "QOS_STATIC_OVERRIDE_EN", 8, 8, &umr_bitfield_default }, + { "QOS_STATIC_OVERRIDE_VALUE", 9, 12, &umr_bitfield_default }, + { "READ_WRR_WEIGHT", 16, 23, &umr_bitfield_default }, + { "WRITE_WRR_WEIGHT", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL[] = { + { "FLR_ON_RS_RESET_EN", 0, 0, &umr_bitfield_default }, + { "LKRST_ON_RS_RESET_EN", 1, 1, &umr_bitfield_default }, + { "QOS_STATIC_OVERRIDE_EN", 8, 8, &umr_bitfield_default }, + { "QOS_STATIC_OVERRIDE_VALUE", 9, 12, &umr_bitfield_default }, + { "READ_WRR_WEIGHT", 16, 23, &umr_bitfield_default }, + { "WRITE_WRR_WEIGHT", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL[] = { + { "FLR_ON_RS_RESET_EN", 0, 0, &umr_bitfield_default }, + { "LKRST_ON_RS_RESET_EN", 1, 1, &umr_bitfield_default }, + { "QOS_STATIC_OVERRIDE_EN", 8, 8, &umr_bitfield_default }, + { "QOS_STATIC_OVERRIDE_VALUE", 9, 12, &umr_bitfield_default }, + { "READ_WRR_WEIGHT", 16, 23, &umr_bitfield_default }, + { "WRITE_WRR_WEIGHT", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL[] = { + { "FLR_ON_RS_RESET_EN", 0, 0, &umr_bitfield_default }, + { "LKRST_ON_RS_RESET_EN", 1, 1, &umr_bitfield_default }, + { "QOS_STATIC_OVERRIDE_EN", 8, 8, &umr_bitfield_default }, + { "QOS_STATIC_OVERRIDE_VALUE", 9, 12, &umr_bitfield_default }, + { "READ_WRR_WEIGHT", 16, 23, &umr_bitfield_default }, + { "WRITE_WRR_WEIGHT", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL[] = { + { "FLR_ON_RS_RESET_EN", 0, 0, &umr_bitfield_default }, + { "LKRST_ON_RS_RESET_EN", 1, 1, &umr_bitfield_default }, + { "QOS_STATIC_OVERRIDE_EN", 8, 8, &umr_bitfield_default }, + { "QOS_STATIC_OVERRIDE_VALUE", 9, 12, &umr_bitfield_default }, + { "READ_WRR_WEIGHT", 16, 23, &umr_bitfield_default }, + { "WRITE_WRR_WEIGHT", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL[] = { + { "FLR_ON_RS_RESET_EN", 0, 0, &umr_bitfield_default }, + { "LKRST_ON_RS_RESET_EN", 1, 1, &umr_bitfield_default }, + { "QOS_STATIC_OVERRIDE_EN", 8, 8, &umr_bitfield_default }, + { "QOS_STATIC_OVERRIDE_VALUE", 9, 12, &umr_bitfield_default }, + { "READ_WRR_WEIGHT", 16, 23, &umr_bitfield_default }, + { "WRITE_WRR_WEIGHT", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL[] = { + { "FLR_ON_RS_RESET_EN", 0, 0, &umr_bitfield_default }, + { "LKRST_ON_RS_RESET_EN", 1, 1, &umr_bitfield_default }, + { "QOS_STATIC_OVERRIDE_EN", 8, 8, &umr_bitfield_default }, + { "QOS_STATIC_OVERRIDE_VALUE", 9, 12, &umr_bitfield_default }, + { "READ_WRR_WEIGHT", 16, 23, &umr_bitfield_default }, + { "WRITE_WRR_WEIGHT", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL[] = { + { "FLR_ON_RS_RESET_EN", 0, 0, &umr_bitfield_default }, + { "LKRST_ON_RS_RESET_EN", 1, 1, &umr_bitfield_default }, + { "QOS_STATIC_OVERRIDE_EN", 8, 8, &umr_bitfield_default }, + { "QOS_STATIC_OVERRIDE_VALUE", 9, 12, &umr_bitfield_default }, + { "READ_WRR_WEIGHT", 16, 23, &umr_bitfield_default }, + { "WRITE_WRR_WEIGHT", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL[] = { + { "FLR_ON_RS_RESET_EN", 0, 0, &umr_bitfield_default }, + { "LKRST_ON_RS_RESET_EN", 1, 1, &umr_bitfield_default }, + { "QOS_STATIC_OVERRIDE_EN", 8, 8, &umr_bitfield_default }, + { "QOS_STATIC_OVERRIDE_VALUE", 9, 12, &umr_bitfield_default }, + { "READ_WRR_WEIGHT", 16, 23, &umr_bitfield_default }, + { "WRITE_WRR_WEIGHT", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK[] = { + { "SYSHUB_MGCG_EN_SHUBCLK", 0, 0, &umr_bitfield_default }, + { "SYSHUB_MGCG_MODE_SHUBCLK", 1, 1, &umr_bitfield_default }, + { "SYSHUB_MGCG_HYSTERESIS_SHUBCLK", 2, 9, &umr_bitfield_default }, + { "SYSHUB_MGCG_HST_DIS_SHUBCLK", 10, 10, &umr_bitfield_default }, + { "SYSHUB_MGCG_DMA_DIS_SHUBCLK", 11, 11, &umr_bitfield_default }, + { "SYSHUB_MGCG_REGS_DIS_SHUBCLK", 12, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_NIC400_0_ASIB_0_FN_MOD[] = { + { "read_iss_override", 0, 0, &umr_bitfield_default }, + { "write_iss_override", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_NIC400_0_AMIB_0_FN_MOD_BM_ISS[] = { + { "read_iss_override", 0, 0, &umr_bitfield_default }, + { "write_iss_override", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_NIC400_0_AMIB_1_FN_MOD_BM_ISS[] = { + { "read_iss_override", 0, 0, &umr_bitfield_default }, + { "write_iss_override", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_NIC400_1_ASIB_0_FN_MOD[] = { + { "read_iss_override", 0, 0, &umr_bitfield_default }, + { "write_iss_override", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_NIC400_1_AMIB_0_FN_MOD[] = { + { "read_iss_override", 0, 0, &umr_bitfield_default }, + { "write_iss_override", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_NIC400_1_AMIB_1_FN_MOD[] = { + { "read_iss_override", 0, 0, &umr_bitfield_default }, + { "write_iss_override", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_NIC400_1_AMIB_2_FN_MOD[] = { + { "read_iss_override", 0, 0, &umr_bitfield_default }, + { "write_iss_override", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_NIC400_2_ASIB_0_FN_MOD[] = { + { "read_iss_override", 0, 0, &umr_bitfield_default }, + { "write_iss_override", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_NIC400_2_ASIB_1_FN_MOD[] = { + { "read_iss_override", 0, 0, &umr_bitfield_default }, + { "write_iss_override", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_NIC400_2_ASIB_2_FN_MOD[] = { + { "read_iss_override", 0, 0, &umr_bitfield_default }, + { "write_iss_override", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_NIC400_2_ASIB_3_FN_MOD[] = { + { "read_iss_override", 0, 0, &umr_bitfield_default }, + { "write_iss_override", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_NIC400_2_ASIB_4_FN_MOD[] = { + { "read_iss_override", 0, 0, &umr_bitfield_default }, + { "write_iss_override", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_NIC400_2_AMIB_0_FN_MOD_BM_ISS[] = { + { "read_iss_override", 0, 0, &umr_bitfield_default }, + { "write_iss_override", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_NIC400_5_ASIB_0_FN_MOD[] = { + { "read_iss_override", 0, 0, &umr_bitfield_default }, + { "write_iss_override", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_NIC400_5_ASIB_1_FN_MOD[] = { + { "read_iss_override", 0, 0, &umr_bitfield_default }, + { "write_iss_override", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_NIC400_5_ASIB_2_FN_MOD[] = { + { "read_iss_override", 0, 0, &umr_bitfield_default }, + { "write_iss_override", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_NIC400_5_ASIB_3_FN_MOD[] = { + { "read_iss_override", 0, 0, &umr_bitfield_default }, + { "write_iss_override", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_NIC400_5_ASIB_4_FN_MOD[] = { + { "read_iss_override", 0, 0, &umr_bitfield_default }, + { "write_iss_override", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_NIC400_5_AMIB_0_FN_MOD[] = { + { "read_iss_override", 0, 0, &umr_bitfield_default }, + { "write_iss_override", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_NIC400_4_ASIB_0_FN_MOD[] = { + { "read_iss_override", 0, 0, &umr_bitfield_default }, + { "write_iss_override", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_NIC400_4_ASIB_1_FN_MOD[] = { + { "read_iss_override", 0, 0, &umr_bitfield_default }, + { "write_iss_override", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield ixSYSHUB_MMREG_IND_NIC400_4_AMIB_0_FN_MOD[] = { + { "read_iss_override", 0, 0, &umr_bitfield_default }, + { "write_iss_override", 1, 1, &umr_bitfield_default }, +}; diff --git a/src/lib/ip/nbio70_regs.i b/src/lib/ip/nbio70_regs.i new file mode 100644 index 0000000..77214d5 --- /dev/null +++ b/src/lib/ip/nbio70_regs.i @@ -0,0 +1,553 @@ + { "mmport_a_addr", REG_MMIO, 0x01ac, 1, &mmport_a_addr[0], sizeof(mmport_a_addr)/sizeof(mmport_a_addr[0]), 0, 0 }, + { "mmport_a_data_lo", REG_MMIO, 0x01ad, 1, &mmport_a_data_lo[0], sizeof(mmport_a_data_lo)/sizeof(mmport_a_data_lo[0]), 0, 0 }, + { "mmport_a_data_hi", REG_MMIO, 0x01ae, 1, &mmport_a_data_hi[0], sizeof(mmport_a_data_hi)/sizeof(mmport_a_data_hi[0]), 0, 0 }, + { "mmport_b_addr", REG_MMIO, 0x01af, 1, &mmport_b_addr[0], sizeof(mmport_b_addr)/sizeof(mmport_b_addr[0]), 0, 0 }, + { "mmport_b_data_lo", REG_MMIO, 0x01b0, 1, &mmport_b_data_lo[0], sizeof(mmport_b_data_lo)/sizeof(mmport_b_data_lo[0]), 0, 0 }, + { "mmport_b_data_hi", REG_MMIO, 0x01b1, 1, &mmport_b_data_hi[0], sizeof(mmport_b_data_hi)/sizeof(mmport_b_data_hi[0]), 0, 0 }, + { "mmport_c_addr", REG_MMIO, 0x01b2, 1, &mmport_c_addr[0], sizeof(mmport_c_addr)/sizeof(mmport_c_addr[0]), 0, 0 }, + { "mmport_c_data_lo", REG_MMIO, 0x01b3, 1, &mmport_c_data_lo[0], sizeof(mmport_c_data_lo)/sizeof(mmport_c_data_lo[0]), 0, 0 }, + { "mmport_c_data_hi", REG_MMIO, 0x01b4, 1, &mmport_c_data_hi[0], sizeof(mmport_c_data_hi)/sizeof(mmport_c_data_hi[0]), 0, 0 }, + { "mmport_d_addr", REG_MMIO, 0x01b5, 1, &mmport_d_addr[0], sizeof(mmport_d_addr)/sizeof(mmport_d_addr[0]), 0, 0 }, + { "mmport_d_data_lo", REG_MMIO, 0x01b6, 1, &mmport_d_data_lo[0], sizeof(mmport_d_data_lo)/sizeof(mmport_d_data_lo[0]), 0, 0 }, + { "mmport_d_data_hi", REG_MMIO, 0x01b7, 1, &mmport_d_data_hi[0], sizeof(mmport_d_data_hi)/sizeof(mmport_d_data_hi[0]), 0, 0 }, + { "mmIOMMU_MMIO_DEVTBL_BASE_0", REG_MMIO, 0x0000, 0, &mmIOMMU_MMIO_DEVTBL_BASE_0[0], sizeof(mmIOMMU_MMIO_DEVTBL_BASE_0)/sizeof(mmIOMMU_MMIO_DEVTBL_BASE_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_DEVTBL_BASE_1", REG_MMIO, 0x0001, 0, &mmIOMMU_MMIO_DEVTBL_BASE_1[0], sizeof(mmIOMMU_MMIO_DEVTBL_BASE_1)/sizeof(mmIOMMU_MMIO_DEVTBL_BASE_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_CMD_BASE_0", REG_MMIO, 0x0002, 0, &mmIOMMU_MMIO_CMD_BASE_0[0], sizeof(mmIOMMU_MMIO_CMD_BASE_0)/sizeof(mmIOMMU_MMIO_CMD_BASE_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_CMD_BASE_1", REG_MMIO, 0x0003, 0, &mmIOMMU_MMIO_CMD_BASE_1[0], sizeof(mmIOMMU_MMIO_CMD_BASE_1)/sizeof(mmIOMMU_MMIO_CMD_BASE_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_EVENT_BASE_0", REG_MMIO, 0x0004, 0, &mmIOMMU_MMIO_EVENT_BASE_0[0], sizeof(mmIOMMU_MMIO_EVENT_BASE_0)/sizeof(mmIOMMU_MMIO_EVENT_BASE_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_EVENT_BASE_1", REG_MMIO, 0x0005, 0, &mmIOMMU_MMIO_EVENT_BASE_1[0], sizeof(mmIOMMU_MMIO_EVENT_BASE_1)/sizeof(mmIOMMU_MMIO_EVENT_BASE_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_CNTRL_0", REG_MMIO, 0x0006, 0, &mmIOMMU_MMIO_CNTRL_0[0], sizeof(mmIOMMU_MMIO_CNTRL_0)/sizeof(mmIOMMU_MMIO_CNTRL_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_CNTRL_1", REG_MMIO, 0x0007, 0, &mmIOMMU_MMIO_CNTRL_1[0], sizeof(mmIOMMU_MMIO_CNTRL_1)/sizeof(mmIOMMU_MMIO_CNTRL_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_EXCL_BASE_0", REG_MMIO, 0x0008, 0, &mmIOMMU_MMIO_EXCL_BASE_0[0], sizeof(mmIOMMU_MMIO_EXCL_BASE_0)/sizeof(mmIOMMU_MMIO_EXCL_BASE_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_EXCL_BASE_1", REG_MMIO, 0x0009, 0, &mmIOMMU_MMIO_EXCL_BASE_1[0], sizeof(mmIOMMU_MMIO_EXCL_BASE_1)/sizeof(mmIOMMU_MMIO_EXCL_BASE_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_EXCL_LIM_0", REG_MMIO, 0x000a, 0, &mmIOMMU_MMIO_EXCL_LIM_0[0], sizeof(mmIOMMU_MMIO_EXCL_LIM_0)/sizeof(mmIOMMU_MMIO_EXCL_LIM_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_EXCL_LIM_1", REG_MMIO, 0x000b, 0, &mmIOMMU_MMIO_EXCL_LIM_1[0], sizeof(mmIOMMU_MMIO_EXCL_LIM_1)/sizeof(mmIOMMU_MMIO_EXCL_LIM_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_EFR_0", REG_MMIO, 0x000c, 0, &mmIOMMU_MMIO_EFR_0[0], sizeof(mmIOMMU_MMIO_EFR_0)/sizeof(mmIOMMU_MMIO_EFR_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_EFR_1", REG_MMIO, 0x000d, 0, &mmIOMMU_MMIO_EFR_1[0], sizeof(mmIOMMU_MMIO_EFR_1)/sizeof(mmIOMMU_MMIO_EFR_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_PPR_BASE_0", REG_MMIO, 0x000e, 0, &mmIOMMU_MMIO_PPR_BASE_0[0], sizeof(mmIOMMU_MMIO_PPR_BASE_0)/sizeof(mmIOMMU_MMIO_PPR_BASE_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_PPR_BASE_1", REG_MMIO, 0x000f, 0, &mmIOMMU_MMIO_PPR_BASE_1[0], sizeof(mmIOMMU_MMIO_PPR_BASE_1)/sizeof(mmIOMMU_MMIO_PPR_BASE_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_HW_ERR_UPPER_0", REG_MMIO, 0x0010, 0, &mmIOMMU_MMIO_HW_ERR_UPPER_0[0], sizeof(mmIOMMU_MMIO_HW_ERR_UPPER_0)/sizeof(mmIOMMU_MMIO_HW_ERR_UPPER_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_HW_ERR_UPPER_1", REG_MMIO, 0x0011, 0, &mmIOMMU_MMIO_HW_ERR_UPPER_1[0], sizeof(mmIOMMU_MMIO_HW_ERR_UPPER_1)/sizeof(mmIOMMU_MMIO_HW_ERR_UPPER_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_HW_ERR_LOWER_0", REG_MMIO, 0x0012, 0, &mmIOMMU_MMIO_HW_ERR_LOWER_0[0], sizeof(mmIOMMU_MMIO_HW_ERR_LOWER_0)/sizeof(mmIOMMU_MMIO_HW_ERR_LOWER_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_HW_ERR_LOWER_1", REG_MMIO, 0x0013, 0, &mmIOMMU_MMIO_HW_ERR_LOWER_1[0], sizeof(mmIOMMU_MMIO_HW_ERR_LOWER_1)/sizeof(mmIOMMU_MMIO_HW_ERR_LOWER_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_HW_ERR_STATUS_0", REG_MMIO, 0x0000, 1, &mmIOMMU_MMIO_HW_ERR_STATUS_0[0], sizeof(mmIOMMU_MMIO_HW_ERR_STATUS_0)/sizeof(mmIOMMU_MMIO_HW_ERR_STATUS_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_HW_ERR_STATUS_1", REG_MMIO, 0x0001, 1, &mmIOMMU_MMIO_HW_ERR_STATUS_1[0], sizeof(mmIOMMU_MMIO_HW_ERR_STATUS_1)/sizeof(mmIOMMU_MMIO_HW_ERR_STATUS_1[0]), 0, 0 }, + { "mmSMI_FILTER_REGISTER_0_0", REG_MMIO, 0x0004, 1, &mmSMI_FILTER_REGISTER_0_0[0], sizeof(mmSMI_FILTER_REGISTER_0_0)/sizeof(mmSMI_FILTER_REGISTER_0_0[0]), 0, 0 }, + { "mmSMI_FILTER_REGISTER_0_1", REG_MMIO, 0x0005, 1, &mmSMI_FILTER_REGISTER_0_1[0], sizeof(mmSMI_FILTER_REGISTER_0_1)/sizeof(mmSMI_FILTER_REGISTER_0_1[0]), 0, 0 }, + { "mmSMI_FILTER_REGISTER_1_0", REG_MMIO, 0x0006, 1, &mmSMI_FILTER_REGISTER_1_0[0], sizeof(mmSMI_FILTER_REGISTER_1_0)/sizeof(mmSMI_FILTER_REGISTER_1_0[0]), 0, 0 }, + { "mmSMI_FILTER_REGISTER_1_1", REG_MMIO, 0x0007, 1, &mmSMI_FILTER_REGISTER_1_1[0], sizeof(mmSMI_FILTER_REGISTER_1_1)/sizeof(mmSMI_FILTER_REGISTER_1_1[0]), 0, 0 }, + { "mmSMI_FILTER_REGISTER_2_0", REG_MMIO, 0x0008, 1, &mmSMI_FILTER_REGISTER_2_0[0], sizeof(mmSMI_FILTER_REGISTER_2_0)/sizeof(mmSMI_FILTER_REGISTER_2_0[0]), 0, 0 }, + { "mmSMI_FILTER_REGISTER_2_1", REG_MMIO, 0x0009, 1, &mmSMI_FILTER_REGISTER_2_1[0], sizeof(mmSMI_FILTER_REGISTER_2_1)/sizeof(mmSMI_FILTER_REGISTER_2_1[0]), 0, 0 }, + { "mmSMI_FILTER_REGISTER_3_0", REG_MMIO, 0x000a, 1, &mmSMI_FILTER_REGISTER_3_0[0], sizeof(mmSMI_FILTER_REGISTER_3_0)/sizeof(mmSMI_FILTER_REGISTER_3_0[0]), 0, 0 }, + { "mmSMI_FILTER_REGISTER_3_1", REG_MMIO, 0x000b, 1, &mmSMI_FILTER_REGISTER_3_1[0], sizeof(mmSMI_FILTER_REGISTER_3_1)/sizeof(mmSMI_FILTER_REGISTER_3_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_GA_LOG_BASE_0", REG_MMIO, 0x0024, 1, &mmIOMMU_MMIO_GA_LOG_BASE_0[0], sizeof(mmIOMMU_MMIO_GA_LOG_BASE_0)/sizeof(mmIOMMU_MMIO_GA_LOG_BASE_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_GA_LOG_BASE_1", REG_MMIO, 0x0025, 1, &mmIOMMU_MMIO_GA_LOG_BASE_1[0], sizeof(mmIOMMU_MMIO_GA_LOG_BASE_1)/sizeof(mmIOMMU_MMIO_GA_LOG_BASE_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_GA_LOG_TAILPTR_ADDR_0", REG_MMIO, 0x0026, 1, &mmIOMMU_MMIO_GA_LOG_TAILPTR_ADDR_0[0], sizeof(mmIOMMU_MMIO_GA_LOG_TAILPTR_ADDR_0)/sizeof(mmIOMMU_MMIO_GA_LOG_TAILPTR_ADDR_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_GA_LOG_TAILPTR_ADDR_1", REG_MMIO, 0x0027, 1, &mmIOMMU_MMIO_GA_LOG_TAILPTR_ADDR_1[0], sizeof(mmIOMMU_MMIO_GA_LOG_TAILPTR_ADDR_1)/sizeof(mmIOMMU_MMIO_GA_LOG_TAILPTR_ADDR_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_PPR_B_BASE_0", REG_MMIO, 0x0028, 1, &mmIOMMU_MMIO_PPR_B_BASE_0[0], sizeof(mmIOMMU_MMIO_PPR_B_BASE_0)/sizeof(mmIOMMU_MMIO_PPR_B_BASE_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_PPR_B_BASE_1", REG_MMIO, 0x0029, 1, &mmIOMMU_MMIO_PPR_B_BASE_1[0], sizeof(mmIOMMU_MMIO_PPR_B_BASE_1)/sizeof(mmIOMMU_MMIO_PPR_B_BASE_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_EVENT_B_BASE_0", REG_MMIO, 0x002a, 1, &mmIOMMU_MMIO_EVENT_B_BASE_0[0], sizeof(mmIOMMU_MMIO_EVENT_B_BASE_0)/sizeof(mmIOMMU_MMIO_EVENT_B_BASE_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_EVENT_B_BASE_1", REG_MMIO, 0x002b, 1, &mmIOMMU_MMIO_EVENT_B_BASE_1[0], sizeof(mmIOMMU_MMIO_EVENT_B_BASE_1)/sizeof(mmIOMMU_MMIO_EVENT_B_BASE_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_DEVTBL_1_BASE_0", REG_MMIO, 0x002c, 1, &mmIOMMU_MMIO_DEVTBL_1_BASE_0[0], sizeof(mmIOMMU_MMIO_DEVTBL_1_BASE_0)/sizeof(mmIOMMU_MMIO_DEVTBL_1_BASE_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_DEVTBL_1_BASE_1", REG_MMIO, 0x002d, 1, &mmIOMMU_MMIO_DEVTBL_1_BASE_1[0], sizeof(mmIOMMU_MMIO_DEVTBL_1_BASE_1)/sizeof(mmIOMMU_MMIO_DEVTBL_1_BASE_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_DEVTBL_2_BASE_0", REG_MMIO, 0x002e, 1, &mmIOMMU_MMIO_DEVTBL_2_BASE_0[0], sizeof(mmIOMMU_MMIO_DEVTBL_2_BASE_0)/sizeof(mmIOMMU_MMIO_DEVTBL_2_BASE_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_DEVTBL_2_BASE_1", REG_MMIO, 0x002f, 1, &mmIOMMU_MMIO_DEVTBL_2_BASE_1[0], sizeof(mmIOMMU_MMIO_DEVTBL_2_BASE_1)/sizeof(mmIOMMU_MMIO_DEVTBL_2_BASE_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_DEVTBL_3_BASE_0", REG_MMIO, 0x0030, 1, &mmIOMMU_MMIO_DEVTBL_3_BASE_0[0], sizeof(mmIOMMU_MMIO_DEVTBL_3_BASE_0)/sizeof(mmIOMMU_MMIO_DEVTBL_3_BASE_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_DEVTBL_3_BASE_1", REG_MMIO, 0x0031, 1, &mmIOMMU_MMIO_DEVTBL_3_BASE_1[0], sizeof(mmIOMMU_MMIO_DEVTBL_3_BASE_1)/sizeof(mmIOMMU_MMIO_DEVTBL_3_BASE_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_DEVTBL_4_BASE_0", REG_MMIO, 0x0032, 1, &mmIOMMU_MMIO_DEVTBL_4_BASE_0[0], sizeof(mmIOMMU_MMIO_DEVTBL_4_BASE_0)/sizeof(mmIOMMU_MMIO_DEVTBL_4_BASE_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_DEVTBL_4_BASE_1", REG_MMIO, 0x0033, 1, &mmIOMMU_MMIO_DEVTBL_4_BASE_1[0], sizeof(mmIOMMU_MMIO_DEVTBL_4_BASE_1)/sizeof(mmIOMMU_MMIO_DEVTBL_4_BASE_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_DEVTBL_5_BASE_0", REG_MMIO, 0x0034, 1, &mmIOMMU_MMIO_DEVTBL_5_BASE_0[0], sizeof(mmIOMMU_MMIO_DEVTBL_5_BASE_0)/sizeof(mmIOMMU_MMIO_DEVTBL_5_BASE_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_DEVTBL_5_BASE_1", REG_MMIO, 0x0035, 1, &mmIOMMU_MMIO_DEVTBL_5_BASE_1[0], sizeof(mmIOMMU_MMIO_DEVTBL_5_BASE_1)/sizeof(mmIOMMU_MMIO_DEVTBL_5_BASE_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_DEVTBL_6_BASE_0", REG_MMIO, 0x0036, 1, &mmIOMMU_MMIO_DEVTBL_6_BASE_0[0], sizeof(mmIOMMU_MMIO_DEVTBL_6_BASE_0)/sizeof(mmIOMMU_MMIO_DEVTBL_6_BASE_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_DEVTBL_6_BASE_1", REG_MMIO, 0x0037, 1, &mmIOMMU_MMIO_DEVTBL_6_BASE_1[0], sizeof(mmIOMMU_MMIO_DEVTBL_6_BASE_1)/sizeof(mmIOMMU_MMIO_DEVTBL_6_BASE_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_DEVTBL_7_BASE_0", REG_MMIO, 0x0038, 1, &mmIOMMU_MMIO_DEVTBL_7_BASE_0[0], sizeof(mmIOMMU_MMIO_DEVTBL_7_BASE_0)/sizeof(mmIOMMU_MMIO_DEVTBL_7_BASE_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_DEVTBL_7_BASE_1", REG_MMIO, 0x0039, 1, &mmIOMMU_MMIO_DEVTBL_7_BASE_1[0], sizeof(mmIOMMU_MMIO_DEVTBL_7_BASE_1)/sizeof(mmIOMMU_MMIO_DEVTBL_7_BASE_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_DSFX", REG_MMIO, 0x003a, 1, &mmIOMMU_MMIO_DSFX[0], sizeof(mmIOMMU_MMIO_DSFX)/sizeof(mmIOMMU_MMIO_DSFX[0]), 0, 0 }, + { "mmIOMMU_MMIO_DSCX", REG_MMIO, 0x003c, 1, &mmIOMMU_MMIO_DSCX[0], sizeof(mmIOMMU_MMIO_DSCX)/sizeof(mmIOMMU_MMIO_DSCX[0]), 0, 0 }, + { "mmIOMMU_MMIO_DSSX", REG_MMIO, 0x003e, 1, &mmIOMMU_MMIO_DSSX[0], sizeof(mmIOMMU_MMIO_DSSX)/sizeof(mmIOMMU_MMIO_DSSX[0]), 0, 0 }, + { "mmIOMMU_MMIO_CAP_MISC", REG_MMIO, 0x0040, 1, &mmIOMMU_MMIO_CAP_MISC[0], sizeof(mmIOMMU_MMIO_CAP_MISC)/sizeof(mmIOMMU_MMIO_CAP_MISC[0]), 0, 0 }, + { "mmIOMMU_MMIO_CAP_MISC_1", REG_MMIO, 0x0041, 1, &mmIOMMU_MMIO_CAP_MISC_1[0], sizeof(mmIOMMU_MMIO_CAP_MISC_1)/sizeof(mmIOMMU_MMIO_CAP_MISC_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_MSI_CAP", REG_MMIO, 0x0042, 1, &mmIOMMU_MMIO_MSI_CAP[0], sizeof(mmIOMMU_MMIO_MSI_CAP)/sizeof(mmIOMMU_MMIO_MSI_CAP[0]), 0, 0 }, + { "mmIOMMU_MMIO_MSI_ADDR_LO", REG_MMIO, 0x0043, 1, &mmIOMMU_MMIO_MSI_ADDR_LO[0], sizeof(mmIOMMU_MMIO_MSI_ADDR_LO)/sizeof(mmIOMMU_MMIO_MSI_ADDR_LO[0]), 0, 0 }, + { "mmIOMMU_MMIO_MSI_ADDR_HI", REG_MMIO, 0x0044, 1, &mmIOMMU_MMIO_MSI_ADDR_HI[0], sizeof(mmIOMMU_MMIO_MSI_ADDR_HI)/sizeof(mmIOMMU_MMIO_MSI_ADDR_HI[0]), 0, 0 }, + { "mmIOMMU_MMIO_MSI_DATA", REG_MMIO, 0x0045, 1, &mmIOMMU_MMIO_MSI_DATA[0], sizeof(mmIOMMU_MMIO_MSI_DATA)/sizeof(mmIOMMU_MMIO_MSI_DATA[0]), 0, 0 }, + { "mmIOMMU_MMIO_MSI_MAPPING_CAP", REG_MMIO, 0x0046, 1, &mmIOMMU_MMIO_MSI_MAPPING_CAP[0], sizeof(mmIOMMU_MMIO_MSI_MAPPING_CAP)/sizeof(mmIOMMU_MMIO_MSI_MAPPING_CAP[0]), 0, 0 }, + { "mmIOMMU_MMIO_CONTROL_W", REG_MMIO, 0x0047, 1, &mmIOMMU_MMIO_CONTROL_W[0], sizeof(mmIOMMU_MMIO_CONTROL_W)/sizeof(mmIOMMU_MMIO_CONTROL_W[0]), 0, 0 }, + { "mmIOMMU_MARC_BASE_LO_0", REG_MMIO, 0x006c, 1, &mmIOMMU_MARC_BASE_LO_0[0], sizeof(mmIOMMU_MARC_BASE_LO_0)/sizeof(mmIOMMU_MARC_BASE_LO_0[0]), 0, 0 }, + { "mmIOMMU_MARC_BASE_HI_0", REG_MMIO, 0x006d, 1, &mmIOMMU_MARC_BASE_HI_0[0], sizeof(mmIOMMU_MARC_BASE_HI_0)/sizeof(mmIOMMU_MARC_BASE_HI_0[0]), 0, 0 }, + { "mmIOMMU_MARC_RELOC_LO_0", REG_MMIO, 0x006e, 1, &mmIOMMU_MARC_RELOC_LO_0[0], sizeof(mmIOMMU_MARC_RELOC_LO_0)/sizeof(mmIOMMU_MARC_RELOC_LO_0[0]), 0, 0 }, + { "mmIOMMU_MARC_RELOC_HI_0", REG_MMIO, 0x006f, 1, &mmIOMMU_MARC_RELOC_HI_0[0], sizeof(mmIOMMU_MARC_RELOC_HI_0)/sizeof(mmIOMMU_MARC_RELOC_HI_0[0]), 0, 0 }, + { "mmIOMMU_MARC_LEN_LO_0", REG_MMIO, 0x0070, 1, &mmIOMMU_MARC_LEN_LO_0[0], sizeof(mmIOMMU_MARC_LEN_LO_0)/sizeof(mmIOMMU_MARC_LEN_LO_0[0]), 0, 0 }, + { "mmIOMMU_MARC_LEN_HI_0", REG_MMIO, 0x0071, 1, &mmIOMMU_MARC_LEN_HI_0[0], sizeof(mmIOMMU_MARC_LEN_HI_0)/sizeof(mmIOMMU_MARC_LEN_HI_0[0]), 0, 0 }, + { "mmIOMMU_MARC_BASE_LO_1", REG_MMIO, 0x0072, 1, &mmIOMMU_MARC_BASE_LO_1[0], sizeof(mmIOMMU_MARC_BASE_LO_1)/sizeof(mmIOMMU_MARC_BASE_LO_1[0]), 0, 0 }, + { "mmIOMMU_MARC_BASE_HI_1", REG_MMIO, 0x0073, 1, &mmIOMMU_MARC_BASE_HI_1[0], sizeof(mmIOMMU_MARC_BASE_HI_1)/sizeof(mmIOMMU_MARC_BASE_HI_1[0]), 0, 0 }, + { "mmIOMMU_MARC_RELOC_LO_1", REG_MMIO, 0x0074, 1, &mmIOMMU_MARC_RELOC_LO_1[0], sizeof(mmIOMMU_MARC_RELOC_LO_1)/sizeof(mmIOMMU_MARC_RELOC_LO_1[0]), 0, 0 }, + { "mmIOMMU_MARC_RELOC_HI_1", REG_MMIO, 0x0075, 1, &mmIOMMU_MARC_RELOC_HI_1[0], sizeof(mmIOMMU_MARC_RELOC_HI_1)/sizeof(mmIOMMU_MARC_RELOC_HI_1[0]), 0, 0 }, + { "mmIOMMU_MARC_LEN_LO_1", REG_MMIO, 0x0076, 1, &mmIOMMU_MARC_LEN_LO_1[0], sizeof(mmIOMMU_MARC_LEN_LO_1)/sizeof(mmIOMMU_MARC_LEN_LO_1[0]), 0, 0 }, + { "mmIOMMU_MARC_LEN_HI_1", REG_MMIO, 0x0077, 1, &mmIOMMU_MARC_LEN_HI_1[0], sizeof(mmIOMMU_MARC_LEN_HI_1)/sizeof(mmIOMMU_MARC_LEN_HI_1[0]), 0, 0 }, + { "mmIOMMU_MARC_BASE_LO_2", REG_MMIO, 0x0078, 1, &mmIOMMU_MARC_BASE_LO_2[0], sizeof(mmIOMMU_MARC_BASE_LO_2)/sizeof(mmIOMMU_MARC_BASE_LO_2[0]), 0, 0 }, + { "mmIOMMU_MARC_BASE_HI_2", REG_MMIO, 0x0079, 1, &mmIOMMU_MARC_BASE_HI_2[0], sizeof(mmIOMMU_MARC_BASE_HI_2)/sizeof(mmIOMMU_MARC_BASE_HI_2[0]), 0, 0 }, + { "mmIOMMU_MARC_RELOC_LO_2", REG_MMIO, 0x007a, 1, &mmIOMMU_MARC_RELOC_LO_2[0], sizeof(mmIOMMU_MARC_RELOC_LO_2)/sizeof(mmIOMMU_MARC_RELOC_LO_2[0]), 0, 0 }, + { "mmIOMMU_MARC_RELOC_HI_2", REG_MMIO, 0x007b, 1, &mmIOMMU_MARC_RELOC_HI_2[0], sizeof(mmIOMMU_MARC_RELOC_HI_2)/sizeof(mmIOMMU_MARC_RELOC_HI_2[0]), 0, 0 }, + { "mmIOMMU_MARC_LEN_LO_2", REG_MMIO, 0x007c, 1, &mmIOMMU_MARC_LEN_LO_2[0], sizeof(mmIOMMU_MARC_LEN_LO_2)/sizeof(mmIOMMU_MARC_LEN_LO_2[0]), 0, 0 }, + { "mmIOMMU_MARC_LEN_HI_2", REG_MMIO, 0x007d, 1, &mmIOMMU_MARC_LEN_HI_2[0], sizeof(mmIOMMU_MARC_LEN_HI_2)/sizeof(mmIOMMU_MARC_LEN_HI_2[0]), 0, 0 }, + { "mmIOMMU_MARC_BASE_LO_3", REG_MMIO, 0x007e, 1, &mmIOMMU_MARC_BASE_LO_3[0], sizeof(mmIOMMU_MARC_BASE_LO_3)/sizeof(mmIOMMU_MARC_BASE_LO_3[0]), 0, 0 }, + { "mmIOMMU_MARC_BASE_HI_3", REG_MMIO, 0x007f, 1, &mmIOMMU_MARC_BASE_HI_3[0], sizeof(mmIOMMU_MARC_BASE_HI_3)/sizeof(mmIOMMU_MARC_BASE_HI_3[0]), 0, 0 }, + { "mmIOMMU_MARC_RELOC_LO_3", REG_MMIO, 0x0080, 1, &mmIOMMU_MARC_RELOC_LO_3[0], sizeof(mmIOMMU_MARC_RELOC_LO_3)/sizeof(mmIOMMU_MARC_RELOC_LO_3[0]), 0, 0 }, + { "mmIOMMU_MARC_RELOC_HI_3", REG_MMIO, 0x0081, 1, &mmIOMMU_MARC_RELOC_HI_3[0], sizeof(mmIOMMU_MARC_RELOC_HI_3)/sizeof(mmIOMMU_MARC_RELOC_HI_3[0]), 0, 0 }, + { "mmIOMMU_MARC_LEN_LO_3", REG_MMIO, 0x0082, 1, &mmIOMMU_MARC_LEN_LO_3[0], sizeof(mmIOMMU_MARC_LEN_LO_3)/sizeof(mmIOMMU_MARC_LEN_LO_3[0]), 0, 0 }, + { "mmIOMMU_MARC_LEN_HI_3", REG_MMIO, 0x0083, 1, &mmIOMMU_MARC_LEN_HI_3[0], sizeof(mmIOMMU_MARC_LEN_HI_3)/sizeof(mmIOMMU_MARC_LEN_HI_3[0]), 0, 0 }, + { "mmIOMMU_MMIO_CMD_BUF_HDPTR_0", REG_MMIO, 0x07ec, 1, &mmIOMMU_MMIO_CMD_BUF_HDPTR_0[0], sizeof(mmIOMMU_MMIO_CMD_BUF_HDPTR_0)/sizeof(mmIOMMU_MMIO_CMD_BUF_HDPTR_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_CMD_BUF_HDPTR_1", REG_MMIO, 0x07ed, 1, &mmIOMMU_MMIO_CMD_BUF_HDPTR_1[0], sizeof(mmIOMMU_MMIO_CMD_BUF_HDPTR_1)/sizeof(mmIOMMU_MMIO_CMD_BUF_HDPTR_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_CMD_BUF_TAILPTR_0", REG_MMIO, 0x07ee, 1, &mmIOMMU_MMIO_CMD_BUF_TAILPTR_0[0], sizeof(mmIOMMU_MMIO_CMD_BUF_TAILPTR_0)/sizeof(mmIOMMU_MMIO_CMD_BUF_TAILPTR_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_CMD_BUF_TAILPTR_1", REG_MMIO, 0x07ef, 1, &mmIOMMU_MMIO_CMD_BUF_TAILPTR_1[0], sizeof(mmIOMMU_MMIO_CMD_BUF_TAILPTR_1)/sizeof(mmIOMMU_MMIO_CMD_BUF_TAILPTR_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_EVENT_BUF_HDPTR_0", REG_MMIO, 0x07f0, 1, &mmIOMMU_MMIO_EVENT_BUF_HDPTR_0[0], sizeof(mmIOMMU_MMIO_EVENT_BUF_HDPTR_0)/sizeof(mmIOMMU_MMIO_EVENT_BUF_HDPTR_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_EVENT_BUF_HDPTR_1", REG_MMIO, 0x07f1, 1, &mmIOMMU_MMIO_EVENT_BUF_HDPTR_1[0], sizeof(mmIOMMU_MMIO_EVENT_BUF_HDPTR_1)/sizeof(mmIOMMU_MMIO_EVENT_BUF_HDPTR_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_EVENT_BUF_TAILPTR_0", REG_MMIO, 0x07f2, 1, &mmIOMMU_MMIO_EVENT_BUF_TAILPTR_0[0], sizeof(mmIOMMU_MMIO_EVENT_BUF_TAILPTR_0)/sizeof(mmIOMMU_MMIO_EVENT_BUF_TAILPTR_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_EVENT_BUF_TAILPTR_1", REG_MMIO, 0x07f3, 1, &mmIOMMU_MMIO_EVENT_BUF_TAILPTR_1[0], sizeof(mmIOMMU_MMIO_EVENT_BUF_TAILPTR_1)/sizeof(mmIOMMU_MMIO_EVENT_BUF_TAILPTR_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_STATUS_0", REG_MMIO, 0x07f4, 1, &mmIOMMU_MMIO_STATUS_0[0], sizeof(mmIOMMU_MMIO_STATUS_0)/sizeof(mmIOMMU_MMIO_STATUS_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_STATUS_1", REG_MMIO, 0x07f5, 1, &mmIOMMU_MMIO_STATUS_1[0], sizeof(mmIOMMU_MMIO_STATUS_1)/sizeof(mmIOMMU_MMIO_STATUS_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_PPR_BUF_HDPTR_0", REG_MMIO, 0x07f8, 1, &mmIOMMU_MMIO_PPR_BUF_HDPTR_0[0], sizeof(mmIOMMU_MMIO_PPR_BUF_HDPTR_0)/sizeof(mmIOMMU_MMIO_PPR_BUF_HDPTR_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_PPR_BUF_HDPTR_1", REG_MMIO, 0x07f9, 1, &mmIOMMU_MMIO_PPR_BUF_HDPTR_1[0], sizeof(mmIOMMU_MMIO_PPR_BUF_HDPTR_1)/sizeof(mmIOMMU_MMIO_PPR_BUF_HDPTR_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_PPR_BUF_TAILPTR_0", REG_MMIO, 0x07fa, 1, &mmIOMMU_MMIO_PPR_BUF_TAILPTR_0[0], sizeof(mmIOMMU_MMIO_PPR_BUF_TAILPTR_0)/sizeof(mmIOMMU_MMIO_PPR_BUF_TAILPTR_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_PPR_BUF_TAILPTR_1", REG_MMIO, 0x07fb, 1, &mmIOMMU_MMIO_PPR_BUF_TAILPTR_1[0], sizeof(mmIOMMU_MMIO_PPR_BUF_TAILPTR_1)/sizeof(mmIOMMU_MMIO_PPR_BUF_TAILPTR_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_GA_BUF_HDPTR_0", REG_MMIO, 0x07fc, 1, &mmIOMMU_MMIO_GA_BUF_HDPTR_0[0], sizeof(mmIOMMU_MMIO_GA_BUF_HDPTR_0)/sizeof(mmIOMMU_MMIO_GA_BUF_HDPTR_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_GA_BUF_HDPTR_1", REG_MMIO, 0x07fd, 1, &mmIOMMU_MMIO_GA_BUF_HDPTR_1[0], sizeof(mmIOMMU_MMIO_GA_BUF_HDPTR_1)/sizeof(mmIOMMU_MMIO_GA_BUF_HDPTR_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_GA_BUF_TAILPTR_0", REG_MMIO, 0x07fe, 1, &mmIOMMU_MMIO_GA_BUF_TAILPTR_0[0], sizeof(mmIOMMU_MMIO_GA_BUF_TAILPTR_0)/sizeof(mmIOMMU_MMIO_GA_BUF_TAILPTR_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_GA_BUF_TAILPTR_1", REG_MMIO, 0x07ff, 1, &mmIOMMU_MMIO_GA_BUF_TAILPTR_1[0], sizeof(mmIOMMU_MMIO_GA_BUF_TAILPTR_1)/sizeof(mmIOMMU_MMIO_GA_BUF_TAILPTR_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_PPR_B_BUF_HDPTR_0", REG_MMIO, 0x0800, 1, &mmIOMMU_MMIO_PPR_B_BUF_HDPTR_0[0], sizeof(mmIOMMU_MMIO_PPR_B_BUF_HDPTR_0)/sizeof(mmIOMMU_MMIO_PPR_B_BUF_HDPTR_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_PPR_B_BUF_HDPTR_1", REG_MMIO, 0x0801, 1, &mmIOMMU_MMIO_PPR_B_BUF_HDPTR_1[0], sizeof(mmIOMMU_MMIO_PPR_B_BUF_HDPTR_1)/sizeof(mmIOMMU_MMIO_PPR_B_BUF_HDPTR_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_PPR_B_BUF_TAILPTR_0", REG_MMIO, 0x0802, 1, &mmIOMMU_MMIO_PPR_B_BUF_TAILPTR_0[0], sizeof(mmIOMMU_MMIO_PPR_B_BUF_TAILPTR_0)/sizeof(mmIOMMU_MMIO_PPR_B_BUF_TAILPTR_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_PPR_B_BUF_TAILPTR_1", REG_MMIO, 0x0803, 1, &mmIOMMU_MMIO_PPR_B_BUF_TAILPTR_1[0], sizeof(mmIOMMU_MMIO_PPR_B_BUF_TAILPTR_1)/sizeof(mmIOMMU_MMIO_PPR_B_BUF_TAILPTR_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_EVENT_B_BUF_HDPTR_0", REG_MMIO, 0x0808, 1, &mmIOMMU_MMIO_EVENT_B_BUF_HDPTR_0[0], sizeof(mmIOMMU_MMIO_EVENT_B_BUF_HDPTR_0)/sizeof(mmIOMMU_MMIO_EVENT_B_BUF_HDPTR_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_EVENT_B_BUF_HDPTR_1", REG_MMIO, 0x0809, 1, &mmIOMMU_MMIO_EVENT_B_BUF_HDPTR_1[0], sizeof(mmIOMMU_MMIO_EVENT_B_BUF_HDPTR_1)/sizeof(mmIOMMU_MMIO_EVENT_B_BUF_HDPTR_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_EVENT_B_BUF_TAILPTR_0", REG_MMIO, 0x080a, 1, &mmIOMMU_MMIO_EVENT_B_BUF_TAILPTR_0[0], sizeof(mmIOMMU_MMIO_EVENT_B_BUF_TAILPTR_0)/sizeof(mmIOMMU_MMIO_EVENT_B_BUF_TAILPTR_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_EVENT_B_BUF_TAILPTR_1", REG_MMIO, 0x080b, 1, &mmIOMMU_MMIO_EVENT_B_BUF_TAILPTR_1[0], sizeof(mmIOMMU_MMIO_EVENT_B_BUF_TAILPTR_1)/sizeof(mmIOMMU_MMIO_EVENT_B_BUF_TAILPTR_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_PPR_AUTORESP_0", REG_MMIO, 0x080c, 1, &mmIOMMU_MMIO_PPR_AUTORESP_0[0], sizeof(mmIOMMU_MMIO_PPR_AUTORESP_0)/sizeof(mmIOMMU_MMIO_PPR_AUTORESP_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_PPR_OVERFLOW_EARLY_0", REG_MMIO, 0x080e, 1, &mmIOMMU_MMIO_PPR_OVERFLOW_EARLY_0[0], sizeof(mmIOMMU_MMIO_PPR_OVERFLOW_EARLY_0)/sizeof(mmIOMMU_MMIO_PPR_OVERFLOW_EARLY_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0", REG_MMIO, 0x0810, 1, &mmIOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0[0], sizeof(mmIOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0)/sizeof(mmIOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_COUNTER_CONFIG_0", REG_MMIO, 0x02e0, 2, &mmIOMMU_MMIO_COUNTER_CONFIG_0[0], sizeof(mmIOMMU_MMIO_COUNTER_CONFIG_0)/sizeof(mmIOMMU_MMIO_COUNTER_CONFIG_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_COUNTER_CONFIG_1", REG_MMIO, 0x02e1, 2, &mmIOMMU_MMIO_COUNTER_CONFIG_1[0], sizeof(mmIOMMU_MMIO_COUNTER_CONFIG_1)/sizeof(mmIOMMU_MMIO_COUNTER_CONFIG_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_COUNTER_PASID_BANK_LOCK_0", REG_MMIO, 0x02e2, 2, &mmIOMMU_MMIO_COUNTER_PASID_BANK_LOCK_0[0], sizeof(mmIOMMU_MMIO_COUNTER_PASID_BANK_LOCK_0)/sizeof(mmIOMMU_MMIO_COUNTER_PASID_BANK_LOCK_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_COUNTER_PASID_BANK_LOCK_1", REG_MMIO, 0x02e3, 2, &mmIOMMU_MMIO_COUNTER_PASID_BANK_LOCK_1[0], sizeof(mmIOMMU_MMIO_COUNTER_PASID_BANK_LOCK_1)/sizeof(mmIOMMU_MMIO_COUNTER_PASID_BANK_LOCK_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_0", REG_MMIO, 0x02e4, 2, &mmIOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_0[0], sizeof(mmIOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_0)/sizeof(mmIOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_1", REG_MMIO, 0x02e5, 2, &mmIOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_1[0], sizeof(mmIOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_1)/sizeof(mmIOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_0", REG_MMIO, 0x02e6, 2, &mmIOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_0[0], sizeof(mmIOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_0)/sizeof(mmIOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_1", REG_MMIO, 0x02e7, 2, &mmIOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_1[0], sizeof(mmIOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_1)/sizeof(mmIOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_COUNTER_BANK_0_CNT_0_0", REG_MMIO, 0xf2e0, 2, &mmIOMMU_MMIO_COUNTER_BANK_0_CNT_0_0[0], sizeof(mmIOMMU_MMIO_COUNTER_BANK_0_CNT_0_0)/sizeof(mmIOMMU_MMIO_COUNTER_BANK_0_CNT_0_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_COUNTER_BANK_0_CNT_0_1", REG_MMIO, 0xf2e1, 2, &mmIOMMU_MMIO_COUNTER_BANK_0_CNT_0_1[0], sizeof(mmIOMMU_MMIO_COUNTER_BANK_0_CNT_0_1)/sizeof(mmIOMMU_MMIO_COUNTER_BANK_0_CNT_0_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0", REG_MMIO, 0xf2e2, 2, &mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0[0], sizeof(mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0)/sizeof(mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_1", REG_MMIO, 0xf2e3, 2, &mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_1[0], sizeof(mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_1)/sizeof(mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0", REG_MMIO, 0xf2e4, 2, &mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0[0], sizeof(mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0)/sizeof(mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1", REG_MMIO, 0xf2e5, 2, &mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1[0], sizeof(mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1)/sizeof(mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0", REG_MMIO, 0xf2e6, 2, &mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0[0], sizeof(mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0)/sizeof(mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1", REG_MMIO, 0xf2e7, 2, &mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1[0], sizeof(mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1)/sizeof(mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0", REG_MMIO, 0xf2e8, 2, &mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0[0], sizeof(mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0)/sizeof(mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1", REG_MMIO, 0xf2e9, 2, &mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1[0], sizeof(mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1)/sizeof(mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_0", REG_MMIO, 0xf2ea, 2, &mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_0[0], sizeof(mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_0)/sizeof(mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1", REG_MMIO, 0xf2eb, 2, &mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1[0], sizeof(mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1)/sizeof(mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_COUNTER_BANK_0_CNT_1_0", REG_MMIO, 0xf320, 2, &mmIOMMU_MMIO_COUNTER_BANK_0_CNT_1_0[0], sizeof(mmIOMMU_MMIO_COUNTER_BANK_0_CNT_1_0)/sizeof(mmIOMMU_MMIO_COUNTER_BANK_0_CNT_1_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_COUNTER_BANK_0_CNT_1_1", REG_MMIO, 0xf321, 2, &mmIOMMU_MMIO_COUNTER_BANK_0_CNT_1_1[0], sizeof(mmIOMMU_MMIO_COUNTER_BANK_0_CNT_1_1)/sizeof(mmIOMMU_MMIO_COUNTER_BANK_0_CNT_1_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0", REG_MMIO, 0xf322, 2, &mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0[0], sizeof(mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0)/sizeof(mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_1", REG_MMIO, 0xf323, 2, &mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_1[0], sizeof(mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_1)/sizeof(mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0", REG_MMIO, 0xf324, 2, &mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0[0], sizeof(mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0)/sizeof(mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1", REG_MMIO, 0xf325, 2, &mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1[0], sizeof(mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1)/sizeof(mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0", REG_MMIO, 0xf326, 2, &mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0[0], sizeof(mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0)/sizeof(mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1", REG_MMIO, 0xf327, 2, &mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1[0], sizeof(mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1)/sizeof(mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0", REG_MMIO, 0xf328, 2, &mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0[0], sizeof(mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0)/sizeof(mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1", REG_MMIO, 0xf329, 2, &mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1[0], sizeof(mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1)/sizeof(mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_0", REG_MMIO, 0xf32a, 2, &mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_0[0], sizeof(mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_0)/sizeof(mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1", REG_MMIO, 0xf32b, 2, &mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1[0], sizeof(mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1)/sizeof(mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_COUNTER_BANK_0_CNT_2_0", REG_MMIO, 0xf360, 2, &mmIOMMU_MMIO_COUNTER_BANK_0_CNT_2_0[0], sizeof(mmIOMMU_MMIO_COUNTER_BANK_0_CNT_2_0)/sizeof(mmIOMMU_MMIO_COUNTER_BANK_0_CNT_2_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_COUNTER_BANK_0_CNT_2_1", REG_MMIO, 0xf361, 2, &mmIOMMU_MMIO_COUNTER_BANK_0_CNT_2_1[0], sizeof(mmIOMMU_MMIO_COUNTER_BANK_0_CNT_2_1)/sizeof(mmIOMMU_MMIO_COUNTER_BANK_0_CNT_2_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0", REG_MMIO, 0xf362, 2, &mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0[0], sizeof(mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0)/sizeof(mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_1", REG_MMIO, 0xf363, 2, &mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_1[0], sizeof(mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_1)/sizeof(mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0", REG_MMIO, 0xf364, 2, &mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0[0], sizeof(mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0)/sizeof(mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1", REG_MMIO, 0xf365, 2, &mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1[0], sizeof(mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1)/sizeof(mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0", REG_MMIO, 0xf366, 2, &mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0[0], sizeof(mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0)/sizeof(mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1", REG_MMIO, 0xf367, 2, &mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1[0], sizeof(mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1)/sizeof(mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0", REG_MMIO, 0xf368, 2, &mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0[0], sizeof(mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0)/sizeof(mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1", REG_MMIO, 0xf369, 2, &mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1[0], sizeof(mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1)/sizeof(mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_0", REG_MMIO, 0xf36a, 2, &mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_0[0], sizeof(mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_0)/sizeof(mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1", REG_MMIO, 0xf36b, 2, &mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1[0], sizeof(mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1)/sizeof(mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_COUNTER_BANK_0_CNT_3_0", REG_MMIO, 0xf3a0, 2, &mmIOMMU_MMIO_COUNTER_BANK_0_CNT_3_0[0], sizeof(mmIOMMU_MMIO_COUNTER_BANK_0_CNT_3_0)/sizeof(mmIOMMU_MMIO_COUNTER_BANK_0_CNT_3_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_COUNTER_BANK_0_CNT_3_1", REG_MMIO, 0xf3a1, 2, &mmIOMMU_MMIO_COUNTER_BANK_0_CNT_3_1[0], sizeof(mmIOMMU_MMIO_COUNTER_BANK_0_CNT_3_1)/sizeof(mmIOMMU_MMIO_COUNTER_BANK_0_CNT_3_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0", REG_MMIO, 0xf3a2, 2, &mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0[0], sizeof(mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0)/sizeof(mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_1", REG_MMIO, 0xf3a3, 2, &mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_1[0], sizeof(mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_1)/sizeof(mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0", REG_MMIO, 0xf3a4, 2, &mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0[0], sizeof(mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0)/sizeof(mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1", REG_MMIO, 0xf3a5, 2, &mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1[0], sizeof(mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1)/sizeof(mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0", REG_MMIO, 0xf3a6, 2, &mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0[0], sizeof(mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0)/sizeof(mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1", REG_MMIO, 0xf3a7, 2, &mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1[0], sizeof(mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1)/sizeof(mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0", REG_MMIO, 0xf3a8, 2, &mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0[0], sizeof(mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0)/sizeof(mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1", REG_MMIO, 0xf3a9, 2, &mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1[0], sizeof(mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1)/sizeof(mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_0", REG_MMIO, 0xf3aa, 2, &mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_0[0], sizeof(mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_0)/sizeof(mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1", REG_MMIO, 0xf3ab, 2, &mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1[0], sizeof(mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1)/sizeof(mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_COUNTER_BANK_1_CNT_0_0", REG_MMIO, 0x0000, 3, &mmIOMMU_MMIO_COUNTER_BANK_1_CNT_0_0[0], sizeof(mmIOMMU_MMIO_COUNTER_BANK_1_CNT_0_0)/sizeof(mmIOMMU_MMIO_COUNTER_BANK_1_CNT_0_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_COUNTER_BANK_1_CNT_0_1", REG_MMIO, 0x0001, 3, &mmIOMMU_MMIO_COUNTER_BANK_1_CNT_0_1[0], sizeof(mmIOMMU_MMIO_COUNTER_BANK_1_CNT_0_1)/sizeof(mmIOMMU_MMIO_COUNTER_BANK_1_CNT_0_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0", REG_MMIO, 0x0002, 3, &mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0[0], sizeof(mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0)/sizeof(mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_1", REG_MMIO, 0x0003, 3, &mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_1[0], sizeof(mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_1)/sizeof(mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0", REG_MMIO, 0x0004, 3, &mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0[0], sizeof(mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0)/sizeof(mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1", REG_MMIO, 0x0005, 3, &mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1[0], sizeof(mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1)/sizeof(mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0", REG_MMIO, 0x0006, 3, &mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0[0], sizeof(mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0)/sizeof(mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1", REG_MMIO, 0x0007, 3, &mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1[0], sizeof(mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1)/sizeof(mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0", REG_MMIO, 0x0008, 3, &mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0[0], sizeof(mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0)/sizeof(mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1", REG_MMIO, 0x0009, 3, &mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1[0], sizeof(mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1)/sizeof(mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_0", REG_MMIO, 0x000a, 3, &mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_0[0], sizeof(mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_0)/sizeof(mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1", REG_MMIO, 0x000b, 3, &mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1[0], sizeof(mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1)/sizeof(mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_COUNTER_BANK_1_CNT_1_0", REG_MMIO, 0x0040, 3, &mmIOMMU_MMIO_COUNTER_BANK_1_CNT_1_0[0], sizeof(mmIOMMU_MMIO_COUNTER_BANK_1_CNT_1_0)/sizeof(mmIOMMU_MMIO_COUNTER_BANK_1_CNT_1_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_COUNTER_BANK_1_CNT_1_1", REG_MMIO, 0x0041, 3, &mmIOMMU_MMIO_COUNTER_BANK_1_CNT_1_1[0], sizeof(mmIOMMU_MMIO_COUNTER_BANK_1_CNT_1_1)/sizeof(mmIOMMU_MMIO_COUNTER_BANK_1_CNT_1_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0", REG_MMIO, 0x0042, 3, &mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0[0], sizeof(mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0)/sizeof(mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_1", REG_MMIO, 0x0043, 3, &mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_1[0], sizeof(mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_1)/sizeof(mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0", REG_MMIO, 0x0044, 3, &mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0[0], sizeof(mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0)/sizeof(mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1", REG_MMIO, 0x0045, 3, &mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1[0], sizeof(mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1)/sizeof(mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0", REG_MMIO, 0x0046, 3, &mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0[0], sizeof(mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0)/sizeof(mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1", REG_MMIO, 0x0047, 3, &mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1[0], sizeof(mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1)/sizeof(mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0", REG_MMIO, 0x0048, 3, &mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0[0], sizeof(mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0)/sizeof(mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1", REG_MMIO, 0x0049, 3, &mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1[0], sizeof(mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1)/sizeof(mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_0", REG_MMIO, 0x004a, 3, &mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_0[0], sizeof(mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_0)/sizeof(mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1", REG_MMIO, 0x004b, 3, &mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1[0], sizeof(mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1)/sizeof(mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_COUNTER_BANK_1_CNT_2_0", REG_MMIO, 0x0080, 3, &mmIOMMU_MMIO_COUNTER_BANK_1_CNT_2_0[0], sizeof(mmIOMMU_MMIO_COUNTER_BANK_1_CNT_2_0)/sizeof(mmIOMMU_MMIO_COUNTER_BANK_1_CNT_2_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_COUNTER_BANK_1_CNT_2_1", REG_MMIO, 0x0081, 3, &mmIOMMU_MMIO_COUNTER_BANK_1_CNT_2_1[0], sizeof(mmIOMMU_MMIO_COUNTER_BANK_1_CNT_2_1)/sizeof(mmIOMMU_MMIO_COUNTER_BANK_1_CNT_2_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0", REG_MMIO, 0x0082, 3, &mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0[0], sizeof(mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0)/sizeof(mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_1", REG_MMIO, 0x0083, 3, &mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_1[0], sizeof(mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_1)/sizeof(mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0", REG_MMIO, 0x0084, 3, &mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0[0], sizeof(mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0)/sizeof(mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1", REG_MMIO, 0x0085, 3, &mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1[0], sizeof(mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1)/sizeof(mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0", REG_MMIO, 0x0086, 3, &mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0[0], sizeof(mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0)/sizeof(mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1", REG_MMIO, 0x0087, 3, &mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1[0], sizeof(mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1)/sizeof(mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0", REG_MMIO, 0x0088, 3, &mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0[0], sizeof(mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0)/sizeof(mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1", REG_MMIO, 0x0089, 3, &mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1[0], sizeof(mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1)/sizeof(mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_0", REG_MMIO, 0x008a, 3, &mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_0[0], sizeof(mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_0)/sizeof(mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1", REG_MMIO, 0x008b, 3, &mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1[0], sizeof(mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1)/sizeof(mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_COUNTER_BANK_1_CNT_3_0", REG_MMIO, 0x00c0, 3, &mmIOMMU_MMIO_COUNTER_BANK_1_CNT_3_0[0], sizeof(mmIOMMU_MMIO_COUNTER_BANK_1_CNT_3_0)/sizeof(mmIOMMU_MMIO_COUNTER_BANK_1_CNT_3_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_COUNTER_BANK_1_CNT_3_1", REG_MMIO, 0x00c1, 3, &mmIOMMU_MMIO_COUNTER_BANK_1_CNT_3_1[0], sizeof(mmIOMMU_MMIO_COUNTER_BANK_1_CNT_3_1)/sizeof(mmIOMMU_MMIO_COUNTER_BANK_1_CNT_3_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0", REG_MMIO, 0x00c2, 3, &mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0[0], sizeof(mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0)/sizeof(mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_1", REG_MMIO, 0x00c3, 3, &mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_1[0], sizeof(mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_1)/sizeof(mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0", REG_MMIO, 0x00c4, 3, &mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0[0], sizeof(mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0)/sizeof(mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1", REG_MMIO, 0x00c5, 3, &mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1[0], sizeof(mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1)/sizeof(mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0", REG_MMIO, 0x00c6, 3, &mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0[0], sizeof(mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0)/sizeof(mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1", REG_MMIO, 0x00c7, 3, &mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1[0], sizeof(mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1)/sizeof(mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0", REG_MMIO, 0x00c8, 3, &mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0[0], sizeof(mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0)/sizeof(mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1", REG_MMIO, 0x00c9, 3, &mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1[0], sizeof(mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1)/sizeof(mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1[0]), 0, 0 }, + { "mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_0", REG_MMIO, 0x00ca, 3, &mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_0[0], sizeof(mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_0)/sizeof(mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_0[0]), 0, 0 }, + { "mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1", REG_MMIO, 0x00cb, 3, &mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1[0], sizeof(mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1)/sizeof(mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1[0]), 0, 0 }, + { "mmMM_INDEX", REG_MMIO, 0x0000, 0, &mmMM_INDEX[0], sizeof(mmMM_INDEX)/sizeof(mmMM_INDEX[0]), 0, 0 }, + { "mmMM_DATA", REG_MMIO, 0x0001, 0, &mmMM_DATA[0], sizeof(mmMM_DATA)/sizeof(mmMM_DATA[0]), 0, 0 }, + { "mmMM_INDEX_HI", REG_MMIO, 0x0006, 0, &mmMM_INDEX_HI[0], sizeof(mmMM_INDEX_HI)/sizeof(mmMM_INDEX_HI[0]), 0, 0 }, + { "mmSYSHUB_INDEX_OVLP", REG_MMIO, 0x0008, 0, &mmSYSHUB_INDEX_OVLP[0], sizeof(mmSYSHUB_INDEX_OVLP)/sizeof(mmSYSHUB_INDEX_OVLP[0]), 0, 0 }, + { "mmSYSHUB_DATA_OVLP", REG_MMIO, 0x0009, 0, &mmSYSHUB_DATA_OVLP[0], sizeof(mmSYSHUB_DATA_OVLP)/sizeof(mmSYSHUB_DATA_OVLP[0]), 0, 0 }, + { "mmPCIE_INDEX", REG_MMIO, 0x000c, 0, &mmPCIE_INDEX[0], sizeof(mmPCIE_INDEX)/sizeof(mmPCIE_INDEX[0]), 0, 0 }, + { "mmPCIE_DATA", REG_MMIO, 0x000d, 0, &mmPCIE_DATA[0], sizeof(mmPCIE_DATA)/sizeof(mmPCIE_DATA[0]), 0, 0 }, + { "mmPCIE_INDEX2", REG_MMIO, 0x000e, 0, &mmPCIE_INDEX2[0], sizeof(mmPCIE_INDEX2)/sizeof(mmPCIE_INDEX2[0]), 0, 0 }, + { "mmPCIE_DATA2", REG_MMIO, 0x000f, 0, &mmPCIE_DATA2[0], sizeof(mmPCIE_DATA2)/sizeof(mmPCIE_DATA2[0]), 0, 0 }, + { "mmSBIOS_SCRATCH_0", REG_MMIO, 0x0034, 1, &mmSBIOS_SCRATCH_0[0], sizeof(mmSBIOS_SCRATCH_0)/sizeof(mmSBIOS_SCRATCH_0[0]), 0, 0 }, + { "mmSBIOS_SCRATCH_1", REG_MMIO, 0x0035, 1, &mmSBIOS_SCRATCH_1[0], sizeof(mmSBIOS_SCRATCH_1)/sizeof(mmSBIOS_SCRATCH_1[0]), 0, 0 }, + { "mmSBIOS_SCRATCH_2", REG_MMIO, 0x0036, 1, &mmSBIOS_SCRATCH_2[0], sizeof(mmSBIOS_SCRATCH_2)/sizeof(mmSBIOS_SCRATCH_2[0]), 0, 0 }, + { "mmSBIOS_SCRATCH_3", REG_MMIO, 0x0037, 1, &mmSBIOS_SCRATCH_3[0], sizeof(mmSBIOS_SCRATCH_3)/sizeof(mmSBIOS_SCRATCH_3[0]), 0, 0 }, + { "mmBIOS_SCRATCH_0", REG_MMIO, 0x0038, 1, &mmBIOS_SCRATCH_0[0], sizeof(mmBIOS_SCRATCH_0)/sizeof(mmBIOS_SCRATCH_0[0]), 0, 0 }, + { "mmBIOS_SCRATCH_1", REG_MMIO, 0x0039, 1, &mmBIOS_SCRATCH_1[0], sizeof(mmBIOS_SCRATCH_1)/sizeof(mmBIOS_SCRATCH_1[0]), 0, 0 }, + { "mmBIOS_SCRATCH_2", REG_MMIO, 0x003a, 1, &mmBIOS_SCRATCH_2[0], sizeof(mmBIOS_SCRATCH_2)/sizeof(mmBIOS_SCRATCH_2[0]), 0, 0 }, + { "mmBIOS_SCRATCH_3", REG_MMIO, 0x003b, 1, &mmBIOS_SCRATCH_3[0], sizeof(mmBIOS_SCRATCH_3)/sizeof(mmBIOS_SCRATCH_3[0]), 0, 0 }, + { "mmBIOS_SCRATCH_4", REG_MMIO, 0x003c, 1, &mmBIOS_SCRATCH_4[0], sizeof(mmBIOS_SCRATCH_4)/sizeof(mmBIOS_SCRATCH_4[0]), 0, 0 }, + { "mmBIOS_SCRATCH_5", REG_MMIO, 0x003d, 1, &mmBIOS_SCRATCH_5[0], sizeof(mmBIOS_SCRATCH_5)/sizeof(mmBIOS_SCRATCH_5[0]), 0, 0 }, + { "mmBIOS_SCRATCH_6", REG_MMIO, 0x003e, 1, &mmBIOS_SCRATCH_6[0], sizeof(mmBIOS_SCRATCH_6)/sizeof(mmBIOS_SCRATCH_6[0]), 0, 0 }, + { "mmBIOS_SCRATCH_7", REG_MMIO, 0x003f, 1, &mmBIOS_SCRATCH_7[0], sizeof(mmBIOS_SCRATCH_7)/sizeof(mmBIOS_SCRATCH_7[0]), 0, 0 }, + { "mmBIOS_SCRATCH_8", REG_MMIO, 0x0040, 1, &mmBIOS_SCRATCH_8[0], sizeof(mmBIOS_SCRATCH_8)/sizeof(mmBIOS_SCRATCH_8[0]), 0, 0 }, + { "mmBIOS_SCRATCH_9", REG_MMIO, 0x0041, 1, &mmBIOS_SCRATCH_9[0], sizeof(mmBIOS_SCRATCH_9)/sizeof(mmBIOS_SCRATCH_9[0]), 0, 0 }, + { "mmBIOS_SCRATCH_10", REG_MMIO, 0x0042, 1, &mmBIOS_SCRATCH_10[0], sizeof(mmBIOS_SCRATCH_10)/sizeof(mmBIOS_SCRATCH_10[0]), 0, 0 }, + { "mmBIOS_SCRATCH_11", REG_MMIO, 0x0043, 1, &mmBIOS_SCRATCH_11[0], sizeof(mmBIOS_SCRATCH_11)/sizeof(mmBIOS_SCRATCH_11[0]), 0, 0 }, + { "mmBIOS_SCRATCH_12", REG_MMIO, 0x0044, 1, &mmBIOS_SCRATCH_12[0], sizeof(mmBIOS_SCRATCH_12)/sizeof(mmBIOS_SCRATCH_12[0]), 0, 0 }, + { "mmBIOS_SCRATCH_13", REG_MMIO, 0x0045, 1, &mmBIOS_SCRATCH_13[0], sizeof(mmBIOS_SCRATCH_13)/sizeof(mmBIOS_SCRATCH_13[0]), 0, 0 }, + { "mmBIOS_SCRATCH_14", REG_MMIO, 0x0046, 1, &mmBIOS_SCRATCH_14[0], sizeof(mmBIOS_SCRATCH_14)/sizeof(mmBIOS_SCRATCH_14[0]), 0, 0 }, + { "mmBIOS_SCRATCH_15", REG_MMIO, 0x0047, 1, &mmBIOS_SCRATCH_15[0], sizeof(mmBIOS_SCRATCH_15)/sizeof(mmBIOS_SCRATCH_15[0]), 0, 0 }, + { "mmBIF_RLC_INTR_CNTL", REG_MMIO, 0x004c, 1, &mmBIF_RLC_INTR_CNTL[0], sizeof(mmBIF_RLC_INTR_CNTL)/sizeof(mmBIF_RLC_INTR_CNTL[0]), 0, 0 }, + { "mmBIF_VCE_INTR_CNTL", REG_MMIO, 0x004d, 1, &mmBIF_VCE_INTR_CNTL[0], sizeof(mmBIF_VCE_INTR_CNTL)/sizeof(mmBIF_VCE_INTR_CNTL[0]), 0, 0 }, + { "mmBIF_UVD_INTR_CNTL", REG_MMIO, 0x004e, 1, &mmBIF_UVD_INTR_CNTL[0], sizeof(mmBIF_UVD_INTR_CNTL)/sizeof(mmBIF_UVD_INTR_CNTL[0]), 0, 0 }, + { "mmGFX_MMIOREG_CAM_ADDR0", REG_MMIO, 0x006c, 1, &mmGFX_MMIOREG_CAM_ADDR0[0], sizeof(mmGFX_MMIOREG_CAM_ADDR0)/sizeof(mmGFX_MMIOREG_CAM_ADDR0[0]), 0, 0 }, + { "mmGFX_MMIOREG_CAM_REMAP_ADDR0", REG_MMIO, 0x006d, 1, &mmGFX_MMIOREG_CAM_REMAP_ADDR0[0], sizeof(mmGFX_MMIOREG_CAM_REMAP_ADDR0)/sizeof(mmGFX_MMIOREG_CAM_REMAP_ADDR0[0]), 0, 0 }, + { "mmGFX_MMIOREG_CAM_ADDR1", REG_MMIO, 0x006e, 1, &mmGFX_MMIOREG_CAM_ADDR1[0], sizeof(mmGFX_MMIOREG_CAM_ADDR1)/sizeof(mmGFX_MMIOREG_CAM_ADDR1[0]), 0, 0 }, + { "mmGFX_MMIOREG_CAM_REMAP_ADDR1", REG_MMIO, 0x006f, 1, &mmGFX_MMIOREG_CAM_REMAP_ADDR1[0], sizeof(mmGFX_MMIOREG_CAM_REMAP_ADDR1)/sizeof(mmGFX_MMIOREG_CAM_REMAP_ADDR1[0]), 0, 0 }, + { "mmGFX_MMIOREG_CAM_ADDR2", REG_MMIO, 0x0070, 1, &mmGFX_MMIOREG_CAM_ADDR2[0], sizeof(mmGFX_MMIOREG_CAM_ADDR2)/sizeof(mmGFX_MMIOREG_CAM_ADDR2[0]), 0, 0 }, + { "mmGFX_MMIOREG_CAM_REMAP_ADDR2", REG_MMIO, 0x0071, 1, &mmGFX_MMIOREG_CAM_REMAP_ADDR2[0], sizeof(mmGFX_MMIOREG_CAM_REMAP_ADDR2)/sizeof(mmGFX_MMIOREG_CAM_REMAP_ADDR2[0]), 0, 0 }, + { "mmGFX_MMIOREG_CAM_ADDR3", REG_MMIO, 0x0072, 1, &mmGFX_MMIOREG_CAM_ADDR3[0], sizeof(mmGFX_MMIOREG_CAM_ADDR3)/sizeof(mmGFX_MMIOREG_CAM_ADDR3[0]), 0, 0 }, + { "mmGFX_MMIOREG_CAM_REMAP_ADDR3", REG_MMIO, 0x0073, 1, &mmGFX_MMIOREG_CAM_REMAP_ADDR3[0], sizeof(mmGFX_MMIOREG_CAM_REMAP_ADDR3)/sizeof(mmGFX_MMIOREG_CAM_REMAP_ADDR3[0]), 0, 0 }, + { "mmGFX_MMIOREG_CAM_ADDR4", REG_MMIO, 0x0074, 1, &mmGFX_MMIOREG_CAM_ADDR4[0], sizeof(mmGFX_MMIOREG_CAM_ADDR4)/sizeof(mmGFX_MMIOREG_CAM_ADDR4[0]), 0, 0 }, + { "mmGFX_MMIOREG_CAM_REMAP_ADDR4", REG_MMIO, 0x0075, 1, &mmGFX_MMIOREG_CAM_REMAP_ADDR4[0], sizeof(mmGFX_MMIOREG_CAM_REMAP_ADDR4)/sizeof(mmGFX_MMIOREG_CAM_REMAP_ADDR4[0]), 0, 0 }, + { "mmGFX_MMIOREG_CAM_ADDR5", REG_MMIO, 0x0076, 1, &mmGFX_MMIOREG_CAM_ADDR5[0], sizeof(mmGFX_MMIOREG_CAM_ADDR5)/sizeof(mmGFX_MMIOREG_CAM_ADDR5[0]), 0, 0 }, + { "mmGFX_MMIOREG_CAM_REMAP_ADDR5", REG_MMIO, 0x0077, 1, &mmGFX_MMIOREG_CAM_REMAP_ADDR5[0], sizeof(mmGFX_MMIOREG_CAM_REMAP_ADDR5)/sizeof(mmGFX_MMIOREG_CAM_REMAP_ADDR5[0]), 0, 0 }, + { "mmGFX_MMIOREG_CAM_ADDR6", REG_MMIO, 0x0078, 1, &mmGFX_MMIOREG_CAM_ADDR6[0], sizeof(mmGFX_MMIOREG_CAM_ADDR6)/sizeof(mmGFX_MMIOREG_CAM_ADDR6[0]), 0, 0 }, + { "mmGFX_MMIOREG_CAM_REMAP_ADDR6", REG_MMIO, 0x0079, 1, &mmGFX_MMIOREG_CAM_REMAP_ADDR6[0], sizeof(mmGFX_MMIOREG_CAM_REMAP_ADDR6)/sizeof(mmGFX_MMIOREG_CAM_REMAP_ADDR6[0]), 0, 0 }, + { "mmGFX_MMIOREG_CAM_ADDR7", REG_MMIO, 0x007a, 1, &mmGFX_MMIOREG_CAM_ADDR7[0], sizeof(mmGFX_MMIOREG_CAM_ADDR7)/sizeof(mmGFX_MMIOREG_CAM_ADDR7[0]), 0, 0 }, + { "mmGFX_MMIOREG_CAM_REMAP_ADDR7", REG_MMIO, 0x007b, 1, &mmGFX_MMIOREG_CAM_REMAP_ADDR7[0], sizeof(mmGFX_MMIOREG_CAM_REMAP_ADDR7)/sizeof(mmGFX_MMIOREG_CAM_REMAP_ADDR7[0]), 0, 0 }, + { "mmGFX_MMIOREG_CAM_CNTL", REG_MMIO, 0x007c, 1, &mmGFX_MMIOREG_CAM_CNTL[0], sizeof(mmGFX_MMIOREG_CAM_CNTL)/sizeof(mmGFX_MMIOREG_CAM_CNTL[0]), 0, 0 }, + { "mmGFX_MMIOREG_CAM_ZERO_CPL", REG_MMIO, 0x007d, 1, &mmGFX_MMIOREG_CAM_ZERO_CPL[0], sizeof(mmGFX_MMIOREG_CAM_ZERO_CPL)/sizeof(mmGFX_MMIOREG_CAM_ZERO_CPL[0]), 0, 0 }, + { "mmGFX_MMIOREG_CAM_ONE_CPL", REG_MMIO, 0x007e, 1, &mmGFX_MMIOREG_CAM_ONE_CPL[0], sizeof(mmGFX_MMIOREG_CAM_ONE_CPL)/sizeof(mmGFX_MMIOREG_CAM_ONE_CPL[0]), 0, 0 }, + { "mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL", REG_MMIO, 0x007f, 1, &mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL[0], sizeof(mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL)/sizeof(mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL[0]), 0, 0 }, + { "mmSYSHUB_INDEX", REG_MMIO, 0x0008, 0, &mmSYSHUB_INDEX[0], sizeof(mmSYSHUB_INDEX)/sizeof(mmSYSHUB_INDEX[0]), 0, 0 }, + { "mmSYSHUB_DATA", REG_MMIO, 0x0009, 0, &mmSYSHUB_DATA[0], sizeof(mmSYSHUB_DATA)/sizeof(mmSYSHUB_DATA[0]), 0, 0 }, + { "mmRCC_DEV0_EPF0_STRAP0", REG_MMIO, 0x000f, 2, &mmRCC_DEV0_EPF0_STRAP0[0], sizeof(mmRCC_DEV0_EPF0_STRAP0)/sizeof(mmRCC_DEV0_EPF0_STRAP0[0]), 0, 0 }, + { "mmEP_PCIE_SCRATCH", REG_MMIO, 0x0023, 2, &mmEP_PCIE_SCRATCH[0], sizeof(mmEP_PCIE_SCRATCH)/sizeof(mmEP_PCIE_SCRATCH[0]), 0, 0 }, + { "mmEP_PCIE_CNTL", REG_MMIO, 0x0025, 2, &mmEP_PCIE_CNTL[0], sizeof(mmEP_PCIE_CNTL)/sizeof(mmEP_PCIE_CNTL[0]), 0, 0 }, + { "mmEP_PCIE_INT_CNTL", REG_MMIO, 0x0026, 2, &mmEP_PCIE_INT_CNTL[0], sizeof(mmEP_PCIE_INT_CNTL)/sizeof(mmEP_PCIE_INT_CNTL[0]), 0, 0 }, + { "mmEP_PCIE_INT_STATUS", REG_MMIO, 0x0027, 2, &mmEP_PCIE_INT_STATUS[0], sizeof(mmEP_PCIE_INT_STATUS)/sizeof(mmEP_PCIE_INT_STATUS[0]), 0, 0 }, + { "mmEP_PCIE_RX_CNTL2", REG_MMIO, 0x0028, 2, &mmEP_PCIE_RX_CNTL2[0], sizeof(mmEP_PCIE_RX_CNTL2)/sizeof(mmEP_PCIE_RX_CNTL2[0]), 0, 0 }, + { "mmEP_PCIE_BUS_CNTL", REG_MMIO, 0x0029, 2, &mmEP_PCIE_BUS_CNTL[0], sizeof(mmEP_PCIE_BUS_CNTL)/sizeof(mmEP_PCIE_BUS_CNTL[0]), 0, 0 }, + { "mmEP_PCIE_CFG_CNTL", REG_MMIO, 0x002a, 2, &mmEP_PCIE_CFG_CNTL[0], sizeof(mmEP_PCIE_CFG_CNTL)/sizeof(mmEP_PCIE_CFG_CNTL[0]), 0, 0 }, + { "mmEP_PCIE_TX_LTR_CNTL", REG_MMIO, 0x002c, 2, &mmEP_PCIE_TX_LTR_CNTL[0], sizeof(mmEP_PCIE_TX_LTR_CNTL)/sizeof(mmEP_PCIE_TX_LTR_CNTL[0]), 0, 0 }, + { "mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0", REG_MMIO, 0x002d, 2, &mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0[0], sizeof(mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0)/sizeof(mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0[0]), 0, 0 }, + { "mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1", REG_MMIO, 0x002d, 2, &mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1[0], sizeof(mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1)/sizeof(mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1[0]), 0, 0 }, + { "mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2", REG_MMIO, 0x002d, 2, &mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2[0], sizeof(mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2)/sizeof(mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2[0]), 0, 0 }, + { "mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3", REG_MMIO, 0x002d, 2, &mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3[0], sizeof(mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3)/sizeof(mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3[0]), 0, 0 }, + { "mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4", REG_MMIO, 0x002e, 2, &mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4[0], sizeof(mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4)/sizeof(mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4[0]), 0, 0 }, + { "mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5", REG_MMIO, 0x002e, 2, &mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5[0], sizeof(mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5)/sizeof(mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5[0]), 0, 0 }, + { "mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6", REG_MMIO, 0x002e, 2, &mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6[0], sizeof(mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6)/sizeof(mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6[0]), 0, 0 }, + { "mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7", REG_MMIO, 0x002e, 2, &mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7[0], sizeof(mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7)/sizeof(mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7[0]), 0, 0 }, + { "mmEP_PCIE_F0_DPA_CAP", REG_MMIO, 0x0032, 2, &mmEP_PCIE_F0_DPA_CAP[0], sizeof(mmEP_PCIE_F0_DPA_CAP)/sizeof(mmEP_PCIE_F0_DPA_CAP[0]), 0, 0 }, + { "mmEP_PCIE_F0_DPA_LATENCY_INDICATOR", REG_MMIO, 0x0033, 2, &mmEP_PCIE_F0_DPA_LATENCY_INDICATOR[0], sizeof(mmEP_PCIE_F0_DPA_LATENCY_INDICATOR)/sizeof(mmEP_PCIE_F0_DPA_LATENCY_INDICATOR[0]), 0, 0 }, + { "mmEP_PCIE_F0_DPA_CNTL", REG_MMIO, 0x0033, 2, &mmEP_PCIE_F0_DPA_CNTL[0], sizeof(mmEP_PCIE_F0_DPA_CNTL)/sizeof(mmEP_PCIE_F0_DPA_CNTL[0]), 0, 0 }, + { "mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0", REG_MMIO, 0x0033, 2, &mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0[0], sizeof(mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0)/sizeof(mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0[0]), 0, 0 }, + { "mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1", REG_MMIO, 0x0034, 2, &mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1[0], sizeof(mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1)/sizeof(mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1[0]), 0, 0 }, + { "mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2", REG_MMIO, 0x0034, 2, &mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2[0], sizeof(mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2)/sizeof(mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2[0]), 0, 0 }, + { "mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3", REG_MMIO, 0x0034, 2, &mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3[0], sizeof(mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3)/sizeof(mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3[0]), 0, 0 }, + { "mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4", REG_MMIO, 0x0034, 2, &mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4[0], sizeof(mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4)/sizeof(mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4[0]), 0, 0 }, + { "mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5", REG_MMIO, 0x0035, 2, &mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5[0], sizeof(mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5)/sizeof(mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5[0]), 0, 0 }, + { "mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6", REG_MMIO, 0x0035, 2, &mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6[0], sizeof(mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6)/sizeof(mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6[0]), 0, 0 }, + { "mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7", REG_MMIO, 0x0035, 2, &mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7[0], sizeof(mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7)/sizeof(mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7[0]), 0, 0 }, + { "mmEP_PCIE_PME_CONTROL", REG_MMIO, 0x0035, 2, &mmEP_PCIE_PME_CONTROL[0], sizeof(mmEP_PCIE_PME_CONTROL)/sizeof(mmEP_PCIE_PME_CONTROL[0]), 0, 0 }, + { "mmEP_PCIEP_RESERVED", REG_MMIO, 0x0036, 2, &mmEP_PCIEP_RESERVED[0], sizeof(mmEP_PCIEP_RESERVED)/sizeof(mmEP_PCIEP_RESERVED[0]), 0, 0 }, + { "mmEP_PCIE_TX_CNTL", REG_MMIO, 0x0038, 2, &mmEP_PCIE_TX_CNTL[0], sizeof(mmEP_PCIE_TX_CNTL)/sizeof(mmEP_PCIE_TX_CNTL[0]), 0, 0 }, + { "mmEP_PCIE_TX_REQUESTER_ID", REG_MMIO, 0x0039, 2, &mmEP_PCIE_TX_REQUESTER_ID[0], sizeof(mmEP_PCIE_TX_REQUESTER_ID)/sizeof(mmEP_PCIE_TX_REQUESTER_ID[0]), 0, 0 }, + { "mmEP_PCIE_ERR_CNTL", REG_MMIO, 0x003a, 2, &mmEP_PCIE_ERR_CNTL[0], sizeof(mmEP_PCIE_ERR_CNTL)/sizeof(mmEP_PCIE_ERR_CNTL[0]), 0, 0 }, + { "mmEP_PCIE_RX_CNTL", REG_MMIO, 0x003b, 2, &mmEP_PCIE_RX_CNTL[0], sizeof(mmEP_PCIE_RX_CNTL)/sizeof(mmEP_PCIE_RX_CNTL[0]), 0, 0 }, + { "mmEP_PCIE_LC_SPEED_CNTL", REG_MMIO, 0x003c, 2, &mmEP_PCIE_LC_SPEED_CNTL[0], sizeof(mmEP_PCIE_LC_SPEED_CNTL)/sizeof(mmEP_PCIE_LC_SPEED_CNTL[0]), 0, 0 }, + { "mmDN_PCIE_RESERVED", REG_MMIO, 0x0040, 2, &mmDN_PCIE_RESERVED[0], sizeof(mmDN_PCIE_RESERVED)/sizeof(mmDN_PCIE_RESERVED[0]), 0, 0 }, + { "mmDN_PCIE_SCRATCH", REG_MMIO, 0x0041, 2, &mmDN_PCIE_SCRATCH[0], sizeof(mmDN_PCIE_SCRATCH)/sizeof(mmDN_PCIE_SCRATCH[0]), 0, 0 }, + { "mmDN_PCIE_CNTL", REG_MMIO, 0x0043, 2, &mmDN_PCIE_CNTL[0], sizeof(mmDN_PCIE_CNTL)/sizeof(mmDN_PCIE_CNTL[0]), 0, 0 }, + { "mmDN_PCIE_CONFIG_CNTL", REG_MMIO, 0x0044, 2, &mmDN_PCIE_CONFIG_CNTL[0], sizeof(mmDN_PCIE_CONFIG_CNTL)/sizeof(mmDN_PCIE_CONFIG_CNTL[0]), 0, 0 }, + { "mmDN_PCIE_RX_CNTL2", REG_MMIO, 0x0045, 2, &mmDN_PCIE_RX_CNTL2[0], sizeof(mmDN_PCIE_RX_CNTL2)/sizeof(mmDN_PCIE_RX_CNTL2[0]), 0, 0 }, + { "mmDN_PCIE_BUS_CNTL", REG_MMIO, 0x0046, 2, &mmDN_PCIE_BUS_CNTL[0], sizeof(mmDN_PCIE_BUS_CNTL)/sizeof(mmDN_PCIE_BUS_CNTL[0]), 0, 0 }, + { "mmDN_PCIE_CFG_CNTL", REG_MMIO, 0x0047, 2, &mmDN_PCIE_CFG_CNTL[0], sizeof(mmDN_PCIE_CFG_CNTL)/sizeof(mmDN_PCIE_CFG_CNTL[0]), 0, 0 }, + { "mmPCIE_ERR_CNTL", REG_MMIO, 0x004f, 2, &mmPCIE_ERR_CNTL[0], sizeof(mmPCIE_ERR_CNTL)/sizeof(mmPCIE_ERR_CNTL[0]), 0, 0 }, + { "mmPCIE_RX_CNTL", REG_MMIO, 0x0050, 2, &mmPCIE_RX_CNTL[0], sizeof(mmPCIE_RX_CNTL)/sizeof(mmPCIE_RX_CNTL[0]), 0, 0 }, + { "mmPCIE_LC_SPEED_CNTL", REG_MMIO, 0x0051, 2, &mmPCIE_LC_SPEED_CNTL[0], sizeof(mmPCIE_LC_SPEED_CNTL)/sizeof(mmPCIE_LC_SPEED_CNTL[0]), 0, 0 }, + { "mmPCIE_LC_CNTL2", REG_MMIO, 0x0052, 2, &mmPCIE_LC_CNTL2[0], sizeof(mmPCIE_LC_CNTL2)/sizeof(mmPCIE_LC_CNTL2[0]), 0, 0 }, + { "mmPCIEP_STRAP_MISC", REG_MMIO, 0x0053, 2, &mmPCIEP_STRAP_MISC[0], sizeof(mmPCIEP_STRAP_MISC)/sizeof(mmPCIEP_STRAP_MISC[0]), 0, 0 }, + { "mmLTR_MSG_INFO_FROM_EP", REG_MMIO, 0x0054, 2, &mmLTR_MSG_INFO_FROM_EP[0], sizeof(mmLTR_MSG_INFO_FROM_EP)/sizeof(mmLTR_MSG_INFO_FROM_EP[0]), 0, 0 }, + { "mmRCC_ERR_LOG", REG_MMIO, 0x0085, 2, &mmRCC_ERR_LOG[0], sizeof(mmRCC_ERR_LOG)/sizeof(mmRCC_ERR_LOG[0]), 0, 0 }, + { "mmRCC_DOORBELL_APER_EN", REG_MMIO, 0x00c0, 2, &mmRCC_DOORBELL_APER_EN[0], sizeof(mmRCC_DOORBELL_APER_EN)/sizeof(mmRCC_DOORBELL_APER_EN[0]), 0, 0 }, + { "mmRCC_CONFIG_MEMSIZE", REG_MMIO, 0x00c3, 2, &mmRCC_CONFIG_MEMSIZE[0], sizeof(mmRCC_CONFIG_MEMSIZE)/sizeof(mmRCC_CONFIG_MEMSIZE[0]), 0, 0 }, + { "mmRCC_CONFIG_RESERVED", REG_MMIO, 0x00c4, 2, &mmRCC_CONFIG_RESERVED[0], sizeof(mmRCC_CONFIG_RESERVED)/sizeof(mmRCC_CONFIG_RESERVED[0]), 0, 0 }, + { "mmRCC_IOV_FUNC_IDENTIFIER", REG_MMIO, 0x00c5, 2, &mmRCC_IOV_FUNC_IDENTIFIER[0], sizeof(mmRCC_IOV_FUNC_IDENTIFIER)/sizeof(mmRCC_IOV_FUNC_IDENTIFIER[0]), 0, 0 }, + { "mmRCC_ERR_INT_CNTL", REG_MMIO, 0x0086, 2, &mmRCC_ERR_INT_CNTL[0], sizeof(mmRCC_ERR_INT_CNTL)/sizeof(mmRCC_ERR_INT_CNTL[0]), 0, 0 }, + { "mmRCC_BACO_CNTL_MISC", REG_MMIO, 0x0087, 2, &mmRCC_BACO_CNTL_MISC[0], sizeof(mmRCC_BACO_CNTL_MISC)/sizeof(mmRCC_BACO_CNTL_MISC[0]), 0, 0 }, + { "mmRCC_RESET_EN", REG_MMIO, 0x0088, 2, &mmRCC_RESET_EN[0], sizeof(mmRCC_RESET_EN)/sizeof(mmRCC_RESET_EN[0]), 0, 0 }, + { "mmRCC_VDM_SUPPORT", REG_MMIO, 0x0089, 2, &mmRCC_VDM_SUPPORT[0], sizeof(mmRCC_VDM_SUPPORT)/sizeof(mmRCC_VDM_SUPPORT[0]), 0, 0 }, + { "mmRCC_PEER_REG_RANGE0", REG_MMIO, 0x00be, 2, &mmRCC_PEER_REG_RANGE0[0], sizeof(mmRCC_PEER_REG_RANGE0)/sizeof(mmRCC_PEER_REG_RANGE0[0]), 0, 0 }, + { "mmRCC_PEER_REG_RANGE1", REG_MMIO, 0x00bf, 2, &mmRCC_PEER_REG_RANGE1[0], sizeof(mmRCC_PEER_REG_RANGE1)/sizeof(mmRCC_PEER_REG_RANGE1[0]), 0, 0 }, + { "mmRCC_BUS_CNTL", REG_MMIO, 0x00c1, 2, &mmRCC_BUS_CNTL[0], sizeof(mmRCC_BUS_CNTL)/sizeof(mmRCC_BUS_CNTL[0]), 0, 0 }, + { "mmRCC_CONFIG_CNTL", REG_MMIO, 0x00c2, 2, &mmRCC_CONFIG_CNTL[0], sizeof(mmRCC_CONFIG_CNTL)/sizeof(mmRCC_CONFIG_CNTL[0]), 0, 0 }, + { "mmRCC_CONFIG_F0_BASE", REG_MMIO, 0x00c6, 2, &mmRCC_CONFIG_F0_BASE[0], sizeof(mmRCC_CONFIG_F0_BASE)/sizeof(mmRCC_CONFIG_F0_BASE[0]), 0, 0 }, + { "mmRCC_CONFIG_APER_SIZE", REG_MMIO, 0x00c7, 2, &mmRCC_CONFIG_APER_SIZE[0], sizeof(mmRCC_CONFIG_APER_SIZE)/sizeof(mmRCC_CONFIG_APER_SIZE[0]), 0, 0 }, + { "mmRCC_CONFIG_REG_APER_SIZE", REG_MMIO, 0x00c8, 2, &mmRCC_CONFIG_REG_APER_SIZE[0], sizeof(mmRCC_CONFIG_REG_APER_SIZE)/sizeof(mmRCC_CONFIG_REG_APER_SIZE[0]), 0, 0 }, + { "mmRCC_XDMA_LO", REG_MMIO, 0x00c9, 2, &mmRCC_XDMA_LO[0], sizeof(mmRCC_XDMA_LO)/sizeof(mmRCC_XDMA_LO[0]), 0, 0 }, + { "mmRCC_XDMA_HI", REG_MMIO, 0x00ca, 2, &mmRCC_XDMA_HI[0], sizeof(mmRCC_XDMA_HI)/sizeof(mmRCC_XDMA_HI[0]), 0, 0 }, + { "mmRCC_FEATURES_CONTROL_MISC", REG_MMIO, 0x00cb, 2, &mmRCC_FEATURES_CONTROL_MISC[0], sizeof(mmRCC_FEATURES_CONTROL_MISC)/sizeof(mmRCC_FEATURES_CONTROL_MISC[0]), 0, 0 }, + { "mmRCC_BUSNUM_CNTL1", REG_MMIO, 0x00cc, 2, &mmRCC_BUSNUM_CNTL1[0], sizeof(mmRCC_BUSNUM_CNTL1)/sizeof(mmRCC_BUSNUM_CNTL1[0]), 0, 0 }, + { "mmRCC_BUSNUM_LIST0", REG_MMIO, 0x00cd, 2, &mmRCC_BUSNUM_LIST0[0], sizeof(mmRCC_BUSNUM_LIST0)/sizeof(mmRCC_BUSNUM_LIST0[0]), 0, 0 }, + { "mmRCC_BUSNUM_LIST1", REG_MMIO, 0x00ce, 2, &mmRCC_BUSNUM_LIST1[0], sizeof(mmRCC_BUSNUM_LIST1)/sizeof(mmRCC_BUSNUM_LIST1[0]), 0, 0 }, + { "mmRCC_BUSNUM_CNTL2", REG_MMIO, 0x00cf, 2, &mmRCC_BUSNUM_CNTL2[0], sizeof(mmRCC_BUSNUM_CNTL2)/sizeof(mmRCC_BUSNUM_CNTL2[0]), 0, 0 }, + { "mmRCC_CAPTURE_HOST_BUSNUM", REG_MMIO, 0x00d0, 2, &mmRCC_CAPTURE_HOST_BUSNUM[0], sizeof(mmRCC_CAPTURE_HOST_BUSNUM)/sizeof(mmRCC_CAPTURE_HOST_BUSNUM[0]), 0, 0 }, + { "mmRCC_HOST_BUSNUM", REG_MMIO, 0x00d1, 2, &mmRCC_HOST_BUSNUM[0], sizeof(mmRCC_HOST_BUSNUM)/sizeof(mmRCC_HOST_BUSNUM[0]), 0, 0 }, + { "mmRCC_PEER0_FB_OFFSET_HI", REG_MMIO, 0x00d2, 2, &mmRCC_PEER0_FB_OFFSET_HI[0], sizeof(mmRCC_PEER0_FB_OFFSET_HI)/sizeof(mmRCC_PEER0_FB_OFFSET_HI[0]), 0, 0 }, + { "mmRCC_PEER0_FB_OFFSET_LO", REG_MMIO, 0x00d3, 2, &mmRCC_PEER0_FB_OFFSET_LO[0], sizeof(mmRCC_PEER0_FB_OFFSET_LO)/sizeof(mmRCC_PEER0_FB_OFFSET_LO[0]), 0, 0 }, + { "mmRCC_PEER1_FB_OFFSET_HI", REG_MMIO, 0x00d4, 2, &mmRCC_PEER1_FB_OFFSET_HI[0], sizeof(mmRCC_PEER1_FB_OFFSET_HI)/sizeof(mmRCC_PEER1_FB_OFFSET_HI[0]), 0, 0 }, + { "mmRCC_PEER1_FB_OFFSET_LO", REG_MMIO, 0x00d5, 2, &mmRCC_PEER1_FB_OFFSET_LO[0], sizeof(mmRCC_PEER1_FB_OFFSET_LO)/sizeof(mmRCC_PEER1_FB_OFFSET_LO[0]), 0, 0 }, + { "mmRCC_PEER2_FB_OFFSET_HI", REG_MMIO, 0x00d6, 2, &mmRCC_PEER2_FB_OFFSET_HI[0], sizeof(mmRCC_PEER2_FB_OFFSET_HI)/sizeof(mmRCC_PEER2_FB_OFFSET_HI[0]), 0, 0 }, + { "mmRCC_PEER2_FB_OFFSET_LO", REG_MMIO, 0x00d7, 2, &mmRCC_PEER2_FB_OFFSET_LO[0], sizeof(mmRCC_PEER2_FB_OFFSET_LO)/sizeof(mmRCC_PEER2_FB_OFFSET_LO[0]), 0, 0 }, + { "mmRCC_PEER3_FB_OFFSET_HI", REG_MMIO, 0x00d8, 2, &mmRCC_PEER3_FB_OFFSET_HI[0], sizeof(mmRCC_PEER3_FB_OFFSET_HI)/sizeof(mmRCC_PEER3_FB_OFFSET_HI[0]), 0, 0 }, + { "mmRCC_PEER3_FB_OFFSET_LO", REG_MMIO, 0x00d9, 2, &mmRCC_PEER3_FB_OFFSET_LO[0], sizeof(mmRCC_PEER3_FB_OFFSET_LO)/sizeof(mmRCC_PEER3_FB_OFFSET_LO[0]), 0, 0 }, + { "mmRCC_CMN_LINK_CNTL", REG_MMIO, 0x00de, 2, &mmRCC_CMN_LINK_CNTL[0], sizeof(mmRCC_CMN_LINK_CNTL)/sizeof(mmRCC_CMN_LINK_CNTL[0]), 0, 0 }, + { "mmRCC_EP_REQUESTERID_RESTORE", REG_MMIO, 0x00df, 2, &mmRCC_EP_REQUESTERID_RESTORE[0], sizeof(mmRCC_EP_REQUESTERID_RESTORE)/sizeof(mmRCC_EP_REQUESTERID_RESTORE[0]), 0, 0 }, + { "mmRCC_LTR_LSWITCH_CNTL", REG_MMIO, 0x00e0, 2, &mmRCC_LTR_LSWITCH_CNTL[0], sizeof(mmRCC_LTR_LSWITCH_CNTL)/sizeof(mmRCC_LTR_LSWITCH_CNTL[0]), 0, 0 }, + { "mmRCC_MH_ARB_CNTL", REG_MMIO, 0x00e1, 2, &mmRCC_MH_ARB_CNTL[0], sizeof(mmRCC_MH_ARB_CNTL)/sizeof(mmRCC_MH_ARB_CNTL[0]), 0, 0 }, + { "mmBIF_MM_INDACCESS_CNTL", REG_MMIO, 0x00e6, 2, &mmBIF_MM_INDACCESS_CNTL[0], sizeof(mmBIF_MM_INDACCESS_CNTL)/sizeof(mmBIF_MM_INDACCESS_CNTL[0]), 0, 0 }, + { "mmBUS_CNTL", REG_MMIO, 0x00e7, 2, &mmBUS_CNTL[0], sizeof(mmBUS_CNTL)/sizeof(mmBUS_CNTL[0]), 0, 0 }, + { "mmBIF_SCRATCH0", REG_MMIO, 0x00e8, 2, &mmBIF_SCRATCH0[0], sizeof(mmBIF_SCRATCH0)/sizeof(mmBIF_SCRATCH0[0]), 0, 0 }, + { "mmBIF_SCRATCH1", REG_MMIO, 0x00e9, 2, &mmBIF_SCRATCH1[0], sizeof(mmBIF_SCRATCH1)/sizeof(mmBIF_SCRATCH1[0]), 0, 0 }, + { "mmBX_RESET_EN", REG_MMIO, 0x00ed, 2, &mmBX_RESET_EN[0], sizeof(mmBX_RESET_EN)/sizeof(mmBX_RESET_EN[0]), 0, 0 }, + { "mmMM_CFGREGS_CNTL", REG_MMIO, 0x00ee, 2, &mmMM_CFGREGS_CNTL[0], sizeof(mmMM_CFGREGS_CNTL)/sizeof(mmMM_CFGREGS_CNTL[0]), 0, 0 }, + { "mmBX_RESET_CNTL", REG_MMIO, 0x00f0, 2, &mmBX_RESET_CNTL[0], sizeof(mmBX_RESET_CNTL)/sizeof(mmBX_RESET_CNTL[0]), 0, 0 }, + { "mmINTERRUPT_CNTL", REG_MMIO, 0x00f1, 2, &mmINTERRUPT_CNTL[0], sizeof(mmINTERRUPT_CNTL)/sizeof(mmINTERRUPT_CNTL[0]), 0, 0 }, + { "mmINTERRUPT_CNTL2", REG_MMIO, 0x00f2, 2, &mmINTERRUPT_CNTL2[0], sizeof(mmINTERRUPT_CNTL2)/sizeof(mmINTERRUPT_CNTL2[0]), 0, 0 }, + { "mmCLKREQB_PAD_CNTL", REG_MMIO, 0x00f8, 2, &mmCLKREQB_PAD_CNTL[0], sizeof(mmCLKREQB_PAD_CNTL)/sizeof(mmCLKREQB_PAD_CNTL[0]), 0, 0 }, + { "mmBIF_FEATURES_CONTROL_MISC", REG_MMIO, 0x00fb, 2, &mmBIF_FEATURES_CONTROL_MISC[0], sizeof(mmBIF_FEATURES_CONTROL_MISC)/sizeof(mmBIF_FEATURES_CONTROL_MISC[0]), 0, 0 }, + { "mmBIF_DOORBELL_CNTL", REG_MMIO, 0x00fc, 2, &mmBIF_DOORBELL_CNTL[0], sizeof(mmBIF_DOORBELL_CNTL)/sizeof(mmBIF_DOORBELL_CNTL[0]), 0, 0 }, + { "mmBIF_DOORBELL_INT_CNTL", REG_MMIO, 0x00fd, 2, &mmBIF_DOORBELL_INT_CNTL[0], sizeof(mmBIF_DOORBELL_INT_CNTL)/sizeof(mmBIF_DOORBELL_INT_CNTL[0]), 0, 0 }, + { "mmBIF_FB_EN", REG_MMIO, 0x00ff, 2, &mmBIF_FB_EN[0], sizeof(mmBIF_FB_EN)/sizeof(mmBIF_FB_EN[0]), 0, 0 }, + { "mmBIF_BUSY_DELAY_CNTR", REG_MMIO, 0x0100, 2, &mmBIF_BUSY_DELAY_CNTR[0], sizeof(mmBIF_BUSY_DELAY_CNTR)/sizeof(mmBIF_BUSY_DELAY_CNTR[0]), 0, 0 }, + { "mmBIF_MST_TRANS_PENDING_VF", REG_MMIO, 0x0109, 2, &mmBIF_MST_TRANS_PENDING_VF[0], sizeof(mmBIF_MST_TRANS_PENDING_VF)/sizeof(mmBIF_MST_TRANS_PENDING_VF[0]), 0, 0 }, + { "mmBIF_SLV_TRANS_PENDING_VF", REG_MMIO, 0x010a, 2, &mmBIF_SLV_TRANS_PENDING_VF[0], sizeof(mmBIF_SLV_TRANS_PENDING_VF)/sizeof(mmBIF_SLV_TRANS_PENDING_VF[0]), 0, 0 }, + { "mmBACO_CNTL", REG_MMIO, 0x010b, 2, &mmBACO_CNTL[0], sizeof(mmBACO_CNTL)/sizeof(mmBACO_CNTL[0]), 0, 0 }, + { "mmBIF_BACO_EXIT_TIME0", REG_MMIO, 0x010c, 2, &mmBIF_BACO_EXIT_TIME0[0], sizeof(mmBIF_BACO_EXIT_TIME0)/sizeof(mmBIF_BACO_EXIT_TIME0[0]), 0, 0 }, + { "mmBIF_BACO_EXIT_TIMER1", REG_MMIO, 0x010d, 2, &mmBIF_BACO_EXIT_TIMER1[0], sizeof(mmBIF_BACO_EXIT_TIMER1)/sizeof(mmBIF_BACO_EXIT_TIMER1[0]), 0, 0 }, + { "mmBIF_BACO_EXIT_TIMER2", REG_MMIO, 0x010e, 2, &mmBIF_BACO_EXIT_TIMER2[0], sizeof(mmBIF_BACO_EXIT_TIMER2)/sizeof(mmBIF_BACO_EXIT_TIMER2[0]), 0, 0 }, + { "mmBIF_BACO_EXIT_TIMER3", REG_MMIO, 0x010f, 2, &mmBIF_BACO_EXIT_TIMER3[0], sizeof(mmBIF_BACO_EXIT_TIMER3)/sizeof(mmBIF_BACO_EXIT_TIMER3[0]), 0, 0 }, + { "mmBIF_BACO_EXIT_TIMER4", REG_MMIO, 0x0110, 2, &mmBIF_BACO_EXIT_TIMER4[0], sizeof(mmBIF_BACO_EXIT_TIMER4)/sizeof(mmBIF_BACO_EXIT_TIMER4[0]), 0, 0 }, + { "mmMEM_TYPE_CNTL", REG_MMIO, 0x0111, 2, &mmMEM_TYPE_CNTL[0], sizeof(mmMEM_TYPE_CNTL)/sizeof(mmMEM_TYPE_CNTL[0]), 0, 0 }, + { "mmSMU_BIF_VDDGFX_PWR_STATUS", REG_MMIO, 0x0113, 2, &mmSMU_BIF_VDDGFX_PWR_STATUS[0], sizeof(mmSMU_BIF_VDDGFX_PWR_STATUS)/sizeof(mmSMU_BIF_VDDGFX_PWR_STATUS[0]), 0, 0 }, + { "mmBIF_VDDGFX_GFX0_LOWER", REG_MMIO, 0x0114, 2, &mmBIF_VDDGFX_GFX0_LOWER[0], sizeof(mmBIF_VDDGFX_GFX0_LOWER)/sizeof(mmBIF_VDDGFX_GFX0_LOWER[0]), 0, 0 }, + { "mmBIF_VDDGFX_GFX0_UPPER", REG_MMIO, 0x0115, 2, &mmBIF_VDDGFX_GFX0_UPPER[0], sizeof(mmBIF_VDDGFX_GFX0_UPPER)/sizeof(mmBIF_VDDGFX_GFX0_UPPER[0]), 0, 0 }, + { "mmBIF_VDDGFX_GFX1_LOWER", REG_MMIO, 0x0116, 2, &mmBIF_VDDGFX_GFX1_LOWER[0], sizeof(mmBIF_VDDGFX_GFX1_LOWER)/sizeof(mmBIF_VDDGFX_GFX1_LOWER[0]), 0, 0 }, + { "mmBIF_VDDGFX_GFX1_UPPER", REG_MMIO, 0x0117, 2, &mmBIF_VDDGFX_GFX1_UPPER[0], sizeof(mmBIF_VDDGFX_GFX1_UPPER)/sizeof(mmBIF_VDDGFX_GFX1_UPPER[0]), 0, 0 }, + { "mmBIF_VDDGFX_GFX2_LOWER", REG_MMIO, 0x0118, 2, &mmBIF_VDDGFX_GFX2_LOWER[0], sizeof(mmBIF_VDDGFX_GFX2_LOWER)/sizeof(mmBIF_VDDGFX_GFX2_LOWER[0]), 0, 0 }, + { "mmBIF_VDDGFX_GFX2_UPPER", REG_MMIO, 0x0119, 2, &mmBIF_VDDGFX_GFX2_UPPER[0], sizeof(mmBIF_VDDGFX_GFX2_UPPER)/sizeof(mmBIF_VDDGFX_GFX2_UPPER[0]), 0, 0 }, + { "mmBIF_VDDGFX_GFX3_LOWER", REG_MMIO, 0x011a, 2, &mmBIF_VDDGFX_GFX3_LOWER[0], sizeof(mmBIF_VDDGFX_GFX3_LOWER)/sizeof(mmBIF_VDDGFX_GFX3_LOWER[0]), 0, 0 }, + { "mmBIF_VDDGFX_GFX3_UPPER", REG_MMIO, 0x011b, 2, &mmBIF_VDDGFX_GFX3_UPPER[0], sizeof(mmBIF_VDDGFX_GFX3_UPPER)/sizeof(mmBIF_VDDGFX_GFX3_UPPER[0]), 0, 0 }, + { "mmBIF_VDDGFX_GFX4_LOWER", REG_MMIO, 0x011c, 2, &mmBIF_VDDGFX_GFX4_LOWER[0], sizeof(mmBIF_VDDGFX_GFX4_LOWER)/sizeof(mmBIF_VDDGFX_GFX4_LOWER[0]), 0, 0 }, + { "mmBIF_VDDGFX_GFX4_UPPER", REG_MMIO, 0x011d, 2, &mmBIF_VDDGFX_GFX4_UPPER[0], sizeof(mmBIF_VDDGFX_GFX4_UPPER)/sizeof(mmBIF_VDDGFX_GFX4_UPPER[0]), 0, 0 }, + { "mmBIF_VDDGFX_GFX5_LOWER", REG_MMIO, 0x011e, 2, &mmBIF_VDDGFX_GFX5_LOWER[0], sizeof(mmBIF_VDDGFX_GFX5_LOWER)/sizeof(mmBIF_VDDGFX_GFX5_LOWER[0]), 0, 0 }, + { "mmBIF_VDDGFX_GFX5_UPPER", REG_MMIO, 0x011f, 2, &mmBIF_VDDGFX_GFX5_UPPER[0], sizeof(mmBIF_VDDGFX_GFX5_UPPER)/sizeof(mmBIF_VDDGFX_GFX5_UPPER[0]), 0, 0 }, + { "mmBIF_VDDGFX_RSV1_LOWER", REG_MMIO, 0x0120, 2, &mmBIF_VDDGFX_RSV1_LOWER[0], sizeof(mmBIF_VDDGFX_RSV1_LOWER)/sizeof(mmBIF_VDDGFX_RSV1_LOWER[0]), 0, 0 }, + { "mmBIF_VDDGFX_RSV1_UPPER", REG_MMIO, 0x0121, 2, &mmBIF_VDDGFX_RSV1_UPPER[0], sizeof(mmBIF_VDDGFX_RSV1_UPPER)/sizeof(mmBIF_VDDGFX_RSV1_UPPER[0]), 0, 0 }, + { "mmBIF_VDDGFX_RSV2_LOWER", REG_MMIO, 0x0122, 2, &mmBIF_VDDGFX_RSV2_LOWER[0], sizeof(mmBIF_VDDGFX_RSV2_LOWER)/sizeof(mmBIF_VDDGFX_RSV2_LOWER[0]), 0, 0 }, + { "mmBIF_VDDGFX_RSV2_UPPER", REG_MMIO, 0x0123, 2, &mmBIF_VDDGFX_RSV2_UPPER[0], sizeof(mmBIF_VDDGFX_RSV2_UPPER)/sizeof(mmBIF_VDDGFX_RSV2_UPPER[0]), 0, 0 }, + { "mmBIF_VDDGFX_RSV3_LOWER", REG_MMIO, 0x0124, 2, &mmBIF_VDDGFX_RSV3_LOWER[0], sizeof(mmBIF_VDDGFX_RSV3_LOWER)/sizeof(mmBIF_VDDGFX_RSV3_LOWER[0]), 0, 0 }, + { "mmBIF_VDDGFX_RSV3_UPPER", REG_MMIO, 0x0125, 2, &mmBIF_VDDGFX_RSV3_UPPER[0], sizeof(mmBIF_VDDGFX_RSV3_UPPER)/sizeof(mmBIF_VDDGFX_RSV3_UPPER[0]), 0, 0 }, + { "mmBIF_VDDGFX_RSV4_LOWER", REG_MMIO, 0x0126, 2, &mmBIF_VDDGFX_RSV4_LOWER[0], sizeof(mmBIF_VDDGFX_RSV4_LOWER)/sizeof(mmBIF_VDDGFX_RSV4_LOWER[0]), 0, 0 }, + { "mmBIF_VDDGFX_RSV4_UPPER", REG_MMIO, 0x0127, 2, &mmBIF_VDDGFX_RSV4_UPPER[0], sizeof(mmBIF_VDDGFX_RSV4_UPPER)/sizeof(mmBIF_VDDGFX_RSV4_UPPER[0]), 0, 0 }, + { "mmBIF_VDDGFX_FB_CMP", REG_MMIO, 0x0128, 2, &mmBIF_VDDGFX_FB_CMP[0], sizeof(mmBIF_VDDGFX_FB_CMP)/sizeof(mmBIF_VDDGFX_FB_CMP[0]), 0, 0 }, + { "mmBIF_DOORBELL_GBLAPER1_LOWER", REG_MMIO, 0x0129, 2, &mmBIF_DOORBELL_GBLAPER1_LOWER[0], sizeof(mmBIF_DOORBELL_GBLAPER1_LOWER)/sizeof(mmBIF_DOORBELL_GBLAPER1_LOWER[0]), 0, 0 }, + { "mmBIF_DOORBELL_GBLAPER1_UPPER", REG_MMIO, 0x012a, 2, &mmBIF_DOORBELL_GBLAPER1_UPPER[0], sizeof(mmBIF_DOORBELL_GBLAPER1_UPPER)/sizeof(mmBIF_DOORBELL_GBLAPER1_UPPER[0]), 0, 0 }, + { "mmBIF_DOORBELL_GBLAPER2_LOWER", REG_MMIO, 0x012b, 2, &mmBIF_DOORBELL_GBLAPER2_LOWER[0], sizeof(mmBIF_DOORBELL_GBLAPER2_LOWER)/sizeof(mmBIF_DOORBELL_GBLAPER2_LOWER[0]), 0, 0 }, + { "mmBIF_DOORBELL_GBLAPER2_UPPER", REG_MMIO, 0x012c, 2, &mmBIF_DOORBELL_GBLAPER2_UPPER[0], sizeof(mmBIF_DOORBELL_GBLAPER2_UPPER)/sizeof(mmBIF_DOORBELL_GBLAPER2_UPPER[0]), 0, 0 }, + { "mmREMAP_HDP_MEM_FLUSH_CNTL", REG_MMIO, 0x012d, 2, &mmREMAP_HDP_MEM_FLUSH_CNTL[0], sizeof(mmREMAP_HDP_MEM_FLUSH_CNTL)/sizeof(mmREMAP_HDP_MEM_FLUSH_CNTL[0]), 0, 0 }, + { "mmREMAP_HDP_REG_FLUSH_CNTL", REG_MMIO, 0x012e, 2, &mmREMAP_HDP_REG_FLUSH_CNTL[0], sizeof(mmREMAP_HDP_REG_FLUSH_CNTL)/sizeof(mmREMAP_HDP_REG_FLUSH_CNTL[0]), 0, 0 }, + { "mmBIF_RB_CNTL", REG_MMIO, 0x012f, 2, &mmBIF_RB_CNTL[0], sizeof(mmBIF_RB_CNTL)/sizeof(mmBIF_RB_CNTL[0]), 0, 0 }, + { "mmBIF_RB_BASE", REG_MMIO, 0x0130, 2, &mmBIF_RB_BASE[0], sizeof(mmBIF_RB_BASE)/sizeof(mmBIF_RB_BASE[0]), 0, 0 }, + { "mmBIF_RB_RPTR", REG_MMIO, 0x0131, 2, &mmBIF_RB_RPTR[0], sizeof(mmBIF_RB_RPTR)/sizeof(mmBIF_RB_RPTR[0]), 0, 0 }, + { "mmBIF_RB_WPTR", REG_MMIO, 0x0132, 2, &mmBIF_RB_WPTR[0], sizeof(mmBIF_RB_WPTR)/sizeof(mmBIF_RB_WPTR[0]), 0, 0 }, + { "mmBIF_RB_WPTR_ADDR_HI", REG_MMIO, 0x0133, 2, &mmBIF_RB_WPTR_ADDR_HI[0], sizeof(mmBIF_RB_WPTR_ADDR_HI)/sizeof(mmBIF_RB_WPTR_ADDR_HI[0]), 0, 0 }, + { "mmBIF_RB_WPTR_ADDR_LO", REG_MMIO, 0x0134, 2, &mmBIF_RB_WPTR_ADDR_LO[0], sizeof(mmBIF_RB_WPTR_ADDR_LO)/sizeof(mmBIF_RB_WPTR_ADDR_LO[0]), 0, 0 }, + { "mmMAILBOX_INDEX", REG_MMIO, 0x0135, 2, &mmMAILBOX_INDEX[0], sizeof(mmMAILBOX_INDEX)/sizeof(mmMAILBOX_INDEX[0]), 0, 0 }, + { "mmBIF_UVD_GPUIOV_CFG_SIZE", REG_MMIO, 0x0143, 2, &mmBIF_UVD_GPUIOV_CFG_SIZE[0], sizeof(mmBIF_UVD_GPUIOV_CFG_SIZE)/sizeof(mmBIF_UVD_GPUIOV_CFG_SIZE[0]), 0, 0 }, + { "mmBIF_VCE_GPUIOV_CFG_SIZE", REG_MMIO, 0x0144, 2, &mmBIF_VCE_GPUIOV_CFG_SIZE[0], sizeof(mmBIF_VCE_GPUIOV_CFG_SIZE)/sizeof(mmBIF_VCE_GPUIOV_CFG_SIZE[0]), 0, 0 }, + { "mmBIF_GFX_SDMA_GPUIOV_CFG_SIZE", REG_MMIO, 0x0145, 2, &mmBIF_GFX_SDMA_GPUIOV_CFG_SIZE[0], sizeof(mmBIF_GFX_SDMA_GPUIOV_CFG_SIZE)/sizeof(mmBIF_GFX_SDMA_GPUIOV_CFG_SIZE[0]), 0, 0 }, + { "mmBIF_PERSTB_PAD_CNTL", REG_MMIO, 0x0148, 2, &mmBIF_PERSTB_PAD_CNTL[0], sizeof(mmBIF_PERSTB_PAD_CNTL)/sizeof(mmBIF_PERSTB_PAD_CNTL[0]), 0, 0 }, + { "mmBIF_PX_EN_PAD_CNTL", REG_MMIO, 0x0149, 2, &mmBIF_PX_EN_PAD_CNTL[0], sizeof(mmBIF_PX_EN_PAD_CNTL)/sizeof(mmBIF_PX_EN_PAD_CNTL[0]), 0, 0 }, + { "mmBIF_REFPADKIN_PAD_CNTL", REG_MMIO, 0x014a, 2, &mmBIF_REFPADKIN_PAD_CNTL[0], sizeof(mmBIF_REFPADKIN_PAD_CNTL)/sizeof(mmBIF_REFPADKIN_PAD_CNTL[0]), 0, 0 }, + { "mmBIF_CLKREQB_PAD_CNTL", REG_MMIO, 0x014b, 2, &mmBIF_CLKREQB_PAD_CNTL[0], sizeof(mmBIF_CLKREQB_PAD_CNTL)/sizeof(mmBIF_CLKREQB_PAD_CNTL[0]), 0, 0 }, + { "mmBIF_BME_STATUS", REG_MMIO, 0x00eb, 2, &mmBIF_BME_STATUS[0], sizeof(mmBIF_BME_STATUS)/sizeof(mmBIF_BME_STATUS[0]), 0, 0 }, + { "mmBIF_ATOMIC_ERR_LOG", REG_MMIO, 0x00ec, 2, &mmBIF_ATOMIC_ERR_LOG[0], sizeof(mmBIF_ATOMIC_ERR_LOG)/sizeof(mmBIF_ATOMIC_ERR_LOG[0]), 0, 0 }, + { "mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH", REG_MMIO, 0x00f3, 2, &mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH[0], sizeof(mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH)/sizeof(mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH[0]), 0, 0 }, + { "mmDOORBELL_SELFRING_GPA_APER_BASE_LOW", REG_MMIO, 0x00f4, 2, &mmDOORBELL_SELFRING_GPA_APER_BASE_LOW[0], sizeof(mmDOORBELL_SELFRING_GPA_APER_BASE_LOW)/sizeof(mmDOORBELL_SELFRING_GPA_APER_BASE_LOW[0]), 0, 0 }, + { "mmDOORBELL_SELFRING_GPA_APER_CNTL", REG_MMIO, 0x00f5, 2, &mmDOORBELL_SELFRING_GPA_APER_CNTL[0], sizeof(mmDOORBELL_SELFRING_GPA_APER_CNTL)/sizeof(mmDOORBELL_SELFRING_GPA_APER_CNTL[0]), 0, 0 }, + { "mmHDP_REG_COHERENCY_FLUSH_CNTL", REG_MMIO, 0x00f6, 2, &mmHDP_REG_COHERENCY_FLUSH_CNTL[0], sizeof(mmHDP_REG_COHERENCY_FLUSH_CNTL)/sizeof(mmHDP_REG_COHERENCY_FLUSH_CNTL[0]), 0, 0 }, + { "mmHDP_MEM_COHERENCY_FLUSH_CNTL", REG_MMIO, 0x00f7, 2, &mmHDP_MEM_COHERENCY_FLUSH_CNTL[0], sizeof(mmHDP_MEM_COHERENCY_FLUSH_CNTL)/sizeof(mmHDP_MEM_COHERENCY_FLUSH_CNTL[0]), 0, 0 }, + { "mmGPU_HDP_FLUSH_REQ", REG_MMIO, 0x0106, 2, &mmGPU_HDP_FLUSH_REQ[0], sizeof(mmGPU_HDP_FLUSH_REQ)/sizeof(mmGPU_HDP_FLUSH_REQ[0]), 0, 0 }, + { "mmGPU_HDP_FLUSH_DONE", REG_MMIO, 0x0107, 2, &mmGPU_HDP_FLUSH_DONE[0], sizeof(mmGPU_HDP_FLUSH_DONE)/sizeof(mmGPU_HDP_FLUSH_DONE[0]), 0, 0 }, + { "mmBIF_TRANS_PENDING", REG_MMIO, 0x0108, 2, &mmBIF_TRANS_PENDING[0], sizeof(mmBIF_TRANS_PENDING)/sizeof(mmBIF_TRANS_PENDING[0]), 0, 0 }, + { "mmMAILBOX_MSGBUF_TRN_DW0", REG_MMIO, 0x0136, 2, &mmMAILBOX_MSGBUF_TRN_DW0[0], sizeof(mmMAILBOX_MSGBUF_TRN_DW0)/sizeof(mmMAILBOX_MSGBUF_TRN_DW0[0]), 0, 0 }, + { "mmMAILBOX_MSGBUF_TRN_DW1", REG_MMIO, 0x0137, 2, &mmMAILBOX_MSGBUF_TRN_DW1[0], sizeof(mmMAILBOX_MSGBUF_TRN_DW1)/sizeof(mmMAILBOX_MSGBUF_TRN_DW1[0]), 0, 0 }, + { "mmMAILBOX_MSGBUF_TRN_DW2", REG_MMIO, 0x0138, 2, &mmMAILBOX_MSGBUF_TRN_DW2[0], sizeof(mmMAILBOX_MSGBUF_TRN_DW2)/sizeof(mmMAILBOX_MSGBUF_TRN_DW2[0]), 0, 0 }, + { "mmMAILBOX_MSGBUF_TRN_DW3", REG_MMIO, 0x0139, 2, &mmMAILBOX_MSGBUF_TRN_DW3[0], sizeof(mmMAILBOX_MSGBUF_TRN_DW3)/sizeof(mmMAILBOX_MSGBUF_TRN_DW3[0]), 0, 0 }, + { "mmMAILBOX_MSGBUF_RCV_DW0", REG_MMIO, 0x013a, 2, &mmMAILBOX_MSGBUF_RCV_DW0[0], sizeof(mmMAILBOX_MSGBUF_RCV_DW0)/sizeof(mmMAILBOX_MSGBUF_RCV_DW0[0]), 0, 0 }, + { "mmMAILBOX_MSGBUF_RCV_DW1", REG_MMIO, 0x013b, 2, &mmMAILBOX_MSGBUF_RCV_DW1[0], sizeof(mmMAILBOX_MSGBUF_RCV_DW1)/sizeof(mmMAILBOX_MSGBUF_RCV_DW1[0]), 0, 0 }, + { "mmMAILBOX_MSGBUF_RCV_DW2", REG_MMIO, 0x013c, 2, &mmMAILBOX_MSGBUF_RCV_DW2[0], sizeof(mmMAILBOX_MSGBUF_RCV_DW2)/sizeof(mmMAILBOX_MSGBUF_RCV_DW2[0]), 0, 0 }, + { "mmMAILBOX_MSGBUF_RCV_DW3", REG_MMIO, 0x013d, 2, &mmMAILBOX_MSGBUF_RCV_DW3[0], sizeof(mmMAILBOX_MSGBUF_RCV_DW3)/sizeof(mmMAILBOX_MSGBUF_RCV_DW3[0]), 0, 0 }, + { "mmMAILBOX_CONTROL", REG_MMIO, 0x013e, 2, &mmMAILBOX_CONTROL[0], sizeof(mmMAILBOX_CONTROL)/sizeof(mmMAILBOX_CONTROL[0]), 0, 0 }, + { "mmMAILBOX_INT_CNTL", REG_MMIO, 0x013f, 2, &mmMAILBOX_INT_CNTL[0], sizeof(mmMAILBOX_INT_CNTL)/sizeof(mmMAILBOX_INT_CNTL[0]), 0, 0 }, + { "mmBIF_VMHV_MAILBOX", REG_MMIO, 0x0140, 2, &mmBIF_VMHV_MAILBOX[0], sizeof(mmBIF_VMHV_MAILBOX)/sizeof(mmBIF_VMHV_MAILBOX[0]), 0, 0 }, + { "mmNGDC_SDP_PORT_CTRL", REG_MMIO, 0x01c2, 2, &mmNGDC_SDP_PORT_CTRL[0], sizeof(mmNGDC_SDP_PORT_CTRL)/sizeof(mmNGDC_SDP_PORT_CTRL[0]), 0, 0 }, + { "mmSHUB_REGS_IF_CTL", REG_MMIO, 0x01c3, 2, &mmSHUB_REGS_IF_CTL[0], sizeof(mmSHUB_REGS_IF_CTL)/sizeof(mmSHUB_REGS_IF_CTL[0]), 0, 0 }, + { "mmNGDC_RESERVED_0", REG_MMIO, 0x01cb, 2, &mmNGDC_RESERVED_0[0], sizeof(mmNGDC_RESERVED_0)/sizeof(mmNGDC_RESERVED_0[0]), 0, 0 }, + { "mmNGDC_RESERVED_1", REG_MMIO, 0x01cc, 2, &mmNGDC_RESERVED_1[0], sizeof(mmNGDC_RESERVED_1)/sizeof(mmNGDC_RESERVED_1[0]), 0, 0 }, + { "mmNGDC_SDP_PORT_CTRL_SOCCLK", REG_MMIO, 0x01cd, 2, &mmNGDC_SDP_PORT_CTRL_SOCCLK[0], sizeof(mmNGDC_SDP_PORT_CTRL_SOCCLK)/sizeof(mmNGDC_SDP_PORT_CTRL_SOCCLK[0]), 0, 0 }, + { "mmBIF_SDMA0_DOORBELL_RANGE", REG_MMIO, 0x01d0, 2, &mmBIF_SDMA0_DOORBELL_RANGE[0], sizeof(mmBIF_SDMA0_DOORBELL_RANGE)/sizeof(mmBIF_SDMA0_DOORBELL_RANGE[0]), 0, 0 }, + { "mmBIF_SDMA1_DOORBELL_RANGE", REG_MMIO, 0x01d1, 2, &mmBIF_SDMA1_DOORBELL_RANGE[0], sizeof(mmBIF_SDMA1_DOORBELL_RANGE)/sizeof(mmBIF_SDMA1_DOORBELL_RANGE[0]), 0, 0 }, + { "mmBIF_IH_DOORBELL_RANGE", REG_MMIO, 0x01d2, 2, &mmBIF_IH_DOORBELL_RANGE[0], sizeof(mmBIF_IH_DOORBELL_RANGE)/sizeof(mmBIF_IH_DOORBELL_RANGE[0]), 0, 0 }, + { "mmBIF_MMSCH0_DOORBELL_RANGE", REG_MMIO, 0x01d3, 2, &mmBIF_MMSCH0_DOORBELL_RANGE[0], sizeof(mmBIF_MMSCH0_DOORBELL_RANGE)/sizeof(mmBIF_MMSCH0_DOORBELL_RANGE[0]), 0, 0 }, + { "mmATDMA_MISC_CNTL", REG_MMIO, 0x01dd, 2, &mmATDMA_MISC_CNTL[0], sizeof(mmATDMA_MISC_CNTL)/sizeof(mmATDMA_MISC_CNTL[0]), 0, 0 }, + { "mmBIF_DOORBELL_FENCE_CNTL", REG_MMIO, 0x01de, 2, &mmBIF_DOORBELL_FENCE_CNTL[0], sizeof(mmBIF_DOORBELL_FENCE_CNTL)/sizeof(mmBIF_DOORBELL_FENCE_CNTL[0]), 0, 0 }, + { "mmS2A_MISC_CNTL", REG_MMIO, 0x01df, 2, &mmS2A_MISC_CNTL[0], sizeof(mmS2A_MISC_CNTL)/sizeof(mmS2A_MISC_CNTL[0]), 0, 0 }, + { "mmGDC_PG_MISC_CNTL", REG_MMIO, 0x01f0, 2, &mmGDC_PG_MISC_CNTL[0], sizeof(mmGDC_PG_MISC_CNTL)/sizeof(mmGDC_PG_MISC_CNTL[0]), 0, 0 }, + { "mmGFXMSIX_VECT0_ADDR_LO", REG_MMIO, 0x0400, 3, &mmGFXMSIX_VECT0_ADDR_LO[0], sizeof(mmGFXMSIX_VECT0_ADDR_LO)/sizeof(mmGFXMSIX_VECT0_ADDR_LO[0]), 0, 0 }, + { "mmGFXMSIX_VECT0_ADDR_HI", REG_MMIO, 0x0401, 3, &mmGFXMSIX_VECT0_ADDR_HI[0], sizeof(mmGFXMSIX_VECT0_ADDR_HI)/sizeof(mmGFXMSIX_VECT0_ADDR_HI[0]), 0, 0 }, + { "mmGFXMSIX_VECT0_MSG_DATA", REG_MMIO, 0x0402, 3, &mmGFXMSIX_VECT0_MSG_DATA[0], sizeof(mmGFXMSIX_VECT0_MSG_DATA)/sizeof(mmGFXMSIX_VECT0_MSG_DATA[0]), 0, 0 }, + { "mmGFXMSIX_VECT0_CONTROL", REG_MMIO, 0x0403, 3, &mmGFXMSIX_VECT0_CONTROL[0], sizeof(mmGFXMSIX_VECT0_CONTROL)/sizeof(mmGFXMSIX_VECT0_CONTROL[0]), 0, 0 }, + { "mmGFXMSIX_VECT1_ADDR_LO", REG_MMIO, 0x0404, 3, &mmGFXMSIX_VECT1_ADDR_LO[0], sizeof(mmGFXMSIX_VECT1_ADDR_LO)/sizeof(mmGFXMSIX_VECT1_ADDR_LO[0]), 0, 0 }, + { "mmGFXMSIX_VECT1_ADDR_HI", REG_MMIO, 0x0405, 3, &mmGFXMSIX_VECT1_ADDR_HI[0], sizeof(mmGFXMSIX_VECT1_ADDR_HI)/sizeof(mmGFXMSIX_VECT1_ADDR_HI[0]), 0, 0 }, + { "mmGFXMSIX_VECT1_MSG_DATA", REG_MMIO, 0x0406, 3, &mmGFXMSIX_VECT1_MSG_DATA[0], sizeof(mmGFXMSIX_VECT1_MSG_DATA)/sizeof(mmGFXMSIX_VECT1_MSG_DATA[0]), 0, 0 }, + { "mmGFXMSIX_VECT1_CONTROL", REG_MMIO, 0x0407, 3, &mmGFXMSIX_VECT1_CONTROL[0], sizeof(mmGFXMSIX_VECT1_CONTROL)/sizeof(mmGFXMSIX_VECT1_CONTROL[0]), 0, 0 }, + { "mmGFXMSIX_VECT2_ADDR_LO", REG_MMIO, 0x0408, 3, &mmGFXMSIX_VECT2_ADDR_LO[0], sizeof(mmGFXMSIX_VECT2_ADDR_LO)/sizeof(mmGFXMSIX_VECT2_ADDR_LO[0]), 0, 0 }, + { "mmGFXMSIX_VECT2_ADDR_HI", REG_MMIO, 0x0409, 3, &mmGFXMSIX_VECT2_ADDR_HI[0], sizeof(mmGFXMSIX_VECT2_ADDR_HI)/sizeof(mmGFXMSIX_VECT2_ADDR_HI[0]), 0, 0 }, + { "mmGFXMSIX_VECT2_MSG_DATA", REG_MMIO, 0x040a, 3, &mmGFXMSIX_VECT2_MSG_DATA[0], sizeof(mmGFXMSIX_VECT2_MSG_DATA)/sizeof(mmGFXMSIX_VECT2_MSG_DATA[0]), 0, 0 }, + { "mmGFXMSIX_VECT2_CONTROL", REG_MMIO, 0x040b, 3, &mmGFXMSIX_VECT2_CONTROL[0], sizeof(mmGFXMSIX_VECT2_CONTROL)/sizeof(mmGFXMSIX_VECT2_CONTROL[0]), 0, 0 }, + { "mmGFXMSIX_PBA", REG_MMIO, 0x0800, 3, &mmGFXMSIX_PBA[0], sizeof(mmGFXMSIX_PBA)/sizeof(mmGFXMSIX_PBA[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK", REG_SMC, 0x10000, 0, &ixSYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK[0], sizeof(ixSYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK)/sizeof(ixSYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_SYSHUB_DS_CTRL2_SOCCLK", REG_SMC, 0x10004, 0, &ixSYSHUB_MMREG_IND_SYSHUB_DS_CTRL2_SOCCLK[0], sizeof(ixSYSHUB_MMREG_IND_SYSHUB_DS_CTRL2_SOCCLK)/sizeof(ixSYSHUB_MMREG_IND_SYSHUB_DS_CTRL2_SOCCLK[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK", REG_SMC, 0x10008, 0, &ixSYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK[0], sizeof(ixSYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK)/sizeof(ixSYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK", REG_SMC, 0x1000c, 0, &ixSYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK[0], sizeof(ixSYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK)/sizeof(ixSYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL", REG_SMC, 0x10010, 0, &ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL[0], sizeof(ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL)/sizeof(ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL", REG_SMC, 0x10014, 0, &ixSYSHUB_MMREG_IND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL[0], sizeof(ixSYSHUB_MMREG_IND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL)/sizeof(ixSYSHUB_MMREG_IND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_DMA_CLK0_SW2_SYSHUB_QOS_CNTL", REG_SMC, 0x10018, 0, &ixSYSHUB_MMREG_IND_DMA_CLK0_SW2_SYSHUB_QOS_CNTL[0], sizeof(ixSYSHUB_MMREG_IND_DMA_CLK0_SW2_SYSHUB_QOS_CNTL)/sizeof(ixSYSHUB_MMREG_IND_DMA_CLK0_SW2_SYSHUB_QOS_CNTL[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL", REG_SMC, 0x1001c, 0, &ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL[0], sizeof(ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL)/sizeof(ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL", REG_SMC, 0x10020, 0, &ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL[0], sizeof(ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL)/sizeof(ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL", REG_SMC, 0x10024, 0, &ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL[0], sizeof(ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL)/sizeof(ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL", REG_SMC, 0x10028, 0, &ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL[0], sizeof(ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL)/sizeof(ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL", REG_SMC, 0x1002c, 0, &ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL[0], sizeof(ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL)/sizeof(ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL", REG_SMC, 0x10030, 0, &ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL[0], sizeof(ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL)/sizeof(ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL", REG_SMC, 0x10034, 0, &ixSYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL[0], sizeof(ixSYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL)/sizeof(ixSYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL", REG_SMC, 0x10038, 0, &ixSYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL[0], sizeof(ixSYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL)/sizeof(ixSYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_HST_CLK0_SW0_CL0_CNTL", REG_SMC, 0x10100, 0, &ixSYSHUB_MMREG_IND_HST_CLK0_SW0_CL0_CNTL[0], sizeof(ixSYSHUB_MMREG_IND_HST_CLK0_SW0_CL0_CNTL)/sizeof(ixSYSHUB_MMREG_IND_HST_CLK0_SW0_CL0_CNTL[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_HST_CLK0_SW0_CL1_CNTL", REG_SMC, 0x10104, 0, &ixSYSHUB_MMREG_IND_HST_CLK0_SW0_CL1_CNTL[0], sizeof(ixSYSHUB_MMREG_IND_HST_CLK0_SW0_CL1_CNTL)/sizeof(ixSYSHUB_MMREG_IND_HST_CLK0_SW0_CL1_CNTL[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_HST_CLK0_SW0_CL2_CNTL", REG_SMC, 0x10108, 0, &ixSYSHUB_MMREG_IND_HST_CLK0_SW0_CL2_CNTL[0], sizeof(ixSYSHUB_MMREG_IND_HST_CLK0_SW0_CL2_CNTL)/sizeof(ixSYSHUB_MMREG_IND_HST_CLK0_SW0_CL2_CNTL[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL0_CNTL", REG_SMC, 0x1010c, 0, &ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL0_CNTL[0], sizeof(ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL0_CNTL)/sizeof(ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL0_CNTL[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL1_CNTL", REG_SMC, 0x10110, 0, &ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL1_CNTL[0], sizeof(ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL1_CNTL)/sizeof(ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL1_CNTL[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL2_CNTL", REG_SMC, 0x10114, 0, &ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL2_CNTL[0], sizeof(ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL2_CNTL)/sizeof(ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL2_CNTL[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL3_CNTL", REG_SMC, 0x10118, 0, &ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL3_CNTL[0], sizeof(ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL3_CNTL)/sizeof(ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL3_CNTL[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL4_CNTL", REG_SMC, 0x1011c, 0, &ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL4_CNTL[0], sizeof(ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL4_CNTL)/sizeof(ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL4_CNTL[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_SYSHUB_CG_CNTL", REG_SMC, 0x10300, 0, &ixSYSHUB_MMREG_IND_SYSHUB_CG_CNTL[0], sizeof(ixSYSHUB_MMREG_IND_SYSHUB_CG_CNTL)/sizeof(ixSYSHUB_MMREG_IND_SYSHUB_CG_CNTL[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE", REG_SMC, 0x10308, 0, &ixSYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE[0], sizeof(ixSYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE)/sizeof(ixSYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_SYSHUB_HP_TIMER", REG_SMC, 0x1030c, 0, &ixSYSHUB_MMREG_IND_SYSHUB_HP_TIMER[0], sizeof(ixSYSHUB_MMREG_IND_SYSHUB_HP_TIMER)/sizeof(ixSYSHUB_MMREG_IND_SYSHUB_HP_TIMER[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK", REG_SMC, 0x10310, 0, &ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK[0], sizeof(ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK)/sizeof(ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_SYSUB_CPF_DOORBELL_RS_RESET", REG_SMC, 0x10314, 0, &ixSYSHUB_MMREG_IND_SYSUB_CPF_DOORBELL_RS_RESET[0], sizeof(ixSYSHUB_MMREG_IND_SYSUB_CPF_DOORBELL_RS_RESET)/sizeof(ixSYSHUB_MMREG_IND_SYSUB_CPF_DOORBELL_RS_RESET[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_SYSHUB_SCRATCH", REG_SMC, 0x10f00, 0, &ixSYSHUB_MMREG_IND_SYSHUB_SCRATCH[0], sizeof(ixSYSHUB_MMREG_IND_SYSHUB_SCRATCH)/sizeof(ixSYSHUB_MMREG_IND_SYSHUB_SCRATCH[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_SYSHUB_CL_MASK", REG_SMC, 0x10f04, 0, &ixSYSHUB_MMREG_IND_SYSHUB_CL_MASK[0], sizeof(ixSYSHUB_MMREG_IND_SYSHUB_CL_MASK)/sizeof(ixSYSHUB_MMREG_IND_SYSHUB_CL_MASK[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK", REG_SMC, 0x11000, 0, &ixSYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK[0], sizeof(ixSYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK)/sizeof(ixSYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_SYSHUB_DS_CTRL2_SHUBCLK", REG_SMC, 0x11004, 0, &ixSYSHUB_MMREG_IND_SYSHUB_DS_CTRL2_SHUBCLK[0], sizeof(ixSYSHUB_MMREG_IND_SYSHUB_DS_CTRL2_SHUBCLK)/sizeof(ixSYSHUB_MMREG_IND_SYSHUB_DS_CTRL2_SHUBCLK[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK", REG_SMC, 0x11008, 0, &ixSYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK[0], sizeof(ixSYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK)/sizeof(ixSYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK", REG_SMC, 0x1100c, 0, &ixSYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK[0], sizeof(ixSYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK)/sizeof(ixSYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL", REG_SMC, 0x11010, 0, &ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL[0], sizeof(ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL)/sizeof(ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL", REG_SMC, 0x11014, 0, &ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL[0], sizeof(ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL)/sizeof(ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL", REG_SMC, 0x11018, 0, &ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL[0], sizeof(ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL)/sizeof(ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL", REG_SMC, 0x1101c, 0, &ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL[0], sizeof(ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL)/sizeof(ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL", REG_SMC, 0x11020, 0, &ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL[0], sizeof(ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL)/sizeof(ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL", REG_SMC, 0x11024, 0, &ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL[0], sizeof(ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL)/sizeof(ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL", REG_SMC, 0x11028, 0, &ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL[0], sizeof(ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL)/sizeof(ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL", REG_SMC, 0x1102c, 0, &ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL[0], sizeof(ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL)/sizeof(ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL", REG_SMC, 0x11030, 0, &ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL[0], sizeof(ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL)/sizeof(ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL", REG_SMC, 0x11034, 0, &ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL[0], sizeof(ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL)/sizeof(ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL", REG_SMC, 0x11038, 0, &ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL[0], sizeof(ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL)/sizeof(ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL", REG_SMC, 0x1103c, 0, &ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL[0], sizeof(ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL)/sizeof(ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK", REG_SMC, 0x11040, 0, &ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK[0], sizeof(ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK)/sizeof(ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_NIC400_0_ASIB_0_FN_MOD", REG_SMC, 0x20108, 0, &ixSYSHUB_MMREG_IND_NIC400_0_ASIB_0_FN_MOD[0], sizeof(ixSYSHUB_MMREG_IND_NIC400_0_ASIB_0_FN_MOD)/sizeof(ixSYSHUB_MMREG_IND_NIC400_0_ASIB_0_FN_MOD[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_NIC400_0_AMIB_0_FN_MOD_BM_ISS", REG_SMC, 0x30008, 0, &ixSYSHUB_MMREG_IND_NIC400_0_AMIB_0_FN_MOD_BM_ISS[0], sizeof(ixSYSHUB_MMREG_IND_NIC400_0_AMIB_0_FN_MOD_BM_ISS)/sizeof(ixSYSHUB_MMREG_IND_NIC400_0_AMIB_0_FN_MOD_BM_ISS[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_NIC400_0_AMIB_1_FN_MOD_BM_ISS", REG_SMC, 0x31008, 0, &ixSYSHUB_MMREG_IND_NIC400_0_AMIB_1_FN_MOD_BM_ISS[0], sizeof(ixSYSHUB_MMREG_IND_NIC400_0_AMIB_1_FN_MOD_BM_ISS)/sizeof(ixSYSHUB_MMREG_IND_NIC400_0_AMIB_1_FN_MOD_BM_ISS[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_NIC400_1_ASIB_0_FN_MOD", REG_SMC, 0x40108, 0, &ixSYSHUB_MMREG_IND_NIC400_1_ASIB_0_FN_MOD[0], sizeof(ixSYSHUB_MMREG_IND_NIC400_1_ASIB_0_FN_MOD)/sizeof(ixSYSHUB_MMREG_IND_NIC400_1_ASIB_0_FN_MOD[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_NIC400_1_AMIB_0_FN_MOD", REG_SMC, 0x50008, 0, &ixSYSHUB_MMREG_IND_NIC400_1_AMIB_0_FN_MOD[0], sizeof(ixSYSHUB_MMREG_IND_NIC400_1_AMIB_0_FN_MOD)/sizeof(ixSYSHUB_MMREG_IND_NIC400_1_AMIB_0_FN_MOD[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_NIC400_1_AMIB_1_FN_MOD", REG_SMC, 0x51008, 0, &ixSYSHUB_MMREG_IND_NIC400_1_AMIB_1_FN_MOD[0], sizeof(ixSYSHUB_MMREG_IND_NIC400_1_AMIB_1_FN_MOD)/sizeof(ixSYSHUB_MMREG_IND_NIC400_1_AMIB_1_FN_MOD[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_NIC400_1_AMIB_2_FN_MOD", REG_SMC, 0x52008, 0, &ixSYSHUB_MMREG_IND_NIC400_1_AMIB_2_FN_MOD[0], sizeof(ixSYSHUB_MMREG_IND_NIC400_1_AMIB_2_FN_MOD)/sizeof(ixSYSHUB_MMREG_IND_NIC400_1_AMIB_2_FN_MOD[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_NIC400_2_ASIB_0_FN_MOD", REG_SMC, 0x60108, 0, &ixSYSHUB_MMREG_IND_NIC400_2_ASIB_0_FN_MOD[0], sizeof(ixSYSHUB_MMREG_IND_NIC400_2_ASIB_0_FN_MOD)/sizeof(ixSYSHUB_MMREG_IND_NIC400_2_ASIB_0_FN_MOD[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_NIC400_2_ASIB_1_FN_MOD", REG_SMC, 0x61108, 0, &ixSYSHUB_MMREG_IND_NIC400_2_ASIB_1_FN_MOD[0], sizeof(ixSYSHUB_MMREG_IND_NIC400_2_ASIB_1_FN_MOD)/sizeof(ixSYSHUB_MMREG_IND_NIC400_2_ASIB_1_FN_MOD[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_NIC400_2_ASIB_2_FN_MOD", REG_SMC, 0x62108, 0, &ixSYSHUB_MMREG_IND_NIC400_2_ASIB_2_FN_MOD[0], sizeof(ixSYSHUB_MMREG_IND_NIC400_2_ASIB_2_FN_MOD)/sizeof(ixSYSHUB_MMREG_IND_NIC400_2_ASIB_2_FN_MOD[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_NIC400_2_ASIB_3_FN_MOD", REG_SMC, 0x63108, 0, &ixSYSHUB_MMREG_IND_NIC400_2_ASIB_3_FN_MOD[0], sizeof(ixSYSHUB_MMREG_IND_NIC400_2_ASIB_3_FN_MOD)/sizeof(ixSYSHUB_MMREG_IND_NIC400_2_ASIB_3_FN_MOD[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_NIC400_2_ASIB_4_FN_MOD", REG_SMC, 0x64108, 0, &ixSYSHUB_MMREG_IND_NIC400_2_ASIB_4_FN_MOD[0], sizeof(ixSYSHUB_MMREG_IND_NIC400_2_ASIB_4_FN_MOD)/sizeof(ixSYSHUB_MMREG_IND_NIC400_2_ASIB_4_FN_MOD[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_NIC400_2_AMIB_0_FN_MOD_BM_ISS", REG_SMC, 0x70008, 0, &ixSYSHUB_MMREG_IND_NIC400_2_AMIB_0_FN_MOD_BM_ISS[0], sizeof(ixSYSHUB_MMREG_IND_NIC400_2_AMIB_0_FN_MOD_BM_ISS)/sizeof(ixSYSHUB_MMREG_IND_NIC400_2_AMIB_0_FN_MOD_BM_ISS[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_NIC400_5_ASIB_0_FN_MOD", REG_SMC, 0xc0108, 0, &ixSYSHUB_MMREG_IND_NIC400_5_ASIB_0_FN_MOD[0], sizeof(ixSYSHUB_MMREG_IND_NIC400_5_ASIB_0_FN_MOD)/sizeof(ixSYSHUB_MMREG_IND_NIC400_5_ASIB_0_FN_MOD[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_NIC400_5_ASIB_1_FN_MOD", REG_SMC, 0xc1108, 0, &ixSYSHUB_MMREG_IND_NIC400_5_ASIB_1_FN_MOD[0], sizeof(ixSYSHUB_MMREG_IND_NIC400_5_ASIB_1_FN_MOD)/sizeof(ixSYSHUB_MMREG_IND_NIC400_5_ASIB_1_FN_MOD[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_NIC400_5_ASIB_2_FN_MOD", REG_SMC, 0xc2108, 0, &ixSYSHUB_MMREG_IND_NIC400_5_ASIB_2_FN_MOD[0], sizeof(ixSYSHUB_MMREG_IND_NIC400_5_ASIB_2_FN_MOD)/sizeof(ixSYSHUB_MMREG_IND_NIC400_5_ASIB_2_FN_MOD[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_NIC400_5_ASIB_3_FN_MOD", REG_SMC, 0xc3108, 0, &ixSYSHUB_MMREG_IND_NIC400_5_ASIB_3_FN_MOD[0], sizeof(ixSYSHUB_MMREG_IND_NIC400_5_ASIB_3_FN_MOD)/sizeof(ixSYSHUB_MMREG_IND_NIC400_5_ASIB_3_FN_MOD[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_NIC400_5_ASIB_4_FN_MOD", REG_SMC, 0xc4108, 0, &ixSYSHUB_MMREG_IND_NIC400_5_ASIB_4_FN_MOD[0], sizeof(ixSYSHUB_MMREG_IND_NIC400_5_ASIB_4_FN_MOD)/sizeof(ixSYSHUB_MMREG_IND_NIC400_5_ASIB_4_FN_MOD[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_NIC400_5_AMIB_0_FN_MOD", REG_SMC, 0xd0008, 0, &ixSYSHUB_MMREG_IND_NIC400_5_AMIB_0_FN_MOD[0], sizeof(ixSYSHUB_MMREG_IND_NIC400_5_AMIB_0_FN_MOD)/sizeof(ixSYSHUB_MMREG_IND_NIC400_5_AMIB_0_FN_MOD[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_NIC400_4_ASIB_0_FN_MOD", REG_SMC, 0xe0108, 0, &ixSYSHUB_MMREG_IND_NIC400_4_ASIB_0_FN_MOD[0], sizeof(ixSYSHUB_MMREG_IND_NIC400_4_ASIB_0_FN_MOD)/sizeof(ixSYSHUB_MMREG_IND_NIC400_4_ASIB_0_FN_MOD[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_NIC400_4_ASIB_1_FN_MOD", REG_SMC, 0xe1108, 0, &ixSYSHUB_MMREG_IND_NIC400_4_ASIB_1_FN_MOD[0], sizeof(ixSYSHUB_MMREG_IND_NIC400_4_ASIB_1_FN_MOD)/sizeof(ixSYSHUB_MMREG_IND_NIC400_4_ASIB_1_FN_MOD[0]), 0, 0 }, + { "ixSYSHUB_MMREG_IND_NIC400_4_AMIB_0_FN_MOD", REG_SMC, 0xf0008, 0, &ixSYSHUB_MMREG_IND_NIC400_4_AMIB_0_FN_MOD[0], sizeof(ixSYSHUB_MMREG_IND_NIC400_4_AMIB_0_FN_MOD)/sizeof(ixSYSHUB_MMREG_IND_NIC400_4_AMIB_0_FN_MOD[0]), 0, 0 }, diff --git a/src/lib/ip/sdma041.c b/src/lib/ip/sdma041.c new file mode 100644 index 0000000..3eeea96 --- /dev/null +++ b/src/lib/ip/sdma041.c @@ -0,0 +1,55 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Tom St Denis <tom.stdenis@amd.com> + * + */ +#include "umr.h" + +#include "sdma041_bits.i" + +static const struct umr_reg_soc15 sdma041_registers[] = { +#include "sdma041_regs.i" +}; + +struct umr_ip_block *umr_create_sdma041(struct umr_ip_offsets_soc15 *soc15_offsets, struct umr_options *options) +{ + struct umr_ip_block *ip; + + ip = calloc(1, sizeof *ip); + if (!ip) + return NULL; + + ip->ipname = "sdma041"; + ip->no_regs = sizeof(sdma041_registers)/sizeof(sdma041_registers[0]); + ip->regs = calloc(ip->no_regs, sizeof(ip->regs[0])); + if (!ip->regs) { + free(ip); + return NULL; + } + + if (umr_transfer_soc15_to_reg(options, soc15_offsets, "SDMA0", sdma041_registers, ip)) { + free(ip); + return NULL; + } + + return ip; +} diff --git a/src/lib/ip/sdma041_bits.i b/src/lib/ip/sdma041_bits.i new file mode 100644 index 0000000..a6ecf52 --- /dev/null +++ b/src/lib/ip/sdma041_bits.i @@ -0,0 +1,1138 @@ +static struct umr_bitfield mmSDMA0_UCODE_ADDR[] = { + { "VALUE", 0, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_UCODE_DATA[] = { + { "VALUE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_VM_CNTL[] = { + { "CMD", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_VM_CTX_LO[] = { + { "ADDR", 2, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_VM_CTX_HI[] = { + { "ADDR", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_ACTIVE_FCN_ID[] = { + { "VFID", 0, 3, &umr_bitfield_default }, + { "RESERVED", 4, 30, &umr_bitfield_default }, + { "VF", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_VM_CTX_CNTL[] = { + { "PRIV", 0, 0, &umr_bitfield_default }, + { "VMID", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_VIRT_RESET_REQ[] = { + { "VF", 0, 15, &umr_bitfield_default }, + { "PF", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_CONTEXT_REG_TYPE0[] = { + { "SDMA0_GFX_RB_CNTL", 0, 0, &umr_bitfield_default }, + { "SDMA0_GFX_RB_BASE", 1, 1, &umr_bitfield_default }, + { "SDMA0_GFX_RB_BASE_HI", 2, 2, &umr_bitfield_default }, + { "SDMA0_GFX_RB_RPTR", 3, 3, &umr_bitfield_default }, + { "SDMA0_GFX_RB_RPTR_HI", 4, 4, &umr_bitfield_default }, + { "SDMA0_GFX_RB_WPTR", 5, 5, &umr_bitfield_default }, + { "SDMA0_GFX_RB_WPTR_HI", 6, 6, &umr_bitfield_default }, + { "SDMA0_GFX_RB_WPTR_POLL_CNTL", 7, 7, &umr_bitfield_default }, + { "SDMA0_GFX_RB_RPTR_ADDR_HI", 8, 8, &umr_bitfield_default }, + { "SDMA0_GFX_RB_RPTR_ADDR_LO", 9, 9, &umr_bitfield_default }, + { "SDMA0_GFX_IB_CNTL", 10, 10, &umr_bitfield_default }, + { "SDMA0_GFX_IB_RPTR", 11, 11, &umr_bitfield_default }, + { "SDMA0_GFX_IB_OFFSET", 12, 12, &umr_bitfield_default }, + { "SDMA0_GFX_IB_BASE_LO", 13, 13, &umr_bitfield_default }, + { "SDMA0_GFX_IB_BASE_HI", 14, 14, &umr_bitfield_default }, + { "SDMA0_GFX_IB_SIZE", 15, 15, &umr_bitfield_default }, + { "SDMA0_GFX_SKIP_CNTL", 16, 16, &umr_bitfield_default }, + { "SDMA0_GFX_CONTEXT_STATUS", 17, 17, &umr_bitfield_default }, + { "SDMA0_GFX_DOORBELL", 18, 18, &umr_bitfield_default }, + { "SDMA0_GFX_CONTEXT_CNTL", 19, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_CONTEXT_REG_TYPE1[] = { + { "SDMA0_GFX_STATUS", 8, 8, &umr_bitfield_default }, + { "SDMA0_GFX_DOORBELL_LOG", 9, 9, &umr_bitfield_default }, + { "SDMA0_GFX_WATERMARK", 10, 10, &umr_bitfield_default }, + { "SDMA0_GFX_DOORBELL_OFFSET", 11, 11, &umr_bitfield_default }, + { "SDMA0_GFX_CSA_ADDR_LO", 12, 12, &umr_bitfield_default }, + { "SDMA0_GFX_CSA_ADDR_HI", 13, 13, &umr_bitfield_default }, + { "VOID_REG2", 14, 14, &umr_bitfield_default }, + { "SDMA0_GFX_IB_SUB_REMAIN", 15, 15, &umr_bitfield_default }, + { "SDMA0_GFX_PREEMPT", 16, 16, &umr_bitfield_default }, + { "SDMA0_GFX_DUMMY_REG", 17, 17, &umr_bitfield_default }, + { "SDMA0_GFX_RB_WPTR_POLL_ADDR_HI", 18, 18, &umr_bitfield_default }, + { "SDMA0_GFX_RB_WPTR_POLL_ADDR_LO", 19, 19, &umr_bitfield_default }, + { "SDMA0_GFX_RB_AQL_CNTL", 20, 20, &umr_bitfield_default }, + { "SDMA0_GFX_MINOR_PTR_UPDATE", 21, 21, &umr_bitfield_default }, + { "RESERVED", 22, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_CONTEXT_REG_TYPE2[] = { + { "SDMA0_GFX_MIDCMD_DATA0", 0, 0, &umr_bitfield_default }, + { "SDMA0_GFX_MIDCMD_DATA1", 1, 1, &umr_bitfield_default }, + { "SDMA0_GFX_MIDCMD_DATA2", 2, 2, &umr_bitfield_default }, + { "SDMA0_GFX_MIDCMD_DATA3", 3, 3, &umr_bitfield_default }, + { "SDMA0_GFX_MIDCMD_DATA4", 4, 4, &umr_bitfield_default }, + { "SDMA0_GFX_MIDCMD_DATA5", 5, 5, &umr_bitfield_default }, + { "SDMA0_GFX_MIDCMD_DATA6", 6, 6, &umr_bitfield_default }, + { "SDMA0_GFX_MIDCMD_DATA7", 7, 7, &umr_bitfield_default }, + { "SDMA0_GFX_MIDCMD_DATA8", 8, 8, &umr_bitfield_default }, + { "SDMA0_GFX_MIDCMD_CNTL", 9, 9, &umr_bitfield_default }, + { "RESERVED", 10, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_CONTEXT_REG_TYPE3[] = { + { "RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_PUB_REG_TYPE0[] = { + { "SDMA0_UCODE_ADDR", 0, 0, &umr_bitfield_default }, + { "SDMA0_UCODE_DATA", 1, 1, &umr_bitfield_default }, + { "RESERVED3", 3, 3, &umr_bitfield_default }, + { "SDMA0_VM_CNTL", 4, 4, &umr_bitfield_default }, + { "SDMA0_VM_CTX_LO", 5, 5, &umr_bitfield_default }, + { "SDMA0_VM_CTX_HI", 6, 6, &umr_bitfield_default }, + { "SDMA0_ACTIVE_FCN_ID", 7, 7, &umr_bitfield_default }, + { "SDMA0_VM_CTX_CNTL", 8, 8, &umr_bitfield_default }, + { "SDMA0_VIRT_RESET_REQ", 9, 9, &umr_bitfield_default }, + { "RESERVED10", 10, 10, &umr_bitfield_default }, + { "SDMA0_CONTEXT_REG_TYPE0", 11, 11, &umr_bitfield_default }, + { "SDMA0_CONTEXT_REG_TYPE1", 12, 12, &umr_bitfield_default }, + { "SDMA0_CONTEXT_REG_TYPE2", 13, 13, &umr_bitfield_default }, + { "SDMA0_CONTEXT_REG_TYPE3", 14, 14, &umr_bitfield_default }, + { "SDMA0_PUB_REG_TYPE0", 15, 15, &umr_bitfield_default }, + { "SDMA0_PUB_REG_TYPE1", 16, 16, &umr_bitfield_default }, + { "SDMA0_PUB_REG_TYPE2", 17, 17, &umr_bitfield_default }, + { "SDMA0_PUB_REG_TYPE3", 18, 18, &umr_bitfield_default }, + { "SDMA0_MMHUB_CNTL", 19, 19, &umr_bitfield_default }, + { "RESERVED_FOR_PSPSMU_ACCESS_ONLY", 20, 24, &umr_bitfield_default }, + { "SDMA0_CONTEXT_GROUP_BOUNDARY", 25, 25, &umr_bitfield_default }, + { "SDMA0_POWER_CNTL", 26, 26, &umr_bitfield_default }, + { "SDMA0_CLK_CTRL", 27, 27, &umr_bitfield_default }, + { "SDMA0_CNTL", 28, 28, &umr_bitfield_default }, + { "SDMA0_CHICKEN_BITS", 29, 29, &umr_bitfield_default }, + { "SDMA0_GB_ADDR_CONFIG", 30, 30, &umr_bitfield_default }, + { "SDMA0_GB_ADDR_CONFIG_READ", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_PUB_REG_TYPE1[] = { + { "SDMA0_RB_RPTR_FETCH_HI", 0, 0, &umr_bitfield_default }, + { "SDMA0_SEM_WAIT_FAIL_TIMER_CNTL", 1, 1, &umr_bitfield_default }, + { "SDMA0_RB_RPTR_FETCH", 2, 2, &umr_bitfield_default }, + { "SDMA0_IB_OFFSET_FETCH", 3, 3, &umr_bitfield_default }, + { "SDMA0_PROGRAM", 4, 4, &umr_bitfield_default }, + { "SDMA0_STATUS_REG", 5, 5, &umr_bitfield_default }, + { "SDMA0_STATUS1_REG", 6, 6, &umr_bitfield_default }, + { "SDMA0_RD_BURST_CNTL", 7, 7, &umr_bitfield_default }, + { "SDMA0_HBM_PAGE_CONFIG", 8, 8, &umr_bitfield_default }, + { "SDMA0_UCODE_CHECKSUM", 9, 9, &umr_bitfield_default }, + { "SDMA0_F32_CNTL", 10, 10, &umr_bitfield_default }, + { "SDMA0_FREEZE", 11, 11, &umr_bitfield_default }, + { "SDMA0_PHASE0_QUANTUM", 12, 12, &umr_bitfield_default }, + { "SDMA0_PHASE1_QUANTUM", 13, 13, &umr_bitfield_default }, + { "SDMA_POWER_GATING", 14, 14, &umr_bitfield_default }, + { "SDMA_PGFSM_CONFIG", 15, 15, &umr_bitfield_default }, + { "SDMA_PGFSM_WRITE", 16, 16, &umr_bitfield_default }, + { "SDMA_PGFSM_READ", 17, 17, &umr_bitfield_default }, + { "SDMA0_EDC_CONFIG", 18, 18, &umr_bitfield_default }, + { "SDMA0_BA_THRESHOLD", 19, 19, &umr_bitfield_default }, + { "SDMA0_ID", 20, 20, &umr_bitfield_default }, + { "SDMA0_VERSION", 21, 21, &umr_bitfield_default }, + { "SDMA0_EDC_COUNTER", 22, 22, &umr_bitfield_default }, + { "SDMA0_EDC_COUNTER_CLEAR", 23, 23, &umr_bitfield_default }, + { "SDMA0_STATUS2_REG", 24, 24, &umr_bitfield_default }, + { "SDMA0_ATOMIC_CNTL", 25, 25, &umr_bitfield_default }, + { "SDMA0_ATOMIC_PREOP_LO", 26, 26, &umr_bitfield_default }, + { "SDMA0_ATOMIC_PREOP_HI", 27, 27, &umr_bitfield_default }, + { "SDMA0_UTCL1_CNTL", 28, 28, &umr_bitfield_default }, + { "SDMA0_UTCL1_WATERMK", 29, 29, &umr_bitfield_default }, + { "SDMA0_UTCL1_RD_STATUS", 30, 30, &umr_bitfield_default }, + { "SDMA0_UTCL1_WR_STATUS", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_PUB_REG_TYPE2[] = { + { "SDMA0_UTCL1_INV0", 0, 0, &umr_bitfield_default }, + { "SDMA0_UTCL1_INV1", 1, 1, &umr_bitfield_default }, + { "SDMA0_UTCL1_INV2", 2, 2, &umr_bitfield_default }, + { "SDMA0_UTCL1_RD_XNACK0", 3, 3, &umr_bitfield_default }, + { "SDMA0_UTCL1_RD_XNACK1", 4, 4, &umr_bitfield_default }, + { "SDMA0_UTCL1_WR_XNACK0", 5, 5, &umr_bitfield_default }, + { "SDMA0_UTCL1_WR_XNACK1", 6, 6, &umr_bitfield_default }, + { "SDMA0_UTCL1_TIMEOUT", 7, 7, &umr_bitfield_default }, + { "SDMA0_UTCL1_PAGE", 8, 8, &umr_bitfield_default }, + { "SDMA0_POWER_CNTL_IDLE", 9, 9, &umr_bitfield_default }, + { "SDMA0_RELAX_ORDERING_LUT", 10, 10, &umr_bitfield_default }, + { "SDMA0_CHICKEN_BITS_2", 11, 11, &umr_bitfield_default }, + { "SDMA0_STATUS3_REG", 12, 12, &umr_bitfield_default }, + { "SDMA0_PHYSICAL_ADDR_LO", 13, 13, &umr_bitfield_default }, + { "SDMA0_PHYSICAL_ADDR_HI", 14, 14, &umr_bitfield_default }, + { "SDMA0_ERROR_LOG", 16, 16, &umr_bitfield_default }, + { "SDMA0_PUB_DUMMY_REG0", 17, 17, &umr_bitfield_default }, + { "SDMA0_PUB_DUMMY_REG1", 18, 18, &umr_bitfield_default }, + { "SDMA0_PUB_DUMMY_REG2", 19, 19, &umr_bitfield_default }, + { "SDMA0_PUB_DUMMY_REG3", 20, 20, &umr_bitfield_default }, + { "SDMA0_F32_COUNTER", 21, 21, &umr_bitfield_default }, + { "SDMA0_UNBREAKABLE", 22, 22, &umr_bitfield_default }, + { "SDMA0_PERFMON_CNTL", 23, 23, &umr_bitfield_default }, + { "SDMA0_PERFCOUNTER0_RESULT", 24, 24, &umr_bitfield_default }, + { "SDMA0_PERFCOUNTER1_RESULT", 25, 25, &umr_bitfield_default }, + { "SDMA0_PERFCOUNTER_TAG_DELAY_RANGE", 26, 26, &umr_bitfield_default }, + { "SDMA0_CRD_CNTL", 27, 27, &umr_bitfield_default }, + { "SDMA0_MMHUB_TRUSTLVL", 28, 28, &umr_bitfield_default }, + { "SDMA0_GPU_IOV_VIOLATION_LOG", 29, 29, &umr_bitfield_default }, + { "SDMA0_ULV_CNTL", 30, 30, &umr_bitfield_default }, + { "RESERVED", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_PUB_REG_TYPE3[] = { + { "SDMA0_EA_DBIT_ADDR_DATA", 0, 0, &umr_bitfield_default }, + { "SDMA0_EA_DBIT_ADDR_INDEX", 1, 1, &umr_bitfield_default }, + { "RESERVED", 2, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_MMHUB_CNTL[] = { + { "UNIT_ID", 0, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_CONTEXT_GROUP_BOUNDARY[] = { + { "RESERVED", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_POWER_CNTL[] = { + { "PG_CNTL_ENABLE", 0, 0, &umr_bitfield_default }, + { "EXT_PG_POWER_ON_REQ", 1, 1, &umr_bitfield_default }, + { "EXT_PG_POWER_OFF_REQ", 2, 2, &umr_bitfield_default }, + { "ON_OFF_CONDITION_HOLD_TIME", 3, 7, &umr_bitfield_default }, + { "MEM_POWER_OVERRIDE", 8, 8, &umr_bitfield_default }, + { "MEM_POWER_LS_EN", 9, 9, &umr_bitfield_default }, + { "MEM_POWER_DS_EN", 10, 10, &umr_bitfield_default }, + { "MEM_POWER_SD_EN", 11, 11, &umr_bitfield_default }, + { "MEM_POWER_DELAY", 12, 21, &umr_bitfield_default }, + { "ON_OFF_STATUS_DURATION_TIME", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_CLK_CTRL[] = { + { "ON_DELAY", 0, 3, &umr_bitfield_default }, + { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default }, + { "RESERVED", 12, 23, &umr_bitfield_default }, + { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default }, + { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default }, + { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default }, + { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default }, + { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default }, + { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default }, + { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default }, + { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_CNTL[] = { + { "TRAP_ENABLE", 0, 0, &umr_bitfield_default }, + { "UTC_L1_ENABLE", 1, 1, &umr_bitfield_default }, + { "SEM_WAIT_INT_ENABLE", 2, 2, &umr_bitfield_default }, + { "DATA_SWAP_ENABLE", 3, 3, &umr_bitfield_default }, + { "FENCE_SWAP_ENABLE", 4, 4, &umr_bitfield_default }, + { "MIDCMD_PREEMPT_ENABLE", 5, 5, &umr_bitfield_default }, + { "MIDCMD_WORLDSWITCH_ENABLE", 17, 17, &umr_bitfield_default }, + { "AUTO_CTXSW_ENABLE", 18, 18, &umr_bitfield_default }, + { "CTXEMPTY_INT_ENABLE", 28, 28, &umr_bitfield_default }, + { "FROZEN_INT_ENABLE", 29, 29, &umr_bitfield_default }, + { "IB_PREEMPT_INT_ENABLE", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_CHICKEN_BITS[] = { + { "COPY_EFFICIENCY_ENABLE", 0, 0, &umr_bitfield_default }, + { "STALL_ON_TRANS_FULL_ENABLE", 1, 1, &umr_bitfield_default }, + { "STALL_ON_NO_FREE_DATA_BUFFER_ENABLE", 2, 2, &umr_bitfield_default }, + { "WRITE_BURST_LENGTH", 8, 9, &umr_bitfield_default }, + { "WRITE_BURST_WAIT_CYCLE", 10, 12, &umr_bitfield_default }, + { "COPY_OVERLAP_ENABLE", 16, 16, &umr_bitfield_default }, + { "RAW_CHECK_ENABLE", 17, 17, &umr_bitfield_default }, + { "SRBM_POLL_RETRYING", 20, 20, &umr_bitfield_default }, + { "CG_STATUS_OUTPUT", 23, 23, &umr_bitfield_default }, + { "TIME_BASED_QOS", 25, 25, &umr_bitfield_default }, + { "CE_AFIFO_WATERMARK", 26, 27, &umr_bitfield_default }, + { "CE_DFIFO_WATERMARK", 28, 29, &umr_bitfield_default }, + { "CE_LFIFO_WATERMARK", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_GB_ADDR_CONFIG[] = { + { "NUM_PIPES", 0, 2, &umr_bitfield_default }, + { "PIPE_INTERLEAVE_SIZE", 3, 5, &umr_bitfield_default }, + { "BANK_INTERLEAVE_SIZE", 8, 10, &umr_bitfield_default }, + { "NUM_BANKS", 12, 14, &umr_bitfield_default }, + { "NUM_SHADER_ENGINES", 19, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_GB_ADDR_CONFIG_READ[] = { + { "NUM_PIPES", 0, 2, &umr_bitfield_default }, + { "PIPE_INTERLEAVE_SIZE", 3, 5, &umr_bitfield_default }, + { "BANK_INTERLEAVE_SIZE", 8, 10, &umr_bitfield_default }, + { "NUM_BANKS", 12, 14, &umr_bitfield_default }, + { "NUM_SHADER_ENGINES", 19, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RB_RPTR_FETCH_HI[] = { + { "OFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL[] = { + { "TIMER", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RB_RPTR_FETCH[] = { + { "OFFSET", 2, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_IB_OFFSET_FETCH[] = { + { "OFFSET", 2, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_PROGRAM[] = { + { "STREAM", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_STATUS_REG[] = { + { "IDLE", 0, 0, &umr_bitfield_default }, + { "REG_IDLE", 1, 1, &umr_bitfield_default }, + { "RB_EMPTY", 2, 2, &umr_bitfield_default }, + { "RB_FULL", 3, 3, &umr_bitfield_default }, + { "RB_CMD_IDLE", 4, 4, &umr_bitfield_default }, + { "RB_CMD_FULL", 5, 5, &umr_bitfield_default }, + { "IB_CMD_IDLE", 6, 6, &umr_bitfield_default }, + { "IB_CMD_FULL", 7, 7, &umr_bitfield_default }, + { "BLOCK_IDLE", 8, 8, &umr_bitfield_default }, + { "INSIDE_IB", 9, 9, &umr_bitfield_default }, + { "EX_IDLE", 10, 10, &umr_bitfield_default }, + { "EX_IDLE_POLL_TIMER_EXPIRE", 11, 11, &umr_bitfield_default }, + { "PACKET_READY", 12, 12, &umr_bitfield_default }, + { "MC_WR_IDLE", 13, 13, &umr_bitfield_default }, + { "SRBM_IDLE", 14, 14, &umr_bitfield_default }, + { "CONTEXT_EMPTY", 15, 15, &umr_bitfield_default }, + { "DELTA_RPTR_FULL", 16, 16, &umr_bitfield_default }, + { "RB_MC_RREQ_IDLE", 17, 17, &umr_bitfield_default }, + { "IB_MC_RREQ_IDLE", 18, 18, &umr_bitfield_default }, + { "MC_RD_IDLE", 19, 19, &umr_bitfield_default }, + { "DELTA_RPTR_EMPTY", 20, 20, &umr_bitfield_default }, + { "MC_RD_RET_STALL", 21, 21, &umr_bitfield_default }, + { "MC_RD_NO_POLL_IDLE", 22, 22, &umr_bitfield_default }, + { "PREV_CMD_IDLE", 25, 25, &umr_bitfield_default }, + { "SEM_IDLE", 26, 26, &umr_bitfield_default }, + { "SEM_REQ_STALL", 27, 27, &umr_bitfield_default }, + { "SEM_RESP_STATE", 28, 29, &umr_bitfield_default }, + { "INT_IDLE", 30, 30, &umr_bitfield_default }, + { "INT_REQ_STALL", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_STATUS1_REG[] = { + { "CE_WREQ_IDLE", 0, 0, &umr_bitfield_default }, + { "CE_WR_IDLE", 1, 1, &umr_bitfield_default }, + { "CE_SPLIT_IDLE", 2, 2, &umr_bitfield_default }, + { "CE_RREQ_IDLE", 3, 3, &umr_bitfield_default }, + { "CE_OUT_IDLE", 4, 4, &umr_bitfield_default }, + { "CE_IN_IDLE", 5, 5, &umr_bitfield_default }, + { "CE_DST_IDLE", 6, 6, &umr_bitfield_default }, + { "CE_CMD_IDLE", 9, 9, &umr_bitfield_default }, + { "CE_AFIFO_FULL", 10, 10, &umr_bitfield_default }, + { "CE_INFO_FULL", 13, 13, &umr_bitfield_default }, + { "CE_INFO1_FULL", 14, 14, &umr_bitfield_default }, + { "EX_START", 15, 15, &umr_bitfield_default }, + { "CE_RD_STALL", 17, 17, &umr_bitfield_default }, + { "CE_WR_STALL", 18, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RD_BURST_CNTL[] = { + { "RD_BURST", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_HBM_PAGE_CONFIG[] = { + { "PAGE_SIZE_EXPONENT", 0, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_UCODE_CHECKSUM[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_F32_CNTL[] = { + { "HALT", 0, 0, &umr_bitfield_default }, + { "STEP", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_FREEZE[] = { + { "PREEMPT", 0, 0, &umr_bitfield_default }, + { "FREEZE", 4, 4, &umr_bitfield_default }, + { "FROZEN", 5, 5, &umr_bitfield_default }, + { "F32_FREEZE", 6, 6, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_PHASE0_QUANTUM[] = { + { "UNIT", 0, 3, &umr_bitfield_default }, + { "VALUE", 8, 23, &umr_bitfield_default }, + { "PREFER", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_PHASE1_QUANTUM[] = { + { "UNIT", 0, 3, &umr_bitfield_default }, + { "VALUE", 8, 23, &umr_bitfield_default }, + { "PREFER", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA_POWER_GATING[] = { + { "SDMA0_POWER_OFF_CONDITION", 0, 0, &umr_bitfield_default }, + { "SDMA0_POWER_ON_CONDITION", 1, 1, &umr_bitfield_default }, + { "SDMA0_POWER_OFF_REQ", 2, 2, &umr_bitfield_default }, + { "SDMA0_POWER_ON_REQ", 3, 3, &umr_bitfield_default }, + { "PG_CNTL_STATUS", 4, 5, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA_PGFSM_CONFIG[] = { + { "FSM_ADDR", 0, 7, &umr_bitfield_default }, + { "POWER_DOWN", 8, 8, &umr_bitfield_default }, + { "POWER_UP", 9, 9, &umr_bitfield_default }, + { "P1_SELECT", 10, 10, &umr_bitfield_default }, + { "P2_SELECT", 11, 11, &umr_bitfield_default }, + { "WRITE", 12, 12, &umr_bitfield_default }, + { "READ", 13, 13, &umr_bitfield_default }, + { "SRBM_OVERRIDE", 27, 27, &umr_bitfield_default }, + { "REG_ADDR", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA_PGFSM_WRITE[] = { + { "VALUE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA_PGFSM_READ[] = { + { "VALUE", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_EDC_CONFIG[] = { + { "DIS_EDC", 1, 1, &umr_bitfield_default }, + { "ECC_INT_ENABLE", 2, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_BA_THRESHOLD[] = { + { "READ_THRES", 0, 9, &umr_bitfield_default }, + { "WRITE_THRES", 16, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_ID[] = { + { "DEVICE_ID", 0, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_VERSION[] = { + { "MINVER", 0, 6, &umr_bitfield_default }, + { "MAJVER", 8, 14, &umr_bitfield_default }, + { "REV", 16, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_EDC_COUNTER[] = { + { "SDMA_UCODE_BUF_DED", 0, 0, &umr_bitfield_default }, + { "SDMA_UCODE_BUF_SEC", 1, 1, &umr_bitfield_default }, + { "SDMA_RB_CMD_BUF_SED", 2, 2, &umr_bitfield_default }, + { "SDMA_IB_CMD_BUF_SED", 3, 3, &umr_bitfield_default }, + { "SDMA_UTCL1_RD_FIFO_SED", 4, 4, &umr_bitfield_default }, + { "SDMA_UTCL1_RDBST_FIFO_SED", 5, 5, &umr_bitfield_default }, + { "SDMA_DATA_LUT_FIFO_SED", 6, 6, &umr_bitfield_default }, + { "SDMA_MBANK_DATA_BUF0_SED", 7, 7, &umr_bitfield_default }, + { "SDMA_MBANK_DATA_BUF1_SED", 8, 8, &umr_bitfield_default }, + { "SDMA_MBANK_DATA_BUF2_SED", 9, 9, &umr_bitfield_default }, + { "SDMA_MBANK_DATA_BUF3_SED", 10, 10, &umr_bitfield_default }, + { "SDMA_MBANK_DATA_BUF4_SED", 11, 11, &umr_bitfield_default }, + { "SDMA_MBANK_DATA_BUF5_SED", 12, 12, &umr_bitfield_default }, + { "SDMA_MBANK_DATA_BUF6_SED", 13, 13, &umr_bitfield_default }, + { "SDMA_MBANK_DATA_BUF7_SED", 14, 14, &umr_bitfield_default }, + { "SDMA_SPLIT_DAT_BUF_SED", 15, 15, &umr_bitfield_default }, + { "SDMA_MC_WR_ADDR_FIFO_SED", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_EDC_COUNTER_CLEAR[] = { + { "DUMMY", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_STATUS2_REG[] = { + { "ID", 0, 1, &umr_bitfield_default }, + { "F32_INSTR_PTR", 2, 11, &umr_bitfield_default }, + { "CMD_OP", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_ATOMIC_CNTL[] = { + { "LOOP_TIMER", 0, 30, &umr_bitfield_default }, + { "ATOMIC_RTN_INT_ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_ATOMIC_PREOP_LO[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_ATOMIC_PREOP_HI[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_UTCL1_CNTL[] = { + { "REDO_ENABLE", 0, 0, &umr_bitfield_default }, + { "REDO_DELAY", 1, 10, &umr_bitfield_default }, + { "REDO_WATERMK", 11, 13, &umr_bitfield_default }, + { "INVACK_DELAY", 14, 23, &umr_bitfield_default }, + { "REQL2_CREDIT", 24, 28, &umr_bitfield_default }, + { "VADDR_WATERMK", 29, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_UTCL1_WATERMK[] = { + { "REQMC_WATERMK", 0, 9, &umr_bitfield_default }, + { "REQPG_WATERMK", 10, 17, &umr_bitfield_default }, + { "INVREQ_WATERMK", 18, 25, &umr_bitfield_default }, + { "XNACK_WATERMK", 26, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_UTCL1_RD_STATUS[] = { + { "RQMC_RET_ADDR_FIFO_EMPTY", 0, 0, &umr_bitfield_default }, + { "RQMC_REQ_FIFO_EMPTY", 1, 1, &umr_bitfield_default }, + { "RTPG_RET_BUF_EMPTY", 2, 2, &umr_bitfield_default }, + { "RTPG_VADDR_FIFO_EMPTY", 3, 3, &umr_bitfield_default }, + { "RQPG_HEAD_VIRT_FIFO_EMPTY", 4, 4, &umr_bitfield_default }, + { "RQPG_REDO_FIFO_EMPTY", 5, 5, &umr_bitfield_default }, + { "RQPG_REQPAGE_FIFO_EMPTY", 6, 6, &umr_bitfield_default }, + { "RQPG_XNACK_FIFO_EMPTY", 7, 7, &umr_bitfield_default }, + { "RQPG_INVREQ_FIFO_EMPTY", 8, 8, &umr_bitfield_default }, + { "RQMC_RET_ADDR_FIFO_FULL", 9, 9, &umr_bitfield_default }, + { "RQMC_REQ_FIFO_FULL", 10, 10, &umr_bitfield_default }, + { "RTPG_RET_BUF_FULL", 11, 11, &umr_bitfield_default }, + { "RTPG_VADDR_FIFO_FULL", 12, 12, &umr_bitfield_default }, + { "RQPG_HEAD_VIRT_FIFO_FULL", 13, 13, &umr_bitfield_default }, + { "RQPG_REDO_FIFO_FULL", 14, 14, &umr_bitfield_default }, + { "RQPG_REQPAGE_FIFO_FULL", 15, 15, &umr_bitfield_default }, + { "RQPG_XNACK_FIFO_FULL", 16, 16, &umr_bitfield_default }, + { "RQPG_INVREQ_FIFO_FULL", 17, 17, &umr_bitfield_default }, + { "PAGE_FAULT", 18, 18, &umr_bitfield_default }, + { "PAGE_NULL", 19, 19, &umr_bitfield_default }, + { "REQL2_IDLE", 20, 20, &umr_bitfield_default }, + { "CE_L1_STALL", 21, 21, &umr_bitfield_default }, + { "NEXT_RD_VECTOR", 22, 25, &umr_bitfield_default }, + { "MERGE_STATE", 26, 28, &umr_bitfield_default }, + { "ADDR_RD_RTR", 29, 29, &umr_bitfield_default }, + { "WPTR_POLLING", 30, 30, &umr_bitfield_default }, + { "INVREQ_SIZE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_UTCL1_WR_STATUS[] = { + { "RQMC_RET_ADDR_FIFO_EMPTY", 0, 0, &umr_bitfield_default }, + { "RQMC_REQ_FIFO_EMPTY", 1, 1, &umr_bitfield_default }, + { "RTPG_RET_BUF_EMPTY", 2, 2, &umr_bitfield_default }, + { "RTPG_VADDR_FIFO_EMPTY", 3, 3, &umr_bitfield_default }, + { "RQPG_HEAD_VIRT_FIFO_EMPTY", 4, 4, &umr_bitfield_default }, + { "RQPG_REDO_FIFO_EMPTY", 5, 5, &umr_bitfield_default }, + { "RQPG_REQPAGE_FIFO_EMPTY", 6, 6, &umr_bitfield_default }, + { "RQPG_XNACK_FIFO_EMPTY", 7, 7, &umr_bitfield_default }, + { "RQPG_INVREQ_FIFO_EMPTY", 8, 8, &umr_bitfield_default }, + { "RQMC_RET_ADDR_FIFO_FULL", 9, 9, &umr_bitfield_default }, + { "RQMC_REQ_FIFO_FULL", 10, 10, &umr_bitfield_default }, + { "RTPG_RET_BUF_FULL", 11, 11, &umr_bitfield_default }, + { "RTPG_VADDR_FIFO_FULL", 12, 12, &umr_bitfield_default }, + { "RQPG_HEAD_VIRT_FIFO_FULL", 13, 13, &umr_bitfield_default }, + { "RQPG_REDO_FIFO_FULL", 14, 14, &umr_bitfield_default }, + { "RQPG_REQPAGE_FIFO_FULL", 15, 15, &umr_bitfield_default }, + { "RQPG_XNACK_FIFO_FULL", 16, 16, &umr_bitfield_default }, + { "RQPG_INVREQ_FIFO_FULL", 17, 17, &umr_bitfield_default }, + { "PAGE_FAULT", 18, 18, &umr_bitfield_default }, + { "PAGE_NULL", 19, 19, &umr_bitfield_default }, + { "REQL2_IDLE", 20, 20, &umr_bitfield_default }, + { "F32_WR_RTR", 21, 21, &umr_bitfield_default }, + { "NEXT_WR_VECTOR", 22, 24, &umr_bitfield_default }, + { "MERGE_STATE", 25, 27, &umr_bitfield_default }, + { "RPTR_DATA_FIFO_EMPTY", 28, 28, &umr_bitfield_default }, + { "RPTR_DATA_FIFO_FULL", 29, 29, &umr_bitfield_default }, + { "WRREQ_DATA_FIFO_EMPTY", 30, 30, &umr_bitfield_default }, + { "WRREQ_DATA_FIFO_FULL", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_UTCL1_INV0[] = { + { "INV_MIDDLE", 0, 0, &umr_bitfield_default }, + { "RD_TIMEOUT", 1, 1, &umr_bitfield_default }, + { "WR_TIMEOUT", 2, 2, &umr_bitfield_default }, + { "RD_IN_INVADR", 3, 3, &umr_bitfield_default }, + { "WR_IN_INVADR", 4, 4, &umr_bitfield_default }, + { "PAGE_NULL_SW", 5, 5, &umr_bitfield_default }, + { "XNACK_IS_INVADR", 6, 6, &umr_bitfield_default }, + { "INVREQ_ENABLE", 7, 7, &umr_bitfield_default }, + { "NACK_TIMEOUT_SW", 8, 8, &umr_bitfield_default }, + { "NFLUSH_INV_IDLE", 9, 9, &umr_bitfield_default }, + { "FLUSH_INV_IDLE", 10, 10, &umr_bitfield_default }, + { "INV_FLUSHTYPE", 11, 11, &umr_bitfield_default }, + { "INV_VMID_VEC", 12, 27, &umr_bitfield_default }, + { "INV_ADDR_HI", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_UTCL1_INV1[] = { + { "INV_ADDR_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_UTCL1_INV2[] = { + { "INV_NFLUSH_VMID_VEC", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_UTCL1_RD_XNACK0[] = { + { "XNACK_ADDR_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_UTCL1_RD_XNACK1[] = { + { "XNACK_ADDR_HI", 0, 3, &umr_bitfield_default }, + { "XNACK_VMID", 4, 7, &umr_bitfield_default }, + { "XNACK_VECTOR", 8, 25, &umr_bitfield_default }, + { "IS_XNACK", 26, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_UTCL1_WR_XNACK0[] = { + { "XNACK_ADDR_LO", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_UTCL1_WR_XNACK1[] = { + { "XNACK_ADDR_HI", 0, 3, &umr_bitfield_default }, + { "XNACK_VMID", 4, 7, &umr_bitfield_default }, + { "XNACK_VECTOR", 8, 25, &umr_bitfield_default }, + { "IS_XNACK", 26, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_UTCL1_TIMEOUT[] = { + { "RD_XNACK_LIMIT", 0, 15, &umr_bitfield_default }, + { "WR_XNACK_LIMIT", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_UTCL1_PAGE[] = { + { "VM_HOLE", 0, 0, &umr_bitfield_default }, + { "REQ_TYPE", 1, 4, &umr_bitfield_default }, + { "USE_MTYPE", 6, 8, &umr_bitfield_default }, + { "USE_PT_SNOOP", 9, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_POWER_CNTL_IDLE[] = { + { "DELAY0", 0, 15, &umr_bitfield_default }, + { "DELAY1", 16, 23, &umr_bitfield_default }, + { "DELAY2", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RELAX_ORDERING_LUT[] = { + { "RESERVED0", 0, 0, &umr_bitfield_default }, + { "COPY", 1, 1, &umr_bitfield_default }, + { "WRITE", 2, 2, &umr_bitfield_default }, + { "RESERVED3", 3, 3, &umr_bitfield_default }, + { "RESERVED4", 4, 4, &umr_bitfield_default }, + { "FENCE", 5, 5, &umr_bitfield_default }, + { "RESERVED76", 6, 7, &umr_bitfield_default }, + { "POLL_MEM", 8, 8, &umr_bitfield_default }, + { "COND_EXE", 9, 9, &umr_bitfield_default }, + { "ATOMIC", 10, 10, &umr_bitfield_default }, + { "CONST_FILL", 11, 11, &umr_bitfield_default }, + { "PTEPDE", 12, 12, &umr_bitfield_default }, + { "TIMESTAMP", 13, 13, &umr_bitfield_default }, + { "RESERVED", 14, 26, &umr_bitfield_default }, + { "WORLD_SWITCH", 27, 27, &umr_bitfield_default }, + { "RPTR_WRB", 28, 28, &umr_bitfield_default }, + { "WPTR_POLL", 29, 29, &umr_bitfield_default }, + { "IB_FETCH", 30, 30, &umr_bitfield_default }, + { "RB_FETCH", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_CHICKEN_BITS_2[] = { + { "F32_CMD_PROC_DELAY", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_STATUS3_REG[] = { + { "CMD_OP_STATUS", 0, 15, &umr_bitfield_default }, + { "PREV_VM_CMD", 16, 19, &umr_bitfield_default }, + { "EXCEPTION_IDLE", 20, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_PHYSICAL_ADDR_LO[] = { + { "D_VALID", 0, 0, &umr_bitfield_default }, + { "DIRTY", 1, 1, &umr_bitfield_default }, + { "PHY_VALID", 2, 2, &umr_bitfield_default }, + { "ADDR", 12, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_PHYSICAL_ADDR_HI[] = { + { "ADDR", 0, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_ERROR_LOG[] = { + { "OVERRIDE", 0, 15, &umr_bitfield_default }, + { "STATUS", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_PUB_DUMMY_REG0[] = { + { "VALUE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_PUB_DUMMY_REG1[] = { + { "VALUE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_PUB_DUMMY_REG2[] = { + { "VALUE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_PUB_DUMMY_REG3[] = { + { "VALUE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_F32_COUNTER[] = { + { "VALUE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_UNBREAKABLE[] = { + { "VALUE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_PERFMON_CNTL[] = { + { "PERF_ENABLE0", 0, 0, &umr_bitfield_default }, + { "PERF_CLEAR0", 1, 1, &umr_bitfield_default }, + { "PERF_SEL0", 2, 9, &umr_bitfield_default }, + { "PERF_ENABLE1", 10, 10, &umr_bitfield_default }, + { "PERF_CLEAR1", 11, 11, &umr_bitfield_default }, + { "PERF_SEL1", 12, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_PERFCOUNTER0_RESULT[] = { + { "PERF_COUNT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_PERFCOUNTER1_RESULT[] = { + { "PERF_COUNT", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE[] = { + { "RANGE_LOW", 0, 13, &umr_bitfield_default }, + { "RANGE_HIGH", 14, 27, &umr_bitfield_default }, + { "SELECT_RW", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_CRD_CNTL[] = { + { "MC_WRREQ_CREDIT", 7, 12, &umr_bitfield_default }, + { "MC_RDREQ_CREDIT", 13, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_MMHUB_TRUSTLVL[] = { + { "SECFLAG0", 0, 2, &umr_bitfield_default }, + { "SECFLAG1", 3, 5, &umr_bitfield_default }, + { "SECFLAG2", 6, 8, &umr_bitfield_default }, + { "SECFLAG3", 9, 11, &umr_bitfield_default }, + { "SECFLAG4", 12, 14, &umr_bitfield_default }, + { "SECFLAG5", 15, 17, &umr_bitfield_default }, + { "SECFLAG6", 18, 20, &umr_bitfield_default }, + { "SECFLAG7", 21, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_GPU_IOV_VIOLATION_LOG[] = { + { "VIOLATION_STATUS", 0, 0, &umr_bitfield_default }, + { "MULTIPLE_VIOLATION_STATUS", 1, 1, &umr_bitfield_default }, + { "ADDRESS", 2, 17, &umr_bitfield_default }, + { "WRITE_OPERATION", 18, 18, &umr_bitfield_default }, + { "VF", 19, 19, &umr_bitfield_default }, + { "VFID", 20, 23, &umr_bitfield_default }, + { "INITIATOR_ID", 24, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_ULV_CNTL[] = { + { "HYSTERESIS", 0, 4, &umr_bitfield_default }, + { "ENTER_ULV_INT", 29, 29, &umr_bitfield_default }, + { "EXIT_ULV_INT", 30, 30, &umr_bitfield_default }, + { "ULV_STATUS", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_EA_DBIT_ADDR_DATA[] = { + { "VALUE", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_EA_DBIT_ADDR_INDEX[] = { + { "VALUE", 0, 2, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_GFX_RB_CNTL[] = { + { "RB_ENABLE", 0, 0, &umr_bitfield_default }, + { "RB_SIZE", 1, 6, &umr_bitfield_default }, + { "RB_SWAP_ENABLE", 9, 9, &umr_bitfield_default }, + { "RPTR_WRITEBACK_ENABLE", 12, 12, &umr_bitfield_default }, + { "RPTR_WRITEBACK_SWAP_ENABLE", 13, 13, &umr_bitfield_default }, + { "RPTR_WRITEBACK_TIMER", 16, 20, &umr_bitfield_default }, + { "RB_PRIV", 23, 23, &umr_bitfield_default }, + { "RB_VMID", 24, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_GFX_RB_BASE[] = { + { "ADDR", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_GFX_RB_BASE_HI[] = { + { "ADDR", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_GFX_RB_RPTR[] = { + { "OFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_GFX_RB_RPTR_HI[] = { + { "OFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_GFX_RB_WPTR[] = { + { "OFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_GFX_RB_WPTR_HI[] = { + { "OFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_GFX_RB_WPTR_POLL_CNTL[] = { + { "ENABLE", 0, 0, &umr_bitfield_default }, + { "SWAP_ENABLE", 1, 1, &umr_bitfield_default }, + { "F32_POLL_ENABLE", 2, 2, &umr_bitfield_default }, + { "FREQUENCY", 4, 15, &umr_bitfield_default }, + { "IDLE_POLL_COUNT", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_GFX_RB_RPTR_ADDR_HI[] = { + { "ADDR", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_GFX_RB_RPTR_ADDR_LO[] = { + { "ADDR", 2, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_GFX_IB_CNTL[] = { + { "IB_ENABLE", 0, 0, &umr_bitfield_default }, + { "IB_SWAP_ENABLE", 4, 4, &umr_bitfield_default }, + { "SWITCH_INSIDE_IB", 8, 8, &umr_bitfield_default }, + { "CMD_VMID", 16, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_GFX_IB_RPTR[] = { + { "OFFSET", 2, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_GFX_IB_OFFSET[] = { + { "OFFSET", 2, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_GFX_IB_BASE_LO[] = { + { "ADDR", 5, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_GFX_IB_BASE_HI[] = { + { "ADDR", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_GFX_IB_SIZE[] = { + { "SIZE", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_GFX_SKIP_CNTL[] = { + { "SKIP_COUNT", 0, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_GFX_CONTEXT_STATUS[] = { + { "SELECTED", 0, 0, &umr_bitfield_default }, + { "IDLE", 2, 2, &umr_bitfield_default }, + { "EXPIRED", 3, 3, &umr_bitfield_default }, + { "EXCEPTION", 4, 6, &umr_bitfield_default }, + { "CTXSW_ABLE", 7, 7, &umr_bitfield_default }, + { "CTXSW_READY", 8, 8, &umr_bitfield_default }, + { "PREEMPTED", 9, 9, &umr_bitfield_default }, + { "PREEMPT_DISABLE", 10, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_GFX_DOORBELL[] = { + { "ENABLE", 28, 28, &umr_bitfield_default }, + { "CAPTURED", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_GFX_CONTEXT_CNTL[] = { + { "RESUME_CTX", 16, 16, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_GFX_STATUS[] = { + { "WPTR_UPDATE_FAIL_COUNT", 0, 7, &umr_bitfield_default }, + { "WPTR_UPDATE_PENDING", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_GFX_DOORBELL_LOG[] = { + { "BE_ERROR", 0, 0, &umr_bitfield_default }, + { "DATA", 2, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_GFX_WATERMARK[] = { + { "RD_OUTSTANDING", 0, 11, &umr_bitfield_default }, + { "WR_OUTSTANDING", 16, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_GFX_DOORBELL_OFFSET[] = { + { "OFFSET", 2, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_GFX_CSA_ADDR_LO[] = { + { "ADDR", 2, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_GFX_CSA_ADDR_HI[] = { + { "ADDR", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_GFX_IB_SUB_REMAIN[] = { + { "SIZE", 0, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_GFX_PREEMPT[] = { + { "IB_PREEMPT", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_GFX_DUMMY_REG[] = { + { "DUMMY", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI[] = { + { "ADDR", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO[] = { + { "ADDR", 2, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_GFX_RB_AQL_CNTL[] = { + { "AQL_ENABLE", 0, 0, &umr_bitfield_default }, + { "AQL_PACKET_SIZE", 1, 7, &umr_bitfield_default }, + { "PACKET_STEP", 8, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_GFX_MINOR_PTR_UPDATE[] = { + { "ENABLE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_GFX_MIDCMD_DATA0[] = { + { "DATA0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_GFX_MIDCMD_DATA1[] = { + { "DATA1", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_GFX_MIDCMD_DATA2[] = { + { "DATA2", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_GFX_MIDCMD_DATA3[] = { + { "DATA3", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_GFX_MIDCMD_DATA4[] = { + { "DATA4", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_GFX_MIDCMD_DATA5[] = { + { "DATA5", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_GFX_MIDCMD_DATA6[] = { + { "DATA6", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_GFX_MIDCMD_DATA7[] = { + { "DATA7", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_GFX_MIDCMD_DATA8[] = { + { "DATA8", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_GFX_MIDCMD_CNTL[] = { + { "DATA_VALID", 0, 0, &umr_bitfield_default }, + { "COPY_MODE", 1, 1, &umr_bitfield_default }, + { "SPLIT_STATE", 4, 7, &umr_bitfield_default }, + { "ALLOW_PREEMPT", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC0_RB_CNTL[] = { + { "RB_ENABLE", 0, 0, &umr_bitfield_default }, + { "RB_SIZE", 1, 6, &umr_bitfield_default }, + { "RB_SWAP_ENABLE", 9, 9, &umr_bitfield_default }, + { "RPTR_WRITEBACK_ENABLE", 12, 12, &umr_bitfield_default }, + { "RPTR_WRITEBACK_SWAP_ENABLE", 13, 13, &umr_bitfield_default }, + { "RPTR_WRITEBACK_TIMER", 16, 20, &umr_bitfield_default }, + { "RB_PRIV", 23, 23, &umr_bitfield_default }, + { "RB_VMID", 24, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC0_RB_BASE[] = { + { "ADDR", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC0_RB_BASE_HI[] = { + { "ADDR", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC0_RB_RPTR[] = { + { "OFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC0_RB_RPTR_HI[] = { + { "OFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC0_RB_WPTR[] = { + { "OFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC0_RB_WPTR_HI[] = { + { "OFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC0_RB_WPTR_POLL_CNTL[] = { + { "ENABLE", 0, 0, &umr_bitfield_default }, + { "SWAP_ENABLE", 1, 1, &umr_bitfield_default }, + { "F32_POLL_ENABLE", 2, 2, &umr_bitfield_default }, + { "FREQUENCY", 4, 15, &umr_bitfield_default }, + { "IDLE_POLL_COUNT", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC0_RB_RPTR_ADDR_HI[] = { + { "ADDR", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC0_RB_RPTR_ADDR_LO[] = { + { "ADDR", 2, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC0_IB_CNTL[] = { + { "IB_ENABLE", 0, 0, &umr_bitfield_default }, + { "IB_SWAP_ENABLE", 4, 4, &umr_bitfield_default }, + { "SWITCH_INSIDE_IB", 8, 8, &umr_bitfield_default }, + { "CMD_VMID", 16, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC0_IB_RPTR[] = { + { "OFFSET", 2, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC0_IB_OFFSET[] = { + { "OFFSET", 2, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC0_IB_BASE_LO[] = { + { "ADDR", 5, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC0_IB_BASE_HI[] = { + { "ADDR", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC0_IB_SIZE[] = { + { "SIZE", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC0_SKIP_CNTL[] = { + { "SKIP_COUNT", 0, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC0_CONTEXT_STATUS[] = { + { "SELECTED", 0, 0, &umr_bitfield_default }, + { "IDLE", 2, 2, &umr_bitfield_default }, + { "EXPIRED", 3, 3, &umr_bitfield_default }, + { "EXCEPTION", 4, 6, &umr_bitfield_default }, + { "CTXSW_ABLE", 7, 7, &umr_bitfield_default }, + { "CTXSW_READY", 8, 8, &umr_bitfield_default }, + { "PREEMPTED", 9, 9, &umr_bitfield_default }, + { "PREEMPT_DISABLE", 10, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC0_DOORBELL[] = { + { "ENABLE", 28, 28, &umr_bitfield_default }, + { "CAPTURED", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC0_STATUS[] = { + { "WPTR_UPDATE_FAIL_COUNT", 0, 7, &umr_bitfield_default }, + { "WPTR_UPDATE_PENDING", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC0_DOORBELL_LOG[] = { + { "BE_ERROR", 0, 0, &umr_bitfield_default }, + { "DATA", 2, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC0_WATERMARK[] = { + { "RD_OUTSTANDING", 0, 11, &umr_bitfield_default }, + { "WR_OUTSTANDING", 16, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC0_DOORBELL_OFFSET[] = { + { "OFFSET", 2, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC0_CSA_ADDR_LO[] = { + { "ADDR", 2, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC0_CSA_ADDR_HI[] = { + { "ADDR", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC0_IB_SUB_REMAIN[] = { + { "SIZE", 0, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC0_PREEMPT[] = { + { "IB_PREEMPT", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC0_DUMMY_REG[] = { + { "DUMMY", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI[] = { + { "ADDR", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO[] = { + { "ADDR", 2, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC0_RB_AQL_CNTL[] = { + { "AQL_ENABLE", 0, 0, &umr_bitfield_default }, + { "AQL_PACKET_SIZE", 1, 7, &umr_bitfield_default }, + { "PACKET_STEP", 8, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC0_MINOR_PTR_UPDATE[] = { + { "ENABLE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC0_MIDCMD_DATA0[] = { + { "DATA0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC0_MIDCMD_DATA1[] = { + { "DATA1", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC0_MIDCMD_DATA2[] = { + { "DATA2", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC0_MIDCMD_DATA3[] = { + { "DATA3", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC0_MIDCMD_DATA4[] = { + { "DATA4", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC0_MIDCMD_DATA5[] = { + { "DATA5", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC0_MIDCMD_DATA6[] = { + { "DATA6", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC0_MIDCMD_DATA7[] = { + { "DATA7", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC0_MIDCMD_DATA8[] = { + { "DATA8", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC0_MIDCMD_CNTL[] = { + { "DATA_VALID", 0, 0, &umr_bitfield_default }, + { "COPY_MODE", 1, 1, &umr_bitfield_default }, + { "SPLIT_STATE", 4, 7, &umr_bitfield_default }, + { "ALLOW_PREEMPT", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC1_RB_CNTL[] = { + { "RB_ENABLE", 0, 0, &umr_bitfield_default }, + { "RB_SIZE", 1, 6, &umr_bitfield_default }, + { "RB_SWAP_ENABLE", 9, 9, &umr_bitfield_default }, + { "RPTR_WRITEBACK_ENABLE", 12, 12, &umr_bitfield_default }, + { "RPTR_WRITEBACK_SWAP_ENABLE", 13, 13, &umr_bitfield_default }, + { "RPTR_WRITEBACK_TIMER", 16, 20, &umr_bitfield_default }, + { "RB_PRIV", 23, 23, &umr_bitfield_default }, + { "RB_VMID", 24, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC1_RB_BASE[] = { + { "ADDR", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC1_RB_BASE_HI[] = { + { "ADDR", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC1_RB_RPTR[] = { + { "OFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC1_RB_RPTR_HI[] = { + { "OFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC1_RB_WPTR[] = { + { "OFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC1_RB_WPTR_HI[] = { + { "OFFSET", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC1_RB_WPTR_POLL_CNTL[] = { + { "ENABLE", 0, 0, &umr_bitfield_default }, + { "SWAP_ENABLE", 1, 1, &umr_bitfield_default }, + { "F32_POLL_ENABLE", 2, 2, &umr_bitfield_default }, + { "FREQUENCY", 4, 15, &umr_bitfield_default }, + { "IDLE_POLL_COUNT", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC1_RB_RPTR_ADDR_HI[] = { + { "ADDR", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC1_RB_RPTR_ADDR_LO[] = { + { "ADDR", 2, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC1_IB_CNTL[] = { + { "IB_ENABLE", 0, 0, &umr_bitfield_default }, + { "IB_SWAP_ENABLE", 4, 4, &umr_bitfield_default }, + { "SWITCH_INSIDE_IB", 8, 8, &umr_bitfield_default }, + { "CMD_VMID", 16, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC1_IB_RPTR[] = { + { "OFFSET", 2, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC1_IB_OFFSET[] = { + { "OFFSET", 2, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC1_IB_BASE_LO[] = { + { "ADDR", 5, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC1_IB_BASE_HI[] = { + { "ADDR", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC1_IB_SIZE[] = { + { "SIZE", 0, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC1_SKIP_CNTL[] = { + { "SKIP_COUNT", 0, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC1_CONTEXT_STATUS[] = { + { "SELECTED", 0, 0, &umr_bitfield_default }, + { "IDLE", 2, 2, &umr_bitfield_default }, + { "EXPIRED", 3, 3, &umr_bitfield_default }, + { "EXCEPTION", 4, 6, &umr_bitfield_default }, + { "CTXSW_ABLE", 7, 7, &umr_bitfield_default }, + { "CTXSW_READY", 8, 8, &umr_bitfield_default }, + { "PREEMPTED", 9, 9, &umr_bitfield_default }, + { "PREEMPT_DISABLE", 10, 10, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC1_DOORBELL[] = { + { "ENABLE", 28, 28, &umr_bitfield_default }, + { "CAPTURED", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC1_STATUS[] = { + { "WPTR_UPDATE_FAIL_COUNT", 0, 7, &umr_bitfield_default }, + { "WPTR_UPDATE_PENDING", 8, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC1_DOORBELL_LOG[] = { + { "BE_ERROR", 0, 0, &umr_bitfield_default }, + { "DATA", 2, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC1_WATERMARK[] = { + { "RD_OUTSTANDING", 0, 11, &umr_bitfield_default }, + { "WR_OUTSTANDING", 16, 25, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC1_DOORBELL_OFFSET[] = { + { "OFFSET", 2, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC1_CSA_ADDR_LO[] = { + { "ADDR", 2, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC1_CSA_ADDR_HI[] = { + { "ADDR", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC1_IB_SUB_REMAIN[] = { + { "SIZE", 0, 13, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC1_PREEMPT[] = { + { "IB_PREEMPT", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC1_DUMMY_REG[] = { + { "DUMMY", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI[] = { + { "ADDR", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO[] = { + { "ADDR", 2, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC1_RB_AQL_CNTL[] = { + { "AQL_ENABLE", 0, 0, &umr_bitfield_default }, + { "AQL_PACKET_SIZE", 1, 7, &umr_bitfield_default }, + { "PACKET_STEP", 8, 15, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC1_MINOR_PTR_UPDATE[] = { + { "ENABLE", 0, 0, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC1_MIDCMD_DATA0[] = { + { "DATA0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC1_MIDCMD_DATA1[] = { + { "DATA1", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC1_MIDCMD_DATA2[] = { + { "DATA2", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC1_MIDCMD_DATA3[] = { + { "DATA3", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC1_MIDCMD_DATA4[] = { + { "DATA4", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC1_MIDCMD_DATA5[] = { + { "DATA5", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC1_MIDCMD_DATA6[] = { + { "DATA6", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC1_MIDCMD_DATA7[] = { + { "DATA7", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC1_MIDCMD_DATA8[] = { + { "DATA8", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmSDMA0_RLC1_MIDCMD_CNTL[] = { + { "DATA_VALID", 0, 0, &umr_bitfield_default }, + { "COPY_MODE", 1, 1, &umr_bitfield_default }, + { "SPLIT_STATE", 4, 7, &umr_bitfield_default }, + { "ALLOW_PREEMPT", 8, 8, &umr_bitfield_default }, +}; diff --git a/src/lib/ip/sdma041_regs.i b/src/lib/ip/sdma041_regs.i new file mode 100644 index 0000000..ed50713 --- /dev/null +++ b/src/lib/ip/sdma041_regs.i @@ -0,0 +1,215 @@ + { "mmSDMA0_UCODE_ADDR", REG_MMIO, 0x0000, 0, &mmSDMA0_UCODE_ADDR[0], sizeof(mmSDMA0_UCODE_ADDR)/sizeof(mmSDMA0_UCODE_ADDR[0]), 0, 0 }, + { "mmSDMA0_UCODE_DATA", REG_MMIO, 0x0001, 0, &mmSDMA0_UCODE_DATA[0], sizeof(mmSDMA0_UCODE_DATA)/sizeof(mmSDMA0_UCODE_DATA[0]), 0, 0 }, + { "mmSDMA0_VM_CNTL", REG_MMIO, 0x0004, 0, &mmSDMA0_VM_CNTL[0], sizeof(mmSDMA0_VM_CNTL)/sizeof(mmSDMA0_VM_CNTL[0]), 0, 0 }, + { "mmSDMA0_VM_CTX_LO", REG_MMIO, 0x0005, 0, &mmSDMA0_VM_CTX_LO[0], sizeof(mmSDMA0_VM_CTX_LO)/sizeof(mmSDMA0_VM_CTX_LO[0]), 0, 0 }, + { "mmSDMA0_VM_CTX_HI", REG_MMIO, 0x0006, 0, &mmSDMA0_VM_CTX_HI[0], sizeof(mmSDMA0_VM_CTX_HI)/sizeof(mmSDMA0_VM_CTX_HI[0]), 0, 0 }, + { "mmSDMA0_ACTIVE_FCN_ID", REG_MMIO, 0x0007, 0, &mmSDMA0_ACTIVE_FCN_ID[0], sizeof(mmSDMA0_ACTIVE_FCN_ID)/sizeof(mmSDMA0_ACTIVE_FCN_ID[0]), 0, 0 }, + { "mmSDMA0_VM_CTX_CNTL", REG_MMIO, 0x0008, 0, &mmSDMA0_VM_CTX_CNTL[0], sizeof(mmSDMA0_VM_CTX_CNTL)/sizeof(mmSDMA0_VM_CTX_CNTL[0]), 0, 0 }, + { "mmSDMA0_VIRT_RESET_REQ", REG_MMIO, 0x0009, 0, &mmSDMA0_VIRT_RESET_REQ[0], sizeof(mmSDMA0_VIRT_RESET_REQ)/sizeof(mmSDMA0_VIRT_RESET_REQ[0]), 0, 0 }, + { "mmSDMA0_CONTEXT_REG_TYPE0", REG_MMIO, 0x000b, 0, &mmSDMA0_CONTEXT_REG_TYPE0[0], sizeof(mmSDMA0_CONTEXT_REG_TYPE0)/sizeof(mmSDMA0_CONTEXT_REG_TYPE0[0]), 0, 0 }, + { "mmSDMA0_CONTEXT_REG_TYPE1", REG_MMIO, 0x000c, 0, &mmSDMA0_CONTEXT_REG_TYPE1[0], sizeof(mmSDMA0_CONTEXT_REG_TYPE1)/sizeof(mmSDMA0_CONTEXT_REG_TYPE1[0]), 0, 0 }, + { "mmSDMA0_CONTEXT_REG_TYPE2", REG_MMIO, 0x000d, 0, &mmSDMA0_CONTEXT_REG_TYPE2[0], sizeof(mmSDMA0_CONTEXT_REG_TYPE2)/sizeof(mmSDMA0_CONTEXT_REG_TYPE2[0]), 0, 0 }, + { "mmSDMA0_CONTEXT_REG_TYPE3", REG_MMIO, 0x000e, 0, &mmSDMA0_CONTEXT_REG_TYPE3[0], sizeof(mmSDMA0_CONTEXT_REG_TYPE3)/sizeof(mmSDMA0_CONTEXT_REG_TYPE3[0]), 0, 0 }, + { "mmSDMA0_PUB_REG_TYPE0", REG_MMIO, 0x000f, 0, &mmSDMA0_PUB_REG_TYPE0[0], sizeof(mmSDMA0_PUB_REG_TYPE0)/sizeof(mmSDMA0_PUB_REG_TYPE0[0]), 0, 0 }, + { "mmSDMA0_PUB_REG_TYPE1", REG_MMIO, 0x0010, 0, &mmSDMA0_PUB_REG_TYPE1[0], sizeof(mmSDMA0_PUB_REG_TYPE1)/sizeof(mmSDMA0_PUB_REG_TYPE1[0]), 0, 0 }, + { "mmSDMA0_PUB_REG_TYPE2", REG_MMIO, 0x0011, 0, &mmSDMA0_PUB_REG_TYPE2[0], sizeof(mmSDMA0_PUB_REG_TYPE2)/sizeof(mmSDMA0_PUB_REG_TYPE2[0]), 0, 0 }, + { "mmSDMA0_PUB_REG_TYPE3", REG_MMIO, 0x0012, 0, &mmSDMA0_PUB_REG_TYPE3[0], sizeof(mmSDMA0_PUB_REG_TYPE3)/sizeof(mmSDMA0_PUB_REG_TYPE3[0]), 0, 0 }, + { "mmSDMA0_MMHUB_CNTL", REG_MMIO, 0x0013, 0, &mmSDMA0_MMHUB_CNTL[0], sizeof(mmSDMA0_MMHUB_CNTL)/sizeof(mmSDMA0_MMHUB_CNTL[0]), 0, 0 }, + { "mmSDMA0_CONTEXT_GROUP_BOUNDARY", REG_MMIO, 0x0019, 0, &mmSDMA0_CONTEXT_GROUP_BOUNDARY[0], sizeof(mmSDMA0_CONTEXT_GROUP_BOUNDARY)/sizeof(mmSDMA0_CONTEXT_GROUP_BOUNDARY[0]), 0, 0 }, + { "mmSDMA0_POWER_CNTL", REG_MMIO, 0x001a, 0, &mmSDMA0_POWER_CNTL[0], sizeof(mmSDMA0_POWER_CNTL)/sizeof(mmSDMA0_POWER_CNTL[0]), 0, 0 }, + { "mmSDMA0_CLK_CTRL", REG_MMIO, 0x001b, 0, &mmSDMA0_CLK_CTRL[0], sizeof(mmSDMA0_CLK_CTRL)/sizeof(mmSDMA0_CLK_CTRL[0]), 0, 0 }, + { "mmSDMA0_CNTL", REG_MMIO, 0x001c, 0, &mmSDMA0_CNTL[0], sizeof(mmSDMA0_CNTL)/sizeof(mmSDMA0_CNTL[0]), 0, 0 }, + { "mmSDMA0_CHICKEN_BITS", REG_MMIO, 0x001d, 0, &mmSDMA0_CHICKEN_BITS[0], sizeof(mmSDMA0_CHICKEN_BITS)/sizeof(mmSDMA0_CHICKEN_BITS[0]), 0, 0 }, + { "mmSDMA0_GB_ADDR_CONFIG", REG_MMIO, 0x001e, 0, &mmSDMA0_GB_ADDR_CONFIG[0], sizeof(mmSDMA0_GB_ADDR_CONFIG)/sizeof(mmSDMA0_GB_ADDR_CONFIG[0]), 0, 0 }, + { "mmSDMA0_GB_ADDR_CONFIG_READ", REG_MMIO, 0x001f, 0, &mmSDMA0_GB_ADDR_CONFIG_READ[0], sizeof(mmSDMA0_GB_ADDR_CONFIG_READ)/sizeof(mmSDMA0_GB_ADDR_CONFIG_READ[0]), 0, 0 }, + { "mmSDMA0_RB_RPTR_FETCH_HI", REG_MMIO, 0x0020, 0, &mmSDMA0_RB_RPTR_FETCH_HI[0], sizeof(mmSDMA0_RB_RPTR_FETCH_HI)/sizeof(mmSDMA0_RB_RPTR_FETCH_HI[0]), 0, 0 }, + { "mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL", REG_MMIO, 0x0021, 0, &mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL[0], sizeof(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL)/sizeof(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL[0]), 0, 0 }, + { "mmSDMA0_RB_RPTR_FETCH", REG_MMIO, 0x0022, 0, &mmSDMA0_RB_RPTR_FETCH[0], sizeof(mmSDMA0_RB_RPTR_FETCH)/sizeof(mmSDMA0_RB_RPTR_FETCH[0]), 0, 0 }, + { "mmSDMA0_IB_OFFSET_FETCH", REG_MMIO, 0x0023, 0, &mmSDMA0_IB_OFFSET_FETCH[0], sizeof(mmSDMA0_IB_OFFSET_FETCH)/sizeof(mmSDMA0_IB_OFFSET_FETCH[0]), 0, 0 }, + { "mmSDMA0_PROGRAM", REG_MMIO, 0x0024, 0, &mmSDMA0_PROGRAM[0], sizeof(mmSDMA0_PROGRAM)/sizeof(mmSDMA0_PROGRAM[0]), 0, 0 }, + { "mmSDMA0_STATUS_REG", REG_MMIO, 0x0025, 0, &mmSDMA0_STATUS_REG[0], sizeof(mmSDMA0_STATUS_REG)/sizeof(mmSDMA0_STATUS_REG[0]), 0, 0 }, + { "mmSDMA0_STATUS1_REG", REG_MMIO, 0x0026, 0, &mmSDMA0_STATUS1_REG[0], sizeof(mmSDMA0_STATUS1_REG)/sizeof(mmSDMA0_STATUS1_REG[0]), 0, 0 }, + { "mmSDMA0_RD_BURST_CNTL", REG_MMIO, 0x0027, 0, &mmSDMA0_RD_BURST_CNTL[0], sizeof(mmSDMA0_RD_BURST_CNTL)/sizeof(mmSDMA0_RD_BURST_CNTL[0]), 0, 0 }, + { "mmSDMA0_HBM_PAGE_CONFIG", REG_MMIO, 0x0028, 0, &mmSDMA0_HBM_PAGE_CONFIG[0], sizeof(mmSDMA0_HBM_PAGE_CONFIG)/sizeof(mmSDMA0_HBM_PAGE_CONFIG[0]), 0, 0 }, + { "mmSDMA0_UCODE_CHECKSUM", REG_MMIO, 0x0029, 0, &mmSDMA0_UCODE_CHECKSUM[0], sizeof(mmSDMA0_UCODE_CHECKSUM)/sizeof(mmSDMA0_UCODE_CHECKSUM[0]), 0, 0 }, + { "mmSDMA0_F32_CNTL", REG_MMIO, 0x002a, 0, &mmSDMA0_F32_CNTL[0], sizeof(mmSDMA0_F32_CNTL)/sizeof(mmSDMA0_F32_CNTL[0]), 0, 0 }, + { "mmSDMA0_FREEZE", REG_MMIO, 0x002b, 0, &mmSDMA0_FREEZE[0], sizeof(mmSDMA0_FREEZE)/sizeof(mmSDMA0_FREEZE[0]), 0, 0 }, + { "mmSDMA0_PHASE0_QUANTUM", REG_MMIO, 0x002c, 0, &mmSDMA0_PHASE0_QUANTUM[0], sizeof(mmSDMA0_PHASE0_QUANTUM)/sizeof(mmSDMA0_PHASE0_QUANTUM[0]), 0, 0 }, + { "mmSDMA0_PHASE1_QUANTUM", REG_MMIO, 0x002d, 0, &mmSDMA0_PHASE1_QUANTUM[0], sizeof(mmSDMA0_PHASE1_QUANTUM)/sizeof(mmSDMA0_PHASE1_QUANTUM[0]), 0, 0 }, + { "mmSDMA_POWER_GATING", REG_MMIO, 0x002e, 0, &mmSDMA_POWER_GATING[0], sizeof(mmSDMA_POWER_GATING)/sizeof(mmSDMA_POWER_GATING[0]), 0, 0 }, + { "mmSDMA_PGFSM_CONFIG", REG_MMIO, 0x002f, 0, &mmSDMA_PGFSM_CONFIG[0], sizeof(mmSDMA_PGFSM_CONFIG)/sizeof(mmSDMA_PGFSM_CONFIG[0]), 0, 0 }, + { "mmSDMA_PGFSM_WRITE", REG_MMIO, 0x0030, 0, &mmSDMA_PGFSM_WRITE[0], sizeof(mmSDMA_PGFSM_WRITE)/sizeof(mmSDMA_PGFSM_WRITE[0]), 0, 0 }, + { "mmSDMA_PGFSM_READ", REG_MMIO, 0x0031, 0, &mmSDMA_PGFSM_READ[0], sizeof(mmSDMA_PGFSM_READ)/sizeof(mmSDMA_PGFSM_READ[0]), 0, 0 }, + { "mmSDMA0_EDC_CONFIG", REG_MMIO, 0x0032, 0, &mmSDMA0_EDC_CONFIG[0], sizeof(mmSDMA0_EDC_CONFIG)/sizeof(mmSDMA0_EDC_CONFIG[0]), 0, 0 }, + { "mmSDMA0_BA_THRESHOLD", REG_MMIO, 0x0033, 0, &mmSDMA0_BA_THRESHOLD[0], sizeof(mmSDMA0_BA_THRESHOLD)/sizeof(mmSDMA0_BA_THRESHOLD[0]), 0, 0 }, + { "mmSDMA0_ID", REG_MMIO, 0x0034, 0, &mmSDMA0_ID[0], sizeof(mmSDMA0_ID)/sizeof(mmSDMA0_ID[0]), 0, 0 }, + { "mmSDMA0_VERSION", REG_MMIO, 0x0035, 0, &mmSDMA0_VERSION[0], sizeof(mmSDMA0_VERSION)/sizeof(mmSDMA0_VERSION[0]), 0, 0 }, + { "mmSDMA0_EDC_COUNTER", REG_MMIO, 0x0036, 0, &mmSDMA0_EDC_COUNTER[0], sizeof(mmSDMA0_EDC_COUNTER)/sizeof(mmSDMA0_EDC_COUNTER[0]), 0, 0 }, + { "mmSDMA0_EDC_COUNTER_CLEAR", REG_MMIO, 0x0037, 0, &mmSDMA0_EDC_COUNTER_CLEAR[0], sizeof(mmSDMA0_EDC_COUNTER_CLEAR)/sizeof(mmSDMA0_EDC_COUNTER_CLEAR[0]), 0, 0 }, + { "mmSDMA0_STATUS2_REG", REG_MMIO, 0x0038, 0, &mmSDMA0_STATUS2_REG[0], sizeof(mmSDMA0_STATUS2_REG)/sizeof(mmSDMA0_STATUS2_REG[0]), 0, 0 }, + { "mmSDMA0_ATOMIC_CNTL", REG_MMIO, 0x0039, 0, &mmSDMA0_ATOMIC_CNTL[0], sizeof(mmSDMA0_ATOMIC_CNTL)/sizeof(mmSDMA0_ATOMIC_CNTL[0]), 0, 0 }, + { "mmSDMA0_ATOMIC_PREOP_LO", REG_MMIO, 0x003a, 0, &mmSDMA0_ATOMIC_PREOP_LO[0], sizeof(mmSDMA0_ATOMIC_PREOP_LO)/sizeof(mmSDMA0_ATOMIC_PREOP_LO[0]), 0, 0 }, + { "mmSDMA0_ATOMIC_PREOP_HI", REG_MMIO, 0x003b, 0, &mmSDMA0_ATOMIC_PREOP_HI[0], sizeof(mmSDMA0_ATOMIC_PREOP_HI)/sizeof(mmSDMA0_ATOMIC_PREOP_HI[0]), 0, 0 }, + { "mmSDMA0_UTCL1_CNTL", REG_MMIO, 0x003c, 0, &mmSDMA0_UTCL1_CNTL[0], sizeof(mmSDMA0_UTCL1_CNTL)/sizeof(mmSDMA0_UTCL1_CNTL[0]), 0, 0 }, + { "mmSDMA0_UTCL1_WATERMK", REG_MMIO, 0x003d, 0, &mmSDMA0_UTCL1_WATERMK[0], sizeof(mmSDMA0_UTCL1_WATERMK)/sizeof(mmSDMA0_UTCL1_WATERMK[0]), 0, 0 }, + { "mmSDMA0_UTCL1_RD_STATUS", REG_MMIO, 0x003e, 0, &mmSDMA0_UTCL1_RD_STATUS[0], sizeof(mmSDMA0_UTCL1_RD_STATUS)/sizeof(mmSDMA0_UTCL1_RD_STATUS[0]), 0, 0 }, + { "mmSDMA0_UTCL1_WR_STATUS", REG_MMIO, 0x003f, 0, &mmSDMA0_UTCL1_WR_STATUS[0], sizeof(mmSDMA0_UTCL1_WR_STATUS)/sizeof(mmSDMA0_UTCL1_WR_STATUS[0]), 0, 0 }, + { "mmSDMA0_UTCL1_INV0", REG_MMIO, 0x0040, 0, &mmSDMA0_UTCL1_INV0[0], sizeof(mmSDMA0_UTCL1_INV0)/sizeof(mmSDMA0_UTCL1_INV0[0]), 0, 0 }, + { "mmSDMA0_UTCL1_INV1", REG_MMIO, 0x0041, 0, &mmSDMA0_UTCL1_INV1[0], sizeof(mmSDMA0_UTCL1_INV1)/sizeof(mmSDMA0_UTCL1_INV1[0]), 0, 0 }, + { "mmSDMA0_UTCL1_INV2", REG_MMIO, 0x0042, 0, &mmSDMA0_UTCL1_INV2[0], sizeof(mmSDMA0_UTCL1_INV2)/sizeof(mmSDMA0_UTCL1_INV2[0]), 0, 0 }, + { "mmSDMA0_UTCL1_RD_XNACK0", REG_MMIO, 0x0043, 0, &mmSDMA0_UTCL1_RD_XNACK0[0], sizeof(mmSDMA0_UTCL1_RD_XNACK0)/sizeof(mmSDMA0_UTCL1_RD_XNACK0[0]), 0, 0 }, + { "mmSDMA0_UTCL1_RD_XNACK1", REG_MMIO, 0x0044, 0, &mmSDMA0_UTCL1_RD_XNACK1[0], sizeof(mmSDMA0_UTCL1_RD_XNACK1)/sizeof(mmSDMA0_UTCL1_RD_XNACK1[0]), 0, 0 }, + { "mmSDMA0_UTCL1_WR_XNACK0", REG_MMIO, 0x0045, 0, &mmSDMA0_UTCL1_WR_XNACK0[0], sizeof(mmSDMA0_UTCL1_WR_XNACK0)/sizeof(mmSDMA0_UTCL1_WR_XNACK0[0]), 0, 0 }, + { "mmSDMA0_UTCL1_WR_XNACK1", REG_MMIO, 0x0046, 0, &mmSDMA0_UTCL1_WR_XNACK1[0], sizeof(mmSDMA0_UTCL1_WR_XNACK1)/sizeof(mmSDMA0_UTCL1_WR_XNACK1[0]), 0, 0 }, + { "mmSDMA0_UTCL1_TIMEOUT", REG_MMIO, 0x0047, 0, &mmSDMA0_UTCL1_TIMEOUT[0], sizeof(mmSDMA0_UTCL1_TIMEOUT)/sizeof(mmSDMA0_UTCL1_TIMEOUT[0]), 0, 0 }, + { "mmSDMA0_UTCL1_PAGE", REG_MMIO, 0x0048, 0, &mmSDMA0_UTCL1_PAGE[0], sizeof(mmSDMA0_UTCL1_PAGE)/sizeof(mmSDMA0_UTCL1_PAGE[0]), 0, 0 }, + { "mmSDMA0_POWER_CNTL_IDLE", REG_MMIO, 0x0049, 0, &mmSDMA0_POWER_CNTL_IDLE[0], sizeof(mmSDMA0_POWER_CNTL_IDLE)/sizeof(mmSDMA0_POWER_CNTL_IDLE[0]), 0, 0 }, + { "mmSDMA0_RELAX_ORDERING_LUT", REG_MMIO, 0x004a, 0, &mmSDMA0_RELAX_ORDERING_LUT[0], sizeof(mmSDMA0_RELAX_ORDERING_LUT)/sizeof(mmSDMA0_RELAX_ORDERING_LUT[0]), 0, 0 }, + { "mmSDMA0_CHICKEN_BITS_2", REG_MMIO, 0x004b, 0, &mmSDMA0_CHICKEN_BITS_2[0], sizeof(mmSDMA0_CHICKEN_BITS_2)/sizeof(mmSDMA0_CHICKEN_BITS_2[0]), 0, 0 }, + { "mmSDMA0_STATUS3_REG", REG_MMIO, 0x004c, 0, &mmSDMA0_STATUS3_REG[0], sizeof(mmSDMA0_STATUS3_REG)/sizeof(mmSDMA0_STATUS3_REG[0]), 0, 0 }, + { "mmSDMA0_PHYSICAL_ADDR_LO", REG_MMIO, 0x004d, 0, &mmSDMA0_PHYSICAL_ADDR_LO[0], sizeof(mmSDMA0_PHYSICAL_ADDR_LO)/sizeof(mmSDMA0_PHYSICAL_ADDR_LO[0]), 0, 0 }, + { "mmSDMA0_PHYSICAL_ADDR_HI", REG_MMIO, 0x004e, 0, &mmSDMA0_PHYSICAL_ADDR_HI[0], sizeof(mmSDMA0_PHYSICAL_ADDR_HI)/sizeof(mmSDMA0_PHYSICAL_ADDR_HI[0]), 0, 0 }, + { "mmSDMA0_ERROR_LOG", REG_MMIO, 0x0050, 0, &mmSDMA0_ERROR_LOG[0], sizeof(mmSDMA0_ERROR_LOG)/sizeof(mmSDMA0_ERROR_LOG[0]), 0, 0 }, + { "mmSDMA0_PUB_DUMMY_REG0", REG_MMIO, 0x0051, 0, &mmSDMA0_PUB_DUMMY_REG0[0], sizeof(mmSDMA0_PUB_DUMMY_REG0)/sizeof(mmSDMA0_PUB_DUMMY_REG0[0]), 0, 0 }, + { "mmSDMA0_PUB_DUMMY_REG1", REG_MMIO, 0x0052, 0, &mmSDMA0_PUB_DUMMY_REG1[0], sizeof(mmSDMA0_PUB_DUMMY_REG1)/sizeof(mmSDMA0_PUB_DUMMY_REG1[0]), 0, 0 }, + { "mmSDMA0_PUB_DUMMY_REG2", REG_MMIO, 0x0053, 0, &mmSDMA0_PUB_DUMMY_REG2[0], sizeof(mmSDMA0_PUB_DUMMY_REG2)/sizeof(mmSDMA0_PUB_DUMMY_REG2[0]), 0, 0 }, + { "mmSDMA0_PUB_DUMMY_REG3", REG_MMIO, 0x0054, 0, &mmSDMA0_PUB_DUMMY_REG3[0], sizeof(mmSDMA0_PUB_DUMMY_REG3)/sizeof(mmSDMA0_PUB_DUMMY_REG3[0]), 0, 0 }, + { "mmSDMA0_F32_COUNTER", REG_MMIO, 0x0055, 0, &mmSDMA0_F32_COUNTER[0], sizeof(mmSDMA0_F32_COUNTER)/sizeof(mmSDMA0_F32_COUNTER[0]), 0, 0 }, + { "mmSDMA0_UNBREAKABLE", REG_MMIO, 0x0056, 0, &mmSDMA0_UNBREAKABLE[0], sizeof(mmSDMA0_UNBREAKABLE)/sizeof(mmSDMA0_UNBREAKABLE[0]), 0, 0 }, + { "mmSDMA0_PERFMON_CNTL", REG_MMIO, 0x0057, 0, &mmSDMA0_PERFMON_CNTL[0], sizeof(mmSDMA0_PERFMON_CNTL)/sizeof(mmSDMA0_PERFMON_CNTL[0]), 0, 0 }, + { "mmSDMA0_PERFCOUNTER0_RESULT", REG_MMIO, 0x0058, 0, &mmSDMA0_PERFCOUNTER0_RESULT[0], sizeof(mmSDMA0_PERFCOUNTER0_RESULT)/sizeof(mmSDMA0_PERFCOUNTER0_RESULT[0]), 0, 0 }, + { "mmSDMA0_PERFCOUNTER1_RESULT", REG_MMIO, 0x0059, 0, &mmSDMA0_PERFCOUNTER1_RESULT[0], sizeof(mmSDMA0_PERFCOUNTER1_RESULT)/sizeof(mmSDMA0_PERFCOUNTER1_RESULT[0]), 0, 0 }, + { "mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE", REG_MMIO, 0x005a, 0, &mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE[0], sizeof(mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE)/sizeof(mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE[0]), 0, 0 }, + { "mmSDMA0_CRD_CNTL", REG_MMIO, 0x005b, 0, &mmSDMA0_CRD_CNTL[0], sizeof(mmSDMA0_CRD_CNTL)/sizeof(mmSDMA0_CRD_CNTL[0]), 0, 0 }, + { "mmSDMA0_MMHUB_TRUSTLVL", REG_MMIO, 0x005c, 0, &mmSDMA0_MMHUB_TRUSTLVL[0], sizeof(mmSDMA0_MMHUB_TRUSTLVL)/sizeof(mmSDMA0_MMHUB_TRUSTLVL[0]), 0, 0 }, + { "mmSDMA0_GPU_IOV_VIOLATION_LOG", REG_MMIO, 0x005d, 0, &mmSDMA0_GPU_IOV_VIOLATION_LOG[0], sizeof(mmSDMA0_GPU_IOV_VIOLATION_LOG)/sizeof(mmSDMA0_GPU_IOV_VIOLATION_LOG[0]), 0, 0 }, + { "mmSDMA0_ULV_CNTL", REG_MMIO, 0x005e, 0, &mmSDMA0_ULV_CNTL[0], sizeof(mmSDMA0_ULV_CNTL)/sizeof(mmSDMA0_ULV_CNTL[0]), 0, 0 }, + { "mmSDMA0_EA_DBIT_ADDR_DATA", REG_MMIO, 0x0060, 0, &mmSDMA0_EA_DBIT_ADDR_DATA[0], sizeof(mmSDMA0_EA_DBIT_ADDR_DATA)/sizeof(mmSDMA0_EA_DBIT_ADDR_DATA[0]), 0, 0 }, + { "mmSDMA0_EA_DBIT_ADDR_INDEX", REG_MMIO, 0x0061, 0, &mmSDMA0_EA_DBIT_ADDR_INDEX[0], sizeof(mmSDMA0_EA_DBIT_ADDR_INDEX)/sizeof(mmSDMA0_EA_DBIT_ADDR_INDEX[0]), 0, 0 }, + { "mmSDMA0_GFX_RB_CNTL", REG_MMIO, 0x0080, 0, &mmSDMA0_GFX_RB_CNTL[0], sizeof(mmSDMA0_GFX_RB_CNTL)/sizeof(mmSDMA0_GFX_RB_CNTL[0]), 0, 0 }, + { "mmSDMA0_GFX_RB_BASE", REG_MMIO, 0x0081, 0, &mmSDMA0_GFX_RB_BASE[0], sizeof(mmSDMA0_GFX_RB_BASE)/sizeof(mmSDMA0_GFX_RB_BASE[0]), 0, 0 }, + { "mmSDMA0_GFX_RB_BASE_HI", REG_MMIO, 0x0082, 0, &mmSDMA0_GFX_RB_BASE_HI[0], sizeof(mmSDMA0_GFX_RB_BASE_HI)/sizeof(mmSDMA0_GFX_RB_BASE_HI[0]), 0, 0 }, + { "mmSDMA0_GFX_RB_RPTR", REG_MMIO, 0x0083, 0, &mmSDMA0_GFX_RB_RPTR[0], sizeof(mmSDMA0_GFX_RB_RPTR)/sizeof(mmSDMA0_GFX_RB_RPTR[0]), 0, 0 }, + { "mmSDMA0_GFX_RB_RPTR_HI", REG_MMIO, 0x0084, 0, &mmSDMA0_GFX_RB_RPTR_HI[0], sizeof(mmSDMA0_GFX_RB_RPTR_HI)/sizeof(mmSDMA0_GFX_RB_RPTR_HI[0]), 0, 0 }, + { "mmSDMA0_GFX_RB_WPTR", REG_MMIO, 0x0085, 0, &mmSDMA0_GFX_RB_WPTR[0], sizeof(mmSDMA0_GFX_RB_WPTR)/sizeof(mmSDMA0_GFX_RB_WPTR[0]), 0, 0 }, + { "mmSDMA0_GFX_RB_WPTR_HI", REG_MMIO, 0x0086, 0, &mmSDMA0_GFX_RB_WPTR_HI[0], sizeof(mmSDMA0_GFX_RB_WPTR_HI)/sizeof(mmSDMA0_GFX_RB_WPTR_HI[0]), 0, 0 }, + { "mmSDMA0_GFX_RB_WPTR_POLL_CNTL", REG_MMIO, 0x0087, 0, &mmSDMA0_GFX_RB_WPTR_POLL_CNTL[0], sizeof(mmSDMA0_GFX_RB_WPTR_POLL_CNTL)/sizeof(mmSDMA0_GFX_RB_WPTR_POLL_CNTL[0]), 0, 0 }, + { "mmSDMA0_GFX_RB_RPTR_ADDR_HI", REG_MMIO, 0x0088, 0, &mmSDMA0_GFX_RB_RPTR_ADDR_HI[0], sizeof(mmSDMA0_GFX_RB_RPTR_ADDR_HI)/sizeof(mmSDMA0_GFX_RB_RPTR_ADDR_HI[0]), 0, 0 }, + { "mmSDMA0_GFX_RB_RPTR_ADDR_LO", REG_MMIO, 0x0089, 0, &mmSDMA0_GFX_RB_RPTR_ADDR_LO[0], sizeof(mmSDMA0_GFX_RB_RPTR_ADDR_LO)/sizeof(mmSDMA0_GFX_RB_RPTR_ADDR_LO[0]), 0, 0 }, + { "mmSDMA0_GFX_IB_CNTL", REG_MMIO, 0x008a, 0, &mmSDMA0_GFX_IB_CNTL[0], sizeof(mmSDMA0_GFX_IB_CNTL)/sizeof(mmSDMA0_GFX_IB_CNTL[0]), 0, 0 }, + { "mmSDMA0_GFX_IB_RPTR", REG_MMIO, 0x008b, 0, &mmSDMA0_GFX_IB_RPTR[0], sizeof(mmSDMA0_GFX_IB_RPTR)/sizeof(mmSDMA0_GFX_IB_RPTR[0]), 0, 0 }, + { "mmSDMA0_GFX_IB_OFFSET", REG_MMIO, 0x008c, 0, &mmSDMA0_GFX_IB_OFFSET[0], sizeof(mmSDMA0_GFX_IB_OFFSET)/sizeof(mmSDMA0_GFX_IB_OFFSET[0]), 0, 0 }, + { "mmSDMA0_GFX_IB_BASE_LO", REG_MMIO, 0x008d, 0, &mmSDMA0_GFX_IB_BASE_LO[0], sizeof(mmSDMA0_GFX_IB_BASE_LO)/sizeof(mmSDMA0_GFX_IB_BASE_LO[0]), 0, 0 }, + { "mmSDMA0_GFX_IB_BASE_HI", REG_MMIO, 0x008e, 0, &mmSDMA0_GFX_IB_BASE_HI[0], sizeof(mmSDMA0_GFX_IB_BASE_HI)/sizeof(mmSDMA0_GFX_IB_BASE_HI[0]), 0, 0 }, + { "mmSDMA0_GFX_IB_SIZE", REG_MMIO, 0x008f, 0, &mmSDMA0_GFX_IB_SIZE[0], sizeof(mmSDMA0_GFX_IB_SIZE)/sizeof(mmSDMA0_GFX_IB_SIZE[0]), 0, 0 }, + { "mmSDMA0_GFX_SKIP_CNTL", REG_MMIO, 0x0090, 0, &mmSDMA0_GFX_SKIP_CNTL[0], sizeof(mmSDMA0_GFX_SKIP_CNTL)/sizeof(mmSDMA0_GFX_SKIP_CNTL[0]), 0, 0 }, + { "mmSDMA0_GFX_CONTEXT_STATUS", REG_MMIO, 0x0091, 0, &mmSDMA0_GFX_CONTEXT_STATUS[0], sizeof(mmSDMA0_GFX_CONTEXT_STATUS)/sizeof(mmSDMA0_GFX_CONTEXT_STATUS[0]), 0, 0 }, + { "mmSDMA0_GFX_DOORBELL", REG_MMIO, 0x0092, 0, &mmSDMA0_GFX_DOORBELL[0], sizeof(mmSDMA0_GFX_DOORBELL)/sizeof(mmSDMA0_GFX_DOORBELL[0]), 0, 0 }, + { "mmSDMA0_GFX_CONTEXT_CNTL", REG_MMIO, 0x0093, 0, &mmSDMA0_GFX_CONTEXT_CNTL[0], sizeof(mmSDMA0_GFX_CONTEXT_CNTL)/sizeof(mmSDMA0_GFX_CONTEXT_CNTL[0]), 0, 0 }, + { "mmSDMA0_GFX_STATUS", REG_MMIO, 0x00a8, 0, &mmSDMA0_GFX_STATUS[0], sizeof(mmSDMA0_GFX_STATUS)/sizeof(mmSDMA0_GFX_STATUS[0]), 0, 0 }, + { "mmSDMA0_GFX_DOORBELL_LOG", REG_MMIO, 0x00a9, 0, &mmSDMA0_GFX_DOORBELL_LOG[0], sizeof(mmSDMA0_GFX_DOORBELL_LOG)/sizeof(mmSDMA0_GFX_DOORBELL_LOG[0]), 0, 0 }, + { "mmSDMA0_GFX_WATERMARK", REG_MMIO, 0x00aa, 0, &mmSDMA0_GFX_WATERMARK[0], sizeof(mmSDMA0_GFX_WATERMARK)/sizeof(mmSDMA0_GFX_WATERMARK[0]), 0, 0 }, + { "mmSDMA0_GFX_DOORBELL_OFFSET", REG_MMIO, 0x00ab, 0, &mmSDMA0_GFX_DOORBELL_OFFSET[0], sizeof(mmSDMA0_GFX_DOORBELL_OFFSET)/sizeof(mmSDMA0_GFX_DOORBELL_OFFSET[0]), 0, 0 }, + { "mmSDMA0_GFX_CSA_ADDR_LO", REG_MMIO, 0x00ac, 0, &mmSDMA0_GFX_CSA_ADDR_LO[0], sizeof(mmSDMA0_GFX_CSA_ADDR_LO)/sizeof(mmSDMA0_GFX_CSA_ADDR_LO[0]), 0, 0 }, + { "mmSDMA0_GFX_CSA_ADDR_HI", REG_MMIO, 0x00ad, 0, &mmSDMA0_GFX_CSA_ADDR_HI[0], sizeof(mmSDMA0_GFX_CSA_ADDR_HI)/sizeof(mmSDMA0_GFX_CSA_ADDR_HI[0]), 0, 0 }, + { "mmSDMA0_GFX_IB_SUB_REMAIN", REG_MMIO, 0x00af, 0, &mmSDMA0_GFX_IB_SUB_REMAIN[0], sizeof(mmSDMA0_GFX_IB_SUB_REMAIN)/sizeof(mmSDMA0_GFX_IB_SUB_REMAIN[0]), 0, 0 }, + { "mmSDMA0_GFX_PREEMPT", REG_MMIO, 0x00b0, 0, &mmSDMA0_GFX_PREEMPT[0], sizeof(mmSDMA0_GFX_PREEMPT)/sizeof(mmSDMA0_GFX_PREEMPT[0]), 0, 0 }, + { "mmSDMA0_GFX_DUMMY_REG", REG_MMIO, 0x00b1, 0, &mmSDMA0_GFX_DUMMY_REG[0], sizeof(mmSDMA0_GFX_DUMMY_REG)/sizeof(mmSDMA0_GFX_DUMMY_REG[0]), 0, 0 }, + { "mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI", REG_MMIO, 0x00b2, 0, &mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI[0], sizeof(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI)/sizeof(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI[0]), 0, 0 }, + { "mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO", REG_MMIO, 0x00b3, 0, &mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO[0], sizeof(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO)/sizeof(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO[0]), 0, 0 }, + { "mmSDMA0_GFX_RB_AQL_CNTL", REG_MMIO, 0x00b4, 0, &mmSDMA0_GFX_RB_AQL_CNTL[0], sizeof(mmSDMA0_GFX_RB_AQL_CNTL)/sizeof(mmSDMA0_GFX_RB_AQL_CNTL[0]), 0, 0 }, + { "mmSDMA0_GFX_MINOR_PTR_UPDATE", REG_MMIO, 0x00b5, 0, &mmSDMA0_GFX_MINOR_PTR_UPDATE[0], sizeof(mmSDMA0_GFX_MINOR_PTR_UPDATE)/sizeof(mmSDMA0_GFX_MINOR_PTR_UPDATE[0]), 0, 0 }, + { "mmSDMA0_GFX_MIDCMD_DATA0", REG_MMIO, 0x00c0, 0, &mmSDMA0_GFX_MIDCMD_DATA0[0], sizeof(mmSDMA0_GFX_MIDCMD_DATA0)/sizeof(mmSDMA0_GFX_MIDCMD_DATA0[0]), 0, 0 }, + { "mmSDMA0_GFX_MIDCMD_DATA1", REG_MMIO, 0x00c1, 0, &mmSDMA0_GFX_MIDCMD_DATA1[0], sizeof(mmSDMA0_GFX_MIDCMD_DATA1)/sizeof(mmSDMA0_GFX_MIDCMD_DATA1[0]), 0, 0 }, + { "mmSDMA0_GFX_MIDCMD_DATA2", REG_MMIO, 0x00c2, 0, &mmSDMA0_GFX_MIDCMD_DATA2[0], sizeof(mmSDMA0_GFX_MIDCMD_DATA2)/sizeof(mmSDMA0_GFX_MIDCMD_DATA2[0]), 0, 0 }, + { "mmSDMA0_GFX_MIDCMD_DATA3", REG_MMIO, 0x00c3, 0, &mmSDMA0_GFX_MIDCMD_DATA3[0], sizeof(mmSDMA0_GFX_MIDCMD_DATA3)/sizeof(mmSDMA0_GFX_MIDCMD_DATA3[0]), 0, 0 }, + { "mmSDMA0_GFX_MIDCMD_DATA4", REG_MMIO, 0x00c4, 0, &mmSDMA0_GFX_MIDCMD_DATA4[0], sizeof(mmSDMA0_GFX_MIDCMD_DATA4)/sizeof(mmSDMA0_GFX_MIDCMD_DATA4[0]), 0, 0 }, + { "mmSDMA0_GFX_MIDCMD_DATA5", REG_MMIO, 0x00c5, 0, &mmSDMA0_GFX_MIDCMD_DATA5[0], sizeof(mmSDMA0_GFX_MIDCMD_DATA5)/sizeof(mmSDMA0_GFX_MIDCMD_DATA5[0]), 0, 0 }, + { "mmSDMA0_GFX_MIDCMD_DATA6", REG_MMIO, 0x00c6, 0, &mmSDMA0_GFX_MIDCMD_DATA6[0], sizeof(mmSDMA0_GFX_MIDCMD_DATA6)/sizeof(mmSDMA0_GFX_MIDCMD_DATA6[0]), 0, 0 }, + { "mmSDMA0_GFX_MIDCMD_DATA7", REG_MMIO, 0x00c7, 0, &mmSDMA0_GFX_MIDCMD_DATA7[0], sizeof(mmSDMA0_GFX_MIDCMD_DATA7)/sizeof(mmSDMA0_GFX_MIDCMD_DATA7[0]), 0, 0 }, + { "mmSDMA0_GFX_MIDCMD_DATA8", REG_MMIO, 0x00c8, 0, &mmSDMA0_GFX_MIDCMD_DATA8[0], sizeof(mmSDMA0_GFX_MIDCMD_DATA8)/sizeof(mmSDMA0_GFX_MIDCMD_DATA8[0]), 0, 0 }, + { "mmSDMA0_GFX_MIDCMD_CNTL", REG_MMIO, 0x00c9, 0, &mmSDMA0_GFX_MIDCMD_CNTL[0], sizeof(mmSDMA0_GFX_MIDCMD_CNTL)/sizeof(mmSDMA0_GFX_MIDCMD_CNTL[0]), 0, 0 }, + { "mmSDMA0_RLC0_RB_CNTL", REG_MMIO, 0x0140, 0, &mmSDMA0_RLC0_RB_CNTL[0], sizeof(mmSDMA0_RLC0_RB_CNTL)/sizeof(mmSDMA0_RLC0_RB_CNTL[0]), 0, 0 }, + { "mmSDMA0_RLC0_RB_BASE", REG_MMIO, 0x0141, 0, &mmSDMA0_RLC0_RB_BASE[0], sizeof(mmSDMA0_RLC0_RB_BASE)/sizeof(mmSDMA0_RLC0_RB_BASE[0]), 0, 0 }, + { "mmSDMA0_RLC0_RB_BASE_HI", REG_MMIO, 0x0142, 0, &mmSDMA0_RLC0_RB_BASE_HI[0], sizeof(mmSDMA0_RLC0_RB_BASE_HI)/sizeof(mmSDMA0_RLC0_RB_BASE_HI[0]), 0, 0 }, + { "mmSDMA0_RLC0_RB_RPTR", REG_MMIO, 0x0143, 0, &mmSDMA0_RLC0_RB_RPTR[0], sizeof(mmSDMA0_RLC0_RB_RPTR)/sizeof(mmSDMA0_RLC0_RB_RPTR[0]), 0, 0 }, + { "mmSDMA0_RLC0_RB_RPTR_HI", REG_MMIO, 0x0144, 0, &mmSDMA0_RLC0_RB_RPTR_HI[0], sizeof(mmSDMA0_RLC0_RB_RPTR_HI)/sizeof(mmSDMA0_RLC0_RB_RPTR_HI[0]), 0, 0 }, + { "mmSDMA0_RLC0_RB_WPTR", REG_MMIO, 0x0145, 0, &mmSDMA0_RLC0_RB_WPTR[0], sizeof(mmSDMA0_RLC0_RB_WPTR)/sizeof(mmSDMA0_RLC0_RB_WPTR[0]), 0, 0 }, + { "mmSDMA0_RLC0_RB_WPTR_HI", REG_MMIO, 0x0146, 0, &mmSDMA0_RLC0_RB_WPTR_HI[0], sizeof(mmSDMA0_RLC0_RB_WPTR_HI)/sizeof(mmSDMA0_RLC0_RB_WPTR_HI[0]), 0, 0 }, + { "mmSDMA0_RLC0_RB_WPTR_POLL_CNTL", REG_MMIO, 0x0147, 0, &mmSDMA0_RLC0_RB_WPTR_POLL_CNTL[0], sizeof(mmSDMA0_RLC0_RB_WPTR_POLL_CNTL)/sizeof(mmSDMA0_RLC0_RB_WPTR_POLL_CNTL[0]), 0, 0 }, + { "mmSDMA0_RLC0_RB_RPTR_ADDR_HI", REG_MMIO, 0x0148, 0, &mmSDMA0_RLC0_RB_RPTR_ADDR_HI[0], sizeof(mmSDMA0_RLC0_RB_RPTR_ADDR_HI)/sizeof(mmSDMA0_RLC0_RB_RPTR_ADDR_HI[0]), 0, 0 }, + { "mmSDMA0_RLC0_RB_RPTR_ADDR_LO", REG_MMIO, 0x0149, 0, &mmSDMA0_RLC0_RB_RPTR_ADDR_LO[0], sizeof(mmSDMA0_RLC0_RB_RPTR_ADDR_LO)/sizeof(mmSDMA0_RLC0_RB_RPTR_ADDR_LO[0]), 0, 0 }, + { "mmSDMA0_RLC0_IB_CNTL", REG_MMIO, 0x014a, 0, &mmSDMA0_RLC0_IB_CNTL[0], sizeof(mmSDMA0_RLC0_IB_CNTL)/sizeof(mmSDMA0_RLC0_IB_CNTL[0]), 0, 0 }, + { "mmSDMA0_RLC0_IB_RPTR", REG_MMIO, 0x014b, 0, &mmSDMA0_RLC0_IB_RPTR[0], sizeof(mmSDMA0_RLC0_IB_RPTR)/sizeof(mmSDMA0_RLC0_IB_RPTR[0]), 0, 0 }, + { "mmSDMA0_RLC0_IB_OFFSET", REG_MMIO, 0x014c, 0, &mmSDMA0_RLC0_IB_OFFSET[0], sizeof(mmSDMA0_RLC0_IB_OFFSET)/sizeof(mmSDMA0_RLC0_IB_OFFSET[0]), 0, 0 }, + { "mmSDMA0_RLC0_IB_BASE_LO", REG_MMIO, 0x014d, 0, &mmSDMA0_RLC0_IB_BASE_LO[0], sizeof(mmSDMA0_RLC0_IB_BASE_LO)/sizeof(mmSDMA0_RLC0_IB_BASE_LO[0]), 0, 0 }, + { "mmSDMA0_RLC0_IB_BASE_HI", REG_MMIO, 0x014e, 0, &mmSDMA0_RLC0_IB_BASE_HI[0], sizeof(mmSDMA0_RLC0_IB_BASE_HI)/sizeof(mmSDMA0_RLC0_IB_BASE_HI[0]), 0, 0 }, + { "mmSDMA0_RLC0_IB_SIZE", REG_MMIO, 0x014f, 0, &mmSDMA0_RLC0_IB_SIZE[0], sizeof(mmSDMA0_RLC0_IB_SIZE)/sizeof(mmSDMA0_RLC0_IB_SIZE[0]), 0, 0 }, + { "mmSDMA0_RLC0_SKIP_CNTL", REG_MMIO, 0x0150, 0, &mmSDMA0_RLC0_SKIP_CNTL[0], sizeof(mmSDMA0_RLC0_SKIP_CNTL)/sizeof(mmSDMA0_RLC0_SKIP_CNTL[0]), 0, 0 }, + { "mmSDMA0_RLC0_CONTEXT_STATUS", REG_MMIO, 0x0151, 0, &mmSDMA0_RLC0_CONTEXT_STATUS[0], sizeof(mmSDMA0_RLC0_CONTEXT_STATUS)/sizeof(mmSDMA0_RLC0_CONTEXT_STATUS[0]), 0, 0 }, + { "mmSDMA0_RLC0_DOORBELL", REG_MMIO, 0x0152, 0, &mmSDMA0_RLC0_DOORBELL[0], sizeof(mmSDMA0_RLC0_DOORBELL)/sizeof(mmSDMA0_RLC0_DOORBELL[0]), 0, 0 }, + { "mmSDMA0_RLC0_STATUS", REG_MMIO, 0x0168, 0, &mmSDMA0_RLC0_STATUS[0], sizeof(mmSDMA0_RLC0_STATUS)/sizeof(mmSDMA0_RLC0_STATUS[0]), 0, 0 }, + { "mmSDMA0_RLC0_DOORBELL_LOG", REG_MMIO, 0x0169, 0, &mmSDMA0_RLC0_DOORBELL_LOG[0], sizeof(mmSDMA0_RLC0_DOORBELL_LOG)/sizeof(mmSDMA0_RLC0_DOORBELL_LOG[0]), 0, 0 }, + { "mmSDMA0_RLC0_WATERMARK", REG_MMIO, 0x016a, 0, &mmSDMA0_RLC0_WATERMARK[0], sizeof(mmSDMA0_RLC0_WATERMARK)/sizeof(mmSDMA0_RLC0_WATERMARK[0]), 0, 0 }, + { "mmSDMA0_RLC0_DOORBELL_OFFSET", REG_MMIO, 0x016b, 0, &mmSDMA0_RLC0_DOORBELL_OFFSET[0], sizeof(mmSDMA0_RLC0_DOORBELL_OFFSET)/sizeof(mmSDMA0_RLC0_DOORBELL_OFFSET[0]), 0, 0 }, + { "mmSDMA0_RLC0_CSA_ADDR_LO", REG_MMIO, 0x016c, 0, &mmSDMA0_RLC0_CSA_ADDR_LO[0], sizeof(mmSDMA0_RLC0_CSA_ADDR_LO)/sizeof(mmSDMA0_RLC0_CSA_ADDR_LO[0]), 0, 0 }, + { "mmSDMA0_RLC0_CSA_ADDR_HI", REG_MMIO, 0x016d, 0, &mmSDMA0_RLC0_CSA_ADDR_HI[0], sizeof(mmSDMA0_RLC0_CSA_ADDR_HI)/sizeof(mmSDMA0_RLC0_CSA_ADDR_HI[0]), 0, 0 }, + { "mmSDMA0_RLC0_IB_SUB_REMAIN", REG_MMIO, 0x016f, 0, &mmSDMA0_RLC0_IB_SUB_REMAIN[0], sizeof(mmSDMA0_RLC0_IB_SUB_REMAIN)/sizeof(mmSDMA0_RLC0_IB_SUB_REMAIN[0]), 0, 0 }, + { "mmSDMA0_RLC0_PREEMPT", REG_MMIO, 0x0170, 0, &mmSDMA0_RLC0_PREEMPT[0], sizeof(mmSDMA0_RLC0_PREEMPT)/sizeof(mmSDMA0_RLC0_PREEMPT[0]), 0, 0 }, + { "mmSDMA0_RLC0_DUMMY_REG", REG_MMIO, 0x0171, 0, &mmSDMA0_RLC0_DUMMY_REG[0], sizeof(mmSDMA0_RLC0_DUMMY_REG)/sizeof(mmSDMA0_RLC0_DUMMY_REG[0]), 0, 0 }, + { "mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI", REG_MMIO, 0x0172, 0, &mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI[0], sizeof(mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI)/sizeof(mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI[0]), 0, 0 }, + { "mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO", REG_MMIO, 0x0173, 0, &mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO[0], sizeof(mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO)/sizeof(mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO[0]), 0, 0 }, + { "mmSDMA0_RLC0_RB_AQL_CNTL", REG_MMIO, 0x0174, 0, &mmSDMA0_RLC0_RB_AQL_CNTL[0], sizeof(mmSDMA0_RLC0_RB_AQL_CNTL)/sizeof(mmSDMA0_RLC0_RB_AQL_CNTL[0]), 0, 0 }, + { "mmSDMA0_RLC0_MINOR_PTR_UPDATE", REG_MMIO, 0x0175, 0, &mmSDMA0_RLC0_MINOR_PTR_UPDATE[0], sizeof(mmSDMA0_RLC0_MINOR_PTR_UPDATE)/sizeof(mmSDMA0_RLC0_MINOR_PTR_UPDATE[0]), 0, 0 }, + { "mmSDMA0_RLC0_MIDCMD_DATA0", REG_MMIO, 0x0180, 0, &mmSDMA0_RLC0_MIDCMD_DATA0[0], sizeof(mmSDMA0_RLC0_MIDCMD_DATA0)/sizeof(mmSDMA0_RLC0_MIDCMD_DATA0[0]), 0, 0 }, + { "mmSDMA0_RLC0_MIDCMD_DATA1", REG_MMIO, 0x0181, 0, &mmSDMA0_RLC0_MIDCMD_DATA1[0], sizeof(mmSDMA0_RLC0_MIDCMD_DATA1)/sizeof(mmSDMA0_RLC0_MIDCMD_DATA1[0]), 0, 0 }, + { "mmSDMA0_RLC0_MIDCMD_DATA2", REG_MMIO, 0x0182, 0, &mmSDMA0_RLC0_MIDCMD_DATA2[0], sizeof(mmSDMA0_RLC0_MIDCMD_DATA2)/sizeof(mmSDMA0_RLC0_MIDCMD_DATA2[0]), 0, 0 }, + { "mmSDMA0_RLC0_MIDCMD_DATA3", REG_MMIO, 0x0183, 0, &mmSDMA0_RLC0_MIDCMD_DATA3[0], sizeof(mmSDMA0_RLC0_MIDCMD_DATA3)/sizeof(mmSDMA0_RLC0_MIDCMD_DATA3[0]), 0, 0 }, + { "mmSDMA0_RLC0_MIDCMD_DATA4", REG_MMIO, 0x0184, 0, &mmSDMA0_RLC0_MIDCMD_DATA4[0], sizeof(mmSDMA0_RLC0_MIDCMD_DATA4)/sizeof(mmSDMA0_RLC0_MIDCMD_DATA4[0]), 0, 0 }, + { "mmSDMA0_RLC0_MIDCMD_DATA5", REG_MMIO, 0x0185, 0, &mmSDMA0_RLC0_MIDCMD_DATA5[0], sizeof(mmSDMA0_RLC0_MIDCMD_DATA5)/sizeof(mmSDMA0_RLC0_MIDCMD_DATA5[0]), 0, 0 }, + { "mmSDMA0_RLC0_MIDCMD_DATA6", REG_MMIO, 0x0186, 0, &mmSDMA0_RLC0_MIDCMD_DATA6[0], sizeof(mmSDMA0_RLC0_MIDCMD_DATA6)/sizeof(mmSDMA0_RLC0_MIDCMD_DATA6[0]), 0, 0 }, + { "mmSDMA0_RLC0_MIDCMD_DATA7", REG_MMIO, 0x0187, 0, &mmSDMA0_RLC0_MIDCMD_DATA7[0], sizeof(mmSDMA0_RLC0_MIDCMD_DATA7)/sizeof(mmSDMA0_RLC0_MIDCMD_DATA7[0]), 0, 0 }, + { "mmSDMA0_RLC0_MIDCMD_DATA8", REG_MMIO, 0x0188, 0, &mmSDMA0_RLC0_MIDCMD_DATA8[0], sizeof(mmSDMA0_RLC0_MIDCMD_DATA8)/sizeof(mmSDMA0_RLC0_MIDCMD_DATA8[0]), 0, 0 }, + { "mmSDMA0_RLC0_MIDCMD_CNTL", REG_MMIO, 0x0189, 0, &mmSDMA0_RLC0_MIDCMD_CNTL[0], sizeof(mmSDMA0_RLC0_MIDCMD_CNTL)/sizeof(mmSDMA0_RLC0_MIDCMD_CNTL[0]), 0, 0 }, + { "mmSDMA0_RLC1_RB_CNTL", REG_MMIO, 0x01a0, 0, &mmSDMA0_RLC1_RB_CNTL[0], sizeof(mmSDMA0_RLC1_RB_CNTL)/sizeof(mmSDMA0_RLC1_RB_CNTL[0]), 0, 0 }, + { "mmSDMA0_RLC1_RB_BASE", REG_MMIO, 0x01a1, 0, &mmSDMA0_RLC1_RB_BASE[0], sizeof(mmSDMA0_RLC1_RB_BASE)/sizeof(mmSDMA0_RLC1_RB_BASE[0]), 0, 0 }, + { "mmSDMA0_RLC1_RB_BASE_HI", REG_MMIO, 0x01a2, 0, &mmSDMA0_RLC1_RB_BASE_HI[0], sizeof(mmSDMA0_RLC1_RB_BASE_HI)/sizeof(mmSDMA0_RLC1_RB_BASE_HI[0]), 0, 0 }, + { "mmSDMA0_RLC1_RB_RPTR", REG_MMIO, 0x01a3, 0, &mmSDMA0_RLC1_RB_RPTR[0], sizeof(mmSDMA0_RLC1_RB_RPTR)/sizeof(mmSDMA0_RLC1_RB_RPTR[0]), 0, 0 }, + { "mmSDMA0_RLC1_RB_RPTR_HI", REG_MMIO, 0x01a4, 0, &mmSDMA0_RLC1_RB_RPTR_HI[0], sizeof(mmSDMA0_RLC1_RB_RPTR_HI)/sizeof(mmSDMA0_RLC1_RB_RPTR_HI[0]), 0, 0 }, + { "mmSDMA0_RLC1_RB_WPTR", REG_MMIO, 0x01a5, 0, &mmSDMA0_RLC1_RB_WPTR[0], sizeof(mmSDMA0_RLC1_RB_WPTR)/sizeof(mmSDMA0_RLC1_RB_WPTR[0]), 0, 0 }, + { "mmSDMA0_RLC1_RB_WPTR_HI", REG_MMIO, 0x01a6, 0, &mmSDMA0_RLC1_RB_WPTR_HI[0], sizeof(mmSDMA0_RLC1_RB_WPTR_HI)/sizeof(mmSDMA0_RLC1_RB_WPTR_HI[0]), 0, 0 }, + { "mmSDMA0_RLC1_RB_WPTR_POLL_CNTL", REG_MMIO, 0x01a7, 0, &mmSDMA0_RLC1_RB_WPTR_POLL_CNTL[0], sizeof(mmSDMA0_RLC1_RB_WPTR_POLL_CNTL)/sizeof(mmSDMA0_RLC1_RB_WPTR_POLL_CNTL[0]), 0, 0 }, + { "mmSDMA0_RLC1_RB_RPTR_ADDR_HI", REG_MMIO, 0x01a8, 0, &mmSDMA0_RLC1_RB_RPTR_ADDR_HI[0], sizeof(mmSDMA0_RLC1_RB_RPTR_ADDR_HI)/sizeof(mmSDMA0_RLC1_RB_RPTR_ADDR_HI[0]), 0, 0 }, + { "mmSDMA0_RLC1_RB_RPTR_ADDR_LO", REG_MMIO, 0x01a9, 0, &mmSDMA0_RLC1_RB_RPTR_ADDR_LO[0], sizeof(mmSDMA0_RLC1_RB_RPTR_ADDR_LO)/sizeof(mmSDMA0_RLC1_RB_RPTR_ADDR_LO[0]), 0, 0 }, + { "mmSDMA0_RLC1_IB_CNTL", REG_MMIO, 0x01aa, 0, &mmSDMA0_RLC1_IB_CNTL[0], sizeof(mmSDMA0_RLC1_IB_CNTL)/sizeof(mmSDMA0_RLC1_IB_CNTL[0]), 0, 0 }, + { "mmSDMA0_RLC1_IB_RPTR", REG_MMIO, 0x01ab, 0, &mmSDMA0_RLC1_IB_RPTR[0], sizeof(mmSDMA0_RLC1_IB_RPTR)/sizeof(mmSDMA0_RLC1_IB_RPTR[0]), 0, 0 }, + { "mmSDMA0_RLC1_IB_OFFSET", REG_MMIO, 0x01ac, 0, &mmSDMA0_RLC1_IB_OFFSET[0], sizeof(mmSDMA0_RLC1_IB_OFFSET)/sizeof(mmSDMA0_RLC1_IB_OFFSET[0]), 0, 0 }, + { "mmSDMA0_RLC1_IB_BASE_LO", REG_MMIO, 0x01ad, 0, &mmSDMA0_RLC1_IB_BASE_LO[0], sizeof(mmSDMA0_RLC1_IB_BASE_LO)/sizeof(mmSDMA0_RLC1_IB_BASE_LO[0]), 0, 0 }, + { "mmSDMA0_RLC1_IB_BASE_HI", REG_MMIO, 0x01ae, 0, &mmSDMA0_RLC1_IB_BASE_HI[0], sizeof(mmSDMA0_RLC1_IB_BASE_HI)/sizeof(mmSDMA0_RLC1_IB_BASE_HI[0]), 0, 0 }, + { "mmSDMA0_RLC1_IB_SIZE", REG_MMIO, 0x01af, 0, &mmSDMA0_RLC1_IB_SIZE[0], sizeof(mmSDMA0_RLC1_IB_SIZE)/sizeof(mmSDMA0_RLC1_IB_SIZE[0]), 0, 0 }, + { "mmSDMA0_RLC1_SKIP_CNTL", REG_MMIO, 0x01b0, 0, &mmSDMA0_RLC1_SKIP_CNTL[0], sizeof(mmSDMA0_RLC1_SKIP_CNTL)/sizeof(mmSDMA0_RLC1_SKIP_CNTL[0]), 0, 0 }, + { "mmSDMA0_RLC1_CONTEXT_STATUS", REG_MMIO, 0x01b1, 0, &mmSDMA0_RLC1_CONTEXT_STATUS[0], sizeof(mmSDMA0_RLC1_CONTEXT_STATUS)/sizeof(mmSDMA0_RLC1_CONTEXT_STATUS[0]), 0, 0 }, + { "mmSDMA0_RLC1_DOORBELL", REG_MMIO, 0x01b2, 0, &mmSDMA0_RLC1_DOORBELL[0], sizeof(mmSDMA0_RLC1_DOORBELL)/sizeof(mmSDMA0_RLC1_DOORBELL[0]), 0, 0 }, + { "mmSDMA0_RLC1_STATUS", REG_MMIO, 0x01c8, 0, &mmSDMA0_RLC1_STATUS[0], sizeof(mmSDMA0_RLC1_STATUS)/sizeof(mmSDMA0_RLC1_STATUS[0]), 0, 0 }, + { "mmSDMA0_RLC1_DOORBELL_LOG", REG_MMIO, 0x01c9, 0, &mmSDMA0_RLC1_DOORBELL_LOG[0], sizeof(mmSDMA0_RLC1_DOORBELL_LOG)/sizeof(mmSDMA0_RLC1_DOORBELL_LOG[0]), 0, 0 }, + { "mmSDMA0_RLC1_WATERMARK", REG_MMIO, 0x01ca, 0, &mmSDMA0_RLC1_WATERMARK[0], sizeof(mmSDMA0_RLC1_WATERMARK)/sizeof(mmSDMA0_RLC1_WATERMARK[0]), 0, 0 }, + { "mmSDMA0_RLC1_DOORBELL_OFFSET", REG_MMIO, 0x01cb, 0, &mmSDMA0_RLC1_DOORBELL_OFFSET[0], sizeof(mmSDMA0_RLC1_DOORBELL_OFFSET)/sizeof(mmSDMA0_RLC1_DOORBELL_OFFSET[0]), 0, 0 }, + { "mmSDMA0_RLC1_CSA_ADDR_LO", REG_MMIO, 0x01cc, 0, &mmSDMA0_RLC1_CSA_ADDR_LO[0], sizeof(mmSDMA0_RLC1_CSA_ADDR_LO)/sizeof(mmSDMA0_RLC1_CSA_ADDR_LO[0]), 0, 0 }, + { "mmSDMA0_RLC1_CSA_ADDR_HI", REG_MMIO, 0x01cd, 0, &mmSDMA0_RLC1_CSA_ADDR_HI[0], sizeof(mmSDMA0_RLC1_CSA_ADDR_HI)/sizeof(mmSDMA0_RLC1_CSA_ADDR_HI[0]), 0, 0 }, + { "mmSDMA0_RLC1_IB_SUB_REMAIN", REG_MMIO, 0x01cf, 0, &mmSDMA0_RLC1_IB_SUB_REMAIN[0], sizeof(mmSDMA0_RLC1_IB_SUB_REMAIN)/sizeof(mmSDMA0_RLC1_IB_SUB_REMAIN[0]), 0, 0 }, + { "mmSDMA0_RLC1_PREEMPT", REG_MMIO, 0x01d0, 0, &mmSDMA0_RLC1_PREEMPT[0], sizeof(mmSDMA0_RLC1_PREEMPT)/sizeof(mmSDMA0_RLC1_PREEMPT[0]), 0, 0 }, + { "mmSDMA0_RLC1_DUMMY_REG", REG_MMIO, 0x01d1, 0, &mmSDMA0_RLC1_DUMMY_REG[0], sizeof(mmSDMA0_RLC1_DUMMY_REG)/sizeof(mmSDMA0_RLC1_DUMMY_REG[0]), 0, 0 }, + { "mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI", REG_MMIO, 0x01d2, 0, &mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI[0], sizeof(mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI)/sizeof(mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI[0]), 0, 0 }, + { "mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO", REG_MMIO, 0x01d3, 0, &mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO[0], sizeof(mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO)/sizeof(mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO[0]), 0, 0 }, + { "mmSDMA0_RLC1_RB_AQL_CNTL", REG_MMIO, 0x01d4, 0, &mmSDMA0_RLC1_RB_AQL_CNTL[0], sizeof(mmSDMA0_RLC1_RB_AQL_CNTL)/sizeof(mmSDMA0_RLC1_RB_AQL_CNTL[0]), 0, 0 }, + { "mmSDMA0_RLC1_MINOR_PTR_UPDATE", REG_MMIO, 0x01d5, 0, &mmSDMA0_RLC1_MINOR_PTR_UPDATE[0], sizeof(mmSDMA0_RLC1_MINOR_PTR_UPDATE)/sizeof(mmSDMA0_RLC1_MINOR_PTR_UPDATE[0]), 0, 0 }, + { "mmSDMA0_RLC1_MIDCMD_DATA0", REG_MMIO, 0x01e0, 0, &mmSDMA0_RLC1_MIDCMD_DATA0[0], sizeof(mmSDMA0_RLC1_MIDCMD_DATA0)/sizeof(mmSDMA0_RLC1_MIDCMD_DATA0[0]), 0, 0 }, + { "mmSDMA0_RLC1_MIDCMD_DATA1", REG_MMIO, 0x01e1, 0, &mmSDMA0_RLC1_MIDCMD_DATA1[0], sizeof(mmSDMA0_RLC1_MIDCMD_DATA1)/sizeof(mmSDMA0_RLC1_MIDCMD_DATA1[0]), 0, 0 }, + { "mmSDMA0_RLC1_MIDCMD_DATA2", REG_MMIO, 0x01e2, 0, &mmSDMA0_RLC1_MIDCMD_DATA2[0], sizeof(mmSDMA0_RLC1_MIDCMD_DATA2)/sizeof(mmSDMA0_RLC1_MIDCMD_DATA2[0]), 0, 0 }, + { "mmSDMA0_RLC1_MIDCMD_DATA3", REG_MMIO, 0x01e3, 0, &mmSDMA0_RLC1_MIDCMD_DATA3[0], sizeof(mmSDMA0_RLC1_MIDCMD_DATA3)/sizeof(mmSDMA0_RLC1_MIDCMD_DATA3[0]), 0, 0 }, + { "mmSDMA0_RLC1_MIDCMD_DATA4", REG_MMIO, 0x01e4, 0, &mmSDMA0_RLC1_MIDCMD_DATA4[0], sizeof(mmSDMA0_RLC1_MIDCMD_DATA4)/sizeof(mmSDMA0_RLC1_MIDCMD_DATA4[0]), 0, 0 }, + { "mmSDMA0_RLC1_MIDCMD_DATA5", REG_MMIO, 0x01e5, 0, &mmSDMA0_RLC1_MIDCMD_DATA5[0], sizeof(mmSDMA0_RLC1_MIDCMD_DATA5)/sizeof(mmSDMA0_RLC1_MIDCMD_DATA5[0]), 0, 0 }, + { "mmSDMA0_RLC1_MIDCMD_DATA6", REG_MMIO, 0x01e6, 0, &mmSDMA0_RLC1_MIDCMD_DATA6[0], sizeof(mmSDMA0_RLC1_MIDCMD_DATA6)/sizeof(mmSDMA0_RLC1_MIDCMD_DATA6[0]), 0, 0 }, + { "mmSDMA0_RLC1_MIDCMD_DATA7", REG_MMIO, 0x01e7, 0, &mmSDMA0_RLC1_MIDCMD_DATA7[0], sizeof(mmSDMA0_RLC1_MIDCMD_DATA7)/sizeof(mmSDMA0_RLC1_MIDCMD_DATA7[0]), 0, 0 }, + { "mmSDMA0_RLC1_MIDCMD_DATA8", REG_MMIO, 0x01e8, 0, &mmSDMA0_RLC1_MIDCMD_DATA8[0], sizeof(mmSDMA0_RLC1_MIDCMD_DATA8)/sizeof(mmSDMA0_RLC1_MIDCMD_DATA8[0]), 0, 0 }, + { "mmSDMA0_RLC1_MIDCMD_CNTL", REG_MMIO, 0x01e9, 0, &mmSDMA0_RLC1_MIDCMD_CNTL[0], sizeof(mmSDMA0_RLC1_MIDCMD_CNTL)/sizeof(mmSDMA0_RLC1_MIDCMD_CNTL[0]), 0, 0 }, diff --git a/src/lib/ip/vcn10.c b/src/lib/ip/vcn10.c new file mode 100644 index 0000000..70393cc --- /dev/null +++ b/src/lib/ip/vcn10.c @@ -0,0 +1,55 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Tom St Denis <tom.stdenis@amd.com> + * + */ +#include "umr.h" + +#include "vcn10_bits.i" + +static const struct umr_reg_soc15 vcn10_registers[] = { +#include "vcn10_regs.i" +}; + +struct umr_ip_block *umr_create_vcn10(struct umr_ip_offsets_soc15 *soc15_offsets, struct umr_options *options) +{ + struct umr_ip_block *ip; + + ip = calloc(1, sizeof *ip); + if (!ip) + return NULL; + + ip->ipname = "vcn10"; + ip->no_regs = sizeof(vcn10_registers)/sizeof(vcn10_registers[0]); + ip->regs = calloc(ip->no_regs, sizeof(ip->regs[0])); + if (!ip->regs) { + free(ip); + return NULL; + } + + if (umr_transfer_soc15_to_reg(options, soc15_offsets, "VCN", vcn10_registers, ip)) { + free(ip); + return NULL; + } + + return ip; +} diff --git a/src/lib/ip/vcn10_bits.i b/src/lib/ip/vcn10_bits.i new file mode 100644 index 0000000..de7bd22 --- /dev/null +++ b/src/lib/ip/vcn10_bits.i @@ -0,0 +1,871 @@ +static struct umr_bitfield mmUVD_PGFSM_CONFIG[] = { + { "UVDM_PWR_CONFIG", 0, 1, &umr_bitfield_default }, + { "UVDU_PWR_CONFIG", 2, 3, &umr_bitfield_default }, + { "UVDF_PWR_CONFIG", 4, 5, &umr_bitfield_default }, + { "UVDC_PWR_CONFIG", 6, 7, &umr_bitfield_default }, + { "UVDB_PWR_CONFIG", 8, 9, &umr_bitfield_default }, + { "UVDIL_PWR_CONFIG", 10, 11, &umr_bitfield_default }, + { "UVDIR_PWR_CONFIG", 12, 13, &umr_bitfield_default }, + { "UVDTD_PWR_CONFIG", 14, 15, &umr_bitfield_default }, + { "UVDTE_PWR_CONFIG", 16, 17, &umr_bitfield_default }, + { "UVDE_PWR_CONFIG", 18, 19, &umr_bitfield_default }, + { "UVDW_PWR_CONFIG", 20, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_PGFSM_STATUS[] = { + { "UVDM_PWR_STATUS", 0, 1, &umr_bitfield_default }, + { "UVDU_PWR_STATUS", 2, 3, &umr_bitfield_default }, + { "UVDF_PWR_STATUS", 4, 5, &umr_bitfield_default }, + { "UVDC_PWR_STATUS", 6, 7, &umr_bitfield_default }, + { "UVDB_PWR_STATUS", 8, 9, &umr_bitfield_default }, + { "UVDIL_PWR_STATUS", 10, 11, &umr_bitfield_default }, + { "UVDIR_PWR_STATUS", 12, 13, &umr_bitfield_default }, + { "UVDTD_PWR_STATUS", 14, 15, &umr_bitfield_default }, + { "UVDTE_PWR_STATUS", 16, 17, &umr_bitfield_default }, + { "UVDE_PWR_STATUS", 18, 19, &umr_bitfield_default }, + { "UVDW_PWR_STATUS", 20, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_POWER_STATUS[] = { + { "UVD_POWER_STATUS", 0, 1, &umr_bitfield_default }, + { "UVD_PG_MODE", 2, 2, &umr_bitfield_default }, + { "UVD_CG_MODE", 4, 5, &umr_bitfield_default }, + { "UVD_PG_EN", 8, 8, &umr_bitfield_default }, + { "RBC_SNOOP_DIS", 9, 9, &umr_bitfield_default }, + { "JRBC_SNOOP_DIS", 10, 10, &umr_bitfield_default }, + { "SW_RB_SNOOP_DIS", 11, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmCC_UVD_HARVESTING[] = { + { "UVD_DISABLE", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_SCRATCH1[] = { + { "SCRATCH1_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_SCRATCH2[] = { + { "SCRATCH2_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_SCRATCH3[] = { + { "SCRATCH3_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_SCRATCH4[] = { + { "SCRATCH4_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_SCRATCH5[] = { + { "SCRATCH5_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_SCRATCH6[] = { + { "SCRATCH6_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_SCRATCH7[] = { + { "SCRATCH7_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_SCRATCH8[] = { + { "SCRATCH8_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_SCRATCH9[] = { + { "SCRATCH9_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_SCRATCH10[] = { + { "SCRATCH10_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_SCRATCH11[] = { + { "SCRATCH11_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_SCRATCH12[] = { + { "SCRATCH12_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_SCRATCH13[] = { + { "SCRATCH13_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_SCRATCH14[] = { + { "SCRATCH14_DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW[] = { + { "BITS_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH[] = { + { "BITS_63_32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_DPG_VCPU_CACHE_OFFSET0[] = { + { "CACHE_OFFSET0", 0, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_LCM_CGC_CNTRL[] = { + { "FORCE_OFF", 18, 18, &umr_bitfield_default }, + { "FORCE_ON", 19, 19, &umr_bitfield_default }, + { "OFF_DELAY", 20, 27, &umr_bitfield_default }, + { "ON_DELAY", 28, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_JPEG_CNTL[] = { + { "SOFT_RESET", 0, 0, &umr_bitfield_default }, + { "REQUEST_EN", 1, 1, &umr_bitfield_default }, + { "ERR_RST_EN", 2, 2, &umr_bitfield_default }, + { "HUFF_SPEED_EN", 3, 3, &umr_bitfield_default }, + { "HUFF_SPEED_STATUS", 4, 4, &umr_bitfield_default }, + { "DBG_MUX_SEL", 8, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_JPEG_RB_BASE[] = { + { "RB_BYTE_OFF", 0, 5, &umr_bitfield_default }, + { "RB_BASE", 6, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_JPEG_RB_WPTR[] = { + { "RB_WPTR", 4, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_JPEG_RB_RPTR[] = { + { "RB_RPTR", 4, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_JPEG_RB_SIZE[] = { + { "RB_SIZE", 4, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_JPEG_ADDR_CONFIG[] = { + { "NUM_PIPES", 0, 2, &umr_bitfield_default }, + { "PIPE_INTERLEAVE_SIZE", 3, 5, &umr_bitfield_default }, + { "MAX_COMPRESSED_FRAGS", 6, 7, &umr_bitfield_default }, + { "BANK_INTERLEAVE_SIZE", 8, 10, &umr_bitfield_default }, + { "NUM_BANKS", 12, 14, &umr_bitfield_default }, + { "SHADER_ENGINE_TILE_SIZE", 16, 18, &umr_bitfield_default }, + { "NUM_SHADER_ENGINES", 19, 20, &umr_bitfield_default }, + { "NUM_GPUS", 21, 23, &umr_bitfield_default }, + { "MULTI_GPU_TILE_SIZE", 24, 25, &umr_bitfield_default }, + { "NUM_RB_PER_SE", 26, 27, &umr_bitfield_default }, + { "ROW_SIZE", 28, 29, &umr_bitfield_default }, + { "NUM_LOWER_PIPES", 30, 30, &umr_bitfield_default }, + { "SE_ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_JPEG_GPCOM_CMD[] = { + { "CMD_SEND", 0, 0, &umr_bitfield_default }, + { "CMD", 1, 30, &umr_bitfield_default }, + { "CMD_SOURCE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_JPEG_GPCOM_DATA0[] = { + { "DATA0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_JPEG_GPCOM_DATA1[] = { + { "DATA1", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_JPEG_JRB_BASE_LO[] = { + { "JRB_BASE_LO", 6, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_JPEG_JRB_BASE_HI[] = { + { "JRB_BASE_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_JPEG_JRB_SIZE[] = { + { "JRB_SIZE", 4, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_JPEG_JRB_RPTR[] = { + { "JRB_RPTR", 4, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_JPEG_JRB_WPTR[] = { + { "JRB_WPTR", 4, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_JPEG_UV_ADDR_CONFIG[] = { + { "NUM_PIPES", 0, 2, &umr_bitfield_default }, + { "PIPE_INTERLEAVE_SIZE", 3, 5, &umr_bitfield_default }, + { "MAX_COMPRESSED_FRAGS", 6, 7, &umr_bitfield_default }, + { "BANK_INTERLEAVE_SIZE", 8, 10, &umr_bitfield_default }, + { "NUM_BANKS", 12, 14, &umr_bitfield_default }, + { "SHADER_ENGINE_TILE_SIZE", 16, 18, &umr_bitfield_default }, + { "NUM_SHADER_ENGINES", 19, 20, &umr_bitfield_default }, + { "NUM_GPUS", 21, 23, &umr_bitfield_default }, + { "MULTI_GPU_TILE_SIZE", 24, 25, &umr_bitfield_default }, + { "NUM_RB_PER_SE", 26, 27, &umr_bitfield_default }, + { "ROW_SIZE", 28, 29, &umr_bitfield_default }, + { "NUM_LOWER_PIPES", 30, 30, &umr_bitfield_default }, + { "SE_ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_SEMA_ADDR_LOW[] = { + { "ADDR_26_3", 0, 23, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_SEMA_ADDR_HIGH[] = { + { "ADDR_47_27", 0, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_SEMA_CMD[] = { + { "REQ_CMD", 0, 3, &umr_bitfield_default }, + { "WR_PHASE", 4, 5, &umr_bitfield_default }, + { "MODE", 6, 6, &umr_bitfield_default }, + { "VMID_EN", 7, 7, &umr_bitfield_default }, + { "VMID", 8, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_GPCOM_VCPU_CMD[] = { + { "CMD_SEND", 0, 0, &umr_bitfield_default }, + { "CMD", 1, 30, &umr_bitfield_default }, + { "CMD_SOURCE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_GPCOM_VCPU_DATA0[] = { + { "DATA0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_GPCOM_VCPU_DATA1[] = { + { "DATA1", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_UDEC_DBW_UV_ADDR_CONFIG[] = { + { "NUM_PIPES", 0, 2, &umr_bitfield_default }, + { "PIPE_INTERLEAVE_SIZE", 3, 5, &umr_bitfield_default }, + { "MAX_COMPRESSED_FRAGS", 6, 7, &umr_bitfield_default }, + { "BANK_INTERLEAVE_SIZE", 8, 10, &umr_bitfield_default }, + { "NUM_BANKS", 12, 14, &umr_bitfield_default }, + { "SHADER_ENGINE_TILE_SIZE", 16, 18, &umr_bitfield_default }, + { "NUM_SHADER_ENGINES", 19, 20, &umr_bitfield_default }, + { "NUM_GPUS", 21, 23, &umr_bitfield_default }, + { "MULTI_GPU_TILE_SIZE", 24, 25, &umr_bitfield_default }, + { "NUM_RB_PER_SE", 26, 27, &umr_bitfield_default }, + { "ROW_SIZE", 28, 29, &umr_bitfield_default }, + { "NUM_LOWER_PIPES", 30, 30, &umr_bitfield_default }, + { "SE_ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_UDEC_ADDR_CONFIG[] = { + { "NUM_PIPES", 0, 2, &umr_bitfield_default }, + { "PIPE_INTERLEAVE_SIZE", 3, 5, &umr_bitfield_default }, + { "MAX_COMPRESSED_FRAGS", 6, 7, &umr_bitfield_default }, + { "BANK_INTERLEAVE_SIZE", 8, 10, &umr_bitfield_default }, + { "NUM_BANKS", 12, 14, &umr_bitfield_default }, + { "SHADER_ENGINE_TILE_SIZE", 16, 18, &umr_bitfield_default }, + { "NUM_SHADER_ENGINES", 19, 20, &umr_bitfield_default }, + { "NUM_GPUS", 21, 23, &umr_bitfield_default }, + { "MULTI_GPU_TILE_SIZE", 24, 25, &umr_bitfield_default }, + { "NUM_RB_PER_SE", 26, 27, &umr_bitfield_default }, + { "ROW_SIZE", 28, 29, &umr_bitfield_default }, + { "NUM_LOWER_PIPES", 30, 30, &umr_bitfield_default }, + { "SE_ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_UDEC_DB_ADDR_CONFIG[] = { + { "NUM_PIPES", 0, 2, &umr_bitfield_default }, + { "PIPE_INTERLEAVE_SIZE", 3, 5, &umr_bitfield_default }, + { "MAX_COMPRESSED_FRAGS", 6, 7, &umr_bitfield_default }, + { "BANK_INTERLEAVE_SIZE", 8, 10, &umr_bitfield_default }, + { "NUM_BANKS", 12, 14, &umr_bitfield_default }, + { "SHADER_ENGINE_TILE_SIZE", 16, 18, &umr_bitfield_default }, + { "NUM_SHADER_ENGINES", 19, 20, &umr_bitfield_default }, + { "NUM_GPUS", 21, 23, &umr_bitfield_default }, + { "MULTI_GPU_TILE_SIZE", 24, 25, &umr_bitfield_default }, + { "NUM_RB_PER_SE", 26, 27, &umr_bitfield_default }, + { "ROW_SIZE", 28, 29, &umr_bitfield_default }, + { "NUM_LOWER_PIPES", 30, 30, &umr_bitfield_default }, + { "SE_ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_UDEC_DBW_ADDR_CONFIG[] = { + { "NUM_PIPES", 0, 2, &umr_bitfield_default }, + { "PIPE_INTERLEAVE_SIZE", 3, 5, &umr_bitfield_default }, + { "MAX_COMPRESSED_FRAGS", 6, 7, &umr_bitfield_default }, + { "BANK_INTERLEAVE_SIZE", 8, 10, &umr_bitfield_default }, + { "NUM_BANKS", 12, 14, &umr_bitfield_default }, + { "SHADER_ENGINE_TILE_SIZE", 16, 18, &umr_bitfield_default }, + { "NUM_SHADER_ENGINES", 19, 20, &umr_bitfield_default }, + { "NUM_GPUS", 21, 23, &umr_bitfield_default }, + { "MULTI_GPU_TILE_SIZE", 24, 25, &umr_bitfield_default }, + { "NUM_RB_PER_SE", 26, 27, &umr_bitfield_default }, + { "ROW_SIZE", 28, 29, &umr_bitfield_default }, + { "NUM_LOWER_PIPES", 30, 30, &umr_bitfield_default }, + { "SE_ENABLE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_SUVD_CGC_GATE[] = { + { "SRE", 0, 0, &umr_bitfield_default }, + { "SIT", 1, 1, &umr_bitfield_default }, + { "SMP", 2, 2, &umr_bitfield_default }, + { "SCM", 3, 3, &umr_bitfield_default }, + { "SDB", 4, 4, &umr_bitfield_default }, + { "SRE_H264", 5, 5, &umr_bitfield_default }, + { "SRE_HEVC", 6, 6, &umr_bitfield_default }, + { "SIT_H264", 7, 7, &umr_bitfield_default }, + { "SIT_HEVC", 8, 8, &umr_bitfield_default }, + { "SCM_H264", 9, 9, &umr_bitfield_default }, + { "SCM_HEVC", 10, 10, &umr_bitfield_default }, + { "SDB_H264", 11, 11, &umr_bitfield_default }, + { "SDB_HEVC", 12, 12, &umr_bitfield_default }, + { "SCLR", 13, 13, &umr_bitfield_default }, + { "UVD_SC", 14, 14, &umr_bitfield_default }, + { "ENT", 15, 15, &umr_bitfield_default }, + { "IME", 16, 16, &umr_bitfield_default }, + { "SIT_HEVC_DEC", 17, 17, &umr_bitfield_default }, + { "SIT_HEVC_ENC", 18, 18, &umr_bitfield_default }, + { "SITE", 19, 19, &umr_bitfield_default }, + { "SRE_VP9", 20, 20, &umr_bitfield_default }, + { "SCM_VP9", 21, 21, &umr_bitfield_default }, + { "SIT_VP9_DEC", 22, 22, &umr_bitfield_default }, + { "SDB_VP9", 23, 23, &umr_bitfield_default }, + { "IME_HEVC", 24, 24, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_SUVD_CGC_STATUS[] = { + { "SRE_VCLK", 0, 0, &umr_bitfield_default }, + { "SRE_DCLK", 1, 1, &umr_bitfield_default }, + { "SIT_DCLK", 2, 2, &umr_bitfield_default }, + { "SMP_DCLK", 3, 3, &umr_bitfield_default }, + { "SCM_DCLK", 4, 4, &umr_bitfield_default }, + { "SDB_DCLK", 5, 5, &umr_bitfield_default }, + { "SRE_H264_VCLK", 6, 6, &umr_bitfield_default }, + { "SRE_HEVC_VCLK", 7, 7, &umr_bitfield_default }, + { "SIT_H264_DCLK", 8, 8, &umr_bitfield_default }, + { "SIT_HEVC_DCLK", 9, 9, &umr_bitfield_default }, + { "SCM_H264_DCLK", 10, 10, &umr_bitfield_default }, + { "SCM_HEVC_DCLK", 11, 11, &umr_bitfield_default }, + { "SDB_H264_DCLK", 12, 12, &umr_bitfield_default }, + { "SDB_HEVC_DCLK", 13, 13, &umr_bitfield_default }, + { "SCLR_DCLK", 14, 14, &umr_bitfield_default }, + { "UVD_SC", 15, 15, &umr_bitfield_default }, + { "ENT_DCLK", 16, 16, &umr_bitfield_default }, + { "IME_DCLK", 17, 17, &umr_bitfield_default }, + { "SIT_HEVC_DEC_DCLK", 18, 18, &umr_bitfield_default }, + { "SIT_HEVC_ENC_DCLK", 19, 19, &umr_bitfield_default }, + { "SITE_DCLK", 20, 20, &umr_bitfield_default }, + { "SITE_HEVC_DCLK", 21, 21, &umr_bitfield_default }, + { "SITE_HEVC_ENC_DCLK", 22, 22, &umr_bitfield_default }, + { "SRE_VP9_VCLK", 23, 23, &umr_bitfield_default }, + { "SCM_VP9_VCLK", 24, 24, &umr_bitfield_default }, + { "SIT_VP9_DEC_DCLK", 25, 25, &umr_bitfield_default }, + { "SDB_VP9_DCLK", 26, 26, &umr_bitfield_default }, + { "IME_HEVC_DCLK", 27, 27, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_SUVD_CGC_CTRL[] = { + { "SRE_MODE", 0, 0, &umr_bitfield_default }, + { "SIT_MODE", 1, 1, &umr_bitfield_default }, + { "SMP_MODE", 2, 2, &umr_bitfield_default }, + { "SCM_MODE", 3, 3, &umr_bitfield_default }, + { "SDB_MODE", 4, 4, &umr_bitfield_default }, + { "SCLR_MODE", 5, 5, &umr_bitfield_default }, + { "UVD_SC_MODE", 6, 6, &umr_bitfield_default }, + { "ENT_MODE", 7, 7, &umr_bitfield_default }, + { "IME_MODE", 8, 8, &umr_bitfield_default }, + { "SITE_MODE", 9, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW[] = { + { "BITS_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH[] = { + { "BITS_63_32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW[] = { + { "BITS_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH[] = { + { "BITS_63_32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_NO_OP[] = { + { "NO_OP", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_VERSION[] = { + { "MINOR_VERSION", 0, 15, &umr_bitfield_default }, + { "MAJOR_VERSION", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_GP_SCRATCH8[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_GP_SCRATCH9[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_GP_SCRATCH10[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_GP_SCRATCH11[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_GP_SCRATCH12[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_GP_SCRATCH13[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_GP_SCRATCH14[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_GP_SCRATCH15[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_GP_SCRATCH16[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_GP_SCRATCH17[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_GP_SCRATCH18[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_GP_SCRATCH19[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_GP_SCRATCH20[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_GP_SCRATCH21[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_GP_SCRATCH22[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_GP_SCRATCH23[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_RB_BASE_LO2[] = { + { "RB_BASE_LO", 6, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_RB_BASE_HI2[] = { + { "RB_BASE_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_RB_SIZE2[] = { + { "RB_SIZE", 4, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_RB_RPTR2[] = { + { "RB_RPTR", 4, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_RB_WPTR2[] = { + { "RB_WPTR", 4, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_RB_BASE_LO[] = { + { "RB_BASE_LO", 6, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_RB_BASE_HI[] = { + { "RB_BASE_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_RB_SIZE[] = { + { "RB_SIZE", 4, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_RB_RPTR[] = { + { "RB_RPTR", 4, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_RB_WPTR[] = { + { "RB_WPTR", 4, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_RB_WPTR4[] = { + { "RB_WPTR", 4, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_JRBC_RB_RPTR[] = { + { "RB_RPTR", 4, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH[] = { + { "BITS_63_32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW[] = { + { "BITS_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH[] = { + { "BITS_63_32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_LMI_RBC_IB_64BIT_BAR_LOW[] = { + { "BITS_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH[] = { + { "BITS_63_32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_LMI_RBC_RB_64BIT_BAR_LOW[] = { + { "BITS_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_SEMA_CNTL[] = { + { "SEMAPHORE_EN", 0, 0, &umr_bitfield_default }, + { "ADVANCED_MODE_DIS", 1, 1, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW[] = { + { "BITS_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH[] = { + { "BITS_63_32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW[] = { + { "BITS_31_0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH[] = { + { "BITS_63_32", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_LMI_JRBC_IB_VMID[] = { + { "IB_WR_VMID", 0, 3, &umr_bitfield_default }, + { "IB_RD_VMID", 4, 7, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_JRBC_RB_WPTR[] = { + { "RB_WPTR", 4, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_JRBC_RB_CNTL[] = { + { "RB_NO_FETCH", 0, 0, &umr_bitfield_default }, + { "RB_RPTR_WR_EN", 1, 1, &umr_bitfield_default }, + { "RB_PRE_WRITE_TIMER", 4, 18, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_JRBC_IB_SIZE[] = { + { "IB_SIZE", 4, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_JRBC_LMI_SWAP_CNTL[] = { + { "RB_MC_SWAP", 0, 1, &umr_bitfield_default }, + { "IB_MC_SWAP", 2, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_JRBC_SOFT_RESET[] = { + { "RESET", 0, 0, &umr_bitfield_default }, + { "VCLK_RESET_STATUS", 16, 16, &umr_bitfield_default }, + { "SCLK_RESET_STATUS", 17, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_JRBC_STATUS[] = { + { "RB_JOB_DONE", 0, 0, &umr_bitfield_default }, + { "IB_JOB_DONE", 1, 1, &umr_bitfield_default }, + { "RB_ILLEGAL_CMD", 2, 2, &umr_bitfield_default }, + { "RB_COND_REG_RD_TIMEOUT", 3, 3, &umr_bitfield_default }, + { "RB_MEM_WR_TIMEOUT", 4, 4, &umr_bitfield_default }, + { "RB_MEM_RD_TIMEOUT", 5, 5, &umr_bitfield_default }, + { "IB_ILLEGAL_CMD", 6, 6, &umr_bitfield_default }, + { "IB_COND_REG_RD_TIMEOUT", 7, 7, &umr_bitfield_default }, + { "IB_MEM_WR_TIMEOUT", 8, 8, &umr_bitfield_default }, + { "IB_MEM_RD_TIMEOUT", 9, 9, &umr_bitfield_default }, + { "RB_TRAP_STATUS", 10, 10, &umr_bitfield_default }, + { "PREEMPT_STATUS", 11, 11, &umr_bitfield_default }, + { "IB_TRAP_STATUS", 12, 12, &umr_bitfield_default }, + { "INT_EN", 16, 16, &umr_bitfield_default }, + { "INT_ACK", 17, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_RB_RPTR3[] = { + { "RB_RPTR", 4, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_RB_WPTR3[] = { + { "RB_WPTR", 4, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_RB_BASE_LO3[] = { + { "RB_BASE_LO", 6, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_RB_BASE_HI3[] = { + { "RB_BASE_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_RB_SIZE3[] = { + { "RB_SIZE", 4, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmJPEG_CGC_GATE[] = { + { "JPEG", 20, 20, &umr_bitfield_default }, + { "JPEG2", 21, 21, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_CTX_INDEX[] = { + { "INDEX", 0, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_CTX_DATA[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_CGC_GATE[] = { + { "SYS", 0, 0, &umr_bitfield_default }, + { "UDEC", 1, 1, &umr_bitfield_default }, + { "MPEG2", 2, 2, &umr_bitfield_default }, + { "REGS", 3, 3, &umr_bitfield_default }, + { "RBC", 4, 4, &umr_bitfield_default }, + { "LMI_MC", 5, 5, &umr_bitfield_default }, + { "LMI_UMC", 6, 6, &umr_bitfield_default }, + { "IDCT", 7, 7, &umr_bitfield_default }, + { "MPRD", 8, 8, &umr_bitfield_default }, + { "MPC", 9, 9, &umr_bitfield_default }, + { "LBSI", 10, 10, &umr_bitfield_default }, + { "LRBBM", 11, 11, &umr_bitfield_default }, + { "UDEC_RE", 12, 12, &umr_bitfield_default }, + { "UDEC_CM", 13, 13, &umr_bitfield_default }, + { "UDEC_IT", 14, 14, &umr_bitfield_default }, + { "UDEC_DB", 15, 15, &umr_bitfield_default }, + { "UDEC_MP", 16, 16, &umr_bitfield_default }, + { "WCB", 17, 17, &umr_bitfield_default }, + { "VCPU", 18, 18, &umr_bitfield_default }, + { "SCPU", 19, 19, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_CGC_STATUS[] = { + { "SYS_SCLK", 0, 0, &umr_bitfield_default }, + { "SYS_DCLK", 1, 1, &umr_bitfield_default }, + { "SYS_VCLK", 2, 2, &umr_bitfield_default }, + { "UDEC_SCLK", 3, 3, &umr_bitfield_default }, + { "UDEC_DCLK", 4, 4, &umr_bitfield_default }, + { "UDEC_VCLK", 5, 5, &umr_bitfield_default }, + { "MPEG2_SCLK", 6, 6, &umr_bitfield_default }, + { "MPEG2_DCLK", 7, 7, &umr_bitfield_default }, + { "MPEG2_VCLK", 8, 8, &umr_bitfield_default }, + { "REGS_SCLK", 9, 9, &umr_bitfield_default }, + { "REGS_VCLK", 10, 10, &umr_bitfield_default }, + { "RBC_SCLK", 11, 11, &umr_bitfield_default }, + { "LMI_MC_SCLK", 12, 12, &umr_bitfield_default }, + { "LMI_UMC_SCLK", 13, 13, &umr_bitfield_default }, + { "IDCT_SCLK", 14, 14, &umr_bitfield_default }, + { "IDCT_VCLK", 15, 15, &umr_bitfield_default }, + { "MPRD_SCLK", 16, 16, &umr_bitfield_default }, + { "MPRD_DCLK", 17, 17, &umr_bitfield_default }, + { "MPRD_VCLK", 18, 18, &umr_bitfield_default }, + { "MPC_SCLK", 19, 19, &umr_bitfield_default }, + { "MPC_DCLK", 20, 20, &umr_bitfield_default }, + { "LBSI_SCLK", 21, 21, &umr_bitfield_default }, + { "LBSI_VCLK", 22, 22, &umr_bitfield_default }, + { "LRBBM_SCLK", 23, 23, &umr_bitfield_default }, + { "WCB_SCLK", 24, 24, &umr_bitfield_default }, + { "VCPU_SCLK", 25, 25, &umr_bitfield_default }, + { "VCPU_VCLK", 26, 26, &umr_bitfield_default }, + { "SCPU_SCLK", 27, 27, &umr_bitfield_default }, + { "SCPU_VCLK", 28, 28, &umr_bitfield_default }, + { "ALL_ENC_ACTIVE", 29, 29, &umr_bitfield_default }, + { "JPEG_ACTIVE", 30, 30, &umr_bitfield_default }, + { "ALL_DEC_ACTIVE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_CGC_CTRL[] = { + { "DYN_CLOCK_MODE", 0, 0, &umr_bitfield_default }, + { "CLK_GATE_DLY_TIMER", 2, 5, &umr_bitfield_default }, + { "CLK_OFF_DELAY", 6, 10, &umr_bitfield_default }, + { "UDEC_RE_MODE", 11, 11, &umr_bitfield_default }, + { "UDEC_CM_MODE", 12, 12, &umr_bitfield_default }, + { "UDEC_IT_MODE", 13, 13, &umr_bitfield_default }, + { "UDEC_DB_MODE", 14, 14, &umr_bitfield_default }, + { "UDEC_MP_MODE", 15, 15, &umr_bitfield_default }, + { "SYS_MODE", 16, 16, &umr_bitfield_default }, + { "UDEC_MODE", 17, 17, &umr_bitfield_default }, + { "MPEG2_MODE", 18, 18, &umr_bitfield_default }, + { "REGS_MODE", 19, 19, &umr_bitfield_default }, + { "RBC_MODE", 20, 20, &umr_bitfield_default }, + { "LMI_MC_MODE", 21, 21, &umr_bitfield_default }, + { "LMI_UMC_MODE", 22, 22, &umr_bitfield_default }, + { "IDCT_MODE", 23, 23, &umr_bitfield_default }, + { "MPRD_MODE", 24, 24, &umr_bitfield_default }, + { "MPC_MODE", 25, 25, &umr_bitfield_default }, + { "LBSI_MODE", 26, 26, &umr_bitfield_default }, + { "LRBBM_MODE", 27, 27, &umr_bitfield_default }, + { "WCB_MODE", 28, 28, &umr_bitfield_default }, + { "VCPU_MODE", 29, 29, &umr_bitfield_default }, + { "SCPU_MODE", 30, 30, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_GP_SCRATCH0[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_GP_SCRATCH1[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_GP_SCRATCH2[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_GP_SCRATCH3[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_GP_SCRATCH4[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_GP_SCRATCH5[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_GP_SCRATCH6[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_GP_SCRATCH7[] = { + { "DATA", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_LMI_VCPU_CACHE_VMID[] = { + { "VCPU_CACHE_VMID", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_LMI_CTRL2[] = { + { "SPH_DIS", 0, 0, &umr_bitfield_default }, + { "STALL_ARB", 1, 1, &umr_bitfield_default }, + { "ASSERT_UMC_URGENT", 2, 2, &umr_bitfield_default }, + { "MASK_UMC_URGENT", 3, 3, &umr_bitfield_default }, + { "DRCITF_BUBBLE_FIX_DIS", 7, 7, &umr_bitfield_default }, + { "STALL_ARB_UMC", 8, 8, &umr_bitfield_default }, + { "MC_READ_ID_SEL", 9, 10, &umr_bitfield_default }, + { "MC_WRITE_ID_SEL", 11, 12, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_MASTINT_EN[] = { + { "OVERRUN_RST", 0, 0, &umr_bitfield_default }, + { "VCPU_EN", 1, 1, &umr_bitfield_default }, + { "SYS_EN", 2, 2, &umr_bitfield_default }, + { "INT_OVERRUN", 4, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmJPEG_CGC_CTRL[] = { + { "DYN_CLOCK_MODE", 0, 0, &umr_bitfield_default }, + { "JPEG2_MODE", 1, 1, &umr_bitfield_default }, + { "CLK_GATE_DLY_TIMER", 2, 5, &umr_bitfield_default }, + { "CLK_OFF_DELAY", 6, 10, &umr_bitfield_default }, + { "JPEG_MODE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_LMI_CTRL[] = { + { "WRITE_CLEAN_TIMER", 0, 7, &umr_bitfield_default }, + { "WRITE_CLEAN_TIMER_EN", 8, 8, &umr_bitfield_default }, + { "REQ_MODE", 9, 9, &umr_bitfield_default }, + { "ASSERT_MC_URGENT", 11, 11, &umr_bitfield_default }, + { "MASK_MC_URGENT", 12, 12, &umr_bitfield_default }, + { "DATA_COHERENCY_EN", 13, 13, &umr_bitfield_default }, + { "CRC_RESET", 14, 14, &umr_bitfield_default }, + { "CRC_SEL", 15, 19, &umr_bitfield_default }, + { "VCPU_DATA_COHERENCY_EN", 21, 21, &umr_bitfield_default }, + { "CM_DATA_COHERENCY_EN", 22, 22, &umr_bitfield_default }, + { "DB_DB_DATA_COHERENCY_EN", 23, 23, &umr_bitfield_default }, + { "DB_IT_DATA_COHERENCY_EN", 24, 24, &umr_bitfield_default }, + { "IT_IT_DATA_COHERENCY_EN", 25, 25, &umr_bitfield_default }, + { "RFU", 27, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_LMI_SWAP_CNTL[] = { + { "RB_MC_SWAP", 0, 1, &umr_bitfield_default }, + { "IB_MC_SWAP", 2, 3, &umr_bitfield_default }, + { "RB_RPTR_MC_SWAP", 4, 5, &umr_bitfield_default }, + { "VCPU_R_MC_SWAP", 6, 7, &umr_bitfield_default }, + { "VCPU_W_MC_SWAP", 8, 9, &umr_bitfield_default }, + { "CM_MC_SWAP", 10, 11, &umr_bitfield_default }, + { "IT_MC_SWAP", 12, 13, &umr_bitfield_default }, + { "DB_R_MC_SWAP", 14, 15, &umr_bitfield_default }, + { "DB_W_MC_SWAP", 16, 17, &umr_bitfield_default }, + { "CSM_MC_SWAP", 18, 19, &umr_bitfield_default }, + { "ACAP_MC_SWAP", 20, 21, &umr_bitfield_default }, + { "MP_REF16_MC_SWAP", 22, 23, &umr_bitfield_default }, + { "DBW_MC_SWAP", 24, 25, &umr_bitfield_default }, + { "RB_WR_MC_SWAP", 26, 27, &umr_bitfield_default }, + { "RE_MC_SWAP", 28, 29, &umr_bitfield_default }, + { "MP_MC_SWAP", 30, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_MPC_SET_MUXA0[] = { + { "VARA_0", 0, 5, &umr_bitfield_default }, + { "VARA_1", 6, 11, &umr_bitfield_default }, + { "VARA_2", 12, 17, &umr_bitfield_default }, + { "VARA_3", 18, 23, &umr_bitfield_default }, + { "VARA_4", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_MPC_SET_MUXA1[] = { + { "VARA_5", 0, 5, &umr_bitfield_default }, + { "VARA_6", 6, 11, &umr_bitfield_default }, + { "VARA_7", 12, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_MPC_SET_MUXB0[] = { + { "VARB_0", 0, 5, &umr_bitfield_default }, + { "VARB_1", 6, 11, &umr_bitfield_default }, + { "VARB_2", 12, 17, &umr_bitfield_default }, + { "VARB_3", 18, 23, &umr_bitfield_default }, + { "VARB_4", 24, 29, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_MPC_SET_MUXB1[] = { + { "VARB_5", 0, 5, &umr_bitfield_default }, + { "VARB_6", 6, 11, &umr_bitfield_default }, + { "VARB_7", 12, 17, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_MPC_SET_MUX[] = { + { "SET_0", 0, 2, &umr_bitfield_default }, + { "SET_1", 3, 5, &umr_bitfield_default }, + { "SET_2", 6, 8, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_MPC_SET_ALU[] = { + { "FUNCT", 0, 2, &umr_bitfield_default }, + { "OPERAND", 4, 11, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_GPCOM_SYS_CMD[] = { + { "CMD_SEND", 0, 0, &umr_bitfield_default }, + { "CMD", 1, 30, &umr_bitfield_default }, + { "CMD_SOURCE", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_GPCOM_SYS_DATA0[] = { + { "DATA0", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_GPCOM_SYS_DATA1[] = { + { "DATA1", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_VCPU_CACHE_OFFSET0[] = { + { "CACHE_OFFSET0", 0, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_VCPU_CACHE_SIZE0[] = { + { "CACHE_SIZE0", 0, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_VCPU_CACHE_OFFSET1[] = { + { "CACHE_OFFSET1", 0, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_VCPU_CACHE_SIZE1[] = { + { "CACHE_SIZE1", 0, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_VCPU_CACHE_OFFSET2[] = { + { "CACHE_OFFSET2", 0, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_VCPU_CACHE_SIZE2[] = { + { "CACHE_SIZE2", 0, 20, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_VCPU_CNTL[] = { + { "CLK_EN", 9, 9, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_SOFT_RESET[] = { + { "RBC_SOFT_RESET", 0, 0, &umr_bitfield_default }, + { "LBSI_SOFT_RESET", 1, 1, &umr_bitfield_default }, + { "LMI_SOFT_RESET", 2, 2, &umr_bitfield_default }, + { "VCPU_SOFT_RESET", 3, 3, &umr_bitfield_default }, + { "UDEC_SOFT_RESET", 4, 4, &umr_bitfield_default }, + { "CSM_SOFT_RESET", 5, 5, &umr_bitfield_default }, + { "CXW_SOFT_RESET", 6, 6, &umr_bitfield_default }, + { "TAP_SOFT_RESET", 7, 7, &umr_bitfield_default }, + { "MPC_SOFT_RESET", 8, 8, &umr_bitfield_default }, + { "IH_SOFT_RESET", 10, 10, &umr_bitfield_default }, + { "LMI_UMC_SOFT_RESET", 13, 13, &umr_bitfield_default }, + { "SPH_SOFT_RESET", 14, 14, &umr_bitfield_default }, + { "MIF_SOFT_RESET", 15, 15, &umr_bitfield_default }, + { "LCM_SOFT_RESET", 16, 16, &umr_bitfield_default }, + { "SUVD_SOFT_RESET", 17, 17, &umr_bitfield_default }, + { "LBSI_VCLK_RESET_STATUS", 18, 18, &umr_bitfield_default }, + { "VCPU_VCLK_RESET_STATUS", 19, 19, &umr_bitfield_default }, + { "UDEC_VCLK_RESET_STATUS", 20, 20, &umr_bitfield_default }, + { "UDEC_DCLK_RESET_STATUS", 21, 21, &umr_bitfield_default }, + { "MPC_DCLK_RESET_STATUS", 22, 22, &umr_bitfield_default }, + { "MIF_DCLK_RESET_STATUS", 26, 26, &umr_bitfield_default }, + { "LCM_DCLK_RESET_STATUS", 27, 27, &umr_bitfield_default }, + { "SUVD_VCLK_RESET_STATUS", 28, 28, &umr_bitfield_default }, + { "SUVD_DCLK_RESET_STATUS", 29, 29, &umr_bitfield_default }, + { "RE_DCLK_RESET_STATUS", 30, 30, &umr_bitfield_default }, + { "SRE_DCLK_RESET_STATUS", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_LMI_RBC_IB_VMID[] = { + { "IB_VMID", 0, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_RBC_IB_SIZE[] = { + { "IB_SIZE", 4, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_RBC_RB_RPTR[] = { + { "RB_RPTR", 4, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_RBC_RB_WPTR[] = { + { "RB_WPTR", 4, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_RBC_RB_WPTR_CNTL[] = { + { "RB_PRE_WRITE_TIMER", 0, 14, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_RBC_RB_CNTL[] = { + { "RB_BUFSZ", 0, 4, &umr_bitfield_default }, + { "RB_BLKSZ", 8, 12, &umr_bitfield_default }, + { "RB_NO_FETCH", 16, 16, &umr_bitfield_default }, + { "RB_WPTR_POLL_EN", 20, 20, &umr_bitfield_default }, + { "RB_NO_UPDATE", 24, 24, &umr_bitfield_default }, + { "RB_RPTR_WR_EN", 28, 28, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_RBC_RB_RPTR_ADDR[] = { + { "RB_RPTR_ADDR", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_STATUS[] = { + { "RBC_BUSY", 0, 0, &umr_bitfield_default }, + { "VCPU_REPORT", 1, 7, &umr_bitfield_default }, + { "AVP_BUSY", 8, 8, &umr_bitfield_default }, + { "IDCT_BUSY", 9, 9, &umr_bitfield_default }, + { "IDCT_CTL_ACK", 11, 11, &umr_bitfield_default }, + { "UVD_CTL_ACK", 12, 12, &umr_bitfield_default }, + { "AVP_BLOCK_ACK", 13, 13, &umr_bitfield_default }, + { "IDCT_BLOCK_ACK", 14, 14, &umr_bitfield_default }, + { "UVD_BLOCK_ACK", 15, 15, &umr_bitfield_default }, + { "RBC_ACCESS_GPCOM", 16, 16, &umr_bitfield_default }, + { "SYS_GPCOM_REQ", 31, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_SEMA_TIMEOUT_STATUS[] = { + { "SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT", 0, 0, &umr_bitfield_default }, + { "SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT", 1, 1, &umr_bitfield_default }, + { "SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT", 2, 2, &umr_bitfield_default }, + { "SEMAPHORE_TIMEOUT_CLEAR", 3, 3, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL[] = { + { "WAIT_INCOMPLETE_EN", 0, 0, &umr_bitfield_default }, + { "WAIT_INCOMPLETE_COUNT", 1, 20, &umr_bitfield_default }, + { "RESEND_TIMER", 24, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL[] = { + { "WAIT_FAULT_EN", 0, 0, &umr_bitfield_default }, + { "WAIT_FAULT_COUNT", 1, 20, &umr_bitfield_default }, + { "RESEND_TIMER", 24, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL[] = { + { "SIGNAL_INCOMPLETE_EN", 0, 0, &umr_bitfield_default }, + { "SIGNAL_INCOMPLETE_COUNT", 1, 20, &umr_bitfield_default }, + { "RESEND_TIMER", 24, 26, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_CONTEXT_ID[] = { + { "CONTEXT_ID", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_CONTEXT_ID2[] = { + { "CONTEXT_ID2", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_RBC_WPTR_POLL_CNTL[] = { + { "POLL_FREQ", 0, 15, &umr_bitfield_default }, + { "IDLE_POLL_COUNT", 16, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_RBC_WPTR_POLL_ADDR[] = { + { "POLL_ADDR", 2, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_RB_BASE_LO4[] = { + { "RB_BASE_LO", 6, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_RB_BASE_HI4[] = { + { "RB_BASE_HI", 0, 31, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_RB_SIZE4[] = { + { "RB_SIZE", 4, 22, &umr_bitfield_default }, +}; +static struct umr_bitfield mmUVD_RB_RPTR4[] = { + { "RB_RPTR", 4, 22, &umr_bitfield_default }, +}; diff --git a/src/lib/ip/vcn10_regs.i b/src/lib/ip/vcn10_regs.i new file mode 100644 index 0000000..7635b2d --- /dev/null +++ b/src/lib/ip/vcn10_regs.i @@ -0,0 +1,167 @@ + { "mmUVD_PGFSM_CONFIG", REG_MMIO, 0x00c0, 1, &mmUVD_PGFSM_CONFIG[0], sizeof(mmUVD_PGFSM_CONFIG)/sizeof(mmUVD_PGFSM_CONFIG[0]), 0, 0 }, + { "mmUVD_PGFSM_STATUS", REG_MMIO, 0x00c1, 1, &mmUVD_PGFSM_STATUS[0], sizeof(mmUVD_PGFSM_STATUS)/sizeof(mmUVD_PGFSM_STATUS[0]), 0, 0 }, + { "mmUVD_POWER_STATUS", REG_MMIO, 0x00c4, 1, &mmUVD_POWER_STATUS[0], sizeof(mmUVD_POWER_STATUS)/sizeof(mmUVD_POWER_STATUS[0]), 0, 0 }, + { "mmCC_UVD_HARVESTING", REG_MMIO, 0x00c7, 1, &mmCC_UVD_HARVESTING[0], sizeof(mmCC_UVD_HARVESTING)/sizeof(mmCC_UVD_HARVESTING[0]), 0, 0 }, + { "mmUVD_SCRATCH1", REG_MMIO, 0x00d5, 1, &mmUVD_SCRATCH1[0], sizeof(mmUVD_SCRATCH1)/sizeof(mmUVD_SCRATCH1[0]), 0, 0 }, + { "mmUVD_SCRATCH2", REG_MMIO, 0x00d6, 1, &mmUVD_SCRATCH2[0], sizeof(mmUVD_SCRATCH2)/sizeof(mmUVD_SCRATCH2[0]), 0, 0 }, + { "mmUVD_SCRATCH3", REG_MMIO, 0x00d7, 1, &mmUVD_SCRATCH3[0], sizeof(mmUVD_SCRATCH3)/sizeof(mmUVD_SCRATCH3[0]), 0, 0 }, + { "mmUVD_SCRATCH4", REG_MMIO, 0x00d8, 1, &mmUVD_SCRATCH4[0], sizeof(mmUVD_SCRATCH4)/sizeof(mmUVD_SCRATCH4[0]), 0, 0 }, + { "mmUVD_SCRATCH5", REG_MMIO, 0x00d9, 1, &mmUVD_SCRATCH5[0], sizeof(mmUVD_SCRATCH5)/sizeof(mmUVD_SCRATCH5[0]), 0, 0 }, + { "mmUVD_SCRATCH6", REG_MMIO, 0x00da, 1, &mmUVD_SCRATCH6[0], sizeof(mmUVD_SCRATCH6)/sizeof(mmUVD_SCRATCH6[0]), 0, 0 }, + { "mmUVD_SCRATCH7", REG_MMIO, 0x00db, 1, &mmUVD_SCRATCH7[0], sizeof(mmUVD_SCRATCH7)/sizeof(mmUVD_SCRATCH7[0]), 0, 0 }, + { "mmUVD_SCRATCH8", REG_MMIO, 0x00dc, 1, &mmUVD_SCRATCH8[0], sizeof(mmUVD_SCRATCH8)/sizeof(mmUVD_SCRATCH8[0]), 0, 0 }, + { "mmUVD_SCRATCH9", REG_MMIO, 0x00dd, 1, &mmUVD_SCRATCH9[0], sizeof(mmUVD_SCRATCH9)/sizeof(mmUVD_SCRATCH9[0]), 0, 0 }, + { "mmUVD_SCRATCH10", REG_MMIO, 0x00de, 1, &mmUVD_SCRATCH10[0], sizeof(mmUVD_SCRATCH10)/sizeof(mmUVD_SCRATCH10[0]), 0, 0 }, + { "mmUVD_SCRATCH11", REG_MMIO, 0x00df, 1, &mmUVD_SCRATCH11[0], sizeof(mmUVD_SCRATCH11)/sizeof(mmUVD_SCRATCH11[0]), 0, 0 }, + { "mmUVD_SCRATCH12", REG_MMIO, 0x00e0, 1, &mmUVD_SCRATCH12[0], sizeof(mmUVD_SCRATCH12)/sizeof(mmUVD_SCRATCH12[0]), 0, 0 }, + { "mmUVD_SCRATCH13", REG_MMIO, 0x00e1, 1, &mmUVD_SCRATCH13[0], sizeof(mmUVD_SCRATCH13)/sizeof(mmUVD_SCRATCH13[0]), 0, 0 }, + { "mmUVD_SCRATCH14", REG_MMIO, 0x00e2, 1, &mmUVD_SCRATCH14[0], sizeof(mmUVD_SCRATCH14)/sizeof(mmUVD_SCRATCH14[0]), 0, 0 }, + { "mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW", REG_MMIO, 0x00e5, 1, &mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW[0], sizeof(mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW)/sizeof(mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW[0]), 0, 0 }, + { "mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH", REG_MMIO, 0x00e6, 1, &mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH[0], sizeof(mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH)/sizeof(mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH[0]), 0, 0 }, + { "mmUVD_DPG_VCPU_CACHE_OFFSET0", REG_MMIO, 0x00e7, 1, &mmUVD_DPG_VCPU_CACHE_OFFSET0[0], sizeof(mmUVD_DPG_VCPU_CACHE_OFFSET0)/sizeof(mmUVD_DPG_VCPU_CACHE_OFFSET0[0]), 0, 0 }, + { "mmUVD_LCM_CGC_CNTRL", REG_MMIO, 0x0123, 1, &mmUVD_LCM_CGC_CNTRL[0], sizeof(mmUVD_LCM_CGC_CNTRL)/sizeof(mmUVD_LCM_CGC_CNTRL[0]), 0, 0 }, + { "mmUVD_JPEG_CNTL", REG_MMIO, 0x0200, 1, &mmUVD_JPEG_CNTL[0], sizeof(mmUVD_JPEG_CNTL)/sizeof(mmUVD_JPEG_CNTL[0]), 0, 0 }, + { "mmUVD_JPEG_RB_BASE", REG_MMIO, 0x0201, 1, &mmUVD_JPEG_RB_BASE[0], sizeof(mmUVD_JPEG_RB_BASE)/sizeof(mmUVD_JPEG_RB_BASE[0]), 0, 0 }, + { "mmUVD_JPEG_RB_WPTR", REG_MMIO, 0x0202, 1, &mmUVD_JPEG_RB_WPTR[0], sizeof(mmUVD_JPEG_RB_WPTR)/sizeof(mmUVD_JPEG_RB_WPTR[0]), 0, 0 }, + { "mmUVD_JPEG_RB_RPTR", REG_MMIO, 0x0203, 1, &mmUVD_JPEG_RB_RPTR[0], sizeof(mmUVD_JPEG_RB_RPTR)/sizeof(mmUVD_JPEG_RB_RPTR[0]), 0, 0 }, + { "mmUVD_JPEG_RB_SIZE", REG_MMIO, 0x0204, 1, &mmUVD_JPEG_RB_SIZE[0], sizeof(mmUVD_JPEG_RB_SIZE)/sizeof(mmUVD_JPEG_RB_SIZE[0]), 0, 0 }, + { "mmUVD_JPEG_ADDR_CONFIG", REG_MMIO, 0x021f, 1, &mmUVD_JPEG_ADDR_CONFIG[0], sizeof(mmUVD_JPEG_ADDR_CONFIG)/sizeof(mmUVD_JPEG_ADDR_CONFIG[0]), 0, 0 }, + { "mmUVD_JPEG_GPCOM_CMD", REG_MMIO, 0x022c, 1, &mmUVD_JPEG_GPCOM_CMD[0], sizeof(mmUVD_JPEG_GPCOM_CMD)/sizeof(mmUVD_JPEG_GPCOM_CMD[0]), 0, 0 }, + { "mmUVD_JPEG_GPCOM_DATA0", REG_MMIO, 0x022d, 1, &mmUVD_JPEG_GPCOM_DATA0[0], sizeof(mmUVD_JPEG_GPCOM_DATA0)/sizeof(mmUVD_JPEG_GPCOM_DATA0[0]), 0, 0 }, + { "mmUVD_JPEG_GPCOM_DATA1", REG_MMIO, 0x022e, 1, &mmUVD_JPEG_GPCOM_DATA1[0], sizeof(mmUVD_JPEG_GPCOM_DATA1)/sizeof(mmUVD_JPEG_GPCOM_DATA1[0]), 0, 0 }, + { "mmUVD_JPEG_JRB_BASE_LO", REG_MMIO, 0x022f, 1, &mmUVD_JPEG_JRB_BASE_LO[0], sizeof(mmUVD_JPEG_JRB_BASE_LO)/sizeof(mmUVD_JPEG_JRB_BASE_LO[0]), 0, 0 }, + { "mmUVD_JPEG_JRB_BASE_HI", REG_MMIO, 0x0230, 1, &mmUVD_JPEG_JRB_BASE_HI[0], sizeof(mmUVD_JPEG_JRB_BASE_HI)/sizeof(mmUVD_JPEG_JRB_BASE_HI[0]), 0, 0 }, + { "mmUVD_JPEG_JRB_SIZE", REG_MMIO, 0x0232, 1, &mmUVD_JPEG_JRB_SIZE[0], sizeof(mmUVD_JPEG_JRB_SIZE)/sizeof(mmUVD_JPEG_JRB_SIZE[0]), 0, 0 }, + { "mmUVD_JPEG_JRB_RPTR", REG_MMIO, 0x0233, 1, &mmUVD_JPEG_JRB_RPTR[0], sizeof(mmUVD_JPEG_JRB_RPTR)/sizeof(mmUVD_JPEG_JRB_RPTR[0]), 0, 0 }, + { "mmUVD_JPEG_JRB_WPTR", REG_MMIO, 0x0234, 1, &mmUVD_JPEG_JRB_WPTR[0], sizeof(mmUVD_JPEG_JRB_WPTR)/sizeof(mmUVD_JPEG_JRB_WPTR[0]), 0, 0 }, + { "mmUVD_JPEG_UV_ADDR_CONFIG", REG_MMIO, 0x0238, 1, &mmUVD_JPEG_UV_ADDR_CONFIG[0], sizeof(mmUVD_JPEG_UV_ADDR_CONFIG)/sizeof(mmUVD_JPEG_UV_ADDR_CONFIG[0]), 0, 0 }, + { "mmUVD_SEMA_ADDR_LOW", REG_MMIO, 0x03c0, 1, &mmUVD_SEMA_ADDR_LOW[0], sizeof(mmUVD_SEMA_ADDR_LOW)/sizeof(mmUVD_SEMA_ADDR_LOW[0]), 0, 0 }, + { "mmUVD_SEMA_ADDR_HIGH", REG_MMIO, 0x03c1, 1, &mmUVD_SEMA_ADDR_HIGH[0], sizeof(mmUVD_SEMA_ADDR_HIGH)/sizeof(mmUVD_SEMA_ADDR_HIGH[0]), 0, 0 }, + { "mmUVD_SEMA_CMD", REG_MMIO, 0x03c2, 1, &mmUVD_SEMA_CMD[0], sizeof(mmUVD_SEMA_CMD)/sizeof(mmUVD_SEMA_CMD[0]), 0, 0 }, + { "mmUVD_GPCOM_VCPU_CMD", REG_MMIO, 0x03c3, 1, &mmUVD_GPCOM_VCPU_CMD[0], sizeof(mmUVD_GPCOM_VCPU_CMD)/sizeof(mmUVD_GPCOM_VCPU_CMD[0]), 0, 0 }, + { "mmUVD_GPCOM_VCPU_DATA0", REG_MMIO, 0x03c4, 1, &mmUVD_GPCOM_VCPU_DATA0[0], sizeof(mmUVD_GPCOM_VCPU_DATA0)/sizeof(mmUVD_GPCOM_VCPU_DATA0[0]), 0, 0 }, + { "mmUVD_GPCOM_VCPU_DATA1", REG_MMIO, 0x03c5, 1, &mmUVD_GPCOM_VCPU_DATA1[0], sizeof(mmUVD_GPCOM_VCPU_DATA1)/sizeof(mmUVD_GPCOM_VCPU_DATA1[0]), 0, 0 }, + { "mmUVD_UDEC_DBW_UV_ADDR_CONFIG", REG_MMIO, 0x03d2, 1, &mmUVD_UDEC_DBW_UV_ADDR_CONFIG[0], sizeof(mmUVD_UDEC_DBW_UV_ADDR_CONFIG)/sizeof(mmUVD_UDEC_DBW_UV_ADDR_CONFIG[0]), 0, 0 }, + { "mmUVD_UDEC_ADDR_CONFIG", REG_MMIO, 0x03d3, 1, &mmUVD_UDEC_ADDR_CONFIG[0], sizeof(mmUVD_UDEC_ADDR_CONFIG)/sizeof(mmUVD_UDEC_ADDR_CONFIG[0]), 0, 0 }, + { "mmUVD_UDEC_DB_ADDR_CONFIG", REG_MMIO, 0x03d4, 1, &mmUVD_UDEC_DB_ADDR_CONFIG[0], sizeof(mmUVD_UDEC_DB_ADDR_CONFIG)/sizeof(mmUVD_UDEC_DB_ADDR_CONFIG[0]), 0, 0 }, + { "mmUVD_UDEC_DBW_ADDR_CONFIG", REG_MMIO, 0x03d5, 1, &mmUVD_UDEC_DBW_ADDR_CONFIG[0], sizeof(mmUVD_UDEC_DBW_ADDR_CONFIG)/sizeof(mmUVD_UDEC_DBW_ADDR_CONFIG[0]), 0, 0 }, + { "mmUVD_SUVD_CGC_GATE", REG_MMIO, 0x03e4, 1, &mmUVD_SUVD_CGC_GATE[0], sizeof(mmUVD_SUVD_CGC_GATE)/sizeof(mmUVD_SUVD_CGC_GATE[0]), 0, 0 }, + { "mmUVD_SUVD_CGC_STATUS", REG_MMIO, 0x03e5, 1, &mmUVD_SUVD_CGC_STATUS[0], sizeof(mmUVD_SUVD_CGC_STATUS)/sizeof(mmUVD_SUVD_CGC_STATUS[0]), 0, 0 }, + { "mmUVD_SUVD_CGC_CTRL", REG_MMIO, 0x03e6, 1, &mmUVD_SUVD_CGC_CTRL[0], sizeof(mmUVD_SUVD_CGC_CTRL)/sizeof(mmUVD_SUVD_CGC_CTRL[0]), 0, 0 }, + { "mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW", REG_MMIO, 0x03ec, 1, &mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW[0], sizeof(mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW)/sizeof(mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW[0]), 0, 0 }, + { "mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH", REG_MMIO, 0x03ed, 1, &mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH[0], sizeof(mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH)/sizeof(mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH[0]), 0, 0 }, + { "mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW", REG_MMIO, 0x03f0, 1, &mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW[0], sizeof(mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW)/sizeof(mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW[0]), 0, 0 }, + { "mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH", REG_MMIO, 0x03f1, 1, &mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH[0], sizeof(mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH)/sizeof(mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH[0]), 0, 0 }, + { "mmUVD_NO_OP", REG_MMIO, 0x03ff, 1, &mmUVD_NO_OP[0], sizeof(mmUVD_NO_OP)/sizeof(mmUVD_NO_OP[0]), 0, 0 }, + { "mmUVD_JPEG_CNTL2", REG_MMIO, 0x0404, 1, NULL, 0, 0, 0 }, + { "mmUVD_VERSION", REG_MMIO, 0x0409, 1, &mmUVD_VERSION[0], sizeof(mmUVD_VERSION)/sizeof(mmUVD_VERSION[0]), 0, 0 }, + { "mmUVD_GP_SCRATCH8", REG_MMIO, 0x040a, 1, &mmUVD_GP_SCRATCH8[0], sizeof(mmUVD_GP_SCRATCH8)/sizeof(mmUVD_GP_SCRATCH8[0]), 0, 0 }, + { "mmUVD_GP_SCRATCH9", REG_MMIO, 0x040b, 1, &mmUVD_GP_SCRATCH9[0], sizeof(mmUVD_GP_SCRATCH9)/sizeof(mmUVD_GP_SCRATCH9[0]), 0, 0 }, + { "mmUVD_GP_SCRATCH10", REG_MMIO, 0x040c, 1, &mmUVD_GP_SCRATCH10[0], sizeof(mmUVD_GP_SCRATCH10)/sizeof(mmUVD_GP_SCRATCH10[0]), 0, 0 }, + { "mmUVD_GP_SCRATCH11", REG_MMIO, 0x040d, 1, &mmUVD_GP_SCRATCH11[0], sizeof(mmUVD_GP_SCRATCH11)/sizeof(mmUVD_GP_SCRATCH11[0]), 0, 0 }, + { "mmUVD_GP_SCRATCH12", REG_MMIO, 0x040e, 1, &mmUVD_GP_SCRATCH12[0], sizeof(mmUVD_GP_SCRATCH12)/sizeof(mmUVD_GP_SCRATCH12[0]), 0, 0 }, + { "mmUVD_GP_SCRATCH13", REG_MMIO, 0x040f, 1, &mmUVD_GP_SCRATCH13[0], sizeof(mmUVD_GP_SCRATCH13)/sizeof(mmUVD_GP_SCRATCH13[0]), 0, 0 }, + { "mmUVD_GP_SCRATCH14", REG_MMIO, 0x0410, 1, &mmUVD_GP_SCRATCH14[0], sizeof(mmUVD_GP_SCRATCH14)/sizeof(mmUVD_GP_SCRATCH14[0]), 0, 0 }, + { "mmUVD_GP_SCRATCH15", REG_MMIO, 0x0411, 1, &mmUVD_GP_SCRATCH15[0], sizeof(mmUVD_GP_SCRATCH15)/sizeof(mmUVD_GP_SCRATCH15[0]), 0, 0 }, + { "mmUVD_GP_SCRATCH16", REG_MMIO, 0x0412, 1, &mmUVD_GP_SCRATCH16[0], sizeof(mmUVD_GP_SCRATCH16)/sizeof(mmUVD_GP_SCRATCH16[0]), 0, 0 }, + { "mmUVD_GP_SCRATCH17", REG_MMIO, 0x0413, 1, &mmUVD_GP_SCRATCH17[0], sizeof(mmUVD_GP_SCRATCH17)/sizeof(mmUVD_GP_SCRATCH17[0]), 0, 0 }, + { "mmUVD_GP_SCRATCH18", REG_MMIO, 0x0414, 1, &mmUVD_GP_SCRATCH18[0], sizeof(mmUVD_GP_SCRATCH18)/sizeof(mmUVD_GP_SCRATCH18[0]), 0, 0 }, + { "mmUVD_GP_SCRATCH19", REG_MMIO, 0x0415, 1, &mmUVD_GP_SCRATCH19[0], sizeof(mmUVD_GP_SCRATCH19)/sizeof(mmUVD_GP_SCRATCH19[0]), 0, 0 }, + { "mmUVD_GP_SCRATCH20", REG_MMIO, 0x0416, 1, &mmUVD_GP_SCRATCH20[0], sizeof(mmUVD_GP_SCRATCH20)/sizeof(mmUVD_GP_SCRATCH20[0]), 0, 0 }, + { "mmUVD_GP_SCRATCH21", REG_MMIO, 0x0417, 1, &mmUVD_GP_SCRATCH21[0], sizeof(mmUVD_GP_SCRATCH21)/sizeof(mmUVD_GP_SCRATCH21[0]), 0, 0 }, + { "mmUVD_GP_SCRATCH22", REG_MMIO, 0x0418, 1, &mmUVD_GP_SCRATCH22[0], sizeof(mmUVD_GP_SCRATCH22)/sizeof(mmUVD_GP_SCRATCH22[0]), 0, 0 }, + { "mmUVD_GP_SCRATCH23", REG_MMIO, 0x0419, 1, &mmUVD_GP_SCRATCH23[0], sizeof(mmUVD_GP_SCRATCH23)/sizeof(mmUVD_GP_SCRATCH23[0]), 0, 0 }, + { "mmUVD_RB_BASE_LO2", REG_MMIO, 0x0421, 1, &mmUVD_RB_BASE_LO2[0], sizeof(mmUVD_RB_BASE_LO2)/sizeof(mmUVD_RB_BASE_LO2[0]), 0, 0 }, + { "mmUVD_RB_BASE_HI2", REG_MMIO, 0x0422, 1, &mmUVD_RB_BASE_HI2[0], sizeof(mmUVD_RB_BASE_HI2)/sizeof(mmUVD_RB_BASE_HI2[0]), 0, 0 }, + { "mmUVD_RB_SIZE2", REG_MMIO, 0x0423, 1, &mmUVD_RB_SIZE2[0], sizeof(mmUVD_RB_SIZE2)/sizeof(mmUVD_RB_SIZE2[0]), 0, 0 }, + { "mmUVD_RB_RPTR2", REG_MMIO, 0x0424, 1, &mmUVD_RB_RPTR2[0], sizeof(mmUVD_RB_RPTR2)/sizeof(mmUVD_RB_RPTR2[0]), 0, 0 }, + { "mmUVD_RB_WPTR2", REG_MMIO, 0x0425, 1, &mmUVD_RB_WPTR2[0], sizeof(mmUVD_RB_WPTR2)/sizeof(mmUVD_RB_WPTR2[0]), 0, 0 }, + { "mmUVD_RB_BASE_LO", REG_MMIO, 0x0426, 1, &mmUVD_RB_BASE_LO[0], sizeof(mmUVD_RB_BASE_LO)/sizeof(mmUVD_RB_BASE_LO[0]), 0, 0 }, + { "mmUVD_RB_BASE_HI", REG_MMIO, 0x0427, 1, &mmUVD_RB_BASE_HI[0], sizeof(mmUVD_RB_BASE_HI)/sizeof(mmUVD_RB_BASE_HI[0]), 0, 0 }, + { "mmUVD_RB_SIZE", REG_MMIO, 0x0428, 1, &mmUVD_RB_SIZE[0], sizeof(mmUVD_RB_SIZE)/sizeof(mmUVD_RB_SIZE[0]), 0, 0 }, + { "mmUVD_RB_RPTR", REG_MMIO, 0x0429, 1, &mmUVD_RB_RPTR[0], sizeof(mmUVD_RB_RPTR)/sizeof(mmUVD_RB_RPTR[0]), 0, 0 }, + { "mmUVD_RB_WPTR", REG_MMIO, 0x042a, 1, &mmUVD_RB_WPTR[0], sizeof(mmUVD_RB_WPTR)/sizeof(mmUVD_RB_WPTR[0]), 0, 0 }, + { "mmUVD_RB_WPTR4", REG_MMIO, 0x0456, 1, &mmUVD_RB_WPTR4[0], sizeof(mmUVD_RB_WPTR4)/sizeof(mmUVD_RB_WPTR4[0]), 0, 0 }, + { "mmUVD_JRBC_RB_RPTR", REG_MMIO, 0x0457, 1, &mmUVD_JRBC_RB_RPTR[0], sizeof(mmUVD_JRBC_RB_RPTR)/sizeof(mmUVD_JRBC_RB_RPTR[0]), 0, 0 }, + { "mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH", REG_MMIO, 0x045e, 1, &mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH[0], sizeof(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH)/sizeof(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH[0]), 0, 0 }, + { "mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW", REG_MMIO, 0x045f, 1, &mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW[0], sizeof(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW)/sizeof(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW[0]), 0, 0 }, + { "mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH", REG_MMIO, 0x0466, 1, &mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH[0], sizeof(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH)/sizeof(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH[0]), 0, 0 }, + { "mmUVD_LMI_RBC_IB_64BIT_BAR_LOW", REG_MMIO, 0x0467, 1, &mmUVD_LMI_RBC_IB_64BIT_BAR_LOW[0], sizeof(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW)/sizeof(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW[0]), 0, 0 }, + { "mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH", REG_MMIO, 0x0468, 1, &mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH[0], sizeof(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH)/sizeof(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH[0]), 0, 0 }, + { "mmUVD_LMI_RBC_RB_64BIT_BAR_LOW", REG_MMIO, 0x0469, 1, &mmUVD_LMI_RBC_RB_64BIT_BAR_LOW[0], sizeof(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW)/sizeof(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW[0]), 0, 0 }, + { "mmUVD_SEMA_CNTL", REG_MMIO, 0x0500, 1, &mmUVD_SEMA_CNTL[0], sizeof(mmUVD_SEMA_CNTL)/sizeof(mmUVD_SEMA_CNTL[0]), 0, 0 }, + { "mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW", REG_MMIO, 0x0503, 1, &mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW[0], sizeof(mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW)/sizeof(mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW[0]), 0, 0 }, + { "mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH", REG_MMIO, 0x0504, 1, &mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH[0], sizeof(mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH)/sizeof(mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH[0]), 0, 0 }, + { "mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW", REG_MMIO, 0x0505, 1, &mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW[0], sizeof(mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW)/sizeof(mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW[0]), 0, 0 }, + { "mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH", REG_MMIO, 0x0506, 1, &mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH[0], sizeof(mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH)/sizeof(mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH[0]), 0, 0 }, + { "mmUVD_LMI_JRBC_IB_VMID", REG_MMIO, 0x0507, 1, &mmUVD_LMI_JRBC_IB_VMID[0], sizeof(mmUVD_LMI_JRBC_IB_VMID)/sizeof(mmUVD_LMI_JRBC_IB_VMID[0]), 0, 0 }, + { "mmUVD_JRBC_RB_WPTR", REG_MMIO, 0x0509, 1, &mmUVD_JRBC_RB_WPTR[0], sizeof(mmUVD_JRBC_RB_WPTR)/sizeof(mmUVD_JRBC_RB_WPTR[0]), 0, 0 }, + { "mmUVD_JRBC_RB_CNTL", REG_MMIO, 0x050a, 1, &mmUVD_JRBC_RB_CNTL[0], sizeof(mmUVD_JRBC_RB_CNTL)/sizeof(mmUVD_JRBC_RB_CNTL[0]), 0, 0 }, + { "mmUVD_JRBC_IB_SIZE", REG_MMIO, 0x050b, 1, &mmUVD_JRBC_IB_SIZE[0], sizeof(mmUVD_JRBC_IB_SIZE)/sizeof(mmUVD_JRBC_IB_SIZE[0]), 0, 0 }, + { "mmUVD_JRBC_LMI_SWAP_CNTL", REG_MMIO, 0x050d, 1, &mmUVD_JRBC_LMI_SWAP_CNTL[0], sizeof(mmUVD_JRBC_LMI_SWAP_CNTL)/sizeof(mmUVD_JRBC_LMI_SWAP_CNTL[0]), 0, 0 }, + { "mmUVD_JRBC_SOFT_RESET", REG_MMIO, 0x0519, 1, &mmUVD_JRBC_SOFT_RESET[0], sizeof(mmUVD_JRBC_SOFT_RESET)/sizeof(mmUVD_JRBC_SOFT_RESET[0]), 0, 0 }, + { "mmUVD_JRBC_STATUS", REG_MMIO, 0x051a, 1, &mmUVD_JRBC_STATUS[0], sizeof(mmUVD_JRBC_STATUS)/sizeof(mmUVD_JRBC_STATUS[0]), 0, 0 }, + { "mmUVD_RB_RPTR3", REG_MMIO, 0x051b, 1, &mmUVD_RB_RPTR3[0], sizeof(mmUVD_RB_RPTR3)/sizeof(mmUVD_RB_RPTR3[0]), 0, 0 }, + { "mmUVD_RB_WPTR3", REG_MMIO, 0x051c, 1, &mmUVD_RB_WPTR3[0], sizeof(mmUVD_RB_WPTR3)/sizeof(mmUVD_RB_WPTR3[0]), 0, 0 }, + { "mmUVD_RB_BASE_LO3", REG_MMIO, 0x051d, 1, &mmUVD_RB_BASE_LO3[0], sizeof(mmUVD_RB_BASE_LO3)/sizeof(mmUVD_RB_BASE_LO3[0]), 0, 0 }, + { "mmUVD_RB_BASE_HI3", REG_MMIO, 0x051e, 1, &mmUVD_RB_BASE_HI3[0], sizeof(mmUVD_RB_BASE_HI3)/sizeof(mmUVD_RB_BASE_HI3[0]), 0, 0 }, + { "mmUVD_RB_SIZE3", REG_MMIO, 0x051f, 1, &mmUVD_RB_SIZE3[0], sizeof(mmUVD_RB_SIZE3)/sizeof(mmUVD_RB_SIZE3[0]), 0, 0 }, + { "mmJPEG_CGC_GATE", REG_MMIO, 0x0526, 1, &mmJPEG_CGC_GATE[0], sizeof(mmJPEG_CGC_GATE)/sizeof(mmJPEG_CGC_GATE[0]), 0, 0 }, + { "mmUVD_CTX_INDEX", REG_MMIO, 0x0528, 1, &mmUVD_CTX_INDEX[0], sizeof(mmUVD_CTX_INDEX)/sizeof(mmUVD_CTX_INDEX[0]), 0, 0 }, + { "mmUVD_CTX_DATA", REG_MMIO, 0x0529, 1, &mmUVD_CTX_DATA[0], sizeof(mmUVD_CTX_DATA)/sizeof(mmUVD_CTX_DATA[0]), 0, 0 }, + { "mmUVD_CGC_GATE", REG_MMIO, 0x052a, 1, &mmUVD_CGC_GATE[0], sizeof(mmUVD_CGC_GATE)/sizeof(mmUVD_CGC_GATE[0]), 0, 0 }, + { "mmUVD_CGC_STATUS", REG_MMIO, 0x052b, 1, &mmUVD_CGC_STATUS[0], sizeof(mmUVD_CGC_STATUS)/sizeof(mmUVD_CGC_STATUS[0]), 0, 0 }, + { "mmUVD_CGC_CTRL", REG_MMIO, 0x052c, 1, &mmUVD_CGC_CTRL[0], sizeof(mmUVD_CGC_CTRL)/sizeof(mmUVD_CGC_CTRL[0]), 0, 0 }, + { "mmUVD_GP_SCRATCH0", REG_MMIO, 0x0534, 1, &mmUVD_GP_SCRATCH0[0], sizeof(mmUVD_GP_SCRATCH0)/sizeof(mmUVD_GP_SCRATCH0[0]), 0, 0 }, + { "mmUVD_GP_SCRATCH1", REG_MMIO, 0x0535, 1, &mmUVD_GP_SCRATCH1[0], sizeof(mmUVD_GP_SCRATCH1)/sizeof(mmUVD_GP_SCRATCH1[0]), 0, 0 }, + { "mmUVD_GP_SCRATCH2", REG_MMIO, 0x0536, 1, &mmUVD_GP_SCRATCH2[0], sizeof(mmUVD_GP_SCRATCH2)/sizeof(mmUVD_GP_SCRATCH2[0]), 0, 0 }, + { "mmUVD_GP_SCRATCH3", REG_MMIO, 0x0537, 1, &mmUVD_GP_SCRATCH3[0], sizeof(mmUVD_GP_SCRATCH3)/sizeof(mmUVD_GP_SCRATCH3[0]), 0, 0 }, + { "mmUVD_GP_SCRATCH4", REG_MMIO, 0x0538, 1, &mmUVD_GP_SCRATCH4[0], sizeof(mmUVD_GP_SCRATCH4)/sizeof(mmUVD_GP_SCRATCH4[0]), 0, 0 }, + { "mmUVD_GP_SCRATCH5", REG_MMIO, 0x0539, 1, &mmUVD_GP_SCRATCH5[0], sizeof(mmUVD_GP_SCRATCH5)/sizeof(mmUVD_GP_SCRATCH5[0]), 0, 0 }, + { "mmUVD_GP_SCRATCH6", REG_MMIO, 0x053a, 1, &mmUVD_GP_SCRATCH6[0], sizeof(mmUVD_GP_SCRATCH6)/sizeof(mmUVD_GP_SCRATCH6[0]), 0, 0 }, + { "mmUVD_GP_SCRATCH7", REG_MMIO, 0x053b, 1, &mmUVD_GP_SCRATCH7[0], sizeof(mmUVD_GP_SCRATCH7)/sizeof(mmUVD_GP_SCRATCH7[0]), 0, 0 }, + { "mmUVD_LMI_VCPU_CACHE_VMID", REG_MMIO, 0x053c, 1, &mmUVD_LMI_VCPU_CACHE_VMID[0], sizeof(mmUVD_LMI_VCPU_CACHE_VMID)/sizeof(mmUVD_LMI_VCPU_CACHE_VMID[0]), 0, 0 }, + { "mmUVD_LMI_CTRL2", REG_MMIO, 0x053d, 1, &mmUVD_LMI_CTRL2[0], sizeof(mmUVD_LMI_CTRL2)/sizeof(mmUVD_LMI_CTRL2[0]), 0, 0 }, + { "mmUVD_MASTINT_EN", REG_MMIO, 0x0540, 1, &mmUVD_MASTINT_EN[0], sizeof(mmUVD_MASTINT_EN)/sizeof(mmUVD_MASTINT_EN[0]), 0, 0 }, + { "mmJPEG_CGC_CTRL", REG_MMIO, 0x0565, 1, &mmJPEG_CGC_CTRL[0], sizeof(mmJPEG_CGC_CTRL)/sizeof(mmJPEG_CGC_CTRL[0]), 0, 0 }, + { "mmUVD_LMI_CTRL", REG_MMIO, 0x0566, 1, &mmUVD_LMI_CTRL[0], sizeof(mmUVD_LMI_CTRL)/sizeof(mmUVD_LMI_CTRL[0]), 0, 0 }, + { "mmUVD_LMI_STATUS", REG_MMIO, 0x0567, 1, NULL, 0, 0, 0 }, + { "mmUVD_LMI_VM_CTRL", REG_MMIO, 0x0568, 1, NULL, 0, 0, 0 }, + { "mmUVD_LMI_SWAP_CNTL", REG_MMIO, 0x056d, 1, &mmUVD_LMI_SWAP_CNTL[0], sizeof(mmUVD_LMI_SWAP_CNTL)/sizeof(mmUVD_LMI_SWAP_CNTL[0]), 0, 0 }, + { "mmUVD_MPC_SET_MUXA0", REG_MMIO, 0x0579, 1, &mmUVD_MPC_SET_MUXA0[0], sizeof(mmUVD_MPC_SET_MUXA0)/sizeof(mmUVD_MPC_SET_MUXA0[0]), 0, 0 }, + { "mmUVD_MPC_SET_MUXA1", REG_MMIO, 0x057a, 1, &mmUVD_MPC_SET_MUXA1[0], sizeof(mmUVD_MPC_SET_MUXA1)/sizeof(mmUVD_MPC_SET_MUXA1[0]), 0, 0 }, + { "mmUVD_MPC_SET_MUXB0", REG_MMIO, 0x057b, 1, &mmUVD_MPC_SET_MUXB0[0], sizeof(mmUVD_MPC_SET_MUXB0)/sizeof(mmUVD_MPC_SET_MUXB0[0]), 0, 0 }, + { "mmUVD_MPC_SET_MUXB1", REG_MMIO, 0x057c, 1, &mmUVD_MPC_SET_MUXB1[0], sizeof(mmUVD_MPC_SET_MUXB1)/sizeof(mmUVD_MPC_SET_MUXB1[0]), 0, 0 }, + { "mmUVD_MPC_SET_MUX", REG_MMIO, 0x057d, 1, &mmUVD_MPC_SET_MUX[0], sizeof(mmUVD_MPC_SET_MUX)/sizeof(mmUVD_MPC_SET_MUX[0]), 0, 0 }, + { "mmUVD_MPC_SET_ALU", REG_MMIO, 0x057e, 1, &mmUVD_MPC_SET_ALU[0], sizeof(mmUVD_MPC_SET_ALU)/sizeof(mmUVD_MPC_SET_ALU[0]), 0, 0 }, + { "mmUVD_GPCOM_SYS_CMD", REG_MMIO, 0x057f, 1, &mmUVD_GPCOM_SYS_CMD[0], sizeof(mmUVD_GPCOM_SYS_CMD)/sizeof(mmUVD_GPCOM_SYS_CMD[0]), 0, 0 }, + { "mmUVD_GPCOM_SYS_DATA0", REG_MMIO, 0x0580, 1, &mmUVD_GPCOM_SYS_DATA0[0], sizeof(mmUVD_GPCOM_SYS_DATA0)/sizeof(mmUVD_GPCOM_SYS_DATA0[0]), 0, 0 }, + { "mmUVD_GPCOM_SYS_DATA1", REG_MMIO, 0x0581, 1, &mmUVD_GPCOM_SYS_DATA1[0], sizeof(mmUVD_GPCOM_SYS_DATA1)/sizeof(mmUVD_GPCOM_SYS_DATA1[0]), 0, 0 }, + { "mmUVD_VCPU_CACHE_OFFSET0", REG_MMIO, 0x0582, 1, &mmUVD_VCPU_CACHE_OFFSET0[0], sizeof(mmUVD_VCPU_CACHE_OFFSET0)/sizeof(mmUVD_VCPU_CACHE_OFFSET0[0]), 0, 0 }, + { "mmUVD_VCPU_CACHE_SIZE0", REG_MMIO, 0x0583, 1, &mmUVD_VCPU_CACHE_SIZE0[0], sizeof(mmUVD_VCPU_CACHE_SIZE0)/sizeof(mmUVD_VCPU_CACHE_SIZE0[0]), 0, 0 }, + { "mmUVD_VCPU_CACHE_OFFSET1", REG_MMIO, 0x0584, 1, &mmUVD_VCPU_CACHE_OFFSET1[0], sizeof(mmUVD_VCPU_CACHE_OFFSET1)/sizeof(mmUVD_VCPU_CACHE_OFFSET1[0]), 0, 0 }, + { "mmUVD_VCPU_CACHE_SIZE1", REG_MMIO, 0x0585, 1, &mmUVD_VCPU_CACHE_SIZE1[0], sizeof(mmUVD_VCPU_CACHE_SIZE1)/sizeof(mmUVD_VCPU_CACHE_SIZE1[0]), 0, 0 }, + { "mmUVD_VCPU_CACHE_OFFSET2", REG_MMIO, 0x0586, 1, &mmUVD_VCPU_CACHE_OFFSET2[0], sizeof(mmUVD_VCPU_CACHE_OFFSET2)/sizeof(mmUVD_VCPU_CACHE_OFFSET2[0]), 0, 0 }, + { "mmUVD_VCPU_CACHE_SIZE2", REG_MMIO, 0x0587, 1, &mmUVD_VCPU_CACHE_SIZE2[0], sizeof(mmUVD_VCPU_CACHE_SIZE2)/sizeof(mmUVD_VCPU_CACHE_SIZE2[0]), 0, 0 }, + { "mmUVD_VCPU_CNTL", REG_MMIO, 0x0598, 1, &mmUVD_VCPU_CNTL[0], sizeof(mmUVD_VCPU_CNTL)/sizeof(mmUVD_VCPU_CNTL[0]), 0, 0 }, + { "mmUVD_SOFT_RESET", REG_MMIO, 0x05a0, 1, &mmUVD_SOFT_RESET[0], sizeof(mmUVD_SOFT_RESET)/sizeof(mmUVD_SOFT_RESET[0]), 0, 0 }, + { "mmUVD_LMI_RBC_IB_VMID", REG_MMIO, 0x05a1, 1, &mmUVD_LMI_RBC_IB_VMID[0], sizeof(mmUVD_LMI_RBC_IB_VMID)/sizeof(mmUVD_LMI_RBC_IB_VMID[0]), 0, 0 }, + { "mmUVD_RBC_IB_SIZE", REG_MMIO, 0x05a2, 1, &mmUVD_RBC_IB_SIZE[0], sizeof(mmUVD_RBC_IB_SIZE)/sizeof(mmUVD_RBC_IB_SIZE[0]), 0, 0 }, + { "mmUVD_RBC_RB_RPTR", REG_MMIO, 0x05a4, 1, &mmUVD_RBC_RB_RPTR[0], sizeof(mmUVD_RBC_RB_RPTR)/sizeof(mmUVD_RBC_RB_RPTR[0]), 0, 0 }, + { "mmUVD_RBC_RB_WPTR", REG_MMIO, 0x05a5, 1, &mmUVD_RBC_RB_WPTR[0], sizeof(mmUVD_RBC_RB_WPTR)/sizeof(mmUVD_RBC_RB_WPTR[0]), 0, 0 }, + { "mmUVD_RBC_RB_WPTR_CNTL", REG_MMIO, 0x05a6, 1, &mmUVD_RBC_RB_WPTR_CNTL[0], sizeof(mmUVD_RBC_RB_WPTR_CNTL)/sizeof(mmUVD_RBC_RB_WPTR_CNTL[0]), 0, 0 }, + { "mmUVD_RBC_RB_CNTL", REG_MMIO, 0x05a9, 1, &mmUVD_RBC_RB_CNTL[0], sizeof(mmUVD_RBC_RB_CNTL)/sizeof(mmUVD_RBC_RB_CNTL[0]), 0, 0 }, + { "mmUVD_RBC_RB_RPTR_ADDR", REG_MMIO, 0x05aa, 1, &mmUVD_RBC_RB_RPTR_ADDR[0], sizeof(mmUVD_RBC_RB_RPTR_ADDR)/sizeof(mmUVD_RBC_RB_RPTR_ADDR[0]), 0, 0 }, + { "mmUVD_STATUS", REG_MMIO, 0x05af, 1, &mmUVD_STATUS[0], sizeof(mmUVD_STATUS)/sizeof(mmUVD_STATUS[0]), 0, 0 }, + { "mmUVD_SEMA_TIMEOUT_STATUS", REG_MMIO, 0x05b0, 1, &mmUVD_SEMA_TIMEOUT_STATUS[0], sizeof(mmUVD_SEMA_TIMEOUT_STATUS)/sizeof(mmUVD_SEMA_TIMEOUT_STATUS[0]), 0, 0 }, + { "mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL", REG_MMIO, 0x05b1, 1, &mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL[0], sizeof(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL)/sizeof(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL[0]), 0, 0 }, + { "mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL", REG_MMIO, 0x05b2, 1, &mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL[0], sizeof(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL)/sizeof(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL[0]), 0, 0 }, + { "mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL", REG_MMIO, 0x05b3, 1, &mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL[0], sizeof(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL)/sizeof(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL[0]), 0, 0 }, + { "mmUVD_CONTEXT_ID", REG_MMIO, 0x05bd, 1, &mmUVD_CONTEXT_ID[0], sizeof(mmUVD_CONTEXT_ID)/sizeof(mmUVD_CONTEXT_ID[0]), 0, 0 }, + { "mmUVD_CONTEXT_ID2", REG_MMIO, 0x05bf, 1, &mmUVD_CONTEXT_ID2[0], sizeof(mmUVD_CONTEXT_ID2)/sizeof(mmUVD_CONTEXT_ID2[0]), 0, 0 }, + { "mmUVD_RBC_WPTR_POLL_CNTL", REG_MMIO, 0x05d8, 1, &mmUVD_RBC_WPTR_POLL_CNTL[0], sizeof(mmUVD_RBC_WPTR_POLL_CNTL)/sizeof(mmUVD_RBC_WPTR_POLL_CNTL[0]), 0, 0 }, + { "mmUVD_RBC_WPTR_POLL_ADDR", REG_MMIO, 0x05d9, 1, &mmUVD_RBC_WPTR_POLL_ADDR[0], sizeof(mmUVD_RBC_WPTR_POLL_ADDR)/sizeof(mmUVD_RBC_WPTR_POLL_ADDR[0]), 0, 0 }, + { "mmUVD_RB_BASE_LO4", REG_MMIO, 0x05df, 1, &mmUVD_RB_BASE_LO4[0], sizeof(mmUVD_RB_BASE_LO4)/sizeof(mmUVD_RB_BASE_LO4[0]), 0, 0 }, + { "mmUVD_RB_BASE_HI4", REG_MMIO, 0x05e0, 1, &mmUVD_RB_BASE_HI4[0], sizeof(mmUVD_RB_BASE_HI4)/sizeof(mmUVD_RB_BASE_HI4[0]), 0, 0 }, + { "mmUVD_RB_SIZE4", REG_MMIO, 0x05e1, 1, &mmUVD_RB_SIZE4[0], sizeof(mmUVD_RB_SIZE4)/sizeof(mmUVD_RB_SIZE4[0]), 0, 0 }, + { "mmUVD_RB_RPTR4", REG_MMIO, 0x05e2, 1, &mmUVD_RB_RPTR4[0], sizeof(mmUVD_RB_RPTR4)/sizeof(mmUVD_RB_RPTR4[0]), 0, 0 }, diff --git a/src/lib/read_vram.c b/src/lib/read_vram.c index 0061aaf..ef92af7 100644 --- a/src/lib/read_vram.c +++ b/src/lib/read_vram.c @@ -424,6 +424,7 @@ int umr_read_vram(struct umr_asic *asic, uint32_t vmid, uint64_t address, uint32 switch (asic->family) { case FAMILY_VI: return umr_read_vram_vi(asic, vmid, address, size, dst); + case FAMILY_RV: case FAMILY_AI: return umr_read_vram_ai(asic, vmid, address, size, dst); default: diff --git a/src/lib/wave_status.c b/src/lib/wave_status.c index 22f92c2..9cdc259 100644 --- a/src/lib/wave_status.c +++ b/src/lib/wave_status.c @@ -201,7 +201,7 @@ static int umr_get_wave_status_vi(struct umr_asic *asic, unsigned se, unsigned s return 0; } -static int umr_get_wave_status_next(struct umr_asic *asic, unsigned se, unsigned sh, unsigned cu, unsigned simd, unsigned wave, struct umr_wave_status *ws) +static int umr_get_wave_status_ai(struct umr_asic *asic, unsigned se, unsigned sh, unsigned cu, unsigned simd, unsigned wave, struct umr_wave_status *ws) { uint32_t x, value, buf[32]; @@ -301,8 +301,8 @@ static int umr_get_wave_status_next(struct umr_asic *asic, unsigned se, unsigned int umr_get_wave_status(struct umr_asic *asic, unsigned se, unsigned sh, unsigned cu, unsigned simd, unsigned wave, struct umr_wave_status *ws) { - if (asic->family == FAMILY_AI) - return umr_get_wave_status_next(asic, se, sh, cu, simd, wave, ws); + if (asic->family == FAMILY_AI || asic->family == FAMILY_RV) + return umr_get_wave_status_ai(asic, se, sh, cu, simd, wave, ws); else if (asic->family <= FAMILY_VI) return umr_get_wave_status_vi(asic, se, sh, cu, simd, wave, ws); return -1; @@ -54,6 +54,7 @@ enum chipfamily { FAMILY_CIK, FAMILY_VI, FAMILY_AI, + FAMILY_RV, }; enum regclass { @@ -357,20 +358,25 @@ struct umr_ring_decoder { /* ip block constructors for soc15 */ int umr_transfer_soc15_to_reg(struct umr_options *options, struct umr_ip_offsets_soc15 *ip, char *ipname, const struct umr_reg_soc15 *regs, struct umr_ip_block *dst); struct umr_ip_block *umr_create_gfx90(struct umr_ip_offsets_soc15 *soc15_offsets, struct umr_options *options); +struct umr_ip_block *umr_create_gfx91(struct umr_ip_offsets_soc15 *soc15_offsets, struct umr_options *options); struct umr_ip_block *umr_create_uvd70(struct umr_ip_offsets_soc15 *soc15_offsets, struct umr_options *options); struct umr_ip_block *umr_create_vce40(struct umr_ip_offsets_soc15 *soc15_offsets, struct umr_options *options); struct umr_ip_block *umr_create_dce120(struct umr_ip_offsets_soc15 *soc15_offsets, struct umr_options *options); +struct umr_ip_block *umr_create_dcn10(struct umr_ip_offsets_soc15 *soc15_offsets, struct umr_options *options); struct umr_ip_block *umr_create_hdp40(struct umr_ip_offsets_soc15 *soc15_offsets, struct umr_options *options); -struct umr_ip_block *umr_create_nbif61(struct umr_ip_offsets_soc15 *soc15_offsets, struct umr_options *options); struct umr_ip_block *umr_create_nbio61(struct umr_ip_offsets_soc15 *soc15_offsets, struct umr_options *options); +struct umr_ip_block *umr_create_nbio70(struct umr_ip_offsets_soc15 *soc15_offsets, struct umr_options *options); struct umr_ip_block *umr_create_oss40(struct umr_ip_offsets_soc15 *soc15_offsets, struct umr_options *options); struct umr_ip_block *umr_create_sdma040(struct umr_ip_offsets_soc15 *soc15_offsets, struct umr_options *options); struct umr_ip_block *umr_create_sdma140(struct umr_ip_offsets_soc15 *soc15_offsets, struct umr_options *options); +struct umr_ip_block *umr_create_sdma041(struct umr_ip_offsets_soc15 *soc15_offsets, struct umr_options *options); struct umr_ip_block *umr_create_mmhub10(struct umr_ip_offsets_soc15 *soc15_offsets, struct umr_options *options); +struct umr_ip_block *umr_create_mmhub91(struct umr_ip_offsets_soc15 *soc15_offsets, struct umr_options *options); struct umr_ip_block *umr_create_mp90(struct umr_ip_offsets_soc15 *soc15_offsets, struct umr_options *options); struct umr_ip_block *umr_create_mp100(struct umr_ip_offsets_soc15 *soc15_offsets, struct umr_options *options); struct umr_ip_block *umr_create_thm90(struct umr_ip_offsets_soc15 *soc15_offsets, struct umr_options *options); struct umr_ip_block *umr_create_umc70(struct umr_ip_offsets_soc15 *soc15_offsets, struct umr_options *options); +struct umr_ip_block *umr_create_vcn10(struct umr_ip_offsets_soc15 *soc15_offsets, struct umr_options *options); /* ip block constructors */ struct umr_ip_block *umr_create_uvd40(struct umr_options *options); @@ -429,6 +435,7 @@ struct umr_asic *umr_create_pitcairn(struct umr_options *options); struct umr_asic *umr_create_polaris10(struct umr_options *options); struct umr_asic *umr_create_polaris11(struct umr_options *options); struct umr_asic *umr_create_polaris12(struct umr_options *options); +struct umr_asic *umr_create_raven1(struct umr_options *options); struct umr_asic *umr_create_stoney(struct umr_options *options); struct umr_asic *umr_create_tahiti(struct umr_options *options); struct umr_asic *umr_create_tonga(struct umr_options *options); |