diff options
Diffstat (limited to 'lib/Target/AArch64/AArch64InstrNEON.td')
| -rw-r--r-- | lib/Target/AArch64/AArch64InstrNEON.td | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/lib/Target/AArch64/AArch64InstrNEON.td b/lib/Target/AArch64/AArch64InstrNEON.td index e4c946b45a3..b6271717f6e 100644 --- a/lib/Target/AArch64/AArch64InstrNEON.td +++ b/lib/Target/AArch64/AArch64InstrNEON.td @@ -3092,6 +3092,30 @@ multiclass Neon_Scalar3Same_SD_size_patterns<SDPatternOperator opnode, (INSTD FPR64:$Rn, FPR64:$Rm)>; } +// Scalar Two Registers Miscellaneous + +multiclass NeonI_Scalar2SameMisc_SD_size<bit u, bit size_high, bits<5> opcode, + string asmop> { + def ss : NeonI_Scalar2SameMisc<u, {size_high, 0b0}, opcode, + (outs FPR32:$Rd), (ins FPR32:$Rn), + !strconcat(asmop, " $Rd, $Rn"), + [], NoItinerary>; + def dd : NeonI_Scalar2SameMisc<u, {size_high, 0b1}, opcode, + (outs FPR64:$Rd), (ins FPR64:$Rn), + !strconcat(asmop, " $Rd, $Rn"), + [], NoItinerary>; +} + +multiclass Neon_Scalar2SameMisc_SD_size_patterns<SDPatternOperator Sopnode, + SDPatternOperator Dopnode, + Instruction INSTS, + Instruction INSTD> { + def : Pat<(v1f32 (Sopnode (v1i32 FPR32:$Rn))), + (INSTS FPR32:$Rn)>; + def : Pat<(v1f64 (Dopnode (v1i64 FPR64:$Rn))), + (INSTD FPR64:$Rn)>; +} + // Scalar Integer Add let isCommutable = 1 in { def ADDddd : NeonI_Scalar3Same_D_size<0b0, 0b10000, "add">; @@ -3232,6 +3256,18 @@ defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqrshlu, UQRSHLbbb, defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqrshifts, SQRSHLddd>; defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqrshiftu, UQRSHLddd>; +// Scalar Signed Integer Convert To Floating-point +defm SCVTF : NeonI_Scalar2SameMisc_SD_size<0b0, 0b0, 0b11101, "scvtf">; +defm : Neon_Scalar2SameMisc_SD_size_patterns<int_aarch64_neon_vcvtf32_s32, + int_aarch64_neon_vcvtf64_s64, + SCVTFss, SCVTFdd>; + +// Scalar Unsigned Integer Convert To Floating-point +defm UCVTF : NeonI_Scalar2SameMisc_SD_size<0b1, 0b0, 0b11101, "ucvtf">; +defm : Neon_Scalar2SameMisc_SD_size_patterns<int_aarch64_neon_vcvtf32_u32, + int_aarch64_neon_vcvtf64_u64, + UCVTFss, UCVTFdd>; + // Scalar Reduce Pairwise multiclass NeonI_ScalarPair_D_sizes<bit u, bit size, bits<5> opcode, |