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| author | Colin LeMahieu <colinl@codeaurora.org> | 2014-12-30 22:34:08 +0000 |
|---|---|---|
| committer | Colin LeMahieu <colinl@codeaurora.org> | 2014-12-30 22:34:08 +0000 |
| commit | a7940ef0e4566ea1f9148c30eb90aeb4026c0ce5 (patch) | |
| tree | 186d5073d5595f6b23dc46999819202b4e4c53bf | |
| parent | df2531486d763c533693934aaa336733c295b187 (diff) | |
[Hexagon] Adding postincrement register newvalue stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225010 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/Hexagon/HexagonInstrInfoV4.td | 30 | ||||
| -rw-r--r-- | test/MC/Disassembler/Hexagon/nv_st.txt | 9 |
2 files changed, 39 insertions, 0 deletions
diff --git a/lib/Target/Hexagon/HexagonInstrInfoV4.td b/lib/Target/Hexagon/HexagonInstrInfoV4.td index 5509e18e975..e0606878b46 100644 --- a/lib/Target/Hexagon/HexagonInstrInfoV4.td +++ b/lib/Target/Hexagon/HexagonInstrInfoV4.td @@ -1312,6 +1312,36 @@ defm storerhnew: ST_PostInc_nv <"memh", "STrih", s4_1Imm, 0b01>; let accessSize = WordAccess, isCodeGenOnly = 0 in defm storerinew: ST_PostInc_nv <"memw", "STriw", s4_2Imm, 0b10>; +//===----------------------------------------------------------------------===// +// Template class for post increment .new stores with register offset +//===----------------------------------------------------------------------===// +let isNewValue = 1, mayStore = 1, isNVStore = 1, opNewValue = 3 in +class T_StorePI_RegNV <string mnemonic, bits<2> MajOp, MemAccessSize AccessSz> + : NVInstPI_V4 <(outs IntRegs:$_dst_), + (ins IntRegs:$src1, ModRegs:$src2, IntRegs:$src3), + #mnemonic#"($src1++$src2) = $src3.new", + [], "$src1 = $_dst_"> { + bits<5> src1; + bits<1> src2; + bits<3> src3; + let accessSize = AccessSz; + + let IClass = 0b1010; + + let Inst{27-21} = 0b1101101; + let Inst{20-16} = src1; + let Inst{13} = src2; + let Inst{12-11} = MajOp; + let Inst{10-8} = src3; + let Inst{7} = 0b0; + } + +let isCodeGenOnly = 0 in { +def S2_storerbnew_pr : T_StorePI_RegNV<"memb", 0b00, ByteAccess>; +def S2_storerhnew_pr : T_StorePI_RegNV<"memh", 0b01, HalfWordAccess>; +def S2_storerinew_pr : T_StorePI_RegNV<"memw", 0b10, WordAccess>; +} + // memb(Rx++#s4:0:circ(Mu))=Nt.new // memb(Rx++I:circ(Mu))=Nt.new // memb(Rx++Mu)=Nt.new diff --git a/test/MC/Disassembler/Hexagon/nv_st.txt b/test/MC/Disassembler/Hexagon/nv_st.txt index f9e97b559ef..83057098734 100644 --- a/test/MC/Disassembler/Hexagon/nv_st.txt +++ b/test/MC/Disassembler/Hexagon/nv_st.txt @@ -9,6 +9,9 @@ 0x1f 0x40 0x7f 0x70 0x28 0xc2 0xb1 0xab # CHECK: r31 = r31 # CHECK-NEXT: memb(r17++#5) = r2.new +0x1f 0x40 0x7f 0x70 0x00 0xe2 0xb1 0xad +# CHECK: r31 = r31 +# CHECK-NEXT: memb(r17++m1) = r2.new 0x1f 0x40 0x7f 0x70 0xe2 0xf5 0xb1 0x34 # CHECK: r31 = r31 # CHECK-NEXT: if (p3) memb(r17+r21<<#3) = r2.new @@ -61,6 +64,9 @@ 0x1f 0x40 0x7f 0x70 0x28 0xca 0xb1 0xab # CHECK: r31 = r31 # CHECK-NEXT: memh(r17++#10) = r2.new +0x1f 0x40 0x7f 0x70 0x00 0xea 0xb1 0xad +# CHECK: r31 = r31 +# CHECK-NEXT: memh(r17++m1) = r2.new 0x1f 0x40 0x7f 0x70 0xea 0xf5 0xb1 0x34 # CHECK: r31 = r31 # CHECK-NEXT: if (p3) memh(r17+r21<<#3) = r2.new @@ -113,6 +119,9 @@ 0x1f 0x40 0x7f 0x70 0x28 0xd2 0xb1 0xab # CHECK: r31 = r31 # CHECK-NEXT: memw(r17++#20) = r2.new +0x1f 0x40 0x7f 0x70 0x00 0xf2 0xb1 0xad +# CHECK: r31 = r31 +# CHECK-NEXT: memw(r17++m1) = r2.new 0x1f 0x40 0x7f 0x70 0xf2 0xf5 0xb1 0x34 # CHECK: r31 = r31 # CHECK-NEXT: if (p3) memw(r17+r21<<#3) = r2.new |