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| author | Tom Stellard <thomas.stellard@amd.com> | 2013-12-18 18:09:03 -0500 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2014-01-28 14:24:13 -0500 |
| commit | 6848d5b989da9f97c60f04d8a3ccb3183d46bb63 (patch) | |
| tree | fe261f35ce9330f0ea130749d3ca377ac317b26f | |
| parent | 8272791426921a077e0bd22a6f1801345452c88a (diff) | |
XXX: 32-bit priv fixesmaster-testing-v2
| -rw-r--r-- | lib/Target/R600/SIISelLowering.cpp | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/lib/Target/R600/SIISelLowering.cpp b/lib/Target/R600/SIISelLowering.cpp index c1576e9f519..0cfe4236cdc 100644 --- a/lib/Target/R600/SIISelLowering.cpp +++ b/lib/Target/R600/SIISelLowering.cpp @@ -754,10 +754,7 @@ SDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const { Ret = SplitVectorLoad(Op, DAG); } else if (Load->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS) { - SDValue TruncPtr = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, - Load->getBasePtr(), - DAG.getConstant(0, MVT::i32)); - SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, TruncPtr, + SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Load->getBasePtr(), DAG.getConstant(2, MVT::i32)); Ret = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, Op.getValueType(), Load->getChain(), Ptr, |