diff options
| author | Thierry Reding <treding@nvidia.com> | 2014-11-27 13:49:55 +0100 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2014-12-19 10:12:44 +0100 |
| commit | 2588b7aed097224f7d81e13f787316e9d6591be7 (patch) | |
| tree | 75bdf1f44dffbd1b708c42d25ebac5976cd1416c | |
| parent | 518cf0e0a178d4acd797eed780f145bf6c1b76d3 (diff) | |
PCI: tegra: Mark Tegra20 as being coherentstaging/pci
The PCIe controller is connected to the SCU on Tegra20, so technically
transactions should be coherent. In practice this doesn't seem to work
unfortunately, so we mark the SoC generation as being coherent with a
comment that it doesn't actually work.
If nothing else this prevents accesses to non-existent registers on
later Tegra generations.
Signed-off-by: Thierry Reding <treding@nvidia.com>
| -rw-r--r-- | drivers/pci/host/pci-tegra.c | 22 |
1 files changed, 17 insertions, 5 deletions
diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index 19a0c57d219..860a07adcba 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -252,6 +252,7 @@ struct tegra_pcie_soc_data { unsigned int msi_base_shift; u32 pads_pll_ctl; u32 tx_ref_sel; + bool coherent; bool has_pex_clkreq_en; bool has_pex_bias_ctrl; bool has_intr_prsnt_sense; @@ -784,6 +785,7 @@ static irqreturn_t tegra_pcie_isr(int irq, void *arg) */ static void tegra_pcie_setup_translations(struct tegra_pcie *pcie) { + const struct tegra_pcie_soc_data *soc = pcie->soc_data; u32 fpci_bar, size, axi_address; /* Bar 0: type 1 extended configuration space */ @@ -827,11 +829,18 @@ static void tegra_pcie_setup_translations(struct tegra_pcie *pcie) afi_writel(pcie, 0, AFI_AXI_BAR5_SZ); afi_writel(pcie, 0, AFI_FPCI_BAR5); - /* map all upstream transactions as uncached */ - afi_writel(pcie, 0, AFI_CACHE_BAR0_ST); - afi_writel(pcie, 0, AFI_CACHE_BAR0_SZ); - afi_writel(pcie, 0, AFI_CACHE_BAR1_ST); - afi_writel(pcie, 0, AFI_CACHE_BAR1_SZ); + if (soc->coherent) { + /* + * The PCIe controller is connected to the SCU on Tegra20, so + * accesses to system memory should be coherent. In practice + * this doesn't work, so map all upstream transactions as + * uncached. + */ + afi_writel(pcie, 0, AFI_CACHE_BAR0_ST); + afi_writel(pcie, 0, AFI_CACHE_BAR0_SZ); + afi_writel(pcie, 0, AFI_CACHE_BAR1_ST); + afi_writel(pcie, 0, AFI_CACHE_BAR1_SZ); + } /* MSI translations are setup only when needed */ afi_writel(pcie, 0, AFI_MSI_FPCI_BAR_ST); @@ -1929,6 +1938,7 @@ static const struct tegra_pcie_soc_data tegra20_pcie_data = { .msi_base_shift = 0, .pads_pll_ctl = PADS_PLL_CTL_TEGRA20, .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_DIV10, + .coherent = true, .has_pex_clkreq_en = false, .has_pex_bias_ctrl = false, .has_intr_prsnt_sense = false, @@ -1941,6 +1951,7 @@ static const struct tegra_pcie_soc_data tegra30_pcie_data = { .msi_base_shift = 8, .pads_pll_ctl = PADS_PLL_CTL_TEGRA30, .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN, + .coherent = false, .has_pex_clkreq_en = true, .has_pex_bias_ctrl = true, .has_intr_prsnt_sense = true, @@ -1953,6 +1964,7 @@ static const struct tegra_pcie_soc_data tegra124_pcie_data = { .msi_base_shift = 8, .pads_pll_ctl = PADS_PLL_CTL_TEGRA30, .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN, + .coherent = false, .has_pex_clkreq_en = true, .has_pex_bias_ctrl = true, .has_intr_prsnt_sense = true, |