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2011-09-05Add support for IBM Power ISA 2.06 -- stage 3.HEADmastersewardj6-276/+1487
2011-09-02Add support for s390x model z114.florian1-1/+2
2011-08-27Support "ENTER $imm16, $0"; some part of the OSX 10.7 library stacksewardj1-0/+31
2011-08-19Support alternate (C0 /6) encoding of SHL on x86 and amd64. Fixes #209995.tom2-12/+4
2011-08-19Fix panic message.florian1-1/+1
2011-08-12Support an address size override prefix for REP prefixed stringtom1-41/+84
2011-08-11Add support for CKSM. florian1-1/+69
2011-08-11Support FEMMS in x86 mode as we already do for amd64. Fix for #204574.tom1-1/+2
2011-08-10Support XCHG AX, reg16 on amd64. Fixes #252695.tom1-5/+14
2011-08-08Supplement to r2189.florian1-0/+2
2011-08-08Handle the invalid opcode 0000.florian3-0/+38
2011-08-01Remove a redundant check. Found by Coverity. florian1-2/+1
2011-08-01For a special opcode the address of the next insn was florian1-3/+6
2011-07-30Fix an assert.florian1-0/+1
2011-07-27Do not access addresses that belong to the client executable.florian1-2/+2
2011-07-24Add support for IBM Power ISA 2.06 -- stage 2. Bug 276784.sewardj7-183/+1756
2011-07-23Comparing a boolean value for != 0 yields a result that is identicalflorian1-0/+16
2011-07-22Remove a redundant assert. Minor code tweaks.florian1-11/+4
2011-07-21Neon loads/stores: rename some vars, plus the main function, and addsewardj1-30/+38
2011-07-21Add algebraic simplification as follows:florian1-24/+35
2011-07-21Add support for Thumb2 encodings of PLD and PLDW. Bug 277653.sewardj1-0/+32
2011-07-19Make VMOV.F32 load the correct value into the destination register.sewardj2-2/+2
2011-07-19Fix BLX r14 in ARM mode, which was broken due to incorrect sequencingsewardj1-3/+3
2011-07-19Fix NEON VMUL by float scalar. Bug 277663.sewardj1-13/+28
2011-07-17Update a FIXME. Should have been included in r2174florian1-2/+2
2011-07-16VEX-side changes to enable chasing of unconditional jumps/calls florian1-22/+51
2011-07-11Tighten up an instruction decoding exception forsewardj1-1/+1
2011-07-11Complete the implementation of ARM atomic ops: {LD,ST}REX{,B,H,D} insewardj5-89/+308
2011-07-11Support the STFLE instruction via a dirty helper.florian4-3/+77
2011-07-08Add support for Thumb ADDW reg, reg, #uimm12 and SUBW ditto. Bugsewardj1-0/+48
2011-07-07Add a spec rule for NZ after LOGICQ, whilst chasing after a strangesewardj1-0/+5
2011-07-05Rename S390_GUEST_OFFSET to S390X_GUEST_OFFSET and useflorian3-69/+69
2011-07-05Misc s390x cleanupsflorian4-59/+45
2011-07-04Thumb2 front end: improved analysis of IT instructions that mightsewardj1-6/+102
2011-06-25Get rid of redundant address mode calculation.florian1-1/+1
2011-06-23Update ignored files for VEX.florian0-0/+0
2011-06-16Rename and rationalise the vector narrowing and widening primops, sosewardj15-232/+259
2011-06-16Reduce warning noise (make it in line with main Valgrind build)sewardj1-0/+1
2011-06-15Unbreak Altivec support following r2159 (rename of saturatingsewardj1-1/+2
2011-06-15Implement PACKUSDW (SSE4.1). Fixes #274776.sewardj6-2/+65
2011-06-15Partially fix underspecification of saturating narrowing primops thatsewardj11-100/+127
2011-06-07Change the interface to LibVEX_Translate slightly, so as to make thesewardj5-88/+144
2011-06-06Add some more spec rules, for performance purposes:sewardj1-1/+33
2011-06-05Improvements to code generation for 32 bit instructions. Whensewardj4-80/+220
2011-05-29x86 and amd64 back ends: when generating transfers back to thesewardj12-43/+105
2011-05-28Comment-only change.sewardj1-0/+5
2011-05-27Add a field 'UChar delta' to IRStmt_IMark, and use it to carry aroundsewardj4-25/+65
2011-05-17s390x: provide clock instructions like STCKsewardj3-3/+103
2011-05-11ARM front end only: when processing Thumb instructions, createsewardj1-2/+15
2011-05-09Add LIKELY/UNLIKELY macros for general use, replacing s390x-specificsewardj3-286/+277