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authorAlex Deucher <alexdeucher@gmail.com>2009-12-10 15:29:14 -0500
committerAlex Deucher <alexdeucher@gmail.com>2010-02-01 12:07:26 -0500
commit2c9cf0a07ff9e5a4989861bc2fdfd71d841013a8 (patch)
treeeb65f26dde222d30d1b583f7a527888687c66985
parent65246545c3dd9bfef73e8a0f200bd5909b89a167 (diff)
evergreen: add lut support
-rw-r--r--src/radeon_crtc.c61
1 files changed, 41 insertions, 20 deletions
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index 413bad4f..b50cf42d 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -414,36 +414,57 @@ radeon_crtc_load_lut(xf86CrtcPtr crtc)
if (!crtc->enabled)
return;
- if (IS_AVIVO_VARIANT) {
- OUTREG(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
+ if (IS_DCE4_VARIANT) {
+ OUTREG(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
- OUTREG(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
- OUTREG(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
- OUTREG(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
+ OUTREG(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
+ OUTREG(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
+ OUTREG(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
- OUTREG(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0x0000ffff);
- OUTREG(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0x0000ffff);
- OUTREG(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0x0000ffff);
- }
+ OUTREG(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0x0000ffff);
+ OUTREG(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0x0000ffff);
+ OUTREG(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0x0000ffff);
- PAL_SELECT(radeon_crtc->crtc_id);
+ OUTREG(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
+ OUTREG(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
- if (IS_AVIVO_VARIANT) {
- OUTREG(AVIVO_DC_LUT_RW_MODE, 0);
- OUTREG(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
- }
+ for (i = 0; i < 256; i++) {
+ OUTREG(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, i);
+ OUTREG(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
+ (((radeon_crtc->lut_r[i]) << 20) |
+ ((radeon_crtc->lut_g[i]) << 10) |
+ (radeon_crtc->lut_b[i])));
+ }
+ } else {
+ if (IS_AVIVO_VARIANT) {
+ OUTREG(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
- for (i = 0; i < 256; i++) {
- OUTPAL(i, radeon_crtc->lut_r[i], radeon_crtc->lut_g[i], radeon_crtc->lut_b[i]);
- }
+ OUTREG(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
+ OUTREG(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
+ OUTREG(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
- if (IS_AVIVO_VARIANT) {
- OUTREG(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
+ OUTREG(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0x0000ffff);
+ OUTREG(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0x0000ffff);
+ OUTREG(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0x0000ffff);
+ }
+
+ PAL_SELECT(radeon_crtc->crtc_id);
+
+ if (IS_AVIVO_VARIANT) {
+ OUTREG(AVIVO_DC_LUT_RW_MODE, 0);
+ OUTREG(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
+ }
+
+ for (i = 0; i < 256; i++) {
+ OUTPAL(i, radeon_crtc->lut_r[i], radeon_crtc->lut_g[i], radeon_crtc->lut_b[i]);
+ }
+
+ if (IS_AVIVO_VARIANT)
+ OUTREG(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
}
}
-
static void
radeon_crtc_gamma_set(xf86CrtcPtr crtc, uint16_t *red, uint16_t *green,
uint16_t *blue, int size)