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-rw-r--r--src/gallium/state_trackers/vallium/val_pipeline.c119
1 files changed, 33 insertions, 86 deletions
diff --git a/src/gallium/state_trackers/vallium/val_pipeline.c b/src/gallium/state_trackers/vallium/val_pipeline.c
index d14b78930f9..feb74c56de2 100644
--- a/src/gallium/state_trackers/vallium/val_pipeline.c
+++ b/src/gallium/state_trackers/vallium/val_pipeline.c
@@ -645,23 +645,32 @@ merge_tess_info(struct shader_info *tes_info,
tes_info->tess.point_mode |= tcs_info->tess.point_mode;
}
-static void
-val_pipeline_to_nir(struct val_pipeline *pipeline,
- struct val_shader_module *module,
- const char *entrypoint,
- gl_shader_stage stage,
- const VkSpecializationInfo *spec_info)
+static gl_shader_stage
+val_shader_stage(VkShaderStageFlagBits stage)
{
- struct val_device *device = pipeline->device;
- val_shader_compile_to_ir(pipeline, module, entrypoint, stage, spec_info);
+ switch (stage) {
+ case VK_SHADER_STAGE_VERTEX_BIT:
+ return MESA_SHADER_VERTEX;
+ case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
+ return MESA_SHADER_TESS_CTRL;
+ case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
+ return MESA_SHADER_TESS_EVAL;
+ case VK_SHADER_STAGE_GEOMETRY_BIT:
+ return MESA_SHADER_GEOMETRY;
+ case VK_SHADER_STAGE_FRAGMENT_BIT:
+ return MESA_SHADER_FRAGMENT;
+ case VK_SHADER_STAGE_COMPUTE_BIT:
+ return MESA_SHADER_COMPUTE;
+ default:
+ unreachable("invalid VkShaderStageFlagBits");
+ return MESA_SHADER_NONE;
+ }
}
+
static VkResult
val_pipeline_compile(struct val_pipeline *pipeline,
- struct val_shader_module *module,
- const char *entrypoint,
- gl_shader_stage stage,
- const VkSpecializationInfo *spec_info)
+ gl_shader_stage stage)
{
struct val_device *device = pipeline->device;
device->physical_device->pscreen->finalize_nir(device->physical_device->pscreen, pipeline->pipeline_nir[stage], true);
@@ -715,41 +724,11 @@ val_graphics_pipeline_init(struct val_pipeline *pipeline,
for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
VAL_FROM_HANDLE(val_shader_module, module,
pCreateInfo->pStages[i].module);
-
- switch (pCreateInfo->pStages[i].stage) {
- case VK_SHADER_STAGE_VERTEX_BIT:
- val_pipeline_to_nir(pipeline, module,
- pCreateInfo->pStages[i].pName,
- MESA_SHADER_VERTEX,
- pCreateInfo->pStages[i].pSpecializationInfo);
- break;
- case VK_SHADER_STAGE_FRAGMENT_BIT:
- val_pipeline_to_nir(pipeline, module,
- pCreateInfo->pStages[i].pName,
- MESA_SHADER_FRAGMENT,
- pCreateInfo->pStages[i].pSpecializationInfo);
- break;
- case VK_SHADER_STAGE_GEOMETRY_BIT:
- val_pipeline_to_nir(pipeline, module,
- pCreateInfo->pStages[i].pName,
- MESA_SHADER_GEOMETRY,
- pCreateInfo->pStages[i].pSpecializationInfo);
- break;
- case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
- val_pipeline_to_nir(pipeline, module,
- pCreateInfo->pStages[i].pName,
- MESA_SHADER_TESS_CTRL,
- pCreateInfo->pStages[i].pSpecializationInfo);
- break;
- case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
- val_pipeline_to_nir(pipeline, module,
- pCreateInfo->pStages[i].pName,
- MESA_SHADER_TESS_EVAL,
- pCreateInfo->pStages[i].pSpecializationInfo);
- break;
- default:
- val_finishme("Unsupported shader stage");
- }
+ gl_shader_stage stage = val_shader_stage(pCreateInfo->pStages[i].stage);
+ val_shader_compile_to_ir(pipeline, module,
+ pCreateInfo->pStages[i].pName,
+ stage,
+ pCreateInfo->pStages[i].pSpecializationInfo);
}
if (pipeline->pipeline_nir[MESA_SHADER_TESS_CTRL]) {
nir_lower_patch_vertices(pipeline->pipeline_nir[MESA_SHADER_TESS_EVAL], pipeline->pipeline_nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out, NULL);
@@ -760,41 +739,8 @@ val_graphics_pipeline_init(struct val_pipeline *pipeline,
for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
VAL_FROM_HANDLE(val_shader_module, module,
pCreateInfo->pStages[i].module);
-
- switch (pCreateInfo->pStages[i].stage) {
- case VK_SHADER_STAGE_VERTEX_BIT:
- val_pipeline_compile(pipeline, module,
- pCreateInfo->pStages[i].pName,
- MESA_SHADER_VERTEX,
- pCreateInfo->pStages[i].pSpecializationInfo);
- break;
- case VK_SHADER_STAGE_FRAGMENT_BIT:
- val_pipeline_compile(pipeline, module,
- pCreateInfo->pStages[i].pName,
- MESA_SHADER_FRAGMENT,
- pCreateInfo->pStages[i].pSpecializationInfo);
- break;
- case VK_SHADER_STAGE_GEOMETRY_BIT:
- val_pipeline_compile(pipeline, module,
- pCreateInfo->pStages[i].pName,
- MESA_SHADER_GEOMETRY,
- pCreateInfo->pStages[i].pSpecializationInfo);
- break;
- case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
- val_pipeline_compile(pipeline, module,
- pCreateInfo->pStages[i].pName,
- MESA_SHADER_TESS_CTRL,
- pCreateInfo->pStages[i].pSpecializationInfo);
- break;
- case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
- val_pipeline_compile(pipeline, module,
- pCreateInfo->pStages[i].pName,
- MESA_SHADER_TESS_EVAL,
- pCreateInfo->pStages[i].pSpecializationInfo);
- break;
- default:
- val_finishme("Unsupported shader stage");
- }
+ gl_shader_stage stage = val_shader_stage(pCreateInfo->pStages[i].stage);
+ val_pipeline_compile(pipeline, stage);
}
return VK_SUCCESS;
}
@@ -879,10 +825,11 @@ val_compute_pipeline_init(struct val_pipeline *pipeline,
deep_copy_compute_create_info(&pipeline->compute_create_info, pCreateInfo);
pipeline->is_compute_pipeline = true;
- val_pipeline_compile(pipeline, module,
- pCreateInfo->stage.pName,
- MESA_SHADER_COMPUTE,
- pCreateInfo->stage.pSpecializationInfo);
+ val_shader_compile_to_ir(pipeline, module,
+ pCreateInfo->stage.pName,
+ MESA_SHADER_COMPUTE,
+ pCreateInfo->stage.pSpecializationInfo);
+ val_pipeline_compile(pipeline, MESA_SHADER_COMPUTE);
return VK_SUCCESS;
}