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authorDave Airlie <airlied@redhat.com>2014-05-07 08:55:27 +1000
committerDave Airlie <airlied@redhat.com>2014-05-07 08:55:27 +1000
commit9eabb9110094d92e112d1027e2f05133fa4ae602 (patch)
tree245730fe8b6ee0406df6f12287eabe201ec77cdb /drivers/gpu/drm/radeon/si_dma.c
parent3cf0b0311e746a26dcc7c0b5ba0756f61d636a33 (diff)
parentcbe655137aa8f644f4985021a1e1e65df1d28fa8 (diff)
Merge branch 'drm-fixes-3.15' of git://people.freedesktop.org/~deathsimple/linux into drm-fixes
this is the next pull quested for stashed up radeon fixes for 3.15. As discussed support for Mullins was separated out and will get it's own pull request. Remaining highlights are: 1. Some more patches to better handle PLL limits. 2. Making use of the PFLIP additional to the VBLANK interrupt, otherwise we sometimes miss page flip events. 3. Fix for the UVD command stream parser. 4. Fix for bootup UVD clocks on RV7xx systems. 5. Adding missing error check on dpcd reads. 6. Fixes number of banks calculation on SI. * 'drm-fixes-3.15' of git://people.freedesktop.org/~deathsimple/linux: drm/radeon: lower the ref * post PLL maximum drm/radeon: check that we have a clock before PLL setup drm/radeon: drm/radeon: add missing radeon_semaphore_free to error path drm/radeon: Fix num_banks calculation for SI drm/radeon/dp: check for errors in dpcd reads drm/radeon: avoid high jitter with small frac divs drm/radeon: check buffer relocation offset drm/radeon: use pflip irq on R600+ v2 drm/radeon/uvd: use lower clocks on old UVD to boot v2
Diffstat (limited to 'drivers/gpu/drm/radeon/si_dma.c')
-rw-r--r--drivers/gpu/drm/radeon/si_dma.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/si_dma.c b/drivers/gpu/drm/radeon/si_dma.c
index cf0fdad8c278..de0ca070122f 100644
--- a/drivers/gpu/drm/radeon/si_dma.c
+++ b/drivers/gpu/drm/radeon/si_dma.c
@@ -213,6 +213,7 @@ int si_copy_dma(struct radeon_device *rdev,
r = radeon_fence_emit(rdev, fence, ring->idx);
if (r) {
radeon_ring_unlock_undo(rdev, ring);
+ radeon_semaphore_free(rdev, &sem, NULL);
return r;
}