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authorDave Airlie <airlied@redhat.com>2013-11-10 18:33:17 +1000
committerDave Airlie <airlied@redhat.com>2013-11-10 18:33:17 +1000
commit8d0a2215931f1ffd77aef65cae2c0becc3f5d560 (patch)
tree3e0209cfb61a5453408cb3fc18ab4da6b613579a
parentc4b3a81f4e053bb13382e0ffaf69f3e7e4f124fd (diff)
parent28ed756f1f4cf778785e6b627cabdcf337070fd6 (diff)
Merge branch 'drm-next-3.13' of git://people.freedesktop.org/~agd5f/linux into drm-next
A few more patches for 3.13. The big one here is Hawaii support. I wanted to get that out sooner, but was sick earlier this week. That said, it's mostly self contained, so it shouldn't impact other asics. The rest are just bug fixes and a merge fix. * 'drm-next-3.13' of git://people.freedesktop.org/~agd5f/linux: (23 commits) Revert "drm/radeon/audio: don't set speaker allocation on DCE4+" drm/radeon/audio: improve ACR calculation drm/radeon/audio: correct ACR table drm/radeon: fix mismerge of drm-next with 3.12 drm/radeon: add pci ids for hawaii drm/radeon: fill in radeon_asic_init for hawaii drm/radeon: modesetting updates for hawaii drm/radeon: atombios.h updates for hawaii drm/radeon: update cik_get_csb_buffer for hawaii drm/radeon: add hawaii dpm support drm/radeon/cik: add hawaii UVD support drm/radeon: update firmware loading for hawaii drm/radeon: update rb setup for hawaii drm/radeon: add golden register settings for hawaii drm/radeon: update cik_tiling_mode_table_init() for hawaii drm/radeon: minor updates to cik.c for hawaii drm/radeon: update cik_gpu_init() for hawaii drm/radeon: add Hawaii chip family drm/radeon: fix-up some float to fixed conversion thinkos drm/radeon: use HDP_MEM_COHERENCY_FLUSH_CNTL for sdma as well ...
Diffstat
-rw-r--r--drivers/gpu/drm/radeon/atombios.h127
-rw-r--r--drivers/gpu/drm/radeon/atombios_crtc.c19
-rw-r--r--drivers/gpu/drm/radeon/ci_dpm.c58
-rw-r--r--drivers/gpu/drm/radeon/ci_smc.c4
-rw-r--r--drivers/gpu/drm/radeon/cik.c504
-rw-r--r--drivers/gpu/drm/radeon/cik_sdma.c40
-rw-r--r--drivers/gpu/drm/radeon/cikd.h8
-rw-r--r--drivers/gpu/drm/radeon/dce6_afmt.c23
-rw-r--r--drivers/gpu/drm/radeon/evergreen_hdmi.c23
-rw-r--r--drivers/gpu/drm/radeon/r600_hdmi.c94
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.c57
-rw-r--r--drivers/gpu/drm/radeon/radeon_connectors.c16
-rw-r--r--drivers/gpu/drm/radeon/radeon_device.c1
-rw-r--r--drivers/gpu/drm/radeon/radeon_family.h1
-rw-r--r--drivers/gpu/drm/radeon/radeon_legacy_crtc.c21
-rw-r--r--drivers/gpu/drm/radeon/radeon_pm.c1
-rw-r--r--drivers/gpu/drm/radeon/radeon_ucode.h4
-rw-r--r--drivers/gpu/drm/radeon/radeon_uvd.c1
-rw-r--r--drivers/gpu/drm/radeon/rs690.c16
-rw-r--r--drivers/gpu/drm/radeon/rv515.c8
-rw-r--r--include/drm/drm_pciids.h12
21 files changed, 882 insertions, 156 deletions
diff --git a/drivers/gpu/drm/radeon/atombios.h b/drivers/gpu/drm/radeon/atombios.h
index af10f8571d87..92be50c39ffd 100644
--- a/drivers/gpu/drm/radeon/atombios.h
+++ b/drivers/gpu/drm/radeon/atombios.h
@@ -1711,7 +1711,9 @@ typedef struct _PIXEL_CLOCK_PARAMETERS_V6
1711#define PIXEL_CLOCK_V6_MISC_HDMI_BPP_MASK 0x0c 1711#define PIXEL_CLOCK_V6_MISC_HDMI_BPP_MASK 0x0c
1712#define PIXEL_CLOCK_V6_MISC_HDMI_24BPP 0x00 1712#define PIXEL_CLOCK_V6_MISC_HDMI_24BPP 0x00
1713#define PIXEL_CLOCK_V6_MISC_HDMI_36BPP 0x04 1713#define PIXEL_CLOCK_V6_MISC_HDMI_36BPP 0x04
1714#define PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6 0x08 //for V6, the correct defintion for 36bpp should be 2 for 36bpp(2:1)
1714#define PIXEL_CLOCK_V6_MISC_HDMI_30BPP 0x08 1715#define PIXEL_CLOCK_V6_MISC_HDMI_30BPP 0x08
1716#define PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6 0x04 //for V6, the correct defintion for 30bpp should be 1 for 36bpp(5:4)
1715#define PIXEL_CLOCK_V6_MISC_HDMI_48BPP 0x0c 1717#define PIXEL_CLOCK_V6_MISC_HDMI_48BPP 0x0c
1716#define PIXEL_CLOCK_V6_MISC_REF_DIV_SRC 0x10 1718#define PIXEL_CLOCK_V6_MISC_REF_DIV_SRC 0x10
1717#define PIXEL_CLOCK_V6_MISC_GEN_DPREFCLK 0x40 1719#define PIXEL_CLOCK_V6_MISC_GEN_DPREFCLK 0x40
@@ -2223,7 +2225,7 @@ typedef struct _SET_VOLTAGE_PARAMETERS_V2
2223 USHORT usVoltageLevel; // real voltage level 2225 USHORT usVoltageLevel; // real voltage level
2224}SET_VOLTAGE_PARAMETERS_V2; 2226}SET_VOLTAGE_PARAMETERS_V2;
2225 2227
2226 2228// used by both SetVoltageTable v1.3 and v1.4
2227typedef struct _SET_VOLTAGE_PARAMETERS_V1_3 2229typedef struct _SET_VOLTAGE_PARAMETERS_V1_3
2228{ 2230{
2229 UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI 2231 UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI
@@ -2290,15 +2292,36 @@ typedef struct _GET_LEAKAGE_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1
2290#define ATOM_GET_VOLTAGE_VID 0x00 2292#define ATOM_GET_VOLTAGE_VID 0x00
2291#define ATOM_GET_VOTLAGE_INIT_SEQ 0x03 2293#define ATOM_GET_VOTLAGE_INIT_SEQ 0x03
2292#define ATOM_GET_VOLTTAGE_PHASE_PHASE_VID 0x04 2294#define ATOM_GET_VOLTTAGE_PHASE_PHASE_VID 0x04
2293// for SI, this state map to 0xff02 voltage state in Power Play table, which is power boost state 2295#define ATOM_GET_VOLTAGE_SVID2 0x07 //Get SVI2 Regulator Info
2294#define ATOM_GET_VOLTAGE_STATE0_LEAKAGE_VID 0x10
2295 2296
2297// for SI, this state map to 0xff02 voltage state in Power Play table, which is power boost state
2298#define ATOM_GET_VOLTAGE_STATE0_LEAKAGE_VID 0x10
2296// for SI, this state map to 0xff01 voltage state in Power Play table, which is performance state 2299// for SI, this state map to 0xff01 voltage state in Power Play table, which is performance state
2297#define ATOM_GET_VOLTAGE_STATE1_LEAKAGE_VID 0x11 2300#define ATOM_GET_VOLTAGE_STATE1_LEAKAGE_VID 0x11
2298// undefined power state 2301
2299#define ATOM_GET_VOLTAGE_STATE2_LEAKAGE_VID 0x12 2302#define ATOM_GET_VOLTAGE_STATE2_LEAKAGE_VID 0x12
2300#define ATOM_GET_VOLTAGE_STATE3_LEAKAGE_VID 0x13 2303#define ATOM_GET_VOLTAGE_STATE3_LEAKAGE_VID 0x13
2301 2304
2305// New Added from CI Hawaii for GetVoltageInfoTable, input parameter structure
2306typedef struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2
2307{
2308 UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI
2309 UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info
2310 USHORT usVoltageLevel; // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id
2311 ULONG ulSCLKFreq; // Input: when ucVoltageMode= ATOM_GET_VOLTAGE_EVV_VOLTAGE, DPM state SCLK frequency, Define in PPTable SCLK/Voltage dependence table
2312}GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2;
2313
2314// New in GetVoltageInfo v1.2 ucVoltageMode
2315#define ATOM_GET_VOLTAGE_EVV_VOLTAGE 0x09
2316
2317// New Added from CI Hawaii for EVV feature
2318typedef struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2
2319{
2320 USHORT usVoltageLevel; // real voltage level in unit of mv
2321 USHORT usVoltageId; // Voltage Id programmed in Voltage Regulator
2322 ULONG ulReseved;
2323}GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2;
2324
2302/****************************************************************************/ 2325/****************************************************************************/
2303// Structures used by TVEncoderControlTable 2326// Structures used by TVEncoderControlTable
2304/****************************************************************************/ 2327/****************************************************************************/
@@ -3864,6 +3887,8 @@ typedef struct _ATOM_GPIO_PIN_ASSIGNMENT
3864#define PP_AC_DC_SWITCH_GPIO_PINID 60 3887#define PP_AC_DC_SWITCH_GPIO_PINID 60
3865//from SMU7.x, if ucGPIO_ID=VDDC_REGULATOR_VRHOT_GPIO_PINID in GPIO_LUTable, VRHot feature is enable 3888//from SMU7.x, if ucGPIO_ID=VDDC_REGULATOR_VRHOT_GPIO_PINID in GPIO_LUTable, VRHot feature is enable
3866#define VDDC_VRHOT_GPIO_PINID 61 3889#define VDDC_VRHOT_GPIO_PINID 61
3890//if ucGPIO_ID=VDDC_PCC_GPIO_PINID in GPIO_LUTable, Peak Current Control feature is enabled
3891#define VDDC_PCC_GPIO_PINID 62
3867 3892
3868typedef struct _ATOM_GPIO_PIN_LUT 3893typedef struct _ATOM_GPIO_PIN_LUT
3869{ 3894{
@@ -4169,10 +4194,10 @@ typedef struct _ATOM_COMMON_RECORD_HEADER
4169#define ATOM_OBJECT_LINK_RECORD_TYPE 18 //Once this record is present under one object, it indicats the oobject is linked to another obj described by the record 4194#define ATOM_OBJECT_LINK_RECORD_TYPE 18 //Once this record is present under one object, it indicats the oobject is linked to another obj described by the record
4170#define ATOM_CONNECTOR_REMOTE_CAP_RECORD_TYPE 19 4195#define ATOM_CONNECTOR_REMOTE_CAP_RECORD_TYPE 19
4171#define ATOM_ENCODER_CAP_RECORD_TYPE 20 4196#define ATOM_ENCODER_CAP_RECORD_TYPE 20
4172 4197#define ATOM_BRACKET_LAYOUT_RECORD_TYPE 21
4173 4198
4174//Must be updated when new record type is added,equal to that record definition! 4199//Must be updated when new record type is added,equal to that record definition!
4175#define ATOM_MAX_OBJECT_RECORD_NUMBER ATOM_ENCODER_CAP_RECORD_TYPE 4200#define ATOM_MAX_OBJECT_RECORD_NUMBER ATOM_BRACKET_LAYOUT_RECORD_TYPE
4176 4201
4177typedef struct _ATOM_I2C_RECORD 4202typedef struct _ATOM_I2C_RECORD
4178{ 4203{
@@ -4397,6 +4422,31 @@ typedef struct _ATOM_CONNECTOR_REMOTE_CAP_RECORD
4397 USHORT usReserved; 4422 USHORT usReserved;
4398}ATOM_CONNECTOR_REMOTE_CAP_RECORD; 4423}ATOM_CONNECTOR_REMOTE_CAP_RECORD;
4399 4424
4425typedef struct _ATOM_CONNECTOR_LAYOUT_INFO
4426{
4427 USHORT usConnectorObjectId;
4428 UCHAR ucConnectorType;
4429 UCHAR ucPosition;
4430}ATOM_CONNECTOR_LAYOUT_INFO;
4431
4432// define ATOM_CONNECTOR_LAYOUT_INFO.ucConnectorType to describe the display connector size
4433#define CONNECTOR_TYPE_DVI_D 1
4434#define CONNECTOR_TYPE_DVI_I 2
4435#define CONNECTOR_TYPE_VGA 3
4436#define CONNECTOR_TYPE_HDMI 4
4437#define CONNECTOR_TYPE_DISPLAY_PORT 5
4438#define CONNECTOR_TYPE_MINI_DISPLAY_PORT 6
4439
4440typedef struct _ATOM_BRACKET_LAYOUT_RECORD
4441{
4442 ATOM_COMMON_RECORD_HEADER sheader;
4443 UCHAR ucLength;
4444 UCHAR ucWidth;
4445 UCHAR ucConnNum;
4446 UCHAR ucReserved;
4447 ATOM_CONNECTOR_LAYOUT_INFO asConnInfo[1];
4448}ATOM_BRACKET_LAYOUT_RECORD;
4449
4400/****************************************************************************/ 4450/****************************************************************************/
4401// ASIC voltage data table 4451// ASIC voltage data table
4402/****************************************************************************/ 4452/****************************************************************************/
@@ -4524,8 +4574,9 @@ typedef struct _ATOM_VOLTAGE_OBJECT_HEADER_V3{
4524#define VOLTAGE_OBJ_VR_I2C_INIT_SEQ 3 //VOLTAGE REGULATOR INIT sequece through I2C -> ATOM_I2C_VOLTAGE_OBJECT_V3 4574#define VOLTAGE_OBJ_VR_I2C_INIT_SEQ 3 //VOLTAGE REGULATOR INIT sequece through I2C -> ATOM_I2C_VOLTAGE_OBJECT_V3
4525#define VOLTAGE_OBJ_PHASE_LUT 4 //Set Vregulator Phase lookup table ->ATOM_GPIO_VOLTAGE_OBJECT_V3 4575#define VOLTAGE_OBJ_PHASE_LUT 4 //Set Vregulator Phase lookup table ->ATOM_GPIO_VOLTAGE_OBJECT_V3
4526#define VOLTAGE_OBJ_SVID2 7 //Indicate voltage control by SVID2 ->ATOM_SVID2_VOLTAGE_OBJECT_V3 4576#define VOLTAGE_OBJ_SVID2 7 //Indicate voltage control by SVID2 ->ATOM_SVID2_VOLTAGE_OBJECT_V3
4527#define VOLTAGE_OBJ_PWRBOOST_LEAKAGE_LUT 0x10 //Powerboost Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 4577#define VOLTAGE_OBJ_EVV 8
4528#define VOLTAGE_OBJ_HIGH_STATE_LEAKAGE_LUT 0x11 //High voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 4578#define VOLTAGE_OBJ_PWRBOOST_LEAKAGE_LUT 0x10 //Powerboost Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3
4579#define VOLTAGE_OBJ_HIGH_STATE_LEAKAGE_LUT 0x11 //High voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3
4529#define VOLTAGE_OBJ_HIGH1_STATE_LEAKAGE_LUT 0x12 //High1 voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 4580#define VOLTAGE_OBJ_HIGH1_STATE_LEAKAGE_LUT 0x12 //High1 voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3
4530 4581
4531typedef struct _VOLTAGE_LUT_ENTRY_V2 4582typedef struct _VOLTAGE_LUT_ENTRY_V2
@@ -4552,6 +4603,10 @@ typedef struct _ATOM_I2C_VOLTAGE_OBJECT_V3
4552 VOLTAGE_LUT_ENTRY asVolI2cLut[1]; // end with 0xff 4603 VOLTAGE_LUT_ENTRY asVolI2cLut[1]; // end with 0xff
4553}ATOM_I2C_VOLTAGE_OBJECT_V3; 4604}ATOM_I2C_VOLTAGE_OBJECT_V3;
4554 4605
4606// ATOM_I2C_VOLTAGE_OBJECT_V3.ucVoltageControlFlag
4607#define VOLTAGE_DATA_ONE_BYTE 0
4608#define VOLTAGE_DATA_TWO_BYTE 1
4609
4555typedef struct _ATOM_GPIO_VOLTAGE_OBJECT_V3 4610typedef struct _ATOM_GPIO_VOLTAGE_OBJECT_V3
4556{ 4611{
4557 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_GPIO_LUT or VOLTAGE_OBJ_PHASE_LUT 4612 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_GPIO_LUT or VOLTAGE_OBJ_PHASE_LUT
@@ -4584,7 +4639,8 @@ typedef struct _ATOM_SVID2_VOLTAGE_OBJECT_V3
4584// 1:0 – offset trim, 4639// 1:0 – offset trim,
4585 USHORT usLoadLine_PSI; 4640 USHORT usLoadLine_PSI;
4586// GPU GPIO pin Id to SVID2 regulator VRHot pin. possible value 0~31. 0 means GPIO0, 31 means GPIO31 4641// GPU GPIO pin Id to SVID2 regulator VRHot pin. possible value 0~31. 0 means GPIO0, 31 means GPIO31
4587 UCHAR ucReserved[2]; 4642 UCHAR ucSVDGpioId; //0~31 indicate GPIO0~31
4643 UCHAR ucSVCGpioId; //0~31 indicate GPIO0~31
4588 ULONG ulReserved; 4644 ULONG ulReserved;
4589}ATOM_SVID2_VOLTAGE_OBJECT_V3; 4645}ATOM_SVID2_VOLTAGE_OBJECT_V3;
4590 4646
@@ -4637,6 +4693,49 @@ typedef struct _ATOM_ASIC_PROFILING_INFO_V2_1
4637 USHORT usElbVDDCI_LevelArrayOffset; // offset of 2 dimension voltage level USHORT array 4693 USHORT usElbVDDCI_LevelArrayOffset; // offset of 2 dimension voltage level USHORT array
4638}ATOM_ASIC_PROFILING_INFO_V2_1; 4694}ATOM_ASIC_PROFILING_INFO_V2_1;
4639 4695
4696typedef struct _ATOM_ASIC_PROFILING_INFO_V3_1
4697{
4698 ATOM_COMMON_TABLE_HEADER asHeader;
4699 ULONG ulEvvDerateTdp;
4700 ULONG ulEvvDerateTdc;
4701 ULONG ulBoardCoreTemp;
4702 ULONG ulMaxVddc;
4703 ULONG ulMinVddc;
4704 ULONG ulLoadLineSlop;
4705 ULONG ulLeakageTemp;
4706 ULONG ulLeakageVoltage;
4707 ULONG ulCACmEncodeRange;
4708 ULONG ulCACmEncodeAverage;
4709 ULONG ulCACbEncodeRange;
4710 ULONG ulCACbEncodeAverage;
4711 ULONG ulKt_bEncodeRange;
4712 ULONG ulKt_bEncodeAverage;
4713 ULONG ulKv_mEncodeRange;
4714 ULONG ulKv_mEncodeAverage;
4715 ULONG ulKv_bEncodeRange;
4716 ULONG ulKv_bEncodeAverage;
4717 ULONG ulLkgEncodeLn_MaxDivMin;
4718 ULONG ulLkgEncodeMin;
4719 ULONG ulEfuseLogisticAlpha;
4720 USHORT usPowerDpm0;
4721 USHORT usCurrentDpm0;
4722 USHORT usPowerDpm1;
4723 USHORT usCurrentDpm1;
4724 USHORT usPowerDpm2;
4725 USHORT usCurrentDpm2;
4726 USHORT usPowerDpm3;
4727 USHORT usCurrentDpm3;
4728 USHORT usPowerDpm4;
4729 USHORT usCurrentDpm4;
4730 USHORT usPowerDpm5;
4731 USHORT usCurrentDpm5;
4732 USHORT usPowerDpm6;
4733 USHORT usCurrentDpm6;
4734 USHORT usPowerDpm7;
4735 USHORT usCurrentDpm7;
4736}ATOM_ASIC_PROFILING_INFO_V3_1;
4737
4738
4640typedef struct _ATOM_POWER_SOURCE_OBJECT 4739typedef struct _ATOM_POWER_SOURCE_OBJECT
4641{ 4740{
4642 UCHAR ucPwrSrcId; // Power source 4741 UCHAR ucPwrSrcId; // Power source
@@ -5808,6 +5907,8 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3
5808#define ATOM_S7_DOS_MODE_PIXEL_DEPTHb0 0x0C 5907#define ATOM_S7_DOS_MODE_PIXEL_DEPTHb0 0x0C
5809#define ATOM_S7_DOS_MODE_PIXEL_FORMATb0 0xF0 5908#define ATOM_S7_DOS_MODE_PIXEL_FORMATb0 0xF0
5810#define ATOM_S7_DOS_8BIT_DAC_ENb1 0x01 5909#define ATOM_S7_DOS_8BIT_DAC_ENb1 0x01
5910#define ATOM_S7_ASIC_INIT_COMPLETEb1 0x02
5911#define ATOM_S7_ASIC_INIT_COMPLETE_MASK 0x00000200
5811#define ATOM_S7_DOS_MODE_NUMBERw1 0x0FFFF 5912#define ATOM_S7_DOS_MODE_NUMBERw1 0x0FFFF
5812 5913
5813#define ATOM_S7_DOS_8BIT_DAC_EN_SHIFT 8 5914#define ATOM_S7_DOS_8BIT_DAC_EN_SHIFT 8
@@ -6242,6 +6343,7 @@ typedef struct _ATOM_MC_INIT_PARAM_TABLE
6242#define _128Mx32 0x53 6343#define _128Mx32 0x53
6243#define _256Mx8 0x61 6344#define _256Mx8 0x61
6244#define _256Mx16 0x62 6345#define _256Mx16 0x62
6346#define _512Mx8 0x71
6245 6347
6246#define SAMSUNG 0x1 6348#define SAMSUNG 0x1
6247#define INFINEON 0x2 6349#define INFINEON 0x2
@@ -6987,9 +7089,10 @@ typedef struct _ATOM_DISP_OUT_INFO_V3
6987 UCHAR ucMaxDispEngineNum; 7089 UCHAR ucMaxDispEngineNum;
6988 UCHAR ucMaxActiveDispEngineNum; 7090 UCHAR ucMaxActiveDispEngineNum;
6989 UCHAR ucMaxPPLLNum; 7091 UCHAR ucMaxPPLLNum;
6990 UCHAR ucCoreRefClkSource; // value of CORE_REF_CLK_SOURCE 7092 UCHAR ucCoreRefClkSource; // value of CORE_REF_CLK_SOURCE
6991 UCHAR ucReserved[3]; 7093 UCHAR ucDispCaps;
6992 ASIC_TRANSMITTER_INFO_V2 asTransmitterInfo[1]; // for alligment only 7094 UCHAR ucReserved[2];
7095 ASIC_TRANSMITTER_INFO_V2 asTransmitterInfo[1]; // for alligment only
6993}ATOM_DISP_OUT_INFO_V3; 7096}ATOM_DISP_OUT_INFO_V3;
6994 7097
6995//ucDispCaps 7098//ucDispCaps
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index 86d9ee08b13f..80a20120e625 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -1910,6 +1910,21 @@ static void atombios_crtc_disable(struct drm_crtc *crtc)
1910 int i; 1910 int i;
1911 1911
1912 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 1912 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1913 if (crtc->fb) {
1914 int r;
1915 struct radeon_framebuffer *radeon_fb;
1916 struct radeon_bo *rbo;
1917
1918 radeon_fb = to_radeon_framebuffer(crtc->fb);
1919 rbo = gem_to_radeon_bo(radeon_fb->obj);
1920 r = radeon_bo_reserve(rbo, false);
1921 if (unlikely(r))
1922 DRM_ERROR("failed to reserve rbo before unpin\n");
1923 else {
1924 radeon_bo_unpin(rbo);
1925 radeon_bo_unreserve(rbo);
1926 }
1927 }
1913 /* disable the GRPH */ 1928 /* disable the GRPH */
1914 if (ASIC_IS_DCE4(rdev)) 1929 if (ASIC_IS_DCE4(rdev))
1915 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 0); 1930 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 0);
@@ -1940,7 +1955,9 @@ static void atombios_crtc_disable(struct drm_crtc *crtc)
1940 break; 1955 break;
1941 case ATOM_PPLL0: 1956 case ATOM_PPLL0:
1942 /* disable the ppll */ 1957 /* disable the ppll */
1943 if ((rdev->family == CHIP_ARUBA) || (rdev->family == CHIP_BONAIRE)) 1958 if ((rdev->family == CHIP_ARUBA) ||
1959 (rdev->family == CHIP_BONAIRE) ||
1960 (rdev->family == CHIP_HAWAII))
1944 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, 1961 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1945 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); 1962 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
1946 break; 1963 break;
diff --git a/drivers/gpu/drm/radeon/ci_dpm.c b/drivers/gpu/drm/radeon/ci_dpm.c
index 51e947a97edf..1ed479976358 100644
--- a/drivers/gpu/drm/radeon/ci_dpm.c
+++ b/drivers/gpu/drm/radeon/ci_dpm.c
@@ -40,6 +40,20 @@
40#define VOLTAGE_VID_OFFSET_SCALE1 625 40#define VOLTAGE_VID_OFFSET_SCALE1 625
41#define VOLTAGE_VID_OFFSET_SCALE2 100 41#define VOLTAGE_VID_OFFSET_SCALE2 100
42 42
43static const struct ci_pt_defaults defaults_hawaii_xt =
44{
45 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0xB0000,
46 { 0x84, 0x0, 0x0, 0x7F, 0x0, 0x0, 0x5A, 0x60, 0x51, 0x8E, 0x79, 0x6B, 0x5F, 0x90, 0x79 },
47 { 0x1EA, 0x1EA, 0x1EA, 0x224, 0x224, 0x224, 0x24F, 0x24F, 0x24F, 0x28E, 0x28E, 0x28E, 0x2BC, 0x2BC, 0x2BC }
48};
49
50static const struct ci_pt_defaults defaults_hawaii_pro =
51{
52 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0x65062,
53 { 0x93, 0x0, 0x0, 0x97, 0x0, 0x0, 0x6B, 0x60, 0x51, 0x95, 0x79, 0x6B, 0x5F, 0x90, 0x79 },
54 { 0x1EA, 0x1EA, 0x1EA, 0x224, 0x224, 0x224, 0x24F, 0x24F, 0x24F, 0x28E, 0x28E, 0x28E, 0x2BC, 0x2BC, 0x2BC }
55};
56
43static const struct ci_pt_defaults defaults_bonaire_xt = 57static const struct ci_pt_defaults defaults_bonaire_xt =
44{ 58{
45 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000, 59 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
@@ -187,22 +201,38 @@ static void ci_initialize_powertune_defaults(struct radeon_device *rdev)
187 struct ci_power_info *pi = ci_get_pi(rdev); 201 struct ci_power_info *pi = ci_get_pi(rdev);
188 202
189 switch (rdev->pdev->device) { 203 switch (rdev->pdev->device) {
190 case 0x6650: 204 case 0x6650:
191 case 0x6658: 205 case 0x6658:
192 case 0x665C: 206 case 0x665C:
193 default: 207 default:
194 pi->powertune_defaults = &defaults_bonaire_xt; 208 pi->powertune_defaults = &defaults_bonaire_xt;
195 break; 209 break;
196 case 0x6651: 210 case 0x6651:
197 case 0x665D: 211 case 0x665D:
198 pi->powertune_defaults = &defaults_bonaire_pro; 212 pi->powertune_defaults = &defaults_bonaire_pro;
199 break; 213 break;
200 case 0x6640: 214 case 0x6640:
201 pi->powertune_defaults = &defaults_saturn_xt; 215 pi->powertune_defaults = &defaults_saturn_xt;
202 break; 216 break;
203 case 0x6641: 217 case 0x6641:
204 pi->powertune_defaults = &defaults_saturn_pro; 218 pi->powertune_defaults = &defaults_saturn_pro;
205 break; 219 break;
220 case 0x67B8:
221 case 0x67B0:
222 case 0x67A0:
223 case 0x67A1:
224 case 0x67A2:
225 case 0x67A8:
226 case 0x67A9:
227 case 0x67AA:
228 case 0x67B9:
229 case 0x67BE:
230 pi->powertune_defaults = &defaults_hawaii_xt;
231 break;
232 case 0x67BA:
233 case 0x67B1:
234 pi->powertune_defaults = &defaults_hawaii_pro;
235 break;
206 } 236 }
207 237
208 pi->dte_tj_offset = 0; 238 pi->dte_tj_offset = 0;
@@ -5142,9 +5172,15 @@ int ci_dpm_init(struct radeon_device *rdev)
5142 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; 5172 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
5143 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; 5173 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
5144 5174
5145 pi->thermal_temp_setting.temperature_low = 99500; 5175 if (rdev->family == CHIP_HAWAII) {
5146 pi->thermal_temp_setting.temperature_high = 100000; 5176 pi->thermal_temp_setting.temperature_low = 94500;
5147 pi->thermal_temp_setting.temperature_shutdown = 104000; 5177 pi->thermal_temp_setting.temperature_high = 95000;
5178 pi->thermal_temp_setting.temperature_shutdown = 104000;
5179 } else {
5180 pi->thermal_temp_setting.temperature_low = 99500;
5181 pi->thermal_temp_setting.temperature_high = 100000;
5182 pi->thermal_temp_setting.temperature_shutdown = 104000;
5183 }
5148 5184
5149 pi->uvd_enabled = false; 5185 pi->uvd_enabled = false;
5150 5186
diff --git a/drivers/gpu/drm/radeon/ci_smc.c b/drivers/gpu/drm/radeon/ci_smc.c
index 252e10a41cf5..9c745dd22438 100644
--- a/drivers/gpu/drm/radeon/ci_smc.c
+++ b/drivers/gpu/drm/radeon/ci_smc.c
@@ -217,6 +217,10 @@ int ci_load_smc_ucode(struct radeon_device *rdev, u32 limit)
217 ucode_start_address = BONAIRE_SMC_UCODE_START; 217 ucode_start_address = BONAIRE_SMC_UCODE_START;
218 ucode_size = BONAIRE_SMC_UCODE_SIZE; 218 ucode_size = BONAIRE_SMC_UCODE_SIZE;
219 break; 219 break;
220 case CHIP_HAWAII:
221 ucode_start_address = HAWAII_SMC_UCODE_START;
222 ucode_size = HAWAII_SMC_UCODE_SIZE;
223 break;
220 default: 224 default:
221 DRM_ERROR("unknown asic in smc ucode loader\n"); 225 DRM_ERROR("unknown asic in smc ucode loader\n");
222 BUG(); 226 BUG();
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index e8544758b569..ae92aa041c6a 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -41,6 +41,14 @@ MODULE_FIRMWARE("radeon/BONAIRE_mc.bin");
41MODULE_FIRMWARE("radeon/BONAIRE_rlc.bin"); 41MODULE_FIRMWARE("radeon/BONAIRE_rlc.bin");
42MODULE_FIRMWARE("radeon/BONAIRE_sdma.bin"); 42MODULE_FIRMWARE("radeon/BONAIRE_sdma.bin");
43MODULE_FIRMWARE("radeon/BONAIRE_smc.bin"); 43MODULE_FIRMWARE("radeon/BONAIRE_smc.bin");
44MODULE_FIRMWARE("radeon/HAWAII_pfp.bin");
45MODULE_FIRMWARE("radeon/HAWAII_me.bin");
46MODULE_FIRMWARE("radeon/HAWAII_ce.bin");
47MODULE_FIRMWARE("radeon/HAWAII_mec.bin");
48MODULE_FIRMWARE("radeon/HAWAII_mc.bin");
49MODULE_FIRMWARE("radeon/HAWAII_rlc.bin");
50MODULE_FIRMWARE("radeon/HAWAII_sdma.bin");
51MODULE_FIRMWARE("radeon/HAWAII_smc.bin");
44MODULE_FIRMWARE("radeon/KAVERI_pfp.bin"); 52MODULE_FIRMWARE("radeon/KAVERI_pfp.bin");
45MODULE_FIRMWARE("radeon/KAVERI_me.bin"); 53MODULE_FIRMWARE("radeon/KAVERI_me.bin");
46MODULE_FIRMWARE("radeon/KAVERI_ce.bin"); 54MODULE_FIRMWARE("radeon/KAVERI_ce.bin");
@@ -1297,6 +1305,171 @@ static const u32 kalindi_mgcg_cgcg_init[] =
1297 0xd80c, 0xff000ff0, 0x00000100 1305 0xd80c, 0xff000ff0, 0x00000100
1298}; 1306};
1299 1307
1308static const u32 hawaii_golden_spm_registers[] =
1309{
1310 0x30800, 0xe0ffffff, 0xe0000000
1311};
1312
1313static const u32 hawaii_golden_common_registers[] =
1314{
1315 0x30800, 0xffffffff, 0xe0000000,
1316 0x28350, 0xffffffff, 0x3a00161a,
1317 0x28354, 0xffffffff, 0x0000002e,
1318 0x9a10, 0xffffffff, 0x00018208,
1319 0x98f8, 0xffffffff, 0x12011003
1320};
1321
1322static const u32 hawaii_golden_registers[] =
1323{
1324 0x3354, 0x00000333, 0x00000333,
1325 0x9a10, 0x00010000, 0x00058208,
1326 0x9830, 0xffffffff, 0x00000000,
1327 0x9834, 0xf00fffff, 0x00000400,
1328 0x9838, 0x0002021c, 0x00020200,
1329 0xc78, 0x00000080, 0x00000000,
1330 0x5bb0, 0x000000f0, 0x00000070,
1331 0x5bc0, 0xf0311fff, 0x80300000,
1332 0x350c, 0x00810000, 0x408af000,
1333 0x7030, 0x31000111, 0x00000011,
1334 0x2f48, 0x73773777, 0x12010001,
1335 0x2120, 0x0000007f, 0x0000001b,
1336 0x21dc, 0x00007fb6, 0x00002191,
1337 0x3628, 0x0000003f, 0x0000000a,
1338 0x362c, 0x0000003f, 0x0000000a,
1339 0x2ae4, 0x00073ffe, 0x000022a2,
1340 0x240c, 0x000007ff, 0x00000000,
1341 0x8bf0, 0x00002001, 0x00000001,
1342 0x8b24, 0xffffffff, 0x00ffffff,
1343 0x30a04, 0x0000ff0f, 0x00000000,
1344 0x28a4c, 0x07ffffff, 0x06000000,
1345 0x3e78, 0x00000001, 0x00000002,
1346 0xc768, 0x00000008, 0x00000008,
1347 0xc770, 0x00000f00, 0x00000800,
1348 0xc774, 0x00000f00, 0x00000800,
1349 0xc798, 0x00ffffff, 0x00ff7fbf,
1350 0xc79c, 0x00ffffff, 0x00ff7faf,
1351 0x8c00, 0x000000ff, 0x00000800,
1352 0xe40, 0x00001fff, 0x00001fff,
1353 0x9060, 0x0000007f, 0x00000020,
1354 0x9508, 0x00010000, 0x00010000,
1355 0xae00, 0x00100000, 0x000ff07c,
1356 0xac14, 0x000003ff, 0x0000000f,
1357 0xac10, 0xffffffff, 0x7564fdec,
1358 0xac0c, 0xffffffff, 0x3120b9a8,
1359 0xac08, 0x20000000, 0x0f9c0000
1360};
1361
1362static const u32 hawaii_mgcg_cgcg_init[] =
1363{
1364 0xc420, 0xffffffff, 0xfffffffd,
1365 0x30800, 0xffffffff, 0xe0000000,
1366 0x3c2a0, 0xffffffff, 0x00000100,
1367 0x3c208, 0xffffffff, 0x00000100,
1368 0x3c2c0, 0xffffffff, 0x00000100,
1369 0x3c2c8, 0xffffffff, 0x00000100,
1370 0x3c2c4, 0xffffffff, 0x00000100,
1371 0x55e4, 0xffffffff, 0x00200100,
1372 0x3c280, 0xffffffff, 0x00000100,
1373 0x3c214, 0xffffffff, 0x06000100,
1374 0x3c220, 0xffffffff, 0x00000100,
1375 0x3c218, 0xffffffff, 0x06000100,
1376 0x3c204, 0xffffffff, 0x00000100,
1377 0x3c2e0, 0xffffffff, 0x00000100,
1378 0x3c224, 0xffffffff, 0x00000100,
1379 0x3c200, 0xffffffff, 0x00000100,
1380 0x3c230, 0xffffffff, 0x00000100,
1381 0x3c234, 0xffffffff, 0x00000100,
1382 0x3c250, 0xffffffff, 0x00000100,
1383 0x3c254, 0xffffffff, 0x00000100,
1384 0x3c258, 0xffffffff, 0x00000100,
1385 0x3c25c, 0xffffffff, 0x00000100,
1386 0x3c260, 0xffffffff, 0x00000100,
1387 0x3c27c, 0xffffffff, 0x00000100,
1388 0x3c278, 0xffffffff, 0x00000100,
1389 0x3c210, 0xffffffff, 0x06000100,
1390 0x3c290, 0xffffffff, 0x00000100,
1391 0x3c274, 0xffffffff, 0x00000100,
1392 0x3c2b4, 0xffffffff, 0x00000100,
1393 0x3c2b0, 0xffffffff, 0x00000100,
1394 0x3c270, 0xffffffff, 0x00000100,
1395 0x30800, 0xffffffff, 0xe0000000,
1396 0x3c020, 0xffffffff, 0x00010000,
1397 0x3c024, 0xffffffff, 0x00030002,
1398 0x3c028, 0xffffffff, 0x00040007,
1399 0x3c02c, 0xffffffff, 0x00060005,
1400 0x3c030, 0xffffffff, 0x00090008,
1401 0x3c034, 0xffffffff, 0x00010000,
1402 0x3c038, 0xffffffff, 0x00030002,
1403 0x3c03c, 0xffffffff, 0x00040007,
1404 0x3c040, 0xffffffff, 0x00060005,
1405 0x3c044, 0xffffffff, 0x00090008,
1406 0x3c048, 0xffffffff, 0x00010000,
1407 0x3c04c, 0xffffffff, 0x00030002,
1408 0x3c050, 0xffffffff, 0x00040007,
1409 0x3c054, 0xffffffff, 0x00060005,
1410 0x3c058, 0xffffffff, 0x00090008,
1411 0x3c05c, 0xffffffff, 0x00010000,
1412 0x3c060, 0xffffffff, 0x00030002,
1413 0x3c064, 0xffffffff, 0x00040007,
1414 0x3c068, 0xffffffff, 0x00060005,
1415 0x3c06c, 0xffffffff, 0x00090008,
1416 0x3c070, 0xffffffff, 0x00010000,
1417 0x3c074, 0xffffffff, 0x00030002,
1418 0x3c078, 0xffffffff, 0x00040007,
1419 0x3c07c, 0xffffffff, 0x00060005,
1420 0x3c080, 0xffffffff, 0x00090008,
1421 0x3c084, 0xffffffff, 0x00010000,
1422 0x3c088, 0xffffffff, 0x00030002,
1423 0x3c08c, 0xffffffff, 0x00040007,
1424 0x3c090, 0xffffffff, 0x00060005,
1425 0x3c094, 0xffffffff, 0x00090008,
1426 0x3c098, 0xffffffff, 0x00010000,
1427 0x3c09c, 0xffffffff, 0x00030002,
1428 0x3c0a0, 0xffffffff, 0x00040007,
1429 0x3c0a4, 0xffffffff, 0x00060005,
1430 0x3c0a8, 0xffffffff, 0x00090008,
1431 0x3c0ac, 0xffffffff, 0x00010000,
1432 0x3c0b0, 0xffffffff, 0x00030002,
1433 0x3c0b4, 0xffffffff, 0x00040007,
1434 0x3c0b8, 0xffffffff, 0x00060005,
1435 0x3c0bc, 0xffffffff, 0x00090008,
1436 0x3c0c0, 0xffffffff, 0x00010000,
1437 0x3c0c4, 0xffffffff, 0x00030002,
1438 0x3c0c8, 0xffffffff, 0x00040007,
1439 0x3c0cc, 0xffffffff, 0x00060005,
1440 0x3c0d0, 0xffffffff, 0x00090008,
1441 0x3c0d4, 0xffffffff, 0x00010000,
1442 0x3c0d8, 0xffffffff, 0x00030002,
1443 0x3c0dc, 0xffffffff, 0x00040007,
1444 0x3c0e0, 0xffffffff, 0x00060005,
1445 0x3c0e4, 0xffffffff, 0x00090008,
1446 0x3c0e8, 0xffffffff, 0x00010000,
1447 0x3c0ec, 0xffffffff, 0x00030002,
1448 0x3c0f0, 0xffffffff, 0x00040007,
1449 0x3c0f4, 0xffffffff, 0x00060005,
1450 0x3c0f8, 0xffffffff, 0x00090008,
1451 0xc318, 0xffffffff, 0x00020200,
1452 0x3350, 0xffffffff, 0x00000200,
1453 0x15c0, 0xffffffff, 0x00000400,
1454 0x55e8, 0xffffffff, 0x00000000,
1455 0x2f50, 0xffffffff, 0x00000902,
1456 0x3c000, 0xffffffff, 0x96940200,
1457 0x8708, 0xffffffff, 0x00900100,
1458 0xc424, 0xffffffff, 0x0020003f,
1459 0x38, 0xffffffff, 0x0140001c,
1460 0x3c, 0x000f0000, 0x000f0000,
1461 0x220, 0xffffffff, 0xc060000c,
1462 0x224, 0xc0000fff, 0x00000100,
1463 0xf90, 0xffffffff, 0x00000100,
1464 0xf98, 0x00000101, 0x00000000,
1465 0x20a8, 0xffffffff, 0x00000104,
1466 0x55e4, 0xff000fff, 0x00000100,
1467 0x30cc, 0xc0000fff, 0x00000104,
1468 0xc1e4, 0x00000001, 0x00000001,
1469 0xd00c, 0xff000ff0, 0x00000100,
1470 0xd80c, 0xff000ff0, 0x00000100
1471};
1472
1300static void cik_init_golden_registers(struct radeon_device *rdev) 1473static void cik_init_golden_registers(struct radeon_device *rdev)
1301{ 1474{
1302 switch (rdev->family) { 1475 switch (rdev->family) {
@@ -1342,6 +1515,20 @@ static void cik_init_golden_registers(struct radeon_device *rdev)
1342 spectre_golden_spm_registers, 1515 spectre_golden_spm_registers,
1343 (const u32)ARRAY_SIZE(spectre_golden_spm_registers)); 1516 (const u32)ARRAY_SIZE(spectre_golden_spm_registers));
1344 break; 1517 break;
1518 case CHIP_HAWAII:
1519 radeon_program_register_sequence(rdev,
1520 hawaii_mgcg_cgcg_init,
1521 (const u32)ARRAY_SIZE(hawaii_mgcg_cgcg_init));
1522 radeon_program_register_sequence(rdev,
1523 hawaii_golden_registers,
1524 (const u32)ARRAY_SIZE(hawaii_golden_registers));
1525 radeon_program_register_sequence(rdev,
1526 hawaii_golden_common_registers,
1527 (const u32)ARRAY_SIZE(hawaii_golden_common_registers));
1528 radeon_program_register_sequence(rdev,
1529 hawaii_golden_spm_registers,
1530 (const u32)ARRAY_SIZE(hawaii_golden_spm_registers));
1531 break;
1345 default: 1532 default:
1346 break; 1533 break;
1347 } 1534 }
@@ -1449,6 +1636,35 @@ static const u32 bonaire_io_mc_regs[BONAIRE_IO_MC_REGS_SIZE][2] =
1449 {0x0000009f, 0x00b48000} 1636 {0x0000009f, 0x00b48000}
1450}; 1637};
1451 1638
1639#define HAWAII_IO_MC_REGS_SIZE 22
1640
1641static const u32 hawaii_io_mc_regs[HAWAII_IO_MC_REGS_SIZE][2] =
1642{
1643 {0x0000007d, 0x40000000},
1644 {0x0000007e, 0x40180304},
1645 {0x0000007f, 0x0000ff00},
1646 {0x00000081, 0x00000000},
1647 {0x00000083, 0x00000800},
1648 {0x00000086, 0x00000000},
1649 {0x00000087, 0x00000100},
1650 {0x00000088, 0x00020100},
1651 {0x00000089, 0x00000000},
1652 {0x0000008b, 0x00040000},
1653 {0x0000008c, 0x00000100},
1654 {0x0000008e, 0xff010000},
1655 {0x00000090, 0xffffefff},
1656 {0x00000091, 0xfff3efff},
1657 {0x00000092, 0xfff3efbf},
1658 {0x00000093, 0xf7ffffff},
1659 {0x00000094, 0xffffff7f},
1660 {0x00000095, 0x00000fff},
1661 {0x00000096, 0x00116fff},
1662 {0x00000097, 0x60010000},
1663 {0x00000098, 0x10010000},
1664 {0x0000009f, 0x00c79000}
1665};
1666
1667
1452/** 1668/**
1453 * cik_srbm_select - select specific register instances 1669 * cik_srbm_select - select specific register instances
1454 * 1670 *
@@ -1493,11 +1709,17 @@ static int ci_mc_load_microcode(struct radeon_device *rdev)
1493 1709
1494 switch (rdev->family) { 1710 switch (rdev->family) {
1495 case CHIP_BONAIRE: 1711 case CHIP_BONAIRE:
1496 default:
1497 io_mc_regs = (u32 *)&bonaire_io_mc_regs; 1712 io_mc_regs = (u32 *)&bonaire_io_mc_regs;
1498 ucode_size = CIK_MC_UCODE_SIZE; 1713 ucode_size = CIK_MC_UCODE_SIZE;
1499 regs_size = BONAIRE_IO_MC_REGS_SIZE; 1714 regs_size = BONAIRE_IO_MC_REGS_SIZE;
1500 break; 1715 break;
1716 case CHIP_HAWAII:
1717 io_mc_regs = (u32 *)&hawaii_io_mc_regs;
1718 ucode_size = HAWAII_MC_UCODE_SIZE;
1719 regs_size = HAWAII_IO_MC_REGS_SIZE;
1720 break;
1721 default:
1722 return -EINVAL;
1501 } 1723 }
1502 1724
1503 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK; 1725 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
@@ -1559,8 +1781,8 @@ static int cik_init_microcode(struct radeon_device *rdev)
1559{ 1781{
1560 const char *chip_name; 1782 const char *chip_name;
1561 size_t pfp_req_size, me_req_size, ce_req_size, 1783 size_t pfp_req_size, me_req_size, ce_req_size,
1562 mec_req_size, rlc_req_size, mc_req_size, 1784 mec_req_size, rlc_req_size, mc_req_size = 0,
1563 sdma_req_size, smc_req_size; 1785 sdma_req_size, smc_req_size = 0;
1564 char fw_name[30]; 1786 char fw_name[30];
1565 int err; 1787 int err;
1566 1788
@@ -1578,6 +1800,17 @@ static int cik_init_microcode(struct radeon_device *rdev)
1578 sdma_req_size = CIK_SDMA_UCODE_SIZE * 4; 1800 sdma_req_size = CIK_SDMA_UCODE_SIZE * 4;
1579 smc_req_size = ALIGN(BONAIRE_SMC_UCODE_SIZE, 4); 1801 smc_req_size = ALIGN(BONAIRE_SMC_UCODE_SIZE, 4);
1580 break; 1802 break;
1803 case CHIP_HAWAII:
1804 chip_name = "HAWAII";
1805 pfp_req_size = CIK_PFP_UCODE_SIZE * 4;
1806 me_req_size = CIK_ME_UCODE_SIZE * 4;
1807 ce_req_size = CIK_CE_UCODE_SIZE * 4;
1808 mec_req_size = CIK_MEC_UCODE_SIZE * 4;
1809 rlc_req_size = BONAIRE_RLC_UCODE_SIZE * 4;
1810 mc_req_size = HAWAII_MC_UCODE_SIZE * 4;
1811 sdma_req_size = CIK_SDMA_UCODE_SIZE * 4;
1812 smc_req_size = ALIGN(HAWAII_SMC_UCODE_SIZE, 4);
1813 break;
1581 case CHIP_KAVERI: 1814 case CHIP_KAVERI:
1582 chip_name = "KAVERI"; 1815 chip_name = "KAVERI";
1583 pfp_req_size = CIK_PFP_UCODE_SIZE * 4; 1816 pfp_req_size = CIK_PFP_UCODE_SIZE * 4;
@@ -1758,9 +1991,227 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
1758 1991
1759 num_pipe_configs = rdev->config.cik.max_tile_pipes; 1992 num_pipe_configs = rdev->config.cik.max_tile_pipes;
1760 if (num_pipe_configs > 8) 1993 if (num_pipe_configs > 8)
1761 num_pipe_configs = 8; /* ??? */ 1994 num_pipe_configs = 16;
1762 1995
1763 if (num_pipe_configs == 8) { 1996 if (num_pipe_configs == 16) {
1997 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1998 switch (reg_offset) {
1999 case 0:
2000 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2001 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2002 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2003 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
2004 break;
2005 case 1:
2006 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2007 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2008 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2009 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
2010 break;
2011 case 2:
2012 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2013 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2014 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2015 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2016 break;
2017 case 3:
2018 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2019 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2020 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2021 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
2022 break;
2023 case 4:
2024 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2025 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2026 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2027 TILE_SPLIT(split_equal_to_row_size));
2028 break;
2029 case 5:
2030 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2031 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2032 break;
2033 case 6:
2034 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2035 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2036 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2037 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2038 break;
2039 case 7:
2040 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2041 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2042 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2043 TILE_SPLIT(split_equal_to_row_size));
2044 break;
2045 case 8:
2046 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2047 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
2048 break;
2049 case 9:
2050 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2051 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
2052 break;
2053 case 10:
2054 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2055 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2056 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2057 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2058 break;
2059 case 11:
2060 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2061 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2062 PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) |
2063 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2064 break;
2065 case 12:
2066 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2067 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2068 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2069 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2070 break;
2071 case 13:
2072 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2073 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
2074 break;
2075 case 14:
2076 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2077 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2078 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2079 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2080 break;
2081 case 16:
2082 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2083 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2084 PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) |
2085 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2086 break;
2087 case 17:
2088 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2089 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2090 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2091 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2092 break;
2093 case 27:
2094 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2095 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
2096 break;
2097 case 28:
2098 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2099 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2100 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2101 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2102 break;
2103 case 29:
2104 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2105 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2106 PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) |
2107 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2108 break;
2109 case 30:
2110 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2111 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2112 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2113 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2114 break;
2115 default:
2116 gb_tile_moden = 0;
2117 break;
2118 }
2119 rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;
2120 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
2121 }
2122 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
2123 switch (reg_offset) {
2124 case 0:
2125 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2126 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2127 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2128 NUM_BANKS(ADDR_SURF_16_BANK));
2129 break;
2130 case 1:
2131 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2132 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2133 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2134 NUM_BANKS(ADDR_SURF_16_BANK));
2135 break;
2136 case 2:
2137 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2138 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2139 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2140 NUM_BANKS(ADDR_SURF_16_BANK));
2141 break;
2142 case 3:
2143 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2144 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2145 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2146 NUM_BANKS(ADDR_SURF_16_BANK));
2147 break;
2148 case 4:
2149 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2150 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2151 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2152 NUM_BANKS(ADDR_SURF_8_BANK));
2153 break;
2154 case 5:
2155 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2156 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2157 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2158 NUM_BANKS(ADDR_SURF_4_BANK));
2159 break;
2160 case 6:
2161 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2162 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2163 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2164 NUM_BANKS(ADDR_SURF_2_BANK));
2165 break;
2166 case 8:
2167 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2168 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2169 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2170 NUM_BANKS(ADDR_SURF_16_BANK));
2171 break;
2172 case 9:
2173 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2174 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2175 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2176 NUM_BANKS(ADDR_SURF_16_BANK));
2177 break;
2178 case 10:
2179 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2180 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2181 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2182 NUM_BANKS(ADDR_SURF_16_BANK));
2183 break;
2184 case 11:
2185 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2186 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2187 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2188 NUM_BANKS(ADDR_SURF_8_BANK));
2189 break;
2190 case 12:
2191 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2192 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2193 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2194 NUM_BANKS(ADDR_SURF_4_BANK));
2195 break;
2196 case 13:
2197 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2198 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2199 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2200 NUM_BANKS(ADDR_SURF_2_BANK));
2201 break;
2202 case 14:
2203 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2204 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2205 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2206 NUM_BANKS(ADDR_SURF_2_BANK));
2207 break;
2208 default:
2209 gb_tile_moden = 0;
2210 break;
2211 }
2212 WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);
2213 }
2214 } else if (num_pipe_configs == 8) {
1764 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { 2215 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1765 switch (reg_offset) { 2216 switch (reg_offset) {
1766 case 0: 2217 case 0:
@@ -2645,7 +3096,10 @@ static void cik_setup_rb(struct radeon_device *rdev,
2645 for (j = 0; j < sh_per_se; j++) { 3096 for (j = 0; j < sh_per_se; j++) {
2646 cik_select_se_sh(rdev, i, j); 3097 cik_select_se_sh(rdev, i, j);
2647 data = cik_get_rb_disabled(rdev, max_rb_num, se_num, sh_per_se); 3098 data = cik_get_rb_disabled(rdev, max_rb_num, se_num, sh_per_se);
2648 disabled_rbs |= data << ((i * sh_per_se + j) * CIK_RB_BITMAP_WIDTH_PER_SH); 3099 if (rdev->family == CHIP_HAWAII)
3100 disabled_rbs |= data << ((i * sh_per_se + j) * HAWAII_RB_BITMAP_WIDTH_PER_SH);
3101 else
3102 disabled_rbs |= data << ((i * sh_per_se + j) * CIK_RB_BITMAP_WIDTH_PER_SH);
2649 } 3103 }
2650 } 3104 }
2651 cik_select_se_sh(rdev, 0xffffffff, 0xffffffff); 3105 cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
@@ -2662,6 +3116,12 @@ static void cik_setup_rb(struct radeon_device *rdev,
2662 data = 0; 3116 data = 0;
2663 for (j = 0; j < sh_per_se; j++) { 3117 for (j = 0; j < sh_per_se; j++) {
2664 switch (enabled_rbs & 3) { 3118 switch (enabled_rbs & 3) {
3119 case 0:
3120 if (j == 0)
3121 data |= PKR_MAP(RASTER_CONFIG_RB_MAP_3);
3122 else
3123 data |= PKR_MAP(RASTER_CONFIG_RB_MAP_0);
3124 break;
2665 case 1: 3125 case 1:
2666 data |= (RASTER_CONFIG_RB_MAP_0 << (i * sh_per_se + j) * 2); 3126 data |= (RASTER_CONFIG_RB_MAP_0 << (i * sh_per_se + j) * 2);
2667 break; 3127 break;
@@ -2714,6 +3174,23 @@ static void cik_gpu_init(struct radeon_device *rdev)
2714 rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130; 3174 rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130;
2715 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN; 3175 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
2716 break; 3176 break;
3177 case CHIP_HAWAII:
3178 rdev->config.cik.max_shader_engines = 4;
3179 rdev->config.cik.max_tile_pipes = 16;
3180 rdev->config.cik.max_cu_per_sh = 11;
3181 rdev->config.cik.max_sh_per_se = 1;
3182 rdev->config.cik.max_backends_per_se = 4;
3183 rdev->config.cik.max_texture_channel_caches = 16;
3184 rdev->config.cik.max_gprs = 256;
3185 rdev->config.cik.max_gs_threads = 32;
3186 rdev->config.cik.max_hw_contexts = 8;
3187
3188 rdev->config.cik.sc_prim_fifo_size_frontend = 0x20;
3189 rdev->config.cik.sc_prim_fifo_size_backend = 0x100;
3190 rdev->config.cik.sc_hiz_tile_fifo_size = 0x30;
3191 rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130;
3192 gb_addr_config = HAWAII_GB_ADDR_CONFIG_GOLDEN;
3193 break;
2717 case CHIP_KAVERI: 3194 case CHIP_KAVERI:
2718 rdev->config.cik.max_shader_engines = 1; 3195 rdev->config.cik.max_shader_engines = 1;
2719 rdev->config.cik.max_tile_pipes = 4; 3196 rdev->config.cik.max_tile_pipes = 4;
@@ -3477,7 +3954,8 @@ static int cik_cp_gfx_resume(struct radeon_device *rdev)
3477 int r; 3954 int r;
3478 3955
3479 WREG32(CP_SEM_WAIT_TIMER, 0x0); 3956 WREG32(CP_SEM_WAIT_TIMER, 0x0);
3480 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); 3957 if (rdev->family != CHIP_HAWAII)
3958 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
3481 3959
3482 /* Set the write pointer delay */ 3960 /* Set the write pointer delay */
3483 WREG32(CP_RB_WPTR_DELAY, 0); 3961 WREG32(CP_RB_WPTR_DELAY, 0);
@@ -4814,12 +5292,17 @@ void cik_vm_fini(struct radeon_device *rdev)
4814static void cik_vm_decode_fault(struct radeon_device *rdev, 5292static void cik_vm_decode_fault(struct radeon_device *rdev,
4815 u32 status, u32 addr, u32 mc_client) 5293 u32 status, u32 addr, u32 mc_client)
4816{ 5294{
4817 u32 mc_id = (status & MEMORY_CLIENT_ID_MASK) >> MEMORY_CLIENT_ID_SHIFT; 5295 u32 mc_id;
4818 u32 vmid = (status & FAULT_VMID_MASK) >> FAULT_VMID_SHIFT; 5296 u32 vmid = (status & FAULT_VMID_MASK) >> FAULT_VMID_SHIFT;
4819 u32 protections = (status & PROTECTIONS_MASK) >> PROTECTIONS_SHIFT; 5297 u32 protections = (status & PROTECTIONS_MASK) >> PROTECTIONS_SHIFT;
4820 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff, 5298 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
4821 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 }; 5299 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
4822 5300
5301 if (rdev->family == CHIP_HAWAII)
5302 mc_id = (status & HAWAII_MEMORY_CLIENT_ID_MASK) >> MEMORY_CLIENT_ID_SHIFT;
5303 else
5304 mc_id = (status & MEMORY_CLIENT_ID_MASK) >> MEMORY_CLIENT_ID_SHIFT;
5305
4823 printk("VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n", 5306 printk("VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
4824 protections, vmid, addr, 5307 protections, vmid, addr,
4825 (status & MEMORY_CLIENT_RW_MASK) ? "write" : "read", 5308 (status & MEMORY_CLIENT_RW_MASK) ? "write" : "read",
@@ -5076,6 +5559,7 @@ static int cik_rlc_resume(struct radeon_device *rdev)
5076 5559
5077 switch (rdev->family) { 5560 switch (rdev->family) {
5078 case CHIP_BONAIRE: 5561 case CHIP_BONAIRE:
5562 case CHIP_HAWAII:
5079 default: 5563 default:
5080 size = BONAIRE_RLC_UCODE_SIZE; 5564 size = BONAIRE_RLC_UCODE_SIZE;
5081 break; 5565 break;
@@ -5832,6 +6316,10 @@ void cik_get_csb_buffer(struct radeon_device *rdev, volatile u32 *buffer)
5832 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */ 6316 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */
5833 buffer[count++] = cpu_to_le32(0x00000000); 6317 buffer[count++] = cpu_to_le32(0x00000000);
5834 break; 6318 break;
6319 case CHIP_HAWAII:
6320 buffer[count++] = 0x3a00161a;
6321 buffer[count++] = 0x0000002e;
6322 break;
5835 default: 6323 default:
5836 buffer[count++] = cpu_to_le32(0x00000000); 6324 buffer[count++] = cpu_to_le32(0x00000000);
5837 buffer[count++] = cpu_to_le32(0x00000000); 6325 buffer[count++] = cpu_to_le32(0x00000000);
diff --git a/drivers/gpu/drm/radeon/cik_sdma.c b/drivers/gpu/drm/radeon/cik_sdma.c
index 8d84ebe2b6fa..9c9529de20ee 100644
--- a/drivers/gpu/drm/radeon/cik_sdma.c
+++ b/drivers/gpu/drm/radeon/cik_sdma.c
@@ -102,14 +102,6 @@ void cik_sdma_fence_ring_emit(struct radeon_device *rdev,
102{ 102{
103 struct radeon_ring *ring = &rdev->ring[fence->ring]; 103 struct radeon_ring *ring = &rdev->ring[fence->ring];
104 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; 104 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
105 u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) |
106 SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */
107 u32 ref_and_mask;
108
109 if (fence->ring == R600_RING_TYPE_DMA_INDEX)
110 ref_and_mask = SDMA0;
111 else
112 ref_and_mask = SDMA1;
113 105
114 /* write the fence */ 106 /* write the fence */
115 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0)); 107 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
@@ -119,12 +111,12 @@ void cik_sdma_fence_ring_emit(struct radeon_device *rdev,
119 /* generate an interrupt */ 111 /* generate an interrupt */
120 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0)); 112 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0));
121 /* flush HDP */ 113 /* flush HDP */
122 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits)); 114 /* We should be using the new POLL_REG_MEM special op packet here
123 radeon_ring_write(ring, GPU_HDP_FLUSH_DONE); 115 * but it causes sDMA to hang sometimes
124 radeon_ring_write(ring, GPU_HDP_FLUSH_REQ); 116 */
125 radeon_ring_write(ring, ref_and_mask); /* REFERENCE */ 117 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
126 radeon_ring_write(ring, ref_and_mask); /* MASK */ 118 radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2);
127 radeon_ring_write(ring, (4 << 16) | 10); /* RETRY_COUNT, POLL_INTERVAL */ 119 radeon_ring_write(ring, 0);
128} 120}
129 121
130/** 122/**
@@ -720,18 +712,10 @@ void cik_sdma_vm_set_page(struct radeon_device *rdev,
720void cik_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm) 712void cik_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
721{ 713{
722 struct radeon_ring *ring = &rdev->ring[ridx]; 714 struct radeon_ring *ring = &rdev->ring[ridx];
723 u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) |
724 SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */
725 u32 ref_and_mask;
726 715
727 if (vm == NULL) 716 if (vm == NULL)
728 return; 717 return;
729 718
730 if (ridx == R600_RING_TYPE_DMA_INDEX)
731 ref_and_mask = SDMA0;
732 else
733 ref_and_mask = SDMA1;
734
735 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); 719 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
736 if (vm->id < 8) { 720 if (vm->id < 8) {
737 radeon_ring_write(ring, (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2); 721 radeon_ring_write(ring, (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2);
@@ -766,12 +750,12 @@ void cik_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm
766 radeon_ring_write(ring, VMID(0)); 750 radeon_ring_write(ring, VMID(0));
767 751
768 /* flush HDP */ 752 /* flush HDP */
769 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits)); 753 /* We should be using the new POLL_REG_MEM special op packet here
770 radeon_ring_write(ring, GPU_HDP_FLUSH_DONE); 754 * but it causes sDMA to hang sometimes
771 radeon_ring_write(ring, GPU_HDP_FLUSH_REQ); 755 */
772 radeon_ring_write(ring, ref_and_mask); /* REFERENCE */ 756 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
773 radeon_ring_write(ring, ref_and_mask); /* MASK */ 757 radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2);
774 radeon_ring_write(ring, (4 << 16) | 10); /* RETRY_COUNT, POLL_INTERVAL */ 758 radeon_ring_write(ring, 0);
775 759
776 /* flush TLB */ 760 /* flush TLB */
777 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); 761 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
diff --git a/drivers/gpu/drm/radeon/cikd.h b/drivers/gpu/drm/radeon/cikd.h
index 380cea311a2b..5964af5e5b2d 100644
--- a/drivers/gpu/drm/radeon/cikd.h
+++ b/drivers/gpu/drm/radeon/cikd.h
@@ -25,8 +25,10 @@
25#define CIK_H 25#define CIK_H
26 26
27#define BONAIRE_GB_ADDR_CONFIG_GOLDEN 0x12010001 27#define BONAIRE_GB_ADDR_CONFIG_GOLDEN 0x12010001
28#define HAWAII_GB_ADDR_CONFIG_GOLDEN 0x12011003
28 29
29#define CIK_RB_BITMAP_WIDTH_PER_SH 2 30#define CIK_RB_BITMAP_WIDTH_PER_SH 2
31#define HAWAII_RB_BITMAP_WIDTH_PER_SH 4
30 32
31/* DIDT IND registers */ 33/* DIDT IND registers */
32#define DIDT_SQ_CTRL0 0x0 34#define DIDT_SQ_CTRL0 0x0
@@ -499,6 +501,7 @@
499 * bit 4: write 501 * bit 4: write
500 */ 502 */
501#define MEMORY_CLIENT_ID_MASK (0xff << 12) 503#define MEMORY_CLIENT_ID_MASK (0xff << 12)
504#define HAWAII_MEMORY_CLIENT_ID_MASK (0x1ff << 12)
502#define MEMORY_CLIENT_ID_SHIFT 12 505#define MEMORY_CLIENT_ID_SHIFT 12
503#define MEMORY_CLIENT_RW_MASK (1 << 24) 506#define MEMORY_CLIENT_RW_MASK (1 << 24)
504#define MEMORY_CLIENT_RW_SHIFT 24 507#define MEMORY_CLIENT_RW_SHIFT 24
@@ -1162,6 +1165,8 @@
1162# define ADDR_SURF_P8_32x32_16x16 12 1165# define ADDR_SURF_P8_32x32_16x16 12
1163# define ADDR_SURF_P8_32x32_16x32 13 1166# define ADDR_SURF_P8_32x32_16x32 13
1164# define ADDR_SURF_P8_32x64_32x32 14 1167# define ADDR_SURF_P8_32x64_32x32 14
1168# define ADDR_SURF_P16_32x32_8x16 16
1169# define ADDR_SURF_P16_32x32_16x16 17
1165# define TILE_SPLIT(x) ((x) << 11) 1170# define TILE_SPLIT(x) ((x) << 11)
1166# define ADDR_SURF_TILE_SPLIT_64B 0 1171# define ADDR_SURF_TILE_SPLIT_64B 0
1167# define ADDR_SURF_TILE_SPLIT_128B 1 1172# define ADDR_SURF_TILE_SPLIT_128B 1
@@ -1455,6 +1460,7 @@
1455# define RASTER_CONFIG_RB_MAP_1 1 1460# define RASTER_CONFIG_RB_MAP_1 1
1456# define RASTER_CONFIG_RB_MAP_2 2 1461# define RASTER_CONFIG_RB_MAP_2 2
1457# define RASTER_CONFIG_RB_MAP_3 3 1462# define RASTER_CONFIG_RB_MAP_3 3
1463#define PKR_MAP(x) ((x) << 8)
1458 1464
1459#define VGT_EVENT_INITIATOR 0x28a90 1465#define VGT_EVENT_INITIATOR 0x28a90
1460# define SAMPLE_STREAMOUTSTATS1 (1 << 0) 1466# define SAMPLE_STREAMOUTSTATS1 (1 << 0)
diff --git a/drivers/gpu/drm/radeon/dce6_afmt.c b/drivers/gpu/drm/radeon/dce6_afmt.c
index ab92620ed83a..009f46e0ce72 100644
--- a/drivers/gpu/drm/radeon/dce6_afmt.c
+++ b/drivers/gpu/drm/radeon/dce6_afmt.c
@@ -156,9 +156,6 @@ void dce6_afmt_write_speaker_allocation(struct drm_encoder *encoder)
156 u8 *sadb; 156 u8 *sadb;
157 int sad_count; 157 int sad_count;
158 158
159 /* XXX: setting this register causes hangs on some asics */
160 return;
161
162 if (!dig->afmt->pin) 159 if (!dig->afmt->pin)
163 return; 160 return;
164 161
@@ -244,20 +241,30 @@ void dce6_afmt_write_sad_regs(struct drm_encoder *encoder)
244 241
245 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { 242 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
246 u32 value = 0; 243 u32 value = 0;
244 u8 stereo_freqs = 0;
245 int max_channels = -1;
247 int j; 246 int j;
248 247
249 for (j = 0; j < sad_count; j++) { 248 for (j = 0; j < sad_count; j++) {
250 struct cea_sad *sad = &sads[j]; 249 struct cea_sad *sad = &sads[j];
251 250
252 if (sad->format == eld_reg_to_type[i][1]) { 251 if (sad->format == eld_reg_to_type[i][1]) {
253 value = MAX_CHANNELS(sad->channels) | 252 if (sad->channels > max_channels) {
254 DESCRIPTOR_BYTE_2(sad->byte2) | 253 value = MAX_CHANNELS(sad->channels) |
255 SUPPORTED_FREQUENCIES(sad->freq); 254 DESCRIPTOR_BYTE_2(sad->byte2) |
255 SUPPORTED_FREQUENCIES(sad->freq);
256 max_channels = sad->channels;
257 }
258
256 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) 259 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
257 value |= SUPPORTED_FREQUENCIES_STEREO(sad->freq); 260 stereo_freqs |= sad->freq;
258 break; 261 else
262 break;
259 } 263 }
260 } 264 }
265
266 value |= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs);
267
261 WREG32_ENDPOINT(offset, eld_reg_to_type[i][0], value); 268 WREG32_ENDPOINT(offset, eld_reg_to_type[i][0], value);
262 } 269 }
263 270
diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c b/drivers/gpu/drm/radeon/evergreen_hdmi.c
index a82b6f78d7f2..aa695c4feb3d 100644
--- a/drivers/gpu/drm/radeon/evergreen_hdmi.c
+++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c
@@ -105,9 +105,6 @@ static void dce4_afmt_write_speaker_allocation(struct drm_encoder *encoder)
105 u8 *sadb; 105 u8 *sadb;
106 int sad_count; 106 int sad_count;
107 107
108 /* XXX: setting this register causes hangs on some asics */
109 return;
110
111 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 108 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
112 if (connector->encoder == encoder) { 109 if (connector->encoder == encoder) {
113 radeon_connector = to_radeon_connector(connector); 110 radeon_connector = to_radeon_connector(connector);
@@ -184,20 +181,30 @@ static void evergreen_hdmi_write_sad_regs(struct drm_encoder *encoder)
184 181
185 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { 182 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
186 u32 value = 0; 183 u32 value = 0;
184 u8 stereo_freqs = 0;
185 int max_channels = -1;
187 int j; 186 int j;
188 187
189 for (j = 0; j < sad_count; j++) { 188 for (j = 0; j < sad_count; j++) {
190 struct cea_sad *sad = &sads[j]; 189 struct cea_sad *sad = &sads[j];
191 190
192 if (sad->format == eld_reg_to_type[i][1]) { 191 if (sad->format == eld_reg_to_type[i][1]) {
193 value = MAX_CHANNELS(sad->channels) | 192 if (sad->channels > max_channels) {
194 DESCRIPTOR_BYTE_2(sad->byte2) | 193 value = MAX_CHANNELS(sad->channels) |
195 SUPPORTED_FREQUENCIES(sad->freq); 194 DESCRIPTOR_BYTE_2(sad->byte2) |
195 SUPPORTED_FREQUENCIES(sad->freq);
196 max_channels = sad->channels;
197 }
198
196 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) 199 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
197 value |= SUPPORTED_FREQUENCIES_STEREO(sad->freq); 200 stereo_freqs |= sad->freq;
198 break; 201 else
202 break;
199 } 203 }
200 } 204 }
205
206 value |= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs);
207
201 WREG32(eld_reg_to_type[i][0], value); 208 WREG32(eld_reg_to_type[i][0], value);
202 } 209 }
203 210
diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c b/drivers/gpu/drm/radeon/r600_hdmi.c
index 0977c303aeec..4b89262f3f0e 100644
--- a/drivers/gpu/drm/radeon/r600_hdmi.c
+++ b/drivers/gpu/drm/radeon/r600_hdmi.c
@@ -24,6 +24,7 @@
24 * Authors: Christian König 24 * Authors: Christian König
25 */ 25 */
26#include <linux/hdmi.h> 26#include <linux/hdmi.h>
27#include <linux/gcd.h>
27#include <drm/drmP.h> 28#include <drm/drmP.h>
28#include <drm/radeon_drm.h> 29#include <drm/radeon_drm.h>
29#include "radeon.h" 30#include "radeon.h"
@@ -57,35 +58,57 @@ enum r600_hdmi_iec_status_bits {
57static const struct radeon_hdmi_acr r600_hdmi_predefined_acr[] = { 58static const struct radeon_hdmi_acr r600_hdmi_predefined_acr[] = {
58 /* 32kHz 44.1kHz 48kHz */ 59 /* 32kHz 44.1kHz 48kHz */
59 /* Clock N CTS N CTS N CTS */ 60 /* Clock N CTS N CTS N CTS */
60 { 25175, 4576, 28125, 7007, 31250, 6864, 28125 }, /* 25,20/1.001 MHz */ 61 { 25175, 4096, 25175, 28224, 125875, 6144, 25175 }, /* 25,20/1.001 MHz */
61 { 25200, 4096, 25200, 6272, 28000, 6144, 25200 }, /* 25.20 MHz */ 62 { 25200, 4096, 25200, 6272, 28000, 6144, 25200 }, /* 25.20 MHz */
62 { 27000, 4096, 27000, 6272, 30000, 6144, 27000 }, /* 27.00 MHz */ 63 { 27000, 4096, 27000, 6272, 30000, 6144, 27000 }, /* 27.00 MHz */
63 { 27027, 4096, 27027, 6272, 30030, 6144, 27027 }, /* 27.00*1.001 MHz */ 64 { 27027, 4096, 27027, 6272, 30030, 6144, 27027 }, /* 27.00*1.001 MHz */
64 { 54000, 4096, 54000, 6272, 60000, 6144, 54000 }, /* 54.00 MHz */ 65 { 54000, 4096, 54000, 6272, 60000, 6144, 54000 }, /* 54.00 MHz */
65 { 54054, 4096, 54054, 6272, 60060, 6144, 54054 }, /* 54.00*1.001 MHz */ 66 { 54054, 4096, 54054, 6272, 60060, 6144, 54054 }, /* 54.00*1.001 MHz */
66 { 74176, 11648, 210937, 17836, 234375, 11648, 140625 }, /* 74.25/1.001 MHz */ 67 { 74176, 4096, 74176, 5733, 75335, 6144, 74176 }, /* 74.25/1.001 MHz */
67 { 74250, 4096, 74250, 6272, 82500, 6144, 74250 }, /* 74.25 MHz */ 68 { 74250, 4096, 74250, 6272, 82500, 6144, 74250 }, /* 74.25 MHz */
68 { 148352, 11648, 421875, 8918, 234375, 5824, 140625 }, /* 148.50/1.001 MHz */ 69 { 148352, 4096, 148352, 5733, 150670, 6144, 148352 }, /* 148.50/1.001 MHz */
69 { 148500, 4096, 148500, 6272, 165000, 6144, 148500 }, /* 148.50 MHz */ 70 { 148500, 4096, 148500, 6272, 165000, 6144, 148500 }, /* 148.50 MHz */
70 { 0, 4096, 0, 6272, 0, 6144, 0 } /* Other */
71}; 71};
72 72
73
73/* 74/*
74 * calculate CTS value if it's not found in the table 75 * calculate CTS and N values if they are not found in the table
75 */ 76 */
76static void r600_hdmi_calc_cts(uint32_t clock, int *CTS, int N, int freq) 77static void r600_hdmi_calc_cts(uint32_t clock, int *CTS, int *N, int freq)
77{ 78{
78 u64 n; 79 int n, cts;
79 u32 d; 80 unsigned long div, mul;
80 81
81 if (*CTS == 0) { 82 /* Safe, but overly large values */
82 n = (u64)clock * (u64)N * 1000ULL; 83 n = 128 * freq;
83 d = 128 * freq; 84 cts = clock * 1000;
84 do_div(n, d); 85
85 *CTS = n; 86 /* Smallest valid fraction */
86 } 87 div = gcd(n, cts);
87 DRM_DEBUG("Using ACR timing N=%d CTS=%d for frequency %d\n", 88
88 N, *CTS, freq); 89 n /= div;
90 cts /= div;
91
92 /*
93 * The optimal N is 128*freq/1000. Calculate the closest larger
94 * value that doesn't truncate any bits.
95 */
96 mul = ((128*freq/1000) + (n-1))/n;
97
98 n *= mul;
99 cts *= mul;
100
101 /* Check that we are in spec (not always possible) */
102 if (n < (128*freq/1500))
103 printk(KERN_WARNING "Calculated ACR N value is too small. You may experience audio problems.\n");
104 if (n > (128*freq/300))
105 printk(KERN_WARNING "Calculated ACR N value is too large. You may experience audio problems.\n");
106
107 *N = n;
108 *CTS = cts;
109
110 DRM_DEBUG("Calculated ACR timing N=%d CTS=%d for frequency %d\n",
111 *N, *CTS, freq);
89} 112}
90 113
91struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock) 114struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock)
@@ -93,15 +116,16 @@ struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock)
93 struct radeon_hdmi_acr res; 116 struct radeon_hdmi_acr res;
94 u8 i; 117 u8 i;
95 118
96 for (i = 0; r600_hdmi_predefined_acr[i].clock != clock && 119 /* Precalculated values for common clocks */
97 r600_hdmi_predefined_acr[i].clock != 0; i++) 120 for (i = 0; i < ARRAY_SIZE(r600_hdmi_predefined_acr); i++) {
98 ; 121 if (r600_hdmi_predefined_acr[i].clock == clock)
99 res = r600_hdmi_predefined_acr[i]; 122 return r600_hdmi_predefined_acr[i];
123 }
100 124
101 /* In case some CTS are missing */ 125 /* And odd clocks get manually calculated */
102 r600_hdmi_calc_cts(clock, &res.cts_32khz, res.n_32khz, 32000); 126 r600_hdmi_calc_cts(clock, &res.cts_32khz, &res.n_32khz, 32000);
103 r600_hdmi_calc_cts(clock, &res.cts_44_1khz, res.n_44_1khz, 44100); 127 r600_hdmi_calc_cts(clock, &res.cts_44_1khz, &res.n_44_1khz, 44100);
104 r600_hdmi_calc_cts(clock, &res.cts_48khz, res.n_48khz, 48000); 128 r600_hdmi_calc_cts(clock, &res.cts_48khz, &res.n_48khz, 48000);
105 129
106 return res; 130 return res;
107} 131}
@@ -388,20 +412,30 @@ static void dce3_2_afmt_write_sad_regs(struct drm_encoder *encoder)
388 412
389 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { 413 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
390 u32 value = 0; 414 u32 value = 0;
415 u8 stereo_freqs = 0;
416 int max_channels = -1;
391 int j; 417 int j;
392 418
393 for (j = 0; j < sad_count; j++) { 419 for (j = 0; j < sad_count; j++) {
394 struct cea_sad *sad = &sads[j]; 420 struct cea_sad *sad = &sads[j];
395 421
396 if (sad->format == eld_reg_to_type[i][1]) { 422 if (sad->format == eld_reg_to_type[i][1]) {
397 value = MAX_CHANNELS(sad->channels) | 423 if (sad->channels > max_channels) {
398 DESCRIPTOR_BYTE_2(sad->byte2) | 424 value = MAX_CHANNELS(sad->channels) |
399 SUPPORTED_FREQUENCIES(sad->freq); 425 DESCRIPTOR_BYTE_2(sad->byte2) |
426 SUPPORTED_FREQUENCIES(sad->freq);
427 max_channels = sad->channels;
428 }
429
400 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) 430 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
401 value |= SUPPORTED_FREQUENCIES_STEREO(sad->freq); 431 stereo_freqs |= sad->freq;
402 break; 432 else
433 break;
403 } 434 }
404 } 435 }
436
437 value |= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs);
438
405 WREG32(eld_reg_to_type[i][0], value); 439 WREG32(eld_reg_to_type[i][0], value);
406 } 440 }
407 441
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c
index d4b91675671d..50853c0cb49d 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -2437,27 +2437,48 @@ int radeon_asic_init(struct radeon_device *rdev)
2437 } 2437 }
2438 break; 2438 break;
2439 case CHIP_BONAIRE: 2439 case CHIP_BONAIRE:
2440 case CHIP_HAWAII:
2440 rdev->asic = &ci_asic; 2441 rdev->asic = &ci_asic;
2441 rdev->num_crtc = 6; 2442 rdev->num_crtc = 6;
2442 rdev->has_uvd = true; 2443 rdev->has_uvd = true;
2443 rdev->cg_flags = 2444 if (rdev->family == CHIP_BONAIRE) {
2444 RADEON_CG_SUPPORT_GFX_MGCG | 2445 rdev->cg_flags =
2445 RADEON_CG_SUPPORT_GFX_MGLS | 2446 RADEON_CG_SUPPORT_GFX_MGCG |
2446 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2447 RADEON_CG_SUPPORT_GFX_MGLS |
2447 RADEON_CG_SUPPORT_GFX_CGLS | 2448 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2448 RADEON_CG_SUPPORT_GFX_CGTS | 2449 RADEON_CG_SUPPORT_GFX_CGLS |
2449 RADEON_CG_SUPPORT_GFX_CGTS_LS | 2450 RADEON_CG_SUPPORT_GFX_CGTS |
2450 RADEON_CG_SUPPORT_GFX_CP_LS | 2451 RADEON_CG_SUPPORT_GFX_CGTS_LS |
2451 RADEON_CG_SUPPORT_MC_LS | 2452 RADEON_CG_SUPPORT_GFX_CP_LS |
2452 RADEON_CG_SUPPORT_MC_MGCG | 2453 RADEON_CG_SUPPORT_MC_LS |
2453 RADEON_CG_SUPPORT_SDMA_MGCG | 2454 RADEON_CG_SUPPORT_MC_MGCG |
2454 RADEON_CG_SUPPORT_SDMA_LS | 2455 RADEON_CG_SUPPORT_SDMA_MGCG |
2455 RADEON_CG_SUPPORT_BIF_LS | 2456 RADEON_CG_SUPPORT_SDMA_LS |
2456 RADEON_CG_SUPPORT_VCE_MGCG | 2457 RADEON_CG_SUPPORT_BIF_LS |
2457 RADEON_CG_SUPPORT_UVD_MGCG | 2458 RADEON_CG_SUPPORT_VCE_MGCG |
2458 RADEON_CG_SUPPORT_HDP_LS | 2459 RADEON_CG_SUPPORT_UVD_MGCG |
2459 RADEON_CG_SUPPORT_HDP_MGCG; 2460 RADEON_CG_SUPPORT_HDP_LS |
2460 rdev->pg_flags = 0; 2461 RADEON_CG_SUPPORT_HDP_MGCG;
2462 rdev->pg_flags = 0;
2463 } else {
2464 rdev->cg_flags =
2465 RADEON_CG_SUPPORT_GFX_MGCG |
2466 RADEON_CG_SUPPORT_GFX_MGLS |
2467 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2468 RADEON_CG_SUPPORT_GFX_CGLS |
2469 RADEON_CG_SUPPORT_GFX_CGTS |
2470 RADEON_CG_SUPPORT_GFX_CP_LS |
2471 RADEON_CG_SUPPORT_MC_LS |
2472 RADEON_CG_SUPPORT_MC_MGCG |
2473 RADEON_CG_SUPPORT_SDMA_MGCG |
2474 RADEON_CG_SUPPORT_SDMA_LS |
2475 RADEON_CG_SUPPORT_BIF_LS |
2476 RADEON_CG_SUPPORT_VCE_MGCG |
2477 RADEON_CG_SUPPORT_UVD_MGCG |
2478 RADEON_CG_SUPPORT_HDP_LS |
2479 RADEON_CG_SUPPORT_HDP_MGCG;
2480 rdev->pg_flags = 0;
2481 }
2461 break; 2482 break;
2462 case CHIP_KAVERI: 2483 case CHIP_KAVERI:
2463 case CHIP_KABINI: 2484 case CHIP_KABINI:
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c
index f60b310b1399..20a768ac89a8 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -1728,9 +1728,7 @@ radeon_add_atom_connector(struct drm_device *dev,
1728 if (radeon_audio != 0) 1728 if (radeon_audio != 0)
1729 drm_object_attach_property(&radeon_connector->base.base, 1729 drm_object_attach_property(&radeon_connector->base.base,
1730 rdev->mode_info.audio_property, 1730 rdev->mode_info.audio_property,
1731 (radeon_audio == 1) ? 1731 RADEON_AUDIO_AUTO);
1732 RADEON_AUDIO_AUTO :
1733 RADEON_AUDIO_DISABLE);
1734 1732
1735 subpixel_order = SubPixelHorizontalRGB; 1733 subpixel_order = SubPixelHorizontalRGB;
1736 connector->interlace_allowed = true; 1734 connector->interlace_allowed = true;
@@ -1828,9 +1826,7 @@ radeon_add_atom_connector(struct drm_device *dev,
1828 if (ASIC_IS_DCE2(rdev) && (radeon_audio != 0)) { 1826 if (ASIC_IS_DCE2(rdev) && (radeon_audio != 0)) {
1829 drm_object_attach_property(&radeon_connector->base.base, 1827 drm_object_attach_property(&radeon_connector->base.base,
1830 rdev->mode_info.audio_property, 1828 rdev->mode_info.audio_property,
1831 (radeon_audio == 1) ? 1829 RADEON_AUDIO_AUTO);
1832 RADEON_AUDIO_AUTO :
1833 RADEON_AUDIO_DISABLE);
1834 } 1830 }
1835 if (ASIC_IS_AVIVO(rdev)) { 1831 if (ASIC_IS_AVIVO(rdev)) {
1836 drm_object_attach_property(&radeon_connector->base.base, 1832 drm_object_attach_property(&radeon_connector->base.base,
@@ -1880,9 +1876,7 @@ radeon_add_atom_connector(struct drm_device *dev,
1880 if (ASIC_IS_DCE2(rdev) && (radeon_audio != 0)) { 1876 if (ASIC_IS_DCE2(rdev) && (radeon_audio != 0)) {
1881 drm_object_attach_property(&radeon_connector->base.base, 1877 drm_object_attach_property(&radeon_connector->base.base,
1882 rdev->mode_info.audio_property, 1878 rdev->mode_info.audio_property,
1883 (radeon_audio == 1) ? 1879 RADEON_AUDIO_AUTO);
1884 RADEON_AUDIO_AUTO :
1885 RADEON_AUDIO_DISABLE);
1886 } 1880 }
1887 if (ASIC_IS_AVIVO(rdev)) { 1881 if (ASIC_IS_AVIVO(rdev)) {
1888 drm_object_attach_property(&radeon_connector->base.base, 1882 drm_object_attach_property(&radeon_connector->base.base,
@@ -1931,9 +1925,7 @@ radeon_add_atom_connector(struct drm_device *dev,
1931 if (ASIC_IS_DCE2(rdev) && (radeon_audio != 0)) { 1925 if (ASIC_IS_DCE2(rdev) && (radeon_audio != 0)) {
1932 drm_object_attach_property(&radeon_connector->base.base, 1926 drm_object_attach_property(&radeon_connector->base.base,
1933 rdev->mode_info.audio_property, 1927 rdev->mode_info.audio_property,
1934 (radeon_audio == 1) ? 1928 RADEON_AUDIO_AUTO);
1935 RADEON_AUDIO_AUTO :
1936 RADEON_AUDIO_DISABLE);
1937 } 1929 }
1938 if (ASIC_IS_AVIVO(rdev)) { 1930 if (ASIC_IS_AVIVO(rdev)) {
1939 drm_object_attach_property(&radeon_connector->base.base, 1931 drm_object_attach_property(&radeon_connector->base.base,
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index 61dbdd938133..b9234c43f43d 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -98,6 +98,7 @@ static const char radeon_family_name[][16] = {
98 "BONAIRE", 98 "BONAIRE",
99 "KAVERI", 99 "KAVERI",
100 "KABINI", 100 "KABINI",
101 "HAWAII",
101 "LAST", 102 "LAST",
102}; 103};
103 104
diff --git a/drivers/gpu/drm/radeon/radeon_family.h b/drivers/gpu/drm/radeon/radeon_family.h
index 3c8289083f9d..614ad549297f 100644
--- a/drivers/gpu/drm/radeon/radeon_family.h
+++ b/drivers/gpu/drm/radeon/radeon_family.h
@@ -96,6 +96,7 @@ enum radeon_family {
96 CHIP_BONAIRE, 96 CHIP_BONAIRE,
97 CHIP_KAVERI, 97 CHIP_KAVERI,
98 CHIP_KABINI, 98 CHIP_KABINI,
99 CHIP_HAWAII,
99 CHIP_LAST, 100 CHIP_LAST,
100}; 101};
101 102
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
index 7cb178a34a0f..0c7b8c66301b 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
@@ -1056,6 +1056,26 @@ static void radeon_crtc_commit(struct drm_crtc *crtc)
1056 } 1056 }
1057} 1057}
1058 1058
1059static void radeon_crtc_disable(struct drm_crtc *crtc)
1060{
1061 radeon_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1062 if (crtc->fb) {
1063 int r;
1064 struct radeon_framebuffer *radeon_fb;
1065 struct radeon_bo *rbo;
1066
1067 radeon_fb = to_radeon_framebuffer(crtc->fb);
1068 rbo = gem_to_radeon_bo(radeon_fb->obj);
1069 r = radeon_bo_reserve(rbo, false);
1070 if (unlikely(r))
1071 DRM_ERROR("failed to reserve rbo before unpin\n");
1072 else {
1073 radeon_bo_unpin(rbo);
1074 radeon_bo_unreserve(rbo);
1075 }
1076 }
1077}
1078
1059static const struct drm_crtc_helper_funcs legacy_helper_funcs = { 1079static const struct drm_crtc_helper_funcs legacy_helper_funcs = {
1060 .dpms = radeon_crtc_dpms, 1080 .dpms = radeon_crtc_dpms,
1061 .mode_fixup = radeon_crtc_mode_fixup, 1081 .mode_fixup = radeon_crtc_mode_fixup,
@@ -1065,6 +1085,7 @@ static const struct drm_crtc_helper_funcs legacy_helper_funcs = {
1065 .prepare = radeon_crtc_prepare, 1085 .prepare = radeon_crtc_prepare,
1066 .commit = radeon_crtc_commit, 1086 .commit = radeon_crtc_commit,
1067 .load_lut = radeon_crtc_load_lut, 1087 .load_lut = radeon_crtc_load_lut,
1088 .disable = radeon_crtc_disable
1068}; 1089};
1069 1090
1070 1091
diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c
index 00bdcd3e47ba..866ace070b91 100644
--- a/drivers/gpu/drm/radeon/radeon_pm.c
+++ b/drivers/gpu/drm/radeon/radeon_pm.c
@@ -1256,6 +1256,7 @@ int radeon_pm_init(struct radeon_device *rdev)
1256 case CHIP_BONAIRE: 1256 case CHIP_BONAIRE:
1257 case CHIP_KABINI: 1257 case CHIP_KABINI:
1258 case CHIP_KAVERI: 1258 case CHIP_KAVERI:
1259 case CHIP_HAWAII:
1259 /* DPM requires the RLC, RV770+ dGPU requires SMC */ 1260 /* DPM requires the RLC, RV770+ dGPU requires SMC */
1260 if (!rdev->rlc_fw) 1261 if (!rdev->rlc_fw)
1261 rdev->pm.pm_method = PM_METHOD_PROFILE; 1262 rdev->pm.pm_method = PM_METHOD_PROFILE;
diff --git a/drivers/gpu/drm/radeon/radeon_ucode.h b/drivers/gpu/drm/radeon/radeon_ucode.h
index 33858364fe89..a77cd274dfc3 100644
--- a/drivers/gpu/drm/radeon/radeon_ucode.h
+++ b/drivers/gpu/drm/radeon/radeon_ucode.h
@@ -59,6 +59,7 @@
59#define SI_MC_UCODE_SIZE 7769 59#define SI_MC_UCODE_SIZE 7769
60#define OLAND_MC_UCODE_SIZE 7863 60#define OLAND_MC_UCODE_SIZE 7863
61#define CIK_MC_UCODE_SIZE 7866 61#define CIK_MC_UCODE_SIZE 7866
62#define HAWAII_MC_UCODE_SIZE 7933
62 63
63/* SDMA */ 64/* SDMA */
64#define CIK_SDMA_UCODE_SIZE 1050 65#define CIK_SDMA_UCODE_SIZE 1050
@@ -143,4 +144,7 @@
143#define BONAIRE_SMC_UCODE_START 0x20000 144#define BONAIRE_SMC_UCODE_START 0x20000
144#define BONAIRE_SMC_UCODE_SIZE 0x1FDEC 145#define BONAIRE_SMC_UCODE_SIZE 0x1FDEC
145 146
147#define HAWAII_SMC_UCODE_START 0x20000
148#define HAWAII_SMC_UCODE_SIZE 0x1FDEC
149
146#endif 150#endif
diff --git a/drivers/gpu/drm/radeon/radeon_uvd.c b/drivers/gpu/drm/radeon/radeon_uvd.c
index ab0a17248d55..373d088bac66 100644
--- a/drivers/gpu/drm/radeon/radeon_uvd.c
+++ b/drivers/gpu/drm/radeon/radeon_uvd.c
@@ -97,6 +97,7 @@ int radeon_uvd_init(struct radeon_device *rdev)
97 case CHIP_BONAIRE: 97 case CHIP_BONAIRE:
98 case CHIP_KABINI: 98 case CHIP_KABINI:
99 case CHIP_KAVERI: 99 case CHIP_KAVERI:
100 case CHIP_HAWAII:
100 fw_name = FIRMWARE_BONAIRE; 101 fw_name = FIRMWARE_BONAIRE;
101 break; 102 break;
102 103
diff --git a/drivers/gpu/drm/radeon/rs690.c b/drivers/gpu/drm/radeon/rs690.c
index 1447d794c22a..1c560629575a 100644
--- a/drivers/gpu/drm/radeon/rs690.c
+++ b/drivers/gpu/drm/radeon/rs690.c
@@ -345,9 +345,11 @@ static void rs690_crtc_bandwidth_compute(struct radeon_device *rdev,
345 if (max_bandwidth.full > rdev->pm.sideport_bandwidth.full && 345 if (max_bandwidth.full > rdev->pm.sideport_bandwidth.full &&
346 rdev->pm.sideport_bandwidth.full) 346 rdev->pm.sideport_bandwidth.full)
347 max_bandwidth = rdev->pm.sideport_bandwidth; 347 max_bandwidth = rdev->pm.sideport_bandwidth;
348 read_delay_latency.full = dfixed_const(370 * 800 * 1000); 348 read_delay_latency.full = dfixed_const(370 * 800);
349 read_delay_latency.full = dfixed_div(read_delay_latency, 349 a.full = dfixed_const(1000);
350 rdev->pm.igp_sideport_mclk); 350 b.full = dfixed_div(rdev->pm.igp_sideport_mclk, a);
351 read_delay_latency.full = dfixed_div(read_delay_latency, b);
352 read_delay_latency.full = dfixed_mul(read_delay_latency, a);
351 } else { 353 } else {
352 if (max_bandwidth.full > rdev->pm.k8_bandwidth.full && 354 if (max_bandwidth.full > rdev->pm.k8_bandwidth.full &&
353 rdev->pm.k8_bandwidth.full) 355 rdev->pm.k8_bandwidth.full)
@@ -488,14 +490,10 @@ static void rs690_compute_mode_priority(struct radeon_device *rdev,
488 } 490 }
489 if (wm0->priority_mark.full > priority_mark02.full) 491 if (wm0->priority_mark.full > priority_mark02.full)
490 priority_mark02.full = wm0->priority_mark.full; 492 priority_mark02.full = wm0->priority_mark.full;
491 if (dfixed_trunc(priority_mark02) < 0)
492 priority_mark02.full = 0;
493 if (wm0->priority_mark_max.full > priority_mark02.full) 493 if (wm0->priority_mark_max.full > priority_mark02.full)
494 priority_mark02.full = wm0->priority_mark_max.full; 494 priority_mark02.full = wm0->priority_mark_max.full;
495 if (wm1->priority_mark.full > priority_mark12.full) 495 if (wm1->priority_mark.full > priority_mark12.full)
496 priority_mark12.full = wm1->priority_mark.full; 496 priority_mark12.full = wm1->priority_mark.full;
497 if (dfixed_trunc(priority_mark12) < 0)
498 priority_mark12.full = 0;
499 if (wm1->priority_mark_max.full > priority_mark12.full) 497 if (wm1->priority_mark_max.full > priority_mark12.full)
500 priority_mark12.full = wm1->priority_mark_max.full; 498 priority_mark12.full = wm1->priority_mark_max.full;
501 *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); 499 *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
@@ -526,8 +524,6 @@ static void rs690_compute_mode_priority(struct radeon_device *rdev,
526 } 524 }
527 if (wm0->priority_mark.full > priority_mark02.full) 525 if (wm0->priority_mark.full > priority_mark02.full)
528 priority_mark02.full = wm0->priority_mark.full; 526 priority_mark02.full = wm0->priority_mark.full;
529 if (dfixed_trunc(priority_mark02) < 0)
530 priority_mark02.full = 0;
531 if (wm0->priority_mark_max.full > priority_mark02.full) 527 if (wm0->priority_mark_max.full > priority_mark02.full)
532 priority_mark02.full = wm0->priority_mark_max.full; 528 priority_mark02.full = wm0->priority_mark_max.full;
533 *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); 529 *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
@@ -555,8 +551,6 @@ static void rs690_compute_mode_priority(struct radeon_device *rdev,
555 } 551 }
556 if (wm1->priority_mark.full > priority_mark12.full) 552 if (wm1->priority_mark.full > priority_mark12.full)
557 priority_mark12.full = wm1->priority_mark.full; 553 priority_mark12.full = wm1->priority_mark.full;
558 if (dfixed_trunc(priority_mark12) < 0)
559 priority_mark12.full = 0;
560 if (wm1->priority_mark_max.full > priority_mark12.full) 554 if (wm1->priority_mark_max.full > priority_mark12.full)
561 priority_mark12.full = wm1->priority_mark_max.full; 555 priority_mark12.full = wm1->priority_mark_max.full;
562 *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); 556 *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c
index 873eb4b193b4..5d1c316115ef 100644
--- a/drivers/gpu/drm/radeon/rv515.c
+++ b/drivers/gpu/drm/radeon/rv515.c
@@ -1155,14 +1155,10 @@ static void rv515_compute_mode_priority(struct radeon_device *rdev,
1155 } 1155 }
1156 if (wm0->priority_mark.full > priority_mark02.full) 1156 if (wm0->priority_mark.full > priority_mark02.full)
1157 priority_mark02.full = wm0->priority_mark.full; 1157 priority_mark02.full = wm0->priority_mark.full;
1158 if (dfixed_trunc(priority_mark02) < 0)
1159 priority_mark02.full = 0;
1160 if (wm0->priority_mark_max.full > priority_mark02.full) 1158 if (wm0->priority_mark_max.full > priority_mark02.full)
1161 priority_mark02.full = wm0->priority_mark_max.full; 1159 priority_mark02.full = wm0->priority_mark_max.full;
1162 if (wm1->priority_mark.full > priority_mark12.full) 1160 if (wm1->priority_mark.full > priority_mark12.full)
1163 priority_mark12.full = wm1->priority_mark.full; 1161 priority_mark12.full = wm1->priority_mark.full;
1164 if (dfixed_trunc(priority_mark12) < 0)
1165 priority_mark12.full = 0;
1166 if (wm1->priority_mark_max.full > priority_mark12.full) 1162 if (wm1->priority_mark_max.full > priority_mark12.full)
1167 priority_mark12.full = wm1->priority_mark_max.full; 1163 priority_mark12.full = wm1->priority_mark_max.full;
1168 *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); 1164 *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
@@ -1193,8 +1189,6 @@ static void rv515_compute_mode_priority(struct radeon_device *rdev,
1193 } 1189 }
1194 if (wm0->priority_mark.full > priority_mark02.full) 1190 if (wm0->priority_mark.full > priority_mark02.full)
1195 priority_mark02.full = wm0->priority_mark.full; 1191 priority_mark02.full = wm0->priority_mark.full;
1196 if (dfixed_trunc(priority_mark02) < 0)
1197 priority_mark02.full = 0;
1198 if (wm0->priority_mark_max.full > priority_mark02.full) 1192 if (wm0->priority_mark_max.full > priority_mark02.full)
1199 priority_mark02.full = wm0->priority_mark_max.full; 1193 priority_mark02.full = wm0->priority_mark_max.full;
1200 *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); 1194 *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
@@ -1222,8 +1216,6 @@ static void rv515_compute_mode_priority(struct radeon_device *rdev,
1222 } 1216 }
1223 if (wm1->priority_mark.full > priority_mark12.full) 1217 if (wm1->priority_mark.full > priority_mark12.full)
1224 priority_mark12.full = wm1->priority_mark.full; 1218 priority_mark12.full = wm1->priority_mark.full;
1225 if (dfixed_trunc(priority_mark12) < 0)
1226 priority_mark12.full = 0;
1227 if (wm1->priority_mark_max.full > priority_mark12.full) 1219 if (wm1->priority_mark_max.full > priority_mark12.full)
1228 priority_mark12.full = wm1->priority_mark_max.full; 1220 priority_mark12.full = wm1->priority_mark_max.full;
1229 *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); 1221 *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
diff --git a/include/drm/drm_pciids.h b/include/drm/drm_pciids.h
index 3d79e513c0b3..87578c109e48 100644
--- a/include/drm/drm_pciids.h
+++ b/include/drm/drm_pciids.h
@@ -261,6 +261,18 @@
261 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI|RADEON_NEW_MEMMAP}, \ 261 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI|RADEON_NEW_MEMMAP}, \
262 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI|RADEON_NEW_MEMMAP}, \ 262 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI|RADEON_NEW_MEMMAP}, \
263 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI|RADEON_NEW_MEMMAP}, \ 263 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI|RADEON_NEW_MEMMAP}, \
264 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII|RADEON_NEW_MEMMAP}, \
265 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII|RADEON_NEW_MEMMAP}, \
266 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII|RADEON_NEW_MEMMAP}, \
267 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII|RADEON_NEW_MEMMAP}, \
268 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII|RADEON_NEW_MEMMAP}, \
269 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII|RADEON_NEW_MEMMAP}, \
270 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII|RADEON_NEW_MEMMAP}, \
271 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII|RADEON_NEW_MEMMAP}, \
272 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII|RADEON_NEW_MEMMAP}, \
273 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII|RADEON_NEW_MEMMAP}, \
274 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII|RADEON_NEW_MEMMAP}, \
275 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII|RADEON_NEW_MEMMAP}, \
264 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ 276 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
265 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ 277 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
266 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ 278 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-26 15:58:46 +0000