diff options
author | Dave Airlie <airlied@redhat.com> | 2013-08-22 10:38:28 +1000 |
---|---|---|
committer | Dave Airlie <airlied@redhat.com> | 2013-08-22 10:38:28 +1000 |
commit | 291d284c6004e3a63d0c2f6c31570ab2126843a8 (patch) | |
tree | fb38da263bfd8d76ffe440f4ac9549ee53acd893 | |
parent | d0b2c5334f41bdd18adaa3fbc1f7b5f1daab7eac (diff) | |
parent | 75346fe9bc4c9b366c760200a665a2c55b789389 (diff) |
Merge branch 'gma500-next' of git://github.com/patjak/drm-gma500 into drm-next
Here's some gma500 unifying and cleanups for drm-next. There is more stuff in
the pipe for 3.12 but I'd like to get these out of the way first.
* 'gma500-next' of git://github.com/patjak/drm-gma500: (35 commits)
drm/gma500/cdv: Add and hook up chip op for disabling sr
drm/gma500/cdv: Add and hook up chip op for watermarks
drm/gma500: Rename psb_intel_encoder to gma_encoder
drm/gma500: Rename psb_intel_connector to gma_connector
drm/gma500: Rename psb_intel_crtc to gma_crtc
drm/gma500/cdv: Convert to generic set_config()
drm/gma500/psb: Convert to generic set_config()
drm/gma500: Add generic set_config() function
drm/gma500/cdv: Convert to generic save/restore
drm/gma500/psb: Convert to generic save/restore
drm/gma500: Add generic crtc save/restore funcs
drm/gma500: Convert to generic encoder funcs
drm/gma500: Add generic encoder functions
drm/gma500/psb: Convert to generic cursor funcs
drm/gma500/cdv: Convert to generic cursor funcs
drm/gma500: Add generic cursor functions
drm/gma500/psb: Convert to generic crtc->destroy
drm/gma500/mdfld: Use identical generic crtc funcs
drm/gma500/oak: Use identical generic crtc funcs
drm/gma500/psb: Convert to gma_crtc_dpms()
...
26 files changed, 1446 insertions, 2168 deletions
diff --git a/drivers/gpu/drm/gma500/Makefile b/drivers/gpu/drm/gma500/Makefile index 7a2d40a5c1e1..e9064dd9045d 100644 --- a/drivers/gpu/drm/gma500/Makefile +++ b/drivers/gpu/drm/gma500/Makefile | |||
@@ -15,6 +15,7 @@ gma500_gfx-y += \ | |||
15 | mmu.o \ | 15 | mmu.o \ |
16 | power.o \ | 16 | power.o \ |
17 | psb_drv.o \ | 17 | psb_drv.o \ |
18 | gma_display.o \ | ||
18 | psb_intel_display.o \ | 19 | psb_intel_display.o \ |
19 | psb_intel_lvds.o \ | 20 | psb_intel_lvds.o \ |
20 | psb_intel_modes.o \ | 21 | psb_intel_modes.o \ |
diff --git a/drivers/gpu/drm/gma500/cdv_device.c b/drivers/gpu/drm/gma500/cdv_device.c index 23e14e93991f..162f686c532d 100644 --- a/drivers/gpu/drm/gma500/cdv_device.c +++ b/drivers/gpu/drm/gma500/cdv_device.c | |||
@@ -641,6 +641,7 @@ const struct psb_ops cdv_chip_ops = { | |||
641 | 641 | ||
642 | .crtc_helper = &cdv_intel_helper_funcs, | 642 | .crtc_helper = &cdv_intel_helper_funcs, |
643 | .crtc_funcs = &cdv_intel_crtc_funcs, | 643 | .crtc_funcs = &cdv_intel_crtc_funcs, |
644 | .clock_funcs = &cdv_clock_funcs, | ||
644 | 645 | ||
645 | .output_init = cdv_output_init, | 646 | .output_init = cdv_output_init, |
646 | .hotplug = cdv_hotplug_event, | 647 | .hotplug = cdv_hotplug_event, |
@@ -655,4 +656,6 @@ const struct psb_ops cdv_chip_ops = { | |||
655 | .restore_regs = cdv_restore_display_registers, | 656 | .restore_regs = cdv_restore_display_registers, |
656 | .power_down = cdv_power_down, | 657 | .power_down = cdv_power_down, |
657 | .power_up = cdv_power_up, | 658 | .power_up = cdv_power_up, |
659 | .update_wm = cdv_update_wm, | ||
660 | .disable_sr = cdv_disable_sr, | ||
658 | }; | 661 | }; |
diff --git a/drivers/gpu/drm/gma500/cdv_device.h b/drivers/gpu/drm/gma500/cdv_device.h index 9561e17621b3..705c11d47d45 100644 --- a/drivers/gpu/drm/gma500/cdv_device.h +++ b/drivers/gpu/drm/gma500/cdv_device.h | |||
@@ -17,6 +17,7 @@ | |||
17 | 17 | ||
18 | extern const struct drm_crtc_helper_funcs cdv_intel_helper_funcs; | 18 | extern const struct drm_crtc_helper_funcs cdv_intel_helper_funcs; |
19 | extern const struct drm_crtc_funcs cdv_intel_crtc_funcs; | 19 | extern const struct drm_crtc_funcs cdv_intel_crtc_funcs; |
20 | extern const struct gma_clock_funcs cdv_clock_funcs; | ||
20 | extern void cdv_intel_crt_init(struct drm_device *dev, | 21 | extern void cdv_intel_crt_init(struct drm_device *dev, |
21 | struct psb_intel_mode_device *mode_dev); | 22 | struct psb_intel_mode_device *mode_dev); |
22 | extern void cdv_intel_lvds_init(struct drm_device *dev, | 23 | extern void cdv_intel_lvds_init(struct drm_device *dev, |
@@ -25,12 +26,5 @@ extern void cdv_hdmi_init(struct drm_device *dev, struct psb_intel_mode_device * | |||
25 | int reg); | 26 | int reg); |
26 | extern struct drm_display_mode *cdv_intel_crtc_mode_get(struct drm_device *dev, | 27 | extern struct drm_display_mode *cdv_intel_crtc_mode_get(struct drm_device *dev, |
27 | struct drm_crtc *crtc); | 28 | struct drm_crtc *crtc); |
28 | 29 | extern void cdv_update_wm(struct drm_device *dev, struct drm_crtc *crtc); | |
29 | static inline void cdv_intel_wait_for_vblank(struct drm_device *dev) | 30 | extern void cdv_disable_sr(struct drm_device *dev); |
30 | { | ||
31 | /* Wait for 20ms, i.e. one cycle at 50hz. */ | ||
32 | /* FIXME: msleep ?? */ | ||
33 | mdelay(20); | ||
34 | } | ||
35 | |||
36 | |||
diff --git a/drivers/gpu/drm/gma500/cdv_intel_crt.c b/drivers/gpu/drm/gma500/cdv_intel_crt.c index 7b8386fc3024..661af492173d 100644 --- a/drivers/gpu/drm/gma500/cdv_intel_crt.c +++ b/drivers/gpu/drm/gma500/cdv_intel_crt.c | |||
@@ -95,13 +95,12 @@ static void cdv_intel_crt_mode_set(struct drm_encoder *encoder, | |||
95 | 95 | ||
96 | struct drm_device *dev = encoder->dev; | 96 | struct drm_device *dev = encoder->dev; |
97 | struct drm_crtc *crtc = encoder->crtc; | 97 | struct drm_crtc *crtc = encoder->crtc; |
98 | struct psb_intel_crtc *psb_intel_crtc = | 98 | struct gma_crtc *gma_crtc = to_gma_crtc(crtc); |
99 | to_psb_intel_crtc(crtc); | ||
100 | int dpll_md_reg; | 99 | int dpll_md_reg; |
101 | u32 adpa, dpll_md; | 100 | u32 adpa, dpll_md; |
102 | u32 adpa_reg; | 101 | u32 adpa_reg; |
103 | 102 | ||
104 | if (psb_intel_crtc->pipe == 0) | 103 | if (gma_crtc->pipe == 0) |
105 | dpll_md_reg = DPLL_A_MD; | 104 | dpll_md_reg = DPLL_A_MD; |
106 | else | 105 | else |
107 | dpll_md_reg = DPLL_B_MD; | 106 | dpll_md_reg = DPLL_B_MD; |
@@ -124,7 +123,7 @@ static void cdv_intel_crt_mode_set(struct drm_encoder *encoder, | |||
124 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | 123 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
125 | adpa |= ADPA_VSYNC_ACTIVE_HIGH; | 124 | adpa |= ADPA_VSYNC_ACTIVE_HIGH; |
126 | 125 | ||
127 | if (psb_intel_crtc->pipe == 0) | 126 | if (gma_crtc->pipe == 0) |
128 | adpa |= ADPA_PIPE_A_SELECT; | 127 | adpa |= ADPA_PIPE_A_SELECT; |
129 | else | 128 | else |
130 | adpa |= ADPA_PIPE_B_SELECT; | 129 | adpa |= ADPA_PIPE_B_SELECT; |
@@ -197,10 +196,9 @@ static enum drm_connector_status cdv_intel_crt_detect( | |||
197 | 196 | ||
198 | static void cdv_intel_crt_destroy(struct drm_connector *connector) | 197 | static void cdv_intel_crt_destroy(struct drm_connector *connector) |
199 | { | 198 | { |
200 | struct psb_intel_encoder *psb_intel_encoder = | 199 | struct gma_encoder *gma_encoder = gma_attached_encoder(connector); |
201 | psb_intel_attached_encoder(connector); | ||
202 | 200 | ||
203 | psb_intel_i2c_destroy(psb_intel_encoder->ddc_bus); | 201 | psb_intel_i2c_destroy(gma_encoder->ddc_bus); |
204 | drm_sysfs_connector_remove(connector); | 202 | drm_sysfs_connector_remove(connector); |
205 | drm_connector_cleanup(connector); | 203 | drm_connector_cleanup(connector); |
206 | kfree(connector); | 204 | kfree(connector); |
@@ -208,9 +206,9 @@ static void cdv_intel_crt_destroy(struct drm_connector *connector) | |||
208 | 206 | ||
209 | static int cdv_intel_crt_get_modes(struct drm_connector *connector) | 207 | static int cdv_intel_crt_get_modes(struct drm_connector *connector) |
210 | { | 208 | { |
211 | struct psb_intel_encoder *psb_intel_encoder = | 209 | struct gma_encoder *gma_encoder = gma_attached_encoder(connector); |
212 | psb_intel_attached_encoder(connector); | 210 | return psb_intel_ddc_get_modes(connector, |
213 | return psb_intel_ddc_get_modes(connector, &psb_intel_encoder->ddc_bus->adapter); | 211 | &gma_encoder->ddc_bus->adapter); |
214 | } | 212 | } |
215 | 213 | ||
216 | static int cdv_intel_crt_set_property(struct drm_connector *connector, | 214 | static int cdv_intel_crt_set_property(struct drm_connector *connector, |
@@ -227,8 +225,8 @@ static int cdv_intel_crt_set_property(struct drm_connector *connector, | |||
227 | static const struct drm_encoder_helper_funcs cdv_intel_crt_helper_funcs = { | 225 | static const struct drm_encoder_helper_funcs cdv_intel_crt_helper_funcs = { |
228 | .dpms = cdv_intel_crt_dpms, | 226 | .dpms = cdv_intel_crt_dpms, |
229 | .mode_fixup = cdv_intel_crt_mode_fixup, | 227 | .mode_fixup = cdv_intel_crt_mode_fixup, |
230 | .prepare = psb_intel_encoder_prepare, | 228 | .prepare = gma_encoder_prepare, |
231 | .commit = psb_intel_encoder_commit, | 229 | .commit = gma_encoder_commit, |
232 | .mode_set = cdv_intel_crt_mode_set, | 230 | .mode_set = cdv_intel_crt_mode_set, |
233 | }; | 231 | }; |
234 | 232 | ||
@@ -244,7 +242,7 @@ static const struct drm_connector_helper_funcs | |||
244 | cdv_intel_crt_connector_helper_funcs = { | 242 | cdv_intel_crt_connector_helper_funcs = { |
245 | .mode_valid = cdv_intel_crt_mode_valid, | 243 | .mode_valid = cdv_intel_crt_mode_valid, |
246 | .get_modes = cdv_intel_crt_get_modes, | 244 | .get_modes = cdv_intel_crt_get_modes, |
247 | .best_encoder = psb_intel_best_encoder, | 245 | .best_encoder = gma_best_encoder, |
248 | }; | 246 | }; |
249 | 247 | ||
250 | static void cdv_intel_crt_enc_destroy(struct drm_encoder *encoder) | 248 | static void cdv_intel_crt_enc_destroy(struct drm_encoder *encoder) |
@@ -260,32 +258,31 @@ void cdv_intel_crt_init(struct drm_device *dev, | |||
260 | struct psb_intel_mode_device *mode_dev) | 258 | struct psb_intel_mode_device *mode_dev) |
261 | { | 259 | { |
262 | 260 | ||
263 | struct psb_intel_connector *psb_intel_connector; | 261 | struct gma_connector *gma_connector; |
264 | struct psb_intel_encoder *psb_intel_encoder; | 262 | struct gma_encoder *gma_encoder; |
265 | struct drm_connector *connector; | 263 | struct drm_connector *connector; |
266 | struct drm_encoder *encoder; | 264 | struct drm_encoder *encoder; |
267 | 265 | ||
268 | u32 i2c_reg; | 266 | u32 i2c_reg; |
269 | 267 | ||
270 | psb_intel_encoder = kzalloc(sizeof(struct psb_intel_encoder), GFP_KERNEL); | 268 | gma_encoder = kzalloc(sizeof(struct gma_encoder), GFP_KERNEL); |
271 | if (!psb_intel_encoder) | 269 | if (!gma_encoder) |
272 | return; | 270 | return; |
273 | 271 | ||
274 | psb_intel_connector = kzalloc(sizeof(struct psb_intel_connector), GFP_KERNEL); | 272 | gma_connector = kzalloc(sizeof(struct gma_connector), GFP_KERNEL); |
275 | if (!psb_intel_connector) | 273 | if (!gma_connector) |
276 | goto failed_connector; | 274 | goto failed_connector; |
277 | 275 | ||
278 | connector = &psb_intel_connector->base; | 276 | connector = &gma_connector->base; |
279 | connector->polled = DRM_CONNECTOR_POLL_HPD; | 277 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
280 | drm_connector_init(dev, connector, | 278 | drm_connector_init(dev, connector, |
281 | &cdv_intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA); | 279 | &cdv_intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA); |
282 | 280 | ||
283 | encoder = &psb_intel_encoder->base; | 281 | encoder = &gma_encoder->base; |
284 | drm_encoder_init(dev, encoder, | 282 | drm_encoder_init(dev, encoder, |
285 | &cdv_intel_crt_enc_funcs, DRM_MODE_ENCODER_DAC); | 283 | &cdv_intel_crt_enc_funcs, DRM_MODE_ENCODER_DAC); |
286 | 284 | ||
287 | psb_intel_connector_attach_encoder(psb_intel_connector, | 285 | gma_connector_attach_encoder(gma_connector, gma_encoder); |
288 | psb_intel_encoder); | ||
289 | 286 | ||
290 | /* Set up the DDC bus. */ | 287 | /* Set up the DDC bus. */ |
291 | i2c_reg = GPIOA; | 288 | i2c_reg = GPIOA; |
@@ -294,15 +291,15 @@ void cdv_intel_crt_init(struct drm_device *dev, | |||
294 | if (dev_priv->crt_ddc_bus != 0) | 291 | if (dev_priv->crt_ddc_bus != 0) |
295 | i2c_reg = dev_priv->crt_ddc_bus; | 292 | i2c_reg = dev_priv->crt_ddc_bus; |
296 | }*/ | 293 | }*/ |
297 | psb_intel_encoder->ddc_bus = psb_intel_i2c_create(dev, | 294 | gma_encoder->ddc_bus = psb_intel_i2c_create(dev, |
298 | i2c_reg, "CRTDDC_A"); | 295 | i2c_reg, "CRTDDC_A"); |
299 | if (!psb_intel_encoder->ddc_bus) { | 296 | if (!gma_encoder->ddc_bus) { |
300 | dev_printk(KERN_ERR, &dev->pdev->dev, "DDC bus registration " | 297 | dev_printk(KERN_ERR, &dev->pdev->dev, "DDC bus registration " |
301 | "failed.\n"); | 298 | "failed.\n"); |
302 | goto failed_ddc; | 299 | goto failed_ddc; |
303 | } | 300 | } |
304 | 301 | ||
305 | psb_intel_encoder->type = INTEL_OUTPUT_ANALOG; | 302 | gma_encoder->type = INTEL_OUTPUT_ANALOG; |
306 | /* | 303 | /* |
307 | psb_intel_output->clone_mask = (1 << INTEL_ANALOG_CLONE_BIT); | 304 | psb_intel_output->clone_mask = (1 << INTEL_ANALOG_CLONE_BIT); |
308 | psb_intel_output->crtc_mask = (1 << 0) | (1 << 1); | 305 | psb_intel_output->crtc_mask = (1 << 0) | (1 << 1); |
@@ -318,10 +315,10 @@ void cdv_intel_crt_init(struct drm_device *dev, | |||
318 | 315 | ||
319 | return; | 316 | return; |
320 | failed_ddc: | 317 | failed_ddc: |
321 | drm_encoder_cleanup(&psb_intel_encoder->base); | 318 | drm_encoder_cleanup(&gma_encoder->base); |
322 | drm_connector_cleanup(&psb_intel_connector->base); | 319 | drm_connector_cleanup(&gma_connector->base); |
323 | kfree(psb_intel_connector); | 320 | kfree(gma_connector); |
324 | failed_connector: | 321 | failed_connector: |
325 | kfree(psb_intel_encoder); | 322 | kfree(gma_encoder); |
326 | return; | 323 | return; |
327 | } | 324 | } |
diff --git a/drivers/gpu/drm/gma500/cdv_intel_display.c b/drivers/gpu/drm/gma500/cdv_intel_display.c index 82430ad8ba62..8fbfa06da62d 100644 --- a/drivers/gpu/drm/gma500/cdv_intel_display.c +++ b/drivers/gpu/drm/gma500/cdv_intel_display.c | |||
@@ -19,54 +19,20 @@ | |||
19 | */ | 19 | */ |
20 | 20 | ||
21 | #include <linux/i2c.h> | 21 | #include <linux/i2c.h> |
22 | #include <linux/pm_runtime.h> | ||
23 | 22 | ||
24 | #include <drm/drmP.h> | 23 | #include <drm/drmP.h> |
25 | #include "framebuffer.h" | 24 | #include "framebuffer.h" |
26 | #include "psb_drv.h" | 25 | #include "psb_drv.h" |
27 | #include "psb_intel_drv.h" | 26 | #include "psb_intel_drv.h" |
28 | #include "psb_intel_reg.h" | 27 | #include "psb_intel_reg.h" |
29 | #include "psb_intel_display.h" | 28 | #include "gma_display.h" |
30 | #include "power.h" | 29 | #include "power.h" |
31 | #include "cdv_device.h" | 30 | #include "cdv_device.h" |
32 | 31 | ||
32 | static bool cdv_intel_find_dp_pll(const struct gma_limit_t *limit, | ||
33 | struct drm_crtc *crtc, int target, | ||
34 | int refclk, struct gma_clock_t *best_clock); | ||
33 | 35 | ||
34 | struct cdv_intel_range_t { | ||
35 | int min, max; | ||
36 | }; | ||
37 | |||
38 | struct cdv_intel_p2_t { | ||
39 | int dot_limit; | ||
40 | int p2_slow, p2_fast; | ||
41 | }; | ||
42 | |||
43 | struct cdv_intel_clock_t { | ||
44 | /* given values */ | ||
45 | int n; | ||
46 | int m1, m2; | ||
47 | int p1, p2; | ||
48 | /* derived values */ | ||
49 | int dot; | ||
50 | int vco; | ||
51 | int m; | ||
52 | int p; | ||
53 | }; | ||
54 | |||
55 | #define INTEL_P2_NUM 2 | ||
56 | |||
57 | struct cdv_intel_limit_t { | ||
58 | struct cdv_intel_range_t dot, vco, n, m, m1, m2, p, p1; | ||
59 | struct cdv_intel_p2_t p2; | ||
60 | bool (*find_pll)(const struct cdv_intel_limit_t *, struct drm_crtc *, | ||
61 | int, int, struct cdv_intel_clock_t *); | ||
62 | }; | ||
63 | |||
64 | static bool cdv_intel_find_best_PLL(const struct cdv_intel_limit_t *limit, | ||
65 | struct drm_crtc *crtc, int target, int refclk, | ||
66 | struct cdv_intel_clock_t *best_clock); | ||
67 | static bool cdv_intel_find_dp_pll(const struct cdv_intel_limit_t *limit, struct drm_crtc *crtc, int target, | ||
68 | int refclk, | ||
69 | struct cdv_intel_clock_t *best_clock); | ||
70 | 36 | ||
71 | #define CDV_LIMIT_SINGLE_LVDS_96 0 | 37 | #define CDV_LIMIT_SINGLE_LVDS_96 0 |
72 | #define CDV_LIMIT_SINGLE_LVDS_100 1 | 38 | #define CDV_LIMIT_SINGLE_LVDS_100 1 |
@@ -75,7 +41,7 @@ static bool cdv_intel_find_dp_pll(const struct cdv_intel_limit_t *limit, struct | |||
75 | #define CDV_LIMIT_DP_27 4 | 41 | #define CDV_LIMIT_DP_27 4 |
76 | #define CDV_LIMIT_DP_100 5 | 42 | #define CDV_LIMIT_DP_100 5 |
77 | 43 | ||
78 | static const struct cdv_intel_limit_t cdv_intel_limits[] = { | 44 | static const struct gma_limit_t cdv_intel_limits[] = { |
79 | { /* CDV_SINGLE_LVDS_96MHz */ | 45 | { /* CDV_SINGLE_LVDS_96MHz */ |
80 | .dot = {.min = 20000, .max = 115500}, | 46 | .dot = {.min = 20000, .max = 115500}, |
81 | .vco = {.min = 1800000, .max = 3600000}, | 47 | .vco = {.min = 1800000, .max = 3600000}, |
@@ -85,9 +51,8 @@ static const struct cdv_intel_limit_t cdv_intel_limits[] = { | |||
85 | .m2 = {.min = 58, .max = 158}, | 51 | .m2 = {.min = 58, .max = 158}, |
86 | .p = {.min = 28, .max = 140}, | 52 | .p = {.min = 28, .max = 140}, |
87 | .p1 = {.min = 2, .max = 10}, | 53 | .p1 = {.min = 2, .max = 10}, |
88 | .p2 = {.dot_limit = 200000, | 54 | .p2 = {.dot_limit = 200000, .p2_slow = 14, .p2_fast = 14}, |
89 | .p2_slow = 14, .p2_fast = 14}, | 55 | .find_pll = gma_find_best_pll, |
90 | .find_pll = cdv_intel_find_best_PLL, | ||
91 | }, | 56 | }, |
92 | { /* CDV_SINGLE_LVDS_100MHz */ | 57 | { /* CDV_SINGLE_LVDS_100MHz */ |
93 | .dot = {.min = 20000, .max = 115500}, | 58 | .dot = {.min = 20000, .max = 115500}, |
@@ -102,7 +67,7 @@ static const struct cdv_intel_limit_t cdv_intel_limits[] = { | |||
102 | * is 80-224Mhz. Prefer single channel as much as possible. | 67 | * is 80-224Mhz. Prefer single channel as much as possible. |
103 | */ | 68 | */ |
104 | .p2 = {.dot_limit = 200000, .p2_slow = 14, .p2_fast = 14}, | 69 | .p2 = {.dot_limit = 200000, .p2_slow = 14, .p2_fast = 14}, |
105 | .find_pll = cdv_intel_find_best_PLL, | 70 | .find_pll = gma_find_best_pll, |
106 | }, | 71 | }, |
107 | { /* CDV_DAC_HDMI_27MHz */ | 72 | { /* CDV_DAC_HDMI_27MHz */ |
108 | .dot = {.min = 20000, .max = 400000}, | 73 | .dot = {.min = 20000, .max = 400000}, |
@@ -114,7 +79,7 @@ static const struct cdv_intel_limit_t cdv_intel_limits[] = { | |||
114 | .p = {.min = 5, .max = 90}, | 79 | .p = {.min = 5, .max = 90}, |
115 | .p1 = {.min = 1, .max = 9}, | 80 | .p1 = {.min = 1, .max = 9}, |
116 | .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 5}, | 81 | .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 5}, |
117 | .find_pll = cdv_intel_find_best_PLL, | 82 | .find_pll = gma_find_best_pll, |
118 | }, | 83 | }, |
119 | { /* CDV_DAC_HDMI_96MHz */ | 84 | { /* CDV_DAC_HDMI_96MHz */ |
120 | .dot = {.min = 20000, .max = 400000}, | 85 | .dot = {.min = 20000, .max = 400000}, |
@@ -126,7 +91,7 @@ static const struct cdv_intel_limit_t cdv_intel_limits[] = { | |||
126 | .p = {.min = 5, .max = 100}, | 91 | .p = {.min = 5, .max = 100}, |
127 | .p1 = {.min = 1, .max = 10}, | 92 | .p1 = {.min = 1, .max = 10}, |
128 | .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 5}, | 93 | .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 5}, |
129 | .find_pll = cdv_intel_find_best_PLL, | 94 | .find_pll = gma_find_best_pll, |
130 | }, | 95 | }, |
131 | { /* CDV_DP_27MHz */ | 96 | { /* CDV_DP_27MHz */ |
132 | .dot = {.min = 160000, .max = 272000}, | 97 | .dot = {.min = 160000, .max = 272000}, |
@@ -255,10 +220,10 @@ void cdv_sb_reset(struct drm_device *dev) | |||
255 | */ | 220 | */ |
256 | static int | 221 | static int |
257 | cdv_dpll_set_clock_cdv(struct drm_device *dev, struct drm_crtc *crtc, | 222 | cdv_dpll_set_clock_cdv(struct drm_device *dev, struct drm_crtc *crtc, |
258 | struct cdv_intel_clock_t *clock, bool is_lvds, u32 ddi_select) | 223 | struct gma_clock_t *clock, bool is_lvds, u32 ddi_select) |
259 | { | 224 | { |
260 | struct psb_intel_crtc *psb_crtc = to_psb_intel_crtc(crtc); | 225 | struct gma_crtc *gma_crtc = to_gma_crtc(crtc); |
261 | int pipe = psb_crtc->pipe; | 226 | int pipe = gma_crtc->pipe; |
262 | u32 m, n_vco, p; | 227 | u32 m, n_vco, p; |
263 | int ret = 0; | 228 | int ret = 0; |
264 | int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; | 229 | int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; |
@@ -405,31 +370,11 @@ cdv_dpll_set_clock_cdv(struct drm_device *dev, struct drm_crtc *crtc, | |||
405 | return 0; | 370 | return 0; |
406 | } | 371 | } |
407 | 372 | ||
408 | /* | 373 | static const struct gma_limit_t *cdv_intel_limit(struct drm_crtc *crtc, |
409 | * Returns whether any encoder on the specified pipe is of the specified type | 374 | int refclk) |
410 | */ | ||
411 | static bool cdv_intel_pipe_has_type(struct drm_crtc *crtc, int type) | ||
412 | { | ||
413 | struct drm_device *dev = crtc->dev; | ||
414 | struct drm_mode_config *mode_config = &dev->mode_config; | ||
415 | struct drm_connector *l_entry; | ||
416 | |||
417 | list_for_each_entry(l_entry, &mode_config->connector_list, head) { | ||
418 | if (l_entry->encoder && l_entry->encoder->crtc == crtc) { | ||
419 | struct psb_intel_encoder *psb_intel_encoder = | ||
420 | psb_intel_attached_encoder(l_entry); | ||
421 | if (psb_intel_encoder->type == type) | ||
422 | return true; | ||
423 | } | ||
424 | } | ||
425 | return false; | ||
426 | } | ||
427 | |||
428 | static const struct cdv_intel_limit_t *cdv_intel_limit(struct drm_crtc *crtc, | ||
429 | int refclk) | ||
430 | { | 375 | { |
431 | const struct cdv_intel_limit_t *limit; | 376 | const struct gma_limit_t *limit; |
432 | if (cdv_intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | 377 | if (gma_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
433 | /* | 378 | /* |
434 | * Now only single-channel LVDS is supported on CDV. If it is | 379 | * Now only single-channel LVDS is supported on CDV. If it is |
435 | * incorrect, please add the dual-channel LVDS. | 380 | * incorrect, please add the dual-channel LVDS. |
@@ -438,8 +383,8 @@ static const struct cdv_intel_limit_t *cdv_intel_limit(struct drm_crtc *crtc, | |||
438 | limit = &cdv_intel_limits[CDV_LIMIT_SINGLE_LVDS_96]; | 383 | limit = &cdv_intel_limits[CDV_LIMIT_SINGLE_LVDS_96]; |
439 | else | 384 | else |
440 | limit = &cdv_intel_limits[CDV_LIMIT_SINGLE_LVDS_100]; | 385 | limit = &cdv_intel_limits[CDV_LIMIT_SINGLE_LVDS_100]; |
441 | } else if (psb_intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || | 386 | } else if (gma_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
442 | psb_intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) { | 387 | gma_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) { |
443 | if (refclk == 27000) | 388 | if (refclk == 27000) |
444 | limit = &cdv_intel_limits[CDV_LIMIT_DP_27]; | 389 | limit = &cdv_intel_limits[CDV_LIMIT_DP_27]; |
445 | else | 390 | else |
@@ -454,8 +399,7 @@ static const struct cdv_intel_limit_t *cdv_intel_limit(struct drm_crtc *crtc, | |||
454 | } | 399 | } |
455 | 400 | ||
456 | /* m1 is reserved as 0 in CDV, n is a ring counter */ | 401 | /* m1 is reserved as 0 in CDV, n is a ring counter */ |
457 | static void cdv_intel_clock(struct drm_device *dev, | 402 | static void cdv_intel_clock(int refclk, struct gma_clock_t *clock) |
458 | int refclk, struct cdv_intel_clock_t *clock) | ||
459 | { | 403 | { |
460 | clock->m = clock->m2 + 2; | 404 | clock->m = clock->m2 + 2; |
461 | clock->p = clock->p1 * clock->p2; | 405 | clock->p = clock->p1 * clock->p2; |
@@ -463,93 +407,12 @@ static void cdv_intel_clock(struct drm_device *dev, | |||
463 | clock->dot = clock->vco / clock->p; | 407 | clock->dot = clock->vco / clock->p; |
464 | } | 408 | } |
465 | 409 | ||
466 | 410 | static bool cdv_intel_find_dp_pll(const struct gma_limit_t *limit, | |
467 | #define INTELPllInvalid(s) { /* ErrorF (s) */; return false; } | 411 | struct drm_crtc *crtc, int target, |
468 | static bool cdv_intel_PLL_is_valid(struct drm_crtc *crtc, | 412 | int refclk, |
469 | const struct cdv_intel_limit_t *limit, | 413 | struct gma_clock_t *best_clock) |
470 | struct cdv_intel_clock_t *clock) | ||
471 | { | ||
472 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) | ||
473 | INTELPllInvalid("p1 out of range\n"); | ||
474 | if (clock->p < limit->p.min || limit->p.max < clock->p) | ||
475 | INTELPllInvalid("p out of range\n"); | ||
476 | /* unnecessary to check the range of m(m1/M2)/n again */ | ||
477 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) | ||
478 | INTELPllInvalid("vco out of range\n"); | ||
479 | /* XXX: We may need to be checking "Dot clock" | ||
480 | * depending on the multiplier, connector, etc., | ||
481 | * rather than just a single range. | ||
482 | */ | ||
483 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | ||
484 | INTELPllInvalid("dot out of range\n"); | ||
485 | |||
486 | return true; | ||
487 | } | ||
488 | |||
489 | static bool cdv_intel_find_best_PLL(const struct cdv_intel_limit_t *limit, | ||
490 | struct drm_crtc *crtc, int target, int refclk, | ||
491 | struct cdv_intel_clock_t *best_clock) | ||
492 | { | 414 | { |
493 | struct drm_device *dev = crtc->dev; | 415 | struct gma_clock_t clock; |
494 | struct cdv_intel_clock_t clock; | ||
495 | int err = target; | ||
496 | |||
497 | |||
498 | if (cdv_intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && | ||
499 | (REG_READ(LVDS) & LVDS_PORT_EN) != 0) { | ||
500 | /* | ||
501 | * For LVDS, if the panel is on, just rely on its current | ||
502 | * settings for dual-channel. We haven't figured out how to | ||
503 | * reliably set up different single/dual channel state, if we | ||
504 | * even can. | ||
505 | */ | ||
506 | if ((REG_READ(LVDS) & LVDS_CLKB_POWER_MASK) == | ||
507 | LVDS_CLKB_POWER_UP) | ||
508 | clock.p2 = limit->p2.p2_fast; | ||
509 | else | ||
510 | clock.p2 = limit->p2.p2_slow; | ||
511 | } else { | ||
512 | if (target < limit->p2.dot_limit) | ||
513 | clock.p2 = limit->p2.p2_slow; | ||
514 | else | ||
515 | clock.p2 = limit->p2.p2_fast; | ||
516 | } | ||
517 | |||
518 | memset(best_clock, 0, sizeof(*best_clock)); | ||
519 | clock.m1 = 0; | ||
520 | /* m1 is reserved as 0 in CDV, n is a ring counter. | ||
521 | So skip the m1 loop */ | ||
522 | for (clock.n = limit->n.min; clock.n <= limit->n.max; clock.n++) { | ||
523 | for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; | ||
524 | clock.m2++) { | ||
525 | for (clock.p1 = limit->p1.min; | ||
526 | clock.p1 <= limit->p1.max; | ||
527 | clock.p1++) { | ||
528 | int this_err; | ||
529 | |||
530 | cdv_intel_clock(dev, refclk, &clock); | ||
531 | |||
532 | if (!cdv_intel_PLL_is_valid(crtc, | ||
533 | limit, &clock)) | ||
534 | continue; | ||
535 | |||
536 | this_err = abs(clock.dot - target); | ||
537 | if (this_err < err) { | ||
538 | *best_clock = clock; | ||
539 | err = this_err; | ||
540 | } | ||
541 | } | ||
542 | } | ||
543 | } | ||
544 | |||
545 | return err != target; | ||
546 | } | ||
547 | |||
548 | static bool cdv_intel_find_dp_pll(const struct cdv_intel_limit_t *limit, struct drm_crtc *crtc, int target, | ||
549 | int refclk, | ||
550 | struct cdv_intel_clock_t *best_clock) | ||
551 | { | ||
552 | struct cdv_intel_clock_t clock; | ||
553 | if (refclk == 27000) { | 416 | if (refclk == 27000) { |
554 | if (target < 200000) { | 417 | if (target < 200000) { |
555 | clock.p1 = 2; | 418 | clock.p1 = 2; |
@@ -584,85 +447,10 @@ static bool cdv_intel_find_dp_pll(const struct cdv_intel_limit_t *limit, struct | |||
584 | clock.p = clock.p1 * clock.p2; | 447 | clock.p = clock.p1 * clock.p2; |
585 | clock.vco = (refclk * clock.m) / clock.n; | 448 | clock.vco = (refclk * clock.m) / clock.n; |
586 | clock.dot = clock.vco / clock.p; | 449 | clock.dot = clock.vco / clock.p; |
587 | memcpy(best_clock, &clock, sizeof(struct cdv_intel_clock_t)); | 450 | memcpy(best_clock, &clock, sizeof(struct gma_clock_t)); |
588 | return true; | 451 | return true; |
589 | } | 452 | } |
590 | 453 | ||
591 | static int cdv_intel_pipe_set_base(struct drm_crtc *crtc, | ||
592 | int x, int y, struct drm_framebuffer *old_fb) | ||
593 | { | ||
594 | struct drm_device *dev = crtc->dev; | ||
595 | struct drm_psb_private *dev_priv = dev->dev_private; | ||
596 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); | ||
597 | struct psb_framebuffer *psbfb = to_psb_fb(crtc->fb); | ||
598 | int pipe = psb_intel_crtc->pipe; | ||
599 | const struct psb_offset *map = &dev_priv->regmap[pipe]; | ||
600 | unsigned long start, offset; | ||
601 | u32 dspcntr; | ||
602 | int ret = 0; | ||
603 | |||
604 | if (!gma_power_begin(dev, true)) | ||
605 | return 0; | ||
606 | |||
607 | /* no fb bound */ | ||
608 | if (!crtc->fb) { | ||
609 | dev_err(dev->dev, "No FB bound\n"); | ||
610 | goto psb_intel_pipe_cleaner; | ||
611 | } | ||
612 | |||
613 | |||
614 | /* We are displaying this buffer, make sure it is actually loaded | ||
615 | into the GTT */ | ||
616 | ret = psb_gtt_pin(psbfb->gtt); | ||
617 | if (ret < 0) | ||
618 | goto psb_intel_pipe_set_base_exit; | ||
619 | start = psbfb->gtt->offset; | ||
620 | offset = y * crtc->fb->pitches[0] + x * (crtc->fb->bits_per_pixel / 8); | ||
621 | |||
622 | REG_WRITE(map->stride, crtc->fb->pitches[0]); | ||
623 | |||
624 | dspcntr = REG_READ(map->cntr); | ||
625 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | ||
626 | |||
627 | switch (crtc->fb->bits_per_pixel) { | ||
628 | case 8: | ||
629 | dspcntr |= DISPPLANE_8BPP; | ||
630 | break; | ||
631 | case 16: | ||
632 | if (crtc->fb->depth == 15) | ||
633 | dspcntr |= DISPPLANE_15_16BPP; | ||
634 | else | ||
635 | dspcntr |= DISPPLANE_16BPP; | ||
636 | break; | ||
637 | case 24: | ||
638 | case 32: | ||
639 | dspcntr |= DISPPLANE_32BPP_NO_ALPHA; | ||
640 | break; | ||
641 | default: | ||
642 | dev_err(dev->dev, "Unknown color depth\n"); | ||
643 | ret = -EINVAL; | ||
644 | goto psb_intel_pipe_set_base_exit; | ||
645 | } | ||
646 | REG_WRITE(map->cntr, dspcntr); | ||
647 | |||
648 | dev_dbg(dev->dev, | ||
649 | "Writing base %08lX %08lX %d %d\n", start, offset, x, y); | ||
650 | |||
651 | REG_WRITE(map->base, offset); | ||
652 | REG_READ(map->base); | ||
653 | REG_WRITE(map->surf, start); | ||
654 | REG_READ(map->surf); | ||
655 | |||
656 | psb_intel_pipe_cleaner: | ||
657 | /* If there was a previous display we can now unpin it */ | ||
658 | if (old_fb) | ||
659 | psb_gtt_unpin(to_psb_fb(old_fb)->gtt); | ||
660 | |||
661 | psb_intel_pipe_set_base_exit: | ||
662 | gma_power_end(dev); | ||
663 | return ret; | ||
664 | } | ||
665 | |||
666 | #define FIFO_PIPEA (1 << 0) | 454 | #define FIFO_PIPEA (1 << 0) |
667 | #define FIFO_PIPEB (1 << 1) | 455 | #define FIFO_PIPEB (1 << 1) |
668 | 456 | ||
@@ -670,12 +458,12 @@ static bool cdv_intel_pipe_enabled(struct drm_device *dev, int pipe) | |||
670 | { | 458 | { |
671 | struct drm_crtc *crtc; | 459 | struct drm_crtc *crtc; |
672 | struct drm_psb_private *dev_priv = dev->dev_private; | 460 | struct drm_psb_private *dev_priv = dev->dev_private; |
673 | struct psb_intel_crtc *psb_intel_crtc = NULL; | 461 | struct gma_crtc *gma_crtc = NULL; |
674 | 462 | ||
675 | crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | 463 | crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
676 | psb_intel_crtc = to_psb_intel_crtc(crtc); | 464 | gma_crtc = to_gma_crtc(crtc); |
677 | 465 | ||
678 | if (crtc->fb == NULL || !psb_intel_crtc->active) | 466 | if (crtc->fb == NULL || !gma_crtc->active) |
679 | return false; | 467 | return false; |
680 | return true; | 468 | return true; |
681 | } | 469 | } |
@@ -701,29 +489,29 @@ static bool cdv_intel_single_pipe_active (struct drm_device *dev) | |||
701 | 489 | ||
702 | static bool is_pipeb_lvds(struct drm_device *dev, struct drm_crtc *crtc) | 490 | static bool is_pipeb_lvds(struct drm_device *dev, struct drm_crtc *crtc) |
703 | { | 491 | { |
704 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); | 492 | struct gma_crtc *gma_crtc = to_gma_crtc(crtc); |
705 | struct drm_mode_config *mode_config = &dev->mode_config; | 493 | struct drm_mode_config *mode_config = &dev->mode_config; |
706 | struct drm_connector *connector; | 494 | struct drm_connector *connector; |
707 | 495 | ||
708 | if (psb_intel_crtc->pipe != 1) | 496 | if (gma_crtc->pipe != 1) |
709 | return false; | 497 | return false; |
710 | 498 | ||
711 | list_for_each_entry(connector, &mode_config->connector_list, head) { | 499 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
712 | struct psb_intel_encoder *psb_intel_encoder = | 500 | struct gma_encoder *gma_encoder = |
713 | psb_intel_attached_encoder(connector); | 501 | gma_attached_encoder(connector); |
714 | 502 | ||
715 | if (!connector->encoder | 503 | if (!connector->encoder |
716 | || connector->encoder->crtc != crtc) | 504 | || connector->encoder->crtc != crtc) |
717 | continue; | 505 | continue; |
718 | 506 | ||
719 | if (psb_intel_encoder->type == INTEL_OUTPUT_LVDS) | 507 | if (gma_encoder->type == INTEL_OUTPUT_LVDS) |
720 | return true; | 508 | return true; |
721 | } | 509 | } |
722 | 510 | ||
723 | return false; | 511 | return false; |
724 | } | 512 | } |
725 | 513 | ||
726 | static void cdv_intel_disable_self_refresh (struct drm_device *dev) | 514 | void cdv_disable_sr(struct drm_device *dev) |
727 | { | 515 | { |
728 | if (REG_READ(FW_BLC_SELF) & FW_BLC_SELF_EN) { | 516 | if (REG_READ(FW_BLC_SELF) & FW_BLC_SELF_EN) { |
729 | 517 | ||
@@ -731,7 +519,7 @@ static void cdv_intel_disable_self_refresh (struct drm_device *dev) | |||
731 | REG_WRITE(FW_BLC_SELF, (REG_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN)); | 519 | REG_WRITE(FW_BLC_SELF, (REG_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN)); |
732 | REG_READ(FW_BLC_SELF); | 520 | REG_READ(FW_BLC_SELF); |
733 | 521 | ||
734 | cdv_intel_wait_for_vblank(dev); | 522 | gma_wait_for_vblank(dev); |
735 | 523 | ||
736 | /* Cedarview workaround to write ovelay plane, which force to leave | 524 | /* Cedarview workaround to write ovelay plane, which force to leave |
737 | * MAX_FIFO state. | 525 | * MAX_FIFO state. |
@@ -739,13 +527,14 @@ static void cdv_intel_disable_self_refresh (struct drm_device *dev) | |||
739 | REG_WRITE(OV_OVADD, 0/*dev_priv->ovl_offset*/); | 527 | REG_WRITE(OV_OVADD, 0/*dev_priv->ovl_offset*/); |
740 | REG_READ(OV_OVADD); | 528 | REG_READ(OV_OVADD); |
741 | 529 | ||
742 | cdv_intel_wait_for_vblank(dev); | 530 | gma_wait_for_vblank(dev); |
743 | } | 531 | } |
744 | 532 | ||
745 | } | 533 | } |
746 | 534 | ||
747 | static void cdv_intel_update_watermark (struct drm_device *dev, struct drm_crtc *crtc) | 535 | void cdv_update_wm(struct drm_device *dev, struct drm_crtc *crtc) |
748 | { | 536 | { |
537 | struct drm_psb_private *dev_priv = dev->dev_private; | ||
749 | 538 | ||
750 | if (cdv_intel_single_pipe_active(dev)) { | 539 | if (cdv_intel_single_pipe_active(dev)) { |
751 | u32 fw; | 540 | u32 fw; |
@@ -780,12 +569,12 @@ static void cdv_intel_update_watermark (struct drm_device *dev, struct drm_crtc | |||
780 | 569 | ||
781 | REG_WRITE(DSPFW6, 0x10); | 570 | REG_WRITE(DSPFW6, 0x10); |
782 | 571 | ||
783 | cdv_intel_wait_for_vblank(dev); | 572 | gma_wait_for_vblank(dev); |
784 | 573 | ||
785 | /* enable self-refresh for single pipe active */ | 574 | /* enable self-refresh for single pipe active */ |
786 | REG_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); | 575 | REG_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); |
787 | REG_READ(FW_BLC_SELF); | 576 | REG_READ(FW_BLC_SELF); |
788 | cdv_intel_wait_for_vblank(dev); | 577 | gma_wait_for_vblank(dev); |
789 | 578 | ||
790 | } else { | 579 | } else { |
791 | 580 | ||
@@ -797,216 +586,12 @@ static void cdv_intel_update_watermark (struct drm_device *dev, struct drm_crtc | |||
797 | REG_WRITE(DSPFW5, 0x01010101); | 586 | REG_WRITE(DSPFW5, 0x01010101); |
798 | REG_WRITE(DSPFW6, 0x1d0); | 587 | REG_WRITE(DSPFW6, 0x1d0); |
799 | 588 | ||
800 | cdv_intel_wait_for_vblank(dev); | 589 | gma_wait_for_vblank(dev); |
801 | |||
802 | cdv_intel_disable_self_refresh(dev); | ||
803 | |||
804 | } | ||
805 | } | ||
806 | |||
807 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | ||
808 | static void cdv_intel_crtc_load_lut(struct drm_crtc *crtc) | ||
809 | { | ||
810 | struct drm_device *dev = crtc->dev; | ||
811 | struct drm_psb_private *dev_priv = dev->dev_private; | ||
812 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); | ||
813 | int palreg = PALETTE_A; | ||
814 | int i; | ||
815 | |||
816 | /* The clocks have to be on to load the palette. */ | ||
817 | if (!crtc->enabled) | ||
818 | return; | ||
819 | |||
820 | switch (psb_intel_crtc->pipe) { | ||
821 | case 0: | ||
822 | break; | ||
823 | case 1: | ||
824 | palreg = PALETTE_B; | ||
825 | break; | ||
826 | case 2: | ||
827 | palreg = PALETTE_C; | ||
828 | break; | ||
829 | default: | ||
830 | dev_err(dev->dev, "Illegal Pipe Number.\n"); | ||
831 | return; | ||
832 | } | ||
833 | |||
834 | if (gma_power_begin(dev, false)) { | ||
835 | for (i = 0; i < 256; i++) { | ||
836 | REG_WRITE(palreg + 4 * i, | ||
837 | ((psb_intel_crtc->lut_r[i] + | ||
838 | psb_intel_crtc->lut_adj[i]) << 16) | | ||
839 | ((psb_intel_crtc->lut_g[i] + | ||
840 | psb_intel_crtc->lut_adj[i]) << 8) | | ||
841 | (psb_intel_crtc->lut_b[i] + | ||
842 | psb_intel_crtc->lut_adj[i])); | ||
843 | } | ||
844 | gma_power_end(dev); | ||
845 | } else { | ||
846 | for (i = 0; i < 256; i++) { | ||
847 | dev_priv->regs.pipe[0].palette[i] = | ||
848 | ((psb_intel_crtc->lut_r[i] + | ||
849 | psb_intel_crtc->lut_adj[i]) << 16) | | ||
850 | ((psb_intel_crtc->lut_g[i] + | ||
851 | psb_intel_crtc->lut_adj[i]) << 8) | | ||
852 | (psb_intel_crtc->lut_b[i] + | ||
853 | psb_intel_crtc->lut_adj[i]); | ||
854 | } | ||
855 | |||
856 | } | ||
857 | } | ||
858 | |||
859 | /** | ||
860 | * Sets the power management mode of the pipe and plane. | ||
861 | * | ||
862 | * This code should probably grow support for turning the cursor off and back | ||
863 | * on appropriately at the same time as we're turning the pipe off/on. | ||
864 | */ | ||
865 | static void cdv_intel_crtc_dpms(struct drm_crtc *crtc, int mode) | ||
866 | { | ||
867 | struct drm_device *dev = crtc->dev; | ||
868 | struct drm_psb_private *dev_priv = dev->dev_private; | ||
869 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); | ||
870 | int pipe = psb_intel_crtc->pipe; | ||
871 | const struct psb_offset *map = &dev_priv->regmap[pipe]; | ||
872 | u32 temp; | ||
873 | |||
874 | /* XXX: When our outputs are all unaware of DPMS modes other than off | ||
875 | * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. | ||
876 | */ | ||
877 | cdv_intel_disable_self_refresh(dev); | ||
878 | |||
879 | switch (mode) { | ||
880 | case DRM_MODE_DPMS_ON: | ||
881 | case DRM_MODE_DPMS_STANDBY: | ||
882 | case DRM_MODE_DPMS_SUSPEND: | ||
883 | if (psb_intel_crtc->active) | ||
884 | break; | ||
885 | |||
886 | psb_intel_crtc->active = true; | ||
887 | |||
888 | /* Enable the DPLL */ | ||
889 | temp = REG_READ(map->dpll); | ||
890 | if ((temp & DPLL_VCO_ENABLE) == 0) { | ||
891 | REG_WRITE(map->dpll, temp); | ||
892 | REG_READ(map->dpll); | ||
893 | /* Wait for the clocks to stabilize. */ | ||
894 | udelay(150); | ||
895 | REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); | ||
896 | REG_READ(map->dpll); | ||
897 | /* Wait for the clocks to stabilize. */ | ||
898 | udelay(150); | ||
899 | REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); | ||
900 | REG_READ(map->dpll); | ||
901 | /* Wait for the clocks to stabilize. */ | ||
902 | udelay(150); | ||
903 | } | ||
904 | |||
905 | /* Jim Bish - switch plan and pipe per scott */ | ||
906 | /* Enable the plane */ | ||
907 | temp = REG_READ(map->cntr); | ||
908 | if ((temp & DISPLAY_PLANE_ENABLE) == 0) { | ||
909 | REG_WRITE(map->cntr, | ||
910 | temp | DISPLAY_PLANE_ENABLE); | ||
911 | /* Flush the plane changes */ | ||
912 | REG_WRITE(map->base, REG_READ(map->base)); | ||
913 | } | ||
914 | |||
915 | udelay(150); | ||
916 | |||
917 | /* Enable the pipe */ | ||
918 | temp = REG_READ(map->conf); | ||
919 | if ((temp & PIPEACONF_ENABLE) == 0) | ||
920 | REG_WRITE(map->conf, temp | PIPEACONF_ENABLE); | ||
921 | |||
922 | temp = REG_READ(map->status); | ||
923 | temp &= ~(0xFFFF); | ||
924 | temp |= PIPE_FIFO_UNDERRUN; | ||
925 | REG_WRITE(map->status, temp); | ||
926 | REG_READ(map->status); | ||
927 | |||
928 | cdv_intel_crtc_load_lut(crtc); | ||
929 | |||
930 | /* Give the overlay scaler a chance to enable | ||
931 | * if it's on this pipe */ | ||
932 | /* psb_intel_crtc_dpms_video(crtc, true); TODO */ | ||
933 | break; | ||
934 | case DRM_MODE_DPMS_OFF: | ||
935 | if (!psb_intel_crtc->active) | ||
936 | break; | ||
937 | |||
938 | psb_intel_crtc->active = false; | ||
939 | |||
940 | /* Give the overlay scaler a chance to disable | ||
941 | * if it's on this pipe */ | ||
942 | /* psb_intel_crtc_dpms_video(crtc, FALSE); TODO */ | ||
943 | |||
944 | /* Disable the VGA plane that we never use */ | ||
945 | REG_WRITE(VGACNTRL, VGA_DISP_DISABLE); | ||
946 | |||
947 | /* Jim Bish - changed pipe/plane here as well. */ | ||
948 | |||
949 | drm_vblank_off(dev, pipe); | ||
950 | /* Wait for vblank for the disable to take effect */ | ||
951 | cdv_intel_wait_for_vblank(dev); | ||
952 | |||
953 | /* Next, disable display pipes */ | ||
954 | temp = REG_READ(map->conf); | ||
955 | if ((temp & PIPEACONF_ENABLE) != 0) { | ||
956 | REG_WRITE(map->conf, temp & ~PIPEACONF_ENABLE); | ||
957 | REG_READ(map->conf); | ||
958 | } | ||
959 | |||
960 | /* Wait for vblank for the disable to take effect. */ | ||
961 | cdv_intel_wait_for_vblank(dev); | ||
962 | |||
963 | udelay(150); | ||
964 | |||
965 | /* Disable display plane */ | ||
966 | temp = REG_READ(map->cntr); | ||
967 | if ((temp & DISPLAY_PLANE_ENABLE) != 0) { | ||
968 | REG_WRITE(map->cntr, | ||
969 | temp & ~DISPLAY_PLANE_ENABLE); | ||
970 | /* Flush the plane changes */ | ||
971 | REG_WRITE(map->base, REG_READ(map->base)); | ||
972 | REG_READ(map->base); | ||
973 | } | ||
974 | |||
975 | temp = REG_READ(map->dpll); | ||
976 | if ((temp & DPLL_VCO_ENABLE) != 0) { | ||
977 | REG_WRITE(map->dpll, temp & ~DPLL_VCO_ENABLE); | ||
978 | REG_READ(map->dpll); | ||
979 | } | ||
980 | 590 | ||
981 | /* Wait for the clocks to turn off. */ | 591 | dev_priv->ops->disable_sr(dev); |
982 | udelay(150); | ||
983 | break; | ||
984 | } | 592 | } |
985 | cdv_intel_update_watermark(dev, crtc); | ||
986 | /*Set FIFO Watermarks*/ | ||
987 | REG_WRITE(DSPARB, 0x3F3E); | ||
988 | } | ||
989 | |||
990 | static void cdv_intel_crtc_prepare(struct drm_crtc *crtc) | ||
991 | { | ||
992 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; | ||
993 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF); | ||
994 | } | ||
995 | |||
996 | static void cdv_intel_crtc_commit(struct drm_crtc *crtc) | ||
997 | { | ||
998 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; | ||
999 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); | ||
1000 | } | ||
1001 | |||
1002 | static bool cdv_intel_crtc_mode_fixup(struct drm_crtc *crtc, | ||
1003 | const struct drm_display_mode *mode, | ||
1004 | struct drm_display_mode *adjusted_mode) | ||
1005 | { | ||
1006 | return true; | ||
1007 | } | 593 | } |
1008 | 594 | ||
1009 | |||
1010 | /** | 595 | /** |
1011 | * Return the pipe currently connected to the panel fitter, | 596 | * Return the pipe currently connected to the panel fitter, |
1012 | * or -1 if the panel fitter is not present or not in use | 597 | * or -1 if the panel fitter is not present or not in use |
@@ -1031,31 +616,31 @@ static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc, | |||
1031 | { | 616 | { |
1032 | struct drm_device *dev = crtc->dev; | 617 | struct drm_device *dev = crtc->dev; |
1033 | struct drm_psb_private *dev_priv = dev->dev_private; | 618 | struct drm_psb_private *dev_priv = dev->dev_private; |
1034 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); | 619 | struct gma_crtc *gma_crtc = to_gma_crtc(crtc); |
1035 | int pipe = psb_intel_crtc->pipe; | 620 | int pipe = gma_crtc->pipe; |
1036 | const struct psb_offset *map = &dev_priv->regmap[pipe]; | 621 | const struct psb_offset *map = &dev_priv->regmap[pipe]; |
1037 | int refclk; | 622 | int refclk; |
1038 | struct cdv_intel_clock_t clock; | 623 | struct gma_clock_t clock; |
1039 | u32 dpll = 0, dspcntr, pipeconf; | 624 | u32 dpll = 0, dspcntr, pipeconf; |
1040 | bool ok; | 625 | bool ok; |
1041 | bool is_crt = false, is_lvds = false, is_tv = false; | 626 | bool is_crt = false, is_lvds = false, is_tv = false; |
1042 | bool is_hdmi = false, is_dp = false; | 627 | bool is_hdmi = false, is_dp = false; |
1043 | struct drm_mode_config *mode_config = &dev->mode_config; | 628 | struct drm_mode_config *mode_config = &dev->mode_config; |
1044 | struct drm_connector *connector; | 629 | struct drm_connector *connector; |
1045 | const struct cdv_intel_limit_t *limit; | 630 | const struct gma_limit_t *limit; |
1046 | u32 ddi_select = 0; | 631 | u32 ddi_select = 0; |
1047 | bool is_edp = false; | 632 | bool is_edp = false; |
1048 | 633 | ||
1049 | list_for_each_entry(connector, &mode_config->connector_list, head) { | 634 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
1050 | struct psb_intel_encoder *psb_intel_encoder = | 635 | struct gma_encoder *gma_encoder = |
1051 | psb_intel_attached_encoder(connector); | 636 | gma_attached_encoder(connector); |
1052 | 637 | ||
1053 | if (!connector->encoder | 638 | if (!connector->encoder |
1054 | || connector->encoder->crtc != crtc) | 639 | || connector->encoder->crtc != crtc) |
1055 | continue; | 640 | continue; |
1056 | 641 | ||
1057 | ddi_select = psb_intel_encoder->ddi_select; | 642 | ddi_select = gma_encoder->ddi_select; |
1058 | switch (psb_intel_encoder->type) { | 643 | switch (gma_encoder->type) { |
1059 | case INTEL_OUTPUT_LVDS: | 644 | case INTEL_OUTPUT_LVDS: |
1060 | is_lvds = true; | 645 | is_lvds = true; |
1061 | break; | 646 | break; |
@@ -1108,12 +693,13 @@ static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc, | |||
1108 | 693 | ||
1109 | drm_mode_debug_printmodeline(adjusted_mode); | 694 | drm_mode_debug_printmodeline(adjusted_mode); |
1110 | 695 | ||
1111 | limit = cdv_intel_limit(crtc, refclk); | 696 | limit = gma_crtc->clock_funcs->limit(crtc, refclk); |
1112 | 697 | ||
1113 | ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, | 698 | ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, |
1114 | &clock); | 699 | &clock); |
1115 | if (!ok) { | 700 | if (!ok) { |
1116 | dev_err(dev->dev, "Couldn't find PLL settings for mode!\n"); | 701 | DRM_ERROR("Couldn't find PLL settings for mode! target: %d, actual: %d", |
702 | adjusted_mode->clock, clock.dot); | ||
1117 | return 0; | 703 | return 0; |
1118 | } | 704 | } |
1119 | 705 | ||
@@ -1264,7 +850,7 @@ static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc, | |||
1264 | REG_WRITE(map->conf, pipeconf); | 850 | REG_WRITE(map->conf, pipeconf); |
1265 | REG_READ(map->conf); | 851 | REG_READ(map->conf); |
1266 | 852 | ||
1267 | cdv_intel_wait_for_vblank(dev); | 853 | gma_wait_for_vblank(dev); |
1268 | 854 | ||
1269 | REG_WRITE(map->cntr, dspcntr); | 855 | REG_WRITE(map->cntr, dspcntr); |
1270 | 856 | ||
@@ -1275,344 +861,16 @@ static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc, | |||
1275 | crtc_funcs->mode_set_base(crtc, x, y, old_fb); | 861 | crtc_funcs->mode_set_base(crtc, x, y, old_fb); |
1276 | } | 862 | } |
1277 | 863 | ||
1278 | cdv_intel_wait_for_vblank(dev); | 864 | gma_wait_for_vblank(dev); |
1279 | |||
1280 | return 0; | ||
1281 | } | ||
1282 | |||
1283 | |||
1284 | /** | ||
1285 | * Save HW states of giving crtc | ||
1286 | */ | ||
1287 | static void cdv_intel_crtc_save(struct drm_crtc *crtc) | ||
1288 | { | ||
1289 | struct drm_device *dev = crtc->dev; | ||
1290 | struct drm_psb_private *dev_priv = dev->dev_private; | ||
1291 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); | ||
1292 | struct psb_intel_crtc_state *crtc_state = psb_intel_crtc->crtc_state; | ||
1293 | const struct psb_offset *map = &dev_priv->regmap[psb_intel_crtc->pipe]; | ||
1294 | uint32_t paletteReg; | ||
1295 | int i; | ||
1296 | |||
1297 | if (!crtc_state) { | ||
1298 | dev_dbg(dev->dev, "No CRTC state found\n"); | ||
1299 | return; | ||
1300 | } | ||
1301 | |||
1302 | crtc_state->saveDSPCNTR = REG_READ(map->cntr); | ||
1303 | crtc_state->savePIPECONF = REG_READ(map->conf); | ||
1304 | crtc_state->savePIPESRC = REG_READ(map->src); | ||
1305 | crtc_state->saveFP0 = REG_READ(map->fp0); | ||
1306 | crtc_state->saveFP1 = REG_READ(map->fp1); | ||
1307 | crtc_state->saveDPLL = REG_READ(map->dpll); | ||
1308 | crtc_state->saveHTOTAL = REG_READ(map->htotal); | ||
1309 | crtc_state->saveHBLANK = REG_READ(map->hblank); | ||
1310 | crtc_state->saveHSYNC = REG_READ(map->hsync); | ||
1311 | crtc_state->saveVTOTAL = REG_READ(map->vtotal); | ||
1312 | crtc_state->saveVBLANK = REG_READ(map->vblank); | ||
1313 | crtc_state->saveVSYNC = REG_READ(map->vsync); | ||
1314 | crtc_state->saveDSPSTRIDE = REG_READ(map->stride); | ||
1315 | |||
1316 | /*NOTE: DSPSIZE DSPPOS only for psb*/ | ||
1317 | crtc_state->saveDSPSIZE = REG_READ(map->size); | ||
1318 | crtc_state->saveDSPPOS = REG_READ(map->pos); | ||
1319 | |||
1320 | crtc_state->saveDSPBASE = REG_READ(map->base); | ||
1321 | |||
1322 | DRM_DEBUG("(%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x)\n", | ||
1323 | crtc_state->saveDSPCNTR, | ||
1324 | crtc_state->savePIPECONF, | ||
1325 | crtc_state->savePIPESRC, | ||
1326 | crtc_state->saveFP0, | ||
1327 | crtc_state->saveFP1, | ||
1328 | crtc_state->saveDPLL, | ||
1329 | crtc_state->saveHTOTAL, | ||
1330 | crtc_state->saveHBLANK, | ||
1331 | crtc_state->saveHSYNC, | ||
1332 | crtc_state->saveVTOTAL, | ||
1333 | crtc_state->saveVBLANK, | ||
1334 | crtc_state->saveVSYNC, | ||
1335 | crtc_state->saveDSPSTRIDE, | ||
1336 | crtc_state->saveDSPSIZE, | ||
1337 | crtc_state->saveDSPPOS, | ||
1338 | crtc_state->saveDSPBASE | ||
1339 | ); | ||
1340 | |||
1341 | paletteReg = map->palette; | ||
1342 | for (i = 0; i < 256; ++i) | ||
1343 | crtc_state->savePalette[i] = REG_READ(paletteReg + (i << 2)); | ||
1344 | } | ||
1345 | |||
1346 | /** | ||
1347 | * Restore HW states of giving crtc | ||
1348 | */ | ||
1349 | static void cdv_intel_crtc_restore(struct drm_crtc *crtc) | ||
1350 | { | ||
1351 | struct drm_device *dev = crtc->dev; | ||
1352 | struct drm_psb_private *dev_priv = dev->dev_private; | ||
1353 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); | ||
1354 | struct psb_intel_crtc_state *crtc_state = psb_intel_crtc->crtc_state; | ||
1355 | const struct psb_offset *map = &dev_priv->regmap[psb_intel_crtc->pipe]; | ||
1356 | uint32_t paletteReg; | ||
1357 | int i; | ||
1358 | |||
1359 | if (!crtc_state) { | ||
1360 | dev_dbg(dev->dev, "No crtc state\n"); | ||
1361 | return; | ||
1362 | } | ||
1363 | |||
1364 | DRM_DEBUG( | ||
1365 | "current:(%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x)\n", | ||
1366 | REG_READ(map->cntr), | ||
1367 | REG_READ(map->conf), | ||
1368 | REG_READ(map->src), | ||
1369 | REG_READ(map->fp0), | ||
1370 | REG_READ(map->fp1), | ||
1371 | REG_READ(map->dpll), | ||
1372 | REG_READ(map->htotal), | ||
1373 | REG_READ(map->hblank), | ||
1374 | REG_READ(map->hsync), | ||
1375 | REG_READ(map->vtotal), | ||
1376 | REG_READ(map->vblank), | ||
1377 | REG_READ(map->vsync), | ||
1378 | REG_READ(map->stride), | ||
1379 | REG_READ(map->size), | ||
1380 | REG_READ(map->pos), | ||
1381 | REG_READ(map->base) | ||
1382 | ); | ||
1383 | |||
1384 | DRM_DEBUG( | ||
1385 | "saved: (%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x)\n", | ||
1386 | crtc_state->saveDSPCNTR, | ||
1387 | crtc_state->savePIPECONF, | ||
1388 | crtc_state->savePIPESRC, | ||
1389 | crtc_state->saveFP0, | ||
1390 | crtc_state->saveFP1, | ||
1391 | crtc_state->saveDPLL, | ||
1392 | crtc_state->saveHTOTAL, | ||
1393 | crtc_state->saveHBLANK, | ||
1394 | crtc_state->saveHSYNC, | ||
1395 | crtc_state->saveVTOTAL, | ||
1396 | crtc_state->saveVBLANK, | ||
1397 | crtc_state->saveVSYNC, | ||
1398 | crtc_state->saveDSPSTRIDE, | ||
1399 | crtc_state->saveDSPSIZE, | ||
1400 | crtc_state->saveDSPPOS, | ||
1401 | crtc_state->saveDSPBASE | ||
1402 | ); | ||
1403 | |||
1404 | |||
1405 | if (crtc_state->saveDPLL & DPLL_VCO_ENABLE) { | ||
1406 | REG_WRITE(map->dpll, | ||
1407 | crtc_state->saveDPLL & ~DPLL_VCO_ENABLE); | ||
1408 | REG_READ(map->dpll); | ||
1409 | DRM_DEBUG("write dpll: %x\n", | ||
1410 | REG_READ(map->dpll)); | ||
1411 | udelay(150); | ||
1412 | } | ||
1413 | |||
1414 | REG_WRITE(map->fp0, crtc_state->saveFP0); | ||
1415 | REG_READ(map->fp0); | ||
1416 | |||
1417 | REG_WRITE(map->fp1, crtc_state->saveFP1); | ||
1418 | REG_READ(map->fp1); | ||
1419 | |||
1420 | REG_WRITE(map->dpll, crtc_state->saveDPLL); | ||
1421 | REG_READ(map->dpll); | ||
1422 | udelay(150); | ||
1423 | |||
1424 | REG_WRITE(map->htotal, crtc_state->saveHTOTAL); | ||
1425 | REG_WRITE(map->hblank, crtc_state->saveHBLANK); | ||
1426 | REG_WRITE(map->hsync, crtc_state->saveHSYNC); | ||
1427 | REG_WRITE(map->vtotal, crtc_state->saveVTOTAL); | ||
1428 | REG_WRITE(map->vblank, crtc_state->saveVBLANK); | ||
1429 | REG_WRITE(map->vsync, crtc_state->saveVSYNC); | ||
1430 | REG_WRITE(map->stride, crtc_state->saveDSPSTRIDE); | ||
1431 | |||
1432 | REG_WRITE(map->size, crtc_state->saveDSPSIZE); | ||
1433 | REG_WRITE(map->pos, crtc_state->saveDSPPOS); | ||
1434 | |||
1435 | REG_WRITE(map->src, crtc_state->savePIPESRC); | ||
1436 | REG_WRITE(map->base, crtc_state->saveDSPBASE); | ||
1437 | REG_WRITE(map->conf, crtc_state->savePIPECONF); | ||
1438 | |||
1439 | cdv_intel_wait_for_vblank(dev); | ||
1440 | |||
1441 | REG_WRITE(map->cntr, crtc_state->saveDSPCNTR); | ||
1442 | REG_WRITE(map->base, crtc_state->saveDSPBASE); | ||
1443 | |||
1444 | cdv_intel_wait_for_vblank(dev); | ||
1445 | |||
1446 | paletteReg = map->palette; | ||
1447 | for (i = 0; i < 256; ++i) | ||
1448 | REG_WRITE(paletteReg + (i << 2), crtc_state->savePalette[i]); | ||
1449 | } | ||
1450 | |||
1451 | static int cdv_intel_crtc_cursor_set(struct drm_crtc *crtc, | ||
1452 | struct drm_file *file_priv, | ||
1453 | uint32_t handle, | ||
1454 | uint32_t width, uint32_t height) | ||
1455 | { | ||
1456 | struct drm_device *dev = crtc->dev; | ||
1457 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); | ||
1458 | int pipe = psb_intel_crtc->pipe; | ||
1459 | uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR; | ||
1460 | uint32_t base = (pipe == 0) ? CURABASE : CURBBASE; | ||
1461 | uint32_t temp; | ||
1462 | size_t addr = 0; | ||
1463 | struct gtt_range *gt; | ||
1464 | struct drm_gem_object *obj; | ||
1465 | int ret = 0; | ||
1466 | |||
1467 | /* if we want to turn of the cursor ignore width and height */ | ||
1468 | if (!handle) { | ||
1469 | /* turn off the cursor */ | ||
1470 | temp = CURSOR_MODE_DISABLE; | ||
1471 | |||
1472 | if (gma_power_begin(dev, false)) { | ||
1473 | REG_WRITE(control, temp); | ||
1474 | REG_WRITE(base, 0); | ||
1475 | gma_power_end(dev); | ||
1476 | } | ||
1477 | |||
1478 | /* unpin the old GEM object */ | ||
1479 | if (psb_intel_crtc->cursor_obj) { | ||
1480 | gt = container_of(psb_intel_crtc->cursor_obj, | ||
1481 | struct gtt_range, gem); | ||
1482 | psb_gtt_unpin(gt); | ||
1483 | drm_gem_object_unreference(psb_intel_crtc->cursor_obj); | ||
1484 | psb_intel_crtc->cursor_obj = NULL; | ||
1485 | } | ||
1486 | |||
1487 | return 0; | ||
1488 | } | ||
1489 | |||
1490 | /* Currently we only support 64x64 cursors */ | ||
1491 | if (width != 64 || height != 64) { | ||
1492 | dev_dbg(dev->dev, "we currently only support 64x64 cursors\n"); | ||
1493 | return -EINVAL; | ||
1494 | } | ||
1495 | |||
1496 | obj = drm_gem_object_lookup(dev, file_priv, handle); | ||
1497 | if (!obj) | ||
1498 | return -ENOENT; | ||
1499 | |||
1500 | if (obj->size < width * height * 4) { | ||
1501 | dev_dbg(dev->dev, "buffer is to small\n"); | ||
1502 | ret = -ENOMEM; | ||
1503 | goto unref_cursor; | ||
1504 | } | ||
1505 | |||
1506 | gt = container_of(obj, struct gtt_range, gem); | ||
1507 | |||
1508 | /* Pin the memory into the GTT */ | ||
1509 | ret = psb_gtt_pin(gt); | ||
1510 | if (ret) { | ||
1511 | dev_err(dev->dev, "Can not pin down handle 0x%x\n", handle); | ||
1512 | goto unref_cursor; | ||
1513 | } | ||
1514 | |||
1515 | addr = gt->offset; /* Or resource.start ??? */ | ||
1516 | |||
1517 | psb_intel_crtc->cursor_addr = addr; | ||
1518 | |||
1519 | temp = 0; | ||
1520 | /* set the pipe for the cursor */ | ||
1521 | temp |= (pipe << 28); | ||
1522 | temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; | ||
1523 | |||
1524 | if (gma_power_begin(dev, false)) { | ||
1525 | REG_WRITE(control, temp); | ||
1526 | REG_WRITE(base, addr); | ||
1527 | gma_power_end(dev); | ||
1528 | } | ||
1529 | |||
1530 | /* unpin the old GEM object */ | ||
1531 | if (psb_intel_crtc->cursor_obj) { | ||
1532 | gt = container_of(psb_intel_crtc->cursor_obj, | ||
1533 | struct gtt_range, gem); | ||
1534 | psb_gtt_unpin(gt); | ||
1535 | drm_gem_object_unreference(psb_intel_crtc->cursor_obj); | ||
1536 | } | ||
1537 | |||
1538 | psb_intel_crtc->cursor_obj = obj; | ||
1539 | return ret; | ||
1540 | |||
1541 | unref_cursor: | ||
1542 | drm_gem_object_unreference(obj); | ||
1543 | return ret; | ||
1544 | } | ||
1545 | |||
1546 | static int cdv_intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) | ||
1547 | { | ||
1548 | struct drm_device *dev = crtc->dev; | ||
1549 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); | ||
1550 | int pipe = psb_intel_crtc->pipe; | ||
1551 | uint32_t temp = 0; | ||
1552 | uint32_t adder; | ||
1553 | |||
1554 | |||
1555 | if (x < 0) { | ||
1556 | temp |= (CURSOR_POS_SIGN << CURSOR_X_SHIFT); | ||
1557 | x = -x; | ||
1558 | } | ||
1559 | if (y < 0) { | ||
1560 | temp |= (CURSOR_POS_SIGN << CURSOR_Y_SHIFT); | ||
1561 | y = -y; | ||
1562 | } | ||
1563 | |||
1564 | temp |= ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT); | ||
1565 | temp |= ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT); | ||
1566 | 865 | ||
1567 | adder = psb_intel_crtc->cursor_addr; | ||
1568 | |||
1569 | if (gma_power_begin(dev, false)) { | ||
1570 | REG_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp); | ||
1571 | REG_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder); | ||
1572 | gma_power_end(dev); | ||
1573 | } | ||
1574 | return 0; | 866 | return 0; |
1575 | } | 867 | } |
1576 | 868 | ||
1577 | static void cdv_intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, | ||
1578 | u16 *green, u16 *blue, uint32_t start, uint32_t size) | ||
1579 | { | ||
1580 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); | ||
1581 | int i; | ||
1582 | int end = (start + size > 256) ? 256 : start + size; | ||
1583 | |||
1584 | for (i = start; i < end; i++) { | ||
1585 | psb_intel_crtc->lut_r[i] = red[i] >> 8; | ||
1586 | psb_intel_crtc->lut_g[i] = green[i] >> 8; | ||
1587 | psb_intel_crtc->lut_b[i] = blue[i] >> 8; | ||
1588 | } | ||
1589 | |||
1590 | cdv_intel_crtc_load_lut(crtc); | ||
1591 | } | ||
1592 | |||
1593 | static int cdv_crtc_set_config(struct drm_mode_set *set) | ||
1594 | { | ||
1595 | int ret = 0; | ||
1596 | struct drm_device *dev = set->crtc->dev; | ||
1597 | struct drm_psb_private *dev_priv = dev->dev_private; | ||
1598 | |||
1599 | if (!dev_priv->rpm_enabled) | ||
1600 | return drm_crtc_helper_set_config(set); | ||
1601 | |||
1602 | pm_runtime_forbid(&dev->pdev->dev); | ||
1603 | |||
1604 | ret = drm_crtc_helper_set_config(set); | ||
1605 | |||
1606 | pm_runtime_allow(&dev->pdev->dev); | ||
1607 | |||
1608 | return ret; | ||
1609 | } | ||
1610 | |||
1611 | /** Derive the pixel clock for the given refclk and divisors for 8xx chips. */ | 869 | /** Derive the pixel clock for the given refclk and divisors for 8xx chips. */ |
1612 | 870 | ||
1613 | /* FIXME: why are we using this, should it be cdv_ in this tree ? */ | 871 | /* FIXME: why are we using this, should it be cdv_ in this tree ? */ |
1614 | 872 | ||
1615 | static void i8xx_clock(int refclk, struct cdv_intel_clock_t *clock) | 873 | static void i8xx_clock(int refclk, struct gma_clock_t *clock) |
1616 | { | 874 | { |
1617 | clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); | 875 | clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); |
1618 | clock->p = clock->p1 * clock->p2; | 876 | clock->p = clock->p1 * clock->p2; |
@@ -1625,12 +883,12 @@ static int cdv_intel_crtc_clock_get(struct drm_device *dev, | |||
1625 | struct drm_crtc *crtc) | 883 | struct drm_crtc *crtc) |
1626 | { | 884 | { |
1627 | struct drm_psb_private *dev_priv = dev->dev_private; | 885 | struct drm_psb_private *dev_priv = dev->dev_private; |
1628 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); | 886 | struct gma_crtc *gma_crtc = to_gma_crtc(crtc); |
1629 | int pipe = psb_intel_crtc->pipe; | 887 | int pipe = gma_crtc->pipe; |
1630 | const struct psb_offset *map = &dev_priv->regmap[pipe]; | 888 | const struct psb_offset *map = &dev_priv->regmap[pipe]; |
1631 | u32 dpll; | 889 | u32 dpll; |
1632 | u32 fp; | 890 | u32 fp; |
1633 | struct cdv_intel_clock_t clock; | 891 | struct gma_clock_t clock; |
1634 | bool is_lvds; | 892 | bool is_lvds; |
1635 | struct psb_pipe *p = &dev_priv->regs.pipe[pipe]; | 893 | struct psb_pipe *p = &dev_priv->regs.pipe[pipe]; |
1636 | 894 | ||
@@ -1703,8 +961,8 @@ static int cdv_intel_crtc_clock_get(struct drm_device *dev, | |||
1703 | struct drm_display_mode *cdv_intel_crtc_mode_get(struct drm_device *dev, | 961 | struct drm_display_mode *cdv_intel_crtc_mode_get(struct drm_device *dev, |
1704 | struct drm_crtc *crtc) | 962 | struct drm_crtc *crtc) |
1705 | { | 963 | { |
1706 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); | 964 | struct gma_crtc *gma_crtc = to_gma_crtc(crtc); |
1707 | int pipe = psb_intel_crtc->pipe; | 965 | int pipe = gma_crtc->pipe; |
1708 | struct drm_psb_private *dev_priv = dev->dev_private; | 966 | struct drm_psb_private *dev_priv = dev->dev_private; |
1709 | struct psb_pipe *p = &dev_priv->regs.pipe[pipe]; | 967 | struct psb_pipe *p = &dev_priv->regs.pipe[pipe]; |
1710 | const struct psb_offset *map = &dev_priv->regmap[pipe]; | 968 | const struct psb_offset *map = &dev_priv->regmap[pipe]; |
@@ -1747,44 +1005,28 @@ struct drm_display_mode *cdv_intel_crtc_mode_get(struct drm_device *dev, | |||
1747 | return mode; | 1005 | return mode; |
1748 | } | 1006 | } |
1749 | 1007 | ||
1750 | static void cdv_intel_crtc_destroy(struct drm_crtc *crtc) | ||
1751 | { | ||
1752 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); | ||
1753 | |||
1754 | kfree(psb_intel_crtc->crtc_state); | ||
1755 | drm_crtc_cleanup(crtc); | ||
1756 | kfree(psb_intel_crtc); | ||
1757 | } | ||
1758 | |||
1759 | static void cdv_intel_crtc_disable(struct drm_crtc *crtc) | ||
1760 | { | ||
1761 | struct gtt_range *gt; | ||
1762 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; | ||
1763 | |||
1764 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF); | ||
1765 | |||
1766 | if (crtc->fb) { | ||
1767 | gt = to_psb_fb(crtc->fb)->gtt; | ||
1768 | psb_gtt_unpin(gt); | ||
1769 | } | ||
1770 | } | ||
1771 | |||
1772 | const struct drm_crtc_helper_funcs cdv_intel_helper_funcs = { | 1008 | const struct drm_crtc_helper_funcs cdv_intel_helper_funcs = { |
1773 | .dpms = cdv_intel_crtc_dpms, | 1009 | .dpms = gma_crtc_dpms, |
1774 | .mode_fixup = cdv_intel_crtc_mode_fixup, | 1010 | .mode_fixup = gma_crtc_mode_fixup, |
1775 | .mode_set = cdv_intel_crtc_mode_set, | 1011 | .mode_set = cdv_intel_crtc_mode_set, |
1776 | .mode_set_base = cdv_intel_pipe_set_base, | 1012 | .mode_set_base = gma_pipe_set_base, |
1777 | .prepare = cdv_intel_crtc_prepare, | 1013 | .prepare = gma_crtc_prepare, |
1778 | .commit = cdv_intel_crtc_commit, | 1014 | .commit = gma_crtc_commit, |
1779 | .disable = cdv_intel_crtc_disable, | 1015 | .disable = gma_crtc_disable, |
1780 | }; | 1016 | }; |
1781 | 1017 | ||
1782 | const struct drm_crtc_funcs cdv_intel_crtc_funcs = { | 1018 | const struct drm_crtc_funcs cdv_intel_crtc_funcs = { |
1783 | .save = cdv_intel_crtc_save, | 1019 | .save = gma_crtc_save, |
1784 | .restore = cdv_intel_crtc_restore, | 1020 | .restore = gma_crtc_restore, |
1785 | .cursor_set = cdv_intel_crtc_cursor_set, | 1021 | .cursor_set = gma_crtc_cursor_set, |
1786 | .cursor_move = cdv_intel_crtc_cursor_move, | 1022 | .cursor_move = gma_crtc_cursor_move, |
1787 | .gamma_set = cdv_intel_crtc_gamma_set, | 1023 | .gamma_set = gma_crtc_gamma_set, |
1788 | .set_config = cdv_crtc_set_config, | 1024 | .set_config = gma_crtc_set_config, |
1789 | .destroy = cdv_intel_crtc_destroy, | 1025 | .destroy = gma_crtc_destroy, |
1026 | }; | ||
1027 | |||
1028 | const struct gma_clock_funcs cdv_clock_funcs = { | ||
1029 | .clock = cdv_intel_clock, | ||
1030 | .limit = cdv_intel_limit, | ||
1031 | .pll_is_valid = gma_pll_is_valid, | ||
1790 | }; | 1032 | }; |
diff --git a/drivers/gpu/drm/gma500/cdv_intel_dp.c b/drivers/gpu/drm/gma500/cdv_intel_dp.c index 88d9ef6b5b4a..f4eb43573cad 100644 --- a/drivers/gpu/drm/gma500/cdv_intel_dp.c +++ b/drivers/gpu/drm/gma500/cdv_intel_dp.c | |||
@@ -34,6 +34,7 @@ | |||
34 | #include "psb_drv.h" | 34 | #include "psb_drv.h" |
35 | #include "psb_intel_drv.h" | 35 | #include "psb_intel_drv.h" |
36 | #include "psb_intel_reg.h" | 36 | #include "psb_intel_reg.h" |
37 | #include "gma_display.h" | ||
37 | #include <drm/drm_dp_helper.h> | 38 | #include <drm/drm_dp_helper.h> |
38 | 39 | ||
39 | #define _wait_for(COND, MS, W) ({ \ | 40 | #define _wait_for(COND, MS, W) ({ \ |
@@ -68,7 +69,7 @@ struct cdv_intel_dp { | |||
68 | uint8_t link_bw; | 69 | uint8_t link_bw; |
69 | uint8_t lane_count; | 70 | uint8_t lane_count; |
70 | uint8_t dpcd[4]; | 71 | uint8_t dpcd[4]; |
71 | struct psb_intel_encoder *encoder; | 72 | struct gma_encoder *encoder; |
72 | struct i2c_adapter adapter; | 73 | struct i2c_adapter adapter; |
73 | struct i2c_algo_dp_aux_data algo; | 74 | struct i2c_algo_dp_aux_data algo; |
74 | uint8_t train_set[4]; | 75 | uint8_t train_set[4]; |
@@ -114,18 +115,18 @@ static uint32_t dp_vswing_premph_table[] = { | |||
114 | * If a CPU or PCH DP output is attached to an eDP panel, this function | 115 | * If a CPU or PCH DP output is attached to an eDP panel, this function |
115 | * will return true, and false otherwise. | 116 | * will return true, and false otherwise. |
116 | */ | 117 | */ |
117 | static bool is_edp(struct psb_intel_encoder *encoder) | 118 | static bool is_edp(struct gma_encoder *encoder) |
118 | { | 119 | { |
119 | return encoder->type == INTEL_OUTPUT_EDP; | 120 | return encoder->type == INTEL_OUTPUT_EDP; |
120 | } | 121 | } |
121 | 122 | ||
122 | 123 | ||
123 | static void cdv_intel_dp_start_link_train(struct psb_intel_encoder *encoder); | 124 | static void cdv_intel_dp_start_link_train(struct gma_encoder *encoder); |
124 | static void cdv_intel_dp_complete_link_train(struct psb_intel_encoder *encoder); | 125 | static void cdv_intel_dp_complete_link_train(struct gma_encoder *encoder); |
125 | static void cdv_intel_dp_link_down(struct psb_intel_encoder *encoder); | 126 | static void cdv_intel_dp_link_down(struct gma_encoder *encoder); |
126 | 127 | ||
127 | static int | 128 | static int |
128 | cdv_intel_dp_max_lane_count(struct psb_intel_encoder *encoder) | 129 | cdv_intel_dp_max_lane_count(struct gma_encoder *encoder) |
129 | { | 130 | { |
130 | struct cdv_intel_dp *intel_dp = encoder->dev_priv; | 131 | struct cdv_intel_dp *intel_dp = encoder->dev_priv; |
131 | int max_lane_count = 4; | 132 | int max_lane_count = 4; |
@@ -143,7 +144,7 @@ cdv_intel_dp_max_lane_count(struct psb_intel_encoder *encoder) | |||
143 | } | 144 | } |
144 | 145 | ||
145 | static int | 146 | static int |
146 | cdv_intel_dp_max_link_bw(struct psb_intel_encoder *encoder) | 147 | cdv_intel_dp_max_link_bw(struct gma_encoder *encoder) |
147 | { | 148 | { |
148 | struct cdv_intel_dp *intel_dp = encoder->dev_priv; | 149 | struct cdv_intel_dp *intel_dp = encoder->dev_priv; |
149 | int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; | 150 | int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; |
@@ -180,7 +181,7 @@ cdv_intel_dp_max_data_rate(int max_link_clock, int max_lanes) | |||
180 | return (max_link_clock * max_lanes * 19) / 20; | 181 | return (max_link_clock * max_lanes * 19) / 20; |
181 | } | 182 | } |
182 | 183 | ||
183 | static void cdv_intel_edp_panel_vdd_on(struct psb_intel_encoder *intel_encoder) | 184 | static void cdv_intel_edp_panel_vdd_on(struct gma_encoder *intel_encoder) |
184 | { | 185 | { |
185 | struct drm_device *dev = intel_encoder->base.dev; | 186 | struct drm_device *dev = intel_encoder->base.dev; |
186 | struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv; | 187 | struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv; |
@@ -200,7 +201,7 @@ static void cdv_intel_edp_panel_vdd_on(struct psb_intel_encoder *intel_encoder) | |||
200 | msleep(intel_dp->panel_power_up_delay); | 201 | msleep(intel_dp->panel_power_up_delay); |
201 | } | 202 | } |
202 | 203 | ||
203 | static void cdv_intel_edp_panel_vdd_off(struct psb_intel_encoder *intel_encoder) | 204 | static void cdv_intel_edp_panel_vdd_off(struct gma_encoder *intel_encoder) |
204 | { | 205 | { |
205 | struct drm_device *dev = intel_encoder->base.dev; | 206 | struct drm_device *dev = intel_encoder->base.dev; |
206 | u32 pp; | 207 | u32 pp; |
@@ -215,7 +216,7 @@ static void cdv_intel_edp_panel_vdd_off(struct psb_intel_encoder *intel_encoder) | |||
215 | } | 216 | } |
216 | 217 | ||
217 | /* Returns true if the panel was already on when called */ | 218 | /* Returns true if the panel was already on when called */ |
218 | static bool cdv_intel_edp_panel_on(struct psb_intel_encoder *intel_encoder) | 219 | static bool cdv_intel_edp_panel_on(struct gma_encoder *intel_encoder) |
219 | { | 220 | { |
220 | struct drm_device *dev = intel_encoder->base.dev; | 221 | struct drm_device *dev = intel_encoder->base.dev; |
221 | struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv; | 222 | struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv; |
@@ -242,7 +243,7 @@ static bool cdv_intel_edp_panel_on(struct psb_intel_encoder *intel_encoder) | |||
242 | return false; | 243 | return false; |
243 | } | 244 | } |
244 | 245 | ||
245 | static void cdv_intel_edp_panel_off (struct psb_intel_encoder *intel_encoder) | 246 | static void cdv_intel_edp_panel_off (struct gma_encoder *intel_encoder) |
246 | { | 247 | { |
247 | struct drm_device *dev = intel_encoder->base.dev; | 248 | struct drm_device *dev = intel_encoder->base.dev; |
248 | u32 pp, idle_off_mask = PP_ON ; | 249 | u32 pp, idle_off_mask = PP_ON ; |
@@ -274,7 +275,7 @@ static void cdv_intel_edp_panel_off (struct psb_intel_encoder *intel_encoder) | |||
274 | DRM_DEBUG_KMS("Over\n"); | 275 | DRM_DEBUG_KMS("Over\n"); |
275 | } | 276 | } |
276 | 277 | ||
277 | static void cdv_intel_edp_backlight_on (struct psb_intel_encoder *intel_encoder) | 278 | static void cdv_intel_edp_backlight_on (struct gma_encoder *intel_encoder) |
278 | { | 279 | { |
279 | struct drm_device *dev = intel_encoder->base.dev; | 280 | struct drm_device *dev = intel_encoder->base.dev; |
280 | u32 pp; | 281 | u32 pp; |
@@ -294,7 +295,7 @@ static void cdv_intel_edp_backlight_on (struct psb_intel_encoder *intel_encoder) | |||
294 | gma_backlight_enable(dev); | 295 | gma_backlight_enable(dev); |
295 | } | 296 | } |
296 | 297 | ||
297 | static void cdv_intel_edp_backlight_off (struct psb_intel_encoder *intel_encoder) | 298 | static void cdv_intel_edp_backlight_off (struct gma_encoder *intel_encoder) |
298 | { | 299 | { |
299 | struct drm_device *dev = intel_encoder->base.dev; | 300 | struct drm_device *dev = intel_encoder->base.dev; |
300 | struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv; | 301 | struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv; |
@@ -314,7 +315,7 @@ static int | |||
314 | cdv_intel_dp_mode_valid(struct drm_connector *connector, | 315 | cdv_intel_dp_mode_valid(struct drm_connector *connector, |
315 | struct drm_display_mode *mode) | 316 | struct drm_display_mode *mode) |
316 | { | 317 | { |
317 | struct psb_intel_encoder *encoder = psb_intel_attached_encoder(connector); | 318 | struct gma_encoder *encoder = gma_attached_encoder(connector); |
318 | struct cdv_intel_dp *intel_dp = encoder->dev_priv; | 319 | struct cdv_intel_dp *intel_dp = encoder->dev_priv; |
319 | int max_link_clock = cdv_intel_dp_link_clock(cdv_intel_dp_max_link_bw(encoder)); | 320 | int max_link_clock = cdv_intel_dp_link_clock(cdv_intel_dp_max_link_bw(encoder)); |
320 | int max_lanes = cdv_intel_dp_max_lane_count(encoder); | 321 | int max_lanes = cdv_intel_dp_max_lane_count(encoder); |
@@ -370,7 +371,7 @@ unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) | |||
370 | } | 371 | } |
371 | 372 | ||
372 | static int | 373 | static int |
373 | cdv_intel_dp_aux_ch(struct psb_intel_encoder *encoder, | 374 | cdv_intel_dp_aux_ch(struct gma_encoder *encoder, |
374 | uint8_t *send, int send_bytes, | 375 | uint8_t *send, int send_bytes, |
375 | uint8_t *recv, int recv_size) | 376 | uint8_t *recv, int recv_size) |
376 | { | 377 | { |
@@ -472,7 +473,7 @@ cdv_intel_dp_aux_ch(struct psb_intel_encoder *encoder, | |||
472 | 473 | ||
473 | /* Write data to the aux channel in native mode */ | 474 | /* Write data to the aux channel in native mode */ |
474 | static int | 475 | static int |
475 | cdv_intel_dp_aux_native_write(struct psb_intel_encoder *encoder, | 476 | cdv_intel_dp_aux_native_write(struct gma_encoder *encoder, |
476 | uint16_t address, uint8_t *send, int send_bytes) | 477 | uint16_t address, uint8_t *send, int send_bytes) |
477 | { | 478 | { |
478 | int ret; | 479 | int ret; |
@@ -504,7 +505,7 @@ cdv_intel_dp_aux_native_write(struct psb_intel_encoder *encoder, | |||
504 | 505 | ||
505 | /* Write a single byte to the aux channel in native mode */ | 506 | /* Write a single byte to the aux channel in native mode */ |
506 | static int | 507 | static int |
507 | cdv_intel_dp_aux_native_write_1(struct psb_intel_encoder *encoder, | 508 | cdv_intel_dp_aux_native_write_1(struct gma_encoder *encoder, |
508 | uint16_t address, uint8_t byte) | 509 | uint16_t address, uint8_t byte) |
509 | { | 510 | { |
510 | return cdv_intel_dp_aux_native_write(encoder, address, &byte, 1); | 511 | return cdv_intel_dp_aux_native_write(encoder, address, &byte, 1); |
@@ -512,7 +513,7 @@ cdv_intel_dp_aux_native_write_1(struct psb_intel_encoder *encoder, | |||
512 | 513 | ||
513 | /* read bytes from a native aux channel */ | 514 | /* read bytes from a native aux channel */ |
514 | static int | 515 | static int |
515 | cdv_intel_dp_aux_native_read(struct psb_intel_encoder *encoder, | 516 | cdv_intel_dp_aux_native_read(struct gma_encoder *encoder, |
516 | uint16_t address, uint8_t *recv, int recv_bytes) | 517 | uint16_t address, uint8_t *recv, int recv_bytes) |
517 | { | 518 | { |
518 | uint8_t msg[4]; | 519 | uint8_t msg[4]; |
@@ -557,7 +558,7 @@ cdv_intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, | |||
557 | struct cdv_intel_dp *intel_dp = container_of(adapter, | 558 | struct cdv_intel_dp *intel_dp = container_of(adapter, |
558 | struct cdv_intel_dp, | 559 | struct cdv_intel_dp, |
559 | adapter); | 560 | adapter); |
560 | struct psb_intel_encoder *encoder = intel_dp->encoder; | 561 | struct gma_encoder *encoder = intel_dp->encoder; |
561 | uint16_t address = algo_data->address; | 562 | uint16_t address = algo_data->address; |
562 | uint8_t msg[5]; | 563 | uint8_t msg[5]; |
563 | uint8_t reply[2]; | 564 | uint8_t reply[2]; |
@@ -647,7 +648,8 @@ cdv_intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, | |||
647 | } | 648 | } |
648 | 649 | ||
649 | static int | 650 | static int |
650 | cdv_intel_dp_i2c_init(struct psb_intel_connector *connector, struct psb_intel_encoder *encoder, const char *name) | 651 | cdv_intel_dp_i2c_init(struct gma_connector *connector, |
652 | struct gma_encoder *encoder, const char *name) | ||
651 | { | 653 | { |
652 | struct cdv_intel_dp *intel_dp = encoder->dev_priv; | 654 | struct cdv_intel_dp *intel_dp = encoder->dev_priv; |
653 | int ret; | 655 | int ret; |
@@ -698,7 +700,7 @@ cdv_intel_dp_mode_fixup(struct drm_encoder *encoder, const struct drm_display_mo | |||
698 | struct drm_display_mode *adjusted_mode) | 700 | struct drm_display_mode *adjusted_mode) |
699 | { | 701 | { |
700 | struct drm_psb_private *dev_priv = encoder->dev->dev_private; | 702 | struct drm_psb_private *dev_priv = encoder->dev->dev_private; |
701 | struct psb_intel_encoder *intel_encoder = to_psb_intel_encoder(encoder); | 703 | struct gma_encoder *intel_encoder = to_gma_encoder(encoder); |
702 | struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv; | 704 | struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv; |
703 | int lane_count, clock; | 705 | int lane_count, clock; |
704 | int max_lane_count = cdv_intel_dp_max_lane_count(intel_encoder); | 706 | int max_lane_count = cdv_intel_dp_max_lane_count(intel_encoder); |
@@ -792,22 +794,22 @@ cdv_intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, | |||
792 | struct drm_psb_private *dev_priv = dev->dev_private; | 794 | struct drm_psb_private *dev_priv = dev->dev_private; |
793 | struct drm_mode_config *mode_config = &dev->mode_config; | 795 | struct drm_mode_config *mode_config = &dev->mode_config; |
794 | struct drm_encoder *encoder; | 796 | struct drm_encoder *encoder; |
795 | struct psb_intel_crtc *intel_crtc = to_psb_intel_crtc(crtc); | 797 | struct gma_crtc *gma_crtc = to_gma_crtc(crtc); |
796 | int lane_count = 4, bpp = 24; | 798 | int lane_count = 4, bpp = 24; |
797 | struct cdv_intel_dp_m_n m_n; | 799 | struct cdv_intel_dp_m_n m_n; |
798 | int pipe = intel_crtc->pipe; | 800 | int pipe = gma_crtc->pipe; |
799 | 801 | ||
800 | /* | 802 | /* |
801 | * Find the lane count in the intel_encoder private | 803 | * Find the lane count in the intel_encoder private |
802 | */ | 804 | */ |
803 | list_for_each_entry(encoder, &mode_config->encoder_list, head) { | 805 | list_for_each_entry(encoder, &mode_config->encoder_list, head) { |
804 | struct psb_intel_encoder *intel_encoder; | 806 | struct gma_encoder *intel_encoder; |
805 | struct cdv_intel_dp *intel_dp; | 807 | struct cdv_intel_dp *intel_dp; |
806 | 808 | ||
807 | if (encoder->crtc != crtc) | 809 | if (encoder->crtc != crtc) |
808 | continue; | 810 | continue; |
809 | 811 | ||
810 | intel_encoder = to_psb_intel_encoder(encoder); | 812 | intel_encoder = to_gma_encoder(encoder); |
811 | intel_dp = intel_encoder->dev_priv; | 813 | intel_dp = intel_encoder->dev_priv; |
812 | if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) { | 814 | if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) { |
813 | lane_count = intel_dp->lane_count; | 815 | lane_count = intel_dp->lane_count; |
@@ -841,9 +843,9 @@ static void | |||
841 | cdv_intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, | 843 | cdv_intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, |
842 | struct drm_display_mode *adjusted_mode) | 844 | struct drm_display_mode *adjusted_mode) |
843 | { | 845 | { |
844 | struct psb_intel_encoder *intel_encoder = to_psb_intel_encoder(encoder); | 846 | struct gma_encoder *intel_encoder = to_gma_encoder(encoder); |
845 | struct drm_crtc *crtc = encoder->crtc; | 847 | struct drm_crtc *crtc = encoder->crtc; |
846 | struct psb_intel_crtc *intel_crtc = to_psb_intel_crtc(crtc); | 848 | struct gma_crtc *gma_crtc = to_gma_crtc(crtc); |
847 | struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv; | 849 | struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv; |
848 | struct drm_device *dev = encoder->dev; | 850 | struct drm_device *dev = encoder->dev; |
849 | 851 | ||
@@ -885,7 +887,7 @@ cdv_intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode | |||
885 | } | 887 | } |
886 | 888 | ||
887 | /* CPT DP's pipe select is decided in TRANS_DP_CTL */ | 889 | /* CPT DP's pipe select is decided in TRANS_DP_CTL */ |
888 | if (intel_crtc->pipe == 1) | 890 | if (gma_crtc->pipe == 1) |
889 | intel_dp->DP |= DP_PIPEB_SELECT; | 891 | intel_dp->DP |= DP_PIPEB_SELECT; |
890 | 892 | ||
891 | REG_WRITE(intel_dp->output_reg, (intel_dp->DP | DP_PORT_EN)); | 893 | REG_WRITE(intel_dp->output_reg, (intel_dp->DP | DP_PORT_EN)); |
@@ -900,7 +902,7 @@ cdv_intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode | |||
900 | else | 902 | else |
901 | pfit_control = 0; | 903 | pfit_control = 0; |
902 | 904 | ||
903 | pfit_control |= intel_crtc->pipe << PFIT_PIPE_SHIFT; | 905 | pfit_control |= gma_crtc->pipe << PFIT_PIPE_SHIFT; |
904 | 906 | ||
905 | REG_WRITE(PFIT_CONTROL, pfit_control); | 907 | REG_WRITE(PFIT_CONTROL, pfit_control); |
906 | } | 908 | } |
@@ -908,7 +910,7 @@ cdv_intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode | |||
908 | 910 | ||
909 | 911 | ||
910 | /* If the sink supports it, try to set the power state appropriately */ | 912 | /* If the sink supports it, try to set the power state appropriately */ |
911 | static void cdv_intel_dp_sink_dpms(struct psb_intel_encoder *encoder, int mode) | 913 | static void cdv_intel_dp_sink_dpms(struct gma_encoder *encoder, int mode) |
912 | { | 914 | { |
913 | struct cdv_intel_dp *intel_dp = encoder->dev_priv; | 915 | struct cdv_intel_dp *intel_dp = encoder->dev_priv; |
914 | int ret, i; | 916 | int ret, i; |
@@ -940,7 +942,7 @@ static void cdv_intel_dp_sink_dpms(struct psb_intel_encoder *encoder, int mode) | |||
940 | 942 | ||
941 | static void cdv_intel_dp_prepare(struct drm_encoder *encoder) | 943 | static void cdv_intel_dp_prepare(struct drm_encoder *encoder) |
942 | { | 944 | { |
943 | struct psb_intel_encoder *intel_encoder = to_psb_intel_encoder(encoder); | 945 | struct gma_encoder *intel_encoder = to_gma_encoder(encoder); |
944 | int edp = is_edp(intel_encoder); | 946 | int edp = is_edp(intel_encoder); |
945 | 947 | ||
946 | if (edp) { | 948 | if (edp) { |
@@ -957,7 +959,7 @@ static void cdv_intel_dp_prepare(struct drm_encoder *encoder) | |||
957 | 959 | ||
958 | static void cdv_intel_dp_commit(struct drm_encoder *encoder) | 960 | static void cdv_intel_dp_commit(struct drm_encoder *encoder) |
959 | { | 961 | { |
960 | struct psb_intel_encoder *intel_encoder = to_psb_intel_encoder(encoder); | 962 | struct gma_encoder *intel_encoder = to_gma_encoder(encoder); |
961 | int edp = is_edp(intel_encoder); | 963 | int edp = is_edp(intel_encoder); |
962 | 964 | ||
963 | if (edp) | 965 | if (edp) |
@@ -971,7 +973,7 @@ static void cdv_intel_dp_commit(struct drm_encoder *encoder) | |||
971 | static void | 973 | static void |
972 | cdv_intel_dp_dpms(struct drm_encoder *encoder, int mode) | 974 | cdv_intel_dp_dpms(struct drm_encoder *encoder, int mode) |
973 | { | 975 | { |
974 | struct psb_intel_encoder *intel_encoder = to_psb_intel_encoder(encoder); | 976 | struct gma_encoder *intel_encoder = to_gma_encoder(encoder); |
975 | struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv; | 977 | struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv; |
976 | struct drm_device *dev = encoder->dev; | 978 | struct drm_device *dev = encoder->dev; |
977 | uint32_t dp_reg = REG_READ(intel_dp->output_reg); | 979 | uint32_t dp_reg = REG_READ(intel_dp->output_reg); |
@@ -1006,7 +1008,7 @@ cdv_intel_dp_dpms(struct drm_encoder *encoder, int mode) | |||
1006 | * cases where the sink may still be asleep. | 1008 | * cases where the sink may still be asleep. |
1007 | */ | 1009 | */ |
1008 | static bool | 1010 | static bool |
1009 | cdv_intel_dp_aux_native_read_retry(struct psb_intel_encoder *encoder, uint16_t address, | 1011 | cdv_intel_dp_aux_native_read_retry(struct gma_encoder *encoder, uint16_t address, |
1010 | uint8_t *recv, int recv_bytes) | 1012 | uint8_t *recv, int recv_bytes) |
1011 | { | 1013 | { |
1012 | int ret, i; | 1014 | int ret, i; |
@@ -1031,7 +1033,7 @@ cdv_intel_dp_aux_native_read_retry(struct psb_intel_encoder *encoder, uint16_t a | |||
1031 | * link status information | 1033 | * link status information |
1032 | */ | 1034 | */ |
1033 | static bool | 1035 | static bool |
1034 | cdv_intel_dp_get_link_status(struct psb_intel_encoder *encoder) | 1036 | cdv_intel_dp_get_link_status(struct gma_encoder *encoder) |
1035 | { | 1037 | { |
1036 | struct cdv_intel_dp *intel_dp = encoder->dev_priv; | 1038 | struct cdv_intel_dp *intel_dp = encoder->dev_priv; |
1037 | return cdv_intel_dp_aux_native_read_retry(encoder, | 1039 | return cdv_intel_dp_aux_native_read_retry(encoder, |
@@ -1105,7 +1107,7 @@ cdv_intel_dp_pre_emphasis_max(uint8_t voltage_swing) | |||
1105 | } | 1107 | } |
1106 | */ | 1108 | */ |
1107 | static void | 1109 | static void |
1108 | cdv_intel_get_adjust_train(struct psb_intel_encoder *encoder) | 1110 | cdv_intel_get_adjust_train(struct gma_encoder *encoder) |
1109 | { | 1111 | { |
1110 | struct cdv_intel_dp *intel_dp = encoder->dev_priv; | 1112 | struct cdv_intel_dp *intel_dp = encoder->dev_priv; |
1111 | uint8_t v = 0; | 1113 | uint8_t v = 0; |
@@ -1164,7 +1166,7 @@ cdv_intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_c | |||
1164 | DP_LANE_CHANNEL_EQ_DONE|\ | 1166 | DP_LANE_CHANNEL_EQ_DONE|\ |
1165 | DP_LANE_SYMBOL_LOCKED) | 1167 | DP_LANE_SYMBOL_LOCKED) |
1166 | static bool | 1168 | static bool |
1167 | cdv_intel_channel_eq_ok(struct psb_intel_encoder *encoder) | 1169 | cdv_intel_channel_eq_ok(struct gma_encoder *encoder) |
1168 | { | 1170 | { |
1169 | struct cdv_intel_dp *intel_dp = encoder->dev_priv; | 1171 | struct cdv_intel_dp *intel_dp = encoder->dev_priv; |
1170 | uint8_t lane_align; | 1172 | uint8_t lane_align; |
@@ -1184,7 +1186,7 @@ cdv_intel_channel_eq_ok(struct psb_intel_encoder *encoder) | |||
1184 | } | 1186 | } |
1185 | 1187 | ||
1186 | static bool | 1188 | static bool |
1187 | cdv_intel_dp_set_link_train(struct psb_intel_encoder *encoder, | 1189 | cdv_intel_dp_set_link_train(struct gma_encoder *encoder, |
1188 | uint32_t dp_reg_value, | 1190 | uint32_t dp_reg_value, |
1189 | uint8_t dp_train_pat) | 1191 | uint8_t dp_train_pat) |
1190 | { | 1192 | { |
@@ -1211,7 +1213,7 @@ cdv_intel_dp_set_link_train(struct psb_intel_encoder *encoder, | |||
1211 | 1213 | ||
1212 | 1214 | ||
1213 | static bool | 1215 | static bool |
1214 | cdv_intel_dplink_set_level(struct psb_intel_encoder *encoder, | 1216 | cdv_intel_dplink_set_level(struct gma_encoder *encoder, |
1215 | uint8_t dp_train_pat) | 1217 | uint8_t dp_train_pat) |
1216 | { | 1218 | { |
1217 | 1219 | ||
@@ -1232,7 +1234,7 @@ cdv_intel_dplink_set_level(struct psb_intel_encoder *encoder, | |||
1232 | } | 1234 | } |
1233 | 1235 | ||
1234 | static void | 1236 | static void |
1235 | cdv_intel_dp_set_vswing_premph(struct psb_intel_encoder *encoder, uint8_t signal_level) | 1237 | cdv_intel_dp_set_vswing_premph(struct gma_encoder *encoder, uint8_t signal_level) |
1236 | { | 1238 | { |
1237 | struct drm_device *dev = encoder->base.dev; | 1239 | struct drm_device *dev = encoder->base.dev; |
1238 | struct cdv_intel_dp *intel_dp = encoder->dev_priv; | 1240 | struct cdv_intel_dp *intel_dp = encoder->dev_priv; |
@@ -1298,7 +1300,7 @@ cdv_intel_dp_set_vswing_premph(struct psb_intel_encoder *encoder, uint8_t signal | |||
1298 | 1300 | ||
1299 | /* Enable corresponding port and start training pattern 1 */ | 1301 | /* Enable corresponding port and start training pattern 1 */ |
1300 | static void | 1302 | static void |
1301 | cdv_intel_dp_start_link_train(struct psb_intel_encoder *encoder) | 1303 | cdv_intel_dp_start_link_train(struct gma_encoder *encoder) |
1302 | { | 1304 | { |
1303 | struct drm_device *dev = encoder->base.dev; | 1305 | struct drm_device *dev = encoder->base.dev; |
1304 | struct cdv_intel_dp *intel_dp = encoder->dev_priv; | 1306 | struct cdv_intel_dp *intel_dp = encoder->dev_priv; |
@@ -1317,7 +1319,7 @@ cdv_intel_dp_start_link_train(struct psb_intel_encoder *encoder) | |||
1317 | /* Enable output, wait for it to become active */ | 1319 | /* Enable output, wait for it to become active */ |
1318 | REG_WRITE(intel_dp->output_reg, reg); | 1320 | REG_WRITE(intel_dp->output_reg, reg); |
1319 | REG_READ(intel_dp->output_reg); | 1321 | REG_READ(intel_dp->output_reg); |
1320 | psb_intel_wait_for_vblank(dev); | 1322 | gma_wait_for_vblank(dev); |
1321 | 1323 | ||
1322 | DRM_DEBUG_KMS("Link config\n"); | 1324 | DRM_DEBUG_KMS("Link config\n"); |
1323 | /* Write the link configuration data */ | 1325 | /* Write the link configuration data */ |
@@ -1392,7 +1394,7 @@ cdv_intel_dp_start_link_train(struct psb_intel_encoder *encoder) | |||
1392 | } | 1394 | } |
1393 | 1395 | ||
1394 | static void | 1396 | static void |
1395 | cdv_intel_dp_complete_link_train(struct psb_intel_encoder *encoder) | 1397 | cdv_intel_dp_complete_link_train(struct gma_encoder *encoder) |
1396 | { | 1398 | { |
1397 | struct drm_device *dev = encoder->base.dev; | 1399 | struct drm_device *dev = encoder->base.dev; |
1398 | struct cdv_intel_dp *intel_dp = encoder->dev_priv; | 1400 | struct cdv_intel_dp *intel_dp = encoder->dev_priv; |
@@ -1478,7 +1480,7 @@ cdv_intel_dp_complete_link_train(struct psb_intel_encoder *encoder) | |||
1478 | } | 1480 | } |
1479 | 1481 | ||
1480 | static void | 1482 | static void |
1481 | cdv_intel_dp_link_down(struct psb_intel_encoder *encoder) | 1483 | cdv_intel_dp_link_down(struct gma_encoder *encoder) |
1482 | { | 1484 | { |
1483 | struct drm_device *dev = encoder->base.dev; | 1485 | struct drm_device *dev = encoder->base.dev; |
1484 | struct cdv_intel_dp *intel_dp = encoder->dev_priv; | 1486 | struct cdv_intel_dp *intel_dp = encoder->dev_priv; |
@@ -1502,8 +1504,7 @@ cdv_intel_dp_link_down(struct psb_intel_encoder *encoder) | |||
1502 | REG_READ(intel_dp->output_reg); | 1504 | REG_READ(intel_dp->output_reg); |
1503 | } | 1505 | } |
1504 | 1506 | ||
1505 | static enum drm_connector_status | 1507 | static enum drm_connector_status cdv_dp_detect(struct gma_encoder *encoder) |
1506 | cdv_dp_detect(struct psb_intel_encoder *encoder) | ||
1507 | { | 1508 | { |
1508 | struct cdv_intel_dp *intel_dp = encoder->dev_priv; | 1509 | struct cdv_intel_dp *intel_dp = encoder->dev_priv; |
1509 | enum drm_connector_status status; | 1510 | enum drm_connector_status status; |
@@ -1531,7 +1532,7 @@ cdv_dp_detect(struct psb_intel_encoder *encoder) | |||
1531 | static enum drm_connector_status | 1532 | static enum drm_connector_status |
1532 | cdv_intel_dp_detect(struct drm_connector *connector, bool force) | 1533 | cdv_intel_dp_detect(struct drm_connector *connector, bool force) |
1533 | { | 1534 | { |
1534 | struct psb_intel_encoder *encoder = psb_intel_attached_encoder(connector); | 1535 | struct gma_encoder *encoder = gma_attached_encoder(connector); |
1535 | struct cdv_intel_dp *intel_dp = encoder->dev_priv; | 1536 | struct cdv_intel_dp *intel_dp = encoder->dev_priv; |
1536 | enum drm_connector_status status; | 1537 | enum drm_connector_status status; |
1537 | struct edid *edid = NULL; | 1538 | struct edid *edid = NULL; |
@@ -1565,7 +1566,7 @@ cdv_intel_dp_detect(struct drm_connector *connector, bool force) | |||
1565 | 1566 | ||
1566 | static int cdv_intel_dp_get_modes(struct drm_connector *connector) | 1567 | static int cdv_intel_dp_get_modes(struct drm_connector *connector) |
1567 | { | 1568 | { |
1568 | struct psb_intel_encoder *intel_encoder = psb_intel_attached_encoder(connector); | 1569 | struct gma_encoder *intel_encoder = gma_attached_encoder(connector); |
1569 | struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv; | 1570 | struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv; |
1570 | struct edid *edid = NULL; | 1571 | struct edid *edid = NULL; |
1571 | int ret = 0; | 1572 | int ret = 0; |
@@ -1621,7 +1622,7 @@ static int cdv_intel_dp_get_modes(struct drm_connector *connector) | |||
1621 | static bool | 1622 | static bool |
1622 | cdv_intel_dp_detect_audio(struct drm_connector *connector) | 1623 | cdv_intel_dp_detect_audio(struct drm_connector *connector) |
1623 | { | 1624 | { |
1624 | struct psb_intel_encoder *encoder = psb_intel_attached_encoder(connector); | 1625 | struct gma_encoder *encoder = gma_attached_encoder(connector); |
1625 | struct cdv_intel_dp *intel_dp = encoder->dev_priv; | 1626 | struct cdv_intel_dp *intel_dp = encoder->dev_priv; |
1626 | struct edid *edid; | 1627 | struct edid *edid; |
1627 | bool has_audio = false; | 1628 | bool has_audio = false; |
@@ -1647,7 +1648,7 @@ cdv_intel_dp_set_property(struct drm_connector *connector, | |||
1647 | uint64_t val) | 1648 | uint64_t val) |
1648 | { | 1649 | { |
1649 | struct drm_psb_private *dev_priv = connector->dev->dev_private; | 1650 | struct drm_psb_private *dev_priv = connector->dev->dev_private; |
1650 | struct psb_intel_encoder *encoder = psb_intel_attached_encoder(connector); | 1651 | struct gma_encoder *encoder = gma_attached_encoder(connector); |
1651 | struct cdv_intel_dp *intel_dp = encoder->dev_priv; | 1652 | struct cdv_intel_dp *intel_dp = encoder->dev_priv; |
1652 | int ret; | 1653 | int ret; |
1653 | 1654 | ||
@@ -1700,11 +1701,10 @@ done: | |||
1700 | static void | 1701 | static void |
1701 | cdv_intel_dp_destroy(struct drm_connector *connector) | 1702 | cdv_intel_dp_destroy(struct drm_connector *connector) |
1702 | { | 1703 | { |
1703 | struct psb_intel_encoder *psb_intel_encoder = | 1704 | struct gma_encoder *gma_encoder = gma_attached_encoder(connector); |
1704 | psb_intel_attached_encoder(connector); | 1705 | struct cdv_intel_dp *intel_dp = gma_encoder->dev_priv; |
1705 | struct cdv_intel_dp *intel_dp = psb_intel_encoder->dev_priv; | ||
1706 | 1706 | ||
1707 | if (is_edp(psb_intel_encoder)) { | 1707 | if (is_edp(gma_encoder)) { |
1708 | /* cdv_intel_panel_destroy_backlight(connector->dev); */ | 1708 | /* cdv_intel_panel_destroy_backlight(connector->dev); */ |
1709 | if (intel_dp->panel_fixed_mode) { | 1709 | if (intel_dp->panel_fixed_mode) { |
1710 | kfree(intel_dp->panel_fixed_mode); | 1710 | kfree(intel_dp->panel_fixed_mode); |
@@ -1741,7 +1741,7 @@ static const struct drm_connector_funcs cdv_intel_dp_connector_funcs = { | |||
1741 | static const struct drm_connector_helper_funcs cdv_intel_dp_connector_helper_funcs = { | 1741 | static const struct drm_connector_helper_funcs cdv_intel_dp_connector_helper_funcs = { |
1742 | .get_modes = cdv_intel_dp_get_modes, | 1742 | .get_modes = cdv_intel_dp_get_modes, |
1743 | .mode_valid = cdv_intel_dp_mode_valid, | 1743 | .mode_valid = cdv_intel_dp_mode_valid, |
1744 | .best_encoder = psb_intel_best_encoder, | 1744 | .best_encoder = gma_best_encoder, |
1745 | }; | 1745 | }; |
1746 | 1746 | ||
1747 | static const struct drm_encoder_funcs cdv_intel_dp_enc_funcs = { | 1747 | static const struct drm_encoder_funcs cdv_intel_dp_enc_funcs = { |
@@ -1800,19 +1800,19 @@ static void cdv_disable_intel_clock_gating(struct drm_device *dev) | |||
1800 | void | 1800 | void |
1801 | cdv_intel_dp_init(struct drm_device *dev, struct psb_intel_mode_device *mode_dev, int output_reg) | 1801 | cdv_intel_dp_init(struct drm_device *dev, struct psb_intel_mode_device *mode_dev, int output_reg) |
1802 | { | 1802 | { |
1803 | struct psb_intel_encoder *psb_intel_encoder; | 1803 | struct gma_encoder *gma_encoder; |
1804 | struct psb_intel_connector *psb_intel_connector; | 1804 | struct gma_connector *gma_connector; |
1805 | struct drm_connector *connector; | 1805 | struct drm_connector *connector; |
1806 | struct drm_encoder *encoder; | 1806 | struct drm_encoder *encoder; |
1807 | struct cdv_intel_dp *intel_dp; | 1807 | struct cdv_intel_dp *intel_dp; |
1808 | const char *name = NULL; | 1808 | const char *name = NULL; |
1809 | int type = DRM_MODE_CONNECTOR_DisplayPort; | 1809 | int type = DRM_MODE_CONNECTOR_DisplayPort; |
1810 | 1810 | ||
1811 | psb_intel_encoder = kzalloc(sizeof(struct psb_intel_encoder), GFP_KERNEL); | 1811 | gma_encoder = kzalloc(sizeof(struct gma_encoder), GFP_KERNEL); |
1812 | if (!psb_intel_encoder) | 1812 | if (!gma_encoder) |
1813 | return; | 1813 | return; |
1814 | psb_intel_connector = kzalloc(sizeof(struct psb_intel_connector), GFP_KERNEL); | 1814 | gma_connector = kzalloc(sizeof(struct gma_connector), GFP_KERNEL); |
1815 | if (!psb_intel_connector) | 1815 | if (!gma_connector) |
1816 | goto err_connector; | 1816 | goto err_connector; |
1817 | intel_dp = kzalloc(sizeof(struct cdv_intel_dp), GFP_KERNEL); | 1817 | intel_dp = kzalloc(sizeof(struct cdv_intel_dp), GFP_KERNEL); |
1818 | if (!intel_dp) | 1818 | if (!intel_dp) |
@@ -1821,22 +1821,22 @@ cdv_intel_dp_init(struct drm_device *dev, struct psb_intel_mode_device *mode_dev | |||
1821 | if ((output_reg == DP_C) && cdv_intel_dpc_is_edp(dev)) | 1821 | if ((output_reg == DP_C) && cdv_intel_dpc_is_edp(dev)) |
1822 | type = DRM_MODE_CONNECTOR_eDP; | 1822 | type = DRM_MODE_CONNECTOR_eDP; |
1823 | 1823 | ||
1824 | connector = &psb_intel_connector->base; | 1824 | connector = &gma_connector->base; |
1825 | encoder = &psb_intel_encoder->base; | 1825 | encoder = &gma_encoder->base; |
1826 | 1826 | ||
1827 | drm_connector_init(dev, connector, &cdv_intel_dp_connector_funcs, type); | 1827 | drm_connector_init(dev, connector, &cdv_intel_dp_connector_funcs, type); |
1828 | drm_encoder_init(dev, encoder, &cdv_intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS); | 1828 | drm_encoder_init(dev, encoder, &cdv_intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS); |
1829 | 1829 | ||
1830 | psb_intel_connector_attach_encoder(psb_intel_connector, psb_intel_encoder); | 1830 | gma_connector_attach_encoder(gma_connector, gma_encoder); |
1831 | 1831 | ||
1832 | if (type == DRM_MODE_CONNECTOR_DisplayPort) | 1832 | if (type == DRM_MODE_CONNECTOR_DisplayPort) |
1833 | psb_intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; | 1833 | gma_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
1834 | else | 1834 | else |
1835 | psb_intel_encoder->type = INTEL_OUTPUT_EDP; | 1835 | gma_encoder->type = INTEL_OUTPUT_EDP; |
1836 | 1836 | ||
1837 | 1837 | ||
1838 | psb_intel_encoder->dev_priv=intel_dp; | 1838 | gma_encoder->dev_priv=intel_dp; |
1839 | intel_dp->encoder = psb_intel_encoder; | 1839 | intel_dp->encoder = gma_encoder; |
1840 | intel_dp->output_reg = output_reg; | 1840 | intel_dp->output_reg = output_reg; |
1841 | 1841 | ||
1842 | drm_encoder_helper_add(encoder, &cdv_intel_dp_helper_funcs); | 1842 | drm_encoder_helper_add(encoder, &cdv_intel_dp_helper_funcs); |
@@ -1852,21 +1852,21 @@ cdv_intel_dp_init(struct drm_device *dev, struct psb_intel_mode_device *mode_dev | |||
1852 | switch (output_reg) { | 1852 | switch (output_reg) { |
1853 | case DP_B: | 1853 | case DP_B: |
1854 | name = "DPDDC-B"; | 1854 | name = "DPDDC-B"; |
1855 | psb_intel_encoder->ddi_select = (DP_MASK | DDI0_SELECT); | 1855 | gma_encoder->ddi_select = (DP_MASK | DDI0_SELECT); |
1856 | break; | 1856 | break; |
1857 | case DP_C: | 1857 | case DP_C: |
1858 | name = "DPDDC-C"; | 1858 | name = "DPDDC-C"; |
1859 | psb_intel_encoder->ddi_select = (DP_MASK | DDI1_SELECT); | 1859 | gma_encoder->ddi_select = (DP_MASK | DDI1_SELECT); |
1860 | break; | 1860 | break; |
1861 | } | 1861 | } |
1862 | 1862 | ||
1863 | cdv_disable_intel_clock_gating(dev); | 1863 | cdv_disable_intel_clock_gating(dev); |
1864 | 1864 | ||
1865 | cdv_intel_dp_i2c_init(psb_intel_connector, psb_intel_encoder, name); | 1865 | cdv_intel_dp_i2c_init(gma_connector, gma_encoder, name); |
1866 | /* FIXME:fail check */ | 1866 | /* FIXME:fail check */ |
1867 | cdv_intel_dp_add_properties(connector); | 1867 | cdv_intel_dp_add_properties(connector); |
1868 | 1868 | ||
1869 | if (is_edp(psb_intel_encoder)) { | 1869 | if (is_edp(gma_encoder)) { |
1870 | int ret; | 1870 | int ret; |
1871 | struct edp_power_seq cur; | 1871 | struct edp_power_seq cur; |
1872 | u32 pp_on, pp_off, pp_div; | 1872 | u32 pp_on, pp_off, pp_div; |
@@ -1920,11 +1920,11 @@ cdv_intel_dp_init(struct drm_device *dev, struct psb_intel_mode_device *mode_dev | |||
1920 | intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); | 1920 | intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); |
1921 | 1921 | ||
1922 | 1922 | ||
1923 | cdv_intel_edp_panel_vdd_on(psb_intel_encoder); | 1923 | cdv_intel_edp_panel_vdd_on(gma_encoder); |
1924 | ret = cdv_intel_dp_aux_native_read(psb_intel_encoder, DP_DPCD_REV, | 1924 | ret = cdv_intel_dp_aux_native_read(gma_encoder, DP_DPCD_REV, |
1925 | intel_dp->dpcd, | 1925 | intel_dp->dpcd, |
1926 | sizeof(intel_dp->dpcd)); | 1926 | sizeof(intel_dp->dpcd)); |
1927 | cdv_intel_edp_panel_vdd_off(psb_intel_encoder); | 1927 | cdv_intel_edp_panel_vdd_off(gma_encoder); |
1928 | if (ret == 0) { | 1928 | if (ret == 0) { |
1929 | /* if this fails, presume the device is a ghost */ | 1929 | /* if this fails, presume the device is a ghost */ |
1930 | DRM_INFO("failed to retrieve link info, disabling eDP\n"); | 1930 | DRM_INFO("failed to retrieve link info, disabling eDP\n"); |
@@ -1945,7 +1945,7 @@ cdv_intel_dp_init(struct drm_device *dev, struct psb_intel_mode_device *mode_dev | |||
1945 | return; | 1945 | return; |
1946 | 1946 | ||
1947 | err_priv: | 1947 | err_priv: |
1948 | kfree(psb_intel_connector); | 1948 | kfree(gma_connector); |
1949 | err_connector: | 1949 | err_connector: |
1950 | kfree(psb_intel_encoder); | 1950 | kfree(gma_encoder); |
1951 | } | 1951 | } |
diff --git a/drivers/gpu/drm/gma500/cdv_intel_hdmi.c b/drivers/gpu/drm/gma500/cdv_intel_hdmi.c index 464153d9d2df..1c0d723b8d24 100644 --- a/drivers/gpu/drm/gma500/cdv_intel_hdmi.c +++ b/drivers/gpu/drm/gma500/cdv_intel_hdmi.c | |||
@@ -64,11 +64,11 @@ static void cdv_hdmi_mode_set(struct drm_encoder *encoder, | |||
64 | struct drm_display_mode *adjusted_mode) | 64 | struct drm_display_mode *adjusted_mode) |
65 | { | 65 | { |
66 | struct drm_device *dev = encoder->dev; | 66 | struct drm_device *dev = encoder->dev; |
67 | struct psb_intel_encoder *psb_intel_encoder = to_psb_intel_encoder(encoder); | 67 | struct gma_encoder *gma_encoder = to_gma_encoder(encoder); |
68 | struct mid_intel_hdmi_priv *hdmi_priv = psb_intel_encoder->dev_priv; | 68 | struct mid_intel_hdmi_priv *hdmi_priv = gma_encoder->dev_priv; |
69 | u32 hdmib; | 69 | u32 hdmib; |
70 | struct drm_crtc *crtc = encoder->crtc; | 70 | struct drm_crtc *crtc = encoder->crtc; |
71 | struct psb_intel_crtc *intel_crtc = to_psb_intel_crtc(crtc); | 71 | struct gma_crtc *gma_crtc = to_gma_crtc(crtc); |
72 | 72 | ||
73 | hdmib = (2 << 10); | 73 | hdmib = (2 << 10); |
74 | 74 | ||
@@ -77,7 +77,7 @@ static void cdv_hdmi_mode_set(struct drm_encoder *encoder, | |||
77 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | 77 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
78 | hdmib |= HDMI_HSYNC_ACTIVE_HIGH; | 78 | hdmib |= HDMI_HSYNC_ACTIVE_HIGH; |
79 | 79 | ||
80 | if (intel_crtc->pipe == 1) | 80 | if (gma_crtc->pipe == 1) |
81 | hdmib |= HDMIB_PIPE_B_SELECT; | 81 | hdmib |= HDMIB_PIPE_B_SELECT; |
82 | 82 | ||
83 | if (hdmi_priv->has_hdmi_audio) { | 83 | if (hdmi_priv->has_hdmi_audio) { |
@@ -99,9 +99,8 @@ static bool cdv_hdmi_mode_fixup(struct drm_encoder *encoder, | |||
99 | static void cdv_hdmi_dpms(struct drm_encoder *encoder, int mode) | 99 | static void cdv_hdmi_dpms(struct drm_encoder *encoder, int mode) |
100 | { | 100 | { |
101 | struct drm_device *dev = encoder->dev; | 101 | struct drm_device *dev = encoder->dev; |
102 | struct psb_intel_encoder *psb_intel_encoder = | 102 | struct gma_encoder *gma_encoder = to_gma_encoder(encoder); |
103 | to_psb_intel_encoder(encoder); | 103 | struct mid_intel_hdmi_priv *hdmi_priv = gma_encoder->dev_priv; |
104 | struct mid_intel_hdmi_priv *hdmi_priv = psb_intel_encoder->dev_priv; | ||
105 | u32 hdmib; | 104 | u32 hdmib; |
106 | 105 | ||
107 | hdmib = REG_READ(hdmi_priv->hdmi_reg); | 106 | hdmib = REG_READ(hdmi_priv->hdmi_reg); |
@@ -116,9 +115,8 @@ static void cdv_hdmi_dpms(struct drm_encoder *encoder, int mode) | |||
116 | static void cdv_hdmi_save(struct drm_connector *connector) | 115 | static void cdv_hdmi_save(struct drm_connector *connector) |
117 | { | 116 | { |
118 | struct drm_device *dev = connector->dev; | 117 | struct drm_device *dev = connector->dev; |
119 | struct psb_intel_encoder *psb_intel_encoder = | 118 | struct gma_encoder *gma_encoder = gma_attached_encoder(connector); |
120 | psb_intel_attached_encoder(connector); | 119 | struct mid_intel_hdmi_priv *hdmi_priv = gma_encoder->dev_priv; |
121 | struct mid_intel_hdmi_priv *hdmi_priv = psb_intel_encoder->dev_priv; | ||
122 | 120 | ||
123 | hdmi_priv->save_HDMIB = REG_READ(hdmi_priv->hdmi_reg); | 121 | hdmi_priv->save_HDMIB = REG_READ(hdmi_priv->hdmi_reg); |
124 | } | 122 | } |
@@ -126,9 +124,8 @@ static void cdv_hdmi_save(struct drm_connector *connector) | |||
126 | static void cdv_hdmi_restore(struct drm_connector *connector) | 124 | static void cdv_hdmi_restore(struct drm_connector *connector) |
127 | { | 125 | { |
128 | struct drm_device *dev = connector->dev; | 126 | struct drm_device *dev = connector->dev; |
129 | struct psb_intel_encoder *psb_intel_encoder = | 127 | struct gma_encoder *gma_encoder = gma_attached_encoder(connector); |
130 | psb_intel_attached_encoder(connector); | 128 | struct mid_intel_hdmi_priv *hdmi_priv = gma_encoder->dev_priv; |
131 | struct mid_intel_hdmi_priv *hdmi_priv = psb_intel_encoder->dev_priv; | ||
132 | 129 | ||
133 | REG_WRITE(hdmi_priv->hdmi_reg, hdmi_priv->save_HDMIB); | 130 | REG_WRITE(hdmi_priv->hdmi_reg, hdmi_priv->save_HDMIB); |
134 | REG_READ(hdmi_priv->hdmi_reg); | 131 | REG_READ(hdmi_priv->hdmi_reg); |
@@ -137,13 +134,12 @@ static void cdv_hdmi_restore(struct drm_connector *connector) | |||
137 | static enum drm_connector_status cdv_hdmi_detect( | 134 | static enum drm_connector_status cdv_hdmi_detect( |
138 | struct drm_connector *connector, bool force) | 135 | struct drm_connector *connector, bool force) |
139 | { | 136 | { |
140 | struct psb_intel_encoder *psb_intel_encoder = | 137 | struct gma_encoder *gma_encoder = gma_attached_encoder(connector); |
141 | psb_intel_attached_encoder(connector); | 138 | struct mid_intel_hdmi_priv *hdmi_priv = gma_encoder->dev_priv; |
142 | struct mid_intel_hdmi_priv *hdmi_priv = psb_intel_encoder->dev_priv; | ||
143 | struct edid *edid = NULL; | 139 | struct edid *edid = NULL; |
144 | enum drm_connector_status status = connector_status_disconnected; | 140 | enum drm_connector_status status = connector_status_disconnected; |
145 | 141 | ||
146 | edid = drm_get_edid(connector, &psb_intel_encoder->i2c_bus->adapter); | 142 | edid = drm_get_edid(connector, &gma_encoder->i2c_bus->adapter); |
147 | 143 | ||
148 | hdmi_priv->has_hdmi_sink = false; | 144 | hdmi_priv->has_hdmi_sink = false; |
149 | hdmi_priv->has_hdmi_audio = false; | 145 | hdmi_priv->has_hdmi_audio = false; |
@@ -167,7 +163,7 @@ static int cdv_hdmi_set_property(struct drm_connector *connector, | |||
167 | struct drm_encoder *encoder = connector->encoder; | 163 | struct drm_encoder *encoder = connector->encoder; |
168 | 164 | ||
169 | if (!strcmp(property->name, "scaling mode") && encoder) { | 165 | if (!strcmp(property->name, "scaling mode") && encoder) { |
170 | struct psb_intel_crtc *crtc = to_psb_intel_crtc(encoder->crtc); | 166 | struct gma_crtc *crtc = to_gma_crtc(encoder->crtc); |
171 | bool centre; | 167 | bool centre; |
172 | uint64_t curValue; | 168 | uint64_t curValue; |
173 | 169 | ||
@@ -221,12 +217,11 @@ static int cdv_hdmi_set_property(struct drm_connector *connector, | |||
221 | */ | 217 | */ |
222 | static int cdv_hdmi_get_modes(struct drm_connector *connector) | 218 | static int cdv_hdmi_get_modes(struct drm_connector *connector) |
223 | { | 219 | { |
224 | struct psb_intel_encoder *psb_intel_encoder = | 220 | struct gma_encoder *gma_encoder = gma_attached_encoder(connector); |
225 | psb_intel_attached_encoder(connector); | ||
226 | struct edid *edid = NULL; | 221 | struct edid *edid = NULL; |
227 | int ret = 0; | 222 | int ret = 0; |
228 | 223 | ||
229 | edid = drm_get_edid(connector, &psb_intel_encoder->i2c_bus->adapter); | 224 | edid = drm_get_edid(connector, &gma_encoder->i2c_bus->adapter); |
230 | if (edid) { | 225 | if (edid) { |
231 | drm_mode_connector_update_edid_property(connector, edid); | 226 | drm_mode_connector_update_edid_property(connector, edid); |
232 | ret = drm_add_edid_modes(connector, edid); | 227 | ret = drm_add_edid_modes(connector, edid); |
@@ -256,11 +251,10 @@ static int cdv_hdmi_mode_valid(struct drm_connector *connector, | |||
256 | 251 | ||
257 | static void cdv_hdmi_destroy(struct drm_connector *connector) | 252 | static void cdv_hdmi_destroy(struct drm_connector *connector) |
258 | { | 253 | { |
259 | struct psb_intel_encoder *psb_intel_encoder = | 254 | struct gma_encoder *gma_encoder = gma_attached_encoder(connector); |
260 | psb_intel_attached_encoder(connector); | ||
261 | 255 | ||
262 | if (psb_intel_encoder->i2c_bus) | 256 | if (gma_encoder->i2c_bus) |
263 | psb_intel_i2c_destroy(psb_intel_encoder->i2c_bus); | 257 | psb_intel_i2c_destroy(gma_encoder->i2c_bus); |
264 | drm_sysfs_connector_remove(connector); | 258 | drm_sysfs_connector_remove(connector); |
265 | drm_connector_cleanup(connector); | 259 | drm_connector_cleanup(connector); |
266 | kfree(connector); | 260 | kfree(connector); |
@@ -269,16 +263,16 @@ static void cdv_hdmi_destroy(struct drm_connector *connector) | |||
269 | static const struct drm_encoder_helper_funcs cdv_hdmi_helper_funcs = { | 263 | static const struct drm_encoder_helper_funcs cdv_hdmi_helper_funcs = { |
270 | .dpms = cdv_hdmi_dpms, | 264 | .dpms = cdv_hdmi_dpms, |
271 | .mode_fixup = cdv_hdmi_mode_fixup, | 265 | .mode_fixup = cdv_hdmi_mode_fixup, |
272 | .prepare = psb_intel_encoder_prepare, | 266 | .prepare = gma_encoder_prepare, |
273 | .mode_set = cdv_hdmi_mode_set, | 267 | .mode_set = cdv_hdmi_mode_set, |
274 | .commit = psb_intel_encoder_commit, | 268 | .commit = gma_encoder_commit, |
275 | }; | 269 | }; |
276 | 270 | ||
277 | static const struct drm_connector_helper_funcs | 271 | static const struct drm_connector_helper_funcs |
278 | cdv_hdmi_connector_helper_funcs = { | 272 | cdv_hdmi_connector_helper_funcs = { |
279 | .get_modes = cdv_hdmi_get_modes, | 273 | .get_modes = cdv_hdmi_get_modes, |
280 | .mode_valid = cdv_hdmi_mode_valid, | 274 | .mode_valid = cdv_hdmi_mode_valid, |
281 | .best_encoder = psb_intel_best_encoder, | 275 | .best_encoder = gma_best_encoder, |
282 | }; | 276 | }; |
283 | 277 | ||
284 | static const struct drm_connector_funcs cdv_hdmi_connector_funcs = { | 278 | static const struct drm_connector_funcs cdv_hdmi_connector_funcs = { |
@@ -294,23 +288,22 @@ static const struct drm_connector_funcs cdv_hdmi_connector_funcs = { | |||
294 | void cdv_hdmi_init(struct drm_device *dev, | 288 | void cdv_hdmi_init(struct drm_device *dev, |
295 | struct psb_intel_mode_device *mode_dev, int reg) | 289 | struct psb_intel_mode_device *mode_dev, int reg) |
296 | { | 290 | { |
297 | struct psb_intel_encoder *psb_intel_encoder; | 291 | struct gma_encoder *gma_encoder; |
298 | struct psb_intel_connector *psb_intel_connector; | 292 | struct gma_connector *gma_connector; |
299 | struct drm_connector *connector; | 293 | struct drm_connector *connector; |
300 | struct drm_encoder *encoder; | 294 | struct drm_encoder *encoder; |
301 | struct mid_intel_hdmi_priv *hdmi_priv; | 295 | struct mid_intel_hdmi_priv *hdmi_priv; |
302 | int ddc_bus; | 296 | int ddc_bus; |
303 | 297 | ||
304 | psb_intel_encoder = kzalloc(sizeof(struct psb_intel_encoder), | 298 | gma_encoder = kzalloc(sizeof(struct gma_encoder), GFP_KERNEL); |
305 | GFP_KERNEL); | ||
306 | 299 | ||
307 | if (!psb_intel_encoder) | 300 | if (!gma_encoder) |
308 | return; | 301 | return; |
309 | 302 | ||
310 | psb_intel_connector = kzalloc(sizeof(struct psb_intel_connector), | 303 | gma_connector = kzalloc(sizeof(struct gma_connector), |
311 | GFP_KERNEL); | 304 | GFP_KERNEL); |
312 | 305 | ||
313 | if (!psb_intel_connector) | 306 | if (!gma_connector) |
314 | goto err_connector; | 307 | goto err_connector; |
315 | 308 | ||
316 | hdmi_priv = kzalloc(sizeof(struct mid_intel_hdmi_priv), GFP_KERNEL); | 309 | hdmi_priv = kzalloc(sizeof(struct mid_intel_hdmi_priv), GFP_KERNEL); |
@@ -318,9 +311,9 @@ void cdv_hdmi_init(struct drm_device *dev, | |||
318 | if (!hdmi_priv) | 311 | if (!hdmi_priv) |
319 | goto err_priv; | 312 | goto err_priv; |
320 | 313 | ||
321 | connector = &psb_intel_connector->base; | 314 | connector = &gma_connector->base; |
322 | connector->polled = DRM_CONNECTOR_POLL_HPD; | 315 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
323 | encoder = &psb_intel_encoder->base; | 316 | encoder = &gma_encoder->base; |
324 | drm_connector_init(dev, connector, | 317 | drm_connector_init(dev, connector, |
325 | &cdv_hdmi_connector_funcs, | 318 | &cdv_hdmi_connector_funcs, |
326 | DRM_MODE_CONNECTOR_DVID); | 319 | DRM_MODE_CONNECTOR_DVID); |
@@ -328,12 +321,11 @@ void cdv_hdmi_init(struct drm_device *dev, | |||
328 | drm_encoder_init(dev, encoder, &psb_intel_lvds_enc_funcs, | 321 | drm_encoder_init(dev, encoder, &psb_intel_lvds_enc_funcs, |
329 | DRM_MODE_ENCODER_TMDS); | 322 | DRM_MODE_ENCODER_TMDS); |
330 | 323 | ||
331 | psb_intel_connector_attach_encoder(psb_intel_connector, | 324 | gma_connector_attach_encoder(gma_connector, gma_encoder); |
332 | psb_intel_encoder); | 325 | gma_encoder->type = INTEL_OUTPUT_HDMI; |
333 | psb_intel_encoder->type = INTEL_OUTPUT_HDMI; | ||
334 | hdmi_priv->hdmi_reg = reg; | 326 | hdmi_priv->hdmi_reg = reg; |
335 | hdmi_priv->has_hdmi_sink = false; | 327 | hdmi_priv->has_hdmi_sink = false; |
336 | psb_intel_encoder->dev_priv = hdmi_priv; | 328 | gma_encoder->dev_priv = hdmi_priv; |
337 | 329 | ||
338 | drm_encoder_helper_add(encoder, &cdv_hdmi_helper_funcs); | 330 | drm_encoder_helper_add(encoder, &cdv_hdmi_helper_funcs); |
339 | drm_connector_helper_add(connector, | 331 | drm_connector_helper_add(connector, |
@@ -349,11 +341,11 @@ void cdv_hdmi_init(struct drm_device *dev, | |||
349 | switch (reg) { | 341 | switch (reg) { |
350 | case SDVOB: | 342 | case SDVOB: |
351 | ddc_bus = GPIOE; | 343 | ddc_bus = GPIOE; |
352 | psb_intel_encoder->ddi_select = DDI0_SELECT; | 344 | gma_encoder->ddi_select = DDI0_SELECT; |
353 | break; | 345 | break; |
354 | case SDVOC: | 346 | case SDVOC: |
355 | ddc_bus = GPIOD; | 347 | ddc_bus = GPIOD; |
356 | psb_intel_encoder->ddi_select = DDI1_SELECT; | 348 | gma_encoder->ddi_select = DDI1_SELECT; |
357 | break; | 349 | break; |
358 | default: | 350 | default: |
359 | DRM_ERROR("unknown reg 0x%x for HDMI\n", reg); | 351 | DRM_ERROR("unknown reg 0x%x for HDMI\n", reg); |
@@ -361,16 +353,15 @@ void cdv_hdmi_init(struct drm_device *dev, | |||
361 | break; | 353 | break; |
362 | } | 354 | } |
363 | 355 | ||
364 | psb_intel_encoder->i2c_bus = psb_intel_i2c_create(dev, | 356 | gma_encoder->i2c_bus = psb_intel_i2c_create(dev, |
365 | ddc_bus, (reg == SDVOB) ? "HDMIB" : "HDMIC"); | 357 | ddc_bus, (reg == SDVOB) ? "HDMIB" : "HDMIC"); |
366 | 358 | ||
367 | if (!psb_intel_encoder->i2c_bus) { | 359 | if (!gma_encoder->i2c_bus) { |
368 | dev_err(dev->dev, "No ddc adapter available!\n"); | 360 | dev_err(dev->dev, "No ddc adapter available!\n"); |
369 | goto failed_ddc; | 361 | goto failed_ddc; |
370 | } | 362 | } |
371 | 363 | ||
372 | hdmi_priv->hdmi_i2c_adapter = | 364 | hdmi_priv->hdmi_i2c_adapter = &(gma_encoder->i2c_bus->adapter); |
373 | &(psb_intel_encoder->i2c_bus->adapter); | ||
374 | hdmi_priv->dev = dev; | 365 | hdmi_priv->dev = dev; |
375 | drm_sysfs_connector_add(connector); | 366 | drm_sysfs_connector_add(connector); |
376 | return; | 367 | return; |
@@ -379,7 +370,7 @@ failed_ddc: | |||
379 | drm_encoder_cleanup(encoder); | 370 | drm_encoder_cleanup(encoder); |
380 | drm_connector_cleanup(connector); | 371 | drm_connector_cleanup(connector); |
381 | err_priv: | 372 | err_priv: |
382 | kfree(psb_intel_connector); | 373 | kfree(gma_connector); |
383 | err_connector: | 374 | err_connector: |
384 | kfree(psb_intel_encoder); | 375 | kfree(gma_encoder); |
385 | } | 376 | } |
diff --git a/drivers/gpu/drm/gma500/cdv_intel_lvds.c b/drivers/gpu/drm/gma500/cdv_intel_lvds.c index d81dbc3368f0..20e08e65d46c 100644 --- a/drivers/gpu/drm/gma500/cdv_intel_lvds.c +++ b/drivers/gpu/drm/gma500/cdv_intel_lvds.c | |||
@@ -356,8 +356,7 @@ static void cdv_intel_lvds_mode_set(struct drm_encoder *encoder, | |||
356 | { | 356 | { |
357 | struct drm_device *dev = encoder->dev; | 357 | struct drm_device *dev = encoder->dev; |
358 | struct drm_psb_private *dev_priv = dev->dev_private; | 358 | struct drm_psb_private *dev_priv = dev->dev_private; |
359 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc( | 359 | struct gma_crtc *gma_crtc = to_gma_crtc(encoder->crtc); |
360 | encoder->crtc); | ||
361 | u32 pfit_control; | 360 | u32 pfit_control; |
362 | 361 | ||
363 | /* | 362 | /* |
@@ -379,7 +378,7 @@ static void cdv_intel_lvds_mode_set(struct drm_encoder *encoder, | |||
379 | else | 378 | else |
380 | pfit_control = 0; | 379 | pfit_control = 0; |
381 | 380 | ||
382 | pfit_control |= psb_intel_crtc->pipe << PFIT_PIPE_SHIFT; | 381 | pfit_control |= gma_crtc->pipe << PFIT_PIPE_SHIFT; |
383 | 382 | ||
384 | if (dev_priv->lvds_dither) | 383 | if (dev_priv->lvds_dither) |
385 | pfit_control |= PANEL_8TO6_DITHER_ENABLE; | 384 | pfit_control |= PANEL_8TO6_DITHER_ENABLE; |
@@ -407,12 +406,11 @@ static int cdv_intel_lvds_get_modes(struct drm_connector *connector) | |||
407 | { | 406 | { |
408 | struct drm_device *dev = connector->dev; | 407 | struct drm_device *dev = connector->dev; |
409 | struct drm_psb_private *dev_priv = dev->dev_private; | 408 | struct drm_psb_private *dev_priv = dev->dev_private; |
410 | struct psb_intel_encoder *psb_intel_encoder = | 409 | struct gma_encoder *gma_encoder = gma_attached_encoder(connector); |
411 | psb_intel_attached_encoder(connector); | ||
412 | struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev; | 410 | struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev; |
413 | int ret; | 411 | int ret; |
414 | 412 | ||
415 | ret = psb_intel_ddc_get_modes(connector, &psb_intel_encoder->i2c_bus->adapter); | 413 | ret = psb_intel_ddc_get_modes(connector, &gma_encoder->i2c_bus->adapter); |
416 | 414 | ||
417 | if (ret) | 415 | if (ret) |
418 | return ret; | 416 | return ret; |
@@ -444,11 +442,10 @@ static int cdv_intel_lvds_get_modes(struct drm_connector *connector) | |||
444 | */ | 442 | */ |
445 | static void cdv_intel_lvds_destroy(struct drm_connector *connector) | 443 | static void cdv_intel_lvds_destroy(struct drm_connector *connector) |
446 | { | 444 | { |
447 | struct psb_intel_encoder *psb_intel_encoder = | 445 | struct gma_encoder *gma_encoder = gma_attached_encoder(connector); |
448 | psb_intel_attached_encoder(connector); | ||
449 | 446 | ||
450 | if (psb_intel_encoder->i2c_bus) | 447 | if (gma_encoder->i2c_bus) |
451 | psb_intel_i2c_destroy(psb_intel_encoder->i2c_bus); | 448 | psb_intel_i2c_destroy(gma_encoder->i2c_bus); |
452 | drm_sysfs_connector_remove(connector); | 449 | drm_sysfs_connector_remove(connector); |
453 | drm_connector_cleanup(connector); | 450 | drm_connector_cleanup(connector); |
454 | kfree(connector); | 451 | kfree(connector); |
@@ -461,8 +458,7 @@ static int cdv_intel_lvds_set_property(struct drm_connector *connector, | |||
461 | struct drm_encoder *encoder = connector->encoder; | 458 | struct drm_encoder *encoder = connector->encoder; |
462 | 459 | ||
463 | if (!strcmp(property->name, "scaling mode") && encoder) { | 460 | if (!strcmp(property->name, "scaling mode") && encoder) { |
464 | struct psb_intel_crtc *crtc = | 461 | struct gma_crtc *crtc = to_gma_crtc(encoder->crtc); |
465 | to_psb_intel_crtc(encoder->crtc); | ||
466 | uint64_t curValue; | 462 | uint64_t curValue; |
467 | 463 | ||
468 | if (!crtc) | 464 | if (!crtc) |
@@ -529,7 +525,7 @@ static const struct drm_connector_helper_funcs | |||
529 | cdv_intel_lvds_connector_helper_funcs = { | 525 | cdv_intel_lvds_connector_helper_funcs = { |
530 | .get_modes = cdv_intel_lvds_get_modes, | 526 | .get_modes = cdv_intel_lvds_get_modes, |
531 | .mode_valid = cdv_intel_lvds_mode_valid, | 527 | .mode_valid = cdv_intel_lvds_mode_valid, |
532 | .best_encoder = psb_intel_best_encoder, | 528 | .best_encoder = gma_best_encoder, |
533 | }; | 529 | }; |
534 | 530 | ||
535 | static const struct drm_connector_funcs cdv_intel_lvds_connector_funcs = { | 531 | static const struct drm_connector_funcs cdv_intel_lvds_connector_funcs = { |
@@ -612,8 +608,8 @@ static bool lvds_is_present_in_vbt(struct drm_device *dev, | |||
612 | void cdv_intel_lvds_init(struct drm_device *dev, | 608 | void cdv_intel_lvds_init(struct drm_device *dev, |
613 | struct psb_intel_mode_device *mode_dev) | 609 | struct psb_intel_mode_device *mode_dev) |
614 | { | 610 | { |
615 | struct psb_intel_encoder *psb_intel_encoder; | 611 | struct gma_encoder *gma_encoder; |
616 | struct psb_intel_connector *psb_intel_connector; | 612 | struct gma_connector *gma_connector; |
617 | struct cdv_intel_lvds_priv *lvds_priv; | 613 | struct cdv_intel_lvds_priv *lvds_priv; |
618 | struct drm_connector *connector; | 614 | struct drm_connector *connector; |
619 | struct drm_encoder *encoder; | 615 | struct drm_encoder *encoder; |
@@ -630,24 +626,24 @@ void cdv_intel_lvds_init(struct drm_device *dev, | |||
630 | return; | 626 | return; |
631 | } | 627 | } |
632 | 628 | ||
633 | psb_intel_encoder = kzalloc(sizeof(struct psb_intel_encoder), | 629 | gma_encoder = kzalloc(sizeof(struct gma_encoder), |
634 | GFP_KERNEL); | 630 | GFP_KERNEL); |
635 | if (!psb_intel_encoder) | 631 | if (!gma_encoder) |
636 | return; | 632 | return; |
637 | 633 | ||
638 | psb_intel_connector = kzalloc(sizeof(struct psb_intel_connector), | 634 | gma_connector = kzalloc(sizeof(struct gma_connector), |
639 | GFP_KERNEL); | 635 | GFP_KERNEL); |
640 | if (!psb_intel_connector) | 636 | if (!gma_connector) |
641 | goto failed_connector; | 637 | goto failed_connector; |
642 | 638 | ||
643 | lvds_priv = kzalloc(sizeof(struct cdv_intel_lvds_priv), GFP_KERNEL); | 639 | lvds_priv = kzalloc(sizeof(struct cdv_intel_lvds_priv), GFP_KERNEL); |
644 | if (!lvds_priv) | 640 | if (!lvds_priv) |
645 | goto failed_lvds_priv; | 641 | goto failed_lvds_priv; |
646 | 642 | ||
647 | psb_intel_encoder->dev_priv = lvds_priv; | 643 | gma_encoder->dev_priv = lvds_priv; |
648 | 644 | ||
649 | connector = &psb_intel_connector->base; | 645 | connector = &gma_connector->base; |
650 | encoder = &psb_intel_encoder->base; | 646 | encoder = &gma_encoder->base; |
651 | 647 | ||
652 | 648 | ||
653 | drm_connector_init(dev, connector, | 649 | drm_connector_init(dev, connector, |
@@ -659,9 +655,8 @@ void cdv_intel_lvds_init(struct drm_device *dev, | |||
659 | DRM_MODE_ENCODER_LVDS); | 655 | DRM_MODE_ENCODER_LVDS); |
660 | 656 | ||
661 | 657 | ||
662 | psb_intel_connector_attach_encoder(psb_intel_connector, | 658 | gma_connector_attach_encoder(gma_connector, gma_encoder); |
663 | psb_intel_encoder); | 659 | gma_encoder->type = INTEL_OUTPUT_LVDS; |
664 | psb_intel_encoder->type = INTEL_OUTPUT_LVDS; | ||
665 | 660 | ||
666 | drm_encoder_helper_add(encoder, &cdv_intel_lvds_helper_funcs); | 661 | drm_encoder_helper_add(encoder, &cdv_intel_lvds_helper_funcs); |
667 | drm_connector_helper_add(connector, | 662 | drm_connector_helper_add(connector, |
@@ -682,16 +677,16 @@ void cdv_intel_lvds_init(struct drm_device *dev, | |||
682 | * Set up I2C bus | 677 | * Set up I2C bus |
683 | * FIXME: distroy i2c_bus when exit | 678 | * FIXME: distroy i2c_bus when exit |
684 | */ | 679 | */ |
685 | psb_intel_encoder->i2c_bus = psb_intel_i2c_create(dev, | 680 | gma_encoder->i2c_bus = psb_intel_i2c_create(dev, |
686 | GPIOB, | 681 | GPIOB, |
687 | "LVDSBLC_B"); | 682 | "LVDSBLC_B"); |
688 | if (!psb_intel_encoder->i2c_bus) { | 683 | if (!gma_encoder->i2c_bus) { |
689 | dev_printk(KERN_ERR, | 684 | dev_printk(KERN_ERR, |
690 | &dev->pdev->dev, "I2C bus registration failed.\n"); | 685 | &dev->pdev->dev, "I2C bus registration failed.\n"); |
691 | goto failed_blc_i2c; | 686 | goto failed_blc_i2c; |
692 | } | 687 | } |
693 | psb_intel_encoder->i2c_bus->slave_addr = 0x2C; | 688 | gma_encoder->i2c_bus->slave_addr = 0x2C; |
694 | dev_priv->lvds_i2c_bus = psb_intel_encoder->i2c_bus; | 689 | dev_priv->lvds_i2c_bus = gma_encoder->i2c_bus; |
695 | 690 | ||
696 | /* | 691 | /* |
697 | * LVDS discovery: | 692 | * LVDS discovery: |
@@ -704,10 +699,10 @@ void cdv_intel_lvds_init(struct drm_device *dev, | |||
704 | */ | 699 | */ |
705 | 700 | ||
706 | /* Set up the DDC bus. */ | 701 | /* Set up the DDC bus. */ |
707 | psb_intel_encoder->ddc_bus = psb_intel_i2c_create(dev, | 702 | gma_encoder->ddc_bus = psb_intel_i2c_create(dev, |
708 | GPIOC, | 703 | GPIOC, |
709 | "LVDSDDC_C"); | 704 | "LVDSDDC_C"); |
710 | if (!psb_intel_encoder->ddc_bus) { | 705 | if (!gma_encoder->ddc_bus) { |
711 | dev_printk(KERN_ERR, &dev->pdev->dev, | 706 | dev_printk(KERN_ERR, &dev->pdev->dev, |
712 | "DDC bus registration " "failed.\n"); | 707 | "DDC bus registration " "failed.\n"); |
713 | goto failed_ddc; | 708 | goto failed_ddc; |
@@ -718,7 +713,7 @@ void cdv_intel_lvds_init(struct drm_device *dev, | |||
718 | * preferred mode is the right one. | 713 | * preferred mode is the right one. |
719 | */ | 714 | */ |
720 | psb_intel_ddc_get_modes(connector, | 715 | psb_intel_ddc_get_modes(connector, |
721 | &psb_intel_encoder->ddc_bus->adapter); | 716 | &gma_encoder->ddc_bus->adapter); |
722 | list_for_each_entry(scan, &connector->probed_modes, head) { | 717 | list_for_each_entry(scan, &connector->probed_modes, head) { |
723 | if (scan->type & DRM_MODE_TYPE_PREFERRED) { | 718 | if (scan->type & DRM_MODE_TYPE_PREFERRED) { |
724 | mode_dev->panel_fixed_mode = | 719 | mode_dev->panel_fixed_mode = |
@@ -782,19 +777,19 @@ out: | |||
782 | 777 | ||
783 | failed_find: | 778 | failed_find: |
784 | printk(KERN_ERR "Failed find\n"); | 779 | printk(KERN_ERR "Failed find\n"); |
785 | if (psb_intel_encoder->ddc_bus) | 780 | if (gma_encoder->ddc_bus) |
786 | psb_intel_i2c_destroy(psb_intel_encoder->ddc_bus); | 781 | psb_intel_i2c_destroy(gma_encoder->ddc_bus); |
787 | failed_ddc: | 782 | failed_ddc: |
788 | printk(KERN_ERR "Failed DDC\n"); | 783 | printk(KERN_ERR "Failed DDC\n"); |
789 | if (psb_intel_encoder->i2c_bus) | 784 | if (gma_encoder->i2c_bus) |
790 | psb_intel_i2c_destroy(psb_intel_encoder->i2c_bus); | 785 | psb_intel_i2c_destroy(gma_encoder->i2c_bus); |
791 | failed_blc_i2c: | 786 | failed_blc_i2c: |
792 | printk(KERN_ERR "Failed BLC\n"); | 787 | printk(KERN_ERR "Failed BLC\n"); |
793 | drm_encoder_cleanup(encoder); | 788 | drm_encoder_cleanup(encoder); |
794 | drm_connector_cleanup(connector); | 789 | drm_connector_cleanup(connector); |
795 | kfree(lvds_priv); | 790 | kfree(lvds_priv); |
796 | failed_lvds_priv: | 791 | failed_lvds_priv: |
797 | kfree(psb_intel_connector); | 792 | kfree(gma_connector); |
798 | failed_connector: | 793 | failed_connector: |
799 | kfree(psb_intel_encoder); | 794 | kfree(gma_encoder); |
800 | } | 795 | } |
diff --git a/drivers/gpu/drm/gma500/framebuffer.c b/drivers/gpu/drm/gma500/framebuffer.c index 362dd2ad286f..01dd7d225762 100644 --- a/drivers/gpu/drm/gma500/framebuffer.c +++ b/drivers/gpu/drm/gma500/framebuffer.c | |||
@@ -520,21 +520,21 @@ static struct drm_framebuffer *psb_user_framebuffer_create | |||
520 | static void psbfb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, | 520 | static void psbfb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, |
521 | u16 blue, int regno) | 521 | u16 blue, int regno) |
522 | { | 522 | { |
523 | struct psb_intel_crtc *intel_crtc = to_psb_intel_crtc(crtc); | 523 | struct gma_crtc *gma_crtc = to_gma_crtc(crtc); |
524 | 524 | ||
525 | intel_crtc->lut_r[regno] = red >> 8; | 525 | gma_crtc->lut_r[regno] = red >> 8; |
526 | intel_crtc->lut_g[regno] = green >> 8; | 526 | gma_crtc->lut_g[regno] = green >> 8; |
527 | intel_crtc->lut_b[regno] = blue >> 8; | 527 | gma_crtc->lut_b[regno] = blue >> 8; |
528 | } | 528 | } |
529 | 529 | ||
530 | static void psbfb_gamma_get(struct drm_crtc *crtc, u16 *red, | 530 | static void psbfb_gamma_get(struct drm_crtc *crtc, u16 *red, |
531 | u16 *green, u16 *blue, int regno) | 531 | u16 *green, u16 *blue, int regno) |
532 | { | 532 | { |
533 | struct psb_intel_crtc *intel_crtc = to_psb_intel_crtc(crtc); | 533 | struct gma_crtc *gma_crtc = to_gma_crtc(crtc); |
534 | 534 | ||
535 | *red = intel_crtc->lut_r[regno] << 8; | 535 | *red = gma_crtc->lut_r[regno] << 8; |
536 | *green = intel_crtc->lut_g[regno] << 8; | 536 | *green = gma_crtc->lut_g[regno] << 8; |
537 | *blue = intel_crtc->lut_b[regno] << 8; | 537 | *blue = gma_crtc->lut_b[regno] << 8; |
538 | } | 538 | } |
539 | 539 | ||
540 | static int psbfb_probe(struct drm_fb_helper *helper, | 540 | static int psbfb_probe(struct drm_fb_helper *helper, |
@@ -703,13 +703,12 @@ static void psb_setup_outputs(struct drm_device *dev) | |||
703 | 703 | ||
704 | list_for_each_entry(connector, &dev->mode_config.connector_list, | 704 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
705 | head) { | 705 | head) { |
706 | struct psb_intel_encoder *psb_intel_encoder = | 706 | struct gma_encoder *gma_encoder = gma_attached_encoder(connector); |
707 | psb_intel_attached_encoder(connector); | 707 | struct drm_encoder *encoder = &gma_encoder->base; |
708 | struct drm_encoder *encoder = &psb_intel_encoder->base; | ||
709 | int crtc_mask = 0, clone_mask = 0; | 708 | int crtc_mask = 0, clone_mask = 0; |
710 | 709 | ||
711 | /* valid crtcs */ | 710 | /* valid crtcs */ |
712 | switch (psb_intel_encoder->type) { | 711 | switch (gma_encoder->type) { |
713 | case INTEL_OUTPUT_ANALOG: | 712 | case INTEL_OUTPUT_ANALOG: |
714 | crtc_mask = (1 << 0); | 713 | crtc_mask = (1 << 0); |
715 | clone_mask = (1 << INTEL_OUTPUT_ANALOG); | 714 | clone_mask = (1 << INTEL_OUTPUT_ANALOG); |
@@ -744,7 +743,7 @@ static void psb_setup_outputs(struct drm_device *dev) | |||
744 | } | 743 | } |
745 | encoder->possible_crtcs = crtc_mask; | 744 | encoder->possible_crtcs = crtc_mask; |
746 | encoder->possible_clones = | 745 | encoder->possible_clones = |
747 | psb_intel_connector_clones(dev, clone_mask); | 746 | gma_connector_clones(dev, clone_mask); |
748 | } | 747 | } |
749 | } | 748 | } |
750 | 749 | ||
diff --git a/drivers/gpu/drm/gma500/framebuffer.h b/drivers/gpu/drm/gma500/framebuffer.h index 989558a9e6ee..395f20b07aab 100644 --- a/drivers/gpu/drm/gma500/framebuffer.h +++ b/drivers/gpu/drm/gma500/framebuffer.h | |||
@@ -41,7 +41,7 @@ struct psb_fbdev { | |||
41 | 41 | ||
42 | #define to_psb_fb(x) container_of(x, struct psb_framebuffer, base) | 42 | #define to_psb_fb(x) container_of(x, struct psb_framebuffer, base) |
43 | 43 | ||
44 | extern int psb_intel_connector_clones(struct drm_device *dev, int type_mask); | 44 | extern int gma_connector_clones(struct drm_device *dev, int type_mask); |
45 | 45 | ||
46 | #endif | 46 | #endif |
47 | 47 | ||
diff --git a/drivers/gpu/drm/gma500/gma_display.c b/drivers/gpu/drm/gma500/gma_display.c new file mode 100644 index 000000000000..24e8af3d22bf --- /dev/null +++ b/drivers/gpu/drm/gma500/gma_display.c | |||
@@ -0,0 +1,776 @@ | |||
1 | /* | ||
2 | * Copyright © 2006-2011 Intel Corporation | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License along with | ||
14 | * this program; if not, write to the Free Software Foundation, Inc., | ||
15 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | ||
16 | * | ||
17 | * Authors: | ||
18 | * Eric Anholt <eric@anholt.net> | ||
19 | * Patrik Jakobsson <patrik.r.jakobsson@gmail.com> | ||
20 | */ | ||
21 | |||
22 | #include <drm/drmP.h> | ||
23 | #include "gma_display.h" | ||
24 | #include "psb_intel_drv.h" | ||
25 | #include "psb_intel_reg.h" | ||
26 | #include "psb_drv.h" | ||
27 | #include "framebuffer.h" | ||
28 | |||
29 | /** | ||
30 | * Returns whether any output on the specified pipe is of the specified type | ||
31 | */ | ||
32 | bool gma_pipe_has_type(struct drm_crtc *crtc, int type) | ||
33 | { | ||
34 | struct drm_device *dev = crtc->dev; | ||
35 | struct drm_mode_config *mode_config = &dev->mode_config; | ||
36 | struct drm_connector *l_entry; | ||
37 | |||
38 | list_for_each_entry(l_entry, &mode_config->connector_list, head) { | ||
39 | if (l_entry->encoder && l_entry->encoder->crtc == crtc) { | ||
40 | struct gma_encoder *gma_encoder = | ||
41 | gma_attached_encoder(l_entry); | ||
42 | if (gma_encoder->type == type) | ||
43 | return true; | ||
44 | } | ||
45 | } | ||
46 | |||
47 | return false; | ||
48 | } | ||
49 | |||
50 | void gma_wait_for_vblank(struct drm_device *dev) | ||
51 | { | ||
52 | /* Wait for 20ms, i.e. one cycle at 50hz. */ | ||
53 | mdelay(20); | ||
54 | } | ||
55 | |||
56 | int gma_pipe_set_base(struct drm_crtc *crtc, int x, int y, | ||
57 | struct drm_framebuffer *old_fb) | ||
58 | { | ||
59 | struct drm_device *dev = crtc->dev; | ||
60 | struct drm_psb_private *dev_priv = dev->dev_private; | ||
61 | struct gma_crtc *gma_crtc = to_gma_crtc(crtc); | ||
62 | struct psb_framebuffer *psbfb = to_psb_fb(crtc->fb); | ||
63 | int pipe = gma_crtc->pipe; | ||
64 | const struct psb_offset *map = &dev_priv->regmap[pipe]; | ||
65 | unsigned long start, offset; | ||
66 | u32 dspcntr; | ||
67 | int ret = 0; | ||
68 | |||
69 | if (!gma_power_begin(dev, true)) | ||
70 | return 0; | ||
71 | |||
72 | /* no fb bound */ | ||
73 | if (!crtc->fb) { | ||
74 | dev_err(dev->dev, "No FB bound\n"); | ||
75 | goto gma_pipe_cleaner; | ||
76 | } | ||
77 | |||
78 | /* We are displaying this buffer, make sure it is actually loaded | ||
79 | into the GTT */ | ||
80 | ret = psb_gtt_pin(psbfb->gtt); | ||
81 | if (ret < 0) | ||
82 | goto gma_pipe_set_base_exit; | ||
83 | start = psbfb->gtt->offset; | ||
84 | offset = y * crtc->fb->pitches[0] + x * (crtc->fb->bits_per_pixel / 8); | ||
85 | |||
86 | REG_WRITE(map->stride, crtc->fb->pitches[0]); | ||
87 | |||
88 | dspcntr = REG_READ(map->cntr); | ||
89 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | ||
90 | |||
91 | switch (crtc->fb->bits_per_pixel) { | ||
92 | case 8: | ||
93 | dspcntr |= DISPPLANE_8BPP; | ||
94 | break; | ||
95 | case 16: | ||
96 | if (crtc->fb->depth == 15) | ||
97 | dspcntr |= DISPPLANE_15_16BPP; | ||
98 | else | ||
99 | dspcntr |= DISPPLANE_16BPP; | ||
100 | break; | ||
101 | case 24: | ||
102 | case 32: | ||
103 | dspcntr |= DISPPLANE_32BPP_NO_ALPHA; | ||
104 | break; | ||
105 | default: | ||
106 | dev_err(dev->dev, "Unknown color depth\n"); | ||
107 | ret = -EINVAL; | ||
108 | goto gma_pipe_set_base_exit; | ||
109 | } | ||
110 | REG_WRITE(map->cntr, dspcntr); | ||
111 | |||
112 | dev_dbg(dev->dev, | ||
113 | "Writing base %08lX %08lX %d %d\n", start, offset, x, y); | ||
114 | |||
115 | /* FIXME: Investigate whether this really is the base for psb and why | ||
116 | the linear offset is named base for the other chips. map->surf | ||
117 | should be the base and map->linoff the offset for all chips */ | ||
118 | if (IS_PSB(dev)) { | ||
119 | REG_WRITE(map->base, offset + start); | ||
120 | REG_READ(map->base); | ||
121 | } else { | ||
122 | REG_WRITE(map->base, offset); | ||
123 | REG_READ(map->base); | ||
124 | REG_WRITE(map->surf, start); | ||
125 | REG_READ(map->surf); | ||
126 | } | ||
127 | |||
128 | gma_pipe_cleaner: | ||
129 | /* If there was a previous display we can now unpin it */ | ||
130 | if (old_fb) | ||
131 | psb_gtt_unpin(to_psb_fb(old_fb)->gtt); | ||
132 | |||
133 | gma_pipe_set_base_exit: | ||
134 | gma_power_end(dev); | ||
135 | return ret; | ||
136 | } | ||
137 | |||
138 | /* Loads the palette/gamma unit for the CRTC with the prepared values */ | ||
139 | void gma_crtc_load_lut(struct drm_crtc *crtc) | ||
140 | { | ||
141 | struct drm_device *dev = crtc->dev; | ||
142 | struct drm_psb_private *dev_priv = dev->dev_private; | ||
143 | struct gma_crtc *gma_crtc = to_gma_crtc(crtc); | ||
144 | const struct psb_offset *map = &dev_priv->regmap[gma_crtc->pipe]; | ||
145 | int palreg = map->palette; | ||
146 | int i; | ||
147 | |||
148 | /* The clocks have to be on to load the palette. */ | ||
149 | if (!crtc->enabled) | ||
150 | return; | ||
151 | |||
152 | if (gma_power_begin(dev, false)) { | ||
153 | for (i = 0; i < 256; i++) { | ||
154 | REG_WRITE(palreg + 4 * i, | ||
155 | ((gma_crtc->lut_r[i] + | ||
156 | gma_crtc->lut_adj[i]) << 16) | | ||
157 | ((gma_crtc->lut_g[i] + | ||
158 | gma_crtc->lut_adj[i]) << 8) | | ||
159 | (gma_crtc->lut_b[i] + | ||
160 | gma_crtc->lut_adj[i])); | ||
161 | } | ||
162 | gma_power_end(dev); | ||
163 | } else { | ||
164 | for (i = 0; i < 256; i++) { | ||
165 | /* FIXME: Why pipe[0] and not pipe[..._crtc->pipe]? */ | ||
166 | dev_priv->regs.pipe[0].palette[i] = | ||
167 | ((gma_crtc->lut_r[i] + | ||
168 | gma_crtc->lut_adj[i]) << 16) | | ||
169 | ((gma_crtc->lut_g[i] + | ||
170 | gma_crtc->lut_adj[i]) << 8) | | ||
171 | (gma_crtc->lut_b[i] + | ||
172 | gma_crtc->lut_adj[i]); | ||
173 | } | ||
174 | |||
175 | } | ||
176 | } | ||
177 | |||
178 | void gma_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, u16 *blue, | ||
179 | u32 start, u32 size) | ||
180 | { | ||
181 | struct gma_crtc *gma_crtc = to_gma_crtc(crtc); | ||
182 | int i; | ||
183 | int end = (start + size > 256) ? 256 : start + size; | ||
184 | |||
185 | for (i = start; i < end; i++) { | ||
186 | gma_crtc->lut_r[i] = red[i] >> 8; | ||
187 | gma_crtc->lut_g[i] = green[i] >> 8; | ||
188 | gma_crtc->lut_b[i] = blue[i] >> 8; | ||
189 | } | ||
190 | |||
191 | gma_crtc_load_lut(crtc); | ||
192 | } | ||
193 | |||
194 | /** | ||
195 | * Sets the power management mode of the pipe and plane. | ||
196 | * | ||
197 | * This code should probably grow support for turning the cursor off and back | ||
198 | * on appropriately at the same time as we're turning the pipe off/on. | ||
199 | */ | ||
200 | void gma_crtc_dpms(struct drm_crtc *crtc, int mode) | ||
201 | { | ||
202 | struct drm_device *dev = crtc->dev; | ||
203 | struct drm_psb_private *dev_priv = dev->dev_private; | ||
204 | struct gma_crtc *gma_crtc = to_gma_crtc(crtc); | ||
205 | int pipe = gma_crtc->pipe; | ||
206 | const struct psb_offset *map = &dev_priv->regmap[pipe]; | ||
207 | u32 temp; | ||
208 | |||
209 | /* XXX: When our outputs are all unaware of DPMS modes other than off | ||
210 | * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. | ||
211 | */ | ||
212 | |||
213 | if (IS_CDV(dev)) | ||
214 | dev_priv->ops->disable_sr(dev); | ||
215 | |||
216 | switch (mode) { | ||
217 | case DRM_MODE_DPMS_ON: | ||
218 | case DRM_MODE_DPMS_STANDBY: | ||
219 | case DRM_MODE_DPMS_SUSPEND: | ||
220 | if (gma_crtc->active) | ||
221 | break; | ||
222 | |||
223 | gma_crtc->active = true; | ||
224 | |||
225 | /* Enable the DPLL */ | ||
226 | temp = REG_READ(map->dpll); | ||
227 | if ((temp & DPLL_VCO_ENABLE) == 0) { | ||
228 | REG_WRITE(map->dpll, temp); | ||
229 | REG_READ(map->dpll); | ||
230 | /* Wait for the clocks to stabilize. */ | ||
231 | udelay(150); | ||
232 | REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); | ||
233 | REG_READ(map->dpll); | ||
234 | /* Wait for the clocks to stabilize. */ | ||
235 | udelay(150); | ||
236 | REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); | ||
237 | REG_READ(map->dpll); | ||
238 | /* Wait for the clocks to stabilize. */ | ||
239 | udelay(150); | ||
240 | } | ||
241 | |||
242 | /* Enable the plane */ | ||
243 | temp = REG_READ(map->cntr); | ||
244 | if ((temp & DISPLAY_PLANE_ENABLE) == 0) { | ||
245 | REG_WRITE(map->cntr, | ||
246 | temp | DISPLAY_PLANE_ENABLE); | ||
247 | /* Flush the plane changes */ | ||
248 | REG_WRITE(map->base, REG_READ(map->base)); | ||
249 | } | ||
250 | |||
251 | udelay(150); | ||
252 | |||
253 | /* Enable the pipe */ | ||
254 | temp = REG_READ(map->conf); | ||
255 | if ((temp & PIPEACONF_ENABLE) == 0) | ||
256 | REG_WRITE(map->conf, temp | PIPEACONF_ENABLE); | ||
257 | |||
258 | temp = REG_READ(map->status); | ||
259 | temp &= ~(0xFFFF); | ||
260 | temp |= PIPE_FIFO_UNDERRUN; | ||
261 | REG_WRITE(map->status, temp); | ||
262 | REG_READ(map->status); | ||
263 | |||
264 | gma_crtc_load_lut(crtc); | ||
265 | |||
266 | /* Give the overlay scaler a chance to enable | ||
267 | * if it's on this pipe */ | ||
268 | /* psb_intel_crtc_dpms_video(crtc, true); TODO */ | ||
269 | break; | ||
270 | case DRM_MODE_DPMS_OFF: | ||
271 | if (!gma_crtc->active) | ||
272 | break; | ||
273 | |||
274 | gma_crtc->active = false; | ||
275 | |||
276 | /* Give the overlay scaler a chance to disable | ||
277 | * if it's on this pipe */ | ||
278 | /* psb_intel_crtc_dpms_video(crtc, FALSE); TODO */ | ||
279 | |||
280 | /* Disable the VGA plane that we never use */ | ||
281 | REG_WRITE(VGACNTRL, VGA_DISP_DISABLE); | ||
282 | |||
283 | /* Turn off vblank interrupts */ | ||
284 | drm_vblank_off(dev, pipe); | ||
285 | |||
286 | /* Wait for vblank for the disable to take effect */ | ||
287 | gma_wait_for_vblank(dev); | ||
288 | |||
289 | /* Disable plane */ | ||
290 | temp = REG_READ(map->cntr); | ||
291 | if ((temp & DISPLAY_PLANE_ENABLE) != 0) { | ||
292 | REG_WRITE(map->cntr, | ||
293 | temp & ~DISPLAY_PLANE_ENABLE); | ||
294 | /* Flush the plane changes */ | ||
295 | REG_WRITE(map->base, REG_READ(map->base)); | ||
296 | REG_READ(map->base); | ||
297 | } | ||
298 | |||
299 | /* Disable pipe */ | ||
300 | temp = REG_READ(map->conf); | ||
301 | if ((temp & PIPEACONF_ENABLE) != 0) { | ||
302 | REG_WRITE(map->conf, temp & ~PIPEACONF_ENABLE); | ||
303 | REG_READ(map->conf); | ||
304 | } | ||
305 | |||
306 | /* Wait for vblank for the disable to take effect. */ | ||
307 | gma_wait_for_vblank(dev); | ||
308 | |||
309 | udelay(150); | ||
310 | |||
311 | /* Disable DPLL */ | ||
312 | temp = REG_READ(map->dpll); | ||
313 | if ((temp & DPLL_VCO_ENABLE) != 0) { | ||
314 | REG_WRITE(map->dpll, temp & ~DPLL_VCO_ENABLE); | ||
315 | REG_READ(map->dpll); | ||
316 | } | ||
317 | |||
318 | /* Wait for the clocks to turn off. */ | ||
319 | udelay(150); | ||
320 | break; | ||
321 | } | ||
322 | |||
323 | if (IS_CDV(dev)) | ||
324 | dev_priv->ops->update_wm(dev, crtc); | ||
325 | |||
326 | /* Set FIFO watermarks */ | ||
327 | REG_WRITE(DSPARB, 0x3F3E); | ||
328 | } | ||
329 | |||
330 | int gma_crtc_cursor_set(struct drm_crtc *crtc, | ||
331 | struct drm_file *file_priv, | ||
332 | uint32_t handle, | ||
333 | uint32_t width, uint32_t height) | ||
334 | { | ||
335 | struct drm_device *dev = crtc->dev; | ||
336 | struct drm_psb_private *dev_priv = dev->dev_private; | ||
337 | struct gma_crtc *gma_crtc = to_gma_crtc(crtc); | ||
338 | int pipe = gma_crtc->pipe; | ||
339 | uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR; | ||
340 | uint32_t base = (pipe == 0) ? CURABASE : CURBBASE; | ||
341 | uint32_t temp; | ||
342 | size_t addr = 0; | ||
343 | struct gtt_range *gt; | ||
344 | struct gtt_range *cursor_gt = gma_crtc->cursor_gt; | ||
345 | struct drm_gem_object *obj; | ||
346 | void *tmp_dst, *tmp_src; | ||
347 | int ret = 0, i, cursor_pages; | ||
348 | |||
349 | /* If we didn't get a handle then turn the cursor off */ | ||
350 | if (!handle) { | ||
351 | temp = CURSOR_MODE_DISABLE; | ||
352 | |||
353 | if (gma_power_begin(dev, false)) { | ||
354 | REG_WRITE(control, temp); | ||
355 | REG_WRITE(base, 0); | ||
356 | gma_power_end(dev); | ||
357 | } | ||
358 | |||
359 | /* Unpin the old GEM object */ | ||
360 | if (gma_crtc->cursor_obj) { | ||
361 | gt = container_of(gma_crtc->cursor_obj, | ||
362 | struct gtt_range, gem); | ||
363 | psb_gtt_unpin(gt); | ||
364 | drm_gem_object_unreference(gma_crtc->cursor_obj); | ||
365 | gma_crtc->cursor_obj = NULL; | ||
366 | } | ||
367 | |||
368 | return 0; | ||
369 | } | ||
370 | |||
371 | /* Currently we only support 64x64 cursors */ | ||
372 | if (width != 64 || height != 64) { | ||
373 | dev_dbg(dev->dev, "We currently only support 64x64 cursors\n"); | ||
374 | return -EINVAL; | ||
375 | } | ||
376 | |||
377 | obj = drm_gem_object_lookup(dev, file_priv, handle); | ||
378 | if (!obj) | ||
379 | return -ENOENT; | ||
380 | |||
381 | if (obj->size < width * height * 4) { | ||
382 | dev_dbg(dev->dev, "Buffer is too small\n"); | ||
383 | ret = -ENOMEM; | ||
384 | goto unref_cursor; | ||
385 | } | ||
386 | |||
387 | gt = container_of(obj, struct gtt_range, gem); | ||
388 | |||
389 | /* Pin the memory into the GTT */ | ||
390 | ret = psb_gtt_pin(gt); | ||
391 | if (ret) { | ||
392 | dev_err(dev->dev, "Can not pin down handle 0x%x\n", handle); | ||
393 | goto unref_cursor; | ||
394 | } | ||
395 | |||
396 | if (dev_priv->ops->cursor_needs_phys) { | ||
397 | if (cursor_gt == NULL) { | ||
398 | dev_err(dev->dev, "No hardware cursor mem available"); | ||
399 | ret = -ENOMEM; | ||
400 | goto unref_cursor; | ||
401 | } | ||
402 | |||
403 | /* Prevent overflow */ | ||
404 | if (gt->npage > 4) | ||
405 | cursor_pages = 4; | ||
406 | else | ||
407 | cursor_pages = gt->npage; | ||
408 | |||
409 | /* Copy the cursor to cursor mem */ | ||
410 | tmp_dst = dev_priv->vram_addr + cursor_gt->offset; | ||
411 | for (i = 0; i < cursor_pages; i++) { | ||
412 | tmp_src = kmap(gt->pages[i]); | ||
413 | memcpy(tmp_dst, tmp_src, PAGE_SIZE); | ||
414 | kunmap(gt->pages[i]); | ||
415 | tmp_dst += PAGE_SIZE; | ||
416 | } | ||
417 | |||
418 | addr = gma_crtc->cursor_addr; | ||
419 | } else { | ||
420 | addr = gt->offset; | ||
421 | gma_crtc->cursor_addr = addr; | ||
422 | } | ||
423 | |||
424 | temp = 0; | ||
425 | /* set the pipe for the cursor */ | ||
426 | temp |= (pipe << 28); | ||
427 | temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; | ||
428 | |||
429 | if (gma_power_begin(dev, false)) { | ||
430 | REG_WRITE(control, temp); | ||
431 | REG_WRITE(base, addr); | ||
432 | gma_power_end(dev); | ||
433 | } | ||
434 | |||
435 | /* unpin the old bo */ | ||
436 | if (gma_crtc->cursor_obj) { | ||
437 | gt = container_of(gma_crtc->cursor_obj, struct gtt_range, gem); | ||
438 | psb_gtt_unpin(gt); | ||
439 | drm_gem_object_unreference(gma_crtc->cursor_obj); | ||
440 | } | ||
441 | |||
442 | gma_crtc->cursor_obj = obj; | ||
443 | return ret; | ||
444 | |||
445 | unref_cursor: | ||
446 | drm_gem_object_unreference(obj); | ||
447 | return ret; | ||
448 | } | ||
449 | |||
450 | int gma_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) | ||
451 | { | ||
452 | struct drm_device *dev = crtc->dev; | ||
453 | struct gma_crtc *gma_crtc = to_gma_crtc(crtc); | ||
454 | int pipe = gma_crtc->pipe; | ||
455 | uint32_t temp = 0; | ||
456 | uint32_t addr; | ||
457 | |||
458 | if (x < 0) { | ||
459 | temp |= (CURSOR_POS_SIGN << CURSOR_X_SHIFT); | ||
460 | x = -x; | ||
461 | } | ||
462 | if (y < 0) { | ||
463 | temp |= (CURSOR_POS_SIGN << CURSOR_Y_SHIFT); | ||
464 | y = -y; | ||
465 | } | ||
466 | |||
467 | temp |= ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT); | ||
468 | temp |= ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT); | ||
469 | |||
470 | addr = gma_crtc->cursor_addr; | ||
471 | |||
472 | if (gma_power_begin(dev, false)) { | ||
473 | REG_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp); | ||
474 | REG_WRITE((pipe == 0) ? CURABASE : CURBBASE, addr); | ||
475 | gma_power_end(dev); | ||
476 | } | ||
477 | return 0; | ||
478 | } | ||
479 | |||
480 | bool gma_crtc_mode_fixup(struct drm_crtc *crtc, | ||
481 | const struct drm_display_mode *mode, | ||
482 | struct drm_display_mode *adjusted_mode) | ||
483 | { | ||
484 | return true; | ||
485 | } | ||
486 | |||
487 | void gma_crtc_prepare(struct drm_crtc *crtc) | ||
488 | { | ||
489 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; | ||
490 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF); | ||
491 | } | ||
492 | |||
493 | void gma_crtc_commit(struct drm_crtc *crtc) | ||
494 | { | ||
495 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; | ||
496 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); | ||
497 | } | ||
498 | |||
499 | void gma_crtc_disable(struct drm_crtc *crtc) | ||
500 | { | ||
501 | struct gtt_range *gt; | ||
502 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; | ||
503 | |||
504 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF); | ||
505 | |||
506 | if (crtc->fb) { | ||
507 | gt = to_psb_fb(crtc->fb)->gtt; | ||
508 | psb_gtt_unpin(gt); | ||
509 | } | ||
510 | } | ||
511 | |||
512 | void gma_crtc_destroy(struct drm_crtc *crtc) | ||
513 | { | ||
514 | struct gma_crtc *gma_crtc = to_gma_crtc(crtc); | ||
515 | |||
516 | kfree(gma_crtc->crtc_state); | ||
517 | drm_crtc_cleanup(crtc); | ||
518 | kfree(gma_crtc); | ||
519 | } | ||
520 | |||
521 | int gma_crtc_set_config(struct drm_mode_set *set) | ||
522 | { | ||
523 | struct drm_device *dev = set->crtc->dev; | ||
524 | struct drm_psb_private *dev_priv = dev->dev_private; | ||
525 | int ret; | ||
526 | |||
527 | if (!dev_priv->rpm_enabled) | ||
528 | return drm_crtc_helper_set_config(set); | ||
529 | |||
530 | pm_runtime_forbid(&dev->pdev->dev); | ||
531 | ret = drm_crtc_helper_set_config(set); | ||
532 | pm_runtime_allow(&dev->pdev->dev); | ||
533 | |||
534 | return ret; | ||
535 | } | ||
536 | |||
537 | /** | ||
538 | * Save HW states of given crtc | ||
539 | */ | ||
540 | void gma_crtc_save(struct drm_crtc *crtc) | ||
541 | { | ||
542 | struct drm_device *dev = crtc->dev; | ||
543 | struct drm_psb_private *dev_priv = dev->dev_private; | ||
544 | struct gma_crtc *gma_crtc = to_gma_crtc(crtc); | ||
545 | struct psb_intel_crtc_state *crtc_state = gma_crtc->crtc_state; | ||
546 | const struct psb_offset *map = &dev_priv->regmap[gma_crtc->pipe]; | ||
547 | uint32_t palette_reg; | ||
548 | int i; | ||
549 | |||
550 | if (!crtc_state) { | ||
551 | dev_err(dev->dev, "No CRTC state found\n"); | ||
552 | return; | ||
553 | } | ||
554 | |||
555 | crtc_state->saveDSPCNTR = REG_READ(map->cntr); | ||
556 | crtc_state->savePIPECONF = REG_READ(map->conf); | ||
557 | crtc_state->savePIPESRC = REG_READ(map->src); | ||
558 | crtc_state->saveFP0 = REG_READ(map->fp0); | ||
559 | crtc_state->saveFP1 = REG_READ(map->fp1); | ||
560 | crtc_state->saveDPLL = REG_READ(map->dpll); | ||
561 | crtc_state->saveHTOTAL = REG_READ(map->htotal); | ||
562 | crtc_state->saveHBLANK = REG_READ(map->hblank); | ||
563 | crtc_state->saveHSYNC = REG_READ(map->hsync); | ||
564 | crtc_state->saveVTOTAL = REG_READ(map->vtotal); | ||
565 | crtc_state->saveVBLANK = REG_READ(map->vblank); | ||
566 | crtc_state->saveVSYNC = REG_READ(map->vsync); | ||
567 | crtc_state->saveDSPSTRIDE = REG_READ(map->stride); | ||
568 | |||
569 | /* NOTE: DSPSIZE DSPPOS only for psb */ | ||
570 | crtc_state->saveDSPSIZE = REG_READ(map->size); | ||
571 | crtc_state->saveDSPPOS = REG_READ(map->pos); | ||
572 | |||
573 | crtc_state->saveDSPBASE = REG_READ(map->base); | ||
574 | |||
575 | palette_reg = map->palette; | ||
576 | for (i = 0; i < 256; ++i) | ||
577 | crtc_state->savePalette[i] = REG_READ(palette_reg + (i << 2)); | ||
578 | } | ||
579 | |||
580 | /** | ||
581 | * Restore HW states of given crtc | ||
582 | */ | ||
583 | void gma_crtc_restore(struct drm_crtc *crtc) | ||
584 | { | ||
585 | struct drm_device *dev = crtc->dev; | ||
586 | struct drm_psb_private *dev_priv = dev->dev_private; | ||
587 | struct gma_crtc *gma_crtc = to_gma_crtc(crtc); | ||
588 | struct psb_intel_crtc_state *crtc_state = gma_crtc->crtc_state; | ||
589 | const struct psb_offset *map = &dev_priv->regmap[gma_crtc->pipe]; | ||
590 | uint32_t palette_reg; | ||
591 | int i; | ||
592 | |||
593 | if (!crtc_state) { | ||
594 | dev_err(dev->dev, "No crtc state\n"); | ||
595 | return; | ||
596 | } | ||
597 | |||
598 | if (crtc_state->saveDPLL & DPLL_VCO_ENABLE) { | ||
599 | REG_WRITE(map->dpll, | ||
600 | crtc_state->saveDPLL & ~DPLL_VCO_ENABLE); | ||
601 | REG_READ(map->dpll); | ||
602 | udelay(150); | ||
603 | } | ||
604 | |||
605 | REG_WRITE(map->fp0, crtc_state->saveFP0); | ||
606 | REG_READ(map->fp0); | ||
607 | |||
608 | REG_WRITE(map->fp1, crtc_state->saveFP1); | ||
609 | REG_READ(map->fp1); | ||
610 | |||
611 | REG_WRITE(map->dpll, crtc_state->saveDPLL); | ||
612 | REG_READ(map->dpll); | ||
613 | udelay(150); | ||
614 | |||
615 | REG_WRITE(map->htotal, crtc_state->saveHTOTAL); | ||
616 | REG_WRITE(map->hblank, crtc_state->saveHBLANK); | ||
617 | REG_WRITE(map->hsync, crtc_state->saveHSYNC); | ||
618 | REG_WRITE(map->vtotal, crtc_state->saveVTOTAL); | ||
619 | REG_WRITE(map->vblank, crtc_state->saveVBLANK); | ||
620 | REG_WRITE(map->vsync, crtc_state->saveVSYNC); | ||
621 | REG_WRITE(map->stride, crtc_state->saveDSPSTRIDE); | ||
622 | |||
623 | REG_WRITE(map->size, crtc_state->saveDSPSIZE); | ||
624 | REG_WRITE(map->pos, crtc_state->saveDSPPOS); | ||
625 | |||
626 | REG_WRITE(map->src, crtc_state->savePIPESRC); | ||
627 | REG_WRITE(map->base, crtc_state->saveDSPBASE); | ||
628 | REG_WRITE(map->conf, crtc_state->savePIPECONF); | ||
629 | |||
630 | gma_wait_for_vblank(dev); | ||
631 | |||
632 | REG_WRITE(map->cntr, crtc_state->saveDSPCNTR); | ||
633 | REG_WRITE(map->base, crtc_state->saveDSPBASE); | ||
634 | |||
635 | gma_wait_for_vblank(dev); | ||
636 | |||
637 | palette_reg = map->palette; | ||
638 | for (i = 0; i < 256; ++i) | ||
639 | REG_WRITE(palette_reg + (i << 2), crtc_state->savePalette[i]); | ||
640 | } | ||
641 | |||
642 | void gma_encoder_prepare(struct drm_encoder *encoder) | ||
643 | { | ||
644 | struct drm_encoder_helper_funcs *encoder_funcs = | ||
645 | encoder->helper_private; | ||
646 | /* lvds has its own version of prepare see psb_intel_lvds_prepare */ | ||
647 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF); | ||
648 | } | ||
649 | |||
650 | void gma_encoder_commit(struct drm_encoder *encoder) | ||
651 | { | ||
652 | struct drm_encoder_helper_funcs *encoder_funcs = | ||
653 | encoder->helper_private; | ||
654 | /* lvds has its own version of commit see psb_intel_lvds_commit */ | ||
655 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); | ||
656 | } | ||
657 | |||
658 | void gma_encoder_destroy(struct drm_encoder *encoder) | ||
659 | { | ||
660 | struct gma_encoder *intel_encoder = to_gma_encoder(encoder); | ||
661 | |||
662 | drm_encoder_cleanup(encoder); | ||
663 | kfree(intel_encoder); | ||
664 | } | ||
665 | |||
666 | /* Currently there is only a 1:1 mapping of encoders and connectors */ | ||
667 | struct drm_encoder *gma_best_encoder(struct drm_connector *connector) | ||
668 | { | ||
669 | struct gma_encoder *gma_encoder = gma_attached_encoder(connector); | ||
670 | |||
671 | return &gma_encoder->base; | ||
672 | } | ||
673 | |||
674 | void gma_connector_attach_encoder(struct gma_connector *connector, | ||
675 | struct gma_encoder *encoder) | ||
676 | { | ||
677 | connector->encoder = encoder; | ||
678 | drm_mode_connector_attach_encoder(&connector->base, | ||
679 | &encoder->base); | ||
680 | } | ||
681 | |||
682 | #define GMA_PLL_INVALID(s) { /* DRM_ERROR(s); */ return false; } | ||
683 | |||
684 | bool gma_pll_is_valid(struct drm_crtc *crtc, | ||
685 | const struct gma_limit_t *limit, | ||
686 | struct gma_clock_t *clock) | ||
687 | { | ||
688 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) | ||
689 | GMA_PLL_INVALID("p1 out of range"); | ||
690 | if (clock->p < limit->p.min || limit->p.max < clock->p) | ||
691 | GMA_PLL_INVALID("p out of range"); | ||
692 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) | ||
693 | GMA_PLL_INVALID("m2 out of range"); | ||
694 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) | ||
695 | GMA_PLL_INVALID("m1 out of range"); | ||
696 | /* On CDV m1 is always 0 */ | ||
697 | if (clock->m1 <= clock->m2 && clock->m1 != 0) | ||
698 | GMA_PLL_INVALID("m1 <= m2 && m1 != 0"); | ||
699 | if (clock->m < limit->m.min || limit->m.max < clock->m) | ||
700 | GMA_PLL_INVALID("m out of range"); | ||
701 | if (clock->n < limit->n.min || limit->n.max < clock->n) | ||
702 | GMA_PLL_INVALID("n out of range"); | ||
703 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) | ||
704 | GMA_PLL_INVALID("vco out of range"); | ||
705 | /* XXX: We may need to be checking "Dot clock" | ||
706 | * depending on the multiplier, connector, etc., | ||
707 | * rather than just a single range. | ||
708 | */ | ||
709 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | ||
710 | GMA_PLL_INVALID("dot out of range"); | ||
711 | |||
712 | return true; | ||
713 | } | ||
714 | |||
715 | bool gma_find_best_pll(const struct gma_limit_t *limit, | ||
716 | struct drm_crtc *crtc, int target, int refclk, | ||
717 | struct gma_clock_t *best_clock) | ||
718 | { | ||
719 | struct drm_device *dev = crtc->dev; | ||
720 | const struct gma_clock_funcs *clock_funcs = | ||
721 | to_gma_crtc(crtc)->clock_funcs; | ||
722 | struct gma_clock_t clock; | ||
723 | int err = target; | ||
724 | |||
725 | if (gma_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && | ||
726 | (REG_READ(LVDS) & LVDS_PORT_EN) != 0) { | ||
727 | /* | ||
728 | * For LVDS, if the panel is on, just rely on its current | ||
729 | * settings for dual-channel. We haven't figured out how to | ||
730 | * reliably set up different single/dual channel state, if we | ||
731 | * even can. | ||
732 | */ | ||
733 | if ((REG_READ(LVDS) & LVDS_CLKB_POWER_MASK) == | ||
734 | LVDS_CLKB_POWER_UP) | ||
735 | clock.p2 = limit->p2.p2_fast; | ||
736 | else | ||
737 | clock.p2 = limit->p2.p2_slow; | ||
738 | } else { | ||
739 | if (target < limit->p2.dot_limit) | ||
740 | clock.p2 = limit->p2.p2_slow; | ||
741 | else | ||
742 | clock.p2 = limit->p2.p2_fast; | ||
743 | } | ||
744 | |||
745 | memset(best_clock, 0, sizeof(*best_clock)); | ||
746 | |||
747 | /* m1 is always 0 on CDV so the outmost loop will run just once */ | ||
748 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { | ||
749 | for (clock.m2 = limit->m2.min; | ||
750 | (clock.m2 < clock.m1 || clock.m1 == 0) && | ||
751 | clock.m2 <= limit->m2.max; clock.m2++) { | ||
752 | for (clock.n = limit->n.min; | ||
753 | clock.n <= limit->n.max; clock.n++) { | ||
754 | for (clock.p1 = limit->p1.min; | ||
755 | clock.p1 <= limit->p1.max; | ||
756 | clock.p1++) { | ||
757 | int this_err; | ||
758 | |||
759 | clock_funcs->clock(refclk, &clock); | ||
760 | |||
761 | if (!clock_funcs->pll_is_valid(crtc, | ||
762 | limit, &clock)) | ||
763 | continue; | ||
764 | |||
765 | this_err = abs(clock.dot - target); | ||
766 | if (this_err < err) { | ||
767 | *best_clock = clock; | ||
768 | err = this_err; | ||
769 | } | ||
770 | } | ||
771 | } | ||
772 | } | ||
773 | } | ||
774 | |||
775 | return err != target; | ||
776 | } | ||
diff --git a/drivers/gpu/drm/gma500/gma_display.h b/drivers/gpu/drm/gma500/gma_display.h new file mode 100644 index 000000000000..78b9f986a6e5 --- /dev/null +++ b/drivers/gpu/drm/gma500/gma_display.h | |||
@@ -0,0 +1,103 @@ | |||
1 | /* | ||
2 | * Copyright © 2006-2011 Intel Corporation | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License along with | ||
14 | * this program; if not, write to the Free Software Foundation, Inc., | ||
15 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | ||
16 | * | ||
17 | * Authors: | ||
18 | * Eric Anholt <eric@anholt.net> | ||
19 | * Patrik Jakobsson <patrik.r.jakobsson@gmail.com> | ||
20 | */ | ||
21 | |||
22 | #ifndef _GMA_DISPLAY_H_ | ||
23 | #define _GMA_DISPLAY_H_ | ||
24 | |||
25 | #include <linux/pm_runtime.h> | ||
26 | |||
27 | struct gma_clock_t { | ||
28 | /* given values */ | ||
29 | int n; | ||
30 | int m1, m2; | ||
31 | int p1, p2; | ||
32 | /* derived values */ | ||
33 | int dot; | ||
34 | int vco; | ||
35 | int m; | ||
36 | int p; | ||
37 | }; | ||
38 | |||
39 | struct gma_range_t { | ||
40 | int min, max; | ||
41 | }; | ||
42 | |||
43 | struct gma_p2_t { | ||
44 | int dot_limit; | ||
45 | int p2_slow, p2_fast; | ||
46 | }; | ||
47 | |||
48 | struct gma_limit_t { | ||
49 | struct gma_range_t dot, vco, n, m, m1, m2, p, p1; | ||
50 | struct gma_p2_t p2; | ||
51 | bool (*find_pll)(const struct gma_limit_t *, struct drm_crtc *, | ||
52 | int target, int refclk, | ||
53 | struct gma_clock_t *best_clock); | ||
54 | }; | ||
55 | |||
56 | struct gma_clock_funcs { | ||
57 | void (*clock)(int refclk, struct gma_clock_t *clock); | ||
58 | const struct gma_limit_t *(*limit)(struct drm_crtc *crtc, int refclk); | ||
59 | bool (*pll_is_valid)(struct drm_crtc *crtc, | ||
60 | const struct gma_limit_t *limit, | ||
61 | struct gma_clock_t *clock); | ||
62 | }; | ||
63 | |||
64 | /* Common pipe related functions */ | ||
65 | extern bool gma_pipe_has_type(struct drm_crtc *crtc, int type); | ||
66 | extern void gma_wait_for_vblank(struct drm_device *dev); | ||
67 | extern int gma_pipe_set_base(struct drm_crtc *crtc, int x, int y, | ||
68 | struct drm_framebuffer *old_fb); | ||
69 | extern int gma_crtc_cursor_set(struct drm_crtc *crtc, | ||
70 | struct drm_file *file_priv, | ||
71 | uint32_t handle, | ||
72 | uint32_t width, uint32_t height); | ||
73 | extern int gma_crtc_cursor_move(struct drm_crtc *crtc, int x, int y); | ||
74 | extern void gma_crtc_load_lut(struct drm_crtc *crtc); | ||
75 | extern void gma_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, | ||
76 | u16 *blue, u32 start, u32 size); | ||
77 | extern void gma_crtc_dpms(struct drm_crtc *crtc, int mode); | ||
78 | extern bool gma_crtc_mode_fixup(struct drm_crtc *crtc, | ||
79 | const struct drm_display_mode *mode, | ||
80 | struct drm_display_mode *adjusted_mode); | ||
81 | extern void gma_crtc_prepare(struct drm_crtc *crtc); | ||
82 | extern void gma_crtc_commit(struct drm_crtc *crtc); | ||
83 | extern void gma_crtc_disable(struct drm_crtc *crtc); | ||
84 | extern void gma_crtc_destroy(struct drm_crtc *crtc); | ||
85 | extern int gma_crtc_set_config(struct drm_mode_set *set); | ||
86 | |||
87 | extern void gma_crtc_save(struct drm_crtc *crtc); | ||
88 | extern void gma_crtc_restore(struct drm_crtc *crtc); | ||
89 | |||
90 | extern void gma_encoder_prepare(struct drm_encoder *encoder); | ||
91 | extern void gma_encoder_commit(struct drm_encoder *encoder); | ||
92 | extern void gma_encoder_destroy(struct drm_encoder *encoder); | ||
93 | |||
94 | /* Common clock related functions */ | ||
95 | extern const struct gma_limit_t *gma_limit(struct drm_crtc *crtc, int refclk); | ||
96 | extern void gma_clock(int refclk, struct gma_clock_t *clock); | ||
97 | extern bool gma_pll_is_valid(struct drm_crtc *crtc, | ||
98 | const struct gma_limit_t *limit, | ||
99 | struct gma_clock_t *clock); | ||
100 | extern bool gma_find_best_pll(const struct gma_limit_t *limit, | ||
101 | struct drm_crtc *crtc, int target, int refclk, | ||
102 | struct gma_clock_t *best_clock); | ||
103 | #endif | ||
diff --git a/drivers/gpu/drm/gma500/mdfld_dsi_output.c b/drivers/gpu/drm/gma500/mdfld_dsi_output.c index 3abf8315f57c..860a4ee9baaf 100644 --- a/drivers/gpu/drm/gma500/mdfld_dsi_output.c +++ b/drivers/gpu/drm/gma500/mdfld_dsi_output.c | |||
@@ -249,12 +249,11 @@ static int mdfld_dsi_connector_set_property(struct drm_connector *connector, | |||
249 | struct drm_encoder *encoder = connector->encoder; | 249 | struct drm_encoder *encoder = connector->encoder; |
250 | 250 | ||
251 | if (!strcmp(property->name, "scaling mode") && encoder) { | 251 | if (!strcmp(property->name, "scaling mode") && encoder) { |
252 | struct psb_intel_crtc *psb_crtc = | 252 | struct gma_crtc *gma_crtc = to_gma_crtc(encoder->crtc); |
253 | to_psb_intel_crtc(encoder->crtc); | ||
254 | bool centerechange; | 253 | bool centerechange; |
255 | uint64_t val; | 254 | uint64_t val; |
256 | 255 | ||
257 | if (!psb_crtc) | 256 | if (!gma_crtc) |
258 | goto set_prop_error; | 257 | goto set_prop_error; |
259 | 258 | ||
260 | switch (value) { | 259 | switch (value) { |
@@ -281,11 +280,11 @@ static int mdfld_dsi_connector_set_property(struct drm_connector *connector, | |||
281 | centerechange = (val == DRM_MODE_SCALE_NO_SCALE) || | 280 | centerechange = (val == DRM_MODE_SCALE_NO_SCALE) || |
282 | (value == DRM_MODE_SCALE_NO_SCALE); | 281 | (value == DRM_MODE_SCALE_NO_SCALE); |
283 | 282 | ||
284 | if (psb_crtc->saved_mode.hdisplay != 0 && | 283 | if (gma_crtc->saved_mode.hdisplay != 0 && |
285 | psb_crtc->saved_mode.vdisplay != 0) { | 284 | gma_crtc->saved_mode.vdisplay != 0) { |
286 | if (centerechange) { | 285 | if (centerechange) { |
287 | if (!drm_crtc_helper_set_mode(encoder->crtc, | 286 | if (!drm_crtc_helper_set_mode(encoder->crtc, |
288 | &psb_crtc->saved_mode, | 287 | &gma_crtc->saved_mode, |
289 | encoder->crtc->x, | 288 | encoder->crtc->x, |
290 | encoder->crtc->y, | 289 | encoder->crtc->y, |
291 | encoder->crtc->fb)) | 290 | encoder->crtc->fb)) |
@@ -294,8 +293,8 @@ static int mdfld_dsi_connector_set_property(struct drm_connector *connector, | |||
294 | struct drm_encoder_helper_funcs *funcs = | 293 | struct drm_encoder_helper_funcs *funcs = |
295 | encoder->helper_private; | 294 | encoder->helper_private; |
296 | funcs->mode_set(encoder, | 295 | funcs->mode_set(encoder, |
297 | &psb_crtc->saved_mode, | 296 | &gma_crtc->saved_mode, |
298 | &psb_crtc->saved_adjusted_mode); | 297 | &gma_crtc->saved_adjusted_mode); |
299 | } | 298 | } |
300 | } | 299 | } |
301 | } else if (!strcmp(property->name, "backlight") && encoder) { | 300 | } else if (!strcmp(property->name, "backlight") && encoder) { |
diff --git a/drivers/gpu/drm/gma500/mdfld_dsi_output.h b/drivers/gpu/drm/gma500/mdfld_dsi_output.h index 36eb0744841c..45d5af0546bf 100644 --- a/drivers/gpu/drm/gma500/mdfld_dsi_output.h +++ b/drivers/gpu/drm/gma500/mdfld_dsi_output.h | |||
@@ -227,7 +227,7 @@ enum { | |||
227 | #define DSI_DPI_DISABLE_BTA BIT(3) | 227 | #define DSI_DPI_DISABLE_BTA BIT(3) |
228 | 228 | ||
229 | struct mdfld_dsi_connector { | 229 | struct mdfld_dsi_connector { |
230 | struct psb_intel_connector base; | 230 | struct gma_connector base; |
231 | 231 | ||
232 | int pipe; | 232 | int pipe; |
233 | void *private; | 233 | void *private; |
@@ -238,7 +238,7 @@ struct mdfld_dsi_connector { | |||
238 | }; | 238 | }; |
239 | 239 | ||
240 | struct mdfld_dsi_encoder { | 240 | struct mdfld_dsi_encoder { |
241 | struct psb_intel_encoder base; | 241 | struct gma_encoder base; |
242 | void *private; | 242 | void *private; |
243 | }; | 243 | }; |
244 | 244 | ||
@@ -269,21 +269,21 @@ struct mdfld_dsi_config { | |||
269 | static inline struct mdfld_dsi_connector *mdfld_dsi_connector( | 269 | static inline struct mdfld_dsi_connector *mdfld_dsi_connector( |
270 | struct drm_connector *connector) | 270 | struct drm_connector *connector) |
271 | { | 271 | { |
272 | struct psb_intel_connector *psb_connector; | 272 | struct gma_connector *gma_connector; |
273 | 273 | ||
274 | psb_connector = to_psb_intel_connector(connector); | 274 | gma_connector = to_gma_connector(connector); |
275 | 275 | ||
276 | return container_of(psb_connector, struct mdfld_dsi_connector, base); | 276 | return container_of(gma_connector, struct mdfld_dsi_connector, base); |
277 | } | 277 | } |
278 | 278 | ||
279 | static inline struct mdfld_dsi_encoder *mdfld_dsi_encoder( | 279 | static inline struct mdfld_dsi_encoder *mdfld_dsi_encoder( |
280 | struct drm_encoder *encoder) | 280 | struct drm_encoder *encoder) |
281 | { | 281 | { |
282 | struct psb_intel_encoder *psb_encoder; | 282 | struct gma_encoder *gma_encoder; |
283 | 283 | ||
284 | psb_encoder = to_psb_intel_encoder(encoder); | 284 | gma_encoder = to_gma_encoder(encoder); |
285 | 285 | ||
286 | return container_of(psb_encoder, struct mdfld_dsi_encoder, base); | 286 | return container_of(gma_encoder, struct mdfld_dsi_encoder, base); |
287 | } | 287 | } |
288 | 288 | ||
289 | static inline struct mdfld_dsi_config * | 289 | static inline struct mdfld_dsi_config * |
diff --git a/drivers/gpu/drm/gma500/mdfld_intel_display.c b/drivers/gpu/drm/gma500/mdfld_intel_display.c index 74485dc43945..321c00a944e9 100644 --- a/drivers/gpu/drm/gma500/mdfld_intel_display.c +++ b/drivers/gpu/drm/gma500/mdfld_intel_display.c | |||
@@ -23,7 +23,7 @@ | |||
23 | 23 | ||
24 | #include <drm/drmP.h> | 24 | #include <drm/drmP.h> |
25 | #include "psb_intel_reg.h" | 25 | #include "psb_intel_reg.h" |
26 | #include "psb_intel_display.h" | 26 | #include "gma_display.h" |
27 | #include "framebuffer.h" | 27 | #include "framebuffer.h" |
28 | #include "mdfld_output.h" | 28 | #include "mdfld_output.h" |
29 | #include "mdfld_dsi_output.h" | 29 | #include "mdfld_dsi_output.h" |
@@ -65,7 +65,7 @@ void mdfldWaitForPipeDisable(struct drm_device *dev, int pipe) | |||
65 | } | 65 | } |
66 | 66 | ||
67 | /* FIXME JLIU7_PO */ | 67 | /* FIXME JLIU7_PO */ |
68 | psb_intel_wait_for_vblank(dev); | 68 | gma_wait_for_vblank(dev); |
69 | return; | 69 | return; |
70 | 70 | ||
71 | /* Wait for for the pipe disable to take effect. */ | 71 | /* Wait for for the pipe disable to take effect. */ |
@@ -93,7 +93,7 @@ void mdfldWaitForPipeEnable(struct drm_device *dev, int pipe) | |||
93 | } | 93 | } |
94 | 94 | ||
95 | /* FIXME JLIU7_PO */ | 95 | /* FIXME JLIU7_PO */ |
96 | psb_intel_wait_for_vblank(dev); | 96 | gma_wait_for_vblank(dev); |
97 | return; | 97 | return; |
98 | 98 | ||
99 | /* Wait for for the pipe enable to take effect. */ | 99 | /* Wait for for the pipe enable to take effect. */ |
@@ -104,25 +104,6 @@ void mdfldWaitForPipeEnable(struct drm_device *dev, int pipe) | |||
104 | } | 104 | } |
105 | } | 105 | } |
106 | 106 | ||
107 | static void psb_intel_crtc_prepare(struct drm_crtc *crtc) | ||
108 | { | ||
109 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; | ||
110 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF); | ||
111 | } | ||
112 | |||
113 | static void psb_intel_crtc_commit(struct drm_crtc *crtc) | ||
114 | { | ||
115 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; | ||
116 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); | ||
117 | } | ||
118 | |||
119 | static bool psb_intel_crtc_mode_fixup(struct drm_crtc *crtc, | ||
120 | const struct drm_display_mode *mode, | ||
121 | struct drm_display_mode *adjusted_mode) | ||
122 | { | ||
123 | return true; | ||
124 | } | ||
125 | |||
126 | /** | 107 | /** |
127 | * Return the pipe currently connected to the panel fitter, | 108 | * Return the pipe currently connected to the panel fitter, |
128 | * or -1 if the panel fitter is not present or not in use | 109 | * or -1 if the panel fitter is not present or not in use |
@@ -184,9 +165,9 @@ static int mdfld__intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, | |||
184 | { | 165 | { |
185 | struct drm_device *dev = crtc->dev; | 166 | struct drm_device *dev = crtc->dev; |
186 | struct drm_psb_private *dev_priv = dev->dev_private; | 167 | struct drm_psb_private *dev_priv = dev->dev_private; |
187 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); | 168 | struct gma_crtc *gma_crtc = to_gma_crtc(crtc); |
188 | struct psb_framebuffer *psbfb = to_psb_fb(crtc->fb); | 169 | struct psb_framebuffer *psbfb = to_psb_fb(crtc->fb); |
189 | int pipe = psb_intel_crtc->pipe; | 170 | int pipe = gma_crtc->pipe; |
190 | const struct psb_offset *map = &dev_priv->regmap[pipe]; | 171 | const struct psb_offset *map = &dev_priv->regmap[pipe]; |
191 | unsigned long start, offset; | 172 | unsigned long start, offset; |
192 | u32 dspcntr; | 173 | u32 dspcntr; |
@@ -324,8 +305,8 @@ static void mdfld_crtc_dpms(struct drm_crtc *crtc, int mode) | |||
324 | { | 305 | { |
325 | struct drm_device *dev = crtc->dev; | 306 | struct drm_device *dev = crtc->dev; |
326 | struct drm_psb_private *dev_priv = dev->dev_private; | 307 | struct drm_psb_private *dev_priv = dev->dev_private; |
327 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); | 308 | struct gma_crtc *gma_crtc = to_gma_crtc(crtc); |
328 | int pipe = psb_intel_crtc->pipe; | 309 | int pipe = gma_crtc->pipe; |
329 | const struct psb_offset *map = &dev_priv->regmap[pipe]; | 310 | const struct psb_offset *map = &dev_priv->regmap[pipe]; |
330 | u32 pipeconf = dev_priv->pipeconf[pipe]; | 311 | u32 pipeconf = dev_priv->pipeconf[pipe]; |
331 | u32 temp; | 312 | u32 temp; |
@@ -436,7 +417,7 @@ static void mdfld_crtc_dpms(struct drm_crtc *crtc, int mode) | |||
436 | } | 417 | } |
437 | } | 418 | } |
438 | 419 | ||
439 | psb_intel_crtc_load_lut(crtc); | 420 | gma_crtc_load_lut(crtc); |
440 | 421 | ||
441 | /* Give the overlay scaler a chance to enable | 422 | /* Give the overlay scaler a chance to enable |
442 | if it's on this pipe */ | 423 | if it's on this pipe */ |
@@ -611,8 +592,8 @@ static const struct mrst_limit_t *mdfld_limit(struct drm_crtc *crtc) | |||
611 | struct drm_device *dev = crtc->dev; | 592 | struct drm_device *dev = crtc->dev; |
612 | struct drm_psb_private *dev_priv = dev->dev_private; | 593 | struct drm_psb_private *dev_priv = dev->dev_private; |
613 | 594 | ||
614 | if (psb_intel_pipe_has_type(crtc, INTEL_OUTPUT_MIPI) | 595 | if (gma_pipe_has_type(crtc, INTEL_OUTPUT_MIPI) |
615 | || psb_intel_pipe_has_type(crtc, INTEL_OUTPUT_MIPI2)) { | 596 | || gma_pipe_has_type(crtc, INTEL_OUTPUT_MIPI2)) { |
616 | if ((ksel == KSEL_CRYSTAL_19) || (ksel == KSEL_BYPASS_19)) | 597 | if ((ksel == KSEL_CRYSTAL_19) || (ksel == KSEL_BYPASS_19)) |
617 | limit = &mdfld_limits[MDFLD_LIMT_DSIPLL_19]; | 598 | limit = &mdfld_limits[MDFLD_LIMT_DSIPLL_19]; |
618 | else if (ksel == KSEL_BYPASS_25) | 599 | else if (ksel == KSEL_BYPASS_25) |
@@ -624,7 +605,7 @@ static const struct mrst_limit_t *mdfld_limit(struct drm_crtc *crtc) | |||
624 | (dev_priv->core_freq == 100 || | 605 | (dev_priv->core_freq == 100 || |
625 | dev_priv->core_freq == 200)) | 606 | dev_priv->core_freq == 200)) |
626 | limit = &mdfld_limits[MDFLD_LIMT_DSIPLL_100]; | 607 | limit = &mdfld_limits[MDFLD_LIMT_DSIPLL_100]; |
627 | } else if (psb_intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) { | 608 | } else if (gma_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) { |
628 | if ((ksel == KSEL_CRYSTAL_19) || (ksel == KSEL_BYPASS_19)) | 609 | if ((ksel == KSEL_CRYSTAL_19) || (ksel == KSEL_BYPASS_19)) |
629 | limit = &mdfld_limits[MDFLD_LIMT_DPLL_19]; | 610 | limit = &mdfld_limits[MDFLD_LIMT_DPLL_19]; |
630 | else if (ksel == KSEL_BYPASS_25) | 611 | else if (ksel == KSEL_BYPASS_25) |
@@ -688,9 +669,9 @@ static int mdfld_crtc_mode_set(struct drm_crtc *crtc, | |||
688 | struct drm_framebuffer *old_fb) | 669 | struct drm_framebuffer *old_fb) |
689 | { | 670 | { |
690 | struct drm_device *dev = crtc->dev; | 671 | struct drm_device *dev = crtc->dev; |
691 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); | 672 | struct gma_crtc *gma_crtc = to_gma_crtc(crtc); |
692 | struct drm_psb_private *dev_priv = dev->dev_private; | 673 | struct drm_psb_private *dev_priv = dev->dev_private; |
693 | int pipe = psb_intel_crtc->pipe; | 674 | int pipe = gma_crtc->pipe; |
694 | const struct psb_offset *map = &dev_priv->regmap[pipe]; | 675 | const struct psb_offset *map = &dev_priv->regmap[pipe]; |
695 | int refclk = 0; | 676 | int refclk = 0; |
696 | int clk_n = 0, clk_p2 = 0, clk_byte = 1, clk = 0, m_conv = 0, | 677 | int clk_n = 0, clk_p2 = 0, clk_byte = 1, clk = 0, m_conv = 0, |
@@ -700,7 +681,7 @@ static int mdfld_crtc_mode_set(struct drm_crtc *crtc, | |||
700 | u32 dpll = 0, fp = 0; | 681 | u32 dpll = 0, fp = 0; |
701 | bool is_mipi = false, is_mipi2 = false, is_hdmi = false; | 682 | bool is_mipi = false, is_mipi2 = false, is_hdmi = false; |
702 | struct drm_mode_config *mode_config = &dev->mode_config; | 683 | struct drm_mode_config *mode_config = &dev->mode_config; |
703 | struct psb_intel_encoder *psb_intel_encoder = NULL; | 684 | struct gma_encoder *gma_encoder = NULL; |
704 | uint64_t scalingType = DRM_MODE_SCALE_FULLSCREEN; | 685 | uint64_t scalingType = DRM_MODE_SCALE_FULLSCREEN; |
705 | struct drm_encoder *encoder; | 686 | struct drm_encoder *encoder; |
706 | struct drm_connector *connector; | 687 | struct drm_connector *connector; |
@@ -749,9 +730,9 @@ static int mdfld_crtc_mode_set(struct drm_crtc *crtc, | |||
749 | if (!gma_power_begin(dev, true)) | 730 | if (!gma_power_begin(dev, true)) |
750 | return 0; | 731 | return 0; |
751 | 732 | ||
752 | memcpy(&psb_intel_crtc->saved_mode, mode, | 733 | memcpy(&gma_crtc->saved_mode, mode, |
753 | sizeof(struct drm_display_mode)); | 734 | sizeof(struct drm_display_mode)); |
754 | memcpy(&psb_intel_crtc->saved_adjusted_mode, adjusted_mode, | 735 | memcpy(&gma_crtc->saved_adjusted_mode, adjusted_mode, |
755 | sizeof(struct drm_display_mode)); | 736 | sizeof(struct drm_display_mode)); |
756 | 737 | ||
757 | list_for_each_entry(connector, &mode_config->connector_list, head) { | 738 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
@@ -766,9 +747,9 @@ static int mdfld_crtc_mode_set(struct drm_crtc *crtc, | |||
766 | if (encoder->crtc != crtc) | 747 | if (encoder->crtc != crtc) |
767 | continue; | 748 | continue; |
768 | 749 | ||
769 | psb_intel_encoder = psb_intel_attached_encoder(connector); | 750 | gma_encoder = gma_attached_encoder(connector); |
770 | 751 | ||
771 | switch (psb_intel_encoder->type) { | 752 | switch (gma_encoder->type) { |
772 | case INTEL_OUTPUT_MIPI: | 753 | case INTEL_OUTPUT_MIPI: |
773 | is_mipi = true; | 754 | is_mipi = true; |
774 | break; | 755 | break; |
@@ -819,7 +800,7 @@ static int mdfld_crtc_mode_set(struct drm_crtc *crtc, | |||
819 | 800 | ||
820 | REG_WRITE(map->pos, 0); | 801 | REG_WRITE(map->pos, 0); |
821 | 802 | ||
822 | if (psb_intel_encoder) | 803 | if (gma_encoder) |
823 | drm_object_property_get_value(&connector->base, | 804 | drm_object_property_get_value(&connector->base, |
824 | dev->mode_config.scaling_mode_property, &scalingType); | 805 | dev->mode_config.scaling_mode_property, &scalingType); |
825 | 806 | ||
@@ -1034,7 +1015,7 @@ static int mdfld_crtc_mode_set(struct drm_crtc *crtc, | |||
1034 | 1015 | ||
1035 | /* Wait for for the pipe enable to take effect. */ | 1016 | /* Wait for for the pipe enable to take effect. */ |
1036 | REG_WRITE(map->cntr, dev_priv->dspcntr[pipe]); | 1017 | REG_WRITE(map->cntr, dev_priv->dspcntr[pipe]); |
1037 | psb_intel_wait_for_vblank(dev); | 1018 | gma_wait_for_vblank(dev); |
1038 | 1019 | ||
1039 | mrst_crtc_mode_set_exit: | 1020 | mrst_crtc_mode_set_exit: |
1040 | 1021 | ||
@@ -1045,10 +1026,10 @@ mrst_crtc_mode_set_exit: | |||
1045 | 1026 | ||
1046 | const struct drm_crtc_helper_funcs mdfld_helper_funcs = { | 1027 | const struct drm_crtc_helper_funcs mdfld_helper_funcs = { |
1047 | .dpms = mdfld_crtc_dpms, | 1028 | .dpms = mdfld_crtc_dpms, |
1048 | .mode_fixup = psb_intel_crtc_mode_fixup, | 1029 | .mode_fixup = gma_crtc_mode_fixup, |
1049 | .mode_set = mdfld_crtc_mode_set, | 1030 | .mode_set = mdfld_crtc_mode_set, |
1050 | .mode_set_base = mdfld__intel_pipe_set_base, | 1031 | .mode_set_base = mdfld__intel_pipe_set_base, |
1051 | .prepare = psb_intel_crtc_prepare, | 1032 | .prepare = gma_crtc_prepare, |
1052 | .commit = psb_intel_crtc_commit, | 1033 | .commit = gma_crtc_commit, |
1053 | }; | 1034 | }; |
1054 | 1035 | ||
diff --git a/drivers/gpu/drm/gma500/oaktrail_crtc.c b/drivers/gpu/drm/gma500/oaktrail_crtc.c index 3071526bc3c1..54c98962b73e 100644 --- a/drivers/gpu/drm/gma500/oaktrail_crtc.c +++ b/drivers/gpu/drm/gma500/oaktrail_crtc.c | |||
@@ -23,7 +23,7 @@ | |||
23 | #include "psb_drv.h" | 23 | #include "psb_drv.h" |
24 | #include "psb_intel_drv.h" | 24 | #include "psb_intel_drv.h" |
25 | #include "psb_intel_reg.h" | 25 | #include "psb_intel_reg.h" |
26 | #include "psb_intel_display.h" | 26 | #include "gma_display.h" |
27 | #include "power.h" | 27 | #include "power.h" |
28 | 28 | ||
29 | struct psb_intel_range_t { | 29 | struct psb_intel_range_t { |
@@ -88,8 +88,8 @@ static const struct oaktrail_limit_t *oaktrail_limit(struct drm_crtc *crtc) | |||
88 | struct drm_device *dev = crtc->dev; | 88 | struct drm_device *dev = crtc->dev; |
89 | struct drm_psb_private *dev_priv = dev->dev_private; | 89 | struct drm_psb_private *dev_priv = dev->dev_private; |
90 | 90 | ||
91 | if (psb_intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) | 91 | if (gma_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) |
92 | || psb_intel_pipe_has_type(crtc, INTEL_OUTPUT_MIPI)) { | 92 | || gma_pipe_has_type(crtc, INTEL_OUTPUT_MIPI)) { |
93 | switch (dev_priv->core_freq) { | 93 | switch (dev_priv->core_freq) { |
94 | case 100: | 94 | case 100: |
95 | limit = &oaktrail_limits[MRST_LIMIT_LVDS_100L]; | 95 | limit = &oaktrail_limits[MRST_LIMIT_LVDS_100L]; |
@@ -163,8 +163,8 @@ static void oaktrail_crtc_dpms(struct drm_crtc *crtc, int mode) | |||
163 | { | 163 | { |
164 | struct drm_device *dev = crtc->dev; | 164 | struct drm_device *dev = crtc->dev; |
165 | struct drm_psb_private *dev_priv = dev->dev_private; | 165 | struct drm_psb_private *dev_priv = dev->dev_private; |
166 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); | 166 | struct gma_crtc *gma_crtc = to_gma_crtc(crtc); |
167 | int pipe = psb_intel_crtc->pipe; | 167 | int pipe = gma_crtc->pipe; |
168 | const struct psb_offset *map = &dev_priv->regmap[pipe]; | 168 | const struct psb_offset *map = &dev_priv->regmap[pipe]; |
169 | u32 temp; | 169 | u32 temp; |
170 | 170 | ||
@@ -212,7 +212,7 @@ static void oaktrail_crtc_dpms(struct drm_crtc *crtc, int mode) | |||
212 | REG_WRITE(map->base, REG_READ(map->base)); | 212 | REG_WRITE(map->base, REG_READ(map->base)); |
213 | } | 213 | } |
214 | 214 | ||
215 | psb_intel_crtc_load_lut(crtc); | 215 | gma_crtc_load_lut(crtc); |
216 | 216 | ||
217 | /* Give the overlay scaler a chance to enable | 217 | /* Give the overlay scaler a chance to enable |
218 | if it's on this pipe */ | 218 | if it's on this pipe */ |
@@ -242,7 +242,7 @@ static void oaktrail_crtc_dpms(struct drm_crtc *crtc, int mode) | |||
242 | REG_READ(map->conf); | 242 | REG_READ(map->conf); |
243 | } | 243 | } |
244 | /* Wait for for the pipe disable to take effect. */ | 244 | /* Wait for for the pipe disable to take effect. */ |
245 | psb_intel_wait_for_vblank(dev); | 245 | gma_wait_for_vblank(dev); |
246 | 246 | ||
247 | temp = REG_READ(map->dpll); | 247 | temp = REG_READ(map->dpll); |
248 | if ((temp & DPLL_VCO_ENABLE) != 0) { | 248 | if ((temp & DPLL_VCO_ENABLE) != 0) { |
@@ -292,9 +292,9 @@ static int oaktrail_crtc_mode_set(struct drm_crtc *crtc, | |||
292 | struct drm_framebuffer *old_fb) | 292 | struct drm_framebuffer *old_fb) |
293 | { | 293 | { |
294 | struct drm_device *dev = crtc->dev; | 294 | struct drm_device *dev = crtc->dev; |
295 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); | 295 | struct gma_crtc *gma_crtc = to_gma_crtc(crtc); |
296 | struct drm_psb_private *dev_priv = dev->dev_private; | 296 | struct drm_psb_private *dev_priv = dev->dev_private; |
297 | int pipe = psb_intel_crtc->pipe; | 297 | int pipe = gma_crtc->pipe; |
298 | const struct psb_offset *map = &dev_priv->regmap[pipe]; | 298 | const struct psb_offset *map = &dev_priv->regmap[pipe]; |
299 | int refclk = 0; | 299 | int refclk = 0; |
300 | struct oaktrail_clock_t clock; | 300 | struct oaktrail_clock_t clock; |
@@ -303,7 +303,7 @@ static int oaktrail_crtc_mode_set(struct drm_crtc *crtc, | |||
303 | bool is_lvds = false; | 303 | bool is_lvds = false; |
304 | bool is_mipi = false; | 304 | bool is_mipi = false; |
305 | struct drm_mode_config *mode_config = &dev->mode_config; | 305 | struct drm_mode_config *mode_config = &dev->mode_config; |
306 | struct psb_intel_encoder *psb_intel_encoder = NULL; | 306 | struct gma_encoder *gma_encoder = NULL; |
307 | uint64_t scalingType = DRM_MODE_SCALE_FULLSCREEN; | 307 | uint64_t scalingType = DRM_MODE_SCALE_FULLSCREEN; |
308 | struct drm_connector *connector; | 308 | struct drm_connector *connector; |
309 | 309 | ||
@@ -313,10 +313,10 @@ static int oaktrail_crtc_mode_set(struct drm_crtc *crtc, | |||
313 | if (!gma_power_begin(dev, true)) | 313 | if (!gma_power_begin(dev, true)) |
314 | return 0; | 314 | return 0; |
315 | 315 | ||
316 | memcpy(&psb_intel_crtc->saved_mode, | 316 | memcpy(&gma_crtc->saved_mode, |
317 | mode, | 317 | mode, |
318 | sizeof(struct drm_display_mode)); | 318 | sizeof(struct drm_display_mode)); |
319 | memcpy(&psb_intel_crtc->saved_adjusted_mode, | 319 | memcpy(&gma_crtc->saved_adjusted_mode, |
320 | adjusted_mode, | 320 | adjusted_mode, |
321 | sizeof(struct drm_display_mode)); | 321 | sizeof(struct drm_display_mode)); |
322 | 322 | ||
@@ -324,9 +324,9 @@ static int oaktrail_crtc_mode_set(struct drm_crtc *crtc, | |||
324 | if (!connector->encoder || connector->encoder->crtc != crtc) | 324 | if (!connector->encoder || connector->encoder->crtc != crtc) |
325 | continue; | 325 | continue; |
326 | 326 | ||
327 | psb_intel_encoder = psb_intel_attached_encoder(connector); | 327 | gma_encoder = gma_attached_encoder(connector); |
328 | 328 | ||
329 | switch (psb_intel_encoder->type) { | 329 | switch (gma_encoder->type) { |
330 | case INTEL_OUTPUT_LVDS: | 330 | case INTEL_OUTPUT_LVDS: |
331 | is_lvds = true; | 331 | is_lvds = true; |
332 | break; | 332 | break; |
@@ -350,7 +350,7 @@ static int oaktrail_crtc_mode_set(struct drm_crtc *crtc, | |||
350 | ((mode->crtc_hdisplay - 1) << 16) | | 350 | ((mode->crtc_hdisplay - 1) << 16) | |
351 | (mode->crtc_vdisplay - 1)); | 351 | (mode->crtc_vdisplay - 1)); |
352 | 352 | ||
353 | if (psb_intel_encoder) | 353 | if (gma_encoder) |
354 | drm_object_property_get_value(&connector->base, | 354 | drm_object_property_get_value(&connector->base, |
355 | dev->mode_config.scaling_mode_property, &scalingType); | 355 | dev->mode_config.scaling_mode_property, &scalingType); |
356 | 356 | ||
@@ -484,31 +484,24 @@ static int oaktrail_crtc_mode_set(struct drm_crtc *crtc, | |||
484 | 484 | ||
485 | REG_WRITE(map->conf, pipeconf); | 485 | REG_WRITE(map->conf, pipeconf); |
486 | REG_READ(map->conf); | 486 | REG_READ(map->conf); |
487 | psb_intel_wait_for_vblank(dev); | 487 | gma_wait_for_vblank(dev); |
488 | 488 | ||
489 | REG_WRITE(map->cntr, dspcntr); | 489 | REG_WRITE(map->cntr, dspcntr); |
490 | psb_intel_wait_for_vblank(dev); | 490 | gma_wait_for_vblank(dev); |
491 | 491 | ||
492 | oaktrail_crtc_mode_set_exit: | 492 | oaktrail_crtc_mode_set_exit: |
493 | gma_power_end(dev); | 493 | gma_power_end(dev); |
494 | return 0; | 494 | return 0; |
495 | } | 495 | } |
496 | 496 | ||
497 | static bool oaktrail_crtc_mode_fixup(struct drm_crtc *crtc, | ||
498 | const struct drm_display_mode *mode, | ||
499 | struct drm_display_mode *adjusted_mode) | ||
500 | { | ||
501 | return true; | ||
502 | } | ||
503 | |||
504 | static int oaktrail_pipe_set_base(struct drm_crtc *crtc, | 497 | static int oaktrail_pipe_set_base(struct drm_crtc *crtc, |
505 | int x, int y, struct drm_framebuffer *old_fb) | 498 | int x, int y, struct drm_framebuffer *old_fb) |
506 | { | 499 | { |
507 | struct drm_device *dev = crtc->dev; | 500 | struct drm_device *dev = crtc->dev; |
508 | struct drm_psb_private *dev_priv = dev->dev_private; | 501 | struct drm_psb_private *dev_priv = dev->dev_private; |
509 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); | 502 | struct gma_crtc *gma_crtc = to_gma_crtc(crtc); |
510 | struct psb_framebuffer *psbfb = to_psb_fb(crtc->fb); | 503 | struct psb_framebuffer *psbfb = to_psb_fb(crtc->fb); |
511 | int pipe = psb_intel_crtc->pipe; | 504 | int pipe = gma_crtc->pipe; |
512 | const struct psb_offset *map = &dev_priv->regmap[pipe]; | 505 | const struct psb_offset *map = &dev_priv->regmap[pipe]; |
513 | unsigned long start, offset; | 506 | unsigned long start, offset; |
514 | 507 | ||
@@ -563,24 +556,12 @@ pipe_set_base_exit: | |||
563 | return ret; | 556 | return ret; |
564 | } | 557 | } |
565 | 558 | ||
566 | static void oaktrail_crtc_prepare(struct drm_crtc *crtc) | ||
567 | { | ||
568 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; | ||
569 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF); | ||
570 | } | ||
571 | |||
572 | static void oaktrail_crtc_commit(struct drm_crtc *crtc) | ||
573 | { | ||
574 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; | ||
575 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); | ||
576 | } | ||
577 | |||
578 | const struct drm_crtc_helper_funcs oaktrail_helper_funcs = { | 559 | const struct drm_crtc_helper_funcs oaktrail_helper_funcs = { |
579 | .dpms = oaktrail_crtc_dpms, | 560 | .dpms = oaktrail_crtc_dpms, |
580 | .mode_fixup = oaktrail_crtc_mode_fixup, | 561 | .mode_fixup = gma_crtc_mode_fixup, |
581 | .mode_set = oaktrail_crtc_mode_set, | 562 | .mode_set = oaktrail_crtc_mode_set, |
582 | .mode_set_base = oaktrail_pipe_set_base, | 563 | .mode_set_base = oaktrail_pipe_set_base, |
583 | .prepare = oaktrail_crtc_prepare, | 564 | .prepare = gma_crtc_prepare, |
584 | .commit = oaktrail_crtc_commit, | 565 | .commit = gma_crtc_commit, |
585 | }; | 566 | }; |
586 | 567 | ||
diff --git a/drivers/gpu/drm/gma500/oaktrail_hdmi.c b/drivers/gpu/drm/gma500/oaktrail_hdmi.c index f036f1fc161e..38153143ed8c 100644 --- a/drivers/gpu/drm/gma500/oaktrail_hdmi.c +++ b/drivers/gpu/drm/gma500/oaktrail_hdmi.c | |||
@@ -155,12 +155,6 @@ static void oaktrail_hdmi_audio_disable(struct drm_device *dev) | |||
155 | HDMI_READ(HDMI_HCR); | 155 | HDMI_READ(HDMI_HCR); |
156 | } | 156 | } |
157 | 157 | ||
158 | static void wait_for_vblank(struct drm_device *dev) | ||
159 | { | ||
160 | /* Wait for 20ms, i.e. one cycle at 50hz. */ | ||
161 | mdelay(20); | ||
162 | } | ||
163 | |||
164 | static unsigned int htotal_calculate(struct drm_display_mode *mode) | 158 | static unsigned int htotal_calculate(struct drm_display_mode *mode) |
165 | { | 159 | { |
166 | u32 htotal, new_crtc_htotal; | 160 | u32 htotal, new_crtc_htotal; |
@@ -372,10 +366,10 @@ int oaktrail_crtc_hdmi_mode_set(struct drm_crtc *crtc, | |||
372 | 366 | ||
373 | REG_WRITE(PCH_PIPEBCONF, pipeconf); | 367 | REG_WRITE(PCH_PIPEBCONF, pipeconf); |
374 | REG_READ(PCH_PIPEBCONF); | 368 | REG_READ(PCH_PIPEBCONF); |
375 | wait_for_vblank(dev); | 369 | gma_wait_for_vblank(dev); |
376 | 370 | ||
377 | REG_WRITE(dspcntr_reg, dspcntr); | 371 | REG_WRITE(dspcntr_reg, dspcntr); |
378 | wait_for_vblank(dev); | 372 | gma_wait_for_vblank(dev); |
379 | 373 | ||
380 | gma_power_end(dev); | 374 | gma_power_end(dev); |
381 | 375 | ||
@@ -459,7 +453,7 @@ void oaktrail_crtc_hdmi_dpms(struct drm_crtc *crtc, int mode) | |||
459 | REG_READ(PCH_PIPEBCONF); | 453 | REG_READ(PCH_PIPEBCONF); |
460 | } | 454 | } |
461 | 455 | ||
462 | wait_for_vblank(dev); | 456 | gma_wait_for_vblank(dev); |
463 | 457 | ||
464 | /* Enable plane */ | 458 | /* Enable plane */ |
465 | temp = REG_READ(DSPBCNTR); | 459 | temp = REG_READ(DSPBCNTR); |
@@ -470,7 +464,7 @@ void oaktrail_crtc_hdmi_dpms(struct drm_crtc *crtc, int mode) | |||
470 | REG_READ(DSPBSURF); | 464 | REG_READ(DSPBSURF); |
471 | } | 465 | } |
472 | 466 | ||
473 | psb_intel_crtc_load_lut(crtc); | 467 | gma_crtc_load_lut(crtc); |
474 | } | 468 | } |
475 | 469 | ||
476 | /* DSPARB */ | 470 | /* DSPARB */ |
@@ -615,16 +609,16 @@ static void oaktrail_hdmi_destroy(struct drm_connector *connector) | |||
615 | static const struct drm_encoder_helper_funcs oaktrail_hdmi_helper_funcs = { | 609 | static const struct drm_encoder_helper_funcs oaktrail_hdmi_helper_funcs = { |
616 | .dpms = oaktrail_hdmi_dpms, | 610 | .dpms = oaktrail_hdmi_dpms, |
617 | .mode_fixup = oaktrail_hdmi_mode_fixup, | 611 | .mode_fixup = oaktrail_hdmi_mode_fixup, |
618 | .prepare = psb_intel_encoder_prepare, | 612 | .prepare = gma_encoder_prepare, |
619 | .mode_set = oaktrail_hdmi_mode_set, | 613 | .mode_set = oaktrail_hdmi_mode_set, |
620 | .commit = psb_intel_encoder_commit, | 614 | .commit = gma_encoder_commit, |
621 | }; | 615 | }; |
622 | 616 | ||
623 | static const struct drm_connector_helper_funcs | 617 | static const struct drm_connector_helper_funcs |
624 | oaktrail_hdmi_connector_helper_funcs = { | 618 | oaktrail_hdmi_connector_helper_funcs = { |
625 | .get_modes = oaktrail_hdmi_get_modes, | 619 | .get_modes = oaktrail_hdmi_get_modes, |
626 | .mode_valid = oaktrail_hdmi_mode_valid, | 620 | .mode_valid = oaktrail_hdmi_mode_valid, |
627 | .best_encoder = psb_intel_best_encoder, | 621 | .best_encoder = gma_best_encoder, |
628 | }; | 622 | }; |
629 | 623 | ||
630 | static const struct drm_connector_funcs oaktrail_hdmi_connector_funcs = { | 624 | static const struct drm_connector_funcs oaktrail_hdmi_connector_funcs = { |
@@ -646,21 +640,21 @@ static const struct drm_encoder_funcs oaktrail_hdmi_enc_funcs = { | |||
646 | void oaktrail_hdmi_init(struct drm_device *dev, | 640 | void oaktrail_hdmi_init(struct drm_device *dev, |
647 | struct psb_intel_mode_device *mode_dev) | 641 | struct psb_intel_mode_device *mode_dev) |
648 | { | 642 | { |
649 | struct psb_intel_encoder *psb_intel_encoder; | 643 | struct gma_encoder *gma_encoder; |
650 | struct psb_intel_connector *psb_intel_connector; | 644 | struct gma_connector *gma_connector; |
651 | struct drm_connector *connector; | 645 | struct drm_connector *connector; |
652 | struct drm_encoder *encoder; | 646 | struct drm_encoder *encoder; |
653 | 647 | ||
654 | psb_intel_encoder = kzalloc(sizeof(struct psb_intel_encoder), GFP_KERNEL); | 648 | gma_encoder = kzalloc(sizeof(struct gma_encoder), GFP_KERNEL); |
655 | if (!psb_intel_encoder) | 649 | if (!gma_encoder) |
656 | return; | 650 | return; |
657 | 651 | ||
658 | psb_intel_connector = kzalloc(sizeof(struct psb_intel_connector), GFP_KERNEL); | 652 | gma_connector = kzalloc(sizeof(struct gma_connector), GFP_KERNEL); |
659 | if (!psb_intel_connector) | 653 | if (!gma_connector) |
660 | goto failed_connector; | 654 | goto failed_connector; |
661 | 655 | ||
662 | connector = &psb_intel_connector->base; | 656 | connector = &gma_connector->base; |
663 | encoder = &psb_intel_encoder->base; | 657 | encoder = &gma_encoder->base; |
664 | drm_connector_init(dev, connector, | 658 | drm_connector_init(dev, connector, |
665 | &oaktrail_hdmi_connector_funcs, | 659 | &oaktrail_hdmi_connector_funcs, |
666 | DRM_MODE_CONNECTOR_DVID); | 660 | DRM_MODE_CONNECTOR_DVID); |
@@ -669,10 +663,9 @@ void oaktrail_hdmi_init(struct drm_device *dev, | |||
669 | &oaktrail_hdmi_enc_funcs, | 663 | &oaktrail_hdmi_enc_funcs, |
670 | DRM_MODE_ENCODER_TMDS); | 664 | DRM_MODE_ENCODER_TMDS); |
671 | 665 | ||
672 | psb_intel_connector_attach_encoder(psb_intel_connector, | 666 | gma_connector_attach_encoder(gma_connector, gma_encoder); |
673 | psb_intel_encoder); | ||
674 | 667 | ||
675 | psb_intel_encoder->type = INTEL_OUTPUT_HDMI; | 668 | gma_encoder->type = INTEL_OUTPUT_HDMI; |
676 | drm_encoder_helper_add(encoder, &oaktrail_hdmi_helper_funcs); | 669 | drm_encoder_helper_add(encoder, &oaktrail_hdmi_helper_funcs); |
677 | drm_connector_helper_add(connector, &oaktrail_hdmi_connector_helper_funcs); | 670 | drm_connector_helper_add(connector, &oaktrail_hdmi_connector_helper_funcs); |
678 | 671 | ||
@@ -685,7 +678,7 @@ void oaktrail_hdmi_init(struct drm_device *dev, | |||
685 | return; | 678 | return; |
686 | 679 | ||
687 | failed_connector: | 680 | failed_connector: |
688 | kfree(psb_intel_encoder); | 681 | kfree(gma_encoder); |
689 | } | 682 | } |
690 | 683 | ||
691 | static DEFINE_PCI_DEVICE_TABLE(hdmi_ids) = { | 684 | static DEFINE_PCI_DEVICE_TABLE(hdmi_ids) = { |
diff --git a/drivers/gpu/drm/gma500/oaktrail_lvds.c b/drivers/gpu/drm/gma500/oaktrail_lvds.c index 325013a9c48c..e77d7214fca4 100644 --- a/drivers/gpu/drm/gma500/oaktrail_lvds.c +++ b/drivers/gpu/drm/gma500/oaktrail_lvds.c | |||
@@ -43,7 +43,7 @@ | |||
43 | * Sets the power state for the panel. | 43 | * Sets the power state for the panel. |
44 | */ | 44 | */ |
45 | static void oaktrail_lvds_set_power(struct drm_device *dev, | 45 | static void oaktrail_lvds_set_power(struct drm_device *dev, |
46 | struct psb_intel_encoder *psb_intel_encoder, | 46 | struct gma_encoder *gma_encoder, |
47 | bool on) | 47 | bool on) |
48 | { | 48 | { |
49 | u32 pp_status; | 49 | u32 pp_status; |
@@ -78,13 +78,12 @@ static void oaktrail_lvds_set_power(struct drm_device *dev, | |||
78 | static void oaktrail_lvds_dpms(struct drm_encoder *encoder, int mode) | 78 | static void oaktrail_lvds_dpms(struct drm_encoder *encoder, int mode) |
79 | { | 79 | { |
80 | struct drm_device *dev = encoder->dev; | 80 | struct drm_device *dev = encoder->dev; |
81 | struct psb_intel_encoder *psb_intel_encoder = | 81 | struct gma_encoder *gma_encoder = to_gma_encoder(encoder); |
82 | to_psb_intel_encoder(encoder); | ||
83 | 82 | ||
84 | if (mode == DRM_MODE_DPMS_ON) | 83 | if (mode == DRM_MODE_DPMS_ON) |
85 | oaktrail_lvds_set_power(dev, psb_intel_encoder, true); | 84 | oaktrail_lvds_set_power(dev, gma_encoder, true); |
86 | else | 85 | else |
87 | oaktrail_lvds_set_power(dev, psb_intel_encoder, false); | 86 | oaktrail_lvds_set_power(dev, gma_encoder, false); |
88 | 87 | ||
89 | /* XXX: We never power down the LVDS pairs. */ | 88 | /* XXX: We never power down the LVDS pairs. */ |
90 | } | 89 | } |
@@ -166,8 +165,7 @@ static void oaktrail_lvds_prepare(struct drm_encoder *encoder) | |||
166 | { | 165 | { |
167 | struct drm_device *dev = encoder->dev; | 166 | struct drm_device *dev = encoder->dev; |
168 | struct drm_psb_private *dev_priv = dev->dev_private; | 167 | struct drm_psb_private *dev_priv = dev->dev_private; |
169 | struct psb_intel_encoder *psb_intel_encoder = | 168 | struct gma_encoder *gma_encoder = to_gma_encoder(encoder); |
170 | to_psb_intel_encoder(encoder); | ||
171 | struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev; | 169 | struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev; |
172 | 170 | ||
173 | if (!gma_power_begin(dev, true)) | 171 | if (!gma_power_begin(dev, true)) |
@@ -176,7 +174,7 @@ static void oaktrail_lvds_prepare(struct drm_encoder *encoder) | |||
176 | mode_dev->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL); | 174 | mode_dev->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL); |
177 | mode_dev->backlight_duty_cycle = (mode_dev->saveBLC_PWM_CTL & | 175 | mode_dev->backlight_duty_cycle = (mode_dev->saveBLC_PWM_CTL & |
178 | BACKLIGHT_DUTY_CYCLE_MASK); | 176 | BACKLIGHT_DUTY_CYCLE_MASK); |
179 | oaktrail_lvds_set_power(dev, psb_intel_encoder, false); | 177 | oaktrail_lvds_set_power(dev, gma_encoder, false); |
180 | gma_power_end(dev); | 178 | gma_power_end(dev); |
181 | } | 179 | } |
182 | 180 | ||
@@ -203,14 +201,13 @@ static void oaktrail_lvds_commit(struct drm_encoder *encoder) | |||
203 | { | 201 | { |
204 | struct drm_device *dev = encoder->dev; | 202 | struct drm_device *dev = encoder->dev; |
205 | struct drm_psb_private *dev_priv = dev->dev_private; | 203 | struct drm_psb_private *dev_priv = dev->dev_private; |
206 | struct psb_intel_encoder *psb_intel_encoder = | 204 | struct gma_encoder *gma_encoder = to_gma_encoder(encoder); |
207 | to_psb_intel_encoder(encoder); | ||
208 | struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev; | 205 | struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev; |
209 | 206 | ||
210 | if (mode_dev->backlight_duty_cycle == 0) | 207 | if (mode_dev->backlight_duty_cycle == 0) |
211 | mode_dev->backlight_duty_cycle = | 208 | mode_dev->backlight_duty_cycle = |
212 | oaktrail_lvds_get_max_backlight(dev); | 209 | oaktrail_lvds_get_max_backlight(dev); |
213 | oaktrail_lvds_set_power(dev, psb_intel_encoder, true); | 210 | oaktrail_lvds_set_power(dev, gma_encoder, true); |
214 | } | 211 | } |
215 | 212 | ||
216 | static const struct drm_encoder_helper_funcs oaktrail_lvds_helper_funcs = { | 213 | static const struct drm_encoder_helper_funcs oaktrail_lvds_helper_funcs = { |
@@ -325,8 +322,8 @@ static void oaktrail_lvds_get_configuration_mode(struct drm_device *dev, | |||
325 | void oaktrail_lvds_init(struct drm_device *dev, | 322 | void oaktrail_lvds_init(struct drm_device *dev, |
326 | struct psb_intel_mode_device *mode_dev) | 323 | struct psb_intel_mode_device *mode_dev) |
327 | { | 324 | { |
328 | struct psb_intel_encoder *psb_intel_encoder; | 325 | struct gma_encoder *gma_encoder; |
329 | struct psb_intel_connector *psb_intel_connector; | 326 | struct gma_connector *gma_connector; |
330 | struct drm_connector *connector; | 327 | struct drm_connector *connector; |
331 | struct drm_encoder *encoder; | 328 | struct drm_encoder *encoder; |
332 | struct drm_psb_private *dev_priv = dev->dev_private; | 329 | struct drm_psb_private *dev_priv = dev->dev_private; |
@@ -334,16 +331,16 @@ void oaktrail_lvds_init(struct drm_device *dev, | |||
334 | struct i2c_adapter *i2c_adap; | 331 | struct i2c_adapter *i2c_adap; |
335 | struct drm_display_mode *scan; /* *modes, *bios_mode; */ | 332 | struct drm_display_mode *scan; /* *modes, *bios_mode; */ |
336 | 333 | ||
337 | psb_intel_encoder = kzalloc(sizeof(struct psb_intel_encoder), GFP_KERNEL); | 334 | gma_encoder = kzalloc(sizeof(struct gma_encoder), GFP_KERNEL); |
338 | if (!psb_intel_encoder) | 335 | if (!gma_encoder) |
339 | return; | 336 | return; |
340 | 337 | ||
341 | psb_intel_connector = kzalloc(sizeof(struct psb_intel_connector), GFP_KERNEL); | 338 | gma_connector = kzalloc(sizeof(struct gma_connector), GFP_KERNEL); |
342 | if (!psb_intel_connector) | 339 | if (!gma_connector) |
343 | goto failed_connector; | 340 | goto failed_connector; |
344 | 341 | ||
345 | connector = &psb_intel_connector->base; | 342 | connector = &gma_connector->base; |
346 | encoder = &psb_intel_encoder->base; | 343 | encoder = &gma_encoder->base; |
347 | dev_priv->is_lvds_on = true; | 344 | dev_priv->is_lvds_on = true; |
348 | drm_connector_init(dev, connector, | 345 | drm_connector_init(dev, connector, |
349 | &psb_intel_lvds_connector_funcs, | 346 | &psb_intel_lvds_connector_funcs, |
@@ -352,9 +349,8 @@ void oaktrail_lvds_init(struct drm_device *dev, | |||
352 | drm_encoder_init(dev, encoder, &psb_intel_lvds_enc_funcs, | 349 | drm_encoder_init(dev, encoder, &psb_intel_lvds_enc_funcs, |
353 | DRM_MODE_ENCODER_LVDS); | 350 | DRM_MODE_ENCODER_LVDS); |
354 | 351 | ||
355 | psb_intel_connector_attach_encoder(psb_intel_connector, | 352 | gma_connector_attach_encoder(gma_connector, gma_encoder); |
356 | psb_intel_encoder); | 353 | gma_encoder->type = INTEL_OUTPUT_LVDS; |
357 | psb_intel_encoder->type = INTEL_OUTPUT_LVDS; | ||
358 | 354 | ||
359 | drm_encoder_helper_add(encoder, &oaktrail_lvds_helper_funcs); | 355 | drm_encoder_helper_add(encoder, &oaktrail_lvds_helper_funcs); |
360 | drm_connector_helper_add(connector, | 356 | drm_connector_helper_add(connector, |
@@ -434,15 +430,15 @@ out: | |||
434 | 430 | ||
435 | failed_find: | 431 | failed_find: |
436 | dev_dbg(dev->dev, "No LVDS modes found, disabling.\n"); | 432 | dev_dbg(dev->dev, "No LVDS modes found, disabling.\n"); |
437 | if (psb_intel_encoder->ddc_bus) | 433 | if (gma_encoder->ddc_bus) |
438 | psb_intel_i2c_destroy(psb_intel_encoder->ddc_bus); | 434 | psb_intel_i2c_destroy(gma_encoder->ddc_bus); |
439 | 435 | ||
440 | /* failed_ddc: */ | 436 | /* failed_ddc: */ |
441 | 437 | ||
442 | drm_encoder_cleanup(encoder); | 438 | drm_encoder_cleanup(encoder); |
443 | drm_connector_cleanup(connector); | 439 | drm_connector_cleanup(connector); |
444 | kfree(psb_intel_connector); | 440 | kfree(gma_connector); |
445 | failed_connector: | 441 | failed_connector: |
446 | kfree(psb_intel_encoder); | 442 | kfree(gma_encoder); |
447 | } | 443 | } |
448 | 444 | ||
diff --git a/drivers/gpu/drm/gma500/psb_device.c b/drivers/gpu/drm/gma500/psb_device.c index f6f534b4197e..697678619bd1 100644 --- a/drivers/gpu/drm/gma500/psb_device.c +++ b/drivers/gpu/drm/gma500/psb_device.c | |||
@@ -25,7 +25,7 @@ | |||
25 | #include "psb_reg.h" | 25 | #include "psb_reg.h" |
26 | #include "psb_intel_reg.h" | 26 | #include "psb_intel_reg.h" |
27 | #include "intel_bios.h" | 27 | #include "intel_bios.h" |
28 | 28 | #include "psb_device.h" | |
29 | 29 | ||
30 | static int psb_output_init(struct drm_device *dev) | 30 | static int psb_output_init(struct drm_device *dev) |
31 | { | 31 | { |
@@ -380,6 +380,7 @@ const struct psb_ops psb_chip_ops = { | |||
380 | 380 | ||
381 | .crtc_helper = &psb_intel_helper_funcs, | 381 | .crtc_helper = &psb_intel_helper_funcs, |
382 | .crtc_funcs = &psb_intel_crtc_funcs, | 382 | .crtc_funcs = &psb_intel_crtc_funcs, |
383 | .clock_funcs = &psb_clock_funcs, | ||
383 | 384 | ||
384 | .output_init = psb_output_init, | 385 | .output_init = psb_output_init, |
385 | 386 | ||
diff --git a/drivers/gpu/drm/gma500/psb_intel_display.h b/drivers/gpu/drm/gma500/psb_device.h index 3724b971e91c..35e304c7f85a 100644 --- a/drivers/gpu/drm/gma500/psb_intel_display.h +++ b/drivers/gpu/drm/gma500/psb_device.h | |||
@@ -1,4 +1,6 @@ | |||
1 | /* copyright (c) 2008, Intel Corporation | 1 | /* |
2 | * Copyright © 2013 Patrik Jakobsson | ||
3 | * Copyright © 2011 Intel Corporation | ||
2 | * | 4 | * |
3 | * This program is free software; you can redistribute it and/or modify it | 5 | * This program is free software; you can redistribute it and/or modify it |
4 | * under the terms and conditions of the GNU General Public License, | 6 | * under the terms and conditions of the GNU General Public License, |
@@ -12,14 +14,11 @@ | |||
12 | * You should have received a copy of the GNU General Public License along with | 14 | * You should have received a copy of the GNU General Public License along with |
13 | * this program; if not, write to the Free Software Foundation, Inc., | 15 | * this program; if not, write to the Free Software Foundation, Inc., |
14 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | 16 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. |
15 | * | ||
16 | * Authors: | ||
17 | * Eric Anholt <eric@anholt.net> | ||
18 | */ | 17 | */ |
19 | 18 | ||
20 | #ifndef _INTEL_DISPLAY_H_ | 19 | #ifndef _PSB_DEVICE_H_ |
21 | #define _INTEL_DISPLAY_H_ | 20 | #define _PSB_DEVICE_H_ |
22 | 21 | ||
23 | bool psb_intel_pipe_has_type(struct drm_crtc *crtc, int type); | 22 | extern const struct gma_clock_funcs psb_clock_funcs; |
24 | 23 | ||
25 | #endif | 24 | #endif |
diff --git a/drivers/gpu/drm/gma500/psb_drv.c b/drivers/gpu/drm/gma500/psb_drv.c index 1383e75acf25..fcb4e9ff1f20 100644 --- a/drivers/gpu/drm/gma500/psb_drv.c +++ b/drivers/gpu/drm/gma500/psb_drv.c | |||
@@ -270,7 +270,7 @@ static int psb_driver_load(struct drm_device *dev, unsigned long chipset) | |||
270 | unsigned long irqflags; | 270 | unsigned long irqflags; |
271 | int ret = -ENOMEM; | 271 | int ret = -ENOMEM; |
272 | struct drm_connector *connector; | 272 | struct drm_connector *connector; |
273 | struct psb_intel_encoder *psb_intel_encoder; | 273 | struct gma_encoder *gma_encoder; |
274 | 274 | ||
275 | dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL); | 275 | dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL); |
276 | if (dev_priv == NULL) | 276 | if (dev_priv == NULL) |
@@ -372,9 +372,9 @@ static int psb_driver_load(struct drm_device *dev, unsigned long chipset) | |||
372 | /* Only add backlight support if we have LVDS output */ | 372 | /* Only add backlight support if we have LVDS output */ |
373 | list_for_each_entry(connector, &dev->mode_config.connector_list, | 373 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
374 | head) { | 374 | head) { |
375 | psb_intel_encoder = psb_intel_attached_encoder(connector); | 375 | gma_encoder = gma_attached_encoder(connector); |
376 | 376 | ||
377 | switch (psb_intel_encoder->type) { | 377 | switch (gma_encoder->type) { |
378 | case INTEL_OUTPUT_LVDS: | 378 | case INTEL_OUTPUT_LVDS: |
379 | case INTEL_OUTPUT_MIPI: | 379 | case INTEL_OUTPUT_MIPI: |
380 | ret = gma_backlight_init(dev); | 380 | ret = gma_backlight_init(dev); |
@@ -441,7 +441,7 @@ static int psb_gamma_ioctl(struct drm_device *dev, void *data, | |||
441 | struct drm_mode_object *obj; | 441 | struct drm_mode_object *obj; |
442 | struct drm_crtc *crtc; | 442 | struct drm_crtc *crtc; |
443 | struct drm_connector *connector; | 443 | struct drm_connector *connector; |
444 | struct psb_intel_crtc *psb_intel_crtc; | 444 | struct gma_crtc *gma_crtc; |
445 | int i = 0; | 445 | int i = 0; |
446 | int32_t obj_id; | 446 | int32_t obj_id; |
447 | 447 | ||
@@ -454,12 +454,12 @@ static int psb_gamma_ioctl(struct drm_device *dev, void *data, | |||
454 | 454 | ||
455 | connector = obj_to_connector(obj); | 455 | connector = obj_to_connector(obj); |
456 | crtc = connector->encoder->crtc; | 456 | crtc = connector->encoder->crtc; |
457 | psb_intel_crtc = to_psb_intel_crtc(crtc); | 457 | gma_crtc = to_gma_crtc(crtc); |
458 | 458 | ||
459 | for (i = 0; i < 256; i++) | 459 | for (i = 0; i < 256; i++) |
460 | psb_intel_crtc->lut_adj[i] = lut_arg->lut[i]; | 460 | gma_crtc->lut_adj[i] = lut_arg->lut[i]; |
461 | 461 | ||
462 | psb_intel_crtc_load_lut(crtc); | 462 | gma_crtc_load_lut(crtc); |
463 | 463 | ||
464 | return 0; | 464 | return 0; |
465 | } | 465 | } |
diff --git a/drivers/gpu/drm/gma500/psb_drv.h b/drivers/gpu/drm/gma500/psb_drv.h index 984cacfcbaf2..4535ac7708f8 100644 --- a/drivers/gpu/drm/gma500/psb_drv.h +++ b/drivers/gpu/drm/gma500/psb_drv.h | |||
@@ -27,6 +27,7 @@ | |||
27 | #include <drm/gma_drm.h> | 27 | #include <drm/gma_drm.h> |
28 | #include "psb_reg.h" | 28 | #include "psb_reg.h" |
29 | #include "psb_intel_drv.h" | 29 | #include "psb_intel_drv.h" |
30 | #include "gma_display.h" | ||
30 | #include "intel_bios.h" | 31 | #include "intel_bios.h" |
31 | #include "gtt.h" | 32 | #include "gtt.h" |
32 | #include "power.h" | 33 | #include "power.h" |
@@ -46,6 +47,7 @@ enum { | |||
46 | #define IS_PSB(dev) (((dev)->pci_device & 0xfffe) == 0x8108) | 47 | #define IS_PSB(dev) (((dev)->pci_device & 0xfffe) == 0x8108) |
47 | #define IS_MRST(dev) (((dev)->pci_device & 0xfffc) == 0x4100) | 48 | #define IS_MRST(dev) (((dev)->pci_device & 0xfffc) == 0x4100) |
48 | #define IS_MFLD(dev) (((dev)->pci_device & 0xfff8) == 0x0130) | 49 | #define IS_MFLD(dev) (((dev)->pci_device & 0xfff8) == 0x0130) |
50 | #define IS_CDV(dev) (((dev)->pci_device & 0xfff0) == 0x0be0) | ||
49 | 51 | ||
50 | /* | 52 | /* |
51 | * Driver definitions | 53 | * Driver definitions |
@@ -675,6 +677,7 @@ struct psb_ops { | |||
675 | /* Sub functions */ | 677 | /* Sub functions */ |
676 | struct drm_crtc_helper_funcs const *crtc_helper; | 678 | struct drm_crtc_helper_funcs const *crtc_helper; |
677 | struct drm_crtc_funcs const *crtc_funcs; | 679 | struct drm_crtc_funcs const *crtc_funcs; |
680 | const struct gma_clock_funcs *clock_funcs; | ||
678 | 681 | ||
679 | /* Setup hooks */ | 682 | /* Setup hooks */ |
680 | int (*chip_setup)(struct drm_device *dev); | 683 | int (*chip_setup)(struct drm_device *dev); |
@@ -692,6 +695,8 @@ struct psb_ops { | |||
692 | int (*restore_regs)(struct drm_device *dev); | 695 | int (*restore_regs)(struct drm_device *dev); |
693 | int (*power_up)(struct drm_device *dev); | 696 | int (*power_up)(struct drm_device *dev); |
694 | int (*power_down)(struct drm_device *dev); | 697 | int (*power_down)(struct drm_device *dev); |
698 | void (*update_wm)(struct drm_device *dev, struct drm_crtc *crtc); | ||
699 | void (*disable_sr)(struct drm_device *dev); | ||
695 | 700 | ||
696 | void (*lvds_bl_power)(struct drm_device *dev, bool on); | 701 | void (*lvds_bl_power)(struct drm_device *dev, bool on); |
697 | #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE | 702 | #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE |
diff --git a/drivers/gpu/drm/gma500/psb_intel_display.c b/drivers/gpu/drm/gma500/psb_intel_display.c index 6666493789d1..97f8a03fee43 100644 --- a/drivers/gpu/drm/gma500/psb_intel_display.c +++ b/drivers/gpu/drm/gma500/psb_intel_display.c | |||
@@ -19,46 +19,19 @@ | |||
19 | */ | 19 | */ |
20 | 20 | ||
21 | #include <linux/i2c.h> | 21 | #include <linux/i2c.h> |
22 | #include <linux/pm_runtime.h> | ||
23 | 22 | ||
24 | #include <drm/drmP.h> | 23 | #include <drm/drmP.h> |
25 | #include "framebuffer.h" | 24 | #include "framebuffer.h" |
26 | #include "psb_drv.h" | 25 | #include "psb_drv.h" |
27 | #include "psb_intel_drv.h" | 26 | #include "psb_intel_drv.h" |
28 | #include "psb_intel_reg.h" | 27 | #include "psb_intel_reg.h" |
29 | #include "psb_intel_display.h" | 28 | #include "gma_display.h" |
30 | #include "power.h" | 29 | #include "power.h" |
31 | 30 | ||
32 | struct psb_intel_clock_t { | ||
33 | /* given values */ | ||
34 | int n; | ||
35 | int m1, m2; | ||
36 | int p1, p2; | ||
37 | /* derived values */ | ||
38 | int dot; | ||
39 | int vco; | ||
40 | int m; | ||
41 | int p; | ||
42 | }; | ||
43 | |||
44 | struct psb_intel_range_t { | ||
45 | int min, max; | ||
46 | }; | ||
47 | |||
48 | struct psb_intel_p2_t { | ||
49 | int dot_limit; | ||
50 | int p2_slow, p2_fast; | ||
51 | }; | ||
52 | |||
53 | struct psb_intel_limit_t { | ||
54 | struct psb_intel_range_t dot, vco, n, m, m1, m2, p, p1; | ||
55 | struct psb_intel_p2_t p2; | ||
56 | }; | ||
57 | |||
58 | #define INTEL_LIMIT_I9XX_SDVO_DAC 0 | 31 | #define INTEL_LIMIT_I9XX_SDVO_DAC 0 |
59 | #define INTEL_LIMIT_I9XX_LVDS 1 | 32 | #define INTEL_LIMIT_I9XX_LVDS 1 |
60 | 33 | ||
61 | static const struct psb_intel_limit_t psb_intel_limits[] = { | 34 | static const struct gma_limit_t psb_intel_limits[] = { |
62 | { /* INTEL_LIMIT_I9XX_SDVO_DAC */ | 35 | { /* INTEL_LIMIT_I9XX_SDVO_DAC */ |
63 | .dot = {.min = 20000, .max = 400000}, | 36 | .dot = {.min = 20000, .max = 400000}, |
64 | .vco = {.min = 1400000, .max = 2800000}, | 37 | .vco = {.min = 1400000, .max = 2800000}, |
@@ -68,8 +41,8 @@ static const struct psb_intel_limit_t psb_intel_limits[] = { | |||
68 | .m2 = {.min = 3, .max = 7}, | 41 | .m2 = {.min = 3, .max = 7}, |
69 | .p = {.min = 5, .max = 80}, | 42 | .p = {.min = 5, .max = 80}, |
70 | .p1 = {.min = 1, .max = 8}, | 43 | .p1 = {.min = 1, .max = 8}, |
71 | .p2 = {.dot_limit = 200000, | 44 | .p2 = {.dot_limit = 200000, .p2_slow = 10, .p2_fast = 5}, |
72 | .p2_slow = 10, .p2_fast = 5}, | 45 | .find_pll = gma_find_best_pll, |
73 | }, | 46 | }, |
74 | { /* INTEL_LIMIT_I9XX_LVDS */ | 47 | { /* INTEL_LIMIT_I9XX_LVDS */ |
75 | .dot = {.min = 20000, .max = 400000}, | 48 | .dot = {.min = 20000, .max = 400000}, |
@@ -83,23 +56,24 @@ static const struct psb_intel_limit_t psb_intel_limits[] = { | |||
83 | /* The single-channel range is 25-112Mhz, and dual-channel | 56 | /* The single-channel range is 25-112Mhz, and dual-channel |
84 | * is 80-224Mhz. Prefer single channel as much as possible. | 57 | * is 80-224Mhz. Prefer single channel as much as possible. |
85 | */ | 58 | */ |
86 | .p2 = {.dot_limit = 112000, | 59 | .p2 = {.dot_limit = 112000, .p2_slow = 14, .p2_fast = 7}, |
87 | .p2_slow = 14, .p2_fast = 7}, | 60 | .find_pll = gma_find_best_pll, |
88 | }, | 61 | }, |
89 | }; | 62 | }; |
90 | 63 | ||
91 | static const struct psb_intel_limit_t *psb_intel_limit(struct drm_crtc *crtc) | 64 | static const struct gma_limit_t *psb_intel_limit(struct drm_crtc *crtc, |
65 | int refclk) | ||
92 | { | 66 | { |
93 | const struct psb_intel_limit_t *limit; | 67 | const struct gma_limit_t *limit; |
94 | 68 | ||
95 | if (psb_intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | 69 | if (gma_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
96 | limit = &psb_intel_limits[INTEL_LIMIT_I9XX_LVDS]; | 70 | limit = &psb_intel_limits[INTEL_LIMIT_I9XX_LVDS]; |
97 | else | 71 | else |
98 | limit = &psb_intel_limits[INTEL_LIMIT_I9XX_SDVO_DAC]; | 72 | limit = &psb_intel_limits[INTEL_LIMIT_I9XX_SDVO_DAC]; |
99 | return limit; | 73 | return limit; |
100 | } | 74 | } |
101 | 75 | ||
102 | static void psb_intel_clock(int refclk, struct psb_intel_clock_t *clock) | 76 | static void psb_intel_clock(int refclk, struct gma_clock_t *clock) |
103 | { | 77 | { |
104 | clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); | 78 | clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); |
105 | clock->p = clock->p1 * clock->p2; | 79 | clock->p = clock->p1 * clock->p2; |
@@ -108,353 +82,6 @@ static void psb_intel_clock(int refclk, struct psb_intel_clock_t *clock) | |||
108 | } | 82 | } |
109 | 83 | ||
110 | /** | 84 | /** |
111 | * Returns whether any output on the specified pipe is of the specified type | ||
112 | */ | ||
113 | bool psb_intel_pipe_has_type(struct drm_crtc *crtc, int type) | ||
114 | { | ||
115 | struct drm_device *dev = crtc->dev; | ||
116 | struct drm_mode_config *mode_config = &dev->mode_config; | ||
117 | struct drm_connector *l_entry; | ||
118 | |||
119 | list_for_each_entry(l_entry, &mode_config->connector_list, head) { | ||
120 | if (l_entry->encoder && l_entry->encoder->crtc == crtc) { | ||
121 | struct psb_intel_encoder *psb_intel_encoder = | ||
122 | psb_intel_attached_encoder(l_entry); | ||
123 | if (psb_intel_encoder->type == type) | ||
124 | return true; | ||
125 | } | ||
126 | } | ||
127 | return false; | ||
128 | } | ||
129 | |||
130 | #define INTELPllInvalid(s) { /* ErrorF (s) */; return false; } | ||
131 | /** | ||
132 | * Returns whether the given set of divisors are valid for a given refclk with | ||
133 | * the given connectors. | ||
134 | */ | ||
135 | |||
136 | static bool psb_intel_PLL_is_valid(struct drm_crtc *crtc, | ||
137 | struct psb_intel_clock_t *clock) | ||
138 | { | ||
139 | const struct psb_intel_limit_t *limit = psb_intel_limit(crtc); | ||
140 | |||
141 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) | ||
142 | INTELPllInvalid("p1 out of range\n"); | ||
143 | if (clock->p < limit->p.min || limit->p.max < clock->p) | ||
144 | INTELPllInvalid("p out of range\n"); | ||
145 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) | ||
146 | INTELPllInvalid("m2 out of range\n"); | ||
147 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) | ||
148 | INTELPllInvalid("m1 out of range\n"); | ||
149 | if (clock->m1 <= clock->m2) | ||
150 | INTELPllInvalid("m1 <= m2\n"); | ||
151 | if (clock->m < limit->m.min || limit->m.max < clock->m) | ||
152 | INTELPllInvalid("m out of range\n"); | ||
153 | if (clock->n < limit->n.min || limit->n.max < clock->n) | ||
154 | INTELPllInvalid("n out of range\n"); | ||
155 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) | ||
156 | INTELPllInvalid("vco out of range\n"); | ||
157 | /* XXX: We may need to be checking "Dot clock" | ||
158 | * depending on the multiplier, connector, etc., | ||
159 | * rather than just a single range. | ||
160 | */ | ||
161 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | ||
162 | INTELPllInvalid("dot out of range\n"); | ||
163 | |||
164 | return true; | ||
165 | } | ||
166 | |||
167 | /** | ||
168 | * Returns a set of divisors for the desired target clock with the given | ||
169 | * refclk, or FALSE. The returned values represent the clock equation: | ||
170 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | ||
171 | */ | ||
172 | static bool psb_intel_find_best_PLL(struct drm_crtc *crtc, int target, | ||
173 | int refclk, | ||
174 | struct psb_intel_clock_t *best_clock) | ||
175 | { | ||
176 | struct drm_device *dev = crtc->dev; | ||
177 | struct psb_intel_clock_t clock; | ||
178 | const struct psb_intel_limit_t *limit = psb_intel_limit(crtc); | ||
179 | int err = target; | ||
180 | |||
181 | if (psb_intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && | ||
182 | (REG_READ(LVDS) & LVDS_PORT_EN) != 0) { | ||
183 | /* | ||
184 | * For LVDS, if the panel is on, just rely on its current | ||
185 | * settings for dual-channel. We haven't figured out how to | ||
186 | * reliably set up different single/dual channel state, if we | ||
187 | * even can. | ||
188 | */ | ||
189 | if ((REG_READ(LVDS) & LVDS_CLKB_POWER_MASK) == | ||
190 | LVDS_CLKB_POWER_UP) | ||
191 | clock.p2 = limit->p2.p2_fast; | ||
192 | else | ||
193 | clock.p2 = limit->p2.p2_slow; | ||
194 | } else { | ||
195 | if (target < limit->p2.dot_limit) | ||
196 | clock.p2 = limit->p2.p2_slow; | ||
197 | else | ||
198 | clock.p2 = limit->p2.p2_fast; | ||
199 | } | ||
200 | |||
201 | memset(best_clock, 0, sizeof(*best_clock)); | ||
202 | |||
203 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; | ||
204 | clock.m1++) { | ||
205 | for (clock.m2 = limit->m2.min; | ||
206 | clock.m2 < clock.m1 && clock.m2 <= limit->m2.max; | ||
207 | clock.m2++) { | ||
208 | for (clock.n = limit->n.min; | ||
209 | clock.n <= limit->n.max; clock.n++) { | ||
210 | for (clock.p1 = limit->p1.min; | ||
211 | clock.p1 <= limit->p1.max; | ||
212 | clock.p1++) { | ||
213 | int this_err; | ||
214 | |||
215 | psb_intel_clock(refclk, &clock); | ||
216 | |||
217 | if (!psb_intel_PLL_is_valid | ||
218 | (crtc, &clock)) | ||
219 | continue; | ||
220 | |||
221 | this_err = abs(clock.dot - target); | ||
222 | if (this_err < err) { | ||
223 | *best_clock = clock; | ||
224 | err = this_err; | ||
225 | } | ||
226 | } | ||
227 | } | ||
228 | } | ||
229 | } | ||
230 | |||
231 | return err != target; | ||
232 | } | ||
233 | |||
234 | void psb_intel_wait_for_vblank(struct drm_device *dev) | ||
235 | { | ||
236 | /* Wait for 20ms, i.e. one cycle at 50hz. */ | ||
237 | mdelay(20); | ||
238 | } | ||
239 | |||
240 | static int psb_intel_pipe_set_base(struct drm_crtc *crtc, | ||
241 | int x, int y, struct drm_framebuffer *old_fb) | ||
242 | { | ||
243 | struct drm_device *dev = crtc->dev; | ||
244 | struct drm_psb_private *dev_priv = dev->dev_private; | ||
245 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); | ||
246 | struct psb_framebuffer *psbfb = to_psb_fb(crtc->fb); | ||
247 | int pipe = psb_intel_crtc->pipe; | ||
248 | const struct psb_offset *map = &dev_priv->regmap[pipe]; | ||
249 | unsigned long start, offset; | ||
250 | u32 dspcntr; | ||
251 | int ret = 0; | ||
252 | |||
253 | if (!gma_power_begin(dev, true)) | ||
254 | return 0; | ||
255 | |||
256 | /* no fb bound */ | ||
257 | if (!crtc->fb) { | ||
258 | dev_dbg(dev->dev, "No FB bound\n"); | ||
259 | goto psb_intel_pipe_cleaner; | ||
260 | } | ||
261 | |||
262 | /* We are displaying this buffer, make sure it is actually loaded | ||
263 | into the GTT */ | ||
264 | ret = psb_gtt_pin(psbfb->gtt); | ||
265 | if (ret < 0) | ||
266 | goto psb_intel_pipe_set_base_exit; | ||
267 | start = psbfb->gtt->offset; | ||
268 | |||
269 | offset = y * crtc->fb->pitches[0] + x * (crtc->fb->bits_per_pixel / 8); | ||
270 | |||
271 | REG_WRITE(map->stride, crtc->fb->pitches[0]); | ||
272 | |||
273 | dspcntr = REG_READ(map->cntr); | ||
274 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | ||
275 | |||
276 | switch (crtc->fb->bits_per_pixel) { | ||
277 | case 8: | ||
278 | dspcntr |= DISPPLANE_8BPP; | ||
279 | break; | ||
280 | case 16: | ||
281 | if (crtc->fb->depth == 15) | ||
282 | dspcntr |= DISPPLANE_15_16BPP; | ||
283 | else | ||
284 | dspcntr |= DISPPLANE_16BPP; | ||
285 | break; | ||
286 | case 24: | ||
287 | case 32: | ||
288 | dspcntr |= DISPPLANE_32BPP_NO_ALPHA; | ||
289 | break; | ||
290 | default: | ||
291 | dev_err(dev->dev, "Unknown color depth\n"); | ||
292 | ret = -EINVAL; | ||
293 | psb_gtt_unpin(psbfb->gtt); | ||
294 | goto psb_intel_pipe_set_base_exit; | ||
295 | } | ||
296 | REG_WRITE(map->cntr, dspcntr); | ||
297 | |||
298 | REG_WRITE(map->base, start + offset); | ||
299 | REG_READ(map->base); | ||
300 | |||
301 | psb_intel_pipe_cleaner: | ||
302 | /* If there was a previous display we can now unpin it */ | ||
303 | if (old_fb) | ||
304 | psb_gtt_unpin(to_psb_fb(old_fb)->gtt); | ||
305 | |||
306 | psb_intel_pipe_set_base_exit: | ||
307 | gma_power_end(dev); | ||
308 | return ret; | ||
309 | } | ||
310 | |||
311 | /** | ||
312 | * Sets the power management mode of the pipe and plane. | ||
313 | * | ||
314 | * This code should probably grow support for turning the cursor off and back | ||
315 | * on appropriately at the same time as we're turning the pipe off/on. | ||
316 | */ | ||
317 | static void psb_intel_crtc_dpms(struct drm_crtc *crtc, int mode) | ||
318 | { | ||
319 | struct drm_device *dev = crtc->dev; | ||
320 | struct drm_psb_private *dev_priv = dev->dev_private; | ||
321 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); | ||
322 | int pipe = psb_intel_crtc->pipe; | ||
323 | const struct psb_offset *map = &dev_priv->regmap[pipe]; | ||
324 | u32 temp; | ||
325 | |||
326 | /* XXX: When our outputs are all unaware of DPMS modes other than off | ||
327 | * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. | ||
328 | */ | ||
329 | switch (mode) { | ||
330 | case DRM_MODE_DPMS_ON: | ||
331 | case DRM_MODE_DPMS_STANDBY: | ||
332 | case DRM_MODE_DPMS_SUSPEND: | ||
333 | /* Enable the DPLL */ | ||
334 | temp = REG_READ(map->dpll); | ||
335 | if ((temp & DPLL_VCO_ENABLE) == 0) { | ||
336 | REG_WRITE(map->dpll, temp); | ||
337 | REG_READ(map->dpll); | ||
338 | /* Wait for the clocks to stabilize. */ | ||
339 | udelay(150); | ||
340 | REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); | ||
341 | REG_READ(map->dpll); | ||
342 | /* Wait for the clocks to stabilize. */ | ||
343 | udelay(150); | ||
344 | REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); | ||
345 | REG_READ(map->dpll); | ||
346 | /* Wait for the clocks to stabilize. */ | ||
347 | udelay(150); | ||
348 | } | ||
349 | |||
350 | /* Enable the pipe */ | ||
351 | temp = REG_READ(map->conf); | ||
352 | if ((temp & PIPEACONF_ENABLE) == 0) | ||
353 | REG_WRITE(map->conf, temp | PIPEACONF_ENABLE); | ||
354 | |||
355 | /* Enable the plane */ | ||
356 | temp = REG_READ(map->cntr); | ||
357 | if ((temp & DISPLAY_PLANE_ENABLE) == 0) { | ||
358 | REG_WRITE(map->cntr, | ||
359 | temp | DISPLAY_PLANE_ENABLE); | ||
360 | /* Flush the plane changes */ | ||
361 | REG_WRITE(map->base, REG_READ(map->base)); | ||
362 | } | ||
363 | |||
364 | psb_intel_crtc_load_lut(crtc); | ||
365 | |||
366 | /* Give the overlay scaler a chance to enable | ||
367 | * if it's on this pipe */ | ||
368 | /* psb_intel_crtc_dpms_video(crtc, true); TODO */ | ||
369 | break; | ||
370 | case DRM_MODE_DPMS_OFF: | ||
371 | /* Give the overlay scaler a chance to disable | ||
372 | * if it's on this pipe */ | ||
373 | /* psb_intel_crtc_dpms_video(crtc, FALSE); TODO */ | ||
374 | |||
375 | /* Disable the VGA plane that we never use */ | ||
376 | REG_WRITE(VGACNTRL, VGA_DISP_DISABLE); | ||
377 | |||
378 | /* Disable display plane */ | ||
379 | temp = REG_READ(map->cntr); | ||
380 | if ((temp & DISPLAY_PLANE_ENABLE) != 0) { | ||
381 | REG_WRITE(map->cntr, | ||
382 | temp & ~DISPLAY_PLANE_ENABLE); | ||
383 | /* Flush the plane changes */ | ||
384 | REG_WRITE(map->base, REG_READ(map->base)); | ||
385 | REG_READ(map->base); | ||
386 | } | ||
387 | |||
388 | /* Next, disable display pipes */ | ||
389 | temp = REG_READ(map->conf); | ||
390 | if ((temp & PIPEACONF_ENABLE) != 0) { | ||
391 | REG_WRITE(map->conf, temp & ~PIPEACONF_ENABLE); | ||
392 | REG_READ(map->conf); | ||
393 | } | ||
394 | |||
395 | /* Wait for vblank for the disable to take effect. */ | ||
396 | psb_intel_wait_for_vblank(dev); | ||
397 | |||
398 | temp = REG_READ(map->dpll); | ||
399 | if ((temp & DPLL_VCO_ENABLE) != 0) { | ||
400 | REG_WRITE(map->dpll, temp & ~DPLL_VCO_ENABLE); | ||
401 | REG_READ(map->dpll); | ||
402 | } | ||
403 | |||
404 | /* Wait for the clocks to turn off. */ | ||
405 | udelay(150); | ||
406 | break; | ||
407 | } | ||
408 | |||
409 | /*Set FIFO Watermarks*/ | ||
410 | REG_WRITE(DSPARB, 0x3F3E); | ||
411 | } | ||
412 | |||
413 | static void psb_intel_crtc_prepare(struct drm_crtc *crtc) | ||
414 | { | ||
415 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; | ||
416 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF); | ||
417 | } | ||
418 | |||
419 | static void psb_intel_crtc_commit(struct drm_crtc *crtc) | ||
420 | { | ||
421 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; | ||
422 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); | ||
423 | } | ||
424 | |||
425 | void psb_intel_encoder_prepare(struct drm_encoder *encoder) | ||
426 | { | ||
427 | struct drm_encoder_helper_funcs *encoder_funcs = | ||
428 | encoder->helper_private; | ||
429 | /* lvds has its own version of prepare see psb_intel_lvds_prepare */ | ||
430 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF); | ||
431 | } | ||
432 | |||
433 | void psb_intel_encoder_commit(struct drm_encoder *encoder) | ||
434 | { | ||
435 | struct drm_encoder_helper_funcs *encoder_funcs = | ||
436 | encoder->helper_private; | ||
437 | /* lvds has its own version of commit see psb_intel_lvds_commit */ | ||
438 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); | ||
439 | } | ||
440 | |||
441 | void psb_intel_encoder_destroy(struct drm_encoder *encoder) | ||
442 | { | ||
443 | struct psb_intel_encoder *intel_encoder = to_psb_intel_encoder(encoder); | ||
444 | |||
445 | drm_encoder_cleanup(encoder); | ||
446 | kfree(intel_encoder); | ||
447 | } | ||
448 | |||
449 | static bool psb_intel_crtc_mode_fixup(struct drm_crtc *crtc, | ||
450 | const struct drm_display_mode *mode, | ||
451 | struct drm_display_mode *adjusted_mode) | ||
452 | { | ||
453 | return true; | ||
454 | } | ||
455 | |||
456 | |||
457 | /** | ||
458 | * Return the pipe currently connected to the panel fitter, | 85 | * Return the pipe currently connected to the panel fitter, |
459 | * or -1 if the panel fitter is not present or not in use | 86 | * or -1 if the panel fitter is not present or not in use |
460 | */ | 87 | */ |
@@ -479,17 +106,18 @@ static int psb_intel_crtc_mode_set(struct drm_crtc *crtc, | |||
479 | { | 106 | { |
480 | struct drm_device *dev = crtc->dev; | 107 | struct drm_device *dev = crtc->dev; |
481 | struct drm_psb_private *dev_priv = dev->dev_private; | 108 | struct drm_psb_private *dev_priv = dev->dev_private; |
482 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); | 109 | struct gma_crtc *gma_crtc = to_gma_crtc(crtc); |
483 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; | 110 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; |
484 | int pipe = psb_intel_crtc->pipe; | 111 | int pipe = gma_crtc->pipe; |
485 | const struct psb_offset *map = &dev_priv->regmap[pipe]; | 112 | const struct psb_offset *map = &dev_priv->regmap[pipe]; |
486 | int refclk; | 113 | int refclk; |
487 | struct psb_intel_clock_t clock; | 114 | struct gma_clock_t clock; |
488 | u32 dpll = 0, fp = 0, dspcntr, pipeconf; | 115 | u32 dpll = 0, fp = 0, dspcntr, pipeconf; |
489 | bool ok, is_sdvo = false; | 116 | bool ok, is_sdvo = false; |
490 | bool is_lvds = false, is_tv = false; | 117 | bool is_lvds = false, is_tv = false; |
491 | struct drm_mode_config *mode_config = &dev->mode_config; | 118 | struct drm_mode_config *mode_config = &dev->mode_config; |
492 | struct drm_connector *connector; | 119 | struct drm_connector *connector; |
120 | const struct gma_limit_t *limit; | ||
493 | 121 | ||
494 | /* No scan out no play */ | 122 | /* No scan out no play */ |
495 | if (crtc->fb == NULL) { | 123 | if (crtc->fb == NULL) { |
@@ -498,14 +126,13 @@ static int psb_intel_crtc_mode_set(struct drm_crtc *crtc, | |||
498 | } | 126 | } |
499 | 127 | ||
500 | list_for_each_entry(connector, &mode_config->connector_list, head) { | 128 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
501 | struct psb_intel_encoder *psb_intel_encoder = | 129 | struct gma_encoder *gma_encoder = gma_attached_encoder(connector); |
502 | psb_intel_attached_encoder(connector); | ||
503 | 130 | ||
504 | if (!connector->encoder | 131 | if (!connector->encoder |
505 | || connector->encoder->crtc != crtc) | 132 | || connector->encoder->crtc != crtc) |
506 | continue; | 133 | continue; |
507 | 134 | ||
508 | switch (psb_intel_encoder->type) { | 135 | switch (gma_encoder->type) { |
509 | case INTEL_OUTPUT_LVDS: | 136 | case INTEL_OUTPUT_LVDS: |
510 | is_lvds = true; | 137 | is_lvds = true; |
511 | break; | 138 | break; |
@@ -520,10 +147,13 @@ static int psb_intel_crtc_mode_set(struct drm_crtc *crtc, | |||
520 | 147 | ||
521 | refclk = 96000; | 148 | refclk = 96000; |
522 | 149 | ||
523 | ok = psb_intel_find_best_PLL(crtc, adjusted_mode->clock, refclk, | 150 | limit = gma_crtc->clock_funcs->limit(crtc, refclk); |
151 | |||
152 | ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, | ||
524 | &clock); | 153 | &clock); |
525 | if (!ok) { | 154 | if (!ok) { |
526 | dev_err(dev->dev, "Couldn't find PLL settings for mode!\n"); | 155 | DRM_ERROR("Couldn't find PLL settings for mode! target: %d, actual: %d", |
156 | adjusted_mode->clock, clock.dot); | ||
527 | return 0; | 157 | return 0; |
528 | } | 158 | } |
529 | 159 | ||
@@ -661,368 +291,29 @@ static int psb_intel_crtc_mode_set(struct drm_crtc *crtc, | |||
661 | REG_WRITE(map->conf, pipeconf); | 291 | REG_WRITE(map->conf, pipeconf); |
662 | REG_READ(map->conf); | 292 | REG_READ(map->conf); |
663 | 293 | ||
664 | psb_intel_wait_for_vblank(dev); | 294 | gma_wait_for_vblank(dev); |
665 | 295 | ||
666 | REG_WRITE(map->cntr, dspcntr); | 296 | REG_WRITE(map->cntr, dspcntr); |
667 | 297 | ||
668 | /* Flush the plane changes */ | 298 | /* Flush the plane changes */ |
669 | crtc_funcs->mode_set_base(crtc, x, y, old_fb); | 299 | crtc_funcs->mode_set_base(crtc, x, y, old_fb); |
670 | 300 | ||
671 | psb_intel_wait_for_vblank(dev); | 301 | gma_wait_for_vblank(dev); |
672 | |||
673 | return 0; | ||
674 | } | ||
675 | |||
676 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | ||
677 | void psb_intel_crtc_load_lut(struct drm_crtc *crtc) | ||
678 | { | ||
679 | struct drm_device *dev = crtc->dev; | ||
680 | struct drm_psb_private *dev_priv = dev->dev_private; | ||
681 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); | ||
682 | const struct psb_offset *map = &dev_priv->regmap[psb_intel_crtc->pipe]; | ||
683 | int palreg = map->palette; | ||
684 | int i; | ||
685 | |||
686 | /* The clocks have to be on to load the palette. */ | ||
687 | if (!crtc->enabled) | ||
688 | return; | ||
689 | |||
690 | switch (psb_intel_crtc->pipe) { | ||
691 | case 0: | ||
692 | case 1: | ||
693 | break; | ||
694 | default: | ||
695 | dev_err(dev->dev, "Illegal Pipe Number.\n"); | ||
696 | return; | ||
697 | } | ||
698 | |||
699 | if (gma_power_begin(dev, false)) { | ||
700 | for (i = 0; i < 256; i++) { | ||
701 | REG_WRITE(palreg + 4 * i, | ||
702 | ((psb_intel_crtc->lut_r[i] + | ||
703 | psb_intel_crtc->lut_adj[i]) << 16) | | ||
704 | ((psb_intel_crtc->lut_g[i] + | ||
705 | psb_intel_crtc->lut_adj[i]) << 8) | | ||
706 | (psb_intel_crtc->lut_b[i] + | ||
707 | psb_intel_crtc->lut_adj[i])); | ||
708 | } | ||
709 | gma_power_end(dev); | ||
710 | } else { | ||
711 | for (i = 0; i < 256; i++) { | ||
712 | dev_priv->regs.pipe[0].palette[i] = | ||
713 | ((psb_intel_crtc->lut_r[i] + | ||
714 | psb_intel_crtc->lut_adj[i]) << 16) | | ||
715 | ((psb_intel_crtc->lut_g[i] + | ||
716 | psb_intel_crtc->lut_adj[i]) << 8) | | ||
717 | (psb_intel_crtc->lut_b[i] + | ||
718 | psb_intel_crtc->lut_adj[i]); | ||
719 | } | ||
720 | |||
721 | } | ||
722 | } | ||
723 | |||
724 | /** | ||
725 | * Save HW states of giving crtc | ||
726 | */ | ||
727 | static void psb_intel_crtc_save(struct drm_crtc *crtc) | ||
728 | { | ||
729 | struct drm_device *dev = crtc->dev; | ||
730 | struct drm_psb_private *dev_priv = dev->dev_private; | ||
731 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); | ||
732 | struct psb_intel_crtc_state *crtc_state = psb_intel_crtc->crtc_state; | ||
733 | const struct psb_offset *map = &dev_priv->regmap[psb_intel_crtc->pipe]; | ||
734 | uint32_t paletteReg; | ||
735 | int i; | ||
736 | |||
737 | if (!crtc_state) { | ||
738 | dev_err(dev->dev, "No CRTC state found\n"); | ||
739 | return; | ||
740 | } | ||
741 | |||
742 | crtc_state->saveDSPCNTR = REG_READ(map->cntr); | ||
743 | crtc_state->savePIPECONF = REG_READ(map->conf); | ||
744 | crtc_state->savePIPESRC = REG_READ(map->src); | ||
745 | crtc_state->saveFP0 = REG_READ(map->fp0); | ||
746 | crtc_state->saveFP1 = REG_READ(map->fp1); | ||
747 | crtc_state->saveDPLL = REG_READ(map->dpll); | ||
748 | crtc_state->saveHTOTAL = REG_READ(map->htotal); | ||
749 | crtc_state->saveHBLANK = REG_READ(map->hblank); | ||
750 | crtc_state->saveHSYNC = REG_READ(map->hsync); | ||
751 | crtc_state->saveVTOTAL = REG_READ(map->vtotal); | ||
752 | crtc_state->saveVBLANK = REG_READ(map->vblank); | ||
753 | crtc_state->saveVSYNC = REG_READ(map->vsync); | ||
754 | crtc_state->saveDSPSTRIDE = REG_READ(map->stride); | ||
755 | |||
756 | /*NOTE: DSPSIZE DSPPOS only for psb*/ | ||
757 | crtc_state->saveDSPSIZE = REG_READ(map->size); | ||
758 | crtc_state->saveDSPPOS = REG_READ(map->pos); | ||
759 | |||
760 | crtc_state->saveDSPBASE = REG_READ(map->base); | ||
761 | |||
762 | paletteReg = map->palette; | ||
763 | for (i = 0; i < 256; ++i) | ||
764 | crtc_state->savePalette[i] = REG_READ(paletteReg + (i << 2)); | ||
765 | } | ||
766 | |||
767 | /** | ||
768 | * Restore HW states of giving crtc | ||
769 | */ | ||
770 | static void psb_intel_crtc_restore(struct drm_crtc *crtc) | ||
771 | { | ||
772 | struct drm_device *dev = crtc->dev; | ||
773 | struct drm_psb_private *dev_priv = dev->dev_private; | ||
774 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); | ||
775 | struct psb_intel_crtc_state *crtc_state = psb_intel_crtc->crtc_state; | ||
776 | const struct psb_offset *map = &dev_priv->regmap[psb_intel_crtc->pipe]; | ||
777 | uint32_t paletteReg; | ||
778 | int i; | ||
779 | |||
780 | if (!crtc_state) { | ||
781 | dev_err(dev->dev, "No crtc state\n"); | ||
782 | return; | ||
783 | } | ||
784 | |||
785 | if (crtc_state->saveDPLL & DPLL_VCO_ENABLE) { | ||
786 | REG_WRITE(map->dpll, | ||
787 | crtc_state->saveDPLL & ~DPLL_VCO_ENABLE); | ||
788 | REG_READ(map->dpll); | ||
789 | udelay(150); | ||
790 | } | ||
791 | |||
792 | REG_WRITE(map->fp0, crtc_state->saveFP0); | ||
793 | REG_READ(map->fp0); | ||
794 | |||
795 | REG_WRITE(map->fp1, crtc_state->saveFP1); | ||
796 | REG_READ(map->fp1); | ||
797 | |||
798 | REG_WRITE(map->dpll, crtc_state->saveDPLL); | ||
799 | REG_READ(map->dpll); | ||
800 | udelay(150); | ||
801 | |||
802 | REG_WRITE(map->htotal, crtc_state->saveHTOTAL); | ||
803 | REG_WRITE(map->hblank, crtc_state->saveHBLANK); | ||
804 | REG_WRITE(map->hsync, crtc_state->saveHSYNC); | ||
805 | REG_WRITE(map->vtotal, crtc_state->saveVTOTAL); | ||
806 | REG_WRITE(map->vblank, crtc_state->saveVBLANK); | ||
807 | REG_WRITE(map->vsync, crtc_state->saveVSYNC); | ||
808 | REG_WRITE(map->stride, crtc_state->saveDSPSTRIDE); | ||
809 | |||
810 | REG_WRITE(map->size, crtc_state->saveDSPSIZE); | ||
811 | REG_WRITE(map->pos, crtc_state->saveDSPPOS); | ||
812 | |||
813 | REG_WRITE(map->src, crtc_state->savePIPESRC); | ||
814 | REG_WRITE(map->base, crtc_state->saveDSPBASE); | ||
815 | REG_WRITE(map->conf, crtc_state->savePIPECONF); | ||
816 | |||
817 | psb_intel_wait_for_vblank(dev); | ||
818 | |||
819 | REG_WRITE(map->cntr, crtc_state->saveDSPCNTR); | ||
820 | REG_WRITE(map->base, crtc_state->saveDSPBASE); | ||
821 | |||
822 | psb_intel_wait_for_vblank(dev); | ||
823 | |||
824 | paletteReg = map->palette; | ||
825 | for (i = 0; i < 256; ++i) | ||
826 | REG_WRITE(paletteReg + (i << 2), crtc_state->savePalette[i]); | ||
827 | } | ||
828 | |||
829 | static int psb_intel_crtc_cursor_set(struct drm_crtc *crtc, | ||
830 | struct drm_file *file_priv, | ||
831 | uint32_t handle, | ||
832 | uint32_t width, uint32_t height) | ||
833 | { | ||
834 | struct drm_device *dev = crtc->dev; | ||
835 | struct drm_psb_private *dev_priv = dev->dev_private; | ||
836 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); | ||
837 | int pipe = psb_intel_crtc->pipe; | ||
838 | uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR; | ||
839 | uint32_t base = (pipe == 0) ? CURABASE : CURBBASE; | ||
840 | uint32_t temp; | ||
841 | size_t addr = 0; | ||
842 | struct gtt_range *gt; | ||
843 | struct gtt_range *cursor_gt = psb_intel_crtc->cursor_gt; | ||
844 | struct drm_gem_object *obj; | ||
845 | void *tmp_dst, *tmp_src; | ||
846 | int ret = 0, i, cursor_pages; | ||
847 | |||
848 | /* if we want to turn of the cursor ignore width and height */ | ||
849 | if (!handle) { | ||
850 | /* turn off the cursor */ | ||
851 | temp = CURSOR_MODE_DISABLE; | ||
852 | |||
853 | if (gma_power_begin(dev, false)) { | ||
854 | REG_WRITE(control, temp); | ||
855 | REG_WRITE(base, 0); | ||
856 | gma_power_end(dev); | ||
857 | } | ||
858 | |||
859 | /* Unpin the old GEM object */ | ||
860 | if (psb_intel_crtc->cursor_obj) { | ||
861 | gt = container_of(psb_intel_crtc->cursor_obj, | ||
862 | struct gtt_range, gem); | ||
863 | psb_gtt_unpin(gt); | ||
864 | drm_gem_object_unreference(psb_intel_crtc->cursor_obj); | ||
865 | psb_intel_crtc->cursor_obj = NULL; | ||
866 | } | ||
867 | |||
868 | return 0; | ||
869 | } | ||
870 | |||
871 | /* Currently we only support 64x64 cursors */ | ||
872 | if (width != 64 || height != 64) { | ||
873 | dev_dbg(dev->dev, "we currently only support 64x64 cursors\n"); | ||
874 | return -EINVAL; | ||
875 | } | ||
876 | |||
877 | obj = drm_gem_object_lookup(dev, file_priv, handle); | ||
878 | if (!obj) | ||
879 | return -ENOENT; | ||
880 | |||
881 | if (obj->size < width * height * 4) { | ||
882 | dev_dbg(dev->dev, "buffer is to small\n"); | ||
883 | ret = -ENOMEM; | ||
884 | goto unref_cursor; | ||
885 | } | ||
886 | |||
887 | gt = container_of(obj, struct gtt_range, gem); | ||
888 | |||
889 | /* Pin the memory into the GTT */ | ||
890 | ret = psb_gtt_pin(gt); | ||
891 | if (ret) { | ||
892 | dev_err(dev->dev, "Can not pin down handle 0x%x\n", handle); | ||
893 | goto unref_cursor; | ||
894 | } | ||
895 | |||
896 | if (dev_priv->ops->cursor_needs_phys) { | ||
897 | if (cursor_gt == NULL) { | ||
898 | dev_err(dev->dev, "No hardware cursor mem available"); | ||
899 | ret = -ENOMEM; | ||
900 | goto unref_cursor; | ||
901 | } | ||
902 | |||
903 | /* Prevent overflow */ | ||
904 | if (gt->npage > 4) | ||
905 | cursor_pages = 4; | ||
906 | else | ||
907 | cursor_pages = gt->npage; | ||
908 | |||
909 | /* Copy the cursor to cursor mem */ | ||
910 | tmp_dst = dev_priv->vram_addr + cursor_gt->offset; | ||
911 | for (i = 0; i < cursor_pages; i++) { | ||
912 | tmp_src = kmap(gt->pages[i]); | ||
913 | memcpy(tmp_dst, tmp_src, PAGE_SIZE); | ||
914 | kunmap(gt->pages[i]); | ||
915 | tmp_dst += PAGE_SIZE; | ||
916 | } | ||
917 | |||
918 | addr = psb_intel_crtc->cursor_addr; | ||
919 | } else { | ||
920 | addr = gt->offset; /* Or resource.start ??? */ | ||
921 | psb_intel_crtc->cursor_addr = addr; | ||
922 | } | ||
923 | |||
924 | temp = 0; | ||
925 | /* set the pipe for the cursor */ | ||
926 | temp |= (pipe << 28); | ||
927 | temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; | ||
928 | |||
929 | if (gma_power_begin(dev, false)) { | ||
930 | REG_WRITE(control, temp); | ||
931 | REG_WRITE(base, addr); | ||
932 | gma_power_end(dev); | ||
933 | } | ||
934 | |||
935 | /* unpin the old bo */ | ||
936 | if (psb_intel_crtc->cursor_obj) { | ||
937 | gt = container_of(psb_intel_crtc->cursor_obj, | ||
938 | struct gtt_range, gem); | ||
939 | psb_gtt_unpin(gt); | ||
940 | drm_gem_object_unreference(psb_intel_crtc->cursor_obj); | ||
941 | } | ||
942 | |||
943 | psb_intel_crtc->cursor_obj = obj; | ||
944 | return ret; | ||
945 | |||
946 | unref_cursor: | ||
947 | drm_gem_object_unreference(obj); | ||
948 | return ret; | ||
949 | } | ||
950 | |||
951 | static int psb_intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) | ||
952 | { | ||
953 | struct drm_device *dev = crtc->dev; | ||
954 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); | ||
955 | int pipe = psb_intel_crtc->pipe; | ||
956 | uint32_t temp = 0; | ||
957 | uint32_t addr; | ||
958 | |||
959 | |||
960 | if (x < 0) { | ||
961 | temp |= (CURSOR_POS_SIGN << CURSOR_X_SHIFT); | ||
962 | x = -x; | ||
963 | } | ||
964 | if (y < 0) { | ||
965 | temp |= (CURSOR_POS_SIGN << CURSOR_Y_SHIFT); | ||
966 | y = -y; | ||
967 | } | ||
968 | |||
969 | temp |= ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT); | ||
970 | temp |= ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT); | ||
971 | |||
972 | addr = psb_intel_crtc->cursor_addr; | ||
973 | 302 | ||
974 | if (gma_power_begin(dev, false)) { | ||
975 | REG_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp); | ||
976 | REG_WRITE((pipe == 0) ? CURABASE : CURBBASE, addr); | ||
977 | gma_power_end(dev); | ||
978 | } | ||
979 | return 0; | 303 | return 0; |
980 | } | 304 | } |
981 | 305 | ||
982 | static void psb_intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, | ||
983 | u16 *green, u16 *blue, uint32_t type, uint32_t size) | ||
984 | { | ||
985 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); | ||
986 | int i; | ||
987 | |||
988 | if (size != 256) | ||
989 | return; | ||
990 | |||
991 | for (i = 0; i < 256; i++) { | ||
992 | psb_intel_crtc->lut_r[i] = red[i] >> 8; | ||
993 | psb_intel_crtc->lut_g[i] = green[i] >> 8; | ||
994 | psb_intel_crtc->lut_b[i] = blue[i] >> 8; | ||
995 | } | ||
996 | |||
997 | psb_intel_crtc_load_lut(crtc); | ||
998 | } | ||
999 | |||
1000 | static int psb_crtc_set_config(struct drm_mode_set *set) | ||
1001 | { | ||
1002 | int ret; | ||
1003 | struct drm_device *dev = set->crtc->dev; | ||
1004 | struct drm_psb_private *dev_priv = dev->dev_private; | ||
1005 | |||
1006 | if (!dev_priv->rpm_enabled) | ||
1007 | return drm_crtc_helper_set_config(set); | ||
1008 | |||
1009 | pm_runtime_forbid(&dev->pdev->dev); | ||
1010 | ret = drm_crtc_helper_set_config(set); | ||
1011 | pm_runtime_allow(&dev->pdev->dev); | ||
1012 | return ret; | ||
1013 | } | ||
1014 | |||
1015 | /* Returns the clock of the currently programmed mode of the given pipe. */ | 306 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
1016 | static int psb_intel_crtc_clock_get(struct drm_device *dev, | 307 | static int psb_intel_crtc_clock_get(struct drm_device *dev, |
1017 | struct drm_crtc *crtc) | 308 | struct drm_crtc *crtc) |
1018 | { | 309 | { |
1019 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); | 310 | struct gma_crtc *gma_crtc = to_gma_crtc(crtc); |
1020 | struct drm_psb_private *dev_priv = dev->dev_private; | 311 | struct drm_psb_private *dev_priv = dev->dev_private; |
1021 | int pipe = psb_intel_crtc->pipe; | 312 | int pipe = gma_crtc->pipe; |
1022 | const struct psb_offset *map = &dev_priv->regmap[pipe]; | 313 | const struct psb_offset *map = &dev_priv->regmap[pipe]; |
1023 | u32 dpll; | 314 | u32 dpll; |
1024 | u32 fp; | 315 | u32 fp; |
1025 | struct psb_intel_clock_t clock; | 316 | struct gma_clock_t clock; |
1026 | bool is_lvds; | 317 | bool is_lvds; |
1027 | struct psb_pipe *p = &dev_priv->regs.pipe[pipe]; | 318 | struct psb_pipe *p = &dev_priv->regs.pipe[pipe]; |
1028 | 319 | ||
@@ -1092,8 +383,8 @@ static int psb_intel_crtc_clock_get(struct drm_device *dev, | |||
1092 | struct drm_display_mode *psb_intel_crtc_mode_get(struct drm_device *dev, | 383 | struct drm_display_mode *psb_intel_crtc_mode_get(struct drm_device *dev, |
1093 | struct drm_crtc *crtc) | 384 | struct drm_crtc *crtc) |
1094 | { | 385 | { |
1095 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); | 386 | struct gma_crtc *gma_crtc = to_gma_crtc(crtc); |
1096 | int pipe = psb_intel_crtc->pipe; | 387 | int pipe = gma_crtc->pipe; |
1097 | struct drm_display_mode *mode; | 388 | struct drm_display_mode *mode; |
1098 | int htot; | 389 | int htot; |
1099 | int hsync; | 390 | int hsync; |
@@ -1136,58 +427,30 @@ struct drm_display_mode *psb_intel_crtc_mode_get(struct drm_device *dev, | |||
1136 | return mode; | 427 | return mode; |
1137 | } | 428 | } |
1138 | 429 | ||
1139 | static void psb_intel_crtc_destroy(struct drm_crtc *crtc) | ||
1140 | { | ||
1141 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); | ||
1142 | struct gtt_range *gt; | ||
1143 | |||
1144 | /* Unpin the old GEM object */ | ||
1145 | if (psb_intel_crtc->cursor_obj) { | ||
1146 | gt = container_of(psb_intel_crtc->cursor_obj, | ||
1147 | struct gtt_range, gem); | ||
1148 | psb_gtt_unpin(gt); | ||
1149 | drm_gem_object_unreference(psb_intel_crtc->cursor_obj); | ||
1150 | psb_intel_crtc->cursor_obj = NULL; | ||
1151 | } | ||
1152 | |||
1153 | if (psb_intel_crtc->cursor_gt != NULL) | ||
1154 | psb_gtt_free_range(crtc->dev, psb_intel_crtc->cursor_gt); | ||
1155 | kfree(psb_intel_crtc->crtc_state); | ||
1156 | drm_crtc_cleanup(crtc); | ||
1157 | kfree(psb_intel_crtc); | ||
1158 | } | ||
1159 | |||
1160 | static void psb_intel_crtc_disable(struct drm_crtc *crtc) | ||
1161 | { | ||
1162 | struct gtt_range *gt; | ||
1163 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; | ||
1164 | |||
1165 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF); | ||
1166 | |||
1167 | if (crtc->fb) { | ||
1168 | gt = to_psb_fb(crtc->fb)->gtt; | ||
1169 | psb_gtt_unpin(gt); | ||
1170 | } | ||
1171 | } | ||
1172 | |||
1173 | const struct drm_crtc_helper_funcs psb_intel_helper_funcs = { | 430 | const struct drm_crtc_helper_funcs psb_intel_helper_funcs = { |
1174 | .dpms = psb_intel_crtc_dpms, | 431 | .dpms = gma_crtc_dpms, |
1175 | .mode_fixup = psb_intel_crtc_mode_fixup, | 432 | .mode_fixup = gma_crtc_mode_fixup, |
1176 | .mode_set = psb_intel_crtc_mode_set, | 433 | .mode_set = psb_intel_crtc_mode_set, |
1177 | .mode_set_base = psb_intel_pipe_set_base, | 434 | .mode_set_base = gma_pipe_set_base, |
1178 | .prepare = psb_intel_crtc_prepare, | 435 | .prepare = gma_crtc_prepare, |
1179 | .commit = psb_intel_crtc_commit, | 436 | .commit = gma_crtc_commit, |
1180 | .disable = psb_intel_crtc_disable, | 437 | .disable = gma_crtc_disable, |
1181 | }; | 438 | }; |
1182 | 439 | ||
1183 | const struct drm_crtc_funcs psb_intel_crtc_funcs = { | 440 | const struct drm_crtc_funcs psb_intel_crtc_funcs = { |
1184 | .save = psb_intel_crtc_save, | 441 | .save = gma_crtc_save, |
1185 | .restore = psb_intel_crtc_restore, | 442 | .restore = gma_crtc_restore, |
1186 | .cursor_set = psb_intel_crtc_cursor_set, | 443 | .cursor_set = gma_crtc_cursor_set, |
1187 | .cursor_move = psb_intel_crtc_cursor_move, | 444 | .cursor_move = gma_crtc_cursor_move, |
1188 | .gamma_set = psb_intel_crtc_gamma_set, | 445 | .gamma_set = gma_crtc_gamma_set, |
1189 | .set_config = psb_crtc_set_config, | 446 | .set_config = gma_crtc_set_config, |
1190 | .destroy = psb_intel_crtc_destroy, | 447 | .destroy = gma_crtc_destroy, |
448 | }; | ||
449 | |||
450 | const struct gma_clock_funcs psb_clock_funcs = { | ||
451 | .clock = psb_intel_clock, | ||
452 | .limit = psb_intel_limit, | ||
453 | .pll_is_valid = gma_pll_is_valid, | ||
1191 | }; | 454 | }; |
1192 | 455 | ||
1193 | /* | 456 | /* |
@@ -1195,7 +458,7 @@ const struct drm_crtc_funcs psb_intel_crtc_funcs = { | |||
1195 | * to zero. This is a workaround for h/w defect on Oaktrail | 458 | * to zero. This is a workaround for h/w defect on Oaktrail |
1196 | */ | 459 | */ |
1197 | static void psb_intel_cursor_init(struct drm_device *dev, | 460 | static void psb_intel_cursor_init(struct drm_device *dev, |
1198 | struct psb_intel_crtc *psb_intel_crtc) | 461 | struct gma_crtc *gma_crtc) |
1199 | { | 462 | { |
1200 | struct drm_psb_private *dev_priv = dev->dev_private; | 463 | struct drm_psb_private *dev_priv = dev->dev_private; |
1201 | u32 control[3] = { CURACNTR, CURBCNTR, CURCCNTR }; | 464 | u32 control[3] = { CURACNTR, CURBCNTR, CURCCNTR }; |
@@ -1208,88 +471,87 @@ static void psb_intel_cursor_init(struct drm_device *dev, | |||
1208 | */ | 471 | */ |
1209 | cursor_gt = psb_gtt_alloc_range(dev, 4 * PAGE_SIZE, "cursor", 1); | 472 | cursor_gt = psb_gtt_alloc_range(dev, 4 * PAGE_SIZE, "cursor", 1); |
1210 | if (!cursor_gt) { | 473 | if (!cursor_gt) { |
1211 | psb_intel_crtc->cursor_gt = NULL; | 474 | gma_crtc->cursor_gt = NULL; |
1212 | goto out; | 475 | goto out; |
1213 | } | 476 | } |
1214 | psb_intel_crtc->cursor_gt = cursor_gt; | 477 | gma_crtc->cursor_gt = cursor_gt; |
1215 | psb_intel_crtc->cursor_addr = dev_priv->stolen_base + | 478 | gma_crtc->cursor_addr = dev_priv->stolen_base + |
1216 | cursor_gt->offset; | 479 | cursor_gt->offset; |
1217 | } else { | 480 | } else { |
1218 | psb_intel_crtc->cursor_gt = NULL; | 481 | gma_crtc->cursor_gt = NULL; |
1219 | } | 482 | } |
1220 | 483 | ||
1221 | out: | 484 | out: |
1222 | REG_WRITE(control[psb_intel_crtc->pipe], 0); | 485 | REG_WRITE(control[gma_crtc->pipe], 0); |
1223 | REG_WRITE(base[psb_intel_crtc->pipe], 0); | 486 | REG_WRITE(base[gma_crtc->pipe], 0); |
1224 | } | 487 | } |
1225 | 488 | ||
1226 | void psb_intel_crtc_init(struct drm_device *dev, int pipe, | 489 | void psb_intel_crtc_init(struct drm_device *dev, int pipe, |
1227 | struct psb_intel_mode_device *mode_dev) | 490 | struct psb_intel_mode_device *mode_dev) |
1228 | { | 491 | { |
1229 | struct drm_psb_private *dev_priv = dev->dev_private; | 492 | struct drm_psb_private *dev_priv = dev->dev_private; |
1230 | struct psb_intel_crtc *psb_intel_crtc; | 493 | struct gma_crtc *gma_crtc; |
1231 | int i; | 494 | int i; |
1232 | uint16_t *r_base, *g_base, *b_base; | 495 | uint16_t *r_base, *g_base, *b_base; |
1233 | 496 | ||
1234 | /* We allocate a extra array of drm_connector pointers | 497 | /* We allocate a extra array of drm_connector pointers |
1235 | * for fbdev after the crtc */ | 498 | * for fbdev after the crtc */ |
1236 | psb_intel_crtc = | 499 | gma_crtc = kzalloc(sizeof(struct gma_crtc) + |
1237 | kzalloc(sizeof(struct psb_intel_crtc) + | 500 | (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), |
1238 | (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), | 501 | GFP_KERNEL); |
1239 | GFP_KERNEL); | 502 | if (gma_crtc == NULL) |
1240 | if (psb_intel_crtc == NULL) | ||
1241 | return; | 503 | return; |
1242 | 504 | ||
1243 | psb_intel_crtc->crtc_state = | 505 | gma_crtc->crtc_state = |
1244 | kzalloc(sizeof(struct psb_intel_crtc_state), GFP_KERNEL); | 506 | kzalloc(sizeof(struct psb_intel_crtc_state), GFP_KERNEL); |
1245 | if (!psb_intel_crtc->crtc_state) { | 507 | if (!gma_crtc->crtc_state) { |
1246 | dev_err(dev->dev, "Crtc state error: No memory\n"); | 508 | dev_err(dev->dev, "Crtc state error: No memory\n"); |
1247 | kfree(psb_intel_crtc); | 509 | kfree(gma_crtc); |
1248 | return; | 510 | return; |
1249 | } | 511 | } |
1250 | 512 | ||
1251 | /* Set the CRTC operations from the chip specific data */ | 513 | /* Set the CRTC operations from the chip specific data */ |
1252 | drm_crtc_init(dev, &psb_intel_crtc->base, dev_priv->ops->crtc_funcs); | 514 | drm_crtc_init(dev, &gma_crtc->base, dev_priv->ops->crtc_funcs); |
1253 | 515 | ||
1254 | drm_mode_crtc_set_gamma_size(&psb_intel_crtc->base, 256); | 516 | /* Set the CRTC clock functions from chip specific data */ |
1255 | psb_intel_crtc->pipe = pipe; | 517 | gma_crtc->clock_funcs = dev_priv->ops->clock_funcs; |
1256 | psb_intel_crtc->plane = pipe; | ||
1257 | 518 | ||
1258 | r_base = psb_intel_crtc->base.gamma_store; | 519 | drm_mode_crtc_set_gamma_size(&gma_crtc->base, 256); |
520 | gma_crtc->pipe = pipe; | ||
521 | gma_crtc->plane = pipe; | ||
522 | |||
523 | r_base = gma_crtc->base.gamma_store; | ||
1259 | g_base = r_base + 256; | 524 | g_base = r_base + 256; |
1260 | b_base = g_base + 256; | 525 | b_base = g_base + 256; |
1261 | for (i = 0; i < 256; i++) { | 526 | for (i = 0; i < 256; i++) { |
1262 | psb_intel_crtc->lut_r[i] = i; | 527 | gma_crtc->lut_r[i] = i; |
1263 | psb_intel_crtc->lut_g[i] = i; | 528 | gma_crtc->lut_g[i] = i; |
1264 | psb_intel_crtc->lut_b[i] = i; | 529 | gma_crtc->lut_b[i] = i; |
1265 | r_base[i] = i << 8; | 530 | r_base[i] = i << 8; |
1266 | g_base[i] = i << 8; | 531 | g_base[i] = i << 8; |
1267 | b_base[i] = i << 8; | 532 | b_base[i] = i << 8; |
1268 | 533 | ||
1269 | psb_intel_crtc->lut_adj[i] = 0; | 534 | gma_crtc->lut_adj[i] = 0; |
1270 | } | 535 | } |
1271 | 536 | ||
1272 | psb_intel_crtc->mode_dev = mode_dev; | 537 | gma_crtc->mode_dev = mode_dev; |
1273 | psb_intel_crtc->cursor_addr = 0; | 538 | gma_crtc->cursor_addr = 0; |
1274 | 539 | ||
1275 | drm_crtc_helper_add(&psb_intel_crtc->base, | 540 | drm_crtc_helper_add(&gma_crtc->base, |
1276 | dev_priv->ops->crtc_helper); | 541 | dev_priv->ops->crtc_helper); |
1277 | 542 | ||
1278 | /* Setup the array of drm_connector pointer array */ | 543 | /* Setup the array of drm_connector pointer array */ |
1279 | psb_intel_crtc->mode_set.crtc = &psb_intel_crtc->base; | 544 | gma_crtc->mode_set.crtc = &gma_crtc->base; |
1280 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || | 545 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
1281 | dev_priv->plane_to_crtc_mapping[psb_intel_crtc->plane] != NULL); | 546 | dev_priv->plane_to_crtc_mapping[gma_crtc->plane] != NULL); |
1282 | dev_priv->plane_to_crtc_mapping[psb_intel_crtc->plane] = | 547 | dev_priv->plane_to_crtc_mapping[gma_crtc->plane] = &gma_crtc->base; |
1283 | &psb_intel_crtc->base; | 548 | dev_priv->pipe_to_crtc_mapping[gma_crtc->pipe] = &gma_crtc->base; |
1284 | dev_priv->pipe_to_crtc_mapping[psb_intel_crtc->pipe] = | 549 | gma_crtc->mode_set.connectors = (struct drm_connector **)(gma_crtc + 1); |
1285 | &psb_intel_crtc->base; | 550 | gma_crtc->mode_set.num_connectors = 0; |
1286 | psb_intel_crtc->mode_set.connectors = | 551 | psb_intel_cursor_init(dev, gma_crtc); |
1287 | (struct drm_connector **) (psb_intel_crtc + 1); | ||
1288 | psb_intel_crtc->mode_set.num_connectors = 0; | ||
1289 | psb_intel_cursor_init(dev, psb_intel_crtc); | ||
1290 | 552 | ||
1291 | /* Set to true so that the pipe is forced off on initial config. */ | 553 | /* Set to true so that the pipe is forced off on initial config. */ |
1292 | psb_intel_crtc->active = true; | 554 | gma_crtc->active = true; |
1293 | } | 555 | } |
1294 | 556 | ||
1295 | int psb_intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, | 557 | int psb_intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
@@ -1298,7 +560,7 @@ int psb_intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, | |||
1298 | struct drm_psb_private *dev_priv = dev->dev_private; | 560 | struct drm_psb_private *dev_priv = dev->dev_private; |
1299 | struct drm_psb_get_pipe_from_crtc_id_arg *pipe_from_crtc_id = data; | 561 | struct drm_psb_get_pipe_from_crtc_id_arg *pipe_from_crtc_id = data; |
1300 | struct drm_mode_object *drmmode_obj; | 562 | struct drm_mode_object *drmmode_obj; |
1301 | struct psb_intel_crtc *crtc; | 563 | struct gma_crtc *crtc; |
1302 | 564 | ||
1303 | if (!dev_priv) { | 565 | if (!dev_priv) { |
1304 | dev_err(dev->dev, "called with no initialization\n"); | 566 | dev_err(dev->dev, "called with no initialization\n"); |
@@ -1313,7 +575,7 @@ int psb_intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, | |||
1313 | return -EINVAL; | 575 | return -EINVAL; |
1314 | } | 576 | } |
1315 | 577 | ||
1316 | crtc = to_psb_intel_crtc(obj_to_crtc(drmmode_obj)); | 578 | crtc = to_gma_crtc(obj_to_crtc(drmmode_obj)); |
1317 | pipe_from_crtc_id->pipe = crtc->pipe; | 579 | pipe_from_crtc_id->pipe = crtc->pipe; |
1318 | 580 | ||
1319 | return 0; | 581 | return 0; |
@@ -1324,14 +586,14 @@ struct drm_crtc *psb_intel_get_crtc_from_pipe(struct drm_device *dev, int pipe) | |||
1324 | struct drm_crtc *crtc = NULL; | 586 | struct drm_crtc *crtc = NULL; |
1325 | 587 | ||
1326 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | 588 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
1327 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); | 589 | struct gma_crtc *gma_crtc = to_gma_crtc(crtc); |
1328 | if (psb_intel_crtc->pipe == pipe) | 590 | if (gma_crtc->pipe == pipe) |
1329 | break; | 591 | break; |
1330 | } | 592 | } |
1331 | return crtc; | 593 | return crtc; |
1332 | } | 594 | } |
1333 | 595 | ||
1334 | int psb_intel_connector_clones(struct drm_device *dev, int type_mask) | 596 | int gma_connector_clones(struct drm_device *dev, int type_mask) |
1335 | { | 597 | { |
1336 | int index_mask = 0; | 598 | int index_mask = 0; |
1337 | struct drm_connector *connector; | 599 | struct drm_connector *connector; |
@@ -1339,30 +601,10 @@ int psb_intel_connector_clones(struct drm_device *dev, int type_mask) | |||
1339 | 601 | ||
1340 | list_for_each_entry(connector, &dev->mode_config.connector_list, | 602 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
1341 | head) { | 603 | head) { |
1342 | struct psb_intel_encoder *psb_intel_encoder = | 604 | struct gma_encoder *gma_encoder = gma_attached_encoder(connector); |
1343 | psb_intel_attached_encoder(connector); | 605 | if (type_mask & (1 << gma_encoder->type)) |
1344 | if (type_mask & (1 << psb_intel_encoder->type)) | ||
1345 | index_mask |= (1 << entry); | 606 | index_mask |= (1 << entry); |
1346 | entry++; | 607 | entry++; |
1347 | } | 608 | } |
1348 | return index_mask; | 609 | return index_mask; |
1349 | } | 610 | } |
1350 | |||
1351 | /* current intel driver doesn't take advantage of encoders | ||
1352 | always give back the encoder for the connector | ||
1353 | */ | ||
1354 | struct drm_encoder *psb_intel_best_encoder(struct drm_connector *connector) | ||
1355 | { | ||
1356 | struct psb_intel_encoder *psb_intel_encoder = | ||
1357 | psb_intel_attached_encoder(connector); | ||
1358 | |||
1359 | return &psb_intel_encoder->base; | ||
1360 | } | ||
1361 | |||
1362 | void psb_intel_connector_attach_encoder(struct psb_intel_connector *connector, | ||
1363 | struct psb_intel_encoder *encoder) | ||
1364 | { | ||
1365 | connector->encoder = encoder; | ||
1366 | drm_mode_connector_attach_encoder(&connector->base, | ||
1367 | &encoder->base); | ||
1368 | } | ||
diff --git a/drivers/gpu/drm/gma500/psb_intel_drv.h b/drivers/gpu/drm/gma500/psb_intel_drv.h index 4dcae421a58d..bde27fdb41bf 100644 --- a/drivers/gpu/drm/gma500/psb_intel_drv.h +++ b/drivers/gpu/drm/gma500/psb_intel_drv.h | |||
@@ -24,6 +24,7 @@ | |||
24 | #include <drm/drm_crtc.h> | 24 | #include <drm/drm_crtc.h> |
25 | #include <drm/drm_crtc_helper.h> | 25 | #include <drm/drm_crtc_helper.h> |
26 | #include <linux/gpio.h> | 26 | #include <linux/gpio.h> |
27 | #include "gma_display.h" | ||
27 | 28 | ||
28 | /* | 29 | /* |
29 | * Display related stuff | 30 | * Display related stuff |
@@ -116,11 +117,11 @@ struct psb_intel_i2c_chan { | |||
116 | u8 slave_addr; | 117 | u8 slave_addr; |
117 | }; | 118 | }; |
118 | 119 | ||
119 | struct psb_intel_encoder { | 120 | struct gma_encoder { |
120 | struct drm_encoder base; | 121 | struct drm_encoder base; |
121 | int type; | 122 | int type; |
122 | bool needs_tv_clock; | 123 | bool needs_tv_clock; |
123 | void (*hot_plug)(struct psb_intel_encoder *); | 124 | void (*hot_plug)(struct gma_encoder *); |
124 | int crtc_mask; | 125 | int crtc_mask; |
125 | int clone_mask; | 126 | int clone_mask; |
126 | u32 ddi_select; /* Channel info */ | 127 | u32 ddi_select; /* Channel info */ |
@@ -136,9 +137,9 @@ struct psb_intel_encoder { | |||
136 | struct psb_intel_i2c_chan *ddc_bus; | 137 | struct psb_intel_i2c_chan *ddc_bus; |
137 | }; | 138 | }; |
138 | 139 | ||
139 | struct psb_intel_connector { | 140 | struct gma_connector { |
140 | struct drm_connector base; | 141 | struct drm_connector base; |
141 | struct psb_intel_encoder *encoder; | 142 | struct gma_encoder *encoder; |
142 | }; | 143 | }; |
143 | 144 | ||
144 | struct psb_intel_crtc_state { | 145 | struct psb_intel_crtc_state { |
@@ -161,7 +162,7 @@ struct psb_intel_crtc_state { | |||
161 | uint32_t savePalette[256]; | 162 | uint32_t savePalette[256]; |
162 | }; | 163 | }; |
163 | 164 | ||
164 | struct psb_intel_crtc { | 165 | struct gma_crtc { |
165 | struct drm_crtc base; | 166 | struct drm_crtc base; |
166 | int pipe; | 167 | int pipe; |
167 | int plane; | 168 | int plane; |
@@ -188,14 +189,16 @@ struct psb_intel_crtc { | |||
188 | 189 | ||
189 | /* Saved Crtc HW states */ | 190 | /* Saved Crtc HW states */ |
190 | struct psb_intel_crtc_state *crtc_state; | 191 | struct psb_intel_crtc_state *crtc_state; |
192 | |||
193 | const struct gma_clock_funcs *clock_funcs; | ||
191 | }; | 194 | }; |
192 | 195 | ||
193 | #define to_psb_intel_crtc(x) \ | 196 | #define to_gma_crtc(x) \ |
194 | container_of(x, struct psb_intel_crtc, base) | 197 | container_of(x, struct gma_crtc, base) |
195 | #define to_psb_intel_connector(x) \ | 198 | #define to_gma_connector(x) \ |
196 | container_of(x, struct psb_intel_connector, base) | 199 | container_of(x, struct gma_connector, base) |
197 | #define to_psb_intel_encoder(x) \ | 200 | #define to_gma_encoder(x) \ |
198 | container_of(x, struct psb_intel_encoder, base) | 201 | container_of(x, struct gma_encoder, base) |
199 | #define to_psb_intel_framebuffer(x) \ | 202 | #define to_psb_intel_framebuffer(x) \ |
200 | container_of(x, struct psb_intel_framebuffer, base) | 203 | container_of(x, struct psb_intel_framebuffer, base) |
201 | 204 | ||
@@ -223,27 +226,18 @@ extern void oaktrail_dsi_init(struct drm_device *dev, | |||
223 | extern void mid_dsi_init(struct drm_device *dev, | 226 | extern void mid_dsi_init(struct drm_device *dev, |
224 | struct psb_intel_mode_device *mode_dev, int dsi_num); | 227 | struct psb_intel_mode_device *mode_dev, int dsi_num); |
225 | 228 | ||
226 | extern void psb_intel_crtc_load_lut(struct drm_crtc *crtc); | 229 | extern struct drm_encoder *gma_best_encoder(struct drm_connector *connector); |
227 | extern void psb_intel_encoder_prepare(struct drm_encoder *encoder); | 230 | extern void gma_connector_attach_encoder(struct gma_connector *connector, |
228 | extern void psb_intel_encoder_commit(struct drm_encoder *encoder); | 231 | struct gma_encoder *encoder); |
229 | extern void psb_intel_encoder_destroy(struct drm_encoder *encoder); | ||
230 | 232 | ||
231 | static inline struct psb_intel_encoder *psb_intel_attached_encoder( | 233 | static inline struct gma_encoder *gma_attached_encoder( |
232 | struct drm_connector *connector) | 234 | struct drm_connector *connector) |
233 | { | 235 | { |
234 | return to_psb_intel_connector(connector)->encoder; | 236 | return to_gma_connector(connector)->encoder; |
235 | } | 237 | } |
236 | 238 | ||
237 | extern void psb_intel_connector_attach_encoder( | ||
238 | struct psb_intel_connector *connector, | ||
239 | struct psb_intel_encoder *encoder); | ||
240 | |||
241 | extern struct drm_encoder *psb_intel_best_encoder(struct drm_connector | ||
242 | *connector); | ||
243 | |||
244 | extern struct drm_display_mode *psb_intel_crtc_mode_get(struct drm_device *dev, | 239 | extern struct drm_display_mode *psb_intel_crtc_mode_get(struct drm_device *dev, |
245 | struct drm_crtc *crtc); | 240 | struct drm_crtc *crtc); |
246 | extern void psb_intel_wait_for_vblank(struct drm_device *dev); | ||
247 | extern int psb_intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, | 241 | extern int psb_intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
248 | struct drm_file *file_priv); | 242 | struct drm_file *file_priv); |
249 | extern struct drm_crtc *psb_intel_get_crtc_from_pipe(struct drm_device *dev, | 243 | extern struct drm_crtc *psb_intel_get_crtc_from_pipe(struct drm_device *dev, |
diff --git a/drivers/gpu/drm/gma500/psb_intel_lvds.c b/drivers/gpu/drm/gma500/psb_intel_lvds.c index 9fa5fa2e6192..32342f6990d9 100644 --- a/drivers/gpu/drm/gma500/psb_intel_lvds.c +++ b/drivers/gpu/drm/gma500/psb_intel_lvds.c | |||
@@ -267,10 +267,9 @@ static void psb_intel_lvds_save(struct drm_connector *connector) | |||
267 | struct drm_device *dev = connector->dev; | 267 | struct drm_device *dev = connector->dev; |
268 | struct drm_psb_private *dev_priv = | 268 | struct drm_psb_private *dev_priv = |
269 | (struct drm_psb_private *)dev->dev_private; | 269 | (struct drm_psb_private *)dev->dev_private; |
270 | struct psb_intel_encoder *psb_intel_encoder = | 270 | struct gma_encoder *gma_encoder = gma_attached_encoder(connector); |
271 | psb_intel_attached_encoder(connector); | ||
272 | struct psb_intel_lvds_priv *lvds_priv = | 271 | struct psb_intel_lvds_priv *lvds_priv = |
273 | (struct psb_intel_lvds_priv *)psb_intel_encoder->dev_priv; | 272 | (struct psb_intel_lvds_priv *)gma_encoder->dev_priv; |
274 | 273 | ||
275 | lvds_priv->savePP_ON = REG_READ(LVDSPP_ON); | 274 | lvds_priv->savePP_ON = REG_READ(LVDSPP_ON); |
276 | lvds_priv->savePP_OFF = REG_READ(LVDSPP_OFF); | 275 | lvds_priv->savePP_OFF = REG_READ(LVDSPP_OFF); |
@@ -307,10 +306,9 @@ static void psb_intel_lvds_restore(struct drm_connector *connector) | |||
307 | { | 306 | { |
308 | struct drm_device *dev = connector->dev; | 307 | struct drm_device *dev = connector->dev; |
309 | u32 pp_status; | 308 | u32 pp_status; |
310 | struct psb_intel_encoder *psb_intel_encoder = | 309 | struct gma_encoder *gma_encoder = gma_attached_encoder(connector); |
311 | psb_intel_attached_encoder(connector); | ||
312 | struct psb_intel_lvds_priv *lvds_priv = | 310 | struct psb_intel_lvds_priv *lvds_priv = |
313 | (struct psb_intel_lvds_priv *)psb_intel_encoder->dev_priv; | 311 | (struct psb_intel_lvds_priv *)gma_encoder->dev_priv; |
314 | 312 | ||
315 | dev_dbg(dev->dev, "(0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x)\n", | 313 | dev_dbg(dev->dev, "(0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x)\n", |
316 | lvds_priv->savePP_ON, | 314 | lvds_priv->savePP_ON, |
@@ -349,12 +347,11 @@ int psb_intel_lvds_mode_valid(struct drm_connector *connector, | |||
349 | struct drm_display_mode *mode) | 347 | struct drm_display_mode *mode) |
350 | { | 348 | { |
351 | struct drm_psb_private *dev_priv = connector->dev->dev_private; | 349 | struct drm_psb_private *dev_priv = connector->dev->dev_private; |
352 | struct psb_intel_encoder *psb_intel_encoder = | 350 | struct gma_encoder *gma_encoder = gma_attached_encoder(connector); |
353 | psb_intel_attached_encoder(connector); | ||
354 | struct drm_display_mode *fixed_mode = | 351 | struct drm_display_mode *fixed_mode = |
355 | dev_priv->mode_dev.panel_fixed_mode; | 352 | dev_priv->mode_dev.panel_fixed_mode; |
356 | 353 | ||
357 | if (psb_intel_encoder->type == INTEL_OUTPUT_MIPI2) | 354 | if (gma_encoder->type == INTEL_OUTPUT_MIPI2) |
358 | fixed_mode = dev_priv->mode_dev.panel_fixed_mode2; | 355 | fixed_mode = dev_priv->mode_dev.panel_fixed_mode2; |
359 | 356 | ||
360 | /* just in case */ | 357 | /* just in case */ |
@@ -381,22 +378,20 @@ bool psb_intel_lvds_mode_fixup(struct drm_encoder *encoder, | |||
381 | struct drm_device *dev = encoder->dev; | 378 | struct drm_device *dev = encoder->dev; |
382 | struct drm_psb_private *dev_priv = dev->dev_private; | 379 | struct drm_psb_private *dev_priv = dev->dev_private; |
383 | struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev; | 380 | struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev; |
384 | struct psb_intel_crtc *psb_intel_crtc = | 381 | struct gma_crtc *gma_crtc = to_gma_crtc(encoder->crtc); |
385 | to_psb_intel_crtc(encoder->crtc); | ||
386 | struct drm_encoder *tmp_encoder; | 382 | struct drm_encoder *tmp_encoder; |
387 | struct drm_display_mode *panel_fixed_mode = mode_dev->panel_fixed_mode; | 383 | struct drm_display_mode *panel_fixed_mode = mode_dev->panel_fixed_mode; |
388 | struct psb_intel_encoder *psb_intel_encoder = | 384 | struct gma_encoder *gma_encoder = to_gma_encoder(encoder); |
389 | to_psb_intel_encoder(encoder); | ||
390 | 385 | ||
391 | if (psb_intel_encoder->type == INTEL_OUTPUT_MIPI2) | 386 | if (gma_encoder->type == INTEL_OUTPUT_MIPI2) |
392 | panel_fixed_mode = mode_dev->panel_fixed_mode2; | 387 | panel_fixed_mode = mode_dev->panel_fixed_mode2; |
393 | 388 | ||
394 | /* PSB requires the LVDS is on pipe B, MRST has only one pipe anyway */ | 389 | /* PSB requires the LVDS is on pipe B, MRST has only one pipe anyway */ |
395 | if (!IS_MRST(dev) && psb_intel_crtc->pipe == 0) { | 390 | if (!IS_MRST(dev) && gma_crtc->pipe == 0) { |
396 | printk(KERN_ERR "Can't support LVDS on pipe A\n"); | 391 | printk(KERN_ERR "Can't support LVDS on pipe A\n"); |
397 | return false; | 392 | return false; |
398 | } | 393 | } |
399 | if (IS_MRST(dev) && psb_intel_crtc->pipe != 0) { | 394 | if (IS_MRST(dev) && gma_crtc->pipe != 0) { |
400 | printk(KERN_ERR "Must use PIPE A\n"); | 395 | printk(KERN_ERR "Must use PIPE A\n"); |
401 | return false; | 396 | return false; |
402 | } | 397 | } |
@@ -525,9 +520,8 @@ static int psb_intel_lvds_get_modes(struct drm_connector *connector) | |||
525 | struct drm_device *dev = connector->dev; | 520 | struct drm_device *dev = connector->dev; |
526 | struct drm_psb_private *dev_priv = dev->dev_private; | 521 | struct drm_psb_private *dev_priv = dev->dev_private; |
527 | struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev; | 522 | struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev; |
528 | struct psb_intel_encoder *psb_intel_encoder = | 523 | struct gma_encoder *gma_encoder = gma_attached_encoder(connector); |
529 | psb_intel_attached_encoder(connector); | 524 | struct psb_intel_lvds_priv *lvds_priv = gma_encoder->dev_priv; |
530 | struct psb_intel_lvds_priv *lvds_priv = psb_intel_encoder->dev_priv; | ||
531 | int ret = 0; | 525 | int ret = 0; |
532 | 526 | ||
533 | if (!IS_MRST(dev)) | 527 | if (!IS_MRST(dev)) |
@@ -564,9 +558,8 @@ static int psb_intel_lvds_get_modes(struct drm_connector *connector) | |||
564 | */ | 558 | */ |
565 | void psb_intel_lvds_destroy(struct drm_connector *connector) | 559 | void psb_intel_lvds_destroy(struct drm_connector *connector) |
566 | { | 560 | { |
567 | struct psb_intel_encoder *psb_intel_encoder = | 561 | struct gma_encoder *gma_encoder = gma_attached_encoder(connector); |
568 | psb_intel_attached_encoder(connector); | 562 | struct psb_intel_lvds_priv *lvds_priv = gma_encoder->dev_priv; |
569 | struct psb_intel_lvds_priv *lvds_priv = psb_intel_encoder->dev_priv; | ||
570 | 563 | ||
571 | if (lvds_priv->ddc_bus) | 564 | if (lvds_priv->ddc_bus) |
572 | psb_intel_i2c_destroy(lvds_priv->ddc_bus); | 565 | psb_intel_i2c_destroy(lvds_priv->ddc_bus); |
@@ -585,8 +578,7 @@ int psb_intel_lvds_set_property(struct drm_connector *connector, | |||
585 | return -1; | 578 | return -1; |
586 | 579 | ||
587 | if (!strcmp(property->name, "scaling mode")) { | 580 | if (!strcmp(property->name, "scaling mode")) { |
588 | struct psb_intel_crtc *crtc = | 581 | struct gma_crtc *crtc = to_gma_crtc(encoder->crtc); |
589 | to_psb_intel_crtc(encoder->crtc); | ||
590 | uint64_t curval; | 582 | uint64_t curval; |
591 | 583 | ||
592 | if (!crtc) | 584 | if (!crtc) |
@@ -656,7 +648,7 @@ const struct drm_connector_helper_funcs | |||
656 | psb_intel_lvds_connector_helper_funcs = { | 648 | psb_intel_lvds_connector_helper_funcs = { |
657 | .get_modes = psb_intel_lvds_get_modes, | 649 | .get_modes = psb_intel_lvds_get_modes, |
658 | .mode_valid = psb_intel_lvds_mode_valid, | 650 | .mode_valid = psb_intel_lvds_mode_valid, |
659 | .best_encoder = psb_intel_best_encoder, | 651 | .best_encoder = gma_best_encoder, |
660 | }; | 652 | }; |
661 | 653 | ||
662 | const struct drm_connector_funcs psb_intel_lvds_connector_funcs = { | 654 | const struct drm_connector_funcs psb_intel_lvds_connector_funcs = { |
@@ -691,8 +683,8 @@ const struct drm_encoder_funcs psb_intel_lvds_enc_funcs = { | |||
691 | void psb_intel_lvds_init(struct drm_device *dev, | 683 | void psb_intel_lvds_init(struct drm_device *dev, |
692 | struct psb_intel_mode_device *mode_dev) | 684 | struct psb_intel_mode_device *mode_dev) |
693 | { | 685 | { |
694 | struct psb_intel_encoder *psb_intel_encoder; | 686 | struct gma_encoder *gma_encoder; |
695 | struct psb_intel_connector *psb_intel_connector; | 687 | struct gma_connector *gma_connector; |
696 | struct psb_intel_lvds_priv *lvds_priv; | 688 | struct psb_intel_lvds_priv *lvds_priv; |
697 | struct drm_connector *connector; | 689 | struct drm_connector *connector; |
698 | struct drm_encoder *encoder; | 690 | struct drm_encoder *encoder; |
@@ -702,17 +694,15 @@ void psb_intel_lvds_init(struct drm_device *dev, | |||
702 | u32 lvds; | 694 | u32 lvds; |
703 | int pipe; | 695 | int pipe; |
704 | 696 | ||
705 | psb_intel_encoder = | 697 | gma_encoder = kzalloc(sizeof(struct gma_encoder), GFP_KERNEL); |
706 | kzalloc(sizeof(struct psb_intel_encoder), GFP_KERNEL); | 698 | if (!gma_encoder) { |
707 | if (!psb_intel_encoder) { | 699 | dev_err(dev->dev, "gma_encoder allocation error\n"); |
708 | dev_err(dev->dev, "psb_intel_encoder allocation error\n"); | ||
709 | return; | 700 | return; |
710 | } | 701 | } |
711 | 702 | ||
712 | psb_intel_connector = | 703 | gma_connector = kzalloc(sizeof(struct gma_connector), GFP_KERNEL); |
713 | kzalloc(sizeof(struct psb_intel_connector), GFP_KERNEL); | 704 | if (!gma_connector) { |
714 | if (!psb_intel_connector) { | 705 | dev_err(dev->dev, "gma_connector allocation error\n"); |
715 | dev_err(dev->dev, "psb_intel_connector allocation error\n"); | ||
716 | goto failed_encoder; | 706 | goto failed_encoder; |
717 | } | 707 | } |
718 | 708 | ||
@@ -722,10 +712,10 @@ void psb_intel_lvds_init(struct drm_device *dev, | |||
722 | goto failed_connector; | 712 | goto failed_connector; |
723 | } | 713 | } |
724 | 714 | ||
725 | psb_intel_encoder->dev_priv = lvds_priv; | 715 | gma_encoder->dev_priv = lvds_priv; |
726 | 716 | ||
727 | connector = &psb_intel_connector->base; | 717 | connector = &gma_connector->base; |
728 | encoder = &psb_intel_encoder->base; | 718 | encoder = &gma_encoder->base; |
729 | drm_connector_init(dev, connector, | 719 | drm_connector_init(dev, connector, |
730 | &psb_intel_lvds_connector_funcs, | 720 | &psb_intel_lvds_connector_funcs, |
731 | DRM_MODE_CONNECTOR_LVDS); | 721 | DRM_MODE_CONNECTOR_LVDS); |
@@ -734,9 +724,8 @@ void psb_intel_lvds_init(struct drm_device *dev, | |||
734 | &psb_intel_lvds_enc_funcs, | 724 | &psb_intel_lvds_enc_funcs, |
735 | DRM_MODE_ENCODER_LVDS); | 725 | DRM_MODE_ENCODER_LVDS); |
736 | 726 | ||
737 | psb_intel_connector_attach_encoder(psb_intel_connector, | 727 | gma_connector_attach_encoder(gma_connector, gma_encoder); |
738 | psb_intel_encoder); | 728 | gma_encoder->type = INTEL_OUTPUT_LVDS; |
739 | psb_intel_encoder->type = INTEL_OUTPUT_LVDS; | ||
740 | 729 | ||
741 | drm_encoder_helper_add(encoder, &psb_intel_lvds_helper_funcs); | 730 | drm_encoder_helper_add(encoder, &psb_intel_lvds_helper_funcs); |
742 | drm_connector_helper_add(connector, | 731 | drm_connector_helper_add(connector, |
@@ -851,8 +840,8 @@ failed_blc_i2c: | |||
851 | drm_encoder_cleanup(encoder); | 840 | drm_encoder_cleanup(encoder); |
852 | drm_connector_cleanup(connector); | 841 | drm_connector_cleanup(connector); |
853 | failed_connector: | 842 | failed_connector: |
854 | kfree(psb_intel_connector); | 843 | kfree(gma_connector); |
855 | failed_encoder: | 844 | failed_encoder: |
856 | kfree(psb_intel_encoder); | 845 | kfree(gma_encoder); |
857 | } | 846 | } |
858 | 847 | ||
diff --git a/drivers/gpu/drm/gma500/psb_intel_sdvo.c b/drivers/gpu/drm/gma500/psb_intel_sdvo.c index 19e36603b23b..77841a113617 100644 --- a/drivers/gpu/drm/gma500/psb_intel_sdvo.c +++ b/drivers/gpu/drm/gma500/psb_intel_sdvo.c | |||
@@ -65,7 +65,7 @@ static const char *tv_format_names[] = { | |||
65 | #define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names)) | 65 | #define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names)) |
66 | 66 | ||
67 | struct psb_intel_sdvo { | 67 | struct psb_intel_sdvo { |
68 | struct psb_intel_encoder base; | 68 | struct gma_encoder base; |
69 | 69 | ||
70 | struct i2c_adapter *i2c; | 70 | struct i2c_adapter *i2c; |
71 | u8 slave_addr; | 71 | u8 slave_addr; |
@@ -140,7 +140,7 @@ struct psb_intel_sdvo { | |||
140 | }; | 140 | }; |
141 | 141 | ||
142 | struct psb_intel_sdvo_connector { | 142 | struct psb_intel_sdvo_connector { |
143 | struct psb_intel_connector base; | 143 | struct gma_connector base; |
144 | 144 | ||
145 | /* Mark the type of connector */ | 145 | /* Mark the type of connector */ |
146 | uint16_t output_flag; | 146 | uint16_t output_flag; |
@@ -200,13 +200,13 @@ static struct psb_intel_sdvo *to_psb_intel_sdvo(struct drm_encoder *encoder) | |||
200 | 200 | ||
201 | static struct psb_intel_sdvo *intel_attached_sdvo(struct drm_connector *connector) | 201 | static struct psb_intel_sdvo *intel_attached_sdvo(struct drm_connector *connector) |
202 | { | 202 | { |
203 | return container_of(psb_intel_attached_encoder(connector), | 203 | return container_of(gma_attached_encoder(connector), |
204 | struct psb_intel_sdvo, base); | 204 | struct psb_intel_sdvo, base); |
205 | } | 205 | } |
206 | 206 | ||
207 | static struct psb_intel_sdvo_connector *to_psb_intel_sdvo_connector(struct drm_connector *connector) | 207 | static struct psb_intel_sdvo_connector *to_psb_intel_sdvo_connector(struct drm_connector *connector) |
208 | { | 208 | { |
209 | return container_of(to_psb_intel_connector(connector), struct psb_intel_sdvo_connector, base); | 209 | return container_of(to_gma_connector(connector), struct psb_intel_sdvo_connector, base); |
210 | } | 210 | } |
211 | 211 | ||
212 | static bool | 212 | static bool |
@@ -987,7 +987,7 @@ static void psb_intel_sdvo_mode_set(struct drm_encoder *encoder, | |||
987 | { | 987 | { |
988 | struct drm_device *dev = encoder->dev; | 988 | struct drm_device *dev = encoder->dev; |
989 | struct drm_crtc *crtc = encoder->crtc; | 989 | struct drm_crtc *crtc = encoder->crtc; |
990 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); | 990 | struct gma_crtc *gma_crtc = to_gma_crtc(crtc); |
991 | struct psb_intel_sdvo *psb_intel_sdvo = to_psb_intel_sdvo(encoder); | 991 | struct psb_intel_sdvo *psb_intel_sdvo = to_psb_intel_sdvo(encoder); |
992 | u32 sdvox; | 992 | u32 sdvox; |
993 | struct psb_intel_sdvo_in_out_map in_out; | 993 | struct psb_intel_sdvo_in_out_map in_out; |
@@ -1070,7 +1070,7 @@ static void psb_intel_sdvo_mode_set(struct drm_encoder *encoder, | |||
1070 | } | 1070 | } |
1071 | sdvox |= (9 << 19) | SDVO_BORDER_ENABLE; | 1071 | sdvox |= (9 << 19) | SDVO_BORDER_ENABLE; |
1072 | 1072 | ||
1073 | if (psb_intel_crtc->pipe == 1) | 1073 | if (gma_crtc->pipe == 1) |
1074 | sdvox |= SDVO_PIPE_B_SELECT; | 1074 | sdvox |= SDVO_PIPE_B_SELECT; |
1075 | if (psb_intel_sdvo->has_hdmi_audio) | 1075 | if (psb_intel_sdvo->has_hdmi_audio) |
1076 | sdvox |= SDVO_AUDIO_ENABLE; | 1076 | sdvox |= SDVO_AUDIO_ENABLE; |
@@ -1121,7 +1121,7 @@ static void psb_intel_sdvo_dpms(struct drm_encoder *encoder, int mode) | |||
1121 | if ((temp & SDVO_ENABLE) == 0) | 1121 | if ((temp & SDVO_ENABLE) == 0) |
1122 | psb_intel_sdvo_write_sdvox(psb_intel_sdvo, temp | SDVO_ENABLE); | 1122 | psb_intel_sdvo_write_sdvox(psb_intel_sdvo, temp | SDVO_ENABLE); |
1123 | for (i = 0; i < 2; i++) | 1123 | for (i = 0; i < 2; i++) |
1124 | psb_intel_wait_for_vblank(dev); | 1124 | gma_wait_for_vblank(dev); |
1125 | 1125 | ||
1126 | status = psb_intel_sdvo_get_trained_inputs(psb_intel_sdvo, &input1, &input2); | 1126 | status = psb_intel_sdvo_get_trained_inputs(psb_intel_sdvo, &input1, &input2); |
1127 | /* Warn if the device reported failure to sync. | 1127 | /* Warn if the device reported failure to sync. |
@@ -1836,10 +1836,8 @@ done: | |||
1836 | static void psb_intel_sdvo_save(struct drm_connector *connector) | 1836 | static void psb_intel_sdvo_save(struct drm_connector *connector) |
1837 | { | 1837 | { |
1838 | struct drm_device *dev = connector->dev; | 1838 | struct drm_device *dev = connector->dev; |
1839 | struct psb_intel_encoder *psb_intel_encoder = | 1839 | struct gma_encoder *gma_encoder = gma_attached_encoder(connector); |
1840 | psb_intel_attached_encoder(connector); | 1840 | struct psb_intel_sdvo *sdvo = to_psb_intel_sdvo(&gma_encoder->base); |
1841 | struct psb_intel_sdvo *sdvo = | ||
1842 | to_psb_intel_sdvo(&psb_intel_encoder->base); | ||
1843 | 1841 | ||
1844 | sdvo->saveSDVO = REG_READ(sdvo->sdvo_reg); | 1842 | sdvo->saveSDVO = REG_READ(sdvo->sdvo_reg); |
1845 | } | 1843 | } |
@@ -1847,8 +1845,7 @@ static void psb_intel_sdvo_save(struct drm_connector *connector) | |||
1847 | static void psb_intel_sdvo_restore(struct drm_connector *connector) | 1845 | static void psb_intel_sdvo_restore(struct drm_connector *connector) |
1848 | { | 1846 | { |
1849 | struct drm_device *dev = connector->dev; | 1847 | struct drm_device *dev = connector->dev; |
1850 | struct drm_encoder *encoder = | 1848 | struct drm_encoder *encoder = &gma_attached_encoder(connector)->base; |
1851 | &psb_intel_attached_encoder(connector)->base; | ||
1852 | struct psb_intel_sdvo *sdvo = to_psb_intel_sdvo(encoder); | 1849 | struct psb_intel_sdvo *sdvo = to_psb_intel_sdvo(encoder); |
1853 | struct drm_crtc *crtc = encoder->crtc; | 1850 | struct drm_crtc *crtc = encoder->crtc; |
1854 | 1851 | ||
@@ -1864,9 +1861,9 @@ static void psb_intel_sdvo_restore(struct drm_connector *connector) | |||
1864 | static const struct drm_encoder_helper_funcs psb_intel_sdvo_helper_funcs = { | 1861 | static const struct drm_encoder_helper_funcs psb_intel_sdvo_helper_funcs = { |
1865 | .dpms = psb_intel_sdvo_dpms, | 1862 | .dpms = psb_intel_sdvo_dpms, |
1866 | .mode_fixup = psb_intel_sdvo_mode_fixup, | 1863 | .mode_fixup = psb_intel_sdvo_mode_fixup, |
1867 | .prepare = psb_intel_encoder_prepare, | 1864 | .prepare = gma_encoder_prepare, |
1868 | .mode_set = psb_intel_sdvo_mode_set, | 1865 | .mode_set = psb_intel_sdvo_mode_set, |
1869 | .commit = psb_intel_encoder_commit, | 1866 | .commit = gma_encoder_commit, |
1870 | }; | 1867 | }; |
1871 | 1868 | ||
1872 | static const struct drm_connector_funcs psb_intel_sdvo_connector_funcs = { | 1869 | static const struct drm_connector_funcs psb_intel_sdvo_connector_funcs = { |
@@ -1882,7 +1879,7 @@ static const struct drm_connector_funcs psb_intel_sdvo_connector_funcs = { | |||
1882 | static const struct drm_connector_helper_funcs psb_intel_sdvo_connector_helper_funcs = { | 1879 | static const struct drm_connector_helper_funcs psb_intel_sdvo_connector_helper_funcs = { |
1883 | .get_modes = psb_intel_sdvo_get_modes, | 1880 | .get_modes = psb_intel_sdvo_get_modes, |
1884 | .mode_valid = psb_intel_sdvo_mode_valid, | 1881 | .mode_valid = psb_intel_sdvo_mode_valid, |
1885 | .best_encoder = psb_intel_best_encoder, | 1882 | .best_encoder = gma_best_encoder, |
1886 | }; | 1883 | }; |
1887 | 1884 | ||
1888 | static void psb_intel_sdvo_enc_destroy(struct drm_encoder *encoder) | 1885 | static void psb_intel_sdvo_enc_destroy(struct drm_encoder *encoder) |
@@ -1894,7 +1891,7 @@ static void psb_intel_sdvo_enc_destroy(struct drm_encoder *encoder) | |||
1894 | psb_intel_sdvo->sdvo_lvds_fixed_mode); | 1891 | psb_intel_sdvo->sdvo_lvds_fixed_mode); |
1895 | 1892 | ||
1896 | i2c_del_adapter(&psb_intel_sdvo->ddc); | 1893 | i2c_del_adapter(&psb_intel_sdvo->ddc); |
1897 | psb_intel_encoder_destroy(encoder); | 1894 | gma_encoder_destroy(encoder); |
1898 | } | 1895 | } |
1899 | 1896 | ||
1900 | static const struct drm_encoder_funcs psb_intel_sdvo_enc_funcs = { | 1897 | static const struct drm_encoder_funcs psb_intel_sdvo_enc_funcs = { |
@@ -2055,7 +2052,7 @@ psb_intel_sdvo_connector_init(struct psb_intel_sdvo_connector *connector, | |||
2055 | connector->base.base.doublescan_allowed = 0; | 2052 | connector->base.base.doublescan_allowed = 0; |
2056 | connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB; | 2053 | connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB; |
2057 | 2054 | ||
2058 | psb_intel_connector_attach_encoder(&connector->base, &encoder->base); | 2055 | gma_connector_attach_encoder(&connector->base, &encoder->base); |
2059 | drm_sysfs_connector_add(&connector->base.base); | 2056 | drm_sysfs_connector_add(&connector->base.base); |
2060 | } | 2057 | } |
2061 | 2058 | ||
@@ -2075,7 +2072,7 @@ psb_intel_sdvo_dvi_init(struct psb_intel_sdvo *psb_intel_sdvo, int device) | |||
2075 | { | 2072 | { |
2076 | struct drm_encoder *encoder = &psb_intel_sdvo->base.base; | 2073 | struct drm_encoder *encoder = &psb_intel_sdvo->base.base; |
2077 | struct drm_connector *connector; | 2074 | struct drm_connector *connector; |
2078 | struct psb_intel_connector *intel_connector; | 2075 | struct gma_connector *intel_connector; |
2079 | struct psb_intel_sdvo_connector *psb_intel_sdvo_connector; | 2076 | struct psb_intel_sdvo_connector *psb_intel_sdvo_connector; |
2080 | 2077 | ||
2081 | psb_intel_sdvo_connector = kzalloc(sizeof(struct psb_intel_sdvo_connector), GFP_KERNEL); | 2078 | psb_intel_sdvo_connector = kzalloc(sizeof(struct psb_intel_sdvo_connector), GFP_KERNEL); |
@@ -2115,7 +2112,7 @@ psb_intel_sdvo_tv_init(struct psb_intel_sdvo *psb_intel_sdvo, int type) | |||
2115 | { | 2112 | { |
2116 | struct drm_encoder *encoder = &psb_intel_sdvo->base.base; | 2113 | struct drm_encoder *encoder = &psb_intel_sdvo->base.base; |
2117 | struct drm_connector *connector; | 2114 | struct drm_connector *connector; |
2118 | struct psb_intel_connector *intel_connector; | 2115 | struct gma_connector *intel_connector; |
2119 | struct psb_intel_sdvo_connector *psb_intel_sdvo_connector; | 2116 | struct psb_intel_sdvo_connector *psb_intel_sdvo_connector; |
2120 | 2117 | ||
2121 | psb_intel_sdvo_connector = kzalloc(sizeof(struct psb_intel_sdvo_connector), GFP_KERNEL); | 2118 | psb_intel_sdvo_connector = kzalloc(sizeof(struct psb_intel_sdvo_connector), GFP_KERNEL); |
@@ -2154,7 +2151,7 @@ psb_intel_sdvo_analog_init(struct psb_intel_sdvo *psb_intel_sdvo, int device) | |||
2154 | { | 2151 | { |
2155 | struct drm_encoder *encoder = &psb_intel_sdvo->base.base; | 2152 | struct drm_encoder *encoder = &psb_intel_sdvo->base.base; |
2156 | struct drm_connector *connector; | 2153 | struct drm_connector *connector; |
2157 | struct psb_intel_connector *intel_connector; | 2154 | struct gma_connector *intel_connector; |
2158 | struct psb_intel_sdvo_connector *psb_intel_sdvo_connector; | 2155 | struct psb_intel_sdvo_connector *psb_intel_sdvo_connector; |
2159 | 2156 | ||
2160 | psb_intel_sdvo_connector = kzalloc(sizeof(struct psb_intel_sdvo_connector), GFP_KERNEL); | 2157 | psb_intel_sdvo_connector = kzalloc(sizeof(struct psb_intel_sdvo_connector), GFP_KERNEL); |
@@ -2188,7 +2185,7 @@ psb_intel_sdvo_lvds_init(struct psb_intel_sdvo *psb_intel_sdvo, int device) | |||
2188 | { | 2185 | { |
2189 | struct drm_encoder *encoder = &psb_intel_sdvo->base.base; | 2186 | struct drm_encoder *encoder = &psb_intel_sdvo->base.base; |
2190 | struct drm_connector *connector; | 2187 | struct drm_connector *connector; |
2191 | struct psb_intel_connector *intel_connector; | 2188 | struct gma_connector *intel_connector; |
2192 | struct psb_intel_sdvo_connector *psb_intel_sdvo_connector; | 2189 | struct psb_intel_sdvo_connector *psb_intel_sdvo_connector; |
2193 | 2190 | ||
2194 | psb_intel_sdvo_connector = kzalloc(sizeof(struct psb_intel_sdvo_connector), GFP_KERNEL); | 2191 | psb_intel_sdvo_connector = kzalloc(sizeof(struct psb_intel_sdvo_connector), GFP_KERNEL); |
@@ -2540,7 +2537,7 @@ psb_intel_sdvo_init_ddc_proxy(struct psb_intel_sdvo *sdvo, | |||
2540 | bool psb_intel_sdvo_init(struct drm_device *dev, int sdvo_reg) | 2537 | bool psb_intel_sdvo_init(struct drm_device *dev, int sdvo_reg) |
2541 | { | 2538 | { |
2542 | struct drm_psb_private *dev_priv = dev->dev_private; | 2539 | struct drm_psb_private *dev_priv = dev->dev_private; |
2543 | struct psb_intel_encoder *psb_intel_encoder; | 2540 | struct gma_encoder *gma_encoder; |
2544 | struct psb_intel_sdvo *psb_intel_sdvo; | 2541 | struct psb_intel_sdvo *psb_intel_sdvo; |
2545 | int i; | 2542 | int i; |
2546 | 2543 | ||
@@ -2557,9 +2554,9 @@ bool psb_intel_sdvo_init(struct drm_device *dev, int sdvo_reg) | |||
2557 | } | 2554 | } |
2558 | 2555 | ||
2559 | /* encoder type will be decided later */ | 2556 | /* encoder type will be decided later */ |
2560 | psb_intel_encoder = &psb_intel_sdvo->base; | 2557 | gma_encoder = &psb_intel_sdvo->base; |
2561 | psb_intel_encoder->type = INTEL_OUTPUT_SDVO; | 2558 | gma_encoder->type = INTEL_OUTPUT_SDVO; |
2562 | drm_encoder_init(dev, &psb_intel_encoder->base, &psb_intel_sdvo_enc_funcs, 0); | 2559 | drm_encoder_init(dev, &gma_encoder->base, &psb_intel_sdvo_enc_funcs, 0); |
2563 | 2560 | ||
2564 | /* Read the regs to test if we can talk to the device */ | 2561 | /* Read the regs to test if we can talk to the device */ |
2565 | for (i = 0; i < 0x40; i++) { | 2562 | for (i = 0; i < 0x40; i++) { |
@@ -2577,7 +2574,7 @@ bool psb_intel_sdvo_init(struct drm_device *dev, int sdvo_reg) | |||
2577 | else | 2574 | else |
2578 | dev_priv->hotplug_supported_mask |= SDVOC_HOTPLUG_INT_STATUS; | 2575 | dev_priv->hotplug_supported_mask |= SDVOC_HOTPLUG_INT_STATUS; |
2579 | 2576 | ||
2580 | drm_encoder_helper_add(&psb_intel_encoder->base, &psb_intel_sdvo_helper_funcs); | 2577 | drm_encoder_helper_add(&gma_encoder->base, &psb_intel_sdvo_helper_funcs); |
2581 | 2578 | ||
2582 | /* In default case sdvo lvds is false */ | 2579 | /* In default case sdvo lvds is false */ |
2583 | if (!psb_intel_sdvo_get_capabilities(psb_intel_sdvo, &psb_intel_sdvo->caps)) | 2580 | if (!psb_intel_sdvo_get_capabilities(psb_intel_sdvo, &psb_intel_sdvo->caps)) |
@@ -2620,7 +2617,7 @@ bool psb_intel_sdvo_init(struct drm_device *dev, int sdvo_reg) | |||
2620 | return true; | 2617 | return true; |
2621 | 2618 | ||
2622 | err: | 2619 | err: |
2623 | drm_encoder_cleanup(&psb_intel_encoder->base); | 2620 | drm_encoder_cleanup(&gma_encoder->base); |
2624 | i2c_del_adapter(&psb_intel_sdvo->ddc); | 2621 | i2c_del_adapter(&psb_intel_sdvo->ddc); |
2625 | kfree(psb_intel_sdvo); | 2622 | kfree(psb_intel_sdvo); |
2626 | 2623 | ||