path: root/shared-core/nouveau_fifo.c

/* 
 * Copyright 2005-2006 Stephane Marchesin
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */

#include "drmP.h"
#include "drm.h"
#include "nouveau_drv.h"
#include "nouveau_drm.h"


/* returns the number of hw fifos */
int nouveau_fifo_number(drm_device_t* dev)
{
	drm_nouveau_private_t *dev_priv=dev->dev_private;
	switch(dev_priv->card_type)
	{
		case NV_03:
			return 8;
		case NV_04:
		case NV_05:
			return 16;
		default:
			return 32;
	}
}

/* returns the size of fifo context */
static int nouveau_fifo_ctx_size(drm_device_t* dev)
{
	drm_nouveau_private_t *dev_priv=dev->dev_private;

	if (dev_priv->card_type >= NV_40)
		return 128;
	else if (dev_priv->card_type >= NV_10)
		return 64;
	else
		return 32;
}

/***********************************
 * functions doing the actual work
 ***********************************/

/* voir nv_xaa.c : NVResetGraphics
 * mémoire mappée par nv_driver.c : NVMapMem
 * voir nv_driver.c : NVPreInit 
 */

static int nouveau_fifo_instmem_configure(drm_device_t *dev)
{
	drm_nouveau_private_t *dev_priv = dev->dev_private;
	uint32_t obj_base, obj_size;
	int i;

	/* Clear RAMIN */
	for (i=0x00710000; i<0x00800000; i++)
		NV_WRITE(i, 0x00000000);

	/* FIFO hash table (RAMHT)
	 *   use 4k hash table at RAMIN+0x10000
	 *   TODO: extend the hash table
	 */
	dev_priv->ramht_offset = 0x10000;
	dev_priv->ramht_bits   = 9;
	dev_priv->ramht_size   = (1 << dev_priv->ramht_bits);
	NV_WRITE(NV_PFIFO_RAMHT,
			(0x03 << 24) /* search 128 */ | 
			((dev_priv->ramht_bits - 9) << 16) |
			(dev_priv->ramht_offset >> 8)
			);
	DRM_DEBUG("RAMHT offset=0x%x, size=%d\n",
			dev_priv->ramht_offset,
			dev_priv->ramht_size);

	/* FIFO runout table (RAMRO) - 512k at 0x11200 */
	dev_priv->ramro_offset = 0x11200;
	dev_priv->ramro_size   = 512;
	NV_WRITE(NV_PFIFO_RAMRO, dev_priv->ramro_offset>>8);
	DRM_DEBUG("RAMRO offset=0x%x, size=%d\n",
			dev_priv->ramro_offset,
			dev_priv->ramro_size);

	/* FIFO context table (RAMFC)
	 *   NV40  : Not sure exactly how to position RAMFC on some cards,
	 *           0x30002 seems to position it at RAMIN+0x20000 on these
	 *           cards.  RAMFC is 4kb (32 fifos, 128byte entries).
	 *   Others: Position RAMFC at RAMIN+0x11400
	 */
	if (dev_priv->card_type >= NV_40) {
		dev_priv->ramfc_offset = 0x20000;
		dev_priv->ramfc_size   = nouveau_fifo_number(dev) * 128;
		NV_WRITE(NV40_PFIFO_RAMFC, 0x30002);
	} else if (dev_priv->card_type >= NV_10) {
		dev_priv->ramfc_offset = 0x11400;
		dev_priv->ramfc_size   = nouveau_fifo_number(dev) * 64;
		NV_WRITE(NV_PFIFO_RAMFC, (dev_priv->ramfc_offset>>8) |
				(1 << 16) /* 64 Bytes entry*/);
	} else {
		dev_priv->ramfc_offset = 0x11400;
		dev_priv->ramfc_size   = nouveau_fifo_number(dev) * 32;
		NV_WRITE(NV_PFIFO_RAMFC, dev_priv->ramfc_offset>>8);
	}
	DRM_DEBUG("RAMFC offset=0x%x, size=%d\n",
			dev_priv->ramfc_offset,
			dev_priv->ramfc_size);

	obj_base = dev_priv->ramfc_offset + dev_priv->ramfc_size;
	obj_size = (512*1024) - obj_base; /*XXX: probably wrong on some cards*/
	if (nouveau_instmem_init(dev, obj_base, obj_size))
		return 1;
	DRM_DEBUG("RAMIN object space: offset=0x%08x, size=%dKiB\n",
			obj_base, obj_size>>10);

	return 0;
}

int nouveau_fifo_init(drm_device_t *dev)
{
	drm_nouveau_private_t *dev_priv = dev->dev_private;
	int ret;

	NV_WRITE(NV_PFIFO_CACHES, 0x00000000);

	ret = nouveau_fifo_instmem_configure(dev);
	if (ret) {
		DRM_ERROR("Failed to configure instance memory\n");
		return ret;
	}

	/* FIXME remove all the stuff that's done in nouveau_fifo_alloc */

	DRM_DEBUG("Setting defaults for remaining PFIFO regs\n");

	/* All channels into PIO mode */
	NV_WRITE(NV_PFIFO_MODE, 0x00000000);

	NV_WRITE(NV_PFIFO_CACH1_PSH0, 0x00000000);
	NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000000);
	/* Channel 0 active, PIO mode */
	NV_WRITE(NV_PFIFO_CACH1_PSH1, 0x00000000);
	/* PUT and GET to 0 */
	NV_WRITE(NV_PFIFO_CACH1_DMAP, 0x00000000);
	NV_WRITE(NV_PFIFO_CACH1_DMAP, 0x00000000);
	/* No cmdbuf object */
	NV_WRITE(NV_PFIFO_CACH1_DMAI, 0x00000000);
	NV_WRITE(NV_PFIFO_CACH0_PSH0, 0x00000000);
	NV_WRITE(NV_PFIFO_CACH0_PUL0, 0x00000000);
	NV_WRITE(NV_PFIFO_SIZE, 0x0000FFFF);
	NV_WRITE(NV_PFIFO_CACH1_HASH, 0x0000FFFF);
	NV_WRITE(NV_PFIFO_CACH0_PUL1, 0x00000001);
	NV_WRITE(NV_PFIFO_CACH1_DMAC, 0x00000000);
	NV_WRITE(NV_PFIFO_CACH1_DMAS, 0x00000000);
	NV_WRITE(NV_PFIFO_CACH1_ENG, 0x00000000);
#ifdef __BIG_ENDIAN
	NV_WRITE(NV_PFIFO_CACH1_DMAF, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES |
				      NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES |
				      NV_PFIFO_CACH1_DMAF_MAX_REQS_4 |
				      NV_PFIFO_CACH1_BIG_ENDIAN);
#else
	NV_WRITE(NV_PFIFO_CACH1_DMAF, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES |
				      NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES | 
				      NV_PFIFO_CACH1_DMAF_MAX_REQS_4);
#endif
	NV_WRITE(NV_PFIFO_CACH1_DMAPSH, 0x00000001);
	NV_WRITE(NV_PFIFO_CACH1_PSH0, 0x00000001);
	NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000001);
	NV_WRITE(NV_PFIFO_CACH1_PUL1, 0x00000001);

	NV_WRITE(NV_PGRAPH_CTX_USER, 0x0);
	NV_WRITE(NV_PFIFO_DELAY_0, 0xff /* retrycount*/ );
	if (dev_priv->card_type >= NV_40)
		NV_WRITE(NV_PGRAPH_CTX_CONTROL, 0x00002001);
	else
		NV_WRITE(NV_PGRAPH_CTX_CONTROL, 0x10110000);

	NV_WRITE(NV_PFIFO_DMA_TIMESLICE, 0x001fffff);
	NV_WRITE(NV_PFIFO_CACHES, 0x00000001);

	return 0;
}

static int nouveau_dma_init(struct drm_device *dev)
{
	drm_nouveau_private_t *dev_priv = dev->dev_private;
	struct nouveau_config *config = &dev_priv->config;
	struct mem_block *cb;
	int cb_min_size = nouveau_fifo_number(dev) * max(NV03_FIFO_SIZE,PAGE_SIZE);

	/* Defaults for unconfigured values */
	if (!config->cmdbuf.location)
		config->cmdbuf.location = NOUVEAU_MEM_FB;
	if (!config->cmdbuf.size || config->cmdbuf.size < cb_min_size)
		config->cmdbuf.size = cb_min_size;

	cb = nouveau_mem_alloc(dev, 0, config->cmdbuf.size,
			config->cmdbuf.location, (DRMFILE)-2);
	/* Try defaults if that didn't succeed */
	if (!cb) {
		config->cmdbuf.location = NOUVEAU_MEM_FB;
		config->cmdbuf.size = cb_min_size;
		cb = nouveau_mem_alloc(dev, 0, config->cmdbuf.size,
				config->cmdbuf.location, (DRMFILE)-2);
	}
	if (!cb) {
		DRM_ERROR("Couldn't allocate DMA command buffer.\n");
		return DRM_ERR(ENOMEM);
	}

	dev_priv->cmdbuf_ch_size = (uint32_t)cb->size / nouveau_fifo_number(dev);
	dev_priv->cmdbuf_alloc = cb;

	DRM_INFO("DMA command buffer is %dKiB at 0x%08x(%s)\n",
			(uint32_t)cb->size>>10, (uint32_t)cb->start,
			config->cmdbuf.location == NOUVEAU_MEM_FB ? "VRAM" : "AGP");
	DRM_INFO("FIFO size is %dKiB\n", dev_priv->cmdbuf_ch_size>>10);

	return 0;
}

static void nouveau_context_init(drm_device_t *dev,
				 drm_nouveau_fifo_alloc_t *init)
{
	drm_nouveau_private_t *dev_priv = dev->dev_private;
	struct nouveau_object *cb_obj;
	uint32_t ctx_addr, ctx_size = 32;
	int i;

	cb_obj = dev_priv->fifos[init->channel].cmdbuf_obj;

	ctx_addr=NV_RAMIN+dev_priv->ramfc_offset+init->channel*ctx_size;
	// clear the fifo context
	for(i=0;i<ctx_size/4;i++)
		NV_WRITE(ctx_addr+4*i,0x0);

	NV_WRITE(ctx_addr,init->put_base);
	NV_WRITE(ctx_addr+4,init->put_base);
	// that's what is done in nvosdk, but that part of the code is buggy so...
	NV_WRITE(ctx_addr+8, nouveau_chip_instance_get(dev, cb_obj->instance));
#ifdef __BIG_ENDIAN
	NV_WRITE(ctx_addr+16,NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES|NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES|NV_PFIFO_CACH1_DMAF_MAX_REQS_4|NV_PFIFO_CACH1_BIG_ENDIAN);
#else
	NV_WRITE(ctx_addr+16,NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES|NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES|NV_PFIFO_CACH1_DMAF_MAX_REQS_4);
#endif
}

#define RAMFC_WR(offset, val) NV_WRITE(fifoctx + NV10_RAMFC_##offset, (val))
static void nouveau_nv10_context_init(drm_device_t *dev,
				      drm_nouveau_fifo_alloc_t *init)
{
	drm_nouveau_private_t *dev_priv = dev->dev_private;
	struct nouveau_object *cb_obj;
	uint32_t fifoctx;
	int i;

	cb_obj  = dev_priv->fifos[init->channel].cmdbuf_obj;
	fifoctx = NV_RAMIN + dev_priv->ramfc_offset + init->channel*64;
	for (i=0;i<64;i+=4)
		NV_WRITE(fifoctx + i, 0);

	/* Fill entries that are seen filled in dumps of nvidia driver just
	 * after channel's is put into DMA mode
	 */
	RAMFC_WR(DMA_PUT       , init->put_base);
	RAMFC_WR(DMA_GET       , init->put_base);
	RAMFC_WR(DMA_INSTANCE  , nouveau_chip_instance_get(dev,
				cb_obj->instance));
#ifdef __BIG_ENDIAN
		RAMFC_WR(DMA_FETCH, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES | 
				    NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES |
				    NV_PFIFO_CACH1_DMAF_MAX_REQS_4     |
				    NV_PFIFO_CACH1_BIG_ENDIAN);
#else
		RAMFC_WR(DMA_FETCH, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES | 
				    NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES |
				    NV_PFIFO_CACH1_DMAF_MAX_REQS_4);
#endif
	RAMFC_WR(DMA_SUBROUTINE, 0);
}

static void nouveau_nv10_context_save(drm_device_t *dev)
{
	drm_nouveau_private_t *dev_priv = dev->dev_private;
	uint32_t fifoctx;
	int channel;

	channel = NV_READ(NV_PFIFO_CACH1_PSH1) & (nouveau_fifo_number(dev)-1);
	fifoctx = NV_RAMIN + dev_priv->ramfc_offset + channel*64;

	RAMFC_WR(DMA_PUT          , NV_READ(NV_PFIFO_CACH1_DMAP));
	RAMFC_WR(DMA_GET          , NV_READ(NV_PFIFO_CACH1_DMAG));
	RAMFC_WR(REF_CNT          , NV_READ(NV_PFIFO_CACH1_REF_CNT));
	RAMFC_WR(DMA_INSTANCE     , NV_READ(NV_PFIFO_CACH1_DMAI));
	RAMFC_WR(DMA_STATE        , NV_READ(NV_PFIFO_CACH1_DMAS));
	RAMFC_WR(DMA_FETCH        , NV_READ(NV_PFIFO_CACH1_DMAF));
	RAMFC_WR(ENGINE           , NV_READ(NV_PFIFO_CACH1_ENG));
	RAMFC_WR(PULL1_ENGINE     , NV_READ(NV_PFIFO_CACH1_PUL1));
	RAMFC_WR(ACQUIRE_VALUE    , NV_READ(NV_PFIFO_CACH1_ACQUIRE_VALUE));
	RAMFC_WR(ACQUIRE_TIMESTAMP, NV_READ(NV_PFIFO_CACH1_ACQUIRE_TIMESTAMP));
	RAMFC_WR(ACQUIRE_TIMEOUT  , NV_READ(NV_PFIFO_CACH1_ACQUIRE_TIMEOUT));
	RAMFC_WR(SEMAPHORE        , NV_READ(NV_PFIFO_CACH1_SEMAPHORE));
	RAMFC_WR(DMA_SUBROUTINE   , NV_READ(NV_PFIFO_CACH1_DMASR));
}
#undef RAMFC_WR

#define RAMFC_WR(offset, val) NV_WRITE(fifoctx + NV40_RAMFC_##offset, (val))
static void nouveau_nv40_context_init(drm_device_t *dev,
				      drm_nouveau_fifo_alloc_t *init)
{
	drm_nouveau_private_t *dev_priv = dev->dev_private;
	struct nouveau_object *cb_obj;
	uint32_t fifoctx;
	int i;

	cb_obj  = dev_priv->fifos[init->channel].cmdbuf_obj;
	fifoctx = NV_RAMIN + dev_priv->ramfc_offset + init->channel*128;
	for (i=0;i<128;i+=4)
		NV_WRITE(fifoctx + i, 0);

	/* Fill entries that are seen filled in dumps of nvidia driver just
	 * after channel's is put into DMA mode
	 */
	RAMFC_WR(DMA_PUT       , init->put_base);
	RAMFC_WR(DMA_GET       , init->put_base);
	RAMFC_WR(DMA_INSTANCE  , nouveau_chip_instance_get(dev, 
				cb_obj->instance));
	RAMFC_WR(DMA_FETCH     , 0x30086078);
	RAMFC_WR(DMA_SUBROUTINE, init->put_base);
	RAMFC_WR(GRCTX_INSTANCE, 0); /* XXX */
	RAMFC_WR(DMA_TIMESLICE , 0x0001FFFF);
}

static void nouveau_nv40_context_save(drm_device_t *dev)
{
	drm_nouveau_private_t *dev_priv = dev->dev_private;
	uint32_t fifoctx;
	int channel;

	channel = NV_READ(NV_PFIFO_CACH1_PSH1) & (nouveau_fifo_number(dev)-1);
	fifoctx = NV_RAMIN + dev_priv->ramfc_offset + channel*128;

	RAMFC_WR(DMA_PUT          , NV_READ(NV_PFIFO_CACH1_DMAP));
	RAMFC_WR(DMA_GET          , NV_READ(NV_PFIFO_CACH1_DMAG));
	RAMFC_WR(REF_CNT          , NV_READ(NV_PFIFO_CACH1_REF_CNT));
	RAMFC_WR(DMA_INSTANCE     , NV_READ(NV_PFIFO_CACH1_DMAI));
	RAMFC_WR(DMA_DCOUNT       , NV_READ(NV_PFIFO_CACH1_DMA_DCOUNT));
	RAMFC_WR(DMA_STATE        , NV_READ(NV_PFIFO_CACH1_DMAS));
	//fetch
	RAMFC_WR(ENGINE           , NV_READ(NV_PFIFO_CACH1_ENG));
	RAMFC_WR(PULL1_ENGINE     , NV_READ(NV_PFIFO_CACH1_PUL1));
	RAMFC_WR(ACQUIRE_VALUE    , NV_READ(NV_PFIFO_CACH1_ACQUIRE_VALUE));
	RAMFC_WR(ACQUIRE_TIMESTAMP, NV_READ(NV_PFIFO_CACH1_ACQUIRE_TIMESTAMP));
	RAMFC_WR(ACQUIRE_TIMEOUT  , NV_READ(NV_PFIFO_CACH1_ACQUIRE_TIMEOUT));
	RAMFC_WR(SEMAPHORE        , NV_READ(NV_PFIFO_CACH1_SEMAPHORE));
	RAMFC_WR(DMA_SUBROUTINE   , NV_READ(NV_PFIFO_CACH1_DMAG));
	RAMFC_WR(GRCTX_INSTANCE   , NV_READ(NV40_PFIFO_GRCTX_INSTANCE));
	RAMFC_WR(DMA_TIMESLICE    , NV_READ(NV_PFIFO_DMA_TIMESLICE) & 0x1FFFF);
	RAMFC_WR(UNK_40           , NV_READ(NV40_PFIFO_UNK32E4));
}
#undef RAMFC_WR

/* allocates and initializes a fifo for user space consumption */
static int nouveau_fifo_alloc(drm_device_t* dev,drm_nouveau_fifo_alloc_t* init, DRMFILE filp)
{
	int i;
	int ret;
	drm_nouveau_private_t *dev_priv = dev->dev_private;
	struct nouveau_object *cb_obj;

	/* Init cmdbuf on first FIFO init, this is delayed until now to
	 * give the ddx a chance to configure the cmdbuf with SETPARAM
	 */
	if (!dev_priv->cmdbuf_alloc) {
		ret = nouveau_dma_init(dev);
		if (ret)
			return ret;
	}

	/*
	 * Alright, here is the full story
	 * Nvidia cards have multiple hw fifo contexts (praise them for that, 
	 * no complicated crash-prone context switches)
	 * We allocate a new context for each app and let it write to it directly 
	 * (woo, full userspace command submission !)
	 * When there are no more contexts, you lost
	 */
	for(i=0;i<nouveau_fifo_number(dev);i++)
		if (dev_priv->fifos[i].used==0)
			break;

	DRM_INFO("Allocating FIFO number %d\n", i);
	/* no more fifos. you lost. */
	if (i==nouveau_fifo_number(dev))
		return DRM_ERR(EINVAL);

	/* allocate a dma object for the command buffer */
	if (dev_priv->cmdbuf_alloc->flags & NOUVEAU_MEM_AGP) {
		cb_obj = nouveau_dma_object_create(dev,
				dev_priv->cmdbuf_alloc->start,
				dev_priv->cmdbuf_alloc->size,
				NV_DMA_ACCESS_RO,
				NV_DMA_TARGET_AGP);
	} else {
		cb_obj = nouveau_dma_object_create(dev,
				dev_priv->cmdbuf_alloc->start -
					drm_get_resource_start(dev, 1),
				dev_priv->cmdbuf_alloc->size,
				NV_DMA_ACCESS_RO,
				NV_DMA_TARGET_VIDMEM);
	}
	if (!cb_obj) {
		DRM_ERROR("unable to alloc object for command buffer\n");
		return DRM_ERR(EINVAL);
	}
	dev_priv->fifos[i].cmdbuf_obj = cb_obj;

	/* that fifo is used */
	dev_priv->fifos[i].used=1;
	dev_priv->fifos[i].filp=filp;

	init->channel  = i;
	init->put_base = i*dev_priv->cmdbuf_ch_size;
	dev_priv->cur_fifo = init->channel;

	nouveau_wait_for_idle(dev);

	/* disable the fifo caches */
	NV_WRITE(NV_PFIFO_CACHES, 0x00000000);
	NV_WRITE(NV_PFIFO_CACH1_DMAPSH, NV_READ(NV_PFIFO_CACH1_DMAPSH)&(~0x1));
	NV_WRITE(NV_PFIFO_CACH1_PSH0, 0x00000000);
	NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000000);

	/* Save current channel's state to it's RAMFC entry.
	 *
	 * Then, construct inital RAMFC for new channel, I'm not entirely
	 * sure this is needed if we activate the channel immediately.
	 * My understanding is that the GPU will fill RAMFC itself when
	 * it switches away from the channel
	 */
	if (dev_priv->card_type < NV_10) {
		nouveau_context_init(dev, init);
	} else if (dev_priv->card_type < NV_40) {
		nouveau_nv10_context_save(dev);
		nouveau_nv10_context_init(dev, init);
	} else {
		nouveau_nv40_context_save(dev);
		nouveau_nv40_context_init(dev, init);
	}

	/* enable the fifo dma operation */
	NV_WRITE(NV_PFIFO_MODE,NV_READ(NV_PFIFO_MODE)|(1<<init->channel));

	NV_WRITE(NV03_FIFO_REGS_DMAPUT(init->channel), init->put_base);
	NV_WRITE(NV03_FIFO_REGS_DMAGET(init->channel), init->put_base);

	// FIXME check if we need to refill the time quota with something like NV_WRITE(0x204C, 0x0003FFFF);

	if (dev_priv->card_type >= NV_40)
		NV_WRITE(NV_PFIFO_CACH1_PSH1, 0x00010000|dev_priv->cur_fifo);
	else
		NV_WRITE(NV_PFIFO_CACH1_PSH1, 0x00000100|dev_priv->cur_fifo);

	NV_WRITE(NV_PFIFO_CACH1_DMAP, init->put_base);
	NV_WRITE(NV_PFIFO_CACH1_DMAG, init->put_base);
	NV_WRITE(NV_PFIFO_CACH1_DMAI,
			nouveau_chip_instance_get(dev, cb_obj->instance));
	NV_WRITE(NV_PFIFO_SIZE , 0x0000FFFF);
	NV_WRITE(NV_PFIFO_CACH1_HASH, 0x0000FFFF);

	NV_WRITE(NV_PFIFO_CACH0_PUL1, 0x00000001);
	NV_WRITE(NV_PFIFO_CACH1_DMAC, 0x00000000);
	NV_WRITE(NV_PFIFO_CACH1_DMAS, 0x00000000);
	NV_WRITE(NV_PFIFO_CACH1_ENG, 0x00000000);
#ifdef __BIG_ENDIAN
		NV_WRITE(NV_PFIFO_CACH1_DMAF, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES|NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES|NV_PFIFO_CACH1_DMAF_MAX_REQS_4|NV_PFIFO_CACH1_BIG_ENDIAN);
#else
		NV_WRITE(NV_PFIFO_CACH1_DMAF, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES|NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES|NV_PFIFO_CACH1_DMAF_MAX_REQS_4);
#endif
	NV_WRITE(NV_PFIFO_CACH1_DMAPSH, 0x00000001);
	NV_WRITE(NV_PFIFO_CACH1_PSH0, 0x00000001);
	NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000001);
	NV_WRITE(NV_PFIFO_CACH1_PUL1, 0x00000001);

	/* reenable the fifo caches */
	NV_WRITE(NV_PFIFO_CACHES, 0x00000001);

	/* make the fifo available to user space */
	/* first, the fifo control regs */
	init->ctrl      = dev_priv->mmio->offset + NV03_FIFO_REGS(init->channel);
	init->ctrl_size = NV03_FIFO_REGS_SIZE;
	ret = drm_addmap(dev, init->ctrl, init->ctrl_size, _DRM_REGISTERS,
			 0, &dev_priv->fifos[init->channel].regs);
	if (ret != 0)
		return ret;

	/* then, the fifo itself */
	init->cmdbuf       = dev_priv->cmdbuf_alloc->start;
	init->cmdbuf      += init->channel * dev_priv->cmdbuf_ch_size;
	init->cmdbuf_size  = dev_priv->cmdbuf_ch_size;
	ret = drm_addmap(dev, init->cmdbuf, init->cmdbuf_size, _DRM_REGISTERS,
			 0, &dev_priv->fifos[init->channel].map);
	if (ret != 0)
		return ret;

	/* FIFO has no objects yet */
	dev_priv->fifos[init->channel].objs = NULL;
	dev_priv->fifo_alloc_count++;

	DRM_INFO("%s: initialised FIFO %d\n", __func__, init->channel);
	return 0;
}

/* stops a fifo */
void nouveau_fifo_free(drm_device_t* dev,int n)
{
	drm_nouveau_private_t *dev_priv = dev->dev_private;
	int i;
	int ctx_size = nouveau_fifo_ctx_size(dev);

	dev_priv->fifos[n].used=0;
	DRM_INFO("%s: freeing fifo %d\n", __func__, n);

	/* disable the fifo caches */
	NV_WRITE(NV_PFIFO_CACHES, 0x00000000);

	NV_WRITE(NV_PFIFO_MODE,NV_READ(NV_PFIFO_MODE)&~(1<<n));
	// FIXME XXX needs more code
	
	/* Clean RAMFC */
	for (i=0;i<ctx_size;i+=4) {
		DRM_DEBUG("RAMFC +%02x: 0x%08x\n", i, NV_READ(NV_RAMIN +
					dev_priv->ramfc_offset + n*ctx_size + i));
		NV_WRITE(NV_RAMIN + dev_priv->ramfc_offset + n*ctx_size + i, 0);
	}

	/* reenable the fifo caches */
	NV_WRITE(NV_PFIFO_CACHES, 0x00000001);

	dev_priv->fifo_alloc_count--;
}

/* cleanups all the fifos from filp */
void nouveau_fifo_cleanup(drm_device_t* dev, DRMFILE filp)
{
	int i;
	drm_nouveau_private_t *dev_priv = dev->dev_private;

	DRM_DEBUG("clearing FIFO enables from filp\n");
	for(i=0;i<nouveau_fifo_number(dev);i++)
		if (dev_priv->fifos[i].used && dev_priv->fifos[i].filp==filp)
			nouveau_fifo_free(dev,i);

	/* check we still point at an active channel */
	if (dev_priv->fifos[dev_priv->cur_fifo].used == 0) {	
		DRM_DEBUG("%s: cur_fifo is no longer owned.\n", __func__);
		for (i=0;i<nouveau_fifo_number(dev);i++)
			if (dev_priv->fifos[i].used) break;
		if (i==nouveau_fifo_number(dev))
			i=0;
		DRM_DEBUG("%s: new cur_fifo is %d\n", __func__, i);
		dev_priv->cur_fifo = i;
	}

/*	if (dev_priv->cmdbuf_alloc)
		nouveau_fifo_init(dev);*/
}

int nouveau_fifo_id_get(drm_device_t* dev, DRMFILE filp)
{
	drm_nouveau_private_t *dev_priv=dev->dev_private;
	int i;

	for(i=0;i<nouveau_fifo_number(dev);i++)
		if (dev_priv->fifos[i].used && dev_priv->fifos[i].filp == filp)
			return i;
	return -1;
}

/***********************************
 * ioctls wrapping the functions
 ***********************************/

static int nouveau_ioctl_fifo_alloc(DRM_IOCTL_ARGS)
{
	DRM_DEVICE;
	drm_nouveau_fifo_alloc_t init;
	int res;
	DRM_COPY_FROM_USER_IOCTL(init, (drm_nouveau_fifo_alloc_t __user *) data, sizeof(init));

	res=nouveau_fifo_alloc(dev,&init,filp);
	if (!res)
		DRM_COPY_TO_USER_IOCTL((drm_nouveau_fifo_alloc_t __user *)data, init, sizeof(init));

	return res;
}

/***********************************
 * finally, the ioctl table
 ***********************************/

drm_ioctl_desc_t nouveau_ioctls[] = {
	[DRM_IOCTL_NR(DRM_NOUVEAU_FIFO_ALLOC)] = {nouveau_ioctl_fifo_alloc, DRM_AUTH},
	[DRM_IOCTL_NR(DRM_NOUVEAU_OBJECT_INIT)] = {nouveau_ioctl_object_init, DRM_AUTH},
	[DRM_IOCTL_NR(DRM_NOUVEAU_DMA_OBJECT_INIT)] = {nouveau_ioctl_dma_object_init, DRM_AUTH},
	[DRM_IOCTL_NR(DRM_NOUVEAU_MEM_ALLOC)] = {nouveau_ioctl_mem_alloc, DRM_AUTH},
	[DRM_IOCTL_NR(DRM_NOUVEAU_MEM_FREE)] = {nouveau_ioctl_mem_free, DRM_AUTH},
	[DRM_IOCTL_NR(DRM_NOUVEAU_GETPARAM)] = {nouveau_ioctl_getparam, DRM_AUTH},
	[DRM_IOCTL_NR(DRM_NOUVEAU_SETPARAM)] = {nouveau_ioctl_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},	
};

int nouveau_max_ioctl = DRM_ARRAY_SIZE(nouveau_ioctls);