diff options
Diffstat (limited to 'src/svga_reg.h')
-rw-r--r-- | src/svga_reg.h | 1433 |
1 files changed, 1066 insertions, 367 deletions
diff --git a/src/svga_reg.h b/src/svga_reg.h index 4fa363a..6757aa6 100644 --- a/src/svga_reg.h +++ b/src/svga_reg.h | |||
@@ -1,52 +1,81 @@ | |||
1 | /* ********************************************************** | 1 | /********************************************************** |
2 | * Copyright 1998 VMware, Inc. All rights reserved. | 2 | * Copyright 1998-2009 VMware, Inc. All rights reserved. |
3 | * **********************************************************/ | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person | ||
5 | * obtaining a copy of this software and associated documentation | ||
6 | * files (the "Software"), to deal in the Software without | ||
7 | * restriction, including without limitation the rights to use, copy, | ||
8 | * modify, merge, publish, distribute, sublicense, and/or sell copies | ||
9 | * of the Software, and to permit persons to whom the Software is | ||
10 | * furnished to do so, subject to the following conditions: | ||
11 | * | ||
12 | * The above copyright notice and this permission notice shall be | ||
13 | * included in all copies or substantial portions of the Software. | ||
14 | * | ||
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | ||
16 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
17 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | ||
18 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | ||
19 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | ||
20 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | ||
21 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | ||
22 | * SOFTWARE. | ||
23 | * | ||
24 | **********************************************************/ | ||
4 | 25 | ||
5 | /* | 26 | /* |
6 | * svga_reg.h -- | 27 | * svga_reg.h -- |
7 | * | 28 | * |
8 | * SVGA hardware definitions | 29 | * Virtual hardware definitions for the VMware SVGA II device. |
9 | */ | 30 | */ |
10 | 31 | ||
11 | #ifndef _SVGA_REG_H_ | 32 | #ifndef _SVGA_REG_H_ |
12 | #define _SVGA_REG_H_ | 33 | #define _SVGA_REG_H_ |
13 | 34 | ||
14 | #define INCLUDE_ALLOW_USERLEVEL | 35 | /* |
15 | #define INCLUDE_ALLOW_VMMEXT | 36 | * PCI device IDs. |
16 | #define INCLUDE_ALLOW_VMCORE | 37 | */ |
17 | #include "includeCheck.h" | 38 | #define PCI_VENDOR_ID_VMWARE 0x15AD |
39 | #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405 | ||
18 | 40 | ||
19 | /* | 41 | /* |
20 | * Memory and port addresses and fundamental constants | 42 | * SVGA_REG_ENABLE bit definitions. |
21 | */ | 43 | */ |
44 | #define SVGA_REG_ENABLE_DISABLE 0 | ||
45 | #define SVGA_REG_ENABLE_ENABLE 1 | ||
46 | #define SVGA_REG_ENABLE_HIDE 2 | ||
47 | #define SVGA_REG_ENABLE_ENABLE_HIDE (SVGA_REG_ENABLE_ENABLE |\ | ||
48 | SVGA_REG_ENABLE_HIDE) | ||
22 | 49 | ||
23 | /* | 50 | /* |
24 | * Note-- MAX_WIDTH and MAX_HEIGHT are largely ignored by the code. This | 51 | * Legal values for the SVGA_REG_CURSOR_ON register in old-fashioned |
25 | * isn't such a bad thing for forward compatibility. --Jeremy. | 52 | * cursor bypass mode. This is still supported, but no new guest |
53 | * drivers should use it. | ||
26 | */ | 54 | */ |
27 | #define SVGA_MAX_WIDTH 2360 | 55 | #define SVGA_CURSOR_ON_HIDE 0x0 /* Must be 0 to maintain backward compatibility */ |
28 | #define SVGA_MAX_HEIGHT 1770 | 56 | #define SVGA_CURSOR_ON_SHOW 0x1 /* Must be 1 to maintain backward compatibility */ |
29 | #define SVGA_MAX_BITS_PER_PIXEL 32 | 57 | #define SVGA_CURSOR_ON_REMOVE_FROM_FB 0x2 /* Remove the cursor from the framebuffer because we need to see what's under it */ |
30 | #define SVGA_MAX_DEPTH 24 | 58 | #define SVGA_CURSOR_ON_RESTORE_TO_FB 0x3 /* Put the cursor back in the framebuffer so the user can see it */ |
31 | #define SVGA_MAX_DISPLAYS 10 | ||
32 | 59 | ||
33 | /* | 60 | /* |
34 | * The maximum size of the onscreen framebuffer. The size of the | 61 | * The maximum framebuffer size that can traced for e.g. guests in VESA mode. |
35 | * changeMap in the monitor is proportional to this number since it's | 62 | * The changeMap in the monitor is proportional to this number. Therefore, we'd |
36 | * the amount of memory we need to trace in VESA mode. Therefore, we'd | ||
37 | * like to keep it as small as possible to reduce monitor overhead (using | 63 | * like to keep it as small as possible to reduce monitor overhead (using |
38 | * SVGA_VRAM_MAX_SIZE for this increases the size of the shared area | 64 | * SVGA_VRAM_MAX_SIZE for this increases the size of the shared area by over |
39 | * by over 4k!). | 65 | * 4k!). |
66 | * | ||
67 | * NB: For compatibility reasons, this value must be greater than 0xff0000. | ||
68 | * See bug 335072. | ||
40 | */ | 69 | */ |
41 | 70 | #define SVGA_FB_MAX_TRACEABLE_SIZE 0x1000000 | |
42 | #define SVGA_FB_MAX_SIZE \ | ||
43 | ((((SVGA_MAX_WIDTH * SVGA_MAX_HEIGHT * \ | ||
44 | SVGA_MAX_BITS_PER_PIXEL / 8) >> PAGE_SHIFT) + 1) << PAGE_SHIFT) | ||
45 | 71 | ||
46 | #define SVGA_MAX_PSEUDOCOLOR_DEPTH 8 | 72 | #define SVGA_MAX_PSEUDOCOLOR_DEPTH 8 |
47 | #define SVGA_MAX_PSEUDOCOLORS (1 << SVGA_MAX_PSEUDOCOLOR_DEPTH) | 73 | #define SVGA_MAX_PSEUDOCOLORS (1 << SVGA_MAX_PSEUDOCOLOR_DEPTH) |
48 | #define SVGA_NUM_PALETTE_REGS (3 * SVGA_MAX_PSEUDOCOLORS) | 74 | #define SVGA_NUM_PALETTE_REGS (3 * SVGA_MAX_PSEUDOCOLORS) |
49 | 75 | ||
76 | /* Base and Offset gets us headed the right way for PCI Base Addr Registers */ | ||
77 | #define SVGA_LEGACY_BASE_PORT 0x4560 | ||
78 | |||
50 | #define SVGA_MAGIC 0x900000UL | 79 | #define SVGA_MAGIC 0x900000UL |
51 | #define SVGA_MAKE_ID(ver) (SVGA_MAGIC << 8 | (ver)) | 80 | #define SVGA_MAKE_ID(ver) (SVGA_MAGIC << 8 | (ver)) |
52 | 81 | ||
@@ -63,19 +92,14 @@ | |||
63 | #define SVGA_VERSION_0 0 | 92 | #define SVGA_VERSION_0 0 |
64 | #define SVGA_ID_0 SVGA_MAKE_ID(SVGA_VERSION_0) | 93 | #define SVGA_ID_0 SVGA_MAKE_ID(SVGA_VERSION_0) |
65 | 94 | ||
66 | /* Invalid SVGA_ID_ */ | 95 | /* "Invalid" value for all SVGA IDs. (Version ID, screen object ID, surface ID...) */ |
67 | #define SVGA_ID_INVALID 0xFFFFFFFF | 96 | #define SVGA_ID_INVALID 0xFFFFFFFF |
68 | 97 | ||
69 | /* More backwards compatibility, old location of color map: */ | 98 | /* Port offsets, relative to BAR0 */ |
70 | #define SVGA_OLD_PALETTE_BASE 17 | 99 | #define SVGA_INDEX_PORT 0x0 |
71 | 100 | #define SVGA_VALUE_PORT 0x1 | |
72 | /* Base and Offset gets us headed the right way for PCI Base Addr Registers */ | 101 | #define SVGA_BIOS_PORT 0x2 |
73 | #define SVGA_LEGACY_BASE_PORT 0x4560 | 102 | #define SVGA_IRQSTATUS_PORT 0x8 |
74 | #define SVGA_INDEX_PORT 0x0 | ||
75 | #define SVGA_VALUE_PORT 0x1 | ||
76 | #define SVGA_BIOS_PORT 0x2 | ||
77 | #define SVGA_NUM_PORTS 0x3 | ||
78 | #define SVGA_IRQSTATUS_PORT 0x8 | ||
79 | 103 | ||
80 | /* | 104 | /* |
81 | * Interrupt source flags for IRQSTATUS_PORT and IRQMASK. | 105 | * Interrupt source flags for IRQSTATUS_PORT and IRQMASK. |
@@ -87,15 +111,6 @@ | |||
87 | #define SVGA_IRQFLAG_FIFO_PROGRESS 0x2 /* Made forward progress in the FIFO */ | 111 | #define SVGA_IRQFLAG_FIFO_PROGRESS 0x2 /* Made forward progress in the FIFO */ |
88 | #define SVGA_IRQFLAG_FENCE_GOAL 0x4 /* SVGA_FIFO_FENCE_GOAL reached */ | 112 | #define SVGA_IRQFLAG_FENCE_GOAL 0x4 /* SVGA_FIFO_FENCE_GOAL reached */ |
89 | 113 | ||
90 | /* This port is deprecated, but retained because of old drivers. */ | ||
91 | #define SVGA_LEGACY_ACCEL_PORT 0x3 | ||
92 | |||
93 | /* Legal values for the SVGA_REG_CURSOR_ON register in cursor bypass mode */ | ||
94 | #define SVGA_CURSOR_ON_HIDE 0x0 /* Must be 0 to maintain backward compatibility */ | ||
95 | #define SVGA_CURSOR_ON_SHOW 0x1 /* Must be 1 to maintain backward compatibility */ | ||
96 | #define SVGA_CURSOR_ON_REMOVE_FROM_FB 0x2 /* Remove the cursor from the framebuffer because we need to see what's under it */ | ||
97 | #define SVGA_CURSOR_ON_RESTORE_TO_FB 0x3 /* Put the cursor back in the framebuffer so the user can see it */ | ||
98 | |||
99 | /* | 114 | /* |
100 | * Registers | 115 | * Registers |
101 | */ | 116 | */ |
@@ -108,13 +123,13 @@ enum { | |||
108 | SVGA_REG_MAX_WIDTH = 4, | 123 | SVGA_REG_MAX_WIDTH = 4, |
109 | SVGA_REG_MAX_HEIGHT = 5, | 124 | SVGA_REG_MAX_HEIGHT = 5, |
110 | SVGA_REG_DEPTH = 6, | 125 | SVGA_REG_DEPTH = 6, |
111 | SVGA_REG_BITS_PER_PIXEL = 7, /* Current bpp in the guest */ | 126 | SVGA_REG_BITS_PER_PIXEL = 7, /* Current bpp in the guest */ |
112 | SVGA_REG_PSEUDOCOLOR = 8, | 127 | SVGA_REG_PSEUDOCOLOR = 8, |
113 | SVGA_REG_RED_MASK = 9, | 128 | SVGA_REG_RED_MASK = 9, |
114 | SVGA_REG_GREEN_MASK = 10, | 129 | SVGA_REG_GREEN_MASK = 10, |
115 | SVGA_REG_BLUE_MASK = 11, | 130 | SVGA_REG_BLUE_MASK = 11, |
116 | SVGA_REG_BYTES_PER_LINE = 12, | 131 | SVGA_REG_BYTES_PER_LINE = 12, |
117 | SVGA_REG_FB_START = 13, | 132 | SVGA_REG_FB_START = 13, /* (Deprecated) */ |
118 | SVGA_REG_FB_OFFSET = 14, | 133 | SVGA_REG_FB_OFFSET = 14, |
119 | SVGA_REG_VRAM_SIZE = 15, | 134 | SVGA_REG_VRAM_SIZE = 15, |
120 | SVGA_REG_FB_SIZE = 16, | 135 | SVGA_REG_FB_SIZE = 16, |
@@ -122,33 +137,46 @@ enum { | |||
122 | /* ID 0 implementation only had the above registers, then the palette */ | 137 | /* ID 0 implementation only had the above registers, then the palette */ |
123 | 138 | ||
124 | SVGA_REG_CAPABILITIES = 17, | 139 | SVGA_REG_CAPABILITIES = 17, |
125 | SVGA_REG_MEM_START = 18, /* Memory for command FIFO and bitmaps */ | 140 | SVGA_REG_MEM_START = 18, /* (Deprecated) */ |
126 | SVGA_REG_MEM_SIZE = 19, | 141 | SVGA_REG_MEM_SIZE = 19, |
127 | SVGA_REG_CONFIG_DONE = 20, /* Set when memory area configured */ | 142 | SVGA_REG_CONFIG_DONE = 20, /* Set when memory area configured */ |
128 | SVGA_REG_SYNC = 21, /* See "FIFO Synchronization Registers" */ | 143 | SVGA_REG_SYNC = 21, /* See "FIFO Synchronization Registers" */ |
129 | SVGA_REG_BUSY = 22, /* See "FIFO Synchronization Registers" */ | 144 | SVGA_REG_BUSY = 22, /* See "FIFO Synchronization Registers" */ |
130 | SVGA_REG_GUEST_ID = 23, /* Set guest OS identifier */ | 145 | SVGA_REG_GUEST_ID = 23, /* Set guest OS identifier */ |
131 | SVGA_REG_CURSOR_ID = 24, /* ID of cursor */ | 146 | SVGA_REG_CURSOR_ID = 24, /* (Deprecated) */ |
132 | SVGA_REG_CURSOR_X = 25, /* Set cursor X position */ | 147 | SVGA_REG_CURSOR_X = 25, /* (Deprecated) */ |
133 | SVGA_REG_CURSOR_Y = 26, /* Set cursor Y position */ | 148 | SVGA_REG_CURSOR_Y = 26, /* (Deprecated) */ |
134 | SVGA_REG_CURSOR_ON = 27, /* Turn cursor on/off */ | 149 | SVGA_REG_CURSOR_ON = 27, /* (Deprecated) */ |
135 | SVGA_REG_HOST_BITS_PER_PIXEL = 28, /* Current bpp in the host */ | 150 | SVGA_REG_HOST_BITS_PER_PIXEL = 28, /* (Deprecated) */ |
136 | SVGA_REG_SCRATCH_SIZE = 29, /* Number of scratch registers */ | 151 | SVGA_REG_SCRATCH_SIZE = 29, /* Number of scratch registers */ |
137 | SVGA_REG_MEM_REGS = 30, /* Number of FIFO registers */ | 152 | SVGA_REG_MEM_REGS = 30, /* Number of FIFO registers */ |
138 | SVGA_REG_NUM_DISPLAYS = 31, /* Number of guest displays */ | 153 | SVGA_REG_NUM_DISPLAYS = 31, /* (Deprecated) */ |
139 | SVGA_REG_PITCHLOCK = 32, /* Fixed pitch for all modes */ | 154 | SVGA_REG_PITCHLOCK = 32, /* Fixed pitch for all modes */ |
140 | SVGA_REG_IRQMASK = 33, /* Interrupt mask */ | 155 | SVGA_REG_IRQMASK = 33, /* Interrupt mask */ |
156 | |||
157 | /* Legacy multi-monitor support */ | ||
141 | SVGA_REG_NUM_GUEST_DISPLAYS = 34,/* Number of guest displays in X/Y direction */ | 158 | SVGA_REG_NUM_GUEST_DISPLAYS = 34,/* Number of guest displays in X/Y direction */ |
142 | SVGA_REG_DISPLAY_ID = 35, /* The display ID for the following display attributes */ | 159 | SVGA_REG_DISPLAY_ID = 35, /* Display ID for the following display attributes */ |
143 | SVGA_REG_DISPLAY_IS_PRIMARY = 36,/* Whether this is a primary display */ | 160 | SVGA_REG_DISPLAY_IS_PRIMARY = 36,/* Whether this is a primary display */ |
144 | SVGA_REG_DISPLAY_POSITION_X = 37,/* The display position x */ | 161 | SVGA_REG_DISPLAY_POSITION_X = 37,/* The display position x */ |
145 | SVGA_REG_DISPLAY_POSITION_Y = 38,/* The display position y */ | 162 | SVGA_REG_DISPLAY_POSITION_Y = 38,/* The display position y */ |
146 | SVGA_REG_DISPLAY_WIDTH = 39, /* The display's width */ | 163 | SVGA_REG_DISPLAY_WIDTH = 39, /* The display's width */ |
147 | SVGA_REG_DISPLAY_HEIGHT = 40, /* The display's height */ | 164 | SVGA_REG_DISPLAY_HEIGHT = 40, /* The display's height */ |
148 | SVGA_REG_TOP = 41, /* Must be 1 more than the last register */ | ||
149 | 165 | ||
150 | SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */ | 166 | /* See "Guest memory regions" below. */ |
167 | SVGA_REG_GMR_ID = 41, | ||
168 | SVGA_REG_GMR_DESCRIPTOR = 42, | ||
169 | SVGA_REG_GMR_MAX_IDS = 43, | ||
170 | SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH = 44, | ||
171 | |||
172 | SVGA_REG_TRACES = 45, /* Enable trace-based updates even when FIFO is on */ | ||
173 | SVGA_REG_GMRS_MAX_PAGES = 46, /* Maximum number of 4KB pages for all GMRs */ | ||
174 | SVGA_REG_MEMORY_SIZE = 47, /* Total dedicated device memory excluding FIFO */ | ||
175 | SVGA_REG_TOP = 48, /* Must be 1 more than the last register */ | ||
176 | |||
177 | SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */ | ||
151 | /* Next 768 (== 256*3) registers exist for colormap */ | 178 | /* Next 768 (== 256*3) registers exist for colormap */ |
179 | |||
152 | SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + SVGA_NUM_PALETTE_REGS | 180 | SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + SVGA_NUM_PALETTE_REGS |
153 | /* Base of scratch registers */ | 181 | /* Base of scratch registers */ |
154 | /* Next reg[SVGA_REG_SCRATCH_SIZE] registers exist for scratch usage: | 182 | /* Next reg[SVGA_REG_SCRATCH_SIZE] registers exist for scratch usage: |
@@ -156,126 +184,264 @@ enum { | |||
156 | the use of the current SVGA driver. */ | 184 | the use of the current SVGA driver. */ |
157 | }; | 185 | }; |
158 | 186 | ||
187 | /* | ||
188 | * Macros to compute variable length items (sizes in 32-bit words, except | ||
189 | * for SVGA_GLYPH_SCANLINE_SIZE, which is in bytes). | ||
190 | */ | ||
191 | #define SVGA_BITMAP_SIZE(w,h) ((((w)+31) >> 5) * (h)) | ||
192 | #define SVGA_PIXMAP_SIZE(w,h,bpp) ((( ((w)*(bpp))+31 ) >> 5) * (h)) | ||
193 | #define SVGA_BITMAP_INCREMENT(w) ((( (w)+31 ) >> 5) * sizeof (uint32)) | ||
194 | #define SVGA_PIXMAP_INCREMENT(w,bpp) ((( ((w)*(bpp))+31 ) >> 5) * sizeof (uint32)) | ||
159 | 195 | ||
160 | /* | 196 | /* |
161 | * Capabilities | 197 | * Guest memory regions (GMRs): |
198 | * | ||
199 | * This is a new memory mapping feature available in SVGA devices | ||
200 | * which have the SVGA_CAP_GMR bit set. Previously, there were two | ||
201 | * fixed memory regions available with which to share data between the | ||
202 | * device and the driver: the FIFO ('MEM') and the framebuffer. GMRs | ||
203 | * are our name for an extensible way of providing arbitrary DMA | ||
204 | * buffers for use between the driver and the SVGA device. They are a | ||
205 | * new alternative to framebuffer memory, usable for both 2D and 3D | ||
206 | * graphics operations. | ||
207 | * | ||
208 | * Since GMR mapping must be done synchronously with guest CPU | ||
209 | * execution, we use a new pair of SVGA registers: | ||
210 | * | ||
211 | * SVGA_REG_GMR_ID -- | ||
212 | * | ||
213 | * Read/write. | ||
214 | * This register holds the 32-bit ID (a small positive integer) | ||
215 | * of a GMR to create, delete, or redefine. Writing this register | ||
216 | * has no side-effects. | ||
217 | * | ||
218 | * SVGA_REG_GMR_DESCRIPTOR -- | ||
219 | * | ||
220 | * Write-only. | ||
221 | * Writing this register will create, delete, or redefine the GMR | ||
222 | * specified by the above ID register. If this register is zero, | ||
223 | * the GMR is deleted. Any pointers into this GMR (including those | ||
224 | * currently being processed by FIFO commands) will be | ||
225 | * synchronously invalidated. | ||
226 | * | ||
227 | * If this register is nonzero, it must be the physical page | ||
228 | * number (PPN) of a data structure which describes the physical | ||
229 | * layout of the memory region this GMR should describe. The | ||
230 | * descriptor structure will be read synchronously by the SVGA | ||
231 | * device when this register is written. The descriptor need not | ||
232 | * remain allocated for the lifetime of the GMR. | ||
233 | * | ||
234 | * The guest driver should write SVGA_REG_GMR_ID first, then | ||
235 | * SVGA_REG_GMR_DESCRIPTOR. | ||
236 | * | ||
237 | * SVGA_REG_GMR_MAX_IDS -- | ||
238 | * | ||
239 | * Read-only. | ||
240 | * The SVGA device may choose to support a maximum number of | ||
241 | * user-defined GMR IDs. This register holds the number of supported | ||
242 | * IDs. (The maximum supported ID plus 1) | ||
243 | * | ||
244 | * SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH -- | ||
245 | * | ||
246 | * Read-only. | ||
247 | * The SVGA device may choose to put a limit on the total number | ||
248 | * of SVGAGuestMemDescriptor structures it will read when defining | ||
249 | * a single GMR. | ||
250 | * | ||
251 | * The descriptor structure is an array of SVGAGuestMemDescriptor | ||
252 | * structures. Each structure may do one of three things: | ||
253 | * | ||
254 | * - Terminate the GMR descriptor list. | ||
255 | * (ppn==0, numPages==0) | ||
256 | * | ||
257 | * - Add a PPN or range of PPNs to the GMR's virtual address space. | ||
258 | * (ppn != 0, numPages != 0) | ||
259 | * | ||
260 | * - Provide the PPN of the next SVGAGuestMemDescriptor, in order to | ||
261 | * support multi-page GMR descriptor tables without forcing the | ||
262 | * driver to allocate physically contiguous memory. | ||
263 | * (ppn != 0, numPages == 0) | ||
264 | * | ||
265 | * Note that each physical page of SVGAGuestMemDescriptor structures | ||
266 | * can describe at least 2MB of guest memory. If the driver needs to | ||
267 | * use more than one page of descriptor structures, it must use one of | ||
268 | * its SVGAGuestMemDescriptors to point to an additional page. The | ||
269 | * device will never automatically cross a page boundary. | ||
270 | * | ||
271 | * Once the driver has described a GMR, it is immediately available | ||
272 | * for use via any FIFO command that uses an SVGAGuestPtr structure. | ||
273 | * These pointers include a GMR identifier plus an offset into that | ||
274 | * GMR. | ||
275 | * | ||
276 | * The driver must check the SVGA_CAP_GMR bit before using the GMR | ||
277 | * registers. | ||
162 | */ | 278 | */ |
163 | 279 | ||
164 | #define SVGA_CAP_NONE 0x00000000 | 280 | /* |
165 | #define SVGA_CAP_RECT_FILL 0x00000001 | 281 | * Special GMR IDs, allowing SVGAGuestPtrs to point to framebuffer |
166 | #define SVGA_CAP_RECT_COPY 0x00000002 | 282 | * memory as well. In the future, these IDs could even be used to |
167 | #define SVGA_CAP_RECT_PAT_FILL 0x00000004 | 283 | * allow legacy memory regions to be redefined by the guest as GMRs. |
168 | #define SVGA_CAP_LEGACY_OFFSCREEN 0x00000008 | 284 | * |
169 | #define SVGA_CAP_RASTER_OP 0x00000010 | 285 | * Using the guest framebuffer (GFB) at BAR1 for general purpose DMA |
170 | #define SVGA_CAP_CURSOR 0x00000020 | 286 | * is being phased out. Please try to use user-defined GMRs whenever |
171 | #define SVGA_CAP_CURSOR_BYPASS 0x00000040 | 287 | * possible. |
172 | #define SVGA_CAP_CURSOR_BYPASS_2 0x00000080 | 288 | */ |
173 | #define SVGA_CAP_8BIT_EMULATION 0x00000100 | 289 | #define SVGA_GMR_NULL ((uint32) -1) |
174 | #define SVGA_CAP_ALPHA_CURSOR 0x00000200 | 290 | #define SVGA_GMR_FRAMEBUFFER ((uint32) -2) /* Guest Framebuffer (GFB) */ |
175 | #define SVGA_CAP_GLYPH 0x00000400 | 291 | |
176 | #define SVGA_CAP_GLYPH_CLIPPING 0x00000800 | 292 | typedef |
177 | #define SVGA_CAP_OFFSCREEN_1 0x00001000 | 293 | struct SVGAGuestMemDescriptor { |
178 | #define SVGA_CAP_ALPHA_BLEND 0x00002000 | 294 | uint32 ppn; |
179 | #define SVGA_CAP_3D 0x00004000 | 295 | uint32 numPages; |
180 | #define SVGA_CAP_EXTENDED_FIFO 0x00008000 | 296 | } SVGAGuestMemDescriptor; |
181 | #define SVGA_CAP_MULTIMON 0x00010000 | 297 | |
182 | #define SVGA_CAP_PITCHLOCK 0x00020000 | 298 | typedef |
183 | #define SVGA_CAP_IRQMASK 0x00040000 | 299 | struct SVGAGuestPtr { |
184 | #define SVGA_CAP_DISPLAY_TOPOLOGY 0x00080000 | 300 | uint32 gmrId; |
301 | uint32 offset; | ||
302 | } SVGAGuestPtr; | ||
185 | 303 | ||
186 | 304 | ||
187 | /* | 305 | /* |
188 | * Raster op codes (same encoding as X) used by FIFO drivers. | 306 | * SVGAGMRImageFormat -- |
307 | * | ||
308 | * This is a packed representation of the source 2D image format | ||
309 | * for a GMR-to-screen blit. Currently it is defined as an encoding | ||
310 | * of the screen's color depth and bits-per-pixel, however, 16 bits | ||
311 | * are reserved for future use to identify other encodings (such as | ||
312 | * RGBA or higher-precision images). | ||
313 | * | ||
314 | * Currently supported formats: | ||
315 | * | ||
316 | * bpp depth Format Name | ||
317 | * --- ----- ----------- | ||
318 | * 32 24 32-bit BGRX | ||
319 | * 24 24 24-bit BGR | ||
320 | * 16 16 RGB 5-6-5 | ||
321 | * 16 15 RGB 5-5-5 | ||
322 | * | ||
189 | */ | 323 | */ |
190 | 324 | ||
191 | #define SVGA_ROP_CLEAR 0x00 /* 0 */ | 325 | typedef |
192 | #define SVGA_ROP_AND 0x01 /* src AND dst */ | 326 | struct SVGAGMRImageFormat { |
193 | #define SVGA_ROP_AND_REVERSE 0x02 /* src AND NOT dst */ | 327 | union { |
194 | #define SVGA_ROP_COPY 0x03 /* src */ | 328 | struct { |
195 | #define SVGA_ROP_AND_INVERTED 0x04 /* NOT src AND dst */ | 329 | uint32 bitsPerPixel : 8; |
196 | #define SVGA_ROP_NOOP 0x05 /* dst */ | 330 | uint32 colorDepth : 8; |
197 | #define SVGA_ROP_XOR 0x06 /* src XOR dst */ | 331 | uint32 reserved : 16; /* Must be zero */ |
198 | #define SVGA_ROP_OR 0x07 /* src OR dst */ | 332 | }; |
199 | #define SVGA_ROP_NOR 0x08 /* NOT src AND NOT dst */ | ||
200 | #define SVGA_ROP_EQUIV 0x09 /* NOT src XOR dst */ | ||
201 | #define SVGA_ROP_INVERT 0x0a /* NOT dst */ | ||
202 | #define SVGA_ROP_OR_REVERSE 0x0b /* src OR NOT dst */ | ||
203 | #define SVGA_ROP_COPY_INVERTED 0x0c /* NOT src */ | ||
204 | #define SVGA_ROP_OR_INVERTED 0x0d /* NOT src OR dst */ | ||
205 | #define SVGA_ROP_NAND 0x0e /* NOT src OR NOT dst */ | ||
206 | #define SVGA_ROP_SET 0x0f /* 1 */ | ||
207 | #define SVGA_ROP_UNSUPPORTED 0x10 | ||
208 | 333 | ||
209 | #define SVGA_NUM_SUPPORTED_ROPS 16 | 334 | uint32 value; |
210 | #define SVGA_ROP_ALL (MASK(SVGA_NUM_SUPPORTED_ROPS)) | 335 | }; |
211 | #define SVGA_IS_VALID_ROP(rop) (rop < SVGA_NUM_SUPPORTED_ROPS) | 336 | } SVGAGMRImageFormat; |
212 | 337 | ||
213 | #define SVGA_INVALID_DISPLAY_ID ((uint32)-1) | 338 | typedef |
339 | struct SVGAGuestImage { | ||
340 | SVGAGuestPtr ptr; | ||
341 | |||
342 | /* | ||
343 | * A note on interpretation of pitch: This value of pitch is the | ||
344 | * number of bytes between vertically adjacent image | ||
345 | * blocks. Normally this is the number of bytes between the first | ||
346 | * pixel of two adjacent scanlines. With compressed textures, | ||
347 | * however, this may represent the number of bytes between | ||
348 | * compression blocks rather than between rows of pixels. | ||
349 | * | ||
350 | * XXX: Compressed textures currently must be tightly packed in guest memory. | ||
351 | * | ||
352 | * If the image is 1-dimensional, pitch is ignored. | ||
353 | * | ||
354 | * If 'pitch' is zero, the SVGA3D device calculates a pitch value | ||
355 | * assuming each row of blocks is tightly packed. | ||
356 | */ | ||
357 | uint32 pitch; | ||
358 | } SVGAGuestImage; | ||
214 | 359 | ||
215 | /* | 360 | /* |
216 | * Ops | 361 | * SVGAColorBGRX -- |
217 | * For each pixel, the four channels of the image are computed with: | 362 | * |
218 | * | 363 | * A 24-bit color format (BGRX), which does not depend on the |
219 | * C = Ca * Fa + Cb * Fb | 364 | * format of the legacy guest framebuffer (GFB) or the current |
220 | * | 365 | * GMRFB state. |
221 | * where C, Ca, Cb are the values of the respective channels and Fa | 366 | */ |
222 | * and Fb come from the following table: | 367 | |
223 | * | 368 | typedef |
224 | * BlendOp Fa Fb | 369 | struct SVGAColorBGRX { |
225 | * ------------------------------------------ | 370 | union { |
226 | * Clear 0 0 | 371 | struct { |
227 | * Src 1 0 | 372 | uint32 b : 8; |
228 | * Dst 0 1 | 373 | uint32 g : 8; |
229 | * Over 1 1-Aa | 374 | uint32 r : 8; |
230 | * OverReverse 1-Ab 1 | 375 | uint32 x : 8; /* Unused */ |
231 | * In Ab 0 | 376 | }; |
232 | * InReverse 0 Aa | 377 | |
233 | * Out 1-Ab 0 | 378 | uint32 value; |
234 | * OutReverse 0 1-Aa | 379 | }; |
235 | * Atop Ab 1-Aa | 380 | } SVGAColorBGRX; |
236 | * AtopReverse 1-Ab Aa | 381 | |
237 | * Xor 1-Ab 1-Aa | 382 | |
238 | * Add 1 1 | 383 | /* |
239 | * Saturate min(1,(1-Ab)/Aa) 1 | 384 | * SVGASignedRect -- |
240 | * | 385 | * SVGASignedPoint -- |
241 | * Flags | 386 | * |
242 | * You can use the following flags to achieve additional affects: | 387 | * Signed rectangle and point primitives. These are used by the new |
243 | * | 388 | * 2D primitives for drawing to Screen Objects, which can occupy a |
244 | * Flag Effect | 389 | * signed virtual coordinate space. |
245 | * ------------------------------------------ | 390 | * |
246 | * ConstantSourceAlpha Ca = Ca * Param0 | 391 | * SVGASignedRect specifies a half-open interval: the (left, top) |
247 | * ConstantDestAlpha Cb = Cb * Param1 | 392 | * pixel is part of the rectangle, but the (right, bottom) pixel is |
248 | * | 393 | * not. |
249 | * Flag effects resolve before the op. For example | 394 | */ |
250 | * BlendOp == Add && Flags == ConstantSourceAlpha | | 395 | |
251 | * ConstantDestAlpha results in: | 396 | typedef |
252 | * | 397 | struct SVGASignedRect { |
253 | * C = (Ca * Param0) + (Cb * Param1) | 398 | int32 left; |
254 | */ | 399 | int32 top; |
255 | 400 | int32 right; | |
256 | #define SVGA_BLENDOP_CLEAR 0 | 401 | int32 bottom; |
257 | #define SVGA_BLENDOP_SRC 1 | 402 | } SVGASignedRect; |
258 | #define SVGA_BLENDOP_DST 2 | 403 | |
259 | #define SVGA_BLENDOP_OVER 3 | 404 | typedef |
260 | #define SVGA_BLENDOP_OVER_REVERSE 4 | 405 | struct SVGASignedPoint { |
261 | #define SVGA_BLENDOP_IN 5 | 406 | int32 x; |
262 | #define SVGA_BLENDOP_IN_REVERSE 6 | 407 | int32 y; |
263 | #define SVGA_BLENDOP_OUT 7 | 408 | } SVGASignedPoint; |
264 | #define SVGA_BLENDOP_OUT_REVERSE 8 | 409 | |
265 | #define SVGA_BLENDOP_ATOP 9 | 410 | |
266 | #define SVGA_BLENDOP_ATOP_REVERSE 10 | 411 | /* |
267 | #define SVGA_BLENDOP_XOR 11 | 412 | * Capabilities |
268 | #define SVGA_BLENDOP_ADD 12 | 413 | * |
269 | #define SVGA_BLENDOP_SATURATE 13 | 414 | * Note the holes in the bitfield. Missing bits have been deprecated, |
270 | 415 | * and must not be reused. Those capabilities will never be reported | |
271 | #define SVGA_NUM_BLENDOPS 14 | 416 | * by new versions of the SVGA device. |
272 | #define SVGA_IS_VALID_BLENDOP(op) (op >= 0 && op < SVGA_NUM_BLENDOPS) | 417 | * |
273 | 418 | * SVGA_CAP_GMR2 -- | |
274 | #define SVGA_BLENDFLAG_CONSTANT_SOURCE_ALPHA 0x01 | 419 | * Provides asynchronous commands to define and remap guest memory |
275 | #define SVGA_BLENDFLAG_CONSTANT_DEST_ALPHA 0x02 | 420 | * regions. Adds device registers SVGA_REG_GMRS_MAX_PAGES and |
276 | #define SVGA_NUM_BLENDFLAGS 2 | 421 | * SVGA_REG_MEMORY_SIZE. |
277 | #define SVGA_BLENDFLAG_ALL (MASK(SVGA_NUM_BLENDFLAGS)) | 422 | * |
278 | #define SVGA_IS_VALID_BLENDFLAG(flag) ((flag & ~SVGA_BLENDFLAG_ALL) == 0) | 423 | * SVGA_CAP_SCREEN_OBJECT_2 -- |
424 | * Allow screen object support, and require backing stores from the | ||
425 | * guest for each screen object. | ||
426 | */ | ||
427 | |||
428 | #define SVGA_CAP_NONE 0x00000000 | ||
429 | #define SVGA_CAP_RECT_COPY 0x00000002 | ||
430 | #define SVGA_CAP_CURSOR 0x00000020 | ||
431 | #define SVGA_CAP_CURSOR_BYPASS 0x00000040 /* Legacy (Use Cursor Bypass 3 instead) */ | ||
432 | #define SVGA_CAP_CURSOR_BYPASS_2 0x00000080 /* Legacy (Use Cursor Bypass 3 instead) */ | ||
433 | #define SVGA_CAP_8BIT_EMULATION 0x00000100 | ||
434 | #define SVGA_CAP_ALPHA_CURSOR 0x00000200 | ||
435 | #define SVGA_CAP_3D 0x00004000 | ||
436 | #define SVGA_CAP_EXTENDED_FIFO 0x00008000 | ||
437 | #define SVGA_CAP_MULTIMON 0x00010000 /* Legacy multi-monitor support */ | ||
438 | #define SVGA_CAP_PITCHLOCK 0x00020000 | ||
439 | #define SVGA_CAP_IRQMASK 0x00040000 | ||
440 | #define SVGA_CAP_DISPLAY_TOPOLOGY 0x00080000 /* Legacy multi-monitor support */ | ||
441 | #define SVGA_CAP_GMR 0x00100000 | ||
442 | #define SVGA_CAP_TRACES 0x00200000 | ||
443 | #define SVGA_CAP_GMR2 0x00400000 | ||
444 | #define SVGA_CAP_SCREEN_OBJECT_2 0x00800000 | ||
279 | 445 | ||
280 | 446 | ||
281 | /* | 447 | /* |
@@ -332,19 +498,47 @@ enum { | |||
332 | * These in block 3a, the VMX currently considers mandatory for the | 498 | * These in block 3a, the VMX currently considers mandatory for the |
333 | * extended FIFO. | 499 | * extended FIFO. |
334 | */ | 500 | */ |
335 | 501 | ||
336 | /* Valid if exists (i.e. if extended FIFO enabled): */ | 502 | /* Valid if exists (i.e. if extended FIFO enabled): */ |
337 | SVGA_FIFO_3D_HWVERSION, /* See SVGA3dHardwareVersion in svga3d_reg.h */ | 503 | SVGA_FIFO_3D_HWVERSION, /* See SVGA3dHardwareVersion in svga3d_reg.h */ |
338 | /* Valid with SVGA_FIFO_CAP_PITCHLOCK: */ | 504 | /* Valid with SVGA_FIFO_CAP_PITCHLOCK: */ |
339 | SVGA_FIFO_PITCHLOCK, | 505 | SVGA_FIFO_PITCHLOCK, |
506 | |||
340 | /* Valid with SVGA_FIFO_CAP_CURSOR_BYPASS_3: */ | 507 | /* Valid with SVGA_FIFO_CAP_CURSOR_BYPASS_3: */ |
341 | SVGA_FIFO_CURSOR_ON, /* Cursor bypass 3 show/hide register */ | 508 | SVGA_FIFO_CURSOR_ON, /* Cursor bypass 3 show/hide register */ |
342 | SVGA_FIFO_CURSOR_X, /* Cursor bypass 3 x register */ | 509 | SVGA_FIFO_CURSOR_X, /* Cursor bypass 3 x register */ |
343 | SVGA_FIFO_CURSOR_Y, /* Cursor bypass 3 y register */ | 510 | SVGA_FIFO_CURSOR_Y, /* Cursor bypass 3 y register */ |
344 | SVGA_FIFO_CURSOR_COUNT, /* Incremented when any of the other 3 change */ | 511 | SVGA_FIFO_CURSOR_COUNT, /* Incremented when any of the other 3 change */ |
345 | SVGA_FIFO_CURSOR_LAST_UPDATED,/* Last time the host updated the cursor */ | 512 | SVGA_FIFO_CURSOR_LAST_UPDATED,/* Last time the host updated the cursor */ |
513 | |||
346 | /* Valid with SVGA_FIFO_CAP_RESERVE: */ | 514 | /* Valid with SVGA_FIFO_CAP_RESERVE: */ |
347 | SVGA_FIFO_RESERVED, /* Bytes past NEXT_CMD with real contents */ | 515 | SVGA_FIFO_RESERVED, /* Bytes past NEXT_CMD with real contents */ |
516 | |||
517 | /* | ||
518 | * Valid with SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2: | ||
519 | * | ||
520 | * By default this is SVGA_ID_INVALID, to indicate that the cursor | ||
521 | * coordinates are specified relative to the virtual root. If this | ||
522 | * is set to a specific screen ID, cursor position is reinterpreted | ||
523 | * as a signed offset relative to that screen's origin. | ||
524 | */ | ||
525 | SVGA_FIFO_CURSOR_SCREEN_ID, | ||
526 | |||
527 | /* | ||
528 | * Valid with SVGA_FIFO_CAP_DEAD | ||
529 | * | ||
530 | * An arbitrary value written by the host, drivers should not use it. | ||
531 | */ | ||
532 | SVGA_FIFO_DEAD, | ||
533 | |||
534 | /* | ||
535 | * Valid with SVGA_FIFO_CAP_3D_HWVERSION_REVISED: | ||
536 | * | ||
537 | * Contains 3D HWVERSION (see SVGA3dHardwareVersion in svga3d_reg.h) | ||
538 | * on platforms that can enforce graphics resource limits. | ||
539 | */ | ||
540 | SVGA_FIFO_3D_HWVERSION_REVISED, | ||
541 | |||
348 | /* | 542 | /* |
349 | * XXX: The gap here, up until SVGA_FIFO_3D_CAPS, can be used for new | 543 | * XXX: The gap here, up until SVGA_FIFO_3D_CAPS, can be used for new |
350 | * registers, but this must be done carefully and with judicious use of | 544 | * registers, but this must be done carefully and with judicious use of |
@@ -361,6 +555,7 @@ enum { | |||
361 | * before 3D_CAPS, needs to reason about something other than | 555 | * before 3D_CAPS, needs to reason about something other than |
362 | * SVGA_FIFO_MIN. | 556 | * SVGA_FIFO_MIN. |
363 | */ | 557 | */ |
558 | |||
364 | /* | 559 | /* |
365 | * 3D caps block space; valid with 3D hardware version >= | 560 | * 3D caps block space; valid with 3D hardware version >= |
366 | * SVGA3D_HWVERSION_WS6_B1. | 561 | * SVGA3D_HWVERSION_WS6_B1. |
@@ -533,6 +728,87 @@ enum { | |||
533 | * Pitch Lock -- Pitch lock register is supported | 728 | * Pitch Lock -- Pitch lock register is supported |
534 | * Video -- SVGA Video overlay units are supported | 729 | * Video -- SVGA Video overlay units are supported |
535 | * Escape -- Escape command is supported | 730 | * Escape -- Escape command is supported |
731 | * | ||
732 | * XXX: Add longer descriptions for each capability, including a list | ||
733 | * of the new features that each capability provides. | ||
734 | * | ||
735 | * SVGA_FIFO_CAP_SCREEN_OBJECT -- | ||
736 | * | ||
737 | * Provides dynamic multi-screen rendering, for improved Unity and | ||
738 | * multi-monitor modes. With Screen Object, the guest can | ||
739 | * dynamically create and destroy 'screens', which can represent | ||
740 | * Unity windows or virtual monitors. Screen Object also provides | ||
741 | * strong guarantees that DMA operations happen only when | ||
742 | * guest-initiated. Screen Object deprecates the BAR1 guest | ||
743 | * framebuffer (GFB) and all commands that work only with the GFB. | ||
744 | * | ||
745 | * New registers: | ||
746 | * FIFO_CURSOR_SCREEN_ID, VIDEO_DATA_GMRID, VIDEO_DST_SCREEN_ID | ||
747 | * | ||
748 | * New 2D commands: | ||
749 | * DEFINE_SCREEN, DESTROY_SCREEN, DEFINE_GMRFB, BLIT_GMRFB_TO_SCREEN, | ||
750 | * BLIT_SCREEN_TO_GMRFB, ANNOTATION_FILL, ANNOTATION_COPY | ||
751 | * | ||
752 | * New 3D commands: | ||
753 | * BLIT_SURFACE_TO_SCREEN | ||
754 | * | ||
755 | * New guarantees: | ||
756 | * | ||
757 | * - The host will not read or write guest memory, including the GFB, | ||
758 | * except when explicitly initiated by a DMA command. | ||
759 | * | ||
760 | * - All DMA, including legacy DMA like UPDATE and PRESENT_READBACK, | ||
761 | * is guaranteed to complete before any subsequent FENCEs. | ||
762 | * | ||
763 | * - All legacy commands which affect a Screen (UPDATE, PRESENT, | ||
764 | * PRESENT_READBACK) as well as new Screen blit commands will | ||
765 | * all behave consistently as blits, and memory will be read | ||
766 | * or written in FIFO order. | ||
767 | * | ||
768 | * For example, if you PRESENT from one SVGA3D surface to multiple | ||
769 | * places on the screen, the data copied will always be from the | ||
770 | * SVGA3D surface at the time the PRESENT was issued in the FIFO. | ||
771 | * This was not necessarily true on devices without Screen Object. | ||
772 | * | ||
773 | * This means that on devices that support Screen Object, the | ||
774 | * PRESENT_READBACK command should not be necessary unless you | ||
775 | * actually want to read back the results of 3D rendering into | ||
776 | * system memory. (And for that, the BLIT_SCREEN_TO_GMRFB | ||
777 | * command provides a strict superset of functionality.) | ||
778 | * | ||
779 | * - When a screen is resized, either using Screen Object commands or | ||
780 | * legacy multimon registers, its contents are preserved. | ||
781 | * | ||
782 | * SVGA_FIFO_CAP_GMR2 -- | ||
783 | * | ||
784 | * Provides new commands to define and remap guest memory regions (GMR). | ||
785 | * | ||
786 | * New 2D commands: | ||
787 | * DEFINE_GMR2, REMAP_GMR2. | ||
788 | * | ||
789 | * SVGA_FIFO_CAP_3D_HWVERSION_REVISED -- | ||
790 | * | ||
791 | * Indicates new register SVGA_FIFO_3D_HWVERSION_REVISED exists. | ||
792 | * This register may replace SVGA_FIFO_3D_HWVERSION on platforms | ||
793 | * that enforce graphics resource limits. This allows the platform | ||
794 | * to clear SVGA_FIFO_3D_HWVERSION and disable 3D in legacy guest | ||
795 | * drivers that do not limit their resources. | ||
796 | * | ||
797 | * Note this is an alias to SVGA_FIFO_CAP_GMR2 because these indicators | ||
798 | * are codependent (and thus we use a single capability bit). | ||
799 | * | ||
800 | * SVGA_FIFO_CAP_SCREEN_OBJECT_2 -- | ||
801 | * | ||
802 | * Modifies the DEFINE_SCREEN command to include a guest provided | ||
803 | * backing store in GMR memory and the bytesPerLine for the backing | ||
804 | * store. This capability requires the use of a backing store when | ||
805 | * creating screen objects. However if SVGA_FIFO_CAP_SCREEN_OBJECT | ||
806 | * is present then backing stores are optional. | ||
807 | * | ||
808 | * SVGA_FIFO_CAP_DEAD -- | ||
809 | * | ||
810 | * Drivers should not use this cap bit. This cap bit can not be | ||
811 | * reused since some hosts already expose it. | ||
536 | */ | 812 | */ |
537 | 813 | ||
538 | #define SVGA_FIFO_CAP_NONE 0 | 814 | #define SVGA_FIFO_CAP_NONE 0 |
@@ -543,6 +819,11 @@ enum { | |||
543 | #define SVGA_FIFO_CAP_CURSOR_BYPASS_3 (1<<4) | 819 | #define SVGA_FIFO_CAP_CURSOR_BYPASS_3 (1<<4) |
544 | #define SVGA_FIFO_CAP_ESCAPE (1<<5) | 820 | #define SVGA_FIFO_CAP_ESCAPE (1<<5) |
545 | #define SVGA_FIFO_CAP_RESERVE (1<<6) | 821 | #define SVGA_FIFO_CAP_RESERVE (1<<6) |
822 | #define SVGA_FIFO_CAP_SCREEN_OBJECT (1<<7) | ||
823 | #define SVGA_FIFO_CAP_GMR2 (1<<8) | ||
824 | #define SVGA_FIFO_CAP_3D_HWVERSION_REVISED SVGA_FIFO_CAP_GMR2 | ||
825 | #define SVGA_FIFO_CAP_SCREEN_OBJECT_2 (1<<9) | ||
826 | #define SVGA_FIFO_CAP_DEAD (1<<10) | ||
546 | 827 | ||
547 | 828 | ||
548 | /* | 829 | /* |
@@ -586,20 +867,22 @@ enum { | |||
586 | SVGA_VIDEO_DATA_OFFSET, | 867 | SVGA_VIDEO_DATA_OFFSET, |
587 | SVGA_VIDEO_FORMAT, | 868 | SVGA_VIDEO_FORMAT, |
588 | SVGA_VIDEO_COLORKEY, | 869 | SVGA_VIDEO_COLORKEY, |
589 | SVGA_VIDEO_SIZE, | 870 | SVGA_VIDEO_SIZE, /* Deprecated */ |
590 | SVGA_VIDEO_WIDTH, | 871 | SVGA_VIDEO_WIDTH, |
591 | SVGA_VIDEO_HEIGHT, | 872 | SVGA_VIDEO_HEIGHT, |
592 | SVGA_VIDEO_SRC_X, | 873 | SVGA_VIDEO_SRC_X, |
593 | SVGA_VIDEO_SRC_Y, | 874 | SVGA_VIDEO_SRC_Y, |
594 | SVGA_VIDEO_SRC_WIDTH, | 875 | SVGA_VIDEO_SRC_WIDTH, |
595 | SVGA_VIDEO_SRC_HEIGHT, | 876 | SVGA_VIDEO_SRC_HEIGHT, |
596 | SVGA_VIDEO_DST_X, | 877 | SVGA_VIDEO_DST_X, /* Signed int32 */ |
597 | SVGA_VIDEO_DST_Y, | 878 | SVGA_VIDEO_DST_Y, /* Signed int32 */ |
598 | SVGA_VIDEO_DST_WIDTH, | 879 | SVGA_VIDEO_DST_WIDTH, |
599 | SVGA_VIDEO_DST_HEIGHT, | 880 | SVGA_VIDEO_DST_HEIGHT, |
600 | SVGA_VIDEO_PITCH_1, | 881 | SVGA_VIDEO_PITCH_1, |
601 | SVGA_VIDEO_PITCH_2, | 882 | SVGA_VIDEO_PITCH_2, |
602 | SVGA_VIDEO_PITCH_3, | 883 | SVGA_VIDEO_PITCH_3, |
884 | SVGA_VIDEO_DATA_GMRID, /* Optional, defaults to SVGA_GMR_FRAMEBUFFER */ | ||
885 | SVGA_VIDEO_DST_SCREEN_ID, /* Optional, defaults to virtual coords (SVGA_ID_INVALID) */ | ||
603 | SVGA_VIDEO_NUM_REGS | 886 | SVGA_VIDEO_NUM_REGS |
604 | }; | 887 | }; |
605 | 888 | ||
@@ -625,242 +908,658 @@ typedef struct SVGAOverlayUnit { | |||
625 | uint32 srcY; | 908 | uint32 srcY; |
626 | uint32 srcWidth; | 909 | uint32 srcWidth; |
627 | uint32 srcHeight; | 910 | uint32 srcHeight; |
628 | uint32 dstX; | 911 | int32 dstX; |
629 | uint32 dstY; | 912 | int32 dstY; |
630 | uint32 dstWidth; | 913 | uint32 dstWidth; |
631 | uint32 dstHeight; | 914 | uint32 dstHeight; |
632 | uint32 pitches[3]; | 915 | uint32 pitches[3]; |
916 | uint32 dataGMRId; | ||
917 | uint32 dstScreenId; | ||
633 | } SVGAOverlayUnit; | 918 | } SVGAOverlayUnit; |
634 | 919 | ||
635 | 920 | ||
636 | /* | 921 | /* |
637 | * Drawing object ID's, in the range 0 to SVGA_MAX_ID | 922 | * SVGAScreenObject -- |
923 | * | ||
924 | * This is a new way to represent a guest's multi-monitor screen or | ||
925 | * Unity window. Screen objects are only supported if the | ||
926 | * SVGA_FIFO_CAP_SCREEN_OBJECT capability bit is set. | ||
927 | * | ||
928 | * If Screen Objects are supported, they can be used to fully | ||
929 | * replace the functionality provided by the framebuffer registers | ||
930 | * (SVGA_REG_WIDTH, HEIGHT, etc.) and by SVGA_CAP_DISPLAY_TOPOLOGY. | ||
931 | * | ||
932 | * The screen object is a struct with guaranteed binary | ||
933 | * compatibility. New flags can be added, and the struct may grow, | ||
934 | * but existing fields must retain their meaning. | ||
935 | * | ||
936 | * Added with SVGA_FIFO_CAP_SCREEN_OBJECT_2 are required fields of | ||
937 | * a SVGAGuestPtr that is used to back the screen contents. This | ||
938 | * memory must come from the GFB. The guest is not allowed to | ||
939 | * access the memory and doing so will have undefined results. The | ||
940 | * backing store is required to be page aligned and the size is | ||
941 | * padded to the next page boundry. The number of pages is: | ||
942 | * (bytesPerLine * size.width * 4 + PAGE_SIZE - 1) / PAGE_SIZE | ||
943 | * | ||
944 | * The pitch in the backingStore is required to be at least large | ||
945 | * enough to hold a 32bbp scanline. It is recommended that the | ||
946 | * driver pad bytesPerLine for a potential performance win. | ||
947 | * | ||
948 | * The cloneCount field is treated as a hint from the guest that | ||
949 | * the user wants this display to be cloned, countCount times. A | ||
950 | * value of zero means no cloning should happen. | ||
638 | */ | 951 | */ |
639 | 952 | ||
640 | #define SVGA_MAX_ID 499 | 953 | #define SVGA_SCREEN_MUST_BE_SET (1 << 0) /* Must be set or results undefined */ |
954 | #define SVGA_SCREEN_HAS_ROOT SVGA_SCREEN_MUST_BE_SET /* Deprecated */ | ||
955 | #define SVGA_SCREEN_IS_PRIMARY (1 << 1) /* Guest considers this screen to be 'primary' */ | ||
956 | #define SVGA_SCREEN_FULLSCREEN_HINT (1 << 2) /* Guest is running a fullscreen app here */ | ||
641 | 957 | ||
642 | /* | 958 | /* |
643 | * Macros to compute variable length items (sizes in 32-bit words, except | 959 | * Added with SVGA_FIFO_CAP_SCREEN_OBJECT_2. When the screen is |
644 | * for SVGA_GLYPH_SCANLINE_SIZE, which is in bytes). | 960 | * deactivated the base layer is defined to lose all contents and |
961 | * become black. When a screen is deactivated the backing store is | ||
962 | * optional. When set backingPtr and bytesPerLine will be ignored. | ||
645 | */ | 963 | */ |
964 | #define SVGA_SCREEN_DEACTIVATE (1 << 3) | ||
965 | |||
966 | /* | ||
967 | * Added with SVGA_FIFO_CAP_SCREEN_OBJECT_2. When this flag is set | ||
968 | * the screen contents will be outputted as all black to the user | ||
969 | * though the base layer contents is preserved. The screen base layer | ||
970 | * can still be read and written to like normal though the no visible | ||
971 | * effect will be seen by the user. When the flag is changed the | ||
972 | * screen will be blanked or redrawn to the current contents as needed | ||
973 | * without any extra commands from the driver. This flag only has an | ||
974 | * effect when the screen is not deactivated. | ||
975 | */ | ||
976 | #define SVGA_SCREEN_BLANKING (1 << 4) | ||
977 | |||
978 | typedef | ||
979 | struct SVGAScreenObject { | ||
980 | uint32 structSize; /* sizeof(SVGAScreenObject) */ | ||
981 | uint32 id; | ||
982 | uint32 flags; | ||
983 | struct { | ||
984 | uint32 width; | ||
985 | uint32 height; | ||
986 | } size; | ||
987 | struct { | ||
988 | int32 x; | ||
989 | int32 y; | ||
990 | } root; | ||
991 | |||
992 | /* | ||
993 | * Added and required by SVGA_FIFO_CAP_SCREEN_OBJECT_2, optional | ||
994 | * with SVGA_FIFO_CAP_SCREEN_OBJECT. | ||
995 | */ | ||
996 | SVGAGuestImage backingStore; | ||
997 | uint32 cloneCount; | ||
998 | } SVGAScreenObject; | ||
646 | 999 | ||
647 | #define SVGA_BITMAP_SIZE(w,h) ((((w)+31) >> 5) * (h)) | ||
648 | #define SVGA_BITMAP_SCANLINE_SIZE(w) (( (w)+31 ) >> 5) | ||
649 | #define SVGA_PIXMAP_SIZE(w,h,bpp) ((( ((w)*(bpp))+31 ) >> 5) * (h)) | ||
650 | #define SVGA_PIXMAP_SCANLINE_SIZE(w,bpp) (( ((w)*(bpp))+31 ) >> 5) | ||
651 | #define SVGA_GLYPH_SIZE(w,h) ((((((w) + 7) >> 3) * (h)) + 3) >> 2) | ||
652 | #define SVGA_GLYPH_SCANLINE_SIZE(w) (((w) + 7) >> 3) | ||
653 | #define SVGA_ESCAPE_SIZE(s) (((s) + 3) >> 2) | ||
654 | 1000 | ||
655 | /* | 1001 | /* |
656 | * Increment from one scanline to the next of a bitmap or pixmap | 1002 | * Commands in the command FIFO: |
1003 | * | ||
1004 | * Command IDs defined below are used for the traditional 2D FIFO | ||
1005 | * communication (not all commands are available for all versions of the | ||
1006 | * SVGA FIFO protocol). | ||
1007 | * | ||
1008 | * Note the holes in the command ID numbers: These commands have been | ||
1009 | * deprecated, and the old IDs must not be reused. | ||
1010 | * | ||
1011 | * Command IDs from 1000 to 1999 are reserved for use by the SVGA3D | ||
1012 | * protocol. | ||
1013 | * | ||
1014 | * Each command's parameters are described by the comments and | ||
1015 | * structs below. | ||
657 | */ | 1016 | */ |
658 | #define SVGA_BITMAP_INCREMENT(w) ((( (w)+31 ) >> 5) * sizeof (uint32)) | 1017 | |
659 | #define SVGA_PIXMAP_INCREMENT(w,bpp) ((( ((w)*(bpp))+31 ) >> 5) * sizeof (uint32)) | 1018 | typedef enum { |
1019 | SVGA_CMD_INVALID_CMD = 0, | ||
1020 | SVGA_CMD_UPDATE = 1, | ||
1021 | SVGA_CMD_RECT_COPY = 3, | ||
1022 | SVGA_CMD_DEFINE_CURSOR = 19, | ||
1023 | SVGA_CMD_DEFINE_ALPHA_CURSOR = 22, | ||
1024 | SVGA_CMD_UPDATE_VERBOSE = 25, | ||
1025 | SVGA_CMD_FRONT_ROP_FILL = 29, | ||
1026 | SVGA_CMD_FENCE = 30, | ||
1027 | SVGA_CMD_ESCAPE = 33, | ||
1028 | SVGA_CMD_DEFINE_SCREEN = 34, | ||
1029 | SVGA_CMD_DESTROY_SCREEN = 35, | ||
1030 | SVGA_CMD_DEFINE_GMRFB = 36, | ||
1031 | SVGA_CMD_BLIT_GMRFB_TO_SCREEN = 37, | ||
1032 | SVGA_CMD_BLIT_SCREEN_TO_GMRFB = 38, | ||
1033 | SVGA_CMD_ANNOTATION_FILL = 39, | ||
1034 | SVGA_CMD_ANNOTATION_COPY = 40, | ||
1035 | SVGA_CMD_DEFINE_GMR2 = 41, | ||
1036 | SVGA_CMD_REMAP_GMR2 = 42, | ||
1037 | SVGA_CMD_MAX | ||
1038 | } SVGAFifoCmdId; | ||
1039 | |||
1040 | #define SVGA_CMD_MAX_ARGS 64 | ||
1041 | |||
660 | 1042 | ||
661 | /* | 1043 | /* |
662 | * Transparent color for DRAW_GLYPH_CLIPPED | 1044 | * SVGA_CMD_UPDATE -- |
1045 | * | ||
1046 | * This is a DMA transfer which copies from the Guest Framebuffer | ||
1047 | * (GFB) at BAR1 + SVGA_REG_FB_OFFSET to any screens which | ||
1048 | * intersect with the provided virtual rectangle. | ||
1049 | * | ||
1050 | * This command does not support using arbitrary guest memory as a | ||
1051 | * data source- it only works with the pre-defined GFB memory. | ||
1052 | * This command also does not support signed virtual coordinates. | ||
1053 | * If you have defined screens (using SVGA_CMD_DEFINE_SCREEN) with | ||
1054 | * negative root x/y coordinates, the negative portion of those | ||
1055 | * screens will not be reachable by this command. | ||
1056 | * | ||
1057 | * This command is not necessary when using framebuffer | ||
1058 | * traces. Traces are automatically enabled if the SVGA FIFO is | ||
1059 | * disabled, and you may explicitly enable/disable traces using | ||
1060 | * SVGA_REG_TRACES. With traces enabled, any write to the GFB will | ||
1061 | * automatically act as if a subsequent SVGA_CMD_UPDATE was issued. | ||
1062 | * | ||
1063 | * Traces and SVGA_CMD_UPDATE are the only supported ways to render | ||
1064 | * pseudocolor screen updates. The newer Screen Object commands | ||
1065 | * only support true color formats. | ||
1066 | * | ||
1067 | * Availability: | ||
1068 | * Always available. | ||
663 | */ | 1069 | */ |
664 | #define SVGA_COLOR_TRANSPARENT (~0) | 1070 | |
1071 | typedef | ||
1072 | struct SVGAFifoCmdUpdate { | ||
1073 | uint32 x; | ||
1074 | uint32 y; | ||
1075 | uint32 width; | ||
1076 | uint32 height; | ||
1077 | } SVGAFifoCmdUpdate; | ||
1078 | |||
665 | 1079 | ||
666 | /* | 1080 | /* |
667 | * Commands in the command FIFO | 1081 | * SVGA_CMD_RECT_COPY -- |
1082 | * | ||
1083 | * Perform a rectangular DMA transfer from one area of the GFB to | ||
1084 | * another, and copy the result to any screens which intersect it. | ||
1085 | * | ||
1086 | * Availability: | ||
1087 | * SVGA_CAP_RECT_COPY | ||
668 | */ | 1088 | */ |
669 | 1089 | ||
670 | #define SVGA_CMD_INVALID_CMD 0 | 1090 | typedef |
671 | /* FIFO layout: | 1091 | struct SVGAFifoCmdRectCopy { |
672 | <nothing> (well, undefined) */ | 1092 | uint32 srcX; |
1093 | uint32 srcY; | ||
1094 | uint32 destX; | ||
1095 | uint32 destY; | ||
1096 | uint32 width; | ||
1097 | uint32 height; | ||
1098 | } SVGAFifoCmdRectCopy; | ||
673 | 1099 | ||
674 | #define SVGA_CMD_UPDATE 1 | ||
675 | /* FIFO layout: | ||
676 | X, Y, Width, Height */ | ||
677 | 1100 | ||
678 | #define SVGA_CMD_RECT_FILL 2 | 1101 | /* |
679 | /* FIFO layout: | 1102 | * SVGA_CMD_DEFINE_CURSOR -- |
680 | Color, X, Y, Width, Height */ | 1103 | * |
1104 | * Provide a new cursor image, as an AND/XOR mask. | ||
1105 | * | ||
1106 | * The recommended way to position the cursor overlay is by using | ||
1107 | * the SVGA_FIFO_CURSOR_* registers, supported by the | ||
1108 | * SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability. | ||
1109 | * | ||
1110 | * Availability: | ||
1111 | * SVGA_CAP_CURSOR | ||
1112 | */ | ||
681 | 1113 | ||
682 | #define SVGA_CMD_RECT_COPY 3 | 1114 | typedef |
683 | /* FIFO layout: | 1115 | struct SVGAFifoCmdDefineCursor { |
684 | Source X, Source Y, Dest X, Dest Y, Width, Height */ | 1116 | uint32 id; /* Reserved, must be zero. */ |
1117 | uint32 hotspotX; | ||
1118 | uint32 hotspotY; | ||
1119 | uint32 width; | ||
1120 | uint32 height; | ||
1121 | uint32 andMaskDepth; /* Value must be 1 or equal to BITS_PER_PIXEL */ | ||
1122 | uint32 xorMaskDepth; /* Value must be 1 or equal to BITS_PER_PIXEL */ | ||
1123 | /* | ||
1124 | * Followed by scanline data for AND mask, then XOR mask. | ||
1125 | * Each scanline is padded to a 32-bit boundary. | ||
1126 | */ | ||
1127 | } SVGAFifoCmdDefineCursor; | ||
685 | 1128 | ||
686 | #define SVGA_CMD_DEFINE_BITMAP 4 | ||
687 | /* FIFO layout: | ||
688 | Pixmap ID, Width, Height, <scanlines> */ | ||
689 | 1129 | ||
690 | #define SVGA_CMD_DEFINE_BITMAP_SCANLINE 5 | 1130 | /* |
691 | /* FIFO layout: | 1131 | * SVGA_CMD_DEFINE_ALPHA_CURSOR -- |
692 | Pixmap ID, Width, Height, Line #, scanline */ | 1132 | * |
1133 | * Provide a new cursor image, in 32-bit BGRA format. | ||
1134 | * | ||
1135 | * The recommended way to position the cursor overlay is by using | ||
1136 | * the SVGA_FIFO_CURSOR_* registers, supported by the | ||
1137 | * SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability. | ||
1138 | * | ||
1139 | * Availability: | ||
1140 | * SVGA_CAP_ALPHA_CURSOR | ||
1141 | */ | ||
693 | 1142 | ||
694 | #define SVGA_CMD_DEFINE_PIXMAP 6 | 1143 | typedef |
695 | /* FIFO layout: | 1144 | struct SVGAFifoCmdDefineAlphaCursor { |
696 | Pixmap ID, Width, Height, Depth, <scanlines> */ | 1145 | uint32 id; /* Reserved, must be zero. */ |
1146 | uint32 hotspotX; | ||
1147 | uint32 hotspotY; | ||
1148 | uint32 width; | ||
1149 | uint32 height; | ||
1150 | /* Followed by scanline data */ | ||
1151 | } SVGAFifoCmdDefineAlphaCursor; | ||
697 | 1152 | ||
698 | #define SVGA_CMD_DEFINE_PIXMAP_SCANLINE 7 | ||
699 | /* FIFO layout: | ||
700 | Pixmap ID, Width, Height, Depth, Line #, scanline */ | ||
701 | 1153 | ||
702 | #define SVGA_CMD_RECT_BITMAP_FILL 8 | 1154 | /* |
703 | /* FIFO layout: | 1155 | * SVGA_CMD_UPDATE_VERBOSE -- |
704 | Bitmap ID, X, Y, Width, Height, Foreground, Background */ | 1156 | * |
1157 | * Just like SVGA_CMD_UPDATE, but also provide a per-rectangle | ||
1158 | * 'reason' value, an opaque cookie which is used by internal | ||
1159 | * debugging tools. Third party drivers should not use this | ||
1160 | * command. | ||
1161 | * | ||
1162 | * Availability: | ||
1163 | * SVGA_CAP_EXTENDED_FIFO | ||
1164 | */ | ||
705 | 1165 | ||
706 | #define SVGA_CMD_RECT_PIXMAP_FILL 9 | 1166 | typedef |
707 | /* FIFO layout: | 1167 | struct SVGAFifoCmdUpdateVerbose { |
708 | Pixmap ID, X, Y, Width, Height */ | 1168 | uint32 x; |
1169 | uint32 y; | ||
1170 | uint32 width; | ||
1171 | uint32 height; | ||
1172 | uint32 reason; | ||
1173 | } SVGAFifoCmdUpdateVerbose; | ||
709 | 1174 | ||
710 | #define SVGA_CMD_RECT_BITMAP_COPY 10 | ||
711 | /* FIFO layout: | ||
712 | Bitmap ID, Source X, Source Y, Dest X, Dest Y, | ||
713 | Width, Height, Foreground, Background */ | ||
714 | 1175 | ||
715 | #define SVGA_CMD_RECT_PIXMAP_COPY 11 | 1176 | /* |
716 | /* FIFO layout: | 1177 | * SVGA_CMD_FRONT_ROP_FILL -- |
717 | Pixmap ID, Source X, Source Y, Dest X, Dest Y, Width, Height */ | 1178 | * |
1179 | * This is a hint which tells the SVGA device that the driver has | ||
1180 | * just filled a rectangular region of the GFB with a solid | ||
1181 | * color. Instead of reading these pixels from the GFB, the device | ||
1182 | * can assume that they all equal 'color'. This is primarily used | ||
1183 | * for remote desktop protocols. | ||
1184 | * | ||
1185 | * Availability: | ||
1186 | * SVGA_FIFO_CAP_ACCELFRONT | ||
1187 | */ | ||
1188 | |||
1189 | #define SVGA_ROP_COPY 0x03 | ||
718 | 1190 | ||
719 | #define SVGA_CMD_FREE_OBJECT 12 | 1191 | #define SVGA_INVALID_DISPLAY_ID ((uint32)-1) |
720 | /* FIFO layout: | ||
721 | Object (pixmap, bitmap, ...) ID */ | ||
722 | 1192 | ||
723 | #define SVGA_CMD_RECT_ROP_FILL 13 | 1193 | typedef |
724 | /* FIFO layout: | 1194 | struct SVGAFifoCmdFrontRopFill { |
725 | Color, X, Y, Width, Height, ROP */ | 1195 | uint32 color; /* In the same format as the GFB */ |
1196 | uint32 x; | ||
1197 | uint32 y; | ||
1198 | uint32 width; | ||
1199 | uint32 height; | ||
1200 | uint32 rop; /* Must be SVGA_ROP_COPY */ | ||
1201 | } SVGAFifoCmdFrontRopFill; | ||
726 | 1202 | ||
727 | #define SVGA_CMD_RECT_ROP_COPY 14 | ||
728 | /* FIFO layout: | ||
729 | Source X, Source Y, Dest X, Dest Y, Width, Height, ROP */ | ||
730 | 1203 | ||
731 | #define SVGA_CMD_RECT_ROP_BITMAP_FILL 15 | 1204 | /* |
732 | /* FIFO layout: | 1205 | * SVGA_CMD_FENCE -- |
733 | ID, X, Y, Width, Height, Foreground, Background, ROP */ | 1206 | * |
1207 | * Insert a synchronization fence. When the SVGA device reaches | ||
1208 | * this command, it will copy the 'fence' value into the | ||
1209 | * SVGA_FIFO_FENCE register. It will also compare the fence against | ||
1210 | * SVGA_FIFO_FENCE_GOAL. If the fence matches the goal and the | ||
1211 | * SVGA_IRQFLAG_FENCE_GOAL interrupt is enabled, the device will | ||
1212 | * raise this interrupt. | ||
1213 | * | ||
1214 | * Availability: | ||
1215 | * SVGA_FIFO_FENCE for this command, | ||
1216 | * SVGA_CAP_IRQMASK for SVGA_FIFO_FENCE_GOAL. | ||
1217 | */ | ||
734 | 1218 | ||
735 | #define SVGA_CMD_RECT_ROP_PIXMAP_FILL 16 | 1219 | typedef |
736 | /* FIFO layout: | 1220 | struct { |
737 | ID, X, Y, Width, Height, ROP */ | 1221 | uint32 fence; |
1222 | } SVGAFifoCmdFence; | ||
738 | 1223 | ||
739 | #define SVGA_CMD_RECT_ROP_BITMAP_COPY 17 | ||
740 | /* FIFO layout: | ||
741 | ID, Source X, Source Y, | ||
742 | Dest X, Dest Y, Width, Height, Foreground, Background, ROP */ | ||
743 | 1224 | ||
744 | #define SVGA_CMD_RECT_ROP_PIXMAP_COPY 18 | 1225 | /* |
745 | /* FIFO layout: | 1226 | * SVGA_CMD_ESCAPE -- |
746 | ID, Source X, Source Y, Dest X, Dest Y, Width, Height, ROP */ | 1227 | * |
1228 | * Send an extended or vendor-specific variable length command. | ||
1229 | * This is used for video overlay, third party plugins, and | ||
1230 | * internal debugging tools. See svga_escape.h | ||
1231 | * | ||
1232 | * Availability: | ||
1233 | * SVGA_FIFO_CAP_ESCAPE | ||
1234 | */ | ||
747 | 1235 | ||
748 | #define SVGA_CMD_DEFINE_CURSOR 19 | 1236 | typedef |
749 | /* FIFO layout: | 1237 | struct SVGAFifoCmdEscape { |
750 | ID, Hotspot X, Hotspot Y, Width, Height, | 1238 | uint32 nsid; |
751 | Depth for AND mask, Depth for XOR mask, | 1239 | uint32 size; |
752 | <scanlines for AND mask>, <scanlines for XOR mask> */ | 1240 | /* followed by 'size' bytes of data */ |
1241 | } SVGAFifoCmdEscape; | ||
753 | 1242 | ||
754 | #define SVGA_CMD_DISPLAY_CURSOR 20 | ||
755 | /* FIFO layout: | ||
756 | ID, On/Off (1 or 0) */ | ||
757 | 1243 | ||
758 | #define SVGA_CMD_MOVE_CURSOR 21 | 1244 | /* |
759 | /* FIFO layout: | 1245 | * SVGA_CMD_DEFINE_SCREEN -- |
760 | X, Y */ | 1246 | * |
1247 | * Define or redefine an SVGAScreenObject. See the description of | ||
1248 | * SVGAScreenObject above. The video driver is responsible for | ||
1249 | * generating new screen IDs. They should be small positive | ||
1250 | * integers. The virtual device will have an implementation | ||
1251 | * specific upper limit on the number of screen IDs | ||
1252 | * supported. Drivers are responsible for recycling IDs. The first | ||
1253 | * valid ID is zero. | ||
1254 | * | ||
1255 | * - Interaction with other registers: | ||
1256 | * | ||
1257 | * For backwards compatibility, when the GFB mode registers (WIDTH, | ||
1258 | * HEIGHT, PITCHLOCK, BITS_PER_PIXEL) are modified, the SVGA device | ||
1259 | * deletes all screens other than screen #0, and redefines screen | ||
1260 | * #0 according to the specified mode. Drivers that use | ||
1261 | * SVGA_CMD_DEFINE_SCREEN should destroy or redefine screen #0. | ||
1262 | * | ||
1263 | * If you use screen objects, do not use the legacy multi-mon | ||
1264 | * registers (SVGA_REG_NUM_GUEST_DISPLAYS, SVGA_REG_DISPLAY_*). | ||
1265 | * | ||
1266 | * Availability: | ||
1267 | * SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2 | ||
1268 | */ | ||
761 | 1269 | ||
762 | #define SVGA_CMD_DEFINE_ALPHA_CURSOR 22 | 1270 | typedef |
763 | /* FIFO layout: | 1271 | struct { |
764 | ID, Hotspot X, Hotspot Y, Width, Height, | 1272 | SVGAScreenObject screen; /* Variable-length according to version */ |
765 | <scanlines> */ | 1273 | } SVGAFifoCmdDefineScreen; |
766 | 1274 | ||
767 | #define SVGA_CMD_DRAW_GLYPH 23 | ||
768 | /* FIFO layout: | ||
769 | X, Y, W, H, FGCOLOR, <stencil buffer> */ | ||
770 | |||
771 | #define SVGA_CMD_DRAW_GLYPH_CLIPPED 24 | ||
772 | /* FIFO layout: | ||
773 | X, Y, W, H, FGCOLOR, BGCOLOR, <cliprect>, <stencil buffer> | ||
774 | Transparent color expands are done by setting BGCOLOR to ~0 */ | ||
775 | |||
776 | #define SVGA_CMD_UPDATE_VERBOSE 25 | ||
777 | /* FIFO layout: | ||
778 | X, Y, Width, Height, Reason */ | ||
779 | |||
780 | #define SVGA_CMD_SURFACE_FILL 26 | ||
781 | /* FIFO layout: | ||
782 | color, dstSurfaceOffset, x, y, w, h, rop */ | ||
783 | |||
784 | #define SVGA_CMD_SURFACE_COPY 27 | ||
785 | /* FIFO layout: | ||
786 | srcSurfaceOffset, dstSurfaceOffset, srcX, srcY, | ||
787 | destX, destY, w, h, rop */ | ||
788 | |||
789 | #define SVGA_CMD_SURFACE_ALPHA_BLEND 28 | ||
790 | /* FIFO layout: | ||
791 | srcSurfaceOffset, dstSurfaceOffset, srcX, srcY, | ||
792 | destX, destY, w, h, op (SVGA_BLENDOP*), flags (SVGA_BLENDFLAGS*), | ||
793 | param1, param2 */ | ||
794 | |||
795 | #define SVGA_CMD_FRONT_ROP_FILL 29 | ||
796 | /* FIFO layout: | ||
797 | Color, X, Y, Width, Height, ROP */ | ||
798 | |||
799 | #define SVGA_CMD_FENCE 30 | ||
800 | /* FIFO layout: | ||
801 | Fence value */ | ||
802 | |||
803 | #define SVGA_CMD_VIDEO_PLAY_OBSOLETE 31 | ||
804 | /* Obsolete; do not use. */ | ||
805 | |||
806 | #define SVGA_CMD_VIDEO_END_OBSOLETE 32 | ||
807 | /* Obsolete; do not use. */ | ||
808 | |||
809 | #define SVGA_CMD_ESCAPE 33 | ||
810 | /* FIFO layout: | ||
811 | Namespace ID, size(bytes), data */ | ||
812 | |||
813 | #define SVGA_CMD_MAX 34 | ||
814 | |||
815 | #define SVGA_CMD_MAX_ARGS 64 | ||
816 | |||
817 | /* | ||
818 | * Location and size of SVGA frame buffer and the FIFO. | ||
819 | */ | ||
820 | #define SVGA_VRAM_MIN_SIZE (4 * 640 * 480) /* bytes */ | ||
821 | #define SVGA_VRAM_MAX_SIZE (128 * 1024 * 1024) | ||
822 | |||
823 | #define SVGA_VRAM_SIZE_WS (16 * 1024 * 1024) /* 16 MB */ | ||
824 | #define SVGA_MEM_SIZE_WS (2 * 1024 * 1024) /* 2 MB */ | ||
825 | #define SVGA_VRAM_SIZE_SERVER (4 * 1024 * 1024) /* 4 MB */ | ||
826 | #define SVGA_MEM_SIZE_SERVER (256 * 1024) /* 256 KB */ | ||
827 | |||
828 | #if /* defined(VMX86_WGS) || */ defined(VMX86_SERVER) | ||
829 | #define SVGA_VRAM_SIZE SVGA_VRAM_SIZE_SERVER | ||
830 | #define SVGA_MEM_SIZE SVGA_MEM_SIZE_SERVER | ||
831 | #else | ||
832 | #define SVGA_VRAM_SIZE SVGA_VRAM_SIZE_WS | ||
833 | #define SVGA_MEM_SIZE SVGA_MEM_SIZE_WS | ||
834 | #endif | ||
835 | 1275 | ||
836 | /* | 1276 | /* |
837 | * SVGA_FB_START is the default starting address of the SVGA frame | 1277 | * SVGA_CMD_DESTROY_SCREEN -- |
838 | * buffer in the guest's physical address space. | 1278 | * |
839 | * SVGA_FB_START_BIGMEM is the starting address of the SVGA frame | 1279 | * Destroy an SVGAScreenObject. Its ID is immediately available for |
840 | * buffer for VMs that have a large amount of physical memory. | 1280 | * re-use. |
841 | * | 1281 | * |
842 | * The address of SVGA_FB_START is set to 2GB - (SVGA_FB_MAX_SIZE + SVGA_MEM_SIZE), | 1282 | * Availability: |
843 | * thus the SVGA frame buffer sits at [SVGA_FB_START .. 2GB-1] in the | 1283 | * SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2 |
844 | * physical address space. Our older SVGA drivers for NT treat the | 1284 | */ |
845 | * address of the frame buffer as a signed integer. For backwards | 1285 | |
846 | * compatibility, we keep the default location of the frame buffer | 1286 | typedef |
847 | * at under 2GB in the address space. This restricts VMs to have "only" | 1287 | struct { |
848 | * up to ~2031MB (i.e., up to SVGA_FB_START) of physical memory. | 1288 | uint32 screenId; |
849 | * | 1289 | } SVGAFifoCmdDestroyScreen; |
850 | * For VMs that want more memory than the ~2031MB, we place the SVGA | 1290 | |
851 | * frame buffer at SVGA_FB_START_BIGMEM. This allows VMs to have up | 1291 | |
852 | * to 3584MB, at least as far as the SVGA frame buffer is concerned | 1292 | /* |
853 | * (note that there may be other issues that limit the VM memory | 1293 | * SVGA_CMD_DEFINE_GMRFB -- |
854 | * size). PCI devices use high memory addresses, so we have to put | 1294 | * |
855 | * SVGA_FB_START_BIGMEM low enough so that it doesn't overlap with any | 1295 | * This command sets a piece of SVGA device state called the |
856 | * of these devices. Placing SVGA_FB_START_BIGMEM at 0xE0000000 | 1296 | * Guest Memory Region Framebuffer, or GMRFB. The GMRFB is a |
857 | * should leave plenty of room for the PCI devices. | 1297 | * piece of light-weight state which identifies the location and |
858 | * | 1298 | * format of an image in guest memory or in BAR1. The GMRFB has |
859 | * NOTE: All of that is only true for the 0710 chipset. As of the 0405 | 1299 | * an arbitrary size, and it doesn't need to match the geometry |
860 | * chipset, the framebuffer start is determined solely based on the value | 1300 | * of the GFB or any screen object. |
861 | * the guest BIOS or OS programs into the PCI base address registers. | 1301 | * |
862 | */ | 1302 | * The GMRFB can be redefined as often as you like. You could |
863 | #define SVGA_FB_LEGACY_START 0x7EFC0000 | 1303 | * always use the same GMRFB, you could redefine it before |
864 | #define SVGA_FB_LEGACY_START_BIGMEM 0xE0000000 | 1304 | * rendering from a different guest screen, or you could even |
1305 | * redefine it before every blit. | ||
1306 | * | ||
1307 | * There are multiple ways to use this command. The simplest way is | ||
1308 | * to use it to move the framebuffer either to elsewhere in the GFB | ||
1309 | * (BAR1) memory region, or to a user-defined GMR. This lets a | ||
1310 | * driver use a framebuffer allocated entirely out of normal system | ||
1311 | * memory, which we encourage. | ||
1312 | * | ||
1313 | * Another way to use this command is to set up a ring buffer of | ||
1314 | * updates in GFB memory. If a driver wants to ensure that no | ||
1315 | * frames are skipped by the SVGA device, it is important that the | ||
1316 | * driver not modify the source data for a blit until the device is | ||
1317 | * done processing the command. One efficient way to accomplish | ||
1318 | * this is to use a ring of small DMA buffers. Each buffer is used | ||
1319 | * for one blit, then we move on to the next buffer in the | ||
1320 | * ring. The FENCE mechanism is used to protect each buffer from | ||
1321 | * re-use until the device is finished with that buffer's | ||
1322 | * corresponding blit. | ||
1323 | * | ||
1324 | * This command does not affect the meaning of SVGA_CMD_UPDATE. | ||
1325 | * UPDATEs always occur from the legacy GFB memory area. This | ||
1326 | * command has no support for pseudocolor GMRFBs. Currently only | ||
1327 | * true-color 15, 16, and 24-bit depths are supported. Future | ||
1328 | * devices may expose capabilities for additional framebuffer | ||
1329 | * formats. | ||
1330 | * | ||
1331 | * The default GMRFB value is undefined. Drivers must always send | ||
1332 | * this command at least once before performing any blit from the | ||
1333 | * GMRFB. | ||
1334 | * | ||
1335 | * Availability: | ||
1336 | * SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2 | ||
1337 | */ | ||
1338 | |||
1339 | typedef | ||
1340 | struct { | ||
1341 | SVGAGuestPtr ptr; | ||
1342 | uint32 bytesPerLine; | ||
1343 | SVGAGMRImageFormat format; | ||
1344 | } SVGAFifoCmdDefineGMRFB; | ||
1345 | |||
1346 | |||
1347 | /* | ||
1348 | * SVGA_CMD_BLIT_GMRFB_TO_SCREEN -- | ||
1349 | * | ||
1350 | * This is a guest-to-host blit. It performs a DMA operation to | ||
1351 | * copy a rectangular region of pixels from the current GMRFB to | ||
1352 | * one or more Screen Objects. | ||
1353 | * | ||
1354 | * The destination coordinate may be specified relative to a | ||
1355 | * screen's origin (if a screen ID is specified) or relative to the | ||
1356 | * virtual coordinate system's origin (if the screen ID is | ||
1357 | * SVGA_ID_INVALID). The actual destination may span zero or more | ||
1358 | * screens, in the case of a virtual destination rect or a rect | ||
1359 | * which extends off the edge of the specified screen. | ||
1360 | * | ||
1361 | * This command writes to the screen's "base layer": the underlying | ||
1362 | * framebuffer which exists below any cursor or video overlays. No | ||
1363 | * action is necessary to explicitly hide or update any overlays | ||
1364 | * which exist on top of the updated region. | ||
1365 | * | ||
1366 | * The SVGA device is guaranteed to finish reading from the GMRFB | ||
1367 | * by the time any subsequent FENCE commands are reached. | ||
1368 | * | ||
1369 | * This command consumes an annotation. See the | ||
1370 | * SVGA_CMD_ANNOTATION_* commands for details. | ||
1371 | * | ||
1372 | * Availability: | ||
1373 | * SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2 | ||
1374 | */ | ||
1375 | |||
1376 | typedef | ||
1377 | struct { | ||
1378 | SVGASignedPoint srcOrigin; | ||
1379 | SVGASignedRect destRect; | ||
1380 | uint32 destScreenId; | ||
1381 | } SVGAFifoCmdBlitGMRFBToScreen; | ||
1382 | |||
1383 | |||
1384 | /* | ||
1385 | * SVGA_CMD_BLIT_SCREEN_TO_GMRFB -- | ||
1386 | * | ||
1387 | * This is a host-to-guest blit. It performs a DMA operation to | ||
1388 | * copy a rectangular region of pixels from a single Screen Object | ||
1389 | * back to the current GMRFB. | ||
1390 | * | ||
1391 | * Usage note: This command should be used rarely. It will | ||
1392 | * typically be inefficient, but it is necessary for some types of | ||
1393 | * synchronization between 3D (GPU) and 2D (CPU) rendering into | ||
1394 | * overlapping areas of a screen. | ||
1395 | * | ||
1396 | * The source coordinate is specified relative to a screen's | ||
1397 | * origin. The provided screen ID must be valid. If any parameters | ||
1398 | * are invalid, the resulting pixel values are undefined. | ||
1399 | * | ||
1400 | * This command reads the screen's "base layer". Overlays like | ||
1401 | * video and cursor are not included, but any data which was sent | ||
1402 | * using a blit-to-screen primitive will be available, no matter | ||
1403 | * whether the data's original source was the GMRFB or the 3D | ||
1404 | * acceleration hardware. | ||
1405 | * | ||
1406 | * Note that our guest-to-host blits and host-to-guest blits aren't | ||
1407 | * symmetric in their current implementation. While the parameters | ||
1408 | * are identical, host-to-guest blits are a lot less featureful. | ||
1409 | * They do not support clipping: If the source parameters don't | ||
1410 | * fully fit within a screen, the blit fails. They must originate | ||
1411 | * from exactly one screen. Virtual coordinates are not directly | ||
1412 | * supported. | ||
1413 | * | ||
1414 | * Host-to-guest blits do support the same set of GMRFB formats | ||
1415 | * offered by guest-to-host blits. | ||
1416 | * | ||
1417 | * The SVGA device is guaranteed to finish writing to the GMRFB by | ||
1418 | * the time any subsequent FENCE commands are reached. | ||
1419 | * | ||
1420 | * Availability: | ||
1421 | * SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2 | ||
1422 | */ | ||
1423 | |||
1424 | typedef | ||
1425 | struct { | ||
1426 | SVGASignedPoint destOrigin; | ||
1427 | SVGASignedRect srcRect; | ||
1428 | uint32 srcScreenId; | ||
1429 | } SVGAFifoCmdBlitScreenToGMRFB; | ||
1430 | |||
1431 | |||
1432 | /* | ||
1433 | * SVGA_CMD_ANNOTATION_FILL -- | ||
1434 | * | ||
1435 | * This is a blit annotation. This command stores a small piece of | ||
1436 | * device state which is consumed by the next blit-to-screen | ||
1437 | * command. The state is only cleared by commands which are | ||
1438 | * specifically documented as consuming an annotation. Other | ||
1439 | * commands (such as ESCAPEs for debugging) may intervene between | ||
1440 | * the annotation and its associated blit. | ||
1441 | * | ||
1442 | * This annotation is a promise about the contents of the next | ||
1443 | * blit: The video driver is guaranteeing that all pixels in that | ||
1444 | * blit will have the same value, specified here as a color in | ||
1445 | * SVGAColorBGRX format. | ||
1446 | * | ||
1447 | * The SVGA device can still render the blit correctly even if it | ||
1448 | * ignores this annotation, but the annotation may allow it to | ||
1449 | * perform the blit more efficiently, for example by ignoring the | ||
1450 | * source data and performing a fill in hardware. | ||
1451 | * | ||
1452 | * This annotation is most important for performance when the | ||
1453 | * user's display is being remoted over a network connection. | ||
1454 | * | ||
1455 | * Availability: | ||
1456 | * SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2 | ||
1457 | */ | ||
1458 | |||
1459 | typedef | ||
1460 | struct { | ||
1461 | SVGAColorBGRX color; | ||
1462 | } SVGAFifoCmdAnnotationFill; | ||
1463 | |||
1464 | |||
1465 | /* | ||
1466 | * SVGA_CMD_ANNOTATION_COPY -- | ||
1467 | * | ||
1468 | * This is a blit annotation. See SVGA_CMD_ANNOTATION_FILL for more | ||
1469 | * information about annotations. | ||
1470 | * | ||
1471 | * This annotation is a promise about the contents of the next | ||
1472 | * blit: The video driver is guaranteeing that all pixels in that | ||
1473 | * blit will have the same value as those which already exist at an | ||
1474 | * identically-sized region on the same or a different screen. | ||
1475 | * | ||
1476 | * Note that the source pixels for the COPY in this annotation are | ||
1477 | * sampled before applying the anqnotation's associated blit. They | ||
1478 | * are allowed to overlap with the blit's destination pixels. | ||
1479 | * | ||
1480 | * The copy source rectangle is specified the same way as the blit | ||
1481 | * destination: it can be a rectangle which spans zero or more | ||
1482 | * screens, specified relative to either a screen or to the virtual | ||
1483 | * coordinate system's origin. If the source rectangle includes | ||
1484 | * pixels which are not from exactly one screen, the results are | ||
1485 | * undefined. | ||
1486 | * | ||
1487 | * Availability: | ||
1488 | * SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2 | ||
1489 | */ | ||
1490 | |||
1491 | typedef | ||
1492 | struct { | ||
1493 | SVGASignedPoint srcOrigin; | ||
1494 | uint32 srcScreenId; | ||
1495 | } SVGAFifoCmdAnnotationCopy; | ||
1496 | |||
1497 | |||
1498 | /* | ||
1499 | * SVGA_CMD_DEFINE_GMR2 -- | ||
1500 | * | ||
1501 | * Define guest memory region v2. See the description of GMRs above. | ||
1502 | * | ||
1503 | * Availability: | ||
1504 | * SVGA_CAP_GMR2 | ||
1505 | */ | ||
1506 | |||
1507 | typedef | ||
1508 | struct { | ||
1509 | uint32 gmrId; | ||
1510 | uint32 numPages; | ||
1511 | } SVGAFifoCmdDefineGMR2; | ||
1512 | |||
1513 | |||
1514 | /* | ||
1515 | * SVGA_CMD_REMAP_GMR2 -- | ||
1516 | * | ||
1517 | * Remap guest memory region v2. See the description of GMRs above. | ||
1518 | * | ||
1519 | * This command allows guest to modify a portion of an existing GMR by | ||
1520 | * invalidating it or reassigning it to different guest physical pages. | ||
1521 | * The pages are identified by physical page number (PPN). The pages | ||
1522 | * are assumed to be pinned and valid for DMA operations. | ||
1523 | * | ||
1524 | * Description of command flags: | ||
1525 | * | ||
1526 | * SVGA_REMAP_GMR2_VIA_GMR: If enabled, references a PPN list in a GMR. | ||
1527 | * The PPN list must not overlap with the remap region (this can be | ||
1528 | * handled trivially by referencing a separate GMR). If flag is | ||
1529 | * disabled, PPN list is appended to SVGARemapGMR command. | ||
1530 | * | ||
1531 | * SVGA_REMAP_GMR2_PPN64: If set, PPN list is in PPN64 format, otherwise | ||
1532 | * it is in PPN32 format. | ||
1533 | * | ||
1534 | * SVGA_REMAP_GMR2_SINGLE_PPN: If set, PPN list contains a single entry. | ||
1535 | * A single PPN can be used to invalidate a portion of a GMR or | ||
1536 | * map it to to a single guest scratch page. | ||
1537 | * | ||
1538 | * Availability: | ||
1539 | * SVGA_CAP_GMR2 | ||
1540 | */ | ||
1541 | |||
1542 | typedef enum { | ||
1543 | SVGA_REMAP_GMR2_PPN32 = 0, | ||
1544 | SVGA_REMAP_GMR2_VIA_GMR = (1 << 0), | ||
1545 | SVGA_REMAP_GMR2_PPN64 = (1 << 1), | ||
1546 | SVGA_REMAP_GMR2_SINGLE_PPN = (1 << 2), | ||
1547 | } SVGARemapGMR2Flags; | ||
1548 | |||
1549 | typedef | ||
1550 | struct { | ||
1551 | uint32 gmrId; | ||
1552 | SVGARemapGMR2Flags flags; | ||
1553 | uint32 offsetPages; /* offset in pages to begin remap */ | ||
1554 | uint32 numPages; /* number of pages to remap */ | ||
1555 | /* | ||
1556 | * Followed by additional data depending on SVGARemapGMR2Flags. | ||
1557 | * | ||
1558 | * If flag SVGA_REMAP_GMR2_VIA_GMR is set, single SVGAGuestPtr follows. | ||
1559 | * Otherwise an array of page descriptors in PPN32 or PPN64 format | ||
1560 | * (according to flag SVGA_REMAP_GMR2_PPN64) follows. If flag | ||
1561 | * SVGA_REMAP_GMR2_SINGLE_PPN is set, array contains a single entry. | ||
1562 | */ | ||
1563 | } SVGAFifoCmdRemapGMR2; | ||
865 | 1564 | ||
866 | #endif | 1565 | #endif |