AgeCommit message (Expand)AuthorFilesLines
2013-12-11sna: Enable scanline waits for BroadwellChris Wilson1-1/+1
2013-11-07sna/gen7: Request secure batches for Haswell vsyncChris Wilson1-0/+1
2013-09-20uxa: Do not change DPMS mode on unconnected outputsChris Wilson1-4/+7
2013-09-19sna: Do not change DPMS mode on unconnected outputsChris Wilson3-34/+90
2013-09-09sna/hsw: Scanline waits require both DERRMR and forcewakeChris Wilson1-6/+30
2013-07-30sna/gen7: Set appropriate constants for Haswell GT3Chris Wilson1-10/+30
2013-07-28intel: Replace the codename in the user facing string for unknown Haswell partsChris Wilson1-22/+22
2013-07-02sna: Include connector status in the initial probeChris Wilson1-13/+12
2013-06-13sna/gen7: Set sampler swizzle for video sourcesChris Wilson1-20/+28
2013-06-05Add more correct names for Haswell.Rodrigo Vivi1-14/+14
2013-05-29sna: fixup up possible_clones kms->X impedance mismatchDaniel Vetter1-22/+36
2013-05-28Add the known marketing names for the performance Haswell partsChris Wilson1-10/+10
2013-05-14Adding more reserved PCI IDs for Haswell.Rodrigo Vivi2-24/+73
2013-05-14Fix Haswell GT3 names.Rodrigo Vivi2-44/+44
2013-04-27Add all reserved PCI-IDs for HaswellChris Wilson2-0/+29
2013-03-28sna/gen7: Refine is_gt2() for Haswell versus IvybridgeChris Wilson1-1/+1
2013-03-27sna/gen7: Fix MOCS for HaswellChris Wilson2-5/+10
2013-03-19sna: Haswell reintroduces MI_LOAD_SCAN_LINESChris Wilson1-5/+41
2013-03-01Fix Haswell CRW PCI-IDsChris Wilson1-9/+9
2013-01-29sna: Add GT1/GT2 thread counts for HaswellChris Wilson1-0/+23
2012-10-23sna: Only disallow hw sprite scaling on HaswellChris Wilson1-2/+9
2012-10-12Fix possible_clones computation for shared encoders between outputsPaulo Zanoni2-1/+88
2012-08-07Add Haswell PCI IDsPaulo Zanoni2-0/+110
2012-08-03sna/gen7: Add constant variations and hookup a basic GT descriptor for HaswellChris Wilson2-8/+37
2012-08-03uxa: fix 3DSTATE_PS to fill in number of samples for HaswellGwenole Beauchesne3-2/+7
2012-08-03uxa: set "Shader Channel Select" fields in surface state for HaswellGwenole Beauchesne4-1/+34
2012-08-03uxa: fix max PS threads shift value for HaswellGwenole Beauchesne3-3/+14
2012-08-03uxa: use at least 64 URB entries for HaswellGwenole Beauchesne1-1/+6
2012-08-03uxa: add IS_HSW() macro to distinguish Haswell from IvybridgeGwenole Beauchesne1-0/+1
2012-08-03Introduce a chipset identifier for Haswell (Ivybridge successor)Gwenole Beauchesne1-0/+4