diff options
| author | Chris Wilson <chris@chris-wilson.co.uk> | 2012-03-30 10:21:26 +0100 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2012-03-30 10:21:26 +0100 |
| commit | 451489b49916cf5a9d27844196f9656e590d9124 (patch) | |
| tree | 83bbd89664ba6775fa2210c87040ecfa9cb2c9c6 | |
| parent | ea36f2c4a3fa9afa8184eeaf944af9924c080368 (diff) | |
sna/gen7: Allow per-device specific maxima
As the maximum thread count and urb size differs between different
incarnations of the GT units, be a little more flexible in programming
those maximums.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| -rw-r--r-- | src/sna/gen7_render.c | 33 | ||||
| -rw-r--r-- | src/sna/sna.h | 1 | ||||
| -rw-r--r-- | src/sna/sna_render.h | 1 |
3 files changed, 32 insertions, 3 deletions
diff --git a/src/sna/gen7_render.c b/src/sna/gen7_render.c index 14911673..6917c21e 100644 --- a/src/sna/gen7_render.c +++ b/src/sna/gen7_render.c @@ -67,6 +67,31 @@ #define is_aligned(x, y) (((x) & ((y) - 1)) == 0) +struct gt_info { + int max_vs_threads; + int max_gs_threads; + int max_wm_threads; + struct { + int size; + int max_vs_entries; + int max_gs_entries; + } urb; +}; + +static const struct gt_info gt1_info = { + .max_vs_threads = 36, + .max_gs_threads = 36, + .max_wm_threads = 86, + .urb = { 128, 512, 192 }, +}; + +static const struct gt_info gt2_info = { + .max_vs_threads = 128, + .max_gs_threads = 128, + .max_wm_threads = 86, + .urb = { 256, 704, 320 }, +}; + static const uint32_t ps_kernel_nomask_affine[][4] = { #include "exa_wm_src_affine.g7b" #include "exa_wm_src_sample_argb.g7b" @@ -427,7 +452,7 @@ gen7_emit_urb(struct sna *sna) /* num of VS entries must be divisible by 8 if size < 9 */ OUT_BATCH(GEN7_3DSTATE_URB_VS | (2 - 2)); - OUT_BATCH((32 << GEN7_URB_ENTRY_NUMBER_SHIFT) | /* at least 32 */ + OUT_BATCH((sna->render_state.gen7.info->urb.max_vs_entries << GEN7_URB_ENTRY_NUMBER_SHIFT) | (2 - 1) << GEN7_URB_ENTRY_SIZE_SHIFT | (1 << GEN7_URB_STARTING_ADDRESS_SHIFT)); @@ -802,7 +827,7 @@ gen7_emit_wm(struct sna *sna, unsigned int kernel, int nr_surfaces, int nr_input OUT_BATCH(1 << GEN7_PS_SAMPLER_COUNT_SHIFT | nr_surfaces << GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT); OUT_BATCH(0); /* scratch address */ - OUT_BATCH((86 - 1) << GEN7_PS_MAX_THREADS_SHIFT | + OUT_BATCH((sna->render_state.gen7.info->max_wm_threads - 1) << GEN7_PS_MAX_THREADS_SHIFT | GEN7_PS_ATTRIBUTE_ENABLE | GEN7_PS_16_DISPATCH_ENABLE); OUT_BATCH(6 << GEN7_PS_DISPATCH_START_GRF_SHIFT_0); @@ -4292,6 +4317,10 @@ static Bool gen7_render_setup(struct sna *sna) struct gen7_sampler_state *ss; int i, j, k, l, m; + state->info = >1_info; + if (DEVICE_ID(sna->PciInfo) & 0x20) + state->info = >2_info; + sna_static_stream_init(&general); /* Zero pad the start. If you see an offset of 0x0 in the batchbuffer diff --git a/src/sna/sna.h b/src/sna/sna.h index 8ad8efc4..7a1e2f63 100644 --- a/src/sna/sna.h +++ b/src/sna/sna.h @@ -257,7 +257,6 @@ struct sna { #define SNA_TILING_3D 0x4 #define SNA_TILING_ALL (~0) - int Chipset; EntityInfoPtr pEnt; struct pci_device *PciInfo; struct intel_chipset chipset; diff --git a/src/sna/sna_render.h b/src/sna/sna_render.h index a83f78ed..73ef5680 100644 --- a/src/sna/sna_render.h +++ b/src/sna/sna_render.h @@ -428,6 +428,7 @@ enum { }; struct gen7_render_state { + const struct gt_info *info; struct kgem_bo *general_bo; uint32_t vs_state; |