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authorZhenyu Wang <zhenyuw@linux.intel.com>2009-06-05 12:56:04 +0800
committerZhenyu Wang <zhenyuw@linux.intel.com>2009-06-10 10:37:01 +0800
commit440ccc44f51d3a5d6f46c28cfcc576cad155fbbc (patch)
tree9b807c6c73c57405f712cd0fb02a6c124cb184f8
parent0d8a9e2c6f58115b9b8449de52e795699ed032af (diff)
Add new register definitions
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
-rw-r--r--src/i810_reg.h492
1 files changed, 489 insertions, 3 deletions
diff --git a/src/i810_reg.h b/src/i810_reg.h
index db542aa3..ae1933d3 100644
--- a/src/i810_reg.h
+++ b/src/i810_reg.h
@@ -982,13 +982,18 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
982# define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 982# define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
983# define DPLL_FPA01_P1_POST_DIV_SHIFT 16 983# define DPLL_FPA01_P1_POST_DIV_SHIFT 16
984# define DPLL_FPA01_P1_POST_DIV_SHIFT_IGD 15 984# define DPLL_FPA01_P1_POST_DIV_SHIFT_IGD 15
985/* IGDNG */
986# define DPLL_FPA0_P1_POST_DIV_SHIFT 16
987
985# define PLL_P2_DIVIDE_BY_4 (1 << 23) /* i830, required in DVO non-gang */ 988# define PLL_P2_DIVIDE_BY_4 (1 << 23) /* i830, required in DVO non-gang */
986# define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ 989# define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
987# define PLL_REF_INPUT_DREFCLK (0 << 13) 990# define PLL_REF_INPUT_DREFCLK (0 << 13)
988# define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ 991# define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
992# define PLL_REF_INPUT_SUPER_SSC (1 << 13) /* IGDNG: 120M SSC */
989# define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ 993# define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
990# define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) 994# define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
991# define PLL_REF_INPUT_MASK (3 << 13) 995# define PLL_REF_INPUT_MASK (3 << 13)
996# define PLL_REF_INPUT_DMICLK (5 << 13) /* IGDNG: DMI refclk */
992# define PLL_LOAD_PULSE_PHASE_SHIFT 9 997# define PLL_LOAD_PULSE_PHASE_SHIFT 9
993/* 998/*
994 * Parallel to Serial Load Pulse phase selection. 999 * Parallel to Serial Load Pulse phase selection.
@@ -998,6 +1003,12 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
998 */ 1003 */
999# define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) 1004# define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
1000# define DISPLAY_RATE_SELECT_FPA1 (1 << 8) 1005# define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
1006/* IGDNG */
1007# define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
1008# define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
1009# define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1)<< PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT)
1010# define DPLL_FPA1_P1_POST_DIV_SHIFT 0
1011# define DPLL_FPA1_P1_POST_DIV_MASK 0xff
1001 1012
1002/** 1013/**
1003 * SDVO multiplier for 945G/GM. Not used on 965. 1014 * SDVO multiplier for 945G/GM. Not used on 965.
@@ -2146,10 +2157,33 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
2146#define PIPEACONF_PIPE_LOCKED (1<<25) 2157#define PIPEACONF_PIPE_LOCKED (1<<25)
2147#define PIPEACONF_PALETTE 0 2158#define PIPEACONF_PALETTE 0
2148#define PIPEACONF_GAMMA (1<<24) 2159#define PIPEACONF_GAMMA (1<<24)
2160/* IGDNG: gamma */
2161#define PIPECONF_PALETTE_8BIT (0<<24)
2162#define PIPECONF_PALETTE_10BIT (1<<24)
2163#define PIPECONF_PALETTE_12BIT (2<<24)
2149#define PIPECONF_FORCE_BORDER (1<<25) 2164#define PIPECONF_FORCE_BORDER (1<<25)
2150#define PIPECONF_PROGRESSIVE (0 << 21) 2165#define PIPECONF_PROGRESSIVE (0 << 21)
2151#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) 2166#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
2152#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) 2167#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21)
2168/* IGDNG */
2169#define PIPECONF_MSA_TIMING_DELAY (0<<18) /* for eDP */
2170#define PIPECONF_NO_DYNAMIC_RATE_CHANGE (0 << 16)
2171#define PIPECONF_NO_ROTATION (0<<14)
2172#define PIPECONF_FULL_COLOR_RANGE (0<<13)
2173#define PIPECONF_CE_COLOR_RANGE (1<<13)
2174#define PIPECONF_COLOR_SPACE_RGB (0<<11)
2175#define PIPECONF_COLOR_SPACE_YUV601 (1<<11)
2176#define PIPECONF_COLOR_SPACE_YUV709 (2<<11)
2177#define PIPECONF_CONNECT_DEFAULT (0<<9)
2178#define PIPECONF_8BPP (0<<5)
2179#define PIPECONF_10BPP (1<<5)
2180#define PIPECONF_6BPP (2<<5)
2181#define PIPECONF_12BPP (3<<5)
2182#define PIPECONF_ENABLE_DITHER (1<<4)
2183#define PIPECONF_DITHER_SPATIAL (0<<2)
2184#define PIPECONF_DITHER_ST1 (1<<2)
2185#define PIPECONF_DITHER_ST2 (2<<2)
2186#define PIPECONF_DITHER_TEMPORAL (3<<2)
2153 2187
2154#define PIPEAGCMAXRED 0x70010 2188#define PIPEAGCMAXRED 0x70010
2155#define PIPEAGCMAXGREEN 0x70014 2189#define PIPEAGCMAXGREEN 0x70014
@@ -2285,13 +2319,23 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
2285#define DISPPLANE_8BPP (0x2<<26) 2319#define DISPPLANE_8BPP (0x2<<26)
2286#define DISPPLANE_15_16BPP (0x4<<26) 2320#define DISPPLANE_15_16BPP (0x4<<26)
2287#define DISPPLANE_16BPP (0x5<<26) 2321#define DISPPLANE_16BPP (0x5<<26)
2288#define DISPPLANE_32BPP_NO_ALPHA (0x6<<26) 2322#define DISPPLANE_32BPP_NO_ALPHA (0x6<<26) /* IGDNG: BGRX */
2289#define DISPPLANE_32BPP (0x7<<26) 2323#define DISPPLANE_32BPP (0x7<<26) /* IGDNG: not support */
2324/* IGDNG */
2325#define DISPPLANE_32BPP_10 (0x8<<26) /* 2:10:10:10 */
2326#define DISPPLANE_32BPP_BGRX (0xa<<26)
2327#define DISPPLANE_64BPP (0xc<<26)
2328#define DISPPLANE_32BPP_RGBX (0xe<<26)
2290#define DISPPLANE_STEREO_ENABLE (1<<25) 2329#define DISPPLANE_STEREO_ENABLE (1<<25)
2291#define DISPPLANE_STEREO_DISABLE 0 2330#define DISPPLANE_STEREO_DISABLE 0
2292#define DISPPLANE_SEL_PIPE_MASK (1<<24) 2331#define DISPPLANE_SEL_PIPE_MASK (1<<24)
2293#define DISPPLANE_SEL_PIPE_A 0 2332#define DISPPLANE_SEL_PIPE_A 0 /* IGDNG: don't use */
2294#define DISPPLANE_SEL_PIPE_B (1<<24) 2333#define DISPPLANE_SEL_PIPE_B (1<<24)
2334#define DISPPLANE_NORMAL_RANGE (0<<25)
2335#define DISPPLANE_EXT_RANGE (1<<25)
2336/* IGDNG */
2337#define DISPPLANE_CSC_BYPASS (0<<24)
2338#define DISPPLANE_CSC_PASSTHROUGH (1<<24)
2295#define DISPPLANE_SRC_KEY_ENABLE (1<<22) 2339#define DISPPLANE_SRC_KEY_ENABLE (1<<22)
2296#define DISPPLANE_SRC_KEY_DISABLE 0 2340#define DISPPLANE_SRC_KEY_DISABLE 0
2297#define DISPPLANE_LINE_DOUBLE (1<<20) 2341#define DISPPLANE_LINE_DOUBLE (1<<20)
@@ -2303,11 +2347,18 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
2303#define DISPPLANE_ALPHA_TRANS_DISABLE 0 2347#define DISPPLANE_ALPHA_TRANS_DISABLE 0
2304#define DISPPLANE_SPRITE_ABOVE_DISPLAYA 0 2348#define DISPPLANE_SPRITE_ABOVE_DISPLAYA 0
2305#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) 2349#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
2350/* IGDNG */
2351#define DISPPLANE_X_TILE (1<<10)
2352#define DISPPLANE_LINEAR (0<<10)
2306 2353
2307#define DSPABASE 0x70184 2354#define DSPABASE 0x70184
2355/* IGDNG */
2356#define DSPALINOFF 0x70184
2308#define DSPASTRIDE 0x70188 2357#define DSPASTRIDE 0x70188
2309 2358
2310#define DSPBBASE 0x71184 2359#define DSPBBASE 0x71184
2360/* IGDNG */
2361#define DSPBLINOFF 0x71184
2311#define DSPBADDR DSPBBASE 2362#define DSPBADDR DSPBBASE
2312#define DSPBSTRIDE 0x71188 2363#define DSPBSTRIDE 0x71188
2313 2364
@@ -2919,4 +2970,439 @@ typedef enum {
2919#define MCHBAR_RENDER_STANDBY 0x111B8 2970#define MCHBAR_RENDER_STANDBY 0x111B8
2920#define RENDER_STANDBY_ENABLE (1 << 30) 2971#define RENDER_STANDBY_ENABLE (1 << 30)
2921 2972
2973/* IGDNG */
2974
2975/* warmup time in us */
2976#define WARMUP_PCH_REF_CLK_SSC_MOD 1
2977#define WARMUP_PCH_FDI_RECEIVER_PLL 25
2978#define WARMUP_PCH_DPLL 50
2979#define WARMUP_CPU_DP_PLL 20
2980#define WARMUP_CPU_FDI_TRANSMITTER_PLL 10
2981#define WARMUP_DMI_LATENCY 20
2982#define FDI_TRAIN_PATTERN_1_TIME 0.5
2983#define FDI_TRAIN_PATTERN_2_TIME 1.5
2984#define FDI_ONE_IDLE_PATTERN_TIME 31
2985
2986#define CPU_VGACNTRL 0x41000
2987
2988#define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030
2989#define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
2990#define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2)
2991#define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2)
2992#define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2)
2993#define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2)
2994#define DIGITAL_PORTA_NO_DETECT (0 << 0)
2995#define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1)
2996#define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0)
2997
2998/* refresh rate hardware control */
2999#define RR_HW_CTL 0x45300
3000#define RR_HW_LOW_POWER_FRAMES_MASK 0xff
3001#define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
3002
3003#define FDI_PLL_BIOS_0 0x46000
3004#define FDI_PLL_BIOS_1 0x46004
3005#define FDI_PLL_BIOS_2 0x46008
3006#define DISPLAY_PORT_PLL_BIOS_0 0x4600c
3007#define DISPLAY_PORT_PLL_BIOS_1 0x46010
3008#define DISPLAY_PORT_PLL_BIOS_2 0x46014
3009
3010#define FDI_PLL_FREQ_CTL 0x46030
3011#define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24)
3012#define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00
3013#define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
3014
3015#define PIPEA_DATA_M1 0x60030
3016#define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */
3017#define TU_SIZE_MASK 0x7e000000
3018#define PIPEA_DATA_M1_OFFSET 0
3019#define PIPEA_DATA_N1 0x60034
3020#define PIPEA_DATA_N1_OFFSET 0
3021
3022#define PIPEA_DATA_M2 0x60038
3023#define PIPEA_DATA_M2_OFFSET 0
3024#define PIPEA_DATA_N2 0x6003c
3025#define PIPEA_DATA_N2_OFFSET 0
3026
3027#define PIPEA_LINK_M1 0x60040
3028#define PIPEA_LINK_M1_OFFSET 0
3029#define PIPEA_LINK_N1 0x60044
3030#define PIPEA_LINK_N1_OFFSET 0
3031
3032#define PIPEA_LINK_M2 0x60048
3033#define PIPEA_LINK_M2_OFFSET 0
3034#define PIPEA_LINK_N2 0x6004c
3035#define PIPEA_LINK_N2_OFFSET 0
3036
3037/* PIPEB timing regs are same start from 0x61000 */
3038
3039#define PIPEB_DATA_M1 0x61030
3040#define PIPEB_DATA_M1_OFFSET 0
3041#define PIPEB_DATA_N1 0x61034
3042#define PIPEB_DATA_N1_OFFSET 0
3043
3044#define PIPEB_DATA_M2 0x61038
3045#define PIPEB_DATA_M2_OFFSET 0
3046#define PIPEB_DATA_N2 0x6103c
3047#define PIPEB_DATA_N2_OFFSET 0
3048
3049#define PIPEB_LINK_M1 0x61040
3050#define PIPEB_LINK_M1_OFFSET 0
3051#define PIPEB_LINK_N1 0x61044
3052#define PIPEB_LINK_N1_OFFSET 0
3053
3054#define PIPEB_LINK_M2 0x61048
3055#define PIPEB_LINK_M2_OFFSET 0
3056#define PIPEB_LINK_N2 0x6104c
3057#define PIPEB_LINK_N2_OFFSET 0
3058
3059/* PIPECONF for pipe A/B addr is same */
3060
3061/* cusor A is only connected to pipe A,
3062 cursor B is connected to pipe B. Otherwise no change. */
3063
3064/* Plane A/B, DSPACNTR/DSPBCNTR addr not changed */
3065
3066/* CPU panel fitter */
3067#define PFA_CTL_1 0x68080
3068#define PFB_CTL_1 0x68880
3069#define PF_ENABLE (1<<31)
3070
3071/* CPU panel fitter */
3072#define PFA_CTRL_1 0x68080
3073#define PFB_CTRL_1 0x68880
3074
3075/* legacy palette */
3076#define LGC_PALETTE_A 0x4a000
3077#define LGC_PALETTE_B 0x4a800
3078
3079/* interrupts */
3080#define DE_MASTER_IRQ_CONTROL (1 << 31)
3081#define DE_SPRITEB_FLIP_DONE (1 << 29)
3082#define DE_SPRITEA_FLIP_DONE (1 << 28)
3083#define DE_PLANEB_FLIP_DONE (1 << 27)
3084#define DE_PLANEA_FLIP_DONE (1 << 26)
3085#define DE_PCU_EVENT (1 << 25)
3086#define DE_GTT_FAULT (1 << 24)
3087#define DE_POISON (1 << 23)
3088#define DE_PERFORM_COUNTER (1 << 22)
3089#define DE_PCH_EVENT (1 << 21)
3090#define DE_AUX_CHANNEL_A (1 << 20)
3091#define DE_DP_A_HOTPLUG (1 << 19)
3092#define DE_GSE (1 << 18)
3093#define DE_PIPEB_VBLANK (1 << 15)
3094#define DE_PIPEB_EVEN_FIELD (1 << 14)
3095#define DE_PIPEB_ODD_FIELD (1 << 13)
3096#define DE_PIPEB_LINE_COMPARE (1 << 12)
3097#define DE_PIPEB_VSYNC (1 << 11)
3098#define DE_PIPEB_FIFO_UNDERRUN (1 << 8)
3099#define DE_PIPEA_VBLANK (1 << 7)
3100#define DE_PIPEA_EVEN_FIELD (1 << 6)
3101#define DE_PIPEA_ODD_FIELD (1 << 5)
3102#define DE_PIPEA_LINE_COMPARE (1 << 4)
3103#define DE_PIPEA_VSYNC (1 << 3)
3104#define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
3105
3106#define DEISR 0x44000
3107#define DEIMR 0x44004
3108#define DEIIR 0x44008
3109#define DEIER 0x4400c
3110
3111/* GT interrupt */
3112#define GT_SYNC_STATUS (1 << 2)
3113#define GT_USER_INTERRUPT (1 << 0)
3114
3115#define GTISR 0x44010
3116#define GTIMR 0x44014
3117#define GTIIR 0x44018
3118#define GTIER 0x4401c
3119
3120/* PCH */
3121
3122/* south display engine interrupt */
3123#define SDE_CRT_HOTPLUG (1 << 11)
3124#define SDE_PORTD_HOTPLUG (1 << 10)
3125#define SDE_PORTC_HOTPLUG (1 << 9)
3126#define SDE_PORTB_HOTPLUG (1 << 8)
3127#define SDE_SDVOB_HOTPLUG (1 << 6)
3128
3129#define SDEISR 0xc4000
3130#define SDEIMR 0xc4004
3131#define SDEIIR 0xc4008
3132#define SDEIER 0xc400c
3133
3134/* digital port hotplug */
3135#define PCH_PORT_HOTPLUG 0xc4030
3136#define PORTD_HOTPLUG_ENABLE (1 << 20)
3137#define PORTD_PULSE_DURATION_2ms (0)
3138#define PORTD_PULSE_DURATION_4_5ms (1 << 18)
3139#define PORTD_PULSE_DURATION_6ms (2 << 18)
3140#define PORTD_PULSE_DURATION_100ms (3 << 18)
3141#define PORTD_HOTPLUG_NO_DETECT (0)
3142#define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
3143#define PORTD_HOTPLUG_LONG_DETECT (1 << 17)
3144#define PORTC_HOTPLUG_ENABLE (1 << 12)
3145#define PORTC_PULSE_DURATION_2ms (0)
3146#define PORTC_PULSE_DURATION_4_5ms (1 << 10)
3147#define PORTC_PULSE_DURATION_6ms (2 << 10)
3148#define PORTC_PULSE_DURATION_100ms (3 << 10)
3149#define PORTC_HOTPLUG_NO_DETECT (0)
3150#define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
3151#define PORTC_HOTPLUG_LONG_DETECT (1 << 9)
3152#define PORTB_HOTPLUG_ENABLE (1 << 4)
3153#define PORTB_PULSE_DURATION_2ms (0)
3154#define PORTB_PULSE_DURATION_4_5ms (1 << 2)
3155#define PORTB_PULSE_DURATION_6ms (2 << 2)
3156#define PORTB_PULSE_DURATION_100ms (3 << 2)
3157#define PORTB_HOTPLUG_NO_DETECT (0)
3158#define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
3159#define PORTB_HOTPLUG_LONG_DETECT (1 << 1)
3160
3161#define PCH_GPIOA 0xc5010
3162#define PCH_GPIOB 0xc5014
3163#define PCH_GPIOC 0xc5018
3164#define PCH_GPIOD 0xc501c
3165#define PCH_GPIOE 0xc5020
3166#define PCH_GPIOF 0xc5024
3167#define PCH_GMBUS0 0xc5100
3168#define PCH_GMBUS1 0xc5104
3169#define PCH_GMBUS2 0xc5108
3170#define PCH_GMBUS3 0xc510c
3171#define PCH_GMBUS4 0xc5110
3172#define PCH_GMBUS5 0xc5120
3173
3174#define PCH_DPLL_A 0xc6014
3175#define PCH_DPLL_B 0xc6018
3176
3177#define PCH_FPA0 0xc6040
3178#define PCH_FPA1 0xc6044
3179#define PCH_FPB0 0xc6048
3180#define PCH_FPB1 0xc604c
3181
3182#define PCH_DPLL_TEST 0xc606c
3183
3184#define PCH_DREF_CONTROL 0xC6200
3185#define DREF_CONTROL_MASK 0x7fc3
3186#define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13)
3187#define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13)
3188#define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13)
3189#define DREF_SSC_SOURCE_DISABLE (0<<11)
3190#define DREF_SSC_SOURCE_ENABLE (2<<11)
3191#define DREF_NONSPREAD_SOURCE_DISABLE (0<<9)
3192#define DREF_NONSPREAD_SOURCE_ENABLE (2<<9)
3193#define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7)
3194#define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7)
3195#define DREF_SSC4_DOWNSPREAD (0<<6)
3196#define DREF_SSC4_CENTERSPREAD (1<<6)
3197#define DREF_SSC1_DISABLE (0<<1)
3198#define DREF_SSC1_ENABLE (1<<1)
3199#define DREF_SSC4_DISABLE (0)
3200#define DREF_SSC4_ENABLE (1)
3201
3202#define PCH_RAWCLK_FREQ 0xc6204
3203#define FDL_TP1_TIMER_SHIFT 12
3204#define FDL_TP1_TIMER_MASK (3<<12)
3205#define FDL_TP2_TIMER_SHIFT 10
3206#define FDL_TP2_TIMER_MASK (3<<10)
3207#define RAWCLK_FREQ_MASK 0x3ff
3208
3209#define PCH_DPLL_TMR_CFG 0xc6208
3210
3211#define PCH_SSC4_PARMS 0xc6210
3212#define PCH_SSC4_AUX_PARMS 0xc6214
3213
3214/* transcoder */
3215
3216#define TRANS_HTOTAL_A 0xe0000
3217#define TRANS_HTOTAL_SHIFT 16
3218#define TRANS_HACTIVE_SHIFT 0
3219#define TRANS_HBLANK_A 0xe0004
3220#define TRANS_HBLANK_END_SHIFT 16
3221#define TRANS_HBLANK_START_SHIFT 0
3222#define TRANS_HSYNC_A 0xe0008
3223#define TRANS_HSYNC_END_SHIFT 16
3224#define TRANS_HSYNC_START_SHIFT 0
3225#define TRANS_VTOTAL_A 0xe000c
3226#define TRANS_VTOTAL_SHIFT 16
3227#define TRANS_VACTIVE_SHIFT 0
3228#define TRANS_VBLANK_A 0xe0010
3229#define TRANS_VBLANK_END_SHIFT 16
3230#define TRANS_VBLANK_START_SHIFT 0
3231#define TRANS_VSYNC_A 0xe0014
3232#define TRANS_VSYNC_END_SHIFT 16
3233#define TRANS_VSYNC_START_SHIFT 0
3234
3235#define TRANSA_DATA_M1 0xe0030
3236#define TRANSA_DATA_N1 0xe0034
3237#define TRANSA_DATA_M2 0xe0038
3238#define TRANSA_DATA_N2 0xe003c
3239#define TRANSA_DP_LINK_M1 0xe0040
3240#define TRANSA_DP_LINK_N1 0xe0044
3241#define TRANSA_DP_LINK_M2 0xe0048
3242#define TRANSA_DP_LINK_N2 0xe004c
3243
3244#define TRANS_HTOTAL_B 0xe1000
3245#define TRANS_HBLANK_B 0xe1004
3246#define TRANS_HSYNC_B 0xe1008
3247#define TRANS_VTOTAL_B 0xe100c
3248#define TRANS_VBLANK_B 0xe1010
3249#define TRANS_VSYNC_B 0xe1014
3250
3251#define TRANSB_DATA_M1 0xe1030
3252#define TRANSB_DATA_N1 0xe1034
3253#define TRANSB_DATA_M2 0xe1038
3254#define TRANSB_DATA_N2 0xe103c
3255#define TRANSB_DP_LINK_M1 0xe1040
3256#define TRANSB_DP_LINK_N1 0xe1044
3257#define TRANSB_DP_LINK_M2 0xe1048
3258#define TRANSB_DP_LINK_N2 0xe104c
3259
3260#define TRANSACONF 0xf0008
3261#define TRANSBCONF 0xf1008
3262#define TRANS_DISABLE (0<<31)
3263#define TRANS_ENABLE (1<<31)
3264#define TRANS_STATE_MASK (1<<30)
3265#define TRANS_STATE_DISABLE (0<<30)
3266#define TRANS_STATE_ENABLE (1<<30)
3267#define TRANS_FSYNC_DELAY_HB1 (0<<27)
3268#define TRANS_FSYNC_DELAY_HB2 (1<<27)
3269#define TRANS_FSYNC_DELAY_HB3 (2<<27)
3270#define TRANS_FSYNC_DELAY_HB4 (3<<27)
3271#define TRANS_DP_AUDIO_ONLY (1<<26)
3272#define TRANS_DP_VIDEO_AUDIO (0<<26)
3273#define TRANS_PROGRESSIVE (0<<21)
3274#define TRANS_8BPC (0<<5)
3275#define TRANS_10BPC (1<<5)
3276#define TRANS_6BPC (2<<5)
3277#define TRANS_12BPC (3<<5)
3278
3279#define FDI_RXA_CHICKEN 0xc200c
3280#define FDI_RXB_CHICKEN 0xc2010
3281#define FDI_RX_PHASE_SYNC_POINTER_ENABLE (1)
3282
3283/* CPU: FDI_TX */
3284#define FDI_TXA_CTL 0x60100
3285#define FDI_TXB_CTL 0x61100
3286#define FDI_TX_DISABLE (0<<31)
3287#define FDI_TX_ENABLE (1<<31)
3288#define FDI_LINK_TRAIN_PATTERN_1 (0<<28)
3289#define FDI_LINK_TRAIN_PATTERN_2 (1<<28)
3290#define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28)
3291#define FDI_LINK_TRAIN_NONE (3<<28)
3292#define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25)
3293#define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25)
3294#define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25)
3295#define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25)
3296#define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22)
3297#define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22)
3298#define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22)
3299#define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22)
3300#define FDI_DP_PORT_WIDTH_X1 (0<<19)
3301#define FDI_DP_PORT_WIDTH_X2 (1<<19)
3302#define FDI_DP_PORT_WIDTH_X3 (2<<19)
3303#define FDI_DP_PORT_WIDTH_X4 (3<<19)
3304#define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18)
3305/* IGDNG: hardwired to 1 */
3306#define FDI_TX_PLL_ENABLE (1<<14)
3307/* both Tx and Rx */
3308#define FDI_SCRAMBLING_ENABLE (0<<7)
3309#define FDI_SCRAMBLING_DISABLE (1<<7)
3310
3311/* FDI_RX, FDI_X is hard-wired to Transcoder_X */
3312#define FDI_RXA_CTL 0xf000c
3313#define FDI_RXB_CTL 0xf100c
3314#define FDI_RX_ENABLE (1<<31)
3315#define FDI_RX_DISABLE (0<<31)
3316/* train, dp width same as FDI_TX */
3317#define FDI_DP_PORT_WIDTH_X8 (7<<19)
3318#define FDI_8BPC (0<<16)
3319#define FDI_10BPC (1<<16)
3320#define FDI_6BPC (2<<16)
3321#define FDI_12BPC (3<<16)
3322#define FDI_LINK_REVERSE_OVERWRITE (1<<15)
3323#define FDI_DMI_LINK_REVERSE_MASK (1<<14)
3324#define FDI_RX_PLL_ENABLE (1<<13)
3325#define FDI_FS_ERR_CORRECT_ENABLE (1<<11)
3326#define FDI_FE_ERR_CORRECT_ENABLE (1<<10)
3327#define FDI_FS_ERR_REPORT_ENABLE (1<<9)
3328#define FDI_FE_ERR_REPORT_ENABLE (1<<8)
3329#define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6)
3330#define FDI_SEL_RAWCLK (0<<4)
3331#define FDI_SEL_PCDCLK (1<<4)
3332
3333#define FDI_RXA_MISC 0xf0010
3334#define FDI_RXB_MISC 0xf1010
3335#define FDI_RXA_TUSIZE1 0xf0030
3336#define FDI_RXA_TUSIZE2 0xf0038
3337#define FDI_RXB_TUSIZE1 0xf1030
3338#define FDI_RXB_TUSIZE2 0xf1038
3339
3340/* FDI_RX interrupt register format */
3341#define FDI_RX_INTER_LANE_ALIGN (1<<10)
3342#define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */
3343#define FDI_RX_BIT_LOCK (1<<8) /* train 1 */
3344#define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7)
3345#define FDI_RX_FS_CODE_ERR (1<<6)
3346#define FDI_RX_FE_CODE_ERR (1<<5)
3347#define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4)
3348#define FDI_RX_HDCP_LINK_FAIL (1<<3)
3349#define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2)
3350#define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1)
3351#define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0)
3352
3353#define FDI_RXA_IIR 0xf0014
3354#define FDI_RXA_IMR 0xf0018
3355#define FDI_RXB_IIR 0xf1014
3356#define FDI_RXB_IMR 0xf1018
3357
3358#define FDI_PLL_CTL_1 0xfe000
3359#define FDI_PLL_CTL_2 0xfe004
3360
3361/* CRT */
3362#define PCH_ADPA 0xe1100
3363#define ADPA_TRANS_SELECT_MASK (1<<30)
3364#define ADPA_TRANS_A_SELECT 0
3365#define ADPA_TRANS_B_SELECT (1<<30)
3366/* HPD is here */
3367#define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */
3368#define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24)
3369#define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24)
3370#define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24)
3371#define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24)
3372#define ADPA_CRT_HOTPLUG_ENABLE (1<<23)
3373#define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22)
3374#define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22)
3375#define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21)
3376#define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21)
3377#define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20)
3378#define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20)
3379#define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18)
3380#define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18)
3381#define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18)
3382#define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18)
3383#define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17)
3384#define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17)
3385#define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
3386/* polarity control not changed */
3387
3388/* or SDVOB */
3389#define HDMIB 0xe1140
3390#define PORT_ENABLE (1 << 31)
3391#define TRANSCODER_A (0)
3392#define TRANSCODER_B (1 << 30)
3393#define COLOR_FORMAT_8bpc (0)
3394#define COLOR_FORMAT_12bpc (3 << 26)
3395#define SDVOB_HOTPLUG_ENABLE (1 << 23)
3396#define SDVO_ENCODING (0)
3397#define TMDS_ENCODING (2 << 10)
3398#define NULL_PACKET_VSYNC_ENABLE (1 << 9)
3399#define SDVOB_BORDER_ENABLE (1 << 7)
3400#define AUDIO_ENABLE (1 << 6)
3401#define VSYNC_ACTIVE_HIGH (1 << 4)
3402#define HSYNC_ACTIVE_HIGH (1 << 3)
3403#define PORT_DETECTED (1 << 2)
3404
3405#define HDMIC 0xe1150
3406#define HDMID 0xe1160
3407
2922#endif /* _I810_REG_H */ 3408#endif /* _I810_REG_H */