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authorZhenyu Wang <zhenyuw@linux.intel.com>2009-08-18 10:01:12 +0800
committerZhenyu Wang <zhenyuw@linux.intel.com>2009-08-18 10:01:12 +0800
commit376397c21eb9a7e4ea79d349af41da81c1af861f (patch)
tree485165c8a3f118ca9a9c256abcfe72c67ef4086b
parent926c7e7d30458078f8185d4e0b9b32b40102b3d5 (diff)
Fix VGA plane disabling
Only apply on G4X with SR01 bit5 workaround for VGA plane disable, and restore behavior back for other chips to make sure other modes got disabled too. For bug #17235, #19715, #21064, #23178 Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
-rw-r--r--src/i830_display.c38
1 files changed, 20 insertions, 18 deletions
diff --git a/src/i830_display.c b/src/i830_display.c
index 59ededcf..f83e0212 100644
--- a/src/i830_display.c
+++ b/src/i830_display.c
@@ -1076,29 +1076,31 @@ i830_disable_vga_plane (xf86CrtcPtr crtc)
1076{ 1076{
1077 ScrnInfoPtr pScrn = crtc->scrn; 1077 ScrnInfoPtr pScrn = crtc->scrn;
1078 I830Ptr pI830 = I830PTR(pScrn); 1078 I830Ptr pI830 = I830PTR(pScrn);
1079 uint32_t vgacntrl = INREG(VGACNTRL);
1080 uint8_t sr01; 1079 uint8_t sr01;
1081 1080
1082 if (vgacntrl & VGA_DISP_DISABLE)
1083 return;
1084
1085 /* 1081 /*
1086 Set bit 5 of SR01; 1082 * Bug #17235: G4X machine needs following steps
1087 Wait 30us; 1083 * for disable VGA.
1088 */ 1084 * - set bit 5 of SR01;
1089 OUTREG8(SRX, 1); 1085 * - Wait 30us;
1090 sr01 = INREG8(SRX + 1); 1086 * - disable vga plane;
1091 OUTREG8(SRX + 1, sr01 | (1 << 5)); 1087 * - restore SR01;
1092 usleep(30); 1088 */
1093 /* disable center mode on 965GM and G4X platform */ 1089 if (IS_G4X(pI830)) {
1094 if (IS_I965GM(pI830) || IS_G4X(pI830)) 1090 OUTREG8(SRX, 1);
1095 vgacntrl &= ~(3 << 24); 1091 sr01 = INREG8(SRX + 1);
1096 1092 OUTREG8(SRX + 1, sr01 | (1 << 5));
1097 vgacntrl |= VGA_DISP_DISABLE; 1093 usleep(30);
1098 1094 }
1099 OUTREG(VGACNTRL, vgacntrl); 1095
1096 OUTREG(VGACNTRL, VGA_DISP_DISABLE);
1100 i830WaitForVblank(pScrn); 1097 i830WaitForVblank(pScrn);
1101 1098
1099 /* restore SR01 */
1100 if (IS_G4X(pI830)) {
1101 OUTREG8(SRX, 1);
1102 OUTREG8(SRX + 1, sr01);
1103 }
1102} 1104}
1103 1105
1104static void 1106static void