diff options
| author | Zhenyu Wang <zhenyuw@linux.intel.com> | 2009-08-18 10:01:12 +0800 |
|---|---|---|
| committer | Zhenyu Wang <zhenyuw@linux.intel.com> | 2009-08-18 10:01:12 +0800 |
| commit | 376397c21eb9a7e4ea79d349af41da81c1af861f (patch) | |
| tree | 485165c8a3f118ca9a9c256abcfe72c67ef4086b | |
| parent | 926c7e7d30458078f8185d4e0b9b32b40102b3d5 (diff) | |
Fix VGA plane disabling
Only apply on G4X with SR01 bit5 workaround for VGA plane disable, and
restore behavior back for other chips to make sure other modes got disabled
too.
For bug #17235, #19715, #21064, #23178
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
| -rw-r--r-- | src/i830_display.c | 38 |
1 files changed, 20 insertions, 18 deletions
diff --git a/src/i830_display.c b/src/i830_display.c index 59ededcf..f83e0212 100644 --- a/src/i830_display.c +++ b/src/i830_display.c @@ -1073,35 +1073,37 @@ static void i830_modeset_ctl(xf86CrtcPtr crtc, int dpms_state) static void i830_disable_vga_plane (xf86CrtcPtr crtc) { ScrnInfoPtr pScrn = crtc->scrn; I830Ptr pI830 = I830PTR(pScrn); - uint32_t vgacntrl = INREG(VGACNTRL); uint8_t sr01; - if (vgacntrl & VGA_DISP_DISABLE) - return; - /* - Set bit 5 of SR01; - Wait 30us; - */ - OUTREG8(SRX, 1); - sr01 = INREG8(SRX + 1); - OUTREG8(SRX + 1, sr01 | (1 << 5)); - usleep(30); - /* disable center mode on 965GM and G4X platform */ - if (IS_I965GM(pI830) || IS_G4X(pI830)) - vgacntrl &= ~(3 << 24); - - vgacntrl |= VGA_DISP_DISABLE; - - OUTREG(VGACNTRL, vgacntrl); + * Bug #17235: G4X machine needs following steps + * for disable VGA. + * - set bit 5 of SR01; + * - Wait 30us; + * - disable vga plane; + * - restore SR01; + */ + if (IS_G4X(pI830)) { + OUTREG8(SRX, 1); + sr01 = INREG8(SRX + 1); + OUTREG8(SRX + 1, sr01 | (1 << 5)); + usleep(30); + } + + OUTREG(VGACNTRL, VGA_DISP_DISABLE); i830WaitForVblank(pScrn); + /* restore SR01 */ + if (IS_G4X(pI830)) { + OUTREG8(SRX, 1); + OUTREG8(SRX + 1, sr01); + } } static void i830_crtc_enable(xf86CrtcPtr crtc) { ScrnInfoPtr pScrn = crtc->scrn; |